From f156e95bbda714fdf6424d6b8080e8bb6c486c9d Mon Sep 17 00:00:00 2001 From: Anas Nashif Date: Tue, 20 Aug 2019 06:37:49 -0700 Subject: [PATCH] ext: hal: make TI HAL a zephyr module Move TI HAL to a module repository: https://github.com/zephyrproject-rtos/hal_ti managed by west. Signed-off-by: Anas Nashif --- CODEOWNERS | 1 - drivers/wifi/simplelink/CMakeLists.txt | 3 - ext/hal/CMakeLists.txt | 1 - ext/hal/Kconfig | 2 - ext/hal/ti/CMakeLists.txt | 1 - ext/hal/ti/simplelink/CMakeLists.txt | 60 - ext/hal/ti/simplelink/README | 90 - .../kernel/zephyr/dpl/ClockP_zephyr.c | 20 - .../kernel/zephyr/dpl/HwiP_zephyr.c | 160 - .../kernel/zephyr/dpl/MutexP_zephyr.c | 95 - .../kernel/zephyr/dpl/SemaphoreP_zephyr.c | 140 - ext/hal/ti/simplelink/kernel/zephyr/dpl/dpl.c | 116 - ext/hal/ti/simplelink/kernel/zephyr/dpl/dpl.h | 9 - .../source/ti/devices/CMakeLists.txt | 3 - .../source/ti/devices/DeviceFamily.h | 198 - .../ti/devices/cc13x2_cc26x2/CMakeLists.txt | 16 - .../ti/devices/cc13x2_cc26x2/driverlib/adi.c | 43 - .../ti/devices/cc13x2_cc26x2/driverlib/adi.h | 791 - .../devices/cc13x2_cc26x2/driverlib/adi_doc.h | 68 - .../ti/devices/cc13x2_cc26x2/driverlib/aes.c | 372 - .../ti/devices/cc13x2_cc26x2/driverlib/aes.h | 843 - .../devices/cc13x2_cc26x2/driverlib/aes_doc.h | 66 - .../cc13x2_cc26x2/driverlib/aon_batmon.c | 80 - .../cc13x2_cc26x2/driverlib/aon_batmon.h | 306 - .../cc13x2_cc26x2/driverlib/aon_event.c | 180 - .../cc13x2_cc26x2/driverlib/aon_event.h | 564 - .../cc13x2_cc26x2/driverlib/aon_event_doc.h | 58 - .../devices/cc13x2_cc26x2/driverlib/aon_ioc.c | 39 - .../devices/cc13x2_cc26x2/driverlib/aon_ioc.h | 292 - .../cc13x2_cc26x2/driverlib/aon_ioc_doc.h | 65 - .../cc13x2_cc26x2/driverlib/aon_pmctl.c | 41 - .../cc13x2_cc26x2/driverlib/aon_pmctl.h | 201 - .../cc13x2_cc26x2/driverlib/aon_pmctl_doc.h | 99 - .../devices/cc13x2_cc26x2/driverlib/aon_rtc.c | 77 - .../devices/cc13x2_cc26x2/driverlib/aon_rtc.h | 931 - .../cc13x2_cc26x2/driverlib/aon_rtc_doc.h | 41 - .../devices/cc13x2_cc26x2/driverlib/aux_adc.c | 337 - .../devices/cc13x2_cc26x2/driverlib/aux_adc.h | 599 - .../cc13x2_cc26x2/driverlib/aux_smph.c | 41 - .../cc13x2_cc26x2/driverlib/aux_smph.h | 258 - .../cc13x2_cc26x2/driverlib/aux_sysif.c | 96 - .../cc13x2_cc26x2/driverlib/aux_sysif.h | 154 - .../devices/cc13x2_cc26x2/driverlib/aux_tdc.c | 111 - .../devices/cc13x2_cc26x2/driverlib/aux_tdc.h | 904 - .../cc13x2_cc26x2/driverlib/ccfgread.c | 41 - .../cc13x2_cc26x2/driverlib/ccfgread.h | 187 - .../cc13x2_cc26x2/driverlib/ccfgread_doc.h | 51 - .../cc13x2_cc26x2/driverlib/chipinfo.c | 210 - .../cc13x2_cc26x2/driverlib/chipinfo.h | 685 - .../ti/devices/cc13x2_cc26x2/driverlib/cpu.c | 396 - .../ti/devices/cc13x2_cc26x2/driverlib/cpu.h | 466 - .../devices/cc13x2_cc26x2/driverlib/cpu_doc.h | 44 - .../devices/cc13x2_cc26x2/driverlib/crypto.c | 943 - .../devices/cc13x2_cc26x2/driverlib/crypto.h | 856 - .../ti/devices/cc13x2_cc26x2/driverlib/ddi.c | 214 - .../ti/devices/cc13x2_cc26x2/driverlib/ddi.h | 462 - .../devices/cc13x2_cc26x2/driverlib/ddi_doc.h | 67 - .../devices/cc13x2_cc26x2/driverlib/debug.c | 57 - .../devices/cc13x2_cc26x2/driverlib/debug.h | 84 - .../driverlib/driverlib_release.c | 45 - .../driverlib/driverlib_release.h | 156 - .../devices/cc13x2_cc26x2/driverlib/event.c | 41 - .../devices/cc13x2_cc26x2/driverlib/event.h | 267 - .../cc13x2_cc26x2/driverlib/event_doc.h | 58 - .../devices/cc13x2_cc26x2/driverlib/flash.c | 672 - .../devices/cc13x2_cc26x2/driverlib/flash.h | 817 - .../ti/devices/cc13x2_cc26x2/driverlib/gpio.c | 41 - .../ti/devices/cc13x2_cc26x2/driverlib/gpio.h | 643 - .../cc13x2_cc26x2/driverlib/gpio_doc.h | 90 - .../driverlib/group_analog_doc.h | 105 - .../cc13x2_cc26x2/driverlib/group_aon_doc.h | 76 - .../cc13x2_cc26x2/driverlib/group_aux_doc.h | 58 - .../ti/devices/cc13x2_cc26x2/driverlib/i2c.c | 172 - .../ti/devices/cc13x2_cc26x2/driverlib/i2c.h | 974 - .../devices/cc13x2_cc26x2/driverlib/i2c_doc.h | 162 - .../ti/devices/cc13x2_cc26x2/driverlib/i2s.c | 349 - .../ti/devices/cc13x2_cc26x2/driverlib/i2s.h | 1359 - .../devices/cc13x2_cc26x2/driverlib/i2s_doc.h | 141 - .../cc13x2_cc26x2/driverlib/interrupt.c | 469 - .../cc13x2_cc26x2/driverlib/interrupt.h | 718 - .../cc13x2_cc26x2/driverlib/interrupt_doc.h | 162 - .../ti/devices/cc13x2_cc26x2/driverlib/ioc.c | 683 - .../ti/devices/cc13x2_cc26x2/driverlib/ioc.h | 1225 - .../devices/cc13x2_cc26x2/driverlib/ioc_doc.h | 92 - .../ti/devices/cc13x2_cc26x2/driverlib/osc.c | 625 - .../ti/devices/cc13x2_cc26x2/driverlib/osc.h | 730 - .../ti/devices/cc13x2_cc26x2/driverlib/pka.c | 1661 - .../ti/devices/cc13x2_cc26x2/driverlib/pka.h | 1455 - .../devices/cc13x2_cc26x2/driverlib/pka_doc.h | 80 - .../ti/devices/cc13x2_cc26x2/driverlib/prcm.c | 647 - .../ti/devices/cc13x2_cc26x2/driverlib/prcm.h | 1234 - .../cc13x2_cc26x2/driverlib/pwr_ctrl.c | 80 - .../cc13x2_cc26x2/driverlib/pwr_ctrl.h | 301 - .../cc13x2_cc26x2/driverlib/rf_ble_cmd.h | 2674 -- .../cc13x2_cc26x2/driverlib/rf_ble_mailbox.h | 76 - .../cc13x2_cc26x2/driverlib/rf_common_cmd.h | 1089 - .../cc13x2_cc26x2/driverlib/rf_data_entry.h | 219 - .../cc13x2_cc26x2/driverlib/rf_hs_cmd.h | 210 - .../cc13x2_cc26x2/driverlib/rf_hs_mailbox.h | 65 - .../cc13x2_cc26x2/driverlib/rf_ieee_cmd.h | 628 - .../cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h | 73 - .../cc13x2_cc26x2/driverlib/rf_mailbox.h | 364 - .../cc13x2_cc26x2/driverlib/rf_prop_cmd.h | 1171 - .../cc13x2_cc26x2/driverlib/rf_prop_mailbox.h | 71 - .../ti/devices/cc13x2_cc26x2/driverlib/rfc.c | 295 - .../ti/devices/cc13x2_cc26x2/driverlib/rfc.h | 465 - .../ti/devices/cc13x2_cc26x2/driverlib/rom.h | 1055 - .../cc13x2_cc26x2/driverlib/rom_crypto.c | 159 - .../cc13x2_cc26x2/driverlib/rom_crypto.h | 212 - .../devices/cc13x2_cc26x2/driverlib/setup.c | 344 - .../devices/cc13x2_cc26x2/driverlib/setup.h | 141 - .../cc13x2_cc26x2/driverlib/setup_doc.h | 41 - .../cc13x2_cc26x2/driverlib/setup_rom.c | 943 - .../cc13x2_cc26x2/driverlib/setup_rom.h | 469 - .../cc13x2_cc26x2/driverlib/setup_rom_doc.h | 44 - .../ti/devices/cc13x2_cc26x2/driverlib/sha2.c | 272 - .../ti/devices/cc13x2_cc26x2/driverlib/sha2.h | 802 - .../cc13x2_cc26x2/driverlib/sha2_doc.h | 62 - .../ti/devices/cc13x2_cc26x2/driverlib/smph.c | 101 - .../ti/devices/cc13x2_cc26x2/driverlib/smph.h | 312 - .../cc13x2_cc26x2/driverlib/smph_doc.h | 57 - .../ti/devices/cc13x2_cc26x2/driverlib/ssi.c | 253 - .../ti/devices/cc13x2_cc26x2/driverlib/ssi.h | 700 - .../cc13x2_cc26x2/driverlib/sw_chacha.c | 121 - .../driverlib/sw_ecrypt-config.h | 279 - .../driverlib/sw_ecrypt-machine.h | 51 - .../driverlib/sw_ecrypt-portable.h | 308 - .../cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h | 284 - .../driverlib/sw_poly1305-donna-32.h | 223 - .../driverlib/sw_poly1305-donna.c | 186 - .../driverlib/sw_poly1305-donna.h | 25 - .../cc13x2_cc26x2/driverlib/sys_ctrl.c | 375 - .../cc13x2_cc26x2/driverlib/sys_ctrl.h | 577 - .../devices/cc13x2_cc26x2/driverlib/systick.c | 41 - .../devices/cc13x2_cc26x2/driverlib/systick.h | 287 - .../cc13x2_cc26x2/driverlib/systick_doc.h | 68 - .../devices/cc13x2_cc26x2/driverlib/timer.c | 392 - .../devices/cc13x2_cc26x2/driverlib/timer.h | 1176 - .../cc13x2_cc26x2/driverlib/timer_doc.h | 121 - .../ti/devices/cc13x2_cc26x2/driverlib/trng.c | 112 - .../ti/devices/cc13x2_cc26x2/driverlib/trng.h | 451 - .../ti/devices/cc13x2_cc26x2/driverlib/uart.c | 304 - .../ti/devices/cc13x2_cc26x2/driverlib/uart.h | 1097 - .../cc13x2_cc26x2/driverlib/uart_doc.h | 107 - .../ti/devices/cc13x2_cc26x2/driverlib/udma.c | 448 - .../ti/devices/cc13x2_cc26x2/driverlib/udma.h | 1240 - .../ti/devices/cc13x2_cc26x2/driverlib/vims.c | 176 - .../ti/devices/cc13x2_cc26x2/driverlib/vims.h | 371 - .../cc13x2_cc26x2/driverlib/watchdog.c | 41 - .../cc13x2_cc26x2/driverlib/watchdog.h | 520 - .../cc13x2_cc26x2/driverlib/watchdog_doc.h | 121 - .../ti/devices/cc13x2_cc26x2/inc/asmdefs.h | 151 - .../ti/devices/cc13x2_cc26x2/inc/hw_adi.h | 1182 - .../cc13x2_cc26x2/inc/hw_adi_2_refsys.h | 362 - .../cc13x2_cc26x2/inc/hw_adi_3_refsys.h | 685 - .../devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h | 513 - .../devices/cc13x2_cc26x2/inc/hw_aon_batmon.h | 662 - .../devices/cc13x2_cc26x2/inc/hw_aon_event.h | 1135 - .../ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h | 158 - .../devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h | 625 - .../ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h | 546 - .../devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h | 1030 - .../devices/cc13x2_cc26x2/inc/hw_aux_anaif.h | 633 - .../devices/cc13x2_cc26x2/inc/hw_aux_evctl.h | 2355 -- .../ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h | 748 - .../ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h | 48 - .../ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h | 398 - .../devices/cc13x2_cc26x2/inc/hw_aux_smph.h | 282 - .../devices/cc13x2_cc26x2/inc/hw_aux_spim.h | 239 - .../devices/cc13x2_cc26x2/inc/hw_aux_sysif.h | 2088 -- .../ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h | 879 - .../cc13x2_cc26x2/inc/hw_aux_timer01.h | 611 - .../devices/cc13x2_cc26x2/inc/hw_aux_timer2.h | 2491 -- .../ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h | 1910 - .../cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h | 81 - .../devices/cc13x2_cc26x2/inc/hw_chip_def.h | 234 - .../ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h | 856 - .../ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h | 443 - .../ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h | 1122 - .../cc13x2_cc26x2/inc/hw_cpu_rom_table.h | 220 - .../ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h | 4789 --- .../devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h | 68 - .../devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h | 347 - .../ti/devices/cc13x2_cc26x2/inc/hw_crypto.h | 3966 -- .../ti/devices/cc13x2_cc26x2/inc/hw_ddi.h | 197 - .../devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h | 1153 - .../ti/devices/cc13x2_cc26x2/inc/hw_event.h | 3688 -- .../ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h | 2904 -- .../ti/devices/cc13x2_cc26x2/inc/hw_flash.h | 3498 -- .../ti/devices/cc13x2_cc26x2/inc/hw_gpio.h | 2247 -- .../ti/devices/cc13x2_cc26x2/inc/hw_gpram.h | 48 - .../ti/devices/cc13x2_cc26x2/inc/hw_gpt.h | 1697 - .../ti/devices/cc13x2_cc26x2/inc/hw_i2c.h | 728 - .../ti/devices/cc13x2_cc26x2/inc/hw_i2s.h | 967 - .../ti/devices/cc13x2_cc26x2/inc/hw_ints.h | 120 - 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100644 ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XX.h delete mode 100644 ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XXDMA.c delete mode 100644 ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XXDMA.h delete mode 100644 ext/hal/ti/simplelink/source/ti/drivers/utils/List.c delete mode 100644 ext/hal/ti/simplelink/source/ti/drivers/utils/List.h delete mode 100644 ext/hal/ti/simplelink/source/ti/drivers/utils/RingBuf.c delete mode 100644 ext/hal/ti/simplelink/source/ti/drivers/utils/RingBuf.h delete mode 100644 ext/hal/ti/simplelink/source/ti/drivers/watchdog/WatchdogCC32XX.c delete mode 100644 ext/hal/ti/simplelink/source/ti/drivers/watchdog/WatchdogCC32XX.h delete mode 100644 ext/hal/ti/simplelink/source/ti/net/slneterr.h delete mode 100644 ext/hal/ti/simplelink/source/ti/net/slnetif.c delete mode 100644 ext/hal/ti/simplelink/source/ti/net/slnetif.h delete mode 100644 ext/hal/ti/simplelink/source/ti/net/slnetsock.c delete mode 100644 ext/hal/ti/simplelink/source/ti/net/slnetsock.h delete mode 100644 ext/hal/ti/simplelink/source/ti/net/slnetutils.c delete mode 100644 ext/hal/ti/simplelink/source/ti/net/slnetutils.h rename ext/hal/ti/simplelink/Kconfig => modules/Kconfig.simplelink (100%) diff --git a/CODEOWNERS b/CODEOWNERS index 2c21235b280..97048d9702e 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -211,7 +211,6 @@ /ext/hal/microchip/ @franciscomunoz @albertofloyd @scottwcpg /ext/hal/nordic/ @carlescufi @anangl /ext/hal/nxp/ @MaureenHelm -/ext/hal/ti/simplelink/ @vanti /ext/lib/crypto/tinycrypt/ @ceolin /include/ @nashif @carlescufi @galak @MaureenHelm /include/drivers/adc.h @anangl diff --git a/drivers/wifi/simplelink/CMakeLists.txt b/drivers/wifi/simplelink/CMakeLists.txt index c4ba3dd1705..59ef94cdd54 100644 --- a/drivers/wifi/simplelink/CMakeLists.txt +++ b/drivers/wifi/simplelink/CMakeLists.txt @@ -3,9 +3,6 @@ if(CONFIG_WIFI_SIMPLELINK) zephyr_include_directories( . - $ENV{ZEPHYR_BASE}/ext/hal/ti/simplelink/kernel/zephyr/dpl - $ENV{ZEPHYR_BASE}/ext/hal/ti/simplelink/source - $ENV{ZEPHYR_BASE}/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting $ENV{ZEPHYR_BASE}/subsys/net/lib/tls_credentials ) zephyr_sources( diff --git a/ext/hal/CMakeLists.txt b/ext/hal/CMakeLists.txt index 46575689cf2..5da776fe0e5 100644 --- a/ext/hal/CMakeLists.txt +++ b/ext/hal/CMakeLists.txt @@ -3,6 +3,5 @@ add_subdirectory(cmsis) add_subdirectory(nordic) add_subdirectory(nxp) add_subdirectory(openisa) -add_subdirectory(ti) add_subdirectory_ifdef(CONFIG_HAS_ALTERA_HAL altera) add_subdirectory(microchip) diff --git a/ext/hal/Kconfig b/ext/hal/Kconfig index 11fd0413648..ab728dd1139 100644 --- a/ext/hal/Kconfig +++ b/ext/hal/Kconfig @@ -26,6 +26,4 @@ source "ext/hal/nxp/imx/Kconfig" source "ext/hal/openisa/vega_sdk_riscv/Kconfig" -source "ext/hal/ti/simplelink/Kconfig" - endmenu diff --git a/ext/hal/ti/CMakeLists.txt b/ext/hal/ti/CMakeLists.txt deleted file mode 100644 index 71592eef101..00000000000 --- a/ext/hal/ti/CMakeLists.txt +++ /dev/null @@ -1 +0,0 @@ -add_subdirectory(simplelink) diff --git a/ext/hal/ti/simplelink/CMakeLists.txt b/ext/hal/ti/simplelink/CMakeLists.txt deleted file mode 100644 index 85967225d01..00000000000 --- a/ext/hal/ti/simplelink/CMakeLists.txt +++ /dev/null @@ -1,60 +0,0 @@ -add_subdirectory(source/ti/devices) - -if(CONFIG_SIMPLELINK_HOST_DRIVER) - zephyr_include_directories( - . - source - kernel/zephyr/dpl - ) - zephyr_compile_definitions( - SL_SUPPORT_IPV6 - SL_PLATFORM_MULTI_THREADED - ) -endif() - -if(CONFIG_HAS_CC3220SDK) - if(CONFIG_SIMPLELINK_HOST_DRIVER) - zephyr_library() - zephyr_library_compile_definitions(${COMPILER}) - zephyr_library_sources( - source/ti/drivers/SPI.c - source/ti/drivers/spi/SPICC32XXDMA.c - source/ti/drivers/dma/UDMACC32XX.c - source/ti/drivers/power/PowerCC32XX.c - source/ti/drivers/utils/List.c - source/ti/drivers/net/wifi/source/driver.c - source/ti/drivers/net/wifi/source/device.c - source/ti/drivers/net/wifi/source/flowcont.c - source/ti/drivers/net/wifi/source/fs.c - source/ti/drivers/net/wifi/source/netapp.c - source/ti/drivers/net/wifi/source/netcfg.c - source/ti/drivers/net/wifi/source/netutil.c - source/ti/drivers/net/wifi/source/nonos.c - source/ti/drivers/net/wifi/source/spawn.c - source/ti/drivers/net/wifi/source/wlan.c - source/ti/drivers/net/wifi/porting/CC3220SF_LAUNCHXL.c - source/ti/drivers/net/wifi/porting/cc_pal.c - source/ti/drivers/net/wifi/eventreg.c - source/ti/drivers/net/wifi/source/sl_socket.c - - source/ti/devices/cc32xx/driverlib/timer.c - source/ti/devices/cc32xx/driverlib/udma.c - - kernel/zephyr/dpl/dpl.c - kernel/zephyr/dpl/MutexP_zephyr.c - kernel/zephyr/dpl/SemaphoreP_zephyr.c - kernel/zephyr/dpl/ClockP_zephyr.c - kernel/zephyr/dpl/HwiP_zephyr.c - ) - - set_source_files_properties(source/ti/drivers/net/wifi/source/driver.c - PROPERTIES COMPILE_DEFINITIONS "__LINUX_ERRNO_EXTENSIONS__;${COMPILER}" ) - set_source_files_properties(source/ti/drivers/net/wifi/source/driver.c - PROPERTIES COMPILE_FLAGS -Wno-incompatible-pointer-types) # driver.c warns on incompatible-pointer-types - endif() - -elseif(CONFIG_HAS_MSP432P4XXSDK) - zephyr_include_directories( - source - ) -endif() diff --git a/ext/hal/ti/simplelink/README b/ext/hal/ti/simplelink/README deleted file mode 100644 index b8a1adbed5e..00000000000 --- a/ext/hal/ti/simplelink/README +++ /dev/null @@ -1,90 +0,0 @@ -The SimpleLink SDKs provide peripheral driver and WiFi libraries -and hardware register access header files for the Texas Instruments -SimpleLink SoCs. - -For an explanation of the SimpleLink family SDK directory structure, see: -http://dev.ti.com/tirex/content/simplelink_cc32xx_sdk_2_40_01_01/docs/simplelink_mcu_sdk/Users_Guide.html#directory-structure - -1. CC13x2/26x2 SDK - -The current version supported in Zephyr is the SimpleLink CC13x2 and CC26x2 SDK -3.10.00.53, downloaded from: - - http://www.ti.com/tool/simplelink-cc13x2-26x2-sdk - -The driver library source is copied from the SDK, as follows: - - EXT_DIR=$ZEPHYR_BASE/ext/hal/ti/simplelink/source/ti - pushd simplelink_cc13x2_26x2_sdk_3_10_00_53/source/ti - find devices/cc13x2_cc26x2/{driverlib,inc,rf_patches} -depth -name '*.[c|h]' -print0 | cpio --null -pvdm $EXT_DIR - find devices/cc13x2_cc26x2/startup_files -depth -name ccfg.c -print0 | cpio --null -pvd $EXT_DIR - find $EXT_DIR/devices/cc13x2_cc26x2 -name '*.[c|h]' -exec dos2unix {} \; - popd - -The source file startup_files/ccfg.c has been modified to use the appropriate -sections when linking. - -TI provides the driver library functions burned into ROM at the factory, -or updated via a service pack patch, thus saving application code space. - -After setting CONFIG_HAS_CC13X2_CC26X2_SDK=y in Kconfig, most of the -peripheral driver library functions will be accessible from ROM. - -2. CC32xx SDK - -The current version supported in Zephyr is the SimpleLink CC32xx SDK -2.40.01.01, downloaded from: - - http://www.ti.com/tool/download/simplelink-cc32xx-sdk - -Source files from select subdirectories are copied from the -source/ti/ subdirectory of the SDK installation, as follows: - - EXT_DIR=$ZEPHYR_BASE/ext/hal/ti/simplelink/source/ti - find devices -not -path '*/\.*' -name '*.[c|h]' | \ - cpio -pdm $EXT_DIR - find drivers -name '*.[c|h]' | \ - cpio -pdm $EXT_DIR - find net -maxdepth 1 -name '*.[c|h]' | cpio -pdm $EXT_DIR - cd $EXT_DIR - find . -name '*.[c|h]' -exec chmod 664 {} \; - -In addition, some files in the drivers/net/wifi/porting directory -may need to be updated: notably user.h, cc_pal.h, and CC3220SF_LAUNCHXL.c. - -Note: TI provides the driver library functions burned into ROM at the factory, -or updated via a service pack patch, thus saving application code space. - -Calling driverlib APIs prefixed by "MAP_" will vector to those functions -already existing in ROM. - -After setting CONFIG_HAS_CC3220SDK=y in Kconfig, most of the -peripheral driver library functions will be accessible from ROM, -except for some functions in the following modules, which are -compiled in the Kbuild file: -- driverlib/pin.c -- driverlib/utils.c -- driverlib/prcm.c - -Setting CONFIG_SIMPLELINK_HOST_DRIVER=y builds the SimpleLink Host -Driver, which communicates over dedicated SPI to the -network coprocessor. - -2. MSP432 SDK - -The current version supported in Zephyr is MSP432 SDK V1.50.00.12, downloaded -from: - - http://www.ti.com/tool/simplelink-msp432-sdk - -Files in source/ti/devices/msp432p4xx/driverlib/ and inc/ are copied from -a Linux SDK installation (without modification). - -TI provides the driver library functions burned into ROM at the factory, -or updated via a service pack patch, thus saving application code space. - -Calling driverlib APIs prefixed by "MAP_" will vector to those functions -already existing in ROM. - -After setting CONFIG_HAS_MSP432P4XXSDK=y in Kconfig, most of the -peripheral driver library functions will be accessible from ROM. diff --git a/ext/hal/ti/simplelink/kernel/zephyr/dpl/ClockP_zephyr.c b/ext/hal/ti/simplelink/kernel/zephyr/dpl/ClockP_zephyr.c deleted file mode 100644 index aa8f2caf274..00000000000 --- a/ext/hal/ti/simplelink/kernel/zephyr/dpl/ClockP_zephyr.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -uint32_t ClockP_getSystemTicks() -{ - return (uint32_t)z_ms_to_ticks(k_uptime_get_32()); -} - -void ClockP_usleep(uint32_t usec) -{ - k_sleep((s32_t)usec); -} diff --git a/ext/hal/ti/simplelink/kernel/zephyr/dpl/HwiP_zephyr.c b/ext/hal/ti/simplelink/kernel/zephyr/dpl/HwiP_zephyr.c deleted file mode 100644 index 8201fcda357..00000000000 --- a/ext/hal/ti/simplelink/kernel/zephyr/dpl/HwiP_zephyr.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * - * SPDX-License-Identifier: Apache-2.0 - */ - - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/* - * IRQ_CONNECT requires we know the ISR signature and argument - * at build time; whereas SimpleLink plugs the interrupts - * at run time, so we create an ISR shim, and register that. - * The callback argument doesn't change after the ISR is registered. - */ -struct sl_isr_args -{ - HwiP_Fxn cb; - uintptr_t arg; -}; - -static struct sl_isr_args sl_UDMA_cb = {NULL, 0}; -static struct sl_isr_args sl_UDMAERR_cb = {NULL, 0}; -static struct sl_isr_args sl_NWPIC_cb = {NULL, 0}; -static struct sl_isr_args sl_LSPI_cb = {NULL, 0}; - -static void sl_isr(void *isr_arg) -{ - HwiP_Fxn cb = ((struct sl_isr_args *)isr_arg)->cb; - uintptr_t arg = ((struct sl_isr_args *)isr_arg)->arg; - - /* Call the SimpleLink ISR Handler: */ - if (cb) { - cb(arg); - } -} - -/* Must hardcode the IRQ for IRQ_CONNECT macro. Must be <= CONFIG_NUM_IRQS.*/ -#define EXCEPTION_UDMA 46 /* == INT_UDMA (62) - 16 */ -#define EXCEPTION_UDMAERR 47 /* == INT_UDMAERR (63) - 16 */ -#define EXCEPTION_NWPIC 171 /* == INT_NWPIC (187) - 16 */ -#define EXCEPTION_LSPI 177 /* == INT_LSPI (193) - 16 */ - -HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, HwiP_Params *params) -{ - HwiP_Handle handle = 0; - uint32_t priority = ~0; - uintptr_t arg = 0; - - if (params) { - priority = params->priority; - arg = params->arg; - } - - /* - * SimpleLink only uses the NWPIC, UDMA, UDMAERR and LSPI interrupts: - */ - __ASSERT(INT_NWPIC == interruptNum || INT_UDMA == interruptNum || - INT_UDMAERR == interruptNum || INT_LSPI == interruptNum, - "Unexpected interruptNum: %d\r\n", - interruptNum); - /* - * Priority expected is either: - * INT_PRIORITY_LVL_1, - * or ~0 or 255 (meaning lowest priority) - * ~0 and 255 are meant to be the same as INT_PRIORITY_LVL_7. - * For ~0 or 255, we want 7; but Zephyr IRQ_CONNECT adds +1, - * so we pass 6 for those TI drivers passing prio = ~0. - */ - __ASSERT((INT_PRIORITY_LVL_1 == priority) || - (0xff == (priority & 0xff)), - "Expected priority: 0x%x or 0x%x, got: 0x%x\r\n", - INT_PRIORITY_LVL_1, 0xff, (unsigned int)priority); - - switch(interruptNum) { - case INT_UDMA: - sl_UDMA_cb.cb = hwiFxn; - sl_UDMA_cb.arg = arg; - IRQ_CONNECT(EXCEPTION_UDMA, 6, sl_isr, &sl_UDMA_cb, 0); - break; - case INT_UDMAERR: - sl_UDMAERR_cb.cb = hwiFxn; - sl_UDMAERR_cb.arg = arg; - IRQ_CONNECT(EXCEPTION_UDMAERR, 6, sl_isr, &sl_UDMAERR_cb, 0); - break; - case INT_NWPIC: - sl_NWPIC_cb.cb = hwiFxn; - sl_NWPIC_cb.arg = arg; - IRQ_CONNECT(EXCEPTION_NWPIC, 1, sl_isr, &sl_NWPIC_cb, 0); - break; - case INT_LSPI: - sl_LSPI_cb.cb = hwiFxn; - sl_LSPI_cb.arg = arg; - IRQ_CONNECT(EXCEPTION_LSPI, 6, sl_isr, &sl_LSPI_cb, 0); - break; - default: - return(handle); - } - irq_enable(interruptNum - 16); - - return (HwiP_Handle)interruptNum; -} - -/* Can't actually de-register an interrupt in Zephyr, so just disable: */ -void HwiP_delete(HwiP_Handle handle) -{ - int interruptNum = (int)handle; - - __ASSERT(INT_NWPIC == interruptNum || INT_UDMA == interruptNum || - INT_UDMAERR == interruptNum || INT_LSPI == interruptNum, - "Unexpected interruptNum: %d\r\n", - interruptNum); - - irq_disable(interruptNum - 16); -} - -void HwiP_Params_init(HwiP_Params *params) -{ - params->arg = 0; - params->priority = ~0; -} - -/* Zephyr has no functions for clearing an interrupt, so use driverlib: */ -void HwiP_clearInterrupt(int interruptNum) -{ - MAP_IntPendClear((unsigned long)interruptNum); -} - -void HwiP_enableInterrupt(int interruptNum) -{ - irq_enable(interruptNum - 16); -} - -void HwiP_disableInterrupt(int interruptNum) -{ - irq_disable(interruptNum - 16); -} - -uintptr_t HwiP_disable(void) -{ - uintptr_t key; - - key = irq_lock(); - - return (key); -} - -void HwiP_restore(uintptr_t key) -{ - irq_unlock(key); -} diff --git a/ext/hal/ti/simplelink/kernel/zephyr/dpl/MutexP_zephyr.c b/ext/hal/ti/simplelink/kernel/zephyr/dpl/MutexP_zephyr.c deleted file mode 100644 index ead1f5e4373..00000000000 --- a/ext/hal/ti/simplelink/kernel/zephyr/dpl/MutexP_zephyr.c +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -/* - * Zephyr kernel object pools: - * - * This bit of code enables the simplelink host driver, which assumes dynamic - * allocation of kernel objects (semaphores, mutexes, hwis), to be - * more easily ported to Zephyr (which supports static allocation). - * - * It leverages the Zephyr memory slab, enabling us to define a mutex object - * pool for use by the SimpleLink host driver. - */ - -/* Define a Mutex pool: */ -#define DPL_MAX_MUTEXES 4 /* From simplelink driver code inspection */ -K_MEM_SLAB_DEFINE(mutex_slab, sizeof(struct k_mutex), DPL_MAX_MUTEXES,\ - MEM_ALIGN); - -static struct k_mutex *dpl_mutex_pool_alloc() -{ - struct k_mutex *mutex_ptr = NULL; - - if (k_mem_slab_alloc(&mutex_slab, (void **)&mutex_ptr, - K_NO_WAIT) < 0) { - /* - * We assert, as this is a logic error, due to a change in # - * of mutexes needed by the simplelink driver. In that case, - * the mutex pool must be increased programmatically to match. - */ - __ASSERT(0, "Increase size of DPL mutex pool"); - } - return mutex_ptr; -} - -static MutexP_Status dpl_mutex_pool_free(struct k_mutex *mutex) -{ - k_mem_slab_free(&mutex_slab, (void **)&mutex); - return MutexP_OK; -} - -MutexP_Handle MutexP_create(MutexP_Params *params) -{ - struct k_mutex *mutex; - - ARG_UNUSED(params); - - mutex = dpl_mutex_pool_alloc(); - __ASSERT(mutex, "MutexP_create failed\r\n"); - - if (mutex) { - k_mutex_init(mutex); - } - return ((MutexP_Handle)mutex); -} - -void MutexP_delete(MutexP_Handle handle) -{ - /* No way in Zephyr to "reset" the lock, so just re-init: */ - k_mutex_init((struct k_mutex *)handle); - - dpl_mutex_pool_free((struct k_mutex *)handle); -} - -uintptr_t MutexP_lock(MutexP_Handle handle) -{ - unsigned int key = 0; - int retval; - - retval = k_mutex_lock((struct k_mutex *)handle, K_FOREVER); - __ASSERT(retval == 0, - "MutexP_lock: retval: %d\r\n", retval); - - return ((uintptr_t)key); -} - -void MutexP_Params_init(MutexP_Params *params) -{ - params->callback = NULL; -} - -void MutexP_unlock(MutexP_Handle handle, uintptr_t key) -{ - ARG_UNUSED(key); - - k_mutex_unlock((struct k_mutex *)handle); -} diff --git a/ext/hal/ti/simplelink/kernel/zephyr/dpl/SemaphoreP_zephyr.c b/ext/hal/ti/simplelink/kernel/zephyr/dpl/SemaphoreP_zephyr.c deleted file mode 100644 index 07fb5b36859..00000000000 --- a/ext/hal/ti/simplelink/kernel/zephyr/dpl/SemaphoreP_zephyr.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -/* - * Zephyr kernel object pools: - * - * This bit of code enables the simplelink host driver, which assumes dynamic - * allocation of kernel objects (semaphores, mutexes, hwis), to be - * more easily ported to Zephyr (which supports static allocation). - * - * It leverages the Zephyr memory slab, enabling us to define a semaphore - * object pool for use by the SimpleLink host driver. - */ -#define DPL_MAX_SEMAPHORES 14 /* (user.h:MAX_CONCURRENT_ACTIONS+4) = 14 */ -K_MEM_SLAB_DEFINE(sem_slab, sizeof(struct k_sem), DPL_MAX_SEMAPHORES,\ - MEM_ALIGN); - -static struct k_sem *dpl_sem_pool_alloc() -{ - struct k_sem *sem_ptr = NULL; - - if (k_mem_slab_alloc(&sem_slab, (void **)&sem_ptr, K_NO_WAIT) < 0) { - /* - * We assert, as this is a logic error, due to a change in # - * of semaphores needed by the simplelink driver. In that case, - * the sem pool must be increased programmatically to match. - */ - __ASSERT(0, "Increase size of DPL semaphore pool"); - } - return sem_ptr; -} - -static SemaphoreP_Status dpl_sem_pool_free(struct k_sem *sem) -{ - k_mem_slab_free(&sem_slab, (void **)&sem); - - return SemaphoreP_OK; -} - -/* timeout comes in and out as milliSeconds: */ -static int32_t dpl_convert_timeout(uint32_t timeout) -{ - int32_t zephyr_timeout; - - switch(timeout) { - case SemaphoreP_NO_WAIT: - zephyr_timeout = K_NO_WAIT; - break; - case SemaphoreP_WAIT_FOREVER: - zephyr_timeout = K_FOREVER; - break; - default: - zephyr_timeout = timeout; - } - return zephyr_timeout; -} - - -SemaphoreP_Handle SemaphoreP_create(unsigned int count, - SemaphoreP_Params *params) -{ - unsigned int limit = UINT_MAX; - struct k_sem *sem; - - if (params) { - limit = (params->mode == SemaphoreP_Mode_BINARY) ? - 1 : UINT_MAX; - } - - sem = dpl_sem_pool_alloc(); - if (sem) { - k_sem_init(sem, 0, limit); - } - - return (SemaphoreP_Handle)sem; -} - -SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count) -{ - SemaphoreP_Params params; - - SemaphoreP_Params_init(¶ms); - params.mode = SemaphoreP_Mode_BINARY; - - return (SemaphoreP_create(count, ¶ms)); -} - - -void SemaphoreP_delete(SemaphoreP_Handle handle) -{ - k_sem_reset((struct k_sem *)handle); - - (void)dpl_sem_pool_free((struct k_sem *)handle); -} - -void SemaphoreP_Params_init(SemaphoreP_Params *params) -{ - params->mode = SemaphoreP_Mode_COUNTING; - params->callback = NULL; -} - -/* - * The SimpleLink driver calls this function with a timeout of 0 to "clear" - * the SyncObject, rather than calling dpl_SyncObjClear() directly. - * See: /source/ti/drivers/net/wifi/source/driver.h - * #define SL_DRV_SYNC_OBJ_CLEAR(pObj) - * (void)sl_SyncObjWait(pObj,SL_OS_NO_WAIT); - * - * So, we claim (via simplelink driver code inspection), that SyncObjWait - * will *only* be called with timeout == 0 if the intention is to clear the - * semaphore: in that case, we just call k_sem_reset. - */ -SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, uint32_t timeout) -{ - int retval; - - if (0 == timeout) { - k_sem_reset((struct k_sem *)handle); - retval = SemaphoreP_OK; - } else { - retval = k_sem_take((struct k_sem *)handle, - dpl_convert_timeout(timeout)); - __ASSERT_NO_MSG(retval != -EBUSY); - retval = (retval >= 0) ? SemaphoreP_OK : SemaphoreP_TIMEOUT; - } - return retval; -} - -void SemaphoreP_post(SemaphoreP_Handle handle) -{ - k_sem_give((struct k_sem *)handle); -} diff --git a/ext/hal/ti/simplelink/kernel/zephyr/dpl/dpl.c b/ext/hal/ti/simplelink/kernel/zephyr/dpl/dpl.c deleted file mode 100644 index 39f3ef22e04..00000000000 --- a/ext/hal/ti/simplelink/kernel/zephyr/dpl/dpl.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -#define SPAWN_TASK_STACKSIZE 2048 -/* - * Priority must be higher than any thread priority in the system which - * might use the SimpleLink host driver, which involves the spawn_task(). - * Since SimpleLink APIs may be called from any thread, including - * cooperative threads, and the _main kernel thread, we must set this - * as highest prioirty. - */ -#define SPAWN_TASK_PRIORITY K_HIGHEST_THREAD_PRIO - -/* Spawn message queue size: Could be 1, but 3 is used by other DPL ports */ -#define SPAWN_QUEUE_SIZE ( 3 ) - -/* Stack, for the simplelink spawn task: */ -static K_THREAD_STACK_DEFINE(spawn_task_stack, SPAWN_TASK_STACKSIZE); -static struct k_thread spawn_task_data; - -static void spawn_task(void *unused1, void *unused2, void *unused3); - -/* - * MessageQ to send message from an ISR or other task to the SimpleLink - * "Spawn" task: - */ -K_MSGQ_DEFINE(spawn_msgq, sizeof(tSimpleLinkSpawnMsg), SPAWN_QUEUE_SIZE,\ - MEM_ALIGN); - -/* - * SimpleLink does not have an init hook, so we export this function to - * be called early during system initialization. - */ -static int dpl_zephyr_init(struct device *port) -{ - (void)k_thread_create(&spawn_task_data, spawn_task_stack, - SPAWN_TASK_STACKSIZE, spawn_task, - NULL, NULL, NULL, - SPAWN_TASK_PRIORITY, 0, K_NO_WAIT); - return 0; -} -SYS_INIT(dpl_zephyr_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); - -/* SimpleLink driver code can call this from ISR or task context: */ -_SlReturnVal_t os_Spawn(P_OS_SPAWN_ENTRY pEntry, void *pValue, - unsigned long flags) -{ - tSimpleLinkSpawnMsg slMsg; - _SlReturnVal_t retval; - - slMsg.pEntry = pEntry; - slMsg.pValue = pValue; - - if (0 == k_msgq_put(&spawn_msgq, &slMsg, K_NO_WAIT)) { - retval = OS_OK; - } - else { - retval = -1; - __ASSERT(retval == OS_OK, - "os_Spawn: Failed to k_msgq_put failed\r\n"); - - } - - return retval; -} - -void spawn_task(void *unused1, void *unused2, void *unused3) -{ - tSimpleLinkSpawnMsg slMsg; - - ARG_UNUSED(unused1); - ARG_UNUSED(unused2); - ARG_UNUSED(unused3); - - while (1) { - k_msgq_get(&spawn_msgq, &slMsg, K_FOREVER); - slMsg.pEntry(slMsg.pValue); - } -} - -#if CONFIG_ERRNO && !defined(SL_INC_INTERNAL_ERRNO) -/* - * Called by the SimpleLink host driver to set POSIX error codes - * for the host OS. - */ -int dpl_set_errno(int err) -{ - /* Ensure (POSIX) errno is positive. - * __errno() is a Zephyr function returning a pointer to the - * current thread's errno variable. - */ - *__errno() = (err < 0? -err : err); - return -1; -} -#endif diff --git a/ext/hal/ti/simplelink/kernel/zephyr/dpl/dpl.h b/ext/hal/ti/simplelink/kernel/zephyr/dpl/dpl.h deleted file mode 100644 index 3642a74603a..00000000000 --- a/ext/hal/ti/simplelink/kernel/zephyr/dpl/dpl.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#define MEM_ALIGN (sizeof(uint32_t)) - -extern int *__errno(void); diff --git a/ext/hal/ti/simplelink/source/ti/devices/CMakeLists.txt b/ext/hal/ti/simplelink/source/ti/devices/CMakeLists.txt deleted file mode 100644 index 93caf4e5873..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -add_subdirectory_ifdef(CONFIG_HAS_CC3220SDK cc32xx) -add_subdirectory_ifdef(CONFIG_HAS_MSP432P4XXSDK msp432p4xx) -add_subdirectory_ifdef(CONFIG_HAS_CC13X2_CC26X2_SDK cc13x2_cc26x2) diff --git a/ext/hal/ti/simplelink/source/ti/devices/DeviceFamily.h b/ext/hal/ti/simplelink/source/ti/devices/DeviceFamily.h deleted file mode 100644 index 67d41a9c40e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/DeviceFamily.h +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file DeviceFamily.h - * - * @brief Infrastructure to select correct driverlib path and identify devices - * - * This module enables the selection of the correct driverlib path for the current - * device. It also facilitates the use of per-device conditional compilation - * to enable minor variations in drivers between devices. - * - * In order to use this functionality, DeviceFamily_XYZ must be defined as one of - * the supported values. The DeviceFamily_ID and DeviceFamily_DIRECTORY defines - * are set based on DeviceFamily_XYZ. - */ - -#ifndef ti_devices_DeviceFamily__include -#define ti_devices_DeviceFamily__include - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * DeviceFamily_ID_XYZ values. - * - * DeviceFamily_ID may be used in the preprocessor for conditional compilation. - * DeviceFamily_ID is set to one of these values based on the top level - * DeviceFamily_XYZ define. - */ -#define DeviceFamily_ID_CC13X0 1 -#define DeviceFamily_ID_CC26X0 2 -#define DeviceFamily_ID_CC26X0R2 3 -#define DeviceFamily_ID_CC13X2 4 -#define DeviceFamily_ID_CC26X2 5 -#define DeviceFamily_ID_CC3200 8 -#define DeviceFamily_ID_CC3220 9 -#define DeviceFamily_ID_MSP432P401x 10 -#define DeviceFamily_ID_MSP432P4x1xI 11 -#define DeviceFamily_ID_MSP432P4x1xT 12 -#define DeviceFamily_ID_MSP432E401Y 13 -#define DeviceFamily_ID_MSP432E411Y 14 - -/* - * DeviceFamily_PARENT_XYZ values. - * - * DeviceFamily_PARENT may be used in the preprocessor for conditional - * compilation. DeviceFamily_PARENT is set to one of these values based - * on the top-level DeviceFamily_XYZ define. - */ -#define DeviceFamily_PARENT_CC13X0_CC26X0 1 -#define DeviceFamily_PARENT_CC13X2_CC26X2 2 -#define DeviceFamily_PARENT_MSP432P401R 3 -#define DeviceFamily_PARENT_MSP432P4111 4 - -/* - * Lookup table that sets DeviceFamily_ID, DeviceFamily_DIRECTORY, and - * DeviceFamily_PARENT based on the DeviceFamily_XYZ define. - * If DeviceFamily_XYZ is undefined, a compiler error is thrown. If - * multiple DeviceFamily_XYZ are defined, the first one encountered is used. - */ -#if defined(DeviceFamily_CC13X0) - #define DeviceFamily_ID DeviceFamily_ID_CC13X0 - #define DeviceFamily_DIRECTORY cc13x0 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 - -#elif defined(DeviceFamily_CC13X2) - #define DeviceFamily_ID DeviceFamily_ID_CC13X2 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC26X0) - #define DeviceFamily_ID DeviceFamily_ID_CC26X0 - #define DeviceFamily_DIRECTORY cc26x0 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 - -#elif defined(DeviceFamily_CC26X0R2) - #define DeviceFamily_ID DeviceFamily_ID_CC26X0R2 - #define DeviceFamily_DIRECTORY cc26x0r2 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X0_CC26X0 - -#elif defined(DeviceFamily_CC26X2) - #define DeviceFamily_ID DeviceFamily_ID_CC26X2 - #define DeviceFamily_DIRECTORY cc13x2_cc26x2 - #define DeviceFamily_PARENT DeviceFamily_PARENT_CC13X2_CC26X2 - -#elif defined(DeviceFamily_CC3200) - #define DeviceFamily_ID DeviceFamily_ID_CC3200 - #define DeviceFamily_DIRECTORY cc32xx - -#elif defined(DeviceFamily_CC3220) - #define DeviceFamily_ID DeviceFamily_ID_CC3220 - #define DeviceFamily_DIRECTORY cc32xx - -#elif defined(DeviceFamily_MSP432P401x) || defined(__MSP432P401R__) - #define DeviceFamily_ID DeviceFamily_ID_MSP432P401x - #define DeviceFamily_DIRECTORY msp432p4xx - #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P401R - #if !defined(__MSP432P401R__) - #define __MSP432P401R__ - #endif - -#elif defined(DeviceFamily_MSP432P4x1xI) - #define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xI - #define DeviceFamily_DIRECTORY msp432p4xx - #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 - #if !defined(__MSP432P4111__) - #define __MSP432P4111__ - #endif - -#elif defined(DeviceFamily_MSP432P4x1xT) - #define DeviceFamily_ID DeviceFamily_ID_MSP432P4x1xT - #define DeviceFamily_DIRECTORY msp432p4xx - #define DeviceFamily_PARENT DeviceFamily_PARENT_MSP432P4111 - #if !defined(__MSP432P4111__) - #define __MSP432P4111__ - #endif - -#elif defined(DeviceFamily_MSP432E401Y) - #define DeviceFamily_ID DeviceFamily_ID_MSP432E401Y - #define DeviceFamily_DIRECTORY msp432e4 - #if !defined(__MSP432E401Y__) - #define __MSP432E401Y__ - #endif - -#elif defined(DeviceFamily_MSP432E411Y) - #define DeviceFamily_ID DeviceFamily_ID_MSP432E411Y - #define DeviceFamily_DIRECTORY msp432e4 - #if !defined(__MSP432E411Y__) - #define __MSP432E411Y__ - #endif -#else - #error "DeviceFamily_XYZ undefined. You must define a DeviceFamily_XYZ!" -#endif - -/* Ensure that only one DeviceFamily was specified */ -#if (defined(DeviceFamily_CC13X0) + defined(DeviceFamily_CC13X2) \ - + defined(DeviceFamily_CC26X0) + defined(DeviceFamily_CC26X0R2) \ - + defined(DeviceFamily_CC26X2) \ - + defined(DeviceFamily_CC3200) + defined(DeviceFamily_CC3220) \ - + defined(DeviceFamily_MSP432P401x) + defined(DeviceFamily_MSP432P4x1xI) \ - + defined(DeviceFamily_MSP432P4x1xT) + defined(DeviceFamily_MSP432E401Y) \ - + defined(DeviceFamily_MSP432E411Y) \ - ) > 1 - #error More then one DeviceFamily has been defined! -#endif - -/*! - * @brief Macro to include correct driverlib path. - * - * @pre DeviceFamily_XYZ which sets DeviceFamily_DIRECTORY must be defined - * first. - * - * @param x A token containing the path of the file to include based on - * the root device folder. The preceding forward slash must be - * omitted. For example: - * - #include DeviceFamily_constructPath(inc/hw_memmap.h) - * - #include DeviceFamily_constructPath(driverlib/ssi.h) - * - * @return Returns an include path. - * - */ -#define DeviceFamily_constructPath(x) - -#ifdef __cplusplus -} -#endif - -#endif /* ti_devices_DeviceFamily__include */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/CMakeLists.txt b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/CMakeLists.txt deleted file mode 100644 index 3f2deafc66e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories( - . - ) - -zephyr_library() -zephyr_library_compile_definitions(${COMPILER}) -zephyr_library_sources( - # Required for SystemTrimDevice which is not in ROM - driverlib/setup.c - driverlib/chipinfo.c - driverlib/aux_sysif.c - # Required for CPUdelay which is not in ROM - driverlib/cpu.c - ) diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.c deleted file mode 100644 index 77e5a47db83..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.c +++ /dev/null @@ -1,43 +0,0 @@ -/****************************************************************************** -* Filename: adi.c -* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) -* Revision: 47706 -* -* Description: Driver for the ADI interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aux_smph.h" -#include "adi.h" -#include "cpu.h" diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h deleted file mode 100644 index 450847eb47d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi.h +++ /dev/null @@ -1,791 +0,0 @@ -/****************************************************************************** -* Filename: adi.h -* Revised: 2016-11-17 16:39:28 +0100 (Thu, 17 Nov 2016) -* Revision: 47706 -* -* Description: Defines and prototypes for the ADI master interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup analog_group -//! @{ -//! \addtogroup adi_api -//! @{ -// -//***************************************************************************** - -#ifndef __ADI_H__ -#define __ADI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_uart.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_adi.h" -#include "debug.h" -#include "ddi.h" - -//***************************************************************************** -// -// Number of registers in the ADI slave -// -//***************************************************************************** -#define ADI_SLAVE_REGS 16 - - -//***************************************************************************** -// -// Defines that is used to control the ADI slave and master -// -//***************************************************************************** -#define ADI_PROTECT 0x00000080 -#define ADI_ACK 0x00000001 -#define ADI_SYNC 0x00000000 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! \brief Checks an ADI base address. -//! -//! This function determines if an ADI port base address is valid. -//! -//! \param ui32Base is the base address of the ADI port. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise -// -//***************************************************************************** -static bool -ADIBaseValid(uint32_t ui32Base) -{ - return(ui32Base == ADI2_BASE || ui32Base == ADI3_BASE || - ui32Base == AUX_ADI4_BASE); -} -#endif - - - - - -//***************************************************************************** -// -//! \brief Write an 8 bit value to a register in an ADI slave. -//! -//! This function will write a value to a single register in the analog domain. -//! The access to the registers in the analog domain is either 8, 16, or 32 bit -//! aligned. You can only do 16 bit access on registers 0-1 / 2-3, etc. Similarly -//! 32 bit accesses are always performed on register 0-3 / 4-7, etc. Addresses -//! for the registers and values being written to the registers will be -//! truncated according to this access scheme. -//! -//! \note This operation is write only for the specified register. No -//! previous value of the register will be kept (i.e. this is NOT -//! read-modify-write on the register). -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the register to write. -//! \param ui8Val is the 8 bit value to write to the register. -//! -//! \return None -//! -//! \sa ADI16RegWrite(), ADI32RegWrite() -// -//***************************************************************************** -__STATIC_INLINE void -ADI8RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) -{ - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Write the value to the register. - HWREGB(ui32Base + ui32Reg) = ui8Val; -} - -//***************************************************************************** -// -//! \brief Write a 16 bit value to 2 registers in the ADI slave. -//! -//! This function will write a value to 2 consecutive registers in the analog -//! domain. The access to the registers in the analog domain is either 8, 16 -//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3, -//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7, -//! etc. Addresses for the registers and values being written -//! to the registers will be truncated according to this access scheme. -//! -//! \note The byte addressing bit will be ignored, to ensure 16 bit access -//! to the ADI slave. -//! -//! \note This operation is write only for the specified register. No -//! previous value of the register will be kept (i.e. this is NOT -//! read-modify-write on the register). -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the register to write. -//! \param ui16Val is the 16 bit value to write to the register. -//! -//! \return None -//! -//! \sa ADI8RegWrite(), ADI32RegWrite() -// -//***************************************************************************** -__STATIC_INLINE void -ADI16RegWrite(uint32_t ui32Base, uint32_t ui32Reg, - uint16_t ui16Val) -{ - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Write the value to the register. - HWREGH(ui32Base + (ui32Reg & 0xFE)) = ui16Val; -} - -//***************************************************************************** -// -//! \brief Write a 32 bit value to 4 registers in the ADI slave. -//! -//! This function will write a value to 4 consecutive registers in the analog -//! domain. The access to the registers in the analog domain is either 8, 16 -//! or 32 bit aligned. You can only do 16 bit access on registers 0-1 / 2-3, -//! etc. Similarly 32 bit accesses are always performed on register 0-3 / 4-7, -//! etc. Addresses for the registers and values being written -//! to the registers will be truncated according to this access scheme. -//! -//! \note The byte and half word addressing bits will be ignored, to ensure -//! 32 bit access to the ADI slave. -//! -//! \note This operation is write only for the specified register. No -//! previous value of the register will be kept (i.e. this is NOT -//! read-modify-write on the register). -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the register to write. -//! \param ui32Val is the 32 bit value to write to the register. -//! -//! \return None -//! -//! \sa ADI8RegWrite(), ADI16RegWrite() -// -//***************************************************************************** -__STATIC_INLINE void -ADI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) -{ - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Write the value to the register. - HWREG(ui32Base + (ui32Reg & 0xFC)) = ui32Val; -} - -//***************************************************************************** -// -//! \brief Read the value of an 8 bit register in the ADI slave. -//! -//! This function will read an 8 bit register in the analog domain and return -//! the value as the lower 8 bits of an \c uint32_t. The access to the -//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can -//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses -//! are always performed on register 0-3 / 4-7, etc. Addresses for the -//! registers and values being written to the registers will be truncated -//! according to this access scheme. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the 8 bit register to read. -//! -//! \return Returns the 8 bit value of the analog register in the least -//! significant byte of the \c uint32_t. -//! -//! \sa ADI16RegRead(), ADI32RegRead() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -ADI8RegRead(uint32_t ui32Base, uint32_t ui32Reg) -{ - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Read the register and return the value. - return(HWREGB(ui32Base + ui32Reg)); -} - -//***************************************************************************** -// -//! \brief Read the value in a 16 bit register. -//! -//! This function will read 2 x 8 bit registers in the analog domain and return -//! the value as the lower 16 bits of an \c uint32_t. The access to the -//! registers in the analog domain is either 8, 16 or 32 bit aligned. You can -//! only do 16 bit access on registers 0-1 / 2-3, etc. Similarly 32 bit accesses -//! are always performed on register 0-3 / 4-7, etc. Addresses for the -//! registers and values being written to the registers will be truncated -//! according to this access scheme. -//! -//! \note The byte addressing bit will be ignored, to ensure 16 bit access -//! to the ADI slave. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the 16 bit register to read. -//! -//! \return Returns the 16 bit value of the 2 analog register in the 2 least -//! significant bytes of the \c uint32_t. -//! -//! \sa ADI8RegRead(), ADI32RegRead() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -ADI16RegRead(uint32_t ui32Base, uint32_t ui32Reg) -{ - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Read the registers and return the value. - return(HWREGH(ui32Base + (ui32Reg & 0xFE))); -} - -//***************************************************************************** -// -//! \brief Read the value in a 32 bit register. -//! -//! This function will read 4 x 8 bit registers in the analog domain and return -//! the value as an \c uint32_t. The access to the registers in the analog -//! domain is either 8, 16 or 32 bit aligned. You can only do 16 bit access on -//! registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always performed on -//! register 0-3 / 4-7, etc. Addresses for the registers and values being -//! written to the registers will be truncated according to this access scheme. -//! -//! \note The byte and half word addressing bits will be ignored, to ensure -//! 32 bit access to the ADI slave. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the 32 bit register to read. -//! -//! \return Returns the 32 bit value of the 4 analog registers. -//! -//! \sa ADI8RegRead(), ADI16RegRead() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -ADI32RegRead(uint32_t ui32Base, uint32_t ui32Reg) -{ - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Read the registers and return the value. - return(HWREG(ui32Base + (ui32Reg & 0xFC))); -} - -//***************************************************************************** -// -//! \brief Set specific bits in a single 8 bit ADI register. -//! -//! This function will set bits in a single register in the analog domain. -//! The access to the registers in the analog domain is either 8, 16 or 32 bit -//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access -//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always -//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values -//! being written to the registers will be truncated according to this access -//! scheme. -//! -//! \note This operation is write only for the specified register. -//! This function is used to set bits in a specific 8 bit register in the -//! ADI slave. Only bits in the selected register are affected by the -//! operation. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the base register to assert the bits in. -//! \param ui8Val is the 8 bit one-hot encoded value specifying which -//! bits to set in the register. -//! -//! \return None -//! -//! \sa ADI16BitsSet(), ADI32BitsSet() -// -//***************************************************************************** -__STATIC_INLINE void -ADI8BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_SET; - - // Set the selected bits. - HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val; -} - -//***************************************************************************** -// -//! \brief Set specific bits in 2 x 8 bit ADI slave registers. -//! -//! This function will set bits in 2 registers in the analog domain. -//! The access to the registers in the analog domain is either 8, 16 or 32 bit -//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access -//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always -//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values -//! being written to the registers will be truncated according to this access -//! scheme. -//! -//! \note This operation is write only for the specified register. -//! This function is used to set bits in 2 consecutive 8 bit registers in the -//! ADI slave. Only bits in the selected registers are affected by the -//! operation. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the base register to assert the bits in. -//! \param ui16Val is the 16 bit one-hot encoded value specifying which -//! bits to set in the registers. -//! -//! \return None -//! -//! \sa ADI8BitsSet(), ADI32BitsSet() -// -//***************************************************************************** -__STATIC_INLINE void -ADI16BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_SET; - - // Set the selected bits. - HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val; -} - -//***************************************************************************** -// -//! \brief Set specific bits in 4 x 8 bit ADI slave registers. -//! -//! This function will set bits in 4 registers in the analog domain. -//! The access to the registers in the analog domain is either 8, 16 or 32 bit -//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access -//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always -//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values -//! being written to the registers will be truncated according to this access -//! scheme. -//! -//! \note This operation is write only for the specified register. -//! This function is used to set bits in 4 consecutive 8 bit registers in the -//! ADI slave. Only bits in the selected registers are affected by the -//! operation. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the base register to assert the bits in. -//! \param ui32Val is the 32 bit one-hot encoded value specifying which -//! bits to set in the registers. -//! -//! \return None -//! -//! \sa ADI8BitsSet(), ADI16BitsSet() -// -//***************************************************************************** -__STATIC_INLINE void -ADI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_SET; - - // Set the selected bits. - HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val; -} - -//***************************************************************************** -// -//! \brief Clear specific bits in an 8 bit ADI register. -//! -//! This function will clear bits in a register in the analog domain. -//! The access to the registers in the analog domain is either 8, 16 or 32 bit -//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access -//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always -//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values -//! being written to the registers will be truncated according to this access -//! scheme. -//! -//! \note This operation is write only for the specified register. -//! This function is used to clear bits in a specific 8 bit register in -//! the ADI slave. Only bits in the selected register are affected by the -//! operation. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the base registers to clear the bits in. -//! \param ui8Val is the 8 bit one-hot encoded value specifying which -//! bits to clear in the register. -//! -//! \return None -//! -//! \sa ADI16BitsClear(), ADI32BitsClear() -// -//***************************************************************************** -__STATIC_INLINE void -ADI8BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint8_t ui8Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_CLR; - - // Set the selected bits. - HWREGB(ui32Base + ui32RegOffset + ui32Reg) = ui8Val; -} - -//***************************************************************************** -// -//! \brief Clear specific bits in two 8 bit ADI register. -//! -//! This function will clear bits in 2 registers in the analog domain. -//! The access to the registers in the analog domain is either 8, 16 or 32 bit -//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access -//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always -//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values -//! being written to the registers will be truncated according to this access -//! scheme. -//! -//! \note This operation is write only for the specified register. -//! This function is used to clear bits in 2 consecutive 8 bit registers in -//! the ADI slave. Only bits in the selected registers are affected by the -//! operation. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the base registers to clear the bits in. -//! \param ui16Val is the 16 bit one-hot encoded value specifying which -//! bits to clear in the registers. -//! -//! \return None -//! -//! \sa ADI8BitsClear(), ADI32BitsClear() -// -//***************************************************************************** -__STATIC_INLINE void -ADI16BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_CLR; - - // Set the selected bits. - HWREGH(ui32Base + ui32RegOffset + (ui32Reg & 0xFE)) = ui16Val; -} - -//***************************************************************************** -// -//! \brief Clear specific bits in four 8 bit ADI register. -//! -//! This function will clear bits in 4 registers in the analog domain. -//! The access to the registers in the analog domain is either 8, 16 or 32 bit -//! aligned, but arranged in chunks of 32 bits. You can only do 16 bit access -//! on registers 0-1 / 2-3, etc. Similarly 32 bit accesses are always -//! performed on register 0-3 / 4-7 etc. Addresses for the registers and values -//! being written to the registers will be truncated according to this access -//! scheme. -//! -//! \note This operation is write only for the specified register. -//! This function is used to clear bits in 4 consecutive 8 bit registers in -//! the ADI slave. Only bits in the selected registers are affected by the -//! operation. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is ADI base address. -//! \param ui32Reg is the base registers to clear the bits in. -//! \param ui32Val is the 32 bit one-hot encoded value specifying which -//! bits to clear in the registers. -//! -//! \return None -//! -//! \sa ADI8BitsClear(), ADI16BitsClear() -// -//***************************************************************************** -__STATIC_INLINE void -ADI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_CLR; - - // Set the selected bits. - HWREG(ui32Base + ui32RegOffset + (ui32Reg & 0xFC)) = ui32Val; -} - -//***************************************************************************** -// -//! \brief Set a value on any 4 bits inside an 8 bit register in the ADI slave. -//! -//! This function allows halfbyte (4 bit) access to the ADI slave registers. -//! The parameter \c bWriteHigh determines whether to write to the lower -//! or higher part of the 8 bit register. -//! -//! Use this function to write any value in the range 0-3 bits aligned on a -//! half byte boundary. Fx. for writing the value 0b101 to bits 1 to 3 the -//! \c ui8Val = 0xA and the \c ui8Mask = 0xE. Bit 0 will not be affected by -//! the operation, as the corresponding bit is not set in the \c ui8Mask. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is the base address of the ADI port. -//! \param ui32Reg is the Least Significant Register in the ADI slave that -//! will be affected by the write operation. -//! \param bWriteHigh defines which part of the register to write in. -//! - \c true: Write upper half byte of register. -//! - \c false: Write lower half byte of register. -//! \param ui8Mask is the mask defining which of the 4 bits that should be -//! overwritten. The mask must be defined in the lower half of the 8 bits of -//! the parameter. -//! \param ui8Val is the value to write. The value must be defined in the lower -//! half of the 8 bits of the parameter. -//! -//! \return None -//! -//! \sa ADI8SetValBit(), ADI16SetValBit -// -//***************************************************************************** -__STATIC_INLINE void -ADI4SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh, - uint8_t ui8Mask, uint8_t ui8Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - ASSERT(!(ui8Val & 0xF0)); - ASSERT(!(ui8Mask & 0xF0)); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_MASK4B + (ui32Reg << 1) + (bWriteHigh ? 1 : 0); - - // Set the selected bits. - HWREGB(ui32Base + ui32RegOffset) = (ui8Mask << 4) | ui8Val; -} - -//***************************************************************************** -// -//! \brief Set a value on any bits inside an 8 bit register in the ADI slave. -//! -//! This function allows byte (8 bit) access to the ADI slave registers. -//! -//! Use this function to write any value in the range 0-7 bits aligned on a -//! byte boundary. Fx. for writing the value 0b101 to bits 1 and 3 the -//! \c ui16Val = 0x0A and the \c ui16Mask = 0x0E. Bits 0 and 5-7 will not be affected -//! by the operation, as the corresponding bits are not set in the -//! \c ui16Mask. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is the base address of the ADI port. -//! \param ui32Reg is the Least Significant Register in the ADI slave that -//! will be affected by the write operation. -//! \param ui16Mask is the mask defining which of the 8 bit that should be -//! overwritten. The mask must be defined in the lower half of the 16 bits. -//! \param ui16Val is the value to write. The value must be defined in the lower -//! half of the 16 bits. -//! -//! \return None -//! -//! \sa ADI4SetValBit(), ADI16SetValBit() -// -//***************************************************************************** -__STATIC_INLINE void -ADI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint16_t ui16Mask, - uint16_t ui16Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - ASSERT(!(ui16Val & 0xFF00)); - ASSERT(!(ui16Mask & 0xFF00)); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_MASK8B + (ui32Reg << 1); - - // Set the selected bits. - HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val; -} - -//***************************************************************************** -// -//! \brief Set a value on any bits inside an 2 x 8 bit register aligned on a -//! half-word (byte) boundary in the ADI slave. -//! -//! This function allows 2 byte (16 bit) access to the ADI slave registers. -//! -//! Use this function to write any value in the range 0-15 bits aligned on a -//! half-word (byte) boundary. Fx. for writing the value 0b101 to bits 1 and 3 the -//! \c ui32Val = 0x000A and the \c ui32Mask = 0x000E. Bits 0 and 5-15 will not -//! be affected by the operation, as the corresponding bits are not set -//! in the \c ui32Mask. -//! -//! \note AUX_ADI4_BASE : Both the AUX module and the clock for the AUX SMPH module must be -//! enabled before calling this function. -//! -//! \param ui32Base is the base address of the ADI port. -//! \param ui32Reg is the Least Significant Register in the ADI slave that -//! will be affected by the write operation. -//! \param ui32Mask is the mask defining which of the 16 bit that should be -//! overwritten. The mask must be defined in the lower half of the 32 bits. -//! \param ui32Val is the value to write. The value must be defined in the lower -//! half of the 32 bits. -//! -//! \return None -//! -//! \sa ADI4SetValBit(), ADI8SetValBit() -// -//***************************************************************************** -__STATIC_INLINE void -ADI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, - uint32_t ui32Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(ADIBaseValid(ui32Base)); - ASSERT(ui32Reg < ADI_SLAVE_REGS); - ASSERT(!(ui32Val & 0xFFFF0000)); - ASSERT(!(ui32Mask & 0xFFFF0000)); - - // Get the correct address of the first register used for setting bits - // in the ADI slave. - ui32RegOffset = ADI_O_MASK16B + ((ui32Reg << 1) & 0xFC); - - // Set the selected bits. - HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val; -} - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __ADI_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h deleted file mode 100644 index e7eadcaf17a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/adi_doc.h +++ /dev/null @@ -1,68 +0,0 @@ -/****************************************************************************** -* Filename: adi_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup adi_api -//! @{ -//! \section sec_adi Introduction -//! \n -//! -//! \section sec_adi_api API -//! -//! The API functions can be grouped like this: -//! -//! Write: -//! - Direct (all bits): -//! - \ref ADI8RegWrite() -//! - \ref ADI16RegWrite() -//! - \ref ADI32RegWrite() -//! - Set individual bits: -//! - \ref ADI8BitsSet() -//! - \ref ADI16BitsSet() -//! - \ref ADI32BitsSet() -//! - Clear individual bits: -//! - \ref ADI8BitsClear() -//! - \ref ADI16BitsClear() -//! - \ref ADI32BitsClear() -//! - Masked: -//! - \ref ADI4SetValBit() -//! - \ref ADI8SetValBit() -//! - \ref ADI16SetValBit() -//! -//! Read: -//! - \ref ADI8RegRead() -//! - \ref ADI16RegRead() -//! - \ref ADI32RegRead() -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.c deleted file mode 100644 index c480bf7c66d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.c +++ /dev/null @@ -1,372 +0,0 @@ - -/****************************************************************************** -* Filename: crypto.c -* Revised: 2019-01-25 13:11:50 +0100 (Fri, 25 Jan 2019) -* Revision: 54285 -* -* Description: Driver for the aes functions of the crypto module -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aes.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AESStartDMAOperation - #define AESStartDMAOperation NOROM_AESStartDMAOperation - #undef AESSetInitializationVector - #define AESSetInitializationVector NOROM_AESSetInitializationVector - #undef AESWriteCCMInitializationVector - #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector - #undef AESReadTag - #define AESReadTag NOROM_AESReadTag - #undef AESVerifyTag - #define AESVerifyTag NOROM_AESVerifyTag - #undef AESWriteToKeyStore - #define AESWriteToKeyStore NOROM_AESWriteToKeyStore - #undef AESReadFromKeyStore - #define AESReadFromKeyStore NOROM_AESReadFromKeyStore - #undef AESWaitForIRQFlags - #define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags - #undef AESConfigureCCMCtrl - #define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl -#endif - - - -//***************************************************************************** -// -// Load the initialization vector. -// -//***************************************************************************** -void AESSetInitializationVector(const uint32_t *initializationVector) -{ - // Write initialization vector to the aes registers - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = initializationVector[0]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = initializationVector[1]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = initializationVector[2]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = initializationVector[3]; -} - -//***************************************************************************** -// -// Start a crypto DMA operation. -// -//***************************************************************************** -void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) -{ - if (channel0Length && channel0Addr) { - // We actually want to perform an operation. Clear any outstanding events. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; // This might need AES_IRQEN_DMA_IN_DONE as well - - while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); - - // Configure the DMA controller - enable both DMA channels. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Base address of the payload data in ext. memory. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; - - // Payload data length in bytes, equal to the cipher text length. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; - } - - if (channel1Length && channel1Addr) { - // Enable DMA channel 1. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; - - // Base address of the output data buffer. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; - - // Output data length in bytes, equal to the cipher text length. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; - } -} - -//***************************************************************************** -// -// Poll the IRQ status register and return. -// -//***************************************************************************** -uint32_t AESWaitForIRQFlags(uint32_t irqFlags) -{ - uint32_t irqTrigger = 0; - // Wait for the DMA operation to complete. Add a delay to make sure we are - // not flooding the bus with requests too much. - do { - CPUdelay(1); - } - while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | - CRYPTO_IRQSTAT_RESULT_AVAIL_M | - CRYPTO_IRQSTAT_DMA_BUS_ERR_M | - CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M))); - - // Save the IRQ trigger source - irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags; - - // Clear IRQ flags - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqTrigger; - - return irqTrigger; -} - -//***************************************************************************** -// -// Transfer a key from CM3 memory to a key store location. -// -//***************************************************************************** -uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea) -{ - // Check the arguments. - ASSERT((keyStoreArea == AES_KEY_AREA_0) || - (keyStoreArea == AES_KEY_AREA_1) || - (keyStoreArea == AES_KEY_AREA_2) || - (keyStoreArea == AES_KEY_AREA_3) || - (keyStoreArea == AES_KEY_AREA_4) || - (keyStoreArea == AES_KEY_AREA_5) || - (keyStoreArea == AES_KEY_AREA_6) || - (keyStoreArea == AES_KEY_AREA_7)); - - ASSERT((aesKeyLength == AES_128_KEY_LENGTH_BYTES) || - (aesKeyLength == AES_192_KEY_LENGTH_BYTES) || - (aesKeyLength == AES_256_KEY_LENGTH_BYTES)); - - uint32_t keySize = 0; - - switch (aesKeyLength) { - case AES_128_KEY_LENGTH_BYTES: - keySize = CRYPTO_KEYSIZE_SIZE_128_BIT; - break; - case AES_192_KEY_LENGTH_BYTES: - keySize = CRYPTO_KEYSIZE_SIZE_192_BIT; - break; - case AES_256_KEY_LENGTH_BYTES: - keySize = CRYPTO_KEYSIZE_SIZE_256_BIT; - break; - } - - // Clear any previously written key at the keyLocation - AESInvalidateKey(keyStoreArea); - - // Disable the external interrupt to stop the interrupt form propagating - // from the module to the System CPU. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE_M | CRYPTO_IRQEN_RESULT_AVAIL_M; - - // Configure master control module. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_KEY_STORE; - - // Clear any outstanding events. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQCLR_RESULT_AVAIL); - - // Configure the size of keys contained within the key store - // Do not write to the register if the correct key size is already set. - // Writing to this register causes all current keys to be invalidated. - uint32_t keyStoreKeySize = HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE); - if (keySize != keyStoreKeySize) { - HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = keySize; - } - - // Enable key to write (e.g. Key 0). - HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = 1 << keyStoreArea; - - // Total key length in bytes (16 for 1 x 128-bit key and 32 for 1 x 256-bit key). - AESStartDMAOperation(aesKey, aesKeyLength, 0, 0); - - // Wait for the DMA operation to complete. - uint32_t irqTrigger = AESWaitForIRQFlags(CRYPTO_IRQCLR_RESULT_AVAIL | CRYPTO_IRQCLR_DMA_IN_DONE | CRYPTO_IRQSTAT_DMA_BUS_ERR | CRYPTO_IRQSTAT_KEY_ST_WR_ERR); - - // Re-enable interrupts globally. - IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); - IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); - - // If we had a bus error or the key is not in the CRYPTO_O_KEYWRITTENAREA, return an error. - if ((irqTrigger & (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M)) || !(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { - // There was an error in writing to the keyStore. - return AES_KEYSTORE_ERROR; - } - else { - return AES_SUCCESS; - } -} - -//***************************************************************************** -// -// Transfer a key from the keyStoreArea to the internal buffer of the module. -// -//***************************************************************************** -uint32_t AESReadFromKeyStore(uint32_t keyStoreArea) -{ - // Check the arguments. - ASSERT((keyStoreArea == AES_KEY_AREA_0) || - (keyStoreArea == AES_KEY_AREA_1) || - (keyStoreArea == AES_KEY_AREA_2) || - (keyStoreArea == AES_KEY_AREA_3) || - (keyStoreArea == AES_KEY_AREA_4) || - (keyStoreArea == AES_KEY_AREA_5) || - (keyStoreArea == AES_KEY_AREA_6) || - (keyStoreArea == AES_KEY_AREA_7)); - - // Check if there is a valid key in the specified keyStoreArea - if (!(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (1 << keyStoreArea))) { - return AES_KEYSTORE_AREA_INVALID; - } - - // Enable keys to read (e.g. Key 0). - HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = keyStoreArea; - - // Wait until key is loaded to the AES module. - // We cannot simply poll the IRQ status as only an error is communicated through - // the IRQ status and not the completion of the transfer. - do { - CPUdelay(1); - } - while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY_M)); - - // Check for keyStore read error. - if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M)) { - return AES_KEYSTORE_ERROR; - } - else { - return AES_SUCCESS; - } -} - -//***************************************************************************** -// -// Read the tag after a completed CCM, GCM, or CBC-MAC operation. -// -//***************************************************************************** -uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength) -{ - // The intermediate array is used instead of a caller-provided one - // to enable a simple API with no unintuitive alignment or size requirements. - // This is a trade-off of stack-depth vs ease-of-use that came out on the - // ease-of-use side. - uint32_t computedTag[AES_BLOCK_SIZE / sizeof(uint32_t)]; - - // Wait until the computed tag is ready. - while (!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M)); - - // Read computed tag out from the HW registers - // Need to read out all 128 bits in four reads to correctly clear CRYPTO_AESCTL_SAVED_CONTEXT_RDY flag - computedTag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); - computedTag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); - computedTag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); - computedTag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); - - memcpy(tag, computedTag, tagLength); - - return AES_SUCCESS; -} - -//***************************************************************************** -// -// Verify the provided tag against the computed tag after a completed CCM or -// GCM operation. -// -//***************************************************************************** -uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength) -{ - uint32_t resultStatus; - // The intermediate array is allocated on the stack to ensure users do not - // point the tag they provide and the one computed at the same location. - // That would cause memcmp to compare an array against itself. We could add - // a check that verifies that the arrays are not the same. If we did that and - // modified AESReadTag to just copy all 128 bits into a provided array, - // we could save 16 bytes of stack space while making the API much more - // complicated. - uint8_t computedTag[AES_BLOCK_SIZE]; - - resultStatus = AESReadTag(computedTag, tagLength); - - if (resultStatus != AES_SUCCESS) { - return resultStatus; - } - - resultStatus = memcmp(computedTag, tag, tagLength); - - if (resultStatus != 0) { - return AES_TAG_VERIFICATION_FAILED; - } - - return AES_SUCCESS; -} - -//***************************************************************************** -// -// Configure the AES module for CCM mode -// -//***************************************************************************** -void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt) -{ - uint32_t ctrlVal = 0; - - ctrlVal = ((15 - nonceLength - 1) << CRYPTO_AESCTL_CCM_L_S); - if ( macLength >= 2 ) { - ctrlVal |= ((( macLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); - } - ctrlVal |= CRYPTO_AESCTL_CCM | - CRYPTO_AESCTL_CTR | - CRYPTO_AESCTL_SAVE_CONTEXT | - CRYPTO_AESCTL_CTR_WIDTH_128_BIT; - ctrlVal |= encrypt ? CRYPTO_AESCTL_DIR : 0; - - AESSetCtrl(ctrlVal); -} - -//***************************************************************************** -// -// Configure an IV for CCM mode of operation -// -//***************************************************************************** -void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength) -{ - union { - uint32_t word[4]; - uint8_t byte[16]; - } initializationVector = {{0}}; - - initializationVector.byte[0] = 15 - nonceLength - 1; - - memcpy(&(initializationVector.byte[1]), nonce, nonceLength); - - AESSetInitializationVector(initializationVector.word); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h deleted file mode 100644 index f1ac452f595..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes.h +++ /dev/null @@ -1,843 +0,0 @@ -/****************************************************************************** -* Filename: aes.h -* Revised: 2019-01-25 14:45:16 +0100 (Fri, 25 Jan 2019) -* Revision: 54287 -* -* Description: AES header file. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup aes_api -//! @{ -// -//***************************************************************************** - -#ifndef __AES_H__ -#define __AES_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_crypto.h" -#include "debug.h" -#include "interrupt.h" -#include "cpu.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AESStartDMAOperation NOROM_AESStartDMAOperation - #define AESSetInitializationVector NOROM_AESSetInitializationVector - #define AESWriteCCMInitializationVector NOROM_AESWriteCCMInitializationVector - #define AESReadTag NOROM_AESReadTag - #define AESVerifyTag NOROM_AESVerifyTag - #define AESWriteToKeyStore NOROM_AESWriteToKeyStore - #define AESReadFromKeyStore NOROM_AESReadFromKeyStore - #define AESWaitForIRQFlags NOROM_AESWaitForIRQFlags - #define AESConfigureCCMCtrl NOROM_AESConfigureCCMCtrl -#endif - - -//***************************************************************************** -// -// Values that can be passed to AESIntEnable, AESIntDisable, and AESIntClear -// as the intFlags parameter, and returned from AESIntStatus. -// Only AES_DMA_IN_DONE and AES_RESULT_RDY are routed to the NVIC. Check each -// function to see if it supports other interrupt status flags. -// -//***************************************************************************** -#define AES_DMA_IN_DONE CRYPTO_IRQEN_DMA_IN_DONE_M -#define AES_RESULT_RDY CRYPTO_IRQEN_RESULT_AVAIL_M -#define AES_DMA_BUS_ERR CRYPTO_IRQCLR_DMA_BUS_ERR_M -#define AES_KEY_ST_WR_ERR CRYPTO_IRQCLR_KEY_ST_WR_ERR_M -#define AES_KEY_ST_RD_ERR CRYPTO_IRQCLR_KEY_ST_RD_ERR_M - - -//***************************************************************************** -// -// General constants -// -//***************************************************************************** - -// AES module return codes -#define AES_SUCCESS 0 -#define AES_KEYSTORE_ERROR 1 -#define AES_KEYSTORE_AREA_INVALID 2 -#define AES_DMA_BUSY 3 -#define AES_DMA_ERROR 4 -#define AES_TAG_NOT_READY 5 -#define AES_TAG_VERIFICATION_FAILED 6 - -// Key store module defines -#define AES_IV_LENGTH_BYTES 16 -#define AES_TAG_LENGTH_BYTES 16 -#define AES_128_KEY_LENGTH_BYTES (128 / 8) -#define AES_192_KEY_LENGTH_BYTES (192 / 8) -#define AES_256_KEY_LENGTH_BYTES (256 / 8) - -#define AES_BLOCK_SIZE 16 - -// DMA status codes -#define AES_DMA_CHANNEL0_ACTIVE CRYPTO_DMASTAT_CH0_ACT_M -#define AES_DMA_CHANNEL1_ACTIVE CRYPTO_DMASTAT_CH1_ACT_M -#define AES_DMA_PORT_ERROR CRYPTO_DMASTAT_PORT_ERR_M - -// Crypto module operation types -#define AES_ALGSEL_AES CRYPTO_ALGSEL_AES_M -#define AES_ALGSEL_KEY_STORE CRYPTO_ALGSEL_KEY_STORE_M -#define AES_ALGSEL_TAG CRYPTO_ALGSEL_TAG_M - - -//***************************************************************************** -// -// For 128-bit keys, all 8 key area locations from 0 to 7 are valid. -// A 256-bit key requires two consecutive Key Area locations. The base key area -// may be odd. Do not attempt to write a 256-bit key to AES_KEY_AREA_7. -// -//***************************************************************************** -#define AES_KEY_AREA_0 0 -#define AES_KEY_AREA_1 1 -#define AES_KEY_AREA_2 2 -#define AES_KEY_AREA_3 3 -#define AES_KEY_AREA_4 4 -#define AES_KEY_AREA_5 5 -#define AES_KEY_AREA_6 6 -#define AES_KEY_AREA_7 7 - -//***************************************************************************** -// -// Defines for the AES-CTR mode counter width -// -//***************************************************************************** -#define AES_CTR_WIDTH_32 0x0 -#define AES_CTR_WIDTH_64 0x1 -#define AES_CTR_WIDTH_96 0x2 -#define AES_CTR_WIDTH_128 0x3 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Start a crypto DMA operation -//! -//! Enable the crypto DMA channels, configure the channel addresses, -//! and set the length of the data transfer. -//! Setting the length of the data transfer automatically starts the -//! transfer. It is also used by the hardware module as a signal to -//! begin the encryption, decryption, or MAC operation. -//! -//! \param [in] channel0Addr A pointer to the address channel 0 shall use. -//! -//! \param [in] channel0Length Length of the data in bytes to be read from or -//! written to at channel0Addr. Set to 0 to not set up -//! this channel. Permitted ranges are mode dependent -//! and displayed below. -//! - ECB: [16] -//! - CBC: [1, sizeof(RAM)] -//! - CBC-MAC: [1, sizeof(RAM)] -//! - CCM: [1, sizeof(RAM)] -//! -//! \param [out] channel1Addr A pointer to the address channel 1 shall use. -//! -//! \param [in] channel1Length Length of the data in bytes to be read from or -//! written to at channel1Addr. Set to 0 to not set up -//! this channel.Permitted ranges are mode dependent -//! and displayed below. -//! - ECB: [16] -//! - CBC: [1, sizeof(RAM)] -//! - CBC-MAC: [1, sizeof(RAM)] -//! - CCM: [1, sizeof(RAM)] -//! -//! \return None -// -//***************************************************************************** -extern void AESStartDMAOperation(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length); - -//***************************************************************************** -// -//! \brief Write the initialization vector (IV) to the crypto module. -//! -//! Depending on the mode of operation, the tag must be constructed -//! differently: -//! - CBC: No special care must be taken. Any 128-bit IV -//! (initialization vector) will suffice. -//! - CBC-MAC: IV's must be all 0's. -//! - CCM: Only 12 and 13 byte IV's are permitted. See code -//! below for formatting. -//! \code -//! uint8_t initVectorLength = 12; // Could also be 13 -//! -//! union { -//! uint32_t word[4]; -//! uint8_t byte[16]; -//! } initVector; -//! -//! uint8_t initVectorUnformatted[initVectorLength]; -//! -//! // This is the same field length value that is written to the ctrl register -//! initVector.byte[0] = L - 1; -//! -//! memcpy(&initVector.byte[1], initVectorUnformatted, initVectorLength); -//! -//! // Fill the remaining bytes with zeros -//! for (initVectorLength++; initVectorLength < sizeof(initVector.byte); initVectorLength++) { -//! initVector.byte[initVectorLength] = 0; -//! } -//! \endcode -//! -//! \param [in] initializationVector Pointer to an array with four 32-bit elements -//! to be used as initialization vector. -//! Elements of array must be word aligned in memory. -//! -//! \return None -// -//***************************************************************************** -extern void AESSetInitializationVector(const uint32_t *initializationVector); - -//***************************************************************************** -// -//! \brief Generate and load the initialization vector for a CCM operation. -//! -//! -//! \param [in] nonce Pointer to a nonce of length \c nonceLength. -//! -//! \param [in] nonceLength Number of bytes to copy from \c nonce when creating -//! the CCM IV. The L-value is also derived from it. -//! -//! \return None -// -//***************************************************************************** -extern void AESWriteCCMInitializationVector(const uint8_t *nonce, uint32_t nonceLength); - -//***************************************************************************** -// -//! \brief Read the tag out from the crypto module. -//! -//! This function copies the \c tagLength bytes from the tag calculated by the -//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag. -//! -//! \param [out] tag Pointer to an array of \c tagLength bytes. -//! -//! \param [in] tagLength Number of bytes to copy to \c tag. -//! -//! \return Returns a status code depending on the result of the transfer. -//! - \ref AES_TAG_NOT_READY if the tag is not ready yet -//! - \ref AES_SUCCESS otherwise -// -//***************************************************************************** -extern uint32_t AESReadTag(uint8_t *tag, uint32_t tagLength); - -//***************************************************************************** -// -//! \brief Verifies the provided \c tag against calculated one -//! -//! This function compares the provided tag against the tag calculated by the -//! crypto module during the last CCM, GCM, or CBC-MAC -//! -//! This function copies the \c tagLength bytes from the tag calculated by the -//! crypto module in CCM, GCM, or CBC-MAC mode to \c tag. -//! -//! \param [in] tag Pointer to an array of \c tagLength bytes. -//! -//! \param [in] tagLength Number of bytes to compare. -//! -//! \return Returns a status code depending on the result of the transfer. -//! - \ref AES_TAG_VERIFICATION_FAILED if the verification failed -//! - \ref AES_SUCCESS otherwise -// -//***************************************************************************** -extern uint32_t AESVerifyTag(const uint8_t *tag, uint32_t tagLength); - -//***************************************************************************** -// -//! \brief Transfer a key from main memory to a key area within the key store. -//! -//! The crypto DMA transfers the key and function does not return until -//! the operation completes. -//! The keyStore can only contain valid keys of one \c aesKeyLength at -//! any one point in time. The keyStore cannot contain both 128-bit and -//! 256-bit keys simultaneously. When a key of a different \c aesKeyLength -//! from the previous \c aesKeyLength is loaded, all previous keys are -//! invalidated. -//! -//! \param [in] aesKey Pointer to key. Does not need to be word-aligned. -//! -//! \param [in] aesKeyLength The key size in bytes. Currently, 128-bit, 192-bit, -//! and 256-bit keys are supported. -//! - \ref AES_128_KEY_LENGTH_BYTES -//! - \ref AES_192_KEY_LENGTH_BYTES -//! - \ref AES_256_KEY_LENGTH_BYTES -//! -//! \param [in] keyStoreArea The key store area to transfer the key to. -//! When using 128-bit keys, only the specified key store -//! area will be occupied. -//! When using 256-bit or 192-bit keys, two consecutive key areas -//! are used to store the key. -//! - \ref AES_KEY_AREA_0 -//! - \ref AES_KEY_AREA_1 -//! - \ref AES_KEY_AREA_2 -//! - \ref AES_KEY_AREA_3 -//! - \ref AES_KEY_AREA_4 -//! - \ref AES_KEY_AREA_5 -//! - \ref AES_KEY_AREA_6 -//! - \ref AES_KEY_AREA_7 -//! -//! When using 256-bit or 192-bit keys, the 8 \c keyStoreArea's are -//! split into four sets of two. Selecting any \c keyStoreArea automatically -//! occupies the second \c keyStoreArea of the tuples below: -//! -//! - (\ref AES_KEY_AREA_0, \ref AES_KEY_AREA_1) -//! - (\ref AES_KEY_AREA_2, \ref AES_KEY_AREA_3) -//! - (\ref AES_KEY_AREA_4, \ref AES_KEY_AREA_5) -//! - (\ref AES_KEY_AREA_6, \ref AES_KEY_AREA_7) -//! -//! For example: if \c keyStoreArea == \ref AES_KEY_AREA_2, -//! both \ref AES_KEY_AREA_2 and \ref AES_KEY_AREA_3 are occupied. -//! If \c keyStoreArea == \ref AES_KEY_AREA_5, both \ref AES_KEY_AREA_4 and \ref AES_KEY_AREA_5 are occupied. -//! -//! \return Returns a status code depending on the result of the transfer. -//! If there was an error in the read process itself, an error is -//! returned. -//! Otherwise, a success code is returned. -//! - \ref AES_KEYSTORE_ERROR -//! - \ref AES_SUCCESS -//! -//! \sa AESReadFromKeyStore -// -//***************************************************************************** -extern uint32_t AESWriteToKeyStore(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea); - -//***************************************************************************** -// -//! \brief Transfer a key from key store area to the internal buffers within -//! the hardware module. -//! -//! The function polls until the transfer is complete. -//! -//! \param [in] keyStoreArea The key store area to transfer the key from. When using -//! 256-bit keys, either of the occupied key areas may be -//! specified to load the key. There is no need to specify -//! the length of the key here as the key store keeps track -//! of how long a key associated with any valid key area is -//! and where is starts. -//! - \ref AES_KEY_AREA_0 -//! - \ref AES_KEY_AREA_1 -//! - \ref AES_KEY_AREA_2 -//! - \ref AES_KEY_AREA_3 -//! - \ref AES_KEY_AREA_4 -//! - \ref AES_KEY_AREA_5 -//! - \ref AES_KEY_AREA_6 -//! - \ref AES_KEY_AREA_7 -//! -//! \return Returns a status code depending on the result of the transfer. -//! When specifying a \c keyStoreArea value without a valid key in it an -//! error is returned. -//! If there was an error in the read process itself, an error is -//! returned. -//! Otherwise, a success code is returned. -//! - \ref AES_KEYSTORE_AREA_INVALID -//! - \ref AES_KEYSTORE_ERROR -//! - \ref AES_SUCCESS -//! -//! \sa AESWriteToKeyStore -// -//***************************************************************************** -extern uint32_t AESReadFromKeyStore(uint32_t keyStoreArea); - - -//***************************************************************************** -// -//! \brief Poll the interrupt status register and clear when done. -//! -//! This function polls until one of the bits in the \c irqFlags is -//! asserted. Only \ref AES_DMA_IN_DONE and \ref AES_RESULT_RDY can actually -//! trigger the interrupt line. That means that one of those should -//! always be included in \c irqFlags and will always be returned together -//! with any error codes. -//! -//! \param [in] irqFlags IRQ flags to poll and mask that the status register will be -//! masked with. May consist of any bitwise OR of the flags -//! below that includes at least one of -//! \ref AES_DMA_IN_DONE or \ref AES_RESULT_RDY : -//! - \ref AES_DMA_IN_DONE -//! - \ref AES_RESULT_RDY -//! - \ref AES_DMA_BUS_ERR -//! - \ref AES_KEY_ST_WR_ERR -//! - \ref AES_KEY_ST_RD_ERR -//! -//! \return Returns the IRQ status register masked with \c irqFlags. May be any -//! bitwise OR of the following masks: -//! - \ref AES_DMA_IN_DONE -//! - \ref AES_RESULT_RDY -//! - \ref AES_DMA_BUS_ERR -//! - \ref AES_KEY_ST_WR_ERR -//! - \ref AES_KEY_ST_RD_ERR -// -//***************************************************************************** -extern uint32_t AESWaitForIRQFlags(uint32_t irqFlags); - -//***************************************************************************** -// -//! \brief Configure AES engine for CCM operation. -//! -//! \param [in] nonceLength Length of the nonce. Must be <= 14. -//! -//! \param [in] macLength Length of the MAC. Must be <= 16. -//! -//! \param [in] encrypt Whether to set up an encrypt or decrypt operation. -//! - true: encrypt -//! - false: decrypt -//! -//! \return None -// -//***************************************************************************** -extern void AESConfigureCCMCtrl(uint32_t nonceLength, uint32_t macLength, bool encrypt); - -//***************************************************************************** -// -//! \brief Invalidate a key in the key store -//! -//! \param [in] keyStoreArea is the entry in the key store to invalidate. This -//! permanently deletes the key from the key store. -//! - \ref AES_KEY_AREA_0 -//! - \ref AES_KEY_AREA_1 -//! - \ref AES_KEY_AREA_2 -//! - \ref AES_KEY_AREA_3 -//! - \ref AES_KEY_AREA_4 -//! - \ref AES_KEY_AREA_5 -//! - \ref AES_KEY_AREA_6 -//! - \ref AES_KEY_AREA_7 -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void AESInvalidateKey(uint32_t keyStoreArea) -{ - ASSERT((keyStoreArea == AES_KEY_AREA_0) || - (keyStoreArea == AES_KEY_AREA_1) || - (keyStoreArea == AES_KEY_AREA_2) || - (keyStoreArea == AES_KEY_AREA_3) || - (keyStoreArea == AES_KEY_AREA_4) || - (keyStoreArea == AES_KEY_AREA_5) || - (keyStoreArea == AES_KEY_AREA_6) || - (keyStoreArea == AES_KEY_AREA_7)); - - // Clear any previously written key at the key location - HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << keyStoreArea); -} - -//***************************************************************************** -// -//! \brief Select type of operation -//! -//! \param [in] algorithm Flags that specify which type of operation the crypto -//! module shall perform. The flags are mutually exclusive. -//! - 0 : Reset the module -//! - \ref AES_ALGSEL_AES -//! - \ref AES_ALGSEL_TAG -//! - \ref AES_ALGSEL_KEY_STORE -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void AESSelectAlgorithm(uint32_t algorithm) -{ - ASSERT((algorithm == AES_ALGSEL_AES) || - (algorithm == AES_ALGSEL_AES | AES_ALGSEL_TAG) || - (algorithm == AES_ALGSEL_KEY_STORE)); - - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm; -} - -//***************************************************************************** -// -//! \brief Set up the next crypto module operation. -//! -//! The function uses a bitwise OR of the fields within the CRYPTO_O_AESCTL -//! register. The relevant field names have the format: -//! - CRYPTO_AESCTL_[field name] -//! -//! \param [in] ctrlMask Specifies which register fields shall be set. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void AESSetCtrl(uint32_t ctrlMask) -{ - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ctrlMask; -} - -//***************************************************************************** -// -//! \brief Specify length of the crypto operation. -//! -//! Despite specifying it here, the crypto DMA must still be -//! set up with the correct data length. -//! -//! \param [in] length Data length in bytes. If this -//! value is set to 0, only authentication of the AAD is -//! performed in CCM-mode and AESWriteAuthLength() must be set to -//! >0. -//! Range depends on the mode: -//! - ECB: [16] -//! - CBC: [1, sizeof(RAM)] -//! - CBC-MAC: [1, sizeof(RAM)] -//! - CCM: [0, sizeof(RAM)] -//! -//! \return None -//! -//! \sa AESWriteAuthLength -// -//***************************************************************************** -__STATIC_INLINE void AESSetDataLength(uint32_t length) -{ - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = length; - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; -} - -//***************************************************************************** -// -//! \brief Specify the length of the additional authentication data (AAD). -//! -//! Despite specifying it here, the crypto DMA must still be set up with -//! the correct AAD length. -//! -//! \param [in] length Specifies how long the AAD is in a CCM operation. In CCM mode, -//! set this to 0 if no AAD is required. If set to 0, -//! AESWriteDataLength() must be set to >0. -//! Range depends on the mode: -//! - ECB: Do not call. -//! - CBC: [0] -//! - CBC-MAC: [0] -//! - CCM: [0, sizeof(RAM)] -//! -//! \return None -//! -//! \sa AESWriteDataLength -// -//***************************************************************************** -__STATIC_INLINE void AESSetAuthLength(uint32_t length) -{ - HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = length; -} - -//***************************************************************************** -// -//! \brief Reset the accelerator and cancel ongoing operations -//! -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void AESReset(void) -{ - HWREG(CRYPTO_BASE + CRYPTO_O_SWRESET) = 0x00000001; -} - -//***************************************************************************** -// -//! \brief Enable individual crypto interrupt sources. -//! -//! This function enables the indicated crypto interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt. -//! Disabled sources have no effect on the processor. -//! -//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled. -//! - \ref AES_DMA_IN_DONE -//! - \ref AES_RESULT_RDY -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void AESIntEnable(uint32_t intFlags) -{ - // Check the arguments. - ASSERT((intFlags & AES_DMA_IN_DONE) || - (intFlags & AES_RESULT_RDY)); - - // Using level interrupt. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; - - // Enable the specified interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; -} - -//***************************************************************************** -// -//! \brief Disable individual crypto interrupt sources. -//! -//! This function disables the indicated crypto interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt. -//! Disabled sources have no effect on the processor. -//! -//! \param [in] intFlags is the bitwise OR of the interrupt sources to be enabled. -//! - \ref AES_DMA_IN_DONE -//! - \ref AES_RESULT_RDY -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void AESIntDisable(uint32_t intFlags) -{ - // Check the arguments. - ASSERT((intFlags & AES_DMA_IN_DONE) || - (intFlags & AES_RESULT_RDY)); - - // Disable the specified interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; -} - -//***************************************************************************** -// -//! \brief Get the current masked interrupt status. -//! -//! This function returns the masked interrupt status of the crypto module. -//! -//! \return Returns the status of the masked lines when enabled: -//! - \ref AES_DMA_IN_DONE -//! - \ref AES_RESULT_RDY -// -//***************************************************************************** -__STATIC_INLINE uint32_t AESIntStatusMasked(void) -{ - uint32_t mask; - - // Return the masked interrupt status - mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); - return(mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); -} - -//***************************************************************************** -// -//! \brief Get the current raw interrupt status. -//! -//! This function returns the raw interrupt status of the crypto module. -//! It returns both the status of the lines routed to the NVIC as well as the -//! error flags. -//! -//! \return Returns the raw interrupt status: -//! - \ref AES_DMA_IN_DONE -//! - \ref AES_RESULT_RDY -//! - \ref AES_DMA_BUS_ERR -//! - \ref AES_KEY_ST_WR_ERR -//! - \ref AES_KEY_ST_RD_ERR -// -//***************************************************************************** -__STATIC_INLINE uint32_t AESIntStatusRaw(void) -{ - // Return either the raw interrupt status - return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); -} - -//***************************************************************************** -// -//! \brief Clear crypto interrupt sources. -//! -//! The specified crypto interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in the module until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! -//! \param [in] intFlags is a bit mask of the interrupt sources to be cleared. -//! - \ref AES_DMA_IN_DONE -//! - \ref AES_RESULT_RDY -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void AESIntClear(uint32_t intFlags) -{ - // Check the arguments. - ASSERT((intFlags & AES_DMA_IN_DONE) || - (intFlags & AES_RESULT_RDY)); - - // Clear the requested interrupt sources, - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = intFlags; -} - -//***************************************************************************** -// -//! \brief Register an interrupt handler for a crypto interrupt. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; specific -//! crypto interrupts must be enabled via \ref AESIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \param handlerFxn is a pointer to the function to be called when the -//! crypto interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void AESIntRegister(void (*handlerFxn)(void)) -{ - // Register the interrupt handler. - IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, handlerFxn); - - // Enable the crypto interrupt. - IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); -} - -//***************************************************************************** -// -//! \brief Unregister an interrupt handler for a crypto interrupt. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler called when a crypto interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void AESIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AESStartDMAOperation - #undef AESStartDMAOperation - #define AESStartDMAOperation ROM_AESStartDMAOperation - #endif - #ifdef ROM_AESSetInitializationVector - #undef AESSetInitializationVector - #define AESSetInitializationVector ROM_AESSetInitializationVector - #endif - #ifdef ROM_AESWriteCCMInitializationVector - #undef AESWriteCCMInitializationVector - #define AESWriteCCMInitializationVector ROM_AESWriteCCMInitializationVector - #endif - #ifdef ROM_AESReadTag - #undef AESReadTag - #define AESReadTag ROM_AESReadTag - #endif - #ifdef ROM_AESVerifyTag - #undef AESVerifyTag - #define AESVerifyTag ROM_AESVerifyTag - #endif - #ifdef ROM_AESWriteToKeyStore - #undef AESWriteToKeyStore - #define AESWriteToKeyStore ROM_AESWriteToKeyStore - #endif - #ifdef ROM_AESReadFromKeyStore - #undef AESReadFromKeyStore - #define AESReadFromKeyStore ROM_AESReadFromKeyStore - #endif - #ifdef ROM_AESWaitForIRQFlags - #undef AESWaitForIRQFlags - #define AESWaitForIRQFlags ROM_AESWaitForIRQFlags - #endif - #ifdef ROM_AESConfigureCCMCtrl - #undef AESConfigureCCMCtrl - #define AESConfigureCCMCtrl ROM_AESConfigureCCMCtrl - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AES_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h deleted file mode 100644 index 6d156a4abf3..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aes_doc.h +++ /dev/null @@ -1,66 +0,0 @@ -/****************************************************************************** -* Filename: aes_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup aes_api -//! @{ -//! \section sec_aes Introduction -//! -//! The AES (advanced encryption standard) API provides access to the AES and key -//! store functionality of the crypto core. The SHA2 accelerator is also -//! contained within the crypto core. Hence, only one of SHA2 and AES may be -//! used at the same time. -//! This module offers hardware acceleration for several protocols using the -//! AES block cypher. The protocols below are supported by the hardware. The -//! driverlib documentation only explicitly references the most commonly used ones. -//! - ECB -//! - CBC -//! - CCM -//! - CBC-MAC -//! - GCM -//! -//! The key store is a section of crypto memory that is only accessible to the crypto module -//! and may be written to by the application via the crypto DMA. It is not possible to -//! read from the key store to main memory. Thereby, it is not possible to -//! compromise the key should the application be hacked if the original key in main -//! memory was overwritten already. -//! -//! The crypto core does not have retention and all configuration settings and -//! keys in the keystore are lost when going into standby or shutdown. -//! The typical security advantages a key store offers are not available in these -//! low power modes as the key must be saved in regular memory to reload -//! it after going into standby or shutdown. -//! Consequently, the keystore primarily serves as an interface to the AES accelerator. -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.c deleted file mode 100644 index de80801e095..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.c +++ /dev/null @@ -1,80 +0,0 @@ -/****************************************************************************** -* Filename: aon_batmon.c -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Driver for the AON Battery and Temperature Monitor -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aon_batmon.h" -#include "../inc/hw_fcfg1.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AONBatMonTemperatureGetDegC - #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC -#endif - -//***************************************************************************** -// -// AONBatMonTemperatureGetDegC() -// Returns sign extended temperature in Deg C (-256 .. +255) -// -//***************************************************************************** -int32_t -AONBatMonTemperatureGetDegC( void ) -{ - int32_t signedTemp ; // Signed extended temperature with 8 fractional bits - int32_t tempCorrection ; // Voltage dependent temp correction with 8 fractional bits - int8_t voltageSlope ; // Signed byte value representing the TEMP slope with battery voltage, in degrees C/V, with 4 fractional bits. - - // Shift left then right to sign extend the BATMON_TEMP field - signedTemp = ((((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_TEMP )) - << ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )) - >> ( 32 - AON_BATMON_TEMP_INT_W - AON_BATMON_TEMP_INT_S )); - - // Typecasting voltageSlope to int8_t prior to assignment in order to make sure sign extension works properly - // Using byte read (HWREGB) in order to make more efficient code since voltageSlope is assigned to bits[7:0] of FCFG1_O_MISC_TRIM - voltageSlope = ((int8_t)HWREGB( FCFG1_BASE + FCFG1_O_MISC_TRIM )); - tempCorrection = (( voltageSlope * (((int32_t)HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT )) - 0x300 )) >> 4 ); - - return ((( signedTemp - tempCorrection ) + 0x80 ) >> 8 ); -} - - -// See aon_batmon.h for implementation of remaining functions diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h deleted file mode 100644 index 3a9b1adb178..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_batmon.h +++ /dev/null @@ -1,306 +0,0 @@ -/****************************************************************************** -* Filename: aon_batmon.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AON Battery and Temperature -* Monitor -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aon_group -//! @{ -//! \addtogroup aonbatmon_api -//! @{ -// -//***************************************************************************** - -#ifndef __AON_BATMON_H__ -#define __AON_BATMON_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_batmon.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AONBatMonTemperatureGetDegC NOROM_AONBatMonTemperatureGetDegC -#endif - - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Enable the temperature and battery monitoring. -//! -//! This function will enable the measurements of the temperature and the -//! battery voltage. -//! -//! To speed up the measurement of the levels the measurement can be enabled -//! before configuring the battery and temperature settings. When all of the -//! AON_BATMON registers are configured, the calculation of the voltage and -//! temperature values can be enabled (the measurement will now take -//! effect/propagate to other blocks). -//! -//! It is possible to enable both at the same time, after the AON_BATMON -//! registers are configured, but then the first values will be ready at a -//! later point compared to the scenario above. -//! -//! \note Temperature and battery voltage measurements are not done in -//! parallel. The measurement cycle is controlled by a hardware Finite State -//! Machine. First the temperature and then the battery voltage each taking -//! one cycle to complete. However, if the comparator measuring the battery -//! voltage detects a change on the reference value, a new measurement of the -//! battery voltage only is performed immediately after. This has no impact on -//! the cycle count. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONBatMonEnable(void) -{ - // Enable the measurements. - HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = - AON_BATMON_CTL_CALC_EN | - AON_BATMON_CTL_MEAS_EN; -} - -//***************************************************************************** -// -//! \brief Disable the temperature and battery monitoring. -//! -//! This function will disable the measurements of the temperature and the -//! battery voltage. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONBatMonDisable(void) -{ - // Disable the measurements. - HWREG(AON_BATMON_BASE + AON_BATMON_O_CTL) = 0; -} - - -//***************************************************************************** -// -//! \brief Get the current temperature measurement as a signed value in Deg Celsius. -//! -//! This function returns an calibrated and rounded value in degree Celsius. -//! The temperature measurements are updated every cycle. -//! -//! \note The temperature drifts slightly depending on the battery voltage. -//! This function compensates for this drift and returns a calibrated temperature. -//! -//! \note Use the function AONBatMonNewTempMeasureReady() to test for a new measurement. -//! -//! \return Returns signed integer part of temperature in Deg C (-256 .. +255) -//! -//! \sa AONBatMonNewTempMeasureReady() -// -//***************************************************************************** -extern int32_t AONBatMonTemperatureGetDegC( void ); - -//***************************************************************************** -// -//! \brief Get the battery monitor measurement. -//! -//! This function will return the current battery monitor measurement. -//! The battery voltage measurements are updated every cycle. -//! -//! \note The returned value is NOT sign-extended! -//! -//! \note Use the function \ref AONBatMonNewBatteryMeasureReady() to test for -//! a change in measurement. -//! -//! \return Returns the current battery monitor value of the battery voltage -//! measurement in a format size <3.8> in units of volt. -//! -//! \sa AONBatMonNewBatteryMeasureReady() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONBatMonBatteryVoltageGet(void) -{ - uint32_t ui32CurrentBattery; - - ui32CurrentBattery = HWREG(AON_BATMON_BASE + AON_BATMON_O_BAT); - - // Return the current battery voltage measurement. - return (ui32CurrentBattery >> AON_BATMON_BAT_FRAC_S); -} - -//***************************************************************************** -// -//! \brief Check if battery monitor measurement has changed. -//! -//! This function checks if a new battery monitor value is available. If the -//! measurement value has \b changed since last clear the function returns \c true. -//! -//! If the measurement has changed the function will automatically clear the -//! status bit. -//! -//! \note It is always possible to read out the current value of the -//! battery level using AONBatMonBatteryVoltageGet() but this function can be -//! used to check if the measurement has changed. -//! -//! \return Returns \c true if the measurement value has changed and \c false -//! otherwise. -//! -//! \sa AONBatMonNewTempMeasureReady(), AONBatMonBatteryVoltageGet() -// -//***************************************************************************** -__STATIC_INLINE bool -AONBatMonNewBatteryMeasureReady(void) -{ - bool bStatus; - - // Check the status bit. - bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) & - AON_BATMON_BATUPD_STAT ? true : false; - - // Clear status bit if set. - if(bStatus) - { - HWREG(AON_BATMON_BASE + AON_BATMON_O_BATUPD) = 1; - } - - // Return status. - return (bStatus); -} - -//***************************************************************************** -// -//! \brief Check if temperature monitor measurement has changed. -//! -//! This function checks if a new temperature value is available. If the -//! measurement value has \b changed since last clear the function returns \c true. -//! -//! If the measurement has changed the function will automatically clear the -//! status bit. -//! -//! \note It is always possible to read out the current value of the -//! temperature using \ref AONBatMonTemperatureGetDegC() -//! but this function can be used to check if the measurement has changed. -//! -//! \return Returns \c true if the measurement value has changed and \c false -//! otherwise. -//! -//! \sa AONBatMonNewBatteryMeasureReady(), AONBatMonTemperatureGetDegC() -// -//***************************************************************************** -__STATIC_INLINE bool -AONBatMonNewTempMeasureReady(void) -{ - bool bStatus; - - // Check the status bit. - bStatus = HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) & - AON_BATMON_TEMPUPD_STAT ? true : false; - - // Clear status bit if set. - if(bStatus) - { - HWREG(AON_BATMON_BASE + AON_BATMON_O_TEMPUPD) = 1; - } - - // Return status. - return (bStatus); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AONBatMonTemperatureGetDegC - #undef AONBatMonTemperatureGetDegC - #define AONBatMonTemperatureGetDegC ROM_AONBatMonTemperatureGetDegC - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AON_BATMON_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.c deleted file mode 100644 index cb699a1523b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.c +++ /dev/null @@ -1,180 +0,0 @@ -/****************************************************************************** -* Filename: aon_event.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the AON Event fabric. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aon_event.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AONEventMcuWakeUpSet - #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet - #undef AONEventMcuWakeUpGet - #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet - #undef AONEventMcuSet - #define AONEventMcuSet NOROM_AONEventMcuSet - #undef AONEventMcuGet - #define AONEventMcuGet NOROM_AONEventMcuGet -#endif - -//***************************************************************************** -// -// Select event source for the specified MCU wakeup programmable event -// -//***************************************************************************** -void -AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc) -{ - uint32_t ui32Shift ; - uint32_t ui32Mask ; - uint32_t ui32RegAdr ; - - // Check the arguments. - ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 )) - ASSERT( ui32EventSrc <= AON_EVENT_NONE ); - - ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 ); - ui32Mask = ( 0x3F << ui32Shift ); - ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL ); - if ( ui32MCUWUEvent > 3 ) { - ui32RegAdr += 4; - } - HWREG( ui32RegAdr ) = ( HWREG( ui32RegAdr ) & ( ~ui32Mask )) | ( ui32EventSrc << ui32Shift ); -} - -//***************************************************************************** -// -// Get event source for the specified MCU wakeup programmable event -// -//***************************************************************************** -uint32_t -AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent) -{ - uint32_t ui32Shift ; - uint32_t ui32RegAdr ; - - // Check the arguments. - ASSERT(( ui32MCUWUEvent >= AON_EVENT_MCU_WU0 ) && ( ui32MCUWUEvent <= AON_EVENT_MCU_WU7 )) - - ui32Shift = (( ui32MCUWUEvent & 3 ) << 3 ); - ui32RegAdr = ( AON_EVENT_BASE + AON_EVENT_O_MCUWUSEL ); - if ( ui32MCUWUEvent > 3 ) { - ui32RegAdr += 4; - } - return (( HWREG( ui32RegAdr ) >> ui32Shift ) & 0x3F ); -} - -//***************************************************************************** -// -// Select event source for the specified programmable event forwarded to the -// MCU event fabric -// -//***************************************************************************** -void -AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc) -{ - uint32_t ui32Ctrl; - - // Check the arguments. - ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || - (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || - (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); - ASSERT(ui32EventSrc <= AON_EVENT_NONE); - - ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); - - if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) - { - ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S; - } - else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) - { - ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S; - } - else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) - { - ui32Ctrl &= ~(AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S; - } - - HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL) = ui32Ctrl; -} - -//***************************************************************************** -// -// Get source for the specified programmable event forwarded to the MCU event -// fabric. -// -//***************************************************************************** -uint32_t -AONEventMcuGet(uint32_t ui32MCUEvent) -{ - uint32_t ui32EventSrc; - - // Check the arguments. - ASSERT((ui32MCUEvent == AON_EVENT_MCU_EVENT0) || - (ui32MCUEvent == AON_EVENT_MCU_EVENT1) || - (ui32MCUEvent == AON_EVENT_MCU_EVENT2)); - - ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_EVTOMCUSEL); - - if(ui32MCUEvent == AON_EVENT_MCU_EVENT0) - { - return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M) >> - AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S); - } - else if(ui32MCUEvent == AON_EVENT_MCU_EVENT1) - { - return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M) >> - AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S); - } - else if(ui32MCUEvent == AON_EVENT_MCU_EVENT2) - { - return((ui32EventSrc & AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M) >> - AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S); - } - - // Should never get to this statement, but suppress warning. - ASSERT(0); - return(0); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h deleted file mode 100644 index 999844a0d4c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event.h +++ /dev/null @@ -1,564 +0,0 @@ -/****************************************************************************** -* Filename: aon_event.h -* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) -* Revision: 49506 -* -* Description: Defines and prototypes for the AON Event fabric. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aon_group -//! @{ -//! \addtogroup aonevent_api -//! @{ -// -//***************************************************************************** - -#ifndef __AON_EVENT_H__ -#define __AON_EVENT_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_event.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AONEventMcuWakeUpSet NOROM_AONEventMcuWakeUpSet - #define AONEventMcuWakeUpGet NOROM_AONEventMcuWakeUpGet - #define AONEventMcuSet NOROM_AONEventMcuSet - #define AONEventMcuGet NOROM_AONEventMcuGet -#endif - -//***************************************************************************** -// -// Event sources for the event AON fabric. -// Note: Events are level-triggered active high -// -//***************************************************************************** -#define AON_EVENT_IOEV_MCU_WU 0 // Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU -#define AON_EVENT_AUX_TIMER2_EV0 1 // Event 0 from AUX Timer2 -#define AON_EVENT_AUX_TIMER2_EV1 2 // Event 1 from AUX Timer2 -#define AON_EVENT_AUX_TIMER2_EV2 3 // Event 2 from AUX Timer2 -#define AON_EVENT_AUX_TIMER2_EV3 4 // Event 3 from AUX Timer2 -#define AON_EVENT_BATMON_BATT_UL 5 // BATMON event: Battery level above upper limit -#define AON_EVENT_BATMON_BATT_LL 6 // BATMON event: Battery level below lower limit -#define AON_EVENT_BATMON_TEMP_UL 7 // BATMON event: Temperature level above upper limit -#define AON_EVENT_BATMON_TEMP_LL 8 // BATMON event: Temperature level below lower limit -#define AON_EVENT_BATMON_COMBINED 9 // Combined event from BATMON -#define AON_EVENT_IO 32 // Edge detect on any DIO. Edge detect is enabled and configured in IOC. - // Event ID 33 is reserved for future use - // Event ID 34 is reserved for future use -#define AON_EVENT_RTC_CH0 35 // RTC channel 0 -#define AON_EVENT_RTC_CH1 36 // RTC channel 1 -#define AON_EVENT_RTC_CH2 37 // RTC channel 2 -#define AON_EVENT_RTC_CH0_DLY 38 // RTC channel 0 - delayed event -#define AON_EVENT_RTC_CH1_DLY 39 // RTC channel 1 - delayed event -#define AON_EVENT_RTC_CH2_DLY 40 // RTC channel 2 - delayed event -#define AON_EVENT_RTC_COMB_DLY 41 // RTC combined delayed event -#define AON_EVENT_RTC_UPD 42 // RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -#define AON_EVENT_JTAG 43 // JTAG generated event -#define AON_EVENT_AUX_SWEV0 44 // AUX Software triggered event #0 -#define AON_EVENT_AUX_SWEV1 45 // AUX Software triggered event #1 -#define AON_EVENT_AUX_SWEV2 46 // AUX Software triggered event #2 -#define AON_EVENT_AUX_COMPA 47 // Comparator A triggered (synchronized in AUX) -#define AON_EVENT_AUX_COMPB 48 // Comparator B triggered (synchronized in AUX) -#define AON_EVENT_AUX_ADC_DONE 49 // ADC conversion completed -#define AON_EVENT_AUX_TDC_DONE 50 // TDC completed or timed out -#define AON_EVENT_AUX_TIMER0_EV 51 // Timer 0 event -#define AON_EVENT_AUX_TIMER1_EV 52 // Timer 1 event -#define AON_EVENT_BATMON_TEMP 53 // BATMON temperature update event -#define AON_EVENT_BATMON_VOLT 54 // BATMON voltage update event -#define AON_EVENT_AUX_COMPB_ASYNC 55 // Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -#define AON_EVENT_AUX_COMPB_ASYNC_N 56 // Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B - // Event ID 57-62 is reserved for future use -#define AON_EVENT_NONE 63 // No event, always low - -// Keeping backward compatibility until major revision number is incremented -#define AON_EVENT_RTC0 ( AON_EVENT_RTC_CH0 ) - -//***************************************************************************** -// -// Values that can be passed to AONEventMCUWakeUpSet() and returned -// by AONEventMCUWakeUpGet(). -// -//***************************************************************************** -#define AON_EVENT_MCU_WU0 0 // Programmable MCU wake-up event 0 -#define AON_EVENT_MCU_WU1 1 // Programmable MCU wake-up event 1 -#define AON_EVENT_MCU_WU2 2 // Programmable MCU wake-up event 2 -#define AON_EVENT_MCU_WU3 3 // Programmable MCU wake-up event 3 -#define AON_EVENT_MCU_WU4 4 // Programmable MCU wake-up event 4 -#define AON_EVENT_MCU_WU5 5 // Programmable MCU wake-up event 5 -#define AON_EVENT_MCU_WU6 6 // Programmable MCU wake-up event 6 -#define AON_EVENT_MCU_WU7 7 // Programmable MCU wake-up event 7 - -//***************************************************************************** -// -// Values that can be passed to AONEventMcuSet() and AONEventMcuGet() -// -//***************************************************************************** -#define AON_EVENT_MCU_EVENT0 0 // Programmable event source fed to MCU event fabric (first of 3) -#define AON_EVENT_MCU_EVENT1 1 // Programmable event source fed to MCU event fabric (second of 3) -#define AON_EVENT_MCU_EVENT2 2 // Programmable event source fed to MCU event fabric (third of 3) - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Select event source for the specified MCU wake-up programmable event. -//! -//! The AON event fabric has several programmable events that can wake up the MCU. -//! -//! \note The programmable event sources are effectively OR'ed together -//! to form a single wake-up event. -//! -//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources. -//! - \ref AON_EVENT_MCU_WU0 -//! - \ref AON_EVENT_MCU_WU1 -//! - \ref AON_EVENT_MCU_WU2 -//! - \ref AON_EVENT_MCU_WU3 -//! - \ref AON_EVENT_MCU_WU4 -//! - \ref AON_EVENT_MCU_WU5 -//! - \ref AON_EVENT_MCU_WU6 -//! - \ref AON_EVENT_MCU_WU7 -//! \param ui32EventSrc is an event source for the event AON fabric. -//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU -//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 -//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit -//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit -//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit -//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit -//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \return None -//! -//! \sa AONEventMcuWakeUpGet() -// -//***************************************************************************** -extern void AONEventMcuWakeUpSet(uint32_t ui32MCUWUEvent, - uint32_t ui32EventSrc); - -//***************************************************************************** -// -//! \brief Get event source for the specified MCU wake-up programmable event. -//! -//! \param ui32MCUWUEvent is one of the programmable MCU wake-up event sources. -//! - \ref AON_EVENT_MCU_WU0 -//! - \ref AON_EVENT_MCU_WU1 -//! - \ref AON_EVENT_MCU_WU2 -//! - \ref AON_EVENT_MCU_WU3 -//! - \ref AON_EVENT_MCU_WU4 -//! - \ref AON_EVENT_MCU_WU5 -//! - \ref AON_EVENT_MCU_WU6 -//! - \ref AON_EVENT_MCU_WU7 -//! -//! \return Returns the event source for the event AON fabric. -//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU -//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 -//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit -//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit -//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit -//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit -//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \sa AONEventMcuWakeUpSet() -// -//***************************************************************************** -extern uint32_t AONEventMcuWakeUpGet(uint32_t ui32MCUWUEvent); - -//***************************************************************************** -// -//! \brief Select event source for the specified programmable event forwarded to the -//! MCU event fabric. -//! -//! The AON event fabric has a total of three programmable events that can -//! be forwarded to the MCU event fabric. -//! -//! \note The three programmable event sources are forwarded to the MCU Event -//! Fabric as: -//! - AON_PROG0 -//! - AON_PROG1 -//! - AON_PROG2 -//! -//! \param ui32MCUEvent is one of three programmable events forwarded to the -//! MCU event fabric. -//! - \ref AON_EVENT_MCU_EVENT0 -//! - \ref AON_EVENT_MCU_EVENT1 -//! - \ref AON_EVENT_MCU_EVENT2 -//! \param ui32EventSrc is an event source for the event AON fabric. -//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU -//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 -//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit -//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit -//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit -//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit -//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \return None -//! -//! \sa AONEventMcuGet() -// -//***************************************************************************** -extern void AONEventMcuSet(uint32_t ui32MCUEvent, uint32_t ui32EventSrc); - -//***************************************************************************** -// -//! \brief Get source for the specified programmable event forwarded to the MCU event -//! fabric. -//! -//! The AON event fabric has a total of three programmable events that can -//! be forwarded to the MCU event fabric. -//! -//! \param ui32MCUEvent is one of three programmable events forwarded to the -//! MCU event fabric. -//! - \ref AON_EVENT_MCU_EVENT0 -//! - \ref AON_EVENT_MCU_EVENT1 -//! - \ref AON_EVENT_MCU_EVENT2 -//! -//! \return Returns the event source for the event AON fabric. -//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU -//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 -//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit -//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit -//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit -//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit -//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \sa AONEventMcuSet() -// -//***************************************************************************** -extern uint32_t AONEventMcuGet(uint32_t ui32MCUEvent); - -//***************************************************************************** -// -//! \brief Select event source forwarded to AON Real Time Clock (RTC). -//! -//! A programmable event can be forwarded to the AON real time clock -//! for triggering a capture event on RTC channel 1. -//! -//! \param ui32EventSrc is an event source for the event AON fabric. -//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU -//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 -//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit -//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit -//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit -//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit -//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \return None -//! -//! \sa AONEventRtcGet() -// -//***************************************************************************** -__STATIC_INLINE void -AONEventRtcSet(uint32_t ui32EventSrc) -{ - uint32_t ui32Ctrl; - - // Check the arguments. - ASSERT(ui32EventSrc <= AON_EVENT_NONE); - - ui32Ctrl = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL); - ui32Ctrl &= ~(AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M); - ui32Ctrl |= (ui32EventSrc & 0x3f) << AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S; - - HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL) = ui32Ctrl; -} - -//***************************************************************************** -// -//! \brief Get event source forwarded to AON Real Time Clock (RTC). -//! -//! A programmable event can be forwarded to the AON real time clock -//! for triggering a capture event on RTC channel 1. -//! -//! \return Returns the event source to the event AON fabric. -//! - \ref AON_EVENT_IOEV_MCU_WU : Edge detect event from DIOs which have enabled contribution to IOEV_MCU_WU -//! - \ref AON_EVENT_AUX_TIMER2_EV0 : Event 0 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV1 : Event 1 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV2 : Event 2 from AUX Timer2 -//! - \ref AON_EVENT_AUX_TIMER2_EV3 : Event 3 from AUX Timer2 -//! - \ref AON_EVENT_BATMON_BATT_UL : BATMON event: Battery level above upper limit -//! - \ref AON_EVENT_BATMON_BATT_LL : BATMON event: Battery level below lower limit -//! - \ref AON_EVENT_BATMON_TEMP_UL : BATMON event: Temperature level above upper limit -//! - \ref AON_EVENT_BATMON_TEMP_LL : BATMON event: Temperature level below lower limit -//! - \ref AON_EVENT_BATMON_COMBINED : Combined event from BATMON -//! - \ref AON_EVENT_IO : Edge detect on any DIO. Edge detect is enabled and configured in IOC. -//! - \ref AON_EVENT_RTC_CH0 : RTC channel 0 -//! - \ref AON_EVENT_RTC_CH1 : RTC channel 1 -//! - \ref AON_EVENT_RTC_CH2 : RTC channel 2 -//! - \ref AON_EVENT_RTC_CH0_DLY : RTC channel 0 - delayed event -//! - \ref AON_EVENT_RTC_CH1_DLY : RTC channel 1 - delayed event -//! - \ref AON_EVENT_RTC_CH2_DLY : RTC channel 2 - delayed event -//! - \ref AON_EVENT_RTC_COMB_DLY : RTC combined delayed event -//! - \ref AON_EVENT_RTC_UPD : RTC Update Tick (16 kHz signal, i.e. event line toggles value every 32 kHz clock period) -//! - \ref AON_EVENT_JTAG : JTAG generated event -//! - \ref AON_EVENT_AUX_SWEV0 : AUX Software triggered event #0 -//! - \ref AON_EVENT_AUX_SWEV1 : AUX Software triggered event #1 -//! - \ref AON_EVENT_AUX_SWEV2 : AUX Software triggered event #2 -//! - \ref AON_EVENT_AUX_COMPA : Comparator A triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_COMPB : Comparator B triggered (synchronized in AUX) -//! - \ref AON_EVENT_AUX_ADC_DONE : ADC conversion completed -//! - \ref AON_EVENT_AUX_TDC_DONE : TDC completed or timed out -//! - \ref AON_EVENT_AUX_TIMER0_EV : Timer 0 event -//! - \ref AON_EVENT_AUX_TIMER1_EV : Timer 1 event -//! - \ref AON_EVENT_BATMON_TEMP : BATMON temperature update event -//! - \ref AON_EVENT_BATMON_VOLT : BATMON voltage update event -//! - \ref AON_EVENT_AUX_COMPB_ASYNC : Comparator B triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_AUX_COMPB_ASYNC_N : Comparator B not triggered. Asynchronous signal directly from the AUX Comparator B -//! - \ref AON_EVENT_NONE : No event, always low -//! -//! \sa AONEventRtcSet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONEventRtcGet(void) -{ - uint32_t ui32EventSrc; - - // Return the active event. - ui32EventSrc = HWREG(AON_EVENT_BASE + AON_EVENT_O_RTCSEL); - - return ((ui32EventSrc & AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M) >> - AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AONEventMcuWakeUpSet - #undef AONEventMcuWakeUpSet - #define AONEventMcuWakeUpSet ROM_AONEventMcuWakeUpSet - #endif - #ifdef ROM_AONEventMcuWakeUpGet - #undef AONEventMcuWakeUpGet - #define AONEventMcuWakeUpGet ROM_AONEventMcuWakeUpGet - #endif - #ifdef ROM_AONEventMcuSet - #undef AONEventMcuSet - #define AONEventMcuSet ROM_AONEventMcuSet - #endif - #ifdef ROM_AONEventMcuGet - #undef AONEventMcuGet - #define AONEventMcuGet ROM_AONEventMcuGet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AON_EVENT_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h deleted file mode 100644 index 5210bbfc71b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_event_doc.h +++ /dev/null @@ -1,58 +0,0 @@ -/****************************************************************************** -* Filename: aon_event_doc.h -* Revised: 2017-08-09 16:56:05 +0200 (Wed, 09 Aug 2017) -* Revision: 49506 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup aonevent_api -//! @{ -//! \section sec_aonevent Introduction -//! -//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and -//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers -//! to the AON event fabric. For more information on MCU event fabric, see [MCU event API](@ref event_api). -//! -//! The AON event fabric is a configurable combinatorial router between AON event sources and event -//! subscribers in both AON and MCU domains. The API to control the AON event fabric configuration -//! can be grouped based on the event subscriber to configure: -//! -//! - Wake-up events. -//! - MCU wake-up event -//! - @ref AONEventMcuWakeUpSet() -//! - @ref AONEventMcuWakeUpGet() -//! - AON RTC receives a single programmable event line from the AON event fabric. For more information, see [AON RTC API](@ref aonrtc_api). -//! - @ref AONEventRtcSet() -//! - @ref AONEventRtcGet() -//! - MCU event fabric receives a number of programmable event lines from the AON event fabric. For more information, see [MCU event API](@ref event_api). -//! - @ref AONEventMcuSet() -//! - @ref AONEventMcuGet() -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.c deleted file mode 100644 index c0c9b3c4a88..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.c +++ /dev/null @@ -1,39 +0,0 @@ -/****************************************************************************** -* Filename: aon_ioc.c -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Driver for the AON IO Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aon_ioc.h" diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h deleted file mode 100644 index 13ab449602b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc.h +++ /dev/null @@ -1,292 +0,0 @@ -/****************************************************************************** -* Filename: aon_ioc.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AON IO Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aon_group -//! @{ -//! \addtogroup aonioc_api -//! @{ -// -//***************************************************************************** - -#ifndef __AON_IOC_H__ -#define __AON_IOC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_ioc.h" -#include "debug.h" - -//***************************************************************************** -// -// Defines for the drive strength -// -//***************************************************************************** -#define AONIOC_DRV_STR_1 0x00000000 // Lowest drive strength -#define AONIOC_DRV_STR_2 0x00000001 -#define AONIOC_DRV_STR_3 0x00000003 -#define AONIOC_DRV_STR_4 0x00000002 -#define AONIOC_DRV_STR_5 0x00000006 -#define AONIOC_DRV_STR_6 0x00000007 -#define AONIOC_DRV_STR_7 0x00000005 -#define AONIOC_DRV_STR_8 0x00000004 // Highest drive strength - -#define AONIOC_DRV_LVL_MIN (AON_IOC_O_IOSTRMIN) -#define AONIOC_DRV_LVL_MED (AON_IOC_O_IOSTRMED) -#define AONIOC_DRV_LVL_MAX (AON_IOC_O_IOSTRMAX) - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Configure drive strength values for the manual drive strength options. -//! -//! This function defines the general drive strength settings for the non-AUTO -//! drive strength options in the MCU IOC. Consequently, if all IOs are using the -//! automatic drive strength option this function has no effect. -//! -//! Changing the drive strength values affects all current modes (Low-Current, -//! High-Current, and Extended-Current). Current mode for individual IOs is set in -//! MCU IOC by \ref IOCIODrvStrengthSet(). -//! -//! \note Values are Gray encoded. Simply incrementing values to increase drive -//! strength will not work. -//! -//! \param ui32DriveLevel -//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. Default value is selected -//! to give minimum 2/4/8 mA @3.3V for Low-Current mode, High-Current mode, -//! and Extended-Current mode respectively. -//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. Default value is selected -//! to give minimum 2/4/8 mA @2.5V for Low-Current mode, High-Current mode, -//! and Extended-Current mode respectively. -//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. Default value is selected -//! to give minimum 2/4/8 mA @1.8V for Low-Current mode, High-Current mode, -//! and Extended-Current mode respectively. -//! \param ui32DriveStrength sets the value used by IOs configured as non-AUTO drive strength in MCU IOC. -//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength -//! - \ref AONIOC_DRV_STR_2 -//! - \ref AONIOC_DRV_STR_3 -//! - \ref AONIOC_DRV_STR_4 -//! - \ref AONIOC_DRV_STR_5 -//! - \ref AONIOC_DRV_STR_6 -//! - \ref AONIOC_DRV_STR_7 -//! - \ref AONIOC_DRV_STR_8 : Highest drive strength -//! -//! \return None -//! -//! \sa \ref AONIOCDriveStrengthGet(), \ref IOCIODrvStrengthSet() -// -//***************************************************************************** -__STATIC_INLINE void -AONIOCDriveStrengthSet(uint32_t ui32DriveLevel, uint32_t ui32DriveStrength) -{ - ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) || - (ui32DriveLevel == AONIOC_DRV_LVL_MED) || - (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); - ASSERT((ui32DriveStrength == AONIOC_DRV_STR_1) || - (ui32DriveStrength == AONIOC_DRV_STR_2) || - (ui32DriveStrength == AONIOC_DRV_STR_3) || - (ui32DriveStrength == AONIOC_DRV_STR_4) || - (ui32DriveStrength == AONIOC_DRV_STR_5) || - (ui32DriveStrength == AONIOC_DRV_STR_6) || - (ui32DriveStrength == AONIOC_DRV_STR_7) || - (ui32DriveStrength == AONIOC_DRV_STR_8)); - - // Set the drive strength. - HWREG(AON_IOC_BASE + ui32DriveLevel) = ui32DriveStrength; -} - -//***************************************************************************** -// -//! \brief Get a specific drive level setting for all IOs. -//! -//! Use this function to read the drive strength setting for a specific -//! IO drive level. -//! -//! \note Values are Gray encoded. -//! -//! \param ui32DriveLevel is the specific drive level to get the setting for. -//! - \ref AONIOC_DRV_LVL_MIN : Minimum drive strength option. -//! - \ref AONIOC_DRV_LVL_MED : Medium drive strength option. -//! - \ref AONIOC_DRV_LVL_MAX : Maximum drive strength option. -//! -//! \return Returns the requested drive strength level setting for all IOs. -//! Possible values are: -//! - \ref AONIOC_DRV_STR_1 : Lowest drive strength -//! - \ref AONIOC_DRV_STR_2 -//! - \ref AONIOC_DRV_STR_3 -//! - \ref AONIOC_DRV_STR_4 -//! - \ref AONIOC_DRV_STR_5 -//! - \ref AONIOC_DRV_STR_6 -//! - \ref AONIOC_DRV_STR_7 -//! - \ref AONIOC_DRV_STR_8 : Highest drive strength -//! -//! \sa AONIOCDriveStrengthSet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONIOCDriveStrengthGet(uint32_t ui32DriveLevel) -{ - // Check the arguments. - ASSERT((ui32DriveLevel == AONIOC_DRV_LVL_MIN) || - (ui32DriveLevel == AONIOC_DRV_LVL_MED) || - (ui32DriveLevel == AONIOC_DRV_LVL_MAX)); - - // Return the drive strength value. - return( HWREG(AON_IOC_BASE + ui32DriveLevel) ); -} - -//***************************************************************************** -// -//! \brief Freeze the IOs. -//! -//! To retain the values of the output IOs during a powerdown/shutdown of the -//! device all IO latches in the AON domain should be frozen in their current -//! state. This ensures that software can regain control of the IOs after a -//! reboot without the IOs first falling back to the default values (i.e. input -//! and no pull). -//! -//! \return None -//! -//! \sa AONIOCFreezeDisable() -// -//***************************************************************************** -__STATIC_INLINE void -AONIOCFreezeEnable(void) -{ - // Set the AON IO latches as static. - HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = 0x0; -} - -//***************************************************************************** -// -//! \brief Un-freeze the IOs. -//! -//! When rebooting the chip after it has entered powerdown/shutdown mode, the -//! software can regain control of the IOs by setting the IO latches as -//! transparent. The IOs should not be unfrozen before software has restored -//! the functionality of the IO. -//! -//! \return None -//! -//! \sa AONIOCFreezeEnable() -// -//***************************************************************************** -__STATIC_INLINE void -AONIOCFreezeDisable(void) -{ - // Set the AON IOC latches as transparent. - HWREG(AON_IOC_BASE + AON_IOC_O_IOCLATCH) = AON_IOC_IOCLATCH_EN; -} - -//***************************************************************************** -// -//! \brief Disable the 32kHz clock output. -//! -//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality -//! in the IOC is bypassed. Therefore, the programmer needs to call this -//! function to disable the clock output. -//! -//! \return None -//! -//! \sa AONIOC32kHzOutputEnable() -// -//***************************************************************************** -__STATIC_INLINE void -AONIOC32kHzOutputDisable(void) -{ - // Disable the LF clock output. - HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = AON_IOC_CLK32KCTL_OE_N; -} - -//***************************************************************************** -// -//! \brief Enable the 32kHz clock output. -//! -//! When outputting a 32 kHz clock on an IO, the output enable/disable functionality -//! in the IOC is bypassed. Therefore, the programmer needs to call this -//! function to enable the clock output. -//! -//! \return None -//! -//! \sa AONIOC32kHzOutputDisable() -// -//***************************************************************************** -__STATIC_INLINE void -AONIOC32kHzOutputEnable(void) -{ - // Enable the LF clock output. - HWREG(AON_IOC_BASE + AON_IOC_O_CLK32KCTL) = 0x0; -} - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AON_IOC_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h deleted file mode 100644 index 3d379780c46..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_ioc_doc.h +++ /dev/null @@ -1,65 +0,0 @@ -/****************************************************************************** -* Filename: aon_ioc_doc.h -* Revised: 2016-03-30 11:01:30 +0200 (Wed, 30 Mar 2016) -* Revision: 45969 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup aonioc_api -//! @{ -//! \section sec_aonioc Introduction -//! -//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO). -//! The IOC consists of two APIs: -//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it. -//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc. -//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is -//! routed to a DIO for external use. -//! -//! For more information on the MCU IOC see the [IOC API](\ref ioc_api). -//! -//! \section sec_aonioc_api API -//! -//! The API functions can be grouped like this: -//! -//! Freeze IOs while MCU domain is powered down: -//! - \ref AONIOCFreezeEnable() -//! - \ref AONIOCFreezeDisable() -//! -//! Output LF clock to a DIO: -//! - \ref AONIOC32kHzOutputEnable() -//! - \ref AONIOC32kHzOutputDisable() -//! -//! Configure the value of drive strength for the three manual MCU IOC settings (MIN, MED, MAX): -//! - \ref AONIOCDriveStrengthSet() -//! - \ref AONIOCDriveStrengthGet() -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.c deleted file mode 100644 index b680fd73e4f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.c +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: aon_pmctl.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the AON Power-Management Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aon_pmctl.h" - -// See aon_pmctl.h for implementation diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h deleted file mode 100644 index ec6bf2e53b5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl.h +++ /dev/null @@ -1,201 +0,0 @@ -/****************************************************************************** -* Filename: aon_pmctl.h -* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) -* Revision: 50156 -* -* Description: Defines and prototypes for the AON Power-Management Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aon_group -//! @{ -//! \addtogroup aonpmctl_api -//! @{ -// -//***************************************************************************** - -#ifndef __AON_PMCTL_H__ -#define __AON_PMCTL_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_pmctl.h" -#include "debug.h" - -//***************************************************************************** -// -// Defines that can be be used to enable/disable the retention on the SRAM -// banks during power off of the MCU BUS domain. The defines can be passed to -// AONPMCTLMcuSRamConfig) . -// -//***************************************************************************** -#define MCU_RAM_RET_NONE AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE -#define MCU_RAM_RET_LVL1 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1 -#define MCU_RAM_RET_LVL2 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 -#define MCU_RAM_RET_LVL3 AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 -#define MCU_RAM_RET_FULL AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL - -//***************************************************************************** -// -// Defines for all the different power modes available through -// AONPMCTLPowerStatusGet() . -// -//***************************************************************************** -#define AONPMCTL_JTAG_POWER_ON AON_PMCTL_PWRSTAT_JTAG_PD_ON - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Configure the retention on the block SRAM in the MCU BUS domain. -//! -//! MCU SRAM is partitioned into 5 banks of 16 KB each. The SRAM supports -//! retention on all 5 banks during MCU BUS domain power off. The retention -//! on the SRAM can be turned on and off. Use this function to enable the -//! retention on the banks. -//! -//! If a group of banks is not represented in the parameter \c ui32Retention -//! then the retention will be disabled for that bank group during MCU BUS -//! domain power off. -//! -//! \note Retention on all SRAM banks is enabled by default. Configuration of -//! individual SRAM banks is not supported. Configuration is only supported -//! on bank group level. -//! -//! \param ui32Retention defines which groups of SRAM banks to enable/disable -//! retention on: -//! - \ref MCU_RAM_RET_NONE Retention is disabled -//! - \ref MCU_RAM_RET_LVL1 Retention on for banks 0 and 1 -//! - \ref MCU_RAM_RET_LVL2 Retention on for banks 0, 1 and 2 -//! - \ref MCU_RAM_RET_LVL3 Retention on for banks 0, 1, 2 and 3 -//! - \ref MCU_RAM_RET_FULL Retention on for all five banks -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONPMCTLMcuSRamRetConfig(uint32_t ui32Retention) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT((ui32Retention == MCU_RAM_RET_NONE) || - (ui32Retention == MCU_RAM_RET_LVL1) || - (ui32Retention == MCU_RAM_RET_LVL2) || - (ui32Retention == MCU_RAM_RET_LVL3) || - (ui32Retention == MCU_RAM_RET_FULL)); - - // Configure the retention. - ui32Reg = HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RAMCFG) & ~AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M; - ui32Reg |= ui32Retention; - HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RAMCFG) = ui32Reg; -} - -//***************************************************************************** -// -//! \brief Get the power status of the Always On (AON) domain. -//! -//! This function reports the power management status in AON. -//! -//! \return Returns the current power status of the device as a bitwise OR'ed -//! combination of these values: -//! - \ref AONPMCTL_JTAG_POWER_ON -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONPMCTLPowerStatusGet(void) -{ - // Return the power status. - return (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRSTAT)); -} - - -//***************************************************************************** -// -//! \brief Request power off of the JTAG domain. -//! -//! The JTAG domain is automatically powered up on if a debugger is connected. -//! If a debugger is not connected this function can be used to power off the -//! JTAG domain. -//! -//! \note Achieving the lowest power modes (shutdown/powerdown) requires the -//! JTAG domain to be turned off. In general the JTAG domain should never be -//! powered in production code. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONPMCTLJtagPowerOff(void) -{ - // Request the power off of the JTAG domain - HWREG(AON_PMCTL_BASE + AON_PMCTL_O_JTAGCFG) = 0; -} - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AON_PMCTL_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h deleted file mode 100644 index 0f44256b25e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_pmctl_doc.h +++ /dev/null @@ -1,99 +0,0 @@ -/****************************************************************************** -* Filename: aon_pmctl_doc.h -* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) -* Revision: 50165 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup aonpmctl_api -//! @{ -//! \section sec_aonpmctl Introduction -//! -//! This API provides a set of functions for using the AON Power Management -//! Controller module (AON_PMCTL). -//! -//! The AON_PMCTL module contains the following functional options: -//! - Selection of voltage regulator for the digital domain. -//! - Control of retention of MCU SRAM banks during power off of the BUS power domain. -//! - Control of power and retention of AUX SRAM. -//! - Control of power, reset, and clock for the following domains: -//! - MCU_VD -//! - JTAG_PD -//! - AUX -//! - Control of the recharging of VDDR while in uLDO state. -//! - Control of the generation of a periodic request to the OSCDIG to initiate -//! an XOSC_HF amplitude calibration sequence. -//! -//! The main clock for the AON_PMCTL module is the 2 MHz SCLK MF clock. -//! -//! AON_PMCTL supports the MCU_voltage domain with a 48 MHz clock (SCLK_HF) that is divided -//! and gated by the PRCM module before being distributed to all modules in the -//! MCU voltage domain. -//! -//! The AON_PMCTL controls the SCLK_HF clock to ensure that it is available in the -//! Active and Idle power modes, and disabled for all other modes. SCLK_HF is not -//! allowed in uLDO state since it uses too much power. -//! The SCLK_HF clock is also available for the AUX module in the Active and Idle -//! power modes. -//! -//! The AON_PMCTL selects the clock source for the AUX domain in the different -//! power modes. -//! -//! Main functionality to control power management of the JTAG power domain is -//! supported. Note that no clock control is supported, as the JTAG is clocked -//! on the TCK clock. -//! -//! -//! \section sec_aonpmctl_api API -//! -//! The API functions can be grouped like this: -//! -//! Functions to perform status report: -//! - \ref AONPMCTLPowerStatusGet() -//! -//! -//! Functions to perform device configuration: -//! - \ref AONPMCTLJtagPowerOff() -//! - \ref AONPMCTLMcuSRamRetConfig() -//! -//! Please note that due to legacy software compatibility some functionalities controlled -//! by the AON Power Management Controller module are supported through the APIs of -//! the [System Controller](@ref sysctrl_api) and [Power Controller](@ref pwrctrl_api). Relevant functions are: -//! - \ref PowerCtrlSourceGet() -//! - \ref PowerCtrlSourceSet() -//! - \ref PowerCtrlResetSourceGet() -//! - \ref SysCtrl_DCDC_VoltageConditionalControl() -//! - \ref SysCtrlClockLossResetDisable() -//! - \ref SysCtrlClockLossResetEnable() -//! - \ref SysCtrlSystemReset() -//! - \ref SysCtrlResetSourceGet() -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.c deleted file mode 100644 index 7187f84deb6..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.c +++ /dev/null @@ -1,77 +0,0 @@ -/****************************************************************************** -* Filename: aon_rtc.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the AON RTC. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aon_rtc.h" -#include "cpu.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AONRTCCurrent64BitValueGet - #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet -#endif - - -//***************************************************************************** -// -// Get the current 64-bit value of the RTC counter. -// -//***************************************************************************** -uint64_t -AONRTCCurrent64BitValueGet( void ) -{ - union { - uint64_t returnValue ; - uint32_t secAndSubSec[ 2 ] ; - } currentRtc ; - uint32_t ui32SecondSecRead ; - - // Reading SEC both before and after SUBSEC in order to detect if SEC incremented while reading SUBSEC - // If SEC incremented, we can't be sure which SEC the SUBSEC belongs to, so repeating the sequence then. - do { - currentRtc.secAndSubSec[ 1 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); - currentRtc.secAndSubSec[ 0 ] = HWREG( AON_RTC_BASE + AON_RTC_O_SUBSEC ); - ui32SecondSecRead = HWREG( AON_RTC_BASE + AON_RTC_O_SEC ); - } while ( currentRtc.secAndSubSec[ 1 ] != ui32SecondSecRead ); - - return ( currentRtc.returnValue ); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h deleted file mode 100644 index 6e131d2f34b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc.h +++ /dev/null @@ -1,931 +0,0 @@ -/****************************************************************************** -* Filename: aon_rtc.h -* Revised: 2017-08-16 15:13:43 +0200 (Wed, 16 Aug 2017) -* Revision: 49593 -* -* Description: Defines and prototypes for the AON RTC -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aon_group -//! @{ -//! \addtogroup aonrtc_api -//! @{ -// -//***************************************************************************** - -#ifndef __AON_RTC_H__ -#define __AON_RTC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aon_rtc.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AONRTCCurrent64BitValueGet NOROM_AONRTCCurrent64BitValueGet -#endif - -//***************************************************************************** -// -// Values that can be passed to most of the AON_RTC APIs as the ui32Channel -// parameter. -// -//***************************************************************************** -#define AON_RTC_CH_NONE 0x0 // RTC No channel -#define AON_RTC_CH0 0x1 // RTC Channel 0 -#define AON_RTC_CH1 0x2 // RTC Channel 1 -#define AON_RTC_CH2 0x4 // RTC Channel 2 -#define AON_RTC_ACTIVE 0x8 // RTC Active - -//***************************************************************************** -// -// Values that can be passed to AONRTCConfigDelay as the ui32Delay parameter. -// -//***************************************************************************** -#define AON_RTC_CONFIG_DELAY_NODELAY 0 // NO DELAY -#define AON_RTC_CONFIG_DELAY_1 1 // Delay of 1 clk cycle -#define AON_RTC_CONFIG_DELAY_2 2 // Delay of 2 clk cycles -#define AON_RTC_CONFIG_DELAY_4 3 // Delay of 4 clk cycles -#define AON_RTC_CONFIG_DELAY_8 4 // Delay of 8 clk cycles -#define AON_RTC_CONFIG_DELAY_16 5 // Delay of 16 clk cycles -#define AON_RTC_CONFIG_DELAY_32 6 // Delay of 32 clk cycles -#define AON_RTC_CONFIG_DELAY_48 7 // Delay of 48 clk cycles -#define AON_RTC_CONFIG_DELAY_64 8 // Delay of 64 clk cycles -#define AON_RTC_CONFIG_DELAY_80 9 // Delay of 80 clk cycles -#define AON_RTC_CONFIG_DELAY_96 10 // Delay of 96 clk cycles -#define AON_RTC_CONFIG_DELAY_112 11 // Delay of 112 clk cycles -#define AON_RTC_CONFIG_DELAY_128 12 // Delay of 128 clk cycles -#define AON_RTC_CONFIG_DELAY_144 13 // Delay of 144 clk cycles - -//***************************************************************************** -// -// Values that can be passed to AONRTCSetModeCH1 as the ui32Mode -// parameter. -// -//***************************************************************************** -#define AON_RTC_MODE_CH1_CAPTURE 1 // Capture mode -#define AON_RTC_MODE_CH1_COMPARE 0 // Compare Mode - -//***************************************************************************** -// -// Values that can be passed to AONRTCSetModeCH2 as the ui32Mode -// parameter. -// -//***************************************************************************** -#define AON_RTC_MODE_CH2_CONTINUOUS 1 // Continuous mode -#define AON_RTC_MODE_CH2_NORMALCOMPARE 0 // Normal compare mode - -//***************************************************************************** -// -// Mutliplication factor for converting from seconds to corresponding time in -// the "CompareValue" format. -// The factor correspond to the compare value format described in the registers -// \ref AON_RTC_O_CH0CMP, \ref AON_RTC_O_CH1CMP and \ref AON_RTC_O_CH2CMP. -// Example1: -// 4 milliseconds in CompareValue format can be written like this: -// ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT )) -// Example2: -// 4 seconds in CompareValue format can be written like this: -// ( 4 * FACTOR_SEC_TO_COMP_VAL_FORMAT ) -// -//***************************************************************************** -#define FACTOR_SEC_TO_COMP_VAL_FORMAT 0x00010000 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Enable the RTC. -//! -//! Enable the AON Real Time Clock. -//! -//! \note Event generation for each of the three channels must also be enabled -//! using the function AONRTCChannelEnable(). -//! -//! \return None -//! -//! \sa AONRTCChannelEnable() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCEnable(void) -{ - // Enable RTC. - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Disable the RTC. -//! -//! Disable the AON Real Time Clock. -//! -//! \note Event generation for each of the three channels can also be disabled -//! using the function AONRTCChannelDisable(). -//! -//! \return None -//! -//! \sa AONRTCChannelDisable() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCDisable(void) -{ - // Disable RTC - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN) = 0; -} - -//***************************************************************************** -// -//! \brief Reset the RTC. -//! -//! Reset the AON Real Time Clock. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCReset(void) -{ - // Reset RTC. - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_RESET_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Check if the RTC is active (enabled). -//! -//! \return Returns the status of the RTC. -//! - false : RTC is disabled -//! - true : RTC is enabled -// -//***************************************************************************** -__STATIC_INLINE bool -AONRTCActive(void) -{ - // Read if RTC is enabled - return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CTL, AON_RTC_CTL_EN_BITN)); -} - -//***************************************************************************** -// -//! \brief Check if an RTC channel is active (enabled). -//! -//! \param ui32Channel specifies the RTC channel to check status of. -//! Parameter must be one (and only one) of the following: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! -//! \return Returns the status of the requested channel: -//! - false : Channel is disabled -//! - true : Channel is enabled -// -//***************************************************************************** -__STATIC_INLINE bool -AONRTCChannelActive(uint32_t ui32Channel) -{ - uint32_t uint32Status = 0; - - if(ui32Channel & AON_RTC_CH0) - { - uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN); - } - - if(ui32Channel & AON_RTC_CH1) - { - uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN); - } - - if(ui32Channel & AON_RTC_CH2) - { - uint32Status = HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN); - } - - return(uint32Status); -} - -//***************************************************************************** -// -//! \brief Configure Event Delay for the RTC. -//! -//! Each event from the three individual channels can generate a delayed -//! event. The delay time for these events is set using this function. -//! The delay is measured in clock cycles. -//! -//! \note There is only one delay setting shared for all three channels. -//! -//! \param ui32Delay specifies the delay time for delayed events. -//! Parameter must be one of the following: -//! - \ref AON_RTC_CONFIG_DELAY_NODELAY -//! - \ref AON_RTC_CONFIG_DELAY_1 -//! - \ref AON_RTC_CONFIG_DELAY_2 -//! - \ref AON_RTC_CONFIG_DELAY_4 -//! - \ref AON_RTC_CONFIG_DELAY_8 -//! - \ref AON_RTC_CONFIG_DELAY_16 -//! - \ref AON_RTC_CONFIG_DELAY_32 -//! - \ref AON_RTC_CONFIG_DELAY_48 -//! - \ref AON_RTC_CONFIG_DELAY_64 -//! - \ref AON_RTC_CONFIG_DELAY_80 -//! - \ref AON_RTC_CONFIG_DELAY_96 -//! - \ref AON_RTC_CONFIG_DELAY_112 -//! - \ref AON_RTC_CONFIG_DELAY_128 -//! - \ref AON_RTC_CONFIG_DELAY_144 -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCDelayConfig(uint32_t ui32Delay) -{ - uint32_t ui32Cfg; - - // Check the arguments. - ASSERT(ui32Delay <= AON_RTC_CONFIG_DELAY_144); - - - ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); - ui32Cfg &= ~(AON_RTC_CTL_EV_DELAY_M); - ui32Cfg |= (ui32Delay << AON_RTC_CTL_EV_DELAY_S); - - HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg; -} - -//***************************************************************************** -// -//! \brief Configure the source of the combined event. -//! -//! A combined delayed event can be generated from a combination of the three -//! delayed events. Delayed events form the specified channels are OR'ed -//! together to generate the combined event. -//! -//! \param ui32Channels specifies the channels that are to be used for -//! generating the combined event. -//! The parameter must be the bitwise OR of any of the following: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! - \ref AON_RTC_CH_NONE -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCCombinedEventConfig(uint32_t ui32Channels) -{ - uint32_t ui32Cfg; - - // Check the arguments. - ASSERT( (ui32Channels & (AON_RTC_CH0 | AON_RTC_CH1 | AON_RTC_CH2)) || - (ui32Channels == AON_RTC_CH_NONE) ); - - ui32Cfg = HWREG(AON_RTC_BASE + AON_RTC_O_CTL); - ui32Cfg &= ~(AON_RTC_CTL_COMB_EV_MASK_M); - ui32Cfg |= (ui32Channels << AON_RTC_CTL_COMB_EV_MASK_S); - - HWREG(AON_RTC_BASE + AON_RTC_O_CTL) = ui32Cfg; -} - -//***************************************************************************** -// -//! \brief Clear event from a specified channel. -//! -//! In case of an active event from the specified channel, the event -//! will be cleared (de-asserted). -//! -//! \param ui32Channel clears the event from one or more RTC channels: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCEventClear(uint32_t ui32Channel) -{ - // Check the arguments. - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH0; - } - - if(ui32Channel & AON_RTC_CH1) - { - HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH1; - } - - if(ui32Channel & AON_RTC_CH2) - { - HWREG(AON_RTC_BASE + AON_RTC_O_EVFLAGS) = AON_RTC_EVFLAGS_CH2; - } -} - -//***************************************************************************** -// -//! \brief Get event status for a specified channel. -//! -//! In case of an active event from the specified channel, -//! this call will return \c true otherwise \c false. -//! -//! \param ui32Channel specifies the channel from which to query the event state. -//! The parameter must be one (and only one) of the following: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! -//! \return Returns \c true if an event has occurred for the given channel, -//! otherwise \c false. -// -//***************************************************************************** -__STATIC_INLINE bool -AONRTCEventGet(uint32_t ui32Channel) -{ - uint32_t uint32Event = 0; - - // Check the arguments. - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH0_BITN); - } - - if(ui32Channel & AON_RTC_CH1) - { - uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH1_BITN); - } - - if(ui32Channel & AON_RTC_CH2) - { - uint32Event = HWREGBITW(AON_RTC_BASE + AON_RTC_O_EVFLAGS, AON_RTC_EVFLAGS_CH2_BITN); - } - - return(uint32Event); -} - -//***************************************************************************** -// -//! \brief Get integer part (seconds) of RTC free-running timer. -//! -//! Get the value in seconds of RTC free-running timer, i.e. the integer part. -//! The fractional part is returned from a call to AONRTCFractionGet(). -//! -//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead -//! of this function if the <16.16> format is sufficient. -//! -//! \note To read a consistent pair of integer and fractional parts, -//! \ref AONRTCSecGet() must be called first to trigger latching of the -//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts -//! must be disabled to ensure that these operations are performed atomically. -//! -//! \return Returns the integer part of RTC free running timer. -//! -//! \sa \ref AONRTCFractionGet() \ref AONRTCCurrentCompareValueGet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCSecGet(void) -{ - // The following read gets the seconds, but also latches the fractional - // part. - return(HWREG(AON_RTC_BASE + AON_RTC_O_SEC)); -} - -//***************************************************************************** -// -//! \brief Get fractional part (sub-seconds) of RTC free-running timer. -//! -//! Get the value of the fractional part of RTC free-running timer, i.e. the -//! sub-second part. -//! -//! \note It is recommended to use \ref AONRTCCurrentCompareValueGet() instead -//! of this function if the <16.16> format is sufficient. -//! -//! \note To read a consistent pair of integer and fractional parts, -//! \ref AONRTCSecGet() must be called first to trigger latching of the -//! fractional part, which is then read by \ref AONRTCFractionGet(). Interrupts -//! must be disabled to ensure that these operations are performed atomically. -//! -//! \return Returns the fractional part of RTC free running timer. -//! -//! \sa \ref AONRTCSecGet() \ref AONRTCCurrentCompareValueGet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCFractionGet(void) -{ - // Note1: It is recommended to use AON RTCCurrentCompareValueGet() instead - // of this function if the <16.16> format is sufficient. - // Note2: AONRTCSecGet() must be called before this function to get a - // consistent reading. - // Note3: Interrupts must be disabled between the call to AONRTCSecGet() and this - // call since there are interrupt functions that reads AON_RTC_O_SEC - return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSEC)); -} - -//***************************************************************************** -// -//! \brief Get the sub second increment of the RTC. -//! -//! Get the value of the sub-second increment which is added to the RTC -//! absolute time on every clock tick. -//! -//! \note For a precise and temperature independent LF clock (e.g. an LF XTAL) -//! this value would stay the same across temperature. For temperatue -//! dependent clock sources like an RC oscillator, this value will change -//! over time if the application includes functionality for doing temperature -//! compensation of the RTC clock source. The default value corresponds to a -//! LF clock frequency of exactly 32.768 kHz. -//! -//! \return Returns the sub-second increment of the RTC added to the overall -//! value on every RTC clock tick. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCSubSecIncrGet(void) -{ - return(HWREG(AON_RTC_BASE + AON_RTC_O_SUBSECINC)); -} - -//***************************************************************************** -// -//! \brief Set operational mode of channel 1. -//! -//! Set the operational mode of channel 1. It can be capture or compare mode. -//! In capture mode, an external event causes the value of the free running -//! counter to be stored, to remember the time of the event. -//! -//! \note The default mode is compare. -//! -//! \param ui32Mode specifies the mode for channel 1. -//! The parameter must be one of the following: -//! - \ref AON_RTC_MODE_CH1_CAPTURE -//! - \ref AON_RTC_MODE_CH1_COMPARE -//! -//! \return None -//! -//! \sa AONRTCModeCh1Get() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCModeCh1Set(uint32_t ui32Mode) -{ - // Check the arguments. - ASSERT((ui32Mode == AON_RTC_MODE_CH1_CAPTURE) || - (ui32Mode == AON_RTC_MODE_CH1_COMPARE)); - - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN) = ui32Mode; -} - -//***************************************************************************** -// -//! \brief Get operational mode of channel 1. -//! -//! Get the operational mode of channel 1. It can be capture or compare mode. -//! In capture mode, an external event causes the value of the free running -//! counter to be stored, to remember the time of the event. -//! -//! \return Returns the operational mode of channel 1, one of: -//! - \ref AON_RTC_MODE_CH1_CAPTURE -//! - \ref AON_RTC_MODE_CH1_COMPARE -//! -//! \sa AONRTCModeCh1Set() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCModeCh1Get(void) -{ - return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_CAPT_EN_BITN)); -} - -//***************************************************************************** -// -//! \brief Set operational mode of channel 2. -//! -//! Set the operational mode of channel 2. It can be in continuous compare -//! mode or normal compare mode. -//! In continuous mode, a value is automatically incremented to the channel 2 -//! compare register, upon a channel 2 compare event. This allows channel 2 to -//! generate a series of completely equidistant events. -//! The increment value is set by the AONRTCIncValueCh2Set() call. -//! -//! \note The default mode is normal compare. -//! -//! \param ui32Mode specifies the mode for channel 2. -//! The parameter must be one of the following: -//! - \ref AON_RTC_MODE_CH2_CONTINUOUS -//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE -//! -//! \return None -//! -//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCModeCh2Set(uint32_t ui32Mode) -{ - // Check the arguments. - ASSERT((ui32Mode == AON_RTC_MODE_CH2_CONTINUOUS) || - (ui32Mode == AON_RTC_MODE_CH2_NORMALCOMPARE)); - - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN) = ui32Mode; -} - -//***************************************************************************** -// -//! \brief Get operational mode of channel 2. -//! -//! Get the operational mode of channel 2. It can be in continuous compare -//! mode or normal compare mode. -//! In continuous mode, a value is automatically incremented to the channel 2 -//! compare register, upon a channel 2 compare event. This allows channel 2 to -//! generate a series of completely equidistant events. -//! The increment value is set by the AONRTCIncValueCh2Set() call. -//! -//! \return Returns the operational mode of channel 2, i.e. one of: -//! - \ref AON_RTC_MODE_CH2_CONTINUOUS -//! - \ref AON_RTC_MODE_CH2_NORMALCOMPARE -//! -//! \sa AONRTCIncValueCh2Set(), AONRTCIncValueCh2Get() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCModeCh2Get(void) -{ - return(HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_CONT_EN_BITN)); -} - -//***************************************************************************** -// -//! \brief Enable event operation for the specified channel. -//! -//! Enable the event generation for the specified channel. -//! -//! \note The RTC free running clock must also be enabled globally using the -//! AONRTCEnable() call. -//! -//! \param ui32Channel specifies one or more channels to enable: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! -//! \return None -//! -//! \sa AONRTCEnable() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCChannelEnable(uint32_t ui32Channel) -{ - // Check the arguments. - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 1; - } - - if(ui32Channel & AON_RTC_CH1) - { - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 1; - } - - if(ui32Channel & AON_RTC_CH2) - { - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 1; - } -} - -//***************************************************************************** -// -//! \brief Disable event operation for the specified channel. -//! -//! Disable the event generation for the specified channel. -//! -//! \note The RTC free running clock can also be disabled globally using the -//! AONRTCDisable() call. -//! -//! \param ui32Channel specifies one or more channels to disable: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! -//! \return None -//! -//! \sa AONRTCDisable() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCChannelDisable(uint32_t ui32Channel) -{ - // Check the arguments. - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH0_EN_BITN) = 0; - } - - if(ui32Channel & AON_RTC_CH1) - { - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH1_EN_BITN) = 0; - } - - if(ui32Channel & AON_RTC_CH2) - { - HWREGBITW(AON_RTC_BASE + AON_RTC_O_CHCTL, AON_RTC_CHCTL_CH2_EN_BITN) = 0; - } -} - -//***************************************************************************** -// -//! \brief Set the compare value for the given channel. -//! -//! Set compare value for the specified channel. -//! -//! The format of the compare value is a 16 bit integer and 16 bit fractional -//! format <16 sec.16 subsec>. The current value of the RTC counter -//! can be retrieved in a format compatible to the compare register using -//! \ref AONRTCCurrentCompareValueGet() -//! -//! \param ui32Channel specifies one or more channels to set compare value for: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! \param ui32CompValue is the compare value to set for the specified channel. -//! - Format: <16 sec.16 subsec> -//! -//! \return None -//! -//! \sa AONRTCCurrentCompareValueGet() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCCompareValueSet(uint32_t ui32Channel, uint32_t ui32CompValue) -{ - // Check the arguments. - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP) = ui32CompValue; - } - - if(ui32Channel & AON_RTC_CH1) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP) = ui32CompValue; - } - - if(ui32Channel & AON_RTC_CH2) - { - HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP) = ui32CompValue; - } -} - -//***************************************************************************** -// -//! \brief Get the compare value for the given channel. -//! -//! Get compare value for the specified channel. -//! -//! \param ui32Channel specifies a channel. -//! The parameter must be one (and only one) of the following: -//! - \ref AON_RTC_CH0 -//! - \ref AON_RTC_CH1 -//! - \ref AON_RTC_CH2 -//! -//! \return Returns the stored compare value for the given channel. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCCompareValueGet(uint32_t ui32Channel) -{ - uint32_t ui32Value = 0; - - // Check the arguments - ASSERT((ui32Channel == AON_RTC_CH0) || - (ui32Channel == AON_RTC_CH1) || - (ui32Channel == AON_RTC_CH2)); - - if(ui32Channel & AON_RTC_CH0) - { - ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH0CMP); - } - - if(ui32Channel & AON_RTC_CH1) - { - ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH1CMP); - } - - if(ui32Channel & AON_RTC_CH2) - { - ui32Value = HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMP); - } - - return(ui32Value); -} - -//***************************************************************************** -// -//! \brief Get the current value of the RTC counter in a format that matches -//! RTC compare values. -//! -//! The compare value registers contains 16 integer and 16 fractional bits. -//! This function will return the current value of the RTC counter in an -//! identical format. -//! -//! \return Returns the current value of the RTC counter in a <16.16> format -//! (SEC[15:0].SUBSEC[31:16]). -//! -//! \sa \ref AONRTCCompareValueSet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCCurrentCompareValueGet( void ) -{ - return ( HWREG( AON_RTC_BASE + AON_RTC_O_TIME )); -} - -//***************************************************************************** -// -//! \brief Get the current 64-bit value of the RTC counter. -//! -//! \note Reading SEC both before and after SUBSEC in order to detect if SEC -//! incremented while reading SUBSEC. If SEC incremented, we can't be sure -//! which SEC the SUBSEC belongs to, so repeating the sequence then. -//! -//! \return Returns the current value of the RTC counter in a 64-bits format -//! (SEC[31:0].SUBSEC[31:0]). -// -//***************************************************************************** -extern uint64_t AONRTCCurrent64BitValueGet(void); - -//***************************************************************************** -// -//! \brief Set the channel 2 increment value when operating in continuous mode. -//! -//! Set the channel 2 increment value when operating in continuous mode. -//! The specified value is automatically incremented to the channel 2 compare -//! register, upon a channel 2 compare event. This allows channel 2 to generate -//! a series of completely equidistant events. -//! -//! \param ui32IncValue is the increment value when operating in continuous mode. -//! -//! \return None -//! -//! \sa AONRTCIncValueCh2Get() -// -//***************************************************************************** -__STATIC_INLINE void -AONRTCIncValueCh2Set(uint32_t ui32IncValue) -{ - HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC) = ui32IncValue; -} - -//***************************************************************************** -// -//! \brief Get the channel2 increment value when operating in continuous mode. -//! -//! Get the channel 2 increment value, when channel 2 is operating in -//! continuous mode. -//! This value is automatically incremented to the channel 2 compare -//! register, upon a channel 2 compare event. This allows channel 2 to -//! generate a series of completely equidistant events. -//! -//! \return Returns the channel 2 increment value when operating in continuous -//! mode. -//! -//! \sa AONRTCIncValueCh2Set() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCIncValueCh2Get(void) -{ - return(HWREG(AON_RTC_BASE + AON_RTC_O_CH2CMPINC)); -} - -//***************************************************************************** -// -//! \brief Get the channel 1 capture value. -//! -//! Get the channel 1 capture value. -//! The upper 16 bits of the returned value is the lower 16 bits of the -//! integer part of the RTC timer. The lower 16 bits of the returned part -//! is the upper 16 bits of the fractional part. -//! -//! \return Returns the channel 1 capture value. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AONRTCCaptureValueCh1Get(void) -{ - return(HWREG(AON_RTC_BASE + AON_RTC_O_CH1CAPT)); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AONRTCCurrent64BitValueGet - #undef AONRTCCurrent64BitValueGet - #define AONRTCCurrent64BitValueGet ROM_AONRTCCurrent64BitValueGet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AON_RTC_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h deleted file mode 100644 index e5be29f0267..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aon_rtc_doc.h +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: aon_rtc_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup aonrtc_api -//! @{ -//! \section sec_aonrtc Introduction -//! -//! \note If using TI-RTOS then only TI-RTOS is allowed to configure the RTC timer! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.c deleted file mode 100644 index b1b3f198f73..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.c +++ /dev/null @@ -1,337 +0,0 @@ -/****************************************************************************** -* Filename: aux_adc.c -* Revised: 2017-11-20 14:31:35 +0100 (Mon, 20 Nov 2017) -* Revision: 50315 -* -* Description: Driver for the AUX Time to Digital Converter interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aux_adc.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aux_sysif.h" -#include "../inc/hw_fcfg1.h" -#include "adi.h" -#include "event.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AUXADCDisable - #define AUXADCDisable NOROM_AUXADCDisable - #undef AUXADCEnableAsync - #define AUXADCEnableAsync NOROM_AUXADCEnableAsync - #undef AUXADCEnableSync - #define AUXADCEnableSync NOROM_AUXADCEnableSync - #undef AUXADCDisableInputScaling - #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling - #undef AUXADCFlushFifo - #define AUXADCFlushFifo NOROM_AUXADCFlushFifo - #undef AUXADCReadFifo - #define AUXADCReadFifo NOROM_AUXADCReadFifo - #undef AUXADCPopFifo - #define AUXADCPopFifo NOROM_AUXADCPopFifo - #undef AUXADCGetAdjustmentGain - #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain - #undef AUXADCGetAdjustmentOffset - #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset - #undef AUXADCValueToMicrovolts - #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts - #undef AUXADCMicrovoltsToValue - #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue - #undef AUXADCAdjustValueForGainAndOffset - #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset - #undef AUXADCUnadjustValueForGainAndOffset - #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset -#endif - -//***************************************************************************** -// -// Disables the ADC -// -//***************************************************************************** -void -AUXADCDisable(void) -{ - // Disable the ADC reference - ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, ADI_4_AUX_ADCREF0_EN_M | ADI_4_AUX_ADCREF0_REF_ON_IDLE_M | ADI_4_AUX_ADCREF0_SRC_M); - - // Assert reset and disable the ADC - ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M | ADI_4_AUX_ADC0_SMPL_MODE_M | ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M); - - // Ensure that scaling is enabled by default before next use of the ADC - ADI8BitsClear(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); - - // Flush the FIFO before disabling the clocks - HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) - HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) - - // Disable the ADC clock (no need to wait since IOB_WUC_ADCCLKCTL_ACK goes low immediately) - HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = 0; - - // Disable the ADC data interface - HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = 0; -} - -//***************************************************************************** -// -// Enables the ADC for asynchronous operation -// -//***************************************************************************** -void -AUXADCEnableAsync(uint32_t refSource, uint32_t trigger) -{ - // Enable the ADC reference, with the following options: - // - SRC: Set when using relative reference - // - REF_ON_IDLE: Always cleared since there is no idle state in asynchronous operation - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, refSource | ADI_4_AUX_ADCREF0_EN_M); - - // Enable the ADC clock - HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M; - while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M)); - - // Enable the ADC data interface - if (trigger == AUXADC_TRIGGER_MANUAL) { - // Manual trigger: No need to configure event routing from GPT - HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN; - } else { - // GPT trigger: Configure event routing via MCU_EV to the AUX domain - HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; - HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; - } - - // Configure the ADC - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_SMPL_MODE_M); - - // Release reset and enable the ADC - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); -} - -//***************************************************************************** -// -// Enables the ADC for synchronous operation -// -//***************************************************************************** -void -AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger) -{ - // Enable the ADC reference, with the following options: - // - SRC: Set when using relative reference - // - REF_ON_IDLE: Set when using fixed reference and sample time < 21.3 us - uint8_t adcref0 = refSource | ADI_4_AUX_ADCREF0_EN_M; - if (!refSource && (sampleTime < AUXADC_SAMPLE_TIME_21P3_US)) { - adcref0 |= ADI_4_AUX_ADCREF0_REF_ON_IDLE_M; - } - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADCREF0, adcref0); - - // Enable the ADC clock - HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) = AUX_SYSIF_ADCCLKCTL_REQ_M; - while (!(HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_ADCCLKCTL) & AUX_SYSIF_ADCCLKCTL_ACK_M)); - - // Enable the ADC data interface - if (trigger == AUXADC_TRIGGER_MANUAL) { - // Manual trigger: No need to configure event routing from GPT - HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT | AUX_ANAIF_ADCCTL_CMD_EN; - } else { - // GPT trigger: Configure event routing via MCU_EV to the AUX domain - HWREG(EVENT_BASE + EVENT_O_AUXSEL0) = trigger; - HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL) = AUX_ANAIF_ADCCTL_START_SRC_MCU_EV | AUX_ANAIF_ADCCTL_CMD_EN; - } - - // Configure the ADC - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, sampleTime << ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S); - - // Release reset and enable the ADC - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC0, ADI_4_AUX_ADC0_EN_M | ADI_4_AUX_ADC0_RESET_N_M); -} - -//***************************************************************************** -// -// Disables scaling of the ADC input -// -//***************************************************************************** -void -AUXADCDisableInputScaling(void) -{ - ADI8BitsSet(AUX_ADI4_BASE, ADI_4_AUX_O_ADC1, ADI_4_AUX_ADC1_SCALE_DIS_M); -} - -//***************************************************************************** -// -// Flushes the ADC FIFO -// -//***************************************************************************** -void -AUXADCFlushFifo(void) -{ - HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 1; // CMD: EN(1) -> FLUSH(3) - HWREGBITW(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCCTL, 1) = 0; // CMD: FLUSH(3) -> EN(1) -} - -//***************************************************************************** -// -// Waits for and returns the first sample in the ADC FIFO -// -//***************************************************************************** -uint32_t -AUXADCReadFifo(void) { - - // Wait until there is at least one sample in the FIFO - while (HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT) & AUX_ANAIF_ADCFIFOSTAT_EMPTY_M); - - // Return the first sample from the FIFO - return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); -} - -//***************************************************************************** -// -// Returns the first sample in the ADC FIFO, without waiting -// -//***************************************************************************** -uint32_t -AUXADCPopFifo(void) { - - // Return the first sample from the FIFO. If the FIFO is empty, this - // generates ADC FIFO underflow - return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFO); -} - -//***************************************************************************** -// -// Returns the gain value used when adjusting for ADC gain/offset -// -//***************************************************************************** -int32_t -AUXADCGetAdjustmentGain(uint32_t refSource) -{ - int32_t gain; - if (refSource == AUXADC_REF_FIXED) { - // AUXADC_REF_FIXED ==> ABS_GAIN - gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_ABS_GAIN) & FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S; - } else { - // AUXADC_REF_VDDS_REL ==> REL_GAIN - gain = (HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_REL_GAIN) & FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M) >> FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S; - } - return gain; -} - -//***************************************************************************** -// -// Returns the offset value used when adjusting for ADC gain/offset -// -//***************************************************************************** -int32_t -AUXADCGetAdjustmentOffset(uint32_t refSource) -{ - int8_t offset; - if ( refSource == AUXADC_REF_FIXED ) { - // AUXADC_REF_FIXED ==> ABS_OFFSET - offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S; - } else { - // AUXADC_REF_VDDS_REL ==> REL_OFFSET - offset = HWREG(FCFG1_BASE + FCFG1_O_SOC_ADC_OFFSET_INT) >> FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S; - } - return offset; -} - -//***************************************************************************** -// -// Converts an "ideal" ADC value to microvolts -// -//***************************************************************************** -int32_t -AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue) -{ - // Chop off 4 bits during calculations to avoid 32-bit overflow - fixedRefVoltage >>= 4; - return (((adcValue * fixedRefVoltage) + 2047) / 4095) << 4; -} - -//***************************************************************************** -// -// Converts a number of microvolts to corresponding "ideal" ADC value -// -//***************************************************************************** -int32_t -AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts) -{ - // Chop off 4 bits during calculations to avoid 32-bit overflow - fixedRefVoltage >>= 4; - microvolts >>= 4; - return ((microvolts * 4095) + (fixedRefVoltage / 2)) / fixedRefVoltage; -} - -//***************************************************************************** -// -// Performs ADC value gain and offset adjustment -// -//***************************************************************************** -int32_t -AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) -{ - // Apply gain and offset adjustment - adcValue = (((adcValue + offset) * gain) + 16384) / 32768; - - // Saturate - if (adcValue < 0) { - return 0; - } else if (adcValue > 4095) { - return 4095; - } else { - return adcValue; - } -} - -//***************************************************************************** -// -// Performs the inverse of the ADC value gain and offset adjustment -// -//***************************************************************************** -int32_t -AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset) -{ - // Apply inverse gain and offset adjustment - adcValue = (((adcValue * 32768) + (gain / 2)) / gain) - offset; - - // Saturate - if (adcValue < 0) { - return 0; - } else if (adcValue > 4095) { - return 4095; - } else { - return adcValue; - } -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h deleted file mode 100644 index c87fd2fb94d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_adc.h +++ /dev/null @@ -1,599 +0,0 @@ -/****************************************************************************** -* Filename: aux_adc.h -* Revised: 2018-02-07 09:45:39 +0100 (Wed, 07 Feb 2018) -* Revision: 51437 -* -* Description: Defines and prototypes for the AUX Analog-to-Digital -* Converter -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aux_group -//! @{ -//! \addtogroup auxadc_api -//! @{ -// -//***************************************************************************** - -#ifndef __AUX_ADC_H__ -#define __AUX_ADC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_event.h" -#include "../inc/hw_adi.h" -#include "../inc/hw_adi_4_aux.h" -#include "../inc/hw_aux_anaif.h" -#include "rom.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AUXADCDisable NOROM_AUXADCDisable - #define AUXADCEnableAsync NOROM_AUXADCEnableAsync - #define AUXADCEnableSync NOROM_AUXADCEnableSync - #define AUXADCDisableInputScaling NOROM_AUXADCDisableInputScaling - #define AUXADCFlushFifo NOROM_AUXADCFlushFifo - #define AUXADCReadFifo NOROM_AUXADCReadFifo - #define AUXADCPopFifo NOROM_AUXADCPopFifo - #define AUXADCGetAdjustmentGain NOROM_AUXADCGetAdjustmentGain - #define AUXADCGetAdjustmentOffset NOROM_AUXADCGetAdjustmentOffset - #define AUXADCValueToMicrovolts NOROM_AUXADCValueToMicrovolts - #define AUXADCMicrovoltsToValue NOROM_AUXADCMicrovoltsToValue - #define AUXADCAdjustValueForGainAndOffset NOROM_AUXADCAdjustValueForGainAndOffset - #define AUXADCUnadjustValueForGainAndOffset NOROM_AUXADCUnadjustValueForGainAndOffset -#endif - -//***************************************************************************** -// -// Defines for ADC reference sources. -// -//***************************************************************************** -#define AUXADC_REF_FIXED (0 << ADI_4_AUX_ADCREF0_SRC_S) -#define AUXADC_REF_VDDS_REL (1 << ADI_4_AUX_ADCREF0_SRC_S) - -//***************************************************************************** -// -// Defines for the ADC FIFO status bits. -// -//***************************************************************************** -#define AUXADC_FIFO_EMPTY_M (AUX_ANAIF_ADCFIFOSTAT_EMPTY_M) -#define AUXADC_FIFO_ALMOST_FULL_M (AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M) -#define AUXADC_FIFO_FULL_M (AUX_ANAIF_ADCFIFOSTAT_FULL_M) -#define AUXADC_FIFO_UNDERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M) -#define AUXADC_FIFO_OVERFLOW_M (AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M) - -//***************************************************************************** -// -// Defines for supported ADC triggers. -// -//***************************************************************************** -#define AUXADC_TRIGGER_MANUAL (EVENT_AUXSEL0_EV_NONE) -#define AUXADC_TRIGGER_GPT0A (EVENT_AUXSEL0_EV_GPT0A) -#define AUXADC_TRIGGER_GPT0B (EVENT_AUXSEL0_EV_GPT0B) -#define AUXADC_TRIGGER_GPT1A (EVENT_AUXSEL0_EV_GPT1A) -#define AUXADC_TRIGGER_GPT1B (EVENT_AUXSEL0_EV_GPT1B) -#define AUXADC_TRIGGER_GPT2A (EVENT_AUXSEL0_EV_GPT2A) -#define AUXADC_TRIGGER_GPT2B (EVENT_AUXSEL0_EV_GPT2B) -#define AUXADC_TRIGGER_GPT3A (EVENT_AUXSEL0_EV_GPT3A) -#define AUXADC_TRIGGER_GPT3B (EVENT_AUXSEL0_EV_GPT3B) -// Additional triggers specific for cc26x2 and cc13x2 devices -#define AUXADC_TRIGGER_GPT0A_CMP (EVENT_AUXSEL0_EV_GPT0A_CMP) -#define AUXADC_TRIGGER_GPT0B_CMP (EVENT_AUXSEL0_EV_GPT0B_CMP) -#define AUXADC_TRIGGER_GPT1A_CMP (EVENT_AUXSEL0_EV_GPT1A_CMP) -#define AUXADC_TRIGGER_GPT1B_CMP (EVENT_AUXSEL0_EV_GPT1B_CMP) -#define AUXADC_TRIGGER_GPT2A_CMP (EVENT_AUXSEL0_EV_GPT2A_CMP) -#define AUXADC_TRIGGER_GPT2B_CMP (EVENT_AUXSEL0_EV_GPT2B_CMP) -#define AUXADC_TRIGGER_GPT3A_CMP (EVENT_AUXSEL0_EV_GPT3A_CMP) -#define AUXADC_TRIGGER_GPT3B_CMP (EVENT_AUXSEL0_EV_GPT3B_CMP) - -//***************************************************************************** -// -// Defines for ADC sampling type for synchronous operation. -// -//***************************************************************************** -#define AUXADC_SAMPLE_TIME_2P7_US 3 -#define AUXADC_SAMPLE_TIME_5P3_US 4 -#define AUXADC_SAMPLE_TIME_10P6_US 5 -#define AUXADC_SAMPLE_TIME_21P3_US 6 -#define AUXADC_SAMPLE_TIME_42P6_US 7 -#define AUXADC_SAMPLE_TIME_85P3_US 8 -#define AUXADC_SAMPLE_TIME_170_US 9 -#define AUXADC_SAMPLE_TIME_341_US 10 -#define AUXADC_SAMPLE_TIME_682_US 11 -#define AUXADC_SAMPLE_TIME_1P37_MS 12 -#define AUXADC_SAMPLE_TIME_2P73_MS 13 -#define AUXADC_SAMPLE_TIME_5P46_MS 14 -#define AUXADC_SAMPLE_TIME_10P9_MS 15 - -//***************************************************************************** -// -// Equivalent voltages for fixed ADC reference, in microvolts. -// -//***************************************************************************** -#define AUXADC_FIXED_REF_VOLTAGE_NORMAL 4300000 -#define AUXADC_FIXED_REF_VOLTAGE_UNSCALED 1478500 - - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - - -//***************************************************************************** -// -//! \brief Disables the ADC. -//! -//! This function must be called: -//! - Before re-enabling the ADC using \ref AUXADCEnableAsync() or -//! \ref AUXADCEnableSync() -//! - Before entering system standby -// -//***************************************************************************** -extern void AUXADCDisable(void); - -//***************************************************************************** -// -//! \brief Enables the ADC for asynchronous operation. -//! -//! In asynchronous operation, the ADC samples continuously between -//! conversions. -//! -//! The ADC trigger starts the conversion. Note that the first conversion may -//! be invalid if the sampling period is too short. -//! -//! ADC input scaling is enabled by default after device reset, and is also re- -//! enabled by \ref AUXADCDisable(). To disable input scaling, call -//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableAsync(). -//! -//! \param refSource -//! ADC reference source: -//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) -//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) -//! \param trigger -//! ADC conversion trigger: -//! - \ref AUXADC_TRIGGER_MANUAL -//! - \ref AUXADC_TRIGGER_GPT0A -//! - \ref AUXADC_TRIGGER_GPT0B -//! - \ref AUXADC_TRIGGER_GPT1A -//! - \ref AUXADC_TRIGGER_GPT1B -//! - \ref AUXADC_TRIGGER_GPT2A -//! - \ref AUXADC_TRIGGER_GPT2B -//! - \ref AUXADC_TRIGGER_GPT3A -//! - \ref AUXADC_TRIGGER_GPT3B -// -//***************************************************************************** -extern void AUXADCEnableAsync(uint32_t refSource, uint32_t trigger); - -//***************************************************************************** -// -//! \brief Enables the ADC for synchronous operation. -//! -//! In synchronous operation, the ADC is idle between a conversion and -//! subsequent samplings. -//! -//! The ADC trigger starts sampling with specified duration, followed by the -//! conversion. Note that the first conversion may be invalid if the initial -//! sampling period is too short. -//! -//! ADC input scaling is enabled by default after device reset, and is also re- -//! enabled by \ref AUXADCDisable(). To disable input scaling, call -//! \ref AUXADCDisableInputScaling() before calling \ref AUXADCEnableSync(). -//! -//! \param refSource -//! ADC reference source: -//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) -//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) -//! \param sampleTime -//! ADC sampling time: -//! - \ref AUXADC_SAMPLE_TIME_2P7_US -//! - \ref AUXADC_SAMPLE_TIME_5P3_US -//! - \ref AUXADC_SAMPLE_TIME_10P6_US -//! - \ref AUXADC_SAMPLE_TIME_21P3_US -//! - \ref AUXADC_SAMPLE_TIME_42P6_US -//! - \ref AUXADC_SAMPLE_TIME_85P3_US -//! - \ref AUXADC_SAMPLE_TIME_170_US -//! - \ref AUXADC_SAMPLE_TIME_341_US -//! - \ref AUXADC_SAMPLE_TIME_682_US -//! - \ref AUXADC_SAMPLE_TIME_1P37_MS -//! - \ref AUXADC_SAMPLE_TIME_2P73_MS -//! - \ref AUXADC_SAMPLE_TIME_5P46_MS -//! - \ref AUXADC_SAMPLE_TIME_10P9_MS -//! \param trigger -//! ADC conversion trigger: -//! - \ref AUXADC_TRIGGER_MANUAL -//! - \ref AUXADC_TRIGGER_GPT0A -//! - \ref AUXADC_TRIGGER_GPT0B -//! - \ref AUXADC_TRIGGER_GPT1A -//! - \ref AUXADC_TRIGGER_GPT1B -//! - \ref AUXADC_TRIGGER_GPT2A -//! - \ref AUXADC_TRIGGER_GPT2B -//! - \ref AUXADC_TRIGGER_GPT3A -//! - \ref AUXADC_TRIGGER_GPT3B -// -//***************************************************************************** -extern void AUXADCEnableSync(uint32_t refSource, uint32_t sampleTime, uint32_t trigger); - -//***************************************************************************** -// -//! \brief Disables scaling of the ADC input. -//! -//! By default, the ADC operates internally on a version of the input signal -//! that has been scaled down by a factor 1408 / 4095. This function -//! disables that scaling, allowing for a trade-off between dynamic range and -//! and resolution. -//! -//! \note This function must only be called while the ADC is disabled, before -//! calling \ref AUXADCEnableSync() or \ref AUXADCEnableAsync(). -//! \note Different input maximum ratings apply when input scaling is disabled. -//! Violating these may damage the device. -// -//***************************************************************************** -extern void AUXADCDisableInputScaling(void); - -//***************************************************************************** -// -//! \brief Flushes the ADC FIFO. -//! -//! This empties the FIFO and clears the underflow/overflow flags. -//! -//! Note: This function must only be called while the ADC is enabled. -// -//***************************************************************************** -extern void AUXADCFlushFifo(void); - -//***************************************************************************** -// -//! \brief Generates a single manual ADC trigger. -//! -//! For synchronous mode, the trigger starts sampling followed by conversion. -//! For asynchronous mode, the trigger starts conversion. -// -//***************************************************************************** -__STATIC_INLINE void -AUXADCGenManualTrigger(void) -{ - HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCTRIG) = 0; -} - -//***************************************************************************** -// -//! \brief Returns flags indicating the status of the ADC FIFO. -//! -//! The flags indicate FIFO empty, full and almost full, and whether -//! overflow/underflow has occurred. -//! -//! \return -//! A combination (bitwise OR) of the following flags: -//! - \ref AUXADC_FIFO_EMPTY_M -//! - \ref AUXADC_FIFO_ALMOST_FULL_M -//! - \ref AUXADC_FIFO_FULL_M -//! - \ref AUXADC_FIFO_UNDERFLOW_M -//! - \ref AUXADC_FIFO_OVERFLOW_M -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AUXADCGetFifoStatus(void) -{ - return HWREG(AUX_ANAIF_BASE + AUX_ANAIF_O_ADCFIFOSTAT); -} - -//***************************************************************************** -// -//! \brief Waits for and returns the first sample in the ADC FIFO. -//! -//! This function waits until there is at least one sample in the ADC FIFO. It -//! then pops and returns the first sample from the FIFO. -//! -//! \note This procedure will deadlock if called without setting up ADC trigger -//! generation in advance. The trigger can either be manual or periodical -//! (using a GPT). -//! -//! \return The first (12-bit) sample from the ADC FIFO -// -//***************************************************************************** -extern uint32_t AUXADCReadFifo(void); - -//***************************************************************************** -// -//! \brief Returns the first sample in the ADC FIFO, without waiting. -//! -//! This function does not wait, and must only be called when there is at least -//! one sample in the ADC FIFO. Otherwise the call will generate FIFO underflow -//! (\ref AUXADC_FIFO_UNDERFLOW_M). -//! -//! \return The first (12-bit) sample from the ADC FIFO, or an undefined value -//! if the FIFO is empty -// -//***************************************************************************** -extern uint32_t AUXADCPopFifo(void); - -//***************************************************************************** -// -//! \brief Selects internal or external input for the ADC. -//! -//! Note that calling this function also selects the same input for AUX_COMPB. -//! -//! \param input -//! Internal/external input selection: -//! - \ref ADC_COMPB_IN_DCOUPL -//! - \ref ADC_COMPB_IN_VSS -//! - \ref ADC_COMPB_IN_VDDS -//! - \ref ADC_COMPB_IN_AUXIO7 -//! - \ref ADC_COMPB_IN_AUXIO6 -//! - \ref ADC_COMPB_IN_AUXIO5 -//! - \ref ADC_COMPB_IN_AUXIO4 -//! - \ref ADC_COMPB_IN_AUXIO3 -//! - \ref ADC_COMPB_IN_AUXIO2 -//! - \ref ADC_COMPB_IN_AUXIO1 -//! - \ref ADC_COMPB_IN_AUXIO0 -// -//***************************************************************************** -__STATIC_INLINE void -AUXADCSelectInput(uint32_t input) -{ - HapiSelectADCCompBInput(input); -} - -//***************************************************************************** -// -//! \brief Returns the gain value used when adjusting for ADC gain/offset. -//! -//! The function returns the gain value to be used with -//! \ref AUXADCAdjustValueForGainAndOffset() or -//! \ref AUXADCUnadjustValueForGainAndOffset(). The gain value is found during -//! chip manufacturing and is stored in the factory configuration, FCFG1. -//! -//! \param refSource -//! ADC reference source: -//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) -//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) -//! -//! \return -//! The gain value to be used in adjustments -// -//***************************************************************************** -extern int32_t AUXADCGetAdjustmentGain(uint32_t refSource); - -//***************************************************************************** -// -//! \brief Returns the offset value used when adjusting for ADC gain/offset. -//! -//! The function returns the offset value to be used with -//! \ref AUXADCAdjustValueForGainAndOffset() or -//! \ref AUXADCUnadjustValueForGainAndOffset(). The offset value is found -//! during chip manufacturing and is stored in the factory configuration, -//! FCFG1. -//! -//! \param refSource -//! ADC reference source: -//! - \ref AUXADC_REF_FIXED (nominally 4.3 V) -//! - \ref AUXADC_REF_VDDS_REL (nominally VDDS) -//! -//! \return -//! The offset value to be used in adjustments -// -//***************************************************************************** -extern int32_t AUXADCGetAdjustmentOffset(uint32_t refSource); - -//***************************************************************************** -// -//! \brief Converts an "adjusted" ADC value to microvolts. -//! -//! This function can only be used when measuring with fixed ADC reference -//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for -//! whether the sampled ADC input is scaled down before conversion or not. -//! -//! \param fixedRefVoltage -//! Fixed reference voltage, in microvolts -//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal) -//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input -//! \param adcValue -//! The ADC value -//! -//! \return -//! The corresponding number of microvolts -// -//***************************************************************************** -extern int32_t AUXADCValueToMicrovolts(int32_t fixedRefVoltage, int32_t adcValue); - -//***************************************************************************** -// -//! \brief Converts a number of microvolts to corresponding "adjusted" ADC value. -//! -//! This function can only be used when measuring with fixed ADC reference -//! (\ref AUXADC_REF_FIXED). The specified reference voltage accounts for -//! whether the sampled ADC input is scaled down before conversion or not. -//! -//! \param fixedRefVoltage -//! Fixed reference voltage, in microvolts -//! - \ref AUXADC_FIXED_REF_VOLTAGE_NORMAL when using scaled input (normal) -//! - \ref AUXADC_FIXED_REF_VOLTAGE_UNSCALED when using unscaled input -//! \param microvolts -//! The number of microvolts -//! -//! \return -//! The corresponding expected ADC value (adjusted for ADC gain/offset) -// -//***************************************************************************** -extern int32_t AUXADCMicrovoltsToValue(int32_t fixedRefVoltage, int32_t microvolts); - -//***************************************************************************** -// -//! \brief Performs ADC value gain and offset adjustment. -//! -//! This function takes a measured ADC value compensates for the internal gain -//! and offset in the ADC. -//! -//! \param adcValue -//! 12-bit ADC unadjusted value -//! \param gain -//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain() -//! \param offset -//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset() -//! -//! \return -//! 12-bit ADC adjusted value -// -//***************************************************************************** -extern int32_t AUXADCAdjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset); - -//***************************************************************************** -// -//! \brief Performs the inverse of the ADC value gain and offset adjustment. -//! -//! This function finds the expected measured ADC value, without gain and -//! offset compensation, for a given "ideal" ADC value. The function can for -//! example be used to find ADC value thresholds to be used in Sensor -//! Controller task configurations. -//! -//! \param adcValue -//! 12-bit ADC adjusted value -//! \param gain -//! Gain adjustment value provided by \ref AUXADCGetAdjustmentGain() -//! \param offset -//! Offset adjustment value provided by \ref AUXADCGetAdjustmentOffset() -//! -//! \return -//! 12-bit ADC unadjusted value -// -//***************************************************************************** -extern int32_t AUXADCUnadjustValueForGainAndOffset(int32_t adcValue, int32_t gain, int32_t offset); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AUXADCDisable - #undef AUXADCDisable - #define AUXADCDisable ROM_AUXADCDisable - #endif - #ifdef ROM_AUXADCEnableAsync - #undef AUXADCEnableAsync - #define AUXADCEnableAsync ROM_AUXADCEnableAsync - #endif - #ifdef ROM_AUXADCEnableSync - #undef AUXADCEnableSync - #define AUXADCEnableSync ROM_AUXADCEnableSync - #endif - #ifdef ROM_AUXADCDisableInputScaling - #undef AUXADCDisableInputScaling - #define AUXADCDisableInputScaling ROM_AUXADCDisableInputScaling - #endif - #ifdef ROM_AUXADCFlushFifo - #undef AUXADCFlushFifo - #define AUXADCFlushFifo ROM_AUXADCFlushFifo - #endif - #ifdef ROM_AUXADCReadFifo - #undef AUXADCReadFifo - #define AUXADCReadFifo ROM_AUXADCReadFifo - #endif - #ifdef ROM_AUXADCPopFifo - #undef AUXADCPopFifo - #define AUXADCPopFifo ROM_AUXADCPopFifo - #endif - #ifdef ROM_AUXADCGetAdjustmentGain - #undef AUXADCGetAdjustmentGain - #define AUXADCGetAdjustmentGain ROM_AUXADCGetAdjustmentGain - #endif - #ifdef ROM_AUXADCGetAdjustmentOffset - #undef AUXADCGetAdjustmentOffset - #define AUXADCGetAdjustmentOffset ROM_AUXADCGetAdjustmentOffset - #endif - #ifdef ROM_AUXADCValueToMicrovolts - #undef AUXADCValueToMicrovolts - #define AUXADCValueToMicrovolts ROM_AUXADCValueToMicrovolts - #endif - #ifdef ROM_AUXADCMicrovoltsToValue - #undef AUXADCMicrovoltsToValue - #define AUXADCMicrovoltsToValue ROM_AUXADCMicrovoltsToValue - #endif - #ifdef ROM_AUXADCAdjustValueForGainAndOffset - #undef AUXADCAdjustValueForGainAndOffset - #define AUXADCAdjustValueForGainAndOffset ROM_AUXADCAdjustValueForGainAndOffset - #endif - #ifdef ROM_AUXADCUnadjustValueForGainAndOffset - #undef AUXADCUnadjustValueForGainAndOffset - #define AUXADCUnadjustValueForGainAndOffset ROM_AUXADCUnadjustValueForGainAndOffset - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AUX_ADC_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.c deleted file mode 100644 index a5d3f08644a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.c +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: aux_smph.c -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Driver for the AUX Semaphore. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aux_smph.h" - -// See aux_smph.h for implementation diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h deleted file mode 100644 index d2d6d4d3294..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_smph.h +++ /dev/null @@ -1,258 +0,0 @@ -/****************************************************************************** -* Filename: aux_smph.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the AUX Semaphore -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aux_group -//! @{ -//! \addtogroup auxsmph_api -//! @{ -// -//***************************************************************************** - -#ifndef __AUX_SMPH_H__ -#define __AUX_SMPH_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_aux_smph.h" -#include "../inc/hw_memmap.h" -#include "debug.h" - -//***************************************************************************** -// -// General constants and defines -// -//***************************************************************************** -#define AUX_SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed -#define AUX_SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed - -//***************************************************************************** -// -// Values that can be passed to AUXSMPHAcquire and AUXSMPHRelease -// as the ui32Semaphore parameter. -// -//***************************************************************************** -#define AUX_SMPH_0 0 // AUX Semaphore 0 -#define AUX_SMPH_1 1 // AUX Semaphore 1 -#define AUX_SMPH_2 2 // AUX Semaphore 2 -#define AUX_SMPH_3 3 // AUX Semaphore 3 -#define AUX_SMPH_4 4 // AUX Semaphore 4 -#define AUX_SMPH_5 5 // AUX Semaphore 5 -#define AUX_SMPH_6 6 // AUX Semaphore 6 -#define AUX_SMPH_7 7 // AUX Semaphore 7 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Acquire an AUX semaphore. -//! -//! This function acquires the given AUX semaphore, blocking the call until -//! the semaphore is available. -//! -//! \note The semaphore can also be acquired by the dedicated Sensor Controller. -//! The System CPU master can thus be competing for the shared resource, i.e. -//! the specified semaphore. -//! -//! \param ui32Semaphore is the semaphore number. -//! - \ref AUX_SMPH_0 -//! - \ref AUX_SMPH_1 -//! - \ref AUX_SMPH_2 -//! - \ref AUX_SMPH_3 -//! - \ref AUX_SMPH_4 -//! - \ref AUX_SMPH_5 -//! - \ref AUX_SMPH_6 -//! - \ref AUX_SMPH_7 -//! -//! \return None -//! -//! \sa AUXSMPHTryAcquire(), AUXSMPHRelease() -// -//***************************************************************************** -__STATIC_INLINE void -AUXSMPHAcquire(uint32_t ui32Semaphore) -{ - // Check the arguments. - ASSERT((ui32Semaphore == AUX_SMPH_0) || - (ui32Semaphore == AUX_SMPH_1) || - (ui32Semaphore == AUX_SMPH_2) || - (ui32Semaphore == AUX_SMPH_3) || - (ui32Semaphore == AUX_SMPH_4) || - (ui32Semaphore == AUX_SMPH_5) || - (ui32Semaphore == AUX_SMPH_6) || - (ui32Semaphore == AUX_SMPH_7)); - - // Wait for semaphore to be released such that it can be claimed - // Semaphore register reads 1 when lock was acquired otherwise 0 - // (i.e. AUX_SMPH_CLAIMED). - while(HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) == - AUX_SMPH_CLAIMED) - { - } -} - -//***************************************************************************** -// -//! \brief Try to acquire an AUX semaphore. -//! -//! This function tries to acquire the given AUX semaphore, if the semaphore -//! could not be claimed the function returns false. -//! -//! \note The semaphore can also be acquired by the dedicated Sensor Controller. -//! The System CPU master can thus be competing for the shared resource, i.e. -//! the specified semaphore. -//! -//! \param ui32Semaphore is the semaphore number. -//! - \ref AUX_SMPH_0 -//! - \ref AUX_SMPH_1 -//! - \ref AUX_SMPH_2 -//! - \ref AUX_SMPH_3 -//! - \ref AUX_SMPH_4 -//! - \ref AUX_SMPH_5 -//! - \ref AUX_SMPH_6 -//! - \ref AUX_SMPH_7 -//! -//! \return Returns true if semaphore was acquired, false otherwise -//! -//! \sa AUXSMPHAcquire(), AUXSMPHRelease() -// -//***************************************************************************** -__STATIC_INLINE bool -AUXSMPHTryAcquire(uint32_t ui32Semaphore) -{ - uint32_t ui32SemaReg; - - // Check the arguments. - ASSERT((ui32Semaphore == AUX_SMPH_0) || - (ui32Semaphore == AUX_SMPH_1) || - (ui32Semaphore == AUX_SMPH_2) || - (ui32Semaphore == AUX_SMPH_3) || - (ui32Semaphore == AUX_SMPH_4) || - (ui32Semaphore == AUX_SMPH_5) || - (ui32Semaphore == AUX_SMPH_6) || - (ui32Semaphore == AUX_SMPH_7)); - - // AUX Semaphore register reads 1 if lock was acquired - // (i.e. SMPH_FREE when read) but subsequent reads will read 0. - ui32SemaReg = HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore); - - return (ui32SemaReg == AUX_SMPH_FREE); -} - -//***************************************************************************** -// -//! \brief Release an AUX semaphore by System CPU master. -//! -//! This function releases the given AUX semaphore. -//! -//! \note It is up to the application to provide the convention for clearing -//! semaphore. -//! -//! \note The semaphore can also be acquired by the dedicated Sensor Controller. -//! The System CPU master can thus be competing for the shared resource, i.e. -//! the specified semaphore. -//! -//! \param ui32Semaphore is the semaphore number. -//! - \ref AUX_SMPH_0 -//! - \ref AUX_SMPH_1 -//! - \ref AUX_SMPH_2 -//! - \ref AUX_SMPH_3 -//! - \ref AUX_SMPH_4 -//! - \ref AUX_SMPH_5 -//! - \ref AUX_SMPH_6 -//! - \ref AUX_SMPH_7 -//! -//! \return None -//! -//! \sa AUXSMPHAcquire(), AUXSMPHTryAcquire() -// -//***************************************************************************** -__STATIC_INLINE void -AUXSMPHRelease(uint32_t ui32Semaphore) -{ - // Check the arguments. - ASSERT((ui32Semaphore == AUX_SMPH_0) || - (ui32Semaphore == AUX_SMPH_1) || - (ui32Semaphore == AUX_SMPH_2) || - (ui32Semaphore == AUX_SMPH_3) || - (ui32Semaphore == AUX_SMPH_4) || - (ui32Semaphore == AUX_SMPH_5) || - (ui32Semaphore == AUX_SMPH_6) || - (ui32Semaphore == AUX_SMPH_7)); - - // No check before release. It is up to the application to provide the - // conventions for who and when a semaphore can be released. - HWREG(AUX_SMPH_BASE + AUX_SMPH_O_SMPH0 + 4 * ui32Semaphore) = - AUX_SMPH_FREE; -} - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AUX_SMPH_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.c deleted file mode 100644 index 5e3e90b7c2f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.c +++ /dev/null @@ -1,96 +0,0 @@ -/****************************************************************************** -* Filename: aux_sysif.c -* Revised: 2018-04-17 14:54:06 +0200 (Tue, 17 Apr 2018) -* Revision: 51890 -* -* Description: Driver for the AUX System Interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aux_sysif.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AUXSYSIFOpModeChange - #define AUXSYSIFOpModeChange NOROM_AUXSYSIFOpModeChange -#endif - - -//***************************************************************************** -// -// Used in AUXSYSIFOpModeChange() to control the change of the operational mode. -// -//***************************************************************************** -static const uint8_t g_OpMode_to_order[4] = {1,2,0,3}; -static const uint8_t g_Order_to_OpMode[4] = {2,0,1,3}; - -//***************************************************************************** -// -// Controls AUX operational mode change -// -//***************************************************************************** -void -AUXSYSIFOpModeChange(uint32_t targetOpMode) -{ - uint32_t currentOpMode; - uint32_t currentOrder; - uint32_t nextMode; - - // Check the argument - ASSERT((targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_PDLP)|| - (targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_PDA) || - (targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_LP) || - (targetOpMode == AUX_SYSIF_OPMODEREQ_REQ_A)); - - do { - currentOpMode = HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEREQ); - while ( currentOpMode != HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEACK)); - if (currentOpMode != targetOpMode) - { - currentOrder = g_OpMode_to_order[currentOpMode]; - if ( currentOrder < g_OpMode_to_order[targetOpMode]) - { - nextMode = g_Order_to_OpMode[currentOrder + 1]; - } - else - { - nextMode = g_Order_to_OpMode[currentOrder - 1]; - } - HWREG(AUX_SYSIF_BASE + AUX_SYSIF_O_OPMODEREQ) = nextMode; - } - } while ( currentOpMode != targetOpMode ); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h deleted file mode 100644 index 04214bc1a37..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_sysif.h +++ /dev/null @@ -1,154 +0,0 @@ -/****************************************************************************** -* Filename: aux_sysif.h -* Revised: 2017-06-27 08:41:49 +0200 (Tue, 27 Jun 2017) -* Revision: 49245 -* -* Description: Defines and prototypes for the AUX System Interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aux_group -//! @{ -//! \addtogroup auxsysif_api -//! @{ -// -//***************************************************************************** - -#ifndef __AUX_SYSIF_H__ -#define __AUX_SYSIF_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_aux_sysif.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AUXSYSIFOpModeChange NOROM_AUXSYSIFOpModeChange -#endif - - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -// Defines for AUX operational modes. -// -//***************************************************************************** -#define AUX_SYSIF_OPMODE_TARGET_PDLP (AUX_SYSIF_OPMODEREQ_REQ_PDLP) -#define AUX_SYSIF_OPMODE_TARGET_PDA (AUX_SYSIF_OPMODEREQ_REQ_PDA) -#define AUX_SYSIF_OPMODE_TARGET_LP (AUX_SYSIF_OPMODEREQ_REQ_LP) -#define AUX_SYSIF_OPMODE_TARGET_A (AUX_SYSIF_OPMODEREQ_REQ_A) - -//***************************************************************************** -// -//! \brief Changes the AUX operational mode to the requested target mode. -//! -//! This function controls the change of the AUX operational mode. -//! The function controls the change of the current operational mode to the -//! operational mode target by adhering to rules specified by HW. -//! -//! \param targetOpMode -//! AUX operational mode: -//! - \ref AUX_SYSIF_OPMODE_TARGET_PDLP (Powerdown operational mode with wakeup to lowpower mode) -//! - \ref AUX_SYSIF_OPMODE_TARGET_PDA (Powerdown operational mode with wakeup to active mode) -//! - \ref AUX_SYSIF_OPMODE_TARGET_LP (Lowpower operational mode) -//! - \ref AUX_SYSIF_OPMODE_TARGET_A (Active operational mode) -//! -//! \return None -// -//***************************************************************************** -extern void AUXSYSIFOpModeChange(uint32_t targetOpMode); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AUXSYSIFOpModeChange - #undef AUXSYSIFOpModeChange - #define AUXSYSIFOpModeChange ROM_AUXSYSIFOpModeChange - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AUX_SYSIF_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.c deleted file mode 100644 index 6bbcf55a5e5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.c +++ /dev/null @@ -1,111 +0,0 @@ -/****************************************************************************** -* Filename: aux_tdc.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for the AUX Time to Digital Converter interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "aux_tdc.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef AUXTDCConfigSet - #define AUXTDCConfigSet NOROM_AUXTDCConfigSet - #undef AUXTDCMeasurementDone - #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone -#endif - -//***************************************************************************** -// -// Configure the operation of the AUX TDC -// -//***************************************************************************** -void -AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, - uint32_t ui32StopCondition) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Make sure the AUX TDC is in the idle state before changing the - // configuration. - while(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) - { - } - - // Clear previous results. - HWREG(ui32Base + AUX_TDC_O_CTL) = 0x0; - - // Change the configuration. - HWREG(ui32Base + AUX_TDC_O_TRIGSRC) = ui32StartCondition | ui32StopCondition; -} - -//***************************************************************************** -// -// Check if the AUX TDC is done measuring -// -//***************************************************************************** -uint32_t -AUXTDCMeasurementDone(uint32_t ui32Base) -{ - uint32_t ui32Reg; - uint32_t ui32Status; - - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Check if the AUX TDC is done measuring. - ui32Reg = HWREG(ui32Base + AUX_TDC_O_STAT); - if(ui32Reg & AUX_TDC_STAT_DONE) - { - ui32Status = AUX_TDC_DONE; - } - else if(ui32Reg & AUX_TDC_STAT_SAT) - { - ui32Status = AUX_TDC_TIMEOUT; - } - else - { - ui32Status = AUX_TDC_BUSY; - } - - // Return the status. - return (ui32Status); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h deleted file mode 100644 index 402c83423a7..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/aux_tdc.h +++ /dev/null @@ -1,904 +0,0 @@ -/****************************************************************************** -* Filename: aux_tdc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the AUX Time-to-Digital Converter -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup aux_group -//! @{ -//! \addtogroup auxtdc_api -//! @{ -// -//***************************************************************************** - -#ifndef __AUX_TDC_H__ -#define __AUX_TDC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_aux_tdc.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define AUXTDCConfigSet NOROM_AUXTDCConfigSet - #define AUXTDCMeasurementDone NOROM_AUXTDCMeasurementDone -#endif - -//***************************************************************************** -// -// Defines for the status of a AUX TDC measurement. -// -//***************************************************************************** -#define AUX_TDC_BUSY 0x00000001 -#define AUX_TDC_TIMEOUT 0x00000002 -#define AUX_TDC_DONE 0x00000004 - -//***************************************************************************** -// -// Defines for the control of a AUX TDC. -// -//***************************************************************************** -#define AUX_TDC_RUNSYNC 0x00000001 -#define AUX_TDC_RUN 0x00000002 -#define AUX_TDC_ABORT 0x00000003 - -//***************************************************************************** -// -// Defines for possible states of the TDC internal state machine. -// -//***************************************************************************** -#define AUXTDC_WAIT_START (AUX_TDC_STAT_STATE_WAIT_START) -#define AUXTDC_WAIT_START_CNTEN (AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN) -#define AUXTDC_IDLE (AUX_TDC_STAT_STATE_IDLE) -#define AUXTDC_CLRCNT (AUX_TDC_STAT_STATE_CLR_CNT) -#define AUXTDC_WAIT_STOP (AUX_TDC_STAT_STATE_WAIT_STOP) -#define AUXTDC_WAIT_STOP_CNTDOWN (AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN) -#define AUXTDC_GETRESULTS (AUX_TDC_STAT_STATE_GET_RESULT) -#define AUXTDC_POR (AUX_TDC_STAT_STATE_POR) -#define AUXTDC_WAIT_CLRCNT_DONE (AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE) -#define AUXTDC_START_FALL (AUX_TDC_STAT_STATE_START_FALL) -#define AUXTDC_FORCE_STOP (AUX_TDC_STAT_STATE_FORCE_STOP) - -//***************************************************************************** -// -// Defines for controlling the AUX TDC. Values can be passed to AUXTDCConfigSet(). -// -//***************************************************************************** -#define AUXTDC_STOPPOL_RIS (AUX_TDC_TRIGSRC_STOP_POL_HIGH) // Rising edge polarity for stop event -#define AUXTDC_STOPPOL_FALL (AUX_TDC_TRIGSRC_STOP_POL_LOW) // Falling edge polarity for stop event - -#define AUXTDC_STOP_AUXIO0 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0) -#define AUXTDC_STOP_AUXIO1 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1) -#define AUXTDC_STOP_AUXIO2 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2) -#define AUXTDC_STOP_AUXIO3 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3) -#define AUXTDC_STOP_AUXIO4 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4) -#define AUXTDC_STOP_AUXIO5 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5) -#define AUXTDC_STOP_AUXIO6 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6) -#define AUXTDC_STOP_AUXIO7 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7) -#define AUXTDC_STOP_AUXIO8 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8) -#define AUXTDC_STOP_AUXIO9 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9) -#define AUXTDC_STOP_AUXIO10 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10) -#define AUXTDC_STOP_AUXIO11 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11) -#define AUXTDC_STOP_AUXIO12 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12) -#define AUXTDC_STOP_AUXIO13 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13) -#define AUXTDC_STOP_AUXIO14 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14) -#define AUXTDC_STOP_AUXIO15 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15) -#define AUXTDC_STOP_AUXIO16 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16) -#define AUXTDC_STOP_AUXIO17 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17) -#define AUXTDC_STOP_AUXIO18 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18) -#define AUXTDC_STOP_AUXIO19 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19) -#define AUXTDC_STOP_AUXIO20 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20) -#define AUXTDC_STOP_AUXIO21 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21) -#define AUXTDC_STOP_AUXIO22 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22) -#define AUXTDC_STOP_AUXIO23 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23) -#define AUXTDC_STOP_AUXIO24 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24) -#define AUXTDC_STOP_AUXIO25 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25) -#define AUXTDC_STOP_AUXIO26 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26) -#define AUXTDC_STOP_AUXIO27 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27) -#define AUXTDC_STOP_AUXIO28 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28) -#define AUXTDC_STOP_AUXIO29 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29) -#define AUXTDC_STOP_AUXIO30 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30) -#define AUXTDC_STOP_AUXIO31 (AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31) -#define AUXTDC_STOP_MANUAL_EV (AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV) -#define AUXTDC_STOP_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY) -#define AUXTDC_STOP_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ) -#define AUXTDC_STOP_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD) -#define AUXTDC_STOP_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD) -#define AUXTDC_STOP_SCLK_LF (AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF) -#define AUXTDC_STOP_PWR_DWN (AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN) -#define AUXTDC_STOP_MCU_ACTIVE (AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE) -#define AUXTDC_STOP_VDDR_RECHARGE (AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE) -#define AUXTDC_STOP_TIMER2_EV0 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0) -#define AUXTDC_STOP_TIMER2_EV1 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1) -#define AUXTDC_STOP_TIMER2_EV2 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2) -#define AUXTDC_STOP_TIMER2_EV3 (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3) -#define AUXTDC_STOP_TIMER2_PULSE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE) -#define AUXTDC_STOP_TDC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE) -#define AUXTDC_STOP_ADC_IRQ (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ) -#define AUXTDC_STOP_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY) -#define AUXTDC_STOP_NO_EVENT (AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT) -#define AUXTDC_STOP_ADC_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE) -#define AUXTDC_STOP_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL) -#define AUXTDC_STOP_ISRC_RESET (AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N) -#define AUXTDC_STOP_OBSMUX0 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0) -#define AUXTDC_STOP_OBSMUX1 (AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1) -#define AUXTDC_STOP_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE) -#define AUXTDC_STOP_TDC_PRE (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE) -#define AUXTDC_STOP_TIMER0_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV) -#define AUXTDC_STOP_TIMER1_EV (AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV) -#define AUXTDC_STOP_AON_RTC_CH2 (AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2) -#define AUXTDC_STOP_AUX_COMPA (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA) -#define AUXTDC_STOP_AUX_COMPB (AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB) -#define AUXTDC_STOP_ACLK_REF (AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF) -#define AUXTDC_STOP_MCU_EV (AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV) - -#define AUXTDC_STARTPOL_RIS (AUX_TDC_TRIGSRC_START_POL_HIGH) // Rising edge polarity for start event -#define AUXTDC_STARTPOL_FALL (AUX_TDC_TRIGSRC_START_POL_LOW) // Falling edge polarity for start event - -#define AUXTDC_START_AUXIO0 (AUX_TDC_TRIGSRC_START_SRC_AUXIO0) -#define AUXTDC_START_AUXIO1 (AUX_TDC_TRIGSRC_START_SRC_AUXIO1) -#define AUXTDC_START_AUXIO2 (AUX_TDC_TRIGSRC_START_SRC_AUXIO2) -#define AUXTDC_START_AUXIO3 (AUX_TDC_TRIGSRC_START_SRC_AUXIO3) -#define AUXTDC_START_AUXIO4 (AUX_TDC_TRIGSRC_START_SRC_AUXIO4) -#define AUXTDC_START_AUXIO5 (AUX_TDC_TRIGSRC_START_SRC_AUXIO5) -#define AUXTDC_START_AUXIO6 (AUX_TDC_TRIGSRC_START_SRC_AUXIO6) -#define AUXTDC_START_AUXIO7 (AUX_TDC_TRIGSRC_START_SRC_AUXIO7) -#define AUXTDC_START_AUXIO8 (AUX_TDC_TRIGSRC_START_SRC_AUXIO8) -#define AUXTDC_START_AUXIO9 (AUX_TDC_TRIGSRC_START_SRC_AUXIO9) -#define AUXTDC_START_AUXIO10 (AUX_TDC_TRIGSRC_START_SRC_AUXIO10) -#define AUXTDC_START_AUXIO11 (AUX_TDC_TRIGSRC_START_SRC_AUXIO11) -#define AUXTDC_START_AUXIO12 (AUX_TDC_TRIGSRC_START_SRC_AUXIO12) -#define AUXTDC_START_AUXIO13 (AUX_TDC_TRIGSRC_START_SRC_AUXIO13) -#define AUXTDC_START_AUXIO14 (AUX_TDC_TRIGSRC_START_SRC_AUXIO14) -#define AUXTDC_START_AUXIO15 (AUX_TDC_TRIGSRC_START_SRC_AUXIO15) -#define AUXTDC_START_AUXIO16 (AUX_TDC_TRIGSRC_START_SRC_AUXIO16) -#define AUXTDC_START_AUXIO17 (AUX_TDC_TRIGSRC_START_SRC_AUXIO17) -#define AUXTDC_START_AUXIO18 (AUX_TDC_TRIGSRC_START_SRC_AUXIO18) -#define AUXTDC_START_AUXIO19 (AUX_TDC_TRIGSRC_START_SRC_AUXIO19) -#define AUXTDC_START_AUXIO20 (AUX_TDC_TRIGSRC_START_SRC_AUXIO20) -#define AUXTDC_START_AUXIO21 (AUX_TDC_TRIGSRC_START_SRC_AUXIO21) -#define AUXTDC_START_AUXIO22 (AUX_TDC_TRIGSRC_START_SRC_AUXIO22) -#define AUXTDC_START_AUXIO23 (AUX_TDC_TRIGSRC_START_SRC_AUXIO23) -#define AUXTDC_START_AUXIO24 (AUX_TDC_TRIGSRC_START_SRC_AUXIO24) -#define AUXTDC_START_AUXIO25 (AUX_TDC_TRIGSRC_START_SRC_AUXIO25) -#define AUXTDC_START_AUXIO26 (AUX_TDC_TRIGSRC_START_SRC_AUXIO26) -#define AUXTDC_START_AUXIO27 (AUX_TDC_TRIGSRC_START_SRC_AUXIO27) -#define AUXTDC_START_AUXIO28 (AUX_TDC_TRIGSRC_START_SRC_AUXIO28) -#define AUXTDC_START_AUXIO29 (AUX_TDC_TRIGSRC_START_SRC_AUXIO29) -#define AUXTDC_START_AUXIO30 (AUX_TDC_TRIGSRC_START_SRC_AUXIO30) -#define AUXTDC_START_AUXIO31 (AUX_TDC_TRIGSRC_START_SRC_AUXIO31) -#define AUXTDC_START_MANUAL_EV (AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV) -#define AUXTDC_START_AON_RTC_CH2_DLY (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY) -#define AUXTDC_START_AON_RTC_4KHZ (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ) -#define AUXTDC_START_AON_BATMON_BAT_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD) -#define AUXTDC_START_AON_BATMON_TEMP_UPD (AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD) -#define AUXTDC_START_SCLK_LF (AUX_TDC_TRIGSRC_START_SRC_SCLK_LF) -#define AUXTDC_START_PWR_DWN (AUX_TDC_TRIGSRC_START_SRC_PWR_DWN) -#define AUXTDC_START_MCU_ACTIVE (AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE) -#define AUXTDC_START_VDDR_RECHARGE (AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE) -#define AUXTDC_START_TIMER2_EV0 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0) -#define AUXTDC_START_TIMER2_EV1 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1) -#define AUXTDC_START_TIMER2_EV2 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2) -#define AUXTDC_START_TIMER2_EV3 (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3) -#define AUXTDC_START_TIMER2_PULSE (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE) -#define AUXTDC_START_TDC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE) -#define AUXTDC_START_ADC_IRQ (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ) -#define AUXTDC_START_ADC_FIFO_NOT_EMPTY (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY) -#define AUXTDC_START_NO_EVENT (AUX_TDC_TRIGSRC_START_SRC_NO_EVENT) -#define AUXTDC_START_ADC_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE) -#define AUXTDC_START_ADC_FIFO_ALMOST_FULL (AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL) -#define AUXTDC_START_ISRC_RESET (AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N) -#define AUXTDC_START_OBSMUX0 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0) -#define AUXTDC_START_OBSMUX1 (AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1) -#define AUXTDC_START_SMPH_AUTOTAKE_DONE (AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE) -#define AUXTDC_START_TDC_PRE (AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE) -#define AUXTDC_START_TIMER0_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV) -#define AUXTDC_START_TIMER1_EV (AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV) -#define AUXTDC_START_AON_RTC_CH2 (AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2) -#define AUXTDC_START_AUX_COMPA (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA) -#define AUXTDC_START_AUX_COMPB (AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB) -#define AUXTDC_START_ACLK_REF (AUX_TDC_TRIGSRC_START_SRC_ACLK_REF) -#define AUXTDC_START_MCU_EV (AUX_TDC_TRIGSRC_START_SRC_MCU_EV) - -//***************************************************************************** -// -// Defines for the possible saturation values set using AUXTDCLimitSet(). -// -//***************************************************************************** -#define AUXTDC_SAT_4096 (AUX_TDC_SATCFG_LIMIT_R12) -#define AUXTDC_SAT_8192 (AUX_TDC_SATCFG_LIMIT_R13) -#define AUXTDC_SAT_16384 (AUX_TDC_SATCFG_LIMIT_R14) -#define AUXTDC_SAT_32768 (AUX_TDC_SATCFG_LIMIT_R15) -#define AUXTDC_SAT_65536 (AUX_TDC_SATCFG_LIMIT_R16) -#define AUXTDC_SAT_131072 (AUX_TDC_SATCFG_LIMIT_R17) -#define AUXTDC_SAT_262144 (AUX_TDC_SATCFG_LIMIT_R18) -#define AUXTDC_SAT_524288 (AUX_TDC_SATCFG_LIMIT_R19) -#define AUXTDC_SAT_1048576 (AUX_TDC_SATCFG_LIMIT_R20) -#define AUXTDC_SAT_2097152 (AUX_TDC_SATCFG_LIMIT_R21) -#define AUXTDC_SAT_4194304 (AUX_TDC_SATCFG_LIMIT_R22) -#define AUXTDC_SAT_8388608 (AUX_TDC_SATCFG_LIMIT_R23) -#define AUXTDC_SAT_16777216 (AUX_TDC_SATCFG_LIMIT_R24) -#define AUXTDC_NUM_SAT_VALS 16 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! \brief Checks an AUX TDC base address. -//! -//! This function determines if a AUX TDC port base address is valid. -//! -//! \param ui32Base is the base address of the AUX TDC port. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -AUXTDCBaseValid(uint32_t ui32Base) -{ - return(ui32Base == AUX_TDC_BASE); -} -#endif - -//***************************************************************************** -// -//! \brief Get the status of the AUX TDC internal state machine. -//! -//! This function will return the current state of the AUX TDC internal state -//! machine. -//! \param ui32Base is base address of the AUX TDC -//! -//! \return Returns the current state of the state machine. -//! Possible states for the state machine are: -//! - \ref AUXTDC_WAIT_START -//! - \ref AUXTDC_WAIT_START_CNTEN -//! - \ref AUXTDC_IDLE -//! - \ref AUXTDC_CLRCNT -//! - \ref AUXTDC_WAIT_STOP -//! - \ref AUXTDC_WAIT_STOP_CNTDOWN -//! - \ref AUXTDC_GETRESULTS -//! - \ref AUXTDC_POR -//! - \ref AUXTDC_WAIT_CLRCNT_DONE -//! - \ref AUXTDC_START_FALL -//! - \ref AUXTDC_FORCE_STOP. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AUXTDCStatusGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Return the status value for the correct ADI Slave. - return((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) >> - AUX_TDC_STAT_STATE_S); -} - -//***************************************************************************** -// -//! \brief Configure the operation of the AUX TDC. -//! -//! Use this function to configure the start and stop event for the AUX TDC. -//! -//! The \c ui32StartCondition must be a bitwise OR of the start event and the -//! polarity of the start event. The start events are: -//! - \ref AUXTDC_START_AUXIO0 -//! - \ref AUXTDC_START_AUXIO1 -//! - \ref AUXTDC_START_AUXIO2 -//! - \ref AUXTDC_START_AUXIO3 -//! - \ref AUXTDC_START_AUXIO4 -//! - \ref AUXTDC_START_AUXIO5 -//! - \ref AUXTDC_START_AUXIO6 -//! - \ref AUXTDC_START_AUXIO7 -//! - \ref AUXTDC_START_AUXIO8 -//! - \ref AUXTDC_START_AUXIO9 -//! - \ref AUXTDC_START_AUXIO10 -//! - \ref AUXTDC_START_AUXIO11 -//! - \ref AUXTDC_START_AUXIO12 -//! - \ref AUXTDC_START_AUXIO13 -//! - \ref AUXTDC_START_AUXIO14 -//! - \ref AUXTDC_START_AUXIO15 -//! - \ref AUXTDC_START_AUXIO16 -//! - \ref AUXTDC_START_AUXIO17 -//! - \ref AUXTDC_START_AUXIO18 -//! - \ref AUXTDC_START_AUXIO19 -//! - \ref AUXTDC_START_AUXIO20 -//! - \ref AUXTDC_START_AUXIO21 -//! - \ref AUXTDC_START_AUXIO22 -//! - \ref AUXTDC_START_AUXIO23 -//! - \ref AUXTDC_START_AUXIO24 -//! - \ref AUXTDC_START_AUXIO25 -//! - \ref AUXTDC_START_AUXIO26 -//! - \ref AUXTDC_START_AUXIO27 -//! - \ref AUXTDC_START_AUXIO28 -//! - \ref AUXTDC_START_AUXIO29 -//! - \ref AUXTDC_START_AUXIO30 -//! - \ref AUXTDC_START_AUXIO31 -//! - \ref AUXTDC_START_MANUAL_EV -//! - \ref AUXTDC_START_AON_RTC_CH2_DLY -//! - \ref AUXTDC_START_AON_RTC_4KHZ -//! - \ref AUXTDC_START_AON_BATMON_BAT_UPD -//! - \ref AUXTDC_START_AON_BATMON_TEMP_UPD -//! - \ref AUXTDC_START_SCLK_LF -//! - \ref AUXTDC_START_PWR_DWN -//! - \ref AUXTDC_START_MCU_ACTIVE -//! - \ref AUXTDC_START_VDDR_RECHARGE -//! - \ref AUXTDC_START_TIMER2_EV0 -//! - \ref AUXTDC_START_TIMER2_EV1 -//! - \ref AUXTDC_START_TIMER2_EV2 -//! - \ref AUXTDC_START_TIMER2_EV3 -//! - \ref AUXTDC_START_TIMER2_PULSE -//! - \ref AUXTDC_START_TDC_DONE -//! - \ref AUXTDC_START_ADC_IRQ -//! - \ref AUXTDC_START_ADC_FIFO_NOT_EMPTY -//! - \ref AUXTDC_START_NO_EVENT -//! - \ref AUXTDC_START_ADC_DONE -//! - \ref AUXTDC_START_ADC_FIFO_ALMOST_FULL -//! - \ref AUXTDC_START_ISRC_RESET -//! - \ref AUXTDC_START_OBSMUX0 -//! - \ref AUXTDC_START_OBSMUX1 -//! - \ref AUXTDC_START_SMPH_AUTOTAKE_DONE -//! - \ref AUXTDC_START_TDC_PRE -//! - \ref AUXTDC_START_TIMER0_EV -//! - \ref AUXTDC_START_TIMER1_EV -//! - \ref AUXTDC_START_AON_RTC_CH2 -//! - \ref AUXTDC_START_AUX_COMPA -//! - \ref AUXTDC_START_AUX_COMPB -//! - \ref AUXTDC_START_ACLK_REF -//! - \ref AUXTDC_START_MCU_EV -//! -//! The polarity of the start event is either rising \ref AUXTDC_STARTPOL_RIS -//! or falling \ref AUXTDC_STARTPOL_FALL. -//! -//! The \c ui32StopCondition must be a bitwise OR of the stop event and the -//! polarity of the stop event. The stop events are: -//! - \ref AUXTDC_STOP_AUXIO0 -//! - \ref AUXTDC_STOP_AUXIO1 -//! - \ref AUXTDC_STOP_AUXIO2 -//! - \ref AUXTDC_STOP_AUXIO3 -//! - \ref AUXTDC_STOP_AUXIO4 -//! - \ref AUXTDC_STOP_AUXIO5 -//! - \ref AUXTDC_STOP_AUXIO6 -//! - \ref AUXTDC_STOP_AUXIO7 -//! - \ref AUXTDC_STOP_AUXIO8 -//! - \ref AUXTDC_STOP_AUXIO9 -//! - \ref AUXTDC_STOP_AUXIO10 -//! - \ref AUXTDC_STOP_AUXIO11 -//! - \ref AUXTDC_STOP_AUXIO12 -//! - \ref AUXTDC_STOP_AUXIO13 -//! - \ref AUXTDC_STOP_AUXIO14 -//! - \ref AUXTDC_STOP_AUXIO15 -//! - \ref AUXTDC_STOP_AUXIO16 -//! - \ref AUXTDC_STOP_AUXIO17 -//! - \ref AUXTDC_STOP_AUXIO18 -//! - \ref AUXTDC_STOP_AUXIO19 -//! - \ref AUXTDC_STOP_AUXIO20 -//! - \ref AUXTDC_STOP_AUXIO21 -//! - \ref AUXTDC_STOP_AUXIO22 -//! - \ref AUXTDC_STOP_AUXIO23 -//! - \ref AUXTDC_STOP_AUXIO24 -//! - \ref AUXTDC_STOP_AUXIO25 -//! - \ref AUXTDC_STOP_AUXIO26 -//! - \ref AUXTDC_STOP_AUXIO27 -//! - \ref AUXTDC_STOP_AUXIO28 -//! - \ref AUXTDC_STOP_AUXIO29 -//! - \ref AUXTDC_STOP_AUXIO30 -//! - \ref AUXTDC_STOP_AUXIO31 -//! - \ref AUXTDC_STOP_MANUAL_EV -//! - \ref AUXTDC_STOP_AON_RTC_CH2_DLY -//! - \ref AUXTDC_STOP_AON_RTC_4KHZ -//! - \ref AUXTDC_STOP_AON_BATMON_BAT_UPD -//! - \ref AUXTDC_STOP_AON_BATMON_TEMP_UPD -//! - \ref AUXTDC_STOP_SCLK_LF -//! - \ref AUXTDC_STOP_PWR_DWN -//! - \ref AUXTDC_STOP_MCU_ACTIVE -//! - \ref AUXTDC_STOP_VDDR_RECHARGE -//! - \ref AUXTDC_STOP_TIMER2_EV0 -//! - \ref AUXTDC_STOP_TIMER2_EV1 -//! - \ref AUXTDC_STOP_TIMER2_EV2 -//! - \ref AUXTDC_STOP_TIMER2_EV3 -//! - \ref AUXTDC_STOP_TIMER2_PULSE -//! - \ref AUXTDC_STOP_TDC_DONE -//! - \ref AUXTDC_STOP_ADC_IRQ -//! - \ref AUXTDC_STOP_ADC_FIFO_NOT_EMPTY -//! - \ref AUXTDC_STOP_NO_EVENT -//! - \ref AUXTDC_STOP_ADC_DONE -//! - \ref AUXTDC_STOP_ADC_FIFO_ALMOST_FULL -//! - \ref AUXTDC_STOP_ISRC_RESET -//! - \ref AUXTDC_STOP_OBSMUX0 -//! - \ref AUXTDC_STOP_OBSMUX1 -//! - \ref AUXTDC_STOP_SMPH_AUTOTAKE_DONE -//! - \ref AUXTDC_STOP_TDC_PRE -//! - \ref AUXTDC_STOP_TIMER0_EV -//! - \ref AUXTDC_STOP_TIMER1_EV -//! - \ref AUXTDC_STOP_AON_RTC_CH2 -//! - \ref AUXTDC_STOP_AUX_COMPA -//! - \ref AUXTDC_STOP_AUX_COMPB -//! - \ref AUXTDC_STOP_ACLK_REF -//! - \ref AUXTDC_STOP_MCU_EV -//! -//! The polarity of the stop event is either rising \ref AUXTDC_STOPPOL_RIS -//! or falling \ref AUXTDC_STOPPOL_FALL. -//! -//! \note The AUX TDC should only be configured when the AUX TDC is in the Idle -//! state. To ensure that software does not lock up, it is recommended to -//! ensure that the AUX TDC is actually in idle when calling \ref AUXTDCConfigSet(). -//! This can be tested using \ref AUXTDCIdle(). -//! -//! \param ui32Base is base address of the AUX TDC. -//! \param ui32StartCondition is AUX TDC a bitwise OR of a start event and polarity. -//! \param ui32StopCondition is AUX TDC a bitwise OR of a stop event and polarity. -//! -//! \return None -//! -//! \sa \ref AUXTDCConfigSet(), \ref AUXTDCIdle() -// -//***************************************************************************** -extern void AUXTDCConfigSet(uint32_t ui32Base, uint32_t ui32StartCondition, - uint32_t ui32StopCondition); - -//***************************************************************************** -// -//! \brief Check if the AUX TDC is in idle mode. -//! -//! This function can be used to check whether the AUX TDC internal state -//! machine is in idle mode. This is required before setting the polarity -//! of the start and stop event. -//! -//! \param ui32Base is the base address of the AUX TDC. -//! -//! \return Returns \c true if state machine is in idle and returns \c false -//! if the state machine is in any other state. -// -//***************************************************************************** -__STATIC_INLINE bool -AUXTDCIdle(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Check if the AUX TDC is in the Idle state. - return (((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE) ? true : false); -} - -//***************************************************************************** -// -//! \brief Enable the AUX TDC for a measurement. -//! -//! This function is used for arming the AUX TDC to begin a measurement as -//! soon as the start condition is met. There are two run modes: -//! - \ref AUX_TDC_RUNSYNC will wait for a falling event of the start pulse before -//! starting measurement on next rising edge of start. This guarantees an edge -//! triggered start and is recommended for frequency measurements. If the -//! first falling edge is close to the start command it may be missed, but -//! the TDC shall catch later falling edges and in any case guarantee a -//! measurement start synchronous to the rising edge of the start event. -//! - The \ref AUX_TDC_RUN is asynchronous start and asynchronous stop mode. Using -//! this a TDC measurement may start immediately if start is high and hence it -//! may not give precise edge to edge measurements. This mode is only -//! recommended when start pulse is guaranteed to arrive at least 7 clock -//! periods after command. -//! -//! \note The AUX TDC should be configured and in Idle mode before calling this -//! function. -//! -//! \param ui32Base is the base address of the AUX TDC. -//! \param ui32RunMode is the run mode for the AUX TDC. -//! - \ref AUX_TDC_RUNSYNC : Synchronous run mode. -//! - \ref AUX_TDC_RUN : Asynchronous run mode. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -AUXTDCEnable(uint32_t ui32Base, uint32_t ui32RunMode) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - ASSERT((ui32RunMode == AUX_TDC_RUN) || - (ui32RunMode == AUX_TDC_RUNSYNC)); - - // Enable the AUX TDC. - HWREG(ui32Base + AUX_TDC_O_CTL) = ui32RunMode; -} - -//***************************************************************************** -// -//! \brief Force the AUX TDC back to Idle mode. -//! -//! This function will force the AUX TDC in Idle mode. The internal state -//! machine will not go directly to Idle mode, so it is left to the programmer to -//! ensure that the state machine is in Idle mode before doing any new -//! configuration. This can be checked using \ref AUXTDCIdle(). -//! -//! \param ui32Base is the base address of the AUX TDC. -//! -//! \return None -//! -//! \sa \ref AUXTDCIdle() -// -//***************************************************************************** -__STATIC_INLINE void -AUXTDCIdleForce(uint32_t ui32Base) -{ - // Check the arguments - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Abort operation of AUX TDC and force into Idle mode. - HWREG(ui32Base + AUX_TDC_O_CTL) = AUX_TDC_CTL_CMD_ABORT; -} - -//***************************************************************************** -// -//! \brief Check if the AUX TDC is done measuring. -//! -//! This function can be used to check whether the AUX TDC has finished a -//! measurement. The AUX TDC may have completed a measurement for two reasons. -//! Either it finish successfully \ref AUX_TDC_DONE or it failed due to a timeout -//! \ref AUX_TDC_TIMEOUT. If the AUX TDC is still measuring it this function -//! will return \ref AUX_TDC_BUSY. -//! -//! \param ui32Base is the base address of the AUX TDC. -//! -//! \return Returns the current status of a measurement: -//! - \ref AUX_TDC_DONE : An AUX TDC measurement finished successfully. -//! - \ref AUX_TDC_TIMEOUT : An AUX TDC measurement failed due to timeout. -//! - \ref AUX_TDC_BUSY : An AUX TDC measurement is being performed. -// -//***************************************************************************** -extern uint32_t AUXTDCMeasurementDone(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Get the value of the latest measurement. -//! -//! This function is used for retrieving the value of the latest measurement -//! performed by the AUX TDC. -//! -//! \param ui32Base is the base address of the AUX TDC. -//! -//! \return Returns the result of the latest measurement. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AUXTDCMeasurementGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Return the measurement. - return (HWREG(ui32Base + AUX_TDC_O_RESULT)); -} - -//***************************************************************************** -// -//! \brief Set the saturation limit of the measurement. -//! -//! This function is used to set a saturation limit for the event accumulation -//! register. The saturation limit is defined as a bit width of the -//! accumulation register and therefore increases in power of 2. -//! -//! \param ui32Base is base address of the AUX TDC. -//! \param ui32Limit is the saturation limit. -//! - \ref AUXTDC_SAT_4096 -//! - \ref AUXTDC_SAT_8192 -//! - \ref AUXTDC_SAT_16384 -//! - \ref AUXTDC_SAT_32768 -//! - \ref AUXTDC_SAT_65536 -//! - \ref AUXTDC_SAT_131072 -//! - \ref AUXTDC_SAT_262144 -//! - \ref AUXTDC_SAT_524288 -//! - \ref AUXTDC_SAT_1048576 -//! - \ref AUXTDC_SAT_2097152 -//! - \ref AUXTDC_SAT_4194304 -//! - \ref AUXTDC_SAT_8388608 -//! - \ref AUXTDC_SAT_16777216 (default) -//! -//! \return None -//! -//! \note The actual value of the accumulation register might increase slightly beyond -//! the saturation value before the saturation takes effect. -//! -//! \sa \ref AUXTDCLimitGet() -// -//***************************************************************************** -__STATIC_INLINE void -AUXTDCLimitSet(uint32_t ui32Base, uint32_t ui32Limit) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - ASSERT(ui32Limit < AUXTDC_NUM_SAT_VALS); - - // Set the saturation limit. - HWREG(ui32Base + AUX_TDC_O_SATCFG) = ui32Limit; -} - -//***************************************************************************** -// -//! \brief Get the saturation limit of the measurement. -//! -//! This function is used to retrieve the current saturation for the -//! accumulator register. -//! -//! \param ui32Base is base address of the AUX TDC. -//! -//! \return Returns the saturation limit. -//! - \ref AUXTDC_SAT_4096 -//! - \ref AUXTDC_SAT_8192 -//! - \ref AUXTDC_SAT_16384 -//! - \ref AUXTDC_SAT_32768 -//! - \ref AUXTDC_SAT_65536 -//! - \ref AUXTDC_SAT_131072 -//! - \ref AUXTDC_SAT_262144 -//! - \ref AUXTDC_SAT_524288 -//! - \ref AUXTDC_SAT_1048576 -//! - \ref AUXTDC_SAT_2097152 -//! - \ref AUXTDC_SAT_4194304 -//! - \ref AUXTDC_SAT_8388608 -//! - \ref AUXTDC_SAT_16777216 -//! -//! \sa \ref AUXTDCLimitSet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AUXTDCLimitGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Return the saturation limit. - return (HWREG(ui32Base + AUX_TDC_O_SATCFG)); -} - -//***************************************************************************** -// -//! \brief Enables the counter if possible. -//! -//! This function can be used to enable the AUX TDC stop/compare event counter. -//! The counter can be used to measure multiple periods of a clock signal. -//! For each stop/compare event the counter will be decremented by one and -//! the measurement will continue running until the value of the counter -//! reaches 0. The current value of the counter can be read using -//! \ref AUXTDCCounterGet(). The reset value of the counter can be set using -//! \ref AUXTDCCounterSet(). -//! -//! \param ui32Base is base address of the AUX TDC. -//! -//! \return Returns \c true if the counter was successfully enabled. If the -//! AUX TDC is not in Idle mode, the counter can not be enabled, and the -//! return value will be \c false. -//! -//! \sa \ref AUXTDCCounterGet(), \ref AUXTDCCounterSet() -// -//***************************************************************************** -__STATIC_INLINE bool -AUXTDCCounterEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Check if the AUX TDC is in idle mode. If not in Idle mode, the counter - // will not be enabled. - if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) - { - return false; - } - - // Enable the counter. - HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = AUX_TDC_TRIGCNTCFG_EN; - - // Counter successfully enabled. - return true; -} - -//***************************************************************************** -// -//! \brief Disables the counter if possible. -//! -//! This function can be used to disable the AUX TDC stop/compare event counter. -//! -//! \param ui32Base is base address of the AUX TDC. -//! -//! \return Returns \c true if the counter was successfully disabled. If the -//! AUX TDC is not in Idle mode, the counter can not be disabled, and the -//! return value will be \c false. -//! -//! \sa \ref AUXTDCCounterEnable() for more information on how to use the counter. -// -//***************************************************************************** -__STATIC_INLINE bool -AUXTDCCounterDisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Check if the AUX TDC is in Idle mode. If not in Idle mode, the counter - // will not be disabled. - if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) - { - return false; - } - - // Disable the counter. - HWREG(ui32Base + AUX_TDC_O_TRIGCNTCFG) = 0; - - // Counter successfully disabled. - return true; -} - -//***************************************************************************** -// -//! \brief Set the reset number of counter compare/stop event to ignore before taking -//! a measurement. -//! -//! This function loads the reset value of the counter with the specified -//! number of events to ignore. A reset in this context means the counter -//! has been disabled and then enabled. -//! -//! \param ui32Base is base address of the AUX TDC. -//! \param ui32Events is the number of compare/stop events to load into the -//! counter. -//! -//! \return Returns \c true if the counter was successfully updated. If the -//! AUX TDC is not in Idle mode, the counter can not be updated, and the -//! return value will be \c false. -//! -//! \sa \ref AUXTDCCounterEnable() -// -//***************************************************************************** -__STATIC_INLINE bool -AUXTDCCounterSet(uint32_t ui32Base, uint32_t ui32Events) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Check if the AUX TDC is in idle mode. If not in idle mode, the counter - // will not be disabled. - if(!((HWREG(ui32Base + AUX_TDC_O_STAT) & AUX_TDC_STAT_STATE_M) == - AUX_TDC_STAT_STATE_IDLE)) - { - return false; - } - - // Update the reset counter value. - HWREG(ui32Base + AUX_TDC_O_TRIGCNTLOAD) = ui32Events; - - // Counter successfully updated. - return true; -} - -//***************************************************************************** -// -//! \brief Get the current number of counter compare/stop event to ignore before -//! taking a measurement. -//! -//! This function returns the current value of compare/stop events before -//! a measurement is registered. This value is decremented by one for each -//! registered compare/stop event and will always be less than or equal the -//! reset value of the counter set using \ref AUXTDCCounterSet(). -//! -//! \param ui32Base is base address of the AUX TDC. -//! -//! \return Returns the current value of compare/stop events ignored before a -//! measurement is performed. -//! -//! \sa \ref AUXTDCCounterEnable(). -// -//***************************************************************************** -__STATIC_INLINE uint32_t -AUXTDCCounterGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(AUXTDCBaseValid(ui32Base)); - - // Return the current counter value. - return (HWREG(ui32Base + AUX_TDC_O_TRIGCNT)); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_AUXTDCConfigSet - #undef AUXTDCConfigSet - #define AUXTDCConfigSet ROM_AUXTDCConfigSet - #endif - #ifdef ROM_AUXTDCMeasurementDone - #undef AUXTDCMeasurementDone - #define AUXTDCMeasurementDone ROM_AUXTDCMeasurementDone - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AUX_TDC_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.c deleted file mode 100644 index 9f0e8d7aa21..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.c +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: ccfgread.c -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: API for reading CCFG. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "ccfgread.h" - -// See ccfgread.h for implementation diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h deleted file mode 100644 index a1e809d7765..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread.h +++ /dev/null @@ -1,187 +0,0 @@ -/****************************************************************************** -* Filename: ccfgread.h -* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) -* Revision: 47152 -* -* Description: API for reading CCFG. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup ccfgread_api -//! @{ -// -//***************************************************************************** - -#ifndef __CCFGREAD_H__ -#define __CCFGREAD_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ccfg.h" - -//***************************************************************************** -// -// General constants and defines -// -//***************************************************************************** - - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Read DIS_GPRAM from CCFG. -//! -//! \return Value of CCFG field CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM -// -//***************************************************************************** -__STATIC_INLINE bool -CCFGRead_DIS_GPRAM( void ) -{ - return (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & - CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) >> - CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) ; -} - -//***************************************************************************** -// -//! \brief Read EXT_LF_CLK_DIO from CCFG. -//! -//! \return Value of CCFG field CCFG_EXT_LF_CLK_DIO -// -//***************************************************************************** -__STATIC_INLINE bool -CCFGRead_EXT_LF_CLK_DIO( void ) -{ - return (( HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ) & - CCFG_EXT_LF_CLK_DIO_M ) >> - CCFG_EXT_LF_CLK_DIO_S ) ; -} - -//***************************************************************************** -// -// Defines the possible values returned from CCFGRead_SCLK_LF_OPTION() -// -//***************************************************************************** -#define CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) -#define CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) -#define CCFGREAD_SCLK_LF_OPTION_XOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) -#define CCFGREAD_SCLK_LF_OPTION_RCOSC_LF ( CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) - -//***************************************************************************** -// -//! \brief Read SCLK_LF_OPTION from CCFG. -//! -//! \return Returns the value of the CCFG field CCFG_MODE_CONF_SCLK_LF_OPTION field. -//! Returns one of the following: -//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_HF_DLF -//! - \ref CCFGREAD_SCLK_LF_OPTION_EXTERNAL_LF -//! - \ref CCFGREAD_SCLK_LF_OPTION_XOSC_LF -//! - \ref CCFGREAD_SCLK_LF_OPTION_RCOSC_LF -// -//***************************************************************************** -__STATIC_INLINE uint32_t -CCFGRead_SCLK_LF_OPTION( void ) -{ - return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & - CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> - CCFG_MODE_CONF_SCLK_LF_OPTION_S ) ; -} - -//***************************************************************************** -// -// Defines the possible values returned from CCFGRead_XOSC_FREQ() -// -//***************************************************************************** -#define CCFGREAD_XOSC_FREQ_24M ( CCFG_MODE_CONF_XOSC_FREQ_24M >> CCFG_MODE_CONF_XOSC_FREQ_S ) -#define CCFGREAD_XOSC_FREQ_48M ( CCFG_MODE_CONF_XOSC_FREQ_48M >> CCFG_MODE_CONF_XOSC_FREQ_S ) -#define CCFGREAD_XOSC_FREQ_HPOSC ( CCFG_MODE_CONF_XOSC_FREQ_HPOSC >> CCFG_MODE_CONF_XOSC_FREQ_S ) - -//***************************************************************************** -// -//! \brief Read XOSC_FREQ setting CCFG. -//! -//! \return Returns the value of the CCFG_MODE_CONF_XOSC_FREQ field. -//! Returns one of the following: -//! - \ref CCFGREAD_XOSC_FREQ_24M -//! - \ref CCFGREAD_XOSC_FREQ_48M -//! - \ref CCFGREAD_XOSC_FREQ_HPOSC -//! -// -//***************************************************************************** -__STATIC_INLINE uint32_t -CCFGRead_XOSC_FREQ( void ) -{ - return (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF ) & - CCFG_MODE_CONF_XOSC_FREQ_M ) >> - CCFG_MODE_CONF_XOSC_FREQ_S ) ; -} - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __AUX_SMPH_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h deleted file mode 100644 index 76946f1492e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ccfgread_doc.h +++ /dev/null @@ -1,51 +0,0 @@ -/****************************************************************************** -* Filename: ccfgread_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup ccfgread_api -//! @{ -//! \section sec_ccfgread Introduction -//! -//! The values of customer configuration (CCFG) settings in flash are determined by ccfg.c and typically -//! a user application does not need to read these CCFG values as they are used mainly during ROM boot -//! and device trimming. However, a subset of the CCFG settings need to be read by application -//! code thus DriverLib provides this API to allow easy read access to these specific settings. -//! -//! The remaining settings not accessible through this API can of course be read directly at the CCFG -//! addresses in the flash (starting at CCFG_BASE) using the HWREG macro and the provided defines. -//! CCFG settings are documented as part of the register descriptions in the CPU memory map. -//! -//! \note CCFG settings are located in flash and should be considered read-only from an application -//! point-of-view. -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.c deleted file mode 100644 index d0b00a182ae..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.c +++ /dev/null @@ -1,210 +0,0 @@ -/****************************************************************************** -* Filename: chipinfo.c -* Revised: 2018-08-17 09:28:06 +0200 (Fri, 17 Aug 2018) -* Revision: 52354 -* -* Description: Collection of functions returning chip information. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "chipinfo.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef ChipInfo_GetSupportedProtocol_BV - #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV - #undef ChipInfo_GetPackageType - #define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType - #undef ChipInfo_GetChipType - #define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType - #undef ChipInfo_GetChipFamily - #define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily - #undef ChipInfo_GetHwRevision - #define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision - #undef ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated - #define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated -#endif - -//***************************************************************************** -// -// ChipInfo_GetSupportedProtocol_BV() -// -//***************************************************************************** -ProtocolBitVector_t -ChipInfo_GetSupportedProtocol_BV( void ) -{ - return ((ProtocolBitVector_t)( HWREG( PRCM_BASE + 0x1D4 ) & 0x0E )); -} - -//***************************************************************************** -// -// ChipInfo_GetPackageType() -// -//***************************************************************************** -PackageType_t -ChipInfo_GetPackageType( void ) -{ - PackageType_t packType = (PackageType_t)(( - HWREG( FCFG1_BASE + FCFG1_O_USER_ID ) & - FCFG1_USER_ID_PKG_M ) >> - FCFG1_USER_ID_PKG_S ) ; - - if (( packType < PACKAGE_4x4 ) || - ( packType > PACKAGE_7x7_Q1 ) ) - { - packType = PACKAGE_Unknown; - } - - return ( packType ); -} - -//***************************************************************************** -// -// ChipInfo_GetChipFamily() -// -//***************************************************************************** -ChipFamily_t -ChipInfo_GetChipFamily( void ) -{ - uint32_t waferId ; - ChipFamily_t chipFam = FAMILY_Unknown ; - - waferId = (( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) & - FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M ) >> - FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S ) ; - - if ( waferId == 0xBB41 ) { - chipFam = FAMILY_CC13x2_CC26x2 ; - } - - return ( chipFam ); -} - -//***************************************************************************** -// -// ChipInfo_GetChipType() -// -//***************************************************************************** -ChipType_t -ChipInfo_GetChipType( void ) -{ - ChipType_t chipType = CHIP_TYPE_Unknown ; - ChipFamily_t chipFam = ChipInfo_GetChipFamily() ; - uint32_t fcfg1UserId = ChipInfo_GetUserId() ; - uint32_t fcfg1Protocol = (( fcfg1UserId & FCFG1_USER_ID_PROTOCOL_M ) >> - FCFG1_USER_ID_PROTOCOL_S ) ; - uint32_t fcfg1Cc13 = (( fcfg1UserId & FCFG1_USER_ID_CC13_M ) >> - FCFG1_USER_ID_CC13_S ) ; - uint32_t fcfg1Pa = (( fcfg1UserId & FCFG1_USER_ID_PA_M ) >> - FCFG1_USER_ID_PA_S ) ; - - if ( chipFam == FAMILY_CC13x2_CC26x2 ) { - switch ( fcfg1Protocol ) { - case 0xF : - if( fcfg1Cc13 ) { - if ( fcfg1Pa ) { - chipType = CHIP_TYPE_CC1352P ; - } else { - chipType = CHIP_TYPE_CC1352 ; - } - } else { - chipType = CHIP_TYPE_CC2652 ; - } - break; - case 0x9 : - if( fcfg1Pa ) { - chipType = CHIP_TYPE_unused ; - } else { - chipType = CHIP_TYPE_CC2642 ; - } - break; - case 0x8 : - chipType = CHIP_TYPE_CC1312 ; - break; - } - } - - return ( chipType ); -} - -//***************************************************************************** -// -// ChipInfo_GetHwRevision() -// -//***************************************************************************** -HwRevision_t -ChipInfo_GetHwRevision( void ) -{ - HwRevision_t hwRev = HWREV_Unknown ; - uint32_t fcfg1Rev = ChipInfo_GetDeviceIdHwRevCode() ; - uint32_t minorHwRev = ChipInfo_GetMinorHwRev() ; - ChipFamily_t chipFam = ChipInfo_GetChipFamily() ; - - if ( chipFam == FAMILY_CC13x2_CC26x2 ) { - switch ( fcfg1Rev ) { - case 0 : // CC13x2, CC26x2 - PG1.0 - case 1 : // CC13x2, CC26x2 - PG1.01 (will also show up as PG1.0) - hwRev = (HwRevision_t)((uint32_t)HWREV_1_0 ); - break; - case 2 : // CC13x2, CC26x2 - PG1.1 (or later) - hwRev = (HwRevision_t)(((uint32_t)HWREV_1_1 ) + minorHwRev ); - break; - case 3 : // CC13x2, CC26x2 - PG2.1 (or later) - hwRev = (HwRevision_t)(((uint32_t)HWREV_2_1 ) + minorHwRev ); - break; - } - } - - return ( hwRev ); -} - -//***************************************************************************** -// ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated() -//***************************************************************************** -void -ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated( void ) -{ - if (( ! ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) || - ( ! ChipInfo_HwRevisionIs_GTEQ_2_0() ) ) - { - while(1) - { - // This driverlib version is for the CC13x2/CC26x2 PG2.0 and later chips. - // Do nothing - stay here forever - } - } -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h deleted file mode 100644 index b02d5f8e820..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/chipinfo.h +++ /dev/null @@ -1,685 +0,0 @@ -/****************************************************************************** -* Filename: chipinfo.h -* Revised: 2018-06-18 10:26:12 +0200 (Mon, 18 Jun 2018) -* Revision: 52189 -* -* Description: Collection of functions returning chip information. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup ChipInfo -//! @{ -// -//***************************************************************************** - -#ifndef __CHIP_INFO_H__ -#define __CHIP_INFO_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_fcfg1.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define ChipInfo_GetSupportedProtocol_BV NOROM_ChipInfo_GetSupportedProtocol_BV - #define ChipInfo_GetPackageType NOROM_ChipInfo_GetPackageType - #define ChipInfo_GetChipType NOROM_ChipInfo_GetChipType - #define ChipInfo_GetChipFamily NOROM_ChipInfo_GetChipFamily - #define ChipInfo_GetHwRevision NOROM_ChipInfo_GetHwRevision - #define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated NOROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated -#endif - -//***************************************************************************** -// -//! \brief Enumeration identifying the protocols supported. -//! -//! \note -//! This is a bit vector enumeration that indicates supported protocols. -//! E.g: 0x06 means that the chip supports both BLE and IEEE 802.15.4 -// -//***************************************************************************** -typedef enum { - PROTOCOL_Unknown = 0 , //!< None of the known protocols are supported. - PROTOCOLBIT_BLE = 0x02, //!< Bit[1] set, indicates that Bluetooth Low Energy is supported. - PROTOCOLBIT_IEEE_802_15_4 = 0x04, //!< Bit[2] set, indicates that IEEE 802.15.4 is supported. - PROTOCOLBIT_Proprietary = 0x08 //!< Bit[3] set, indicates that proprietary protocols are supported. -} ProtocolBitVector_t; - -//***************************************************************************** -// -//! \brief Returns bit vector showing supported protocols. -//! -//! \return -//! Returns \ref ProtocolBitVector_t which is a bit vector indicating supported protocols. -// -//***************************************************************************** -extern ProtocolBitVector_t ChipInfo_GetSupportedProtocol_BV( void ); - -//***************************************************************************** -// -//! \brief Returns true if the chip supports the BLE protocol. -//! -//! \return -//! Returns \c true if supporting the BLE protocol, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_SupportsBLE( void ) -{ - return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_BLE ) != 0 ); -} - -//***************************************************************************** -// -//! \brief Returns true if the chip supports the IEEE 802.15.4 protocol. -//! -//! \return -//! Returns \c true if supporting the IEEE 802.15.4 protocol, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_SupportsIEEE_802_15_4( void ) -{ - return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_IEEE_802_15_4 ) != 0 ); -} - -//***************************************************************************** -// -//! \brief Returns true if the chip supports proprietary protocols. -//! -//! \return -//! Returns \c true if supporting proprietary protocols, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_SupportsPROPRIETARY( void ) -{ - return (( ChipInfo_GetSupportedProtocol_BV() & PROTOCOLBIT_Proprietary ) != 0 ); -} - -//***************************************************************************** -// -//! \brief Package type enumeration -//! -//! \note -//! Packages available for a specific device are shown in the device datasheet. -// -//***************************************************************************** -typedef enum { - PACKAGE_Unknown = -1, //!< -1 means that current package type is unknown. - PACKAGE_4x4 = 0, //!< 0 means that this is a 4x4 mm QFN (RHB) package. - PACKAGE_5x5 = 1, //!< 1 means that this is a 5x5 mm QFN (RSM) package. - PACKAGE_7x7 = 2, //!< 2 means that this is a 7x7 mm QFN (RGZ) package. - PACKAGE_WAFER = 3, //!< 3 means that this is a wafer sale package (naked die). - PACKAGE_WCSP = 4, //!< 4 means that this is a 2.7x2.7 mm WCSP (YFV). - PACKAGE_7x7_Q1 = 5 //!< 5 means that this is a 7x7 mm QFN package with Wettable Flanks. -} PackageType_t; - -//***************************************************************************** -// -//! \brief Returns package type. -//! -//! \return -//! Returns \ref PackageType_t -// -//***************************************************************************** -extern PackageType_t ChipInfo_GetPackageType( void ); - -//***************************************************************************** -// -//! \brief Returns true if this is a 4x4mm chip. -//! -//! \return -//! Returns \c true if this is a 4x4mm chip, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_PackageTypeIs4x4( void ) -{ - return ( ChipInfo_GetPackageType() == PACKAGE_4x4 ); -} - -//***************************************************************************** -// -//! \brief Returns true if this is a 5x5mm chip. -//! -//! \return -//! Returns \c true if this is a 5x5mm chip, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_PackageTypeIs5x5( void ) -{ - return ( ChipInfo_GetPackageType() == PACKAGE_5x5 ); -} - -//***************************************************************************** -// -//! \brief Returns true if this is a 7x7mm chip. -//! -//! \return -//! Returns \c true if this is a 7x7mm chip, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_PackageTypeIs7x7( void ) -{ - return ( ChipInfo_GetPackageType() == PACKAGE_7x7 ); -} - -//***************************************************************************** -// -//! \brief Returns true if this is a wafer sale chip (naked die). -//! -//! \return -//! Returns \c true if this is a wafer sale chip, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_PackageTypeIsWAFER( void ) -{ - return ( ChipInfo_GetPackageType() == PACKAGE_WAFER ); -} - -//***************************************************************************** -// -//! \brief Returns true if this is a WCSP chip (flip chip). -//! -//! \return -//! Returns \c true if this is a WCSP chip, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_PackageTypeIsWCSP( void ) -{ - return ( ChipInfo_GetPackageType() == PACKAGE_WCSP ); -} - -//***************************************************************************** -// -//! \brief Returns true if this is a 7x7 Q1 chip. -//! -//! \return -//! Returns \c true if this is a 7x7 Q1 chip, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_PackageTypeIs7x7Q1( void ) -{ - return ( ChipInfo_GetPackageType() == PACKAGE_7x7_Q1 ); -} - -//***************************************************************************** -// -//! \brief Returns the internal chip HW revision code. -//! -//! \return -//! Returns the internal chip HW revision code (in range 0-15) -//***************************************************************************** -__STATIC_INLINE uint32_t -ChipInfo_GetDeviceIdHwRevCode( void ) -{ - // Returns HwRevCode = FCFG1_O_ICEPICK_DEVICE_ID[31:28] - return ( HWREG( FCFG1_BASE + FCFG1_O_ICEPICK_DEVICE_ID ) >> 28 ); -} - -//***************************************************************************** -// -//! \brief Returns minor hardware revision number -//! -//! The minor revision number is set to 0 for the first market released chip -//! and thereafter incremented by 1 for each minor hardware change. -//! -//! \return -//! Returns the minor hardware revision number (in range 0-127) -// -//***************************************************************************** -__STATIC_INLINE uint32_t -ChipInfo_GetMinorHwRev( void ) -{ - uint32_t minorRev = (( HWREG( FCFG1_BASE + FCFG1_O_MISC_CONF_1 ) & - FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M ) >> - FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S ) ; - - if ( minorRev >= 0x80 ) { - minorRev = 0; - } - - return( minorRev ); -} - -//***************************************************************************** -// -//! \brief Returns the 32 bits USER_ID field -//! -//! How to decode the USER_ID filed is described in the Technical Reference Manual (TRM) -//! -//! \return -//! Returns the 32 bits USER_ID field -// -//***************************************************************************** -__STATIC_INLINE uint32_t -ChipInfo_GetUserId( void ) -{ - return ( HWREG( FCFG1_BASE + FCFG1_O_USER_ID )); -} - -//***************************************************************************** -// -//! \brief Chip type enumeration -// -//***************************************************************************** -typedef enum { - CHIP_TYPE_Unknown = -1, //!< -1 means that the chip type is unknown. - CHIP_TYPE_CC1310 = 0, //!< 0 means that this is a CC1310 chip. - CHIP_TYPE_CC1350 = 1, //!< 1 means that this is a CC1350 chip. - CHIP_TYPE_CC2620 = 2, //!< 2 means that this is a CC2620 chip. - CHIP_TYPE_CC2630 = 3, //!< 3 means that this is a CC2630 chip. - CHIP_TYPE_CC2640 = 4, //!< 4 means that this is a CC2640 chip. - CHIP_TYPE_CC2650 = 5, //!< 5 means that this is a CC2650 chip. - CHIP_TYPE_CUSTOM_0 = 6, //!< 6 means that this is a CUSTOM_0 chip. - CHIP_TYPE_CUSTOM_1 = 7, //!< 7 means that this is a CUSTOM_1 chip. - CHIP_TYPE_CC2640R2 = 8, //!< 8 means that this is a CC2640R2 chip. - CHIP_TYPE_CC2642 = 9, //!< 9 means that this is a CC2642 chip. - CHIP_TYPE_unused = 10,//!< 10 unused value - CHIP_TYPE_CC2652 = 11,//!< 11 means that this is a CC2652 chip. - CHIP_TYPE_CC1312 = 12,//!< 12 means that this is a CC1312 chip. - CHIP_TYPE_CC1352 = 13,//!< 13 means that this is a CC1352 chip. - CHIP_TYPE_CC1352P = 14 //!< 14 means that this is a CC1352P chip. -} ChipType_t; - -//***************************************************************************** -// -//! \brief Returns chip type. -//! -//! \return -//! Returns \ref ChipType_t -// -//***************************************************************************** -extern ChipType_t ChipInfo_GetChipType( void ); - -//***************************************************************************** -// -//! \brief Chip family enumeration -// -//***************************************************************************** -typedef enum { - FAMILY_Unknown = -1, //!< -1 means that the chip's family member is unknown. - FAMILY_CC26x0 = 0, //!< 0 means that the chip is a CC26x0 family member. - FAMILY_CC13x0 = 1, //!< 1 means that the chip is a CC13x0 family member. - FAMILY_CC26x1 = 2, //!< 2 means that the chip is a CC26x1 family member. - FAMILY_CC26x0R2 = 3, //!< 3 means that the chip is a CC26x0R2 family (new ROM contents). - FAMILY_CC13x2_CC26x2 = 4 //!< 4 means that the chip is a CC13x2, CC26x2 family member. -} ChipFamily_t; - -//***************************************************************************** -// -//! \brief Returns chip family member. -//! -//! \return -//! Returns \ref ChipFamily_t -// -//***************************************************************************** -extern ChipFamily_t ChipInfo_GetChipFamily( void ); - -//***************************************************************************** -// -// Options for the define THIS_DRIVERLIB_BUILD -// -//***************************************************************************** -#define DRIVERLIB_BUILD_CC26X0 0 //!< 0 is the driverlib build ID for the cc26x0 driverlib. -#define DRIVERLIB_BUILD_CC13X0 1 //!< 1 is the driverlib build ID for the cc13x0 driverlib. -#define DRIVERLIB_BUILD_CC26X1 2 //!< 2 is the driverlib build ID for the cc26x1 driverlib. -#define DRIVERLIB_BUILD_CC26X0R2 3 //!< 3 is the driverlib build ID for the cc26x0r2 driverlib. -#define DRIVERLIB_BUILD_CC13X2_CC26X2 4 //!< 4 is the driverlib build ID for the cc13x2_cc26x2 driverlib. - -//***************************************************************************** -// -//! \brief Define THIS_DRIVERLIB_BUILD, identifying current driverlib build ID. -//! -//! This driverlib build identifier can be useful for compile time checking/optimization (supporting C preprocessor expressions). -// -//***************************************************************************** -#define THIS_DRIVERLIB_BUILD DRIVERLIB_BUILD_CC13X2_CC26X2 - -//***************************************************************************** -// -//! \brief Returns true if this chip is member of the CC13x0 family. -//! -//! \return -//! Returns \c true if this chip is member of the CC13x0 family, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC13x0( void ) -{ - return ( ChipInfo_GetChipFamily() == FAMILY_CC13x0 ); -} - -//***************************************************************************** -// -//! \brief Returns true if this chip is member of the CC26x0 family. -//! -//! \return -//! Returns \c true if this chip is member of the CC26x0 family, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC26x0( void ) -{ - return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0 ); -} - -//***************************************************************************** -// -//! \brief Returns true if this chip is member of the CC26x0R2 family. -//! -//! \return -//! Returns \c true if this chip is member of the CC26x0R2 family, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC26x0R2( void ) -{ - return ( ChipInfo_GetChipFamily() == FAMILY_CC26x0R2 ); -} - -//***************************************************************************** -// -//! \brief Returns true if this chip is member of the CC26x1 family. -//! -//! \return -//! Returns \c true if this chip is member of the CC26x1 family, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC26x1( void ) -{ - return ( ChipInfo_GetChipFamily() == FAMILY_CC26x1 ); -} - -//***************************************************************************** -// -//! \brief Returns true if this chip is member of the CC13x2, CC26x2 family. -//! -//! \return -//! Returns \c true if this chip is member of the CC13x2, CC26x2 family, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_ChipFamilyIs_CC13x2_CC26x2( void ) -{ - return ( ChipInfo_GetChipFamily() == FAMILY_CC13x2_CC26x2 ); -} - -//***************************************************************************** -// -//! \brief HW revision enumeration. -// -//***************************************************************************** -typedef enum { - HWREV_Unknown = -1, //!< -1 means that the chip's HW revision is unknown. - HWREV_1_0 = 10, //!< 10 means that the chip's HW revision is 1.0 - HWREV_1_1 = 11, //!< 11 means that the chip's HW revision is 1.1 - HWREV_2_0 = 20, //!< 20 means that the chip's HW revision is 2.0 - HWREV_2_1 = 21, //!< 21 means that the chip's HW revision is 2.1 - HWREV_2_2 = 22, //!< 22 means that the chip's HW revision is 2.2 - HWREV_2_3 = 23, //!< 23 means that the chip's HW revision is 2.3 - HWREV_2_4 = 24 //!< 24 means that the chip's HW revision is 2.4 -} HwRevision_t; - -//***************************************************************************** -// -//! \brief Returns chip HW revision. -//! -//! \return -//! Returns \ref HwRevision_t -// -//***************************************************************************** -extern HwRevision_t ChipInfo_GetHwRevision( void ); - -//***************************************************************************** -// -//! \brief Returns true if HW revision for this chip is 1.0. -//! -//! \return -//! Returns \c true if HW revision for this chip is 1.0, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_HwRevisionIs_1_0( void ) -{ - return ( ChipInfo_GetHwRevision() == HWREV_1_0 ); -} - -//***************************************************************************** -// -//! \brief Returns true if HW revision for this chip is 2.0. -//! -//! \return -//! Returns \c true if HW revision for this chip is 2.0, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_HwRevisionIs_2_0( void ) -{ - return ( ChipInfo_GetHwRevision() == HWREV_2_0 ); -} - -//***************************************************************************** -// -//! \brief Returns true if HW revision for this chip is 2.0 or greater. -//! -//! \return -//! Returns \c true if HW revision for this chip is 2.0 or greater, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_0( void ) -{ - return ( ChipInfo_GetHwRevision() >= HWREV_2_0 ); -} - -//***************************************************************************** -// -//! \brief Returns true if HW revision for this chip is 2.1. -//! -//! \return -//! Returns \c true if HW revision for this chip is 2.1, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_HwRevisionIs_2_1( void ) -{ - return ( ChipInfo_GetHwRevision() == HWREV_2_1 ); -} - -//***************************************************************************** -// -//! \brief Returns true if HW revision for this chip is 2.1 or greater. -//! -//! \return -//! Returns \c true if HW revision for this chip is 2.1 or greater, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_1( void ) -{ - return ( ChipInfo_GetHwRevision() >= HWREV_2_1 ); -} - -//***************************************************************************** -// -//! \brief Returns true if HW revision for this chip is 2.2. -//! -//! \return -//! Returns \c true if HW revision for this chip is 2.2, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_HwRevisionIs_2_2( void ) -{ - return ( ChipInfo_GetHwRevision() == HWREV_2_2 ); -} - -//***************************************************************************** -// -//! \brief Returns true if HW revision for this chip is 2.2 or greater. -//! -//! \return -//! Returns \c true if HW revision for this chip is 2.2 or greater, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_2( void ) -{ - return ( ChipInfo_GetHwRevision() >= HWREV_2_2 ); -} - -//***************************************************************************** -// -//! \brief Returns true if HW revision for this chip is 2.3 or greater. -//! -//! \return -//! Returns \c true if HW revision for this chip is 2.3 or greater, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_3( void ) -{ - return ( ChipInfo_GetHwRevision() >= HWREV_2_3 ); -} - -//***************************************************************************** -// -//! \brief Returns true if HW revision for this chip is 2.4 or greater. -//! -//! \return -//! Returns \c true if HW revision for this chip is 2.4 or greater, \c false otherwise. -// -//***************************************************************************** -__STATIC_INLINE bool -ChipInfo_HwRevisionIs_GTEQ_2_4( void ) -{ - return ( ChipInfo_GetHwRevision() >= HWREV_2_4 ); -} - -//***************************************************************************** -// -//! \brief Verifies that current chip is CC13x2 or CC26x2 PG2.0 or later and never returns if violated. -//! -//! \return None -// -//***************************************************************************** -extern void ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated( void ); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_ChipInfo_GetSupportedProtocol_BV - #undef ChipInfo_GetSupportedProtocol_BV - #define ChipInfo_GetSupportedProtocol_BV ROM_ChipInfo_GetSupportedProtocol_BV - #endif - #ifdef ROM_ChipInfo_GetPackageType - #undef ChipInfo_GetPackageType - #define ChipInfo_GetPackageType ROM_ChipInfo_GetPackageType - #endif - #ifdef ROM_ChipInfo_GetChipType - #undef ChipInfo_GetChipType - #define ChipInfo_GetChipType ROM_ChipInfo_GetChipType - #endif - #ifdef ROM_ChipInfo_GetChipFamily - #undef ChipInfo_GetChipFamily - #define ChipInfo_GetChipFamily ROM_ChipInfo_GetChipFamily - #endif - #ifdef ROM_ChipInfo_GetHwRevision - #undef ChipInfo_GetHwRevision - #define ChipInfo_GetHwRevision ROM_ChipInfo_GetHwRevision - #endif - #ifdef ROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated - #undef ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated - #define ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated ROM_ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __CHIP_INFO_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.c deleted file mode 100644 index 14d549e8b68..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.c +++ /dev/null @@ -1,396 +0,0 @@ -/****************************************************************************** -* Filename: cpu.c -* Revised: 2018-05-08 10:04:01 +0200 (Tue, 08 May 2018) -* Revision: 51972 -* -* Description: Instruction wrappers for special CPU instructions needed by -* the drivers. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "cpu.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef CPUcpsid - #define CPUcpsid NOROM_CPUcpsid - #undef CPUprimask - #define CPUprimask NOROM_CPUprimask - #undef CPUcpsie - #define CPUcpsie NOROM_CPUcpsie - #undef CPUbasepriGet - #define CPUbasepriGet NOROM_CPUbasepriGet - #undef CPUdelay - #define CPUdelay NOROM_CPUdelay -#endif - -//***************************************************************************** -// -// Disable all external interrupts -// -//***************************************************************************** -#if defined(DOXYGEN) -uint32_t -CPUcpsid(void) -{ - // This function is written in assembly. See cpu.c for compiler specific implementation. -} -#elif defined(__IAR_SYSTEMS_ICC__) -uint32_t -CPUcpsid(void) -{ - // Read PRIMASK and disable interrupts. - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n"); - - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUcpsid(void) -{ - // Read PRIMASK and disable interrupts. - mrs r0, PRIMASK; - cpsid i; - bx lr -} -#elif defined(__TI_COMPILER_VERSION__) -uint32_t -CPUcpsid(void) -{ - // Read PRIMASK and disable interrupts. - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " bx lr\n"); - - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - return(0); -} -#else -uint32_t __attribute__((naked)) -CPUcpsid(void) -{ - uint32_t ui32Ret; - - // Read PRIMASK and disable interrupts - __asm volatile (" mrs %0, PRIMASK\n" - " cpsid i\n" - " bx lr\n" - : "=r"(ui32Ret) - ); - - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - return(ui32Ret); -} -#endif - -//***************************************************************************** -// -// Get the current interrupt state -// -//***************************************************************************** -#if defined(DOXYGEN) -uint32_t -CPUprimask(void) -{ - // This function is written in assembly. See cpu.c for compiler specific implementation. -} -#elif defined(__IAR_SYSTEMS_ICC__) -uint32_t -CPUprimask(void) -{ - // Read PRIMASK. - __asm(" mrs r0, PRIMASK\n"); - - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUprimask(void) -{ - // Read PRIMASK. - mrs r0, PRIMASK; - bx lr -} -#elif defined(__TI_COMPILER_VERSION__) -uint32_t -CPUprimask(void) -{ - // Read PRIMASK. - __asm(" mrs r0, PRIMASK\n" - " bx lr\n"); - - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - return(0); -} -#else -uint32_t __attribute__((naked)) -CPUprimask(void) -{ - uint32_t ui32Ret; - - // Read PRIMASK - __asm volatile (" mrs %0, PRIMASK\n" - " bx lr\n" - : "=r"(ui32Ret) - ); - - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - return(ui32Ret); -} -#endif - -//***************************************************************************** -// -// Enable all external interrupts -// -//***************************************************************************** -#if defined(DOXYGEN) -uint32_t -CPUcpsie(void) -{ - // This function is written in assembly. See cpu.c for compiler specific implementation. -} -#elif defined(__IAR_SYSTEMS_ICC__) -uint32_t -CPUcpsie(void) -{ - // Read PRIMASK and enable interrupts. - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n"); - - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUcpsie(void) -{ - // Read PRIMASK and enable interrupts. - mrs r0, PRIMASK; - cpsie i; - bx lr -} -#elif defined(__TI_COMPILER_VERSION__) -uint32_t -CPUcpsie(void) -{ - // Read PRIMASK and enable interrupts. - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " bx lr\n"); - - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - return(0); -} -#else -uint32_t __attribute__((naked)) -CPUcpsie(void) -{ - uint32_t ui32Ret; - - // Read PRIMASK and enable interrupts. - __asm volatile (" mrs %0, PRIMASK\n" - " cpsie i\n" - " bx lr\n" - : "=r"(ui32Ret) - ); - - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - return(ui32Ret); -} -#endif - -//***************************************************************************** -// -// Get the interrupt priority disable level -// -//***************************************************************************** -#if defined(DOXYGEN) -uint32_t -CPUbasepriGet(void) -{ - // This function is written in assembly. See cpu.c for compiler specific implementation. -} -#elif defined(__IAR_SYSTEMS_ICC__) -uint32_t -CPUbasepriGet(void) -{ - // Read BASEPRI. - __asm(" mrs r0, BASEPRI\n"); - - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -__asm uint32_t -CPUbasepriGet(void) -{ - // Read BASEPRI. - mrs r0, BASEPRI; - bx lr -} -#elif defined(__TI_COMPILER_VERSION__) -uint32_t -CPUbasepriGet(void) -{ - // Read BASEPRI. - __asm(" mrs r0, BASEPRI\n" - " bx lr\n"); - - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - return(0); -} -#else -uint32_t __attribute__((naked)) -CPUbasepriGet(void) -{ - uint32_t ui32Ret; - - // Read BASEPRI. - __asm volatile (" mrs %0, BASEPRI\n" - " bx lr\n" - : "=r"(ui32Ret) - ); - - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - return(ui32Ret); -} -#endif -//***************************************************************************** -// -// Provide a small delay -// -//***************************************************************************** -#if defined(DOXYGEN) -void -CPUdelay(uint32_t ui32Count) -{ - // This function is written in assembly. See cpu.c for compiler specific implementation. -} -#elif defined(__IAR_SYSTEMS_ICC__) -void -CPUdelay(uint32_t ui32Count) -{ - // Loop the specified number of times - __asm("CPUdelay:\n" - " subs r0, #1\n" - " bne.n CPUdelay\n" - " bx lr"); -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -__asm void -CPUdelay(uint32_t ui32Count) -{ - // Delay the specified number of times (3 cycles pr. loop) -CPUdel - subs r0, #1; - bne CPUdel; - bx lr; -} -#elif defined(__TI_COMPILER_VERSION__) - // For CCS implement this function in pure assembly. This prevents the TI - // compiler from doing funny things with the optimizer. - - // Loop the specified number of times -__asm(" .sect \".text:NOROM_CPUdelay\"\n" - " .clink\n" - " .thumbfunc NOROM_CPUdelay\n" - " .thumb\n" - " .global NOROM_CPUdelay\n" - "NOROM_CPUdelay:\n" - " subs r0, #1\n" - " bne.n NOROM_CPUdelay\n" - " bx lr\n"); -#else -// GCC -void __attribute__((naked)) -CPUdelay(uint32_t ui32Count) -{ - // Loop the specified number of times - __asm volatile ("%=: subs %0, #1\n" - " bne %=b\n" - " bx lr\n" - : /* No output */ - : "r" (ui32Count) - ); -} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h deleted file mode 100644 index 13fda81dd02..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu.h +++ /dev/null @@ -1,466 +0,0 @@ -/****************************************************************************** -* Filename: cpu.h -* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) -* Revision: 52111 -* -* Description: Defines and prototypes for the CPU instruction wrapper -* functions. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_cpu_group -//! @{ -//! \addtogroup cpu_api -//! @{ -// -//***************************************************************************** - -#ifndef __CPU_H__ -#define __CPU_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_cpu_scs.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define CPUcpsid NOROM_CPUcpsid - #define CPUprimask NOROM_CPUprimask - #define CPUcpsie NOROM_CPUcpsie - #define CPUbasepriGet NOROM_CPUbasepriGet - #define CPUdelay NOROM_CPUdelay -#endif - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Disable all external interrupts. -//! -//! Use this function to disable all system interrupts. This function is -//! implemented as a wrapper function for the CPSID instruction. -//! -//! \return Returns the state of \b PRIMASK on entry -// -//***************************************************************************** -extern uint32_t CPUcpsid(void); - -//***************************************************************************** -// -//! \brief Get the current interrupt state. -//! -//! Use this function to retrieve the current state of the interrupts. This -//! function is implemented as a wrapper function returning the state of -//! PRIMASK. -//! -//! \return Returns the state of the \b PRIMASK (indicating whether interrupts -//! are enabled or disabled). -// -//***************************************************************************** -extern uint32_t CPUprimask(void); - -//***************************************************************************** -// -//! \brief Enable all external interrupts. -//! -//! Use this function to enable all system interrupts. This function is -//! implemented as a wrapper function for the CPSIE instruction. -//! -//! \return Returns the state of \b PRIMASK on entry. -// -//***************************************************************************** -extern uint32_t CPUcpsie(void); - -//***************************************************************************** -// -//! \brief Get the interrupt priority disable level. -//! -//! Use this function to get the level of priority that will disable -//! interrupts with a lower priority level. -//! -//! \return Returns the value of the \b BASEPRI register. -// -//***************************************************************************** -extern uint32_t CPUbasepriGet(void); - -//***************************************************************************** -// -//! \brief Provide a small non-zero delay using a simple loop counter. -//! -//! This function provides means for generating a constant length delay. It -//! is written in assembly to keep the delay consistent across tool chains, -//! avoiding the need to tune the delay based on the tool chain in use. -//! -//! \note It is not recommended using this function for long delays. -//! -//! Notice that interrupts can affect the delay if not manually disabled in advance. -//! -//! The delay depends on where code resides and the path for code fetching: -//! - Code in flash, cache enabled, prefetch enabled : 4 cycles per loop (Default) -//! - Code in flash, cache enabled, prefetch disabled : 5 cycles per loop -//! - Code in flash, cache disabled : 7 cycles per loop -//! - Code in SRAM : 6 cycles per loop -//! - Code in GPRAM : 3 cycles per loop -//! -//! \note If using an RTOS, consider using RTOS provided delay functions because -//! these will not block task scheduling and will potentially save power. -//! -//! Calculate delay count based on the wanted delay in microseconds (us): -//! - ui32Count = [delay in us] * [CPU clock in MHz] / [cycles per loop] -//! -//! Example: 250 us delay with code in flash and with cache and prefetch enabled: -//! - ui32Count = 250 * 48 / 4 = 3000 -//! -//! \param ui32Count is the number of delay loop iterations to perform. Number must be greater than zero. -//! -//! \return None -// -//***************************************************************************** -extern void CPUdelay(uint32_t ui32Count); - -//***************************************************************************** -// -//! \brief Wait for interrupt. -//! -//! Use this function to let the System CPU wait for the next interrupt. This -//! function is implemented as a wrapper function for the WFI instruction. -//! -//! \return None -// -//***************************************************************************** -#if defined(DOXYGEN) -__STATIC_INLINE void -CPUwfi(void) -{ - // This function is written in assembly. See cpu.h for compiler specific implementation. -} -#elif defined(__IAR_SYSTEMS_ICC__) -__STATIC_INLINE void -CPUwfi(void) -{ - // Wait for the next interrupt. - __asm(" wfi\n"); -} -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -__asm __STATIC_INLINE void -CPUwfi(void) -{ - // Wait for the next interrupt. - wfi; - bx lr -} -#elif defined(__TI_COMPILER_VERSION__) -__STATIC_INLINE void -CPUwfi(void) -{ - // Wait for the next interrupt. - __asm(" wfi\n"); -} -#else -__STATIC_INLINE void __attribute__((always_inline)) -CPUwfi(void) -{ - // Wait for the next interrupt. - __asm volatile (" wfi\n"); -} -#endif - -//***************************************************************************** -// -//! \brief Wait for event. -//! -//! Use this function to let the System CPU wait for the next event. This -//! function is implemented as a wrapper function for the WFE instruction. -//! -//! \return None -// -//***************************************************************************** -#if defined(DOXYGEN) -__STATIC_INLINE void -CPUwfe(void) -{ - // This function is written in assembly. See cpu.h for compiler specific implementation. -} -#elif defined(__IAR_SYSTEMS_ICC__) -__STATIC_INLINE void -CPUwfe(void) -{ - // Wait for the next event. - __asm(" wfe\n"); -} -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -__asm __STATIC_INLINE void -CPUwfe(void) -{ - // Wait for the next event. - wfe; - bx lr -} -#elif defined(__TI_COMPILER_VERSION__) -__STATIC_INLINE void -CPUwfe(void) -{ - // Wait for the next event. - __asm(" wfe\n"); -} -#else -__STATIC_INLINE void __attribute__((always_inline)) -CPUwfe(void) -{ - // Wait for the next event. - __asm volatile (" wfe\n"); -} -#endif - -//***************************************************************************** -// -//! \brief Send event. -//! -//! Use this function to let the System CPU send an event. This function is -//! implemented as a wrapper function for the SEV instruction. -//! -//! \return None -// -//***************************************************************************** -#if defined(DOXYGEN) -__STATIC_INLINE void -CPUsev(void) -{ - // This function is written in assembly. See cpu.h for compiler specific implementation. -} -#elif defined(__IAR_SYSTEMS_ICC__) -__STATIC_INLINE void -CPUsev(void) -{ - // Send event. - __asm(" sev\n"); -} -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -__asm __STATIC_INLINE void -CPUsev(void) -{ - // Send event. - sev; - bx lr -} -#elif defined(__TI_COMPILER_VERSION__) -__STATIC_INLINE void -CPUsev(void) -{ - // Send event. - __asm(" sev\n"); -} -#else -__STATIC_INLINE void __attribute__((always_inline)) -CPUsev(void) -{ - // Send event. - __asm volatile (" sev\n"); -} -#endif - - -//***************************************************************************** -// -//! \brief Update the interrupt priority disable level. -//! -//! Use this function to change the level of priority that will disable -//! interrupts with a lower priority level. -//! -//! \param ui32NewBasepri is the new basis priority level to set. -//! -//! \return None -// -//***************************************************************************** -#if defined(DOXYGEN) -__STATIC_INLINE void -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // This function is written in assembly. See cpu.h for compiler specific implementation. -} -#elif defined(__IAR_SYSTEMS_ICC__) -__STATIC_INLINE void -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // Set the BASEPRI register. - __asm(" msr BASEPRI, r0\n"); -} -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -__asm __STATIC_INLINE void -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // Set the BASEPRI register. - msr BASEPRI, r0; - bx lr -} -#elif defined(__TI_COMPILER_VERSION__) -__STATIC_INLINE void -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // Set the BASEPRI register. - __asm(" msr BASEPRI, r0\n"); -} -#else -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wattributes" -__STATIC_INLINE void __attribute__ ((naked)) -CPUbasepriSet(uint32_t ui32NewBasepri) -{ - // Set the BASEPRI register. - __asm volatile (" msr BASEPRI, %0\n" - " bx lr\n" - : /* No output */ - : "r" (ui32NewBasepri) - ); -} -#pragma GCC diagnostic pop -#endif - -//***************************************************************************** -// -//! \brief Disable CPU write buffering (recommended for debug purpose only). -//! -//! This function helps debugging "bus fault crashes". -//! Disables write buffer use during default memory map accesses. -//! -//! This causes all bus faults to be precise bus faults but decreases the -//! performance of the processor because the stores to memory have to complete -//! before the next instruction can be executed. -//! -//! \return None -//! -//! \sa \ref CPU_WriteBufferEnable() -// -//***************************************************************************** -__STATIC_INLINE void -CPU_WriteBufferDisable( void ) -{ - HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 1; -} - -//***************************************************************************** -// -//! \brief Enable CPU write buffering (default setting). -//! -//! Re-enables write buffer during default memory map accesses if -//! \ref CPU_WriteBufferDisable() has been used for bus fault debugging. -//! -//! \return None -//! -//! \sa \ref CPU_WriteBufferDisable() -// -//***************************************************************************** -__STATIC_INLINE void -CPU_WriteBufferEnable( void ) -{ - HWREGBITW( CPU_SCS_BASE + CPU_SCS_O_ACTLR, CPU_SCS_ACTLR_DISDEFWBUF_BITN ) = 0; -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_CPUcpsid - #undef CPUcpsid - #define CPUcpsid ROM_CPUcpsid - #endif - #ifdef ROM_CPUprimask - #undef CPUprimask - #define CPUprimask ROM_CPUprimask - #endif - #ifdef ROM_CPUcpsie - #undef CPUcpsie - #define CPUcpsie ROM_CPUcpsie - #endif - #ifdef ROM_CPUbasepriGet - #undef CPUbasepriGet - #define CPUbasepriGet ROM_CPUbasepriGet - #endif - #ifdef ROM_CPUdelay - #undef CPUdelay - #define CPUdelay ROM_CPUdelay - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __CPU_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h deleted file mode 100644 index 2981e8cf01b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/cpu_doc.h +++ /dev/null @@ -1,44 +0,0 @@ -/****************************************************************************** -* Filename: cpu_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup cpu_api -//! @{ -//! \section sec_cpu Introduction -//! -//! The CPU API provides a set of functions performing very low-level control of the system CPU. -//! All functions in this API are written in assembler in order to either access special registers -//! or avoid any compiler optimizations. Each function exists in several compiler specific versions: -//! One version for each supported compiler. -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.c deleted file mode 100644 index 1944f85a6f2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.c +++ /dev/null @@ -1,943 +0,0 @@ -/****************************************************************************** -* Filename: crypto.c -* Revised: 2017-12-20 16:40:03 +0100 (Wed, 20 Dec 2017) -* Revision: 50869 -* -* Description: Driver for the Crypto module -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "crypto.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef CRYPTOAesLoadKey - #define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey - #undef CRYPTOAesCbc - #define CRYPTOAesCbc NOROM_CRYPTOAesCbc - #undef CRYPTOAesCbcStatus - #define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus - #undef CRYPTOAesEcb - #define CRYPTOAesEcb NOROM_CRYPTOAesEcb - #undef CRYPTOAesEcbStatus - #define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus - #undef CRYPTOCcmAuthEncrypt - #define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt - #undef CRYPTOCcmAuthEncryptStatus - #define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus - #undef CRYPTOCcmAuthEncryptResultGet - #define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet - #undef CRYPTOCcmInvAuthDecrypt - #define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt - #undef CRYPTOCcmInvAuthDecryptStatus - #define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus - #undef CRYPTOCcmInvAuthDecryptResultGet - #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet - #undef CRYPTODmaEnable - #define CRYPTODmaEnable NOROM_CRYPTODmaEnable - #undef CRYPTODmaDisable - #define CRYPTODmaDisable NOROM_CRYPTODmaDisable -#endif - -//***************************************************************************** -// -// Write the key into the Key Ram. -// -//***************************************************************************** -uint32_t -CRYPTOAesLoadKey(uint32_t *pui32AesKey, - uint32_t ui32KeyLocation) -{ - uint32_t returnStatus = AES_KEYSTORE_READ_ERROR; - - // Check the arguments. - ASSERT((ui32KeyLocation == CRYPTO_KEY_AREA_0) | - (ui32KeyLocation == CRYPTO_KEY_AREA_1) | - (ui32KeyLocation == CRYPTO_KEY_AREA_2) | - (ui32KeyLocation == CRYPTO_KEY_AREA_3) | - (ui32KeyLocation == CRYPTO_KEY_AREA_4) | - (ui32KeyLocation == CRYPTO_KEY_AREA_5) | - (ui32KeyLocation == CRYPTO_KEY_AREA_6) | - (ui32KeyLocation == CRYPTO_KEY_AREA_7)); - - // Disable the external interrupt to stop the interrupt form propagating - // from the module to the System CPU. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - - // Clear any previously written key at the keyLocation - HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) = (0x00000001 << ui32KeyLocation); - - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | - CRYPTO_IRQEN_RESULT_AVAIL; - - // Configure master control module. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_ALGSEL, CRYPTO_ALGSEL_KEY_STORE_BITN) = 1; - - // Clear any outstanding events. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Configure key store module for 128 bit operation. - // Do not write to the register if the correct key size is already set. - // Writing to this register causes all current keys to be invalidated. - if (HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) != KEY_STORE_SIZE_128) { - HWREG(CRYPTO_BASE + CRYPTO_O_KEYSIZE) = KEY_STORE_SIZE_128; - } - - // Enable keys to write (e.g. Key 0). - HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITEAREA) = (0x00000001 << ui32KeyLocation); - - // Enable Crypto DMA channel 0. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Base address of the key in ext. memory. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32AesKey; - - // Total key length in bytes (e.g. 16 for 1 x 128-bit key). - // Writing the length of the key enables the DMA operation. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = KEY_BLENGTH; - - // Wait for the DMA operation to complete. - do - { - CPUdelay(1); - } - while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & - (CRYPTO_IRQSTAT_DMA_BUS_ERR_M | - CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M | - CRYPTO_IRQSTAT_DMA_IN_DONE | - CRYPTO_IRQSTAT_RESULT_AVAIL_M))); - - // Check for errors in DMA and key store. - if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & - (CRYPTO_IRQSTAT_DMA_BUS_ERR | - CRYPTO_IRQSTAT_KEY_ST_WR_ERR)) == 0) - { - // Acknowledge/clear the interrupt and disable the master control. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; - - // Check key status, return success if key valid. - if(HWREG(CRYPTO_BASE + CRYPTO_O_KEYWRITTENAREA) & (0x00000001 << ui32KeyLocation)) - { - returnStatus = AES_SUCCESS; - } - } - - // Return status. - return returnStatus; -} - -//***************************************************************************** -// -// Start an AES-CBC operation (encryption or decryption). -// -//***************************************************************************** -uint32_t -CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, uint32_t ui32MsgLength, - uint32_t *pui32Nonce, uint32_t ui32KeyLocation, - bool bEncrypt, bool bIntEnable) -{ - uint32_t ui32CtrlVal; - - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; - - // Clear any outstanding interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Wait for interrupt lines from module to be cleared - while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); - - // If using interrupts clear any pending interrupts and enable interrupts - // for the Crypto module. - if(bIntEnable) - { - IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); - IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); - } - - // Configure Master Control module. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; - - // Enable keys to read (e.g. Key 0). - HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; - - //Wait until key is loaded to the AES module. - do - { - CPUdelay(1); - } - while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); - - // Check for Key store Read error. - if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) - { - return (AES_KEYSTORE_READ_ERROR); - } - - // Write initialization vector. - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = pui32Nonce[0]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = pui32Nonce[1]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = pui32Nonce[2]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = pui32Nonce[3]; - - // Configure AES engine for AES-CBC with 128-bit key size. - ui32CtrlVal = (CRYPTO_AESCTL_SAVE_CONTEXT | CRYPTO_AESCTL_CBC); - if(bEncrypt) - { - ui32CtrlVal |= CRYPTO_AES128_ENCRYPT; - } - else - { - ui32CtrlVal |= CRYPTO_AES128_DECRYPT; - } - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; - - // Write the length of the crypto block (plain text). - // Low and high part (high part is assumed to be always 0). - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32MsgLength; - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; - HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = 0; - - // Enable Crypto DMA channel 0. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Base address of the input data in ext. memory. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn; - - // Input data length in bytes, equal to the message. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32MsgLength; - - // Enable Crypto DMA channel 1. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; - - // Set up the address and length of the output data. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut; - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32MsgLength; - - // Return success - return AES_SUCCESS; -} - -//***************************************************************************** -// -// Check the result of an AES CBC operation -// -//***************************************************************************** -uint32_t -CRYPTOAesCbcStatus(void) -{ - return(CRYPTOAesEcbStatus()); -} - -//***************************************************************************** -// -// Start an AES-ECB operation (encryption or decryption). -// -//***************************************************************************** -uint32_t -CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, - uint32_t ui32KeyLocation, bool bEncrypt, - bool bIntEnable) -{ - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; - - // Clear any outstanding interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Wait for interrupt lines from module to be cleared - while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); - - // If using interrupts clear any pending interrupts and enable interrupts - // for the Crypto module. - if(bIntEnable) - { - IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); - IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); - } - - // Configure Master Control module. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; - - // Enable keys to read (e.g. Key 0). - HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; - - //Wait until key is loaded to the AES module. - do - { - CPUdelay(1); - } - while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); - - // Check for Key store Read error. - if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) - { - return (AES_KEYSTORE_READ_ERROR); - } - - // Configure AES engine (program AES-ECB-128 encryption and no - // initialization vector - IV). - if(bEncrypt) - { - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_ENCRYPT; - } - else - { - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = CRYPTO_AES128_DECRYPT; - } - - // Write the length of the data. - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = AES_ECB_LENGTH; - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; - - // Enable Crypto DMA channel 0. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Base address of the input data in ext. memory. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32MsgIn; - - // Input data length in bytes, equal to the message. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = AES_ECB_LENGTH; - - // Enable Crypto DMA channel 1. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; - - // Set up the address and length of the output data. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)pui32MsgOut; - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = AES_ECB_LENGTH; - - // Return success - return AES_SUCCESS; -} - -//***************************************************************************** -// -// Check the result of an AES ECB operation -// -//***************************************************************************** -uint32_t -CRYPTOAesEcbStatus(void) -{ - uint32_t ui32Status; - - // Get the current DMA status. - ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); - - // Check if DMA is still busy. - if(ui32Status & CRYPTO_DMA_BSY) - { - return (AES_DMA_BSY); - } - - // Check the status of the DMA operation - return error if not success. - if(ui32Status & CRYPTO_DMA_BUS_ERROR) - { - return (AES_DMA_BUS_ERROR); - } - - // Operation successful - disable interrupt and return success. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - return (AES_SUCCESS); -} - -//***************************************************************************** -// -// Start CCM operation -// -//***************************************************************************** -uint32_t -CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength , - uint32_t *pui32Nonce, uint32_t *pui32PlainText, - uint32_t ui32PlainTextLength, uint32_t *pui32Header, - uint32_t ui32HeaderLength, uint32_t ui32KeyLocation, - uint32_t ui32FieldLength, bool bIntEnable) -{ - uint32_t ui32CtrlVal; - uint32_t i; - uint32_t *pui32CipherText; - union { - uint32_t w[4]; - uint8_t b[16]; - } ui8InitVec; - - // Input address for the encryption engine is the same as the output. - pui32CipherText = pui32PlainText; - - // Disable global interrupt, enable local interrupt and clear any pending - // interrupts. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | - CRYPTO_IRQEN_RESULT_AVAIL; - - // Configure master control module for AES operation. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; - - // Enable keys to read (e.g. Key 0). - HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; - - // Wait until key is loaded to the AES module. - do - { - CPUdelay(1); - } - while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); - - // Check for Key store Read error. - if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) - { - return (AES_KEYSTORE_READ_ERROR); - } - - // Prepare the initialization vector (IV), - // Length of Nonce l(n) = 15 - ui32FieldLength. - ui8InitVec.b[0] = ui32FieldLength - 1; - for(i = 0; i < 12; i++) - { - ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i]; - } - if(ui32FieldLength == 2) - { - ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12]; - } - else - { - ui8InitVec.b[13] = 0; - } - ui8InitVec.b[14] = 0; - ui8InitVec.b[15] = 0; - - // Write initialization vector. - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3]; - - // Configure AES engine. - ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S); - if ( ui32AuthLength >= 2 ) { - ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); - } - ui32CtrlVal |= CRYPTO_AESCTL_CCM; - ui32CtrlVal |= CRYPTO_AESCTL_CTR; - ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT; - ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S); - ui32CtrlVal |= (1 << CRYPTO_AESCTL_DIR_S); - ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S); - - // Write the configuration for 128 bit AES-CCM. - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; - - // Write the length of the crypto block (plain text). - // Low and high part (high part is assumed to be always 0). - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32PlainTextLength; - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; - - // Write the length of the header field. - // Also called AAD - Additional Authentication Data. - HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength; - - // Check if any header information (AAD). - // If so configure the DMA controller to fetch the header. - if(ui32HeaderLength != 0) - { - // Enable DMA channel 0. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Register the base address of the header (AAD). - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header; - - // Header length in bytes (may be non-block size aligned). - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength; - - // Wait for completion of the header data transfer, DMA_IN_DONE. - do - { - CPUdelay(1); - } - while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE)); - - // Check for DMA errors. - if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR) - { - return AES_DMA_BUS_ERROR; - } - } - - // Clear interrupt status. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Wait for interrupt lines from module to be cleared - while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); - - // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only - // want interrupt to trigger once RESULT_AVAIL occurs. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE; - - - // Is using interrupts enable globally. - if(bIntEnable) - { - IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); - IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); - } - - // Enable interrupts locally. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; - - // Perform encryption if requested. - if(bEncrypt) - { - // Enable DMA channel 0 - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // base address of the payload data in ext. memory. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = - (uint32_t)pui32PlainText; - - // Enable DMA channel 1 - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; - - // Base address of the output data buffer. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = - (uint32_t)pui32CipherText; - - // Payload data length in bytes, equal to the plaintext length. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32PlainTextLength; - // Output data length in bytes, equal to the plaintext length. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32PlainTextLength; - } - - return AES_SUCCESS; -} - -//***************************************************************************** -// -// Check the result of an AES CCM operation. -// -//***************************************************************************** -uint32_t -CRYPTOCcmAuthEncryptStatus(void) -{ - uint32_t ui32Status; - - // Get the current DMA status. - ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); - - // Check if DMA is still busy. - if(ui32Status & CRYPTO_DMA_BSY) - { - return (AES_DMA_BSY); - } - - // Check the status of the DMA operation - return error if not success. - if(ui32Status & CRYPTO_DMA_BUS_ERROR) - { - return (AES_DMA_BUS_ERROR); - } - - // Operation successful - disable interrupt and return success. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - return (AES_SUCCESS); -} - -//***************************************************************************** -// -// Get the result of an AES-CCM operation -// -//***************************************************************************** -uint32_t -CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, uint32_t *pui32CcmTag) -{ - uint32_t volatile ui32Tag[4]; - uint32_t ui32Idx; - - // Result has already been copied to the output buffer by DMA - // Disable master control. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; - - // Read tag - wait for the context ready bit. - do - { - CPUdelay(1); - } - while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & - CRYPTO_AESCTL_SAVED_CONTEXT_RDY)); - - // Read the Tag registers. - ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); - ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); - ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); - ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); - - for(ui32Idx = 0; ui32Idx < ui32TagLength ; ui32Idx++) - { - *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx); - } - - // Operation successful - clear interrupt status. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - return AES_SUCCESS; -} - -//***************************************************************************** -// -// Start a CCM Decryption and Inverse Authentication operation. -// -//***************************************************************************** -uint32_t -CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength, - uint32_t *pui32Nonce, uint32_t *pui32CipherText, - uint32_t ui32CipherTextLength, - uint32_t *pui32Header, uint32_t ui32HeaderLength, - uint32_t ui32KeyLocation, - uint32_t ui32FieldLength, bool bIntEnable) -{ - uint32_t ui32CtrlVal; - uint32_t i; - uint32_t *pui32PlainText; - uint32_t ui32CryptoBlockLength; - union { - uint32_t w[4]; - uint8_t b[16]; - } ui8InitVec; - - // Input address for the encryption engine is the same as the output. - pui32PlainText = pui32CipherText; - - // Disable global interrupt, enable local interrupt and clear any pending. - // interrupts. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_DMA_IN_DONE | - CRYPTO_IRQEN_RESULT_AVAIL; - - // Configure master control module for AES operation. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = CRYPTO_ALGSEL_AES; - - // Enable keys to read (e.g. Key 0). - HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) = ui32KeyLocation; - - // Wait until key is loaded to the AES module. - do - { - CPUdelay(1); - } - while((HWREG(CRYPTO_BASE + CRYPTO_O_KEYREADAREA) & CRYPTO_KEYREADAREA_BUSY)); - - // Check for Key store Read error. - if((HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)& CRYPTO_KEY_ST_RD_ERR)) - { - return (AES_KEYSTORE_READ_ERROR); - } - - // Prepare the initialization vector (IV), - // Length of Nonce l(n) = 15 - ui32FieldLength. - ui8InitVec.b[0] = ui32FieldLength - 1; - for(i = 0; i < 12; i++) - { - ui8InitVec.b[i + 1] = ((uint8_t*)pui32Nonce)[i]; - } - if(ui32FieldLength == 2) - { - ui8InitVec.b[13] = ((uint8_t*)pui32Nonce)[12]; - } - else - { - ui8InitVec.b[13] = 0; - } - ui8InitVec.b[14] = 0; - ui8InitVec.b[15] = 0; - - // Write initialization vector. - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV0) = ui8InitVec.w[0]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV1) = ui8InitVec.w[1]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV2) = ui8InitVec.w[2]; - HWREG(CRYPTO_BASE + CRYPTO_O_AESIV3) = ui8InitVec.w[3]; - - // Configure AES engine - ui32CryptoBlockLength = ui32CipherTextLength - ui32AuthLength; - ui32CtrlVal = ((ui32FieldLength - 1) << CRYPTO_AESCTL_CCM_L_S); - if ( ui32AuthLength >= 2 ) { - ui32CtrlVal |= ((( ui32AuthLength - 2 ) >> 1 ) << CRYPTO_AESCTL_CCM_M_S ); - } - ui32CtrlVal |= CRYPTO_AESCTL_CCM; - ui32CtrlVal |= CRYPTO_AESCTL_CTR; - ui32CtrlVal |= CRYPTO_AESCTL_SAVE_CONTEXT; - ui32CtrlVal |= (KEY_STORE_SIZE_128 << CRYPTO_AESCTL_KEY_SIZE_S); - ui32CtrlVal |= (0 << CRYPTO_AESCTL_DIR_S); - ui32CtrlVal |= (CRYPTO_AES_CTR_128 << CRYPTO_AESCTL_CTR_WIDTH_S); - - // Write the configuration for 128 bit AES-CCM. - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = ui32CtrlVal; - - // Write the length of the crypto block (plain text). - // Low and high part (high part is assumed to be always 0). - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN0) = ui32CryptoBlockLength; - HWREG(CRYPTO_BASE + CRYPTO_O_AESDATALEN1) = 0; - - // Write the length of the header field. - // Also called AAD - Additional Authentication Data. - HWREG(CRYPTO_BASE + CRYPTO_O_AESAUTHLEN) = ui32HeaderLength; - - // Check if any header information (AAD). - // If so configure the DMA controller to fetch the header. - if(ui32HeaderLength != 0) - { - // Enable DMA channel 0. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Register the base address of the header (AAD). - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)pui32Header; - - // Header length in bytes (may be non-block size aligned). - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32HeaderLength; - - // Wait for completion of the header data transfer, DMA_IN_DONE. - do - { - CPUdelay(1); - } - while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_IRQSTAT_DMA_IN_DONE)); - - // Check for DMA errors. - if(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & CRYPTO_DMA_BUS_ERR) - { - return AES_DMA_BUS_ERROR; - } - } - - // Clear interrupt status. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Wait for interrupt lines from module to be cleared - while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE | CRYPTO_IRQSTAT_RESULT_AVAIL)); - - // Disable CRYPTO_IRQEN_DMA_IN_DONE interrupt as we only - // want interrupt to trigger once RESULT_AVAIL occurs. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~CRYPTO_IRQEN_DMA_IN_DONE; - - // Is using interrupts - clear and enable globally. - if(bIntEnable) - { - IntPendClear(INT_CRYPTO_RESULT_AVAIL_IRQ); - IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); - } - - // Enable internal interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) = CRYPTO_IRQEN_RESULT_AVAIL; - - // Perform decryption if requested. - if(bDecrypt) - { - // Configure the DMA controller - enable both DMA channels. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Base address of the payload data in ext. memory. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = - (uint32_t)pui32CipherText; - - // Payload data length in bytes, equal to the cipher text length. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = ui32CryptoBlockLength; - - // Enable DMA channel 1. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; - - // Base address of the output data buffer. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = - (uint32_t)pui32PlainText; - - // Output data length in bytes, equal to the cipher text length. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = ui32CryptoBlockLength; - } - - return AES_SUCCESS; -} - -//***************************************************************************** -// -// Checks CCM decrypt and Inverse Authentication result. -// -//***************************************************************************** -uint32_t -CRYPTOCcmInvAuthDecryptStatus(void) -{ - uint32_t ui32Status; - - // Get the current DMA status. - ui32Status = HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT); - - // Check if DMA is still busy. - if(ui32Status & CRYPTO_DMA_BSY) - { - return (AES_DMA_BSY); - } - - // Check the status of the DMA operation - return error if not success. - if(ui32Status & CRYPTO_DMA_BUS_ERROR) - { - return (AES_DMA_BUS_ERROR); - } - - // Operation successful - disable interrupt and return success - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - return (AES_SUCCESS); -} - -//***************************************************************************** -// -// Get the result of the CCM operation. -// -//***************************************************************************** -uint32_t -CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength, - uint32_t *pui32CipherText, - uint32_t ui32CipherTextLength, - uint32_t *pui32CcmTag) -{ - uint32_t volatile ui32Tag[4]; - uint32_t ui32TagIndex; - uint32_t i; - uint32_t ui32Idx; - - ui32TagIndex = ui32CipherTextLength - ui32AuthLength; - - // Result has already been copied to the output buffer by DMA - // Disable master control. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; - - // Read tag - wait for the context ready bit. - do - { - CPUdelay(1); - } - while(!(HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) & - CRYPTO_AESCTL_SAVED_CONTEXT_RDY)); - - // Read the Tag registers. - ui32Tag[0] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT0); - ui32Tag[1] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT1); - ui32Tag[2] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT2); - ui32Tag[3] = HWREG(CRYPTO_BASE + CRYPTO_O_AESTAGOUT3); - - for(ui32Idx = 0; ui32Idx < ui32AuthLength ; ui32Idx++) - { - *((uint8_t*)pui32CcmTag + ui32Idx) = *((uint8_t*)ui32Tag + ui32Idx); - } - - // Operation successful - clear interrupt status. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = (CRYPTO_IRQCLR_DMA_IN_DONE | - CRYPTO_IRQCLR_RESULT_AVAIL); - - // Verify the Tag. - for(i = 0; i < ui32AuthLength; i++) - { - if(*((uint8_t *)pui32CcmTag + i) != - (*((uint8_t *)pui32CipherText + ui32TagIndex + i))) - { - return CCM_AUTHENTICATION_FAILED; - } - } - - return AES_SUCCESS; -} - -//***************************************************************************** -// -// Enable Crypto DMA operation -// -//***************************************************************************** -void -CRYPTODmaEnable(uint32_t ui32Channels) -{ - // Check the arguments. - ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) | - (ui32Channels & CRYPTO_DMA_CHAN1)); - - // Enable the selected channels, - if(ui32Channels & CRYPTO_DMA_CHAN0) - { - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - } - if(ui32Channels & CRYPTO_DMA_CHAN1) - { - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; - } -} - -//***************************************************************************** -// -// Disable Crypto DMA operation -// -//***************************************************************************** -void -CRYPTODmaDisable(uint32_t ui32Channels) -{ - // Check the arguments. - ASSERT((ui32Channels & CRYPTO_DMA_CHAN0) | - (ui32Channels & CRYPTO_DMA_CHAN1)); - - // Enable the selected channels. - if(ui32Channels & CRYPTO_DMA_CHAN0) - { - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 0; - } - if(ui32Channels & CRYPTO_DMA_CHAN1) - { - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 0; - } -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h deleted file mode 100644 index e9e449625a1..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/crypto.h +++ /dev/null @@ -1,856 +0,0 @@ -/****************************************************************************** -* Filename: crypto.h -* Revised: 2018-01-12 18:46:31 +0100 (Fri, 12 Jan 2018) -* Revision: 51161 -* -* Description: AES header file. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup crypto_api -//! @{ -// -//***************************************************************************** - -#ifndef __CRYPTO_H__ -#define __CRYPTO_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_crypto.h" -#include "debug.h" -#include "interrupt.h" -#include "cpu.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define CRYPTOAesLoadKey NOROM_CRYPTOAesLoadKey - #define CRYPTOAesCbc NOROM_CRYPTOAesCbc - #define CRYPTOAesCbcStatus NOROM_CRYPTOAesCbcStatus - #define CRYPTOAesEcb NOROM_CRYPTOAesEcb - #define CRYPTOAesEcbStatus NOROM_CRYPTOAesEcbStatus - #define CRYPTOCcmAuthEncrypt NOROM_CRYPTOCcmAuthEncrypt - #define CRYPTOCcmAuthEncryptStatus NOROM_CRYPTOCcmAuthEncryptStatus - #define CRYPTOCcmAuthEncryptResultGet NOROM_CRYPTOCcmAuthEncryptResultGet - #define CRYPTOCcmInvAuthDecrypt NOROM_CRYPTOCcmInvAuthDecrypt - #define CRYPTOCcmInvAuthDecryptStatus NOROM_CRYPTOCcmInvAuthDecryptStatus - #define CRYPTOCcmInvAuthDecryptResultGet NOROM_CRYPTOCcmInvAuthDecryptResultGet - #define CRYPTODmaEnable NOROM_CRYPTODmaEnable - #define CRYPTODmaDisable NOROM_CRYPTODmaDisable -#endif - -//***************************************************************************** -// -// Length of AES Electronic Code Book (ECB) block in bytes -// -//***************************************************************************** -#define AES_ECB_LENGTH 16 - -//***************************************************************************** -// -// Values that can be passed to CryptoIntEnable, CryptoIntDisable, and CryptoIntClear -// as the ui32IntFlags parameter, and returned from CryptoIntStatus. -// -//***************************************************************************** -#define CRYPTO_DMA_IN_DONE 0x00000002 // DMA done interrupt mask -#define CRYPTO_RESULT_RDY 0x00000001 // Result ready interrupt mask -#define CRYPTO_DMA_BUS_ERR 0x80000000 // DMA Bus error -#define CRYPTO_KEY_ST_WR_ERR 0x40000000 // Key Store Write failed -#define CRYPTO_KEY_ST_RD_ERR 0x20000000 // Key Store Read failed - -#define CRYPTO_IRQTYPE_LEVEL 0x00000001 // Crypto Level interrupt enabled -#define CRYPTO_IRQTYPE_PULSE 0x00000000 // Crypto pulse interrupt enabled - -#define CRYPTO_DMA_CHAN0 0x00000001 // Crypto DMA Channel 0 -#define CRYPTO_DMA_CHAN1 0x00000002 // Crypto DMA Channel 1 - -#define CRYPTO_AES128_ENCRYPT 0x0000000C // -#define CRYPTO_AES128_DECRYPT 0x00000008 // - -#define CRYPTO_DMA_READY 0x00000000 // DMA ready -#define CRYPTO_DMA_BSY 0x00000003 // DMA busy -#define CRYPTO_DMA_BUS_ERROR 0x00020000 // DMA encountered bus error - -//***************************************************************************** -// -// General constants -// -//***************************************************************************** - -// AES module return codes -#define AES_SUCCESS 0 -#define AES_KEYSTORE_READ_ERROR 1 -#define AES_KEYSTORE_WRITE_ERROR 2 -#define AES_DMA_BUS_ERROR 3 -#define CCM_AUTHENTICATION_FAILED 4 -#define AES_ECB_TEST_ERROR 8 -#define AES_NULL_ERROR 9 -#define AES_CCM_TEST_ERROR 10 -#define AES_DMA_BSY 11 - -// Key store module defines -#define STATE_BLENGTH 16 // Number of bytes in State -#define KEY_BLENGTH 16 // Number of bytes in Key -#define KEY_EXP_LENGTH 176 // Nb * (Nr+1) * 4 - -#define KEY_STORE_SIZE_128 0x00000001 -#define KEY_STORE_SIZE_192 0x00000002 -#define KEY_STORE_SIZE_256 0x00000003 -#define KEY_STORE_SIZE_BITS 0x00000003 - -//***************************************************************************** -// -// For 128 bit key all 8 Key Area locations from 0 to 8 are valid -// However for 192 bit and 256 bit keys, only even Key Areas 0, 2, 4, 6 -// are valid. -// -//***************************************************************************** -#define CRYPTO_KEY_AREA_0 0 -#define CRYPTO_KEY_AREA_1 1 -#define CRYPTO_KEY_AREA_2 2 -#define CRYPTO_KEY_AREA_3 3 -#define CRYPTO_KEY_AREA_4 4 -#define CRYPTO_KEY_AREA_5 5 -#define CRYPTO_KEY_AREA_6 6 -#define CRYPTO_KEY_AREA_7 7 - -//***************************************************************************** -// -// Defines for the current AES operation -// -//***************************************************************************** -#define CRYPTO_AES_NONE 0 -#define CRYPTO_AES_KEYL0AD 1 -#define CRYPTO_AES_ECB 2 -#define CRYPTO_AES_CCM 3 -#define CRYPTO_AES_RNG 4 -#define CRYPTO_AES_CBC 5 - -//***************************************************************************** -// -// Defines for the AES-CTR mode counter width -// -//***************************************************************************** -#define CRYPTO_AES_CTR_32 0x0 -#define CRYPTO_AES_CTR_64 0x1 -#define CRYPTO_AES_CTR_96 0x2 -#define CRYPTO_AES_CTR_128 0x3 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Write the key into the Key Ram. -//! -//! The \c ui32KeyLocation parameter is an enumerated type which specifies -//! the Key Ram location in which the key is stored. -//! -//! The pointer \c pui8AesKey has the address where the Key is stored. -//! -//! \param pui32AesKey is a pointer to an AES Key. -//! \param ui32KeyLocation is the location of the key in Key RAM. -//! This parameter can have any of the following values: -//! - \ref CRYPTO_KEY_AREA_0 -//! - \ref CRYPTO_KEY_AREA_1 -//! - \ref CRYPTO_KEY_AREA_2 -//! - \ref CRYPTO_KEY_AREA_3 -//! - \ref CRYPTO_KEY_AREA_4 -//! - \ref CRYPTO_KEY_AREA_5 -//! - \ref CRYPTO_KEY_AREA_6 -//! - \ref CRYPTO_KEY_AREA_7 -//! -//! \return Returns status of the function: -//! - \ref AES_SUCCESS -//! - \ref AES_KEYSTORE_READ_ERROR -// -//***************************************************************************** -extern uint32_t CRYPTOAesLoadKey(uint32_t *pui32AesKey, - uint32_t ui32KeyLocation); - -//***************************************************************************** -// -//! \brief Start an AES-CBC operation (encryption or decryption). -//! -//! The function starts an AES CBC mode encrypt or decrypt operation. -//! End operation can be detected by enabling interrupt or by polling -//! CRYPTOAesCbcStatus(). Result of operation is returned by CRYPTOAesCbcStatus(). -//! -//! \param pui32MsgIn is a pointer to the input data. -//! \param pui32MsgOut is a pointer to the output data. -//! \param ui32MsgLength is the length in bytes of the input data. -//! \param pui32Nonce is a pointer to 16-byte Nonce. -//! \param ui32KeyLocation is the location of the key in Key RAM. -//! This parameter can have any of the following values: -//! - \ref CRYPTO_KEY_AREA_0 -//! - \ref CRYPTO_KEY_AREA_1 -//! - \ref CRYPTO_KEY_AREA_2 -//! - \ref CRYPTO_KEY_AREA_3 -//! - \ref CRYPTO_KEY_AREA_4 -//! - \ref CRYPTO_KEY_AREA_5 -//! - \ref CRYPTO_KEY_AREA_6 -//! - \ref CRYPTO_KEY_AREA_7 -//! \param bEncrypt is set \c true to encrypt or set \c false to decrypt. -//! \param bIntEnable is set \c true to enable Crypto interrupts or \c false to -//! disable Crypto interrupt. -//! -//! \return Returns status of the AES-CBC operation: -//! - \ref AES_SUCCESS -//! - \ref AES_KEYSTORE_READ_ERROR -//! -//! \sa \ref CRYPTOAesCbcStatus() -// -//***************************************************************************** -extern uint32_t CRYPTOAesCbc(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, - uint32_t ui32MsgLength, uint32_t *pui32Nonce, - uint32_t ui32KeyLocation, bool bEncrypt, - bool bIntEnable); - -//***************************************************************************** -// -//! \brief Check the result of an AES CBC operation. -//! -//! This function should be called after \ref CRYPTOAesCbc() function to -//! check if the AES CBC operation was successful. -//! -//! \return Returns the status of the AES CBC operation: -//! - \ref AES_SUCCESS : Successful. -//! - \ref AES_DMA_BUS_ERROR : Failed. -//! - \ref AES_DMA_BSY : Operation is ongoing. -//! -//! \sa \ref CRYPTOAesCbc() -// -//***************************************************************************** -extern uint32_t CRYPTOAesCbcStatus(void); - -//***************************************************************************** -// -//! \brief Start an AES-ECB operation (encryption or decryption). -//! -//! The \c ui32KeyLocation parameter is an enumerated type which specifies -//! the Key Ram location in which the key is stored. -//! -//! \param pui32MsgIn is a pointer to the input data. -//! \param pui32MsgOut is a pointer to the output data. -//! \param ui32KeyLocation is the location of the key in Key RAM. -//! This parameter can have any of the following values: -//! - \ref CRYPTO_KEY_AREA_0 -//! - \ref CRYPTO_KEY_AREA_1 -//! - \ref CRYPTO_KEY_AREA_2 -//! - \ref CRYPTO_KEY_AREA_3 -//! - \ref CRYPTO_KEY_AREA_4 -//! - \ref CRYPTO_KEY_AREA_5 -//! - \ref CRYPTO_KEY_AREA_6 -//! - \ref CRYPTO_KEY_AREA_7 -//! \param bEncrypt is set \c true to encrypt or set \c false to decrypt. -//! \param bIntEnable is set \c true to enable Crypto interrupts or \c false to -//! disable Crypto interrupt. -//! -//! \return Returns status of the AES-ECB operation: -//! - \ref AES_SUCCESS -//! - \ref AES_KEYSTORE_READ_ERROR -//! -//! \sa \ref CRYPTOAesEcbStatus() -// -//***************************************************************************** -extern uint32_t CRYPTOAesEcb(uint32_t *pui32MsgIn, uint32_t *pui32MsgOut, - uint32_t ui32KeyLocation, bool bEncrypt, - bool bIntEnable); - -//***************************************************************************** -// -//! \brief Check the result of an AES ECB operation. -//! -//! This function should be called after \ref CRYPTOAesEcb() function to -//! check if the AES ECB operation was successful. -//! -//! \return Returns the status of the AES ECB operation: -//! - \ref AES_SUCCESS : Successful. -//! - \ref AES_DMA_BUS_ERROR : Failed. -//! - \ref AES_DMA_BSY : Operation is ongoing. -//! -//! \sa \ref CRYPTOAesEcb() -// -//***************************************************************************** -extern uint32_t CRYPTOAesEcbStatus(void); - -//***************************************************************************** -// -//! \brief Finish the encryption operation by resetting the operation mode. -//! -//! This function should be called after \ref CRYPTOAesEcbStatus() has reported -//! that the operation is finished successfully. -//! -//! \return None -//! -//! \sa \ref CRYPTOAesEcbStatus() -// -//***************************************************************************** -__STATIC_INLINE void -CRYPTOAesEcbFinish(void) -{ - // Result has already been copied to the output buffer by DMA. - // Disable master control/DMA clock and clear the operating mode. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000; -} - -//***************************************************************************** -// -//! \brief Finish the encryption operation by resetting the operation mode. -//! -//! This function should be called after \ref CRYPTOAesCbcStatus() has reported -//! that the operation is finished successfully. -//! -//! \return None -//! -//! \sa \ref CRYPTOAesCbcStatus() -// -//***************************************************************************** -__STATIC_INLINE void -CRYPTOAesCbcFinish(void) -{ - // Result has already been copied to the output buffer by DMA. - // Disable master control/DMA clock and clear the operating mode. - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = 0x00000000; - HWREG(CRYPTO_BASE + CRYPTO_O_AESCTL) = 0x00000000; -} - -//***************************************************************************** -// -//! \brief Start CCM operation. -//! -//! The \c ui32KeyLocation is an enumerated type which specifies the Key Ram -//! location in which the key is stored. -//! -//! \param bEncrypt determines whether to run encryption or not. -//! \param ui32AuthLength is the length of the authentication field - -//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. -//! \param pui32Nonce is a pointer to 13-byte or 12-byte Nonce (Number used once). -//! \param pui32PlainText is a pointer to the octet string input message. -//! \param ui32PlainTextLength is the length of the message. -//! \param pui32Header is the length of the header (Additional Authentication -//! Data or AAD). -//! \param ui32HeaderLength is the length of the header in octets. -//! \param ui32KeyLocation is the location in Key RAM where the key is stored. -//! This parameter can have any of the following values: -//! - \ref CRYPTO_KEY_AREA_0 -//! - \ref CRYPTO_KEY_AREA_1 -//! - \ref CRYPTO_KEY_AREA_2 -//! - \ref CRYPTO_KEY_AREA_3 -//! - \ref CRYPTO_KEY_AREA_4 -//! - \ref CRYPTO_KEY_AREA_5 -//! - \ref CRYPTO_KEY_AREA_6 -//! - \ref CRYPTO_KEY_AREA_7 -//! \param ui32FieldLength is the size of the length field (2 or 3). -//! \param bIntEnable enables interrupts. -//! -//! \return Returns the status of the CCM operation -//! - \ref AES_SUCCESS -//! - \ref AES_KEYSTORE_READ_ERROR -//! - \ref AES_DMA_BUS_ERROR -//! -//! \sa \ref CRYPTOCcmAuthEncryptStatus() -// -//***************************************************************************** -extern uint32_t CRYPTOCcmAuthEncrypt(bool bEncrypt, uint32_t ui32AuthLength, - uint32_t *pui32Nonce, - uint32_t *pui32PlainText, - uint32_t ui32PlainTextLength, - uint32_t *pui32Header, - uint32_t ui32HeaderLength, - uint32_t ui32KeyLocation, - uint32_t ui32FieldLength, - bool bIntEnable); - -//***************************************************************************** -// -//! \brief Check the result of an AES CCM operation. -//! -//! This function should be called after \ref CRYPTOCcmAuthEncrypt() function to check -//! if the AES CCM operation was successful. -//! -//! \return Returns the status of the AES CCM operation: -//! - \ref AES_SUCCESS : Successful. -//! - \ref AES_DMA_BUS_ERROR : Failed. -//! - \ref AES_DMA_BSY : Operation is ongoing. -//! -//! \sa \ref CRYPTOCcmAuthEncrypt() -// -//***************************************************************************** -extern uint32_t CRYPTOCcmAuthEncryptStatus(void); - -//***************************************************************************** -// -//! \brief Get the result of an AES CCM operation. -//! -//! This function should be called after \ref CRYPTOCcmAuthEncryptStatus(). -//! -//! \param ui32TagLength is length of the Tag. -//! \param pui32CcmTag is the location of the authentication Tag. -//! -//! \return Returns \ref AES_SUCCESS if successful. -//! -//! \sa \ref CRYPTOCcmAuthEncryptStatus() -// -//***************************************************************************** -extern uint32_t CRYPTOCcmAuthEncryptResultGet(uint32_t ui32TagLength, - uint32_t *pui32CcmTag); - -//***************************************************************************** -// -//! \brief Start a CCM Decryption and Inverse Authentication operation. -//! -//! The \c ui32KeyLocation is an enumerated type which specifies the Key Ram -//! location in which the key is stored. -//! -//! \param bDecrypt determines whether to run decryption or not. -//! \param ui32AuthLength is the length of the authentication field - -//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. -//! \param pui32Nonce is a pointer to 13-byte or 12-byte Nonce (Number used once). -//! \param pui32CipherText is a pointer to the octet string encrypted message. -//! \param ui32CipherTextLength is the length of the encrypted message. -//! \param pui32Header is the length of the header (Additional Authentication -//! Data or AAD). -//! \param ui32HeaderLength is the length of the header in octets. -//! \param ui32KeyLocation is the location in Key RAM where the key is stored. -//! This parameter can have any of the following values: -//! - \ref CRYPTO_KEY_AREA_0 -//! - \ref CRYPTO_KEY_AREA_1 -//! - \ref CRYPTO_KEY_AREA_2 -//! - \ref CRYPTO_KEY_AREA_3 -//! - \ref CRYPTO_KEY_AREA_4 -//! - \ref CRYPTO_KEY_AREA_5 -//! - \ref CRYPTO_KEY_AREA_6 -//! - \ref CRYPTO_KEY_AREA_7 -//! \param ui32FieldLength is the size of the length field (2 or 3). -//! \param bIntEnable enables interrupts. -//! -//! \return Returns the status of the operation: -//! - \ref AES_SUCCESS -//! - \ref AES_KEYSTORE_READ_ERROR -//! - \ref AES_DMA_BUS_ERROR -// -//***************************************************************************** -extern uint32_t CRYPTOCcmInvAuthDecrypt(bool bDecrypt, uint32_t ui32AuthLength, - uint32_t *pui32Nonce, - uint32_t *pui32CipherText, - uint32_t ui32CipherTextLength, - uint32_t *pui32Header, - uint32_t ui32HeaderLength, - uint32_t ui32KeyLocation, - uint32_t ui32FieldLength, - bool bIntEnable); - -//***************************************************************************** -// -//! \brief Checks CCM decrypt and Inverse Authentication result. -//! -//! \return Returns status of operation: -//! - \ref AES_SUCCESS : Operation was successful. -//! - \ref AES_DMA_BSY : Operation is busy. -//! - \ref AES_DMA_BUS_ERROR : An error is encountered. -// -//***************************************************************************** -extern uint32_t CRYPTOCcmInvAuthDecryptStatus(void); - -//***************************************************************************** -// -//! \brief Get the result of the CCM operation. -//! -//! \param ui32AuthLength is the length of the authentication field - -//! 0, 2, 4, 6, 8, 10, 12, 14 or 16 octets. -//! \param pui32CipherText is a pointer to the octet string encrypted message. -//! \param ui32CipherTextLength is the length of the encrypted message. -//! \param pui32CcmTag is the location of the authentication Tag. -//! -//! \return Returns AES_SUCCESS if successful. -// -//***************************************************************************** -extern uint32_t CRYPTOCcmInvAuthDecryptResultGet(uint32_t ui32AuthLength, - uint32_t *pui32CipherText, - uint32_t ui32CipherTextLength, - uint32_t *pui32CcmTag); - -//***************************************************************************** -// -//! \brief Get the current status of the Crypto DMA controller. -//! -//! This function is used to poll the Crypto DMA controller to check if it is -//! ready for a new operation or if an error has occurred. -//! -//! The \ref CRYPTO_DMA_BUS_ERROR can also be caught using the crypto event -//! handler. -//! -//! \return Returns the current status of the DMA controller: -//! - \ref CRYPTO_DMA_READY : DMA ready for a new operation -//! - \ref CRYPTO_DMA_BSY : DMA is busy -//! - \ref CRYPTO_DMA_BUS_ERROR : DMA Bus error -// -//***************************************************************************** -__STATIC_INLINE uint32_t -CRYPTODmaStatus(void) -{ - // Return the value of the status register. - return (HWREG(CRYPTO_BASE + CRYPTO_O_DMASTAT)); -} - -//***************************************************************************** -// -//! \brief Enable Crypto DMA operation. -//! -//! The specified Crypto DMA channels are enabled. -//! -//! \param ui32Channels is a bitwise OR of the channels to enable. -//! - \ref CRYPTO_DMA_CHAN0 -//! - \ref CRYPTO_DMA_CHAN1 -//! -//! \return None -// -//***************************************************************************** -extern void CRYPTODmaEnable(uint32_t ui32Channels); - -//***************************************************************************** -// -//! \brief Disable Crypto DMA operation. -//! -//! The specified Crypto DMA channels are disabled. -//! -//! \param ui32Channels is a bitwise OR of the channels to disable. -//! - \ref CRYPTO_DMA_CHAN0 -//! - \ref CRYPTO_DMA_CHAN1 -//! -//! \return None -// -//***************************************************************************** -extern void CRYPTODmaDisable(uint32_t ui32Channels); - -//***************************************************************************** -// -//! \brief Enables individual Crypto interrupt sources. -//! -//! This function enables the indicated Crypto interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt. -//! Disabled sources have no effect on the processor. -//! -//! \param ui32IntFlags is the bitwise OR of the interrupt sources to be enabled. -//! - \ref CRYPTO_DMA_IN_DONE -//! - \ref CRYPTO_RESULT_RDY -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -CRYPTOIntEnable(uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) | - (ui32IntFlags & CRYPTO_RESULT_RDY)); - - // Using level interrupt. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL; - - // Enable the specified interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Disables individual CRYPTO interrupt sources. -//! -//! This function disables the indicated Crypto interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt. -//! Disabled sources have no effect on the processor. -//! -//! \param ui32IntFlags is the bitwise OR of the interrupt sources to be enabled. -//! - \ref CRYPTO_DMA_IN_DONE -//! - \ref CRYPTO_RESULT_RDY -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -CRYPTOIntDisable(uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) | - (ui32IntFlags & CRYPTO_RESULT_RDY)); - - // Disable the specified interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Gets the current interrupt status. -//! -//! This function returns the interrupt status for the specified Crypto. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \param bMasked whether to use raw or masked interrupt status: -//! - \c false : Raw interrupt status is required. -//! - \c true : Masked interrupt status is required. -//! -//! \return Returns the current interrupt status: -//! - \ref CRYPTO_DMA_IN_DONE -//! - \ref CRYPTO_RESULT_RDY -// -//***************************************************************************** -__STATIC_INLINE uint32_t -CRYPTOIntStatus(bool bMasked) -{ - uint32_t ui32Mask; - - // Return either the interrupt status or the raw interrupt status as - // requested. - if(bMasked) - { - ui32Mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); - return(ui32Mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); - } - else - { - return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & 0x00000003); - } -} - -//***************************************************************************** -// -//! \brief Clears Crypto interrupt sources. -//! -//! The specified Crypto interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! - \ref CRYPTO_DMA_IN_DONE -//! - \ref CRYPTO_RESULT_RDY -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -CRYPTOIntClear(uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT((ui32IntFlags & CRYPTO_DMA_IN_DONE) | - (ui32IntFlags & CRYPTO_RESULT_RDY)); - - // Clear the requested interrupt sources, - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for a Crypto interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific UART interrupts must be enabled via \ref CRYPTOIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! UART interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -CRYPTOIntRegister(void (*pfnHandler)(void)) -{ - // Register the interrupt handler. - IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, pfnHandler); - - // Enable the UART interrupt. - IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); -} - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for a Crypto interrupt in the dynamic interrupt table. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a Crypto interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -CRYPTOIntUnregister(void) -{ - // Disable the interrupt. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - - // Unregister the interrupt handler. - IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_CRYPTOAesLoadKey - #undef CRYPTOAesLoadKey - #define CRYPTOAesLoadKey ROM_CRYPTOAesLoadKey - #endif - #ifdef ROM_CRYPTOAesCbc - #undef CRYPTOAesCbc - #define CRYPTOAesCbc ROM_CRYPTOAesCbc - #endif - #ifdef ROM_CRYPTOAesCbcStatus - #undef CRYPTOAesCbcStatus - #define CRYPTOAesCbcStatus ROM_CRYPTOAesCbcStatus - #endif - #ifdef ROM_CRYPTOAesEcb - #undef CRYPTOAesEcb - #define CRYPTOAesEcb ROM_CRYPTOAesEcb - #endif - #ifdef ROM_CRYPTOAesEcbStatus - #undef CRYPTOAesEcbStatus - #define CRYPTOAesEcbStatus ROM_CRYPTOAesEcbStatus - #endif - #ifdef ROM_CRYPTOCcmAuthEncrypt - #undef CRYPTOCcmAuthEncrypt - #define CRYPTOCcmAuthEncrypt ROM_CRYPTOCcmAuthEncrypt - #endif - #ifdef ROM_CRYPTOCcmAuthEncryptStatus - #undef CRYPTOCcmAuthEncryptStatus - #define CRYPTOCcmAuthEncryptStatus ROM_CRYPTOCcmAuthEncryptStatus - #endif - #ifdef ROM_CRYPTOCcmAuthEncryptResultGet - #undef CRYPTOCcmAuthEncryptResultGet - #define CRYPTOCcmAuthEncryptResultGet ROM_CRYPTOCcmAuthEncryptResultGet - #endif - #ifdef ROM_CRYPTOCcmInvAuthDecrypt - #undef CRYPTOCcmInvAuthDecrypt - #define CRYPTOCcmInvAuthDecrypt ROM_CRYPTOCcmInvAuthDecrypt - #endif - #ifdef ROM_CRYPTOCcmInvAuthDecryptStatus - #undef CRYPTOCcmInvAuthDecryptStatus - #define CRYPTOCcmInvAuthDecryptStatus ROM_CRYPTOCcmInvAuthDecryptStatus - #endif - #ifdef ROM_CRYPTOCcmInvAuthDecryptResultGet - #undef CRYPTOCcmInvAuthDecryptResultGet - #define CRYPTOCcmInvAuthDecryptResultGet ROM_CRYPTOCcmInvAuthDecryptResultGet - #endif - #ifdef ROM_CRYPTODmaEnable - #undef CRYPTODmaEnable - #define CRYPTODmaEnable ROM_CRYPTODmaEnable - #endif - #ifdef ROM_CRYPTODmaDisable - #undef CRYPTODmaDisable - #define CRYPTODmaDisable ROM_CRYPTODmaDisable - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __CRYPTO_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.c deleted file mode 100644 index 35cf60f8c1b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.c +++ /dev/null @@ -1,214 +0,0 @@ -/****************************************************************************** -* Filename: ddi.c -* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) -* Revision: 52111 -* -* Description: Driver for the DDI master interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "ddi.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef DDI32RegWrite - #define DDI32RegWrite NOROM_DDI32RegWrite - #undef DDI16BitWrite - #define DDI16BitWrite NOROM_DDI16BitWrite - #undef DDI16BitfieldWrite - #define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite - #undef DDI16BitRead - #define DDI16BitRead NOROM_DDI16BitRead - #undef DDI16BitfieldRead - #define DDI16BitfieldRead NOROM_DDI16BitfieldRead -#endif - -//***************************************************************************** -// -// Write a 32 bit value to a register in the DDI slave. -// -//***************************************************************************** -void -DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, - uint32_t ui32Val) -{ - // Check the arguments. - ASSERT(DDIBaseValid(ui32Base)); - ASSERT(ui32Reg < DDI_SLAVE_REGS); - - // Write the value to the register. - HWREG(ui32Base + ui32Reg) = ui32Val; -} - -//***************************************************************************** -// -// Write a single bit using a 16-bit maskable write -// -//***************************************************************************** -void -DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, - uint32_t ui32Mask, uint32_t ui32WrData) -{ - uint32_t ui32RegAddr; - uint32_t ui32Data; - - // Check the arguments. - ASSERT(DDIBaseValid(ui32Base)); - ASSERT(!((ui32Mask & 0xFFFF0000) ^ (ui32Mask & 0x0000FFFF))); - ASSERT(!(ui32WrData & 0xFFFF0000)); - - // DDI 16-bit target is on 32-bit boundary so double offset - ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; - - // Adjust for target bit in high half of the word. - if(ui32Mask & 0xFFFF0000) - { - ui32RegAddr += 4; - ui32Mask >>= 16; - } - - // Write mask if data is not zero (to set mask bit), else write '0'. - ui32Data = ui32WrData ? ui32Mask : 0x0; - - // Update the register. - HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32Data; -} - -//***************************************************************************** -// -// Write a bit field via the DDI using 16-bit maskable write -// -//***************************************************************************** -void -DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, - uint32_t ui32Mask, uint32_t ui32Shift, - uint16_t ui32Data) -{ - uint32_t ui32RegAddr; - uint32_t ui32WrData; - - // Check the arguments. - ASSERT(DDIBaseValid(ui32Base)); - - // 16-bit target is on 32-bit boundary so double offset. - ui32RegAddr = ui32Base + (ui32Reg << 1) + DDI_O_MASK16B; - - // Adjust for target bit in high half of the word. - if(ui32Shift >= 16) - { - ui32Shift = ui32Shift - 16; - ui32RegAddr += 4; - ui32Mask = ui32Mask >> 16; - } - - // Shift data in to position. - ui32WrData = ui32Data << ui32Shift; - - // Write data. - HWREG(ui32RegAddr) = (ui32Mask << 16) | ui32WrData; -} - -//***************************************************************************** -// -// Read a bit via the DDI using 16-bit READ. -// -//***************************************************************************** -uint16_t -DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask) -{ - uint32_t ui32RegAddr; - uint16_t ui16Data; - - // Check the arguments. - ASSERT(DDIBaseValid(ui32Base)); - - // Calculate the address of the register. - ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; - - // Adjust for target bit in high half of the word. - if(ui32Mask & 0xFFFF0000) - { - ui32RegAddr += 2; - ui32Mask = ui32Mask >> 16; - } - - // Read a halfword on the DDI interface. - ui16Data = HWREGH(ui32RegAddr); - - // Mask data. - ui16Data = ui16Data & ui32Mask; - - // Return masked data. - return(ui16Data); -} - -//***************************************************************************** -// -// Read a bit field via the DDI using 16-bit read. -// -//***************************************************************************** -uint16_t -DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, - uint32_t ui32Mask, uint32_t ui32Shift) -{ - uint32_t ui32RegAddr; - uint16_t ui16Data; - - // Check the arguments. - ASSERT(DDIBaseValid(ui32Base)); - - // Calculate the register address. - ui32RegAddr = ui32Base + ui32Reg + DDI_O_DIR; - - // Adjust for target bit in high half of the word. - if(ui32Shift >= 16) - { - ui32Shift = ui32Shift - 16; - ui32RegAddr += 2; - ui32Mask = ui32Mask >> 16; - } - - // Read the register. - ui16Data = HWREGH(ui32RegAddr); - - // Mask data and shift into place. - ui16Data &= ui32Mask; - ui16Data >>= ui32Shift; - - // Return data. - return(ui16Data); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h deleted file mode 100644 index c4e83e3fa92..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi.h +++ /dev/null @@ -1,462 +0,0 @@ -/****************************************************************************** -* Filename: ddi.h -* Revised: 2018-06-04 16:10:13 +0200 (Mon, 04 Jun 2018) -* Revision: 52111 -* -* Description: Defines and prototypes for the DDI master interface. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup analog_group -//! @{ -//! \addtogroup ddi_api -//! @{ -// -//***************************************************************************** - -#ifndef __DDI_H__ -#define __DDI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ddi.h" -#include "../inc/hw_aux_smph.h" -#include "debug.h" -#include "cpu.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define DDI32RegWrite NOROM_DDI32RegWrite - #define DDI16BitWrite NOROM_DDI16BitWrite - #define DDI16BitfieldWrite NOROM_DDI16BitfieldWrite - #define DDI16BitRead NOROM_DDI16BitRead - #define DDI16BitfieldRead NOROM_DDI16BitfieldRead -#endif - -//***************************************************************************** -// -// Number of register in the DDI slave -// -//***************************************************************************** -#define DDI_SLAVE_REGS 64 - - -//***************************************************************************** -// -// Defines that is used to control the ADI slave and master -// -//***************************************************************************** -#define DDI_PROTECT 0x00000080 -#define DDI_ACK 0x00000001 -#define DDI_SYNC 0x00000000 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - - -//***************************************************************************** -// -// Helper functions -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! -//! \brief Check a DDI base address. -//! -//! This function determines if a DDI port base address is valid. -//! -//! \param ui32Base is the base address of the DDI port. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -//! -//! \endinternal -// -//***************************************************************************** -static bool -DDIBaseValid(uint32_t ui32Base) -{ - return(ui32Base == AUX_DDI0_OSC_BASE); -} -#endif - - -//***************************************************************************** -// -//! \brief Read the value in a 32 bit register. -//! -//! This function will read a register in the analog domain and return -//! the value as an \c uint32_t. -//! -//! \param ui32Base is DDI base address. -//! \param ui32Reg is the 32 bit register to read. -//! -//! \return Returns the 32 bit value of the analog register. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -DDI32RegRead(uint32_t ui32Base, uint32_t ui32Reg) -{ - // Check the arguments. - ASSERT(DDIBaseValid(ui32Base)); - ASSERT(ui32Reg < DDI_SLAVE_REGS); - - // Read the register and return the value. - return(HWREG(ui32Base + ui32Reg)); -} - -//***************************************************************************** -// -//! \brief Set specific bits in a DDI slave register. -//! -//! This function will set bits in a register in the analog domain. -//! -//! \note This operation is write only for the specified register. -//! This function is used to set bits in specific register in the -//! DDI slave. Only bits in the selected register are affected by the -//! operation. -//! -//! \param ui32Base is DDI base address. -//! \param ui32Reg is the base register to assert the bits in. -//! \param ui32Val is the 32 bit one-hot encoded value specifying which -//! bits to set in the register. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -DDI32BitsSet(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(DDIBaseValid(ui32Base)); - ASSERT(ui32Reg < DDI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the DDI slave. - ui32RegOffset = DDI_O_SET; - - // Set the selected bits. - HWREG(ui32Base + ui32RegOffset + ui32Reg) = ui32Val; -} - -//***************************************************************************** -// -//! \brief Clear specific bits in a 32 bit DDI register. -//! -//! This function will clear bits in a register in the analog domain. -//! -//! \param ui32Base is DDI base address. -//! \param ui32Reg is the base registers to clear the bits in. -//! \param ui32Val is the 32 bit one-hot encoded value specifying which -//! bits to clear in the register. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -DDI32BitsClear(uint32_t ui32Base, uint32_t ui32Reg, - uint32_t ui32Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(DDIBaseValid(ui32Base)); - ASSERT(ui32Reg < DDI_SLAVE_REGS); - - // Get the correct address of the first register used for setting bits - // in the DDI slave. - ui32RegOffset = DDI_O_CLR; - - // Clear the selected bits. - HWREG(ui32Base + ui32RegOffset + ui32Reg) = ui32Val; -} - -//***************************************************************************** -// -//! \brief Set a value on any 8 bits inside a 32 bit register in the DDI slave. -//! -//! This function allows byte (8 bit access) to the DDI slave registers. -//! -//! Use this function to write any value in the range 0-7 bits aligned on a -//! byte boundary. For example, for writing the value 0b101 to bits 1-3 set -//! ui16Val = 0x0A and ui16Mask = 0x0E. Bits 0 and 5-7 will -//! not be affected by the operation, as long as the corresponding bits are -//! not set in the \c ui16Mask. -//! -//! \param ui32Base is the base address of the DDI port. -//! \param ui32Reg is the Least Significant Register in the DDI slave that -//! will be affected by the write operation. -//! \param ui32Byte is the byte number to access within the 32 bit register. -//! \param ui16Mask is the mask defining which of the 8 bits that should be -//! overwritten. The mask must be defined in the lower half of the 16 bits. -//! \param ui16Val is the value to write. The value must be defined in the lower -//! half of the 16 bits. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -DDI8SetValBit(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Byte, - uint16_t ui16Mask, uint16_t ui16Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(DDIBaseValid(ui32Base)); - ASSERT(ui32Reg < DDI_SLAVE_REGS); - ASSERT(!(ui16Val & 0xFF00)); - ASSERT(!(ui16Mask & 0xFF00)); - - // Get the correct address of the first register used for setting bits - // in the DDI slave. - ui32RegOffset = DDI_O_MASK8B + (ui32Reg << 1) + (ui32Byte << 1); - - // Set the selected bits. - HWREGH(ui32Base + ui32RegOffset) = (ui16Mask << 8) | ui16Val; -} - -//***************************************************************************** -// -//! \brief Set a value on any 16 bits inside a 32 bit register aligned on a -//! half-word boundary in the DDI slave. -//! -//! This function allows 16 bit masked access to the DDI slave registers. -//! -//! Use this function to write any value in the range 0-15 bits aligned on a -//! half-word boundary. For example, for writing the value 0b101 to bits 1-3 set -//! ui32Val = 0x000A and ui32Mask = 0x000E. Bits 0 and 5-15 will not be -//! affected by the operation, as long as the corresponding bits are not set -//! in the \c ui32Mask. -//! -//! \param ui32Base is the base address of the DDI port. -//! \param ui32Reg is register to access. -//! \param bWriteHigh defines which part of the register to write in. -//! \param ui32Mask is the mask defining which of the 16 bit that should be -//! overwritten. The mask must be defined in the lower half of the 32 bits. -//! \param ui32Val is the value to write. The value must be defined in the lower -//! half of the 32 bits. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -DDI16SetValBit(uint32_t ui32Base, uint32_t ui32Reg, bool bWriteHigh, - uint32_t ui32Mask, uint32_t ui32Val) -{ - uint32_t ui32RegOffset; - - // Check the arguments. - ASSERT(DDIBaseValid(ui32Base)); - ASSERT(ui32Reg < DDI_SLAVE_REGS); - ASSERT(!(ui32Val & 0xFFFF0000)); - ASSERT(!(ui32Mask & 0xFFFF0000)); - - // Get the correct address of the first register used for setting bits - // in the DDI slave. - ui32RegOffset = DDI_O_MASK16B + (ui32Reg << 1) + (bWriteHigh ? 4 : 0); - - // Set the selected bits. - HWREG(ui32Base + ui32RegOffset) = (ui32Mask << 16) | ui32Val; -} - -//***************************************************************************** -// -//! \brief Write a 32 bit value to a register in the DDI slave. -//! -//! This function will write a value to a register in the analog -//! domain. -//! -//! \note This operation is write only for the specified register. No -//! conservation of the previous value of the register will be kept (i.e. this -//! is NOT read-modify-write on the register). -//! -//! \param ui32Base is DDI base address. -//! \param ui32Reg is the register to write. -//! \param ui32Val is the 32 bit value to write to the register. -//! -//! \return None -// -//***************************************************************************** -extern void DDI32RegWrite(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val); - -//***************************************************************************** -// -//! \brief Write a single bit using a 16-bit maskable write. -//! -//! A '1' is written to the bit if \c ui32WrData is non-zero, else a '0' is written. -//! -//! \param ui32Base is the base address of the DDI port. -//! \param ui32Reg is register to access. -//! \param ui32Mask is the mask defining which of the 16 bit that should be overwritten. -//! \param ui32WrData is the value to write. The value must be defined in the lower half of the 32 bits. -//! -//! \return None -// -//***************************************************************************** -extern void DDI16BitWrite(uint32_t ui32Base, uint32_t ui32Reg, - uint32_t ui32Mask, uint32_t ui32WrData); - - -//***************************************************************************** -// -//! \brief Write a bit field via the DDI using 16-bit maskable write. -//! -//! Requires that entire bit field is within the half word boundary. -//! -//! \param ui32Base is the base address of the DDI port. -//! \param ui32Reg is register to access. -//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten. -//! \param ui32Shift is the shift value for the bit field. -//! \param ui32Data is the data aligned to bit 0. -//! -//! \return None -// -//***************************************************************************** -extern void DDI16BitfieldWrite(uint32_t ui32Base, uint32_t ui32Reg, - uint32_t ui32Mask, uint32_t ui32Shift, - uint16_t ui32Data); - -//***************************************************************************** -// -//! \brief Read a bit via the DDI using 16-bit read. -//! -//! \param ui32Base is the base address of the DDI module. -//! \param ui32Reg is the register to read. -//! \param ui32Mask defines the bit which should be read. -//! -//! \return Returns a zero if bit selected by mask is '0'. Else returns the mask. -// -//***************************************************************************** -extern uint16_t DDI16BitRead(uint32_t ui32Base, uint32_t ui32Reg, - uint32_t ui32Mask); - -//***************************************************************************** -// -//! \brief Read a bit field via the DDI using 16-bit read. -//! -//! Requires that entire bit field is within the half word boundary. -//! -//! \param ui32Base is the base address of the DDI port. -//! \param ui32Reg is register to access. -//! \param ui32Mask is the mask defining which of the 16 bits that should be overwritten. -//! \param ui32Shift defines the required shift of the data to align with bit 0. -//! -//! \return Returns data aligned to bit 0. -// -//***************************************************************************** -extern uint16_t DDI16BitfieldRead(uint32_t ui32Base, uint32_t ui32Reg, - uint32_t ui32Mask, uint32_t ui32Shift); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_DDI32RegWrite - #undef DDI32RegWrite - #define DDI32RegWrite ROM_DDI32RegWrite - #endif - #ifdef ROM_DDI16BitWrite - #undef DDI16BitWrite - #define DDI16BitWrite ROM_DDI16BitWrite - #endif - #ifdef ROM_DDI16BitfieldWrite - #undef DDI16BitfieldWrite - #define DDI16BitfieldWrite ROM_DDI16BitfieldWrite - #endif - #ifdef ROM_DDI16BitRead - #undef DDI16BitRead - #define DDI16BitRead ROM_DDI16BitRead - #endif - #ifdef ROM_DDI16BitfieldRead - #undef DDI16BitfieldRead - #define DDI16BitfieldRead ROM_DDI16BitfieldRead - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DDI_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h deleted file mode 100644 index 063c156962e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ddi_doc.h +++ /dev/null @@ -1,67 +0,0 @@ -/****************************************************************************** -* Filename: ddi_doc.h -* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) -* Revision: 47080 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup ddi_api -//! @{ -//! \section sec_ddi Introduction -//! \n -//! -//! \section sec_ddi_api API -//! -//! The API functions can be grouped like this: -//! -//! Write: -//! - Direct (all bits): -//! - \ref DDI32RegWrite() -//! - Set individual bits: -//! - \ref DDI32BitsSet() -//! - Clear individual bits: -//! - \ref DDI32BitsClear() -//! - Masked: -//! - \ref DDI8SetValBit() -//! - \ref DDI16SetValBit() -//! - Special functions using masked write: -//! - \ref DDI16BitWrite() -//! - \ref DDI16BitfieldWrite() -//! -//! Read: -//! - Direct (all bits): -//! - \ref DDI32RegRead() -//! - Special functions using masked read: -//! - \ref DDI16BitRead() -//! - \ref DDI16BitfieldRead() -//! -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.c deleted file mode 100644 index d27d6234b48..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.c +++ /dev/null @@ -1,57 +0,0 @@ -/****************************************************************************** -* Filename: debug.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for the Debug functionality (NB. This is a stub which -* should never be included in a release). -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include -#include -#include "../inc/hw_types.h" -#include "debug.h" - -//***************************************************************************** -// -// Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted. -// -//***************************************************************************** -void -__error__(char *pcFilename, uint32_t ui32Line) -{ - // Error catching. - // User can implement custom error handling for failing ASSERTs. - // Setting breakpoint here allows tracing of the failing ASSERT. - while( true ); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h deleted file mode 100644 index 0cd8a6a2912..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/debug.h +++ /dev/null @@ -1,84 +0,0 @@ -/****************************************************************************** -* Filename: debug.h -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Macros for assisting debug of the driver library. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup debug_api -//! @{ -// -//***************************************************************************** - -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -//! Function stub for allowing compile with DRIVERLIB_DEBUG flag asserted. -// -//***************************************************************************** -extern void __error__(char *pcFilename, uint32_t ui32Line); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DRIVERLIB_DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } - -#else -#define ASSERT(expr) -#endif - -#endif // __DEBUG_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c deleted file mode 100644 index cdb08e35d02..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.c +++ /dev/null @@ -1,45 +0,0 @@ -/****************************************************************************** -* Filename: driverlib_release.c -* Revised: $Date: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) $ -* Revision: $Revision: 47152 $ -* -* Description: Provides macros for ensuring that a specfic release of -* DriverLib is used. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -#include "../driverlib/driverlib_release.h" - - - - -/// Declare the current DriverLib release -DRIVERLIB_DECLARE_RELEASE(0, 54539); diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h deleted file mode 100644 index 497f8b0f99b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/driverlib_release.h +++ /dev/null @@ -1,156 +0,0 @@ -/****************************************************************************** -* Filename: driverlib_release.h -* Revised: $Date: 2015-07-16 12:12:04 +0200 (Thu, 16 Jul 2015) $ -* Revision: $Revision: 44151 $ -* -* Description: Provides macros for ensuring that a specfic release of -* DriverLib is used. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup driverlib_release_api -//! @{ -// -//***************************************************************************** - -#ifndef __DRIVERLIB_RELEASE_H__ -#define __DRIVERLIB_RELEASE_H__ - - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include - - - - -/// DriverLib release group number -#define DRIVERLIB_RELEASE_GROUP 0 -/// DriverLib release build number -#define DRIVERLIB_RELEASE_BUILD 54539 - - - - -//***************************************************************************** -// -//! This macro is called internally from within DriverLib to declare the -//! DriverLib release locking object: -//! \param group is the DriverLib release group number. -//! \param build is the DriverLib release build number. -//! -//! This macro shall not be called in the application unless the intention is -//! to bypass the release locking (at own risk). -// -//***************************************************************************** -#define DRIVERLIB_DECLARE_RELEASE(group, build) \ - const volatile uint8_t driverlib_release_##group##_##build - -/// External declaration of the DriverLib release locking object -extern DRIVERLIB_DECLARE_RELEASE(0, 54539); - - - - -//***************************************************************************** -// -//! This macro shall be called once from within a function of a precompiled -//! software deliverable to lock the deliverable to a specific DriverLib -//! release. It is essential that the call is made from code that is not -//! optimized away. -//! -//! This macro locks to a specific DriverLib release: -//! \param group is the DriverLib release group number. -//! \param build is the DriverLib release build number. -//! -//! If attempting to use the precompiled deliverable with a different release -//! of DriverLib, a linker error will be produced, stating that -//! "driverlib_release_xx_yyyyy is undefined" or similar. -//! -//! To override the check, for example when upgrading DriverLib but not the -//! precompiled deliverables, or when mixing precompiled deliverables, -//! application developers may (at own risk) declare the missing DriverLib -//! release using the \ref DRIVERLIB_DECLARE_RELEASE() macro. -// -//***************************************************************************** -#define DRIVERLIB_ASSERT_RELEASE(group, build) \ - (driverlib_release_##group##_##build) - - - - -//***************************************************************************** -// -//! This macro shall be called once from within a function of a precompiled -//! software deliverable to lock the deliverable to a specific DriverLib -//! release. It is essential that the call is made from code that is not -//! optimized away. -//! -//! This macro locks to the current DriverLib release used at compile-time. -//! -//! If attempting to use the precompiled deliverable with a different release -//! of DriverLib, a linker error will be produced, stating that -//! "driverlib_release_xx_yyyyy is undefined" or similar. -//! -//! To override the check, for example when upgrading DriverLib but not the -//! precompiled deliverables, or when mixing precompiled deliverables, -//! application developers may (at own risk) declare the missing DriverLib -//! release using the \ref DRIVERLIB_DECLARE_RELEASE() macro. -// -//***************************************************************************** -#define DRIVERLIB_ASSERT_CURR_RELEASE() \ - DRIVERLIB_ASSERT_RELEASE(0, 54539) - - - - -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_RELEASE_H__ - - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.c deleted file mode 100644 index a5cf55f45da..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.c +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: event.c -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Driver for the Event Fabric. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "event.h" - -// See event.h for implementation diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.h deleted file mode 100644 index 2df3e200713..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event.h +++ /dev/null @@ -1,267 +0,0 @@ -/****************************************************************************** -* Filename: event.h -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Defines and prototypes for the Event Handler. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup event_api -//! @{ -// -//***************************************************************************** - -#ifndef __EVENT_H__ -#define __EVENT_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_event.h" -#include "debug.h" - - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Connects an event to an event subscriber via Event Fabric. -//! -//! This function connects event sources to event subscribers. -//! -//! It is not possible to read event status in this module (except software events). -//! Event status must be read in the module that contains the event source. How a -//! specific event subscriber reacts to an event is configured and documented in -//! the respective modules. -//! -//! For a full list of configurable and constant mapped event sources to event -//! subscribers see the register descriptions for -//! Event Fabric. -//! -//! Defines for event subscriber argument (\c ui32EventSubscriber) have the format: -//! - \ti_code{EVENT_O_[subscriber_name]} -//! -//! Defines for event source argument (\c ui32EventSource) must have the -//! following format where valid \c event_enum values are found in the -//! register description : -//! - \ti_code{EVENT_[subscriber_name]_EV_[event_enum]} -//! -//! Examples of valid defines for \c ui32EventSource: -//! - EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE -//! - EVENT_RFCSEL9_EV_AUX_COMPA -//! - EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD -//! -//! \note Each event subscriber can only receive a sub-set of the event sources! -//! -//! \note Switching the event source is not glitch free, so it is imperative -//! that the subscriber is disabled for interrupts when switching the event -//! source. The behavior is undefined if not disabled. -//! -//! \param ui32EventSubscriber is the \b configurable event subscriber to receive the event. -//! Click the event subscriber to see the list of valid event sources in the -//! register description. -//! - EVENT_O_CPUIRQSEL30 : System CPU interrupt 30 -//! - EVENT_O_RFCSEL9 : RF Core event 9 -//! - EVENT_O_GPT0ACAPTSEL : GPT 0A capture event -//! - EVENT_O_GPT0BCAPTSEL : GPT 0B capture event -//! - EVENT_O_GPT1ACAPTSEL : GPT 1A capture event -//! - EVENT_O_GPT1BCAPTSEL : GPT 1B capture event -//! - EVENT_O_GPT2ACAPTSEL : GPT 2A capture event -//! - EVENT_O_GPT2BCAPTSEL : GPT 2B capture event -//! - EVENT_O_GPT3ACAPTSEL : GPT 3A capture event -//! - EVENT_O_GPT3BCAPTSEL : GPT 3B capture event -//! - EVENT_O_UDMACH9SSEL : uDMA channel 9 single request -//! - EVENT_O_UDMACH9BSEL : uDMA channel 9 burst request -//! - EVENT_O_UDMACH10SSEL : uDMA channel 10 single request -//! - EVENT_O_UDMACH10BSEL : uDMA channel 10 burst request -//! - EVENT_O_UDMACH11SSEL : uDMA channel 11 single request -//! - EVENT_O_UDMACH11BSEL : uDMA channel 11 burst request -//! - EVENT_O_UDMACH12SSEL : uDMA channel 12 single request -//! - EVENT_O_UDMACH12BSEL : uDMA channel 12 burst request -//! - EVENT_O_UDMACH14BSEL : uDMA channel 14 single request -//! - EVENT_O_AUXSEL0 : AUX -//! - EVENT_O_I2SSTMPSEL0 : I2S -//! - EVENT_O_FRZSEL0 : Freeze modules (some modules can freeze on CPU Halt) -//! \param ui32EventSource is the specific event that must be acted upon. -//! - Format: \ti_code{EVENT_[subscriber_name]_EV_[event_enum]} (see explanation above) -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -EventRegister(uint32_t ui32EventSubscriber, uint32_t ui32EventSource) -{ - // Check the arguments. - ASSERT(( ui32EventSubscriber == EVENT_O_CPUIRQSEL30 ) || - ( ui32EventSubscriber == EVENT_O_RFCSEL9 ) || - ( ui32EventSubscriber == EVENT_O_GPT0ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT0BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT1ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT1BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT2ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT2BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT3ACAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_GPT3BCAPTSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH9SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH9BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH10SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH10BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH11SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH11BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH12SSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH12BSEL ) || - ( ui32EventSubscriber == EVENT_O_UDMACH14BSEL ) || - ( ui32EventSubscriber == EVENT_O_AUXSEL0 ) || - ( ui32EventSubscriber == EVENT_O_I2SSTMPSEL0 ) || - ( ui32EventSubscriber == EVENT_O_FRZSEL0 ) ); - - // Map the event source to the event subscriber - HWREG(EVENT_BASE + ui32EventSubscriber) = ui32EventSource; -} - -//***************************************************************************** -// -//! \brief Sets software event. -//! -//! Setting a software event triggers the event if the value was 0 before. -//! -//! \note The software event must be cleared manually after the event has -//! triggered the event subscriber. -//! -//! \param ui32SwEvent is the software event number. -//! - 0 : SW Event 0 -//! - 1 : SW Event 1 -//! - 2 : SW Event 2 -//! - 3 : SW Event 3 -//! -//! \return None -//! -//! \sa \ref EventSwEventClear() -// -//***************************************************************************** -__STATIC_INLINE void -EventSwEventSet(uint32_t ui32SwEvent) -{ - // Check the arguments. - ASSERT( ui32SwEvent <= 3 ); - - // Each software event is byte accessible - HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 1; -} - -//***************************************************************************** -// -//! \brief Clears software event. -//! -//! \param ui32SwEvent is the software event number. -//! - 0 : SW Event 0 -//! - 1 : SW Event 1 -//! - 2 : SW Event 2 -//! - 3 : SW Event 3 -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -EventSwEventClear(uint32_t ui32SwEvent) -{ - // Check the arguments. - ASSERT( ui32SwEvent <= 3 ); - - // Each software event is byte accessible - HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent) = 0; -} - -//***************************************************************************** -// -//! \brief Gets software event status. -//! -//! \param ui32SwEvent is the software event number. -//! - 0 : SW Event 0 -//! - 1 : SW Event 1 -//! - 2 : SW Event 2 -//! - 3 : SW Event 3 -//! -//! \return Returns current value of requested software event. -//! - 0 : Software event is de-asserted. -//! - 1 : Software event is asserted. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -EventSwEventGet(uint32_t ui32SwEvent) -{ - // Check the arguments. - ASSERT( ui32SwEvent <= 3 ); - - // Each software event is byte accessible - return( HWREGB(EVENT_BASE + EVENT_O_SWEV + ui32SwEvent)); -} - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __EVENT_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h deleted file mode 100644 index 299305c74a1..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/event_doc.h +++ /dev/null @@ -1,58 +0,0 @@ -/****************************************************************************** -* Filename: event_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup event_api -//! @{ -//! \section sec_event Introduction -//! -//! The event fabric consists of two event modules. One in the MCU power domain (MCU event fabric) and -//! the other in the AON power domain (AON event fabric). The MCU event fabric is one of the subscribers -//! to the AON event fabric. For more information on AON event fabric, see [AON event API](@ref aonevent_api). -//! -//! The MCU event fabric is a combinational router between event sources and event subscribers. Most -//! event subscribers have statically routed event sources but several event subscribers have -//! configurable event sources which is configured in the MCU event fabric through this API. Although -//! configurable only a subset of event sources are available to each of the configurable event subscribers. -//! This is explained in more details in the function @ref EventRegister() which does all the event routing -//! configuration. -//! -//! MCU event fabric also contains four software events which allow software to trigger certain event -//! subscribers. Each of the four software events is an independent event source which must be set and -//! cleared in the MCU event fabric through the functions: -//! - @ref EventSwEventSet() -//! - @ref EventSwEventClear() -//! - @ref EventSwEventGet() -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.c deleted file mode 100644 index f51b30fee50..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.c +++ /dev/null @@ -1,672 +0,0 @@ -/****************************************************************************** -* Filename: flash.c -* Revised: 2017-10-30 13:37:49 +0100 (Mon, 30 Oct 2017) -* Revision: 50105 -* -* Description: Driver for on chip Flash. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "../inc/hw_types.h" -#include "../inc/hw_ccfg.h" -#include "flash.h" -#include "rom.h" -#include "chipinfo.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef FlashPowerModeSet - #define FlashPowerModeSet NOROM_FlashPowerModeSet - #undef FlashPowerModeGet - #define FlashPowerModeGet NOROM_FlashPowerModeGet - #undef FlashProtectionSet - #define FlashProtectionSet NOROM_FlashProtectionSet - #undef FlashProtectionGet - #define FlashProtectionGet NOROM_FlashProtectionGet - #undef FlashProtectionSave - #define FlashProtectionSave NOROM_FlashProtectionSave - #undef FlashSectorErase - #define FlashSectorErase NOROM_FlashSectorErase - #undef FlashProgram - #define FlashProgram NOROM_FlashProgram - #undef FlashEfuseReadRow - #define FlashEfuseReadRow NOROM_FlashEfuseReadRow - #undef FlashDisableSectorsForWrite - #define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite -#endif - - -//***************************************************************************** -// -// Defines for accesses to the security control in the customer configuration -// area in flash top sector. -// -//***************************************************************************** -#define CCFG_OFFSET_SECURITY CCFG_O_BL_CONFIG -#define CCFG_OFFSET_SECT_PROT CCFG_O_CCFG_PROT_31_0 -#define CCFG_SIZE_SECURITY 0x00000014 -#define CCFG_SIZE_SECT_PROT 0x00000004 - -//***************************************************************************** -// -// Default values for security control in customer configuration area in flash -// top sector. -// -//***************************************************************************** -const uint8_t g_pui8CcfgDefaultSec[] = {0xFF, 0xFF, 0xFF, 0xC5, - 0xFF, 0xFF, 0xFF, 0xFF, - 0xC5, 0xFF, 0xFF, 0xFF, - 0xC5, 0xC5, 0xC5, 0xFF, - 0xC5, 0xC5, 0xC5, 0xFF - }; - -typedef uint32_t (* FlashPrgPointer_t) (uint8_t *, uint32_t, uint32_t); - -typedef uint32_t (* FlashSectorErasePointer_t) (uint32_t); - -//***************************************************************************** -// -// Function prototypes for static functions -// -//***************************************************************************** -static void SetReadMode(void); - -//***************************************************************************** -// -// Set power mode -// -//***************************************************************************** -void -FlashPowerModeSet(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, - uint32_t ui32PumpGracePeriod) -{ - // Check the arguments. - ASSERT(ui32PowerMode == FLASH_PWR_ACTIVE_MODE || - ui32PowerMode == FLASH_PWR_OFF_MODE || - ui32PowerMode == FLASH_PWR_DEEP_STDBY_MODE); - ASSERT(ui32BankGracePeriod <= 0xFF); - ASSERT(ui32PumpGracePeriod <= 0xFFFF); - - switch(ui32PowerMode) - { - case FLASH_PWR_ACTIVE_MODE: - // Set bank power mode to ACTIVE. - HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = - (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & - ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_ACTIVE; - - // Set charge pump power mode to ACTIVE mode. - HWREG(FLASH_BASE + FLASH_O_FPAC1) = - (HWREG(FLASH_BASE + FLASH_O_FPAC1) & ~FLASH_FPAC1_PUMPPWR_M) | (1 << FLASH_FPAC1_PUMPPWR_S); - break; - - case FLASH_PWR_OFF_MODE: - // Set bank grace period. - HWREG(FLASH_BASE + FLASH_O_FBAC) = - (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | - ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); - - // Set pump grace period. - HWREG(FLASH_BASE + FLASH_O_FPAC2) = - (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | - ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); - - // Set bank power mode to SLEEP. - HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) &= ~FLASH_FBFALLBACK_BANKPWR0_M; - - // Set charge pump power mode to SLEEP mode. - HWREG(FLASH_BASE + FLASH_O_FPAC1) &= ~FLASH_FPAC1_PUMPPWR_M; - break; - - case FLASH_PWR_DEEP_STDBY_MODE: - // Set bank grace period. - HWREG(FLASH_BASE + FLASH_O_FBAC) = - (HWREG(FLASH_BASE + FLASH_O_FBAC) & (~FLASH_FBAC_BAGP_M)) | - ((ui32BankGracePeriod << FLASH_FBAC_BAGP_S) & FLASH_FBAC_BAGP_M); - - // Set pump grace period. - HWREG(FLASH_BASE + FLASH_O_FPAC2) = - (HWREG(FLASH_BASE + FLASH_O_FPAC2) & (~FLASH_FPAC2_PAGP_M)) | - ((ui32PumpGracePeriod << FLASH_FPAC2_PAGP_S) & FLASH_FPAC2_PAGP_M); - - // Set bank power mode to DEEP STANDBY mode. - HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) = - (HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & - ~FLASH_FBFALLBACK_BANKPWR0_M) | FBFALLBACK_DEEP_STDBY; - - // Set charge pump power mode to STANDBY mode. - HWREG(FLASH_BASE + FLASH_O_FPAC1) |= FLASH_FPAC1_PUMPPWR_M; - break; - } -} - -//***************************************************************************** -// -// Get current configured power mode -// -//***************************************************************************** -uint32_t -FlashPowerModeGet(void) -{ - uint32_t ui32PowerMode; - uint32_t ui32BankPwrMode; - - ui32BankPwrMode = HWREG(FLASH_BASE + FLASH_O_FBFALLBACK) & - FLASH_FBFALLBACK_BANKPWR0_M; - - if(ui32BankPwrMode == FBFALLBACK_SLEEP) - { - ui32PowerMode = FLASH_PWR_OFF_MODE; - } - else if(ui32BankPwrMode == FBFALLBACK_DEEP_STDBY) - { - ui32PowerMode = FLASH_PWR_DEEP_STDBY_MODE; - } - else - { - ui32PowerMode = FLASH_PWR_ACTIVE_MODE; - } - - // Return power mode. - return(ui32PowerMode); -} - -//***************************************************************************** -// -// Set sector protection -// -//***************************************************************************** -void -FlashProtectionSet(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode) -{ - uint32_t ui32SectorNumber; - - // Check the arguments. - ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - - FlashSectorSizeGet())); - ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); - - if(ui32ProtectMode == FLASH_WRITE_PROTECT) - { - ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / - FlashSectorSizeGet(); - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - - if(ui32SectorNumber <= 31) - { - HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) |= (1 << ui32SectorNumber); - HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) |= (1 << ui32SectorNumber); - } - else if(ui32SectorNumber <= 63) - { - HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) |= - (1 << (ui32SectorNumber & 0x1F)); - HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) |= - (1 << (ui32SectorNumber & 0x1F)); - } - - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; - } -} - -//***************************************************************************** -// -// Get sector protection -// -//***************************************************************************** -uint32_t -FlashProtectionGet(uint32_t ui32SectorAddress) -{ - uint32_t ui32SectorProtect; - uint32_t ui32SectorNumber; - - // Check the arguments. - ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - - FlashSectorSizeGet())); - ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); - - ui32SectorProtect = FLASH_NO_PROTECT; - ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); - - if(ui32SectorNumber <= 31) - { - if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE0) & (1 << ui32SectorNumber)) && - (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP0) & (1 << ui32SectorNumber))) - { - ui32SectorProtect = FLASH_WRITE_PROTECT; - } - } - else if(ui32SectorNumber <= 63) - { - if((HWREG(FLASH_BASE + FLASH_O_FSM_BSLE1) & - (1 << (ui32SectorNumber & 0x1F))) && - (HWREG(FLASH_BASE + FLASH_O_FSM_BSLP1) & - (1 << (ui32SectorNumber & 0x1F)))) - { - ui32SectorProtect = FLASH_WRITE_PROTECT; - } - } - - return(ui32SectorProtect); -} - -//***************************************************************************** -// -// Save sector protection to make it permanent -// -//***************************************************************************** -uint32_t -FlashProtectionSave(uint32_t ui32SectorAddress) -{ - uint32_t ui32ErrorReturn; - uint32_t ui32SectorNumber; - uint32_t ui32CcfgSectorAddr; - uint32_t ui32ProgBuf; - - ui32ErrorReturn = FAPI_STATUS_SUCCESS; - - // Check the arguments. - ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - - FlashSectorSizeGet())); - ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); - - if(FlashProtectionGet(ui32SectorAddress) == FLASH_WRITE_PROTECT) - { - // Find sector number for specified sector. - ui32SectorNumber = (ui32SectorAddress - FLASHMEM_BASE) / FlashSectorSizeGet(); - ui32CcfgSectorAddr = FLASHMEM_BASE + FlashSizeGet() - FlashSectorSizeGet(); - - // Adjust CCFG address to the 32-bit CCFG word holding the - // protect-bit for the specified sector. - ui32CcfgSectorAddr += (((ui32SectorNumber >> 5) * 4) + CCFG_OFFSET_SECT_PROT); - - // Find value to program by setting the protect-bit which - // corresponds to specified sector number, to 0. - // Leave other protect-bits unchanged. - ui32ProgBuf = (~(1 << (ui32SectorNumber & 0x1F))) & - *(uint32_t *)ui32CcfgSectorAddr; - - ui32ErrorReturn = FlashProgram((uint8_t*)&ui32ProgBuf, ui32CcfgSectorAddr, - CCFG_SIZE_SECT_PROT); - } - - // Return status. - return(ui32ErrorReturn); -} - -//***************************************************************************** -// -// Erase a flash sector -// -//***************************************************************************** -uint32_t -FlashSectorErase(uint32_t ui32SectorAddress) -{ - uint32_t ui32ErrorReturn; - FlashSectorErasePointer_t FuncPointer; - - // Check the arguments. - ASSERT(ui32SectorAddress <= (FLASHMEM_BASE + FlashSizeGet() - - FlashSectorSizeGet())); - ASSERT((ui32SectorAddress & (FlashSectorSizeGet() - 1)) == 00); - - // Call ROM function that handles the actual erase operation - FuncPointer = (uint32_t (*)(uint32_t)) (ROM_API_FLASH_TABLE[5]); - ui32ErrorReturn = FuncPointer(ui32SectorAddress); - - // Enable standby in flash bank since ROM function might have disabled it - HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; - - // Return status of operation. - return(ui32ErrorReturn); - -} - - -//***************************************************************************** -// -// Programs unprotected main bank flash sectors -// -//***************************************************************************** -uint32_t -FlashProgram(uint8_t *pui8DataBuffer, uint32_t ui32Address, uint32_t ui32Count) -{ - uint32_t ui32ErrorReturn; - FlashPrgPointer_t FuncPointer; - - // Check the arguments. - ASSERT((ui32Address + ui32Count) <= (FLASHMEM_BASE + FlashSizeGet())); - - // Call ROM function that handles the actual program operation - FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ROM_API_FLASH_TABLE[6]); - ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count); - - // Enable standby in flash bank since ROM function might have disabled it - HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; - - // Return status of operation. - return(ui32ErrorReturn); - -} - -//***************************************************************************** -// -// Reads efuse data from specified row -// -//***************************************************************************** -bool -FlashEfuseReadRow(uint32_t *pui32EfuseData, uint32_t ui32RowAddress) -{ - bool bStatus; - - // Make sure the clock for the efuse is enabled - HWREG(FLASH_BASE + FLASH_O_CFG) &= ~FLASH_CFG_DIS_EFUSECLK; - - // Set timing for EFUSE read operations. - HWREG(FLASH_BASE + FLASH_O_EFUSEREAD) |= ((5 << FLASH_EFUSEREAD_READCLOCK_S) & - FLASH_EFUSEREAD_READCLOCK_M); - - // Clear status register. - HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) = 0; - - // Select the FuseROM block 0. - HWREG(FLASH_BASE + FLASH_O_EFUSEADDR) = 0x00000000; - - // Start the read operation. - HWREG(FLASH_BASE + FLASH_O_EFUSE) = - (DUMPWORD_INSTR << FLASH_EFUSE_INSTRUCTION_S) | - (ui32RowAddress & FLASH_EFUSE_DUMPWORD_M); - - // Wait for operation to finish. - while(!(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_DONE)) - { - } - - // Check if error reported. - if(HWREG(FLASH_BASE + FLASH_O_EFUSEERROR) & FLASH_EFUSEERROR_CODE_M) - { - // Set error status. - bStatus = 1; - - // Clear data. - *pui32EfuseData = 0; - } - else - { - // Set ok status. - bStatus = 0; - - // No error. Get data from data register. - *pui32EfuseData = HWREG(FLASH_BASE + FLASH_O_DATALOWER); - } - - // Disable the efuse clock to conserve power - HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_EFUSECLK; - - // Return the data. - return(bStatus); -} - - -//***************************************************************************** -// -// Disables all sectors for erase and programming on the active bank -// -//***************************************************************************** -void -FlashDisableSectorsForWrite(void) -{ - // Configure flash back to read mode - SetReadMode(); - - // Disable Level 1 Protection. - HWREG(FLASH_BASE + FLASH_O_FBPROT) = FLASH_FBPROT_PROTL1DIS; - - // Disable all sectors for erase and programming. - HWREG(FLASH_BASE + FLASH_O_FBSE) = 0x0000; - - // Enable Level 1 Protection. - HWREG(FLASH_BASE + FLASH_O_FBPROT) = 0; - - // Protect sectors from sector erase. - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR1) = 0xFFFFFFFF; - HWREG(FLASH_BASE + FLASH_O_FSM_SECTOR2) = 0xFFFFFFFF; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; -} - -//***************************************************************************** -// -//! \internal -//! Used to set flash in read mode. -//! -//! Flash is configured with values loaded from OTP dependent on the current -//! regulator mode. -//! -//! \return None. -// -//***************************************************************************** -static void -SetReadMode(void) -{ - uint32_t ui32TrimValue; - uint32_t ui32Value; - - // Configure the STANDBY_MODE_SEL, STANDBY_PW_SEL, DIS_STANDBY, DIS_IDLE, - // VIN_AT_X and VIN_BY_PASS for read mode - if(HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & - AON_PMCTL_PWRCTL_EXT_REG_MODE) - { - // Select trim values for external regulator mode: - // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 7) - // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 6:5) - // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 - HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; - - ui32TrimValue = - HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); - - ui32Value = ((ui32TrimValue & - FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M) >> - FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S) << - FLASH_CFG_STANDBY_MODE_SEL_S; - - ui32Value |= ((ui32TrimValue & - FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M) >> - FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S) << - FLASH_CFG_STANDBY_PW_SEL_S; - - // Configure DIS_STANDBY (OTP offset 0x308 bit 4). - // Configure DIS_IDLE (OTP offset 0x308 bit 3). - ui32Value |= ((ui32TrimValue & - (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M | - FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M)) >> - FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S) << - FLASH_CFG_DIS_IDLE_S; - - HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & - ~(FLASH_CFG_STANDBY_MODE_SEL_M | - FLASH_CFG_STANDBY_PW_SEL_M | - FLASH_CFG_DIS_STANDBY_M | - FLASH_CFG_DIS_IDLE_M)) | ui32Value; - - // Check if sample and hold functionality is disabled. - if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) - { - // Wait for disabled sample and hold functionality to be stable. - while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) - { - } - } - - // Configure VIN_AT_X (OTP offset 0x308 bits 2:0) - ui32Value = ((ui32TrimValue & - FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M) >> - FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S) << - FLASH_FSEQPMP_VIN_AT_X_S; - - // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. - // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise - // VIN_BY_PASS should be 1 - if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> - FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) - { - ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; - } - - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; - HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = - (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & - ~(FLASH_FSEQPMP_VIN_BY_PASS_M | - FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; - } - else - { - // Select trim values for internal regulator mode: - // Configure STANDBY_MODE_SEL (OTP offset 0x308 bit 15) - // COnfigure STANDBY_PW_SEL (OTP offset 0x308 bit 14:13) - // Must be done while the register bit field CONFIG.DIS_STANDBY = 1 - HWREG(FLASH_BASE + FLASH_O_CFG) |= FLASH_CFG_DIS_STANDBY; - - ui32TrimValue = - HWREG(FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_FLASH_OTP_DATA4); - - ui32Value = ((ui32TrimValue & - FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M) >> - FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S) << - FLASH_CFG_STANDBY_MODE_SEL_S; - - ui32Value |= ((ui32TrimValue & - FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M) >> - FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S) << - FLASH_CFG_STANDBY_PW_SEL_S; - - // Configure DIS_STANDBY (OTP offset 0x308 bit 12). - // Configure DIS_IDLE (OTP offset 0x308 bit 11). - ui32Value |= ((ui32TrimValue & - (FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M | - FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M)) >> - FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S) << - FLASH_CFG_DIS_IDLE_S; - - HWREG(FLASH_BASE + FLASH_O_CFG) = (HWREG(FLASH_BASE + FLASH_O_CFG) & - ~(FLASH_CFG_STANDBY_MODE_SEL_M | - FLASH_CFG_STANDBY_PW_SEL_M | - FLASH_CFG_DIS_STANDBY_M | - FLASH_CFG_DIS_IDLE_M)) | ui32Value; - - // Check if sample and hold functionality is disabled. - if(HWREG(FLASH_BASE + FLASH_O_CFG) & FLASH_CFG_DIS_IDLE) - { - // Wait for disabled sample and hold functionality to be stable. - while(!(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_SAMHOLD_DIS)) - { - } - } - - // Configure VIN_AT_X (OTP offset 0x308 bits 10:8) - ui32Value = (((ui32TrimValue & - FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M) >> - FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S) << - FLASH_FSEQPMP_VIN_AT_X_S); - - // Configure VIN_BY_PASS which is dependent on the VIN_AT_X value. - // If VIN_AT_X = 7 then VIN_BY_PASS should be 0 otherwise - // VIN_BY_PASS should be 1 - if(((ui32Value & FLASH_FSEQPMP_VIN_AT_X_M) >> - FLASH_FSEQPMP_VIN_AT_X_S) != 0x7) - { - ui32Value |= FLASH_FSEQPMP_VIN_BY_PASS; - } - - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0xAAAA; - HWREG(FLASH_BASE + FLASH_O_FSEQPMP) = - (HWREG(FLASH_BASE + FLASH_O_FSEQPMP) & - ~(FLASH_FSEQPMP_VIN_BY_PASS_M | - FLASH_FSEQPMP_VIN_AT_X_M)) | ui32Value; - HWREG(FLASH_BASE + FLASH_O_FLOCK) = 0x55AA; - } -} - -//***************************************************************************** -// -// HAPI Flash program function -// -//***************************************************************************** -uint32_t -MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, uint32_t ui32Address, - uint32_t ui32Count) -{ - uint32_t ui32ErrorReturn; - FlashPrgPointer_t FuncPointer; - uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (5 * 4)); - - // Call ROM function - FuncPointer = (uint32_t (*)(uint8_t *, uint32_t, uint32_t)) (ui32RomAddr); - ui32ErrorReturn = FuncPointer( pui8DataBuffer, ui32Address, ui32Count); - - // Enable standby in flash bank since ROM function might have disabled it - HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; - - // Return status of operation. - return(ui32ErrorReturn); -} - -//***************************************************************************** -// -// HAPI Flash sector erase function -// -//***************************************************************************** -uint32_t -MemBusWrkAroundHapiEraseSector(uint32_t ui32Address) -{ - uint32_t ui32ErrorReturn; - - FlashSectorErasePointer_t FuncPointer; - uint32_t ui32RomAddr = HWREG(ROM_HAPI_TABLE_ADDR + (3 * 4)); - - // Call ROM function - FuncPointer = (uint32_t (*)(uint32_t)) (ui32RomAddr); - ui32ErrorReturn = FuncPointer(ui32Address); - - // Enable standby in flash bank since ROM function might have disabled it - HWREGBITW(FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; - - // Return status of operation. - return(ui32ErrorReturn); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h deleted file mode 100644 index a44b02dad6f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/flash.h +++ /dev/null @@ -1,817 +0,0 @@ -/****************************************************************************** -* Filename: flash.h -* Revised: 2017-11-02 16:09:32 +0100 (Thu, 02 Nov 2017) -* Revision: 50166 -* -* Description: Defines and prototypes for the Flash driver. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup flash_api -//! @{ -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_flash.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_aon_pmctl.h" -#include "../inc/hw_fcfg1.h" -#include "interrupt.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define FlashPowerModeSet NOROM_FlashPowerModeSet - #define FlashPowerModeGet NOROM_FlashPowerModeGet - #define FlashProtectionSet NOROM_FlashProtectionSet - #define FlashProtectionGet NOROM_FlashProtectionGet - #define FlashProtectionSave NOROM_FlashProtectionSave - #define FlashSectorErase NOROM_FlashSectorErase - #define FlashProgram NOROM_FlashProgram - #define FlashEfuseReadRow NOROM_FlashEfuseReadRow - #define FlashDisableSectorsForWrite NOROM_FlashDisableSectorsForWrite -#endif - -//***************************************************************************** -// -// Values that can be returned from the API functions -// -//***************************************************************************** -#define FAPI_STATUS_SUCCESS 0x00000000 // Function completed successfully -#define FAPI_STATUS_FSM_BUSY 0x00000001 // FSM is Busy -#define FAPI_STATUS_FSM_READY 0x00000002 // FSM is Ready -#define FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH \ - 0x00000003 // Incorrect parameter value -#define FAPI_STATUS_FSM_ERROR 0x00000004 // Operation failed - -//***************************************************************************** -// -// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and -// returned from FlashIntStatus(). -// -//***************************************************************************** -#define FLASH_INT_FSM_DONE 0x00400000 // FSM Done Interrupt Mask -#define FLASH_INT_RV 0x00010000 // Read Verify error Interrupt Mask - -//***************************************************************************** -// -// Values passed to FlashSetPowerMode() and returned from FlashGetPowerMode(). -// -//***************************************************************************** -#define FLASH_PWR_ACTIVE_MODE 0x00000000 -#define FLASH_PWR_OFF_MODE 0x00000001 -#define FLASH_PWR_DEEP_STDBY_MODE \ - 0x00000002 - -//***************************************************************************** -// -// Values passed to FlashSetProtection() and returned from FlashGetProtection(). -// -//***************************************************************************** -#define FLASH_NO_PROTECT 0x00000000 // Sector not protected -#define FLASH_WRITE_PROTECT 0x00000001 // Sector erase and program - // protected - -//***************************************************************************** -// -// Define used by the flash programming and erase functions -// -//***************************************************************************** -#define ADDR_OFFSET (0x1F800000 - FLASHMEM_BASE) - -//***************************************************************************** -// -// Define used for access to factory configuration area. -// -//***************************************************************************** -#define FCFG1_OFFSET 0x1000 - -//***************************************************************************** -// -// Define for the clock frequency input to the flash module in number of MHz -// -//***************************************************************************** -#define FLASH_MODULE_CLK_FREQ 48 - -//***************************************************************************** -// -//! \brief Defined values for Flash State Machine commands -// -//***************************************************************************** -typedef enum -{ - FAPI_PROGRAM_DATA = 0x0002, //!< Program data. - FAPI_ERASE_SECTOR = 0x0006, //!< Erase sector. - FAPI_ERASE_BANK = 0x0008, //!< Erase bank. - FAPI_VALIDATE_SECTOR = 0x000E, //!< Validate sector. - FAPI_CLEAR_STATUS = 0x0010, //!< Clear status. - FAPI_PROGRAM_RESUME = 0x0014, //!< Program resume. - FAPI_ERASE_RESUME = 0x0016, //!< Erase resume. - FAPI_CLEAR_MORE = 0x0018, //!< Clear more. - FAPI_PROGRAM_SECTOR = 0x0020, //!< Program sector. - FAPI_ERASE_OTP = 0x0030 //!< Erase OTP. -} tFlashStateCommandsType; - -//***************************************************************************** -// -// Defines for values written to the FLASH_O_FSM_WR_ENA register -// -//***************************************************************************** -#define FSM_REG_WRT_ENABLE 5 -#define FSM_REG_WRT_DISABLE 2 - -//***************************************************************************** -// -// Defines for the bank power mode field the FLASH_O_FBFALLBACK register -// -//***************************************************************************** -#define FBFALLBACK_SLEEP 0 -#define FBFALLBACK_DEEP_STDBY 1 -#define FBFALLBACK_ACTIVE 3 - -//***************************************************************************** -// -// Defines for the bank grace period and pump grace period -// -//***************************************************************************** -#define FLASH_BAGP 0x14 -#define FLASH_PAGP 0x14 - -//***************************************************************************** -// -// Defines used by the FlashProgramPattern() function -// -//***************************************************************************** -#define PATTERN_BITS 0x20 // No of bits in data pattern to program - -//***************************************************************************** -// -// Defines for the FW flag bits in the FLASH_O_FWFLAG register -// -//***************************************************************************** -#define FW_WRT_TRIMMED 0x00000001 - -//***************************************************************************** -// -// Defines used by the flash programming functions -// -//***************************************************************************** -typedef volatile uint8_t tFwpWriteByte; -#define FWPWRITE_BYTE_ADDRESS ((tFwpWriteByte *)((FLASH_BASE + FLASH_O_FWPWRITE0))) - -//***************************************************************************** -// -// Define for efuse instruction -// -//***************************************************************************** -#define DUMPWORD_INSTR 0x04 - -//***************************************************************************** -// -// Define for FSM command execution -// -//***************************************************************************** -#define FLASH_CMD_EXEC 0x15 - -//***************************************************************************** -// -//! \brief Get size of a flash sector in number of bytes. -//! -//! This function will return the size of a flash sector in number of bytes. -//! -//! \return Returns size of a flash sector in number of bytes. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -FlashSectorSizeGet(void) -{ - uint32_t ui32SectorSizeInKbyte; - - ui32SectorSizeInKbyte = (HWREG(FLASH_BASE + FLASH_O_FCFG_B0_SSIZE0) & - FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M) >> - FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S; - - // Return flash sector size in number of bytes. - return(ui32SectorSizeInKbyte * 1024); -} - -//***************************************************************************** -// -//! \brief Get the size of the flash. -//! -//! This function returns the size of the flash main bank in number of bytes. -//! -//! \return Returns the flash size in number of bytes. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -FlashSizeGet(void) -{ - uint32_t ui32NoOfSectors; - - // Get number of flash sectors - ui32NoOfSectors = (HWREG(FLASH_BASE + FLASH_O_FLASH_SIZE) & - FLASH_FLASH_SIZE_SECTORS_M) >> - FLASH_FLASH_SIZE_SECTORS_S; - - // Return flash size in number of bytes - return(ui32NoOfSectors * FlashSectorSizeGet()); -} - -//***************************************************************************** -// -//! \brief Set power mode. -//! -//! This function will set the specified power mode. -//! -//! Any access to the bank causes a reload of the specified bank grace period -//! input value into the bank down counter. After the last access to the -//! flash bank, the down counter delays from 0 to 255 prescaled HCLK clock -//! cycles before putting the bank into one of the fallback power modes as -//! determined by \c ui32PowerMode. This value must be greater than 1 when the -//! fallback mode is not \ref FLASH_PWR_ACTIVE_MODE. -//! -//! Note: The prescaled clock used for the down counter is a clock divided by -//! 16 from input HCLK. The \c ui32BankGracePeriod parameter is ignored if -//! \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE. -//! Any access to flash memory causes the pump grace period down counter to -//! reload with value of \c ui32PumpGracePeriod. After the bank has gone to sleep, -//! the down counter delays this number of prescaled HCLK clock cycles before -//! entering one of the charge pump fallback power modes as determined by -//! \c ui32PowerMode. The prescaled clock used for the pump grace period down -//! counter is a clock divided by 16 from input HCLK. This parameter is ignored -//! if \c ui32PowerMode is equal to \ref FLASH_PWR_ACTIVE_MODE. -//! -//! Changing the power mode of the flash module must be a part within a -//! device power mode transition requiring configuration of multiple modules. -//! Refer to documents describing the device power modes. -//! -//! \param ui32PowerMode is the wanted power mode. -//! The defined flash power modes are: -//! - \ref FLASH_PWR_ACTIVE_MODE -//! - \ref FLASH_PWR_OFF_MODE -//! - \ref FLASH_PWR_DEEP_STDBY_MODE -//! \param ui32BankGracePeriod is the starting count value for the bank grace -//! period down counter. -//! \param ui32PumpGracePeriod is the starting count value for the pump grace -//! period down counter. -//! -//! \return None -// -//***************************************************************************** -extern void FlashPowerModeSet(uint32_t ui32PowerMode, - uint32_t ui32BankGracePeriod, - uint32_t ui32PumpGracePeriod); - -//***************************************************************************** -// -//! \brief Get current configured power mode. -//! -//! This function will return the current configured power mode. -//! -//! \return Returns the current configured power mode. -//! The defined power modes are: -//! - \ref FLASH_PWR_ACTIVE_MODE -//! - \ref FLASH_PWR_OFF_MODE -//! - \ref FLASH_PWR_DEEP_STDBY_MODE -// -//***************************************************************************** -extern uint32_t FlashPowerModeGet(void); - -//***************************************************************************** -// -//! \brief Set sector protection. -//! -//! This function will set the specified protection on specified flash bank -//! sector. A sector can either have no protection or have write protection -//! which guards for both program and erase of that sector. -//! Sector protection can only be changed from \ref FLASH_NO_PROTECT to -//! \ref FLASH_WRITE_PROTECT! After write protecting a sector this sector can -//! only be set back to unprotected by a device reset. -//! -//! \param ui32SectorAddress is the start address of the sector to protect. -//! \param ui32ProtectMode is the enumerated sector protection mode. -//! - \ref FLASH_NO_PROTECT -//! - \ref FLASH_WRITE_PROTECT -//! -//! \return None -// -//***************************************************************************** -extern void FlashProtectionSet(uint32_t ui32SectorAddress, - uint32_t ui32ProtectMode); - -//***************************************************************************** -// -//! \brief Get sector protection. -//! -//! This return the protection mode for the specified flash bank sector. -//! -//! \param ui32SectorAddress is the start address of the desired sector. -//! -//! \return Returns the sector protection: -//! - \ref FLASH_NO_PROTECT -//! - \ref FLASH_WRITE_PROTECT -// -//***************************************************************************** -extern uint32_t FlashProtectionGet(uint32_t ui32SectorAddress); - -//***************************************************************************** -// -//! \brief Save sector protection to make it permanent. -//! -//! This function will save the current protection mode for the specified -//! flash bank sector. -//! -//! This function must only be executed from ROM or SRAM. -//! -//! \note A write protected sector will become permanent write -//! protected!! A device reset will not change the write protection! -//! -//! \param ui32SectorAddress is the start address of the sector to be protected. -//! -//! \return Returns the status of the sector protection: -//! - \ref FAPI_STATUS_SUCCESS : Success. -//! - \ref FAPI_STATUS_FSM_ERROR : An erase error is encountered. -// -//***************************************************************************** -extern uint32_t FlashProtectionSave(uint32_t ui32SectorAddress); - -//***************************************************************************** -// -//! \brief Checks if the Flash state machine has detected an error. -//! -//! This function returns the status of the Flash State Machine indicating if -//! an error is detected or not. Primary use is to check if an Erase or -//! Program operation has failed. -//! -//! \note Please note that code can not execute in flash while any part of the flash -//! is being programmed or erased. This function must be called from ROM or -//! SRAM while any part of the flash is being programmed or erased. -//! -//! \return Returns status of Flash state machine: -//! - \ref FAPI_STATUS_FSM_ERROR -//! - \ref FAPI_STATUS_SUCCESS -// -//***************************************************************************** -__STATIC_INLINE uint32_t -FlashCheckFsmForError(void) -{ - if(HWREG(FLASH_BASE + FLASH_O_FMSTAT) & FLASH_FMSTAT_CSTAT) - { - return(FAPI_STATUS_FSM_ERROR); - } - else - { - return(FAPI_STATUS_SUCCESS); - } -} - -//***************************************************************************** -// -//! \brief Checks if the Flash state machine is ready. -//! -//! This function returns the status of the Flash State Machine indicating if -//! it is ready to accept a new command or not. Primary use is to check if an -//! Erase or Program operation has finished. -//! -//! \note Please note that code can not execute in flash while any part of the flash -//! is being programmed or erased. This function must be called from ROM or -//! SRAMh while any part of the flash is being programmed or erased. -//! -//! \return Returns readiness status of Flash state machine: -//! - \ref FAPI_STATUS_FSM_READY -//! - \ref FAPI_STATUS_FSM_BUSY -// -//***************************************************************************** -__STATIC_INLINE uint32_t -FlashCheckFsmForReady(void) -{ - if(HWREG(FLASH_BASE + FLASH_O_STAT) & FLASH_STAT_BUSY) - { - return(FAPI_STATUS_FSM_BUSY); - } - else - { - return(FAPI_STATUS_FSM_READY); - } -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for the flash interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific FLASH interrupts must be enabled via \ref FlashIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source. -//! -//! \param pfnHandler is a pointer to the function to be called when the flash -//! interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -FlashIntRegister(void (*pfnHandler)(void)) -{ - // Register the interrupt handler. - IntRegister(INT_FLASH, pfnHandler); - - // Enable the flash interrupt. - IntEnable(INT_FLASH); -} - -//***************************************************************************** -// -//! \brief Unregisters the interrupt handler for the flash interrupt in the dynamic interrupt table. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a FLASH interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -FlashIntUnregister(void) -{ - // Disable the interrupts. - IntDisable(INT_FLASH); - - // Unregister the interrupt handler. - IntUnregister(INT_FLASH); -} - -//***************************************************************************** -// -//! \brief Enables flash controller interrupt sources. -//! -//! This function enables the flash controller interrupt sources. -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! The parameter is the bitwise OR of any of the following: -//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt. -//! - \ref FLASH_INT_RV : Read verify error interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -FlashIntEnable(uint32_t ui32IntFlags) -{ - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) |= ui32IntFlags; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; -} - -//***************************************************************************** -// -//! \brief Disables individual flash controller interrupt sources. -//! -//! This function disables the flash controller interrupt sources. -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. -//! The parameter is the bitwise OR of any of the following: -//! - \ref FLASH_INT_FSM_DONE : FSM Done interrupt. -//! - \ref FLASH_INT_RV : Read verify error interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -FlashIntDisable(uint32_t ui32IntFlags) -{ - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_ENABLE; - HWREG(FLASH_BASE + FLASH_O_FSM_ST_MACHINE) &= ~ui32IntFlags; - HWREG(FLASH_BASE + FLASH_O_FSM_WR_ENA) = FSM_REG_WRT_DISABLE; -} - -//***************************************************************************** -// -//! \brief Gets the current interrupt status. -//! -//! This function returns the interrupt status for the Flash. -//! -//! \return Returns the current interrupt status as values described in -//! \ref FlashIntEnable(). -// -//***************************************************************************** -__STATIC_INLINE uint32_t -FlashIntStatus(void) -{ - uint32_t ui32IntFlags; - - ui32IntFlags = 0; - - // Check if FSM_DONE interrupt status is set. - if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_FSM_DONE) - { - ui32IntFlags = FLASH_INT_FSM_DONE; - } - - // Check if RVF_INT interrupt status is set. - if(HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) & FLASH_FEDACSTAT_RVF_INT) - { - ui32IntFlags |= FLASH_INT_RV; - } - - return(ui32IntFlags); -} - -//***************************************************************************** -// -//! \brief Clears flash controller interrupt source. -//! -//! The flash controller interrupt source is cleared, so that it no longer -//! asserts. This must be done in the interrupt handler to keep it from being -//! called again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be cleared. -//! Can be any of: -//! - \ref FLASH_INT_FSM_DONE -//! - \ref FLASH_INT_RV -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -FlashIntClear(uint32_t ui32IntFlags) -{ - uint32_t ui32TempVal; - - ui32TempVal = 0; - - if(ui32IntFlags & FLASH_INT_FSM_DONE) - { - ui32TempVal = FLASH_FEDACSTAT_FSM_DONE; - } - - if(ui32IntFlags & FLASH_INT_RV) - { - ui32TempVal |= FLASH_FEDACSTAT_RVF_INT; - } - - // Clear the flash interrupt source. - HWREG(FLASH_BASE + FLASH_O_FEDACSTAT) = ui32TempVal; -} - -//***************************************************************************** -// -//! \brief Erase a flash sector. -//! -//! This function will erase the specified flash sector. The function will -//! not return until the flash sector has been erased or an error condition -//! occurred. If flash top sector is erased the function will program the -//! the device security data bytes with default values. The device security -//! data located in the customer configuration area of the flash top sector, -//! must have valid values at all times. These values affect the configuration -//! of the device during boot. -//! -//! \warning Please note that code can not execute in flash while any part of the flash -//! is being programmed or erased. The application must disable interrupts that have -//! interrupt routines in flash. This function calls a ROM function which handles the -//! actual program operation. -//! -//! \param ui32SectorAddress is the starting address in flash of the sector to be -//! erased. -//! -//! \return Returns the status of the sector erase: -//! - \ref FAPI_STATUS_SUCCESS : Success. -//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Invalid argument. -//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered. -// -//***************************************************************************** -extern uint32_t FlashSectorErase(uint32_t ui32SectorAddress); - - -//***************************************************************************** -// -//! \brief Programs unprotected flash sectors in the main bank. -//! -//! This function programs a sequence of bytes into the on-chip flash. -//! Programming each location consists of the result of an AND operation -//! of the new data and the existing data; in other words bits that contain -//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed -//! to 1. Therefore, a byte can be programmed multiple times as long as these -//! rules are followed; if a program operation attempts to change a 0 bit to -//! a 1 bit, that bit will not have its value changed. -//! -//! This function does not return until the data has been programmed or a -//! programming error occurs. -//! -//! \note It is recommended to disable cache and line buffer before programming the -//! flash. Cache and line buffer are not automatically updated if a flash program -//! causes a mismatch between new flash content and old content in cache and -//! line buffer. Remember to enable cache and line buffer when the program -//! operation completes. See \ref VIMSModeSafeSet(), \ref VIMSLineBufDisable(), -//! and \ref VIMSLineBufEnable() for more information. -//! -//! \warning Please note that code can not execute in flash while any part of the flash -//! is being programmed or erased. The application must disable interrupts that have -//! interrupt routines in flash. This function calls a ROM function which handles the -//! actual program operation. -//! -//! The \c pui8DataBuffer pointer can not point to flash. -//! -//! \param pui8DataBuffer is a pointer to the data to be programmed. -//! \param ui32Address is the starting address in flash to be programmed. -//! \param ui32Count is the number of bytes to be programmed. -//! -//! \return Returns status of the flash programming: -//! - \ref FAPI_STATUS_SUCCESS : Success. -//! - \ref FAPI_STATUS_INCORRECT_DATABUFFER_LENGTH : Too many bytes were requested. -//! - \ref FAPI_STATUS_FSM_ERROR : A programming error is encountered. -// -//***************************************************************************** -extern uint32_t FlashProgram(uint8_t *pui8DataBuffer, - uint32_t ui32Address, uint32_t ui32Count); - -//***************************************************************************** -// -//! \brief Reads efuse data from specified row. -//! -//! This function will read one efuse row. -//! It is assumed that any previous efuse operation has finished. -//! -//! \param pui32EfuseData is pointer to variable to be updated with efuse data. -//! \param ui32RowAddress is the efuse row number to be read. First row is row -//! number 0. -//! -//! \return Returns the status of the efuse read operation. -//! - \c false : OK status. -//! - \c true : Error status -// -//***************************************************************************** -extern bool FlashEfuseReadRow(uint32_t *pui32EfuseData, - uint32_t ui32RowAddress); - -//***************************************************************************** -// -//! \brief Disables all sectors for erase and programming on the active bank. -//! -//! This function disables all sectors for erase and programming on the active -//! bank and enables the Idle Reading Power reduction mode if no low power -//! mode is configured. Furthermore, an additional level of protection from -//! erase is enabled. -//! -//! \note Please note that code can not execute in flash while any part of the flash -//! is being programmed or erased. -//! -//! \return None -// -//***************************************************************************** -extern void FlashDisableSectorsForWrite(void); - - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_FlashPowerModeSet - #undef FlashPowerModeSet - #define FlashPowerModeSet ROM_FlashPowerModeSet - #endif - #ifdef ROM_FlashPowerModeGet - #undef FlashPowerModeGet - #define FlashPowerModeGet ROM_FlashPowerModeGet - #endif - #ifdef ROM_FlashProtectionSet - #undef FlashProtectionSet - #define FlashProtectionSet ROM_FlashProtectionSet - #endif - #ifdef ROM_FlashProtectionGet - #undef FlashProtectionGet - #define FlashProtectionGet ROM_FlashProtectionGet - #endif - #ifdef ROM_FlashProtectionSave - #undef FlashProtectionSave - #define FlashProtectionSave ROM_FlashProtectionSave - #endif - #ifdef ROM_FlashSectorErase - #undef FlashSectorErase - #define FlashSectorErase ROM_FlashSectorErase - #endif - #ifdef ROM_FlashProgram - #undef FlashProgram - #define FlashProgram ROM_FlashProgram - #endif - #ifdef ROM_FlashEfuseReadRow - #undef FlashEfuseReadRow - #define FlashEfuseReadRow ROM_FlashEfuseReadRow - #endif - #ifdef ROM_FlashDisableSectorsForWrite - #undef FlashDisableSectorsForWrite - #define FlashDisableSectorsForWrite ROM_FlashDisableSectorsForWrite - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.c deleted file mode 100644 index ace56ae8cff..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.c +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: gpio.c -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Driver for the GPIO -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "gpio.h" - -// see gpio.h for implementation diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h deleted file mode 100644 index 2829ea62b19..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio.h +++ /dev/null @@ -1,643 +0,0 @@ -/****************************************************************************** -* Filename: gpio.h -* Revised: 2018-05-02 11:11:40 +0200 (Wed, 02 May 2018) -* Revision: 51951 -* -* Description: Defines and prototypes for the GPIO. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup gpio_api -//! @{ -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_gpio.h" -#include "debug.h" - -//***************************************************************************** -// -// Check for legal range of variable dioNumber -// -//***************************************************************************** -#ifdef DRIVERLIB_DEBUG -#include "../inc/hw_fcfg1.h" -#include "chipinfo.h" - -static bool -dioNumberLegal( uint32_t dioNumber ) -{ - uint32_t ioCount = - (( HWREG( FCFG1_BASE + FCFG1_O_IOCONF ) & - FCFG1_IOCONF_GPIO_CNT_M ) >> - FCFG1_IOCONF_GPIO_CNT_S ) ; - - // CC13x2 + CC26x2 - if ( ChipInfo_ChipFamilyIs_CC13x2_CC26x2() ) - { - return ( (dioNumber >= (31 - ioCount)) && (dioNumber < 31) ) - } - // Special handling of CC13x0 7x7, where IO_CNT = 30 and legal range is 1..30 - // for all other chips legal range is 0..(dioNumber-1) - else if (( ioCount == 30 ) && ChipInfo_ChipFamilyIs_CC13x0() ) - { - return (( dioNumber > 0 ) && ( dioNumber <= ioCount )); - } - else - { - return ( dioNumber < ioCount ); - } - -} -#endif - -//***************************************************************************** -// -// The following values define the bit field for the GPIO DIOs. -// -//***************************************************************************** -#define GPIO_DIO_0_MASK 0x00000001 // GPIO DIO 0 mask -#define GPIO_DIO_1_MASK 0x00000002 // GPIO DIO 1 mask -#define GPIO_DIO_2_MASK 0x00000004 // GPIO DIO 2 mask -#define GPIO_DIO_3_MASK 0x00000008 // GPIO DIO 3 mask -#define GPIO_DIO_4_MASK 0x00000010 // GPIO DIO 4 mask -#define GPIO_DIO_5_MASK 0x00000020 // GPIO DIO 5 mask -#define GPIO_DIO_6_MASK 0x00000040 // GPIO DIO 6 mask -#define GPIO_DIO_7_MASK 0x00000080 // GPIO DIO 7 mask -#define GPIO_DIO_8_MASK 0x00000100 // GPIO DIO 8 mask -#define GPIO_DIO_9_MASK 0x00000200 // GPIO DIO 9 mask -#define GPIO_DIO_10_MASK 0x00000400 // GPIO DIO 10 mask -#define GPIO_DIO_11_MASK 0x00000800 // GPIO DIO 11 mask -#define GPIO_DIO_12_MASK 0x00001000 // GPIO DIO 12 mask -#define GPIO_DIO_13_MASK 0x00002000 // GPIO DIO 13 mask -#define GPIO_DIO_14_MASK 0x00004000 // GPIO DIO 14 mask -#define GPIO_DIO_15_MASK 0x00008000 // GPIO DIO 15 mask -#define GPIO_DIO_16_MASK 0x00010000 // GPIO DIO 16 mask -#define GPIO_DIO_17_MASK 0x00020000 // GPIO DIO 17 mask -#define GPIO_DIO_18_MASK 0x00040000 // GPIO DIO 18 mask -#define GPIO_DIO_19_MASK 0x00080000 // GPIO DIO 19 mask -#define GPIO_DIO_20_MASK 0x00100000 // GPIO DIO 20 mask -#define GPIO_DIO_21_MASK 0x00200000 // GPIO DIO 21 mask -#define GPIO_DIO_22_MASK 0x00400000 // GPIO DIO 22 mask -#define GPIO_DIO_23_MASK 0x00800000 // GPIO DIO 23 mask -#define GPIO_DIO_24_MASK 0x01000000 // GPIO DIO 24 mask -#define GPIO_DIO_25_MASK 0x02000000 // GPIO DIO 25 mask -#define GPIO_DIO_26_MASK 0x04000000 // GPIO DIO 26 mask -#define GPIO_DIO_27_MASK 0x08000000 // GPIO DIO 27 mask -#define GPIO_DIO_28_MASK 0x10000000 // GPIO DIO 28 mask -#define GPIO_DIO_29_MASK 0x20000000 // GPIO DIO 29 mask -#define GPIO_DIO_30_MASK 0x40000000 // GPIO DIO 30 mask -#define GPIO_DIO_31_MASK 0x80000000 // GPIO DIO 31 mask -#define GPIO_DIO_ALL_MASK 0xFFFFFFFF // GPIO all DIOs mask - -//***************************************************************************** -// -// Define constants that shall be passed as the outputEnableValue parameter to -// GPIO_setOutputEnableDio() and will be returned from the function -// GPIO_getOutputEnableDio(). -// -//***************************************************************************** -#define GPIO_OUTPUT_DISABLE 0x00000000 // DIO output is disabled -#define GPIO_OUTPUT_ENABLE 0x00000001 // DIO output is enabled - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Reads a specific DIO. -//! -//! \param dioNumber specifies the DIO to read (0-31). -//! -//! \return Returns 0 or 1 reflecting the input value of the specified DIO. -//! -//! \sa \ref GPIO_readMultiDio(), \ref GPIO_writeDio(), \ref GPIO_writeMultiDio() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -GPIO_readDio( uint32_t dioNumber ) -{ - // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - - // Return the input value from the specified DIO. - return (( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) >> dioNumber ) & 1 ); -} - -//***************************************************************************** -// -//! \brief Reads the input value for the specified DIOs. -//! -//! This function returns the input value for multiple DIOs. -//! The value returned is not shifted and hence matches the corresponding dioMask bits. -//! -//! \param dioMask is the bit-mask representation of the DIOs to read. -//! The parameter must be a bitwise OR'ed combination of the following: -//! - \ref GPIO_DIO_0_MASK -//! - ... -//! - \ref GPIO_DIO_31_MASK -//! -//! \return Returns a bit vector reflecting the input value of the corresponding DIOs. -//! - 0 : Corresponding DIO is low. -//! - 1 : Corresponding DIO is high. -//! -//! \sa \ref GPIO_readDio(), \ref GPIO_writeDio(), \ref GPIO_writeMultiDio() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -GPIO_readMultiDio( uint32_t dioMask ) -{ - // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); - - // Return the input value from the specified DIOs. - return ( HWREG( GPIO_BASE + GPIO_O_DIN31_0 ) & dioMask ); -} - -//***************************************************************************** -// -//! \brief Writes a value to a specific DIO. -//! -//! \param dioNumber specifies the DIO to update (0-31). -//! \param value specifies the value to write -//! - 0 : Logic zero (low) -//! - 1 : Logic one (high) -//! -//! \return None -//! -//! \sa \ref GPIO_writeMultiDio(), \ref GPIO_readDio(), \ref GPIO_readMultiDio() -// -//***************************************************************************** -__STATIC_INLINE void -GPIO_writeDio( uint32_t dioNumber, uint32_t value ) -{ - // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - ASSERT(( value == 0 ) || ( value == 1 )); - - // Write 0 or 1 to the byte indexed DOUT map - HWREGB( GPIO_BASE + dioNumber ) = value; -} - -//***************************************************************************** -// -//! \brief Writes masked data to the specified DIOs. -//! -//! Enables for writing multiple bits simultaneously. -//! The value to write must be shifted so it matches the corresponding dioMask bits. -//! -//! \note Note that this is a read-modify-write operation and hence not atomic. -//! -//! \param dioMask is the bit-mask representation of the DIOs to write. -//! The parameter must be a bitwise OR'ed combination of the following: -//! - \ref GPIO_DIO_0_MASK -//! - ... -//! - \ref GPIO_DIO_31_MASK -//! \param bitVectoredValue holds the value to be written to the corresponding DIO-bits. -//! -//! \return None -//! -//! \sa \ref GPIO_writeDio(), \ref GPIO_readDio(), \ref GPIO_readMultiDio() -// -//***************************************************************************** -__STATIC_INLINE void -GPIO_writeMultiDio( uint32_t dioMask, uint32_t bitVectoredValue ) -{ - // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); - - HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) = - ( HWREG( GPIO_BASE + GPIO_O_DOUT31_0 ) & ~dioMask ) | - ( bitVectoredValue & dioMask ); -} - -//***************************************************************************** -// -//! \brief Sets a specific DIO to 1 (high). -//! -//! \param dioNumber specifies the DIO to set (0-31). -//! -//! \return None -//! -//! \sa \ref GPIO_setMultiDio(), \ref GPIO_clearDio(), \ref GPIO_clearMultiDio() -// -//***************************************************************************** -__STATIC_INLINE void -GPIO_setDio( uint32_t dioNumber ) -{ - // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - - // Set the specified DIO. - HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = ( 1 << dioNumber ); -} - -//***************************************************************************** -// -//! \brief Sets the specified DIOs to 1 (high). -//! -//! \param dioMask is the bit-mask representation of the DIOs to set. -//! The parameter must be a bitwise OR'ed combination of the following: -//! - \ref GPIO_DIO_0_MASK -//! - ... -//! - \ref GPIO_DIO_31_MASK -//! -//! \return None -//! -//! \sa \ref GPIO_setDio(), \ref GPIO_clearDio(), \ref GPIO_clearMultiDio() -// -//***************************************************************************** -__STATIC_INLINE void -GPIO_setMultiDio( uint32_t dioMask ) -{ - // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); - - // Set the DIOs. - HWREG( GPIO_BASE + GPIO_O_DOUTSET31_0 ) = dioMask; -} - -//***************************************************************************** -// -//! \brief Clears a specific DIO to 0 (low). -//! -//! \param dioNumber specifies the DIO to clear (0-31). -//! -//! \return None -//! -//! \sa \ref GPIO_clearMultiDio(), \ref GPIO_setDio(), \ref GPIO_setMultiDio() -// -//***************************************************************************** -__STATIC_INLINE void -GPIO_clearDio( uint32_t dioNumber ) -{ - // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - - // Clear the specified DIO. - HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = ( 1 << dioNumber ); -} - -//***************************************************************************** -// -//! \brief Clears the specified DIOs to 0 (low). -//! -//! \param dioMask is the bit-mask representation of the DIOs to clear. -//! The parameter must be a bitwise OR'ed combination of the following: -//! - \ref GPIO_DIO_0_MASK -//! - ... -//! - \ref GPIO_DIO_31_MASK -//! -//! \return None -//! -//! \sa \ref GPIO_clearDio(), \ref GPIO_setDio(), \ref GPIO_setMultiDio() -// -//***************************************************************************** -__STATIC_INLINE void -GPIO_clearMultiDio( uint32_t dioMask ) -{ - // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); - - // Clear the DIOs. - HWREG( GPIO_BASE + GPIO_O_DOUTCLR31_0 ) = dioMask; -} - -//***************************************************************************** -// -//! \brief Toggles a specific DIO. -//! -//! \param dioNumber specifies the DIO to toggle (0-31). -//! -//! \return None -//! -//! \sa \ref GPIO_toggleMultiDio() -// -//***************************************************************************** -__STATIC_INLINE void -GPIO_toggleDio( uint32_t dioNumber ) -{ - // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - - // Toggle the specified DIO. - HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = ( 1 << dioNumber ); -} - -//***************************************************************************** -// -//! \brief Toggles the specified DIOs. -//! -//! \param dioMask is the bit-mask representation of the DIOs to toggle. -//! The parameter must be a bitwise OR'ed combination of the following: -//! - \ref GPIO_DIO_0_MASK -//! - ... -//! - \ref GPIO_DIO_31_MASK -//! -//! \return None -//! -//! \sa \ref GPIO_toggleDio() -// -//***************************************************************************** -__STATIC_INLINE void -GPIO_toggleMultiDio( uint32_t dioMask ) -{ - // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); - - // Toggle the DIOs. - HWREG( GPIO_BASE + GPIO_O_DOUTTGL31_0 ) = dioMask; -} - -//***************************************************************************** -// -//! \brief Gets the output enable status of a specific DIO. -//! -//! This function returns the output enable status for the specified DIO. -//! The DIO can be configured as either input or output under software control. -//! -//! \param dioNumber specifies the DIO to get the output enable setting from (0-31). -//! -//! \return Returns one of the enumerated data types (0 or 1): -//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled. -//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled. -//! -//! \sa \ref GPIO_getOutputEnableMultiDio(), \ref GPIO_setOutputEnableDio(), \ref GPIO_setOutputEnableMultiDio() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -GPIO_getOutputEnableDio( uint32_t dioNumber ) -{ - // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - - // Return the output enable status for the specified DIO. - return (( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) >> dioNumber ) & 1 ); -} - -//***************************************************************************** -// -//! \brief Gets the output enable setting of the specified DIOs. -//! -//! This function returns the output enable setting for multiple DIOs. -//! The value returned is not shifted and hence matches the corresponding dioMask bits. -//! -//! \param dioMask is the bit-mask representation of the DIOs to return the output enable settings from. -//! The parameter must be a bitwise OR'ed combination of the following: -//! - \ref GPIO_DIO_0_MASK -//! - ... -//! - \ref GPIO_DIO_31_MASK -//! -//! \return Returns the output enable setting for multiple DIOs as a bit vector corresponding to the dioMask bits. -//! - 0 : Corresponding DIO is configured with output disabled. -//! - 1 : Corresponding DIO is configured with output enabled. -//! -//! \sa \ref GPIO_getOutputEnableDio(), \ref GPIO_setOutputEnableDio(), \ref GPIO_setOutputEnableMultiDio() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -GPIO_getOutputEnableMultiDio( uint32_t dioMask ) -{ - // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); - - // Return the output enable value for the specified DIOs. - return ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & dioMask ); -} - -//***************************************************************************** -// -//! \brief Sets output enable of a specific DIO. -//! -//! This function sets the GPIO output enable bit for the specified DIO. -//! The DIO can be configured as either input or output under software control. -//! -//! \param dioNumber specifies the DIO to configure (0-31). -//! \param outputEnableValue specifies the output enable setting of the specified DIO: -//! - \ref GPIO_OUTPUT_DISABLE : DIO output is disabled. -//! - \ref GPIO_OUTPUT_ENABLE : DIO output is enabled. -//! -//! \return None -//! -//! \sa \ref GPIO_setOutputEnableMultiDio(), \ref GPIO_getOutputEnableDio(), \ref GPIO_getOutputEnableMultiDio() -// -//***************************************************************************** -__STATIC_INLINE void -GPIO_setOutputEnableDio( uint32_t dioNumber, uint32_t outputEnableValue ) -{ - // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - ASSERT(( outputEnableValue == GPIO_OUTPUT_DISABLE ) || - ( outputEnableValue == GPIO_OUTPUT_ENABLE ) ); - - // Update the output enable bit for the specified DIO. - HWREGBITW( GPIO_BASE + GPIO_O_DOE31_0, dioNumber ) = outputEnableValue; -} - -//***************************************************************************** -// -//! \brief Configures the output enable setting for all specified DIOs. -//! -//! This function configures the output enable setting for the specified DIOs. -//! The output enable setting must be shifted so it matches the corresponding dioMask bits. -//! The DIOs can be configured as either an input or output under software control. -//! -//! \note Note that this is a read-modify-write operation and hence not atomic. -//! -//! \param dioMask is the bit-mask representation of the DIOs on which to configure the -//! output enable setting. The parameter must be a bitwise OR'ed combination of the following: -//! - \ref GPIO_DIO_0_MASK -//! - ... -//! - \ref GPIO_DIO_31_MASK -//! \param bitVectoredOutputEnable holds the output enable setting the corresponding DIO-bits: -//! - 0 : Corresponding DIO is configured with output disabled. -//! - 1 : Corresponding DIO is configured with output enabled. -//! -//! \return None -//! -//! \sa \ref GPIO_setOutputEnableDio(), \ref GPIO_getOutputEnableDio(), \ref GPIO_getOutputEnableMultiDio() -// -//***************************************************************************** -__STATIC_INLINE void -GPIO_setOutputEnableMultiDio( uint32_t dioMask, uint32_t bitVectoredOutputEnable ) -{ - // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); - - HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) = - ( HWREG( GPIO_BASE + GPIO_O_DOE31_0 ) & ~dioMask ) | - ( bitVectoredOutputEnable & dioMask ); -} - -//***************************************************************************** -// -//! \brief Gets the event status of a specific DIO. -//! -//! \param dioNumber specifies the DIO to get the event status from (0-31). -//! -//! \return Returns the current event status on the specified DIO. -//! - 0 : Non-triggered event. -//! - 1 : Triggered event. -//! -//! \sa \ref GPIO_getEventMultiDio(), \ref GPIO_clearEventDio(), \ref GPIO_clearEventMultiDio() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -GPIO_getEventDio( uint32_t dioNumber ) -{ - // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - - // Return the event status for the specified DIO. - return (( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) >> dioNumber ) & 1 ); -} - -//***************************************************************************** -// -//! \brief Gets the event status of the specified DIOs. -//! -//! This function returns the event status for multiple DIOs. -//! The value returned is not shifted and hence matches the corresponding dioMask bits. -//! -//! \param dioMask is the bit-mask representation of the DIOs to get the -//! event status from (0-31). -//! The parameter must be a bitwise OR'ed combination of the following: -//! - \ref GPIO_DIO_0_MASK -//! - ... -//! - \ref GPIO_DIO_31_MASK -//! -//! \return Returns a bit vector with the current event status corresponding to the specified DIOs. -//! - 0 : Corresponding DIO has no triggered event. -//! - 1 : Corresponding DIO has a triggered event. -//! -//! \sa \ref GPIO_getEventDio(), \ref GPIO_clearEventDio(), \ref GPIO_clearEventMultiDio() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -GPIO_getEventMultiDio( uint32_t dioMask ) -{ - // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); - - // Return the event status for the specified DIO. - return ( HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) & dioMask ); -} - -//***************************************************************************** -// -//! \brief Clears the IO event status of a specific DIO. -//! -//! \param dioNumber specifies the DIO on which to clear the event status (0-31). -//! -//! \return None -//! -//! \sa \ref GPIO_clearEventMultiDio(), \ref GPIO_getEventDio(), \ref GPIO_getEventMultiDio() -// -//***************************************************************************** -__STATIC_INLINE void -GPIO_clearEventDio( uint32_t dioNumber ) -{ - // Check the arguments. - ASSERT( dioNumberLegal( dioNumber )); - - // Clear the event status for the specified DIO. - HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = ( 1 << dioNumber ); -} - -//***************************************************************************** -// -//! \brief Clears the IO event status on the specified DIOs. -//! -//! \param dioMask is the bit-mask representation of the DIOs on which to -//! clear the events status. -//! The parameter must be a bitwise OR'ed combination of the following: -//! - \ref GPIO_DIO_0_MASK -//! - ... -//! - \ref GPIO_DIO_31_MASK -//! -//! \return None -//! -//! \sa \ref GPIO_clearEventDio(), \ref GPIO_getEventDio(), \ref GPIO_getEventMultiDio() -// -//***************************************************************************** -__STATIC_INLINE void -GPIO_clearEventMultiDio( uint32_t dioMask ) -{ - // Check the arguments. - ASSERT( dioMask & GPIO_DIO_ALL_MASK ); - - // Clear the event status for the specified DIOs. - HWREG( GPIO_BASE + GPIO_O_EVFLAGS31_0 ) = dioMask; -} - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h deleted file mode 100644 index bdee473788f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/gpio_doc.h +++ /dev/null @@ -1,90 +0,0 @@ -/****************************************************************************** -* Filename: gpio_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup gpio_api -//! @{ -//! \section sec_gpio Introduction -//! -//! The GPIO module allows software to control the pins of the device directly if the IOC module has -//! been configured to route the GPIO signal to a physical pin (called DIO). Alternatively, pins can -//! be hardware controlled by other peripheral modules. For more information about the IOC module, -//! how to configure physical pins, and how to select between software controlled and hardware controlled, -//! see the [IOC API](\ref ioc_api). -//! -//! The System CPU can access the GPIO module to read the value of any DIO of the device and if the IOC -//! module has been configured such that one or more DIOs are GPIO controlled (software controlled) the -//! System CPU can write these DIOs through the GPIO module. -//! -//! The IOC module can also be configured to generate events on edge detection and these events can be -//! read and cleared in the GPIO module by the System CPU. -//! -//! \section sec_gpio_api API -//! -//! The API functions can be grouped like this: -//! -//! Set and get direction of DIO (output enable): -//! - \ref GPIO_setOutputEnableDio() -//! - \ref GPIO_setOutputEnableMultiDio() -//! - \ref GPIO_getOutputEnableDio() -//! - \ref GPIO_getOutputEnableMultiDio() -//! -//! Write DIO (requires IOC to be configured for GPIO usage): -//! - \ref GPIO_writeDio() -//! - \ref GPIO_writeMultiDio() -//! -//! Set, clear, or toggle DIO (requires IOC to be configured for GPIO usage): -//! - \ref GPIO_setDio() -//! - \ref GPIO_setMultiDio() -//! - \ref GPIO_clearDio() -//! - \ref GPIO_clearMultiDio() -//! - \ref GPIO_toggleDio() -//! - \ref GPIO_toggleMultiDio() -//! -//! Read DIO (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC): -//! - \ref GPIO_readDio() -//! - \ref GPIO_readMultiDio() -//! -//! Read or clear events (even if IOC is NOT configured for GPIO usage; however, the DIO must be configured for input enable in IOC): -//! - \ref GPIO_getEventDio() -//! - \ref GPIO_getEventMultiDio() -//! - \ref GPIO_clearEventDio() -//! - \ref GPIO_clearEventMultiDio() -//! -//! The [IOC API](\ref ioc_api) provides two functions for easy configuration of DIOs as GPIO enabled using -//! typical settings. They also serve as examples on how to configure the IOC and GPIO modules for GPIO usage: -//! - \ref IOCPinTypeGpioInput() -//! - \ref IOCPinTypeGpioOutput() -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h deleted file mode 100644 index 67422a54b36..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_analog_doc.h +++ /dev/null @@ -1,105 +0,0 @@ -/****************************************************************************** -* Filename: group_analog_doc.h -* Revised: 2016-08-30 14:34:13 +0200 (Tue, 30 Aug 2016) -* Revision: 47080 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup analog_group -//! @{ -//! \section sec_analog Introduction -//! -//! Access to registers in the analog domain of the device goes through master modules controlling slave -//! modules which contain the actual registers. The master module is located in the digital domain of the -//! device. The interfaces between master and slave modules are called ADI (Analog-to-Digital Interface) -//! and DDI (Digital-to-Digital Interface) depending on the type of module to access and thus the slave -//! modules are referred to as ADI slave and DDI slave. -//! -//! The ADI and DDI APIs provide access to these registers: -//! - ADI_2_REFSYS : Reference System for generating reference voltages and reference currents. -//! - Reference system control -//! - SOC LDO control -//! - ADI_3_REFSYS : Reference System for generating reference voltages and reference currents. -//! - Reference system control -//! - DC/DC control -//! - ADI_4_AUX : Controlling analog peripherals of AUX. -//! - Multiplexers -//! - Current source -//! - Comparators -//! - ADCs -//! - DDI_0_OSC : Controlling the oscillators (via AUX domain) -//! -//! The register descriptions of CPU memory map document the ADI/DDI masters. The register descriptions of -//! analog memory map document the ADI/DDI slaves. The ADI/DDI APIs allow the programmer to focus on the -//! slave registers of interest without being concerned with the ADI/DDI master part of the interface. -//! -//! Although the ADI/DDI APIs make the master "transparent" it can be useful to know a few details about -//! the ADI/DDI protocol and how the master handles transactions as it can affect how the system CPU performs. -//! - ADI protocol uses 8-bit write bus compared to 32-bit write bus in DDI. ADI protocol uses 4-bit read -//! bus compared to 16-bit read bus in DDI. Hence a 32-bit read from an ADI register is translated into 8 -//! transactions in the ADI protocol. -//! - One transaction on the ADI/DDI protocol takes several clock cycles for the master to complete. -//! - ADI slave registers are 8-bit wide. -//! - DDI slave registers are 32-bit wide. -//! - ADI/DDI master supports multiple data width accesses seen from the system CPU -//! (however, not all bit width accesses are supported by the APIs): -//! - Read: 8, 16, 32-bit -//! - Write -//! - Direct (write, set, clear): 8, 16, 32-bit -//! - Masked: 4, 8, 16-bit -//! -//! Making posted/buffered writes from the system CPU (default) to the ADI/DDI allows the system CPU to continue -//! while the ADI/DDI master handles the transactions on the ADI/DDI protocol. If using non-posted/non-buffered -//! writes the system CPU will wait for ADI/DDI master to complete the transactions to the slave before continuing -//! execution. -//! -//! Reading from ADI/DDI requires that all transactions on the ADI/DDI protocol have completed before the system CPU -//! receives the response thus the programmer must understand that the response time depends on the number of bytes -//! read. However, due to the 'set', 'clear' and 'masked write' features of the ADI/DDI most writes can be done -//! without the typical read-modify-write sequence thus reducing the need for reads to a minimum. -//! -//! Consequently, if making posted/buffered writes then the written value will not take effect in the -//! analog domain until some point later in time. An alternative to non-posted/non-buffered writes - in order to make -//! sure a written value has taken effect - is to read from the same ADI/DDI as the write as this will keep the system CPU -//! waiting until both the write and the read have completed. -//! -//! \note -//! Do NOT use masked write when writing bit fields spanning the "masked write boundary" i.e. the widest possible -//! masked write that the protocol supports (ADI = 4 bits, DDI = 16 bits). This will put the device into a -//! temporary state - which is potentially harmful to the device - as the bit field will be written over two transactions. -//! Thus to use masked writes: -//! - For ADI the bit field(s) must be within bit 0 to 3 (REG[3:0]) or bit 4 to 7 (REG[7:4]). -//! - For DDI the bit field(s) must be within bit 0 to 15 (REG[15:0]) or bit 16 to 31 (REG[31:16]). -//! -//! \note -//! If masked write is not allowed, a regular read-modify-write is necessary. -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h deleted file mode 100644 index 55cc2ea88d8..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_aon_doc.h +++ /dev/null @@ -1,76 +0,0 @@ -/****************************************************************************** -* Filename: group_aon_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup aon_group -//! @{ -//! \section sec_aon Introduction -//! -//! The Always-ON (AON) voltage domain contains the AUX power domain, AON power domain, and JTAG power domain. -//! The AON API includes functions to access the AON power domain. For functions accessing the AUX power domain -//! see the [AUX API](@ref aux_group). -//! -//! The AON power domain contains circuitry that is always enabled, except for the shutdown mode -//! (digital supply is off), and the AON power domain is clocked at 32-kHz. -//! -//! The AON API accesses the AON registers through a common module called AON Interface (AON IF) which handles the -//! actual transactions towards the much slower AON registers. Because accessing AON can cause a significant -//! delay in terms of system CPU clock cycles it is important to understand the basics about how the AON IF -//! operates. The following list describes a few of the most relevant properties of the AON IF seen from the system CPU: -//! - \ti_bold{Shadow registers}: The system CPU actually accesses a set of "shadow registers" which are being synchronized to the AON registers -//! by the AON IF every AON clock cycle. -//! - Writing an AON register via AON IF can take up to one AON clock cycle before taking effect in the AON domain. However, the system CPU can -//! continue executing without waiting for this. -//! - The AON IF supports multiple writes within the same AON clock cycle thus several registers/bit fields can be synchronized simultaneously. -//! - Reading from AON IF returns the value from last time the shadow registers were synchronized (if no writes to AON IF have occurred since) -//! thus the value can be up to one AON clock cycle old. -//! - Reading from AON IF after a write (but before synchronization has happened) will return the value from the shadow register -//! and not the last value from the AON register. Thus doing multiple read-modify-writes within one AON clock cycle is supported. -//! - \ti_bold{Read delay}: Due to an asynchronous interface to the AON IF, reading AON registers will generate a few wait cycles thus stalling -//! the system CPU until the read completes. There is no delay on writes to AON IF if using posted/buffered writes. -//! - \ti_bold{Synchronizing}: If it is required that a write to AON takes effect before continuing code execution it is possible to do a conditional "wait for -//! synchronization" by calling \ref SysCtrlAonSync(). This will wait for any pending writes to synchronize. -//! - \ti_bold{Updating}: It is also possible to do an unconditional "wait for synchronization", in case a new read -//! value is required, by calling \ref SysCtrlAonUpdate(). This is typically used after wake-up to make sure the AON IF has been -//! synchronized at least once before reading the values. -//! -//! Below are a few guidelines to write efficient code for AON access based on the properties of the interface to the AON registers. -//! - Avoid synchronizing unless required by the application. If synchronization is needed then try to group/arrange AON writes to -//! minimize the number of required synchronizations. -//! - If modifying several bit fields within a single AON register it is slightly faster to do a single read, modify the bit fields, -//! and then write it back rather than doing multiple independent read-modify-writes (due to the read delay). -//! - Using posted/buffered writes to AON (default) lets the system CPU continue execution immediately. Using non-posted/non-buffered -//! writes will generate a delay similar to a read access. -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h deleted file mode 100644 index 6efc1c67a06..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/group_aux_doc.h +++ /dev/null @@ -1,58 +0,0 @@ -/****************************************************************************** -* Filename: group_aux_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup aux_group -//! @{ -//! \section sec_aux Introduction -//! -//! The AUX is a collective description of all the analog peripherals (ADC, comparators, and current source) and -//! the digital modules in the AUX power domain (AUX_PD) such as the sensor controller, timers, time-to-digital -//! converter, etc. AUX_PD is located within the AON voltage domain of the device. -//! -//! The sensor controller has the ability to -//! do its own power and clock management of AUX_PD, independently of the MCU domain. The sensor -//! controller can also continue doing tasks while the MCU subsystem is powered down, but with limited -//! resources compared to the larger MCU domain. -//! -//! The AUX power domain is connected to the MCU system through an asynchronous interface, ensuring -//! that all modules connected to the AUX bus are accessible from the system CPU. -//! Accessing the analog peripherals from the system CPU must be done by using TI-provided -//! drivers to ensure proper control of power management. -//! -//! \note To ease development of program code running on the sensor controller, TI provides a tool -//! chain for writing software for the controller, Sensor Controller Studio (SCS), which is a fully -//! integrated tool consisting of an IDE, compiler, assembler, and linker. -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.c deleted file mode 100644 index 0d254fbd778..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.c +++ /dev/null @@ -1,172 +0,0 @@ -/****************************************************************************** -* Filename: i2c.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for the I2C module -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "i2c.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef I2CMasterInitExpClk - #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk - #undef I2CMasterErr - #define I2CMasterErr NOROM_I2CMasterErr - #undef I2CIntRegister - #define I2CIntRegister NOROM_I2CIntRegister - #undef I2CIntUnregister - #define I2CIntUnregister NOROM_I2CIntUnregister -#endif - -//***************************************************************************** -// -// Initializes the I2C Master block -// -//***************************************************************************** -void -I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, - bool bFast) -{ - uint32_t ui32SCLFreq; - uint32_t ui32TPR; - - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Must enable the device before doing anything else. - I2CMasterEnable(I2C0_BASE); - - // Get the desired SCL speed. - if(bFast == true) - { - ui32SCLFreq = 400000; - } - else - { - ui32SCLFreq = 100000; - } - - // Compute the clock divider that achieves the fastest speed less than or - // equal to the desired speed. The numerator is biased to favor a larger - // clock divider so that the resulting clock is always less than or equal - // to the desired clock, never greater. - ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / (2 * 10 * ui32SCLFreq)) - 1; - HWREG(I2C0_BASE + I2C_O_MTPR) = ui32TPR; -} - -//***************************************************************************** -// -// Gets the error status of the I2C Master module -// -//***************************************************************************** -uint32_t -I2CMasterErr(uint32_t ui32Base) -{ - uint32_t ui32Err; - - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Get the raw error state. - ui32Err = HWREG(I2C0_BASE + I2C_O_MSTAT); - - // If the I2C master is busy, then all the other status bits are invalid, - // and there is no error to report. - if(ui32Err & I2C_MSTAT_BUSY) - { - return(I2C_MASTER_ERR_NONE); - } - - // Check for errors. - if(ui32Err & (I2C_MSTAT_ERR | I2C_MSTAT_ARBLST)) - { - return(ui32Err & (I2C_MSTAT_ARBLST | I2C_MSTAT_DATACK_N | I2C_MSTAT_ADRACK_N)); - } - else - { - return(I2C_MASTER_ERR_NONE); - } -} - -//***************************************************************************** -// -// Registers an interrupt handler for the I2C module -// -//***************************************************************************** -void -I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Get the interrupt number. - ui32Int = INT_I2C_IRQ; - - // Register the interrupt handler, returning an error if an error occurs. - IntRegister(ui32Int, pfnHandler); - - // Enable the I2C interrupt. - IntEnable(ui32Int); -} - -//***************************************************************************** -// -// Unregisters an interrupt handler for the I2C module -// -//***************************************************************************** -void -I2CIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Get the interrupt number. - ui32Int = INT_I2C_IRQ; - - // Disable the interrupt. - IntDisable(ui32Int); - - // Unregister the interrupt handler. - IntUnregister(ui32Int); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h deleted file mode 100644 index 4ef0930f809..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c.h +++ /dev/null @@ -1,974 +0,0 @@ -/****************************************************************************** -* Filename: i2c.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the I2C. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup i2c_api -//! @{ -// -//***************************************************************************** - -#ifndef __I2C_H__ -#define __I2C_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_i2c.h" -#include "../inc/hw_sysctl.h" -#include "debug.h" -#include "interrupt.h" -#include "cpu.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define I2CMasterInitExpClk NOROM_I2CMasterInitExpClk - #define I2CMasterErr NOROM_I2CMasterErr - #define I2CIntRegister NOROM_I2CIntRegister - #define I2CIntUnregister NOROM_I2CIntUnregister -#endif - -//***************************************************************************** -// -// I2C Master commands -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - 0x00000007 -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - 0x00000007 -#define I2C_MASTER_CMD_BURST_SEND_START \ - 0x00000003 -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - 0x00000001 -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - 0x00000005 -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - 0x0000000b -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - 0x00000009 -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - 0x00000005 -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - 0x00000004 - -//***************************************************************************** -// -// I2C Master error status -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data -#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte - -//***************************************************************************** -// -// I2C Slave interrupts -// -//***************************************************************************** -#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt. -#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt. -#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt. - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! -//! \brief Checks an I2C base address. -//! -//! This function determines if a I2C port base address is valid. -//! -//! \param ui32Base is the base address of the I2C port. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise -// -//***************************************************************************** -static bool -I2CBaseValid(uint32_t ui32Base) -{ - return(ui32Base == I2C0_BASE); -} -#endif - -//***************************************************************************** -// -//! \brief Initializes the I2C Master block. -//! -//! This function initializes operation of the I2C Master block. Upon -//! successful initialization of the I2C block, this function will have set the -//! bus speed for the master, and will have enabled the I2C Master block. -//! -//! If the parameter \c bFast is \c true, then the master block will be set up -//! to transfer data at 400 kbps; otherwise, it will be set up to transfer data -//! at 100 kbps. -//! -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32I2CClk is the rate of the clock supplied to the I2C module. -//! \param bFast set up for fast data transfers. -//! -//! \return None -// -//***************************************************************************** -extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, - bool bFast); - -//***************************************************************************** -// -//! \brief Controls the state of the I2C Master module. -//! -//! This function is used to control the state of the Master module send and -//! receive operations. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32Cmd is the command to be issued by the I2C Master module -//! The parameter can be one of the following values: -//! - \ref I2C_MASTER_CMD_SINGLE_SEND -//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE -//! - \ref I2C_MASTER_CMD_BURST_SEND_START -//! - \ref I2C_MASTER_CMD_BURST_SEND_CONT -//! - \ref I2C_MASTER_CMD_BURST_SEND_FINISH -//! - \ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP -//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START -//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT -//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH -//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || - // (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || -> Equal to SINGLE_SEND - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP)); - - // Send the command. - HWREG(I2C0_BASE + I2C_O_MCTRL) = ui32Cmd; - - // Delay minimum four cycles in order to ensure that the I2C_O_MSTAT - // register has been correctly updated before function exit - CPUdelay(2); -} - -//***************************************************************************** -// -//! \brief Sets the address that the I2C Master will place on the bus. -//! -//! This function will set the address that the I2C Master will place on the -//! bus when initiating a transaction. When the \e bReceive parameter is set -//! to \b true, the address will indicate that the I2C Master is initiating a -//! read from the slave; otherwise the address will indicate that the I2C -//! Master is initiating a write to the slave. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8SlaveAddr is a 7-bit slave address -//! \param bReceive flag indicates the type of communication with the slave. -//! - \c true : I2C Master is initiating a read from the slave. -//! - \c false : I2C Master is initiating a write to the slave. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, - bool bReceive) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // Set the address of the slave with which the master will communicate. - HWREG(I2C0_BASE + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; -} - -//***************************************************************************** -// -//! \brief Enables the I2C Master block. -//! -//! This will enable operation of the I2C Master block. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CMasterEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Enable the clock for the master. - HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 1; - - // Enable the master block. - HWREG(I2C0_BASE + I2C_O_MCTRL) = I2C_MCTRL_RUN; -} - -//***************************************************************************** -// -//! \brief Disables the I2C master block. -//! -//! This will disable operation of the I2C master block. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CMasterDisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Disable the master block. - HWREG(I2C0_BASE + I2C_O_MCTRL) = 0; - - // Disable the clock for the master. - HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_MFE_BITN) = 0; -} - -//***************************************************************************** -// -//! \brief Indicates whether or not the I2C Master is busy. -//! -//! This function returns an indication of whether or not the I2C Master is -//! busy transmitting or receiving data. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! \return Returns status of I2C Master: -//! - \c true : I2C Master is busy. -//! - \c false : I2C Master is not busy. -// -//***************************************************************************** -__STATIC_INLINE bool -I2CMasterBusy(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Return the busy status. - if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSY) - { - return(true); - } - else - { - return(false); - } -} - -//***************************************************************************** -// -//! \brief Indicates whether or not the I2C bus is busy. -//! -//! This function returns an indication of whether or not the I2C bus is busy. -//! This function can be used in a multi-master environment to determine if -//! another master is currently using the bus. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! \return Returns status of the I2C bus: -//! - \c true : I2C bus is busy. -//! - \c false : I2C bus is not busy. -// -//***************************************************************************** -__STATIC_INLINE bool -I2CMasterBusBusy(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Return the bus busy status. - if(HWREG(I2C0_BASE + I2C_O_MSTAT) & I2C_MSTAT_BUSBSY) - { - return(true); - } - else - { - return(false); - } -} - -//***************************************************************************** -// -//! \brief Receives a byte that has been sent to the I2C Master. -//! -//! This function reads a byte of data from the I2C Master Data Register. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! \return Returns the byte received from by the I2C Master, cast as an -//! uint32_t. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -I2CMasterDataGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Read a byte. - return(HWREG(I2C0_BASE + I2C_O_MDR)); -} - -//***************************************************************************** -// -//! \brief Transmits a byte from the I2C Master. -//! -//! This function will place the supplied data into I2C Master Data Register. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui8Data is the data to be transmitted by the I2C Master -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Write the byte. - HWREG(I2C0_BASE + I2C_O_MDR) = ui8Data; -} - -//***************************************************************************** -// -//! \brief Gets the error status of the I2C Master module. -//! -//! This function is used to obtain the error status of the Master module send -//! and receive operations. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! \return Returns the error status of the Master module: -//! - \ref I2C_MASTER_ERR_NONE -//! - \ref I2C_MASTER_ERR_ADDR_ACK -//! - \ref I2C_MASTER_ERR_DATA_ACK -//! - \ref I2C_MASTER_ERR_ARB_LOST -// -//***************************************************************************** -extern uint32_t I2CMasterErr(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Enables the I2C Master interrupt. -//! -//! Enables the I2C Master interrupt source. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CMasterIntEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Enable the master interrupt. - HWREG(I2C0_BASE + I2C_O_MIMR) = I2C_MIMR_IM; -} - -//***************************************************************************** -// -//! \brief Disables the I2C Master interrupt. -//! -//! Disables the I2C Master interrupt source. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CMasterIntDisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Disable the master interrupt. - HWREG(I2C0_BASE + I2C_O_MIMR) = 0; -} - -//***************************************************************************** -// -//! \brief Clears I2C Master interrupt sources. -//! -//! The I2C Master interrupt source is cleared, so that it no longer asserts. -//! This must be done in the interrupt handler to keep it from being called -//! again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CMasterIntClear(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Clear the I2C master interrupt source. - HWREG(I2C0_BASE + I2C_O_MICR) = I2C_MICR_IC; -} - -//***************************************************************************** -// -//! \brief Gets the current I2C Master interrupt status. -//! -//! This returns the interrupt status for the I2C Master module. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param bMasked selects either raw or masked interrupt status. -//! - \c false : Raw interrupt status is requested. -//! - \c true : Masked interrupt status is requested. -//! -//! \return Returns the current interrupt status. -//! - \c true : Active. -//! - \c false : Not active. -// -//***************************************************************************** -__STATIC_INLINE bool -I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Return either the interrupt status or the raw interrupt status as - // requested. - if(bMasked) - { - return((HWREG(I2C0_BASE + I2C_O_MMIS)) ? true : false); - } - else - { - return((HWREG(I2C0_BASE + I2C_O_MRIS)) ? true : false); - } -} - -//***************************************************************************** -// -//! \brief Enables the I2C Slave block. -//! -//! This will enable operation of the I2C Slave block. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CSlaveEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Enable the clock to the slave block. - HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 1; - - // Enable the slave. - HWREG(I2C0_BASE + I2C_O_SCTL) = I2C_SCTL_DA; -} - -//***************************************************************************** -// -//! \brief Initializes the I2C Slave block. -//! -//! This function initializes operation of the I2C Slave block. Upon -//! successful initialization of the I2C blocks, this function will have set -//! the slave address and have enabled the I2C Slave block. -//! -//! The parameter \c ui8SlaveAddr is the value that will be compared against the -//! slave address sent by an I2C master. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui8SlaveAddr is the 7-bit slave address. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // Must enable the device before doing anything else. - I2CSlaveEnable(I2C0_BASE); - - // Set up the slave address. - HWREG(I2C0_BASE + I2C_O_SOAR) = ui8SlaveAddr; -} - -//***************************************************************************** -// -//! \brief Sets the I2C slave address. -//! -//! This function writes the specified slave address. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui8SlaveAddr is the 7-bit slave address -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8SlaveAddr) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // Set up the primary slave address. - HWREG(I2C0_BASE + I2C_O_SOAR) = ui8SlaveAddr; -} - -//***************************************************************************** -// -//! \brief Disables the I2C slave block. -//! -//! This will disable operation of the I2C slave block. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CSlaveDisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Disable the slave. - HWREG(I2C0_BASE + I2C_O_SCTL) = 0x0; - - // Disable the clock to the slave block. - HWREGBITW(I2C0_BASE + I2C_O_MCR, I2C_MCR_SFE_BITN) = 0; -} - -//***************************************************************************** -// -//! \brief Gets the I2C Slave module status. -//! -//! This function will return the action requested from a master, if any. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! \return Returns the status of the I2C Slave module: -//! - \ref I2C_SLAVE_ACT_NONE : No action has been requested of the I2C Slave module. -//! - \ref I2C_SLAVE_ACT_RREQ : An I2C master has sent data to the I2C Slave module. -//! - \ref I2C_SLAVE_ACT_TREQ : An I2C master has requested that the I2C Slave module send data. -//! - \ref I2C_SLAVE_ACT_RREQ_FBR : An I2C master has sent data to the I2C slave -//! and the first byte following the slave's own address has been received. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -I2CSlaveStatus(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Return the slave status. - return(HWREG(I2C0_BASE + I2C_O_SSTAT)); -} - -//***************************************************************************** -// -//! \brief Receives a byte that has been sent to the I2C Slave. -//! -//! This function reads a byte of data from the I2C Slave Data Register. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! \return Returns the byte received from by the I2C Slave, cast as an -//! uint32_t. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -I2CSlaveDataGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Read a byte. - return(HWREG(I2C0_BASE + I2C_O_SDR)); -} - -//***************************************************************************** -// -//! \brief Transmits a byte from the I2C Slave. -//! -//! This function will place the supplied data into I2C Slave Data Register. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui8Data data to be transmitted from the I2C Slave. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Write the byte. - HWREG(I2C0_BASE + I2C_O_SDR) = ui8Data; -} - -//***************************************************************************** -// -//! \brief Enables individual I2C Slave interrupt sources. -//! -//! Enables the indicated I2C Slave interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is the bit mask of the slave interrupt sources to be enabled. -//! The parameter is the bitwise OR of any of the following: -//! - \ref I2C_SLAVE_INT_STOP -//! - \ref I2C_SLAVE_INT_START -//! - \ref I2C_SLAVE_INT_DATA -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CSlaveIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - uint32_t ui32Val; - - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START | - I2C_SLAVE_INT_DATA)); - - // Enable the slave interrupt. - ui32Val = HWREG(I2C0_BASE + I2C_O_SIMR); - ui32Val |= ui32IntFlags; - HWREG(I2C0_BASE + I2C_O_SIMR) = ui32Val; -} - -//***************************************************************************** -// -//! \brief Disables individual I2C Slave interrupt sources. -//! -//! Disables the indicated I2C Slave interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. -//! The parameter is the bitwise OR of any of the following: -//! - \ref I2C_SLAVE_INT_STOP -//! - \ref I2C_SLAVE_INT_START -//! - \ref I2C_SLAVE_INT_DATA -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CSlaveIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - uint32_t ui32Val; - - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - ASSERT(ui32IntFlags & (I2C_SLAVE_INT_STOP | I2C_SLAVE_INT_START | - I2C_SLAVE_INT_DATA)); - - // Disable the slave interrupt. - ui32Val = HWREG(I2C0_BASE + I2C_O_SIMR); - ui32Val &= ~ui32IntFlags; - HWREG(I2C0_BASE + I2C_O_SIMR) = ui32Val; -} - -//***************************************************************************** -// -//! \brief Clears I2C Slave interrupt sources. -//! -//! The specified I2C Slave interrupt sources are cleared, so that they no -//! longer assert. This must be done in the interrupt handler to keep it from -//! being called again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32Base is the base address of the I2C module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! The parameter is the bitwise OR of any of the following: -//! - \ref I2C_SLAVE_INT_STOP -//! - \ref I2C_SLAVE_INT_START -//! - \ref I2C_SLAVE_INT_DATA -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2CSlaveIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Clear the I2C slave interrupt source. - HWREG(I2C0_BASE + I2C_O_SICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Gets the current I2C Slave interrupt status. -//! -//! This returns the interrupt status for the I2C Slave module. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param bMasked selects either raw or masked interrupt status. -//! - \c false : Raw interrupt status is requested. -//! - \c true : Masked interrupt status is requested. -//! -//! \return Returns the current interrupt status as an OR'ed combination of: -//! - \ref I2C_SLAVE_INT_STOP -//! - \ref I2C_SLAVE_INT_START -//! - \ref I2C_SLAVE_INT_DATA -// -//***************************************************************************** -__STATIC_INLINE uint32_t -I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) -{ - // Check the arguments. - ASSERT(I2CBaseValid(ui32Base)); - - // Return either the interrupt status or the raw interrupt status as - // requested. - if(bMasked) - { - return(HWREG(I2C0_BASE + I2C_O_SMIS)); - } - else - { - return(HWREG(I2C0_BASE + I2C_O_SRIS)); - } -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for the I2C module in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific I2C interrupts must be enabled via \ref I2CMasterIntEnable() and -//! \ref I2CSlaveIntEnable(). If necessary, it is the interrupt handler's -//! responsibility to clear the interrupt source via \ref I2CMasterIntClear() and -//! \ref I2CSlaveIntClear(). -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param pfnHandler is a pointer to the function to be called when the -//! I2C interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for the I2C module in the dynamic interrupt table. -//! -//! This function will clear the handler to be called when an I2C interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler no longer is called. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! \return None -//! -//! \sa \brief IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void I2CIntUnregister(uint32_t ui32Base); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_I2CMasterInitExpClk - #undef I2CMasterInitExpClk - #define I2CMasterInitExpClk ROM_I2CMasterInitExpClk - #endif - #ifdef ROM_I2CMasterErr - #undef I2CMasterErr - #define I2CMasterErr ROM_I2CMasterErr - #endif - #ifdef ROM_I2CIntRegister - #undef I2CIntRegister - #define I2CIntRegister ROM_I2CIntRegister - #endif - #ifdef ROM_I2CIntUnregister - #undef I2CIntUnregister - #define I2CIntUnregister ROM_I2CIntUnregister - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __I2C_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h deleted file mode 100644 index 05298e00832..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2c_doc.h +++ /dev/null @@ -1,162 +0,0 @@ -/****************************************************************************** -* Filename: i2c_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup i2c_api -//! @{ -//! \section sec_i2c Introduction -//! -//! The Inter-Integrated Circuit (\i2c) API provides a set of functions for using -//! the \ti_device \i2c master and slave module. Functions are provided to perform -//! the following actions: -//! - Initialize the \i2c module. -//! - Send and receive data. -//! - Obtain status. -//! - Manage interrupts for the \i2c module. -//! -//! The \i2c master and slave module provide the ability to communicate to other IC -//! devices over an \i2c bus. The \i2c bus is specified to support devices that can -//! both transmit and receive (write and read) data. Also, devices on the \i2c bus -//! can be designated as either a master or a slave. The \ti_device \i2c module -//! supports both sending and receiving data as either a master or a slave, and also -//! support the simultaneous operation as both a master and a slave. Finally, the -//! \ti_device \i2c module can operate at two speeds: standard (100 kb/s) and fast -//! (400 kb/s). -//! -//! The master and slave \i2c module can generate interrupts. The \i2c master -//! module generates interrupts when a transmit or receive operation -//! completes (or aborts due to an error). -//! The \i2c slave module can generate interrupts when data is -//! sent or requested by a master and when a START or STOP condition is present. -//! -//! \section sec_i2c_master Master Operations -//! -//! When using this API to drive the \i2c master module, the user must first -//! initialize the \i2c master module with a call to \ref I2CMasterInitExpClk(). This -//! function sets the bus speed and enables the master module. -//! -//! The user may transmit or receive data after the successful initialization of -//! the \i2c master module. Data is transferred by first setting the slave address -//! using \ref I2CMasterSlaveAddrSet(). This function is also used to define whether -//! the transfer is a send (a write to the slave from the master) or a receive (a -//! read from the slave by the master). Then, if connected to an \i2c bus that has -//! multiple masters, the \ti_device \i2c master must first call \ref I2CMasterBusBusy() -//! before trying to initiate the desired transaction. After determining that -//! the bus is not busy, if trying to send data, the user must call the -//! \ref I2CMasterDataPut() function. The transaction can then be initiated on the bus -//! by calling the \ref I2CMasterControl() function with any of the following commands: -//! - \ref I2C_MASTER_CMD_SINGLE_SEND -//! - \ref I2C_MASTER_CMD_SINGLE_RECEIVE -//! - \ref I2C_MASTER_CMD_BURST_SEND_START -//! - \ref I2C_MASTER_CMD_BURST_RECEIVE_START -//! -//! Any of these commands result in the master arbitrating for the bus, -//! driving the start sequence onto the bus, and sending the slave address and -//! direction bit across the bus. The remainder of the transaction can then be -//! driven using either a polling or interrupt-driven method. -//! -//! For the single send and receive cases, the polling method involves looping -//! on the return from \ref I2CMasterBusy(). Once the function indicates that the \i2c -//! master is no longer busy, the bus transaction is complete and can be -//! checked for errors using \ref I2CMasterErr(). If there are no errors, then the data -//! has been sent or is ready to be read using \ref I2CMasterDataGet(). For the burst -//! send and receive cases, the polling method also involves calling the -//! \ref I2CMasterControl() function for each byte transmitted or received -//! (using either the \ref I2C_MASTER_CMD_BURST_SEND_CONT or \ref I2C_MASTER_CMD_BURST_RECEIVE_CONT -//! commands), and for the last byte sent or received (using either the -//! \ref I2C_MASTER_CMD_BURST_SEND_FINISH or \ref I2C_MASTER_CMD_BURST_RECEIVE_FINISH -//! commands). -//! -//! If any error is detected during the burst transfer, -//! the appropriate stop command (\ref I2C_MASTER_CMD_BURST_SEND_ERROR_STOP or -//! \ref I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) should be used to call the -//! \ref I2CMasterControl() function. -//! -//! For the interrupt-driven transaction, the user must register an interrupt -//! handler for the \i2c devices and enable the \i2c master interrupt; the interrupt -//! occurs when the master is no longer busy. -//! -//! \section sec_i2c_slave Slave Operations -//! -//! When using this API to drive the \i2c slave module, the user must first -//! initialize the \i2c slave module with a call to \ref I2CSlaveInit(). This function -//! enables the \i2c slave module and initializes the address of the slave. After the -//! initialization completes, the user may poll the slave status using -//! \ref I2CSlaveStatus() to determine if a master requested a send or receive -//! operation. Depending on the type of operation requested, the user can call -//! \ref I2CSlaveDataPut() or \ref I2CSlaveDataGet() to complete the transaction. -//! Alternatively, the \i2c slave can handle transactions using an interrupt handler -//! registered with \ref I2CIntRegister(), and by enabling the \i2c slave interrupt. -//! -//! \section sec_i2c_api API -//! -//! The \i2c API is broken into three groups of functions: -//! those that handle status and initialization, those that -//! deal with sending and receiving data, and those that deal with -//! interrupts. -//! -//! Status and initialization functions for the \i2c module are: -//! - \ref I2CMasterInitExpClk() -//! - \ref I2CMasterEnable() -//! - \ref I2CMasterDisable() -//! - \ref I2CMasterBusBusy() -//! - \ref I2CMasterBusy() -//! - \ref I2CMasterErr() -//! - \ref I2CSlaveInit() -//! - \ref I2CSlaveEnable() -//! - \ref I2CSlaveDisable() -//! - \ref I2CSlaveStatus() -//! -//! Sending and receiving data from the \i2c module is handled by the following functions: -//! - \ref I2CMasterSlaveAddrSet() -//! - \ref I2CSlaveAddressSet() -//! - \ref I2CMasterControl() -//! - \ref I2CMasterDataGet() -//! - \ref I2CMasterDataPut() -//! - \ref I2CSlaveDataGet() -//! - \ref I2CSlaveDataPut() -//! -//! The \i2c master and slave interrupts are handled by the following functions: -//! - \ref I2CIntRegister() -//! - \ref I2CIntUnregister() -//! - \ref I2CMasterIntEnable() -//! - \ref I2CMasterIntDisable() -//! - \ref I2CMasterIntClear() -//! - \ref I2CMasterIntStatus() -//! - \ref I2CSlaveIntEnable() -//! - \ref I2CSlaveIntDisable() -//! - \ref I2CSlaveIntClear() -//! - \ref I2CSlaveIntStatus() -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.c deleted file mode 100644 index b8b38a0b710..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.c +++ /dev/null @@ -1,349 +0,0 @@ -/****************************************************************************** -* Filename: i2s.c -* Revised: 2017-05-08 12:18:04 +0200 (Mon, 08 May 2017) -* Revision: 48924 -* -* Description: Driver for the I2S. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "i2s.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef I2SEnable - #define I2SEnable NOROM_I2SEnable - #undef I2SAudioFormatConfigure - #define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure - #undef I2SChannelConfigure - #define I2SChannelConfigure NOROM_I2SChannelConfigure - #undef I2SBufferConfig - #define I2SBufferConfig NOROM_I2SBufferConfig - #undef I2SPointerUpdate - #define I2SPointerUpdate NOROM_I2SPointerUpdate - #undef I2SPointerSet - #define I2SPointerSet NOROM_I2SPointerSet - #undef I2SSampleStampConfigure - #define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure - #undef I2SSampleStampGet - #define I2SSampleStampGet NOROM_I2SSampleStampGet -#endif - -//***************************************************************************** -// -// Global pointer to the current I2S data structure -// -//***************************************************************************** -I2SControlTable *g_pControlTable; - -//***************************************************************************** -// -// Enables the I2S module for operation -// -//***************************************************************************** -void -I2SEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Make sure the control table pointer is setup to a memory location. - if(!(g_pControlTable)) - { - return; - } - - // Write the address to the first input/output buffer. - HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InBase; - g_pControlTable->ui32InOffset = 0; - HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = g_pControlTable->ui32OutBase; - g_pControlTable->ui32OutOffset = 0; - - // Enable the I2S module. - HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = (uint32_t)g_pControlTable->ui16DMABufSize - 1; -} - -//***************************************************************************** -// -// Configures the I2S module -// -//***************************************************************************** -void -I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg, - uint32_t ui32BitClkDelay) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - ASSERT(ui32BitClkDelay <= 255); - - // Save the length of the audio words stored in memory. - g_pControlTable->ui16MemLen = (ui32FmtCfg & I2S_MEM_LENGTH_24) ? 24 : 16; - - // Write the configuration. - HWREG(I2S0_BASE + I2S_O_AIFFMTCFG) = ui32FmtCfg | (ui32BitClkDelay << I2S_AIFFMTCFG_DATA_DELAY_S); -} - -//**************************************************************************** -// -// Setup the audio channel configuration -// -//**************************************************************************** -void -I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg, - uint32_t ui32Chan1Cfg) -{ - uint32_t ui32InChan; - uint32_t ui32OutChan; - uint32_t ui32ChanMask; - - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - ASSERT(ui32Chan0Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK)) - ASSERT(ui32Chan1Cfg & (I2S_CHAN_CFG_MASK | I2S_LINE_MASK)) - - ui32InChan = 0; - ui32OutChan = 0; - - // Configure input/output channels. - HWREG(I2S0_BASE + I2S_O_AIFDIRCFG) = ( - (( ui32Chan0Cfg << I2S_AIFDIRCFG_AD0_S) & I2S_AIFDIRCFG_AD0_M ) | - (( ui32Chan1Cfg << I2S_AIFDIRCFG_AD1_S) & I2S_AIFDIRCFG_AD1_M ) ); - - // Configure the valid channel mask. - HWREG(I2S0_BASE + I2S_O_AIFWMASK0) = (ui32Chan0Cfg >> 8) & I2S_AIFWMASK0_MASK_M; - HWREG(I2S0_BASE + I2S_O_AIFWMASK1) = (ui32Chan1Cfg >> 8) & I2S_AIFWMASK1_MASK_M; - - // Resolve and save the number of input and output channels. - ui32ChanMask = (ui32Chan0Cfg & I2S_CHAN_CFG_MASK) >> 8; - if(ui32Chan0Cfg & I2S_LINE_INPUT) - { - while(ui32ChanMask) - { - if(ui32ChanMask & 0x1) - { - ui32InChan++; - } - // Shift down channel mask - ui32ChanMask >>= 1; - } - - } - else if(ui32Chan0Cfg & I2S_LINE_OUTPUT) - { - while(ui32ChanMask) - { - if(ui32ChanMask & 0x1) - { - ui32OutChan++; - } - // Shift down channel mask - ui32ChanMask >>= 1; - } - } - - ui32ChanMask = (ui32Chan1Cfg & I2S_CHAN_CFG_MASK) >> 8; - if(ui32Chan1Cfg & I2S_LINE_INPUT) - { - while(ui32ChanMask) - { - if(ui32ChanMask & 0x1) - { - ui32InChan++; - } - // Shift down channel mask - ui32ChanMask >>= 1; - } - } - else if(ui32Chan1Cfg & I2S_LINE_OUTPUT) - { - while(ui32ChanMask) - { - if(ui32ChanMask & 0x1) - { - ui32OutChan++; - } - // Shift down channel mask - ui32ChanMask >>= 1; - } - } - - g_pControlTable->ui8InChan = (uint8_t)ui32InChan; - g_pControlTable->ui8OutChan = (uint8_t)ui32OutChan; -} - -//**************************************************************************** -// -// Set the input buffer pointers -// -//**************************************************************************** -void -I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase, - uint32_t ui32OutBufBase, uint16_t ui16DMABufSize, - uint16_t ui16ChanBufSize) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - ASSERT(ui16DMABufSize > 0); - - // Setup the input data pointer and buffer sizes. - g_pControlTable->ui16DMABufSize = ui16DMABufSize; - g_pControlTable->ui16ChBufSize = ui16ChanBufSize; - g_pControlTable->ui32InBase = ui32InBufBase; - g_pControlTable->ui32OutBase = ui32OutBufBase; -} - -//**************************************************************************** -// -// Set the buffer pointers -// -//**************************************************************************** -void -I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Update the next input/output pointer with the correct address. - if(bInput == true) - { - HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = (uint32_t)pNextPointer; - } - else - { - HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = (uint32_t)pNextPointer; - } -} - -//**************************************************************************** -// -// Update the buffer pointers -// -//**************************************************************************** -void -I2SPointerUpdate(uint32_t ui32Base, bool bInput) -{ - uint32_t ui32NextPtr; - - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Update the next input/output pointer with the correct address. - if(bInput == true) - { - ui32NextPtr = (g_pControlTable->ui8InChan * - (g_pControlTable->ui16MemLen >> 3)) * - g_pControlTable->ui16DMABufSize; - g_pControlTable->ui32InOffset = ((g_pControlTable->ui32InOffset + - ui32NextPtr) % - g_pControlTable->ui16ChBufSize); - HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = g_pControlTable->ui32InOffset + - g_pControlTable->ui32InBase; - } - else - { - ui32NextPtr = (g_pControlTable->ui8OutChan * - (g_pControlTable->ui16MemLen >> 3)) * - g_pControlTable->ui16DMABufSize; - g_pControlTable->ui32OutOffset = ((g_pControlTable->ui32OutOffset + - ui32NextPtr) % - g_pControlTable->ui16ChBufSize); - HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = - g_pControlTable->ui32OutOffset + - g_pControlTable->ui32OutBase; - } -} - -//***************************************************************************** -// -// Configure the sample stamp generator -// -//***************************************************************************** -void -I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, bool bOutput) -{ - uint32_t ui32Trigger; - - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - ui32Trigger = HWREG(I2S0_BASE + I2S_O_STMPWCNT); - ui32Trigger = (ui32Trigger + 2) % g_pControlTable->ui16ChBufSize; - - // Setup the sample stamp trigger for input streams. - if(bInput) - { - HWREG(I2S0_BASE + I2S_O_STMPINTRIG) = ui32Trigger; - } - - // Setup the sample stamp trigger for output streams. - if(bOutput) - { - HWREG(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui32Trigger; - } - -} - -//***************************************************************************** -// -// Get the current value of a sample stamp counter -// -//***************************************************************************** -uint32_t -I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel) -{ - uint32_t ui32FrameClkCnt; - uint32_t ui32SysClkCnt; - uint32_t ui32PeriodSysClkCnt; - uint32_t ui32SampleStamp; - - // Get the number of Frame clock counts since last stamp. - ui32FrameClkCnt = HWREG(I2S0_BASE + I2S_O_STMPWCNTCAPT0); - - // Get the number of system clock ticks since last frame clock edge. - ui32SysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXCNTCAPT0); - - // Get the number system clock ticks in the last frame clock period. - ui32PeriodSysClkCnt = HWREG(I2S0_BASE + I2S_O_STMPXPER); - - // Calculate the sample stamp. - ui32SampleStamp = (ui32SysClkCnt << 16) / ui32PeriodSysClkCnt; - ui32SampleStamp = (ui32SampleStamp > I2S_STMP_SATURATION) ? - I2S_STMP_SATURATION : ui32SampleStamp; - ui32SampleStamp |= (ui32FrameClkCnt << 16); - - return (ui32SampleStamp); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h deleted file mode 100644 index 62c2c5ef3aa..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s.h +++ /dev/null @@ -1,1359 +0,0 @@ -/****************************************************************************** -* Filename: i2s.h -* Revised: 2018-11-16 11:16:53 +0100 (Fri, 16 Nov 2018) -* Revision: 53356 -* -* Description: Defines and prototypes for the I2S. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//**************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup i2s_api -//! @{ -// -//**************************************************************************** - -#ifndef __I2S_H__ -#define __I2S_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_i2s.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define I2SEnable NOROM_I2SEnable - #define I2SAudioFormatConfigure NOROM_I2SAudioFormatConfigure - #define I2SChannelConfigure NOROM_I2SChannelConfigure - #define I2SBufferConfig NOROM_I2SBufferConfig - #define I2SPointerUpdate NOROM_I2SPointerUpdate - #define I2SPointerSet NOROM_I2SPointerSet - #define I2SSampleStampConfigure NOROM_I2SSampleStampConfigure - #define I2SSampleStampGet NOROM_I2SSampleStampGet -#endif - -//***************************************************************************** -// -//! \brief A structure that defines an audio control table. Note: Memory for this -//! structure \b must be initialized by user application. See detailed description! -//! -//! \deprecated This structure will be removed in a future release. -//! -//! These fields are used by the I2S and normally it is not necessary for -//! software to directly read or write fields in the table. -//! -//! \note The control table must be defined by the user as a global variable and -//! the global pointer must then be assigned the address of the control table -//! inside a user function (but before calling any I2S-function). -//! -/*! -\verbatim - I2SControlTable g_controlTable; // Define global - g_pControlTable = &g_controlTable; // Assign pointer (inside a function) -\endverbatim -*/ -//! -// -//***************************************************************************** -#ifndef DEPRECATED -typedef struct -{ - uint16_t ui16DMABufSize; //!< Size of DMA buffer in number of samples. - uint16_t ui16ChBufSize; //!< Size of Channel buffer. - uint8_t ui8InChan; //!< Input Channel. - uint8_t ui8OutChan; //!< Output Channel. - uint16_t ui16MemLen; //!< Length of the audio words stored in memory. - uint32_t ui32InBase; //!< Base address of the input buffer. - uint32_t ui32InOffset; //!< Value of the current input pointer offset. - uint32_t ui32OutBase; //!< Base address of the output buffer. - uint32_t ui32OutOffset; //!< Value of the current output pointer offset. -} I2SControlTable; -#endif - -//***************************************************************************** -// -// Declare global pointer to the I2S data structure. -// -// The control table must be defined by the user as a global variable and the -// global pointer must then be assigned the address of the control table: -// -// I2SControlTable g_controlTable; -// g_pControlTable = &g_controlTable; -// -//***************************************************************************** -#ifndef DEPRECATED -extern I2SControlTable *g_pControlTable; -#endif - -//***************************************************************************** -// -// Defines for the I2S DMA buffer sizes -// -//***************************************************************************** -#ifndef DEPRECATED -#define I2S_DMA_BUF_SIZE_64 0x00000040 -#define I2S_DMA_BUF_SIZE_128 0x00000080 -#define I2S_DMA_BUF_SIZE_256 0x00000100 -#endif - -//***************************************************************************** -// -// Defines for the I2S audio clock configuration -// -//***************************************************************************** -#ifndef DEPRECATED -#define I2S_EXT_WCLK 0x00000001 -#define I2S_INT_WCLK 0x00000002 -#define I2S_INVERT_WCLK 0x00000004 -#define I2S_NORMAL_WCLK 0x00000000 -#endif - -//***************************************************************************** -// -// Defines for the audio data line input/output configuration -// -//***************************************************************************** -#ifndef DEPRECATED -#define I2S_LINE_UNUSED 0x00000000 -#define I2S_LINE_INPUT 0x00000001 -#define I2S_LINE_OUTPUT 0x00000002 -#define I2S_LINE_MASK 0x00000003 -#endif - -//***************************************************************************** -// -// Defines for activating an audio channel. -// -//***************************************************************************** -#ifndef DEPRECATED -#define I2S_CHAN0_ACT 0x00000100 -#define I2S_CHAN1_ACT 0x00000200 -#define I2S_CHAN2_ACT 0x00000400 -#define I2S_CHAN3_ACT 0x00000800 -#define I2S_CHAN4_ACT 0x00001000 -#define I2S_CHAN5_ACT 0x00002000 -#define I2S_CHAN6_ACT 0x00004000 -#define I2S_CHAN7_ACT 0x00008000 -#define I2S_MONO_MODE 0x00000100 -#define I2S_STEREO_MODE 0x00000300 -#define I2S_CHAN_CFG_MASK 0x0000FF00 -#endif - -#define I2S_CHAN0_MASK 0x00000001 -#define I2S_CHAN1_MASK 0x00000002 -#define I2S_CHAN2_MASK 0x00000004 -#define I2S_CHAN3_MASK 0x00000008 -#define I2S_CHAN4_MASK 0x00000010 -#define I2S_CHAN5_MASK 0x00000020 -#define I2S_CHAN6_MASK 0x00000040 -#define I2S_CHAN7_MASK 0x00000080 - -//***************************************************************************** -// -// Defines for the audio format configuration -// -//***************************************************************************** -#define I2S_MEM_LENGTH_16 0x00000000 // 16 bit size of word in memory -#define I2S_MEM_LENGTH_24 0x00000080 // 24 bit size of word in memory -#define I2S_POS_EDGE 0x00000040 // Sample on positive edge -#define I2S_NEG_EDGE 0x00000000 // Sample on negative edge -#define I2S_DUAL_PHASE_FMT 0x00000020 // Dual Phased audio format -#define I2S_SINGLE_PHASE_FMT 0x00000000 // Single Phased audio format -#define I2S_WORD_LENGTH_8 0x00000008 // Word length is 8 bits -#define I2S_WORD_LENGTH_16 0x00000010 // Word length is 16 bits -#define I2S_WORD_LENGTH_24 0x00000018 // Word length is 24 bits - -//***************************************************************************** -// -// Defines for the sample stamp counters -// -//***************************************************************************** -#ifndef DEPRECATED -#define I2S_STMP0 0x00000001 // Sample stamp counter channel 0 -#define I2S_STMP1 0x00000002 // Sample stamp counter channel 1 -#endif -#define I2S_STMP_SATURATION 0x0000FFFF // The saturation value used when - // calculating the sample stamp - -//***************************************************************************** -// -// Defines for the interrupt -// -//***************************************************************************** -#define I2S_INT_DMA_IN 0x00000020 // DMA output buffer full interrupt -#define I2S_INT_DMA_OUT 0x00000010 // DMA input buffer empty interrupt -#define I2S_INT_TIMEOUT 0x00000008 // Word Clock Timeout -#define I2S_INT_BUS_ERR 0x00000004 // DMA Bus error -#define I2S_INT_WCLK_ERR 0x00000002 // Word Clock error -#define I2S_INT_PTR_ERR 0x00000001 // Data pointer error (DMA data was not updated in time). -#define I2S_INT_ALL 0x0000003F // All interrupts - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! -//! \brief Checks an I2S base address. -//! -//! This function determines if an I2S port base address is valid. -//! -//! \param ui32Base is the base address of the I2S port. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -I2SBaseValid(uint32_t ui32Base) -{ - return(ui32Base == I2S0_BASE); -} -#endif - -//***************************************************************************** -// -//! \brief Enables the I2S module for operation. -//! -//! \deprecated This function will be removed in a future release. -//! -//! \note The module should only be enabled after configuration. When the -//! module is disabled, no data or clocks will be generated on the I2S signals. -//! -//! \note Immediately after enabling the module the programmer should update -//! the DMA data pointer registers using \ref I2SPointerUpdate() to ensure a new -//! pointer is written before the DMA transfer completes. Failure to update -//! the pointer in time will result in an \ref I2S_INT_PTR_ERR. -//! -//! \param ui32Base is the I2S module base address. -//! -//! \return None -// -//***************************************************************************** -#ifndef DEPRECATED -extern void I2SEnable(uint32_t ui32Base); -#endif - -//***************************************************************************** -// -//! \brief Disables the I2S module for operation. -//! -//! \deprecated This function will be removed in a future release. -//! -//! This function will immediately disable the I2S module. To ensure that -//! all buffer operations are completed before shutting down, the correct -//! procedure is: -//! 1. Do not update the data pointers using \ref I2SPointerUpdate(). -//! 2. Await next interrupt resulting in \ref I2S_INT_PTR_ERR. -//! 3. Disable the I2S using \ref I2SDisable() and clear the pointer error using -//! \ref I2SIntClear(). -//! 4. Disable bit clock source (done externally). -//! -//! \param ui32Base is the I2S module base address. -//! -//! \return None -// -//***************************************************************************** -#ifndef DEPRECATED -__STATIC_INLINE void -I2SDisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Disable the I2S module. - HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x0; -} -#endif - -//***************************************************************************** -// -//! \brief Configures the I2S module. -//! -//! \deprecated This function will be removed in a future release. -//! -//! The word length defines the size of the word transmitted on the data -//! lines. For single phased formats \c I2S_WORD_LENGTH_x is the exact number -//! of bits per word. In dual phased format this is the maximum number of bits -//! per word. The size is set using \ref I2S_WORD_LENGTH_8, -//! \ref I2S_WORD_LENGTH_16 or \ref I2S_WORD_LENGTH_24. -//! -//! \param ui32Base is the I2S module base address. -//! \param ui32FmtCfg is the bitwise OR of several options: -//! - Sample size: -//! - \ref I2S_MEM_LENGTH_16 -//! - \ref I2S_MEM_LENGTH_24 -//! - Clock edge sampling: -//! - \ref I2S_POS_EDGE -//! - \ref I2S_NEG_EDGE -//! - Phase: -//! - \ref I2S_DUAL_PHASE_FMT -//! - \ref I2S_SINGLE_PHASE_FMT -//! - Word length: -//! - \ref I2S_WORD_LENGTH_8 -//! - \ref I2S_WORD_LENGTH_16 -//! - \ref I2S_WORD_LENGTH_24 -//! \param ui32BitClkDelay defines the bit clock delay by setting the number of bit clock periods between the -//! positive word clock edge and the MSB of the first word in a phase. The bit -//! clock delay is determined by the ratio between the bit clock and the frame -//! clock and the chosen audio format. The bit clock delay \b must be configured -//! depending on the chosen audio format: -//! - 0 : Left Justified Format (LJF). -//! - 1 : I2S and DSP format. -//! - 2-255 : Right Justified format (RJF). -//! -//! \return None -//! -//! \sa \ref I2SChannelConfigure() -// -//***************************************************************************** -#ifndef DEPRECATED -extern void I2SAudioFormatConfigure(uint32_t ui32Base, uint32_t ui32FmtCfg, - uint32_t ui32BitClkDelay); -#endif - -//**************************************************************************** -// -//! \brief Setup the audio channel configuration. -//! -//! \deprecated This function will be removed in a future release. -//! -//! The channel configuration is a bitwise OR of the input/output mode of each -//! data line and the active audio channels within a specific audio frame. -//! -//! Setting up the input/output mode use one of: -//! - \ref I2S_LINE_UNUSED -//! - \ref I2S_LINE_INPUT -//! - \ref I2S_LINE_OUTPUT -//! -//! For dual phased audio (LJF,RJF,I2S) only mono and stereo modes are allowed. -//! For single phased audio format (DSP) up to 8 active channels are allowed -//! on a single data line. For setting up the active channels in a frame use: -//! - Single phased, use a bitwise OR'ed combination of: -//! - \ref I2S_CHAN0_ACT -//! - \ref I2S_CHAN1_ACT -//! - \ref I2S_CHAN2_ACT -//! - \ref I2S_CHAN3_ACT -//! - \ref I2S_CHAN4_ACT -//! - \ref I2S_CHAN5_ACT -//! - \ref I2S_CHAN6_ACT -//! - \ref I2S_CHAN7_ACT -//! - Dual phased, use one of: -//! - \ref I2S_MONO_MODE (same as \ref I2S_CHAN0_ACT) -//! - \ref I2S_STEREO_MODE (same as \ref I2S_CHAN0_ACT | \ref I2S_CHAN1_ACT) -//! -//! \note The audio format and the clock configuration should be set using -//! \ref I2SAudioFormatConfigure() -//! -//! \param ui32Base is base address of the I2S module. -//! \param ui32Chan0Cfg defines the channel configuration for data line 0. -//! \param ui32Chan1Cfg defines the channel configuration for data line 1. -//! -//! \return None -//! -//! \sa \ref I2SAudioFormatConfigure() -// -//**************************************************************************** -#ifndef DEPRECATED -extern void I2SChannelConfigure(uint32_t ui32Base, uint32_t ui32Chan0Cfg, - uint32_t ui32Chan1Cfg); -#endif - -//**************************************************************************** -// -//! \brief Configure the I2S frame clock. -//! -//! \deprecated This function will be removed in a future release. -//! -//! Configure I2S clock to be either internal or external and either normal -//! or inverted. -//! -//! \note The bit clock configuration is done externally, but the internal/ -//! external setting must match what is chosen internally in the I2S module -//! for the frame clock. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param ui32ClkConfig is the clock configuration parameter. Bitwise OR'ed -//! combination of clock source and clock polarity: -//! - Clock source: -//! - \ref I2S_EXT_WCLK : External clock. -//! - \ref I2S_INT_WCLK : Internal clock. -//! - Clock polarity: -//! - \ref I2S_NORMAL_WCLK : Normal clock. -//! - \ref I2S_INVERT_WCLK : Inverted clock. -//! -//! \return None -// -//**************************************************************************** -#ifndef DEPRECATED -__STATIC_INLINE void -I2SClockConfigure(uint32_t ui32Base, uint32_t ui32ClkConfig) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Setup register WCLK Source. - HWREG(I2S0_BASE + I2S_O_AIFWCLKSRC) = ui32ClkConfig & - (I2S_AIFWCLKSRC_WCLK_INV_M | - I2S_AIFWCLKSRC_WCLK_SRC_M); -} -#endif - -//**************************************************************************** -// -//! \brief Set the input buffer pointers. -//! -//! \deprecated This function will be removed in a future release. -//! -//! The next pointer should always be written while the DMA is using the -//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will -//! occur and all outputs will be disabled. -//! -//! \note At startup the next data pointer should be -//! written just before and just after calling the \ref I2SEnable(). -//! -//! \param ui32Base is the base address of the I2S module. -//! \param ui32InBufBase is the address of the input buffer. -//! \param ui32OutBufBase is the address of the output buffer. -//! \param ui16DMABufSize is the size of the DMA buffers. Must be greater than 0! -//! \param ui16ChanBufSize is the size of the channel buffers. -//! -//! \return None -// -//**************************************************************************** -#ifndef DEPRECATED -extern void I2SBufferConfig(uint32_t ui32Base, uint32_t ui32InBufBase, - uint32_t ui32OutBufBase, uint16_t ui16DMABufSize, - uint16_t ui16ChanBufSize); -#endif - -//**************************************************************************** -// -//! \brief Update the buffer pointers. -//! -//! \deprecated This function will be removed in a future release. -//! -//! The next pointer should always be written while the DMA is using the -//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur -//! and all outputs will be disabled. Nothing is preventing the pointers from -//! being identical, but this function relies on both pointers (input or -//! output pointers) are pointing to a valid address. -//! -//! \note It is recommended that the pointer update is done in an interrupt context -//! to ensure that the update is performed before the buffer is full. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param bInput determines whether to update input or output pointer. -//! - \c true : Update input pointer. -//! - \c false : Update output pointer -//! -//! \return None -//! -//! \sa \ref I2SPointerSet() -// -//**************************************************************************** -#ifndef DEPRECATED -extern void I2SPointerUpdate(uint32_t ui32Base, bool bInput); -#endif - -//**************************************************************************** -// -//! \brief Set a buffer pointer (input or output) directly. -//! -//! \deprecated This function will be removed in a future release. -//! -//! This function allows bypassing of the pointers in the global control table. -//! -//! The next pointer should always be written while the DMA is using the -//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR will occur -//! and all outputs will be disabled. Nothing is preventing the pointers from -//! being identical, but this function relies on both pointers (input or -//! output pointers) are pointing to a valid address. -//! -//! \note It is recommended that the pointer update is done in an interrupt context -//! to ensure that the update is performed before the buffer is full. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param bInput determines whether to update input or output pointer. -//! - \c true : Update input pointer. -//! - \c false : Update output pointer -//! \param pNextPointer is a void pointer to user defined buffer. -//! -//! \return None -//! -//! \sa \ref I2SPointerUpdate() -// -//**************************************************************************** -#ifndef DEPRECATED -extern void I2SPointerSet(uint32_t ui32Base, bool bInput, void * pNextPointer); -#endif - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for an I2S interrupt in the dynamic interrupt table. -//! -//! \deprecated This function will be removed in a future release. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific I2S interrupts must be enabled via \ref I2SIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param pfnHandler is a pointer to the function to be called when the -//! I2S interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -#ifndef DEPRECATED -__STATIC_INLINE void -I2SIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Register the interrupt handler. - IntRegister(INT_I2S_IRQ, pfnHandler); - - // Enable the I2S interrupt. - IntEnable(INT_I2S_IRQ); -} -#endif - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for a I2S interrupt in the dynamic interrupt table. -//! -//! \deprecated This function will be removed in a future release. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when an I2S interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \param ui32Base is the base address of the I2S port. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -#ifndef DEPRECATED -__STATIC_INLINE void -I2SIntUnregister(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Disable the interrupt. - IntDisable(INT_I2S_IRQ); - - // Unregister the interrupt handler. - IntUnregister(INT_I2S_IRQ); -} -#endif - -//***************************************************************************** -// -//! \brief Configure the sample stamp generator. -//! -//! \deprecated This function will be removed in a future release. -//! -//! Use this function to configure the sample stamp generator. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param bInput enables triggering of the sample stamp generator on input. -//! \param bOutput enables triggering of the sample stamp generator on output. -//! -//! \return None -// -//***************************************************************************** -#ifndef DEPRECATED -extern void I2SSampleStampConfigure(uint32_t ui32Base, bool bInput, - bool bOutput); -#endif - -//***************************************************************************** -// -//! \brief Enables individual I2S interrupt sources. -//! -//! This function enables the indicated I2S interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32Base is the base address of the I2S port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! The parameter is the bitwise OR of any of the following: -//! - \ref I2S_INT_DMA_IN -//! - \ref I2S_INT_DMA_OUT -//! - \ref I2S_INT_TIMEOUT -//! - \ref I2S_INT_BUS_ERR -//! - \ref I2S_INT_WCLK_ERR -//! - \ref I2S_INT_PTR_ERR -//! - \ref I2S_INT_ALL (covers all the above) -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -I2SIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Enable the specified interrupts. - HWREG(I2S0_BASE + I2S_O_IRQMASK) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Disables individual I2S interrupt sources. -//! -//! This function disables the indicated I2S interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32Base is the base address of the I2S port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. -//! The parameter is the bitwise OR of any of the following: -//! - \ref I2S_INT_DMA_IN -//! - \ref I2S_INT_DMA_OUT -//! - \ref I2S_INT_TIMEOUT -//! - \ref I2S_INT_BUS_ERR -//! - \ref I2S_INT_WCLK_ERR -//! - \ref I2S_INT_PTR_ERR -//! - \ref I2S_INT_ALL (covers all the above) -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -I2SIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Disable the specified interrupts. - HWREG(I2S0_BASE + I2S_O_IRQMASK) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Gets the current interrupt status. -//! -//! This function returns the interrupt status for the specified I2S. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \param ui32Base is the base address of the I2S port -//! \param bMasked selects between raw and masked interrupt status: -//! - \c false : Raw interrupt status is required. -//! - \c true : Masked interrupt status is required. -//! -//! \return Returns the current interrupt status as a vector of: -//! - \ref I2S_INT_DMA_IN -//! - \ref I2S_INT_DMA_OUT -//! - \ref I2S_INT_TIMEOUT -//! - \ref I2S_INT_BUS_ERR -//! - \ref I2S_INT_WCLK_ERR -//! - \ref I2S_INT_PTR_ERR -// -//***************************************************************************** -__STATIC_INLINE uint32_t -I2SIntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Mask; - - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Return either the interrupt status or the raw interrupt status as - // requested. - if(bMasked) - { - ui32Mask = HWREG(I2S0_BASE + I2S_O_IRQFLAGS); - return(ui32Mask & HWREG(I2S0_BASE + I2S_O_IRQMASK)); - } - else - { - return(HWREG(I2S0_BASE + I2S_O_IRQFLAGS)); - } -} - -//***************************************************************************** -// -//! \brief Clears I2S interrupt sources. -//! -//! The specified I2S interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32Base is the base address of the I2S port. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! The parameter is the bitwise OR of any of the following: -//! - \ref I2S_INT_DMA_IN -//! - \ref I2S_INT_DMA_OUT -//! - \ref I2S_INT_TIMEOUT -//! - \ref I2S_INT_BUS_ERR -//! - \ref I2S_INT_WCLK_ERR -//! - \ref I2S_INT_PTR_ERR -//! - \ref I2S_INT_ALL (covers all the above) -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2SIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Clear the requested interrupt sources. - HWREG(I2S0_BASE + I2S_O_IRQCLR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Enable the Sample Stamp generator. -//! -//! Use this function to enable the sample stamp generators. -//! -//! \note It is the user's responsibility to ensure that the sample stamp -//! generator is properly configured before it is enabled. It is the setting -//! of the Input and Output triggers configured using \ref I2SSampleStampConfigure() -//! that triggers the start point of the audio streams. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2SSampleStampEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Set the enable bit. - HWREG(I2S0_BASE + I2S_O_STMPCTL) = I2S_STMPCTL_STMP_EN; -} - -//***************************************************************************** -// -//! \brief Disable the Sample Stamp generator. -//! -//! Use this function to disable the sample stamp generators. When the sample -//! stamp generator is disabled, the clock counters are automatically cleared. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2SSampleStampDisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Clear the enable bit. - HWREG(I2S0_BASE + I2S_O_STMPCTL) = 0; - -} - -//***************************************************************************** -// -//! \brief Get the current value of a sample stamp counter. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param ui32Channel is the sample stamp counter to sample -//! -//! \return Returns the current value of the selected sample stamp channel. -// -//***************************************************************************** -extern uint32_t I2SSampleStampGet(uint32_t ui32Base, uint32_t ui32Channel); - -//***************************************************************************** -// -//! \brief Starts the I2S. -//! -//! I2S must be configured before it is started. -//! -//! \note Immediately after enabling the module the programmer must update -//! the DMA data pointer registers using \ref I2SInPointerSet() and -//! \ref I2SOutPointerSet() to ensure a new pointer is written before the DMA -//! transfer completes. Failure to update the pointer in time will result in -//! an \ref I2S_INT_PTR_ERR. -//! -//! \param ui32Base is the I2S module base address. -//! \param ui8FixDMALength is the length of the DMA buffer: this will allow -//! the DMA to read ui8FixDMALength between to pointer refreshes. -//! -//! \return None -//! -//! \sa \ref I2SStop() -// -//***************************************************************************** -__STATIC_INLINE void I2SStart(uint32_t ui32Base, uint8_t ui8FixDMALength) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Enable the I2S module. - HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = ui8FixDMALength; -} - -//***************************************************************************** -// -//! \brief Stops the I2S module for operation. -//! -//! This function will immediately disable the I2S module. To ensure that -//! all buffer operations are completed before shutting down, the correct -//! procedure is: -//! 1. Do not update the data pointers using \ref I2SInPointerSet() and -//! \ref I2SOutPointerSet(). -//! 2. Await that values returned by \ref I2SInPointerNextGet(), -//! \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and \ref I2SOutPointerGet() -//! are zero. -//! 3. Disable the I2S using \ref I2SStop() and clear the pointer -//! error using \ref I2SIntClear(). -//! 4. Disable bit clock source (done externally). -//! -//! \param ui32Base is the I2S module base address. -//! -//! \return None -//! -//! \sa \ref I2SStart() -// -//***************************************************************************** -__STATIC_INLINE void I2SStop(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Disable the I2S module. - HWREG(I2S0_BASE + I2S_O_AIFDMACFG) = 0x00; -} - -//***************************************************************************** -// -//! \brief Configure the serial format of the I2S module. -//! -//! The word length defines the size of the word transmitted on the data -//! lines. For single phased formats \c ui8BitsPerSample is the exact number -//! of bits per word. In dual phased format this is the maximum number of bits -//! per word. -//! -//! \param ui32Base is the I2S module base address. -//! \param ui8iDataDelay is the number of BCLK periods between the first WCLK -//! edge and the MSB of the first audio channel data transferred during -//! the phase. -//! \param ui8iMemory24Bits selects if the samples in memory are coded on 16 bits -//! or 24 bits. Possible values are: -//! - \ref I2S_MEM_LENGTH_16 -//! - \ref I2S_MEM_LENGTH_24 -//! \param ui8iSamplingEdge selects if sampling on falling or rising edges. -//! Possible values are: -//! - \ref I2S_NEG_EDGE -//! - \ref I2S_POS_EDGE -//! \param boolDualPhase must be set to true for dual phase and to false for -//! single phase and user-defined phase. -//! \param ui8BitsPerSample is the number of bits transmitted for each sample. -//! If this number does not match with the memory length selected -//! (16 bits or24 bits), samples will be truncated or padded. -//! \param ui16transmissionDelay is the number of WCLK periods before the first -//! transmission. -//! -//! \return None -//! -//! \sa \ref I2SFrameConfigure() -// -//***************************************************************************** -__STATIC_INLINE void -I2SFormatConfigure(uint32_t ui32Base, - uint8_t ui8iDataDelay, - uint8_t ui8iMemory24Bits, - uint8_t ui8iSamplingEdge, - bool boolDualPhase, - uint8_t ui8BitsPerSample, - uint16_t ui16transmissionDelay) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - ASSERT(ui8BitsPerSample <= I2S_AIFFMTCFG_WORD_LEN_MAX); - ASSERT(ui8BitsPerSample >= I2S_AIFFMTCFG_WORD_LEN_MIN); - - // Setup register AIFFMTCFG Source. - HWREGH(I2S0_BASE + I2S_O_AIFFMTCFG) = - (ui8iDataDelay << I2S_AIFFMTCFG_DATA_DELAY_S) | - (ui8iMemory24Bits << I2S_AIFFMTCFG_MEM_LEN_24_S) | - (ui8iSamplingEdge << I2S_AIFFMTCFG_SMPL_EDGE_S ) | - (boolDualPhase << I2S_AIFFMTCFG_DUAL_PHASE_S) | - (ui8BitsPerSample << I2S_AIFFMTCFG_WORD_LEN_S ); - - // Number of WCLK periods before the first read / write - HWREGH(I2S0_BASE + I2S_O_STMPWPER) = ui16transmissionDelay; -} - -//**************************************************************************** -// -//! \brief Setup the two interfaces SD0 and SD1 (also called AD0 and AD1). -//! -//! This function sets interface's direction and activated channels. -//! -//! \param ui32Base is base address of the I2S module. -//! \param ui8StatusAD0 defines the usage of AD0 -//! 0x00: AD0 is disabled -//! 0x01, AD0 is an input -//! 0x02, AD0 is an output -//! \param ui8ChanAD0 defines the channel mask for AD0. -//! Use a bitwise OR'ed combination of: -//! - \ref I2S_CHAN0_MASK -//! - \ref I2S_CHAN1_MASK -//! - \ref I2S_CHAN2_MASK -//! - \ref I2S_CHAN3_MASK -//! - \ref I2S_CHAN4_MASK -//! - \ref I2S_CHAN5_MASK -//! - \ref I2S_CHAN6_MASK -//! - \ref I2S_CHAN7_MASK -//! \param ui8StatusAD1 defines the usage of AD1 -//! 0x00: AD1 is disabled -//! 0x10, AD1 is an input -//! 0x20, AD1 is an output -//! \param ui8ChanAD1 defines the channel mask for AD1. -//! Use a bitwise OR'ed combination of: -//! - \ref I2S_CHAN0_MASK -//! - \ref I2S_CHAN1_MASK -//! - \ref I2S_CHAN2_MASK -//! - \ref I2S_CHAN3_MASK -//! - \ref I2S_CHAN4_MASK -//! - \ref I2S_CHAN5_MASK -//! - \ref I2S_CHAN6_MASK -//! - \ref I2S_CHAN7_MASK -//! -//! \return None -//! -//! \sa \ref I2SFormatConfigure() -// -//**************************************************************************** -__STATIC_INLINE void -I2SFrameConfigure(uint32_t ui32Base, - uint8_t ui8StatusAD0, uint8_t ui8ChanAD0, - uint8_t ui8StatusAD1, uint8_t ui8ChanAD1) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Configure input/output channels. - HWREGB(I2S0_BASE + I2S_O_AIFDIRCFG) = (ui8StatusAD0 | ui8StatusAD1); - - // Configure the valid channel mask. - HWREGB(I2S0_BASE + I2S_O_AIFWMASK0) = ui8ChanAD0; - HWREGB(I2S0_BASE + I2S_O_AIFWMASK1) = ui8ChanAD1; -} - -//**************************************************************************** -// -//! \brief Configure the I2S frame clock (also called WCLK or WS). -//! -//! Configure WCLK clock to be either internal (master) or external (slave). -//! Configure WCLK clock either normal or inverted. -//! -//! \note The bit clock configuration is done externally, but the internal/ -//! external setting must match what is chosen internally in the I2S module -//! for the frame clock. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param boolMaster false: the device is a slave (external clock) -//! true: the device is a master (internal clock) -//! \param boolWCLKInvert false: WCLK is not inverted -//! true: WCLK is internally inverted -//! -//! \return None -// -//**************************************************************************** -__STATIC_INLINE void -I2SWclkConfigure(uint32_t ui32Base, - bool boolMaster, - bool boolWCLKInvert) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - ASSERT(ui8ClkSource < I2S_AIFWCLKSRC_WCLK_SRC_RESERVED); - - // if(boolMaster == 0) then ui8ClkSource = 1 - // if(boolMaster == 1) then ui8ClkSource = 2 - uint8_t ui8ClkSource = (uint8_t)boolMaster + 0x01; - - // Setup register WCLK Source. - HWREGB(I2S0_BASE + I2S_O_AIFWCLKSRC) = - ((ui8ClkSource << I2S_AIFWCLKSRC_WCLK_SRC_S) | - (boolWCLKInvert << I2S_AIFWCLKSRC_WCLK_INV_S )); -} - -//**************************************************************************** -// -//! \brief Set the input buffer pointer. -//! -//! The next pointer should always be written while the DMA is using the -//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR -//! will occur and all inputs and outputs will be disabled. -//! This function relies on pointer is pointing to a valid address. -//! -//! \note It is recommended that the pointer update is done in an interrupt context -//! to ensure that the update is performed before the buffer is full. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param ui32NextPointer is the adress of the data -//! -//! \return None -//! -//! \sa \ref I2SOutPointerSet() -// -//**************************************************************************** -__STATIC_INLINE void -I2SInPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT) = ui32NextPointer; -} - -//**************************************************************************** -// -//! \brief Set the output buffer pointer. -//! -//! The next pointer should always be written while the DMA is using the -//! previous written pointer. If not written in time an \ref I2S_INT_PTR_ERR -//! will occur and all inputs and outputs will be disabled. -//! This function relies on pointer is pointing to a valid address. -//! -//! \note It is recommended that the pointer update is done in an interrupt context -//! to ensure that the update is performed before the buffer is full. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param ui32NextPointer is the adress of the data -//! -//! \return None -//! -//! \sa \ref I2SInPointerSet() -// -//**************************************************************************** -__STATIC_INLINE void -I2SOutPointerSet(uint32_t ui32Base, uint32_t ui32NextPointer) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT) = ui32NextPointer; -} - -//**************************************************************************** -// -//! \brief Get value stored in PTR NEXT IN register -//! -//! \param ui32Base is the base address of the I2S module. -//! -//! \return the value of PTR NEXT IN. -// -//**************************************************************************** -__STATIC_INLINE uint32_t -I2SInPointerNextGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - return (HWREG(I2S0_BASE + I2S_O_AIFINPTRNEXT)); -} - - -//**************************************************************************** -// -//! \brief Get value stored in PTR NEXT OUT register -//! -//! \param ui32Base is the base address of the I2S module. -//! -//! \return the value of PTR NEXT OUT. -// -//**************************************************************************** -__STATIC_INLINE uint32_t -I2SOutPointerNextGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTRNEXT)); -} - -//**************************************************************************** -// -//! \brief Get value stored in PTR IN register -//! -//! \param ui32Base is the base address of the I2S module. -//! -//! \return the value of PTR IN. -// -//**************************************************************************** -__STATIC_INLINE uint32_t -I2SInPointerGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - return (HWREG(I2S0_BASE + I2S_O_AIFINPTR)); -} - -//**************************************************************************** -// -//! \brief Get value stored in PTR OUT register -//! -//! \param ui32Base is the base address of the I2S module. -//! -//! \return the value of PTR OUT. -// -//**************************************************************************** -__STATIC_INLINE uint32_t -I2SOutPointerGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - return (HWREG(I2S0_BASE + I2S_O_AIFOUTPTR)); -} - -//***************************************************************************** -// -//! \brief Configure the IN sample stamp generator. -//! -//! Use this function to configure the sample stamp generator. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param ui16TrigValue value used to set the trigger. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2SSampleStampInConfigure(uint32_t ui32Base, uint16_t ui16TrigValue) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Setup the sample stamp trigger for input streams. - HWREGH(I2S0_BASE + I2S_O_STMPINTRIG) = ui16TrigValue; -} - -//***************************************************************************** -// -//! \brief Configure the OUT sample stamp generator. -//! -//! Use this function to configure the sample stamp generator. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param ui16TrigValue value used to set the trigger. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2SSampleStampOutConfigure(uint32_t ui32Base, uint16_t ui16TrigValue) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - // Setup the sample stamp trigger for output streams. - HWREGH(I2S0_BASE + I2S_O_STMPOUTTRIG) = ui16TrigValue; -} - -//***************************************************************************** -// -//! \brief Add the specified value to the WCLK count. -//! -//! \param ui32Base is the base address of the I2S module. -//! \param i16Value is the offset to add to the counter (this value can be negative) -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2SWclkCounterConfigure(uint32_t ui32Base, int16_t i16Value) -{ - uint16_t ui16MinusValue; - - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - if (i16Value >= 0) - { - HWREGH(I2S0_BASE + I2S_O_STMPWADD) = i16Value; - } - else - { - ui16MinusValue = (uint16_t)(-i16Value); - HWREGH(I2S0_BASE + I2S_O_STMPWADD) = HWREGH(I2S0_BASE + I2S_O_STMPWPER) - ui16MinusValue; - } -} - -//***************************************************************************** -// -//! \brief Reset the WCLK count. -//! -//! \param ui32Base is the base address of the I2S module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -I2SWclkCounterReset(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(I2SBaseValid(ui32Base)); - - HWREGH(I2S0_BASE + I2S_O_STMPWSET) = 0; -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_I2SEnable - #undef I2SEnable - #define I2SEnable ROM_I2SEnable - #endif - #ifdef ROM_I2SAudioFormatConfigure - #undef I2SAudioFormatConfigure - #define I2SAudioFormatConfigure ROM_I2SAudioFormatConfigure - #endif - #ifdef ROM_I2SChannelConfigure - #undef I2SChannelConfigure - #define I2SChannelConfigure ROM_I2SChannelConfigure - #endif - #ifdef ROM_I2SBufferConfig - #undef I2SBufferConfig - #define I2SBufferConfig ROM_I2SBufferConfig - #endif - #ifdef ROM_I2SPointerUpdate - #undef I2SPointerUpdate - #define I2SPointerUpdate ROM_I2SPointerUpdate - #endif - #ifdef ROM_I2SPointerSet - #undef I2SPointerSet - #define I2SPointerSet ROM_I2SPointerSet - #endif - #ifdef ROM_I2SSampleStampConfigure - #undef I2SSampleStampConfigure - #define I2SSampleStampConfigure ROM_I2SSampleStampConfigure - #endif - #ifdef ROM_I2SSampleStampGet - #undef I2SSampleStampGet - #define I2SSampleStampGet ROM_I2SSampleStampGet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __I2S_H__ - -//**************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//**************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h deleted file mode 100644 index 5f2e1d9e046..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/i2s_doc.h +++ /dev/null @@ -1,141 +0,0 @@ -/****************************************************************************** -* Filename: i2s_doc.h -* Revised: $$ -* Revision: $$ -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup i2s_api -//! @{ -//! \section sec_i2s Introduction -//! -//! The I2S API provides a set of functions for using the I2S module. -//! This module provides a standardized serial interface to transfer -//! audio samples from and to external audio devices such as a codec, -//! DAC, or ADC. -//! -//! The I2S module has the following features: -//! - Audio clock signals are internally generated by the PRCM module -//! or externally by another device. -//! - One or two data pins, which can be configured independently as -//! input or output -//! - Various data formats according to the settings of the module -//! - Up to two channels per data pin for dual phase formats and up -//! to eight channels per data pin for single phase formats -//! - DMA with double-buffered pointers -//! - Error detection for DMA and audio clock signal integrity -//! - A Samplestamp generator that allows maintaining of constant -//! audio latency -//! -//! The I2S module is configured through the functions \ref I2SFormatConfigure(), -//! \ref I2SFrameConfigure() and \ref I2SWclkConfigure(). -//! Transfers are enabled using \ref I2SStart(). Transfers are disabled using -//! \ref I2SStop(). Please note that a specific procedure exists in order -//! to disable transfers without losing data (refer to \ref I2SStop()). -//! -//! Data are transmitted using the two double-buffered pointers. -//! For each interface, two registers are set with the address of the data to -//! transfer. These registers are named INPTR and INPTRNEXT for the input -//! interface and OUTPTR and OUTPTRNEXT for the output. When PTR is consumed, -//! the hardware copies the content of PTRNEXT into PTR and the next transfer -//! begins. -//! The address of the next value to write or to read in memory (i.e. to receive -//! or to send out) is set using \ref I2SInPointerSet() and \ref I2SOutPointerSet(). -//! The values contented by INPTRNEXT, OUTPTRNEXT, INPTR and OUTPTR can be read using -//! \ref I2SInPointerNextGet(), \ref I2SOutPointerNextGet(), \ref I2SInPointerGet() and -//! \ref I2SOutPointerGet() functions. -//! -//! Interrupts can help the user to refresh pointers on time. Interrupts can also -//! be used to detect I2S errors. \ref I2SIntEnable() and \ref I2SIntDisable() -//! activate and deactivate interrupt(s). Interrupt status can be read through -//! \ref I2SIntStatus() and a pending interrupt can be acquitted by -//! \ref I2SIntClear() function. -//! -//! The sample stamps generator can be configured to slightly delay the -//! emission or the reception of the data (based on the number of WCLK -//! cycles) using \ref I2SSampleStampInConfigure(), \ref I2SSampleStampOutConfigure(), -//! \ref I2SWclkCounterReset() and \ref I2SWclkCounterConfigure(). The current sample stamp -//! can be computed using \ref I2SSampleStampGet(). -//! To finish, the sample stamps generator can be enable and disable using -//! the following functions: \ref I2SSampleStampEnable() and -//! \ref I2SSampleStampDisable(). -//! The sample stamps generator must be enabled prior to any transfer. -//! -//! Note: Other functions contained in the PRCM API are required to handle I2S. -//! -//! \section sec_i2s_api API -//! -//! Two APIs are coexisting. -//! It is recommended to only use the new API as the old one is deprecated and -//! will be removed soon. -//! -//! New API: -//! Functions to perform I2S configuration: -//! - \ref I2SStart() -//! - \ref I2SStop() -//! - \ref I2SFormatConfigure() -//! - \ref I2SFrameConfigure() -//! - \ref I2SWclkConfigure() -//! -//! Functions to perform transfers: -//! - \ref I2SInPointerSet() -//! - \ref I2SOutPointerSet() -//! - \ref I2SInPointerGet() -//! - \ref I2SOutPointerGet() -//! - \ref I2SInPointerNextGet() -//! - \ref I2SOutPointerNextGet() -//! -//! Functions to handle interruptions: -//! - \ref I2SIntEnable() -//! - \ref I2SIntDisable() -//! - \ref I2SIntStatus() -//! - \ref I2SIntClear() -//! -//! Functions to handle sample stamps -//! - \ref I2SSampleStampEnable() -//! - \ref I2SSampleStampDisable() -//! - \ref I2SSampleStampInConfigure() -//! - \ref I2SSampleStampOutConfigure() -//! - \ref I2SSampleStampGet() -//! - \ref I2SWclkCounterConfigure() -//! - \ref I2SWclkCounterReset() -//! -//! Old API: -//! \ref I2SEnable(), \ref I2SDisable(), \ref I2SAudioFormatConfigure(), -//! \ref I2SChannelConfigure(), \ref I2SClockConfigure(), -//! \ref I2SBufferConfig(), \ref I2SIntEnable(), \ref I2SIntDisable(), -//! \ref I2SIntStatus(), \ref I2SIntClear(), \ref I2SSampleStampEnable(), -//! \ref I2SSampleStampDisable(), \ref I2SSampleStampGet(), -//! \ref I2SPointerSet (), \ref I2SPointerUpdate(), -//! \ref I2SSampleStampConfigure(), \ref I2SIntRegister(), -//! \ref I2SIntUnregister() -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.c deleted file mode 100644 index d0cd9bc593c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.c +++ /dev/null @@ -1,469 +0,0 @@ -/****************************************************************************** -* Filename: interrupt.c -* Revised: 2017-05-19 11:31:39 +0200 (Fri, 19 May 2017) -* Revision: 49017 -* -* Description: Driver for the NVIC Interrupt Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "interrupt.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef IntRegister - #define IntRegister NOROM_IntRegister - #undef IntUnregister - #define IntUnregister NOROM_IntUnregister - #undef IntPriorityGroupingSet - #define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet - #undef IntPriorityGroupingGet - #define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet - #undef IntPrioritySet - #define IntPrioritySet NOROM_IntPrioritySet - #undef IntPriorityGet - #define IntPriorityGet NOROM_IntPriorityGet - #undef IntEnable - #define IntEnable NOROM_IntEnable - #undef IntDisable - #define IntDisable NOROM_IntDisable - #undef IntPendSet - #define IntPendSet NOROM_IntPendSet - #undef IntPendGet - #define IntPendGet NOROM_IntPendGet - #undef IntPendClear - #define IntPendClear NOROM_IntPendClear -#endif - -//***************************************************************************** -// -//! This is a mapping between priority grouping encodings and the number of -//! preemption priority bits. -// -//***************************************************************************** -static const uint32_t g_pui32Priority[] = -{ - NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, - NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, - NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 -}; - -//***************************************************************************** -// -//! This is a mapping between interrupt number and the register that contains -//! the priority encoding for that interrupt. -// -//***************************************************************************** -static const uint32_t g_pui32Regs[] = -{ - 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, - NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, - NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13 -}; - -//***************************************************************************** -// -//! \brief The default interrupt handler. -//! -//! This is the default interrupt handler for all interrupts. It simply loops -//! forever so that the system state is preserved for observation by a -//! debugger. Since interrupts should be disabled before unregistering the -//! corresponding handler, this should never be called. -//! -//! \return None -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // Go into an infinite loop. - while(1) - { - } -} - -//***************************************************************************** -// -//! \brief Global pointer to the (dynamic) interrupt vector table when placed in SRAM. -//! -//! Interrupt vector table is placed at "vtable_ram" defined in the linker file -//! provided by Texas Instruments. By default, this is at the beginning of SRAM. -//! -//! \note See \ti_code{interrupt.c} for compiler specific implementation! -// -//***************************************************************************** -#if defined(DOXYGEN) -// Dummy void pointer used as placeholder to generate Doxygen documentation. -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); -#elif defined(__IAR_SYSTEMS_ICC__) -#pragma data_alignment=256 -static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ ".vtable_ram"; -#elif defined(__TI_COMPILER_VERSION__) -#pragma DATA_ALIGN(g_pfnRAMVectors, 256) -#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable_ram") -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void); -#elif defined (__CC_ARM) -static __attribute__((section("vtable_ram"))) -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256))); -#else -static __attribute__((section("vtable_ram"))) -void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(256))); -#endif - -//***************************************************************************** -// -// Registers a function to be called when an interrupt occurs. -// -//***************************************************************************** -void -IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)) -{ - uint32_t ui32Idx, ui32Value; - - // Check the arguments. - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // Make sure that the RAM vector table is correctly aligned. - ASSERT(((uint32_t)g_pfnRAMVectors & 0x000000ff) == 0); - - // See if the RAM vector table has been initialized. - if(HWREG(NVIC_VTABLE) != (uint32_t)g_pfnRAMVectors) - { - // Copy the vector table from the beginning of FLASH to the RAM vector - // table. - ui32Value = HWREG(NVIC_VTABLE); - for(ui32Idx = 0; ui32Idx < NUM_INTERRUPTS; ui32Idx++) - { - g_pfnRAMVectors[ui32Idx] = (void (*)(void))HWREG((ui32Idx * 4) + - ui32Value); - } - - // Point NVIC at the RAM vector table. - HWREG(NVIC_VTABLE) = (uint32_t)g_pfnRAMVectors; - } - - // Save the interrupt handler. - g_pfnRAMVectors[ui32Interrupt] = pfnHandler; -} - -//***************************************************************************** -// -// Unregisters the function to be called when an interrupt occurs. -// -//***************************************************************************** -void -IntUnregister(uint32_t ui32Interrupt) -{ - // Check the arguments. - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // Reset the interrupt handler. - g_pfnRAMVectors[ui32Interrupt] = IntDefaultHandler; -} - -//***************************************************************************** -// -// Sets the priority grouping of the interrupt controller. -// -//***************************************************************************** -void -IntPriorityGroupingSet(uint32_t ui32Bits) -{ - // Check the arguments. - ASSERT(ui32Bits < NUM_PRIORITY); - - // Set the priority grouping. - HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pui32Priority[ui32Bits]; -} - -//***************************************************************************** -// -// Gets the priority grouping of the interrupt controller -// -//***************************************************************************** -uint32_t -IntPriorityGroupingGet(void) -{ - uint32_t ui32Loop, ui32Value; - - // Read the priority grouping. - ui32Value = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; - - // Loop through the priority grouping values. - for(ui32Loop = 0; ui32Loop < NUM_PRIORITY; ui32Loop++) - { - // Stop looping if this value matches. - if(ui32Value == g_pui32Priority[ui32Loop]) - { - break; - } - } - - // Return the number of priority bits. - return(ui32Loop); -} - -//***************************************************************************** -// -// Sets the priority of an interrupt -// -//***************************************************************************** -void -IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority) -{ - uint32_t ui32Temp; - - // Check the arguments. - ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); - ASSERT(ui8Priority <= INT_PRI_LEVEL7); - - // Set the interrupt priority. - ui32Temp = HWREG(g_pui32Regs[ui32Interrupt >> 2]); - ui32Temp &= ~(0xFF << (8 * (ui32Interrupt & 3))); - ui32Temp |= ui8Priority << (8 * (ui32Interrupt & 3)); - HWREG(g_pui32Regs[ui32Interrupt >> 2]) = ui32Temp; -} - -//***************************************************************************** -// -// Gets the priority of an interrupt -// -//***************************************************************************** -int32_t -IntPriorityGet(uint32_t ui32Interrupt) -{ - // Check the arguments. - ASSERT((ui32Interrupt >= 4) && (ui32Interrupt < NUM_INTERRUPTS)); - - // Return the interrupt priority. - return((HWREG(g_pui32Regs[ui32Interrupt >> 2]) >> (8 * (ui32Interrupt & 3))) & - 0xFF); -} - -//***************************************************************************** -// -// Enables an interrupt -// -//***************************************************************************** -void -IntEnable(uint32_t ui32Interrupt) -{ - // Check the arguments. - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // Determine the interrupt to enable. - if(ui32Interrupt == INT_MEMMANAGE_FAULT) - { - // Enable the MemManage interrupt. - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; - } - else if(ui32Interrupt == INT_BUS_FAULT) - { - // Enable the bus fault interrupt. - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; - } - else if(ui32Interrupt == INT_USAGE_FAULT) - { - // Enable the usage fault interrupt. - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; - } - else if(ui32Interrupt == INT_SYSTICK) - { - // Enable the System Tick interrupt. - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; - } - else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) - { - // Enable the general interrupt. - HWREG(NVIC_EN0) = 1 << (ui32Interrupt - 16); - } - else if(ui32Interrupt >= 48) - { - // Enable the general interrupt. - HWREG(NVIC_EN1) = 1 << (ui32Interrupt - 48); - } -} - -//***************************************************************************** -// -// Disables an interrupt -// -//***************************************************************************** -void -IntDisable(uint32_t ui32Interrupt) -{ - // Check the arguments. - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // Determine the interrupt to disable. - if(ui32Interrupt == INT_MEMMANAGE_FAULT) - { - // Disable the MemManage interrupt. - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); - } - else if(ui32Interrupt == INT_BUS_FAULT) - { - // Disable the bus fault interrupt. - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); - } - else if(ui32Interrupt == INT_USAGE_FAULT) - { - // Disable the usage fault interrupt. - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); - } - else if(ui32Interrupt == INT_SYSTICK) - { - // Disable the System Tick interrupt. - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - } - else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) - { - // Disable the general interrupt. - HWREG(NVIC_DIS0) = 1 << (ui32Interrupt - 16); - } - else if(ui32Interrupt >= 48) - { - // Disable the general interrupt. - HWREG(NVIC_DIS1) = 1 << (ui32Interrupt - 48); - } -} - -//***************************************************************************** -// -// Pends an interrupt -// -//***************************************************************************** -void -IntPendSet(uint32_t ui32Interrupt) -{ - // Check the arguments. - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // Determine the interrupt to pend. - if(ui32Interrupt == INT_NMI_FAULT) - { - // Pend the NMI interrupt. - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; - } - else if(ui32Interrupt == INT_PENDSV) - { - // Pend the PendSV interrupt. - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; - } - else if(ui32Interrupt == INT_SYSTICK) - { - // Pend the SysTick interrupt. - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; - } - else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) - { - // Pend the general interrupt. - HWREG(NVIC_PEND0) = 1 << (ui32Interrupt - 16); - } - else if(ui32Interrupt >= 48) - { - // Pend the general interrupt. - HWREG(NVIC_PEND1) = 1 << (ui32Interrupt - 48); - } -} - -//***************************************************************************** -// -// Query whether an interrupt is pending -// -//***************************************************************************** -bool -IntPendGet(uint32_t ui32Interrupt) -{ - uint32_t ui32IntPending; - - // Check the arguments. - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // Assume no interrupts are pending. - ui32IntPending = 0; - - // The lower 16 IRQ vectors are unsupported by this function - if (ui32Interrupt < 16) - { - - return 0; - } - - // Subtract lower 16 irq vectors - ui32Interrupt -= 16; - - // Check if the interrupt is pending - ui32IntPending = HWREG(NVIC_PEND0 + (ui32Interrupt / 32)); - ui32IntPending &= (1 << (ui32Interrupt & 31)); - - return ui32IntPending ? true : false; -} - -//***************************************************************************** -// -// Unpends an interrupt -// -//***************************************************************************** -void -IntPendClear(uint32_t ui32Interrupt) -{ - // Check the arguments. - ASSERT(ui32Interrupt < NUM_INTERRUPTS); - - // Determine the interrupt to unpend. - if(ui32Interrupt == INT_PENDSV) - { - // Unpend the PendSV interrupt. - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; - } - else if(ui32Interrupt == INT_SYSTICK) - { - // Unpend the SysTick interrupt. - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; - } - else if((ui32Interrupt >= 16) && (ui32Interrupt <= 47)) - { - // Unpend the general interrupt. - HWREG(NVIC_UNPEND0) = 1 << (ui32Interrupt - 16); - } - else if(ui32Interrupt >= 48) - { - // Unpend the general interrupt. - HWREG(NVIC_UNPEND1) = 1 << (ui32Interrupt - 48); - } -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h deleted file mode 100644 index 3a2d1dd61af..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt.h +++ /dev/null @@ -1,718 +0,0 @@ -/****************************************************************************** -* Filename: interrupt.h -* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) -* Revision: 50272 -* -* Description: Defines and prototypes for the NVIC Interrupt Controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_cpu_group -//! @{ -//! \addtogroup interrupt_api -//! @{ -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_ints.h" -#include "../inc/hw_types.h" -#include "../inc/hw_nvic.h" -#include "debug.h" -#include "cpu.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define IntRegister NOROM_IntRegister - #define IntUnregister NOROM_IntUnregister - #define IntPriorityGroupingSet NOROM_IntPriorityGroupingSet - #define IntPriorityGroupingGet NOROM_IntPriorityGroupingGet - #define IntPrioritySet NOROM_IntPrioritySet - #define IntPriorityGet NOROM_IntPriorityGet - #define IntEnable NOROM_IntEnable - #define IntDisable NOROM_IntDisable - #define IntPendSet NOROM_IntPendSet - #define IntPendGet NOROM_IntPendGet - #define IntPendClear NOROM_IntPendClear -#endif - -//***************************************************************************** -// -// Macro to generate an interrupt priority mask based on the number of bits -// of priority supported by the hardware. For CC26xx the number of priority -// bit is 3 as defined in hw_types.h. The priority mask is -// defined as -// -// INT_PRIORITY_MASK = ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) -// -//***************************************************************************** -#define INT_PRIORITY_MASK 0x000000E0 -#define INT_PRI_LEVEL0 0x00000000 -#define INT_PRI_LEVEL1 0x00000020 -#define INT_PRI_LEVEL2 0x00000040 -#define INT_PRI_LEVEL3 0x00000060 -#define INT_PRI_LEVEL4 0x00000080 -#define INT_PRI_LEVEL5 0x000000A0 -#define INT_PRI_LEVEL6 0x000000C0 -#define INT_PRI_LEVEL7 0x000000E0 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Registers a function as an interrupt handler in the dynamic vector table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function writes a function pointer to the dynamic interrupt vector table -//! in SRAM to register the function as an interrupt handler (ISR). When the corresponding -//! interrupt occurs, and it has been enabled (see \ref IntEnable()), the function -//! pointer is fetched from the dynamic vector table, and the System CPU will -//! execute the interrupt handler. -//! -//! \note The first call to this function (directly or indirectly via a peripheral -//! driver interrupt register function) copies the interrupt vector table from -//! Flash to SRAM. NVIC uses the static vector table (in Flash) until this function -//! is called. -//! -//! \param ui32Interrupt specifies the index in the vector table to modify. -//! - System exceptions (vectors 0 to 15): -//! - INT_NMI_FAULT -//! - INT_HARD_FAULT -//! - INT_MEMMANAGE_FAULT -//! - INT_BUS_FAULT -//! - INT_USAGE_FAULT -//! - INT_SVCALL -//! - INT_DEBUG -//! - INT_PENDSV -//! - INT_SYSTICK -//! - Interrupts (vectors >15): -//! - INT_AON_GPIO_EDGE -//! - INT_I2C_IRQ -//! - INT_RFC_CPE_1 -//! - INT_PKA_IRQ -//! - INT_AON_RTC_COMB -//! - INT_UART0_COMB -//! - INT_AUX_SWEV0 -//! - INT_SSI0_COMB -//! - INT_SSI1_COMB -//! - INT_RFC_CPE_0 -//! - INT_RFC_HW_COMB -//! - INT_RFC_CMD_ACK -//! - INT_I2S_IRQ -//! - INT_AUX_SWEV1 -//! - INT_WDT_IRQ -//! - INT_GPT0A -//! - INT_GPT0B -//! - INT_GPT1A -//! - INT_GPT1B -//! - INT_GPT2A -//! - INT_GPT2B -//! - INT_GPT3A -//! - INT_GPT3B -//! - INT_CRYPTO_RESULT_AVAIL_IRQ -//! - INT_DMA_DONE_COMB -//! - INT_DMA_ERR -//! - INT_FLASH -//! - INT_SWEV0 -//! - INT_AUX_COMB -//! - INT_AON_PROG0 -//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) -//! - INT_AUX_COMPA -//! - INT_AUX_ADC_IRQ -//! - INT_TRNG_IRQ -//! - INT_OSC_COMB -//! - INT_AUX_TIMER2_EV0 -//! - INT_UART1_COMB -//! - INT_BATMON_COMB -//! \param pfnHandler is a pointer to the function to register as interrupt handler. -//! -//! \return None. -//! -//! \sa \ref IntUnregister(), \ref IntEnable() -// -//***************************************************************************** -extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)); - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler in the dynamic vector table. -//! -//! This function removes an interrupt handler from the dynamic vector table and -//! replaces it with the default interrupt handler \ref IntDefaultHandler(). -//! -//! \note Remember to disable the interrupt before removing its interrupt handler -//! from the vector table. -//! -//! \param ui32Interrupt specifies the index in the vector table to modify. -//! - See \ref IntRegister() for list of valid arguments. -//! -//! \return None. -//! -//! \sa \ref IntRegister(), \ref IntDisable() -// -//***************************************************************************** -extern void IntUnregister(uint32_t ui32Interrupt); - -//***************************************************************************** -// -//! \brief Sets the priority grouping of the interrupt controller. -//! -//! This function specifies the split between preemptable priority levels and -//! subpriority levels in the interrupt priority specification. -//! -//! Three bits are available for hardware interrupt prioritization thus priority -//! grouping values of three through seven have the same effect. -//! -//! \param ui32Bits specifies the number of bits of preemptable priority. -//! - 0 : No pre-emption priority, eight bits of subpriority. -//! - 1 : One bit of pre-emption priority, seven bits of subpriority -//! - 2 : Two bits of pre-emption priority, six bits of subpriority -//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority -//! -//! \return None -//! -//! \sa \ref IntPrioritySet() -// -//***************************************************************************** -extern void IntPriorityGroupingSet(uint32_t ui32Bits); - -//***************************************************************************** -// -//! \brief Gets the priority grouping of the interrupt controller. -//! -//! This function returns the split between preemptable priority levels and -//! subpriority levels in the interrupt priority specification. -//! -//! \return Returns the number of bits of preemptable priority. -//! - 0 : No pre-emption priority, eight bits of subpriority. -//! - 1 : One bit of pre-emption priority, seven bits of subpriority -//! - 2 : Two bits of pre-emption priority, six bits of subpriority -//! - 3-7 : Three bits of pre-emption priority, five bits of subpriority -// -//***************************************************************************** -extern uint32_t IntPriorityGroupingGet(void); - -//***************************************************************************** -// -//! \brief Sets the priority of an interrupt. -//! -//! This function sets the priority of an interrupt, including system exceptions. -//! When multiple interrupts are asserted simultaneously, the ones with the highest -//! priority are processed before the lower priority interrupts. Smaller numbers -//! correspond to higher interrupt priorities thus priority 0 is the highest -//! interrupt priority. -//! -//! \warning This function does not support setting priority of interrupt vectors -//! one through three which are: -//! - 1: Reset handler -//! - 2: NMI handler -//! - 3: Hard fault handler -//! -//! \param ui32Interrupt specifies the index in the vector table to change priority for. -//! - System exceptions: -//! - INT_MEMMANAGE_FAULT -//! - INT_BUS_FAULT -//! - INT_USAGE_FAULT -//! - INT_SVCALL -//! - INT_DEBUG -//! - INT_PENDSV -//! - INT_SYSTICK -//! - Interrupts: -//! - INT_AON_GPIO_EDGE -//! - INT_I2C_IRQ -//! - INT_RFC_CPE_1 -//! - INT_PKA_IRQ -//! - INT_AON_RTC_COMB -//! - INT_UART0_COMB -//! - INT_AUX_SWEV0 -//! - INT_SSI0_COMB -//! - INT_SSI1_COMB -//! - INT_RFC_CPE_0 -//! - INT_RFC_HW_COMB -//! - INT_RFC_CMD_ACK -//! - INT_I2S_IRQ -//! - INT_AUX_SWEV1 -//! - INT_WDT_IRQ -//! - INT_GPT0A -//! - INT_GPT0B -//! - INT_GPT1A -//! - INT_GPT1B -//! - INT_GPT2A -//! - INT_GPT2B -//! - INT_GPT3A -//! - INT_GPT3B -//! - INT_CRYPTO_RESULT_AVAIL_IRQ -//! - INT_DMA_DONE_COMB -//! - INT_DMA_ERR -//! - INT_FLASH -//! - INT_SWEV0 -//! - INT_AUX_COMB -//! - INT_AON_PROG0 -//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) -//! - INT_AUX_COMPA -//! - INT_AUX_ADC_IRQ -//! - INT_TRNG_IRQ -//! - INT_OSC_COMB -//! - INT_AUX_TIMER2_EV0 -//! - INT_UART1_COMB -//! - INT_BATMON_COMB -//! \param ui8Priority specifies the priority of the interrupt. -//! - \ref INT_PRI_LEVEL0 : Highest priority. -//! - \ref INT_PRI_LEVEL1 -//! - \ref INT_PRI_LEVEL2 -//! - \ref INT_PRI_LEVEL3 -//! - \ref INT_PRI_LEVEL4 -//! - \ref INT_PRI_LEVEL5 -//! - \ref INT_PRI_LEVEL6 -//! - \ref INT_PRI_LEVEL7 : Lowest priority. -//! -//! \return None -//! -//! \sa \ref IntPriorityGroupingSet() -// -//***************************************************************************** -extern void IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority); - -//***************************************************************************** -// -//! \brief Gets the priority of an interrupt. -//! -//! This function gets the priority of an interrupt. -//! -//! \warning This function does not support getting priority of interrupt vectors -//! one through three which are: -//! - 1: Reset handler -//! - 2: NMI handler -//! - 3: Hard fault handler -//! -//! \param ui32Interrupt specifies the index in the vector table to read priority of. -//! - See \ref IntPrioritySet() for list of valid arguments. -//! -//! \return Returns the interrupt priority: -//! - \ref INT_PRI_LEVEL0 : Highest priority. -//! - \ref INT_PRI_LEVEL1 -//! - \ref INT_PRI_LEVEL2 -//! - \ref INT_PRI_LEVEL3 -//! - \ref INT_PRI_LEVEL4 -//! - \ref INT_PRI_LEVEL5 -//! - \ref INT_PRI_LEVEL6 -//! - \ref INT_PRI_LEVEL7 : Lowest priority. -// -//***************************************************************************** -extern int32_t IntPriorityGet(uint32_t ui32Interrupt); - -//***************************************************************************** -// -//! \brief Enables an interrupt or system exception. -//! -//! This function enables the specified interrupt in the interrupt controller. -//! -//! \note If a fault condition occurs while the corresponding system exception -//! is disabled, the fault is treated as a Hard Fault. -//! -//! \param ui32Interrupt specifies the index in the vector table to enable. -//! - System exceptions: -//! - INT_MEMMANAGE_FAULT -//! - INT_BUS_FAULT -//! - INT_USAGE_FAULT -//! - INT_SYSTICK -//! - Interrupts: -//! - INT_AON_GPIO_EDGE -//! - INT_I2C_IRQ -//! - INT_RFC_CPE_1 -//! - INT_PKA_IRQ -//! - INT_AON_RTC_COMB -//! - INT_UART0_COMB -//! - INT_AUX_SWEV0 -//! - INT_SSI0_COMB -//! - INT_SSI1_COMB -//! - INT_RFC_CPE_0 -//! - INT_RFC_HW_COMB -//! - INT_RFC_CMD_ACK -//! - INT_I2S_IRQ -//! - INT_AUX_SWEV1 -//! - INT_WDT_IRQ -//! - INT_GPT0A -//! - INT_GPT0B -//! - INT_GPT1A -//! - INT_GPT1B -//! - INT_GPT2A -//! - INT_GPT2B -//! - INT_GPT3A -//! - INT_GPT3B -//! - INT_CRYPTO_RESULT_AVAIL_IRQ -//! - INT_DMA_DONE_COMB -//! - INT_DMA_ERR -//! - INT_FLASH -//! - INT_SWEV0 -//! - INT_AUX_COMB -//! - INT_AON_PROG0 -//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) -//! - INT_AUX_COMPA -//! - INT_AUX_ADC_IRQ -//! - INT_TRNG_IRQ -//! - INT_OSC_COMB -//! - INT_AUX_TIMER2_EV0 -//! - INT_UART1_COMB -//! - INT_BATMON_COMB -//! -//! \return None -//! -//! \sa \ref IntDisable() -// -//***************************************************************************** -extern void IntEnable(uint32_t ui32Interrupt); - -//***************************************************************************** -// -//! \brief Disables an interrupt or system exception. -//! -//! This function disables the specified interrupt in the interrupt controller. -//! -//! \param ui32Interrupt specifies the index in the vector table to disable. -//! - See \ref IntEnable() for list of valid arguments. -//! -//! \return None -//! -//! \sa \ref IntEnable() -// -//***************************************************************************** -extern void IntDisable(uint32_t ui32Interrupt); - -//***************************************************************************** -// -//! \brief Pends an interrupt. -//! -//! This function pends the specified interrupt in the interrupt controller. -//! This causes the interrupt controller to execute the corresponding interrupt -//! handler at the next available time, based on the current interrupt state -//! priorities. -//! -//! This interrupt controller automatically clears the pending interrupt once the -//! interrupt handler is executed. -//! -//! \param ui32Interrupt specifies the index in the vector table to pend. -//! - System exceptions: -//! - INT_NMI_FAULT -//! - INT_PENDSV -//! - INT_SYSTICK -//! - Interrupts: -//! - INT_AON_GPIO_EDGE -//! - INT_I2C_IRQ -//! - INT_RFC_CPE_1 -//! - INT_PKA_IRQ -//! - INT_AON_RTC_COMB -//! - INT_UART0_COMB -//! - INT_AUX_SWEV0 -//! - INT_SSI0_COMB -//! - INT_SSI1_COMB -//! - INT_RFC_CPE_0 -//! - INT_RFC_HW_COMB -//! - INT_RFC_CMD_ACK -//! - INT_I2S_IRQ -//! - INT_AUX_SWEV1 -//! - INT_WDT_IRQ -//! - INT_GPT0A -//! - INT_GPT0B -//! - INT_GPT1A -//! - INT_GPT1B -//! - INT_GPT2A -//! - INT_GPT2B -//! - INT_GPT3A -//! - INT_GPT3B -//! - INT_CRYPTO_RESULT_AVAIL_IRQ -//! - INT_DMA_DONE_COMB -//! - INT_DMA_ERR -//! - INT_FLASH -//! - INT_SWEV0 -//! - INT_AUX_COMB -//! - INT_AON_PROG0 -//! - INT_PROG0 (Programmable interrupt, see \ref EventRegister()) -//! - INT_AUX_COMPA -//! - INT_AUX_ADC_IRQ -//! - INT_TRNG_IRQ -//! - INT_OSC_COMB -//! - INT_AUX_TIMER2_EV0 -//! - INT_UART1_COMB -//! - INT_BATMON_COMB -//! -//! \return None -//! -//! \sa \ref IntEnable() -// -//***************************************************************************** -extern void IntPendSet(uint32_t ui32Interrupt); - -//***************************************************************************** -// -//! \brief Checks if an interrupt is pending. -//! -//! This function checks the interrupt controller to see if an interrupt is pending. -//! -//! The interrupt must be enabled in order for the corresponding interrupt handler -//! to be executed, so an interrupt can be pending waiting to be enabled or waiting -//! for an interrupt of higher priority to be done executing. -//! -//! \note This function does not support reading pending status for system exceptions -//! (vector table indexes <16). -//! -//! \param ui32Interrupt specifies the index in the vector table to check pending -//! status for. -//! - See \ref IntPendSet() for list of valid arguments (except system exceptions). -//! -//! \return Returns: -//! - \c true : Specified interrupt is pending. -//! - \c false : Specified interrupt is not pending. -// -//***************************************************************************** -extern bool IntPendGet(uint32_t ui32Interrupt); - -//***************************************************************************** -// -//! \brief Unpends an interrupt. -//! -//! This function unpends the specified interrupt in the interrupt controller. -//! This causes any previously generated interrupts that have not been handled yet -//! (due to higher priority interrupts or the interrupt no having been enabled -//! yet) to be discarded. -//! -//! \note It is not possible to unpend the NMI because it takes effect -//! immediately when being pended. -//! -//! \param ui32Interrupt specifies the index in the vector table to unpend. -//! - See \ref IntPendSet() for list of valid arguments (except NMI). -//! -//! \return None -// -//***************************************************************************** -extern void IntPendClear(uint32_t ui32Interrupt); - -//***************************************************************************** -// -//! \brief Enables the CPU interrupt. -//! -//! Allows the CPU to respond to interrupts. -//! -//! \return Returns: -//! - \c true : Interrupts were disabled and are now enabled. -//! - \c false : Interrupts were already enabled when the function was called. -// -//***************************************************************************** -__STATIC_INLINE bool -IntMasterEnable(void) -{ - // Enable CPU interrupts. - return(CPUcpsie()); -} - -//***************************************************************************** -// -//! \brief Disables the CPU interrupts with configurable priority. -//! -//! Prevents the CPU from receiving interrupts except NMI and hard fault. This -//! does not affect the set of interrupts enabled in the interrupt controller; -//! it just gates the interrupt from the interrupt controller to the CPU. -//! -//! \return Returns: -//! - \c true : Interrupts were already disabled when the function was called. -//! - \c false : Interrupts were enabled and are now disabled. -// -//***************************************************************************** -__STATIC_INLINE bool -IntMasterDisable(void) -{ - // Disable CPU interrupts. - return(CPUcpsid()); -} - -//***************************************************************************** -// -//! \brief Sets the priority masking level. -//! -//! This function sets the interrupt priority masking level so that all -//! interrupts at the specified or lesser priority level are masked. This -//! can be used to globally disable a set of interrupts with priority below -//! a predetermined threshold. A value of 0 disables priority -//! masking. -//! -//! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 will allow interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater will be blocked. -//! The device supports priority levels 0 through 7. -//! -//! \param ui32PriorityMask is the priority level that will be masked. -//! - 0 : Disable priority masking. -//! - 1 : Allow priority 0 interrupts, mask interrupts with priority 1-7. -//! - 2 : Allow priority 0-1 interrupts, mask interrupts with priority 2-7. -//! - 3 : Allow priority 0-2 interrupts, mask interrupts with priority 3-7. -//! - 4 : Allow priority 0-3 interrupts, mask interrupts with priority 4-7. -//! - 5 : Allow priority 0-4 interrupts, mask interrupts with priority 5-7. -//! - 6 : Allow priority 0-5 interrupts, mask interrupts with priority 6-7. -//! - 7 : Allow priority 0-6 interrupts, mask interrupts with priority 7. -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -IntPriorityMaskSet(uint32_t ui32PriorityMask) -{ - CPUbasepriSet(ui32PriorityMask); -} - -//***************************************************************************** -// -//! \brief Gets the priority masking level. -//! -//! This function gets the current setting of the interrupt priority masking -//! level. The value returned is the priority level such that all interrupts -//! of that and lesser priority are masked. A value of 0 means that priority -//! masking is disabled. -//! -//! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 will allow interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater will be blocked. -//! -//! \return Returns the value of the interrupt priority level mask. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -IntPriorityMaskGet(void) -{ - return(CPUbasepriGet()); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_IntRegister - #undef IntRegister - #define IntRegister ROM_IntRegister - #endif - #ifdef ROM_IntUnregister - #undef IntUnregister - #define IntUnregister ROM_IntUnregister - #endif - #ifdef ROM_IntPriorityGroupingSet - #undef IntPriorityGroupingSet - #define IntPriorityGroupingSet ROM_IntPriorityGroupingSet - #endif - #ifdef ROM_IntPriorityGroupingGet - #undef IntPriorityGroupingGet - #define IntPriorityGroupingGet ROM_IntPriorityGroupingGet - #endif - #ifdef ROM_IntPrioritySet - #undef IntPrioritySet - #define IntPrioritySet ROM_IntPrioritySet - #endif - #ifdef ROM_IntPriorityGet - #undef IntPriorityGet - #define IntPriorityGet ROM_IntPriorityGet - #endif - #ifdef ROM_IntEnable - #undef IntEnable - #define IntEnable ROM_IntEnable - #endif - #ifdef ROM_IntDisable - #undef IntDisable - #define IntDisable ROM_IntDisable - #endif - #ifdef ROM_IntPendSet - #undef IntPendSet - #define IntPendSet ROM_IntPendSet - #endif - #ifdef ROM_IntPendGet - #undef IntPendGet - #define IntPendGet ROM_IntPendGet - #endif - #ifdef ROM_IntPendClear - #undef IntPendClear - #define IntPendClear ROM_IntPendClear - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h deleted file mode 100644 index a8a0ad491af..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/interrupt_doc.h +++ /dev/null @@ -1,162 +0,0 @@ -/****************************************************************************** -* Filename: interrupt_doc.h -* Revised: 2017-11-14 15:26:03 +0100 (Tue, 14 Nov 2017) -* Revision: 50272 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup interrupt_api -//! @{ -//! \section sec_interrupt Introduction -//! -//! The interrupt controller API provides a set of functions for dealing with the -//! Nested Vectored Interrupt Controller (NVIC). Functions are provided to enable -//! and disable interrupts, register interrupt handlers, and set the priority of -//! interrupts. -//! -//! The event sources that trigger the interrupt lines in the NVIC are controlled by -//! the MCU event fabric. All event sources are statically connected to the NVIC interrupt lines -//! except one which is programmable. For more information about the MCU event fabric, see the -//! [MCU event fabric API](\ref event_api). -//! -//! \section sec_interrupt_api API -//! -//! Interrupts and system exceptions must be individually enabled and disabled through: -//! - \ref IntEnable() -//! - \ref IntDisable() -//! -//! The global CPU interrupt can be enabled and disabled with the following functions: -//! - \ref IntMasterEnable() -//! - \ref IntMasterDisable() -//! -//! This does not affect the individual interrupt enable states. Masking of the CPU -//! interrupt can be used as a simple critical section (only an NMI can interrupt the -//! CPU while the CPU interrupt is disabled), although masking the CPU -//! interrupt can increase the interrupt response time. -//! -//! It is possible to access the NVIC to see if any interrupts are pending and manually -//! clear pending interrupts which have not yet been serviced or set a specific interrupt as -//! pending to be handled based on its priority. Pending interrupts are cleared automatically -//! when the interrupt is accepted and executed. However, the event source which caused the -//! interrupt might need to be cleared manually to avoid re-triggering the corresponding interrupt. -//! The functions to read, clear, and set pending interrupts are: -//! - \ref IntPendGet() -//! - \ref IntPendClear() -//! - \ref IntPendSet() -//! -//! The interrupt prioritization in the NVIC allows handling of higher priority interrupts -//! before lower priority interrupts, as well as allowing preemption of lower priority interrupt -//! handlers by higher priority interrupts. -//! The device supports eight priority levels from 0 to 7 with 0 being the highest priority. -//! The priority of each interrupt source can be set and examined using: -//! - \ref IntPrioritySet() -//! - \ref IntPriorityGet() -//! -//! Interrupts can be masked based on their priority such that interrupts with the same or lower -//! priority than the mask are effectively disabled. This can be configured with: -//! - \ref IntPriorityMaskSet() -//! - \ref IntPriorityMaskGet() -//! -//! Subprioritization is also possible. Instead of having three bits of preemptable -//! prioritization (eight levels), the NVIC can be configured for 3 - M bits of -//! preemptable prioritization and M bits of subpriority. In this scheme, two -//! interrupts with the same preemptable prioritization but different subpriorities -//! do not cause a preemption. Instead, tail chaining is used to process -//! the two interrupts back-to-back. -//! If two interrupts with the same priority (and subpriority if so configured) are -//! asserted at the same time, the one with the lower interrupt number is -//! processed first. -//! Subprioritization is handled by: -//! - \ref IntPriorityGroupingSet() -//! - \ref IntPriorityGroupingGet() -//! -//! \section sec_interrupt_table Interrupt Vector Table -//! -//! The interrupt vector table can be configured in one of two ways: -//! - Statically (at compile time): Vector table is placed in Flash and each entry has a fixed -//! pointer to an interrupt handler (ISR). -//! - Dynamically (at runtime): Vector table is placed in SRAM and each entry can be changed -//! (registered or unregistered) at runtime. This allows a single interrupt to trigger different -//! interrupt handlers (ISRs) depending on which interrupt handler is registered at the time the -//! System CPU responds to the interrupt. -//! -//! When configured, the interrupts must be explicitly enabled in the NVIC through \ref IntEnable() -//! before the CPU can respond to the interrupt (in addition to any interrupt enabling required -//! within the peripheral). -//! -//! \subsection sec_interrupt_table_static Static Vector Table -//! -//! Static registration of interrupt handlers is accomplished by editing the interrupt handler -//! table in the startup code of the application. Texas Instruments provides startup files for -//! each supported compiler ( \ti_code{startup_.c} ) and these startup files include -//! a default static interrupt vector table. -//! All entries, except ResetISR, are declared as \c extern with weak assignment to a default -//! interrupt handler. This allows the user to declare and define a function (in the user's code) -//! with the same name as an entry in the vector table. At compile time, the linker then replaces -//! the pointer to the default interrupt handler in the vector table with the pointer to the -//! interrupt handler defined by the user. -//! -//! Statically configuring the interrupt table provides the fastest interrupt response time -//! because the stacking operation (a write to SRAM on the data bus) is performed in parallel -//! with the interrupt handler table fetch (a read from Flash on the instruction bus), as well -//! as the prefetch of the interrupt handler (assuming it is also in Flash). -//! -//! \subsection sec_interrupt_table_dynamic Dynamic Vector Table -//! -//! Alternatively, interrupts can be registered in the vector table at runtime, thus dynamically. -//! The dynamic vector table is placed in SRAM and the code can then modify the pointers to -//! interrupt handlers throughout the application. -//! -//! DriverLib uses these two functions to modify the dynamic vector table: -//! - \ref IntRegister() : Write a pointer to an interrupt handler into the vector table. -//! - \ref IntUnregister() : Write pointer to default interrupt handler into the vector table. -//! -//! \note First call to \ref IntRegister() initializes the vector table in SRAM by copying the -//! static vector table from Flash and forcing the NVIC to use the dynamic vector table from -//! this point forward. If using the dynamic vector table it is highly recommended to -//! initialize it during the setup phase of the application. The NVIC uses the static vector -//! table in Flash until the application initializes the dynamic vector table in SRAM. -//! -//! Runtime configuration of interrupts adds a small latency to the interrupt response time -//! because the stacking operation (a write to SRAM on the data bus) and the interrupt handler -//! fetch from the vector table (a read from SRAM on the instruction bus) must be performed -//! sequentially. -//! -//! The dynamic vector table, \ref g_pfnRAMVectors, is placed in SRAM in the section called -//! \c vtable_ram which is a section defined in the linker file. By default the linker file -//! places this section at the start of the SRAM but this is configurable by the user. -//! -//! \warning Runtime configuration of interrupt handlers requires that the interrupt -//! handler table is placed on a 256-byte boundary in SRAM (typically, this is -//! at the beginning of SRAM). Failure to do so results in an incorrect vector -//! address being fetched in response to an interrupt. -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.c deleted file mode 100644 index d92f811064c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.c +++ /dev/null @@ -1,683 +0,0 @@ -/****************************************************************************** -* Filename: ioc.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the IOC. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "ioc.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef IOCPortConfigureSet - #define IOCPortConfigureSet NOROM_IOCPortConfigureSet - #undef IOCPortConfigureGet - #define IOCPortConfigureGet NOROM_IOCPortConfigureGet - #undef IOCIOShutdownSet - #define IOCIOShutdownSet NOROM_IOCIOShutdownSet - #undef IOCIOModeSet - #define IOCIOModeSet NOROM_IOCIOModeSet - #undef IOCIOIntSet - #define IOCIOIntSet NOROM_IOCIOIntSet - #undef IOCIOEvtSet - #define IOCIOEvtSet NOROM_IOCIOEvtSet - #undef IOCIOPortPullSet - #define IOCIOPortPullSet NOROM_IOCIOPortPullSet - #undef IOCIOHystSet - #define IOCIOHystSet NOROM_IOCIOHystSet - #undef IOCIOInputSet - #define IOCIOInputSet NOROM_IOCIOInputSet - #undef IOCIOSlewCtrlSet - #define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet - #undef IOCIODrvStrengthSet - #define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet - #undef IOCIOPortIdSet - #define IOCIOPortIdSet NOROM_IOCIOPortIdSet - #undef IOCIntEnable - #define IOCIntEnable NOROM_IOCIntEnable - #undef IOCIntDisable - #define IOCIntDisable NOROM_IOCIntDisable - #undef IOCPinTypeGpioInput - #define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput - #undef IOCPinTypeGpioOutput - #define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput - #undef IOCPinTypeUart - #define IOCPinTypeUart NOROM_IOCPinTypeUart - #undef IOCPinTypeSsiMaster - #define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster - #undef IOCPinTypeSsiSlave - #define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave - #undef IOCPinTypeI2c - #define IOCPinTypeI2c NOROM_IOCPinTypeI2c - #undef IOCPinTypeAux - #define IOCPinTypeAux NOROM_IOCPinTypeAux -#endif - -//***************************************************************************** -// -// Set the configuration of an IO port -// -//***************************************************************************** -void -IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, - uint32_t ui32IOConfig) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); - - // Get the register address. - ui32Reg = IOC_BASE + ( ui32IOId << 2 ); - - // Configure the port. - HWREG(ui32Reg) = ui32IOConfig | ui32PortId; -} - -//***************************************************************************** -// -// Get the configuration of an IO port -// -//***************************************************************************** -uint32_t -IOCPortConfigureGet(uint32_t ui32IOId) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - - // Get the register address. - ui32Reg = IOC_BASE + ( ui32IOId << 2 ); - - // Return the IO configuration. - return HWREG(ui32Reg); -} - -//***************************************************************************** -// -// Set wake-up on an IO port -// -//***************************************************************************** -void -IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown) -{ - uint32_t ui32Reg; - uint32_t ui32Config; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32IOShutdown == IOC_NO_WAKE_UP) || - (ui32IOShutdown == IOC_WAKE_ON_LOW) || - (ui32IOShutdown == IOC_WAKE_ON_HIGH)); - - // Get the register address. - ui32Reg = IOC_BASE + ( ui32IOId << 2 ); - - // Configure the IO. - ui32Config = HWREG(ui32Reg); - ui32Config &= ~IOC_IOCFG0_WU_CFG_M; - HWREG(ui32Reg) = ui32Config | ui32IOShutdown; -} - - -//***************************************************************************** -// -// Set the IO Mode of an IO Port -// -//***************************************************************************** -void -IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode) -{ - uint32_t ui32Reg; - uint32_t ui32Config; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32IOMode == IOC_IOMODE_NORMAL) || - (ui32IOMode == IOC_IOMODE_INV) || - (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_NORMAL) || - (ui32IOMode == IOC_IOMODE_OPEN_DRAIN_INV) || - (ui32IOMode == IOC_IOMODE_OPEN_SRC_NORMAL) || - (ui32IOMode == IOC_IOMODE_OPEN_SRC_INV)); - - // Get the register address. - ui32Reg = IOC_BASE + ( ui32IOId << 2 ); - - // Configure the IO. - ui32Config = HWREG(ui32Reg); - ui32Config &= ~IOC_IOCFG0_IOMODE_M; - HWREG(ui32Reg) = ui32Config | ui32IOMode; -} - -//***************************************************************************** -// -// Setup interrupt detection on an IO Port -// -//***************************************************************************** -void -IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32Int == IOC_INT_ENABLE) || - (ui32Int == IOC_INT_DISABLE)); - ASSERT((ui32EdgeDet == IOC_NO_EDGE) || - (ui32EdgeDet == IOC_FALLING_EDGE) || - (ui32EdgeDet == IOC_RISING_EDGE) || - (ui32EdgeDet == IOC_BOTH_EDGES)); - - // Get the register address. - ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); - - // Configure the IO. - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~(IOC_IOCFG0_EDGE_IRQ_EN | IOC_IOCFG0_EDGE_DET_M); - HWREG(ui32IOReg) = ui32Config | ((ui32Int ? IOC_IOCFG0_EDGE_IRQ_EN : 0) | ui32EdgeDet); -} - -//***************************************************************************** -// -// Setup event generation on IO edge detection -// -//***************************************************************************** -void -IOCIOEvtSet(uint32_t ui32IOId, uint32_t ui32Evt) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - ASSERT( (ui32Evt & ~(IOC_IOCFG0_IOEV_AON_PROG2_EN_M | - IOC_IOCFG0_IOEV_AON_PROG1_EN_M | - IOC_IOCFG0_IOEV_AON_PROG0_EN_M | - IOC_IOCFG0_IOEV_RTC_EN_M | - IOC_IOCFG0_IOEV_MCU_WU_EN_M) ) == 0x00000000); - - // Get the register address. - ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); - - // Read current configuration. - ui32Config = HWREG(ui32IOReg); - - // Disable generation of all events. - ui32Config &= ~(IOC_IOCFG0_IOEV_AON_PROG2_EN_M | - IOC_IOCFG0_IOEV_AON_PROG1_EN_M | - IOC_IOCFG0_IOEV_AON_PROG0_EN_M | - IOC_IOCFG0_IOEV_RTC_EN_M | - IOC_IOCFG0_IOEV_MCU_WU_EN_M); - - // Enable the required events. - HWREG(ui32IOReg) = ui32Config | ui32Evt; -} - -//***************************************************************************** -// -// Set the pull on an IO port -// -//***************************************************************************** -void -IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // Check the argument. - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32Pull == IOC_NO_IOPULL) || - (ui32Pull == IOC_IOPULL_UP) || - (ui32Pull == IOC_IOPULL_DOWN)); - - // Get the register address. - ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); - - // Configure the IO. - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~IOC_IOCFG0_PULL_CTL_M; - HWREG(ui32IOReg) = ui32Config | ui32Pull; -} - -//***************************************************************************** -// -// Configure hysteresis on and IO port -// -//***************************************************************************** -void -IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32Hysteresis == IOC_HYST_ENABLE) || - (ui32Hysteresis == IOC_HYST_DISABLE)); - - // Get the register address. - ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); - - // Configure the IO. - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~IOC_IOCFG0_HYST_EN; - HWREG(ui32IOReg) = ui32Config | ui32Hysteresis; -} - -//***************************************************************************** -// -// Enable/disable IO port as input -// -//***************************************************************************** -void -IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32Input == IOC_INPUT_ENABLE) || - (ui32Input == IOC_INPUT_DISABLE)); - - // Get the register address. - ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); - - // Configure the IO. - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~IOC_IOCFG0_IE; - HWREG(ui32IOReg) = ui32Config | ui32Input; -} - -//***************************************************************************** -// -// Enable/disable the slew control on an IO port -// -//***************************************************************************** -void -IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32SlewEnable == IOC_SLEW_ENABLE) || - (ui32SlewEnable == IOC_SLEW_DISABLE)); - - // Get the register address. - ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); - - // Configure the IO. - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~IOC_IOCFG0_SLEW_RED; - HWREG(ui32IOReg) = ui32Config | ui32SlewEnable; -} - -//***************************************************************************** -// -// Configure the drive strength and maximum current of an IO port -// -//***************************************************************************** -void -IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, - uint32_t ui32DrvStrength) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - ASSERT((ui32IOCurrent == IOC_CURRENT_2MA) || - (ui32IOCurrent == IOC_CURRENT_4MA) || - (ui32IOCurrent == IOC_CURRENT_8MA)); - ASSERT((ui32DrvStrength == IOC_STRENGTH_MIN) || - (ui32DrvStrength == IOC_STRENGTH_MAX) || - (ui32DrvStrength == IOC_STRENGTH_MED) || - (ui32DrvStrength == IOC_STRENGTH_AUTO)); - - // Get the register address. - ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); - - // Configure the IO. - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~(IOC_IOCFG0_IOCURR_M | IOC_IOCFG0_IOSTR_M); - HWREG(ui32IOReg) = ui32Config | (ui32IOCurrent | ui32DrvStrength); -} - -//***************************************************************************** -// -// Setup the Port ID for this IO -// -//***************************************************************************** -void -IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - ASSERT(ui32PortId <= IOC_PORT_RFC_GPI1); - - // Get the register address. - ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); - - // Configure the IO. - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~IOC_IOCFG0_PORT_ID_M; - HWREG(ui32IOReg) = ui32Config | ui32PortId; -} - -//***************************************************************************** -// -// Enables individual IO edge detect interrupt -// -//***************************************************************************** -void -IOCIntEnable(uint32_t ui32IOId) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - - // Get the register address. - ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); - - // Enable the specified interrupt. - ui32Config = HWREG(ui32IOReg); - ui32Config |= IOC_IOCFG0_EDGE_IRQ_EN; - HWREG(ui32IOReg) = ui32Config; -} - -//***************************************************************************** -// -// Disables individual IO edge interrupt sources -// -//***************************************************************************** -void -IOCIntDisable(uint32_t ui32IOId) -{ - uint32_t ui32IOReg; - uint32_t ui32Config; - - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - - // Get the register address. - ui32IOReg = IOC_BASE + ( ui32IOId << 2 ); - - // Disable the specified interrupt. - ui32Config = HWREG(ui32IOReg); - ui32Config &= ~IOC_IOCFG0_EDGE_IRQ_EN; - HWREG(ui32IOReg) = ui32Config; -} - -//***************************************************************************** -// -// Setup an IO for standard GPIO input -// -//***************************************************************************** -void -IOCPinTypeGpioInput(uint32_t ui32IOId) -{ - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - - // Setup the IO for standard input. - IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_INPUT); - - // Enable input mode in the GPIO module. - GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_DISABLE); -} - -//***************************************************************************** -// -// Setup an IO for standard GPIO output -// -//***************************************************************************** -void -IOCPinTypeGpioOutput(uint32_t ui32IOId) -{ - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - - // Setup the IO for standard input. - IOCPortConfigureSet(ui32IOId, IOC_PORT_GPIO, IOC_STD_OUTPUT); - - // Enable output mode in the GPIO module. - GPIO_setOutputEnableDio(ui32IOId, GPIO_OUTPUT_ENABLE); -} - -//***************************************************************************** -// -// Configure a set of IOs for standard UART peripheral control -// -//***************************************************************************** -void -IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, - uint32_t ui32Cts, uint32_t ui32Rts) -{ - // Check the arguments. - ASSERT(ui32Base == UART0_BASE); - ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); - ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); - ASSERT((ui32Cts <= IOID_31) || (ui32Cts == IOID_UNUSED)); - ASSERT((ui32Rts <= IOID_31) || (ui32Rts == IOID_UNUSED)); - - // Setup the IOs in the desired configuration. - if(ui32Rx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_UART0_RX, IOC_STD_INPUT); - } - if(ui32Tx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_UART0_TX, IOC_STD_OUTPUT); - } - if(ui32Cts != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Cts, IOC_PORT_MCU_UART0_CTS, IOC_STD_INPUT); - } - if(ui32Rts != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rts, IOC_PORT_MCU_UART0_RTS, IOC_STD_OUTPUT); - } -} - -//***************************************************************************** -// -// Configure a set of IOs for standard SSI peripheral master control -// -//***************************************************************************** -void -IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, - uint32_t ui32Tx, uint32_t ui32Fss, - uint32_t ui32Clk) -{ - // Check the arguments. - ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); - ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); - ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); - ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); - ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); - - // Setup the IOs in the desired configuration. - if(ui32Base == SSI0_BASE) - { - if(ui32Rx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); - } - if(ui32Tx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); - } - if(ui32Fss != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_OUTPUT); - } - if(ui32Clk != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_OUTPUT); - } - } - else - { - if(ui32Rx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); - } - if(ui32Tx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); - } - if(ui32Fss != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_OUTPUT); - } - if(ui32Clk != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_OUTPUT); - } - } -} - -//***************************************************************************** -// -// Configure a set of IOs for standard SSI peripheral slave control -// -//***************************************************************************** -void -IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, - uint32_t ui32Tx, uint32_t ui32Fss, - uint32_t ui32Clk) -{ - // Check the arguments. - ASSERT((ui32Base == SSI0_BASE) || (ui32Base == SSI1_BASE)); - ASSERT((ui32Rx <= IOID_31) || (ui32Rx == IOID_UNUSED)); - ASSERT((ui32Tx <= IOID_31) || (ui32Tx == IOID_UNUSED)); - ASSERT((ui32Fss <= IOID_31) || (ui32Fss == IOID_UNUSED)); - ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); - - // Setup the IOs in the desired configuration. - if(ui32Base == SSI0_BASE) - { - if(ui32Rx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI0_RX, IOC_STD_INPUT); - } - if(ui32Tx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI0_TX, IOC_STD_OUTPUT); - } - if(ui32Fss != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI0_FSS, IOC_STD_INPUT); - } - if(ui32Clk != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI0_CLK, IOC_STD_INPUT); - } - } - else - { - if(ui32Rx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Rx, IOC_PORT_MCU_SSI1_RX, IOC_STD_INPUT); - } - if(ui32Tx != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Tx, IOC_PORT_MCU_SSI1_TX, IOC_STD_OUTPUT); - } - if(ui32Fss != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Fss, IOC_PORT_MCU_SSI1_FSS, IOC_STD_INPUT); - } - if(ui32Clk != IOID_UNUSED) - { - IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_SSI1_CLK, IOC_STD_INPUT); - } - } -} - -//***************************************************************************** -// -// Configure a set of IOs for standard I2C peripheral control -// -//***************************************************************************** -void -IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk) -{ - uint32_t ui32IOConfig; - - // Check the arguments. - ASSERT((ui32Data <= IOID_31) || (ui32Data == IOID_UNUSED)); - ASSERT((ui32Clk <= IOID_31) || (ui32Clk == IOID_UNUSED)); - - // Define the IO configuration parameters. - ui32IOConfig = IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | IOC_IOPULL_UP | - IOC_SLEW_DISABLE | IOC_HYST_DISABLE | IOC_NO_EDGE | - IOC_INT_DISABLE | IOC_IOMODE_OPEN_DRAIN_NORMAL | - IOC_NO_WAKE_UP | IOC_INPUT_ENABLE; - - // Setup the IOs in the desired configuration. - IOCPortConfigureSet(ui32Data, IOC_PORT_MCU_I2C_MSSDA, ui32IOConfig); - IOCPortConfigureSet(ui32Clk, IOC_PORT_MCU_I2C_MSSCL, ui32IOConfig); -} - - -//***************************************************************************** -// -// Configure an IO for AUX control -// -//***************************************************************************** -void -IOCPinTypeAux(uint32_t ui32IOId) -{ - // Check the arguments. - ASSERT((ui32IOId <= IOID_31) || (ui32IOId == IOID_UNUSED)); - - // Setup the IO. - IOCPortConfigureSet(ui32IOId, IOC_PORT_AUX_IO, IOC_STD_INPUT); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h deleted file mode 100644 index 6e4caaab710..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h +++ /dev/null @@ -1,1225 +0,0 @@ -/****************************************************************************** -* Filename: ioc.h -* Revised: 2017-11-02 14:16:14 +0100 (Thu, 02 Nov 2017) -* Revision: 50156 -* -* Description: Defines and prototypes for the IO Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup ioc_api -//! @{ -// -//***************************************************************************** - -#ifndef __IOC_H__ -#define __IOC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ioc.h" -#include "../inc/hw_ints.h" -#include "interrupt.h" -#include "debug.h" -#include "gpio.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define IOCPortConfigureSet NOROM_IOCPortConfigureSet - #define IOCPortConfigureGet NOROM_IOCPortConfigureGet - #define IOCIOShutdownSet NOROM_IOCIOShutdownSet - #define IOCIOModeSet NOROM_IOCIOModeSet - #define IOCIOIntSet NOROM_IOCIOIntSet - #define IOCIOEvtSet NOROM_IOCIOEvtSet - #define IOCIOPortPullSet NOROM_IOCIOPortPullSet - #define IOCIOHystSet NOROM_IOCIOHystSet - #define IOCIOInputSet NOROM_IOCIOInputSet - #define IOCIOSlewCtrlSet NOROM_IOCIOSlewCtrlSet - #define IOCIODrvStrengthSet NOROM_IOCIODrvStrengthSet - #define IOCIOPortIdSet NOROM_IOCIOPortIdSet - #define IOCIntEnable NOROM_IOCIntEnable - #define IOCIntDisable NOROM_IOCIntDisable - #define IOCPinTypeGpioInput NOROM_IOCPinTypeGpioInput - #define IOCPinTypeGpioOutput NOROM_IOCPinTypeGpioOutput - #define IOCPinTypeUart NOROM_IOCPinTypeUart - #define IOCPinTypeSsiMaster NOROM_IOCPinTypeSsiMaster - #define IOCPinTypeSsiSlave NOROM_IOCPinTypeSsiSlave - #define IOCPinTypeI2c NOROM_IOCPinTypeI2c - #define IOCPinTypeAux NOROM_IOCPinTypeAux -#endif - -//***************************************************************************** -// -// Number of IOs (max. total of 32) -// -//***************************************************************************** -#define NUM_IO_MAX 32 - -//***************************************************************************** -// -// The following fields are IO Id for the IOC module -// -//***************************************************************************** -#define IOID_0 0x00000000 // IO Id 0 -#define IOID_1 0x00000001 // IO Id 1 -#define IOID_2 0x00000002 // IO Id 2 -#define IOID_3 0x00000003 // IO Id 3 -#define IOID_4 0x00000004 // IO Id 4 -#define IOID_5 0x00000005 // IO Id 5 -#define IOID_6 0x00000006 // IO Id 6 -#define IOID_7 0x00000007 // IO Id 7 -#define IOID_8 0x00000008 // IO Id 8 -#define IOID_9 0x00000009 // IO Id 9 -#define IOID_10 0x0000000A // IO Id 10 -#define IOID_11 0x0000000B // IO Id 11 -#define IOID_12 0x0000000C // IO Id 12 -#define IOID_13 0x0000000D // IO Id 13 -#define IOID_14 0x0000000E // IO Id 14 -#define IOID_15 0x0000000F // IO Id 15 -#define IOID_16 0x00000010 // IO Id 16 -#define IOID_17 0x00000011 // IO Id 17 -#define IOID_18 0x00000012 // IO Id 18 -#define IOID_19 0x00000013 // IO Id 19 -#define IOID_20 0x00000014 // IO Id 20 -#define IOID_21 0x00000015 // IO Id 21 -#define IOID_22 0x00000016 // IO Id 22 -#define IOID_23 0x00000017 // IO Id 23 -#define IOID_24 0x00000018 // IO Id 24 -#define IOID_25 0x00000019 // IO Id 25 -#define IOID_26 0x0000001A // IO Id 26 -#define IOID_27 0x0000001B // IO Id 27 -#define IOID_28 0x0000001C // IO Id 28 -#define IOID_29 0x0000001D // IO Id 29 -#define IOID_30 0x0000001E // IO Id 30 -#define IOID_31 0x0000001F // IO Id 31 -#define IOID_UNUSED 0xFFFFFFFF // Unused IO Id - -#define IOC_IOID_MASK 0x000000FF // IOC IO Id bit mask - -//***************************************************************************** -// -// Number of IO ports -// -//***************************************************************************** -#define NUM_IO_PORTS 56 - -//***************************************************************************** -// -// IOC Peripheral Port Mapping -// -//***************************************************************************** -#define IOC_PORT_GPIO 0x00000000 // Default general purpose IO usage -#define IOC_PORT_AON_CLK32K 0x00000007 // AON External 32kHz clock -#define IOC_PORT_AUX_IO 0x00000008 // AUX IO Pin -#define IOC_PORT_MCU_SSI0_RX 0x00000009 // MCU SSI0 Receive Pin -#define IOC_PORT_MCU_SSI0_TX 0x0000000A // MCU SSI0 Transmit Pin -#define IOC_PORT_MCU_SSI0_FSS 0x0000000B // MCU SSI0 FSS Pin -#define IOC_PORT_MCU_SSI0_CLK 0x0000000C // MCU SSI0 Clock Pin -#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D // MCU I2C Data Pin -#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E // MCU I2C Clock Pin -#define IOC_PORT_MCU_UART0_RX 0x0000000F // MCU UART0 Receive Pin -#define IOC_PORT_MCU_UART0_TX 0x00000010 // MCU UART0 Transmit Pin -#define IOC_PORT_MCU_UART0_CTS 0x00000011 // MCU UART0 Clear To Send Pin -#define IOC_PORT_MCU_UART0_RTS 0x00000012 // MCU UART0 Request To Send Pin -#define IOC_PORT_MCU_UART1_RX 0x00000013 // MCU UART1 Receive Pin -#define IOC_PORT_MCU_UART1_TX 0x00000014 // MCU UART1 Transmit Pin -#define IOC_PORT_MCU_UART1_CTS 0x00000015 // MCU UART1 Clear To Send Pin -#define IOC_PORT_MCU_UART1_RTS 0x00000016 // MCU UART1 Request To Send Pin -#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 // MCU PORT EVENT 0 -#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 // MCU PORT EVENT 1 -#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 // MCU PORT EVENT 2 -#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A // MCU PORT EVENT 3 -#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B // MCU PORT EVENT 4 -#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C // MCU PORT EVENT 5 -#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D // MCU PORT EVENT 6 -#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E // MCU PORT EVENT 7 -#define IOC_PORT_MCU_SWV 0x00000020 // Serial Wire Viewer -#define IOC_PORT_MCU_SSI1_RX 0x00000021 // MCU SSI1 Receive Pin -#define IOC_PORT_MCU_SSI1_TX 0x00000022 // MCU SSI1 Transmit Pin -#define IOC_PORT_MCU_SSI1_FSS 0x00000023 // MCU SSI1 FSS Pin -#define IOC_PORT_MCU_SSI1_CLK 0x00000024 // MCU SSI1 Clock Pin -#define IOC_PORT_MCU_I2S_AD0 0x00000025 // MCU I2S Data Pin 0 -#define IOC_PORT_MCU_I2S_AD1 0x00000026 // MCU I2S Data Pin 1 -#define IOC_PORT_MCU_I2S_WCLK 0x00000027 // MCU I2S Frame/Word Clock -#define IOC_PORT_MCU_I2S_BCLK 0x00000028 // MCU I2S Bit Clock -#define IOC_PORT_MCU_I2S_MCLK 0x00000029 // MCU I2S Master clock 2 -#define IOC_PORT_RFC_TRC 0x0000002E // RF Core Tracer -#define IOC_PORT_RFC_GPO0 0x0000002F // RC Core Data Out Pin 0 -#define IOC_PORT_RFC_GPO1 0x00000030 // RC Core Data Out Pin 1 -#define IOC_PORT_RFC_GPO2 0x00000031 // RC Core Data Out Pin 2 -#define IOC_PORT_RFC_GPO3 0x00000032 // RC Core Data Out Pin 3 -#define IOC_PORT_RFC_GPI0 0x00000033 // RC Core Data In Pin 0 -#define IOC_PORT_RFC_GPI1 0x00000034 // RC Core Data In Pin 1 -#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 // RF Core SMI Data Link Out -#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 // RF Core SMI Data Link in -#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 // RF Core SMI Command Link Out -#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 // RF Core SMI Command Link In - -//***************************************************************************** -// -// Defines for enabling/disabling an IO -// -//***************************************************************************** -#define IOC_SLEW_ENABLE 0x00001000 -#define IOC_SLEW_DISABLE 0x00000000 -#define IOC_INPUT_ENABLE 0x20000000 -#define IOC_INPUT_DISABLE 0x00000000 -#define IOC_HYST_ENABLE 0x40000000 -#define IOC_HYST_DISABLE 0x00000000 - -//***************************************************************************** -// -// Defines that can be used to set the shutdown mode of an IO -// -//***************************************************************************** -#define IOC_NO_WAKE_UP 0x00000000 -#define IOC_WAKE_ON_LOW 0x10000000 -#define IOC_WAKE_ON_HIGH 0x18000000 - -//***************************************************************************** -// -// Defines that can be used to set the IO Mode of an IO -// -//***************************************************************************** -#define IOC_IOMODE_NORMAL 0x00000000 // Normal Input/Output -#define IOC_IOMODE_INV 0x01000000 // Inverted Input/Output -#define IOC_IOMODE_OPEN_DRAIN_NORMAL \ - 0x04000000 // Open Drain, Normal Input/Output -#define IOC_IOMODE_OPEN_DRAIN_INV \ - 0x05000000 // Open Drain, Inverted - // Input/Output -#define IOC_IOMODE_OPEN_SRC_NORMAL \ - 0x06000000 // Open Source, Normal Input/Output -#define IOC_IOMODE_OPEN_SRC_INV \ - 0x07000000 // Open Source, Inverted - // Input/Output - -//***************************************************************************** -// -// Defines that can be used to set the edge detection on an IO -// -//***************************************************************************** -#define IOC_NO_EDGE 0x00000000 // No edge detection -#define IOC_FALLING_EDGE 0x00010000 // Edge detection on falling edge -#define IOC_RISING_EDGE 0x00020000 // Edge detection on rising edge -#define IOC_BOTH_EDGES 0x00030000 // Edge detection on both edges -#define IOC_INT_ENABLE 0x00040000 // Enable interrupt on edge detect -#define IOC_INT_DISABLE 0x00000000 // Disable interrupt on edge detect -#define IOC_INT_M 0x00070000 // Int config mask - -//***************************************************************************** -// -// Defines that be used to set pull on an IO -// -//***************************************************************************** -#define IOC_NO_IOPULL 0x00006000 // No IO pull -#define IOC_IOPULL_UP 0x00004000 // Pull up -#define IOC_IOPULL_DOWN 0x00002000 // Pull down -#define IOC_IOPULL_M 0x00006000 // Pull config mask -#define IOC_IOPULL_M 0x00006000 - -//***************************************************************************** -// -// Defines that can be used to select the drive strength of an IO -// -//***************************************************************************** -#define IOC_CURRENT_2MA 0x00000000 // 2mA drive strength -#define IOC_CURRENT_4MA 0x00000400 // 4mA drive strength -#define IOC_CURRENT_8MA 0x00000800 // 4 or 8mA drive strength - -#define IOC_STRENGTH_AUTO 0x00000000 // Automatic Drive Strength - // (2/4/8 mA @ VVDS) -#define IOC_STRENGTH_MAX 0x00000300 // Maximum Drive Strength - // (2/4/8 mA @ 1.8V) -#define IOC_STRENGTH_MED 0x00000200 // Medium Drive Strength - // (2/4/8 mA @ 2.5V) -#define IOC_STRENGTH_MIN 0x00000100 // Minimum Drive Strength - // (2/4/8 mA @ 3.3V) - -//***************************************************************************** -// -// Defines that can be used to enable event generation on edge detect -// -//***************************************************************************** -#define IOC_EVT_AON_PROG2_DISABLE 0x00000000 -#define IOC_EVT_AON_PROG2_ENABLE 0x00800000 -#define IOC_EVT_AON_PROG1_DISABLE 0x00000000 -#define IOC_EVT_AON_PROG1_ENABLE 0x00400000 -#define IOC_EVT_AON_PROG0_DISABLE 0x00000000 -#define IOC_EVT_AON_PROG0_ENABLE 0x00200000 -#define IOC_EVT_RTC_DISABLE 0x00000000 -#define IOC_EVT_RTC_ENABLE 0x00000080 -#define IOC_EVT_MCU_WU_DISABLE 0x00000000 -#define IOC_EVT_MCU_WU_ENABLE 0x00000040 - -//***************************************************************************** -// -// Defines for standard IO setup -// -//***************************************************************************** -#define IOC_STD_INPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ - IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ - IOC_HYST_DISABLE | IOC_NO_EDGE | \ - IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ - IOC_NO_WAKE_UP | IOC_INPUT_ENABLE ) -#define IOC_STD_OUTPUT (IOC_CURRENT_2MA | IOC_STRENGTH_AUTO | \ - IOC_NO_IOPULL | IOC_SLEW_DISABLE | \ - IOC_HYST_DISABLE | IOC_NO_EDGE | \ - IOC_INT_DISABLE | IOC_IOMODE_NORMAL | \ - IOC_NO_WAKE_UP | IOC_INPUT_DISABLE ) - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Set the configuration of an IO port. -//! -//! This function is used to configure the functionality of an IO. -//! -//! The \c ui32IOId parameter specifies which IO to configure. -//! -//! The \c ui32PortId parameter specifies which functional peripheral to hook -//! up to this IO. -//! -//! The \c ui32IOConfig parameter consists of a bitwise OR'ed value of all -//! the available configuration modes -//! -//! \note All IO Ports are tied to a specific functionality in a sub module -//! except for the \ref IOC_PORT_AUX_IO. Each of the IOs in the AUX domain are -//! hardcoded to a specific IO. When enabling one or more pins for the AUX -//! domain, they should all be configured to using \ref IOC_PORT_AUX_IO. -//! -//! \param ui32IOId defines the IO to configure and must be one of the following: -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! \param ui32PortId selects the functional IO port to connect. -//! The available IO ports are: -//! - \ref IOC_PORT_GPIO -//! - \ref IOC_PORT_AON_CLK32K -//! - \ref IOC_PORT_AUX_IO -//! - \ref IOC_PORT_MCU_SSI0_RX -//! - \ref IOC_PORT_MCU_SSI0_TX -//! - \ref IOC_PORT_MCU_SSI0_FSS -//! - \ref IOC_PORT_MCU_SSI0_CLK -//! - \ref IOC_PORT_MCU_I2C_MSSDA -//! - \ref IOC_PORT_MCU_I2C_MSSCL -//! - \ref IOC_PORT_MCU_UART0_RX -//! - \ref IOC_PORT_MCU_UART0_TX -//! - \ref IOC_PORT_MCU_UART0_CTS -//! - \ref IOC_PORT_MCU_UART0_RTS -//! - \ref IOC_PORT_MCU_UART1_RX -//! - \ref IOC_PORT_MCU_UART1_TX -//! - \ref IOC_PORT_MCU_UART1_CTS -//! - \ref IOC_PORT_MCU_UART1_RTS -//! - \ref IOC_PORT_MCU_PORT_EVENT0 -//! - \ref IOC_PORT_MCU_PORT_EVENT1 -//! - \ref IOC_PORT_MCU_PORT_EVENT2 -//! - \ref IOC_PORT_MCU_PORT_EVENT3 -//! - \ref IOC_PORT_MCU_PORT_EVENT4 -//! - \ref IOC_PORT_MCU_PORT_EVENT5 -//! - \ref IOC_PORT_MCU_PORT_EVENT6 -//! - \ref IOC_PORT_MCU_PORT_EVENT7 -//! - \ref IOC_PORT_MCU_SWV -//! - \ref IOC_PORT_MCU_SSI1_RX -//! - \ref IOC_PORT_MCU_SSI1_TX -//! - \ref IOC_PORT_MCU_SSI1_FSS -//! - \ref IOC_PORT_MCU_SSI1_CLK -//! - \ref IOC_PORT_MCU_I2S_AD0 -//! - \ref IOC_PORT_MCU_I2S_AD1 -//! - \ref IOC_PORT_MCU_I2S_WCLK -//! - \ref IOC_PORT_MCU_I2S_BCLK -//! - \ref IOC_PORT_MCU_I2S_MCLK -//! - \ref IOC_PORT_RFC_TRC -//! - \ref IOC_PORT_RFC_GPO0 -//! - \ref IOC_PORT_RFC_GPO1 -//! - \ref IOC_PORT_RFC_GPO2 -//! - \ref IOC_PORT_RFC_GPO3 -//! - \ref IOC_PORT_RFC_GPI0 -//! - \ref IOC_PORT_RFC_GPI1 -//! \param ui32IOConfig is the IO configuration consisting of -//! the bitwise OR of all configuration modes: -//! - Input/output mode: -//! - \ref IOC_IOMODE_NORMAL -//! - \ref IOC_IOMODE_INV -//! - \ref IOC_IOMODE_OPEN_DRAIN_NORMAL -//! - \ref IOC_IOMODE_OPEN_DRAIN_INV -//! - \ref IOC_IOMODE_OPEN_SRC_NORMAL -//! - \ref IOC_IOMODE_OPEN_SRC_INV -//! - Wake-up mode (from shutdown): -//! - \ref IOC_NO_WAKE_UP -//! - \ref IOC_WAKE_ON_LOW -//! - \ref IOC_WAKE_ON_HIGH -//! - Edge detection mode: -//! - \ref IOC_NO_EDGE -//! - \ref IOC_FALLING_EDGE -//! - \ref IOC_RISING_EDGE -//! - \ref IOC_BOTH_EDGES -//! - Interrupt mode on edge detection: -//! - \ref IOC_INT_ENABLE -//! - \ref IOC_INT_DISABLE -//! - Pull mode: -//! - \ref IOC_NO_IOPULL -//! - \ref IOC_IOPULL_UP -//! - \ref IOC_IOPULL_DOWN -//! - Input mode: -//! - \ref IOC_INPUT_ENABLE -//! - \ref IOC_INPUT_DISABLE -//! - Hysteresis mode: -//! - \ref IOC_HYST_ENABLE -//! - \ref IOC_HYST_DISABLE -//! - Slew rate reduction mode: -//! - \ref IOC_SLEW_ENABLE -//! - \ref IOC_SLEW_DISABLE -//! - Current mode (see \ref IOCIODrvStrengthSet() for more details): -//! - \ref IOC_CURRENT_2MA : Low-Current mode. Min 2 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. -//! - \ref IOC_CURRENT_4MA : High-Current mode. Min 4 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. -//! - \ref IOC_CURRENT_8MA : Extended-Current mode. Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. -//! - Drive strength mode: -//! - \ref IOC_STRENGTH_AUTO : Automatic drive strength based on battery voltage. -//! - \ref IOC_STRENGTH_MAX : Maximum drive strength, used for low supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). -//! - \ref IOC_STRENGTH_MED : Medium drive strength, used for medium supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). -//! - \ref IOC_STRENGTH_MIN : Minimum drive strength, used for high supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). -//! - Assert AON_PROG2 event on edge detection: -//! - \ref IOC_EVT_AON_PROG2_DISABLE -//! - \ref IOC_EVT_AON_PROG2_ENABLE -//! - Assert AON_PROG1 event on edge detection: -//! - \ref IOC_EVT_AON_PROG1_DISABLE -//! - \ref IOC_EVT_AON_PROG1_ENABLE -//! - Assert AON_PROG0 event on edge detection: -//! - \ref IOC_EVT_AON_PROG0_DISABLE -//! - \ref IOC_EVT_AON_PROG0_ENABLE -//! - Assert RTC event on edge detection: -//! - \ref IOC_EVT_RTC_DISABLE -//! - \ref IOC_EVT_RTC_ENABLE -//! - Assert MCU_WU event on edge detection: -//! - \ref IOC_EVT_MCU_WU_DISABLE -//! - \ref IOC_EVT_MCU_WU_ENABLE -//! -//! \return None -// -//***************************************************************************** -extern void IOCPortConfigureSet(uint32_t ui32IOId, uint32_t ui32PortId, - uint32_t ui32IOConfig); - -//***************************************************************************** -// -//! \brief Get the configuration of an IO port. -//! -//! This function is used for getting the configuration of an IO. -//! -//! Each IO port has a dedicated register for setting up the IO. This function -//! returns the current configuration for the given IO. -//! -//! \param ui32IOId selects the IO to return the configuration for. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! -//! \return Returns the IO Port configuration. -//! See \ref IOCPortConfigureSet() for configuration options. -// -//***************************************************************************** -extern uint32_t IOCPortConfigureGet(uint32_t ui32IOId); - -//***************************************************************************** -// -//! \brief Set wake-up mode from shutdown on an IO port. -//! -//! This function is used to set the wake-up mode from shutdown of an IO. -//! -//! IO must be configured as input in order for wakeup to work. See \ref IOCIOInputSet(). -//! -//! \param ui32IOId defines the IO to configure. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! \param ui32IOShutdown enables wake-up from shutdown on LOW/HIGH by this IO port. -//! - \ref IOC_NO_WAKE_UP -//! - \ref IOC_WAKE_ON_LOW -//! - \ref IOC_WAKE_ON_HIGH -//! -//! \return None -// -//***************************************************************************** -extern void IOCIOShutdownSet(uint32_t ui32IOId, uint32_t ui32IOShutdown); - - -//***************************************************************************** -// -//! \brief Set the IO Mode of an IO Port. -//! -//! This function is used to set the input/output mode of an IO. -//! -//! \param ui32IOId defines the IO to configure. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! \param ui32IOMode sets the port IO Mode. -//! - \ref IOC_IOMODE_NORMAL -//! - \ref IOC_IOMODE_INV -//! - \ref IOC_IOMODE_OPEN_DRAIN_NORMAL -//! - \ref IOC_IOMODE_OPEN_DRAIN_INV -//! - \ref IOC_IOMODE_OPEN_SRC_NORMAL -//! - \ref IOC_IOMODE_OPEN_SRC_INV -//! -//! \return None -// -//***************************************************************************** -extern void IOCIOModeSet(uint32_t ui32IOId, uint32_t ui32IOMode); - -//***************************************************************************** -// -//! \brief Setup edge detection and interrupt generation on an IO Port. -//! -//! This function is used to setup the edge detection and interrupt generation on an IO. -//! -//! \param ui32IOId defines the IO to configure. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! \param ui32Int enables/disables interrupt generation on this IO port. -//! - \ref IOC_INT_ENABLE -//! - \ref IOC_INT_DISABLE -//! \param ui32EdgeDet enables/disables edge detection events on this IO port. -//! - \ref IOC_NO_EDGE -//! - \ref IOC_FALLING_EDGE -//! - \ref IOC_RISING_EDGE -//! - \ref IOC_BOTH_EDGES -//! -//! \return None -// -//***************************************************************************** -extern void IOCIOIntSet(uint32_t ui32IOId, uint32_t ui32Int, - uint32_t ui32EdgeDet); - -//***************************************************************************** -// -//! \brief Setup event generation on IO edge detection. -//! -//! This function is used to setup event generation for specific events -//! when an IO edge detection occurs. -//! -//! \param ui32IOId defines the IO to configure. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! \param ui32Evt is a bitwise OR of the IO events to generate when an IO edge detection occurs. -//! All other IO event generations are disabled. -//! - \ref IOC_EVT_AON_PROG2_ENABLE : AON_PROG2 event. -//! - \ref IOC_EVT_AON_PROG1_ENABLE : AON_PROG1 event. -//! - \ref IOC_EVT_AON_PROG0_ENABLE : AON_PROG0 event. -//! - \ref IOC_EVT_RTC_ENABLE : RTC event. -//! - \ref IOC_EVT_MCU_WU_ENABLE : MCU_WU event. -//! -// -//***************************************************************************** -extern void IOCIOEvtSet(uint32_t ui32IOId, uint32_t ui32Evt); - -//***************************************************************************** -// -//! \brief Set the pull on an IO port. -//! -//! This function is used to configure the pull on an IO. -//! -//! \param ui32IOId defines the IO to configure. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! \param ui32Pull enables/disables pull on this IO port. -//! - \ref IOC_NO_IOPULL -//! - \ref IOC_IOPULL_UP -//! - \ref IOC_IOPULL_DOWN -//! -//! \return None -// -//***************************************************************************** -extern void IOCIOPortPullSet(uint32_t ui32IOId, uint32_t ui32Pull); - -//***************************************************************************** -// -//! \brief Configure hysteresis on and IO port. -//! -//! This function is used to enable/disable hysteresis on an IO. -//! -//! \param ui32IOId defines the IO to configure. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! \param ui32Hysteresis enable/disable input hysteresis on IO. -//! - \ref IOC_HYST_ENABLE -//! - \ref IOC_HYST_DISABLE -//! -//! \return None -// -//***************************************************************************** -extern void IOCIOHystSet(uint32_t ui32IOId, uint32_t ui32Hysteresis); - -//***************************************************************************** -// -//! \brief Enable/disable IO port as input. -//! -//! This function is used to enable/disable input on an IO. -//! -//! \param ui32IOId defines the IO to configure. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! \param ui32Input enable/disable input on IO. -//! - \ref IOC_INPUT_ENABLE -//! - \ref IOC_INPUT_DISABLE -//! -//! \return None -// -//***************************************************************************** -extern void IOCIOInputSet(uint32_t ui32IOId, uint32_t ui32Input); - -//***************************************************************************** -// -//! \brief Configure slew rate on an IO port. -//! -//! This function is used to enable/disable reduced slew rate on an IO. -//! -//! \param ui32IOId defines the IO to configure. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! \param ui32SlewEnable enables/disables reduced slew rate on an output. -//! - \ref IOC_SLEW_ENABLE -//! - \ref IOC_SLEW_DISABLE -//! -//! \return None -// -//***************************************************************************** -extern void IOCIOSlewCtrlSet(uint32_t ui32IOId, uint32_t ui32SlewEnable); - -//***************************************************************************** -// -//! \brief Configure the drive strength source and current mode of an IO port. -//! -//! The drive strength of an IO is configured by a combination of multiple settings -//! in several modules. The drive strength source \ti_code{ui32DrvStrength} is used for controlling -//! drive strength at different supply levels. When set to AUTO the battery monitor -//! (BATMON) adjusts the drive strength to compensate for changes in supply voltage -//! in order to keep IO current constant. Alternatively, drive strength source can -//! be controlled manually by selecting one of three options each of which is configurable -//! in the AON IOC by \ref AONIOCDriveStrengthSet(). -//! -//! Each drive strength source has three current modes: Low-Current (LC), High-Current (HC), and -//! Extended-Current (EC), and typically drive strength doubles when selecting a higher mode. -//! I.e. EC = 2 x HC = 4 x LC. -//! -//! \note Not all IOs support Extended-Current mode. See datasheet for more information -//! on the specific device. -//! -//! \param ui32IOId defines the IO to configure. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! \param ui32IOCurrent selects the IO current mode. -//! - \ref IOC_CURRENT_2MA : Low-Current mode. Min 2 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. -//! - \ref IOC_CURRENT_4MA : High-Current mode. Min 4 mA when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. -//! - \ref IOC_CURRENT_8MA : Extended-Current mode. Min 8 mA for double drive strength IOs (min 4 mA for normal IOs) when \ti_code{ui32DrvStrength} is set to \ref IOC_STRENGTH_AUTO. -//! \param ui32DrvStrength sets the source for drive strength control of the IO port. -//! - \ref IOC_STRENGTH_AUTO : Automatic drive strength based on battery voltage. -//! - \ref IOC_STRENGTH_MAX : Maximum drive strength, used for low supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). -//! - \ref IOC_STRENGTH_MED : Medium drive strength, used for medium supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). -//! - \ref IOC_STRENGTH_MIN : Minimum drive strength, used for high supply levels. Controlled by AON IOC (see \ref AONIOCDriveStrengthSet()). -//! -//! \return None -// -//***************************************************************************** -extern void IOCIODrvStrengthSet(uint32_t ui32IOId, uint32_t ui32IOCurrent, - uint32_t ui32DrvStrength); - -//***************************************************************************** -// -//! \brief Setup the Port ID for this IO. -//! -//! The \c ui32PortId specifies which functional peripheral to hook up to this -//! IO. -//! -//! \param ui32IOId defines the IO to configure. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! \param ui32PortId selects the port to map to the IO. -//! - \ref IOC_PORT_GPIO -//! - \ref IOC_PORT_AON_CLK32K -//! - \ref IOC_PORT_AUX_IO -//! - \ref IOC_PORT_MCU_SSI0_RX -//! - \ref IOC_PORT_MCU_SSI0_TX -//! - \ref IOC_PORT_MCU_SSI0_FSS -//! - \ref IOC_PORT_MCU_SSI0_CLK -//! - \ref IOC_PORT_MCU_I2C_MSSDA -//! - \ref IOC_PORT_MCU_I2C_MSSCL -//! - \ref IOC_PORT_MCU_UART0_RX -//! - \ref IOC_PORT_MCU_UART0_TX -//! - \ref IOC_PORT_MCU_UART0_CTS -//! - \ref IOC_PORT_MCU_UART0_RTS -//! - \ref IOC_PORT_MCU_UART1_RX -//! - \ref IOC_PORT_MCU_UART1_TX -//! - \ref IOC_PORT_MCU_UART1_CTS -//! - \ref IOC_PORT_MCU_UART1_RTS -//! - \ref IOC_PORT_MCU_PORT_EVENT0 -//! - \ref IOC_PORT_MCU_PORT_EVENT1 -//! - \ref IOC_PORT_MCU_PORT_EVENT2 -//! - \ref IOC_PORT_MCU_PORT_EVENT3 -//! - \ref IOC_PORT_MCU_PORT_EVENT4 -//! - \ref IOC_PORT_MCU_PORT_EVENT5 -//! - \ref IOC_PORT_MCU_PORT_EVENT6 -//! - \ref IOC_PORT_MCU_PORT_EVENT7 -//! - \ref IOC_PORT_MCU_SWV -//! - \ref IOC_PORT_MCU_SSI1_RX -//! - \ref IOC_PORT_MCU_SSI1_TX -//! - \ref IOC_PORT_MCU_SSI1_FSS -//! - \ref IOC_PORT_MCU_SSI1_CLK -//! - \ref IOC_PORT_MCU_I2S_AD0 -//! - \ref IOC_PORT_MCU_I2S_AD1 -//! - \ref IOC_PORT_MCU_I2S_WCLK -//! - \ref IOC_PORT_MCU_I2S_BCLK -//! - \ref IOC_PORT_MCU_I2S_MCLK -//! - \ref IOC_PORT_RFC_TRC -//! - \ref IOC_PORT_RFC_GPO0 -//! - \ref IOC_PORT_RFC_GPO1 -//! - \ref IOC_PORT_RFC_GPO2 -//! - \ref IOC_PORT_RFC_GPO3 -//! - \ref IOC_PORT_RFC_GPI0 -//! - \ref IOC_PORT_RFC_GPI1 -//! -//! \return None -// -//***************************************************************************** -extern void IOCIOPortIdSet(uint32_t ui32IOId, uint32_t ui32PortId); - -//***************************************************************************** -// -//! \brief Register an interrupt handler for an IO edge interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific IO interrupts must be enabled via \ref IOCIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! IOC interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -IOCIntRegister(void (*pfnHandler)(void)) -{ - // Register the interrupt handler. - IntRegister(INT_AON_GPIO_EDGE, pfnHandler); - - // Enable the IO edge interrupt. - IntEnable(INT_AON_GPIO_EDGE); -} - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for a IO edge interrupt in the dynamic interrupt table. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when an IO edge interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -IOCIntUnregister(void) -{ - // Disable the interrupts. - IntDisable(INT_AON_GPIO_EDGE); - - // Unregister the interrupt handler. - IntUnregister(INT_AON_GPIO_EDGE); -} - -//***************************************************************************** -// -//! \brief Enables individual IO edge detect interrupt. -//! -//! This function enables the indicated IO edge interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32IOId is the IO to enable edge detect interrupt for. -//! -//! \return None -// -//***************************************************************************** -extern void IOCIntEnable(uint32_t ui32IOId); - -//***************************************************************************** -// -//! \brief Disables individual IO edge interrupt sources. -//! -//! This function disables the indicated IO edge interrupt source. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32IOId is the IO edge interrupt source to be disabled. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! -//! \return None -// -//***************************************************************************** -extern void IOCIntDisable(uint32_t ui32IOId); - -//***************************************************************************** -// -//! \brief Clears the IO edge interrupt source. -//! -//! The specified IO edge interrupt source is cleared, so that it no longer -//! asserts. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32IOId is the IO causing the interrupt. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -IOCIntClear(uint32_t ui32IOId) -{ - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - - // Clear the requested interrupt source by clearing the event. - GPIO_clearEventDio(ui32IOId); -} - -//***************************************************************************** -// -//! \brief Returns the status of the IO interrupts. -//! -//! \param ui32IOId is the IO to get the status for. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE uint32_t -IOCIntStatus(uint32_t ui32IOId) -{ - // Check the arguments. - ASSERT(ui32IOId <= IOID_31); - - // Get the event status. - return (GPIO_getEventDio(ui32IOId)); -} - - -//***************************************************************************** -// -//! \brief Setup an IO for standard GPIO input. -//! -//! Setup an IO for standard GPIO input with the following configuration: -//! - Port ID: -//! - \ref IOC_PORT_GPIO -//! - Configuration: -//! - \ref IOC_CURRENT_2MA -//! - \ref IOC_STRENGTH_AUTO -//! - \ref IOC_NO_IOPULL -//! - \ref IOC_SLEW_DISABLE -//! - \ref IOC_HYST_DISABLE -//! - \ref IOC_NO_EDGE -//! - \ref IOC_INT_DISABLE -//! - \ref IOC_IOMODE_NORMAL -//! - \ref IOC_NO_WAKE_UP -//! - \ref IOC_INPUT_ENABLE -//! -//! \param ui32IOId is the IO to setup for GPIO input -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! -//! \return None -// -//***************************************************************************** -extern void IOCPinTypeGpioInput(uint32_t ui32IOId); - -//***************************************************************************** -// -//! \brief Setup an IO for standard GPIO output. -//! -//! Setup an IO for standard GPIO output with the following configuration: -//! - Port ID: -//! - \ref IOC_PORT_GPIO -//! - Configuration: -//! - \ref IOC_CURRENT_2MA -//! - \ref IOC_STRENGTH_AUTO -//! - \ref IOC_NO_IOPULL -//! - \ref IOC_SLEW_DISABLE -//! - \ref IOC_HYST_DISABLE -//! - \ref IOC_NO_EDGE -//! - \ref IOC_INT_DISABLE -//! - \ref IOC_IOMODE_NORMAL -//! - \ref IOC_NO_WAKE_UP -//! - \ref IOC_INPUT_DISABLE -//! -//! \param ui32IOId is the IO to setup for GPIO output -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! -//! \return None -// -//***************************************************************************** -extern void IOCPinTypeGpioOutput(uint32_t ui32IOId); - -//***************************************************************************** -// -//! \brief Configure a set of IOs for standard UART peripheral control. -//! -//! The UART pins must be properly configured for the UART peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin(s). Other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! \note If a UART pin is not intended to be used, then the parameter in the -//! function should be \ref IOID_UNUSED. -//! -//! \param ui32Base is the base address of the UART module. -//! \param ui32Rx is the IO Id of the IO to use as UART Receive. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! \param ui32Tx is the IO Id of the IO to use as UART Transmit. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! \param ui32Cts is the IO Id of the IO to use for UART Clear to send. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! \param ui32Rts is the IO Id of the IO to use for UART Request to send. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! -//! \return None -// -//***************************************************************************** -extern void IOCPinTypeUart(uint32_t ui32Base, uint32_t ui32Rx, - uint32_t ui32Tx, uint32_t ui32Cts, - uint32_t ui32Rts); - -//***************************************************************************** -// -//! \brief Configure a set of IOs for standard SSI peripheral master control. -//! -//! \param ui32Base is the base address of the SSI module to connect to the IOs -//! \param ui32Rx is the IO to connect to the SSI MISO line. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! \param ui32Tx is the IO to connect to the SSI MOSI line. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! \param ui32Fss is the IO to connect to the SSI FSS line. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! \param ui32Clk is the IO to connect to the SSI Clock output line. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! -//! \return None -// -//***************************************************************************** -extern void IOCPinTypeSsiMaster(uint32_t ui32Base, uint32_t ui32Rx, - uint32_t ui32Tx, uint32_t ui32Fss, - uint32_t ui32Clk); - -//***************************************************************************** -// -//! \brief Configure a set of IOs for standard SSI peripheral slave control. -//! -//! \param ui32Base is the base address of the SSI module to connect to the IOs -//! \param ui32Rx is the IO to connect to the SSI MOSI line. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! \param ui32Tx is the IO to connect to the SSI MISO line. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! \param ui32Fss is the IO to connect to the SSI FSS line. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! \param ui32Clk is the IO to connect to the SSI Clock input line. -//! -//! \return None -// -//***************************************************************************** -extern void IOCPinTypeSsiSlave(uint32_t ui32Base, uint32_t ui32Rx, - uint32_t ui32Tx, uint32_t ui32Fss, - uint32_t ui32Clk); - -//***************************************************************************** -// -//! \brief Configure a set of IOs for standard I2C peripheral control. -//! -//! \param ui32Base is the base address of the I2C module to connect to the IOs -//! \param ui32Data is the I2C data line -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! \param ui32Clk is the I2C input clock -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! -//! \return None -// -//***************************************************************************** -extern void IOCPinTypeI2c(uint32_t ui32Base, uint32_t ui32Data, - uint32_t ui32Clk); - - -//***************************************************************************** -// -//! \brief Configure an IO for AUX control. -//! -//! Use this function to enable AUX to control a specific IO. Please note, that -//! when using AUX to control the IO, the input/output control in the IOC is -//! bypassed and completely controlled by AUX, so enabling or disabling input -//! in the IOC has no effect. -//! -//! \note The IOs available for AUX control can vary from device to device. -//! -//! \param ui32IOId is the IO to setup for AUX usage. -//! - \ref IOID_0 -//! - ... -//! - \ref IOID_31 -//! - \ref IOID_UNUSED -//! -//! \return None -// -//***************************************************************************** -extern void IOCPinTypeAux(uint32_t ui32IOId); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_IOCPortConfigureSet - #undef IOCPortConfigureSet - #define IOCPortConfigureSet ROM_IOCPortConfigureSet - #endif - #ifdef ROM_IOCPortConfigureGet - #undef IOCPortConfigureGet - #define IOCPortConfigureGet ROM_IOCPortConfigureGet - #endif - #ifdef ROM_IOCIOShutdownSet - #undef IOCIOShutdownSet - #define IOCIOShutdownSet ROM_IOCIOShutdownSet - #endif - #ifdef ROM_IOCIOModeSet - #undef IOCIOModeSet - #define IOCIOModeSet ROM_IOCIOModeSet - #endif - #ifdef ROM_IOCIOIntSet - #undef IOCIOIntSet - #define IOCIOIntSet ROM_IOCIOIntSet - #endif - #ifdef ROM_IOCIOEvtSet - #undef IOCIOEvtSet - #define IOCIOEvtSet ROM_IOCIOEvtSet - #endif - #ifdef ROM_IOCIOPortPullSet - #undef IOCIOPortPullSet - #define IOCIOPortPullSet ROM_IOCIOPortPullSet - #endif - #ifdef ROM_IOCIOHystSet - #undef IOCIOHystSet - #define IOCIOHystSet ROM_IOCIOHystSet - #endif - #ifdef ROM_IOCIOInputSet - #undef IOCIOInputSet - #define IOCIOInputSet ROM_IOCIOInputSet - #endif - #ifdef ROM_IOCIOSlewCtrlSet - #undef IOCIOSlewCtrlSet - #define IOCIOSlewCtrlSet ROM_IOCIOSlewCtrlSet - #endif - #ifdef ROM_IOCIODrvStrengthSet - #undef IOCIODrvStrengthSet - #define IOCIODrvStrengthSet ROM_IOCIODrvStrengthSet - #endif - #ifdef ROM_IOCIOPortIdSet - #undef IOCIOPortIdSet - #define IOCIOPortIdSet ROM_IOCIOPortIdSet - #endif - #ifdef ROM_IOCIntEnable - #undef IOCIntEnable - #define IOCIntEnable ROM_IOCIntEnable - #endif - #ifdef ROM_IOCIntDisable - #undef IOCIntDisable - #define IOCIntDisable ROM_IOCIntDisable - #endif - #ifdef ROM_IOCPinTypeGpioInput - #undef IOCPinTypeGpioInput - #define IOCPinTypeGpioInput ROM_IOCPinTypeGpioInput - #endif - #ifdef ROM_IOCPinTypeGpioOutput - #undef IOCPinTypeGpioOutput - #define IOCPinTypeGpioOutput ROM_IOCPinTypeGpioOutput - #endif - #ifdef ROM_IOCPinTypeUart - #undef IOCPinTypeUart - #define IOCPinTypeUart ROM_IOCPinTypeUart - #endif - #ifdef ROM_IOCPinTypeSsiMaster - #undef IOCPinTypeSsiMaster - #define IOCPinTypeSsiMaster ROM_IOCPinTypeSsiMaster - #endif - #ifdef ROM_IOCPinTypeSsiSlave - #undef IOCPinTypeSsiSlave - #define IOCPinTypeSsiSlave ROM_IOCPinTypeSsiSlave - #endif - #ifdef ROM_IOCPinTypeI2c - #undef IOCPinTypeI2c - #define IOCPinTypeI2c ROM_IOCPinTypeI2c - #endif - #ifdef ROM_IOCPinTypeAux - #undef IOCPinTypeAux - #define IOCPinTypeAux ROM_IOCPinTypeAux - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __IOC_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h deleted file mode 100644 index dcd74ca1146..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc_doc.h +++ /dev/null @@ -1,92 +0,0 @@ -/****************************************************************************** -* Filename: ioc_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup ioc_api -//! @{ -//! \section sec_ioc Introduction -//! -//! The Input/Output Controller (IOC) controls the functionality of the pins (called DIO). -//! The IOC consists of two APIs: -//! - MCU IOC API selects which peripheral module is connected to the individual DIO and thus allowed to control it. -//! It also controls individual drive strength, slew rate, pull-up/pull-down, edge detection, etc. -//! - AON IOC API controls the general drive strength definitions, IO latches, and if the LF clock is -//! routed to a DIO for external use. -//! -//! For more information on the AON IOC see the [AON IOC API](\ref aonioc_api). -//! -//! \note The output driver of a DIO is not configured by the IOC API (except for drive strength); instead, it is controlled by the -//! peripheral module which is selected to control the DIO. -//! -//! A DIO is considered "software controlled" if it is configured for GPIO control which allows the -//! System CPU to set the value of the DIO via the [GPIO API](\ref gpio_api). Alternatively, a DIO -//! can be "hardware controlled" if it is controlled by other modules than GPIO. -//! -//! \section sec_ioc_api API -//! -//! The API functions can be grouped like this: -//! -//! Configure all settings at the same time: -//! - \ref IOCPortConfigureSet() -//! - \ref IOCPortConfigureGet() -//! -//! Configure individual settings: -//! - \ref IOCIODrvStrengthSet() -//! - \ref IOCIOHystSet() -//! - \ref IOCIOInputSet() -//! - \ref IOCIOIntSet() -//! - \ref IOCIOModeSet() -//! - \ref IOCIOPortIdSet() -//! - \ref IOCIOPortPullSet() -//! - \ref IOCIOShutdownSet() -//! - \ref IOCIOSlewCtrlSet() -//! -//! Handle edge detection events: -//! - \ref IOCIntEnable() -//! - \ref IOCIntDisable() -//! - \ref IOCIntClear() -//! - \ref IOCIntStatus() -//! - \ref IOCIntRegister() -//! - \ref IOCIntUnregister() -//! -//! Configure IOCs for typical use cases (can also be used as example code): -//! - \ref IOCPinTypeAux() -//! - \ref IOCPinTypeGpioInput() -//! - \ref IOCPinTypeGpioOutput() -//! - \ref IOCPinTypeI2c() -//! - \ref IOCPinTypeSsiMaster() -//! - \ref IOCPinTypeSsiSlave() -//! - \ref IOCPinTypeUart() -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.c deleted file mode 100644 index 1212d01e7b8..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.c +++ /dev/null @@ -1,625 +0,0 @@ -/****************************************************************************** -* Filename: osc.c -* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) -* Revision: 54539 -* -* Description: Driver for setting up the system Oscillators -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "../inc/hw_types.h" -#include "../inc/hw_ccfg.h" -#include "../inc/hw_fcfg1.h" -#include "aon_batmon.h" -#include "aon_rtc.h" -#include "osc.h" -#include "setup_rom.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef OSCClockSourceSet - #define OSCClockSourceSet NOROM_OSCClockSourceSet - #undef OSCClockSourceGet - #define OSCClockSourceGet NOROM_OSCClockSourceGet - #undef OSCHF_GetStartupTime - #define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime - #undef OSCHF_TurnOnXosc - #define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc - #undef OSCHF_AttemptToSwitchToXosc - #define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc - #undef OSCHF_SwitchToRcOscTurnOffXosc - #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc - #undef OSCHF_DebugGetCrystalAmplitude - #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude - #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude - #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude - #undef OSC_HPOSC_Debug_InitFreqOffsetParams - #define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams - #undef OSC_HPOSCInitializeFrequencyOffsetParameters - #define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters - #undef OSC_HPOSCRelativeFrequencyOffsetGet - #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet - #undef OSC_AdjustXoscHfCapArray - #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray - #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert - #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert - #undef OSC_HPOSCRtcCompensate - #define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate -#endif - -//***************************************************************************** -// -// Global HPOSC curve fitting polynomials -// Parameters found/calculated when calling function -// OSC_HPOSCInitializeFrequencyOffsetParameters() -// (or OSC_HPOSC_Debug_InitFreqOffsetParams() used for debugging only) -// These global variables must be updated before using HPOSC -// -//***************************************************************************** - -static int16_t _hpOscPolynomials[ 4 ]; - -//***************************************************************************** -// -// OSCHF switch time calculator defines and globals -// -//***************************************************************************** - -#define RTC_CV_TO_MS(x) (( 1000 * ( x )) >> 16 ) -#define RTC_CV_TO_US(x) (( 1000000 * ( x )) >> 16 ) - -typedef struct { - uint32_t previousStartupTimeInUs ; - uint32_t timeXoscOff_CV ; - uint32_t timeXoscOn_CV ; - uint32_t timeXoscStable_CV ; - int32_t tempXoscOff ; -} OscHfGlobals_t; - -static OscHfGlobals_t oscHfGlobals; - -//***************************************************************************** -// -// Configure the oscillator input to the a source clock. -// -//***************************************************************************** -void -OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc) -{ - // Check the arguments. - ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || - (ui32SrcClk & OSC_SRC_CLK_HF)); - ASSERT((ui32Osc == OSC_RCOSC_HF) || - (ui32Osc == OSC_RCOSC_LF) || - (ui32Osc == OSC_XOSC_HF) || - (ui32Osc == OSC_XOSC_LF)); - - // Request the high frequency source clock (using 24 MHz XTAL) - if(ui32SrcClk & OSC_SRC_CLK_HF) - { - // Enable the HF XTAL as HF clock source - DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, - DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M, - DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S, - ui32Osc); - } - - // Configure the low frequency source clock. - if(ui32SrcClk & OSC_SRC_CLK_LF) - { - // Change the clock source. - DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, - DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M, - DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S, - ui32Osc); - } -} - -//***************************************************************************** -// -// Get the source clock settings -// -//***************************************************************************** -uint32_t -OSCClockSourceGet(uint32_t ui32SrcClk) -{ - uint32_t ui32ClockSource; - - // Check the arguments. - ASSERT((ui32SrcClk & OSC_SRC_CLK_LF) || - (ui32SrcClk & OSC_SRC_CLK_HF)); - - // Return the source for the selected clock. - if(ui32SrcClk == OSC_SRC_CLK_LF) - { - ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, - DDI_0_OSC_STAT0_SCLK_LF_SRC_M, - DDI_0_OSC_STAT0_SCLK_LF_SRC_S); - } - else - { - ui32ClockSource = DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, - DDI_0_OSC_STAT0_SCLK_HF_SRC_M, - DDI_0_OSC_STAT0_SCLK_HF_SRC_S); - } - return (ui32ClockSource); -} - -//***************************************************************************** -// -// Returns maximum startup time (in microseconds) of XOSC_HF -// -//***************************************************************************** -uint32_t -OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ) -{ - uint32_t deltaTimeSinceXoscOnInMs ; - int32_t deltaTempSinceXoscOn ; - uint32_t newStartupTimeInUs ; - - deltaTimeSinceXoscOnInMs = RTC_CV_TO_MS( AONRTCCurrentCompareValueGet() - oscHfGlobals.timeXoscOn_CV ); - deltaTempSinceXoscOn = AONBatMonTemperatureGetDegC() - oscHfGlobals.tempXoscOff; - - if ( deltaTempSinceXoscOn < 0 ) { - deltaTempSinceXoscOn = -deltaTempSinceXoscOn; - } - - if ( (( timeUntilWakeupInMs + deltaTimeSinceXoscOnInMs ) > 3000 ) || - ( deltaTempSinceXoscOn > 5 ) || - ( oscHfGlobals.timeXoscStable_CV < oscHfGlobals.timeXoscOn_CV ) || - ( oscHfGlobals.previousStartupTimeInUs == 0 ) ) - { - newStartupTimeInUs = 2000; - if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { - newStartupTimeInUs = (( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & - CCFG_MODE_CONF_1_XOSC_MAX_START_M ) >> - CCFG_MODE_CONF_1_XOSC_MAX_START_S ) * 125; - // Note: CCFG startup time is "in units of 100us" adding 25% margin results in *125 - } - } else { - newStartupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV ); - newStartupTimeInUs += ( newStartupTimeInUs >> 2 ); // Add 25 percent margin - if ( newStartupTimeInUs < oscHfGlobals.previousStartupTimeInUs ) { - newStartupTimeInUs = oscHfGlobals.previousStartupTimeInUs; - } - } - - if ( newStartupTimeInUs < 200 ) { - newStartupTimeInUs = 200; - } - if ( newStartupTimeInUs > 4000 ) { - newStartupTimeInUs = 4000; - } - return ( newStartupTimeInUs ); -} - - -//***************************************************************************** -// -// Turns on XOSC_HF (but without switching to XOSC_HF) -// -//***************************************************************************** -void -OSCHF_TurnOnXosc( void ) -{ -#if ( defined( ROM_OSCClockSourceSet )) - ROM_OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_XOSC_HF ); -#else - OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_XOSC_HF ); -#endif - oscHfGlobals.timeXoscOn_CV = AONRTCCurrentCompareValueGet(); -} - - -//***************************************************************************** -// -// Switch to XOSC_HF if XOSC_HF is ready. -// -//***************************************************************************** -bool -OSCHF_AttemptToSwitchToXosc( void ) -{ - uint32_t startupTimeInUs; - uint32_t prevLimmit25InUs; - -#if ( defined( ROM_OSCClockSourceGet )) - if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF ) -#else - if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) == OSC_XOSC_HF ) -#endif - { - // Already on XOSC - nothing to do - return ( 1 ); - } - if ( OSCHfSourceReady()) { - OSCHfSourceSwitch(); - - // Store startup time, but limit to 25 percent reduction each time. - oscHfGlobals.timeXoscStable_CV = AONRTCCurrentCompareValueGet(); - startupTimeInUs = RTC_CV_TO_US( oscHfGlobals.timeXoscStable_CV - oscHfGlobals.timeXoscOn_CV ); - prevLimmit25InUs = oscHfGlobals.previousStartupTimeInUs; - prevLimmit25InUs -= ( prevLimmit25InUs >> 2 ); // 25 percent margin - oscHfGlobals.previousStartupTimeInUs = startupTimeInUs; - if ( prevLimmit25InUs > startupTimeInUs ) { - oscHfGlobals.previousStartupTimeInUs = prevLimmit25InUs; - } - return ( 1 ); - } - return ( 0 ); -} - - -//***************************************************************************** -// -// Switch to RCOSC_HF and turn off XOSC_HF -// -//***************************************************************************** -void -OSCHF_SwitchToRcOscTurnOffXosc( void ) -{ -#if ( defined( ROM_OSCClockSourceSet )) - ROM_OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_RCOSC_HF ); -#else - OSCClockSourceSet( OSC_SRC_CLK_HF, OSC_RCOSC_HF ); -#endif - - // Do the switching if not already running on RCOSC_HF -#if ( defined( ROM_OSCClockSourceGet )) - if ( ROM_OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF ) -#else - if ( OSCClockSourceGet( OSC_SRC_CLK_HF ) != OSC_RCOSC_HF ) -#endif - { - OSCHfSourceSwitch(); - } - - oscHfGlobals.timeXoscOff_CV = AONRTCCurrentCompareValueGet(); - oscHfGlobals.tempXoscOff = AONBatMonTemperatureGetDegC(); -} - -//***************************************************************************** -// -// Adjust the XOSC HF cap array relative to the factory setting -// -//***************************************************************************** -void -OSC_AdjustXoscHfCapArray( int32_t capArrDelta ) -{ - // read the MODE_CONF register in CCFG - uint32_t ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); - // Clear CAP_MODE and the CAPARRAY_DELATA field - ccfg_ModeConfReg &= ~( CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M | CCFG_MODE_CONF_XOSC_CAP_MOD_M ); - // Insert new delta value - ccfg_ModeConfReg |= ((((uint32_t)capArrDelta) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) & CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ); - // Update the HW register with the new delta value - DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg )); -} - -//***************************************************************************** -// -// Initialize the frequency offset curve fitting parameters -// These are either picked diretly from FCFG1:FREQ_OFFSET & FCFG1:MISC_CONF_2 or -// calculated based on the FCFG1:HPOSC_MEAS_x parameters. -// -//***************************************************************************** - -// Using the following hardcoded constants (Using temporary constants for now) -#define D1OFFSET_p25C -24 -#define D2OFFSET_p85C -36 -#define D3OFFSET_m40C 18 -#define P3_POLYNOMIAL -47 -#define N_INSERTIONS 3 - -typedef struct { - int32_t dFreq ; - int32_t temp ; -} insertion_t ; - -static void -InitializeMeasurmentSet( insertion_t * pInsertion, uint32_t registerAddress, int32_t deltaOffset, int32_t p3PolOffset ) -{ - // Doing the following adjustment to the deltaFrequence before finding the polynomials P0, P1, P2 - // Dx = Dx + DxOFFSET - ((P3*Tx^3)/2^18) - uint32_t insertionData = HWREG( registerAddress ); - pInsertion->dFreq = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W - FCFG1_HPOSC_MEAS_1_HPOSC_D1_S ))) - >> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_D1_W )); - pInsertion->temp = (((int32_t)( insertionData << ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W - FCFG1_HPOSC_MEAS_1_HPOSC_T1_S ))) - >> ( 32 - FCFG1_HPOSC_MEAS_1_HPOSC_T1_W )); - pInsertion->dFreq = pInsertion->dFreq + deltaOffset - (( p3PolOffset * pInsertion->temp * pInsertion->temp * pInsertion->temp ) >> 18 ); -} - -static void -FindPolynomialsAndUpdateGlobals( insertion_t * pMeasurment ) -{ - uint32_t loopCount ; - int32_t polynomial_0 ; - int32_t polynomial_1 ; - int32_t polynomial_2 ; - - int32_t Syi_ = 0 ; - int32_t Sxi_ = 0 ; - int32_t Sxi2_ = 0 ; - int32_t Sxiyi_ = 0 ; - int32_t Sxi2yi_ = 0 ; - int32_t Sxi3_ = 0 ; - int32_t Sxi4_ = 0 ; - - for ( loopCount = 0 ; loopCount < N_INSERTIONS ; loopCount++ ) { - int32_t x ; - int32_t x2 ; - int32_t y ; - - x = pMeasurment[ loopCount ].temp ; - x2 = ( x * x ); - y = pMeasurment[ loopCount ].dFreq ; - - Syi_ += ( y ); - Sxi_ += ( x ); - Sxi2_ += ( x2 ); - Sxiyi_ += ( x * y ); - Sxi2yi_ += ( x2 * y ); - Sxi3_ += ( x2 * x ); - Sxi4_ += ( x2 * x2 ); - } - - int32_t Sxx_ = ( Sxi2_ * N_INSERTIONS ) - ( Sxi_ * Sxi_ ); - int32_t Sxy_ = ( Sxiyi_ * N_INSERTIONS ) - ( Sxi_ * Syi_ ); - int32_t Sxx2_ = ( Sxi3_ * N_INSERTIONS ) - ( Sxi_ * Sxi2_ ); - int32_t Sx2y_ = ( Sxi2yi_ * N_INSERTIONS ) - ( Sxi2_ * Syi_ ); - int32_t Sx2x2_ = ( Sxi4_ * N_INSERTIONS ) - ( Sxi2_ * Sxi2_ ); - - int32_t divisor = ((((int64_t) Sxx_ * Sx2x2_ ) - ((int64_t) Sxx2_ * Sxx2_ )) + (1<<9)) >> 10 ; - if ( divisor == 0 ) { - polynomial_2 = 0 ; - polynomial_1 = 0 ; - } else { - polynomial_2 = (((int64_t) Sx2y_ * Sxx_ ) - ((int64_t) Sxy_ * Sxx2_ )) / divisor ; - polynomial_1 = (((int64_t) Sxy_ * Sx2x2_ ) - ((int64_t) Sx2y_ * Sxx2_ )) / divisor ; - } - polynomial_0 = ( Syi_ - (((( polynomial_1 * Sxi_ ) + ( polynomial_2 * Sxi2_ )) + (1<<9)) >> 10 )) / N_INSERTIONS ; - polynomial_1 = ( polynomial_1 + (1<<6)) >> 7 ; - - _hpOscPolynomials[ 0 ] = polynomial_0 ; - _hpOscPolynomials[ 1 ] = polynomial_1 ; - _hpOscPolynomials[ 2 ] = polynomial_2 ; - _hpOscPolynomials[ 3 ] = P3_POLYNOMIAL ; -} - -//***************************************************************************** -// Degub function to calculate the HPOSC polynomials for experimental data sets. -//***************************************************************************** -void -OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData ) -{ - // Calculate the curve fitting parameters from temp insertion measurements - // But first adjust the measurements with constants found in characterization - insertion_t pMeasurment[ 3 ]; - - InitializeMeasurmentSet( &pMeasurment[ 0 ], (uint32_t)&pDebugData->meas_1, pDebugData->offsetD1, pDebugData->polyP3 ); - InitializeMeasurmentSet( &pMeasurment[ 1 ], (uint32_t)&pDebugData->meas_2, pDebugData->offsetD2, pDebugData->polyP3 ); - InitializeMeasurmentSet( &pMeasurment[ 2 ], (uint32_t)&pDebugData->meas_3, pDebugData->offsetD3, pDebugData->polyP3 ); - - FindPolynomialsAndUpdateGlobals( pMeasurment ); -} - -//***************************************************************************** -// The general HPOSC initialization function - Must always be called before using HPOSC -//***************************************************************************** -void -OSC_HPOSCInitializeFrequencyOffsetParameters( void ) -{ - { - // Calculate the curve fitting parameters from temp insertion measurements - // But first adjust the measurements with constants found in characterization - insertion_t pMeasurment[ 3 ]; - - InitializeMeasurmentSet( &pMeasurment[ 0 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_1, D1OFFSET_p25C, P3_POLYNOMIAL ); - InitializeMeasurmentSet( &pMeasurment[ 1 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_2, D2OFFSET_p85C, P3_POLYNOMIAL ); - InitializeMeasurmentSet( &pMeasurment[ 2 ], FCFG1_BASE + FCFG1_O_HPOSC_MEAS_3, D3OFFSET_m40C, P3_POLYNOMIAL ); - - FindPolynomialsAndUpdateGlobals( pMeasurment ); - } -} - -//***************************************************************************** -// -// Calculate the temperature dependent relative frequency offset of HPOSC -// -//***************************************************************************** -int32_t -OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ) -{ - // Estimate HPOSC frequency, using temperature and curve fitting parameters - - int32_t paramP0 = _hpOscPolynomials[ 0 ]; - int32_t paramP1 = _hpOscPolynomials[ 1 ]; - int32_t paramP2 = _hpOscPolynomials[ 2 ]; - int32_t paramP3 = _hpOscPolynomials[ 3 ]; - - // Now we can find the HPOSC freq offset, given as a signed variable d, expressed by: - // - // F_HPOSC = F_nom * (1 + d/(2^22)) , where: F_HPOSC = HPOSC frequency - // F_nom = nominal clock source frequency (e.g. 48.000 MHz) - // d = describes relative freq offset - - // We can estimate the d variable, using temperature compensation parameters: - // - // d = P0 + P1*(t - T0) + P2*(t - T0)^2 + P3*(t - T0)^3, where: P0,P1,P2,P3 are curve fitting parameters from FCFG1 - // t = current temperature (from temp sensor) in deg C - // T0 = 27 deg C (fixed temperature constant) - int32_t tempDelta = (tempDegC - 27); - int32_t tempDeltaX2 = tempDelta * tempDelta; - int32_t d = paramP0 + ((tempDelta*paramP1)>>3) + ((tempDeltaX2*paramP2)>>10) + ((tempDeltaX2*tempDelta*paramP3)>>18); - - return ( d ); -} - -//***************************************************************************** -// -// Converts the relative frequency offset of HPOSC to the RF Core parameter format. -// -//***************************************************************************** -int16_t -OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ) -{ - // The input argument, hereby referred to simply as "d", describes the frequency offset - // of the HPOSC relative to the nominal frequency in this way: - // - // F_HPOSC = F_nom * (1 + d/(2^22)) - // - // But for use by the radio, to compensate the frequency error, we need to find the - // frequency offset "rfcFreqOffset" defined in the following format: - // - // F_nom = F_HPOSC * (1 + rfCoreFreqOffset/(2^22)) - // - // To derive "rfCoreFreqOffset" from "d" we combine the two above equations and get: - // - // (1 + rfCoreFreqOffset/(2^22)) = (1 + d/(2^22))^-1 - // - // Which can be rewritten into: - // - // rfCoreFreqOffset = -d*(2^22) / ((2^22) + d) - // - // = -d * [ 1 / (1 + d/(2^22)) ] - // - // To avoid doing a 64-bit division due to the (1 + d/(2^22))^-1 expression, - // we can use Taylor series (Maclaurin series) to approximate it: - // - // 1 / (1 - x) ~= 1 + x + x^2 + x^3 + x^4 + ... etc (Maclaurin series) - // - // In our case, we have x = - d/(2^22), and we only include up to the first - // order term of the series, as the second order term ((d^2)/(2^44)) is very small: - // - // freqError ~= -d + d^2/(2^22) (+ small approximation error) - // - // The approximation error is negligible for our use. - - int32_t rfCoreFreqOffset = -HPOSC_RelFreqOffset + (( HPOSC_RelFreqOffset * HPOSC_RelFreqOffset ) >> 22 ); - - return ( rfCoreFreqOffset ); -} - -//***************************************************************************** -// -// Compensate the RTC increment based on the relative frequency offset of HPOSC -// -//***************************************************************************** -void -OSC_HPOSCRtcCompensate( int32_t relFreqOffset ) -{ - uint32_t rtcSubSecInc; - uint32_t lfClkFrequency; - uint32_t hfFreq; - int64_t calcFactor; - - // Calculate SCLK_HF frequency, defined as: - // hfFreq = 48000000 * (1 + relFreqOffset/(2^22)) - if( relFreqOffset >= 0 ) - { - calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) + 0x200000 ) / 0x400000; - } - else - { - calcFactor = ( ( 48000000 * (int64_t)relFreqOffset ) - 0x200000 ) / 0x400000; - } - hfFreq = 48000000 + calcFactor; - - // Calculate SCLK_LF frequency, defined as SCLK_LF_FREQ = SCLK_HF_FREQ / 1536 - lfClkFrequency = ( hfFreq + 768 ) / 1536; - - // Calculate SUBSECINC, defined as: SUBSECINC = 2^38 / SCLK_LF_FREQ - rtcSubSecInc = 0x4000000000 / lfClkFrequency; - - /* Update SUBSECINC value */ - SetupSetAonRtcSubSecInc(rtcSubSecInc); -} - -//***************************************************************************** -// -// Get crystal amplitude (assuming crystal is running). -// -//***************************************************************************** -uint32_t -OSCHF_DebugGetCrystalAmplitude( void ) -{ - uint32_t oscCfgRegCopy ; - uint32_t startTime ; - uint32_t deltaTime ; - uint32_t ampValue ; - - // The specified method is as follows: - // 1. Set minimum interval between oscillator amplitude calibrations. - // (Done by setting PER_M=0 and PER_E=1) - // 2. Wait approximately 4 milliseconds in order to measure over a - // moderately large number of calibrations. - // 3. Read out the crystal amplitude value from the peek detector. - // 4. Restore original oscillator amplitude calibrations interval. - // 5. Return crystal amplitude value converted to millivolt. - oscCfgRegCopy = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ); - HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ) = ( 1 << AON_PMCTL_OSCCFG_PER_E_S ); - startTime = AONRTCCurrentCompareValueGet(); - do { - deltaTime = AONRTCCurrentCompareValueGet() - startTime; - } while ( deltaTime < ((uint32_t)( 0.004 * FACTOR_SEC_TO_COMP_VAL_FORMAT ))); - ampValue = ( HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_STAT1 ) & - DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M ) >> - DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S ; - HWREG( AON_PMCTL_BASE + AON_PMCTL_O_OSCCFG ) = oscCfgRegCopy; - - return ( ampValue * 15 ); -} - -//***************************************************************************** -// -// Get the expected average crystal amplitude. -// -//***************************************************************************** -uint32_t -OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ) -{ - uint32_t ampCompTh1 ; - uint32_t highThreshold ; - uint32_t lowThreshold ; - - ampCompTh1 = HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_AMPCOMPTH1 ); - highThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M ) >> - DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S ; - lowThreshold = ( ampCompTh1 & DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M ) >> - DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S ; - - return ((( highThreshold + lowThreshold ) * 15 ) >> 1 ); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h deleted file mode 100644 index 52fe0f30abd..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/osc.h +++ /dev/null @@ -1,730 +0,0 @@ -/****************************************************************************** -* Filename: osc.h -* Revised: 2019-02-14 09:35:31 +0100 (Thu, 14 Feb 2019) -* Revision: 54539 -* -* Description: Defines and prototypes for the system oscillator control. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup osc_api -//! @{ -// -//***************************************************************************** - -#ifndef __OSC_H__ -#define __OSC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_aon_pmctl.h" -#include "../inc/hw_ccfg.h" -#include "../inc/hw_fcfg1.h" -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ddi.h" -#include "../inc/hw_ddi_0_osc.h" -#include "rom.h" -#include "ddi.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define OSCClockSourceSet NOROM_OSCClockSourceSet - #define OSCClockSourceGet NOROM_OSCClockSourceGet - #define OSCHF_GetStartupTime NOROM_OSCHF_GetStartupTime - #define OSCHF_TurnOnXosc NOROM_OSCHF_TurnOnXosc - #define OSCHF_AttemptToSwitchToXosc NOROM_OSCHF_AttemptToSwitchToXosc - #define OSCHF_SwitchToRcOscTurnOffXosc NOROM_OSCHF_SwitchToRcOscTurnOffXosc - #define OSCHF_DebugGetCrystalAmplitude NOROM_OSCHF_DebugGetCrystalAmplitude - #define OSCHF_DebugGetExpectedAverageCrystalAmplitude NOROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude - #define OSC_HPOSC_Debug_InitFreqOffsetParams NOROM_OSC_HPOSC_Debug_InitFreqOffsetParams - #define OSC_HPOSCInitializeFrequencyOffsetParameters NOROM_OSC_HPOSCInitializeFrequencyOffsetParameters - #define OSC_HPOSCRelativeFrequencyOffsetGet NOROM_OSC_HPOSCRelativeFrequencyOffsetGet - #define OSC_AdjustXoscHfCapArray NOROM_OSC_AdjustXoscHfCapArray - #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert NOROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert - #define OSC_HPOSCRtcCompensate NOROM_OSC_HPOSCRtcCompensate -#endif - -//***************************************************************************** -// -// Defines for the High Frequency XTAL Power mode -// -//***************************************************************************** -#define LOW_POWER_XOSC 1 -#define HIGH_POWER_XOSC 0 - -//***************************************************************************** -// -// Defines for the High Frequency XTAL Power mode -// -//***************************************************************************** -#define OSC_SRC_CLK_HF 0x00000001 -#define OSC_SRC_CLK_LF 0x00000004 - -#define OSC_RCOSC_HF 0x00000000 -#define OSC_XOSC_HF 0x00000001 -#define OSC_RCOSC_LF 0x00000002 -#define OSC_XOSC_LF 0x00000003 - -#define SCLK_HF_RCOSC_HF 0 -#define SCLK_HF_XOSC_HF 1 - -#define SCLK_LF_FROM_RCOSC_HF 0 -#define SCLK_LF_FROM_XOSC_HF 1 -#define SCLK_LF_FROM_RCOSC_LF 2 -#define SCLK_LF_FROM_XOSC_LF 3 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Set Power Mode for High Frequency XTAL Oscillator. -//! -//! \param ui32Mode is the power mode for the HF XTAL. -//! - \ref LOW_POWER_XOSC -//! - \ref HIGH_POWER_XOSC -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -OSCXHfPowerModeSet(uint32_t ui32Mode) -{ - // Check the arguments. - ASSERT((ui32Mode == LOW_POWER_XOSC) || - (ui32Mode == HIGH_POWER_XOSC)); - - // Change the power mode. - DDI16BitWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE, - ui32Mode); -} - -//***************************************************************************** -// -//! \brief Enables OSC clock loss event detection. -//! -//! Enables the clock loss event flag to be raised if a clock loss is detected. -//! -//! \note OSC clock loss event must be disabled before SCLK_LF clock source is -//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the -//! change is confirmed (by calling \ref OSCClockSourceGet()). -//! -//! \return None -//! -//! \sa \ref OSCClockLossEventDisable() -// -//***************************************************************************** -__STATIC_INLINE void -OSCClockLossEventEnable( void ) -{ - DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, - DDI_0_OSC_CTL0_CLK_LOSS_EN_M, - DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 1 ); -} - -//***************************************************************************** -// -//! \brief Disables OSC clock loss event detection. -//! -//! Disabling the OSC clock loss event does also clear the clock loss event flag. -//! -//! \note OSC clock loss event must be disabled before SCLK_LF clock source is -//! changed (by calling \ref OSCClockSourceSet()) and remain disabled until the -//! change is confirmed (by calling \ref OSCClockSourceGet()). -//! -//! \return None -//! -//! \sa \ref OSCClockLossEventEnable() -// -//***************************************************************************** -__STATIC_INLINE void -OSCClockLossEventDisable( void ) -{ - DDI16BitfieldWrite( AUX_DDI0_OSC_BASE, DDI_0_OSC_O_CTL0, - DDI_0_OSC_CTL0_CLK_LOSS_EN_M, - DDI_0_OSC_CTL0_CLK_LOSS_EN_S, 0 ); -} - -//***************************************************************************** -// -//! \brief Configure the oscillator input to the a source clock. -//! -//! Use this function to set the oscillator source for one or more of the -//! system source clocks. -//! -//! When selecting the high frequency clock source (OSC_SRC_CLK_HF), this function will not do -//! the actual switch. Enabling the high frequency XTAL can take several hundred -//! micro seconds, so the actual switch is done in a separate function, \ref OSCHfSourceSwitch(), -//! leaving System CPU free to perform other tasks as the XTAL starts up. -//! -//! \note The High Frequency (\ref OSC_SRC_CLK_HF) can only be derived from the -//! high frequency oscillator. The Low Frequency source clock (\ref OSC_SRC_CLK_LF) -//! can be derived from all 4 oscillators. -//! -//! \note If enabling \ref OSC_XOSC_LF it is not safe to go to powerdown/shutdown -//! until the LF clock is running which can be checked using \ref OSCClockSourceGet(). -//! -//! \note Clock loss reset generation must be disabled before SCLK_LF (\ref OSC_SRC_CLK_LF) -//! clock source is changed and remain disabled until the change is confirmed. -//! -//! \param ui32SrcClk is the source clocks to configure. -//! - \ref OSC_SRC_CLK_HF -//! - \ref OSC_SRC_CLK_LF -//! \param ui32Osc is the oscillator that drives the source clock. -//! - \ref OSC_RCOSC_HF -//! - \ref OSC_XOSC_HF -//! - \ref OSC_RCOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF) -//! - \ref OSC_XOSC_LF (only when ui32SrcClk is \ref OSC_SRC_CLK_LF) -//! -//! \sa \ref OSCClockSourceGet(), \ref OSCHfSourceSwitch() -//! -//! \return None -// -//***************************************************************************** -extern void OSCClockSourceSet(uint32_t ui32SrcClk, uint32_t ui32Osc); - -//***************************************************************************** -// -//! \brief Get the source clock settings. -//! -//! Use this function to get the oscillator source for one of the system source -//! clocks. -//! -//! \param ui32SrcClk is the source clock to check. -//! - \ref OSC_SRC_CLK_HF -//! - \ref OSC_SRC_CLK_LF -//! -//! \return Returns the type of oscillator that drives the clock source. -//! - \ref OSC_RCOSC_HF -//! - \ref OSC_XOSC_HF -//! - \ref OSC_RCOSC_LF -//! - \ref OSC_XOSC_LF -//! -//! \sa \ref OSCClockSourceSet(), \ref OSCHfSourceSwitch() -// -//***************************************************************************** -extern uint32_t OSCClockSourceGet(uint32_t ui32SrcClk); - -//***************************************************************************** -// -//! \brief Check if the HF clock source is ready to be switched. -//! -//! If a request to switch the HF clock source has been made, this function -//! can be used to check if the clock source is ready to be switched. -//! -//! Once the HF clock source is ready the switch can be performed by calling -//! the \ref OSCHfSourceSwitch() -//! -//! \return Returns status of HF clock source: -//! - \c true : HF clock source is ready. -//! - \c false : HF clock source is \b not ready. -// -//***************************************************************************** -__STATIC_INLINE bool -OSCHfSourceReady(void) -{ - // Return the readiness of the HF clock source - return (DDI16BitfieldRead(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_STAT0, - DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M, - DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S)) ? - true : false; -} - -//***************************************************************************** -// -//! \brief Switch the high frequency clock. -//! -//! When switching the HF clock source the clock period might be prolonged -//! leaving the clock 'stuck-at' high or low for a few cycles. To ensure that -//! this does not coincide with a read access to the Flash, potentially -//! freezing the device, the HF clock source switch must be executed from ROM. -//! -//! \note This function will not return until the clock source has been -//! switched. It is left to the programmer to ensure, that there is a pending -//! request for a HF clock source switch before this function is called. -//! -//! \return None -//! -//! \sa \ref OSCClockSourceSet() -// -//***************************************************************************** -__STATIC_INLINE void -OSCHfSourceSwitch(void) -{ - // Read target clock (lower half of the 32-bit CTL0 register) - uint16_t hfSrc = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0) & DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M; - - // If target clock source is RCOSC, change clock source for DCDC to RCOSC - if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC) - { - // Force DCDC to use RCOSC before switching SCLK_HF to RCOSC - HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16); - // Dummy read to ensure that the write has propagated - HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); - } - - // Switch the HF clock source - HapiHFSourceSafeSwitch(); - - // If target clock source is XOSC, change clock source for DCDC to "auto" - if(hfSrc == DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC) - { - // Set DCDC clock source back to "auto" after SCLK_HF was switched to XOSC - HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M; - } -} - -//***************************************************************************** -// -//! \brief Identifies if HPOSC is enabled. -//! -//! This function checks if the device supports HPOSC and that HPOSC is selected -//! as HF oscillator for use when the radio is active. -//! -//! \return Returns status of HPOSC functionality: -//! - \c true : HPOSC is enabled. -//! - \c false : HPOSC is not enabled. -// -//***************************************************************************** -__STATIC_INLINE bool -OSC_IsHPOSCEnabled(void) -{ - bool enabled = false; - - if((( HWREG(CCFG_BASE + CCFG_O_MODE_CONF) & CCFG_MODE_CONF_XOSC_FREQ_M) == CCFG_MODE_CONF_XOSC_FREQ_HPOSC) && - (( HWREG(FCFG1_BASE + FCFG1_O_OSC_CONF) & FCFG1_OSC_CONF_HPOSC_OPTION) == 0)) - { - enabled = true; - } - - return (enabled); -} - -//***************************************************************************** -// -//! \brief Identifies if HPOSC is enabled and that SCLK_LF is derived from XOSC_HF. -//! -//! This function checks if the device supports HPOSC and that HPOSC is selected -//! as HF oscillator for use when the radio is active and also that SCLK_LF is -//! derived from XOSC_HF. -//! -//! \return Returns status of HPOSC and SCLK_LF configuration: -//! - \c true : HPOSC is enabled and SCLK_LF is derived from XOSC_HF. -//! - \c false : Either HPOSC not enabled or SCLK_LF is not derived from XOSC_HF. -// -//***************************************************************************** -__STATIC_INLINE bool -OSC_IsHPOSCEnabledWithHfDerivedLfClock(void) -{ - bool enabled = false; - - // Check configuration by reading lower half of the 32-bit CTL0 register - uint16_t regVal = HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); - if( ( ( regVal & DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M ) == DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF ) && - ( ( regVal & DDI_0_OSC_CTL0_HPOSC_MODE_EN_M ) == DDI_0_OSC_CTL0_HPOSC_MODE_EN ) ) - { - enabled = true; - } - - return (enabled); -} - -//***************************************************************************** -// -//! \brief Returns maximum startup time (in microseconds) of XOSC_HF. -//! -//! The startup time depends on several factors. This function calculates the -//! maximum startup time based on statistical information. -//! -//! \param timeUntilWakeupInMs indicates how long time (milliseconds) to the -//! startup will occur. -//! -//! \return Time margin to use in microseconds. -// -//***************************************************************************** -extern uint32_t OSCHF_GetStartupTime( uint32_t timeUntilWakeupInMs ); - -//***************************************************************************** -// -//! \brief Turns on XOSC_HF (but without switching to XOSC_HF). -//! -//! This function simply indicates the need for XOSC_HF to the hardware which -//! initiates the XOSC_HF startup. -//! -//! \return None -// -//***************************************************************************** -extern void OSCHF_TurnOnXosc( void ); - -//***************************************************************************** -// -//! \brief Switch to XOSC_HF if XOSC_HF is ready. -//! -//! This is a non-blocking function checking if the XOSC_HF is ready and -//! performs the switching if ready. The function is somewhat blocking in the -//! case where switching is performed. -//! -//! \return Returns status of the XOSC_HF switching: -//! - \c true : Switching to XOSC_HF has occurred. -//! - \c false : Switching has not occurred. -// -//***************************************************************************** -extern bool OSCHF_AttemptToSwitchToXosc( void ); - -//***************************************************************************** -// -//! \brief Switch to RCOSC_HF and turn off XOSC_HF. -//! -//! This operation takes approximately 50 microseconds (can be shorter if -//! RCOSC_HF already was running). -//! -//! \return None -// -//***************************************************************************** -extern void OSCHF_SwitchToRcOscTurnOffXosc( void ); - -//***************************************************************************** -// -//! \brief Get crystal amplitude (assuming crystal is running). -//! -//! \note This is a debug function only. -//! It is hence not recommended to call this function in normal operation. -//! -//! This function uses an on-chip ADC and peak detector for reading the crystal -//! amplitude. The measurement time is set to 4 milliseconds and this function -//! does not return before the measurement is done. -//! -//! Expected value is \ref OSCHF_DebugGetExpectedAverageCrystalAmplitude +/- 50 millivolt. -//! -//! \return Returns crystal amplitude in millivolt. -//! -//! \sa OSCHF_DebugGetExpectedAverageCrystalAmplitude() -// -//***************************************************************************** -extern uint32_t OSCHF_DebugGetCrystalAmplitude( void ); - -//***************************************************************************** -// -//! \brief Get the expected average crystal amplitude. -//! -//! \note This is a debug function only. -//! It is hence not recommended to call this function in normal operation. -//! -//! This function read the configured high and low thresholds and returns -//! the mean value converted to millivolt. -//! -//! \return Returns expected average crystal amplitude in millivolt. -//! -//! \sa OSCHF_DebugGetCrystalAmplitude() -// -//***************************************************************************** -extern uint32_t OSCHF_DebugGetExpectedAverageCrystalAmplitude( void ); - -//***************************************************************************** -// -//! \brief Data structure for experimental HPOSC polynomials calculation. -//! -//! The structure of the meas_1, meas_2 and meas_3 parameter is -//! as defined in FCFG1_O_HPOSC_MEAS_1, 2 and 3. -//! -//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams() -// -//***************************************************************************** -typedef struct { - uint32_t meas_1 ; //!< Measurement set 1 (typically at room temp) - uint32_t meas_2 ; //!< Measurement set 2 (typically at high temp) - uint32_t meas_3 ; //!< Measurement set 3 (typically at low temp) - int32_t offsetD1 ; //!< Offset to measurement set 1 - int32_t offsetD2 ; //!< Offset to measurement set 2 - int32_t offsetD3 ; //!< Offset to measurement set 3 - int32_t polyP3 ; //!< The P3 polynomial -} HposcDebugData_t; - -//***************************************************************************** -// -//! \brief Debug function to calculate the HPOSC polynomials for experimental data sets. -//! -//! \param pDebugData pointer to the input data collected in \ref HposcDebugData_t -//! -//! \return None -//! -//! \sa OSC_HPOSCInitializeFrequencyOffsetParameters() -// -//***************************************************************************** -extern void OSC_HPOSC_Debug_InitFreqOffsetParams( HposcDebugData_t * pDebugData ); - -//***************************************************************************** -// -//! \brief HPOSC initialization function. Must always be called before using HPOSC. -//! -//! Calculates the fitting curve parameters (polynomials) to used by the -//! HPOSC temperature compensation. -//! -//! \return None -//! -//! \sa OSC_HPOSC_Debug_InitFreqOffsetParams() -// -//***************************************************************************** -extern void OSC_HPOSCInitializeFrequencyOffsetParameters( void ); - -//***************************************************************************** -// -//! \brief Calculate the temperature dependent relative frequency offset of HPOSC -//! -//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature. -//! The frequency offset from the nominal value can be predicted based on -//! second order linear interpolation using coefficients measured in chip -//! production and stored as factory configuration parameters. -//! -//! This function calculates the relative frequency offset, defined as: -//! 
-//!     F_HPOSC = F_nom * (1 + d/(2^22))
-//!
-//! where -//! - F_HPOSC is the current HPOSC frequency. -//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. -//! - d is the relative frequency offset (the value returned). -//! -//! By knowing the relative frequency offset it is then possible to compensate -//! any timing related values accordingly. -//! -//! \param tempDegC is the chip temperature in degrees Celsius. Use the -//! function \ref AONBatMonTemperatureGetDegC() to get current chip temperature. -//! -//! \return Returns the relative frequency offset parameter d. -//! -//! \sa OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert(), AONBatMonTemperatureGetDegC() -// -//***************************************************************************** -extern int32_t OSC_HPOSCRelativeFrequencyOffsetGet( int32_t tempDegC ); - -//***************************************************************************** -// -//! \brief Adjust the XOSC HF cap array relative to the factory setting -//! -//! The cap array factory setting (FCFG) can be converted to a number in the range 0 - 63. -//! Both this function and the customer configuration (CCFG) setting can apply a delta to the FCFG setting. -//! The CCFG setting is automatically applied at boot time (See ../startup_files/ccfg.c). -//! Calling this function will discard the CCFG setting and adjust relative to the FCFG setting. -//! -//! \note Adjusted value will not take effect before XOSC_HF is stopped and restarted -//! -//! \param capArrDelta specifies number of step to adjust the cap array relative to the factory setting. -//! -//! \return None -// -//***************************************************************************** -extern void OSC_AdjustXoscHfCapArray( int32_t capArrDelta ); - -//***************************************************************************** -// -//! \brief Converts the relative frequency offset of HPOSC to the RF Core parameter format. -//! -//! The HPOSC (High Precision Oscillator) clock is used by the RF Core. -//! To compensate for a frequency offset in the frequency of the clock source, -//! a frequency offset parameter can be provided as part of the radio configuration -//! override setting list to enable compensation of the RF synthesizer frequency, -//! symbol timing, and radio timer to still achieve correct frequencies. -//! -//! The RF Core takes a relative frequency offset parameter defined differently -//! compared to the relative frequency offset parameter returned from function -//! \ref OSC_HPOSCRelativeFrequencyOffsetGet() and thus needs to be converted: -//! 
-//!     F_nom = F_HPOSC * (1 + RfCoreRelFreqOffset/(2^22))
-//!
-//! where -//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. -//! - F_HPOSC is the current HPOSC frequency. -//! - RfCoreRelFreqOffset is the relative frequency offset in the "RF Core" format (the value returned). -//! -//! \param HPOSC_RelFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet() -//! -//! \return Returns the relative frequency offset in RF Core format. -//! -//! \sa OSC_HPOSCRelativeFrequencyOffsetGet() -// -//***************************************************************************** -extern int16_t OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert( int32_t HPOSC_RelFreqOffset ); - -//***************************************************************************** -// -//! \brief Compensate the RTC increment based on the relative frequency offset of HPOSC -//! -//! The HPOSC (High Precision Oscillator) frequency will vary slightly with chip temperature. -//! This variation forces the RTC increment to be compensated if SCLK_LF is configured -//! to be derived from the HF clock of HPOSC. -//! This function must only be called if SCLK_LF is configured to be derived from -//! the HF clock of HPOSC. The status of this configuration can be determined -//! by calling the \ref OSC_IsHPOSCEnabledWithHfDerivedLfClock() function. -//! -//! This function first calculates the HPOSC frequency, defined as: -//! 
-//!     F_HPOSC = F_nom * (1 + d/(2^22))
-//!
-//! where -//! - F_HPOSC is the current HPOSC frequency. -//! - F_nom is the nominal oscillator frequency, assumed to be 48.000 MHz. -//! - d is the relative frequency offset given by the input argument relFreqOffset. -//! Then the SCLK_LF frequency is calculated, defined as: -//! 
-//!     F_SCLK_LF = F_HPOSC / 1536
-//!
-//! Then the RTC increment SUBSECINC is calculated, defined as; -//! 
-//!     SUBSECINC = (2^38) / F_SCLK_LF
-//!
-//! Finally the RTC module is updated with the calculated SUBSECINC value. -//! -//! \param relFreqOffset is the relative frequency offset parameter d returned from \ref OSC_HPOSCRelativeFrequencyOffsetGet() -//! -//! \return None -//! -// -//***************************************************************************** -extern void OSC_HPOSCRtcCompensate( int32_t relFreqOffset ); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_OSCClockSourceSet - #undef OSCClockSourceSet - #define OSCClockSourceSet ROM_OSCClockSourceSet - #endif - #ifdef ROM_OSCClockSourceGet - #undef OSCClockSourceGet - #define OSCClockSourceGet ROM_OSCClockSourceGet - #endif - #ifdef ROM_OSCHF_GetStartupTime - #undef OSCHF_GetStartupTime - #define OSCHF_GetStartupTime ROM_OSCHF_GetStartupTime - #endif - #ifdef ROM_OSCHF_TurnOnXosc - #undef OSCHF_TurnOnXosc - #define OSCHF_TurnOnXosc ROM_OSCHF_TurnOnXosc - #endif - #ifdef ROM_OSCHF_AttemptToSwitchToXosc - #undef OSCHF_AttemptToSwitchToXosc - #define OSCHF_AttemptToSwitchToXosc ROM_OSCHF_AttemptToSwitchToXosc - #endif - #ifdef ROM_OSCHF_SwitchToRcOscTurnOffXosc - #undef OSCHF_SwitchToRcOscTurnOffXosc - #define OSCHF_SwitchToRcOscTurnOffXosc ROM_OSCHF_SwitchToRcOscTurnOffXosc - #endif - #ifdef ROM_OSCHF_DebugGetCrystalAmplitude - #undef OSCHF_DebugGetCrystalAmplitude - #define OSCHF_DebugGetCrystalAmplitude ROM_OSCHF_DebugGetCrystalAmplitude - #endif - #ifdef ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude - #undef OSCHF_DebugGetExpectedAverageCrystalAmplitude - #define OSCHF_DebugGetExpectedAverageCrystalAmplitude ROM_OSCHF_DebugGetExpectedAverageCrystalAmplitude - #endif - #ifdef ROM_OSC_HPOSC_Debug_InitFreqOffsetParams - #undef OSC_HPOSC_Debug_InitFreqOffsetParams - #define OSC_HPOSC_Debug_InitFreqOffsetParams ROM_OSC_HPOSC_Debug_InitFreqOffsetParams - #endif - #ifdef ROM_OSC_HPOSCInitializeFrequencyOffsetParameters - #undef OSC_HPOSCInitializeFrequencyOffsetParameters - #define OSC_HPOSCInitializeFrequencyOffsetParameters ROM_OSC_HPOSCInitializeFrequencyOffsetParameters - #endif - #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetGet - #undef OSC_HPOSCRelativeFrequencyOffsetGet - #define OSC_HPOSCRelativeFrequencyOffsetGet ROM_OSC_HPOSCRelativeFrequencyOffsetGet - #endif - #ifdef ROM_OSC_AdjustXoscHfCapArray - #undef OSC_AdjustXoscHfCapArray - #define OSC_AdjustXoscHfCapArray ROM_OSC_AdjustXoscHfCapArray - #endif - #ifdef ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert - #undef OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert - #define OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert - #endif - #ifdef ROM_OSC_HPOSCRtcCompensate - #undef OSC_HPOSCRtcCompensate - #define OSC_HPOSCRtcCompensate ROM_OSC_HPOSCRtcCompensate - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __OSC_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka.c deleted file mode 100644 index 57e4b58182c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka.c +++ /dev/null @@ -1,1661 +0,0 @@ -/****************************************************************************** -* Filename: pka.c -* Revised: 2018-07-19 15:07:05 +0200 (Thu, 19 Jul 2018) -* Revision: 52294 -* -* Description: Driver for the PKA module -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "pka.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef PKAClearPkaRam - #define PKAClearPkaRam NOROM_PKAClearPkaRam - #undef PKAGetOpsStatus - #define PKAGetOpsStatus NOROM_PKAGetOpsStatus - #undef PKAArrayAllZeros - #define PKAArrayAllZeros NOROM_PKAArrayAllZeros - #undef PKAZeroOutArray - #define PKAZeroOutArray NOROM_PKAZeroOutArray - #undef PKABigNumModStart - #define PKABigNumModStart NOROM_PKABigNumModStart - #undef PKABigNumModGetResult - #define PKABigNumModGetResult NOROM_PKABigNumModGetResult - #undef PKABigNumDivideStart - #define PKABigNumDivideStart NOROM_PKABigNumDivideStart - #undef PKABigNumDivideGetQuotient - #define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient - #undef PKABigNumDivideGetRemainder - #define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder - #undef PKABigNumCmpStart - #define PKABigNumCmpStart NOROM_PKABigNumCmpStart - #undef PKABigNumCmpGetResult - #define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult - #undef PKABigNumInvModStart - #define PKABigNumInvModStart NOROM_PKABigNumInvModStart - #undef PKABigNumInvModGetResult - #define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult - #undef PKABigNumMultiplyStart - #define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart - #undef PKABigNumMultGetResult - #define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult - #undef PKABigNumAddStart - #define PKABigNumAddStart NOROM_PKABigNumAddStart - #undef PKABigNumAddGetResult - #define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult - #undef PKABigNumSubStart - #define PKABigNumSubStart NOROM_PKABigNumSubStart - #undef PKABigNumSubGetResult - #define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult - #undef PKAEccMultiplyStart - #define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart - #undef PKAEccMontgomeryMultiplyStart - #define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart - #undef PKAEccMultiplyGetResult - #define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult - #undef PKAEccAddStart - #define PKAEccAddStart NOROM_PKAEccAddStart - #undef PKAEccAddGetResult - #define PKAEccAddGetResult NOROM_PKAEccAddGetResult - #undef PKAEccVerifyPublicKeyWeierstrassStart - #define PKAEccVerifyPublicKeyWeierstrassStart NOROM_PKAEccVerifyPublicKeyWeierstrassStart -#endif - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef PKAClearPkaRam - #define PKAClearPkaRam NOROM_PKAClearPkaRam - #undef PKAGetOpsStatus - #define PKAGetOpsStatus NOROM_PKAGetOpsStatus - #undef PKAArrayAllZeros - #define PKAArrayAllZeros NOROM_PKAArrayAllZeros - #undef PKAZeroOutArray - #define PKAZeroOutArray NOROM_PKAZeroOutArray - #undef PKABigNumModStart - #define PKABigNumModStart NOROM_PKABigNumModStart - #undef PKABigNumModGetResult - #define PKABigNumModGetResult NOROM_PKABigNumModGetResult - #undef PKABigNumDivideStart - #define PKABigNumDivideStart NOROM_PKABigNumDivideStart - #undef PKABigNumDivideGetQuotient - #define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient - #undef PKABigNumDivideGetRemainder - #define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder - #undef PKABigNumCmpStart - #define PKABigNumCmpStart NOROM_PKABigNumCmpStart - #undef PKABigNumCmpGetResult - #define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult - #undef PKABigNumInvModStart - #define PKABigNumInvModStart NOROM_PKABigNumInvModStart - #undef PKABigNumInvModGetResult - #define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult - #undef PKABigNumMultiplyStart - #define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart - #undef PKABigNumMultGetResult - #define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult - #undef PKABigNumAddStart - #define PKABigNumAddStart NOROM_PKABigNumAddStart - #undef PKABigNumAddGetResult - #define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult - #undef PKABigNumSubStart - #define PKABigNumSubStart NOROM_PKABigNumSubStart - #undef PKABigNumSubGetResult - #define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult - #undef PKAEccMultiplyStart - #define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart - #undef PKAEccMontgomeryMultiplyStart - #define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart - #undef PKAEccMultiplyGetResult - #define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult - #undef PKAEccAddStart - #define PKAEccAddStart NOROM_PKAEccAddStart - #undef PKAEccAddGetResult - #define PKAEccAddGetResult NOROM_PKAEccAddGetResult - #undef PKAEccVerifyPublicKeyWeierstrassStart - #define PKAEccVerifyPublicKeyWeierstrassStart NOROM_PKAEccVerifyPublicKeyWeierstrassStart -#endif - - - -#define MAX(x,y) (((x) > (y)) ? (x) : (y)) -#define MIN(x,y) (((x) < (y)) ? (x) : (y)) -#define INRANGE(x,y,z) ((x) > (y) && (x) < (z)) - - -//***************************************************************************** -// -// Define for the maximum curve size supported by the PKA module in 32 bit -// word. -// \note PKA hardware module can support up to 384 bit curve size due to the -// 2K of PKA RAM. -// -//***************************************************************************** -#define PKA_MAX_CURVE_SIZE_32_BIT_WORD 12 - -//***************************************************************************** -// -// Define for the maximum length of the big number supported by the PKA module -// in 32 bit word. -// -//***************************************************************************** -#define PKA_MAX_LEN_IN_32_BIT_WORD PKA_MAX_CURVE_SIZE_32_BIT_WORD - -//***************************************************************************** -// -// Used in PKAWritePkaParam() and PKAWritePkaParamExtraOffset() to specify that -// the base address of the parameter should not be written to a NPTR register. -// -//***************************************************************************** -#define PKA_NO_POINTER_REG 0xFF - -//***************************************************************************** -// -// NIST P224 constants in little endian format. byte[0] is the least -// significant byte and byte[NISTP224_PARAM_SIZE_BYTES - 1] is the most -// significant. -// -//***************************************************************************** -const PKA_EccPoint224 NISTP224_generator = { - .x = {.byte = {0x21, 0x1D, 0x5C, 0x11, 0xD6, 0x80, 0x32, 0x34, - 0x22, 0x11, 0xC2, 0x56, 0xD3, 0xC1, 0x03, 0x4A, - 0xB9, 0x90, 0x13, 0x32, 0x7F, 0xBF, 0xB4, 0x6B, - 0xBD, 0x0C, 0x0E, 0xB7, }}, - .y = {.byte = {0x34, 0x7E, 0x00, 0x85, 0x99, 0x81, 0xD5, 0x44, - 0x64, 0x47, 0x07, 0x5A, 0xA0, 0x75, 0x43, 0xCD, - 0xE6, 0xDF, 0x22, 0x4C, 0xFB, 0x23, 0xF7, 0xB5, - 0x88, 0x63, 0x37, 0xBD, }}, -}; - -const PKA_EccParam224 NISTP224_prime = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF}}; - -const PKA_EccParam224 NISTP224_a = {.byte = {0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF}}; - -const PKA_EccParam224 NISTP224_b = {.byte = {0xB4, 0xFF, 0x55, 0x23, 0x43, 0x39, 0x0B, 0x27, - 0xBA, 0xD8, 0xBF, 0xD7, 0xB7, 0xB0, 0x44, 0x50, - 0x56, 0x32, 0x41, 0xF5, 0xAB, 0xB3, 0x04, 0x0C, - 0x85, 0x0A, 0x05, 0xB4}}; - -const PKA_EccParam224 NISTP224_order = {.byte = {0x3D, 0x2A, 0x5C, 0x5C, 0x45, 0x29, 0xDD, 0x13, - 0x3E, 0xF0, 0xB8, 0xE0, 0xA2, 0x16, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF}}; - -//***************************************************************************** -// -// NIST P256 constants in little endian format. byte[0] is the least -// significant byte and byte[NISTP256_PARAM_SIZE_BYTES - 1] is the most -// significant. -// -//***************************************************************************** -const PKA_EccPoint256 NISTP256_generator = { - .x = {.byte = {0x96, 0xc2, 0x98, 0xd8, 0x45, 0x39, 0xa1, 0xf4, - 0xa0, 0x33, 0xeb, 0x2d, 0x81, 0x7d, 0x03, 0x77, - 0xf2, 0x40, 0xa4, 0x63, 0xe5, 0xe6, 0xbc, 0xf8, - 0x47, 0x42, 0x2c, 0xe1, 0xf2, 0xd1, 0x17, 0x6b}}, - .y = {.byte = {0xf5, 0x51, 0xbf, 0x37, 0x68, 0x40, 0xb6, 0xcb, - 0xce, 0x5e, 0x31, 0x6b, 0x57, 0x33, 0xce, 0x2b, - 0x16, 0x9e, 0x0f, 0x7c, 0x4a, 0xeb, 0xe7, 0x8e, - 0x9b, 0x7f, 0x1a, 0xfe, 0xe2, 0x42, 0xe3, 0x4f}}, -}; - -const PKA_EccParam256 NISTP256_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; - -const PKA_EccParam256 NISTP256_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; - -const PKA_EccParam256 NISTP256_b = {.byte = {0x4b, 0x60, 0xd2, 0x27, 0x3e, 0x3c, 0xce, 0x3b, - 0xf6, 0xb0, 0x53, 0xcc, 0xb0, 0x06, 0x1d, 0x65, - 0xbc, 0x86, 0x98, 0x76, 0x55, 0xbd, 0xeb, 0xb3, - 0xe7, 0x93, 0x3a, 0xaa, 0xd8, 0x35, 0xc6, 0x5a}}; - -const PKA_EccParam256 NISTP256_order = {.byte = {0x51, 0x25, 0x63, 0xfc, 0xc2, 0xca, 0xb9, 0xf3, - 0x84, 0x9e, 0x17, 0xa7, 0xad, 0xfa, 0xe6, 0xbc, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff}}; - -//***************************************************************************** -// -// NIST P384 constants in little endian format. byte[0] is the least -// significant byte and byte[NISTP384_PARAM_SIZE_BYTES - 1] is the most -// significant. -// -//***************************************************************************** -const PKA_EccPoint384 NISTP384_generator = { - .x = {.byte = {0xb7, 0x0a, 0x76, 0x72, 0x38, 0x5e, 0x54, 0x3a, - 0x6c, 0x29, 0x55, 0xbf, 0x5d, 0xf2, 0x02, 0x55, - 0x38, 0x2a, 0x54, 0x82, 0xe0, 0x41, 0xf7, 0x59, - 0x98, 0x9b, 0xa7, 0x8b, 0x62, 0x3b, 0x1d, 0x6e, - 0x74, 0xad, 0x20, 0xf3, 0x1e, 0xc7, 0xb1, 0x8e, - 0x37, 0x05, 0x8b, 0xbe, 0x22, 0xca, 0x87, 0xaa}}, - .y = {.byte = {0x5f, 0x0e, 0xea, 0x90, 0x7c, 0x1d, 0x43, 0x7a, - 0x9d, 0x81, 0x7e, 0x1d, 0xce, 0xb1, 0x60, 0x0a, - 0xc0, 0xb8, 0xf0, 0xb5, 0x13, 0x31, 0xda, 0xe9, - 0x7c, 0x14, 0x9a, 0x28, 0xbd, 0x1d, 0xf4, 0xf8, - 0x29, 0xdc, 0x92, 0x92, 0xbf, 0x98, 0x9e, 0x5d, - 0x6f, 0x2c, 0x26, 0x96, 0x4a, 0xde, 0x17, 0x36,}}, -}; - -const PKA_EccParam384 NISTP384_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, - 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; - -const PKA_EccParam384 NISTP384_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, - 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; - -const PKA_EccParam384 NISTP384_b = {.byte = {0xef, 0x2a, 0xec, 0xd3, 0xed, 0xc8, 0x85, 0x2a, - 0x9d, 0xd1, 0x2e, 0x8a, 0x8d, 0x39, 0x56, 0xc6, - 0x5a, 0x87, 0x13, 0x50, 0x8f, 0x08, 0x14, 0x03, - 0x12, 0x41, 0x81, 0xfe, 0x6e, 0x9c, 0x1d, 0x18, - 0x19, 0x2d, 0xf8, 0xe3, 0x6b, 0x05, 0x8e, 0x98, - 0xe4, 0xe7, 0x3e, 0xe2, 0xa7, 0x2f, 0x31, 0xb3}}; - -const PKA_EccParam384 NISTP384_order = {.byte = {0x73, 0x29, 0xc5, 0xcc, 0x6a, 0x19, 0xec, 0xec, - 0x7a, 0xa7, 0xb0, 0x48, 0xb2, 0x0d, 0x1a, 0x58, - 0xdf, 0x2d, 0x37, 0xf4, 0x81, 0x4d, 0x63, 0xc7, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}}; - - -//***************************************************************************** -// -// NIST P521 constants in little endian format. byte[0] is the least -// significant byte and byte[NISTP521_PARAM_SIZE_BYTES - 1] is the most -// significant. -// -//***************************************************************************** -const PKA_EccPoint521 NISTP521_generator = { - .x = {.byte = {0x66, 0xbd, 0xe5, 0xc2, 0x31, 0x7e, 0x7e, 0xf9, - 0x9b, 0x42, 0x6a, 0x85, 0xc1, 0xb3, 0x48, 0x33, - 0xde, 0xa8, 0xff, 0xa2, 0x27, 0xc1, 0x1d, 0xfe, - 0x28, 0x59, 0xe7, 0xef, 0x77, 0x5e, 0x4b, 0xa1, - 0xba, 0x3d, 0x4d, 0x6b, 0x60, 0xaf, 0x28, 0xf8, - 0x21, 0xb5, 0x3f, 0x05, 0x39, 0x81, 0x64, 0x9c, - 0x42, 0xb4, 0x95, 0x23, 0x66, 0xcb, 0x3e, 0x9e, - 0xcd, 0xe9, 0x04, 0x04, 0xb7, 0x06, 0x8e, 0x85, - 0xc6, 0x00}}, - .y = {.byte = {0x50, 0x66, 0xd1, 0x9f, 0x76, 0x94, 0xbe, 0x88, - 0x40, 0xc2, 0x72, 0xa2, 0x86, 0x70, 0x3c, 0x35, - 0x61, 0x07, 0xad, 0x3f, 0x01, 0xb9, 0x50, 0xc5, - 0x40, 0x26, 0xf4, 0x5e, 0x99, 0x72, 0xee, 0x97, - 0x2c, 0x66, 0x3e, 0x27, 0x17, 0xbd, 0xaf, 0x17, - 0x68, 0x44, 0x9b, 0x57, 0x49, 0x44, 0xf5, 0x98, - 0xd9, 0x1b, 0x7d, 0x2c, 0xb4, 0x5f, 0x8a, 0x5c, - 0x04, 0xc0, 0x3b, 0x9a, 0x78, 0x6a, 0x29, 0x39, - 0x18, 0x01}}, -}; - -const PKA_EccParam521 NISTP521_prime = {.byte = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0x01}}; - -const PKA_EccParam521 NISTP521_a = {.byte = {0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0x01}}; - -const PKA_EccParam521 NISTP521_b = {.byte = {0x00, 0x3f, 0x50, 0x6b, 0xd4, 0x1f, 0x45, 0xef, - 0xf1, 0x34, 0x2c, 0x3d, 0x88, 0xdf, 0x73, 0x35, - 0x07, 0xbf, 0xb1, 0x3b, 0xbd, 0xc0, 0x52, 0x16, - 0x7b, 0x93, 0x7e, 0xec, 0x51, 0x39, 0x19, 0x56, - 0xe1, 0x09, 0xf1, 0x8e, 0x91, 0x89, 0xb4, 0xb8, - 0xf3, 0x15, 0xb3, 0x99, 0x5b, 0x72, 0xda, 0xa2, - 0xee, 0x40, 0x85, 0xb6, 0xa0, 0x21, 0x9a, 0x92, - 0x1f, 0x9a, 0x1c, 0x8e, 0x61, 0xb9, 0x3e, 0x95, - 0x51, 0x00}}; - -const PKA_EccParam521 NISTP521_order = {.byte = {0x09, 0x64, 0x38, 0x91, 0x1e, 0xb7, 0x6f, 0xbb, - 0xae, 0x47, 0x9c, 0x89, 0xb8, 0xc9, 0xb5, 0x3b, - 0xd0, 0xa5, 0x09, 0xf7, 0x48, 0x01, 0xcc, 0x7f, - 0x6b, 0x96, 0x2f, 0xbf, 0x83, 0x87, 0x86, 0x51, - 0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0x01}}; - - -//***************************************************************************** -// -// Brainpool P256r1 constants in little endian format. byte[0] is the least -// significant byte and byte[BrainpoolP256R1_PARAM_SIZE_BYTES - 1] is the most -// significant. -// -//***************************************************************************** -const PKA_EccPoint256 BrainpoolP256R1_generator = { - .x = {.byte = {0x62, 0x32, 0xCE, 0x9A, 0xBD, 0x53, 0x44, 0x3A, - 0xC2, 0x23, 0xBD, 0xE3, 0xE1, 0x27, 0xDE, 0xB9, - 0xAF, 0xB7, 0x81, 0xFC, 0x2F, 0x48, 0x4B, 0x2C, - 0xCB, 0x57, 0x7E, 0xCB, 0xB9, 0xAE, 0xD2, 0x8B}}, - .y = {.byte = {0x97, 0x69, 0x04, 0x2F, 0xC7, 0x54, 0x1D, 0x5C, - 0x54, 0x8E, 0xED, 0x2D, 0x13, 0x45, 0x77, 0xC2, - 0xC9, 0x1D, 0x61, 0x14, 0x1A, 0x46, 0xF8, 0x97, - 0xFD, 0xC4, 0xDA, 0xC3, 0x35, 0xF8, 0x7E, 0x54}}, -}; - -const PKA_EccParam256 BrainpoolP256R1_prime = {.byte = {0x77, 0x53, 0x6E, 0x1F, 0x1D, 0x48, 0x13, 0x20, - 0x28, 0x20, 0x26, 0xD5, 0x23, 0xF6, 0x3B, 0x6E, - 0x72, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E, - 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}}; - -const PKA_EccParam256 BrainpoolP256R1_a = {.byte = {0xD9, 0xB5, 0x30, 0xF3, 0x44, 0x4B, 0x4A, 0xE9, - 0x6C, 0x5C, 0xDC, 0x26, 0xC1, 0x55, 0x80, 0xFB, - 0xE7, 0xFF, 0x7A, 0x41, 0x30, 0x75, 0xF6, 0xEE, - 0x57, 0x30, 0x2C, 0xFC, 0x75, 0x09, 0x5A, 0x7D}}; - -const PKA_EccParam256 BrainpoolP256R1_b = {.byte = {0xB6, 0x07, 0x8C, 0xFF, 0x18, 0xDC, 0xCC, 0x6B, - 0xCE, 0xE1, 0xF7, 0x5C, 0x29, 0x16, 0x84, 0x95, - 0xBF, 0x7C, 0xD7, 0xBB, 0xD9, 0xB5, 0x30, 0xF3, - 0x44, 0x4B, 0x4A, 0xE9, 0x6C, 0x5C, 0xDC, 0x26,}}; - -const PKA_EccParam256 BrainpoolP256R1_order = {.byte = {0xA7, 0x56, 0x48, 0x97, 0x82, 0x0E, 0x1E, 0x90, - 0xF7, 0xA6, 0x61, 0xB5, 0xA3, 0x7A, 0x39, 0x8C, - 0x71, 0x8D, 0x83, 0x9D, 0x90, 0x0A, 0x66, 0x3E, - 0xBC, 0xA9, 0xEE, 0xA1, 0xDB, 0x57, 0xFB, 0xA9}}; - -//***************************************************************************** -// -// Brainpool P384r1 constants in little endian format. byte[0] is the least -// significant byte and byte[BrainpoolP384R1_PARAM_SIZE_BYTES - 1] is the most -// significant. -// -//***************************************************************************** -const PKA_EccPoint384 BrainpoolP384R1_generator = { - .x = {.byte = {0x1E, 0xAF, 0xD4, 0x47, 0xE2, 0xB2, 0x87, 0xEF, - 0xAA, 0x46, 0xD6, 0x36, 0x34, 0xE0, 0x26, 0xE8, - 0xE8, 0x10, 0xBD, 0x0C, 0xFE, 0xCA, 0x7F, 0xDB, - 0xE3, 0x4F, 0xF1, 0x7E, 0xE7, 0xA3, 0x47, 0x88, - 0x6B, 0x3F, 0xC1, 0xB7, 0x81, 0x3A, 0xA6, 0xA2, - 0xFF, 0x45, 0xCF, 0x68, 0xF0, 0x64, 0x1C, 0x1D}}, - .y = {.byte = {0x15, 0x53, 0x3C, 0x26, 0x41, 0x03, 0x82, 0x42, - 0x11, 0x81, 0x91, 0x77, 0x21, 0x46, 0x46, 0x0E, - 0x28, 0x29, 0x91, 0xF9, 0x4F, 0x05, 0x9C, 0xE1, - 0x64, 0x58, 0xEC, 0xFE, 0x29, 0x0B, 0xB7, 0x62, - 0x52, 0xD5, 0xCF, 0x95, 0x8E, 0xEB, 0xB1, 0x5C, - 0xA4, 0xC2, 0xF9, 0x20, 0x75, 0x1D, 0xBE, 0x8A}}, -}; - -const PKA_EccParam384 BrainpoolP384R1_prime = {.byte = {0x53, 0xEC, 0x07, 0x31, 0x13, 0x00, 0x47, 0x87, - 0x71, 0x1A, 0x1D, 0x90, 0x29, 0xA7, 0xD3, 0xAC, - 0x23, 0x11, 0xB7, 0x7F, 0x19, 0xDA, 0xB1, 0x12, - 0xB4, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15, - 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F, - 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}}; - -const PKA_EccParam384 BrainpoolP384R1_a = {.byte = {0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04, - 0xEB, 0xD4, 0x3A, 0x50, 0x4A, 0x81, 0xA5, 0x8A, - 0x0F, 0xF9, 0x91, 0xBA, 0xEF, 0x65, 0x91, 0x13, - 0x87, 0x27, 0xB2, 0x4F, 0x8E, 0xA2, 0xBE, 0xC2, - 0xA0, 0xAF, 0x05, 0xCE, 0x0A, 0x08, 0x72, 0x3C, - 0x0C, 0x15, 0x8C, 0x3D, 0xC6, 0x82, 0xC3, 0x7B}}; - -const PKA_EccParam384 BrainpoolP384R1_b = {.byte = {0x11, 0x4C, 0x50, 0xFA, 0x96, 0x86, 0xB7, 0x3A, - 0x94, 0xC9, 0xDB, 0x95, 0x02, 0x39, 0xB4, 0x7C, - 0xD5, 0x62, 0xEB, 0x3E, 0xA5, 0x0E, 0x88, 0x2E, - 0xA6, 0xD2, 0xDC, 0x07, 0xE1, 0x7D, 0xB7, 0x2F, - 0x7C, 0x44, 0xF0, 0x16, 0x54, 0xB5, 0x39, 0x8B, - 0x26, 0x28, 0xCE, 0x22, 0xDD, 0xC7, 0xA8, 0x04}}; - -const PKA_EccParam384 BrainpoolP384R1_order = {.byte = {0x65, 0x65, 0x04, 0xE9, 0x02, 0x32, 0x88, 0x3B, - 0x10, 0xC3, 0x7F, 0x6B, 0xAF, 0xB6, 0x3A, 0xCF, - 0xA7, 0x25, 0x04, 0xAC, 0x6C, 0x6E, 0x16, 0x1F, - 0xB3, 0x56, 0x54, 0xED, 0x09, 0x71, 0x2F, 0x15, - 0xDF, 0x41, 0xE6, 0x50, 0x7E, 0x6F, 0x5D, 0x0F, - 0x28, 0x6D, 0x38, 0xA3, 0x82, 0x1E, 0xB9, 0x8C}}; - -//***************************************************************************** -// -// Brainpool P512r1 constants in little endian format. byte[0] is the least -// significant byte and byte[BrainpoolP512R1_PARAM_SIZE_BYTES - 1] is the most -// significant. -// -//***************************************************************************** -const PKA_EccPoint512 BrainpoolP512R1_generator = { - .x = {.byte = {0x22, 0xF8, 0xB9, 0xBC, 0x09, 0x22, 0x35, 0x8B, - 0x68, 0x5E, 0x6A, 0x40, 0x47, 0x50, 0x6D, 0x7C, - 0x5F, 0x7D, 0xB9, 0x93, 0x7B, 0x68, 0xD1, 0x50, - 0x8D, 0xD4, 0xD0, 0xE2, 0x78, 0x1F, 0x3B, 0xFF, - 0x8E, 0x09, 0xD0, 0xF4, 0xEE, 0x62, 0x3B, 0xB4, - 0xC1, 0x16, 0xD9, 0xB5, 0x70, 0x9F, 0xED, 0x85, - 0x93, 0x6A, 0x4C, 0x9C, 0x2E, 0x32, 0x21, 0x5A, - 0x64, 0xD9, 0x2E, 0xD8, 0xBD, 0xE4, 0xAE, 0x81}}, - .y = {.byte = {0x92, 0x08, 0xD8, 0x3A, 0x0F, 0x1E, 0xCD, 0x78, - 0x06, 0x54, 0xF0, 0xA8, 0x2F, 0x2B, 0xCA, 0xD1, - 0xAE, 0x63, 0x27, 0x8A, 0xD8, 0x4B, 0xCA, 0x5B, - 0x5E, 0x48, 0x5F, 0x4A, 0x49, 0xDE, 0xDC, 0xB2, - 0x11, 0x81, 0x1F, 0x88, 0x5B, 0xC5, 0x00, 0xA0, - 0x1A, 0x7B, 0xA5, 0x24, 0x00, 0xF7, 0x09, 0xF2, - 0xFD, 0x22, 0x78, 0xCF, 0xA9, 0xBF, 0xEA, 0xC0, - 0xEC, 0x32, 0x63, 0x56, 0x5D, 0x38, 0xDE, 0x7D}}, -}; - -const PKA_EccParam512 BrainpoolP512R1_prime = {.byte = {0xF3, 0x48, 0x3A, 0x58, 0x56, 0x60, 0xAA, 0x28, - 0x85, 0xC6, 0x82, 0x2D, 0x2F, 0xFF, 0x81, 0x28, - 0xE6, 0x80, 0xA3, 0xE6, 0x2A, 0xA1, 0xCD, 0xAE, - 0x42, 0x68, 0xC6, 0x9B, 0x00, 0x9B, 0x4D, 0x7D, - 0x71, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6, - 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB, - 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F, - 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}}; - -const PKA_EccParam512 BrainpoolP512R1_a = {.byte = {0xCA, 0x94, 0xFC, 0x77, 0x4D, 0xAC, 0xC1, 0xE7, - 0xB9, 0xC7, 0xF2, 0x2B, 0xA7, 0x17, 0x11, 0x7F, - 0xB5, 0xC8, 0x9A, 0x8B, 0xC9, 0xF1, 0x2E, 0x0A, - 0xA1, 0x3A, 0x25, 0xA8, 0x5A, 0x5D, 0xED, 0x2D, - 0xBC, 0x63, 0x98, 0xEA, 0xCA, 0x41, 0x34, 0xA8, - 0x10, 0x16, 0xF9, 0x3D, 0x8D, 0xDD, 0xCB, 0x94, - 0xC5, 0x4C, 0x23, 0xAC, 0x45, 0x71, 0x32, 0xE2, - 0x89, 0x3B, 0x60, 0x8B, 0x31, 0xA3, 0x30, 0x78}}; - -const PKA_EccParam512 BrainpoolP512R1_b = {.byte = {0x23, 0xF7, 0x16, 0x80, 0x63, 0xBD, 0x09, 0x28, - 0xDD, 0xE5, 0xBA, 0x5E, 0xB7, 0x50, 0x40, 0x98, - 0x67, 0x3E, 0x08, 0xDC, 0xCA, 0x94, 0xFC, 0x77, - 0x4D, 0xAC, 0xC1, 0xE7, 0xB9, 0xC7, 0xF2, 0x2B, - 0xA7, 0x17, 0x11, 0x7F, 0xB5, 0xC8, 0x9A, 0x8B, - 0xC9, 0xF1, 0x2E, 0x0A, 0xA1, 0x3A, 0x25, 0xA8, - 0x5A, 0x5D, 0xED, 0x2D, 0xBC, 0x63, 0x98, 0xEA, - 0xCA, 0x41, 0x34, 0xA8, 0x10, 0x16, 0xF9, 0x3D}}; - -const PKA_EccParam512 BrainpoolP512R1_order = {.byte = {0x69, 0x00, 0xA9, 0x9C, 0x82, 0x96, 0x87, 0xB5, - 0xDD, 0xDA, 0x5D, 0x08, 0x81, 0xD3, 0xB1, 0x1D, - 0x47, 0x10, 0xAC, 0x7F, 0x19, 0x61, 0x86, 0x41, - 0x19, 0x26, 0xA9, 0x4C, 0x41, 0x5C, 0x3E, 0x55, - 0x70, 0x08, 0x33, 0x70, 0xCA, 0x9C, 0x63, 0xD6, - 0x0E, 0xD2, 0xC9, 0xB3, 0xB3, 0x8D, 0x30, 0xCB, - 0x07, 0xFC, 0xC9, 0x33, 0xAE, 0xE6, 0xD4, 0x3F, - 0x8B, 0xC4, 0xE9, 0xDB, 0xB8, 0x9D, 0xDD, 0xAA}}; - -//***************************************************************************** -// -// Curve25519 constants in little endian format. byte[0] is the least -// significant byte and byte[Curve25519_PARAM_SIZE_BYTES - 1] is the most -// significant. -// -//***************************************************************************** -const PKA_EccPoint256 Curve25519_generator = { - .x = {.byte = {0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}, - .y = {.byte = {0xd9, 0xd3, 0xce, 0x7e, 0xa2, 0xc5, 0xe9, 0x29, - 0xb2, 0x61, 0x7c, 0x6d, 0x7e, 0x4d, 0x3d, 0x92, - 0x4c, 0xd1, 0x48, 0x77, 0x2c, 0xdd, 0x1e, 0xe0, - 0xb4, 0x86, 0xa0, 0xb8, 0xa1, 0x19, 0xae, 0x20}}, -}; - -const PKA_EccParam256 Curve25519_prime = {.byte = {0xed, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7f}}; - -const PKA_EccParam256 Curve25519_a = {.byte = {0x06, 0x6d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; - -const PKA_EccParam256 Curve25519_b = {.byte = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; - -const PKA_EccParam256 Curve25519_order = {.byte = {0xb9, 0xdc, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, - 0xd6, 0x9c, 0xf7, 0xa2, 0xde, 0xf9, 0xde, 0x14, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,}}; - - -//***************************************************************************** -// -// Zeroize PKA RAM. Not threadsafe. -// -//***************************************************************************** -void PKAClearPkaRam(void){ - // Get initial state - uint32_t secdmaclkgr = HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR); - - // OR in zeroize bit - secdmaclkgr |= PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N; - - // Start zeroization - HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr; - - // Wait 256 cycles for PKA RAM to be cleared - CPUdelay(256 / 4); - - // Turn off zeroization - HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) = secdmaclkgr & (~PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N); -} - -//***************************************************************************** -// -// Write a PKA parameter to the PKA module, set required registers, and add an offset. -// -//***************************************************************************** -static uint32_t PKAWritePkaParam(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset) -{ - uint32_t i; - uint32_t *paramWordAlias = (uint32_t *)param; - // Take the floor of paramLength in 32-bit words - uint32_t paramLengthInWords = paramLength / sizeof(uint32_t); - - // Only copy data if it is specified. We may wish to simply allocate another buffer and get - // the required offset. - if (param) { - // Load the number in PKA RAM - for (i = 0; i < paramLengthInWords; i++) { - HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = paramWordAlias[i]; - } - - // If the length is not a word-multiple, fill up a temporary word and copy that in - // to avoid a bus error. The extra zeros at the end should not matter, as the large - // number is little-endian and thus has no effect. - // We could have correctly calculated ceiling(paramLength / sizeof(uint32_t)) above. - // However, we would not have been able to zero-out the extra few most significant - // bytes of the most significant word. That would have resulted in doing maths operations - // on whatever follows param in RAM. - if (paramLength % sizeof(uint32_t)) { - uint32_t temp = 0; - uint8_t j; - - // Load the entire word line of the param remainder - temp = paramWordAlias[i]; - - // Zero-out all bytes beyond the end of the param - for (j = paramLength % sizeof(uint32_t); j < sizeof(uint32_t); j++) { - ((uint8_t *)&temp)[j] = 0; - } - - HWREG(PKA_RAM_BASE + paramOffset + sizeof(uint32_t) * i) = temp; - - // Increment paramLengthInWords since we take the ceiling of length / sizeof(uint32_t) - paramLengthInWords++; - } - } - - // Update the A, B, C, or D pointer with the offset address of the PKA RAM location - // where the number will be stored. - switch (ptrRegOffset) { - case PKA_O_APTR: - HWREG(PKA_BASE + PKA_O_APTR) = paramOffset >> 2; - HWREG(PKA_BASE + PKA_O_ALENGTH) = paramLengthInWords; - break; - case PKA_O_BPTR: - HWREG(PKA_BASE + PKA_O_BPTR) = paramOffset >> 2; - HWREG(PKA_BASE + PKA_O_BLENGTH) = paramLengthInWords; - break; - case PKA_O_CPTR: - HWREG(PKA_BASE + PKA_O_CPTR) = paramOffset >> 2; - break; - case PKA_O_DPTR: - HWREG(PKA_BASE + PKA_O_DPTR) = paramOffset >> 2; - break; - } - - // Ensure 8-byte alignment of next parameter. - // Returns the offset for the next parameter. - return paramOffset + sizeof(uint32_t) * (paramLengthInWords + (paramLengthInWords % 2)); -} - -//***************************************************************************** -// -// Write a PKA parameter to the PKA module but return a larger offset. -// -//***************************************************************************** -static uint32_t PKAWritePkaParamExtraOffset(const uint8_t *param, uint32_t paramLength, uint32_t paramOffset, uint32_t ptrRegOffset) -{ - // Ensure 16-byte alignment. - return (sizeof(uint32_t) * 2) + PKAWritePkaParam(param, paramLength, paramOffset, ptrRegOffset); -} - -//***************************************************************************** -// -// Writes the result of a large number arithmetic operation to a provided buffer. -// -//***************************************************************************** -static uint32_t PKAGetBigNumResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) -{ - uint32_t mswOffset; - uint32_t lswOffset; - uint32_t lengthInWords; - uint32_t i; - uint32_t *resultWordAlias = (uint32_t *)resultBuf; - - // Check the arguments. - ASSERT(resultBuf); - ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && - (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); - - // Verify that the operation is complete. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - // Get the MSW register value. - mswOffset = HWREG(PKA_BASE + PKA_O_MSW); - - // If the result vector is zero, write back one zero byte so the caller does not need - // to handle a special error for the perhaps valid result of zero. - // They will only get the error status if they do not provide a buffer - if (mswOffset & PKA_MSW_RESULT_IS_ZERO_M) { - if (*resultLength){ - if(resultBuf){ - resultBuf[0] = 0; - } - - *resultLength = 1; - - return PKA_STATUS_SUCCESS; - } - else { - return PKA_STATUS_BUF_UNDERFLOW; - } - } - - // Get the length of the result - mswOffset = ((mswOffset & PKA_MSW_MSW_ADDRESS_M) + 1); - lswOffset = ((resultPKAMemAddr - PKA_RAM_BASE) >> 2); - - if (mswOffset >= lswOffset) { - lengthInWords = mswOffset - lswOffset; - } - else { - return PKA_STATUS_RESULT_ADDRESS_INCORRECT; - } - - // Check if the provided buffer length is adequate to store the result data. - if (*resultLength < lengthInWords * sizeof(uint32_t)) { - return PKA_STATUS_BUF_UNDERFLOW; - } - - // Copy the resultant length. - *resultLength = lengthInWords * sizeof(uint32_t); - - - if (resultBuf) { - // Copy the result into the resultBuf. - for (i = 0; i < lengthInWords; i++) { - resultWordAlias[i]= HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); - } - } - - return PKA_STATUS_SUCCESS; -} - -//***************************************************************************** -// -// Retrieve the result of a modulo operation or the remainder of a division. -// -//***************************************************************************** -static uint32_t PKAGetBigNumResultRemainder(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) -{ - uint32_t regMSWVal; - uint32_t lengthInWords; - uint32_t i; - uint32_t *resultWordAlias = (uint32_t *)resultBuf; - - // Check the arguments. - ASSERT(resultBuf); - ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && - (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); - - // Verify that the operation is complete. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - // Get the MSW register value. - regMSWVal = HWREG(PKA_BASE + PKA_O_DIVMSW); - - // If the result vector is zero, write back one zero byte so the caller does not need - // to handle a special error for the perhaps valid result of zero. - // They will only get the error status if they do not provide a buffer - if (regMSWVal & PKA_DIVMSW_RESULT_IS_ZERO_M) { - if (*resultLength){ - if(resultBuf){ - resultBuf[0] = 0; - } - - *resultLength = 1; - - return PKA_STATUS_SUCCESS; - } - else { - return PKA_STATUS_BUF_UNDERFLOW; - } - } - - // Get the length of the result - lengthInWords = ((regMSWVal & PKA_DIVMSW_MSW_ADDRESS_M) + 1) - ((resultPKAMemAddr - PKA_RAM_BASE) >> 2); - - // Check if the provided buffer length is adequate to store the result data. - if (*resultLength < lengthInWords * sizeof(uint32_t)) { - return PKA_STATUS_BUF_UNDERFLOW; - } - - // Copy the resultant length. - *resultLength = lengthInWords * sizeof(uint32_t); - - if (resultBuf) { - // Copy the result into the resultBuf. - for (i = 0; i < lengthInWords; i++) { - resultWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); - } - } - - return PKA_STATUS_SUCCESS; -} - -//***************************************************************************** -// -// Writes the resultant curve point of an ECC operation to the provided buffer. -// -//***************************************************************************** -static uint32_t PKAGetECCResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) -{ - uint32_t i = 0; - uint32_t *xWordAlias = (uint32_t *)curvePointX; - uint32_t *yWordAlias = (uint32_t *)curvePointY; - uint32_t lengthInWordsCeiling = 0; - - // Check for the arguments. - ASSERT(curvePointX); - ASSERT(curvePointY); - ASSERT((resultPKAMemAddr > PKA_RAM_BASE) && - (resultPKAMemAddr < (PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE))); - - // Verify that the operation is completed. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - if (HWREG(PKA_BASE + PKA_O_SHIFT)) { - return PKA_STATUS_FAILURE; - } - - // Check to make sure that the result vector is not the point at infinity. - if (HWREG(PKA_BASE + PKA_O_MSW) & PKA_MSW_RESULT_IS_ZERO) { - return PKA_STATUS_POINT_AT_INFINITY; - } - - if (curvePointX != NULL) { - // Copy the x co-ordinate value of the result from vector D into - // the curvePoint. - for (i = 0; i < (length / sizeof(uint32_t)); i++) { - xWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); - } - - // If the length is not a word-multiple, fill up a temporary word and copy that in - // to avoid a bus error. - if (length % sizeof(uint32_t)) { - uint32_t temp = 0; - uint8_t j; - - // Load the entire word line of the coordinate remainder - temp = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); - - // Write all remaining bytes to the coordinate - for (j = 0; j < length % sizeof(uint32_t); j++) { - curvePointX[i * sizeof(uint32_t) + j] = ((uint8_t *)&temp)[j]; - } - - } - } - - lengthInWordsCeiling = (length % sizeof(uint32_t)) ? length / sizeof(uint32_t) + 1 : length / sizeof(uint32_t); - - resultPKAMemAddr += sizeof(uint32_t) * (2 + lengthInWordsCeiling + (lengthInWordsCeiling % 2)); - - if (curvePointY != NULL) { - // Copy the y co-ordinate value of the result from vector D into - // the curvePoint. - for (i = 0; i < (length / sizeof(uint32_t)); i++) { - yWordAlias[i] = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); - } - - // If the length is not a word-multiple, fill up a temporary word and copy that in - // to avoid a bus error. - if (length % sizeof(uint32_t)) { - uint32_t temp = 0; - uint8_t j; - - // Load the entire word line of the coordinate remainder - temp = HWREG(resultPKAMemAddr + sizeof(uint32_t) * i); - - // Write all remaining bytes to the coordinate - for (j = 0; j < length % sizeof(uint32_t); j++) { - curvePointY[i * sizeof(uint32_t) + j] = ((uint8_t *)&temp)[j]; - } - } - } - - - return PKA_STATUS_SUCCESS; -} - - -//***************************************************************************** -// -// Provides the PKA operation status. -// -//***************************************************************************** -uint32_t PKAGetOpsStatus(void) -{ - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN_M) { - return PKA_STATUS_OPERATION_BUSY; - } - else { - return PKA_STATUS_OPERATION_RDY; - } -} - -//***************************************************************************** -// -// Check if an array consists only of zeros. -// -//***************************************************************************** -bool PKAArrayAllZeros(const uint8_t *array, uint32_t arrayLength) -{ - uint32_t i; - uint8_t arrayBits = 0; - - // We could speed things up by comparing word-wise rather than byte-wise. - // However, this extra overhead is inconsequential compared to running an - // actual PKA operation. Especially ECC operations. - for (i = 0; i < arrayLength; i++) { - arrayBits |= array[i]; - } - - if (arrayBits) { - return false; - } - else { - return true; - } - -} - -//***************************************************************************** -// -// Fill an array with zeros -// -//***************************************************************************** -void PKAZeroOutArray(const uint8_t *array, uint32_t arrayLength) -{ - uint32_t i; - // Take the floor of paramLength in 32-bit words - uint32_t arrayLengthInWords = arrayLength / sizeof(uint32_t); - - // Zero-out the array word-wise until i >= arrayLength - for (i = 0; i < arrayLengthInWords * sizeof(uint32_t); i += 4) { - HWREG(array + i) = 0; - } - - // If i != arrayLength, there are some remaining bytes to zero-out - if (arrayLength % sizeof(uint32_t)) { - // Subtract 4 from i, since i has already overshot the array - for (i -= 4; i < arrayLength; i++) { - HWREGB(array + i * sizeof(uint32_t)); - } - } -} - -//***************************************************************************** -// -// Start the big number modulus operation. -// -//***************************************************************************** -uint32_t PKABigNumModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) -{ - uint32_t offset = 0; - - // Check the arguments. - ASSERT(bigNum); - ASSERT(modulus); - ASSERT(resultPKAMemAddr); - - // Make sure no operation is in progress. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR); - - offset = PKAWritePkaParamExtraOffset(modulus, modulusLength, offset, PKA_O_BPTR); - - // Copy the result vector address location. - *resultPKAMemAddr = PKA_RAM_BASE + offset; - - // Load C pointer with the result location in PKA RAM - HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; - - // Start the PKCP modulo operation by setting the PKA Function register. - HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MODULO); - - return PKA_STATUS_SUCCESS; -} - -//***************************************************************************** -// -// Get the result of the big number modulus operation. -// -//***************************************************************************** -uint32_t PKABigNumModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) -{ - // Zero-out array in case modulo result is shorter than length - PKAZeroOutArray(resultBuf, length); - - return PKAGetBigNumResultRemainder(resultBuf, &length, resultPKAMemAddr); -} - -//***************************************************************************** -// -// Start the big number divide operation. -// -//***************************************************************************** -uint32_t PKABigNumDivideStart(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr) -{ - uint32_t offset = 0; - - // Check the arguments. - ASSERT(dividend); - ASSERT(divisor); - ASSERT(resultQuotientMemAddr); - ASSERT(resultRemainderMemAddr); - - // Make sure no operation is in progress. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - offset = PKAWritePkaParam(dividend, dividendLength, offset, PKA_O_APTR); - - offset = PKAWritePkaParamExtraOffset(divisor, divisorLength, offset, PKA_O_BPTR); - - // Copy the remainder result vector address location. - if (resultRemainderMemAddr) { - *resultRemainderMemAddr = PKA_RAM_BASE + offset; - } - - // The remainder cannot ever be larger than the divisor. It should fit inside - // a buffer of that size. - offset = PKAWritePkaParamExtraOffset(0, divisorLength, offset, PKA_O_CPTR); - - // Copy the remainder result vector address location. - if (resultQuotientMemAddr) { - *resultQuotientMemAddr = PKA_RAM_BASE + offset; - } - - // Load D pointer with the quotient location in PKA RAM - HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; - - // Start the PKCP modulo operation by setting the PKA Function register. - HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_DIVIDE); - - return PKA_STATUS_SUCCESS; -} - -//***************************************************************************** -// -// Get the quotient of the big number divide operation. -// -//***************************************************************************** -uint32_t PKABigNumDivideGetQuotient(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr) -{ - return PKAGetBigNumResult(resultBuf, length, resultQuotientMemAddr); -} - -//***************************************************************************** -// -// Get the remainder of the big number divide operation. -// -//***************************************************************************** -uint32_t PKABigNumDivideGetRemainder(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr) -{ - return PKAGetBigNumResultRemainder(resultBuf, length, resultQuotientMemAddr); -} - - -//***************************************************************************** -// -// Start the comparison of two big numbers. -// -//***************************************************************************** -uint32_t PKABigNumCmpStart(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length) -{ - uint32_t offset = 0; - - // Check the arguments. - ASSERT(bigNum1); - ASSERT(bigNum2); - - // Make sure no operation is in progress. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - offset = PKAWritePkaParam(bigNum1, length, offset, PKA_O_APTR); - - offset = PKAWritePkaParam(bigNum2, length, offset, PKA_O_BPTR); - - // Set the PKA Function register for the Compare operation - // and start the operation. - HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_COMPARE); - - return PKA_STATUS_SUCCESS; -} - -//***************************************************************************** -// -// Get the result of the comparison operation of two big numbers. -// -//***************************************************************************** -uint32_t PKABigNumCmpGetResult(void) -{ - uint32_t status; - - // verify that the operation is complete. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - // Check the COMPARE register. - switch(HWREG(PKA_BASE + PKA_O_COMPARE)) { - case PKA_COMPARE_A_EQUALS_B: - status = PKA_STATUS_EQUAL; - break; - - case PKA_COMPARE_A_GREATER_THAN_B: - status = PKA_STATUS_A_GREATER_THAN_B; - break; - - case PKA_COMPARE_A_LESS_THAN_B: - status = PKA_STATUS_A_LESS_THAN_B; - break; - - default: - status = PKA_STATUS_FAILURE; - break; - } - - return status; -} - -//***************************************************************************** -// -// Start the big number inverse modulo operation. -// -//***************************************************************************** -uint32_t PKABigNumInvModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr) -{ - uint32_t offset = 0; - - // Check the arguments. - ASSERT(bigNum); - ASSERT(modulus); - ASSERT(resultPKAMemAddr); - - // Make sure no operation is in progress. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - offset = PKAWritePkaParam(bigNum, bigNumLength, offset, PKA_O_APTR); - - offset = PKAWritePkaParam(modulus, modulusLength, offset, PKA_O_BPTR); - - // Copy the result vector address location. - *resultPKAMemAddr = PKA_RAM_BASE + offset; - - // Load D pointer with the result location in PKA RAM. - HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; - - // set the PKA function to InvMod operation and the start the operation. - HWREG(PKA_BASE + PKA_O_FUNCTION) = 0x0000F000; - - return PKA_STATUS_SUCCESS; -} - -//***************************************************************************** -// -// Get the result of the big number inverse modulo operation. -// -//***************************************************************************** -uint32_t PKABigNumInvModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr) -{ - // Zero-out array in case modulo result is shorter than length - PKAZeroOutArray(resultBuf, length); - - return PKAGetBigNumResult(resultBuf, &length, resultPKAMemAddr); -} - -//***************************************************************************** -// -// Start the big number multiplication. -// -//***************************************************************************** -uint32_t PKABigNumMultiplyStart(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr) -{ - uint32_t offset = 0; - - // Check for the arguments. - ASSERT(multiplicand); - ASSERT(multiplier); - ASSERT(resultPKAMemAddr); - - // Make sure no operation is in progress. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - offset = PKAWritePkaParam(multiplicand, multiplicandLength, offset, PKA_O_APTR); - - offset = PKAWritePkaParam(multiplier, multiplierLength, offset, PKA_O_BPTR); - - - // Copy the result vector address location. - *resultPKAMemAddr = PKA_RAM_BASE + offset; - - // Load C pointer with the result location in PKA RAM. - HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; - - // Set the PKA function to the multiplication and start it. - HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_MULTIPLY); - - return PKA_STATUS_SUCCESS; -} - -//***************************************************************************** -// -// Get the results of the big number multiplication. -// -//***************************************************************************** -uint32_t PKABigNumMultGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) -{ - return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); -} - -//***************************************************************************** -// -// Start the addition of two big number. -// -//***************************************************************************** -uint32_t PKABigNumAddStart(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr) -{ - uint32_t offset = 0; - - // Check for arguments. - ASSERT(bigNum1); - ASSERT(bigNum2); - ASSERT(resultPKAMemAddr); - - // Make sure no operation is in progress. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - offset = PKAWritePkaParam(bigNum1, bigNum1Length, offset, PKA_O_APTR); - - offset = PKAWritePkaParam(bigNum2, bigNum2Length, offset, PKA_O_BPTR); - - // Copy the result vector address location. - *resultPKAMemAddr = PKA_RAM_BASE + offset; - - // Load C pointer with the result location in PKA RAM. - HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; - - // Set the function for the add operation and start the operation. - HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_ADD); - - return PKA_STATUS_SUCCESS; -} - -//***************************************************************************** -// -// Get the result of the addition operation on two big number. -// -//***************************************************************************** -uint32_t PKABigNumSubGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) -{ - return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); -} - -//***************************************************************************** -// -// Start the addition of two big number. -// -//***************************************************************************** -uint32_t PKABigNumSubStart(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr) -{ - uint32_t offset = 0; - - // Check for arguments. - ASSERT(minuend); - ASSERT(subtrahend); - ASSERT(resultPKAMemAddr); - - - // Make sure no operation is in progress. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - offset = PKAWritePkaParam(minuend, minuendLength, offset, PKA_O_APTR); - - offset = PKAWritePkaParam(subtrahend, subtrahendLength, offset, PKA_O_BPTR); - - // Copy the result vector address location. - *resultPKAMemAddr = PKA_RAM_BASE + offset; - - // Load C pointer with the result location in PKA RAM. - HWREG(PKA_BASE + PKA_O_CPTR) = offset >> 2; - - // Set the function for the add operation and start the operation. - HWREG(PKA_BASE + PKA_O_FUNCTION) = (PKA_FUNCTION_RUN | PKA_FUNCTION_SUBTRACT); - - return PKA_STATUS_SUCCESS; -} - -//***************************************************************************** -// -// Get the result of the addition operation on two big number. -// -//***************************************************************************** -uint32_t PKABigNumAddGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr) -{ - return PKAGetBigNumResult(resultBuf, resultLength, resultPKAMemAddr); -} - - -//***************************************************************************** -// -// Start ECC Multiplication. -// -//***************************************************************************** -uint32_t PKAEccMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr) -{ - uint32_t offset = 0; - - // Check for the arguments. - ASSERT(scalar); - ASSERT(curvePointX); - ASSERT(curvePointY); - ASSERT(prime); - ASSERT(a); - ASSERT(b); - ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t)); - ASSERT(resultPKAMemAddr); - - // Make sure no PKA operation is in progress. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR); - - offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); - offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); - offset = PKAWritePkaParamExtraOffset(b, length, offset, PKA_NO_POINTER_REG); - - offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR); - offset = PKAWritePkaParamExtraOffset(curvePointY, length, offset, PKA_NO_POINTER_REG); - - // Update the result location. - // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity - if (resultPKAMemAddr) { - *resultPKAMemAddr = PKA_RAM_BASE + offset; - } - - // Load D pointer with the result location in PKA RAM. - HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; - - // Set the PKA function to ECC-MULT and start the operation. - HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x05 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); - - return PKA_STATUS_SUCCESS; -} - - -//***************************************************************************** -// -// Start ECC Montgomery Multiplication. -// -//***************************************************************************** -uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr) -{ - uint32_t offset = 0; - - // Check for the arguments. - ASSERT(scalar); - ASSERT(curvePointX); - ASSERT(prime); - ASSERT(a); - ASSERT(length <= PKA_MAX_CURVE_SIZE_32_BIT_WORD * sizeof(uint32_t)); - ASSERT(resultPKAMemAddr); - - // Make sure no PKA operation is in progress. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - offset = PKAWritePkaParam(scalar, length, offset, PKA_O_APTR); - - offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); - offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); - - offset = PKAWritePkaParamExtraOffset(curvePointX, length, offset, PKA_O_CPTR); - - // Update the result location. - // The resultPKAMemAddr may be 0 if we only want to check that we generated the point at infinity - if (resultPKAMemAddr) { - *resultPKAMemAddr = PKA_RAM_BASE + offset; - } - - // Load D pointer with the result location in PKA RAM. - HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; - - // Set the PKA function to Montgomery ECC-MULT and start the operation. - HWREG(PKA_BASE + PKA_O_FUNCTION) = PKA_FUNCTION_RUN_M | (0x02 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); - - return PKA_STATUS_SUCCESS; -} - - -//***************************************************************************** -// -// Get the result of ECC Multiplication -// -//***************************************************************************** -uint32_t PKAEccMultiplyGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) -{ - return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length); -} - -//***************************************************************************** -// -// Start the ECC Addition. -// -//***************************************************************************** -uint32_t PKAEccAddStart(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr) -{ - uint32_t offset = 0; - - // Check for the arguments. - ASSERT(curvePoint1X); - ASSERT(curvePoint1Y); - ASSERT(curvePoint2X); - ASSERT(curvePoint2Y); - ASSERT(prime); - ASSERT(a); - ASSERT(resultPKAMemAddr); - - // Make sure no operation is in progress. - if (HWREG(PKA_BASE + PKA_O_FUNCTION) & PKA_FUNCTION_RUN) { - return PKA_STATUS_OPERATION_BUSY; - } - - offset = PKAWritePkaParamExtraOffset(curvePoint1X, length, offset, PKA_O_APTR); - offset = PKAWritePkaParamExtraOffset(curvePoint1Y, length, offset, PKA_NO_POINTER_REG); - - - offset = PKAWritePkaParamExtraOffset(prime, length, offset, PKA_O_BPTR); - offset = PKAWritePkaParamExtraOffset(a, length, offset, PKA_NO_POINTER_REG); - - offset = PKAWritePkaParamExtraOffset(curvePoint2X, length, offset, PKA_O_CPTR); - offset = PKAWritePkaParamExtraOffset(curvePoint2Y, length, offset, PKA_NO_POINTER_REG); - - // Copy the result vector location. - *resultPKAMemAddr = PKA_RAM_BASE + offset; - - // Load D pointer with the result location in PKA RAM. - HWREG(PKA_BASE + PKA_O_DPTR) = offset >> 2; - - // Set the PKA Function to ECC-ADD and start the operation. - HWREG(PKA_BASE + PKA_O_FUNCTION ) = PKA_FUNCTION_RUN_M | (0x03 << PKA_FUNCTION_SEQUENCER_OPERATIONS_S); - - return PKA_STATUS_SUCCESS; -} - -//***************************************************************************** -// -// Get the result of the ECC Addition -// -//***************************************************************************** -uint32_t PKAEccAddGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length) -{ - return PKAGetECCResult(curvePointX, curvePointY, resultPKAMemAddr, length); -} - -//***************************************************************************** -// -// Verify a public key against the supplied elliptic curve equation -// -//***************************************************************************** -uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length) -{ - uint32_t pkaResult; - uint32_t resultAddress; - uint32_t resultLength; - uint8_t *scratchBuffer = (uint8_t *)(PKA_RAM_BASE + PKA_RAM_TOT_BYTE_SIZE / 2); - uint8_t *scratchBuffer2 = scratchBuffer + 512; - - - // Verify X in range [0, prime - 1] - PKABigNumCmpStart(curvePointX, - prime, - length); - - while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); - - pkaResult = PKABigNumCmpGetResult(); - - if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { - return PKA_STATUS_X_LARGER_THAN_PRIME; - } - - // Verify Y in range [0, prime - 1] - PKABigNumCmpStart(curvePointY, - prime, - length); - - while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); - - pkaResult = PKABigNumCmpGetResult(); - - if (pkaResult != PKA_STATUS_A_LESS_THAN_B) { - return PKA_STATUS_Y_LARGER_THAN_PRIME; - } - - // Verify point on curve - // Short-Weierstrass equation: Y ^ 2 = X ^3 + a * X + b mod P - // Reduced: Y ^ 2 = X * (X ^ 2 + a) + b - - // tmp = X ^ 2 - PKABigNumMultiplyStart(curvePointX, length, curvePointX, length, &resultAddress); - - while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); - - resultLength = 200; - pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); - - if (pkaResult != PKA_STATUS_SUCCESS) { - return PKA_STATUS_FAILURE; - } - - // tmp += a - PKABigNumAddStart(scratchBuffer, resultLength, a, length, &resultAddress); - - while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); - - resultLength = 200; - pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress); - - if (pkaResult != PKA_STATUS_SUCCESS) { - return PKA_STATUS_FAILURE; - } - - // tmp *= x - PKABigNumMultiplyStart(scratchBuffer, resultLength, curvePointX, length, &resultAddress); - - while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); - - resultLength = 200; - pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); - - if (pkaResult != PKA_STATUS_SUCCESS) { - return PKA_STATUS_FAILURE; - } - - // tmp += b - PKABigNumAddStart(scratchBuffer, resultLength, b, length, &resultAddress); - - while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); - - resultLength = 200; - pkaResult = PKABigNumAddGetResult(scratchBuffer, &resultLength, resultAddress); - - if (pkaResult != PKA_STATUS_SUCCESS) { - return PKA_STATUS_FAILURE; - } - - - // tmp2 = tmp % prime to ensure we have no fraction in the division. - // The number will only shrink from here on out. - PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress); - - while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); - - // If the result is not a multiple of the word-length, the PKA HW will round up - // because it deals in words only. That means that using 'length' directly - // would cause and underflow, since length refers to the actual length in bytes of - // the curve parameters while the PKA HW reports that rounded up to the next - // word boundary. - // Use 200 as the resultLength instead since we are copying to the scratch buffer - // anyway. - // Practically, this only happens with curves such as NIST-P521 that are not word - // multiples. - resultLength = 200; - pkaResult = PKABigNumModGetResult(scratchBuffer2, resultLength, resultAddress); - - if (pkaResult != PKA_STATUS_SUCCESS) { - return PKA_STATUS_FAILURE; - } - - // tmp = y^2 - PKABigNumMultiplyStart(curvePointY, length, curvePointY, length, &resultAddress); - - while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); - - resultLength = 200; - pkaResult = PKABigNumMultGetResult(scratchBuffer, &resultLength, resultAddress); - - if (pkaResult != PKA_STATUS_SUCCESS) { - return PKA_STATUS_FAILURE; - } - - // tmp %= prime - PKABigNumModStart(scratchBuffer, resultLength, prime, length, &resultAddress); - - while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); - - // If the result is not a multiple of the word-length, the PKA HW will round up - // because it deals in words only. That means that using 'length' directly - // would cause and underflow, since length refers to the actual length in bytes of - // the curve parameters while the PKA HW reports that rounded up to the next - // word boundary. - // Use 200 as the resultLength instead since we are copying to the scratch buffer - // anyway. - // Practically, this only happens with curves such as NIST-P521 that are not word - // multiples. - resultLength = 200; - pkaResult = PKABigNumModGetResult(scratchBuffer, resultLength, resultAddress); - - if (pkaResult != PKA_STATUS_SUCCESS) { - return PKA_STATUS_FAILURE; - } - - // tmp ?= tmp2 - PKABigNumCmpStart(scratchBuffer, - scratchBuffer2, - length); - - while(PKAGetOpsStatus() == PKA_STATUS_OPERATION_BUSY); - - pkaResult = PKABigNumCmpGetResult(); - - if (pkaResult != PKA_STATUS_EQUAL) { - return PKA_STATUS_POINT_NOT_ON_CURVE; - } - else { - return PKA_STATUS_SUCCESS; - } -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h deleted file mode 100644 index e175ada8d7e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka.h +++ /dev/null @@ -1,1455 +0,0 @@ -/****************************************************************************** -* Filename: pka.h -* Revised: 2018-07-19 15:07:05 +0200 (Thu, 19 Jul 2018) -* Revision: 52294 -* -* Description: PKA header file. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup pka_api -//! @{ -// -//***************************************************************************** - -#ifndef __PKA_H__ -#define __PKA_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_pka.h" -#include "../inc/hw_pka_ram.h" -#include "interrupt.h" -#include "sys_ctrl.h" -#include "debug.h" -#include - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define PKAClearPkaRam NOROM_PKAClearPkaRam - #define PKAGetOpsStatus NOROM_PKAGetOpsStatus - #define PKAArrayAllZeros NOROM_PKAArrayAllZeros - #define PKAZeroOutArray NOROM_PKAZeroOutArray - #define PKABigNumModStart NOROM_PKABigNumModStart - #define PKABigNumModGetResult NOROM_PKABigNumModGetResult - #define PKABigNumDivideStart NOROM_PKABigNumDivideStart - #define PKABigNumDivideGetQuotient NOROM_PKABigNumDivideGetQuotient - #define PKABigNumDivideGetRemainder NOROM_PKABigNumDivideGetRemainder - #define PKABigNumCmpStart NOROM_PKABigNumCmpStart - #define PKABigNumCmpGetResult NOROM_PKABigNumCmpGetResult - #define PKABigNumInvModStart NOROM_PKABigNumInvModStart - #define PKABigNumInvModGetResult NOROM_PKABigNumInvModGetResult - #define PKABigNumMultiplyStart NOROM_PKABigNumMultiplyStart - #define PKABigNumMultGetResult NOROM_PKABigNumMultGetResult - #define PKABigNumAddStart NOROM_PKABigNumAddStart - #define PKABigNumAddGetResult NOROM_PKABigNumAddGetResult - #define PKABigNumSubStart NOROM_PKABigNumSubStart - #define PKABigNumSubGetResult NOROM_PKABigNumSubGetResult - #define PKAEccMultiplyStart NOROM_PKAEccMultiplyStart - #define PKAEccMontgomeryMultiplyStart NOROM_PKAEccMontgomeryMultiplyStart - #define PKAEccMultiplyGetResult NOROM_PKAEccMultiplyGetResult - #define PKAEccAddStart NOROM_PKAEccAddStart - #define PKAEccAddGetResult NOROM_PKAEccAddGetResult - #define PKAEccVerifyPublicKeyWeierstrassStart NOROM_PKAEccVerifyPublicKeyWeierstrassStart -#endif - - - - -//***************************************************************************** -// -// Function return values -// -//***************************************************************************** -#define PKA_STATUS_SUCCESS 0 //!< Success -#define PKA_STATUS_FAILURE 1 //!< Failure -#define PKA_STATUS_INVALID_PARAM 2 //!< Invalid parameter -#define PKA_STATUS_BUF_UNDERFLOW 3 //!< Buffer underflow -#define PKA_STATUS_RESULT_0 4 //!< Result is all zeros -#define PKA_STATUS_A_GREATER_THAN_B 5 //!< Big number compare return status if the first big number is greater than the second. -#define PKA_STATUS_A_LESS_THAN_B 6 //!< Big number compare return status if the first big number is less than the second. -#define PKA_STATUS_EQUAL 7 //!< Big number compare return status if the first big number is equal to the second. -#define PKA_STATUS_OPERATION_BUSY 8 //!< PKA operation is in progress. -#define PKA_STATUS_OPERATION_RDY 9 //!< No PKA operation is in progress. -#define PKA_STATUS_LOCATION_IN_USE 10 //!< Location in PKA RAM is not available -#define PKA_STATUS_X_ZERO 11 //!< X coordinate of public key is 0 -#define PKA_STATUS_Y_ZERO 12 //!< Y coordinate of public key is 0 -#define PKA_STATUS_X_LARGER_THAN_PRIME 13 //!< X coordinate of public key is larger than the curve prime -#define PKA_STATUS_Y_LARGER_THAN_PRIME 14 //!< Y coordinate of public key is larger than the curve prime -#define PKA_STATUS_POINT_NOT_ON_CURVE 15 //!< The public key is not on the specified elliptic curve -#define PKA_STATUS_RESULT_ADDRESS_INCORRECT 16 //!< The address of the result passed into one of the PKA*GetResult functions is incorrect -#define PKA_STATUS_POINT_AT_INFINITY 17 //!< The ECC operation resulted in the point at infinity - - -//***************************************************************************** -// -// Length in bytes of NISTP224 parameters. -// -//***************************************************************************** -#define NISTP224_PARAM_SIZE_BYTES 28 - -//***************************************************************************** -// -// Length in bytes of NISTP256 parameters. -// -//***************************************************************************** -#define NISTP256_PARAM_SIZE_BYTES 32 - -//***************************************************************************** -// -// Length in bytes of NISTP384 parameters. -// -//***************************************************************************** -#define NISTP384_PARAM_SIZE_BYTES 48 - -//***************************************************************************** -// -// Length in bytes of NISTP521 parameters. -// -//***************************************************************************** -#define NISTP521_PARAM_SIZE_BYTES 66 - -//***************************************************************************** -// -// Length in bytes of BrainpoolP256R1 parameters. -// -//***************************************************************************** -#define BrainpoolP256R1_PARAM_SIZE_BYTES 32 - -//***************************************************************************** -// -// Length in bytes of BrainpoolP384R1 parameters. -// -//***************************************************************************** -#define BrainpoolP384R1_PARAM_SIZE_BYTES 48 - -//***************************************************************************** -// -// Length in bytes of BrainpoolP512R1 parameters. -// -//***************************************************************************** -#define BrainpoolP512R1_PARAM_SIZE_BYTES 64 - -//***************************************************************************** -// -// Length in bytes of Curve25519 parameters. -// -//***************************************************************************** -#define Curve25519_PARAM_SIZE_BYTES 32 - -//***************************************************************************** -// -// Union for parameters that forces 32-bit alignment on the byte array. -// -//***************************************************************************** -typedef union { - uint8_t byte[28]; - uint32_t word[28 / sizeof(uint32_t)]; -} PKA_EccParam224; - -typedef union { - uint8_t byte[32]; - uint32_t word[32 / sizeof(uint32_t)]; -} PKA_EccParam256; - -typedef union { - uint8_t byte[48]; - uint32_t word[48 / sizeof(uint32_t)]; -} PKA_EccParam384; - -typedef union { - uint8_t byte[64]; - uint32_t word[64 / sizeof(uint32_t)]; -} PKA_EccParam512; - -typedef union { - uint8_t byte[68]; - uint32_t word[68 / sizeof(uint32_t)]; -} PKA_EccParam521; - -//***************************************************************************** -// -// Struct to keep points in that forces adjacency of X and Y coordinates in -// memmory. -// -//***************************************************************************** - - -typedef struct PKA_EccPoint224_ { - PKA_EccParam224 x; - PKA_EccParam224 y; -} PKA_EccPoint224; - -typedef struct PKA_EccPoint256_ { - PKA_EccParam256 x; - PKA_EccParam256 y; -} PKA_EccPoint256; - -typedef struct PKA_EccPoint384_ { - PKA_EccParam384 x; - PKA_EccParam384 y; -} PKA_EccPoint384; - -typedef struct PKA_EccPoint512_ { - PKA_EccParam512 x; - PKA_EccParam512 y; -} PKA_EccPoint512; - -typedef struct PKA_EccPoint521_ { - PKA_EccParam521 x; - PKA_EccParam521 y; -} PKA_EccPoint521; - - -//***************************************************************************** -// -//! \brief X coordinate of the generator point of the NISTP224 curve. -// -//***************************************************************************** -extern const PKA_EccPoint224 NISTP224_generator; - -//***************************************************************************** -// -//! \brief Prime of the NISTP224 curve. -// -//***************************************************************************** -extern const PKA_EccParam224 NISTP224_prime; - - -//***************************************************************************** -// -//! \brief a constant of the NISTP224 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam224 NISTP224_a; - - -//***************************************************************************** -// -//! \brief b constant of the NISTP224 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam224 NISTP224_b; - - -//***************************************************************************** -// -//! \brief Order of the NISTP224 curve. -// -//***************************************************************************** -extern const PKA_EccParam224 NISTP224_order; - - - - -//***************************************************************************** -// -//! \brief X coordinate of the generator point of the NISTP256 curve. -// -//***************************************************************************** -extern const PKA_EccPoint256 NISTP256_generator; - -//***************************************************************************** -// -//! \brief Prime of the NISTP256 curve. -// -//***************************************************************************** -extern const PKA_EccParam256 NISTP256_prime; - - -//***************************************************************************** -// -//! \brief a constant of the NISTP256 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam256 NISTP256_a; - - -//***************************************************************************** -// -//! \brief b constant of the NISTP256 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam256 NISTP256_b; - - -//***************************************************************************** -// -//! \brief Order of the NISTP256 curve. -// -//***************************************************************************** -extern const PKA_EccParam256 NISTP256_order; - - - - - -//***************************************************************************** -// -//! \brief X coordinate of the generator point of the NISTP384 curve. -// -//***************************************************************************** -extern const PKA_EccPoint384 NISTP384_generator; - -//***************************************************************************** -// -//! \brief Prime of the NISTP384 curve. -// -//***************************************************************************** -extern const PKA_EccParam384 NISTP384_prime; - - -//***************************************************************************** -// -//! \brief a constant of the NISTP384 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam384 NISTP384_a; - - -//***************************************************************************** -// -//! \brief b constant of the NISTP384 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam384 NISTP384_b; - - -//***************************************************************************** -// -//! \brief Order of the NISTP384 curve. -// -//***************************************************************************** -extern const PKA_EccParam384 NISTP384_order; - - - - -//***************************************************************************** -// -//! \brief X coordinate of the generator point of the NISTP521 curve. -// -//***************************************************************************** -extern const PKA_EccPoint521 NISTP521_generator; - -//***************************************************************************** -// -//! \brief Prime of the NISTP521 curve. -// -//***************************************************************************** -extern const PKA_EccParam521 NISTP521_prime; - - -//***************************************************************************** -// -//! \brief a constant of the NISTP521 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam521 NISTP521_a; - - -//***************************************************************************** -// -//! \brief b constant of the NISTP521 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam521 NISTP521_b; - - -//***************************************************************************** -// -//! \brief Order of the NISTP521 curve. -// -//***************************************************************************** -extern const PKA_EccParam521 NISTP521_order; - - - - -//***************************************************************************** -// -//! \brief X coordinate of the generator point of the BrainpoolP256R1 curve. -// -//***************************************************************************** -extern const PKA_EccPoint256 BrainpoolP256R1_generator; - -//***************************************************************************** -// -//! \brief Prime of the BrainpoolP256R1 curve. -// -//***************************************************************************** -extern const PKA_EccParam256 BrainpoolP256R1_prime; - - -//***************************************************************************** -// -//! \brief a constant of the BrainpoolP256R1 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam256 BrainpoolP256R1_a; - - -//***************************************************************************** -// -//! \brief b constant of the BrainpoolP256R1 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam256 BrainpoolP256R1_b; - - -//***************************************************************************** -// -//! \brief Order of the BrainpoolP256R1 curve. -// -//***************************************************************************** -extern const PKA_EccParam256 BrainpoolP256R1_order; - - - - -//***************************************************************************** -// -//! \brief X coordinate of the generator point of the BrainpoolP384R1 curve. -// -//***************************************************************************** -extern const PKA_EccPoint384 BrainpoolP384R1_generator; - -//***************************************************************************** -// -//! \brief Prime of the BrainpoolP384R1 curve. -// -//***************************************************************************** -extern const PKA_EccParam384 BrainpoolP384R1_prime; - - -//***************************************************************************** -// -//! \brief a constant of the BrainpoolP384R1 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam384 BrainpoolP384R1_a; - - -//***************************************************************************** -// -//! \brief b constant of the BrainpoolP384R1 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam384 BrainpoolP384R1_b; - - -//***************************************************************************** -// -//! \brief Order of the BrainpoolP384R1 curve. -// -//***************************************************************************** -extern const PKA_EccParam384 BrainpoolP384R1_order; - - - -//***************************************************************************** -// -//! \brief X coordinate of the generator point of the BrainpoolP512R1 curve. -// -//***************************************************************************** -extern const PKA_EccPoint512 BrainpoolP512R1_generator; - -//***************************************************************************** -// -//! \brief Prime of the BrainpoolP512R1 curve. -// -//***************************************************************************** -extern const PKA_EccParam512 BrainpoolP512R1_prime; - - -//***************************************************************************** -// -//! \brief a constant of the BrainpoolP512R1 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam512 BrainpoolP512R1_a; - - -//***************************************************************************** -// -//! \brief b constant of the BrainpoolP512R1 curve when expressed in short -//! Weierstrass form (y^3 = x^2 + a*x + b). -// -//***************************************************************************** -extern const PKA_EccParam512 BrainpoolP512R1_b; - - -//***************************************************************************** -// -//! \brief Order of the BrainpoolP512R1 curve. -// -//***************************************************************************** -extern const PKA_EccParam512 BrainpoolP512R1_order; - - - -//***************************************************************************** -// -//! \brief X coordinate of the generator point of the Curve25519 curve. -// -//***************************************************************************** -extern const PKA_EccPoint256 Curve25519_generator; - -//***************************************************************************** -// -//! \brief Prime of the Curve25519 curve. -// -//***************************************************************************** -extern const PKA_EccParam256 Curve25519_prime; - - -//***************************************************************************** -// -//! \brief a constant of the Curve25519 curve when expressed in Montgomery -//! form (By^2 = x^3 + a*x^2 + x). -// -//***************************************************************************** -extern const PKA_EccParam256 Curve25519_a; - - -//***************************************************************************** -// -//! \brief b constant of the Curve25519 curve when expressed in Montgomery -//! form (By^2 = x^3 + a*x^2 + x). -// -//***************************************************************************** -extern const PKA_EccParam256 Curve25519_b; - - -//***************************************************************************** -// -//! \brief Order of the Curve25519 curve. -// -//***************************************************************************** -extern const PKA_EccParam256 Curve25519_order; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Zeroizes PKA RAM. -//! -//! This function uses the zeroization function in PRCM to clear the PKA RAM. -// -//***************************************************************************** -extern void PKAClearPkaRam(void); - -//***************************************************************************** -// -//! \brief Gets the PKA operation status. -//! -//! This function gets information on whether any PKA operation is in -//! progress or not. This function allows to check the PKA operation status -//! before starting any new PKA operation. -//! -//! \return Returns a status code. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA operation is in progress. -//! - \ref PKA_STATUS_OPERATION_RDY if the PKA operation is not in progress. -// -//***************************************************************************** -extern uint32_t PKAGetOpsStatus(void); - -//***************************************************************************** -// -//! \brief Checks whether and array only consists of zeros -//! -//! \param [in] array is the array to check. -//! -//! \param [in] arrayLength is the length of the array. -//! -//! \return Returns true if the array contains only zeros and false if one -//! or more bits are set. -// -//***************************************************************************** -extern bool PKAArrayAllZeros(const uint8_t *array, uint32_t arrayLength); - -//***************************************************************************** -// -//! \brief Zeros-out an array -//! -//! \param [in] array is the array to zero-out. -//! -//! \param [in] arrayLength is the length of the array. -// -//***************************************************************************** -extern void PKAZeroOutArray(const uint8_t *array, uint32_t arrayLength); - -//***************************************************************************** -// -//! \brief Starts a big number modulus operation. -//! -//! This function starts the modulo operation on the big number \c bigNum -//! using the divisor \c modulus. The PKA RAM location where the result -//! will be available is stored in \c resultPKAMemAddr. -//! -//! \param [in] bigNum is the pointer to the big number on which modulo operation -//! needs to be carried out. -//! -//! \param [in] bigNumLength is the size of the big number \c bigNum in bytes. -//! -//! \param [in] modulus is the pointer to the divisor. -//! -//! \param [in] modulusLength is the size of the divisor \c modulus in bytes. -//! -//! \param [out] resultPKAMemAddr is the pointer to the result vector location -//! which will be set by this function. -//! -//!\return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. -//! - \ref PKA_STATUS_OPERATION_BUSY, if the PKA module is busy doing -//! some other operation. -//! -//! \sa PKABigNumModGetResult() -// -//***************************************************************************** -extern uint32_t PKABigNumModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr); - -//***************************************************************************** -// -//! \brief Gets the result of the big number modulus operation. -//! -//! This function gets the result of the big number modulus operation which was -//! previously started using the function PKABigNumModStart(). -//! The function will zero-out \c resultBuf prior to copying in the result of -//! the modulo operation. -//! -//! \param [out] resultBuf is the pointer to buffer where the result needs to -//! be stored. -//! -//! \param [in] length is the size of the provided buffer in bytes. -//! -//! \param [in] resultPKAMemAddr is the address of the result location which -//! was provided by the start function PKABigNumModStart(). -//! -//! \return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing -//! the operation. -//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. -//! - \ref PKA_STATUS_BUF_UNDERFLOW if the \c length is less than the length -//! of the result. -//! -//! \sa PKABigNumModStart() -// -//***************************************************************************** -extern uint32_t PKABigNumModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr); - -//***************************************************************************** -// -//! \brief Starts a big number divide operation. -//! -//! This function starts the dive operation on the big number \c bigNum -//! using the \c divisor. The PKA RAM location where the result -//! will be available is stored in \c resultPKAMemAddr. -//! -//! \param [in] dividend is the pointer to the big number to be divided. -//! -//! \param [in] dividendLength is the size of the big number \c dividend in bytes. -//! -//! \param [in] divisor is the pointer to the divisor. -//! -//! \param [in] divisorLength is the size of the \c divisor in bytes. -//! -//! \param [out] resultQuotientMemAddr is the pointer to the quotient vector location -//! which will be set by this function. -//! -//! \param [out] resultRemainderMemAddr is the pointer to the remainder vector location -//! which will be set by this function. -//! -//!\return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. -//! - \ref PKA_STATUS_OPERATION_BUSY, if the PKA module is busy doing -//! some other operation. -//! -//! \sa PKABigNumDivideGetResult() -// -//***************************************************************************** -extern uint32_t PKABigNumDivideStart(const uint8_t *dividend, - uint32_t dividendLength, - const uint8_t *divisor, - uint32_t divisorLength, - uint32_t *resultQuotientMemAddr, - uint32_t *resultRemainderMemAddr); - -//***************************************************************************** -// -//! \brief Gets the quotient of the big number divide operation. -//! -//! This function gets the quotient of the big number divide operation which was -//! previously started using the function PKABigNumDivideStart(). -//! -//! \param [out] resultBuf is the pointer to buffer where the result needs to -//! be stored. -//! -//! \param [in] length is the size of the provided buffer in bytes. -//! -//! \param [in] resultQuotientMemAddr is the address of the result location which -//! was provided by the start function PKABigNumDivideStart(). -//! -//! \return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing -//! the operation. -//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. -//! - \ref PKA_STATUS_BUF_UNDERFLOW if the \c length is less than the length -//! of the result. -//! -//! \sa PKABigNumDivideStart() -// -//***************************************************************************** -extern uint32_t PKABigNumDivideGetQuotient(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr); - -//***************************************************************************** -// -//! \brief Gets the remainder of the big number divide operation. -//! -//! This function gets the remainder of the big number divide operation which was -//! previously started using the function PKABigNumDivideStart(). -//! -//! \param [out] resultBuf is the pointer to buffer where the result needs to -//! be stored. -//! -//! \param [in] length is the size of the provided buffer in bytes. -//! -//! \param [in] resultRemainderMemAddr is the address of the result location which -//! was provided by the start function PKABigNumDivideStart(). -//! -//! \return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing -//! the operation. -//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. -//! - \ref PKA_STATUS_BUF_UNDERFLOW if the \c length is less than the length -//! of the result. -//! -//! \sa PKABigNumDivideStart() -// -//***************************************************************************** -extern uint32_t PKABigNumDivideGetRemainder(uint8_t *resultBuf, uint32_t *length, uint32_t resultRemainderMemAddr); - -//***************************************************************************** -// -//! \brief Starts the comparison of two big numbers. -//! -//! This function starts the comparison of two big numbers pointed by -//! \c bigNum1 and \c bigNum2. -//! -//! \note \c bigNum1 and \c bigNum2 must have same size. -//! -//! \param [in] bigNum1 is the pointer to the first big number. -//! -//! \param [in] bigNum2 is the pointer to the second big number. -//! -//! \param [in] length is the size of the big numbers in bytes. -//! -//!\return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing -//! some other operation. -//! -//! \sa PKABigNumCmpGetResult() -// -//***************************************************************************** -extern uint32_t PKABigNumCmpStart(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length); - -//***************************************************************************** -// -//! \brief Gets the result of the comparison operation of two big numbers. -//! -//! This function provides the results of the comparison of two big numbers -//! which was started using the PKABigNumCmpStart(). -//! -//! \return Returns a status code. -//! - \ref PKA_STATUS_OPERATION_BUSY if the operation is in progress. -//! - \ref PKA_STATUS_SUCCESS if the two big numbers are equal. -//! - \ref PKA_STATUS_A_GREATER_THAN_B if the first number is greater than the second. -//! - \ref PKA_STATUS_A_LESS_THAN_B if the first number is less than the second. -//! -//! \sa PKABigNumCmpStart() -// -//***************************************************************************** -extern uint32_t PKABigNumCmpGetResult(void); - -//***************************************************************************** -// -//! \brief Starts a big number inverse modulo operation. -//! -//! This function starts the inverse modulo operation on \c bigNum -//! using the divisor \c modulus. -//! -//! \param [in] bigNum is the pointer to the buffer containing the big number -//! (dividend). -//! -//! \param [in] bigNumLength is the size of the \c bigNum in bytes. -//! -//! \param [in] modulus is the pointer to the buffer containing the divisor. -//! -//! \param [in] modulusLength is the size of the divisor in bytes. -//! -//! \param [out] resultPKAMemAddr is the pointer to the result vector location -//! which will be set by this function. -//! -//! -//!\return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing -//! some other operation. -//! -//! \sa PKABigNumInvModGetResult() -// -//***************************************************************************** -extern uint32_t PKABigNumInvModStart(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr); - - -//***************************************************************************** -// -//! \brief Gets the result of the big number inverse modulo operation. -//! -//! This function gets the result of the big number inverse modulo operation -//! previously started using the function PKABigNumInvModStart(). -//! The function will zero-out \c resultBuf prior to copying in the result of -//! the inverse modulo operation. -//! -//! \param [out] resultBuf is the pointer to buffer where the result needs to be -//! stored. -//! -//! \param [in] length is the size of the provided buffer in bytes. -//! -//! \param [in] resultPKAMemAddr is the address of the result location which -//! was provided by the start function PKABigNumInvModStart(). -//! -//! \return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if the operation is successful. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing -//! the operation. -//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. -//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less -//! than the result. -//! -//! \sa PKABigNumInvModStart() -// -//***************************************************************************** -extern uint32_t PKABigNumInvModGetResult(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr); - - -//***************************************************************************** -// -//! \brief Starts the multiplication of two big numbers. -//! -//! \param [in] multiplicand is the pointer to the buffer containing the big -//! number multiplicand. -//! -//! \param [in] multiplicandLength is the size of the multiplicand in bytes. -//! -//! \param [in] multiplier is the pointer to the buffer containing the big -//! number multiplier. -//! -//! \param [in] multiplierLength is the size of the multiplier in bytes. -//! -//! \param [out] resultPKAMemAddr is the pointer to the result vector location -//! which will be set by this function. -//! -//!\return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing -//! some other operation. -//! -//! \sa PKABigNumMultGetResult() -// -//***************************************************************************** -extern uint32_t PKABigNumMultiplyStart(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr); - - -//***************************************************************************** -// -//! \brief Gets the result of the big number multiplication. -//! -//! This function gets the result of the multiplication of two big numbers -//! operation previously started using the function PKABigNumMultiplyStart(). -//! -//! \param [out] resultBuf is the pointer to buffer where the result needs to be -//! stored. -//! -//! \param [in, out] resultLength is the address of the variable containing the length of the -//! buffer in bytes. After the operation, the actual length of the resultant is stored -//! at this address. -//! -//! \param [in] resultPKAMemAddr is the address of the result location which -//! was provided by the start function PKABigNumMultiplyStart(). -//! -//! \return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if the operation is successful. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing -//! the operation. -//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. -//! - \ref PKA_STATUS_FAILURE if the operation is not successful. -//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less -//! then the length of the result. -//! -//! \sa PKABigNumMultiplyStart() -// -//***************************************************************************** -extern uint32_t PKABigNumMultGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr); - -//***************************************************************************** -// -//! \brief Starts the addition of two big numbers. -//! -//! \param [in] bigNum1 is the pointer to the buffer containing the first -//! big number. -//! -//! \param [in] bigNum1Length is the size of the first big number in bytes. -//! -//! \param [in] bigNum2 is the pointer to the buffer containing the second -//! big number. -//! -//! \param [in] bigNum2Length is the size of the second big number in bytes. -//! -//! \param [out] resultPKAMemAddr is the pointer to the result vector location -//! which will be set by this function. -//! -//!\return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing -//! some other operation. -//! -//! \sa PKABigNumAddGetResult() -// -//***************************************************************************** -extern uint32_t PKABigNumAddStart(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr); - -//***************************************************************************** -// -//! \brief Gets the result of the addition operation on two big numbers. -//! -//! \param [out] resultBuf is the pointer to buffer where the result -//! needs to be stored. -//! -//! \param [in, out] resultLength is the address of the variable containing -//! the length of the buffer. After the operation the actual length of the -//! resultant is stored at this address. -//! -//! \param [in] resultPKAMemAddr is the address of the result location which -//! was provided by the start function PKABigNumAddStart(). -//! -//! -//! \return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if the operation is successful. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing -//! the operation. -//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. -//! - \ref PKA_STATUS_FAILURE if the operation is not successful. -//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less -//! then the length of the result. -//! -//! \sa PKABigNumAddStart() -// -//***************************************************************************** -extern uint32_t PKABigNumAddGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr); - -//***************************************************************************** -// -//! \brief Starts the subtraction of one big number from another. -//! -//! \param [in] minuend is the pointer to the buffer containing the big number -//! to be subtracted from. -//! -//! \param [in] minuendLength is the size of the minuend in bytes. -//! -//! \param [in] subtrahend is the pointer to the buffer containing the big -//! number to subtract from the \c minuend. -//! -//! \param [in] subtrahendLength is the size of the subtrahend in bytes. -//! -//! \param [out] resultPKAMemAddr is the pointer to the result vector location -//! which will be set by this function. -//! -//!\return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing -//! some other operation. -//! -//! \sa PKABigNumSubGetResult() -// -//***************************************************************************** -extern uint32_t PKABigNumSubStart(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr); - -//***************************************************************************** -// -//! \brief Gets the result of the subtraction operation on two big numbers. -//! -//! \param [out] resultBuf is the pointer to buffer where the result -//! needs to be stored. -//! -//! \param [in, out] resultLength is the address of the variable containing -//! the length of the buffer. After the operation the actual length of the -//! resultant is stored at this address. -//! -//! \param [in] resultPKAMemAddr is the address of the result location which -//! was provided by the start function PKABigNumAddStart(). -//! -//! -//! \return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if the operation is successful. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing -//! the operation. -//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. -//! - \ref PKA_STATUS_FAILURE if the operation is not successful. -//! - \ref PKA_STATUS_BUF_UNDERFLOW if the length of the provided buffer is less -//! then the length of the result. -//! -//! \sa PKABigNumSubStart() -// -//***************************************************************************** -extern uint32_t PKABigNumSubGetResult(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr); - -//***************************************************************************** -// -//! \brief Starts ECC multiplication. -//! -//! \param [in] scalar is pointer to the buffer containing the scalar -//! value to be multiplied. -//! -//! \param [in] curvePointX is the pointer to the buffer containing the -//! X coordinate of the elliptic curve point to be multiplied. -//! The point must be on the given curve. -//! -//! \param [in] curvePointY is the pointer to the buffer containing the -//! Y coordinate of the elliptic curve point to be multiplied. -//! The point must be on the given curve. -//! -//! \param [in] prime is the prime of the curve. -//! -//! \param [in] a is the a constant of the curve when the curve equation is expressed -//! in short Weierstrass form (y^3 = x^2 + a*x + b). -//! -//! \param [in] b is the b constant of the curve when the curve equation is expressed -//! in short Weierstrass form (y^3 = x^2 + a*x + b). -//! -//! \param [in] length is the length of the curve parameters in bytes. -//! -//! \param [out] resultPKAMemAddr is the pointer to the result vector location -//! which will be set by this function. -//! -//!\return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing -//! some other operation. -//! -//! \sa PKAEccMultiplyGetResult() -// -//***************************************************************************** -extern uint32_t PKAEccMultiplyStart(const uint8_t *scalar, - const uint8_t *curvePointX, - const uint8_t *curvePointY, - const uint8_t *prime, - const uint8_t *a, - const uint8_t *b, - uint32_t length, - uint32_t *resultPKAMemAddr); - -//***************************************************************************** -// -//! \brief Starts ECC Montgomery multiplication. -//! -//! \param [in] scalar is pointer to the buffer containing the scalar -//! value to be multiplied. -//! -//! \param [in] curvePointX is the pointer to the buffer containing the -//! X coordinate of the elliptic curve point to be multiplied. -//! The point must be on the given curve. -//! -//! \param [in] prime is the prime of the curve. -//! -//! \param [in] a is the a constant of the curve when the curve equation is expressed -//! in short Weierstrass form (y^3 = x^2 + a*x + b). -//! -//! \param [in] length is the length of the curve parameters in bytes. -//! -//! \param [out] resultPKAMemAddr is the pointer to the result vector location -//! which will be set by this function. -//! -//!\return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing -//! some other operation. -//! -//! \sa PKAEccMultiplyGetResult() -// -//***************************************************************************** -extern uint32_t PKAEccMontgomeryMultiplyStart(const uint8_t *scalar, - const uint8_t *curvePointX, - const uint8_t *prime, - const uint8_t *a, - uint32_t length, - uint32_t *resultPKAMemAddr); - -//***************************************************************************** -// -//! \brief Gets the result of ECC multiplication -//! -//! This function gets the result of ECC point multiplication operation on the -//! EC point and the scalar value, previously started using the function -//! PKAEccMultiplyStart(). -//! -//! \param [out] curvePointX is the pointer to the structure where the X coordinate -//! of the resultant EC point will be stored. -//! -//! \param [out] curvePointY is the pointer to the structure where the Y coordinate -//! of the resultant EC point will be stored. -//! -//! \param [in] resultPKAMemAddr is the address of the result location which -//! was provided by the start function PKAEccMultiplyStart(). -//! -//! \param [in] length is the length of the curve parameters in bytes. -//! -//! \return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if the operation is successful. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing -//! the operation. -//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. -//! - \ref PKA_STATUS_FAILURE if the operation is not successful. -//! -//! \sa PKAEccMultiplyStart() -// -//***************************************************************************** -extern uint32_t PKAEccMultiplyGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length); - -//***************************************************************************** -// -//! \brief Starts the ECC addition. -//! -//! \param [in] curvePoint1X is the pointer to the buffer containing the -//! X coordinate of the first elliptic curve point to be added. -//! The point must be on the given curve. -//! -//! \param [in] curvePoint1Y is the pointer to the buffer containing the -//! Y coordinate of the first elliptic curve point to be added. -//! The point must be on the given curve. -//! -//! \param [in] curvePoint2X is the pointer to the buffer containing the -//! X coordinate of the second elliptic curve point to be added. -//! The point must be on the given curve. -//! -//! \param [in] curvePoint2Y is the pointer to the buffer containing the -//! Y coordinate of the second elliptic curve point to be added. -//! The point must be on the given curve. -//! -//! \param [in] prime is the prime of the curve. -//! -//! \param [in] a is the a constant of the curve when the curve equation is expressed -//! in short Weierstrass form (y^3 = x^2 + a*x + b). -//! -//! \param [in] length is the length of the curve parameters in bytes. -//! -//! \param [out] resultPKAMemAddr is the pointer to the result vector location -//! which will be set by this function. -//! -//!\return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if successful in starting the operation. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy doing -//! some other operation. -//! -//! \sa PKAEccAddGetResult() -// -//***************************************************************************** -extern uint32_t PKAEccAddStart(const uint8_t *curvePoint1X, - const uint8_t *curvePoint1Y, - const uint8_t *curvePoint2X, - const uint8_t *curvePoint2Y, - const uint8_t *prime, - const uint8_t *a, - uint32_t length, - uint32_t *resultPKAMemAddr); - -//***************************************************************************** -// -//! \brief Gets the result of the ECC addition -//! -//! This function gets the result of ECC point addition operation on the -//! on the two given EC points, previously started using the function -//! PKAEccAddStart(). -//! -//! \param [out] curvePointX is the pointer to the structure where the X coordinate -//! of the resultant EC point will be stored. -//! -//! \param [out] curvePointY is the pointer to the structure where the Y coordinate -//! of the resultant EC point will be stored. -//! -//! \param [in] resultPKAMemAddr is the address of the result location which -//! was provided by the start function PKAEccAddGetResult(). -//! -//! \param [in] length is the length of the curve parameters in bytes. -//! -//! \return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if the operation is successful. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing the operation. -//! - \ref PKA_STATUS_RESULT_0 if the result is all zeros. -//! - \ref PKA_STATUS_FAILURE if the operation is not successful. -//! -//! \sa PKAEccAddStart() -// -//***************************************************************************** -extern uint32_t PKAEccAddGetResult(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length); - - -//***************************************************************************** -// -//! \brief Begins the validation of a public key against a Short-Weierstrass curve -//! -//! This function validates a public key against a curve. -//! After performing multiple smaller PKA operations in polling mode, -//! it starts an ECC scalar multiplication. -//! -//! The function verifies that: -//! - X and Y are in the range [1, prime - 1] -//! - The point is not the point at infinity -//! - X and Y satisfy the Short-Weierstrass curve equation Y^2 = X^3 + a*X + b mod P -//! - Multiplying the point by the order of the curve yields the point at infinity -//! -//! \param [in] curvePointX is the pointer to the buffer containing the -//! X coordinate of the elliptic curve point to verify. -//! -//! \param [in] curvePointY is the pointer to the buffer containing the -//! Y coordinate of the elliptic curve point to verify. -//! -//! \param [in] prime is the prime of the curve. -//! -//! \param [in] a is the a constant of the curve when the curve equation is expressed -//! in Short-Weierstrass form (y^3 = x^2 + a*x + b). -//! -//! \param [in] b is the b constant of the curve when the curve equation is expressed -//! in Short-Weierstrass form (y^3 = x^2 + a*x + b). -//! -//! \param [in] order is the order of the curve. -//! -//! \param [in] length is the length of the curve parameters in bytes. -//! -//! \return Returns a status code. -//! - \ref PKA_STATUS_SUCCESS if the operation is successful. -//! - \ref PKA_STATUS_OPERATION_BUSY if the PKA module is busy performing the operation. -//! - \ref PKA_STATUS_FAILURE if the operation is not successful. -//! - \ref PKA_STATUS_X_ZERO if X is zero. -//! - \ref PKA_STATUS_Y_ZERO if Y is zero. -//! - \ref PKA_STATUS_X_LARGER_THAN_PRIME if X is larger than the curve prime -//! - \ref PKA_STATUS_Y_LARGER_THAN_PRIME if Y is larger than the curve prime -//! - \ref PKA_STATUS_POINT_NOT_ON_CURVE if X and Y do not satisfy the curve equation -//! -//! \sa PKAEccVerifyPublicKeyGetResult() -// -//***************************************************************************** -extern uint32_t PKAEccVerifyPublicKeyWeierstrassStart(const uint8_t *curvePointX, - const uint8_t *curvePointY, - const uint8_t *prime, - const uint8_t *a, - const uint8_t *b, - const uint8_t *order, - uint32_t length); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_PKAClearPkaRam - #undef PKAClearPkaRam - #define PKAClearPkaRam ROM_PKAClearPkaRam - #endif - #ifdef ROM_PKAGetOpsStatus - #undef PKAGetOpsStatus - #define PKAGetOpsStatus ROM_PKAGetOpsStatus - #endif - #ifdef ROM_PKAArrayAllZeros - #undef PKAArrayAllZeros - #define PKAArrayAllZeros ROM_PKAArrayAllZeros - #endif - #ifdef ROM_PKAZeroOutArray - #undef PKAZeroOutArray - #define PKAZeroOutArray ROM_PKAZeroOutArray - #endif - #ifdef ROM_PKABigNumModStart - #undef PKABigNumModStart - #define PKABigNumModStart ROM_PKABigNumModStart - #endif - #ifdef ROM_PKABigNumModGetResult - #undef PKABigNumModGetResult - #define PKABigNumModGetResult ROM_PKABigNumModGetResult - #endif - #ifdef ROM_PKABigNumDivideStart - #undef PKABigNumDivideStart - #define PKABigNumDivideStart ROM_PKABigNumDivideStart - #endif - #ifdef ROM_PKABigNumDivideGetQuotient - #undef PKABigNumDivideGetQuotient - #define PKABigNumDivideGetQuotient ROM_PKABigNumDivideGetQuotient - #endif - #ifdef ROM_PKABigNumDivideGetRemainder - #undef PKABigNumDivideGetRemainder - #define PKABigNumDivideGetRemainder ROM_PKABigNumDivideGetRemainder - #endif - #ifdef ROM_PKABigNumCmpStart - #undef PKABigNumCmpStart - #define PKABigNumCmpStart ROM_PKABigNumCmpStart - #endif - #ifdef ROM_PKABigNumCmpGetResult - #undef PKABigNumCmpGetResult - #define PKABigNumCmpGetResult ROM_PKABigNumCmpGetResult - #endif - #ifdef ROM_PKABigNumInvModStart - #undef PKABigNumInvModStart - #define PKABigNumInvModStart ROM_PKABigNumInvModStart - #endif - #ifdef ROM_PKABigNumInvModGetResult - #undef PKABigNumInvModGetResult - #define PKABigNumInvModGetResult ROM_PKABigNumInvModGetResult - #endif - #ifdef ROM_PKABigNumMultiplyStart - #undef PKABigNumMultiplyStart - #define PKABigNumMultiplyStart ROM_PKABigNumMultiplyStart - #endif - #ifdef ROM_PKABigNumMultGetResult - #undef PKABigNumMultGetResult - #define PKABigNumMultGetResult ROM_PKABigNumMultGetResult - #endif - #ifdef ROM_PKABigNumAddStart - #undef PKABigNumAddStart - #define PKABigNumAddStart ROM_PKABigNumAddStart - #endif - #ifdef ROM_PKABigNumAddGetResult - #undef PKABigNumAddGetResult - #define PKABigNumAddGetResult ROM_PKABigNumAddGetResult - #endif - #ifdef ROM_PKABigNumSubStart - #undef PKABigNumSubStart - #define PKABigNumSubStart ROM_PKABigNumSubStart - #endif - #ifdef ROM_PKABigNumSubGetResult - #undef PKABigNumSubGetResult - #define PKABigNumSubGetResult ROM_PKABigNumSubGetResult - #endif - #ifdef ROM_PKAEccMultiplyStart - #undef PKAEccMultiplyStart - #define PKAEccMultiplyStart ROM_PKAEccMultiplyStart - #endif - #ifdef ROM_PKAEccMontgomeryMultiplyStart - #undef PKAEccMontgomeryMultiplyStart - #define PKAEccMontgomeryMultiplyStart ROM_PKAEccMontgomeryMultiplyStart - #endif - #ifdef ROM_PKAEccMultiplyGetResult - #undef PKAEccMultiplyGetResult - #define PKAEccMultiplyGetResult ROM_PKAEccMultiplyGetResult - #endif - #ifdef ROM_PKAEccAddStart - #undef PKAEccAddStart - #define PKAEccAddStart ROM_PKAEccAddStart - #endif - #ifdef ROM_PKAEccAddGetResult - #undef PKAEccAddGetResult - #define PKAEccAddGetResult ROM_PKAEccAddGetResult - #endif - #ifdef ROM_PKAEccVerifyPublicKeyWeierstrassStart - #undef PKAEccVerifyPublicKeyWeierstrassStart - #define PKAEccVerifyPublicKeyWeierstrassStart ROM_PKAEccVerifyPublicKeyWeierstrassStart - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __PKA_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h deleted file mode 100644 index c780a53456a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pka_doc.h +++ /dev/null @@ -1,80 +0,0 @@ -/****************************************************************************** -* Filename: pka_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup pka_api -//! @{ -//! \section sec_pka Introduction -//! -//! The PKA (Public Key Accelerator) API provides access to the Large Number -//! Engine (LNME). The LNME allows for efficient math operations on numbers -//! larger than those that fit within the ALU of the system CPU. It is significantly faster -//! to perform these operations using the LNME than implementing the same -//! functionality in software using regular word-wise math operations. While the -//! LNME runs in the background, the system CPU may perform other operations -//! or be turned off. -//! -//! The LNME supports both primitive math operations and serialized primitive -//! operations (sequencer operations). -//! - Addition -//! - Multiplication -//! - Comparison -//! - Modulo -//! - Inverse Modulo -//! - ECC Point Addition (including point doubling) -//! - ECC Scalar Multiplication -//! -//! These primitives and sequencer operations can be used to implement various -//! public key encryption schemes. -//! It is possible to implement the following schemes using the operations mentioned above: -//! - RSA encryption and decryption -//! - RSA sign and verify -//! - DHE (Diffie-Hellman Key Exchange) -//! - ECDH (Elliptic Curve Diffie-Hellman Key Exchange) -//! - ECDSA (Elliptic Curve Digital Signature Algorithm) -//! - ECIES (Elliptic Curve Integrated Encryption Scheme) -//! -//! The DriverLib PKA functions copy the relevant parameters into the dedicated -//! PKA RAM. The LNME requires these parameters be present and correctly -//! formatted in the PKA RAM and not system RAM. They are copied word-wise as -//! the PKA RAM does not support byte-wise access. The CPU handles the alignment differences -//! during the memory copy operation. Forcing buffer alignment in system RAM results -//! in a significant speedup of the copy operation compared to unaligned buffers. -//! -//! When the operation completes, the result is copied back into -//! a buffer in system RAM specified by the application. The PKA RAM is then cleared -//! to prevent sensitive keying material from remaining in PKA RAM. -//! -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.c deleted file mode 100644 index e81df8f93a2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.c +++ /dev/null @@ -1,647 +0,0 @@ -/****************************************************************************** -* Filename: prcm.c -* Revised: 2018-10-18 17:33:32 +0200 (Thu, 18 Oct 2018) -* Revision: 52954 -* -* Description: Driver for the PRCM. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "prcm.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef PRCMInfClockConfigureSet - #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet - #undef PRCMInfClockConfigureGet - #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet - #undef PRCMAudioClockConfigSet - #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet - #undef PRCMAudioClockConfigSetOverride - #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride - #undef PRCMAudioClockInternalSource - #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource - #undef PRCMAudioClockExternalSource - #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource - #undef PRCMPowerDomainOn - #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn - #undef PRCMPowerDomainOff - #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff - #undef PRCMPeripheralRunEnable - #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable - #undef PRCMPeripheralRunDisable - #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable - #undef PRCMPeripheralSleepEnable - #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable - #undef PRCMPeripheralSleepDisable - #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable - #undef PRCMPeripheralDeepSleepEnable - #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable - #undef PRCMPeripheralDeepSleepDisable - #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable - #undef PRCMPowerDomainStatus - #define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus - #undef PRCMDeepSleep - #define PRCMDeepSleep NOROM_PRCMDeepSleep -#endif - - -//***************************************************************************** -// -// Arrays that maps the "peripheral set" number (which is stored in -// bits[11:8] of the PRCM_PERIPH_* defines) to the PRCM register that -// contains the relevant bit for that peripheral. -// -//***************************************************************************** - -// Run mode registers -static const uint32_t g_pui32RCGCRegs[] = -{ - PRCM_O_GPTCLKGR , // Index 0 - PRCM_O_SSICLKGR , // Index 1 - PRCM_O_UARTCLKGR , // Index 2 - PRCM_O_I2CCLKGR , // Index 3 - PRCM_O_SECDMACLKGR , // Index 4 - PRCM_O_GPIOCLKGR , // Index 5 - PRCM_O_I2SCLKGR // Index 6 -}; - -// Sleep mode registers -static const uint32_t g_pui32SCGCRegs[] = -{ - PRCM_O_GPTCLKGS , // Index 0 - PRCM_O_SSICLKGS , // Index 1 - PRCM_O_UARTCLKGS , // Index 2 - PRCM_O_I2CCLKGS , // Index 3 - PRCM_O_SECDMACLKGS , // Index 4 - PRCM_O_GPIOCLKGS , // Index 5 - PRCM_O_I2SCLKGS // Index 6 -}; - -// Deep sleep mode registers -static const uint32_t g_pui32DCGCRegs[] = -{ - PRCM_O_GPTCLKGDS , // Index 0 - PRCM_O_SSICLKGDS , // Index 1 - PRCM_O_UARTCLKGDS , // Index 2 - PRCM_O_I2CCLKGDS , // Index 3 - PRCM_O_SECDMACLKGDS , // Index 4 - PRCM_O_GPIOCLKGDS , // Index 5 - PRCM_O_I2SCLKGDS // Index 6 -}; - -//***************************************************************************** -// -// This macro extracts the array index out of the peripheral number -// -//***************************************************************************** -#define PRCM_PERIPH_INDEX(a) (((a) >> 8) & 0xf) - -//***************************************************************************** -// -// This macro extracts the peripheral instance number and generates bit mask -// -//***************************************************************************** -#define PRCM_PERIPH_MASKBIT(a) (0x00000001 << ((a) & 0x1f)) - - -//***************************************************************************** -// -// Configure the infrastructure clock. -// -//***************************************************************************** -void -PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, uint32_t ui32PowerMode) -{ - uint32_t ui32Divisor; - - // Check the arguments. - ASSERT((ui32ClkDiv == PRCM_CLOCK_DIV_1) || - (ui32ClkDiv == PRCM_CLOCK_DIV_2) || - (ui32ClkDiv == PRCM_CLOCK_DIV_8) || - (ui32ClkDiv == PRCM_CLOCK_DIV_32)); - ASSERT((ui32PowerMode == PRCM_RUN_MODE) || - (ui32PowerMode == PRCM_SLEEP_MODE) || - (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); - - ui32Divisor = 0; - - // Find the correct division factor. - if(ui32ClkDiv == PRCM_CLOCK_DIV_1) - { - ui32Divisor = 0x0; - } - else if(ui32ClkDiv == PRCM_CLOCK_DIV_2) - { - ui32Divisor = 0x1; - } - else if(ui32ClkDiv == PRCM_CLOCK_DIV_8) - { - ui32Divisor = 0x2; - } - else if(ui32ClkDiv == PRCM_CLOCK_DIV_32) - { - ui32Divisor = 0x3; - } - - // Determine the correct power mode set the division factor accordingly. - if(ui32PowerMode == PRCM_RUN_MODE) - { - HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR) = ui32Divisor; - } - else if(ui32PowerMode == PRCM_SLEEP_MODE) - { - HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS) = ui32Divisor; - } - else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) - { - HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS) = ui32Divisor; - } -} - -//***************************************************************************** -// -// Use this function to get the infrastructure clock configuration -// -//***************************************************************************** -uint32_t -PRCMInfClockConfigureGet(uint32_t ui32PowerMode) -{ - uint32_t ui32ClkDiv; - uint32_t ui32Divisor; - - // Check the arguments. - ASSERT((ui32PowerMode == PRCM_RUN_MODE) || - (ui32PowerMode == PRCM_SLEEP_MODE) || - (ui32PowerMode == PRCM_DEEP_SLEEP_MODE)); - - ui32ClkDiv = 0; - ui32Divisor = 0; - - // Determine the correct power mode. - if(ui32PowerMode == PRCM_RUN_MODE) - { - ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVR); - } - else if(ui32PowerMode == PRCM_SLEEP_MODE) - { - ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVS); - } - else if(ui32PowerMode == PRCM_DEEP_SLEEP_MODE) - { - ui32ClkDiv = HWREG(PRCM_BASE + PRCM_O_INFRCLKDIVDS); - } - - // Find the correct division factor. - if(ui32ClkDiv == 0x0) - { - ui32Divisor = PRCM_CLOCK_DIV_1; - } - else if(ui32ClkDiv == 0x1) - { - ui32Divisor = PRCM_CLOCK_DIV_2; - } - else if(ui32ClkDiv == 0x2) - { - ui32Divisor = PRCM_CLOCK_DIV_8; - } - else if(ui32ClkDiv == 0x3) - { - ui32Divisor = PRCM_CLOCK_DIV_32; - } - - // Return the clock division factor. - return ui32Divisor; -} - - -//***************************************************************************** -// -// Configure the audio clock generation -// -//***************************************************************************** -void -PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, uint32_t ui32SampleRate) -{ - uint32_t ui32Reg; - uint32_t ui32MstDiv; - uint32_t ui32BitDiv; - uint32_t ui32WordDiv; - - // Check the arguments. - ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); - ASSERT((ui32SampleRate == I2S_SAMPLE_RATE_16K) || - (ui32SampleRate == I2S_SAMPLE_RATE_24K) || - (ui32SampleRate == I2S_SAMPLE_RATE_32K) || - (ui32SampleRate == I2S_SAMPLE_RATE_48K)); - - ui32MstDiv = 0; - ui32BitDiv = 0; - ui32WordDiv = 0; - - // Make sure the audio clock generation is disabled before reconfiguring. - PRCMAudioClockDisable(); - - // Define the clock division factors for the audio interface. - switch(ui32SampleRate) - { - case I2S_SAMPLE_RATE_16K : - ui32MstDiv = 6; - ui32BitDiv = 60; - ui32WordDiv = 25; - break; - case I2S_SAMPLE_RATE_24K : - ui32MstDiv = 4; - ui32BitDiv = 40; - ui32WordDiv = 25; - break; - case I2S_SAMPLE_RATE_32K : - ui32MstDiv = 3; - ui32BitDiv = 30; - ui32WordDiv = 25; - break; - case I2S_SAMPLE_RATE_48K : - ui32MstDiv = 2; - ui32BitDiv = 20; - ui32WordDiv = 25; - break; - } - - // Make sure to compensate the Frame clock division factor if using single - // phase format. - if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) - { - ui32WordDiv -= 1; - } - - // Write the clock division factors. - HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; - HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; - HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; - - // Configure the Word clock format and polarity. - ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | - PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); - HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; -} - -//***************************************************************************** -// -// Configure the audio clock generation with manual setting of clock divider. -// -//***************************************************************************** -void -PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, - uint32_t ui32BitDiv, uint32_t ui32WordDiv) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT(!(ui32ClkConfig & (PRCM_I2SCLKCTL_WCLK_PHASE_M | PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M))); - - // Make sure the audio clock generation is disabled before reconfiguring. - PRCMAudioClockDisable(); - - // Make sure to compensate the Frame clock division factor if using single - // phase format. - if((ui32ClkConfig & PRCM_I2SCLKCTL_WCLK_PHASE_M) == PRCM_WCLK_SINGLE_PHASE) - { - ui32WordDiv -= 1; - } - - // Write the clock division factors. - HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; - HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; - HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; - - // Configure the Word clock format and polarity. - ui32Reg = HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) & ~(PRCM_I2SCLKCTL_WCLK_PHASE_M | - PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M); - HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = ui32Reg | ui32ClkConfig; -} - -//***************************************************************************** -// -// Configure the audio clocks for I2S module -// -//***************************************************************************** -void -PRCMAudioClockConfigOverride(uint8_t ui8SamplingEdge, - uint8_t ui8WCLKPhase, - uint32_t ui32MstDiv, - uint32_t ui32BitDiv, - uint32_t ui32WordDiv) -{ - // Check the arguments. - ASSERT( ui8BitsPerSample == PRCM_WCLK_SINGLE_PHASE - || ui8BitsPerSample == PRCM_WCLK_DUAL_PHASE - || ui8BitsPerSample == PRCM_WCLK_USER_DEF); - - // Make sure the audio clock generation is disabled before reconfiguring. - PRCMAudioClockDisable(); - - // Make sure to compensate the Frame clock division factor if using single - // phase format. - if((ui8WCLKPhase) == PRCM_WCLK_SINGLE_PHASE) - { - ui32WordDiv -= 1; - } - - // Write the clock division factors. - HWREG(PRCM_BASE + PRCM_O_I2SMCLKDIV) = ui32MstDiv; - HWREG(PRCM_BASE + PRCM_O_I2SBCLKDIV) = ui32BitDiv; - HWREG(PRCM_BASE + PRCM_O_I2SWCLKDIV) = ui32WordDiv; - - // Configure the Word clock format and polarity and enable it. - HWREG(PRCM_BASE + PRCM_O_I2SCLKCTL) = (ui8SamplingEdge << PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S) | - (ui8WCLKPhase << PRCM_I2SCLKCTL_WCLK_PHASE_S ) | - (1 << PRCM_I2SCLKCTL_EN_S ); -} - -//***************************************************************************** -// -// Configure the clocks as "internally generated". -// -//***************************************************************************** -void PRCMAudioClockInternalSource(void) -{ - HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 1; -} - -//***************************************************************************** -// -// Configure the clocks as "externally generated". -// -//***************************************************************************** -void PRCMAudioClockExternalSource(void) -{ - HWREGBITW(PRCM_BASE + PRCM_O_I2SBCLKSEL, PRCM_I2SBCLKSEL_SRC_BITN) = 0; -} - -//***************************************************************************** -// -// Turn power on in power domains in the MCU domain -// -//***************************************************************************** -void -PRCMPowerDomainOn(uint32_t ui32Domains) -{ - // Check the arguments. - ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || - (ui32Domains & PRCM_DOMAIN_SERIAL) || - (ui32Domains & PRCM_DOMAIN_PERIPH) || - (ui32Domains & PRCM_DOMAIN_CPU) || - (ui32Domains & PRCM_DOMAIN_VIMS)); - - // Assert the request to power on the right domains. - if(ui32Domains & PRCM_DOMAIN_RFCORE) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 1; - } - if(ui32Domains & PRCM_DOMAIN_SERIAL) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 1; - } - if(ui32Domains & PRCM_DOMAIN_PERIPH) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 1; - } - if(ui32Domains & PRCM_DOMAIN_VIMS) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 1; - } - if(ui32Domains & PRCM_DOMAIN_CPU) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 1; - } -} - -//***************************************************************************** -// -// Turn off a specific power domain -// -//***************************************************************************** -void -PRCMPowerDomainOff(uint32_t ui32Domains) -{ - // Check the arguments. - ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || - (ui32Domains & PRCM_DOMAIN_SERIAL) || - (ui32Domains & PRCM_DOMAIN_PERIPH) || - (ui32Domains & PRCM_DOMAIN_CPU) || - (ui32Domains & PRCM_DOMAIN_VIMS)); - - // Assert the request to power off the right domains. - if(ui32Domains & PRCM_DOMAIN_RFCORE) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL0RFC ) = 0; - } - if(ui32Domains & PRCM_DOMAIN_SERIAL) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL0SERIAL) = 0; - } - if(ui32Domains & PRCM_DOMAIN_PERIPH) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL0PERIPH) = 0; - } - if(ui32Domains & PRCM_DOMAIN_VIMS) - { - // Write bits ui32Domains[17:16] to the VIMS_MODE alias register. - // PRCM_DOMAIN_VIMS sets VIMS_MODE=0b00, PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP sets VIMS_MODE=0b10. - ASSERT(!(ui32Domains & 0x00010000)); - HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS ) = ( ui32Domains >> 16 ) & 3; - } - if(ui32Domains & PRCM_DOMAIN_CPU) - { - HWREG(PRCM_BASE + PRCM_O_PDCTL1CPU ) = 0; - } -} - -//***************************************************************************** -// -// Enables a peripheral in Run mode -// -//***************************************************************************** -void -PRCMPeripheralRunEnable(uint32_t ui32Peripheral) -{ - // Check the arguments. - ASSERT(PRCMPeripheralValid(ui32Peripheral)); - - // Enable module in Run Mode. - HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= - PRCM_PERIPH_MASKBIT(ui32Peripheral); -} - -//***************************************************************************** -// -// Disables a peripheral in Run mode -// -//***************************************************************************** -void -PRCMPeripheralRunDisable(uint32_t ui32Peripheral) -{ - // Check the arguments. - ASSERT(PRCMPeripheralValid(ui32Peripheral)); - - // Disable module in Run Mode. - HWREG(PRCM_BASE + g_pui32RCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= - ~PRCM_PERIPH_MASKBIT(ui32Peripheral); -} - -//***************************************************************************** -// -// Enables a peripheral in sleep mode -// -//***************************************************************************** -void -PRCMPeripheralSleepEnable(uint32_t ui32Peripheral) -{ - // Check the arguments. - ASSERT(PRCMPeripheralValid(ui32Peripheral)); - - // Enable this peripheral in sleep mode. - HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= - PRCM_PERIPH_MASKBIT(ui32Peripheral); -} - -//***************************************************************************** -// -// Disables a peripheral in sleep mode -// -//***************************************************************************** -void -PRCMPeripheralSleepDisable(uint32_t ui32Peripheral) -{ - // Check the arguments. - ASSERT(PRCMPeripheralValid(ui32Peripheral)); - - // Disable this peripheral in sleep mode - HWREG(PRCM_BASE + g_pui32SCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= - ~PRCM_PERIPH_MASKBIT(ui32Peripheral); -} - -//***************************************************************************** -// -// Enables a peripheral in deep-sleep mode -// -//***************************************************************************** -void -PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral) -{ - // Check the arguments. - ASSERT(PRCMPeripheralValid(ui32Peripheral)); - - // Enable this peripheral in deep-sleep mode. - HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) |= - PRCM_PERIPH_MASKBIT(ui32Peripheral); -} - -//***************************************************************************** -// -// Disables a peripheral in deep-sleep mode -// -//***************************************************************************** -void -PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral) -{ - // Check the arguments. - ASSERT(PRCMPeripheralValid(ui32Peripheral)); - - // Disable this peripheral in Deep Sleep mode. - HWREG(PRCM_BASE + g_pui32DCGCRegs[PRCM_PERIPH_INDEX(ui32Peripheral)]) &= - ~PRCM_PERIPH_MASKBIT(ui32Peripheral); -} - -//***************************************************************************** -// -// Get the status for a specific power domain -// -//***************************************************************************** -uint32_t -PRCMPowerDomainStatus(uint32_t ui32Domains) -{ - bool bStatus; - uint32_t ui32StatusRegister0; - uint32_t ui32StatusRegister1; - - // Check the arguments. - ASSERT((ui32Domains & (PRCM_DOMAIN_RFCORE | - PRCM_DOMAIN_SERIAL | - PRCM_DOMAIN_PERIPH))); - - bStatus = true; - ui32StatusRegister0 = HWREG(PRCM_BASE + PRCM_O_PDSTAT0); - ui32StatusRegister1 = HWREG(PRCM_BASE + PRCM_O_PDSTAT1); - - // Return the correct power status. - if(ui32Domains & PRCM_DOMAIN_RFCORE) - { - bStatus = bStatus && - ((ui32StatusRegister0 & PRCM_PDSTAT0_RFC_ON) || - (ui32StatusRegister1 & PRCM_PDSTAT1_RFC_ON)); - } - if(ui32Domains & PRCM_DOMAIN_SERIAL) - { - bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_SERIAL_ON); - } - if(ui32Domains & PRCM_DOMAIN_PERIPH) - { - bStatus = bStatus && (ui32StatusRegister0 & PRCM_PDSTAT0_PERIPH_ON); - } - - // Return the status. - return (bStatus ? PRCM_DOMAIN_POWER_ON : PRCM_DOMAIN_POWER_OFF); -} - -//***************************************************************************** -// -// Put the processor into deep-sleep mode -// -//***************************************************************************** -void -PRCMDeepSleep(void) -{ - // Enable deep-sleep. - HWREG(NVIC_SYS_CTRL) |= NVIC_SYS_CTRL_SLEEPDEEP; - - // Wait for an interrupt. - CPUwfi(); - - // Disable deep-sleep so that a future sleep will work correctly. - HWREG(NVIC_SYS_CTRL) &= ~(NVIC_SYS_CTRL_SLEEPDEEP); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h deleted file mode 100644 index 783ca421435..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/prcm.h +++ /dev/null @@ -1,1234 +0,0 @@ -/****************************************************************************** -* Filename: prcm.h -* Revised: 2018-10-23 10:19:14 +0200 (Tue, 23 Oct 2018) -* Revision: 52979 -* -* Description: Defines and prototypes for the PRCM -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup prcm_api -//! @{ -// -//***************************************************************************** - -#ifndef __PRCM_H__ -#define __PRCM_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_nvic.h" -#include "../inc/hw_aon_rtc.h" -#include "interrupt.h" -#include "debug.h" -#include "cpu.h" - - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define PRCMInfClockConfigureSet NOROM_PRCMInfClockConfigureSet - #define PRCMInfClockConfigureGet NOROM_PRCMInfClockConfigureGet - #define PRCMAudioClockConfigSet NOROM_PRCMAudioClockConfigSet - #define PRCMAudioClockConfigSetOverride NOROM_PRCMAudioClockConfigSetOverride - #define PRCMAudioClockInternalSource NOROM_PRCMAudioClockInternalSource - #define PRCMAudioClockExternalSource NOROM_PRCMAudioClockExternalSource - #define PRCMPowerDomainOn NOROM_PRCMPowerDomainOn - #define PRCMPowerDomainOff NOROM_PRCMPowerDomainOff - #define PRCMPeripheralRunEnable NOROM_PRCMPeripheralRunEnable - #define PRCMPeripheralRunDisable NOROM_PRCMPeripheralRunDisable - #define PRCMPeripheralSleepEnable NOROM_PRCMPeripheralSleepEnable - #define PRCMPeripheralSleepDisable NOROM_PRCMPeripheralSleepDisable - #define PRCMPeripheralDeepSleepEnable NOROM_PRCMPeripheralDeepSleepEnable - #define PRCMPeripheralDeepSleepDisable NOROM_PRCMPeripheralDeepSleepDisable - #define PRCMPowerDomainStatus NOROM_PRCMPowerDomainStatus - #define PRCMDeepSleep NOROM_PRCMDeepSleep -#endif - -//***************************************************************************** -// -// Defines for the different System CPU power modes. -// -//***************************************************************************** -#define PRCM_RUN_MODE 0x00000001 -#define PRCM_SLEEP_MODE 0x00000002 -#define PRCM_DEEP_SLEEP_MODE 0x00000004 - -//***************************************************************************** -// -// Defines used for setting the clock division factors -// -//***************************************************************************** -#define PRCM_CLOCK_DIV_1 PRCM_GPTCLKDIV_RATIO_DIV1 -#define PRCM_CLOCK_DIV_2 PRCM_GPTCLKDIV_RATIO_DIV2 -#define PRCM_CLOCK_DIV_4 PRCM_GPTCLKDIV_RATIO_DIV4 -#define PRCM_CLOCK_DIV_8 PRCM_GPTCLKDIV_RATIO_DIV8 -#define PRCM_CLOCK_DIV_16 PRCM_GPTCLKDIV_RATIO_DIV16 -#define PRCM_CLOCK_DIV_32 PRCM_GPTCLKDIV_RATIO_DIV32 -#define PRCM_CLOCK_DIV_64 PRCM_GPTCLKDIV_RATIO_DIV64 -#define PRCM_CLOCK_DIV_128 PRCM_GPTCLKDIV_RATIO_DIV128 -#define PRCM_CLOCK_DIV_256 PRCM_GPTCLKDIV_RATIO_DIV256 - -//***************************************************************************** -// -// Defines used for enabling and disabling domains and memories in the MCU -// domain -// -//***************************************************************************** -#define PRCM_DOMAIN_RFCORE 0x00000001 // RF Core domain ID for - // clock/power control. -#define PRCM_DOMAIN_SERIAL 0x00000002 // Serial domain ID for - // clock/power control. -#define PRCM_DOMAIN_PERIPH 0x00000004 // Peripheral domain ID for - // clock/power control. -#define PRCM_DOMAIN_SYSBUS 0x00000008 // Bus domain ID for clock/power - // control. -#define PRCM_DOMAIN_VIMS 0x00000010 // VIMS domain ID for clock/power - // control. -#define PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP \ - 0x00020010 // For function PRCMPowerDomainOff() it is an option to - // select that VIMS power domain shall not power up - // during the next wake up from uLDO (VIMS_MODE=0b10). -#define PRCM_DOMAIN_CPU 0x00000020 // CPU domain ID for clock/power - // control. -#define PRCM_DOMAIN_TIMER 0x00000040 // GPT domain ID for clock - // control. -#define PRCM_DOMAIN_CLKCTRL 0x00000080 // Clock Control domain ID for - // clock/power control. -#define PRCM_DOMAIN_MCU 0x00000100 // Reset control for entire MCU - // domain. -#define PRCM_DOMAIN_POWER_OFF 0x00000002 // The domain is powered off -#define PRCM_DOMAIN_POWER_ON 0x00000001 // The domain is powered on -#define PRCM_DOMAIN_POWER_DOWN_READY \ - 0x00000000 // The domain is ready to be - // powered down. - -//***************************************************************************** -// -// Defines for setting up the audio interface in the I2S module. -// -//***************************************************************************** -#define PRCM_WCLK_NEG_EDGE 0x00000008 -#define PRCM_WCLK_POS_EDGE 0x00000000 -#define PRCM_WCLK_SINGLE_PHASE 0x00000000 -#define PRCM_WCLK_DUAL_PHASE 0x00000002 -#define PRCM_WCLK_USER_DEF 0x00000004 -#define PRCM_I2S_WCLK_NEG_EDGE 0 -#define PRCM_I2S_WCLK_POS_EDGE 1 -#define PRCM_I2S_WCLK_SINGLE_PHASE 0 -#define PRCM_I2S_WCLK_DUAL_PHASE 1 -#define PRCM_I2S_WCLK_USER_DEF 2 - -#define I2S_SAMPLE_RATE_16K 0x00000001 -#define I2S_SAMPLE_RATE_24K 0x00000002 -#define I2S_SAMPLE_RATE_32K 0x00000004 -#define I2S_SAMPLE_RATE_48K 0x00000008 - -//***************************************************************************** -// -// Defines used for enabling and disabling peripheral modules in the MCU domain -// bits[11:8] Defines the index into the register offset constant tables: -// g_pui32RCGCRegs, g_pui32SCGCRegs and g_pui32DCGCRegs -// bits[4:0] Defines the bit position within the register pointet on in [11:8] -// -//***************************************************************************** -#define PRCM_PERIPH_TIMER0 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S )) // Peripheral ID for GPT module 0 -#define PRCM_PERIPH_TIMER1 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for GPT module 1 -#define PRCM_PERIPH_TIMER2 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 2 )) // Peripheral ID for GPT module 2 -#define PRCM_PERIPH_TIMER3 ( 0x00000000 | ( PRCM_GPTCLKGR_CLK_EN_S + 3 )) // Peripheral ID for GPT module 3 -#define PRCM_PERIPH_SSI0 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S )) // Peripheral ID for SSI module 0 -#define PRCM_PERIPH_SSI1 ( 0x00000100 | ( PRCM_SSICLKGR_CLK_EN_S + 1 )) // Peripheral ID for SSI module 1 -#define PRCM_PERIPH_UART0 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S )) // Peripheral ID for UART module 0 -#define PRCM_PERIPH_UART1 ( 0x00000200 | ( PRCM_UARTCLKGR_CLK_EN_S + 1 )) // Peripheral ID for UART module 1 -#define PRCM_PERIPH_I2C0 ( 0x00000300 | ( PRCM_I2CCLKGR_CLK_EN_S )) // Peripheral ID for I2C module 0 -#define PRCM_PERIPH_CRYPTO ( 0x00000400 | ( PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S )) // Peripheral ID for CRYPTO module -#define PRCM_PERIPH_TRNG ( 0x00000400 | ( PRCM_SECDMACLKGR_TRNG_CLK_EN_S )) // Peripheral ID for TRNG module -#define PRCM_PERIPH_PKA ( 0x00000400 | ( PRCM_SECDMACLKGR_PKA_CLK_EN_S )) // Peripheral ID for PKA module -#define PRCM_PERIPH_UDMA ( 0x00000400 | ( PRCM_SECDMACLKGR_DMA_CLK_EN_S )) // Peripheral ID for UDMA module -#define PRCM_PERIPH_GPIO ( 0x00000500 | ( PRCM_GPIOCLKGR_CLK_EN_S )) // Peripheral ID for GPIO module -#define PRCM_PERIPH_I2S ( 0x00000600 | ( PRCM_I2SCLKGR_CLK_EN_S )) // Peripheral ID for I2S module - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \brief Checks a peripheral identifier. -//! -//! This function determines if a peripheral identifier is valid. -//! -//! \param ui32Peripheral is the peripheral identifier. -//! -//! \return Returns status of peripheral identifier: -//! - \b true : Peripheral identifier is valid. -//! - \b false : Peripheral identifier is invalid. -// -//***************************************************************************** -static bool -PRCMPeripheralValid(uint32_t ui32Peripheral) -{ - return((ui32Peripheral == PRCM_PERIPH_TIMER0) || - (ui32Peripheral == PRCM_PERIPH_TIMER1) || - (ui32Peripheral == PRCM_PERIPH_TIMER2) || - (ui32Peripheral == PRCM_PERIPH_TIMER3) || - (ui32Peripheral == PRCM_PERIPH_SSI0) || - (ui32Peripheral == PRCM_PERIPH_SSI1) || - (ui32Peripheral == PRCM_PERIPH_UART0) || - (ui32Peripheral == PRCM_PERIPH_UART1) || - (ui32Peripheral == PRCM_PERIPH_I2C0) || - (ui32Peripheral == PRCM_PERIPH_CRYPTO) || - (ui32Peripheral == PRCM_PERIPH_TRNG) || - (ui32Peripheral == PRCM_PERIPH_PKA) || - (ui32Peripheral == PRCM_PERIPH_UDMA) || - (ui32Peripheral == PRCM_PERIPH_GPIO) || - (ui32Peripheral == PRCM_PERIPH_I2S)); -} -#endif - -//***************************************************************************** -// -//! \brief Configure the infrastructure clock. -//! -//! Each System CPU power mode has its own infrastructure clock division factor. This -//! function can be used for setting up the division factor for the -//! infrastructure clock in the available power modes for the System CPU. The -//! infrastructure clock is used for all internal logic in the PRCM, and is -//! always running as long as power is on in the MCU voltage domain. -//! This can be enabled and disabled from the AON Wake Up Controller. -//! -//! \note If source clock is 48 MHz, minimum clock divider is \ref PRCM_CLOCK_DIV_2. -//! -//! \param ui32ClkDiv determines the division ratio for the infrastructure -//! clock when the device is in the specified mode. -//! Allowed division factors for all three System CPU power modes are: -//! - \ref PRCM_CLOCK_DIV_1 -//! - \ref PRCM_CLOCK_DIV_2 -//! - \ref PRCM_CLOCK_DIV_8 -//! - \ref PRCM_CLOCK_DIV_32 -//! \param ui32PowerMode determines the System CPU operation mode for which to -//! modify the clock division factor. -//! The three allowed power modes are: -//! - \ref PRCM_RUN_MODE -//! - \ref PRCM_SLEEP_MODE -//! - \ref PRCM_DEEP_SLEEP_MODE -//! -//! \return None -// -//***************************************************************************** -extern void PRCMInfClockConfigureSet(uint32_t ui32ClkDiv, - uint32_t ui32PowerMode); - -//***************************************************************************** -// -//! \brief Use this function to get the infrastructure clock configuration. -//! -//! \param ui32PowerMode determines which System CPU power mode to return the -//! infrastructure clock division ratio for. -//! The three allowed power modes are: -//! - \ref PRCM_RUN_MODE -//! - \ref PRCM_SLEEP_MODE -//! - \ref PRCM_DEEP_SLEEP_MODE -//! -//! \return Returns the infrastructure clock division factor for the specified -//! power mode. -//! - \ref PRCM_CLOCK_DIV_1 -//! - \ref PRCM_CLOCK_DIV_2 -//! - \ref PRCM_CLOCK_DIV_8 -//! - \ref PRCM_CLOCK_DIV_32 -//! -//! \sa \ref PRCMInfClockConfigureSet(). -// -//***************************************************************************** -extern uint32_t PRCMInfClockConfigureGet(uint32_t ui32PowerMode); - -//***************************************************************************** -// -//! \brief Assert or de-assert a request for the uLDO. -//! -//! Use this function to request to switch to the micro Low Voltage Dropout -//! regulator (uLDO). The uLDO has a much lower capacity for supplying power -//! to the system. It is therefore imperative and solely the programmers -//! responsibility to ensure that a sufficient amount of peripheral modules -//! have been turned of before requesting a switch to the uLDO. -//! -//! \note Asserting this bit has no effect until: -//! 1. FLASH has accepted to be powered down -//! 2. Deepsleep must be asserted -//! -//! \param ui32Enable -//! - 0 : Disable uLDO request -//! - 1 : Enable uLDO request -//! -//! \return None -//! -//! \sa \ref PRCMDeepSleep() -// -//***************************************************************************** -__STATIC_INLINE void -PRCMMcuUldoConfigure(uint32_t ui32Enable) -{ - // Enable or disable the uLDO request signal. - HWREGBITW(PRCM_BASE + PRCM_O_VDCTL, PRCM_VDCTL_ULDO_BITN) = ui32Enable; -} - -//***************************************************************************** -// -//! \brief Setup the clock division factor for the GP-Timer domain. -//! -//! Use this function to set up the clock division factor on the GP-Timer. -//! -//! The division rate will be constant and ungated for Run / Sleep / DeepSleep mode when -//! it is slower than PRCM_GPTCLKDIV_RATIO setting. -//! When set faster than PRCM_GPTCLKDIV_RATIO setting PRCM_GPTCLKDIV_RATIO will be used. -//! Note that the register will contain the written content even though the setting is -//! faster than PRCM_GPTCLKDIV_RATIO setting. -//! -//! \note For change to take effect, \ref PRCMLoadSet() needs to be called -//! -//! \param clkDiv is the division factor to set. -//! The argument must be only one of the following values: -//! - \ref PRCM_CLOCK_DIV_1 -//! - \ref PRCM_CLOCK_DIV_2 -//! - \ref PRCM_CLOCK_DIV_4 -//! - \ref PRCM_CLOCK_DIV_8 -//! - \ref PRCM_CLOCK_DIV_16 -//! - \ref PRCM_CLOCK_DIV_32 -//! - \ref PRCM_CLOCK_DIV_64 -//! - \ref PRCM_CLOCK_DIV_128 -//! - \ref PRCM_CLOCK_DIV_256 -//! -//! \return None -//! -//! \sa \ref PRCMGPTimerClockDivisionGet() -// -//***************************************************************************** -__STATIC_INLINE void -PRCMGPTimerClockDivisionSet( uint32_t clkDiv ) -{ - ASSERT( clkDiv <= PRCM_GPTCLKDIV_RATIO_DIV256 ); - - HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV ) = clkDiv; -} - -//***************************************************************************** -// -//! \brief Get the clock division factor for the GP-Timer domain. -//! -//! Use this function to get the clock division factor set for the GP-Timer. -//! -//! \return Returns one of the following values: -//! - \ref PRCM_CLOCK_DIV_1 -//! - \ref PRCM_CLOCK_DIV_2 -//! - \ref PRCM_CLOCK_DIV_4 -//! - \ref PRCM_CLOCK_DIV_8 -//! - \ref PRCM_CLOCK_DIV_16 -//! - \ref PRCM_CLOCK_DIV_32 -//! - \ref PRCM_CLOCK_DIV_64 -//! - \ref PRCM_CLOCK_DIV_128 -//! - \ref PRCM_CLOCK_DIV_256 -//! -//! \sa \ref PRCMGPTimerClockDivisionSet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -PRCMGPTimerClockDivisionGet( void ) -{ - return ( HWREG( PRCM_BASE + PRCM_O_GPTCLKDIV )); -} - - -//***************************************************************************** -// -//! \brief Enable the audio clock generation. -//! -//! Use this function to enable the audio clock generation. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -PRCMAudioClockEnable(void) -{ - // Enable the audio clock generation. - HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Disable the audio clock generation. -//! -//! Use this function to disable the audio clock generation. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -PRCMAudioClockDisable(void) -{ - // Disable the audio clock generation - HWREGBITW(PRCM_BASE + PRCM_O_I2SCLKCTL, PRCM_I2SCLKCTL_EN_BITN) = 0; -} - -//***************************************************************************** -// -//! \brief Configure the audio clock generation. -//! -//! \deprecated This function will be removed in a future release. -//! -//! Use this function to set the sample rate when using internal audio clock -//! generation for the I2S module. -//! -//! \note While other clocks are possible, the stability of the four sample -//! rates defined here are only guaranteed if the clock input to the I2S module -//! is 48MHz. -//! -//! \param ui32ClkConfig is the audio clock configuration. -//! The parameter is a bitwise OR'ed value consisting of: -//! - Phase -//! - \ref PRCM_WCLK_SINGLE_PHASE -//! - \ref PRCM_WCLK_DUAL_PHASE -//! - Clock polarity -//! - \ref PRCM_WCLK_NEG_EDGE -//! - \ref PRCM_WCLK_POS_EDGE -//! \param ui32SampleRate is the desired audio clock sample rate. -//! The supported sample rate configurations are: -//! - \ref I2S_SAMPLE_RATE_16K -//! - \ref I2S_SAMPLE_RATE_24K -//! - \ref I2S_SAMPLE_RATE_32K -//! - \ref I2S_SAMPLE_RATE_48K -//! -//! \return None -//! -//! \sa \ref PRCMAudioClockConfigSetOverride() -// -//***************************************************************************** -#ifndef DEPRECATED -extern void PRCMAudioClockConfigSet(uint32_t ui32ClkConfig, - uint32_t ui32SampleRate); -#endif - -//***************************************************************************** -// -//! \brief Configure the audio clock generation with manual setting of clock divider. -//! -//! \deprecated This function will be removed in a future release. -//! -//! Use this function to set the audio clock divider values manually. -//! -//! \note See hardware documentation before setting audio clock dividers manually. -//! -//! \param ui32ClkConfig is the audio clock configuration. -//! The parameter is a bitwise OR'ed value consisting of: -//! - Phase -//! - \ref PRCM_WCLK_SINGLE_PHASE -//! - \ref PRCM_WCLK_DUAL_PHASE -//! - Clock polarity -//! - \ref PRCM_WCLK_NEG_EDGE -//! - \ref PRCM_WCLK_POS_EDGE -//! \param ui32MstDiv is the desired master clock divider. -//! \param ui32WordDiv is the desired word clock divider. -//! \param ui32BitDiv is the desired bit clock divider. -//! -//! \return None -//! -//! \sa \ref PRCMAudioClockConfigSet() -// -//***************************************************************************** -#ifndef DEPRECATED -extern void PRCMAudioClockConfigSetOverride(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, - uint32_t ui32BitDiv, uint32_t ui32WordDiv); -#endif - -//***************************************************************************** -// -//! \brief Configure the audio clocks for I2S module. -//! -//! \note See hardware documentation before setting audio clock dividers. -//! This is user's responsability to provide valid clock dividers. -//! -//! \param ui8SamplingEdge Define the clock polarity: -//! - \ref PRCM_I2S_WCLK_NEG_EDGE -//! - \ref PRCM_I2S_WCLK_POS_EDGE -//! \param ui8WCLKPhase Define I2S phase used -//! - PRCM_I2S_WCLK_SINGLE_PHASE -//! - PRCM_I2S_WCLK_DUAL_PHASE -//! - PRCM_I2S_WCLK_USER_DEF -//! \param ui32MstDiv is the desired master clock divider. -//! \param ui32BitDiv is the desired bit clock divider. -//! \param ui32WordDiv is the desired word clock divider. -//! -//! \return None -//! -//***************************************************************************** -extern void PRCMAudioClockConfigOverride - (uint8_t ui8SamplingEdge, - uint8_t ui8WCLKPhase, - uint32_t ui32MstDiv, - uint32_t ui32BitDiv, - uint32_t ui32WordDiv); - -//***************************************************************************** -// -//! \brief Configure the audio clocks to be internally generated. -//! -//! Use this function to set the audio clocks as internal. -//! -//! \return None -//! -//! \sa \ref PRCMAudioClockExternalSource() -// -//***************************************************************************** -extern void PRCMAudioClockInternalSource(void); - -//***************************************************************************** -// -//! \brief Configure the audio clocks to be externally generated. -//! -//! Use this function to set the audio clocks as external. -//! -//! \return None -//! -//! \sa \ref PRCMAudioClockInternalSource() -// -//***************************************************************************** -extern void PRCMAudioClockExternalSource(void); - -//***************************************************************************** -// -//! \brief Use this function to synchronize the load settings. -//! -//! Most of the clock settings in the PRCM module should be updated -//! synchronously. This is ensured by the implementation of a load registers -//! that, when written to, will let the previous written update values for all -//! the relevant registers propagate through to hardware. -//! -//! The functions that require a synchronization of the clock settings are: -//! - \ref PRCMAudioClockConfigSet() -//! - \ref PRCMAudioClockConfigSetOverride() -//! - \ref PRCMAudioClockDisable() -//! - \ref PRCMDomainEnable() -//! - \ref PRCMDomainDisable() -//! - \ref PRCMPeripheralRunEnable() -//! - \ref PRCMPeripheralRunDisable() -//! - \ref PRCMPeripheralSleepEnable() -//! - \ref PRCMPeripheralSleepDisable() -//! - \ref PRCMPeripheralDeepSleepEnable() -//! - \ref PRCMPeripheralDeepSleepDisable() -//! -//! \return None -//! -//! \sa \ref PRCMLoadGet() -// -//***************************************************************************** -__STATIC_INLINE void -PRCMLoadSet(void) -{ - // Enable the update of all load related registers. - HWREG(PRCM_NONBUF_BASE + PRCM_O_CLKLOADCTL) = PRCM_CLKLOADCTL_LOAD; -} - -//***************************************************************************** -// -//! \brief Check if any of the load sensitive register has been updated. -//! -//! \return Returns status of the load sensitive register: -//! - \c true : No registers have changed since the last load. -//! - \c false : Any register has changed. -//! -//! \sa \ref PRCMLoadSet() -// -//***************************************************************************** -__STATIC_INLINE bool -PRCMLoadGet(void) -{ - // Return the load status. - return ((HWREG(PRCM_BASE + PRCM_O_CLKLOADCTL) & PRCM_CLKLOADCTL_LOAD_DONE) ? - true : false); -} - -//***************************************************************************** -// -//! \brief Enable clock domains in the MCU voltage domain. -//! -//! \note A call to this function will only setup the shadow registers in the -//! MCU domain for the PRCM module. For the changes to propagate to the system -//! controller in the AON domain a call to this function should always be -//! followed by a call to \ref PRCMLoadSet(). -//! -//! \note Clocks will only be running if the domain is powered. -//! -//! \param ui32Domains is a bit mask containing the clock domains to enable. -//! The independent clock domains inside the MCU voltage domain which can be -//! configured are: -//! - \ref PRCM_DOMAIN_RFCORE -//! - \ref PRCM_DOMAIN_VIMS -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -PRCMDomainEnable(uint32_t ui32Domains) -{ - // Check the arguments. - ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || - (ui32Domains & PRCM_DOMAIN_VIMS)); - - // Enable the clock domain(s). - if(ui32Domains & PRCM_DOMAIN_RFCORE) - { - HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = PRCM_RFCCLKG_CLK_EN; - } - if(ui32Domains & PRCM_DOMAIN_VIMS) - { - HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = PRCM_VIMSCLKG_CLK_EN_M; - } -} - -//***************************************************************************** -// -//! \brief Disable clock domains in the MCU voltage domain. -//! -//! \note A call to this function will only setup the shadow registers in the -//! MCU domain for the PRCM module. For the changes to propagate to the system -//! controller in the AON domain a call to this function should always be -//! followed by a call to \ref PRCMLoadSet(). -//! -//! \note Clocks will only be running if the domain is powered. -//! -//! \param ui32Domains is a bit mask containing the clock domains to disable. -//! The independent clock domains inside the MCU voltage domain are: -//! - \ref PRCM_DOMAIN_RFCORE -//! - \ref PRCM_DOMAIN_VIMS -//! -//! \return None -//! -//! \sa PRCMDomainEnable() -// -//***************************************************************************** -__STATIC_INLINE void -PRCMDomainDisable(uint32_t ui32Domains) -{ - // Check the arguments. - ASSERT((ui32Domains & PRCM_DOMAIN_RFCORE) || - (ui32Domains & PRCM_DOMAIN_VIMS)); - - // Disable the power domains. - if(ui32Domains & PRCM_DOMAIN_RFCORE) - { - HWREG(PRCM_BASE + PRCM_O_RFCCLKG) = 0x0; - } - if(ui32Domains & PRCM_DOMAIN_VIMS) - { - HWREG(PRCM_BASE + PRCM_O_VIMSCLKG) = 0x0; - } -} - -//***************************************************************************** -// -//! \brief Turn power on in power domains in the MCU domain. -//! -//! Use this function to turn on power domains inside the MCU voltage domain. -//! -//! Power on and power off request has different implications for the -//! different power domains. -//! - RF Core power domain: -//! - Power On : Domain is on or in the process of turning on. -//! - Power Off : Domain is powered down when System CPU is in deep sleep. The third -//! option for the RF Core is to power down when the it is idle. -//! This can be set using \b PRCMRfPowerDownWhenIdle() -//! - SERIAL power domain: -//! - Power on : Domain is powered on. -//! - Power off : Domain is powered off. -//! - PERIPHERIAL power domain: -//! - Power on : Domain is powered on. -//! - Power off : Domain is powered off. -//! - VIMS power domain: -//! - Power On : Domain is powered if Bus domain is powered. -//! - Power Off : Domain is only powered when CPU domain is on. -//! - BUS power domain: -//! - Power On : Domain is on. -//! - Power Off : Domain is on if requested by RF Core or if CPU domain is on. -//! - CPU power domain: -//! - Power On : Domain is on. -//! - Power Off : Domain is powering down if System CPU is idle. This will also -//! initiate a power down of the SRAM and BUS power domains, unless -//! RF Core is requesting them to be on. -//! -//! \note After a call to this function the status of the power domain should -//! be checked using either \ref PRCMPowerDomainStatus(). -//! Any write operation to a power domain which is still not operational can -//! result in unexpected behavior. -//! -//! \param ui32Domains determines which power domains to turn on. -//! The domains that can be turned on/off are: -//! - \b PRCM_DOMAIN_RFCORE : RF Core -//! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 -//! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 -//! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM -//! - \b PRCM_DOMAIN_SYSBUS -//! - \b PRCM_DOMAIN_CPU -//! -//! \return None -// -//***************************************************************************** -extern void PRCMPowerDomainOn(uint32_t ui32Domains); - -//***************************************************************************** -// -//! \brief Turn off a specific power domain. -//! -//! Use this function to power down domains inside the MCU voltage domain. -//! -//! \note For specifics regarding on/off configuration please see -//! \ref PRCMPowerDomainOn(). -//! -//! \param ui32Domains determines which domain to request a power down for. -//! The domains that can be turned on/off are: -//! - \b PRCM_DOMAIN_RFCORE : RF Core -//! - \b PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 -//! - \b PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 -//! - \b PRCM_DOMAIN_VIMS : SRAM, FLASH, ROM -//! - \b PRCM_DOMAIN_VIMS_OFF_NO_WAKEUP : SRAM, FLASH, ROM -//! - \b PRCM_DOMAIN_SYSBUS -//! - \b PRCM_DOMAIN_CPU -//! -//! \return None -// -//***************************************************************************** -extern void PRCMPowerDomainOff(uint32_t ui32Domains); - -//***************************************************************************** -// -//! \brief Configure RF core to power down when idle. -//! -//! Use this function to configure the RF core to power down when Idle. This -//! is handled automatically in hardware if the RF Core reports that it is -//! idle. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -PRCMRfPowerDownWhenIdle(void) -{ - // Configure the RF power domain. - HWREGBITW(PRCM_BASE + PRCM_O_PDCTL0RFC, PRCM_PDCTL0RFC_ON_BITN) = 0; -} - -//***************************************************************************** -// -//! \brief Enables a peripheral in Run mode. -//! -//! Peripherals are enabled with this function. At power-up, some peripherals -//! are disabled; they must be enabled in order to operate or respond to -//! register reads/writes. -//! -//! \note The actual enabling of the peripheral may be delayed until some -//! time after this function returns. Care should be taken to ensure that the -//! peripheral is not accessed until it is enabled. -//! When enabling Timers always make sure that the division factor for the -//! \b PERBUSCPUCLK is set. This will guarantee that the timers run at a -//! continuous rate even if the \b SYSBUSCLK is gated. -//! -//! \note A call to this function will only setup the shadow registers in the -//! MCU domain for the PRCM module. For the changes to propagate to the system -//! controller in the AON domain a call to this function should always be -//! followed by a call to \ref PRCMLoadSet(). -//! -//! \param ui32Peripheral is the peripheral to enable. -//! The parameter must be one of the following: -//! - \ref PRCM_PERIPH_TIMER0 -//! - \ref PRCM_PERIPH_TIMER1 -//! - \ref PRCM_PERIPH_TIMER2 -//! - \ref PRCM_PERIPH_TIMER3 -//! - \ref PRCM_PERIPH_SSI0 -//! - \ref PRCM_PERIPH_SSI1 -//! - \ref PRCM_PERIPH_UART0 -//! - \ref PRCM_PERIPH_UART1 -//! - \ref PRCM_PERIPH_I2C0 -//! - \ref PRCM_PERIPH_CRYPTO -//! - \ref PRCM_PERIPH_TRNG -//! - \ref PRCM_PERIPH_PKA -//! - \ref PRCM_PERIPH_UDMA -//! - \ref PRCM_PERIPH_GPIO -//! - \ref PRCM_PERIPH_I2S -//! -//! \return None -//! -//! \sa \ref PRCMLoadSet() -// -//***************************************************************************** -extern void PRCMPeripheralRunEnable(uint32_t ui32Peripheral); - -//***************************************************************************** -// -//! \brief Disables a peripheral in Run mode -//! -//! Peripherals are disabled with this function. Once disabled, they will not -//! operate or respond to register reads/writes. -//! -//! \note A call to this function will only setup the shadow registers in the -//! MCU domain for the PRCM module. For the changes to propagate to the system -//! controller in the AON domain a call to this function should always be -//! followed by a call to \ref PRCMLoadSet(). -//! -//! \note The actual disabling of the peripheral may be delayed until some -//! time after this function returns. Care should be taken by the user to -//! ensure that the peripheral is not accessed in this interval as this might -//! cause the system to hang. -//! -//! \param ui32Peripheral is the peripheral to disable. -//! The parameter must be one of the following: -//! - \ref PRCM_PERIPH_TIMER0 -//! - \ref PRCM_PERIPH_TIMER1 -//! - \ref PRCM_PERIPH_TIMER2 -//! - \ref PRCM_PERIPH_TIMER3 -//! - \ref PRCM_PERIPH_SSI0 -//! - \ref PRCM_PERIPH_SSI1 -//! - \ref PRCM_PERIPH_UART0 -//! - \ref PRCM_PERIPH_UART1 -//! - \ref PRCM_PERIPH_I2C0 -//! - \ref PRCM_PERIPH_CRYPTO -//! - \ref PRCM_PERIPH_TRNG -//! - \ref PRCM_PERIPH_PKA -//! - \ref PRCM_PERIPH_UDMA -//! - \ref PRCM_PERIPH_GPIO -//! - \ref PRCM_PERIPH_I2S -//! -//! \return None -//! -//! \sa \ref PRCMLoadSet() -// -//***************************************************************************** -extern void PRCMPeripheralRunDisable(uint32_t ui32Peripheral); - -//***************************************************************************** -// -//! \brief Enables a peripheral in sleep mode. -//! -//! This function allows a peripheral to continue operating when the processor -//! goes into sleep mode. Since the clocking configuration of the device does -//! not change, any peripheral can safely continue operating while the -//! processor is in sleep mode, and can therefore wake the processor from sleep -//! mode. -//! -//! \note A call to this function will only setup the shadow registers in the -//! MCU domain for the PRCM module. For the changes to propagate to the system -//! controller in the AON domain a call to this function should always be -//! followed by a call to \ref PRCMLoadSet(). -//! -//! \param ui32Peripheral is the peripheral to enable in sleep mode. -//! The parameter must be one of the following: -//! - \ref PRCM_PERIPH_TIMER0 -//! - \ref PRCM_PERIPH_TIMER1 -//! - \ref PRCM_PERIPH_TIMER2 -//! - \ref PRCM_PERIPH_TIMER3 -//! - \ref PRCM_PERIPH_SSI0 -//! - \ref PRCM_PERIPH_SSI1 -//! - \ref PRCM_PERIPH_UART0 -//! - \ref PRCM_PERIPH_UART1 -//! - \ref PRCM_PERIPH_I2C0 -//! - \ref PRCM_PERIPH_CRYPTO -//! - \ref PRCM_PERIPH_TRNG -//! - \ref PRCM_PERIPH_PKA -//! - \ref PRCM_PERIPH_UDMA -//! - \ref PRCM_PERIPH_GPIO -//! - \ref PRCM_PERIPH_I2S -//! -//! \return None -//! -//! \sa \ref PRCMLoadSet() -// -//***************************************************************************** -extern void PRCMPeripheralSleepEnable(uint32_t ui32Peripheral); - -//***************************************************************************** -// -//! \brief Disables a peripheral in sleep mode. -//! -//! This function causes a peripheral to stop operating when the processor goes -//! into sleep mode. Disabling peripherals while in sleep mode helps to lower -//! the current draw of the device. If enabled (via \ref PRCMPeripheralRunEnable()), -//! the peripheral will automatically resume operation when the processor -//! leaves sleep mode, maintaining its entire state from before sleep mode was -//! entered. -//! -//! \note A call to this function will only setup the shadow registers in the -//! MCU domain for the PRCM module. For the changes to propagate to the system -//! controller in the AON domain a call to this function should always be -//! followed by a call to \ref PRCMLoadSet(). -//! -//! \param ui32Peripheral is the peripheral to disable in sleep mode. -//! The parameter must be one of the following: -//! - \ref PRCM_PERIPH_TIMER0 -//! - \ref PRCM_PERIPH_TIMER1 -//! - \ref PRCM_PERIPH_TIMER2 -//! - \ref PRCM_PERIPH_TIMER3 -//! - \ref PRCM_PERIPH_SSI0 -//! - \ref PRCM_PERIPH_SSI1 -//! - \ref PRCM_PERIPH_UART0 -//! - \ref PRCM_PERIPH_UART1 -//! - \ref PRCM_PERIPH_I2C0 -//! - \ref PRCM_PERIPH_CRYPTO -//! - \ref PRCM_PERIPH_TRNG -//! - \ref PRCM_PERIPH_PKA -//! - \ref PRCM_PERIPH_UDMA -//! - \ref PRCM_PERIPH_GPIO -//! - \ref PRCM_PERIPH_I2S -//! -//! \return None -//! -//! \sa \ref PRCMLoadSet() -// -//***************************************************************************** -extern void PRCMPeripheralSleepDisable(uint32_t ui32Peripheral); - -//***************************************************************************** -// -//! \brief Enables a peripheral in deep-sleep mode. -//! -//! This function allows a peripheral to continue operating when the processor -//! goes into deep-sleep mode. Since the clocking configuration of the device -//! may change, not all peripherals can safely continue operating while the -//! processor is in sleep mode. This in turn depends on the chosen power mode. -//! It is the responsibility of the caller to make sensible choices. -//! -//! \note A call to this function will only setup the shadow registers in the -//! MCU domain for the PRCM module. For the changes to propagate to the system -//! controller in the AON domain a call to this function should always be -//! followed by a call to \ref PRCMLoadSet(). -//! -//! \param ui32Peripheral is the peripheral to enable in deep-sleep mode. -//! The parameter must be one of the following: -//! - \ref PRCM_PERIPH_TIMER0 -//! - \ref PRCM_PERIPH_TIMER1 -//! - \ref PRCM_PERIPH_TIMER2 -//! - \ref PRCM_PERIPH_TIMER3 -//! - \ref PRCM_PERIPH_SSI0 -//! - \ref PRCM_PERIPH_SSI1 -//! - \ref PRCM_PERIPH_UART0 -//! - \ref PRCM_PERIPH_UART1 -//! - \ref PRCM_PERIPH_I2C0 -//! - \ref PRCM_PERIPH_CRYPTO -//! - \ref PRCM_PERIPH_TRNG -//! - \ref PRCM_PERIPH_PKA -//! - \ref PRCM_PERIPH_UDMA -//! - \ref PRCM_PERIPH_GPIO -//! - \ref PRCM_PERIPH_I2S -//! -//! \return None -//! -//! \sa \ref PRCMLoadSet() -// -//***************************************************************************** -extern void PRCMPeripheralDeepSleepEnable(uint32_t ui32Peripheral); - -//***************************************************************************** -// -//! \brief Disables a peripheral in deep-sleep mode. -//! -//! This function causes a peripheral to stop operating when the processor goes -//! into deep-sleep mode. Disabling peripherals while in deep-sleep mode helps -//! to lower the current draw of the device, and can keep peripherals that -//! require a particular clock frequency from operating when the clock changes -//! as a result of entering deep-sleep mode. If enabled (via -//! \ref PRCMPeripheralRunEnable()), the peripheral will automatically resume -//! operation when the processor leaves deep-sleep mode, maintaining its entire -//! state from before deep-sleep mode was entered. -//! -//! \note A call to this function will only setup the shadow registers in the -//! MCU domain for the PRCM module. For the changes to propagate to the system -//! controller in the AON domain a call to this function should always be -//! followed by a call to \ref PRCMLoadSet(). -//! -//! \param ui32Peripheral is the peripheral to disable in deep-sleep mode. -//! The parameter must be one of the following: -//! - \ref PRCM_PERIPH_TIMER0 -//! - \ref PRCM_PERIPH_TIMER1 -//! - \ref PRCM_PERIPH_TIMER2 -//! - \ref PRCM_PERIPH_TIMER3 -//! - \ref PRCM_PERIPH_SSI0 -//! - \ref PRCM_PERIPH_SSI1 -//! - \ref PRCM_PERIPH_UART0 -//! - \ref PRCM_PERIPH_UART1 -//! - \ref PRCM_PERIPH_I2C0 -//! - \ref PRCM_PERIPH_CRYPTO -//! - \ref PRCM_PERIPH_TRNG -//! - \ref PRCM_PERIPH_PKA -//! - \ref PRCM_PERIPH_UDMA -//! - \ref PRCM_PERIPH_GPIO -//! - \ref PRCM_PERIPH_I2S -//! -//! \return None -//! -//! \sa \ref PRCMLoadSet() -// -//***************************************************************************** -extern void PRCMPeripheralDeepSleepDisable(uint32_t ui32Peripheral); - -//***************************************************************************** -// -//! \brief Get the status for a specific power domain. -//! -//! Use this function to retrieve the current power status of one or more -//! power domains. -//! -//! \param ui32Domains determines which domain to get the power status for. -//! The parameter must be an OR'ed combination of one or several of: -//! - \ref PRCM_DOMAIN_RFCORE : RF Core. -//! - \ref PRCM_DOMAIN_SERIAL : SSI0, UART0, I2C0 -//! - \ref PRCM_DOMAIN_PERIPH : GPT0, GPT1, GPT2, GPT3, GPIO, SSI1, I2S, DMA, UART1 -//! -//! \return Returns status of the requested domains: -//! - \ref PRCM_DOMAIN_POWER_ON : The specified domains are \b all powered up. -//! This status is unconditional and the powered up status is guaranteed. -//! - \ref PRCM_DOMAIN_POWER_OFF : Any of the domains are powered down. -// -//***************************************************************************** -extern uint32_t PRCMPowerDomainStatus(uint32_t ui32Domains); - -//***************************************************************************** -// -//! \brief Return the access status of the RF Core. -//! -//! Use this function to check if the RF Core is on and ready to be accessed. -//! Accessing register or memories that are not powered and clocked will -//! cause a bus fault. -//! -//! \return Returns access status of the RF Core. -//! - \c true : RF Core can be accessed. -//! - \c false : RF Core domain is not ready for access. -// -//***************************************************************************** -__STATIC_INLINE bool -PRCMRfReady(void) -{ - // Return the ready status of the RF Core. - return ((HWREG(PRCM_BASE + PRCM_O_PDSTAT1RFC) & - PRCM_PDSTAT1RFC_ON) ? true : false); -} - - -//***************************************************************************** -// -//! \brief Put the processor into sleep mode. -//! -//! This function places the processor into sleep mode; it does not return -//! until the processor returns to run mode. The peripherals that are enabled -//! via PRCMPeripheralSleepEnable() continue to operate and can wake up the -//! processor. -//! -//! \return None -//! -//! \sa \ref PRCMPeripheralSleepEnable() -// -//***************************************************************************** -__STATIC_INLINE void -PRCMSleep(void) -{ - // Wait for an interrupt. - CPUwfi(); -} - -//***************************************************************************** -// -//! \brief Put the processor into deep-sleep mode. -//! -//! This function places the processor into deep-sleep mode; it does not return -//! until the processor returns to run mode. The peripherals that are enabled -//! via \ref PRCMPeripheralDeepSleepEnable() continue to operate and can wake up -//! the processor. -//! -//! \return None -//! -//! \sa \ref PRCMPeripheralDeepSleepEnable() -// -//***************************************************************************** -extern void PRCMDeepSleep(void); - -//***************************************************************************** -// -//! \brief Enable CACHE RAM retention -//! -//! Enables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -PRCMCacheRetentionEnable( void ) -{ - HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) |= PRCM_RAMRETEN_VIMS_M; -} - -//***************************************************************************** -// -//! \brief Disable CACHE RAM retention -//! -//! Disables CACHE RAM retention on both VIMS_TRAM and VIMS_CRAM -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -PRCMCacheRetentionDisable( void ) -{ - HWREG( PRCM_BASE + PRCM_O_RAMRETEN ) &= ~PRCM_RAMRETEN_VIMS_M; -} - - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_PRCMInfClockConfigureSet - #undef PRCMInfClockConfigureSet - #define PRCMInfClockConfigureSet ROM_PRCMInfClockConfigureSet - #endif - #ifdef ROM_PRCMInfClockConfigureGet - #undef PRCMInfClockConfigureGet - #define PRCMInfClockConfigureGet ROM_PRCMInfClockConfigureGet - #endif - #ifdef ROM_PRCMAudioClockConfigSet - #undef PRCMAudioClockConfigSet - #define PRCMAudioClockConfigSet ROM_PRCMAudioClockConfigSet - #endif - #ifdef ROM_PRCMAudioClockConfigSetOverride - #undef PRCMAudioClockConfigSetOverride - #define PRCMAudioClockConfigSetOverride ROM_PRCMAudioClockConfigSetOverride - #endif - #ifdef ROM_PRCMAudioClockInternalSource - #undef PRCMAudioClockInternalSource - #define PRCMAudioClockInternalSource ROM_PRCMAudioClockInternalSource - #endif - #ifdef ROM_PRCMAudioClockExternalSource - #undef PRCMAudioClockExternalSource - #define PRCMAudioClockExternalSource ROM_PRCMAudioClockExternalSource - #endif - #ifdef ROM_PRCMPowerDomainOn - #undef PRCMPowerDomainOn - #define PRCMPowerDomainOn ROM_PRCMPowerDomainOn - #endif - #ifdef ROM_PRCMPowerDomainOff - #undef PRCMPowerDomainOff - #define PRCMPowerDomainOff ROM_PRCMPowerDomainOff - #endif - #ifdef ROM_PRCMPeripheralRunEnable - #undef PRCMPeripheralRunEnable - #define PRCMPeripheralRunEnable ROM_PRCMPeripheralRunEnable - #endif - #ifdef ROM_PRCMPeripheralRunDisable - #undef PRCMPeripheralRunDisable - #define PRCMPeripheralRunDisable ROM_PRCMPeripheralRunDisable - #endif - #ifdef ROM_PRCMPeripheralSleepEnable - #undef PRCMPeripheralSleepEnable - #define PRCMPeripheralSleepEnable ROM_PRCMPeripheralSleepEnable - #endif - #ifdef ROM_PRCMPeripheralSleepDisable - #undef PRCMPeripheralSleepDisable - #define PRCMPeripheralSleepDisable ROM_PRCMPeripheralSleepDisable - #endif - #ifdef ROM_PRCMPeripheralDeepSleepEnable - #undef PRCMPeripheralDeepSleepEnable - #define PRCMPeripheralDeepSleepEnable ROM_PRCMPeripheralDeepSleepEnable - #endif - #ifdef ROM_PRCMPeripheralDeepSleepDisable - #undef PRCMPeripheralDeepSleepDisable - #define PRCMPeripheralDeepSleepDisable ROM_PRCMPeripheralDeepSleepDisable - #endif - #ifdef ROM_PRCMPowerDomainStatus - #undef PRCMPowerDomainStatus - #define PRCMPowerDomainStatus ROM_PRCMPowerDomainStatus - #endif - #ifdef ROM_PRCMDeepSleep - #undef PRCMDeepSleep - #define PRCMDeepSleep ROM_PRCMDeepSleep - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __PRCM_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.c deleted file mode 100644 index 92e79557efc..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.c +++ /dev/null @@ -1,80 +0,0 @@ -/****************************************************************************** -* Filename: pwr_ctrl.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Power Control driver. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "pwr_ctrl.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef PowerCtrlSourceSet - #define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet -#endif - - -//***************************************************************************** -// -// Set (Request) the main power source -// -//***************************************************************************** -void -PowerCtrlSourceSet(uint32_t ui32PowerConfig) -{ - // Check the arguments. - ASSERT((ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) || - (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) || - (ui32PowerConfig == PWRCTRL_PWRSRC_ULDO)); - - // Configure the power. - if(ui32PowerConfig == PWRCTRL_PWRSRC_DCDC) { - HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) |= - (AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE); - } - else if (ui32PowerConfig == PWRCTRL_PWRSRC_GLDO) - { - HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) &= - ~(AON_PMCTL_PWRCTL_DCDC_EN | AON_PMCTL_PWRCTL_DCDC_ACTIVE); - } - else - { - PRCMMcuUldoConfigure(true); - } -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h deleted file mode 100644 index fe989721712..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/pwr_ctrl.h +++ /dev/null @@ -1,301 +0,0 @@ -/****************************************************************************** -* Filename: pwr_ctrl.h -* Revised: 2017-11-02 15:41:14 +0100 (Thu, 02 Nov 2017) -* Revision: 50165 -* -* Description: Defines and prototypes for the System Power Control. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup pwrctrl_api -//! @{ -// -//***************************************************************************** - -#ifndef __PWR_CTRL_H__ -#define __PWR_CTRL_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_aon_pmctl.h" -#include "../inc/hw_aon_rtc.h" -#include "../inc/hw_adi_2_refsys.h" -#include "debug.h" -#include "interrupt.h" -#include "osc.h" -#include "cpu.h" -#include "prcm.h" -#include "aon_ioc.h" -#include "adi.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define PowerCtrlSourceSet NOROM_PowerCtrlSourceSet -#endif - -//***************************************************************************** -// -// Defines for the system power states -// -//***************************************************************************** -#define PWRCTRL_ACTIVE 0x00000001 -#define PWRCTRL_STANDBY 0x00000002 -#define PWRCTRL_POWER_DOWN 0x00000004 -#define PWRCTRL_SHUTDOWN 0x00000008 - -//***************************************************************************** -// -// Defines for the power configuration in the AON System Control 1.2 V -// -//***************************************************************************** -#define PWRCTRL_IOSEG3_ENABLE 0x00000800 -#define PWRCTRL_IOSEG2_ENABLE 0x00000400 -#define PWRCTRL_IOSEG3_DISABLE 0x00000200 -#define PWRCTRL_IOSEG2_DISABLE 0x00000100 -#define PWRCTRL_PWRSRC_DCDC 0x00000001 -#define PWRCTRL_PWRSRC_GLDO 0x00000000 -#define PWRCTRL_PWRSRC_ULDO 0x00000002 - -//***************************************************************************** -// -// The following are defines for the various reset source for the device. -// -//***************************************************************************** -#define PWRCTRL_RST_POWER_ON 0x00000000 // Reset by power on -#define PWRCTRL_RST_PIN 0x00000001 // Pin reset -#define PWRCTRL_RST_VDDS_BOD 0x00000002 // VDDS Brown Out Detect -#define PWRCTRL_RST_VDD_BOD 0x00000003 // VDD Brown Out Detect -#define PWRCTRL_RST_VDDR_BOD 0x00000004 // VDDR Brown Out Detect -#define PWRCTRL_RST_CLK_LOSS 0x00000005 // Clock loss Reset -#define PWRCTRL_RST_SW_PIN 0x00000006 // SYSRESET or pin reset -#define PWRCTRL_RST_WARM 0x00000007 // Reset via PRCM warm reset request - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Set (Request) the main power source. -//! -//! \note The system will never allow a switch to the \ref PWRCTRL_PWRSRC_ULDO -//! when in active mode. This is only allowed when the system is in lower power -//! mode where no code is executing and no peripherals are active. -//! Assuming that there is an external capacitor available for the -//! \ref PWRCTRL_PWRSRC_DCDC the system can dynamically switch back and forth -//! between the two when in active mode. -//! -//! \note The system will automatically switch to the GLDO / DCDC when waking -//! up from a low power mode. -//! -//! \param ui32PowerConfig is a bitmask indicating the target power source. -//! - \ref PWRCTRL_PWRSRC_DCDC -//! - \ref PWRCTRL_PWRSRC_GLDO -//! - \ref PWRCTRL_PWRSRC_ULDO -//! -//! \return None -// -//***************************************************************************** -extern void PowerCtrlSourceSet(uint32_t ui32PowerConfig); - -//***************************************************************************** -// -//! \brief Get the main power source. -//! -//! Use this function to retrieve the current active power source. -//! -//! When the System CPU is active it can never be powered by uLDO as this -//! is too weak a power source. -//! -//! \note Using the DCDC power supply requires an external inductor. -//! -//! \return Returns the main power source. -//! - \ref PWRCTRL_PWRSRC_DCDC -//! - \ref PWRCTRL_PWRSRC_GLDO -// -//***************************************************************************** -__STATIC_INLINE uint32_t -PowerCtrlSourceGet(void) -{ - uint32_t ui32PowerConfig; - - // Return the current power source - ui32PowerConfig = HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL); - if(ui32PowerConfig & AON_PMCTL_PWRCTL_DCDC_ACTIVE) - { - return (PWRCTRL_PWRSRC_DCDC); - } - else - { - return (PWRCTRL_PWRSRC_GLDO); - } -} - -//***************************************************************************** -// -//! \brief OBSOLETE: Get the last known reset source of the system. -//! -//! \deprecated This function will be removed in a future release. -//! Use \ref SysCtrlResetSourceGet() instead. -//! -//! This function returns reset source but does not cover if waking up from shutdown. -//! This function can be seen as a subset of function \ref SysCtrlResetSourceGet() -//! and will be removed in a future release. -//! -//! \return Returns one of the known reset values. -//! The possible reset sources are: -//! - \ref PWRCTRL_RST_POWER_ON -//! - \ref PWRCTRL_RST_PIN -//! - \ref PWRCTRL_RST_VDDS_BOD -//! - \ref PWRCTRL_RST_VDD_BOD -//! - \ref PWRCTRL_RST_VDDR_BOD -//! - \ref PWRCTRL_RST_CLK_LOSS -//! - \ref PWRCTRL_RST_SW_PIN -//! - \ref PWRCTRL_RST_WARM -//! -//! \sa \ref SysCtrlResetSourceGet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -PowerCtrlResetSourceGet(void) -{ - // Get the reset source. - return (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & - AON_PMCTL_RESETCTL_RESET_SRC_M ) >> - AON_PMCTL_RESETCTL_RESET_SRC_S ) ; -} - -//***************************************************************************** -// -//! \brief Enables pad sleep in order to latch device outputs before shutdown. -//! -//! See \ref SysCtrlShutdown() for more information about how to enter -//! shutdown and how to wake up from shutdown. -//! -//! \return None -//! -//! \sa \ref PowerCtrlPadSleepDisable() -// -//***************************************************************************** -__STATIC_INLINE void -PowerCtrlPadSleepEnable(void) -{ - HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL) = 0; - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); -} - -//***************************************************************************** -// -//! \brief Disables pad sleep in order to unlatch device outputs after wakeup from shutdown. -//! -//! This function must be called by the application after the device wakes up -//! from shutdown. -//! -//! See \ref SysCtrlShutdown() for more information about how to enter -//! shutdown and how to wake up from shutdown. -//! -//! \return None -//! -//! \sa \ref PowerCtrlPadSleepEnable() -// -//***************************************************************************** -__STATIC_INLINE void -PowerCtrlPadSleepDisable(void) -{ - HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL) = 1; - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_PowerCtrlSourceSet - #undef PowerCtrlSourceSet - #define PowerCtrlSourceSet ROM_PowerCtrlSourceSet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __PWR_CTRL_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h deleted file mode 100644 index d8517d0e4d5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_cmd.h +++ /dev/null @@ -1,2674 +0,0 @@ -/****************************************************************************** -* Filename: rf_ble_cmd.h -* Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018) -* Revision: 18572 -* -* Description: CC13x2/CC26x2 API for Bluetooth Low Energy commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __BLE_CMD_H -#define __BLE_CMD_H - -#ifndef __RFC_STRUCT -#define __RFC_STRUCT -#endif - -#ifndef __RFC_STRUCT_ATTR -#if defined(__GNUC__) -#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) -#elif defined(__TI_ARM__) -#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) -#else -#define __RFC_STRUCT_ATTR -#endif -#endif - -//! \addtogroup rfc -//! @{ - -//! \addtogroup ble_cmd -//! @{ - -#include -#include "rf_mailbox.h" -#include "rf_common_cmd.h" - -typedef struct __RFC_STRUCT rfc_bleRadioOp_s rfc_bleRadioOp_t; -typedef struct __RFC_STRUCT rfc_ble5RadioOp_s rfc_ble5RadioOp_t; -typedef struct __RFC_STRUCT rfc_ble5Tx20RadioOp_s rfc_ble5Tx20RadioOp_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s rfc_CMD_BLE_SLAVE_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s rfc_CMD_BLE_MASTER_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_s rfc_CMD_BLE_ADV_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s rfc_CMD_BLE_ADV_DIR_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s rfc_CMD_BLE_ADV_NC_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s rfc_CMD_BLE_ADV_SCAN_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s rfc_CMD_BLE_SCANNER_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s rfc_CMD_BLE_INITIATOR_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s rfc_CMD_BLE_GENERIC_RX_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s rfc_CMD_BLE_TX_TEST_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s rfc_CMD_BLE_ADV_PAYLOAD_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s rfc_CMD_BLE5_RADIO_SETUP_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_SLAVE_s rfc_CMD_BLE5_SLAVE_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_MASTER_s rfc_CMD_BLE5_MASTER_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_EXT_s rfc_CMD_BLE5_ADV_EXT_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_AUX_s rfc_CMD_BLE5_ADV_AUX_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_s rfc_CMD_BLE5_SCANNER_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_INITIATOR_s rfc_CMD_BLE5_INITIATOR_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_GENERIC_RX_s rfc_CMD_BLE5_GENERIC_RX_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_TX_TEST_s rfc_CMD_BLE5_TX_TEST_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_s rfc_CMD_BLE5_ADV_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_DIR_s rfc_CMD_BLE5_ADV_DIR_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_NC_s rfc_CMD_BLE5_ADV_NC_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_ADV_SCAN_s rfc_CMD_BLE5_ADV_SCAN_t; -typedef struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_PA_s rfc_CMD_BLE5_RADIO_SETUP_PA_t; -typedef struct __RFC_STRUCT rfc_bleMasterSlavePar_s rfc_bleMasterSlavePar_t; -typedef struct __RFC_STRUCT rfc_bleSlavePar_s rfc_bleSlavePar_t; -typedef struct __RFC_STRUCT rfc_bleMasterPar_s rfc_bleMasterPar_t; -typedef struct __RFC_STRUCT rfc_bleAdvPar_s rfc_bleAdvPar_t; -typedef struct __RFC_STRUCT rfc_bleScannerPar_s rfc_bleScannerPar_t; -typedef struct __RFC_STRUCT rfc_bleInitiatorPar_s rfc_bleInitiatorPar_t; -typedef struct __RFC_STRUCT rfc_bleGenericRxPar_s rfc_bleGenericRxPar_t; -typedef struct __RFC_STRUCT rfc_bleTxTestPar_s rfc_bleTxTestPar_t; -typedef struct __RFC_STRUCT rfc_ble5SlavePar_s rfc_ble5SlavePar_t; -typedef struct __RFC_STRUCT rfc_ble5MasterPar_s rfc_ble5MasterPar_t; -typedef struct __RFC_STRUCT rfc_ble5AdvExtPar_s rfc_ble5AdvExtPar_t; -typedef struct __RFC_STRUCT rfc_ble5AdvAuxPar_s rfc_ble5AdvAuxPar_t; -typedef struct __RFC_STRUCT rfc_ble5AuxChRes_s rfc_ble5AuxChRes_t; -typedef struct __RFC_STRUCT rfc_ble5ScannerPar_s rfc_ble5ScannerPar_t; -typedef struct __RFC_STRUCT rfc_ble5InitiatorPar_s rfc_ble5InitiatorPar_t; -typedef struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s rfc_bleMasterSlaveOutput_t; -typedef struct __RFC_STRUCT rfc_bleAdvOutput_s rfc_bleAdvOutput_t; -typedef struct __RFC_STRUCT rfc_bleScannerOutput_s rfc_bleScannerOutput_t; -typedef struct __RFC_STRUCT rfc_bleInitiatorOutput_s rfc_bleInitiatorOutput_t; -typedef struct __RFC_STRUCT rfc_ble5ScanInitOutput_s rfc_ble5ScanInitOutput_t; -typedef struct __RFC_STRUCT rfc_bleGenericRxOutput_s rfc_bleGenericRxOutput_t; -typedef struct __RFC_STRUCT rfc_bleTxTestOutput_s rfc_bleTxTestOutput_t; -typedef struct __RFC_STRUCT rfc_ble5ExtAdvEntry_s rfc_ble5ExtAdvEntry_t; -typedef struct __RFC_STRUCT rfc_bleWhiteListEntry_s rfc_bleWhiteListEntry_t; -typedef struct __RFC_STRUCT rfc_ble5AdiEntry_s rfc_ble5AdiEntry_t; -typedef struct __RFC_STRUCT rfc_bleRxStatus_s rfc_bleRxStatus_t; -typedef struct __RFC_STRUCT rfc_ble5RxStatus_s rfc_ble5RxStatus_t; - -//! \addtogroup bleRadioOp -//! @{ -struct __RFC_STRUCT rfc_bleRadioOp_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - uint8_t* pParams; //!< Pointer to command specific parameter structure - uint8_t* pOutput; //!< Pointer to command specific output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5RadioOp -//! @{ -struct __RFC_STRUCT rfc_ble5RadioOp_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - uint8_t* pParams; //!< Pointer to command specific parameter structure - uint8_t* pOutput; //!< Pointer to command specific output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5Tx20RadioOp -//! @{ -//! Command structure for Bluetooth commands which includes the optional field for 20-dBm PA TX power -struct __RFC_STRUCT rfc_ble5Tx20RadioOp_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - uint8_t* pParams; //!< Pointer to command specific parameter structure - uint8_t* pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE_SLAVE -//! @{ -#define CMD_BLE_SLAVE 0x1801 -//! BLE Slave Command -struct __RFC_STRUCT rfc_CMD_BLE_SLAVE_s { - uint16_t commandNo; //!< The command ID number 0x1801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleSlavePar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE_MASTER -//! @{ -#define CMD_BLE_MASTER 0x1802 -//! BLE Master Command -struct __RFC_STRUCT rfc_CMD_BLE_MASTER_s { - uint16_t commandNo; //!< The command ID number 0x1802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleMasterPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE_ADV -//! @{ -#define CMD_BLE_ADV 0x1803 -//! BLE Connectable Undirected Advertiser Command -struct __RFC_STRUCT rfc_CMD_BLE_ADV_s { - uint16_t commandNo; //!< The command ID number 0x1803 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE_ADV_DIR -//! @{ -#define CMD_BLE_ADV_DIR 0x1804 -//! BLE Connectable Directed Advertiser Command -struct __RFC_STRUCT rfc_CMD_BLE_ADV_DIR_s { - uint16_t commandNo; //!< The command ID number 0x1804 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE_ADV_NC -//! @{ -#define CMD_BLE_ADV_NC 0x1805 -//! BLE Non-Connectable Advertiser Command -struct __RFC_STRUCT rfc_CMD_BLE_ADV_NC_s { - uint16_t commandNo; //!< The command ID number 0x1805 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE_ADV_SCAN -//! @{ -#define CMD_BLE_ADV_SCAN 0x1806 -//! BLE Scannable Undirected Advertiser Command -struct __RFC_STRUCT rfc_CMD_BLE_ADV_SCAN_s { - uint16_t commandNo; //!< The command ID number 0x1806 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE_SCANNER -//! @{ -#define CMD_BLE_SCANNER 0x1807 -//! BLE Scanner Command -struct __RFC_STRUCT rfc_CMD_BLE_SCANNER_s { - uint16_t commandNo; //!< The command ID number 0x1807 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleScannerPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleScannerOutput_t *pOutput; //!< Pointer to command specific output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE_INITIATOR -//! @{ -#define CMD_BLE_INITIATOR 0x1808 -//! BLE Initiator Command -struct __RFC_STRUCT rfc_CMD_BLE_INITIATOR_s { - uint16_t commandNo; //!< The command ID number 0x1808 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleInitiatorPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleInitiatorOutput_t *pOutput; //!< Pointer to command specific output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE_GENERIC_RX -//! @{ -#define CMD_BLE_GENERIC_RX 0x1809 -//! BLE Generic Receiver Command -struct __RFC_STRUCT rfc_CMD_BLE_GENERIC_RX_s { - uint16_t commandNo; //!< The command ID number 0x1809 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleGenericRxPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleGenericRxOutput_t *pOutput; //!< Pointer to command specific output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE_TX_TEST -//! @{ -#define CMD_BLE_TX_TEST 0x180A -//! BLE PHY Test Transmitter Command -struct __RFC_STRUCT rfc_CMD_BLE_TX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x180A - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - rfc_bleTxTestPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleTxTestOutput_t *pOutput; //!< Pointer to command specific output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE_ADV_PAYLOAD -//! @{ -#define CMD_BLE_ADV_PAYLOAD 0x1001 -//! BLE Update Advertising Payload Command -struct __RFC_STRUCT rfc_CMD_BLE_ADV_PAYLOAD_s { - uint16_t commandNo; //!< The command ID number 0x1001 - uint8_t payloadType; //!< \brief 0: Advertising data
- //!< 1: Scan response data - uint8_t newLen; //!< Length of the new payload - uint8_t* pNewData; //!< Pointer to the buffer containing the new data - rfc_bleAdvPar_t *pParams; //!< Pointer to the parameter structure to update -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_RADIO_SETUP -//! @{ -#define CMD_BLE5_RADIO_SETUP 0x1820 -//! Bluetooth 5 Radio Setup Command for all PHYs -struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x1820 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t mainMode:2; //!< \brief PHY to use for non-BLE commands:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:1; //!< \brief Coding to use for TX if coded PHY is selected for non-BLE commands
- //!< 0: S = 8 (125 kbps)
- //!< 1: S = 2 (500 kbps) - } defaultPhy; - uint8_t loDivider; //!< LO divider setting to use. Supported values: 0 or 2. - struct { - uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode:1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Default transmit power - uint32_t* pRegOverrideCommon; //!< \brief Pointer to a list of hardware and configuration registers to override during common - //!< initialization. If NULL, no override is used. - uint32_t* pRegOverride1Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting - //!< 1 Mbps PHY mode. If NULL, no override is used. - uint32_t* pRegOverride2Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting - //!< 2 Mbps PHY mode. If NULL, no override is used. - uint32_t* pRegOverrideCoded; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting - //!< coded PHY mode. If NULL, no override is used. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_SLAVE -//! @{ -#define CMD_BLE5_SLAVE 0x1821 -//! Bluetooth 5 Slave Command -struct __RFC_STRUCT rfc_CMD_BLE5_SLAVE_s { - uint16_t commandNo; //!< The command ID number 0x1821 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_ble5SlavePar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_MASTER -//! @{ -#define CMD_BLE5_MASTER 0x1822 -//! Bluetooth 5 Master Command -struct __RFC_STRUCT rfc_CMD_BLE5_MASTER_s { - uint16_t commandNo; //!< The command ID number 0x1822 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_ble5MasterPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleMasterSlaveOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_ADV_EXT -//! @{ -#define CMD_BLE5_ADV_EXT 0x1823 -//! Bluetooth 5 Extended Advertiser Command -struct __RFC_STRUCT rfc_CMD_BLE5_ADV_EXT_s { - uint16_t commandNo; //!< The command ID number 0x1823 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_ble5AdvExtPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_ADV_AUX -//! @{ -#define CMD_BLE5_ADV_AUX 0x1824 -//! Bluetooth 5 Secondary Channel Advertiser Command -struct __RFC_STRUCT rfc_CMD_BLE5_ADV_AUX_s { - uint16_t commandNo; //!< The command ID number 0x1824 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_ble5AdvAuxPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_SCANNER -//! @{ -#define CMD_BLE5_SCANNER 0x1827 -//! Bluetooth 5 Scanner Command -struct __RFC_STRUCT rfc_CMD_BLE5_SCANNER_s { - uint16_t commandNo; //!< The command ID number 0x1827 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_ble5ScannerPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_INITIATOR -//! @{ -#define CMD_BLE5_INITIATOR 0x1828 -//! Bluetooth 5 Initiator Command -struct __RFC_STRUCT rfc_CMD_BLE5_INITIATOR_s { - uint16_t commandNo; //!< The command ID number 0x1828 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_ble5InitiatorPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_ble5ScanInitOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_GENERIC_RX -//! @{ -#define CMD_BLE5_GENERIC_RX 0x1829 -//! Bluetooth 5 Generic Receiver Command -struct __RFC_STRUCT rfc_CMD_BLE5_GENERIC_RX_s { - uint16_t commandNo; //!< The command ID number 0x1829 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_bleGenericRxPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleGenericRxOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_TX_TEST -//! @{ -#define CMD_BLE5_TX_TEST 0x182A -//! Bluetooth 5 PHY Test Transmitter Command -struct __RFC_STRUCT rfc_CMD_BLE5_TX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x182A - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_bleTxTestPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleTxTestOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_ADV -//! @{ -#define CMD_BLE5_ADV 0x182B -//! Bluetooth 5 Connectable Undirected Advertiser Command -struct __RFC_STRUCT rfc_CMD_BLE5_ADV_s { - uint16_t commandNo; //!< The command ID number 0x182B - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_ADV_DIR -//! @{ -#define CMD_BLE5_ADV_DIR 0x182C -//! Bluetooth 5 Connectable Directed Advertiser Command -struct __RFC_STRUCT rfc_CMD_BLE5_ADV_DIR_s { - uint16_t commandNo; //!< The command ID number 0x182C - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_ADV_NC -//! @{ -#define CMD_BLE5_ADV_NC 0x182D -//! Bluetooth 5 Non-Connectable Advertiser Command -struct __RFC_STRUCT rfc_CMD_BLE5_ADV_NC_s { - uint16_t commandNo; //!< The command ID number 0x182D - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_ADV_SCAN -//! @{ -#define CMD_BLE5_ADV_SCAN 0x182E -//! Bluetooth 5 Scannable Undirected Advertiser Command -struct __RFC_STRUCT rfc_CMD_BLE5_ADV_SCAN_s { - uint16_t commandNo; //!< The command ID number 0x182E - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to use
- //!< 0--39: BLE advertising/data channel index
- //!< 60--207: Custom frequency; (2300 + channel) MHz
- //!< 255: Use existing frequency
- //!< Others: Reserved - struct { - uint8_t init:7; //!< \brief If bOverride = 1 or custom frequency is used:
- //!< 0: Do not use whitening
- //!< Other value: Initialization for 7-bit LFSR whitener - uint8_t bOverride:1; //!< \brief 0: Use default whitening for BLE advertising/data channels
- //!< 1: Override whitening initialization with value of init - } whitening; - struct { - uint8_t mainMode:2; //!< \brief PHY to use:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:6; //!< \brief Coding to use for TX if coded PHY is selected. - //!< See the Technical Reference Manual for details. - } phyMode; - uint8_t rangeDelay; //!< Number of RAT ticks to add to the listening time after T_IFS - uint16_t txPower; //!< \brief Transmit power to use (overrides the one given in radio setup)
- //!< 0x0000: Use default TX power
- //!< 0xFFFF: 20-dBm PA only: Use TX power from tx20Power field (command - //!< structure that includes tx20Power must be used) - rfc_bleAdvPar_t *pParams; //!< Pointer to command specific parameter structure - rfc_bleAdvOutput_t *pOutput; //!< Pointer to command specific output structure - uint32_t tx20Power; //!< \brief If txPower = 0xFFFF:
- //!< If tx20Power < 0x10000000: Transmit power to use for the 20-dBm PA; - //!< overrides the one given in radio setup for the duration of the command.
- //!< If tx20Power >= 0x10000000: Pointer to PA change override structure - //!< as for CMD_CHANGE_PA ; permanently changes the PA and PA power set in radio setup.
- //!< For other values of txPower, this field is not accessed by the radio - //!< CPU and may be omitted from the structure. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BLE5_RADIO_SETUP_PA -//! @{ -//! Bluetooth 5 Radio Setup Command for all PHYs with PA Switching Fields -struct __RFC_STRUCT rfc_CMD_BLE5_RADIO_SETUP_PA_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t mainMode:2; //!< \brief PHY to use for non-BLE commands:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< 3: Reserved - uint8_t coding:1; //!< \brief Coding to use for TX if coded PHY is selected for non-BLE commands
- //!< 0: S = 8 (125 kbps)
- //!< 1: S = 2 (500 kbps) - } defaultPhy; - uint8_t loDivider; //!< LO divider setting to use. Supported values: 0 or 2. - struct { - uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode:1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Default transmit power - uint32_t* pRegOverrideCommon; //!< \brief Pointer to a list of hardware and configuration registers to override during common - //!< initialization. If NULL, no override is used. - uint32_t* pRegOverride1Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting - //!< 1 Mbps PHY mode. If NULL, no override is used. - uint32_t* pRegOverride2Mbps; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting - //!< 2 Mbps PHY mode. If NULL, no override is used. - uint32_t* pRegOverrideCoded; //!< \brief Pointer to a list of hardware and configuration registers to override when selecting - //!< coded PHY mode. If NULL, no override is used. - uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< standard PA. Used by RF driver only, not radio CPU. - uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< 20-dBm PA. Used by RF driver only, not radio CPU. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleMasterSlavePar -//! @{ -struct __RFC_STRUCT rfc_bleMasterSlavePar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct { - uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; //!< Sequence number status - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleSlavePar -//! @{ -//! Parameter structure for legacy slave (CMD_BLE_SLAVE) - -struct __RFC_STRUCT rfc_bleSlavePar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct { - uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; //!< Sequence number status - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first - //!< receive operation - uint16_t __dummy0; - uint8_t __dummy1; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< connection event as soon as allowed -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleMasterPar -//! @{ -//! Parameter structure for legacy master (CMD_BLE_MASTER) - -struct __RFC_STRUCT rfc_bleMasterPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct { - uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; //!< Sequence number status - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< connection event as soon as allowed -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleAdvPar -//! @{ -//! Parameter structure for legacy advertiser (CMD_BLE_ADV* and CMD_BLE5_ADV*) - -struct __RFC_STRUCT rfc_bleAdvPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct { - uint8_t advFilterPolicy:2; //!< \brief Advertiser filter policy
- //!< 0: Process scan and connect requests from all devices
- //!< 1: Process connect requests from all devices and only scan requests from - //!< devices that are in the white list
- //!< 2: Process scan requests from all devices and only connect requests from - //!< devices that are in the white list
- //!< 3: Process scan and connect requests only from devices in the white list - uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) - uint8_t peerAddrType:1; //!< Directed advertiser: The type of the peer address -- public (0) or random (1) - uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2
- //!< 1: Report support of Channel Selection Algorithm #2 - uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used - //!< 1: Filter on bPrivIgn always - uint8_t rpaMode:1; //!< \brief Resolvable private address mode
- //!< 0: Normal operation
- //!< 1: Use white list for a received RPA regardless of filter policy - } advConfig; - uint8_t advLen; //!< Size of advertiser data - uint8_t scanRspLen; //!< Size of scan response data - uint8_t* pAdvData; //!< Pointer to buffer containing ADV*_IND data - uint8_t* pScanRspData; //!< Pointer to buffer containing SCAN_RSP data - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< advConfig.deviceAddrType is inverted. - rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed - //!< advertiser). If least significant bit is 1, the address type given by - //!< advConfig.peerAddrType is inverted. - struct { - uint8_t scanRspEndType:1; //!< \brief Command status at end if SCAN_RSP was sent:
- //!< 0: End with BLE_DONE_OK and result True
- //!< 1: End with BLE_DONE_SCAN_RSP and result False - } behConfig; - uint8_t __dummy0; - uint8_t __dummy1; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the advertiser event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< advertiser event as soon as allowed -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleScannerPar -//! @{ -//! Parameter structure for legacy scanner (CMD_BLE_SCANNER) - -struct __RFC_STRUCT rfc_bleScannerPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct { - uint8_t scanFilterPolicy:1; //!< \brief Scanning filter policy regarding advertiser address
- //!< 0: Accept all advertisement packets
- //!< 1: Accept only advertisement packets from devices where the advertiser's address - //!< is in the white list - uint8_t bActiveScan:1; //!< \brief 0: Passive scan
- //!< 1: Active scan - uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) - uint8_t rpaFilterPolicy:1; //!< \brief Filter policy for initA for ADV_DIRECT_IND messages
- //!< 0: Accept only initA that matches own address
- //!< 1: Also accept all resolvable private addresses - uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU
- //!< 1: Automatically set ignore bit in white list - uint8_t bEndOnRpt:1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
- //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP - uint8_t rpaMode:1; //!< \brief Resolvable private address mode
- //!< 0: Normal operation
- //!< 1: Use white list for a received RPA regardless of filter policy - } scanConfig; - uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure - uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec - struct { - uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure - uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit - //!< not changed - uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not - //!< changed - } backoffPar; - uint8_t scanReqLen; //!< Size of scan request data - uint8_t* pScanReqData; //!< Pointer to buffer containing SCAN_REQ data - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< scanConfig.deviceAddrType is inverted. - rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list - uint16_t __dummy0; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_ENDED -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleInitiatorPar -//! @{ -//! Parameter structure for legacy initiator (CMD_BLE_INITIATOR) - -struct __RFC_STRUCT rfc_bleInitiatorPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct { - uint8_t bUseWhiteList:1; //!< \brief Initiator filter policy
- //!< 0: Use specific peer address
- //!< 1: Use white list - uint8_t bDynamicWinOffset:1; //!< \brief 0: No dynamic WinOffset insertion
- //!< 1: Use dynamic WinOffset insertion - uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) - uint8_t peerAddrType:1; //!< The type of the peer address -- public (0) or random (1) - uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2
- //!< 1: Report support of Channel Selection Algorithm #2 - } initConfig; - uint8_t __dummy0; - uint8_t connectReqLen; //!< Size of connect request data - uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_IND (CONNECT_REQ) - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< initConfig.deviceAddrType is inverted. - rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address. If least - //!< significant bit is 1, the address type given by initConfig.peerAddrType - //!< is inverted. - ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. - //!< Set to the calculated value if a connection is made and to the next possible connection - //!< time if not. - uint16_t __dummy1; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_ENDED -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleGenericRxPar -//! @{ -//! Parameter structure for generic Rx (CMD_BLE_GENERIC_RX and CMD_BLE5_GENERIC_RX) - -struct __RFC_STRUCT rfc_bleGenericRxPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue. May be NULL; if so, received packets are not stored - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - uint8_t bRepeat; //!< \brief 0: End operation after receiving a packet
- //!< 1: Restart receiver after receiving a packet - uint16_t __dummy0; - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Rx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< Rx operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleTxTestPar -//! @{ -//! Parameter structure for Tx test (CMD_BLE_TX_TEST and CMD_BLE5_TX_TEST) - -struct __RFC_STRUCT rfc_bleTxTestPar_s { - uint16_t numPackets; //!< \brief Number of packets to transmit
- //!< 0: Transmit unlimited number of packets - uint8_t payloadLength; //!< The number of payload bytes in each packet. - uint8_t packetType; //!< \brief The packet type to be used, encoded according to the Bluetooth 5.0 spec, Volume 6, Part F, - //!< Section 4.1.4 - ratmr_t period; //!< Number of radio timer cycles between the start of each packet - struct { - uint8_t bOverrideDefault:1; //!< \brief 0: Use default packet encoding
- //!< 1: Override packet contents - uint8_t bUsePrbs9:1; //!< \brief If bOverride is 1:
- //!< 0: No PRBS9 encoding of packet
- //!< 1: Use PRBS9 encoding of packet - uint8_t bUsePrbs15:1; //!< \brief If bOverride is 1:
- //!< 0: No PRBS15 encoding of packet
- //!< 1: Use PRBS15 encoding of packet - } config; - uint8_t byteVal; //!< If config.bOverride is 1, value of each byte to be sent - uint8_t __dummy0; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Test Tx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< Test Tx operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5SlavePar -//! @{ -//! Parameter structure for Bluetooth 5 slave (CMD_BLE5_SLAVE) - -struct __RFC_STRUCT rfc_ble5SlavePar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct { - uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; //!< Sequence number status - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that defines timeout of the first receive operation - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that defines timeout of the first - //!< receive operation - uint8_t maxRxPktLen; //!< Maximum packet length currently allowed for received packets on the connection - uint8_t maxLenLowRate; //!< Maximum packet length for which using S = 8 (125 kbps) is allowed when transmitting. 0: no limit. - uint8_t __dummy0; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< connection event as soon as allowed -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5MasterPar -//! @{ -//! Parameter structure for Bluetooth 5 master (CMD_BLE5_MASTER) - -struct __RFC_STRUCT rfc_ble5MasterPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - dataQueue_t* pTxQ; //!< Pointer to transmit queue - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct { - uint8_t lastRxSn:1; //!< The SN bit of the header of the last packet received with CRC OK - uint8_t lastTxSn:1; //!< The SN bit of the header of the last transmitted packet - uint8_t nextTxSn:1; //!< The SN bit of the header of the next packet to transmit - uint8_t bFirstPkt:1; //!< For slave: 0 if a packet has been transmitted on the connection, 1 otherwise - uint8_t bAutoEmpty:1; //!< 1 if the last transmitted packet was an auto-empty packet - uint8_t bLlCtrlTx:1; //!< 1 if the last transmitted packet was an LL control packet (LLID = 11) - uint8_t bLlCtrlAckRx:1; //!< 1 if the last received packet was the ACK of an LL control packet - uint8_t bLlCtrlAckPending:1; //!< 1 if the last successfully received packet was an LL control packet which has not yet been ACK'ed - } seqStat; //!< Sequence number status - uint8_t maxNack; //!< Maximum number of NACKs received before operation ends. 0: No limit - uint8_t maxPkt; //!< Maximum number of packets transmitted in the operation before it ends. 0: No limit - uint32_t accessAddress; //!< Access address used on the connection - uint8_t crcInit0; //!< CRC initialization value used on the connection -- least significant byte - uint8_t crcInit1; //!< CRC initialization value used on the connection -- middle byte - uint8_t crcInit2; //!< CRC initialization value used on the connection -- most significant byte - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the connection event as soon as allowed - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< connection event as soon as allowed - uint8_t maxRxPktLen; //!< Maximum packet length currently allowed for received packets on the connection - uint8_t maxLenLowRate; //!< Maximum packet length for which using S = 8 (125 kbps) is allowed when transmitting. 0: no limit. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5AdvExtPar -//! @{ -//! Parameter structure for extended advertiser (CMD_BLE5_ADV_EXT) - -struct __RFC_STRUCT rfc_ble5AdvExtPar_s { - struct { - uint8_t :2; - uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) - } advConfig; - uint8_t __dummy0; - uint8_t __dummy1; - uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types, - //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed - ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points - uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_EXT_IND packet - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< advConfig.deviceAddrType is inverted. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5AdvAuxPar -//! @{ -//! Parameter structure for secondary channel advertiser (CMD_BLE5_ADV_AUX) - -struct __RFC_STRUCT rfc_ble5AdvAuxPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct { - uint8_t advFilterPolicy:2; //!< \brief Advertiser filter policy
- //!< 0: Process scan and connect requests from all devices
- //!< 1: Process connect requests from all devices and only scan requests from - //!< devices that are in the white list
- //!< 2: Process scan requests from all devices and only connect requests from - //!< devices that are in the white list
- //!< 3: Process scan and connect requests only from devices in the white list - uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) - uint8_t targetAddrType:1; //!< Directed secondary advertiser: The type of the target address -- public (0) or random (1) - uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t bDirected:1; //!< \brief 0: Advertiser is undirected: pWhiteList points to a white list - //!< 1: Advertiser is directed: pWhiteList points to a single device address - uint8_t privIgnMode:1; //!< \brief 0: Filter on bPrivIgn only when white list is used - //!< 1: Filter on bPrivIgn always - uint8_t rpaMode:1; //!< \brief Resolvable private address mode
- //!< 0: Normal operation
- //!< 1: Use white list for a received RPA regardless of filter policy - } advConfig; - struct { - uint8_t scanRspEndType:1; //!< \brief Command status at end if AUX_SCAN_RSP was sent:
- //!< 0: End with BLE_DONE_OK and result True
- //!< 1: End with BLE_DONE_SCAN_RSP and result False - } behConfig; - uint8_t auxPtrTargetType; //!< \brief Number indicating reference for auxPtrTargetTime. Takes same values as trigger types, - //!< but only TRIG_ABSTIME and TRIG_REL_* are allowed - ratmr_t auxPtrTargetTime; //!< Time of start of packet to which auxPtr points - uint8_t* pAdvPkt; //!< Pointer to extended advertising packet for the ADV_AUX_IND packet - uint8_t* pRspPkt; //!< \brief Pointer to extended advertising packet for the AUX_SCAN_RSP or AUX_CONNECT_RSP packet - //!< (may be NULL if not applicable) - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< advConfig.deviceAddrType is inverted. - rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address (directed - //!< advertiser). If least significant bit is 1, the address type given by - //!< advConfig.peerAddrType is inverted. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5AuxChRes -//! @{ -struct __RFC_STRUCT rfc_ble5AuxChRes_s { - ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet - uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet - uint8_t channelNo; //!< The channel index used for secondary advertising - uint8_t phyMode; //!< \brief PHY to use on secondary channel:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< Others: Reserved -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5ScannerPar -//! @{ -//! Parameter structure for Bluetooth 5 scanner (CMD_BLE5_SCANNER) - -struct __RFC_STRUCT rfc_ble5ScannerPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct { - uint8_t scanFilterPolicy:1; //!< \brief Scanning filter policy regarding advertiser address
- //!< 0: Accept all advertisement packets
- //!< 1: Accept only advertisement packets from devices where the advertiser's address - //!< is in the White list. - uint8_t bActiveScan:1; //!< \brief 0: Passive scan
- //!< 1: Active scan - uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) - uint8_t rpaFilterPolicy:1; //!< \brief Filter policy for initA of ADV_DIRECT_IND messages
- //!< 0: Accept only initA that matches own address
- //!< 1: Also accept all resolvable private addresses - uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for legacy packets
- //!< 1: Automatically set ignore bit in white list for legacy packets - uint8_t bEndOnRpt:1; //!< \brief 0: Continue scanner operation after each reporting ADV*_IND or sending SCAN_RSP
- //!< 1: End scanner operation after each reported ADV*_IND and potentially SCAN_RSP - uint8_t rpaMode:1; //!< \brief Resolvable private address mode
- //!< 0: Normal operation
- //!< 1: Use white list for a received RPA regardless of filter policy - } scanConfig; - uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure - uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec - struct { - uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure - uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit - //!< not changed - uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not - //!< changed - } backoffPar; - struct { - uint8_t bCheckAdi:1; //!< \brief 0: Do not perform ADI filtering
- //!< 1: Perform ADI filtering on packets where ADI is present - uint8_t bAutoAdiUpdate:1; //!< \brief 0: Do not update ADI entries in radio CPU using legacy mode (recommended)
- //!< 1: Legacy mode: Automatically update ADI entry for received packets with - //!< AdvDataInfo after first occurrence - uint8_t bApplyDuplicateFiltering:1;//!< \brief 0: Do not apply duplicate filtering based on device address for extended - //!< advertiser packets (recommended)
- //!< 1: Apply duplicate filtering based on device address for extended advertiser - //!< packets with no ADI field - uint8_t bAutoWlIgnore:1; //!< \brief 0: Do not set ignore bit in white list from radio CPU for extended advertising packets
- //!< 1: Automatically set ignore bit in white list for extended advertising packets - uint8_t bAutoAdiProcess:1; //!< \brief 0: Do not use automatic ADI processing
- //!< 1: Automatically update ADI entry for received packets so that only the same - //!< ADI is accepted for the rest of the chain and the SID/DID combination is - //!< ignored after the entire chain is received. - uint8_t bExclusiveSid:1; //!< \brief 0: Set adiStatus.state to 0 when command starts so that all - //!< valid SIDs are accepted
- //!< 1: Do not modify adiStatus.state when command starts
- } extFilterConfig; - struct { - uint8_t lastAcceptedSid:4; //!< Indication of SID of last successfully received packet that was not ignored - uint8_t state:3; //!< \brief 0: No extended packet received, or last extended packet didn't have an ADI; - //!< lastAcceptedSid field is not valid
- //!< 1: A message with ADI has been received, but no chain is under reception; - //!< ADI filtering to be performed normally
- //!< 2: A message with SID as given in lastAcceptedSid has been - //!< received, and chained messages are still pending. Messages without this - //!< SID will be ignored
- //!< 3: An AUX_SCAN_RSP message has been received after receiving messages with SID - //!< as given in lastAcceptedSid, and chained messages are - //!< pending. Messages with an ADI field will be ignored.
- //!< 4: A message with no ADI has been received, and chained messages are still - //!< pending. Messages with an ADI field will be ignored.
- //!< Others: Reserved - } adiStatus; - uint8_t __dummy0; - uint16_t __dummy1; - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< scanConfig.deviceAddrType is inverted. - rfc_bleWhiteListEntry_t *pWhiteList; //!< Pointer to white list - rfc_ble5AdiEntry_t *pAdiList; //!< Pointer to advDataInfo list - uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time - //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX. - //!< If it is smaller, the radio will automatically switch to the correct channel and PHY. - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_ENDED - ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet - uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet - uint8_t channelNo; //!< The channel index used for secondary advertising - uint8_t phyMode; //!< \brief PHY to use on secondary channel:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< Others: Reserved -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5InitiatorPar -//! @{ -//! Parameter structure for Bluetooth 5 initiator (CMD_BLE5_INITIATOR) - -struct __RFC_STRUCT rfc_ble5InitiatorPar_s { - dataQueue_t* pRxQ; //!< Pointer to receive queue - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically remove ignored packets from Rx queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushEmpty:1; //!< If 1, automatically remove empty packets from Rx queue - uint8_t bIncludeLenByte:1; //!< If 1, include the received length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; //!< Configuration bits for the receive queue entries - struct { - uint8_t bUseWhiteList:1; //!< \brief Initiator filter policy
- //!< 0: Use specific peer address
- //!< 1: Use white list - uint8_t bDynamicWinOffset:1; //!< 1: Use dynamic WinOffset insertion - uint8_t deviceAddrType:1; //!< The type of the device address -- public (0) or random (1) - uint8_t peerAddrType:1; //!< The type of the peer address -- public (0) or random (1) - uint8_t bStrictLenFilter:1; //!< \brief 0: Accept any packet with a valid advertising packet length
- //!< 1: Discard messages with illegal length for the given packet type - uint8_t chSel:1; //!< \brief 0: Do not report support of Channel Selection Algorithm #2 in CONNECT_IND
- //!< 1: Report support of Channel Selection Algorithm #2 in CONNECT_IND - } initConfig; - uint16_t randomState; //!< State for pseudo-random number generation used in backoff procedure - uint16_t backoffCount; //!< Parameter backoffCount used in backoff procedure, cf. Bluetooth spec - struct { - uint8_t logUpperLimit:4; //!< Binary logarithm of parameter upperLimit used in scanner backoff procedure - uint8_t bLastSucceeded:1; //!< \brief 1 if the last SCAN_RSP was successfully received and upperLimit - //!< not changed - uint8_t bLastFailed:1; //!< \brief 1 if reception of the last SCAN_RSP failed and upperLimit was not - //!< changed - } backoffPar; - uint8_t connectReqLen; //!< Size of connect request data - uint8_t* pConnectReqData; //!< Pointer to buffer containing LLData to go in the CONNECT_IND or AUX_CONNECT_REQ packet - uint16_t* pDeviceAddress; //!< \brief Pointer (with least significant bit set to 0) to device address used for this device. - //!< If least significant bit is 1, the address type given by - //!< initConfig.deviceAddrType is inverted. - rfc_bleWhiteListEntry_t *pWhiteList; //!< \brief Pointer (with least significant bit set to 0) to white list or peer address. If least - //!< significant bit is 1, the address type given by initConfig.peerAddrType - //!< is inverted. - ratmr_t connectTime; //!< \brief Indication of timer value of the first possible start time of the first connection event. - //!< Set to the calculated value if a connection is made and to the next possible connection - //!< time if not. - uint16_t maxWaitTimeForAuxCh; //!< \brief Maximum wait time for switching to secondary scanning withing the command. If the time - //!< to the start of the event is greater than this, the command will end with BLE_DONE_AUX. - //!< If it is smaller, the radio will automatically switch to the correct channel and PHY. - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } timeoutTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to stop receiving as soon as allowed - ratmr_t timeoutTime; //!< \brief Time used together with timeoutTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_RXTIMEOUT - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to stop - //!< receiving as soon as allowed, ending with BLE_DONE_ENDED - ratmr_t rxStartTime; //!< The time needed to start RX in order to receive the packet - uint16_t rxListenTime; //!< The time needed to listen in order to receive the packet. 0: No AUX packet - uint8_t channelNo; //!< The channel index used for secondary advertising - uint8_t phyMode; //!< \brief PHY to use on secondary channel:
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded
- //!< Others: Reserved -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleMasterSlaveOutput -//! @{ -//! Output structure for master and slave (CMD_BLE_MASTER/CMD_BLE_SLAVE/CMD_BLE5_MASTER/CMD_BLE5_SLAVE) - -struct __RFC_STRUCT rfc_bleMasterSlaveOutput_s { - uint8_t nTx; //!< \brief Total number of packets (including auto-empty and retransmissions) that have been - //!< transmitted - uint8_t nTxAck; //!< Total number of transmitted packets (including auto-empty) that have been ACK'ed - uint8_t nTxCtrl; //!< Number of unique LL control packets from the Tx queue that have been transmitted - uint8_t nTxCtrlAck; //!< Number of LL control packets from the Tx queue that have been finished (ACK'ed) - uint8_t nTxCtrlAckAck; //!< \brief Number of LL control packets that have been ACK'ed and where an ACK has been sent in - //!< response - uint8_t nTxRetrans; //!< Number of retransmissions that has been done - uint8_t nTxEntryDone; //!< Number of packets from the Tx queue that have been finished (ACK'ed) - uint8_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored - uint8_t nRxCtrl; //!< Number of LL control packets that have been received with CRC OK and not ignored - uint8_t nRxCtrlAck; //!< \brief Number of LL control packets that have been received with CRC OK and not ignored, and - //!< then ACK'ed - uint8_t nRxNok; //!< Number of packets that have been received with CRC error - uint8_t nRxIgnored; //!< \brief Number of packets that have been received with CRC OK and ignored due to repeated - //!< sequence number - uint8_t nRxEmpty; //!< Number of packets that have been received with CRC OK and no payload - uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< RSSI of last received packet (signed) - struct { - uint8_t bTimeStampValid:1; //!< 1 if a valid time stamp has been written to timeStamp; 0 otherwise - uint8_t bLastCrcErr:1; //!< 1 if the last received packet had CRC error; 0 otherwise - uint8_t bLastIgnored:1; //!< 1 if the last received packet with CRC OK was ignored; 0 otherwise - uint8_t bLastEmpty:1; //!< 1 if the last received packet with CRC OK was empty; 0 otherwise - uint8_t bLastCtrl:1; //!< 1 if the last received packet with CRC OK was an LL control packet; 0 otherwise - uint8_t bLastMd:1; //!< 1 if the last received packet with CRC OK had MD = 1; 0 otherwise - uint8_t bLastAck:1; //!< \brief 1 if the last received packet with CRC OK was an ACK of a transmitted packet; - //!< 0 otherwise - } pktStatus; //!< Status of received packets - ratmr_t timeStamp; //!< Slave operation: Time stamp of first received packet -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleAdvOutput -//! @{ -//! Output structure for advertiser (CMD_BLE_ADV* and CMD_BLE5_ADV*) - -struct __RFC_STRUCT rfc_bleAdvOutput_s { - uint16_t nTxAdvInd; //!< Number of ADV*_IND packets completely transmitted - uint8_t nTxScanRsp; //!< Number of AUX_SCAN_RSP or SCAN_RSP packets transmitted - uint8_t nRxScanReq; //!< Number of AUX_SCAN_REQ or SCAN_REQ packets received OK and not ignored - uint8_t nRxConnectReq; //!< Number of AUX_CONNECT_REQ or CONNECT_IND (CONNECT_REQ) packets received OK and not ignored - uint8_t nTxConnectRsp; //!< Number of AUX_CONNECT_RSP packets transmitted - uint16_t nRxNok; //!< Number of packets received with CRC error - uint16_t nRxIgnored; //!< Number of packets received with CRC OK, but ignored - uint8_t nRxBufFull; //!< Number of packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet (signed) - ratmr_t timeStamp; //!< Time stamp of the last received packet -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleScannerOutput -//! @{ -//! Output structure for legacy scanner (CMD_BLE_SCANNER) - -struct __RFC_STRUCT rfc_bleScannerOutput_s { - uint16_t nTxScanReq; //!< Number of transmitted SCAN_REQ packets - uint16_t nBackedOffScanReq; //!< Number of SCAN_REQ packets not sent due to backoff procedure - uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored - uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored - uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error - uint16_t nRxScanRspOk; //!< Number of SCAN_RSP packets received with CRC OK and not ignored - uint16_t nRxScanRspIgnored; //!< Number of SCAN_RSP packets received with CRC OK, but ignored - uint16_t nRxScanRspNok; //!< Number of SCAN_RSP packets received with CRC error - uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue - uint8_t nRxScanRspBufFull; //!< Number of SCAN_RSP packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet (signed) - uint8_t __dummy0; - ratmr_t timeStamp; //!< Time stamp of the last successfully received ADV*_IND packet that was not ignored -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleInitiatorOutput -//! @{ -//! Output structure for legacy initiator (CMD_BLE_INITIATOR) - -struct __RFC_STRUCT rfc_bleInitiatorOutput_s { - uint8_t nTxConnectReq; //!< Number of transmitted CONNECT_IND (CONNECT_REQ) packets - uint8_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored - uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored - uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error - uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet (signed) - ratmr_t timeStamp; //!< Time stamp of the received ADV*_IND packet that caused transmission of CONNECT_IND (CONNECT_REQ) -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5ScanInitOutput -//! @{ -//! Output structure for BLE scanner and initiator (CMD_BLE5_SCANNER and CMD_BLE5_INITIATOR) - -struct __RFC_STRUCT rfc_ble5ScanInitOutput_s { - uint16_t nTxReq; //!< Number of transmitted AUX_SCAN_REQ, SCAN_REQ, AUX_CONNECT_REQ, or CONNECT_IND packets - uint16_t nBackedOffReq; //!< Number of AUX_SCAN_REQ, SCAN_REQ, or AUX_CONNECT_REQ packets not sent due to backoff procedure - uint16_t nRxAdvOk; //!< Number of ADV*_IND packets received with CRC OK and not ignored - uint16_t nRxAdvIgnored; //!< Number of ADV*_IND packets received with CRC OK, but ignored - uint16_t nRxAdvNok; //!< Number of ADV*_IND packets received with CRC error - uint16_t nRxRspOk; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC OK and not ignored - uint16_t nRxRspIgnored; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC OK, but ignored - uint16_t nRxRspNok; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received with CRC error - uint8_t nRxAdvBufFull; //!< Number of ADV*_IND packets received that did not fit in Rx queue - uint8_t nRxRspBufFull; //!< Number of AUX_SCAN_RSP, SCAN_RSP, or AUX_CONNECT_RSP packets received that did not fit in Rx queue - int8_t lastRssi; //!< The RSSI of the last received packet (signed) - uint8_t __dummy0; - ratmr_t timeStamp; //!< Time stamp of the last successfully received *ADV*_IND packet that was not ignored -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleGenericRxOutput -//! @{ -//! Output structure for generic Rx (CMD_BLE_GENERIC_RX and CMD_BLE5_GENERIC_RX) - -struct __RFC_STRUCT rfc_bleGenericRxOutput_s { - uint16_t nRxOk; //!< Number of packets received with CRC OK - uint16_t nRxNok; //!< Number of packets received with CRC error - uint16_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< The RSSI of the last received packet (signed) - uint8_t __dummy0; - ratmr_t timeStamp; //!< Time stamp of the last received packet -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleTxTestOutput -//! @{ -//! Output structure for Tx test (CMD_BLE_TX_TEST and CMD_BLE5_TX_TEST) - -struct __RFC_STRUCT rfc_bleTxTestOutput_s { - uint16_t nTx; //!< Number of packets transmitted -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5ExtAdvEntry -//! @{ -//! Common Extended Packet Entry Format - -struct __RFC_STRUCT rfc_ble5ExtAdvEntry_s { - struct { - uint8_t length:6; //!< Extended header length - uint8_t advMode:2; //!< \brief Advertiser mode as defined in BLE:
- //!< 0: Non-connectable, non-scannable
- //!< 1: Connectable, non-scannable
- //!< 2: Non-connectable, scannable
- //!< 3: Reserved - } extHdrInfo; - uint8_t extHdrFlags; //!< Extended header flags as defined in BLE - struct { - uint8_t bSkipAdvA:1; //!< \brief 0: AdvA is present in extended payload if configured in - //!< extHdrFlags
- //!< 1: AdvA is inserted automatically from command structure if configured in - //!< extHdrFlags and is omitted from extended header - uint8_t bSkipTargetA:1; //!< \brief 0: TargetA is present in extended payload if configured in - //!< extHdrFlags. For response messages, the value is replaced - //!< by the received address when sending
- //!< 1: TargetA is inserted automatically from command structure or received - //!< address if configured in extHdrFlags and is omitted from - //!< extended header. Not supported with CMD_BLE5_ADV_EXT. - uint8_t deviceAddrType:1; //!< \brief If bSkipAdvA = 0: The type of the device address in extended - //!< header buffer -- public (0) or random (1) - uint8_t targetAddrType:1; //!< \brief If bSkipAdvA = 0: The type of the target address in extended - //!< header buffer -- public (0) or random (1) - } extHdrConfig; - uint8_t advDataLen; //!< Size of payload buffer - uint8_t* pExtHeader; //!< \brief Pointer to buffer containing extended header. If no fields except extended - //!< header flags, automatic advertiser address, or automatic target address are - //!< present, pointer may be NULL. - uint8_t* pAdvData; //!< \brief Pointer to buffer containing advData. If advDataLen = 0, - //!< pointer may be NULL. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleWhiteListEntry -//! @{ -//! White list entry structure - -struct __RFC_STRUCT rfc_bleWhiteListEntry_s { - uint8_t size; //!< Number of while list entries. Used in the first entry of the list only - struct { - uint8_t bEnable:1; //!< 1 if the entry is in use, 0 if the entry is not in use - uint8_t addrType:1; //!< The type address in the entry -- public (0) or random (1) - uint8_t bWlIgn:1; //!< \brief 1 if the entry is to be ignored by a scanner if the AdvDataInfo - //!< field is not present, 0 otherwise. Used to mask out entries that - //!< have already been scanned and reported. - uint8_t :1; - uint8_t bPrivIgn:1; //!< \brief 1 if the entry is to be ignored as part of a privacy algorithm, - //!< 0 otherwise - } conf; - uint16_t address; //!< Least significant 16 bits of the address contained in the entry - uint32_t addressHi; //!< Most significant 32 bits of the address contained in the entry -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5AdiEntry -//! @{ -//! AdvDataInfo list entry structure - -struct __RFC_STRUCT rfc_ble5AdiEntry_s { - struct { - uint16_t advDataId:12; //!< \brief If bValid = 1: Last Advertising Data ID (DID) for the - //!< Advertising Set ID (SID) corresponding to the entry number in the array - uint16_t mode:2; //!< \brief 0: Entry is invalid (always receive packet with the given SID)
- //!< 1: Entry is valid (ignore packets with the given SID where DID equals - //!< advDataId)
- //!< 2: Entry is blocked (always ignore packet with the given SID)
- //!< 3: Reserved - } advDataInfo; -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup bleRxStatus -//! @{ -//! Receive status byte that may be appended to message in receive buffer for legacy commands - -struct __RFC_STRUCT rfc_bleRxStatus_s { - struct { - uint8_t channel:6; //!< \brief The channel on which the packet was received, provided channel is in the range - //!< 0--39; otherwise 0x3F - uint8_t bIgnore:1; //!< 1 if the packet is marked as ignored, 0 otherwise - uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise - } status; -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ble5RxStatus -//! @{ -//! Receive status field that may be appended to message in receive buffer for Bluetooth 5 commands - -struct __RFC_STRUCT rfc_ble5RxStatus_s { - struct { - uint16_t channel:6; //!< \brief The channel on which the packet was received, provided channel is in the range - //!< 0--39; otherwise 0x3F - uint16_t bIgnore:1; //!< 1 if the packet is marked as ignored, 0 otherwise - uint16_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise - uint16_t phyMode:2; //!< \brief The PHY on which the packet was received
- //!< 0: 1 Mbps
- //!< 1: 2 Mbps
- //!< 2: Coded, S = 8 (125 kbps)
- //!< 3: Coded, S = 2 (500 kbps) - } status; -} __RFC_STRUCT_ATTR; - -//! @} - -//! @} -//! @} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h deleted file mode 100644 index b43d0993dbe..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ble_mailbox.h +++ /dev/null @@ -1,76 +0,0 @@ -/****************************************************************************** -* Filename: rf_ble_mailbox.h -* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) -* Revision: 18171 -* -* Description: Definitions for BLE interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _BLE_MAILBOX_H -#define _BLE_MAILBOX_H - -/// \name Radio operation status -///@{ -/// \name Operation finished normally -///@{ -#define BLE_DONE_OK 0x1400 ///< Operation ended normally -#define BLE_DONE_RXTIMEOUT 0x1401 ///< Timeout of first Rx of slave operation or end of scan window -#define BLE_DONE_NOSYNC 0x1402 ///< Timeout of subsequent Rx -#define BLE_DONE_RXERR 0x1403 ///< Operation ended because of receive error (CRC or other) -#define BLE_DONE_CONNECT 0x1404 ///< CONNECT_IND or AUX_CONNECT_RSP received or transmitted -#define BLE_DONE_MAXNACK 0x1405 ///< Maximum number of retransmissions exceeded -#define BLE_DONE_ENDED 0x1406 ///< Operation stopped after end trigger -#define BLE_DONE_ABORT 0x1407 ///< Operation aborted by command -#define BLE_DONE_STOPPED 0x1408 ///< Operation stopped after stop command -#define BLE_DONE_AUX 0x1409 ///< Operation ended after following aux pointer pointing far ahead -#define BLE_DONE_CONNECT_CHSEL0 0x140A ///< CONNECT_IND received or transmitted; peer does not support channel selection algorithm #2 -#define BLE_DONE_SCAN_RSP 0x140B ///< SCAN_RSP or AUX_SCAN_RSP transmitted -///@} -/// \name Operation finished with error -///@{ -#define BLE_ERROR_PAR 0x1800 ///< Illegal parameter -#define BLE_ERROR_RXBUF 0x1801 ///< No available Rx buffer (Advertiser, Scanner, Initiator) -#define BLE_ERROR_NO_SETUP 0x1802 ///< Operation using Rx or Tx attempted when not in BLE mode -#define BLE_ERROR_NO_FS 0x1803 ///< Operation using Rx or Tx attempted without frequency synth configured -#define BLE_ERROR_SYNTH_PROG 0x1804 ///< Synthesizer programming failed to complete on time -#define BLE_ERROR_RXOVF 0x1805 ///< Receiver overflowed during operation -#define BLE_ERROR_TXUNF 0x1806 ///< Transmitter underflowed during operation -#define BLE_ERROR_AUX 0x1807 ///< Calculated AUX pointer was too far into the future or in the past -///@} -///@} - - -/// Special trigger for BLE slave command -#define BLE_TRIG_REL_SYNC 15 - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h deleted file mode 100644 index b479f88836b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_common_cmd.h +++ /dev/null @@ -1,1089 +0,0 @@ -/****************************************************************************** -* Filename: rf_common_cmd.h -* Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018) -* Revision: 18756 -* -* Description: CC13x2/CC26x2 API for common/generic commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __COMMON_CMD_H -#define __COMMON_CMD_H - -#ifndef __RFC_STRUCT -#define __RFC_STRUCT -#endif - -#ifndef __RFC_STRUCT_ATTR -#if defined(__GNUC__) -#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) -#elif defined(__TI_ARM__) -#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) -#else -#define __RFC_STRUCT_ATTR -#endif -#endif - -//! \addtogroup rfc -//! @{ - -//! \addtogroup common_cmd -//! @{ - -#include -#include "rf_mailbox.h" - -typedef struct __RFC_STRUCT rfc_command_s rfc_command_t; -typedef struct __RFC_STRUCT rfc_radioOp_s rfc_radioOp_t; -typedef struct __RFC_STRUCT rfc_CMD_NOP_s rfc_CMD_NOP_t; -typedef struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s rfc_CMD_RADIO_SETUP_t; -typedef struct __RFC_STRUCT rfc_CMD_FS_s rfc_CMD_FS_t; -typedef struct __RFC_STRUCT rfc_CMD_FS_OFF_s rfc_CMD_FS_OFF_t; -typedef struct __RFC_STRUCT rfc_CMD_RX_TEST_s rfc_CMD_RX_TEST_t; -typedef struct __RFC_STRUCT rfc_CMD_TX_TEST_s rfc_CMD_TX_TEST_t; -typedef struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s rfc_CMD_SYNC_STOP_RAT_t; -typedef struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s rfc_CMD_SYNC_START_RAT_t; -typedef struct __RFC_STRUCT rfc_CMD_RESYNC_RAT_s rfc_CMD_RESYNC_RAT_t; -typedef struct __RFC_STRUCT rfc_CMD_COUNT_s rfc_CMD_COUNT_t; -typedef struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s rfc_CMD_FS_POWERUP_t; -typedef struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s rfc_CMD_FS_POWERDOWN_t; -typedef struct __RFC_STRUCT rfc_CMD_SCH_IMM_s rfc_CMD_SCH_IMM_t; -typedef struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s rfc_CMD_COUNT_BRANCH_t; -typedef struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s rfc_CMD_PATTERN_CHECK_t; -typedef struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_PA_s rfc_CMD_RADIO_SETUP_PA_t; -typedef struct __RFC_STRUCT rfc_CMD_ABORT_s rfc_CMD_ABORT_t; -typedef struct __RFC_STRUCT rfc_CMD_STOP_s rfc_CMD_STOP_t; -typedef struct __RFC_STRUCT rfc_CMD_GET_RSSI_s rfc_CMD_GET_RSSI_t; -typedef struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s rfc_CMD_UPDATE_RADIO_SETUP_t; -typedef struct __RFC_STRUCT rfc_CMD_TRIGGER_s rfc_CMD_TRIGGER_t; -typedef struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s rfc_CMD_GET_FW_INFO_t; -typedef struct __RFC_STRUCT rfc_CMD_START_RAT_s rfc_CMD_START_RAT_t; -typedef struct __RFC_STRUCT rfc_CMD_PING_s rfc_CMD_PING_t; -typedef struct __RFC_STRUCT rfc_CMD_READ_RFREG_s rfc_CMD_READ_RFREG_t; -typedef struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s rfc_CMD_ADD_DATA_ENTRY_t; -typedef struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s rfc_CMD_REMOVE_DATA_ENTRY_t; -typedef struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s rfc_CMD_FLUSH_QUEUE_t; -typedef struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s rfc_CMD_CLEAR_RX_t; -typedef struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s rfc_CMD_REMOVE_PENDING_ENTRIES_t; -typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s rfc_CMD_SET_RAT_CMP_t; -typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s rfc_CMD_SET_RAT_CPT_t; -typedef struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s rfc_CMD_DISABLE_RAT_CH_t; -typedef struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s rfc_CMD_SET_RAT_OUTPUT_t; -typedef struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s rfc_CMD_ARM_RAT_CH_t; -typedef struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s rfc_CMD_DISARM_RAT_CH_t; -typedef struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s rfc_CMD_SET_TX_POWER_t; -typedef struct __RFC_STRUCT rfc_CMD_SET_TX20_POWER_s rfc_CMD_SET_TX20_POWER_t; -typedef struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s rfc_CMD_CHANGE_PA_t; -typedef struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s rfc_CMD_UPDATE_HPOSC_FREQ_t; -typedef struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s rfc_CMD_UPDATE_FS_t; -typedef struct __RFC_STRUCT rfc_CMD_MODIFY_FS_s rfc_CMD_MODIFY_FS_t; -typedef struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s rfc_CMD_BUS_REQUEST_t; -typedef struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s rfc_CMD_SET_CMD_START_IRQ_t; - -//! \addtogroup command -//! @{ -struct __RFC_STRUCT rfc_command_s { - uint16_t commandNo; //!< The command ID number -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup radioOp -//! @{ -//! Common definition for radio operation commands - -struct __RFC_STRUCT rfc_radioOp_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_NOP -//! @{ -#define CMD_NOP 0x0801 -//! No Operation Command -struct __RFC_STRUCT rfc_CMD_NOP_s { - uint16_t commandNo; //!< The command ID number 0x0801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_RADIO_SETUP -//! @{ -#define CMD_RADIO_SETUP 0x0802 -//! Radio Setup Command for Pre-Defined Schemes -struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x0802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t mode; //!< \brief The main mode to use
- //!< 0x00: BLE
- //!< 0x01: IEEE 802.15.4
- //!< 0x02: 2 Mbps GFSK
- //!< 0x05: 5 Mbps coded 8-FSK
- //!< 0xFF: Keep existing mode; update overrides only
- //!< Others: Reserved - uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0, 2, 4, - //!< 5, 6, 10, 12, 15, and 30. - struct { - uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode:1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_FS -//! @{ -#define CMD_FS 0x0803 -//! Frequency Synthesizer Programming Command -struct __RFC_STRUCT rfc_CMD_FS_s { - uint16_t commandNo; //!< The command ID number 0x0803 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t frequency; //!< The frequency in MHz to tune to - uint16_t fractFreq; //!< Fractional part of the frequency to tune to - struct { - uint8_t bTxMode:1; //!< \brief 0: Start synth in RX mode
- //!< 1: Start synth in TX mode - uint8_t refFreq:6; //!< \brief 0: Use default reference frequency
- //!< Others: Use reference frequency 48 MHz/refFreq - } synthConf; - uint8_t __dummy0; //!< Reserved, always write 0 - uint8_t __dummy1; //!< Reserved - uint8_t __dummy2; //!< Reserved - uint16_t __dummy3; //!< Reserved -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_FS_OFF -//! @{ -#define CMD_FS_OFF 0x0804 -//! Command for Turning off Frequency Synthesizer -struct __RFC_STRUCT rfc_CMD_FS_OFF_s { - uint16_t commandNo; //!< The command ID number 0x0804 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_RX_TEST -//! @{ -#define CMD_RX_TEST 0x0807 -//! Receiver Test Command -struct __RFC_STRUCT rfc_CMD_RX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x0807 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t bEnaFifo:1; //!< \brief 0: Do not enable FIFO in modem, so that received data is not available
- //!< 1: Enable FIFO in modem -- the data must be read out by the application - uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bNoSync:1; //!< \brief 0: Run sync search as normal for the configured mode
- //!< 1: Write correlation thresholds to the maximum value to avoid getting sync - } config; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - uint32_t syncWord; //!< Sync word to use for receiver - ratmr_t endTime; //!< Time to end the operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_TX_TEST -//! @{ -#define CMD_TX_TEST 0x0808 -//! Transmitter Test Command -struct __RFC_STRUCT rfc_CMD_TX_TEST_s { - uint16_t commandNo; //!< The command ID number 0x0808 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t bUseCw:1; //!< \brief 0: Send modulated signal
- //!< 1: Send continuous wave - uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t whitenMode:2; //!< \brief 0: No whitening
- //!< 1: Default whitening
- //!< 2: PRBS-15
- //!< 3: PRBS-32 - } config; - uint8_t __dummy0; - uint16_t txWord; //!< Value to send to the modem before whitening - uint8_t __dummy1; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - uint32_t syncWord; //!< Sync word to use for transmitter - ratmr_t endTime; //!< Time to end the operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_SYNC_STOP_RAT -//! @{ -#define CMD_SYNC_STOP_RAT 0x0809 -//! Synchronize and Stop Radio Timer Command -struct __RFC_STRUCT rfc_CMD_SYNC_STOP_RAT_s { - uint16_t commandNo; //!< The command ID number 0x0809 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - ratmr_t rat0; //!< \brief The returned RAT timer value corresponding to the value the RAT would have had when the - //!< RTC was zero -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_SYNC_START_RAT -//! @{ -#define CMD_SYNC_START_RAT 0x080A -//! Synchrously Start Radio Timer Command -struct __RFC_STRUCT rfc_CMD_SYNC_START_RAT_s { - uint16_t commandNo; //!< The command ID number 0x080A - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the - //!< RTC was zero. This parameter is returned by CMD_SYNC_STOP_RAT -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_RESYNC_RAT -//! @{ -#define CMD_RESYNC_RAT 0x0816 -//! Re-calculate rat0 value while RAT is running -struct __RFC_STRUCT rfc_CMD_RESYNC_RAT_s { - uint16_t commandNo; //!< The command ID number 0x0816 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - ratmr_t rat0; //!< \brief The desired RAT timer value corresponding to the value the RAT would have had when the - //!< RTC was zero -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_COUNT -//! @{ -#define CMD_COUNT 0x080B -//! Counter Command -struct __RFC_STRUCT rfc_CMD_COUNT_s { - uint16_t commandNo; //!< The command ID number 0x080B - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation - //!< differs if the result is zero -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_FS_POWERUP -//! @{ -#define CMD_FS_POWERUP 0x080C -//! Power up Frequency Syntheszier Command -struct __RFC_STRUCT rfc_CMD_FS_POWERUP_s { - uint16_t commandNo; //!< The command ID number 0x080C - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override. If NULL, no override is used. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_FS_POWERDOWN -//! @{ -#define CMD_FS_POWERDOWN 0x080D -//! Power down Frequency Syntheszier Command -struct __RFC_STRUCT rfc_CMD_FS_POWERDOWN_s { - uint16_t commandNo; //!< The command ID number 0x080D - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_SCH_IMM -//! @{ -#define CMD_SCH_IMM 0x0810 -//! Run Immidiate Command as Radio Operation Command -struct __RFC_STRUCT rfc_CMD_SCH_IMM_s { - uint16_t commandNo; //!< The command ID number 0x0810 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t __dummy0; - uint32_t cmdrVal; //!< Value as would be written to CMDR - uint32_t cmdstaVal; //!< Value as would be returned in CMDSTA -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_COUNT_BRANCH -//! @{ -#define CMD_COUNT_BRANCH 0x0812 -//! Counter Command with Branch of Command Chain -struct __RFC_STRUCT rfc_CMD_COUNT_BRANCH_s { - uint16_t commandNo; //!< The command ID number 0x0812 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t counter; //!< \brief Counter. On start, the radio CPU decrements the value, and the end status of the operation - //!< differs if the result is zero - rfc_radioOp_t *pNextOpIfOk; //!< Pointer to next operation if counter did not expire -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PATTERN_CHECK -//! @{ -#define CMD_PATTERN_CHECK 0x0813 -//! Command for Checking a Value in Memory aginst a Pattern -struct __RFC_STRUCT rfc_CMD_PATTERN_CHECK_s { - uint16_t commandNo; //!< The command ID number 0x0813 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint16_t operation:2; //!< \brief Operation to perform
- //!< 0: True if value == compareVal
- //!< 1: True if value < compareVal
- //!< 2: True if value > compareVal
- //!< 3: Reserved - uint16_t bByteRev:1; //!< \brief If 1, interchange the four bytes of the value, so that they are read - //!< most-significant-byte-first. - uint16_t bBitRev:1; //!< If 1, perform bit reversal of the value - uint16_t signExtend:5; //!< \brief 0: Treat value and compareVal as unsigned
- //!< 1--31: Treat value and compareVal as signed, where the value - //!< gives the number of the most significant bit in the signed number. - uint16_t bRxVal:1; //!< \brief 0: Use pValue as a pointer
- //!< 1: Use pValue as a signed offset to the start of the last - //!< committed RX entry element - } patternOpt; //!< Options for comparison - rfc_radioOp_t *pNextOpIfOk; //!< Pointer to next operation if comparison result was true - uint8_t* pValue; //!< Pointer to read from, or offset from last RX entry if patternOpt.bRxVal == 1 - uint32_t mask; //!< Bit mask to apply before comparison - uint32_t compareVal; //!< Value to compare to -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_RADIO_SETUP_PA -//! @{ -//! Radio Setup Command for Pre-Defined Schemes with PA Switching Fields -struct __RFC_STRUCT rfc_CMD_RADIO_SETUP_PA_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t mode; //!< \brief The main mode to use
- //!< 0x00: BLE
- //!< 0x01: IEEE 802.15.4
- //!< 0x02: 2 Mbps GFSK
- //!< 0x05: 5 Mbps coded 8-FSK
- //!< 0xFF: Keep existing mode; update overrides only
- //!< Others: Reserved - uint8_t loDivider; //!< \brief LO divider setting to use. Supported values: 0, 2, 4, - //!< 5, 6, 10, 12, 15, and 30. - struct { - uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode:1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. - uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< standard PA. Used by RF driver only, not radio CPU. - uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< 20-dBm PA. Used by RF driver only, not radio CPU. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_ABORT -//! @{ -#define CMD_ABORT 0x0401 -//! Abort Running Radio Operation Command -struct __RFC_STRUCT rfc_CMD_ABORT_s { - uint16_t commandNo; //!< The command ID number 0x0401 -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_STOP -//! @{ -#define CMD_STOP 0x0402 -//! Stop Running Radio Operation Command Gracefully -struct __RFC_STRUCT rfc_CMD_STOP_s { - uint16_t commandNo; //!< The command ID number 0x0402 -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_GET_RSSI -//! @{ -#define CMD_GET_RSSI 0x0403 -//! Read RSSI Command -struct __RFC_STRUCT rfc_CMD_GET_RSSI_s { - uint16_t commandNo; //!< The command ID number 0x0403 -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_UPDATE_RADIO_SETUP -//! @{ -#define CMD_UPDATE_RADIO_SETUP 0x0001 -//! Update Radio Settings Command -struct __RFC_STRUCT rfc_CMD_UPDATE_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x0001 - uint16_t __dummy0; - uint32_t* pRegOverride; //!< Pointer to a list of hardware and configuration registers to override -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_TRIGGER -//! @{ -#define CMD_TRIGGER 0x0404 -//! Generate Command Trigger -struct __RFC_STRUCT rfc_CMD_TRIGGER_s { - uint16_t commandNo; //!< The command ID number 0x0404 - uint8_t triggerNo; //!< Command trigger number -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_GET_FW_INFO -//! @{ -#define CMD_GET_FW_INFO 0x0002 -//! Request Information on the RF Core ROM Firmware -struct __RFC_STRUCT rfc_CMD_GET_FW_INFO_s { - uint16_t commandNo; //!< The command ID number 0x0002 - uint16_t versionNo; //!< Firmware version number - uint16_t startOffset; //!< The start of free RAM - uint16_t freeRamSz; //!< The size of free RAM - uint16_t availRatCh; //!< Bitmap of available RAT channels -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_START_RAT -//! @{ -#define CMD_START_RAT 0x0405 -//! Asynchronously Start Radio Timer Command -struct __RFC_STRUCT rfc_CMD_START_RAT_s { - uint16_t commandNo; //!< The command ID number 0x0405 -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PING -//! @{ -#define CMD_PING 0x0406 -//! Respond with Command ACK Only -struct __RFC_STRUCT rfc_CMD_PING_s { - uint16_t commandNo; //!< The command ID number 0x0406 -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_READ_RFREG -//! @{ -#define CMD_READ_RFREG 0x0601 -//! Read RF Core Hardware Register -struct __RFC_STRUCT rfc_CMD_READ_RFREG_s { - uint16_t commandNo; //!< The command ID number 0x0601 - uint16_t address; //!< The offset from the start of the RF core HW register bank (0x40040000) - uint32_t value; //!< Returned value of the register -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_ADD_DATA_ENTRY -//! @{ -#define CMD_ADD_DATA_ENTRY 0x0005 -//! Add Data Entry to Queue -struct __RFC_STRUCT rfc_CMD_ADD_DATA_ENTRY_s { - uint16_t commandNo; //!< The command ID number 0x0005 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to which the entry will be added - uint8_t* pEntry; //!< Pointer to the entry -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_REMOVE_DATA_ENTRY -//! @{ -#define CMD_REMOVE_DATA_ENTRY 0x0006 -//! Remove First Data Entry from Queue -struct __RFC_STRUCT rfc_CMD_REMOVE_DATA_ENTRY_s { - uint16_t commandNo; //!< The command ID number 0x0006 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure from which the entry will be removed - uint8_t* pEntry; //!< Pointer to the entry that was removed -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_FLUSH_QUEUE -//! @{ -#define CMD_FLUSH_QUEUE 0x0007 -//! Flush Data Queue -struct __RFC_STRUCT rfc_CMD_FLUSH_QUEUE_s { - uint16_t commandNo; //!< The command ID number 0x0007 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed - uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_CLEAR_RX -//! @{ -#define CMD_CLEAR_RX 0x0008 -//! Clear all RX Queue Entries -struct __RFC_STRUCT rfc_CMD_CLEAR_RX_s { - uint16_t commandNo; //!< The command ID number 0x0008 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to be cleared -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_REMOVE_PENDING_ENTRIES -//! @{ -#define CMD_REMOVE_PENDING_ENTRIES 0x0009 -//! Remove Pending Entries from Queue -struct __RFC_STRUCT rfc_CMD_REMOVE_PENDING_ENTRIES_s { - uint16_t commandNo; //!< The command ID number 0x0009 - uint16_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to the queue structure to be flushed - uint8_t* pFirstEntry; //!< Pointer to the first entry that was removed -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_SET_RAT_CMP -//! @{ -#define CMD_SET_RAT_CMP 0x000A -//! Set Radio Timer Channel in Compare Mode -struct __RFC_STRUCT rfc_CMD_SET_RAT_CMP_s { - uint16_t commandNo; //!< The command ID number 0x000A - uint8_t ratCh; //!< The radio timer channel number - uint8_t __dummy0; - ratmr_t compareTime; //!< The time at which the compare occurs -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_SET_RAT_CPT -//! @{ -#define CMD_SET_RAT_CPT 0x0603 -//! Set Radio Timer Channel in Capture Mode -struct __RFC_STRUCT rfc_CMD_SET_RAT_CPT_s { - uint16_t commandNo; //!< The command ID number 0x0603 - struct { - uint16_t :3; - uint16_t inputSrc:5; //!< Input source indicator - uint16_t ratCh:4; //!< The radio timer channel number - uint16_t bRepeated:1; //!< \brief 0: Single capture mode
- //!< 1: Repeated capture mode - uint16_t inputMode:2; //!< \brief Input mode:
- //!< 0: Capture on rising edge
- //!< 1: Capture on falling edge
- //!< 2: Capture on both edges
- //!< 3: Reserved - } config; -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_DISABLE_RAT_CH -//! @{ -#define CMD_DISABLE_RAT_CH 0x0408 -//! Disable Radio Timer Channel -struct __RFC_STRUCT rfc_CMD_DISABLE_RAT_CH_s { - uint16_t commandNo; //!< The command ID number 0x0408 - uint8_t ratCh; //!< The radio timer channel number -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_SET_RAT_OUTPUT -//! @{ -#define CMD_SET_RAT_OUTPUT 0x0604 -//! Set Radio Timer Output to a Specified Mode -struct __RFC_STRUCT rfc_CMD_SET_RAT_OUTPUT_s { - uint16_t commandNo; //!< The command ID number 0x0604 - struct { - uint16_t :2; - uint16_t outputSel:3; //!< Output event indicator - uint16_t outputMode:3; //!< \brief 0: Set output line low as default; and pulse on event. Duration of pulse is one RF Core clock period (ca. 41.67 ns).
- //!< 1: Set output line high on event
- //!< 2: Set output line low on event
- //!< 3: Toggle (invert) output line state on event
- //!< 4: Immediately set output line to low (does not change upon event)
- //!< 5: Immediately set output line to high (does not change upon event)
- //!< Others: Reserved - uint16_t ratCh:4; //!< The radio timer channel number - } config; -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_ARM_RAT_CH -//! @{ -#define CMD_ARM_RAT_CH 0x0409 -//! Arm Radio Timer Channel -struct __RFC_STRUCT rfc_CMD_ARM_RAT_CH_s { - uint16_t commandNo; //!< The command ID number 0x0409 - uint8_t ratCh; //!< The radio timer channel number -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_DISARM_RAT_CH -//! @{ -#define CMD_DISARM_RAT_CH 0x040A -//! Disarm Radio Timer Channel -struct __RFC_STRUCT rfc_CMD_DISARM_RAT_CH_s { - uint16_t commandNo; //!< The command ID number 0x040A - uint8_t ratCh; //!< The radio timer channel number -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_SET_TX_POWER -//! @{ -#define CMD_SET_TX_POWER 0x0010 -//! Set Transmit Power -struct __RFC_STRUCT rfc_CMD_SET_TX_POWER_s { - uint16_t commandNo; //!< The command ID number 0x0010 - uint16_t txPower; //!< New TX power setting -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_SET_TX20_POWER -//! @{ -#define CMD_SET_TX20_POWER 0x0014 -//! Set Transmit Power for 20-dBm PA -struct __RFC_STRUCT rfc_CMD_SET_TX20_POWER_s { - uint16_t commandNo; //!< The command ID number 0x0014 - uint16_t __dummy0; - uint32_t tx20Power; //!< New TX power setting -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_CHANGE_PA -//! @{ -#define CMD_CHANGE_PA 0x0015 -//! Set TX power with possibility to switch between PAs -struct __RFC_STRUCT rfc_CMD_CHANGE_PA_s { - uint16_t commandNo; //!< The command ID number 0x0015 - uint16_t __dummy0; - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override as part of the - //!< change, including new TX power -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_UPDATE_HPOSC_FREQ -//! @{ -#define CMD_UPDATE_HPOSC_FREQ 0x0608 -//! Set New Frequency Offset for HPOSC -struct __RFC_STRUCT rfc_CMD_UPDATE_HPOSC_FREQ_s { - uint16_t commandNo; //!< The command ID number 0x0608 - int16_t freqOffset; //!< Relative frequency offset, signed, scaled by 2-22 -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_UPDATE_FS -//! @{ -#define CMD_UPDATE_FS 0x0011 -//! Set New Synthesizer Frequency without Recalibration (Deprecated; use CMD_MODIFY_FS) -struct __RFC_STRUCT rfc_CMD_UPDATE_FS_s { - uint16_t commandNo; //!< The command ID number 0x0011 - uint16_t __dummy0; - uint32_t __dummy1; - uint32_t __dummy2; - uint16_t __dummy3; - uint16_t frequency; //!< The frequency in MHz to tune to - uint16_t fractFreq; //!< Fractional part of the frequency to tune to -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_MODIFY_FS -//! @{ -#define CMD_MODIFY_FS 0x0013 -//! Set New Synthesizer Frequency without Recalibration -struct __RFC_STRUCT rfc_CMD_MODIFY_FS_s { - uint16_t commandNo; //!< The command ID number 0x0013 - uint16_t frequency; //!< The frequency in MHz to tune to - uint16_t fractFreq; //!< Fractional part of the frequency to tune to -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_BUS_REQUEST -//! @{ -#define CMD_BUS_REQUEST 0x040E -//! Request System Bus to be Availbale -struct __RFC_STRUCT rfc_CMD_BUS_REQUEST_s { - uint16_t commandNo; //!< The command ID number 0x040E - uint8_t bSysBusNeeded; //!< \brief 0: System bus may sleep
- //!< 1: System bus access needed -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_SET_CMD_START_IRQ -//! @{ -#define CMD_SET_CMD_START_IRQ 0x0411 -//! Enable or disable generation of IRQ when a radio operation command starts -struct __RFC_STRUCT rfc_CMD_SET_CMD_START_IRQ_s { - uint16_t commandNo; //!< The command ID number 0x0411 - uint8_t bEna; //!< 1 to enable interrupt generation; 0 to disable it -} __RFC_STRUCT_ATTR; - -//! @} - -//! @} -//! @} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h deleted file mode 100644 index c79465c4f54..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_data_entry.h +++ /dev/null @@ -1,219 +0,0 @@ -/****************************************************************************** -* Filename: rf_data_entry.h -* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) -* Revision: 18170 -* -* Description: Definition of API for data exchange -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __DATA_ENTRY_H -#define __DATA_ENTRY_H - -#ifndef __RFC_STRUCT -#define __RFC_STRUCT -#endif - -#ifndef __RFC_STRUCT_ATTR -#if defined(__GNUC__) -#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) -#elif defined(__TI_ARM__) -#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) -#else -#define __RFC_STRUCT_ATTR -#endif -#endif - -//! \addtogroup rfc -//! @{ - -//! \addtogroup data_entry -//! @{ - -#include -#include "rf_mailbox.h" - -typedef struct __RFC_STRUCT rfc_dataEntry_s rfc_dataEntry_t; -typedef struct __RFC_STRUCT rfc_dataEntryGeneral_s rfc_dataEntryGeneral_t; -typedef struct __RFC_STRUCT rfc_dataEntryMulti_s rfc_dataEntryMulti_t; -typedef struct __RFC_STRUCT rfc_dataEntryPointer_s rfc_dataEntryPointer_t; -typedef struct __RFC_STRUCT rfc_dataEntryPartial_s rfc_dataEntryPartial_t; - -//! \addtogroup dataEntry -//! @{ -struct __RFC_STRUCT rfc_dataEntry_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct { - uint8_t type:2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup dataEntryGeneral -//! @{ -//! General data entry structure (type = 0) - -struct __RFC_STRUCT rfc_dataEntryGeneral_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct { - uint8_t type:2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - uint8_t data; //!< First byte of the data array to be received or transmitted -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup dataEntryMulti -//! @{ -//! Multi-element data entry structure (type = 1) - -struct __RFC_STRUCT rfc_dataEntryMulti_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct { - uint8_t type:2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - uint16_t numElements; //!< Number of entry elements committed in the entry - uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU - uint8_t rxData; //!< First byte of the data array of received data entry elements -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup dataEntryPointer -//! @{ -//! Pointer data entry structure (type = 2) - -struct __RFC_STRUCT rfc_dataEntryPointer_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct { - uint8_t type:2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - uint8_t* pData; //!< Pointer to data buffer of data to be received ro transmitted -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup dataEntryPartial -//! @{ -//! Partial read data entry structure (type = 3) - -struct __RFC_STRUCT rfc_dataEntryPartial_s { - uint8_t* pNextEntry; //!< Pointer to next entry in the queue, NULL if this is the last entry - uint8_t status; //!< Indicates status of entry, including whether it is free for the system CPU to write to - struct { - uint8_t type:2; //!< \brief Type of data entry structure
- //!< 0: General data entry
- //!< 1: Multi-element Rx entry
- //!< 2: Pointer entry
- //!< 3: Partial read Rx entry - uint8_t lenSz:2; //!< \brief Size of length word in start of each Rx entry element
- //!< 0: No length indicator
- //!< 1: One byte length indicator
- //!< 2: Two bytes length indicator
- //!< 3: Reserved - uint8_t irqIntv:4; //!< \brief For partial read Rx entry only: The number of bytes between interrupt generated - //!< by the radio CPU (0: 16 bytes) - } config; - uint16_t length; //!< \brief For pointer entries: Number of bytes in the data buffer pointed to
- //!< For other entries: Number of bytes following this length field - struct { - uint16_t numElements:13; //!< Number of entry elements committed in the entry - uint16_t bEntryOpen:1; //!< 1 if the entry contains an element that is still open for appending data - uint16_t bFirstCont:1; //!< 1 if the first element is a continuation of the last packet from the previous entry - uint16_t bLastCont:1; //!< 1 if the packet in the last element continues in the next entry - } pktStatus; - uint16_t nextIndex; //!< Index to the byte after the last byte of the last entry element committed by the radio CPU - uint8_t rxData; //!< First byte of the data array of received data entry elements -} __RFC_STRUCT_ATTR; - -//! @} - -//! @} -//! @} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h deleted file mode 100644 index e681acc04ee..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_cmd.h +++ /dev/null @@ -1,210 +0,0 @@ -/****************************************************************************** -* Filename: rf_hs_cmd.h -* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) -* Revision: 18170 -* -* Description: CC13x2/CC26x2 API for high-speed mode commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HS_CMD_H -#define __HS_CMD_H - -#ifndef __RFC_STRUCT -#define __RFC_STRUCT -#endif - -#ifndef __RFC_STRUCT_ATTR -#if defined(__GNUC__) -#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) -#elif defined(__TI_ARM__) -#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) -#else -#define __RFC_STRUCT_ATTR -#endif -#endif - -//! \addtogroup rfc -//! @{ - -//! \addtogroup hs_cmd -//! @{ - -#include -#include "rf_mailbox.h" -#include "rf_common_cmd.h" - -typedef struct __RFC_STRUCT rfc_CMD_HS_TX_s rfc_CMD_HS_TX_t; -typedef struct __RFC_STRUCT rfc_CMD_HS_RX_s rfc_CMD_HS_RX_t; -typedef struct __RFC_STRUCT rfc_hsRxOutput_s rfc_hsRxOutput_t; -typedef struct __RFC_STRUCT rfc_hsRxStatus_s rfc_hsRxStatus_t; - -//! \addtogroup CMD_HS_TX -//! @{ -#define CMD_HS_TX 0x3841 -//! High-Speed Transmit Command -struct __RFC_STRUCT rfc_CMD_HS_TX_s { - uint16_t commandNo; //!< The command ID number 0x3841 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
- //!< 1: Append CRC - uint8_t bVarLen:1; //!< \brief 0: Fixed length
- //!< 1: Transmit length as first half-word - uint8_t bCheckQAtEnd:1; //!< \brief 0: Always end with HS_DONE_OK when packet has been transmitted
- //!< 1: Check if Tx queue is empty when packet has been transmitted - } pktConf; - uint8_t __dummy0; - dataQueue_t* pQueue; //!< Pointer to Tx queue -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_HS_RX -//! @{ -#define CMD_HS_RX 0x3842 -//! High-Speed Receive Command -struct __RFC_STRUCT rfc_CMD_HS_RX_s { - uint16_t commandNo; //!< The command ID number 0x3842 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bUseCrc:1; //!< \brief 0: Do not receive or check CRC
- //!< 1: Receive and check CRC - uint8_t bVarLen:1; //!< \brief 0: Fixed length
- //!< 1: Receive length as first byte - uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t addressMode:2; //!< \brief 0: No address check
- //!< 1: Accept address0 and address1
- //!< 2: Accept address0, address1, and 0x0000
- //!< 3: Accept address0, address1, 0x0000, and 0xFFFF - } pktConf; - struct { - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bIncludeLen:1; //!< If 1, include the received length field in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise 3scard it - uint8_t bAppendStatus:1; //!< If 1, append a status word to the packet in the Rx queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConf; - uint16_t maxPktLen; //!< Packet length for fixed length; maximum packet length for variable length - uint16_t address0; //!< Address - uint16_t address1; //!< Address (set equal to address0 to accept only one address) - uint8_t __dummy0; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - dataQueue_t* pQueue; //!< Pointer to receive queue - rfc_hsRxOutput_t *pOutput; //!< Pointer to output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup hsRxOutput -//! @{ -//! Output structure for CMD_HS_RX - -struct __RFC_STRUCT rfc_hsRxOutput_s { - uint16_t nRxOk; //!< Number of packets that have been received with CRC OK - uint16_t nRxNok; //!< Number of packets that have been received with CRC error - uint16_t nRxAborted; //!< Number of packets not received due to illegal length or address mismatch - uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< RSSI of last received packet - ratmr_t timeStamp; //!< Time stamp of last received packet -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup hsRxStatus -//! @{ -//! Receive status word that may be appended to message in receive buffer - -struct __RFC_STRUCT rfc_hsRxStatus_s { - struct { - uint16_t rssi:8; //!< RSSI of the received packet in dBm (signed) - uint16_t bCrcErr:1; //!< \brief 0: Packet received OK
- //!< 1: Packet received with CRC error - uint16_t addressInd:2; //!< \brief 0: Received address0 (or no address check)
- //!< 1: Received address1
- //!< 2: Received address 0x0000
- //!< 3: Received address 0xFFFF - } status; -} __RFC_STRUCT_ATTR; - -//! @} - -//! @} -//! @} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h deleted file mode 100644 index e1fb7a05cd8..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_hs_mailbox.h +++ /dev/null @@ -1,65 +0,0 @@ -/****************************************************************************** -* Filename: rf_hs_mailbox.h -* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) -* Revision: 18171 -* -* Description: Definitions for high-speed mode radio interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _HS_MAILBOX_H -#define _HS_MAILBOX_H - -/// \name Radio operation status -///@{ -/// \name Operation finished normally -///@{ -#define HS_DONE_OK 0x3440 ///< Operation ended normally -#define HS_DONE_RXTIMEOUT 0x3441 ///< Operation stopped after end trigger while waiting for sync -#define HS_DONE_RXERR 0x3442 ///< Operation ended after CRC error -#define HS_DONE_TXBUF 0x3443 ///< Tx queue was empty at start of operation -#define HS_DONE_ENDED 0x3444 ///< Operation stopped after end trigger during reception -#define HS_DONE_STOPPED 0x3445 ///< Operation stopped after stop command -#define HS_DONE_ABORT 0x3446 ///< Operation aborted by abort command -///@} -/// \name Operation finished with error -///@{ -#define HS_ERROR_PAR 0x3840 ///< Illegal parameter -#define HS_ERROR_RXBUF 0x3841 ///< No available Rx buffer at the start of a packet -#define HS_ERROR_NO_SETUP 0x3842 ///< Radio was not set up in a compatible mode -#define HS_ERROR_NO_FS 0x3843 ///< Synth was not programmed when running Rx or Tx -#define HS_ERROR_RXOVF 0x3844 ///< Rx overflow observed during operation -#define HS_ERROR_TXUNF 0x3845 ///< Tx underflow observed during operation -///@} -///@} - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h deleted file mode 100644 index f33facdfe07..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_cmd.h +++ /dev/null @@ -1,628 +0,0 @@ -/****************************************************************************** -* Filename: rf_ieee_cmd.h -* Revised: 2018-01-15 06:15:14 +0100 (Mon, 15 Jan 2018) -* Revision: 18170 -* -* Description: CC13x2/CC26x2 API for IEEE 802.15.4 commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __IEEE_CMD_H -#define __IEEE_CMD_H - -#ifndef __RFC_STRUCT -#define __RFC_STRUCT -#endif - -#ifndef __RFC_STRUCT_ATTR -#if defined(__GNUC__) -#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) -#elif defined(__TI_ARM__) -#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) -#else -#define __RFC_STRUCT_ATTR -#endif -#endif - -//! \addtogroup rfc -//! @{ - -//! \addtogroup ieee_cmd -//! @{ - -#include -#include "rf_mailbox.h" -#include "rf_common_cmd.h" - -typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_s rfc_CMD_IEEE_RX_t; -typedef struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s rfc_CMD_IEEE_ED_SCAN_t; -typedef struct __RFC_STRUCT rfc_CMD_IEEE_TX_s rfc_CMD_IEEE_TX_t; -typedef struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s rfc_CMD_IEEE_CSMA_t; -typedef struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s rfc_CMD_IEEE_RX_ACK_t; -typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s rfc_CMD_IEEE_ABORT_BG_t; -typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s rfc_CMD_IEEE_MOD_CCA_t; -typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s rfc_CMD_IEEE_MOD_FILT_t; -typedef struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s rfc_CMD_IEEE_MOD_SRC_MATCH_t; -typedef struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s rfc_CMD_IEEE_ABORT_FG_t; -typedef struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s rfc_CMD_IEEE_STOP_FG_t; -typedef struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s rfc_CMD_IEEE_CCA_REQ_t; -typedef struct __RFC_STRUCT rfc_ieeeRxOutput_s rfc_ieeeRxOutput_t; -typedef struct __RFC_STRUCT rfc_shortAddrEntry_s rfc_shortAddrEntry_t; -typedef struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s rfc_ieeeRxCorrCrc_t; - -//! \addtogroup CMD_IEEE_RX -//! @{ -#define CMD_IEEE_RX 0x2801 -//! IEEE 802.15.4 Receive Command -struct __RFC_STRUCT rfc_CMD_IEEE_RX_s { - uint16_t commandNo; //!< The command ID number 0x2801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to tune to in the start of the operation
- //!< 0: Use existing channel
- //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
- //!< 60--207: Frequency is (2300 + channel) MHz
- //!< Others: Reserved - struct { - uint8_t bAutoFlushCrc:1; //!< If 1, automatically remove packets with CRC error from Rx queue - uint8_t bAutoFlushIgn:1; //!< If 1, automatically remove packets that can be ignored according to frame filtering from Rx queue - uint8_t bIncludePhyHdr:1; //!< If 1, include the received PHY header field in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the Rx queue - uint8_t bAppendCorrCrc:1; //!< If 1, append a correlation value and CRC result byte to the packet in the Rx queue - uint8_t bAppendSrcInd:1; //!< If 1, append an index from the source matching algorithm - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the Rx queue - } rxConfig; - dataQueue_t* pRxQ; //!< Pointer to receive queue - rfc_ieeeRxOutput_t *pOutput; //!< Pointer to output structure (NULL: Do not store results) - struct { - uint16_t frameFiltEn:1; //!< \brief 0: Disable frame filtering
- //!< 1: Enable frame filtering - uint16_t frameFiltStop:1; //!< \brief 0: Receive all packets to the end
- //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. - uint16_t autoAckEn:1; //!< \brief 0: Disable auto ACK
- //!< 1: Enable auto ACK. - uint16_t slottedAckEn:1; //!< \brief 0: Non-slotted ACK
- //!< 1: Slotted ACK. - uint16_t autoPendEn:1; //!< \brief 0: Auto-pend disabled
- //!< 1: Auto-pend enabled - uint16_t defaultPend:1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend - uint16_t bPendDataReqOnly:1; //!< \brief 0: Use auto-pend for any packet
- //!< 1: Use auto-pend for data request packets only - uint16_t bPanCoord:1; //!< \brief 0: Device is not PAN coordinator
- //!< 1: Device is PAN coordinator - uint16_t maxFrameVersion:2; //!< Reject frames where the frame version field in the FCF is greater than this value - uint16_t fcfReservedMask:3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero - uint16_t modifyFtFilter:2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
- //!< 0: No modification
- //!< 1: Invert MSB
- //!< 2: Set MSB to 0
- //!< 3: Set MSB to 1 - uint16_t bStrictLenFilter:1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
- //!< 1: Accept only acknowledgement frames of length 5 - } frameFiltOpt; //!< Frame filtering options - struct { - uint8_t bAcceptFt0Beacon:1; //!< \brief Treatment of frames with frame type 000 (beacon):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt1Data:1; //!< \brief Treatment of frames with frame type 001 (data):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt2Ack:1; //!< \brief Treatment of frames with frame type 010 (ACK):
- //!< 0: Reject, unless running ACK receive command
- //!< 1: Always accept - uint8_t bAcceptFt3MacCmd:1; //!< \brief Treatment of frames with frame type 011 (MAC command):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt4Reserved:1; //!< \brief Treatment of frames with frame type 100 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt5Reserved:1; //!< \brief Treatment of frames with frame type 101 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt6Reserved:1; //!< \brief Treatment of frames with frame type 110 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt7Reserved:1; //!< \brief Treatment of frames with frame type 111 (reserved):
- //!< 0: Reject
- //!< 1: Accept - } frameTypes; //!< Frame types to receive in frame filtering - struct { - uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source - uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source - uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source - uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA
- //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
- //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy - uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others
- //!< 0: Always report busy channel if ccaSync is busy
- //!< 1: Always report idle channel if ccaSync is idle - uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense - } ccaOpt; //!< CCA options - int8_t ccaRssiThr; //!< RSSI threshold for CCA - uint8_t __dummy0; - uint8_t numExtEntries; //!< Number of extended address entries - uint8_t numShortEntries; //!< Number of short address entries - uint32_t* pExtEntryList; //!< Pointer to list of extended address entries - uint32_t* pShortEntryList; //!< Pointer to list of short address entries - uint64_t localExtAddr; //!< The extended address of the local device - uint16_t localShortAddr; //!< The short address of the local device - uint16_t localPanID; //!< The PAN ID of the local device - uint16_t __dummy1; - uint8_t __dummy2; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Rx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx - //!< operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_IEEE_ED_SCAN -//! @{ -#define CMD_IEEE_ED_SCAN 0x2802 -//! IEEE 802.15.4 Energy Detect Scan Command -struct __RFC_STRUCT rfc_CMD_IEEE_ED_SCAN_s { - uint16_t commandNo; //!< The command ID number 0x2802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t channel; //!< \brief Channel to tune to in the start of the operation
- //!< 0: Use existing channel
- //!< 11--26: Use as IEEE 802.15.4 channel, i.e. frequency is (2405 + 5 × (channel - 11)) MHz
- //!< 60--207: Frequency is (2300 + channel) MHz
- //!< Others: Reserved - struct { - uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source - uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source - uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source - uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA
- //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
- //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy - uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others
- //!< 0: Always report busy channel if ccaSync is busy
- //!< 1: Always report idle channel if ccaSync is idle - uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense - } ccaOpt; //!< CCA options - int8_t ccaRssiThr; //!< RSSI threshold for CCA - uint8_t __dummy0; - int8_t maxRssi; //!< The maximum RSSI recorded during the ED scan - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the Rx operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the Rx - //!< operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_IEEE_TX -//! @{ -#define CMD_IEEE_TX 0x2C01 -//! IEEE 802.15.4 Transmit Command -struct __RFC_STRUCT rfc_CMD_IEEE_TX_s { - uint16_t commandNo; //!< The command ID number 0x2C01 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t bIncludePhyHdr:1; //!< \brief 0: Find PHY header automatically
- //!< 1: Insert PHY header from the buffer - uint8_t bIncludeCrc:1; //!< \brief 0: Append automatically calculated CRC
- //!< 1: Insert FCS (CRC) from the buffer - uint8_t :1; - uint8_t payloadLenMsb:5; //!< \brief Most significant bits of payload length. Should only be non-zero to create long - //!< non-standard packets for test purposes - } txOpt; - uint8_t payloadLen; //!< Number of bytes in the payload - uint8_t* pPayload; //!< Pointer to payload buffer of size payloadLen - ratmr_t timeStamp; //!< Time stamp of transmitted frame -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_IEEE_CSMA -//! @{ -#define CMD_IEEE_CSMA 0x2C02 -//! IEEE 802.15.4 CSMA-CA Command -struct __RFC_STRUCT rfc_CMD_IEEE_CSMA_s { - uint16_t commandNo; //!< The command ID number 0x2C02 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint16_t randomState; //!< The state of the pseudo-random generator - uint8_t macMaxBE; //!< The IEEE 802.15.4 MAC parameter macMaxBE - uint8_t macMaxCSMABackoffs; //!< The IEEE 802.15.4 MAC parameter macMaxCSMABackoffs - struct { - uint8_t initCW:5; //!< The initialization value for the CW parameter - uint8_t bSlotted:1; //!< \brief 0: non-slotted CSMA
- //!< 1: slotted CSMA - uint8_t rxOffMode:2; //!< \brief 0: RX stays on during CSMA backoffs
- //!< 1: The CSMA-CA algorithm will suspend the receiver if no frame is being received
- //!< 2: The CSMA-CA algorithm will suspend the receiver if no frame is being received, - //!< or after finishing it (including auto ACK) otherwise
- //!< 3: The CSMA-CA algorithm will suspend the receiver immediately during back-offs - } csmaConfig; - uint8_t NB; //!< The NB parameter from the IEEE 802.15.4 CSMA-CA algorithm - uint8_t BE; //!< The BE parameter from the IEEE 802.15.4 CSMA-CA algorithm - uint8_t remainingPeriods; //!< The number of remaining periods from a paused backoff countdown - int8_t lastRssi; //!< RSSI measured at the last CCA operation - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to end the CSMA-CA operation - ratmr_t lastTimeStamp; //!< Time of the last CCA operation - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to end the - //!< CSMA-CA operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_IEEE_RX_ACK -//! @{ -#define CMD_IEEE_RX_ACK 0x2C03 -//! IEEE 802.15.4 Receive Acknowledgement Command -struct __RFC_STRUCT rfc_CMD_IEEE_RX_ACK_s { - uint16_t commandNo; //!< The command ID number 0x2C03 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - uint8_t seqNo; //!< Sequence number to expect - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger that causes the device to give up acknowledgement reception - ratmr_t endTime; //!< \brief Time used together with endTrigger that causes the device to give up - //!< acknowledgement reception -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_IEEE_ABORT_BG -//! @{ -#define CMD_IEEE_ABORT_BG 0x2C04 -//! IEEE 802.15.4 Abort Background Level Command -struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_BG_s { - uint16_t commandNo; //!< The command ID number 0x2C04 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_IEEE_MOD_CCA -//! @{ -#define CMD_IEEE_MOD_CCA 0x2001 -//! IEEE 802.15.4 Modify CCA Parameter Command -struct __RFC_STRUCT rfc_CMD_IEEE_MOD_CCA_s { - uint16_t commandNo; //!< The command ID number 0x2001 - struct { - uint8_t ccaEnEnergy:1; //!< Enable energy scan as CCA source - uint8_t ccaEnCorr:1; //!< Enable correlator based carrier sense as CCA source - uint8_t ccaEnSync:1; //!< Enable sync found based carrier sense as CCA source - uint8_t ccaCorrOp:1; //!< \brief Operator to use between energy based and correlator based CCA
- //!< 0: Report busy channel if either ccaEnergy or ccaCorr are busy
- //!< 1: Report busy channel if both ccaEnergy and ccaCorr are busy - uint8_t ccaSyncOp:1; //!< \brief Operator to use between sync found based CCA and the others
- //!< 0: Always report busy channel if ccaSync is busy
- //!< 1: Always report idle channel if ccaSync is idle - uint8_t ccaCorrThr:2; //!< Threshold for number of correlation peaks in correlator based carrier sense - } newCcaOpt; //!< New value of ccaOpt for the running background level operation - int8_t newCcaRssiThr; //!< New value of ccaRssiThr for the running background level operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_IEEE_MOD_FILT -//! @{ -#define CMD_IEEE_MOD_FILT 0x2002 -//! IEEE 802.15.4 Modify Frame Filtering Parameter Command -struct __RFC_STRUCT rfc_CMD_IEEE_MOD_FILT_s { - uint16_t commandNo; //!< The command ID number 0x2002 - struct { - uint16_t frameFiltEn:1; //!< \brief 0: Disable frame filtering
- //!< 1: Enable frame filtering - uint16_t frameFiltStop:1; //!< \brief 0: Receive all packets to the end
- //!< 1: Stop receiving frame once frame filtering has caused the frame to be rejected. - uint16_t autoAckEn:1; //!< \brief 0: Disable auto ACK
- //!< 1: Enable auto ACK. - uint16_t slottedAckEn:1; //!< \brief 0: Non-slotted ACK
- //!< 1: Slotted ACK. - uint16_t autoPendEn:1; //!< \brief 0: Auto-pend disabled
- //!< 1: Auto-pend enabled - uint16_t defaultPend:1; //!< The value of the pending data bit in auto ACK packets that are not subject to auto-pend - uint16_t bPendDataReqOnly:1; //!< \brief 0: Use auto-pend for any packet
- //!< 1: Use auto-pend for data request packets only - uint16_t bPanCoord:1; //!< \brief 0: Device is not PAN coordinator
- //!< 1: Device is PAN coordinator - uint16_t maxFrameVersion:2; //!< Reject frames where the frame version field in the FCF is greater than this value - uint16_t fcfReservedMask:3; //!< Value to be AND-ed with the reserved part of the FCF; frame rejected if result is non-zero - uint16_t modifyFtFilter:2; //!< \brief Treatment of MSB of frame type field before frame-type filtering:
- //!< 0: No modification
- //!< 1: Invert MSB
- //!< 2: Set MSB to 0
- //!< 3: Set MSB to 1 - uint16_t bStrictLenFilter:1; //!< \brief 0: Accept acknowledgement frames of any length >= 5
- //!< 1: Accept only acknowledgement frames of length 5 - } newFrameFiltOpt; //!< New value of frameFiltOpt for the running background level operation - struct { - uint8_t bAcceptFt0Beacon:1; //!< \brief Treatment of frames with frame type 000 (beacon):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt1Data:1; //!< \brief Treatment of frames with frame type 001 (data):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt2Ack:1; //!< \brief Treatment of frames with frame type 010 (ACK):
- //!< 0: Reject, unless running ACK receive command
- //!< 1: Always accept - uint8_t bAcceptFt3MacCmd:1; //!< \brief Treatment of frames with frame type 011 (MAC command):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt4Reserved:1; //!< \brief Treatment of frames with frame type 100 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt5Reserved:1; //!< \brief Treatment of frames with frame type 101 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt6Reserved:1; //!< \brief Treatment of frames with frame type 110 (reserved):
- //!< 0: Reject
- //!< 1: Accept - uint8_t bAcceptFt7Reserved:1; //!< \brief Treatment of frames with frame type 111 (reserved):
- //!< 0: Reject
- //!< 1: Accept - } newFrameTypes; //!< New value of frameTypes for the running background level operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_IEEE_MOD_SRC_MATCH -//! @{ -#define CMD_IEEE_MOD_SRC_MATCH 0x2003 -//! IEEE 802.15.4 Enable/Disable Source Matching Entry Command -struct __RFC_STRUCT rfc_CMD_IEEE_MOD_SRC_MATCH_s { - uint16_t commandNo; //!< The command ID number 0x2003 - struct { - uint8_t bEnable:1; //!< \brief 0: Disable entry
- //!< 1: Enable entry - uint8_t srcPend:1; //!< New value of the pending bit for the entry - uint8_t entryType:1; //!< \brief 0: Short address
- //!< 1: Extended address - } options; - uint8_t entryNo; //!< Index of entry to enable or disable -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_IEEE_ABORT_FG -//! @{ -#define CMD_IEEE_ABORT_FG 0x2401 -//! IEEE 802.15.4 Abort Foreground Level Command -struct __RFC_STRUCT rfc_CMD_IEEE_ABORT_FG_s { - uint16_t commandNo; //!< The command ID number 0x2401 -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_IEEE_STOP_FG -//! @{ -#define CMD_IEEE_STOP_FG 0x2402 -//! IEEE 802.15.4 Gracefully Stop Foreground Level Command -struct __RFC_STRUCT rfc_CMD_IEEE_STOP_FG_s { - uint16_t commandNo; //!< The command ID number 0x2402 -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_IEEE_CCA_REQ -//! @{ -#define CMD_IEEE_CCA_REQ 0x2403 -//! IEEE 802.15.4 CCA and RSSI Information Request Command -struct __RFC_STRUCT rfc_CMD_IEEE_CCA_REQ_s { - uint16_t commandNo; //!< The command ID number 0x2403 - int8_t currentRssi; //!< The RSSI currently observed on the channel - int8_t maxRssi; //!< The maximum RSSI observed on the channel since Rx was started - struct { - uint8_t ccaState:2; //!< \brief Value of the current CCA state
- //!< 0: Idle
- //!< 1: Busy
- //!< 2: Invalid - uint8_t ccaEnergy:2; //!< \brief Value of the current energy detect CCA state
- //!< 0: Idle
- //!< 1: Busy
- //!< 2: Invalid - uint8_t ccaCorr:2; //!< \brief Value of the current correlator based carrier sense CCA state
- //!< 0: Idle
- //!< 1: Busy
- //!< 2: Invalid - uint8_t ccaSync:1; //!< \brief Value of the current sync found based carrier sense CCA state
- //!< 0: Idle
- //!< 1: Busy - } ccaInfo; -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ieeeRxOutput -//! @{ -//! Output structure for CMD_IEEE_RX - -struct __RFC_STRUCT rfc_ieeeRxOutput_s { - uint8_t nTxAck; //!< Total number of transmitted ACK frames - uint8_t nRxBeacon; //!< Number of received beacon frames - uint8_t nRxData; //!< Number of received data frames - uint8_t nRxAck; //!< Number of received acknowledgement frames - uint8_t nRxMacCmd; //!< Number of received MAC command frames - uint8_t nRxReserved; //!< Number of received frames with reserved frame type - uint8_t nRxNok; //!< Number of received frames with CRC error - uint8_t nRxIgnored; //!< Number of frames received that are to be ignored - uint8_t nRxBufFull; //!< Number of received frames discarded because the Rx buffer was full - int8_t lastRssi; //!< RSSI of last received frame - int8_t maxRssi; //!< Highest RSSI observed in the operation - uint8_t __dummy0; - ratmr_t beaconTimeStamp; //!< Time stamp of last received beacon frame -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup shortAddrEntry -//! @{ -//! Structure for short address entries - -struct __RFC_STRUCT rfc_shortAddrEntry_s { - uint16_t shortAddr; //!< Short address - uint16_t panId; //!< PAN ID -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup ieeeRxCorrCrc -//! @{ -//! Receive status byte that may be appended to message in receive buffer - -struct __RFC_STRUCT rfc_ieeeRxCorrCrc_s { - struct { - uint8_t corr:6; //!< The correlation value - uint8_t bIgnore:1; //!< 1 if the packet should be rejected by frame filtering, 0 otherwise - uint8_t bCrcErr:1; //!< 1 if the packet was received with CRC error, 0 otherwise - } status; -} __RFC_STRUCT_ATTR; - -//! @} - -//! @} -//! @} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h deleted file mode 100644 index a9fc22162d4..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_ieee_mailbox.h +++ /dev/null @@ -1,73 +0,0 @@ -/****************************************************************************** -* Filename: rf_ieee_mailbox.h -* Revised: 2018-01-23 19:51:42 +0100 (Tue, 23 Jan 2018) -* Revision: 18189 -* -* Description: Definitions for IEEE 802.15.4 interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _IEEE_MAILBOX_H -#define _IEEE_MAILBOX_H - -#include "rf_mailbox.h" - -/// \name Radio operation status -///@{ -/// \name Operation not finished -///@{ -#define IEEE_SUSPENDED 0x2001 ///< Operation suspended -///@} -/// \name Operation finished normally -///@{ -#define IEEE_DONE_OK 0x2400 ///< Operation ended normally -#define IEEE_DONE_BUSY 0x2401 ///< CSMA-CA operation ended with failure -#define IEEE_DONE_STOPPED 0x2402 ///< Operation stopped after stop command -#define IEEE_DONE_ACK 0x2403 ///< ACK packet received with pending data bit cleared -#define IEEE_DONE_ACKPEND 0x2404 ///< ACK packet received with pending data bit set -#define IEEE_DONE_TIMEOUT 0x2405 ///< Operation ended due to timeout -#define IEEE_DONE_BGEND 0x2406 ///< FG operation ended because necessary background level - ///< operation ended -#define IEEE_DONE_ABORT 0x2407 ///< Operation aborted by command -///@} -/// \name Operation finished with error -///@{ -#define IEEE_ERROR_PAR 0x2800 ///< Illegal parameter -#define IEEE_ERROR_NO_SETUP 0x2801 ///< Operation using Rx or Tx attempted when not in 15.4 mode -#define IEEE_ERROR_NO_FS 0x2802 ///< Operation using Rx or Tx attempted without frequency synth configured -#define IEEE_ERROR_SYNTH_PROG 0x2803 ///< Synthesizer programming failed to complete on time -#define IEEE_ERROR_RXOVF 0x2804 ///< Receiver overflowed during operation -#define IEEE_ERROR_TXUNF 0x2805 ///< Transmitter underflowed during operation -///@} -///@} - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h deleted file mode 100644 index a23d71ad0be..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_mailbox.h +++ /dev/null @@ -1,364 +0,0 @@ -/****************************************************************************** -* Filename: rf_mailbox.h -* Revised: 2018-11-02 11:52:02 +0100 (Fri, 02 Nov 2018) -* Revision: 18756 -* -* Description: Definitions for interface between system and radio CPU -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _MAILBOX_H -#define _MAILBOX_H - -#include -#include - - -/// \name RF mode values -/// Defines used to indicate mode of operation to radio core. -///@{ -#define RF_MODE_AUTO 0x00 -#define RF_MODE_BLE 0x00 -#define RF_MODE_IEEE_15_4 0x00 -#define RF_MODE_PROPRIETARY_2_4 0x00 -#define RF_MODE_PROPRIETARY RF_MODE_PROPRIETARY_2_4 -#define RF_MODE_MULTIPLE 0x00 -///@} - - -/// Type definition for RAT -typedef uint32_t ratmr_t; - - - -/// Type definition for a data queue -typedef struct { - uint8_t *pCurrEntry; ///< Pointer to the data queue entry to be used, NULL for an empty queue - uint8_t *pLastEntry; ///< Pointer to the last entry in the queue, NULL for a circular queue -} dataQueue_t; - - - -/// \name CPE interrupt definitions -/// Interrupt masks for the CPE interrupt in RDBELL. -///@{ -#define IRQN_COMMAND_DONE 0 ///< Radio operation command finished -#define IRQN_LAST_COMMAND_DONE 1 ///< Last radio operation command in a chain finished -#define IRQN_FG_COMMAND_DONE 2 ///< FG level Radio operation command finished -#define IRQN_LAST_FG_COMMAND_DONE 3 ///< Last FG level radio operation command in a chain finished -#define IRQN_TX_DONE 4 ///< Packet transmitted -#define IRQN_TX_ACK 5 ///< ACK packet transmitted -#define IRQN_TX_CTRL 6 ///< Control packet transmitted -#define IRQN_TX_CTRL_ACK 7 ///< Acknowledgement received on a transmitted control packet -#define IRQN_TX_CTRL_ACK_ACK 8 ///< Acknowledgement received on a transmitted control packet, and acknowledgement transmitted for that packet -#define IRQN_TX_RETRANS 9 ///< Packet retransmitted -#define IRQN_TX_ENTRY_DONE 10 ///< Tx queue data entry state changed to Finished -#define IRQN_TX_BUFFER_CHANGED 11 ///< A buffer change is complete -#define IRQN_COMMAND_STARTED 12 ///< A radio operation command has gone into active state -#define IRQN_FG_COMMAND_STARTED 13 ///< FG level radio operation command has gone into active state -#define IRQN_PA_CHANGED 14 ///< PA is changed -#define IRQN_RX_OK 16 ///< Packet received with CRC OK, payload, and not to be ignored -#define IRQN_RX_NOK 17 ///< Packet received with CRC error -#define IRQN_RX_IGNORED 18 ///< Packet received with CRC OK, but to be ignored -#define IRQN_RX_EMPTY 19 ///< Packet received with CRC OK, not to be ignored, no payload -#define IRQN_RX_CTRL 20 ///< Control packet received with CRC OK, not to be ignored -#define IRQN_RX_CTRL_ACK 21 ///< Control packet received with CRC OK, not to be ignored, then ACK sent -#define IRQN_RX_BUF_FULL 22 ///< Packet received that did not fit in the Rx queue -#define IRQN_RX_ENTRY_DONE 23 ///< Rx queue data entry changing state to Finished -#define IRQN_RX_DATA_WRITTEN 24 ///< Data written to partial read Rx buffer -#define IRQN_RX_N_DATA_WRITTEN 25 ///< Specified number of bytes written to partial read Rx buffer -#define IRQN_RX_ABORTED 26 ///< Packet reception stopped before packet was done -#define IRQN_RX_COLLISION_DETECTED 27 ///< A collision was indicated during packet reception -#define IRQN_SYNTH_NO_LOCK 28 ///< The synth has gone out of lock after calibration -#define IRQN_MODULES_UNLOCKED 29 ///< As part of the boot process, the CM0 has opened access to RF core modules and memories -#define IRQN_BOOT_DONE 30 ///< The RF core CPU boot is finished - -#define IRQN_INTERNAL_ERROR 31 ///< Internal error observed - -#define IRQ_COMMAND_DONE (1U << IRQN_COMMAND_DONE) -#define IRQ_LAST_COMMAND_DONE (1U << IRQN_LAST_COMMAND_DONE) -#define IRQ_FG_COMMAND_DONE (1U << IRQN_FG_COMMAND_DONE) -#define IRQ_LAST_FG_COMMAND_DONE (1U << IRQN_LAST_FG_COMMAND_DONE) - -#define IRQ_TX_DONE (1U << IRQN_TX_DONE) -#define IRQ_TX_ACK (1U << IRQN_TX_ACK) -#define IRQ_TX_CTRL (1U << IRQN_TX_CTRL) -#define IRQ_TX_CTRL_ACK (1U << IRQN_TX_CTRL_ACK) -#define IRQ_TX_CTRL_ACK_ACK (1U << IRQN_TX_CTRL_ACK_ACK) -#define IRQ_TX_RETRANS (1U << IRQN_TX_RETRANS) - -#define IRQ_TX_ENTRY_DONE (1U << IRQN_TX_ENTRY_DONE) -#define IRQ_TX_BUFFER_CHANGED (1U << IRQN_TX_BUFFER_CHANGED) - -#define IRQ_COMMAND_STARTED (1U << IRQN_COMMAND_STARTED) -#define IRQ_FG_COMMAND_STARTED (1U << IRQN_FG_COMMAND_STARTED) -#define IRQ_PA_CHANGED (1U << IRQN_PA_CHANGED) - -#define IRQ_RX_OK (1U << IRQN_RX_OK) -#define IRQ_RX_NOK (1U << IRQN_RX_NOK) -#define IRQ_RX_IGNORED (1U << IRQN_RX_IGNORED) -#define IRQ_RX_EMPTY (1U << IRQN_RX_EMPTY) -#define IRQ_RX_CTRL (1U << IRQN_RX_CTRL) -#define IRQ_RX_CTRL_ACK (1U << IRQN_RX_CTRL_ACK) -#define IRQ_RX_BUF_FULL (1U << IRQN_RX_BUF_FULL) -#define IRQ_RX_ENTRY_DONE (1U << IRQN_RX_ENTRY_DONE) -#define IRQ_RX_DATA_WRITTEN (1U << IRQN_RX_DATA_WRITTEN) -#define IRQ_RX_N_DATA_WRITTEN (1U << IRQN_RX_N_DATA_WRITTEN) -#define IRQ_RX_ABORTED (1U << IRQN_RX_ABORTED) -#define IRQ_RX_COLLISION_DETECTED (1U << IRQN_RX_COLLISION_DETECTED) -#define IRQ_SYNTH_NO_LOCK (1U << IRQN_SYNTH_NO_LOCK) -#define IRQ_MODULES_UNLOCKED (1U << IRQN_MODULES_UNLOCKED) -#define IRQ_BOOT_DONE (1U << IRQN_BOOT_DONE) -#define IRQ_INTERNAL_ERROR (1U << IRQN_INTERNAL_ERROR) -///@} - - - -/// \name CMDSTA values -/// Values returned in result byte of CMDSTA -///@{ -#define CMDSTA_Pending 0x00 ///< The command has not yet been parsed -#define CMDSTA_Done 0x01 ///< Command successfully parsed - -#define CMDSTA_IllegalPointer 0x81 ///< The pointer signaled in CMDR is not valid -#define CMDSTA_UnknownCommand 0x82 ///< The command number in the command structure is unknown -#define CMDSTA_UnknownDirCommand 0x83 ///< The command number for a direct command is unknown, or the - ///< command is not a direct command -#define CMDSTA_ContextError 0x85 ///< An immediate or direct command was issued in a context - ///< where it is not supported -#define CMDSTA_SchedulingError 0x86 ///< A radio operation command was attempted to be scheduled - ///< while another operation was already running in the RF core -#define CMDSTA_ParError 0x87 ///< There were errors in the command parameters that are parsed - ///< on submission. -#define CMDSTA_QueueError 0x88 ///< An operation on a data entry queue was attempted that was - ///< not supported by the queue in its current state -#define CMDSTA_QueueBusy 0x89 ///< An operation on a data entry was attempted while that entry - ///< was busy -///@} - - - -/// \name Macros for sending direct commands -///@{ -/// Direct command with no parameter -#define CMDR_DIR_CMD(cmdId) (((cmdId) << 16) | 1) - -/// Direct command with 1-byte parameter -#define CMDR_DIR_CMD_1BYTE(cmdId, par) (((cmdId) << 16) | ((par) << 8) | 1) - -/// Direct command with 2-byte parameter -#define CMDR_DIR_CMD_2BYTE(cmdId, par) (((cmdId) << 16) | ((par) & 0xFFFC) | 1) - -///@} - - - -/// \name Definitions for trigger types -///@{ -#define TRIG_NOW 0 ///< Triggers immediately -#define TRIG_NEVER 1 ///< Never trigs -#define TRIG_ABSTIME 2 ///< Trigs at an absolute time -#define TRIG_REL_SUBMIT 3 ///< Trigs at a time relative to the command was submitted -#define TRIG_REL_START 4 ///< Trigs at a time relative to the command started -#define TRIG_REL_PREVSTART 5 ///< Trigs at a time relative to the previous command in the chain started -#define TRIG_REL_FIRSTSTART 6 ///< Trigs at a time relative to the first command in the chain started -#define TRIG_REL_PREVEND 7 ///< Trigs at a time relative to the previous command in the chain ended -#define TRIG_REL_EVT1 8 ///< Trigs at a time relative to the context defined "Event 1" -#define TRIG_REL_EVT2 9 ///< Trigs at a time relative to the context defined "Event 2" -#define TRIG_EXTERNAL 10 ///< Trigs at an external event to the radio timer -#define TRIG_PAST_BM 0x80 ///< Bitmask for setting pastTrig bit in order to trig immediately if - ///< trigger happened in the past -///@} - - -/// \name Definitions for conditional execution -///@{ -#define COND_ALWAYS 0 ///< Always run next command (except in case of Abort) -#define COND_NEVER 1 ///< Never run next command -#define COND_STOP_ON_FALSE 2 ///< Run next command if this command returned True, stop if it returned - ///< False -#define COND_STOP_ON_TRUE 3 ///< Stop if this command returned True, run next command if it returned - ///< False -#define COND_SKIP_ON_FALSE 4 ///< Run next command if this command returned True, skip a number of - ///< commands if it returned False -#define COND_SKIP_ON_TRUE 5 ///< Skip a number of commands if this command returned True, run next - ///< command if it returned False -///@} - - - -/// \name Radio operation status -///@{ -/// \name Operation not finished -///@{ -#define IDLE 0x0000 ///< Operation not started -#define PENDING 0x0001 ///< Start of command is pending -#define ACTIVE 0x0002 ///< Running -#define SKIPPED 0x0003 ///< Operation skipped due to condition in another command -///@} -/// \name Operation finished normally -///@{ -#define DONE_OK 0x0400 ///< Operation ended normally -#define DONE_COUNTDOWN 0x0401 ///< Counter reached zero -#define DONE_RXERR 0x0402 ///< Operation ended with CRC error -#define DONE_TIMEOUT 0x0403 ///< Operation ended with timeout -#define DONE_STOPPED 0x0404 ///< Operation stopped after CMD_STOP command -#define DONE_ABORT 0x0405 ///< Operation aborted by CMD_ABORT command -#define DONE_FAILED 0x0406 ///< Scheduled immediate command failed -///@} -/// \name Operation finished with error -///@{ -#define ERROR_PAST_START 0x0800 ///< The start trigger occurred in the past -#define ERROR_START_TRIG 0x0801 ///< Illegal start trigger parameter -#define ERROR_CONDITION 0x0802 ///< Illegal condition for next operation -#define ERROR_PAR 0x0803 ///< Error in a command specific parameter -#define ERROR_POINTER 0x0804 ///< Invalid pointer to next operation -#define ERROR_CMDID 0x0805 ///< Next operation has a command ID that is undefined or not a radio - ///< operation command -#define ERROR_WRONG_BG 0x0806 ///< FG level command not compatible with running BG level command -#define ERROR_NO_SETUP 0x0807 ///< Operation using Rx or Tx attempted without CMD_RADIO_SETUP -#define ERROR_NO_FS 0x0808 ///< Operation using Rx or Tx attempted without frequency synth configured -#define ERROR_SYNTH_PROG 0x0809 ///< Synthesizer calibration failed -#define ERROR_TXUNF 0x080A ///< Tx underflow observed -#define ERROR_RXOVF 0x080B ///< Rx overflow observed -#define ERROR_NO_RX 0x080C ///< Attempted to access data from Rx when no such data was yet received -#define ERROR_PENDING 0x080D ///< Command submitted in the future with another command at different level pending -///@} -///@} - - -/// \name Data entry types -///@{ -#define DATA_ENTRY_TYPE_GEN 0 ///< General type: Tx entry or single element Rx entry -#define DATA_ENTRY_TYPE_MULTI 1 ///< Multi-element Rx entry type -#define DATA_ENTRY_TYPE_PTR 2 ///< Pointer entry type -#define DATA_ENTRY_TYPE_PARTIAL 3 ///< Partial read entry type -///@ - - -/// \name Data entry statuses -///@{ -#define DATA_ENTRY_PENDING 0 ///< Entry not yet used -#define DATA_ENTRY_ACTIVE 1 ///< Entry in use by radio CPU -#define DATA_ENTRY_BUSY 2 ///< Entry being updated -#define DATA_ENTRY_FINISHED 3 ///< Radio CPU is finished accessing the entry -#define DATA_ENTRY_UNFINISHED 4 ///< Radio CPU is finished accessing the entry, but packet could not be finished -///@} - - -/// \name Macros for RF register override -///@{ -/// Macro for ADI half-size value-mask combination -#define ADI_VAL_MASK(addr, mask, value) \ -(((addr) & 1) ? (((mask) & 0x0F) | (((value) & 0x0F) << 4)) : \ - ((((mask) & 0x0F) << 4) | ((value) & 0x0F))) -/// 32-bit write of 16-bit value -#define HW_REG_OVERRIDE(addr, val) ((((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(val) << 16)) -/// ADI register, full-size write -#define ADI_REG_OVERRIDE(adiNo, addr, val) (2 | ((uint32_t)(val) << 16) | \ -(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) -/// 2 ADI registers, full-size write -#define ADI_2REG_OVERRIDE(adiNo, addr, val, addr2, val2) \ -(2 | ((uint32_t)(val2) << 2) | (((addr2) & 0x3F) << 10) | ((uint32_t)(val) << 16) | \ -(((addr) & 0x3F) << 24) | (((adiNo) ? 1U : 0) << 31)) -/// ADI register, half-size read-modify-write -#define ADI_HALFREG_OVERRIDE(adiNo, addr, mask, val) (2 | (ADI_VAL_MASK(addr, mask, val) << 16) | \ -(((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) -/// 2 ADI registers, half-size read-modify-write -#define ADI_2HALFREG_OVERRIDE(adiNo, addr, mask, val, addr2, mask2, val2) \ -(2 | (ADI_VAL_MASK(addr2, mask2, val2) << 2) | (((addr2) & 0x3F) << 10) | \ -(ADI_VAL_MASK(addr, mask, val) << 16) | (((addr) & 0x3F) << 24) | (1U << 30) | (((adiNo) ? 1U : 0) << 31)) - -/// 16-bit SW register as defined in radio_par_def.txt -#define SW_REG_OVERRIDE(cmd, field, val) (3 | ((_POSITION_##cmd##_##field) << 4) | ((uint32_t)(val) << 16)) -/// SW register as defined in radio_par_def.txt with added index (for use with registers > 16 bits). -#define SW_REG_IND_OVERRIDE(cmd, field, offset, val) (3 | \ -(((_POSITION_##cmd##_##field) + ((offset) << 1)) << 4) | ((uint32_t)(val) << 16)) -/// 8-bit SW register as defined in radio_par_def.txt -#define SW_REG_BYTE_OVERRIDE(cmd, field, val) (0x8003 | ((_POSITION_##cmd##_##field) << 4) | \ -(((uint32_t)(val) & 0xFF) << 16)) -/// Two 8-bit SW registers as defined in radio_par_def.txt; the one given by field and the next byte. -#define SW_REG_2BYTE_OVERRIDE(cmd, field, val0, val1) (3 | (((_POSITION_##cmd##_##field) & 0xFFFE) << 4) | \ - (((uint32_t)(val0) << 16) & 0x00FF0000) | ((uint32_t)(val1) << 24)) -#define SW_REG_MASK_OVERRIDE(cmd, field, offset, mask, val) (0x8003 | \ -((_POSITION_##cmd##_##field + (offset)) << 4) | (((uint32_t)(val) & 0xFF) << 16) | (((uint32_t)(mask) & 0xFF) << 24)) - -#define HW16_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) -#define HW32_ARRAY_OVERRIDE(addr, length) (1 | (((uintptr_t) (addr)) & 0xFFFC) | \ -((uint32_t)(length) << 16) | (1U << 30)) -#define HW16_MASK_ARRAY_OVERRIDE(addr, length) (0x20000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) -#define HW32_MASK_ARRAY_OVERRIDE(addr, length) (0x60000001 | (((uintptr_t) (addr)) & 0xFFFC) | ((uint32_t)(length) << 16)) -#define HW16_MASK_VAL(mask, val) ((mask) << 16 | (val)) -#define ADI_ARRAY_OVERRIDE(adiNo, addr, bHalfSize, length) (1 | ((((addr) & 0x3F) << 2)) | \ -((!!(bHalfSize)) << 8) | ((!!(adiNo)) << 9) | ((uint32_t)(length) << 16) | (2U << 30)) -#define SW_ARRAY_OVERRIDE(cmd, firstfield, length) (1 | (((_POSITION_##cmd##_##firstfield)) << 2) | \ -((uint32_t)(length) << 16) | (3U << 30)) -#define MCE_RFE_OVERRIDE(mceCfg, mceRomBank, mceMode, rfeCfg, rfeRomBank, rfeMode) \ - (7 | ((mceCfg & 2) << 3) | ((rfeCfg & 2) << 4) |\ - ((mceCfg & 1) << 6) | (((mceRomBank) & 0x0F) << 7) | \ - ((rfeCfg & 1) << 11) | (((rfeRomBank) & 0x0F) << 12) | \ - (((mceMode) & 0x00FF) << 16) | (((rfeMode) & 0x00FF) << 24)) -#define HPOSC_OVERRIDE(freqOffset) (0x000B | ((freqOffset) << 16)) -#define TX20_POWER_OVERRIDE(tx20Power) (0x002B | (((uint32_t) tx20Power) << 10)) -#define TX_STD_POWER_OVERRIDE(txPower) (0x022B | (((uint32_t) txPower) << 10)) -#define MCE_RFE_SPLIT_OVERRIDE(mceRxCfg, mceTxCfg, rfeRxCfg, rfeTxCfg) \ - (0x003B | ((mceRxCfg) << 12) | ((mceTxCfg) << 17) | ((rfeRxCfg) << 22) | ((rfeTxCfg) << 27)) -#define CENTER_FREQ_OVERRIDE(centerFreq, flags) (0x004B | ((flags & 0x03) << 18) | \ - ((centerFreq) << 20)) -#define MOD_TYPE_OVERRIDE(modType, deviation, stepSz, flags) (0x005B | ((flags & 0x01) << 15) | \ - ((modType) << 16) | ((deviation) << 19) |((stepSz) << 30) ) -#define NEW_OVERRIDE_SEGMENT(address) (((((uintptr_t)(address)) & 0x03FFFFFC) << 6) | 0x000F | \ - (((((uintptr_t)(address) >> 24) == 0x20) ? 0x01 : \ - (((uintptr_t)(address) >> 24) == 0x21) ? 0x02 : \ - (((uintptr_t)(address) >> 24) == 0xA0) ? 0x03 : \ - (((uintptr_t)(address) >> 24) == 0x00) ? 0x04 : \ - (((uintptr_t)(address) >> 24) == 0x10) ? 0x05 : \ - (((uintptr_t)(address) >> 24) == 0x11) ? 0x06 : \ - (((uintptr_t)(address) >> 24) == 0x40) ? 0x07 : \ - (((uintptr_t)(address) >> 24) == 0x50) ? 0x08 : \ - 0x09) << 4)) // Use illegal value for illegal address range -/// End of string for override register -#define END_OVERRIDE 0xFFFFFFFF - - -/// ADI address-value pair -#define ADI_ADDR_VAL(addr, value) ((((addr) & 0x7F) << 8) | ((value) & 0xFF)) -#define ADI_ADDR_VAL_MASK(addr, mask, value) ((((addr) & 0x7F) << 8) | ADI_VAL_MASK(addr, mask, value)) - -/// Low half-word -#define LOWORD(value) ((value) & 0xFFFF) -/// High half-word -#define HIWORD(value) ((value) >> 16) -///@} - - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h deleted file mode 100644 index 6dbccd65523..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_cmd.h +++ /dev/null @@ -1,1171 +0,0 @@ -/****************************************************************************** -* Filename: rf_prop_cmd.h -* Revised: 2018-07-31 20:13:42 +0200 (Tue, 31 Jul 2018) -* Revision: 18572 -* -* Description: CC13x2/CC26x2 API for Proprietary mode commands -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __PROP_CMD_H -#define __PROP_CMD_H - -#ifndef __RFC_STRUCT -#define __RFC_STRUCT -#endif - -#ifndef __RFC_STRUCT_ATTR -#if defined(__GNUC__) -#define __RFC_STRUCT_ATTR __attribute__ ((aligned (4))) -#elif defined(__TI_ARM__) -#define __RFC_STRUCT_ATTR __attribute__ ((__packed__,aligned (4))) -#else -#define __RFC_STRUCT_ATTR -#endif -#endif - -//! \addtogroup rfc -//! @{ - -//! \addtogroup prop_cmd -//! @{ - -#include -#include "rf_mailbox.h" -#include "rf_common_cmd.h" - -typedef struct __RFC_STRUCT rfc_carrierSense_s rfc_carrierSense_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_s rfc_CMD_PROP_TX_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_s rfc_CMD_PROP_RX_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s rfc_CMD_PROP_TX_ADV_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s rfc_CMD_PROP_RX_ADV_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_CS_s rfc_CMD_PROP_CS_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s rfc_CMD_PROP_RADIO_SETUP_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s rfc_CMD_PROP_RADIO_DIV_SETUP_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_SNIFF_s rfc_CMD_PROP_RX_SNIFF_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s rfc_CMD_PROP_RX_ADV_SNIFF_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_PA_s rfc_CMD_PROP_RADIO_SETUP_PA_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_PA_s rfc_CMD_PROP_RADIO_DIV_SETUP_PA_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s rfc_CMD_PROP_SET_LEN_t; -typedef struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s rfc_CMD_PROP_RESTART_RX_t; -typedef struct __RFC_STRUCT rfc_propRxOutput_s rfc_propRxOutput_t; -typedef struct __RFC_STRUCT rfc_propRxStatus_s rfc_propRxStatus_t; - -//! \addtogroup carrierSense -//! @{ -struct __RFC_STRUCT rfc_carrierSense_s { - struct { - uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion - uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion - uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
- //!< 1: Busy if both RSSI and correlation indicates Busy - uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
- //!< 1: End carrier sense on channel Busy
- //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle - uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
- //!< 1: End on channel Idle - uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
- //!< 1: Timeout with channel state Invalid treated as Idle - } csConf; - int8_t rssiThr; //!< RSSI threshold - uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is - //!< declared Idle - uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is - //!< declared Busy - uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods - struct { - uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Idle to Invalid - uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Invalid to Busy - } corrConfig; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } csEndTrigger; //!< Trigger classifier for ending the carrier sense - ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_TX -//! @{ -#define CMD_PROP_TX 0x3801 -//! Proprietary Mode Transmit Command -struct __RFC_STRUCT rfc_CMD_PROP_TX_s { - uint16_t commandNo; //!< The command ID number 0x3801 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t :2; - uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
- //!< 1: Append CRC - uint8_t bVarLen:1; //!< \brief 0: Fixed length
- //!< 1: Transmit length as first byte - } pktConf; - uint8_t pktLen; //!< Packet length - uint32_t syncWord; //!< Sync word to transmit - uint8_t* pPkt; //!< Pointer to packet -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_RX -//! @{ -#define CMD_PROP_RX 0x3802 -//! Proprietary Mode Receive Command -struct __RFC_STRUCT rfc_CMD_PROP_RX_s { - uint16_t commandNo; //!< The command ID number 0x3802 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bVarLen:1; //!< \brief 0: Fixed length
- //!< 1: Receive length as first byte - uint8_t bChkAddress:1; //!< \brief 0: No address check
- //!< 1: Check address - uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t :1; - uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord; //!< Sync word to listen for - uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - uint8_t address0; //!< Address - uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept - //!< 0x00 as well) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_TX_ADV -//! @{ -#define CMD_PROP_TX_ADV 0x3803 -//! Proprietary Mode Advanced Transmit Command -struct __RFC_STRUCT rfc_CMD_PROP_TX_ADV_s { - uint16_t commandNo; //!< The command ID number 0x3803 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t :2; - uint8_t bUseCrc:1; //!< \brief 0: Do not append CRC
- //!< 1: Append CRC - uint8_t bCrcIncSw:1; //!< \brief 0:Do not include sync word in CRC calculation
- //!< 1: Include sync word in CRC calculation - uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
- //!< 1: Include header in CRC calculation - } pktConf; - uint8_t numHdrBits; //!< Number of bits in header (0--32) - uint16_t pktLen; //!< Packet length. 0: Unlimited - struct { - uint8_t bExtTxTrig:1; //!< \brief 0: Start packet on a fixed time from the command start trigger
- //!< 1: Start packet on an external trigger (input event to RAT) - uint8_t inputMode:2; //!< \brief Input mode if external trigger is used for TX start
- //!< 0: Rising edge
- //!< 1: Falling edge
- //!< 2: Both edges
- //!< 3: Reserved - uint8_t source:5; //!< RAT input event number used for capture if external trigger is used for TX start - } startConf; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } preTrigger; //!< Trigger for transition from preamble to sync word - ratmr_t preTime; //!< \brief Time used together with preTrigger for transition from preamble to sync - //!< word. If preTrigger.triggerType is set to "now", one preamble as - //!< configured in the setup will be sent. Otherwise, the preamble will be repeated until - //!< this trigger is observed. - uint32_t syncWord; //!< Sync word to transmit - uint8_t* pPkt; //!< Pointer to packet, or TX queue for unlimited length -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_RX_ADV -//! @{ -#define CMD_PROP_RX_ADV 0x3804 -//! Proprietary Mode Advanced Receive Command -struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_s { - uint16_t commandNo; //!< The command ID number 0x3804 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bCrcIncSw:1; //!< \brief 0: Do not include sync word in CRC calculation
- //!< 1: Include sync word in CRC calculation - uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
- //!< 1: Include header in CRC calculation - uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t :1; - uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord0; //!< Sync word to listen for - uint32_t syncWord1; //!< Alternative sync word if non-zero - uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - struct { - uint16_t numHdrBits:6; //!< Number of bits in header (0--32) - uint16_t lenPos:5; //!< Position of length field in header (0--31) - uint16_t numLenBits:5; //!< Number of bits in length field (0--16) - } hdrConf; - struct { - uint16_t addrType:1; //!< \brief 0: Address after header
- //!< 1: Address in header - uint16_t addrSize:5; //!< \brief If addrType = 0: Address size in bytes
- //!< If addrType = 1: Address size in bits - uint16_t addrPos:5; //!< \brief If addrType = 1: Bit position of address in header
- //!< If addrType = 0: Non-zero to extend address with sync word identifier - uint16_t numAddr:5; //!< Number of addresses in address list - } addrConf; - int8_t lenOffset; //!< Signed value to add to length field - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - uint8_t* pAddr; //!< Pointer to address list - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_CS -//! @{ -#define CMD_PROP_CS 0x3805 -//! Carrier Sense Command -struct __RFC_STRUCT rfc_CMD_PROP_CS_s { - uint16_t commandNo; //!< The command ID number 0x3805 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t bFsOffIdle:1; //!< \brief 0: Keep synth running if command ends with channel Idle
- //!< 1: Turn off synth if command ends with channel Idle - uint8_t bFsOffBusy:1; //!< \brief 0: Keep synth running if command ends with channel Busy
- //!< 1: Turn off synth if command ends with channel Busy - } csFsConf; - uint8_t __dummy0; - struct { - uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion - uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion - uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
- //!< 1: Busy if both RSSI and correlation indicates Busy - uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
- //!< 1: End carrier sense on channel Busy
- //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle - uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
- //!< 1: End on channel Idle - uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
- //!< 1: Timeout with channel state Invalid treated as Idle - } csConf; - int8_t rssiThr; //!< RSSI threshold - uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is - //!< declared Idle - uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is - //!< declared Busy - uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods - struct { - uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Idle to Invalid - uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Invalid to Busy - } corrConfig; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } csEndTrigger; //!< Trigger classifier for ending the carrier sense - ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_RADIO_SETUP -//! @{ -#define CMD_PROP_RADIO_SETUP 0x3806 -//! Proprietary Mode Radio Setup Command for 2.4 GHz -struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x3806 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint16_t modType:3; //!< \brief 0: FSK
- //!< 1: GFSK
- //!< 2: OOK
- //!< Others: Reserved - uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) - uint16_t deviationStepSz:2; //!< \brief Deviation step size
- //!< 0: 250 Hz
- //!< 1: 1000 Hz
- //!< 2: 15.625 Hz
- //!< 3: 62.5 Hz - } modulation; - struct { - uint32_t preScale:8; //!< Prescaler value - uint32_t rateWord:21; //!< Rate word - uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
- //!< 1: Force PDIF decimation to 0
- //!< 3: Force PDIF decimation to 1
- //!< 5: Force PDIF decimation to 2
- //!< Others: Reserved - } symbolRate; //!< Symbol rate setting - uint8_t rxBw; //!< Receiver bandwidth - struct { - uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
- //!< 1--16: Number of preamble bytes
- //!< 18, 20, ..., 30: Number of preamble bytes
- //!< 31: 4 preamble bits
- //!< 32: 32 preamble bytes
- //!< Others: Reserved - uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
- //!< 1: Send 1 as the first preamble bit
- //!< 2: Send same first bit in preamble and sync word
- //!< 3: Send different first bit in preamble and sync word - } preamConf; - struct { - uint16_t nSwBits:6; //!< Number of sync word bits (8--32) - uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
- //!< 1: Use positive deviation for 0 - uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
- //!< 1: Most significant bit transmitted first - uint16_t fecMode:4; //!< \brief Select coding
- //!< 0: Uncoded binary modulation
- //!< 10: Manchester coded binary modulation
- //!< Others: Reserved - uint16_t :1; - uint16_t whitenMode:3; //!< \brief 0: No whitening
- //!< 1: CC1101/CC2500 compatible whitening
- //!< 2: PN9 whitening without byte reversal
- //!< 3: Reserved
- //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
- //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
- //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
- //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC - } formatConf; - struct { - uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode:1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_RADIO_DIV_SETUP -//! @{ -#define CMD_PROP_RADIO_DIV_SETUP 0x3807 -//! Proprietary Mode Radio Setup Command for All Frequency Bands -struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_s { - uint16_t commandNo; //!< The command ID number 0x3807 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint16_t modType:3; //!< \brief 0: FSK
- //!< 1: GFSK
- //!< 2: OOK
- //!< Others: Reserved - uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) - uint16_t deviationStepSz:2; //!< \brief Deviation step size
- //!< 0: 250 Hz
- //!< 1: 1000 Hz
- //!< 2: 15.625 Hz
- //!< 3: 62.5 Hz - } modulation; - struct { - uint32_t preScale:8; //!< Prescaler value - uint32_t rateWord:21; //!< Rate word - uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
- //!< 1: Force PDIF decimation to 0
- //!< 3: Force PDIF decimation to 1
- //!< 5: Force PDIF decimation to 2
- //!< Others: Reserved - } symbolRate; //!< Symbol rate setting - uint8_t rxBw; //!< Receiver bandwidth - struct { - uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
- //!< 1--16: Number of preamble bytes
- //!< 18, 20, ..., 30: Number of preamble bytes
- //!< 31: 4 preamble bits
- //!< 32: 32 preamble bytes
- //!< Others: Reserved - uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
- //!< 1: Send 1 as the first preamble bit
- //!< 2: Send same first bit in preamble and sync word
- //!< 3: Send different first bit in preamble and sync word - } preamConf; - struct { - uint16_t nSwBits:6; //!< Number of sync word bits (8--32) - uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
- //!< 1: Use positive deviation for 0 - uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
- //!< 1: Most significant bit transmitted first - uint16_t fecMode:4; //!< \brief Select coding
- //!< 0: Uncoded binary modulation
- //!< 10: Manchester coded binary modulation
- //!< Others: Reserved - uint16_t :1; - uint16_t whitenMode:3; //!< \brief 0: No whitening
- //!< 1: CC1101/CC2500 compatible whitening
- //!< 2: PN9 whitening without byte reversal
- //!< 3: Reserved
- //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
- //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
- //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
- //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC - } formatConf; - struct { - uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode:1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. - uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. - //!< For a single channel RF system, this should be set equal to the RF frequency used. - //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal - //!< to the center frequency of the frequency band used. - int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same - //!< intermediate frequency if supported, otherwise 0.
- //!< 0x8000: Use default. - uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 0, 2, 4, 5, 6, 10, 12, 15, and 30 -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_RX_SNIFF -//! @{ -#define CMD_PROP_RX_SNIFF 0x3808 -//! Proprietary Mode Receive Command with Sniff Mode -struct __RFC_STRUCT rfc_CMD_PROP_RX_SNIFF_s { - uint16_t commandNo; //!< The command ID number 0x3808 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bVarLen:1; //!< \brief 0: Fixed length
- //!< 1: Receive length as first byte - uint8_t bChkAddress:1; //!< \brief 0: No address check
- //!< 1: Check address - uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t :1; - uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord; //!< Sync word to listen for - uint8_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - uint8_t address0; //!< Address - uint8_t address1; //!< \brief Address (set equal to address0 to accept only one address. If 0xFF, accept - //!< 0x00 as well) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure - struct { - uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion - uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion - uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
- //!< 1: Busy if both RSSI and correlation indicates Busy - uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
- //!< 1: End carrier sense on channel Busy
- //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle - uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
- //!< 1: End on channel Idle - uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
- //!< 1: Timeout with channel state Invalid treated as Idle - } csConf; - int8_t rssiThr; //!< RSSI threshold - uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is - //!< declared Idle - uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is - //!< declared Busy - uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods - struct { - uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Idle to Invalid - uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Invalid to Busy - } corrConfig; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } csEndTrigger; //!< Trigger classifier for ending the carrier sense - ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_RX_ADV_SNIFF -//! @{ -#define CMD_PROP_RX_ADV_SNIFF 0x3809 -//! Proprietary Mode Advanced Receive Command with Sniff Mode -struct __RFC_STRUCT rfc_CMD_PROP_RX_ADV_SNIFF_s { - uint16_t commandNo; //!< The command ID number 0x3809 - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint8_t bFsOff:1; //!< \brief 0: Keep frequency synth on after command
- //!< 1: Turn frequency synth off after command - uint8_t bRepeatOk:1; //!< \brief 0: End operation after receiving a packet correctly
- //!< 1: Go back to sync search after receiving a packet correctly - uint8_t bRepeatNok:1; //!< \brief 0: End operation after receiving a packet with CRC error
- //!< 1: Go back to sync search after receiving a packet with CRC error - uint8_t bUseCrc:1; //!< \brief 0: Do not check CRC
- //!< 1: Check CRC - uint8_t bCrcIncSw:1; //!< \brief 0: Do not include sync word in CRC calculation
- //!< 1: Include sync word in CRC calculation - uint8_t bCrcIncHdr:1; //!< \brief 0: Do not include header in CRC calculation
- //!< 1: Include header in CRC calculation - uint8_t endType:1; //!< \brief 0: Packet is received to the end if end trigger happens after sync is obtained
- //!< 1: Packet reception is stopped if end trigger happens - uint8_t filterOp:1; //!< \brief 0: Stop receiver and restart sync search on address mismatch
- //!< 1: Receive packet and mark it as ignored on address mismatch - } pktConf; - struct { - uint8_t bAutoFlushIgnored:1; //!< If 1, automatically discard ignored packets from RX queue - uint8_t bAutoFlushCrcErr:1; //!< If 1, automatically discard packets with CRC error from RX queue - uint8_t :1; - uint8_t bIncludeHdr:1; //!< If 1, include the received header or length byte in the stored packet; otherwise discard it - uint8_t bIncludeCrc:1; //!< If 1, include the received CRC field in the stored packet; otherwise discard it - uint8_t bAppendRssi:1; //!< If 1, append an RSSI byte to the packet in the RX queue - uint8_t bAppendTimestamp:1; //!< If 1, append a timestamp to the packet in the RX queue - uint8_t bAppendStatus:1; //!< If 1, append a status byte to the packet in the RX queue - } rxConf; //!< RX configuration - uint32_t syncWord0; //!< Sync word to listen for - uint32_t syncWord1; //!< Alternative sync word if non-zero - uint16_t maxPktLen; //!< \brief Packet length for fixed length, maximum packet length for variable length
- //!< 0: Unlimited or unknown length - struct { - uint16_t numHdrBits:6; //!< Number of bits in header (0--32) - uint16_t lenPos:5; //!< Position of length field in header (0--31) - uint16_t numLenBits:5; //!< Number of bits in length field (0--16) - } hdrConf; - struct { - uint16_t addrType:1; //!< \brief 0: Address after header
- //!< 1: Address in header - uint16_t addrSize:5; //!< \brief If addrType = 0: Address size in bytes
- //!< If addrType = 1: Address size in bits - uint16_t addrPos:5; //!< \brief If addrType = 1: Bit position of address in header
- //!< If addrType = 0: Non-zero to extend address with sync word identifier - uint16_t numAddr:5; //!< Number of addresses in address list - } addrConf; - int8_t lenOffset; //!< Signed value to add to length field - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } endTrigger; //!< Trigger classifier for ending the operation - ratmr_t endTime; //!< Time used together with endTrigger for ending the operation - uint8_t* pAddr; //!< Pointer to address list - dataQueue_t* pQueue; //!< Pointer to receive queue - uint8_t* pOutput; //!< Pointer to output structure - struct { - uint8_t bEnaRssi:1; //!< If 1, enable RSSI as a criterion - uint8_t bEnaCorr:1; //!< If 1, enable correlation as a criterion - uint8_t operation:1; //!< \brief 0: Busy if either RSSI or correlation indicates Busy
- //!< 1: Busy if both RSSI and correlation indicates Busy - uint8_t busyOp:1; //!< \brief 0: Continue carrier sense on channel Busy
- //!< 1: End carrier sense on channel Busy
- //!< For an RX command, the receiver will continue when carrier sense ends, but it will then not end if channel goes Idle - uint8_t idleOp:1; //!< \brief 0: Continue on channel Idle
- //!< 1: End on channel Idle - uint8_t timeoutRes:1; //!< \brief 0: Timeout with channel state Invalid treated as Busy
- //!< 1: Timeout with channel state Invalid treated as Idle - } csConf; - int8_t rssiThr; //!< RSSI threshold - uint8_t numRssiIdle; //!< \brief Number of consecutive RSSI measurements below the threshold needed before the channel is - //!< declared Idle - uint8_t numRssiBusy; //!< \brief Number of consecutive RSSI measurements above the threshold needed before the channel is - //!< declared Busy - uint16_t corrPeriod; //!< Number of RAT ticks for a correlation observation periods - struct { - uint8_t numCorrInv:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Idle to Invalid - uint8_t numCorrBusy:4; //!< \brief Number of subsequent correlation tops with maximum corrPeriod RAT - //!< ticks between them needed to go from Invalid to Busy - } corrConfig; - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } csEndTrigger; //!< Trigger classifier for ending the carrier sense - ratmr_t csEndTime; //!< Time used together with csEndTrigger for ending the operation -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_RADIO_SETUP_PA -//! @{ -//! Proprietary Mode Radio Setup Command for 2.4 GHz with PA Switching Fields -struct __RFC_STRUCT rfc_CMD_PROP_RADIO_SETUP_PA_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint16_t modType:3; //!< \brief 0: FSK
- //!< 1: GFSK
- //!< 2: OOK
- //!< Others: Reserved - uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) - uint16_t deviationStepSz:2; //!< \brief Deviation step size
- //!< 0: 250 Hz
- //!< 1: 1000 Hz
- //!< 2: 15.625 Hz
- //!< 3: 62.5 Hz - } modulation; - struct { - uint32_t preScale:8; //!< Prescaler value - uint32_t rateWord:21; //!< Rate word - uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
- //!< 1: Force PDIF decimation to 0
- //!< 3: Force PDIF decimation to 1
- //!< 5: Force PDIF decimation to 2
- //!< Others: Reserved - } symbolRate; //!< Symbol rate setting - uint8_t rxBw; //!< Receiver bandwidth - struct { - uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
- //!< 1--16: Number of preamble bytes
- //!< 18, 20, ..., 30: Number of preamble bytes
- //!< 31: 4 preamble bits
- //!< 32: 32 preamble bytes
- //!< Others: Reserved - uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
- //!< 1: Send 1 as the first preamble bit
- //!< 2: Send same first bit in preamble and sync word
- //!< 3: Send different first bit in preamble and sync word - } preamConf; - struct { - uint16_t nSwBits:6; //!< Number of sync word bits (8--32) - uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
- //!< 1: Use positive deviation for 0 - uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
- //!< 1: Most significant bit transmitted first - uint16_t fecMode:4; //!< \brief Select coding
- //!< 0: Uncoded binary modulation
- //!< 10: Manchester coded binary modulation
- //!< Others: Reserved - uint16_t :1; - uint16_t whitenMode:3; //!< \brief 0: No whitening
- //!< 1: CC1101/CC2500 compatible whitening
- //!< 2: PN9 whitening without byte reversal
- //!< 3: Reserved
- //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
- //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
- //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
- //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC - } formatConf; - struct { - uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode:1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. - uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< standard PA. Used by RF driver only, not radio CPU. - uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< 20-dBm PA. Used by RF driver only, not radio CPU. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_RADIO_DIV_SETUP_PA -//! @{ -//! Proprietary Mode Radio Setup Command for All Frequency Bands with PA Switching Fields -struct __RFC_STRUCT rfc_CMD_PROP_RADIO_DIV_SETUP_PA_s { - uint16_t commandNo; //!< The command ID number - uint16_t status; //!< \brief An integer telling the status of the command. This value is - //!< updated by the radio CPU during operation and may be read by the - //!< system CPU at any time. - rfc_radioOp_t *pNextOp; //!< Pointer to the next operation to run after this operation is done - ratmr_t startTime; //!< Absolute or relative start time (depending on the value of startTrigger) - struct { - uint8_t triggerType:4; //!< The type of trigger - uint8_t bEnaCmd:1; //!< \brief 0: No alternative trigger command
- //!< 1: CMD_TRIGGER can be used as an alternative trigger - uint8_t triggerNo:2; //!< The trigger number of the CMD_TRIGGER command that triggers this action - uint8_t pastTrig:1; //!< \brief 0: A trigger in the past is never triggered, or for start of commands, give an error
- //!< 1: A trigger in the past is triggered as soon as possible - } startTrigger; //!< Identification of the trigger that starts the operation - struct { - uint8_t rule:4; //!< Condition for running next command: Rule for how to proceed - uint8_t nSkip:4; //!< Number of skips + 1 if the rule involves skipping. 0: same, 1: next, 2: skip next, ... - } condition; - struct { - uint16_t modType:3; //!< \brief 0: FSK
- //!< 1: GFSK
- //!< 2: OOK
- //!< Others: Reserved - uint16_t deviation:11; //!< Deviation (specified in number of steps, with step size given by deviationStepSz) - uint16_t deviationStepSz:2; //!< \brief Deviation step size
- //!< 0: 250 Hz
- //!< 1: 1000 Hz
- //!< 2: 15.625 Hz
- //!< 3: 62.5 Hz - } modulation; - struct { - uint32_t preScale:8; //!< Prescaler value - uint32_t rateWord:21; //!< Rate word - uint32_t decimMode:3; //!< \brief 0: Use automatic PDIF decimation
- //!< 1: Force PDIF decimation to 0
- //!< 3: Force PDIF decimation to 1
- //!< 5: Force PDIF decimation to 2
- //!< Others: Reserved - } symbolRate; //!< Symbol rate setting - uint8_t rxBw; //!< Receiver bandwidth - struct { - uint8_t nPreamBytes:6; //!< \brief 0: 1 preamble bit
- //!< 1--16: Number of preamble bytes
- //!< 18, 20, ..., 30: Number of preamble bytes
- //!< 31: 4 preamble bits
- //!< 32: 32 preamble bytes
- //!< Others: Reserved - uint8_t preamMode:2; //!< \brief 0: Send 0 as the first preamble bit
- //!< 1: Send 1 as the first preamble bit
- //!< 2: Send same first bit in preamble and sync word
- //!< 3: Send different first bit in preamble and sync word - } preamConf; - struct { - uint16_t nSwBits:6; //!< Number of sync word bits (8--32) - uint16_t bBitReversal:1; //!< \brief 0: Use positive deviation for 1
- //!< 1: Use positive deviation for 0 - uint16_t bMsbFirst:1; //!< \brief 0: Least significant bit transmitted first
- //!< 1: Most significant bit transmitted first - uint16_t fecMode:4; //!< \brief Select coding
- //!< 0: Uncoded binary modulation
- //!< 10: Manchester coded binary modulation
- //!< Others: Reserved - uint16_t :1; - uint16_t whitenMode:3; //!< \brief 0: No whitening
- //!< 1: CC1101/CC2500 compatible whitening
- //!< 2: PN9 whitening without byte reversal
- //!< 3: Reserved
- //!< 4: No whitener, 32-bit IEEE 802.15.4g compatible CRC
- //!< 5: IEEE 802.15.4g compatible whitener and 32-bit CRC
- //!< 6: No whitener, dynamically IEEE 802.15.4g compatible 16-bit or 32-bit CRC
- //!< 7: Dynamically IEEE 802.15.4g compatible whitener and 16-bit or 32-bit CRC - } formatConf; - struct { - uint16_t frontEndMode:3; //!< \brief 0x00: Differential mode
- //!< 0x01: Single-ended mode RFP
- //!< 0x02: Single-ended mode RFN
- //!< 0x05 Single-ended mode RFP with external frontend control on RF pins (RFN and RXTX)
- //!< 0x06 Single-ended mode RFN with external frontend control on RF pins (RFP and RXTX)
- //!< Others: Reserved - uint16_t biasMode:1; //!< \brief 0: Internal bias
- //!< 1: External bias - uint16_t analogCfgMode:6; //!< \brief 0x00: Write analog configuration.
- //!< Required first time after boot and when changing frequency band - //!< or front-end configuration
- //!< 0x2D: Keep analog configuration.
- //!< May be used after standby or when changing mode with the same frequency - //!< band and front-end configuration
- //!< Others: Reserved - uint16_t bNoFsPowerUp:1; //!< \brief 0: Power up frequency synth
- //!< 1: Do not power up frequency synth - } config; //!< Configuration options - uint16_t txPower; //!< Transmit power - uint32_t* pRegOverride; //!< \brief Pointer to a list of hardware and configuration registers to override. If NULL, no - //!< override is used. - uint16_t centerFreq; //!< \brief Center frequency of the frequency band used, in MHz; used for calculating some internal TX and RX parameters. - //!< For a single channel RF system, this should be set equal to the RF frequency used. - //!< For a multi channel RF system (e.g. frequency hopping spread spectrum), this should be set equal - //!< to the center frequency of the frequency band used. - int16_t intFreq; //!< \brief Intermediate frequency to use for RX, in MHz on 4.12 signed format. TX will use same - //!< intermediate frequency if supported, otherwise 0.
- //!< 0x8000: Use default. - uint8_t loDivider; //!< LO frequency divider setting to use. Supported values: 0, 2, 4, 5, 6, 10, 12, 15, and 30 - uint8_t __dummy0; - uint16_t __dummy1; - uint32_t* pRegOverrideTxStd; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< standard PA. Used by RF driver only, not radio CPU. - uint32_t* pRegOverrideTx20; //!< \brief Pointer to a list of hardware and configuration registers to override when switching to - //!< 20-dBm PA. Used by RF driver only, not radio CPU. -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_SET_LEN -//! @{ -#define CMD_PROP_SET_LEN 0x3401 -//! Set Packet Length Command -struct __RFC_STRUCT rfc_CMD_PROP_SET_LEN_s { - uint16_t commandNo; //!< The command ID number 0x3401 - uint16_t rxLen; //!< Payload length to use -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup CMD_PROP_RESTART_RX -//! @{ -#define CMD_PROP_RESTART_RX 0x3402 -//! Restart Packet Command -struct __RFC_STRUCT rfc_CMD_PROP_RESTART_RX_s { - uint16_t commandNo; //!< The command ID number 0x3402 -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup propRxOutput -//! @{ -//! Output structure for RX operations - -struct __RFC_STRUCT rfc_propRxOutput_s { - uint16_t nRxOk; //!< Number of packets that have been received with payload, CRC OK and not ignored - uint16_t nRxNok; //!< Number of packets that have been received with CRC error - uint8_t nRxIgnored; //!< Number of packets that have been received with CRC OK and ignored due to address mismatch - uint8_t nRxStopped; //!< Number of packets not received due to illegal length or address mismatch with pktConf.filterOp = 1 - uint8_t nRxBufFull; //!< Number of packets that have been received and discarded due to lack of buffer space - int8_t lastRssi; //!< RSSI of last received packet - ratmr_t timeStamp; //!< Time stamp of last received packet -} __RFC_STRUCT_ATTR; - -//! @} - -//! \addtogroup propRxStatus -//! @{ -//! Receive status byte that may be appended to message in receive buffer - -struct __RFC_STRUCT rfc_propRxStatus_s { - struct { - uint8_t addressInd:5; //!< Index of address found (0 if not applicable) - uint8_t syncWordId:1; //!< 0 for primary sync word, 1 for alternate sync word - uint8_t result:2; //!< \brief 0: Packet received correctly, not ignored
- //!< 1: Packet received with CRC error
- //!< 2: Packet received correctly, but can be ignored
- //!< 3: Packet reception was aborted - } status; -} __RFC_STRUCT_ATTR; - -//! @} - -//! @} -//! @} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h deleted file mode 100644 index 6819d8c8c46..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rf_prop_mailbox.h +++ /dev/null @@ -1,71 +0,0 @@ -/****************************************************************************** -* Filename: rf_prop_mailbox.h -* Revised: 2018-01-15 15:58:36 +0100 (Mon, 15 Jan 2018) -* Revision: 18171 -* -* Description: Definitions for proprietary mode radio interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _PROP_MAILBOX_H -#define _PROP_MAILBOX_H - -/// \name Radio operation status -///@{ -/// \name Operation finished normally -///@{ -#define PROP_DONE_OK 0x3400 ///< Operation ended normally -#define PROP_DONE_RXTIMEOUT 0x3401 ///< Operation stopped after end trigger while waiting for sync -#define PROP_DONE_BREAK 0x3402 ///< Rx stopped due to timeout in the middle of a packet -#define PROP_DONE_ENDED 0x3403 ///< Operation stopped after end trigger during reception -#define PROP_DONE_STOPPED 0x3404 ///< Operation stopped after stop command -#define PROP_DONE_ABORT 0x3405 ///< Operation aborted by abort command -#define PROP_DONE_RXERR 0x3406 ///< Operation ended after receiving packet with CRC error -#define PROP_DONE_IDLE 0x3407 ///< Carrier sense operation ended because of idle channel -#define PROP_DONE_BUSY 0x3408 ///< Carrier sense operation ended because of busy channel -#define PROP_DONE_IDLETIMEOUT 0x3409 ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 1 -#define PROP_DONE_BUSYTIMEOUT 0x340A ///< Carrier sense operation ended because of timeout with csConf.timeoutRes = 0 - -///@} -/// \name Operation finished with error -///@{ -#define PROP_ERROR_PAR 0x3800 ///< Illegal parameter -#define PROP_ERROR_RXBUF 0x3801 ///< No available Rx buffer at the start of a packet -#define PROP_ERROR_RXFULL 0x3802 ///< Out of Rx buffer during reception in a partial read buffer -#define PROP_ERROR_NO_SETUP 0x3803 ///< Radio was not set up in proprietary mode -#define PROP_ERROR_NO_FS 0x3804 ///< Synth was not programmed when running Rx or Tx -#define PROP_ERROR_RXOVF 0x3805 ///< Rx overflow observed during operation -#define PROP_ERROR_TXUNF 0x3806 ///< Tx underflow observed during operation -///@} -///@} - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.c deleted file mode 100644 index 474768506e5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.c +++ /dev/null @@ -1,295 +0,0 @@ -/****************************************************************************** -* Filename: rfc.c -* Revised: 2018-08-08 11:04:37 +0200 (Wed, 08 Aug 2018) -* Revision: 52334 -* -* Description: Driver for the RF Core. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "rfc.h" -#include "rf_mailbox.h" -#include - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef RFCCpeIntGetAndClear - #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear - #undef RFCDoorbellSendTo - #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo - #undef RFCSynthPowerDown - #define RFCSynthPowerDown NOROM_RFCSynthPowerDown - #undef RFCCpePatchReset - #define RFCCpePatchReset NOROM_RFCCpePatchReset - #undef RFCOverrideSearch - #define RFCOverrideSearch NOROM_RFCOverrideSearch - #undef RFCOverrideUpdate - #define RFCOverrideUpdate NOROM_RFCOverrideUpdate - #undef RFCHwIntGetAndClear - #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear - #undef RFCAnaDivTxOverride - #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride -#endif - - -//***************************************************************************** -// -// Get and clear CPE interrupt flags which match the provided bitmask -// -//***************************************************************************** -uint32_t -RFCCpeIntGetAndClear(uint32_t ui32Mask) -{ - // Read the CPE interrupt flags which match the provided bitmask - uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) & ui32Mask; - - // Clear the interrupt flags - RFCCpeIntClear(ui32Ifg); - - // Return with the interrupt flags - return (ui32Ifg); -} - - -//***************************************************************************** -// -// Send a radio operation to the doorbell and wait for an acknowledgement -// -//***************************************************************************** -uint32_t -RFCDoorbellSendTo(uint32_t pOp) -{ - // Wait until the doorbell becomes available - while(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) != 0); - RFCAckIntClear(); - - // Submit the command to the CM0 through the doorbell - HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDR) = pOp; - - // Wait until the CM0 starts to parse the command - while(!HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG)); - RFCAckIntClear(); - - // Return with the content of status register - return(HWREG(RFC_DBELL_BASE + RFC_DBELL_O_CMDSTA)); -} - - -//***************************************************************************** -// -// Turn off the RF synthesizer. The radio will no longer respond to commands! -// -//***************************************************************************** -void -RFCSynthPowerDown(void) -{ - // Definition of reserved words - const uint32_t RFC_RESERVED0 = 0x40046054; - const uint32_t RFC_RESERVED1 = 0x40046060; - const uint32_t RFC_RESERVED2 = 0x40046058; - const uint32_t RFC_RESERVED3 = 0x40044100; - - // Disable CPE clock, enable FSCA clock. - HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = (HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) - & ~RFC_PWR_PWMCLKEN_CPE_M) | RFC_PWR_PWMCLKEN_FSCA_M | RFC_PWR_PWMCLKEN_RFE_M; - - HWREG(RFC_RESERVED0) = 3; - HWREG(RFC_RESERVED1) = 0x1030; - HWREG(RFC_RESERVED2) = 1; - HWREG(RFC_RESERVED1) = 0x50; - HWREG(RFC_RESERVED2) = 1; - HWREG(RFC_RESERVED1) = 0x650; - HWREG(RFC_RESERVED2) = 1; - HWREG(RFC_RESERVED1) = 0x10C0; - HWREG(RFC_RESERVED2) = 1; - HWREG(RFC_RESERVED3) = 1; -} - - -//***************************************************************************** -// -// Reset previously patched CPE RAM to a state where it can be patched again -// -//***************************************************************************** -void -RFCCpePatchReset(void) -{ - // Function is not complete -} - - -//***************************************************************************** -// -// Function to search an override list for the provided pattern within the search depth. -// -//***************************************************************************** -uint8_t -RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth) -{ - // Search from start of the override list, to look for first override entry that matches search pattern - uint8_t override_index; - for(override_index = 0; (override_index < searchDepth) && (pOverride[override_index] != END_OVERRIDE); override_index++) - { - // Compare the value to the given pattern - if((pOverride[override_index] & mask) == pattern) - { - // Return with the index of override in case of match - return override_index; - } - } - - // Return with an invalid index - return 0xFF; -} - -//***************************************************************************** -// -// Function to calculate the proper override run-time for the High Gain PA. -// -//***************************************************************************** -uint32_t -RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode) -{ - uint16_t fsOnly; - uint16_t txSetting; - - switch (loDivider) - { - case 0: fsOnly = 0x0502; - break; - case 2: - fsOnly = 0x0102; - break; - case 4: - case 6: - case 12: - fsOnly = 0xF101; - break; - case 5: - case 10: - case 15: - case 30: - fsOnly = 0x1101; - break; - default: - // Error, should not occur! - fsOnly = 0; - break; - } - - if (frontEndMode == 255) - { - // Special value meaning 20 dBm PA - txSetting = (fsOnly | 0x00C0) & ~0x0400; - } - else if (frontEndMode == 0) - { - // Differential - txSetting = fsOnly | 0x0030; - } - else if (frontEndMode & 1) - { - // Single ended on RFP - txSetting = fsOnly | 0x0010; - } - else - { - // Single ended on RFN - txSetting = fsOnly | 0x0020; - } - - return ((((uint32_t) txSetting) << 16) | RFC_FE_OVERRIDE_ADDRESS); -} - -//***************************************************************************** -// -// Update the override list based on values stored in FCFG1 -// -//***************************************************************************** -uint8_t -RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams) -{ - // Function is left blank for compatibility reasons. - return 0; -} - - -//***************************************************************************** -// -// Get and clear HW interrupt flags -// -//***************************************************************************** -uint32_t -RFCHwIntGetAndClear(uint32_t ui32Mask) -{ - // Read the CPE interrupt flags which match the provided bitmask - uint32_t ui32Ifg = HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) & ui32Mask; - - // Clear the interupt flags - RFCHwIntClear(ui32Ifg); - - // Return with the interrupt flags - return (ui32Ifg); -} - - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef RFCCpeIntGetAndClear - #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear - #undef RFCDoorbellSendTo - #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo - #undef RFCSynthPowerDown - #define RFCSynthPowerDown NOROM_RFCSynthPowerDown - #undef RFCCpePatchReset - #define RFCCpePatchReset NOROM_RFCCpePatchReset - #undef RFCOverrideSearch - #define RFCOverrideSearch NOROM_RFCOverrideSearch - #undef RFCOverrideUpdate - #define RFCOverrideUpdate NOROM_RFCOverrideUpdate - #undef RFCHwIntGetAndClear - #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear - #undef RFCAnaDivTxOverride - #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride -#endif - -// See rfc.h for implementation diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h deleted file mode 100644 index 00d8f188cd8..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rfc.h +++ /dev/null @@ -1,465 +0,0 @@ -/****************************************************************************** -* Filename: rfc.h -* Revised: 2018-08-08 14:03:25 +0200 (Wed, 08 Aug 2018) -* Revision: 52338 -* -* Description: Defines and prototypes for the RF Core. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup rfc_api -//! @{ -// -//***************************************************************************** - -#ifndef __RFC_H__ -#define __RFC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_rfc_pwr.h" -#include "../inc/hw_rfc_dbell.h" -#include "../inc/hw_fcfg1.h" -#include "../inc/hw_adi_3_refsys.h" -#include "../inc/hw_adi.h" -#include "rf_common_cmd.h" -#include "rf_prop_cmd.h" -#include "rf_ble_cmd.h" - -// Definition of RFTRIM container -typedef struct { - uint32_t configIfAdc; - uint32_t configRfFrontend; - uint32_t configSynth; - uint32_t configMiscAdc; -} rfTrim_t; - -// Definition of maximum search depth used by the RFCOverrideUpdate function -#define RFC_MAX_SEARCH_DEPTH 5 -#define RFC_PA_TYPE_ADDRESS 0x21000345 -#define RFC_PA_TYPE_MASK 0x04 -#define RFC_PA_GAIN_ADDRESS 0x2100034C -#define RFC_PA_GAIN_MASK 0x003FFFFF -#define RFC_FE_MODE_ESCAPE_VALUE 0xFF -#define RFC_FE_OVERRIDE_ADDRESS 0x0703 -#define RFC_FE_OVERRIDE_MASK 0x0000FFFF - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define RFCCpeIntGetAndClear NOROM_RFCCpeIntGetAndClear - #define RFCDoorbellSendTo NOROM_RFCDoorbellSendTo - #define RFCSynthPowerDown NOROM_RFCSynthPowerDown - #define RFCCpePatchReset NOROM_RFCCpePatchReset - #define RFCOverrideSearch NOROM_RFCOverrideSearch - #define RFCOverrideUpdate NOROM_RFCOverrideUpdate - #define RFCHwIntGetAndClear NOROM_RFCHwIntGetAndClear - #define RFCAnaDivTxOverride NOROM_RFCAnaDivTxOverride -#endif - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Enable the RF core clocks. -//! -//! As soon as the RF core is started it will handle clock control -//! autonomously. No check should be performed to check the clocks. Instead -//! the radio can be ping'ed through the command interface. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -RFCClockEnable(void) -{ - // Enable basic clocks to get the CPE run - HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = RFC_PWR_PWMCLKEN_CPERAM - | RFC_PWR_PWMCLKEN_CPE - | RFC_PWR_PWMCLKEN_RFC; -} - - -//***************************************************************************** -// -//! \brief Disable the RF core clocks. -//! -//! As soon as the RF core is started it will handle clock control -//! autonomously. No check should be performed to check the clocks. Instead -//! the radio can be ping'ed through the command interface. -//! -//! When disabling clocks it is the programmers responsibility that the -//! RF core clocks are safely gated. I.e. the RF core should be safely -//! 'parked'. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -RFCClockDisable(void) -{ - // Disable all clocks - HWREG(RFC_PWR_NONBUF_BASE + RFC_PWR_O_PWMCLKEN) = 0x0; -} - - -//***************************************************************************** -// -//! Clear HW interrupt flags -// -//***************************************************************************** -__STATIC_INLINE void -RFCCpeIntClear(uint32_t ui32Mask) -{ - // Clear the masked pending interrupts. - HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIFG) = ~ui32Mask; -} - - -//***************************************************************************** -// -//! Clear CPE interrupt flags. -// -//***************************************************************************** -__STATIC_INLINE void -RFCHwIntClear(uint32_t ui32Mask) -{ - // Clear the masked pending interrupts. - HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIFG) = ~ui32Mask; -} - - -//***************************************************************************** -// -//! Select interrupt sources to CPE0 (assign to INT_RFC_CPE_0 interrupt vector). -// -//***************************************************************************** -__STATIC_INLINE void -RFCCpe0IntSelect(uint32_t ui32Mask) -{ - // Multiplex RF Core interrupts to CPE0 IRQ. - HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) &= ~ui32Mask; -} - - -//***************************************************************************** -// -//! Select interrupt sources to CPE1 (assign to INT_RFC_CPE_1 interrupt vector). -// -//***************************************************************************** -__STATIC_INLINE void -RFCCpe1IntSelect(uint32_t ui32Mask) -{ - // Multiplex RF Core interrupts to CPE1 IRQ. - HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEISL) |= ui32Mask; -} - - -//***************************************************************************** -// -//! Enable CPEx interrupt sources. -// -//***************************************************************************** -__STATIC_INLINE void -RFCCpeIntEnable(uint32_t ui32Mask) -{ - // Enable CPE interrupts from RF Core. - HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) |= ui32Mask; -} - - -//***************************************************************************** -// -//! Select, clear, and enable interrupt sources to CPE0. -// -//***************************************************************************** -__STATIC_INLINE void -RFCCpe0IntSelectClearEnable(uint32_t ui32Mask) -{ - // Multiplex RF Core interrupts to CPE0 IRQ. - RFCCpe0IntSelect(ui32Mask); - - // Clear the masked interrupts. - RFCCpeIntClear(ui32Mask); - - // Enable the masked interrupts. - RFCCpeIntEnable(ui32Mask); -} - - -//***************************************************************************** -// -//! Select, clear, and enable interrupt sources to CPE1. -// -//***************************************************************************** -__STATIC_INLINE void -RFCCpe1IntSelectClearEnable(uint32_t ui32Mask) -{ - // Multiplex RF Core interrupts to CPE1 IRQ. - RFCCpe1IntSelect(ui32Mask); - - // Clear the masked interrupts. - RFCCpeIntClear(ui32Mask); - - // Enable the masked interrupts. - RFCCpeIntEnable(ui32Mask); -} - - -//***************************************************************************** -// -//! Enable HW interrupt sources. -// -//***************************************************************************** -__STATIC_INLINE void -RFCHwIntEnable(uint32_t ui32Mask) -{ - // Enable the masked interrupts - HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) |= ui32Mask; -} - - -//***************************************************************************** -// -//! Disable CPE interrupt sources. -// -//***************************************************************************** -__STATIC_INLINE void -RFCCpeIntDisable(uint32_t ui32Mask) -{ - // Disable the masked interrupts - HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFCPEIEN) &= ~ui32Mask; -} - - -//***************************************************************************** -// -//! Disable HW interrupt sources. -// -//***************************************************************************** -__STATIC_INLINE void -RFCHwIntDisable(uint32_t ui32Mask) -{ - // Disable the masked interrupts - HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFHWIEN) &= ~ui32Mask; -} - - -//***************************************************************************** -// -//! Get and clear CPE interrupt flags. -// -//***************************************************************************** -extern uint32_t RFCCpeIntGetAndClear(uint32_t ui32Mask); - - -//***************************************************************************** -// -//! Clear ACK interrupt flag. -// -//***************************************************************************** -__STATIC_INLINE void -RFCAckIntClear(void) -{ - // Clear any pending interrupts. - HWREG(RFC_DBELL_BASE + RFC_DBELL_O_RFACKIFG) = 0x0; -} - - -//***************************************************************************** -// -//! Send a radio operation to the doorbell and wait for an acknowledgment. -// -//***************************************************************************** -extern uint32_t RFCDoorbellSendTo(uint32_t pOp); - - -//***************************************************************************** -// -//! This function implements a fast way to turn off the synthesizer. -// -//***************************************************************************** -extern void RFCSynthPowerDown(void); - - -//***************************************************************************** -// -//! Reset previously patched CPE RAM to a state where it can be patched again. -// -//***************************************************************************** -extern void RFCCpePatchReset(void); - - -//***************************************************************************** -// -// Function to search an override list for the provided pattern within the search depth. -// -//***************************************************************************** -extern uint8_t RFCOverrideSearch(const uint32_t *pOverride, const uint32_t pattern, const uint32_t mask, const uint8_t searchDepth); - - -//***************************************************************************** -// -//! Function to update override list -// -//***************************************************************************** -extern uint8_t RFCOverrideUpdate(rfc_radioOp_t *pOpSetup, uint32_t *pParams); - - -//***************************************************************************** -// -//! Get and clear HW interrupt flags. -// -//***************************************************************************** -extern uint32_t RFCHwIntGetAndClear(uint32_t ui32Mask); - - -//***************************************************************************** -// -//! Get the type of currently selected PA. -// -//***************************************************************************** -__STATIC_INLINE bool -RFCGetPaType(void) -{ - return (bool)(HWREGB(RFC_PA_TYPE_ADDRESS) & RFC_PA_TYPE_MASK); -} - -//***************************************************************************** -// -//! Get the gain of currently selected PA. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -RFCGetPaGain(void) -{ - return (HWREG(RFC_PA_GAIN_ADDRESS) & RFC_PA_GAIN_MASK); -} - - -//***************************************************************************** -// -//! Function to calculate the proper override run-time for the High Gain PA. -// -//***************************************************************************** -extern uint32_t RFCAnaDivTxOverride(uint8_t loDivider, uint8_t frontEndMode); - - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_RFCCpeIntGetAndClear - #undef RFCCpeIntGetAndClear - #define RFCCpeIntGetAndClear ROM_RFCCpeIntGetAndClear - #endif - #ifdef ROM_RFCDoorbellSendTo - #undef RFCDoorbellSendTo - #define RFCDoorbellSendTo ROM_RFCDoorbellSendTo - #endif - #ifdef ROM_RFCSynthPowerDown - #undef RFCSynthPowerDown - #define RFCSynthPowerDown ROM_RFCSynthPowerDown - #endif - #ifdef ROM_RFCCpePatchReset - #undef RFCCpePatchReset - #define RFCCpePatchReset ROM_RFCCpePatchReset - #endif - #ifdef ROM_RFCOverrideSearch - #undef RFCOverrideSearch - #define RFCOverrideSearch ROM_RFCOverrideSearch - #endif - #ifdef ROM_RFCOverrideUpdate - #undef RFCOverrideUpdate - #define RFCOverrideUpdate ROM_RFCOverrideUpdate - #endif - #ifdef ROM_RFCHwIntGetAndClear - #undef RFCHwIntGetAndClear - #define RFCHwIntGetAndClear ROM_RFCHwIntGetAndClear - #endif - #ifdef ROM_RFCAnaDivTxOverride - #undef RFCAnaDivTxOverride - #define RFCAnaDivTxOverride ROM_RFCAnaDivTxOverride - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __RFC_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h deleted file mode 100644 index fc79556d788..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom.h +++ /dev/null @@ -1,1055 +0,0 @@ -/****************************************************************************** -* Filename: rom.h -* Revised: 2018-11-02 13:54:49 +0100 (Fri, 02 Nov 2018) -* Revision: 53196 -* -* Description: Prototypes for the ROM utility functions. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __ROM_H__ -#define __ROM_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include "../inc/hw_types.h" - -#ifndef __HAPI_H__ -#define __HAPI_H__ - -// Start address of the ROM hard API access table (located after the ROM FW rev field) -#define ROM_HAPI_TABLE_ADDR 0x10000048 - -// ROM Hard-API function interface types -typedef uint32_t (* FPTR_CRC32_T) ( uint8_t* /* pui8Data */,\ - uint32_t /* ui32ByteCount */,\ - uint32_t /* ui32RepeatCount */); - -typedef uint32_t (* FPTR_GETFLSIZE_T) ( void ); - -typedef uint32_t (* FPTR_GETCHIPID_T) ( void ); - -typedef uint32_t (* FPTR_RESERVED1_T) ( uint32_t ); - -typedef uint32_t (* FPTR_RESERVED2_T) ( void ); - -typedef uint32_t (* FPTR_RESERVED3_T) ( uint8_t* ,\ - uint32_t ,\ - uint32_t ); -typedef void (* FPTR_RESETDEV_T) ( void ); - -typedef uint32_t (* FPTR_FLETCHER32_T) ( uint16_t* /* pui16Data */,\ - uint16_t /* ui16WordCount */,\ - uint16_t /* ui16RepeatCount */); - -typedef uint32_t (* FPTR_MINVAL_T) ( uint32_t* /* ulpDataBuffer */,\ - uint32_t /* ui32DataCount */); - -typedef uint32_t (* FPTR_MAXVAL_T) ( uint32_t* /* pui32DataBuffer */,\ - uint32_t /* ui32DataCount */); - -typedef uint32_t (* FPTR_MEANVAL_T) ( uint32_t* /* pui32DataBuffer */,\ - uint32_t /* ui32DataCount */); - -typedef uint32_t (* FPTR_STDDVAL_T) ( uint32_t* /* pui32DataBuffer */,\ - uint32_t /* ui32DataCount */); - -typedef void (* FPTR_HFSOURCESAFESWITCH_T) ( void ); - -typedef void (* FPTR_RESERVED4_T) ( uint32_t ); - -typedef void (* FPTR_RESERVED5_T) ( uint32_t ); - -typedef void (* FPTR_COMPAIN_T) ( uint8_t /* ut8Signal */); - -typedef void (* FPTR_COMPAREF_T) ( uint8_t /* ut8Signal */); - -typedef void (* FPTR_ADCCOMPBIN_T) ( uint8_t /* ut8Signal */); - -typedef void (* FPTR_DACVREF_T) ( uint8_t /* ut8Signal */); - -extern uint32_t MemBusWrkAroundHapiProgramFlash(uint8_t *pui8DataBuffer, - uint32_t ui32Address, - uint32_t ui32Count); - -extern uint32_t MemBusWrkAroundHapiEraseSector(uint32_t ui32Address); - -// ROM Hard-API access table type -typedef struct -{ - FPTR_CRC32_T Crc32; - FPTR_GETFLSIZE_T FlashGetSize; - FPTR_GETCHIPID_T GetChipId; - FPTR_RESERVED1_T ReservedLocation1; - FPTR_RESERVED2_T ReservedLocation2; - FPTR_RESERVED3_T ReservedLocation3; - FPTR_RESETDEV_T ResetDevice; - FPTR_FLETCHER32_T Fletcher32; - FPTR_MINVAL_T MinValue; - FPTR_MAXVAL_T MaxValue; - FPTR_MEANVAL_T MeanValue; - FPTR_STDDVAL_T StandDeviationValue; - FPTR_RESERVED4_T ReservedLocation4; - FPTR_RESERVED5_T ReservedLocation5; - FPTR_HFSOURCESAFESWITCH_T HFSourceSafeSwitch; - FPTR_COMPAIN_T SelectCompAInput; - FPTR_COMPAREF_T SelectCompARef; - FPTR_ADCCOMPBIN_T SelectADCCompBInput; - FPTR_DACVREF_T SelectDACVref; -} HARD_API_T; - -// Pointer to the ROM HAPI table -#define P_HARD_API ((HARD_API_T*) ROM_HAPI_TABLE_ADDR) - -#define HapiCrc32(a,b,c) P_HARD_API->Crc32(a,b,c) -#define HapiGetFlashSize() P_HARD_API->FlashGetSize() -#define HapiGetChipId() P_HARD_API->GetChipId() -#define HapiSectorErase(a) MemBusWrkAroundHapiEraseSector(a) -#define HapiProgramFlash(a,b,c) MemBusWrkAroundHapiProgramFlash(a,b,c) -#define HapiResetDevice() P_HARD_API->ResetDevice() -#define HapiFletcher32(a,b,c) P_HARD_API->Fletcher32(a,b,c) -#define HapiMinValue(a,b) P_HARD_API->MinValue(a,b) -#define HapiMaxValue(a,b) P_HARD_API->MaxValue(a,b) -#define HapiMeanValue(a,b) P_HARD_API->MeanValue(a,b) -#define HapiStandDeviationValue(a,b) P_HARD_API->StandDeviationValue(a,b) -#define HapiHFSourceSafeSwitch() P_HARD_API->HFSourceSafeSwitch() -#define HapiSelectCompAInput(a) P_HARD_API->SelectCompAInput(a) -#define HapiSelectCompARef(a) P_HARD_API->SelectCompARef(a) -#define HapiSelectADCCompBInput(a) P_HARD_API->SelectADCCompBInput(a) -#define HapiSelectDACVref(a) P_HARD_API->SelectDACVref(a) - -// Defines for input parameter to the HapiSelectCompAInput function. -#define COMPA_IN_NC 0x00 -// Defines used in CC13x0/CC26x0 devices -#define COMPA_IN_AUXIO7 0x09 -#define COMPA_IN_AUXIO6 0x0A -#define COMPA_IN_AUXIO5 0x0B -#define COMPA_IN_AUXIO4 0x0C -#define COMPA_IN_AUXIO3 0x0D -#define COMPA_IN_AUXIO2 0x0E -#define COMPA_IN_AUXIO1 0x0F -#define COMPA_IN_AUXIO0 0x10 -// Defines used in CC13x2/CC26x2 devices -#define COMPA_IN_AUXIO26 COMPA_IN_AUXIO7 -#define COMPA_IN_AUXIO25 COMPA_IN_AUXIO6 -#define COMPA_IN_AUXIO24 COMPA_IN_AUXIO5 -#define COMPA_IN_AUXIO23 COMPA_IN_AUXIO4 -#define COMPA_IN_AUXIO22 COMPA_IN_AUXIO3 -#define COMPA_IN_AUXIO21 COMPA_IN_AUXIO2 -#define COMPA_IN_AUXIO20 COMPA_IN_AUXIO1 -#define COMPA_IN_AUXIO19 COMPA_IN_AUXIO0 - -// Defines for input parameter to the HapiSelectCompARef function. -#define COMPA_REF_NC 0x00 -#define COMPA_REF_DCOUPL 0x01 -#define COMPA_REF_VSS 0x02 -#define COMPA_REF_VDDS 0x03 -#define COMPA_REF_ADCVREFP 0x04 -// Defines used in CC13x0/CC26x0 devices -#define COMPA_REF_AUXIO7 0x09 -#define COMPA_REF_AUXIO6 0x0A -#define COMPA_REF_AUXIO5 0x0B -#define COMPA_REF_AUXIO4 0x0C -#define COMPA_REF_AUXIO3 0x0D -#define COMPA_REF_AUXIO2 0x0E -#define COMPA_REF_AUXIO1 0x0F -#define COMPA_REF_AUXIO0 0x10 -// Defines used in CC13x2/CC26x2 devices -#define COMPA_REF_AUXIO26 COMPA_REF_AUXIO7 -#define COMPA_REF_AUXIO25 COMPA_REF_AUXIO6 -#define COMPA_REF_AUXIO24 COMPA_REF_AUXIO5 -#define COMPA_REF_AUXIO23 COMPA_REF_AUXIO4 -#define COMPA_REF_AUXIO22 COMPA_REF_AUXIO3 -#define COMPA_REF_AUXIO21 COMPA_REF_AUXIO2 -#define COMPA_REF_AUXIO20 COMPA_REF_AUXIO1 -#define COMPA_REF_AUXIO19 COMPA_REF_AUXIO0 - -// Defines for input parameter to the HapiSelectADCCompBInput function. -#define ADC_COMPB_IN_NC 0x00 -#define ADC_COMPB_IN_DCOUPL 0x03 -#define ADC_COMPB_IN_VSS 0x04 -#define ADC_COMPB_IN_VDDS 0x05 -// Defines used in CC13x0/CC26x0 devices -#define ADC_COMPB_IN_AUXIO7 0x09 -#define ADC_COMPB_IN_AUXIO6 0x0A -#define ADC_COMPB_IN_AUXIO5 0x0B -#define ADC_COMPB_IN_AUXIO4 0x0C -#define ADC_COMPB_IN_AUXIO3 0x0D -#define ADC_COMPB_IN_AUXIO2 0x0E -#define ADC_COMPB_IN_AUXIO1 0x0F -#define ADC_COMPB_IN_AUXIO0 0x10 -// Defines used in CC13x2/CC26x2 devices -#define ADC_COMPB_IN_AUXIO26 ADC_COMPB_IN_AUXIO7 -#define ADC_COMPB_IN_AUXIO25 ADC_COMPB_IN_AUXIO6 -#define ADC_COMPB_IN_AUXIO24 ADC_COMPB_IN_AUXIO5 -#define ADC_COMPB_IN_AUXIO23 ADC_COMPB_IN_AUXIO4 -#define ADC_COMPB_IN_AUXIO22 ADC_COMPB_IN_AUXIO3 -#define ADC_COMPB_IN_AUXIO21 ADC_COMPB_IN_AUXIO2 -#define ADC_COMPB_IN_AUXIO20 ADC_COMPB_IN_AUXIO1 -#define ADC_COMPB_IN_AUXIO19 ADC_COMPB_IN_AUXIO0 - -// Defines for input parameter to the HapiSelectDACVref function. -// The define values can not be changed! -#define DAC_REF_NC 0x00 -#define DAC_REF_DCOUPL 0x01 -#define DAC_REF_VSS 0x02 -#define DAC_REF_VDDS 0x03 - -#endif // __HAPI_H__ - -//***************************************************************************** -// -// Pointers to the main API tables. -// -//***************************************************************************** -#define ROM_API_TABLE ((uint32_t *) 0x10000180) -#define ROM_VERSION (ROM_API_TABLE[0]) - - -#define ROM_API_AON_EVENT_TABLE ((uint32_t*) (ROM_API_TABLE[1])) -#define ROM_API_AON_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[2])) -#define ROM_API_AON_RTC_TABLE ((uint32_t*) (ROM_API_TABLE[3])) -#define ROM_API_AUX_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[5])) -#define ROM_API_AUX_TDC_TABLE ((uint32_t*) (ROM_API_TABLE[6])) -#define ROM_API_DDI_TABLE ((uint32_t*) (ROM_API_TABLE[9])) -#define ROM_API_FLASH_TABLE ((uint32_t*) (ROM_API_TABLE[10])) -#define ROM_API_I2C_TABLE ((uint32_t*) (ROM_API_TABLE[11])) -#define ROM_API_INTERRUPT_TABLE ((uint32_t*) (ROM_API_TABLE[12])) -#define ROM_API_IOC_TABLE ((uint32_t*) (ROM_API_TABLE[13])) -#define ROM_API_PRCM_TABLE ((uint32_t*) (ROM_API_TABLE[14])) -#define ROM_API_SMPH_TABLE ((uint32_t*) (ROM_API_TABLE[15])) -#define ROM_API_SSI_TABLE ((uint32_t*) (ROM_API_TABLE[17])) -#define ROM_API_TIMER_TABLE ((uint32_t*) (ROM_API_TABLE[18])) -#define ROM_API_TRNG_TABLE ((uint32_t*) (ROM_API_TABLE[19])) -#define ROM_API_UART_TABLE ((uint32_t*) (ROM_API_TABLE[20])) -#define ROM_API_UDMA_TABLE ((uint32_t*) (ROM_API_TABLE[21])) -#define ROM_API_VIMS_TABLE ((uint32_t*) (ROM_API_TABLE[22])) -#define ROM_API_CRYPTO_TABLE ((uint32_t*) (ROM_API_TABLE[23])) -#define ROM_API_OSC_TABLE ((uint32_t*) (ROM_API_TABLE[24])) -#define ROM_API_AUX_ADC_TABLE ((uint32_t*) (ROM_API_TABLE[25])) -#define ROM_API_SYS_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[26])) -#define ROM_API_AON_BATMON_TABLE ((uint32_t*) (ROM_API_TABLE[27])) -#define ROM_API_SETUP_ROM_TABLE ((uint32_t*) (ROM_API_TABLE[28])) -#define ROM_API_I2S_TABLE ((uint32_t*) (ROM_API_TABLE[29])) -#define ROM_API_PWR_CTRL_TABLE ((uint32_t*) (ROM_API_TABLE[30])) -#define ROM_API_AES_TABLE ((uint32_t*) (ROM_API_TABLE[31])) -#define ROM_API_PKA_TABLE ((uint32_t*) (ROM_API_TABLE[32])) -#define ROM_API_SHA2_TABLE ((uint32_t*) (ROM_API_TABLE[33])) - -// AON_EVENT FUNCTIONS -#define ROM_AONEventMcuWakeUpSet \ - ((void (*)(uint32_t ui32MCUWUEvent, uint32_t ui32EventSrc)) \ - ROM_API_AON_EVENT_TABLE[0]) - -#define ROM_AONEventMcuWakeUpGet \ - ((uint32_t (*)(uint32_t ui32MCUWUEvent)) \ - ROM_API_AON_EVENT_TABLE[1]) - -#define ROM_AONEventMcuSet \ - ((void (*)(uint32_t ui32MCUEvent, uint32_t ui32EventSrc)) \ - ROM_API_AON_EVENT_TABLE[4]) - -#define ROM_AONEventMcuGet \ - ((uint32_t (*)(uint32_t ui32MCUEvent)) \ - ROM_API_AON_EVENT_TABLE[5]) - - -// AON_RTC FUNCTIONS -#define ROM_AONRTCCurrent64BitValueGet \ - ((uint64_t (*)(void)) \ - ROM_API_AON_RTC_TABLE[12]) - - -// AUX_TDC FUNCTIONS -#define ROM_AUXTDCConfigSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32StartCondition, uint32_t ui32StopCondition)) \ - ROM_API_AUX_TDC_TABLE[0]) - -#define ROM_AUXTDCMeasurementDone \ - ((uint32_t (*)(uint32_t ui32Base)) \ - ROM_API_AUX_TDC_TABLE[1]) - - -// DDI FUNCTIONS -#define ROM_DDI16BitWrite \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32WrData)) \ - ROM_API_DDI_TABLE[0]) - -#define ROM_DDI16BitfieldWrite \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift, uint16_t ui32Data)) \ - ROM_API_DDI_TABLE[1]) - -#define ROM_DDI16BitRead \ - ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask)) \ - ROM_API_DDI_TABLE[2]) - -#define ROM_DDI16BitfieldRead \ - ((uint16_t (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Mask, uint32_t ui32Shift)) \ - ROM_API_DDI_TABLE[3]) - -#define ROM_DDI32RegWrite \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Reg, uint32_t ui32Val)) \ - ROM_API_DDI_TABLE[4]) - - -// FLASH FUNCTIONS -#define ROM_FlashPowerModeSet \ - ((void (*)(uint32_t ui32PowerMode, uint32_t ui32BankGracePeriod, uint32_t ui32PumpGracePeriod)) \ - ROM_API_FLASH_TABLE[0]) - -#define ROM_FlashPowerModeGet \ - ((uint32_t (*)(void)) \ - ROM_API_FLASH_TABLE[1]) - -#define ROM_FlashProtectionSet \ - ((void (*)(uint32_t ui32SectorAddress, uint32_t ui32ProtectMode)) \ - ROM_API_FLASH_TABLE[2]) - -#define ROM_FlashProtectionGet \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ - ROM_API_FLASH_TABLE[3]) - -#define ROM_FlashProtectionSave \ - ((uint32_t (*)(uint32_t ui32SectorAddress)) \ - ROM_API_FLASH_TABLE[4]) - -#define ROM_FlashEfuseReadRow \ - ((bool (*)(uint32_t *pui32EfuseData, uint32_t ui32RowAddress)) \ - ROM_API_FLASH_TABLE[8]) - -#define ROM_FlashDisableSectorsForWrite \ - ((void (*)(void)) \ - ROM_API_FLASH_TABLE[9]) - - -// I2C FUNCTIONS -#define ROM_I2CMasterInitExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32I2CClk, bool bFast)) \ - ROM_API_I2C_TABLE[0]) - -#define ROM_I2CMasterErr \ - ((uint32_t (*)(uint32_t ui32Base)) \ - ROM_API_I2C_TABLE[1]) - - -// INTERRUPT FUNCTIONS -#define ROM_IntPriorityGroupingSet \ - ((void (*)(uint32_t ui32Bits)) \ - ROM_API_INTERRUPT_TABLE[0]) - -#define ROM_IntPriorityGroupingGet \ - ((uint32_t (*)(void)) \ - ROM_API_INTERRUPT_TABLE[1]) - -#define ROM_IntPrioritySet \ - ((void (*)(uint32_t ui32Interrupt, uint8_t ui8Priority)) \ - ROM_API_INTERRUPT_TABLE[2]) - -#define ROM_IntPriorityGet \ - ((int32_t (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[3]) - -#define ROM_IntEnable \ - ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[4]) - -#define ROM_IntDisable \ - ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[5]) - -#define ROM_IntPendSet \ - ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[6]) - -#define ROM_IntPendGet \ - ((bool (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[7]) - -#define ROM_IntPendClear \ - ((void (*)(uint32_t ui32Interrupt)) \ - ROM_API_INTERRUPT_TABLE[8]) - - -// IOC FUNCTIONS -#define ROM_IOCPortConfigureSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId, uint32_t ui32IOConfig)) \ - ROM_API_IOC_TABLE[0]) - -#define ROM_IOCPortConfigureGet \ - ((uint32_t (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[1]) - -#define ROM_IOCIOShutdownSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32IOShutdown)) \ - ROM_API_IOC_TABLE[2]) - -#define ROM_IOCIOModeSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32IOMode)) \ - ROM_API_IOC_TABLE[4]) - -#define ROM_IOCIOIntSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Int, uint32_t ui32EdgeDet)) \ - ROM_API_IOC_TABLE[5]) - -#define ROM_IOCIOPortPullSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Pull)) \ - ROM_API_IOC_TABLE[6]) - -#define ROM_IOCIOHystSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Hysteresis)) \ - ROM_API_IOC_TABLE[7]) - -#define ROM_IOCIOInputSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32Input)) \ - ROM_API_IOC_TABLE[8]) - -#define ROM_IOCIOSlewCtrlSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32SlewEnable)) \ - ROM_API_IOC_TABLE[9]) - -#define ROM_IOCIODrvStrengthSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32IOCurrent, uint32_t ui32DrvStrength)) \ - ROM_API_IOC_TABLE[10]) - -#define ROM_IOCIOPortIdSet \ - ((void (*)(uint32_t ui32IOId, uint32_t ui32PortId)) \ - ROM_API_IOC_TABLE[11]) - -#define ROM_IOCIntEnable \ - ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[12]) - -#define ROM_IOCIntDisable \ - ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[13]) - -#define ROM_IOCPinTypeGpioInput \ - ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[14]) - -#define ROM_IOCPinTypeGpioOutput \ - ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[15]) - -#define ROM_IOCPinTypeUart \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Cts, uint32_t ui32Rts)) \ - ROM_API_IOC_TABLE[16]) - -#define ROM_IOCPinTypeSsiMaster \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ - ROM_API_IOC_TABLE[17]) - -#define ROM_IOCPinTypeSsiSlave \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Rx, uint32_t ui32Tx, uint32_t ui32Fss, uint32_t ui32Clk)) \ - ROM_API_IOC_TABLE[18]) - -#define ROM_IOCPinTypeI2c \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Data, uint32_t ui32Clk)) \ - ROM_API_IOC_TABLE[19]) - -#define ROM_IOCPinTypeAux \ - ((void (*)(uint32_t ui32IOId)) \ - ROM_API_IOC_TABLE[21]) - - -// PRCM FUNCTIONS -#define ROM_PRCMInfClockConfigureSet \ - ((void (*)(uint32_t ui32ClkDiv, uint32_t ui32PowerMode)) \ - ROM_API_PRCM_TABLE[0]) - -#define ROM_PRCMInfClockConfigureGet \ - ((uint32_t (*)(uint32_t ui32PowerMode)) \ - ROM_API_PRCM_TABLE[1]) - -#define ROM_PRCMAudioClockConfigSet \ - ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32SampleRate)) \ - ROM_API_PRCM_TABLE[4]) - -#define ROM_PRCMPowerDomainOn \ - ((void (*)(uint32_t ui32Domains)) \ - ROM_API_PRCM_TABLE[5]) - -#define ROM_PRCMPowerDomainOff \ - ((void (*)(uint32_t ui32Domains)) \ - ROM_API_PRCM_TABLE[6]) - -#define ROM_PRCMPeripheralRunEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[7]) - -#define ROM_PRCMPeripheralRunDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[8]) - -#define ROM_PRCMPeripheralSleepEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[9]) - -#define ROM_PRCMPeripheralSleepDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[10]) - -#define ROM_PRCMPeripheralDeepSleepEnable \ - ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[11]) - -#define ROM_PRCMPeripheralDeepSleepDisable \ - ((void (*)(uint32_t ui32Peripheral)) \ - ROM_API_PRCM_TABLE[12]) - -#define ROM_PRCMPowerDomainStatus \ - ((uint32_t (*)(uint32_t ui32Domains)) \ - ROM_API_PRCM_TABLE[13]) - -#define ROM_PRCMDeepSleep \ - ((void (*)(void)) \ - ROM_API_PRCM_TABLE[14]) - -#define ROM_PRCMAudioClockConfigSetOverride \ - ((void (*)(uint32_t ui32ClkConfig, uint32_t ui32MstDiv, uint32_t ui32BitDiv, uint32_t ui32WordDiv)) \ - ROM_API_PRCM_TABLE[17]) - - -// SMPH FUNCTIONS -#define ROM_SMPHAcquire \ - ((void (*)(uint32_t ui32Semaphore)) \ - ROM_API_SMPH_TABLE[0]) - - -// SSI FUNCTIONS -#define ROM_SSIConfigSetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32SSIClk, uint32_t ui32Protocol, uint32_t ui32Mode, uint32_t ui32BitRate, uint32_t ui32DataWidth)) \ - ROM_API_SSI_TABLE[0]) - -#define ROM_SSIDataPut \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Data)) \ - ROM_API_SSI_TABLE[1]) - -#define ROM_SSIDataPutNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t ui32Data)) \ - ROM_API_SSI_TABLE[2]) - -#define ROM_SSIDataGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ - ROM_API_SSI_TABLE[3]) - -#define ROM_SSIDataGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base, uint32_t *pui32Data)) \ - ROM_API_SSI_TABLE[4]) - - -// TIMER FUNCTIONS -#define ROM_TimerConfigure \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Config)) \ - ROM_API_TIMER_TABLE[0]) - -#define ROM_TimerLevelControl \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert)) \ - ROM_API_TIMER_TABLE[1]) - -#define ROM_TimerStallControl \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bStall)) \ - ROM_API_TIMER_TABLE[3]) - -#define ROM_TimerWaitOnTriggerControl \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, bool bWait)) \ - ROM_API_TIMER_TABLE[4]) - -#define ROM_TimerIntervalLoadMode \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \ - ROM_API_TIMER_TABLE[5]) - -#define ROM_TimerMatchUpdateMode \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode)) \ - ROM_API_TIMER_TABLE[6]) - - -// TRNG FUNCTIONS -#define ROM_TRNGConfigure \ - ((void (*)(uint32_t ui32MinSamplesPerCycle, uint32_t ui32MaxSamplesPerCycle, uint32_t ui32ClocksPerSample)) \ - ROM_API_TRNG_TABLE[0]) - -#define ROM_TRNGNumberGet \ - ((uint32_t (*)(uint32_t ui32Word)) \ - ROM_API_TRNG_TABLE[1]) - - -// UART FUNCTIONS -#define ROM_UARTFIFOLevelGet \ - ((void (*)(uint32_t ui32Base, uint32_t *pui32TxLevel, uint32_t *pui32RxLevel)) \ - ROM_API_UART_TABLE[0]) - -#define ROM_UARTConfigSetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t ui32Baud, uint32_t ui32Config)) \ - ROM_API_UART_TABLE[1]) - -#define ROM_UARTConfigGetExpClk \ - ((void (*)(uint32_t ui32Base, uint32_t ui32UARTClk, uint32_t *pui32Baud, uint32_t *pui32Config)) \ - ROM_API_UART_TABLE[2]) - -#define ROM_UARTDisable \ - ((void (*)(uint32_t ui32Base)) \ - ROM_API_UART_TABLE[3]) - -#define ROM_UARTCharGetNonBlocking \ - ((int32_t (*)(uint32_t ui32Base)) \ - ROM_API_UART_TABLE[4]) - -#define ROM_UARTCharGet \ - ((int32_t (*)(uint32_t ui32Base)) \ - ROM_API_UART_TABLE[5]) - -#define ROM_UARTCharPutNonBlocking \ - ((bool (*)(uint32_t ui32Base, uint8_t ui8Data)) \ - ROM_API_UART_TABLE[6]) - -#define ROM_UARTCharPut \ - ((void (*)(uint32_t ui32Base, uint8_t ui8Data)) \ - ROM_API_UART_TABLE[7]) - - -// UDMA FUNCTIONS -#define ROM_uDMAChannelAttributeEnable \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ - ROM_API_UDMA_TABLE[0]) - -#define ROM_uDMAChannelAttributeDisable \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32Attr)) \ - ROM_API_UDMA_TABLE[1]) - -#define ROM_uDMAChannelAttributeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelNum)) \ - ROM_API_UDMA_TABLE[2]) - -#define ROM_uDMAChannelControlSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Control)) \ - ROM_API_UDMA_TABLE[3]) - -#define ROM_uDMAChannelTransferSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, uint32_t ui32TransferSize)) \ - ROM_API_UDMA_TABLE[4]) - -#define ROM_uDMAChannelScatterGatherSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32ChannelNum, uint32_t ui32TaskCount, void *pvTaskList, uint32_t ui32IsPeriphSG)) \ - ROM_API_UDMA_TABLE[5]) - -#define ROM_uDMAChannelSizeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ - ROM_API_UDMA_TABLE[6]) - -#define ROM_uDMAChannelModeGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32ChannelStructIndex)) \ - ROM_API_UDMA_TABLE[7]) - - -// VIMS FUNCTIONS -#define ROM_VIMSConfigure \ - ((void (*)(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch)) \ - ROM_API_VIMS_TABLE[0]) - -#define ROM_VIMSModeSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32Mode)) \ - ROM_API_VIMS_TABLE[1]) - -#define ROM_VIMSModeGet \ - ((uint32_t (*)(uint32_t ui32Base)) \ - ROM_API_VIMS_TABLE[2]) - -#define ROM_VIMSModeSafeSet \ - ((void (*)(uint32_t ui32Base, uint32_t ui32NewMode, bool blocking)) \ - ROM_API_VIMS_TABLE[3]) - - -// OSC FUNCTIONS -#define ROM_OSCClockSourceGet \ - ((uint32_t (*)(uint32_t ui32SrcClk)) \ - ROM_API_OSC_TABLE[0]) - -#define ROM_OSCClockSourceSet \ - ((void (*)(uint32_t ui32SrcClk, uint32_t ui32Osc)) \ - ROM_API_OSC_TABLE[1]) - -#define ROM_OSC_HPOSCRelativeFrequencyOffsetToRFCoreFormatConvert \ - ((int16_t (*)(int32_t HPOSC_RelFreqOffset)) \ - ROM_API_OSC_TABLE[3]) - - -// AUX_ADC FUNCTIONS -#define ROM_AUXADCAdjustValueForGainAndOffset \ - ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \ - ROM_API_AUX_ADC_TABLE[0]) - -#define ROM_AUXADCDisable \ - ((void (*)(void)) \ - ROM_API_AUX_ADC_TABLE[1]) - -#define ROM_AUXADCDisableInputScaling \ - ((void (*)(void)) \ - ROM_API_AUX_ADC_TABLE[2]) - -#define ROM_AUXADCEnableAsync \ - ((void (*)(uint32_t refSource, uint32_t trigger)) \ - ROM_API_AUX_ADC_TABLE[3]) - -#define ROM_AUXADCEnableSync \ - ((void (*)(uint32_t refSource, uint32_t sampleTime, uint32_t trigger)) \ - ROM_API_AUX_ADC_TABLE[4]) - -#define ROM_AUXADCFlushFifo \ - ((void (*)(void)) \ - ROM_API_AUX_ADC_TABLE[5]) - -#define ROM_AUXADCGetAdjustmentGain \ - ((int32_t (*)(uint32_t refSource)) \ - ROM_API_AUX_ADC_TABLE[6]) - -#define ROM_AUXADCGetAdjustmentOffset \ - ((int32_t (*)(uint32_t refSource)) \ - ROM_API_AUX_ADC_TABLE[7]) - -#define ROM_AUXADCMicrovoltsToValue \ - ((int32_t (*)(int32_t fixedRefVoltage, int32_t microvolts)) \ - ROM_API_AUX_ADC_TABLE[8]) - -#define ROM_AUXADCPopFifo \ - ((uint32_t (*)(void)) \ - ROM_API_AUX_ADC_TABLE[9]) - -#define ROM_AUXADCReadFifo \ - ((uint32_t (*)(void)) \ - ROM_API_AUX_ADC_TABLE[10]) - -#define ROM_AUXADCUnadjustValueForGainAndOffset \ - ((int32_t (*)(int32_t adcValue, int32_t gain, int32_t offset)) \ - ROM_API_AUX_ADC_TABLE[11]) - -#define ROM_AUXADCValueToMicrovolts \ - ((int32_t (*)(int32_t fixedRefVoltage, int32_t adcValue)) \ - ROM_API_AUX_ADC_TABLE[12]) - - -// SYS_CTRL FUNCTIONS -#define ROM_SysCtrlResetSourceGet \ - ((uint32_t (*)(void)) \ - ROM_API_SYS_CTRL_TABLE[0]) - -#define ROM_SysCtrl_DCDC_VoltageConditionalControl \ - ((void (*)(void)) \ - ROM_API_SYS_CTRL_TABLE[1]) - - -// AON_BATMON FUNCTIONS -#define ROM_AONBatMonTemperatureGetDegC \ - ((int32_t (*)(void)) \ - ROM_API_AON_BATMON_TABLE[0]) - - -// SETUP_ROM FUNCTIONS -#define ROM_SetupAfterColdResetWakeupFromShutDownCfg1 \ - ((void (*)(uint32_t ccfg_ModeConfReg)) \ - ROM_API_SETUP_ROM_TABLE[0]) - -#define ROM_SetupAfterColdResetWakeupFromShutDownCfg2 \ - ((void (*)(uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg)) \ - ROM_API_SETUP_ROM_TABLE[1]) - -#define ROM_SetupAfterColdResetWakeupFromShutDownCfg3 \ - ((void (*)(uint32_t ccfg_ModeConfReg)) \ - ROM_API_SETUP_ROM_TABLE[2]) - -#define ROM_SetupGetTrimForAdcShModeEn \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[3]) - -#define ROM_SetupGetTrimForAdcShVbufEn \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[4]) - -#define ROM_SetupGetTrimForAmpcompCtrl \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[5]) - -#define ROM_SetupGetTrimForAmpcompTh1 \ - ((uint32_t (*)(void)) \ - ROM_API_SETUP_ROM_TABLE[6]) - -#define ROM_SetupGetTrimForAmpcompTh2 \ - ((uint32_t (*)(void)) \ - ROM_API_SETUP_ROM_TABLE[7]) - -#define ROM_SetupGetTrimForAnabypassValue1 \ - ((uint32_t (*)(uint32_t ccfg_ModeConfReg)) \ - ROM_API_SETUP_ROM_TABLE[8]) - -#define ROM_SetupGetTrimForDblrLoopFilterResetVoltage \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[9]) - -#define ROM_SetupGetTrimForRadcExtCfg \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[10]) - -#define ROM_SetupGetTrimForRcOscLfIBiasTrim \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[11]) - -#define ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim \ - ((uint32_t (*)(void)) \ - ROM_API_SETUP_ROM_TABLE[12]) - -#define ROM_SetupGetTrimForXoscHfCtl \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[13]) - -#define ROM_SetupGetTrimForXoscHfFastStart \ - ((uint32_t (*)(void)) \ - ROM_API_SETUP_ROM_TABLE[14]) - -#define ROM_SetupGetTrimForXoscHfIbiastherm \ - ((uint32_t (*)(void)) \ - ROM_API_SETUP_ROM_TABLE[15]) - -#define ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio \ - ((uint32_t (*)(uint32_t ui32Fcfg1Revision)) \ - ROM_API_SETUP_ROM_TABLE[16]) - -#define ROM_SetupSetAonRtcSubSecInc \ - ((void (*)(uint32_t subSecInc)) \ - ROM_API_SETUP_ROM_TABLE[17]) - -#define ROM_SetupSetCacheModeAccordingToCcfgSetting \ - ((void (*)(void)) \ - ROM_API_SETUP_ROM_TABLE[18]) - -#define ROM_SetupStepVddrTrimTo \ - ((void (*)(uint32_t toCode)) \ - ROM_API_SETUP_ROM_TABLE[19]) - - -// I2S FUNCTIONS -#define ROM_I2SPointerSet \ - ((void (*)(uint32_t ui32Base, bool bInput, void * pNextPointer)) \ - ROM_API_I2S_TABLE[0]) - -#define ROM_I2SSampleStampGet \ - ((uint32_t (*)(uint32_t ui32Base, uint32_t ui32Channel)) \ - ROM_API_I2S_TABLE[1]) - - -// PWR_CTRL FUNCTIONS -#define ROM_PowerCtrlSourceSet \ - ((void (*)(uint32_t ui32PowerConfig)) \ - ROM_API_PWR_CTRL_TABLE[0]) - - -// AES FUNCTIONS -#define ROM_AESConfigureCCMCtrl \ - ((void (*)(uint32_t nonceLength, uint32_t macLength, bool encrypt)) \ - ROM_API_AES_TABLE[0]) - -#define ROM_AESReadFromKeyStore \ - ((uint32_t (*)(uint32_t keyStoreArea)) \ - ROM_API_AES_TABLE[1]) - -#define ROM_AESReadTag \ - ((uint32_t (*)(uint8_t *tag, uint32_t tagLength)) \ - ROM_API_AES_TABLE[2]) - -#define ROM_AESSetInitializationVector \ - ((void (*)(const uint32_t *initializationVector)) \ - ROM_API_AES_TABLE[3]) - -#define ROM_AESStartDMAOperation \ - ((void (*)(const uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \ - ROM_API_AES_TABLE[4]) - -#define ROM_AESVerifyTag \ - ((uint32_t (*)(const uint8_t *tag, uint32_t tagLength)) \ - ROM_API_AES_TABLE[5]) - -#define ROM_AESWaitForIRQFlags \ - ((uint32_t (*)(uint32_t irqFlags)) \ - ROM_API_AES_TABLE[6]) - -#define ROM_AESWriteCCMInitializationVector \ - ((void (*)(const uint8_t *nonce, uint32_t nonceLength)) \ - ROM_API_AES_TABLE[7]) - -#define ROM_AESWriteToKeyStore \ - ((uint32_t (*)(const uint8_t *aesKey, uint32_t aesKeyLength, uint32_t keyStoreArea)) \ - ROM_API_AES_TABLE[8]) - - -// PKA FUNCTIONS -#define ROM_PKABigNumAddGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[0]) - -#define ROM_PKABigNumCmpGetResult \ - ((uint32_t (*)(void)) \ - ROM_API_PKA_TABLE[1]) - -#define ROM_PKABigNumInvModGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[2]) - -#define ROM_PKABigNumModGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t length, uint32_t resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[3]) - -#define ROM_PKABigNumMultGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[4]) - -#define ROM_PKAEccAddGetResult \ - ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ - ROM_API_PKA_TABLE[5]) - -#define ROM_PKAEccAddStart \ - ((uint32_t (*)(const uint8_t *curvePoint1X, const uint8_t *curvePoint1Y, const uint8_t *curvePoint2X, const uint8_t *curvePoint2Y, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[6]) - -#define ROM_PKAEccMultiplyGetResult \ - ((uint32_t (*)(uint8_t *curvePointX, uint8_t *curvePointY, uint32_t resultPKAMemAddr, uint32_t length)) \ - ROM_API_PKA_TABLE[7]) - -#define ROM_PKAEccMultiplyStart \ - ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, uint32_t length, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[8]) - -#define ROM_PKAGetOpsStatus \ - ((uint32_t (*)(void)) \ - ROM_API_PKA_TABLE[9]) - -#define ROM_PKABigNumAddStart \ - ((uint32_t (*)(const uint8_t *bigNum1, uint32_t bigNum1Length, const uint8_t *bigNum2, uint32_t bigNum2Length, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[10]) - -#define ROM_PKABigNumCmpStart \ - ((uint32_t (*)(const uint8_t *bigNum1, const uint8_t *bigNum2, uint32_t length)) \ - ROM_API_PKA_TABLE[11]) - -#define ROM_PKABigNumInvModStart \ - ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[12]) - -#define ROM_PKABigNumModStart \ - ((uint32_t (*)(const uint8_t *bigNum, uint32_t bigNumLength, const uint8_t *modulus, uint32_t modulusLength, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[13]) - -#define ROM_PKABigNumMultiplyStart \ - ((uint32_t (*)(const uint8_t *multiplicand, uint32_t multiplicandLength, const uint8_t *multiplier, uint32_t multiplierLength, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[14]) - -#define ROM_PKABigNumSubGetResult \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *resultLength, uint32_t resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[15]) - -#define ROM_PKABigNumSubStart \ - ((uint32_t (*)(const uint8_t *minuend, uint32_t minuendLength, const uint8_t *subtrahend, uint32_t subtrahendLength, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[16]) - -#define ROM_PKAArrayAllZeros \ - ((bool (*)(const uint8_t *array, uint32_t arrayLength)) \ - ROM_API_PKA_TABLE[17]) - -#define ROM_PKABigNumDivideGetQuotient \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultQuotientMemAddr)) \ - ROM_API_PKA_TABLE[18]) - -#define ROM_PKABigNumDivideGetRemainder \ - ((uint32_t (*)(uint8_t *resultBuf, uint32_t *length, uint32_t resultRemainderMemAddr)) \ - ROM_API_PKA_TABLE[19]) - -#define ROM_PKABigNumDivideStart \ - ((uint32_t (*)(const uint8_t *dividend, uint32_t dividendLength, const uint8_t *divisor, uint32_t divisorLength, uint32_t *resultQuotientMemAddr, uint32_t *resultRemainderMemAddr)) \ - ROM_API_PKA_TABLE[20]) - -#define ROM_PKAEccVerifyPublicKeyWeierstrassStart \ - ((uint32_t (*)(const uint8_t *curvePointX, const uint8_t *curvePointY, const uint8_t *prime, const uint8_t *a, const uint8_t *b, const uint8_t *order, uint32_t length)) \ - ROM_API_PKA_TABLE[21]) - -#define ROM_PKAZeroOutArray \ - ((void (*)(const uint8_t *array, uint32_t arrayLength)) \ - ROM_API_PKA_TABLE[22]) - -#define ROM_PKAEccMontgomeryMultiplyStart \ - ((uint32_t (*)(const uint8_t *scalar, const uint8_t *curvePointX, const uint8_t *prime, const uint8_t *a, uint32_t length, uint32_t *resultPKAMemAddr)) \ - ROM_API_PKA_TABLE[23]) - - -// SHA2 FUNCTIONS -#define ROM_SHA2ComputeFinalHash \ - ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm)) \ - ROM_API_SHA2_TABLE[0]) - -#define ROM_SHA2ComputeHash \ - ((uint32_t (*)(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm)) \ - ROM_API_SHA2_TABLE[1]) - -#define ROM_SHA2ComputeInitialHash \ - ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength)) \ - ROM_API_SHA2_TABLE[2]) - -#define ROM_SHA2ComputeIntermediateHash \ - ((uint32_t (*)(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength)) \ - ROM_API_SHA2_TABLE[3]) - -#define ROM_SHA2StartDMAOperation \ - ((void (*)(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length)) \ - ROM_API_SHA2_TABLE[4]) - -#define ROM_SHA2WaitForIRQFlags \ - ((uint32_t (*)(uint32_t irqFlags)) \ - ROM_API_SHA2_TABLE[5]) - - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __ROM_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c deleted file mode 100644 index 2f284cdf326..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.c +++ /dev/null @@ -1,159 +0,0 @@ -/******************************************************************************* -* Filename: rom_crypto.c -* Revised: 2018-09-17 08:57:21 +0200 (Mon, 17 Sep 2018) -* Revision: 52619 -* -* Description: This is the implementation for the API to the ECC functions -* built into ROM on the CC13x2/CC26x2. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -*******************************************************************************/ - -#include -#include "rom_crypto.h" - - -////////////////////////////////////* ECC *//////////////////////////////////// -#ifdef ECC_PRIME_NIST256_CURVE -//#define TEST_NIST256 -//#define PARAM_P NIST256_p; -#define PARAM_P 0x100257d4; - -//#define PARAM_R NIST256_r; -#define PARAM_R 0x100257f8; - -//#define PARAM_A NIST256_a; -#define PARAM_A 0x1002581c; - -//#define PARAM_B NIST256_b; -#define PARAM_B 0x10025840; - -//#define PARAM_GX NIST256_Gx; -#define PARAM_GX 0x10025864; - -//#define PARAM_GY NIST256_Gy; -#define PARAM_GY 0x10025888; - -#endif - - -//***************************************************************************** -// ECC_initialize -//***************************************************************************** -void -ECC_initialize(uint32_t *pWorkzone) -{ - // Initialize curve parameters - //data_p = (uint32_t *)PARAM_P; - *((uint32_t **)0x20000138) = (uint32_t *)PARAM_P; - - //data_r = (uint32_t *)PARAM_R; - *((uint32_t **)0x2000013c) = (uint32_t *)PARAM_R; - - //data_a = (uint32_t *)PARAM_A; - *((uint32_t **)0x20000140) = (uint32_t *)PARAM_A; - - //data_b = (uint32_t *)PARAM_B; - *((uint32_t **)0x20000144) = (uint32_t *)PARAM_B; - - //data_Gx = (uint32_t *)PARAM_GX; - *((uint32_t **)0x2000012c) = (uint32_t *)PARAM_GX; - - //data_Gy = (uint32_t *)PARAM_GY; - *((uint32_t **)0x20000130) = (uint32_t *)PARAM_GY; - - // Initialize window size - //win = (uint8_t) ECC_WINDOW_SIZE; - *((uint8_t *)0x20000148) = (uint8_t) ECC_WINDOW_SIZE; - - // Initialize work zone - //workzone = (uint32_t *) pWorkzone; - *((uint32_t **)0x20000134) = (uint32_t *) pWorkzone; -} - -typedef uint8_t(*ecc_keygen_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *); -ecc_keygen_t ecc_generatekey = (ecc_keygen_t)(0x1001f94d); - -typedef uint8_t(*ecdsa_sign_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); -ecdsa_sign_t ecc_ecdsa_sign = (ecdsa_sign_t)(0x10010381); - -typedef uint8_t(*ecdsa_verify_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); -ecdsa_verify_t ecc_ecdsa_verify = (ecdsa_verify_t)(0x1000c805); - -typedef uint8_t(*ecdh_computeSharedSecret_t)(uint32_t *, uint32_t *,uint32_t *, uint32_t *, uint32_t *); -ecdh_computeSharedSecret_t ecdh_computeSharedSecret = (ecdh_computeSharedSecret_t)(0x10023485); - -//***************************************************************************** -// ECC_generateKey -//***************************************************************************** -uint8_t -ECC_generateKey(uint32_t *randString, uint32_t *privateKey, - uint32_t *publicKey_x, uint32_t *publicKey_y) -{ - return (uint8_t)ecc_generatekey((uint32_t*)randString, (uint32_t*)privateKey, - (uint32_t*)publicKey_x, (uint32_t*)publicKey_y); - -} - -//***************************************************************************** -// ECC_ECDSA_sign -//***************************************************************************** -uint8_t -ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString, - uint32_t *sign1, uint32_t *sign2) -{ - return (uint8_t)ecc_ecdsa_sign((uint32_t*)secretKey, (uint32_t*)text, (uint32_t*)randString, - (uint32_t*)sign1, (uint32_t*)sign2); -} - -//***************************************************************************** -// ECC_ECDSA_verify -//***************************************************************************** -uint8_t -ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y, - uint32_t *text, uint32_t *sign1, uint32_t *sign2) -{ - return (uint8_t)ecc_ecdsa_verify((uint32_t*)publicKey_x, (uint32_t*)publicKey_y, (uint32_t*)text, - (uint32_t*)sign1, (uint32_t*)sign2); -} - -//***************************************************************************** -// ECC_ECDH_computeSharedSecret -//***************************************************************************** -uint8_t -ECC_ECDH_computeSharedSecret(uint32_t *privateKey, uint32_t *publicKey_x, - uint32_t *publicKey_y, uint32_t *sharedSecret_x, - uint32_t *sharedSecret_y) -{ - return (uint8_t)ecdh_computeSharedSecret((uint32_t*)privateKey, (uint32_t*)publicKey_x, - (uint32_t*)publicKey_y, (uint32_t*)sharedSecret_x, - (uint32_t*)sharedSecret_y); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h deleted file mode 100644 index eecafac5a93..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/rom_crypto.h +++ /dev/null @@ -1,212 +0,0 @@ -/****************************************************************************** -* Filename: rom_crypto.h -* Revised: 2018-09-17 09:24:56 +0200 (Mon, 17 Sep 2018) -* Revision: 52624 -* -* Description: This header file is the API to the crypto functions -* built into ROM on the CC13xx/CC26xx. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -*******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup rom_crypto_api -//! @{ -// -//***************************************************************************** - -#ifndef ROM_CRYPTO_H -#define ROM_CRYPTO_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -////////////////////////////////////* ECC *///////////////////////////////////// - -/* Window size, valid values are 2,3,4,5. - * Higher the value, faster the computation at the expense of memory usage. - * - * Recommended workzone size (in 4-byte words) - * Window size: 3, Workzone size: 275 - * - */ -#define ECC_WINDOW_SIZE 3 - -/* - * ECC Supported Curves, define one: - * ECC_PRIME_NIST256_CURVE - */ -#define ECC_PRIME_NIST256_CURVE - -/* - * ECC Return Status Flags. - */ -// Scalar multiplication status -#define ECC_MODULUS_EVEN 0xDC -#define ECC_MODULUS_LARGER_THAN_255_WORDS 0xD2 -#define ECC_MODULUS_LENGTH_ZERO 0x08 -#define ECC_MODULUS_MSW_IS_ZERO 0x30 -#define ECC_SCALAR_TOO_LONG 0x35 -#define ECC_SCALAR_LENGTH_ZERO 0x53 -#define ECC_ORDER_TOO_LONG 0xC6 -#define ECC_ORDER_LENGTH_ZERO 0x6C -#define ECC_X_COORD_TOO_LONG 0x3C -#define ECC_X_COORD_LENGTH_ZERO 0xC3 -#define ECC_Y_COORD_TOO_LONG 0x65 -#define ECC_Y_COORD_LENGTH_ZERO 0x56 -#define ECC_A_COEF_TOO_LONG 0x5C -#define ECC_A_COEF_LENGTH_ZERO 0xC5 -#define ECC_BAD_WINDOW_SIZE 0x66 -#define ECC_SCALAR_MUL_OK 0x99 - -// ECDSA and ECDH status -#define ECC_ORDER_LARGER_THAN_255_WORDS 0x28 -#define ECC_ORDER_EVEN 0x82 -#define ECC_ORDER_MSW_IS_ZERO 0x23 -#define ECC_ECC_KEY_TOO_LONG 0x25 -#define ECC_ECC_KEY_LENGTH_ZERO 0x52 -#define ECC_DIGEST_TOO_LONG 0x27 -#define ECC_DIGEST_LENGTH_ZERO 0x72 -#define ECC_ECDSA_SIGN_OK 0x32 -#define ECC_ECDSA_INVALID_SIGNATURE 0x5A -#define ECC_ECDSA_VALID_SIGNATURE 0xA5 -#define ECC_SIG_P1_TOO_LONG 0x11 -#define ECC_SIG_P1_LENGTH_ZERO 0x12 -#define ECC_SIG_P2_TOO_LONG 0x22 -#define ECC_SIG_P2_LENGTH_ZERO 0x21 - -#define ECC_ECDSA_KEYGEN_OK ECC_SCALAR_MUL_OK -#define ECC_ECDH_KEYGEN_OK ECC_SCALAR_MUL_OK -#define ECC_ECDH_COMMON_KEY_OK ECC_SCALAR_MUL_OK - -//***************************************************************************** -/*! - * \brief Pass pointer to ECC memory allocation to ECC engine. - * - * This function can be called again to point the ECC workzone at - * a different memory buffer. - * - * \param pWorkzone Pointer to memory allocated for computations, input. - * See description at beginning of ECC section for - * memory requirements. - * - * \return None - */ -//***************************************************************************** - extern void ECC_initialize(uint32_t *pWorkzone); - -//***************************************************************************** - /*! - * \brief Generate a key. - * - * This is used for both ECDH and ECDSA. - * - * \param randString Pointer to random string, input. - * \param privateKey Pointer to the private key, output. - * \param publicKey_x Pointer to public key X-coordinate, output. - * \param publicKey_y Pointer to public key Y-coordinate, output. - * - * \return Status - */ -//***************************************************************************** -extern uint8_t ECC_generateKey(uint32_t *randString, uint32_t *privateKey, - uint32_t *publicKey_x, uint32_t *publicKey_y); - -//***************************************************************************** -/*! - * \brief Sign data. - * - * \param secretKey Pointer to the secret key, input. - * \param text Pointer to the message, input. - * \param randString Pointer to random string, input. - * \param sign1 Pointer to signature part 1, output. - * \param sign2 Pointer to signature part 2, output. - * - * \return Status - */ -//***************************************************************************** -extern uint8_t ECC_ECDSA_sign(uint32_t *secretKey, uint32_t *text, uint32_t *randString, - uint32_t *sign1, uint32_t *sign2); - -//***************************************************************************** -/*! - * \brief Verify signature. - * - * \param publicKey_x Pointer to public key X-coordinate, input. - * \param publicKey_y Pointer to public key Y-coordinate, input. - * \param text Pointer to message data, input. - * \param sign1 Pointer to signature part 1, input. - * \param sign2 Pointer to signature part 2, input. - * - * \return Status - */ -//***************************************************************************** -extern uint8_t ECC_ECDSA_verify(uint32_t *publicKey_x, uint32_t *publicKey_y, - uint32_t *text, uint32_t *sign1, uint32_t *sign2); - -//***************************************************************************** -/*! - * \brief Compute the shared secret. - * - * \param privateKey Pointer to private key, input. - * \param publicKey_x Pointer to public key X-coordinate, input. - * \param publicKey_y Pointer to public key Y-coordinate, input. - * \param sharedSecret_x Pointer to shared secret X-coordinate, output. - * \param sharedSecret_y Pointer to shared secret Y-coordinate, output. - * - * \return Status - */ -//***************************************************************************** -extern uint8_t ECC_ECDH_computeSharedSecret(uint32_t *privateKey, - uint32_t *publicKey_x, - uint32_t *publicKey_y, - uint32_t *sharedSecret_x, - uint32_t *sharedSecret_y); - - -#ifdef __cplusplus -} -#endif - -#endif /* ROM_CRYPTO_H */ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup.c deleted file mode 100644 index 1f438bed05f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup.c +++ /dev/null @@ -1,344 +0,0 @@ -/****************************************************************************** -* Filename: setup.c -* Revised: 2018-11-06 15:08:57 +0100 (Tue, 06 Nov 2018) -* Revision: 53239 -* -* Description: Setup file for CC13xx/CC26xx devices. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -// Hardware headers -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_adi.h" -#include "../inc/hw_adi_2_refsys.h" -#include "../inc/hw_adi_3_refsys.h" -#include "../inc/hw_adi_4_aux.h" -// Temporarily adding these defines as they are missing in hw_adi_4_aux.h -#define ADI_4_AUX_O_LPMBIAS 0x0000000E -#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F -#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0 -#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038 -#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3 -#include "../inc/hw_aon_ioc.h" -#include "../inc/hw_aon_pmctl.h" -#include "../inc/hw_aon_rtc.h" -#include "../inc/hw_ddi_0_osc.h" -#include "../inc/hw_ddi.h" -#include "../inc/hw_ccfg.h" -#include "../inc/hw_fcfg1.h" -#include "../inc/hw_flash.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_vims.h" -// Driverlib headers -#include "aux_sysif.h" -#include "chipinfo.h" -#include "setup.h" -#include "setup_rom.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef SetupTrimDevice - #define SetupTrimDevice NOROM_SetupTrimDevice -#endif - - - -//***************************************************************************** -// -// Defined CPU delay macro with microseconds as input -// Quick check shows: (To be further investigated) -// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 5 cycles -// At 48 MHz RCOSC and VIMS.CONTROL.PREFETCH = 1, there is 4 cycles -// At 24 MHz RCOSC and VIMS.CONTROL.PREFETCH = 0, there is 3 cycles -// -//***************************************************************************** -#define CPU_DELAY_MICRO_SECONDS( x ) \ - CPUdelay(((uint32_t)((( x ) * 48.0 ) / 5.0 )) - 1 ) - - -//***************************************************************************** -// -// Function declarations -// -//***************************************************************************** -static void TrimAfterColdReset( void ); -static void TrimAfterColdResetWakeupFromShutDown( uint32_t ui32Fcfg1Revision ); -static void TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void ); - -//***************************************************************************** -// -// Perform the necessary trim of the device which is not done in boot code -// -// This function should only execute coming from ROM boot. The current -// implementation does not take soft reset into account. However, it does no -// damage to execute it again. It only consumes time. -// -//***************************************************************************** -void -SetupTrimDevice(void) -{ - uint32_t ui32Fcfg1Revision; - uint32_t ui32AonSysResetctl; - - // Get layout revision of the factory configuration area - // (Handle undefined revision as revision = 0) - ui32Fcfg1Revision = HWREG(FCFG1_BASE + FCFG1_O_FCFG1_REVISION); - if ( ui32Fcfg1Revision == 0xFFFFFFFF ) { - ui32Fcfg1Revision = 0; - } - - // This driverlib version and setup file is for the CC13x2, CC26x2 PG2.0 or later chips. - // Halt if violated - ThisLibraryIsFor_CC13x2_CC26x2_HwRev20AndLater_HaltIfViolated(); - - // Enable standby in flash bank - HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_STANDBY_BITN ) = 0; - - // Select correct CACHE mode and set correct CACHE configuration -#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) - SetupSetCacheModeAccordingToCcfgSetting(); -#else - NOROM_SetupSetCacheModeAccordingToCcfgSetting(); -#endif - - // 1. Check for powerdown - // 2. Check for shutdown - // 3. Assume cold reset if none of the above. - // - // It is always assumed that the application will freeze the latches in - // AON_IOC when going to powerdown in order to retain the values on the IOs. - // - // NB. If this bit is not cleared before proceeding to powerdown, the IOs - // will all default to the reset configuration when restarting. - if( ! ( HWREGBITW( AON_IOC_BASE + AON_IOC_O_IOCLATCH, AON_IOC_IOCLATCH_EN_BITN ))) - { - // NB. This should be calling a ROM implementation of required trim and - // compensation - // e.g. TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown() - TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); - } - // Check for shutdown - // - // When device is going to shutdown the hardware will automatically clear - // the SLEEPDIS bit in the SLEEP register in the AON_PMCTL module. - // It is left for the application to assert this bit when waking back up, - // but not before the desired IO configuration has been re-established. - else if( ! ( HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_SLEEPCTL, AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN ))) - { - // NB. This should be calling a ROM implementation of required trim and - // compensation - // e.g. TrimAfterColdResetWakeupFromShutDown() --> - // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); - TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision); - TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); - } - else - { - // Consider adding a check for soft reset to allow debugging to skip - // this section!!! - // - // NB. This should be calling a ROM implementation of required trim and - // compensation - // e.g. TrimAfterColdReset() --> - // TrimAfterColdResetWakeupFromShutDown() --> - // TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown() - TrimAfterColdReset(); - TrimAfterColdResetWakeupFromShutDown(ui32Fcfg1Revision); - TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown(); - - } - - // Set VIMS power domain control. - // PDCTL1VIMS = 0 ==> VIMS power domain is only powered when CPU power domain is powered - HWREG( PRCM_BASE + PRCM_O_PDCTL1VIMS ) = 0; - - // Configure optimal wait time for flash FSM in cases where flash pump - // wakes up from sleep - HWREG(FLASH_BASE + FLASH_O_FPAC1) = (HWREG(FLASH_BASE + FLASH_O_FPAC1) & - ~FLASH_FPAC1_PSLEEPTDIS_M) | - (0x139<> - AON_PMCTL_RESETCTL_BOOT_DET_0_S ) == 1 ) - { - ui32AonSysResetctl = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & - ~( AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M | AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M | - AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M | AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M | AON_PMCTL_RESETCTL_MCU_WARM_RESET_M )); - HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl | AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M; - HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ui32AonSysResetctl; - } - - // Make sure there are no ongoing VIMS mode change when leaving SetupTrimDevice() - // (There should typically be no wait time here, but need to be sure) - while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { - // Do nothing - wait for an eventual ongoing mode change to complete. - } -} - -//***************************************************************************** -// -//! \brief Trims to be applied when coming from POWER_DOWN (also called when -//! coming from SHUTDOWN and PIN_RESET). -//! -//! \return None -// -//***************************************************************************** -static void -TrimAfterColdResetWakeupFromShutDownWakeupFromPowerDown( void ) -{ - // Currently no specific trim for Powerdown -} - -//***************************************************************************** -// -//! \brief Trims to be applied when coming from SHUTDOWN (also called when -//! coming from PIN_RESET). -//! -//! \param ui32Fcfg1Revision -//! -//! \return None -// -//***************************************************************************** -static void -TrimAfterColdResetWakeupFromShutDown(uint32_t ui32Fcfg1Revision) -{ - uint32_t ccfg_ModeConfReg ; - - // Check in CCFG for alternative DCDC setting - if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) { - // ADI_3_REFSYS:DCDCCTL5[3] (=DITHER_EN) = CCFG_MODE_CONF_1[19] (=ALT_DCDC_DITHER_EN) - // ADI_3_REFSYS:DCDCCTL5[2:0](=IPEAK ) = CCFG_MODE_CONF_1[18:16](=ALT_DCDC_IPEAK ) - // Using a single 4-bit masked write since layout is equal for both source and destination - HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_DCDCCTL5 * 2 )) = ( 0xF0 | - ( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) >> CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S )); - - } - - // TBD - Temporarily removed for CC13x2 / CC26x2 - - // Force DCDC to use RCOSC before starting up XOSC. - // Clock loss detector does not use XOSC until SCLK_HF actually switches - // and thus DCDC is not protected from clock loss on XOSC in that time frame. - // The force must be released when the switch to XOSC has happened. This is done - // in OSCHfSourceSwitch(). - HWREG(AUX_DDI0_OSC_BASE + DDI_O_MASK16B + (DDI_0_OSC_O_CTL0 << 1) + 4) = DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M | (DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M >> 16); - // Dummy read to ensure that the write has propagated - HWREGH(AUX_DDI0_OSC_BASE + DDI_0_OSC_O_CTL0); - - // read the MODE_CONF register in CCFG - ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); - - // First part of trim done after cold reset and wakeup from shutdown: - // -Adjust the VDDR_TRIM_SLEEP value. - // -Configure DCDC. - SetupAfterColdResetWakeupFromShutDownCfg1( ccfg_ModeConfReg ); - - // Addition to the CC1352 boost mode for HWREV >= 2.0 - // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode - if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) && - (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) - { - HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL3 ) = ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST ; - } - - // Second part of trim done after cold reset and wakeup from shutdown: - // -Configure XOSC. -#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) - SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); -#else - NOROM_SetupAfterColdResetWakeupFromShutDownCfg2( ui32Fcfg1Revision, ccfg_ModeConfReg ); -#endif - - { - uint32_t trimReg ; - uint32_t ui32TrimValue ; - - //--- Propagate the LPM_BIAS trim --- - trimReg = HWREG( FCFG1_BASE + FCFG1_O_DAC_BIAS_CNF ); - ui32TrimValue = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M ) >> - FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S ) ; - HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_LPMBIAS ) = (( ui32TrimValue << ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S ) & - ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M ) ; - // Set LPM_BIAS_BACKUP_EN according to FCFG1 configuration - if ( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN ) { - HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN; - } else { - HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_AUX_DEBUG ) = ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN; - } - // Set LPM_BIAS_WIDTH_TRIM according to FCFG1 configuration - { - uint32_t widthTrim = (( trimReg & FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M ) >> FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S ); - HWREGH( AUX_ADI4_BASE + ADI_O_MASK8B + ( ADI_4_AUX_O_COMP * 2 )) = // Set LPM_BIAS_WIDTH_TRIM = 3 - (( ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M << 8 ) | // Set mask (bits to be written) in [15:8] - ( widthTrim << ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S ) ); // Set value (in correct bit pos) in [7:0] - } - } - - // Third part of trim done after cold reset and wakeup from shutdown: - // -Configure HPOSC. - // -Setup the LF clock. -#if ( CCFG_BASE == CCFG_BASE_DEFAULT ) - SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg ); -#else - NOROM_SetupAfterColdResetWakeupFromShutDownCfg3( ccfg_ModeConfReg ); -#endif - - // Set AUX into power down active mode - AUXSYSIFOpModeChange( AUX_SYSIF_OPMODE_TARGET_PDA ); - - // Disable EFUSE clock - HWREGBITW( FLASH_BASE + FLASH_O_CFG, FLASH_CFG_DIS_EFUSECLK_BITN ) = 1; -} - - -//***************************************************************************** -// -//! \brief Trims to be applied when coming from PIN_RESET. -//! -//! \return None -// -//***************************************************************************** -static void -TrimAfterColdReset( void ) -{ - // Currently no specific trim for Cold Reset -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h deleted file mode 100644 index c2093d7fa7f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup.h +++ /dev/null @@ -1,141 +0,0 @@ -/****************************************************************************** -* Filename: setup.h -* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) -* Revision: 52993 -* -* Description: Prototypes and defines for the setup API. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup setup_api -//! @{ -// -//***************************************************************************** - -#ifndef __SETUP_H__ -#define __SETUP_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -// Hardware headers -#include "../inc/hw_types.h" -// Driverlib headers -// - None needed - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define SetupTrimDevice NOROM_SetupTrimDevice -#endif - -//***************************************************************************** -// -//! \brief Performs the necessary trim of the device which is not done in ROM boot code. -//! -//! This function should only execute coming from ROM boot. -//! -//! The following is handled by this function: -//! - Checks if the driverlib variant used by the application is supported by the -//! device. Execution is halted in case of unsupported driverlib variant. -//! - Configures VIMS cache mode based on setting in CCFG. -//! - Configures functionalities like DCDC and XOSC dependent on startup modes like -//! cold reset, wakeup from shutdown and wakeup from from powerdown. -//! - Configures VIMS power domain control. -//! - Configures optimal wait time for flash FSM in cases where flash pump wakes up from sleep. -//! -//! \note The current implementation does not take soft reset into account. However, -//! it does no damage to execute it again. It only consumes time. -//! -//! \note This function is called by the compiler specific device startup codes -//! that are integrated in the SimpleLink SDKs for CC13xx/CC26XX devices. -//! -//! \return None -// -//***************************************************************************** -extern void SetupTrimDevice( void ); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_SetupTrimDevice - #undef SetupTrimDevice - #define SetupTrimDevice ROM_SetupTrimDevice - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SETUP_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h deleted file mode 100644 index 469279907c4..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_doc.h +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: setup_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup setup_api -//! @{ -//! -//! This module contains functions for device setup which is not done in boot code. -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.c deleted file mode 100644 index 745204b4430..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.c +++ /dev/null @@ -1,943 +0,0 @@ -/****************************************************************************** -* Filename: setup_rom.c -* Revised: 2017-11-02 11:31:15 +0100 (Thu, 02 Nov 2017) -* Revision: 50143 -* -* Description: Setup file for CC13xx/CC26xx devices. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -// Hardware headers -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_adi.h" -#include "../inc/hw_adi_2_refsys.h" -#include "../inc/hw_adi_3_refsys.h" -#include "../inc/hw_adi_4_aux.h" -#include "../inc/hw_aon_batmon.h" -#include "../inc/hw_aux_sysif.h" -#include "../inc/hw_ccfg.h" -#include "../inc/hw_ddi_0_osc.h" -#include "../inc/hw_fcfg1.h" -// Driverlib headers -#include "ddi.h" -#include "ioc.h" -#include "osc.h" -#include "sys_ctrl.h" -#include "setup_rom.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef SetupAfterColdResetWakeupFromShutDownCfg1 - #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 - #undef SetupAfterColdResetWakeupFromShutDownCfg2 - #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 - #undef SetupAfterColdResetWakeupFromShutDownCfg3 - #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 - #undef SetupGetTrimForAdcShModeEn - #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn - #undef SetupGetTrimForAdcShVbufEn - #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn - #undef SetupGetTrimForAmpcompCtrl - #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl - #undef SetupGetTrimForAmpcompTh1 - #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 - #undef SetupGetTrimForAmpcompTh2 - #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 - #undef SetupGetTrimForAnabypassValue1 - #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 - #undef SetupGetTrimForDblrLoopFilterResetVoltage - #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage - #undef SetupGetTrimForRadcExtCfg - #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg - #undef SetupGetTrimForRcOscLfIBiasTrim - #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim - #undef SetupGetTrimForRcOscLfRtuneCtuneTrim - #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim - #undef SetupGetTrimForXoscHfCtl - #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl - #undef SetupGetTrimForXoscHfFastStart - #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart - #undef SetupGetTrimForXoscHfIbiastherm - #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm - #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio - #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio - #undef SetupSetCacheModeAccordingToCcfgSetting - #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting - #undef SetupSetAonRtcSubSecInc - #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc - #undef SetupStepVddrTrimTo - #define SetupStepVddrTrimTo NOROM_SetupStepVddrTrimTo -#endif - -//***************************************************************************** -// -// Function declarations -// -//***************************************************************************** - -//***************************************************************************** -// -// SetupStepVddrTrimTo -// -//***************************************************************************** -void -SetupStepVddrTrimTo( uint32_t toCode ) -{ - uint32_t pmctlResetctl_reg ; - int32_t targetTrim ; - int32_t currentTrim ; - - targetTrim = SetupSignExtendVddrTrimValue( toCode & ( ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M >> ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S )); - currentTrim = SetupSignExtendVddrTrimValue(( - HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & - ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) >> - ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) ; - - if ( targetTrim != currentTrim ) { - pmctlResetctl_reg = ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) & ~AON_PMCTL_RESETCTL_MCU_WARM_RESET_M ); - if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) { - HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = ( pmctlResetctl_reg & ~AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ); - HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // Wait for VDDR_LOSS_EN setting to propagate - } - - while ( targetTrim != currentTrim ) { - HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) - - if ( targetTrim > currentTrim ) currentTrim++; - else currentTrim--; - - HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) = ( - ( HWREGB( ADI3_BASE + ADI_3_REFSYS_O_DCDCCTL0 ) & ~ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) | - ((((uint32_t)currentTrim) << ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S ) & - ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M ) ); - } - - HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) - - if ( pmctlResetctl_reg & AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M ) { - HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) - HWREG( AON_RTC_BASE + AON_RTC_O_SYNCLF ); // Wait for next edge on SCLK_LF (positive or negative) - HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ) = pmctlResetctl_reg; - HWREG( AON_RTC_BASE + AON_RTC_O_SYNC ); // And finally wait for VDDR_LOSS_EN setting to propagate - } - } -} - -//***************************************************************************** -// -// SetupAfterColdResetWakeupFromShutDownCfg1 -// -//***************************************************************************** -void -SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ) -{ - // Check for CC1352 boost mode - // The combination VDDR_EXT_LOAD=0 and VDDS_BOD_LEVEL=1 is defined to select boost mode - if ((( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_EXT_LOAD ) == 0 ) && - (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDS_BOD_LEVEL ) != 0 ) ) - { - // Set VDDS_BOD trim - using masked write {MASK8:DATA8} - // - TRIM_VDDS_BOD is bits[7:3] of ADI3..REFSYSCTL1 - // - Needs a positive transition on BOD_BG_TRIM_EN (bit[7] of REFSYSCTL3) to - // latch new VDDS BOD. Set to 0 first to guarantee a positive transition. - HWREGB( ADI3_BASE + ADI_O_CLR + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; - // - // VDDS_BOD_LEVEL = 1 means that boost mode is selected - // - Max out the VDDS_BOD trim (=VDDS_BOD_POS_31) - HWREGH( ADI3_BASE + ADI_O_MASK8B + ( ADI_3_REFSYS_O_REFSYSCTL1 * 2 )) = - ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M << 8 ) | - ( ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 ) ; - HWREGB( ADI3_BASE + ADI_O_SET + ADI_3_REFSYS_O_REFSYSCTL3 ) = ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN; - - SetupStepVddrTrimTo(( HWREG( FCFG1_BASE + FCFG1_O_VOLT_TRIM ) & - FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M ) >> - FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S ) ; - } - - // 1. - // Do not allow DCDC to be enabled if in external regulator mode. - // Preventing this by setting both the RECHARGE and the ACTIVE bits bit in the CCFG_MODE_CONF copy register (ccfg_ModeConfReg). - // - // 2. - // Adjusted battery monitor low limit in internal regulator mode. - // This is done by setting AON_BATMON_FLASHPUMPP0_LOWLIM=0 in internal regulator mode. - if ( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) { - ccfg_ModeConfReg |= ( CCFG_MODE_CONF_DCDC_RECHARGE_M | CCFG_MODE_CONF_DCDC_ACTIVE_M ); - } else { - HWREGBITW( AON_BATMON_BASE + AON_BATMON_O_FLASHPUMPP0, AON_BATMON_FLASHPUMPP0_LOWLIM_BITN ) = 0; - } - - // set the RECHARGE source based upon CCFG:MODE_CONF:DCDC_RECHARGE - // Note: Inverse polarity - HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_EN_BITN ) = - ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_RECHARGE_S ) & 1 ) ^ 1 ); - - // set the ACTIVE source based upon CCFG:MODE_CONF:DCDC_ACTIVE - // Note: Inverse polarity - HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL, AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN ) = - ((( ccfg_ModeConfReg >> CCFG_MODE_CONF_DCDC_ACTIVE_S ) & 1 ) ^ 1 ); -} - -//***************************************************************************** -// -// SetupAfterColdResetWakeupFromShutDownCfg2 -// -//***************************************************************************** -void -SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ) -{ - uint32_t ui32Trim; - - // Following sequence is required for using XOSCHF, if not included - // devices crashes when trying to switch to XOSCHF. - // - // Trim CAP settings. Get and set trim value for the ANABYPASS_VALUE1 - // register - ui32Trim = SetupGetTrimForAnabypassValue1( ccfg_ModeConfReg ); - DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL1, ui32Trim); - - // Trim RCOSC_LF. Get and set trim values for the RCOSCLF_RTUNE_TRIM and - // RCOSCLF_CTUNE_TRIM fields in the XOSCLF_RCOSCLF_CTRL register. - ui32Trim = SetupGetTrimForRcOscLfRtuneCtuneTrim(); - DDI16BitfieldWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_LFOSCCTL, - (DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M | - DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M), - DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S, - ui32Trim); - - // Trim XOSCHF IBIAS THERM. Get and set trim value for the - // XOSCHF IBIAS THERM bit field in the ANABYPASS_VALUE2 register. Other - // register bit fields are set to 0. - ui32Trim = SetupGetTrimForXoscHfIbiastherm(); - DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_ANABYPASSVAL2, - ui32Trim< writing to bits[7:4] - ui32Trim = SetupGetTrimForAdcShModeEn( ui32Fcfg1Revision ); - HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = - ( 0x20 | ( ui32Trim << 1 )); - - // Set trim for DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN in accordance to FCFG1 setting - // This is bit[4] in the DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL register - // Using MASK4 write + 1 => writing to bits[7:4] - ui32Trim = SetupGetTrimForAdcShVbufEn( ui32Fcfg1Revision ); - HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 1 ) = - ( 0x10 | ( ui32Trim )); - - // Set trim for the PEAK_DET_ITRIM, HP_BUF_ITRIM and LP_BUF_ITRIM bit fields - // in the DDI0_OSC_O_XOSCHFCTL register in accordance to FCFG1 setting. - // Remaining register bit fields are set to their reset values of 0. - ui32Trim = SetupGetTrimForXoscHfCtl(ui32Fcfg1Revision); - DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_XOSCHFCTL, ui32Trim); - - // Set trim for DBLR_LOOP_FILTER_RESET_VOLTAGE in accordance to FCFG1 setting - // (This is bits [18:17] in DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL) - // (Using MASK4 write + 4 => writing to bits[19:16] => (4*4)) - // (Assuming: DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_S = 17 and - // that DDI_0_OSC_ADCDOUBLERNANOAMPCTL_DBLR_LOOP_FILTER_RESET_VOLTAGE_M = 0x00060000) - ui32Trim = SetupGetTrimForDblrLoopFilterResetVoltage( ui32Fcfg1Revision ); - HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL * 2 ) + 4 ) = - ( 0x60 | ( ui32Trim << 1 )); - - // Update DDI_0_OSC_ATESTCTL_ATESTLF_RCOSCLF_IBIAS_TRIM with data from - // FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM - // This is DDI_0_OSC_O_ATESTCTL bit[7] - // ( DDI_0_OSC_O_ATESTCTL is currently hidden (but=0x00000020)) - // Using MASK4 write + 1 => writing to bits[7:4] - ui32Trim = SetupGetTrimForRcOscLfIBiasTrim( ui32Fcfg1Revision ); - HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( 0x00000020 * 2 ) + 1 ) = - ( 0x80 | ( ui32Trim << 3 )); - - // Update DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM and - // DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO in one write - // This can be simplified since the registers are packed together in the same - // order both in FCFG1 and in the HW register. - // This spans DDI_0_OSC_O_LFOSCCTL bits[23:18] - // Using MASK8 write + 4 => writing to bits[23:16] - ui32Trim = SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( ui32Fcfg1Revision ); - HWREGH( AUX_DDI0_OSC_BASE + DDI_O_MASK8B + ( DDI_0_OSC_O_LFOSCCTL * 2 ) + 4 ) = - ( 0xFC00 | ( ui32Trim << 2 )); - - // Set trim the HPM_IBIAS_WAIT_CNT, LPM_IBIAS_WAIT_CNT and IDAC_STEP bit - // fields in the DDI0_OSC_O_RADCEXTCFG register in accordance to FCFG1 setting. - // Remaining register bit fields are set to their reset values of 0. - ui32Trim = SetupGetTrimForRadcExtCfg(ui32Fcfg1Revision); - DDI32RegWrite(AUX_DDI0_OSC_BASE, DDI_0_OSC_O_RADCEXTCFG, ui32Trim); - -} - -//***************************************************************************** -// -// SetupAfterColdResetWakeupFromShutDownCfg3 -// -//***************************************************************************** -void -SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ) -{ - uint32_t fcfg1OscConf; - uint32_t ui32Trim; - uint32_t currentHfClock; - uint32_t ccfgExtLfClk; - - // Examine the XOSC_FREQ field to select 0x1=HPOSC, 0x2=48MHz XOSC, 0x3=24MHz XOSC - switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_FREQ_M ) >> CCFG_MODE_CONF_XOSC_FREQ_S ) { - case 2 : - // XOSC source is a 48 MHz crystal - // Do nothing (since this is the reset setting) - break; - case 1 : - // XOSC source is HPOSC (trim the HPOSC if this is a chip with HPOSC, otherwise skip trimming and default to 24 MHz XOSC) - - fcfg1OscConf = HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ); - - if (( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_OPTION ) == 0 ) { - // This is a HPOSC chip, apply HPOSC settings - // Set bit DDI_0_OSC_CTL0_HPOSC_MODE_EN (this is bit 14 in DDI_0_OSC_O_CTL0) - HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_HPOSC_MODE_EN; - - // ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN = FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN (1 bit) - // ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO = FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO (4 bits) - // ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET = FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET (4 bits) - // ADI_2_REFSYS_HPOSCCTL0_FILTER_EN = FCFG1_OSC_CONF_HPOSC_FILTER_EN (1 bit) - // ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY = FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY (2 bits) - // ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP = FCFG1_OSC_CONF_HPOSC_SERIES_CAP (2 bits) - // ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS = FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS (1 bit) - - HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL2 ) & - ~( ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M | ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M ) ) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S ) << ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S ) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M ) >> FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S ) << ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S ) ); - HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL1 ) & ~( ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M ) ) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S ) << ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S ) ); - HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) = (( HWREG( ADI2_BASE + ADI_2_REFSYS_O_HPOSCCTL0 ) & - ~( ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M | ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M | ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M | ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M )) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_FILTER_EN_M ) >> FCFG1_OSC_CONF_HPOSC_FILTER_EN_S ) << ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S ) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M ) >> FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S ) << ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S ) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M ) >> FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S ) << ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S ) | - ((( fcfg1OscConf & FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M ) >> FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S ) << ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S ) ); - break; - } - // Not a HPOSC chip - fall through to default - default : - // XOSC source is a 24 MHz crystal (default) - // Set bit DDI_0_OSC_CTL0_XTAL_IS_24M (this is bit 31 in DDI_0_OSC_O_CTL0) - HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XTAL_IS_24M; - break; - } - - // Set XOSC_HF in bypass mode if CCFG is configured for external TCXO - // Please note that it is up to the customer to make sure that the external clock source is up and running before XOSC_HF can be used. - if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO ) == 0 ) { - HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_XOSCHFCTL ) = DDI_0_OSC_XOSCHFCTL_BYPASS; - } - - // Clear DDI_0_OSC_CTL0_CLK_LOSS_EN (ClockLossEventEnable()). This is bit 9 in DDI_0_OSC_O_CTL0. - // This is typically already 0 except on Lizard where it is set in ROM-boot - HWREG( AUX_DDI0_OSC_BASE + DDI_O_CLR + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN; - - // Setting DDI_0_OSC_CTL1_XOSC_HF_FAST_START according to value found in FCFG1 - ui32Trim = SetupGetTrimForXoscHfFastStart(); - HWREGB( AUX_DDI0_OSC_BASE + DDI_O_MASK4B + ( DDI_0_OSC_O_CTL1 * 2 )) = ( 0x30 | ui32Trim ); - - // setup the LF clock based upon CCFG:MODE_CONF:SCLK_LF_OPTION - switch (( ccfg_ModeConfReg & CCFG_MODE_CONF_SCLK_LF_OPTION_M ) >> CCFG_MODE_CONF_SCLK_LF_OPTION_S ) { - case 0 : // XOSC_HF_DLF (XOSCHF/1536) -> SCLK_LF (=31250 Hz) - OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_HF ); - SetupSetAonRtcSubSecInc( 0x8637BD ); // RTC_INCREMENT = 2^38 / frequency - break; - case 1 : // EXTERNAL signal -> SCLK_LF (frequency=2^38/CCFG_EXT_LF_CLK_RTC_INCREMENT) - // Set SCLK_LF to use the same source as SCLK_HF - // Can be simplified a bit since possible return values for HF matches LF settings - currentHfClock = OSCClockSourceGet( OSC_SRC_CLK_HF ); - OSCClockSourceSet( OSC_SRC_CLK_LF, currentHfClock ); - while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != currentHfClock ) { - // Wait until switched - } - ccfgExtLfClk = HWREG( CCFG_BASE + CCFG_O_EXT_LF_CLK ); - SetupSetAonRtcSubSecInc(( ccfgExtLfClk & CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) >> CCFG_EXT_LF_CLK_RTC_INCREMENT_S ); - IOCPortConfigureSet(( ccfgExtLfClk & CCFG_EXT_LF_CLK_DIO_M ) >> CCFG_EXT_LF_CLK_DIO_S, - IOC_PORT_AON_CLK32K, - IOC_STD_INPUT | IOC_HYST_ENABLE ); // Route external clock to AON IOC w/hysteresis - // Set XOSC_LF in bypass mode to allow external 32 kHz clock - HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS; - // Fall through to set XOSC_LF as SCLK_LF source - case 2 : // XOSC_LF -> SLCK_LF (32768 Hz) - OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF ); - break; - default : // (=3) RCOSC_LF - OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF ); - break; - } - - // Update ADI_4_AUX_ADCREF1_VTRIM with value from FCFG1 - HWREGB( AUX_ADI4_BASE + ADI_4_AUX_O_ADCREF1 ) = - ((( HWREG( FCFG1_BASE + FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT ) >> - FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S ) << - ADI_4_AUX_ADCREF1_VTRIM_S ) & - ADI_4_AUX_ADCREF1_VTRIM_M ); - - // Sync with AON - SysCtrlAonSync(); -} - -//***************************************************************************** -// -// SetupGetTrimForAnabypassValue1 -// -//***************************************************************************** -uint32_t -SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ) -{ - uint32_t ui32Fcfg1Value ; - uint32_t ui32XoscHfRow ; - uint32_t ui32XoscHfCol ; - uint32_t ui32TrimValue ; - - // Use device specific trim values located in factory configuration - // area for the XOSC_HF_COLUMN_Q12 and XOSC_HF_ROW_Q12 bit fields in - // the ANABYPASS_VALUE1 register. Value for the other bit fields - // are set to 0. - - ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP); - ui32XoscHfRow = (( ui32Fcfg1Value & - FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M ) >> - FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S ); - ui32XoscHfCol = (( ui32Fcfg1Value & - FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M ) >> - FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S ); - - if (( ccfg_ModeConfReg & CCFG_MODE_CONF_XOSC_CAP_MOD ) == 0 ) { - // XOSC_CAP_MOD = 0 means: CAP_ARRAY_DELTA is in use -> Apply compensation - // XOSC_CAPARRAY_DELTA is located in bit[15:8] of ccfg_ModeConfReg - // Note: HW_REV_DEPENDENT_IMPLEMENTATION. Field width is not given by - // a define and sign extension must therefore be hard coded. - // ( A small test program is created verifying the code lines below: - // Ref.: ..\test\small_standalone_test_programs\CapArrayDeltaAdjust_test.c) - int32_t i32CustomerDeltaAdjust = - (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ))) - >> ( 32 - CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W )); - - while ( i32CustomerDeltaAdjust < 0 ) { - ui32XoscHfCol >>= 1; // COL 1 step down - if ( ui32XoscHfCol == 0 ) { // if COL below minimum - ui32XoscHfCol = 0xFFFF; // Set COL to maximum - ui32XoscHfRow >>= 1; // ROW 1 step down - if ( ui32XoscHfRow == 0 ) { // if ROW below minimum - ui32XoscHfRow = 1; // Set both ROW and COL - ui32XoscHfCol = 1; // to minimum - } - } - i32CustomerDeltaAdjust++; - } - while ( i32CustomerDeltaAdjust > 0 ) { - ui32XoscHfCol = ( ui32XoscHfCol << 1 ) | 1; // COL 1 step up - if ( ui32XoscHfCol > 0xFFFF ) { // if COL above maximum - ui32XoscHfCol = 1; // Set COL to minimum - ui32XoscHfRow = ( ui32XoscHfRow << 1 ) | 1; // ROW 1 step up - if ( ui32XoscHfRow > 0xF ) { // if ROW above maximum - ui32XoscHfRow = 0xF; // Set both ROW and COL - ui32XoscHfCol = 0xFFFF; // to maximum - } - } - i32CustomerDeltaAdjust--; - } - } - - ui32TrimValue = (( ui32XoscHfRow << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S ) | - ( ui32XoscHfCol << DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S ) ); - - return (ui32TrimValue); -} - -//***************************************************************************** -// -// SetupGetTrimForRcOscLfRtuneCtuneTrim -// -//***************************************************************************** -uint32_t -SetupGetTrimForRcOscLfRtuneCtuneTrim( void ) -{ - uint32_t ui32TrimValue; - - // Use device specific trim values located in factory configuration - // area - ui32TrimValue = - ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & - FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M)>> - FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S)<< - DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S; - - ui32TrimValue |= - ((HWREG(FCFG1_BASE + FCFG1_O_CONFIG_OSC_TOP) & - FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M)>> - FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S)<< - DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S; - - return(ui32TrimValue); -} - -//***************************************************************************** -// -// SetupGetTrimForXoscHfIbiastherm -// -//***************************************************************************** -uint32_t -SetupGetTrimForXoscHfIbiastherm( void ) -{ - uint32_t ui32TrimValue; - - // Use device specific trim value located in factory configuration - // area - ui32TrimValue = - (HWREG(FCFG1_BASE + FCFG1_O_ANABYPASS_VALUE2) & - FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M)>> - FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S; - - return(ui32TrimValue); -} - -//***************************************************************************** -// -// SetupGetTrimForAmpcompTh2 -// -//***************************************************************************** -uint32_t -SetupGetTrimForAmpcompTh2( void ) -{ - uint32_t ui32TrimValue; - uint32_t ui32Fcfg1Value; - - // Use device specific trim value located in factory configuration - // area. All defined register bit fields have corresponding trim - // value in the factory configuration area - ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH2); - ui32TrimValue = ((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M)>> - FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S)<< - DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S; - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M)>> - FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S)<< - DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M)>> - FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S)<< - DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M)>> - FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S)<< - DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S); - - return(ui32TrimValue); -} - -//***************************************************************************** -// -// SetupGetTrimForAmpcompTh1 -// -//***************************************************************************** -uint32_t -SetupGetTrimForAmpcompTh1( void ) -{ - uint32_t ui32TrimValue; - uint32_t ui32Fcfg1Value; - - // Use device specific trim values located in factory configuration - // area. All defined register bit fields have a corresponding trim - // value in the factory configuration area - ui32Fcfg1Value = HWREG(FCFG1_BASE + FCFG1_O_AMPCOMP_TH1); - ui32TrimValue = (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M)>> - FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S)<< - DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M)>> - FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S)<< - DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M)>> - FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S)<< - DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M)>> - FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S)<< - DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S); - - return(ui32TrimValue); -} - -//***************************************************************************** -// -// SetupGetTrimForAmpcompCtrl -// -//***************************************************************************** -uint32_t -SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ) -{ - uint32_t ui32TrimValue ; - uint32_t ui32Fcfg1Value ; - uint32_t ibiasOffset ; - uint32_t ibiasInit ; - uint32_t modeConf1 ; - int32_t deltaAdjust ; - - // Use device specific trim values located in factory configuration - // area. Register bit fields without trim values in the factory - // configuration area will be set to the value of 0. - ui32Fcfg1Value = HWREG( FCFG1_BASE + FCFG1_O_AMPCOMP_CTRL1 ); - - ibiasOffset = ( ui32Fcfg1Value & - FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M ) >> - FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S ; - ibiasInit = ( ui32Fcfg1Value & - FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M ) >> - FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S ; - - if (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) == 0 ) { - // Adjust with DELTA_IBIAS_OFFSET and DELTA_IBIAS_INIT from CCFG - modeConf1 = HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ); - - // Both fields are signed 4-bit values. This is an assumption when doing the sign extension. - deltaAdjust = - (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ))) - >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W )); - deltaAdjust += (int32_t)ibiasOffset; - if ( deltaAdjust < 0 ) { - deltaAdjust = 0; - } - if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S )) { - deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ); - } - ibiasOffset = (uint32_t)deltaAdjust; - - deltaAdjust = - (((int32_t)( modeConf1 << ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ))) - >> ( 32 - CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W )); - deltaAdjust += (int32_t)ibiasInit; - if ( deltaAdjust < 0 ) { - deltaAdjust = 0; - } - if ( deltaAdjust > ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S )) { - deltaAdjust = ( DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M >> DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ); - } - ibiasInit = (uint32_t)deltaAdjust; - } - ui32TrimValue = ( ibiasOffset << DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S ) | - ( ibiasInit << DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S ) ; - - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M)>> - FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S)<< - DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_CTRL1_CAP_STEP_M)>> - FCFG1_AMPCOMP_CTRL1_CAP_STEP_S)<< - DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S); - ui32TrimValue |= (((ui32Fcfg1Value & - FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M)>> - FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S)<< - DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S); - - if ( ui32Fcfg1Revision >= 0x00000022 ) { - ui32TrimValue |= ((( ui32Fcfg1Value & - FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M ) >> - FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S ) << - DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S ); - } - - return(ui32TrimValue); -} - -//***************************************************************************** -// -// SetupGetTrimForDblrLoopFilterResetVoltage -// -//***************************************************************************** -uint32_t -SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ) -{ - uint32_t dblrLoopFilterResetVoltageValue = 0; // Reset value - - if ( ui32Fcfg1Revision >= 0x00000020 ) { - dblrLoopFilterResetVoltageValue = ( HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ) & - FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M ) >> - FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S; - } - - return ( dblrLoopFilterResetVoltageValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForAdcShModeEn -// -//***************************************************************************** -uint32_t -SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ) -{ - uint32_t getTrimForAdcShModeEnValue = 1; // Recommended default setting - - if ( ui32Fcfg1Revision >= 0x00000022 ) { - getTrimForAdcShModeEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & - FCFG1_OSC_CONF_ADC_SH_MODE_EN_M ) >> - FCFG1_OSC_CONF_ADC_SH_MODE_EN_S; - } - - return ( getTrimForAdcShModeEnValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForAdcShVbufEn -// -//***************************************************************************** -uint32_t -SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ) -{ - uint32_t getTrimForAdcShVbufEnValue = 1; // Recommended default setting - - if ( ui32Fcfg1Revision >= 0x00000022 ) { - getTrimForAdcShVbufEnValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & - FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M ) >> - FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S; - } - - return ( getTrimForAdcShVbufEnValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForXoscHfCtl -// -//***************************************************************************** -uint32_t -SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ) -{ - uint32_t getTrimForXoschfCtlValue = 0; // Recommended default setting - uint32_t fcfg1Data; - - if ( ui32Fcfg1Revision >= 0x00000020 ) { - fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); - getTrimForXoschfCtlValue = - ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M ) >> - FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S ) << - DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S); - - getTrimForXoschfCtlValue |= - ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M ) >> - FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S ) << - DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S); - - getTrimForXoschfCtlValue |= - ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M ) >> - FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S ) << - DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S); - } - - return ( getTrimForXoschfCtlValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForXoscHfFastStart -// -//***************************************************************************** -uint32_t -SetupGetTrimForXoscHfFastStart( void ) -{ - uint32_t ui32XoscHfFastStartValue ; - - // Get value from FCFG1 - ui32XoscHfFastStartValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & - FCFG1_OSC_CONF_XOSC_HF_FAST_START_M ) >> - FCFG1_OSC_CONF_XOSC_HF_FAST_START_S; - - return ( ui32XoscHfFastStartValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForRadcExtCfg -// -//***************************************************************************** -uint32_t -SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ) -{ - uint32_t getTrimForRadcExtCfgValue = 0x403F8000; // Recommended default setting - uint32_t fcfg1Data; - - if ( ui32Fcfg1Revision >= 0x00000020 ) { - fcfg1Data = HWREG( FCFG1_BASE + FCFG1_O_MISC_OTP_DATA_1 ); - getTrimForRadcExtCfgValue = - ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M ) >> - FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S ) << - DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S); - - getTrimForRadcExtCfgValue |= - ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M ) >> - FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S ) << - DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S); - - getTrimForRadcExtCfgValue |= - ( ( ( fcfg1Data & FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M ) >> - FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S ) << - DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S); - } - - return ( getTrimForRadcExtCfgValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForRcOscLfIBiasTrim -// -//***************************************************************************** -uint32_t -SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ) -{ - uint32_t trimForRcOscLfIBiasTrimValue = 0; // Default value - - if ( ui32Fcfg1Revision >= 0x00000022 ) { - trimForRcOscLfIBiasTrimValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & - FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M ) >> - FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S ; - } - - return ( trimForRcOscLfIBiasTrimValue ); -} - -//***************************************************************************** -// -// SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio -// -//***************************************************************************** -uint32_t -SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ) -{ - uint32_t trimForXoscLfRegulatorAndCmirrwrRatioValue = 0; // Default value for both fields - - if ( ui32Fcfg1Revision >= 0x00000022 ) { - trimForXoscLfRegulatorAndCmirrwrRatioValue = ( HWREG( FCFG1_BASE + FCFG1_O_OSC_CONF ) & - ( FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M | - FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M )) >> - FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S ; - } - - return ( trimForXoscLfRegulatorAndCmirrwrRatioValue ); -} - -//***************************************************************************** -// -// SetupSetCacheModeAccordingToCcfgSetting -// -//***************************************************************************** -void -SetupSetCacheModeAccordingToCcfgSetting( void ) -{ - // - Make sure to enable aggressive VIMS clock gating for power optimization - // Only for PG2 devices. - // - Enable cache prefetch enable as default setting - // (Slightly higher power consumption, but higher CPU performance) - // - IF ( CCFG_..._DIS_GPRAM == 1 ) - // then: Enable cache (set cache mode = 1), even if set by ROM boot code - // (This is done because it's not set by boot code when running inside - // a debugger supporting the Halt In Boot (HIB) functionality). - // else: Set MODE_GPRAM if not already set (see inline comments as well) - uint32_t vimsCtlMode0 ; - - while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { - // Do nothing - wait for an eventual ongoing mode change to complete. - // (There should typically be no wait time here, but need to be sure) - } - - // Note that Mode=0 is equal to MODE_GPRAM - vimsCtlMode0 = (( HWREG( VIMS_BASE + VIMS_O_CTL ) & ~VIMS_CTL_MODE_M ) | VIMS_CTL_DYN_CG_EN_M | VIMS_CTL_PREF_EN_M ); - - - if ( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM ) { - // Enable cache (and hence disable GPRAM) - HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_CACHE ); - } else if (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_GPRAM ) { - // GPRAM is enabled in CCFG but not selected - // Note: It is recommended to go via MODE_OFF when switching to MODE_GPRAM - HWREG( VIMS_BASE + VIMS_O_CTL ) = ( vimsCtlMode0 | VIMS_CTL_MODE_OFF ); - while (( HWREG( VIMS_BASE + VIMS_O_STAT ) & VIMS_STAT_MODE_M ) != VIMS_STAT_MODE_OFF ) { - // Do nothing - wait for an eventual mode change to complete (This goes fast). - } - HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; - } else { - // Correct mode, but make sure PREF_EN and DYN_CG_EN always are set - HWREG( VIMS_BASE + VIMS_O_CTL ) = vimsCtlMode0; - } -} - -//***************************************************************************** -// -// SetupSetAonRtcSubSecInc -// -//***************************************************************************** -void -SetupSetAonRtcSubSecInc( uint32_t subSecInc ) -{ - // Loading a new RTCSUBSECINC value is done in 5 steps: - // 1. Write bit[15:0] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC0 - // 2. Write bit[23:16] of new SUBSECINC value to AUX_SYSIF_O_RTCSUBSECINC1 - // 3. Set AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ - // 4. Wait for AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK - // 5. Clear AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ - HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC0 ) = (( subSecInc ) & AUX_SYSIF_RTCSUBSECINC0_INC15_0_M ); - HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINC1 ) = (( subSecInc >> 16 ) & AUX_SYSIF_RTCSUBSECINC1_INC23_16_M ); - - HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ; - while( ! ( HWREGBITW( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL, AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN ))); - HWREG( AUX_SYSIF_BASE + AUX_SYSIF_O_RTCSUBSECINCCTL ) = 0; -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h deleted file mode 100644 index e06ba293149..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom.h +++ /dev/null @@ -1,469 +0,0 @@ -/****************************************************************************** -* Filename: setup_rom.h -* Revised: 2018-10-24 11:23:04 +0200 (Wed, 24 Oct 2018) -* Revision: 52993 -* -* Description: Prototypes and defines for the setup API. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup setup_rom_api -//! @{ -// -//***************************************************************************** - -#ifndef __SETUP_ROM_H__ -#define __SETUP_ROM_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -// Hardware headers -#include "../inc/hw_types.h" -// Driverlib headers -// - None needed - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define SetupAfterColdResetWakeupFromShutDownCfg1 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 - #define SetupAfterColdResetWakeupFromShutDownCfg2 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 - #define SetupAfterColdResetWakeupFromShutDownCfg3 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 - #define SetupGetTrimForAdcShModeEn NOROM_SetupGetTrimForAdcShModeEn - #define SetupGetTrimForAdcShVbufEn NOROM_SetupGetTrimForAdcShVbufEn - #define SetupGetTrimForAmpcompCtrl NOROM_SetupGetTrimForAmpcompCtrl - #define SetupGetTrimForAmpcompTh1 NOROM_SetupGetTrimForAmpcompTh1 - #define SetupGetTrimForAmpcompTh2 NOROM_SetupGetTrimForAmpcompTh2 - #define SetupGetTrimForAnabypassValue1 NOROM_SetupGetTrimForAnabypassValue1 - #define SetupGetTrimForDblrLoopFilterResetVoltage NOROM_SetupGetTrimForDblrLoopFilterResetVoltage - #define SetupGetTrimForRadcExtCfg NOROM_SetupGetTrimForRadcExtCfg - #define SetupGetTrimForRcOscLfIBiasTrim NOROM_SetupGetTrimForRcOscLfIBiasTrim - #define SetupGetTrimForRcOscLfRtuneCtuneTrim NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim - #define SetupGetTrimForXoscHfCtl NOROM_SetupGetTrimForXoscHfCtl - #define SetupGetTrimForXoscHfFastStart NOROM_SetupGetTrimForXoscHfFastStart - #define SetupGetTrimForXoscHfIbiastherm NOROM_SetupGetTrimForXoscHfIbiastherm - #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio - #define SetupSetCacheModeAccordingToCcfgSetting NOROM_SetupSetCacheModeAccordingToCcfgSetting - #define SetupSetAonRtcSubSecInc NOROM_SetupSetAonRtcSubSecInc - #define SetupStepVddrTrimTo NOROM_SetupStepVddrTrimTo -#endif - -//***************************************************************************** -// -//! \brief First part of configuration required after cold reset and when waking up from shutdown. -//! -//! Configures the following based on settings in CCFG (Customer Configuration area: -//! - Boost mode for CC13xx devices -//! - Minimal VDDR voltage threshold used during sleep mode -//! - DCDC functionality: -//! - Selects if DCDC or GLDO regulator will be used for VDDR in active mode -//! - Selects if DCDC or GLDO regulator will be used for VDDR in sleep mode -//! -//! In addition the battery monitor low limit for internal regulator mode is set -//! to a hard coded value. -//! -//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register -//! -//! \return None -// -//***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg1( uint32_t ccfg_ModeConfReg ); - -//***************************************************************************** -// -//! \brief Second part of configuration required after cold reset and when waking up from shutdown. -//! -//! Configures and trims functionalites required for use of XOSC_HF. -//! The configurations and trimmings are based on settings in FCFG1 (Factory -//! Configuration area) and partly on \c ccfg_ModeConfReg. -//! -//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register -//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register -//! -//! \return None -// -//***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg2( uint32_t ui32Fcfg1Revision, uint32_t ccfg_ModeConfReg ); - -//***************************************************************************** -// -//! \brief Third part of configuration required after cold reset and when waking up from shutdown. -//! -//! Configures the following: -//! - XOSC source selection based on \c ccfg_ModeConfReg. If HPOSC is selected on a -//! HPOSC device the oscillator is configured based on settings in FCFG1 (Factory -//! Configuration area). -//! - Clock loss detection is disabled. Will be re-enabled by TIRTOS power driver. -//! - Duration of the XOSC_HF fast startup mode based on FCFG1 setting. -//! - SCLK_LF based on \c ccfg_ModeConfReg. -//! - Output voltage of ADC fixed reference based on FCFG1 setting. -//! -//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register -//! -//! \return None -// -//***************************************************************************** -extern void SetupAfterColdResetWakeupFromShutDownCfg3( uint32_t ccfg_ModeConfReg ); - -//***************************************************************************** -// -//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_MODE_EN setting. -//! -//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register -//! -//! \return Returns the trim value from FCFG1. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForAdcShModeEn( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the trim value from FCFG1 to be used as ADC_SH_VBUF_EN setting. -//! -//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register -//! -//! \return Returns the trim value from FCFG1. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForAdcShVbufEn( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the AMPCOMP_CTRL register in OSC_DIG. -//! -//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompCtrl( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the AMPCOMP_TH1 register in OSC_DIG. -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompTh1( void ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the AMPCOMP_TH2 register in OSC_DIG. -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForAmpcompTh2( void ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the ANABYPASS_VALUE1 register in OSC_DIG. -//! -//! \param ccfg_ModeConfReg is the value of the CCFG_O_MODE_CONF_1 register -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForAnabypassValue1( uint32_t ccfg_ModeConfReg ); - -//***************************************************************************** -// -//! \brief Returns the trim value from FCFG1 to be used as DBLR_LOOP_FILTER_RESET_VOLTAGE setting. -//! -//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register -//! -//! \return Returns the trim value from FCFG1. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForDblrLoopFilterResetVoltage( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the RADCEXTCFG register in OSC_DIG. -//! -//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForRadcExtCfg( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the FCFG1 OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM. -//! -//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register -//! -//! \return Returns the trim value from FCFG1. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForRcOscLfIBiasTrim( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the RCOSCLF_RTUNE_TRIM and the -//! RCOSCLF_CTUNE_TRIM bit fields in the XOSCLF_RCOSCLF_CTRL register in OSC_DIG. -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForRcOscLfRtuneCtuneTrim( void ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the XOSCHFCTL register in OSC_DIG. -//! -//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfCtl( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used as OSC_DIG:CTL1.XOSC_HF_FAST_START. -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfFastStart( void ); - -//***************************************************************************** -// -//! \brief Returns the trim value to be used for the XOSC_HF_IBIASTHERM bit field in -//! the ANABYPASS_VALUE2 register in OSC_DIG. -//! -//! \return Returns the trim value. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForXoscHfIbiastherm( void ); - -//***************************************************************************** -// -//! \brief Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet -//! spanning bits [5:0] in the returned value. -//! -//! \param ui32Fcfg1Revision is the value of the FCFG1_O_FCFG1_REVISION register -//! -//! \return Returns XOSCLF_REGULATOR_TRIM and XOSCLF_CMIRRWR_RATIO as one packet. -// -//***************************************************************************** -extern uint32_t SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio( uint32_t ui32Fcfg1Revision ); - -//***************************************************************************** -// -//! \brief Sign extend the VDDR_TRIM setting (special format ranging from -10 to +21) -//! -//! \param ui32VddrTrimVal -//! -//! \return Returns Sign extended VDDR_TRIM setting. -// -//***************************************************************************** -__STATIC_INLINE int32_t -SetupSignExtendVddrTrimValue( uint32_t ui32VddrTrimVal ) -{ - // The VDDR trim value is 5 bits representing the range from -10 to +21 - // (where -10=0x16, -1=0x1F, 0=0x00, 1=0x01 and +21=0x15) - int32_t i32SignedVddrVal = ui32VddrTrimVal; - if ( i32SignedVddrVal > 0x15 ) { - i32SignedVddrVal -= 0x20; - } - return ( i32SignedVddrVal ); -} - -//***************************************************************************** -// -//! \brief Set correct VIMS_MODE according to CCFG setting (CACHE or GPRAM) -//! -//! \return None -// -//***************************************************************************** -extern void SetupSetCacheModeAccordingToCcfgSetting( void ); - -//***************************************************************************** -// -//! \brief Doing the tricky stuff needed to enter new RTCSUBSECINC value -//! -//! \param subSecInc -//! -//! \return None -// -//***************************************************************************** -extern void SetupSetAonRtcSubSecInc( uint32_t subSecInc ); - -//***************************************************************************** -// -//! \brief Set VDDR boost mode (by setting VDDR_TRIM to FCFG1..VDDR_TRIM_HH and -//! setting VDDS_BOD to max) -//! -//! \param toCode specifies the target VDDR trim value. -//! The input parameter \c toCode can be either the signed extended -//! trim value or holding the trim code bits only. -//! -//! \return None -// -//***************************************************************************** -extern void SetupStepVddrTrimTo( uint32_t toCode ); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg1 - #undef SetupAfterColdResetWakeupFromShutDownCfg1 - #define SetupAfterColdResetWakeupFromShutDownCfg1 ROM_SetupAfterColdResetWakeupFromShutDownCfg1 - #endif - #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg2 - #undef SetupAfterColdResetWakeupFromShutDownCfg2 - #define SetupAfterColdResetWakeupFromShutDownCfg2 ROM_SetupAfterColdResetWakeupFromShutDownCfg2 - #endif - #ifdef ROM_SetupAfterColdResetWakeupFromShutDownCfg3 - #undef SetupAfterColdResetWakeupFromShutDownCfg3 - #define SetupAfterColdResetWakeupFromShutDownCfg3 ROM_SetupAfterColdResetWakeupFromShutDownCfg3 - #endif - #ifdef ROM_SetupGetTrimForAdcShModeEn - #undef SetupGetTrimForAdcShModeEn - #define SetupGetTrimForAdcShModeEn ROM_SetupGetTrimForAdcShModeEn - #endif - #ifdef ROM_SetupGetTrimForAdcShVbufEn - #undef SetupGetTrimForAdcShVbufEn - #define SetupGetTrimForAdcShVbufEn ROM_SetupGetTrimForAdcShVbufEn - #endif - #ifdef ROM_SetupGetTrimForAmpcompCtrl - #undef SetupGetTrimForAmpcompCtrl - #define SetupGetTrimForAmpcompCtrl ROM_SetupGetTrimForAmpcompCtrl - #endif - #ifdef ROM_SetupGetTrimForAmpcompTh1 - #undef SetupGetTrimForAmpcompTh1 - #define SetupGetTrimForAmpcompTh1 ROM_SetupGetTrimForAmpcompTh1 - #endif - #ifdef ROM_SetupGetTrimForAmpcompTh2 - #undef SetupGetTrimForAmpcompTh2 - #define SetupGetTrimForAmpcompTh2 ROM_SetupGetTrimForAmpcompTh2 - #endif - #ifdef ROM_SetupGetTrimForAnabypassValue1 - #undef SetupGetTrimForAnabypassValue1 - #define SetupGetTrimForAnabypassValue1 ROM_SetupGetTrimForAnabypassValue1 - #endif - #ifdef ROM_SetupGetTrimForDblrLoopFilterResetVoltage - #undef SetupGetTrimForDblrLoopFilterResetVoltage - #define SetupGetTrimForDblrLoopFilterResetVoltage ROM_SetupGetTrimForDblrLoopFilterResetVoltage - #endif - #ifdef ROM_SetupGetTrimForRadcExtCfg - #undef SetupGetTrimForRadcExtCfg - #define SetupGetTrimForRadcExtCfg ROM_SetupGetTrimForRadcExtCfg - #endif - #ifdef ROM_SetupGetTrimForRcOscLfIBiasTrim - #undef SetupGetTrimForRcOscLfIBiasTrim - #define SetupGetTrimForRcOscLfIBiasTrim ROM_SetupGetTrimForRcOscLfIBiasTrim - #endif - #ifdef ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim - #undef SetupGetTrimForRcOscLfRtuneCtuneTrim - #define SetupGetTrimForRcOscLfRtuneCtuneTrim ROM_SetupGetTrimForRcOscLfRtuneCtuneTrim - #endif - #ifdef ROM_SetupGetTrimForXoscHfCtl - #undef SetupGetTrimForXoscHfCtl - #define SetupGetTrimForXoscHfCtl ROM_SetupGetTrimForXoscHfCtl - #endif - #ifdef ROM_SetupGetTrimForXoscHfFastStart - #undef SetupGetTrimForXoscHfFastStart - #define SetupGetTrimForXoscHfFastStart ROM_SetupGetTrimForXoscHfFastStart - #endif - #ifdef ROM_SetupGetTrimForXoscHfIbiastherm - #undef SetupGetTrimForXoscHfIbiastherm - #define SetupGetTrimForXoscHfIbiastherm ROM_SetupGetTrimForXoscHfIbiastherm - #endif - #ifdef ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio - #undef SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio - #define SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio ROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio - #endif - #ifdef ROM_SetupSetCacheModeAccordingToCcfgSetting - #undef SetupSetCacheModeAccordingToCcfgSetting - #define SetupSetCacheModeAccordingToCcfgSetting ROM_SetupSetCacheModeAccordingToCcfgSetting - #endif - #ifdef ROM_SetupSetAonRtcSubSecInc - #undef SetupSetAonRtcSubSecInc - #define SetupSetAonRtcSubSecInc ROM_SetupSetAonRtcSubSecInc - #endif - #ifdef ROM_SetupStepVddrTrimTo - #undef SetupStepVddrTrimTo - #define SetupStepVddrTrimTo ROM_SetupStepVddrTrimTo - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SETUP_ROM_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h deleted file mode 100644 index 072e4eedf76..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/setup_rom_doc.h +++ /dev/null @@ -1,44 +0,0 @@ -/****************************************************************************** -* Filename: setup_rom_doc.h -* Revised: 2017-06-05 12:13:49 +0200 (ma, 05 jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup setup_rom_api -//! @{ -//! -//! This module contains functions from the Setup API which are likely to be in ROM. -//! -//! \note Do not use functions from this module directly! This module is only to be used by -//! SetupTrimDevice(). -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.c deleted file mode 100644 index 814e73729e0..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.c +++ /dev/null @@ -1,272 +0,0 @@ -/****************************************************************************** -* Filename: sha2.c -* Revised: 2018-04-17 15:57:27 +0200 (Tue, 17 Apr 2018) -* Revision: 51892 -* -* Description: Driver for the SHA-2 functions of the crypto module -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "sha2.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef SHA2StartDMAOperation - #define SHA2StartDMAOperation NOROM_SHA2StartDMAOperation - #undef SHA2WaitForIRQFlags - #define SHA2WaitForIRQFlags NOROM_SHA2WaitForIRQFlags - #undef SHA2ComputeInitialHash - #define SHA2ComputeInitialHash NOROM_SHA2ComputeInitialHash - #undef SHA2ComputeIntermediateHash - #define SHA2ComputeIntermediateHash NOROM_SHA2ComputeIntermediateHash - #undef SHA2ComputeFinalHash - #define SHA2ComputeFinalHash NOROM_SHA2ComputeFinalHash - #undef SHA2ComputeHash - #define SHA2ComputeHash NOROM_SHA2ComputeHash -#endif - - -static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash); - - -//***************************************************************************** -// -// Start a SHA-2 DMA operation. -// -//***************************************************************************** -void SHA2StartDMAOperation(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length) -{ - - // Clear any outstanding events. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = CRYPTO_IRQCLR_RESULT_AVAIL_M | CRYPTO_IRQEN_DMA_IN_DONE_M; - - while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); - - if (channel0Addr) { - // Configure the DMA controller - enable both DMA channels. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH0CTL, CRYPTO_DMACH0CTL_EN_BITN) = 1; - - // Base address of the payload data in ext. memory. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0EXTADDR) = (uint32_t)channel0Addr; - - // Payload data length in bytes, equal to the cipher text length. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH0LEN) = channel0Length; - } - - if (channel1Addr) { - // Enable DMA channel 1. - HWREGBITW(CRYPTO_BASE + CRYPTO_O_DMACH1CTL, CRYPTO_DMACH1CTL_EN_BITN) = 1; - - // Base address of the output data buffer. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1EXTADDR) = (uint32_t)channel1Addr; - - // Output data length in bytes, equal to the cipher text length. - HWREG(CRYPTO_BASE + CRYPTO_O_DMACH1LEN) = channel1Length; - } -} - -//***************************************************************************** -// -// Poll the IRQ status register and return. -// -//***************************************************************************** -uint32_t SHA2WaitForIRQFlags(uint32_t irqFlags) -{ - uint32_t irqTrigger = 0; - // Wait for the DMA operation to complete. Add a delay to make sure we are - // not flooding the bus with requests too much. - do { - CPUdelay(1); - } - while(!(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M))); - - // Save the IRQ trigger source - irqTrigger = HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT); - - // Clear IRQ flags - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = irqFlags; - - while(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT) & irqFlags & (CRYPTO_IRQSTAT_DMA_IN_DONE_M | CRYPTO_IRQSTAT_RESULT_AVAIL_M)); - - return irqTrigger; -} - -//***************************************************************************** -// -// Start a new SHA-2 hash operation. -// -//***************************************************************************** -uint32_t SHA2ComputeInitialHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength) -{ - ASSERT(message); - ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || - (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || - (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || - (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); - ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); - - return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, initialMessageLength, initialMessageLength, hashAlgorithm, true, false); -} - -//***************************************************************************** -// -// Start an intermediate SHA-2 hash operation. -// -//***************************************************************************** -uint32_t SHA2ComputeIntermediateHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength) -{ - ASSERT(message); - ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); - ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || - (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || - (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || - (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); - - return SHA2ExecuteHash(message, (uint8_t *)intermediateDigest, intermediateDigest, 0, intermediateMessageLength, hashAlgorithm, false, false); -} - -//***************************************************************************** -// -// Start an intermediate SHA-2 hash operation and finalize it. -// -//***************************************************************************** -uint32_t SHA2ComputeFinalHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm) -{ - ASSERT(message); - ASSERT(totalMsgLength); - ASSERT(!(intermediateDigest == NULL) && !((uint32_t)intermediateDigest & 0x03)); - ASSERT(resultDigest); - ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || - (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || - (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || - (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); - - return SHA2ExecuteHash(message, resultDigest, intermediateDigest, totalMsgLength, messageLength, hashAlgorithm, false, true); -} - -//***************************************************************************** -// -// Start and finalize a new SHA-2 hash operation. -// -//***************************************************************************** -uint32_t SHA2ComputeHash(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm) -{ - ASSERT(message); - ASSERT(totalMsgLength); - ASSERT(resultDigest); - ASSERT((hashAlgorithm == SHA2_MODE_SELECT_SHA224) || - (hashAlgorithm == SHA2_MODE_SELECT_SHA256) || - (hashAlgorithm == SHA2_MODE_SELECT_SHA384) || - (hashAlgorithm == SHA2_MODE_SELECT_SHA512)); - - return SHA2ExecuteHash(message, resultDigest, 0, totalMsgLength, totalMsgLength, hashAlgorithm, true, true); -} - -//***************************************************************************** -// -// Start any SHA-2 hash operation. -// -//***************************************************************************** -static uint32_t SHA2ExecuteHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm, bool initialHash, bool finalHash) -{ - uint8_t digestLength = 0; - uint32_t dmaAlgorithmSelect = 0; - - SHA2ClearDigestAvailableFlag(); - - switch (hashAlgorithm) { - case SHA2_MODE_SELECT_SHA224: - digestLength = SHA2_SHA224_DIGEST_LENGTH_BYTES; - dmaAlgorithmSelect = SHA2_ALGSEL_SHA256; - break; - case SHA2_MODE_SELECT_SHA256: - digestLength = SHA2_SHA256_DIGEST_LENGTH_BYTES; - dmaAlgorithmSelect = SHA2_ALGSEL_SHA256; - break; - case SHA2_MODE_SELECT_SHA384: - digestLength = SHA2_SHA384_DIGEST_LENGTH_BYTES; - dmaAlgorithmSelect = SHA2_ALGSEL_SHA512; - break; - case SHA2_MODE_SELECT_SHA512: - digestLength = SHA2_SHA512_DIGEST_LENGTH_BYTES; - dmaAlgorithmSelect = SHA2_ALGSEL_SHA512; - break; - default: - return SHA2_INVALID_ALGORITHM; - } - - if (initialHash && finalHash) { - // The empty string is a perfectly valid message. It obviously has a length of 0. The DMA cannot - // handle running with a transfer length of 0. This workaround depends on the hash engine adding the - // trailing 1 bit and 0-padding bits after the DMAtransfer is complete and not in the DMA itself. - // totalMsgLength is purposefully not altered as it is appended to the end of the message during finalization - // and determines how many padding-bytes are added. - // Altering totalMsgLength would alter the final hash digest. - // Because totalMsgLength specifies that the message is of length 0, the content of the byte loaded - // through the DMA is irrelevant. It is overwritten internally in the hash engine. - messageLength = messageLength ? messageLength : 1; - } - - // Setting the incorrect number of bits here leads to the calculation of the correct result - // but a failure to read them out. - // The tag bit is set to read out the digest via DMA rather than through the slave interface. - SHA2SelectAlgorithm(dmaAlgorithmSelect | (resultDigest ? SHA2_ALGSEL_TAG : 0)); - SHA2IntClear(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); - SHA2IntEnable(SHA2_DMA_IN_DONE | SHA2_RESULT_RDY); - - HWREG(CRYPTO_BASE + CRYPTO_O_HASHMODE) = hashAlgorithm | (initialHash ? CRYPTO_HASHMODE_NEW_HASH_M : 0); - - // Only load the intermediate digest if requested. - if (intermediateDigest && !initialHash) { - SHA2SetDigest(intermediateDigest, digestLength); - } - - // If this is the final hash, finalization is required. This means appending a 1 bit, padding the message until this section - // is 448 bytes long, and adding the 64 bit total length of the message in bits. Thankfully, this is all done in hardware. - if (finalHash) { - // This specific length must be specified in bits not bytes. - SHA2SetMessageLength(totalMsgLength * 8); - HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) = CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M; - - } - - // The cast is fine in this case. SHA2StartDMAOperation channel one serves as input and no one does - // hash operations in-place. - SHA2StartDMAOperation((uint8_t *)message, messageLength, resultDigest, digestLength); - - return SHA2_SUCCESS; -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h deleted file mode 100644 index 4910222ccac..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2.h +++ /dev/null @@ -1,802 +0,0 @@ -/****************************************************************************** -* Filename: sha2.h -* Revised: 2018-04-17 16:04:03 +0200 (Tue, 17 Apr 2018) -* Revision: 51893 -* -* Description: SHA-2 header file. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup sha2_api -//! @{ -// -//***************************************************************************** - -#ifndef __SHA2_H__ -#define __SHA2_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_crypto.h" -#include "../inc/hw_ccfg.h" -#include "debug.h" -#include "interrupt.h" -#include "cpu.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define SHA2StartDMAOperation NOROM_SHA2StartDMAOperation - #define SHA2WaitForIRQFlags NOROM_SHA2WaitForIRQFlags - #define SHA2ComputeInitialHash NOROM_SHA2ComputeInitialHash - #define SHA2ComputeIntermediateHash NOROM_SHA2ComputeIntermediateHash - #define SHA2ComputeFinalHash NOROM_SHA2ComputeFinalHash - #define SHA2ComputeHash NOROM_SHA2ComputeHash -#endif - -//***************************************************************************** -// -// Values that can be passed to SHA2IntEnable, SHA2IntDisable, and SHA2IntClear -// as the intFlags parameter, and returned from SHA2IntStatus. -// Only SHA2_DMA_IN_DONE and SHA2_RESULT_RDY are routed to the NVIC. Check each -// function to see if it supports other interrupt status flags. -// -//***************************************************************************** -#define SHA2_DMA_IN_DONE (CRYPTO_IRQEN_DMA_IN_DONE_M) -#define SHA2_RESULT_RDY (CRYPTO_IRQEN_RESULT_AVAIL_M) -#define SHA2_DMA_BUS_ERR (CRYPTO_IRQCLR_DMA_BUS_ERR_M) - - -//***************************************************************************** -// -// General constants -// -//***************************************************************************** - -// SHA-2 module return codes -#define SHA2_SUCCESS 0 -#define SHA2_INVALID_ALGORITHM 1 -#define SHA2_DMA_BUSY 3 -#define SHA2_DMA_ERROR 4 -#define SHA2_DIGEST_NOT_READY 5 -#define SHA2_OLD_DIGEST_NOT_READ 6 - -// SHA-2 output digest lengths in bytes. -#define SHA2_SHA224_DIGEST_LENGTH_BYTES (224 / 8) -#define SHA2_SHA256_DIGEST_LENGTH_BYTES (256 / 8) -#define SHA2_SHA384_DIGEST_LENGTH_BYTES (384 / 8) -#define SHA2_SHA512_DIGEST_LENGTH_BYTES (512 / 8) - -//Selectable SHA-2 modes. They determine the algorithm used and if initial -//values will be set to the default constants or not -#define SHA2_MODE_SELECT_SHA224 (CRYPTO_HASHMODE_SHA224_MODE_M) -#define SHA2_MODE_SELECT_SHA256 (CRYPTO_HASHMODE_SHA256_MODE_M) -#define SHA2_MODE_SELECT_SHA384 (CRYPTO_HASHMODE_SHA384_MODE_M) -#define SHA2_MODE_SELECT_SHA512 (CRYPTO_HASHMODE_SHA512_MODE_M) -#define SHA2_MODE_SELECT_NEW_HASH (CRYPTO_HASHMODE_NEW_HASH_M) - -// SHA-2 block lengths. When hashing block-wise, they define the size of each -// block provided to the new and intermediate hash functions. -#define SHA2_SHA224_BLOCK_SIZE_BYTES (512 / 8) -#define SHA2_SHA256_BLOCK_SIZE_BYTES (512 / 8) -#define SHA2_SHA384_BLOCK_SIZE_BYTES (1024 / 8) -#define SHA2_SHA512_BLOCK_SIZE_BYTES (1024 / 8) - -// DMA status codes -#define SHA2_DMA_CHANNEL0_ACTIVE (CRYPTO_DMASTAT_CH0_ACT_M) -#define SHA2_DMA_CHANNEL1_ACTIVE (CRYPTO_DMASTAT_CH1_ACT_M) -#define SHA2_DMA_PORT_ERROR (CRYPTO_DMASTAT_PORT_ERR_M) - -// Crypto module DMA operation types -#define SHA2_ALGSEL_SHA256 0x04 -#define SHA2_ALGSEL_SHA512 0x08 -#define SHA2_ALGSEL_TAG (CRYPTO_ALGSEL_TAG_M) - - - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Start a crypto DMA operation -//! -//! Enable the crypto DMA channels, configure the channel addresses, -//! and set the length of the data transfer. -//! Setting the length of the data transfer automatically starts the -//! transfer. It is also used by the hardware module as a signal to -//! begin the encryption, decryption, or MAC operation. -//! -//! \param [in] channel0Addr -//! A pointer to the address channel 0 shall use. -//! -//! \param [in] channel0Length -//! Length of the data in bytes to be read from or written to at -//! \c channel0Addr. Set to 0 to not set up this channel. -//! -//! \param [out] channel1Addr -//! A pointer to the address channel 1 shall use. -//! -//! \param [in] channel1Length -//! Length of the data in bytes to be read from or written to at -//! \c channel1Addr. Set to 0 to not set up this channel. -//! -//! \return None -// -//***************************************************************************** -extern void SHA2StartDMAOperation(uint8_t *channel0Addr, uint32_t channel0Length, uint8_t *channel1Addr, uint32_t channel1Length); - -//***************************************************************************** -// -//! \brief Poll the interrupt status register and clear when done. -//! -//! This function polls until one of the bits in the \c irqFlags is -//! asserted. Only \ref SHA2_DMA_IN_DONE and \ref SHA2_RESULT_RDY can actually -//! trigger the interrupt line. That means that one of those should -//! always be included in \c irqFlags and will always be returned together -//! with any error codes. -//! -//! \param [in] irqFlags -//! IRQ flags to poll and mask that the status register will be -//! masked with. Consists of any bitwise OR of the flags -//! below that includes at least one of -//! \ref SHA2_DMA_IN_DONE or \ref SHA2_RESULT_RDY : -//! - \ref SHA2_DMA_IN_DONE -//! - \ref SHA2_RESULT_RDY -//! - \ref SHA2_DMA_BUS_ERR -//! -//! \return Returns the IRQ status register masked with \c irqFlags. May be any -//! bitwise OR of the following masks: -//! - \ref SHA2_DMA_IN_DONE -//! - \ref SHA2_RESULT_RDY -//! - \ref SHA2_DMA_BUS_ERR -// -//***************************************************************************** -extern uint32_t SHA2WaitForIRQFlags(uint32_t irqFlags); - -//***************************************************************************** -// -//! \brief Start a new SHA-2 hash operation. -//! -//! This function begins a new piecewise hash operation. -//! -//! Call this function when starting a new hash operation and the -//! entire message is not yet available. -//! -//! Call SHA2ComputeIntermediateHash() or SHA2ComputeFinalHash() -//! after this call. -//! -//! If the device shall go into standby in between calls to this -//! function and either SHA2ComputeIntermediateHash() or -//! SHA2ComputeFinalHash(), the intermediate digest must be saved in -//! system RAM. -//! -//! \param [in] message -//! Byte array containing the start of the message to hash. -//! Must be exactly as long as the block length of the selected -//! algorithm. -//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES -//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES -//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES -//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES -//! -//! \param [out] intermediateDigest -//! Pointer to intermediate digest. -//! - NULL The intermediate digest will be stored in the internal -//! registers of the SHA module. -//! - Not NULL Specifies the location the intermediate digest will -//! be written to. -//! -//! Must be of a length equal to the digest length of the selected -//! hash algorithm. -//! Must be 32-bit aligned. \c intermediateDigest is copied into the -//! registers through the AHB slave interface in -//! SHA2ComputeIntermediateHash() and SHA2ComputeFinalHash(). -//! This can only be done word-by-word. -//! -//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of: -//! - \ref SHA2_MODE_SELECT_SHA224 -//! - \ref SHA2_MODE_SELECT_SHA256 -//! - \ref SHA2_MODE_SELECT_SHA384 -//! - \ref SHA2_MODE_SELECT_SHA512 -//! -//! \param [in] initialMessageLength The length in bytes of the first -//! section of the message to process. Must be a multiple of the -//! block size. -//! -//! \return Returns a SHA-2 return code. -//! - \ref SHA2_SUCCESS -//! - \ref SHA2_INVALID_ALGORITHM -//! -//! \sa SHA2ComputeIntermediateHash() -//! \sa SHA2ComputeFinalHash() -// -//***************************************************************************** -extern uint32_t SHA2ComputeInitialHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t initialMessageLength); - -//***************************************************************************** -// -//! \brief Resume a SHA-2 hash operation but do not finalize it. -//! -//! This function resumes a previous hash operation. -//! -//! Call this function when continuing a hash operation and the -//! message is not yet complete. -//! -//! Call this function again or SHA2ComputeFinalHash() -//! after this call. -//! -//! If the device shall go into standby in between calls to this -//! function and SHA2ComputeFinalHash(), the intermediate -//! digest must be saved in system RAM. -//! -//! \param [in] message -//! Byte array containing the start of the current block of the -//! message to hash. -//! Must be exactly as long as the block length of the selected -//! algorithm. -//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES -//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES -//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES -//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES -//! -//! \param [in, out] intermediateDigest -//! Pointer to intermediate digest. -//! - NULL The intermediate digest will be sourced from the internal -//! registers of the SHA module and stored there after the -//! operation completes. -//! - Not NULL Specifies the location the intermediate digest will -//! be read from and written to. -//! -//! Must be of a length equal to the digest length of the selected -//! hash algorithm. -//! Must be 32-bit aligned. \c intermediateDigest is copied from and -//! to the registers through the AHB slave interface. -//! This can only be done word-by-word. -//! -//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of: -//! - \ref SHA2_MODE_SELECT_SHA224 -//! - \ref SHA2_MODE_SELECT_SHA256 -//! - \ref SHA2_MODE_SELECT_SHA384 -//! - \ref SHA2_MODE_SELECT_SHA512 -//! -//! \param [in] intermediateMessageLength The length in bytes of this -//! section of the message to process. Must be a multiple of the -//! block size. -//! -//! \return Returns a SHA-2 return code. -//! - \ref SHA2_SUCCESS -//! - \ref SHA2_INVALID_ALGORITHM -//! -//! \sa SHA2ComputeInitialHash() -//! \sa SHA2ComputeFinalHash() -// -//***************************************************************************** -extern uint32_t SHA2ComputeIntermediateHash(const uint8_t *message, uint32_t *intermediateDigest, uint32_t hashAlgorithm, uint32_t intermediateMessageLength); - -//***************************************************************************** -// -//! \brief Resume a SHA-2 hash operation and finalize it. -//! -//! This function resumes a previous hash session. -//! -//! Call this function when continuing a hash operation and the -//! message is complete. -//! -//! \param [in] message -//! Byte array containing the final block of the message to hash. -//! Any length <= the block size is acceptable. -//! The DMA finalize the message as necessary. -//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES -//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES -//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES -//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES -//! -//! \param [out] resultDigest -//! Byte array that the final digest will be written to. Must be of -//! a length equal to the digest length of the selected hash algorithm. -//! -//! \param [in] intermediateDigest -//! Pointer to intermediate digest. -//! - NULL The intermediate digest will be sourced from the internal -//! registers of the SHA module. -//! - Not NULL Specifies the location the intermediate digest will -//! be read from. -//! Must be of a length equal to the digest length of the selected -//! hash algorithm. -//! Must be 32-bit aligned. \c intermediateDigest is copied from and -//! to the registers through the AHB slave interface. -//! This can only be done word-by-word. -//! -//! \param [in] totalMsgLength -//! The length in bytes of the entire \c message including the sections -//! passed to previous calls to SHA2ComputeInitialHash() and -//! SHA2ComputeIntermediateHash(). -//! -//! \param [in] messageLength The length in bytes of the last -//! section of the message to process. Does not need to be -//! a multiple of the block size. -//! -//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of: -//! - \ref SHA2_MODE_SELECT_SHA224 -//! - \ref SHA2_MODE_SELECT_SHA256 -//! - \ref SHA2_MODE_SELECT_SHA384 -//! - \ref SHA2_MODE_SELECT_SHA512 -//! -//! \return Returns a SHA-2 return code. -//! - \ref SHA2_SUCCESS -//! - \ref SHA2_INVALID_ALGORITHM -//! -//! \sa SHA2ComputeInitialHash() -//! \sa SHA2ComputeIntermediateHash() -// -//***************************************************************************** -extern uint32_t SHA2ComputeFinalHash(const uint8_t *message, uint8_t *resultDigest, uint32_t *intermediateDigest, uint32_t totalMsgLength, uint32_t messageLength, uint32_t hashAlgorithm); - -//***************************************************************************** -// -//! \brief Start a SHA-2 hash operation and return the finalized digest. -//! -//! This function starts a hash operation and returns the finalized -//! digest. -//! -//! Use this function if the entire message is available when starting -//! the hash. -//! -//! \param [in] message -//! Byte array containing the message that will be hashed. -//! Any length <= the block size is acceptable. -//! The DMA will finalize the message as necessary. -//! - \ref SHA2_SHA224_BLOCK_SIZE_BYTES -//! - \ref SHA2_SHA256_BLOCK_SIZE_BYTES -//! - \ref SHA2_SHA384_BLOCK_SIZE_BYTES -//! - \ref SHA2_SHA512_BLOCK_SIZE_BYTES -//! -//! \param [out] resultDigest -//! Byte array that the final digest will be written to. Must be of a -//! length equal to the digest length of the selected hash algorithm. -//! -//! \param [in] totalMsgLength -//! The length in bytes of the entire \c message. -//! -//! \param [in] hashAlgorithm Selects the hash algorithm to use. One of: -//! - \ref SHA2_MODE_SELECT_SHA224 -//! - \ref SHA2_MODE_SELECT_SHA256 -//! - \ref SHA2_MODE_SELECT_SHA384 -//! - \ref SHA2_MODE_SELECT_SHA512 -//! -//! \return Returns a SHA-2 return code. -//! - \ref SHA2_SUCCESS -//! - \ref SHA2_INVALID_ALGORITHM -//! -// -//***************************************************************************** -extern uint32_t SHA2ComputeHash(const uint8_t *message, uint8_t *resultDigest, uint32_t totalMsgLength, uint32_t hashAlgorithm); - -//***************************************************************************** -// -//! \brief Configure the crypto DMA for a particular operation. -//! -//! \param algorithm -//! Configures the crypto DMA for a particular operation. -//! It also powers on the respective part of the system. -//! \ref SHA2_ALGSEL_TAG may be combined with another flag. All other -//! flags are mutually exclusive. -//! - 0 : Reset the module and turn off all sub-modules. -//! - \ref SHA2_ALGSEL_SHA256 Configure for a SHA224 or SHA256 operation. -//! - \ref SHA2_ALGSEL_SHA512 Configure for a SHA384 or SHA512 operation. -//! - \ref SHA2_ALGSEL_TAG Read out hash via DMA rather than the slave interface -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void SHA2SelectAlgorithm(uint32_t algorithm) -{ - ASSERT((algorithm == SHA2_ALGSEL_SHA256) || - (algorithm == SHA2_ALGSEL_SHA512) || - (algorithm == SHA2_ALGSEL_SHA256 | SHA2_ALGSEL_TAG) || - (algorithm == SHA2_ALGSEL_SHA512 | SHA2_ALGSEL_TAG)); - - HWREG(CRYPTO_BASE + CRYPTO_O_ALGSEL) = algorithm; -} - - - -//***************************************************************************** -// -//! \brief Specify the total length of the message. -//! -//! Despite specifying it here, the crypto DMA must still be -//! set up with the correct data length. -//! -//! Call this function only when setting up the final hash operation to -//! enable finalization. -//! -//! \param length Total message length in bits. -//! -//! \return None -//! -//! \sa SHA2StartDMAOperation() -// -//***************************************************************************** -__STATIC_INLINE void SHA2SetMessageLength(uint32_t length) -{ - HWREG(CRYPTO_BASE + CRYPTO_O_HASHINLENL) = length; - // CRYPTO_O_HASHINLENH is automatically set to 0. No need for the extra write. -} - -//***************************************************************************** -// -//! \brief Load an intermediate digest. -//! -//! \param [in] digestLength -//! Length of the digest in bytes. Must be one of: -//! - \ref SHA2_SHA224_DIGEST_LENGTH_BYTES -//! - \ref SHA2_SHA256_DIGEST_LENGTH_BYTES -//! - \ref SHA2_SHA384_DIGEST_LENGTH_BYTES -//! - \ref SHA2_SHA512_DIGEST_LENGTH_BYTES -//! -//! \param [in] digest -//! Pointer to an intermediate digest. Must be 32-bit aligned. -//! -// -//***************************************************************************** -__STATIC_INLINE void SHA2SetDigest(uint32_t *digest, uint8_t digestLength) -{ - // Check the arguments. - ASSERT(!(digest == NULL) && !((uint32_t)digest & 0x03)); - ASSERT((digestLength == SHA2_SHA224_DIGEST_LENGTH_BYTES) || - (digestLength == SHA2_SHA256_DIGEST_LENGTH_BYTES) || - (digestLength == SHA2_SHA384_DIGEST_LENGTH_BYTES) || - (digestLength == SHA2_SHA512_DIGEST_LENGTH_BYTES)); - - // Write digest - uint32_t i = 0; - for (i = 0; i < (digestLength / sizeof(uint32_t)); i++) { - HWREG(CRYPTO_BASE + CRYPTO_O_HASHDIGESTA + (i * sizeof(uint32_t))) = digest[i]; - } - -} - -//***************************************************************************** -// -//! \brief Read the intermediate or final digest. -//! -//! \param [in] digestLength Length of the digest in bytes. Must be one of: -//! - ref SHA2_SHA224_DIGEST_LENGTH_BYTES -//! - ref SHA2_SHA256_DIGEST_LENGTH_BYTES -//! - ref SHA2_SHA384_DIGEST_LENGTH_BYTES -//! - ref SHA2_SHA512_DIGEST_LENGTH_BYTES -//! -//! \param [out] digest -//! Pointer to an intermediate digest. Must be 32-bit aligned. -//! -//! \return Returns a status code. -//! - \ref SHA2_OLD_DIGEST_NOT_READ -//! - \ref SHA2_SUCCESS -// -//***************************************************************************** -__STATIC_INLINE uint32_t SHA2GetDigest(uint32_t *digest, uint8_t digestLength) -{ - // Check the arguments. - ASSERT(!(digest == NULL) && !((uint32_t)digest & 0x03)); - ASSERT((digestLength == SHA2_SHA224_DIGEST_LENGTH_BYTES) || - (digestLength == SHA2_SHA256_DIGEST_LENGTH_BYTES) || - (digestLength == SHA2_SHA384_DIGEST_LENGTH_BYTES) || - (digestLength == SHA2_SHA512_DIGEST_LENGTH_BYTES)); - - if (HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) & CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_M) { - return SHA2_OLD_DIGEST_NOT_READ; - } - else { - // Read digest - uint32_t i = 0; - for (i = 0; i < (digestLength / sizeof(uint32_t)); i++) { - digest[i] = HWREG(CRYPTO_BASE + CRYPTO_O_HASHDIGESTA + (i * sizeof(uint32_t))); - } - return SHA2_SUCCESS; - } -} - -//***************************************************************************** -// -//! \brief Confirm digest was read. -// -//***************************************************************************** -__STATIC_INLINE void SHA2ClearDigestAvailableFlag(void) -{ - HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL) = HWREG(CRYPTO_BASE + CRYPTO_O_HASHIOBUFCTRL); -} - -//***************************************************************************** -// -//! \brief Enable individual crypto interrupt sources. -//! -//! This function enables the indicated crypto interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt. -//! Disabled sources have no effect on the processor. -//! -//! \param intFlags is the bitwise OR of the interrupt sources to be enabled. -//! - \ref SHA2_DMA_IN_DONE -//! - \ref SHA2_RESULT_RDY -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void SHA2IntEnable(uint32_t intFlags) -{ - // Check the arguments. - ASSERT((intFlags & SHA2_DMA_IN_DONE) || - (intFlags & SHA2_RESULT_RDY)); - - // Using level interrupt. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQTYPE) = CRYPTO_IRQTYPE_LEVEL_M; - - // Enable the specified interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) |= intFlags; -} - -//***************************************************************************** -// -//! \brief Disable individual crypto interrupt sources. -//! -//! This function disables the indicated crypto interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt. -//! Disabled sources have no effect on the processor. -//! -//! \param intFlags is the bitwise OR of the interrupt sources to be enabled. -//! - \ref SHA2_DMA_IN_DONE -//! - \ref SHA2_RESULT_RDY -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void SHA2IntDisable(uint32_t intFlags) -{ - // Check the arguments. - ASSERT((intFlags & SHA2_DMA_IN_DONE) || - (intFlags & SHA2_RESULT_RDY)); - - // Disable the specified interrupts. - HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN) &= ~intFlags; -} - -//***************************************************************************** -// -//! \brief Get the current masked interrupt status. -//! -//! This function returns the masked interrupt status of the crypto module. -//! -//! \return Returns the status of the masked lines when enabled: -//! - \ref SHA2_DMA_IN_DONE -//! - \ref SHA2_RESULT_RDY -// -//***************************************************************************** -__STATIC_INLINE uint32_t SHA2IntStatusMasked(void) -{ - uint32_t mask; - - // Return the masked interrupt status - mask = HWREG(CRYPTO_BASE + CRYPTO_O_IRQEN); - return(mask & HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); -} - -//***************************************************************************** -// -//! \brief Get the current raw interrupt status. -//! -//! This function returns the raw interrupt status of the crypto module. -//! It returns both the status of the lines routed to the NVIC as well as the -//! error flags. -//! -//! \return Returns the raw interrupt status: -//! - \ref SHA2_DMA_IN_DONE -//! - \ref SHA2_RESULT_RDY -//! - \ref SHA2_DMA_BUS_ERR -// -//***************************************************************************** -__STATIC_INLINE uint32_t SHA2IntStatusRaw(void) -{ - // Return either the raw interrupt status - return(HWREG(CRYPTO_BASE + CRYPTO_O_IRQSTAT)); -} - -//***************************************************************************** -// -//! \brief Clear crypto interrupt sources. -//! -//! The specified crypto interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in the module until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! -//! \param intFlags is a bit mask of the interrupt sources to be cleared. -//! - \ref SHA2_DMA_IN_DONE -//! - \ref SHA2_RESULT_RDY -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void SHA2IntClear(uint32_t intFlags) -{ - // Check the arguments. - ASSERT((intFlags & SHA2_DMA_IN_DONE) || - (intFlags & SHA2_RESULT_RDY)); - - // Clear the requested interrupt sources, - HWREG(CRYPTO_BASE + CRYPTO_O_IRQCLR) = intFlags; -} - -//***************************************************************************** -// -//! \brief Register an interrupt handler for a crypto interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific crypto interrupts must be enabled via \ref SHA2IntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source. -//! -//! \param handlerFxn is a pointer to the function to be called when the -//! crypto interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void SHA2IntRegister(void (*handlerFxn)(void)) -{ - // Register the interrupt handler. - IntRegister(INT_CRYPTO_RESULT_AVAIL_IRQ, handlerFxn); - - // Enable the crypto interrupt. - IntEnable(INT_CRYPTO_RESULT_AVAIL_IRQ); -} - -//***************************************************************************** -// -//! \brief Unregister an interrupt handler for a crypto interrupt in the dynamic interrupt table. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler called when a crypto interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void SHA2IntUnregister(void) -{ - // Disable the interrupt. - IntDisable(INT_CRYPTO_RESULT_AVAIL_IRQ); - - // Unregister the interrupt handler. - IntUnregister(INT_CRYPTO_RESULT_AVAIL_IRQ); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_SHA2StartDMAOperation - #undef SHA2StartDMAOperation - #define SHA2StartDMAOperation ROM_SHA2StartDMAOperation - #endif - #ifdef ROM_SHA2WaitForIRQFlags - #undef SHA2WaitForIRQFlags - #define SHA2WaitForIRQFlags ROM_SHA2WaitForIRQFlags - #endif - #ifdef ROM_SHA2ComputeInitialHash - #undef SHA2ComputeInitialHash - #define SHA2ComputeInitialHash ROM_SHA2ComputeInitialHash - #endif - #ifdef ROM_SHA2ComputeIntermediateHash - #undef SHA2ComputeIntermediateHash - #define SHA2ComputeIntermediateHash ROM_SHA2ComputeIntermediateHash - #endif - #ifdef ROM_SHA2ComputeFinalHash - #undef SHA2ComputeFinalHash - #define SHA2ComputeFinalHash ROM_SHA2ComputeFinalHash - #endif - #ifdef ROM_SHA2ComputeHash - #undef SHA2ComputeHash - #define SHA2ComputeHash ROM_SHA2ComputeHash - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SHA2_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h deleted file mode 100644 index 2ca7c754dac..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sha2_doc.h +++ /dev/null @@ -1,62 +0,0 @@ -/****************************************************************************** -* Filename: sha2_doc.h -* Revised: 2017-11-01 10:33:37 +0100 (Wed, 01 Nov 2017) -* Revision: 50125 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup sha2_api -//! @{ -//! \section sec_sha2 Introduction -//! -//! The SHA-2 (Secure Hash Algorithm) API provides access to the SHA-2 -//! functionality of the crypto core. The AES accelerator and keystore are -//! also contained within the crypto core. Hence, only one of SHA-2 and AES -//! may be used at the same time. -//! This module offers hardware acceleration for the SHA-2 family of hash -//! algorithms. The following output digest sizes are supported: -//! - 224 bits -//! - 256 bits -//! - 384 bits -//! - 512 bits -//! -//! Messages are hashed in one go or in multiple steps. Stepwise hashing -//! consists of an initial hash, multiple intermediate hashes, and a -//! finalization hash. -//! -//! The crypto core does not have retention and all configuration settings -//! are lost when going into standby or shutdown. If you wish to continue -//! a hash operation after going into standby or shutdown, you must load -//! the intermediate hash into system RAM before entering standby or shutdown -//! and load the intermediate hash back into the crypto module after resuming -//! operation. -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph.c deleted file mode 100644 index e6f47e6bbff..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph.c +++ /dev/null @@ -1,101 +0,0 @@ -/****************************************************************************** -* Filename: smph.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for the MCU Semaphore. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "smph.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef SMPHAcquire - #define SMPHAcquire NOROM_SMPHAcquire -#endif - -//***************************************************************************** -// -// Acquire a semaphore -// -//***************************************************************************** -void -SMPHAcquire(uint32_t ui32Semaphore) -{ - // Check the arguments. - ASSERT((ui32Semaphore == SMPH_0) || - (ui32Semaphore == SMPH_1) || - (ui32Semaphore == SMPH_2) || - (ui32Semaphore == SMPH_3) || - (ui32Semaphore == SMPH_4) || - (ui32Semaphore == SMPH_5) || - (ui32Semaphore == SMPH_6) || - (ui32Semaphore == SMPH_7) || - (ui32Semaphore == SMPH_8) || - (ui32Semaphore == SMPH_9) || - (ui32Semaphore == SMPH_10) || - (ui32Semaphore == SMPH_11) || - (ui32Semaphore == SMPH_12) || - (ui32Semaphore == SMPH_13) || - (ui32Semaphore == SMPH_14) || - (ui32Semaphore == SMPH_15) || - (ui32Semaphore == SMPH_16) || - (ui32Semaphore == SMPH_17) || - (ui32Semaphore == SMPH_18) || - (ui32Semaphore == SMPH_19) || - (ui32Semaphore == SMPH_20) || - (ui32Semaphore == SMPH_21) || - (ui32Semaphore == SMPH_22) || - (ui32Semaphore == SMPH_23) || - (ui32Semaphore == SMPH_24) || - (ui32Semaphore == SMPH_25) || - (ui32Semaphore == SMPH_26) || - (ui32Semaphore == SMPH_27) || - (ui32Semaphore == SMPH_28) || - (ui32Semaphore == SMPH_29) || - (ui32Semaphore == SMPH_30) || - (ui32Semaphore == SMPH_31)); - - // Wait for semaphore to be release such that it can be claimed - // Semaphore register reads 1 when lock was acquired otherwise 0 - // (i.e. SMPH_CLAIMED). - while(HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) == - SMPH_CLAIMED) - { - } -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h deleted file mode 100644 index 0ed7387fa5b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph.h +++ /dev/null @@ -1,312 +0,0 @@ -/****************************************************************************** -* Filename: smph.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the MCU Semaphore. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup mcusemaphore_api -//! @{ -// -//***************************************************************************** - -#ifndef __SMPH_H__ -#define __SMPH_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_smph.h" -#include "../inc/hw_memmap.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define SMPHAcquire NOROM_SMPHAcquire -#endif - -//***************************************************************************** -// -// General constants and defines -// -//***************************************************************************** -#define SMPH_FREE 0x00000001 // MCU Semaphore has not been claimed -#define SMPH_CLAIMED 0x00000000 // MCU Semaphore has been claimed - -//***************************************************************************** -// -// Values that can be passed to SMPHAcquire, SMPHTryAcquire and SMPHRelease -// as the ui32Semaphore parameter. -// -//***************************************************************************** -#define SMPH_0 0 // MCU Semaphore 0 -#define SMPH_1 1 // MCU Semaphore 1 -#define SMPH_2 2 // MCU Semaphore 2 -#define SMPH_3 3 // MCU Semaphore 3 -#define SMPH_4 4 // MCU Semaphore 4 -#define SMPH_5 5 // MCU Semaphore 5 -#define SMPH_6 6 // MCU Semaphore 6 -#define SMPH_7 7 // MCU Semaphore 7 -#define SMPH_8 8 // MCU Semaphore 8 -#define SMPH_9 9 // MCU Semaphore 9 -#define SMPH_10 10 // MCU Semaphore 10 -#define SMPH_11 11 // MCU Semaphore 11 -#define SMPH_12 12 // MCU Semaphore 12 -#define SMPH_13 13 // MCU Semaphore 13 -#define SMPH_14 14 // MCU Semaphore 14 -#define SMPH_15 15 // MCU Semaphore 15 -#define SMPH_16 16 // MCU Semaphore 16 -#define SMPH_17 17 // MCU Semaphore 17 -#define SMPH_18 18 // MCU Semaphore 18 -#define SMPH_19 19 // MCU Semaphore 19 -#define SMPH_20 20 // MCU Semaphore 20 -#define SMPH_21 21 // MCU Semaphore 21 -#define SMPH_22 22 // MCU Semaphore 22 -#define SMPH_23 23 // MCU Semaphore 23 -#define SMPH_24 24 // MCU Semaphore 24 -#define SMPH_25 25 // MCU Semaphore 25 -#define SMPH_26 26 // MCU Semaphore 26 -#define SMPH_27 27 // MCU Semaphore 27 -#define SMPH_28 28 // MCU Semaphore 28 -#define SMPH_29 29 // MCU Semaphore 29 -#define SMPH_30 30 // MCU Semaphore 30 -#define SMPH_31 31 // MCU Semaphore 31 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Acquire a semaphore. -//! -//! This function acquires the given semaphore, blocking the call until -//! the semaphore is available. -//! -//! \param ui32Semaphore is the semaphore number. -//! - \ref SMPH_0 -//! - \ref SMPH_1 -//! - ... -//! - \ref SMPH_31 -//! -//! \return None -// -//***************************************************************************** -extern void SMPHAcquire(uint32_t ui32Semaphore); - -//***************************************************************************** -// -//! \brief Try to Acquire a semaphore. -//! -//! This function tries to acquire the given semaphore, if the semaphore -//! could not be claimed the function returns false. -//! -//! \param ui32Semaphore is the semaphore number. -//! - \ref SMPH_0 -//! - \ref SMPH_1 -//! - ... -//! - \ref SMPH_31 -//! -//! \return Returns if a semaphore was acquired -//! - \c true : Semaphore acquired. -//! - \c false : Semaphore \b not acquired. -// -//***************************************************************************** -__STATIC_INLINE bool -SMPHTryAcquire(uint32_t ui32Semaphore) -{ - uint32_t ui32SemaReg; - - // Check the arguments. - ASSERT((ui32Semaphore == SMPH_0) || - (ui32Semaphore == SMPH_1) || - (ui32Semaphore == SMPH_2) || - (ui32Semaphore == SMPH_3) || - (ui32Semaphore == SMPH_4) || - (ui32Semaphore == SMPH_5) || - (ui32Semaphore == SMPH_6) || - (ui32Semaphore == SMPH_7) || - (ui32Semaphore == SMPH_8) || - (ui32Semaphore == SMPH_9) || - (ui32Semaphore == SMPH_10) || - (ui32Semaphore == SMPH_11) || - (ui32Semaphore == SMPH_12) || - (ui32Semaphore == SMPH_13) || - (ui32Semaphore == SMPH_14) || - (ui32Semaphore == SMPH_15) || - (ui32Semaphore == SMPH_16) || - (ui32Semaphore == SMPH_17) || - (ui32Semaphore == SMPH_18) || - (ui32Semaphore == SMPH_19) || - (ui32Semaphore == SMPH_20) || - (ui32Semaphore == SMPH_21) || - (ui32Semaphore == SMPH_22) || - (ui32Semaphore == SMPH_23) || - (ui32Semaphore == SMPH_24) || - (ui32Semaphore == SMPH_25) || - (ui32Semaphore == SMPH_26) || - (ui32Semaphore == SMPH_27) || - (ui32Semaphore == SMPH_28) || - (ui32Semaphore == SMPH_29) || - (ui32Semaphore == SMPH_30) || - (ui32Semaphore == SMPH_31)); - - // Semaphore register reads 1 if lock was acquired - // (i.e. SMPH_FREE). - ui32SemaReg = HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore); - - return (ui32SemaReg == SMPH_FREE); -} - -//***************************************************************************** -// -//! \brief Release a semaphore. -//! -//! This function releases the given semaphore. -//! -//! \note It is up to the application to provide the convention for clearing -//! semaphore. -//! -//! \param ui32Semaphore is the semaphore number. -//! - \ref SMPH_0 -//! - \ref SMPH_1 -//! - ... -//! - \ref SMPH_31 -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SMPHRelease(uint32_t ui32Semaphore) -{ - // Check the arguments. - ASSERT((ui32Semaphore == SMPH_0) || - (ui32Semaphore == SMPH_1) || - (ui32Semaphore == SMPH_2) || - (ui32Semaphore == SMPH_3) || - (ui32Semaphore == SMPH_4) || - (ui32Semaphore == SMPH_5) || - (ui32Semaphore == SMPH_6) || - (ui32Semaphore == SMPH_7) || - (ui32Semaphore == SMPH_8) || - (ui32Semaphore == SMPH_9) || - (ui32Semaphore == SMPH_10) || - (ui32Semaphore == SMPH_11) || - (ui32Semaphore == SMPH_12) || - (ui32Semaphore == SMPH_13) || - (ui32Semaphore == SMPH_14) || - (ui32Semaphore == SMPH_15) || - (ui32Semaphore == SMPH_16) || - (ui32Semaphore == SMPH_17) || - (ui32Semaphore == SMPH_18) || - (ui32Semaphore == SMPH_19) || - (ui32Semaphore == SMPH_20) || - (ui32Semaphore == SMPH_21) || - (ui32Semaphore == SMPH_22) || - (ui32Semaphore == SMPH_23) || - (ui32Semaphore == SMPH_24) || - (ui32Semaphore == SMPH_25) || - (ui32Semaphore == SMPH_26) || - (ui32Semaphore == SMPH_27) || - (ui32Semaphore == SMPH_28) || - (ui32Semaphore == SMPH_29) || - (ui32Semaphore == SMPH_30) || - (ui32Semaphore == SMPH_31)); - - // No check before release, it is up to the application to provide the - // conventions for who and when a semaphore can be released. - HWREG(SMPH_BASE + SMPH_O_SMPH0 + 4 * ui32Semaphore) = SMPH_FREE; -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_SMPHAcquire - #undef SMPHAcquire - #define SMPHAcquire ROM_SMPHAcquire - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SMPH_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h deleted file mode 100644 index 3c6f4b3e483..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/smph_doc.h +++ /dev/null @@ -1,57 +0,0 @@ -/****************************************************************************** -* Filename: smph_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup mcusemaphore_api -//! @{ -//! \section sec_mcusemaphore Introduction -//! -//! The MCU Semaphore offers 32 semaphores that each can be claimed and released in an atomic operation. -//! One and only one semaphore can be handled during a transaction. -//! -//! Claiming a semaphore causes subsequent claims/reads to return '0' (i.e. "not available"). -//! How the semaphores are used and respected is decided by software. -//! -//! \section sec_mcusemaphore_api API -//! -//! The API functions can be grouped like this: -//! -//! Semaphore acquire: -//! - \ref SMPHAcquire() -//! - \ref SMPHTryAcquire() -//! -//! Semaphore release: -//! - \ref SMPHRelease() -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.c deleted file mode 100644 index eb66b6b6618..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.c +++ /dev/null @@ -1,253 +0,0 @@ -/****************************************************************************** -* Filename: ssi.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for Synchronous Serial Interface -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "ssi.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef SSIConfigSetExpClk - #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk - #undef SSIDataPut - #define SSIDataPut NOROM_SSIDataPut - #undef SSIDataPutNonBlocking - #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking - #undef SSIDataGet - #define SSIDataGet NOROM_SSIDataGet - #undef SSIDataGetNonBlocking - #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking - #undef SSIIntRegister - #define SSIIntRegister NOROM_SSIIntRegister - #undef SSIIntUnregister - #define SSIIntUnregister NOROM_SSIIntUnregister -#endif - -//***************************************************************************** -// -// Configures the synchronous serial port -// -//***************************************************************************** -void -SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, - uint32_t ui32Protocol, uint32_t ui32Mode, - uint32_t ui32BitRate, uint32_t ui32DataWidth) -{ - uint32_t ui32MaxBitRate; - uint32_t ui32RegVal; - uint32_t ui32PreDiv; - uint32_t ui32SCR; - uint32_t ui32SPH_SPO; - - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - ASSERT((ui32Protocol == SSI_FRF_MOTO_MODE_0) || - (ui32Protocol == SSI_FRF_MOTO_MODE_1) || - (ui32Protocol == SSI_FRF_MOTO_MODE_2) || - (ui32Protocol == SSI_FRF_MOTO_MODE_3) || - (ui32Protocol == SSI_FRF_TI) || - (ui32Protocol == SSI_FRF_NMW)); - ASSERT((ui32Mode == SSI_MODE_MASTER) || - (ui32Mode == SSI_MODE_SLAVE) || - (ui32Mode == SSI_MODE_SLAVE_OD)); - ASSERT(((ui32Mode == SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 2))) || - ((ui32Mode != SSI_MODE_MASTER) && (ui32BitRate <= (ui32SSIClk / 12)))); - ASSERT((ui32SSIClk / ui32BitRate) <= (254 * 256)); - ASSERT((ui32DataWidth >= 4) && (ui32DataWidth <= 16)); - - // Set the mode. - ui32RegVal = (ui32Mode == SSI_MODE_SLAVE_OD) ? SSI_CR1_SOD : 0; - ui32RegVal |= (ui32Mode == SSI_MODE_MASTER) ? 0 : SSI_CR1_MS; - HWREG(ui32Base + SSI_O_CR1) = ui32RegVal; - - // Set the clock predivider. - ui32MaxBitRate = ui32SSIClk / ui32BitRate; - ui32PreDiv = 0; - do - { - ui32PreDiv += 2; - ui32SCR = (ui32MaxBitRate / ui32PreDiv) - 1; - } - while(ui32SCR > 255); - HWREG(ui32Base + SSI_O_CPSR) = ui32PreDiv; - - // Set protocol and clock rate. - ui32SPH_SPO = (ui32Protocol & 3) << 6; - ui32Protocol &= SSI_CR0_FRF_M; - ui32RegVal = (ui32SCR << 8) | ui32SPH_SPO | ui32Protocol | (ui32DataWidth - 1); - HWREG(ui32Base + SSI_O_CR0) = ui32RegVal; -} - -//***************************************************************************** -// -// Puts a data element into the SSI transmit FIFO -// -//***************************************************************************** -int32_t -SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & - SSI_CR0_DSS_M))) == 0); - - // Check for space to write. - if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF) - { - HWREG(ui32Base + SSI_O_DR) = ui32Data; - return(1); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -// Puts a data element into the SSI transmit FIFO -// -//***************************************************************************** -void -SSIDataPut(uint32_t ui32Base, uint32_t ui32Data) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - ASSERT((ui32Data & (0xfffffffe << (HWREG(ui32Base + SSI_O_CR0) & - SSI_CR0_DSS_M))) == 0); - - // Wait until there is space. - while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_TNF)) - { - } - - // Write the data to the SSI. - HWREG(ui32Base + SSI_O_DR) = ui32Data; -} - -//***************************************************************************** -// -// Gets a data element from the SSI receive FIFO -// -//***************************************************************************** -void -SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Wait until there is data to be read. - while(!(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE)) - { - } - - // Read data from SSI. - *pui32Data = HWREG(ui32Base + SSI_O_DR); -} - -//***************************************************************************** -// -// Gets a data element from the SSI receive FIFO -// -//***************************************************************************** -int32_t -SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Check for data to read. - if(HWREG(ui32Base + SSI_O_SR) & SSI_SR_RNE) - { - *pui32Data = HWREG(ui32Base + SSI_O_DR); - return(1); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -// Registers an interrupt handler for the synchronous serial port -// -//***************************************************************************** -void -SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Determine the interrupt number based on the SSI port. - ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB; - - // Register the interrupt handler. - IntRegister(ui32Int, pfnHandler); - - // Enable the synchronous serial port interrupt. - IntEnable(ui32Int); -} - -//***************************************************************************** -// -// Unregisters an interrupt handler for the synchronous serial port -// -//***************************************************************************** -void -SSIIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Determine the interrupt number based on the SSI port. - ui32Int = (ui32Base == SSI0_BASE) ? INT_SSI0_COMB : INT_SSI1_COMB; - - // Disable the interrupt. - IntDisable(ui32Int); - - // Unregister the interrupt handler. - IntUnregister(ui32Int); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h deleted file mode 100644 index 21eacf8a600..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ssi.h +++ /dev/null @@ -1,700 +0,0 @@ -/****************************************************************************** -* Filename: ssi.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and macros for the SSI. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup ssi_api -//! @{ -// -//***************************************************************************** - -#ifndef __SSI_H__ -#define __SSI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_ints.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_types.h" -#include "../inc/hw_ssi.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define SSIConfigSetExpClk NOROM_SSIConfigSetExpClk - #define SSIDataPut NOROM_SSIDataPut - #define SSIDataPutNonBlocking NOROM_SSIDataPutNonBlocking - #define SSIDataGet NOROM_SSIDataGet - #define SSIDataGetNonBlocking NOROM_SSIDataGetNonBlocking - #define SSIIntRegister NOROM_SSIIntRegister - #define SSIIntUnregister NOROM_SSIIntUnregister -#endif - -//***************************************************************************** -// -// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear -// as the ui32IntFlags parameter, and returned by SSIIntStatus. -// -//***************************************************************************** -#define SSI_TXFF 0x00000008 // TX FIFO half full or less -#define SSI_RXFF 0x00000004 // RX FIFO half full or more -#define SSI_RXTO 0x00000002 // RX timeout -#define SSI_RXOR 0x00000001 // RX overrun - -//***************************************************************************** -// -// Values that are returned from SSIStatus -// -//***************************************************************************** -#define SSI_RX_FULL 0x00000008 // Receive FIFO full -#define SSI_RX_NOT_EMPTY 0x00000004 // Receive FIFO not empty -#define SSI_TX_NOT_FULL 0x00000002 // Transmit FIFO not full -#define SSI_TX_EMPTY 0x00000001 // Transmit FIFO empty -#define SSI_STATUS_MASK 0x0000000F - -//***************************************************************************** -// -// Values that can be passed to SSIConfigSetExpClk. -// -//***************************************************************************** -#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 -#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 -#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 -#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 -#define SSI_FRF_TI 0x00000010 // TI frame format -#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format - -#define SSI_MODE_MASTER 0x00000000 // SSI master -#define SSI_MODE_SLAVE 0x00000001 // SSI slave -#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled - -//***************************************************************************** -// -// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). -// -//***************************************************************************** -#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit -#define SSI_DMA_RX 0x00000001 // Enable DMA for receive - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! -//! \brief Checks an SSI base address. -//! -//! This function determines if an SSI module base address is valid. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -SSIBaseValid(uint32_t ui32Base) -{ - return(ui32Base == SSI0_BASE || ui32Base == SSI1_BASE); -} -#endif - -//***************************************************************************** -// -//! \brief Configures the synchronous serial port. -//! -//! This function configures the synchronous serial port. It sets -//! the SSI protocol, mode of operation, bit rate, and data width. -//! -//! The \c ui32Protocol parameter defines the data frame format. The Motorola -//! frame formats imply the following polarity and phase configurations: -//! -//! 
-//! Polarity Phase       Mode
-//!   0       0   SSI_FRF_MOTO_MODE_0
-//!   0       1   SSI_FRF_MOTO_MODE_1
-//!   1       0   SSI_FRF_MOTO_MODE_2
-//!   1       1   SSI_FRF_MOTO_MODE_3
-//!
-//! -//! The \c ui32Mode parameter defines the operating mode of the SSI module. -//! The SSI module can operate as a master or slave; if a slave, the SSI can be -//! configured to disable output on its serial output line. -//! -//! The \c ui32BitRate parameter defines the bit rate for the SSI. This bit -//! rate must satisfy the following clock ratio criteria: -//! - Master mode : FSSI >= 2 * bit rate -//! - Slave mode : FSSI >= 12 * bit rate -//! -//! where FSSI is the frequency of the clock supplied to the SSI module. -//! -//! The \c ui32DataWidth parameter defines the width of the data transfers, and -//! can be a value between 4 and 16, inclusive. -//! -//! \note The peripheral clock is not necessarily the same as the processor clock. -//! The frequency of the peripheral clock is set by the system control. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32SSIClk is the rate of the clock supplied to the SSI module. -//! \param ui32Protocol specifies the data transfer protocol. -//! The parameter can be one of the following values: -//! - \ref SSI_FRF_MOTO_MODE_0 -//! - \ref SSI_FRF_MOTO_MODE_1 -//! - \ref SSI_FRF_MOTO_MODE_2 -//! - \ref SSI_FRF_MOTO_MODE_3 -//! - \ref SSI_FRF_TI -//! - \ref SSI_FRF_NMW. -//! \param ui32Mode specifies the mode of operation. -//! The parameter can be one of the following values: -//! - \ref SSI_MODE_MASTER -//! - \ref SSI_MODE_SLAVE -//! - \ref SSI_MODE_SLAVE_OD -//! \param ui32BitRate specifies the clock rate. -//! \param ui32DataWidth specifies number of bits transferred per frame. -//! Must be a value between 4 and 16, both included. -//! -//! \return None -// -//***************************************************************************** -extern void SSIConfigSetExpClk(uint32_t ui32Base, uint32_t ui32SSIClk, - uint32_t ui32Protocol, uint32_t ui32Mode, - uint32_t ui32BitRate, uint32_t ui32DataWidth); - -//***************************************************************************** -// -//! \brief Enables the synchronous serial port. -//! -//! This function enables operation of the synchronous serial port. The -//! synchronous serial port must be configured before it is enabled. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Read-modify-write the enable bit. - HWREG(ui32Base + SSI_O_CR1) |= SSI_CR1_SSE; -} - -//***************************************************************************** -// -//! \brief Disables the synchronous serial port. -//! -//! This function disables operation of the synchronous serial port. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIDisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Read-modify-write the enable bit. - HWREG(ui32Base + SSI_O_CR1) &= ~(SSI_CR1_SSE); -} - -//***************************************************************************** -// -//! \brief Puts a data element into the SSI transmit FIFO. -//! -//! This function places the supplied data into the transmit FIFO of the -//! specified SSI module. -//! -//! \note The upper 32 - N bits of the \c ui32Data are discarded by the -//! hardware, where N is the data width as configured by \ref SSIConfigSetExpClk(). -//! For example, if the interface is configured for 8-bit data width, the upper -//! 24 bits of \c ui32Data are discarded. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32Data is the data to be transmitted over the SSI interface. -//! -//! \return None -// -//***************************************************************************** -extern void SSIDataPut(uint32_t ui32Base, uint32_t ui32Data); - -//***************************************************************************** -// -//! \brief Puts a data element into the SSI transmit FIFO. -//! -//! This function places the supplied data into the transmit FIFO of the -//! specified SSI module. If there is no space in the FIFO, then this function -//! returns a zero. -//! -//! \note The upper 32 - N bits of the \c ui32Data are discarded by the hardware, -//! where N is the data width as configured by \ref SSIConfigSetExpClk(). For -//! example, if the interface is configured for 8-bit data width, the upper 24 -//! bits of \c ui32Data are discarded. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32Data is the data to be transmitted over the SSI interface. -//! -//! \return Returns the number of elements written to the SSI transmit FIFO. -// -//***************************************************************************** -extern int32_t SSIDataPutNonBlocking(uint32_t ui32Base, uint32_t ui32Data); - -//***************************************************************************** -// -//! \brief Gets a data element from the SSI receive FIFO. -//! -//! This function gets received data from the receive FIFO of the specified -//! SSI module and places that data into the location specified by the -//! \c pui32Data parameter. -//! -//! \note Only the lower N bits of the value written to \c pui32Data contain -//! valid data, where N is the data width as configured by -//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for -//! 8-bit data width, only the lower 8 bits of the value written to -//! \c pui32Data contain valid data. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pui32Data is a pointer to a storage location for data that was -//! received over the SSI interface. -//! -//! \return None -// -//***************************************************************************** -extern void SSIDataGet(uint32_t ui32Base, uint32_t *pui32Data); - -//***************************************************************************** -// -//! \brief Gets a data element from the SSI receive FIFO. -//! -//! This function gets received data from the receive FIFO of the specified SSI -//! module and places that data into the location specified by the \c ui32Data -//! parameter. If there is no data in the FIFO, then this function returns a -//! zero. -//! -//! \note Only the lower N bits of the value written to \c pui32Data contain -//! valid data, where N is the data width as configured by -//! \ref SSIConfigSetExpClk(). For example, if the interface is configured for -//! 8-bit data width, only the lower 8 bits of the value written to \c pui32Data -//! contain valid data. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pui32Data is a pointer to a storage location for data that was -//! received over the SSI interface. -//! -//! \return Returns the number of elements read from the SSI receive FIFO. -// -//***************************************************************************** -extern int32_t SSIDataGetNonBlocking(uint32_t ui32Base, uint32_t *pui32Data); - -//***************************************************************************** -// -//! \brief Determines whether the SSI transmitter is busy or not. -//! -//! Allows the caller to determine whether all transmitted bytes have cleared -//! the transmitter hardware. If \c false is returned, then the transmit FIFO -//! is empty and all bits of the last transmitted word have left the hardware -//! shift register. -//! -//! \param ui32Base is the base address of the SSI port. -//! -//! \return Returns status of the SSI transmit buffer. -//! - \c true : SSI is transmitting. -//! - \c false : SSI transmissions are complete. -// -//***************************************************************************** -__STATIC_INLINE bool -SSIBusy(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Determine if the SSI is busy. - return((HWREG(ui32Base + SSI_O_SR) & SSI_SR_BSY) ? true : false); -} - -//***************************************************************************** -// -//! \brief Get the status of the SSI data buffers. -//! -//! This function is used to poll the status of the internal FIFOs in the SSI -//! module. The status of both TX and RX FIFO is returned. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! \return Returns the current status of the internal SSI data buffers. -//! The status is a bitwise OR'ed combination of: -//! - \ref SSI_RX_FULL : Receive FIFO full. -//! - \ref SSI_RX_NOT_EMPTY : Receive FIFO not empty. -//! - \ref SSI_TX_NOT_FULL : Transmit FIFO not full. -//! - \ref SSI_TX_EMPTY : Transmit FIFO empty. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -SSIStatus(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Return the status - return (HWREG(ui32Base + SSI_O_SR) & SSI_STATUS_MASK); -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific SSI interrupts must be enabled via \ref SSIIntEnable(). If necessary, -//! it is the interrupt handler's responsibility to clear the interrupt source -//! via \ref SSIIntClear(). -//! -//! \param ui32Base specifies the SSI module base address. -//! \param pfnHandler is a pointer to the function to be called when the -//! synchronous serial port interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void SSIIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for the Synchronous Serial Interface in the dynamic interrupt table. -//! -//! This function will clear the handler to be called when a SSI -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \param ui32Base specifies the SSI module base address. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void SSIIntUnregister(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Enables individual SSI interrupt sources. -//! -//! Enables the indicated SSI interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be enabled. -//! - \ref SSI_TXFF -//! - \ref SSI_RXFF -//! - \ref SSI_RXTO -//! - \ref SSI_RXOR -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Enable the specified interrupts. - HWREG(ui32Base + SSI_O_IMSC) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Disables individual SSI interrupt sources. -//! -//! Disables the indicated SSI interrupt sources. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be disabled. -//! - \ref SSI_TXFF -//! - \ref SSI_RXFF -//! - \ref SSI_RXTO -//! - \ref SSI_RXOR -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Disable the specified interrupts. - HWREG(ui32Base + SSI_O_IMSC) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! \brief Clears SSI interrupt sources. -//! -//! The specified SSI interrupt sources are cleared so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupts from being recognized again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32Base specifies the SSI module base address. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! The parameter can consist of either or both of: -//! - \ref SSI_RXTO : Timeout interrupt. -//! - \ref SSI_RXOR : Overrun interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Clear the requested interrupt sources. - HWREG(ui32Base + SSI_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Gets the current interrupt status. -//! -//! This function returns the interrupt status for the SSI module. Either the -//! raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \param ui32Base specifies the SSI module base address. -//! \param bMasked selects either raw or masked interrupt. -//! \c false : Raw interrupt status is required. -//! \c true : Masked interrupt status is required. -//! -//! \return Returns the current interrupt status as an OR'ed combination of: -//! - \ref SSI_TXFF -//! - \ref SSI_RXFF -//! - \ref SSI_RXTO -//! - \ref SSI_RXOR -// -//***************************************************************************** -__STATIC_INLINE uint32_t -SSIIntStatus(uint32_t ui32Base, bool bMasked) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Return either the interrupt status or the raw interrupt status as - // requested. - if(bMasked) - { - return(HWREG(ui32Base + SSI_O_MIS)); - } - else - { - return(HWREG(ui32Base + SSI_O_RIS)); - } -} - -//***************************************************************************** -// -//! \brief Enable SSI DMA operation. -//! -//! The specified SSI DMA features are enabled. The SSI can be -//! configured to use DMA for transmit and/or receive data transfers. -//! -//! \note The uDMA controller must also be set up before DMA can be used -//! with the SSI. -//! -//! \param ui32Base is the base address of the SSI port. -//! \param ui32DMAFlags is a bit mask of the DMA features to enable. -//! The parameter is the bitwise OR of any of the following values: -//! - \ref SSI_DMA_RX : Enable DMA for receive. -//! - \ref SSI_DMA_TX : Enable DMA for transmit. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Set the requested bits in the SSI DMA control register. - HWREG(ui32Base + SSI_O_DMACR) |= ui32DMAFlags; -} - -//***************************************************************************** -// -//! \brief Disable SSI DMA operation. -//! -//! This function is used to disable SSI DMA features that were enabled -//! by \ref SSIDMAEnable(). The specified SSI DMA features are disabled. -//! -//! \param ui32Base is the base address of the SSI port. -//! \param ui32DMAFlags is a bit mask of the DMA features to disable. -//! The parameter is the bitwise OR of any of the following values: -//! - \ref SSI_DMA_RX : Disable DMA for receive. -//! - \ref SSI_DMA_TX : Disable DMA for transmit. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SSIDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // Check the arguments. - ASSERT(SSIBaseValid(ui32Base)); - - // Clear the requested bits in the SSI DMA control register. - HWREG(ui32Base + SSI_O_DMACR) &= ~ui32DMAFlags; -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_SSIConfigSetExpClk - #undef SSIConfigSetExpClk - #define SSIConfigSetExpClk ROM_SSIConfigSetExpClk - #endif - #ifdef ROM_SSIDataPut - #undef SSIDataPut - #define SSIDataPut ROM_SSIDataPut - #endif - #ifdef ROM_SSIDataPutNonBlocking - #undef SSIDataPutNonBlocking - #define SSIDataPutNonBlocking ROM_SSIDataPutNonBlocking - #endif - #ifdef ROM_SSIDataGet - #undef SSIDataGet - #define SSIDataGet ROM_SSIDataGet - #endif - #ifdef ROM_SSIDataGetNonBlocking - #undef SSIDataGetNonBlocking - #define SSIDataGetNonBlocking ROM_SSIDataGetNonBlocking - #endif - #ifdef ROM_SSIIntRegister - #undef SSIIntRegister - #define SSIIntRegister ROM_SSIIntRegister - #endif - #ifdef ROM_SSIIntUnregister - #undef SSIIntUnregister - #define SSIIntUnregister ROM_SSIIntUnregister - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SSI_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_chacha.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_chacha.c deleted file mode 100644 index 781f48fda44..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_chacha.c +++ /dev/null @@ -1,121 +0,0 @@ -/****************************************************************************** -* Filename: sw_chacha.c -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ -/* -chacha-ref.c version 20080118 -D. J. Bernstein -Public domain. -*/ - -#define ECRYPT_LITTLE_ENDIAN - -#include "sw_ecrypt-sync.h" - -#define ROTATE(v,c) (ROTL32(v,c)) -#define XOR(v,w) ((v) ^ (w)) -#define PLUS(v,w) (U32V((v) + (w))) -#define PLUSONE(v) (PLUS((v),1)) - -#define QUARTERROUND(a,b,c,d) \ - x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]),16); \ - x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]),12); \ - x[a] = PLUS(x[a],x[b]); x[d] = ROTATE(XOR(x[d],x[a]), 8); \ - x[c] = PLUS(x[c],x[d]); x[b] = ROTATE(XOR(x[b],x[c]), 7); - -static void salsa20_wordtobyte(u8 output[64],const u32 input[16]) -{ - u32 x[16]; - int i; - - for (i = 0;i < 16;++i) x[i] = input[i]; - for (i = 8;i > 0;i -= 2) { - QUARTERROUND( 0, 4, 8,12) - QUARTERROUND( 1, 5, 9,13) - QUARTERROUND( 2, 6,10,14) - QUARTERROUND( 3, 7,11,15) - QUARTERROUND( 0, 5,10,15) - QUARTERROUND( 1, 6,11,12) - QUARTERROUND( 2, 7, 8,13) - QUARTERROUND( 3, 4, 9,14) - } - for (i = 0;i < 16;++i) x[i] = PLUS(x[i],input[i]); - for (i = 0;i < 16;++i) U32TO8_LITTLE(output + 4 * i,x[i]); -} - -void ECRYPT_init(void) -{ - return; -} - -static const char sigma[16] = "expand 32-byte k"; -static const char tau[16] = "expand 16-byte k"; - -void ECRYPT_keysetup(ECRYPT_ctx *x,const u8 *k,u32 kbits,u32 ivbits) -{ - const char *constants; - - x->input[4] = U8TO32_LITTLE(k + 0); - x->input[5] = U8TO32_LITTLE(k + 4); - x->input[6] = U8TO32_LITTLE(k + 8); - x->input[7] = U8TO32_LITTLE(k + 12); - if (kbits == 256) { /* recommended */ - k += 16; - constants = sigma; - } else { /* kbits == 128 */ - constants = tau; - } - x->input[8] = U8TO32_LITTLE(k + 0); - x->input[9] = U8TO32_LITTLE(k + 4); - x->input[10] = U8TO32_LITTLE(k + 8); - x->input[11] = U8TO32_LITTLE(k + 12); - x->input[0] = U8TO32_LITTLE(constants + 0); - x->input[1] = U8TO32_LITTLE(constants + 4); - x->input[2] = U8TO32_LITTLE(constants + 8); - x->input[3] = U8TO32_LITTLE(constants + 12); -} - -void ECRYPT_ivsetup(ECRYPT_ctx *x,const u8 *iv) -{ - x->input[12] = 0; - x->input[13] = 0; - x->input[14] = U8TO32_LITTLE(iv + 0); - x->input[15] = U8TO32_LITTLE(iv + 4); -} - -void ECRYPT_encrypt_bytes(ECRYPT_ctx *x,const u8 *m,u8 *c,u32 bytes) -{ - u8 output[64]; - int i; - - if (!bytes) return; - for (;;) { - salsa20_wordtobyte(output,x->input); - x->input[12] = PLUSONE(x->input[12]); - if (!x->input[12]) { - x->input[13] = PLUSONE(x->input[13]); - /* stopping at 2^70 bytes per nonce is user's responsibility */ - } - if (bytes <= 64) { - for (i = 0;i < bytes;++i) c[i] = m[i] ^ output[i]; - return; - } - for (i = 0;i < 64;++i) c[i] = m[i] ^ output[i]; - bytes -= 64; - c += 64; - m += 64; - } -} - -void ECRYPT_decrypt_bytes(ECRYPT_ctx *x,const u8 *c,u8 *m,u32 bytes) -{ - ECRYPT_encrypt_bytes(x,c,m,bytes); -} - -void ECRYPT_keystream_bytes(ECRYPT_ctx *x,u8 *stream,u32 bytes) -{ - u32 i; - for (i = 0;i < bytes;++i) stream[i] = 0; - ECRYPT_encrypt_bytes(x,stream,stream,bytes); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h deleted file mode 100644 index 6ec233d3be6..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-config.h +++ /dev/null @@ -1,279 +0,0 @@ -/****************************************************************************** -* Filename: sw_ecrypt-config.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ -/* ecrypt-config.h */ - -/* *** Normally, it should not be necessary to edit this file. *** */ - -#ifndef ECRYPT_CONFIG -#define ECRYPT_CONFIG - -/* ------------------------------------------------------------------------- */ - -/* Guess the endianness of the target architecture. */ - -/* - * The LITTLE endian machines: - */ -#if ( ! defined(ECRYPT_LITTLE_ENDIAN)) -#if defined(__ultrix) /* Older MIPS */ -#define ECRYPT_LITTLE_ENDIAN -#elif defined(__alpha) /* Alpha */ -#define ECRYPT_LITTLE_ENDIAN -#elif defined(i386) /* x86 (gcc) */ -#define ECRYPT_LITTLE_ENDIAN -#elif defined(__i386) /* x86 (gcc) */ -#define ECRYPT_LITTLE_ENDIAN -#elif defined(_M_IX86) /* x86 (MSC, Borland) */ -#define ECRYPT_LITTLE_ENDIAN -#elif defined(_MSC_VER) /* x86 (surely MSC) */ -#define ECRYPT_LITTLE_ENDIAN -#elif defined(__INTEL_COMPILER) /* x86 (surely Intel compiler icl.exe) */ -#define ECRYPT_LITTLE_ENDIAN - -/* - * The BIG endian machines: - */ -#elif defined(sun) /* Newer Sparc's */ -#define ECRYPT_BIG_ENDIAN -#elif defined(__ppc__) /* PowerPC */ -#define ECRYPT_BIG_ENDIAN - -/* - * Finally machines with UNKNOWN endianness: - */ -#elif defined (_AIX) /* RS6000 */ -#define ECRYPT_UNKNOWN -#elif defined(__hpux) /* HP-PA */ -#define ECRYPT_UNKNOWN -#elif defined(__aux) /* 68K */ -#define ECRYPT_UNKNOWN -#elif defined(__dgux) /* 88K (but P6 in latest boxes) */ -#define ECRYPT_UNKNOWN -#elif defined(__sgi) /* Newer MIPS */ -#define ECRYPT_UNKNOWN -#else /* Any other processor */ -#define ECRYPT_UNKNOWN -#endif -#endif - -/* ------------------------------------------------------------------------- */ - -/* - * Find minimal-width types to store 8-bit, 16-bit, 32-bit, and 64-bit - * integers. - * - * Note: to enable 64-bit types on 32-bit compilers, it might be - * necessary to switch from ISO C90 mode to ISO C99 mode (e.g., gcc - * -std=c99). - */ - -#include - -/* --- check char --- */ - -#if (UCHAR_MAX / 0xFU > 0xFU) -#ifndef I8T -#define I8T char -#define U8C(v) (v##U) - -#if (UCHAR_MAX == 0xFFU) -#define ECRYPT_I8T_IS_BYTE -#endif - -#endif - -#if (UCHAR_MAX / 0xFFU > 0xFFU) -#ifndef I16T -#define I16T char -#define U16C(v) (v##U) -#endif - -#if (UCHAR_MAX / 0xFFFFU > 0xFFFFU) -#ifndef I32T -#define I32T char -#define U32C(v) (v##U) -#endif - -#if (UCHAR_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) -#ifndef I64T -#define I64T char -#define U64C(v) (v##U) -#define ECRYPT_NATIVE64 -#endif - -#endif -#endif -#endif -#endif - -/* --- check short --- */ - -#if (USHRT_MAX / 0xFU > 0xFU) -#ifndef I8T -#define I8T short -#define U8C(v) (v##U) - -#if (USHRT_MAX == 0xFFU) -#define ECRYPT_I8T_IS_BYTE -#endif - -#endif - -#if (USHRT_MAX / 0xFFU > 0xFFU) -#ifndef I16T -#define I16T short -#define U16C(v) (v##U) -#endif - -#if (USHRT_MAX / 0xFFFFU > 0xFFFFU) -#ifndef I32T -#define I32T short -#define U32C(v) (v##U) -#endif - -#if (USHRT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) -#ifndef I64T -#define I64T short -#define U64C(v) (v##U) -#define ECRYPT_NATIVE64 -#endif - -#endif -#endif -#endif -#endif - -/* --- check int --- */ - -#if (UINT_MAX / 0xFU > 0xFU) -#ifndef I8T -#define I8T int -#define U8C(v) (v##U) - -#if (ULONG_MAX == 0xFFU) -#define ECRYPT_I8T_IS_BYTE -#endif - -#endif - -#if (UINT_MAX / 0xFFU > 0xFFU) -#ifndef I16T -#define I16T int -#define U16C(v) (v##U) -#endif - -#if (UINT_MAX / 0xFFFFU > 0xFFFFU) -#ifndef I32T -#define I32T int -#define U32C(v) (v##U) -#endif - -#if (UINT_MAX / 0xFFFFFFFFU > 0xFFFFFFFFU) -#ifndef I64T -#define I64T int -#define U64C(v) (v##U) -#define ECRYPT_NATIVE64 -#endif - -#endif -#endif -#endif -#endif - -/* --- check long --- */ - -#if (ULONG_MAX / 0xFUL > 0xFUL) -#ifndef I8T -#define I8T long -#define U8C(v) (v##UL) - -#if (ULONG_MAX == 0xFFUL) -#define ECRYPT_I8T_IS_BYTE -#endif - -#endif - -#if (ULONG_MAX / 0xFFUL > 0xFFUL) -#ifndef I16T -#define I16T long -#define U16C(v) (v##UL) -#endif - -#if (ULONG_MAX / 0xFFFFUL > 0xFFFFUL) -#ifndef I32T -#define I32T long -#define U32C(v) (v##UL) -#endif - -#if (ULONG_MAX / 0xFFFFFFFFUL > 0xFFFFFFFFUL) -#ifndef I64T -#define I64T long -#define U64C(v) (v##UL) -#define ECRYPT_NATIVE64 -#endif - -#endif -#endif -#endif -#endif - -/* --- check long long --- */ - -#ifdef ULLONG_MAX - -#if (ULLONG_MAX / 0xFULL > 0xFULL) -#ifndef I8T -#define I8T long long -#define U8C(v) (v##ULL) - -#if (ULLONG_MAX == 0xFFULL) -#define ECRYPT_I8T_IS_BYTE -#endif - -#endif - -#if (ULLONG_MAX / 0xFFULL > 0xFFULL) -#ifndef I16T -#define I16T long long -#define U16C(v) (v##ULL) -#endif - -#if (ULLONG_MAX / 0xFFFFULL > 0xFFFFULL) -#ifndef I32T -#define I32T long long -#define U32C(v) (v##ULL) -#endif - -#if (ULLONG_MAX / 0xFFFFFFFFULL > 0xFFFFFFFFULL) -#ifndef I64T -#define I64T long long -#define U64C(v) (v##ULL) -#endif - -#endif -#endif -#endif -#endif - -#endif - -/* --- check __int64 --- */ - -#ifdef _UI64_MAX - -#if (_UI64_MAX / 0xFFFFFFFFui64 > 0xFFFFFFFFui64) -#ifndef I64T -#define I64T __int64 -#define U64C(v) (v##ui64) -#endif - -#endif - -#endif - -/* ------------------------------------------------------------------------- */ - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h deleted file mode 100644 index 7194dcb6c60..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-machine.h +++ /dev/null @@ -1,51 +0,0 @@ -/****************************************************************************** -* Filename: sw_ecrypt-machine.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ -/* ecrypt-machine.h */ - -/* - * This file is included by 'ecrypt-portable.h'. It allows to override - * the default macros for specific platforms. Please carefully check - * the machine code generated by your compiler (with optimisations - * turned on) before deciding to edit this file. - */ - -/* ------------------------------------------------------------------------- */ - -#if (defined(ECRYPT_DEFAULT_ROT) && !defined(ECRYPT_MACHINE_ROT)) - -#define ECRYPT_MACHINE_ROT - -#if (defined(WIN32) && defined(_MSC_VER)) - -#undef ROTL32 -#undef ROTR32 -#undef ROTL64 -#undef ROTR64 - -#include - -#define ROTL32(v, n) _lrotl(v, n) -#define ROTR32(v, n) _lrotr(v, n) -#define ROTL64(v, n) _rotl64(v, n) -#define ROTR64(v, n) _rotr64(v, n) - -#endif - -#endif - -/* ------------------------------------------------------------------------- */ - -#if (defined(ECRYPT_DEFAULT_SWAP) && !defined(ECRYPT_MACHINE_SWAP)) - -#define ECRYPT_MACHINE_SWAP - -/* - * If you want to overwrite the default swap macros, put it here. And so on. - */ - -#endif - -/* ------------------------------------------------------------------------- */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h deleted file mode 100644 index dd81b831688..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-portable.h +++ /dev/null @@ -1,308 +0,0 @@ -/****************************************************************************** -* Filename: sw_ecrypt-portable.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ -/* ecrypt-portable.h */ - -/* - * WARNING: the conversions defined below are implemented as macros, - * and should be used carefully. They should NOT be used with - * parameters which perform some action. E.g., the following two lines - * are not equivalent: - * - * 1) ++x; y = ROTL32(x, n); - * 2) y = ROTL32(++x, n); - */ - -/* - * *** Please do not edit this file. *** - * - * The default macros can be overridden for specific architectures by - * editing 'ecrypt-machine.h'. - */ - -#ifndef ECRYPT_PORTABLE -#define ECRYPT_PORTABLE - -#include "sw_ecrypt-config.h" - -/* ------------------------------------------------------------------------- */ - -/* - * The following types are defined (if available): - * - * u8: unsigned integer type, at least 8 bits - * u16: unsigned integer type, at least 16 bits - * u32: unsigned integer type, at least 32 bits - * u64: unsigned integer type, at least 64 bits - * - * s8, s16, s32, s64 -> signed counterparts of u8, u16, u32, u64 - * - * The selection of minimum-width integer types is taken care of by - * 'ecrypt-config.h'. Note: to enable 64-bit types on 32-bit - * compilers, it might be necessary to switch from ISO C90 mode to ISO - * C99 mode (e.g., gcc -std=c99). - */ - -#ifdef I8T -typedef signed I8T s8; -typedef unsigned I8T u8; -#endif - -#ifdef I16T -typedef signed I16T s16; -typedef unsigned I16T u16; -#endif - -#ifdef I32T -typedef signed I32T s32; -typedef unsigned I32T u32; -#endif - -#ifdef I64T -typedef signed I64T s64; -typedef unsigned I64T u64; -#endif - -/* - * The following macros are used to obtain exact-width results. - */ - -#define U8V(v) ((u8)(v) & U8C(0xFF)) -#define U16V(v) ((u16)(v) & U16C(0xFFFF)) -#define U32V(v) ((u32)(v) & U32C(0xFFFFFFFF)) -#define U64V(v) ((u64)(v) & U64C(0xFFFFFFFFFFFFFFFF)) - -/* ------------------------------------------------------------------------- */ - -/* - * The following macros return words with their bits rotated over n - * positions to the left/right. - */ - -#define ECRYPT_DEFAULT_ROT - -#define ROTL8(v, n) \ - (U8V((v) << (n)) | ((v) >> (8 - (n)))) - -#define ROTL16(v, n) \ - (U16V((v) << (n)) | ((v) >> (16 - (n)))) - -#define ROTL32(v, n) \ - (U32V((v) << (n)) | ((v) >> (32 - (n)))) - -#define ROTL64(v, n) \ - (U64V((v) << (n)) | ((v) >> (64 - (n)))) - -#define ROTR8(v, n) ROTL8(v, 8 - (n)) -#define ROTR16(v, n) ROTL16(v, 16 - (n)) -#define ROTR32(v, n) ROTL32(v, 32 - (n)) -#define ROTR64(v, n) ROTL64(v, 64 - (n)) - -#include "sw_ecrypt-machine.h" - -/* ------------------------------------------------------------------------- */ - -/* - * The following macros return a word with bytes in reverse order. - */ - -#define ECRYPT_DEFAULT_SWAP - -#define SWAP16(v) \ - ROTL16(v, 8) - -#define SWAP32(v) \ - ((ROTL32(v, 8) & U32C(0x00FF00FF)) | \ - (ROTL32(v, 24) & U32C(0xFF00FF00))) - -#ifdef ECRYPT_NATIVE64 -#define SWAP64(v) \ - ((ROTL64(v, 8) & U64C(0x000000FF000000FF)) | \ - (ROTL64(v, 24) & U64C(0x0000FF000000FF00)) | \ - (ROTL64(v, 40) & U64C(0x00FF000000FF0000)) | \ - (ROTL64(v, 56) & U64C(0xFF000000FF000000))) -#else -#define SWAP64(v) \ - (((u64)SWAP32(U32V(v)) << 32) | (u64)SWAP32(U32V(v >> 32))) -#endif - -#include "sw_ecrypt-machine.h" - -#define ECRYPT_DEFAULT_WTOW - -#ifdef ECRYPT_LITTLE_ENDIAN -#define U16TO16_LITTLE(v) (v) -#define U32TO32_LITTLE(v) (v) -#define U64TO64_LITTLE(v) (v) - -#define U16TO16_BIG(v) SWAP16(v) -#define U32TO32_BIG(v) SWAP32(v) -#define U64TO64_BIG(v) SWAP64(v) -#endif - -#ifdef ECRYPT_BIG_ENDIAN -#define U16TO16_LITTLE(v) SWAP16(v) -#define U32TO32_LITTLE(v) SWAP32(v) -#define U64TO64_LITTLE(v) SWAP64(v) - -#define U16TO16_BIG(v) (v) -#define U32TO32_BIG(v) (v) -#define U64TO64_BIG(v) (v) -#endif - -#include "sw_ecrypt-machine.h" - -/* - * The following macros load words from an array of bytes with - * different types of endianness, and vice versa. - */ - -#define ECRYPT_DEFAULT_BTOW - -#if (!defined(ECRYPT_UNKNOWN) && defined(ECRYPT_I8T_IS_BYTE)) - -#define U8TO16_LITTLE(p) U16TO16_LITTLE(((u16*)(p))[0]) -#define U8TO32_LITTLE(p) U32TO32_LITTLE(((u32*)(p))[0]) -#define U8TO64_LITTLE(p) U64TO64_LITTLE(((u64*)(p))[0]) - -#define U8TO16_BIG(p) U16TO16_BIG(((u16*)(p))[0]) -#define U8TO32_BIG(p) U32TO32_BIG(((u32*)(p))[0]) -#define U8TO64_BIG(p) U64TO64_BIG(((u64*)(p))[0]) - -#define U16TO8_LITTLE(p, v) (((u16*)(p))[0] = U16TO16_LITTLE(v)) -#define U32TO8_LITTLE(p, v) (((u32*)(p))[0] = U32TO32_LITTLE(v)) -#define U64TO8_LITTLE(p, v) (((u64*)(p))[0] = U64TO64_LITTLE(v)) - -#define U16TO8_BIG(p, v) (((u16*)(p))[0] = U16TO16_BIG(v)) -#define U32TO8_BIG(p, v) (((u32*)(p))[0] = U32TO32_BIG(v)) -#define U64TO8_BIG(p, v) (((u64*)(p))[0] = U64TO64_BIG(v)) - -#else - -#define U8TO16_LITTLE(p) \ - (((u16)((p)[0]) ) | \ - ((u16)((p)[1]) << 8)) - -#define U8TO32_LITTLE(p) \ - (((u32)((p)[0]) ) | \ - ((u32)((p)[1]) << 8) | \ - ((u32)((p)[2]) << 16) | \ - ((u32)((p)[3]) << 24)) - -#ifdef ECRYPT_NATIVE64 -#define U8TO64_LITTLE(p) \ - (((u64)((p)[0]) ) | \ - ((u64)((p)[1]) << 8) | \ - ((u64)((p)[2]) << 16) | \ - ((u64)((p)[3]) << 24) | \ - ((u64)((p)[4]) << 32) | \ - ((u64)((p)[5]) << 40) | \ - ((u64)((p)[6]) << 48) | \ - ((u64)((p)[7]) << 56)) -#else -#define U8TO64_LITTLE(p) \ - ((u64)U8TO32_LITTLE(p) | ((u64)U8TO32_LITTLE((p) + 4) << 32)) -#endif - -#define U8TO16_BIG(p) \ - (((u16)((p)[0]) << 8) | \ - ((u16)((p)[1]) )) - -#define U8TO32_BIG(p) \ - (((u32)((p)[0]) << 24) | \ - ((u32)((p)[1]) << 16) | \ - ((u32)((p)[2]) << 8) | \ - ((u32)((p)[3]) )) - -#ifdef ECRYPT_NATIVE64 -#define U8TO64_BIG(p) \ - (((u64)((p)[0]) << 56) | \ - ((u64)((p)[1]) << 48) | \ - ((u64)((p)[2]) << 40) | \ - ((u64)((p)[3]) << 32) | \ - ((u64)((p)[4]) << 24) | \ - ((u64)((p)[5]) << 16) | \ - ((u64)((p)[6]) << 8) | \ - ((u64)((p)[7]) )) -#else -#define U8TO64_BIG(p) \ - (((u64)U8TO32_BIG(p) << 32) | (u64)U8TO32_BIG((p) + 4)) -#endif - -#define U16TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ - } while (0) - -#define U32TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ - (p)[2] = U8V((v) >> 16); \ - (p)[3] = U8V((v) >> 24); \ - } while (0) - -#ifdef ECRYPT_NATIVE64 -#define U64TO8_LITTLE(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ - (p)[2] = U8V((v) >> 16); \ - (p)[3] = U8V((v) >> 24); \ - (p)[4] = U8V((v) >> 32); \ - (p)[5] = U8V((v) >> 40); \ - (p)[6] = U8V((v) >> 48); \ - (p)[7] = U8V((v) >> 56); \ - } while (0) -#else -#define U64TO8_LITTLE(p, v) \ - do { \ - U32TO8_LITTLE((p), U32V((v) )); \ - U32TO8_LITTLE((p) + 4, U32V((v) >> 32)); \ - } while (0) -#endif - -#define U16TO8_BIG(p, v) \ - do { \ - (p)[0] = U8V((v) ); \ - (p)[1] = U8V((v) >> 8); \ - } while (0) - -#define U32TO8_BIG(p, v) \ - do { \ - (p)[0] = U8V((v) >> 24); \ - (p)[1] = U8V((v) >> 16); \ - (p)[2] = U8V((v) >> 8); \ - (p)[3] = U8V((v) ); \ - } while (0) - -#ifdef ECRYPT_NATIVE64 -#define U64TO8_BIG(p, v) \ - do { \ - (p)[0] = U8V((v) >> 56); \ - (p)[1] = U8V((v) >> 48); \ - (p)[2] = U8V((v) >> 40); \ - (p)[3] = U8V((v) >> 32); \ - (p)[4] = U8V((v) >> 24); \ - (p)[5] = U8V((v) >> 16); \ - (p)[6] = U8V((v) >> 8); \ - (p)[7] = U8V((v) ); \ - } while (0) -#else -#define U64TO8_BIG(p, v) \ - do { \ - U32TO8_BIG((p), U32V((v) >> 32)); \ - U32TO8_BIG((p) + 4, U32V((v) )); \ - } while (0) -#endif - -#endif - -#include "sw_ecrypt-machine.h" - -/* ------------------------------------------------------------------------- */ - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h deleted file mode 100644 index 436d10887c2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_ecrypt-sync.h +++ /dev/null @@ -1,284 +0,0 @@ -/****************************************************************************** -* Filename: sw_ecrypt-sync.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ -/* ecrypt-sync.h */ - -/* - * Header file for synchronous stream ciphers without authentication - * mechanism. - * - * *** Please only edit parts marked with "[edit]". *** - */ - -#ifndef ECRYPT_SYNC -#define ECRYPT_SYNC - -#include "sw_ecrypt-portable.h" - -/* ------------------------------------------------------------------------- */ - -/* Cipher parameters */ - -/* - * The name of your cipher. - */ -#define ECRYPT_NAME "ChaCha8" -#define ECRYPT_PROFILE "_____" - -/* - * Specify which key and IV sizes are supported by your cipher. A user - * should be able to enumerate the supported sizes by running the - * following code: - * - * for (i = 0; ECRYPT_KEYSIZE(i) <= ECRYPT_MAXKEYSIZE; ++i) - * { - * keysize = ECRYPT_KEYSIZE(i); - * - * ... - * } - * - * All sizes are in bits. - */ - -#define ECRYPT_MAXKEYSIZE 256 /* [edit] */ -#define ECRYPT_KEYSIZE(i) (128 + (i)*128) /* [edit] */ - -#define ECRYPT_MAXIVSIZE 64 /* [edit] */ -#define ECRYPT_IVSIZE(i) (64 + (i)*64) /* [edit] */ - -/* ------------------------------------------------------------------------- */ - -/* Data structures */ - -/* - * ECRYPT_ctx is the structure containing the representation of the - * internal state of your cipher. - */ - -typedef struct -{ - u32 input[16]; /* could be compressed */ - /* - * [edit] - * - * Put here all state variable needed during the encryption process. - */ -} ECRYPT_ctx; - -/* ------------------------------------------------------------------------- */ - -/* Mandatory functions */ - -/* - * Key and message independent initialization. This function will be - * called once when the program starts (e.g., to build expanded S-box - * tables). - */ -void ECRYPT_init(void); - -/* - * Key setup. It is the user's responsibility to select the values of - * keysize and ivsize from the set of supported values specified - * above. - */ -void ECRYPT_keysetup( - ECRYPT_ctx* ctx, - const u8* key, - u32 keysize, /* Key size in bits. */ - u32 ivsize); /* IV size in bits. */ - -/* - * IV setup. After having called ECRYPT_keysetup(), the user is - * allowed to call ECRYPT_ivsetup() different times in order to - * encrypt/decrypt different messages with the same key but different - * IV's. - */ -void ECRYPT_ivsetup( - ECRYPT_ctx* ctx, - const u8* iv); - -/* - * Encryption/decryption of arbitrary length messages. - * - * For efficiency reasons, the API provides two types of - * encrypt/decrypt functions. The ECRYPT_encrypt_bytes() function - * (declared here) encrypts byte strings of arbitrary length, while - * the ECRYPT_encrypt_blocks() function (defined later) only accepts - * lengths which are multiples of ECRYPT_BLOCKLENGTH. - * - * The user is allowed to make multiple calls to - * ECRYPT_encrypt_blocks() to incrementally encrypt a long message, - * but he is NOT allowed to make additional encryption calls once he - * has called ECRYPT_encrypt_bytes() (unless he starts a new message - * of course). For example, this sequence of calls is acceptable: - * - * ECRYPT_keysetup(); - * - * ECRYPT_ivsetup(); - * ECRYPT_encrypt_blocks(); - * ECRYPT_encrypt_blocks(); - * ECRYPT_encrypt_bytes(); - * - * ECRYPT_ivsetup(); - * ECRYPT_encrypt_blocks(); - * ECRYPT_encrypt_blocks(); - * - * ECRYPT_ivsetup(); - * ECRYPT_encrypt_bytes(); - * - * The following sequence is not: - * - * ECRYPT_keysetup(); - * ECRYPT_ivsetup(); - * ECRYPT_encrypt_blocks(); - * ECRYPT_encrypt_bytes(); - * ECRYPT_encrypt_blocks(); - */ - -void ECRYPT_encrypt_bytes( - ECRYPT_ctx* ctx, - const u8* plaintext, - u8* ciphertext, - u32 msglen); /* Message length in bytes. */ - -void ECRYPT_decrypt_bytes( - ECRYPT_ctx* ctx, - const u8* ciphertext, - u8* plaintext, - u32 msglen); /* Message length in bytes. */ - -/* ------------------------------------------------------------------------- */ - -/* Optional features */ - -/* - * For testing purposes it can sometimes be useful to have a function - * which immediately generates keystream without having to provide it - * with a zero plaintext. If your cipher cannot provide this function - * (e.g., because it is not strictly a synchronous cipher), please - * reset the ECRYPT_GENERATES_KEYSTREAM flag. - */ - -#define ECRYPT_GENERATES_KEYSTREAM -#ifdef ECRYPT_GENERATES_KEYSTREAM - -void ECRYPT_keystream_bytes( - ECRYPT_ctx* ctx, - u8* keystream, - u32 length); /* Length of keystream in bytes. */ - -#endif - -/* ------------------------------------------------------------------------- */ - -/* Optional optimizations */ - -/* - * By default, the functions in this section are implemented using - * calls to functions declared above. However, you might want to - * implement them differently for performance reasons. - */ - -/* - * All-in-one encryption/decryption of (short) packets. - * - * The default definitions of these functions can be found in - * "ecrypt-sync.c". If you want to implement them differently, please - * undef the ECRYPT_USES_DEFAULT_ALL_IN_ONE flag. - */ -#define ECRYPT_USES_DEFAULT_ALL_IN_ONE /* [edit] */ - -void ECRYPT_encrypt_packet( - ECRYPT_ctx* ctx, - const u8* iv, - const u8* plaintext, - u8* ciphertext, - u32 msglen); - -void ECRYPT_decrypt_packet( - ECRYPT_ctx* ctx, - const u8* iv, - const u8* ciphertext, - u8* plaintext, - u32 msglen); - -/* - * Encryption/decryption of blocks. - * - * By default, these functions are defined as macros. If you want to - * provide a different implementation, please undef the - * ECRYPT_USES_DEFAULT_BLOCK_MACROS flag and implement the functions - * declared below. - */ - -#define ECRYPT_BLOCKLENGTH 64 /* [edit] */ - -#define ECRYPT_USES_DEFAULT_BLOCK_MACROS /* [edit] */ -#ifdef ECRYPT_USES_DEFAULT_BLOCK_MACROS - -#define ECRYPT_encrypt_blocks(ctx, plaintext, ciphertext, blocks) \ - ECRYPT_encrypt_bytes(ctx, plaintext, ciphertext, \ - (blocks) * ECRYPT_BLOCKLENGTH) - -#define ECRYPT_decrypt_blocks(ctx, ciphertext, plaintext, blocks) \ - ECRYPT_decrypt_bytes(ctx, ciphertext, plaintext, \ - (blocks) * ECRYPT_BLOCKLENGTH) - -#ifdef ECRYPT_GENERATES_KEYSTREAM - -#define ECRYPT_keystream_blocks(ctx, keystream, blocks) \ - ECRYPT_keystream_bytes(ctx, keystream, \ - (blocks) * ECRYPT_BLOCKLENGTH) - -#endif - -#else - -void ECRYPT_encrypt_blocks( - ECRYPT_ctx* ctx, - const u8* plaintext, - u8* ciphertext, - u32 blocks); /* Message length in blocks. */ - -void ECRYPT_decrypt_blocks( - ECRYPT_ctx* ctx, - const u8* ciphertext, - u8* plaintext, - u32 blocks); /* Message length in blocks. */ - -#ifdef ECRYPT_GENERATES_KEYSTREAM - -void ECRYPT_keystream_blocks( - ECRYPT_ctx* ctx, - const u8* keystream, - u32 blocks); /* Keystream length in blocks. */ - -#endif - -#endif - -/* - * If your cipher can be implemented in different ways, you can use - * the ECRYPT_VARIANT parameter to allow the user to choose between - * them at compile time (e.g., gcc -DECRYPT_VARIANT=3 ...). Please - * only use this possibility if you really think it could make a - * significant difference and keep the number of variants - * (ECRYPT_MAXVARIANT) as small as possible (definitely not more than - * 10). Note also that all variants should have exactly the same - * external interface (i.e., the same ECRYPT_BLOCKLENGTH, etc.). - */ -#define ECRYPT_MAXVARIANT 1 /* [edit] */ - -#ifndef ECRYPT_VARIANT -#define ECRYPT_VARIANT 1 -#endif - -#if (ECRYPT_VARIANT > ECRYPT_MAXVARIANT) -#error this variant does not exist -#endif - -/* ------------------------------------------------------------------------- */ - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h deleted file mode 100644 index b25d40a3f16..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna-32.h +++ /dev/null @@ -1,223 +0,0 @@ -/****************************************************************************** -* Filename: sw_poly1305-donna-32.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ -/* - poly1305 implementation using 32 bit * 32 bit = 64 bit multiplication and 64 bit addition -*/ - -#if defined(_MSC_VER) - #define POLY1305_NOINLINE __declspec(noinline) -#elif defined(__GNUC__) - #define POLY1305_NOINLINE __attribute__((noinline)) -#else - #define POLY1305_NOINLINE -#endif - -#define poly1305_block_size 16 - -/* 17 + sizeof(size_t) + 14*sizeof(unsigned long) */ -typedef struct { - unsigned long r[5]; - unsigned long h[5]; - unsigned long pad[4]; - size_t leftover; - unsigned char buffer[poly1305_block_size]; - unsigned char final; -} poly1305_state_internal_t; - -/* interpret four 8 bit unsigned integers as a 32 bit unsigned integer in little endian */ -static unsigned long -U8TO32(const unsigned char *p) { - return - (((unsigned long)(p[0] & 0xff) ) | - ((unsigned long)(p[1] & 0xff) << 8) | - ((unsigned long)(p[2] & 0xff) << 16) | - ((unsigned long)(p[3] & 0xff) << 24)); -} - -/* store a 32 bit unsigned integer as four 8 bit unsigned integers in little endian */ -static void -U32TO8(unsigned char *p, unsigned long v) { - p[0] = (v ) & 0xff; - p[1] = (v >> 8) & 0xff; - p[2] = (v >> 16) & 0xff; - p[3] = (v >> 24) & 0xff; -} - -void -poly1305_init(poly1305_context *ctx, const unsigned char key[32]) { - poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; - - /* r &= 0xffffffc0ffffffc0ffffffc0fffffff */ - st->r[0] = (U8TO32(&key[ 0]) ) & 0x3ffffff; - st->r[1] = (U8TO32(&key[ 3]) >> 2) & 0x3ffff03; - st->r[2] = (U8TO32(&key[ 6]) >> 4) & 0x3ffc0ff; - st->r[3] = (U8TO32(&key[ 9]) >> 6) & 0x3f03fff; - st->r[4] = (U8TO32(&key[12]) >> 8) & 0x00fffff; - - /* h = 0 */ - st->h[0] = 0; - st->h[1] = 0; - st->h[2] = 0; - st->h[3] = 0; - st->h[4] = 0; - - /* save pad for later */ - st->pad[0] = U8TO32(&key[16]); - st->pad[1] = U8TO32(&key[20]); - st->pad[2] = U8TO32(&key[24]); - st->pad[3] = U8TO32(&key[28]); - - st->leftover = 0; - st->final = 0; -} - -static void -poly1305_blocks(poly1305_state_internal_t *st, const unsigned char *m, size_t bytes) { - const unsigned long hibit = (st->final) ? 0 : (1UL << 24); /* 1 << 128 */ - unsigned long r0,r1,r2,r3,r4; - unsigned long s1,s2,s3,s4; - unsigned long h0,h1,h2,h3,h4; - unsigned long long d0,d1,d2,d3,d4; - unsigned long c; - - r0 = st->r[0]; - r1 = st->r[1]; - r2 = st->r[2]; - r3 = st->r[3]; - r4 = st->r[4]; - - s1 = r1 * 5; - s2 = r2 * 5; - s3 = r3 * 5; - s4 = r4 * 5; - - h0 = st->h[0]; - h1 = st->h[1]; - h2 = st->h[2]; - h3 = st->h[3]; - h4 = st->h[4]; - - while (bytes >= poly1305_block_size) { - /* h += m[i] */ - h0 += (U8TO32(m+ 0) ) & 0x3ffffff; - h1 += (U8TO32(m+ 3) >> 2) & 0x3ffffff; - h2 += (U8TO32(m+ 6) >> 4) & 0x3ffffff; - h3 += (U8TO32(m+ 9) >> 6) & 0x3ffffff; - h4 += (U8TO32(m+12) >> 8) | hibit; - - /* h *= r */ - d0 = ((unsigned long long)h0 * r0) + ((unsigned long long)h1 * s4) + ((unsigned long long)h2 * s3) + ((unsigned long long)h3 * s2) + ((unsigned long long)h4 * s1); - d1 = ((unsigned long long)h0 * r1) + ((unsigned long long)h1 * r0) + ((unsigned long long)h2 * s4) + ((unsigned long long)h3 * s3) + ((unsigned long long)h4 * s2); - d2 = ((unsigned long long)h0 * r2) + ((unsigned long long)h1 * r1) + ((unsigned long long)h2 * r0) + ((unsigned long long)h3 * s4) + ((unsigned long long)h4 * s3); - d3 = ((unsigned long long)h0 * r3) + ((unsigned long long)h1 * r2) + ((unsigned long long)h2 * r1) + ((unsigned long long)h3 * r0) + ((unsigned long long)h4 * s4); - d4 = ((unsigned long long)h0 * r4) + ((unsigned long long)h1 * r3) + ((unsigned long long)h2 * r2) + ((unsigned long long)h3 * r1) + ((unsigned long long)h4 * r0); - - /* (partial) h %= p */ - c = (unsigned long)(d0 >> 26); h0 = (unsigned long)d0 & 0x3ffffff; - d1 += c; c = (unsigned long)(d1 >> 26); h1 = (unsigned long)d1 & 0x3ffffff; - d2 += c; c = (unsigned long)(d2 >> 26); h2 = (unsigned long)d2 & 0x3ffffff; - d3 += c; c = (unsigned long)(d3 >> 26); h3 = (unsigned long)d3 & 0x3ffffff; - d4 += c; c = (unsigned long)(d4 >> 26); h4 = (unsigned long)d4 & 0x3ffffff; - h0 += c * 5; c = (h0 >> 26); h0 = h0 & 0x3ffffff; - h1 += c; - - m += poly1305_block_size; - bytes -= poly1305_block_size; - } - - st->h[0] = h0; - st->h[1] = h1; - st->h[2] = h2; - st->h[3] = h3; - st->h[4] = h4; -} - -POLY1305_NOINLINE void -poly1305_finish(poly1305_context *ctx, unsigned char mac[16]) { - poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; - unsigned long h0,h1,h2,h3,h4,c; - unsigned long g0,g1,g2,g3,g4; - unsigned long long f; - unsigned long mask; - - /* process the remaining block */ - if (st->leftover) { - size_t i = st->leftover; - st->buffer[i++] = 1; - for (; i < poly1305_block_size; i++) - st->buffer[i] = 0; - st->final = 1; - poly1305_blocks(st, st->buffer, poly1305_block_size); - } - - /* fully carry h */ - h0 = st->h[0]; - h1 = st->h[1]; - h2 = st->h[2]; - h3 = st->h[3]; - h4 = st->h[4]; - - c = h1 >> 26; h1 = h1 & 0x3ffffff; - h2 += c; c = h2 >> 26; h2 = h2 & 0x3ffffff; - h3 += c; c = h3 >> 26; h3 = h3 & 0x3ffffff; - h4 += c; c = h4 >> 26; h4 = h4 & 0x3ffffff; - h0 += c * 5; c = h0 >> 26; h0 = h0 & 0x3ffffff; - h1 += c; - - /* compute h + -p */ - g0 = h0 + 5; c = g0 >> 26; g0 &= 0x3ffffff; - g1 = h1 + c; c = g1 >> 26; g1 &= 0x3ffffff; - g2 = h2 + c; c = g2 >> 26; g2 &= 0x3ffffff; - g3 = h3 + c; c = g3 >> 26; g3 &= 0x3ffffff; - g4 = h4 + c - (1UL << 26); - - /* select h if h < p, or h + -p if h >= p */ - mask = (g4 >> ((sizeof(unsigned long) * 8) - 1)) - 1; - g0 &= mask; - g1 &= mask; - g2 &= mask; - g3 &= mask; - g4 &= mask; - mask = ~mask; - h0 = (h0 & mask) | g0; - h1 = (h1 & mask) | g1; - h2 = (h2 & mask) | g2; - h3 = (h3 & mask) | g3; - h4 = (h4 & mask) | g4; - - /* h = h % (2^128) */ - h0 = ((h0 ) | (h1 << 26)) & 0xffffffff; - h1 = ((h1 >> 6) | (h2 << 20)) & 0xffffffff; - h2 = ((h2 >> 12) | (h3 << 14)) & 0xffffffff; - h3 = ((h3 >> 18) | (h4 << 8)) & 0xffffffff; - - /* mac = (h + pad) % (2^128) */ - f = (unsigned long long)h0 + st->pad[0] ; h0 = (unsigned long)f; - f = (unsigned long long)h1 + st->pad[1] + (f >> 32); h1 = (unsigned long)f; - f = (unsigned long long)h2 + st->pad[2] + (f >> 32); h2 = (unsigned long)f; - f = (unsigned long long)h3 + st->pad[3] + (f >> 32); h3 = (unsigned long)f; - - U32TO8(mac + 0, h0); - U32TO8(mac + 4, h1); - U32TO8(mac + 8, h2); - U32TO8(mac + 12, h3); - - /* zero out the state */ - st->h[0] = 0; - st->h[1] = 0; - st->h[2] = 0; - st->h[3] = 0; - st->h[4] = 0; - st->r[0] = 0; - st->r[1] = 0; - st->r[2] = 0; - st->r[3] = 0; - st->r[4] = 0; - st->pad[0] = 0; - st->pad[1] = 0; - st->pad[2] = 0; - st->pad[3] = 0; -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.c deleted file mode 100644 index 63234fe68c7..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.c +++ /dev/null @@ -1,186 +0,0 @@ -/****************************************************************************** -* Filename: sw_poly1305-donna.c -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ - -#include "sw_poly1305-donna.h" - -#include "sw_poly1305-donna-32.h" - -void -poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes) { - poly1305_state_internal_t *st = (poly1305_state_internal_t *)ctx; - size_t i; - - /* handle leftover */ - if (st->leftover) { - size_t want = (poly1305_block_size - st->leftover); - if (want > bytes) - want = bytes; - for (i = 0; i < want; i++) - st->buffer[st->leftover + i] = m[i]; - bytes -= want; - m += want; - st->leftover += want; - if (st->leftover < poly1305_block_size) - return; - poly1305_blocks(st, st->buffer, poly1305_block_size); - st->leftover = 0; - } - - /* process full blocks */ - if (bytes >= poly1305_block_size) { - size_t want = (bytes & ~(poly1305_block_size - 1)); - poly1305_blocks(st, m, want); - m += want; - bytes -= want; - } - - /* store leftover */ - if (bytes) { - for (i = 0; i < bytes; i++) - st->buffer[st->leftover + i] = m[i]; - st->leftover += bytes; - } -} - -void -poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]) { - poly1305_context ctx; - poly1305_init(&ctx, key); - poly1305_update(&ctx, m, bytes); - poly1305_finish(&ctx, mac); -} - -int -poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]) { - size_t i; - unsigned int dif = 0; - for (i = 0; i < 16; i++) - dif |= (mac1[i] ^ mac2[i]); - dif = (dif - 1) >> ((sizeof(unsigned int) * 8) - 1); - return (dif & 1); -} - - -/* test a few basic operations */ -int -poly1305_power_on_self_test(void) { - /* example from nacl */ - static const unsigned char nacl_key[32] = { - 0xee,0xa6,0xa7,0x25,0x1c,0x1e,0x72,0x91, - 0x6d,0x11,0xc2,0xcb,0x21,0x4d,0x3c,0x25, - 0x25,0x39,0x12,0x1d,0x8e,0x23,0x4e,0x65, - 0x2d,0x65,0x1f,0xa4,0xc8,0xcf,0xf8,0x80 - }; - - static const unsigned char nacl_msg[131] = { - 0x8e,0x99,0x3b,0x9f,0x48,0x68,0x12,0x73, - 0xc2,0x96,0x50,0xba,0x32,0xfc,0x76,0xce, - 0x48,0x33,0x2e,0xa7,0x16,0x4d,0x96,0xa4, - 0x47,0x6f,0xb8,0xc5,0x31,0xa1,0x18,0x6a, - 0xc0,0xdf,0xc1,0x7c,0x98,0xdc,0xe8,0x7b, - 0x4d,0xa7,0xf0,0x11,0xec,0x48,0xc9,0x72, - 0x71,0xd2,0xc2,0x0f,0x9b,0x92,0x8f,0xe2, - 0x27,0x0d,0x6f,0xb8,0x63,0xd5,0x17,0x38, - 0xb4,0x8e,0xee,0xe3,0x14,0xa7,0xcc,0x8a, - 0xb9,0x32,0x16,0x45,0x48,0xe5,0x26,0xae, - 0x90,0x22,0x43,0x68,0x51,0x7a,0xcf,0xea, - 0xbd,0x6b,0xb3,0x73,0x2b,0xc0,0xe9,0xda, - 0x99,0x83,0x2b,0x61,0xca,0x01,0xb6,0xde, - 0x56,0x24,0x4a,0x9e,0x88,0xd5,0xf9,0xb3, - 0x79,0x73,0xf6,0x22,0xa4,0x3d,0x14,0xa6, - 0x59,0x9b,0x1f,0x65,0x4c,0xb4,0x5a,0x74, - 0xe3,0x55,0xa5 - }; - - static const unsigned char nacl_mac[16] = { - 0xf3,0xff,0xc7,0x70,0x3f,0x94,0x00,0xe5, - 0x2a,0x7d,0xfb,0x4b,0x3d,0x33,0x05,0xd9 - }; - - /* generates a final value of (2^130 - 2) == 3 */ - static const unsigned char wrap_key[32] = { - 0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - }; - - static const unsigned char wrap_msg[16] = { - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff - }; - - static const unsigned char wrap_mac[16] = { - 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 - }; - - /* - mac of the macs of messages of length 0 to 256, where the key and messages - have all their values set to the length - */ - static const unsigned char total_key[32] = { - 0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0xff,0xfe,0xfd,0xfc,0xfb,0xfa,0xf9, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff, - 0xff,0xff,0xff,0xff,0xff,0xff,0xff - }; - - static const unsigned char total_mac[16] = { - 0x64,0xaf,0xe2,0xe8,0xd6,0xad,0x7b,0xbd, - 0xd2,0x87,0xf9,0x7c,0x44,0x62,0x3d,0x39 - }; - - poly1305_context ctx; - poly1305_context total_ctx; - unsigned char all_key[32]; - unsigned char all_msg[256]; - unsigned char mac[16]; - size_t i, j; - int result = 1; - - for (i = 0; i < sizeof(mac); i++) - mac[i] = 0; - poly1305_auth(mac, nacl_msg, sizeof(nacl_msg), nacl_key); - result &= poly1305_verify(nacl_mac, mac); - - for (i = 0; i < sizeof(mac); i++) - mac[i] = 0; - poly1305_init(&ctx, nacl_key); - poly1305_update(&ctx, nacl_msg + 0, 32); - poly1305_update(&ctx, nacl_msg + 32, 64); - poly1305_update(&ctx, nacl_msg + 96, 16); - poly1305_update(&ctx, nacl_msg + 112, 8); - poly1305_update(&ctx, nacl_msg + 120, 4); - poly1305_update(&ctx, nacl_msg + 124, 2); - poly1305_update(&ctx, nacl_msg + 126, 1); - poly1305_update(&ctx, nacl_msg + 127, 1); - poly1305_update(&ctx, nacl_msg + 128, 1); - poly1305_update(&ctx, nacl_msg + 129, 1); - poly1305_update(&ctx, nacl_msg + 130, 1); - poly1305_finish(&ctx, mac); - result &= poly1305_verify(nacl_mac, mac); - - for (i = 0; i < sizeof(mac); i++) - mac[i] = 0; - poly1305_auth(mac, wrap_msg, sizeof(wrap_msg), wrap_key); - result &= poly1305_verify(wrap_mac, mac); - - poly1305_init(&total_ctx, total_key); - for (i = 0; i < 256; i++) { - /* set key and message to 'i,i,i..' */ - for (j = 0; j < sizeof(all_key); j++) - all_key[j] = i; - for (j = 0; j < i; j++) - all_msg[j] = i; - poly1305_auth(mac, all_msg, i, all_key); - poly1305_update(&total_ctx, mac, 16); - } - poly1305_finish(&total_ctx, mac); - result &= poly1305_verify(total_mac, mac); - - return result; -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h deleted file mode 100644 index 2c91e4a4715..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sw_poly1305-donna.h +++ /dev/null @@ -1,25 +0,0 @@ -/****************************************************************************** -* Filename: sw_poly1305-donna.h -* Revised: 2016-10-05 12:42:03 +0200 (Wed, 05 Oct 2016) -* Revision: 47308 -******************************************************************************/ - -#ifndef POLY1305_DONNA_H -#define POLY1305_DONNA_H - -#include - -typedef struct { - size_t aligner; - unsigned char opaque[136]; -} poly1305_context; - -void poly1305_init(poly1305_context *ctx, const unsigned char key[32]); -void poly1305_update(poly1305_context *ctx, const unsigned char *m, size_t bytes); -void poly1305_finish(poly1305_context *ctx, unsigned char mac[16]); -void poly1305_auth(unsigned char mac[16], const unsigned char *m, size_t bytes, const unsigned char key[32]); - -int poly1305_verify(const unsigned char mac1[16], const unsigned char mac2[16]); -int poly1305_power_on_self_test(void); - -#endif /* POLY1305_DONNA_H */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c deleted file mode 100644 index 1dd35f40e1c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.c +++ /dev/null @@ -1,375 +0,0 @@ -/****************************************************************************** -* Filename: sys_ctrl.c -* Revised: 2018-06-26 15:19:11 +0200 (Tue, 26 Jun 2018) -* Revision: 52220 -* -* Description: Driver for the System Control. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -// Hardware headers -#include "../inc/hw_types.h" -#include "../inc/hw_ccfg.h" -#include "../inc/hw_ioc.h" -// Driverlib headers -#include "aon_batmon.h" -#include "flash.h" -#include "gpio.h" -#include "setup_rom.h" -#include "sys_ctrl.h" - - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef SysCtrlIdle - #define SysCtrlIdle NOROM_SysCtrlIdle - #undef SysCtrlShutdownWithAbort - #define SysCtrlShutdownWithAbort NOROM_SysCtrlShutdownWithAbort - #undef SysCtrlShutdown - #define SysCtrlShutdown NOROM_SysCtrlShutdown - #undef SysCtrlStandby - #define SysCtrlStandby NOROM_SysCtrlStandby - #undef SysCtrlSetRechargeBeforePowerDown - #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown - #undef SysCtrlAdjustRechargeAfterPowerDown - #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown - #undef SysCtrl_DCDC_VoltageConditionalControl - #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl - #undef SysCtrlResetSourceGet - #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet -#endif - - - -//***************************************************************************** -// -// Force the system in to idle mode -// -//***************************************************************************** -void SysCtrlIdle(uint32_t vimsPdMode) -{ - // Configure the VIMS mode - HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) = vimsPdMode; - - // Always keep cache retention ON in IDLE - PRCMCacheRetentionEnable(); - - // Turn off the CPU power domain, will take effect when PRCMDeepSleep() executes - PRCMPowerDomainOff(PRCM_DOMAIN_CPU); - - // Ensure any possible outstanding AON writes complete - SysCtrlAonSync(); - - // Invoke deep sleep to go to IDLE - PRCMDeepSleep(); -} - -//***************************************************************************** -// -// Try to enter shutdown but abort if wakeup event happened before shutdown -// -//***************************************************************************** -void SysCtrlShutdownWithAbort(void) -{ - uint32_t wu_detect_vector = 0; - uint32_t io_num = 0; - - // For all IO CFG registers check if wakeup detect is enabled - for(io_num = 0; io_num < 32; io_num++) - { - // Read MSB from WU_CFG bit field - if( HWREG(IOC_BASE + IOC_O_IOCFG0 + (io_num * 4) ) & (1 << (IOC_IOCFG0_WU_CFG_S + IOC_IOCFG0_WU_CFG_W - 1)) ) - { - wu_detect_vector |= (1 << io_num); - } - } - - // Wakeup events are detected when pads are in sleep mode - PowerCtrlPadSleepEnable(); - - // Make sure all potential events have propagated before checking event flags - SysCtrlAonUpdate(); - SysCtrlAonUpdate(); - - // If no edge detect flags for wakeup enabled IOs are set then shut down the device - if( GPIO_getEventMultiDio(wu_detect_vector) == 0 ) - { - SysCtrlShutdown(); - } - else - { - PowerCtrlPadSleepDisable(); - } -} - -//***************************************************************************** -// -// Force the system into shutdown mode -// -//***************************************************************************** -void SysCtrlShutdown(void) -{ - // Request shutdown mode - HWREG(AON_PMCTL_BASE + AON_PMCTL_O_SHUTDOWN) = AON_PMCTL_SHUTDOWN_EN; - - // Make sure System CPU does not continue beyond this point. - // Shutdown happens when all shutdown conditions are met. - while(1); -} - -//***************************************************************************** -// -// Force the system in to standby mode -// -//***************************************************************************** -void SysCtrlStandby(bool retainCache, uint32_t vimsPdMode, uint32_t rechargeMode) -{ - uint32_t modeVIMS; - - // Freeze the IOs on the boundary between MCU and AON - AONIOCFreezeEnable(); - - // Ensure any possible outstanding AON writes complete before turning off the power domains - SysCtrlAonSync(); - - // Request power off of domains in the MCU voltage domain - PRCMPowerDomainOff(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | PRCM_DOMAIN_PERIPH | PRCM_DOMAIN_CPU); - - // Ensure that no clocks are forced on in any modes for Crypto, DMA and I2S - HWREG(PRCM_BASE + PRCM_O_SECDMACLKGR) &= (~PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN & ~PRCM_SECDMACLKGR_DMA_AM_CLK_EN); - HWREG(PRCM_BASE + PRCM_O_I2SCLKGR) &= ~PRCM_I2SCLKGR_AM_CLK_EN; - - // Gate running deep sleep clocks for Crypto, DMA and I2S - PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_CRYPTO); - PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_UDMA); - PRCMPeripheralDeepSleepDisable(PRCM_PERIPH_I2S); - - // Load the new clock settings - PRCMLoadSet(); - - // Configure the VIMS power domain mode - HWREG(PRCM_BASE + PRCM_O_PDCTL1VIMS) = vimsPdMode; - - // Request uLDO during standby - PRCMMcuUldoConfigure(1); - - // Check the regulator mode - if (HWREG(AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL) & AON_PMCTL_PWRCTL_EXT_REG_MODE) - { - // In external regulator mode the recharge functionality is disabled - HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = 0x00000000; - } - else - { - // In internal regulator mode the recharge functionality is set up with - // adaptive recharge mode and fixed parameter values - if(rechargeMode == SYSCTRL_PREFERRED_RECHARGE_MODE) - { - // Enable the Recharge Comparator - HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = AON_PMCTL_RECHARGECFG_MODE_COMPARATOR; - } - else - { - // Set requested recharge mode - HWREG(AON_PMCTL_BASE + AON_PMCTL_O_RECHARGECFG) = rechargeMode; - } - } - - // Ensure all writes have taken effect - SysCtrlAonSync(); - - // Ensure UDMA, Crypto and I2C clocks are turned off - while (!PRCMLoadGet()) {;} - - // Ensure power domains have been turned off. - // CPU power domain will power down when PRCMDeepSleep() executes. - while (PRCMPowerDomainStatus(PRCM_DOMAIN_RFCORE | PRCM_DOMAIN_SERIAL | PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_OFF) {;} - - // Turn off cache retention if requested - if (retainCache == false) { - - // Get the current VIMS mode - do { - modeVIMS = VIMSModeGet(VIMS_BASE); - } while (modeVIMS == VIMS_MODE_CHANGING); - - // If in a cache mode, turn VIMS off - if (modeVIMS == VIMS_MODE_ENABLED) { - VIMSModeSet(VIMS_BASE, VIMS_MODE_OFF); - } - - // Disable retention of cache RAM - PRCMCacheRetentionDisable(); - } - - // Invoke deep sleep to go to STANDBY - PRCMDeepSleep(); -} - -//***************************************************************************** -// -// SysCtrlSetRechargeBeforePowerDown( xoscPowerMode ) -// -//***************************************************************************** -void -SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ) -{ - uint32_t ccfg_ModeConfReg ; - - // read the MODE_CONF register in CCFG - ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); - // Do temperature compensation if enabled - if (( ccfg_ModeConfReg & CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC ) == 0 ) { - int32_t vddrSleepDelta ; - int32_t curTemp ; - int32_t tcDelta ; - int32_t vddrSleepTrim ; - - // Get VDDR_TRIM_SLEEP_DELTA + 1 (sign extended) ==> vddrSleepDelta = -7..+8 - vddrSleepDelta = (((int32_t)( ccfg_ModeConfReg << ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ))) - >> ( 32 - CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W )) + 1 ; - curTemp = AONBatMonTemperatureGetDegC(); - tcDelta = ( 62 - curTemp ) >> 3; - if ( tcDelta > 7 ) { - tcDelta = 7 ; - } - if ( tcDelta > vddrSleepDelta ) { - vddrSleepDelta = tcDelta ; - } - vddrSleepTrim = (( HWREG( FLASH_CFG_BASE + FCFG1_OFFSET + FCFG1_O_MISC_TRIM ) & FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_M ) >> - FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_S ) ; - vddrSleepTrim -= vddrSleepDelta ; - if ( vddrSleepTrim > 15 ) vddrSleepTrim = 15 ; - if ( vddrSleepTrim < 1 ) vddrSleepTrim = 1 ; - // Write adjusted value using MASKED write (MASK8) - HWREGB( ADI3_BASE + ADI_O_MASK4B + ( ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 * 2 )) = (( ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_M << 4 ) | - (( vddrSleepTrim << ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_S ) & ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_M ) ); - // Make a dummy read in order to make sure the write above is done before going into standby - HWREGB( ADI3_BASE + ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 ); - } -} - - -//***************************************************************************** -// -// SysCtrlAdjustRechargeAfterPowerDown() -// -//***************************************************************************** -void -SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ) -{ - // Nothing to be done but keeping this function for platform compatibility. -} - - -//***************************************************************************** -// -// SysCtrl_DCDC_VoltageConditionalControl() -// -//***************************************************************************** -void -SysCtrl_DCDC_VoltageConditionalControl( void ) -{ - uint32_t batThreshold ; // Fractional format with 8 fractional bits. - uint32_t aonBatmonBat ; // Fractional format with 8 fractional bits. - uint32_t ccfg_ModeConfReg ; // Holds a copy of the CCFG_O_MODE_CONF register. - uint32_t aonPmctlPwrctl ; // Reflect whats read/written to the AON_PMCTL_O_PWRCTL register. - - // We could potentially call this function before any battery voltage measurement - // is made/available. In that case we must make sure that we do not turn off the DCDC. - // This can be done by doing nothing as long as the battery voltage is 0 (Since the - // reset value of the battery voltage register is 0). - aonBatmonBat = HWREG( AON_BATMON_BASE + AON_BATMON_O_BAT ); - if ( aonBatmonBat != 0 ) { - // Check if Voltage Conditional Control is enabled - // It is enabled if all the following are true: - // - DCDC in use (either in active or recharge mode), (in use if one of the corresponding CCFG bits are zero). - // - Alternative DCDC settings are enabled ( DIS_ALT_DCDC_SETTING == 0 ) - // - Not in external regulator mode ( EXT_REG_MODE == 0 ) - ccfg_ModeConfReg = HWREG( CCFG_BASE + CCFG_O_MODE_CONF ); - - if (((( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) || - (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) ) && - (( HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) & AON_PMCTL_PWRCTL_EXT_REG_MODE ) == 0 ) && - (( HWREG( CCFG_BASE + CCFG_O_SIZE_AND_DIS_FLAGS ) & CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING ) == 0 ) ) - { - aonPmctlPwrctl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ); - batThreshold = (((( HWREG( CCFG_BASE + CCFG_O_MODE_CONF_1 ) & - CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) >> - CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) + 28 ) << 4 ); - - if ( aonPmctlPwrctl & ( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M )) { - // DCDC is ON, check if it should be switched off - if ( aonBatmonBat < batThreshold ) { - aonPmctlPwrctl &= ~( AON_PMCTL_PWRCTL_DCDC_EN_M | AON_PMCTL_PWRCTL_DCDC_ACTIVE_M ); - - HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl; - } - } else { - // DCDC is OFF, check if it should be switched on - if ( aonBatmonBat > batThreshold ) { - if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_RECHARGE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_EN_M ; - if (( ccfg_ModeConfReg & CCFG_MODE_CONF_DCDC_ACTIVE_M ) == 0 ) aonPmctlPwrctl |= AON_PMCTL_PWRCTL_DCDC_ACTIVE_M ; - - HWREG( AON_PMCTL_BASE + AON_PMCTL_O_PWRCTL ) = aonPmctlPwrctl; - } - } - } - } -} - - -//***************************************************************************** -// -// SysCtrlResetSourceGet() -// -//***************************************************************************** -uint32_t -SysCtrlResetSourceGet( void ) -{ - uint32_t aonPmctlResetCtl = HWREG( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL ); - - if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_WU_FROM_SD_M ) { - if ( aonPmctlResetCtl & AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M ) { - return ( RSTSRC_WAKEUP_FROM_SHUTDOWN ); - } else { - return ( RSTSRC_WAKEUP_FROM_TCK_NOISE ); - } - } else { - return (( aonPmctlResetCtl & AON_PMCTL_RESETCTL_RESET_SRC_M ) >> AON_PMCTL_RESETCTL_RESET_SRC_S ); - } -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h deleted file mode 100644 index 6dbe8318461..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/sys_ctrl.h +++ /dev/null @@ -1,577 +0,0 @@ -/****************************************************************************** -* Filename: sys_ctrl.h -* Revised: 2018-09-17 14:58:51 +0200 (Mon, 17 Sep 2018) -* Revision: 52634 -* -* Description: Defines and prototypes for the System Controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup sysctrl_api -//! @{ -// -//***************************************************************************** - -#ifndef __SYSCTRL_H__ -#define __SYSCTRL_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_sysctl.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_nvic.h" -#include "../inc/hw_aon_ioc.h" -#include "../inc/hw_ddi_0_osc.h" -#include "../inc/hw_rfc_pwr.h" -#include "../inc/hw_prcm.h" -#include "../inc/hw_adi_3_refsys.h" -#include "../inc/hw_aon_pmctl.h" -#include "../inc/hw_aon_rtc.h" -#include "../inc/hw_fcfg1.h" -#include "interrupt.h" -#include "debug.h" -#include "pwr_ctrl.h" -#include "osc.h" -#include "prcm.h" -#include "adi.h" -#include "ddi.h" -#include "cpu.h" -#include "vims.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define SysCtrlIdle NOROM_SysCtrlIdle - #define SysCtrlShutdownWithAbort NOROM_SysCtrlShutdownWithAbort - #define SysCtrlShutdown NOROM_SysCtrlShutdown - #define SysCtrlStandby NOROM_SysCtrlStandby - #define SysCtrlSetRechargeBeforePowerDown NOROM_SysCtrlSetRechargeBeforePowerDown - #define SysCtrlAdjustRechargeAfterPowerDown NOROM_SysCtrlAdjustRechargeAfterPowerDown - #define SysCtrl_DCDC_VoltageConditionalControl NOROM_SysCtrl_DCDC_VoltageConditionalControl - #define SysCtrlResetSourceGet NOROM_SysCtrlResetSourceGet -#endif - -//***************************************************************************** -// -// Defines for the settings of the main XOSC -// -//***************************************************************************** -#define SYSCTRL_SYSBUS_ON 0x00000001 -#define SYSCTRL_SYSBUS_OFF 0x00000000 - -//***************************************************************************** -// -// Defines for the different power modes of the System CPU -// -//***************************************************************************** -#define CPU_RUN 0x00000000 -#define CPU_SLEEP 0x00000001 -#define CPU_DEEP_SLEEP 0x00000002 - -//***************************************************************************** -// -// Defines for SysCtrlSetRechargeBeforePowerDown -// -//***************************************************************************** -#define XOSC_IN_HIGH_POWER_MODE 0 // When xosc_hf is in HIGH_POWER_XOSC -#define XOSC_IN_LOW_POWER_MODE 1 // When xosc_hf is in LOW_POWER_XOSC - -//***************************************************************************** -// -// Defines for the vimsPdMode parameter of SysCtrlIdle and SysCtrlStandby -// -//***************************************************************************** -#define VIMS_ON_CPU_ON_MODE 0 // VIMS power domain is only powered when CPU power domain is powered -#define VIMS_ON_BUS_ON_MODE 1 // VIMS power domain is powered whenever the BUS power domain is powered -#define VIMS_NO_PWR_UP_MODE 2 // VIMS power domain is not powered up at next wakeup. - -//***************************************************************************** -// -// Defines for the rechargeMode parameter of SysCtrlStandby -// -//***************************************************************************** -#define SYSCTRL_PREFERRED_RECHARGE_MODE \ - 0xFFFFFFFF // Preferred recharge mode - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Force the system into idle mode. -//! -//! This function forces the system into IDLE mode by configuring the requested -//! VIMS mode, enabling cache retention and powering off the CPU power domain. -//! -//! \param vimsPdMode selects the requested VIMS power domain mode -//! The parameter must be one of the following: -//! - \ref VIMS_ON_CPU_ON_MODE -//! - \ref VIMS_ON_BUS_ON_MODE -//! - \ref VIMS_NO_PWR_UP_MODE -//! -//! \return None -// -//***************************************************************************** -extern void SysCtrlIdle(uint32_t vimsPdMode); - -//***************************************************************************** -// -//! \brief Try to enter shutdown but abort if wakeup event happened before shutdown. -//! -//! This function puts the device in shutdown state if no wakeup events are -//! detected before shutdown. -//! -//! Compared to the basic \ref SysCtrlShutdown() function this function makes sure -//! that wakeup events that happen before actual shutdown are also detected. This -//! function either enters shutdown with a guaranteed wakeup detection or returns -//! to the caller function due to a pre-shutdown wakeup event. -//! -//! See \ref SysCtrlShutdown() for basic information about how to configure the device before -//! shutdown and how to wakeup from shutdown. -//! -//! This function uses IO edge detection in addition to the mandatory wakeup configuration. -//! Additional requirements to the application for this function are: -//! - \b Before : -//! - When the application configures an IO for wakeup (see \ref IOCIOShutdownSet()) -//! the application must also configure the same IO for edge detection -//! (see \ref IOCIOIntSet()). -//! - Edge detection must use the same polarity as the wakeup configuration. -//! - Application must enable peripheral power domain (see \ref PRCMPowerDomainOn()) -//! and enable GPIO module in the peripheral power domain (see \ref PRCMPeripheralRunEnable()). -//! - \b After : -//! - An edge, with same polarity as a wakeup event, was detected on a wakeup -//! enabled IO before shutdown, and the shutdown was aborted. The application must -//! clear the event generated by the edge detect (see \ref GPIO_clearEventDio()) and -//! decide what happens next. -//! -//! Useful functions related to shutdown: -//! - \ref IOCIOShutdownSet() : Enables wakeup from shutdown. -//! - \ref IOCIOIntSet() : Enables IO edge detection. -//! - \ref PRCMPowerDomainOn() : Enables peripheral power domain. -//! - \ref PRCMPeripheralRunEnable() : Enables GPIO module. -//! - \ref SysCtrlResetSourceGet() : Detects wakeup from shutdown. -//! - \ref PowerCtrlPadSleepDisable() : Unlatches outputs (disables pad sleep) after -//! wakeup from shutdown. -//! - \ref GPIO_clearEventDio() : Clears edge detects. -//! -//! It is recommended to disable interrupts before calling this function because: -//! - Pads are in sleep mode while this function runs. -//! - An interrupt routine might be terminated if it is triggered after the decision -//! to enter shutdown. -//! -//! \return None -// -//***************************************************************************** -extern void SysCtrlShutdownWithAbort(void); - -//***************************************************************************** -// -//! \brief Enable shutdown of the device. -//! -//! This function puts the device in shutdown state. The device automatically -//! latches all outputs (pads in sleep) before it turns off all internal power -//! supplies. -//! -//! JTAG must be disconnected and JTAG power domain must be off before device can -//! enter shutdown. This function waits until the device satisfies all shutdown -//! conditions before it enters shutdown. -//! -//! \note The application must unlatch the outputs when the device wakes up from shutdown. -//! It is recommended that any outputs that need to be restored after a wakeup from -//! shutdown are restored before outputs are unlatched in order to avoid glitches. -//! -//! See \ref PowerCtrlPadSleepDisable() for information about how to unlatch outputs -//! (disable pad sleep) after wakeup from shutdown. -//! -//! \note Wakeup events are only detected after the device enters shutdown. -//! -//! See \ref IOCIOShutdownSet() for information about how to enable wakeup from shutdown. -//! -//! See \ref SysCtrlResetSourceGet() for information about how to detect wakeup -//! from shutdown. -//! -//! It is recommended to disable interrupts before calling this function. Shutdown -//! happens immediately when the device satisfies all shutdown conditions thus -//! interrupt routines triggered after this function is called might be -//! aborted. -//! -//! \return This function does \b not return. -// -//***************************************************************************** -extern void SysCtrlShutdown(void); - -//***************************************************************************** -// -//! \brief Force the system into standby mode. -//! -//! This function forces all power domains (RFCORE, SERIAL, PERIPHERAL) off. -//! The VIMS and CPU power domains are turned off by the HW when the -//! \ref PRCMDeepSleep() function is called. -//! The IOs are latched (frozen) before the power domains are turned off to -//! avoid glitches. -//! The VIMS retention (cache) and VIMS module are turned off if requested. -//! The deep-sleep clock for the crypto and DMA modules are turned off, -//! as they must be off in order to enter standby. -//! This function assumes that the LF clock has already been switched to -//! and that the LF clock qualifiers must have been disabled/bypassed. -//! -//! In internal regulator mode the adaptive recharge functionality is enabled -//! with fixed parameter values. -//! In external regulator mode the recharge functionality is disabled. -//! -//! \note This function is optimized to execute with TI-RTOS. There might be -//! application specific prerequisites you would want to do before entering -//! standby which deviate from this specific implementation. -//! -//! \param retainCache selects if VIMS cache shall be retained or not. -//! - false : VIMS cache is not retained -//! - true : VIMS cache is retained -//! \param vimsPdMode selects the VIMS power domain mode. -//! The parameter must be one of the following: -//! - \ref VIMS_ON_CPU_ON_MODE -//! - \ref VIMS_NO_PWR_UP_MODE -//! \param rechargeMode specifies the requested recharge mode. -//! The parameter must be one of the following: -//! - \ref SYSCTRL_PREFERRED_RECHARGE_MODE : Preferred recharge mode specified by TI -//! -//! \return None -// -//***************************************************************************** -extern void SysCtrlStandby(bool retainCache, uint32_t vimsPdMode, uint32_t rechargeMode); - -//***************************************************************************** -// -//! \brief Get the CPU core clock frequency. -//! -//! Use this function to get the current clock frequency for the CPU. -//! -//! The CPU can run from 48 MHz and down to 750kHz. The frequency is defined -//! by the combined division factor of the SYSBUS and the CPU clock divider. -//! -//! \return Returns the current CPU core clock frequency. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -SysCtrlClockGet( void ) -{ - // Return fixed clock speed - return( GET_MCU_CLOCK ); -} - -//***************************************************************************** -// -//! \brief Sync all accesses to the AON register interface. -//! -//! When this function returns, all writes to the AON register interface are -//! guaranteed to have propagated to hardware. The function will return -//! immediately if no AON writes are pending; otherwise, it will wait for the next -//! AON clock before returning. -//! -//! \return None -//! -//! \sa \ref SysCtrlAonUpdate() -// -//***************************************************************************** -__STATIC_INLINE void -SysCtrlAonSync(void) -{ - // Sync the AON interface - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); -} - -//***************************************************************************** -// -//! \brief Update all interfaces to AON. -//! -//! When this function returns, at least 1 clock cycle has progressed on the -//! AON domain, so that any outstanding updates to and from the AON interface -//! is guaranteed to be in sync. -//! -//! \note This function should primarily be used after wakeup from sleep modes, -//! as it will guarantee that all shadow registers on the AON interface are updated -//! before reading any AON registers from the MCU domain. If a write has been -//! done to the AON interface it is sufficient to call the \ref SysCtrlAonSync(). -//! -//! \return None -//! -//! \sa \ref SysCtrlAonSync() -// -//***************************************************************************** -__STATIC_INLINE void -SysCtrlAonUpdate(void) -{ - // Force a clock cycle on the AON interface to guarantee all registers are - // in sync. - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC) = 1; - HWREG(AON_RTC_BASE + AON_RTC_O_SYNC); -} - -//***************************************************************************** -// -//! \brief Set Recharge values before entering Power Down. -//! -//! This function shall be called just before entering Power Down. -//! This function typically does nothing (default setting), but -//! if temperature compensated recharge level are enabled (by setting -//! CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC = 0) -//! it adds temperature compensation to the recharge level. -//! -//! \param xoscPowerMode (typically running in XOSC_IN_HIGH_POWER_MODE all the time). -//! - \ref XOSC_IN_HIGH_POWER_MODE : When xosc_hf is in HIGH_POWER_XOSC. -//! - \ref XOSC_IN_LOW_POWER_MODE : When xosc_hf is in LOW_POWER_XOSC. -//! -//! \return None -// -//***************************************************************************** -extern void SysCtrlSetRechargeBeforePowerDown( uint32_t xoscPowerMode ); - -//***************************************************************************** -// -//! \brief Adjust Recharge calculations to be used next. -//! -//! Nothing to be done but keeping this function for platform compatibility. -//! -//! \return None -// -//***************************************************************************** -extern void SysCtrlAdjustRechargeAfterPowerDown( uint32_t vddrRechargeMargin ); - -//***************************************************************************** -// -//! \brief Turns DCDC on or off depending of what is considered to be optimal usage. -//! -//! This function controls the DCDC only if both the following CCFG settings are \c true: -//! - DCDC is configured to be used. -//! - Alternative DCDC settings are defined and enabled. -//! -//! The DCDC is configured in accordance to the CCFG settings when turned on. -//! -//! This function should be called periodically. -//! -//! \return None -// -//***************************************************************************** -extern void SysCtrl_DCDC_VoltageConditionalControl( void ); - -//***************************************************************************** -// \name Return values from calling SysCtrlResetSourceGet() -//@{ -//***************************************************************************** -#define RSTSRC_PWR_ON (( AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_PIN_RESET (( AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_VDDS_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_VDDR_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_CLK_LOSS (( AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_SYSRESET (( AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_WARMRESET (( AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) -#define RSTSRC_WAKEUP_FROM_SHUTDOWN ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 1 ) -#define RSTSRC_WAKEUP_FROM_TCK_NOISE ((( AON_PMCTL_RESETCTL_RESET_SRC_M ) >> ( AON_PMCTL_RESETCTL_RESET_SRC_S )) + 2 ) -//@} - -//***************************************************************************** -// -//! \brief Returns the reset source (including "wakeup from shutdown"). -//! -//! In case of \ref RSTSRC_WAKEUP_FROM_SHUTDOWN the application is -//! responsible for unlatching the outputs (disable pad sleep). -//! See \ref PowerCtrlPadSleepDisable() for more information. -//! -//! \return Returns the reset source. -//! - \ref RSTSRC_PWR_ON -//! - \ref RSTSRC_PIN_RESET -//! - \ref RSTSRC_VDDS_LOSS -//! - \ref RSTSRC_VDDR_LOSS -//! - \ref RSTSRC_CLK_LOSS -//! - \ref RSTSRC_SYSRESET -//! - \ref RSTSRC_WARMRESET -//! - \ref RSTSRC_WAKEUP_FROM_SHUTDOWN -//! - \ref RSTSRC_WAKEUP_FROM_TCK_NOISE -// -//***************************************************************************** -extern uint32_t SysCtrlResetSourceGet( void ); - -//***************************************************************************** -// -//! \brief Perform a full system reset. -//! -//! \return The chip will reset and hence never return from this call. -// -//***************************************************************************** -__STATIC_INLINE void -SysCtrlSystemReset( void ) -{ - // Disable CPU interrupts - CPUcpsid(); - // Write reset register - HWREGBITW( AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_SYSRESET_BITN ) = 1; - // Finally, wait until the above write propagates - while ( 1 ) { - // Do nothing, just wait for the reset (and never return from here) - } -} - -//***************************************************************************** -// -//! \brief Enables reset if OSC clock loss event is asserted. -//! -//! Clock loss circuit in analog domain must be enabled as well in order to -//! actually enable for a clock loss reset to occur -//! \ref OSCClockLossEventEnable(). -//! -//! \note This function shall typically not be called because the clock loss -//! reset functionality is controlled by the boot code (a factory configuration -//! defines whether it is set or not). -//! -//! \return None -//! -//! \sa \ref SysCtrlClockLossResetDisable(), \ref OSCClockLossEventEnable() -// -//***************************************************************************** -__STATIC_INLINE void -SysCtrlClockLossResetEnable(void) -{ - // Set clock loss enable bit in AON_SYSCTRL using bit banding - HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Disables reset due to OSC clock loss event. -//! -//! \note This function shall typically not be called because the clock loss -//! reset functionality is controlled by the boot code (a factory configuration -//! defines whether it is set or not). -//! -//! \return None -//! -//! \sa \ref SysCtrlClockLossResetEnable() -// -//***************************************************************************** -__STATIC_INLINE void -SysCtrlClockLossResetDisable(void) -{ - // Clear clock loss enable bit in AON_SYSCTRL using bit banding - HWREGBITW(AON_PMCTL_BASE + AON_PMCTL_O_RESETCTL, AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN) = 0; -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_SysCtrlIdle - #undef SysCtrlIdle - #define SysCtrlIdle ROM_SysCtrlIdle - #endif - #ifdef ROM_SysCtrlShutdownWithAbort - #undef SysCtrlShutdownWithAbort - #define SysCtrlShutdownWithAbort ROM_SysCtrlShutdownWithAbort - #endif - #ifdef ROM_SysCtrlShutdown - #undef SysCtrlShutdown - #define SysCtrlShutdown ROM_SysCtrlShutdown - #endif - #ifdef ROM_SysCtrlStandby - #undef SysCtrlStandby - #define SysCtrlStandby ROM_SysCtrlStandby - #endif - #ifdef ROM_SysCtrlSetRechargeBeforePowerDown - #undef SysCtrlSetRechargeBeforePowerDown - #define SysCtrlSetRechargeBeforePowerDown ROM_SysCtrlSetRechargeBeforePowerDown - #endif - #ifdef ROM_SysCtrlAdjustRechargeAfterPowerDown - #undef SysCtrlAdjustRechargeAfterPowerDown - #define SysCtrlAdjustRechargeAfterPowerDown ROM_SysCtrlAdjustRechargeAfterPowerDown - #endif - #ifdef ROM_SysCtrl_DCDC_VoltageConditionalControl - #undef SysCtrl_DCDC_VoltageConditionalControl - #define SysCtrl_DCDC_VoltageConditionalControl ROM_SysCtrl_DCDC_VoltageConditionalControl - #endif - #ifdef ROM_SysCtrlResetSourceGet - #undef SysCtrlResetSourceGet - #define SysCtrlResetSourceGet ROM_SysCtrlResetSourceGet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SYSCTRL_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick.c deleted file mode 100644 index 6a64e2d634c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick.c +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: systick.c -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Driver for the SysTick timer in NVIC -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "systick.h" - -// See systick.h for implementation diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h deleted file mode 100644 index a70702c3104..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick.h +++ /dev/null @@ -1,287 +0,0 @@ -/****************************************************************************** -* Filename: systick.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Prototypes for the SysTick driver. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_cpu_group -//! @{ -//! \addtogroup systick_api -//! @{ -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_ints.h" -#include "../inc/hw_nvic.h" -#include "../inc/hw_types.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// API Functions and Prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Enables the SysTick counter. -//! -//! This will start the SysTick counter. If an interrupt handler has been -//! registered, it will be called when the SysTick counter rolls over. -//! -//! \note Calling this function will cause the SysTick counter to (re)commence -//! counting from its current value. The counter is not automatically reloaded -//! with the period as specified in a previous call to \ref SysTickPeriodSet(). If -//! an immediate reload is required, the NVIC_ST_CURRENT register must be -//! written to force this. Any write to this register clears the SysTick -//! counter to 0 and will cause a reload with the supplied period on the next -//! clock. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SysTickEnable(void) -{ - // Enable SysTick. - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; -} - -//***************************************************************************** -// -//! \brief Disables the SysTick counter. -//! -//! This will stop the SysTick counter. If an interrupt handler has been -//! registered, it will no longer be called until SysTick is restarted. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SysTickDisable(void) -{ - // Disable SysTick. - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for the SysTick interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! SysTick interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -SysTickIntRegister(void (*pfnHandler)(void)) -{ - // Register the interrupt handler, returning an error if an error occurs. - IntRegister(INT_SYSTICK, pfnHandler); - - // Enable the SysTick interrupt. - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; -} - -//***************************************************************************** -// -//! \brief Unregisters the interrupt handler for the SysTick interrupt in the dynamic interrupt table. -//! -//! This function will clear the handler to be called when a SysTick interrupt -//! occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -SysTickIntUnregister(void) -{ - // Disable the SysTick interrupt. - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - - // Unregister the interrupt handler. - IntUnregister(INT_SYSTICK); -} - -//***************************************************************************** -// -//! \brief Enables the SysTick interrupt. -//! -//! This function will enable the SysTick interrupt, allowing it to be -//! reflected to the processor. -//! -//! \note The SysTick interrupt handler does not need to clear the SysTick -//! interrupt source as this is done automatically by NVIC when the interrupt -//! handler is called. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SysTickIntEnable(void) -{ - // Enable the SysTick interrupt. - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; -} - -//***************************************************************************** -// -//! \brief Disables the SysTick interrupt. -//! -//! This function will disable the SysTick interrupt, preventing it from being -//! reflected to the processor. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SysTickIntDisable(void) -{ - // Disable the SysTick interrupt. - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); -} - -//***************************************************************************** -// -//! \brief Sets the period of the SysTick counter. -//! -//! This function sets the rate at which the SysTick counter wraps; this -//! equals to the number of processor clocks between interrupts. -//! -//! \note Calling this function does not cause the SysTick counter to reload -//! immediately. If an immediate reload is required, the NVIC_ST_CURRENT -//! register must be written. Any write to this register clears the SysTick -//! counter to 0 and will cause a reload with the \c ui32Period supplied here -//! on the next clock after the SysTick is enabled. -//! -//! \param ui32Period is the number of clock ticks in each period of the -//! SysTick counter; must be between 1 and 16,777,216 (0x1000000), both included. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -SysTickPeriodSet(uint32_t ui32Period) -{ - // Check the arguments. - ASSERT((ui32Period > 0) && (ui32Period <= 16777216)); - - // Set the period of the SysTick counter. - HWREG(NVIC_ST_RELOAD) = ui32Period - 1; -} - -//***************************************************************************** -// -//! \brief Gets the period of the SysTick counter. -//! -//! This function returns the rate at which the SysTick counter wraps; this -//! equals to the number of processor clocks between interrupts. -//! -//! \return Returns the period of the SysTick counter. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -SysTickPeriodGet(void) -{ - // Return the period of the SysTick counter. - return(HWREG(NVIC_ST_RELOAD) + 1); -} - -//***************************************************************************** -// -//! \brief Gets the current value of the SysTick counter. -//! -//! This function returns the current value of the SysTick counter; this will -//! be a value between the (period - 1) and zero, both included. -//! -//! \return Returns the current value of the SysTick counter -// -//***************************************************************************** -__STATIC_INLINE uint32_t -SysTickValueGet(void) -{ - // Return the current value of the SysTick counter. - return(HWREG(NVIC_ST_CURRENT)); -} - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ - -//***************************************************************************** -// -//! Close the Doxygen group -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h deleted file mode 100644 index 47a37de3d64..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/systick_doc.h +++ /dev/null @@ -1,68 +0,0 @@ -/****************************************************************************** -* Filename: systick_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup systick_api -//! @{ -//! \section sec_systick Introduction -//! -//! The system CPU includes a system timer, SysTick, integrated in the NVIC which provides a simple, 24-bit, -//! clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. -//! When enabled, the timer counts down on each clock from the reload value to 0, reloads (wraps) on -//! the next clock edge, then decrements on subsequent clocks. -//! -//! The SysTick counter runs on the system clock. If this clock signal is stopped for low-power mode, the -//! SysTick counter stops. -//! -//! When the processor is halted for debugging, the counter does not decrement. -//! -//! \section sec_systick_api API -//! -//! The API functions can be grouped like this: -//! -//! Configuration and status: -//! - \ref SysTickPeriodSet() -//! - \ref SysTickPeriodGet() -//! - \ref SysTickValueGet() -//! -//! Enable and disable: -//! - \ref SysTickEnable() -//! - \ref SysTickDisable() -//! -//! Interrupt configuration: -//! - \ref SysTickIntRegister() -//! - \ref SysTickIntUnregister() -//! - \ref SysTickIntEnable() -//! - \ref SysTickIntDisable() -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer.c deleted file mode 100644 index 5acc1a632bc..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer.c +++ /dev/null @@ -1,392 +0,0 @@ -/****************************************************************************** -* Filename: timer.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for the General Purpose Timer -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "timer.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef TimerConfigure - #define TimerConfigure NOROM_TimerConfigure - #undef TimerLevelControl - #define TimerLevelControl NOROM_TimerLevelControl - #undef TimerStallControl - #define TimerStallControl NOROM_TimerStallControl - #undef TimerWaitOnTriggerControl - #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl - #undef TimerIntRegister - #define TimerIntRegister NOROM_TimerIntRegister - #undef TimerIntUnregister - #define TimerIntUnregister NOROM_TimerIntUnregister - #undef TimerMatchUpdateMode - #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode - #undef TimerIntervalLoadMode - #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode -#endif - -//***************************************************************************** -// -//! \brief Gets the timer interrupt number. -//! -//! Given a timer base address, this function returns the corresponding -//! interrupt number. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! \return Returns a timer interrupt number, or -1 if \c ui32Base is invalid. -// -//***************************************************************************** -static uint32_t -TimerIntNumberGet(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // Loop through the table that maps timer base addresses to interrupt - // numbers. - switch(ui32Base) - { - case GPT0_BASE : - ui32Int = INT_GPT0A; - break; - case GPT1_BASE : - ui32Int = INT_GPT1A; - break; - case GPT2_BASE : - ui32Int = INT_GPT2A; - break; - case GPT3_BASE : - ui32Int = INT_GPT3A; - break; - default : - ui32Int = 0x0; - } - - // Return the interrupt number or (-1) if not base address is not matched. - return (ui32Int); -} - -//***************************************************************************** -// -// Configures the timer(s) -// -//***************************************************************************** -void -TimerConfigure(uint32_t ui32Base, uint32_t ui32Config) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Config == TIMER_CFG_ONE_SHOT) || - (ui32Config == TIMER_CFG_ONE_SHOT_UP) || - (ui32Config == TIMER_CFG_PERIODIC) || - (ui32Config == TIMER_CFG_PERIODIC_UP) || - ((ui32Config & 0xFF000000) == TIMER_CFG_SPLIT_PAIR)); - ASSERT(((ui32Config & 0xFF000000) != TIMER_CFG_SPLIT_PAIR) || - ((((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_ONE_SHOT_UP) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_PERIODIC_UP) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_COUNT_UP) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_CAP_TIME_UP) || - ((ui32Config & 0x000000FF) == TIMER_CFG_A_PWM)) && - (((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_ONE_SHOT_UP) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PERIODIC_UP) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_COUNT_UP) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_CAP_TIME_UP) || - ((ui32Config & 0x0000FF00) == TIMER_CFG_B_PWM)))); - - // Disable the timers. - HWREG(ui32Base + GPT_O_CTL) &= ~(GPT_CTL_TAEN | GPT_CTL_TBEN); - - // Set the global timer configuration. - HWREG(ui32Base + GPT_O_CFG) = ui32Config >> 24; - - // Set the configuration of the A and B timers. Note that the B timer - // configuration is ignored by the hardware in 32-bit modes. - HWREG(ui32Base + GPT_O_TAMR) = (ui32Config & 0xFF) | GPT_TAMR_TAPWMIE; - HWREG(ui32Base + GPT_O_TBMR) = - ((ui32Config >> 8) & 0xFF) | GPT_TBMR_TBPWMIE; -} - -//***************************************************************************** -// -// Controls the output level -// -//***************************************************************************** -void -TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, bool bInvert) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Set the output levels as requested. - ui32Timer &= GPT_CTL_TAPWML | GPT_CTL_TBPWML; - HWREG(ui32Base + GPT_O_CTL) = (bInvert ? - (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : - (HWREG(ui32Base + GPT_O_CTL) & - ~(ui32Timer))); -} - -//***************************************************************************** -// -// Controls the stall handling -// -//***************************************************************************** -void -TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, bool bStall) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Set the stall mode. - ui32Timer &= GPT_CTL_TASTALL | GPT_CTL_TBSTALL; - HWREG(ui32Base + GPT_O_CTL) = (bStall ? - (HWREG(ui32Base + GPT_O_CTL) | ui32Timer) : - (HWREG(ui32Base + GPT_O_CTL) & ~(ui32Timer))); -} - -//***************************************************************************** -// -// Controls the wait on trigger handling -// -//***************************************************************************** -void -TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, bool bWait) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Set the wait on trigger mode for timer A. - if(ui32Timer & TIMER_A) - { - if(bWait) - { - HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAWOT; - } - else - { - HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAWOT); - } - } - - // Set the wait on trigger mode for timer B. - if(ui32Timer & TIMER_B) - { - if(bWait) - { - HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBWOT; - } - else - { - HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBWOT); - } - } -} - -//***************************************************************************** -// -// Registers an interrupt handler for the timer interrupt -// -//***************************************************************************** -void -TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Get the interrupt number for this timer module. - ui32Int = TimerIntNumberGet(ui32Base); - - // Register an interrupt handler for timer A if requested. - if(ui32Timer & TIMER_A) - { - // Register the interrupt handler. - IntRegister(ui32Int, pfnHandler); - - // Enable the interrupt. - IntEnable(ui32Int); - } - - // Register an interrupt handler for timer B if requested. - if(ui32Timer & TIMER_B) - { - // Register the interrupt handler. - IntRegister(ui32Int + 1, pfnHandler); - - // Enable the interrupt. - IntEnable(ui32Int + 1); - } -} - -//***************************************************************************** -// -// Unregisters an interrupt handler for the timer interrupt -// -//***************************************************************************** -void -TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer) -{ - uint32_t ui32Int; - - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Get the interrupt number for this timer module. - ui32Int = TimerIntNumberGet(ui32Base); - - // Unregister the interrupt handler for timer A if requested. - if(ui32Timer & TIMER_A) - { - // Disable the interrupt. - IntDisable(ui32Int); - - // Unregister the interrupt handler. - IntUnregister(ui32Int); - } - - // Unregister the interrupt handler for timer B if requested. - if(ui32Timer & TIMER_B) - { - // Disable the interrupt. - IntDisable(ui32Int + 1); - - // Unregister the interrupt handler. - IntUnregister(ui32Int + 1); - } -} - -//***************************************************************************** -// -// Sets the Match Register Update mode -// -//***************************************************************************** -void -TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) -{ - // Check the arguments - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); - ASSERT((ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) || (ui32Mode == TIMER_MATCHUPDATE_TIMEOUT)); - - // Set mode for timer A - if(ui32Timer & TIMER_A) - { - if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) - { - HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAMRSU); - } - else - { - HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAMRSU; - } - } - - // Set mode for timer B - if(ui32Timer & TIMER_B) - { - if(ui32Mode == TIMER_MATCHUPDATE_NEXTCYCLE) - { - HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBMRSU); - } - else - { - HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBMRSU; - } - } -} - -//***************************************************************************** -// -// Sets the Interval Load mode -// -//***************************************************************************** -void -TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode) -{ - // Check the arguments - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || (ui32Timer == TIMER_BOTH)); - ASSERT((ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) || (ui32Mode == TIMER_INTERVALLOAD_TIMEOUT)); - - // Set mode for timer A - if(ui32Timer & TIMER_A) - { - if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) - { - HWREG(ui32Base + GPT_O_TAMR) &= ~(GPT_TAMR_TAILD); - } - else - { - HWREG(ui32Base + GPT_O_TAMR) |= GPT_TAMR_TAILD; - } - } - - // Set mode for timer B - if(ui32Timer & TIMER_B) - { - if(ui32Mode == TIMER_INTERVALLOAD_NEXTCYCLE) - { - HWREG(ui32Base + GPT_O_TBMR) &= ~(GPT_TBMR_TBILD); - } - else - { - HWREG(ui32Base + GPT_O_TBMR) |= GPT_TBMR_TBILD; - } - } -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h deleted file mode 100644 index d34e6ce323e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer.h +++ /dev/null @@ -1,1176 +0,0 @@ -/****************************************************************************** -* Filename: timer.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//**************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup timer_api -//! @{ -// -//**************************************************************************** - -#ifndef __GPT_H__ -#define __GPT_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_ints.h" -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_gpt.h" -#include "interrupt.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define TimerConfigure NOROM_TimerConfigure - #define TimerLevelControl NOROM_TimerLevelControl - #define TimerStallControl NOROM_TimerStallControl - #define TimerWaitOnTriggerControl NOROM_TimerWaitOnTriggerControl - #define TimerIntRegister NOROM_TimerIntRegister - #define TimerIntUnregister NOROM_TimerIntUnregister - #define TimerMatchUpdateMode NOROM_TimerMatchUpdateMode - #define TimerIntervalLoadMode NOROM_TimerIntervalLoadMode -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ui32Config parameter. -// -//***************************************************************************** -#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer -#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count timer -#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer -#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count timer -#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers -#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer -#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer -#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer -#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer -#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer -#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer -#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ui32IntFlags parameter, and returned from -// TimerIntStatus. -// -//***************************************************************************** -#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt -#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt -#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ui32Event parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ui32Timer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000FF // Timer A -#define TIMER_B 0x0000FF00 // Timer B -#define TIMER_BOTH 0x0000FFFF // Timer Both - -//***************************************************************************** -// -// Values that can be passed to GPTSynchronize as the ui32Timers parameter -// -//***************************************************************************** -#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A -#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B -#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A -#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B -#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A -#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B -#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A -#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B - -//***************************************************************************** -// -// Values that can be passed to TimerMatchUpdateMode -// -//***************************************************************************** -#define TIMER_MATCHUPDATE_NEXTCYCLE 0x00000000 // Apply match register on next cycle -#define TIMER_MATCHUPDATE_TIMEOUT 0x00000001 // Apply match register on next timeout - -//***************************************************************************** -// -// Values that can be passed to TimerIntervalLoad -// -//***************************************************************************** -#define TIMER_INTERVALLOAD_NEXTCYCLE 0x00000000 // Load TxR register with the value in the TxILR register on the next clock cycle -#define TIMER_INTERVALLOAD_TIMEOUT 0x00000001 // Load TxR register with the value in the TxILR register on next timeout - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! -//! \brief Checks a timer base address. -//! -//! This function determines if a timer module base address is valid. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -TimerBaseValid(uint32_t ui32Base) -{ - return((ui32Base == GPT0_BASE) || (ui32Base == GPT1_BASE) || - (ui32Base == GPT2_BASE) || (ui32Base == GPT3_BASE)); -} -#endif - -//***************************************************************************** -// -//! \brief Enables the timer(s). -//! -//! This function enables operation of the timer module. The timer must be -//! configured before it is enabled. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to enable. Must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerEnable(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Enable the timer(s) module. - HWREG(ui32Base + GPT_O_CTL) |= ui32Timer & (GPT_CTL_TAEN | GPT_CTL_TBEN); -} - -//***************************************************************************** -// -//! \brief Disables the timer(s). -//! -//! This function disables operation of the timer module. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to disable. Must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerDisable(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Disable the timer module. - HWREG(ui32Base + GPT_O_CTL) &= ~(ui32Timer & - (GPT_CTL_TAEN | GPT_CTL_TBEN)); -} - -//***************************************************************************** -// -//! \brief Configures the timer(s). -//! -//! This function configures the operating mode of the timer(s). The timer -//! module is disabled before being configured and is left in the disabled -//! state. -//! -//! The timers are comprised of two 16-bit timers that can -//! operate independently or be concatenated to form a 32-bit timer. -//! -//! \note If the timers are used independently the length of timer can be -//! extended to 24 bit by use of an 8 bit prescale register set using -//! \ref TimerPrescaleSet(). -//! -//! When configuring for full-width timer \c ui32Config is set -//! as one of the following values: -//! - \ref TIMER_CFG_ONE_SHOT : Full-width one-shot timer. -//! - \ref TIMER_CFG_ONE_SHOT_UP : Full-width one-shot timer that counts up -//! instead of down. -//! - \ref TIMER_CFG_PERIODIC : Full-width periodic timer. -//! - \ref TIMER_CFG_PERIODIC_UP : Full-width periodic timer that counts up -//! instead of down. -//! -//! When configuring for a pair of half-width timers, each timer is separately -//! configured. The timers are configured by setting \c ui32Config to -//! the bitwise OR of one of each of the following three: -//! - Use half-width timers: -//! - \ref TIMER_CFG_SPLIT_PAIR -//! - Timer A: -//! - \ref TIMER_CFG_A_ONE_SHOT : Half-width one-shot timer -//! - \ref TIMER_CFG_A_ONE_SHOT_UP : Half-width one-shot timer that counts up -//! instead of down. -//! - \ref TIMER_CFG_A_PERIODIC : Half-width periodic timer -//! - \ref TIMER_CFG_A_PERIODIC_UP : Half-width periodic timer that counts up -//! instead of down. -//! - \ref TIMER_CFG_A_CAP_COUNT : Half-width edge count capture -//! - \ref TIMER_CFG_A_CAP_COUNT_UP : Half-width edge count capture that counts -//! up instead of down. -//! - \ref TIMER_CFG_A_CAP_TIME : Half-width edge time capture -//! - \ref TIMER_CFG_A_CAP_TIME_UP : Half-width edge time capture that counts up -//! instead of down. -//! - \ref TIMER_CFG_A_PWM : Half-width PWM output -//! - Timer B: -//! - Same as Timer A but using TIMER_CFG_B_* instead. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Config is the configuration for the timer. -//! -//! \return None -// -//***************************************************************************** -extern void TimerConfigure(uint32_t ui32Base, uint32_t ui32Config); - -//***************************************************************************** -// -//! \brief Controls the output level. -//! -//! This function configures the PWM output level for the specified timer. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust. Must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param bInvert specifies the output level. -//! - \c true : Timer's output is active low. -//! - \c false : Timer's output is active high. -//! -//! \return None -// -//***************************************************************************** -extern void TimerLevelControl(uint32_t ui32Base, uint32_t ui32Timer, - bool bInvert); - -//***************************************************************************** -// -//! \brief Controls the event type. -//! -//! This function configures the signal edge(s) that triggers the timer when -//! in capture mode. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Event specifies the type of event; must be one of: -//! - \ref TIMER_EVENT_POS_EDGE -//! - \ref TIMER_EVENT_NEG_EDGE -//! - \ref TIMER_EVENT_BOTH_EDGES -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerEventControl(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Event) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Set the event type. - ui32Timer &= GPT_CTL_TAEVENT_M | GPT_CTL_TBEVENT_M; - HWREG(ui32Base + GPT_O_CTL) = ((HWREG(ui32Base + GPT_O_CTL) & ~ui32Timer) | - (ui32Event & ui32Timer)); -} - -//***************************************************************************** -// -//! \brief Controls the stall handling. -//! -//! This function controls the stall response for the specified timer. If the -//! \e bStall parameter is \b true, then the timer stops counting if the -//! processor enters debug mode; otherwise the timer keeps running while in -//! debug mode. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param bStall specifies the response to a stall signal. -//! - \c true : Timer stops counting if the processor enters debug mode. -//! - \c false : Timer keeps running if the processor enters debug mode. -//! -//! \return None -// -//***************************************************************************** -extern void TimerStallControl(uint32_t ui32Base, uint32_t ui32Timer, - bool bStall); - -//***************************************************************************** -// -//! \brief Controls the wait on trigger handling. -//! -//! This function controls whether or not a timer waits for a trigger input to -//! start counting. When enabled, the previous timer in the trigger chain must -//! count to its timeout in order for this timer to start counting. Refer to -//! the part's data sheet for a description of the trigger chain. -//! -//! \note This function should not be used for Timer 0A or Wide Timer 0A. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to be adjusted; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param bWait specifies if the timer should wait for a trigger input. -//! - \c true : Wait for trigger. -//! - \c false : Do not wait for trigger. -//! -//! \return None -// -//***************************************************************************** -extern void TimerWaitOnTriggerControl(uint32_t ui32Base, uint32_t ui32Timer, - bool bWait); - -//***************************************************************************** -// -//! \brief Set the timer prescale value. -//! -//! This function configures the value of the timer clock prescaler. The -//! prescaler is only operational when in half-width mode and is used to extend -//! the range of the half-width timer modes. -//! -//! When in one-shot or periodic down count modes, \b ui32Value defines the -//! prescaler for the timer counter. When acting as a true prescaler, the -//! prescaler counts down to 0 before the value in timer registers are incremented. -//! -//! In all other individual/split modes, \b ui32Value is a linear extension of -//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes -//! of the 16/32-bit timer. -//! -//! \note Because the prescaler counts down to 0 the timer division ratio equals -//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Value is the timer prescale value which must be between 0 and 255 -//! (both included). -//! - 0 : Timer division ratio = 1 (disable prescaling). -//! - 1 : Timer division ratio = 2. -//! - ... -//! - 255 : Timer division ratio = 256. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerPrescaleSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - ASSERT(ui32Value < 256); - - // Set the timer A prescaler if requested. - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + GPT_O_TAPR) = ui32Value; - } - - // Set the timer B prescaler if requested. - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + GPT_O_TBPR) = ui32Value; - } -} - -//***************************************************************************** -// -//! \brief Get the timer prescale value. -//! -//! This function gets the value of the timer clock prescaler. The -//! prescaler is only operational when in half-width mode and is used to extend -//! the range of the half-width timer modes. -//! -//! When in one-shot or periodic down count modes, \b ui32Value defines the -//! prescaler for the timer counter. When acting as a true prescaler, the -//! prescaler counts down to 0 before the value in timer registers are incremented. -//! -//! In all other individual/split modes, \b ui32Value is a linear extension of -//! the upper range of the timer counter, holding bits 23:16 in the 16-bit modes -//! of the 16/32-bit timer. -//! -//! \note Because the prescaler counts down to 0 the timer division ratio equals -//! \b ui32Value + 1. E.g. a prescale value of 15 divides the timer rate by 16. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! -//! \return Returns the value of the timer prescaler. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TimerPrescaleGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Return the appropriate prescale value. - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPR) : - HWREG(ui32Base + GPT_O_TBPR)); -} - -//***************************************************************************** -// -//! \brief Set the timer prescale match value. -//! -//! This function configures the value of the input clock prescaler match -//! value. When in a half-width mode that uses the counter match and the -//! prescaler, the prescale match effectively extends the range of the match. -//! The prescaler provides the least significant bits when counting down in -//! periodic and one-shot modes; in all other modes, the prescaler provides the -//! most significant bits. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Value is the timer prescale match value which must be between 0 -//! and 255 (both included). -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerPrescaleMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - ASSERT(ui32Value < 256); - - // Set the timer A prescale match if requested. - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + GPT_O_TAPMR) = ui32Value; - } - - // Set the timer B prescale match if requested. - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + GPT_O_TBPMR) = ui32Value; - } -} - -//***************************************************************************** -// -//! \brief Get the timer prescale match value. -//! -//! This function gets the value of the input clock prescaler match value. -//! When in a half-width mode that uses the counter match and prescaler, the -//! prescale match effectively extends the range of the match. The prescaler -//! provides the least significant bits when counting down in periodic and -//! one-shot modes; in all other modes, the prescaler provides the most -//! significant bits. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! -//! \return Returns the value of the timer prescale match. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TimerPrescaleMatchGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // Return the appropriate prescale match value. - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAPMR) : - HWREG(ui32Base + GPT_O_TBPMR)); -} - -//***************************************************************************** -// -//! \brief Sets the timer load value. -//! -//! This function configures the timer load value; if the timer is running then -//! the value is immediately loaded into the timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \note Only \ref TIMER_A should be used when the timer is configured for -//! full-width operation. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Value is the load value. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerLoadSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Set the timer A load value if requested. - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + GPT_O_TAILR) = ui32Value; - } - - // Set the timer B load value if requested. - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + GPT_O_TBILR) = ui32Value; - } -} - -//***************************************************************************** -// -//! \brief Gets the timer load value. -//! -//! This function gets the currently programmed interval load value for the -//! specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \note Only \ref TIMER_A should be used when the timer is configured for -//! full-width operation. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! -//! \return Returns the load value for the timer -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TimerLoadGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // Return the appropriate load value. - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAILR) : - HWREG(ui32Base + GPT_O_TBILR)); -} - -//***************************************************************************** -// -//! \brief Gets the current timer value. -//! -//! This function reads the current value of the specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \note Only \ref TIMER_A should be used when the timer is configured for -//! full-width operation. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! -//! \return Returns the current value of the timer. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TimerValueGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // Return the appropriate timer value. - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAR) : - HWREG(ui32Base + GPT_O_TBR)); -} - -//***************************************************************************** -// -//! \brief Sets the timer match value. -//! -//! This function configures the match value for a timer. This value is used -//! in capture count mode to determine when to interrupt the processor and in -//! PWM mode to determine the duty cycle of the output signal. Match interrupts -//! can also be generated in periodic and one-shot modes when the value of the -//! counter matches this register. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \note Only \ref TIMER_A should be used when the timer is configured for -//! full-width operation. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to adjust; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Value is the match value. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerMatchSet(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Value) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B) || - (ui32Timer == TIMER_BOTH)); - - // Set the timer A match value if requested. - if(ui32Timer & TIMER_A) - { - HWREG(ui32Base + GPT_O_TAMATCHR) = ui32Value; - } - - // Set the timer B match value if requested. - if(ui32Timer & TIMER_B) - { - HWREG(ui32Base + GPT_O_TBMATCHR) = ui32Value; - } -} - -//***************************************************************************** -// -//! \brief Gets the timer match value. -//! -//! This function gets the match value for the specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \note Only \ref TIMER_A should be used when the timer is configured for -//! full-width operation. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! -//! \return Returns the match value for the timer -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TimerMatchGet(uint32_t ui32Base, uint32_t ui32Timer) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - ASSERT((ui32Timer == TIMER_A) || (ui32Timer == TIMER_B)); - - // Return the appropriate match value. - return((ui32Timer == TIMER_A) ? HWREG(ui32Base + GPT_O_TAMATCHR) : - HWREG(ui32Base + GPT_O_TBMATCHR)); -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for the timer interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific timer interrupts must be enabled via \ref TimerIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source via -//! \ref TimerIntClear(). -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s); must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param pfnHandler is a pointer to the function to be called when the timer -//! interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void TimerIntRegister(uint32_t ui32Base, uint32_t ui32Timer, - void (*pfnHandler)(void)); - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for the timer interrupt in the dynamic interrupt table. -//! -//! This function unregisters the handler to be called when a timer interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler is no longer called. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s); must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void TimerIntUnregister(uint32_t ui32Base, uint32_t ui32Timer); - -//***************************************************************************** -// -//! \brief Enables individual timer interrupt sources. -//! -//! This function enables the indicated timer interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! The parameter must be the bitwise OR of any combination of -//! the following: -//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. -//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. -//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. -//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. -//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. -//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - - // Enable the specified interrupts. - HWREG(ui32Base + GPT_O_IMR) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Disables individual timer interrupt sources. -//! -//! This function disables the indicated timer interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. -//! The parameter must be the bitwise OR of any combination of -//! the following: -//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. -//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. -//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. -//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. -//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. -//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - - // Disable the specified interrupts. - HWREG(ui32Base + GPT_O_IMR) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! \brief Gets the current interrupt status. -//! -//! This function returns the interrupt status for the timer module. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \param ui32Base is the base address of the timer module. -//! \param bMasked selects either raw or masked interrupt status: -//! - \c true : Masked interrupt. -//! - \c false : Raw interrupt. -//! -//! \return The current interrupt status, enumerated as a bit field of values: -//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. -//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. -//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. -//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. -//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. -//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TimerIntStatus(uint32_t ui32Base, bool bMasked) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - - // Return either the interrupt status or the raw interrupt status as - // requested. - return(bMasked ? HWREG(ui32Base + GPT_O_MIS) : - HWREG(ui32Base + GPT_O_RIS)); -} - -//***************************************************************************** -// -//! \brief Clears timer interrupt sources. -//! -//! The specified timer interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! The parameter must be the bitwise OR of any combination of -//! the following: -//! - \ref TIMER_CAPB_EVENT : Capture B event interrupt. -//! - \ref TIMER_CAPB_MATCH : Capture B match interrupt. -//! - \ref TIMER_TIMB_TIMEOUT : Timer B timeout interrupt. -//! - \ref TIMER_CAPA_EVENT : Capture A event interrupt. -//! - \ref TIMER_CAPA_MATCH : Capture A match interrupt. -//! - \ref TIMER_TIMA_TIMEOUT : Timer A timeout interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(TimerBaseValid(ui32Base)); - - // Clear the requested interrupt sources. - HWREG(ui32Base + GPT_O_ICLR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Synchronizes the counters in a set of timers. -//! -//! This function synchronizes the counters in a specified set of timers. -//! When a timer is running in half-width mode, each half can be included or -//! excluded in the synchronization event. When a timer is running in -//! full-width mode, only the A timer can be synchronized (specifying the B -//! timer has no effect). -//! -//! \param ui32Base is the base address of the timer module. This parameter must -//! be the base address of Timer0 (in other words, \b GPT0_BASE). -//! \param ui32Timers is the set of timers to synchronize. -//! The parameter is the bitwise OR of any of the following: -//! - \ref TIMER_0A_SYNC -//! - \ref TIMER_0B_SYNC -//! - \ref TIMER_1A_SYNC -//! - \ref TIMER_1B_SYNC -//! - \ref TIMER_2A_SYNC -//! - \ref TIMER_2B_SYNC -//! - \ref TIMER_3A_SYNC -//! - \ref TIMER_3B_SYNC -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerSynchronize(uint32_t ui32Base, uint32_t ui32Timers) -{ - // Check the arguments. - ASSERT(ui32Base == GPT0_BASE); - - // Synchronize the specified timers. - HWREG(ui32Base + GPT_O_SYNC) = ui32Timers; -} - -//***************************************************************************** -// -//! \brief Enables AND'ing of the CCP outputs from Timer A and Timer B. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerCcpCombineEnable(uint32_t ui32Base) -{ - // Check the arguments - ASSERT(TimerBaseValid(ui32Base)); - - // Set the bit - HWREG(ui32Base + GPT_O_ANDCCP) |= GPT_ANDCCP_CCP_AND_EN; -} - -//***************************************************************************** -// -//! \brief Disables AND'ing of the CCP outputs from Timer A and Timer B. -//! -//! \param ui32Base is the base address of the timer module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TimerCcpCombineDisable(uint32_t ui32Base) -{ - // Check the arguments - ASSERT(TimerBaseValid(ui32Base)); - - // Clear the bit - HWREG(ui32Base + GPT_O_ANDCCP) &= ~(GPT_ANDCCP_CCP_AND_EN); -} - -//***************************************************************************** -// -//! \brief Sets the Match Register Update mode. -//! -//! This function controls when the Match Register value and Prescale Register value -//! are applied after writing these registers while a timer is enabled. -//! -//! \note If the timer is disabled when setting the update mode the Match Register -//! and Prescale Register values are applied immediately when enabling the timer. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to configure; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Mode sets the mode: -//! - \ref TIMER_MATCHUPDATE_NEXTCYCLE : Apply Match Register and Prescale Register on next clock -//! cycle after writing any of these registers. -//! - \ref TIMER_MATCHUPDATE_TIMEOUT : Apply Match Register and Prescale Register on next timeout -//! after writing any of these registers. -//! -//! \return None -// -//***************************************************************************** -extern void TimerMatchUpdateMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode); - -//***************************************************************************** -// -//! \brief Sets the Interval Load mode. -//! -//! This function controls when the Timer Register and Prescale Snap-shot (if used) -//! are updated. -//! -//! Timer Register (TAR/TBR) is updated when Interval Load Register (TAILR/TBILR) is written -//! and the Prescale Snap-shot (TAPS/TBPS) is updated when Prescale Register (TAPR/TBPR) is -//! written depending on the mode of operation. -//! -//! \param ui32Base is the base address of the timer module. -//! \param ui32Timer specifies the timer(s) to configure; must be one of: -//! - \ref TIMER_A -//! - \ref TIMER_B -//! - \ref TIMER_BOTH -//! \param ui32Mode sets the mode: -//! - \ref TIMER_INTERVALLOAD_NEXTCYCLE : Update Timer Register and Prescale Snap-shot on next clock -//! cycle after writing Interval Load Register or Prescale Register, respectively. -//! - \ref TIMER_INTERVALLOAD_TIMEOUT : Update Timer Register and Prescale Snap-shot on next timeout -//! after writing Interval Load Register or Prescale Register, respectively. -//! -//! \return None -// -//***************************************************************************** -extern void TimerIntervalLoadMode(uint32_t ui32Base, uint32_t ui32Timer, uint32_t ui32Mode); - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_TimerConfigure - #undef TimerConfigure - #define TimerConfigure ROM_TimerConfigure - #endif - #ifdef ROM_TimerLevelControl - #undef TimerLevelControl - #define TimerLevelControl ROM_TimerLevelControl - #endif - #ifdef ROM_TimerStallControl - #undef TimerStallControl - #define TimerStallControl ROM_TimerStallControl - #endif - #ifdef ROM_TimerWaitOnTriggerControl - #undef TimerWaitOnTriggerControl - #define TimerWaitOnTriggerControl ROM_TimerWaitOnTriggerControl - #endif - #ifdef ROM_TimerIntRegister - #undef TimerIntRegister - #define TimerIntRegister ROM_TimerIntRegister - #endif - #ifdef ROM_TimerIntUnregister - #undef TimerIntUnregister - #define TimerIntUnregister ROM_TimerIntUnregister - #endif - #ifdef ROM_TimerMatchUpdateMode - #undef TimerMatchUpdateMode - #define TimerMatchUpdateMode ROM_TimerMatchUpdateMode - #endif - #ifdef ROM_TimerIntervalLoadMode - #undef TimerIntervalLoadMode - #define TimerIntervalLoadMode ROM_TimerIntervalLoadMode - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __GPT_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h deleted file mode 100644 index f30779f4b4c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/timer_doc.h +++ /dev/null @@ -1,121 +0,0 @@ -/****************************************************************************** -* Filename: timer_doc.h -* Revised: 2016-03-30 13:03:59 +0200 (Wed, 30 Mar 2016) -* Revision: 45971 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup timer_api -//! @{ -//! \section sec_timer Introduction -//! -//! The timer API provides a set of functions for using the general-purpose timer module. -//! -//! The timer module contains four timer blocks with the following functional options: -//! - Operating modes: -//! - 16-bit with 8-bit prescaler or 32-bit programmable one-shot timer. -//! - 16-bit with 8-bit prescaler or 32-bit programmable periodic timer. -//! - Two capture compare PWM pins (CCP) for each 32-bit timer. -//! - 24-bit input-edge count or 24-bit time-capture modes. -//! - 24-bit PWM mode with software-programmable output inversion of the PWM signal. -//! - Count up or down. -//! - Daisy chaining of timer modules allows a single timer to initiate multiple timing events. -//! - Timer synchronization allows selected timers to start counting on the same clock cycle. -//! - User-enabled stalling when the System CPU asserts a CPU Halt flag during debug. -//! - Ability to determine the elapsed time between the assertion of the timer interrupt and -//! entry into the interrupt service routine. -//! -//! Each timer block provides two half-width timers/counters that can be configured -//! to operate independently as timers or event counters or to operate as a combined -//! full-width timer. -//! The timers provide 16-bit half-width timers and a 32-bit full-width timer. -//! For the purposes of this API, the two -//! half-width timers provided by a timer block are referred to as TimerA and -//! TimerB, and the full-width timer is referred to as TimerA. -//! -//! When in half-width mode, the timer can also be configured for event capture or -//! as a pulse width modulation (PWM) generator. When configured for event -//! capture, the timer acts as a counter. It can be configured to count either the -//! time between events or the events themselves. The type of event -//! being counted can be configured as a positive edge, a negative edge, or both -//! edges. When a timer is configured as a PWM generator, the input signal used to -//! capture events becomes an output signal, and the timer drives an -//! edge-aligned pulse onto that signal. -//! -//! Control is also provided over interrupt sources and events. Interrupts can be -//! generated to indicate that an event has been captured, or that a certain number -//! of events have been captured. Interrupts can also be generated when the timer -//! has counted down to 0 or when the timer matches a certain value. -//! -//! Timer configuration is handled by \ref TimerConfigure(), which performs the high -//! level setup of the timer module; that is, it is used to set up full- or -//! half-width modes, and to select between PWM, capture, and timer operations. -//! -//! \section sec_timer_api API -//! -//! The API functions can be grouped like this: -//! -//! Functions to perform timer control: -//! - \ref TimerConfigure() -//! - \ref TimerEnable() -//! - \ref TimerDisable() -//! - \ref TimerLevelControl() -//! - \ref TimerWaitOnTriggerControl() -//! - \ref TimerEventControl() -//! - \ref TimerStallControl() -//! - \ref TimerIntervalLoadMode() -//! - \ref TimerMatchUpdateMode() -//! - \ref TimerCcpCombineDisable() -//! - \ref TimerCcpCombineEnable() -//! -//! Functions to manage timer content: -//! - \ref TimerLoadSet() -//! - \ref TimerLoadGet() -//! - \ref TimerPrescaleSet() -//! - \ref TimerPrescaleGet() -//! - \ref TimerMatchSet() -//! - \ref TimerMatchGet() -//! - \ref TimerPrescaleMatchSet() -//! - \ref TimerPrescaleMatchGet() -//! - \ref TimerValueGet() -//! - \ref TimerSynchronize() -//! -//! Functions to manage the interrupt handler for the timer interrupt: -//! - \ref TimerIntRegister() -//! - \ref TimerIntUnregister() -//! -//! The individual interrupt sources within the timer module are managed with: -//! - \ref TimerIntEnable() -//! - \ref TimerIntDisable() -//! - \ref TimerIntStatus() -//! - \ref TimerIntClear() -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/trng.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/trng.c deleted file mode 100644 index 751c5cbaa13..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/trng.c +++ /dev/null @@ -1,112 +0,0 @@ -/****************************************************************************** -* Filename: trng.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for the TRNG module -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "trng.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef TRNGConfigure - #define TRNGConfigure NOROM_TRNGConfigure - #undef TRNGNumberGet - #define TRNGNumberGet NOROM_TRNGNumberGet -#endif - -//***************************************************************************** -// -// Configure the true random number generator -// -//***************************************************************************** -void -TRNGConfigure(uint32_t ui32MinSamplesPerCycle, - uint32_t ui32MaxSamplesPerCycle, - uint32_t ui32ClocksPerSample) -{ - uint32_t ui32Val; - - // Make sure the TRNG is disabled. - ui32Val = HWREG(TRNG_BASE + TRNG_O_CTL) & ~TRNG_CTL_TRNG_EN; - HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; - - // Configure the startup number of samples. - ui32Val &= ~TRNG_CTL_STARTUP_CYCLES_M; - ui32Val |= ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CTL_STARTUP_CYCLES_S ) & TRNG_CTL_STARTUP_CYCLES_M ); - HWREG(TRNG_BASE + TRNG_O_CTL) = ui32Val; - - // Configure the minimum and maximum number of samples pr generated number - // and the number of clocks per sample. - HWREG(TRNG_BASE + TRNG_O_CFG0) = ( - ((( ui32MaxSamplesPerCycle >> 8 ) << TRNG_CFG0_MAX_REFILL_CYCLES_S ) & TRNG_CFG0_MAX_REFILL_CYCLES_M ) | - ((( ui32ClocksPerSample ) << TRNG_CFG0_SMPL_DIV_S ) & TRNG_CFG0_SMPL_DIV_M ) | - ((( ui32MinSamplesPerCycle >> 6 ) << TRNG_CFG0_MIN_REFILL_CYCLES_S ) & TRNG_CFG0_MIN_REFILL_CYCLES_M ) ); -} - -//***************************************************************************** -// -// Get a random number from the generator -// -//***************************************************************************** -uint32_t -TRNGNumberGet(uint32_t ui32Word) -{ - uint32_t ui32RandomNumber; - - // Check the arguments. - ASSERT((ui32Word == TRNG_HI_WORD) || - (ui32Word == TRNG_LOW_WORD)); - - // Return the right requested part of the generated number. - if(ui32Word == TRNG_HI_WORD) - { - ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT1); - } - else - { - ui32RandomNumber = HWREG(TRNG_BASE + TRNG_O_OUT0); - } - - // Initiate generation of new number. - HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = 0x1; - - // Return the random number. - return ui32RandomNumber; -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h deleted file mode 100644 index 2a2f047cd71..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/trng.h +++ /dev/null @@ -1,451 +0,0 @@ -/****************************************************************************** -* Filename: trng.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the true random number gen. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup trng_api -//! @{ -// -//***************************************************************************** - -#ifndef __TRNG_H__ -#define __TRNG_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_trng.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "debug.h" -#include "interrupt.h" -#include "cpu.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define TRNGConfigure NOROM_TRNGConfigure - #define TRNGNumberGet NOROM_TRNGNumberGet -#endif - -//***************************************************************************** -// -// -// -//***************************************************************************** -#define TRNG_NUMBER_READY 0x00000001 // -#define TRNG_FRO_SHUTDOWN 0x00000002 // -#define TRNG_NEED_CLOCK 0x80000000 // - -#define TRNG_HI_WORD 0x00000001 -#define TRNG_LOW_WORD 0x00000002 - -//***************************************************************************** -// -// API Function and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Configure the true random number generator. -//! -//! Use this function to set the minimum and maximum number of samples required -//! in each generation of a new random number. -//! -//! \param ui32MinSamplesPerCycle is the minimum number of samples per each -//! generated random number. Constraints: -//! - Value must be bigger than or equal to 2^6 and less than 2^14. -//! - The 6 LSBs of the argument are truncated. -//! - If the value is zero, the number of samples is fixed to the value determined -//! by ui32MaxSamplesPerCycle. To ensure same entropy in all generated random -//! numbers the value 0 should be used. -//! \param ui32MaxSamplesPerCycle is the maximum number of samples per each -//! generated random number. Constraints: -//! - Value must be between 2^8 and 2^24 (both included). -//! - The 8 LSBs of the argument are truncated. -//! - Value 0 and 2^24 both give the highest possible value. -//! \param ui32ClocksPerSample is the number of clock cycles for each time -//! a new sample is generated from the FROs. -//! - 0 : Every sample. -//! - 1 : Every second sample. -//! - ... -//! - 15 : Every 16. sample. -//! -//! \return None -// -//***************************************************************************** -extern void TRNGConfigure(uint32_t ui32MinSamplesPerCycle, - uint32_t ui32MaxSamplesPerCycle, - uint32_t ui32ClocksPerSample); - -//***************************************************************************** -// -//! \brief Enable the TRNG. -//! -//! Enable the TRNG to start preparing a random number. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TRNGEnable(void) -{ - // Enable the TRNG. - HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Disable the TRNG module. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TRNGDisable(void) -{ - // Enable the TRNG - HWREGBITW(TRNG_BASE + TRNG_O_CTL, TRNG_CTL_TRNG_EN_BITN) = 0; -} - -//***************************************************************************** -// -//! \brief Get a random number from the generator. -//! -//! Use this function to get either the high or low part of the 64 bit -//! generated number. -//! -//! \note Data from this register is only valid if the TRNG has produced a -//! number. Use \ref TRNGStatusGet() to poll the for status. After calling this -//! function a new random number will be generated. -//! -//! \param ui32Word determines if whether to return the high or low 32 bits. -//! - \ref TRNG_HI_WORD -//! - \ref TRNG_LOW_WORD -//! -//! \return Return either the high or low part of the 64 bit generated random -//! number. -// -//***************************************************************************** -extern uint32_t TRNGNumberGet(uint32_t ui32Word); - -//***************************************************************************** -// -//! \brief Get the status of the TRNG. -//! -//! Use this function to retrieve the status of the TRNG. -//! -//! \return Returns the current status of the TRNG module. -//! The returned status is a bitwise OR'ed combination of: -//! - \ref TRNG_NUMBER_READY -//! - \ref TRNG_FRO_SHUTDOWN -//! - \ref TRNG_NEED_CLOCK -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TRNGStatusGet(void) -{ - // Return the status. - return (HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); -} - -//***************************************************************************** -// -//! \brief Reset the TRNG. -//! -//! Use this function to reset the TRNG module. Reset will be low for -//! approximately 5 clock cycles. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TRNGReset(void) -{ - // Reset the TRNG. - HWREG(TRNG_BASE + TRNG_O_SWRESET) = 1; -} - -//***************************************************************************** -// -//! \brief Enables individual TRNG interrupt sources. -//! -//! This function enables the indicated TRNG interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! The parameter is the bitwise OR of any of the following: -//! - \ref TRNG_NUMBER_READY -//! - \ref TRNG_FRO_SHUTDOWN -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TRNGIntEnable(uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || - (ui32IntFlags & TRNG_FRO_SHUTDOWN)); - - // Enable the specified interrupts. - HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Disables individual TRNG interrupt sources. -//! -//! This function disables the indicated TRNG interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. -//! The parameter is the bitwise OR of any of the following: -//! - \ref TRNG_NUMBER_READY -//! - \ref TRNG_FRO_SHUTDOWN -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TRNGIntDisable(uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || - (ui32IntFlags & TRNG_FRO_SHUTDOWN)); - - // Disable the specified interrupts. - HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Gets the current interrupt status of the TRNG module. -//! -//! This function returns the interrupt status for the specified TRNG. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \param bMasked selects either raw or masked interrupt status. -//! - \c true : Masked interrupt. -//! - \c false : Raw interrupt. -//! -//! \return Returns the current interrupt status, enumerated as: -//! - \ref TRNG_NUMBER_READY -//! - \ref TRNG_FRO_SHUTDOWN -// -//***************************************************************************** -__STATIC_INLINE uint32_t -TRNGIntStatus(bool bMasked) -{ - uint32_t ui32Mask; - - // Return either the interrupt status or the raw interrupt status as - // requested. - if(bMasked) - { - ui32Mask = HWREG(TRNG_BASE + TRNG_O_IRQFLAGMASK); - return(ui32Mask & HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT)); - } - else - { - return(HWREG(TRNG_BASE + TRNG_O_IRQFLAGSTAT) & 0x00000003); - } -} - -//***************************************************************************** -// -//! \brief Clears TRNG interrupt sources. -//! -//! The specified TRNG interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! The parameter is the bitwise OR of any of the following: -//! - \ref TRNG_NUMBER_READY -//! - \ref TRNG_FRO_SHUTDOWN -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -TRNGIntClear(uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT((ui32IntFlags & TRNG_NUMBER_READY) || - (ui32IntFlags & TRNG_FRO_SHUTDOWN)); - - // Clear the requested interrupt sources. - HWREG(TRNG_BASE + TRNG_O_IRQFLAGCLR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for a TRNG interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific TRNG interrupts must be enabled via \ref TRNGIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! TRNG interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -TRNGIntRegister(void (*pfnHandler)(void)) -{ - // Register the interrupt handler. - IntRegister(INT_TRNG_IRQ, pfnHandler); - - // Enable the TRNG interrupt. - IntEnable(INT_TRNG_IRQ); -} - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for a TRNG interrupt in the dynamic interrupt table. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a Crypto interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -TRNGIntUnregister(void) -{ - // Disable the interrupt. - IntDisable(INT_TRNG_IRQ); - - // Unregister the interrupt handler. - IntUnregister(INT_TRNG_IRQ); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_TRNGConfigure - #undef TRNGConfigure - #define TRNGConfigure ROM_TRNGConfigure - #endif - #ifdef ROM_TRNGNumberGet - #undef TRNGNumberGet - #define TRNGNumberGet ROM_TRNGNumberGet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __TRNG_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart.c deleted file mode 100644 index d9f493ba1ff..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart.c +++ /dev/null @@ -1,304 +0,0 @@ -/****************************************************************************** -* Filename: uart.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the UART. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "uart.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef UARTFIFOLevelGet - #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet - #undef UARTConfigSetExpClk - #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk - #undef UARTConfigGetExpClk - #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk - #undef UARTDisable - #define UARTDisable NOROM_UARTDisable - #undef UARTCharGetNonBlocking - #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking - #undef UARTCharGet - #define UARTCharGet NOROM_UARTCharGet - #undef UARTCharPutNonBlocking - #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking - #undef UARTCharPut - #define UARTCharPut NOROM_UARTCharPut - #undef UARTIntRegister - #define UARTIntRegister NOROM_UARTIntRegister - #undef UARTIntUnregister - #define UARTIntUnregister NOROM_UARTIntUnregister -#endif - -//***************************************************************************** -// -// Gets the FIFO level at which interrupts are generated -// -//***************************************************************************** -void -UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, - uint32_t *pui32RxLevel) -{ - uint32_t ui32Temp; - - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Read the FIFO level register. - ui32Temp = HWREG(ui32Base + UART_O_IFLS); - - // Extract the transmit and receive FIFO levels. - *pui32TxLevel = ui32Temp & UART_IFLS_TXSEL_M; - *pui32RxLevel = ui32Temp & UART_IFLS_RXSEL_M; -} - -//***************************************************************************** -// -// Sets the configuration of a UART -// -//***************************************************************************** -void -UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t ui32Baud, uint32_t ui32Config) -{ - uint32_t ui32Div; - - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - ASSERT(ui32Baud != 0); - - // Stop the UART. - UARTDisable(ui32Base); - - // Compute the fractional baud rate divider. - ui32Div = (((ui32UARTClk * 8) / ui32Baud) + 1) / 2; - - // Set the baud rate. - HWREG(ui32Base + UART_O_IBRD) = ui32Div / 64; - HWREG(ui32Base + UART_O_FBRD) = ui32Div % 64; - - // Set parity, data length, and number of stop bits. - HWREG(ui32Base + UART_O_LCRH) = ui32Config; -} - -//***************************************************************************** -// -// Gets the current configuration of a UART -// -//***************************************************************************** -void -UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t *pui32Baud, uint32_t *pui32Config) -{ - uint32_t ui32Int, ui32Frac; - - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Compute the baud rate. - ui32Int = HWREG(ui32Base + UART_O_IBRD); - ui32Frac = HWREG(ui32Base + UART_O_FBRD); - *pui32Baud = (ui32UARTClk * 4) / ((64 * ui32Int) + ui32Frac); - - // Get the parity, data length, and number of stop bits. - *pui32Config = (HWREG(ui32Base + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | - UART_LCRH_EPS | UART_LCRH_PEN)); -} - -//***************************************************************************** -// -// Disables transmitting and receiving -// -//***************************************************************************** -void -UARTDisable(uint32_t ui32Base) -{ - - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Wait for end of TX. - while(HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) - { - } - - // Disable the FIFO. - HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); - - // Disable the UART. - HWREG(ui32Base + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} - -//***************************************************************************** -// -// Receives a character from the specified port -// -//***************************************************************************** -int32_t -UARTCharGetNonBlocking(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // See if there are any characters in the receive FIFO. - if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE)) - { - // Read and return the next character. - return(HWREG(ui32Base + UART_O_DR)); - } - else - { - // There are no characters, so return a failure. - return(-1); - } -} - -//***************************************************************************** -// -// Waits for a character from the specified port -// -//***************************************************************************** -int32_t -UARTCharGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Wait until a char is available. - while(HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) - { - } - - // Now get the character. - return(HWREG(ui32Base + UART_O_DR)); -} - -//***************************************************************************** -// -// Sends a character to the specified port -// -//***************************************************************************** -bool -UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // See if there is space in the transmit FIFO. - if(!(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF)) - { - // Write this character to the transmit FIFO. - HWREG(ui32Base + UART_O_DR) = ui8Data; - - // Success. - return(true); - } - else - { - // There is no space in the transmit FIFO, so return a failure. - return(false); - } -} - -//***************************************************************************** -// -// Waits to send a character from the specified port -// -//***************************************************************************** -void -UARTCharPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Wait until space is available. - while(HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) - { - } - - // Send the char. - HWREG(ui32Base + UART_O_DR) = ui8Data; -} - -//***************************************************************************** -// -// Registers an interrupt handler for a UART interrupt -// -//***************************************************************************** -void -UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Register and enable the interrupt handler. - // (Doing the '& 0xFFFF' to catch both buffered and unbufferd offsets) - if (( ui32Base & 0xFFFF ) == ( UART0_BASE & 0xFFFF )) { - IntRegister(INT_UART0_COMB, pfnHandler); - IntEnable(INT_UART0_COMB); - } else { - IntRegister(INT_UART1_COMB, pfnHandler); - IntEnable(INT_UART1_COMB); - } -} - -//***************************************************************************** -// -// Unregisters an interrupt handler for a UART interrupt -// -//***************************************************************************** -void -UARTIntUnregister(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Disable and unregister the interrupt. - // (Doing the '& 0xFFFF' to catch both buffered and unbufferd offsets) - if (( ui32Base & 0xFFFF ) == ( UART0_BASE & 0xFFFF )) { - IntDisable(INT_UART0_COMB); - IntUnregister(INT_UART0_COMB); - } else { - IntDisable(INT_UART1_COMB); - IntUnregister(INT_UART1_COMB); - } -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h deleted file mode 100644 index 82ec13022b4..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart.h +++ /dev/null @@ -1,1097 +0,0 @@ -/****************************************************************************** -* Filename: uart.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Defines and prototypes for the UART. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup uart_api -//! @{ -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_uart.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_ints.h" -#include "interrupt.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define UARTFIFOLevelGet NOROM_UARTFIFOLevelGet - #define UARTConfigSetExpClk NOROM_UARTConfigSetExpClk - #define UARTConfigGetExpClk NOROM_UARTConfigGetExpClk - #define UARTDisable NOROM_UARTDisable - #define UARTCharGetNonBlocking NOROM_UARTCharGetNonBlocking - #define UARTCharGet NOROM_UARTCharGet - #define UARTCharPutNonBlocking NOROM_UARTCharPutNonBlocking - #define UARTCharPut NOROM_UARTCharPut - #define UARTIntRegister NOROM_UARTIntRegister - #define UARTIntUnregister NOROM_UARTIntUnregister -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ui32IntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_EOT ( UART_IMSC_EOTIM ) // End Of Transmission Interrupt Mask -#define UART_INT_OE ( UART_IMSC_OEIM ) // Overrun Error Interrupt Mask -#define UART_INT_BE ( UART_IMSC_BEIM ) // Break Error Interrupt Mask -#define UART_INT_PE ( UART_IMSC_PEIM ) // Parity Error Interrupt Mask -#define UART_INT_FE ( UART_IMSC_FEIM ) // Framing Error Interrupt Mask -#define UART_INT_RT ( UART_IMSC_RTIM ) // Receive Timeout Interrupt Mask -#define UART_INT_TX ( UART_IMSC_TXIM ) // Transmit Interrupt Mask -#define UART_INT_RX ( UART_IMSC_RXIM ) // Receive Interrupt Mask -#define UART_INT_CTS ( UART_IMSC_CTSMIM ) // CTS Modem Interrupt Mask - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSetExpClk as the ui32Config parameter -// and returned by UARTConfigGetExpClk in the pui32Config parameter. -// Additionally, the UART_CONFIG_PAR_* subset can be passed to -// UARTParityModeSet as the ui32Parity parameter, and are returned by -// UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero - -//***************************************************************************** -// -// Values that can be passed to UARTFIFOLevelSet as the ui32TxLevel parameter -// and returned by UARTFIFOLevelGet in the pui32TxLevel. -// -//***************************************************************************** -#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full -#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full -#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full -#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full -#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full - -//***************************************************************************** -// -// Values that can be passed to UARTFIFOLevelSet as the ui32RxLevel parameter -// and returned by UARTFIFOLevelGet in the pui32RxLevel. -// -//***************************************************************************** -#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full -#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full -#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full -#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full -#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full - -//***************************************************************************** -// -// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). -// -//***************************************************************************** -#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error -#define UART_DMA_TX 0x00000002 // Enable DMA for transmit -#define UART_DMA_RX 0x00000001 // Enable DMA for receive - -//***************************************************************************** -// -// Values returned from UARTRxErrorGet(). -// -//***************************************************************************** -#define UART_RXERROR_OVERRUN 0x00000008 -#define UART_RXERROR_BREAK 0x00000004 -#define UART_RXERROR_PARITY 0x00000002 -#define UART_RXERROR_FRAMING 0x00000001 - -//***************************************************************************** -// -// Values returned from the UARTBusy(). -// -//***************************************************************************** -#define UART_BUSY 0x00000001 -#define UART_IDLE 0x00000000 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! -//! \brief Checks a UART base address. -//! -//! This function determines if a UART port base address is valid. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -UARTBaseValid(uint32_t ui32Base) -{ - return(( ui32Base == UART0_BASE ) || ( ui32Base == UART0_NONBUF_BASE ) || - ( ui32Base == UART1_BASE ) || ( ui32Base == UART1_NONBUF_BASE ) ); -} -#endif - -//***************************************************************************** -// -//! \brief Sets the type of parity. -//! -//! This function sets the type of parity to use for transmitting and expect -//! when receiving. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32Parity specifies the type of parity to use. The last two allow -//! direct control of the parity bit; it is always either one or zero based on -//! the mode. -//! - \ref UART_CONFIG_PAR_NONE -//! - \ref UART_CONFIG_PAR_EVEN -//! - \ref UART_CONFIG_PAR_ODD -//! - \ref UART_CONFIG_PAR_ONE -//! - \ref UART_CONFIG_PAR_ZERO -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTParityModeSet(uint32_t ui32Base, uint32_t ui32Parity) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - ASSERT((ui32Parity == UART_CONFIG_PAR_NONE) || - (ui32Parity == UART_CONFIG_PAR_EVEN) || - (ui32Parity == UART_CONFIG_PAR_ODD) || - (ui32Parity == UART_CONFIG_PAR_ONE) || - (ui32Parity == UART_CONFIG_PAR_ZERO)); - - // Set the parity mode. - HWREG(ui32Base + UART_O_LCRH) = ((HWREG(ui32Base + UART_O_LCRH) & - ~(UART_LCRH_SPS | UART_LCRH_EPS | - UART_LCRH_PEN)) | ui32Parity); -} - -//***************************************************************************** -// -//! \brief Gets the type of parity currently being used. -//! -//! This function gets the type of parity used for transmitting data and -//! expected when receiving data. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns the current parity settings, specified as one of: -//! - \ref UART_CONFIG_PAR_NONE -//! - \ref UART_CONFIG_PAR_EVEN -//! - \ref UART_CONFIG_PAR_ODD -//! - \ref UART_CONFIG_PAR_ONE -//! - \ref UART_CONFIG_PAR_ZERO -// -//***************************************************************************** -__STATIC_INLINE uint32_t -UARTParityModeGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Return the current parity setting - return(HWREG(ui32Base + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); -} - -//***************************************************************************** -// -//! \brief Sets the FIFO level at which interrupts are generated. -//! -//! This function sets the FIFO level at which transmit and receive interrupts -//! are generated. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32TxLevel is the transmit FIFO interrupt level, specified as one of: -//! - \ref UART_FIFO_TX1_8 -//! - \ref UART_FIFO_TX2_8 -//! - \ref UART_FIFO_TX4_8 -//! - \ref UART_FIFO_TX6_8 -//! - \ref UART_FIFO_TX7_8 -//! \param ui32RxLevel is the receive FIFO interrupt level, specified as one of: -//! - \ref UART_FIFO_RX1_8 -//! - \ref UART_FIFO_RX2_8 -//! - \ref UART_FIFO_RX4_8 -//! - \ref UART_FIFO_RX6_8 -//! - \ref UART_FIFO_RX7_8 -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTFIFOLevelSet(uint32_t ui32Base, uint32_t ui32TxLevel, - uint32_t ui32RxLevel) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - ASSERT((ui32TxLevel == UART_FIFO_TX1_8) || - (ui32TxLevel == UART_FIFO_TX2_8) || - (ui32TxLevel == UART_FIFO_TX4_8) || - (ui32TxLevel == UART_FIFO_TX6_8) || - (ui32TxLevel == UART_FIFO_TX7_8)); - ASSERT((ui32RxLevel == UART_FIFO_RX1_8) || - (ui32RxLevel == UART_FIFO_RX2_8) || - (ui32RxLevel == UART_FIFO_RX4_8) || - (ui32RxLevel == UART_FIFO_RX6_8) || - (ui32RxLevel == UART_FIFO_RX7_8)); - - // Set the FIFO interrupt levels. - HWREG(ui32Base + UART_O_IFLS) = ui32TxLevel | ui32RxLevel; -} - -//***************************************************************************** -// -//! \brief Gets the FIFO level at which interrupts are generated. -//! -//! This function gets the FIFO level at which transmit and receive interrupts -//! are generated. -//! -//! \param ui32Base is the base address of the UART port. -//! \param pui32TxLevel is a pointer to storage for the transmit FIFO level, -//! returned as one of: -//! - \ref UART_FIFO_TX1_8 -//! - \ref UART_FIFO_TX2_8 -//! - \ref UART_FIFO_TX4_8 -//! - \ref UART_FIFO_TX6_8 -//! - \ref UART_FIFO_TX7_8 -//! \param pui32RxLevel is a pointer to storage for the receive FIFO level, -//! returned as one of: -//! - \ref UART_FIFO_RX1_8 -//! - \ref UART_FIFO_RX2_8 -//! - \ref UART_FIFO_RX4_8 -//! - \ref UART_FIFO_RX6_8 -//! - \ref UART_FIFO_RX7_8 -//! -//! \return None -// -//***************************************************************************** -extern void UARTFIFOLevelGet(uint32_t ui32Base, uint32_t *pui32TxLevel, - uint32_t *pui32RxLevel); - -//***************************************************************************** -// -//! \brief Sets the configuration of a UART. -//! -//! This function configures the UART for operation in the specified data -//! format. -//! -//! \note The peripheral clock is not necessarily the same as the processor -//! clock. The frequency of the peripheral clock is set by the system control. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32UARTClk is the rate of the clock supplied to the UART module. -//! \param ui32Baud is the desired baud rate. -//! - Minimum baud rate: ui32Baud >= ceil(ui32UARTClk / 1,048,559.875) -//! - Maximum baud rate: ui32Baud <= floor(ui32UARTClk / 15.875) -//! \param ui32Config is the data format for the port. -//! The parameter is the bitwise OR of three values: -//! - Number of data bits -//! - \ref UART_CONFIG_WLEN_8 : 8 data bits per byte. -//! - \ref UART_CONFIG_WLEN_7 : 7 data bits per byte. -//! - \ref UART_CONFIG_WLEN_6 : 6 data bits per byte. -//! - \ref UART_CONFIG_WLEN_5 : 5 data bits per byte. -//! - Number of stop bits -//! - \ref UART_CONFIG_STOP_ONE : One stop bit. -//! - \ref UART_CONFIG_STOP_TWO : Two stop bits. -//! - Parity -//! - \ref UART_CONFIG_PAR_NONE -//! - \ref UART_CONFIG_PAR_EVEN -//! - \ref UART_CONFIG_PAR_ODD -//! - \ref UART_CONFIG_PAR_ONE -//! - \ref UART_CONFIG_PAR_ZERO -//! -//! \return None -// -//***************************************************************************** -extern void UARTConfigSetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t ui32Baud, uint32_t ui32Config); - -//***************************************************************************** -// -//! \brief Gets the current configuration of a UART. -//! -//! The baud rate and data format for the UART is determined, given an -//! explicitly provided peripheral clock (hence the ExpClk suffix). The -//! returned baud rate is the actual baud rate; it may not be the exact baud -//! rate requested or an "official" baud rate. The data format returned in -//! \c pui32Config is enumerated the same as the \c ui32Config parameter of -//! \ref UARTConfigSetExpClk(). -//! -//! \note The peripheral clock is not necessarily the same as the processor -//! clock. The frequency of the peripheral clock is set by the system control. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32UARTClk is the rate of the clock supplied to the UART module. -//! \param pui32Baud is a pointer to storage for the baud rate. -//! \param pui32Config is a pointer to storage for the data format. -//! -//! \return None -// -//***************************************************************************** -extern void UARTConfigGetExpClk(uint32_t ui32Base, uint32_t ui32UARTClk, - uint32_t *pui32Baud, uint32_t *pui32Config); - -//***************************************************************************** -// -//! \brief Enables transmitting and receiving. -//! -//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit -//! and receive FIFOs. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Enable the FIFO. - HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; - - // Enable RX, TX, and the UART. - HWREG(ui32Base + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} - -//***************************************************************************** -// -//! \brief Disables transmitting and receiving. -//! -//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of -//! transmission of the current character, and flushes the transmit FIFO. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -extern void UARTDisable(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Enables the transmit and receive FIFOs. -//! -//! This functions enables the transmit and receive FIFOs in the UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTFIFOEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Enable the FIFO. - HWREG(ui32Base + UART_O_LCRH) |= UART_LCRH_FEN; -} - -//***************************************************************************** -// -//! \brief Disables the transmit and receive FIFOs. -//! -//! This functions disables the transmit and receive FIFOs in the UART. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTFIFODisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Disable the FIFO. - HWREG(ui32Base + UART_O_LCRH) &= ~(UART_LCRH_FEN); -} - -//***************************************************************************** -// -//! \brief Determines if there are any characters in the receive FIFO. -//! -//! This function returns a flag indicating whether or not there is data -//! available in the receive FIFO. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns status of the receive FIFO. -//! - \c true : There is data in the receive FIFO. -//! - \c false : There is no data in the receive FIFO. -// -//***************************************************************************** -__STATIC_INLINE bool -UARTCharsAvail(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Return the availability of characters. - return((HWREG(ui32Base + UART_O_FR) & UART_FR_RXFE) ? false : true); -} - -//***************************************************************************** -// -//! \brief Determines if there is any space in the transmit FIFO. -//! -//! This function returns a flag indicating whether or not there is space -//! available in the transmit FIFO. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns status of the transmit FIFO. -//! - \c true : There is space available in the transmit FIFO. -//! - \c false : There is no space available in the transmit FIFO. -// -//***************************************************************************** -__STATIC_INLINE bool -UARTSpaceAvail(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Return the availability of space. - return((HWREG(ui32Base + UART_O_FR) & UART_FR_TXFF) ? false : true); -} - -//***************************************************************************** -// -//! \brief Receives a character from the specified port. -//! -//! This function gets a character from the receive FIFO for the specified -//! port. -//! -//! \note The \ref UARTCharsAvail() function should be called before -//! attempting to call this function. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns the character read from the specified port, cast as an -//! \c int32_t. A \c -1 is returned if there are no characters present in the -//! receive FIFO. -//! -//! \sa \ref UARTCharsAvail() -// -//***************************************************************************** -extern int32_t UARTCharGetNonBlocking(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Waits for a character from the specified port. -//! -//! This function gets a character from the receive FIFO for the specified -//! port. If there are no characters available, this function waits until a -//! character is received before returning. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns the character read from the specified port, cast as an -//! \c int32_t. -// -//***************************************************************************** -extern int32_t UARTCharGet(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Sends a character to the specified port. -//! -//! This function writes the character \c ui8Data to the transmit FIFO for the -//! specified port. This function does not block, so if there is no space -//! available, then a \c false is returned, and the application must retry the -//! function later. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui8Data is the character to be transmitted. -//! -//! \return Returns status of the character transmit. -//! - \c true : The character was successfully placed in the transmit FIFO. -//! - \c false : There was no space available in the transmit FIFO. Try again later. -// -//***************************************************************************** -extern bool UARTCharPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data); - -//***************************************************************************** -// -//! \brief Waits to send a character from the specified port. -//! -//! This function sends the character \c ui8Data to the transmit FIFO for the -//! specified port. If there is no space available in the transmit FIFO, this -//! function waits until there is space available before returning. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui8Data is the character to be transmitted. -//! -//! \return None -// -//***************************************************************************** -extern void UARTCharPut(uint32_t ui32Base, uint8_t ui8Data); - -//***************************************************************************** -// -//! \brief Determines whether the UART transmitter is busy or not. -//! -//! Allows the caller to determine whether all transmitted bytes have cleared -//! the transmitter hardware. If \c false is returned, the transmit FIFO is -//! empty and all bits of the last transmitted character, including all stop -//! bits, have left the hardware shift register. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns status of UART transmitter. -//! - \c true : UART is transmitting. -//! - \c false : All transmissions are complete. -// -//***************************************************************************** -__STATIC_INLINE bool -UARTBusy(uint32_t ui32Base) -{ - // Check the argument. - ASSERT(UARTBaseValid(ui32Base)); - - // Determine if the UART is busy. - return((HWREG(ui32Base + UART_O_FR) & UART_FR_BUSY) ? - UART_BUSY : UART_IDLE); -} - -//***************************************************************************** -// -//! \brief Causes a BREAK to be sent. -//! -//! \note For proper transmission of a break -//! command, the break must be asserted for at least two complete frames. -//! -//! \param ui32Base is the base address of the UART port. -//! \param bBreakState controls the output level. -//! - \c true : Asserts a break condition on the UART. -//! - \c false : Removes the break condition. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTBreakCtl(uint32_t ui32Base, bool bBreakState) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Set the break condition as requested. - HWREG(ui32Base + UART_O_LCRH) = - (bBreakState ? - (HWREG(ui32Base + UART_O_LCRH) | UART_LCRH_BRK) : - (HWREG(ui32Base + UART_O_LCRH) & ~(UART_LCRH_BRK))); -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for a UART interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! Specific UART interrupts must be enabled via \ref UARTIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source. -//! -//! \param ui32Base is the base address of the UART module. -//! \param pfnHandler is a pointer to the function to be called when the -//! UART interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void UARTIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for a UART interrupt in the dynamic interrupt table. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a UART interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \param ui32Base is the base address of the UART module. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -extern void UARTIntUnregister(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Enables individual UART interrupt sources. -//! -//! This function enables the indicated UART interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! The parameter is the bitwise OR of any of the following: -//! - \ref UART_INT_EOT : End Of Transmission interrupt. -//! - \ref UART_INT_OE : Overrun Error interrupt. -//! - \ref UART_INT_BE : Break Error interrupt. -//! - \ref UART_INT_PE : Parity Error interrupt. -//! - \ref UART_INT_FE : Framing Error interrupt. -//! - \ref UART_INT_RT : Receive Timeout interrupt. -//! - \ref UART_INT_TX : Transmit interrupt. -//! - \ref UART_INT_RX : Receive interrupt. -//! - \ref UART_INT_CTS : CTS interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Enable the specified interrupts. - HWREG(ui32Base + UART_O_IMSC) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Disables individual UART interrupt sources. -//! -//! This function disables the indicated UART interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be disabled. -//! - \ref UART_INT_EOT : End Of Transmission interrupt. -//! - \ref UART_INT_OE : Overrun Error interrupt. -//! - \ref UART_INT_BE : Break Error interrupt. -//! - \ref UART_INT_PE : Parity Error interrupt. -//! - \ref UART_INT_FE : Framing Error interrupt. -//! - \ref UART_INT_RT : Receive Timeout interrupt. -//! - \ref UART_INT_TX : Transmit interrupt. -//! - \ref UART_INT_RX : Receive interrupt. -//! - \ref UART_INT_CTS : CTS interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Disable the specified interrupts. - HWREG(ui32Base + UART_O_IMSC) &= ~(ui32IntFlags); -} - -//***************************************************************************** -// -//! \brief Gets the current interrupt status. -//! -//! This function returns the interrupt status for the specified UART. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \param ui32Base is the base address of the UART port. -//! \param bMasked selects either raw or masked interrupt. -//! - \c true : Masked interrupt status is required. -//! - \c false : Raw interrupt status is required. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of: -//! - \ref UART_INT_EOT : End Of Transmission interrupt. -//! - \ref UART_INT_OE : Overrun Error interrupt. -//! - \ref UART_INT_BE : Break Error interrupt. -//! - \ref UART_INT_PE : Parity Error interrupt. -//! - \ref UART_INT_FE : Framing Error interrupt. -//! - \ref UART_INT_RT : Receive Timeout interrupt. -//! - \ref UART_INT_TX : Transmit interrupt. -//! - \ref UART_INT_RX : Receive interrupt. -//! - \ref UART_INT_CTS : CTS interrupt. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -UARTIntStatus(uint32_t ui32Base, bool bMasked) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Return either the interrupt status or the raw interrupt status as - // requested. - if(bMasked) - { - return(HWREG(ui32Base + UART_O_MIS)); - } - else - { - return(HWREG(ui32Base + UART_O_RIS)); - } -} - -//***************************************************************************** -// -//! \brief Clears UART interrupt sources. -//! -//! The specified UART interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! - \ref UART_INT_EOT : End Of Transmission interrupt. -//! - \ref UART_INT_OE : Overrun Error interrupt. -//! - \ref UART_INT_BE : Break Error interrupt. -//! - \ref UART_INT_PE : Parity Error interrupt. -//! - \ref UART_INT_FE : Framing Error interrupt. -//! - \ref UART_INT_RT : Receive Timeout interrupt. -//! - \ref UART_INT_TX : Transmit interrupt. -//! - \ref UART_INT_RX : Receive interrupt. -//! - \ref UART_INT_CTS : CTS interrupt. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // Check the arguments - ASSERT(UARTBaseValid(ui32Base)); - - // Clear the requested interrupt sources - HWREG(ui32Base + UART_O_ICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! \brief Enable UART DMA operation. -//! -//! The specified UART DMA features are enabled. The UART can be -//! configured to use DMA for transmit or receive, and to disable -//! receive if an error occurs. -//! -//! \note The uDMA controller must also be set up before DMA can be used -//! with the UART. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32DMAFlags is a bit mask of the DMA features to enable. -//! The parameter is the bitwise OR of any of the following values: -//! - UART_DMA_RX : Enable DMA for receive. -//! - UART_DMA_TX : Enable DMA for transmit. -//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTDMAEnable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Set the requested bits in the UART DMA control register. - HWREG(ui32Base + UART_O_DMACTL) |= ui32DMAFlags; -} - -//***************************************************************************** -// -//! \brief Disable UART DMA operation. -//! -//! This function is used to disable UART DMA features that were enabled -//! by \ref UARTDMAEnable(). The specified UART DMA features are disabled. -//! -//! \param ui32Base is the base address of the UART port. -//! \param ui32DMAFlags is a bit mask of the DMA features to disable. -//! The parameter is the bitwise OR of any of the following values: -//! - UART_DMA_RX : Enable DMA for receive. -//! - UART_DMA_TX : Enable DMA for transmit. -//! - UART_DMA_ERR_RXSTOP : Disable DMA receive on UART error. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTDMADisable(uint32_t ui32Base, uint32_t ui32DMAFlags) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Clear the requested bits in the UART DMA control register. - HWREG(ui32Base + UART_O_DMACTL) &= ~ui32DMAFlags; -} - -//***************************************************************************** -// -//! \brief Gets current receiver errors. -//! -//! This function returns the current state of each of the 4 receiver error -//! sources. The returned errors are equivalent to the four error bits -//! returned via the previous call to \ref UARTCharGet() or \ref UARTCharGetNonBlocking() -//! with the exception that the overrun error is set immediately the overrun -//! occurs rather than when a character is next read. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return Returns a bitwise OR combination of the receiver error flags: -//! - \ref UART_RXERROR_FRAMING -//! - \ref UART_RXERROR_PARITY -//! - \ref UART_RXERROR_BREAK -//! - \ref UART_RXERROR_OVERRUN -// -//***************************************************************************** -__STATIC_INLINE uint32_t -UARTRxErrorGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Return the current value of the receive status register. - return(HWREG(ui32Base + UART_O_RSR) & 0x0000000F); -} - -//***************************************************************************** -// -//! \brief Clears all reported receiver errors. -//! -//! This function is used to clear all receiver error conditions reported via -//! \ref UARTRxErrorGet(). If using the overrun, framing error, parity error or -//! break interrupts, this function must be called after clearing the interrupt -//! to ensure that later errors of the same type trigger another interrupt. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTRxErrorClear(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(UARTBaseValid(ui32Base)); - - // Any write to the Error Clear Register will clear all bits which are - // currently set. - HWREG(ui32Base + UART_O_ECR) = 0; -} - -//***************************************************************************** -// -//! \brief Enables hardware flow control for both CTS and RTS -//! -//! Hardware flow control is disabled by default. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTHwFlowControlEnable( uint32_t ui32Base ) -{ - // Check the arguments. - ASSERT( UARTBaseValid( ui32Base )); - - HWREG( ui32Base + UART_O_CTL ) |= ( UART_CTL_CTSEN | UART_CTL_RTSEN ); -} - -//***************************************************************************** -// -//! \brief Disables hardware flow control for both CTS and RTS -//! -//! Hardware flow control is disabled by default. -//! -//! \param ui32Base is the base address of the UART port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -UARTHwFlowControlDisable( uint32_t ui32Base ) -{ - // Check the arguments. - ASSERT( UARTBaseValid( ui32Base )); - - HWREG( ui32Base + UART_O_CTL ) &= ~( UART_CTL_CTSEN | UART_CTL_RTSEN ); -} - - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_UARTFIFOLevelGet - #undef UARTFIFOLevelGet - #define UARTFIFOLevelGet ROM_UARTFIFOLevelGet - #endif - #ifdef ROM_UARTConfigSetExpClk - #undef UARTConfigSetExpClk - #define UARTConfigSetExpClk ROM_UARTConfigSetExpClk - #endif - #ifdef ROM_UARTConfigGetExpClk - #undef UARTConfigGetExpClk - #define UARTConfigGetExpClk ROM_UARTConfigGetExpClk - #endif - #ifdef ROM_UARTDisable - #undef UARTDisable - #define UARTDisable ROM_UARTDisable - #endif - #ifdef ROM_UARTCharGetNonBlocking - #undef UARTCharGetNonBlocking - #define UARTCharGetNonBlocking ROM_UARTCharGetNonBlocking - #endif - #ifdef ROM_UARTCharGet - #undef UARTCharGet - #define UARTCharGet ROM_UARTCharGet - #endif - #ifdef ROM_UARTCharPutNonBlocking - #undef UARTCharPutNonBlocking - #define UARTCharPutNonBlocking ROM_UARTCharPutNonBlocking - #endif - #ifdef ROM_UARTCharPut - #undef UARTCharPut - #define UARTCharPut ROM_UARTCharPut - #endif - #ifdef ROM_UARTIntRegister - #undef UARTIntRegister - #define UARTIntRegister ROM_UARTIntRegister - #endif - #ifdef ROM_UARTIntUnregister - #undef UARTIntUnregister - #define UARTIntUnregister ROM_UARTIntUnregister - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h deleted file mode 100644 index e239428e672..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/uart_doc.h +++ /dev/null @@ -1,107 +0,0 @@ -/****************************************************************************** -* Filename: uart_doc.h -* Revised: 2018-02-09 15:45:36 +0100 (fr, 09 feb 2018) -* Revision: 51470 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -/*! -\addtogroup uart_api -@{ - -\section sec_uart_printf Use printf() - -DriverLib only supports writing a single character at a time to the UART buffer but it is -possible to utilize the library function \c printf by overriding a few of the functions used by -\c printf with a device specific definition. However, the implementation of \c printf is -compiler specific and requires different functions to be overridden depending on the compiler. - -Using \c printf can increase code size significantly but some compilers provide a highly optimized -and configurable implementation suitable for embedded systems which makes the code size increase -acceptable for most applications. See the compiler's documentation for details about how to -configure the \c printf library function. - -It is required that the application configures and enables the UART module before using \c printf -function. - -\subsection sec_uart_printf_ccs Code Composer Studio - -In Code Composer Studio the functions \c fputc and \c fputs must be overridden. - -\code{.c} -#include -#include - -#define PRINTF_UART UART0_BASE - -// Override 'fputc' function in order to use printf() to output to UART -int fputc(int _c, register FILE *_fp) -{ - UARTCharPut(PRINTF_UART, (uint8_t)_c); - return _c; -} - -// Override 'fputs' function in order to use printf() to output to UART -int fputs(const char *_ptr, register FILE *_fp) -{ - unsigned int i, len; - - len = strlen(_ptr); - - for(i=0 ; i -#include - -#define PRINTF_UART UART0_BASE - -// Override 'putchar' function in order to use printf() to output to UART. -int putchar(int data) -{ - UARTCharPut(PRINTF_UART, (uint8_t)data); - return data; -} -\endcode - -@} -*/ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/udma.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/udma.c deleted file mode 100644 index 32807e11d4d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/udma.c +++ /dev/null @@ -1,448 +0,0 @@ -/****************************************************************************** -* Filename: udma.c -* Revised: 2017-04-26 18:27:45 +0200 (Wed, 26 Apr 2017) -* Revision: 48852 -* -* Description: Driver for the uDMA controller -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "udma.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef uDMAChannelAttributeEnable - #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable - #undef uDMAChannelAttributeDisable - #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable - #undef uDMAChannelAttributeGet - #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet - #undef uDMAChannelControlSet - #define uDMAChannelControlSet NOROM_uDMAChannelControlSet - #undef uDMAChannelTransferSet - #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet - #undef uDMAChannelScatterGatherSet - #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet - #undef uDMAChannelSizeGet - #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet - #undef uDMAChannelModeGet - #define uDMAChannelModeGet NOROM_uDMAChannelModeGet -#endif - -//***************************************************************************** -// -// Enables attributes of a uDMA channel -// -//***************************************************************************** -void -uDMAChannelAttributeEnable(uint32_t ui32Base, uint32_t ui32ChannelNum, - uint32_t ui32Attr) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // Set the useburst bit for this channel if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_USEBURST) - { - HWREG(ui32Base + UDMA_O_SETBURST) = 1 << ui32ChannelNum; - } - - // Set the alternate control select bit for this channel, - // if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_ALTSELECT) - { - HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) = 1 << ui32ChannelNum; - } - - // Set the high priority bit for this channel, if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; - } - - // Set the request mask bit for this channel, if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_REQMASK) - { - HWREG(ui32Base + UDMA_O_SETREQMASK) = 1 << ui32ChannelNum; - } -} - -//***************************************************************************** -// -// Disables attributes of an uDMA channel -// -//***************************************************************************** -void -uDMAChannelAttributeDisable(uint32_t ui32Base, uint32_t ui32ChannelNum, - uint32_t ui32Attr) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - ASSERT((ui32Attr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // Clear the useburst bit for this channel if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_USEBURST) - { - HWREG(ui32Base + UDMA_O_CLEARBURST) = 1 << ui32ChannelNum; - } - - // Clear the alternate control select bit for this channel, if set in - // ululAttr. - if(ui32Attr & UDMA_ATTR_ALTSELECT) - { - HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; - } - - // Clear the high priority bit for this channel, if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; - } - - // Clear the request mask bit for this channel, if set in ui32Attr. - if(ui32Attr & UDMA_ATTR_REQMASK) - { - HWREG(ui32Base + UDMA_O_CLEARREQMASK) = 1 << ui32ChannelNum; - } -} - -//***************************************************************************** -// -// Gets the enabled attributes of a uDMA channel -// -//***************************************************************************** -uint32_t -uDMAChannelAttributeGet(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - uint32_t ui32Attr = 0; - - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Check to see if useburst bit is set for this channel. - if(HWREG(ui32Base + UDMA_O_SETBURST) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_USEBURST; - } - - // Check to see if the alternate control bit is set for this channel. - if(HWREG(ui32Base + UDMA_O_SETCHNLPRIALT) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_ALTSELECT; - } - - // Check to see if the high priority bit is set for this channel. - if(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_HIGH_PRIORITY; - } - - // Check to see if the request mask bit is set for this channel. - if(HWREG(ui32Base + UDMA_O_SETREQMASK) & (1 << ui32ChannelNum)) - { - ui32Attr |= UDMA_ATTR_REQMASK; - } - - // Return the configuration flags. - return(ui32Attr); -} - -//***************************************************************************** -// -// Sets the control parameters for a uDMA channel control structure -// -//***************************************************************************** -void -uDMAChannelControlSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, - uint32_t ui32Control) -{ - tDMAControlTable *pControlTable; - - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - - // Get the base address of the control table. - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // Get the current control word value and mask off the fields to be - // changed, then OR in the new settings. - pControlTable[ui32ChannelStructIndex].ui32Control = - ((pControlTable[ui32ChannelStructIndex].ui32Control & - ~(UDMA_DST_INC_M | - UDMA_SRC_INC_M | - UDMA_SIZE_M | - UDMA_ARB_M | - UDMA_NEXT_USEBURST)) | - ui32Control); -} - -//***************************************************************************** -// -// Sets the transfer parameters for a uDMA channel control structure -// -//***************************************************************************** -void -uDMAChannelTransferSet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex, - uint32_t ui32Mode, void *pvSrcAddr, void *pvDstAddr, - uint32_t ui32TransferSize) -{ - tDMAControlTable *pControlTable; - uint32_t ui32Control; - uint32_t ui32Inc; - uint32_t ui32BufferBytes; - - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - ASSERT(ui32Mode <= UDMA_MODE_PER_SCATTER_GATHER); - ASSERT((uint32_t)pvSrcAddr >= SRAM_BASE); - ASSERT((uint32_t)pvDstAddr >= SRAM_BASE); - ASSERT((ui32TransferSize != 0) && (ui32TransferSize <= UDMA_XFER_SIZE_MAX)); - - // Get the base address of the control table. - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // Get the current control word value and mask off the mode and size - // fields. - ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & - ~(UDMA_XFER_SIZE_M | UDMA_MODE_M)); - - // Adjust the mode if the alt control structure is selected. - if(ui32ChannelStructIndex & UDMA_ALT_SELECT) - { - if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) - { - ui32Mode |= UDMA_MODE_ALT_SELECT; - } - } - - // Set the transfer size and mode in the control word (but don't write the - // control word yet as it could kick off a transfer). - ui32Control |= ui32Mode | ((ui32TransferSize - 1) << UDMA_XFER_SIZE_S); - - // Get the address increment value for the source, from the control word. - ui32Inc = (ui32Control & UDMA_SRC_INC_M); - - // Compute the ending source address of the transfer. If the source - // increment is set to none, then the ending address is the same as the - // beginning. - if(ui32Inc != UDMA_SRC_INC_NONE) - { - ui32Inc = ui32Inc >> UDMA_SRC_INC_S; - ui32BufferBytes = ui32TransferSize << ui32Inc; - pvSrcAddr = (void *)((uint32_t)pvSrcAddr + ui32BufferBytes - (1 << ui32Inc)); - } - - // Load the source ending address into the control block. - pControlTable[ui32ChannelStructIndex].pvSrcEndAddr = pvSrcAddr; - - // Get the address increment value for the destination, from the control - // word. - ui32Inc = ui32Control & UDMA_DST_INC_M; - - // Compute the ending destination address of the transfer. If the - // destination increment is set to none, then the ending address is the - // same as the beginning. - if(ui32Inc != UDMA_DST_INC_NONE) - { - // There is a special case if this is setting up a scatter-gather - // transfer. The destination pointer needs to point to the end of - // the alternate structure for this channel instead of calculating - // the end of the buffer in the normal way. - if((ui32Mode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ui32Mode == UDMA_MODE_PER_SCATTER_GATHER)) - { - pvDstAddr = - (void *)&pControlTable[ui32ChannelStructIndex | - UDMA_ALT_SELECT].ui32Spare; - } - // Not a scatter-gather transfer, calculate end pointer normally. - else - { - ui32Inc = ui32Inc >> UDMA_DST_INC_S; - ui32BufferBytes = ui32TransferSize << ui32Inc; - pvDstAddr = (void *)((uint32_t)pvDstAddr + ui32BufferBytes - 1); - } - } - - // Load the destination ending address into the control block. - pControlTable[ui32ChannelStructIndex].pvDstEndAddr = pvDstAddr; - - // Write the new control word value. - pControlTable[ui32ChannelStructIndex].ui32Control = ui32Control; -} - -//***************************************************************************** -// -// Configures a uDMA channel for scatter-gather mode -// -//***************************************************************************** -void -uDMAChannelScatterGatherSet(uint32_t ui32Base, uint32_t ui32ChannelNum, - uint32_t ui32TaskCount, void *pvTaskList, - uint32_t ui32IsPeriphSG) -{ - tDMAControlTable *pControlTable; - tDMAControlTable *pTaskTable; - - // Check the parameters. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - ASSERT(pvTaskList != 0); - ASSERT(ui32TaskCount <= UDMA_XFER_SIZE_MAX); - ASSERT(ui32TaskCount != 0); - - // Get the base address of the control table. - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // Get a handy pointer to the task list. - pTaskTable = (tDMAControlTable *)pvTaskList; - - // Compute the ending address for the source pointer. This will be the - // last element of the last task in the task table. - pControlTable[ui32ChannelNum].pvSrcEndAddr = - &pTaskTable[ui32TaskCount - 1].ui32Spare; - - // Compute the ending address for the destination pointer. This will be - // the end of the alternate structure for this channel. - pControlTable[ui32ChannelNum].pvDstEndAddr = - &pControlTable[ui32ChannelNum | UDMA_ALT_SELECT].ui32Spare; - - // Compute the control word. Most configurable items are fixed for - // scatter-gather. Item and increment sizes are all 32-bit and arb - // size must be 4. The count is the number of items in the task list - // times 4 (4 words per task). - pControlTable[ui32ChannelNum].ui32Control = - (UDMA_DST_INC_32 | UDMA_SRC_INC_32 | - UDMA_SIZE_32 | UDMA_ARB_4 | - (((ui32TaskCount * 4) - 1) << UDMA_XFER_SIZE_S) | - (ui32IsPeriphSG ? UDMA_MODE_PER_SCATTER_GATHER : - UDMA_MODE_MEM_SCATTER_GATHER)); - - // Scatter-gather operations can leave the alt bit set. So if doing - // back to back scatter-gather transfers, the second attempt may not - // work correctly because the alt bit is set. Therefore, clear the - // alt bit here to ensure that it is always cleared before a new SG - // transfer is started. - HWREG(ui32Base + UDMA_O_CLEARCHNLPRIALT) = 1 << ui32ChannelNum; - -} - -//***************************************************************************** -// -// Gets the current transfer size for a uDMA channel control structure -// -//***************************************************************************** -uint32_t -uDMAChannelSizeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) -{ - tDMAControlTable *pControlTable; - uint32_t ui32Control; - - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - - // Get the base address of the control table. - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // Get the current control word value and mask off all but the size field - // and the mode field. - ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & - (UDMA_XFER_SIZE_M | UDMA_MODE_M)); - - // If the size field and mode field are 0 then the transfer is finished - // and there are no more items to transfer. - if(ui32Control == 0) - { - return(0); - } - - // Otherwise, if either the size field or more field is non-zero, then - // not all the items have been transferred. - else - { - // Shift the size field and add one, then return to user. - return((ui32Control >> UDMA_XFER_SIZE_S) + 1); - } -} - -//***************************************************************************** -// -// Gets the transfer mode for a uDMA channel control structure -// -//***************************************************************************** -uint32_t -uDMAChannelModeGet(uint32_t ui32Base, uint32_t ui32ChannelStructIndex) -{ - tDMAControlTable *pControlTable; - uint32_t ui32Control; - - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelStructIndex < (UDMA_NUM_CHANNELS * 2)); - ASSERT(HWREG(ui32Base + UDMA_O_CTRL) != 0); - - // Get the base address of the control table. - pControlTable = (tDMAControlTable *)HWREG(ui32Base + UDMA_O_CTRL); - - // Get the current control word value and mask off all but the mode field. - ui32Control = (pControlTable[ui32ChannelStructIndex].ui32Control & - UDMA_MODE_M); - - // Check if scatter/gather mode, and if so, mask off the alt bit. - if(((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || - ((ui32Control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) - { - ui32Control &= ~UDMA_MODE_ALT_SELECT; - } - - // Return the mode to the caller. - return(ui32Control); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h deleted file mode 100644 index 510691b29c2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/udma.h +++ /dev/null @@ -1,1240 +0,0 @@ -/****************************************************************************** -* Filename: udma.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the uDMA controller. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup udma_api -//! @{ -// -//***************************************************************************** - -#ifndef __UDMA_H__ -#define __UDMA_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_udma.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define uDMAChannelAttributeEnable NOROM_uDMAChannelAttributeEnable - #define uDMAChannelAttributeDisable NOROM_uDMAChannelAttributeDisable - #define uDMAChannelAttributeGet NOROM_uDMAChannelAttributeGet - #define uDMAChannelControlSet NOROM_uDMAChannelControlSet - #define uDMAChannelTransferSet NOROM_uDMAChannelTransferSet - #define uDMAChannelScatterGatherSet NOROM_uDMAChannelScatterGatherSet - #define uDMAChannelSizeGet NOROM_uDMAChannelSizeGet - #define uDMAChannelModeGet NOROM_uDMAChannelModeGet -#endif - -//***************************************************************************** -// -//! \brief A structure that defines an entry in the channel control table. -//! -//! These fields are used by the uDMA controller and normally it is not necessary for -//! software to directly read or write fields in the table. -// -//***************************************************************************** -typedef struct -{ - volatile void *pvSrcEndAddr; //!< The ending source address of the data transfer. - volatile void *pvDstEndAddr; //!< The ending destination address of the data transfer. - volatile uint32_t ui32Control; //!< The channel control mode. - volatile uint32_t ui32Spare; //!< An unused location. -} -tDMAControlTable; - -//***************************************************************************** -// -//! \brief A helper macro for building scatter-gather task table entries. -//! -//! This macro is intended to be used to help populate a table of uDMA tasks -//! for a scatter-gather transfer. This macro will calculate the values for -//! the fields of a task structure entry based on the input parameters. -//! -//! There are specific requirements for the values of each parameter. No -//! checking is done so it is up to the caller to ensure that correct values -//! are used for the parameters. -//! -//! This macro is intended to be used to initialize individual entries of -//! a structure of tDMAControlTable type, like this: -//! -/*! -\verbatim - tDMAControlTable MyTaskList[] = - { - uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, - UDMA_SRC_INC_8, MySourceBuf, - UDMA_DST_INC_8, MyDestBuf, - UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), - uDMATaskStructEntry(Task2Count, ... ), - } -\endverbatim -*/ -//! \param ui32TransferCount is the count of items to transfer for this task. -//! It must be in the range 1-1024. -//! \param ui32ItemSize is the bit size of the items to transfer for this task. -//! It must be one of: -//! - \ref UDMA_SIZE_8 -//! - \ref UDMA_SIZE_16 -//! - \ref UDMA_SIZE_32 -//! \param ui32SrcIncrement is the bit size increment for source data. -//! It must be one of: -//! - \ref UDMA_SRC_INC_8 -//! - \ref UDMA_SRC_INC_16 -//! - \ref UDMA_SRC_INC_32 -//! - \ref UDMA_SRC_INC_NONE -//! \param pvSrcAddr is the starting address of the data to transfer. -//! \param ui32DstIncrement is the bit size increment for destination data. -//! It must be one of: -//! - \ref UDMA_DST_INC_8 -//! - \ref UDMA_DST_INC_16 -//! - \ref UDMA_DST_INC_32 -//! - \ref UDMA_DST_INC_NONE -//! \param pvDstAddr is the starting address of the destination data. -//! \param ui32ArbSize is the arbitration size to use for the transfer task. -//! This is used to select the arbitration size in powers of 2, from 1 to 1024. -//! It must be one of: -//! - \ref UDMA_ARB_1 -//! - \ref UDMA_ARB_2 -//! - \ref UDMA_ARB_4 -//! - ... -//! - \ref UDMA_ARB_1024 -//! \param ui32Mode is the transfer mode for this task. -//! Note that normally all tasks will be one of the scatter-gather modes while the -//! last task is a task list will be AUTO or BASIC. -//! It must be one of: -//! - \ref UDMA_MODE_BASIC -//! - \ref UDMA_MODE_AUTO -//! - \ref UDMA_MODE_MEM_SCATTER_GATHER -//! - \ref UDMA_MODE_PER_SCATTER_GATHER -//! -//! \return None (this is not a function) -// -//***************************************************************************** -#define uDMATaskStructEntry(ui32TransferCount, \ - ui32ItemSize, \ - ui32SrcIncrement, \ - pvSrcAddr, \ - ui32DstIncrement, \ - pvDstAddr, \ - ui32ArbSize, \ - ui32Mode) \ - { \ - (((ui32SrcIncrement) == UDMA_SRC_INC_NONE) ? (pvSrcAddr) : \ - ((void *)(&((uint8_t *)(pvSrcAddr))[((ui32TransferCount) << \ - ((ui32SrcIncrement) >> 26)) - 1]))), \ - (((ui32DstIncrement) == UDMA_DST_INC_NONE) ? (pvDstAddr) : \ - ((void *)(&((uint8_t *)(pvDstAddr))[((ui32TransferCount) << \ - ((ui32DstIncrement) >> 30)) - 1]))), \ - (ui32SrcIncrement) | (ui32DstIncrement) | (ui32ItemSize) | \ - (ui32ArbSize) | (((ui32TransferCount) - 1) << 4) | \ - ((((ui32Mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ - ((ui32Mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ - (ui32Mode) | UDMA_MODE_ALT_SELECT : (ui32Mode)), 0 \ - } - -//***************************************************************************** -// -// The hardware configured number of uDMA channels. -// -//***************************************************************************** -#define UDMA_NUM_CHANNELS 21 - -//***************************************************************************** -// -// The level of priority for the uDMA channels -// -//***************************************************************************** -#define UDMA_PRIORITY_LOW 0x00000000 -#define UDMA_PRIORITY_HIGH 0x00000001 - -//***************************************************************************** -// -// Flags that can be passed to uDMAChannelAttributeEnable(), -// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). -// -//***************************************************************************** -#define UDMA_ATTR_USEBURST 0x00000001 -#define UDMA_ATTR_ALTSELECT 0x00000002 -#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 -#define UDMA_ATTR_REQMASK 0x00000008 -#define UDMA_ATTR_ALL 0x0000000F - -//***************************************************************************** -// -// DMA control modes that can be passed to uDMAChannelModeSet() and returned -// uDMAChannelModeGet(). -// -//***************************************************************************** -#define UDMA_MODE_STOP 0x00000000 -#define UDMA_MODE_BASIC 0x00000001 -#define UDMA_MODE_AUTO 0x00000002 -#define UDMA_MODE_PINGPONG 0x00000003 -#define UDMA_MODE_MEM_SCATTER_GATHER \ - 0x00000004 -#define UDMA_MODE_PER_SCATTER_GATHER \ - 0x00000006 -#define UDMA_MODE_M 0x00000007 // uDMA Transfer Mode -#define UDMA_MODE_ALT_SELECT 0x00000001 - -//***************************************************************************** -// -// Channel configuration values that can be passed to uDMAControlSet(). -// -//***************************************************************************** -#define UDMA_DST_INC_8 0x00000000 -#define UDMA_DST_INC_16 0x40000000 -#define UDMA_DST_INC_32 0x80000000 -#define UDMA_DST_INC_NONE 0xC0000000 -#define UDMA_DST_INC_M 0xC0000000 // Destination Address Increment -#define UDMA_DST_INC_S 30 -#define UDMA_SRC_INC_8 0x00000000 -#define UDMA_SRC_INC_16 0x04000000 -#define UDMA_SRC_INC_32 0x08000000 -#define UDMA_SRC_INC_NONE 0x0c000000 -#define UDMA_SRC_INC_M 0x0C000000 // Source Address Increment -#define UDMA_SRC_INC_S 26 -#define UDMA_SIZE_8 0x00000000 -#define UDMA_SIZE_16 0x11000000 -#define UDMA_SIZE_32 0x22000000 -#define UDMA_SIZE_M 0x33000000 // Data Size -#define UDMA_SIZE_S 24 -#define UDMA_ARB_1 0x00000000 -#define UDMA_ARB_2 0x00004000 -#define UDMA_ARB_4 0x00008000 -#define UDMA_ARB_8 0x0000c000 -#define UDMA_ARB_16 0x00010000 -#define UDMA_ARB_32 0x00014000 -#define UDMA_ARB_64 0x00018000 -#define UDMA_ARB_128 0x0001c000 -#define UDMA_ARB_256 0x00020000 -#define UDMA_ARB_512 0x00024000 -#define UDMA_ARB_1024 0x00028000 -#define UDMA_ARB_M 0x0003C000 // Arbitration Size -#define UDMA_ARB_S 14 -#define UDMA_NEXT_USEBURST 0x00000008 -#define UDMA_XFER_SIZE_MAX 1024 -#define UDMA_XFER_SIZE_M 0x00003FF0 // Transfer size -#define UDMA_XFER_SIZE_S 4 - -//***************************************************************************** -// -// Channel numbers to be passed to API functions that require a channel number -// ID. -// -//***************************************************************************** -#define UDMA_CHAN_SW_EVT0 0 // Software Event Channel 0 -#define UDMA_CHAN_UART0_RX 1 // UART0 RX Data -#define UDMA_CHAN_UART0_TX 2 // UART0 RX Data -#define UDMA_CHAN_SSI0_RX 3 // SSI0 RX Data -#define UDMA_CHAN_SSI0_TX 4 // SSI0 RX Data -#define UDMA_CHAN_AUX_ADC 7 // AUX ADC event -#define UDMA_CHAN_AUX_SW 8 // AUX Software event -#define UDMA_CHAN_TIMER0_A 9 // Timer0 A event -#define UDMA_CHAN_TIMER0_B 10 // Timer0 B event -#define UDMA_CHAN_TIMER1_A 11 -#define UDMA_CHAN_TIMER1_B 12 -#define UDMA_CHAN_AON_PROG2 13 -#define UDMA_CHAN_DMA_PROG 14 -#define UDMA_CHAN_AON_RTC 15 -#define UDMA_CHAN_SSI1_RX 16 -#define UDMA_CHAN_SSI1_TX 17 -#define UDMA_CHAN_SW_EVT1 18 -#define UDMA_CHAN_SW_EVT2 19 -#define UDMA_CHAN_SW_EVT3 20 - -//***************************************************************************** -// -// Flags to be OR'd with the channel ID to indicate if the primary or alternate -// control structure should be used. -// -//***************************************************************************** -#define UDMA_PRI_SELECT 0x00000000 -#define UDMA_ALT_SELECT 0x00000020 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \internal -//! -//! \brief Checks a uDMA base address. -//! -//! This function determines if a uDMA module base address is valid. -//! -//! \param ui32Base specifies the uDMA module base address. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -uDMABaseValid(uint32_t ui32Base) -{ - return(ui32Base == UDMA0_BASE); -} -#endif - -//***************************************************************************** -// -//! \brief Enables the uDMA controller for use. -//! -//! This function enables the uDMA controller. The uDMA controller must be -//! enabled before it can be configured and used. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAEnable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Set the master enable bit in the config register. - HWREG(ui32Base + UDMA_O_CFG) = UDMA_CFG_MASTERENABLE; -} - -//***************************************************************************** -// -//! \brief Disables the uDMA controller for use. -//! -//! This function disables the uDMA controller. Once disabled, the uDMA -//! controller will not operate until re-enabled with \ref uDMAEnable(). -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -uDMADisable(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Clear the master enable bit in the config register. - HWREG(ui32Base + UDMA_O_CFG) = 0; -} - -//***************************************************************************** -// -//! \brief Gets the uDMA error status. -//! -//! This function returns the uDMA error status. It should be called from -//! within the uDMA error interrupt handler to determine if a uDMA error -//! occurred. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return Returns non-zero if a uDMA error is pending. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -uDMAErrorStatusGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Return the uDMA error status. - return(HWREG(ui32Base + UDMA_O_ERROR)); -} - -//***************************************************************************** -// -//! \brief Clears the uDMA error interrupt. -//! -//! This function clears a pending uDMA error interrupt. It should be called -//! from within the uDMA error interrupt handler to clear the interrupt. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAErrorStatusClear(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Clear the uDMA error interrupt. - HWREG(ui32Base + UDMA_O_ERROR) = UDMA_ERROR_STATUS; -} - -//***************************************************************************** -// -//! \brief Enables a uDMA channel for operation. -//! -//! This function enables a specific uDMA channel for use. This function must -//! be used to enable a channel before it can be used to perform a uDMA -//! transfer. -//! -//! When a uDMA transfer is completed, the channel will be automatically -//! disabled by the uDMA controller. Therefore, this function should be called -//! prior to starting up any new transfer. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel number to enable. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAChannelEnable(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Set the bit for this channel in the enable set register. - HWREG(ui32Base + UDMA_O_SETCHANNELEN) = 1 << ui32ChannelNum; -} - -//***************************************************************************** -// -//! \brief Disables a uDMA channel for operation. -//! -//! This function disables a specific uDMA channel. Once disabled, a channel -//! will not respond to uDMA transfer requests until re-enabled via -//! \ref uDMAChannelEnable(). -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel number to disable. -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -uDMAChannelDisable(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Set the bit for this channel in the enable clear register. - HWREG(ui32Base + UDMA_O_CLEARCHANNELEN) = 1 << ui32ChannelNum; -} - -//***************************************************************************** -// -//! \brief Checks if a uDMA channel is enabled for operation. -//! -//! This function checks to see if a specific uDMA channel is enabled. This -//! can be used to check the status of a transfer, since the channel will -//! be automatically disabled at the end of a transfer. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel number to check. -//! -//! \return Returns status of uDMA channel. -//! - \c true : Channel is enabled. -//! - \c false : Disabled. -// -//***************************************************************************** -__STATIC_INLINE bool -uDMAChannelIsEnabled(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // AND the specified channel bit with the enable register, and return the - // result. - return((HWREG(ui32Base + UDMA_O_SETCHANNELEN) & (1 << ui32ChannelNum)) ? - true : false); -} - -//***************************************************************************** -// -//! \brief Sets the base address for the channel control table. -//! -//! This function sets the base address of the channel control table. This -//! table resides in system memory and holds control information for each uDMA -//! channel. The table must be aligned on a 1024 byte boundary. The base -//! address must be set before any of the channel functions can be used. -//! Setting the base address of the primary control table will automatically -//! set the address for the alternate control table as the next memory -//! location after the primary control table. -//! -//! The size of the channel control table depends on the number of uDMA -//! channels, and which transfer modes are used. Refer to the introductory -//! text and the microcontroller datasheet for more information about the -//! channel control table. -//! -//! \note This register cannot be read when the controller is in the reset -//! state. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param pControlTable is a pointer to the 1024 byte aligned base address -//! of the uDMA channel control table. The address must be an absolute address -//! in system memory space. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAControlBaseSet(uint32_t ui32Base, void *pControlTable) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(((uint32_t)pControlTable & ~0x3FF) == - (uint32_t)pControlTable); - ASSERT((uint32_t)pControlTable >= SRAM_BASE); - - // Program the base address into the register. - HWREG(ui32Base + UDMA_O_CTRL) = (uint32_t)pControlTable; -} - -//***************************************************************************** -// -//! \brief Gets the base address for the channel control table. -//! -//! This function gets the base address of the channel control table. This -//! table resides in system memory and holds control information for each uDMA -//! channel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return Returns a pointer to the base address of the channel control table. -// -//***************************************************************************** -__STATIC_INLINE void * -uDMAControlBaseGet(uint32_t ui32Base) -{ - // Check the arguments. - - ASSERT(uDMABaseValid(ui32Base)); - // Read the current value of the control base register, and return it to - // the caller. - return((void *)HWREG(ui32Base + UDMA_O_CTRL)); -} - -//***************************************************************************** -// -//! \brief Gets the base address for the channel control table alternate structures. -//! -//! This function gets the base address of the second half of the channel -//! control table that holds the alternate control structures for each channel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return Returns a pointer to the base address of the second half of the -//! channel control table. -// -//***************************************************************************** -__STATIC_INLINE void * -uDMAControlAlternateBaseGet(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Read the current value of the control base register, and return it to - // the caller. - return((void *)HWREG(ui32Base + UDMA_O_ALTCTRL)); -} - -//***************************************************************************** -// -//! \brief Requests a uDMA channel to start a transfer. -//! -//! This function allows software to request a uDMA channel to begin a -//! transfer. This could be used for performing a memory to memory transfer, -//! or if for some reason a transfer needs to be initiated by software instead -//! of the peripheral associated with that channel. -//! -//! \note If the channel is a software channel and interrupts are used, then -//! the completion will be signaled on the uDMA dedicated interrupt. If a -//! peripheral channel is used, then the completion will be signaled on the -//! peripheral's interrupt. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel number on which to request a uDMA -//! transfer. -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -uDMAChannelRequest(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Set the bit for this channel in the software uDMA request register. - HWREG(ui32Base + UDMA_O_SOFTREQ) = 1 << ui32ChannelNum; -} - -//***************************************************************************** -// -//! \brief Enables attributes of a uDMA channel. -//! -//! This function is used to enable attributes of a uDMA channel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel to configure. -//! \param ui32Attr is a combination of attributes for the channel. -//! The parameter is the bitwise OR of any of the following: -//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. -//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel (it is very unlikely that this flag should be used). -//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None -// -//***************************************************************************** -extern void uDMAChannelAttributeEnable(uint32_t ui32Base, - uint32_t ui32ChannelNum, - uint32_t ui32Attr); - -//***************************************************************************** -// -//! \brief Disables attributes of an uDMA channel. -//! -//! This function is used to disable attributes of a uDMA channel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel to configure. -//! \param ui32Attr is a combination of attributes for the channel. -//! The parameter is the bitwise OR of any of the following: -//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. -//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel (it is very unlikely that this flag should be used). -//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None -// -//***************************************************************************** -extern void uDMAChannelAttributeDisable(uint32_t ui32Base, - uint32_t ui32ChannelNum, - uint32_t ui32Attr); - -//***************************************************************************** -// -//! \brief Gets the enabled attributes of a uDMA channel. -//! -//! This function returns a combination of flags representing the attributes of -//! the uDMA channel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the channel to configure. -//! -//! \return Returns the bitwise OR of the attributes of the uDMA channel, which -//! can be any of the following: -//! - \ref UDMA_ATTR_USEBURST is used to restrict transfers to use only a burst mode. -//! - \ref UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel (it is very unlikely that this flag should be used). -//! - \ref UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \ref UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -// -//***************************************************************************** -extern uint32_t uDMAChannelAttributeGet(uint32_t ui32Base, - uint32_t ui32ChannelNum); - -//***************************************************************************** -// -//! \brief Sets the control parameters for a uDMA channel control structure. -//! -//! This function is used to set control parameters for a uDMA transfer. These -//! are typically parameters that are not changed often. -//! -//! \note The address increment cannot be smaller than the data size. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: -//! - \ref UDMA_PRI_SELECT : Use primary data structure. -//! - \ref UDMA_ALT_SELECT : Use alternate data structure. -//! \param ui32Control is the bitwise OR of five values: -//! - Data size -//! - \ref UDMA_SIZE_8 : 8 bits. -//! - \ref UDMA_SIZE_16 : 16 bits. -//! - \ref UDMA_SIZE_32 : 32 bits. -//! - Source address increment -//! - \ref UDMA_SRC_INC_8 : 8 bits. -//! - \ref UDMA_SRC_INC_16 : 16 bits. -//! - \ref UDMA_SRC_INC_32 : 32 bits. -//! - \ref UDMA_SRC_INC_NONE : Non-incrementing. -//! - Destination address increment -//! - \ref UDMA_DST_INC_8 : 8 bits. -//! - \ref UDMA_DST_INC_16 : 16 bits. -//! - \ref UDMA_DST_INC_32 : 32 bits. -//! - \ref UDMA_DST_INC_NONE : Non-incrementing. -//! - Arbitration size. Determines how many items are transferred before -//! the uDMA controller re-arbitrates for the bus. In power of 2. -//! - \ref UDMA_ARB_1 -//! - \ref UDMA_ARB_2 -//! - \ref UDMA_ARB_4 -//! - \ref UDMA_ARB_8 -//! - ... -//! - \ref UDMA_ARB_1024 -//! - Force the channel to only respond to burst requests at the tail end of a scatter-gather transfer. -//! - \ref UDMA_NEXT_USEBURST -//! -//! \return None -// -//***************************************************************************** -extern void uDMAChannelControlSet(uint32_t ui32Base, - uint32_t ui32ChannelStructIndex, - uint32_t ui32Control); - -//***************************************************************************** -// -//! \brief Sets the transfer parameters for a uDMA channel control structure. -//! -//! This function is used to set the parameters for a uDMA transfer. These are -//! typically parameters that are changed often. The function -//! \ref uDMAChannelControlSet() MUST be called at least once for this channel prior -//! to calling this function. -//! -//! The \c pvSrcAddr and \c pvDstAddr parameters are pointers to the first -//! location of the data to be transferred. These addresses should be aligned -//! according to the item size. The compiler will take care of this if the -//! pointers are pointing to storage of the appropriate data type. -//! -//! The two scatter/gather modes, MEMORY and PERIPHERAL, are actually different -//! depending on whether the primary or alternate control structure is -//! selected. This function will look for the \ref UDMA_PRI_SELECT and -//! \ref UDMA_ALT_SELECT flag along with the channel number and will set the -//! scatter/gather mode as appropriate for the primary or alternate control -//! structure. -//! -//! The channel must also be enabled using \ref uDMAChannelEnable() after calling -//! this function. The transfer will not begin until the channel has been set -//! up and enabled. Note that the channel is automatically disabled after the -//! transfer is completed, meaning that \ref uDMAChannelEnable() must be called -//! again after setting up the next transfer. -//! -//! \note Great care must be taken to not modify a channel control structure -//! that is in use or else the results will be unpredictable, including the -//! possibility of undesired data transfers to or from memory or peripherals. -//! For BASIC and AUTO modes, it is safe to make changes when the channel is -//! disabled, or the \ref uDMAChannelModeGet() returns \ref UDMA_MODE_STOP. For -//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the -//! primary or alternate control structure only when the other is being used. -//! The \ref uDMAChannelModeGet() function will return \ref UDMA_MODE_STOP when a -//! channel control structure is inactive and safe to modify. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: -//! - \ref UDMA_PRI_SELECT : Use primary data structure. -//! - \ref UDMA_ALT_SELECT : Use alternate data structure. -//! \param ui32Mode is the type of uDMA transfer. -//! The parameter should be one of the following values: -//! - \ref UDMA_MODE_STOP : Stops the uDMA transfer. The controller sets the mode -//! to this value at the end of a transfer. -//! - \ref UDMA_MODE_BASIC : Perform a basic transfer based on request. -//! - \ref UDMA_MODE_AUTO to perform a transfer that will always complete once -//! started even if request is removed. -//! - \ref UDMA_MODE_PINGPONG : Set up a transfer that switches between the -//! primary and alternate control structures for the channel. This allows -//! use of ping-pong buffering for uDMA transfers. -//! - \ref UDMA_MODE_MEM_SCATTER_GATHER : Set up a memory scatter-gather transfer. -//! - \ref UDMA_MODE_PER_SCATTER_GATHER : Set up a peripheral scatter-gather transfer. -//! \param pvSrcAddr is the source address for the transfer. -//! \param pvDstAddr is the destination address for the transfer. -//! \param ui32TransferSize is the number of data items to transfer (\b NOT bytes). -//! -//! \return None -// -//***************************************************************************** -extern void uDMAChannelTransferSet(uint32_t ui32Base, - uint32_t ui32ChannelStructIndex, - uint32_t ui32Mode, void *pvSrcAddr, - void *pvDstAddr, uint32_t ui32TransferSize); - -//***************************************************************************** -// -//! \brief Configures a uDMA channel for scatter-gather mode. -//! -//! This function is used to configure a channel for scatter-gather mode. -//! The caller must have already set up a task list, and pass a pointer to -//! the start of the task list as the \c pvTaskList parameter. -//! -//! The \c ui32TaskCount parameter is the count of tasks in the task list, not the -//! size of the task list. -//! -//! The flag \c bIsPeriphSG should be used to indicate -//! if the scatter-gather should be configured for a peripheral or memory -//! scatter-gather operation. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is the uDMA channel number. -//! \param ui32TaskCount is the number of scatter-gather tasks to execute. -//! \param pvTaskList is a pointer to the beginning of the scatter-gather -//! task list. -//! \param ui32IsPeriphSG is a flag to indicate it is a peripheral -//! scatter-gather transfer (else it will be memory scatter-gather transfer) -//! -//! \return None -//! -//! \sa \ref uDMATaskStructEntry() -// -//***************************************************************************** -extern void uDMAChannelScatterGatherSet(uint32_t ui32Base, - uint32_t ui32ChannelNum, - uint32_t ui32TaskCount, - void *pvTaskList, - uint32_t ui32IsPeriphSG); - -//***************************************************************************** -// -//! \brief Gets the current transfer size for a uDMA channel control structure. -//! -//! This function is used to get the uDMA transfer size for a channel. The -//! transfer size is the number of items to transfer, where the size of an item -//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, -//! then the number of remaining items will be returned. If the transfer is -//! complete, then 0 will be returned. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: -//! - \ref UDMA_PRI_SELECT -//! - \ref UDMA_ALT_SELECT -//! -//! \return Returns the number of items remaining to transfer. -// -//***************************************************************************** -extern uint32_t uDMAChannelSizeGet(uint32_t ui32Base, - uint32_t ui32ChannelStructIndex); - -//***************************************************************************** -// -//! \brief Gets the transfer mode for a uDMA channel control structure. -//! -//! This function is used to get the transfer mode for the uDMA channel. It -//! can be used to query the status of a transfer on a channel. When the -//! transfer is complete the mode will be \ref UDMA_MODE_STOP. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelStructIndex is the bitwise OR of the uDMA channel number and: -//! - \ref UDMA_PRI_SELECT -//! - \ref UDMA_ALT_SELECT -//! -//! \return Returns the transfer mode of the specified channel and control -//! structure, which will be one of the following values: -//! - \ref UDMA_MODE_STOP -//! - \ref UDMA_MODE_BASIC -//! - \ref UDMA_MODE_AUTO -//! - \ref UDMA_MODE_PINGPONG -//! - \ref UDMA_MODE_MEM_SCATTER_GATHER -//! - \ref UDMA_MODE_PER_SCATTER_GATHER -// -//***************************************************************************** -extern uint32_t uDMAChannelModeGet(uint32_t ui32Base, - uint32_t ui32ChannelStructIndex); - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for the uDMA controller in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! \note The interrupt handler for uDMA is for transfer completion when the -//! software channel is used, and for error interrupts. The interrupts for each -//! peripheral channel are handled through the individual peripheral interrupt -//! handlers. -//! -//! \param ui32Base is the base address of the uDMA module. -//! \param ui32IntChannel specifies which uDMA interrupt is to be registered. -//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts -//! from the uDMA software channel. -//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error -//! interrupts. -//! \param pfnHandler is a pointer to the function to be called when the -//! interrupt is activated. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -uDMAIntRegister(uint32_t ui32Base, uint32_t ui32IntChannel, - void (*pfnHandler)(void)) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(pfnHandler); - ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR)); - - // Register the interrupt handler. - IntRegister(ui32IntChannel, pfnHandler); - - // Enable the memory management fault. - IntEnable(ui32IntChannel); -} - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for the uDMA controller in the dynamic interrupt table. -//! -//! This function will disable and clear the handler to be called for the -//! specified uDMA interrupt. -//! -//! \param ui32Base is the base address of the uDMA module. -//! \param ui32IntChannel specifies which uDMA interrupt to unregister. -//! - \c INT_DMA_DONE_COMB : Register an interrupt handler to process interrupts -//! from the uDMA software channel. -//! - \c INT_DMA_ERR : Register an interrupt handler to process uDMA error -//! interrupts. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -uDMAIntUnregister(uint32_t ui32Base, uint32_t ui32IntChannel) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT((ui32IntChannel == INT_DMA_DONE_COMB) || (ui32IntChannel == INT_DMA_ERR)); - - // Disable the interrupt. - IntDisable(ui32IntChannel); - - // Unregister the interrupt handler. - IntUnregister(ui32IntChannel); -} - -//***************************************************************************** -// -//! \brief Clears uDMA interrupt done status. -//! -//! Clears bits in the uDMA interrupt status register according to which bits -//! are set in \c ui32ChanMask. There is one bit for each channel. If a a bit -//! is set in \c ui32ChanMask, then that corresponding channel's interrupt -//! status will be cleared (if it was set). -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChanMask is a 32-bit mask with one bit for each uDMA channel. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAIntClear(uint32_t ui32Base, uint32_t ui32ChanMask) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Clear the requested bits in the uDMA interrupt status register. - HWREG(ui32Base + UDMA_O_REQDONE) = ui32ChanMask; -} - -//***************************************************************************** -// -//! \brief Get the uDMA interrupt status. -//! -//! This function returns the interrupt status for the specified UDMA. This -//! function does not differentiate between software or hardware activated -//! interrupts. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE uint32_t -uDMAIntStatus(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Return the uDMA interrupt status register. - return (HWREG(ui32Base + UDMA_O_REQDONE)); -} - -//***************************************************************************** -// -//! \brief Enable interrupt on software event driven uDMA transfers. -//! -//! \note The main purpose of this function is to prevent propagation of uDMA -//! status signals to a peripheral, if a peripheral and a software event is -//! sharing the uDMA channel. If it is desired to initiate a transfer by -//! writing to a register inside the uDMA (this means a software driven -//! channel), then the uDMA status signals propagation need to be blocked to -//! the hardware peripherals. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32IntChannel identifies which uDMA interrupt to enable software -//! interrupts for. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAIntSwEventEnable(uint32_t ui32Base, uint32_t ui32IntChannel) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS); - - // Enable the channel. - HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 1; -} - -//***************************************************************************** -// -//! \brief Disable interrupt on software event driven uDMA transfers. -//! -//! This register disables the blocking of the uDMA status signals propagation -//! to the hardware peripheral connected to the uDMA on the \c ui32IntChannel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32IntChannel identifies which uDMA interrupt to disable software -//! interrupts for. -//! -//! \return None -//! -//! \sa \ref uDMAIntSwEventEnable() -// -//***************************************************************************** -__STATIC_INLINE void -uDMAIntSwEventDisable(uint32_t ui32Base, uint32_t ui32IntChannel) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32IntChannel < UDMA_NUM_CHANNELS); - - // Disable the SW channel. - HWREGBITW(ui32Base + UDMA_O_DONEMASK, ui32IntChannel) = 0; -} - -//***************************************************************************** -// -//! \brief Return the status of the uDMA module. -//! -//! \note This status register cannot be read when the controller is in the reset state. -//! -//! \param ui32Base is the base address of the uDMA port. -//! -//! \return Current status of the uDMA module. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -uDMAGetStatus(uint32_t ui32Base) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - - // Read and return the status register. - return HWREG(ui32Base + UDMA_O_STATUS); -} - -//***************************************************************************** -// -//! \brief Set the priority of a uDMA channel. -//! -//! \note Writing 0 to a bit has no effect on the priority. To reset a channel -//! priority to the default value use \ref uDMAChannelPriorityClear(). -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum is uDMA channel to set the priority for. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAChannelPrioritySet(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Set the channel priority to high. - HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) = 1 << ui32ChannelNum; -} - -//***************************************************************************** -// -//! \brief Get the priority of a uDMA channel. -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum The uDMA channel to get the priority for. -//! -//! \return Returns one of: -//! - \ref UDMA_PRIORITY_HIGH -//! - \ref UDMA_PRIORITY_LOW -// -//***************************************************************************** -__STATIC_INLINE bool -uDMAChannelPriorityGet(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Return the channel priority. - return(HWREG(ui32Base + UDMA_O_SETCHNLPRIORITY) & (1 << ui32ChannelNum) ? - UDMA_PRIORITY_HIGH : UDMA_PRIORITY_LOW); -} - -//***************************************************************************** -// -//! \brief Clear the priority of a uDMA channel. -//! -//! \note Writing 0 to a bit has no effect on the priority. To set a channel -//! priority to high use \ref uDMAChannelPrioritySet(). -//! -//! \param ui32Base is the base address of the uDMA port. -//! \param ui32ChannelNum The uDMA channel to clear the priority for. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -uDMAChannelPriorityClear(uint32_t ui32Base, uint32_t ui32ChannelNum) -{ - // Check the arguments. - ASSERT(uDMABaseValid(ui32Base)); - ASSERT(ui32ChannelNum < UDMA_NUM_CHANNELS); - - // Clear the channel priority. - HWREG(ui32Base + UDMA_O_CLEARCHNLPRIORITY) = 1 << ui32ChannelNum; -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_uDMAChannelAttributeEnable - #undef uDMAChannelAttributeEnable - #define uDMAChannelAttributeEnable ROM_uDMAChannelAttributeEnable - #endif - #ifdef ROM_uDMAChannelAttributeDisable - #undef uDMAChannelAttributeDisable - #define uDMAChannelAttributeDisable ROM_uDMAChannelAttributeDisable - #endif - #ifdef ROM_uDMAChannelAttributeGet - #undef uDMAChannelAttributeGet - #define uDMAChannelAttributeGet ROM_uDMAChannelAttributeGet - #endif - #ifdef ROM_uDMAChannelControlSet - #undef uDMAChannelControlSet - #define uDMAChannelControlSet ROM_uDMAChannelControlSet - #endif - #ifdef ROM_uDMAChannelTransferSet - #undef uDMAChannelTransferSet - #define uDMAChannelTransferSet ROM_uDMAChannelTransferSet - #endif - #ifdef ROM_uDMAChannelScatterGatherSet - #undef uDMAChannelScatterGatherSet - #define uDMAChannelScatterGatherSet ROM_uDMAChannelScatterGatherSet - #endif - #ifdef ROM_uDMAChannelSizeGet - #undef uDMAChannelSizeGet - #define uDMAChannelSizeGet ROM_uDMAChannelSizeGet - #endif - #ifdef ROM_uDMAChannelModeGet - #undef uDMAChannelModeGet - #define uDMAChannelModeGet ROM_uDMAChannelModeGet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __UDMA_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/vims.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/vims.c deleted file mode 100644 index a80d44ea9d7..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/vims.c +++ /dev/null @@ -1,176 +0,0 @@ -/****************************************************************************** -* Filename: vims.c -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Description: Driver for the VIMS. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include "vims.h" - -//***************************************************************************** -// -// Handle support for DriverLib in ROM: -// This section will undo prototype renaming made in the header file -// -//***************************************************************************** -#if !defined(DOXYGEN) - #undef VIMSConfigure - #define VIMSConfigure NOROM_VIMSConfigure - #undef VIMSModeSet - #define VIMSModeSet NOROM_VIMSModeSet - #undef VIMSModeGet - #define VIMSModeGet NOROM_VIMSModeGet - #undef VIMSModeSafeSet - #define VIMSModeSafeSet NOROM_VIMSModeSafeSet -#endif - -//***************************************************************************** -// -// Configures the VIMS. -// -//***************************************************************************** -void -VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, bool bPrefetch) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT(VIMSBaseValid(ui32Base)); - - ui32Reg = HWREG(ui32Base + VIMS_O_CTL); - ui32Reg &= ~(VIMS_CTL_PREF_EN | VIMS_CTL_ARB_CFG); - if(bRoundRobin) - { - ui32Reg |= VIMS_CTL_ARB_CFG; - } - if(bPrefetch) - { - ui32Reg |= VIMS_CTL_PREF_EN; - } - - // Set the Arbitration and prefetch mode. - HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; -} - -//***************************************************************************** -// -// Set the operational mode of the VIMS -// -//***************************************************************************** -void -VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT(VIMSBaseValid(ui32Base)); - - ASSERT((ui32Mode == VIMS_MODE_DISABLED) || - (ui32Mode == VIMS_MODE_ENABLED) || - (ui32Mode == VIMS_MODE_OFF)); - - // Set the mode. - ui32Reg = HWREG(ui32Base + VIMS_O_CTL); - ui32Reg &= ~VIMS_CTL_MODE_M; - ui32Reg |= (ui32Mode & VIMS_CTL_MODE_M); - - HWREG(ui32Base + VIMS_O_CTL) = ui32Reg; -} - -//***************************************************************************** -// -// Get the current operational mode of the VIMS. -// -//***************************************************************************** -uint32_t -VIMSModeGet(uint32_t ui32Base) -{ - uint32_t ui32Reg; - - // Check the arguments. - ASSERT(VIMSBaseValid(ui32Base)); - - ui32Reg = HWREG(ui32Base + VIMS_O_STAT); - if(ui32Reg & VIMS_STAT_MODE_CHANGING) - { - return (VIMS_MODE_CHANGING); - } - else - { - return (ui32Reg & VIMS_STAT_MODE_M); - } -} - -//***************************************************************************** -// -// Safe setting of new VIMS mode -// - Function might be blocking -// - Can be called for any mode change (also if actually not changing mode) -// -//***************************************************************************** -void -VIMSModeSafeSet( uint32_t ui32Base, uint32_t ui32NewMode, bool blocking ) -{ - uint32_t currentMode; - - // Check the arguments. - ASSERT(VIMSBaseValid(ui32Base)); - ASSERT((ui32NewMode == VIMS_MODE_DISABLED) || - (ui32NewMode == VIMS_MODE_ENABLED) || - (ui32NewMode == VIMS_MODE_OFF)); - - // Make sure that only the mode bits are set in the input parameter - // (done just for security since it is critical to the code flow) - ui32NewMode &= VIMS_CTL_MODE_M; - - // Wait for any pending change to complete and get current VIMS mode - // (This is a blocking point but will typically only be a blocking point - // only if mode is changed multiple times with blocking=0) - do { - currentMode = VIMSModeGet( ui32Base ); - } while ( currentMode == VIMS_MODE_CHANGING ); - - // First check that it actually is a mode change request - if ( ui32NewMode != currentMode ) { - // Set new mode - VIMSModeSet( ui32Base, ui32NewMode ); - - // Wait for final mode change to complete - if blocking is requested - if ( blocking ) { - while ( HWREGBITW( VIMS_BASE + VIMS_O_STAT, VIMS_STAT_MODE_CHANGING_BITN )) { - // Do nothing - wait for change to complete. - } - } - } -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h deleted file mode 100644 index 7a35af53d5a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/vims.h +++ /dev/null @@ -1,371 +0,0 @@ -/****************************************************************************** -* Filename: vims.h -* Revised: 2016-10-06 17:21:09 +0200 (Thu, 06 Oct 2016) -* Revision: 47343 -* -* Description: Defines and prototypes for the VIMS. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup system_control_group -//! @{ -//! \addtogroup vims_api -//! @{ -// -//***************************************************************************** - -#ifndef __VIMS_H__ -#define __VIMS_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_vims.h" -#include "debug.h" - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// This section renames all functions that are not "static inline", so that -// calling these functions will default to implementation in flash. At the end -// of this file a second renaming will change the defaults to implementation in -// ROM for available functions. -// -// To force use of the implementation in flash, e.g. for debugging: -// - Globally: Define DRIVERLIB_NOROM at project level -// - Per function: Use prefix "NOROM_" when calling the function -// -//***************************************************************************** -#if !defined(DOXYGEN) - #define VIMSConfigure NOROM_VIMSConfigure - #define VIMSModeSet NOROM_VIMSModeSet - #define VIMSModeGet NOROM_VIMSModeGet - #define VIMSModeSafeSet NOROM_VIMSModeSafeSet -#endif - -//***************************************************************************** -// -// Values that can be passed to VIMSModeSet() as the ui32IntFlags parameter, -// and returned from VIMSModeGet(). -// -//***************************************************************************** -#define VIMS_MODE_CHANGING 0x4 // VIMS mode is changing now and VIMS_MODE - // can not be changed at moment. -#define VIMS_MODE_DISABLED (VIMS_CTL_MODE_GPRAM) // Disabled mode (GPRAM enabled). -#define VIMS_MODE_ENABLED (VIMS_CTL_MODE_CACHE) // Enabled mode, only USERCODE is cached. -#define VIMS_MODE_OFF (VIMS_CTL_MODE_OFF) // VIMS Cache RAM is off - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -#ifdef DRIVERLIB_DEBUG -//***************************************************************************** -// -//! \brief Checks a VIMS base address. -//! -//! This function determines if the VIMS base address is valid. -//! -//! \param ui32Base is the base address of the VIMS. -//! -//! \return Returns \c true if the base address is valid and \c false -//! otherwise. -// -//***************************************************************************** -static bool -VIMSBaseValid(uint32_t ui32Base) -{ - return(ui32Base == VIMS_BASE); -} -#endif - -//***************************************************************************** -// -//! \brief Configures the VIMS. -//! -//! This function sets general control settings of the VIMS system. -//! -//! \note The VIMS mode must be set using the \ref VIMSModeSet() call. -//! -//! \param ui32Base is the base address of the VIMS. -//! \param bRoundRobin specifies the arbitration method. -//! - \c true : Round Robin arbitration between the two available read/write interfaces -//! (i.e. Icode/Dcode and Sysbus) is to be used. -//! - \c false : Strict arbitration will be used, where Icode/Dcode -//! is preferred over the Sysbus. -//! \param bPrefetch specifies if prefetching is to be used. -//! - \c true : Cache is to prefetch tag data for the following address. -//! - \c false : No prefetch. -//! -//! \return None -//! -//! \sa \ref VIMSModeSet() -// -//***************************************************************************** -extern void VIMSConfigure(uint32_t ui32Base, bool bRoundRobin, - bool bPrefetch); - -//***************************************************************************** -// -//! \brief Set the operational mode of the VIMS. -//! -//! This function sets the operational mode of the VIMS. -//! -//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. -//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). -//! The GP RAM will not be operational (read/write will result in bus fault). -//! The Cache will not be operational. -//! Reads and writes to flash will be uncached. -//! After a short delay (approx. 1029 clock cycles) the VIMS will -//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). -//! -//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is -//! accessible: -//! The GP RAM will be accessible. -//! The Cache will not be operational. -//! Reads from flash will be uncached. -//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). -//! -//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. -//! The GP RAM will not be operational (read/write will result in bus fault). -//! The Cache will be operational for SYSCODE space. -//! Reads from flash in USERCODE space will be uncached. -//! -//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. -//! -//! \note The VIMS must be invalidated when switching mode. -//! This is done by setting VIMS_MODE_OFF before setting any new mode. -//! This is automatically handled in \ref VIMSModeSafeSet() -//! -//! \note It is highly recommended that the VIMS is put in disabled mode before -//! \b writing to flash, since the cache will not be updated nor invalidated -//! by flash writes. The line buffers should also be disabled when updating the -//! flash. Once \ref VIMSModeSet() is used to set the VIMS in -//! \ref VIMS_MODE_CHANGING mode, the user should check using -//! \ref VIMSModeGet() when the mode switches to \ref VIMS_MODE_DISABLED. Only when -//! the mode has changed the cache has been completely invalidated. -//! -//! \note Access from System Bus is never cached. Only access through ICODE -//! DCODE bus from the System CPU is cached. -//! -//! \param ui32Base is the base address of the VIMS. -//! \param ui32Mode is the operational mode. -//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) -//! - \ref VIMS_MODE_ENABLED (CACHE mode) -//! - \ref VIMS_MODE_OFF -//! -//! \return None -//! -//! \sa \ref VIMSModeGet() and \ref VIMSModeSafeSet() -// -//***************************************************************************** -extern void VIMSModeSet(uint32_t ui32Base, uint32_t ui32Mode); - -//***************************************************************************** -// -//! \brief Get the current operational mode of the VIMS. -//! -//! This function returns the operational mode of the VIMS. -//! -//! \param ui32Base is the base address of the VIMS. -//! -//! \return Returns one of: -//! - \ref VIMS_MODE_CHANGING -//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) -//! - \ref VIMS_MODE_ENABLED (CACHE mode) -//! - \ref VIMS_MODE_OFF -//! -//! \sa \ref VIMSModeSet() -// -//***************************************************************************** -extern uint32_t VIMSModeGet(uint32_t ui32Base); - -//***************************************************************************** -// -//! \brief Set the operational mode of the VIMS in a safe sequence. -//! -//! This function sets the operational mode of the VIMS in a safe sequence -//! -//! Upon reset the VIMS will be in \ref VIMS_MODE_CHANGING mode. -//! In this mode the VIMS will initialize the cache (GP) RAM (to all zeros). -//! The GP RAM will not be operational (read/write will result in bus fault). -//! The Cache will not be operational (read/write to flash will be uncached). -//! After a short delay (approx. 1029 clock cycles) the VIMS will -//! automatically switch mode to \ref VIMS_MODE_DISABLED (GPRAM enabled). -//! -//! In \ref VIMS_MODE_DISABLED mode, the cache is disabled but the GP RAM is -//! accessible: -//! The GP RAM will be accessible. -//! The Cache will not be operational. -//! Reads from flash will be uncached. -//! From this mode, the VIMS may be put in \ref VIMS_MODE_ENABLED (CACHE mode). -//! -//! In \ref VIMS_MODE_ENABLED mode, the cache is enabled for \b USERCODE space. -//! The GP RAM will not be operational (read/write will result in bus fault). -//! The Cache will be operational for SYSCODE space. -//! Reads from flash in USERCODE space will be uncached. -//! -//! In \ref VIMS_MODE_OFF the cache RAM is off to conserve power. -//! -//! \note The VIMS must be invalidated when switching mode. -//! This is done by setting VIMS_MODE_OFF before setting any new mode. -//! This is automatically handled in this function. -//! -//! \note It is highly recommended that the VIMS is put in disabled mode before -//! \b writing to flash, since the cache will not be updated nor invalidated -//! by flash writes. The line buffers should also be disabled when updating the -//! flash. -//! -//! \note Access from System Bus is never cached. Only access through ICODE -//! DCODE bus from the System CPU is cached. -//! -//! \param ui32Base is the base address of the VIMS. -//! \param ui32NewMode is the new operational mode: -//! - \ref VIMS_MODE_DISABLED (GPRAM enabled) -//! - \ref VIMS_MODE_ENABLED (CACHE mode) -//! - \ref VIMS_MODE_OFF -//! \param blocking shall be set to TRUE if further code execution shall be -//! blocked (delayed) until mode change is completed. -//! -//! \return None -//! -//! \sa \ref VIMSModeSet() and \ref VIMSModeGet() -// -//***************************************************************************** -extern void VIMSModeSafeSet( uint32_t ui32Base , - uint32_t ui32NewMode , - bool blocking ); - -//***************************************************************************** -// -//! \brief Disable VIMS linebuffers. -//! -//! Linebuffers should only be disabled when attempting to update the flash, to -//! ensure that the content of the buffers is not stale. As soon as flash is -//! updated the linebuffers should be reenabled. Failing to enable -//! will have a performance impact. -//! -//! \param ui32Base is the base address of the VIMS. -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -VIMSLineBufDisable(uint32_t ui32Base) -{ - // Disable line buffers - HWREG(ui32Base + VIMS_O_CTL) |= VIMS_CTL_IDCODE_LB_DIS_M | - VIMS_CTL_SYSBUS_LB_DIS_M; -} - -//***************************************************************************** -// -//! \brief Enable VIMS linebuffers. -//! -//! Linebuffers should only be disabled when attempting to update the flash, to -//! ensure that the content of the buffers is not stale. As soon as flash is -//! updated the linebuffers should be reenabled. Failing to enable -//! will have a performance impact. -//! -//! \param ui32Base is the base address of the VIMS. -//! -//! \return None. -// -//***************************************************************************** -__STATIC_INLINE void -VIMSLineBufEnable(uint32_t ui32Base) -{ - // Enable linebuffers - HWREG(ui32Base + VIMS_O_CTL) &= ~(VIMS_CTL_IDCODE_LB_DIS_M | - VIMS_CTL_SYSBUS_LB_DIS_M); -} - -//***************************************************************************** -// -// Support for DriverLib in ROM: -// Redirect to implementation in ROM when available. -// -//***************************************************************************** -#if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN) - #include "../driverlib/rom.h" - #ifdef ROM_VIMSConfigure - #undef VIMSConfigure - #define VIMSConfigure ROM_VIMSConfigure - #endif - #ifdef ROM_VIMSModeSet - #undef VIMSModeSet - #define VIMSModeSet ROM_VIMSModeSet - #endif - #ifdef ROM_VIMSModeGet - #undef VIMSModeGet - #define VIMSModeGet ROM_VIMSModeGet - #endif - #ifdef ROM_VIMSModeSafeSet - #undef VIMSModeSafeSet - #define VIMSModeSafeSet ROM_VIMSModeSafeSet - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __VIMS_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.c deleted file mode 100644 index 2cac28c38e9..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.c +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************** -* Filename: wdt.c -* Revised: 2016-09-19 10:36:17 +0200 (Mon, 19 Sep 2016) -* Revision: 47179 -* -* Description: Driver for the Watchdog Timer. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#include - -// See watchdog.h for implementation diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h deleted file mode 100644 index 3d8de36846b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog.h +++ /dev/null @@ -1,520 +0,0 @@ -/****************************************************************************** -* Filename: wdt.h -* Revised: 2017-05-23 12:08:52 +0200 (Tue, 23 May 2017) -* Revision: 49048 -* -* Description: Defines and prototypes for the Watchdog Timer. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup peripheral_group -//! @{ -//! \addtogroup wdt_api -//! @{ -// -//***************************************************************************** - -#ifndef __WDT_H__ -#define __WDT_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include "../inc/hw_types.h" -#include "../inc/hw_ints.h" -#include "../inc/hw_memmap.h" -#include "../inc/hw_wdt.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOCK register. -// -//***************************************************************************** -#define WATCHDOG_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WATCHDOG_LOCK_LOCKED 0x00000001 // Locked -#define WATCHDOG_LOCK_UNLOCK 0x1ACCE551 // Unlocks the Watchdog Timer - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and -// WDT_MIS registers. -// -//***************************************************************************** -#define WATCHDOG_INT_TIMEOUT 0x00000001 // Watchdog timer expired - -//***************************************************************************** -// -// The type of interrupt that can be generated by the watchdog. -// -//***************************************************************************** -#define WATCHDOG_INT_TYPE_INT 0x00000000 -#define WATCHDOG_INT_TYPE_NMI 0x00000004 - -//***************************************************************************** -// -// API Functions and prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Determines if the watchdog timer is enabled. -//! -//! This function checks to see if the watchdog timer is enabled. -//! -//! \return Returns status of Watchdog Timer: -//! - \c true : Watchdog timer is enabled. -//! - \c false : Watchdog timer is disabled. -// -//***************************************************************************** -__STATIC_INLINE bool -WatchdogRunning(void) -{ - // See if the watchdog timer module is enabled, and return. - return((HWREG(WDT_BASE + WDT_O_CTL) & WDT_CTL_INTEN) ? true : false); -} - -//***************************************************************************** -// -//! \brief Enables the watchdog timer. -//! -//! This function enables the watchdog timer counter and interrupt. -//! -//! Once enabled, the watchdog interrupt can only be disabled by a hardware reset. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None -//! -//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogEnable(void) -{ - // Enable the watchdog timer module. - HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTEN_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Enables the watchdog timer reset. -//! -//! This function enables the capability of the watchdog timer to issue a reset -//! to the processor after a second timeout condition. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None -//! -//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogResetEnable(void) -{ - // Enable the watchdog reset. - HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Disables the watchdog timer reset. -//! -//! This function disables the capability of the watchdog timer to issue a -//! reset to the processor after a second timeout condition. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \return None -//! -//! \sa \ref WatchdogLock(), \ref WatchdogUnlock() -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogResetDisable(void) -{ - // Disable the watchdog reset. - HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_RESEN_BITN) = 0; -} - -//***************************************************************************** -// -//! \brief Enables the watchdog timer lock mechanism. -//! -//! This function locks out write access to the watchdog timer configuration -//! registers. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogLock(void) -{ - // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK - // register causes the lock to go into effect. - HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_LOCKED; -} - -//***************************************************************************** -// -//! \brief Disables the watchdog timer lock mechanism. -//! -//! This function enables write access to the watchdog timer configuration -//! registers. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogUnlock(void) -{ - // Unlock watchdog register writes. - HWREG(WDT_BASE + WDT_O_LOCK) = WATCHDOG_LOCK_UNLOCK; -} - -//***************************************************************************** -// -//! \brief Gets the state of the watchdog timer lock mechanism. -//! -//! This function returns the lock state of the watchdog timer registers. -//! -//! \return Returns state of lock mechanism. -//! - \c true : Watchdog timer registers are locked. -//! - \c false : Registers are not locked. -// -//***************************************************************************** -__STATIC_INLINE bool -WatchdogLockState(void) -{ - // Get the lock state. - return((HWREG(WDT_BASE + WDT_O_LOCK) == WATCHDOG_LOCK_LOCKED) ? - true : false); -} - -//***************************************************************************** -// -//! \brief Sets the watchdog timer reload value. -//! -//! This function configures the value to load into the watchdog timer when the -//! count reaches zero for the first time; if the watchdog timer is running -//! when this function is called, then the value is immediately loaded into the -//! watchdog timer counter. If the \c ui32LoadVal parameter is 0, then an -//! interrupt is immediately generated. -//! -//! \note This function has no effect if the watchdog timer has been locked. -//! -//! \param ui32LoadVal is the load value for the watchdog timer. -//! -//! \return None -//! -//! \sa \ref WatchdogLock(), \ref WatchdogUnlock(), \ref WatchdogReloadGet() -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogReloadSet(uint32_t ui32LoadVal) -{ - // Set the load register. - HWREG(WDT_BASE + WDT_O_LOAD) = ui32LoadVal; -} - -//***************************************************************************** -// -//! \brief Gets the watchdog timer reload value. -//! -//! This function gets the value that is loaded into the watchdog timer when -//! the count reaches zero for the first time. -//! -//! \return None -//! -//! \sa \ref WatchdogReloadSet() -// -//***************************************************************************** -__STATIC_INLINE uint32_t -WatchdogReloadGet(void) -{ - // Get the load register. - return(HWREG(WDT_BASE + WDT_O_LOAD)); -} - -//***************************************************************************** -// -//! \brief Gets the current watchdog timer value. -//! -//! This function reads the current value of the watchdog timer. -//! -//! \return Returns the current value of the watchdog timer. -// -//***************************************************************************** -__STATIC_INLINE uint32_t -WatchdogValueGet(void) -{ - // Get the current watchdog timer register value. - return(HWREG(WDT_BASE + WDT_O_VALUE)); -} - -//***************************************************************************** -// -//! \brief Registers an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table. -//! -//! \note Only use this function if you want to use the dynamic vector table (in SRAM)! -//! -//! This function registers a function as the interrupt handler for a specific -//! interrupt and enables the corresponding interrupt in the interrupt controller. -//! -//! The watchdog timer interrupt must be enabled via \ref WatchdogIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source via -//! \ref WatchdogIntClear(). -//! -//! \note This function registers the standard watchdog interrupt handler. To -//! register the NMI watchdog handler, use \ref IntRegister() to register the -//! handler for the \b INT_NMI_FAULT interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! watchdog timer interrupt occurs. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogIntRegister(void (*pfnHandler)(void)) -{ - // Register the interrupt handler. - IntRegister(INT_WDT_IRQ, pfnHandler); - - // Enable the watchdog timer interrupt. - IntEnable(INT_WDT_IRQ); -} - -//***************************************************************************** -// -//! \brief Unregisters an interrupt handler for the watchdog timer interrupt in the dynamic interrupt table. -//! -//! This function does the actual unregistering of the interrupt handler. This -//! function clears the handler to be called when a watchdog timer interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \note This function registers the standard watchdog interrupt handler. To -//! register the NMI watchdog handler, use \ref IntRegister() to register the -//! handler for the \b INT_NMI_FAULT interrupt. -//! -//! \return None -//! -//! \sa \ref IntRegister() for important information about registering interrupt -//! handlers. -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogIntUnregister(void) -{ - // Disable the interrupt. - IntDisable(INT_WDT_IRQ); - - // Unregister the interrupt handler. - IntUnregister(INT_WDT_IRQ); -} - -//***************************************************************************** -// -//! \brief Enables the watchdog timer. -//! -//! This function enables the watchdog timer interrupt by calling \ref WatchdogEnable(). -//! -//! \return None -//! -//! \sa \ref WatchdogEnable() -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogIntEnable(void) -{ - // Enable the Watchdog interrupt. - WatchdogEnable(); -} - -//***************************************************************************** -// -//! \brief Gets the current watchdog timer interrupt status. -//! -//! This function returns the interrupt status for the watchdog timer module. -//! -//! \return Returns the interrupt status. -//! - 1 : Watchdog time-out has occurred. -//! - 0 : Watchdog time-out has not occurred. -//! -//! \sa \ref WatchdogIntClear(); -// -//***************************************************************************** -__STATIC_INLINE uint32_t -WatchdogIntStatus(void) -{ - // Return either the interrupt status or the raw interrupt status as - // requested. - return(HWREG(WDT_BASE + WDT_O_RIS)); -} - -//***************************************************************************** -// -//! \brief Clears the watchdog timer interrupt. -//! -//! The watchdog timer interrupt source is cleared, so that it no longer -//! asserts. -//! -//! \note Due to write buffers and synchronizers in the system it may take several -//! clock cycles from a register write clearing an event in a module and until the -//! event is actually cleared in the NVIC of the system CPU. It is recommended to -//! clear the event source early in the interrupt service routine (ISR) to allow -//! the event clear to propagate to the NVIC before returning from the ISR. -//! At the same time, an early event clear allows new events of the same type to be -//! pended instead of ignored if the event is cleared later in the ISR. -//! It is the responsibility of the programmer to make sure that enough time has passed -//! before returning from the ISR to avoid false re-triggering of the cleared event. -//! A simple, although not necessarily optimal, way of clearing an event before -//! returning from the ISR is: -//! -# Write to clear event (interrupt source). (buffered write) -//! -# Dummy read from the event source module. (making sure the write has propagated) -//! -# Wait two system CPU clock cycles (user code or two NOPs). (allowing cleared event to propagate through any synchronizers) -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogIntClear(void) -{ - // Clear the interrupt source. - HWREG(WDT_BASE + WDT_O_ICR) = WATCHDOG_INT_TIMEOUT; -} - -//***************************************************************************** -// -//! \brief Sets the type of interrupt generated by the watchdog. -//! -//! This function sets the type of interrupt that is generated if the watchdog -//! timer expires. -//! -//! When configured to generate an NMI, the watchdog interrupt must still be -//! enabled with \ref WatchdogIntEnable(), and it must still be cleared inside the -//! NMI handler with \ref WatchdogIntClear(). -//! -//! \param ui32Type is the type of interrupt to generate. -//! - \ref WATCHDOG_INT_TYPE_INT : Generate a standard interrupt (default). -//! - \ref WATCHDOG_INT_TYPE_NMI : Generate a non-maskable interrupt (NMI). -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogIntTypeSet(uint32_t ui32Type) -{ - // Check the arguments. - ASSERT((ui32Type == WATCHDOG_INT_TYPE_INT) || - (ui32Type == WATCHDOG_INT_TYPE_NMI)); - - // Set the interrupt type. - HWREGBITW(WDT_BASE + WDT_O_CTL, WDT_CTL_INTTYPE_BITN) = (ui32Type == WATCHDOG_INT_TYPE_INT)? 0 : 1; -} - -//***************************************************************************** -// -//! \brief Enables stalling of the watchdog timer during debug events. -//! -//! This function allows the watchdog timer to stop counting when the processor -//! is stopped by the debugger. By doing so, the watchdog is prevented from -//! expiring and resetting the system (if reset is enabled). The watchdog instead expires -//! after the appropriate number of processor cycles have been executed while -//! debugging (or at the appropriate time after the processor has been -//! restarted). -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogStallEnable(void) -{ - // Enable timer stalling. - HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 1; -} - -//***************************************************************************** -// -//! \brief Disables stalling of the watchdog timer during debug events. -//! -//! This function disables the debug mode stall of the watchdog timer. By -//! doing so, the watchdog timer continues to count regardless of the processor -//! debug state. -//! -//! \return None -// -//***************************************************************************** -__STATIC_INLINE void -WatchdogStallDisable(void) -{ - // Disable timer stalling. - HWREGBITW(WDT_BASE + WDT_O_TEST, WDT_TEST_STALL_BITN) = 0; -} - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __WDT_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h deleted file mode 100644 index ef1f2399524..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/watchdog_doc.h +++ /dev/null @@ -1,121 +0,0 @@ -/****************************************************************************** -* Filename: watchdog_doc.h -* Revised: 2018-02-09 15:45:36 +0100 (Fri, 09 Feb 2018) -* Revision: 51470 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -//! \addtogroup wdt_api -//! @{ -//! \section sec_wdt Introduction -//! -//! The Watchdog Timer (WDT) allows the application to regain control if the system stalls due to -//! unexpected software behavior. The WDT can generate a normal interrupt or a non-maskable interrupt -//! on the first time-out and a system reset on the following time-out if the application fails to -//! restart the WDT. -//! -//! WDT has the following features: -//! - 32-bit down counter with a configurable load register. -//! - Configurable interrupt generation logic with interrupt masking and optional NMI function. -//! - Optional reset generation. -//! - Register protection from runaway software (lock). -//! - User-enabled stalling when the system CPU asserts the CPU Halt flag during debug. -//! -//! The WDT runs at system HF clock divided by 32; however, when in powerdown it runs at -//! LF clock (32 kHz) - if the LF clock to the MCU domain is enabled. -//! -//! If application does not restart the WDT, using \ref WatchdogIntClear(), before a time-out: -//! - At the first time-out the WDT asserts the interrupt, reloads the 32-bit counter with the load -//! value, and resumes counting down from that value. -//! - If the WDT counts down to zero again before the application clears the interrupt, and the -//! reset signal has been enabled, the WDT asserts its reset signal to the system. -//! -//! \note By default, a "warm reset" triggers a pin reset and thus reboots the device. -//! -//! A reset caused by the WDT can be detected as a "warm reset" using \ref SysCtrlResetSourceGet(). -//! However, it is not possible to detect which of the warm reset sources that caused the reset. -//! -//! Typical use case: -//! - Use \ref WatchdogIntTypeSet() to select either standard interrupt or non-maskable interrupt on -//! first time-out. -//! - The application must implement an interrupt handler for the selected interrupt type. If -//! application uses the \e static vector table (see startup_.c) the interrupt -//! handlers for standard interrupt and non-maskable interrupt are named WatchdogIntHandler() -//! and NmiSR() respectively. For more information about \e static and \e dynamic vector table, -//! see \ref sec_interrupt_table. -//! - Use \ref WatchdogResetEnable() to enable reset on second time-out. -//! - Use \ref WatchdogReloadSet() to set (re)load value of the counter. -//! - Use \ref WatchdogEnable() to start the WDT counter. The WDT counts down from the load value. -//! - Use \ref WatchdogLock() to lock WDT configuration to prevent unintended re-configuration. -//! - Application must use \ref WatchdogIntClear() to restart the counter before WDT times out. -//! - If application does not restart the counter before it reaches zero (times out) the WDT asserts -//! the selected type of interrupt, reloads the counter, and starts counting down again. -//! - The interrupt handler triggered by the first time-out can be used to log debug information -//! or try to enter a safe "pre-reset" state in order to have a more graceful reset when the WDT -//! times out the second time. -//! - It is \b not recommended that the WDT interrupt handler clears the WDT interrupt and thus -//! reloads the WDT counter. This means that the WDT interrupt handler never returns. -//! - If the application does not clear the WDT interrupt and the WDT times out when the interrupt -//! is still asserted then WDT triggers a reset (if enabled). -//! -//! \section sec_wdt_api API -//! -//! The API functions can be grouped like this: -//! -//! Watchdog configuration: -//! - \ref WatchdogIntTypeSet() -//! - \ref WatchdogResetEnable() -//! - \ref WatchdogResetDisable() -//! - \ref WatchdogReloadSet() -//! - \ref WatchdogEnable() -//! -//! Status: -//! - \ref WatchdogRunning() -//! - \ref WatchdogValueGet() -//! - \ref WatchdogReloadGet() -//! - \ref WatchdogIntStatus() -//! -//! Interrupt configuration: -//! - \ref WatchdogIntEnable() -//! - \ref WatchdogIntClear() -//! - \ref WatchdogIntRegister() -//! - \ref WatchdogIntUnregister() -//! -//! Register protection: -//! - \ref WatchdogLock() -//! - \ref WatchdogLockState() -//! - \ref WatchdogUnlock() -//! -//! Stall configuration for debugging: -//! - \ref WatchdogStallDisable() -//! - \ref WatchdogStallEnable() -//! -//! @} diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h deleted file mode 100644 index 9e5a815870e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/asmdefs.h +++ /dev/null @@ -1,151 +0,0 @@ -/****************************************************************************** -* Filename: asmdefs.h -* Revised: 2015-06-05 14:39:10 +0200 (Fri, 05 Jun 2015) -* Revision: 43803 -* -* Description: Macros to allow assembly code be portable among tool chains. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __ASMDEFS_H__ -#define __ASMDEFS_H__ - -//***************************************************************************** -// -// The defines required for EW-ARM. -// -//***************************************************************************** -#ifdef __IAR_SYSTEMS_ICC__ - -// -// Section headers. -// -#define __LIBRARY__ module -#define __TEXT__ rseg CODE:CODE(2) -#define __DATA__ rseg DATA:DATA(2) -#define __BSS__ rseg DATA:DATA(2) -#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) - -// -// Assembler mnemonics. -// -#define __ALIGN__ alignrom 2 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ thumb -#define __WORD__ dcd -#define __INLINE_DATA__ data - -#endif // __IAR_SYSTEMS_ICC__ - -//***************************************************************************** -// -// The defines required for GCC. -// -//***************************************************************************** -#if defined(__GNUC__) - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler mnemonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // __GNUC__ - -//***************************************************************************** -// -// The defines required for RV-MDK. -// -//***************************************************************************** -#if defined(__CC_ARM) - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - thumb - require8 - preserve8 - -// -// Section headers. -// -#define __LIBRARY__ ; -#define __TEXT__ area ||.text||, code, readonly, align=2 -#define __DATA__ area ||.data||, data, align=2 -#define __BSS__ area ||.bss||, noinit, align=2 -#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 - -// -// Assembler mnemonics. -// -#define __ALIGN__ align 4 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ -#define __WORD__ dcd -#define __INLINE_DATA__ - -#endif // __CC_ARM - - -#endif // __ASMDEF_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h deleted file mode 100644 index b14a5f6b0e1..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi.h +++ /dev/null @@ -1,1182 +0,0 @@ -/****************************************************************************** -* Filename: hw_adi.h -* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) -* Revision: 42365 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_ADI_H__ -#define __HW_ADI_H__ - -//***************************************************************************** -// -// This file contains macros for controlling the ADI master and -// accessing ADI slave registers via the ADI Master. -// There are 3 categories of macros in this file: -// - macros that provide an offset to a register -// located within the DDI Master itself. -// - macros that define bits or bitfields -// within the DDI Master Registers. -// - macros that provide an "instruction offset" -// that are used when accessing a ADI Slave. -// -// The macros that that provide ADI Master register offsets and -// define bits and bitfields for those registers are the typical -// macros that appear in most hw_.h header files. In -// the following example ADI_O_SLAVECONF is a macro for a -// register offset and ADI_SLAVECONF_WAITFORACK is a macro for -// a bit in that register. This example code will set the WAITFORACK -// bit in register ADI_O_SLAVECONF of the ADI Master. (Note: this -// access the Master not the Slave). -// -// HWREG(ADI3_BASE + ADI_O_SLAVECONF) |= ADI_SLAVECONF_WAITFORACK; -// -// The "instruction offset" macros are used to pass an instruction to -// the ADI Master when accessing ADI slave registers. These macros are -// only used when accessing ADI Slave Registers. (Remember ADI -// Master Registers are accessed normally). -// -// The instructions supported when accessing an ADI Slave Register follow: -// - Direct Access to an ADI Slave register. I.e. read or -// write the register. -// - Set the specified bits in a ADI Slave register. -// - Clear the specified bits in a ADI Slave register. -// - Mask write of 4 bits to the a ADI Slave register. -// - Mask write of 8 bits to the a ADI Slave register. -// - Mask write of 16 bits to the a ADI Slave register. -// -// Note: only the "Direct Access" offset should be used when reading -// a ADI Slave register. Only 4-bit reads are supported and 8 bits write are -// supported natively. If accessing wider bitfields, the read/write operation -// will be spread out over a number of transactions. This is hidden for the -// user, but can potentially be very timeconsuming. Especially of running -// on a slow clock. -// -// The generic format of using these macros for a read follows: -// // Read low 8-bits in ADI_SLAVE_OFF -// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); -// -// // Read high 8-bits in ADI_SLAVE_OFF (data[31:16]) -// myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); -// -// Notes: In the above example: -// - ADI_MASTER_BASE is the base address of the ADI Master defined -// in the hw_memmap.h header file. -// - ADI_SLAVE_OFF is the ADI Slave offset defined in the -// hw_.h header file (e.g. hw_adi_3_refsys_top.h for the refsys -// module). -// - ADI_O_DIR is the "instruction offset" macro defined in this -// file that specifies the Direct Access instruction. -// -// Writes can use any of the "instruction macros". -// The following examples do a "direct write" to an ADI Slave register -// ADI_SLAVE_OFF using different size operands: -// -// // ---------- DIRECT WRITES ---------- -// // Write 32-bits aligned -// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x12345678; -// -// // Write 16-bits aligned to high 16-bits then low 16-bits -// // Add 2 to get to high 16-bits. -// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0xabcd; -// HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0xef01; -// -// // Write each byte at ADI_SLAVE_OFF, one at a time. -// // Add 1,2,or 3 to get to bytes 1,2, or 3. -// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x33; -// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 1) = 0x44; -// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0x55; -// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 3) = 0x66; -// -// // ---------- SET/CLR ---------- -// The set and clear functions behave similarly to eachother. Each -// can be performed on an 8-, 16-, or 32-bit operand. -// Examples follow: -// // Set all odd bits in a 32-bit words -// HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_SET) = 0xaaaaaaaa; -// -// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand -// HWREG(DDI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_CLR) = 0x00ff0000; -// -// // Set even bits in byte 2 (data[23:16]) using 8-bit operand -// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + 2 + ADI_O_CLR) = 0x55; -// -// // ---------- MASKED WRITES ---------- -// The mask writes are a bit different. They operate on nibbles, -// bytes, and 16-bit elements. Two operands are required; a 'mask' -// and 'data'; The operands are concatenated and written to the master. -// e.g. the mask and data are combined as follows for a 16 bit masked -// write: -// (mask << 16) | data; -// Examples follow: -// -// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). -// // Byte write is needed. -// HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_MASK4B01) = 0xf7; -// -// // Do an 4 bit masked write of 4 to data[7:4]). -// // Add 1 for next nibble -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + ADI_O_MASK4B01 + 1) = 0xf4; -// -//***************************************************************************** - -//***************************************************************************** -// -// The following are defines for the ADI master instruction offsets. -// -//***************************************************************************** -#define ADI_O_DIR 0x00000000 // Offset for the direct access - // instruction -#define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. -#define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. -#define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. - // Data bit[n] is written if mask - // bit[n] is set ('1'). - // Bits 7:4 are mask. Bits 3:0 are data. - // Requires 'byte' write. -#define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. - // Data bit[n] is written if mask - // bit[n] is set ('1'). Bits 15:8 are - // mask. Bits 7:0 are data. Requires - // 'short' write. -#define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. - // Data bit[n] is written if mask - // bit[n] is set ('1'). Bits 31:16 - // are mask. Bits 15:0 are data. - // Requires 'long' write. - -//***************************************************************************** -// -// The following are defines for the ADI register offsets. -// -//***************************************************************************** -#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register -#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration - -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_SLAVESTAT register. -// -//***************************************************************************** -#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ - // signal. Writing 0 to this bit - // forces a sync with slave, - // ensuring that req will be 0. It - // is recommended to write 0 to - // this register before power down - // of the master. -#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 -#define ADI_SLAVESTAT_DI_REQ_S 1 -#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK - // signal -#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 -#define ADI_SLAVESTAT_DI_ACK_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_SLAVECONF register. -// -//***************************************************************************** -#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer - // accessible when this bit is set. - // (unless sticky_bit_overwrite is - // asserted on top module) -#define ADI_SLAVECONF_CONFLOCK_M \ - 0x00000080 -#define ADI_SLAVECONF_CONFLOCK_S 7 -#define ADI_SLAVECONF_WAITFORACK \ - 0x00000004 // A transaction on the ADI - // interface does not end until ack - // has been received from the slave - // when this bit is set. - -#define ADI_SLAVECONF_WAITFORACK_M \ - 0x00000004 -#define ADI_SLAVECONF_WAITFORACK_S 2 -#define ADI_SLAVECONF_ADICLKSPEED_M \ - 0x00000003 // Sets the period of an ADI - // transactions. All transactions - // takes an even number of clock - // cycles,- ADI clock rising edge - // occurs in the middle of the - // period. Data and ctrl to slave - // is set up in beginning of cycle, - // and data from slave is read in - // after the transaction 00: An ADI - // transaction takes 2 master clock - // cyclkes 01: An ADI transaction - // takes 4 master clock cycles 10: - // And ADI Transaction takes 8 - // master clock cycles 11: An ADI - // transaction takes 16 master - // clock cycles - -#define ADI_SLAVECONF_ADICLKSPEED_S 0 - -//***************************************************************************** -// -// The following are defines pseudo-magic numbers that should go away. -// New code should not use these registers and old code should be ported -// to not use these. -// -//***************************************************************************** -#define ADI_O_DIR03 0x00000000 // Direct access for adi byte - // offsets 0 to 3 -#define ADI_O_DIR47 0x00000004 // Direct access for adi byte - // offsets 4 to 7 -#define ADI_O_DIR811 0x00000008 // Direct access for adi byte - // offsets 8 to 11 -#define ADI_O_DIR1215 0x0000000C // Direct access for adi byte - // offsets 12 to 15 -#define ADI_O_SET03 0x00000010 // Set register for ADI byte - // offsets 0 to 3 -#define ADI_O_SET47 0x00000014 // Set register for ADI byte - // offsets 4 to 7 -#define ADI_O_SET811 0x00000018 // Set register for ADI byte - // offsets 8 to 11 -#define ADI_O_SET1215 0x0000001C // Set register for ADI byte - // offsets 12 to 15 -#define ADI_O_CLR03 0x00000020 // Clear register for ADI byte - // offsets 0 to 3 -#define ADI_O_CLR47 0x00000024 // Clear register for ADI byte - // offsets 4 to 7 -#define ADI_O_CLR811 0x00000028 // Clear register for ADI byte - // offsets 8 to 11 -#define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte - // offsets 12 to 15 -#define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register -#define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration - // register -#define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI - // Registers at byte offsets 0 and - // 1 -#define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI - // Registers at byte offsets 2 and - // 3 -#define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI - // Registers at byte offsets 4 and - // 5 -#define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI - // Registers at byte offsets 6 and - // 7 -#define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI - // Registers at byte offsets 8 and - // 9 -#define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI - // Registers at byte offsets 10 and - // 11 -#define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI - // Registers at byte offsets 12 and - // 13 -#define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI - // Registers at byte offsets 14 and - // 15 -#define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI - // Registers at byte offsets 0 and - // 1 -#define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI - // Registers at byte offsets 2 and - // 3 -#define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI - // Registers at byte offsets 4 and - // 5 -#define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI - // Registers at byte offsets 6 and - // 7 -#define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI - // Registers at byte offsets 8 and - // 9 -#define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI - // Registers at byte offsets 10 and - // 11 -#define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI - // Registers at byte offsets 12 and - // 13 -#define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI - // Registers at byte offsets 14 and - // 15 -#define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI - // Registers at byte offsets 0 and - // 1 -#define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI - // Registers at byte offsets 2 and - // 3 -#define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI - // Registers at byte offsets 4 and - // 5 -#define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI - // Registers at byte offsets 6 and - // 7 -#define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI - // Registers at byte offsets 8 and - // 9 -#define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI - // Registers at byte offsets 10 and - // 11 -#define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI - // Registers at byte offsets 12 and - // 13 -#define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI - // Registers at byte offsets 14 and - // 15 - -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_DIR03 register. -// -//***************************************************************************** -#define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 -#define ADI_DIR03_B3_S 24 -#define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 -#define ADI_DIR03_B2_S 16 -#define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 -#define ADI_DIR03_B1_S 8 -#define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 -#define ADI_DIR03_B0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_DIR47 register. -// -//***************************************************************************** -#define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 -#define ADI_DIR47_B3_S 24 -#define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 -#define ADI_DIR47_B2_S 16 -#define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 -#define ADI_DIR47_B1_S 8 -#define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 -#define ADI_DIR47_B0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_DIR811 register. -// -//***************************************************************************** -#define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register - // 11 -#define ADI_DIR811_B3_S 24 -#define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register - // 10 -#define ADI_DIR811_B2_S 16 -#define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 -#define ADI_DIR811_B1_S 8 -#define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 -#define ADI_DIR811_B0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_DIR1215 register. -// -//***************************************************************************** -#define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register - // 15 -#define ADI_DIR1215_B3_S 24 -#define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register - // 14 -#define ADI_DIR1215_B2_S 16 -#define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register - // 13 -#define ADI_DIR1215_B1_S 8 -#define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register - // 12 -#define ADI_DIR1215_B0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_SET03 register. -// -//***************************************************************************** -#define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the - // corresponding bit in ADI - // register 3. Read returns 0. -#define ADI_SET03_S3_S 24 -#define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the - // corresponding bit in ADI - // register 2. Read returns 0. -#define ADI_SET03_S2_S 16 -#define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the - // corresponding bit in ADI - // register 1. Read returns 0. -#define ADI_SET03_S1_S 8 -#define ADI_SET03_S0_M 0x000000FF // A high bit value will set the - // corresponding bit in ADI - // register 0. Read returns 0. -#define ADI_SET03_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_SET47 register. -// -//***************************************************************************** -#define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the - // corresponding bit in ADI - // register 7. Read returns 0. -#define ADI_SET47_S3_S 24 -#define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the - // corresponding bit in ADI - // register 6. Read returns 0. -#define ADI_SET47_S2_S 16 -#define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the - // corresponding bit in ADI - // register 5. Read returns 0. -#define ADI_SET47_S1_S 8 -#define ADI_SET47_S0_M 0x000000FF // A high bit value will set the - // corresponding bit in ADI - // register 4. Read returns 0. -#define ADI_SET47_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_SET811 register. -// -//***************************************************************************** -#define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the - // corresponding bit in ADI - // register 11. Read returns 0. -#define ADI_SET811_S3_S 24 -#define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the - // corresponding bit in ADI - // register 10. Read returns 0. -#define ADI_SET811_S2_S 16 -#define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the - // corresponding bit in ADI - // register 9. Read returns 0. -#define ADI_SET811_S1_S 8 -#define ADI_SET811_S0_M 0x000000FF // A high bit value will set the - // corresponding bit in ADI - // register 8. Read returns 0. -#define ADI_SET811_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_SET1215 register. -// -//***************************************************************************** -#define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the - // corresponding bit in ADI - // register 15. Read returns 0. -#define ADI_SET1215_S3_S 24 -#define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the - // corresponding bit in ADI - // register 14. Read returns 0. -#define ADI_SET1215_S2_S 16 -#define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the - // corresponding bit in ADI - // register 13. Read returns 0. -#define ADI_SET1215_S1_S 8 -#define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the - // corresponding bit in ADI - // register 12. Read returns 0. -#define ADI_SET1215_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_CLR03 register. -// -//***************************************************************************** -#define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the - // corresponding bit in ADI - // register 3 -#define ADI_CLR03_S3_S 24 -#define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the - // corresponding bit in ADI - // register 2 -#define ADI_CLR03_S2_S 16 -#define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the - // corresponding bit in ADI - // register 1 -#define ADI_CLR03_S1_S 8 -#define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the - // corresponding bit in ADI - // register 0 -#define ADI_CLR03_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_CLR47 register. -// -//***************************************************************************** -#define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the - // corresponding bit in ADI - // register 7 -#define ADI_CLR47_S3_S 24 -#define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the - // corresponding bit in ADI - // register 6 -#define ADI_CLR47_S2_S 16 -#define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the - // corresponding bit in ADI - // register 5 -#define ADI_CLR47_S1_S 8 -#define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the - // corresponding bit in ADI - // register 4 -#define ADI_CLR47_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_CLR811 register. -// -//***************************************************************************** -#define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the - // corresponding bit in ADI - // register 11 -#define ADI_CLR811_S3_S 24 -#define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the - // corresponding bit in ADI - // register 10 -#define ADI_CLR811_S2_S 16 -#define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the - // corresponding bit in ADI - // register 9 -#define ADI_CLR811_S1_S 8 -#define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the - // corresponding bit in ADI - // register 8 -#define ADI_CLR811_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_CLR1215 register. -// -//***************************************************************************** -#define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the - // corresponding bit in ADI - // register 15 -#define ADI_CLR1215_S3_S 24 -#define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the - // corresponding bit in ADI - // register 14 -#define ADI_CLR1215_S2_S 16 -#define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the - // corresponding bit in ADI - // register 13 -#define ADI_CLR1215_S1_S 8 -#define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the - // corresponding bit in ADI - // register 12 -#define ADI_CLR1215_S0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_SLAVESTAT register. -// -//***************************************************************************** -#define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ - // signal. Writing 0 to this bit - // forces a sync with slave, - // ensuring that req will be 0. It - // is recommended to write 0 to - // this register before power down - // of the master. -#define ADI_SLAVESTAT_DI_REQ_M 0x00000002 -#define ADI_SLAVESTAT_DI_REQ_S 1 -#define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK - // signal -#define ADI_SLAVESTAT_DI_ACK_M 0x00000001 -#define ADI_SLAVESTAT_DI_ACK_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_SLAVECONF register. -// -//***************************************************************************** -#define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer - // accessible when this bit is set. - // (unless sticky_bit_overwrite is - // asserted on top module) -#define ADI_SLAVECONF_CONFLOCK_M \ - 0x00000080 -#define ADI_SLAVECONF_CONFLOCK_S 7 -#define ADI_SLAVECONF_WAITFORACK \ - 0x00000004 // A transaction on the ADI - // interface does not end until ack - // has been received from the slave - // when this bit is set. - -#define ADI_SLAVECONF_WAITFORACK_M \ - 0x00000004 -#define ADI_SLAVECONF_WAITFORACK_S 2 -#define ADI_SLAVECONF_ADICLKSPEED_M \ - 0x00000003 // Sets the period of an ADI - // transactions. All transactions - // takes an even number of clock - // cycles,- ADI clock rising edge - // occurs in the middle of the - // period. Data and ctrl to slave - // is set up in beginning of cycle, - // and data from slave is read in - // after the transaction 00: An ADI - // transaction takes 2 master clock - // cyclkes 01: An ADI transaction - // takes 4 master clock cycles 10: - // And ADI Transaction takes 8 - // master clock cycles 11: An ADI - // transaction takes 16 master - // clock cycles - -#define ADI_SLAVECONF_ADICLKSPEED_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK4B01 register. -// -//***************************************************************************** -#define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 1 -#define ADI_MASK4B01_M1H_S 28 -#define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 1, - only bits selected - // by mask M1H will be affected by - // access -#define ADI_MASK4B01_D1H_S 24 -#define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 1 -#define ADI_MASK4B01_M1L_S 20 -#define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 1, - only bits selected - // by mask M1L will be affected by - // access -#define ADI_MASK4B01_D1L_S 16 -#define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 0 -#define ADI_MASK4B01_M0H_S 12 -#define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 0, - only bits selected - // by mask M0H will be affected by - // access -#define ADI_MASK4B01_D0H_S 8 -#define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 0 -#define ADI_MASK4B01_M0L_S 4 -#define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 0, - only bits selected - // by mask M0L will be affected by - // access -#define ADI_MASK4B01_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK4B23 register. -// -//***************************************************************************** -#define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 3 -#define ADI_MASK4B23_M1H_S 28 -#define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 3, - only bits selected - // by mask M1H will be affected by - // access -#define ADI_MASK4B23_D1H_S 24 -#define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 3 -#define ADI_MASK4B23_M1L_S 20 -#define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 3, - only bits selected - // by mask M1L will be affected by - // access -#define ADI_MASK4B23_D1L_S 16 -#define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 2 -#define ADI_MASK4B23_M0H_S 12 -#define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 2, - only bits selected - // by mask M0H will be affected by - // access -#define ADI_MASK4B23_D0H_S 8 -#define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 2 -#define ADI_MASK4B23_M0L_S 4 -#define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 2, - only bits selected - // by mask M0L will be affected by - // access -#define ADI_MASK4B23_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK4B45 register. -// -//***************************************************************************** -#define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 5 -#define ADI_MASK4B45_M1H_S 28 -#define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 5, - only bits selected - // by mask M1H will be affected by - // access -#define ADI_MASK4B45_D1H_S 24 -#define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 5 -#define ADI_MASK4B45_M1L_S 20 -#define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 5, - only bits selected - // by mask M1L will be affected by - // access -#define ADI_MASK4B45_D1L_S 16 -#define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 4 -#define ADI_MASK4B45_M0H_S 12 -#define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 4, - only bits selected - // by mask M0H will be affected by - // access -#define ADI_MASK4B45_D0H_S 8 -#define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 4 -#define ADI_MASK4B45_M0L_S 4 -#define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 4, - only bits selected - // by mask M0L will be affected by - // access -#define ADI_MASK4B45_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK4B67 register. -// -//***************************************************************************** -#define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 7 -#define ADI_MASK4B67_M1H_S 28 -#define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 7, - only bits selected - // by mask M1H will be affected by - // access -#define ADI_MASK4B67_D1H_S 24 -#define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 7 -#define ADI_MASK4B67_M1L_S 20 -#define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 7, - only bits selected - // by mask M1L will be affected by - // access -#define ADI_MASK4B67_D1L_S 16 -#define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 6 -#define ADI_MASK4B67_M0H_S 12 -#define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 6, - only bits selected - // by mask M0H will be affected by - // access -#define ADI_MASK4B67_D0H_S 8 -#define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 6 -#define ADI_MASK4B67_M0L_S 4 -#define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 6, - only bits selected - // by mask M0L will be affected by - // access -#define ADI_MASK4B67_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK4B89 register. -// -//***************************************************************************** -#define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 9 -#define ADI_MASK4B89_M1H_S 28 -#define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 9, - only bits selected - // by mask M1H will be affected by - // access -#define ADI_MASK4B89_D1H_S 24 -#define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 9 -#define ADI_MASK4B89_M1L_S 20 -#define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 9, - only bits selected - // by mask M1L will be affected by - // access -#define ADI_MASK4B89_D1L_S 16 -#define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 8 -#define ADI_MASK4B89_M0H_S 12 -#define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 8, - only bits selected - // by mask M0H will be affected by - // access -#define ADI_MASK4B89_D0H_S 8 -#define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 8 -#define ADI_MASK4B89_M0L_S 4 -#define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 8, - only bits selected - // by mask M0L will be affected by - // access -#define ADI_MASK4B89_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK4B1011 register. -// -//***************************************************************************** -#define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 11 -#define ADI_MASK4B1011_M1H_S 28 -#define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 11, - only bits - // selected by mask M1H will be - // affected by access -#define ADI_MASK4B1011_D1H_S 24 -#define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 11 -#define ADI_MASK4B1011_M1L_S 20 -#define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 11, - only bits - // selected by mask M1L will be - // affected by access -#define ADI_MASK4B1011_D1L_S 16 -#define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 10 -#define ADI_MASK4B1011_M0H_S 12 -#define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 10, - only bits - // selected by mask M0H will be - // affected by access -#define ADI_MASK4B1011_D0H_S 8 -#define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 10 -#define ADI_MASK4B1011_M0L_S 4 -#define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 10, - only bits - // selected by mask M0L will be - // affected by access -#define ADI_MASK4B1011_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK4B1213 register. -// -//***************************************************************************** -#define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 13 -#define ADI_MASK4B1213_M1H_S 28 -#define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 13, - only bits - // selected by mask M1H will be - // affected by access -#define ADI_MASK4B1213_D1H_S 24 -#define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 13 -#define ADI_MASK4B1213_M1L_S 20 -#define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 13, - only bits - // selected by mask M1L will be - // affected by access -#define ADI_MASK4B1213_D1L_S 16 -#define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 12 -#define ADI_MASK4B1213_M0H_S 12 -#define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 12, - only bits - // selected by mask M0H will be - // affected by access -#define ADI_MASK4B1213_D0H_S 8 -#define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 12 -#define ADI_MASK4B1213_M0L_S 4 -#define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 12, - only bits - // selected by mask M0L will be - // affected by access -#define ADI_MASK4B1213_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK4B1415 register. -// -//***************************************************************************** -#define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI - // register 15 -#define ADI_MASK4B1415_M1H_S 28 -#define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI - // register 15, - only bits - // selected by mask M1H will be - // affected by access -#define ADI_MASK4B1415_D1H_S 24 -#define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI - // register 15 -#define ADI_MASK4B1415_M1L_S 20 -#define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI - // register 15, - only bits - // selected by mask M1L will be - // affected by access -#define ADI_MASK4B1415_D1L_S 16 -#define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI - // register 14 -#define ADI_MASK4B1415_M0H_S 12 -#define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI - // register 14, - only bits - // selected by mask M0H will be - // affected by access -#define ADI_MASK4B1415_D0H_S 8 -#define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI - // register 14 -#define ADI_MASK4B1415_M0L_S 4 -#define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI - // register 14, - only bits - // selected by mask M0L will be - // affected by access -#define ADI_MASK4B1415_D0L_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK8B01 register. -// -//***************************************************************************** -#define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 -#define ADI_MASK8B01_M1_S 24 -#define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only - // bits selected by mask M1 will be - // affected by access -#define ADI_MASK8B01_D1_S 16 -#define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 -#define ADI_MASK8B01_M0_S 8 -#define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only - // bits selected by mask M0 will be - // affected by access -#define ADI_MASK8B01_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK8B23 register. -// -//***************************************************************************** -#define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 -#define ADI_MASK8B23_M1_S 24 -#define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only - // bits selected by mask M1 will be - // affected by access -#define ADI_MASK8B23_D1_S 16 -#define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 -#define ADI_MASK8B23_M0_S 8 -#define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only - // bits selected by mask M0 will be - // affected by access -#define ADI_MASK8B23_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK8B45 register. -// -//***************************************************************************** -#define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 -#define ADI_MASK8B45_M1_S 24 -#define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only - // bits selected by mask M1 will be - // affected by access -#define ADI_MASK8B45_D1_S 16 -#define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 -#define ADI_MASK8B45_M0_S 8 -#define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only - // bits selected by mask M0 will be - // affected by access -#define ADI_MASK8B45_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK8B67 register. -// -//***************************************************************************** -#define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 -#define ADI_MASK8B67_M1_S 24 -#define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only - // bits selected by mask M1 will be - // affected by access -#define ADI_MASK8B67_D1_S 16 -#define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 -#define ADI_MASK8B67_M0_S 8 -#define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only - // bits selected by mask M0 will be - // affected by access -#define ADI_MASK8B67_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the ADI_O_MASK8B89 register. -// -//***************************************************************************** -#define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 -#define ADI_MASK8B89_M1_S 24 -#define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only - // bits selected by mask M1 will be - // affected by access -#define ADI_MASK8B89_D1_S 16 -#define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 -#define ADI_MASK8B89_M0_S 8 -#define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only - // bits selected by mask M0 will be - // affected by access -#define ADI_MASK8B89_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK8B1011 register. -// -//***************************************************************************** -#define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 -#define ADI_MASK8B1011_M1_S 24 -#define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - - // only bits selected by mask M1 - // will be affected by access -#define ADI_MASK8B1011_D1_S 16 -#define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 -#define ADI_MASK8B1011_M0_S 8 -#define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - - // only bits selected by mask M0 - // will be affected by access -#define ADI_MASK8B1011_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK8B1213 register. -// -//***************************************************************************** -#define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 -#define ADI_MASK8B1213_M1_S 24 -#define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - - // only bits selected by mask M1 - // will be affected by access -#define ADI_MASK8B1213_D1_S 16 -#define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 -#define ADI_MASK8B1213_M0_S 8 -#define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - - // only bits selected by mask M0 - // will be affected by access -#define ADI_MASK8B1213_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK8B1415 register. -// -//***************************************************************************** -#define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 -#define ADI_MASK8B1415_M1_S 24 -#define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - - // only bits selected by mask M1 - // will be affected by access -#define ADI_MASK8B1415_D1_S 16 -#define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 -#define ADI_MASK8B1415_M0_S 8 -#define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - - // only bits selected by mask M0 - // will be affected by access -#define ADI_MASK8B1415_D0_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B01 register. -// -//***************************************************************************** -#define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 -#define ADI_MASK16B01_M_S 16 -#define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at - // offsets 0 and 1, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B01_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B23 register. -// -//***************************************************************************** -#define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 -#define ADI_MASK16B23_M_S 16 -#define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at - // offsets 2 and 3, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B23_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B45 register. -// -//***************************************************************************** -#define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 -#define ADI_MASK16B45_M_S 16 -#define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at - // offsets 4 and 5, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B45_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B67 register. -// -//***************************************************************************** -#define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 -#define ADI_MASK16B67_M_S 16 -#define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at - // offsets 6 and 7, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B67_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B89 register. -// -//***************************************************************************** -#define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 -#define ADI_MASK16B89_M_S 16 -#define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at - // offsets 8 and 9, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B89_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B1011 register. -// -//***************************************************************************** -#define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 -#define ADI_MASK16B1011_M_S 16 -#define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at - // offsets 10 and 11, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B1011_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B1213 register. -// -//***************************************************************************** -#define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 -#define ADI_MASK16B1213_M_S 16 -#define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at - // offsets 12 and 13, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B1213_D_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the -// ADI_O_MASK16B1415 register. -// -//***************************************************************************** -#define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 -#define ADI_MASK16B1415_M_S 16 -#define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at - // offsets 14 and 15, - only bits - // selected by mask M will be - // affected by access -#define ADI_MASK16B1415_D_S 0 - -#endif // __HW_ADI_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h deleted file mode 100644 index 68d37bde94f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_2_refsys.h +++ /dev/null @@ -1,362 +0,0 @@ -/****************************************************************************** -* Filename: hw_adi_2_refsys_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_ADI_2_REFSYS_H__ -#define __HW_ADI_2_REFSYS_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// ADI_2_REFSYS component -// -//***************************************************************************** -// Internal -#define ADI_2_REFSYS_O_REFSYSCTL0 0x00000000 - -// Internal -#define ADI_2_REFSYS_O_SOCLDOCTL0 0x00000002 - -// Internal -#define ADI_2_REFSYS_O_SOCLDOCTL1 0x00000003 - -// Internal -#define ADI_2_REFSYS_O_SOCLDOCTL2 0x00000004 - -// Internal -#define ADI_2_REFSYS_O_SOCLDOCTL3 0x00000005 - -// Internal -#define ADI_2_REFSYS_O_SOCLDOCTL4 0x00000006 - -// Internal -#define ADI_2_REFSYS_O_SOCLDOCTL5 0x00000007 - -// Internal -#define ADI_2_REFSYS_O_HPOSCCTL0 0x0000000A - -// Internal -#define ADI_2_REFSYS_O_HPOSCCTL1 0x0000000B - -// Internal -#define ADI_2_REFSYS_O_HPOSCCTL2 0x0000000C - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_REFSYSCTL0 -// -//***************************************************************************** -// Field: [4:0] TRIM_IREF -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_W 5 -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_M 0x0000001F -#define ADI_2_REFSYS_REFSYSCTL0_TRIM_IREF_S 0 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_SOCLDOCTL0 -// -//***************************************************************************** -// Field: [7:4] VTRIM_UDIG -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_W 4 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_M 0x000000F0 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_UDIG_S 4 - -// Field: [3:0] VTRIM_BOD -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_W 4 -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_M 0x0000000F -#define ADI_2_REFSYS_SOCLDOCTL0_VTRIM_BOD_S 0 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_SOCLDOCTL1 -// -//***************************************************************************** -// Field: [7:4] VTRIM_COARSE -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_W 4 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_M 0x000000F0 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_COARSE_S 4 - -// Field: [3:0] VTRIM_DIG -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_W 4 -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_M 0x0000000F -#define ADI_2_REFSYS_SOCLDOCTL1_VTRIM_DIG_S 0 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_SOCLDOCTL2 -// -//***************************************************************************** -// Field: [2:0] VTRIM_DELTA -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_W 3 -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL2_VTRIM_DELTA_S 0 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_SOCLDOCTL3 -// -//***************************************************************************** -// Field: [7:6] ITRIM_DIGLDO_LOAD -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_W 2 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_M 0x000000C0 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_LOAD_S 6 - -// Field: [5:3] ITRIM_DIGLDO -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// BIAS_120P Internal. Only to be used through TI provided API. -// BIAS_100P Internal. Only to be used through TI provided API. -// BIAS_80P Internal. Only to be used through TI provided API. -// BIAS_60P Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_W 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_M 0x00000038 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_S 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_120P 0x00000038 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_100P 0x00000028 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_80P 0x00000018 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_DIGLDO_BIAS_60P 0x00000000 - -// Field: [2:0] ITRIM_UDIGLDO -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_W 3 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL3_ITRIM_UDIGLDO_S 0 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_SOCLDOCTL4 -// -//***************************************************************************** -// Field: [6:5] UDIG_ITEST_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_W 2 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_M 0x00000060 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_ITEST_EN_S 5 - -// Field: [4:2] DIG_ITEST_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_W 3 -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_M 0x0000001C -#define ADI_2_REFSYS_SOCLDOCTL4_DIG_ITEST_EN_S 2 - -// Field: [1] BIAS_DIS -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_M 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL4_BIAS_DIS_S 1 - -// Field: [0] UDIG_LDO_EN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// EN Internal. Only to be used through TI provided API. -// DIS Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_M 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_S 0 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_EN 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL4_UDIG_LDO_EN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_SOCLDOCTL5 -// -//***************************************************************************** -// Field: [3] IMON_ITEST_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN 0x00000008 -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_M 0x00000008 -#define ADI_2_REFSYS_SOCLDOCTL5_IMON_ITEST_EN_S 3 - -// Field: [2:0] TESTSEL -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// VDD_AON Internal. Only to be used through TI provided API. -// VREF_AMP Internal. Only to be used through TI provided API. -// ITEST Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_W 3 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_M 0x00000007 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_S 0 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VDD_AON 0x00000004 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_VREF_AMP 0x00000002 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_ITEST 0x00000001 -#define ADI_2_REFSYS_SOCLDOCTL5_TESTSEL_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_HPOSCCTL0 -// -//***************************************************************************** -// Field: [7] FILTER_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_M 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL0_FILTER_EN_S 7 - -// Field: [6:5] BIAS_RECHARGE_DLY -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// MIN_DLY_X8 Internal. Only to be used through TI provided API. -// MIN_DLY_X4 Internal. Only to be used through TI provided API. -// MIN_DLY_X2 Internal. Only to be used through TI provided API. -// MIN_DLY_X1 Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_M 0x00000060 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_S 5 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X8 0x00000060 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X4 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X2 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL0_BIAS_RECHARGE_DLY_MIN_DLY_X1 0x00000000 - -// Field: [4:3] TUNE_CAP -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// SHIFT_M108 Internal. Only to be used through TI provided API. -// SHIFT_M70 Internal. Only to be used through TI provided API. -// SHIFT_M35 Internal. Only to be used through TI provided API. -// SHIFT_0 Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_M 0x00000018 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_S 3 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M108 0x00000018 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M70 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_M35 0x00000008 -#define ADI_2_REFSYS_HPOSCCTL0_TUNE_CAP_SHIFT_0 0x00000000 - -// Field: [2:1] SERIES_CAP -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_W 2 -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_M 0x00000006 -#define ADI_2_REFSYS_HPOSCCTL0_SERIES_CAP_S 1 - -// Field: [0] DIV3_BYPASS -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// HPOSC_2520MHZ Internal. Only to be used through TI provided API. -// HPOSC_840MHZ Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_M 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_S 0 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_2520MHZ 0x00000001 -#define ADI_2_REFSYS_HPOSCCTL0_DIV3_BYPASS_HPOSC_840MHZ 0x00000000 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_HPOSCCTL1 -// -//***************************************************************************** -// Field: [5] BIAS_DIS -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_M 0x00000020 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_DIS_S 5 - -// Field: [4] PWRDET_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_M 0x00000010 -#define ADI_2_REFSYS_HPOSCCTL1_PWRDET_EN_S 4 - -// Field: [3:0] BIAS_RES_SET -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_W 4 -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_M 0x0000000F -#define ADI_2_REFSYS_HPOSCCTL1_BIAS_RES_SET_S 0 - -//***************************************************************************** -// -// Register: ADI_2_REFSYS_O_HPOSCCTL2 -// -//***************************************************************************** -// Field: [7] BIAS_HOLD_MODE_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_M 0x00000080 -#define ADI_2_REFSYS_HPOSCCTL2_BIAS_HOLD_MODE_EN_S 7 - -// Field: [6] TESTMUX_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_M 0x00000040 -#define ADI_2_REFSYS_HPOSCCTL2_TESTMUX_EN_S 6 - -// Field: [5:4] ATEST_SEL -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_W 2 -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_M 0x00000030 -#define ADI_2_REFSYS_HPOSCCTL2_ATEST_SEL_S 4 - -// Field: [3:0] CURRMIRR_RATIO -// -// Internal. Only to be used through TI provided API. -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_W 4 -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_M 0x0000000F -#define ADI_2_REFSYS_HPOSCCTL2_CURRMIRR_RATIO_S 0 - - -#endif // __ADI_2_REFSYS__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h deleted file mode 100644 index 2315d8d5581..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_3_refsys.h +++ /dev/null @@ -1,685 +0,0 @@ -/****************************************************************************** -* Filename: hw_adi_3_refsys_h -* Revised: 2018-09-27 10:33:21 +0200 (Thu, 27 Sep 2018) -* Revision: 52772 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_ADI_3_REFSYS_H__ -#define __HW_ADI_3_REFSYS_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// ADI_3_REFSYS component -// -//***************************************************************************** -// Internal -#define ADI_3_REFSYS_O_ATESTCTL1 0x00000001 - -// Internal -#define ADI_3_REFSYS_O_REFSYSCTL0 0x00000002 - -// Internal -#define ADI_3_REFSYS_O_REFSYSCTL1 0x00000003 - -// Internal -#define ADI_3_REFSYS_O_REFSYSCTL2 0x00000004 - -// Internal -#define ADI_3_REFSYS_O_REFSYSCTL3 0x00000005 - -// DCDC Control 0 -#define ADI_3_REFSYS_O_DCDCCTL0 0x00000006 - -// DCDC Control 1 -#define ADI_3_REFSYS_O_DCDCCTL1 0x00000007 - -// DCDC Control 2 -#define ADI_3_REFSYS_O_DCDCCTL2 0x00000008 - -// Internal -#define ADI_3_REFSYS_O_DCDCCTL3 0x00000009 - -// Internal -#define ADI_3_REFSYS_O_DCDCCTL4 0x0000000A - -// Internal -#define ADI_3_REFSYS_O_DCDCCTL5 0x0000000B - -// RECHARGE_CONTROL_1 -#define ADI_3_REFSYS_O_AUX_DEBUG 0x0000000C - -// Recharge Comparator Control Byte 0 -#define ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 0x0000000D - -// Recharge Comparator Control Byte 1 -#define ADI_3_REFSYS_O_CTL_RECHARGE_CMP1 0x0000000E - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_ATESTCTL1 -// -//***************************************************************************** -// Field: [4:3] ATEST0_CTL -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// ICELL_A0 Internal. Only to be used through TI provided API. -// IREF_A0 Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_W 2 -#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_M 0x00000018 -#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_S 3 -#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_ICELL_A0 0x00000010 -#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_IREF_A0 0x00000008 -#define ADI_3_REFSYS_ATESTCTL1_ATEST0_CTL_NC 0x00000000 - -// Field: [2:0] ATEST1_CTL -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// VREFM_A1 Internal. Only to be used through TI provided API. -// VPP_DIV5_A1 Internal. Only to be used through TI provided API. -// VREAD_DIV2_A1 Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_W 3 -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_M 0x00000007 -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_S 0 -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VREFM_A1 0x00000004 -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VPP_DIV5_A1 0x00000002 -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_VREAD_DIV2_A1 0x00000001 -#define ADI_3_REFSYS_ATESTCTL1_ATEST1_CTL_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_REFSYSCTL0 -// -//***************************************************************************** -// Field: [7:0] TESTCTL -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// BMCOMPOUT Internal. Only to be used through TI provided API. -// VTEMP Internal. Only to be used through TI provided API. -// VREF0P8V Internal. Only to be used through TI provided API. -// VBGUNBUFF Internal. Only to be used through TI provided API. -// VBG Internal. Only to be used through TI provided API. -// IREF4U Internal. Only to be used through TI provided API. -// IVREF4U Internal. Only to be used through TI provided API. -// IPTAT2U Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_W 8 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_M 0x000000FF -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_S 0 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_BMCOMPOUT 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VTEMP 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VREF0P8V 0x00000020 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBGUNBUFF 0x00000010 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_VBG 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IREF4U 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IVREF4U 0x00000002 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_IPTAT2U 0x00000001 -#define ADI_3_REFSYS_REFSYSCTL0_TESTCTL_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_REFSYSCTL1 -// -//***************************************************************************** -// Field: [7:3] TRIM_VDDS_BOD -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// POS_27 Internal. Only to be used through TI provided API. -// POS_26 Internal. Only to be used through TI provided API. -// POS_25 Internal. Only to be used through TI provided API. -// POS_24 Internal. Only to be used through TI provided API. -// POS_31 Internal. Only to be used through TI provided API. -// POS_30 Internal. Only to be used through TI provided API. -// POS_29 Internal. Only to be used through TI provided API. -// POS_28 Internal. Only to be used through TI provided API. -// POS_19 Internal. Only to be used through TI provided API. -// POS_18 Internal. Only to be used through TI provided API. -// POS_17 Internal. Only to be used through TI provided API. -// POS_16 Internal. Only to be used through TI provided API. -// POS_23 Internal. Only to be used through TI provided API. -// POS_22 Internal. Only to be used through TI provided API. -// POS_21 Internal. Only to be used through TI provided API. -// POS_20 Internal. Only to be used through TI provided API. -// POS_11 Internal. Only to be used through TI provided API. -// POS_10 Internal. Only to be used through TI provided API. -// POS_9 Internal. Only to be used through TI provided API. -// POS_8 Internal. Only to be used through TI provided API. -// POS_15 Internal. Only to be used through TI provided API. -// POS_14 Internal. Only to be used through TI provided API. -// POS_13 Internal. Only to be used through TI provided API. -// POS_12 Internal. Only to be used through TI provided API. -// POS_3 Internal. Only to be used through TI provided API. -// POS_2 Internal. Only to be used through TI provided API. -// POS_1 Internal. Only to be used through TI provided API. -// POS_0 Internal. Only to be used through TI provided API. -// POS_7 Internal. Only to be used through TI provided API. -// POS_6 Internal. Only to be used through TI provided API. -// POS_5 Internal. Only to be used through TI provided API. -// POS_4 Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_W 5 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_M 0x000000F8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_S 3 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_27 0x000000F8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_26 0x000000F0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_25 0x000000E8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_24 0x000000E0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_31 0x000000D8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_30 0x000000D0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_29 0x000000C8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_28 0x000000C0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_19 0x000000B8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_18 0x000000B0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_17 0x000000A8 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_16 0x000000A0 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_23 0x00000098 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_22 0x00000090 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_21 0x00000088 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_20 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_11 0x00000078 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_10 0x00000070 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_9 0x00000068 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_8 0x00000060 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_15 0x00000058 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_14 0x00000050 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_13 0x00000048 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_12 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_3 0x00000038 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_2 0x00000030 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_1 0x00000028 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_0 0x00000020 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_7 0x00000018 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_6 0x00000010 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_5 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL1_TRIM_VDDS_BOD_POS_4 0x00000000 - -// Field: [2] BATMON_COMP_TEST_EN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// EN Internal. Only to be used through TI provided API. -// DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_M 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_S 2 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_EN 0x00000004 -#define ADI_3_REFSYS_REFSYSCTL1_BATMON_COMP_TEST_EN_DIS 0x00000000 - -// Field: [1:0] TESTCTL -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// IPTAT1U Internal. Only to be used through TI provided API. -// BMCOMPIN Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_W 2 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_M 0x00000003 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_S 0 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_IPTAT1U 0x00000002 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_BMCOMPIN 0x00000001 -#define ADI_3_REFSYS_REFSYSCTL1_TESTCTL_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_REFSYSCTL2 -// -//***************************************************************************** -// Field: [7:4] TRIM_VREF -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_W 4 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_M 0x000000F0 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_VREF_S 4 - -// Field: [3] BOD_EXTERNAL_REG_MODE -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE_M 0x00000008 -#define ADI_3_REFSYS_REFSYSCTL2_BOD_EXTERNAL_REG_MODE_S 3 - -// Field: [1:0] TRIM_TSENSE -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_W 2 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_M 0x00000003 -#define ADI_3_REFSYS_REFSYSCTL2_TRIM_TSENSE_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_REFSYSCTL3 -// -//***************************************************************************** -// Field: [7] BOD_BG_TRIM_EN -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_M 0x00000080 -#define ADI_3_REFSYS_REFSYSCTL3_BOD_BG_TRIM_EN_S 7 - -// Field: [6] VTEMP_EN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// EN Internal. Only to be used through TI provided API. -// DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_M 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_S 6 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_EN 0x00000040 -#define ADI_3_REFSYS_REFSYSCTL3_VTEMP_EN_DIS 0x00000000 - -// Field: [5:0] TRIM_VBG -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_W 6 -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_M 0x0000003F -#define ADI_3_REFSYS_REFSYSCTL3_TRIM_VBG_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_DCDCCTL0 -// -//***************************************************************************** -// Field: [7:5] GLDO_ISRC -// -// Set charge and re-charge current level. -// 2's complement encoding. -// -// 0x0: Default 11mA. -// 0x3: Max 15mA. -// 0x4: Max 5mA -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_W 3 -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_M 0x000000E0 -#define ADI_3_REFSYS_DCDCCTL0_GLDO_ISRC_S 5 - -// Field: [4:0] VDDR_TRIM -// -// Set the VDDR voltage. -// Proprietary encoding. -// -// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. -// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. -// Step size = 16mV -// -// 0x00: Default, about 1.63V. -// 0x05: Typical voltage after trim voltage 1.71V. -// 0x15: Max voltage 1.96V. -// 0x16: Min voltage 1.47V. -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_W 5 -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_M 0x0000001F -#define ADI_3_REFSYS_DCDCCTL0_VDDR_TRIM_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_DCDCCTL1 -// -//***************************************************************************** -// Field: [7:6] IPTAT_TRIM -// -// Trim GLDO bias current. -// Proprietary encoding. -// -// 0x0: Default -// 0x1: Increase GLDO bias by 1.3x. -// 0x2: Increase GLDO bias by 1.6x. -// 0x3: Decrease GLDO bias by 0.7x. -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_W 2 -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_M 0x000000C0 -#define ADI_3_REFSYS_DCDCCTL1_IPTAT_TRIM_S 6 - -// Field: [5] VDDR_OK_HYST -// -// Increase the hysteresis for when VDDR is considered ok. -// -// 0: Hysteresis = 60mV -// 1: Hysteresis = 70mV -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST 0x00000020 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_OK_HYST_S 5 - -// Field: [4:0] VDDR_TRIM_SLEEP -// -// Set the min VDDR voltage threshold during sleep mode. -// Proprietary encoding. -// -// Increase voltage to max: 0x00, 0x01, 0x02 ... 0x15. -// Decrease voltage to min: 0x00, 0x1F, 0x1E, 0x1D ... 0x16. -// Step size = 16mV -// -// 0x00: Default, about 1.63V. -// 0x19: Typical voltage after trim voltage 1.52V. -// 0x15: Max voltage 1.96V. -// 0x16: Min voltage 1.47V. -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_W 5 -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_M 0x0000001F -#define ADI_3_REFSYS_DCDCCTL1_VDDR_TRIM_SLEEP_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_DCDCCTL2 -// -//***************************************************************************** -// Field: [6] TURNON_EA_SW -// -// Turn on erroramp switch -// -// 0: Erroramp Off (Default) -// 1: Erroramp On. Turns on GLDO error amp switch. -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW 0x00000040 -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_M 0x00000040 -#define ADI_3_REFSYS_DCDCCTL2_TURNON_EA_SW_S 6 - -// Field: [5] TEST_VDDR -// -// Connect VDDR to ATEST bus -// -// 0: Not connected. -// 1: Connected -// -// Set TESTSEL = 0x0 first before setting this bit. -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR 0x00000020 -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL2_TEST_VDDR_S 5 - -// Field: [4] BIAS_DIS -// -// Disable dummy bias current. -// -// 0: Dummy bias current on (Default) -// 1: Dummy bias current off -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS 0x00000010 -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_M 0x00000010 -#define ADI_3_REFSYS_DCDCCTL2_BIAS_DIS_S 4 - -// Field: [3:0] TESTSEL -// -// Select signal for test bus, one hot. -// ENUMs: -// VDDROK VDDR_OK connected to test bus. -// IB1U 1uA bias current connected to test bus. -// PASSGATE Pass transistor gate voltage connected to test -// bus. -// ERRAMP_OUT Error amp output voltage connected to test bus. -// NC No signal connected to test bus. -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_W 4 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_M 0x0000000F -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_S 0 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_VDDROK 0x00000008 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_IB1U 0x00000004 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_PASSGATE 0x00000002 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_ERRAMP_OUT 0x00000001 -#define ADI_3_REFSYS_DCDCCTL2_TESTSEL_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_DCDCCTL3 -// -//***************************************************************************** -// Field: [1:0] VDDR_BOOST_COMP -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// BOOST_P1 Internal. Only to be used through TI provided API. -// BOOST Internal. Only to be used through TI provided API. -// BOOST_N1 Internal. Only to be used through TI provided API. -// DEFAULT Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_W 2 -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_M 0x00000003 -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_S 0 -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_P1 0x00000003 -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST 0x00000002 -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_BOOST_N1 0x00000001 -#define ADI_3_REFSYS_DCDCCTL3_VDDR_BOOST_COMP_DEFAULT 0x00000000 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_DCDCCTL4 -// -//***************************************************************************** -// Field: [7:6] DEADTIME_TRIM -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_W 2 -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_M 0x000000C0 -#define ADI_3_REFSYS_DCDCCTL4_DEADTIME_TRIM_S 6 - -// Field: [5:3] LOW_EN_SEL -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_W 3 -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_M 0x00000038 -#define ADI_3_REFSYS_DCDCCTL4_LOW_EN_SEL_S 3 - -// Field: [2:0] HIGH_EN_SEL -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_W 3 -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_M 0x00000007 -#define ADI_3_REFSYS_DCDCCTL4_HIGH_EN_SEL_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_DCDCCTL5 -// -//***************************************************************************** -// Field: [5] TESTN -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_TESTN 0x00000020 -#define ADI_3_REFSYS_DCDCCTL5_TESTN_M 0x00000020 -#define ADI_3_REFSYS_DCDCCTL5_TESTN_S 5 - -// Field: [4] TESTP -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_TESTP 0x00000010 -#define ADI_3_REFSYS_DCDCCTL5_TESTP_M 0x00000010 -#define ADI_3_REFSYS_DCDCCTL5_TESTP_S 4 - -// Field: [3] DITHER_EN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// EN Internal. Only to be used through TI provided API. -// DIS Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_M 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_S 3 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_EN 0x00000008 -#define ADI_3_REFSYS_DCDCCTL5_DITHER_EN_DIS 0x00000000 - -// Field: [2:0] IPEAK -// -// Internal. Only to be used through TI provided API. -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_W 3 -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_M 0x00000007 -#define ADI_3_REFSYS_DCDCCTL5_IPEAK_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_AUX_DEBUG -// -//***************************************************************************** -// Field: [6] LPM_BIAS_BACKUP_EN -// -// Activate the backup circuit in case the main circuit does not work -#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN 0x00000040 -#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN_M 0x00000040 -#define ADI_3_REFSYS_AUX_DEBUG_LPM_BIAS_BACKUP_EN_S 6 - -// Field: [5] DAC_DBG_OFFSET_COMP -// -// Offset compensation signal (Debug Mode) -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP 0x00000020 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP_M 0x00000020 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_OFFSET_COMP_S 5 - -// Field: [4] DAC_DBG_HOLD -// -// S-H Cap hold signal (Debug Mode) -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD 0x00000010 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD_M 0x00000010 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_HOLD_S 4 - -// Field: [3] DAC_DBG_PRECHARGE -// -// PRE-CHARGE signal (Debug Mode) -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE 0x00000008 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE_M 0x00000008 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_PRECHARGE_S 3 - -// Field: [2] DAC_DBG_CAP_SAMPLE -// -// Cap-array sample signal (Debug Mode) -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE 0x00000004 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE_M 0x00000004 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_CAP_SAMPLE_S 2 - -// Field: [1] DAC_DBG_SAMPLE -// -// S-H Cap sample signal (Debug Mode) -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE 0x00000002 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE_M 0x00000002 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_SAMPLE_S 1 - -// Field: [0] DAC_DBG_EN -// -// Enable Debug Mode -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN 0x00000001 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN_M 0x00000001 -#define ADI_3_REFSYS_AUX_DEBUG_DAC_DBG_EN_S 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_CTL_RECHARGE_CMP0 -// -//***************************************************************************** -// Field: [4] COMP_CLK_DISABLE -// -// Enable/Disable the 32 kHz clock (SCLK_LF) to the recharge comparator -// ENUMs: -// DIS Disable the clock -// EN Enable the clock -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE 0x00000010 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_M 0x00000010 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_S 4 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_DIS 0x00000010 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_COMP_CLK_DISABLE_EN 0x00000000 - -// Field: [3:0] TRIM_RECHARGE_COMP_REFLEVEL -// -// Trim ref level of recharge. -// -// 0xF: 90% of VDDR level. -// 0x0: 100% of VDDR level. -// -// Step size = 0.67% of VDDR level. -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_W \ - 4 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_M \ - 0x0000000F -#define ADI_3_REFSYS_CTL_RECHARGE_CMP0_TRIM_RECHARGE_COMP_REFLEVEL_S \ - 0 - -//***************************************************************************** -// -// Register: ADI_3_REFSYS_O_CTL_RECHARGE_CMP1 -// -//***************************************************************************** -// Field: [7] RECHARGE_BLOCK_VTRIG_EN -// -// Enable/Disable ATEST input to VDDR input of recharge comparator. Used for -// trimming the recharge voltage reference level -// ENUMs: -// EN Enable. VDDR input is connected to ATEST network -// DIS Disable. VDDR input is connected to VDDR itself -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN 0x00000080 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_M \ - 0x00000080 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_S \ - 7 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_EN \ - 0x00000080 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_VTRIG_EN_DIS \ - 0x00000000 - -// Field: [6] RECHARGE_BLOCK_ATEST_EN -// -// Enable/Disable test inputs/outputs to recharge comparator block -// ENUMs: -// EN Enable -// DIS Disable -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN 0x00000040 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_M \ - 0x00000040 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_S \ - 6 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_EN \ - 0x00000040 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_RECHARGE_BLOCK_ATEST_EN_DIS \ - 0x00000000 - -// Field: [5] FORCE_SAMPLE_VDDR -// -// Force Sample of VDDR on cap divider -// ENUMs: -// EN Enable -// DIS Disable -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR 0x00000020 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_M 0x00000020 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_S 5 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_EN 0x00000020 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_FORCE_SAMPLE_VDDR_DIS 0x00000000 - -// Field: [4:0] TRIM_RECHARGE_COMP_OFFSET -// -// Trim offset of Recharge comparator. -// -// 0x00: Maximum degeneration on input side (VDDR side). -// 0x1F: Maximum degeneration on reference side from cap divider. -// 0x10: Nominal code. -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_W \ - 5 -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_M \ - 0x0000001F -#define ADI_3_REFSYS_CTL_RECHARGE_CMP1_TRIM_RECHARGE_COMP_OFFSET_S \ - 0 - - -#endif // __ADI_3_REFSYS__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h deleted file mode 100644 index 45fdfc31b33..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_adi_4_aux.h +++ /dev/null @@ -1,513 +0,0 @@ -/****************************************************************************** -* Filename: hw_adi_4_aux_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_ADI_4_AUX_H__ -#define __HW_ADI_4_AUX_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// ADI_4_AUX component -// -//***************************************************************************** -// Internal -#define ADI_4_AUX_O_MUX0 0x00000000 - -// Internal -#define ADI_4_AUX_O_MUX1 0x00000001 - -// Internal -#define ADI_4_AUX_O_MUX2 0x00000002 - -// Internal -#define ADI_4_AUX_O_MUX3 0x00000003 - -// Current Source -#define ADI_4_AUX_O_ISRC 0x00000004 - -// Comparator -#define ADI_4_AUX_O_COMP 0x00000005 - -// Internal -#define ADI_4_AUX_O_MUX4 0x00000007 - -// ADC Control 0 -#define ADI_4_AUX_O_ADC0 0x00000008 - -// ADC Control 1 -#define ADI_4_AUX_O_ADC1 0x00000009 - -// ADC Reference 0 -#define ADI_4_AUX_O_ADCREF0 0x0000000A - -// ADC Reference 1 -#define ADI_4_AUX_O_ADCREF1 0x0000000B - -// Internal -#define ADI_4_AUX_O_LPMBIAS 0x0000000E - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_MUX0 -// -//***************************************************************************** -// Field: [6] ADCCOMPB_IN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// VDDR_1P8V Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX0_ADCCOMPB_IN 0x00000040 -#define ADI_4_AUX_MUX0_ADCCOMPB_IN_M 0x00000040 -#define ADI_4_AUX_MUX0_ADCCOMPB_IN_S 6 -#define ADI_4_AUX_MUX0_ADCCOMPB_IN_VDDR_1P8V 0x00000040 -#define ADI_4_AUX_MUX0_ADCCOMPB_IN_NC 0x00000000 - -// Field: [3:0] COMPA_REF -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// ADCVREFP Internal. Only to be used through TI provided API. -// VDDS Internal. Only to be used through TI provided API. -// VSS Internal. Only to be used through TI provided API. -// DCOUPL Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX0_COMPA_REF_W 4 -#define ADI_4_AUX_MUX0_COMPA_REF_M 0x0000000F -#define ADI_4_AUX_MUX0_COMPA_REF_S 0 -#define ADI_4_AUX_MUX0_COMPA_REF_ADCVREFP 0x00000008 -#define ADI_4_AUX_MUX0_COMPA_REF_VDDS 0x00000004 -#define ADI_4_AUX_MUX0_COMPA_REF_VSS 0x00000002 -#define ADI_4_AUX_MUX0_COMPA_REF_DCOUPL 0x00000001 -#define ADI_4_AUX_MUX0_COMPA_REF_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_MUX1 -// -//***************************************************************************** -// Field: [7:0] COMPA_IN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// AUXIO19 Internal. Only to be used through TI provided API. -// AUXIO20 Internal. Only to be used through TI provided API. -// AUXIO21 Internal. Only to be used through TI provided API. -// AUXIO22 Internal. Only to be used through TI provided API. -// AUXIO23 Internal. Only to be used through TI provided API. -// AUXIO24 Internal. Only to be used through TI provided API. -// AUXIO25 Internal. Only to be used through TI provided API. -// AUXIO26 Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX1_COMPA_IN_W 8 -#define ADI_4_AUX_MUX1_COMPA_IN_M 0x000000FF -#define ADI_4_AUX_MUX1_COMPA_IN_S 0 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO19 0x00000080 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO20 0x00000040 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO21 0x00000020 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO22 0x00000010 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO23 0x00000008 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO24 0x00000004 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO25 0x00000002 -#define ADI_4_AUX_MUX1_COMPA_IN_AUXIO26 0x00000001 -#define ADI_4_AUX_MUX1_COMPA_IN_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_MUX2 -// -//***************************************************************************** -// Field: [7:3] ADCCOMPB_IN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// VDDS Internal. Only to be used through TI provided API. -// VSS Internal. Only to be used through TI provided API. -// DCOUPL Internal. Only to be used through TI provided API. -// ATEST1 Internal. Only to be used through TI provided API. -// ATEST0 Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_W 5 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_M 0x000000F8 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_S 3 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VDDS 0x00000080 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_VSS 0x00000040 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_DCOUPL 0x00000020 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST1 0x00000010 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_ATEST0 0x00000008 -#define ADI_4_AUX_MUX2_ADCCOMPB_IN_NC 0x00000000 - -// Field: [2:0] DAC_VREF_SEL -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// VDDS Internal. Only to be used through TI provided API. -// ADCREF Internal. Only to be used through TI provided API. -// DCOUPL Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_W 3 -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_M 0x00000007 -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_S 0 -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_VDDS 0x00000004 -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_ADCREF 0x00000002 -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_DCOUPL 0x00000001 -#define ADI_4_AUX_MUX2_DAC_VREF_SEL_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_MUX3 -// -//***************************************************************************** -// Field: [7:0] ADCCOMPB_IN -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// AUXIO19 Internal. Only to be used through TI provided API. -// AUXIO20 Internal. Only to be used through TI provided API. -// AUXIO21 Internal. Only to be used through TI provided API. -// AUXIO22 Internal. Only to be used through TI provided API. -// AUXIO23 Internal. Only to be used through TI provided API. -// AUXIO24 Internal. Only to be used through TI provided API. -// AUXIO25 Internal. Only to be used through TI provided API. -// AUXIO26 Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_W 8 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_M 0x000000FF -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_S 0 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO19 0x00000080 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO20 0x00000040 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO21 0x00000020 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO22 0x00000010 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO23 0x00000008 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO24 0x00000004 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO25 0x00000002 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_AUXIO26 0x00000001 -#define ADI_4_AUX_MUX3_ADCCOMPB_IN_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_ISRC -// -//***************************************************************************** -// Field: [7:2] TRIM -// -// Adjust current from current source. -// -// Output currents may be combined to get desired total current. -// ENUMs: -// 11P75U 11.75 uA -// 4P5U 4.5 uA -// 2P0U 2.0 uA -// 1P0U 1.0 uA -// 0P5U 0.5 uA -// 0P25U 0.25 uA -// NC No current connected -#define ADI_4_AUX_ISRC_TRIM_W 6 -#define ADI_4_AUX_ISRC_TRIM_M 0x000000FC -#define ADI_4_AUX_ISRC_TRIM_S 2 -#define ADI_4_AUX_ISRC_TRIM_11P75U 0x00000080 -#define ADI_4_AUX_ISRC_TRIM_4P5U 0x00000040 -#define ADI_4_AUX_ISRC_TRIM_2P0U 0x00000020 -#define ADI_4_AUX_ISRC_TRIM_1P0U 0x00000010 -#define ADI_4_AUX_ISRC_TRIM_0P5U 0x00000008 -#define ADI_4_AUX_ISRC_TRIM_0P25U 0x00000004 -#define ADI_4_AUX_ISRC_TRIM_NC 0x00000000 - -// Field: [0] EN -// -// Current source enable -#define ADI_4_AUX_ISRC_EN 0x00000001 -#define ADI_4_AUX_ISRC_EN_M 0x00000001 -#define ADI_4_AUX_ISRC_EN_S 0 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_COMP -// -//***************************************************************************** -// Field: [7] COMPA_REF_RES_EN -// -// Enables 400kohm resistance from COMPA reference node to ground. Used with -// COMPA_REF_CURR_EN to generate voltage reference for cap-sense. -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN 0x00000080 -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_M 0x00000080 -#define ADI_4_AUX_COMP_COMPA_REF_RES_EN_S 7 - -// Field: [6] COMPA_REF_CURR_EN -// -// Enables 2uA IPTAT current from ISRC to COMPA reference node. Requires -// ISRC.EN = 1. Used with COMPA_REF_RES_EN to generate voltage reference for -// cap-sense. -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN 0x00000040 -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_M 0x00000040 -#define ADI_4_AUX_COMP_COMPA_REF_CURR_EN_S 6 - -// Field: [5:3] LPM_BIAS_WIDTH_TRIM -// -// Internal. Only to be used through TI provided API. -#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_W 3 -#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_M 0x00000038 -#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_S 3 - -// Field: [2] COMPB_EN -// -// COMPB enable -#define ADI_4_AUX_COMP_COMPB_EN 0x00000004 -#define ADI_4_AUX_COMP_COMPB_EN_M 0x00000004 -#define ADI_4_AUX_COMP_COMPB_EN_S 2 - -// Field: [0] COMPA_EN -// -// COMPA enable -#define ADI_4_AUX_COMP_COMPA_EN 0x00000001 -#define ADI_4_AUX_COMP_COMPA_EN_M 0x00000001 -#define ADI_4_AUX_COMP_COMPA_EN_S 0 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_MUX4 -// -//***************************************************************************** -// Field: [7:0] COMPA_REF -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// AUXIO19 Internal. Only to be used through TI provided API. -// AUXIO20 Internal. Only to be used through TI provided API. -// AUXIO21 Internal. Only to be used through TI provided API. -// AUXIO22 Internal. Only to be used through TI provided API. -// AUXIO23 Internal. Only to be used through TI provided API. -// AUXIO24 Internal. Only to be used through TI provided API. -// AUXIO25 Internal. Only to be used through TI provided API. -// AUXIO26 Internal. Only to be used through TI provided API. -// NC Internal. Only to be used through TI provided API. -#define ADI_4_AUX_MUX4_COMPA_REF_W 8 -#define ADI_4_AUX_MUX4_COMPA_REF_M 0x000000FF -#define ADI_4_AUX_MUX4_COMPA_REF_S 0 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO19 0x00000080 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO20 0x00000040 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO21 0x00000020 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO22 0x00000010 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO23 0x00000008 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO24 0x00000004 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO25 0x00000002 -#define ADI_4_AUX_MUX4_COMPA_REF_AUXIO26 0x00000001 -#define ADI_4_AUX_MUX4_COMPA_REF_NC 0x00000000 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_ADC0 -// -//***************************************************************************** -// Field: [7] SMPL_MODE -// -// ADC Sampling mode: -// -// 0: Synchronous mode -// 1: Asynchronous mode -// -// The ADC does a sample-and-hold before conversion. In synchronous mode the -// sampling starts when the ADC clock detects a rising edge on the trigger -// signal. Jitter/uncertainty will be inferred in the detection if the trigger -// signal originates from a domain that is asynchronous to the ADC clock. -// SMPL_CYCLE_EXP determines the the duration of sampling. -// Conversion starts immediately after sampling ends. -// -// In asynchronous mode the sampling is continuous when enabled. Sampling ends -// and conversion starts immediately with the rising edge of the trigger -// signal. Sampling restarts when the conversion has finished. -// Asynchronous mode is useful when it is important to avoid jitter in the -// sampling instant of an externally driven signal -#define ADI_4_AUX_ADC0_SMPL_MODE 0x00000080 -#define ADI_4_AUX_ADC0_SMPL_MODE_M 0x00000080 -#define ADI_4_AUX_ADC0_SMPL_MODE_S 7 - -// Field: [6:3] SMPL_CYCLE_EXP -// -// Controls the sampling duration before conversion when the ADC is operated in -// synchronous mode (SMPL_MODE = 0). The setting has no effect in asynchronous -// mode. The sampling duration is given as 2^(SMPL_CYCLE_EXP + 1) / 6 us. -// ENUMs: -// 10P9_MS 65536x 6 MHz clock periods = 10.9ms -// 5P46_MS 32768x 6 MHz clock periods = 5.46ms -// 2P73_MS 16384x 6 MHz clock periods = 2.73ms -// 1P37_MS 8192x 6 MHz clock periods = 1.37ms -// 682_US 4096x 6 MHz clock periods = 682us -// 341_US 2048x 6 MHz clock periods = 341us -// 170_US 1024x 6 MHz clock periods = 170us -// 85P3_US 512x 6 MHz clock periods = 85.3us -// 42P6_US 256x 6 MHz clock periods = 42.6us -// 21P3_US 128x 6 MHz clock periods = 21.3us -// 10P6_US 64x 6 MHz clock periods = 10.6us -// 5P3_US 32x 6 MHz clock periods = 5.3us -// 2P7_US 16x 6 MHz clock periods = 2.7us -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_W 4 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_M 0x00000078 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_S 3 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P9_MS 0x00000078 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P46_MS 0x00000070 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P73_MS 0x00000068 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_1P37_MS 0x00000060 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_682_US 0x00000058 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_341_US 0x00000050 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_170_US 0x00000048 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_85P3_US 0x00000040 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_42P6_US 0x00000038 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_21P3_US 0x00000030 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_10P6_US 0x00000028 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_5P3_US 0x00000020 -#define ADI_4_AUX_ADC0_SMPL_CYCLE_EXP_2P7_US 0x00000018 - -// Field: [1] RESET_N -// -// Reset ADC digital subchip, active low. ADC must be reset every time it is -// reconfigured. -// -// 0: Reset -// 1: Normal operation -#define ADI_4_AUX_ADC0_RESET_N 0x00000002 -#define ADI_4_AUX_ADC0_RESET_N_M 0x00000002 -#define ADI_4_AUX_ADC0_RESET_N_S 1 - -// Field: [0] EN -// -// ADC Enable -// -// 0: Disable -// 1: Enable -#define ADI_4_AUX_ADC0_EN 0x00000001 -#define ADI_4_AUX_ADC0_EN_M 0x00000001 -#define ADI_4_AUX_ADC0_EN_S 0 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_ADC1 -// -//***************************************************************************** -// Field: [0] SCALE_DIS -// -// Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADC1_SCALE_DIS 0x00000001 -#define ADI_4_AUX_ADC1_SCALE_DIS_M 0x00000001 -#define ADI_4_AUX_ADC1_SCALE_DIS_S 0 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_ADCREF0 -// -//***************************************************************************** -// Field: [6] REF_ON_IDLE -// -// Enable ADCREF in IDLE state. -// -// 0: Disabled in IDLE state -// 1: Enabled in IDLE state -// -// Keep ADCREF enabled when ADC0.SMPL_MODE = 0. -// Recommendation: Enable ADCREF always when ADC0.SMPL_CYCLE_EXP is less than -// 0x6 (21.3us sampling time). -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE 0x00000040 -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_M 0x00000040 -#define ADI_4_AUX_ADCREF0_REF_ON_IDLE_S 6 - -// Field: [5] IOMUX -// -// Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADCREF0_IOMUX 0x00000020 -#define ADI_4_AUX_ADCREF0_IOMUX_M 0x00000020 -#define ADI_4_AUX_ADCREF0_IOMUX_S 5 - -// Field: [4] EXT -// -// Internal. Only to be used through TI provided API. -#define ADI_4_AUX_ADCREF0_EXT 0x00000010 -#define ADI_4_AUX_ADCREF0_EXT_M 0x00000010 -#define ADI_4_AUX_ADCREF0_EXT_S 4 - -// Field: [3] SRC -// -// ADC reference source: -// -// 0: Fixed reference = 4.3V -// 1: Relative reference = VDDS -#define ADI_4_AUX_ADCREF0_SRC 0x00000008 -#define ADI_4_AUX_ADCREF0_SRC_M 0x00000008 -#define ADI_4_AUX_ADCREF0_SRC_S 3 - -// Field: [0] EN -// -// ADC reference module enable: -// -// 0: ADC reference module powered down -// 1: ADC reference module enabled -#define ADI_4_AUX_ADCREF0_EN 0x00000001 -#define ADI_4_AUX_ADCREF0_EN_M 0x00000001 -#define ADI_4_AUX_ADCREF0_EN_S 0 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_ADCREF1 -// -//***************************************************************************** -// Field: [5:0] VTRIM -// -// Trim output voltage of ADC fixed reference (64 steps, 2's complement). -// Applies only for ADCREF0.SRC = 0. -// -// Examples: -// 0x00 - nominal voltage 1.43V -// 0x01 - nominal + 0.4% 1.435V -// 0x3F - nominal - 0.4% 1.425V -// 0x1F - maximum voltage 1.6V -// 0x20 - minimum voltage 1.3V -#define ADI_4_AUX_ADCREF1_VTRIM_W 6 -#define ADI_4_AUX_ADCREF1_VTRIM_M 0x0000003F -#define ADI_4_AUX_ADCREF1_VTRIM_S 0 - -//***************************************************************************** -// -// Register: ADI_4_AUX_O_LPMBIAS -// -//***************************************************************************** -// Field: [5:0] LPM_TRIM_IOUT -// -// Internal. Only to be used through TI provided API. -#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_W 6 -#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_M 0x0000003F -#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_S 0 - - -#endif // __ADI_4_AUX__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h deleted file mode 100644 index ded130e5006..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_batmon.h +++ /dev/null @@ -1,662 +0,0 @@ -/****************************************************************************** -* Filename: hw_aon_batmon_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AON_BATMON_H__ -#define __HW_AON_BATMON_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AON_BATMON component -// -//***************************************************************************** -// Internal -#define AON_BATMON_O_CTL 0x00000000 - -// Internal -#define AON_BATMON_O_MEASCFG 0x00000004 - -// Internal -#define AON_BATMON_O_TEMPP0 0x0000000C - -// Internal -#define AON_BATMON_O_TEMPP1 0x00000010 - -// Internal -#define AON_BATMON_O_TEMPP2 0x00000014 - -// Internal -#define AON_BATMON_O_BATMONP0 0x00000018 - -// Internal -#define AON_BATMON_O_BATMONP1 0x0000001C - -// Internal -#define AON_BATMON_O_IOSTRP0 0x00000020 - -// Internal -#define AON_BATMON_O_FLASHPUMPP0 0x00000024 - -// Last Measured Battery Voltage -#define AON_BATMON_O_BAT 0x00000028 - -// Battery Update -#define AON_BATMON_O_BATUPD 0x0000002C - -// Temperature -#define AON_BATMON_O_TEMP 0x00000030 - -// Temperature Update -#define AON_BATMON_O_TEMPUPD 0x00000034 - -// Event Mask -#define AON_BATMON_O_EVENTMASK 0x00000048 - -// Event -#define AON_BATMON_O_EVENT 0x0000004C - -// Battery Upper Limit -#define AON_BATMON_O_BATTUL 0x00000050 - -// Battery Lower Limit -#define AON_BATMON_O_BATTLL 0x00000054 - -// Temperature Upper Limit -#define AON_BATMON_O_TEMPUL 0x00000058 - -// Temperature Lower Limit -#define AON_BATMON_O_TEMPLL 0x0000005C - -//***************************************************************************** -// -// Register: AON_BATMON_O_CTL -// -//***************************************************************************** -// Field: [1] CALC_EN -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_CTL_CALC_EN 0x00000002 -#define AON_BATMON_CTL_CALC_EN_BITN 1 -#define AON_BATMON_CTL_CALC_EN_M 0x00000002 -#define AON_BATMON_CTL_CALC_EN_S 1 - -// Field: [0] MEAS_EN -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_CTL_MEAS_EN 0x00000001 -#define AON_BATMON_CTL_MEAS_EN_BITN 0 -#define AON_BATMON_CTL_MEAS_EN_M 0x00000001 -#define AON_BATMON_CTL_MEAS_EN_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_MEASCFG -// -//***************************************************************************** -// Field: [1:0] PER -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// 32CYC Internal. Only to be used through TI provided API. -// 16CYC Internal. Only to be used through TI provided API. -// 8CYC Internal. Only to be used through TI provided API. -// CONT Internal. Only to be used through TI provided API. -#define AON_BATMON_MEASCFG_PER_W 2 -#define AON_BATMON_MEASCFG_PER_M 0x00000003 -#define AON_BATMON_MEASCFG_PER_S 0 -#define AON_BATMON_MEASCFG_PER_32CYC 0x00000003 -#define AON_BATMON_MEASCFG_PER_16CYC 0x00000002 -#define AON_BATMON_MEASCFG_PER_8CYC 0x00000001 -#define AON_BATMON_MEASCFG_PER_CONT 0x00000000 - -//***************************************************************************** -// -// Register: AON_BATMON_O_TEMPP0 -// -//***************************************************************************** -// Field: [7:0] CFG -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP0_CFG_W 8 -#define AON_BATMON_TEMPP0_CFG_M 0x000000FF -#define AON_BATMON_TEMPP0_CFG_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_TEMPP1 -// -//***************************************************************************** -// Field: [5:0] CFG -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP1_CFG_W 6 -#define AON_BATMON_TEMPP1_CFG_M 0x0000003F -#define AON_BATMON_TEMPP1_CFG_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_TEMPP2 -// -//***************************************************************************** -// Field: [4:0] CFG -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_TEMPP2_CFG_W 5 -#define AON_BATMON_TEMPP2_CFG_M 0x0000001F -#define AON_BATMON_TEMPP2_CFG_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_BATMONP0 -// -//***************************************************************************** -// Field: [6:0] CFG -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_BATMONP0_CFG_W 7 -#define AON_BATMON_BATMONP0_CFG_M 0x0000007F -#define AON_BATMON_BATMONP0_CFG_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_BATMONP1 -// -//***************************************************************************** -// Field: [5:0] CFG -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_BATMONP1_CFG_W 6 -#define AON_BATMON_BATMONP1_CFG_M 0x0000003F -#define AON_BATMON_BATMONP1_CFG_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_IOSTRP0 -// -//***************************************************************************** -// Field: [5:4] CFG2 -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_IOSTRP0_CFG2_W 2 -#define AON_BATMON_IOSTRP0_CFG2_M 0x00000030 -#define AON_BATMON_IOSTRP0_CFG2_S 4 - -// Field: [3:0] CFG1 -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_IOSTRP0_CFG1_W 4 -#define AON_BATMON_IOSTRP0_CFG1_M 0x0000000F -#define AON_BATMON_IOSTRP0_CFG1_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_FLASHPUMPP0 -// -//***************************************************************************** -// Field: [9] DIS_NOISE_FILTER -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER 0x00000200 -#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_BITN 9 -#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_M 0x00000200 -#define AON_BATMON_FLASHPUMPP0_DIS_NOISE_FILTER_S 9 - -// Field: [8] FALLB -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_FALLB 0x00000100 -#define AON_BATMON_FLASHPUMPP0_FALLB_BITN 8 -#define AON_BATMON_FLASHPUMPP0_FALLB_M 0x00000100 -#define AON_BATMON_FLASHPUMPP0_FALLB_S 8 - -// Field: [7:6] HIGHLIM -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_W 2 -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_M 0x000000C0 -#define AON_BATMON_FLASHPUMPP0_HIGHLIM_S 6 - -// Field: [5] LOWLIM -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_LOWLIM 0x00000020 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_BITN 5 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_M 0x00000020 -#define AON_BATMON_FLASHPUMPP0_LOWLIM_S 5 - -// Field: [4] OVR -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_OVR 0x00000010 -#define AON_BATMON_FLASHPUMPP0_OVR_BITN 4 -#define AON_BATMON_FLASHPUMPP0_OVR_M 0x00000010 -#define AON_BATMON_FLASHPUMPP0_OVR_S 4 - -// Field: [3:0] CFG -// -// Internal. Only to be used through TI provided API. -#define AON_BATMON_FLASHPUMPP0_CFG_W 4 -#define AON_BATMON_FLASHPUMPP0_CFG_M 0x0000000F -#define AON_BATMON_FLASHPUMPP0_CFG_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_BAT -// -//***************************************************************************** -// Field: [10:8] INT -// -// Integer part: -// -// 0x0: 0V + fractional part -// ... -// 0x3: 3V + fractional part -// 0x4: 4V + fractional part -#define AON_BATMON_BAT_INT_W 3 -#define AON_BATMON_BAT_INT_M 0x00000700 -#define AON_BATMON_BAT_INT_S 8 - -// Field: [7:0] FRAC -// -// Fractional part, standard binary fractional encoding. -// -// 0x00: .0V -// ... -// 0x20: 1/8 = .125V -// 0x40: 1/4 = .25V -// 0x80: 1/2 = .5V -// ... -// 0xA0: 1/2 + 1/8 = .625V -// ... -// 0xFF: Max -#define AON_BATMON_BAT_FRAC_W 8 -#define AON_BATMON_BAT_FRAC_M 0x000000FF -#define AON_BATMON_BAT_FRAC_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_BATUPD -// -//***************************************************************************** -// Field: [0] STAT -// -// -// 0: No update since last clear -// 1: New battery voltage is present. -// -// Write 1 to clear the status. -#define AON_BATMON_BATUPD_STAT 0x00000001 -#define AON_BATMON_BATUPD_STAT_BITN 0 -#define AON_BATMON_BATUPD_STAT_M 0x00000001 -#define AON_BATMON_BATUPD_STAT_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_TEMP -// -//***************************************************************************** -// Field: [16:8] INT -// -// Integer part (signed) of temperature value. -// Total value = INTEGER + FRACTIONAL -// 2's complement encoding -// -// 0x100: Min value -// 0x1D8: -40C -// 0x1FF: -1C -// 0x00: 0C -// 0x1B: 27C -// 0x55: 85C -// 0xFF: Max value -#define AON_BATMON_TEMP_INT_W 9 -#define AON_BATMON_TEMP_INT_M 0x0001FF00 -#define AON_BATMON_TEMP_INT_S 8 - -//***************************************************************************** -// -// Register: AON_BATMON_O_TEMPUPD -// -//***************************************************************************** -// Field: [0] STAT -// -// -// 0: No update since last clear -// 1: New temperature is present. -// -// Write 1 to clear the status. -#define AON_BATMON_TEMPUPD_STAT 0x00000001 -#define AON_BATMON_TEMPUPD_STAT_BITN 0 -#define AON_BATMON_TEMPUPD_STAT_M 0x00000001 -#define AON_BATMON_TEMPUPD_STAT_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_EVENTMASK -// -//***************************************************************************** -// Field: [5] TEMP_UPDATE_MASK -// -// 1: EVENT.TEMP_UPDATE contributes to combined event from BATMON -// 0: EVENT.TEMP_UPDATE does not contribute to combined event from BATMON -#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK 0x00000020 -#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_BITN 5 -#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_M 0x00000020 -#define AON_BATMON_EVENTMASK_TEMP_UPDATE_MASK_S 5 - -// Field: [4] BATT_UPDATE_MASK -// -// 1: EVENT.BATT_UPDATE contributes to combined event from BATMON -// 0: EVENT.BATT_UPDATE does not contribute to combined event from BATMON -#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK 0x00000010 -#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_BITN 4 -#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_M 0x00000010 -#define AON_BATMON_EVENTMASK_BATT_UPDATE_MASK_S 4 - -// Field: [3] TEMP_BELOW_LL_MASK -// -// 1: EVENT.TEMP_BELOW_LL contributes to combined event from BATMON -// 0: EVENT.TEMP_BELOW_LL does not contribute to combined event from BATMON -#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK 0x00000008 -#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_BITN 3 -#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_M 0x00000008 -#define AON_BATMON_EVENTMASK_TEMP_BELOW_LL_MASK_S 3 - -// Field: [2] TEMP_OVER_UL_MASK -// -// 1: EVENT.TEMP_OVER_UL contributes to combined event from BATMON -// 0: EVENT.TEMP_OVER_UL does not contribute to combined event from BATMON -#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK 0x00000004 -#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_BITN 2 -#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_M 0x00000004 -#define AON_BATMON_EVENTMASK_TEMP_OVER_UL_MASK_S 2 - -// Field: [1] BATT_BELOW_LL_MASK -// -// 1: EVENT.BATT_BELOW_LL contributes to combined event from BATMON -// 0: EVENT.BATT_BELOW_LL does not contribute to combined event from BATMON -#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK 0x00000002 -#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_BITN 1 -#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_M 0x00000002 -#define AON_BATMON_EVENTMASK_BATT_BELOW_LL_MASK_S 1 - -// Field: [0] BATT_OVER_UL_MASK -// -// 1: EVENT.BATT_OVER_UL contributes to combined event from BATMON -// 0: EVENT.BATT_OVER_UL does not contribute to combined event from BATMON -#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK 0x00000001 -#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_BITN 0 -#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_M 0x00000001 -#define AON_BATMON_EVENTMASK_BATT_OVER_UL_MASK_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_EVENT -// -//***************************************************************************** -// Field: [5] TEMP_UPDATE -// -// Alias to TEMPUPD.STAT -#define AON_BATMON_EVENT_TEMP_UPDATE 0x00000020 -#define AON_BATMON_EVENT_TEMP_UPDATE_BITN 5 -#define AON_BATMON_EVENT_TEMP_UPDATE_M 0x00000020 -#define AON_BATMON_EVENT_TEMP_UPDATE_S 5 - -// Field: [4] BATT_UPDATE -// -// Alias to BATUPD.STAT -#define AON_BATMON_EVENT_BATT_UPDATE 0x00000010 -#define AON_BATMON_EVENT_BATT_UPDATE_BITN 4 -#define AON_BATMON_EVENT_BATT_UPDATE_M 0x00000010 -#define AON_BATMON_EVENT_BATT_UPDATE_S 4 - -// Field: [3] TEMP_BELOW_LL -// -// Read: -// 1: Temperature level is below the lower limit set by TEMPLL. -// 0: Temperature level is not below the lower limit set by TEMPLL. -// Write: -// 1: Clears the flag -// 0: No change in the flag -#define AON_BATMON_EVENT_TEMP_BELOW_LL 0x00000008 -#define AON_BATMON_EVENT_TEMP_BELOW_LL_BITN 3 -#define AON_BATMON_EVENT_TEMP_BELOW_LL_M 0x00000008 -#define AON_BATMON_EVENT_TEMP_BELOW_LL_S 3 - -// Field: [2] TEMP_OVER_UL -// -// Read: -// 1: Temperature level is above the upper limit set by TEMPUL. -// 0: Temperature level is not above the upper limit set by TEMPUL. -// Write: -// 1: Clears the flag -// 0: No change in the flag -#define AON_BATMON_EVENT_TEMP_OVER_UL 0x00000004 -#define AON_BATMON_EVENT_TEMP_OVER_UL_BITN 2 -#define AON_BATMON_EVENT_TEMP_OVER_UL_M 0x00000004 -#define AON_BATMON_EVENT_TEMP_OVER_UL_S 2 - -// Field: [1] BATT_BELOW_LL -// -// Read: -// 1: Battery level is below the lower limit set by BATTLL. -// 0: Battery level is not below the lower limit set by BATTLL. -// Write: -// 1: Clears the flag -// 0: No change in the flag -#define AON_BATMON_EVENT_BATT_BELOW_LL 0x00000002 -#define AON_BATMON_EVENT_BATT_BELOW_LL_BITN 1 -#define AON_BATMON_EVENT_BATT_BELOW_LL_M 0x00000002 -#define AON_BATMON_EVENT_BATT_BELOW_LL_S 1 - -// Field: [0] BATT_OVER_UL -// -// Read: -// 1: Battery level is above the upper limit set by BATTUL. -// 0: Battery level is not above the upper limit set by BATTUL. -// Write: -// 1: Clears the flag -// 0: No change in the flag -#define AON_BATMON_EVENT_BATT_OVER_UL 0x00000001 -#define AON_BATMON_EVENT_BATT_OVER_UL_BITN 0 -#define AON_BATMON_EVENT_BATT_OVER_UL_M 0x00000001 -#define AON_BATMON_EVENT_BATT_OVER_UL_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_BATTUL -// -//***************************************************************************** -// Field: [10:8] INT -// -// Integer part: -// -// 0x0: 0V + fractional part -// ... -// 0x3: 3V + fractional part -// 0x4: 4V + fractional part -#define AON_BATMON_BATTUL_INT_W 3 -#define AON_BATMON_BATTUL_INT_M 0x00000700 -#define AON_BATMON_BATTUL_INT_S 8 - -// Field: [7:0] FRAC -// -// Fractional part, standard binary fractional encoding. -// -// 0x00: .0V -// ... -// 0x20: 1/8 = .125V -// 0x40: 1/4 = .25V -// 0x80: 1/2 = .5V -// ... -// 0xA0: 1/2 + 1/8 = .625V -// ... -// 0xFF: Max -#define AON_BATMON_BATTUL_FRAC_W 8 -#define AON_BATMON_BATTUL_FRAC_M 0x000000FF -#define AON_BATMON_BATTUL_FRAC_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_BATTLL -// -//***************************************************************************** -// Field: [10:8] INT -// -// Integer part: -// -// 0x0: 0V + fractional part -// ... -// 0x3: 3V + fractional part -// 0x4: 4V + fractional part -#define AON_BATMON_BATTLL_INT_W 3 -#define AON_BATMON_BATTLL_INT_M 0x00000700 -#define AON_BATMON_BATTLL_INT_S 8 - -// Field: [7:0] FRAC -// -// Fractional part, standard binary fractional encoding. -// -// 0x00: .0V -// ... -// 0x20: 1/8 = .125V -// 0x40: 1/4 = .25V -// 0x80: 1/2 = .5V -// ... -// 0xA0: 1/2 + 1/8 = .625V -// ... -// 0xFF: Max -#define AON_BATMON_BATTLL_FRAC_W 8 -#define AON_BATMON_BATTLL_FRAC_M 0x000000FF -#define AON_BATMON_BATTLL_FRAC_S 0 - -//***************************************************************************** -// -// Register: AON_BATMON_O_TEMPUL -// -//***************************************************************************** -// Field: [16:8] INT -// -// Integer part (signed) of temperature upper limit. -// Total value = INTEGER + FRACTIONAL -// 2's complement encoding -// -// 0x100: Min value -// 0x1D8: -40C -// 0x1FF: -1C -// 0x00: 0C -// 0x1B: 27C -// 0x55: 85C -// 0xFF: Max value -#define AON_BATMON_TEMPUL_INT_W 9 -#define AON_BATMON_TEMPUL_INT_M 0x0001FF00 -#define AON_BATMON_TEMPUL_INT_S 8 - -// Field: [7:6] FRAC -// -// Fractional part of temperature upper limit. -// Total value = INTEGER + FRACTIONAL -// The encoding is an extension of the 2's complement encoding. -// -// 00: 0.0C -// 01: 0.25C -// 10: 0.5C -// 11: 0.75C -// -// For example: -// 000000001,00 = ( 1+0,00) = 1,00 -// 000000000,11 = ( 0+0,75) = 0,75 -// 000000000,10 = ( 0+0,50) = 0,50 -// 000000000,01 = ( 0+0,25) = 0,25 -// 000000000,00 = ( 0+0,00) = 0,00 -// 111111111,11 = (-1+0,75) = -0,25 -// 111111111,10 = (-1+0,50) = -0,50 -// 111111111,01 = (-1+0,25) = -0,75 -// 111111111,00 = (-1+0,00) = -1,00 -// 111111110,11 = (-2+0,75) = -1,25 -#define AON_BATMON_TEMPUL_FRAC_W 2 -#define AON_BATMON_TEMPUL_FRAC_M 0x000000C0 -#define AON_BATMON_TEMPUL_FRAC_S 6 - -//***************************************************************************** -// -// Register: AON_BATMON_O_TEMPLL -// -//***************************************************************************** -// Field: [16:8] INT -// -// Integer part (signed) of temperature lower limit. -// Total value = INTEGER + FRACTIONAL -// 2's complement encoding -// -// 0x100: Min value -// 0x1D8: -40C -// 0x1FF: -1C -// 0x00: 0C -// 0x1B: 27C -// 0x55: 85C -// 0xFF: Max value -#define AON_BATMON_TEMPLL_INT_W 9 -#define AON_BATMON_TEMPLL_INT_M 0x0001FF00 -#define AON_BATMON_TEMPLL_INT_S 8 - -// Field: [7:6] FRAC -// -// Fractional part of temperature lower limit. -// Total value = INTEGER + FRACTIONAL -// The encoding is an extension of the 2's complement encoding. -// -// 00: 0.0C -// 01: 0.25C -// 10: 0.5C -// 11: 0.75C -// -// For example: -// 000000001,00 = ( 1+0,00) = 1,00 -// 000000000,11 = ( 0+0,75) = 0,75 -// 000000000,10 = ( 0+0,50) = 0,50 -// 000000000,01 = ( 0+0,25) = 0,25 -// 000000000,00 = ( 0+0,00) = 0,00 -// 111111111,11 = (-1+0,75) = -0,25 -// 111111111,10 = (-1+0,50) = -0,50 -// 111111111,01 = (-1+0,25) = -0,75 -// 111111111,00 = (-1+0,00) = -1,00 -// 111111110,11 = (-2+0,75) = -1,25 -#define AON_BATMON_TEMPLL_FRAC_W 2 -#define AON_BATMON_TEMPLL_FRAC_M 0x000000C0 -#define AON_BATMON_TEMPLL_FRAC_S 6 - - -#endif // __AON_BATMON__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h deleted file mode 100644 index 81c93f387bc..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_event.h +++ /dev/null @@ -1,1135 +0,0 @@ -/****************************************************************************** -* Filename: hw_aon_event_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AON_EVENT_H__ -#define __HW_AON_EVENT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AON_EVENT component -// -//***************************************************************************** -// Wake-up Selector For MCU -#define AON_EVENT_O_MCUWUSEL 0x00000000 - -// Wake-up Selector For MCU -#define AON_EVENT_O_MCUWUSEL1 0x00000004 - -// Event Selector For MCU Event Fabric -#define AON_EVENT_O_EVTOMCUSEL 0x00000008 - -// RTC Capture Event Selector For AON_RTC -#define AON_EVENT_O_RTCSEL 0x0000000C - -//***************************************************************************** -// -// Register: AON_EVENT_O_MCUWUSEL -// -//***************************************************************************** -// Field: [29:24] WU3_EV -// -// MCU Wakeup Source #3 -// -// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up -// the MCU domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// BATMON_COMBINED Combined event from BATMON -// BATMON_TEMP_LL BATMON event: Temperature level below lower limit -// BATMON_TEMP_UL BATMON event: Temperature level above upper limit -// BATMON_BATT_LL BATMON event: Battery level below lower limit -// BATMON_BATT_UL BATMON event: Battery level above upper limit -// AUX_TIMER2_EV3 Event 3 from AUX TImer2 -// AUX_TIMER2_EV2 Event 2 from AUX TImer2 -// AUX_TIMER2_EV1 Event 1 from AUX TImer2 -// AUX_TIMER2_EV0 Event 0 from AUX TImer2 -// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have -// enabled contribution to IOEV_MCU_WU in -// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL_WU3_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU3_EV_M 0x3F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_S 24 -#define AON_EVENT_MCUWUSEL_WU3_EV_NONE 0x3F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC_N 0x38000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB_ASYNC 0x37000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_VOLT 0x36000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP 0x35000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER1_EV 0x34000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER0_EV 0x33000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TDC_DONE 0x32000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_ADC_DONE 0x31000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPB 0x30000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_COMPA 0x2F000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV2 0x2E000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV1 0x2D000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_SWEV0 0x2C000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_JTAG 0x2B000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_UPD 0x2A000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_COMB_DLY 0x29000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2_DLY 0x28000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1_DLY 0x27000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0_DLY 0x26000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH2 0x25000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH1 0x24000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_RTC_CH0 0x23000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_PAD 0x20000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_COMBINED 0x09000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP_LL 0x08000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_TEMP_UL 0x07000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_BATT_LL 0x06000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_BATMON_BATT_UL 0x05000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV3 0x04000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV2 0x03000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV1 0x02000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_AUX_TIMER2_EV0 0x01000000 -#define AON_EVENT_MCUWUSEL_WU3_EV_IOEV_MCU_WU 0x00000000 - -// Field: [21:16] WU2_EV -// -// MCU Wakeup Source #2 -// -// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up -// the MCU domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// BATMON_COMBINED Combined event from BATMON -// BATMON_TEMP_LL BATMON event: Temperature level below lower limit -// BATMON_TEMP_UL BATMON event: Temperature level above upper limit -// BATMON_BATT_LL BATMON event: Battery level below lower limit -// BATMON_BATT_UL BATMON event: Battery level above upper limit -// AUX_TIMER2_EV3 Event 3 from AUX TImer2 -// AUX_TIMER2_EV2 Event 2 from AUX TImer2 -// AUX_TIMER2_EV1 Event 1 from AUX TImer2 -// AUX_TIMER2_EV0 Event 0 from AUX TImer2 -// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have -// enabled contribution to IOEV_MCU_WU in -// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL_WU2_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU2_EV_M 0x003F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_S 16 -#define AON_EVENT_MCUWUSEL_WU2_EV_NONE 0x003F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_JTAG 0x002B0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_MCUWUSEL_WU2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_MCUWUSEL_WU2_EV_PAD 0x00200000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_COMBINED 0x00090000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP_LL 0x00080000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_TEMP_UL 0x00070000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_BATT_LL 0x00060000 -#define AON_EVENT_MCUWUSEL_WU2_EV_BATMON_BATT_UL 0x00050000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV3 0x00040000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV2 0x00030000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV1 0x00020000 -#define AON_EVENT_MCUWUSEL_WU2_EV_AUX_TIMER2_EV0 0x00010000 -#define AON_EVENT_MCUWUSEL_WU2_EV_IOEV_MCU_WU 0x00000000 - -// Field: [13:8] WU1_EV -// -// MCU Wakeup Source #1 -// -// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up -// the MCU domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// BATMON_COMBINED Combined event from BATMON -// BATMON_TEMP_LL BATMON event: Temperature level below lower limit -// BATMON_TEMP_UL BATMON event: Temperature level above upper limit -// BATMON_BATT_LL BATMON event: Battery level below lower limit -// BATMON_BATT_UL BATMON event: Battery level above upper limit -// AUX_TIMER2_EV3 Event 3 from AUX TImer2 -// AUX_TIMER2_EV2 Event 2 from AUX TImer2 -// AUX_TIMER2_EV1 Event 1 from AUX TImer2 -// AUX_TIMER2_EV0 Event 0 from AUX TImer2 -// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have -// enabled contribution to IOEV_MCU_WU in -// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL_WU1_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU1_EV_M 0x00003F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_S 8 -#define AON_EVENT_MCUWUSEL_WU1_EV_NONE 0x00003F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_MCUWUSEL_WU1_EV_JTAG 0x00002B00 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_MCUWUSEL_WU1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_MCUWUSEL_WU1_EV_PAD 0x00002000 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_COMBINED 0x00000900 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP_LL 0x00000800 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_TEMP_UL 0x00000700 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_BATT_LL 0x00000600 -#define AON_EVENT_MCUWUSEL_WU1_EV_BATMON_BATT_UL 0x00000500 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV3 0x00000400 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV2 0x00000300 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV1 0x00000200 -#define AON_EVENT_MCUWUSEL_WU1_EV_AUX_TIMER2_EV0 0x00000100 -#define AON_EVENT_MCUWUSEL_WU1_EV_IOEV_MCU_WU 0x00000000 - -// Field: [5:0] WU0_EV -// -// MCU Wakeup Source #0 -// -// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up -// the MCU domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// BATMON_COMBINED Combined event from BATMON -// BATMON_TEMP_LL BATMON event: Temperature level below lower limit -// BATMON_TEMP_UL BATMON event: Temperature level above upper limit -// BATMON_BATT_LL BATMON event: Battery level below lower limit -// BATMON_BATT_UL BATMON event: Battery level above upper limit -// AUX_TIMER2_EV3 Event 3 from AUX TImer2 -// AUX_TIMER2_EV2 Event 2 from AUX TImer2 -// AUX_TIMER2_EV1 Event 1 from AUX TImer2 -// AUX_TIMER2_EV0 Event 0 from AUX TImer2 -// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have -// enabled contribution to IOEV_MCU_WU in -// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL_WU0_EV_W 6 -#define AON_EVENT_MCUWUSEL_WU0_EV_M 0x0000003F -#define AON_EVENT_MCUWUSEL_WU0_EV_S 0 -#define AON_EVENT_MCUWUSEL_WU0_EV_NONE 0x0000003F -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_MCUWUSEL_WU0_EV_JTAG 0x0000002B -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_MCUWUSEL_WU0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_MCUWUSEL_WU0_EV_PAD 0x00000020 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_COMBINED 0x00000009 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP_LL 0x00000008 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_TEMP_UL 0x00000007 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_BATT_LL 0x00000006 -#define AON_EVENT_MCUWUSEL_WU0_EV_BATMON_BATT_UL 0x00000005 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV3 0x00000004 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV2 0x00000003 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV1 0x00000002 -#define AON_EVENT_MCUWUSEL_WU0_EV_AUX_TIMER2_EV0 0x00000001 -#define AON_EVENT_MCUWUSEL_WU0_EV_IOEV_MCU_WU 0x00000000 - -//***************************************************************************** -// -// Register: AON_EVENT_O_MCUWUSEL1 -// -//***************************************************************************** -// Field: [29:24] WU7_EV -// -// MCU Wakeup Source #7 -// -// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up -// the MCU domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// BATMON_COMBINED Combined event from BATMON -// BATMON_TEMP_LL BATMON event: Temperature level below lower limit -// BATMON_TEMP_UL BATMON event: Temperature level above upper limit -// BATMON_BATT_LL BATMON event: Battery level below lower limit -// BATMON_BATT_UL BATMON event: Battery level above upper limit -// AUX_TIMER2_EV3 Event 3 from AUX TImer2 -// AUX_TIMER2_EV2 Event 2 from AUX TImer2 -// AUX_TIMER2_EV1 Event 1 from AUX TImer2 -// AUX_TIMER2_EV0 Event 0 from AUX TImer2 -// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have -// enabled contribution to IOEV_MCU_WU in -// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL1_WU7_EV_W 6 -#define AON_EVENT_MCUWUSEL1_WU7_EV_M 0x3F000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_S 24 -#define AON_EVENT_MCUWUSEL1_WU7_EV_NONE 0x3F000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB_ASYNC_N 0x38000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB_ASYNC 0x37000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_VOLT 0x36000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP 0x35000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER1_EV 0x34000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER0_EV 0x33000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TDC_DONE 0x32000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_ADC_DONE 0x31000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPB 0x30000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_COMPA 0x2F000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV2 0x2E000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV1 0x2D000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_SWEV0 0x2C000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_JTAG 0x2B000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_UPD 0x2A000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_COMB_DLY 0x29000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH2_DLY 0x28000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH1_DLY 0x27000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH0_DLY 0x26000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH2 0x25000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH1 0x24000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_RTC_CH0 0x23000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_PAD 0x20000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_COMBINED 0x09000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP_LL 0x08000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_TEMP_UL 0x07000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_BATT_LL 0x06000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_BATMON_BATT_UL 0x05000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV3 0x04000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV2 0x03000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV1 0x02000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_AUX_TIMER2_EV0 0x01000000 -#define AON_EVENT_MCUWUSEL1_WU7_EV_IOEV_MCU_WU 0x00000000 - -// Field: [21:16] WU6_EV -// -// MCU Wakeup Source #6 -// -// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up -// the MCU domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// BATMON_COMBINED Combined event from BATMON -// BATMON_TEMP_LL BATMON event: Temperature level below lower limit -// BATMON_TEMP_UL BATMON event: Temperature level above upper limit -// BATMON_BATT_LL BATMON event: Battery level below lower limit -// BATMON_BATT_UL BATMON event: Battery level above upper limit -// AUX_TIMER2_EV3 Event 3 from AUX TImer2 -// AUX_TIMER2_EV2 Event 2 from AUX TImer2 -// AUX_TIMER2_EV1 Event 1 from AUX TImer2 -// AUX_TIMER2_EV0 Event 0 from AUX TImer2 -// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have -// enabled contribution to IOEV_MCU_WU in -// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL1_WU6_EV_W 6 -#define AON_EVENT_MCUWUSEL1_WU6_EV_M 0x003F0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_S 16 -#define AON_EVENT_MCUWUSEL1_WU6_EV_NONE 0x003F0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_JTAG 0x002B0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH2 0x00250000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH1 0x00240000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_RTC_CH0 0x00230000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_PAD 0x00200000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_COMBINED 0x00090000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP_LL 0x00080000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_TEMP_UL 0x00070000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_BATT_LL 0x00060000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_BATMON_BATT_UL 0x00050000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV3 0x00040000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV2 0x00030000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV1 0x00020000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_AUX_TIMER2_EV0 0x00010000 -#define AON_EVENT_MCUWUSEL1_WU6_EV_IOEV_MCU_WU 0x00000000 - -// Field: [13:8] WU5_EV -// -// MCU Wakeup Source #5 -// -// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up -// the MCU domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// BATMON_COMBINED Combined event from BATMON -// BATMON_TEMP_LL BATMON event: Temperature level below lower limit -// BATMON_TEMP_UL BATMON event: Temperature level above upper limit -// BATMON_BATT_LL BATMON event: Battery level below lower limit -// BATMON_BATT_UL BATMON event: Battery level above upper limit -// AUX_TIMER2_EV3 Event 3 from AUX TImer2 -// AUX_TIMER2_EV2 Event 2 from AUX TImer2 -// AUX_TIMER2_EV1 Event 1 from AUX TImer2 -// AUX_TIMER2_EV0 Event 0 from AUX TImer2 -// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have -// enabled contribution to IOEV_MCU_WU in -// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL1_WU5_EV_W 6 -#define AON_EVENT_MCUWUSEL1_WU5_EV_M 0x00003F00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_S 8 -#define AON_EVENT_MCUWUSEL1_WU5_EV_NONE 0x00003F00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_JTAG 0x00002B00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH2 0x00002500 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH1 0x00002400 -#define AON_EVENT_MCUWUSEL1_WU5_EV_RTC_CH0 0x00002300 -#define AON_EVENT_MCUWUSEL1_WU5_EV_PAD 0x00002000 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_COMBINED 0x00000900 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP_LL 0x00000800 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_TEMP_UL 0x00000700 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_BATT_LL 0x00000600 -#define AON_EVENT_MCUWUSEL1_WU5_EV_BATMON_BATT_UL 0x00000500 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV3 0x00000400 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV2 0x00000300 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV1 0x00000200 -#define AON_EVENT_MCUWUSEL1_WU5_EV_AUX_TIMER2_EV0 0x00000100 -#define AON_EVENT_MCUWUSEL1_WU5_EV_IOEV_MCU_WU 0x00000000 - -// Field: [5:0] WU4_EV -// -// MCU Wakeup Source #4 -// -// AON Event Source selecting 1 of 8 events routed to AON_PMCTRL for waking up -// the MCU domain from Power Off or Power Down. -// Note: -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// BATMON_COMBINED Combined event from BATMON -// BATMON_TEMP_LL BATMON event: Temperature level below lower limit -// BATMON_TEMP_UL BATMON event: Temperature level above upper limit -// BATMON_BATT_LL BATMON event: Battery level below lower limit -// BATMON_BATT_UL BATMON event: Battery level above upper limit -// AUX_TIMER2_EV3 Event 3 from AUX TImer2 -// AUX_TIMER2_EV2 Event 2 from AUX TImer2 -// AUX_TIMER2_EV1 Event 1 from AUX TImer2 -// AUX_TIMER2_EV0 Event 0 from AUX TImer2 -// IOEV_MCU_WU Edge detect IO event from the DIO(s) which have -// enabled contribution to IOEV_MCU_WU in -// [MCU_IOC:IOCFGx.IOEV_MCU_WU_EN] -#define AON_EVENT_MCUWUSEL1_WU4_EV_W 6 -#define AON_EVENT_MCUWUSEL1_WU4_EV_M 0x0000003F -#define AON_EVENT_MCUWUSEL1_WU4_EV_S 0 -#define AON_EVENT_MCUWUSEL1_WU4_EV_NONE 0x0000003F -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_MCUWUSEL1_WU4_EV_JTAG 0x0000002B -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_UPD 0x0000002A -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH2 0x00000025 -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH1 0x00000024 -#define AON_EVENT_MCUWUSEL1_WU4_EV_RTC_CH0 0x00000023 -#define AON_EVENT_MCUWUSEL1_WU4_EV_PAD 0x00000020 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_COMBINED 0x00000009 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP_LL 0x00000008 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_TEMP_UL 0x00000007 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_BATT_LL 0x00000006 -#define AON_EVENT_MCUWUSEL1_WU4_EV_BATMON_BATT_UL 0x00000005 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV3 0x00000004 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV2 0x00000003 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV1 0x00000002 -#define AON_EVENT_MCUWUSEL1_WU4_EV_AUX_TIMER2_EV0 0x00000001 -#define AON_EVENT_MCUWUSEL1_WU4_EV_IOEV_MCU_WU 0x00000000 - -//***************************************************************************** -// -// Register: AON_EVENT_O_EVTOMCUSEL -// -//***************************************************************************** -// Field: [21:16] AON_PROG2_EV -// -// Event selector for AON_PROG2 event. -// -// AON Event Source id# selecting event routed to EVENT as AON_PROG2 event. -// ENUMs: -// NONE No event, always low -// AUX_COMPB_ASYNC_N Comparator B not triggered. Asynchronous signal -// directly from AUX Comparator B (inverted) as -// opposed to AUX_COMPB which is synchronized in -// AUX -// AUX_COMPB_ASYNC Comparator B triggered. Asynchronous signal -// directly from the AUX Comparator B as opposed -// to AUX_COMPB which is synchronized in AUX -// BATMON_VOLT BATMON voltage update event -// BATMON_TEMP BATMON temperature update event -// AUX_TIMER1_EV AUX Timer 1 Event -// AUX_TIMER0_EV AUX Timer 0 Event -// AUX_TDC_DONE TDC completed or timed out -// AUX_ADC_DONE ADC conversion completed -// AUX_COMPB Comparator B triggered -// AUX_COMPA Comparator A triggered -// AUX_SWEV2 AUX Software triggered event #2. Triggered by -// AUX_EVCTL:SWEVSET.SWEV2 -// AUX_SWEV1 AUX Software triggered event #1. Triggered by -// AUX_EVCTL:SWEVSET.SWEV1 -// AUX_SWEV0 AUX Software triggered event #0. Triggered by -// AUX_EVCTL:SWEVSET.SWEV0 -// JTAG JTAG generated event -// RTC_UPD RTC Update Tick (16 kHz signal, i.e. event line -// toggles value every 32 kHz clock period) -// RTC_COMB_DLY RTC combined delayed event -// RTC_CH2_DLY RTC channel 2 - delayed event -// RTC_CH1_DLY RTC channel 1 - delayed event -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// BATMON_COMBINED Combined event from BATMON -// BATMON_TEMP_LL BATMON event: Temperature level below lower limit -// BATMON_TEMP_UL BATMON event: Temperature level above upper limit -// BATMON_BATT_LL BATMON event: Battery level below lower limit -// BATMON_BATT_UL BATMON event: Battery level above upper limit -// AUX_TIMER2_EV3 Event 3 from AUX TImer2 -// AUX_TIMER2_EV2 Event 2 from AUX TImer2 -// AUX_TIMER2_EV1 Event 1 from AUX TImer2 -// AUX_TIMER2_EV0 Event 0 from AUX TImer2 -// IOEV_AON_PROG2 Edge detect IO event from the DIO(s) which have -// enabled contribution to IOEV_AON_PROG2 in -// [MCU_IOC:IOCFGx.IOEV_AON_PROG2_EN] -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_M 0x003F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_S 16 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_NONE 0x003F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC_N 0x00380000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB_ASYNC 0x00370000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_VOLT 0x00360000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP 0x00350000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER1_EV 0x00340000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER0_EV 0x00330000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TDC_DONE 0x00320000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_ADC_DONE 0x00310000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPB 0x00300000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_COMPA 0x002F0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV2 0x002E0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV1 0x002D0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_SWEV0 0x002C0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_JTAG 0x002B0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_UPD 0x002A0000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_COMB_DLY 0x00290000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2_DLY 0x00280000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1_DLY 0x00270000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0_DLY 0x00260000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH2 0x00250000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH1 0x00240000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_RTC_CH0 0x00230000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_PAD 0x00200000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_COMBINED 0x00090000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP_LL 0x00080000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_TEMP_UL 0x00070000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_BATT_LL 0x00060000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_BATMON_BATT_UL 0x00050000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV3 0x00040000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV2 0x00030000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV1 0x00020000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_AUX_TIMER2_EV0 0x00010000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG2_EV_IOEV_AON_PROG2 0x00000000 - -// Field: [13:8] AON_PROG1_EV -// -// Event selector for AON_PROG1 event. -// -// AON Event Source id# selecting event routed to EVENT as AON_PROG1 event. -// ENUMs: -// NONE -// AUX_COMPB_ASYNC_N -// AUX_COMPB_ASYNC -// BATMON_VOLT -// BATMON_TEMP -// AUX_TIMER1_EV -// AUX_TIMER0_EV -// AUX_TDC_DONE -// AUX_ADC_DONE -// AUX_COMPB -// AUX_COMPA -// AUX_SWEV2 -// AUX_SWEV1 -// AUX_SWEV0 -// JTAG -// RTC_UPD -// RTC_COMB_DLY -// RTC_CH2_DLY -// RTC_CH1_DLY -// RTC_CH0_DLY RTC channel 0 - delayed event -// RTC_CH2 RTC channel 2 event -// RTC_CH1 RTC channel 1 event -// RTC_CH0 RTC channel 0 event -// PAD Edge detect on any PAD -// BATMON_COMBINED Combined event from BATMON -// BATMON_TEMP_LL BATMON event: Temperature level below lower limit -// BATMON_TEMP_UL BATMON event: Temperature level above upper limit -// BATMON_BATT_LL BATMON event: Battery level below lower limit -// BATMON_BATT_UL BATMON event: Battery level above upper limit -// AUX_TIMER2_EV3 Event 3 from AUX TImer2 -// AUX_TIMER2_EV2 Event 2 from AUX TImer2 -// AUX_TIMER2_EV1 Event 1 from AUX TImer2 -// AUX_TIMER2_EV0 Event 0 from AUX TImer2 -// IOEV_AON_PROG1 Edge detect IO event from the DIO(s) which have -// enabled contribution to IOEV_AON_PROG1 in -// [MCU_IOC:IOCFGx.IOEV_AON_PROG1_EN] -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_M 0x00003F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_S 8 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_NONE 0x00003F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC_N 0x00003800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB_ASYNC 0x00003700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_VOLT 0x00003600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP 0x00003500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER1_EV 0x00003400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER0_EV 0x00003300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TDC_DONE 0x00003200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_ADC_DONE 0x00003100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPB 0x00003000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_COMPA 0x00002F00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV2 0x00002E00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV1 0x00002D00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_SWEV0 0x00002C00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_JTAG 0x00002B00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_UPD 0x00002A00 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_COMB_DLY 0x00002900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2_DLY 0x00002800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1_DLY 0x00002700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0_DLY 0x00002600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH2 0x00002500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH1 0x00002400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_RTC_CH0 0x00002300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_PAD 0x00002000 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_COMBINED 0x00000900 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP_LL 0x00000800 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_TEMP_UL 0x00000700 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_BATT_LL 0x00000600 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_BATMON_BATT_UL 0x00000500 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV3 0x00000400 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV2 0x00000300 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV1 0x00000200 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_AUX_TIMER2_EV0 0x00000100 -#define AON_EVENT_EVTOMCUSEL_AON_PROG1_EV_IOEV_AON_PROG1 0x00000000 - -// Field: [5:0] AON_PROG0_EV -// -// Event selector for AON_PROG0 event. -// -// AON Event Source id# selecting event routed to EVENT as AON_PROG0 event. -// ENUMs: -// NONE -// AUX_COMPB_ASYNC_N -// AUX_COMPB_ASYNC -// BATMON_VOLT -// BATMON_TEMP -// AUX_TIMER1_EV -// AUX_TIMER0_EV -// AUX_TDC_DONE -// AUX_ADC_DONE -// AUX_COMPB -// AUX_COMPA -// AUX_SWEV2 -// AUX_SWEV1 -// AUX_SWEV0 -// JTAG -// RTC_UPD -// RTC_COMB_DLY -// RTC_CH2_DLY -// RTC_CH1_DLY -// RTC_CH0_DLY -// RTC_CH2 -// RTC_CH1 -// RTC_CH0 -// PAD -// BATMON_COMBINED -// BATMON_TEMP_LL -// BATMON_TEMP_UL -// BATMON_BATT_LL -// BATMON_BATT_UL -// AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 -// IOEV_AON_PROG0 Edge detect IO event from the DIO(s) which have -// enabled contribution to IOEV_AON_PROG0 in -// [MCU_IOC:IOCFGx.IOEV_AON_PROG0_EN] -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_W 6 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_M 0x0000003F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_S 0 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_NONE 0x0000003F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_JTAG 0x0000002B -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_UPD 0x0000002A -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH2 0x00000025 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH1 0x00000024 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_RTC_CH0 0x00000023 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_PAD 0x00000020 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_COMBINED 0x00000009 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP_LL 0x00000008 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_TEMP_UL 0x00000007 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_BATT_LL 0x00000006 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_BATMON_BATT_UL 0x00000005 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV3 0x00000004 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV2 0x00000003 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV1 0x00000002 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_AUX_TIMER2_EV0 0x00000001 -#define AON_EVENT_EVTOMCUSEL_AON_PROG0_EV_IOEV_AON_PROG0 0x00000000 - -//***************************************************************************** -// -// Register: AON_EVENT_O_RTCSEL -// -//***************************************************************************** -// Field: [5:0] RTC_CH1_CAPT_EV -// -// AON Event Source id# for RTCSEL event which is fed to AON_RTC. Please refer -// to AON_RTC:CH1CAPT -// ENUMs: -// NONE -// AUX_COMPB_ASYNC_N -// AUX_COMPB_ASYNC -// BATMON_VOLT -// BATMON_TEMP -// AUX_TIMER1_EV -// AUX_TIMER0_EV -// AUX_TDC_DONE -// AUX_ADC_DONE -// AUX_COMPB -// AUX_COMPA -// AUX_SWEV2 -// AUX_SWEV1 -// AUX_SWEV0 -// JTAG -// RTC_UPD -// RTC_COMB_DLY -// RTC_CH2_DLY -// RTC_CH1_DLY -// RTC_CH0_DLY -// RTC_CH2 -// RTC_CH1 -// RTC_CH0 -// PAD -// BATMON_COMBINED -// BATMON_TEMP_LL -// BATMON_TEMP_UL -// BATMON_BATT_LL -// BATMON_BATT_UL -// AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 -// IOEV_RTC Edge detect IO event from the DIO(s) which have -// enabled contribution to IOEV_RTC in -// [MCU_IOC:IOCFGx.IOEV_RTC_EN] -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_W 6 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_M 0x0000003F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_S 0 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_NONE 0x0000003F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC_N 0x00000038 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB_ASYNC 0x00000037 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_VOLT 0x00000036 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP 0x00000035 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER1_EV 0x00000034 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER0_EV 0x00000033 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TDC_DONE 0x00000032 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_ADC_DONE 0x00000031 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPB 0x00000030 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_COMPA 0x0000002F -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV2 0x0000002E -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV1 0x0000002D -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_SWEV0 0x0000002C -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_JTAG 0x0000002B -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_UPD 0x0000002A -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_COMB_DLY 0x00000029 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2_DLY 0x00000028 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1_DLY 0x00000027 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0_DLY 0x00000026 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH2 0x00000025 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH1 0x00000024 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_RTC_CH0 0x00000023 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_PAD 0x00000020 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_COMBINED 0x00000009 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP_LL 0x00000008 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_TEMP_UL 0x00000007 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_BATT_LL 0x00000006 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_BATMON_BATT_UL 0x00000005 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV3 0x00000004 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV2 0x00000003 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV1 0x00000002 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_AUX_TIMER2_EV0 0x00000001 -#define AON_EVENT_RTCSEL_RTC_CH1_CAPT_EV_IOEV_RTC 0x00000000 - - -#endif // __AON_EVENT__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h deleted file mode 100644 index d2e6d1f4f94..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_ioc.h +++ /dev/null @@ -1,158 +0,0 @@ -/****************************************************************************** -* Filename: hw_aon_ioc_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AON_IOC_H__ -#define __HW_AON_IOC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AON_IOC component -// -//***************************************************************************** -// Internal -#define AON_IOC_O_IOSTRMIN 0x00000000 - -// Internal -#define AON_IOC_O_IOSTRMED 0x00000004 - -// Internal -#define AON_IOC_O_IOSTRMAX 0x00000008 - -// IO Latch Control -#define AON_IOC_O_IOCLATCH 0x0000000C - -// SCLK_LF External Output Control -#define AON_IOC_O_CLK32KCTL 0x00000010 - -// TCK IO Pin Control -#define AON_IOC_O_TCKCTL 0x00000014 - -//***************************************************************************** -// -// Register: AON_IOC_O_IOSTRMIN -// -//***************************************************************************** -// Field: [2:0] GRAY_CODE -// -// Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMIN_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMIN_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMIN_GRAY_CODE_S 0 - -//***************************************************************************** -// -// Register: AON_IOC_O_IOSTRMED -// -//***************************************************************************** -// Field: [2:0] GRAY_CODE -// -// Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMED_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMED_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMED_GRAY_CODE_S 0 - -//***************************************************************************** -// -// Register: AON_IOC_O_IOSTRMAX -// -//***************************************************************************** -// Field: [2:0] GRAY_CODE -// -// Internal. Only to be used through TI provided API. -#define AON_IOC_IOSTRMAX_GRAY_CODE_W 3 -#define AON_IOC_IOSTRMAX_GRAY_CODE_M 0x00000007 -#define AON_IOC_IOSTRMAX_GRAY_CODE_S 0 - -//***************************************************************************** -// -// Register: AON_IOC_O_IOCLATCH -// -//***************************************************************************** -// Field: [0] EN -// -// Controls latches between MCU IOC and AON_IOC. -// -// The latches are transparent by default. -// -// They must be closed prior to power off the domain(s) controlling the IOs in -// order to preserve IO values on external pins. -// ENUMs: -// TRANSP Latches are transparent, meaning the value of the -// IO is directly controlled by the GPIO or -// peripheral value -// STATIC Latches are static, meaning the current value on -// the IO pin is frozen by latches and kept even -// if GPIO module or a peripheral module is turned -// off -#define AON_IOC_IOCLATCH_EN 0x00000001 -#define AON_IOC_IOCLATCH_EN_BITN 0 -#define AON_IOC_IOCLATCH_EN_M 0x00000001 -#define AON_IOC_IOCLATCH_EN_S 0 -#define AON_IOC_IOCLATCH_EN_TRANSP 0x00000001 -#define AON_IOC_IOCLATCH_EN_STATIC 0x00000000 - -//***************************************************************************** -// -// Register: AON_IOC_O_CLK32KCTL -// -//***************************************************************************** -// Field: [0] OE_N -// -// 0: Output enable active. SCLK_LF output on IO pin that has PORT_ID (for -// example IOC:IOCFG0.PORT_ID) set to AON_CLK32K. -// 1: Output enable not active -#define AON_IOC_CLK32KCTL_OE_N 0x00000001 -#define AON_IOC_CLK32KCTL_OE_N_BITN 0 -#define AON_IOC_CLK32KCTL_OE_N_M 0x00000001 -#define AON_IOC_CLK32KCTL_OE_N_S 0 - -//***************************************************************************** -// -// Register: AON_IOC_O_TCKCTL -// -//***************************************************************************** -// Field: [0] EN -// -// 0: Input driver for TCK disabled. -// 1: Input driver for TCK enabled. -#define AON_IOC_TCKCTL_EN 0x00000001 -#define AON_IOC_TCKCTL_EN_BITN 0 -#define AON_IOC_TCKCTL_EN_M 0x00000001 -#define AON_IOC_TCKCTL_EN_S 0 - - -#endif // __AON_IOC__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h deleted file mode 100644 index e971217777e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_pmctl.h +++ /dev/null @@ -1,625 +0,0 @@ -/****************************************************************************** -* Filename: hw_aon_pmctl_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AON_PMCTL_H__ -#define __HW_AON_PMCTL_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AON_PMCTL component -// -//***************************************************************************** -// AUX SCE Clock Management -#define AON_PMCTL_O_AUXSCECLK 0x00000004 - -// RAM Configuration -#define AON_PMCTL_O_RAMCFG 0x00000008 - -// Power Management Control -#define AON_PMCTL_O_PWRCTL 0x00000010 - -// AON Power and Reset Status -#define AON_PMCTL_O_PWRSTAT 0x00000014 - -// Shutdown Control -#define AON_PMCTL_O_SHUTDOWN 0x00000018 - -// Recharge Controller Configuration -#define AON_PMCTL_O_RECHARGECFG 0x0000001C - -// Recharge Controller Status -#define AON_PMCTL_O_RECHARGESTAT 0x00000020 - -// Oscillator Configuration -#define AON_PMCTL_O_OSCCFG 0x00000024 - -// Reset Management -#define AON_PMCTL_O_RESETCTL 0x00000028 - -// Sleep Control -#define AON_PMCTL_O_SLEEPCTL 0x0000002C - -// JTAG Configuration -#define AON_PMCTL_O_JTAGCFG 0x00000034 - -// JTAG USERCODE -#define AON_PMCTL_O_JTAGUSERCODE 0x0000003C - -//***************************************************************************** -// -// Register: AON_PMCTL_O_AUXSCECLK -// -//***************************************************************************** -// Field: [8] PD_SRC -// -// Selects the clock source for the AUX domain when AUX is in powerdown mode. -// Note: Switching the clock source is guaranteed to be glitch-free -// ENUMs: -// SCLK_LF LF clock (SCLK_LF ) -// NO_CLOCK No clock -#define AON_PMCTL_AUXSCECLK_PD_SRC 0x00000100 -#define AON_PMCTL_AUXSCECLK_PD_SRC_BITN 8 -#define AON_PMCTL_AUXSCECLK_PD_SRC_M 0x00000100 -#define AON_PMCTL_AUXSCECLK_PD_SRC_S 8 -#define AON_PMCTL_AUXSCECLK_PD_SRC_SCLK_LF 0x00000100 -#define AON_PMCTL_AUXSCECLK_PD_SRC_NO_CLOCK 0x00000000 - -// Field: [0] SRC -// -// Selects the clock source for the AUX domain when AUX is in active mode. -// Note: Switching the clock source is guaranteed to be glitch-free -// ENUMs: -// SCLK_MF MF Clock (SCLK_MF) -// SCLK_HFDIV2 HF Clock divided by 2 (SCLK_HFDIV2) -#define AON_PMCTL_AUXSCECLK_SRC 0x00000001 -#define AON_PMCTL_AUXSCECLK_SRC_BITN 0 -#define AON_PMCTL_AUXSCECLK_SRC_M 0x00000001 -#define AON_PMCTL_AUXSCECLK_SRC_S 0 -#define AON_PMCTL_AUXSCECLK_SRC_SCLK_MF 0x00000001 -#define AON_PMCTL_AUXSCECLK_SRC_SCLK_HFDIV2 0x00000000 - -//***************************************************************************** -// -// Register: AON_PMCTL_O_RAMCFG -// -//***************************************************************************** -// Field: [17] AUX_SRAM_PWR_OFF -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF 0x00020000 -#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_BITN 17 -#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_M 0x00020000 -#define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_S 17 - -// Field: [16] AUX_SRAM_RET_EN -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN 0x00010000 -#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_BITN 16 -#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_M 0x00010000 -#define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_S 16 - -// Field: [3:0] BUS_SRAM_RET_EN -// -// MCU SRAM is partitioned into 5 banks . This register controls which of the -// banks that has retention during MCU Bus domain power off -// ENUMs: -// RET_FULL Retention on for all banks SRAM:BANK0, SRAM:BANK1 -// ,SRAM:BANK2, SRAM:BANK3 and SRAM:BANK4 -// RET_LEVEL3 Retention on for SRAM:BANK0, SRAM:BANK1 -// ,SRAM:BANK2 and SRAM:BANK3 -// RET_LEVEL2 Retention on for SRAM:BANK0, SRAM:BANK1 and -// SRAM:BANK2 -// RET_LEVEL1 Retention on for SRAM:BANK0 and SRAM:BANK1 -// RET_NONE Retention is disabled -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_W 4 -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M 0x0000000F -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_S 0 -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL 0x0000000F -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 0x00000007 -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 0x00000003 -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL1 0x00000001 -#define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AON_PMCTL_O_PWRCTL -// -//***************************************************************************** -// Field: [2] DCDC_ACTIVE -// -// Select to use DCDC regulator for VDDR in active mode -// -// 0: Use GLDO for regulation of VDDR in active mode. -// 1: Use DCDC for regulation of VDDR in active mode. -// -// DCDC_EN must also be set for DCDC to be used as regulator for VDDR in active -// mode -#define AON_PMCTL_PWRCTL_DCDC_ACTIVE 0x00000004 -#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN 2 -#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 -#define AON_PMCTL_PWRCTL_DCDC_ACTIVE_S 2 - -// Field: [1] EXT_REG_MODE -// -// Status of source for VDDRsupply: -// -// 0: DCDC or GLDO are generating VDDR -// 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR -#define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002 -#define AON_PMCTL_PWRCTL_EXT_REG_MODE_BITN 1 -#define AON_PMCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 -#define AON_PMCTL_PWRCTL_EXT_REG_MODE_S 1 - -// Field: [0] DCDC_EN -// -// Select to use DCDC regulator during recharge of VDDR -// -// 0: Use GLDO for recharge of VDDR -// 1: Use DCDC for recharge of VDDR -// -// Note: This bitfield should be set to the same as DCDC_ACTIVE -#define AON_PMCTL_PWRCTL_DCDC_EN 0x00000001 -#define AON_PMCTL_PWRCTL_DCDC_EN_BITN 0 -#define AON_PMCTL_PWRCTL_DCDC_EN_M 0x00000001 -#define AON_PMCTL_PWRCTL_DCDC_EN_S 0 - -//***************************************************************************** -// -// Register: AON_PMCTL_O_PWRSTAT -// -//***************************************************************************** -// Field: [2] JTAG_PD_ON -// -// Indicates JTAG power state: -// -// 0: JTAG is powered off -// 1: JTAG is powered on -#define AON_PMCTL_PWRSTAT_JTAG_PD_ON 0x00000004 -#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_BITN 2 -#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_M 0x00000004 -#define AON_PMCTL_PWRSTAT_JTAG_PD_ON_S 2 - -// Field: [1] AUX_BUS_RESET_DONE -// -// Indicates Reset Done from AUX Bus: -// -// 0: AUX Bus is being reset -// 1: AUX Bus reset is released -#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE 0x00000002 -#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_BITN 1 -#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_M 0x00000002 -#define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_S 1 - -// Field: [0] AUX_RESET_DONE -// -// Indicates Reset Done from AUX: -// -// 0: AUX is being reset -// 1: AUX reset is released -#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE 0x00000001 -#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_BITN 0 -#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_M 0x00000001 -#define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_S 0 - -//***************************************************************************** -// -// Register: AON_PMCTL_O_SHUTDOWN -// -//***************************************************************************** -// Field: [0] EN -// -// Shutdown control. -// -// 0: Do not write 0 to this bit. -// 1: Immediately start the process to enter shutdown mode -#define AON_PMCTL_SHUTDOWN_EN 0x00000001 -#define AON_PMCTL_SHUTDOWN_EN_BITN 0 -#define AON_PMCTL_SHUTDOWN_EN_M 0x00000001 -#define AON_PMCTL_SHUTDOWN_EN_S 0 - -//***************************************************************************** -// -// Register: AON_PMCTL_O_RECHARGECFG -// -//***************************************************************************** -// Field: [31:30] MODE -// -// Selects recharge algorithm for VDDR when the system is running on the uLDO -// ENUMs: -// COMPARATOR External recharge comparator. -// Note that the clock to -// the recharge comparator must be enabled, -// -// [ANATOP_MMAP:ADI_3_REFSYS:CTL_RECHARGE_CMP0:COMP_CLK_DISABLE], -// before selecting this recharge algorithm. -// ADAPTIVE Adaptive timer -// STATIC Static timer -// OFF Recharge disabled -#define AON_PMCTL_RECHARGECFG_MODE_W 2 -#define AON_PMCTL_RECHARGECFG_MODE_M 0xC0000000 -#define AON_PMCTL_RECHARGECFG_MODE_S 30 -#define AON_PMCTL_RECHARGECFG_MODE_COMPARATOR 0xC0000000 -#define AON_PMCTL_RECHARGECFG_MODE_ADAPTIVE 0x80000000 -#define AON_PMCTL_RECHARGECFG_MODE_STATIC 0x40000000 -#define AON_PMCTL_RECHARGECFG_MODE_OFF 0x00000000 - -// Field: [23:20] C2 -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RECHARGECFG_C2_W 4 -#define AON_PMCTL_RECHARGECFG_C2_M 0x00F00000 -#define AON_PMCTL_RECHARGECFG_C2_S 20 - -// Field: [19:16] C1 -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RECHARGECFG_C1_W 4 -#define AON_PMCTL_RECHARGECFG_C1_M 0x000F0000 -#define AON_PMCTL_RECHARGECFG_C1_S 16 - -// Field: [15:11] MAX_PER_M -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RECHARGECFG_MAX_PER_M_W 5 -#define AON_PMCTL_RECHARGECFG_MAX_PER_M_M 0x0000F800 -#define AON_PMCTL_RECHARGECFG_MAX_PER_M_S 11 - -// Field: [10:8] MAX_PER_E -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RECHARGECFG_MAX_PER_E_W 3 -#define AON_PMCTL_RECHARGECFG_MAX_PER_E_M 0x00000700 -#define AON_PMCTL_RECHARGECFG_MAX_PER_E_S 8 - -// Field: [7:3] PER_M -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RECHARGECFG_PER_M_W 5 -#define AON_PMCTL_RECHARGECFG_PER_M_M 0x000000F8 -#define AON_PMCTL_RECHARGECFG_PER_M_S 3 - -// Field: [2:0] PER_E -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RECHARGECFG_PER_E_W 3 -#define AON_PMCTL_RECHARGECFG_PER_E_M 0x00000007 -#define AON_PMCTL_RECHARGECFG_PER_E_S 0 - -//***************************************************************************** -// -// Register: AON_PMCTL_O_RECHARGESTAT -// -//***************************************************************************** -// Field: [19:16] VDDR_SMPLS -// -// The last 4 VDDR samples. -// -// For each bit: -// 0: VDDR was below VDDR_OK threshold when recharge started -// 1: VDDR was above VDDR_OK threshold when recharge started -// -// The register is updated prior to every recharge period with a shift left, -// and bit 0 is updated with the last VDDR sample. -#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_W 4 -#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 -#define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_S 16 - -// Field: [15:0] MAX_USED_PER -// -// Shows the maximum number of 32kHz periods that have separated two recharge -// cycles and VDDR still was above VDDR_OK threshold when the latter recharge -// started. This register can be used as an indication of the leakage current -// during standby. -// -// This bitfield is cleared to 0 when writing this register. -#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_W 16 -#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF -#define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_S 0 - -//***************************************************************************** -// -// Register: AON_PMCTL_O_OSCCFG -// -//***************************************************************************** -// Field: [7:3] PER_M -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_OSCCFG_PER_M_W 5 -#define AON_PMCTL_OSCCFG_PER_M_M 0x000000F8 -#define AON_PMCTL_OSCCFG_PER_M_S 3 - -// Field: [2:0] PER_E -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_OSCCFG_PER_E_W 3 -#define AON_PMCTL_OSCCFG_PER_E_M 0x00000007 -#define AON_PMCTL_OSCCFG_PER_E_S 0 - -//***************************************************************************** -// -// Register: AON_PMCTL_O_RESETCTL -// -//***************************************************************************** -// Field: [31] SYSRESET -// -// Cold reset register. Writing 1 to this bitfield will reset the entire chip -// and cause boot code to run again. -// -// 0: No effect -// 1: Generate system reset. Appears as SYSRESET in RESET_SRC -#define AON_PMCTL_RESETCTL_SYSRESET 0x80000000 -#define AON_PMCTL_RESETCTL_SYSRESET_BITN 31 -#define AON_PMCTL_RESETCTL_SYSRESET_M 0x80000000 -#define AON_PMCTL_RESETCTL_SYSRESET_S 31 - -// Field: [25] BOOT_DET_1_CLR -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_S 25 - -// Field: [24] BOOT_DET_0_CLR -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_S 24 - -// Field: [17] BOOT_DET_1_SET -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_S 17 - -// Field: [16] BOOT_DET_0_SET -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_S 16 - -// Field: [15] WU_FROM_SD -// -// A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from -// SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin -// being forced low) -// -// Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup -// sources. -// -// 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC -// 1: A wakeup has occurred from SHUTDOWN -// -// Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. -#define AON_PMCTL_RESETCTL_WU_FROM_SD 0x00008000 -#define AON_PMCTL_RESETCTL_WU_FROM_SD_BITN 15 -#define AON_PMCTL_RESETCTL_WU_FROM_SD_M 0x00008000 -#define AON_PMCTL_RESETCTL_WU_FROM_SD_S 15 - -// Field: [14] GPIO_WU_FROM_SD -// -// A wakeup from SHUTDOWN on an IO event has occurred -// -// Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup -// sources. -// -// 0: The wakeup did not occur from SHUTDOWN on an IO event -// 1: A wakeup from SHUTDOWN occurred from an IO event -// -// The case where WU_FROM_SD is asserted but this bitfield is not asserted will -// only occur in a debug session. The boot code will not proceed with wakeup -// from SHUTDOWN procedure until this bitfield is asserted as well. -// -// Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. -#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 -#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 -#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 -#define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 - -// Field: [13] BOOT_DET_1 -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_BOOT_DET_1 0x00002000 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_BITN 13 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_M 0x00002000 -#define AON_PMCTL_RESETCTL_BOOT_DET_1_S 13 - -// Field: [12] BOOT_DET_0 -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_BOOT_DET_0 0x00001000 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_BITN 12 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_M 0x00001000 -#define AON_PMCTL_RESETCTL_BOOT_DET_0_S 12 - -// Field: [8] VDDS_LOSS_EN -// -// Controls reset generation in case VDDS is lost -// -// 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 -// 1: Brown out detect of VDDS generates system reset -#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN 0x00000100 -#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_BITN 8 -#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000100 -#define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_S 8 - -// Field: [7] VDDR_LOSS_EN -// -// Controls reset generation in case VDDR is lost -// -// 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 -// 1: Brown out detect of VDDR generates system reset -#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN 0x00000080 -#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_BITN 7 -#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000080 -#define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_S 7 - -// Field: [6] VDD_LOSS_EN -// -// Controls reset generation in case VDD is lost -// -// 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 -// 1: Brown out detect of VDD generates system reset -#define AON_PMCTL_RESETCTL_VDD_LOSS_EN 0x00000040 -#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_BITN 6 -#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_M 0x00000040 -#define AON_PMCTL_RESETCTL_VDD_LOSS_EN_S 6 - -// Field: [5] CLK_LOSS_EN -// -// Controls reset generation in case SCLK_LF, SCLK_MF or SCLK_HF is lost when -// clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] -// -// 0: Clock loss is ignored -// 1: Clock loss generates system reset -// -// Note: Clock loss reset generation must be disabled when changing clock -// source for SCLK_LF. Failure to do so may result in a spurious system -// reset. Clock loss reset generation is controlled by -// [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] -#define AON_PMCTL_RESETCTL_CLK_LOSS_EN 0x00000020 -#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN 5 -#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_M 0x00000020 -#define AON_PMCTL_RESETCTL_CLK_LOSS_EN_S 5 - -// Field: [4] MCU_WARM_RESET -// -// Internal. Only to be used through TI provided API. -#define AON_PMCTL_RESETCTL_MCU_WARM_RESET 0x00000010 -#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_BITN 4 -#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_M 0x00000010 -#define AON_PMCTL_RESETCTL_MCU_WARM_RESET_S 4 - -// Field: [3:1] RESET_SRC -// -// Shows the root cause of the last system reset. More than the reported reset -// source can have been active during the last system reset but only the root -// cause is reported. -// -// The capture feature is not rearmed until all off the possible reset sources -// have been released and the result has been copied to AON_PMCTL. During the -// copy and rearm process it is one 2MHz period in which and eventual new -// system reset will be reported as Power on reset regardless of the root -// cause. -// ENUMs: -// WARMRESET Software reset via PRCM warm reset request -// SYSRESET Software reset via SYSRESET or hardware power -// management timeout detection. -// -// Note: The hardware power -// management timeout circuit is always enabled. -// CLK_LOSS SCLK_LF, SCLK_MF or SCLK_HF clock loss detect -// VDDR_LOSS Brown out detect on VDDR -// VDDS_LOSS Brown out detect on VDDS -// PIN_RESET Reset pin -// PWR_ON Power on reset -#define AON_PMCTL_RESETCTL_RESET_SRC_W 3 -#define AON_PMCTL_RESETCTL_RESET_SRC_M 0x0000000E -#define AON_PMCTL_RESETCTL_RESET_SRC_S 1 -#define AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E -#define AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C -#define AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A -#define AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 -#define AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 -#define AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 -#define AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 - -//***************************************************************************** -// -// Register: AON_PMCTL_O_SLEEPCTL -// -//***************************************************************************** -// Field: [0] IO_PAD_SLEEP_DIS -// -// Controls the I/O pad sleep mode. The boot code will set this bitfield -// automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is -// set). -// -// 0: I/O pad sleep mode is enabled, meaning all outputs and pad configurations -// are latched. Inputs are transparent if pad is configured as input before -// IO_PAD_SLEEP_DIS is set to 1 -// 1: I/O pad sleep mode is disabled -// -// Application software must reconfigure the state for all IO's before setting -// this bitfield upon waking up from a SHUTDOWN to avoid glitches on pins. -#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 -#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 -#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 -#define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 - -//***************************************************************************** -// -// Register: AON_PMCTL_O_JTAGCFG -// -//***************************************************************************** -// Field: [8] JTAG_PD_FORCE_ON -// -// Controls JTAG Power domain power state: -// -// 0: Controlled exclusively by debug subsystem. (JTAG Power domain will be -// powered off unless a debugger is attached) -// 1: JTAG Power Domain is forced on, independent of debug subsystem. -// -// Note: The reset value causes JTAG Power domain to be powered on by default. -// Software must clear this bit to turn off the JTAG Power domain -#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 -#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 -#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 -#define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_S 8 - -//***************************************************************************** -// -// Register: AON_PMCTL_O_JTAGUSERCODE -// -//***************************************************************************** -// Field: [31:0] USER_CODE -// -// 32-bit JTAG USERCODE register feeding main JTAG TAP -// Note: This field can be locked by LOCKCFG.LOCK -#define AON_PMCTL_JTAGUSERCODE_USER_CODE_W 32 -#define AON_PMCTL_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF -#define AON_PMCTL_JTAGUSERCODE_USER_CODE_S 0 - - -#endif // __AON_PMCTL__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h deleted file mode 100644 index 1718015db05..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aon_rtc.h +++ /dev/null @@ -1,546 +0,0 @@ -/****************************************************************************** -* Filename: hw_aon_rtc_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AON_RTC_H__ -#define __HW_AON_RTC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AON_RTC component -// -//***************************************************************************** -// Control -#define AON_RTC_O_CTL 0x00000000 - -// Event Flags, RTC Status -#define AON_RTC_O_EVFLAGS 0x00000004 - -// Second Counter Value, Integer Part -#define AON_RTC_O_SEC 0x00000008 - -// Second Counter Value, Fractional Part -#define AON_RTC_O_SUBSEC 0x0000000C - -// Subseconds Increment -#define AON_RTC_O_SUBSECINC 0x00000010 - -// Channel Configuration -#define AON_RTC_O_CHCTL 0x00000014 - -// Channel 0 Compare Value -#define AON_RTC_O_CH0CMP 0x00000018 - -// Channel 1 Compare Value -#define AON_RTC_O_CH1CMP 0x0000001C - -// Channel 2 Compare Value -#define AON_RTC_O_CH2CMP 0x00000020 - -// Channel 2 Compare Value Auto-increment -#define AON_RTC_O_CH2CMPINC 0x00000024 - -// Channel 1 Capture Value -#define AON_RTC_O_CH1CAPT 0x00000028 - -// AON Synchronization -#define AON_RTC_O_SYNC 0x0000002C - -// Current Counter Value -#define AON_RTC_O_TIME 0x00000030 - -// Synchronization to SCLK_LF -#define AON_RTC_O_SYNCLF 0x00000034 - -//***************************************************************************** -// -// Register: AON_RTC_O_CTL -// -//***************************************************************************** -// Field: [18:16] COMB_EV_MASK -// -// Eventmask selecting which delayed events that form the combined event. -// ENUMs: -// CH2 Use Channel 2 delayed event in combined event -// CH1 Use Channel 1 delayed event in combined event -// CH0 Use Channel 0 delayed event in combined event -// NONE No event is selected for combined event. -#define AON_RTC_CTL_COMB_EV_MASK_W 3 -#define AON_RTC_CTL_COMB_EV_MASK_M 0x00070000 -#define AON_RTC_CTL_COMB_EV_MASK_S 16 -#define AON_RTC_CTL_COMB_EV_MASK_CH2 0x00040000 -#define AON_RTC_CTL_COMB_EV_MASK_CH1 0x00020000 -#define AON_RTC_CTL_COMB_EV_MASK_CH0 0x00010000 -#define AON_RTC_CTL_COMB_EV_MASK_NONE 0x00000000 - -// Field: [11:8] EV_DELAY -// -// Number of SCLK_LF clock cycles waited before generating delayed events. -// (Common setting for all RTC cannels) the delayed event is delayed -// ENUMs: -// D144 Delay by 144 clock cycles -// D128 Delay by 128 clock cycles -// D112 Delay by 112 clock cycles -// D96 Delay by 96 clock cycles -// D80 Delay by 80 clock cycles -// D64 Delay by 64 clock cycles -// D48 Delay by 48 clock cycles -// D32 Delay by 32 clock cycles -// D16 Delay by 16 clock cycles -// D8 Delay by 8 clock cycles -// D4 Delay by 4 clock cycles -// D2 Delay by 2 clock cycles -// D1 Delay by 1 clock cycles -// D0 No delay on delayed event -#define AON_RTC_CTL_EV_DELAY_W 4 -#define AON_RTC_CTL_EV_DELAY_M 0x00000F00 -#define AON_RTC_CTL_EV_DELAY_S 8 -#define AON_RTC_CTL_EV_DELAY_D144 0x00000D00 -#define AON_RTC_CTL_EV_DELAY_D128 0x00000C00 -#define AON_RTC_CTL_EV_DELAY_D112 0x00000B00 -#define AON_RTC_CTL_EV_DELAY_D96 0x00000A00 -#define AON_RTC_CTL_EV_DELAY_D80 0x00000900 -#define AON_RTC_CTL_EV_DELAY_D64 0x00000800 -#define AON_RTC_CTL_EV_DELAY_D48 0x00000700 -#define AON_RTC_CTL_EV_DELAY_D32 0x00000600 -#define AON_RTC_CTL_EV_DELAY_D16 0x00000500 -#define AON_RTC_CTL_EV_DELAY_D8 0x00000400 -#define AON_RTC_CTL_EV_DELAY_D4 0x00000300 -#define AON_RTC_CTL_EV_DELAY_D2 0x00000200 -#define AON_RTC_CTL_EV_DELAY_D1 0x00000100 -#define AON_RTC_CTL_EV_DELAY_D0 0x00000000 - -// Field: [7] RESET -// -// RTC Counter reset. -// -// Writing 1 to this bit will reset the RTC counter. -// -// This bit is cleared when reset takes effect -#define AON_RTC_CTL_RESET 0x00000080 -#define AON_RTC_CTL_RESET_BITN 7 -#define AON_RTC_CTL_RESET_M 0x00000080 -#define AON_RTC_CTL_RESET_S 7 - -// Field: [2] RTC_4KHZ_EN -// -// RTC_4KHZ is a 4 KHz reference output, tapped from SUBSEC.VALUE bit 19 -// which is used by AUX timer. -// -// 0: RTC_4KHZ signal is forced to 0 -// 1: RTC_4KHZ is enabled ( provied that RTC is enabled EN) -#define AON_RTC_CTL_RTC_4KHZ_EN 0x00000004 -#define AON_RTC_CTL_RTC_4KHZ_EN_BITN 2 -#define AON_RTC_CTL_RTC_4KHZ_EN_M 0x00000004 -#define AON_RTC_CTL_RTC_4KHZ_EN_S 2 - -// Field: [1] RTC_UPD_EN -// -// RTC_UPD is a 16 KHz signal used to sync up the radio timer. The 16 Khz is -// SCLK_LF divided by 2 -// -// 0: RTC_UPD signal is forced to 0 -// 1: RTC_UPD signal is toggling @16 kHz -#define AON_RTC_CTL_RTC_UPD_EN 0x00000002 -#define AON_RTC_CTL_RTC_UPD_EN_BITN 1 -#define AON_RTC_CTL_RTC_UPD_EN_M 0x00000002 -#define AON_RTC_CTL_RTC_UPD_EN_S 1 - -// Field: [0] EN -// -// Enable RTC counter -// -// 0: Halted (frozen) -// 1: Running -#define AON_RTC_CTL_EN 0x00000001 -#define AON_RTC_CTL_EN_BITN 0 -#define AON_RTC_CTL_EN_M 0x00000001 -#define AON_RTC_CTL_EN_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_EVFLAGS -// -//***************************************************************************** -// Field: [16] CH2 -// -// Channel 2 event flag, set when CHCTL.CH2_EN = 1 and the RTC value matches or -// passes the CH2CMP value. -// -// An event will be scheduled to occur as soon as possible when writing to -// CH2CMP provided that the channel is enabled and the new value matches any -// time between next RTC value and 1 second in the past -// -// Writing 1 clears this flag. -// -// AUX_SCE can read the flag through AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and clear it -// using AUX_SYSIF:RTCEVCLR.RTC_CH2_EV_CLR. -#define AON_RTC_EVFLAGS_CH2 0x00010000 -#define AON_RTC_EVFLAGS_CH2_BITN 16 -#define AON_RTC_EVFLAGS_CH2_M 0x00010000 -#define AON_RTC_EVFLAGS_CH2_S 16 - -// Field: [8] CH1 -// -// Channel 1 event flag, set when CHCTL.CH1_EN = 1 and one of the following: -// - CHCTL.CH1_CAPT_EN = 0 and the RTC value matches or passes the CH1CMP -// value. -// - CHCTL.CH1_CAPT_EN = 1 and capture occurs. -// -// An event will be scheduled to occur as soon as possible when writing to -// CH1CMP provided that the channel is enabled, in compare mode and the new -// value matches any time between next RTC value and 1 second in the past. -// -// Writing 1 clears this flag. -#define AON_RTC_EVFLAGS_CH1 0x00000100 -#define AON_RTC_EVFLAGS_CH1_BITN 8 -#define AON_RTC_EVFLAGS_CH1_M 0x00000100 -#define AON_RTC_EVFLAGS_CH1_S 8 - -// Field: [0] CH0 -// -// Channel 0 event flag, set when CHCTL.CH0_EN = 1 and the RTC value matches or -// passes the CH0CMP value. -// -// An event will be scheduled to occur as soon as possible when writing to -// CH0CMP provided that the channels is enabled and the new value matches any -// time between next RTC value and 1 second in the past. -// -// Writing 1 clears this flag. -#define AON_RTC_EVFLAGS_CH0 0x00000001 -#define AON_RTC_EVFLAGS_CH0_BITN 0 -#define AON_RTC_EVFLAGS_CH0_M 0x00000001 -#define AON_RTC_EVFLAGS_CH0_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_SEC -// -//***************************************************************************** -// Field: [31:0] VALUE -// -// Unsigned integer representing Real Time Clock in seconds. -// -// When reading this register the content of SUBSEC.VALUE is simultaneously -// latched. A consistent reading of the combined Real Time Clock can be -// obtained by first reading this register, then reading SUBSEC register. -#define AON_RTC_SEC_VALUE_W 32 -#define AON_RTC_SEC_VALUE_M 0xFFFFFFFF -#define AON_RTC_SEC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_SUBSEC -// -//***************************************************************************** -// Field: [31:0] VALUE -// -// Unsigned integer representing Real Time Clock in fractions of a second -// (VALUE/2^32 seconds) at the time when SEC register was read. -// -// Examples : -// - 0x0000_0000 = 0.0 sec -// - 0x4000_0000 = 0.25 sec -// - 0x8000_0000 = 0.5 sec -// - 0xC000_0000 = 0.75 sec -#define AON_RTC_SUBSEC_VALUE_W 32 -#define AON_RTC_SUBSEC_VALUE_M 0xFFFFFFFF -#define AON_RTC_SUBSEC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_SUBSECINC -// -//***************************************************************************** -// Field: [23:0] VALUEINC -// -// This value compensates for a SCLK_LF clock which has an offset from 32768 -// Hz. -// -// The compensation value can be found as 2^38 / freq, where freq is SCLK_LF -// clock frequency in Hertz -// -// This value is added to SUBSEC.VALUE on every cycle, and carry of this is -// added to SEC.VALUE. To perform the addition, bits [23:6] are aligned with -// SUBSEC.VALUE bits [17:0]. The remaining bits [5:0] are accumulated in a -// hidden 6-bit register that generates a carry into the above mentioned -// addition on overflow. -// The default value corresponds to incrementing by precisely 1/32768 of a -// second. -// -// NOTE: This register is read only. Modification of the register value must be -// done using registers AUX_SYSIF:RTCSUBSECINC0 , AUX_SYSIF:RTCSUBSECINC1 and -// AUX_SYSIF:RTCSUBSECINCCTL -#define AON_RTC_SUBSECINC_VALUEINC_W 24 -#define AON_RTC_SUBSECINC_VALUEINC_M 0x00FFFFFF -#define AON_RTC_SUBSECINC_VALUEINC_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_CHCTL -// -//***************************************************************************** -// Field: [18] CH2_CONT_EN -// -// Set to enable continuous operation of Channel 2 -#define AON_RTC_CHCTL_CH2_CONT_EN 0x00040000 -#define AON_RTC_CHCTL_CH2_CONT_EN_BITN 18 -#define AON_RTC_CHCTL_CH2_CONT_EN_M 0x00040000 -#define AON_RTC_CHCTL_CH2_CONT_EN_S 18 - -// Field: [16] CH2_EN -// -// RTC Channel 2 Enable -// -// 0: Disable RTC Channel 2 -// 1: Enable RTC Channel 2 -#define AON_RTC_CHCTL_CH2_EN 0x00010000 -#define AON_RTC_CHCTL_CH2_EN_BITN 16 -#define AON_RTC_CHCTL_CH2_EN_M 0x00010000 -#define AON_RTC_CHCTL_CH2_EN_S 16 - -// Field: [9] CH1_CAPT_EN -// -// Set Channel 1 mode -// -// 0: Compare mode (default) -// 1: Capture mode -#define AON_RTC_CHCTL_CH1_CAPT_EN 0x00000200 -#define AON_RTC_CHCTL_CH1_CAPT_EN_BITN 9 -#define AON_RTC_CHCTL_CH1_CAPT_EN_M 0x00000200 -#define AON_RTC_CHCTL_CH1_CAPT_EN_S 9 - -// Field: [8] CH1_EN -// -// RTC Channel 1 Enable -// -// 0: Disable RTC Channel 1 -// 1: Enable RTC Channel 1 -#define AON_RTC_CHCTL_CH1_EN 0x00000100 -#define AON_RTC_CHCTL_CH1_EN_BITN 8 -#define AON_RTC_CHCTL_CH1_EN_M 0x00000100 -#define AON_RTC_CHCTL_CH1_EN_S 8 - -// Field: [0] CH0_EN -// -// RTC Channel 0 Enable -// -// 0: Disable RTC Channel 0 -// 1: Enable RTC Channel 0 -#define AON_RTC_CHCTL_CH0_EN 0x00000001 -#define AON_RTC_CHCTL_CH0_EN_BITN 0 -#define AON_RTC_CHCTL_CH0_EN_M 0x00000001 -#define AON_RTC_CHCTL_CH0_EN_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_CH0CMP -// -//***************************************************************************** -// Field: [31:0] VALUE -// -// RTC Channel 0 compare value. -// -// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of -// the compare value. -// -// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE -// (31:16) values of the Real Time Clock register. A Cannel 0 event is -// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or -// exciting the compare value. -// -// Writing to this register can trigger an immediate*) event in case the new -// compare value matches a Real Time Clock value from 1 second in the past up -// till current Real Time Clock value. -// -// Example: -// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 -// -// *) It can take up to one SCLK_LF clock cycles before event occurs due to -// synchronization. -#define AON_RTC_CH0CMP_VALUE_W 32 -#define AON_RTC_CH0CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH0CMP_VALUE_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_CH1CMP -// -//***************************************************************************** -// Field: [31:0] VALUE -// -// RTC Channel 1 compare value. -// -// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of -// the compare value. -// -// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE -// (31:16) values of the Real Time Clock register. A Cannel 0 event is -// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or -// exciting the compare value. -// -// Writing to this register can trigger an immediate*) event in case the new -// compare value matches a Real Time Clock value from 1 second in the past up -// till current Real Time Clock value. -// -// Example: -// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 -// -// *) It can take up to one SCLK_LF clock cycles before event occurs due to -// synchronization. -#define AON_RTC_CH1CMP_VALUE_W 32 -#define AON_RTC_CH1CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH1CMP_VALUE_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_CH2CMP -// -//***************************************************************************** -// Field: [31:0] VALUE -// -// RTC Channel 2 compare value. -// -// Bit 31 to 16 represents seconds and bits 15 to 0 represents subseconds of -// the compare value. -// -// The compare value is compared against SEC.VALUE (15:0) and SUBSEC.VALUE -// (31:16) values of the Real Time Clock register. A Cannel 0 event is -// generated when {SEC.VALUE(15:0),SUBSEC.VALUE (31:16)} is reaching or -// exciting the compare value. -// -// Writing to this register can trigger an immediate*) event in case the new -// compare value matches a Real Time Clock value from 1 second in the past up -// till current Real Time Clock value. -// -// Example: -// To generate a compare 5.5 seconds RTC start,- set this value = 0x0005_8000 -// -// *) It can take up to one SCLK_LF clock cycles before event occurs due to -// synchronization. -#define AON_RTC_CH2CMP_VALUE_W 32 -#define AON_RTC_CH2CMP_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH2CMP_VALUE_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_CH2CMPINC -// -//***************************************************************************** -// Field: [31:0] VALUE -// -// If CHCTL.CH2_CONT_EN is set, this value is added to CH2CMP.VALUE on every -// channel 2 compare event. -#define AON_RTC_CH2CMPINC_VALUE_W 32 -#define AON_RTC_CH2CMPINC_VALUE_M 0xFFFFFFFF -#define AON_RTC_CH2CMPINC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_CH1CAPT -// -//***************************************************************************** -// Field: [31:16] SEC -// -// Value of SEC.VALUE bits 15:0 at capture time. -#define AON_RTC_CH1CAPT_SEC_W 16 -#define AON_RTC_CH1CAPT_SEC_M 0xFFFF0000 -#define AON_RTC_CH1CAPT_SEC_S 16 - -// Field: [15:0] SUBSEC -// -// Value of SUBSEC.VALUE bits 31:16 at capture time. -#define AON_RTC_CH1CAPT_SUBSEC_W 16 -#define AON_RTC_CH1CAPT_SUBSEC_M 0x0000FFFF -#define AON_RTC_CH1CAPT_SUBSEC_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_SYNC -// -//***************************************************************************** -// Field: [0] WBUSY -// -// This register will always return 0,- however it will not return the value -// until there are no outstanding write requests between MCU and AON -// -// Note: Writing to this register prior to reading will force a wait until next -// SCLK_MF edge. This is recommended for syncing read registers from AON when -// waking up from sleep -// Failure to do so may result in reading AON values from prior to going to -// sleep -#define AON_RTC_SYNC_WBUSY 0x00000001 -#define AON_RTC_SYNC_WBUSY_BITN 0 -#define AON_RTC_SYNC_WBUSY_M 0x00000001 -#define AON_RTC_SYNC_WBUSY_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_TIME -// -//***************************************************************************** -// Field: [31:16] SEC_L -// -// Returns the lower halfword of SEC register. -#define AON_RTC_TIME_SEC_L_W 16 -#define AON_RTC_TIME_SEC_L_M 0xFFFF0000 -#define AON_RTC_TIME_SEC_L_S 16 - -// Field: [15:0] SUBSEC_H -// -// Returns the upper halfword of SUBSEC register. -#define AON_RTC_TIME_SUBSEC_H_W 16 -#define AON_RTC_TIME_SUBSEC_H_M 0x0000FFFF -#define AON_RTC_TIME_SUBSEC_H_S 0 - -//***************************************************************************** -// -// Register: AON_RTC_O_SYNCLF -// -//***************************************************************************** -// Field: [0] PHASE -// -// This bit will always return the SCLK_LF phase. The return will delayed until -// a positive or negative edge of SCLK_LF is seen. -// 0: Falling edge of SCLK_LF -// 1: Rising edge of SCLK_LF -#define AON_RTC_SYNCLF_PHASE 0x00000001 -#define AON_RTC_SYNCLF_PHASE_BITN 0 -#define AON_RTC_SYNCLF_PHASE_M 0x00000001 -#define AON_RTC_SYNCLF_PHASE_S 0 - - -#endif // __AON_RTC__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h deleted file mode 100644 index a66a0d5d628..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_aiodio.h +++ /dev/null @@ -1,1030 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_aiodio_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_AIODIO_H__ -#define __HW_AUX_AIODIO_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_AIODIO component -// -//***************************************************************************** -// Input Output Mode -#define AUX_AIODIO_O_IOMODE 0x00000000 - -// General Purpose Input Output Digital Input Enable -#define AUX_AIODIO_O_GPIODIE 0x00000004 - -// Input Output Peripheral Output Enable -#define AUX_AIODIO_O_IOPOE 0x00000008 - -// General Purpose Input Output Data Out -#define AUX_AIODIO_O_GPIODOUT 0x0000000C - -// General Purpose Input Output Data In -#define AUX_AIODIO_O_GPIODIN 0x00000010 - -// General Purpose Input Output Data Out Set -#define AUX_AIODIO_O_GPIODOUTSET 0x00000014 - -// General Purpose Input Output Data Out Clear -#define AUX_AIODIO_O_GPIODOUTCLR 0x00000018 - -// General Purpose Input Output Data Out Toggle -#define AUX_AIODIO_O_GPIODOUTTGL 0x0000001C - -// Input Output 0 Peripheral Select -#define AUX_AIODIO_O_IO0PSEL 0x00000020 - -// Input Output 1 Peripheral Select -#define AUX_AIODIO_O_IO1PSEL 0x00000024 - -// Input Output 2 Peripheral Select -#define AUX_AIODIO_O_IO2PSEL 0x00000028 - -// Input Output 3 Peripheral Select -#define AUX_AIODIO_O_IO3PSEL 0x0000002C - -// Input Output 4 Peripheral Select -#define AUX_AIODIO_O_IO4PSEL 0x00000030 - -// Input Output 5 Peripheral Select -#define AUX_AIODIO_O_IO5PSEL 0x00000034 - -// Input Output 6 Peripheral Select -#define AUX_AIODIO_O_IO6PSEL 0x00000038 - -// Input Output 7 Peripheral Select -#define AUX_AIODIO_O_IO7PSEL 0x0000003C - -// Input Output Mode Low -#define AUX_AIODIO_O_IOMODEL 0x00000040 - -// Input Output Mode High -#define AUX_AIODIO_O_IOMODEH 0x00000044 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IOMODE -// -//***************************************************************************** -// Field: [15:14] IO7 -// -// Selects mode for AUXIO[8i+7]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When IOPOE bit 7 is 0: -// - If GPIODOUT bit 7 is 0: -// AUXIO[8i+7] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// - If GPIODOUT bit 7 is 1: -// AUXIO[8i+7] is driven high. -// -// When IOPOE bit 7 is 1: -// - If signal selected by -// IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// - If signal selected by -// IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When IOPOE bit 7 is 0: -// - If GPIODOUT bit 7 is 0: -// AUXIO[8i+7] is driven low. -// - If GPIODOUT bit 7 is 1: -// AUXIO[8i+7] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When IOPOE bit 7 is 1: -// - If signal selected by -// IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low. -// - If signal selected by -// IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 7 is 0: -// AUXIO[8i+7] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 7 is 1: -// AUXIO[8i+7] is enabled for digital input. -// OUT Output Mode: -// -// When IOPOE bit 7 is 0: -// GPIODOUT bit 7 drives AUXIO[8i+7]. -// -// When IOPOE bit 7 is 1: -// The signal selected by IO7PSEL.SRC drives -// AUXIO[8i+7]. -#define AUX_AIODIO_IOMODE_IO7_W 2 -#define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 -#define AUX_AIODIO_IOMODE_IO7_S 14 -#define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 -#define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 -#define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 -#define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 - -// Field: [13:12] IO6 -// -// Selects mode for AUXIO[8i+6]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When IOPOE bit 6 is 0: -// - If GPIODOUT bit 6 is 0: -// AUXIO[8i+6] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// - If GPIODOUT bit 6 is 1: -// AUXIO[8i+6] is driven high. -// -// When IOPOE bit 6 is 1: -// - If signal selected by -// IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// - If signal selected by -// IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When IOPOE bit 6 is 0: -// - If GPIODOUT bit 6 is 0: -// AUXIO[8i+6] is driven low. -// - If GPIODOUT bit 6 is 1: -// AUXIO[8i+6] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When IOPOE bit 6 is 1: -// - If signal selected by -// IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low. -// - If signal selected by -// IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 6 is 0: -// AUXIO[8i+6] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 6 is 1: -// AUXIO[8i+6] is enabled for digital input. -// OUT Output Mode: -// -// When IOPOE bit 6 is 0: -// GPIODOUT bit 6 drives AUXIO[8i+6]. -// -// When IOPOE bit 6 is 1: -// The signal selected by IO6PSEL.SRC drives -// AUXIO[8i+6]. -#define AUX_AIODIO_IOMODE_IO6_W 2 -#define AUX_AIODIO_IOMODE_IO6_M 0x00003000 -#define AUX_AIODIO_IOMODE_IO6_S 12 -#define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 -#define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 -#define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 -#define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 - -// Field: [11:10] IO5 -// -// Selects mode for AUXIO[8i+5]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When IOPOE bit 5 is 0: -// - If GPIODOUT bit 5 is 0: -// AUXIO[8i+5] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// - If GPIODOUT bit 5 is 1: -// AUXIO[8i+5] is driven high. -// -// When IOPOE bit 5 is 1: -// - If signal selected by -// IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// - If signal selected by -// IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When IOPOE bit 5 is 0: -// - If GPIODOUT bit 5 is 0: -// AUXIO[8i+5] is driven low. -// - If GPIODOUT bit 5 is 1: -// AUXIO[8i+5] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When IOPOE bit 5 is 1: -// - If signal selected by -// IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low. -// - If signal selected by -// IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 5 is 0: -// AUXIO[8i+5] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 5 is 1: -// AUXIO[8i+5] is enabled for digital input. -// OUT Output Mode: -// -// When IOPOE bit 5 is 0: -// GPIODOUT bit 5 drives AUXIO[8i+5]. -// -// When IOPOE bit 5 is 1: -// The signal selected by IO5PSEL.SRC drives -// AUXIO[8i+5]. -#define AUX_AIODIO_IOMODE_IO5_W 2 -#define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 -#define AUX_AIODIO_IOMODE_IO5_S 10 -#define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 -#define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 -#define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 -#define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 - -// Field: [9:8] IO4 -// -// Selects mode for AUXIO[8i+4]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When IOPOE bit 4 is 0: -// - If GPIODOUT bit 4 is 0: -// AUXIO[8i+4] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// - If GPIODOUT bit 4 is 1: -// AUXIO[8i+4] is driven high. -// -// When IOPOE bit 4 is 1: -// - If signal selected by -// IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// - If signal selected by -// IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When IOPOE bit 4 is 0: -// - If GPIODOUT bit 4 is 0: -// AUXIO[8i+4] is driven low. -// - If GPIODOUT bit 4 is 1: -// AUXIO[8i+4] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When IOPOE bit 4 is 1: -// - If signal selected by -// IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low. -// - If signal selected by -// IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 4 is 0: -// AUXIO[8i+4] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 4 is 1: -// AUXIO[8i+4] is enabled for digital input. -// OUT Output Mode: -// -// When IOPOE bit 4 is 0: -// GPIODOUT bit 4 drives AUXIO[8i+4]. -// -// When IOPOE bit 4 is 1: -// The signal selected by IO4PSEL.SRC drives -// AUXIO[8i+4]. -#define AUX_AIODIO_IOMODE_IO4_W 2 -#define AUX_AIODIO_IOMODE_IO4_M 0x00000300 -#define AUX_AIODIO_IOMODE_IO4_S 8 -#define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 -#define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 -#define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 -#define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 - -// Field: [7:6] IO3 -// -// Selects mode for AUXIO[8i+3]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When IOPOE bit 3 is 0: -// - If GPIODOUT bit 3 is 0: -// AUXIO[8i+3] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// - If GPIODOUT bit 3 is 1: -// AUXIO[8i+3] is driven high. -// -// When IOPOE bit 3 is 1: -// - If signal selected by -// IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// - If signal selected by -// IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When IOPOE bit 3 is 0: -// - If GPIODOUT bit 3 is 0: -// AUXIO[8i+3] is driven low. -// - If GPIODOUT bit 3 is 1: -// AUXIO[8i+3] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When IOPOE bit 3 is 1: -// - If signal selected by -// IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low. -// - If signal selected by -// IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 3 is 0: -// AUXIO[8i+3] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 3 is 1: -// AUXIO[8i+3] is enabled for digital input. -// OUT Output Mode: -// -// When IOPOE bit 3 is 0: -// GPIODOUT bit 3 drives AUXIO[8i+3]. -// -// When IOPOE bit 3 is 1: -// The signal selected by IO3PSEL.SRC drives -// AUXIO[8i+3]. -#define AUX_AIODIO_IOMODE_IO3_W 2 -#define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 -#define AUX_AIODIO_IOMODE_IO3_S 6 -#define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 -#define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 -#define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 -#define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 - -// Field: [5:4] IO2 -// -// Select mode for AUXIO[8i+2]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When IOPOE bit 2 is 0: -// - If GPIODOUT bit 2 is 0: -// AUXIO[8i+2] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// - If GPIODOUT bit 2 is 1: -// AUXIO[8i+2] is driven high. -// -// When IOPOE bit 2 is 1: -// - If signal selected by -// IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// - If signal selected by -// IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When IOPOE bit 2 is 0: -// - If GPIODOUT bit 2 is 0: -// AUXIO[8i+2] is driven low. -// - If GPIODOUT bit 2 is 1: -// AUXIO[8i+2] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When IOPOE bit 2 is 1: -// - If signal selected by -// IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low. -// - If signal selected by -// IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 2 is 0: -// AUXIO[8i+2] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 2 is 1: -// AUXIO[8i+2] is enabled for digital input. -// OUT Output Mode: -// -// When IOPOE bit 2 is 0: -// GPIODOUT bit 2 drives AUXIO[8i+2]. -// -// When IOPOE bit 2 is 1: -// The signal selected by IO2PSEL.SRC drives -// AUXIO[8i+2]. -#define AUX_AIODIO_IOMODE_IO2_W 2 -#define AUX_AIODIO_IOMODE_IO2_M 0x00000030 -#define AUX_AIODIO_IOMODE_IO2_S 4 -#define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 -#define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 -#define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 -#define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 - -// Field: [3:2] IO1 -// -// Select mode for AUXIO[8i+1]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When IOPOE bit 1 is 0: -// - If GPIODOUT bit 1 is 0: -// AUXIO[8i+1] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// - If GPIODOUT bit 1 is 1: -// AUXIO[8i+1] is driven high. -// -// When IOPOE bit 1 is 1: -// - If signal selected by -// IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// - If signal selected by -// IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When IOPOE bit 1 is 0: -// - If GPIODOUT bit 1 is 0: -// AUXIO[8i+1] is driven low. -// - If GPIODOUT bit 1 is 1: -// AUXIO[8i+1] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When IOPOE bit 1 is 1: -// - If signal selected by -// IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low. -// - If signal selected by -// IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 1 is 0: -// AUXIO[8i+1] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 1 is 1: -// AUXIO[8i+1] is enabled for digital input. -// OUT Output Mode: -// -// When IOPOE bit 1 is 0: -// GPIODOUT bit 1 drives AUXIO[8i+1]. -// -// When IOPOE bit 1 is 1: -// The signal selected by IO1PSEL.SRC drives -// AUXIO[8i+1]. -#define AUX_AIODIO_IOMODE_IO1_W 2 -#define AUX_AIODIO_IOMODE_IO1_M 0x0000000C -#define AUX_AIODIO_IOMODE_IO1_S 2 -#define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C -#define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 -#define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 -#define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 - -// Field: [1:0] IO0 -// -// Select mode for AUXIO[8i+0]. -// ENUMs: -// OPEN_SOURCE Open-Source Mode: -// -// When IOPOE bit 0 is 0: -// - If GPIODOUT bit 0 is 0: -// AUXIO[8i+0] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// - If GPIODOUT bit 0 is 1: -// AUXIO[8i+0] is driven high. -// -// When IOPOE bit 0 is 1: -// - If signal selected by -// IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// - If signal selected by -// IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high. -// OPEN_DRAIN Open-Drain Mode: -// -// When IOPOE bit 0 is 0: -// - If GPIODOUT bit 0 is 0: -// AUXIO[8i+0] is driven low. -// - If GPIODOUT bit 0 is 1: -// AUXIO[8i+0] is tri-stated or pulled. This -// depends on IOC:IOCFGn.PULL_CTL. -// -// When IOPOE bit 0 is 1: -// - If signal selected by -// IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low. -// - If signal selected by -// IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or -// pulled. This depends on IOC:IOCFGn.PULL_CTL. -// IN Input Mode: -// -// When GPIODIE bit 0 is 0: -// AUXIO[8i+0] is enabled for analog signal -// transfer. -// -// When GPIODIE bit 0 is 1: -// AUXIO[8i+0] is enabled for digital input. -// OUT Output Mode: -// -// When IOPOE bit 0 is 0: -// GPIODOUT bit 0 drives AUXIO[8i+0]. -// -// When IOPOE bit 0 is 1: -// The signal selected by IO0PSEL.SRC drives -// AUXIO[8i+0]. -#define AUX_AIODIO_IOMODE_IO0_W 2 -#define AUX_AIODIO_IOMODE_IO0_M 0x00000003 -#define AUX_AIODIO_IOMODE_IO0_S 0 -#define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 -#define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 -#define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 -#define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_GPIODIE -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Write 1 to bit index n in this bit vector to enable digital input buffer for -// AUXIO[8i+n]. -// Write 0 to bit index n in this bit vector to disable digital input buffer -// for AUXIO[8i+n]. -// -// You must enable the digital input buffer for AUXIO[8i+n] to read the pin -// value in GPIODIN. -// You must disable the digital input buffer for analog input or pins that -// float to avoid current leakage. -#define AUX_AIODIO_GPIODIE_IO7_0_W 8 -#define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODIE_IO7_0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IOPOE -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be -// driven from source given in [IOnPSEL.*]. -// Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be -// driven from bit n in GPIODOUT. -#define AUX_AIODIO_IOPOE_IO7_0_W 8 -#define AUX_AIODIO_IOPOE_IO7_0_M 0x000000FF -#define AUX_AIODIO_IOPOE_IO7_0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_GPIODOUT -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. -// Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. -// -// You must clear bit n in IOPOE to connect bit n in this bit vector to -// AUXIO[8i+n]. -#define AUX_AIODIO_GPIODOUT_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUT_IO7_0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_GPIODIN -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit -// n is set. Otherwise, bit n is read as 0. -#define AUX_AIODIO_GPIODIN_IO7_0_W 8 -#define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODIN_IO7_0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_GPIODOUTSET -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Write 1 to bit index n in this bit vector to set GPIODOUT bit n. -// -// Read value is 0. -#define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_GPIODOUTCLR -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. -// -// Read value is 0. -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_GPIODOUTTGL -// -//***************************************************************************** -// Field: [7:0] IO7_0 -// -// Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. -// -// Read value is 0. -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF -#define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IO0PSEL -// -//***************************************************************************** -// Field: [2:0] SRC -// -// Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is -// set. -// ENUMs: -// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. -// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. -// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. -// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. -// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. -// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. -// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. -// AUX_EV_OBS Peripheral output mux selects event selected by -// AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO0PSEL_SRC_W 3 -#define AUX_AIODIO_IO0PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO0PSEL_SRC_S 0 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO0PSEL_SRC_AUX_EV_OBS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IO1PSEL -// -//***************************************************************************** -// Field: [2:0] SRC -// -// Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is -// set. -// ENUMs: -// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. -// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. -// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. -// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. -// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. -// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. -// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. -// AUX_EV_OBS Peripheral output mux selects event selected by -// AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO1PSEL_SRC_W 3 -#define AUX_AIODIO_IO1PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO1PSEL_SRC_S 0 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO1PSEL_SRC_AUX_EV_OBS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IO2PSEL -// -//***************************************************************************** -// Field: [2:0] SRC -// -// Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is -// set. -// ENUMs: -// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. -// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. -// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. -// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. -// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. -// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. -// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. -// AUX_EV_OBS Peripheral output mux selects event selected by -// AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO2PSEL_SRC_W 3 -#define AUX_AIODIO_IO2PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO2PSEL_SRC_S 0 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO2PSEL_SRC_AUX_EV_OBS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IO3PSEL -// -//***************************************************************************** -// Field: [2:0] SRC -// -// Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is -// set. -// ENUMs: -// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. -// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. -// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. -// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. -// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. -// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. -// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. -// AUX_EV_OBS Peripheral output mux selects event selected by -// AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO3PSEL_SRC_W 3 -#define AUX_AIODIO_IO3PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO3PSEL_SRC_S 0 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO3PSEL_SRC_AUX_EV_OBS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IO4PSEL -// -//***************************************************************************** -// Field: [2:0] SRC -// -// Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is -// set. -// ENUMs: -// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. -// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. -// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. -// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. -// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. -// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. -// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. -// AUX_EV_OBS Peripheral output mux selects event selected by -// AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO4PSEL_SRC_W 3 -#define AUX_AIODIO_IO4PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO4PSEL_SRC_S 0 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO4PSEL_SRC_AUX_EV_OBS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IO5PSEL -// -//***************************************************************************** -// Field: [2:0] SRC -// -// Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is -// set. -// ENUMs: -// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. -// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. -// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. -// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. -// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. -// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. -// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. -// AUX_EV_OBS Peripheral output mux selects event selected by -// AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO5PSEL_SRC_W 3 -#define AUX_AIODIO_IO5PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO5PSEL_SRC_S 0 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO5PSEL_SRC_AUX_EV_OBS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IO6PSEL -// -//***************************************************************************** -// Field: [2:0] SRC -// -// Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is -// set. -// ENUMs: -// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. -// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. -// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. -// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. -// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. -// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. -// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. -// AUX_EV_OBS Peripheral output mux selects event selected by -// AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO6PSEL_SRC_W 3 -#define AUX_AIODIO_IO6PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO6PSEL_SRC_S 0 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO6PSEL_SRC_AUX_EV_OBS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IO7PSEL -// -//***************************************************************************** -// Field: [2:0] SRC -// -// Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is -// set. -// ENUMs: -// AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. -// AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. -// AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. -// AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. -// AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version -// of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. -// AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. -// AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. -// AUX_EV_OBS Peripheral output mux selects event selected by -// AUX_EVCTL:EVOBSCFG -#define AUX_AIODIO_IO7PSEL_SRC_W 3 -#define AUX_AIODIO_IO7PSEL_SRC_M 0x00000007 -#define AUX_AIODIO_IO7PSEL_SRC_S 0 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV3 0x00000006 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV2 0x00000005 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV1 0x00000004 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV0 0x00000003 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_MOSI 0x00000002 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_SCLK 0x00000001 -#define AUX_AIODIO_IO7PSEL_SRC_AUX_EV_OBS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IOMODEL -// -//***************************************************************************** -// Field: [7:6] IO3 -// -// See IOMODE.IO3. -#define AUX_AIODIO_IOMODEL_IO3_W 2 -#define AUX_AIODIO_IOMODEL_IO3_M 0x000000C0 -#define AUX_AIODIO_IOMODEL_IO3_S 6 - -// Field: [5:4] IO2 -// -// See IOMODE.IO2. -#define AUX_AIODIO_IOMODEL_IO2_W 2 -#define AUX_AIODIO_IOMODEL_IO2_M 0x00000030 -#define AUX_AIODIO_IOMODEL_IO2_S 4 - -// Field: [3:2] IO1 -// -// See IOMODE.IO1. -#define AUX_AIODIO_IOMODEL_IO1_W 2 -#define AUX_AIODIO_IOMODEL_IO1_M 0x0000000C -#define AUX_AIODIO_IOMODEL_IO1_S 2 - -// Field: [1:0] IO0 -// -// See IOMODE.IO0. -#define AUX_AIODIO_IOMODEL_IO0_W 2 -#define AUX_AIODIO_IOMODEL_IO0_M 0x00000003 -#define AUX_AIODIO_IOMODEL_IO0_S 0 - -//***************************************************************************** -// -// Register: AUX_AIODIO_O_IOMODEH -// -//***************************************************************************** -// Field: [7:6] IO7 -// -// See IOMODE.IO7. -#define AUX_AIODIO_IOMODEH_IO7_W 2 -#define AUX_AIODIO_IOMODEH_IO7_M 0x000000C0 -#define AUX_AIODIO_IOMODEH_IO7_S 6 - -// Field: [5:4] IO6 -// -// See IOMODE.IO6. -#define AUX_AIODIO_IOMODEH_IO6_W 2 -#define AUX_AIODIO_IOMODEH_IO6_M 0x00000030 -#define AUX_AIODIO_IOMODEH_IO6_S 4 - -// Field: [3:2] IO5 -// -// See IOMODE.IO5. -#define AUX_AIODIO_IOMODEH_IO5_W 2 -#define AUX_AIODIO_IOMODEH_IO5_M 0x0000000C -#define AUX_AIODIO_IOMODEH_IO5_S 2 - -// Field: [1:0] IO4 -// -// See IOMODE.IO4. -#define AUX_AIODIO_IOMODEH_IO4_W 2 -#define AUX_AIODIO_IOMODEH_IO4_M 0x00000003 -#define AUX_AIODIO_IOMODEH_IO4_S 0 - - -#endif // __AUX_AIODIO__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h deleted file mode 100644 index 8b08db3d27b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_anaif.h +++ /dev/null @@ -1,633 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_anaif_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_ANAIF_H__ -#define __HW_AUX_ANAIF_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_ANAIF component -// -//***************************************************************************** -// ADC Control -#define AUX_ANAIF_O_ADCCTL 0x00000010 - -// ADC FIFO Status -#define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 - -// ADC FIFO -#define AUX_ANAIF_O_ADCFIFO 0x00000018 - -// ADC Trigger -#define AUX_ANAIF_O_ADCTRIG 0x0000001C - -// Current Source Control -#define AUX_ANAIF_O_ISRCCTL 0x00000020 - -// DAC Control -#define AUX_ANAIF_O_DACCTL 0x00000030 - -// Low Power Mode Bias Control -#define AUX_ANAIF_O_LPMBIASCTL 0x00000034 - -// DAC Sample Control -#define AUX_ANAIF_O_DACSMPLCTL 0x00000038 - -// DAC Sample Configuration 0 -#define AUX_ANAIF_O_DACSMPLCFG0 0x0000003C - -// DAC Sample Configuration 1 -#define AUX_ANAIF_O_DACSMPLCFG1 0x00000040 - -// DAC Value -#define AUX_ANAIF_O_DACVALUE 0x00000044 - -// DAC Status -#define AUX_ANAIF_O_DACSTAT 0x00000048 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_ADCCTL -// -//***************************************************************************** -// Field: [14] START_POL -// -// Select active polarity for START_SRC event. -// ENUMs: -// FALL Set ADC trigger on falling edge of event source. -// RISE Set ADC trigger on rising edge of event source. -#define AUX_ANAIF_ADCCTL_START_POL 0x00004000 -#define AUX_ANAIF_ADCCTL_START_POL_BITN 14 -#define AUX_ANAIF_ADCCTL_START_POL_M 0x00004000 -#define AUX_ANAIF_ADCCTL_START_POL_S 14 -#define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00004000 -#define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 - -// Field: [13:8] START_SRC -// -// Select ADC trigger event source from the asynchronous AUX event bus. -// -// Set START_SRC to NO_EVENT if you want to trigger the ADC manually through -// ADCTRIG.START. -// -// If you write a non-enumerated value the behavior is identical to NO_EVENT. -// The written value is returned when read. -// ENUMs: -// NO_EVENT No event. -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_ANAIF_ADCCTL_START_SRC_W 6 -#define AUX_ANAIF_ADCCTL_START_SRC_M 0x00003F00 -#define AUX_ANAIF_ADCCTL_START_SRC_S 8 -#define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT 0x00003F00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_ISRC_RESET_N 0x00003800 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TDC_DONE 0x00003700 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER0_EV 0x00003600 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER1_EV 0x00003500 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_PULSE 0x00003400 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV3 0x00003300 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV2 0x00003200 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV1 0x00003100 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV0 0x00003000 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00002F00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00002E00 -#define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00002B00 -#define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00002A00 -#define AUX_ANAIF_ADCCTL_START_SRC_VDDR_RECHARGE 0x00002900 -#define AUX_ANAIF_ADCCTL_START_SRC_MCU_ACTIVE 0x00002800 -#define AUX_ANAIF_ADCCTL_START_SRC_PWR_DWN 0x00002700 -#define AUX_ANAIF_ADCCTL_START_SRC_SCLK_LF 0x00002600 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_TEMP_UPD 0x00002500 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_BAT_UPD 0x00002400 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_4KHZ 0x00002300 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2_DLY 0x00002200 -#define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2 0x00002100 -#define AUX_ANAIF_ADCCTL_START_SRC_MANUAL_EV 0x00002000 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO31 0x00001F00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO30 0x00001E00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO29 0x00001D00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO28 0x00001C00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO27 0x00001B00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO26 0x00001A00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO25 0x00001900 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO24 0x00001800 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO23 0x00001700 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO22 0x00001600 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO21 0x00001500 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO20 0x00001400 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO19 0x00001300 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO18 0x00001200 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO17 0x00001100 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO16 0x00001000 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00000F00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00000E00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00000D00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00000C00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00000B00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00000A00 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00000900 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00000800 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00000700 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00000600 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00000500 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00000400 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00000300 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000200 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000100 -#define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000000 - -// Field: [1:0] CMD -// -// ADC interface command. -// -// Non-enumerated values are not supported. The written value is returned when -// read. -// ENUMs: -// FLUSH Flush ADC FIFO. -// -// You must set CMD to EN or -// DIS after flush. -// -// System CPU must wait two -// clock cycles before it sets CMD to EN or DIS. -// EN Enable ADC interface. -// DIS Disable ADC interface. -#define AUX_ANAIF_ADCCTL_CMD_W 2 -#define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 -#define AUX_ANAIF_ADCCTL_CMD_S 0 -#define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 -#define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 -#define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_ADCFIFOSTAT -// -//***************************************************************************** -// Field: [4] OVERFLOW -// -// FIFO overflow flag. -// -// 0: FIFO has not overflowed. -// 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. -// -// When the flag is set, the ADC FIFO write pointer is static. It is not -// possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 -#define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 - -// Field: [3] UNDERFLOW -// -// FIFO underflow flag. -// -// 0: FIFO has not underflowed. -// 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. -// -// When the flag is set, the ADC FIFO read pointer is static. Read returns the -// previous sample that was read. Flush FIFO to clear the flag. -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 -#define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 - -// Field: [2] FULL -// -// FIFO full flag. -// -// 0: FIFO is not full, there is less than 4 samples in the FIFO. -// 1: FIFO is full, there are 4 samples in the FIFO. -// -// When the flag is set, it is not possible to add more samples to the ADC -// FIFO. An attempt to add samples sets the OVERFLOW flag. -#define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 -#define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 - -// Field: [1] ALMOST_FULL -// -// FIFO almost full flag. -// -// 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL -// flag is also asserted in the latter case. -// 1: There are 3 samples in the FIFO, there is room for one more sample. -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 -#define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 - -// Field: [0] EMPTY -// -// FIFO empty flag. -// -// 0: FIFO contains one or more samples. -// 1: FIFO is empty. -// -// When the flag is set, read returns the previous sample that was read and -// sets the UNDERFLOW flag. -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 -#define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_ADCFIFO -// -//***************************************************************************** -// Field: [11:0] DATA -// -// FIFO data. -// -// Read: -// Get oldest ADC sample from FIFO. -// -// Write: -// Write dummy sample to FIFO. This is useful for code development when you do -// not have real ADC samples. -#define AUX_ANAIF_ADCFIFO_DATA_W 12 -#define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF -#define AUX_ANAIF_ADCFIFO_DATA_S 0 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_ADCTRIG -// -//***************************************************************************** -// Field: [0] START -// -// Manual ADC trigger. -// -// 0: No effect. -// 1: Single ADC trigger. -// -// To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to -// avoid conflict with event-driven ADC trigger. -#define AUX_ANAIF_ADCTRIG_START 0x00000001 -#define AUX_ANAIF_ADCTRIG_START_BITN 0 -#define AUX_ANAIF_ADCTRIG_START_M 0x00000001 -#define AUX_ANAIF_ADCTRIG_START_S 0 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_ISRCCTL -// -//***************************************************************************** -// Field: [0] RESET_N -// -// ISRC reset control. -// -// 0: ISRC drives 0 uA. -// 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. -#define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 -#define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 -#define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 -#define AUX_ANAIF_ISRCCTL_RESET_N_S 0 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_DACCTL -// -//***************************************************************************** -// Field: [5] DAC_EN -// -// DAC module enable. -// -// 0: Disable DAC. -// 1: Enable DAC. -// -// The Sensor Controller must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ -// equals PDA. -// -// The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA -// in Standby TI-RTOS power mode. The System CPU must set -// AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE to use the DAC in Active -// and Idle TI-RTOS power modes. -#define AUX_ANAIF_DACCTL_DAC_EN 0x00000020 -#define AUX_ANAIF_DACCTL_DAC_EN_BITN 5 -#define AUX_ANAIF_DACCTL_DAC_EN_M 0x00000020 -#define AUX_ANAIF_DACCTL_DAC_EN_S 5 - -// Field: [4] DAC_BUFFER_EN -// -// DAC buffer enable. -// -// DAC buffer reduces the time required to produce the programmed voltage at -// the expense of increased current consumption. -// -// 0: Disable DAC buffer. -// 1: Enable DAC buffer. -// -// Enable buffer when DAC_VOUT_SEL equals COMPA_IN. -// -// Do not enable the buffer when AUX_SYSIF:OPMODEREQ.REQ equals PDA or PDLP. -#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN 0x00000010 -#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_BITN 4 -#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_M 0x00000010 -#define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_S 4 - -// Field: [3] DAC_PRECHARGE_EN -// -// DAC precharge enable. -// -// Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and -// VDDS is higher than 2.65 V. -// -// DAC output voltage range: -// -// 0: 0 V to 1.28 V. -// 1: 1.28 V to 2.56 V. -// -// Otherwise, see ADI_4_AUX:MUX2.DAC_VREF_SEL for DAC output voltage range. -// -// Enable precharge 1 us before you enable the DAC and the buffer. -#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN 0x00000008 -#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_BITN 3 -#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_M 0x00000008 -#define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S 3 - -// Field: [2:0] DAC_VOUT_SEL -// -// DAC output connection. -// -// An analog node must only have one driver. Other drivers for the following -// analog nodes are configured in [ANATOP_MMAP::ADI_4_AUX:*]. -// ENUMs: -// COMPA_IN Connect to COMPA_IN analog node. -// -// Required setting to drive -// external load selected in -// ADI_4_AUX:MUX1.COMPA_IN. -// COMPA_REF Connect to COMPA_REF analog node. -// -// It is not possible to -// drive external loads connected to COMPA_REF I/O -// mux with this setting. -// COMPB_REF Connect to COMPB_REF analog node. -// -// Required setting to use -// Comparator B. -// NC Connect to nothing -// -// It is recommended to use -// NC as intermediate step when you change -// DAC_VOUT_SEL. -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_W 3 -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_M 0x00000007 -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_S 0 -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_IN 0x00000004 -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_REF 0x00000002 -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPB_REF 0x00000001 -#define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_NC 0x00000000 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_LPMBIASCTL -// -//***************************************************************************** -// Field: [0] EN -// -// Module enable. -// -// 0: Disable low power mode bias module. -// 1: Enable low power mode bias module. -// -// Set EN to 1 15 us before you enable the DAC or Comparator A. -#define AUX_ANAIF_LPMBIASCTL_EN 0x00000001 -#define AUX_ANAIF_LPMBIASCTL_EN_BITN 0 -#define AUX_ANAIF_LPMBIASCTL_EN_M 0x00000001 -#define AUX_ANAIF_LPMBIASCTL_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_DACSMPLCTL -// -//***************************************************************************** -// Field: [0] EN -// -// DAC sample clock enable. -// -// 0: Disable sample clock. The sample clock stops low and DACSTAT becomes 0 -// when the current sample clock period completes. -// 1: Enable DAC sample clock. DACSTAT must be 0 before you enable sample -// clock. -#define AUX_ANAIF_DACSMPLCTL_EN 0x00000001 -#define AUX_ANAIF_DACSMPLCTL_EN_BITN 0 -#define AUX_ANAIF_DACSMPLCTL_EN_M 0x00000001 -#define AUX_ANAIF_DACSMPLCTL_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_DACSMPLCFG0 -// -//***************************************************************************** -// Field: [5:0] CLKDIV -// -// Clock division. -// -// AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the -// sample clock base frequency. -// -// 0: Divide by 1. -// 1: Divide by 2. -// ... -// 63: Divide by 64. -#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_W 6 -#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_M 0x0000003F -#define AUX_ANAIF_DACSMPLCFG0_CLKDIV_S 0 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_DACSMPLCFG1 -// -//***************************************************************************** -// Field: [14] H_PER -// -// High time. -// -// The sample clock period is high for this many base periods. -// -// 0: 2 periods -// 1: 4 periods -#define AUX_ANAIF_DACSMPLCFG1_H_PER 0x00004000 -#define AUX_ANAIF_DACSMPLCFG1_H_PER_BITN 14 -#define AUX_ANAIF_DACSMPLCFG1_H_PER_M 0x00004000 -#define AUX_ANAIF_DACSMPLCFG1_H_PER_S 14 - -// Field: [13:12] L_PER -// -// Low time. -// -// The sample clock period is low for this many base periods. -// -// 0: 1 period -// 1: 2 periods -// 2: 3 periods -// 3: 4 periods -#define AUX_ANAIF_DACSMPLCFG1_L_PER_W 2 -#define AUX_ANAIF_DACSMPLCFG1_L_PER_M 0x00003000 -#define AUX_ANAIF_DACSMPLCFG1_L_PER_S 12 - -// Field: [11:8] SETUP_CNT -// -// Setup count. -// -// Number of active sample clock periods during the setup phase. -// -// 0: 1 sample clock period -// 1: 2 sample clock periods -// ... -// 15 : 16 sample clock periods -#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_W 4 -#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_M 0x00000F00 -#define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_S 8 - -// Field: [7:0] HOLD_INTERVAL -// -// Hold interval. -// -// Number of inactive sample clock periods between each active sample clock -// period during hold phase. The sample clock is low when inactive. -// -// The range is 0 to 255. -#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_W 8 -#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_M 0x000000FF -#define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_S 0 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_DACVALUE -// -//***************************************************************************** -// Field: [7:0] VALUE -// -// DAC value. -// -// Digital data word for the DAC. -// -// Only change VALUE when DACCTL.DAC_EN is 0. Then wait 1 us before you enable -// the DAC. -#define AUX_ANAIF_DACVALUE_VALUE_W 8 -#define AUX_ANAIF_DACVALUE_VALUE_M 0x000000FF -#define AUX_ANAIF_DACVALUE_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_ANAIF_O_DACSTAT -// -//***************************************************************************** -// Field: [1] SETUP_ACTIVE -// -// DAC setup phase status. -// -// 0: Sample clock is disabled or setup phase is complete. -// 1: Setup phase in progress. -#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE 0x00000002 -#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_BITN 1 -#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_M 0x00000002 -#define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_S 1 - -// Field: [0] HOLD_ACTIVE -// -// DAC hold phase status. -// -// 0: Sample clock is disabled or DAC is not in hold phase. -// 1: Hold phase in progress. -#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE 0x00000001 -#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_BITN 0 -#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_M 0x00000001 -#define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_S 0 - - -#endif // __AUX_ANAIF__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h deleted file mode 100644 index b92db64430c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_evctl.h +++ /dev/null @@ -1,2355 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_evctl_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_EVCTL_H__ -#define __HW_AUX_EVCTL_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_EVCTL component -// -//***************************************************************************** -// Event Status 0 -#define AUX_EVCTL_O_EVSTAT0 0x00000000 - -// Event Status 1 -#define AUX_EVCTL_O_EVSTAT1 0x00000004 - -// Event Status 2 -#define AUX_EVCTL_O_EVSTAT2 0x00000008 - -// Event Status 3 -#define AUX_EVCTL_O_EVSTAT3 0x0000000C - -// Sensor Controller Engine Wait Event Configuration 0 -#define AUX_EVCTL_O_SCEWEVCFG0 0x00000010 - -// Sensor Controller Engine Wait Event Configuration 1 -#define AUX_EVCTL_O_SCEWEVCFG1 0x00000014 - -// Direct Memory Access Control -#define AUX_EVCTL_O_DMACTL 0x00000018 - -// Software Event Set -#define AUX_EVCTL_O_SWEVSET 0x00000020 - -// Events To AON Flags -#define AUX_EVCTL_O_EVTOAONFLAGS 0x00000024 - -// Events To AON Polarity -#define AUX_EVCTL_O_EVTOAONPOL 0x00000028 - -// Events To AON Clear -#define AUX_EVCTL_O_EVTOAONFLAGSCLR 0x0000002C - -// Events to MCU Flags -#define AUX_EVCTL_O_EVTOMCUFLAGS 0x00000030 - -// Event To MCU Polarity -#define AUX_EVCTL_O_EVTOMCUPOL 0x00000034 - -// Events To MCU Flags Clear -#define AUX_EVCTL_O_EVTOMCUFLAGSCLR 0x00000038 - -// Combined Event To MCU Mask -#define AUX_EVCTL_O_COMBEVTOMCUMASK 0x0000003C - -// Event Observation Configuration -#define AUX_EVCTL_O_EVOBSCFG 0x00000040 - -// Programmable Delay -#define AUX_EVCTL_O_PROGDLY 0x00000044 - -// Manual -#define AUX_EVCTL_O_MANUAL 0x00000048 - -// Event Status 0 Low -#define AUX_EVCTL_O_EVSTAT0L 0x0000004C - -// Event Status 0 High -#define AUX_EVCTL_O_EVSTAT0H 0x00000050 - -// Event Status 1 Low -#define AUX_EVCTL_O_EVSTAT1L 0x00000054 - -// Event Status 1 High -#define AUX_EVCTL_O_EVSTAT1H 0x00000058 - -// Event Status 2 Low -#define AUX_EVCTL_O_EVSTAT2L 0x0000005C - -// Event Status 2 High -#define AUX_EVCTL_O_EVSTAT2H 0x00000060 - -// Event Status 3 Low -#define AUX_EVCTL_O_EVSTAT3L 0x00000064 - -// Event Status 3 High -#define AUX_EVCTL_O_EVSTAT3H 0x00000068 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT0 -// -//***************************************************************************** -// Field: [15] AUXIO15 -// -// AUXIO15 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT0_AUXIO15 0x00008000 -#define AUX_EVCTL_EVSTAT0_AUXIO15_BITN 15 -#define AUX_EVCTL_EVSTAT0_AUXIO15_M 0x00008000 -#define AUX_EVCTL_EVSTAT0_AUXIO15_S 15 - -// Field: [14] AUXIO14 -// -// AUXIO14 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT0_AUXIO14 0x00004000 -#define AUX_EVCTL_EVSTAT0_AUXIO14_BITN 14 -#define AUX_EVCTL_EVSTAT0_AUXIO14_M 0x00004000 -#define AUX_EVCTL_EVSTAT0_AUXIO14_S 14 - -// Field: [13] AUXIO13 -// -// AUXIO13 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT0_AUXIO13 0x00002000 -#define AUX_EVCTL_EVSTAT0_AUXIO13_BITN 13 -#define AUX_EVCTL_EVSTAT0_AUXIO13_M 0x00002000 -#define AUX_EVCTL_EVSTAT0_AUXIO13_S 13 - -// Field: [12] AUXIO12 -// -// AUXIO12 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT0_AUXIO12 0x00001000 -#define AUX_EVCTL_EVSTAT0_AUXIO12_BITN 12 -#define AUX_EVCTL_EVSTAT0_AUXIO12_M 0x00001000 -#define AUX_EVCTL_EVSTAT0_AUXIO12_S 12 - -// Field: [11] AUXIO11 -// -// AUXIO11 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT0_AUXIO11 0x00000800 -#define AUX_EVCTL_EVSTAT0_AUXIO11_BITN 11 -#define AUX_EVCTL_EVSTAT0_AUXIO11_M 0x00000800 -#define AUX_EVCTL_EVSTAT0_AUXIO11_S 11 - -// Field: [10] AUXIO10 -// -// AUXIO10 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT0_AUXIO10 0x00000400 -#define AUX_EVCTL_EVSTAT0_AUXIO10_BITN 10 -#define AUX_EVCTL_EVSTAT0_AUXIO10_M 0x00000400 -#define AUX_EVCTL_EVSTAT0_AUXIO10_S 10 - -// Field: [9] AUXIO9 -// -// AUXIO9 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT0_AUXIO9 0x00000200 -#define AUX_EVCTL_EVSTAT0_AUXIO9_BITN 9 -#define AUX_EVCTL_EVSTAT0_AUXIO9_M 0x00000200 -#define AUX_EVCTL_EVSTAT0_AUXIO9_S 9 - -// Field: [8] AUXIO8 -// -// AUXIO8 pin level, read value corresponds to AUX_AIODIO1:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT0_AUXIO8 0x00000100 -#define AUX_EVCTL_EVSTAT0_AUXIO8_BITN 8 -#define AUX_EVCTL_EVSTAT0_AUXIO8_M 0x00000100 -#define AUX_EVCTL_EVSTAT0_AUXIO8_S 8 - -// Field: [7] AUXIO7 -// -// AUXIO7 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT0_AUXIO7 0x00000080 -#define AUX_EVCTL_EVSTAT0_AUXIO7_BITN 7 -#define AUX_EVCTL_EVSTAT0_AUXIO7_M 0x00000080 -#define AUX_EVCTL_EVSTAT0_AUXIO7_S 7 - -// Field: [6] AUXIO6 -// -// AUXIO6 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT0_AUXIO6 0x00000040 -#define AUX_EVCTL_EVSTAT0_AUXIO6_BITN 6 -#define AUX_EVCTL_EVSTAT0_AUXIO6_M 0x00000040 -#define AUX_EVCTL_EVSTAT0_AUXIO6_S 6 - -// Field: [5] AUXIO5 -// -// AUXIO5 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT0_AUXIO5 0x00000020 -#define AUX_EVCTL_EVSTAT0_AUXIO5_BITN 5 -#define AUX_EVCTL_EVSTAT0_AUXIO5_M 0x00000020 -#define AUX_EVCTL_EVSTAT0_AUXIO5_S 5 - -// Field: [4] AUXIO4 -// -// AUXIO4 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT0_AUXIO4 0x00000010 -#define AUX_EVCTL_EVSTAT0_AUXIO4_BITN 4 -#define AUX_EVCTL_EVSTAT0_AUXIO4_M 0x00000010 -#define AUX_EVCTL_EVSTAT0_AUXIO4_S 4 - -// Field: [3] AUXIO3 -// -// AUXIO3 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT0_AUXIO3 0x00000008 -#define AUX_EVCTL_EVSTAT0_AUXIO3_BITN 3 -#define AUX_EVCTL_EVSTAT0_AUXIO3_M 0x00000008 -#define AUX_EVCTL_EVSTAT0_AUXIO3_S 3 - -// Field: [2] AUXIO2 -// -// AUXIO2 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT0_AUXIO2 0x00000004 -#define AUX_EVCTL_EVSTAT0_AUXIO2_BITN 2 -#define AUX_EVCTL_EVSTAT0_AUXIO2_M 0x00000004 -#define AUX_EVCTL_EVSTAT0_AUXIO2_S 2 - -// Field: [1] AUXIO1 -// -// AUXIO1 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT0_AUXIO1 0x00000002 -#define AUX_EVCTL_EVSTAT0_AUXIO1_BITN 1 -#define AUX_EVCTL_EVSTAT0_AUXIO1_M 0x00000002 -#define AUX_EVCTL_EVSTAT0_AUXIO1_S 1 - -// Field: [0] AUXIO0 -// -// AUXIO0 pin level, read value corresponds to AUX_AIODIO0:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT0_AUXIO0 0x00000001 -#define AUX_EVCTL_EVSTAT0_AUXIO0_BITN 0 -#define AUX_EVCTL_EVSTAT0_AUXIO0_M 0x00000001 -#define AUX_EVCTL_EVSTAT0_AUXIO0_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT1 -// -//***************************************************************************** -// Field: [15] AUXIO31 -// -// AUXIO31 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT1_AUXIO31 0x00008000 -#define AUX_EVCTL_EVSTAT1_AUXIO31_BITN 15 -#define AUX_EVCTL_EVSTAT1_AUXIO31_M 0x00008000 -#define AUX_EVCTL_EVSTAT1_AUXIO31_S 15 - -// Field: [14] AUXIO30 -// -// AUXIO30 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT1_AUXIO30 0x00004000 -#define AUX_EVCTL_EVSTAT1_AUXIO30_BITN 14 -#define AUX_EVCTL_EVSTAT1_AUXIO30_M 0x00004000 -#define AUX_EVCTL_EVSTAT1_AUXIO30_S 14 - -// Field: [13] AUXIO29 -// -// AUXIO29 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT1_AUXIO29 0x00002000 -#define AUX_EVCTL_EVSTAT1_AUXIO29_BITN 13 -#define AUX_EVCTL_EVSTAT1_AUXIO29_M 0x00002000 -#define AUX_EVCTL_EVSTAT1_AUXIO29_S 13 - -// Field: [12] AUXIO28 -// -// AUXIO28 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT1_AUXIO28 0x00001000 -#define AUX_EVCTL_EVSTAT1_AUXIO28_BITN 12 -#define AUX_EVCTL_EVSTAT1_AUXIO28_M 0x00001000 -#define AUX_EVCTL_EVSTAT1_AUXIO28_S 12 - -// Field: [11] AUXIO27 -// -// AUXIO27 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT1_AUXIO27 0x00000800 -#define AUX_EVCTL_EVSTAT1_AUXIO27_BITN 11 -#define AUX_EVCTL_EVSTAT1_AUXIO27_M 0x00000800 -#define AUX_EVCTL_EVSTAT1_AUXIO27_S 11 - -// Field: [10] AUXIO26 -// -// AUXIO26 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT1_AUXIO26 0x00000400 -#define AUX_EVCTL_EVSTAT1_AUXIO26_BITN 10 -#define AUX_EVCTL_EVSTAT1_AUXIO26_M 0x00000400 -#define AUX_EVCTL_EVSTAT1_AUXIO26_S 10 - -// Field: [9] AUXIO25 -// -// AUXIO25 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT1_AUXIO25 0x00000200 -#define AUX_EVCTL_EVSTAT1_AUXIO25_BITN 9 -#define AUX_EVCTL_EVSTAT1_AUXIO25_M 0x00000200 -#define AUX_EVCTL_EVSTAT1_AUXIO25_S 9 - -// Field: [8] AUXIO24 -// -// AUXIO24 pin level, read value corresponds to AUX_AIODIO3:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT1_AUXIO24 0x00000100 -#define AUX_EVCTL_EVSTAT1_AUXIO24_BITN 8 -#define AUX_EVCTL_EVSTAT1_AUXIO24_M 0x00000100 -#define AUX_EVCTL_EVSTAT1_AUXIO24_S 8 - -// Field: [7] AUXIO23 -// -// AUXIO23 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 7. -#define AUX_EVCTL_EVSTAT1_AUXIO23 0x00000080 -#define AUX_EVCTL_EVSTAT1_AUXIO23_BITN 7 -#define AUX_EVCTL_EVSTAT1_AUXIO23_M 0x00000080 -#define AUX_EVCTL_EVSTAT1_AUXIO23_S 7 - -// Field: [6] AUXIO22 -// -// AUXIO22 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 6. -#define AUX_EVCTL_EVSTAT1_AUXIO22 0x00000040 -#define AUX_EVCTL_EVSTAT1_AUXIO22_BITN 6 -#define AUX_EVCTL_EVSTAT1_AUXIO22_M 0x00000040 -#define AUX_EVCTL_EVSTAT1_AUXIO22_S 6 - -// Field: [5] AUXIO21 -// -// AUXIO21 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 5. -#define AUX_EVCTL_EVSTAT1_AUXIO21 0x00000020 -#define AUX_EVCTL_EVSTAT1_AUXIO21_BITN 5 -#define AUX_EVCTL_EVSTAT1_AUXIO21_M 0x00000020 -#define AUX_EVCTL_EVSTAT1_AUXIO21_S 5 - -// Field: [4] AUXIO20 -// -// AUXIO20 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 4. -#define AUX_EVCTL_EVSTAT1_AUXIO20 0x00000010 -#define AUX_EVCTL_EVSTAT1_AUXIO20_BITN 4 -#define AUX_EVCTL_EVSTAT1_AUXIO20_M 0x00000010 -#define AUX_EVCTL_EVSTAT1_AUXIO20_S 4 - -// Field: [3] AUXIO19 -// -// AUXIO19 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 3. -#define AUX_EVCTL_EVSTAT1_AUXIO19 0x00000008 -#define AUX_EVCTL_EVSTAT1_AUXIO19_BITN 3 -#define AUX_EVCTL_EVSTAT1_AUXIO19_M 0x00000008 -#define AUX_EVCTL_EVSTAT1_AUXIO19_S 3 - -// Field: [2] AUXIO18 -// -// AUXIO18 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 2. -#define AUX_EVCTL_EVSTAT1_AUXIO18 0x00000004 -#define AUX_EVCTL_EVSTAT1_AUXIO18_BITN 2 -#define AUX_EVCTL_EVSTAT1_AUXIO18_M 0x00000004 -#define AUX_EVCTL_EVSTAT1_AUXIO18_S 2 - -// Field: [1] AUXIO17 -// -// AUXIO17 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 1. -#define AUX_EVCTL_EVSTAT1_AUXIO17 0x00000002 -#define AUX_EVCTL_EVSTAT1_AUXIO17_BITN 1 -#define AUX_EVCTL_EVSTAT1_AUXIO17_M 0x00000002 -#define AUX_EVCTL_EVSTAT1_AUXIO17_S 1 - -// Field: [0] AUXIO16 -// -// AUXIO16 pin level, read value corresponds to AUX_AIODIO2:GPIODIN bit 0. -#define AUX_EVCTL_EVSTAT1_AUXIO16 0x00000001 -#define AUX_EVCTL_EVSTAT1_AUXIO16_BITN 0 -#define AUX_EVCTL_EVSTAT1_AUXIO16_M 0x00000001 -#define AUX_EVCTL_EVSTAT1_AUXIO16_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT2 -// -//***************************************************************************** -// Field: [15] AUX_COMPB -// -// Comparator B output. -// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPB_SYNC_RATE sets the -// synchronization rate for this event. -#define AUX_EVCTL_EVSTAT2_AUX_COMPB 0x00008000 -#define AUX_EVCTL_EVSTAT2_AUX_COMPB_BITN 15 -#define AUX_EVCTL_EVSTAT2_AUX_COMPB_M 0x00008000 -#define AUX_EVCTL_EVSTAT2_AUX_COMPB_S 15 - -// Field: [14] AUX_COMPA -// -// Comparator A output. -// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_COMPA_SYNC_RATE sets the -// synchronization rate for this event. -#define AUX_EVCTL_EVSTAT2_AUX_COMPA 0x00004000 -#define AUX_EVCTL_EVSTAT2_AUX_COMPA_BITN 14 -#define AUX_EVCTL_EVSTAT2_AUX_COMPA_M 0x00004000 -#define AUX_EVCTL_EVSTAT2_AUX_COMPA_S 14 - -// Field: [13] MCU_OBSMUX1 -// -// Observation input 1 from IOC. -// This event is configured by IOC:OBSAUXOUTPUT.SEL1. -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1 0x00002000 -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_BITN 13 -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_M 0x00002000 -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX1_S 13 - -// Field: [12] MCU_OBSMUX0 -// -// Observation input 0 from IOC. -// This event is configured by IOC:OBSAUXOUTPUT.SEL0 and can be overridden by -// IOC:OBSAUXOUTPUT.SEL_MISC. -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0 0x00001000 -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_BITN 12 -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_M 0x00001000 -#define AUX_EVCTL_EVSTAT2_MCU_OBSMUX0_S 12 - -// Field: [11] MCU_EV -// -// Event from EVENT configured by EVENT:AUXSEL0. -#define AUX_EVCTL_EVSTAT2_MCU_EV 0x00000800 -#define AUX_EVCTL_EVSTAT2_MCU_EV_BITN 11 -#define AUX_EVCTL_EVSTAT2_MCU_EV_M 0x00000800 -#define AUX_EVCTL_EVSTAT2_MCU_EV_S 11 - -// Field: [10] ACLK_REF -// -// TDC reference clock. -// It is configured by DDI_0_OSC:CTL0.ACLK_REF_SRC_SEL and enabled by -// AUX_SYSIF:TDCREFCLKCTL.REQ. -#define AUX_EVCTL_EVSTAT2_ACLK_REF 0x00000400 -#define AUX_EVCTL_EVSTAT2_ACLK_REF_BITN 10 -#define AUX_EVCTL_EVSTAT2_ACLK_REF_M 0x00000400 -#define AUX_EVCTL_EVSTAT2_ACLK_REF_S 10 - -// Field: [9] VDDR_RECHARGE -// -// Event is high during VDDR recharge. -#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE 0x00000200 -#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_BITN 9 -#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_M 0x00000200 -#define AUX_EVCTL_EVSTAT2_VDDR_RECHARGE_S 9 - -// Field: [8] MCU_ACTIVE -// -// Event is high while system(MCU, AUX, or JTAG domains) is active or -// transitions to active (GLDO or DCDC power supply state). Event is not high -// during VDDR recharge. -#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE 0x00000100 -#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_BITN 8 -#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_M 0x00000100 -#define AUX_EVCTL_EVSTAT2_MCU_ACTIVE_S 8 - -// Field: [7] PWR_DWN -// -// Event is high while system(MCU, AUX, or JTAG domains) is in powerdown (uLDO -// power supply). -#define AUX_EVCTL_EVSTAT2_PWR_DWN 0x00000080 -#define AUX_EVCTL_EVSTAT2_PWR_DWN_BITN 7 -#define AUX_EVCTL_EVSTAT2_PWR_DWN_M 0x00000080 -#define AUX_EVCTL_EVSTAT2_PWR_DWN_S 7 - -// Field: [6] SCLK_LF -// -// SCLK_LF clock -#define AUX_EVCTL_EVSTAT2_SCLK_LF 0x00000040 -#define AUX_EVCTL_EVSTAT2_SCLK_LF_BITN 6 -#define AUX_EVCTL_EVSTAT2_SCLK_LF_M 0x00000040 -#define AUX_EVCTL_EVSTAT2_SCLK_LF_S 6 - -// Field: [5] AON_BATMON_TEMP_UPD -// -// Event is high for two SCLK_MF clock periods when there is an update of -// AON_BATMON:TEMP. -#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD 0x00000020 -#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_BITN 5 -#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_M 0x00000020 -#define AUX_EVCTL_EVSTAT2_AON_BATMON_TEMP_UPD_S 5 - -// Field: [4] AON_BATMON_BAT_UPD -// -// Event is high for two SCLK_MF clock periods when there is an update of -// AON_BATMON:BAT. -#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD 0x00000010 -#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_BITN 4 -#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_M 0x00000010 -#define AUX_EVCTL_EVSTAT2_AON_BATMON_BAT_UPD_S 4 - -// Field: [3] AON_RTC_4KHZ -// -// AON_RTC:SUBSEC.VALUE bit 19. -// AON_RTC:CTL.RTC_4KHZ_EN enables this event. -#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ 0x00000008 -#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_BITN 3 -#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_M 0x00000008 -#define AUX_EVCTL_EVSTAT2_AON_RTC_4KHZ_S 3 - -// Field: [2] AON_RTC_CH2_DLY -// -// AON_RTC:EVFLAGS.CH2 delayed by AON_RTC:CTL.EV_DELAY configuration. -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY 0x00000004 -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_BITN 2 -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_M 0x00000004 -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_DLY_S 2 - -// Field: [1] AON_RTC_CH2 -// -// AON_RTC:EVFLAGS.CH2. -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2 0x00000002 -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_BITN 1 -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_M 0x00000002 -#define AUX_EVCTL_EVSTAT2_AON_RTC_CH2_S 1 - -// Field: [0] MANUAL_EV -// -// Programmable event. See MANUAL for description. -#define AUX_EVCTL_EVSTAT2_MANUAL_EV 0x00000001 -#define AUX_EVCTL_EVSTAT2_MANUAL_EV_BITN 0 -#define AUX_EVCTL_EVSTAT2_MANUAL_EV_M 0x00000001 -#define AUX_EVCTL_EVSTAT2_MANUAL_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT3 -// -//***************************************************************************** -// Field: [15] AUX_TIMER2_CLKSWITCH_RDY -// -// AUX_SYSIF:TIMER2CLKSWITCH.RDY -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY 0x00008000 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_BITN 15 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_M 0x00008000 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_CLKSWITCH_RDY_S 15 - -// Field: [14] AUX_DAC_HOLD_ACTIVE -// -// AUX_ANAIF:DACSTAT.HOLD_ACTIVE -#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE 0x00004000 -#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_BITN 14 -#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_M 0x00004000 -#define AUX_EVCTL_EVSTAT3_AUX_DAC_HOLD_ACTIVE_S 14 - -// Field: [13] AUX_SMPH_AUTOTAKE_DONE -// -// See AUX_SMPH:AUTOTAKE.SMPH_ID for description. -#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE 0x00002000 -#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_BITN 13 -#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_M 0x00002000 -#define AUX_EVCTL_EVSTAT3_AUX_SMPH_AUTOTAKE_DONE_S 13 - -// Field: [12] AUX_ADC_FIFO_NOT_EMPTY -// -// AUX_ANAIF:ADCFIFOSTAT.EMPTY negated -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY 0x00001000 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_BITN 12 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_M 0x00001000 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_NOT_EMPTY_S 12 - -// Field: [11] AUX_ADC_FIFO_ALMOST_FULL -// -// AUX_ANAIF:ADCFIFOSTAT.ALMOST_FULL -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL 0x00000800 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_BITN 11 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000800 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_FIFO_ALMOST_FULL_S 11 - -// Field: [10] AUX_ADC_IRQ -// -// The logical function for this event is configurable. -// -// When DMACTL.EN = 1 : -// Event = UDMA0 Channel 7 done event OR -// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW -// -// When DMACTL.EN = 0 : -// Event = (NOT AUX_ANAIF:ADCFIFOSTAT.EMPTY) OR -// AUX_ANAIF:ADCFIFOSTAT.OVERFLOW OR AUX_ANAIF:ADCFIFOSTAT.UNDERFLOW -// -// Bit 7 in UDMA0:DONEMASK must be 0. -#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_IRQ_S 10 - -// Field: [9] AUX_ADC_DONE -// -// AUX_ANAIF ADC conversion done event. -// Event is synchronized at AUX bus rate. -#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE 0x00000200 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_BITN 9 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_M 0x00000200 -#define AUX_EVCTL_EVSTAT3_AUX_ADC_DONE_S 9 - -// Field: [8] AUX_ISRC_RESET_N -// -// AUX_ANAIF:ISRCCTL.RESET_N -#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N 0x00000100 -#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_BITN 8 -#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_M 0x00000100 -#define AUX_EVCTL_EVSTAT3_AUX_ISRC_RESET_N_S 8 - -// Field: [7] AUX_TDC_DONE -// -// AUX_TDC:STAT.DONE -#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE 0x00000080 -#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_BITN 7 -#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_M 0x00000080 -#define AUX_EVCTL_EVSTAT3_AUX_TDC_DONE_S 7 - -// Field: [6] AUX_TIMER0_EV -// -// AUX_TIMER0_EV event, see AUX_TIMER01:T0TARGET for description. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV 0x00000040 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_BITN 6 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_M 0x00000040 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER0_EV_S 6 - -// Field: [5] AUX_TIMER1_EV -// -// AUX_TIMER1_EV event, see AUX_TIMER01:T1TARGET for description. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER1_EV_S 5 - -// Field: [4] AUX_TIMER2_PULSE -// -// AUX_TIMER2 pulse event. -// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the -// synchronization rate for this event. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE 0x00000010 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_BITN 4 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_M 0x00000010 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_PULSE_S 4 - -// Field: [3] AUX_TIMER2_EV3 -// -// AUX_TIMER2 event output 3. -// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the -// synchronization rate for this event. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3 0x00000008 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_BITN 3 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_M 0x00000008 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV3_S 3 - -// Field: [2] AUX_TIMER2_EV2 -// -// AUX_TIMER2 event output 2. -// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the -// synchronization rate for this event. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2 0x00000004 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_BITN 2 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_M 0x00000004 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV2_S 2 - -// Field: [1] AUX_TIMER2_EV1 -// -// AUX_TIMER2 event output 1. -// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the -// synchronization rate for this event. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1 0x00000002 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_BITN 1 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_M 0x00000002 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV1_S 1 - -// Field: [0] AUX_TIMER2_EV0 -// -// AUX_TIMER2 event output 0. -// Configuration of AUX_SYSIF:EVSYNCRATE.AUX_TIMER2_SYNC_RATE sets the -// synchronization rate for this event. -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0 0x00000001 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_BITN 0 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_M 0x00000001 -#define AUX_EVCTL_EVSTAT3_AUX_TIMER2_EV0_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_SCEWEVCFG0 -// -//***************************************************************************** -// Field: [6] COMB_EV_EN -// -// Event combination control: -// -// 0: Disable event combination. -// 1: Enable event combination. -#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN 0x00000040 -#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_BITN 6 -#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_M 0x00000040 -#define AUX_EVCTL_SCEWEVCFG0_COMB_EV_EN_S 6 - -// Field: [5:0] EV0_SEL -// -// Select the event source from the synchronous event bus to be used in event -// equation. -// ENUMs: -// AUX_TIMER2_CLKSWITCH_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY -// AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE -// AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB EVSTAT2.AUX_COMPB -// AUX_COMPA EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0 -// MCU_EV EVSTAT2.MCU_EV -// ACLK_REF EVSTAT2.ACLK_REF -// VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE EVSTAT2.MCU_ACTIVE -// PWR_DWN EVSTAT2.PWR_DWN -// SCLK_LF EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 EVSTAT2.AON_RTC_CH2 -// AUX_PROG_DLY_IDLE Programmable delay event as described in PROGDLY -// AUXIO31 EVSTAT1.AUXIO31 -// AUXIO30 EVSTAT1.AUXIO30 -// AUXIO29 EVSTAT1.AUXIO29 -// AUXIO28 EVSTAT1.AUXIO28 -// AUXIO27 EVSTAT1.AUXIO27 -// AUXIO26 EVSTAT1.AUXIO26 -// AUXIO25 EVSTAT1.AUXIO25 -// AUXIO24 EVSTAT1.AUXIO24 -// AUXIO23 EVSTAT1.AUXIO23 -// AUXIO22 EVSTAT1.AUXIO22 -// AUXIO21 EVSTAT1.AUXIO21 -// AUXIO20 EVSTAT1.AUXIO20 -// AUXIO19 EVSTAT1.AUXIO19 -// AUXIO18 EVSTAT1.AUXIO18 -// AUXIO17 EVSTAT1.AUXIO17 -// AUXIO16 EVSTAT1.AUXIO16 -// AUXIO15 EVSTAT0.AUXIO15 -// AUXIO14 EVSTAT0.AUXIO14 -// AUXIO13 EVSTAT0.AUXIO13 -// AUXIO12 EVSTAT0.AUXIO12 -// AUXIO11 EVSTAT0.AUXIO11 -// AUXIO10 EVSTAT0.AUXIO10 -// AUXIO9 EVSTAT0.AUXIO9 -// AUXIO8 EVSTAT0.AUXIO8 -// AUXIO7 EVSTAT0.AUXIO7 -// AUXIO6 EVSTAT0.AUXIO6 -// AUXIO5 EVSTAT0.AUXIO5 -// AUXIO4 EVSTAT0.AUXIO4 -// AUXIO3 EVSTAT0.AUXIO3 -// AUXIO2 EVSTAT0.AUXIO2 -// AUXIO1 EVSTAT0.AUXIO1 -// AUXIO0 EVSTAT0.AUXIO0 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_W 6 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_M 0x0000003F -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_S 0 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_CLKSWITCH_RDY 0x0000003F -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_IRQ 0x0000003A -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ADC_DONE 0x00000039 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_ISRC_RESET_N 0x00000038 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TDC_DONE 0x00000037 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER0_EV 0x00000036 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER1_EV 0x00000035 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_PULSE 0x00000034 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV3 0x00000033 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV2 0x00000032 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV1 0x00000031 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_TIMER2_EV0 0x00000030 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_COMPB 0x0000002F -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_COMPA 0x0000002E -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_OBSMUX1 0x0000002D -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_OBSMUX0 0x0000002C -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_EV 0x0000002B -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_ACLK_REF 0x0000002A -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_VDDR_RECHARGE 0x00000029 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_MCU_ACTIVE 0x00000028 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_PWR_DWN 0x00000027 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_SCLK_LF 0x00000026 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_4KHZ 0x00000023 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_CH2_DLY 0x00000022 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AON_RTC_CH2 0x00000021 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUX_PROG_DLY_IDLE 0x00000020 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO31 0x0000001F -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO30 0x0000001E -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO29 0x0000001D -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO28 0x0000001C -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO27 0x0000001B -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO26 0x0000001A -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO25 0x00000019 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO24 0x00000018 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO23 0x00000017 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO22 0x00000016 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO21 0x00000015 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO20 0x00000014 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO19 0x00000013 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO18 0x00000012 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO17 0x00000011 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO16 0x00000010 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO15 0x0000000F -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO14 0x0000000E -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO13 0x0000000D -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO12 0x0000000C -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO11 0x0000000B -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO10 0x0000000A -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO9 0x00000009 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO8 0x00000008 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO7 0x00000007 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO6 0x00000006 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO5 0x00000005 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO4 0x00000004 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO3 0x00000003 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO2 0x00000002 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO1 0x00000001 -#define AUX_EVCTL_SCEWEVCFG0_EV0_SEL_AUXIO0 0x00000000 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_SCEWEVCFG1 -// -//***************************************************************************** -// Field: [7] EV0_POL -// -// Polarity of SCEWEVCFG0.EV0_SEL event. -// -// When SCEWEVCFG0.COMB_EV_EN is 0: -// -// 0: Non-inverted. -// 1: Non-inverted. -// -// When SCEWEVCFG0.COMB_EV_EN is 1. -// -// 0: Non-inverted. -// 1: Inverted. -#define AUX_EVCTL_SCEWEVCFG1_EV0_POL 0x00000080 -#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_BITN 7 -#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_M 0x00000080 -#define AUX_EVCTL_SCEWEVCFG1_EV0_POL_S 7 - -// Field: [6] EV1_POL -// -// Polarity of EV1_SEL event. -// -// When SCEWEVCFG0.COMB_EV_EN is 0: -// -// 0: Non-inverted. -// 1: Non-inverted. -// -// When SCEWEVCFG0.COMB_EV_EN is 1. -// -// 0: Non-inverted. -// 1: Inverted. -#define AUX_EVCTL_SCEWEVCFG1_EV1_POL 0x00000040 -#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_BITN 6 -#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_M 0x00000040 -#define AUX_EVCTL_SCEWEVCFG1_EV1_POL_S 6 - -// Field: [5:0] EV1_SEL -// -// Select the event source from the synchronous event bus to be used in event -// equation. -// ENUMs: -// AUX_TIMER2_CLKSWITCH_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY -// AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE -// AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB EVSTAT2.AUX_COMPB -// AUX_COMPA EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0 -// MCU_EV EVSTAT2.MCU_EV -// ACLK_REF EVSTAT2.ACLK_REF -// VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE EVSTAT2.MCU_ACTIVE -// PWR_DWN EVSTAT2.PWR_DWN -// SCLK_LF EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 EVSTAT2.AON_RTC_CH2 -// AUX_PROG_DLY_IDLE Programmable delay event as described in PROGDLY -// AUXIO31 EVSTAT1.AUXIO31 -// AUXIO30 EVSTAT1.AUXIO30 -// AUXIO29 EVSTAT1.AUXIO29 -// AUXIO28 EVSTAT1.AUXIO28 -// AUXIO27 EVSTAT1.AUXIO27 -// AUXIO26 EVSTAT1.AUXIO26 -// AUXIO25 EVSTAT1.AUXIO25 -// AUXIO24 EVSTAT1.AUXIO24 -// AUXIO23 EVSTAT1.AUXIO23 -// AUXIO22 EVSTAT1.AUXIO22 -// AUXIO21 EVSTAT1.AUXIO21 -// AUXIO20 EVSTAT1.AUXIO20 -// AUXIO19 EVSTAT1.AUXIO19 -// AUXIO18 EVSTAT1.AUXIO18 -// AUXIO17 EVSTAT1.AUXIO17 -// AUXIO16 EVSTAT1.AUXIO16 -// AUXIO15 EVSTAT0.AUXIO15 -// AUXIO14 EVSTAT0.AUXIO14 -// AUXIO13 EVSTAT0.AUXIO13 -// AUXIO12 EVSTAT0.AUXIO12 -// AUXIO11 EVSTAT0.AUXIO11 -// AUXIO10 EVSTAT0.AUXIO10 -// AUXIO9 EVSTAT0.AUXIO9 -// AUXIO8 EVSTAT0.AUXIO8 -// AUXIO7 EVSTAT0.AUXIO7 -// AUXIO6 EVSTAT0.AUXIO6 -// AUXIO5 EVSTAT0.AUXIO5 -// AUXIO4 EVSTAT0.AUXIO4 -// AUXIO3 EVSTAT0.AUXIO3 -// AUXIO2 EVSTAT0.AUXIO2 -// AUXIO1 EVSTAT0.AUXIO1 -// AUXIO0 EVSTAT0.AUXIO0 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_W 6 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_M 0x0000003F -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_S 0 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_CLKSWITCH_RDY 0x0000003F -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_IRQ 0x0000003A -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ADC_DONE 0x00000039 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_ISRC_RESET_N 0x00000038 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TDC_DONE 0x00000037 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER0_EV 0x00000036 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER1_EV 0x00000035 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_PULSE 0x00000034 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV3 0x00000033 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV2 0x00000032 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV1 0x00000031 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_TIMER2_EV0 0x00000030 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_COMPB 0x0000002F -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_COMPA 0x0000002E -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_OBSMUX1 0x0000002D -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_OBSMUX0 0x0000002C -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_EV 0x0000002B -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_ACLK_REF 0x0000002A -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_VDDR_RECHARGE 0x00000029 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_MCU_ACTIVE 0x00000028 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_PWR_DWN 0x00000027 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_SCLK_LF 0x00000026 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_4KHZ 0x00000023 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_CH2_DLY 0x00000022 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AON_RTC_CH2 0x00000021 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUX_PROG_DLY_IDLE 0x00000020 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO31 0x0000001F -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO30 0x0000001E -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO29 0x0000001D -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO28 0x0000001C -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO27 0x0000001B -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO26 0x0000001A -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO25 0x00000019 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO24 0x00000018 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO23 0x00000017 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO22 0x00000016 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO21 0x00000015 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO20 0x00000014 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO19 0x00000013 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO18 0x00000012 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO17 0x00000011 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO16 0x00000010 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO15 0x0000000F -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO14 0x0000000E -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO13 0x0000000D -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO12 0x0000000C -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO11 0x0000000B -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO10 0x0000000A -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO9 0x00000009 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO8 0x00000008 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO7 0x00000007 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO6 0x00000006 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO5 0x00000005 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO4 0x00000004 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO3 0x00000003 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO2 0x00000002 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO1 0x00000001 -#define AUX_EVCTL_SCEWEVCFG1_EV1_SEL_AUXIO0 0x00000000 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_DMACTL -// -//***************************************************************************** -// Field: [2] REQ_MODE -// -// UDMA0 Request mode -// ENUMs: -// SINGLE Single requests are generated on UDMA0 channel 7 -// when the condition configured in SEL is met. -// BURST Burst requests are generated on UDMA0 channel 7 -// when the condition configured in SEL is met. -#define AUX_EVCTL_DMACTL_REQ_MODE 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_BITN 2 -#define AUX_EVCTL_DMACTL_REQ_MODE_M 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_S 2 -#define AUX_EVCTL_DMACTL_REQ_MODE_SINGLE 0x00000004 -#define AUX_EVCTL_DMACTL_REQ_MODE_BURST 0x00000000 - -// Field: [1] EN -// -// uDMA ADC interface enable. -// -// 0: Disable UDMA0 interface to ADC. -// 1: Enable UDMA0 interface to ADC. -#define AUX_EVCTL_DMACTL_EN 0x00000002 -#define AUX_EVCTL_DMACTL_EN_BITN 1 -#define AUX_EVCTL_DMACTL_EN_M 0x00000002 -#define AUX_EVCTL_DMACTL_EN_S 1 - -// Field: [0] SEL -// -// Select FIFO watermark level required to trigger a UDMA0 transfer of ADC FIFO -// data. -// ENUMs: -// AUX_ADC_FIFO_ALMOST_FULL UDMA0 trigger event will be generated when the ADC -// FIFO is almost full (3/4 full). -// AUX_ADC_FIFO_NOT_EMPTY UDMA0 trigger event will be generated when there -// are samples in the ADC FIFO. -#define AUX_EVCTL_DMACTL_SEL 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_BITN 0 -#define AUX_EVCTL_DMACTL_SEL_M 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_S 0 -#define AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x00000001 -#define AUX_EVCTL_DMACTL_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x00000000 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_SWEVSET -// -//***************************************************************************** -// Field: [2] SWEV2 -// -// Software event flag 2. -// -// 0: No effect. -// 1: Set software event flag 2. -#define AUX_EVCTL_SWEVSET_SWEV2 0x00000004 -#define AUX_EVCTL_SWEVSET_SWEV2_BITN 2 -#define AUX_EVCTL_SWEVSET_SWEV2_M 0x00000004 -#define AUX_EVCTL_SWEVSET_SWEV2_S 2 - -// Field: [1] SWEV1 -// -// Software event flag 1. -// -// 0: No effect. -// 1: Set software event flag 1. -#define AUX_EVCTL_SWEVSET_SWEV1 0x00000002 -#define AUX_EVCTL_SWEVSET_SWEV1_BITN 1 -#define AUX_EVCTL_SWEVSET_SWEV1_M 0x00000002 -#define AUX_EVCTL_SWEVSET_SWEV1_S 1 - -// Field: [0] SWEV0 -// -// Software event flag 0. -// -// 0: No effect. -// 1: Set software event flag 0. -#define AUX_EVCTL_SWEVSET_SWEV0 0x00000001 -#define AUX_EVCTL_SWEVSET_SWEV0_BITN 0 -#define AUX_EVCTL_SWEVSET_SWEV0_M 0x00000001 -#define AUX_EVCTL_SWEVSET_SWEV0_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVTOAONFLAGS -// -//***************************************************************************** -// Field: [8] AUX_TIMER1_EV -// -// This event flag is set when level selected by EVTOAONPOL.AUX_TIMER1_EV -// occurs on EVSTAT3.AUX_TIMER1_EV. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER1_EV_S 8 - -// Field: [7] AUX_TIMER0_EV -// -// This event flag is set when level selected by EVTOAONPOL.AUX_TIMER0_EV -// occurs on EVSTAT3.AUX_TIMER0_EV. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TIMER0_EV_S 7 - -// Field: [6] AUX_TDC_DONE -// -// This event flag is set when level selected by EVTOAONPOL.AUX_TDC_DONE occurs -// on EVSTAT3.AUX_TDC_DONE. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_TDC_DONE_S 6 - -// Field: [5] AUX_ADC_DONE -// -// This event flag is set when level selected by EVTOAONPOL.AUX_ADC_DONE occurs -// on EVSTAT3.AUX_ADC_DONE. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_ADC_DONE_S 5 - -// Field: [4] AUX_COMPB -// -// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPB occurs on -// EVSTAT2.AUX_COMPB. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPB_S 4 - -// Field: [3] AUX_COMPA -// -// This event flag is set when edge selected by EVTOAONPOL.AUX_COMPA occurs on -// EVSTAT2.AUX_COMPA. -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGS_AUX_COMPA_S 3 - -// Field: [2] SWEV2 -// -// This event flag is set when software writes a 1 to SWEVSET.SWEV2. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_BITN 2 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_M 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV2_S 2 - -// Field: [1] SWEV1 -// -// This event flag is set when software writes a 1 to SWEVSET.SWEV1. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_BITN 1 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_M 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV1_S 1 - -// Field: [0] SWEV0 -// -// This event flag is set when software writes a 1 to SWEVSET.SWEV0. -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_BITN 0 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_M 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGS_SWEV0_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVTOAONPOL -// -//***************************************************************************** -// Field: [8] AUX_TIMER1_EV -// -// Select the level of EVSTAT3.AUX_TIMER1_EV that sets -// EVTOAONFLAGS.AUX_TIMER1_EV. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_S 8 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_LOW 0x00000100 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER1_EV_HIGH 0x00000000 - -// Field: [7] AUX_TIMER0_EV -// -// Select the level of EVSTAT3.AUX_TIMER0_EV that sets -// EVTOAONFLAGS.AUX_TIMER0_EV. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_S 7 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_LOW 0x00000080 -#define AUX_EVCTL_EVTOAONPOL_AUX_TIMER0_EV_HIGH 0x00000000 - -// Field: [6] AUX_TDC_DONE -// -// Select level of EVSTAT3.AUX_TDC_DONE that sets EVTOAONFLAGS.AUX_TDC_DONE. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_S 6 -#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_LOW 0x00000040 -#define AUX_EVCTL_EVTOAONPOL_AUX_TDC_DONE_HIGH 0x00000000 - -// Field: [5] AUX_ADC_DONE -// -// Select the level of EVSTAT3.AUX_ADC_DONE that sets -// EVTOAONFLAGS.AUX_ADC_DONE. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_S 5 -#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_LOW 0x00000020 -#define AUX_EVCTL_EVTOAONPOL_AUX_ADC_DONE_HIGH 0x00000000 - -// Field: [4] AUX_COMPB -// -// Select the edge of EVSTAT2.AUX_COMPB that sets EVTOAONFLAGS.AUX_COMPB. -// ENUMs: -// FALL Falling edge -// RISE Rising edge -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_S 4 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_FALL 0x00000010 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPB_RISE 0x00000000 - -// Field: [3] AUX_COMPA -// -// Select the edge of EVSTAT2.AUX_COMPA that sets EVTOAONFLAGS.AUX_COMPA. -// ENUMs: -// FALL Falling edge -// RISE Rising edge -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_S 3 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_FALL 0x00000008 -#define AUX_EVCTL_EVTOAONPOL_AUX_COMPA_RISE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVTOAONFLAGSCLR -// -//***************************************************************************** -// Field: [8] AUX_TIMER1_EV -// -// Write 1 to clear EVTOAONFLAGS.AUX_TIMER1_EV. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_BITN 8 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_M 0x00000100 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER1_EV_S 8 - -// Field: [7] AUX_TIMER0_EV -// -// Write 1 to clear EVTOAONFLAGS.AUX_TIMER0_EV. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_BITN 7 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_M 0x00000080 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TIMER0_EV_S 7 - -// Field: [6] AUX_TDC_DONE -// -// Write 1 to clear EVTOAONFLAGS.AUX_TDC_DONE. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_BITN 6 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_TDC_DONE_S 6 - -// Field: [5] AUX_ADC_DONE -// -// Write 1 to clear EVTOAONFLAGS.AUX_ADC_DONE. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_BITN 5 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_M 0x00000020 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_ADC_DONE_S 5 - -// Field: [4] AUX_COMPB -// -// Write 1 to clear EVTOAONFLAGS.AUX_COMPB. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_BITN 4 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_M 0x00000010 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPB_S 4 - -// Field: [3] AUX_COMPA -// -// Write 1 to clear EVTOAONFLAGS.AUX_COMPA. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_BITN 3 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_M 0x00000008 -#define AUX_EVCTL_EVTOAONFLAGSCLR_AUX_COMPA_S 3 - -// Field: [2] SWEV2 -// -// Write 1 to clear EVTOAONFLAGS.SWEV2. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_BITN 2 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_M 0x00000004 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV2_S 2 - -// Field: [1] SWEV1 -// -// Write 1 to clear EVTOAONFLAGS.SWEV1. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_BITN 1 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_M 0x00000002 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV1_S 1 - -// Field: [0] SWEV0 -// -// Write 1 to clear EVTOAONFLAGS.SWEV0. -// -// Read value is 0. -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_BITN 0 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_M 0x00000001 -#define AUX_EVCTL_EVTOAONFLAGSCLR_SWEV0_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVTOMCUFLAGS -// -//***************************************************************************** -// Field: [15] AUX_TIMER2_PULSE -// -// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_PULSE -// occurs on EVSTAT3.AUX_TIMER2_PULSE. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE 0x00008000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_BITN 15 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_M 0x00008000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_PULSE_S 15 - -// Field: [14] AUX_TIMER2_EV3 -// -// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV3 -// occurs on EVSTAT3.AUX_TIMER2_EV3. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3 0x00004000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_BITN 14 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_M 0x00004000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV3_S 14 - -// Field: [13] AUX_TIMER2_EV2 -// -// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV2 -// occurs on EVSTAT3.AUX_TIMER2_EV2. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2 0x00002000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_BITN 13 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_M 0x00002000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV2_S 13 - -// Field: [12] AUX_TIMER2_EV1 -// -// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV1 -// occurs on EVSTAT3.AUX_TIMER2_EV1. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1 0x00001000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_BITN 12 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_M 0x00001000 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV1_S 12 - -// Field: [11] AUX_TIMER2_EV0 -// -// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER2_EV0 -// occurs on EVSTAT3.AUX_TIMER2_EV0. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0 0x00000800 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_BITN 11 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_M 0x00000800 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER2_EV0_S 11 - -// Field: [10] AUX_ADC_IRQ -// -// This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_IRQ occurs -// on EVSTAT3.AUX_ADC_IRQ. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_IRQ_S 10 - -// Field: [9] MCU_OBSMUX0 -// -// This event flag is set when level selected by EVTOMCUPOL.MCU_OBSMUX0 occurs -// on EVSTAT2.MCU_OBSMUX0. -#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGS_MCU_OBSMUX0_S 9 - -// Field: [8] AUX_ADC_FIFO_ALMOST_FULL -// -// This event flag is set when level selected by -// EVTOMCUPOL.AUX_ADC_FIFO_ALMOST_FULL occurs on -// EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_FIFO_ALMOST_FULL_S 8 - -// Field: [7] AUX_ADC_DONE -// -// This event flag is set when level selected by EVTOMCUPOL.AUX_ADC_DONE occurs -// on EVSTAT3.AUX_ADC_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_ADC_DONE_S 7 - -// Field: [6] AUX_SMPH_AUTOTAKE_DONE -// -// This event flag is set when level selected by -// EVTOMCUPOL.AUX_SMPH_AUTOTAKE_DONE occurs on EVSTAT3.AUX_SMPH_AUTOTAKE_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_SMPH_AUTOTAKE_DONE_S 6 - -// Field: [5] AUX_TIMER1_EV -// -// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER1_EV -// occurs on EVSTAT3.AUX_TIMER1_EV. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER1_EV_S 5 - -// Field: [4] AUX_TIMER0_EV -// -// This event flag is set when level selected by EVTOMCUPOL.AUX_TIMER0_EV -// occurs on EVSTAT3.AUX_TIMER0_EV. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TIMER0_EV_S 4 - -// Field: [3] AUX_TDC_DONE -// -// This event flag is set when level selected by EVTOMCUPOL.AUX_TDC_DONE occurs -// on EVSTAT3.AUX_TDC_DONE. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_TDC_DONE_S 3 - -// Field: [2] AUX_COMPB -// -// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPB occurs on -// EVSTAT2.AUX_COMPB. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPB_S 2 - -// Field: [1] AUX_COMPA -// -// This event flag is set when edge selected by EVTOMCUPOL.AUX_COMPA occurs on -// EVSTAT2.AUX_COMPA. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_COMPA_S 1 - -// Field: [0] AUX_WU_EV -// -// This event flag is set when level selected by EVTOMCUPOL.AUX_WU_EV occurs on -// reduction-OR of the AUX_SYSIF:WUFLAGS register. -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGS_AUX_WU_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVTOMCUPOL -// -//***************************************************************************** -// Field: [15] AUX_TIMER2_PULSE -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_PULSE. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE 0x00008000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_BITN 15 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_M 0x00008000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_S 15 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_LOW 0x00008000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_PULSE_HIGH 0x00000000 - -// Field: [14] AUX_TIMER2_EV3 -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV3. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3 0x00004000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_BITN 14 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_M 0x00004000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_S 14 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_LOW 0x00004000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV3_HIGH 0x00000000 - -// Field: [13] AUX_TIMER2_EV2 -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV2. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2 0x00002000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_BITN 13 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_M 0x00002000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_S 13 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_LOW 0x00002000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV2_HIGH 0x00000000 - -// Field: [12] AUX_TIMER2_EV1 -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV1. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1 0x00001000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_BITN 12 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_M 0x00001000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_S 12 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_LOW 0x00001000 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV1_HIGH 0x00000000 - -// Field: [11] AUX_TIMER2_EV0 -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER2_EV0. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0 0x00000800 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_BITN 11 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_M 0x00000800 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_S 11 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_LOW 0x00000800 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER2_EV0_HIGH 0x00000000 - -// Field: [10] AUX_ADC_IRQ -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_IRQ. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_S 10 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_LOW 0x00000400 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_IRQ_HIGH 0x00000000 - -// Field: [9] MCU_OBSMUX0 -// -// Select the event source level that sets EVTOMCUFLAGS.MCU_OBSMUX0. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_S 9 -#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_LOW 0x00000200 -#define AUX_EVCTL_EVTOMCUPOL_MCU_OBSMUX0_HIGH 0x00000000 - -// Field: [8] AUX_ADC_FIFO_ALMOST_FULL -// -// Select the event source level that sets -// EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_S 8 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_LOW 0x00000100 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_FIFO_ALMOST_FULL_HIGH 0x00000000 - -// Field: [7] AUX_ADC_DONE -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_ADC_DONE. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_S 7 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_LOW 0x00000080 -#define AUX_EVCTL_EVTOMCUPOL_AUX_ADC_DONE_HIGH 0x00000000 - -// Field: [6] AUX_SMPH_AUTOTAKE_DONE -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_S 6 -#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_LOW 0x00000040 -#define AUX_EVCTL_EVTOMCUPOL_AUX_SMPH_AUTOTAKE_DONE_HIGH 0x00000000 - -// Field: [5] AUX_TIMER1_EV -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER1_EV. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_S 5 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_LOW 0x00000020 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER1_EV_HIGH 0x00000000 - -// Field: [4] AUX_TIMER0_EV -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_TIMER0_EV. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_S 4 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_LOW 0x00000010 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TIMER0_EV_HIGH 0x00000000 - -// Field: [3] AUX_TDC_DONE -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_TDC_DONE. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_S 3 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_LOW 0x00000008 -#define AUX_EVCTL_EVTOMCUPOL_AUX_TDC_DONE_HIGH 0x00000000 - -// Field: [2] AUX_COMPB -// -// Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPB. -// ENUMs: -// FALL Falling edge -// RISE Rising edge -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_S 2 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_FALL 0x00000004 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPB_RISE 0x00000000 - -// Field: [1] AUX_COMPA -// -// Select the event source edge that sets EVTOMCUFLAGS.AUX_COMPA. -// ENUMs: -// FALL Falling edge -// RISE Rising edge -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_S 1 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_FALL 0x00000002 -#define AUX_EVCTL_EVTOMCUPOL_AUX_COMPA_RISE 0x00000000 - -// Field: [0] AUX_WU_EV -// -// Select the event source level that sets EVTOMCUFLAGS.AUX_WU_EV. -// ENUMs: -// LOW Low level -// HIGH High level -#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_S 0 -#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_LOW 0x00000001 -#define AUX_EVCTL_EVTOMCUPOL_AUX_WU_EV_HIGH 0x00000000 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVTOMCUFLAGSCLR -// -//***************************************************************************** -// Field: [15] AUX_TIMER2_PULSE -// -// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_PULSE. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE 0x00008000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_BITN 15 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_M 0x00008000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_PULSE_S 15 - -// Field: [14] AUX_TIMER2_EV3 -// -// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV3. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3 0x00004000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_BITN 14 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_M 0x00004000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV3_S 14 - -// Field: [13] AUX_TIMER2_EV2 -// -// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV2. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2 0x00002000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_BITN 13 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_M 0x00002000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV2_S 13 - -// Field: [12] AUX_TIMER2_EV1 -// -// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV1. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1 0x00001000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_BITN 12 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_M 0x00001000 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV1_S 12 - -// Field: [11] AUX_TIMER2_EV0 -// -// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER2_EV0. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0 0x00000800 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_BITN 11 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_M 0x00000800 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER2_EV0_S 11 - -// Field: [10] AUX_ADC_IRQ -// -// Write 1 to clear EVTOMCUFLAGS.AUX_ADC_IRQ. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_BITN 10 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_IRQ_S 10 - -// Field: [9] MCU_OBSMUX0 -// -// Write 1 to clear EVTOMCUFLAGS.MCU_OBSMUX0. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_BITN 9 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_MCU_OBSMUX0_S 9 - -// Field: [8] AUX_ADC_FIFO_ALMOST_FULL -// -// Write 1 to clear EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_FIFO_ALMOST_FULL_S 8 - -// Field: [7] AUX_ADC_DONE -// -// Write 1 to clear EVTOMCUFLAGS.AUX_ADC_DONE. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_BITN 7 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_ADC_DONE_S 7 - -// Field: [6] AUX_SMPH_AUTOTAKE_DONE -// -// Write 1 to clear EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_SMPH_AUTOTAKE_DONE_S 6 - -// Field: [5] AUX_TIMER1_EV -// -// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER1_EV. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_BITN 5 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER1_EV_S 5 - -// Field: [4] AUX_TIMER0_EV -// -// Write 1 to clear EVTOMCUFLAGS.AUX_TIMER0_EV. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_BITN 4 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TIMER0_EV_S 4 - -// Field: [3] AUX_TDC_DONE -// -// Write 1 to clear EVTOMCUFLAGS.AUX_TDC_DONE. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_BITN 3 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_TDC_DONE_S 3 - -// Field: [2] AUX_COMPB -// -// Write 1 to clear EVTOMCUFLAGS.AUX_COMPB. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_BITN 2 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPB_S 2 - -// Field: [1] AUX_COMPA -// -// Write 1 to clear EVTOMCUFLAGS.AUX_COMPA. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_BITN 1 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_COMPA_S 1 - -// Field: [0] AUX_WU_EV -// -// Write 1 to clear EVTOMCUFLAGS.AUX_WU_EV. -// -// Read value is 0. -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_BITN 0 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_M 0x00000001 -#define AUX_EVCTL_EVTOMCUFLAGSCLR_AUX_WU_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_COMBEVTOMCUMASK -// -//***************************************************************************** -// Field: [15] AUX_TIMER2_PULSE -// -// EVTOMCUFLAGS.AUX_TIMER2_PULSE contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE 0x00008000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_BITN 15 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_M 0x00008000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_PULSE_S 15 - -// Field: [14] AUX_TIMER2_EV3 -// -// EVTOMCUFLAGS.AUX_TIMER2_EV3 contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3 0x00004000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_BITN 14 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_M 0x00004000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV3_S 14 - -// Field: [13] AUX_TIMER2_EV2 -// -// EVTOMCUFLAGS.AUX_TIMER2_EV2 contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2 0x00002000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_BITN 13 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_M 0x00002000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV2_S 13 - -// Field: [12] AUX_TIMER2_EV1 -// -// EVTOMCUFLAGS.AUX_TIMER2_EV1 contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1 0x00001000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_BITN 12 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_M 0x00001000 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV1_S 12 - -// Field: [11] AUX_TIMER2_EV0 -// -// EVTOMCUFLAGS.AUX_TIMER2_EV0 contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0 0x00000800 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_BITN 11 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_M 0x00000800 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER2_EV0_S 11 - -// Field: [10] AUX_ADC_IRQ -// -// EVTOMCUFLAGS.AUX_ADC_IRQ contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ 0x00000400 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_BITN 10 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_M 0x00000400 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_IRQ_S 10 - -// Field: [9] MCU_OBSMUX0 -// -// EVTOMCUFLAGS.MCU_OBSMUX0 contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0 0x00000200 -#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_BITN 9 -#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_M 0x00000200 -#define AUX_EVCTL_COMBEVTOMCUMASK_MCU_OBSMUX0_S 9 - -// Field: [8] AUX_ADC_FIFO_ALMOST_FULL -// -// EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL 0x00000100 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_BITN 8 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_M 0x00000100 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_FIFO_ALMOST_FULL_S 8 - -// Field: [7] AUX_ADC_DONE -// -// EVTOMCUFLAGS.AUX_ADC_DONE contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE 0x00000080 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_BITN 7 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_M 0x00000080 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_ADC_DONE_S 7 - -// Field: [6] AUX_SMPH_AUTOTAKE_DONE -// -// EVTOMCUFLAGS.AUX_SMPH_AUTOTAKE_DONE contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE 0x00000040 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_BITN 6 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_M 0x00000040 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_SMPH_AUTOTAKE_DONE_S 6 - -// Field: [5] AUX_TIMER1_EV -// -// EVTOMCUFLAGS.AUX_TIMER1_EV contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV 0x00000020 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_BITN 5 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_M 0x00000020 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER1_EV_S 5 - -// Field: [4] AUX_TIMER0_EV -// -// EVTOMCUFLAGS.AUX_TIMER0_EV contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV 0x00000010 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_BITN 4 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_M 0x00000010 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TIMER0_EV_S 4 - -// Field: [3] AUX_TDC_DONE -// -// EVTOMCUFLAGS.AUX_TDC_DONE contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE 0x00000008 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_BITN 3 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_M 0x00000008 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_TDC_DONE_S 3 - -// Field: [2] AUX_COMPB -// -// EVTOMCUFLAGS.AUX_COMPB contribution to the AUX_COMB event. -// -// 0: Exclude -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB 0x00000004 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_BITN 2 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_M 0x00000004 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPB_S 2 - -// Field: [1] AUX_COMPA -// -// EVTOMCUFLAGS.AUX_COMPA contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA 0x00000002 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_BITN 1 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_M 0x00000002 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_COMPA_S 1 - -// Field: [0] AUX_WU_EV -// -// EVTOMCUFLAGS.AUX_WU_EV contribution to the AUX_COMB event. -// -// 0: Exclude. -// 1: Include. -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV 0x00000001 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_BITN 0 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_M 0x00000001 -#define AUX_EVCTL_COMBEVTOMCUMASK_AUX_WU_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVOBSCFG -// -//***************************************************************************** -// Field: [5:0] EVOBS_SEL -// -// Select which event from the asynchronous event bus that represents -// AUX_EV_OBS in AUX_AIODIOn. -// ENUMs: -// AUX_TIMER2_CLKSW_RDY EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY -// AUX_DAC_HOLD_ACTIVE EVSTAT3.AUX_DAC_HOLD_ACTIVE -// AUX_SMPH_AUTOTAKE_DONE EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_PULSE EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB EVSTAT2.AUX_COMPB -// AUX_COMPA EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 EVSTAT2.MCU_OBSMUX0 -// MCU_EV EVSTAT2.MCU_EV -// ACLK_REF EVSTAT2.ACLK_REF -// VDDR_RECHARGE EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE EVSTAT2.MCU_ACTIVE -// PWR_DWN EVSTAT2.PWR_DWN -// SCLK_LF EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 EVSTAT2.AON_RTC_CH2 -// MANUAL_EV EVSTAT2.MANUAL_EV -// AUXIO31 EVSTAT1.AUXIO31 -// AUXIO30 EVSTAT1.AUXIO30 -// AUXIO29 EVSTAT1.AUXIO29 -// AUXIO28 EVSTAT1.AUXIO28 -// AUXIO27 EVSTAT1.AUXIO27 -// AUXIO26 EVSTAT1.AUXIO26 -// AUXIO25 EVSTAT1.AUXIO25 -// AUXIO24 EVSTAT1.AUXIO24 -// AUXIO23 EVSTAT1.AUXIO23 -// AUXIO22 EVSTAT1.AUXIO22 -// AUXIO21 EVSTAT1.AUXIO21 -// AUXIO20 EVSTAT1.AUXIO20 -// AUXIO19 EVSTAT1.AUXIO19 -// AUXIO18 EVSTAT1.AUXIO18 -// AUXIO17 EVSTAT1.AUXIO17 -// AUXIO16 EVSTAT1.AUXIO16 -// AUXIO15 EVSTAT0.AUXIO15 -// AUXIO14 EVSTAT0.AUXIO14 -// AUXIO13 EVSTAT0.AUXIO13 -// AUXIO12 EVSTAT0.AUXIO12 -// AUXIO11 EVSTAT0.AUXIO11 -// AUXIO10 EVSTAT0.AUXIO10 -// AUXIO9 EVSTAT0.AUXIO9 -// AUXIO8 EVSTAT0.AUXIO8 -// AUXIO7 EVSTAT0.AUXIO7 -// AUXIO6 EVSTAT0.AUXIO6 -// AUXIO5 EVSTAT0.AUXIO5 -// AUXIO4 EVSTAT0.AUXIO4 -// AUXIO3 EVSTAT0.AUXIO3 -// AUXIO2 EVSTAT0.AUXIO2 -// AUXIO1 EVSTAT0.AUXIO1 -// AUXIO0 EVSTAT0.AUXIO0 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_W 6 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_M 0x0000003F -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_S 0 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_CLKSW_RDY 0x0000003F -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_DAC_HOLD_ACTIVE 0x0000003E -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_IRQ 0x0000003A -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ADC_DONE 0x00000039 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_ISRC_RESET_N 0x00000038 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TDC_DONE 0x00000037 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER0_EV 0x00000036 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER1_EV 0x00000035 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_PULSE 0x00000034 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV3 0x00000033 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV2 0x00000032 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV1 0x00000031 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_TIMER2_EV0 0x00000030 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_COMPB 0x0000002F -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUX_COMPA 0x0000002E -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_OBSMUX1 0x0000002D -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_OBSMUX0 0x0000002C -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_EV 0x0000002B -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_ACLK_REF 0x0000002A -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_VDDR_RECHARGE 0x00000029 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MCU_ACTIVE 0x00000028 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_PWR_DWN 0x00000027 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_SCLK_LF 0x00000026 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_4KHZ 0x00000023 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_CH2_DLY 0x00000022 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AON_RTC_CH2 0x00000021 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_MANUAL_EV 0x00000020 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO31 0x0000001F -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO30 0x0000001E -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO29 0x0000001D -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO28 0x0000001C -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO27 0x0000001B -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO26 0x0000001A -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO25 0x00000019 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO24 0x00000018 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO23 0x00000017 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO22 0x00000016 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO21 0x00000015 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO20 0x00000014 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO19 0x00000013 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO18 0x00000012 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO17 0x00000011 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO16 0x00000010 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO15 0x0000000F -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO14 0x0000000E -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO13 0x0000000D -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO12 0x0000000C -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO11 0x0000000B -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO10 0x0000000A -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO9 0x00000009 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO8 0x00000008 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO7 0x00000007 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO6 0x00000006 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO5 0x00000005 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO4 0x00000004 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO3 0x00000003 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO2 0x00000002 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO1 0x00000001 -#define AUX_EVCTL_EVOBSCFG_EVOBS_SEL_AUXIO0 0x00000000 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_PROGDLY -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// VALUE decrements to 0 at a rate of 1 MHz. -// -// The event AUX_PROG_DLY_IDLE is high when VALUE is 0, otherwise it is low. -// -// Only use the programmable delay counter and the AUX_PROG_DLY_IDLE event when -// AUX_SYSIF:OPMODEACK.ACK equals A or LP. -// -// Decrementation of VALUE halts when either is true: -// - AUX_SCE:CTL.DBG_FREEZE_EN is set and system CPU is halted in debug mode. -// - AUX_SYSIF:TIMERHALT.PROGDLY is set. -#define AUX_EVCTL_PROGDLY_VALUE_W 16 -#define AUX_EVCTL_PROGDLY_VALUE_M 0x0000FFFF -#define AUX_EVCTL_PROGDLY_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_MANUAL -// -//***************************************************************************** -// Field: [0] EV -// -// This bit field sets the value of EVSTAT2.MANUAL_EV. -#define AUX_EVCTL_MANUAL_EV 0x00000001 -#define AUX_EVCTL_MANUAL_EV_BITN 0 -#define AUX_EVCTL_MANUAL_EV_M 0x00000001 -#define AUX_EVCTL_MANUAL_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT0L -// -//***************************************************************************** -// Field: [7:0] ALIAS_EV -// -// Alias of EVSTAT0 event 7 down to 0. -#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT0L_ALIAS_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT0H -// -//***************************************************************************** -// Field: [7:0] ALIAS_EV -// -// Alias of EVSTAT0 event 15 down to 8. -#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT0H_ALIAS_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT1L -// -//***************************************************************************** -// Field: [7:0] ALIAS_EV -// -// Alias of EVSTAT1 event 7 down to 0. -#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT1L_ALIAS_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT1H -// -//***************************************************************************** -// Field: [7:0] ALIAS_EV -// -// Alias of EVSTAT1 event 15 down to 8. -#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT1H_ALIAS_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT2L -// -//***************************************************************************** -// Field: [7:0] ALIAS_EV -// -// Alias of EVSTAT2 event 7 down to 0. -#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT2L_ALIAS_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT2H -// -//***************************************************************************** -// Field: [7:0] ALIAS_EV -// -// Alias of EVSTAT2 event 15 down to 8. -#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT2H_ALIAS_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT3L -// -//***************************************************************************** -// Field: [7:0] ALIAS_EV -// -// Alias of EVSTAT3 event 7 down to 0. -#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT3L_ALIAS_EV_S 0 - -//***************************************************************************** -// -// Register: AUX_EVCTL_O_EVSTAT3H -// -//***************************************************************************** -// Field: [7:0] ALIAS_EV -// -// Alias of EVSTAT3 event 15 down to 8. -#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_W 8 -#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_M 0x000000FF -#define AUX_EVCTL_EVSTAT3H_ALIAS_EV_S 0 - - -#endif // __AUX_EVCTL__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h deleted file mode 100644 index 83dea0bb862..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_mac.h +++ /dev/null @@ -1,748 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_mac_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_MAC_H__ -#define __HW_AUX_MAC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_MAC component -// -//***************************************************************************** -// Signed Operand 0 -#define AUX_MAC_O_OP0S 0x00000000 - -// Unsigned Operand 0 -#define AUX_MAC_O_OP0U 0x00000004 - -// Signed Operand 1 and Multiply -#define AUX_MAC_O_OP1SMUL 0x00000008 - -// Unsigned Operand 1 and Multiply -#define AUX_MAC_O_OP1UMUL 0x0000000C - -// Signed Operand 1 and Multiply-Accumulate -#define AUX_MAC_O_OP1SMAC 0x00000010 - -// Unsigned Operand 1 and Multiply-Accumulate -#define AUX_MAC_O_OP1UMAC 0x00000014 - -// Signed Operand 1 and 16-bit Addition -#define AUX_MAC_O_OP1SADD16 0x00000018 - -// Unsigned Operand 1 and 16-bit Addition -#define AUX_MAC_O_OP1UADD16 0x0000001C - -// Signed Operand 1 and 32-bit Addition -#define AUX_MAC_O_OP1SADD32 0x00000020 - -// Unsigned Operand 1 and 32-bit Addition -#define AUX_MAC_O_OP1UADD32 0x00000024 - -// Count Leading Zero -#define AUX_MAC_O_CLZ 0x00000028 - -// Count Leading Sign -#define AUX_MAC_O_CLS 0x0000002C - -// Accumulator Shift -#define AUX_MAC_O_ACCSHIFT 0x00000030 - -// Accumulator Reset -#define AUX_MAC_O_ACCRESET 0x00000034 - -// Accumulator Bits 15:0 -#define AUX_MAC_O_ACC15_0 0x00000038 - -// Accumulator Bits 16:1 -#define AUX_MAC_O_ACC16_1 0x0000003C - -// Accumulator Bits 17:2 -#define AUX_MAC_O_ACC17_2 0x00000040 - -// Accumulator Bits 18:3 -#define AUX_MAC_O_ACC18_3 0x00000044 - -// Accumulator Bits 19:4 -#define AUX_MAC_O_ACC19_4 0x00000048 - -// Accumulator Bits 20:5 -#define AUX_MAC_O_ACC20_5 0x0000004C - -// Accumulator Bits 21:6 -#define AUX_MAC_O_ACC21_6 0x00000050 - -// Accumulator Bits 22:7 -#define AUX_MAC_O_ACC22_7 0x00000054 - -// Accumulator Bits 23:8 -#define AUX_MAC_O_ACC23_8 0x00000058 - -// Accumulator Bits 24:9 -#define AUX_MAC_O_ACC24_9 0x0000005C - -// Accumulator Bits 25:10 -#define AUX_MAC_O_ACC25_10 0x00000060 - -// Accumulator Bits 26:11 -#define AUX_MAC_O_ACC26_11 0x00000064 - -// Accumulator Bits 27:12 -#define AUX_MAC_O_ACC27_12 0x00000068 - -// Accumulator Bits 28:13 -#define AUX_MAC_O_ACC28_13 0x0000006C - -// Accumulator Bits 29:14 -#define AUX_MAC_O_ACC29_14 0x00000070 - -// Accumulator Bits 30:15 -#define AUX_MAC_O_ACC30_15 0x00000074 - -// Accumulator Bits 31:16 -#define AUX_MAC_O_ACC31_16 0x00000078 - -// Accumulator Bits 32:17 -#define AUX_MAC_O_ACC32_17 0x0000007C - -// Accumulator Bits 33:18 -#define AUX_MAC_O_ACC33_18 0x00000080 - -// Accumulator Bits 34:19 -#define AUX_MAC_O_ACC34_19 0x00000084 - -// Accumulator Bits 35:20 -#define AUX_MAC_O_ACC35_20 0x00000088 - -// Accumulator Bits 36:21 -#define AUX_MAC_O_ACC36_21 0x0000008C - -// Accumulator Bits 37:22 -#define AUX_MAC_O_ACC37_22 0x00000090 - -// Accumulator Bits 38:23 -#define AUX_MAC_O_ACC38_23 0x00000094 - -// Accumulator Bits 39:24 -#define AUX_MAC_O_ACC39_24 0x00000098 - -// Accumulator Bits 39:32 -#define AUX_MAC_O_ACC39_32 0x0000009C - -//***************************************************************************** -// -// Register: AUX_MAC_O_OP0S -// -//***************************************************************************** -// Field: [15:0] OP0_VALUE -// -// Signed operand 0. -// -// Operand for multiply, multiply-and-accumulate, or 32-bit add operations. -#define AUX_MAC_OP0S_OP0_VALUE_W 16 -#define AUX_MAC_OP0S_OP0_VALUE_M 0x0000FFFF -#define AUX_MAC_OP0S_OP0_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_OP0U -// -//***************************************************************************** -// Field: [15:0] OP0_VALUE -// -// Unsigned operand 0. -// -// Operand for multiply, multiply-and-accumulate, or 32-bit add operations. -#define AUX_MAC_OP0U_OP0_VALUE_W 16 -#define AUX_MAC_OP0U_OP0_VALUE_M 0x0000FFFF -#define AUX_MAC_OP0U_OP0_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_OP1SMUL -// -//***************************************************************************** -// Field: [15:0] OP1_VALUE -// -// Signed operand 1 and multiplication trigger. -// -// Write OP1_VALUE to set signed operand 1 and trigger the following operation: -// -// When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * -// OP0S.OP0_VALUE. -// When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE * -// OP0U.OP0_VALUE. -#define AUX_MAC_OP1SMUL_OP1_VALUE_W 16 -#define AUX_MAC_OP1SMUL_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1SMUL_OP1_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_OP1UMUL -// -//***************************************************************************** -// Field: [15:0] OP1_VALUE -// -// Unsigned operand 1 and multiplication trigger. -// -// Write OP1_VALUE to set unsigned operand 1 and trigger the following -// operation: -// -// When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * -// OP0S.OP0_VALUE. -// When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE * -// OP0U.OP0_VALUE. -#define AUX_MAC_OP1UMUL_OP1_VALUE_W 16 -#define AUX_MAC_OP1UMUL_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1UMUL_OP1_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_OP1SMAC -// -//***************************************************************************** -// Field: [15:0] OP1_VALUE -// -// Signed operand 1 and multiply-accumulation trigger. -// -// Write OP1_VALUE to set signed operand 1 and trigger the following operation: -// -// When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * -// OP0S.OP0_VALUE ). -// When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE * -// OP0U.OP0_VALUE ). -#define AUX_MAC_OP1SMAC_OP1_VALUE_W 16 -#define AUX_MAC_OP1SMAC_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1SMAC_OP1_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_OP1UMAC -// -//***************************************************************************** -// Field: [15:0] OP1_VALUE -// -// Unsigned operand 1 and multiply-accumulation trigger. -// -// Write OP1_VALUE to set unsigned operand 1 and trigger the following -// operation: -// -// When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * -// OP0S.OP0_VALUE ). -// When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE * -// OP0U.OP0_VALUE ). -#define AUX_MAC_OP1UMAC_OP1_VALUE_W 16 -#define AUX_MAC_OP1UMAC_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1UMAC_OP1_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_OP1SADD16 -// -//***************************************************************************** -// Field: [15:0] OP1_VALUE -// -// Signed operand 1 and 16-bit addition trigger. -// -// Write OP1_VALUE to set signed operand 1 and trigger the following operation: -// -// ACC = ACC + OP1_VALUE. -#define AUX_MAC_OP1SADD16_OP1_VALUE_W 16 -#define AUX_MAC_OP1SADD16_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1SADD16_OP1_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_OP1UADD16 -// -//***************************************************************************** -// Field: [15:0] OP1_VALUE -// -// Unsigned operand 1 and 16-bit addition trigger. -// -// Write OP1_VALUE to set unsigned operand 1 and trigger the following -// operation: -// -// ACC = ACC + OP1_VALUE. -#define AUX_MAC_OP1UADD16_OP1_VALUE_W 16 -#define AUX_MAC_OP1UADD16_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1UADD16_OP1_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_OP1SADD32 -// -//***************************************************************************** -// Field: [15:0] OP1_VALUE -// -// Upper half of signed 32-bit operand and addition trigger. -// -// Write OP1_VALUE to set upper half of signed 32-bit operand and trigger the -// following operation: -// -// When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + -// (( OP1_VALUE << 16) | OP0S.OP0_VALUE ). -// When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC + -// (( OP1_VALUE << 16) | OP0U.OP0_VALUE ). -#define AUX_MAC_OP1SADD32_OP1_VALUE_W 16 -#define AUX_MAC_OP1SADD32_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1SADD32_OP1_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_OP1UADD32 -// -//***************************************************************************** -// Field: [15:0] OP1_VALUE -// -// Upper half of unsigned 32-bit operand and addition trigger. -// -// Write OP1_VALUE to set upper half of unsigned 32-bit operand and trigger the -// following operation: -// -// When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + -// (( OP1_VALUE << 16) | OP0S.OP0_VALUE ). -// When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC + -// (( OP1_VALUE << 16) | OP0U.OP0_VALUE ). -#define AUX_MAC_OP1UADD32_OP1_VALUE_W 16 -#define AUX_MAC_OP1UADD32_OP1_VALUE_M 0x0000FFFF -#define AUX_MAC_OP1UADD32_OP1_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_CLZ -// -//***************************************************************************** -// Field: [5:0] VALUE -// -// Number of leading zero bits in the accumulator: -// -// 0x00: 0 leading zeros. -// 0x01: 1 leading zero. -// ... -// 0x28: 40 leading zeros (accumulator value is 0). -#define AUX_MAC_CLZ_VALUE_W 6 -#define AUX_MAC_CLZ_VALUE_M 0x0000003F -#define AUX_MAC_CLZ_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_CLS -// -//***************************************************************************** -// Field: [5:0] VALUE -// -// Number of leading sign bits in the accumulator. -// -// When MSB of accumulator is 0, VALUE is number of leading zeros, MSB -// included. -// When MSB of accumulator is 1, VALUE is number of leading ones, MSB included. -// -// VALUE range is 1 thru 40. -#define AUX_MAC_CLS_VALUE_W 6 -#define AUX_MAC_CLS_VALUE_M 0x0000003F -#define AUX_MAC_CLS_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACCSHIFT -// -//***************************************************************************** -// Field: [2] LSL1 -// -// Logic shift left by 1 bit. -// -// Write 1 to shift the accumulator one bit to the left, 0 inserted at bit 0. -#define AUX_MAC_ACCSHIFT_LSL1 0x00000004 -#define AUX_MAC_ACCSHIFT_LSL1_BITN 2 -#define AUX_MAC_ACCSHIFT_LSL1_M 0x00000004 -#define AUX_MAC_ACCSHIFT_LSL1_S 2 - -// Field: [1] LSR1 -// -// Logic shift right by 1 bit. -// -// Write 1 to shift the accumulator one bit to the right, 0 inserted at bit 39. -#define AUX_MAC_ACCSHIFT_LSR1 0x00000002 -#define AUX_MAC_ACCSHIFT_LSR1_BITN 1 -#define AUX_MAC_ACCSHIFT_LSR1_M 0x00000002 -#define AUX_MAC_ACCSHIFT_LSR1_S 1 - -// Field: [0] ASR1 -// -// Arithmetic shift right by 1 bit. -// -// Write 1 to shift the accumulator one bit to the right, previous sign bit -// inserted at bit 39. -#define AUX_MAC_ACCSHIFT_ASR1 0x00000001 -#define AUX_MAC_ACCSHIFT_ASR1_BITN 0 -#define AUX_MAC_ACCSHIFT_ASR1_M 0x00000001 -#define AUX_MAC_ACCSHIFT_ASR1_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACCRESET -// -//***************************************************************************** -// Field: [15:0] TRG -// -// Write any value to this register to trigger a reset of all bits in the -// accumulator. -#define AUX_MAC_ACCRESET_TRG_W 16 -#define AUX_MAC_ACCRESET_TRG_M 0x0000FFFF -#define AUX_MAC_ACCRESET_TRG_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC15_0 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 15:0. -// -// Write VALUE to initialize bits 15:0 of accumulator. -#define AUX_MAC_ACC15_0_VALUE_W 16 -#define AUX_MAC_ACC15_0_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC15_0_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC16_1 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 16:1. -#define AUX_MAC_ACC16_1_VALUE_W 16 -#define AUX_MAC_ACC16_1_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC16_1_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC17_2 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 17:2. -#define AUX_MAC_ACC17_2_VALUE_W 16 -#define AUX_MAC_ACC17_2_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC17_2_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC18_3 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 18:3. -#define AUX_MAC_ACC18_3_VALUE_W 16 -#define AUX_MAC_ACC18_3_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC18_3_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC19_4 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 19:4. -#define AUX_MAC_ACC19_4_VALUE_W 16 -#define AUX_MAC_ACC19_4_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC19_4_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC20_5 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 20:5. -#define AUX_MAC_ACC20_5_VALUE_W 16 -#define AUX_MAC_ACC20_5_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC20_5_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC21_6 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 21:6. -#define AUX_MAC_ACC21_6_VALUE_W 16 -#define AUX_MAC_ACC21_6_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC21_6_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC22_7 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 22:7. -#define AUX_MAC_ACC22_7_VALUE_W 16 -#define AUX_MAC_ACC22_7_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC22_7_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC23_8 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 23:8. -#define AUX_MAC_ACC23_8_VALUE_W 16 -#define AUX_MAC_ACC23_8_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC23_8_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC24_9 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 24:9. -#define AUX_MAC_ACC24_9_VALUE_W 16 -#define AUX_MAC_ACC24_9_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC24_9_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC25_10 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 25:10. -#define AUX_MAC_ACC25_10_VALUE_W 16 -#define AUX_MAC_ACC25_10_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC25_10_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC26_11 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 26:11. -#define AUX_MAC_ACC26_11_VALUE_W 16 -#define AUX_MAC_ACC26_11_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC26_11_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC27_12 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 27:12. -#define AUX_MAC_ACC27_12_VALUE_W 16 -#define AUX_MAC_ACC27_12_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC27_12_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC28_13 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 28:13. -#define AUX_MAC_ACC28_13_VALUE_W 16 -#define AUX_MAC_ACC28_13_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC28_13_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC29_14 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 29:14. -#define AUX_MAC_ACC29_14_VALUE_W 16 -#define AUX_MAC_ACC29_14_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC29_14_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC30_15 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 30:15. -#define AUX_MAC_ACC30_15_VALUE_W 16 -#define AUX_MAC_ACC30_15_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC30_15_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC31_16 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 31:16. -// -// Write VALUE to initialize bits 31:16 of accumulator. -#define AUX_MAC_ACC31_16_VALUE_W 16 -#define AUX_MAC_ACC31_16_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC31_16_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC32_17 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 32:17. -#define AUX_MAC_ACC32_17_VALUE_W 16 -#define AUX_MAC_ACC32_17_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC32_17_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC33_18 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 33:18. -#define AUX_MAC_ACC33_18_VALUE_W 16 -#define AUX_MAC_ACC33_18_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC33_18_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC34_19 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 34:19. -#define AUX_MAC_ACC34_19_VALUE_W 16 -#define AUX_MAC_ACC34_19_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC34_19_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC35_20 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 35:20. -#define AUX_MAC_ACC35_20_VALUE_W 16 -#define AUX_MAC_ACC35_20_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC35_20_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC36_21 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 36:21. -#define AUX_MAC_ACC36_21_VALUE_W 16 -#define AUX_MAC_ACC36_21_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC36_21_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC37_22 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 37:22. -#define AUX_MAC_ACC37_22_VALUE_W 16 -#define AUX_MAC_ACC37_22_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC37_22_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC38_23 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 38:23. -#define AUX_MAC_ACC38_23_VALUE_W 16 -#define AUX_MAC_ACC38_23_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC38_23_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC39_24 -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Value of the accumulator, bits 39:24. -#define AUX_MAC_ACC39_24_VALUE_W 16 -#define AUX_MAC_ACC39_24_VALUE_M 0x0000FFFF -#define AUX_MAC_ACC39_24_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_MAC_O_ACC39_32 -// -//***************************************************************************** -// Field: [7:0] VALUE -// -// Value of the accumulator, bits 39:32. -// -// Write VALUE to initialize bits 39:32 of accumulator. -#define AUX_MAC_ACC39_32_VALUE_W 8 -#define AUX_MAC_ACC39_32_VALUE_M 0x000000FF -#define AUX_MAC_ACC39_32_VALUE_S 0 - - -#endif // __AUX_MAC__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h deleted file mode 100644 index 6a20b915698..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_ram.h +++ /dev/null @@ -1,48 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_ram_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_RAM_H__ -#define __HW_AUX_RAM_H__ - - -#define AUX_RAM_O_BANK0 0x00000000 -#define AUX_RAM_BANK0_BYTE_SIZE 4096 - -#define AUX_RAM_TOT_BYTE_SIZE 4096 - - - -#endif // __HW_AUX_RAM__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h deleted file mode 100644 index 39f17586708..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sce.h +++ /dev/null @@ -1,398 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_sce_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_SCE_H__ -#define __HW_AUX_SCE_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_SCE component -// -//***************************************************************************** -// Internal -#define AUX_SCE_O_CTL 0x00000000 - -// Internal -#define AUX_SCE_O_FETCHSTAT 0x00000004 - -// Internal -#define AUX_SCE_O_CPUSTAT 0x00000008 - -// Internal -#define AUX_SCE_O_WUSTAT 0x0000000C - -// Internal -#define AUX_SCE_O_REG1_0 0x00000010 - -// Internal -#define AUX_SCE_O_REG3_2 0x00000014 - -// Internal -#define AUX_SCE_O_REG5_4 0x00000018 - -// Internal -#define AUX_SCE_O_REG7_6 0x0000001C - -// Internal -#define AUX_SCE_O_LOOPADDR 0x00000020 - -// Internal -#define AUX_SCE_O_LOOPCNT 0x00000024 - -//***************************************************************************** -// -// Register: AUX_SCE_O_CTL -// -//***************************************************************************** -// Field: [31:24] FORCE_EV_LOW -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_EV_LOW_W 8 -#define AUX_SCE_CTL_FORCE_EV_LOW_M 0xFF000000 -#define AUX_SCE_CTL_FORCE_EV_LOW_S 24 - -// Field: [23:16] FORCE_EV_HIGH -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_EV_HIGH_W 8 -#define AUX_SCE_CTL_FORCE_EV_HIGH_M 0x00FF0000 -#define AUX_SCE_CTL_FORCE_EV_HIGH_S 16 - -// Field: [15:8] RESET_VECTOR -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_RESET_VECTOR_W 8 -#define AUX_SCE_CTL_RESET_VECTOR_M 0x0000FF00 -#define AUX_SCE_CTL_RESET_VECTOR_S 8 - -// Field: [6] DBG_FREEZE_EN -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_DBG_FREEZE_EN 0x00000040 -#define AUX_SCE_CTL_DBG_FREEZE_EN_BITN 6 -#define AUX_SCE_CTL_DBG_FREEZE_EN_M 0x00000040 -#define AUX_SCE_CTL_DBG_FREEZE_EN_S 6 - -// Field: [5] FORCE_WU_LOW -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_WU_LOW 0x00000020 -#define AUX_SCE_CTL_FORCE_WU_LOW_BITN 5 -#define AUX_SCE_CTL_FORCE_WU_LOW_M 0x00000020 -#define AUX_SCE_CTL_FORCE_WU_LOW_S 5 - -// Field: [4] FORCE_WU_HIGH -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_FORCE_WU_HIGH 0x00000010 -#define AUX_SCE_CTL_FORCE_WU_HIGH_BITN 4 -#define AUX_SCE_CTL_FORCE_WU_HIGH_M 0x00000010 -#define AUX_SCE_CTL_FORCE_WU_HIGH_S 4 - -// Field: [3] RESTART -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_RESTART 0x00000008 -#define AUX_SCE_CTL_RESTART_BITN 3 -#define AUX_SCE_CTL_RESTART_M 0x00000008 -#define AUX_SCE_CTL_RESTART_S 3 - -// Field: [2] SINGLE_STEP -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_SINGLE_STEP 0x00000004 -#define AUX_SCE_CTL_SINGLE_STEP_BITN 2 -#define AUX_SCE_CTL_SINGLE_STEP_M 0x00000004 -#define AUX_SCE_CTL_SINGLE_STEP_S 2 - -// Field: [1] SUSPEND -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_SUSPEND 0x00000002 -#define AUX_SCE_CTL_SUSPEND_BITN 1 -#define AUX_SCE_CTL_SUSPEND_M 0x00000002 -#define AUX_SCE_CTL_SUSPEND_S 1 - -// Field: [0] CLK_EN -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CTL_CLK_EN 0x00000001 -#define AUX_SCE_CTL_CLK_EN_BITN 0 -#define AUX_SCE_CTL_CLK_EN_M 0x00000001 -#define AUX_SCE_CTL_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_FETCHSTAT -// -//***************************************************************************** -// Field: [31:16] OPCODE -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_FETCHSTAT_OPCODE_W 16 -#define AUX_SCE_FETCHSTAT_OPCODE_M 0xFFFF0000 -#define AUX_SCE_FETCHSTAT_OPCODE_S 16 - -// Field: [15:0] PC -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_FETCHSTAT_PC_W 16 -#define AUX_SCE_FETCHSTAT_PC_M 0x0000FFFF -#define AUX_SCE_FETCHSTAT_PC_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_CPUSTAT -// -//***************************************************************************** -// Field: [11] BUS_ERROR -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_BUS_ERROR 0x00000800 -#define AUX_SCE_CPUSTAT_BUS_ERROR_BITN 11 -#define AUX_SCE_CPUSTAT_BUS_ERROR_M 0x00000800 -#define AUX_SCE_CPUSTAT_BUS_ERROR_S 11 - -// Field: [10] SLEEP -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_SLEEP 0x00000400 -#define AUX_SCE_CPUSTAT_SLEEP_BITN 10 -#define AUX_SCE_CPUSTAT_SLEEP_M 0x00000400 -#define AUX_SCE_CPUSTAT_SLEEP_S 10 - -// Field: [9] WEV -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_WEV 0x00000200 -#define AUX_SCE_CPUSTAT_WEV_BITN 9 -#define AUX_SCE_CPUSTAT_WEV_M 0x00000200 -#define AUX_SCE_CPUSTAT_WEV_S 9 - -// Field: [8] HALTED -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_HALTED 0x00000100 -#define AUX_SCE_CPUSTAT_HALTED_BITN 8 -#define AUX_SCE_CPUSTAT_HALTED_M 0x00000100 -#define AUX_SCE_CPUSTAT_HALTED_S 8 - -// Field: [3] V_FLAG -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_V_FLAG 0x00000008 -#define AUX_SCE_CPUSTAT_V_FLAG_BITN 3 -#define AUX_SCE_CPUSTAT_V_FLAG_M 0x00000008 -#define AUX_SCE_CPUSTAT_V_FLAG_S 3 - -// Field: [2] C_FLAG -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_C_FLAG 0x00000004 -#define AUX_SCE_CPUSTAT_C_FLAG_BITN 2 -#define AUX_SCE_CPUSTAT_C_FLAG_M 0x00000004 -#define AUX_SCE_CPUSTAT_C_FLAG_S 2 - -// Field: [1] N_FLAG -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_N_FLAG 0x00000002 -#define AUX_SCE_CPUSTAT_N_FLAG_BITN 1 -#define AUX_SCE_CPUSTAT_N_FLAG_M 0x00000002 -#define AUX_SCE_CPUSTAT_N_FLAG_S 1 - -// Field: [0] Z_FLAG -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_CPUSTAT_Z_FLAG 0x00000001 -#define AUX_SCE_CPUSTAT_Z_FLAG_BITN 0 -#define AUX_SCE_CPUSTAT_Z_FLAG_M 0x00000001 -#define AUX_SCE_CPUSTAT_Z_FLAG_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_WUSTAT -// -//***************************************************************************** -// Field: [18:16] EXC_VECTOR -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_EXC_VECTOR_W 3 -#define AUX_SCE_WUSTAT_EXC_VECTOR_M 0x00070000 -#define AUX_SCE_WUSTAT_EXC_VECTOR_S 16 - -// Field: [8] WU_SIGNAL -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_WU_SIGNAL 0x00000100 -#define AUX_SCE_WUSTAT_WU_SIGNAL_BITN 8 -#define AUX_SCE_WUSTAT_WU_SIGNAL_M 0x00000100 -#define AUX_SCE_WUSTAT_WU_SIGNAL_S 8 - -// Field: [7:0] EV_SIGNALS -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// SCEWEV_PROG Internal. Only to be used through TI provided API. -// AUX_ADC_FIFO_NOT_EMPTY Internal. Only to be used through TI provided API. -// AUX_TIMER1_EV_OR_IDLE Internal. Only to be used through TI provided API. -// AUX_TIMER0_EV_OR_IDLE Internal. Only to be used through TI provided API. -// AUX_TDC_DONE Internal. Only to be used through TI provided API. -// AUX_COMPB Internal. Only to be used through TI provided API. -// AUX_COMPA Internal. Only to be used through TI provided API. -// AUX_PROG_DLY_IDLE Internal. Only to be used through TI provided API. -#define AUX_SCE_WUSTAT_EV_SIGNALS_W 8 -#define AUX_SCE_WUSTAT_EV_SIGNALS_M 0x000000FF -#define AUX_SCE_WUSTAT_EV_SIGNALS_S 0 -#define AUX_SCE_WUSTAT_EV_SIGNALS_SCEWEV_PROG 0x00000080 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_ADC_FIFO_NOT_EMPTY 0x00000040 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TIMER1_EV_OR_IDLE 0x00000020 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TIMER0_EV_OR_IDLE 0x00000010 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_TDC_DONE 0x00000008 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_COMPB 0x00000004 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_COMPA 0x00000002 -#define AUX_SCE_WUSTAT_EV_SIGNALS_AUX_PROG_DLY_IDLE 0x00000001 - -//***************************************************************************** -// -// Register: AUX_SCE_O_REG1_0 -// -//***************************************************************************** -// Field: [31:16] REG1 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG1_0_REG1_W 16 -#define AUX_SCE_REG1_0_REG1_M 0xFFFF0000 -#define AUX_SCE_REG1_0_REG1_S 16 - -// Field: [15:0] REG0 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG1_0_REG0_W 16 -#define AUX_SCE_REG1_0_REG0_M 0x0000FFFF -#define AUX_SCE_REG1_0_REG0_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_REG3_2 -// -//***************************************************************************** -// Field: [31:16] REG3 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG3_2_REG3_W 16 -#define AUX_SCE_REG3_2_REG3_M 0xFFFF0000 -#define AUX_SCE_REG3_2_REG3_S 16 - -// Field: [15:0] REG2 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG3_2_REG2_W 16 -#define AUX_SCE_REG3_2_REG2_M 0x0000FFFF -#define AUX_SCE_REG3_2_REG2_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_REG5_4 -// -//***************************************************************************** -// Field: [31:16] REG5 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG5_4_REG5_W 16 -#define AUX_SCE_REG5_4_REG5_M 0xFFFF0000 -#define AUX_SCE_REG5_4_REG5_S 16 - -// Field: [15:0] REG4 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG5_4_REG4_W 16 -#define AUX_SCE_REG5_4_REG4_M 0x0000FFFF -#define AUX_SCE_REG5_4_REG4_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_REG7_6 -// -//***************************************************************************** -// Field: [31:16] REG7 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG7_6_REG7_W 16 -#define AUX_SCE_REG7_6_REG7_M 0xFFFF0000 -#define AUX_SCE_REG7_6_REG7_S 16 - -// Field: [15:0] REG6 -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_REG7_6_REG6_W 16 -#define AUX_SCE_REG7_6_REG6_M 0x0000FFFF -#define AUX_SCE_REG7_6_REG6_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_LOOPADDR -// -//***************************************************************************** -// Field: [31:16] STOP -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPADDR_STOP_W 16 -#define AUX_SCE_LOOPADDR_STOP_M 0xFFFF0000 -#define AUX_SCE_LOOPADDR_STOP_S 16 - -// Field: [15:0] START -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPADDR_START_W 16 -#define AUX_SCE_LOOPADDR_START_M 0x0000FFFF -#define AUX_SCE_LOOPADDR_START_S 0 - -//***************************************************************************** -// -// Register: AUX_SCE_O_LOOPCNT -// -//***************************************************************************** -// Field: [7:0] ITER_LEFT -// -// Internal. Only to be used through TI provided API. -#define AUX_SCE_LOOPCNT_ITER_LEFT_W 8 -#define AUX_SCE_LOOPCNT_ITER_LEFT_M 0x000000FF -#define AUX_SCE_LOOPCNT_ITER_LEFT_S 0 - - -#endif // __AUX_SCE__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h deleted file mode 100644 index 0bee0c53bd5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_smph.h +++ /dev/null @@ -1,282 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_smph_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_SMPH_H__ -#define __HW_AUX_SMPH_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_SMPH component -// -//***************************************************************************** -// Semaphore 0 -#define AUX_SMPH_O_SMPH0 0x00000000 - -// Semaphore 1 -#define AUX_SMPH_O_SMPH1 0x00000004 - -// Semaphore 2 -#define AUX_SMPH_O_SMPH2 0x00000008 - -// Semaphore 3 -#define AUX_SMPH_O_SMPH3 0x0000000C - -// Semaphore 4 -#define AUX_SMPH_O_SMPH4 0x00000010 - -// Semaphore 5 -#define AUX_SMPH_O_SMPH5 0x00000014 - -// Semaphore 6 -#define AUX_SMPH_O_SMPH6 0x00000018 - -// Semaphore 7 -#define AUX_SMPH_O_SMPH7 0x0000001C - -// Auto Take -#define AUX_SMPH_O_AUTOTAKE 0x00000020 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH0 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH0_STAT 0x00000001 -#define AUX_SMPH_SMPH0_STAT_BITN 0 -#define AUX_SMPH_SMPH0_STAT_M 0x00000001 -#define AUX_SMPH_SMPH0_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH1 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH1_STAT 0x00000001 -#define AUX_SMPH_SMPH1_STAT_BITN 0 -#define AUX_SMPH_SMPH1_STAT_M 0x00000001 -#define AUX_SMPH_SMPH1_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH2 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH2_STAT 0x00000001 -#define AUX_SMPH_SMPH2_STAT_BITN 0 -#define AUX_SMPH_SMPH2_STAT_M 0x00000001 -#define AUX_SMPH_SMPH2_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH3 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH3_STAT 0x00000001 -#define AUX_SMPH_SMPH3_STAT_BITN 0 -#define AUX_SMPH_SMPH3_STAT_M 0x00000001 -#define AUX_SMPH_SMPH3_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH4 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH4_STAT 0x00000001 -#define AUX_SMPH_SMPH4_STAT_BITN 0 -#define AUX_SMPH_SMPH4_STAT_M 0x00000001 -#define AUX_SMPH_SMPH4_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH5 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH5_STAT 0x00000001 -#define AUX_SMPH_SMPH5_STAT_BITN 0 -#define AUX_SMPH_SMPH5_STAT_M 0x00000001 -#define AUX_SMPH_SMPH5_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH6 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH6_STAT 0x00000001 -#define AUX_SMPH_SMPH6_STAT_BITN 0 -#define AUX_SMPH_SMPH6_STAT_M 0x00000001 -#define AUX_SMPH_SMPH6_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_SMPH7 -// -//***************************************************************************** -// Field: [0] STAT -// -// Request or release of semaphore. -// -// Request by read: -// -// 0: Semaphore not available. -// 1: Semaphore granted. -// -// Release by write: -// -// 0: Do not use. -// 1: Release semaphore. -#define AUX_SMPH_SMPH7_STAT 0x00000001 -#define AUX_SMPH_SMPH7_STAT_BITN 0 -#define AUX_SMPH_SMPH7_STAT_M 0x00000001 -#define AUX_SMPH_SMPH7_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SMPH_O_AUTOTAKE -// -//***************************************************************************** -// Field: [2:0] SMPH_ID -// -// Write the semaphore ID,0x0-0x7, to SMPH_ID to request this semaphore until -// it is granted. -// -// When semaphore SMPH_ID is granted, event -// AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE becomes 1. -// -// The event becomes 0 when software releases the semaphore or writes a new -// value to SMPH_ID. -// -// To avoid corrupted semaphores: -// - Usage of this functionality must be restricted to one CPU core. -// - Software must wait until AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE is 1 -// before it writes a new value to SMPH_ID. -#define AUX_SMPH_AUTOTAKE_SMPH_ID_W 3 -#define AUX_SMPH_AUTOTAKE_SMPH_ID_M 0x00000007 -#define AUX_SMPH_AUTOTAKE_SMPH_ID_S 0 - - -#endif // __AUX_SMPH__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h deleted file mode 100644 index c2f354da79e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_spim.h +++ /dev/null @@ -1,239 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_spim_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_SPIM_H__ -#define __HW_AUX_SPIM_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_SPIM component -// -//***************************************************************************** -// SPI Master Configuration -#define AUX_SPIM_O_SPIMCFG 0x00000000 - -// MISO Configuration -#define AUX_SPIM_O_MISOCFG 0x00000004 - -// MOSI Control -#define AUX_SPIM_O_MOSICTL 0x00000008 - -// Transmit 8 Bit -#define AUX_SPIM_O_TX8 0x0000000C - -// Transmit 16 Bit -#define AUX_SPIM_O_TX16 0x00000010 - -// Receive 8 Bit -#define AUX_SPIM_O_RX8 0x00000014 - -// Receive 16 Bit -#define AUX_SPIM_O_RX16 0x00000018 - -// SCLK Idle -#define AUX_SPIM_O_SCLKIDLE 0x0000001C - -// Data Idle -#define AUX_SPIM_O_DATAIDLE 0x00000020 - -//***************************************************************************** -// -// Register: AUX_SPIM_O_SPIMCFG -// -//***************************************************************************** -// Field: [7:2] DIV -// -// SCLK divider. -// -// Peripheral clock frequency division gives the SCLK clock frequency. The -// division factor equals (2 * (DIV+1)): -// -// 0x00: Divide by 2. -// 0x01: Divide by 4. -// 0x02: Divide by 6. -// ... -// 0x3F: Divide by 128. -#define AUX_SPIM_SPIMCFG_DIV_W 6 -#define AUX_SPIM_SPIMCFG_DIV_M 0x000000FC -#define AUX_SPIM_SPIMCFG_DIV_S 2 - -// Field: [1] PHA -// -// Phase of the MOSI and MISO data signals. -// -// 0: Sample MISO at leading (odd) edges and shift MOSI at trailing (even) -// edges of SCLK. -// 1: Sample MISO at trailing (even) edges and shift MOSI at leading (odd) -// edges of SCLK. -#define AUX_SPIM_SPIMCFG_PHA 0x00000002 -#define AUX_SPIM_SPIMCFG_PHA_BITN 1 -#define AUX_SPIM_SPIMCFG_PHA_M 0x00000002 -#define AUX_SPIM_SPIMCFG_PHA_S 1 - -// Field: [0] POL -// -// Polarity of the SCLK signal. -// -// 0: SCLK is low when idle, first clock edge rises. -// 1: SCLK is high when idle, first clock edge falls. -#define AUX_SPIM_SPIMCFG_POL 0x00000001 -#define AUX_SPIM_SPIMCFG_POL_BITN 0 -#define AUX_SPIM_SPIMCFG_POL_M 0x00000001 -#define AUX_SPIM_SPIMCFG_POL_S 0 - -//***************************************************************************** -// -// Register: AUX_SPIM_O_MISOCFG -// -//***************************************************************************** -// Field: [4:0] AUXIO -// -// AUXIO to MISO mux. -// -// Select the AUXIO pin that connects to MISO. -#define AUX_SPIM_MISOCFG_AUXIO_W 5 -#define AUX_SPIM_MISOCFG_AUXIO_M 0x0000001F -#define AUX_SPIM_MISOCFG_AUXIO_S 0 - -//***************************************************************************** -// -// Register: AUX_SPIM_O_MOSICTL -// -//***************************************************************************** -// Field: [0] VALUE -// -// MOSI level control. -// -// 0: Set MOSI low. -// 1: Set MOSI high. -#define AUX_SPIM_MOSICTL_VALUE 0x00000001 -#define AUX_SPIM_MOSICTL_VALUE_BITN 0 -#define AUX_SPIM_MOSICTL_VALUE_M 0x00000001 -#define AUX_SPIM_MOSICTL_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_SPIM_O_TX8 -// -//***************************************************************************** -// Field: [7:0] DATA -// -// 8 bit data transfer. -// -// Write DATA to start transfer, MSB first. When transfer completes, MOSI stays -// at the value of LSB. -#define AUX_SPIM_TX8_DATA_W 8 -#define AUX_SPIM_TX8_DATA_M 0x000000FF -#define AUX_SPIM_TX8_DATA_S 0 - -//***************************************************************************** -// -// Register: AUX_SPIM_O_TX16 -// -//***************************************************************************** -// Field: [15:0] DATA -// -// 16 bit data transfer. -// -// Write DATA to start transfer, MSB first. When transfer completes, MOSI stays -// at the value of LSB. -#define AUX_SPIM_TX16_DATA_W 16 -#define AUX_SPIM_TX16_DATA_M 0x0000FFFF -#define AUX_SPIM_TX16_DATA_S 0 - -//***************************************************************************** -// -// Register: AUX_SPIM_O_RX8 -// -//***************************************************************************** -// Field: [7:0] DATA -// -// Latest 8 bits received on MISO. -#define AUX_SPIM_RX8_DATA_W 8 -#define AUX_SPIM_RX8_DATA_M 0x000000FF -#define AUX_SPIM_RX8_DATA_S 0 - -//***************************************************************************** -// -// Register: AUX_SPIM_O_RX16 -// -//***************************************************************************** -// Field: [15:0] DATA -// -// Latest 16 bits received on MISO. -#define AUX_SPIM_RX16_DATA_W 16 -#define AUX_SPIM_RX16_DATA_M 0x0000FFFF -#define AUX_SPIM_RX16_DATA_S 0 - -//***************************************************************************** -// -// Register: AUX_SPIM_O_SCLKIDLE -// -//***************************************************************************** -// Field: [0] STAT -// -// Wait for SCLK idle. -// -// Read operation stalls until SCLK is idle with no remaining clock edges. Read -// then returns 1. -// -// AUX_SCE can use this to control CS deassertion. -#define AUX_SPIM_SCLKIDLE_STAT 0x00000001 -#define AUX_SPIM_SCLKIDLE_STAT_BITN 0 -#define AUX_SPIM_SCLKIDLE_STAT_M 0x00000001 -#define AUX_SPIM_SCLKIDLE_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SPIM_O_DATAIDLE -// -//***************************************************************************** -// Field: [0] STAT -// -// Wait for data idle. -// -// Read operation stalls until the SCLK period associated with LSB transmission -// completes. Read then returns 1. -// -// AUX_SCE can use this to control CS deassertion. -#define AUX_SPIM_DATAIDLE_STAT 0x00000001 -#define AUX_SPIM_DATAIDLE_STAT_BITN 0 -#define AUX_SPIM_DATAIDLE_STAT_M 0x00000001 -#define AUX_SPIM_DATAIDLE_STAT_S 0 - - -#endif // __AUX_SPIM__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h deleted file mode 100644 index a3de3f94fe5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_sysif.h +++ /dev/null @@ -1,2088 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_sysif_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_SYSIF_H__ -#define __HW_AUX_SYSIF_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_SYSIF component -// -//***************************************************************************** -// Operational Mode Request -#define AUX_SYSIF_O_OPMODEREQ 0x00000000 - -// Operational Mode Acknowledgement -#define AUX_SYSIF_O_OPMODEACK 0x00000004 - -// Programmable Wakeup 0 Configuration -#define AUX_SYSIF_O_PROGWU0CFG 0x00000008 - -// Programmable Wakeup 1 Configuration -#define AUX_SYSIF_O_PROGWU1CFG 0x0000000C - -// Programmable Wakeup 2 Configuration -#define AUX_SYSIF_O_PROGWU2CFG 0x00000010 - -// Programmable Wakeup 3 Configuration -#define AUX_SYSIF_O_PROGWU3CFG 0x00000014 - -// Software Wakeup Triggers -#define AUX_SYSIF_O_SWWUTRIG 0x00000018 - -// Wakeup Flags -#define AUX_SYSIF_O_WUFLAGS 0x0000001C - -// Wakeup Flags Clear -#define AUX_SYSIF_O_WUFLAGSCLR 0x00000020 - -// Wakeup Gate -#define AUX_SYSIF_O_WUGATE 0x00000024 - -// Vector Configuration 0 -#define AUX_SYSIF_O_VECCFG0 0x00000028 - -// Vector Configuration 1 -#define AUX_SYSIF_O_VECCFG1 0x0000002C - -// Vector Configuration 2 -#define AUX_SYSIF_O_VECCFG2 0x00000030 - -// Vector Configuration 3 -#define AUX_SYSIF_O_VECCFG3 0x00000034 - -// Vector Configuration 4 -#define AUX_SYSIF_O_VECCFG4 0x00000038 - -// Vector Configuration 5 -#define AUX_SYSIF_O_VECCFG5 0x0000003C - -// Vector Configuration 6 -#define AUX_SYSIF_O_VECCFG6 0x00000040 - -// Vector Configuration 7 -#define AUX_SYSIF_O_VECCFG7 0x00000044 - -// Event Synchronization Rate -#define AUX_SYSIF_O_EVSYNCRATE 0x00000048 - -// Peripheral Operational Rate -#define AUX_SYSIF_O_PEROPRATE 0x0000004C - -// ADC Clock Control -#define AUX_SYSIF_O_ADCCLKCTL 0x00000050 - -// TDC Counter Clock Control -#define AUX_SYSIF_O_TDCCLKCTL 0x00000054 - -// TDC Reference Clock Control -#define AUX_SYSIF_O_TDCREFCLKCTL 0x00000058 - -// AUX_TIMER2 Clock Control -#define AUX_SYSIF_O_TIMER2CLKCTL 0x0000005C - -// AUX_TIMER2 Clock Status -#define AUX_SYSIF_O_TIMER2CLKSTAT 0x00000060 - -// AUX_TIMER2 Clock Switch -#define AUX_SYSIF_O_TIMER2CLKSWITCH 0x00000064 - -// AUX_TIMER2 Debug Control -#define AUX_SYSIF_O_TIMER2DBGCTL 0x00000068 - -// Clock Shift Detection -#define AUX_SYSIF_O_CLKSHIFTDET 0x00000070 - -// VDDR Recharge Trigger -#define AUX_SYSIF_O_RECHARGETRIG 0x00000074 - -// VDDR Recharge Detection -#define AUX_SYSIF_O_RECHARGEDET 0x00000078 - -// Real Time Counter Sub Second Increment 0 -#define AUX_SYSIF_O_RTCSUBSECINC0 0x0000007C - -// Real Time Counter Sub Second Increment 1 -#define AUX_SYSIF_O_RTCSUBSECINC1 0x00000080 - -// Real Time Counter Sub Second Increment Control -#define AUX_SYSIF_O_RTCSUBSECINCCTL 0x00000084 - -// Real Time Counter Second -#define AUX_SYSIF_O_RTCSEC 0x00000088 - -// Real Time Counter Sub-Second -#define AUX_SYSIF_O_RTCSUBSEC 0x0000008C - -// AON_RTC Event Clear -#define AUX_SYSIF_O_RTCEVCLR 0x00000090 - -// AON_BATMON Battery Voltage Value -#define AUX_SYSIF_O_BATMONBAT 0x00000094 - -// AON_BATMON Temperature Value -#define AUX_SYSIF_O_BATMONTEMP 0x0000009C - -// Timer Halt -#define AUX_SYSIF_O_TIMERHALT 0x000000A0 - -// AUX_TIMER2 Bridge -#define AUX_SYSIF_O_TIMER2BRIDGE 0x000000B0 - -// Software Power Profiler -#define AUX_SYSIF_O_SWPWRPROF 0x000000B4 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_OPMODEREQ -// -//***************************************************************************** -// Field: [1:0] REQ -// -// AUX operational mode request. -// ENUMs: -// PDLP Powerdown operational mode with wakeup to lowpower -// mode, characterized by: -// - Powerdown system power -// supply state (uLDO) request. -// - -// AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock -// frequency (SCE_RATE). -// - An active wakeup flag -// overrides the operational mode externally to -// lowpower (LP) as long as the flag is set. -// PDA Powerdown operational mode with wakeup to active -// mode, characterized by: -// - Powerdown system power -// supply state (uLDO) request. -// - -// AON_PMCTL:AUXSCECLK.PD_SRC sets the SCE clock -// frequency (SCE_RATE). -// - An active wakeup flag -// overrides the operational mode externally to -// active (A) as long as the flag is set. -// LP Lowpower operational mode, characterized by: -// - Powerdown system power -// supply state (uLDO) request. -// - SCE clock frequency -// (SCE_RATE) equals SCLK_MF. -// - An active wakeup flag -// does not change operational mode. -// A Active operational mode, characterized by: -// - Active system power -// supply state (GLDO or DCDC) request. -// - AON_PMCTL:AUXSCECLK.SRC -// sets the SCE clock frequency (SCE_RATE). -// - An active wakeup flag -// does not change operational mode. -#define AUX_SYSIF_OPMODEREQ_REQ_W 2 -#define AUX_SYSIF_OPMODEREQ_REQ_M 0x00000003 -#define AUX_SYSIF_OPMODEREQ_REQ_S 0 -#define AUX_SYSIF_OPMODEREQ_REQ_PDLP 0x00000003 -#define AUX_SYSIF_OPMODEREQ_REQ_PDA 0x00000002 -#define AUX_SYSIF_OPMODEREQ_REQ_LP 0x00000001 -#define AUX_SYSIF_OPMODEREQ_REQ_A 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_OPMODEACK -// -//***************************************************************************** -// Field: [1:0] ACK -// -// AUX operational mode acknowledgement. -// ENUMs: -// PDLP Powerdown operational mode with wakeup to lowpower -// mode is acknowledged. -// PDA Powerdown operational mode with wakeup to active -// mode is acknowledged. -// LP Lowpower operational mode is acknowledged. -// A Active operational mode is acknowledged. -#define AUX_SYSIF_OPMODEACK_ACK_W 2 -#define AUX_SYSIF_OPMODEACK_ACK_M 0x00000003 -#define AUX_SYSIF_OPMODEACK_ACK_S 0 -#define AUX_SYSIF_OPMODEACK_ACK_PDLP 0x00000003 -#define AUX_SYSIF_OPMODEACK_ACK_PDA 0x00000002 -#define AUX_SYSIF_OPMODEACK_ACK_LP 0x00000001 -#define AUX_SYSIF_OPMODEACK_ACK_A 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_PROGWU0CFG -// -//***************************************************************************** -// Field: [7] POL -// -// Polarity of WU_SRC. -// -// The procedure used to clear the wakeup flag decides level or edge -// sensitivity, see WUFLAGSCLR.PROG_WU0. -// ENUMs: -// LOW The wakeup flag is set when WU_SRC is low or goes -// low. -// HIGH The wakeup flag is set when WU_SRC is high or goes -// high. -#define AUX_SYSIF_PROGWU0CFG_POL 0x00000080 -#define AUX_SYSIF_PROGWU0CFG_POL_BITN 7 -#define AUX_SYSIF_PROGWU0CFG_POL_M 0x00000080 -#define AUX_SYSIF_PROGWU0CFG_POL_S 7 -#define AUX_SYSIF_PROGWU0CFG_POL_LOW 0x00000080 -#define AUX_SYSIF_PROGWU0CFG_POL_HIGH 0x00000000 - -// Field: [6] EN -// -// Programmable wakeup flag enable. -// -// 0: Disable wakeup flag. -// 1: Enable wakeup flag. -#define AUX_SYSIF_PROGWU0CFG_EN 0x00000040 -#define AUX_SYSIF_PROGWU0CFG_EN_BITN 6 -#define AUX_SYSIF_PROGWU0CFG_EN_M 0x00000040 -#define AUX_SYSIF_PROGWU0CFG_EN_S 6 - -// Field: [5:0] WU_SRC -// -// Wakeup source from the asynchronous AUX event bus. -// -// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU0 is 1. -// -// If you write a non-enumerated value the behavior is identical to NO_EVENT. -// The written value is returned when read. -// ENUMs: -// NO_EVENT No event. -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_W 6 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_M 0x0000003F -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_S 0 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_NO_EVENT 0x0000003F -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ADC_DONE 0x00000039 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TDC_DONE 0x00000037 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPB 0x0000002F -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUX_COMPA 0x0000002E -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX1 0x0000002D -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_OBSMUX0 0x0000002C -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_EV 0x0000002B -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_ACLK_REF 0x0000002A -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_VDDR_RECHARGE 0x00000029 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MCU_ACTIVE 0x00000028 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_PWR_DWN 0x00000027 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_SCLK_LF 0x00000026 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AON_RTC_CH2 0x00000021 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_MANUAL_EV 0x00000020 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO31 0x0000001F -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO30 0x0000001E -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO29 0x0000001D -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO28 0x0000001C -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO27 0x0000001B -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO26 0x0000001A -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO25 0x00000019 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO24 0x00000018 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO23 0x00000017 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO22 0x00000016 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO21 0x00000015 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO20 0x00000014 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO19 0x00000013 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO18 0x00000012 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO17 0x00000011 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO16 0x00000010 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO15 0x0000000F -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO14 0x0000000E -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO13 0x0000000D -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO12 0x0000000C -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO11 0x0000000B -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO10 0x0000000A -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO9 0x00000009 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO8 0x00000008 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO7 0x00000007 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO6 0x00000006 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO5 0x00000005 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO4 0x00000004 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO3 0x00000003 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO2 0x00000002 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO1 0x00000001 -#define AUX_SYSIF_PROGWU0CFG_WU_SRC_AUXIO0 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_PROGWU1CFG -// -//***************************************************************************** -// Field: [7] POL -// -// Polarity of WU_SRC. -// -// The procedure used to clear the wakeup flag decides level or edge -// sensitivity, see WUFLAGSCLR.PROG_WU1. -// ENUMs: -// LOW The wakeup flag is set when WU_SRC is low or goes -// low. -// HIGH The wakeup flag is set when WU_SRC is high or goes -// high. -#define AUX_SYSIF_PROGWU1CFG_POL 0x00000080 -#define AUX_SYSIF_PROGWU1CFG_POL_BITN 7 -#define AUX_SYSIF_PROGWU1CFG_POL_M 0x00000080 -#define AUX_SYSIF_PROGWU1CFG_POL_S 7 -#define AUX_SYSIF_PROGWU1CFG_POL_LOW 0x00000080 -#define AUX_SYSIF_PROGWU1CFG_POL_HIGH 0x00000000 - -// Field: [6] EN -// -// Programmable wakeup flag enable. -// -// 0: Disable wakeup flag. -// 1: Enable wakeup flag. -#define AUX_SYSIF_PROGWU1CFG_EN 0x00000040 -#define AUX_SYSIF_PROGWU1CFG_EN_BITN 6 -#define AUX_SYSIF_PROGWU1CFG_EN_M 0x00000040 -#define AUX_SYSIF_PROGWU1CFG_EN_S 6 - -// Field: [5:0] WU_SRC -// -// Wakeup source from the asynchronous AUX event bus. -// -// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU1 is 1. -// -// If you write a non-enumerated value the behavior is identical to NO_EVENT. -// The written value is returned when read. -// ENUMs: -// NO_EVENT No event. -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_W 6 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_M 0x0000003F -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_S 0 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_NO_EVENT 0x0000003F -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ADC_DONE 0x00000039 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TDC_DONE 0x00000037 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPB 0x0000002F -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUX_COMPA 0x0000002E -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX1 0x0000002D -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_OBSMUX0 0x0000002C -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_EV 0x0000002B -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_ACLK_REF 0x0000002A -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_VDDR_RECHARGE 0x00000029 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MCU_ACTIVE 0x00000028 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_PWR_DWN 0x00000027 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_SCLK_LF 0x00000026 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AON_RTC_CH2 0x00000021 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_MANUAL_EV 0x00000020 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO31 0x0000001F -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO30 0x0000001E -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO29 0x0000001D -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO28 0x0000001C -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO27 0x0000001B -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO26 0x0000001A -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO25 0x00000019 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO24 0x00000018 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO23 0x00000017 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO22 0x00000016 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO21 0x00000015 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO20 0x00000014 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO19 0x00000013 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO18 0x00000012 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO17 0x00000011 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO16 0x00000010 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO15 0x0000000F -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO14 0x0000000E -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO13 0x0000000D -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO12 0x0000000C -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO11 0x0000000B -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO10 0x0000000A -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO9 0x00000009 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO8 0x00000008 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO7 0x00000007 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO6 0x00000006 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO5 0x00000005 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO4 0x00000004 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO3 0x00000003 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO2 0x00000002 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO1 0x00000001 -#define AUX_SYSIF_PROGWU1CFG_WU_SRC_AUXIO0 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_PROGWU2CFG -// -//***************************************************************************** -// Field: [7] POL -// -// Polarity of WU_SRC. -// -// The procedure used to clear the wakeup flag decides level or edge -// sensitivity, see WUFLAGSCLR.PROG_WU2. -// ENUMs: -// LOW The wakeup flag is set when WU_SRC is low or goes -// low. -// HIGH The wakeup flag is set when WU_SRC is high or goes -// high. -#define AUX_SYSIF_PROGWU2CFG_POL 0x00000080 -#define AUX_SYSIF_PROGWU2CFG_POL_BITN 7 -#define AUX_SYSIF_PROGWU2CFG_POL_M 0x00000080 -#define AUX_SYSIF_PROGWU2CFG_POL_S 7 -#define AUX_SYSIF_PROGWU2CFG_POL_LOW 0x00000080 -#define AUX_SYSIF_PROGWU2CFG_POL_HIGH 0x00000000 - -// Field: [6] EN -// -// Programmable wakeup flag enable. -// -// 0: Disable wakeup flag. -// 1: Enable wakeup flag. -#define AUX_SYSIF_PROGWU2CFG_EN 0x00000040 -#define AUX_SYSIF_PROGWU2CFG_EN_BITN 6 -#define AUX_SYSIF_PROGWU2CFG_EN_M 0x00000040 -#define AUX_SYSIF_PROGWU2CFG_EN_S 6 - -// Field: [5:0] WU_SRC -// -// Wakeup source from the asynchronous AUX event bus. -// -// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU2 is 1. -// -// If you write a non-enumerated value the behavior is identical to NO_EVENT. -// The written value is returned when read. -// ENUMs: -// NO_EVENT No event. -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_W 6 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_M 0x0000003F -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_S 0 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_NO_EVENT 0x0000003F -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ADC_DONE 0x00000039 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TDC_DONE 0x00000037 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPB 0x0000002F -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUX_COMPA 0x0000002E -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX1 0x0000002D -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_OBSMUX0 0x0000002C -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_EV 0x0000002B -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_ACLK_REF 0x0000002A -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_VDDR_RECHARGE 0x00000029 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MCU_ACTIVE 0x00000028 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_PWR_DWN 0x00000027 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_SCLK_LF 0x00000026 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AON_RTC_CH2 0x00000021 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_MANUAL_EV 0x00000020 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO31 0x0000001F -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO30 0x0000001E -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO29 0x0000001D -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO28 0x0000001C -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO27 0x0000001B -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO26 0x0000001A -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO25 0x00000019 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO24 0x00000018 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO23 0x00000017 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO22 0x00000016 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO21 0x00000015 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO20 0x00000014 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO19 0x00000013 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO18 0x00000012 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO17 0x00000011 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO16 0x00000010 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO15 0x0000000F -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO14 0x0000000E -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO13 0x0000000D -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO12 0x0000000C -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO11 0x0000000B -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO10 0x0000000A -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO9 0x00000009 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO8 0x00000008 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO7 0x00000007 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO6 0x00000006 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO5 0x00000005 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO4 0x00000004 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO3 0x00000003 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO2 0x00000002 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO1 0x00000001 -#define AUX_SYSIF_PROGWU2CFG_WU_SRC_AUXIO0 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_PROGWU3CFG -// -//***************************************************************************** -// Field: [7] POL -// -// Polarity of WU_SRC. -// -// The procedure used to clear the wakeup flag decides level or edge -// sensitivity, see WUFLAGSCLR.PROG_WU3. -// ENUMs: -// LOW The wakeup flag is set when WU_SRC is low or goes -// low. -// HIGH The wakeup flag is set when WU_SRC is high or goes -// high. -#define AUX_SYSIF_PROGWU3CFG_POL 0x00000080 -#define AUX_SYSIF_PROGWU3CFG_POL_BITN 7 -#define AUX_SYSIF_PROGWU3CFG_POL_M 0x00000080 -#define AUX_SYSIF_PROGWU3CFG_POL_S 7 -#define AUX_SYSIF_PROGWU3CFG_POL_LOW 0x00000080 -#define AUX_SYSIF_PROGWU3CFG_POL_HIGH 0x00000000 - -// Field: [6] EN -// -// Programmable wakeup flag enable. -// -// 0: Disable wakeup flag. -// 1: Enable wakeup flag. -#define AUX_SYSIF_PROGWU3CFG_EN 0x00000040 -#define AUX_SYSIF_PROGWU3CFG_EN_BITN 6 -#define AUX_SYSIF_PROGWU3CFG_EN_M 0x00000040 -#define AUX_SYSIF_PROGWU3CFG_EN_S 6 - -// Field: [5:0] WU_SRC -// -// Wakeup source from the asynchronous AUX event bus. -// -// Only change WU_SRC when EN is 0 or WUFLAGSCLR.PROG_WU3 is 1. -// -// If you write a non-enumerated value the behavior is identical to NO_EVENT. -// The written value is returned when read. -// ENUMs: -// NO_EVENT No event. -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_W 6 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_M 0x0000003F -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_S 0 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_NO_EVENT 0x0000003F -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_IRQ 0x0000003A -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ADC_DONE 0x00000039 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_ISRC_RESET_N 0x00000038 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TDC_DONE 0x00000037 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER0_EV 0x00000036 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER1_EV 0x00000035 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_PULSE 0x00000034 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV3 0x00000033 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV2 0x00000032 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV1 0x00000031 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_TIMER2_EV0 0x00000030 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPB 0x0000002F -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUX_COMPA 0x0000002E -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX1 0x0000002D -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_OBSMUX0 0x0000002C -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_EV 0x0000002B -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_ACLK_REF 0x0000002A -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_VDDR_RECHARGE 0x00000029 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MCU_ACTIVE 0x00000028 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_PWR_DWN 0x00000027 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_SCLK_LF 0x00000026 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_4KHZ 0x00000023 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2_DLY 0x00000022 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AON_RTC_CH2 0x00000021 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_MANUAL_EV 0x00000020 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO31 0x0000001F -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO30 0x0000001E -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO29 0x0000001D -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO28 0x0000001C -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO27 0x0000001B -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO26 0x0000001A -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO25 0x00000019 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO24 0x00000018 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO23 0x00000017 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO22 0x00000016 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO21 0x00000015 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO20 0x00000014 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO19 0x00000013 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO18 0x00000012 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO17 0x00000011 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO16 0x00000010 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO15 0x0000000F -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO14 0x0000000E -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO13 0x0000000D -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO12 0x0000000C -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO11 0x0000000B -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO10 0x0000000A -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO9 0x00000009 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO8 0x00000008 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO7 0x00000007 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO6 0x00000006 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO5 0x00000005 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO4 0x00000004 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO3 0x00000003 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO2 0x00000002 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO1 0x00000001 -#define AUX_SYSIF_PROGWU3CFG_WU_SRC_AUXIO0 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_SWWUTRIG -// -//***************************************************************************** -// Field: [3] SW_WU3 -// -// Software wakeup 3 trigger. -// -// 0: No effect. -// 1: Set WUFLAGS.SW_WU3 and trigger AUX wakeup. -#define AUX_SYSIF_SWWUTRIG_SW_WU3 0x00000008 -#define AUX_SYSIF_SWWUTRIG_SW_WU3_BITN 3 -#define AUX_SYSIF_SWWUTRIG_SW_WU3_M 0x00000008 -#define AUX_SYSIF_SWWUTRIG_SW_WU3_S 3 - -// Field: [2] SW_WU2 -// -// Software wakeup 2 trigger. -// -// 0: No effect. -// 1: Set WUFLAGS.SW_WU2 and trigger AUX wakeup. -#define AUX_SYSIF_SWWUTRIG_SW_WU2 0x00000004 -#define AUX_SYSIF_SWWUTRIG_SW_WU2_BITN 2 -#define AUX_SYSIF_SWWUTRIG_SW_WU2_M 0x00000004 -#define AUX_SYSIF_SWWUTRIG_SW_WU2_S 2 - -// Field: [1] SW_WU1 -// -// Software wakeup 1 trigger. -// -// 0: No effect. -// 1: Set WUFLAGS.SW_WU1 and trigger AUX wakeup. -#define AUX_SYSIF_SWWUTRIG_SW_WU1 0x00000002 -#define AUX_SYSIF_SWWUTRIG_SW_WU1_BITN 1 -#define AUX_SYSIF_SWWUTRIG_SW_WU1_M 0x00000002 -#define AUX_SYSIF_SWWUTRIG_SW_WU1_S 1 - -// Field: [0] SW_WU0 -// -// Software wakeup 0 trigger. -// -// 0: No effect. -// 1: Set WUFLAGS.SW_WU0 and trigger AUX wakeup. -#define AUX_SYSIF_SWWUTRIG_SW_WU0 0x00000001 -#define AUX_SYSIF_SWWUTRIG_SW_WU0_BITN 0 -#define AUX_SYSIF_SWWUTRIG_SW_WU0_M 0x00000001 -#define AUX_SYSIF_SWWUTRIG_SW_WU0_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_WUFLAGS -// -//***************************************************************************** -// Field: [7] SW_WU3 -// -// Software wakeup 3 flag. -// -// 0: Software wakeup 3 not triggered. -// 1: Software wakeup 3 triggered. -#define AUX_SYSIF_WUFLAGS_SW_WU3 0x00000080 -#define AUX_SYSIF_WUFLAGS_SW_WU3_BITN 7 -#define AUX_SYSIF_WUFLAGS_SW_WU3_M 0x00000080 -#define AUX_SYSIF_WUFLAGS_SW_WU3_S 7 - -// Field: [6] SW_WU2 -// -// Software wakeup 2 flag. -// -// 0: Software wakeup 2 not triggered. -// 1: Software wakeup 2 triggered. -#define AUX_SYSIF_WUFLAGS_SW_WU2 0x00000040 -#define AUX_SYSIF_WUFLAGS_SW_WU2_BITN 6 -#define AUX_SYSIF_WUFLAGS_SW_WU2_M 0x00000040 -#define AUX_SYSIF_WUFLAGS_SW_WU2_S 6 - -// Field: [5] SW_WU1 -// -// Software wakeup 1 flag. -// -// 0: Software wakeup 1 not triggered. -// 1: Software wakeup 1 triggered. -#define AUX_SYSIF_WUFLAGS_SW_WU1 0x00000020 -#define AUX_SYSIF_WUFLAGS_SW_WU1_BITN 5 -#define AUX_SYSIF_WUFLAGS_SW_WU1_M 0x00000020 -#define AUX_SYSIF_WUFLAGS_SW_WU1_S 5 - -// Field: [4] SW_WU0 -// -// Software wakeup 0 flag. -// -// 0: Software wakeup 0 not triggered. -// 1: Software wakeup 0 triggered. -#define AUX_SYSIF_WUFLAGS_SW_WU0 0x00000010 -#define AUX_SYSIF_WUFLAGS_SW_WU0_BITN 4 -#define AUX_SYSIF_WUFLAGS_SW_WU0_M 0x00000010 -#define AUX_SYSIF_WUFLAGS_SW_WU0_S 4 - -// Field: [3] PROG_WU3 -// -// Programmable wakeup 3. -// -// 0: Programmable wakeup 3 not triggered. -// 1: Programmable wakeup 3 triggered. -#define AUX_SYSIF_WUFLAGS_PROG_WU3 0x00000008 -#define AUX_SYSIF_WUFLAGS_PROG_WU3_BITN 3 -#define AUX_SYSIF_WUFLAGS_PROG_WU3_M 0x00000008 -#define AUX_SYSIF_WUFLAGS_PROG_WU3_S 3 - -// Field: [2] PROG_WU2 -// -// Programmable wakeup 2. -// -// 0: Programmable wakeup 2 not triggered. -// 1: Programmable wakeup 2 triggered. -#define AUX_SYSIF_WUFLAGS_PROG_WU2 0x00000004 -#define AUX_SYSIF_WUFLAGS_PROG_WU2_BITN 2 -#define AUX_SYSIF_WUFLAGS_PROG_WU2_M 0x00000004 -#define AUX_SYSIF_WUFLAGS_PROG_WU2_S 2 - -// Field: [1] PROG_WU1 -// -// Programmable wakeup 1. -// -// 0: Programmable wakeup 1 not triggered. -// 1: Programmable wakeup 1 triggered. -#define AUX_SYSIF_WUFLAGS_PROG_WU1 0x00000002 -#define AUX_SYSIF_WUFLAGS_PROG_WU1_BITN 1 -#define AUX_SYSIF_WUFLAGS_PROG_WU1_M 0x00000002 -#define AUX_SYSIF_WUFLAGS_PROG_WU1_S 1 - -// Field: [0] PROG_WU0 -// -// Programmable wakeup 0. -// -// 0: Programmable wakeup 0 not triggered. -// 1: Programmable wakeup 0 triggered. -#define AUX_SYSIF_WUFLAGS_PROG_WU0 0x00000001 -#define AUX_SYSIF_WUFLAGS_PROG_WU0_BITN 0 -#define AUX_SYSIF_WUFLAGS_PROG_WU0_M 0x00000001 -#define AUX_SYSIF_WUFLAGS_PROG_WU0_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_WUFLAGSCLR -// -//***************************************************************************** -// Field: [7] SW_WU3 -// -// Clear software wakeup flag 3. -// -// 0: No effect. -// 1: Clear WUFLAGS.SW_WU3. Keep high until WUFLAGS.SW_WU3 is 0. -#define AUX_SYSIF_WUFLAGSCLR_SW_WU3 0x00000080 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_BITN 7 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_M 0x00000080 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU3_S 7 - -// Field: [6] SW_WU2 -// -// Clear software wakeup flag 2. -// -// 0: No effect. -// 1: Clear WUFLAGS.SW_WU2. Keep high until WUFLAGS.SW_WU2 is 0. -#define AUX_SYSIF_WUFLAGSCLR_SW_WU2 0x00000040 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_BITN 6 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_M 0x00000040 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU2_S 6 - -// Field: [5] SW_WU1 -// -// Clear software wakeup flag 1. -// -// 0: No effect. -// 1: Clear WUFLAGS.SW_WU1. Keep high until WUFLAGS.SW_WU1 is 0. -#define AUX_SYSIF_WUFLAGSCLR_SW_WU1 0x00000020 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_BITN 5 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_M 0x00000020 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU1_S 5 - -// Field: [4] SW_WU0 -// -// Clear software wakeup flag 0. -// -// 0: No effect. -// 1: Clear WUFLAGS.SW_WU0. Keep high until WUFLAGS.SW_WU0 is 0. -#define AUX_SYSIF_WUFLAGSCLR_SW_WU0 0x00000010 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_BITN 4 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_M 0x00000010 -#define AUX_SYSIF_WUFLAGSCLR_SW_WU0_S 4 - -// Field: [3] PROG_WU3 -// -// Programmable wakeup flag 3. -// -// 0: No effect. -// 1: Clear WUFLAGS.PROG_WU3. Keep high until WUFLAGS.PROG_WU3 is 0. -// -// The wakeup flag becomes edge sensitive if you write PROG_WU3 to 0 when -// PROGWU3CFG.EN is 1. -// The wakeup flag becomes level sensitive if you write PROG_WU3 to 0 when -// PROGWU3CFG.EN is 0, then set PROGWU3CFG.EN. -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3 0x00000008 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_BITN 3 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_M 0x00000008 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU3_S 3 - -// Field: [2] PROG_WU2 -// -// Programmable wakeup flag 2. -// -// 0: No effect. -// 1: Clear WUFLAGS.PROG_WU2. Keep high until WUFLAGS.PROG_WU2 is 0. -// -// The wakeup flag becomes edge sensitive if you write PROG_WU2 to 0 when -// PROGWU2CFG.EN is 1. -// The wakeup flag becomes level sensitive if you write PROG_WU2 to 0 when -// PROGWU2CFG.EN is 0, then set PROGWU2CFG.EN. -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2 0x00000004 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_BITN 2 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_M 0x00000004 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU2_S 2 - -// Field: [1] PROG_WU1 -// -// Programmable wakeup flag 1. -// -// 0: No effect. -// 1: Clear WUFLAGS.PROG_WU1. Keep high until WUFLAGS.PROG_WU1 is 0. -// -// The wakeup flag becomes edge sensitive if you write PROG_WU1 to 0 when -// PROGWU1CFG.EN is 1. -// The wakeup flag becomes level sensitive if you write PROG_WU1 to 0 when -// PROGWU1CFG.EN is 0, then set PROGWU1CFG.EN. -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1 0x00000002 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_BITN 1 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_M 0x00000002 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU1_S 1 - -// Field: [0] PROG_WU0 -// -// Programmable wakeup flag 0. -// -// 0: No effect. -// 1: Clear WUFLAGS.PROG_WU0. Keep high until WUFLAGS.PROG_WU0 is 0. -// -// The wakeup flag becomes edge sensitive if you write PROG_WU0 to 0 when -// PROGWU0CFG.EN is 1. -// The wakeup flag becomes level sensitive if you write PROG_WU0 to 0 when -// PROGWU0CFG.EN is 0, then set PROGWU0CFG.EN. -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0 0x00000001 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_BITN 0 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_M 0x00000001 -#define AUX_SYSIF_WUFLAGSCLR_PROG_WU0_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_WUGATE -// -//***************************************************************************** -// Field: [0] EN -// -// Wakeup output enable. -// -// 0: Disable AUX wakeup output. -// 1: Enable AUX wakeup output. -#define AUX_SYSIF_WUGATE_EN 0x00000001 -#define AUX_SYSIF_WUGATE_EN_BITN 0 -#define AUX_SYSIF_WUGATE_EN_M 0x00000001 -#define AUX_SYSIF_WUGATE_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_VECCFG0 -// -//***************************************************************************** -// Field: [3:0] VEC_EV -// -// Select trigger event for vector 0. -// -// Non-enumerated values are treated as NONE. -// ENUMs: -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// SW_WU3 WUFLAGS.SW_WU3 -// SW_WU2 WUFLAGS.SW_WU2 -// SW_WU1 WUFLAGS.SW_WU1 -// SW_WU0 WUFLAGS.SW_WU0 -// PROG_WU3 WUFLAGS.PROG_WU3 -// PROG_WU2 WUFLAGS.PROG_WU2 -// PROG_WU1 WUFLAGS.PROG_WU1 -// PROG_WU0 WUFLAGS.PROG_WU0 -// NONE Vector is disabled. -#define AUX_SYSIF_VECCFG0_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG0_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG0_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG0_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG0_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG0_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG0_VEC_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_VECCFG1 -// -//***************************************************************************** -// Field: [3:0] VEC_EV -// -// Select trigger event for vector 1. -// -// Non-enumerated values are treated as NONE. -// ENUMs: -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// SW_WU3 WUFLAGS.SW_WU3 -// SW_WU2 WUFLAGS.SW_WU2 -// SW_WU1 WUFLAGS.SW_WU1 -// SW_WU0 WUFLAGS.SW_WU0 -// PROG_WU3 WUFLAGS.PROG_WU3 -// PROG_WU2 WUFLAGS.PROG_WU2 -// PROG_WU1 WUFLAGS.PROG_WU1 -// PROG_WU0 WUFLAGS.PROG_WU0 -// NONE Vector is disabled. -#define AUX_SYSIF_VECCFG1_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG1_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG1_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG1_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG1_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG1_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG1_VEC_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_VECCFG2 -// -//***************************************************************************** -// Field: [3:0] VEC_EV -// -// Select trigger event for vector 2. -// -// Non-enumerated values are treated as NONE. -// ENUMs: -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// SW_WU3 WUFLAGS.SW_WU3 -// SW_WU2 WUFLAGS.SW_WU2 -// SW_WU1 WUFLAGS.SW_WU1 -// SW_WU0 WUFLAGS.SW_WU0 -// PROG_WU3 WUFLAGS.PROG_WU3 -// PROG_WU2 WUFLAGS.PROG_WU2 -// PROG_WU1 WUFLAGS.PROG_WU1 -// PROG_WU0 WUFLAGS.PROG_WU0 -// NONE Vector is disabled. -#define AUX_SYSIF_VECCFG2_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG2_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG2_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG2_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG2_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG2_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG2_VEC_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_VECCFG3 -// -//***************************************************************************** -// Field: [3:0] VEC_EV -// -// Select trigger event for vector 3. -// -// Non-enumerated values are treated as NONE. -// ENUMs: -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// SW_WU3 WUFLAGS.SW_WU3 -// SW_WU2 WUFLAGS.SW_WU2 -// SW_WU1 WUFLAGS.SW_WU1 -// SW_WU0 WUFLAGS.SW_WU0 -// PROG_WU3 WUFLAGS.PROG_WU3 -// PROG_WU2 WUFLAGS.PROG_WU2 -// PROG_WU1 WUFLAGS.PROG_WU1 -// PROG_WU0 WUFLAGS.PROG_WU0 -// NONE Vector is disabled. -#define AUX_SYSIF_VECCFG3_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG3_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG3_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG3_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG3_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG3_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG3_VEC_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_VECCFG4 -// -//***************************************************************************** -// Field: [3:0] VEC_EV -// -// Select trigger event for vector 4. -// -// Non-enumerated values are treated as NONE. -// ENUMs: -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// SW_WU3 WUFLAGS.SW_WU3 -// SW_WU2 WUFLAGS.SW_WU2 -// SW_WU1 WUFLAGS.SW_WU1 -// SW_WU0 WUFLAGS.SW_WU0 -// PROG_WU3 WUFLAGS.PROG_WU3 -// PROG_WU2 WUFLAGS.PROG_WU2 -// PROG_WU1 WUFLAGS.PROG_WU1 -// PROG_WU0 WUFLAGS.PROG_WU0 -// NONE Vector is disabled. -#define AUX_SYSIF_VECCFG4_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG4_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG4_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG4_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG4_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG4_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG4_VEC_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_VECCFG5 -// -//***************************************************************************** -// Field: [3:0] VEC_EV -// -// Select trigger event for vector 5. -// -// Non-enumerated values are treated as NONE. -// ENUMs: -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// SW_WU3 WUFLAGS.SW_WU3 -// SW_WU2 WUFLAGS.SW_WU2 -// SW_WU1 WUFLAGS.SW_WU1 -// SW_WU0 WUFLAGS.SW_WU0 -// PROG_WU3 WUFLAGS.PROG_WU3 -// PROG_WU2 WUFLAGS.PROG_WU2 -// PROG_WU1 WUFLAGS.PROG_WU1 -// PROG_WU0 WUFLAGS.PROG_WU0 -// NONE Vector is disabled. -#define AUX_SYSIF_VECCFG5_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG5_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG5_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG5_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG5_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG5_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG5_VEC_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_VECCFG6 -// -//***************************************************************************** -// Field: [3:0] VEC_EV -// -// Select trigger event for vector 6. -// -// Non-enumerated values are treated as NONE. -// ENUMs: -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// SW_WU3 WUFLAGS.SW_WU3 -// SW_WU2 WUFLAGS.SW_WU2 -// SW_WU1 WUFLAGS.SW_WU1 -// SW_WU0 WUFLAGS.SW_WU0 -// PROG_WU3 WUFLAGS.PROG_WU3 -// PROG_WU2 WUFLAGS.PROG_WU2 -// PROG_WU1 WUFLAGS.PROG_WU1 -// PROG_WU0 WUFLAGS.PROG_WU0 -// NONE Vector is disabled. -#define AUX_SYSIF_VECCFG6_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG6_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG6_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG6_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG6_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG6_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG6_VEC_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_VECCFG7 -// -//***************************************************************************** -// Field: [3:0] VEC_EV -// -// Select trigger event for vector 7. -// -// Non-enumerated values are treated as NONE. -// ENUMs: -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// SW_WU3 WUFLAGS.SW_WU3 -// SW_WU2 WUFLAGS.SW_WU2 -// SW_WU1 WUFLAGS.SW_WU1 -// SW_WU0 WUFLAGS.SW_WU0 -// PROG_WU3 WUFLAGS.PROG_WU3 -// PROG_WU2 WUFLAGS.PROG_WU2 -// PROG_WU1 WUFLAGS.PROG_WU1 -// PROG_WU0 WUFLAGS.PROG_WU0 -// NONE Vector is disabled. -#define AUX_SYSIF_VECCFG7_VEC_EV_W 4 -#define AUX_SYSIF_VECCFG7_VEC_EV_M 0x0000000F -#define AUX_SYSIF_VECCFG7_VEC_EV_S 0 -#define AUX_SYSIF_VECCFG7_VEC_EV_AON_RTC_CH2_DLY 0x00000009 -#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU3 0x00000008 -#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU2 0x00000007 -#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU1 0x00000006 -#define AUX_SYSIF_VECCFG7_VEC_EV_SW_WU0 0x00000005 -#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU3 0x00000004 -#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU2 0x00000003 -#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU1 0x00000002 -#define AUX_SYSIF_VECCFG7_VEC_EV_PROG_WU0 0x00000001 -#define AUX_SYSIF_VECCFG7_VEC_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_EVSYNCRATE -// -//***************************************************************************** -// Field: [2] AUX_COMPA_SYNC_RATE -// -// Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPA event. -// ENUMs: -// BUS_RATE AUX bus rate -// SCE_RATE SCE rate -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE 0x00000004 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BITN 2 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_M 0x00000004 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_S 2 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_BUS_RATE 0x00000004 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPA_SYNC_RATE_SCE_RATE 0x00000000 - -// Field: [1] AUX_COMPB_SYNC_RATE -// -// Select synchronization rate for AUX_EVCTL:EVSTAT2.AUX_COMPB event. -// ENUMs: -// BUS_RATE AUX bus rate -// SCE_RATE SCE rate -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE 0x00000002 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BITN 1 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_M 0x00000002 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_S 1 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_BUS_RATE 0x00000002 -#define AUX_SYSIF_EVSYNCRATE_AUX_COMPB_SYNC_RATE_SCE_RATE 0x00000000 - -// Field: [0] AUX_TIMER2_SYNC_RATE -// -// Select synchronization rate for: -// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// - AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE -// ENUMs: -// BUS_RATE AUX bus rate -// SCE_RATE SCE rate -#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE 0x00000001 -#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BITN 0 -#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_M 0x00000001 -#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_S 0 -#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_BUS_RATE 0x00000001 -#define AUX_SYSIF_EVSYNCRATE_AUX_TIMER2_SYNC_RATE_SCE_RATE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_PEROPRATE -// -//***************************************************************************** -// Field: [3] ANAIF_DAC_OP_RATE -// -// Select operational rate for AUX_ANAIF DAC sample clock state machine. -// ENUMs: -// BUS_RATE AUX bus rate -// SCE_RATE SCE rate -#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE 0x00000008 -#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BITN 3 -#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_M 0x00000008 -#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_S 3 -#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_BUS_RATE 0x00000008 -#define AUX_SYSIF_PEROPRATE_ANAIF_DAC_OP_RATE_SCE_RATE 0x00000000 - -// Field: [2] TIMER01_OP_RATE -// -// Select operational rate for AUX_TIMER01. -// ENUMs: -// BUS_RATE AUX bus rate -// SCE_RATE SCE rate -#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE 0x00000004 -#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BITN 2 -#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_M 0x00000004 -#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_S 2 -#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_BUS_RATE 0x00000004 -#define AUX_SYSIF_PEROPRATE_TIMER01_OP_RATE_SCE_RATE 0x00000000 - -// Field: [1] SPIM_OP_RATE -// -// Select operational rate for AUX_SPIM. -// ENUMs: -// BUS_RATE AUX bus rate -// SCE_RATE SCE rate -#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE 0x00000002 -#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BITN 1 -#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_M 0x00000002 -#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_S 1 -#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_BUS_RATE 0x00000002 -#define AUX_SYSIF_PEROPRATE_SPIM_OP_RATE_SCE_RATE 0x00000000 - -// Field: [0] MAC_OP_RATE -// -// Select operational rate for AUX_MAC. -// ENUMs: -// BUS_RATE AUX bus rate -// SCE_RATE SCE rate -#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE 0x00000001 -#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BITN 0 -#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_M 0x00000001 -#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_S 0 -#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_BUS_RATE 0x00000001 -#define AUX_SYSIF_PEROPRATE_MAC_OP_RATE_SCE_RATE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_ADCCLKCTL -// -//***************************************************************************** -// Field: [1] ACK -// -// Clock acknowledgement. -// -// 0: ADC clock is disabled. -// 1: ADC clock is enabled. -#define AUX_SYSIF_ADCCLKCTL_ACK 0x00000002 -#define AUX_SYSIF_ADCCLKCTL_ACK_BITN 1 -#define AUX_SYSIF_ADCCLKCTL_ACK_M 0x00000002 -#define AUX_SYSIF_ADCCLKCTL_ACK_S 1 - -// Field: [0] REQ -// -// ADC clock request. -// -// 0: Disable ADC clock. -// 1: Enable ADC clock. -// -// Only modify REQ when equal to ACK. -#define AUX_SYSIF_ADCCLKCTL_REQ 0x00000001 -#define AUX_SYSIF_ADCCLKCTL_REQ_BITN 0 -#define AUX_SYSIF_ADCCLKCTL_REQ_M 0x00000001 -#define AUX_SYSIF_ADCCLKCTL_REQ_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_TDCCLKCTL -// -//***************************************************************************** -// Field: [1] ACK -// -// TDC counter clock acknowledgement. -// -// 0: TDC counter clock is disabled. -// 1: TDC counter clock is enabled. -#define AUX_SYSIF_TDCCLKCTL_ACK 0x00000002 -#define AUX_SYSIF_TDCCLKCTL_ACK_BITN 1 -#define AUX_SYSIF_TDCCLKCTL_ACK_M 0x00000002 -#define AUX_SYSIF_TDCCLKCTL_ACK_S 1 - -// Field: [0] REQ -// -// TDC counter clock request. -// -// 0: Disable TDC counter clock. -// 1: Enable TDC counter clock. -// -// Only modify REQ when equal to ACK. -#define AUX_SYSIF_TDCCLKCTL_REQ 0x00000001 -#define AUX_SYSIF_TDCCLKCTL_REQ_BITN 0 -#define AUX_SYSIF_TDCCLKCTL_REQ_M 0x00000001 -#define AUX_SYSIF_TDCCLKCTL_REQ_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_TDCREFCLKCTL -// -//***************************************************************************** -// Field: [1] ACK -// -// TDC reference clock acknowledgement. -// -// 0: TDC reference clock is disabled. -// 1: TDC reference clock is enabled. -#define AUX_SYSIF_TDCREFCLKCTL_ACK 0x00000002 -#define AUX_SYSIF_TDCREFCLKCTL_ACK_BITN 1 -#define AUX_SYSIF_TDCREFCLKCTL_ACK_M 0x00000002 -#define AUX_SYSIF_TDCREFCLKCTL_ACK_S 1 - -// Field: [0] REQ -// -// TDC reference clock request. -// -// 0: Disable TDC reference clock. -// 1: Enable TDC reference clock. -// -// Only modify REQ when equal to ACK. -#define AUX_SYSIF_TDCREFCLKCTL_REQ 0x00000001 -#define AUX_SYSIF_TDCREFCLKCTL_REQ_BITN 0 -#define AUX_SYSIF_TDCREFCLKCTL_REQ_M 0x00000001 -#define AUX_SYSIF_TDCREFCLKCTL_REQ_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_TIMER2CLKCTL -// -//***************************************************************************** -// Field: [2:0] SRC -// -// Select clock source for AUX_TIMER2. -// -// Update is only accepted if SRC equals TIMER2CLKSTAT.STAT or -// TIMER2CLKSWITCH.RDY is 1. -// -// It is recommended to select NONE only when TIMER2BRIDGE.BUSY is 0. -// -// A non-enumerated value is ignored. -// ENUMs: -// SCLK_HFDIV2 SCLK_HF / 2 -// SCLK_MF SCLK_MF -// SCLK_LF SCLK_LF -// NONE no clock -#define AUX_SYSIF_TIMER2CLKCTL_SRC_W 3 -#define AUX_SYSIF_TIMER2CLKCTL_SRC_M 0x00000007 -#define AUX_SYSIF_TIMER2CLKCTL_SRC_S 0 -#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_HFDIV2 0x00000004 -#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_MF 0x00000002 -#define AUX_SYSIF_TIMER2CLKCTL_SRC_SCLK_LF 0x00000001 -#define AUX_SYSIF_TIMER2CLKCTL_SRC_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_TIMER2CLKSTAT -// -//***************************************************************************** -// Field: [2:0] STAT -// -// AUX_TIMER2 clock source status. -// ENUMs: -// SCLK_HFDIV2 SCLK_HF / 2 -// SCLK_MF SCLK_MF -// SCLK_LF SCLK_LF -// NONE No clock -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_W 3 -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_M 0x00000007 -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_S 0 -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_HFDIV2 0x00000004 -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_MF 0x00000002 -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_SCLK_LF 0x00000001 -#define AUX_SYSIF_TIMER2CLKSTAT_STAT_NONE 0x00000000 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_TIMER2CLKSWITCH -// -//***************************************************************************** -// Field: [0] RDY -// -// Status of clock switcher. -// -// 0: TIMER2CLKCTL.SRC is different from TIMER2CLKSTAT.STAT. -// 1: TIMER2CLKCTL.SRC equals TIMER2CLKSTAT.STAT. -// -// RDY connects to AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY. -#define AUX_SYSIF_TIMER2CLKSWITCH_RDY 0x00000001 -#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_BITN 0 -#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_M 0x00000001 -#define AUX_SYSIF_TIMER2CLKSWITCH_RDY_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_TIMER2DBGCTL -// -//***************************************************************************** -// Field: [0] DBG_FREEZE_EN -// -// Debug freeze enable. -// -// 0: AUX_TIMER2 does not halt when the system CPU halts in debug mode. -// 1: Halt AUX_TIMER2 when the system CPU halts in debug mode. -#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN 0x00000001 -#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_BITN 0 -#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_M 0x00000001 -#define AUX_SYSIF_TIMER2DBGCTL_DBG_FREEZE_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_CLKSHIFTDET -// -//***************************************************************************** -// Field: [0] STAT -// -// Clock shift detection. -// -// Write: -// -// 0: Restart clock shift detection. -// 1: Do not use. -// -// Read: -// -// 0: MCU domain did not enter or exit active state since you wrote 0 to STAT. -// 1: MCU domain entered or exited active state since you wrote 0 to STAT. -#define AUX_SYSIF_CLKSHIFTDET_STAT 0x00000001 -#define AUX_SYSIF_CLKSHIFTDET_STAT_BITN 0 -#define AUX_SYSIF_CLKSHIFTDET_STAT_M 0x00000001 -#define AUX_SYSIF_CLKSHIFTDET_STAT_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_RECHARGETRIG -// -//***************************************************************************** -// Field: [0] TRIG -// -// Recharge trigger. -// -// 0: No effect. -// 1: Request VDDR recharge. -// -// Request VDDR recharge only when AUX_EVCTL:EVSTAT2.PWR_DWN is 1. -// -// Follow this sequence when OPMODEREQ.REQ is LP: -// - Set TRIG. -// - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 1. -// - Clear TRIG. -// - Wait until AUX_EVCTL:EVSTAT2.VDDR_RECHARGE is 0. -// -// Follow this sequence when OPMODEREQ.REQ is PDA or PDLP: -// - Set TRIG. -// - Clear TRIG. -#define AUX_SYSIF_RECHARGETRIG_TRIG 0x00000001 -#define AUX_SYSIF_RECHARGETRIG_TRIG_BITN 0 -#define AUX_SYSIF_RECHARGETRIG_TRIG_M 0x00000001 -#define AUX_SYSIF_RECHARGETRIG_TRIG_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_RECHARGEDET -// -//***************************************************************************** -// Field: [1] STAT -// -// VDDR recharge detector status. -// -// 0: No recharge of VDDR has occurred since EN was set. -// 1: Recharge of VDDR has occurred since EN was set. -#define AUX_SYSIF_RECHARGEDET_STAT 0x00000002 -#define AUX_SYSIF_RECHARGEDET_STAT_BITN 1 -#define AUX_SYSIF_RECHARGEDET_STAT_M 0x00000002 -#define AUX_SYSIF_RECHARGEDET_STAT_S 1 - -// Field: [0] EN -// -// VDDR recharge detector enable. -// -// 0: Disable recharge detection. STAT becomes zero. -// 1: Enable recharge detection. -#define AUX_SYSIF_RECHARGEDET_EN 0x00000001 -#define AUX_SYSIF_RECHARGEDET_EN_BITN 0 -#define AUX_SYSIF_RECHARGEDET_EN_M 0x00000001 -#define AUX_SYSIF_RECHARGEDET_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_RTCSUBSECINC0 -// -//***************************************************************************** -// Field: [15:0] INC15_0 -// -// New value for bits 15:0 in AON_RTC:SUBSECINC. -#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_W 16 -#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_M 0x0000FFFF -#define AUX_SYSIF_RTCSUBSECINC0_INC15_0_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_RTCSUBSECINC1 -// -//***************************************************************************** -// Field: [7:0] INC23_16 -// -// New value for bits 23:16 in AON_RTC:SUBSECINC. -#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_W 8 -#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_M 0x000000FF -#define AUX_SYSIF_RTCSUBSECINC1_INC23_16_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_RTCSUBSECINCCTL -// -//***************************************************************************** -// Field: [1] UPD_ACK -// -// Update acknowledgement. -// -// 0: AON_RTC has not acknowledged UPD_REQ. -// 1: AON_RTC has acknowledged UPD_REQ. -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK 0x00000002 -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_BITN 1 -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_M 0x00000002 -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_ACK_S 1 - -// Field: [0] UPD_REQ -// -// Request AON_RTC to update AON_RTC:SUBSECINC. -// -// 0: Clear request to update. -// 1: Set request to update. -// -// Only change UPD_REQ when it equals UPD_ACK. Clear UPD_REQ after UPD_ACK is -// 1. -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ 0x00000001 -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_BITN 0 -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_M 0x00000001 -#define AUX_SYSIF_RTCSUBSECINCCTL_UPD_REQ_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_RTCSEC -// -//***************************************************************************** -// Field: [15:0] SEC -// -// Bits 15:0 in AON_RTC:SEC.VALUE. -// -// Follow this procedure to get the correct value: -// - Do two dummy reads of SEC. -// - Then read SEC until two consecutive reads are equal. -#define AUX_SYSIF_RTCSEC_SEC_W 16 -#define AUX_SYSIF_RTCSEC_SEC_M 0x0000FFFF -#define AUX_SYSIF_RTCSEC_SEC_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_RTCSUBSEC -// -//***************************************************************************** -// Field: [15:0] SUBSEC -// -// Bits 31:16 in AON_RTC:SUBSEC.VALUE. -// -// Follow this procedure to get the correct value: -// - Do two dummy reads SUBSEC. -// - Then read SUBSEC until two consecutive reads are equal. -#define AUX_SYSIF_RTCSUBSEC_SUBSEC_W 16 -#define AUX_SYSIF_RTCSUBSEC_SUBSEC_M 0x0000FFFF -#define AUX_SYSIF_RTCSUBSEC_SUBSEC_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_RTCEVCLR -// -//***************************************************************************** -// Field: [0] RTC_CH2_EV_CLR -// -// Clear events from AON_RTC channel 2. -// -// 0: No effect. -// 1: Clear events from AON_RTC channel 2. -// -// Keep RTC_CH2_EV_CLR high until AUX_EVCTL:EVSTAT2.AON_RTC_CH2 and -// AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY are 0. -#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR 0x00000001 -#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_BITN 0 -#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_M 0x00000001 -#define AUX_SYSIF_RTCEVCLR_RTC_CH2_EV_CLR_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_BATMONBAT -// -//***************************************************************************** -// Field: [10:8] INT -// -// See AON_BATMON:BAT.INT. -// -// Follow this procedure to get the correct value: -// - Do two dummy reads of INT. -// - Then read INT until two consecutive reads are equal. -#define AUX_SYSIF_BATMONBAT_INT_W 3 -#define AUX_SYSIF_BATMONBAT_INT_M 0x00000700 -#define AUX_SYSIF_BATMONBAT_INT_S 8 - -// Field: [7:0] FRAC -// -// See AON_BATMON:BAT.FRAC. -// -// Follow this procedure to get the correct value: -// - Do two dummy reads of FRAC. -// - Then read FRAC until two consecutive reads are equal. -#define AUX_SYSIF_BATMONBAT_FRAC_W 8 -#define AUX_SYSIF_BATMONBAT_FRAC_M 0x000000FF -#define AUX_SYSIF_BATMONBAT_FRAC_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_BATMONTEMP -// -//***************************************************************************** -// Field: [15:11] SIGN -// -// Sign extension of INT. -// -// Follow this procedure to get the correct value: -// - Do two dummy reads of SIGN. -// - Then read SIGN until two consecutive reads are equal. -#define AUX_SYSIF_BATMONTEMP_SIGN_W 5 -#define AUX_SYSIF_BATMONTEMP_SIGN_M 0x0000F800 -#define AUX_SYSIF_BATMONTEMP_SIGN_S 11 - -// Field: [10:2] INT -// -// See AON_BATMON:TEMP.INT. -// -// Follow this procedure to get the correct value: -// - Do two dummy reads of INT. -// - Then read INT until two consecutive reads are equal. -#define AUX_SYSIF_BATMONTEMP_INT_W 9 -#define AUX_SYSIF_BATMONTEMP_INT_M 0x000007FC -#define AUX_SYSIF_BATMONTEMP_INT_S 2 - -// Field: [1:0] FRAC -// -// See AON_BATMON:TEMP.FRAC. -// -// Follow this procedure to get the correct value: -// - Do two dummy reads of FRAC. -// - Then read FRAC until two consecutive reads are equal. -#define AUX_SYSIF_BATMONTEMP_FRAC_W 2 -#define AUX_SYSIF_BATMONTEMP_FRAC_M 0x00000003 -#define AUX_SYSIF_BATMONTEMP_FRAC_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_TIMERHALT -// -//***************************************************************************** -// Field: [3] PROGDLY -// -// Halt programmable delay. -// -// 0: AUX_EVCTL:PROGDLY.VALUE decrements as normal. -// 1: Halt AUX_EVCTL:PROGDLY.VALUE decrementation. -#define AUX_SYSIF_TIMERHALT_PROGDLY 0x00000008 -#define AUX_SYSIF_TIMERHALT_PROGDLY_BITN 3 -#define AUX_SYSIF_TIMERHALT_PROGDLY_M 0x00000008 -#define AUX_SYSIF_TIMERHALT_PROGDLY_S 3 - -// Field: [2] AUX_TIMER2 -// -// Halt AUX_TIMER2. -// -// 0: AUX_TIMER2 operates as normal. -// 1: Halt AUX_TIMER2 operation. -#define AUX_SYSIF_TIMERHALT_AUX_TIMER2 0x00000004 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_BITN 2 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_M 0x00000004 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER2_S 2 - -// Field: [1] AUX_TIMER1 -// -// Halt AUX_TIMER01 Timer 1. -// -// 0: AUX_TIMER01 Timer 1 operates as normal. -// 1: Halt AUX_TIMER01 Timer 1 operation. -#define AUX_SYSIF_TIMERHALT_AUX_TIMER1 0x00000002 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_BITN 1 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_M 0x00000002 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER1_S 1 - -// Field: [0] AUX_TIMER0 -// -// Halt AUX_TIMER01 Timer 0. -// -// 0: AUX_TIMER01 Timer 0 operates as normal. -// 1: Halt AUX_TIMER01 Timer 0 operation. -#define AUX_SYSIF_TIMERHALT_AUX_TIMER0 0x00000001 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_BITN 0 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_M 0x00000001 -#define AUX_SYSIF_TIMERHALT_AUX_TIMER0_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_TIMER2BRIDGE -// -//***************************************************************************** -// Field: [0] BUSY -// -// Status of bus transactions to AUX_TIMER2. -// -// 0: No unfinished bus transactions. -// 1: A bus transaction is ongoing. -#define AUX_SYSIF_TIMER2BRIDGE_BUSY 0x00000001 -#define AUX_SYSIF_TIMER2BRIDGE_BUSY_BITN 0 -#define AUX_SYSIF_TIMER2BRIDGE_BUSY_M 0x00000001 -#define AUX_SYSIF_TIMER2BRIDGE_BUSY_S 0 - -//***************************************************************************** -// -// Register: AUX_SYSIF_O_SWPWRPROF -// -//***************************************************************************** -// Field: [2:0] STAT -// -// Software status bits that can be read by the power profiler. -#define AUX_SYSIF_SWPWRPROF_STAT_W 3 -#define AUX_SYSIF_SWPWRPROF_STAT_M 0x00000007 -#define AUX_SYSIF_SWPWRPROF_STAT_S 0 - - -#endif // __AUX_SYSIF__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h deleted file mode 100644 index 002d740a5db..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_tdc.h +++ /dev/null @@ -1,879 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_tdc_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_TDC_H__ -#define __HW_AUX_TDC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_TDC component -// -//***************************************************************************** -// Control -#define AUX_TDC_O_CTL 0x00000000 - -// Status -#define AUX_TDC_O_STAT 0x00000004 - -// Result -#define AUX_TDC_O_RESULT 0x00000008 - -// Saturation Configuration -#define AUX_TDC_O_SATCFG 0x0000000C - -// Trigger Source -#define AUX_TDC_O_TRIGSRC 0x00000010 - -// Trigger Counter -#define AUX_TDC_O_TRIGCNT 0x00000014 - -// Trigger Counter Load -#define AUX_TDC_O_TRIGCNTLOAD 0x00000018 - -// Trigger Counter Configuration -#define AUX_TDC_O_TRIGCNTCFG 0x0000001C - -// Prescaler Control -#define AUX_TDC_O_PRECTL 0x00000020 - -// Prescaler Counter -#define AUX_TDC_O_PRECNTR 0x00000024 - -//***************************************************************************** -// -// Register: AUX_TDC_O_CTL -// -//***************************************************************************** -// Field: [1:0] CMD -// -// TDC commands. -// ENUMs: -// ABORT Force TDC state machine back to IDLE state. -// -// Never write this command -// while AUX_TDC:STAT.STATE equals CLR_CNT or -// WAIT_CLR_CNT_DONE. -// RUN Asynchronous counter start. -// -// The counter starts to -// count when the start event is high. To achieve -// precise edge-to-edge measurements you must -// ensure that the start event is low for at least -// 420 ns after you write this command. -// RUN_SYNC_START Synchronous counter start. -// -// The counter looks for the -// opposite edge of the selected start event -// before it starts to count when the selected -// edge occurs. This guarantees an edge-triggered -// start and is recommended for frequency -// measurements. -// CLR_RESULT Clear STAT.SAT, STAT.DONE, and RESULT.VALUE. -// -// This is not needed as -// prerequisite for a measurement. Reliable clear -// is only guaranteed from IDLE state. -#define AUX_TDC_CTL_CMD_W 2 -#define AUX_TDC_CTL_CMD_M 0x00000003 -#define AUX_TDC_CTL_CMD_S 0 -#define AUX_TDC_CTL_CMD_ABORT 0x00000003 -#define AUX_TDC_CTL_CMD_RUN 0x00000002 -#define AUX_TDC_CTL_CMD_RUN_SYNC_START 0x00000001 -#define AUX_TDC_CTL_CMD_CLR_RESULT 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TDC_O_STAT -// -//***************************************************************************** -// Field: [7] SAT -// -// TDC measurement saturation flag. -// -// 0: Conversion has not saturated. -// 1: Conversion stopped due to saturation. -// -// This field is cleared when a new measurement is started or when CLR_RESULT -// is written to CTL.CMD. -#define AUX_TDC_STAT_SAT 0x00000080 -#define AUX_TDC_STAT_SAT_BITN 7 -#define AUX_TDC_STAT_SAT_M 0x00000080 -#define AUX_TDC_STAT_SAT_S 7 - -// Field: [6] DONE -// -// TDC measurement complete flag. -// -// 0: TDC measurement has not yet completed. -// 1: TDC measurement has completed. -// -// This field clears when a new TDC measurement starts or when you write -// CLR_RESULT to CTL.CMD. -#define AUX_TDC_STAT_DONE 0x00000040 -#define AUX_TDC_STAT_DONE_BITN 6 -#define AUX_TDC_STAT_DONE_M 0x00000040 -#define AUX_TDC_STAT_DONE_S 6 - -// Field: [5:0] STATE -// -// TDC state machine status. -// ENUMs: -// FORCE_STOP Current state is TDC_FORCESTOP. -// You wrote ABORT to -// CTL.CMD to abort the TDC measurement. -// START_FALL Current state is TDC_WAIT_STARTFALL. -// The fast-counter circuit -// waits for a falling edge on the start event. -// WAIT_CLR_CNT_DONE Current state is TDC_STATE_WAIT_CLRCNT_DONE. -// The state machine waits -// for fast-counter circuit to finish reset. -// POR Current state is TDC_STATE_POR. -// This is the reset state. -// GET_RESULT Current state is TDC_STATE_GETRESULTS. -// The state machine copies -// the counter value from the fast-counter -// circuit. -// WAIT_STOP_CNTDWN Current state is TDC_STATE_WAIT_STOPCNTDOWN. -// The fast-counter circuit -// looks for the stop condition. It will ignore a -// number of stop events configured in -// TRIGCNTLOAD.CNT. -// WAIT_STOP Current state is TDC_STATE_WAIT_STOP. -// The state machine waits -// for the fast-counter circuit to stop. -// CLR_CNT Current state is TDC_STATE_CLRCNT. The -// fast-counter circuit is reset. -// IDLE Current state is TDC_STATE_IDLE. -// This is the default state -// after reset and abortion. State will change -// when you write CTL.CMD to either RUN_SYNC_START -// or RUN. -// WAIT_START_STOP_CNT_EN Current state is TDC_STATE_WAIT_STARTSTOPCNTEN. -// The fast-counter circuit -// looks for the start condition. The state -// machine waits for the fast-counter to -// increment. -// WAIT_START Current state is TDC_STATE_WAIT_START. -// The fast-counter circuit -// looks for the start condition. The state -// machine waits for the fast-counter to -// increment. -#define AUX_TDC_STAT_STATE_W 6 -#define AUX_TDC_STAT_STATE_M 0x0000003F -#define AUX_TDC_STAT_STATE_S 0 -#define AUX_TDC_STAT_STATE_FORCE_STOP 0x0000002E -#define AUX_TDC_STAT_STATE_START_FALL 0x0000001E -#define AUX_TDC_STAT_STATE_WAIT_CLR_CNT_DONE 0x00000016 -#define AUX_TDC_STAT_STATE_POR 0x0000000F -#define AUX_TDC_STAT_STATE_GET_RESULT 0x0000000E -#define AUX_TDC_STAT_STATE_WAIT_STOP_CNTDWN 0x0000000C -#define AUX_TDC_STAT_STATE_WAIT_STOP 0x00000008 -#define AUX_TDC_STAT_STATE_CLR_CNT 0x00000007 -#define AUX_TDC_STAT_STATE_IDLE 0x00000006 -#define AUX_TDC_STAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004 -#define AUX_TDC_STAT_STATE_WAIT_START 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TDC_O_RESULT -// -//***************************************************************************** -// Field: [24:0] VALUE -// -// TDC conversion result. -// -// The result of the TDC conversion is given in number of clock edges of the -// clock source selected in DDI_0_OSC:CTL0.ACLK_TDC_SRC_SEL. Both rising and -// falling edges are counted. -// -// If TDC counter saturates, VALUE is slightly higher than SATCFG.LIMIT, as it -// takes a non-zero time to stop the measurement. Hence, the maximum value of -// this field becomes slightly higher than 2^24 if you configure SATCFG.LIMIT -// to R24. -#define AUX_TDC_RESULT_VALUE_W 25 -#define AUX_TDC_RESULT_VALUE_M 0x01FFFFFF -#define AUX_TDC_RESULT_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TDC_O_SATCFG -// -//***************************************************************************** -// Field: [3:0] LIMIT -// -// Saturation limit. -// -// The flag STAT.SAT is set when the TDC counter saturates. -// -// Values not enumerated are not supported -// ENUMs: -// R24 Result bit 24: TDC conversion saturates and stops -// when RESULT.VALUE[24] is set. -// R23 Result bit 23: TDC conversion saturates and stops -// when RESULT.VALUE[23] is set. -// R22 Result bit 22: TDC conversion saturates and stops -// when RESULT.VALUE[22] is set. -// R21 Result bit 21: TDC conversion saturates and stops -// when RESULT.VALUE[21] is set. -// R20 Result bit 20: TDC conversion saturates and stops -// when RESULT.VALUE[20] is set. -// R19 Result bit 19: TDC conversion saturates and stops -// when RESULT.VALUE[19] is set. -// R18 Result bit 18: TDC conversion saturates and stops -// when RESULT.VALUE[18] is set. -// R17 Result bit 17: TDC conversion saturates and stops -// when RESULT.VALUE[17] is set. -// R16 Result bit 16: TDC conversion saturates and stops -// when RESULT.VALUE[16] is set. -// R15 Result bit 15: TDC conversion saturates and stops -// when RESULT.VALUE[15] is set. -// R14 Result bit 14: TDC conversion saturates and stops -// when RESULT.VALUE[14] is set. -// R13 Result bit 13: TDC conversion saturates and stops -// when RESULT.VALUE[13] is set. -// R12 Result bit 12: TDC conversion saturates and stops -// when RESULT.VALUE[12] is set. -#define AUX_TDC_SATCFG_LIMIT_W 4 -#define AUX_TDC_SATCFG_LIMIT_M 0x0000000F -#define AUX_TDC_SATCFG_LIMIT_S 0 -#define AUX_TDC_SATCFG_LIMIT_R24 0x0000000F -#define AUX_TDC_SATCFG_LIMIT_R23 0x0000000E -#define AUX_TDC_SATCFG_LIMIT_R22 0x0000000D -#define AUX_TDC_SATCFG_LIMIT_R21 0x0000000C -#define AUX_TDC_SATCFG_LIMIT_R20 0x0000000B -#define AUX_TDC_SATCFG_LIMIT_R19 0x0000000A -#define AUX_TDC_SATCFG_LIMIT_R18 0x00000009 -#define AUX_TDC_SATCFG_LIMIT_R17 0x00000008 -#define AUX_TDC_SATCFG_LIMIT_R16 0x00000007 -#define AUX_TDC_SATCFG_LIMIT_R15 0x00000006 -#define AUX_TDC_SATCFG_LIMIT_R14 0x00000005 -#define AUX_TDC_SATCFG_LIMIT_R13 0x00000004 -#define AUX_TDC_SATCFG_LIMIT_R12 0x00000003 - -//***************************************************************************** -// -// Register: AUX_TDC_O_TRIGSRC -// -//***************************************************************************** -// Field: [14] STOP_POL -// -// Polarity of stop source. -// -// Change only while STAT.STATE is IDLE. -// ENUMs: -// LOW TDC conversion stops when low level is detected. -// HIGH TDC conversion stops when high level is detected. -#define AUX_TDC_TRIGSRC_STOP_POL 0x00004000 -#define AUX_TDC_TRIGSRC_STOP_POL_BITN 14 -#define AUX_TDC_TRIGSRC_STOP_POL_M 0x00004000 -#define AUX_TDC_TRIGSRC_STOP_POL_S 14 -#define AUX_TDC_TRIGSRC_STOP_POL_LOW 0x00004000 -#define AUX_TDC_TRIGSRC_STOP_POL_HIGH 0x00000000 - -// Field: [13:8] STOP_SRC -// -// Select stop source from the asynchronous AUX event bus. -// -// Change only while STAT.STATE is IDLE. -// ENUMs: -// NO_EVENT No event. -// AUX_TDC_PRE Select TDC Prescaler event which is generated by -// configuration of PRECTL. -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TDC_TRIGSRC_STOP_SRC_W 6 -#define AUX_TDC_TRIGSRC_STOP_SRC_M 0x00003F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_S 8 -#define AUX_TDC_TRIGSRC_STOP_SRC_NO_EVENT 0x00003F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_PRE 0x00003E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_IRQ 0x00003A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ADC_DONE 0x00003900 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_ISRC_RESET_N 0x00003800 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TDC_DONE 0x00003700 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER0_EV 0x00003600 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER1_EV 0x00003500 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_PULSE 0x00003400 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV3 0x00003300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV2 0x00003200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV1 0x00003100 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_TIMER2_EV0 0x00003000 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPB 0x00002F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUX_COMPA 0x00002E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX1 0x00002D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_OBSMUX0 0x00002C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_EV 0x00002B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_ACLK_REF 0x00002A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_VDDR_RECHARGE 0x00002900 -#define AUX_TDC_TRIGSRC_STOP_SRC_MCU_ACTIVE 0x00002800 -#define AUX_TDC_TRIGSRC_STOP_SRC_PWR_DWN 0x00002700 -#define AUX_TDC_TRIGSRC_STOP_SRC_SCLK_LF 0x00002600 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_TEMP_UPD 0x00002500 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_BATMON_BAT_UPD 0x00002400 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_4KHZ 0x00002300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2_DLY 0x00002200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AON_RTC_CH2 0x00002100 -#define AUX_TDC_TRIGSRC_STOP_SRC_MANUAL_EV 0x00002000 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO31 0x00001F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO30 0x00001E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO29 0x00001D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO28 0x00001C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO27 0x00001B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO26 0x00001A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO25 0x00001900 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO24 0x00001800 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO23 0x00001700 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO22 0x00001600 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO21 0x00001500 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO20 0x00001400 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO19 0x00001300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO18 0x00001200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO17 0x00001100 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO16 0x00001000 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO15 0x00000F00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO14 0x00000E00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO13 0x00000D00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO12 0x00000C00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO11 0x00000B00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO10 0x00000A00 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO9 0x00000900 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO8 0x00000800 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO7 0x00000700 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO6 0x00000600 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO5 0x00000500 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO4 0x00000400 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO3 0x00000300 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO2 0x00000200 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO1 0x00000100 -#define AUX_TDC_TRIGSRC_STOP_SRC_AUXIO0 0x00000000 - -// Field: [6] START_POL -// -// Polarity of start source. -// -// Change only while STAT.STATE is IDLE. -// ENUMs: -// LOW TDC conversion starts when low level is detected. -// HIGH TDC conversion starts when high level is detected. -#define AUX_TDC_TRIGSRC_START_POL 0x00000040 -#define AUX_TDC_TRIGSRC_START_POL_BITN 6 -#define AUX_TDC_TRIGSRC_START_POL_M 0x00000040 -#define AUX_TDC_TRIGSRC_START_POL_S 6 -#define AUX_TDC_TRIGSRC_START_POL_LOW 0x00000040 -#define AUX_TDC_TRIGSRC_START_POL_HIGH 0x00000000 - -// Field: [5:0] START_SRC -// -// Select start source from the asynchronous AUX event bus. -// -// Change only while STAT.STATE is IDLE. -// ENUMs: -// NO_EVENT No event. -// AUX_TDC_PRE Select TDC Prescaler event which is generated by -// configuration of PRECTL. -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TDC_TRIGSRC_START_SRC_W 6 -#define AUX_TDC_TRIGSRC_START_SRC_M 0x0000003F -#define AUX_TDC_TRIGSRC_START_SRC_S 0 -#define AUX_TDC_TRIGSRC_START_SRC_NO_EVENT 0x0000003F -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_PRE 0x0000003E -#define AUX_TDC_TRIGSRC_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_IRQ 0x0000003A -#define AUX_TDC_TRIGSRC_START_SRC_AUX_ADC_DONE 0x00000039 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_ISRC_RESET_N 0x00000038 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TDC_DONE 0x00000037 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER0_EV 0x00000036 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER1_EV 0x00000035 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_PULSE 0x00000034 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV3 0x00000033 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV2 0x00000032 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV1 0x00000031 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_TIMER2_EV0 0x00000030 -#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPB 0x0000002F -#define AUX_TDC_TRIGSRC_START_SRC_AUX_COMPA 0x0000002E -#define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX1 0x0000002D -#define AUX_TDC_TRIGSRC_START_SRC_MCU_OBSMUX0 0x0000002C -#define AUX_TDC_TRIGSRC_START_SRC_MCU_EV 0x0000002B -#define AUX_TDC_TRIGSRC_START_SRC_ACLK_REF 0x0000002A -#define AUX_TDC_TRIGSRC_START_SRC_VDDR_RECHARGE 0x00000029 -#define AUX_TDC_TRIGSRC_START_SRC_MCU_ACTIVE 0x00000028 -#define AUX_TDC_TRIGSRC_START_SRC_PWR_DWN 0x00000027 -#define AUX_TDC_TRIGSRC_START_SRC_SCLK_LF 0x00000026 -#define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_TDC_TRIGSRC_START_SRC_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_4KHZ 0x00000023 -#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2_DLY 0x00000022 -#define AUX_TDC_TRIGSRC_START_SRC_AON_RTC_CH2 0x00000021 -#define AUX_TDC_TRIGSRC_START_SRC_MANUAL_EV 0x00000020 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO31 0x0000001F -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO30 0x0000001E -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO29 0x0000001D -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO28 0x0000001C -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO27 0x0000001B -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO26 0x0000001A -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO25 0x00000019 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO24 0x00000018 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO23 0x00000017 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO22 0x00000016 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO21 0x00000015 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO20 0x00000014 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO19 0x00000013 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO18 0x00000012 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO17 0x00000011 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO16 0x00000010 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO15 0x0000000F -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO14 0x0000000E -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO13 0x0000000D -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO12 0x0000000C -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO11 0x0000000B -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO10 0x0000000A -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO9 0x00000009 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO8 0x00000008 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO7 0x00000007 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO6 0x00000006 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO5 0x00000005 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO4 0x00000004 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO3 0x00000003 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO2 0x00000002 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO1 0x00000001 -#define AUX_TDC_TRIGSRC_START_SRC_AUXIO0 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TDC_O_TRIGCNT -// -//***************************************************************************** -// Field: [15:0] CNT -// -// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. -// -// Read CNT to get the remaining number of stop events to ignore during a TDC -// measurement. -// -// Write CNT to update the remaining number of stop events to ignore during a -// TDC measurement. The TDC measurement ignores updates of CNT if there are no -// more stop events left to ignore. -// -// When AUX_TDC:TRIGCNTCFG.EN is 1, TRIGCNTLOAD.CNT is loaded into CNT at the -// start of the measurement. -#define AUX_TDC_TRIGCNT_CNT_W 16 -#define AUX_TDC_TRIGCNT_CNT_M 0x0000FFFF -#define AUX_TDC_TRIGCNT_CNT_S 0 - -//***************************************************************************** -// -// Register: AUX_TDC_O_TRIGCNTLOAD -// -//***************************************************************************** -// Field: [15:0] CNT -// -// Number of stop events to ignore when AUX_TDC:TRIGCNTCFG.EN is 1. -// -// To measure frequency of an event source: -// - Set start event equal to stop event. -// - Set CNT to number of periods to measure. Both 0 and 1 values measures a -// single event source period. -// -// To measure pulse width of an event source: -// - Set start event source equal to stop event source. -// - Select different polarity for start and stop event. -// - Set CNT to 0. -// -// To measure time from the start event to the Nth stop event when N > 1: -// - Select different start and stop event source. -// - Set CNT to (N-1). -// -// See the Technical Reference Manual for event timing requirements. -// -// When AUX_TDC:TRIGCNTCFG.EN is 1, CNT is loaded into TRIGCNT.CNT at the start -// of the measurement. -#define AUX_TDC_TRIGCNTLOAD_CNT_W 16 -#define AUX_TDC_TRIGCNTLOAD_CNT_M 0x0000FFFF -#define AUX_TDC_TRIGCNTLOAD_CNT_S 0 - -//***************************************************************************** -// -// Register: AUX_TDC_O_TRIGCNTCFG -// -//***************************************************************************** -// Field: [0] EN -// -// Enable stop-counter. -// -// 0: Disable stop-counter. -// 1: Enable stop-counter. -// -// Change only while STAT.STATE is IDLE. -#define AUX_TDC_TRIGCNTCFG_EN 0x00000001 -#define AUX_TDC_TRIGCNTCFG_EN_BITN 0 -#define AUX_TDC_TRIGCNTCFG_EN_M 0x00000001 -#define AUX_TDC_TRIGCNTCFG_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_TDC_O_PRECTL -// -//***************************************************************************** -// Field: [7] RESET_N -// -// Prescaler reset. -// -// 0: Reset prescaler. -// 1: Release reset of prescaler. -// -// AUX_TDC_PRE event becomes 0 when you reset the prescaler. -#define AUX_TDC_PRECTL_RESET_N 0x00000080 -#define AUX_TDC_PRECTL_RESET_N_BITN 7 -#define AUX_TDC_PRECTL_RESET_N_M 0x00000080 -#define AUX_TDC_PRECTL_RESET_N_S 7 - -// Field: [6] RATIO -// -// Prescaler ratio. -// -// This controls how often the AUX_TDC_PRE event is generated by the prescaler. -// ENUMs: -// DIV64 Prescaler divides input by 64. -// -// AUX_TDC_PRE event has a -// rising edge for every 64 rising edges of the -// input. AUX_TDC_PRE event toggles on every 32nd -// rising edge of the input. -// DIV16 Prescaler divides input by 16. -// -// AUX_TDC_PRE event has a -// rising edge for every 16 rising edges of the -// input. AUX_TDC_PRE event toggles on every 8th -// rising edge of the input. -#define AUX_TDC_PRECTL_RATIO 0x00000040 -#define AUX_TDC_PRECTL_RATIO_BITN 6 -#define AUX_TDC_PRECTL_RATIO_M 0x00000040 -#define AUX_TDC_PRECTL_RATIO_S 6 -#define AUX_TDC_PRECTL_RATIO_DIV64 0x00000040 -#define AUX_TDC_PRECTL_RATIO_DIV16 0x00000000 - -// Field: [5:0] SRC -// -// Prescaler event source. -// -// Select an event from the asynchronous AUX event bus to connect to the -// prescaler input. -// -// Configure only while RESET_N is 0. -// ENUMs: -// NO_EVENT No event. -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TDC_PRECTL_SRC_W 6 -#define AUX_TDC_PRECTL_SRC_M 0x0000003F -#define AUX_TDC_PRECTL_SRC_S 0 -#define AUX_TDC_PRECTL_SRC_NO_EVENT 0x0000003F -#define AUX_TDC_PRECTL_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000003D -#define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x0000003C -#define AUX_TDC_PRECTL_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x0000003B -#define AUX_TDC_PRECTL_SRC_AUX_ADC_IRQ 0x0000003A -#define AUX_TDC_PRECTL_SRC_AUX_ADC_DONE 0x00000039 -#define AUX_TDC_PRECTL_SRC_AUX_ISRC_RESET_N 0x00000038 -#define AUX_TDC_PRECTL_SRC_AUX_TDC_DONE 0x00000037 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER0_EV 0x00000036 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER1_EV 0x00000035 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_PULSE 0x00000034 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV3 0x00000033 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV2 0x00000032 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV1 0x00000031 -#define AUX_TDC_PRECTL_SRC_AUX_TIMER2_EV0 0x00000030 -#define AUX_TDC_PRECTL_SRC_AUX_COMPB 0x0000002F -#define AUX_TDC_PRECTL_SRC_AUX_COMPA 0x0000002E -#define AUX_TDC_PRECTL_SRC_MCU_OBSMUX1 0x0000002D -#define AUX_TDC_PRECTL_SRC_MCU_OBSMUX0 0x0000002C -#define AUX_TDC_PRECTL_SRC_MCU_EV 0x0000002B -#define AUX_TDC_PRECTL_SRC_ACLK_REF 0x0000002A -#define AUX_TDC_PRECTL_SRC_VDDR_RECHARGE 0x00000029 -#define AUX_TDC_PRECTL_SRC_MCU_ACTIVE 0x00000028 -#define AUX_TDC_PRECTL_SRC_PWR_DWN 0x00000027 -#define AUX_TDC_PRECTL_SRC_SCLK_LF 0x00000026 -#define AUX_TDC_PRECTL_SRC_AON_BATMON_TEMP_UPD 0x00000025 -#define AUX_TDC_PRECTL_SRC_AON_BATMON_BAT_UPD 0x00000024 -#define AUX_TDC_PRECTL_SRC_AON_RTC_4KHZ 0x00000023 -#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2_DLY 0x00000022 -#define AUX_TDC_PRECTL_SRC_AON_RTC_CH2 0x00000021 -#define AUX_TDC_PRECTL_SRC_MANUAL_EV 0x00000020 -#define AUX_TDC_PRECTL_SRC_AUXIO31 0x0000001F -#define AUX_TDC_PRECTL_SRC_AUXIO30 0x0000001E -#define AUX_TDC_PRECTL_SRC_AUXIO29 0x0000001D -#define AUX_TDC_PRECTL_SRC_AUXIO28 0x0000001C -#define AUX_TDC_PRECTL_SRC_AUXIO27 0x0000001B -#define AUX_TDC_PRECTL_SRC_AUXIO26 0x0000001A -#define AUX_TDC_PRECTL_SRC_AUXIO25 0x00000019 -#define AUX_TDC_PRECTL_SRC_AUXIO24 0x00000018 -#define AUX_TDC_PRECTL_SRC_AUXIO23 0x00000017 -#define AUX_TDC_PRECTL_SRC_AUXIO22 0x00000016 -#define AUX_TDC_PRECTL_SRC_AUXIO21 0x00000015 -#define AUX_TDC_PRECTL_SRC_AUXIO20 0x00000014 -#define AUX_TDC_PRECTL_SRC_AUXIO19 0x00000013 -#define AUX_TDC_PRECTL_SRC_AUXIO18 0x00000012 -#define AUX_TDC_PRECTL_SRC_AUXIO17 0x00000011 -#define AUX_TDC_PRECTL_SRC_AUXIO16 0x00000010 -#define AUX_TDC_PRECTL_SRC_AUXIO15 0x0000000F -#define AUX_TDC_PRECTL_SRC_AUXIO14 0x0000000E -#define AUX_TDC_PRECTL_SRC_AUXIO13 0x0000000D -#define AUX_TDC_PRECTL_SRC_AUXIO12 0x0000000C -#define AUX_TDC_PRECTL_SRC_AUXIO11 0x0000000B -#define AUX_TDC_PRECTL_SRC_AUXIO10 0x0000000A -#define AUX_TDC_PRECTL_SRC_AUXIO9 0x00000009 -#define AUX_TDC_PRECTL_SRC_AUXIO8 0x00000008 -#define AUX_TDC_PRECTL_SRC_AUXIO7 0x00000007 -#define AUX_TDC_PRECTL_SRC_AUXIO6 0x00000006 -#define AUX_TDC_PRECTL_SRC_AUXIO5 0x00000005 -#define AUX_TDC_PRECTL_SRC_AUXIO4 0x00000004 -#define AUX_TDC_PRECTL_SRC_AUXIO3 0x00000003 -#define AUX_TDC_PRECTL_SRC_AUXIO2 0x00000002 -#define AUX_TDC_PRECTL_SRC_AUXIO1 0x00000001 -#define AUX_TDC_PRECTL_SRC_AUXIO0 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TDC_O_PRECNTR -// -//***************************************************************************** -// Field: [15:0] CNT -// -// Prescaler counter value. -// -// Write a value to CNT to capture the value of the 16-bit prescaler counter -// into CNT. Read CNT to get the captured value. -// -// The read value gets 1 LSB uncertainty if the event source level rises when -// you release the reset. -// The read value gets 1 LSB uncertainty if the event source level rises when -// you capture the prescaler counter. -// -// Please note the following: -// - The prescaler counter is reset to 2 by PRECTL.RESET_N. -// - The captured value is 2 when the number of rising edges on prescaler input -// is less than 3. Otherwise, captured value equals number of event pulses - 1. -#define AUX_TDC_PRECNTR_CNT_W 16 -#define AUX_TDC_PRECNTR_CNT_M 0x0000FFFF -#define AUX_TDC_PRECNTR_CNT_S 0 - - -#endif // __AUX_TDC__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h deleted file mode 100644 index 288a8fd825c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer01.h +++ /dev/null @@ -1,611 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_timer01_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_TIMER01_H__ -#define __HW_AUX_TIMER01_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_TIMER01 component -// -//***************************************************************************** -// Timer 0 Configuration -#define AUX_TIMER01_O_T0CFG 0x00000000 - -// Timer 0 Control -#define AUX_TIMER01_O_T0CTL 0x00000004 - -// Timer 0 Target -#define AUX_TIMER01_O_T0TARGET 0x00000008 - -// Timer 0 Counter -#define AUX_TIMER01_O_T0CNTR 0x0000000C - -// Timer 1 Configuration -#define AUX_TIMER01_O_T1CFG 0x00000010 - -// Timer 1 Control -#define AUX_TIMER01_O_T1CTL 0x00000014 - -// Timer 1 Target -#define AUX_TIMER01_O_T1TARGET 0x00000018 - -// Timer 1 Counter -#define AUX_TIMER01_O_T1CNTR 0x0000001C - -//***************************************************************************** -// -// Register: AUX_TIMER01_O_T0CFG -// -//***************************************************************************** -// Field: [14] TICK_SRC_POL -// -// Tick source polarity for Timer 0. -// ENUMs: -// FALL Count on falling edges of TICK_SRC. -// RISE Count on rising edges of TICK_SRC. -#define AUX_TIMER01_T0CFG_TICK_SRC_POL 0x00004000 -#define AUX_TIMER01_T0CFG_TICK_SRC_POL_BITN 14 -#define AUX_TIMER01_T0CFG_TICK_SRC_POL_M 0x00004000 -#define AUX_TIMER01_T0CFG_TICK_SRC_POL_S 14 -#define AUX_TIMER01_T0CFG_TICK_SRC_POL_FALL 0x00004000 -#define AUX_TIMER01_T0CFG_TICK_SRC_POL_RISE 0x00000000 - -// Field: [13:8] TICK_SRC -// -// Select Timer 0 tick source from the synchronous event bus. -// ENUMs: -// AUX_TIMER2_CLKSW_RDY AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY -// AUX_DAC_HOLD_ACTIVE AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// NO_EVENT No event. -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TIMER01_T0CFG_TICK_SRC_W 6 -#define AUX_TIMER01_T0CFG_TICK_SRC_M 0x00003F00 -#define AUX_TIMER01_T0CFG_TICK_SRC_S 8 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ADC_DONE 0x00003900 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TDC_DONE 0x00003700 -#define AUX_TIMER01_T0CFG_TICK_SRC_NO_EVENT 0x00003600 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER1_EV 0x00003500 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPB 0x00002F00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUX_COMPA 0x00002E00 -#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00 -#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00 -#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_EV 0x00002B00 -#define AUX_TIMER01_T0CFG_TICK_SRC_ACLK_REF 0x00002A00 -#define AUX_TIMER01_T0CFG_TICK_SRC_VDDR_RECHARGE 0x00002900 -#define AUX_TIMER01_T0CFG_TICK_SRC_MCU_ACTIVE 0x00002800 -#define AUX_TIMER01_T0CFG_TICK_SRC_PWR_DWN 0x00002700 -#define AUX_TIMER01_T0CFG_TICK_SRC_SCLK_LF 0x00002600 -#define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500 -#define AUX_TIMER01_T0CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400 -#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300 -#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200 -#define AUX_TIMER01_T0CFG_TICK_SRC_AON_RTC_CH2 0x00002100 -#define AUX_TIMER01_T0CFG_TICK_SRC_MANUAL_EV 0x00002000 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO31 0x00001F00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO30 0x00001E00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO29 0x00001D00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO28 0x00001C00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO27 0x00001B00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO26 0x00001A00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO25 0x00001900 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO24 0x00001800 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO23 0x00001700 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO22 0x00001600 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO21 0x00001500 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO20 0x00001400 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO19 0x00001300 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO18 0x00001200 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO17 0x00001100 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO16 0x00001000 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO15 0x00000F00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO14 0x00000E00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO13 0x00000D00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO12 0x00000C00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO11 0x00000B00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO10 0x00000A00 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO9 0x00000900 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO8 0x00000800 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO7 0x00000700 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO6 0x00000600 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO5 0x00000500 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO4 0x00000400 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO3 0x00000300 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO2 0x00000200 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO1 0x00000100 -#define AUX_TIMER01_T0CFG_TICK_SRC_AUXIO0 0x00000000 - -// Field: [7:4] PRE -// -// Prescaler division ratio is 2^PRE: -// -// 0x0: Divide by 1. -// 0x1: Divide by 2. -// 0x2: Divide by 4. -// ... -// 0xF: Divide by 32,768. -#define AUX_TIMER01_T0CFG_PRE_W 4 -#define AUX_TIMER01_T0CFG_PRE_M 0x000000F0 -#define AUX_TIMER01_T0CFG_PRE_S 4 - -// Field: [1] MODE -// -// Timer 0 mode. -// -// Configure source for Timer 0 prescaler. -// ENUMs: -// TICK Use event set by TICK_SRC as source for prescaler. -// CLK Use clock as source for prescaler. Note that -// AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the -// clock frequency. -#define AUX_TIMER01_T0CFG_MODE 0x00000002 -#define AUX_TIMER01_T0CFG_MODE_BITN 1 -#define AUX_TIMER01_T0CFG_MODE_M 0x00000002 -#define AUX_TIMER01_T0CFG_MODE_S 1 -#define AUX_TIMER01_T0CFG_MODE_TICK 0x00000002 -#define AUX_TIMER01_T0CFG_MODE_CLK 0x00000000 - -// Field: [0] RELOAD -// -// Timer 0 reload mode. -// ENUMs: -// CONT Continuous mode. -// -// Timer 0 restarts when the -// counter value becomes equal to or greater than -// ( T0TARGET.VALUE - 1). -// MAN Manual mode. -// -// Timer 0 stops and -// T0CTL.EN becomes 0 when the counter value -// becomes equal to or greater than -// T0TARGET.VALUE. -#define AUX_TIMER01_T0CFG_RELOAD 0x00000001 -#define AUX_TIMER01_T0CFG_RELOAD_BITN 0 -#define AUX_TIMER01_T0CFG_RELOAD_M 0x00000001 -#define AUX_TIMER01_T0CFG_RELOAD_S 0 -#define AUX_TIMER01_T0CFG_RELOAD_CONT 0x00000001 -#define AUX_TIMER01_T0CFG_RELOAD_MAN 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER01_O_T0CTL -// -//***************************************************************************** -// Field: [0] EN -// -// Timer 0 enable. -// -// 0: Disable Timer 0. -// 1: Enable Timer 0. -// -// The counter restarts from 0 when you enable Timer 0. -#define AUX_TIMER01_T0CTL_EN 0x00000001 -#define AUX_TIMER01_T0CTL_EN_BITN 0 -#define AUX_TIMER01_T0CTL_EN_M 0x00000001 -#define AUX_TIMER01_T0CTL_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER01_O_T0TARGET -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Timer 0 target value. -// -// Manual Reload Mode: -// - Timer 0 increments until the counter value becomes equal to or greater -// than VALUE. -// - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter -// value is equal to or greater than VALUE. -// -// Note: When VALUE is 0, Timer 0 counts to 1. AUX_TIMER0_EV pulses high for 1 -// peripheral clock period. -// -// Continuous Reload Mode: -// - Timer 0 increments until the counter value becomes equal to or greater -// than ( VALUE - 1), then restarts from 0. -// - AUX_TIMER0_EV pulses high for 1 peripheral clock period when the counter -// value is 0, except for when you enable the timer. -// -// Note: When VALUE is less than 2, Timer 0 counter value remains 0. -// AUX_TIMER0_EV goes high and remains high 1 peripheral clock period after you -// enable the timer. -// -// -// It is allowed to update the VALUE while the timer runs. -#define AUX_TIMER01_T0TARGET_VALUE_W 16 -#define AUX_TIMER01_T0TARGET_VALUE_M 0x0000FFFF -#define AUX_TIMER01_T0TARGET_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER01_O_T0CNTR -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Timer 0 counter value. -#define AUX_TIMER01_T0CNTR_VALUE_W 16 -#define AUX_TIMER01_T0CNTR_VALUE_M 0x0000FFFF -#define AUX_TIMER01_T0CNTR_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER01_O_T1CFG -// -//***************************************************************************** -// Field: [14] TICK_SRC_POL -// -// Tick source polarity for Timer 1. -// ENUMs: -// FALL Count on falling edges of TICK_SRC. -// RISE Count on rising edges of TICK_SRC. -#define AUX_TIMER01_T1CFG_TICK_SRC_POL 0x00004000 -#define AUX_TIMER01_T1CFG_TICK_SRC_POL_BITN 14 -#define AUX_TIMER01_T1CFG_TICK_SRC_POL_M 0x00004000 -#define AUX_TIMER01_T1CFG_TICK_SRC_POL_S 14 -#define AUX_TIMER01_T1CFG_TICK_SRC_POL_FALL 0x00004000 -#define AUX_TIMER01_T1CFG_TICK_SRC_POL_RISE 0x00000000 - -// Field: [13:8] TICK_SRC -// -// Select Timer 1 tick source from the synchronous event bus. -// ENUMs: -// AUX_TIMER2_CLKSW_RDY AUX_EVCTL:EVSTAT3.AUX_TIMER2_CLKSWITCH_RDY -// AUX_DAC_HOLD_ACTIVE AUX_EVCTL:EVSTAT3.AUX_DAC_HOLD_ACTIVE -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// NO_EVENT No event. -// AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TIMER01_T1CFG_TICK_SRC_W 6 -#define AUX_TIMER01_T1CFG_TICK_SRC_M 0x00003F00 -#define AUX_TIMER01_T1CFG_TICK_SRC_S 8 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_CLKSW_RDY 0x00003F00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_DAC_HOLD_ACTIVE 0x00003E00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00003C00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00003B00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_IRQ 0x00003A00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ADC_DONE 0x00003900 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_ISRC_RESET_N 0x00003800 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TDC_DONE 0x00003700 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER0_EV 0x00003600 -#define AUX_TIMER01_T1CFG_TICK_SRC_NO_EVENT 0x00003500 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_PULSE 0x00003400 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV3 0x00003300 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV2 0x00003200 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV1 0x00003100 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_TIMER2_EV0 0x00003000 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPB 0x00002F00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUX_COMPA 0x00002E00 -#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX1 0x00002D00 -#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_OBSMUX0 0x00002C00 -#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_EV 0x00002B00 -#define AUX_TIMER01_T1CFG_TICK_SRC_ACLK_REF 0x00002A00 -#define AUX_TIMER01_T1CFG_TICK_SRC_VDDR_RECHARGE 0x00002900 -#define AUX_TIMER01_T1CFG_TICK_SRC_MCU_ACTIVE 0x00002800 -#define AUX_TIMER01_T1CFG_TICK_SRC_PWR_DWN 0x00002700 -#define AUX_TIMER01_T1CFG_TICK_SRC_SCLK_LF 0x00002600 -#define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_TEMP_UPD 0x00002500 -#define AUX_TIMER01_T1CFG_TICK_SRC_AON_BATMON_BAT_UPD 0x00002400 -#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_4KHZ 0x00002300 -#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2_DLY 0x00002200 -#define AUX_TIMER01_T1CFG_TICK_SRC_AON_RTC_CH2 0x00002100 -#define AUX_TIMER01_T1CFG_TICK_SRC_MANUAL_EV 0x00002000 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO31 0x00001F00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO30 0x00001E00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO29 0x00001D00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO28 0x00001C00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO27 0x00001B00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO26 0x00001A00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO25 0x00001900 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO24 0x00001800 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO23 0x00001700 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO22 0x00001600 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO21 0x00001500 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO20 0x00001400 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO19 0x00001300 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO18 0x00001200 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO17 0x00001100 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO16 0x00001000 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO15 0x00000F00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO14 0x00000E00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO13 0x00000D00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO12 0x00000C00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO11 0x00000B00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO10 0x00000A00 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO9 0x00000900 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO8 0x00000800 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO7 0x00000700 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO6 0x00000600 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO5 0x00000500 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO4 0x00000400 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO3 0x00000300 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO2 0x00000200 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO1 0x00000100 -#define AUX_TIMER01_T1CFG_TICK_SRC_AUXIO0 0x00000000 - -// Field: [7:4] PRE -// -// Prescaler division ratio is 2^PRE: -// -// 0x0: Divide by 1. -// 0x1: Divide by 2. -// 0x2: Divide by 4. -// ... -// 0xF: Divide by 32,768. -#define AUX_TIMER01_T1CFG_PRE_W 4 -#define AUX_TIMER01_T1CFG_PRE_M 0x000000F0 -#define AUX_TIMER01_T1CFG_PRE_S 4 - -// Field: [1] MODE -// -// Timer 1 mode. -// -// Configure source for Timer 1 prescaler. -// ENUMs: -// TICK Use event set by TICK_SRC as source for prescaler. -// CLK Use clock as source for prescaler. Note that -// AUX_SYSIF:PEROPRATE.TIMER01_OP_RATE sets the -// clock frequency. -#define AUX_TIMER01_T1CFG_MODE 0x00000002 -#define AUX_TIMER01_T1CFG_MODE_BITN 1 -#define AUX_TIMER01_T1CFG_MODE_M 0x00000002 -#define AUX_TIMER01_T1CFG_MODE_S 1 -#define AUX_TIMER01_T1CFG_MODE_TICK 0x00000002 -#define AUX_TIMER01_T1CFG_MODE_CLK 0x00000000 - -// Field: [0] RELOAD -// -// Timer 1 reload mode. -// ENUMs: -// CONT Continuous mode. -// -// Timer 1 restarts when the -// counter value becomes equal to or greater than -// ( T1TARGET.VALUE - 1). -// MAN Manual mode. -// -// Timer 1 stops and -// T1CTL.EN becomes 0 when the counter value -// becomes equal to or greater than -// T1TARGET.VALUE. -#define AUX_TIMER01_T1CFG_RELOAD 0x00000001 -#define AUX_TIMER01_T1CFG_RELOAD_BITN 0 -#define AUX_TIMER01_T1CFG_RELOAD_M 0x00000001 -#define AUX_TIMER01_T1CFG_RELOAD_S 0 -#define AUX_TIMER01_T1CFG_RELOAD_CONT 0x00000001 -#define AUX_TIMER01_T1CFG_RELOAD_MAN 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER01_O_T1CTL -// -//***************************************************************************** -// Field: [0] EN -// -// Timer 1 enable. -// -// 0: Disable Timer 1. -// 1: Enable Timer 1. -// -// The counter restarts from 0 when you enable Timer 1. -#define AUX_TIMER01_T1CTL_EN 0x00000001 -#define AUX_TIMER01_T1CTL_EN_BITN 0 -#define AUX_TIMER01_T1CTL_EN_M 0x00000001 -#define AUX_TIMER01_T1CTL_EN_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER01_O_T1TARGET -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Timer 1 target value. -// -// Manual Reload Mode: -// - Timer 1 increments until the counter value becomes equal to or greater -// than VALUE. -// - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter -// value is equal to or greater than VALUE. -// -// Note: When VALUE is 0, Timer 1 counts to 1. AUX_TIMER1_EV pulses high for 1 -// peripheral clock period. -// -// Continuous Reload Mode: -// - Timer 1 increments until the counter value becomes equal to or greater -// than ( VALUE - 1), then restarts from 0. -// - AUX_TIMER1_EV pulses high for 1 peripheral clock period when the counter -// value is 0, except for when you enable the timer. -// -// Note: When VALUE is less than 2, Timer 1 counter value remains 0. -// AUX_TIMER1_EV goes high and remains high 1 peripheral clock period after you -// enable the timer. -// -// -// It is allowed to update the VALUE while the timer runs. -#define AUX_TIMER01_T1TARGET_VALUE_W 16 -#define AUX_TIMER01_T1TARGET_VALUE_M 0x0000FFFF -#define AUX_TIMER01_T1TARGET_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER01_O_T1CNTR -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Timer 1 counter value. -#define AUX_TIMER01_T1CNTR_VALUE_W 16 -#define AUX_TIMER01_T1CNTR_VALUE_M 0x0000FFFF -#define AUX_TIMER01_T1CNTR_VALUE_S 0 - - -#endif // __AUX_TIMER01__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h deleted file mode 100644 index aa7423f4d09..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_aux_timer2.h +++ /dev/null @@ -1,2491 +0,0 @@ -/****************************************************************************** -* Filename: hw_aux_timer2_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_AUX_TIMER2_H__ -#define __HW_AUX_TIMER2_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// AUX_TIMER2 component -// -//***************************************************************************** -// Timer Control -#define AUX_TIMER2_O_CTL 0x00000000 - -// Target -#define AUX_TIMER2_O_TARGET 0x00000004 - -// Shadow Target -#define AUX_TIMER2_O_SHDWTARGET 0x00000008 - -// Counter -#define AUX_TIMER2_O_CNTR 0x0000000C - -// Clock Prescaler Configuration -#define AUX_TIMER2_O_PRECFG 0x00000010 - -// Event Control -#define AUX_TIMER2_O_EVCTL 0x00000014 - -// Pulse Trigger -#define AUX_TIMER2_O_PULSETRIG 0x00000018 - -// Channel 0 Event Configuration -#define AUX_TIMER2_O_CH0EVCFG 0x00000080 - -// Channel 0 Capture Configuration -#define AUX_TIMER2_O_CH0CCFG 0x00000084 - -// Channel 0 Pipeline Capture Compare -#define AUX_TIMER2_O_CH0PCC 0x00000088 - -// Channel 0 Capture Compare -#define AUX_TIMER2_O_CH0CC 0x0000008C - -// Channel 1 Event Configuration -#define AUX_TIMER2_O_CH1EVCFG 0x00000090 - -// Channel 1 Capture Configuration -#define AUX_TIMER2_O_CH1CCFG 0x00000094 - -// Channel 1 Pipeline Capture Compare -#define AUX_TIMER2_O_CH1PCC 0x00000098 - -// Channel 1 Capture Compare -#define AUX_TIMER2_O_CH1CC 0x0000009C - -// Channel 2 Event Configuration -#define AUX_TIMER2_O_CH2EVCFG 0x000000A0 - -// Channel 2 Capture Configuration -#define AUX_TIMER2_O_CH2CCFG 0x000000A4 - -// Channel 2 Pipeline Capture Compare -#define AUX_TIMER2_O_CH2PCC 0x000000A8 - -// Channel 2 Capture Compare -#define AUX_TIMER2_O_CH2CC 0x000000AC - -// Channel 3 Event Configuration -#define AUX_TIMER2_O_CH3EVCFG 0x000000B0 - -// Channel 3 Capture Configuration -#define AUX_TIMER2_O_CH3CCFG 0x000000B4 - -// Channel 3 Pipeline Capture Compare -#define AUX_TIMER2_O_CH3PCC 0x000000B8 - -// Channel 3 Capture Compare -#define AUX_TIMER2_O_CH3CC 0x000000BC - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CTL -// -//***************************************************************************** -// Field: [6] CH3_RESET -// -// Channel 3 reset. -// -// 0: No effect. -// 1: Reset CH3CC, CH3PCC, CH3EVCFG, and CH3CCFG. -// -// Read returns 0. -#define AUX_TIMER2_CTL_CH3_RESET 0x00000040 -#define AUX_TIMER2_CTL_CH3_RESET_BITN 6 -#define AUX_TIMER2_CTL_CH3_RESET_M 0x00000040 -#define AUX_TIMER2_CTL_CH3_RESET_S 6 - -// Field: [5] CH2_RESET -// -// Channel 2 reset. -// -// 0: No effect. -// 1: Reset CH2CC, CH2PCC, CH2EVCFG, and CH2CCFG. -// -// Read returns 0. -#define AUX_TIMER2_CTL_CH2_RESET 0x00000020 -#define AUX_TIMER2_CTL_CH2_RESET_BITN 5 -#define AUX_TIMER2_CTL_CH2_RESET_M 0x00000020 -#define AUX_TIMER2_CTL_CH2_RESET_S 5 - -// Field: [4] CH1_RESET -// -// Channel 1 reset. -// -// 0: No effect. -// 1: Reset CH1CC, CH1PCC, CH1EVCFG, and CH1CCFG. -// -// Read returns 0. -#define AUX_TIMER2_CTL_CH1_RESET 0x00000010 -#define AUX_TIMER2_CTL_CH1_RESET_BITN 4 -#define AUX_TIMER2_CTL_CH1_RESET_M 0x00000010 -#define AUX_TIMER2_CTL_CH1_RESET_S 4 - -// Field: [3] CH0_RESET -// -// Channel 0 reset. -// -// 0: No effect. -// 1: Reset CH0CC, CH0PCC, CH0EVCFG, and CH0CCFG. -// -// Read returns 0. -#define AUX_TIMER2_CTL_CH0_RESET 0x00000008 -#define AUX_TIMER2_CTL_CH0_RESET_BITN 3 -#define AUX_TIMER2_CTL_CH0_RESET_M 0x00000008 -#define AUX_TIMER2_CTL_CH0_RESET_S 3 - -// Field: [2] TARGET_EN -// -// Select counter target value. -// -// You must select TARGET to use shadow target functionality. -// ENUMs: -// TARGET TARGET.VALUE -// CNTR_MAX 65535 -#define AUX_TIMER2_CTL_TARGET_EN 0x00000004 -#define AUX_TIMER2_CTL_TARGET_EN_BITN 2 -#define AUX_TIMER2_CTL_TARGET_EN_M 0x00000004 -#define AUX_TIMER2_CTL_TARGET_EN_S 2 -#define AUX_TIMER2_CTL_TARGET_EN_TARGET 0x00000004 -#define AUX_TIMER2_CTL_TARGET_EN_CNTR_MAX 0x00000000 - -// Field: [1:0] MODE -// -// Timer mode control. -// -// The timer restarts from 0 when you set MODE to UP_ONCE, UP_PER, or -// UPDWN_PER. -// -// When you write MODE all internally queued updates to [CHnCC.*] and TARGET -// clear. -// ENUMs: -// UPDWN_PER Count up and down periodically. The timer counts -// from 0 to target value and back to 0, -// repeatedly. -// -// Period = (target value * -// 2) * timer clock period -// UP_PER Count up periodically. The timer increments from 0 -// to target value, repeatedly. -// -// Period = (target value + -// 1) * timer clock period -// UP_ONCE Count up once. The timer increments from 0 to -// target value, then stops and sets MODE to DIS. -// DIS Disable timer. Updates to counter, channels, and -// events stop. -#define AUX_TIMER2_CTL_MODE_W 2 -#define AUX_TIMER2_CTL_MODE_M 0x00000003 -#define AUX_TIMER2_CTL_MODE_S 0 -#define AUX_TIMER2_CTL_MODE_UPDWN_PER 0x00000003 -#define AUX_TIMER2_CTL_MODE_UP_PER 0x00000002 -#define AUX_TIMER2_CTL_MODE_UP_ONCE 0x00000001 -#define AUX_TIMER2_CTL_MODE_DIS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_TARGET -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// 16 bit user defined counter target value, which is used when selected by -// CTL.TARGET_EN. -#define AUX_TIMER2_TARGET_VALUE_W 16 -#define AUX_TIMER2_TARGET_VALUE_M 0x0000FFFF -#define AUX_TIMER2_TARGET_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_SHDWTARGET -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Target value for next counter period. -// -// The timer copies VALUE to TARGET.VALUE when CNTR.VALUE becomes 0. The copy -// does not happen when you restart the timer. -// -// This is useful to avoid period jitter in PWM applications with time-varying -// period, sometimes referenced as phase corrected PWM. -#define AUX_TIMER2_SHDWTARGET_VALUE_W 16 -#define AUX_TIMER2_SHDWTARGET_VALUE_M 0x0000FFFF -#define AUX_TIMER2_SHDWTARGET_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CNTR -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// 16 bit current counter value. -#define AUX_TIMER2_CNTR_VALUE_W 16 -#define AUX_TIMER2_CNTR_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CNTR_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_PRECFG -// -//***************************************************************************** -// Field: [7:0] CLKDIV -// -// Clock division. -// -// CLKDIV determines the timer clock frequency for counter, synchronization, -// and timer event updates. The timer clock frequency is the clock selected by -// AUX_SYSIF:TIMER2CLKCTL.SRC divided by (CLKDIV + 1). This inverse is the -// timer clock period. -// -// 0x00: Divide by 1. -// 0x01: Divide by 2. -// ... -// 0xFF: Divide by 256. -#define AUX_TIMER2_PRECFG_CLKDIV_W 8 -#define AUX_TIMER2_PRECFG_CLKDIV_M 0x000000FF -#define AUX_TIMER2_PRECFG_CLKDIV_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_EVCTL -// -//***************************************************************************** -// Field: [7] EV3_SET -// -// Set event 3. -// -// Write 1 to set event 3. -#define AUX_TIMER2_EVCTL_EV3_SET 0x00000080 -#define AUX_TIMER2_EVCTL_EV3_SET_BITN 7 -#define AUX_TIMER2_EVCTL_EV3_SET_M 0x00000080 -#define AUX_TIMER2_EVCTL_EV3_SET_S 7 - -// Field: [6] EV3_CLR -// -// Clear event 3. -// -// Write 1 to clear event 3. -#define AUX_TIMER2_EVCTL_EV3_CLR 0x00000040 -#define AUX_TIMER2_EVCTL_EV3_CLR_BITN 6 -#define AUX_TIMER2_EVCTL_EV3_CLR_M 0x00000040 -#define AUX_TIMER2_EVCTL_EV3_CLR_S 6 - -// Field: [5] EV2_SET -// -// Set event 2. -// -// Write 1 to set event 2. -#define AUX_TIMER2_EVCTL_EV2_SET 0x00000020 -#define AUX_TIMER2_EVCTL_EV2_SET_BITN 5 -#define AUX_TIMER2_EVCTL_EV2_SET_M 0x00000020 -#define AUX_TIMER2_EVCTL_EV2_SET_S 5 - -// Field: [4] EV2_CLR -// -// Clear event 2. -// -// Write 1 to clear event 2. -#define AUX_TIMER2_EVCTL_EV2_CLR 0x00000010 -#define AUX_TIMER2_EVCTL_EV2_CLR_BITN 4 -#define AUX_TIMER2_EVCTL_EV2_CLR_M 0x00000010 -#define AUX_TIMER2_EVCTL_EV2_CLR_S 4 - -// Field: [3] EV1_SET -// -// Set event 1. -// -// Write 1 to set event 1. -#define AUX_TIMER2_EVCTL_EV1_SET 0x00000008 -#define AUX_TIMER2_EVCTL_EV1_SET_BITN 3 -#define AUX_TIMER2_EVCTL_EV1_SET_M 0x00000008 -#define AUX_TIMER2_EVCTL_EV1_SET_S 3 - -// Field: [2] EV1_CLR -// -// Clear event 1. -// -// Write 1 to clear event 1. -#define AUX_TIMER2_EVCTL_EV1_CLR 0x00000004 -#define AUX_TIMER2_EVCTL_EV1_CLR_BITN 2 -#define AUX_TIMER2_EVCTL_EV1_CLR_M 0x00000004 -#define AUX_TIMER2_EVCTL_EV1_CLR_S 2 - -// Field: [1] EV0_SET -// -// Set event 0. -// -// Write 1 to set event 0. -#define AUX_TIMER2_EVCTL_EV0_SET 0x00000002 -#define AUX_TIMER2_EVCTL_EV0_SET_BITN 1 -#define AUX_TIMER2_EVCTL_EV0_SET_M 0x00000002 -#define AUX_TIMER2_EVCTL_EV0_SET_S 1 - -// Field: [0] EV0_CLR -// -// Clear event 0. -// -// Write 1 to clear event 0. -#define AUX_TIMER2_EVCTL_EV0_CLR 0x00000001 -#define AUX_TIMER2_EVCTL_EV0_CLR_BITN 0 -#define AUX_TIMER2_EVCTL_EV0_CLR_M 0x00000001 -#define AUX_TIMER2_EVCTL_EV0_CLR_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_PULSETRIG -// -//***************************************************************************** -// Field: [0] TRIG -// -// Pulse trigger. -// -// Write 1 to generate a pulse to AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. Pulse -// width equals the duty cycle of AUX_SYSIF:TIMER2CLKCTL.SRC. -#define AUX_TIMER2_PULSETRIG_TRIG 0x00000001 -#define AUX_TIMER2_PULSETRIG_TRIG_BITN 0 -#define AUX_TIMER2_PULSETRIG_TRIG_M 0x00000001 -#define AUX_TIMER2_PULSETRIG_TRIG_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH0EVCFG -// -//***************************************************************************** -// Field: [7] EV3_GEN -// -// Event 3 enable. -// -// 0: Channel 0 does not control event 3. -// 1: Channel 0 controls event 3. -// -// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH0EVCFG_EV3_GEN 0x00000080 -#define AUX_TIMER2_CH0EVCFG_EV3_GEN_BITN 7 -#define AUX_TIMER2_CH0EVCFG_EV3_GEN_M 0x00000080 -#define AUX_TIMER2_CH0EVCFG_EV3_GEN_S 7 - -// Field: [6] EV2_GEN -// -// Event 2 enable. -// -// 0: Channel 0 does not control event 2. -// 1: Channel 0 controls event 2. -// -// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH0EVCFG_EV2_GEN 0x00000040 -#define AUX_TIMER2_CH0EVCFG_EV2_GEN_BITN 6 -#define AUX_TIMER2_CH0EVCFG_EV2_GEN_M 0x00000040 -#define AUX_TIMER2_CH0EVCFG_EV2_GEN_S 6 - -// Field: [5] EV1_GEN -// -// Event 1 enable. -// -// 0: Channel 0 does not control event 1. -// 1: Channel 0 controls event 1. -// -// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH0EVCFG_EV1_GEN 0x00000020 -#define AUX_TIMER2_CH0EVCFG_EV1_GEN_BITN 5 -#define AUX_TIMER2_CH0EVCFG_EV1_GEN_M 0x00000020 -#define AUX_TIMER2_CH0EVCFG_EV1_GEN_S 5 - -// Field: [4] EV0_GEN -// -// Event 0 enable. -// -// 0: Channel 0 does not control event 0. -// 1: Channel 0 controls event 0. -// -// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH0EVCFG_EV0_GEN 0x00000010 -#define AUX_TIMER2_CH0EVCFG_EV0_GEN_BITN 4 -#define AUX_TIMER2_CH0EVCFG_EV0_GEN_M 0x00000010 -#define AUX_TIMER2_CH0EVCFG_EV0_GEN_S 4 - -// Field: [3:0] CCACT -// -// Capture-Compare action. -// -// Capture-Compare action defines 15 different channel functions that utilize -// capture, compare, and zero events. -// ENUMs: -// PULSE_ON_CMP Pulse on compare repeatedly. -// -// Channel function -// sequence: -// - Pulse enabled events -// when CH0CC.VALUE = CNTR.VALUE. -// -// The event is high for -// two timer clock periods. -// TGL_ON_CMP Toggle on compare repeatedly. -// -// Channel function -// sequence: -// - Toggle enabled events -// when CH0CC.VALUE = CNTR.VALUE. -// SET_ON_CMP Set on compare repeatedly. -// -// Channel function -// sequence: -// - Set enabled events -// when CH0CC.VALUE = CNTR.VALUE. -// CLR_ON_CMP Clear on compare repeatedly. -// -// Channel function -// sequence: -// - Clear enabled events -// when CH0CC.VALUE = CNTR.VALUE. -// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. -// -// Channel function -// sequence: -// - Set enabled events when -// CNTR.VALUE = 0. -// - Toggle enabled events -// when CH0CC.VALUE = CNTR.VALUE. -// -// Set CTL.MODE to UP_PER -// for edge-aligned PWM generation. Duty cycle is -// given by: -// -// When CH0CC.VALUE <= -// TARGET.VALUE: -// Duty cycle = -// CH0CC.VALUE / ( TARGET.VALUE + 1 ). -// -// When CH0CC.VALUE > -// TARGET.VALUE: -// Duty cycle = 1. -// -// Enabled events are -// cleared when CH0CC.VALUE = 0 and CNTR.VALUE = -// 0. -// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. -// -// Channel function -// sequence: -// - Clear enabled events -// when CNTR.VALUE = 0. -// - Toggle enabled events -// when CH0CC.VALUE = CNTR.VALUE. -// -// Set CTL.MODE to UPDWN_PER -// for center-aligned PWM generation. Duty cycle -// is given by: -// -// When CH0CC.VALUE <= -// TARGET.VALUE: -// Duty cycle = 1 - ( -// CH0CC.VALUE / TARGET.VALUE ). -// -// When CH0CC.VALUE > -// TARGET.VALUE: -// Duty cycle = 0. -// -// Enabled events are set -// when CH0CC.VALUE = 0 and CNTR.VALUE = 0. -// SET_ON_CAPT Set on capture repeatedly. -// -// Channel function -// sequence: -// - Set enabled events on -// capture event and copy CNTR.VALUE to -// CH0CC.VALUE. -// -// Primary use scenario is -// to select this function before you start the -// timer. -// Follow these steps if you -// need to select this function while CTL.MODE is -// different from DIS: -// - Select this function -// with no event enable. -// - Configure CH0CCFG -// (optional). -// - Wait for three timer -// clock periods as defined in PRECFG before you -// enable events. -// -// These steps prevent -// capture events caused by expired signal values -// in edge-detection circuit. -// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. -// -// Continuously capture -// period and pulse width of the signal selected -// by CH0CCFG.CAPT_SRC relative to the signal edge -// given by CH0CCFG.EDGE. -// -// Set enabled events when -// CH0CC.VALUE contains signal period and -// CH0PCC.VALUE contains signal pulse width. -// -// Notes: -// - Make sure that you -// configure CH0CCFG.CAPT_SRC and CCACT when -// CTL.MODE equals DIS, then set CTL.MODE to -// UP_ONCE or UP_PER. -// - The counter restarts in -// the selected timer mode when CH0CC.VALUE -// contains the signal period. -// - If more than one -// channel uses this function, the channels will -// perform this function one at a time. The -// channel with lowest number has priority and -// performs the function first. Next measurement -// starts when current measurement completes -// successfully or times out. A timeout occurs -// when counter equals target. -// - If you want to observe -// a timeout event configure another channel to -// SET_ON_CAPT. -// -// Signal property -// requirements: -// - Signal Period >= 2 * ( -// 1 + PRECFG.CLKDIV ) * timer clock period. -// - Signal Period <= 65535 -// * (1 + PRECFG.CLKDIV ) * timer clock period. -// - Signal low and high -// phase >= (1 + PRECFG.CLKDIV ) * timer clock -// period. -// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. -// -// Channel function -// sequence: -// - Pulse enabled events -// when CH0CC.VALUE = CNTR.VALUE. -// - Disable channel. -// -// The event is high for -// two timer clock periods. -// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. -// -// Channel function -// sequence: -// - Toggle enabled events -// when CH0CC.VALUE = CNTR.VALUE. -// - Disable channel. -// SET_ON_CMP_DIS Set on compare, and then disable channel. -// -// Channel function -// sequence: -// - Set enabled events when -// CH0CC.VALUE = CNTR.VALUE. -// - Disable channel. -// CLR_ON_CMP_DIS Clear on compare, and then disable channel. -// -// Channel function -// sequence: -// - Clear enabled events -// when CH0CC.VALUE = CNTR.VALUE. -// - Disable channel. -// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable -// channel. -// -// Channel function -// sequence: -// - Set enabled events when -// CNTR.VALUE = 0. -// - Toggle enabled events -// when CH0CC.VALUE = CNTR.VALUE. -// - Disable channel. -// -// Enabled events are -// cleared when CH0CC.VALUE = 0 and CNTR.VALUE = -// 0. -// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable -// channel. -// -// Channel function -// sequence: -// - Clear enabled events -// when CNTR.VALUE = 0. -// - Toggle enabled events -// when CH0CC.VALUE = CNTR.VALUE. -// - Disable channel. -// -// Enabled events are set -// when CH0CC.VALUE = 0 and CNTR.VALUE = 0. -// SET_ON_CAPT_DIS Set on capture, and then disable channel. -// -// Channel function -// sequence: -// - Set enabled events on -// capture event and copy CNTR.VALUE to -// CH0CC.VALUE. -// - Disable channel. -// -// Primary use scenario is -// to select this function before you start the -// timer. -// Follow these steps if you -// need to select this function while CTL.MODE is -// different from DIS: -// - Set CCACT to -// SET_ON_CAPT with no event enable. -// - Configure CH0CCFG -// (optional). -// - Wait for three timer -// clock periods as defined in PRECFG before you -// set CCACT to SET_ON_CAPT_DIS. Event enable is -// optional. -// -// These steps prevent -// capture events caused by expired signal values -// in edge-detection circuit. -// DIS Disable channel. -#define AUX_TIMER2_CH0EVCFG_CCACT_W 4 -#define AUX_TIMER2_CH0EVCFG_CCACT_M 0x0000000F -#define AUX_TIMER2_CH0EVCFG_CCACT_S 0 -#define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP 0x0000000F -#define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP 0x0000000E -#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP 0x0000000D -#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP 0x0000000C -#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B -#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A -#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT 0x00000009 -#define AUX_TIMER2_CH0EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 -#define AUX_TIMER2_CH0EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 -#define AUX_TIMER2_CH0EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 -#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 -#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 -#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 -#define AUX_TIMER2_CH0EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 -#define AUX_TIMER2_CH0EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 -#define AUX_TIMER2_CH0EVCFG_CCACT_DIS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH0CCFG -// -//***************************************************************************** -// Field: [6:1] CAPT_SRC -// -// Select capture signal source from the asynchronous AUX event bus. -// -// The selected signal enters the edge-detection circuit. False capture events -// can occur when: -// - the edge-detection circuit contains expired signal samples and the circuit -// is enabled without flush as described in CH0EVCFG -// - this register is reconfigured while CTL.MODE is different from DIS. -// -// You can avoid false capture events. When wanted channel function is: -// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH0EVCFG.CCACT. -// - SET_ON_CAPT, see description for SET_ON_CAPT in CH0EVCFG.CCACT. -// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in -// CH0EVCFG.CCACT. -// -// If you write a non-enumerated value the behavior is identical to NO_EVENT. -// The written value is returned when read. -// ENUMs: -// NO_EVENT No event. -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_W 6 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_M 0x0000007E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_S 1 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_NO_EVENT 0x0000007E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPB 0x0000005E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUX_COMPA 0x0000005C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_EV 0x00000056 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_ACLK_REF 0x00000054 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_PWR_DWN 0x0000004E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_SCLK_LF 0x0000004C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_MANUAL_EV 0x00000040 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO31 0x0000003E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO30 0x0000003C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO29 0x0000003A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO28 0x00000038 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO27 0x00000036 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO26 0x00000034 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO25 0x00000032 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO24 0x00000030 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO23 0x0000002E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO22 0x0000002C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO21 0x0000002A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO20 0x00000028 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO19 0x00000026 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO18 0x00000024 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO17 0x00000022 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO16 0x00000020 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO15 0x0000001E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO14 0x0000001C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO13 0x0000001A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO12 0x00000018 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO11 0x00000016 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO10 0x00000014 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO9 0x00000012 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO8 0x00000010 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO7 0x0000000E -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO6 0x0000000C -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO5 0x0000000A -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO4 0x00000008 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO3 0x00000006 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO2 0x00000004 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO1 0x00000002 -#define AUX_TIMER2_CH0CCFG_CAPT_SRC_AUXIO0 0x00000000 - -// Field: [0] EDGE -// -// Edge configuration. -// -// Channel captures counter value at selected edge on signal source selected by -// CAPT_SRC. See CH0EVCFG.CCACT. -// ENUMs: -// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. -// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. -#define AUX_TIMER2_CH0CCFG_EDGE 0x00000001 -#define AUX_TIMER2_CH0CCFG_EDGE_BITN 0 -#define AUX_TIMER2_CH0CCFG_EDGE_M 0x00000001 -#define AUX_TIMER2_CH0CCFG_EDGE_S 0 -#define AUX_TIMER2_CH0CCFG_EDGE_RISING 0x00000001 -#define AUX_TIMER2_CH0CCFG_EDGE_FALLING 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH0PCC -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Pipeline Capture Compare value. -// -// 16-bit user defined pipeline compare value or channel-updated capture value. -// -// Compare mode: -// An update of VALUE will be transferred to CH0CC.VALUE when the next -// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for -// PWM generation and prevents jitter on the edges of the generated signal. -// -// Capture mode: -// When CH0EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the -// width of the low or high phase of the selected signal. This is specified by -// CH0CCFG.EDGE and CH0CCFG.CAPT_SRC. -#define AUX_TIMER2_CH0PCC_VALUE_W 16 -#define AUX_TIMER2_CH0PCC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH0PCC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH0CC -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Capture Compare value. -// -// 16-bit user defined compare value or channel-updated capture value. -// -// Compare mode: -// VALUE is compared against CNTR.VALUE and an event is generated as specified -// by CH0EVCFG.CCACT when these are equal. -// -// Capture mode: -// The current counter value is stored in VALUE when a capture event occurs. -// CH0EVCFG.CCACT determines if VALUE is a signal period or a regular capture -// value. -#define AUX_TIMER2_CH0CC_VALUE_W 16 -#define AUX_TIMER2_CH0CC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH0CC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH1EVCFG -// -//***************************************************************************** -// Field: [7] EV3_GEN -// -// Event 3 enable. -// -// 0: Channel 1 does not control event 3. -// 1: Channel 1 controls event 3. -// -// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH1EVCFG_EV3_GEN 0x00000080 -#define AUX_TIMER2_CH1EVCFG_EV3_GEN_BITN 7 -#define AUX_TIMER2_CH1EVCFG_EV3_GEN_M 0x00000080 -#define AUX_TIMER2_CH1EVCFG_EV3_GEN_S 7 - -// Field: [6] EV2_GEN -// -// Event 2 enable. -// -// 0: Channel 1 does not control event 2. -// 1: Channel 1 controls event 2. -// -// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH1EVCFG_EV2_GEN 0x00000040 -#define AUX_TIMER2_CH1EVCFG_EV2_GEN_BITN 6 -#define AUX_TIMER2_CH1EVCFG_EV2_GEN_M 0x00000040 -#define AUX_TIMER2_CH1EVCFG_EV2_GEN_S 6 - -// Field: [5] EV1_GEN -// -// Event 1 enable. -// -// 0: Channel 1 does not control event 1. -// 1: Channel 1 controls event 1. -// -// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH1EVCFG_EV1_GEN 0x00000020 -#define AUX_TIMER2_CH1EVCFG_EV1_GEN_BITN 5 -#define AUX_TIMER2_CH1EVCFG_EV1_GEN_M 0x00000020 -#define AUX_TIMER2_CH1EVCFG_EV1_GEN_S 5 - -// Field: [4] EV0_GEN -// -// Event 0 enable. -// -// 0: Channel 1 does not control event 0. -// 1: Channel 1 controls event 0. -// -// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH1EVCFG_EV0_GEN 0x00000010 -#define AUX_TIMER2_CH1EVCFG_EV0_GEN_BITN 4 -#define AUX_TIMER2_CH1EVCFG_EV0_GEN_M 0x00000010 -#define AUX_TIMER2_CH1EVCFG_EV0_GEN_S 4 - -// Field: [3:0] CCACT -// -// Capture-Compare action. -// -// Capture-Compare action defines 15 different channel functions that utilize -// capture, compare, and zero events. -// ENUMs: -// PULSE_ON_CMP Pulse on compare repeatedly. -// -// Channel function -// sequence: -// - Pulse enabled events -// when CH1CC.VALUE = CNTR.VALUE. -// -// The event is high for -// two timer clock periods. -// TGL_ON_CMP Toggle on compare repeatedly. -// -// Channel function -// sequence: -// - Toggle enabled events -// when CH1CC.VALUE = CNTR.VALUE. -// SET_ON_CMP Set on compare repeatedly. -// -// Channel function -// sequence: -// - Set enabled events -// when CH1CC.VALUE = CNTR.VALUE. -// CLR_ON_CMP Clear on compare repeatedly. -// -// Channel function -// sequence: -// - Clear enabled events -// when CH1CC.VALUE = CNTR.VALUE. -// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. -// -// Channel function -// sequence: -// - Set enabled events when -// CNTR.VALUE = 0. -// - Toggle enabled events -// when CH1CC.VALUE = CNTR.VALUE. -// -// Set CTL.MODE to UP_PER -// for edge-aligned PWM generation. Duty cycle is -// given by: -// -// When CH1CC.VALUE <= -// TARGET.VALUE: -// Duty cycle = -// CH1CC.VALUE / ( TARGET.VALUE + 1 ). -// -// When CH1CC.VALUE > -// TARGET.VALUE: -// Duty cycle = 1. -// -// Enabled events are -// cleared when CH1CC.VALUE = 0 and CNTR.VALUE = -// 0. -// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. -// -// Channel function -// sequence: -// - Clear enabled events -// when CNTR.VALUE = 0. -// - Toggle enabled events -// when CH1CC.VALUE = CNTR.VALUE. -// -// Set CTL.MODE to UPDWN_PER -// for center-aligned PWM generation. Duty cycle -// is given by: -// -// When CH1CC.VALUE <= -// TARGET.VALUE: -// Duty cycle = 1 - ( -// CH1CC.VALUE / TARGET.VALUE ). -// -// When CH1CC.VALUE > -// TARGET.VALUE: -// Duty cycle = 0. -// -// Enabled events are set -// when CH1CC.VALUE = 0 and CNTR.VALUE = 0. -// SET_ON_CAPT Set on capture repeatedly. -// -// Channel function -// sequence: -// - Set enabled events on -// capture event and copy CNTR.VALUE to -// CH1CC.VALUE. -// -// Primary use scenario is -// to select this function before you start the -// timer. -// Follow these steps if you -// need to select this function while CTL.MODE is -// different from DIS: -// - Select this function -// with no event enable. -// - Configure CH1CCFG -// (optional). -// - Wait for three timer -// clock periods as defined in PRECFG before you -// enable events. -// -// These steps prevent -// capture events caused by expired signal values -// in edge-detection circuit. -// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. -// -// Continuously capture -// period and pulse width of the signal selected -// by CH1CCFG.CAPT_SRC relative to the signal edge -// given by CH1CCFG.EDGE. -// -// Set enabled events when -// CH1CC.VALUE contains signal period and -// CH1PCC.VALUE contains signal pulse width. -// -// Notes: -// - Make sure that you -// configure CH1CCFG.CAPT_SRC and CCACT when -// CTL.MODE equals DIS, then set CTL.MODE to -// UP_ONCE or UP_PER. -// - The counter restarts in -// the selected timer mode when CH1CC.VALUE -// contains the signal period. -// - If more than one -// channel uses this function, the channels will -// perform this function one at a time. The -// channel with lowest number has priority and -// performs the function first. Next measurement -// starts when current measurement completes -// successfully or times out. A timeout occurs -// when counter equals target. -// - If you want to observe -// a timeout event configure another channel to -// SET_ON_CAPT. -// -// Signal property -// requirements: -// - Signal Period >= 2 * ( -// 1 + PRECFG.CLKDIV ) * timer clock period. -// - Signal Period <= 65535 -// * (1 + PRECFG.CLKDIV ) * timer clock period. -// - Signal low and high -// phase >= (1 + PRECFG.CLKDIV ) * timer clock -// period. -// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. -// -// Channel function -// sequence: -// - Pulse enabled events -// when CH1CC.VALUE = CNTR.VALUE. -// - Disable channel. -// -// The event is high for -// two timer clock periods. -// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. -// -// Channel function -// sequence: -// - Toggle enabled events -// when CH1CC.VALUE = CNTR.VALUE. -// - Disable channel. -// SET_ON_CMP_DIS Set on compare, and then disable channel. -// -// Channel function -// sequence: -// - Set enabled events when -// CH1CC.VALUE = CNTR.VALUE. -// - Disable channel. -// CLR_ON_CMP_DIS Clear on compare, and then disable channel. -// -// Channel function -// sequence: -// - Clear enabled events -// when CH1CC.VALUE = CNTR.VALUE. -// - Disable channel. -// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable -// channel. -// -// Channel function -// sequence: -// - Set enabled events when -// CNTR.VALUE = 0. -// - Toggle enabled events -// when CH1CC.VALUE = CNTR.VALUE. -// - Disable channel. -// -// Enabled events are -// cleared when CH1CC.VALUE = 0 and CNTR.VALUE = -// 0. -// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable -// channel. -// -// Channel function -// sequence: -// - Clear enabled events -// when CNTR.VALUE = 0. -// - Toggle enabled events -// when CH1CC.VALUE = CNTR.VALUE. -// - Disable channel. -// -// Enabled events are set -// when CH1CC.VALUE = 0 and CNTR.VALUE = 0. -// SET_ON_CAPT_DIS Set on capture, and then disable channel. -// -// Channel function -// sequence: -// - Set enabled events on -// capture event and copy CNTR.VALUE to -// CH1CC.VALUE. -// - Disable channel. -// -// Primary use scenario is -// to select this function before you start the -// timer. -// Follow these steps if you -// need to select this function while CTL.MODE is -// different from DIS: -// - Set CCACT to -// SET_ON_CAPT with no event enable. -// - Configure CH1CCFG -// (optional). -// - Wait for three timer -// clock periods as defined in PRECFG before you -// set CCACT to SET_ON_CAPT_DIS. Event enable is -// optional. -// -// These steps prevent -// capture events caused by expired signal values -// in edge-detection circuit. -// DIS Disable channel. -#define AUX_TIMER2_CH1EVCFG_CCACT_W 4 -#define AUX_TIMER2_CH1EVCFG_CCACT_M 0x0000000F -#define AUX_TIMER2_CH1EVCFG_CCACT_S 0 -#define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP 0x0000000F -#define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP 0x0000000E -#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP 0x0000000D -#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP 0x0000000C -#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B -#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A -#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT 0x00000009 -#define AUX_TIMER2_CH1EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 -#define AUX_TIMER2_CH1EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 -#define AUX_TIMER2_CH1EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 -#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 -#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 -#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 -#define AUX_TIMER2_CH1EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 -#define AUX_TIMER2_CH1EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 -#define AUX_TIMER2_CH1EVCFG_CCACT_DIS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH1CCFG -// -//***************************************************************************** -// Field: [6:1] CAPT_SRC -// -// Select capture signal source from the asynchronous AUX event bus. -// -// The selected signal enters the edge-detection circuit. False capture events -// can occur when: -// - the edge-detection circuit contains expired signal samples and the circuit -// is enabled without flush as described in CH1EVCFG -// - this register is reconfigured while CTL.MODE is different from DIS. -// -// You can avoid false capture events. When wanted channel function is: -// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH1EVCFG.CCACT. -// - SET_ON_CAPT, see description for SET_ON_CAPT in CH1EVCFG.CCACT. -// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in -// CH1EVCFG.CCACT. -// -// If you write a non-enumerated value the behavior is identical to NO_EVENT. -// The written value is returned when read. -// ENUMs: -// NO_EVENT No event. -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_W 6 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_M 0x0000007E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_S 1 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_NO_EVENT 0x0000007E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPB 0x0000005E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUX_COMPA 0x0000005C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_EV 0x00000056 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_ACLK_REF 0x00000054 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_PWR_DWN 0x0000004E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_SCLK_LF 0x0000004C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_MANUAL_EV 0x00000040 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO31 0x0000003E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO30 0x0000003C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO29 0x0000003A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO28 0x00000038 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO27 0x00000036 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO26 0x00000034 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO25 0x00000032 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO24 0x00000030 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO23 0x0000002E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO22 0x0000002C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO21 0x0000002A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO20 0x00000028 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO19 0x00000026 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO18 0x00000024 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO17 0x00000022 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO16 0x00000020 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO15 0x0000001E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO14 0x0000001C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO13 0x0000001A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO12 0x00000018 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO11 0x00000016 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO10 0x00000014 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO9 0x00000012 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO8 0x00000010 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO7 0x0000000E -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO6 0x0000000C -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO5 0x0000000A -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO4 0x00000008 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO3 0x00000006 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO2 0x00000004 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO1 0x00000002 -#define AUX_TIMER2_CH1CCFG_CAPT_SRC_AUXIO0 0x00000000 - -// Field: [0] EDGE -// -// Edge configuration. -// -// Channel captures counter value at selected edge on signal source selected by -// CAPT_SRC. See CH1EVCFG.CCACT. -// ENUMs: -// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. -// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. -#define AUX_TIMER2_CH1CCFG_EDGE 0x00000001 -#define AUX_TIMER2_CH1CCFG_EDGE_BITN 0 -#define AUX_TIMER2_CH1CCFG_EDGE_M 0x00000001 -#define AUX_TIMER2_CH1CCFG_EDGE_S 0 -#define AUX_TIMER2_CH1CCFG_EDGE_RISING 0x00000001 -#define AUX_TIMER2_CH1CCFG_EDGE_FALLING 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH1PCC -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Pipeline Capture Compare value. -// -// 16-bit user defined pipeline compare value or channel-updated capture value. -// -// Compare mode: -// An update of VALUE will be transferred to CH1CC.VALUE when the next -// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for -// PWM generation and prevents jitter on the edges of the generated signal. -// -// Capture mode: -// When CH1EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the -// width of the low or high phase of the selected signal. This is specified by -// CH1CCFG.EDGE and CH1CCFG.CAPT_SRC. -#define AUX_TIMER2_CH1PCC_VALUE_W 16 -#define AUX_TIMER2_CH1PCC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH1PCC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH1CC -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Capture Compare value. -// -// 16-bit user defined compare value or channel-updated capture value. -// -// Compare mode: -// VALUE is compared against CNTR.VALUE and an event is generated as specified -// by CH1EVCFG.CCACT when these are equal. -// -// Capture mode: -// The current counter value is stored in VALUE when a capture event occurs. -// CH1EVCFG.CCACT determines if VALUE is a signal period or a regular capture -// value. -#define AUX_TIMER2_CH1CC_VALUE_W 16 -#define AUX_TIMER2_CH1CC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH1CC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH2EVCFG -// -//***************************************************************************** -// Field: [7] EV3_GEN -// -// Event 3 enable. -// -// 0: Channel 2 does not control event 3. -// 1: Channel 2 controls event 3. -// -// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH2EVCFG_EV3_GEN 0x00000080 -#define AUX_TIMER2_CH2EVCFG_EV3_GEN_BITN 7 -#define AUX_TIMER2_CH2EVCFG_EV3_GEN_M 0x00000080 -#define AUX_TIMER2_CH2EVCFG_EV3_GEN_S 7 - -// Field: [6] EV2_GEN -// -// Event 2 enable. -// -// 0: Channel 2 does not control event 2. -// 1: Channel 2 controls event 2. -// -// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH2EVCFG_EV2_GEN 0x00000040 -#define AUX_TIMER2_CH2EVCFG_EV2_GEN_BITN 6 -#define AUX_TIMER2_CH2EVCFG_EV2_GEN_M 0x00000040 -#define AUX_TIMER2_CH2EVCFG_EV2_GEN_S 6 - -// Field: [5] EV1_GEN -// -// Event 1 enable. -// -// 0: Channel 2 does not control event 1. -// 1: Channel 2 controls event 1. -// -// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH2EVCFG_EV1_GEN 0x00000020 -#define AUX_TIMER2_CH2EVCFG_EV1_GEN_BITN 5 -#define AUX_TIMER2_CH2EVCFG_EV1_GEN_M 0x00000020 -#define AUX_TIMER2_CH2EVCFG_EV1_GEN_S 5 - -// Field: [4] EV0_GEN -// -// Event 0 enable. -// -// 0: Channel 2 does not control event 0. -// 1: Channel 2 controls event 0. -// -// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH2EVCFG_EV0_GEN 0x00000010 -#define AUX_TIMER2_CH2EVCFG_EV0_GEN_BITN 4 -#define AUX_TIMER2_CH2EVCFG_EV0_GEN_M 0x00000010 -#define AUX_TIMER2_CH2EVCFG_EV0_GEN_S 4 - -// Field: [3:0] CCACT -// -// Capture-Compare action. -// -// Capture-Compare action defines 15 different channel functions that utilize -// capture, compare, and zero events. -// ENUMs: -// PULSE_ON_CMP Pulse on compare repeatedly. -// -// Channel function -// sequence: -// - Pulse enabled events -// when CH2CC.VALUE = CNTR.VALUE. -// -// The event is high for -// two timer clock periods. -// TGL_ON_CMP Toggle on compare repeatedly. -// -// Channel function -// sequence: -// - Toggle enabled events -// when CH2CC.VALUE = CNTR.VALUE. -// SET_ON_CMP Set on compare repeatedly. -// -// Channel function -// sequence: -// - Set enabled events -// when CH2CC.VALUE = CNTR.VALUE. -// CLR_ON_CMP Clear on compare repeatedly. -// -// Channel function -// sequence: -// - Clear enabled events -// when CH2CC.VALUE = CNTR.VALUE. -// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. -// -// Channel function -// sequence: -// - Set enabled events when -// CNTR.VALUE = 0. -// - Toggle enabled events -// when CH2CC.VALUE = CNTR.VALUE. -// -// Set CTL.MODE to UP_PER -// for edge-aligned PWM generation. Duty cycle is -// given by: -// -// When CH2CC.VALUE <= -// TARGET.VALUE: -// Duty cycle = -// CH2CC.VALUE / ( TARGET.VALUE + 1 ). -// -// When CH2CC.VALUE > -// TARGET.VALUE: -// Duty cycle = 1. -// -// Enabled events are -// cleared when CH2CC.VALUE = 0 and CNTR.VALUE = -// 0. -// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. -// -// Channel function -// sequence: -// - Clear enabled events -// when CNTR.VALUE = 0. -// - Toggle enabled events -// when CH2CC.VALUE = CNTR.VALUE. -// -// Set CTL.MODE to UPDWN_PER -// for center-aligned PWM generation. Duty cycle -// is given by: -// -// When CH2CC.VALUE <= -// TARGET.VALUE: -// Duty cycle = 1 - ( -// CH2CC.VALUE / TARGET.VALUE ). -// -// When CH2CC.VALUE > -// TARGET.VALUE: -// Duty cycle = 0. -// -// Enabled events are set -// when CH2CC.VALUE = 0 and CNTR.VALUE = 0. -// SET_ON_CAPT Set on capture repeatedly. -// -// Channel function -// sequence: -// - Set enabled events on -// capture event and copy CNTR.VALUE to -// CH2CC.VALUE. -// -// Primary use scenario is -// to select this function before you start the -// timer. -// Follow these steps if you -// need to select this function while CTL.MODE is -// different from DIS: -// - Select this function -// with no event enable. -// - Configure CH2CCFG -// (optional). -// - Wait for three timer -// clock periods as defined in PRECFG before you -// enable events. -// -// These steps prevent -// capture events caused by expired signal values -// in edge-detection circuit. -// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. -// -// Continuously capture -// period and pulse width of the signal selected -// by CH2CCFG.CAPT_SRC relative to the signal edge -// given by CH2CCFG.EDGE. -// -// Set enabled events when -// CH2CC.VALUE contains signal period and -// CH2PCC.VALUE contains signal pulse width. -// -// Notes: -// - Make sure that you -// configure CH2CCFG.CAPT_SRC and CCACT when -// CTL.MODE equals DIS, then set CTL.MODE to -// UP_ONCE or UP_PER. -// - The counter restarts in -// the selected timer mode when CH2CC.VALUE -// contains the signal period. -// - If more than one -// channel uses this function, the channels will -// perform this function one at a time. The -// channel with lowest number has priority and -// performs the function first. Next measurement -// starts when current measurement completes -// successfully or times out. A timeout occurs -// when counter equals target. -// - If you want to observe -// a timeout event configure another channel to -// SET_ON_CAPT. -// -// Signal property -// requirements: -// - Signal Period >= 2 * ( -// 1 + PRECFG.CLKDIV ) * timer clock period. -// - Signal Period <= 65535 -// * (1 + PRECFG.CLKDIV ) * timer clock period. -// - Signal low and high -// phase >= (1 + PRECFG.CLKDIV ) * timer clock -// period. -// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. -// -// Channel function -// sequence: -// - Pulse enabled events -// when CH2CC.VALUE = CNTR.VALUE. -// - Disable channel. -// -// The event is high for -// two timer clock periods. -// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. -// -// Channel function -// sequence: -// - Toggle enabled events -// when CH2CC.VALUE = CNTR.VALUE. -// - Disable channel. -// SET_ON_CMP_DIS Set on compare, and then disable channel. -// -// Channel function -// sequence: -// - Set enabled events when -// CH2CC.VALUE = CNTR.VALUE. -// - Disable channel. -// CLR_ON_CMP_DIS Clear on compare, and then disable channel. -// -// Channel function -// sequence: -// - Clear enabled events -// when CH2CC.VALUE = CNTR.VALUE. -// - Disable channel. -// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable -// channel. -// -// Channel function -// sequence: -// - Set enabled events when -// CNTR.VALUE = 0. -// - Toggle enabled events -// when CH2CC.VALUE = CNTR.VALUE. -// - Disable channel. -// -// Enabled events are -// cleared when CH2CC.VALUE = 0 and CNTR.VALUE = -// 0. -// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable -// channel. -// -// Channel function -// sequence: -// - Clear enabled events -// when CNTR.VALUE = 0. -// - Toggle enabled events -// when CH2CC.VALUE = CNTR.VALUE. -// - Disable channel. -// -// Enabled events are set -// when CH2CC.VALUE = 0 and CNTR.VALUE = 0. -// SET_ON_CAPT_DIS Set on capture, and then disable channel. -// -// Channel function -// sequence: -// - Set enabled events on -// capture event and copy CNTR.VALUE to -// CH2CC.VALUE. -// - Disable channel. -// -// Primary use scenario is -// to select this function before you start the -// timer. -// Follow these steps if you -// need to select this function while CTL.MODE is -// different from DIS: -// - Set to SET_ON_CAPT -// with no event enable. -// - Configure CH2CCFG -// (optional). -// - Wait for three timer -// clock periods as defined in PRECFG before you -// set to SET_ON_CAPT_DIS. Event enable is -// optional. -// -// These steps prevent -// capture events caused by expired signal values -// in edge-detection circuit. -// DIS Disable channel. -#define AUX_TIMER2_CH2EVCFG_CCACT_W 4 -#define AUX_TIMER2_CH2EVCFG_CCACT_M 0x0000000F -#define AUX_TIMER2_CH2EVCFG_CCACT_S 0 -#define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP 0x0000000F -#define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP 0x0000000E -#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP 0x0000000D -#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP 0x0000000C -#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B -#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A -#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT 0x00000009 -#define AUX_TIMER2_CH2EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 -#define AUX_TIMER2_CH2EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 -#define AUX_TIMER2_CH2EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 -#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 -#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 -#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 -#define AUX_TIMER2_CH2EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 -#define AUX_TIMER2_CH2EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 -#define AUX_TIMER2_CH2EVCFG_CCACT_DIS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH2CCFG -// -//***************************************************************************** -// Field: [6:1] CAPT_SRC -// -// Select capture signal source from the asynchronous AUX event bus. -// -// The selected signal enters the edge-detection circuit. False capture events -// can occur when: -// - the edge-detection circuit contains expired signal samples and the circuit -// is enabled without flush as described in CH2EVCFG -// - this register is reconfigured while CTL.MODE is different from DIS. -// -// You can avoid false capture events. When wanted channel function is: -// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH2EVCFG.CCACT. -// - SET_ON_CAPT, see description for SET_ON_CAPT in CH2EVCFG.CCACT. -// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in -// CH2EVCFG.CCACT. -// -// If you write a non-enumerated value the behavior is identical to NO_EVENT. -// The written value is returned when read. -// ENUMs: -// NO_EVENT No event. -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_W 6 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_M 0x0000007E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_S 1 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_NO_EVENT 0x0000007E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPB 0x0000005E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUX_COMPA 0x0000005C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_EV 0x00000056 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_ACLK_REF 0x00000054 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_PWR_DWN 0x0000004E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_SCLK_LF 0x0000004C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_MANUAL_EV 0x00000040 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO31 0x0000003E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO30 0x0000003C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO29 0x0000003A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO28 0x00000038 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO27 0x00000036 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO26 0x00000034 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO25 0x00000032 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO24 0x00000030 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO23 0x0000002E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO22 0x0000002C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO21 0x0000002A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO20 0x00000028 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO19 0x00000026 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO18 0x00000024 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO17 0x00000022 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO16 0x00000020 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO15 0x0000001E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO14 0x0000001C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO13 0x0000001A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO12 0x00000018 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO11 0x00000016 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO10 0x00000014 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO9 0x00000012 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO8 0x00000010 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO7 0x0000000E -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO6 0x0000000C -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO5 0x0000000A -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO4 0x00000008 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO3 0x00000006 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO2 0x00000004 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO1 0x00000002 -#define AUX_TIMER2_CH2CCFG_CAPT_SRC_AUXIO0 0x00000000 - -// Field: [0] EDGE -// -// Edge configuration. -// -// Channel captures counter value at selected edge on signal source selected by -// CAPT_SRC. See CH2EVCFG.CCACT. -// ENUMs: -// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. -// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. -#define AUX_TIMER2_CH2CCFG_EDGE 0x00000001 -#define AUX_TIMER2_CH2CCFG_EDGE_BITN 0 -#define AUX_TIMER2_CH2CCFG_EDGE_M 0x00000001 -#define AUX_TIMER2_CH2CCFG_EDGE_S 0 -#define AUX_TIMER2_CH2CCFG_EDGE_RISING 0x00000001 -#define AUX_TIMER2_CH2CCFG_EDGE_FALLING 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH2PCC -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Pipeline Capture Compare value. -// -// 16-bit user defined pipeline compare value or channel-updated capture value. -// -// Compare mode: -// An update of VALUE will be transferred to CH2CC.VALUE when the next -// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for -// PWM generation and prevents jitter on the edges of the generated signal. -// -// Capture mode: -// When CH2EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the -// width of the low or high phase of the selected signal. This is specified by -// CH2CCFG.EDGE and CH2CCFG.CAPT_SRC. -#define AUX_TIMER2_CH2PCC_VALUE_W 16 -#define AUX_TIMER2_CH2PCC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH2PCC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH2CC -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Capture Compare value. -// -// 16-bit user defined compare value or channel-updated capture value. -// -// Compare mode: -// VALUE is compared against CNTR.VALUE and an event is generated as specified -// by CH2EVCFG.CCACT when these are equal. -// -// Capture mode: -// The current counter value is stored in VALUE when a capture event occurs. -// CH2EVCFG.CCACT determines if VALUE is a signal period or a regular capture -// value. -#define AUX_TIMER2_CH2CC_VALUE_W 16 -#define AUX_TIMER2_CH2CC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH2CC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH3EVCFG -// -//***************************************************************************** -// Field: [7] EV3_GEN -// -// Event 3 enable. -// -// 0: Channel 3 does not control event 3. -// 1: Channel 3 controls event 3. -// -// When 0 < CCACT < 8, EV3_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH3EVCFG_EV3_GEN 0x00000080 -#define AUX_TIMER2_CH3EVCFG_EV3_GEN_BITN 7 -#define AUX_TIMER2_CH3EVCFG_EV3_GEN_M 0x00000080 -#define AUX_TIMER2_CH3EVCFG_EV3_GEN_S 7 - -// Field: [6] EV2_GEN -// -// Event 2 enable. -// -// 0: Channel 3 does not control event 2. -// 1: Channel 3 controls event 2. -// -// When 0 < CCACT < 8, EV2_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH3EVCFG_EV2_GEN 0x00000040 -#define AUX_TIMER2_CH3EVCFG_EV2_GEN_BITN 6 -#define AUX_TIMER2_CH3EVCFG_EV2_GEN_M 0x00000040 -#define AUX_TIMER2_CH3EVCFG_EV2_GEN_S 6 - -// Field: [5] EV1_GEN -// -// Event 1 enable. -// -// 0: Channel 3 does not control event 1. -// 1: Channel 3 controls event 1. -// -// When 0 < CCACT < 8, EV1_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH3EVCFG_EV1_GEN 0x00000020 -#define AUX_TIMER2_CH3EVCFG_EV1_GEN_BITN 5 -#define AUX_TIMER2_CH3EVCFG_EV1_GEN_M 0x00000020 -#define AUX_TIMER2_CH3EVCFG_EV1_GEN_S 5 - -// Field: [4] EV0_GEN -// -// Event 0 enable. -// -// 0: Channel 3 does not control event 0. -// 1: Channel 3 controls event 0. -// -// When 0 < CCACT < 8, EV0_GEN becomes zero after a capture or compare event. -#define AUX_TIMER2_CH3EVCFG_EV0_GEN 0x00000010 -#define AUX_TIMER2_CH3EVCFG_EV0_GEN_BITN 4 -#define AUX_TIMER2_CH3EVCFG_EV0_GEN_M 0x00000010 -#define AUX_TIMER2_CH3EVCFG_EV0_GEN_S 4 - -// Field: [3:0] CCACT -// -// Capture-Compare action. -// -// Capture-Compare action defines 15 different channel functions that utilize -// capture, compare, and zero events. -// ENUMs: -// PULSE_ON_CMP Pulse on compare repeatedly. -// -// Channel function -// sequence: -// - Pulse enabled events -// when CH3CC.VALUE = CNTR.VALUE. -// -// The event is high for -// two timer clock periods. -// TGL_ON_CMP Toggle on compare repeatedly. -// -// Channel function -// sequence: -// - Toggle enabled events -// when CH3CC.VALUE = CNTR.VALUE. -// SET_ON_CMP Set on compare repeatedly. -// -// Channel function -// sequence: -// - Set enabled events -// when CH3CC.VALUE = CNTR.VALUE. -// CLR_ON_CMP Clear on compare repeatedly. -// -// Channel function -// sequence: -// - Clear enabled events -// when CH3CC.VALUE = CNTR.VALUE. -// SET_ON_0_TGL_ON_CMP Set on zero, toggle on compare repeatedly. -// -// Channel function -// sequence: -// - Set enabled events when -// CNTR.VALUE = 0. -// - Toggle enabled events -// when CH3CC.VALUE = CNTR.VALUE. -// -// Set CTL.MODE to UP_PER -// for edge-aligned PWM generation. Duty cycle is -// given by: -// -// When CH3CC.VALUE <= -// TARGET.VALUE: -// Duty cycle = -// CH3CC.VALUE / ( TARGET.VALUE + 1 ). -// -// When CH3CC.VALUE > -// TARGET.VALUE: -// Duty cycle = 1. -// -// Enabled events are -// cleared when CH3CC.VALUE = 0 and CNTR.VALUE = -// 0. -// CLR_ON_0_TGL_ON_CMP Clear on zero, toggle on compare repeatedly. -// -// Channel function -// sequence: -// - Clear enabled events -// when CNTR.VALUE = 0. -// - Toggle enabled events -// when CH3CC.VALUE = CNTR.VALUE. -// -// Set CTL.MODE to UPDWN_PER -// for center-aligned PWM generation. Duty cycle -// is given by: -// -// When CH3CC.VALUE <= -// TARGET.VALUE: -// Duty cycle = 1 - ( -// CH3CC.VALUE / TARGET.VALUE ). -// -// When CH3CC.VALUE > -// TARGET.VALUE: -// Duty cycle = 0. -// -// Enabled events are set -// when CH3CC.VALUE = 0 and CNTR.VALUE = 0. -// SET_ON_CAPT Set on capture repeatedly. -// -// Channel function -// sequence: -// - Set enabled events on -// capture event and copy CNTR.VALUE to -// CH3CC.VALUE. -// -// Primary use scenario is -// to select this function before you start the -// timer. -// Follow these steps if you -// need to select this function while CTL.MODE is -// different from DIS: -// - Select this function -// with no event enable. -// - Configure CH3CCFG -// (optional). -// - Wait for three timer -// clock periods as defined in PRECFG before you -// enable events. -// -// These steps prevent -// capture events caused by expired signal values -// in edge-detection circuit. -// PER_PULSE_WIDTH_MEAS Period and pulse width measurement. -// -// Continuously capture -// period and pulse width of the signal selected -// by CH3CCFG.CAPT_SRC relative to the signal edge -// given by CH3CCFG.EDGE. -// -// Set enabled events when -// CH3CC.VALUE contains signal period and -// CH3PCC.VALUE contains signal pulse width. -// -// Notes: -// - Make sure that you -// configure CH3CCFG.CAPT_SRC and CCACT when -// CTL.MODE equals DIS, then set CTL.MODE to -// UP_ONCE or UP_PER. -// - The counter restarts in -// the selected timer mode when CH3CC.VALUE -// contains the signal period. -// - If more than one -// channel uses this function, the channels will -// perform this function one at a time. The -// channel with lowest number has priority and -// performs the function first. Next measurement -// starts when current measurement completes -// successfully or times out. A timeout occurs -// when counter equals target. -// - If you want to observe -// a timeout event configure another channel to -// SET_ON_CAPT. -// -// Signal property -// requirements: -// - Signal Period >= 2 * ( -// 1 + PRECFG.CLKDIV ) * timer clock period. -// - Signal Period <= 65535 -// * (1 + PRECFG.CLKDIV ) * timer clock period. -// - Signal low and high -// phase >= (1 + PRECFG.CLKDIV ) * timer clock -// period. -// PULSE_ON_CMP_DIS Pulse on compare, and then disable channel. -// -// Channel function -// sequence: -// - Pulse enabled events -// when CH3CC.VALUE = CNTR.VALUE. -// - Disable channel. -// -// The event is high for -// two timer clock periods. -// TGL_ON_CMP_DIS Toggle on compare, and then disable channel. -// -// Channel function -// sequence: -// - Toggle enabled events -// when CH3CC.VALUE = CNTR.VALUE. -// - Disable channel. -// SET_ON_CMP_DIS Set on compare, and then disable channel. -// -// Channel function -// sequence: -// - Set enabled events when -// CH3CC.VALUE = CNTR.VALUE. -// - Disable channel. -// CLR_ON_CMP_DIS Clear on compare, and then disable channel. -// -// Channel function -// sequence: -// - Clear enabled events -// when CH3CC.VALUE = CNTR.VALUE. -// - Disable channel. -// SET_ON_0_TGL_ON_CMP_DIS Set on zero, toggle on compare, and then disable -// channel. -// -// Channel function -// sequence: -// - Set enabled events when -// CNTR.VALUE = 0. -// - Toggle enabled events -// when CH3CC.VALUE = CNTR.VALUE. -// - Disable channel. -// -// Enabled events are -// cleared when CH3CC.VALUE = 0 and CNTR.VALUE = -// 0. -// CLR_ON_0_TGL_ON_CMP_DIS Clear on zero, toggle on compare, and then disable -// channel. -// -// Channel function -// sequence: -// - Clear enabled events -// when CNTR.VALUE = 0. -// - Toggle enabled events -// when CH3CC.VALUE = CNTR.VALUE. -// - Disable channel. -// -// Enabled events are set -// when CH3CC.VALUE = 0 and CNTR.VALUE = 0. -// SET_ON_CAPT_DIS Set on capture, and then disable channel. -// -// Channel function -// sequence: -// - Set enabled events on -// capture event and copy CNTR.VALUE to -// CH3CC.VALUE. -// - Disable channel. -// -// Primary use scenario is -// to select this function before you start the -// timer. -// Follow these steps if you -// need to select this function while CTL.MODE is -// different from DIS: -// - Set CCACT to -// SET_ON_CAPT with no event enable. -// - Configure CH3CCFG -// (optional). -// - Wait for three timer -// clock periods as defined in PRECFG before you -// set CCACT to SET_ON_CAPT_DIS. Event enable is -// optional. -// -// These steps prevent -// capture events caused by expired signal values -// in edge-detection circuit. -// DIS Disable channel. -#define AUX_TIMER2_CH3EVCFG_CCACT_W 4 -#define AUX_TIMER2_CH3EVCFG_CCACT_M 0x0000000F -#define AUX_TIMER2_CH3EVCFG_CCACT_S 0 -#define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP 0x0000000F -#define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP 0x0000000E -#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP 0x0000000D -#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP 0x0000000C -#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP 0x0000000B -#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP 0x0000000A -#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT 0x00000009 -#define AUX_TIMER2_CH3EVCFG_CCACT_PER_PULSE_WIDTH_MEAS 0x00000008 -#define AUX_TIMER2_CH3EVCFG_CCACT_PULSE_ON_CMP_DIS 0x00000007 -#define AUX_TIMER2_CH3EVCFG_CCACT_TGL_ON_CMP_DIS 0x00000006 -#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CMP_DIS 0x00000005 -#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_CMP_DIS 0x00000004 -#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_0_TGL_ON_CMP_DIS 0x00000003 -#define AUX_TIMER2_CH3EVCFG_CCACT_CLR_ON_0_TGL_ON_CMP_DIS 0x00000002 -#define AUX_TIMER2_CH3EVCFG_CCACT_SET_ON_CAPT_DIS 0x00000001 -#define AUX_TIMER2_CH3EVCFG_CCACT_DIS 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH3CCFG -// -//***************************************************************************** -// Field: [6:1] CAPT_SRC -// -// Select capture signal source from the asynchronous AUX event bus. -// -// The selected signal enters the edge-detection circuit. False capture events -// can occur when: -// - the edge-detection circuit contains expired signal samples and the circuit -// is enabled without flush as described in CH3EVCFG -// - this register is reconfigured while CTL.MODE is different from DIS. -// -// You can avoid false capture events. When wanted channel function: -// - SET_ON_CAPT_DIS, see description for SET_ON_CAPT_DIS in CH3EVCFG.CCACT. -// - SET_ON_CAPT, see description for SET_ON_CAPT in CH3EVCFG.CCACT. -// - PER_PULSE_WIDTH_MEAS, see description for PER_PULSE_WIDTH_MEAS in -// CH3EVCFG.CCACT. -// -// If you write a non-enumerated value the behavior is identical to NO_EVENT. -// The written value is returned when read. -// ENUMs: -// NO_EVENT No event. -// AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE -// AUX_ADC_FIFO_NOT_EMPTY AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_NOT_EMPTY -// AUX_ADC_FIFO_ALMOST_FULL AUX_EVCTL:EVSTAT3.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_IRQ AUX_EVCTL:EVSTAT3.AUX_ADC_IRQ -// AUX_ADC_DONE AUX_EVCTL:EVSTAT3.AUX_ADC_DONE -// AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N -// AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE -// AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV -// AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV -// AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 -// AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB -// AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA -// MCU_OBSMUX1 AUX_EVCTL:EVSTAT2.MCU_OBSMUX1 -// MCU_OBSMUX0 AUX_EVCTL:EVSTAT2.MCU_OBSMUX0 -// MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV -// ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF -// VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE -// MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE -// PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN -// SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF -// AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD -// AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD -// AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ -// AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY -// AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 -// MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV -// AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 -// AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 -// AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 -// AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 -// AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 -// AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 -// AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 -// AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 -// AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 -// AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 -// AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 -// AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 -// AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 -// AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 -// AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 -// AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 -// AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 -// AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 -// AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 -// AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 -// AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 -// AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 -// AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 -// AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 -// AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 -// AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 -// AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 -// AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 -// AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 -// AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 -// AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 -// AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_W 6 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_M 0x0000007E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_S 1 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_NO_EVENT 0x0000007E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_SMPH_AUTOTAKE_DONE 0x0000007A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_NOT_EMPTY 0x00000078 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_FIFO_ALMOST_FULL 0x00000076 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_IRQ 0x00000074 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ADC_DONE 0x00000072 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_ISRC_RESET_N 0x00000070 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TDC_DONE 0x0000006E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER0_EV 0x0000006C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER1_EV 0x0000006A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV3 0x00000066 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV2 0x00000064 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV1 0x00000062 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_TIMER2_EV0 0x00000060 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPB 0x0000005E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUX_COMPA 0x0000005C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX1 0x0000005A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_OBSMUX0 0x00000058 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_EV 0x00000056 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_ACLK_REF 0x00000054 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_VDDR_RECHARGE 0x00000052 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MCU_ACTIVE 0x00000050 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_PWR_DWN 0x0000004E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_SCLK_LF 0x0000004C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_TEMP_UPD 0x0000004A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_BATMON_BAT_UPD 0x00000048 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_4KHZ 0x00000046 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2_DLY 0x00000044 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AON_RTC_CH2 0x00000042 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_MANUAL_EV 0x00000040 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO31 0x0000003E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO30 0x0000003C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO29 0x0000003A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO28 0x00000038 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO27 0x00000036 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO26 0x00000034 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO25 0x00000032 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO24 0x00000030 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO23 0x0000002E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO22 0x0000002C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO21 0x0000002A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO20 0x00000028 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO19 0x00000026 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO18 0x00000024 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO17 0x00000022 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO16 0x00000020 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO15 0x0000001E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO14 0x0000001C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO13 0x0000001A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO12 0x00000018 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO11 0x00000016 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO10 0x00000014 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO9 0x00000012 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO8 0x00000010 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO7 0x0000000E -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO6 0x0000000C -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO5 0x0000000A -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO4 0x00000008 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO3 0x00000006 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO2 0x00000004 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO1 0x00000002 -#define AUX_TIMER2_CH3CCFG_CAPT_SRC_AUXIO0 0x00000000 - -// Field: [0] EDGE -// -// Edge configuration. -// -// Channel captures counter value at selected edge on signal source selected by -// CAPT_SRC. See CH3EVCFG.CCACT. -// ENUMs: -// RISING Capture CNTR.VALUE at rising edge of CAPT_SRC. -// FALLING Capture CNTR.VALUE at falling edge of CAPT_SRC. -#define AUX_TIMER2_CH3CCFG_EDGE 0x00000001 -#define AUX_TIMER2_CH3CCFG_EDGE_BITN 0 -#define AUX_TIMER2_CH3CCFG_EDGE_M 0x00000001 -#define AUX_TIMER2_CH3CCFG_EDGE_S 0 -#define AUX_TIMER2_CH3CCFG_EDGE_RISING 0x00000001 -#define AUX_TIMER2_CH3CCFG_EDGE_FALLING 0x00000000 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH3PCC -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Pipeline Capture Compare value. -// -// 16-bit user defined pipeline compare value or channel-updated capture value. -// -// Compare mode: -// An update of VALUE will be transferred to CH3CC.VALUE when the next -// CNTR.VALUE is zero and CTL.MODE is different from DIS. This is useful for -// PWM generation and prevents jitter on the edges of the generated signal. -// -// Capture mode: -// When CH3EVCFG.CCACT equals PER_PULSE_WIDTH_MEAS then VALUE contains the -// width of the low or high phase of the selected signal. This is specified by -// CH3CCFG.EDGE and CH3CCFG.CAPT_SRC. -#define AUX_TIMER2_CH3PCC_VALUE_W 16 -#define AUX_TIMER2_CH3PCC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH3PCC_VALUE_S 0 - -//***************************************************************************** -// -// Register: AUX_TIMER2_O_CH3CC -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Capture Compare value. -// -// 16-bit user defined compare value or channel-updated capture value. -// -// Compare mode: -// VALUE is compared against CNTR.VALUE and an event is generated as specified -// by CH3EVCFG.CCACT when these are equal. -// -// Capture mode: -// The current counter value is stored in VALUE when a capture event occurs. -// CH3EVCFG.CCACT determines if VALUE is a signal period or a regular capture -// value. -#define AUX_TIMER2_CH3CC_VALUE_W 16 -#define AUX_TIMER2_CH3CC_VALUE_M 0x0000FFFF -#define AUX_TIMER2_CH3CC_VALUE_S 0 - - -#endif // __AUX_TIMER2__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h deleted file mode 100644 index 568eca05539..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg.h +++ /dev/null @@ -1,1910 +0,0 @@ -/****************************************************************************** -* Filename: hw_ccfg_h -* Revised: 2018-10-19 08:48:09 +0200 (Fri, 19 Oct 2018) -* Revision: 52957 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CCFG_H__ -#define __HW_CCFG_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CCFG component -// -//***************************************************************************** -// Extern LF clock configuration -#define CCFG_O_EXT_LF_CLK 0x00001FA8 - -// Mode Configuration 1 -#define CCFG_O_MODE_CONF_1 0x00001FAC - -// CCFG Size and Disable Flags -#define CCFG_O_SIZE_AND_DIS_FLAGS 0x00001FB0 - -// Mode Configuration 0 -#define CCFG_O_MODE_CONF 0x00001FB4 - -// Voltage Load 0 -#define CCFG_O_VOLT_LOAD_0 0x00001FB8 - -// Voltage Load 1 -#define CCFG_O_VOLT_LOAD_1 0x00001FBC - -// Real Time Clock Offset -#define CCFG_O_RTC_OFFSET 0x00001FC0 - -// Frequency Offset -#define CCFG_O_FREQ_OFFSET 0x00001FC4 - -// IEEE MAC Address 0 -#define CCFG_O_IEEE_MAC_0 0x00001FC8 - -// IEEE MAC Address 1 -#define CCFG_O_IEEE_MAC_1 0x00001FCC - -// IEEE BLE Address 0 -#define CCFG_O_IEEE_BLE_0 0x00001FD0 - -// IEEE BLE Address 1 -#define CCFG_O_IEEE_BLE_1 0x00001FD4 - -// Bootloader Configuration -#define CCFG_O_BL_CONFIG 0x00001FD8 - -// Erase Configuration -#define CCFG_O_ERASE_CONF 0x00001FDC - -// TI Options -#define CCFG_O_CCFG_TI_OPTIONS 0x00001FE0 - -// Test Access Points Enable 0 -#define CCFG_O_CCFG_TAP_DAP_0 0x00001FE4 - -// Test Access Points Enable 1 -#define CCFG_O_CCFG_TAP_DAP_1 0x00001FE8 - -// Image Valid -#define CCFG_O_IMAGE_VALID_CONF 0x00001FEC - -// Protect Sectors 0-31 -#define CCFG_O_CCFG_PROT_31_0 0x00001FF0 - -// Protect Sectors 32-63 -#define CCFG_O_CCFG_PROT_63_32 0x00001FF4 - -// Protect Sectors 64-95 -#define CCFG_O_CCFG_PROT_95_64 0x00001FF8 - -// Protect Sectors 96-127 -#define CCFG_O_CCFG_PROT_127_96 0x00001FFC - -//***************************************************************************** -// -// Register: CCFG_O_EXT_LF_CLK -// -//***************************************************************************** -// Field: [31:24] DIO -// -// Unsigned integer, selecting the DIO to supply external 32kHz clock as -// SCLK_LF when MODE_CONF.SCLK_LF_OPTION is set to EXTERNAL. The selected DIO -// will be marked as reserved by the pin driver (TI-RTOS environment) and hence -// not selectable for other usage. -#define CCFG_EXT_LF_CLK_DIO_W 8 -#define CCFG_EXT_LF_CLK_DIO_M 0xFF000000 -#define CCFG_EXT_LF_CLK_DIO_S 24 - -// Field: [23:0] RTC_INCREMENT -// -// Unsigned integer, defining the input frequency of the external clock and is -// written to AON_RTC:SUBSECINC.VALUEINC. Defined as follows: -// EXT_LF_CLK.RTC_INCREMENT = 2^38/InputClockFrequency in Hertz (e.g.: -// RTC_INCREMENT=0x800000 for InputClockFrequency=32768 Hz) -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_W 24 -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_M 0x00FFFFFF -#define CCFG_EXT_LF_CLK_RTC_INCREMENT_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_MODE_CONF_1 -// -//***************************************************************************** -// Field: [23:20] ALT_DCDC_VMIN -// -// Minimum voltage for when DC/DC should be used if alternate DC/DC setting is -// enabled (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). -// Voltage = (28 + ALT_DCDC_VMIN) / 16. -// 0: 1.75V -// 1: 1.8125V -// ... -// 14: 2.625V -// 15: 2.6875V -// -// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must -// be called regularly to apply this field (handled automatically if using TI -// RTOS!). -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_W 4 -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M 0x00F00000 -#define CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S 20 - -// Field: [19] ALT_DCDC_DITHER_EN -// -// Enable DC/DC dithering if alternate DC/DC setting is enabled -// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). -// 0: Dither disable -// 1: Dither enable -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x00080000 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_BITN 19 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M 0x00080000 -#define CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S 19 - -// Field: [18:16] ALT_DCDC_IPEAK -// -// Inductor peak current if alternate DC/DC setting is enabled -// (SIZE_AND_DIS_FLAGS.DIS_ALT_DCDC_SETTING=0). Assuming 10uH external -// inductor! -// Peak current = 31 + ( 4 * ALT_DCDC_IPEAK ) : -// 0: 31mA (min) -// ... -// 4: 47mA -// ... -// 7: 59mA (max) -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_W 3 -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M 0x00070000 -#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S 16 - -// Field: [15:12] DELTA_IBIAS_INIT -// -// Signed delta value for IBIAS_INIT. Delta value only applies if -// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. -// See FCFG1:AMPCOMP_CTRL1.IBIAS_INIT -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_W 4 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M 0x0000F000 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S 12 - -// Field: [11:8] DELTA_IBIAS_OFFSET -// -// Signed delta value for IBIAS_OFFSET. Delta value only applies if -// SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. -// See FCFG1:AMPCOMP_CTRL1.IBIAS_OFFSET -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_W 4 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M 0x00000F00 -#define CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S 8 - -// Field: [7:0] XOSC_MAX_START -// -// Unsigned value of maximum XOSC startup time (worst case) in units of 100us. -// Value only applies if SIZE_AND_DIS_FLAGS.DIS_XOSC_OVR=0. -#define CCFG_MODE_CONF_1_XOSC_MAX_START_W 8 -#define CCFG_MODE_CONF_1_XOSC_MAX_START_M 0x000000FF -#define CCFG_MODE_CONF_1_XOSC_MAX_START_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_SIZE_AND_DIS_FLAGS -// -//***************************************************************************** -// Field: [31:16] SIZE_OF_CCFG -// -// Total size of CCFG in bytes. -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_W 16 -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M 0xFFFF0000 -#define CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S 16 - -// Field: [15:4] DISABLE_FLAGS -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_W 12 -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M 0x0000FFF0 -#define CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S 4 - -// Field: [3] DIS_TCXO -// -// Disable TCXO. -// 0: TCXO functionality enabled. -// 1: TCXO functionality disabled. -// Note: -// An external TCXO is required if DIS_TCXO = 0. -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x00000008 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_BITN 3 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M 0x00000008 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S 3 - -// Field: [2] DIS_GPRAM -// -// Disable GPRAM (or use the 8K VIMS RAM as CACHE RAM). -// 0: GPRAM is enabled and hence CACHE disabled. -// 1: GPRAM is disabled and instead CACHE is enabled (default). -// Notes: -// - Disabling CACHE will reduce CPU execution speed (up to 60%). -// - GPRAM is 8 K-bytes in size and located at 0x11000000-0x11001FFF if -// enabled. -// See: -// VIMS:CTL.MODE -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_BITN 2 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M 0x00000004 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S 2 - -// Field: [1] DIS_ALT_DCDC_SETTING -// -// Disable alternate DC/DC settings. -// 0: Enable alternate DC/DC settings. -// 1: Disable alternate DC/DC settings. -// See: -// MODE_CONF_1.ALT_DCDC_VMIN -// MODE_CONF_1.ALT_DCDC_DITHER_EN -// MODE_CONF_1.ALT_DCDC_IPEAK -// -// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must -// be called regularly to apply this field (handled automatically if using TI -// RTOS!). -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_BITN 1 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M 0x00000002 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S 1 - -// Field: [0] DIS_XOSC_OVR -// -// Disable XOSC override functionality. -// 0: Enable XOSC override functionality. -// 1: Disable XOSC override functionality. -// See: -// MODE_CONF_1.DELTA_IBIAS_INIT -// MODE_CONF_1.DELTA_IBIAS_OFFSET -// MODE_CONF_1.XOSC_MAX_START -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x00000001 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_BITN 0 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M 0x00000001 -#define CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_MODE_CONF -// -//***************************************************************************** -// Field: [31:28] VDDR_TRIM_SLEEP_DELTA -// -// Signed delta value to apply to the -// VDDR_TRIM_SLEEP target, minus one. See FCFG1:VOLT_TRIM.VDDR_TRIM_SLEEP_H. -// 0x8 (-8) : Delta = -7 -// ... -// 0xF (-1) : Delta = 0 -// 0x0 (0) : Delta = +1 -// ... -// 0x7 (7) : Delta = +8 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_W 4 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M 0xF0000000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S 28 - -// Field: [27] DCDC_RECHARGE -// -// DC/DC during recharge in powerdown. -// 0: Use the DC/DC during recharge in powerdown. -// 1: Do not use the DC/DC during recharge in powerdown (default). -// -// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must -// be called regularly to apply this field (handled automatically if using TI -// RTOS!). -#define CCFG_MODE_CONF_DCDC_RECHARGE 0x08000000 -#define CCFG_MODE_CONF_DCDC_RECHARGE_BITN 27 -#define CCFG_MODE_CONF_DCDC_RECHARGE_M 0x08000000 -#define CCFG_MODE_CONF_DCDC_RECHARGE_S 27 - -// Field: [26] DCDC_ACTIVE -// -// DC/DC in active mode. -// 0: Use the DC/DC during active mode. -// 1: Do not use the DC/DC during active mode (default). -// -// NOTE! The DriverLib function SysCtrl_DCDC_VoltageConditionalControl() must -// be called regularly to apply this field (handled automatically if using TI -// RTOS!). -#define CCFG_MODE_CONF_DCDC_ACTIVE 0x04000000 -#define CCFG_MODE_CONF_DCDC_ACTIVE_BITN 26 -#define CCFG_MODE_CONF_DCDC_ACTIVE_M 0x04000000 -#define CCFG_MODE_CONF_DCDC_ACTIVE_S 26 - -// Field: [25] VDDR_EXT_LOAD -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_BITN 25 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_M 0x02000000 -#define CCFG_MODE_CONF_VDDR_EXT_LOAD_S 25 - -// Field: [24] VDDS_BOD_LEVEL -// -// VDDS BOD level. -// 0: VDDS BOD level is 2.0V (necessary for external load mode, or for maximum -// PA output power on CC13xx). -// 1: VDDS BOD level is 1.8V (or 1.65V for external regulator mode) (default). -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_BITN 24 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_M 0x01000000 -#define CCFG_MODE_CONF_VDDS_BOD_LEVEL_S 24 - -// Field: [23:22] SCLK_LF_OPTION -// -// Select source for SCLK_LF. -// ENUMs: -// RCOSC_LF Low frequency RCOSC (default) -// XOSC_LF 32.768kHz low frequency XOSC -// EXTERNAL_LF External low frequency clock on DIO defined by -// EXT_LF_CLK.DIO. The RTC tick speed -// AON_RTC:SUBSECINC is updated to -// EXT_LF_CLK.RTC_INCREMENT (done in the -// trimDevice() xxWare boot function). External -// clock must always be running when the chip is -// in standby for VDDR recharge timing. -// XOSC_HF_DLF 31.25kHz clock derived from 24MHz XOSC (dividing -// by 768 in HW). The RTC tick speed -// [AON_RTC.SUBSECINC.*] is updated to 0x8637BD, -// corresponding to a 31.25kHz clock (done in the -// trimDevice() xxWare boot function). Standby -// power mode is not supported when using this -// clock source. -#define CCFG_MODE_CONF_SCLK_LF_OPTION_W 2 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_M 0x00C00000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_S 22 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_RCOSC_LF 0x00C00000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_LF 0x00800000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_EXTERNAL_LF 0x00400000 -#define CCFG_MODE_CONF_SCLK_LF_OPTION_XOSC_HF_DLF 0x00000000 - -// Field: [21] VDDR_TRIM_SLEEP_TC -// -// 0x1: VDDR_TRIM_SLEEP_DELTA is not temperature compensated -// 0x0: RTOS/driver temperature compensates VDDR_TRIM_SLEEP_DELTA every time -// standby mode is entered. This improves low-temperature RCOSC_LF frequency -// stability in standby mode. -// -// When temperature compensation is performed, the delta is calculates this -// way: -// Delta = max (delta, min(8, floor(62-temp)/8)) -// Here, delta is given by VDDR_TRIM_SLEEP_DELTA, and temp is the current -// temperature in degrees C. -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x00200000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_BITN 21 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M 0x00200000 -#define CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S 21 - -// Field: [20] RTC_COMP -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_MODE_CONF_RTC_COMP 0x00100000 -#define CCFG_MODE_CONF_RTC_COMP_BITN 20 -#define CCFG_MODE_CONF_RTC_COMP_M 0x00100000 -#define CCFG_MODE_CONF_RTC_COMP_S 20 - -// Field: [19:18] XOSC_FREQ -// -// Selects high precision HF oscillator (activated when using the radio). -// ENUMs: -// 24M 24 MHz XOSC_HF -// 48M 48 MHz XOSC_HF -// HPOSC HPOSC -#define CCFG_MODE_CONF_XOSC_FREQ_W 2 -#define CCFG_MODE_CONF_XOSC_FREQ_M 0x000C0000 -#define CCFG_MODE_CONF_XOSC_FREQ_S 18 -#define CCFG_MODE_CONF_XOSC_FREQ_24M 0x000C0000 -#define CCFG_MODE_CONF_XOSC_FREQ_48M 0x00080000 -#define CCFG_MODE_CONF_XOSC_FREQ_HPOSC 0x00040000 - -// Field: [17] XOSC_CAP_MOD -// -// Enable modification (delta) to XOSC cap-array. Value specified in -// XOSC_CAPARRAY_DELTA. -// 0: Apply cap-array delta -// 1: Do not apply cap-array delta (default) -#define CCFG_MODE_CONF_XOSC_CAP_MOD 0x00020000 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_BITN 17 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_M 0x00020000 -#define CCFG_MODE_CONF_XOSC_CAP_MOD_S 17 - -// Field: [16] HF_COMP -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_MODE_CONF_HF_COMP 0x00010000 -#define CCFG_MODE_CONF_HF_COMP_BITN 16 -#define CCFG_MODE_CONF_HF_COMP_M 0x00010000 -#define CCFG_MODE_CONF_HF_COMP_S 16 - -// Field: [15:8] XOSC_CAPARRAY_DELTA -// -// Signed 8-bit value, directly modifying trimmed XOSC cap-array step value. -// Enabled by XOSC_CAP_MOD. -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_W 8 -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M 0x0000FF00 -#define CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S 8 - -// Field: [7:0] VDDR_CAP -// -// Unsigned 8-bit integer, representing the minimum decoupling capacitance -// (worst case) on VDDR, in units of 100nF. This should take into account -// capacitor tolerance and voltage dependent capacitance variation. This bit -// affects the recharge period calculation when going into powerdown or -// standby. -// -// NOTE! If using the following functions this field must be configured (used -// by TI RTOS): -// SysCtrlSetRechargeBeforePowerDown() SysCtrlAdjustRechargeAfterPowerDown() -#define CCFG_MODE_CONF_VDDR_CAP_W 8 -#define CCFG_MODE_CONF_VDDR_CAP_M 0x000000FF -#define CCFG_MODE_CONF_VDDR_CAP_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_VOLT_LOAD_0 -// -//***************************************************************************** -// Field: [31:24] VDDR_EXT_TP45 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M 0xFF000000 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S 24 - -// Field: [23:16] VDDR_EXT_TP25 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M 0x00FF0000 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S 16 - -// Field: [15:8] VDDR_EXT_TP5 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M 0x0000FF00 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S 8 - -// Field: [7:0] VDDR_EXT_TM15 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_W 8 -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M 0x000000FF -#define CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_VOLT_LOAD_1 -// -//***************************************************************************** -// Field: [31:24] VDDR_EXT_TP125 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M 0xFF000000 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S 24 - -// Field: [23:16] VDDR_EXT_TP105 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M 0x00FF0000 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S 16 - -// Field: [15:8] VDDR_EXT_TP85 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M 0x0000FF00 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S 8 - -// Field: [7:0] VDDR_EXT_TP65 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_W 8 -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M 0x000000FF -#define CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_RTC_OFFSET -// -//***************************************************************************** -// Field: [31:16] RTC_COMP_P0 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P0_W 16 -#define CCFG_RTC_OFFSET_RTC_COMP_P0_M 0xFFFF0000 -#define CCFG_RTC_OFFSET_RTC_COMP_P0_S 16 - -// Field: [15:8] RTC_COMP_P1 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P1_W 8 -#define CCFG_RTC_OFFSET_RTC_COMP_P1_M 0x0000FF00 -#define CCFG_RTC_OFFSET_RTC_COMP_P1_S 8 - -// Field: [7:0] RTC_COMP_P2 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_RTC_OFFSET_RTC_COMP_P2_W 8 -#define CCFG_RTC_OFFSET_RTC_COMP_P2_M 0x000000FF -#define CCFG_RTC_OFFSET_RTC_COMP_P2_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_FREQ_OFFSET -// -//***************************************************************************** -// Field: [31:16] HF_COMP_P0 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P0_W 16 -#define CCFG_FREQ_OFFSET_HF_COMP_P0_M 0xFFFF0000 -#define CCFG_FREQ_OFFSET_HF_COMP_P0_S 16 - -// Field: [15:8] HF_COMP_P1 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P1_W 8 -#define CCFG_FREQ_OFFSET_HF_COMP_P1_M 0x0000FF00 -#define CCFG_FREQ_OFFSET_HF_COMP_P1_S 8 - -// Field: [7:0] HF_COMP_P2 -// -// Reserved for future use. Software should not rely on the value of a -// reserved. Writing any other value than the reset/default value may result in -// undefined behavior. -#define CCFG_FREQ_OFFSET_HF_COMP_P2_W 8 -#define CCFG_FREQ_OFFSET_HF_COMP_P2_M 0x000000FF -#define CCFG_FREQ_OFFSET_HF_COMP_P2_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_IEEE_MAC_0 -// -//***************************************************************************** -// Field: [31:0] ADDR -// -// Bits[31:0] of the 64-bits custom IEEE MAC address. -// If different from 0xFFFFFFFF then the value of this field is applied; -// otherwise use value from FCFG. -#define CCFG_IEEE_MAC_0_ADDR_W 32 -#define CCFG_IEEE_MAC_0_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_MAC_0_ADDR_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_IEEE_MAC_1 -// -//***************************************************************************** -// Field: [31:0] ADDR -// -// Bits[63:32] of the 64-bits custom IEEE MAC address. -// If different from 0xFFFFFFFF then the value of this field is applied; -// otherwise use value from FCFG. -#define CCFG_IEEE_MAC_1_ADDR_W 32 -#define CCFG_IEEE_MAC_1_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_MAC_1_ADDR_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_IEEE_BLE_0 -// -//***************************************************************************** -// Field: [31:0] ADDR -// -// Bits[31:0] of the 64-bits custom IEEE BLE address. -// If different from 0xFFFFFFFF then the value of this field is applied; -// otherwise use value from FCFG. -#define CCFG_IEEE_BLE_0_ADDR_W 32 -#define CCFG_IEEE_BLE_0_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_BLE_0_ADDR_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_IEEE_BLE_1 -// -//***************************************************************************** -// Field: [31:0] ADDR -// -// Bits[63:32] of the 64-bits custom IEEE BLE address. -// If different from 0xFFFFFFFF then the value of this field is applied; -// otherwise use value from FCFG. -#define CCFG_IEEE_BLE_1_ADDR_W 32 -#define CCFG_IEEE_BLE_1_ADDR_M 0xFFFFFFFF -#define CCFG_IEEE_BLE_1_ADDR_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_BL_CONFIG -// -//***************************************************************************** -// Field: [31:24] BOOTLOADER_ENABLE -// -// Bootloader enable. Boot loader can be accessed if -// IMAGE_VALID_CONF.IMAGE_VALID is non-zero or BL_ENABLE is enabled (and -// conditions for boot loader backdoor are met). -// 0xC5: Boot loader is enabled. -// Any other value: Boot loader is disabled. -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_W 8 -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M 0xFF000000 -#define CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S 24 - -// Field: [16] BL_LEVEL -// -// Sets the active level of the selected DIO number BL_PIN_NUMBER if boot -// loader backdoor is enabled by the BL_ENABLE field. -// 0: Active low. -// 1: Active high. -#define CCFG_BL_CONFIG_BL_LEVEL 0x00010000 -#define CCFG_BL_CONFIG_BL_LEVEL_BITN 16 -#define CCFG_BL_CONFIG_BL_LEVEL_M 0x00010000 -#define CCFG_BL_CONFIG_BL_LEVEL_S 16 - -// Field: [15:8] BL_PIN_NUMBER -// -// DIO number that is level checked if the boot loader backdoor is enabled by -// the BL_ENABLE field. -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_W 8 -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_M 0x0000FF00 -#define CCFG_BL_CONFIG_BL_PIN_NUMBER_S 8 - -// Field: [7:0] BL_ENABLE -// -// Enables the boot loader backdoor. -// 0xC5: Boot loader backdoor is enabled. -// Any other value: Boot loader backdoor is disabled. -// -// NOTE! Boot loader must be enabled (see BOOTLOADER_ENABLE) if boot loader -// backdoor is enabled. -#define CCFG_BL_CONFIG_BL_ENABLE_W 8 -#define CCFG_BL_CONFIG_BL_ENABLE_M 0x000000FF -#define CCFG_BL_CONFIG_BL_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_ERASE_CONF -// -//***************************************************************************** -// Field: [8] CHIP_ERASE_DIS_N -// -// Chip erase. -// This bit controls if a chip erase requested through the JTAG WUC TAP will be -// ignored in a following boot caused by a reset of the MCU VD. -// A successful chip erase operation will force the content of the flash main -// bank back to the state as it was when delivered by TI. -// 0: Disable. Any chip erase request detected during boot will be ignored. -// 1: Enable. Any chip erase request detected during boot will be performed by -// the boot FW. -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x00000100 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_BITN 8 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M 0x00000100 -#define CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S 8 - -// Field: [0] BANK_ERASE_DIS_N -// -// Bank erase. -// This bit controls if the ROM serial boot loader will accept a received Bank -// Erase command (COMMAND_BANK_ERASE). -// A successful Bank Erase operation will erase all main bank sectors not -// protected by write protect configuration bits in CCFG. -// 0: Disable the boot loader bank erase function. -// 1: Enable the boot loader bank erase function. -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x00000001 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_BITN 0 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M 0x00000001 -#define CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_TI_OPTIONS -// -//***************************************************************************** -// Field: [7:0] TI_FA_ENABLE -// -// TI Failure Analysis. -// 0xC5: Enable the functionality of unlocking the TI FA (TI Failure Analysis) -// option with the unlock code. -// All other values: Disable the functionality of unlocking the TI FA option -// with the unlock code. -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_W 8 -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M 0x000000FF -#define CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_TAP_DAP_0 -// -//***************************************************************************** -// Field: [23:16] CPU_DAP_ENABLE -// -// Enable CPU DAP. -// 0xC5: Main CPU DAP access is enabled during power-up/system-reset by ROM -// boot FW. -// Any other value: Main CPU DAP access will remain disabled out of -// power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M 0x00FF0000 -#define CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S 16 - -// Field: [15:8] PWRPROF_TAP_ENABLE -// -// Enable PWRPROF TAP. -// 0xC5: PWRPROF TAP access is enabled during power-up/system-reset by ROM boot -// FW if enabled by corresponding configuration value in FCFG1 defined by TI. -// Any other value: PWRPROF TAP access will remain disabled out of -// power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M 0x0000FF00 -#define CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S 8 - -// Field: [7:0] TEST_TAP_ENABLE -// -// Enable Test TAP. -// 0xC5: TEST TAP access is enabled during power-up/system-reset by ROM boot FW -// if enabled by corresponding configuration value in FCFG1 defined by TI. -// Any other value: TEST TAP access will remain disabled out of -// power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M 0x000000FF -#define CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_TAP_DAP_1 -// -//***************************************************************************** -// Field: [23:16] PBIST2_TAP_ENABLE -// -// Enable PBIST2 TAP. -// 0xC5: PBIST2 TAP access is enabled during power-up/system-reset by ROM boot -// FW if enabled by corresponding configuration value in FCFG1 defined by TI. -// Any other value: PBIST2 TAP access will remain disabled out of -// power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M 0x00FF0000 -#define CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S 16 - -// Field: [15:8] PBIST1_TAP_ENABLE -// -// Enable PBIST1 TAP. -// 0xC5: PBIST1 TAP access is enabled during power-up/system-reset by ROM boot -// FW if enabled by corresponding configuration value in FCFG1 defined by TI. -// Any other value: PBIST1 TAP access will remain disabled out of -// power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M 0x0000FF00 -#define CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S 8 - -// Field: [7:0] AON_TAP_ENABLE -// -// Enable AON TAP -// 0xC5: AON TAP access is enabled during power-up/system-reset by ROM boot FW -// if enabled by corresponding configuration value in FCFG1 defined by TI. -// Any other value: AON TAP access will remain disabled out of -// power-up/system-reset. -#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_W 8 -#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M 0x000000FF -#define CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_IMAGE_VALID_CONF -// -//***************************************************************************** -// Field: [31:0] IMAGE_VALID -// -// This field must have the address value of the start of the flash vector -// table in order to enable the boot FW in ROM to transfer control to a flash -// image. -// Any illegal vector table start address value will force the boot FW in ROM -// to transfer control to the serial boot loader in ROM. -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_W 32 -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_M 0xFFFFFFFF -#define CCFG_IMAGE_VALID_CONF_IMAGE_VALID_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_PROT_31_0 -// -//***************************************************************************** -// Field: [31] WRT_PROT_SEC_31 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31 0x80000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_BITN 31 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_M 0x80000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_31_S 31 - -// Field: [30] WRT_PROT_SEC_30 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30 0x40000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_BITN 30 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_M 0x40000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_30_S 30 - -// Field: [29] WRT_PROT_SEC_29 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29 0x20000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_BITN 29 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_M 0x20000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_29_S 29 - -// Field: [28] WRT_PROT_SEC_28 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28 0x10000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_BITN 28 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_M 0x10000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_28_S 28 - -// Field: [27] WRT_PROT_SEC_27 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27 0x08000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_BITN 27 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_M 0x08000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_27_S 27 - -// Field: [26] WRT_PROT_SEC_26 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26 0x04000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_BITN 26 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_M 0x04000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_26_S 26 - -// Field: [25] WRT_PROT_SEC_25 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25 0x02000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_BITN 25 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_M 0x02000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_25_S 25 - -// Field: [24] WRT_PROT_SEC_24 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24 0x01000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_BITN 24 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_M 0x01000000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_24_S 24 - -// Field: [23] WRT_PROT_SEC_23 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23 0x00800000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_BITN 23 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_M 0x00800000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_23_S 23 - -// Field: [22] WRT_PROT_SEC_22 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22 0x00400000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_BITN 22 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_M 0x00400000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_22_S 22 - -// Field: [21] WRT_PROT_SEC_21 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21 0x00200000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_BITN 21 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_M 0x00200000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_21_S 21 - -// Field: [20] WRT_PROT_SEC_20 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20 0x00100000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_BITN 20 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_M 0x00100000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_20_S 20 - -// Field: [19] WRT_PROT_SEC_19 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19 0x00080000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_BITN 19 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_M 0x00080000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_19_S 19 - -// Field: [18] WRT_PROT_SEC_18 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18 0x00040000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_BITN 18 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_M 0x00040000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_18_S 18 - -// Field: [17] WRT_PROT_SEC_17 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17 0x00020000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_BITN 17 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_M 0x00020000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_17_S 17 - -// Field: [16] WRT_PROT_SEC_16 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16 0x00010000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_BITN 16 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_M 0x00010000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_16_S 16 - -// Field: [15] WRT_PROT_SEC_15 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15 0x00008000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_BITN 15 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_M 0x00008000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_15_S 15 - -// Field: [14] WRT_PROT_SEC_14 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14 0x00004000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_BITN 14 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_M 0x00004000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_14_S 14 - -// Field: [13] WRT_PROT_SEC_13 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13 0x00002000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_BITN 13 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_M 0x00002000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_13_S 13 - -// Field: [12] WRT_PROT_SEC_12 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12 0x00001000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_BITN 12 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_M 0x00001000 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_12_S 12 - -// Field: [11] WRT_PROT_SEC_11 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11 0x00000800 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_BITN 11 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_M 0x00000800 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_11_S 11 - -// Field: [10] WRT_PROT_SEC_10 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10 0x00000400 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_BITN 10 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_M 0x00000400 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_10_S 10 - -// Field: [9] WRT_PROT_SEC_9 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9 0x00000200 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_BITN 9 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_M 0x00000200 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_9_S 9 - -// Field: [8] WRT_PROT_SEC_8 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8 0x00000100 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_BITN 8 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_M 0x00000100 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_8_S 8 - -// Field: [7] WRT_PROT_SEC_7 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7 0x00000080 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_BITN 7 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_M 0x00000080 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_7_S 7 - -// Field: [6] WRT_PROT_SEC_6 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6 0x00000040 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_BITN 6 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_M 0x00000040 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_6_S 6 - -// Field: [5] WRT_PROT_SEC_5 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5 0x00000020 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_BITN 5 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_M 0x00000020 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_5_S 5 - -// Field: [4] WRT_PROT_SEC_4 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4 0x00000010 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_BITN 4 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_M 0x00000010 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_4_S 4 - -// Field: [3] WRT_PROT_SEC_3 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3 0x00000008 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_BITN 3 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_M 0x00000008 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_3_S 3 - -// Field: [2] WRT_PROT_SEC_2 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2 0x00000004 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_BITN 2 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_M 0x00000004 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_2_S 2 - -// Field: [1] WRT_PROT_SEC_1 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1 0x00000002 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_BITN 1 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_M 0x00000002 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_1_S 1 - -// Field: [0] WRT_PROT_SEC_0 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0 0x00000001 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_BITN 0 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_M 0x00000001 -#define CCFG_CCFG_PROT_31_0_WRT_PROT_SEC_0_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_PROT_63_32 -// -//***************************************************************************** -// Field: [31] WRT_PROT_SEC_63 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63 0x80000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_BITN 31 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_M 0x80000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_63_S 31 - -// Field: [30] WRT_PROT_SEC_62 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62 0x40000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_BITN 30 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_M 0x40000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_62_S 30 - -// Field: [29] WRT_PROT_SEC_61 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61 0x20000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_BITN 29 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_M 0x20000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_61_S 29 - -// Field: [28] WRT_PROT_SEC_60 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60 0x10000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_BITN 28 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_M 0x10000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_60_S 28 - -// Field: [27] WRT_PROT_SEC_59 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59 0x08000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_BITN 27 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_M 0x08000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_59_S 27 - -// Field: [26] WRT_PROT_SEC_58 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58 0x04000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_BITN 26 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_M 0x04000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_58_S 26 - -// Field: [25] WRT_PROT_SEC_57 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57 0x02000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_BITN 25 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_M 0x02000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_57_S 25 - -// Field: [24] WRT_PROT_SEC_56 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56 0x01000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_BITN 24 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_M 0x01000000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_56_S 24 - -// Field: [23] WRT_PROT_SEC_55 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55 0x00800000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_BITN 23 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_M 0x00800000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_55_S 23 - -// Field: [22] WRT_PROT_SEC_54 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54 0x00400000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_BITN 22 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_M 0x00400000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_54_S 22 - -// Field: [21] WRT_PROT_SEC_53 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53 0x00200000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_BITN 21 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_M 0x00200000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_53_S 21 - -// Field: [20] WRT_PROT_SEC_52 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52 0x00100000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_BITN 20 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_M 0x00100000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_52_S 20 - -// Field: [19] WRT_PROT_SEC_51 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51 0x00080000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_BITN 19 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_M 0x00080000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_51_S 19 - -// Field: [18] WRT_PROT_SEC_50 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50 0x00040000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_BITN 18 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_M 0x00040000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_50_S 18 - -// Field: [17] WRT_PROT_SEC_49 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49 0x00020000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_BITN 17 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_M 0x00020000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_49_S 17 - -// Field: [16] WRT_PROT_SEC_48 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48 0x00010000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_BITN 16 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_M 0x00010000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_48_S 16 - -// Field: [15] WRT_PROT_SEC_47 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47 0x00008000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_BITN 15 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_M 0x00008000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_47_S 15 - -// Field: [14] WRT_PROT_SEC_46 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46 0x00004000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_BITN 14 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_M 0x00004000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_46_S 14 - -// Field: [13] WRT_PROT_SEC_45 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45 0x00002000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_BITN 13 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_M 0x00002000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_45_S 13 - -// Field: [12] WRT_PROT_SEC_44 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44 0x00001000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_BITN 12 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_M 0x00001000 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_44_S 12 - -// Field: [11] WRT_PROT_SEC_43 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43 0x00000800 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_BITN 11 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_M 0x00000800 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_43_S 11 - -// Field: [10] WRT_PROT_SEC_42 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42 0x00000400 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_BITN 10 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_M 0x00000400 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_42_S 10 - -// Field: [9] WRT_PROT_SEC_41 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41 0x00000200 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_BITN 9 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_M 0x00000200 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_41_S 9 - -// Field: [8] WRT_PROT_SEC_40 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40 0x00000100 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_BITN 8 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_M 0x00000100 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_40_S 8 - -// Field: [7] WRT_PROT_SEC_39 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39 0x00000080 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_BITN 7 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_M 0x00000080 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_39_S 7 - -// Field: [6] WRT_PROT_SEC_38 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38 0x00000040 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_BITN 6 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_M 0x00000040 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_38_S 6 - -// Field: [5] WRT_PROT_SEC_37 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37 0x00000020 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_BITN 5 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_M 0x00000020 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_37_S 5 - -// Field: [4] WRT_PROT_SEC_36 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36 0x00000010 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_BITN 4 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_M 0x00000010 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_36_S 4 - -// Field: [3] WRT_PROT_SEC_35 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35 0x00000008 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_BITN 3 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_M 0x00000008 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_35_S 3 - -// Field: [2] WRT_PROT_SEC_34 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34 0x00000004 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_BITN 2 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_M 0x00000004 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_34_S 2 - -// Field: [1] WRT_PROT_SEC_33 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33 0x00000002 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_BITN 1 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_M 0x00000002 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_33_S 1 - -// Field: [0] WRT_PROT_SEC_32 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32 0x00000001 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_BITN 0 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_M 0x00000001 -#define CCFG_CCFG_PROT_63_32_WRT_PROT_SEC_32_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_PROT_95_64 -// -//***************************************************************************** -// Field: [31] WRT_PROT_SEC_95 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95 0x80000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_BITN 31 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_M 0x80000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_95_S 31 - -// Field: [30] WRT_PROT_SEC_94 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94 0x40000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_BITN 30 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_M 0x40000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_94_S 30 - -// Field: [29] WRT_PROT_SEC_93 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93 0x20000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_BITN 29 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_M 0x20000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_93_S 29 - -// Field: [28] WRT_PROT_SEC_92 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92 0x10000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_BITN 28 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_M 0x10000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_92_S 28 - -// Field: [27] WRT_PROT_SEC_91 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91 0x08000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_BITN 27 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_M 0x08000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_91_S 27 - -// Field: [26] WRT_PROT_SEC_90 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90 0x04000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_BITN 26 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_M 0x04000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_90_S 26 - -// Field: [25] WRT_PROT_SEC_89 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89 0x02000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_BITN 25 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_M 0x02000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_89_S 25 - -// Field: [24] WRT_PROT_SEC_88 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88 0x01000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_BITN 24 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_M 0x01000000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_88_S 24 - -// Field: [23] WRT_PROT_SEC_87 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87 0x00800000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_BITN 23 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_M 0x00800000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_87_S 23 - -// Field: [22] WRT_PROT_SEC_86 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86 0x00400000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_BITN 22 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_M 0x00400000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_86_S 22 - -// Field: [21] WRT_PROT_SEC_85 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85 0x00200000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_BITN 21 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_M 0x00200000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_85_S 21 - -// Field: [20] WRT_PROT_SEC_84 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84 0x00100000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_BITN 20 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_M 0x00100000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_84_S 20 - -// Field: [19] WRT_PROT_SEC_83 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83 0x00080000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_BITN 19 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_M 0x00080000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_83_S 19 - -// Field: [18] WRT_PROT_SEC_82 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82 0x00040000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_BITN 18 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_M 0x00040000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_82_S 18 - -// Field: [17] WRT_PROT_SEC_81 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81 0x00020000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_BITN 17 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_M 0x00020000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_81_S 17 - -// Field: [16] WRT_PROT_SEC_80 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80 0x00010000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_BITN 16 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_M 0x00010000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_80_S 16 - -// Field: [15] WRT_PROT_SEC_79 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79 0x00008000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_BITN 15 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_M 0x00008000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_79_S 15 - -// Field: [14] WRT_PROT_SEC_78 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78 0x00004000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_BITN 14 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_M 0x00004000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_78_S 14 - -// Field: [13] WRT_PROT_SEC_77 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77 0x00002000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_BITN 13 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_M 0x00002000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_77_S 13 - -// Field: [12] WRT_PROT_SEC_76 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76 0x00001000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_BITN 12 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_M 0x00001000 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_76_S 12 - -// Field: [11] WRT_PROT_SEC_75 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75 0x00000800 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_BITN 11 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_M 0x00000800 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_75_S 11 - -// Field: [10] WRT_PROT_SEC_74 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74 0x00000400 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_BITN 10 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_M 0x00000400 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_74_S 10 - -// Field: [9] WRT_PROT_SEC_73 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73 0x00000200 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_BITN 9 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_M 0x00000200 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_73_S 9 - -// Field: [8] WRT_PROT_SEC_72 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72 0x00000100 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_BITN 8 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_M 0x00000100 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_72_S 8 - -// Field: [7] WRT_PROT_SEC_71 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71 0x00000080 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_BITN 7 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_M 0x00000080 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_71_S 7 - -// Field: [6] WRT_PROT_SEC_70 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70 0x00000040 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_BITN 6 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_M 0x00000040 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_70_S 6 - -// Field: [5] WRT_PROT_SEC_69 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69 0x00000020 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_BITN 5 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_M 0x00000020 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_69_S 5 - -// Field: [4] WRT_PROT_SEC_68 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68 0x00000010 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_BITN 4 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_M 0x00000010 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_68_S 4 - -// Field: [3] WRT_PROT_SEC_67 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67 0x00000008 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_BITN 3 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_M 0x00000008 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_67_S 3 - -// Field: [2] WRT_PROT_SEC_66 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66 0x00000004 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_BITN 2 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_M 0x00000004 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_66_S 2 - -// Field: [1] WRT_PROT_SEC_65 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65 0x00000002 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_BITN 1 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_M 0x00000002 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_65_S 1 - -// Field: [0] WRT_PROT_SEC_64 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64 0x00000001 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_BITN 0 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_M 0x00000001 -#define CCFG_CCFG_PROT_95_64_WRT_PROT_SEC_64_S 0 - -//***************************************************************************** -// -// Register: CCFG_O_CCFG_PROT_127_96 -// -//***************************************************************************** -// Field: [31] WRT_PROT_SEC_127 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127 0x80000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_BITN 31 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_M 0x80000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_127_S 31 - -// Field: [30] WRT_PROT_SEC_126 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126 0x40000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_BITN 30 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_M 0x40000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_126_S 30 - -// Field: [29] WRT_PROT_SEC_125 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125 0x20000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_BITN 29 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_M 0x20000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_125_S 29 - -// Field: [28] WRT_PROT_SEC_124 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124 0x10000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_BITN 28 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_M 0x10000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_124_S 28 - -// Field: [27] WRT_PROT_SEC_123 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123 0x08000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_BITN 27 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_M 0x08000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_123_S 27 - -// Field: [26] WRT_PROT_SEC_122 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122 0x04000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_BITN 26 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_M 0x04000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_122_S 26 - -// Field: [25] WRT_PROT_SEC_121 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121 0x02000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_BITN 25 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_M 0x02000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_121_S 25 - -// Field: [24] WRT_PROT_SEC_120 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120 0x01000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_BITN 24 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_M 0x01000000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_120_S 24 - -// Field: [23] WRT_PROT_SEC_119 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119 0x00800000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_BITN 23 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_M 0x00800000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_119_S 23 - -// Field: [22] WRT_PROT_SEC_118 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118 0x00400000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_BITN 22 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_M 0x00400000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_118_S 22 - -// Field: [21] WRT_PROT_SEC_117 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117 0x00200000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_BITN 21 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_M 0x00200000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_117_S 21 - -// Field: [20] WRT_PROT_SEC_116 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116 0x00100000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_BITN 20 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_M 0x00100000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_116_S 20 - -// Field: [19] WRT_PROT_SEC_115 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115 0x00080000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_BITN 19 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_M 0x00080000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_115_S 19 - -// Field: [18] WRT_PROT_SEC_114 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114 0x00040000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_BITN 18 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_M 0x00040000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_114_S 18 - -// Field: [17] WRT_PROT_SEC_113 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113 0x00020000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_BITN 17 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_M 0x00020000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_113_S 17 - -// Field: [16] WRT_PROT_SEC_112 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112 0x00010000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_BITN 16 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_M 0x00010000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_112_S 16 - -// Field: [15] WRT_PROT_SEC_111 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111 0x00008000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_BITN 15 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_M 0x00008000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_111_S 15 - -// Field: [14] WRT_PROT_SEC_110 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110 0x00004000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_BITN 14 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_M 0x00004000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_110_S 14 - -// Field: [13] WRT_PROT_SEC_109 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109 0x00002000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_BITN 13 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_M 0x00002000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_109_S 13 - -// Field: [12] WRT_PROT_SEC_108 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108 0x00001000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_BITN 12 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_M 0x00001000 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_108_S 12 - -// Field: [11] WRT_PROT_SEC_107 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107 0x00000800 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_BITN 11 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_M 0x00000800 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_107_S 11 - -// Field: [10] WRT_PROT_SEC_106 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106 0x00000400 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_BITN 10 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_M 0x00000400 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_106_S 10 - -// Field: [9] WRT_PROT_SEC_105 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105 0x00000200 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_BITN 9 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_M 0x00000200 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_105_S 9 - -// Field: [8] WRT_PROT_SEC_104 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104 0x00000100 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_BITN 8 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_M 0x00000100 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_104_S 8 - -// Field: [7] WRT_PROT_SEC_103 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103 0x00000080 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_BITN 7 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_M 0x00000080 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_103_S 7 - -// Field: [6] WRT_PROT_SEC_102 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102 0x00000040 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_BITN 6 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_M 0x00000040 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_102_S 6 - -// Field: [5] WRT_PROT_SEC_101 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101 0x00000020 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_BITN 5 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_M 0x00000020 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_101_S 5 - -// Field: [4] WRT_PROT_SEC_100 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100 0x00000010 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_BITN 4 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_M 0x00000010 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_100_S 4 - -// Field: [3] WRT_PROT_SEC_99 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99 0x00000008 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_BITN 3 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_M 0x00000008 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_99_S 3 - -// Field: [2] WRT_PROT_SEC_98 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98 0x00000004 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_BITN 2 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_M 0x00000004 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_98_S 2 - -// Field: [1] WRT_PROT_SEC_97 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97 0x00000002 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_BITN 1 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_M 0x00000002 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_97_S 1 - -// Field: [0] WRT_PROT_SEC_96 -// -// 0: Sector protected -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96 0x00000001 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_BITN 0 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_M 0x00000001 -#define CCFG_CCFG_PROT_127_96_WRT_PROT_SEC_96_S 0 - - -#endif // __CCFG__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h deleted file mode 100644 index 59fec586263..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ccfg_simple_struct.h +++ /dev/null @@ -1,81 +0,0 @@ -/****************************************************************************** -* Filename: hw_ccfg_simple_struct_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CCFG_SIMPLE_STRUCT_H__ -#define __HW_CCFG_SIMPLE_STRUCT_H__ - -//***************************************************************************** -// -// Customer configuration (ccfg) typedef. -// The implementation of this struct is required by device ROM boot code -// and must be placed at the end of flash. Do not modify this struct! -// -//***************************************************************************** -typedef struct -{ // Mapped to address - uint32_t CCFG_EXT_LF_CLK ; // 0x50004FA8 - uint32_t CCFG_MODE_CONF_1 ; // 0x50004FAC - uint32_t CCFG_SIZE_AND_DIS_FLAGS ; // 0x50004FB0 - uint32_t CCFG_MODE_CONF ; // 0x50004FB4 - uint32_t CCFG_VOLT_LOAD_0 ; // 0x50004FB8 - uint32_t CCFG_VOLT_LOAD_1 ; // 0x50004FBC - uint32_t CCFG_RTC_OFFSET ; // 0x50004FC0 - uint32_t CCFG_FREQ_OFFSET ; // 0x50004FC4 - uint32_t CCFG_IEEE_MAC_0 ; // 0x50004FC8 - uint32_t CCFG_IEEE_MAC_1 ; // 0x50004FCC - uint32_t CCFG_IEEE_BLE_0 ; // 0x50004FD0 - uint32_t CCFG_IEEE_BLE_1 ; // 0x50004FD4 - uint32_t CCFG_BL_CONFIG ; // 0x50004FD8 - uint32_t CCFG_ERASE_CONF ; // 0x50004FDC - uint32_t CCFG_CCFG_TI_OPTIONS ; // 0x50004FE0 - uint32_t CCFG_CCFG_TAP_DAP_0 ; // 0x50004FE4 - uint32_t CCFG_CCFG_TAP_DAP_1 ; // 0x50004FE8 - uint32_t CCFG_IMAGE_VALID_CONF ; // 0x50004FEC - uint32_t CCFG_CCFG_PROT_31_0 ; // 0x50004FF0 - uint32_t CCFG_CCFG_PROT_63_32 ; // 0x50004FF4 - uint32_t CCFG_CCFG_PROT_95_64 ; // 0x50004FF8 - uint32_t CCFG_CCFG_PROT_127_96 ; // 0x50004FFC -} ccfg_t; - -//***************************************************************************** -// -// Define the extern ccfg structure (__ccfg) -// -//***************************************************************************** -extern const ccfg_t __ccfg; - - -#endif // __HW_CCFG_SIMPLE_STRUCT__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h deleted file mode 100644 index 19f70e0875c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_chip_def.h +++ /dev/null @@ -1,234 +0,0 @@ -/****************************************************************************** -* Filename: hw_chip_def.h -* Revised: 2017-06-26 09:33:33 +0200 (Mon, 26 Jun 2017) -* Revision: 49227 -* -* Description: Defines for device properties. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -//***************************************************************************** -// -//! \addtogroup config_api -//! @{ -// -//***************************************************************************** - -#ifndef __HW_CHIP_DEF_H__ -#define __HW_CHIP_DEF_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Define CC_CHIP_ID code used in the following macros defined at the bottom: -// CC_GET_CHIP_FAMILY/DEVICE/PACKAGE/HWREV -// -//***************************************************************************** -/* CC2620F128 */ -#if defined(CC2620F128RGZ_R20) || defined(CC2620F128RGZ_R21) - #define CC_CHIP_ID 0x26200720 -#elif defined(CC2620F128RHB_R20) || defined(CC2620F128RHB_R21) - #define CC_CHIP_ID 0x26200520 -#elif defined(CC2620F128RSM_R20) || defined(CC2620F128RSM_R21) - #define CC_CHIP_ID 0x26200420 -#elif defined(CC2620F128_R20) || defined(CC2620F128_R21) - #define CC_CHIP_ID 0x26200020 -#elif defined(CC2620F128RGZ_R22) || defined(CC2620F128RGZ) - #define CC_CHIP_ID 0x26200722 -#elif defined(CC2620F128RHB_R22) || defined(CC2620F128RHB) - #define CC_CHIP_ID 0x26200522 -#elif defined(CC2620F128RSM_R22) || defined(CC2620F128RSM) - #define CC_CHIP_ID 0x26200422 -#elif defined(CC2620F128_R22) || defined(CC2620F128) - #define CC_CHIP_ID 0x26200022 -/* CC2630F128 */ -#elif defined(CC2630F128RGZ_R20) || defined(CC2630F128RGZ_R21) - #define CC_CHIP_ID 0x26300720 -#elif defined(CC2630F128RHB_R20) || defined(CC2630F128RHB_R21) - #define CC_CHIP_ID 0x26300520 -#elif defined(CC2630F128RSM_R20) || defined(CC2630F128RSM_R21) - #define CC_CHIP_ID 0x26300420 -#elif defined(CC2630F128_R20) || defined(CC2630F128_R21) - #define CC_CHIP_ID 0x26300020 -#elif defined(CC2630F128RGZ_R22) || defined(CC2630F128RGZ) - #define CC_CHIP_ID 0x26300722 -#elif defined(CC2630F128RHB_R22) || defined(CC2630F128RHB) - #define CC_CHIP_ID 0x26300522 -#elif defined(CC2630F128RSM_R22) || defined(CC2630F128RSM) - #define CC_CHIP_ID 0x26300422 -#elif defined(CC2630F128_R22) || defined(CC2630F128) - #define CC_CHIP_ID 0x26300022 -/* CC2640F128 */ -#elif defined(CC2640F128RGZ_R20) || defined(CC2640F128RGZ_R21) - #define CC_CHIP_ID 0x26400720 -#elif defined(CC2640F128RHB_R20) || defined(CC2640F128RHB_R21) - #define CC_CHIP_ID 0x26400520 -#elif defined(CC2640F128RSM_R20) || defined(CC2640F128RSM_R21) - #define CC_CHIP_ID 0x26400420 -#elif defined(CC2640F128_R20) || defined(CC2640F128_R21) - #define CC_CHIP_ID 0x26400020 -#elif defined(CC2640F128RGZ_R22) || defined(CC2640F128RGZ) - #define CC_CHIP_ID 0x26400722 -#elif defined(CC2640F128RHB_R22) || defined(CC2640F128RHB) - #define CC_CHIP_ID 0x26400522 -#elif defined(CC2640F128RSM_R22) || defined(CC2640F128RSM) - #define CC_CHIP_ID 0x26400422 -#elif defined(CC2640F128_R22) || defined(CC2640F128) - #define CC_CHIP_ID 0x26400022 -/* CC2650F128 */ -#elif defined(CC2650F128RGZ_R20) || defined(CC2650F128RGZ_R21) - #define CC_CHIP_ID 0x26500720 -#elif defined(CC2650F128RHB_R20) || defined(CC2650F128RHB_R21) - #define CC_CHIP_ID 0x26500520 -#elif defined(CC2650F128RSM_R20) || defined(CC2650F128RSM_R21) - #define CC_CHIP_ID 0x26500420 -#elif defined(CC2650F128_R20) || defined(CC2650F128_R21) - #define CC_CHIP_ID 0x26500020 -#elif defined(CC2650F128RGZ_R22) || defined(CC2650F128RGZ) - #define CC_CHIP_ID 0x26500722 -#elif defined(CC2650F128RHB_R22) || defined(CC2650F128RHB) - #define CC_CHIP_ID 0x26500522 -#elif defined(CC2650F128RSM_R22) || defined(CC2650F128RSM) - #define CC_CHIP_ID 0x26500422 -#elif defined(CC2650F128_R22) || defined(CC2650F128) - #define CC_CHIP_ID 0x26500022 -/* CC2650L128 (OTP) */ -#elif defined(CC2650L128) - #define CC_CHIP_ID 0x26501710 -/* CC1310F128 */ -#elif defined(CC1310F128RGZ_R20) || defined(CC1310F128RGZ) - #define CC_CHIP_ID 0x13100720 -#elif defined(CC1310F128RHB_R20) || defined(CC1310F128RHB) - #define CC_CHIP_ID 0x13100520 -#elif defined(CC1310F128RSM_R20) || defined(CC1310F128RSM) - #define CC_CHIP_ID 0x13100420 -#elif defined(CC1310F128_R20) || defined(CC1310F128) - #define CC_CHIP_ID 0x13100020 -/* CC1350F128 */ -#elif defined(CC1350F128RGZ_R20) || defined(CC1350F128RGZ) - #define CC_CHIP_ID 0x13500720 -#elif defined(CC1350F128RHB_R20) || defined(CC1350F128RHB) - #define CC_CHIP_ID 0x13500520 -#elif defined(CC1350F128RSM_R20) || defined(CC1350F128RSM) - #define CC_CHIP_ID 0x13500420 -#elif defined(CC1350F128_R20) || defined(CC1350F128) - #define CC_CHIP_ID 0x13500020 -/* CC2640R2F */ -#elif defined(CC2640R2FRGZ_R25) || defined(CC2640R2FRGZ) - #define CC_CHIP_ID 0x26401710 -#elif defined(CC2640R2FRHB_R25) || defined(CC2640R2FRHB) - #define CC_CHIP_ID 0x26401510 -#elif defined(CC2640R2FRSM_R25) || defined(CC2640R2FRSM) - #define CC_CHIP_ID 0x26401410 -#elif defined(CC2640R2F_R25) || defined(CC2640R2F) - #define CC_CHIP_ID 0x26401010 -/* CC2652R1F */ -#elif defined(CC2652R1FRGZ_R10) || defined(CC2652R1FRGZ) - #define CC_CHIP_ID 0x26523710 -#elif defined(CC2652R1F_R10) || defined(CC2652R1F) - #define CC_CHIP_ID 0x26523010 -/* CC2644R1F */ -#elif defined(CC2644R1FRGZ_R10) || defined(CC2644R1FRGZ) - #define CC_CHIP_ID 0x26443710 -#elif defined(CC2644R1F_R10) || defined(CC2644R1F) - #define CC_CHIP_ID 0x26443010 -/* CC2642R1F */ -#elif defined(CC2642R1FRGZ_R10) || defined(CC2642R1FRGZ) - #define CC_CHIP_ID 0x26423710 -#elif defined(CC2642R1F_R10) || defined(CC2642R1F) - #define CC_CHIP_ID 0x26423010 -/* CC1354R1F */ -#elif defined(CC1354R1FRGZ_R10) || defined(CC1354R1FRGZ) - #define CC_CHIP_ID 0x13543710 -#elif defined(CC1354R1F_R10) || defined(CC1354R1F) - #define CC_CHIP_ID 0x13543010 -/* CC1352R1F */ -#elif defined(CC1352R1FRGZ_R10) || defined(CC1352R1FRGZ) - #define CC_CHIP_ID 0x13523710 -#elif defined(CC1352R1F_R10) || defined(CC1352R1F) - #define CC_CHIP_ID 0x13523010 -/* CC1312R1F */ -#elif defined(CC1312R1FRGZ_R10) || defined(CC1312R1FRGZ) - #define CC_CHIP_ID 0x13123710 -#elif defined(CC1312R1F_R10) || defined(CC1312R1F) - #define CC_CHIP_ID 0x13123010 -#endif - -#define CC_GET_CHIP_FAMILY 0x26 -#define CC_GET_CHIP_OPTION 0x3 -#define CC_GET_CHIP_HWREV 0x20 - -#ifdef CC_CHIP_ID - /* Define chip package only if specified */ - #if (CC_CHIP_ID & 0x00000F00) != 0 - #define CC_GET_CHIP_PACKAGE (((CC_CHIP_ID) & 0x00000F00) >> 8) - #endif - - /* Define chip device */ - #define CC_GET_CHIP_DEVICE (((CC_CHIP_ID) & 0xFFFF0000) >> 16) - - /* The chip family, option and package shall match the DriverLib release */ - #if (CC_GET_CHIP_OPTION != ((CC_CHIP_ID & 0x0000F000) >> 12)) - #error "Specified chip option does not match DriverLib release" - #endif - #if (CC_GET_CHIP_HWREV != ((CC_CHIP_ID & 0x000000FF) >> 0)) - #error "Specified chip hardware revision does not match DriverLib release" - #endif -#endif - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __HW_CHIP_DEF_H__ - -//***************************************************************************** -// -//! Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h deleted file mode 100644 index fa62b893f23..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_dwt.h +++ /dev/null @@ -1,856 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_dwt_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_DWT_H__ -#define __HW_CPU_DWT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_DWT component -// -//***************************************************************************** -// Control -#define CPU_DWT_O_CTRL 0x00000000 - -// Current PC Sampler Cycle Count -#define CPU_DWT_O_CYCCNT 0x00000004 - -// CPI Count -#define CPU_DWT_O_CPICNT 0x00000008 - -// Exception Overhead Count -#define CPU_DWT_O_EXCCNT 0x0000000C - -// Sleep Count -#define CPU_DWT_O_SLEEPCNT 0x00000010 - -// LSU Count -#define CPU_DWT_O_LSUCNT 0x00000014 - -// Fold Count -#define CPU_DWT_O_FOLDCNT 0x00000018 - -// Program Counter Sample -#define CPU_DWT_O_PCSR 0x0000001C - -// Comparator 0 -#define CPU_DWT_O_COMP0 0x00000020 - -// Mask 0 -#define CPU_DWT_O_MASK0 0x00000024 - -// Function 0 -#define CPU_DWT_O_FUNCTION0 0x00000028 - -// Comparator 1 -#define CPU_DWT_O_COMP1 0x00000030 - -// Mask 1 -#define CPU_DWT_O_MASK1 0x00000034 - -// Function 1 -#define CPU_DWT_O_FUNCTION1 0x00000038 - -// Comparator 2 -#define CPU_DWT_O_COMP2 0x00000040 - -// Mask 2 -#define CPU_DWT_O_MASK2 0x00000044 - -// Function 2 -#define CPU_DWT_O_FUNCTION2 0x00000048 - -// Comparator 3 -#define CPU_DWT_O_COMP3 0x00000050 - -// Mask 3 -#define CPU_DWT_O_MASK3 0x00000054 - -// Function 3 -#define CPU_DWT_O_FUNCTION3 0x00000058 - -//***************************************************************************** -// -// Register: CPU_DWT_O_CTRL -// -//***************************************************************************** -// Field: [25] NOCYCCNT -// -// When set, CYCCNT is not supported. -#define CPU_DWT_CTRL_NOCYCCNT 0x02000000 -#define CPU_DWT_CTRL_NOCYCCNT_BITN 25 -#define CPU_DWT_CTRL_NOCYCCNT_M 0x02000000 -#define CPU_DWT_CTRL_NOCYCCNT_S 25 - -// Field: [24] NOPRFCNT -// -// When set, FOLDCNT, LSUCNT, SLEEPCNT, EXCCNT, and CPICNT are not supported. -#define CPU_DWT_CTRL_NOPRFCNT 0x01000000 -#define CPU_DWT_CTRL_NOPRFCNT_BITN 24 -#define CPU_DWT_CTRL_NOPRFCNT_M 0x01000000 -#define CPU_DWT_CTRL_NOPRFCNT_S 24 - -// Field: [22] CYCEVTENA -// -// Enables Cycle count event. Emits an event when the POSTCNT counter triggers -// it. See CYCTAP and POSTPRESET for details. This event is only emitted if -// PCSAMPLEENA is disabled. PCSAMPLEENA overrides the setting of this bit. -// -// 0: Cycle count events disabled -// 1: Cycle count events enabled -#define CPU_DWT_CTRL_CYCEVTENA 0x00400000 -#define CPU_DWT_CTRL_CYCEVTENA_BITN 22 -#define CPU_DWT_CTRL_CYCEVTENA_M 0x00400000 -#define CPU_DWT_CTRL_CYCEVTENA_S 22 - -// Field: [21] FOLDEVTENA -// -// Enables Folded instruction count event. Emits an event when FOLDCNT -// overflows (every 256 cycles of folded instructions). A folded instruction is -// one that does not incur even one cycle to execute. For example, an IT -// instruction is folded away and so does not use up one cycle. -// -// 0: Folded instruction count events disabled. -// 1: Folded instruction count events enabled. -#define CPU_DWT_CTRL_FOLDEVTENA 0x00200000 -#define CPU_DWT_CTRL_FOLDEVTENA_BITN 21 -#define CPU_DWT_CTRL_FOLDEVTENA_M 0x00200000 -#define CPU_DWT_CTRL_FOLDEVTENA_S 21 - -// Field: [20] LSUEVTENA -// -// Enables LSU count event. Emits an event when LSUCNT overflows (every 256 -// cycles of LSU operation). LSU counts include all LSU costs after the initial -// cycle for the instruction. -// -// 0: LSU count events disabled. -// 1: LSU count events enabled. -#define CPU_DWT_CTRL_LSUEVTENA 0x00100000 -#define CPU_DWT_CTRL_LSUEVTENA_BITN 20 -#define CPU_DWT_CTRL_LSUEVTENA_M 0x00100000 -#define CPU_DWT_CTRL_LSUEVTENA_S 20 - -// Field: [19] SLEEPEVTENA -// -// Enables Sleep count event. Emits an event when SLEEPCNT overflows (every 256 -// cycles that the processor is sleeping). -// -// 0: Sleep count events disabled. -// 1: Sleep count events enabled. -#define CPU_DWT_CTRL_SLEEPEVTENA 0x00080000 -#define CPU_DWT_CTRL_SLEEPEVTENA_BITN 19 -#define CPU_DWT_CTRL_SLEEPEVTENA_M 0x00080000 -#define CPU_DWT_CTRL_SLEEPEVTENA_S 19 - -// Field: [18] EXCEVTENA -// -// Enables Interrupt overhead event. Emits an event when EXCCNT overflows -// (every 256 cycles of interrupt overhead). -// -// 0x0: Interrupt overhead event disabled. -// 0x1: Interrupt overhead event enabled. -#define CPU_DWT_CTRL_EXCEVTENA 0x00040000 -#define CPU_DWT_CTRL_EXCEVTENA_BITN 18 -#define CPU_DWT_CTRL_EXCEVTENA_M 0x00040000 -#define CPU_DWT_CTRL_EXCEVTENA_S 18 - -// Field: [17] CPIEVTENA -// -// Enables CPI count event. Emits an event when CPICNT overflows (every 256 -// cycles of multi-cycle instructions). -// -// 0: CPI counter events disabled. -// 1: CPI counter events enabled. -#define CPU_DWT_CTRL_CPIEVTENA 0x00020000 -#define CPU_DWT_CTRL_CPIEVTENA_BITN 17 -#define CPU_DWT_CTRL_CPIEVTENA_M 0x00020000 -#define CPU_DWT_CTRL_CPIEVTENA_S 17 - -// Field: [16] EXCTRCENA -// -// Enables Interrupt event tracing. -// -// 0: Interrupt event trace disabled. -// 1: Interrupt event trace enabled. -#define CPU_DWT_CTRL_EXCTRCENA 0x00010000 -#define CPU_DWT_CTRL_EXCTRCENA_BITN 16 -#define CPU_DWT_CTRL_EXCTRCENA_M 0x00010000 -#define CPU_DWT_CTRL_EXCTRCENA_S 16 - -// Field: [12] PCSAMPLEENA -// -// Enables PC Sampling event. A PC sample event is emitted when the POSTCNT -// counter triggers it. See CYCTAP and POSTPRESET for details. Enabling this -// bit overrides CYCEVTENA. -// -// 0: PC Sampling event disabled. -// 1: Sampling event enabled. -#define CPU_DWT_CTRL_PCSAMPLEENA 0x00001000 -#define CPU_DWT_CTRL_PCSAMPLEENA_BITN 12 -#define CPU_DWT_CTRL_PCSAMPLEENA_M 0x00001000 -#define CPU_DWT_CTRL_PCSAMPLEENA_S 12 - -// Field: [11:10] SYNCTAP -// -// Selects a synchronization packet rate. CYCCNTENA and CPU_ITM:TCR.SYNCENA -// must also be enabled for this feature. -// Synchronization packets (if enabled) are generated on tap transitions (0 to1 -// or 1 to 0). -// ENUMs: -// BIT28 Tap at bit 28 of CYCCNT -// BIT26 Tap at bit 26 of CYCCNT -// BIT24 Tap at bit 24 of CYCCNT -// DIS Disabled. No synchronization packets -#define CPU_DWT_CTRL_SYNCTAP_W 2 -#define CPU_DWT_CTRL_SYNCTAP_M 0x00000C00 -#define CPU_DWT_CTRL_SYNCTAP_S 10 -#define CPU_DWT_CTRL_SYNCTAP_BIT28 0x00000C00 -#define CPU_DWT_CTRL_SYNCTAP_BIT26 0x00000800 -#define CPU_DWT_CTRL_SYNCTAP_BIT24 0x00000400 -#define CPU_DWT_CTRL_SYNCTAP_DIS 0x00000000 - -// Field: [9] CYCTAP -// -// Selects a tap on CYCCNT. These are spaced at bits [6] and [10]. When the -// selected bit in CYCCNT changes from 0 to 1 or 1 to 0, it emits into the -// POSTCNT, post-scalar counter. That counter then counts down. On a bit change -// when post-scalar is 0, it triggers an event for PC sampling or cycle count -// event (see details in CYCEVTENA). -// ENUMs: -// BIT10 Selects bit [10] to tap -// BIT6 Selects bit [6] to tap -#define CPU_DWT_CTRL_CYCTAP 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_BITN 9 -#define CPU_DWT_CTRL_CYCTAP_M 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_S 9 -#define CPU_DWT_CTRL_CYCTAP_BIT10 0x00000200 -#define CPU_DWT_CTRL_CYCTAP_BIT6 0x00000000 - -// Field: [8:5] POSTCNT -// -// Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 -// to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it -// triggers an event for PCSAMPLEENA or CYCEVTENA use. It also reloads with the -// value from POSTPRESET. -#define CPU_DWT_CTRL_POSTCNT_W 4 -#define CPU_DWT_CTRL_POSTCNT_M 0x000001E0 -#define CPU_DWT_CTRL_POSTCNT_S 5 - -// Field: [4:1] POSTPRESET -// -// Reload value for post-scalar counter POSTCNT. When 0, events are triggered -// on each tap change (a power of 2). If this field has a non-0 value, it forms -// a count-down value, to be reloaded into POSTCNT each time it reaches 0. For -// example, a value 1 in this register means an event is formed every other tap -// change. -#define CPU_DWT_CTRL_POSTPRESET_W 4 -#define CPU_DWT_CTRL_POSTPRESET_M 0x0000001E -#define CPU_DWT_CTRL_POSTPRESET_S 1 - -// Field: [0] CYCCNTENA -// -// Enable CYCCNT, allowing it to increment and generate synchronization and -// count events. If NOCYCCNT = 1, this bit reads zero and ignore writes. -#define CPU_DWT_CTRL_CYCCNTENA 0x00000001 -#define CPU_DWT_CTRL_CYCCNTENA_BITN 0 -#define CPU_DWT_CTRL_CYCCNTENA_M 0x00000001 -#define CPU_DWT_CTRL_CYCCNTENA_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_CYCCNT -// -//***************************************************************************** -// Field: [31:0] CYCCNT -// -// Current PC Sampler Cycle Counter count value. When enabled, this counter -// counts the number of core cycles, except when the core is halted. The cycle -// counter is a free running counter, counting upwards (this counter will not -// advance in power modes where free-running clock to CPU stops). It wraps -// around to 0 on overflow. The debugger must initialize this to 0 when first -// enabling. -#define CPU_DWT_CYCCNT_CYCCNT_W 32 -#define CPU_DWT_CYCCNT_CYCCNT_M 0xFFFFFFFF -#define CPU_DWT_CYCCNT_CYCCNT_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_CPICNT -// -//***************************************************************************** -// Field: [7:0] CPICNT -// -// Current CPI counter value. Increments on the additional cycles (the first -// cycle is not counted) required to execute all instructions except those -// recorded by LSUCNT. This counter also increments on all instruction fetch -// stalls. If CTRL.CPIEVTENA is set, an event is emitted when the counter -// overflows. This counter initializes to 0 when it is enabled using -// CTRL.CPIEVTENA. -#define CPU_DWT_CPICNT_CPICNT_W 8 -#define CPU_DWT_CPICNT_CPICNT_M 0x000000FF -#define CPU_DWT_CPICNT_CPICNT_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_EXCCNT -// -//***************************************************************************** -// Field: [7:0] EXCCNT -// -// Current interrupt overhead counter value. Counts the total cycles spent in -// interrupt processing (for example entry stacking, return unstacking, -// pre-emption). An event is emitted on counter overflow (every 256 cycles). -// This counter initializes to 0 when it is enabled using CTRL.EXCEVTENA. -#define CPU_DWT_EXCCNT_EXCCNT_W 8 -#define CPU_DWT_EXCCNT_EXCCNT_M 0x000000FF -#define CPU_DWT_EXCCNT_EXCCNT_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_SLEEPCNT -// -//***************************************************************************** -// Field: [7:0] SLEEPCNT -// -// Sleep counter. Counts the number of cycles during which the processor is -// sleeping. An event is emitted on counter overflow (every 256 cycles). This -// counter initializes to 0 when it is enabled using CTRL.SLEEPEVTENA. Note -// that the sleep counter is clocked using CPU's free-running clock. In some -// power modes the free-running clock to CPU is gated to minimize power -// consumption. This means that the sleep counter will be invalid in these -// power modes. -#define CPU_DWT_SLEEPCNT_SLEEPCNT_W 8 -#define CPU_DWT_SLEEPCNT_SLEEPCNT_M 0x000000FF -#define CPU_DWT_SLEEPCNT_SLEEPCNT_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_LSUCNT -// -//***************************************************************************** -// Field: [7:0] LSUCNT -// -// LSU counter. This counts the total number of cycles that the processor is -// processing an LSU operation. The initial execution cost of the instruction -// is not counted. For example, an LDR that takes two cycles to complete -// increments this counter one cycle. Equivalently, an LDR that stalls for two -// cycles (i.e. takes four cycles to execute), increments this counter three -// times. An event is emitted on counter overflow (every 256 cycles). This -// counter initializes to 0 when it is enabled using CTRL.LSUEVTENA. -#define CPU_DWT_LSUCNT_LSUCNT_W 8 -#define CPU_DWT_LSUCNT_LSUCNT_M 0x000000FF -#define CPU_DWT_LSUCNT_LSUCNT_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_FOLDCNT -// -//***************************************************************************** -// Field: [7:0] FOLDCNT -// -// This counts the total number folded instructions. This counter initializes -// to 0 when it is enabled using CTRL.FOLDEVTENA. -#define CPU_DWT_FOLDCNT_FOLDCNT_W 8 -#define CPU_DWT_FOLDCNT_FOLDCNT_M 0x000000FF -#define CPU_DWT_FOLDCNT_FOLDCNT_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_PCSR -// -//***************************************************************************** -// Field: [31:0] EIASAMPLE -// -// Execution instruction address sample, or 0xFFFFFFFF if the core is halted. -#define CPU_DWT_PCSR_EIASAMPLE_W 32 -#define CPU_DWT_PCSR_EIASAMPLE_M 0xFFFFFFFF -#define CPU_DWT_PCSR_EIASAMPLE_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_COMP0 -// -//***************************************************************************** -// Field: [31:0] COMP -// -// Reference value to compare against PC or the data address as given by -// FUNCTION0. Comparator 0 can also compare against the value of the PC Sampler -// Counter (CYCCNT). -#define CPU_DWT_COMP0_COMP_W 32 -#define CPU_DWT_COMP0_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP0_COMP_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_MASK0 -// -//***************************************************************************** -// Field: [3:0] MASK -// -// Mask on data address when matching against COMP0. This is the size of the -// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF -// left bit-shifted by MASK)) == COMP0. However, the actual comparison is -// slightly more complex to enable matching an address wherever it appears on a -// bus. So, if COMP0 is 3, this matches a word access of 0, because 3 would be -// within the word. -#define CPU_DWT_MASK0_MASK_W 4 -#define CPU_DWT_MASK0_MASK_M 0x0000000F -#define CPU_DWT_MASK0_MASK_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_FUNCTION0 -// -//***************************************************************************** -// Field: [24] MATCHED -// -// This bit is set when the comparator matches, and indicates that the -// operation defined by FUNCTION has occurred since this bit was last read. -// This bit is cleared on read. -#define CPU_DWT_FUNCTION0_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION0_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION0_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION0_MATCHED_S 24 - -// Field: [7] CYCMATCH -// -// This bit is only available in comparator 0. When set, COMP0 will compare -// against the cycle counter (CYCCNT). -#define CPU_DWT_FUNCTION0_CYCMATCH 0x00000080 -#define CPU_DWT_FUNCTION0_CYCMATCH_BITN 7 -#define CPU_DWT_FUNCTION0_CYCMATCH_M 0x00000080 -#define CPU_DWT_FUNCTION0_CYCMATCH_S 7 - -// Field: [5] EMITRANGE -// -// Emit range field. This bit permits emitting offset when range match occurs. -// PC sampling is not supported when emit range is enabled. -// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION0_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION0_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION0_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION0_EMITRANGE_S 5 - -// Field: [3:0] FUNCTION -// -// Function settings. -// -// 0x0: Disabled -// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit -// address offset through ITM -// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, -// emit data and address offset through ITM on read or write. -// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. -// EMITRANGE = 1, emit address offset and data value through ITM on read or -// write. -// 0x4: Watchpoint on PC match. -// 0x5: Watchpoint on read. -// 0x6: Watchpoint on write. -// 0x7: Watchpoint on read or write. -// 0x8: ETM trigger on PC match -// 0x9: ETM trigger on read -// 0xA: ETM trigger on write -// 0xB: ETM trigger on read or write -// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for read transfers -// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for write transfers -// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for read transfers -// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for write transfers -// -// Note 1: If the ETM is not fitted, then ETM trigger is not possible. -// Note 2: Data value is only sampled for accesses that do not fault (MPU or -// bus fault). The PC is sampled irrespective of any faults. The PC is only -// sampled for the first address of a burst. -// Note 3: PC match is not recommended for watchpoints because it stops after -// the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION0_FUNCTION_W 4 -#define CPU_DWT_FUNCTION0_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION0_FUNCTION_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_COMP1 -// -//***************************************************************************** -// Field: [31:0] COMP -// -// Reference value to compare against PC or the data address as given by -// FUNCTION1. -// Comparator 1 can also compare data values. So this register can contain -// reference values for data matching. -#define CPU_DWT_COMP1_COMP_W 32 -#define CPU_DWT_COMP1_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP1_COMP_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_MASK1 -// -//***************************************************************************** -// Field: [3:0] MASK -// -// Mask on data address when matching against COMP1. This is the size of the -// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF -// left bit-shifted by MASK)) == COMP1. However, the actual comparison is -// slightly more complex to enable matching an address wherever it appears on a -// bus. So, if COMP1 is 3, this matches a word access of 0, because 3 would be -// within the word. -#define CPU_DWT_MASK1_MASK_W 4 -#define CPU_DWT_MASK1_MASK_M 0x0000000F -#define CPU_DWT_MASK1_MASK_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_FUNCTION1 -// -//***************************************************************************** -// Field: [24] MATCHED -// -// This bit is set when the comparator matches, and indicates that the -// operation defined by FUNCTION has occurred since this bit was last read. -// This bit is cleared on read. -#define CPU_DWT_FUNCTION1_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION1_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION1_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION1_MATCHED_S 24 - -// Field: [19:16] DATAVADDR1 -// -// Identity of a second linked address comparator for data value matching when -// DATAVMATCH == 1 and LNK1ENA == 1. -#define CPU_DWT_FUNCTION1_DATAVADDR1_W 4 -#define CPU_DWT_FUNCTION1_DATAVADDR1_M 0x000F0000 -#define CPU_DWT_FUNCTION1_DATAVADDR1_S 16 - -// Field: [15:12] DATAVADDR0 -// -// Identity of a linked address comparator for data value matching when -// DATAVMATCH == 1. -#define CPU_DWT_FUNCTION1_DATAVADDR0_W 4 -#define CPU_DWT_FUNCTION1_DATAVADDR0_M 0x0000F000 -#define CPU_DWT_FUNCTION1_DATAVADDR0_S 12 - -// Field: [11:10] DATAVSIZE -// -// Defines the size of the data in the COMP1 register that is to be matched: -// -// 0x0: Byte -// 0x1: Halfword -// 0x2: Word -// 0x3: Unpredictable. -#define CPU_DWT_FUNCTION1_DATAVSIZE_W 2 -#define CPU_DWT_FUNCTION1_DATAVSIZE_M 0x00000C00 -#define CPU_DWT_FUNCTION1_DATAVSIZE_S 10 - -// Field: [9] LNK1ENA -// -// Read only bit-field only supported in comparator 1. -// -// 0: DATAVADDR1 not supported -// 1: DATAVADDR1 supported (enabled) -#define CPU_DWT_FUNCTION1_LNK1ENA 0x00000200 -#define CPU_DWT_FUNCTION1_LNK1ENA_BITN 9 -#define CPU_DWT_FUNCTION1_LNK1ENA_M 0x00000200 -#define CPU_DWT_FUNCTION1_LNK1ENA_S 9 - -// Field: [8] DATAVMATCH -// -// Data match feature: -// -// 0: Perform address comparison -// 1: Perform data value compare. The comparators given by DATAVADDR0 and -// DATAVADDR1 provide the address for the data comparison. The FUNCTION setting -// for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and -// those comparators only provide the address match for the data comparison. -// -// This bit is only available in comparator 1. -#define CPU_DWT_FUNCTION1_DATAVMATCH 0x00000100 -#define CPU_DWT_FUNCTION1_DATAVMATCH_BITN 8 -#define CPU_DWT_FUNCTION1_DATAVMATCH_M 0x00000100 -#define CPU_DWT_FUNCTION1_DATAVMATCH_S 8 - -// Field: [5] EMITRANGE -// -// Emit range field. This bit permits emitting offset when range match occurs. -// PC sampling is not supported when emit range is enabled. -// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION1_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION1_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION1_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION1_EMITRANGE_S 5 - -// Field: [3:0] FUNCTION -// -// Function settings: -// -// 0x0: Disabled -// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit -// address offset through ITM -// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, -// emit data and address offset through ITM on read or write. -// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. -// EMITRANGE = 1, emit address offset and data value through ITM on read or -// write. -// 0x4: Watchpoint on PC match. -// 0x5: Watchpoint on read. -// 0x6: Watchpoint on write. -// 0x7: Watchpoint on read or write. -// 0x8: ETM trigger on PC match -// 0x9: ETM trigger on read -// 0xA: ETM trigger on write -// 0xB: ETM trigger on read or write -// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for read transfers -// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for write transfers -// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for read transfers -// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for write transfers -// -// Note 1: If the ETM is not fitted, then ETM trigger is not possible. -// Note 2: Data value is only sampled for accesses that do not fault (MPU or -// bus fault). The PC is sampled irrespective of any faults. The PC is only -// sampled for the first address of a burst. -// Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and -// DATAVADDR1 if DATAVMATCH is also set. The comparators given by DATAVADDR0 -// and DATAVADDR1 can then only perform address comparator matches for -// comparator 1 data matches. -// Note 4: If the data matching functionality is not included during -// implementation it is not possible to set DATAVADDR0, DATAVADDR1, or -// DATAVMATCH. This means that the data matching functionality is not available -// in the implementation. Test the availability of data matching by writing and -// reading DATAVMATCH. If it is not settable then data matching is unavailable. -// Note 5: PC match is not recommended for watchpoints because it stops after -// the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION1_FUNCTION_W 4 -#define CPU_DWT_FUNCTION1_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION1_FUNCTION_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_COMP2 -// -//***************************************************************************** -// Field: [31:0] COMP -// -// Reference value to compare against PC or the data address as given by -// FUNCTION2. -#define CPU_DWT_COMP2_COMP_W 32 -#define CPU_DWT_COMP2_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP2_COMP_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_MASK2 -// -//***************************************************************************** -// Field: [3:0] MASK -// -// Mask on data address when matching against COMP2. This is the size of the -// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF -// left bit-shifted by MASK)) == COMP2. However, the actual comparison is -// slightly more complex to enable matching an address wherever it appears on a -// bus. So, if COMP2 is 3, this matches a word access of 0, because 3 would be -// within the word. -#define CPU_DWT_MASK2_MASK_W 4 -#define CPU_DWT_MASK2_MASK_M 0x0000000F -#define CPU_DWT_MASK2_MASK_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_FUNCTION2 -// -//***************************************************************************** -// Field: [24] MATCHED -// -// This bit is set when the comparator matches, and indicates that the -// operation defined by FUNCTION has occurred since this bit was last read. -// This bit is cleared on read. -#define CPU_DWT_FUNCTION2_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION2_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION2_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION2_MATCHED_S 24 - -// Field: [5] EMITRANGE -// -// Emit range field. This bit permits emitting offset when range match occurs. -// PC sampling is not supported when emit range is enabled. -// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION2_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION2_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION2_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION2_EMITRANGE_S 5 - -// Field: [3:0] FUNCTION -// -// Function settings. -// -// 0x0: Disabled -// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit -// address offset through ITM -// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, -// emit data and address offset through ITM on read or write. -// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. -// EMITRANGE = 1, emit address offset and data value through ITM on read or -// write. -// 0x4: Watchpoint on PC match. -// 0x5: Watchpoint on read. -// 0x6: Watchpoint on write. -// 0x7: Watchpoint on read or write. -// 0x8: ETM trigger on PC match -// 0x9: ETM trigger on read -// 0xA: ETM trigger on write -// 0xB: ETM trigger on read or write -// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for read transfers -// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for write transfers -// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for read transfers -// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for write transfers -// -// Note 1: If the ETM is not fitted, then ETM trigger is not possible. -// Note 2: Data value is only sampled for accesses that do not fault (MPU or -// bus fault). The PC is sampled irrespective of any faults. The PC is only -// sampled for the first address of a burst. -// Note 3: PC match is not recommended for watchpoints because it stops after -// the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION2_FUNCTION_W 4 -#define CPU_DWT_FUNCTION2_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION2_FUNCTION_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_COMP3 -// -//***************************************************************************** -// Field: [31:0] COMP -// -// Reference value to compare against PC or the data address as given by -// FUNCTION3. -#define CPU_DWT_COMP3_COMP_W 32 -#define CPU_DWT_COMP3_COMP_M 0xFFFFFFFF -#define CPU_DWT_COMP3_COMP_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_MASK3 -// -//***************************************************************************** -// Field: [3:0] MASK -// -// Mask on data address when matching against COMP3. This is the size of the -// ignore mask. That is, DWT matching is performed as:(ADDR ANDed with (0xFFFF -// left bit-shifted by MASK)) == COMP3. However, the actual comparison is -// slightly more complex to enable matching an address wherever it appears on a -// bus. So, if COMP3 is 3, this matches a word access of 0, because 3 would be -// within the word. -#define CPU_DWT_MASK3_MASK_W 4 -#define CPU_DWT_MASK3_MASK_M 0x0000000F -#define CPU_DWT_MASK3_MASK_S 0 - -//***************************************************************************** -// -// Register: CPU_DWT_O_FUNCTION3 -// -//***************************************************************************** -// Field: [24] MATCHED -// -// This bit is set when the comparator matches, and indicates that the -// operation defined by FUNCTION has occurred since this bit was last read. -// This bit is cleared on read. -#define CPU_DWT_FUNCTION3_MATCHED 0x01000000 -#define CPU_DWT_FUNCTION3_MATCHED_BITN 24 -#define CPU_DWT_FUNCTION3_MATCHED_M 0x01000000 -#define CPU_DWT_FUNCTION3_MATCHED_S 24 - -// Field: [5] EMITRANGE -// -// Emit range field. This bit permits emitting offset when range match occurs. -// PC sampling is not supported when emit range is enabled. -// This field only applies for: FUNCTION = 1, 2, 3, 12, 13, 14, and 15. -#define CPU_DWT_FUNCTION3_EMITRANGE 0x00000020 -#define CPU_DWT_FUNCTION3_EMITRANGE_BITN 5 -#define CPU_DWT_FUNCTION3_EMITRANGE_M 0x00000020 -#define CPU_DWT_FUNCTION3_EMITRANGE_S 5 - -// Field: [3:0] FUNCTION -// -// Function settings. -// -// 0x0: Disabled -// 0x1: EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit -// address offset through ITM -// 0x2: EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, -// emit data and address offset through ITM on read or write. -// 0x3: EMITRANGE = 0, sample PC and data value through ITM on read or write. -// EMITRANGE = 1, emit address offset and data value through ITM on read or -// write. -// 0x4: Watchpoint on PC match. -// 0x5: Watchpoint on read. -// 0x6: Watchpoint on write. -// 0x7: Watchpoint on read or write. -// 0x8: ETM trigger on PC match -// 0x9: ETM trigger on read -// 0xA: ETM trigger on write -// 0xB: ETM trigger on read or write -// 0xC: EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for read transfers -// 0xD: EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample -// Daddr (lower 16 bits) for write transfers -// 0xE: EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for read transfers -// 0xF: EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, -// sample Daddr (lower 16 bits) + data for write transfers -// -// Note 1: If the ETM is not fitted, then ETM trigger is not possible. -// Note 2: Data value is only sampled for accesses that do not fault (MPU or -// bus fault). The PC is sampled irrespective of any faults. The PC is only -// sampled for the first address of a burst. -// Note 3: PC match is not recommended for watchpoints because it stops after -// the instruction. It mainly guards and triggers the ETM. -#define CPU_DWT_FUNCTION3_FUNCTION_W 4 -#define CPU_DWT_FUNCTION3_FUNCTION_M 0x0000000F -#define CPU_DWT_FUNCTION3_FUNCTION_S 0 - - -#endif // __CPU_DWT__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h deleted file mode 100644 index efc475c584e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_fpb.h +++ /dev/null @@ -1,443 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_fpb_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_FPB_H__ -#define __HW_CPU_FPB_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_FPB component -// -//***************************************************************************** -// Control -#define CPU_FPB_O_CTRL 0x00000000 - -// Remap -#define CPU_FPB_O_REMAP 0x00000004 - -// Comparator 0 -#define CPU_FPB_O_COMP0 0x00000008 - -// Comparator 1 -#define CPU_FPB_O_COMP1 0x0000000C - -// Comparator 2 -#define CPU_FPB_O_COMP2 0x00000010 - -// Comparator 3 -#define CPU_FPB_O_COMP3 0x00000014 - -// Comparator 4 -#define CPU_FPB_O_COMP4 0x00000018 - -// Comparator 5 -#define CPU_FPB_O_COMP5 0x0000001C - -// Comparator 6 -#define CPU_FPB_O_COMP6 0x00000020 - -// Comparator 7 -#define CPU_FPB_O_COMP7 0x00000024 - -//***************************************************************************** -// -// Register: CPU_FPB_O_CTRL -// -//***************************************************************************** -// Field: [13:12] NUM_CODE2 -// -// Number of full banks of code comparators, sixteen comparators per bank. -// Where less than sixteen code comparators are provided, the bank count is -// zero, and the number present indicated by NUM_CODE1. This read only field -// contains 3'b000 to indicate 0 banks for Cortex-M processor. -#define CPU_FPB_CTRL_NUM_CODE2_W 2 -#define CPU_FPB_CTRL_NUM_CODE2_M 0x00003000 -#define CPU_FPB_CTRL_NUM_CODE2_S 12 - -// Field: [11:8] NUM_LIT -// -// Number of literal slots field. -// -// 0x0: No literal slots -// 0x2: Two literal slots -#define CPU_FPB_CTRL_NUM_LIT_W 4 -#define CPU_FPB_CTRL_NUM_LIT_M 0x00000F00 -#define CPU_FPB_CTRL_NUM_LIT_S 8 - -// Field: [7:4] NUM_CODE1 -// -// Number of code slots field. -// -// 0x0: No code slots -// 0x2: Two code slots -// 0x6: Six code slots -#define CPU_FPB_CTRL_NUM_CODE1_W 4 -#define CPU_FPB_CTRL_NUM_CODE1_M 0x000000F0 -#define CPU_FPB_CTRL_NUM_CODE1_S 4 - -// Field: [1] KEY -// -// Key field. In order to write to this register, this bit-field must be -// written to '1'. This bit always reads 0. -#define CPU_FPB_CTRL_KEY 0x00000002 -#define CPU_FPB_CTRL_KEY_BITN 1 -#define CPU_FPB_CTRL_KEY_M 0x00000002 -#define CPU_FPB_CTRL_KEY_S 1 - -// Field: [0] ENABLE -// -// Flash patch unit enable bit -// -// 0x0: Flash patch unit disabled -// 0x1: Flash patch unit enabled -#define CPU_FPB_CTRL_ENABLE 0x00000001 -#define CPU_FPB_CTRL_ENABLE_BITN 0 -#define CPU_FPB_CTRL_ENABLE_M 0x00000001 -#define CPU_FPB_CTRL_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_REMAP -// -//***************************************************************************** -// Field: [28:5] REMAP -// -// Remap base address field. -#define CPU_FPB_REMAP_REMAP_W 24 -#define CPU_FPB_REMAP_REMAP_M 0x1FFFFFE0 -#define CPU_FPB_REMAP_REMAP_S 5 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP0 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Address -// remapping only takes place for the 0x0 setting. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP0_REPLACE_W 2 -#define CPU_FPB_COMP0_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP0_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP0_COMP_W 27 -#define CPU_FPB_COMP0_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP0_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 0. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 0 disabled -// 0x1: Compare and remap for comparator 0 enabled -#define CPU_FPB_COMP0_ENABLE 0x00000001 -#define CPU_FPB_COMP0_ENABLE_BITN 0 -#define CPU_FPB_COMP0_ENABLE_M 0x00000001 -#define CPU_FPB_COMP0_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP1 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Address -// remapping only takes place for the 0x0 setting. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP1_REPLACE_W 2 -#define CPU_FPB_COMP1_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP1_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP1_COMP_W 27 -#define CPU_FPB_COMP1_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP1_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 1. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 1 disabled -// 0x1: Compare and remap for comparator 1 enabled -#define CPU_FPB_COMP1_ENABLE 0x00000001 -#define CPU_FPB_COMP1_ENABLE_BITN 0 -#define CPU_FPB_COMP1_ENABLE_M 0x00000001 -#define CPU_FPB_COMP1_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP2 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Address -// remapping only takes place for the 0x0 setting. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP2_REPLACE_W 2 -#define CPU_FPB_COMP2_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP2_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP2_COMP_W 27 -#define CPU_FPB_COMP2_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP2_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 2. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 2 disabled -// 0x1: Compare and remap for comparator 2 enabled -#define CPU_FPB_COMP2_ENABLE 0x00000001 -#define CPU_FPB_COMP2_ENABLE_BITN 0 -#define CPU_FPB_COMP2_ENABLE_M 0x00000001 -#define CPU_FPB_COMP2_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP3 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Address -// remapping only takes place for the 0x0 setting. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP3_REPLACE_W 2 -#define CPU_FPB_COMP3_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP3_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP3_COMP_W 27 -#define CPU_FPB_COMP3_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP3_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 3. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 3 disabled -// 0x1: Compare and remap for comparator 3 enabled -#define CPU_FPB_COMP3_ENABLE 0x00000001 -#define CPU_FPB_COMP3_ENABLE_BITN 0 -#define CPU_FPB_COMP3_ENABLE_M 0x00000001 -#define CPU_FPB_COMP3_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP4 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Address -// remapping only takes place for the 0x0 setting. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP4_REPLACE_W 2 -#define CPU_FPB_COMP4_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP4_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP4_COMP_W 27 -#define CPU_FPB_COMP4_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP4_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 4. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 4 disabled -// 0x1: Compare and remap for comparator 4 enabled -#define CPU_FPB_COMP4_ENABLE 0x00000001 -#define CPU_FPB_COMP4_ENABLE_BITN 0 -#define CPU_FPB_COMP4_ENABLE_M 0x00000001 -#define CPU_FPB_COMP4_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP5 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Address -// remapping only takes place for the 0x0 setting. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP5_REPLACE_W 2 -#define CPU_FPB_COMP5_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP5_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP5_COMP_W 27 -#define CPU_FPB_COMP5_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP5_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 5. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 5 disabled -// 0x1: Compare and remap for comparator 5 enabled -#define CPU_FPB_COMP5_ENABLE 0x00000001 -#define CPU_FPB_COMP5_ENABLE_BITN 0 -#define CPU_FPB_COMP5_ENABLE_M 0x00000001 -#define CPU_FPB_COMP5_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP6 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Comparator 6 is -// a literal comparator and the only supported setting is 0x0. Other settings -// will be ignored. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP6_REPLACE_W 2 -#define CPU_FPB_COMP6_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP6_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP6_COMP_W 27 -#define CPU_FPB_COMP6_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP6_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 6. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 6 disabled -// 0x1: Compare and remap for comparator 6 enabled -#define CPU_FPB_COMP6_ENABLE 0x00000001 -#define CPU_FPB_COMP6_ENABLE_BITN 0 -#define CPU_FPB_COMP6_ENABLE_M 0x00000001 -#define CPU_FPB_COMP6_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_FPB_O_COMP7 -// -//***************************************************************************** -// Field: [31:30] REPLACE -// -// This selects what happens when the COMP address is matched. Comparator 7 is -// a literal comparator and the only supported setting is 0x0. Other settings -// will be ignored. -// -// 0x0: Remap to remap address. See REMAP.REMAP -// 0x1: Set BKPT on lower halfword, upper is unaffected -// 0x2: Set BKPT on upper halfword, lower is unaffected -// 0x3: Set BKPT on both lower and upper halfwords. -#define CPU_FPB_COMP7_REPLACE_W 2 -#define CPU_FPB_COMP7_REPLACE_M 0xC0000000 -#define CPU_FPB_COMP7_REPLACE_S 30 - -// Field: [28:2] COMP -// -// Comparison address. -#define CPU_FPB_COMP7_COMP_W 27 -#define CPU_FPB_COMP7_COMP_M 0x1FFFFFFC -#define CPU_FPB_COMP7_COMP_S 2 - -// Field: [0] ENABLE -// -// Compare and remap enable comparator 7. CTRL.ENABLE must also be set to -// enable comparisons. -// -// 0x0: Compare and remap for comparator 7 disabled -// 0x1: Compare and remap for comparator 7 enabled -#define CPU_FPB_COMP7_ENABLE 0x00000001 -#define CPU_FPB_COMP7_ENABLE_BITN 0 -#define CPU_FPB_COMP7_ENABLE_M 0x00000001 -#define CPU_FPB_COMP7_ENABLE_S 0 - - -#endif // __CPU_FPB__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h deleted file mode 100644 index 430c0b0df45..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_itm.h +++ /dev/null @@ -1,1122 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_itm_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_ITM_H__ -#define __HW_CPU_ITM_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_ITM component -// -//***************************************************************************** -// Stimulus Port 0 -#define CPU_ITM_O_STIM0 0x00000000 - -// Stimulus Port 1 -#define CPU_ITM_O_STIM1 0x00000004 - -// Stimulus Port 2 -#define CPU_ITM_O_STIM2 0x00000008 - -// Stimulus Port 3 -#define CPU_ITM_O_STIM3 0x0000000C - -// Stimulus Port 4 -#define CPU_ITM_O_STIM4 0x00000010 - -// Stimulus Port 5 -#define CPU_ITM_O_STIM5 0x00000014 - -// Stimulus Port 6 -#define CPU_ITM_O_STIM6 0x00000018 - -// Stimulus Port 7 -#define CPU_ITM_O_STIM7 0x0000001C - -// Stimulus Port 8 -#define CPU_ITM_O_STIM8 0x00000020 - -// Stimulus Port 9 -#define CPU_ITM_O_STIM9 0x00000024 - -// Stimulus Port 10 -#define CPU_ITM_O_STIM10 0x00000028 - -// Stimulus Port 11 -#define CPU_ITM_O_STIM11 0x0000002C - -// Stimulus Port 12 -#define CPU_ITM_O_STIM12 0x00000030 - -// Stimulus Port 13 -#define CPU_ITM_O_STIM13 0x00000034 - -// Stimulus Port 14 -#define CPU_ITM_O_STIM14 0x00000038 - -// Stimulus Port 15 -#define CPU_ITM_O_STIM15 0x0000003C - -// Stimulus Port 16 -#define CPU_ITM_O_STIM16 0x00000040 - -// Stimulus Port 17 -#define CPU_ITM_O_STIM17 0x00000044 - -// Stimulus Port 18 -#define CPU_ITM_O_STIM18 0x00000048 - -// Stimulus Port 19 -#define CPU_ITM_O_STIM19 0x0000004C - -// Stimulus Port 20 -#define CPU_ITM_O_STIM20 0x00000050 - -// Stimulus Port 21 -#define CPU_ITM_O_STIM21 0x00000054 - -// Stimulus Port 22 -#define CPU_ITM_O_STIM22 0x00000058 - -// Stimulus Port 23 -#define CPU_ITM_O_STIM23 0x0000005C - -// Stimulus Port 24 -#define CPU_ITM_O_STIM24 0x00000060 - -// Stimulus Port 25 -#define CPU_ITM_O_STIM25 0x00000064 - -// Stimulus Port 26 -#define CPU_ITM_O_STIM26 0x00000068 - -// Stimulus Port 27 -#define CPU_ITM_O_STIM27 0x0000006C - -// Stimulus Port 28 -#define CPU_ITM_O_STIM28 0x00000070 - -// Stimulus Port 29 -#define CPU_ITM_O_STIM29 0x00000074 - -// Stimulus Port 30 -#define CPU_ITM_O_STIM30 0x00000078 - -// Stimulus Port 31 -#define CPU_ITM_O_STIM31 0x0000007C - -// Trace Enable -#define CPU_ITM_O_TER 0x00000E00 - -// Trace Privilege -#define CPU_ITM_O_TPR 0x00000E40 - -// Trace Control -#define CPU_ITM_O_TCR 0x00000E80 - -// Lock Access -#define CPU_ITM_O_LAR 0x00000FB0 - -// Lock Status -#define CPU_ITM_O_LSR 0x00000FB4 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM0 -// -//***************************************************************************** -// Field: [31:0] STIM0 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA0 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM0_STIM0_W 32 -#define CPU_ITM_STIM0_STIM0_M 0xFFFFFFFF -#define CPU_ITM_STIM0_STIM0_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM1 -// -//***************************************************************************** -// Field: [31:0] STIM1 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA1 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM1_STIM1_W 32 -#define CPU_ITM_STIM1_STIM1_M 0xFFFFFFFF -#define CPU_ITM_STIM1_STIM1_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM2 -// -//***************************************************************************** -// Field: [31:0] STIM2 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA2 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM2_STIM2_W 32 -#define CPU_ITM_STIM2_STIM2_M 0xFFFFFFFF -#define CPU_ITM_STIM2_STIM2_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM3 -// -//***************************************************************************** -// Field: [31:0] STIM3 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA3 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM3_STIM3_W 32 -#define CPU_ITM_STIM3_STIM3_M 0xFFFFFFFF -#define CPU_ITM_STIM3_STIM3_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM4 -// -//***************************************************************************** -// Field: [31:0] STIM4 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA4 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM4_STIM4_W 32 -#define CPU_ITM_STIM4_STIM4_M 0xFFFFFFFF -#define CPU_ITM_STIM4_STIM4_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM5 -// -//***************************************************************************** -// Field: [31:0] STIM5 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA5 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM5_STIM5_W 32 -#define CPU_ITM_STIM5_STIM5_M 0xFFFFFFFF -#define CPU_ITM_STIM5_STIM5_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM6 -// -//***************************************************************************** -// Field: [31:0] STIM6 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA6 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM6_STIM6_W 32 -#define CPU_ITM_STIM6_STIM6_M 0xFFFFFFFF -#define CPU_ITM_STIM6_STIM6_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM7 -// -//***************************************************************************** -// Field: [31:0] STIM7 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA7 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM7_STIM7_W 32 -#define CPU_ITM_STIM7_STIM7_M 0xFFFFFFFF -#define CPU_ITM_STIM7_STIM7_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM8 -// -//***************************************************************************** -// Field: [31:0] STIM8 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA8 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM8_STIM8_W 32 -#define CPU_ITM_STIM8_STIM8_M 0xFFFFFFFF -#define CPU_ITM_STIM8_STIM8_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM9 -// -//***************************************************************************** -// Field: [31:0] STIM9 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA9 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM9_STIM9_W 32 -#define CPU_ITM_STIM9_STIM9_M 0xFFFFFFFF -#define CPU_ITM_STIM9_STIM9_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM10 -// -//***************************************************************************** -// Field: [31:0] STIM10 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA10 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM10_STIM10_W 32 -#define CPU_ITM_STIM10_STIM10_M 0xFFFFFFFF -#define CPU_ITM_STIM10_STIM10_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM11 -// -//***************************************************************************** -// Field: [31:0] STIM11 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA11 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM11_STIM11_W 32 -#define CPU_ITM_STIM11_STIM11_M 0xFFFFFFFF -#define CPU_ITM_STIM11_STIM11_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM12 -// -//***************************************************************************** -// Field: [31:0] STIM12 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA12 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM12_STIM12_W 32 -#define CPU_ITM_STIM12_STIM12_M 0xFFFFFFFF -#define CPU_ITM_STIM12_STIM12_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM13 -// -//***************************************************************************** -// Field: [31:0] STIM13 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA13 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM13_STIM13_W 32 -#define CPU_ITM_STIM13_STIM13_M 0xFFFFFFFF -#define CPU_ITM_STIM13_STIM13_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM14 -// -//***************************************************************************** -// Field: [31:0] STIM14 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA14 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM14_STIM14_W 32 -#define CPU_ITM_STIM14_STIM14_M 0xFFFFFFFF -#define CPU_ITM_STIM14_STIM14_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM15 -// -//***************************************************************************** -// Field: [31:0] STIM15 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA15 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM15_STIM15_W 32 -#define CPU_ITM_STIM15_STIM15_M 0xFFFFFFFF -#define CPU_ITM_STIM15_STIM15_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM16 -// -//***************************************************************************** -// Field: [31:0] STIM16 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA16 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM16_STIM16_W 32 -#define CPU_ITM_STIM16_STIM16_M 0xFFFFFFFF -#define CPU_ITM_STIM16_STIM16_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM17 -// -//***************************************************************************** -// Field: [31:0] STIM17 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA17 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM17_STIM17_W 32 -#define CPU_ITM_STIM17_STIM17_M 0xFFFFFFFF -#define CPU_ITM_STIM17_STIM17_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM18 -// -//***************************************************************************** -// Field: [31:0] STIM18 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA18 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM18_STIM18_W 32 -#define CPU_ITM_STIM18_STIM18_M 0xFFFFFFFF -#define CPU_ITM_STIM18_STIM18_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM19 -// -//***************************************************************************** -// Field: [31:0] STIM19 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA19 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM19_STIM19_W 32 -#define CPU_ITM_STIM19_STIM19_M 0xFFFFFFFF -#define CPU_ITM_STIM19_STIM19_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM20 -// -//***************************************************************************** -// Field: [31:0] STIM20 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA20 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM20_STIM20_W 32 -#define CPU_ITM_STIM20_STIM20_M 0xFFFFFFFF -#define CPU_ITM_STIM20_STIM20_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM21 -// -//***************************************************************************** -// Field: [31:0] STIM21 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA21 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM21_STIM21_W 32 -#define CPU_ITM_STIM21_STIM21_M 0xFFFFFFFF -#define CPU_ITM_STIM21_STIM21_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM22 -// -//***************************************************************************** -// Field: [31:0] STIM22 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA22 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM22_STIM22_W 32 -#define CPU_ITM_STIM22_STIM22_M 0xFFFFFFFF -#define CPU_ITM_STIM22_STIM22_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM23 -// -//***************************************************************************** -// Field: [31:0] STIM23 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA23 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM23_STIM23_W 32 -#define CPU_ITM_STIM23_STIM23_M 0xFFFFFFFF -#define CPU_ITM_STIM23_STIM23_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM24 -// -//***************************************************************************** -// Field: [31:0] STIM24 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA24 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM24_STIM24_W 32 -#define CPU_ITM_STIM24_STIM24_M 0xFFFFFFFF -#define CPU_ITM_STIM24_STIM24_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM25 -// -//***************************************************************************** -// Field: [31:0] STIM25 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA25 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM25_STIM25_W 32 -#define CPU_ITM_STIM25_STIM25_M 0xFFFFFFFF -#define CPU_ITM_STIM25_STIM25_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM26 -// -//***************************************************************************** -// Field: [31:0] STIM26 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA26 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM26_STIM26_W 32 -#define CPU_ITM_STIM26_STIM26_M 0xFFFFFFFF -#define CPU_ITM_STIM26_STIM26_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM27 -// -//***************************************************************************** -// Field: [31:0] STIM27 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA27 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM27_STIM27_W 32 -#define CPU_ITM_STIM27_STIM27_M 0xFFFFFFFF -#define CPU_ITM_STIM27_STIM27_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM28 -// -//***************************************************************************** -// Field: [31:0] STIM28 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA28 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM28_STIM28_W 32 -#define CPU_ITM_STIM28_STIM28_M 0xFFFFFFFF -#define CPU_ITM_STIM28_STIM28_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM29 -// -//***************************************************************************** -// Field: [31:0] STIM29 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA29 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM29_STIM29_W 32 -#define CPU_ITM_STIM29_STIM29_M 0xFFFFFFFF -#define CPU_ITM_STIM29_STIM29_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM30 -// -//***************************************************************************** -// Field: [31:0] STIM30 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA30 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM30_STIM30_W 32 -#define CPU_ITM_STIM30_STIM30_M 0xFFFFFFFF -#define CPU_ITM_STIM30_STIM30_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_STIM31 -// -//***************************************************************************** -// Field: [31:0] STIM31 -// -// A write to this location causes data to be written into the FIFO if -// TER.STIMENA31 is set. Reading from the stimulus port returns the FIFO status -// in bit [0]: 0 = full, 1 = not full. The polled FIFO interface does not -// provide an atomic read-modify-write, so it's users responsibility to ensure -// exclusive read-modify-write if this ITM port is used concurrently by -// interrupts or other threads. -#define CPU_ITM_STIM31_STIM31_W 32 -#define CPU_ITM_STIM31_STIM31_M 0xFFFFFFFF -#define CPU_ITM_STIM31_STIM31_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_TER -// -//***************************************************************************** -// Field: [31] STIMENA31 -// -// Bit mask to enable tracing on ITM stimulus port 31. -#define CPU_ITM_TER_STIMENA31 0x80000000 -#define CPU_ITM_TER_STIMENA31_BITN 31 -#define CPU_ITM_TER_STIMENA31_M 0x80000000 -#define CPU_ITM_TER_STIMENA31_S 31 - -// Field: [30] STIMENA30 -// -// Bit mask to enable tracing on ITM stimulus port 30. -#define CPU_ITM_TER_STIMENA30 0x40000000 -#define CPU_ITM_TER_STIMENA30_BITN 30 -#define CPU_ITM_TER_STIMENA30_M 0x40000000 -#define CPU_ITM_TER_STIMENA30_S 30 - -// Field: [29] STIMENA29 -// -// Bit mask to enable tracing on ITM stimulus port 29. -#define CPU_ITM_TER_STIMENA29 0x20000000 -#define CPU_ITM_TER_STIMENA29_BITN 29 -#define CPU_ITM_TER_STIMENA29_M 0x20000000 -#define CPU_ITM_TER_STIMENA29_S 29 - -// Field: [28] STIMENA28 -// -// Bit mask to enable tracing on ITM stimulus port 28. -#define CPU_ITM_TER_STIMENA28 0x10000000 -#define CPU_ITM_TER_STIMENA28_BITN 28 -#define CPU_ITM_TER_STIMENA28_M 0x10000000 -#define CPU_ITM_TER_STIMENA28_S 28 - -// Field: [27] STIMENA27 -// -// Bit mask to enable tracing on ITM stimulus port 27. -#define CPU_ITM_TER_STIMENA27 0x08000000 -#define CPU_ITM_TER_STIMENA27_BITN 27 -#define CPU_ITM_TER_STIMENA27_M 0x08000000 -#define CPU_ITM_TER_STIMENA27_S 27 - -// Field: [26] STIMENA26 -// -// Bit mask to enable tracing on ITM stimulus port 26. -#define CPU_ITM_TER_STIMENA26 0x04000000 -#define CPU_ITM_TER_STIMENA26_BITN 26 -#define CPU_ITM_TER_STIMENA26_M 0x04000000 -#define CPU_ITM_TER_STIMENA26_S 26 - -// Field: [25] STIMENA25 -// -// Bit mask to enable tracing on ITM stimulus port 25. -#define CPU_ITM_TER_STIMENA25 0x02000000 -#define CPU_ITM_TER_STIMENA25_BITN 25 -#define CPU_ITM_TER_STIMENA25_M 0x02000000 -#define CPU_ITM_TER_STIMENA25_S 25 - -// Field: [24] STIMENA24 -// -// Bit mask to enable tracing on ITM stimulus port 24. -#define CPU_ITM_TER_STIMENA24 0x01000000 -#define CPU_ITM_TER_STIMENA24_BITN 24 -#define CPU_ITM_TER_STIMENA24_M 0x01000000 -#define CPU_ITM_TER_STIMENA24_S 24 - -// Field: [23] STIMENA23 -// -// Bit mask to enable tracing on ITM stimulus port 23. -#define CPU_ITM_TER_STIMENA23 0x00800000 -#define CPU_ITM_TER_STIMENA23_BITN 23 -#define CPU_ITM_TER_STIMENA23_M 0x00800000 -#define CPU_ITM_TER_STIMENA23_S 23 - -// Field: [22] STIMENA22 -// -// Bit mask to enable tracing on ITM stimulus port 22. -#define CPU_ITM_TER_STIMENA22 0x00400000 -#define CPU_ITM_TER_STIMENA22_BITN 22 -#define CPU_ITM_TER_STIMENA22_M 0x00400000 -#define CPU_ITM_TER_STIMENA22_S 22 - -// Field: [21] STIMENA21 -// -// Bit mask to enable tracing on ITM stimulus port 21. -#define CPU_ITM_TER_STIMENA21 0x00200000 -#define CPU_ITM_TER_STIMENA21_BITN 21 -#define CPU_ITM_TER_STIMENA21_M 0x00200000 -#define CPU_ITM_TER_STIMENA21_S 21 - -// Field: [20] STIMENA20 -// -// Bit mask to enable tracing on ITM stimulus port 20. -#define CPU_ITM_TER_STIMENA20 0x00100000 -#define CPU_ITM_TER_STIMENA20_BITN 20 -#define CPU_ITM_TER_STIMENA20_M 0x00100000 -#define CPU_ITM_TER_STIMENA20_S 20 - -// Field: [19] STIMENA19 -// -// Bit mask to enable tracing on ITM stimulus port 19. -#define CPU_ITM_TER_STIMENA19 0x00080000 -#define CPU_ITM_TER_STIMENA19_BITN 19 -#define CPU_ITM_TER_STIMENA19_M 0x00080000 -#define CPU_ITM_TER_STIMENA19_S 19 - -// Field: [18] STIMENA18 -// -// Bit mask to enable tracing on ITM stimulus port 18. -#define CPU_ITM_TER_STIMENA18 0x00040000 -#define CPU_ITM_TER_STIMENA18_BITN 18 -#define CPU_ITM_TER_STIMENA18_M 0x00040000 -#define CPU_ITM_TER_STIMENA18_S 18 - -// Field: [17] STIMENA17 -// -// Bit mask to enable tracing on ITM stimulus port 17. -#define CPU_ITM_TER_STIMENA17 0x00020000 -#define CPU_ITM_TER_STIMENA17_BITN 17 -#define CPU_ITM_TER_STIMENA17_M 0x00020000 -#define CPU_ITM_TER_STIMENA17_S 17 - -// Field: [16] STIMENA16 -// -// Bit mask to enable tracing on ITM stimulus port 16. -#define CPU_ITM_TER_STIMENA16 0x00010000 -#define CPU_ITM_TER_STIMENA16_BITN 16 -#define CPU_ITM_TER_STIMENA16_M 0x00010000 -#define CPU_ITM_TER_STIMENA16_S 16 - -// Field: [15] STIMENA15 -// -// Bit mask to enable tracing on ITM stimulus port 15. -#define CPU_ITM_TER_STIMENA15 0x00008000 -#define CPU_ITM_TER_STIMENA15_BITN 15 -#define CPU_ITM_TER_STIMENA15_M 0x00008000 -#define CPU_ITM_TER_STIMENA15_S 15 - -// Field: [14] STIMENA14 -// -// Bit mask to enable tracing on ITM stimulus port 14. -#define CPU_ITM_TER_STIMENA14 0x00004000 -#define CPU_ITM_TER_STIMENA14_BITN 14 -#define CPU_ITM_TER_STIMENA14_M 0x00004000 -#define CPU_ITM_TER_STIMENA14_S 14 - -// Field: [13] STIMENA13 -// -// Bit mask to enable tracing on ITM stimulus port 13. -#define CPU_ITM_TER_STIMENA13 0x00002000 -#define CPU_ITM_TER_STIMENA13_BITN 13 -#define CPU_ITM_TER_STIMENA13_M 0x00002000 -#define CPU_ITM_TER_STIMENA13_S 13 - -// Field: [12] STIMENA12 -// -// Bit mask to enable tracing on ITM stimulus port 12. -#define CPU_ITM_TER_STIMENA12 0x00001000 -#define CPU_ITM_TER_STIMENA12_BITN 12 -#define CPU_ITM_TER_STIMENA12_M 0x00001000 -#define CPU_ITM_TER_STIMENA12_S 12 - -// Field: [11] STIMENA11 -// -// Bit mask to enable tracing on ITM stimulus port 11. -#define CPU_ITM_TER_STIMENA11 0x00000800 -#define CPU_ITM_TER_STIMENA11_BITN 11 -#define CPU_ITM_TER_STIMENA11_M 0x00000800 -#define CPU_ITM_TER_STIMENA11_S 11 - -// Field: [10] STIMENA10 -// -// Bit mask to enable tracing on ITM stimulus port 10. -#define CPU_ITM_TER_STIMENA10 0x00000400 -#define CPU_ITM_TER_STIMENA10_BITN 10 -#define CPU_ITM_TER_STIMENA10_M 0x00000400 -#define CPU_ITM_TER_STIMENA10_S 10 - -// Field: [9] STIMENA9 -// -// Bit mask to enable tracing on ITM stimulus port 9. -#define CPU_ITM_TER_STIMENA9 0x00000200 -#define CPU_ITM_TER_STIMENA9_BITN 9 -#define CPU_ITM_TER_STIMENA9_M 0x00000200 -#define CPU_ITM_TER_STIMENA9_S 9 - -// Field: [8] STIMENA8 -// -// Bit mask to enable tracing on ITM stimulus port 8. -#define CPU_ITM_TER_STIMENA8 0x00000100 -#define CPU_ITM_TER_STIMENA8_BITN 8 -#define CPU_ITM_TER_STIMENA8_M 0x00000100 -#define CPU_ITM_TER_STIMENA8_S 8 - -// Field: [7] STIMENA7 -// -// Bit mask to enable tracing on ITM stimulus port 7. -#define CPU_ITM_TER_STIMENA7 0x00000080 -#define CPU_ITM_TER_STIMENA7_BITN 7 -#define CPU_ITM_TER_STIMENA7_M 0x00000080 -#define CPU_ITM_TER_STIMENA7_S 7 - -// Field: [6] STIMENA6 -// -// Bit mask to enable tracing on ITM stimulus port 6. -#define CPU_ITM_TER_STIMENA6 0x00000040 -#define CPU_ITM_TER_STIMENA6_BITN 6 -#define CPU_ITM_TER_STIMENA6_M 0x00000040 -#define CPU_ITM_TER_STIMENA6_S 6 - -// Field: [5] STIMENA5 -// -// Bit mask to enable tracing on ITM stimulus port 5. -#define CPU_ITM_TER_STIMENA5 0x00000020 -#define CPU_ITM_TER_STIMENA5_BITN 5 -#define CPU_ITM_TER_STIMENA5_M 0x00000020 -#define CPU_ITM_TER_STIMENA5_S 5 - -// Field: [4] STIMENA4 -// -// Bit mask to enable tracing on ITM stimulus port 4. -#define CPU_ITM_TER_STIMENA4 0x00000010 -#define CPU_ITM_TER_STIMENA4_BITN 4 -#define CPU_ITM_TER_STIMENA4_M 0x00000010 -#define CPU_ITM_TER_STIMENA4_S 4 - -// Field: [3] STIMENA3 -// -// Bit mask to enable tracing on ITM stimulus port 3. -#define CPU_ITM_TER_STIMENA3 0x00000008 -#define CPU_ITM_TER_STIMENA3_BITN 3 -#define CPU_ITM_TER_STIMENA3_M 0x00000008 -#define CPU_ITM_TER_STIMENA3_S 3 - -// Field: [2] STIMENA2 -// -// Bit mask to enable tracing on ITM stimulus port 2. -#define CPU_ITM_TER_STIMENA2 0x00000004 -#define CPU_ITM_TER_STIMENA2_BITN 2 -#define CPU_ITM_TER_STIMENA2_M 0x00000004 -#define CPU_ITM_TER_STIMENA2_S 2 - -// Field: [1] STIMENA1 -// -// Bit mask to enable tracing on ITM stimulus port 1. -#define CPU_ITM_TER_STIMENA1 0x00000002 -#define CPU_ITM_TER_STIMENA1_BITN 1 -#define CPU_ITM_TER_STIMENA1_M 0x00000002 -#define CPU_ITM_TER_STIMENA1_S 1 - -// Field: [0] STIMENA0 -// -// Bit mask to enable tracing on ITM stimulus port 0. -#define CPU_ITM_TER_STIMENA0 0x00000001 -#define CPU_ITM_TER_STIMENA0_BITN 0 -#define CPU_ITM_TER_STIMENA0_M 0x00000001 -#define CPU_ITM_TER_STIMENA0_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_TPR -// -//***************************************************************************** -// Field: [3:0] PRIVMASK -// -// Bit mask to enable unprivileged (User) access to ITM stimulus ports: -// -// Bit [0] enables stimulus ports 0, 1, ..., and 7. -// Bit [1] enables stimulus ports 8, 9, ..., and 15. -// Bit [2] enables stimulus ports 16, 17, ..., and 23. -// Bit [3] enables stimulus ports 24, 25, ..., and 31. -// -// 0: User access allowed to stimulus ports -// 1: Privileged access only to stimulus ports -#define CPU_ITM_TPR_PRIVMASK_W 4 -#define CPU_ITM_TPR_PRIVMASK_M 0x0000000F -#define CPU_ITM_TPR_PRIVMASK_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_TCR -// -//***************************************************************************** -// Field: [23] BUSY -// -// Set when ITM events present and being drained. -#define CPU_ITM_TCR_BUSY 0x00800000 -#define CPU_ITM_TCR_BUSY_BITN 23 -#define CPU_ITM_TCR_BUSY_M 0x00800000 -#define CPU_ITM_TCR_BUSY_S 23 - -// Field: [22:16] ATBID -// -// Trace Bus ID for CoreSight system. Optional identifier for multi-source -// trace stream formatting. If multi-source trace is in use, this field must be -// written with a non-zero value. -#define CPU_ITM_TCR_ATBID_W 7 -#define CPU_ITM_TCR_ATBID_M 0x007F0000 -#define CPU_ITM_TCR_ATBID_S 16 - -// Field: [9:8] TSPRESCALE -// -// Timestamp prescaler -// ENUMs: -// DIV64 Divide by 64 -// DIV16 Divide by 16 -// DIV4 Divide by 4 -// NOPRESCALING No prescaling -#define CPU_ITM_TCR_TSPRESCALE_W 2 -#define CPU_ITM_TCR_TSPRESCALE_M 0x00000300 -#define CPU_ITM_TCR_TSPRESCALE_S 8 -#define CPU_ITM_TCR_TSPRESCALE_DIV64 0x00000300 -#define CPU_ITM_TCR_TSPRESCALE_DIV16 0x00000200 -#define CPU_ITM_TCR_TSPRESCALE_DIV4 0x00000100 -#define CPU_ITM_TCR_TSPRESCALE_NOPRESCALING 0x00000000 - -// Field: [4] SWOENA -// -// Enables asynchronous clocking of the timestamp counter (when TSENA = 1). If -// TSENA = 0, writing this bit to 1 does not enable asynchronous clocking of -// the timestamp counter. -// -// 0x0: Mode disabled. Timestamp counter uses system clock from the core and -// counts continuously. -// 0x1: Timestamp counter uses lineout (data related) clock from TPIU -// interface. The timestamp counter is held in reset while the output line is -// idle. -#define CPU_ITM_TCR_SWOENA 0x00000010 -#define CPU_ITM_TCR_SWOENA_BITN 4 -#define CPU_ITM_TCR_SWOENA_M 0x00000010 -#define CPU_ITM_TCR_SWOENA_S 4 - -// Field: [3] DWTENA -// -// Enables the DWT stimulus (hardware event packet emission to the TPIU from -// the DWT) -#define CPU_ITM_TCR_DWTENA 0x00000008 -#define CPU_ITM_TCR_DWTENA_BITN 3 -#define CPU_ITM_TCR_DWTENA_M 0x00000008 -#define CPU_ITM_TCR_DWTENA_S 3 - -// Field: [2] SYNCENA -// -// Enables synchronization packet transmission for a synchronous TPIU. -// CPU_DWT:CTRL.SYNCTAP must be configured for the correct synchronization -// speed. -#define CPU_ITM_TCR_SYNCENA 0x00000004 -#define CPU_ITM_TCR_SYNCENA_BITN 2 -#define CPU_ITM_TCR_SYNCENA_M 0x00000004 -#define CPU_ITM_TCR_SYNCENA_S 2 - -// Field: [1] TSENA -// -// Enables differential timestamps. Differential timestamps are emitted when a -// packet is written to the FIFO with a non-zero timestamp counter, and when -// the timestamp counter overflows. Timestamps are emitted during idle times -// after a fixed number of two million cycles. This provides a time reference -// for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps -// are triggered by activity on the internal trace bus only. In this case there -// is no regular timestamp output when the ITM is idle. -#define CPU_ITM_TCR_TSENA 0x00000002 -#define CPU_ITM_TCR_TSENA_BITN 1 -#define CPU_ITM_TCR_TSENA_M 0x00000002 -#define CPU_ITM_TCR_TSENA_S 1 - -// Field: [0] ITMENA -// -// Enables ITM. This is the master enable, and must be set before ITM Stimulus -// and Trace Enable registers can be written. -#define CPU_ITM_TCR_ITMENA 0x00000001 -#define CPU_ITM_TCR_ITMENA_BITN 0 -#define CPU_ITM_TCR_ITMENA_M 0x00000001 -#define CPU_ITM_TCR_ITMENA_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_LAR -// -//***************************************************************************** -// Field: [31:0] LOCK_ACCESS -// -// A privileged write of 0xC5ACCE55 enables more write access to Control -// Registers TER, TPR and TCR. An invalid write removes write access. -#define CPU_ITM_LAR_LOCK_ACCESS_W 32 -#define CPU_ITM_LAR_LOCK_ACCESS_M 0xFFFFFFFF -#define CPU_ITM_LAR_LOCK_ACCESS_S 0 - -//***************************************************************************** -// -// Register: CPU_ITM_O_LSR -// -//***************************************************************************** -// Field: [2] BYTEACC -// -// Reads 0 which means 8-bit lock access is not be implemented. -#define CPU_ITM_LSR_BYTEACC 0x00000004 -#define CPU_ITM_LSR_BYTEACC_BITN 2 -#define CPU_ITM_LSR_BYTEACC_M 0x00000004 -#define CPU_ITM_LSR_BYTEACC_S 2 - -// Field: [1] ACCESS -// -// Write access to component is blocked. All writes are ignored, reads are -// permitted. -#define CPU_ITM_LSR_ACCESS 0x00000002 -#define CPU_ITM_LSR_ACCESS_BITN 1 -#define CPU_ITM_LSR_ACCESS_M 0x00000002 -#define CPU_ITM_LSR_ACCESS_S 1 - -// Field: [0] PRESENT -// -// Indicates that a lock mechanism exists for this component. -#define CPU_ITM_LSR_PRESENT 0x00000001 -#define CPU_ITM_LSR_PRESENT_BITN 0 -#define CPU_ITM_LSR_PRESENT_M 0x00000001 -#define CPU_ITM_LSR_PRESENT_S 0 - - -#endif // __CPU_ITM__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h deleted file mode 100644 index e9e9e06062b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_rom_table.h +++ /dev/null @@ -1,220 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_rom_table_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_ROM_TABLE_H__ -#define __HW_CPU_ROM_TABLE_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_ROM_TABLE component -// -//***************************************************************************** -// System Control Space Component -#define CPU_ROM_TABLE_O_SCS 0x00000000 - -// Data Watchpoint and Trace Component -#define CPU_ROM_TABLE_O_DWT 0x00000004 - -// Flash Patch and Breakpoint Component -#define CPU_ROM_TABLE_O_FPB 0x00000008 - -// Instrumentation Trace Component -#define CPU_ROM_TABLE_O_ITM 0x0000000C - -// Trace Port Interface Component -#define CPU_ROM_TABLE_O_TPIU 0x00000010 - -// Enhanced Trace Component -#define CPU_ROM_TABLE_O_ETM 0x00000014 - -// End Marker -#define CPU_ROM_TABLE_O_END 0x00000018 - -// System Memory Map Access for DAP -#define CPU_ROM_TABLE_O_SYSTEM_ACCESS 0x00000FCC - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_SCS -// -//***************************************************************************** -// Field: [31:0] SCS -// -// Points to the SCS at 0xE000E000. -// (SCS + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE000E000. -#define CPU_ROM_TABLE_SCS_SCS_W 32 -#define CPU_ROM_TABLE_SCS_SCS_M 0xFFFFFFFF -#define CPU_ROM_TABLE_SCS_SCS_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_DWT -// -//***************************************************************************** -// Field: [31:1] DWT -// -// Points to the Data Watchpoint and Trace block at 0xE0001000. -// (2*DWT + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0001000. -#define CPU_ROM_TABLE_DWT_DWT_W 31 -#define CPU_ROM_TABLE_DWT_DWT_M 0xFFFFFFFE -#define CPU_ROM_TABLE_DWT_DWT_S 1 - -// Field: [0] DWT_PRESENT -// -// 0: DWT is not present -// 1: DWT is present. -#define CPU_ROM_TABLE_DWT_DWT_PRESENT 0x00000001 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_BITN 0 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_DWT_DWT_PRESENT_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_FPB -// -//***************************************************************************** -// Field: [31:1] FPB -// -// Points to the Flash Patch and Breakpoint block at 0xE0002000. -// (2*FPB + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0002000. -#define CPU_ROM_TABLE_FPB_FPB_W 31 -#define CPU_ROM_TABLE_FPB_FPB_M 0xFFFFFFFE -#define CPU_ROM_TABLE_FPB_FPB_S 1 - -// Field: [0] FPB_PRESENT -// -// 0: FPB is not present -// 1: FPB is present. -#define CPU_ROM_TABLE_FPB_FPB_PRESENT 0x00000001 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_BITN 0 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_FPB_FPB_PRESENT_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_ITM -// -//***************************************************************************** -// Field: [31:1] ITM -// -// Points to the Instrumentation Trace block at 0xE0000000. -// (2*ITM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0000000. -#define CPU_ROM_TABLE_ITM_ITM_W 31 -#define CPU_ROM_TABLE_ITM_ITM_M 0xFFFFFFFE -#define CPU_ROM_TABLE_ITM_ITM_S 1 - -// Field: [0] ITM_PRESENT -// -// 0: ITM is not present -// 1: ITM is present. -#define CPU_ROM_TABLE_ITM_ITM_PRESENT 0x00000001 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_BITN 0 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_ITM_ITM_PRESENT_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_TPIU -// -//***************************************************************************** -// Field: [31:1] TPIU -// -// Points to the TPIU. TPIU is at 0xE0040000. -// (2*TPIU + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0040000. -#define CPU_ROM_TABLE_TPIU_TPIU_W 31 -#define CPU_ROM_TABLE_TPIU_TPIU_M 0xFFFFFFFE -#define CPU_ROM_TABLE_TPIU_TPIU_S 1 - -// Field: [0] TPIU_PRESENT -// -// 0: TPIU is not present -// 1: TPIU is present. -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT 0x00000001 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_BITN 0 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_TPIU_TPIU_PRESENT_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_ETM -// -//***************************************************************************** -// Field: [31:1] ETM -// -// Points to the ETM. ETM is at 0xE0041000. -// (2*ETM + Base address for ROM_TABLE) & 0x0FFFFFFF0 = 0xE0041000. -#define CPU_ROM_TABLE_ETM_ETM_W 31 -#define CPU_ROM_TABLE_ETM_ETM_M 0xFFFFFFFE -#define CPU_ROM_TABLE_ETM_ETM_S 1 - -// Field: [0] ETM_PRESENT -// -// 0: ETM is not present -// 1: ETM is present. -#define CPU_ROM_TABLE_ETM_ETM_PRESENT 0x00000001 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_BITN 0 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_M 0x00000001 -#define CPU_ROM_TABLE_ETM_ETM_PRESENT_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_END -// -//***************************************************************************** -// Field: [31:0] END -// -// End of the ROM table -#define CPU_ROM_TABLE_END_END_W 32 -#define CPU_ROM_TABLE_END_END_M 0xFFFFFFFF -#define CPU_ROM_TABLE_END_END_S 0 - -//***************************************************************************** -// -// Register: CPU_ROM_TABLE_O_SYSTEM_ACCESS -// -//***************************************************************************** -// Field: [0] SYSTEM_ACCESS -// -// 1: The system memory map is accessible using the DAP -// 0: Only debug resources are accessible using the DAP -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS 0x00000001 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_BITN 0 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_M 0x00000001 -#define CPU_ROM_TABLE_SYSTEM_ACCESS_SYSTEM_ACCESS_S 0 - - -#endif // __CPU_ROM_TABLE__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h deleted file mode 100644 index 2906f443203..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_scs.h +++ /dev/null @@ -1,4789 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_scs_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_SCS_H__ -#define __HW_CPU_SCS_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_SCS component -// -//***************************************************************************** -// Interrupt Control Type -#define CPU_SCS_O_ICTR 0x00000004 - -// Auxiliary Control -#define CPU_SCS_O_ACTLR 0x00000008 - -// SysTick Control and Status -#define CPU_SCS_O_STCSR 0x00000010 - -// SysTick Reload Value -#define CPU_SCS_O_STRVR 0x00000014 - -// SysTick Current Value -#define CPU_SCS_O_STCVR 0x00000018 - -// SysTick Calibration Value -#define CPU_SCS_O_STCR 0x0000001C - -// Irq 0 to 31 Set Enable -#define CPU_SCS_O_NVIC_ISER0 0x00000100 - -// Irq 32 to 63 Set Enable -#define CPU_SCS_O_NVIC_ISER1 0x00000104 - -// Irq 0 to 31 Clear Enable -#define CPU_SCS_O_NVIC_ICER0 0x00000180 - -// Irq 32 to 63 Clear Enable -#define CPU_SCS_O_NVIC_ICER1 0x00000184 - -// Irq 0 to 31 Set Pending -#define CPU_SCS_O_NVIC_ISPR0 0x00000200 - -// Irq 32 to 63 Set Pending -#define CPU_SCS_O_NVIC_ISPR1 0x00000204 - -// Irq 0 to 31 Clear Pending -#define CPU_SCS_O_NVIC_ICPR0 0x00000280 - -// Irq 32 to 63 Clear Pending -#define CPU_SCS_O_NVIC_ICPR1 0x00000284 - -// Irq 0 to 31 Active Bit -#define CPU_SCS_O_NVIC_IABR0 0x00000300 - -// Irq 32 to 63 Active Bit -#define CPU_SCS_O_NVIC_IABR1 0x00000304 - -// Irq 0 to 3 Priority -#define CPU_SCS_O_NVIC_IPR0 0x00000400 - -// Irq 4 to 7 Priority -#define CPU_SCS_O_NVIC_IPR1 0x00000404 - -// Irq 8 to 11 Priority -#define CPU_SCS_O_NVIC_IPR2 0x00000408 - -// Irq 12 to 15 Priority -#define CPU_SCS_O_NVIC_IPR3 0x0000040C - -// Irq 16 to 19 Priority -#define CPU_SCS_O_NVIC_IPR4 0x00000410 - -// Irq 20 to 23 Priority -#define CPU_SCS_O_NVIC_IPR5 0x00000414 - -// Irq 24 to 27 Priority -#define CPU_SCS_O_NVIC_IPR6 0x00000418 - -// Irq 28 to 31 Priority -#define CPU_SCS_O_NVIC_IPR7 0x0000041C - -// Irq 32 to 35 Priority -#define CPU_SCS_O_NVIC_IPR8 0x00000420 - -// Irq 32 to 35 Priority -#define CPU_SCS_O_NVIC_IPR9 0x00000424 - -// CPUID Base -#define CPU_SCS_O_CPUID 0x00000D00 - -// Interrupt Control State -#define CPU_SCS_O_ICSR 0x00000D04 - -// Vector Table Offset -#define CPU_SCS_O_VTOR 0x00000D08 - -// Application Interrupt/Reset Control -#define CPU_SCS_O_AIRCR 0x00000D0C - -// System Control -#define CPU_SCS_O_SCR 0x00000D10 - -// Configuration Control -#define CPU_SCS_O_CCR 0x00000D14 - -// System Handlers 4-7 Priority -#define CPU_SCS_O_SHPR1 0x00000D18 - -// System Handlers 8-11 Priority -#define CPU_SCS_O_SHPR2 0x00000D1C - -// System Handlers 12-15 Priority -#define CPU_SCS_O_SHPR3 0x00000D20 - -// System Handler Control and State -#define CPU_SCS_O_SHCSR 0x00000D24 - -// Configurable Fault Status -#define CPU_SCS_O_CFSR 0x00000D28 - -// Hard Fault Status -#define CPU_SCS_O_HFSR 0x00000D2C - -// Debug Fault Status -#define CPU_SCS_O_DFSR 0x00000D30 - -// Mem Manage Fault Address -#define CPU_SCS_O_MMFAR 0x00000D34 - -// Bus Fault Address -#define CPU_SCS_O_BFAR 0x00000D38 - -// Auxiliary Fault Status -#define CPU_SCS_O_AFSR 0x00000D3C - -// Processor Feature 0 -#define CPU_SCS_O_ID_PFR0 0x00000D40 - -// Processor Feature 1 -#define CPU_SCS_O_ID_PFR1 0x00000D44 - -// Debug Feature 0 -#define CPU_SCS_O_ID_DFR0 0x00000D48 - -// Auxiliary Feature 0 -#define CPU_SCS_O_ID_AFR0 0x00000D4C - -// Memory Model Feature 0 -#define CPU_SCS_O_ID_MMFR0 0x00000D50 - -// Memory Model Feature 1 -#define CPU_SCS_O_ID_MMFR1 0x00000D54 - -// Memory Model Feature 2 -#define CPU_SCS_O_ID_MMFR2 0x00000D58 - -// Memory Model Feature 3 -#define CPU_SCS_O_ID_MMFR3 0x00000D5C - -// ISA Feature 0 -#define CPU_SCS_O_ID_ISAR0 0x00000D60 - -// ISA Feature 1 -#define CPU_SCS_O_ID_ISAR1 0x00000D64 - -// ISA Feature 2 -#define CPU_SCS_O_ID_ISAR2 0x00000D68 - -// ISA Feature 3 -#define CPU_SCS_O_ID_ISAR3 0x00000D6C - -// ISA Feature 4 -#define CPU_SCS_O_ID_ISAR4 0x00000D70 - -// Coprocessor Access Control -#define CPU_SCS_O_CPACR 0x00000D88 - -// MPU Type -#define CPU_SCS_O_MPU_TYPE 0x00000D90 - -// MPU Control -#define CPU_SCS_O_MPU_CTRL 0x00000D94 - -// MPU Region Number -#define CPU_SCS_O_MPU_RNR 0x00000D98 - -// MPU Region Base Address -#define CPU_SCS_O_MPU_RBAR 0x00000D9C - -// MPU Region Attribute and Size -#define CPU_SCS_O_MPU_RASR 0x00000DA0 - -// MPU Alias 1 Region Base Address -#define CPU_SCS_O_MPU_RBAR_A1 0x00000DA4 - -// MPU Alias 1 Region Attribute and Size -#define CPU_SCS_O_MPU_RASR_A1 0x00000DA8 - -// MPU Alias 2 Region Base Address -#define CPU_SCS_O_MPU_RBAR_A2 0x00000DAC - -// MPU Alias 2 Region Attribute and Size -#define CPU_SCS_O_MPU_RASR_A2 0x00000DB0 - -// MPU Alias 3 Region Base Address -#define CPU_SCS_O_MPU_RBAR_A3 0x00000DB4 - -// MPU Alias 3 Region Attribute and Size -#define CPU_SCS_O_MPU_RASR_A3 0x00000DB8 - -// Debug Halting Control and Status -#define CPU_SCS_O_DHCSR 0x00000DF0 - -// Deubg Core Register Selector -#define CPU_SCS_O_DCRSR 0x00000DF4 - -// Debug Core Register Data -#define CPU_SCS_O_DCRDR 0x00000DF8 - -// Debug Exception and Monitor Control -#define CPU_SCS_O_DEMCR 0x00000DFC - -// Software Trigger Interrupt -#define CPU_SCS_O_STIR 0x00000F00 - -// Floating Point Context Control -#define CPU_SCS_O_FPCCR 0x00000F34 - -// Floating-Point Context Address -#define CPU_SCS_O_FPCAR 0x00000F38 - -// Floating Point Default Status Control -#define CPU_SCS_O_FPDSCR 0x00000F3C - -// Media and FP Feature 0 -#define CPU_SCS_O_MVFR0 0x00000F40 - -// Media and FP Feature 1 -#define CPU_SCS_O_MVFR1 0x00000F44 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ICTR -// -//***************************************************************************** -// Field: [2:0] INTLINESNUM -// -// Total number of interrupt lines in groups of 32. -// -// 0: 0...32 -// 1: 33...64 -// 2: 65...96 -// 3: 97...128 -// 4: 129...160 -// 5: 161...192 -// 6: 193...224 -// 7: 225...256 -#define CPU_SCS_ICTR_INTLINESNUM_W 3 -#define CPU_SCS_ICTR_INTLINESNUM_M 0x00000007 -#define CPU_SCS_ICTR_INTLINESNUM_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ACTLR -// -//***************************************************************************** -// Field: [9] DISOOFP -// -// Disables floating point instructions completing out of order with respect to -// integer instructions. -#define CPU_SCS_ACTLR_DISOOFP 0x00000200 -#define CPU_SCS_ACTLR_DISOOFP_BITN 9 -#define CPU_SCS_ACTLR_DISOOFP_M 0x00000200 -#define CPU_SCS_ACTLR_DISOOFP_S 9 - -// Field: [8] DISFPCA -// -// Disable automatic update of CONTROL.FPCA -#define CPU_SCS_ACTLR_DISFPCA 0x00000100 -#define CPU_SCS_ACTLR_DISFPCA_BITN 8 -#define CPU_SCS_ACTLR_DISFPCA_M 0x00000100 -#define CPU_SCS_ACTLR_DISFPCA_S 8 - -// Field: [2] DISFOLD -// -// Disables folding of IT instruction. -#define CPU_SCS_ACTLR_DISFOLD 0x00000004 -#define CPU_SCS_ACTLR_DISFOLD_BITN 2 -#define CPU_SCS_ACTLR_DISFOLD_M 0x00000004 -#define CPU_SCS_ACTLR_DISFOLD_S 2 - -// Field: [1] DISDEFWBUF -// -// Disables write buffer use during default memory map accesses. This causes -// all bus faults to be precise bus faults but decreases the performance of the -// processor because the stores to memory have to complete before the next -// instruction can be executed. -#define CPU_SCS_ACTLR_DISDEFWBUF 0x00000002 -#define CPU_SCS_ACTLR_DISDEFWBUF_BITN 1 -#define CPU_SCS_ACTLR_DISDEFWBUF_M 0x00000002 -#define CPU_SCS_ACTLR_DISDEFWBUF_S 1 - -// Field: [0] DISMCYCINT -// -// Disables interruption of multi-cycle instructions. This increases the -// interrupt latency of the processor becuase LDM/STM completes before -// interrupt stacking occurs. -#define CPU_SCS_ACTLR_DISMCYCINT 0x00000001 -#define CPU_SCS_ACTLR_DISMCYCINT_BITN 0 -#define CPU_SCS_ACTLR_DISMCYCINT_M 0x00000001 -#define CPU_SCS_ACTLR_DISMCYCINT_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_STCSR -// -//***************************************************************************** -// Field: [16] COUNTFLAG -// -// Returns 1 if timer counted to 0 since last time this was read. Clears on -// read by application of any part of the SysTick Control and Status Register. -// If read by the debugger using the DAP, this bit is cleared on read-only if -// the MasterType bit in the **AHB-AP** Control Register is set to 0. -// Otherwise, COUNTFLAG is not changed by the debugger read. -#define CPU_SCS_STCSR_COUNTFLAG 0x00010000 -#define CPU_SCS_STCSR_COUNTFLAG_BITN 16 -#define CPU_SCS_STCSR_COUNTFLAG_M 0x00010000 -#define CPU_SCS_STCSR_COUNTFLAG_S 16 - -// Field: [2] CLKSOURCE -// -// Clock source: -// -// 0: External reference clock. -// 1: Core clock -// -// External clock is not available in this device. Writes to this field will be -// ignored. -#define CPU_SCS_STCSR_CLKSOURCE 0x00000004 -#define CPU_SCS_STCSR_CLKSOURCE_BITN 2 -#define CPU_SCS_STCSR_CLKSOURCE_M 0x00000004 -#define CPU_SCS_STCSR_CLKSOURCE_S 2 - -// Field: [1] TICKINT -// -// 0: Counting down to zero does not pend the SysTick handler. Software can use -// COUNTFLAG to determine if the SysTick handler has ever counted to zero. -// 1: Counting down to zero pends the SysTick handler. -#define CPU_SCS_STCSR_TICKINT 0x00000002 -#define CPU_SCS_STCSR_TICKINT_BITN 1 -#define CPU_SCS_STCSR_TICKINT_M 0x00000002 -#define CPU_SCS_STCSR_TICKINT_S 1 - -// Field: [0] ENABLE -// -// Enable SysTick counter -// -// 0: Counter disabled -// 1: Counter operates in a multi-shot way. That is, counter loads with the -// Reload value STRVR.RELOAD and then begins counting down. On reaching 0, it -// sets COUNTFLAG to 1 and optionally pends the SysTick handler, based on -// TICKINT. It then loads STRVR.RELOAD again, and begins counting. -#define CPU_SCS_STCSR_ENABLE 0x00000001 -#define CPU_SCS_STCSR_ENABLE_BITN 0 -#define CPU_SCS_STCSR_ENABLE_M 0x00000001 -#define CPU_SCS_STCSR_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_STRVR -// -//***************************************************************************** -// Field: [23:0] RELOAD -// -// Value to load into the SysTick Current Value Register STCVR.CURRENT when the -// counter reaches 0. -#define CPU_SCS_STRVR_RELOAD_W 24 -#define CPU_SCS_STRVR_RELOAD_M 0x00FFFFFF -#define CPU_SCS_STRVR_RELOAD_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_STCVR -// -//***************************************************************************** -// Field: [23:0] CURRENT -// -// Current value at the time the register is accessed. No read-modify-write -// protection is provided, so change with care. Writing to it with any value -// clears the register to 0. Clearing this register also clears -// STCSR.COUNTFLAG. -#define CPU_SCS_STCVR_CURRENT_W 24 -#define CPU_SCS_STCVR_CURRENT_M 0x00FFFFFF -#define CPU_SCS_STCVR_CURRENT_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_STCR -// -//***************************************************************************** -// Field: [31] NOREF -// -// Reads as one. Indicates that no separate reference clock is provided. -#define CPU_SCS_STCR_NOREF 0x80000000 -#define CPU_SCS_STCR_NOREF_BITN 31 -#define CPU_SCS_STCR_NOREF_M 0x80000000 -#define CPU_SCS_STCR_NOREF_S 31 - -// Field: [30] SKEW -// -// Reads as one. The calibration value is not exactly 10ms because of clock -// frequency. This could affect its suitability as a software real time clock. -#define CPU_SCS_STCR_SKEW 0x40000000 -#define CPU_SCS_STCR_SKEW_BITN 30 -#define CPU_SCS_STCR_SKEW_M 0x40000000 -#define CPU_SCS_STCR_SKEW_S 30 - -// Field: [23:0] TENMS -// -// An optional Reload value to be used for 10ms (100Hz) timing, subject to -// system clock skew errors. The value read is valid only when core clock is at -// 48MHz. -#define CPU_SCS_STCR_TENMS_W 24 -#define CPU_SCS_STCR_TENMS_M 0x00FFFFFF -#define CPU_SCS_STCR_TENMS_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ISER0 -// -//***************************************************************************** -// Field: [31] SETENA31 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA31 0x80000000 -#define CPU_SCS_NVIC_ISER0_SETENA31_BITN 31 -#define CPU_SCS_NVIC_ISER0_SETENA31_M 0x80000000 -#define CPU_SCS_NVIC_ISER0_SETENA31_S 31 - -// Field: [30] SETENA30 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA30 0x40000000 -#define CPU_SCS_NVIC_ISER0_SETENA30_BITN 30 -#define CPU_SCS_NVIC_ISER0_SETENA30_M 0x40000000 -#define CPU_SCS_NVIC_ISER0_SETENA30_S 30 - -// Field: [29] SETENA29 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA29 0x20000000 -#define CPU_SCS_NVIC_ISER0_SETENA29_BITN 29 -#define CPU_SCS_NVIC_ISER0_SETENA29_M 0x20000000 -#define CPU_SCS_NVIC_ISER0_SETENA29_S 29 - -// Field: [28] SETENA28 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA28 0x10000000 -#define CPU_SCS_NVIC_ISER0_SETENA28_BITN 28 -#define CPU_SCS_NVIC_ISER0_SETENA28_M 0x10000000 -#define CPU_SCS_NVIC_ISER0_SETENA28_S 28 - -// Field: [27] SETENA27 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA27 0x08000000 -#define CPU_SCS_NVIC_ISER0_SETENA27_BITN 27 -#define CPU_SCS_NVIC_ISER0_SETENA27_M 0x08000000 -#define CPU_SCS_NVIC_ISER0_SETENA27_S 27 - -// Field: [26] SETENA26 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA26 0x04000000 -#define CPU_SCS_NVIC_ISER0_SETENA26_BITN 26 -#define CPU_SCS_NVIC_ISER0_SETENA26_M 0x04000000 -#define CPU_SCS_NVIC_ISER0_SETENA26_S 26 - -// Field: [25] SETENA25 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA25 0x02000000 -#define CPU_SCS_NVIC_ISER0_SETENA25_BITN 25 -#define CPU_SCS_NVIC_ISER0_SETENA25_M 0x02000000 -#define CPU_SCS_NVIC_ISER0_SETENA25_S 25 - -// Field: [24] SETENA24 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA24 0x01000000 -#define CPU_SCS_NVIC_ISER0_SETENA24_BITN 24 -#define CPU_SCS_NVIC_ISER0_SETENA24_M 0x01000000 -#define CPU_SCS_NVIC_ISER0_SETENA24_S 24 - -// Field: [23] SETENA23 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA23 0x00800000 -#define CPU_SCS_NVIC_ISER0_SETENA23_BITN 23 -#define CPU_SCS_NVIC_ISER0_SETENA23_M 0x00800000 -#define CPU_SCS_NVIC_ISER0_SETENA23_S 23 - -// Field: [22] SETENA22 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA22 0x00400000 -#define CPU_SCS_NVIC_ISER0_SETENA22_BITN 22 -#define CPU_SCS_NVIC_ISER0_SETENA22_M 0x00400000 -#define CPU_SCS_NVIC_ISER0_SETENA22_S 22 - -// Field: [21] SETENA21 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA21 0x00200000 -#define CPU_SCS_NVIC_ISER0_SETENA21_BITN 21 -#define CPU_SCS_NVIC_ISER0_SETENA21_M 0x00200000 -#define CPU_SCS_NVIC_ISER0_SETENA21_S 21 - -// Field: [20] SETENA20 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA20 0x00100000 -#define CPU_SCS_NVIC_ISER0_SETENA20_BITN 20 -#define CPU_SCS_NVIC_ISER0_SETENA20_M 0x00100000 -#define CPU_SCS_NVIC_ISER0_SETENA20_S 20 - -// Field: [19] SETENA19 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA19 0x00080000 -#define CPU_SCS_NVIC_ISER0_SETENA19_BITN 19 -#define CPU_SCS_NVIC_ISER0_SETENA19_M 0x00080000 -#define CPU_SCS_NVIC_ISER0_SETENA19_S 19 - -// Field: [18] SETENA18 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA18 0x00040000 -#define CPU_SCS_NVIC_ISER0_SETENA18_BITN 18 -#define CPU_SCS_NVIC_ISER0_SETENA18_M 0x00040000 -#define CPU_SCS_NVIC_ISER0_SETENA18_S 18 - -// Field: [17] SETENA17 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA17 0x00020000 -#define CPU_SCS_NVIC_ISER0_SETENA17_BITN 17 -#define CPU_SCS_NVIC_ISER0_SETENA17_M 0x00020000 -#define CPU_SCS_NVIC_ISER0_SETENA17_S 17 - -// Field: [16] SETENA16 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA16 0x00010000 -#define CPU_SCS_NVIC_ISER0_SETENA16_BITN 16 -#define CPU_SCS_NVIC_ISER0_SETENA16_M 0x00010000 -#define CPU_SCS_NVIC_ISER0_SETENA16_S 16 - -// Field: [15] SETENA15 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA15 0x00008000 -#define CPU_SCS_NVIC_ISER0_SETENA15_BITN 15 -#define CPU_SCS_NVIC_ISER0_SETENA15_M 0x00008000 -#define CPU_SCS_NVIC_ISER0_SETENA15_S 15 - -// Field: [14] SETENA14 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA14 0x00004000 -#define CPU_SCS_NVIC_ISER0_SETENA14_BITN 14 -#define CPU_SCS_NVIC_ISER0_SETENA14_M 0x00004000 -#define CPU_SCS_NVIC_ISER0_SETENA14_S 14 - -// Field: [13] SETENA13 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA13 0x00002000 -#define CPU_SCS_NVIC_ISER0_SETENA13_BITN 13 -#define CPU_SCS_NVIC_ISER0_SETENA13_M 0x00002000 -#define CPU_SCS_NVIC_ISER0_SETENA13_S 13 - -// Field: [12] SETENA12 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA12 0x00001000 -#define CPU_SCS_NVIC_ISER0_SETENA12_BITN 12 -#define CPU_SCS_NVIC_ISER0_SETENA12_M 0x00001000 -#define CPU_SCS_NVIC_ISER0_SETENA12_S 12 - -// Field: [11] SETENA11 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA11 0x00000800 -#define CPU_SCS_NVIC_ISER0_SETENA11_BITN 11 -#define CPU_SCS_NVIC_ISER0_SETENA11_M 0x00000800 -#define CPU_SCS_NVIC_ISER0_SETENA11_S 11 - -// Field: [10] SETENA10 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA10 0x00000400 -#define CPU_SCS_NVIC_ISER0_SETENA10_BITN 10 -#define CPU_SCS_NVIC_ISER0_SETENA10_M 0x00000400 -#define CPU_SCS_NVIC_ISER0_SETENA10_S 10 - -// Field: [9] SETENA9 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA9 0x00000200 -#define CPU_SCS_NVIC_ISER0_SETENA9_BITN 9 -#define CPU_SCS_NVIC_ISER0_SETENA9_M 0x00000200 -#define CPU_SCS_NVIC_ISER0_SETENA9_S 9 - -// Field: [8] SETENA8 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA8 0x00000100 -#define CPU_SCS_NVIC_ISER0_SETENA8_BITN 8 -#define CPU_SCS_NVIC_ISER0_SETENA8_M 0x00000100 -#define CPU_SCS_NVIC_ISER0_SETENA8_S 8 - -// Field: [7] SETENA7 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA7 0x00000080 -#define CPU_SCS_NVIC_ISER0_SETENA7_BITN 7 -#define CPU_SCS_NVIC_ISER0_SETENA7_M 0x00000080 -#define CPU_SCS_NVIC_ISER0_SETENA7_S 7 - -// Field: [6] SETENA6 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA6 0x00000040 -#define CPU_SCS_NVIC_ISER0_SETENA6_BITN 6 -#define CPU_SCS_NVIC_ISER0_SETENA6_M 0x00000040 -#define CPU_SCS_NVIC_ISER0_SETENA6_S 6 - -// Field: [5] SETENA5 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA5 0x00000020 -#define CPU_SCS_NVIC_ISER0_SETENA5_BITN 5 -#define CPU_SCS_NVIC_ISER0_SETENA5_M 0x00000020 -#define CPU_SCS_NVIC_ISER0_SETENA5_S 5 - -// Field: [4] SETENA4 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA4 0x00000010 -#define CPU_SCS_NVIC_ISER0_SETENA4_BITN 4 -#define CPU_SCS_NVIC_ISER0_SETENA4_M 0x00000010 -#define CPU_SCS_NVIC_ISER0_SETENA4_S 4 - -// Field: [3] SETENA3 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA3 0x00000008 -#define CPU_SCS_NVIC_ISER0_SETENA3_BITN 3 -#define CPU_SCS_NVIC_ISER0_SETENA3_M 0x00000008 -#define CPU_SCS_NVIC_ISER0_SETENA3_S 3 - -// Field: [2] SETENA2 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA2 0x00000004 -#define CPU_SCS_NVIC_ISER0_SETENA2_BITN 2 -#define CPU_SCS_NVIC_ISER0_SETENA2_M 0x00000004 -#define CPU_SCS_NVIC_ISER0_SETENA2_S 2 - -// Field: [1] SETENA1 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA1 0x00000002 -#define CPU_SCS_NVIC_ISER0_SETENA1_BITN 1 -#define CPU_SCS_NVIC_ISER0_SETENA1_M 0x00000002 -#define CPU_SCS_NVIC_ISER0_SETENA1_S 1 - -// Field: [0] SETENA0 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER0_SETENA0 0x00000001 -#define CPU_SCS_NVIC_ISER0_SETENA0_BITN 0 -#define CPU_SCS_NVIC_ISER0_SETENA0_M 0x00000001 -#define CPU_SCS_NVIC_ISER0_SETENA0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ISER1 -// -//***************************************************************************** -// Field: [5] SETENA37 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA37 0x00000020 -#define CPU_SCS_NVIC_ISER1_SETENA37_BITN 5 -#define CPU_SCS_NVIC_ISER1_SETENA37_M 0x00000020 -#define CPU_SCS_NVIC_ISER1_SETENA37_S 5 - -// Field: [4] SETENA36 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA36 0x00000010 -#define CPU_SCS_NVIC_ISER1_SETENA36_BITN 4 -#define CPU_SCS_NVIC_ISER1_SETENA36_M 0x00000010 -#define CPU_SCS_NVIC_ISER1_SETENA36_S 4 - -// Field: [3] SETENA35 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA35 0x00000008 -#define CPU_SCS_NVIC_ISER1_SETENA35_BITN 3 -#define CPU_SCS_NVIC_ISER1_SETENA35_M 0x00000008 -#define CPU_SCS_NVIC_ISER1_SETENA35_S 3 - -// Field: [2] SETENA34 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA34 0x00000004 -#define CPU_SCS_NVIC_ISER1_SETENA34_BITN 2 -#define CPU_SCS_NVIC_ISER1_SETENA34_M 0x00000004 -#define CPU_SCS_NVIC_ISER1_SETENA34_S 2 - -// Field: [1] SETENA33 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA33 0x00000002 -#define CPU_SCS_NVIC_ISER1_SETENA33_BITN 1 -#define CPU_SCS_NVIC_ISER1_SETENA33_M 0x00000002 -#define CPU_SCS_NVIC_ISER1_SETENA33_S 1 - -// Field: [0] SETENA32 -// -// Writing 0 to this bit has no effect, writing 1 to this bit enables the -// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ISER1_SETENA32 0x00000001 -#define CPU_SCS_NVIC_ISER1_SETENA32_BITN 0 -#define CPU_SCS_NVIC_ISER1_SETENA32_M 0x00000001 -#define CPU_SCS_NVIC_ISER1_SETENA32_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ICER0 -// -//***************************************************************************** -// Field: [31] CLRENA31 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA31 0x80000000 -#define CPU_SCS_NVIC_ICER0_CLRENA31_BITN 31 -#define CPU_SCS_NVIC_ICER0_CLRENA31_M 0x80000000 -#define CPU_SCS_NVIC_ICER0_CLRENA31_S 31 - -// Field: [30] CLRENA30 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA30 0x40000000 -#define CPU_SCS_NVIC_ICER0_CLRENA30_BITN 30 -#define CPU_SCS_NVIC_ICER0_CLRENA30_M 0x40000000 -#define CPU_SCS_NVIC_ICER0_CLRENA30_S 30 - -// Field: [29] CLRENA29 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA29 0x20000000 -#define CPU_SCS_NVIC_ICER0_CLRENA29_BITN 29 -#define CPU_SCS_NVIC_ICER0_CLRENA29_M 0x20000000 -#define CPU_SCS_NVIC_ICER0_CLRENA29_S 29 - -// Field: [28] CLRENA28 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA28 0x10000000 -#define CPU_SCS_NVIC_ICER0_CLRENA28_BITN 28 -#define CPU_SCS_NVIC_ICER0_CLRENA28_M 0x10000000 -#define CPU_SCS_NVIC_ICER0_CLRENA28_S 28 - -// Field: [27] CLRENA27 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA27 0x08000000 -#define CPU_SCS_NVIC_ICER0_CLRENA27_BITN 27 -#define CPU_SCS_NVIC_ICER0_CLRENA27_M 0x08000000 -#define CPU_SCS_NVIC_ICER0_CLRENA27_S 27 - -// Field: [26] CLRENA26 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA26 0x04000000 -#define CPU_SCS_NVIC_ICER0_CLRENA26_BITN 26 -#define CPU_SCS_NVIC_ICER0_CLRENA26_M 0x04000000 -#define CPU_SCS_NVIC_ICER0_CLRENA26_S 26 - -// Field: [25] CLRENA25 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA25 0x02000000 -#define CPU_SCS_NVIC_ICER0_CLRENA25_BITN 25 -#define CPU_SCS_NVIC_ICER0_CLRENA25_M 0x02000000 -#define CPU_SCS_NVIC_ICER0_CLRENA25_S 25 - -// Field: [24] CLRENA24 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA24 0x01000000 -#define CPU_SCS_NVIC_ICER0_CLRENA24_BITN 24 -#define CPU_SCS_NVIC_ICER0_CLRENA24_M 0x01000000 -#define CPU_SCS_NVIC_ICER0_CLRENA24_S 24 - -// Field: [23] CLRENA23 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA23 0x00800000 -#define CPU_SCS_NVIC_ICER0_CLRENA23_BITN 23 -#define CPU_SCS_NVIC_ICER0_CLRENA23_M 0x00800000 -#define CPU_SCS_NVIC_ICER0_CLRENA23_S 23 - -// Field: [22] CLRENA22 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA22 0x00400000 -#define CPU_SCS_NVIC_ICER0_CLRENA22_BITN 22 -#define CPU_SCS_NVIC_ICER0_CLRENA22_M 0x00400000 -#define CPU_SCS_NVIC_ICER0_CLRENA22_S 22 - -// Field: [21] CLRENA21 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA21 0x00200000 -#define CPU_SCS_NVIC_ICER0_CLRENA21_BITN 21 -#define CPU_SCS_NVIC_ICER0_CLRENA21_M 0x00200000 -#define CPU_SCS_NVIC_ICER0_CLRENA21_S 21 - -// Field: [20] CLRENA20 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA20 0x00100000 -#define CPU_SCS_NVIC_ICER0_CLRENA20_BITN 20 -#define CPU_SCS_NVIC_ICER0_CLRENA20_M 0x00100000 -#define CPU_SCS_NVIC_ICER0_CLRENA20_S 20 - -// Field: [19] CLRENA19 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA19 0x00080000 -#define CPU_SCS_NVIC_ICER0_CLRENA19_BITN 19 -#define CPU_SCS_NVIC_ICER0_CLRENA19_M 0x00080000 -#define CPU_SCS_NVIC_ICER0_CLRENA19_S 19 - -// Field: [18] CLRENA18 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA18 0x00040000 -#define CPU_SCS_NVIC_ICER0_CLRENA18_BITN 18 -#define CPU_SCS_NVIC_ICER0_CLRENA18_M 0x00040000 -#define CPU_SCS_NVIC_ICER0_CLRENA18_S 18 - -// Field: [17] CLRENA17 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA17 0x00020000 -#define CPU_SCS_NVIC_ICER0_CLRENA17_BITN 17 -#define CPU_SCS_NVIC_ICER0_CLRENA17_M 0x00020000 -#define CPU_SCS_NVIC_ICER0_CLRENA17_S 17 - -// Field: [16] CLRENA16 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA16 0x00010000 -#define CPU_SCS_NVIC_ICER0_CLRENA16_BITN 16 -#define CPU_SCS_NVIC_ICER0_CLRENA16_M 0x00010000 -#define CPU_SCS_NVIC_ICER0_CLRENA16_S 16 - -// Field: [15] CLRENA15 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA15 0x00008000 -#define CPU_SCS_NVIC_ICER0_CLRENA15_BITN 15 -#define CPU_SCS_NVIC_ICER0_CLRENA15_M 0x00008000 -#define CPU_SCS_NVIC_ICER0_CLRENA15_S 15 - -// Field: [14] CLRENA14 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA14 0x00004000 -#define CPU_SCS_NVIC_ICER0_CLRENA14_BITN 14 -#define CPU_SCS_NVIC_ICER0_CLRENA14_M 0x00004000 -#define CPU_SCS_NVIC_ICER0_CLRENA14_S 14 - -// Field: [13] CLRENA13 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA13 0x00002000 -#define CPU_SCS_NVIC_ICER0_CLRENA13_BITN 13 -#define CPU_SCS_NVIC_ICER0_CLRENA13_M 0x00002000 -#define CPU_SCS_NVIC_ICER0_CLRENA13_S 13 - -// Field: [12] CLRENA12 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA12 0x00001000 -#define CPU_SCS_NVIC_ICER0_CLRENA12_BITN 12 -#define CPU_SCS_NVIC_ICER0_CLRENA12_M 0x00001000 -#define CPU_SCS_NVIC_ICER0_CLRENA12_S 12 - -// Field: [11] CLRENA11 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA11 0x00000800 -#define CPU_SCS_NVIC_ICER0_CLRENA11_BITN 11 -#define CPU_SCS_NVIC_ICER0_CLRENA11_M 0x00000800 -#define CPU_SCS_NVIC_ICER0_CLRENA11_S 11 - -// Field: [10] CLRENA10 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA10 0x00000400 -#define CPU_SCS_NVIC_ICER0_CLRENA10_BITN 10 -#define CPU_SCS_NVIC_ICER0_CLRENA10_M 0x00000400 -#define CPU_SCS_NVIC_ICER0_CLRENA10_S 10 - -// Field: [9] CLRENA9 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA9 0x00000200 -#define CPU_SCS_NVIC_ICER0_CLRENA9_BITN 9 -#define CPU_SCS_NVIC_ICER0_CLRENA9_M 0x00000200 -#define CPU_SCS_NVIC_ICER0_CLRENA9_S 9 - -// Field: [8] CLRENA8 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA8 0x00000100 -#define CPU_SCS_NVIC_ICER0_CLRENA8_BITN 8 -#define CPU_SCS_NVIC_ICER0_CLRENA8_M 0x00000100 -#define CPU_SCS_NVIC_ICER0_CLRENA8_S 8 - -// Field: [7] CLRENA7 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA7 0x00000080 -#define CPU_SCS_NVIC_ICER0_CLRENA7_BITN 7 -#define CPU_SCS_NVIC_ICER0_CLRENA7_M 0x00000080 -#define CPU_SCS_NVIC_ICER0_CLRENA7_S 7 - -// Field: [6] CLRENA6 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA6 0x00000040 -#define CPU_SCS_NVIC_ICER0_CLRENA6_BITN 6 -#define CPU_SCS_NVIC_ICER0_CLRENA6_M 0x00000040 -#define CPU_SCS_NVIC_ICER0_CLRENA6_S 6 - -// Field: [5] CLRENA5 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA5 0x00000020 -#define CPU_SCS_NVIC_ICER0_CLRENA5_BITN 5 -#define CPU_SCS_NVIC_ICER0_CLRENA5_M 0x00000020 -#define CPU_SCS_NVIC_ICER0_CLRENA5_S 5 - -// Field: [4] CLRENA4 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA4 0x00000010 -#define CPU_SCS_NVIC_ICER0_CLRENA4_BITN 4 -#define CPU_SCS_NVIC_ICER0_CLRENA4_M 0x00000010 -#define CPU_SCS_NVIC_ICER0_CLRENA4_S 4 - -// Field: [3] CLRENA3 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA3 0x00000008 -#define CPU_SCS_NVIC_ICER0_CLRENA3_BITN 3 -#define CPU_SCS_NVIC_ICER0_CLRENA3_M 0x00000008 -#define CPU_SCS_NVIC_ICER0_CLRENA3_S 3 - -// Field: [2] CLRENA2 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA2 0x00000004 -#define CPU_SCS_NVIC_ICER0_CLRENA2_BITN 2 -#define CPU_SCS_NVIC_ICER0_CLRENA2_M 0x00000004 -#define CPU_SCS_NVIC_ICER0_CLRENA2_S 2 - -// Field: [1] CLRENA1 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA1 0x00000002 -#define CPU_SCS_NVIC_ICER0_CLRENA1_BITN 1 -#define CPU_SCS_NVIC_ICER0_CLRENA1_M 0x00000002 -#define CPU_SCS_NVIC_ICER0_CLRENA1_S 1 - -// Field: [0] CLRENA0 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER0_CLRENA0 0x00000001 -#define CPU_SCS_NVIC_ICER0_CLRENA0_BITN 0 -#define CPU_SCS_NVIC_ICER0_CLRENA0_M 0x00000001 -#define CPU_SCS_NVIC_ICER0_CLRENA0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ICER1 -// -//***************************************************************************** -// Field: [5] CLRENA37 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA37 0x00000020 -#define CPU_SCS_NVIC_ICER1_CLRENA37_BITN 5 -#define CPU_SCS_NVIC_ICER1_CLRENA37_M 0x00000020 -#define CPU_SCS_NVIC_ICER1_CLRENA37_S 5 - -// Field: [4] CLRENA36 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA36 0x00000010 -#define CPU_SCS_NVIC_ICER1_CLRENA36_BITN 4 -#define CPU_SCS_NVIC_ICER1_CLRENA36_M 0x00000010 -#define CPU_SCS_NVIC_ICER1_CLRENA36_S 4 - -// Field: [3] CLRENA35 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA35 0x00000008 -#define CPU_SCS_NVIC_ICER1_CLRENA35_BITN 3 -#define CPU_SCS_NVIC_ICER1_CLRENA35_M 0x00000008 -#define CPU_SCS_NVIC_ICER1_CLRENA35_S 3 - -// Field: [2] CLRENA34 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA34 0x00000004 -#define CPU_SCS_NVIC_ICER1_CLRENA34_BITN 2 -#define CPU_SCS_NVIC_ICER1_CLRENA34_M 0x00000004 -#define CPU_SCS_NVIC_ICER1_CLRENA34_S 2 - -// Field: [1] CLRENA33 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA33 0x00000002 -#define CPU_SCS_NVIC_ICER1_CLRENA33_BITN 1 -#define CPU_SCS_NVIC_ICER1_CLRENA33_M 0x00000002 -#define CPU_SCS_NVIC_ICER1_CLRENA33_S 1 - -// Field: [0] CLRENA32 -// -// Writing 0 to this bit has no effect, writing 1 to this bit disables the -// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit -// returns its current enable state. -#define CPU_SCS_NVIC_ICER1_CLRENA32 0x00000001 -#define CPU_SCS_NVIC_ICER1_CLRENA32_BITN 0 -#define CPU_SCS_NVIC_ICER1_CLRENA32_M 0x00000001 -#define CPU_SCS_NVIC_ICER1_CLRENA32_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ISPR0 -// -//***************************************************************************** -// Field: [31] SETPEND31 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 31 (See EVENT:CPUIRQSEL31.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND31 0x80000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_BITN 31 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_M 0x80000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND31_S 31 - -// Field: [30] SETPEND30 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 30 (See EVENT:CPUIRQSEL30.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND30 0x40000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_BITN 30 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_M 0x40000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND30_S 30 - -// Field: [29] SETPEND29 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 29 (See EVENT:CPUIRQSEL29.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND29 0x20000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_BITN 29 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_M 0x20000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND29_S 29 - -// Field: [28] SETPEND28 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 28 (See EVENT:CPUIRQSEL28.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND28 0x10000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_BITN 28 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_M 0x10000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND28_S 28 - -// Field: [27] SETPEND27 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 27 (See EVENT:CPUIRQSEL27.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND27 0x08000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_BITN 27 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_M 0x08000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND27_S 27 - -// Field: [26] SETPEND26 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 26 (See EVENT:CPUIRQSEL26.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND26 0x04000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_BITN 26 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_M 0x04000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND26_S 26 - -// Field: [25] SETPEND25 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 25 (See EVENT:CPUIRQSEL25.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND25 0x02000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_BITN 25 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_M 0x02000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND25_S 25 - -// Field: [24] SETPEND24 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 24 (See EVENT:CPUIRQSEL24.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND24 0x01000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_BITN 24 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_M 0x01000000 -#define CPU_SCS_NVIC_ISPR0_SETPEND24_S 24 - -// Field: [23] SETPEND23 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 23 (See EVENT:CPUIRQSEL23.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND23 0x00800000 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_BITN 23 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_M 0x00800000 -#define CPU_SCS_NVIC_ISPR0_SETPEND23_S 23 - -// Field: [22] SETPEND22 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 22 (See EVENT:CPUIRQSEL22.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND22 0x00400000 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_BITN 22 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_M 0x00400000 -#define CPU_SCS_NVIC_ISPR0_SETPEND22_S 22 - -// Field: [21] SETPEND21 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 21 (See EVENT:CPUIRQSEL21.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND21 0x00200000 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_BITN 21 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_M 0x00200000 -#define CPU_SCS_NVIC_ISPR0_SETPEND21_S 21 - -// Field: [20] SETPEND20 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 20 (See EVENT:CPUIRQSEL20.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND20 0x00100000 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_BITN 20 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_M 0x00100000 -#define CPU_SCS_NVIC_ISPR0_SETPEND20_S 20 - -// Field: [19] SETPEND19 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 19 (See EVENT:CPUIRQSEL19.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND19 0x00080000 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_BITN 19 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_M 0x00080000 -#define CPU_SCS_NVIC_ISPR0_SETPEND19_S 19 - -// Field: [18] SETPEND18 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 18 (See EVENT:CPUIRQSEL18.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND18 0x00040000 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_BITN 18 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_M 0x00040000 -#define CPU_SCS_NVIC_ISPR0_SETPEND18_S 18 - -// Field: [17] SETPEND17 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 17 (See EVENT:CPUIRQSEL17.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND17 0x00020000 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_BITN 17 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_M 0x00020000 -#define CPU_SCS_NVIC_ISPR0_SETPEND17_S 17 - -// Field: [16] SETPEND16 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 16 (See EVENT:CPUIRQSEL16.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND16 0x00010000 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_BITN 16 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_M 0x00010000 -#define CPU_SCS_NVIC_ISPR0_SETPEND16_S 16 - -// Field: [15] SETPEND15 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 15 (See EVENT:CPUIRQSEL15.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND15 0x00008000 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_BITN 15 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_M 0x00008000 -#define CPU_SCS_NVIC_ISPR0_SETPEND15_S 15 - -// Field: [14] SETPEND14 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 14 (See EVENT:CPUIRQSEL14.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND14 0x00004000 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_BITN 14 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_M 0x00004000 -#define CPU_SCS_NVIC_ISPR0_SETPEND14_S 14 - -// Field: [13] SETPEND13 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 13 (See EVENT:CPUIRQSEL13.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND13 0x00002000 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_BITN 13 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_M 0x00002000 -#define CPU_SCS_NVIC_ISPR0_SETPEND13_S 13 - -// Field: [12] SETPEND12 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 12 (See EVENT:CPUIRQSEL12.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND12 0x00001000 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_BITN 12 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_M 0x00001000 -#define CPU_SCS_NVIC_ISPR0_SETPEND12_S 12 - -// Field: [11] SETPEND11 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 11 (See EVENT:CPUIRQSEL11.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND11 0x00000800 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_BITN 11 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_M 0x00000800 -#define CPU_SCS_NVIC_ISPR0_SETPEND11_S 11 - -// Field: [10] SETPEND10 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 10 (See EVENT:CPUIRQSEL10.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND10 0x00000400 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_BITN 10 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_M 0x00000400 -#define CPU_SCS_NVIC_ISPR0_SETPEND10_S 10 - -// Field: [9] SETPEND9 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 9 (See EVENT:CPUIRQSEL9.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND9 0x00000200 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_BITN 9 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_M 0x00000200 -#define CPU_SCS_NVIC_ISPR0_SETPEND9_S 9 - -// Field: [8] SETPEND8 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 8 (See EVENT:CPUIRQSEL8.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND8 0x00000100 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_BITN 8 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_M 0x00000100 -#define CPU_SCS_NVIC_ISPR0_SETPEND8_S 8 - -// Field: [7] SETPEND7 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 7 (See EVENT:CPUIRQSEL7.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND7 0x00000080 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_BITN 7 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_M 0x00000080 -#define CPU_SCS_NVIC_ISPR0_SETPEND7_S 7 - -// Field: [6] SETPEND6 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 6 (See EVENT:CPUIRQSEL6.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND6 0x00000040 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_BITN 6 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_M 0x00000040 -#define CPU_SCS_NVIC_ISPR0_SETPEND6_S 6 - -// Field: [5] SETPEND5 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 5 (See EVENT:CPUIRQSEL5.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND5 0x00000020 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_BITN 5 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_M 0x00000020 -#define CPU_SCS_NVIC_ISPR0_SETPEND5_S 5 - -// Field: [4] SETPEND4 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 4 (See EVENT:CPUIRQSEL4.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND4 0x00000010 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_BITN 4 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_M 0x00000010 -#define CPU_SCS_NVIC_ISPR0_SETPEND4_S 4 - -// Field: [3] SETPEND3 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 3 (See EVENT:CPUIRQSEL3.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND3 0x00000008 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_BITN 3 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_M 0x00000008 -#define CPU_SCS_NVIC_ISPR0_SETPEND3_S 3 - -// Field: [2] SETPEND2 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 2 (See EVENT:CPUIRQSEL2.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND2 0x00000004 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_BITN 2 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_M 0x00000004 -#define CPU_SCS_NVIC_ISPR0_SETPEND2_S 2 - -// Field: [1] SETPEND1 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 1 (See EVENT:CPUIRQSEL1.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND1 0x00000002 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_BITN 1 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_M 0x00000002 -#define CPU_SCS_NVIC_ISPR0_SETPEND1_S 1 - -// Field: [0] SETPEND0 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 0 (See EVENT:CPUIRQSEL0.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR0_SETPEND0 0x00000001 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_BITN 0 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_M 0x00000001 -#define CPU_SCS_NVIC_ISPR0_SETPEND0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ISPR1 -// -//***************************************************************************** -// Field: [5] SETPEND37 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 37 (See EVENT:CPUIRQSEL37.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND37 0x00000020 -#define CPU_SCS_NVIC_ISPR1_SETPEND37_BITN 5 -#define CPU_SCS_NVIC_ISPR1_SETPEND37_M 0x00000020 -#define CPU_SCS_NVIC_ISPR1_SETPEND37_S 5 - -// Field: [4] SETPEND36 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 36 (See EVENT:CPUIRQSEL36.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND36 0x00000010 -#define CPU_SCS_NVIC_ISPR1_SETPEND36_BITN 4 -#define CPU_SCS_NVIC_ISPR1_SETPEND36_M 0x00000010 -#define CPU_SCS_NVIC_ISPR1_SETPEND36_S 4 - -// Field: [3] SETPEND35 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 35 (See EVENT:CPUIRQSEL35.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND35 0x00000008 -#define CPU_SCS_NVIC_ISPR1_SETPEND35_BITN 3 -#define CPU_SCS_NVIC_ISPR1_SETPEND35_M 0x00000008 -#define CPU_SCS_NVIC_ISPR1_SETPEND35_S 3 - -// Field: [2] SETPEND34 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 34 (See EVENT:CPUIRQSEL34.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND34 0x00000004 -#define CPU_SCS_NVIC_ISPR1_SETPEND34_BITN 2 -#define CPU_SCS_NVIC_ISPR1_SETPEND34_M 0x00000004 -#define CPU_SCS_NVIC_ISPR1_SETPEND34_S 2 - -// Field: [1] SETPEND33 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 33 (See EVENT:CPUIRQSEL33.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND33 0x00000002 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_BITN 1 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_M 0x00000002 -#define CPU_SCS_NVIC_ISPR1_SETPEND33_S 1 - -// Field: [0] SETPEND32 -// -// Writing 0 to this bit has no effect, writing 1 to this bit pends the -// interrupt number 32 (See EVENT:CPUIRQSEL32.EV for details). Reading the bit -// returns its current state. -#define CPU_SCS_NVIC_ISPR1_SETPEND32 0x00000001 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_BITN 0 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_M 0x00000001 -#define CPU_SCS_NVIC_ISPR1_SETPEND32_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ICPR0 -// -//***************************************************************************** -// Field: [31] CLRPEND31 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND31 0x80000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_BITN 31 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_M 0x80000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND31_S 31 - -// Field: [30] CLRPEND30 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND30 0x40000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_BITN 30 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_M 0x40000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND30_S 30 - -// Field: [29] CLRPEND29 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND29 0x20000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_BITN 29 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_M 0x20000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND29_S 29 - -// Field: [28] CLRPEND28 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND28 0x10000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_BITN 28 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_M 0x10000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND28_S 28 - -// Field: [27] CLRPEND27 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND27 0x08000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_BITN 27 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_M 0x08000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND27_S 27 - -// Field: [26] CLRPEND26 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND26 0x04000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_BITN 26 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_M 0x04000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND26_S 26 - -// Field: [25] CLRPEND25 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND25 0x02000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_BITN 25 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_M 0x02000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND25_S 25 - -// Field: [24] CLRPEND24 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND24 0x01000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_BITN 24 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_M 0x01000000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND24_S 24 - -// Field: [23] CLRPEND23 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND23 0x00800000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_BITN 23 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_M 0x00800000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND23_S 23 - -// Field: [22] CLRPEND22 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND22 0x00400000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_BITN 22 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_M 0x00400000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND22_S 22 - -// Field: [21] CLRPEND21 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND21 0x00200000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_BITN 21 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_M 0x00200000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND21_S 21 - -// Field: [20] CLRPEND20 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND20 0x00100000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_BITN 20 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_M 0x00100000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND20_S 20 - -// Field: [19] CLRPEND19 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND19 0x00080000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_BITN 19 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_M 0x00080000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND19_S 19 - -// Field: [18] CLRPEND18 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND18 0x00040000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_BITN 18 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_M 0x00040000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND18_S 18 - -// Field: [17] CLRPEND17 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND17 0x00020000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_BITN 17 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_M 0x00020000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND17_S 17 - -// Field: [16] CLRPEND16 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND16 0x00010000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_BITN 16 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_M 0x00010000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND16_S 16 - -// Field: [15] CLRPEND15 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND15 0x00008000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_BITN 15 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_M 0x00008000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND15_S 15 - -// Field: [14] CLRPEND14 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND14 0x00004000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_BITN 14 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_M 0x00004000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND14_S 14 - -// Field: [13] CLRPEND13 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND13 0x00002000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_BITN 13 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_M 0x00002000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND13_S 13 - -// Field: [12] CLRPEND12 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND12 0x00001000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_BITN 12 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_M 0x00001000 -#define CPU_SCS_NVIC_ICPR0_CLRPEND12_S 12 - -// Field: [11] CLRPEND11 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND11 0x00000800 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_BITN 11 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_M 0x00000800 -#define CPU_SCS_NVIC_ICPR0_CLRPEND11_S 11 - -// Field: [10] CLRPEND10 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND10 0x00000400 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_BITN 10 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_M 0x00000400 -#define CPU_SCS_NVIC_ICPR0_CLRPEND10_S 10 - -// Field: [9] CLRPEND9 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND9 0x00000200 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_BITN 9 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_M 0x00000200 -#define CPU_SCS_NVIC_ICPR0_CLRPEND9_S 9 - -// Field: [8] CLRPEND8 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND8 0x00000100 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_BITN 8 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_M 0x00000100 -#define CPU_SCS_NVIC_ICPR0_CLRPEND8_S 8 - -// Field: [7] CLRPEND7 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND7 0x00000080 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_BITN 7 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_M 0x00000080 -#define CPU_SCS_NVIC_ICPR0_CLRPEND7_S 7 - -// Field: [6] CLRPEND6 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND6 0x00000040 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_BITN 6 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_M 0x00000040 -#define CPU_SCS_NVIC_ICPR0_CLRPEND6_S 6 - -// Field: [5] CLRPEND5 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND5 0x00000020 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_BITN 5 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_M 0x00000020 -#define CPU_SCS_NVIC_ICPR0_CLRPEND5_S 5 - -// Field: [4] CLRPEND4 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND4 0x00000010 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_BITN 4 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_M 0x00000010 -#define CPU_SCS_NVIC_ICPR0_CLRPEND4_S 4 - -// Field: [3] CLRPEND3 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND3 0x00000008 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_BITN 3 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_M 0x00000008 -#define CPU_SCS_NVIC_ICPR0_CLRPEND3_S 3 - -// Field: [2] CLRPEND2 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND2 0x00000004 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_BITN 2 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_M 0x00000004 -#define CPU_SCS_NVIC_ICPR0_CLRPEND2_S 2 - -// Field: [1] CLRPEND1 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND1 0x00000002 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_BITN 1 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_M 0x00000002 -#define CPU_SCS_NVIC_ICPR0_CLRPEND1_S 1 - -// Field: [0] CLRPEND0 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR0_CLRPEND0 0x00000001 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_BITN 0 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_M 0x00000001 -#define CPU_SCS_NVIC_ICPR0_CLRPEND0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_ICPR1 -// -//***************************************************************************** -// Field: [5] CLRPEND37 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND37 0x00000020 -#define CPU_SCS_NVIC_ICPR1_CLRPEND37_BITN 5 -#define CPU_SCS_NVIC_ICPR1_CLRPEND37_M 0x00000020 -#define CPU_SCS_NVIC_ICPR1_CLRPEND37_S 5 - -// Field: [4] CLRPEND36 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND36 0x00000010 -#define CPU_SCS_NVIC_ICPR1_CLRPEND36_BITN 4 -#define CPU_SCS_NVIC_ICPR1_CLRPEND36_M 0x00000010 -#define CPU_SCS_NVIC_ICPR1_CLRPEND36_S 4 - -// Field: [3] CLRPEND35 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND35 0x00000008 -#define CPU_SCS_NVIC_ICPR1_CLRPEND35_BITN 3 -#define CPU_SCS_NVIC_ICPR1_CLRPEND35_M 0x00000008 -#define CPU_SCS_NVIC_ICPR1_CLRPEND35_S 3 - -// Field: [2] CLRPEND34 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND34 0x00000004 -#define CPU_SCS_NVIC_ICPR1_CLRPEND34_BITN 2 -#define CPU_SCS_NVIC_ICPR1_CLRPEND34_M 0x00000004 -#define CPU_SCS_NVIC_ICPR1_CLRPEND34_S 2 - -// Field: [1] CLRPEND33 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND33 0x00000002 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_BITN 1 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_M 0x00000002 -#define CPU_SCS_NVIC_ICPR1_CLRPEND33_S 1 - -// Field: [0] CLRPEND32 -// -// Writing 0 to this bit has no effect, writing 1 to this bit clears the -// corresponding pending interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). -// Reading the bit returns its current state. -#define CPU_SCS_NVIC_ICPR1_CLRPEND32 0x00000001 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_BITN 0 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_M 0x00000001 -#define CPU_SCS_NVIC_ICPR1_CLRPEND32_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IABR0 -// -//***************************************************************************** -// Field: [31] ACTIVE31 -// -// Reading 0 from this bit implies that interrupt line 31 is not active. -// Reading 1 from this bit implies that the interrupt line 31 is active (See -// EVENT:CPUIRQSEL31.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE31 0x80000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_BITN 31 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_M 0x80000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE31_S 31 - -// Field: [30] ACTIVE30 -// -// Reading 0 from this bit implies that interrupt line 30 is not active. -// Reading 1 from this bit implies that the interrupt line 30 is active (See -// EVENT:CPUIRQSEL30.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE30 0x40000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_BITN 30 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_M 0x40000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE30_S 30 - -// Field: [29] ACTIVE29 -// -// Reading 0 from this bit implies that interrupt line 29 is not active. -// Reading 1 from this bit implies that the interrupt line 29 is active (See -// EVENT:CPUIRQSEL29.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE29 0x20000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_BITN 29 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_M 0x20000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE29_S 29 - -// Field: [28] ACTIVE28 -// -// Reading 0 from this bit implies that interrupt line 28 is not active. -// Reading 1 from this bit implies that the interrupt line 28 is active (See -// EVENT:CPUIRQSEL28.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE28 0x10000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_BITN 28 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_M 0x10000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE28_S 28 - -// Field: [27] ACTIVE27 -// -// Reading 0 from this bit implies that interrupt line 27 is not active. -// Reading 1 from this bit implies that the interrupt line 27 is active (See -// EVENT:CPUIRQSEL27.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE27 0x08000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_BITN 27 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_M 0x08000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE27_S 27 - -// Field: [26] ACTIVE26 -// -// Reading 0 from this bit implies that interrupt line 26 is not active. -// Reading 1 from this bit implies that the interrupt line 26 is active (See -// EVENT:CPUIRQSEL26.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE26 0x04000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_BITN 26 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_M 0x04000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE26_S 26 - -// Field: [25] ACTIVE25 -// -// Reading 0 from this bit implies that interrupt line 25 is not active. -// Reading 1 from this bit implies that the interrupt line 25 is active (See -// EVENT:CPUIRQSEL25.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE25 0x02000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_BITN 25 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_M 0x02000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE25_S 25 - -// Field: [24] ACTIVE24 -// -// Reading 0 from this bit implies that interrupt line 24 is not active. -// Reading 1 from this bit implies that the interrupt line 24 is active (See -// EVENT:CPUIRQSEL24.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE24 0x01000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_BITN 24 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_M 0x01000000 -#define CPU_SCS_NVIC_IABR0_ACTIVE24_S 24 - -// Field: [23] ACTIVE23 -// -// Reading 0 from this bit implies that interrupt line 23 is not active. -// Reading 1 from this bit implies that the interrupt line 23 is active (See -// EVENT:CPUIRQSEL23.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE23 0x00800000 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_BITN 23 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_M 0x00800000 -#define CPU_SCS_NVIC_IABR0_ACTIVE23_S 23 - -// Field: [22] ACTIVE22 -// -// Reading 0 from this bit implies that interrupt line 22 is not active. -// Reading 1 from this bit implies that the interrupt line 22 is active (See -// EVENT:CPUIRQSEL22.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE22 0x00400000 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_BITN 22 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_M 0x00400000 -#define CPU_SCS_NVIC_IABR0_ACTIVE22_S 22 - -// Field: [21] ACTIVE21 -// -// Reading 0 from this bit implies that interrupt line 21 is not active. -// Reading 1 from this bit implies that the interrupt line 21 is active (See -// EVENT:CPUIRQSEL21.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE21 0x00200000 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_BITN 21 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_M 0x00200000 -#define CPU_SCS_NVIC_IABR0_ACTIVE21_S 21 - -// Field: [20] ACTIVE20 -// -// Reading 0 from this bit implies that interrupt line 20 is not active. -// Reading 1 from this bit implies that the interrupt line 20 is active (See -// EVENT:CPUIRQSEL20.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE20 0x00100000 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_BITN 20 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_M 0x00100000 -#define CPU_SCS_NVIC_IABR0_ACTIVE20_S 20 - -// Field: [19] ACTIVE19 -// -// Reading 0 from this bit implies that interrupt line 19 is not active. -// Reading 1 from this bit implies that the interrupt line 19 is active (See -// EVENT:CPUIRQSEL19.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE19 0x00080000 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_BITN 19 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_M 0x00080000 -#define CPU_SCS_NVIC_IABR0_ACTIVE19_S 19 - -// Field: [18] ACTIVE18 -// -// Reading 0 from this bit implies that interrupt line 18 is not active. -// Reading 1 from this bit implies that the interrupt line 18 is active (See -// EVENT:CPUIRQSEL18.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE18 0x00040000 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_BITN 18 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_M 0x00040000 -#define CPU_SCS_NVIC_IABR0_ACTIVE18_S 18 - -// Field: [17] ACTIVE17 -// -// Reading 0 from this bit implies that interrupt line 17 is not active. -// Reading 1 from this bit implies that the interrupt line 17 is active (See -// EVENT:CPUIRQSEL17.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE17 0x00020000 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_BITN 17 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_M 0x00020000 -#define CPU_SCS_NVIC_IABR0_ACTIVE17_S 17 - -// Field: [16] ACTIVE16 -// -// Reading 0 from this bit implies that interrupt line 16 is not active. -// Reading 1 from this bit implies that the interrupt line 16 is active (See -// EVENT:CPUIRQSEL16.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE16 0x00010000 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_BITN 16 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_M 0x00010000 -#define CPU_SCS_NVIC_IABR0_ACTIVE16_S 16 - -// Field: [15] ACTIVE15 -// -// Reading 0 from this bit implies that interrupt line 15 is not active. -// Reading 1 from this bit implies that the interrupt line 15 is active (See -// EVENT:CPUIRQSEL15.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE15 0x00008000 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_BITN 15 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_M 0x00008000 -#define CPU_SCS_NVIC_IABR0_ACTIVE15_S 15 - -// Field: [14] ACTIVE14 -// -// Reading 0 from this bit implies that interrupt line 14 is not active. -// Reading 1 from this bit implies that the interrupt line 14 is active (See -// EVENT:CPUIRQSEL14.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE14 0x00004000 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_BITN 14 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_M 0x00004000 -#define CPU_SCS_NVIC_IABR0_ACTIVE14_S 14 - -// Field: [13] ACTIVE13 -// -// Reading 0 from this bit implies that interrupt line 13 is not active. -// Reading 1 from this bit implies that the interrupt line 13 is active (See -// EVENT:CPUIRQSEL13.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE13 0x00002000 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_BITN 13 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_M 0x00002000 -#define CPU_SCS_NVIC_IABR0_ACTIVE13_S 13 - -// Field: [12] ACTIVE12 -// -// Reading 0 from this bit implies that interrupt line 12 is not active. -// Reading 1 from this bit implies that the interrupt line 12 is active (See -// EVENT:CPUIRQSEL12.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE12 0x00001000 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_BITN 12 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_M 0x00001000 -#define CPU_SCS_NVIC_IABR0_ACTIVE12_S 12 - -// Field: [11] ACTIVE11 -// -// Reading 0 from this bit implies that interrupt line 11 is not active. -// Reading 1 from this bit implies that the interrupt line 11 is active (See -// EVENT:CPUIRQSEL11.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE11 0x00000800 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_BITN 11 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_M 0x00000800 -#define CPU_SCS_NVIC_IABR0_ACTIVE11_S 11 - -// Field: [10] ACTIVE10 -// -// Reading 0 from this bit implies that interrupt line 10 is not active. -// Reading 1 from this bit implies that the interrupt line 10 is active (See -// EVENT:CPUIRQSEL10.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE10 0x00000400 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_BITN 10 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_M 0x00000400 -#define CPU_SCS_NVIC_IABR0_ACTIVE10_S 10 - -// Field: [9] ACTIVE9 -// -// Reading 0 from this bit implies that interrupt line 9 is not active. Reading -// 1 from this bit implies that the interrupt line 9 is active (See -// EVENT:CPUIRQSEL9.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE9 0x00000200 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_BITN 9 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_M 0x00000200 -#define CPU_SCS_NVIC_IABR0_ACTIVE9_S 9 - -// Field: [8] ACTIVE8 -// -// Reading 0 from this bit implies that interrupt line 8 is not active. Reading -// 1 from this bit implies that the interrupt line 8 is active (See -// EVENT:CPUIRQSEL8.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE8 0x00000100 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_BITN 8 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_M 0x00000100 -#define CPU_SCS_NVIC_IABR0_ACTIVE8_S 8 - -// Field: [7] ACTIVE7 -// -// Reading 0 from this bit implies that interrupt line 7 is not active. Reading -// 1 from this bit implies that the interrupt line 7 is active (See -// EVENT:CPUIRQSEL7.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE7 0x00000080 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_BITN 7 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_M 0x00000080 -#define CPU_SCS_NVIC_IABR0_ACTIVE7_S 7 - -// Field: [6] ACTIVE6 -// -// Reading 0 from this bit implies that interrupt line 6 is not active. Reading -// 1 from this bit implies that the interrupt line 6 is active (See -// EVENT:CPUIRQSEL6.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE6 0x00000040 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_BITN 6 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_M 0x00000040 -#define CPU_SCS_NVIC_IABR0_ACTIVE6_S 6 - -// Field: [5] ACTIVE5 -// -// Reading 0 from this bit implies that interrupt line 5 is not active. Reading -// 1 from this bit implies that the interrupt line 5 is active (See -// EVENT:CPUIRQSEL5.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE5 0x00000020 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_BITN 5 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_M 0x00000020 -#define CPU_SCS_NVIC_IABR0_ACTIVE5_S 5 - -// Field: [4] ACTIVE4 -// -// Reading 0 from this bit implies that interrupt line 4 is not active. Reading -// 1 from this bit implies that the interrupt line 4 is active (See -// EVENT:CPUIRQSEL4.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE4 0x00000010 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_BITN 4 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_M 0x00000010 -#define CPU_SCS_NVIC_IABR0_ACTIVE4_S 4 - -// Field: [3] ACTIVE3 -// -// Reading 0 from this bit implies that interrupt line 3 is not active. Reading -// 1 from this bit implies that the interrupt line 3 is active (See -// EVENT:CPUIRQSEL3.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE3 0x00000008 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_BITN 3 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_M 0x00000008 -#define CPU_SCS_NVIC_IABR0_ACTIVE3_S 3 - -// Field: [2] ACTIVE2 -// -// Reading 0 from this bit implies that interrupt line 2 is not active. Reading -// 1 from this bit implies that the interrupt line 2 is active (See -// EVENT:CPUIRQSEL2.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE2 0x00000004 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_BITN 2 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_M 0x00000004 -#define CPU_SCS_NVIC_IABR0_ACTIVE2_S 2 - -// Field: [1] ACTIVE1 -// -// Reading 0 from this bit implies that interrupt line 1 is not active. Reading -// 1 from this bit implies that the interrupt line 1 is active (See -// EVENT:CPUIRQSEL1.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE1 0x00000002 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_BITN 1 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_M 0x00000002 -#define CPU_SCS_NVIC_IABR0_ACTIVE1_S 1 - -// Field: [0] ACTIVE0 -// -// Reading 0 from this bit implies that interrupt line 0 is not active. Reading -// 1 from this bit implies that the interrupt line 0 is active (See -// EVENT:CPUIRQSEL0.EV for details). -#define CPU_SCS_NVIC_IABR0_ACTIVE0 0x00000001 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_BITN 0 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_M 0x00000001 -#define CPU_SCS_NVIC_IABR0_ACTIVE0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IABR1 -// -//***************************************************************************** -// Field: [5] ACTIVE37 -// -// Reading 0 from this bit implies that interrupt line 37 is not active. -// Reading 1 from this bit implies that the interrupt line 37 is active (See -// EVENT:CPUIRQSEL37.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE37 0x00000020 -#define CPU_SCS_NVIC_IABR1_ACTIVE37_BITN 5 -#define CPU_SCS_NVIC_IABR1_ACTIVE37_M 0x00000020 -#define CPU_SCS_NVIC_IABR1_ACTIVE37_S 5 - -// Field: [4] ACTIVE36 -// -// Reading 0 from this bit implies that interrupt line 36 is not active. -// Reading 1 from this bit implies that the interrupt line 36 is active (See -// EVENT:CPUIRQSEL36.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE36 0x00000010 -#define CPU_SCS_NVIC_IABR1_ACTIVE36_BITN 4 -#define CPU_SCS_NVIC_IABR1_ACTIVE36_M 0x00000010 -#define CPU_SCS_NVIC_IABR1_ACTIVE36_S 4 - -// Field: [3] ACTIVE35 -// -// Reading 0 from this bit implies that interrupt line 35 is not active. -// Reading 1 from this bit implies that the interrupt line 35 is active (See -// EVENT:CPUIRQSEL35.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE35 0x00000008 -#define CPU_SCS_NVIC_IABR1_ACTIVE35_BITN 3 -#define CPU_SCS_NVIC_IABR1_ACTIVE35_M 0x00000008 -#define CPU_SCS_NVIC_IABR1_ACTIVE35_S 3 - -// Field: [2] ACTIVE34 -// -// Reading 0 from this bit implies that interrupt line 34 is not active. -// Reading 1 from this bit implies that the interrupt line 34 is active (See -// EVENT:CPUIRQSEL34.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE34 0x00000004 -#define CPU_SCS_NVIC_IABR1_ACTIVE34_BITN 2 -#define CPU_SCS_NVIC_IABR1_ACTIVE34_M 0x00000004 -#define CPU_SCS_NVIC_IABR1_ACTIVE34_S 2 - -// Field: [1] ACTIVE33 -// -// Reading 0 from this bit implies that interrupt line 33 is not active. -// Reading 1 from this bit implies that the interrupt line 33 is active (See -// EVENT:CPUIRQSEL33.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE33 0x00000002 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_BITN 1 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_M 0x00000002 -#define CPU_SCS_NVIC_IABR1_ACTIVE33_S 1 - -// Field: [0] ACTIVE32 -// -// Reading 0 from this bit implies that interrupt line 32 is not active. -// Reading 1 from this bit implies that the interrupt line 32 is active (See -// EVENT:CPUIRQSEL32.EV for details). -#define CPU_SCS_NVIC_IABR1_ACTIVE32 0x00000001 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_BITN 0 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_M 0x00000001 -#define CPU_SCS_NVIC_IABR1_ACTIVE32_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR0 -// -//***************************************************************************** -// Field: [31:24] PRI_3 -// -// Priority of interrupt 3 (See EVENT:CPUIRQSEL3.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_3_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_3_M 0xFF000000 -#define CPU_SCS_NVIC_IPR0_PRI_3_S 24 - -// Field: [23:16] PRI_2 -// -// Priority of interrupt 2 (See EVENT:CPUIRQSEL2.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_2_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_2_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR0_PRI_2_S 16 - -// Field: [15:8] PRI_1 -// -// Priority of interrupt 1 (See EVENT:CPUIRQSEL1.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_1_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_1_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR0_PRI_1_S 8 - -// Field: [7:0] PRI_0 -// -// Priority of interrupt 0 (See EVENT:CPUIRQSEL0.EV for details). -#define CPU_SCS_NVIC_IPR0_PRI_0_W 8 -#define CPU_SCS_NVIC_IPR0_PRI_0_M 0x000000FF -#define CPU_SCS_NVIC_IPR0_PRI_0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR1 -// -//***************************************************************************** -// Field: [31:24] PRI_7 -// -// Priority of interrupt 7 (See EVENT:CPUIRQSEL7.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_7_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_7_M 0xFF000000 -#define CPU_SCS_NVIC_IPR1_PRI_7_S 24 - -// Field: [23:16] PRI_6 -// -// Priority of interrupt 6 (See EVENT:CPUIRQSEL6.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_6_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_6_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR1_PRI_6_S 16 - -// Field: [15:8] PRI_5 -// -// Priority of interrupt 5 (See EVENT:CPUIRQSEL5.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_5_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_5_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR1_PRI_5_S 8 - -// Field: [7:0] PRI_4 -// -// Priority of interrupt 4 (See EVENT:CPUIRQSEL4.EV for details). -#define CPU_SCS_NVIC_IPR1_PRI_4_W 8 -#define CPU_SCS_NVIC_IPR1_PRI_4_M 0x000000FF -#define CPU_SCS_NVIC_IPR1_PRI_4_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR2 -// -//***************************************************************************** -// Field: [31:24] PRI_11 -// -// Priority of interrupt 11 (See EVENT:CPUIRQSEL11.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_11_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_11_M 0xFF000000 -#define CPU_SCS_NVIC_IPR2_PRI_11_S 24 - -// Field: [23:16] PRI_10 -// -// Priority of interrupt 10 (See EVENT:CPUIRQSEL10.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_10_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_10_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR2_PRI_10_S 16 - -// Field: [15:8] PRI_9 -// -// Priority of interrupt 9 (See EVENT:CPUIRQSEL9.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_9_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_9_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR2_PRI_9_S 8 - -// Field: [7:0] PRI_8 -// -// Priority of interrupt 8 (See EVENT:CPUIRQSEL8.EV for details). -#define CPU_SCS_NVIC_IPR2_PRI_8_W 8 -#define CPU_SCS_NVIC_IPR2_PRI_8_M 0x000000FF -#define CPU_SCS_NVIC_IPR2_PRI_8_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR3 -// -//***************************************************************************** -// Field: [31:24] PRI_15 -// -// Priority of interrupt 15 (See EVENT:CPUIRQSEL15.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_15_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_15_M 0xFF000000 -#define CPU_SCS_NVIC_IPR3_PRI_15_S 24 - -// Field: [23:16] PRI_14 -// -// Priority of interrupt 14 (See EVENT:CPUIRQSEL14.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_14_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_14_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR3_PRI_14_S 16 - -// Field: [15:8] PRI_13 -// -// Priority of interrupt 13 (See EVENT:CPUIRQSEL13.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_13_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_13_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR3_PRI_13_S 8 - -// Field: [7:0] PRI_12 -// -// Priority of interrupt 12 (See EVENT:CPUIRQSEL12.EV for details). -#define CPU_SCS_NVIC_IPR3_PRI_12_W 8 -#define CPU_SCS_NVIC_IPR3_PRI_12_M 0x000000FF -#define CPU_SCS_NVIC_IPR3_PRI_12_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR4 -// -//***************************************************************************** -// Field: [31:24] PRI_19 -// -// Priority of interrupt 19 (See EVENT:CPUIRQSEL19.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_19_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_19_M 0xFF000000 -#define CPU_SCS_NVIC_IPR4_PRI_19_S 24 - -// Field: [23:16] PRI_18 -// -// Priority of interrupt 18 (See EVENT:CPUIRQSEL18.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_18_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_18_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR4_PRI_18_S 16 - -// Field: [15:8] PRI_17 -// -// Priority of interrupt 17 (See EVENT:CPUIRQSEL17.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_17_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_17_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR4_PRI_17_S 8 - -// Field: [7:0] PRI_16 -// -// Priority of interrupt 16 (See EVENT:CPUIRQSEL16.EV for details). -#define CPU_SCS_NVIC_IPR4_PRI_16_W 8 -#define CPU_SCS_NVIC_IPR4_PRI_16_M 0x000000FF -#define CPU_SCS_NVIC_IPR4_PRI_16_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR5 -// -//***************************************************************************** -// Field: [31:24] PRI_23 -// -// Priority of interrupt 23 (See EVENT:CPUIRQSEL23.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_23_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_23_M 0xFF000000 -#define CPU_SCS_NVIC_IPR5_PRI_23_S 24 - -// Field: [23:16] PRI_22 -// -// Priority of interrupt 22 (See EVENT:CPUIRQSEL22.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_22_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_22_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR5_PRI_22_S 16 - -// Field: [15:8] PRI_21 -// -// Priority of interrupt 21 (See EVENT:CPUIRQSEL21.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_21_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_21_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR5_PRI_21_S 8 - -// Field: [7:0] PRI_20 -// -// Priority of interrupt 20 (See EVENT:CPUIRQSEL20.EV for details). -#define CPU_SCS_NVIC_IPR5_PRI_20_W 8 -#define CPU_SCS_NVIC_IPR5_PRI_20_M 0x000000FF -#define CPU_SCS_NVIC_IPR5_PRI_20_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR6 -// -//***************************************************************************** -// Field: [31:24] PRI_27 -// -// Priority of interrupt 27 (See EVENT:CPUIRQSEL27.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_27_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_27_M 0xFF000000 -#define CPU_SCS_NVIC_IPR6_PRI_27_S 24 - -// Field: [23:16] PRI_26 -// -// Priority of interrupt 26 (See EVENT:CPUIRQSEL26.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_26_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_26_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR6_PRI_26_S 16 - -// Field: [15:8] PRI_25 -// -// Priority of interrupt 25 (See EVENT:CPUIRQSEL25.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_25_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_25_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR6_PRI_25_S 8 - -// Field: [7:0] PRI_24 -// -// Priority of interrupt 24 (See EVENT:CPUIRQSEL24.EV for details). -#define CPU_SCS_NVIC_IPR6_PRI_24_W 8 -#define CPU_SCS_NVIC_IPR6_PRI_24_M 0x000000FF -#define CPU_SCS_NVIC_IPR6_PRI_24_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR7 -// -//***************************************************************************** -// Field: [31:24] PRI_31 -// -// Priority of interrupt 31 (See EVENT:CPUIRQSEL31.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_31_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_31_M 0xFF000000 -#define CPU_SCS_NVIC_IPR7_PRI_31_S 24 - -// Field: [23:16] PRI_30 -// -// Priority of interrupt 30 (See EVENT:CPUIRQSEL30.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_30_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_30_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR7_PRI_30_S 16 - -// Field: [15:8] PRI_29 -// -// Priority of interrupt 29 (See EVENT:CPUIRQSEL29.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_29_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_29_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR7_PRI_29_S 8 - -// Field: [7:0] PRI_28 -// -// Priority of interrupt 28 (See EVENT:CPUIRQSEL28.EV for details). -#define CPU_SCS_NVIC_IPR7_PRI_28_W 8 -#define CPU_SCS_NVIC_IPR7_PRI_28_M 0x000000FF -#define CPU_SCS_NVIC_IPR7_PRI_28_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR8 -// -//***************************************************************************** -// Field: [31:24] PRI_35 -// -// Priority of interrupt 35 (See EVENT:CPUIRQSEL35.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_35_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_35_M 0xFF000000 -#define CPU_SCS_NVIC_IPR8_PRI_35_S 24 - -// Field: [23:16] PRI_34 -// -// Priority of interrupt 34 (See EVENT:CPUIRQSEL34.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_34_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_34_M 0x00FF0000 -#define CPU_SCS_NVIC_IPR8_PRI_34_S 16 - -// Field: [15:8] PRI_33 -// -// Priority of interrupt 33 (See EVENT:CPUIRQSEL33.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_33_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_33_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR8_PRI_33_S 8 - -// Field: [7:0] PRI_32 -// -// Priority of interrupt 32 (See EVENT:CPUIRQSEL32.EV for details). -#define CPU_SCS_NVIC_IPR8_PRI_32_W 8 -#define CPU_SCS_NVIC_IPR8_PRI_32_M 0x000000FF -#define CPU_SCS_NVIC_IPR8_PRI_32_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_NVIC_IPR9 -// -//***************************************************************************** -// Field: [15:8] PRI_37 -// -// Priority of interrupt 37 (See EVENT:CPUIRQSEL37.EV for details). -#define CPU_SCS_NVIC_IPR9_PRI_37_W 8 -#define CPU_SCS_NVIC_IPR9_PRI_37_M 0x0000FF00 -#define CPU_SCS_NVIC_IPR9_PRI_37_S 8 - -// Field: [7:0] PRI_36 -// -// Priority of interrupt 36 (See EVENT:CPUIRQSEL36.EV for details). -#define CPU_SCS_NVIC_IPR9_PRI_36_W 8 -#define CPU_SCS_NVIC_IPR9_PRI_36_M 0x000000FF -#define CPU_SCS_NVIC_IPR9_PRI_36_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_CPUID -// -//***************************************************************************** -// Field: [31:24] IMPLEMENTER -// -// Implementor code. -#define CPU_SCS_CPUID_IMPLEMENTER_W 8 -#define CPU_SCS_CPUID_IMPLEMENTER_M 0xFF000000 -#define CPU_SCS_CPUID_IMPLEMENTER_S 24 - -// Field: [23:20] VARIANT -// -// Implementation defined variant number. -#define CPU_SCS_CPUID_VARIANT_W 4 -#define CPU_SCS_CPUID_VARIANT_M 0x00F00000 -#define CPU_SCS_CPUID_VARIANT_S 20 - -// Field: [19:16] CONSTANT -// -// Reads as 0xF -#define CPU_SCS_CPUID_CONSTANT_W 4 -#define CPU_SCS_CPUID_CONSTANT_M 0x000F0000 -#define CPU_SCS_CPUID_CONSTANT_S 16 - -// Field: [15:4] PARTNO -// -// Number of processor within family. -#define CPU_SCS_CPUID_PARTNO_W 12 -#define CPU_SCS_CPUID_PARTNO_M 0x0000FFF0 -#define CPU_SCS_CPUID_PARTNO_S 4 - -// Field: [3:0] REVISION -// -// Implementation defined revision number. -#define CPU_SCS_CPUID_REVISION_W 4 -#define CPU_SCS_CPUID_REVISION_M 0x0000000F -#define CPU_SCS_CPUID_REVISION_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ICSR -// -//***************************************************************************** -// Field: [31] NMIPENDSET -// -// Set pending NMI bit. Setting this bit pends and activates an NMI. Because -// NMI is the highest-priority interrupt, it takes effect as soon as it -// registers. -// -// 0: No action -// 1: Set pending NMI -#define CPU_SCS_ICSR_NMIPENDSET 0x80000000 -#define CPU_SCS_ICSR_NMIPENDSET_BITN 31 -#define CPU_SCS_ICSR_NMIPENDSET_M 0x80000000 -#define CPU_SCS_ICSR_NMIPENDSET_S 31 - -// Field: [28] PENDSVSET -// -// Set pending pendSV bit. -// -// 0: No action -// 1: Set pending PendSV -#define CPU_SCS_ICSR_PENDSVSET 0x10000000 -#define CPU_SCS_ICSR_PENDSVSET_BITN 28 -#define CPU_SCS_ICSR_PENDSVSET_M 0x10000000 -#define CPU_SCS_ICSR_PENDSVSET_S 28 - -// Field: [27] PENDSVCLR -// -// Clear pending pendSV bit -// -// 0: No action -// 1: Clear pending pendSV -#define CPU_SCS_ICSR_PENDSVCLR 0x08000000 -#define CPU_SCS_ICSR_PENDSVCLR_BITN 27 -#define CPU_SCS_ICSR_PENDSVCLR_M 0x08000000 -#define CPU_SCS_ICSR_PENDSVCLR_S 27 - -// Field: [26] PENDSTSET -// -// Set a pending SysTick bit. -// -// 0: No action -// 1: Set pending SysTick -#define CPU_SCS_ICSR_PENDSTSET 0x04000000 -#define CPU_SCS_ICSR_PENDSTSET_BITN 26 -#define CPU_SCS_ICSR_PENDSTSET_M 0x04000000 -#define CPU_SCS_ICSR_PENDSTSET_S 26 - -// Field: [25] PENDSTCLR -// -// Clear pending SysTick bit -// -// 0: No action -// 1: Clear pending SysTick -#define CPU_SCS_ICSR_PENDSTCLR 0x02000000 -#define CPU_SCS_ICSR_PENDSTCLR_BITN 25 -#define CPU_SCS_ICSR_PENDSTCLR_M 0x02000000 -#define CPU_SCS_ICSR_PENDSTCLR_S 25 - -// Field: [23] ISRPREEMPT -// -// This field can only be used at debug time. It indicates that a pending -// interrupt is to be taken in the next running cycle. If DHCSR.C_MASKINTS= 0, -// the interrupt is serviced. -// -// 0: A pending exception is not serviced. -// 1: A pending exception is serviced on exit from the debug halt state -#define CPU_SCS_ICSR_ISRPREEMPT 0x00800000 -#define CPU_SCS_ICSR_ISRPREEMPT_BITN 23 -#define CPU_SCS_ICSR_ISRPREEMPT_M 0x00800000 -#define CPU_SCS_ICSR_ISRPREEMPT_S 23 - -// Field: [22] ISRPENDING -// -// Interrupt pending flag. Excludes NMI and faults. -// -// 0x0: Interrupt not pending -// 0x1: Interrupt pending -#define CPU_SCS_ICSR_ISRPENDING 0x00400000 -#define CPU_SCS_ICSR_ISRPENDING_BITN 22 -#define CPU_SCS_ICSR_ISRPENDING_M 0x00400000 -#define CPU_SCS_ICSR_ISRPENDING_S 22 - -// Field: [17:12] VECTPENDING -// -// Pending ISR number field. This field contains the interrupt number of the -// highest priority pending ISR. -#define CPU_SCS_ICSR_VECTPENDING_W 6 -#define CPU_SCS_ICSR_VECTPENDING_M 0x0003F000 -#define CPU_SCS_ICSR_VECTPENDING_S 12 - -// Field: [11] RETTOBASE -// -// Indicates whether there are preempted active exceptions: -// -// 0: There are preempted active exceptions to execute -// 1: There are no active exceptions, or the currently-executing exception is -// the only active exception. -#define CPU_SCS_ICSR_RETTOBASE 0x00000800 -#define CPU_SCS_ICSR_RETTOBASE_BITN 11 -#define CPU_SCS_ICSR_RETTOBASE_M 0x00000800 -#define CPU_SCS_ICSR_RETTOBASE_S 11 - -// Field: [8:0] VECTACTIVE -// -// Active ISR number field. Reset clears this field. -#define CPU_SCS_ICSR_VECTACTIVE_W 9 -#define CPU_SCS_ICSR_VECTACTIVE_M 0x000001FF -#define CPU_SCS_ICSR_VECTACTIVE_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_VTOR -// -//***************************************************************************** -// Field: [29:7] TBLOFF -// -// Bits 29 down to 7 of the vector table base offset. -#define CPU_SCS_VTOR_TBLOFF_W 23 -#define CPU_SCS_VTOR_TBLOFF_M 0x3FFFFF80 -#define CPU_SCS_VTOR_TBLOFF_S 7 - -//***************************************************************************** -// -// Register: CPU_SCS_O_AIRCR -// -//***************************************************************************** -// Field: [31:16] VECTKEY -// -// Register key. Writing to this register (AIRCR) requires 0x05FA in VECTKEY. -// Otherwise the write value is ignored. Read always returns 0xFA05. -#define CPU_SCS_AIRCR_VECTKEY_W 16 -#define CPU_SCS_AIRCR_VECTKEY_M 0xFFFF0000 -#define CPU_SCS_AIRCR_VECTKEY_S 16 - -// Field: [15] ENDIANESS -// -// Data endianness bit -// ENUMs: -// BIG Big endian -// LITTLE Little endian -#define CPU_SCS_AIRCR_ENDIANESS 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_BITN 15 -#define CPU_SCS_AIRCR_ENDIANESS_M 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_S 15 -#define CPU_SCS_AIRCR_ENDIANESS_BIG 0x00008000 -#define CPU_SCS_AIRCR_ENDIANESS_LITTLE 0x00000000 - -// Field: [10:8] PRIGROUP -// -// Interrupt priority grouping field. This field is a binary point position -// indicator for creating subpriorities for exceptions that share the same -// pre-emption level. It divides the PRI_n field in the Interrupt Priority -// Registers (NVIC_IPR0, NVIC_IPR1,..., and NVIC_IPR8) into a pre-emption -// level and a subpriority level. The binary point is a left-of value. This -// means that the PRIGROUP value represents a point starting at the left of the -// Least Significant Bit (LSB). The lowest value might not be 0 depending on -// the number of bits allocated for priorities, and implementation choices. -#define CPU_SCS_AIRCR_PRIGROUP_W 3 -#define CPU_SCS_AIRCR_PRIGROUP_M 0x00000700 -#define CPU_SCS_AIRCR_PRIGROUP_S 8 - -// Field: [2] SYSRESETREQ -// -// Requests a warm reset. Setting this bit does not prevent Halting Debug from -// running. -#define CPU_SCS_AIRCR_SYSRESETREQ 0x00000004 -#define CPU_SCS_AIRCR_SYSRESETREQ_BITN 2 -#define CPU_SCS_AIRCR_SYSRESETREQ_M 0x00000004 -#define CPU_SCS_AIRCR_SYSRESETREQ_S 2 - -// Field: [1] VECTCLRACTIVE -// -// Clears all active state information for active NMI, fault, and interrupts. -// It is the responsibility of the application to reinitialize the stack. This -// bit is for returning to a known state during debug. The bit self-clears. -// IPSR is not cleared by this operation. So, if used by an application, it -// must only be used at the base level of activation, or within a system -// handler whose active bit can be set. -#define CPU_SCS_AIRCR_VECTCLRACTIVE 0x00000002 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_BITN 1 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_M 0x00000002 -#define CPU_SCS_AIRCR_VECTCLRACTIVE_S 1 - -// Field: [0] VECTRESET -// -// System Reset bit. Resets the system, with the exception of debug components. -// This bit is reserved for debug use and can be written to 1 only when the -// core is halted. The bit self-clears. Writing this bit to 1 while core is not -// halted may result in unpredictable behavior. -#define CPU_SCS_AIRCR_VECTRESET 0x00000001 -#define CPU_SCS_AIRCR_VECTRESET_BITN 0 -#define CPU_SCS_AIRCR_VECTRESET_M 0x00000001 -#define CPU_SCS_AIRCR_VECTRESET_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_SCR -// -//***************************************************************************** -// Field: [4] SEVONPEND -// -// Send Event on Pending bit: -// -// 0: Only enabled interrupts or events can wakeup the processor, disabled -// interrupts are excluded -// 1: Enabled events and all interrupts, including disabled interrupts, can -// wakeup the processor. -// -// When an event or interrupt enters pending state, the event signal wakes up -// the processor from WFE. If -// the processor is not waiting for an event, the event is registered and -// affects the next WFE. -// The processor also wakes up on execution of an SEV instruction. -#define CPU_SCS_SCR_SEVONPEND 0x00000010 -#define CPU_SCS_SCR_SEVONPEND_BITN 4 -#define CPU_SCS_SCR_SEVONPEND_M 0x00000010 -#define CPU_SCS_SCR_SEVONPEND_S 4 - -// Field: [2] SLEEPDEEP -// -// Controls whether the processor uses sleep or deep sleep as its low power -// mode -// ENUMs: -// DEEPSLEEP Deep sleep -// SLEEP Sleep -#define CPU_SCS_SCR_SLEEPDEEP 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_BITN 2 -#define CPU_SCS_SCR_SLEEPDEEP_M 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_S 2 -#define CPU_SCS_SCR_SLEEPDEEP_DEEPSLEEP 0x00000004 -#define CPU_SCS_SCR_SLEEPDEEP_SLEEP 0x00000000 - -// Field: [1] SLEEPONEXIT -// -// Sleep on exit when returning from Handler mode to Thread mode. Enables -// interrupt driven applications to avoid returning to empty main application. -// -// 0: Do not sleep when returning to thread mode -// 1: Sleep on ISR exit -#define CPU_SCS_SCR_SLEEPONEXIT 0x00000002 -#define CPU_SCS_SCR_SLEEPONEXIT_BITN 1 -#define CPU_SCS_SCR_SLEEPONEXIT_M 0x00000002 -#define CPU_SCS_SCR_SLEEPONEXIT_S 1 - -//***************************************************************************** -// -// Register: CPU_SCS_O_CCR -// -//***************************************************************************** -// Field: [9] STKALIGN -// -// Stack alignment bit. -// -// 0: Only 4-byte alignment is guaranteed for the SP used prior to the -// exception on exception entry. -// 1: On exception entry, the SP used prior to the exception is adjusted to be -// 8-byte aligned and the context to restore it is saved. The SP is restored on -// the associated exception return. -#define CPU_SCS_CCR_STKALIGN 0x00000200 -#define CPU_SCS_CCR_STKALIGN_BITN 9 -#define CPU_SCS_CCR_STKALIGN_M 0x00000200 -#define CPU_SCS_CCR_STKALIGN_S 9 - -// Field: [8] BFHFNMIGN -// -// Enables handlers with priority -1 or -2 to ignore data BusFaults caused by -// load and store instructions. This applies to the HardFault, NMI, and -// FAULTMASK escalated handlers: -// -// 0: Data BusFaults caused by load and store instructions cause a lock-up -// 1: Data BusFaults caused by load and store instructions are ignored. -// -// Set this bit to 1 only when the handler and its data are in absolutely safe -// memory. The normal use -// of this bit is to probe system devices and bridges to detect problems. -#define CPU_SCS_CCR_BFHFNMIGN 0x00000100 -#define CPU_SCS_CCR_BFHFNMIGN_BITN 8 -#define CPU_SCS_CCR_BFHFNMIGN_M 0x00000100 -#define CPU_SCS_CCR_BFHFNMIGN_S 8 - -// Field: [4] DIV_0_TRP -// -// Enables faulting or halting when the processor executes an SDIV or UDIV -// instruction with a divisor of 0: -// -// 0: Do not trap divide by 0. In this mode, a divide by zero returns a -// quotient of 0. -// 1: Trap divide by 0. The relevant Usage Fault Status Register bit is -// CFSR.DIVBYZERO. -#define CPU_SCS_CCR_DIV_0_TRP 0x00000010 -#define CPU_SCS_CCR_DIV_0_TRP_BITN 4 -#define CPU_SCS_CCR_DIV_0_TRP_M 0x00000010 -#define CPU_SCS_CCR_DIV_0_TRP_S 4 - -// Field: [3] UNALIGN_TRP -// -// Enables unaligned access traps: -// -// 0: Do not trap unaligned halfword and word accesses -// 1: Trap unaligned halfword and word accesses. The relevant Usage Fault -// Status Register bit is CFSR.UNALIGNED. -// -// If this bit is set to 1, an unaligned access generates a UsageFault. -// Unaligned LDM, STM, LDRD, and STRD instructions always fault regardless of -// the value in UNALIGN_TRP. -#define CPU_SCS_CCR_UNALIGN_TRP 0x00000008 -#define CPU_SCS_CCR_UNALIGN_TRP_BITN 3 -#define CPU_SCS_CCR_UNALIGN_TRP_M 0x00000008 -#define CPU_SCS_CCR_UNALIGN_TRP_S 3 - -// Field: [1] USERSETMPEND -// -// Enables unprivileged software access to STIR: -// -// 0: User code is not allowed to write to the Software Trigger Interrupt -// register (STIR). -// 1: User code can write the Software Trigger Interrupt register (STIR) to -// trigger (pend) a Main exception, which is associated with the Main stack -// pointer. -#define CPU_SCS_CCR_USERSETMPEND 0x00000002 -#define CPU_SCS_CCR_USERSETMPEND_BITN 1 -#define CPU_SCS_CCR_USERSETMPEND_M 0x00000002 -#define CPU_SCS_CCR_USERSETMPEND_S 1 - -// Field: [0] NONBASETHREDENA -// -// Indicates how the processor enters Thread mode: -// -// 0: Processor can enter Thread mode only when no exception is active. -// 1: Processor can enter Thread mode from any level using the appropriate -// return value (EXC_RETURN). -// -// Exception returns occur when one of the following instructions loads a value -// of 0xFXXXXXXX into the PC while in Handler mode: -// - POP/LDM which includes loading the PC. -// - LDR with PC as a destination. -// - BX with any register. -// The value written to the PC is intercepted and is referred to as the -// EXC_RETURN value. -#define CPU_SCS_CCR_NONBASETHREDENA 0x00000001 -#define CPU_SCS_CCR_NONBASETHREDENA_BITN 0 -#define CPU_SCS_CCR_NONBASETHREDENA_M 0x00000001 -#define CPU_SCS_CCR_NONBASETHREDENA_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_SHPR1 -// -//***************************************************************************** -// Field: [23:16] PRI_6 -// -// Priority of system handler 6. UsageFault -#define CPU_SCS_SHPR1_PRI_6_W 8 -#define CPU_SCS_SHPR1_PRI_6_M 0x00FF0000 -#define CPU_SCS_SHPR1_PRI_6_S 16 - -// Field: [15:8] PRI_5 -// -// Priority of system handler 5: BusFault -#define CPU_SCS_SHPR1_PRI_5_W 8 -#define CPU_SCS_SHPR1_PRI_5_M 0x0000FF00 -#define CPU_SCS_SHPR1_PRI_5_S 8 - -// Field: [7:0] PRI_4 -// -// Priority of system handler 4: MemManage -#define CPU_SCS_SHPR1_PRI_4_W 8 -#define CPU_SCS_SHPR1_PRI_4_M 0x000000FF -#define CPU_SCS_SHPR1_PRI_4_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_SHPR2 -// -//***************************************************************************** -// Field: [31:24] PRI_11 -// -// Priority of system handler 11. SVCall -#define CPU_SCS_SHPR2_PRI_11_W 8 -#define CPU_SCS_SHPR2_PRI_11_M 0xFF000000 -#define CPU_SCS_SHPR2_PRI_11_S 24 - -//***************************************************************************** -// -// Register: CPU_SCS_O_SHPR3 -// -//***************************************************************************** -// Field: [31:24] PRI_15 -// -// Priority of system handler 15. SysTick exception -#define CPU_SCS_SHPR3_PRI_15_W 8 -#define CPU_SCS_SHPR3_PRI_15_M 0xFF000000 -#define CPU_SCS_SHPR3_PRI_15_S 24 - -// Field: [23:16] PRI_14 -// -// Priority of system handler 14. Pend SV -#define CPU_SCS_SHPR3_PRI_14_W 8 -#define CPU_SCS_SHPR3_PRI_14_M 0x00FF0000 -#define CPU_SCS_SHPR3_PRI_14_S 16 - -// Field: [7:0] PRI_12 -// -// Priority of system handler 12. Debug Monitor -#define CPU_SCS_SHPR3_PRI_12_W 8 -#define CPU_SCS_SHPR3_PRI_12_M 0x000000FF -#define CPU_SCS_SHPR3_PRI_12_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_SHCSR -// -//***************************************************************************** -// Field: [18] USGFAULTENA -// -// Usage fault system handler enable -// ENUMs: -// EN Exception enabled -// DIS Exception disabled -#define CPU_SCS_SHCSR_USGFAULTENA 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_BITN 18 -#define CPU_SCS_SHCSR_USGFAULTENA_M 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_S 18 -#define CPU_SCS_SHCSR_USGFAULTENA_EN 0x00040000 -#define CPU_SCS_SHCSR_USGFAULTENA_DIS 0x00000000 - -// Field: [17] BUSFAULTENA -// -// Bus fault system handler enable -// ENUMs: -// EN Exception enabled -// DIS Exception disabled -#define CPU_SCS_SHCSR_BUSFAULTENA 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_BITN 17 -#define CPU_SCS_SHCSR_BUSFAULTENA_M 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_S 17 -#define CPU_SCS_SHCSR_BUSFAULTENA_EN 0x00020000 -#define CPU_SCS_SHCSR_BUSFAULTENA_DIS 0x00000000 - -// Field: [16] MEMFAULTENA -// -// MemManage fault system handler enable -// ENUMs: -// EN Exception enabled -// DIS Exception disabled -#define CPU_SCS_SHCSR_MEMFAULTENA 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_BITN 16 -#define CPU_SCS_SHCSR_MEMFAULTENA_M 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_S 16 -#define CPU_SCS_SHCSR_MEMFAULTENA_EN 0x00010000 -#define CPU_SCS_SHCSR_MEMFAULTENA_DIS 0x00000000 - -// Field: [15] SVCALLPENDED -// -// SVCall pending -// ENUMs: -// PENDING Exception is pending. -// NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_SVCALLPENDED 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_BITN 15 -#define CPU_SCS_SHCSR_SVCALLPENDED_M 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_S 15 -#define CPU_SCS_SHCSR_SVCALLPENDED_PENDING 0x00008000 -#define CPU_SCS_SHCSR_SVCALLPENDED_NOTPENDING 0x00000000 - -// Field: [14] BUSFAULTPENDED -// -// BusFault pending -// ENUMs: -// PENDING Exception is pending. -// NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_BUSFAULTPENDED 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_BITN 14 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_M 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_S 14 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_PENDING 0x00004000 -#define CPU_SCS_SHCSR_BUSFAULTPENDED_NOTPENDING 0x00000000 - -// Field: [13] MEMFAULTPENDED -// -// MemManage exception pending -// ENUMs: -// PENDING Exception is pending. -// NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_MEMFAULTPENDED 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_BITN 13 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_M 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_S 13 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_PENDING 0x00002000 -#define CPU_SCS_SHCSR_MEMFAULTPENDED_NOTPENDING 0x00000000 - -// Field: [12] USGFAULTPENDED -// -// Usage fault pending -// ENUMs: -// PENDING Exception is pending. -// NOTPENDING Exception is not active -#define CPU_SCS_SHCSR_USGFAULTPENDED 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_BITN 12 -#define CPU_SCS_SHCSR_USGFAULTPENDED_M 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_S 12 -#define CPU_SCS_SHCSR_USGFAULTPENDED_PENDING 0x00001000 -#define CPU_SCS_SHCSR_USGFAULTPENDED_NOTPENDING 0x00000000 - -// Field: [11] SYSTICKACT -// -// SysTick active flag. -// -// 0x0: Not active -// 0x1: Active -// ENUMs: -// ACTIVE Exception is active -// NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_SYSTICKACT 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_BITN 11 -#define CPU_SCS_SHCSR_SYSTICKACT_M 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_S 11 -#define CPU_SCS_SHCSR_SYSTICKACT_ACTIVE 0x00000800 -#define CPU_SCS_SHCSR_SYSTICKACT_NOTACTIVE 0x00000000 - -// Field: [10] PENDSVACT -// -// PendSV active -// -// 0x0: Not active -// 0x1: Active -#define CPU_SCS_SHCSR_PENDSVACT 0x00000400 -#define CPU_SCS_SHCSR_PENDSVACT_BITN 10 -#define CPU_SCS_SHCSR_PENDSVACT_M 0x00000400 -#define CPU_SCS_SHCSR_PENDSVACT_S 10 - -// Field: [8] MONITORACT -// -// Debug monitor active -// ENUMs: -// ACTIVE Exception is active -// NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_MONITORACT 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_BITN 8 -#define CPU_SCS_SHCSR_MONITORACT_M 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_S 8 -#define CPU_SCS_SHCSR_MONITORACT_ACTIVE 0x00000100 -#define CPU_SCS_SHCSR_MONITORACT_NOTACTIVE 0x00000000 - -// Field: [7] SVCALLACT -// -// SVCall active -// ENUMs: -// ACTIVE Exception is active -// NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_SVCALLACT 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_BITN 7 -#define CPU_SCS_SHCSR_SVCALLACT_M 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_S 7 -#define CPU_SCS_SHCSR_SVCALLACT_ACTIVE 0x00000080 -#define CPU_SCS_SHCSR_SVCALLACT_NOTACTIVE 0x00000000 - -// Field: [3] USGFAULTACT -// -// UsageFault exception active -// ENUMs: -// ACTIVE Exception is active -// NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_USGFAULTACT 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_BITN 3 -#define CPU_SCS_SHCSR_USGFAULTACT_M 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_S 3 -#define CPU_SCS_SHCSR_USGFAULTACT_ACTIVE 0x00000008 -#define CPU_SCS_SHCSR_USGFAULTACT_NOTACTIVE 0x00000000 - -// Field: [1] BUSFAULTACT -// -// BusFault exception active -// ENUMs: -// ACTIVE Exception is active -// NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_BUSFAULTACT 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_BITN 1 -#define CPU_SCS_SHCSR_BUSFAULTACT_M 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_S 1 -#define CPU_SCS_SHCSR_BUSFAULTACT_ACTIVE 0x00000002 -#define CPU_SCS_SHCSR_BUSFAULTACT_NOTACTIVE 0x00000000 - -// Field: [0] MEMFAULTACT -// -// MemManage exception active -// ENUMs: -// ACTIVE Exception is active -// NOTACTIVE Exception is not active -#define CPU_SCS_SHCSR_MEMFAULTACT 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_BITN 0 -#define CPU_SCS_SHCSR_MEMFAULTACT_M 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_S 0 -#define CPU_SCS_SHCSR_MEMFAULTACT_ACTIVE 0x00000001 -#define CPU_SCS_SHCSR_MEMFAULTACT_NOTACTIVE 0x00000000 - -//***************************************************************************** -// -// Register: CPU_SCS_O_CFSR -// -//***************************************************************************** -// Field: [25] DIVBYZERO -// -// When CCR.DIV_0_TRP (see Configuration Control Register on page 8-26) is -// enabled and an SDIV or UDIV instruction is used with a divisor of 0, this -// fault occurs The instruction is executed and the return PC points to it. If -// CCR.DIV_0_TRP is not set, then the divide returns a quotient of 0. -#define CPU_SCS_CFSR_DIVBYZERO 0x02000000 -#define CPU_SCS_CFSR_DIVBYZERO_BITN 25 -#define CPU_SCS_CFSR_DIVBYZERO_M 0x02000000 -#define CPU_SCS_CFSR_DIVBYZERO_S 25 - -// Field: [24] UNALIGNED -// -// When CCR.UNALIGN_TRP is enabled, and there is an attempt to make an -// unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD -// instructions always fault irrespective of the setting of CCR.UNALIGN_TRP. -#define CPU_SCS_CFSR_UNALIGNED 0x01000000 -#define CPU_SCS_CFSR_UNALIGNED_BITN 24 -#define CPU_SCS_CFSR_UNALIGNED_M 0x01000000 -#define CPU_SCS_CFSR_UNALIGNED_S 24 - -// Field: [19] NOCP -// -// Attempt to use a coprocessor instruction. The processor does not support -// coprocessor instructions. -#define CPU_SCS_CFSR_NOCP 0x00080000 -#define CPU_SCS_CFSR_NOCP_BITN 19 -#define CPU_SCS_CFSR_NOCP_M 0x00080000 -#define CPU_SCS_CFSR_NOCP_S 19 - -// Field: [18] INVPC -// -// Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid -// context, invalid value. The return PC points to the instruction that tried -// to set the PC. -#define CPU_SCS_CFSR_INVPC 0x00040000 -#define CPU_SCS_CFSR_INVPC_BITN 18 -#define CPU_SCS_CFSR_INVPC_M 0x00040000 -#define CPU_SCS_CFSR_INVPC_S 18 - -// Field: [17] INVSTATE -// -// Indicates an attempt to execute in an invalid EPSR state (e.g. after a BX -// type instruction has changed state). This includes state change after entry -// to or return from exception, as well as from inter-working instructions. -// Return PC points to faulting instruction, with the invalid state. -#define CPU_SCS_CFSR_INVSTATE 0x00020000 -#define CPU_SCS_CFSR_INVSTATE_BITN 17 -#define CPU_SCS_CFSR_INVSTATE_M 0x00020000 -#define CPU_SCS_CFSR_INVSTATE_S 17 - -// Field: [16] UNDEFINSTR -// -// This bit is set when the processor attempts to execute an undefined -// instruction. This is an instruction that the processor cannot decode. The -// return PC points to the undefined instruction. -#define CPU_SCS_CFSR_UNDEFINSTR 0x00010000 -#define CPU_SCS_CFSR_UNDEFINSTR_BITN 16 -#define CPU_SCS_CFSR_UNDEFINSTR_M 0x00010000 -#define CPU_SCS_CFSR_UNDEFINSTR_S 16 - -// Field: [15] BFARVALID -// -// This bit is set if the Bus Fault Address Register (BFAR) contains a valid -// address. This is true after a bus fault where the address is known. Other -// faults can clear this bit, such as a Mem Manage fault occurring later. If a -// Bus fault occurs that is escalated to a Hard Fault because of priority, the -// Hard Fault handler must clear this bit. This prevents problems if returning -// to a stacked active Bus fault handler whose BFAR value has been overwritten. -#define CPU_SCS_CFSR_BFARVALID 0x00008000 -#define CPU_SCS_CFSR_BFARVALID_BITN 15 -#define CPU_SCS_CFSR_BFARVALID_M 0x00008000 -#define CPU_SCS_CFSR_BFARVALID_S 15 - -// Field: [12] STKERR -// -// Stacking from exception has caused one or more bus faults. The SP is still -// adjusted and the values in the context area on the stack might be incorrect. -// BFAR is not written. -#define CPU_SCS_CFSR_STKERR 0x00001000 -#define CPU_SCS_CFSR_STKERR_BITN 12 -#define CPU_SCS_CFSR_STKERR_M 0x00001000 -#define CPU_SCS_CFSR_STKERR_S 12 - -// Field: [11] UNSTKERR -// -// Unstack from exception return has caused one or more bus faults. This is -// chained to the handler, so that the original return stack is still present. -// SP is not adjusted from failing return and new save is not performed. BFAR -// is not written. -#define CPU_SCS_CFSR_UNSTKERR 0x00000800 -#define CPU_SCS_CFSR_UNSTKERR_BITN 11 -#define CPU_SCS_CFSR_UNSTKERR_M 0x00000800 -#define CPU_SCS_CFSR_UNSTKERR_S 11 - -// Field: [10] IMPRECISERR -// -// Imprecise data bus error. It is a BusFault, but the Return PC is not related -// to the causing instruction. This is not a synchronous fault. So, if detected -// when the priority of the current activation is higher than the Bus Fault, it -// only pends. Bus fault activates when returning to a lower priority -// activation. If a precise fault occurs before returning to a lower priority -// exception, the handler detects both IMPRECISERR set and one of the precise -// fault status bits set at the same time. BFAR is not written. -#define CPU_SCS_CFSR_IMPRECISERR 0x00000400 -#define CPU_SCS_CFSR_IMPRECISERR_BITN 10 -#define CPU_SCS_CFSR_IMPRECISERR_M 0x00000400 -#define CPU_SCS_CFSR_IMPRECISERR_S 10 - -// Field: [9] PRECISERR -// -// Precise data bus error return. -#define CPU_SCS_CFSR_PRECISERR 0x00000200 -#define CPU_SCS_CFSR_PRECISERR_BITN 9 -#define CPU_SCS_CFSR_PRECISERR_M 0x00000200 -#define CPU_SCS_CFSR_PRECISERR_S 9 - -// Field: [8] IBUSERR -// -// Instruction bus error flag. This flag is set by a prefetch error. The fault -// stops on the instruction, so if the error occurs under a branch shadow, no -// fault occurs. BFAR is not written. -#define CPU_SCS_CFSR_IBUSERR 0x00000100 -#define CPU_SCS_CFSR_IBUSERR_BITN 8 -#define CPU_SCS_CFSR_IBUSERR_M 0x00000100 -#define CPU_SCS_CFSR_IBUSERR_S 8 - -// Field: [7] MMARVALID -// -// Memory Manage Address Register (MMFAR) address valid flag. A later-arriving -// fault, such as a bus fault, can clear a memory manage fault.. If a MemManage -// fault occurs that is escalated to a Hard Fault because of priority, the Hard -// Fault handler must clear this bit. This prevents problems on return to a -// stacked active MemManage handler whose MMFAR value has been overwritten. -#define CPU_SCS_CFSR_MMARVALID 0x00000080 -#define CPU_SCS_CFSR_MMARVALID_BITN 7 -#define CPU_SCS_CFSR_MMARVALID_M 0x00000080 -#define CPU_SCS_CFSR_MMARVALID_S 7 - -// Field: [4] MSTKERR -// -// Stacking from exception has caused one or more access violations. The SP is -// still adjusted and the values in the context area on the stack might be -// incorrect. MMFAR is not written. -#define CPU_SCS_CFSR_MSTKERR 0x00000010 -#define CPU_SCS_CFSR_MSTKERR_BITN 4 -#define CPU_SCS_CFSR_MSTKERR_M 0x00000010 -#define CPU_SCS_CFSR_MSTKERR_S 4 - -// Field: [3] MUNSTKERR -// -// Unstack from exception return has caused one or more access violations. This -// is chained to the handler, so that the original return stack is still -// present. SP is not adjusted from failing return and new save is not -// performed. MMFAR is not written. -#define CPU_SCS_CFSR_MUNSTKERR 0x00000008 -#define CPU_SCS_CFSR_MUNSTKERR_BITN 3 -#define CPU_SCS_CFSR_MUNSTKERR_M 0x00000008 -#define CPU_SCS_CFSR_MUNSTKERR_S 3 - -// Field: [1] DACCVIOL -// -// Data access violation flag. Attempting to load or store at a location that -// does not permit the operation sets this flag. The return PC points to the -// faulting instruction. This error loads MMFAR with the address of the -// attempted access. -#define CPU_SCS_CFSR_DACCVIOL 0x00000002 -#define CPU_SCS_CFSR_DACCVIOL_BITN 1 -#define CPU_SCS_CFSR_DACCVIOL_M 0x00000002 -#define CPU_SCS_CFSR_DACCVIOL_S 1 - -// Field: [0] IACCVIOL -// -// Instruction access violation flag. Attempting to fetch an instruction from a -// location that does not permit execution sets this flag. This occurs on any -// access to an XN region, even when the MPU is disabled or not present. The -// return PC points to the faulting instruction. MMFAR is not written. -#define CPU_SCS_CFSR_IACCVIOL 0x00000001 -#define CPU_SCS_CFSR_IACCVIOL_BITN 0 -#define CPU_SCS_CFSR_IACCVIOL_M 0x00000001 -#define CPU_SCS_CFSR_IACCVIOL_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_HFSR -// -//***************************************************************************** -// Field: [31] DEBUGEVT -// -// This bit is set if there is a fault related to debug. This is only possible -// when halting debug is not enabled. For monitor enabled debug, it only -// happens for BKPT when the current priority is higher than the monitor. When -// both halting and monitor debug are disabled, it only happens for debug -// events that are not ignored (minimally, BKPT). The Debug Fault Status -// Register is updated. -#define CPU_SCS_HFSR_DEBUGEVT 0x80000000 -#define CPU_SCS_HFSR_DEBUGEVT_BITN 31 -#define CPU_SCS_HFSR_DEBUGEVT_M 0x80000000 -#define CPU_SCS_HFSR_DEBUGEVT_S 31 - -// Field: [30] FORCED -// -// Hard Fault activated because a Configurable Fault was received and cannot -// activate because of priority or because the Configurable Fault is disabled. -// The Hard Fault handler then has to read the other fault status registers to -// determine cause. -#define CPU_SCS_HFSR_FORCED 0x40000000 -#define CPU_SCS_HFSR_FORCED_BITN 30 -#define CPU_SCS_HFSR_FORCED_M 0x40000000 -#define CPU_SCS_HFSR_FORCED_S 30 - -// Field: [1] VECTTBL -// -// This bit is set if there is a fault because of vector table read on -// exception processing (Bus Fault). This case is always a Hard Fault. The -// return PC points to the pre-empted instruction. -#define CPU_SCS_HFSR_VECTTBL 0x00000002 -#define CPU_SCS_HFSR_VECTTBL_BITN 1 -#define CPU_SCS_HFSR_VECTTBL_M 0x00000002 -#define CPU_SCS_HFSR_VECTTBL_S 1 - -//***************************************************************************** -// -// Register: CPU_SCS_O_DFSR -// -//***************************************************************************** -// Field: [4] EXTERNAL -// -// External debug request flag. The processor stops on next instruction -// boundary. -// -// 0x0: External debug request signal not asserted -// 0x1: External debug request signal asserted -#define CPU_SCS_DFSR_EXTERNAL 0x00000010 -#define CPU_SCS_DFSR_EXTERNAL_BITN 4 -#define CPU_SCS_DFSR_EXTERNAL_M 0x00000010 -#define CPU_SCS_DFSR_EXTERNAL_S 4 - -// Field: [3] VCATCH -// -// Vector catch flag. When this flag is set, a flag in one of the local fault -// status registers is also set to indicate the type of fault. -// -// 0x0: No vector catch occurred -// 0x1: Vector catch occurred -#define CPU_SCS_DFSR_VCATCH 0x00000008 -#define CPU_SCS_DFSR_VCATCH_BITN 3 -#define CPU_SCS_DFSR_VCATCH_M 0x00000008 -#define CPU_SCS_DFSR_VCATCH_S 3 - -// Field: [2] DWTTRAP -// -// Data Watchpoint and Trace (DWT) flag. The processor stops at the current -// instruction or at the next instruction. -// -// 0x0: No DWT match -// 0x1: DWT match -#define CPU_SCS_DFSR_DWTTRAP 0x00000004 -#define CPU_SCS_DFSR_DWTTRAP_BITN 2 -#define CPU_SCS_DFSR_DWTTRAP_M 0x00000004 -#define CPU_SCS_DFSR_DWTTRAP_S 2 - -// Field: [1] BKPT -// -// BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, -// and also by normal code. Return PC points to breakpoint containing -// instruction. -// -// 0x0: No BKPT instruction execution -// 0x1: BKPT instruction execution -#define CPU_SCS_DFSR_BKPT 0x00000002 -#define CPU_SCS_DFSR_BKPT_BITN 1 -#define CPU_SCS_DFSR_BKPT_M 0x00000002 -#define CPU_SCS_DFSR_BKPT_S 1 - -// Field: [0] HALTED -// -// Halt request flag. The processor is halted on the next instruction. -// -// 0x0: No halt request -// 0x1: Halt requested by NVIC, including step -#define CPU_SCS_DFSR_HALTED 0x00000001 -#define CPU_SCS_DFSR_HALTED_BITN 0 -#define CPU_SCS_DFSR_HALTED_M 0x00000001 -#define CPU_SCS_DFSR_HALTED_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MMFAR -// -//***************************************************************************** -// Field: [31:0] ADDRESS -// -// Mem Manage fault address field. -// This field is the data address of a faulted load or store attempt. When an -// unaligned access faults, the address is the actual address that faulted. -// Because an access can be split into multiple parts, each aligned, this -// address can be any offset in the range of the requested size. Flags -// CFSR.IACCVIOL, CFSR.DACCVIOL ,CFSR.MUNSTKERR and CFSR.MSTKERR in combination -// with CFSR.MMARVALIDindicate the cause of the fault. -#define CPU_SCS_MMFAR_ADDRESS_W 32 -#define CPU_SCS_MMFAR_ADDRESS_M 0xFFFFFFFF -#define CPU_SCS_MMFAR_ADDRESS_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_BFAR -// -//***************************************************************************** -// Field: [31:0] ADDRESS -// -// Bus fault address field. This field is the data address of a faulted load or -// store attempt. When an unaligned access faults, the address is the address -// requested by the instruction, even if that is not the address that faulted. -// Flags CFSR.IBUSERR, CFSR.PRECISERR, CFSR.IMPRECISERR, CFSR.UNSTKERR and -// CFSR.STKERR in combination with CFSR.BFARVALID indicate the cause of the -// fault. -#define CPU_SCS_BFAR_ADDRESS_W 32 -#define CPU_SCS_BFAR_ADDRESS_M 0xFFFFFFFF -#define CPU_SCS_BFAR_ADDRESS_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_AFSR -// -//***************************************************************************** -// Field: [31:0] IMPDEF -// -// Implementation defined. The bits map directly onto the signal assignment to -// the auxiliary fault inputs. Tied to 0 -#define CPU_SCS_AFSR_IMPDEF_W 32 -#define CPU_SCS_AFSR_IMPDEF_M 0xFFFFFFFF -#define CPU_SCS_AFSR_IMPDEF_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_PFR0 -// -//***************************************************************************** -// Field: [7:4] STATE1 -// -// State1 (T-bit == 1) -// -// 0x0: N/A -// 0x1: N/A -// 0x2: Thumb-2 encoding with the 16-bit basic instructions plus 32-bit -// Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit -// instructions can be added using the appropriate instruction attribute, but -// other 32-bit basic instructions cannot.) -// 0x3: Thumb-2 encoding with all Thumb-2 basic instructions -#define CPU_SCS_ID_PFR0_STATE1_W 4 -#define CPU_SCS_ID_PFR0_STATE1_M 0x000000F0 -#define CPU_SCS_ID_PFR0_STATE1_S 4 - -// Field: [3:0] STATE0 -// -// State0 (T-bit == 0) -// -// 0x0: No ARM encoding -// 0x1: N/A -#define CPU_SCS_ID_PFR0_STATE0_W 4 -#define CPU_SCS_ID_PFR0_STATE0_M 0x0000000F -#define CPU_SCS_ID_PFR0_STATE0_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_PFR1 -// -//***************************************************************************** -// Field: [11:8] MICROCONTROLLER_PROGRAMMERS_MODEL -// -// Microcontroller programmer's model -// -// 0x0: Not supported -// 0x2: Two-stack support -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_W 4 -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_M 0x00000F00 -#define CPU_SCS_ID_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_S 8 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_DFR0 -// -//***************************************************************************** -// Field: [23:20] MICROCONTROLLER_DEBUG_MODEL -// -// Microcontroller Debug Model - memory mapped -// -// 0x0: Not supported -// 0x1: Microcontroller debug v1 (ITMv1 and DWTv1) -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_W 4 -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_M 0x00F00000 -#define CPU_SCS_ID_DFR0_MICROCONTROLLER_DEBUG_MODEL_S 20 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_AFR0 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_MMFR0 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_MMFR1 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_MMFR2 -// -//***************************************************************************** -// Field: [24] WAIT_FOR_INTERRUPT_STALLING -// -// wait for interrupt stalling -// -// 0x0: Not supported -// 0x1: Wait for interrupt supported -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING 0x01000000 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_BITN 24 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_M 0x01000000 -#define CPU_SCS_ID_MMFR2_WAIT_FOR_INTERRUPT_STALLING_S 24 - -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_MMFR3 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_ISAR0 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_ISAR1 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_ISAR2 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_ISAR3 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_ID_ISAR4 -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_CPACR -// -//***************************************************************************** -//***************************************************************************** -// -// Register: CPU_SCS_O_MPU_TYPE -// -//***************************************************************************** -// Field: [23:16] IREGION -// -// The processor core uses only a unified MPU, this field always reads 0x0. -#define CPU_SCS_MPU_TYPE_IREGION_W 8 -#define CPU_SCS_MPU_TYPE_IREGION_M 0x00FF0000 -#define CPU_SCS_MPU_TYPE_IREGION_S 16 - -// Field: [15:8] DREGION -// -// Number of supported MPU regions field. This field reads 0x08 indicating -// eight MPU regions. -#define CPU_SCS_MPU_TYPE_DREGION_W 8 -#define CPU_SCS_MPU_TYPE_DREGION_M 0x0000FF00 -#define CPU_SCS_MPU_TYPE_DREGION_S 8 - -// Field: [0] SEPARATE -// -// The processor core uses only a unified MPU, thus this field is always 0. -#define CPU_SCS_MPU_TYPE_SEPARATE 0x00000001 -#define CPU_SCS_MPU_TYPE_SEPARATE_BITN 0 -#define CPU_SCS_MPU_TYPE_SEPARATE_M 0x00000001 -#define CPU_SCS_MPU_TYPE_SEPARATE_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MPU_CTRL -// -//***************************************************************************** -// Field: [2] PRIVDEFENA -// -// This bit enables the default memory map for privileged access, as a -// background region, when the MPU is enabled. The background region acts as if -// it was region number 1 before any settable regions. Any region that is set -// up overlays this default map, and overrides it. If this bit is not set, the -// default memory map is disabled, and memory not covered by a region faults. -// This applies to memory type, Execute Never (XN), cache and shareable rules. -// However, this only applies to privileged mode (fetch and data access). User -// mode code faults unless a region has been set up for its code and data. When -// the MPU is disabled, the default map acts on both privileged and user mode -// code. XN and SO rules always apply to the system partition whether this -// enable is set or not. If the MPU is disabled, this bit is ignored. -#define CPU_SCS_MPU_CTRL_PRIVDEFENA 0x00000004 -#define CPU_SCS_MPU_CTRL_PRIVDEFENA_BITN 2 -#define CPU_SCS_MPU_CTRL_PRIVDEFENA_M 0x00000004 -#define CPU_SCS_MPU_CTRL_PRIVDEFENA_S 2 - -// Field: [1] HFNMIENA -// -// This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated -// handlers. If this bit and ENABLE are set, the MPU is enabled when in these -// handlers. If this bit is not set, the MPU is disabled when in these -// handlers, regardless of the value of ENABLE bit. If this bit is set and -// ENABLE is not set, behavior is unpredictable. -#define CPU_SCS_MPU_CTRL_HFNMIENA 0x00000002 -#define CPU_SCS_MPU_CTRL_HFNMIENA_BITN 1 -#define CPU_SCS_MPU_CTRL_HFNMIENA_M 0x00000002 -#define CPU_SCS_MPU_CTRL_HFNMIENA_S 1 - -// Field: [0] ENABLE -// -// Enable MPU -// -// 0: MPU disabled -// 1: MPU enabled -#define CPU_SCS_MPU_CTRL_ENABLE 0x00000001 -#define CPU_SCS_MPU_CTRL_ENABLE_BITN 0 -#define CPU_SCS_MPU_CTRL_ENABLE_M 0x00000001 -#define CPU_SCS_MPU_CTRL_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MPU_RNR -// -//***************************************************************************** -// Field: [7:0] REGION -// -// Region select field. -// This field selects the region to operate on when using the MPU_RASR and -// MPU_RBAR. It must be written first except when the address MPU_RBAR.VALID -// and MPU_RBAR.REGION fields are written, which overwrites this. -#define CPU_SCS_MPU_RNR_REGION_W 8 -#define CPU_SCS_MPU_RNR_REGION_M 0x000000FF -#define CPU_SCS_MPU_RNR_REGION_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MPU_RBAR -// -//***************************************************************************** -// Field: [31:5] ADDR -// -// Region base address field. -// The position of the LSB depends on the region size, so that the base address -// is aligned according to an even multiple of size. The power of 2 size -// specified by the SZENABLE field of the MPU Region Attribute and Size -// Register defines how many bits of base address are used. -#define CPU_SCS_MPU_RBAR_ADDR_W 27 -#define CPU_SCS_MPU_RBAR_ADDR_M 0xFFFFFFE0 -#define CPU_SCS_MPU_RBAR_ADDR_S 5 - -// Field: [4] VALID -// -// MPU region number valid: -// 0: MPU_RNR remains unchanged and is interpreted. -// 1: MPU_RNR is overwritten by REGION. -#define CPU_SCS_MPU_RBAR_VALID 0x00000010 -#define CPU_SCS_MPU_RBAR_VALID_BITN 4 -#define CPU_SCS_MPU_RBAR_VALID_M 0x00000010 -#define CPU_SCS_MPU_RBAR_VALID_S 4 - -// Field: [3:0] REGION -// -// MPU region override field -#define CPU_SCS_MPU_RBAR_REGION_W 4 -#define CPU_SCS_MPU_RBAR_REGION_M 0x0000000F -#define CPU_SCS_MPU_RBAR_REGION_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MPU_RASR -// -//***************************************************************************** -// Field: [28] XN -// -// Instruction access disable: -// 0: Enable instruction fetches -// 1: Disable instruction fetches -#define CPU_SCS_MPU_RASR_XN 0x10000000 -#define CPU_SCS_MPU_RASR_XN_BITN 28 -#define CPU_SCS_MPU_RASR_XN_M 0x10000000 -#define CPU_SCS_MPU_RASR_XN_S 28 - -// Field: [26:24] AP -// -// Data access permission: -// 0x0: Priviliged permissions: No access. User permissions: No access. -// 0x1: Priviliged permissions: Read-write. User permissions: No access. -// 0x2: Priviliged permissions: Read-write. User permissions: Read-only. -// 0x3: Priviliged permissions: Read-write. User permissions: Read-write. -// 0x4: Reserved -// 0x5: Priviliged permissions: Read-only. User permissions: No access. -// 0x6: Priviliged permissions: Read-only. User permissions: Read-only. -// 0x7: Priviliged permissions: Read-only. User permissions: Read-only. -#define CPU_SCS_MPU_RASR_AP_W 3 -#define CPU_SCS_MPU_RASR_AP_M 0x07000000 -#define CPU_SCS_MPU_RASR_AP_S 24 - -// Field: [21:19] TEX -// -// Type extension -#define CPU_SCS_MPU_RASR_TEX_W 3 -#define CPU_SCS_MPU_RASR_TEX_M 0x00380000 -#define CPU_SCS_MPU_RASR_TEX_S 19 - -// Field: [18] S -// -// Shareable bit: -// 0: Not shareable -// 1: Shareable -#define CPU_SCS_MPU_RASR_S 0x00040000 -#define CPU_SCS_MPU_RASR_S_BITN 18 -#define CPU_SCS_MPU_RASR_S_M 0x00040000 -#define CPU_SCS_MPU_RASR_S_S 18 - -// Field: [17] C -// -// Cacheable bit: -// 0: Not cacheable -// 1: Cacheable -#define CPU_SCS_MPU_RASR_C 0x00020000 -#define CPU_SCS_MPU_RASR_C_BITN 17 -#define CPU_SCS_MPU_RASR_C_M 0x00020000 -#define CPU_SCS_MPU_RASR_C_S 17 - -// Field: [16] B -// -// Bufferable bit: -// 0: Not bufferable -// 1: Bufferable -#define CPU_SCS_MPU_RASR_B 0x00010000 -#define CPU_SCS_MPU_RASR_B_BITN 16 -#define CPU_SCS_MPU_RASR_B_M 0x00010000 -#define CPU_SCS_MPU_RASR_B_S 16 - -// Field: [15:8] SRD -// -// Sub-Region Disable field: -// Setting a bit in this field disables the corresponding sub-region. Regions -// are split into eight equal-sized sub-regions. Sub-regions are not supported -// for region sizes of 128 bytes and less. -#define CPU_SCS_MPU_RASR_SRD_W 8 -#define CPU_SCS_MPU_RASR_SRD_M 0x0000FF00 -#define CPU_SCS_MPU_RASR_SRD_S 8 - -// Field: [5:1] SIZE -// -// MPU Protection Region Size Field: -// 0x04: 32B -// 0x05: 64B -// 0x06: 128B -// 0x07: 256B -// 0x08: 512B -// 0x09: 1KB -// 0x0A: 2KB -// 0x0B: 4KB -// 0x0C: 8KB -// 0x0D: 16KB -// 0x0E: 32KB -// 0x0F: 64KB -// 0x10: 128KB -// 0x11: 256KB -// 0x12: 512KB -// 0x13: 1MB -// 0x14: 2MB -// 0x15: 4MB -// 0x16: 8MB -// 0x17: 16MB -// 0x18: 32MB -// 0x19: 64MB -// 0x1A: 128MB -// 0x1B: 256MB -// 0x1C: 512MB -// 0x1D: 1GB -// 0x1E: 2GB -// 0x1F: 4GB -#define CPU_SCS_MPU_RASR_SIZE_W 5 -#define CPU_SCS_MPU_RASR_SIZE_M 0x0000003E -#define CPU_SCS_MPU_RASR_SIZE_S 1 - -// Field: [0] ENABLE -// -// Region enable bit: -// 0: Disable region -// 1: Enable region -#define CPU_SCS_MPU_RASR_ENABLE 0x00000001 -#define CPU_SCS_MPU_RASR_ENABLE_BITN 0 -#define CPU_SCS_MPU_RASR_ENABLE_M 0x00000001 -#define CPU_SCS_MPU_RASR_ENABLE_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MPU_RBAR_A1 -// -//***************************************************************************** -// Field: [31:0] MPU_RBAR_A1 -// -// Alias for MPU_RBAR -#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_W 32 -#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_M 0xFFFFFFFF -#define CPU_SCS_MPU_RBAR_A1_MPU_RBAR_A1_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MPU_RASR_A1 -// -//***************************************************************************** -// Field: [31:0] MPU_RASR_A1 -// -// Alias for MPU_RASR -#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_W 32 -#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_M 0xFFFFFFFF -#define CPU_SCS_MPU_RASR_A1_MPU_RASR_A1_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MPU_RBAR_A2 -// -//***************************************************************************** -// Field: [31:0] MPU_RBAR_A2 -// -// Alias for MPU_RBAR -#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_W 32 -#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_M 0xFFFFFFFF -#define CPU_SCS_MPU_RBAR_A2_MPU_RBAR_A2_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MPU_RASR_A2 -// -//***************************************************************************** -// Field: [31:0] MPU_RASR_A2 -// -// Alias for MPU_RASR -#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_W 32 -#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_M 0xFFFFFFFF -#define CPU_SCS_MPU_RASR_A2_MPU_RASR_A2_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MPU_RBAR_A3 -// -//***************************************************************************** -// Field: [31:0] MPU_RBAR_A3 -// -// Alias for MPU_RBAR -#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_W 32 -#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_M 0xFFFFFFFF -#define CPU_SCS_MPU_RBAR_A3_MPU_RBAR_A3_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MPU_RASR_A3 -// -//***************************************************************************** -// Field: [31:0] MPU_RASR_A3 -// -// Alias for MPU_RASR -#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_W 32 -#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_M 0xFFFFFFFF -#define CPU_SCS_MPU_RASR_A3_MPU_RASR_A3_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_DHCSR -// -//***************************************************************************** -// Field: [25] S_RESET_ST -// -// Indicates that the core has been reset, or is now being reset, since the -// last time this bit was read. This a sticky bit that clears on read. So, -// reading twice and getting 1 then 0 means it was reset in the past. Reading -// twice and getting 1 both times means that it is being reset now (held in -// reset still). -// When writing to this register, 0 must be written this bit-field, otherwise -// the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_RESET_ST 0x02000000 -#define CPU_SCS_DHCSR_S_RESET_ST_BITN 25 -#define CPU_SCS_DHCSR_S_RESET_ST_M 0x02000000 -#define CPU_SCS_DHCSR_S_RESET_ST_S 25 - -// Field: [24] S_RETIRE_ST -// -// Indicates that an instruction has completed since last read. This is a -// sticky bit that clears on read. This determines if the core is stalled on a -// load/store or fetch. -// When writing to this register, 0 must be written this bit-field, otherwise -// the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_RETIRE_ST 0x01000000 -#define CPU_SCS_DHCSR_S_RETIRE_ST_BITN 24 -#define CPU_SCS_DHCSR_S_RETIRE_ST_M 0x01000000 -#define CPU_SCS_DHCSR_S_RETIRE_ST_S 24 - -// Field: [19] S_LOCKUP -// -// Reads as one if the core is running (not halted) and a lockup condition is -// present. -// When writing to this register, 1 must be written this bit-field, otherwise -// the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_LOCKUP 0x00080000 -#define CPU_SCS_DHCSR_S_LOCKUP_BITN 19 -#define CPU_SCS_DHCSR_S_LOCKUP_M 0x00080000 -#define CPU_SCS_DHCSR_S_LOCKUP_S 19 - -// Field: [18] S_SLEEP -// -// Indicates that the core is sleeping (WFI, WFE, or **SLEEP-ON-EXIT**). Must -// use C_HALT to gain control or wait for interrupt to wake-up. -// When writing to this register, 1 must be written this bit-field, otherwise -// the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_SLEEP 0x00040000 -#define CPU_SCS_DHCSR_S_SLEEP_BITN 18 -#define CPU_SCS_DHCSR_S_SLEEP_M 0x00040000 -#define CPU_SCS_DHCSR_S_SLEEP_S 18 - -// Field: [17] S_HALT -// -// The core is in debug state when this bit is set. -// When writing to this register, 1 must be written this bit-field, otherwise -// the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_HALT 0x00020000 -#define CPU_SCS_DHCSR_S_HALT_BITN 17 -#define CPU_SCS_DHCSR_S_HALT_M 0x00020000 -#define CPU_SCS_DHCSR_S_HALT_S 17 - -// Field: [16] S_REGRDY -// -// Register Read/Write on the Debug Core Register Selector register is -// available. Last transfer is complete. -// When writing to this register, 1 must be written this bit-field, otherwise -// the write operation is ignored and no bits are written into the register. -#define CPU_SCS_DHCSR_S_REGRDY 0x00010000 -#define CPU_SCS_DHCSR_S_REGRDY_BITN 16 -#define CPU_SCS_DHCSR_S_REGRDY_M 0x00010000 -#define CPU_SCS_DHCSR_S_REGRDY_S 16 - -// Field: [5] C_SNAPSTALL -// -// If the core is stalled on a load/store operation the stall ceases and the -// instruction is forced to complete. This enables Halting debug to gain -// control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. -// The core reads S_RETIRE_ST as 0. This indicates that no instruction has -// advanced. This prevents misuse. The bus state is Unpredictable when this is -// used. S_RETIRE_ST can detect core stalls on load/store operations. -#define CPU_SCS_DHCSR_C_SNAPSTALL 0x00000020 -#define CPU_SCS_DHCSR_C_SNAPSTALL_BITN 5 -#define CPU_SCS_DHCSR_C_SNAPSTALL_M 0x00000020 -#define CPU_SCS_DHCSR_C_SNAPSTALL_S 5 - -// Field: [3] C_MASKINTS -// -// Mask interrupts when stepping or running in halted debug. This masking does -// not affect NMI, fault exceptions and SVC caused by execution of the -// instructions. This bit must only be modified when the processor is halted -// (S_HALT == 1). C_MASKINTS must be set or cleared before halt is released -// (i.e., the writes to set or clear C_MASKINTS and to set or clear C_HALT must -// be separate). Modifying C_MASKINTS while the system is running with halting -// debug support enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable -// behavior. -#define CPU_SCS_DHCSR_C_MASKINTS 0x00000008 -#define CPU_SCS_DHCSR_C_MASKINTS_BITN 3 -#define CPU_SCS_DHCSR_C_MASKINTS_M 0x00000008 -#define CPU_SCS_DHCSR_C_MASKINTS_S 3 - -// Field: [2] C_STEP -// -// Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. -// Must only be modified when the processor is halted (S_HALT == 1). -// Modifying C_STEP while the system is running with halting debug support -// enabled (C_DEBUGEN = 1, S_HALT = 0) may cause unpredictable behavior. -#define CPU_SCS_DHCSR_C_STEP 0x00000004 -#define CPU_SCS_DHCSR_C_STEP_BITN 2 -#define CPU_SCS_DHCSR_C_STEP_M 0x00000004 -#define CPU_SCS_DHCSR_C_STEP_S 2 - -// Field: [1] C_HALT -// -// Halts the core. This bit is set automatically when the core Halts. For -// example Breakpoint. This bit clears on core reset. -#define CPU_SCS_DHCSR_C_HALT 0x00000002 -#define CPU_SCS_DHCSR_C_HALT_BITN 1 -#define CPU_SCS_DHCSR_C_HALT_M 0x00000002 -#define CPU_SCS_DHCSR_C_HALT_S 1 - -// Field: [0] C_DEBUGEN -// -// Enables debug. This can only be written by AHB-AP and not by the core. It is -// ignored when written by the core, which cannot set or clear it. The core -// must write a 1 to it when writing C_HALT to halt itself. -// The values of C_HALT, C_STEP and C_MASKINTS are ignored by hardware when -// C_DEBUGEN = 0. The read values for C_HALT, C_STEP and C_MASKINTS fields will -// be unknown to software when C_DEBUGEN = 0. -#define CPU_SCS_DHCSR_C_DEBUGEN 0x00000001 -#define CPU_SCS_DHCSR_C_DEBUGEN_BITN 0 -#define CPU_SCS_DHCSR_C_DEBUGEN_M 0x00000001 -#define CPU_SCS_DHCSR_C_DEBUGEN_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_DCRSR -// -//***************************************************************************** -// Field: [16] REGWNR -// -// 1: Write -// 0: Read -#define CPU_SCS_DCRSR_REGWNR 0x00010000 -#define CPU_SCS_DCRSR_REGWNR_BITN 16 -#define CPU_SCS_DCRSR_REGWNR_M 0x00010000 -#define CPU_SCS_DCRSR_REGWNR_S 16 - -// Field: [4:0] REGSEL -// -// Register select -// -// 0x00: R0 -// 0x01: R1 -// 0x02: R2 -// 0x03: R3 -// 0x04: R4 -// 0x05: R5 -// 0x06: R6 -// 0x07: R7 -// 0x08: R8 -// 0x09: R9 -// 0x0A: R10 -// 0x0B: R11 -// 0x0C: R12 -// 0x0D: Current SP -// 0x0E: LR -// 0x0F: DebugReturnAddress -// 0x10: XPSR/flags, execution state information, and exception number -// 0x11: MSP (Main SP) -// 0x12: PSP (Process SP) -// 0x14: CONTROL<<24 | FAULTMASK<<16 | BASEPRI<<8 | PRIMASK -#define CPU_SCS_DCRSR_REGSEL_W 5 -#define CPU_SCS_DCRSR_REGSEL_M 0x0000001F -#define CPU_SCS_DCRSR_REGSEL_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_DCRDR -// -//***************************************************************************** -// Field: [31:0] DCRDR -// -// This register holds data for reading and writing registers to and from the -// processor. This is the data value written to the register selected by DCRSR. -// When the processor receives a request from DCRSR, this register is read or -// written by the processor using a normal load-store unit operation. If core -// register transfers are not being performed, software-based debug monitors -// can use this register for communication in non-halting debug. This enables -// flags and bits to acknowledge state and indicate if commands have been -// accepted to, replied to, or accepted and replied to. -#define CPU_SCS_DCRDR_DCRDR_W 32 -#define CPU_SCS_DCRDR_DCRDR_M 0xFFFFFFFF -#define CPU_SCS_DCRDR_DCRDR_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_DEMCR -// -//***************************************************************************** -// Field: [24] TRCENA -// -// This bit must be set to 1 to enable use of the trace and debug blocks: DWT, -// ITM, ETM and TPIU. This enables control of power usage unless tracing is -// required. The application can enable this, for ITM use, or use by a -// debugger. -#define CPU_SCS_DEMCR_TRCENA 0x01000000 -#define CPU_SCS_DEMCR_TRCENA_BITN 24 -#define CPU_SCS_DEMCR_TRCENA_M 0x01000000 -#define CPU_SCS_DEMCR_TRCENA_S 24 - -// Field: [19] MON_REQ -// -// This enables the monitor to identify how it wakes up. This bit clears on a -// Core Reset. -// -// 0x0: Woken up by debug exception. -// 0x1: Woken up by MON_PEND -#define CPU_SCS_DEMCR_MON_REQ 0x00080000 -#define CPU_SCS_DEMCR_MON_REQ_BITN 19 -#define CPU_SCS_DEMCR_MON_REQ_M 0x00080000 -#define CPU_SCS_DEMCR_MON_REQ_S 19 - -// Field: [18] MON_STEP -// -// When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. -// This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped -// according to the priority of the monitor and settings of PRIMASK, FAULTMASK, -// or BASEPRI. -#define CPU_SCS_DEMCR_MON_STEP 0x00040000 -#define CPU_SCS_DEMCR_MON_STEP_BITN 18 -#define CPU_SCS_DEMCR_MON_STEP_M 0x00040000 -#define CPU_SCS_DEMCR_MON_STEP_S 18 - -// Field: [17] MON_PEND -// -// Pend the monitor to activate when priority permits. This can wake up the -// monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for -// Monitor debug. This register does not reset on a system reset. It is only -// reset by a power-on reset. Software in the reset handler or later, or by the -// DAP must enable the debug monitor. -#define CPU_SCS_DEMCR_MON_PEND 0x00020000 -#define CPU_SCS_DEMCR_MON_PEND_BITN 17 -#define CPU_SCS_DEMCR_MON_PEND_M 0x00020000 -#define CPU_SCS_DEMCR_MON_PEND_S 17 - -// Field: [16] MON_EN -// -// Enable the debug monitor. -// When enabled, the System handler priority register controls its priority -// level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN -// overrides this bit. Vector catching is semi-synchronous. When a matching -// event is seen, a Halt is requested. Because the processor can only halt on -// an instruction boundary, it must wait until the next instruction boundary. -// As a result, it stops on the first instruction of the exception handler. -// However, two special cases exist when a vector catch has triggered: 1. If a -// fault is taken during vectoring, vector read or stack push error, the halt -// occurs on the corresponding fault handler, for the vector error or stack -// push. 2. If a late arriving interrupt comes in during vectoring, it is not -// taken. That is, an implementation that supports the late arrival -// optimization must suppress it in this case. -#define CPU_SCS_DEMCR_MON_EN 0x00010000 -#define CPU_SCS_DEMCR_MON_EN_BITN 16 -#define CPU_SCS_DEMCR_MON_EN_M 0x00010000 -#define CPU_SCS_DEMCR_MON_EN_S 16 - -// Field: [10] VC_HARDERR -// -// Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_HARDERR 0x00000400 -#define CPU_SCS_DEMCR_VC_HARDERR_BITN 10 -#define CPU_SCS_DEMCR_VC_HARDERR_M 0x00000400 -#define CPU_SCS_DEMCR_VC_HARDERR_S 10 - -// Field: [9] VC_INTERR -// -// Debug trap on a fault occurring during an exception entry or return -// sequence. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_INTERR 0x00000200 -#define CPU_SCS_DEMCR_VC_INTERR_BITN 9 -#define CPU_SCS_DEMCR_VC_INTERR_M 0x00000200 -#define CPU_SCS_DEMCR_VC_INTERR_S 9 - -// Field: [8] VC_BUSERR -// -// Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_BUSERR 0x00000100 -#define CPU_SCS_DEMCR_VC_BUSERR_BITN 8 -#define CPU_SCS_DEMCR_VC_BUSERR_M 0x00000100 -#define CPU_SCS_DEMCR_VC_BUSERR_S 8 - -// Field: [7] VC_STATERR -// -// Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is -// cleared. -#define CPU_SCS_DEMCR_VC_STATERR 0x00000080 -#define CPU_SCS_DEMCR_VC_STATERR_BITN 7 -#define CPU_SCS_DEMCR_VC_STATERR_M 0x00000080 -#define CPU_SCS_DEMCR_VC_STATERR_S 7 - -// Field: [6] VC_CHKERR -// -// Debug trap on Usage Fault enabled checking errors. Ignored when -// DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_CHKERR 0x00000040 -#define CPU_SCS_DEMCR_VC_CHKERR_BITN 6 -#define CPU_SCS_DEMCR_VC_CHKERR_M 0x00000040 -#define CPU_SCS_DEMCR_VC_CHKERR_S 6 - -// Field: [5] VC_NOCPERR -// -// Debug trap on a UsageFault access to a Coprocessor. Ignored when -// DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_NOCPERR 0x00000020 -#define CPU_SCS_DEMCR_VC_NOCPERR_BITN 5 -#define CPU_SCS_DEMCR_VC_NOCPERR_M 0x00000020 -#define CPU_SCS_DEMCR_VC_NOCPERR_S 5 - -// Field: [4] VC_MMERR -// -// Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is -// cleared. -#define CPU_SCS_DEMCR_VC_MMERR 0x00000010 -#define CPU_SCS_DEMCR_VC_MMERR_BITN 4 -#define CPU_SCS_DEMCR_VC_MMERR_M 0x00000010 -#define CPU_SCS_DEMCR_VC_MMERR_S 4 - -// Field: [0] VC_CORERESET -// -// Reset Vector Catch. Halt running system if Core reset occurs. Ignored when -// DHCSR.C_DEBUGEN is cleared. -#define CPU_SCS_DEMCR_VC_CORERESET 0x00000001 -#define CPU_SCS_DEMCR_VC_CORERESET_BITN 0 -#define CPU_SCS_DEMCR_VC_CORERESET_M 0x00000001 -#define CPU_SCS_DEMCR_VC_CORERESET_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_STIR -// -//***************************************************************************** -// Field: [8:0] INTID -// -// Interrupt ID field. Writing a value to this bit-field is the same as -// manually pending an interrupt by setting the corresponding interrupt bit in -// an Interrupt Set Pending Register in NVIC_ISPR0 or NVIC_ISPR1. -#define CPU_SCS_STIR_INTID_W 9 -#define CPU_SCS_STIR_INTID_M 0x000001FF -#define CPU_SCS_STIR_INTID_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_FPCCR -// -//***************************************************************************** -// Field: [31] ASPEN -// -// Automatic State Preservation enable. -// When this bit is set is will cause bit [2] of the Special CONTROL register -// to be set (FPCA) on execution of a floating point instruction which results -// in the floating point state automatically being preserved on exception -// entry. -#define CPU_SCS_FPCCR_ASPEN 0x80000000 -#define CPU_SCS_FPCCR_ASPEN_BITN 31 -#define CPU_SCS_FPCCR_ASPEN_M 0x80000000 -#define CPU_SCS_FPCCR_ASPEN_S 31 - -// Field: [30] LSPEN -// -// Lazy State Preservation enable. -// Lazy state preservation is when the processor performs a context save, space -// on the stack is reserved for the floating point state but it is not stacked -// until the new context performs a floating point operation. -// 0: Disable automatic lazy state preservation for floating-point context. -// 1: Enable automatic lazy state preservation for floating-point context. -#define CPU_SCS_FPCCR_LSPEN 0x40000000 -#define CPU_SCS_FPCCR_LSPEN_BITN 30 -#define CPU_SCS_FPCCR_LSPEN_M 0x40000000 -#define CPU_SCS_FPCCR_LSPEN_S 30 - -// Field: [8] MONRDY -// -// Indicates whether the the software executing when the processor allocated -// the FP stack frame was able to set the DebugMonitor exception to pending. -// 0: DebugMonitor is disabled or priority did not permit setting -// DEMCR.MON_PEND when the floating-point stack frame was allocated. -// 1: DebugMonitor is enabled and priority permits setting DEMCR.MON_PEND when -// the floating-point stack frame was allocated. -#define CPU_SCS_FPCCR_MONRDY 0x00000100 -#define CPU_SCS_FPCCR_MONRDY_BITN 8 -#define CPU_SCS_FPCCR_MONRDY_M 0x00000100 -#define CPU_SCS_FPCCR_MONRDY_S 8 - -// Field: [6] BFRDY -// -// Indicates whether the software executing when the processor allocated the FP -// stack frame was able to set the BusFault exception to pending. -// 0: BusFault is disabled or priority did not permit setting the BusFault -// handler to the pending state when the floating-point stack frame was -// allocated. -// 1: BusFault is enabled and priority permitted setting the BusFault handler -// to the pending state when the floating-point stack frame was allocated. -#define CPU_SCS_FPCCR_BFRDY 0x00000040 -#define CPU_SCS_FPCCR_BFRDY_BITN 6 -#define CPU_SCS_FPCCR_BFRDY_M 0x00000040 -#define CPU_SCS_FPCCR_BFRDY_S 6 - -// Field: [5] MMRDY -// -// Indicates whether the software executing when the processor allocated the FP -// stack frame was able to set the MemManage exception to pending. -// 0: MemManage is disabled or priority did not permit setting the MemManage -// handler to the pending state when the floating-point stack frame was -// allocated. -// 1: MemManage is enabled and priority permitted setting the MemManage handler -// to the pending state when the floating-point stack frame was allocated. -#define CPU_SCS_FPCCR_MMRDY 0x00000020 -#define CPU_SCS_FPCCR_MMRDY_BITN 5 -#define CPU_SCS_FPCCR_MMRDY_M 0x00000020 -#define CPU_SCS_FPCCR_MMRDY_S 5 - -// Field: [4] HFRDY -// -// Indicates whether the software executing when the processor allocated the FP -// stack frame was able to set the HardFault exception to pending. -// 0: Priority did not permit setting the HardFault handler to the pending -// state when the floating-point stack frame was allocated. -// 1: Priority permitted setting the HardFault handler to the pending state -// when the floating-point stack frame was allocated. -#define CPU_SCS_FPCCR_HFRDY 0x00000010 -#define CPU_SCS_FPCCR_HFRDY_BITN 4 -#define CPU_SCS_FPCCR_HFRDY_M 0x00000010 -#define CPU_SCS_FPCCR_HFRDY_S 4 - -// Field: [3] THREAD -// -// Indicates the processor mode was Thread when it allocated the FP stack -// frame. -// 0: Mode was not Thread Mode when the floating-point stack frame was -// allocated. -// 1: Mode was Thread Mode when the floating-point stack frame was allocated. -#define CPU_SCS_FPCCR_THREAD 0x00000008 -#define CPU_SCS_FPCCR_THREAD_BITN 3 -#define CPU_SCS_FPCCR_THREAD_M 0x00000008 -#define CPU_SCS_FPCCR_THREAD_S 3 - -// Field: [1] USER -// -// Indicates the privilege level of the software executing was User -// (Unpriviledged) when the processor allocated the FP stack frame: -// 0: Privilege level was not user when the floating-point stack frame was -// allocated. -// 1: Privilege level was user when the floating-point stack frame was -// allocated. -#define CPU_SCS_FPCCR_USER 0x00000002 -#define CPU_SCS_FPCCR_USER_BITN 1 -#define CPU_SCS_FPCCR_USER_M 0x00000002 -#define CPU_SCS_FPCCR_USER_S 1 - -// Field: [0] LSPACT -// -// Indicates whether Lazy preservation of the FP state is active: -// 0: Lazy state preservation is not active. -// 1: Lazy state preservation is active. floating-point stack frame has been -// allocated but saving state to it has been deferred. -#define CPU_SCS_FPCCR_LSPACT 0x00000001 -#define CPU_SCS_FPCCR_LSPACT_BITN 0 -#define CPU_SCS_FPCCR_LSPACT_M 0x00000001 -#define CPU_SCS_FPCCR_LSPACT_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_FPCAR -// -//***************************************************************************** -// Field: [31:2] ADDRESS -// -// Holds the (double-word-aligned) location of the unpopulated floating-point -// register space allocated on an exception stack frame. -#define CPU_SCS_FPCAR_ADDRESS_W 30 -#define CPU_SCS_FPCAR_ADDRESS_M 0xFFFFFFFC -#define CPU_SCS_FPCAR_ADDRESS_S 2 - -//***************************************************************************** -// -// Register: CPU_SCS_O_FPDSCR -// -//***************************************************************************** -// Field: [26] AHP -// -// Default value for Alternative Half Precision bit. (If this bit is set to 1 -// then Alternative half-precision format is selected). -#define CPU_SCS_FPDSCR_AHP 0x04000000 -#define CPU_SCS_FPDSCR_AHP_BITN 26 -#define CPU_SCS_FPDSCR_AHP_M 0x04000000 -#define CPU_SCS_FPDSCR_AHP_S 26 - -// Field: [25] DN -// -// Default value for Default NaN mode bit. (If this bit is set to 1 then any -// operation involving one or more NaNs returns the Default NaN). -#define CPU_SCS_FPDSCR_DN 0x02000000 -#define CPU_SCS_FPDSCR_DN_BITN 25 -#define CPU_SCS_FPDSCR_DN_M 0x02000000 -#define CPU_SCS_FPDSCR_DN_S 25 - -// Field: [24] FZ -// -// Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then -// Flush-to-zero mode is enabled). -#define CPU_SCS_FPDSCR_FZ 0x01000000 -#define CPU_SCS_FPDSCR_FZ_BITN 24 -#define CPU_SCS_FPDSCR_FZ_M 0x01000000 -#define CPU_SCS_FPDSCR_FZ_S 24 - -// Field: [23:22] RMODE -// -// Default value for Rounding Mode control field. (The encoding for this field -// is: -// 0b00 Round to Nearest (RN) mode -// 0b01 Round towards Plus Infinity (RP) mode -// 0b10 Round towards Minus Infinity (RM) mode -// 0b11 Round towards Zero (RZ) mode. -// The specified rounding mode is used by almost all floating-point -// instructions). -#define CPU_SCS_FPDSCR_RMODE_W 2 -#define CPU_SCS_FPDSCR_RMODE_M 0x00C00000 -#define CPU_SCS_FPDSCR_RMODE_S 22 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MVFR0 -// -//***************************************************************************** -// Field: [31:28] FP_ROUNDING_MODES -// -// Indicates the rounding modes supported by the FP floating-point hardware. -// The value of this field is: 0b0001 - all rounding modes supported. -#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_W 4 -#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_M 0xF0000000 -#define CPU_SCS_MVFR0_FP_ROUNDING_MODES_S 28 - -// Field: [27:24] SHORT_VECTORS -// -// Indicates the hardware support for FP short vectors. The value of this field -// is: 0b0000 - not supported. -#define CPU_SCS_MVFR0_SHORT_VECTORS_W 4 -#define CPU_SCS_MVFR0_SHORT_VECTORS_M 0x0F000000 -#define CPU_SCS_MVFR0_SHORT_VECTORS_S 24 - -// Field: [23:20] SQUARE_ROOT -// -// Indicates the hardware support for FP square root operations. The value of -// this field is: 0b0001 - supported. -#define CPU_SCS_MVFR0_SQUARE_ROOT_W 4 -#define CPU_SCS_MVFR0_SQUARE_ROOT_M 0x00F00000 -#define CPU_SCS_MVFR0_SQUARE_ROOT_S 20 - -// Field: [19:16] DIVIDE -// -// Indicates the hardware support for FP divide operations. The value of this -// field is: 0b0001 - supported. -#define CPU_SCS_MVFR0_DIVIDE_W 4 -#define CPU_SCS_MVFR0_DIVIDE_M 0x000F0000 -#define CPU_SCS_MVFR0_DIVIDE_S 16 - -// Field: [15:12] FP_EXCEPTION_TRAPPING -// -// Indicates whether the FP hardware implementation supports exception -// trapping. The value of this field is: 0b0000 - not supported. -#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_W 4 -#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_M 0x0000F000 -#define CPU_SCS_MVFR0_FP_EXCEPTION_TRAPPING_S 12 - -// Field: [11:8] DOUBLE_PRECISION -// -// Indicates the hardware support for FP double-precision operations. The value -// of this field is: 0b0000 - not supported. -#define CPU_SCS_MVFR0_DOUBLE_PRECISION_W 4 -#define CPU_SCS_MVFR0_DOUBLE_PRECISION_M 0x00000F00 -#define CPU_SCS_MVFR0_DOUBLE_PRECISION_S 8 - -// Field: [7:4] SINGLE_PRECISION -// -// Indicates the hardware support for FP single-precision operations. The value -// of this field is: 0b0010 - supported. -#define CPU_SCS_MVFR0_SINGLE_PRECISION_W 4 -#define CPU_SCS_MVFR0_SINGLE_PRECISION_M 0x000000F0 -#define CPU_SCS_MVFR0_SINGLE_PRECISION_S 4 - -// Field: [3:0] A_SIMD -// -// Indicates the size of the FP register bank. The value of this field is: -// 0b0001 - supported, 16 x 64-bit registers. -#define CPU_SCS_MVFR0_A_SIMD_W 4 -#define CPU_SCS_MVFR0_A_SIMD_M 0x0000000F -#define CPU_SCS_MVFR0_A_SIMD_S 0 - -//***************************************************************************** -// -// Register: CPU_SCS_O_MVFR1 -// -//***************************************************************************** -// Field: [31:28] FP_FUSED_MAC -// -// Indicates whether the FP supports fused multiply accumulate operations. The -// value of this field is: 0b0001 - supported. -#define CPU_SCS_MVFR1_FP_FUSED_MAC_W 4 -#define CPU_SCS_MVFR1_FP_FUSED_MAC_M 0xF0000000 -#define CPU_SCS_MVFR1_FP_FUSED_MAC_S 28 - -// Field: [27:24] FP_HPFP -// -// Indicates whether the FP supports half-precision floating-point conversion -// operations. The value of this field is: 0b0001 - supported. -#define CPU_SCS_MVFR1_FP_HPFP_W 4 -#define CPU_SCS_MVFR1_FP_HPFP_M 0x0F000000 -#define CPU_SCS_MVFR1_FP_HPFP_S 24 - -// Field: [7:4] D_NAN_MODE -// -// Indicates whether the FP hardware implementation supports only the Default -// NaN mode. The value of this field is: 0b0001 - hardware supports propagation -// of NaN values. -#define CPU_SCS_MVFR1_D_NAN_MODE_W 4 -#define CPU_SCS_MVFR1_D_NAN_MODE_M 0x000000F0 -#define CPU_SCS_MVFR1_D_NAN_MODE_S 4 - -// Field: [3:0] FTZ_MODE -// -// Indicates whether the FP hardware implementation supports only the -// Flush-to-Zero mode of operation. The value of this field is: 0b0001 - -// hardware supports full denormalized number arithmetic. -#define CPU_SCS_MVFR1_FTZ_MODE_W 4 -#define CPU_SCS_MVFR1_FTZ_MODE_M 0x0000000F -#define CPU_SCS_MVFR1_FTZ_MODE_S 0 - - -#endif // __CPU_SCS__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h deleted file mode 100644 index 29e314e16b6..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tiprop.h +++ /dev/null @@ -1,68 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_tiprop_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_TIPROP_H__ -#define __HW_CPU_TIPROP_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_TIPROP component -// -//***************************************************************************** -// Internal -#define CPU_TIPROP_O_TRACECLKMUX 0x00000FF8 - -//***************************************************************************** -// -// Register: CPU_TIPROP_O_TRACECLKMUX -// -//***************************************************************************** -// Field: [0] TRACECLK_N_SWV -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// TRACECLK Internal. Only to be used through TI provided API. -// SWV Internal. Only to be used through TI provided API. -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_BITN 0 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_M 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_S 0 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_TRACECLK 0x00000001 -#define CPU_TIPROP_TRACECLKMUX_TRACECLK_N_SWV_SWV 0x00000000 - - -#endif // __CPU_TIPROP__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h deleted file mode 100644 index 43c7c8e80aa..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_cpu_tpiu.h +++ /dev/null @@ -1,347 +0,0 @@ -/****************************************************************************** -* Filename: hw_cpu_tpiu_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CPU_TPIU_H__ -#define __HW_CPU_TPIU_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CPU_TPIU component -// -//***************************************************************************** -// Supported Sync Port Sizes -#define CPU_TPIU_O_SSPSR 0x00000000 - -// Current Sync Port Size -#define CPU_TPIU_O_CSPSR 0x00000004 - -// Async Clock Prescaler -#define CPU_TPIU_O_ACPR 0x00000010 - -// Selected Pin Protocol -#define CPU_TPIU_O_SPPR 0x000000F0 - -// Formatter and Flush Status -#define CPU_TPIU_O_FFSR 0x00000300 - -// Formatter and Flush Control -#define CPU_TPIU_O_FFCR 0x00000304 - -// Formatter Synchronization Counter -#define CPU_TPIU_O_FSCR 0x00000308 - -// Claim Tag Mask -#define CPU_TPIU_O_CLAIMMASK 0x00000FA0 - -// Claim Tag Set -#define CPU_TPIU_O_CLAIMSET 0x00000FA0 - -// Current Claim Tag -#define CPU_TPIU_O_CLAIMTAG 0x00000FA4 - -// Claim Tag Clear -#define CPU_TPIU_O_CLAIMCLR 0x00000FA4 - -// Device ID -#define CPU_TPIU_O_DEVID 0x00000FC8 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_SSPSR -// -//***************************************************************************** -// Field: [3] FOUR -// -// 4-bit port size support -// -// 0x0: Not supported -// 0x1: Supported -#define CPU_TPIU_SSPSR_FOUR 0x00000008 -#define CPU_TPIU_SSPSR_FOUR_BITN 3 -#define CPU_TPIU_SSPSR_FOUR_M 0x00000008 -#define CPU_TPIU_SSPSR_FOUR_S 3 - -// Field: [2] THREE -// -// 3-bit port size support -// -// 0x0: Not supported -// 0x1: Supported -#define CPU_TPIU_SSPSR_THREE 0x00000004 -#define CPU_TPIU_SSPSR_THREE_BITN 2 -#define CPU_TPIU_SSPSR_THREE_M 0x00000004 -#define CPU_TPIU_SSPSR_THREE_S 2 - -// Field: [1] TWO -// -// 2-bit port size support -// -// 0x0: Not supported -// 0x1: Supported -#define CPU_TPIU_SSPSR_TWO 0x00000002 -#define CPU_TPIU_SSPSR_TWO_BITN 1 -#define CPU_TPIU_SSPSR_TWO_M 0x00000002 -#define CPU_TPIU_SSPSR_TWO_S 1 - -// Field: [0] ONE -// -// 1-bit port size support -// -// 0x0: Not supported -// 0x1: Supported -#define CPU_TPIU_SSPSR_ONE 0x00000001 -#define CPU_TPIU_SSPSR_ONE_BITN 0 -#define CPU_TPIU_SSPSR_ONE_M 0x00000001 -#define CPU_TPIU_SSPSR_ONE_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_CSPSR -// -//***************************************************************************** -// Field: [3] FOUR -// -// 4-bit port enable -// Writing values with more than one bit set in CSPSR, or setting a bit that is -// not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_FOUR 0x00000008 -#define CPU_TPIU_CSPSR_FOUR_BITN 3 -#define CPU_TPIU_CSPSR_FOUR_M 0x00000008 -#define CPU_TPIU_CSPSR_FOUR_S 3 - -// Field: [2] THREE -// -// 3-bit port enable -// Writing values with more than one bit set in CSPSR, or setting a bit that is -// not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_THREE 0x00000004 -#define CPU_TPIU_CSPSR_THREE_BITN 2 -#define CPU_TPIU_CSPSR_THREE_M 0x00000004 -#define CPU_TPIU_CSPSR_THREE_S 2 - -// Field: [1] TWO -// -// 2-bit port enable -// Writing values with more than one bit set in CSPSR, or setting a bit that is -// not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_TWO 0x00000002 -#define CPU_TPIU_CSPSR_TWO_BITN 1 -#define CPU_TPIU_CSPSR_TWO_M 0x00000002 -#define CPU_TPIU_CSPSR_TWO_S 1 - -// Field: [0] ONE -// -// 1-bit port enable -// Writing values with more than one bit set in CSPSR, or setting a bit that is -// not indicated as supported in SSPSR can cause Unpredictable behavior. -#define CPU_TPIU_CSPSR_ONE 0x00000001 -#define CPU_TPIU_CSPSR_ONE_BITN 0 -#define CPU_TPIU_CSPSR_ONE_M 0x00000001 -#define CPU_TPIU_CSPSR_ONE_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_ACPR -// -//***************************************************************************** -// Field: [12:0] PRESCALER -// -// Divisor for input trace clock is (PRESCALER + 1). -#define CPU_TPIU_ACPR_PRESCALER_W 13 -#define CPU_TPIU_ACPR_PRESCALER_M 0x00001FFF -#define CPU_TPIU_ACPR_PRESCALER_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_SPPR -// -//***************************************************************************** -// Field: [1:0] PROTOCOL -// -// Trace output protocol -// ENUMs: -// SWO_NRZ SerialWire Output (NRZ) -// SWO_MANCHESTER SerialWire Output (Manchester). This is the reset -// value. -// TRACEPORT TracePort mode -#define CPU_TPIU_SPPR_PROTOCOL_W 2 -#define CPU_TPIU_SPPR_PROTOCOL_M 0x00000003 -#define CPU_TPIU_SPPR_PROTOCOL_S 0 -#define CPU_TPIU_SPPR_PROTOCOL_SWO_NRZ 0x00000002 -#define CPU_TPIU_SPPR_PROTOCOL_SWO_MANCHESTER 0x00000001 -#define CPU_TPIU_SPPR_PROTOCOL_TRACEPORT 0x00000000 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_FFSR -// -//***************************************************************************** -// Field: [3] FTNONSTOP -// -// 0: Formatter can be stopped -// 1: Formatter cannot be stopped -#define CPU_TPIU_FFSR_FTNONSTOP 0x00000008 -#define CPU_TPIU_FFSR_FTNONSTOP_BITN 3 -#define CPU_TPIU_FFSR_FTNONSTOP_M 0x00000008 -#define CPU_TPIU_FFSR_FTNONSTOP_S 3 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_FFCR -// -//***************************************************************************** -// Field: [8] TRIGIN -// -// Indicates that triggers are inserted when a trigger pin is asserted. -#define CPU_TPIU_FFCR_TRIGIN 0x00000100 -#define CPU_TPIU_FFCR_TRIGIN_BITN 8 -#define CPU_TPIU_FFCR_TRIGIN_M 0x00000100 -#define CPU_TPIU_FFCR_TRIGIN_S 8 - -// Field: [1] ENFCONT -// -// Enable continuous formatting: -// -// 0: Continuous formatting disabled -// 1: Continuous formatting enabled -#define CPU_TPIU_FFCR_ENFCONT 0x00000002 -#define CPU_TPIU_FFCR_ENFCONT_BITN 1 -#define CPU_TPIU_FFCR_ENFCONT_M 0x00000002 -#define CPU_TPIU_FFCR_ENFCONT_S 1 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_FSCR -// -//***************************************************************************** -// Field: [31:0] FSCR -// -// The global synchronization trigger is generated by the Program Counter (PC) -// Sampler block. This means that there is no synchronization counter in the -// TPIU. -#define CPU_TPIU_FSCR_FSCR_W 32 -#define CPU_TPIU_FSCR_FSCR_M 0xFFFFFFFF -#define CPU_TPIU_FSCR_FSCR_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_CLAIMMASK -// -//***************************************************************************** -// Field: [31:0] CLAIMMASK -// -// This register forms one half of the Claim Tag value. When reading this -// register returns the number of bits that can be set (each bit is considered -// separately): -// -// 0: This claim tag bit is not implemented -// 1: This claim tag bit is not implemented -// -// The behavior when writing to this register is described in CLAIMSET. -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_W 32 -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMMASK_CLAIMMASK_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_CLAIMSET -// -//***************************************************************************** -// Field: [31:0] CLAIMSET -// -// This register forms one half of the Claim Tag value. Writing to this -// location allows individual bits to be set (each bit is considered -// separately): -// -// 0: No effect -// 1: Set this bit in the claim tag -// -// The behavior when reading from this location is described in CLAIMMASK. -#define CPU_TPIU_CLAIMSET_CLAIMSET_W 32 -#define CPU_TPIU_CLAIMSET_CLAIMSET_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMSET_CLAIMSET_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_CLAIMTAG -// -//***************************************************************************** -// Field: [31:0] CLAIMTAG -// -// This register forms one half of the Claim Tag value. Reading this register -// returns the current Claim Tag value. -// Reading CLAIMMASK determines how many bits from this register must be used. -// -// The behavior when writing to this register is described in CLAIMCLR. -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_W 32 -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMTAG_CLAIMTAG_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_CLAIMCLR -// -//***************************************************************************** -// Field: [31:0] CLAIMCLR -// -// This register forms one half of the Claim Tag value. Writing to this -// location enables individual bits to be cleared (each bit is considered -// separately): -// -// 0: No effect -// 1: Clear this bit in the claim tag. -// -// The behavior when reading from this location is described in CLAIMTAG. -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_W 32 -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_M 0xFFFFFFFF -#define CPU_TPIU_CLAIMCLR_CLAIMCLR_S 0 - -//***************************************************************************** -// -// Register: CPU_TPIU_O_DEVID -// -//***************************************************************************** -// Field: [31:0] DEVID -// -// This field returns: 0xCA1 if there is an ETM present. 0xCA0 if there is no -// ETM present. -#define CPU_TPIU_DEVID_DEVID_W 32 -#define CPU_TPIU_DEVID_DEVID_M 0xFFFFFFFF -#define CPU_TPIU_DEVID_DEVID_S 0 - - -#endif // __CPU_TPIU__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h deleted file mode 100644 index 2952afda17e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_crypto.h +++ /dev/null @@ -1,3966 +0,0 @@ -/****************************************************************************** -* Filename: hw_crypto_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_CRYPTO_H__ -#define __HW_CRYPTO_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// CRYPTO component -// -//***************************************************************************** -// Channel 0 Control -#define CRYPTO_O_DMACH0CTL 0x00000000 - -// Channel 0 External Address -#define CRYPTO_O_DMACH0EXTADDR 0x00000004 - -// Channel 0 DMA Length -#define CRYPTO_O_DMACH0LEN 0x0000000C - -// DMAC Status -#define CRYPTO_O_DMASTAT 0x00000018 - -// DMAC Software Reset -#define CRYPTO_O_DMASWRESET 0x0000001C - -// Channel 1 Control -#define CRYPTO_O_DMACH1CTL 0x00000020 - -// Channel 1 External Address -#define CRYPTO_O_DMACH1EXTADDR 0x00000024 - -// Channel 1 DMA Length -#define CRYPTO_O_DMACH1LEN 0x0000002C - -// DMAC Master Run-time Parameters -#define CRYPTO_O_DMABUSCFG 0x00000078 - -// DMAC Port Error Raw Status -#define CRYPTO_O_DMAPORTERR 0x0000007C - -// DMAC Version -#define CRYPTO_O_DMAHWVER 0x000000FC - -// Key Store Write Area -#define CRYPTO_O_KEYWRITEAREA 0x00000400 - -// Key Store Written Area -#define CRYPTO_O_KEYWRITTENAREA 0x00000404 - -// Key Store Size -#define CRYPTO_O_KEYSIZE 0x00000408 - -// Key Store Read Area -#define CRYPTO_O_KEYREADAREA 0x0000040C - -// AES_KEY2_0 / AES_GHASH_H_IN_0 -#define CRYPTO_O_AESKEY20 0x00000500 - -// AES_KEY2_0 / AES_GHASH_H_IN_0 -#define CRYPTO_O_AESKEY21 0x00000504 - -// AES_KEY2_0 / AES_GHASH_H_IN_0 -#define CRYPTO_O_AESKEY22 0x00000508 - -// AES_KEY2_0 / AES_GHASH_H_IN_0 -#define CRYPTO_O_AESKEY23 0x0000050C - -// AES_KEY3_0 / AES_KEY2_4 -#define CRYPTO_O_AESKEY30 0x00000510 - -// AES_KEY3_0 / AES_KEY2_4 -#define CRYPTO_O_AESKEY31 0x00000514 - -// AES_KEY3_0 / AES_KEY2_4 -#define CRYPTO_O_AESKEY32 0x00000518 - -// AES_KEY3_0 / AES_KEY2_4 -#define CRYPTO_O_AESKEY33 0x0000051C - -// AES initialization vector registers -#define CRYPTO_O_AESIV0 0x00000540 - -// AES initialization vector registers -#define CRYPTO_O_AESIV1 0x00000544 - -// AES initialization vector registers -#define CRYPTO_O_AESIV2 0x00000548 - -// AES initialization vector registers -#define CRYPTO_O_AESIV3 0x0000054C - -// AES Control -#define CRYPTO_O_AESCTL 0x00000550 - -// AES Crypto Length 0 (LSW) -#define CRYPTO_O_AESDATALEN0 0x00000554 - -// AES Crypto Length 1 (MSW) -#define CRYPTO_O_AESDATALEN1 0x00000558 - -// AES Authentication Length -#define CRYPTO_O_AESAUTHLEN 0x0000055C - -// Data Input/Output -#define CRYPTO_O_AESDATAOUT0 0x00000560 - -// AES Data Input_Output 0 -#define CRYPTO_O_AESDATAIN0 0x00000560 - -// Data Input/Output -#define CRYPTO_O_AESDATAOUT1 0x00000564 - -// AES Data Input_Output 0 -#define CRYPTO_O_AESDATAIN1 0x00000564 - -// Data Input/Output -#define CRYPTO_O_AESDATAOUT2 0x00000568 - -// AES Data Input_Output 2 -#define CRYPTO_O_AESDATAIN2 0x00000568 - -// Data Input/Output -#define CRYPTO_O_AESDATAOUT3 0x0000056C - -// AES Data Input_Output 3 -#define CRYPTO_O_AESDATAIN3 0x0000056C - -// AES Tag Out 0 -#define CRYPTO_O_AESTAGOUT0 0x00000570 - -// AES Tag Out 0 -#define CRYPTO_O_AESTAGOUT1 0x00000574 - -// AES Tag Out 0 -#define CRYPTO_O_AESTAGOUT2 0x00000578 - -// AES Tag Out 0 -#define CRYPTO_O_AESTAGOUT3 0x0000057C - -// HASH Data Input 1 -#define CRYPTO_O_HASHDATAIN1 0x00000604 - -// HASH Data Input 2 -#define CRYPTO_O_HASHDATAIN2 0x00000608 - -// HASH Data Input 3 -#define CRYPTO_O_HASHDATAIN3 0x0000060C - -// HASH Data Input 4 -#define CRYPTO_O_HASHDATAIN4 0x00000610 - -// HASH Data Input 5 -#define CRYPTO_O_HASHDATAIN5 0x00000614 - -// HASH Data Input 6 -#define CRYPTO_O_HASHDATAIN6 0x00000618 - -// HASH Data Input 7 -#define CRYPTO_O_HASHDATAIN7 0x0000061C - -// HASH Data Input 8 -#define CRYPTO_O_HASHDATAIN8 0x00000620 - -// HASH Data Input 9 -#define CRYPTO_O_HASHDATAIN9 0x00000624 - -// HASH Data Input 10 -#define CRYPTO_O_HASHDATAIN10 0x00000628 - -// HASH Data Input 11 -#define CRYPTO_O_HASHDATAIN11 0x0000062C - -// HASH Data Input 12 -#define CRYPTO_O_HASHDATAIN12 0x00000630 - -// HASH Data Input 13 -#define CRYPTO_O_HASHDATAIN13 0x00000634 - -// HASH Data Input 14 -#define CRYPTO_O_HASHDATAIN14 0x00000638 - -// HASH Data Input 15 -#define CRYPTO_O_HASHDATAIN15 0x0000063C - -// HASH Data Input 16 -#define CRYPTO_O_HASHDATAIN16 0x00000640 - -// HASH Data Input 17 -#define CRYPTO_O_HASHDATAIN17 0x00000644 - -// HASH Data Input 18 -#define CRYPTO_O_HASHDATAIN18 0x00000648 - -// HASH Data Input 19 -#define CRYPTO_O_HASHDATAIN19 0x0000064C - -// HASH Data Input 20 -#define CRYPTO_O_HASHDATAIN20 0x00000650 - -// HASH Data Input 21 -#define CRYPTO_O_HASHDATAIN21 0x00000654 - -// HASH Data Input 22 -#define CRYPTO_O_HASHDATAIN22 0x00000658 - -// HASH Data Input 23 -#define CRYPTO_O_HASHDATAIN23 0x0000065C - -// HASH Data Input 24 -#define CRYPTO_O_HASHDATAIN24 0x00000660 - -// HASH Data Input 25 -#define CRYPTO_O_HASHDATAIN25 0x00000664 - -// HASH Data Input 26 -#define CRYPTO_O_HASHDATAIN26 0x00000668 - -// HASH Data Input 27 -#define CRYPTO_O_HASHDATAIN27 0x0000066C - -// HASH Data Input 28 -#define CRYPTO_O_HASHDATAIN28 0x00000670 - -// HASH Data Input 29 -#define CRYPTO_O_HASHDATAIN29 0x00000674 - -// HASH Data Input 30 -#define CRYPTO_O_HASHDATAIN30 0x00000678 - -// HASH Data Input 31 -#define CRYPTO_O_HASHDATAIN31 0x0000067C - -// HASH Input_Output Buffer Control -#define CRYPTO_O_HASHIOBUFCTRL 0x00000680 - -// HASH Mode -#define CRYPTO_O_HASHMODE 0x00000684 - -// HASH Input Length LSB -#define CRYPTO_O_HASHINLENL 0x00000688 - -// HASH Input Length MSB -#define CRYPTO_O_HASHINLENH 0x0000068C - -// HASH Digest A -#define CRYPTO_O_HASHDIGESTA 0x000006C0 - -// HASH Digest B -#define CRYPTO_O_HASHDIGESTB 0x000006C4 - -// HASH Digest C -#define CRYPTO_O_HASHDIGESTC 0x000006C8 - -// HASH Digest D -#define CRYPTO_O_HASHDIGESTD 0x000006CC - -// HASH Digest E -#define CRYPTO_O_HASHDIGESTE 0x000006D0 - -// HASH Digest F -#define CRYPTO_O_HASHDIGESTF 0x000006D4 - -// HASH Digest G -#define CRYPTO_O_HASHDIGESTG 0x000006D8 - -// HASH Digest H -#define CRYPTO_O_HASHDIGESTH 0x000006DC - -// HASH Digest I -#define CRYPTO_O_HASHDIGESTI 0x000006E0 - -// HASH Digest J -#define CRYPTO_O_HASHDIGESTJ 0x000006E4 - -// HASH Digest K -#define CRYPTO_O_HASHDIGESTK 0x000006E8 - -// HASH Digest L -#define CRYPTO_O_HASHDIGESTL 0x000006EC - -// HASH Digest M -#define CRYPTO_O_HASHDIGESTM 0x000006F0 - -// HASH Digest N -#define CRYPTO_O_HASHDIGESTN 0x000006F4 - -// HASH Digest 0 -#define CRYPTO_O_HASHDIGESTO 0x000006F8 - -// HASH Digest P -#define CRYPTO_O_HASHDIGESTP 0x000006FC - -// Algorithm Select -#define CRYPTO_O_ALGSEL 0x00000700 - -// DMA Protection Control -#define CRYPTO_O_DMAPROTCTL 0x00000704 - -// Software Reset -#define CRYPTO_O_SWRESET 0x00000740 - -// Control Interrupt Configuration -#define CRYPTO_O_IRQTYPE 0x00000780 - -// Control Interrupt Enable -#define CRYPTO_O_IRQEN 0x00000784 - -// Control Interrupt Clear -#define CRYPTO_O_IRQCLR 0x00000788 - -// Control Interrupt Set -#define CRYPTO_O_IRQSET 0x0000078C - -// Control Interrupt Status -#define CRYPTO_O_IRQSTAT 0x00000790 - -// Hardware Version -#define CRYPTO_O_HWVER 0x000007FC - -//***************************************************************************** -// -// Register: CRYPTO_O_DMACH0CTL -// -//***************************************************************************** -// Field: [1] PRIO -// -// Channel priority -// 0: Low -// 1: High -// If both channels have the same priority, access of the channels to the -// external port is arbitrated using the round robin scheme. If one channel has -// a high priority and another one low, the channel with the high priority is -// served first, in case of simultaneous access requests. -#define CRYPTO_DMACH0CTL_PRIO 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_BITN 1 -#define CRYPTO_DMACH0CTL_PRIO_M 0x00000002 -#define CRYPTO_DMACH0CTL_PRIO_S 1 - -// Field: [0] EN -// -// Channel enable -// 0: Disabled -// 1: Enable -// Note: Disabling an active channel interrupts the DMA operation. The ongoing -// block transfer completes, but no new transfers are requested. -#define CRYPTO_DMACH0CTL_EN 0x00000001 -#define CRYPTO_DMACH0CTL_EN_BITN 0 -#define CRYPTO_DMACH0CTL_EN_M 0x00000001 -#define CRYPTO_DMACH0CTL_EN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMACH0EXTADDR -// -//***************************************************************************** -// Field: [31:0] ADDR -// -// Channel external address value -// When read during operation, it holds the last updated external address after -// being sent to the master interface. Note: The crypto DMA copies out upto 3 -// bytes until it hits a word boundary, thus the address need not be word -// aligned. -#define CRYPTO_DMACH0EXTADDR_ADDR_W 32 -#define CRYPTO_DMACH0EXTADDR_ADDR_M 0xFFFFFFFF -#define CRYPTO_DMACH0EXTADDR_ADDR_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMACH0LEN -// -//***************************************************************************** -// Field: [15:0] DMALEN -// -// Channel DMA length in bytes -// During configuration, this register contains the DMA transfer length in -// bytes. During operation, it contains the last updated value of the DMA -// transfer length after being sent to the master interface. -// Note: Setting this register to a nonzero value starts the transfer if the -// channel is enabled. Therefore, this register must be written last when -// setting up a DMA channel. -#define CRYPTO_DMACH0LEN_DMALEN_W 16 -#define CRYPTO_DMACH0LEN_DMALEN_M 0x0000FFFF -#define CRYPTO_DMACH0LEN_DMALEN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMASTAT -// -//***************************************************************************** -// Field: [17] PORT_ERR -// -// Reflects possible transfer errors on the AHB port. -#define CRYPTO_DMASTAT_PORT_ERR 0x00020000 -#define CRYPTO_DMASTAT_PORT_ERR_BITN 17 -#define CRYPTO_DMASTAT_PORT_ERR_M 0x00020000 -#define CRYPTO_DMASTAT_PORT_ERR_S 17 - -// Field: [1] CH1_ACT -// -// A value of 1 indicates that channel 1 is active (DMA transfer on-going). -#define CRYPTO_DMASTAT_CH1_ACT 0x00000002 -#define CRYPTO_DMASTAT_CH1_ACT_BITN 1 -#define CRYPTO_DMASTAT_CH1_ACT_M 0x00000002 -#define CRYPTO_DMASTAT_CH1_ACT_S 1 - -// Field: [0] CH0_ACT -// -// A value of 1 indicates that channel 0 is active (DMA transfer on-going). -#define CRYPTO_DMASTAT_CH0_ACT 0x00000001 -#define CRYPTO_DMASTAT_CH0_ACT_BITN 0 -#define CRYPTO_DMASTAT_CH0_ACT_M 0x00000001 -#define CRYPTO_DMASTAT_CH0_ACT_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMASWRESET -// -//***************************************************************************** -// Field: [0] SWRES -// -// Software reset enable -// 0 : Disabled -// 1 : Enabled (self-cleared to 0) -// Completion of the software reset must be checked through the DMASTAT -#define CRYPTO_DMASWRESET_SWRES 0x00000001 -#define CRYPTO_DMASWRESET_SWRES_BITN 0 -#define CRYPTO_DMASWRESET_SWRES_M 0x00000001 -#define CRYPTO_DMASWRESET_SWRES_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMACH1CTL -// -//***************************************************************************** -// Field: [1] PRIO -// -// Channel priority -// 0: Low -// 1: High -// If both channels have the same priority, access of the channels to the -// external port is arbitrated using the round robin scheme. If one channel has -// a high priority and another one low, the channel with the high priority is -// served first, in case of simultaneous access requests. -#define CRYPTO_DMACH1CTL_PRIO 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_BITN 1 -#define CRYPTO_DMACH1CTL_PRIO_M 0x00000002 -#define CRYPTO_DMACH1CTL_PRIO_S 1 - -// Field: [0] EN -// -// Channel enable -// 0: Disabled -// 1: Enable -// Note: Disabling an active channel interrupts the DMA operation. The ongoing -// block transfer completes, but no new transfers are requested. -#define CRYPTO_DMACH1CTL_EN 0x00000001 -#define CRYPTO_DMACH1CTL_EN_BITN 0 -#define CRYPTO_DMACH1CTL_EN_M 0x00000001 -#define CRYPTO_DMACH1CTL_EN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMACH1EXTADDR -// -//***************************************************************************** -// Field: [31:0] ADDR -// -// Channel external address value. -// When read during operation, it holds the last updated external address after -// being sent to the master interface. Note: The crypto DMA copies out upto 3 -// bytes until it hits a word boundary, thus the address need not be word -// aligned. -#define CRYPTO_DMACH1EXTADDR_ADDR_W 32 -#define CRYPTO_DMACH1EXTADDR_ADDR_M 0xFFFFFFFF -#define CRYPTO_DMACH1EXTADDR_ADDR_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMACH1LEN -// -//***************************************************************************** -// Field: [15:0] DMALEN -// -// Channel DMA length in bytes. -// During configuration, this register contains the DMA transfer length in -// bytes. During operation, it contains the last updated value of the DMA -// transfer length after being sent to the master interface. -// Note: Setting this register to a nonzero value starts the transfer if the -// channel is enabled. Therefore, this register must be written last when -// setting up a DMA channel. -#define CRYPTO_DMACH1LEN_DMALEN_W 16 -#define CRYPTO_DMACH1LEN_DMALEN_M 0x0000FFFF -#define CRYPTO_DMACH1LEN_DMALEN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMABUSCFG -// -//***************************************************************************** -// Field: [15:12] AHB_MST1_BURST_SIZE -// -// Maximum burst size that can be performed on the AHB bus -// ENUMs: -// 64_BYTE 64 bytes -// 32_BYTE 32 bytes -// 16_BYTE 16 bytes -// 8_BYTE 8 bytes -// 4_BYTE 4 bytes -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_W 4 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_M 0x0000F000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_S 12 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_64_BYTE 0x00006000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_32_BYTE 0x00005000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_16_BYTE 0x00004000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_8_BYTE 0x00003000 -#define CRYPTO_DMABUSCFG_AHB_MST1_BURST_SIZE_4_BYTE 0x00002000 - -// Field: [11] AHB_MST1_IDLE_EN -// -// Idle insertion between consecutive burst transfers on AHB -// ENUMs: -// IDLE Idle transfer insertion enabled -// NO_IDLE Do not insert idle transfers. -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_BITN 11 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_M 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_S 11 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_IDLE 0x00000800 -#define CRYPTO_DMABUSCFG_AHB_MST1_IDLE_EN_NO_IDLE 0x00000000 - -// Field: [10] AHB_MST1_INCR_EN -// -// Burst length type of AHB transfer -// ENUMs: -// SPECIFIED Fixed length bursts or single transfers -// UNSPECIFIED Unspecified length burst transfers -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_BITN 10 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_M 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_S 10 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_SPECIFIED 0x00000400 -#define CRYPTO_DMABUSCFG_AHB_MST1_INCR_EN_UNSPECIFIED 0x00000000 - -// Field: [9] AHB_MST1_LOCK_EN -// -// Locked transform on AHB -// ENUMs: -// LOCKED Transfers are locked -// NOT_LOCKED Transfers are not locked -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_BITN 9 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_M 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_S 9 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_LOCKED 0x00000200 -#define CRYPTO_DMABUSCFG_AHB_MST1_LOCK_EN_NOT_LOCKED 0x00000000 - -// Field: [8] AHB_MST1_BIGEND -// -// Endianess for the AHB master -// ENUMs: -// BIG_ENDIAN Big Endian -// LITTLE_ENDIAN Little Endian -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BITN 8 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_M 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_S 8 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_BIG_ENDIAN 0x00000100 -#define CRYPTO_DMABUSCFG_AHB_MST1_BIGEND_LITTLE_ENDIAN 0x00000000 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMAPORTERR -// -//***************************************************************************** -// Field: [12] PORT1_AHB_ERROR -// -// A value of 1 indicates that the EIP-101 has detected an AHB bus error -#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR 0x00001000 -#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_BITN 12 -#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_M 0x00001000 -#define CRYPTO_DMAPORTERR_PORT1_AHB_ERROR_S 12 - -// Field: [9] PORT1_CHANNEL -// -// Indicates which channel has serviced last (channel 0 or channel 1) by AHB -// master port. -#define CRYPTO_DMAPORTERR_PORT1_CHANNEL 0x00000200 -#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_BITN 9 -#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_M 0x00000200 -#define CRYPTO_DMAPORTERR_PORT1_CHANNEL_S 9 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMAHWVER -// -//***************************************************************************** -// Field: [27:24] HW_MAJOR_VERSION -// -// Major version number -#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_W 4 -#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_M 0x0F000000 -#define CRYPTO_DMAHWVER_HW_MAJOR_VERSION_S 24 - -// Field: [23:20] HW_MINOR_VERSION -// -// Minor version number -#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_W 4 -#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_M 0x00F00000 -#define CRYPTO_DMAHWVER_HW_MINOR_VERSION_S 20 - -// Field: [19:16] HW_PATCH_LEVEL -// -// Patch level -// Starts at 0 at first delivery of this version -#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_W 4 -#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_M 0x000F0000 -#define CRYPTO_DMAHWVER_HW_PATCH_LEVEL_S 16 - -// Field: [15:8] EIP_NUMBER_COMPL -// -// Bit-by-bit complement of the EIP_NUMBER field bits. -#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_W 8 -#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_M 0x0000FF00 -#define CRYPTO_DMAHWVER_EIP_NUMBER_COMPL_S 8 - -// Field: [7:0] EIP_NUMBER -// -// Binary encoding of the EIP-number of this DMA controller (209) -#define CRYPTO_DMAHWVER_EIP_NUMBER_W 8 -#define CRYPTO_DMAHWVER_EIP_NUMBER_M 0x000000FF -#define CRYPTO_DMAHWVER_EIP_NUMBER_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_KEYWRITEAREA -// -//***************************************************************************** -// Field: [7] RAM_AREA7 -// -// Each RAM_AREAx represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written -// 0: RAM_AREA7 is not selected to be written. -// 1: RAM_AREA7 is selected to be written. -// Writing to multiple RAM locations is possible only when the selected RAM -// areas are sequential. -// Keys that require more than one RAM locations (key size is 192 or 256 bits), -// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, -// or RAM_AREA6. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA7 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_BITN 7 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_M 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_S 7 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_SEL 0x00000080 -#define CRYPTO_KEYWRITEAREA_RAM_AREA7_NOT_SEL 0x00000000 - -// Field: [6] RAM_AREA6 -// -// Each RAM_AREAx represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written -// 0: RAM_AREA6 is not selected to be written. -// 1: RAM_AREA6 is selected to be written. -// Writing to multiple RAM locations is possible only when the selected RAM -// areas are sequential. -// Keys that require more than one RAM locations (key size is 192 or 256 bits), -// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, -// or RAM_AREA6. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA6 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_BITN 6 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_M 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_S 6 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_SEL 0x00000040 -#define CRYPTO_KEYWRITEAREA_RAM_AREA6_NOT_SEL 0x00000000 - -// Field: [5] RAM_AREA5 -// -// Each RAM_AREAx represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written -// 0: RAM_AREA5 is not selected to be written. -// 1: RAM_AREA5 is selected to be written. -// Writing to multiple RAM locations is possible only when the selected RAM -// areas are sequential. -// Keys that require more than one RAM locations (key size is 192 or 256 bits), -// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, -// or RAM_AREA6. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA5 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_BITN 5 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_M 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_S 5 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_SEL 0x00000020 -#define CRYPTO_KEYWRITEAREA_RAM_AREA5_NOT_SEL 0x00000000 - -// Field: [4] RAM_AREA4 -// -// Each RAM_AREAx represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written -// 0: RAM_AREA4 is not selected to be written. -// 1: RAM_AREA4 is selected to be written. -// Writing to multiple RAM locations is possible only when the selected RAM -// areas are sequential. -// Keys that require more than one RAM locations (key size is 192 or 256 bits), -// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, -// or RAM_AREA6. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA4 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_BITN 4 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_M 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_S 4 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_SEL 0x00000010 -#define CRYPTO_KEYWRITEAREA_RAM_AREA4_NOT_SEL 0x00000000 - -// Field: [3] RAM_AREA3 -// -// Each RAM_AREAx represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written -// 0: RAM_AREA3 is not selected to be written. -// 1: RAM_AREA3 is selected to be written. -// Writing to multiple RAM locations is possible only when the selected RAM -// areas are sequential. -// Keys that require more than one RAM locations (key size is 192 or 256 bits), -// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, -// or RAM_AREA6. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA3 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_BITN 3 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_M 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_S 3 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_SEL 0x00000008 -#define CRYPTO_KEYWRITEAREA_RAM_AREA3_NOT_SEL 0x00000000 - -// Field: [2] RAM_AREA2 -// -// Each RAM_AREAx represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written -// 0: RAM_AREA2 is not selected to be written. -// 1: RAM_AREA2 is selected to be written. -// Writing to multiple RAM locations is possible only when the selected RAM -// areas are sequential. -// Keys that require more than one RAM locations (key size is 192 or 256 bits), -// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, -// or RAM_AREA6. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA2 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_BITN 2 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_M 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_S 2 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_SEL 0x00000004 -#define CRYPTO_KEYWRITEAREA_RAM_AREA2_NOT_SEL 0x00000000 - -// Field: [1] RAM_AREA1 -// -// Each RAM_AREAx represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written -// 0: RAM_AREA1 is not selected to be written. -// 1: RAM_AREA1 is selected to be written. -// Writing to multiple RAM locations is possible only when the selected RAM -// areas are sequential. -// Keys that require more than one RAM locations (key size is 192 or 256 bits), -// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, -// or RAM_AREA6. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA1 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_BITN 1 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_M 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_S 1 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_SEL 0x00000002 -#define CRYPTO_KEYWRITEAREA_RAM_AREA1_NOT_SEL 0x00000000 - -// Field: [0] RAM_AREA0 -// -// Each RAM_AREAx represents an area of 128 bits. -// Select the key store RAM area(s) where the key(s) needs to be written -// 0: RAM_AREA0 is not selected to be written. -// 1: RAM_AREA0 is selected to be written. -// Writing to multiple RAM locations is possible only when the selected RAM -// areas are sequential. -// Keys that require more than one RAM locations (key size is 192 or 256 bits), -// must start at one of the following areas: RAM_AREA0, RAM_AREA2, RAM_AREA4, -// or RAM_AREA6. -// ENUMs: -// SEL This RAM area is selected to be written -// NOT_SEL This RAM area is not selected to be written -#define CRYPTO_KEYWRITEAREA_RAM_AREA0 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_BITN 0 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_M 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_S 0 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_SEL 0x00000001 -#define CRYPTO_KEYWRITEAREA_RAM_AREA0_NOT_SEL 0x00000000 - -//***************************************************************************** -// -// Register: CRYPTO_O_KEYWRITTENAREA -// -//***************************************************************************** -// Field: [7] RAM_AREA_WRITTEN7 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_BITN 7 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_M 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_S 7 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_WRITTEN 0x00000080 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN7_NOT_WRITTEN 0x00000000 - -// Field: [6] RAM_AREA_WRITTEN6 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_BITN 6 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_M 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_S 6 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_WRITTEN 0x00000040 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN6_NOT_WRITTEN 0x00000000 - -// Field: [5] RAM_AREA_WRITTEN5 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_BITN 5 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_M 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_S 5 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_WRITTEN 0x00000020 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN5_NOT_WRITTEN 0x00000000 - -// Field: [4] RAM_AREA_WRITTEN4 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_BITN 4 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_M 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_S 4 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_WRITTEN 0x00000010 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN4_NOT_WRITTEN 0x00000000 - -// Field: [3] RAM_AREA_WRITTEN3 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_BITN 3 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_M 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_S 3 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_WRITTEN 0x00000008 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN3_NOT_WRITTEN 0x00000000 - -// Field: [2] RAM_AREA_WRITTEN2 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_BITN 2 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_M 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_S 2 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_WRITTEN 0x00000004 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN2_NOT_WRITTEN 0x00000000 - -// Field: [1] RAM_AREA_WRITTEN1 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key -// store memory. -// ENUMs: -// WRITTEN This RAM area is written with valid key -// information -// NOT_WRITTEN This RAM area is not written with valid key -// information -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_BITN 1 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_M 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_S 1 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_WRITTEN 0x00000002 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN1_NOT_WRITTEN 0x00000000 - -// Field: [0] RAM_AREA_WRITTEN0 -// -// On read this bit returns the key area written status. -// -// This bit can be reset by writing a 1. -// -// Note: This register will be reset on a soft reset initiated by writing to -// DMASWRESET.SWRES. After a soft reset, all keys must be rewritten to the key -// store memory. -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_BITN 0 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_M 0x00000001 -#define CRYPTO_KEYWRITTENAREA_RAM_AREA_WRITTEN0_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_KEYSIZE -// -//***************************************************************************** -// Field: [1:0] SIZE -// -// Key size: -// 00: Reserved -// When writing this to this register, the KEY_STORE_WRITTEN_AREA register is -// reset. -// ENUMs: -// 256_BIT 256 bits -// 192_BIT 192 bits -// 128_BIT 128 bits -#define CRYPTO_KEYSIZE_SIZE_W 2 -#define CRYPTO_KEYSIZE_SIZE_M 0x00000003 -#define CRYPTO_KEYSIZE_SIZE_S 0 -#define CRYPTO_KEYSIZE_SIZE_256_BIT 0x00000003 -#define CRYPTO_KEYSIZE_SIZE_192_BIT 0x00000002 -#define CRYPTO_KEYSIZE_SIZE_128_BIT 0x00000001 - -//***************************************************************************** -// -// Register: CRYPTO_O_KEYREADAREA -// -//***************************************************************************** -// Field: [31] BUSY -// -// Key store operation busy status flag (read only): -// 0: Operation is complete. -// 1: Operation is not completed and the key store is busy. -#define CRYPTO_KEYREADAREA_BUSY 0x80000000 -#define CRYPTO_KEYREADAREA_BUSY_BITN 31 -#define CRYPTO_KEYREADAREA_BUSY_M 0x80000000 -#define CRYPTO_KEYREADAREA_BUSY_S 31 - -// Field: [3:0] RAM_AREA -// -// Selects the area of the key store RAM from where the key needs to be read -// that will be writen to the AES engine -// RAM_AREA: -// -// RAM areas RAM_AREA0, RAM_AREA2, RAM_AREA4 and RAM_AREA6 are the only valid -// read areas for 192 and 256 bits key sizes. -// Only RAM areas that contain valid written keys can be selected. -// ENUMs: -// NO_RAM No RAM -// RAM_AREA7 RAM Area 7 -// RAM_AREA6 RAM Area 6 -// RAM_AREA5 RAM Area 5 -// RAM_AREA4 RAM Area 4 -// RAM_AREA3 RAM Area 3 -// RAM_AREA2 RAM Area 2 -// RAM_AREA1 RAM Area 1 -// RAM_AREA0 RAM Area 0 -#define CRYPTO_KEYREADAREA_RAM_AREA_W 4 -#define CRYPTO_KEYREADAREA_RAM_AREA_M 0x0000000F -#define CRYPTO_KEYREADAREA_RAM_AREA_S 0 -#define CRYPTO_KEYREADAREA_RAM_AREA_NO_RAM 0x00000008 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA7 0x00000007 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA6 0x00000006 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA5 0x00000005 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA4 0x00000004 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA3 0x00000003 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA2 0x00000002 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA1 0x00000001 -#define CRYPTO_KEYREADAREA_RAM_AREA_RAM_AREA0 0x00000000 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY20 -// -//***************************************************************************** -// Field: [31:0] AES_KEY2 -// -// AES_KEY2/AES_GHASH_H[31:0] -// -// For GCM: -// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these -// registers. Only used for modes that use the GHASH function (GCM). -// -[255:128] - This register is used to store intermediate values and is -// initialized with 0s when loading a new key. -// -// For CCM: -// -[255:0] - This register is used to store intermediate values. -// -// For CBC-MAC: -// -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY20_AES_KEY2_W 32 -#define CRYPTO_AESKEY20_AES_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY20_AES_KEY2_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY21 -// -//***************************************************************************** -// Field: [31:0] AES_KEY2 -// -// AES_KEY2/AES_GHASH_H[31:0] -// -// For GCM: -// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these -// registers. Only used for modes that use the GHASH function (GCM). -// -[255:128] - This register is used to store intermediate values and is -// initialized with 0s when loading a new key. -// -// For CCM: -// -[255:0] - This register is used to store intermediate values. -// -// For CBC-MAC: -// -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY21_AES_KEY2_W 32 -#define CRYPTO_AESKEY21_AES_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY21_AES_KEY2_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY22 -// -//***************************************************************************** -// Field: [31:0] AES_KEY2 -// -// AES_KEY2/AES_GHASH_H[31:0] -// -// For GCM: -// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these -// registers. Only used for modes that use the GHASH function (GCM). -// -[255:128] - This register is used to store intermediate values and is -// initialized with 0s when loading a new key. -// -// For CCM: -// -[255:0] - This register is used to store intermediate values. -// -// For CBC-MAC: -// -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY22_AES_KEY2_W 32 -#define CRYPTO_AESKEY22_AES_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY22_AES_KEY2_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY23 -// -//***************************************************************************** -// Field: [31:0] AES_KEY2 -// -// AES_KEY2/AES_GHASH_H[31:0] -// -// For GCM: -// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these -// registers. Only used for modes that use the GHASH function (GCM). -// -[255:128] - This register is used to store intermediate values and is -// initialized with 0s when loading a new key. -// -// For CCM: -// -[255:0] - This register is used to store intermediate values. -// -// For CBC-MAC: -// -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY23_AES_KEY2_W 32 -#define CRYPTO_AESKEY23_AES_KEY2_M 0xFFFFFFFF -#define CRYPTO_AESKEY23_AES_KEY2_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY30 -// -//***************************************************************************** -// Field: [31:0] AES_KEY3 -// -// AES_KEY3[31:0]/AES_KEY2[159:128] -// -// For GCM: -// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these -// registers. Only used for modes that use the GHASH function (GCM). -// -[255:128] - This register is used to store intermediate values and is -// initialized with 0s when loading a new key. -// -// For CCM: -// -[255:0] - This register is used to store intermediate values. -// -// For CBC-MAC: -// -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY30_AES_KEY3_W 32 -#define CRYPTO_AESKEY30_AES_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY30_AES_KEY3_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY31 -// -//***************************************************************************** -// Field: [31:0] AES_KEY3 -// -// AES_KEY3[31:0]/AES_KEY2[159:128] -// -// For GCM: -// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these -// registers. Only used for modes that use the GHASH function (GCM). -// -[255:128] - This register is used to store intermediate values and is -// initialized with 0s when loading a new key. -// -// For CCM: -// -[255:0] - This register is used to store intermediate values. -// -// For CBC-MAC: -// -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY31_AES_KEY3_W 32 -#define CRYPTO_AESKEY31_AES_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY31_AES_KEY3_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY32 -// -//***************************************************************************** -// Field: [31:0] AES_KEY3 -// -// AES_KEY3[31:0]/AES_KEY2[159:128] -// -// For GCM: -// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these -// registers. Only used for modes that use the GHASH function (GCM). -// -[255:128] - This register is used to store intermediate values and is -// initialized with 0s when loading a new key. -// -// For CCM: -// -[255:0] - This register is used to store intermediate values. -// -// For CBC-MAC: -// -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY32_AES_KEY3_W 32 -#define CRYPTO_AESKEY32_AES_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY32_AES_KEY3_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESKEY33 -// -//***************************************************************************** -// Field: [31:0] AES_KEY3 -// -// AES_KEY3[31:0]/AES_KEY2[159:128] -// -// For GCM: -// -[127:0] - GHASH_H - The internally calculated GHASH key is stored in these -// registers. Only used for modes that use the GHASH function (GCM). -// -[255:128] - This register is used to store intermediate values and is -// initialized with 0s when loading a new key. -// -// For CCM: -// -[255:0] - This register is used to store intermediate values. -// -// For CBC-MAC: -// -[255:0] - ZEROES - This register must remain 0. -#define CRYPTO_AESKEY33_AES_KEY3_W 32 -#define CRYPTO_AESKEY33_AES_KEY3_M 0xFFFFFFFF -#define CRYPTO_AESKEY33_AES_KEY3_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESIV0 -// -//***************************************************************************** -// Field: [31:0] AES_IV -// -// AES_IV[31:0] -// -// Initialization vector -// Used for regular non-ECB modes (CBC/CTR): -// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers -// must be written with a new 128-bit IV. After an operation, these registers -// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode -// is selected, this value is incremented with 0x1: After first use - When a -// new data block is submitted to the engine -// -// For GCM: -// -[127:0] - AES_IV - For GCM operations, these registers must be written with -// a new 128-bit IV. -// After an operation, these registers contain the updated 128-bit result IV, -// generated by the EIP-120t. Note that bits [127:96] of the IV represent the -// initial counter value (which is 1 for GCM) and must therefore be initialized -// to 0x01000000. This value is incremented with 0x1: After first use - When a -// new data block is submitted to the engine. -// -// For CCM: -// -[127:0] - A0: For CCM this field must be written with value A0, this value -// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and -// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL -// register. This 'L' indicates the width of the Nonce and counter. The loaded -// counter must be initialized to 0. The total width of A0 is 128-bit. -// -// For CBC-MAC: -// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the -// start of each operation. After an operation, these registers contain the -// 128-bit TAG output, generated by the EIP-120t. -#define CRYPTO_AESIV0_AES_IV_W 32 -#define CRYPTO_AESIV0_AES_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV0_AES_IV_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESIV1 -// -//***************************************************************************** -// Field: [31:0] AES_IV -// -// AES_IV[31:0] -// -// Initialization vector -// Used for regular non-ECB modes (CBC/CTR): -// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers -// must be written with a new 128-bit IV. After an operation, these registers -// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode -// is selected, this value is incremented with 0x1: After first use - When a -// new data block is submitted to the engine -// -// For GCM: -// -[127:0] - AES_IV - For GCM operations, these registers must be written with -// a new 128-bit IV. -// After an operation, these registers contain the updated 128-bit result IV, -// generated by the EIP-120t. Note that bits [127:96] of the IV represent the -// initial counter value (which is 1 for GCM) and must therefore be initialized -// to 0x01000000. This value is incremented with 0x1: After first use - When a -// new data block is submitted to the engine. -// -// For CCM: -// -[127:0] - A0: For CCM this field must be written with value A0, this value -// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and -// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL -// register. This 'L' indicates the width of the Nonce and counter. The loaded -// counter must be initialized to 0. The total width of A0 is 128-bit. -// -// For CBC-MAC: -// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the -// start of each operation. After an operation, these registers contain the -// 128-bit TAG output, generated by the EIP-120t. -#define CRYPTO_AESIV1_AES_IV_W 32 -#define CRYPTO_AESIV1_AES_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV1_AES_IV_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESIV2 -// -//***************************************************************************** -// Field: [31:0] AES_IV -// -// AES_IV[31:0] -// -// Initialization vector -// Used for regular non-ECB modes (CBC/CTR): -// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers -// must be written with a new 128-bit IV. After an operation, these registers -// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode -// is selected, this value is incremented with 0x1: After first use - When a -// new data block is submitted to the engine -// -// For GCM: -// -[127:0] - AES_IV - For GCM operations, these registers must be written with -// a new 128-bit IV. -// After an operation, these registers contain the updated 128-bit result IV, -// generated by the EIP-120t. Note that bits [127:96] of the IV represent the -// initial counter value (which is 1 for GCM) and must therefore be initialized -// to 0x01000000. This value is incremented with 0x1: After first use - When a -// new data block is submitted to the engine. -// -// For CCM: -// -[127:0] - A0: For CCM this field must be written with value A0, this value -// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and -// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL -// register. This 'L' indicates the width of the Nonce and counter. The loaded -// counter must be initialized to 0. The total width of A0 is 128-bit. -// -// For CBC-MAC: -// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the -// start of each operation. After an operation, these registers contain the -// 128-bit TAG output, generated by the EIP-120t. -#define CRYPTO_AESIV2_AES_IV_W 32 -#define CRYPTO_AESIV2_AES_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV2_AES_IV_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESIV3 -// -//***************************************************************************** -// Field: [31:0] AES_IV -// -// AES_IV[31:0] -// -// Initialization vector -// Used for regular non-ECB modes (CBC/CTR): -// -[127:0] - AES_IV - For regular AES operations (CBC and CTR) these registers -// must be written with a new 128-bit IV. After an operation, these registers -// contain the latest 128-bit result IV, generated by the EIP-120t. If CTR mode -// is selected, this value is incremented with 0x1: After first use - When a -// new data block is submitted to the engine -// -// For GCM: -// -[127:0] - AES_IV - For GCM operations, these registers must be written with -// a new 128-bit IV. -// After an operation, these registers contain the updated 128-bit result IV, -// generated by the EIP-120t. Note that bits [127:96] of the IV represent the -// initial counter value (which is 1 for GCM) and must therefore be initialized -// to 0x01000000. This value is incremented with 0x1: After first use - When a -// new data block is submitted to the engine. -// -// For CCM: -// -[127:0] - A0: For CCM this field must be written with value A0, this value -// is the concatenation of: A0-flags (5-bits of 0 and 3-bits 'L'), Nonce and -// counter value. 'L' must be a copy from the 'L' value of the AES_CTRL -// register. This 'L' indicates the width of the Nonce and counter. The loaded -// counter must be initialized to 0. The total width of A0 is 128-bit. -// -// For CBC-MAC: -// -[127:0] - Zeroes - For CBC-MAC this register must be written with 0s at the -// start of each operation. After an operation, these registers contain the -// 128-bit TAG output, generated by the EIP-120t. -#define CRYPTO_AESIV3_AES_IV_W 32 -#define CRYPTO_AESIV3_AES_IV_M 0xFFFFFFFF -#define CRYPTO_AESIV3_AES_IV_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESCTL -// -//***************************************************************************** -// Field: [31] CONTEXT_READY -// -// If 1, this read-only status bit indicates that the context data registers -// can be overwritten and the host is permitted to write the next context. -#define CRYPTO_AESCTL_CONTEXT_READY 0x80000000 -#define CRYPTO_AESCTL_CONTEXT_READY_BITN 31 -#define CRYPTO_AESCTL_CONTEXT_READY_M 0x80000000 -#define CRYPTO_AESCTL_CONTEXT_READY_S 31 - -// Field: [30] SAVED_CONTEXT_RDY -// -// If 1, this status bit indicates that an AES authentication TAG and/or IV -// block(s) is/are available for the host to retrieve. This bit is only -// asserted if the save_context bit is set to 1. The bit is mutual exclusive -// with the context_ready bit. -// Writing one clears the bit to 0, indicating the AES core can start its next -// operation. This bit is also cleared when the 4th word of the output TAG -// and/or IV is read. -// Note: All other mode bit writes are ignored when this mode bit is written -// with 1. -// Note: This bit is controlled automatically by the EIP-120t for TAG read DMA -// operations. -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY 0x40000000 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_BITN 30 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_M 0x40000000 -#define CRYPTO_AESCTL_SAVED_CONTEXT_RDY_S 30 - -// Field: [29] SAVE_CONTEXT -// -// This bit indicates that an authentication TAG or result IV needs to be -// stored as a result context. -// Typically this bit must be set for authentication modes returning a TAG -// (CBC-MAC, GCM and CCM), or for basic encryption modes that require future -// continuation with the current result IV. -// If this bit is set, the engine retains its full context until the TAG and/or -// IV registers are read. -// The TAG or IV must be read before the AES engine can start a new operation. -#define CRYPTO_AESCTL_SAVE_CONTEXT 0x20000000 -#define CRYPTO_AESCTL_SAVE_CONTEXT_BITN 29 -#define CRYPTO_AESCTL_SAVE_CONTEXT_M 0x20000000 -#define CRYPTO_AESCTL_SAVE_CONTEXT_S 29 - -// Field: [24:22] CCM_M -// -// Defines M, which indicates the length of the authentication field for CCM -// operations; the authentication field length equals two times (the value of -// CCM-M plus one). -// Note: The EIP-120t always returns a 128-bit authentication field, of which -// the M least significant bytes are valid. All values are supported. -#define CRYPTO_AESCTL_CCM_M_W 3 -#define CRYPTO_AESCTL_CCM_M_M 0x01C00000 -#define CRYPTO_AESCTL_CCM_M_S 22 - -// Field: [21:19] CCM_L -// -// Defines L, which indicates the width of the length field for CCM operations; -// the length field in bytes equals the value of CMM-L plus one. All values are -// supported. -#define CRYPTO_AESCTL_CCM_L_W 3 -#define CRYPTO_AESCTL_CCM_L_M 0x00380000 -#define CRYPTO_AESCTL_CCM_L_S 19 - -// Field: [18] CCM -// -// If set to 1, AES-CCM is selected -// AES-CCM is a combined mode, using AES for authentication and encryption. -// Note: Selecting AES-CCM mode requires writing of the AAD length register -// after all other registers. -// Note: The CTR mode bit in this register must also be set to 1 to enable -// AES-CTR; selecting other AES modes than CTR mode is invalid. -#define CRYPTO_AESCTL_CCM 0x00040000 -#define CRYPTO_AESCTL_CCM_BITN 18 -#define CRYPTO_AESCTL_CCM_M 0x00040000 -#define CRYPTO_AESCTL_CCM_S 18 - -// Field: [17:16] GCM -// -// Set these bits to 11 to select AES-GCM mode. -// AES-GCM is a combined mode, using the Galois field multiplier GF(2 to the -// power of 128) for authentication and AES-CTR mode for encryption. -// Note: The CTR mode bit in this register must also be set to 1 to enable -// AES-CTR -// Bit combination description: -// 00 = No GCM mode -// 01 = Reserved, do not select -// 10 = Reserved, do not select -// 11 = Autonomous GHASH (both H- and Y0-encrypted calculated internally) -// Note: The EIP-120t-1 configuration only supports mode 11 (autonomous GHASH), -// other GCM modes are not allowed. -#define CRYPTO_AESCTL_GCM_W 2 -#define CRYPTO_AESCTL_GCM_M 0x00030000 -#define CRYPTO_AESCTL_GCM_S 16 - -// Field: [15] CBC_MAC -// -// Set to 1 to select AES-CBC MAC mode. -// The direction bit must be set to 1 for this mode. -// Selecting this mode requires writing the length register after all other -// registers. -#define CRYPTO_AESCTL_CBC_MAC 0x00008000 -#define CRYPTO_AESCTL_CBC_MAC_BITN 15 -#define CRYPTO_AESCTL_CBC_MAC_M 0x00008000 -#define CRYPTO_AESCTL_CBC_MAC_S 15 - -// Field: [8:7] CTR_WIDTH -// -// Specifies the counter width for AES-CTR mode -// 00 = 32-bit counter -// 01 = 64-bit counter -// 10 = 96-bit counter -// 11 = 128-bit counter -// ENUMs: -// 128_BIT 128 bits -// 96_BIT 96 bits -// 64_BIT 64 bits -// 32_BIT 32 bits -#define CRYPTO_AESCTL_CTR_WIDTH_W 2 -#define CRYPTO_AESCTL_CTR_WIDTH_M 0x00000180 -#define CRYPTO_AESCTL_CTR_WIDTH_S 7 -#define CRYPTO_AESCTL_CTR_WIDTH_128_BIT 0x00000180 -#define CRYPTO_AESCTL_CTR_WIDTH_96_BIT 0x00000100 -#define CRYPTO_AESCTL_CTR_WIDTH_64_BIT 0x00000080 -#define CRYPTO_AESCTL_CTR_WIDTH_32_BIT 0x00000000 - -// Field: [6] CTR -// -// If set to 1, AES counter mode (CTR) is selected. -// Note: This bit must also be set for GCM and CCM, when encryption/decryption -// is required. -#define CRYPTO_AESCTL_CTR 0x00000040 -#define CRYPTO_AESCTL_CTR_BITN 6 -#define CRYPTO_AESCTL_CTR_M 0x00000040 -#define CRYPTO_AESCTL_CTR_S 6 - -// Field: [5] CBC -// -// If set to 1, cipher-block-chaining (CBC) mode is selected. -#define CRYPTO_AESCTL_CBC 0x00000020 -#define CRYPTO_AESCTL_CBC_BITN 5 -#define CRYPTO_AESCTL_CBC_M 0x00000020 -#define CRYPTO_AESCTL_CBC_S 5 - -// Field: [4:3] KEY_SIZE -// -// This read-only field specifies the key size. -// The key size is automatically configured when a new key is loaded through -// the key store module. -// 00 = N/A - Reserved -// 01 = 128-bit -// 10 = 192-bit -// 11 = 256-bit -#define CRYPTO_AESCTL_KEY_SIZE_W 2 -#define CRYPTO_AESCTL_KEY_SIZE_M 0x00000018 -#define CRYPTO_AESCTL_KEY_SIZE_S 3 - -// Field: [2] DIR -// -// If set to 1 an encrypt operation is performed. -// If set to 0 a decrypt operation is performed. -// This bit must be written with a 1 when CBC-MAC is selected. -#define CRYPTO_AESCTL_DIR 0x00000004 -#define CRYPTO_AESCTL_DIR_BITN 2 -#define CRYPTO_AESCTL_DIR_M 0x00000004 -#define CRYPTO_AESCTL_DIR_S 2 - -// Field: [1] INPUT_READY -// -// If 1, this status bit indicates that the 16-byte AES input buffer is empty. -// The host is permitted to write the next block of data. -// Writing 0 clears the bit to 0 and indicates that the AES core can use the -// provided input data block. -// Writing 1 to this bit is ignored. -// Note: For DMA operations, this bit is automatically controlled by the -// EIP-120t. -// After reset, this bit is 0. After writing a context, this bit becomes 1. -#define CRYPTO_AESCTL_INPUT_READY 0x00000002 -#define CRYPTO_AESCTL_INPUT_READY_BITN 1 -#define CRYPTO_AESCTL_INPUT_READY_M 0x00000002 -#define CRYPTO_AESCTL_INPUT_READY_S 1 - -// Field: [0] OUTPUT_READY -// -// If 1, this status bit indicates that an AES output block is available to be -// retrieved by the host. -// Writing 0 clears the bit to 0 and indicates that output data is read by the -// host. The AES core can provide a next output data block. -// Writing 1 to this bit is ignored. -// Note: For DMA operations, this bit is automatically controlled by the -// EIP-120t. -#define CRYPTO_AESCTL_OUTPUT_READY 0x00000001 -#define CRYPTO_AESCTL_OUTPUT_READY_BITN 0 -#define CRYPTO_AESCTL_OUTPUT_READY_M 0x00000001 -#define CRYPTO_AESCTL_OUTPUT_READY_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATALEN0 -// -//***************************************************************************** -// Field: [31:0] C_LENGTH -// -// C_LENGTH[31:0] -// Bits [60:0] of the crypto length registers (LSW and MSW) store the -// cryptographic data length in bytes for all modes. Once processing with this -// context is started, this length decrements to 0. Data lengths up to (261: 1) -// bytes are allowed. -// For GCM, any value up to 236 - 32 bytes can be used. This is because a -// 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 - -// 2, resulting in a maximum number of bytes of 236 - 32. -// A write to this register triggers the engine to start using this context. -// This is valid for all modes except GCM and CCM. -// Note: For the combined modes (GCM and CCM), this length does not include the -// authentication only data; the authentication length is specified in the -// AESAUTHLEN register -// All modes must have a length greater than 0. For the combined modes, it is -// allowed to have one of the lengths equal to 0. -// For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program -// zero to the length field; in that case the length is assumed infinite. -// All data must be byte (8-bit) aligned for stream cipher modes; bit aligned -// data streams are not supported by the EIP-120t. For block cipher modes, the -// data length must be programmed in multiples of the block cipher size, 16 -// bytes. -// For a host read operation, these registers return all-0s. -#define CRYPTO_AESDATALEN0_C_LENGTH_W 32 -#define CRYPTO_AESDATALEN0_C_LENGTH_M 0xFFFFFFFF -#define CRYPTO_AESDATALEN0_C_LENGTH_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATALEN1 -// -//***************************************************************************** -// Field: [28:0] C_LENGTH -// -// C_LENGTH[60:32] -// Bits [60:0] of the crypto length registers (LSW and MSW) store the -// cryptographic data length in bytes for all modes. Once processing with this -// context is started, this length decrements to 0. Data lengths up to (261: 1) -// bytes are allowed. -// For GCM, any value up to 236 - 32 bytes can be used. This is because a -// 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 - -// 2, resulting in a maximum number of bytes of 236 - 32. -// A write to this register triggers the engine to start using this context. -// This is valid for all modes except GCM and CCM. -// Note: For the combined modes (GCM and CCM), this length does not include the -// authentication only data; the authentication length is specified in the -// AESAUTHLEN register -// All modes must have a length greater than 0. For the combined modes, it is -// allowed to have one of the lengths equal to 0. -// For the basic encryption modes (ECB, CBC, and CTR) it is allowed to program -// zero to the length field; in that case the length is assumed infinite. -// All data must be byte (8-bit) aligned for stream cipher modes; bit aligned -// data streams are not supported by the EIP-120t. For block cipher modes, the -// data length must be programmed in multiples of the block cipher size, 16 -// bytes. -// For a host read operation, these registers return all-0s. -#define CRYPTO_AESDATALEN1_C_LENGTH_W 29 -#define CRYPTO_AESDATALEN1_C_LENGTH_M 0x1FFFFFFF -#define CRYPTO_AESDATALEN1_C_LENGTH_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESAUTHLEN -// -//***************************************************************************** -// Field: [31:0] AUTH_LENGTH -// -// Bits [31:0] of the authentication length register store the authentication -// data length in bytes for combined modes only (GCM or CCM). -// Supported AAD-lengths for CCM are from 0 to (2^16 - 2^8) bytes. For GCM any -// value up to (2^32 - 1) bytes can be used. Once processing with this context -// is started, this length decrements to 0. -// A write to this register triggers the engine to start using this context for -// GCM and CCM. -// For a host read operation, these registers return all-0s. -#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_W 32 -#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_M 0xFFFFFFFF -#define CRYPTO_AESAUTHLEN_AUTH_LENGTH_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAOUT0 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Data register 0 for output block data from the Crypto peripheral. -// These bits = AES Output Data[31:0] of {127:0] -// -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES engine via DMA. -// -// For a Host read operation, these registers contain the 128-bit output block -// from the latest AES operation. Reading from a word-aligned offset within -// this address range will read one word (4 bytes) of data out the 4-word deep -// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one -// full block) should be read before the core will move the next block to the -// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY -// must be written. -// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid -// (message) bytes/words can be written with any data. -// -// Note: The AAD / authentication only data is not copied to the output buffer -// but only used for authentication. -#define CRYPTO_AESDATAOUT0_DATA_W 32 -#define CRYPTO_AESDATAOUT0_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT0_DATA_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAIN0 -// -//***************************************************************************** -// Field: [31:0] AES_DATA_IN_OUT -// -// AES input data[31:0] / AES output data[31:0] -// Data registers for input/output block data to/from the EIP-120t. -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES core via DMA. For a host write -// operation, these registers must be written with the 128-bit input block for -// the next AES operation. Writing at a word-aligned offset within this address -// range stores the word (4 bytes) of data into the corresponding position of -// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is -// used for the next AES operation. If the last data block is not completely -// filled with valid data (see notes below), it is allowed to write only the -// words with valid data. Next AES operation is triggered by writing to the -// input_ready flag of the AES_CTRL register. -// For a host read operation, these registers contain the 128-bit output block -// from the latest AES operation. Reading from a word-aligned offset within -// this address range reads one word (4 bytes) of data out the 4-word deep (16 -// bytes = 128-bits AES block) data output buffer. The words (4 words, one full -// block) should be read before the core will move the next block to the data -// output buffer. To empty the data output buffer, the output_ready flag of the -// AES_CTRL register must be written. -// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid -// (message) bytes/words can be written with any data. -// Note: AES typically operates on 128 bits block multiple input data. The CTR, -// GCM and CCM modes form an exception. The last block of a CTR-mode message -// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the -// last block of both AAD and message data may contain less than 128 bits -// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks -// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR -// mode, the remaining data in an unaligned data block is ignored. -// Note: The AAD / authentication only data is not copied to the output buffer -// but only used for authentication. -#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_W 32 -#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN0_AES_DATA_IN_OUT_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAOUT1 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Data register 0 for output block data from the Crypto peripheral. -// These bits = AES Output Data[31:0] of {127:0] -// -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES engine via DMA. -// -// For a Host read operation, these registers contain the 128-bit output block -// from the latest AES operation. Reading from a word-aligned offset within -// this address range will read one word (4 bytes) of data out the 4-word deep -// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one -// full block) should be read before the core will move the next block to the -// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY -// must be written. -// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid -// (message) bytes/words can be written with any data. -// -// Note: The AAD / authentication only data is not copied to the output buffer -// but only used for authentication. -#define CRYPTO_AESDATAOUT1_DATA_W 32 -#define CRYPTO_AESDATAOUT1_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT1_DATA_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAIN1 -// -//***************************************************************************** -// Field: [31:0] AES_DATA_IN_OUT -// -// AES input data[31:0] / AES output data[63:32] -// Data registers for input/output block data to/from the EIP-120t. -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES core via DMA. For a host write -// operation, these registers must be written with the 128-bit input block for -// the next AES operation. Writing at a word-aligned offset within this address -// range stores the word (4 bytes) of data into the corresponding position of -// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is -// used for the next AES operation. If the last data block is not completely -// filled with valid data (see notes below), it is allowed to write only the -// words with valid data. Next AES operation is triggered by writing to the -// input_ready flag of the AES_CTRL register. -// For a host read operation, these registers contain the 128-bit output block -// from the latest AES operation. Reading from a word-aligned offset within -// this address range reads one word (4 bytes) of data out the 4-word deep (16 -// bytes = 128-bits AES block) data output buffer. The words (4 words, one full -// block) should be read before the core will move the next block to the data -// output buffer. To empty the data output buffer, the output_ready flag of the -// AES_CTRL register must be written. -// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid -// (message) bytes/words can be written with any data. -// Note: AES typically operates on 128 bits block multiple input data. The CTR, -// GCM and CCM modes form an exception. The last block of a CTR-mode message -// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the -// last block of both AAD and message data may contain less than 128 bits -// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks -// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR -// mode, the remaining data in an unaligned data block is ignored. -// Note: The AAD / authentication only data is not copied to the output buffer -// but only used for authentication. -#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_W 32 -#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN1_AES_DATA_IN_OUT_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAOUT2 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Data register 0 for output block data from the Crypto peripheral. -// These bits = AES Output Data[31:0] of {127:0] -// -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES engine via DMA. -// -// For a Host read operation, these registers contain the 128-bit output block -// from the latest AES operation. Reading from a word-aligned offset within -// this address range will read one word (4 bytes) of data out the 4-word deep -// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one -// full block) should be read before the core will move the next block to the -// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY -// must be written. -// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid -// (message) bytes/words can be written with any data. -// -// Note: The AAD / authentication only data is not copied to the output buffer -// but only used for authentication. -#define CRYPTO_AESDATAOUT2_DATA_W 32 -#define CRYPTO_AESDATAOUT2_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT2_DATA_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAIN2 -// -//***************************************************************************** -// Field: [31:0] AES_DATA_IN_OUT -// -// AES input data[95:64] / AES output data[95:64] -// Data registers for input/output block data to/from the EIP-120t. -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES core via DMA. For a host write -// operation, these registers must be written with the 128-bit input block for -// the next AES operation. Writing at a word-aligned offset within this address -// range stores the word (4 bytes) of data into the corresponding position of -// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is -// used for the next AES operation. If the last data block is not completely -// filled with valid data (see notes below), it is allowed to write only the -// words with valid data. Next AES operation is triggered by writing to the -// input_ready flag of the AES_CTRL register. -// For a host read operation, these registers contain the 128-bit output block -// from the latest AES operation. Reading from a word-aligned offset within -// this address range reads one word (4 bytes) of data out the 4-word deep (16 -// bytes = 128-bits AES block) data output buffer. The words (4 words, one full -// block) should be read before the core will move the next block to the data -// output buffer. To empty the data output buffer, the output_ready flag of the -// AES_CTRL register must be written. -// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid -// (message) bytes/words can be written with any data. -// Note: AES typically operates on 128 bits block multiple input data. The CTR, -// GCM and CCM modes form an exception. The last block of a CTR-mode message -// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the -// last block of both AAD and message data may contain less than 128 bits -// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks -// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR -// mode, the remaining data in an unaligned data block is ignored. -// Note: The AAD / authentication only data is not copied to the output buffer -// but only used for authentication. -#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_W 32 -#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN2_AES_DATA_IN_OUT_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAOUT3 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Data register 0 for output block data from the Crypto peripheral. -// These bits = AES Output Data[31:0] of {127:0] -// -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES engine via DMA. -// -// For a Host read operation, these registers contain the 128-bit output block -// from the latest AES operation. Reading from a word-aligned offset within -// this address range will read one word (4 bytes) of data out the 4-word deep -// (16 bytes = 128-bits AES block) data output buffer. The words (4 words, one -// full block) should be read before the core will move the next block to the -// data output buffer. To empty the data output buffer, AESCTL.OUTPUT_READY -// must be written. -// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid -// (message) bytes/words can be written with any data. -// -// Note: The AAD / authentication only data is not copied to the output buffer -// but only used for authentication. -#define CRYPTO_AESDATAOUT3_DATA_W 32 -#define CRYPTO_AESDATAOUT3_DATA_M 0xFFFFFFFF -#define CRYPTO_AESDATAOUT3_DATA_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESDATAIN3 -// -//***************************************************************************** -// Field: [31:0] AES_DATA_IN_OUT -// -// AES input data[127:96] / AES output data[127:96] -// Data registers for input/output block data to/from the EIP-120t. -// For normal operations, this register is not used, since data input and -// output is transferred from and to the AES core via DMA. For a host write -// operation, these registers must be written with the 128-bit input block for -// the next AES operation. Writing at a word-aligned offset within this address -// range stores the word (4 bytes) of data into the corresponding position of -// 4-word deep (16 bytes = 128-bit AES block) data input buffer. This buffer is -// used for the next AES operation. If the last data block is not completely -// filled with valid data (see notes below), it is allowed to write only the -// words with valid data. Next AES operation is triggered by writing to the -// input_ready flag of the AES_CTRL register. -// For a host read operation, these registers contain the 128-bit output block -// from the latest AES operation. Reading from a word-aligned offset within -// this address range reads one word (4 bytes) of data out the 4-word deep (16 -// bytes = 128-bits AES block) data output buffer. The words (4 words, one full -// block) should be read before the core will move the next block to the data -// output buffer. To empty the data output buffer, the output_ready flag of the -// AES_CTRL register must be written. -// For the modes with authentication (CBC-MAC, GCM and CCM), the invalid -// (message) bytes/words can be written with any data. -// Note: AES typically operates on 128 bits block multiple input data. The CTR, -// GCM and CCM modes form an exception. The last block of a CTR-mode message -// may contain less than 128 bits (refer to [NIST 800-38A]). For GCM/CCM, the -// last block of both AAD and message data may contain less than 128 bits -// (refer to [NIST 800-38D]). The EIP-120t automatically pads or masks -// misaligned ending data blocks with 0s for GCM, CCM and CBC-MAC. For CTR -// mode, the remaining data in an unaligned data block is ignored. -// Note: The AAD / authentication only data is not copied to the output buffer -// but only used for authentication. -#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_W 32 -#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_M 0xFFFFFFFF -#define CRYPTO_AESDATAIN3_AES_DATA_IN_OUT_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESTAGOUT0 -// -//***************************************************************************** -// Field: [31:0] AES_TAG -// -// AES_TAG[31:0] -// Bits [31:0] of this register stores the authentication value for the -// combined and authentication only modes. -// For a host read operation, these registers contain the last 128-bit TAG -// output of the EIP-120t; the TAG is available until the next context is -// written. -// This register will only contain valid data if the TAG is available and when -// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for -// operations/modes that do not return a TAG, reads from this register return -// data from the IV register. -#define CRYPTO_AESTAGOUT0_AES_TAG_W 32 -#define CRYPTO_AESTAGOUT0_AES_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT0_AES_TAG_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESTAGOUT1 -// -//***************************************************************************** -// Field: [31:0] AES_TAG -// -// AES_TAG[31:0] -// Bits [31:0] of this register stores the authentication value for the -// combined and authentication only modes. -// For a host read operation, these registers contain the last 128-bit TAG -// output of the EIP-120t; the TAG is available until the next context is -// written. -// This register will only contain valid data if the TAG is available and when -// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for -// operations/modes that do not return a TAG, reads from this register return -// data from the IV register. -#define CRYPTO_AESTAGOUT1_AES_TAG_W 32 -#define CRYPTO_AESTAGOUT1_AES_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT1_AES_TAG_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESTAGOUT2 -// -//***************************************************************************** -// Field: [31:0] AES_TAG -// -// AES_TAG[31:0] -// Bits [31:0] of this register stores the authentication value for the -// combined and authentication only modes. -// For a host read operation, these registers contain the last 128-bit TAG -// output of the EIP-120t; the TAG is available until the next context is -// written. -// This register will only contain valid data if the TAG is available and when -// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for -// operations/modes that do not return a TAG, reads from this register return -// data from the IV register. -#define CRYPTO_AESTAGOUT2_AES_TAG_W 32 -#define CRYPTO_AESTAGOUT2_AES_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT2_AES_TAG_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_AESTAGOUT3 -// -//***************************************************************************** -// Field: [31:0] AES_TAG -// -// AES_TAG[31:0] -// Bits [31:0] of this register stores the authentication value for the -// combined and authentication only modes. -// For a host read operation, these registers contain the last 128-bit TAG -// output of the EIP-120t; the TAG is available until the next context is -// written. -// This register will only contain valid data if the TAG is available and when -// the AESCTL.SAVED_CONTEXT_RDY register is set. During processing or for -// operations/modes that do not return a TAG, reads from this register return -// data from the IV register. -#define CRYPTO_AESTAGOUT3_AES_TAG_W 32 -#define CRYPTO_AESTAGOUT3_AES_TAG_M 0xFFFFFFFF -#define CRYPTO_AESTAGOUT3_AES_TAG_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN1 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[63:32] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is -// busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN1_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN2 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[95:64] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine is -// busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN2_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN3 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[127:96] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when the rfd_in bit of -// the HASH_IO_BUF_CTRL register is high. If the rfd_in bit is 0, the engine is -// busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASH_IO_BUF_CTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN3_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN4 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[159:128] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is '1'. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN4_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN5 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[191:160] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN5_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN6 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[223:192] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN6_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN7 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[255:224] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN7_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN8 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[287:256] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN8_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN9 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[319:288] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN9_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN10 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[351:320] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN10_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN11 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[383:352] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN11_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN12 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[415:384] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN12_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN13 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[447:416] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN13_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN14 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[479:448] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN14_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN15 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[511:480] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN15_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN16 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[543:512] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN16_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN17 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[575:544] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN17_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN18 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[607:576] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN18_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN19 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[639:608] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN19_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN20 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[671:640] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN20_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN21 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[703:672] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN21_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN22 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[735:704] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN22_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN23 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[767:736] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN23_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN24 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[799:768] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN24_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN25 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[831:800] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN25_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN26 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[863:832] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN26_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN27 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[895:864] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN27_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN28 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[923:896] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN28_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN29 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[959:924] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN29_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN30 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[991:960] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN30_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDATAIN31 -// -//***************************************************************************** -// Field: [31:0] HASH_DATA_IN -// -// HASH_DATA_IN[1023:992] -// These registers must be written with the 512-bit input data. The data lines -// are connected directly to the data input of the hash module and hence into -// the engine's internal data buffer. Writing to each of the registers triggers -// a corresponding 32-bit write enable to the internal buffer. -// Note: The host may only write the input data buffer when -// HASHIOBUFCTRL.RFD_IN is 1. If the HASHIOBUFCTRL.RFD_IN is 0, the engine -// is busy with processing. During processing, it is not allowed to write new -// input data. -// For message lengths larger than 64 bytes, multiple blocks of data are -// written to this input buffer using a handshake through flags of the -// HASHIOBUFCTRL register. All blocks except the last are required to be 512 -// bits in size. If the last block is not 512 bits long, only the least -// significant bits of data must be written, but they must be padded with 0s to -// the next 32-bit boundary. -// Host read operations from these register addresses return 0s. -#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_W 32 -#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_M 0xFFFFFFFF -#define CRYPTO_HASHDATAIN31_HASH_DATA_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHIOBUFCTRL -// -//***************************************************************************** -// Field: [7] PAD_DMA_MESSAGE -// -// Note: This bit must only be used when data is supplied through the DMA. It -// should not be used when data is supplied through the slave interface. -// This bit indicates whether the hash engine has to pad the message, received -// through the DMA and finalize the hash. -// When set to 1, the hash engine pads the last block using the programmed -// length. After padding, the final hash result is calculated. -// When set to 0, the hash engine treats the last written block as block-size -// aligned and calculates the intermediate digest. -// This bit is automatically cleared when the last DMA data block is arrived in -// the hash engine. -#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE 0x00000080 -#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_BITN 7 -#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_M 0x00000080 -#define CRYPTO_HASHIOBUFCTRL_PAD_DMA_MESSAGE_S 7 - -// Field: [6] GET_DIGEST -// -// Note: The bit description below is only applicable when data is sent through -// the slave interface. This bit must be set to 0 when data is received through -// the DMA. -// This bit indicates whether the hash engine should provide the hash digest. -// When provided simultaneously with data_in_av, the hash digest is provided -// after processing the data that is currently in the HASHDATAINn register. -// When provided without data_in_av, the current internal digest buffer value -// is copied to the HASHDIGESTn registers. -// The host must write a 1 to this bit to make the intermediate hash digest -// available. -// Writing 0 to this bit has no effect. -// This bit is automatically cleared (that is, reads 0) when the hash engine -// has processed the contents of the HASHDATAINn register. In the period -// between this bit is set by the host and the actual HASHDATAINn processing, -// this bit reads 1. -#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST 0x00000040 -#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_BITN 6 -#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_M 0x00000040 -#define CRYPTO_HASHIOBUFCTRL_GET_DIGEST_S 6 - -// Field: [5] PAD_MESSAGE -// -// Note: The bit description below is only applicable when data is sent through -// the slave interface. This bit must be set to 0 when data is received through -// the DMA. -// This bit indicates that the HASHDATAINn registers hold the last data of the -// message and hash padding must be applied. -// The host must write this bit to 1 in order to indicate to the hash engine -// that the HASHDATAINn register currently holds the last data of the message. -// When pad_message is set to 1, the hash engine will add padding bits to the -// data currently in the HASHDATAINn register. -// When the last message block is smaller than 512 bits, the pad_message bit -// must be set to 1 together with the data_in_av bit. -// When the last message block is equal to 512 bits, pad_message may be set -// together with data_in_av. In this case the pad_message bit may also be set -// after the last data block has been written to the hash engine (so when the -// rfd_in bit has become 1 again after writing the last data block). -// Writing 0 to this bit has no effect. -// This bit is automatically cleared (i.e. reads 0) by the hash engine. This -// bit reads 1 between the time it was set by the host and the hash engine -// interpreted its value. -#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE 0x00000020 -#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_BITN 5 -#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_M 0x00000020 -#define CRYPTO_HASHIOBUFCTRL_PAD_MESSAGE_S 5 - -// Field: [2] RFD_IN -// -// Note: The bit description below is only applicable when data is sent through -// the slave interface. This bit can be ignored when data is received through -// the DMA. -// Read-only status of the input buffer of the hash engine. -// When 1, the input buffer of the hash engine can accept new data; the -// HASHDATAINn registers can safely be populated with new data. -// When 0, the input buffer of the hash engine is processing the data that is -// currently in HASHDATAINn; writing new data to these registers is not -// allowed. -#define CRYPTO_HASHIOBUFCTRL_RFD_IN 0x00000004 -#define CRYPTO_HASHIOBUFCTRL_RFD_IN_BITN 2 -#define CRYPTO_HASHIOBUFCTRL_RFD_IN_M 0x00000004 -#define CRYPTO_HASHIOBUFCTRL_RFD_IN_S 2 - -// Field: [1] DATA_IN_AV -// -// Note: The bit description below is only applicable when data is sent through -// the slave interface. This bit must be set to 0 when data is received through -// the DMA. -// This bit indicates that the HASHDATAINn registers contain new input data for -// processing. -// The host must write a 1 to this bit to start processing the data in -// HASHDATAINn; the hash engine will process the new data as soon as it is -// ready for it (rfd_in bit is 1). -// Writing 0 to this bit has no effect. -// This bit is automatically cleared (i.e. reads as 0) when the hash engine -// starts processing the HASHDATAINn contents. This bit reads 1 between the -// time it was set by the host and the hash engine actually starts processing -// the input data block. -#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV 0x00000002 -#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_BITN 1 -#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_M 0x00000002 -#define CRYPTO_HASHIOBUFCTRL_DATA_IN_AV_S 1 - -// Field: [0] OUTPUT_FULL -// -// Indicates that the output buffer registers (HASHDIGESTn) are available for -// reading by the host. -// When this bit reads 0, the output buffer registers are released; the hash -// engine is allowed to write new data to it. In this case, the registers -// should not be read by the host. -// When this bit reads 1, the hash engine has stored the result of the latest -// hash operation in the output buffer registers. As long as this bit reads 1, -// the host may read output buffer registers and the hash engine is prevented -// from writing new data to the output buffer. -// After retrieving the hash result data from the output buffer, the host must -// write a 1 to this bit to clear it. This makes the digest output buffer -// available for the hash engine to store new hash results. -// Writing 0 to this bit has no effect. -// Note: If this bit is asserted (1) no new operation should be started before -// the digest is retrieved from the hash engine and this bit is cleared (0). -#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL 0x00000001 -#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_BITN 0 -#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_M 0x00000001 -#define CRYPTO_HASHIOBUFCTRL_OUTPUT_FULL_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHMODE -// -//***************************************************************************** -// Field: [6] SHA384_MODE -// -// The host must write this bit with 1 prior to processing a SHA 384 session. -#define CRYPTO_HASHMODE_SHA384_MODE 0x00000040 -#define CRYPTO_HASHMODE_SHA384_MODE_BITN 6 -#define CRYPTO_HASHMODE_SHA384_MODE_M 0x00000040 -#define CRYPTO_HASHMODE_SHA384_MODE_S 6 - -// Field: [5] SHA512_MODE -// -// The host must write this bit with 1 prior to processing a SHA 512 session. -#define CRYPTO_HASHMODE_SHA512_MODE 0x00000020 -#define CRYPTO_HASHMODE_SHA512_MODE_BITN 5 -#define CRYPTO_HASHMODE_SHA512_MODE_M 0x00000020 -#define CRYPTO_HASHMODE_SHA512_MODE_S 5 - -// Field: [4] SHA224_MODE -// -// The host must write this bit with 1 prior to processing a SHA 224 session. -#define CRYPTO_HASHMODE_SHA224_MODE 0x00000010 -#define CRYPTO_HASHMODE_SHA224_MODE_BITN 4 -#define CRYPTO_HASHMODE_SHA224_MODE_M 0x00000010 -#define CRYPTO_HASHMODE_SHA224_MODE_S 4 - -// Field: [3] SHA256_MODE -// -// The host must write this bit with 1 prior to processing a SHA 256 session. -#define CRYPTO_HASHMODE_SHA256_MODE 0x00000008 -#define CRYPTO_HASHMODE_SHA256_MODE_BITN 3 -#define CRYPTO_HASHMODE_SHA256_MODE_M 0x00000008 -#define CRYPTO_HASHMODE_SHA256_MODE_S 3 - -// Field: [0] NEW_HASH -// -// When set to 1, it indicates that the hash engine must start processing a new -// hash session. The [HASHDIGESTn.* ] registers will automatically be loaded -// with the initial hash algorithm constants of the selected hash algorithm. -// When this bit is 0 while the hash processing is started, the initial hash -// algorithm constants are not loaded in the HASHDIGESTn registers. The hash -// engine will start processing with the digest that is currently in its -// internal HASHDIGESTn registers. -// This bit is automatically cleared when hash processing is started. -#define CRYPTO_HASHMODE_NEW_HASH 0x00000001 -#define CRYPTO_HASHMODE_NEW_HASH_BITN 0 -#define CRYPTO_HASHMODE_NEW_HASH_M 0x00000001 -#define CRYPTO_HASHMODE_NEW_HASH_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHINLENL -// -//***************************************************************************** -// Field: [31:0] LENGTH_IN -// -// LENGTH_IN[31:0] -// Message length registers. The content of these registers is used by the hash -// engine during the message padding phase of the hash session. The data lines -// of this registers are directly connected to the interface of the hash -// engine. -// For a write operation by the host, these registers should be written with -// the message length in bits. -// -// Final hash operations: -// The total input data length must be programmed for new hash operations that -// require finalization (padding). The input data must be provided through the -// slave or DMA interface. -// -// Continued hash operations (finalized): -// For continued hash operations that require finalization, the total message -// length must be programmed, including the length of previously hashed data -// that corresponds to the written input digest. -// -// Non-final hash operations: -// For hash operations that do not require finalization (input data length is -// multiple of 512-bits which is SHA-256 data block size), the length field -// does not need to be programmed since not used by the operation. -// -// If the message length in bits is below (2^32-1), then only this register -// needs to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s -// in this case. -// The host may write the length register at any time during the hash session -// when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written -// before the last data of the active hash session is written into the hash -// engine. -// host read operations from these register locations will return 0s. -// Note: When getting data from DMA, this register must be programmed before -// DMA is programmed to start. -#define CRYPTO_HASHINLENL_LENGTH_IN_W 32 -#define CRYPTO_HASHINLENL_LENGTH_IN_M 0xFFFFFFFF -#define CRYPTO_HASHINLENL_LENGTH_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHINLENH -// -//***************************************************************************** -// Field: [31:0] LENGTH_IN -// -// LENGTH_IN[63:32] -// Message length registers. The content of these registers is used by the hash -// engine during the message padding phase of the hash session. The data lines -// of this registers are directly connected to the interface of the hash -// engine. -// For a write operation by the host, these registers should be written with -// the message length in bits. -// -// Final hash operations: -// The total input data length must be programmed for new hash operations that -// require finalization (padding). The input data must be provided through the -// slave or DMA interface. -// -// Continued hash operations (finalized): -// For continued hash operations that require finalization, the total message -// length must be programmed, including the length of previously hashed data -// that corresponds to the written input digest. -// -// Non-final hash operations: -// For hash operations that do not require finalization (input data length is -// multiple of 512-bits which is SHA-256 data block size), the length field -// does not need to be programmed since not used by the operation. -// -// If the message length in bits is below (2^32-1), then only HASHINLENL needs -// to be written. The hardware automatically sets HASH_LENGTH_IN_H to 0s in -// this case. -// The host may write the length register at any time during the hash session -// when the HASHIOBUFCTRL.RFD_IN is high. The length register must be written -// before the last data of the active hash session is written into the hash -// engine. -// host read operations from these register locations will return 0s. -// Note: When getting data from DMA, this register must be programmed before -// DMA is programmed to start. -#define CRYPTO_HASHINLENH_LENGTH_IN_W 32 -#define CRYPTO_HASHINLENH_LENGTH_IN_M 0xFFFFFFFF -#define CRYPTO_HASHINLENH_LENGTH_IN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTA -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[31:0] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTA_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTA_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTA_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTB -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[63:32] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTB_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTB_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTB_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTC -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[95:64] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTC_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTC_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTC_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTD -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[127:96] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTD_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTD_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTD_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTE -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[159:128] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTE_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTE_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTE_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTF -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[191:160] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTF_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTF_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTF_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTG -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[223:192] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTG_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTG_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTG_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTH -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[255:224] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTH_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTH_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTH_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTI -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[287:256] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTI_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTI_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTI_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTJ -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[319:288] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTJ_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTK -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[351:320] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTK_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTK_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTK_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTL -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[383:352] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTL_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTL_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTL_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTM -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[415:384] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTM_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTM_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTM_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTN -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[447:416] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTN_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTN_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTN_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTO -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[479:448] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTO_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTO_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTO_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HASHDIGESTP -// -//***************************************************************************** -// Field: [31:0] HASH_DIGEST -// -// HASH_DIGEST[511:480] -// Hash digest registers -// Write operation: -// -// Continued hash: -// These registers should be written with the context data, before the start of -// a resumed hash session (the HASHMODE.NEW_HASH bit is 0 when starting a hash -// session). -// -// New hash: -// When initiating a new hash session (theHASHMODE.NEW_HASH bit is 1), the -// internal digest registers are automatically set to the SHA-256 algorithm -// constant and these register should not be written. -// -// Reading from these registers provides the intermediate hash result -// (non-final hash operation) or the final hash result (final hash operation) -// after data processing. -#define CRYPTO_HASHDIGESTP_HASH_DIGEST_W 32 -#define CRYPTO_HASHDIGESTP_HASH_DIGEST_M 0xFFFFFFFF -#define CRYPTO_HASHDIGESTP_HASH_DIGEST_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_ALGSEL -// -//***************************************************************************** -// Field: [32] HASH_SHA_512 -// -// If set to one, selects the hash engine in 512B mode as destination for the -// DMA -// The maximum transfer size to DMA engine is set to 64 bytes for reading and -// 32 bytes for writing (the latter is only applicable if the hash result is -// written out through the DMA). -#define CRYPTO_ALGSEL_HASH_SHA_512 0x100000000 -#define CRYPTO_ALGSEL_HASH_SHA_512_BITN 32 -#define CRYPTO_ALGSEL_HASH_SHA_512_M 0x100000000 -#define CRYPTO_ALGSEL_HASH_SHA_512_S 32 - -// Field: [31] TAG -// -// If this bit is cleared to 0, the DMA operation involves only data. -// If this bit is set, the DMA operation includes a TAG (Authentication Result -// / Digest). -// For SHA-256 operation, a DMA must be set up for both input data and TAG. For -// any other selected module, setting this bit only allows a DMA that reads the -// TAG. No data allowed to be transferred to or from the selected module via -// the DMA. -#define CRYPTO_ALGSEL_TAG 0x80000000 -#define CRYPTO_ALGSEL_TAG_BITN 31 -#define CRYPTO_ALGSEL_TAG_M 0x80000000 -#define CRYPTO_ALGSEL_TAG_S 31 - -// Field: [2] HASH_SHA_256 -// -// If set to one, selects the hash engine in 256B mode as destination for the -// DMA -// The maximum transfer size to DMA engine is set to 64 bytes for reading and -// 32 bytes for writing (the latter is only applicable if the hash result is -// written out through the DMA). -#define CRYPTO_ALGSEL_HASH_SHA_256 0x00000004 -#define CRYPTO_ALGSEL_HASH_SHA_256_BITN 2 -#define CRYPTO_ALGSEL_HASH_SHA_256_M 0x00000004 -#define CRYPTO_ALGSEL_HASH_SHA_256_S 2 - -// Field: [1] AES -// -// If set to one, selects the AES engine as source/destination for the DMA -// The read and write maximum transfer size to the DMA engine is set to 16 -// bytes. -#define CRYPTO_ALGSEL_AES 0x00000002 -#define CRYPTO_ALGSEL_AES_BITN 1 -#define CRYPTO_ALGSEL_AES_M 0x00000002 -#define CRYPTO_ALGSEL_AES_S 1 - -// Field: [0] KEY_STORE -// -// If set to one, selects the Key Store as destination for the DMA -// The maximum transfer size to DMA engine is set to 32 bytes (however -// transfers of 16, 24 and 32 bytes are allowed) -#define CRYPTO_ALGSEL_KEY_STORE 0x00000001 -#define CRYPTO_ALGSEL_KEY_STORE_BITN 0 -#define CRYPTO_ALGSEL_KEY_STORE_M 0x00000001 -#define CRYPTO_ALGSEL_KEY_STORE_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_DMAPROTCTL -// -//***************************************************************************** -// Field: [0] PROT_EN -// -// Select AHB transfer protection control for DMA transfers using the key store -// area as destination. -// 0 : transfers use 'USER' type access. -// 1 : transfers use 'PRIVILEGED' type access. -#define CRYPTO_DMAPROTCTL_PROT_EN 0x00000001 -#define CRYPTO_DMAPROTCTL_PROT_EN_BITN 0 -#define CRYPTO_DMAPROTCTL_PROT_EN_M 0x00000001 -#define CRYPTO_DMAPROTCTL_PROT_EN_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_SWRESET -// -//***************************************************************************** -// Field: [0] SW_RESET -// -// If this bit is set to 1, the following modules are reset: -// - Master control internal state is reset. That includes interrupt, error -// status register, and result available interrupt generation FSM. -// - Key store module state is reset. That includes clearing the written area -// flags; therefore, the keys must be reloaded to the key store module. -// Writing 0 has no effect. -// The bit is self cleared after executing the reset. -#define CRYPTO_SWRESET_SW_RESET 0x00000001 -#define CRYPTO_SWRESET_SW_RESET_BITN 0 -#define CRYPTO_SWRESET_SW_RESET_M 0x00000001 -#define CRYPTO_SWRESET_SW_RESET_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_IRQTYPE -// -//***************************************************************************** -// Field: [0] LEVEL -// -// If this bit is 0, the interrupt output is a pulse. -// If this bit is set to 1, the interrupt is a level interrupt that must be -// cleared by writing the interrupt clear register. -// This bit is applicable for both interrupt output signals. -#define CRYPTO_IRQTYPE_LEVEL 0x00000001 -#define CRYPTO_IRQTYPE_LEVEL_BITN 0 -#define CRYPTO_IRQTYPE_LEVEL_M 0x00000001 -#define CRYPTO_IRQTYPE_LEVEL_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_IRQEN -// -//***************************************************************************** -// Field: [1] DMA_IN_DONE -// -// If this bit is set to 0, the DMA input done (irq_dma_in_done) interrupt -// output is disabled and remains 0. -// If this bit is set to 1, the DMA input done interrupt output is enabled. -#define CRYPTO_IRQEN_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQEN_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQEN_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQEN_DMA_IN_DONE_S 1 - -// Field: [0] RESULT_AVAIL -// -// If this bit is set to 0, the result available (irq_result_av) interrupt -// output is disabled and remains 0. -// If this bit is set to 1, the result available interrupt output is enabled. -#define CRYPTO_IRQEN_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQEN_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQEN_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQEN_RESULT_AVAIL_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_IRQCLR -// -//***************************************************************************** -// Field: [31] DMA_BUS_ERR -// -// If 1 is written to this bit, the DMA bus error status is cleared. -// Writing 0 has no effect. -#define CRYPTO_IRQCLR_DMA_BUS_ERR 0x80000000 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_BITN 31 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_M 0x80000000 -#define CRYPTO_IRQCLR_DMA_BUS_ERR_S 31 - -// Field: [30] KEY_ST_WR_ERR -// -// If 1 is written to this bit, the key store write error status is cleared. -// Writing 0 has no effect. -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR 0x40000000 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_BITN 30 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_M 0x40000000 -#define CRYPTO_IRQCLR_KEY_ST_WR_ERR_S 30 - -// Field: [29] KEY_ST_RD_ERR -// -// If 1 is written to this bit, the key store read error status is cleared. -// Writing 0 has no effect. -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR 0x20000000 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_BITN 29 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_M 0x20000000 -#define CRYPTO_IRQCLR_KEY_ST_RD_ERR_S 29 - -// Field: [1] DMA_IN_DONE -// -// If 1 is written to this bit, the DMA in done (irq_dma_in_done) interrupt -// output is cleared. -// Writing 0 has no effect. -// Note that clearing an interrupt makes sense only if the interrupt output is -// programmed as level (refer to IRQTYPE). -#define CRYPTO_IRQCLR_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQCLR_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQCLR_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQCLR_DMA_IN_DONE_S 1 - -// Field: [0] RESULT_AVAIL -// -// If 1 is written to this bit, the result available (irq_result_av) interrupt -// output is cleared. -// Writing 0 has no effect. -// Note that clearing an interrupt makes sense only if the interrupt output is -// programmed as level (refer to IRQTYPE). -#define CRYPTO_IRQCLR_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQCLR_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQCLR_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQCLR_RESULT_AVAIL_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_IRQSET -// -//***************************************************************************** -// Field: [1] DMA_IN_DONE -// -// If 1 is written to this bit, the DMA data in done (irq_dma_in_done) -// interrupt output is set to one. -// Writing 0 has no effect. -// If the interrupt configuration register is programmed to pulse, clearing the -// DMA data in done (irq_dma_in_done) interrupt is not needed. If it is -// programmed to level, clearing the interrupt output should be done by writing -// the interrupt clear register (IRQCLR.DMA_IN_DONE). -#define CRYPTO_IRQSET_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQSET_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQSET_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQSET_DMA_IN_DONE_S 1 - -// Field: [0] RESULT_AVAIL -// -// If 1 is written to this bit, the result available (irq_result_av) interrupt -// output is set to one. -// Writing 0 has no effect. -// If the interrupt configuration register is programmed to pulse, clearing the -// result available (irq_result_av) interrupt is not needed. If it is -// programmed to level, clearing the interrupt output should be done by writing -// the interrupt clear register (IRQCLR.RESULT_AVAIL). -#define CRYPTO_IRQSET_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQSET_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQSET_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQSET_RESULT_AVAIL_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_IRQSTAT -// -//***************************************************************************** -// Field: [31] DMA_BUS_ERR -// -// This bit is set when a DMA bus error is detected during a DMA operation. The -// value of this register is held until it is cleared through the -// IRQCLR.DMA_BUS_ERR -// Note: This error is asserted if an error is detected on the AHB master -// interface during a DMA operation. -#define CRYPTO_IRQSTAT_DMA_BUS_ERR 0x80000000 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_BITN 31 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_M 0x80000000 -#define CRYPTO_IRQSTAT_DMA_BUS_ERR_S 31 - -// Field: [30] KEY_ST_WR_ERR -// -// This bit is set when a write error is detected during the DMA write -// operation to the key store memory. The value of this register is held until -// it is cleared through the IRQCLR.KEY_ST_WR_ERR register. -// Note: This error is asserted if a DMA operation does not cover a full key -// area or more areas are written than expected. -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR 0x40000000 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_BITN 30 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_M 0x40000000 -#define CRYPTO_IRQSTAT_KEY_ST_WR_ERR_S 30 - -// Field: [29] KEY_ST_RD_ERR -// -// This bit is set when a read error is detected during the read of a key from -// the key store, while copying it to the AES core. The value of this register -// is held until it is cleared through the IRQCLR.KEY_ST_RD_ERR register. -// Note: This error is asserted if a key location is selected in the key store -// that is not available. -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR 0x20000000 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_BITN 29 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_M 0x20000000 -#define CRYPTO_IRQSTAT_KEY_ST_RD_ERR_S 29 - -// Field: [1] DMA_IN_DONE -// -// This read only bit returns the actual DMA data in done (irq_data_in_done) -// interrupt status of the DMA data in done interrupt output pin -// (irq_data_in_done). -#define CRYPTO_IRQSTAT_DMA_IN_DONE 0x00000002 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_BITN 1 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_M 0x00000002 -#define CRYPTO_IRQSTAT_DMA_IN_DONE_S 1 - -// Field: [0] RESULT_AVAIL -// -// This read only bit returns the actual result available (irq_result_av) -// interrupt status of the result available interrupt output pin -// (irq_result_av). -#define CRYPTO_IRQSTAT_RESULT_AVAIL 0x00000001 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_BITN 0 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_M 0x00000001 -#define CRYPTO_IRQSTAT_RESULT_AVAIL_S 0 - -//***************************************************************************** -// -// Register: CRYPTO_O_HWVER -// -//***************************************************************************** -// Field: [27:24] HW_MAJOR_VER -// -// Major version number -#define CRYPTO_HWVER_HW_MAJOR_VER_W 4 -#define CRYPTO_HWVER_HW_MAJOR_VER_M 0x0F000000 -#define CRYPTO_HWVER_HW_MAJOR_VER_S 24 - -// Field: [23:20] HW_MINOR_VER -// -// Minor version number -#define CRYPTO_HWVER_HW_MINOR_VER_W 4 -#define CRYPTO_HWVER_HW_MINOR_VER_M 0x00F00000 -#define CRYPTO_HWVER_HW_MINOR_VER_S 20 - -// Field: [19:16] HW_PATCH_LVL -// -// Patch level -// Starts at 0 at first delivery of this version -#define CRYPTO_HWVER_HW_PATCH_LVL_W 4 -#define CRYPTO_HWVER_HW_PATCH_LVL_M 0x000F0000 -#define CRYPTO_HWVER_HW_PATCH_LVL_S 16 - -// Field: [15:8] VER_NUM_COMPL -// -// These bits simply contain the complement of bits [7:0] (0x87), used by a -// driver to ascertain that the EIP-120t register is indeed read. -#define CRYPTO_HWVER_VER_NUM_COMPL_W 8 -#define CRYPTO_HWVER_VER_NUM_COMPL_M 0x0000FF00 -#define CRYPTO_HWVER_VER_NUM_COMPL_S 8 - -// Field: [7:0] VER_NUM -// -// These bits encode the EIP number for the EIP-120t, this field contains the -// value 120 (decimal) or 0x78. -#define CRYPTO_HWVER_VER_NUM_W 8 -#define CRYPTO_HWVER_VER_NUM_M 0x000000FF -#define CRYPTO_HWVER_VER_NUM_S 0 - - -#endif // __CRYPTO__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h deleted file mode 100644 index fc93c11645d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi.h +++ /dev/null @@ -1,197 +0,0 @@ -/****************************************************************************** -* Filename: hw_ddi.h -* Revised: 2017-06-05 12:13:49 +0200 (Mon, 05 Jun 2017) -* Revision: 49096 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_DDI_H__ -#define __HW_DDI_H__ - -//***************************************************************************** -// -// This file contains macros for controlling the DDI master and -// accessing DDI Slave registers via the DDI Master. -// There are 3 categories of macros in this file: -// - macros that provide an offset to a register -// located within the DDI Master itself. -// - macros that define bits or bitfields -// within the DDI Master Registers. -// - macros that provide an "instruction offset" -// that are used when accessing a DDI Slave. -// -// The macros that that provide DDI Master register offsets and -// define bits and bitfields for those registers are the typical -// macros that appear in most hw_.h header files. In -// the following example DDI_O_CFG is a macro for a -// register offset and DDI_CFG_WAITFORACK is a macro for -// a bit in that register. This example code will set the WAITFORACK -// bit in register DDI_O_CFG of the DDI Master. (Note: this -// access the Master not the Slave). -// -// HWREG(AUX_OSCDDI_BASE + DDI_O_CFG) |= DDI_CFG_WAITFORACK; -// -// -// The "instruction offset" macros are used to pass an instruction to -// the DDI Master when accessing DDI slave registers. These macros are -// only used when accessing DDI Slave Registers. (Remember DDI -// Master Registers are accessed normally). -// -// The instructions supported when accessing a DDI Slave Regsiter follow: -// - Direct Access to a DDI Slave register. I.e. read or -// write the register. -// - Set the specified bits in a DDI Slave register. -// - Clear the specified bits in a DDI Slave register. -// - Mask write of 4 bits to the a DDI Slave register. -// - Mask write of 8 bits to the a DDI Slave register. -// - Mask write of 16 bits to the a DDI Slave register. -// -// Note: only the "Direct Access" offset should be used when reading -// a DDI Slave register. Only 8- and 16-bit reads are supported. -// -// The generic format of using this marcos for a read follows: -// // read low 16-bits in DDI_SLAVE_OFF -// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR); -// -// // read high 16-bits in DDI_SLAVE_OFF -// // add 2 for data[31:16] -// myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_DIR); - -// // read data[31:24] byte in DDI_SLAVE_OFF -// // add 3 for data[31:24] -// myuchar = HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 3 + DDI_O_DIR); -// -// Notes: In the above example: -// - DDI_MASTER_BASE is the base address of the DDI Master defined -// in the hw_memmap.h header file. -// - DDI_SLAVE_OFF is the DDI Slave offset defined in the -// hw_.h header file (e.g. hw_osc_top.h for the oscsc -// oscillator modules. -// - DDI_O_DIR is the "instruction offset" macro defined in this -// file that specifies the Direct Access instruction. -// -// Writes can use any of the "instruction macros". -// The following examples do a "direct write" to DDI Slave register -// DDI_SLAVE_OFF using different size operands: -// -// // ---------- DIRECT WRITES ---------- -// // Write 32-bits aligned -// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x12345678; - -// // Write 16-bits aligned to high 16-bits then low 16-bits -// // Add 2 to get to high 16-bits. -// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0xabcd; -// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0xef01; -// -// // Write each byte at DDI_SLAVE_OFF, one at a time. -// // Add 1,2,or 3 to get to bytes 1,2, or 3. -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x33; -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 1) = 0x44; -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0x55; -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 3) = 0x66; -// -// // ---------- SET/CLR ---------- -// The set and clear functions behave similarly to eachother. Each -// can be performed on an 8-, 16-, or 32-bit operand. -// Examples follow: -// // Set all odd bits in a 32-bit words -// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_SET) = 0xaaaaaaaa; -// -// // Clear all bits in byte 2 (data[23:16]) using 32-bit operand -// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_CLR) = 0x00ff0000; -// -// // Set even bits in byte 2 (data[23:16]) using 8-bit operand -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_CLR) = 0x55; -// -// // ---------- MASKED WRITES ---------- -// The mask writes are a bit different. They operate on nibbles, -// bytes, and 16-bit elements. Two operands are required; a 'mask' -// and 'data'; The operands are concatenated and written to the master. -// e.g. the mask and data are combined as follows for a 16 bit masked -// write: -// (mask << 16) | data; -// Examples follow: -// -// // Write 5555 to low 16-bits of DDI_SLAVE_OFF register -// // a long write is needed (32-bits). -// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xffff5555; - -// // Write 1AA to data bits 24:16 in high 16-bits of DDI_SLAVE_OFF register -// // Note add 4 for high 16-bits at DDI_SLAVE_OFF; mask is 1ff! -// HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 4) = 0x01ff01aa; -// -// // Do an 8 bit masked write of 00 to low byte of register (data[7:0]). -// // a short write is needed (16-bits). -// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xff00; -// -// // Do an 8 bit masked write of 11 to byte 1 of register (data[15:8]). -// // add 2 to get to byte 1. -// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 2) = 0xff11; -// -// // Do an 8 bit masked write of 33 to high byte of register (data[31:24]). -// // add 6 to get to byte 3. -// HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 6) = 0xff33; -// -// // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). -// // Byte write is needed. -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xf7; -// -// // Do an 4 bit masked write of 4 to data[7:4]). -// // Add 1 for next nibble -// HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 1) = 0xf4; -// -//***************************************************************************** - -//***************************************************************************** -// -// The following are defines for the DDI master instruction offsets. -// -//***************************************************************************** -#define DDI_O_DIR 0x00000000 // Offset for the direct access instruction -#define DDI_O_SET 0x00000080 // Offset for 'Set' instruction. -#define DDI_O_CLR 0x00000100 // Offset for 'Clear' instruction. -#define DDI_O_MASK4B 0x00000200 // Offset for 4-bit masked access. - // Data bit[n] is written if mask bit[n] is set ('1'). - // Bits 7:4 are mask. Bits 3:0 are data. - // Requires 'byte' write. -#define DDI_O_MASK8B 0x00000300 // Offset for 8-bit masked access. - // Data bit[n] is written if mask bit[n] is set ('1'). - // Bits 15:8 are mask. Bits 7:0 are data. - // Requires 'short' write. -#define DDI_O_MASK16B 0x00000400 // Offset for 16-bit masked access. - // Data bit[n] is written if mask bit[n] is set ('1'). - // Bits 31:16 are mask. Bits 15:0 are data. - // Requires 'long' write. - - - -#endif // __HW_DDI_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h deleted file mode 100644 index ee49e270950..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ddi_0_osc.h +++ /dev/null @@ -1,1153 +0,0 @@ -/****************************************************************************** -* Filename: hw_ddi_0_osc_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_DDI_0_OSC_H__ -#define __HW_DDI_0_OSC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// DDI_0_OSC component -// -//***************************************************************************** -// Control 0 -#define DDI_0_OSC_O_CTL0 0x00000000 - -// Control 1 -#define DDI_0_OSC_O_CTL1 0x00000004 - -// RADC External Configuration -#define DDI_0_OSC_O_RADCEXTCFG 0x00000008 - -// Amplitude Compensation Control -#define DDI_0_OSC_O_AMPCOMPCTL 0x0000000C - -// Amplitude Compensation Threshold 1 -#define DDI_0_OSC_O_AMPCOMPTH1 0x00000010 - -// Amplitude Compensation Threshold 2 -#define DDI_0_OSC_O_AMPCOMPTH2 0x00000014 - -// Analog Bypass Values 1 -#define DDI_0_OSC_O_ANABYPASSVAL1 0x00000018 - -// Internal -#define DDI_0_OSC_O_ANABYPASSVAL2 0x0000001C - -// Analog Test Control -#define DDI_0_OSC_O_ATESTCTL 0x00000020 - -// ADC Doubler Nanoamp Control -#define DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL 0x00000024 - -// XOSCHF Control -#define DDI_0_OSC_O_XOSCHFCTL 0x00000028 - -// Low Frequency Oscillator Control -#define DDI_0_OSC_O_LFOSCCTL 0x0000002C - -// RCOSCHF Control -#define DDI_0_OSC_O_RCOSCHFCTL 0x00000030 - -// RCOSC_MF Control -#define DDI_0_OSC_O_RCOSCMFCTL 0x00000034 - -// Status 0 -#define DDI_0_OSC_O_STAT0 0x0000003C - -// Status 1 -#define DDI_0_OSC_O_STAT1 0x00000040 - -// Status 2 -#define DDI_0_OSC_O_STAT2 0x00000044 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_CTL0 -// -//***************************************************************************** -// Field: [31] XTAL_IS_24M -// -// Set based on the accurate high frequency XTAL. -// ENUMs: -// 24M Internal. Only to be used through TI provided API. -// 48M Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_S 31 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_24M 0x80000000 -#define DDI_0_OSC_CTL0_XTAL_IS_24M_48M 0x00000000 - -// Field: [29] BYPASS_XOSC_LF_CLK_QUAL -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000 -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_M 0x20000000 -#define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL_S 29 - -// Field: [28] BYPASS_RCOSC_LF_CLK_QUAL -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000 -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_M 0x10000000 -#define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL_S 28 - -// Field: [27:26] DOUBLER_START_DURATION -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_W 2 -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_M 0x0C000000 -#define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_S 26 - -// Field: [25] DOUBLER_RESET_DURATION -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x02000000 -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_M 0x02000000 -#define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION_S 25 - -// Field: [24] CLK_DCDC_SRC_SEL -// -// Select DCDC clock source. -// -// 0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC -// 1: CLK_DCDC is always 48 MHz clock from RCOSC -#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL 0x01000000 -#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_M 0x01000000 -#define DDI_0_OSC_CTL0_CLK_DCDC_SRC_SEL_S 24 - -// Field: [14] HPOSC_MODE_EN -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN 0x00004000 -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_M 0x00004000 -#define DDI_0_OSC_CTL0_HPOSC_MODE_EN_S 14 - -// Field: [12] RCOSC_LF_TRIMMED -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x00001000 -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_M 0x00001000 -#define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED_S 12 - -// Field: [11] XOSC_HF_POWER_MODE -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x00000800 -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_M 0x00000800 -#define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE_S 11 - -// Field: [10] XOSC_LF_DIG_BYPASS -// -// Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf -// clock. -// -// 0: Use 32kHz XOSC as xosc_lf clock source -// 1: Use digital input (from AON) as xosc_lf clock source. -// -// This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf -// as the sclk_lf source. The muxing performed by this bit is not glitch free. -// The following procedure must be followed when changing this field to avoid -// glitches on sclk_lf. -// -// 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock -// source. -// 2) Set or clear this bit to bypass or not bypass the xosc_lf. -// 3) Set SCLK_LF_SRC_SEL to use xosc_lf. -// -// It is recommended that either the rcosc_hf or xosc_hf (whichever is -// currently active) be selected as the source in step 1 above. This provides a -// faster clock change. -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x00000400 -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_M 0x00000400 -#define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS_S 10 - -// Field: [9] CLK_LOSS_EN -// -// Enable clock loss detection and hence the indicators to the system -// controller. Checks both SCLK_HF, SCLK_MF and SCLK_LF clock loss indicators. -// -// 0: Disable -// 1: Enable -// -// Clock loss detection must be disabled when changing the sclk_lf source. -// STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf -// source has completed. -#define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x00000200 -#define DDI_0_OSC_CTL0_CLK_LOSS_EN_M 0x00000200 -#define DDI_0_OSC_CTL0_CLK_LOSS_EN_S 9 - -// Field: [8:7] ACLK_TDC_SRC_SEL -// -// Source select for aclk_tdc. -// -// 00: RCOSC_HF (48MHz) -// 01: RCOSC_HF (24MHz) -// 10: XOSC_HF (24MHz) -// 11: Not used -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_M 0x00000180 -#define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_S 7 - -// Field: [6:4] ACLK_REF_SRC_SEL -// -// Source select for aclk_ref -// -// 000: RCOSC_HF derived (31.25kHz) -// 001: XOSC_HF derived (31.25kHz) -// 010: RCOSC_LF (32kHz) -// 011: XOSC_LF (32.768kHz) -// 100: RCOSC_MF (2MHz) -// 101-111: Not used -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_W 3 -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_M 0x00000070 -#define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_S 4 - -// Field: [3:2] SCLK_LF_SRC_SEL -// -// Source select for sclk_lf -// ENUMs: -// XOSCLF Low frequency XOSC -// RCOSCLF Low frequency RCOSC -// XOSCHFDLF Low frequency clock derived from High Frequency -// XOSC -// RCOSCHFDLF Low frequency clock derived from High Frequency -// RCOSC -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_W 2 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_M 0x0000000C -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_S 2 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCLF 0x0000000C -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCLF 0x00000008 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_XOSCHFDLF 0x00000004 -#define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_RCOSCHFDLF 0x00000000 - -// Field: [0] SCLK_HF_SRC_SEL -// -// Source select for sclk_hf. -// ENUMs: -// XOSC High frequency XOSC clock -// RCOSC High frequency RCOSC clock -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_M 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_S 0 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x00000001 -#define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x00000000 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_CTL1 -// -//***************************************************************************** -// Field: [22:18] RCOSCHFCTRIMFRACT -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_W 5 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_M 0x007C0000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_S 18 - -// Field: [17] RCOSCHFCTRIMFRACT_EN -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN 0x00020000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_M 0x00020000 -#define DDI_0_OSC_CTL1_RCOSCHFCTRIMFRACT_EN_S 17 - -// Field: [1:0] XOSC_HF_FAST_START -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_W 2 -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_M 0x00000003 -#define DDI_0_OSC_CTL1_XOSC_HF_FAST_START_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_RADCEXTCFG -// -//***************************************************************************** -// Field: [31:22] HPM_IBIAS_WAIT_CNT -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_W 10 -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_M 0xFFC00000 -#define DDI_0_OSC_RADCEXTCFG_HPM_IBIAS_WAIT_CNT_S 22 - -// Field: [21:16] LPM_IBIAS_WAIT_CNT -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_W 6 -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_M 0x003F0000 -#define DDI_0_OSC_RADCEXTCFG_LPM_IBIAS_WAIT_CNT_S 16 - -// Field: [15:12] IDAC_STEP -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_W 4 -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_M 0x0000F000 -#define DDI_0_OSC_RADCEXTCFG_IDAC_STEP_S 12 - -// Field: [11:6] RADC_DAC_TH -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_W 6 -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_M 0x00000FC0 -#define DDI_0_OSC_RADCEXTCFG_RADC_DAC_TH_S 6 - -// Field: [5] RADC_MODE_IS_SAR -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR 0x00000020 -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_M 0x00000020 -#define DDI_0_OSC_RADCEXTCFG_RADC_MODE_IS_SAR_S 5 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_AMPCOMPCTL -// -//***************************************************************************** -// Field: [30] AMPCOMP_REQ_MODE -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE 0x40000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_M 0x40000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_REQ_MODE_S 30 - -// Field: [29:28] AMPCOMP_FSM_UPDATE_RATE -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// 250KHZ Internal. Only to be used through TI provided API. -// 500KHZ Internal. Only to be used through TI provided API. -// 1MHZ Internal. Only to be used through TI provided API. -// 2MHZ Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_W 2 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_M 0x30000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_S 28 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_250KHZ 0x30000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_500KHZ 0x20000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_1MHZ 0x10000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_FSM_UPDATE_RATE_2MHZ 0x00000000 - -// Field: [27] AMPCOMP_SW_CTRL -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL 0x08000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_M 0x08000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_CTRL_S 27 - -// Field: [26] AMPCOMP_SW_EN -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN 0x04000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_M 0x04000000 -#define DDI_0_OSC_AMPCOMPCTL_AMPCOMP_SW_EN_S 26 - -// Field: [23:20] IBIAS_OFFSET -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_M 0x00F00000 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_OFFSET_S 20 - -// Field: [19:16] IBIAS_INIT -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_M 0x000F0000 -#define DDI_0_OSC_AMPCOMPCTL_IBIAS_INIT_S 16 - -// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_W 8 -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 -#define DDI_0_OSC_AMPCOMPCTL_LPM_IBIAS_WAIT_CNT_FINAL_S 8 - -// Field: [7:4] CAP_STEP -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_W 4 -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_M 0x000000F0 -#define DDI_0_OSC_AMPCOMPCTL_CAP_STEP_S 4 - -// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_W 4 -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F -#define DDI_0_OSC_AMPCOMPCTL_IBIASCAP_HPTOLP_OL_CNT_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_AMPCOMPTH1 -// -//***************************************************************************** -// Field: [23:18] HPMRAMP3_LTH -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_M 0x00FC0000 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_LTH_S 18 - -// Field: [15:10] HPMRAMP3_HTH -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_M 0x0000FC00 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP3_HTH_S 10 - -// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_W 4 -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 -#define DDI_0_OSC_AMPCOMPTH1_IBIASCAP_LPTOHP_OL_CNT_S 6 - -// Field: [5:0] HPMRAMP1_TH -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_W 6 -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_M 0x0000003F -#define DDI_0_OSC_AMPCOMPTH1_HPMRAMP1_TH_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_AMPCOMPTH2 -// -//***************************************************************************** -// Field: [31:26] LPMUPDATE_LTH -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_W 6 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_M 0xFC000000 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_LTH_S 26 - -// Field: [23:18] LPMUPDATE_HTH -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_W 6 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_M 0x00FC0000 -#define DDI_0_OSC_AMPCOMPTH2_LPMUPDATE_HTH_S 18 - -// Field: [15:10] ADC_COMP_AMPTH_LPM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_W 6 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_LPM_S 10 - -// Field: [7:2] ADC_COMP_AMPTH_HPM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_W 6 -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_M 0x000000FC -#define DDI_0_OSC_AMPCOMPTH2_ADC_COMP_AMPTH_HPM_S 2 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_ANABYPASSVAL1 -// -//***************************************************************************** -// Field: [19:16] XOSC_HF_ROW_Q12 -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_W 4 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_M 0x000F0000 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_ROW_Q12_S 16 - -// Field: [15:0] XOSC_HF_COLUMN_Q12 -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_W 16 -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_M 0x0000FFFF -#define DDI_0_OSC_ANABYPASSVAL1_XOSC_HF_COLUMN_Q12_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_ANABYPASSVAL2 -// -//***************************************************************************** -// Field: [13:0] XOSC_HF_IBIASTHERM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_W 14 -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_M 0x00003FFF -#define DDI_0_OSC_ANABYPASSVAL2_XOSC_HF_IBIASTHERM_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_ATESTCTL -// -//***************************************************************************** -// Field: [31] SCLK_LF_AUX_EN -// -// Enable 32 kHz clock to AUX_COMPB. -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN 0x80000000 -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_M 0x80000000 -#define DDI_0_OSC_ATESTCTL_SCLK_LF_AUX_EN_S 31 - -// Field: [15:14] TEST_RCOSCMF -// -// Test mode control for RCOSC_MF -// -// 0x0: test modes disabled -// 0x1: boosted bias current into self biased inverter -// 0x2: clock qualification disabled -// 0x3: boosted bias current into self biased inverter + clock qualification -// disabled -#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_W 2 -#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_M 0x0000C000 -#define DDI_0_OSC_ATESTCTL_TEST_RCOSCMF_S 14 - -// Field: [13:12] ATEST_RCOSCMF -// -// ATEST control for RCOSC_MF -// -// 0x0: ATEST disabled -// 0x1: ATEST enabled, VDD_LOCAL connected, ATEST internal to **RCOSC_MF* -// enabled to send out 2MHz clock. -// 0x2: ATEST disabled -// 0x3: ATEST enabled, bias current connected, ATEST internal to **RCOSC_MF* -// enabled to send out 2MHz clock. -#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_W 2 -#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_M 0x00003000 -#define DDI_0_OSC_ATESTCTL_ATEST_RCOSCMF_S 12 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_ADCDOUBLERNANOAMPCTL -// -//***************************************************************************** -// Field: [24] NANOAMP_BIAS_ENABLE -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE 0x01000000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_M 0x01000000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_NANOAMP_BIAS_ENABLE_S 24 - -// Field: [23] SPARE23 -// -// Software should not rely on the value of a reserved. Writing any other value -// than the reset value may result in undefined behavior -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23 0x00800000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_M 0x00800000 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_SPARE23_S 23 - -// Field: [5] ADC_SH_MODE_EN -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN 0x00000020 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_M 0x00000020 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_MODE_EN_S 5 - -// Field: [4] ADC_SH_VBUF_EN -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN 0x00000010 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_M 0x00000010 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_SH_VBUF_EN_S 4 - -// Field: [1:0] ADC_IREF_CTRL -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_W 2 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_M 0x00000003 -#define DDI_0_OSC_ADCDOUBLERNANOAMPCTL_ADC_IREF_CTRL_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_XOSCHFCTL -// -//***************************************************************************** -// Field: [13] TCXO_MODE_XOSC_HF_EN -// -// If this register is 1 when TCXO_MODE is 1, then the XOSC_HF is enabled, -// turning on the XOSC_HF bias current allowing a DC bias point to be provided -// to the clipped-sine wave clock signal on external input. -#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN 0x00002000 -#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_M 0x00002000 -#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_XOSC_HF_EN_S 13 - -// Field: [12] TCXO_MODE -// -// If this register is 1 when BYPASS is 1, this will enable clock -// qualification on the TCXO clock on external input. This register has no -// effect when BYPASS is 0. -#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE 0x00001000 -#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_M 0x00001000 -#define DDI_0_OSC_XOSCHFCTL_TCXO_MODE_S 12 - -// Field: [9:8] PEAK_DET_ITRIM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_W 2 -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_M 0x00000300 -#define DDI_0_OSC_XOSCHFCTL_PEAK_DET_ITRIM_S 8 - -// Field: [6] BYPASS -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_BYPASS 0x00000040 -#define DDI_0_OSC_XOSCHFCTL_BYPASS_M 0x00000040 -#define DDI_0_OSC_XOSCHFCTL_BYPASS_S 6 - -// Field: [4:2] HP_BUF_ITRIM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_W 3 -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_M 0x0000001C -#define DDI_0_OSC_XOSCHFCTL_HP_BUF_ITRIM_S 2 - -// Field: [1:0] LP_BUF_ITRIM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_W 2 -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_M 0x00000003 -#define DDI_0_OSC_XOSCHFCTL_LP_BUF_ITRIM_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_LFOSCCTL -// -//***************************************************************************** -// Field: [23:22] XOSCLF_REGULATOR_TRIM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_W 2 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_M 0x00C00000 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_REGULATOR_TRIM_S 22 - -// Field: [21:18] XOSCLF_CMIRRWR_RATIO -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_W 4 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_M 0x003C0000 -#define DDI_0_OSC_LFOSCCTL_XOSCLF_CMIRRWR_RATIO_S 18 - -// Field: [9:8] RCOSCLF_RTUNE_TRIM -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// 6P0MEG Internal. Only to be used through TI provided API. -// 6P5MEG Internal. Only to be used through TI provided API. -// 7P0MEG Internal. Only to be used through TI provided API. -// 7P5MEG Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_W 2 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_M 0x00000300 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_S 8 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P0MEG 0x00000300 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_6P5MEG 0x00000200 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P0MEG 0x00000100 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_RTUNE_TRIM_7P5MEG 0x00000000 - -// Field: [7:0] RCOSCLF_CTUNE_TRIM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_W 8 -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_M 0x000000FF -#define DDI_0_OSC_LFOSCCTL_RCOSCLF_CTUNE_TRIM_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_RCOSCHFCTL -// -//***************************************************************************** -// Field: [15:8] RCOSCHF_CTRIM -// -// Internal. Only to be used through TI provided API. -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_W 8 -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_M 0x0000FF00 -#define DDI_0_OSC_RCOSCHFCTL_RCOSCHF_CTRIM_S 8 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_RCOSCMFCTL -// -//***************************************************************************** -// Field: [15:9] RCOSC_MF_CAP_ARRAY -// -// Adjust RCOSC_MF capacitor array. -// -// 0x0: nominal frequency, 0.625pF -// 0x40: highest frequency, 0.125pF -// 0x3F: lowest frequency, 1.125pF -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_W 7 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_M 0x0000FE00 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_CAP_ARRAY_S 9 - -// Field: [8] RCOSC_MF_REG_SEL -// -// Choose regulator type. -// -// 0: default -// 1: alternate -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL 0x00000100 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_M 0x00000100 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_REG_SEL_S 8 - -// Field: [7:6] RCOSC_MF_RES_COARSE -// -// Select coarse resistor for frequency adjustment. -// -// 0x0: 400kohms, default -// 0x1: 300kohms, min -// 0x2: 600kohms, max -// 0x3: 500kohms -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_W 2 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_M 0x000000C0 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_COARSE_S 6 - -// Field: [5:4] RCOSC_MF_RES_FINE -// -// Select fine resistor for frequency adjustment. -// -// 0x0: 11kohms, minimum resistance, max freq -// 0x1: 13kohms -// 0x2: 16kohms -// 0x3: 20kohms, max resistance, min freq -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_W 2 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_M 0x00000030 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_RES_FINE_S 4 - -// Field: [3:0] RCOSC_MF_BIAS_ADJ -// -// Adjusts bias current to RCOSC_MF. -// -// 0x8 minimum current -// 0x0 default current -// 0x7 maximum current -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_W 4 -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_M 0x0000000F -#define DDI_0_OSC_RCOSCMFCTL_RCOSC_MF_BIAS_ADJ_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_STAT0 -// -//***************************************************************************** -// Field: [30:29] SCLK_LF_SRC -// -// Indicates source for the sclk_lf -// ENUMs: -// XOSCLF Low frequency XOSC -// RCOSCLF Low frequency RCOSC -// XOSCHFDLF Low frequency clock derived from High Frequency -// XOSC -// RCOSCHFDLF Low frequency clock derived from High Frequency -// RCOSC -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_W 2 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_M 0x60000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_S 29 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCLF 0x60000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCLF 0x40000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_XOSCHFDLF 0x20000000 -#define DDI_0_OSC_STAT0_SCLK_LF_SRC_RCOSCHFDLF 0x00000000 - -// Field: [28] SCLK_HF_SRC -// -// Indicates source for the sclk_hf -// ENUMs: -// XOSC High frequency XOSC -// RCOSC High frequency RCOSC clock -#define DDI_0_OSC_STAT0_SCLK_HF_SRC 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_M 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_S 28 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_XOSC 0x10000000 -#define DDI_0_OSC_STAT0_SCLK_HF_SRC_RCOSC 0x00000000 - -// Field: [22] RCOSC_HF_EN -// -// RCOSC_HF_EN -#define DDI_0_OSC_STAT0_RCOSC_HF_EN 0x00400000 -#define DDI_0_OSC_STAT0_RCOSC_HF_EN_M 0x00400000 -#define DDI_0_OSC_STAT0_RCOSC_HF_EN_S 22 - -// Field: [21] RCOSC_LF_EN -// -// RCOSC_LF_EN -#define DDI_0_OSC_STAT0_RCOSC_LF_EN 0x00200000 -#define DDI_0_OSC_STAT0_RCOSC_LF_EN_M 0x00200000 -#define DDI_0_OSC_STAT0_RCOSC_LF_EN_S 21 - -// Field: [20] XOSC_LF_EN -// -// XOSC_LF_EN -#define DDI_0_OSC_STAT0_XOSC_LF_EN 0x00100000 -#define DDI_0_OSC_STAT0_XOSC_LF_EN_M 0x00100000 -#define DDI_0_OSC_STAT0_XOSC_LF_EN_S 20 - -// Field: [19] CLK_DCDC_RDY -// -// CLK_DCDC_RDY -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY 0x00080000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_M 0x00080000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_S 19 - -// Field: [18] CLK_DCDC_RDY_ACK -// -// CLK_DCDC_RDY_ACK -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK 0x00040000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_M 0x00040000 -#define DDI_0_OSC_STAT0_CLK_DCDC_RDY_ACK_S 18 - -// Field: [17] SCLK_HF_LOSS -// -// Indicates sclk_hf is lost -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS 0x00020000 -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_M 0x00020000 -#define DDI_0_OSC_STAT0_SCLK_HF_LOSS_S 17 - -// Field: [16] SCLK_LF_LOSS -// -// Indicates sclk_lf is lost -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS 0x00010000 -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_M 0x00010000 -#define DDI_0_OSC_STAT0_SCLK_LF_LOSS_S 16 - -// Field: [15] XOSC_HF_EN -// -// Indicates that XOSC_HF is enabled. -#define DDI_0_OSC_STAT0_XOSC_HF_EN 0x00008000 -#define DDI_0_OSC_STAT0_XOSC_HF_EN_M 0x00008000 -#define DDI_0_OSC_STAT0_XOSC_HF_EN_S 15 - -// Field: [13] XB_48M_CLK_EN -// -// Indicates that the 48MHz clock from the DOUBLER is enabled. -// -// It will be enabled if 24 or 48 MHz crystal is used (enabled in doubler -// bypass for the 48MHz crystal). -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN 0x00002000 -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_M 0x00002000 -#define DDI_0_OSC_STAT0_XB_48M_CLK_EN_S 13 - -// Field: [11] XOSC_HF_LP_BUF_EN -// -// XOSC_HF_LP_BUF_EN -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN 0x00000800 -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_M 0x00000800 -#define DDI_0_OSC_STAT0_XOSC_HF_LP_BUF_EN_S 11 - -// Field: [10] XOSC_HF_HP_BUF_EN -// -// XOSC_HF_HP_BUF_EN -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN 0x00000400 -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_M 0x00000400 -#define DDI_0_OSC_STAT0_XOSC_HF_HP_BUF_EN_S 10 - -// Field: [8] ADC_THMET -// -// ADC_THMET -#define DDI_0_OSC_STAT0_ADC_THMET 0x00000100 -#define DDI_0_OSC_STAT0_ADC_THMET_M 0x00000100 -#define DDI_0_OSC_STAT0_ADC_THMET_S 8 - -// Field: [7] ADC_DATA_READY -// -// indicates when adc_data is ready. -#define DDI_0_OSC_STAT0_ADC_DATA_READY 0x00000080 -#define DDI_0_OSC_STAT0_ADC_DATA_READY_M 0x00000080 -#define DDI_0_OSC_STAT0_ADC_DATA_READY_S 7 - -// Field: [6:1] ADC_DATA -// -// adc_data -#define DDI_0_OSC_STAT0_ADC_DATA_W 6 -#define DDI_0_OSC_STAT0_ADC_DATA_M 0x0000007E -#define DDI_0_OSC_STAT0_ADC_DATA_S 1 - -// Field: [0] PENDINGSCLKHFSWITCHING -// -// Indicates when SCLK_HF clock source is ready to be switched -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING 0x00000001 -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_M 0x00000001 -#define DDI_0_OSC_STAT0_PENDINGSCLKHFSWITCHING_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_STAT1 -// -//***************************************************************************** -// Field: [31:28] RAMPSTATE -// -// AMPCOMP FSM State -// ENUMs: -// FAST_START_SETTLE FAST_START_SETTLE -// FAST_START FAST_START -// DUMMY_TO_INIT_1 DUMMY_TO_INIT_1 -// IDAC_DEC_W_MEASURE IDAC_DECREMENT_WITH_MEASURE -// IBIAS_INC IBIAS_INCREMENT -// LPM_UPDATE LPM_UPDATE -// IBIAS_DEC_W_MEASURE IBIAS_DECREMENT_WITH_MEASURE -// IBIAS_CAP_UPDATE IBIAS_CAP_UPDATE -// IDAC_INCREMENT IDAC_INCREMENT -// HPM_UPDATE HPM_UPDATE -// HPM_RAMP3 HPM_RAMP3 -// HPM_RAMP2 HPM_RAMP2 -// HPM_RAMP1 HPM_RAMP1 -// INITIALIZATION INITIALIZATION -// RESET RESET -#define DDI_0_OSC_STAT1_RAMPSTATE_W 4 -#define DDI_0_OSC_STAT1_RAMPSTATE_M 0xF0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_S 28 -#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START_SETTLE 0xE0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_FAST_START 0xD0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_DUMMY_TO_INIT_1 0xC0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_DEC_W_MEASURE 0xB0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_INC 0xA0000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_LPM_UPDATE 0x90000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_DEC_W_MEASURE 0x80000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IBIAS_CAP_UPDATE 0x70000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_IDAC_INCREMENT 0x60000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_UPDATE 0x50000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP3 0x40000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP2 0x30000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_HPM_RAMP1 0x20000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_INITIALIZATION 0x10000000 -#define DDI_0_OSC_STAT1_RAMPSTATE_RESET 0x00000000 - -// Field: [27:22] HPM_UPDATE_AMP -// -// XOSC_HF amplitude during HPM_UPDATE state. -// When amplitude compensation of XOSC_HF is enabled in high performance mode, -// this value is the amplitude of the crystal oscillations measured by the -// on-chip oscillator ADC, divided by 15 mV. For example, a value of 0x20 -// would indicate that the amplitude of the crystal is approximately 480 mV. -// To enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero -// value. -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_W 6 -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_M 0x0FC00000 -#define DDI_0_OSC_STAT1_HPM_UPDATE_AMP_S 22 - -// Field: [21:16] LPM_UPDATE_AMP -// -// XOSC_HF amplitude during LPM_UPDATE state -// When amplitude compensation of XOSC_HF is enabled in low power mode, this -// value is the amplitude of the crystal oscillations measured by the on-chip -// oscillator ADC, divided by 15 mV. For example, a value of 0x20 would -// indicate that the amplitude of the crystal is approximately 480 mV. To -// enable amplitude compensation, AON_WUC OSCCFG must be set to a non-zero -// value. -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_W 6 -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_M 0x003F0000 -#define DDI_0_OSC_STAT1_LPM_UPDATE_AMP_S 16 - -// Field: [15] FORCE_RCOSC_HF -// -// force_rcosc_hf -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF 0x00008000 -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_M 0x00008000 -#define DDI_0_OSC_STAT1_FORCE_RCOSC_HF_S 15 - -// Field: [14] SCLK_HF_EN -// -// SCLK_HF_EN -#define DDI_0_OSC_STAT1_SCLK_HF_EN 0x00004000 -#define DDI_0_OSC_STAT1_SCLK_HF_EN_M 0x00004000 -#define DDI_0_OSC_STAT1_SCLK_HF_EN_S 14 - -// Field: [13] SCLK_MF_EN -// -// SCLK_MF_EN -#define DDI_0_OSC_STAT1_SCLK_MF_EN 0x00002000 -#define DDI_0_OSC_STAT1_SCLK_MF_EN_M 0x00002000 -#define DDI_0_OSC_STAT1_SCLK_MF_EN_S 13 - -// Field: [12] ACLK_ADC_EN -// -// ACLK_ADC_EN -#define DDI_0_OSC_STAT1_ACLK_ADC_EN 0x00001000 -#define DDI_0_OSC_STAT1_ACLK_ADC_EN_M 0x00001000 -#define DDI_0_OSC_STAT1_ACLK_ADC_EN_S 12 - -// Field: [11] ACLK_TDC_EN -// -// ACLK_TDC_EN -#define DDI_0_OSC_STAT1_ACLK_TDC_EN 0x00000800 -#define DDI_0_OSC_STAT1_ACLK_TDC_EN_M 0x00000800 -#define DDI_0_OSC_STAT1_ACLK_TDC_EN_S 11 - -// Field: [10] ACLK_REF_EN -// -// ACLK_REF_EN -#define DDI_0_OSC_STAT1_ACLK_REF_EN 0x00000400 -#define DDI_0_OSC_STAT1_ACLK_REF_EN_M 0x00000400 -#define DDI_0_OSC_STAT1_ACLK_REF_EN_S 10 - -// Field: [9] CLK_CHP_EN -// -// CLK_CHP_EN -#define DDI_0_OSC_STAT1_CLK_CHP_EN 0x00000200 -#define DDI_0_OSC_STAT1_CLK_CHP_EN_M 0x00000200 -#define DDI_0_OSC_STAT1_CLK_CHP_EN_S 9 - -// Field: [8] CLK_DCDC_EN -// -// CLK_DCDC_EN -#define DDI_0_OSC_STAT1_CLK_DCDC_EN 0x00000100 -#define DDI_0_OSC_STAT1_CLK_DCDC_EN_M 0x00000100 -#define DDI_0_OSC_STAT1_CLK_DCDC_EN_S 8 - -// Field: [7] SCLK_HF_GOOD -// -// SCLK_HF_GOOD -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD 0x00000080 -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_M 0x00000080 -#define DDI_0_OSC_STAT1_SCLK_HF_GOOD_S 7 - -// Field: [6] SCLK_MF_GOOD -// -// SCLK_MF_GOOD -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD 0x00000040 -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_M 0x00000040 -#define DDI_0_OSC_STAT1_SCLK_MF_GOOD_S 6 - -// Field: [5] SCLK_LF_GOOD -// -// SCLK_LF_GOOD -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD 0x00000020 -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_M 0x00000020 -#define DDI_0_OSC_STAT1_SCLK_LF_GOOD_S 5 - -// Field: [4] ACLK_ADC_GOOD -// -// ACLK_ADC_GOOD -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD 0x00000010 -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_M 0x00000010 -#define DDI_0_OSC_STAT1_ACLK_ADC_GOOD_S 4 - -// Field: [3] ACLK_TDC_GOOD -// -// ACLK_TDC_GOOD -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD 0x00000008 -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_M 0x00000008 -#define DDI_0_OSC_STAT1_ACLK_TDC_GOOD_S 3 - -// Field: [2] ACLK_REF_GOOD -// -// ACLK_REF_GOOD. -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD 0x00000004 -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_M 0x00000004 -#define DDI_0_OSC_STAT1_ACLK_REF_GOOD_S 2 - -// Field: [1] CLK_CHP_GOOD -// -// CLK_CHP_GOOD -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD 0x00000002 -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_M 0x00000002 -#define DDI_0_OSC_STAT1_CLK_CHP_GOOD_S 1 - -// Field: [0] CLK_DCDC_GOOD -// -// CLK_DCDC_GOOD -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD 0x00000001 -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_M 0x00000001 -#define DDI_0_OSC_STAT1_CLK_DCDC_GOOD_S 0 - -//***************************************************************************** -// -// Register: DDI_0_OSC_O_STAT2 -// -//***************************************************************************** -// Field: [31:26] ADC_DCBIAS -// -// DC Bias read by RADC during SAR mode -// The value is an unsigned integer. It is used for debug only. -#define DDI_0_OSC_STAT2_ADC_DCBIAS_W 6 -#define DDI_0_OSC_STAT2_ADC_DCBIAS_M 0xFC000000 -#define DDI_0_OSC_STAT2_ADC_DCBIAS_S 26 - -// Field: [25] HPM_RAMP1_THMET -// -// Indication of threshold is met for hpm_ramp1 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET 0x02000000 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_M 0x02000000 -#define DDI_0_OSC_STAT2_HPM_RAMP1_THMET_S 25 - -// Field: [24] HPM_RAMP2_THMET -// -// Indication of threshold is met for hpm_ramp2 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET 0x01000000 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_M 0x01000000 -#define DDI_0_OSC_STAT2_HPM_RAMP2_THMET_S 24 - -// Field: [23] HPM_RAMP3_THMET -// -// Indication of threshold is met for hpm_ramp3 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET 0x00800000 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_M 0x00800000 -#define DDI_0_OSC_STAT2_HPM_RAMP3_THMET_S 23 - -// Field: [15:12] RAMPSTATE -// -// xosc_hf amplitude compensation FSM -// -// This is identical to STAT1.RAMPSTATE. See that description for encoding. -#define DDI_0_OSC_STAT2_RAMPSTATE_W 4 -#define DDI_0_OSC_STAT2_RAMPSTATE_M 0x0000F000 -#define DDI_0_OSC_STAT2_RAMPSTATE_S 12 - -// Field: [3] AMPCOMP_REQ -// -// ampcomp_req -#define DDI_0_OSC_STAT2_AMPCOMP_REQ 0x00000008 -#define DDI_0_OSC_STAT2_AMPCOMP_REQ_M 0x00000008 -#define DDI_0_OSC_STAT2_AMPCOMP_REQ_S 3 - -// Field: [2] XOSC_HF_AMPGOOD -// -// amplitude of xosc_hf is within the required threshold (set by DDI). Not used -// for anything just for debug/status -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD 0x00000004 -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_M 0x00000004 -#define DDI_0_OSC_STAT2_XOSC_HF_AMPGOOD_S 2 - -// Field: [1] XOSC_HF_FREQGOOD -// -// frequency of xosc_hf is good to use for the digital clocks -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD 0x00000002 -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_M 0x00000002 -#define DDI_0_OSC_STAT2_XOSC_HF_FREQGOOD_S 1 - -// Field: [0] XOSC_HF_RF_FREQGOOD -// -// frequency of xosc_hf is within +/- 20 ppm and xosc_hf is good for radio -// operations. Used for SW to start synthesizer. -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD 0x00000001 -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_M 0x00000001 -#define DDI_0_OSC_STAT2_XOSC_HF_RF_FREQGOOD_S 0 - - -#endif // __DDI_0_OSC__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h deleted file mode 100644 index 754774f014b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_event.h +++ /dev/null @@ -1,3688 +0,0 @@ -/****************************************************************************** -* Filename: hw_event_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_EVENT_H__ -#define __HW_EVENT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// EVENT component -// -//***************************************************************************** -// Output Selection for CPU Interrupt 0 -#define EVENT_O_CPUIRQSEL0 0x00000000 - -// Output Selection for CPU Interrupt 1 -#define EVENT_O_CPUIRQSEL1 0x00000004 - -// Output Selection for CPU Interrupt 2 -#define EVENT_O_CPUIRQSEL2 0x00000008 - -// Output Selection for CPU Interrupt 3 -#define EVENT_O_CPUIRQSEL3 0x0000000C - -// Output Selection for CPU Interrupt 4 -#define EVENT_O_CPUIRQSEL4 0x00000010 - -// Output Selection for CPU Interrupt 5 -#define EVENT_O_CPUIRQSEL5 0x00000014 - -// Output Selection for CPU Interrupt 6 -#define EVENT_O_CPUIRQSEL6 0x00000018 - -// Output Selection for CPU Interrupt 7 -#define EVENT_O_CPUIRQSEL7 0x0000001C - -// Output Selection for CPU Interrupt 8 -#define EVENT_O_CPUIRQSEL8 0x00000020 - -// Output Selection for CPU Interrupt 9 -#define EVENT_O_CPUIRQSEL9 0x00000024 - -// Output Selection for CPU Interrupt 10 -#define EVENT_O_CPUIRQSEL10 0x00000028 - -// Output Selection for CPU Interrupt 11 -#define EVENT_O_CPUIRQSEL11 0x0000002C - -// Output Selection for CPU Interrupt 12 -#define EVENT_O_CPUIRQSEL12 0x00000030 - -// Output Selection for CPU Interrupt 13 -#define EVENT_O_CPUIRQSEL13 0x00000034 - -// Output Selection for CPU Interrupt 14 -#define EVENT_O_CPUIRQSEL14 0x00000038 - -// Output Selection for CPU Interrupt 15 -#define EVENT_O_CPUIRQSEL15 0x0000003C - -// Output Selection for CPU Interrupt 16 -#define EVENT_O_CPUIRQSEL16 0x00000040 - -// Output Selection for CPU Interrupt 17 -#define EVENT_O_CPUIRQSEL17 0x00000044 - -// Output Selection for CPU Interrupt 18 -#define EVENT_O_CPUIRQSEL18 0x00000048 - -// Output Selection for CPU Interrupt 19 -#define EVENT_O_CPUIRQSEL19 0x0000004C - -// Output Selection for CPU Interrupt 20 -#define EVENT_O_CPUIRQSEL20 0x00000050 - -// Output Selection for CPU Interrupt 21 -#define EVENT_O_CPUIRQSEL21 0x00000054 - -// Output Selection for CPU Interrupt 22 -#define EVENT_O_CPUIRQSEL22 0x00000058 - -// Output Selection for CPU Interrupt 23 -#define EVENT_O_CPUIRQSEL23 0x0000005C - -// Output Selection for CPU Interrupt 24 -#define EVENT_O_CPUIRQSEL24 0x00000060 - -// Output Selection for CPU Interrupt 25 -#define EVENT_O_CPUIRQSEL25 0x00000064 - -// Output Selection for CPU Interrupt 26 -#define EVENT_O_CPUIRQSEL26 0x00000068 - -// Output Selection for CPU Interrupt 27 -#define EVENT_O_CPUIRQSEL27 0x0000006C - -// Output Selection for CPU Interrupt 28 -#define EVENT_O_CPUIRQSEL28 0x00000070 - -// Output Selection for CPU Interrupt 29 -#define EVENT_O_CPUIRQSEL29 0x00000074 - -// Output Selection for CPU Interrupt 30 -#define EVENT_O_CPUIRQSEL30 0x00000078 - -// Output Selection for CPU Interrupt 31 -#define EVENT_O_CPUIRQSEL31 0x0000007C - -// Output Selection for CPU Interrupt 32 -#define EVENT_O_CPUIRQSEL32 0x00000080 - -// Output Selection for CPU Interrupt 33 -#define EVENT_O_CPUIRQSEL33 0x00000084 - -// Output Selection for CPU Interrupt 34 -#define EVENT_O_CPUIRQSEL34 0x00000088 - -// Output Selection for CPU Interrupt 35 -#define EVENT_O_CPUIRQSEL35 0x0000008C - -// Output Selection for CPU Interrupt 36 -#define EVENT_O_CPUIRQSEL36 0x00000090 - -// Output Selection for CPU Interrupt 37 -#define EVENT_O_CPUIRQSEL37 0x00000094 - -// Output Selection for RFC Event 0 -#define EVENT_O_RFCSEL0 0x00000100 - -// Output Selection for RFC Event 1 -#define EVENT_O_RFCSEL1 0x00000104 - -// Output Selection for RFC Event 2 -#define EVENT_O_RFCSEL2 0x00000108 - -// Output Selection for RFC Event 3 -#define EVENT_O_RFCSEL3 0x0000010C - -// Output Selection for RFC Event 4 -#define EVENT_O_RFCSEL4 0x00000110 - -// Output Selection for RFC Event 5 -#define EVENT_O_RFCSEL5 0x00000114 - -// Output Selection for RFC Event 6 -#define EVENT_O_RFCSEL6 0x00000118 - -// Output Selection for RFC Event 7 -#define EVENT_O_RFCSEL7 0x0000011C - -// Output Selection for RFC Event 8 -#define EVENT_O_RFCSEL8 0x00000120 - -// Output Selection for RFC Event 9 -#define EVENT_O_RFCSEL9 0x00000124 - -// Output Selection for GPT0 0 -#define EVENT_O_GPT0ACAPTSEL 0x00000200 - -// Output Selection for GPT0 1 -#define EVENT_O_GPT0BCAPTSEL 0x00000204 - -// Output Selection for GPT1 0 -#define EVENT_O_GPT1ACAPTSEL 0x00000300 - -// Output Selection for GPT1 1 -#define EVENT_O_GPT1BCAPTSEL 0x00000304 - -// Output Selection for GPT2 0 -#define EVENT_O_GPT2ACAPTSEL 0x00000400 - -// Output Selection for GPT2 1 -#define EVENT_O_GPT2BCAPTSEL 0x00000404 - -// Output Selection for DMA Channel 1 SREQ -#define EVENT_O_UDMACH1SSEL 0x00000508 - -// Output Selection for DMA Channel 1 REQ -#define EVENT_O_UDMACH1BSEL 0x0000050C - -// Output Selection for DMA Channel 2 SREQ -#define EVENT_O_UDMACH2SSEL 0x00000510 - -// Output Selection for DMA Channel 2 REQ -#define EVENT_O_UDMACH2BSEL 0x00000514 - -// Output Selection for DMA Channel 3 SREQ -#define EVENT_O_UDMACH3SSEL 0x00000518 - -// Output Selection for DMA Channel 3 REQ -#define EVENT_O_UDMACH3BSEL 0x0000051C - -// Output Selection for DMA Channel 4 SREQ -#define EVENT_O_UDMACH4SSEL 0x00000520 - -// Output Selection for DMA Channel 4 REQ -#define EVENT_O_UDMACH4BSEL 0x00000524 - -// Output Selection for DMA Channel 5 SREQ -#define EVENT_O_UDMACH5SSEL 0x00000528 - -// Output Selection for DMA Channel 5 REQ -#define EVENT_O_UDMACH5BSEL 0x0000052C - -// Output Selection for DMA Channel 6 SREQ -#define EVENT_O_UDMACH6SSEL 0x00000530 - -// Output Selection for DMA Channel 6 REQ -#define EVENT_O_UDMACH6BSEL 0x00000534 - -// Output Selection for DMA Channel 7 SREQ -#define EVENT_O_UDMACH7SSEL 0x00000538 - -// Output Selection for DMA Channel 7 REQ -#define EVENT_O_UDMACH7BSEL 0x0000053C - -// Output Selection for DMA Channel 8 SREQ -#define EVENT_O_UDMACH8SSEL 0x00000540 - -// Output Selection for DMA Channel 8 REQ -#define EVENT_O_UDMACH8BSEL 0x00000544 - -// Output Selection for DMA Channel 9 SREQ -#define EVENT_O_UDMACH9SSEL 0x00000548 - -// Output Selection for DMA Channel 9 REQ -#define EVENT_O_UDMACH9BSEL 0x0000054C - -// Output Selection for DMA Channel 10 SREQ -#define EVENT_O_UDMACH10SSEL 0x00000550 - -// Output Selection for DMA Channel 10 REQ -#define EVENT_O_UDMACH10BSEL 0x00000554 - -// Output Selection for DMA Channel 11 SREQ -#define EVENT_O_UDMACH11SSEL 0x00000558 - -// Output Selection for DMA Channel 11 REQ -#define EVENT_O_UDMACH11BSEL 0x0000055C - -// Output Selection for DMA Channel 12 SREQ -#define EVENT_O_UDMACH12SSEL 0x00000560 - -// Output Selection for DMA Channel 12 REQ -#define EVENT_O_UDMACH12BSEL 0x00000564 - -// Output Selection for DMA Channel 13 REQ -#define EVENT_O_UDMACH13BSEL 0x0000056C - -// Output Selection for DMA Channel 14 REQ -#define EVENT_O_UDMACH14BSEL 0x00000574 - -// Output Selection for DMA Channel 15 REQ -#define EVENT_O_UDMACH15BSEL 0x0000057C - -// Output Selection for DMA Channel 16 SREQ -#define EVENT_O_UDMACH16SSEL 0x00000580 - -// Output Selection for DMA Channel 16 REQ -#define EVENT_O_UDMACH16BSEL 0x00000584 - -// Output Selection for DMA Channel 17 SREQ -#define EVENT_O_UDMACH17SSEL 0x00000588 - -// Output Selection for DMA Channel 17 REQ -#define EVENT_O_UDMACH17BSEL 0x0000058C - -// Output Selection for DMA Channel 21 SREQ -#define EVENT_O_UDMACH21SSEL 0x000005A8 - -// Output Selection for DMA Channel 21 REQ -#define EVENT_O_UDMACH21BSEL 0x000005AC - -// Output Selection for DMA Channel 22 SREQ -#define EVENT_O_UDMACH22SSEL 0x000005B0 - -// Output Selection for DMA Channel 22 REQ -#define EVENT_O_UDMACH22BSEL 0x000005B4 - -// Output Selection for DMA Channel 23 SREQ -#define EVENT_O_UDMACH23SSEL 0x000005B8 - -// Output Selection for DMA Channel 23 REQ -#define EVENT_O_UDMACH23BSEL 0x000005BC - -// Output Selection for DMA Channel 24 SREQ -#define EVENT_O_UDMACH24SSEL 0x000005C0 - -// Output Selection for DMA Channel 24 REQ -#define EVENT_O_UDMACH24BSEL 0x000005C4 - -// Output Selection for GPT3 0 -#define EVENT_O_GPT3ACAPTSEL 0x00000600 - -// Output Selection for GPT3 1 -#define EVENT_O_GPT3BCAPTSEL 0x00000604 - -// Output Selection for AUX Subscriber 0 -#define EVENT_O_AUXSEL0 0x00000700 - -// Output Selection for NMI Subscriber 0 -#define EVENT_O_CM3NMISEL0 0x00000800 - -// Output Selection for I2S Subscriber 0 -#define EVENT_O_I2SSTMPSEL0 0x00000900 - -// Output Selection for FRZ Subscriber -#define EVENT_O_FRZSEL0 0x00000A00 - -// Set or Clear Software Events -#define EVENT_O_SWEV 0x00000F00 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL0 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -#define EVENT_CPUIRQSEL0_EV_W 7 -#define EVENT_CPUIRQSEL0_EV_M 0x0000007F -#define EVENT_CPUIRQSEL0_EV_S 0 -#define EVENT_CPUIRQSEL0_EV_AON_GPIO_EDGE 0x00000004 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL1 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// I2C_IRQ Interrupt event from I2C -#define EVENT_CPUIRQSEL1_EV_W 7 -#define EVENT_CPUIRQSEL1_EV_M 0x0000007F -#define EVENT_CPUIRQSEL1_EV_S 0 -#define EVENT_CPUIRQSEL1_EV_I2C_IRQ 0x00000009 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL2 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -#define EVENT_CPUIRQSEL2_EV_W 7 -#define EVENT_CPUIRQSEL2_EV_M 0x0000007F -#define EVENT_CPUIRQSEL2_EV_S 0 -#define EVENT_CPUIRQSEL2_EV_RFC_CPE_1 0x0000001E - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL3 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// PKA_IRQ PKA Interrupt event -#define EVENT_CPUIRQSEL3_EV_W 7 -#define EVENT_CPUIRQSEL3_EV_M 0x0000007F -#define EVENT_CPUIRQSEL3_EV_S 0 -#define EVENT_CPUIRQSEL3_EV_PKA_IRQ 0x0000001F - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL4 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -#define EVENT_CPUIRQSEL4_EV_W 7 -#define EVENT_CPUIRQSEL4_EV_M 0x0000007F -#define EVENT_CPUIRQSEL4_EV_S 0 -#define EVENT_CPUIRQSEL4_EV_AON_RTC_COMB 0x00000007 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL5 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -#define EVENT_CPUIRQSEL5_EV_W 7 -#define EVENT_CPUIRQSEL5_EV_M 0x0000007F -#define EVENT_CPUIRQSEL5_EV_S 0 -#define EVENT_CPUIRQSEL5_EV_UART0_COMB 0x00000024 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL6 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_SWEV0 AUX software event 0, triggered by -// AUX_EVCTL:SWEVSET.SWEV0, also available as -// AUX_EVENT0 AON wake up event. -// MCU domain wakeup control -// AON_EVENT:MCUWUSEL -#define EVENT_CPUIRQSEL6_EV_W 7 -#define EVENT_CPUIRQSEL6_EV_M 0x0000007F -#define EVENT_CPUIRQSEL6_EV_S 0 -#define EVENT_CPUIRQSEL6_EV_AUX_SWEV0 0x0000001C - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL7 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -#define EVENT_CPUIRQSEL7_EV_W 7 -#define EVENT_CPUIRQSEL7_EV_M 0x0000007F -#define EVENT_CPUIRQSEL7_EV_S 0 -#define EVENT_CPUIRQSEL7_EV_SSI0_COMB 0x00000022 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL8 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -#define EVENT_CPUIRQSEL8_EV_W 7 -#define EVENT_CPUIRQSEL8_EV_M 0x0000007F -#define EVENT_CPUIRQSEL8_EV_S 0 -#define EVENT_CPUIRQSEL8_EV_SSI1_COMB 0x00000023 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL9 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -#define EVENT_CPUIRQSEL9_EV_W 7 -#define EVENT_CPUIRQSEL9_EV_M 0x0000007F -#define EVENT_CPUIRQSEL9_EV_S 0 -#define EVENT_CPUIRQSEL9_EV_RFC_CPE_0 0x0000001B - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL10 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -#define EVENT_CPUIRQSEL10_EV_W 7 -#define EVENT_CPUIRQSEL10_EV_M 0x0000007F -#define EVENT_CPUIRQSEL10_EV_S 0 -#define EVENT_CPUIRQSEL10_EV_RFC_HW_COMB 0x0000001A - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL11 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -#define EVENT_CPUIRQSEL11_EV_W 7 -#define EVENT_CPUIRQSEL11_EV_M 0x0000007F -#define EVENT_CPUIRQSEL11_EV_S 0 -#define EVENT_CPUIRQSEL11_EV_RFC_CMD_ACK 0x00000019 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL12 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// I2S_IRQ Interrupt event from I2S -#define EVENT_CPUIRQSEL12_EV_W 7 -#define EVENT_CPUIRQSEL12_EV_M 0x0000007F -#define EVENT_CPUIRQSEL12_EV_S 0 -#define EVENT_CPUIRQSEL12_EV_I2S_IRQ 0x00000008 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL13 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_SWEV1 AUX software event 1, triggered by -// AUX_EVCTL:SWEVSET.SWEV1, also available as -// AUX_EVENT2 AON wake up event. -// MCU domain wakeup control -// AON_EVENT:MCUWUSEL -#define EVENT_CPUIRQSEL13_EV_W 7 -#define EVENT_CPUIRQSEL13_EV_M 0x0000007F -#define EVENT_CPUIRQSEL13_EV_S 0 -#define EVENT_CPUIRQSEL13_EV_AUX_SWEV1 0x0000001D - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL14 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// WDT_IRQ Watchdog interrupt event, controlled by -// WDT:CTL.INTEN -#define EVENT_CPUIRQSEL14_EV_W 7 -#define EVENT_CPUIRQSEL14_EV_M 0x0000007F -#define EVENT_CPUIRQSEL14_EV_S 0 -#define EVENT_CPUIRQSEL14_EV_WDT_IRQ 0x00000018 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL15 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR -#define EVENT_CPUIRQSEL15_EV_W 7 -#define EVENT_CPUIRQSEL15_EV_M 0x0000007F -#define EVENT_CPUIRQSEL15_EV_S 0 -#define EVENT_CPUIRQSEL15_EV_GPT0A 0x00000010 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL16 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR -#define EVENT_CPUIRQSEL16_EV_W 7 -#define EVENT_CPUIRQSEL16_EV_M 0x0000007F -#define EVENT_CPUIRQSEL16_EV_S 0 -#define EVENT_CPUIRQSEL16_EV_GPT0B 0x00000011 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL17 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR -#define EVENT_CPUIRQSEL17_EV_W 7 -#define EVENT_CPUIRQSEL17_EV_M 0x0000007F -#define EVENT_CPUIRQSEL17_EV_S 0 -#define EVENT_CPUIRQSEL17_EV_GPT1A 0x00000012 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL18 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR -#define EVENT_CPUIRQSEL18_EV_W 7 -#define EVENT_CPUIRQSEL18_EV_M 0x0000007F -#define EVENT_CPUIRQSEL18_EV_S 0 -#define EVENT_CPUIRQSEL18_EV_GPT1B 0x00000013 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL19 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR -#define EVENT_CPUIRQSEL19_EV_W 7 -#define EVENT_CPUIRQSEL19_EV_M 0x0000007F -#define EVENT_CPUIRQSEL19_EV_S 0 -#define EVENT_CPUIRQSEL19_EV_GPT2A 0x0000000C - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL20 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR -#define EVENT_CPUIRQSEL20_EV_W 7 -#define EVENT_CPUIRQSEL20_EV_M 0x0000007F -#define EVENT_CPUIRQSEL20_EV_S 0 -#define EVENT_CPUIRQSEL20_EV_GPT2B 0x0000000D - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL21 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR -#define EVENT_CPUIRQSEL21_EV_W 7 -#define EVENT_CPUIRQSEL21_EV_M 0x0000007F -#define EVENT_CPUIRQSEL21_EV_S 0 -#define EVENT_CPUIRQSEL21_EV_GPT3A 0x0000000E - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL22 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR -#define EVENT_CPUIRQSEL22_EV_W 7 -#define EVENT_CPUIRQSEL22_EV_M 0x0000007F -#define EVENT_CPUIRQSEL22_EV_S 0 -#define EVENT_CPUIRQSEL22_EV_GPT3B 0x0000000F - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL23 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the -// corresponding flag is found here -// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by -// CRYPTO:IRQSTAT.RESULT_AVAIL -#define EVENT_CPUIRQSEL23_EV_W 7 -#define EVENT_CPUIRQSEL23_EV_M 0x0000007F -#define EVENT_CPUIRQSEL23_EV_S 0 -#define EVENT_CPUIRQSEL23_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL24 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// DMA_DONE_COMB Combined DMA done, corresponding flags are here -// UDMA0:REQDONE -#define EVENT_CPUIRQSEL24_EV_W 7 -#define EVENT_CPUIRQSEL24_EV_M 0x0000007F -#define EVENT_CPUIRQSEL24_EV_S 0 -#define EVENT_CPUIRQSEL24_EV_DMA_DONE_COMB 0x00000027 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL25 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS -#define EVENT_CPUIRQSEL25_EV_W 7 -#define EVENT_CPUIRQSEL25_EV_M 0x0000007F -#define EVENT_CPUIRQSEL25_EV_S 0 -#define EVENT_CPUIRQSEL25_EV_DMA_ERR 0x00000026 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL26 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -#define EVENT_CPUIRQSEL26_EV_W 7 -#define EVENT_CPUIRQSEL26_EV_M 0x0000007F -#define EVENT_CPUIRQSEL26_EV_S 0 -#define EVENT_CPUIRQSEL26_EV_FLASH 0x00000015 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL27 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_CPUIRQSEL27_EV_W 7 -#define EVENT_CPUIRQSEL27_EV_M 0x0000007F -#define EVENT_CPUIRQSEL27_EV_S 0 -#define EVENT_CPUIRQSEL27_EV_SWEV0 0x00000064 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL28 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -#define EVENT_CPUIRQSEL28_EV_W 7 -#define EVENT_CPUIRQSEL28_EV_M 0x0000007F -#define EVENT_CPUIRQSEL28_EV_S 0 -#define EVENT_CPUIRQSEL28_EV_AUX_COMB 0x0000000B - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL29 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AON_PROG0 AON programmable event 0. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV -#define EVENT_CPUIRQSEL29_EV_W 7 -#define EVENT_CPUIRQSEL29_EV_M 0x0000007F -#define EVENT_CPUIRQSEL29_EV_S 0 -#define EVENT_CPUIRQSEL29_EV_AON_PROG0 0x00000001 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL30 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and -// the AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here -// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV -// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg -// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled -// by CRYPTO:IRQEN.DMA_IN_DONE -// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, -// see UDMA0:SOFTREQ -// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see -// UDMA0:SOFTREQ -// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 -// I2S_IRQ Interrupt event from I2S -// AON_PROG2 AON programmable event 2. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV -// AON_PROG1 AON programmable event 1. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV -// NONE Always inactive -#define EVENT_CPUIRQSEL30_EV_W 7 -#define EVENT_CPUIRQSEL30_EV_M 0x0000007F -#define EVENT_CPUIRQSEL30_EV_S 0 -#define EVENT_CPUIRQSEL30_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_CPUIRQSEL30_EV_AON_RTC_UPD 0x00000077 -#define EVENT_CPUIRQSEL30_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_CPUIRQSEL30_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_CPUIRQSEL30_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_CPUIRQSEL30_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_CPUIRQSEL30_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_CPUIRQSEL30_EV_AUX_COMPB 0x0000006B -#define EVENT_CPUIRQSEL30_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_CPUIRQSEL30_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_CPUIRQSEL30_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_CPUIRQSEL30_EV_DMA_CH18_DONE 0x00000016 -#define EVENT_CPUIRQSEL30_EV_DMA_CH0_DONE 0x00000014 -#define EVENT_CPUIRQSEL30_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_CPUIRQSEL30_EV_I2S_IRQ 0x00000008 -#define EVENT_CPUIRQSEL30_EV_AON_PROG2 0x00000003 -#define EVENT_CPUIRQSEL30_EV_AON_PROG1 0x00000002 -#define EVENT_CPUIRQSEL30_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL31 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -#define EVENT_CPUIRQSEL31_EV_W 7 -#define EVENT_CPUIRQSEL31_EV_M 0x0000007F -#define EVENT_CPUIRQSEL31_EV_S 0 -#define EVENT_CPUIRQSEL31_EV_AUX_COMPA 0x0000006A - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL32 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status -// flags are found here AUX_EVCTL:EVTOMCUFLAGS -#define EVENT_CPUIRQSEL32_EV_W 7 -#define EVENT_CPUIRQSEL32_EV_M 0x0000007F -#define EVENT_CPUIRQSEL32_EV_S 0 -#define EVENT_CPUIRQSEL32_EV_AUX_ADC_IRQ 0x00000073 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL33 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN -#define EVENT_CPUIRQSEL33_EV_W 7 -#define EVENT_CPUIRQSEL33_EV_M 0x0000007F -#define EVENT_CPUIRQSEL33_EV_S 0 -#define EVENT_CPUIRQSEL33_EV_TRNG_IRQ 0x00000068 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL34 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// OSC_COMB Combined event from Oscillator control -#define EVENT_CPUIRQSEL34_EV_W 7 -#define EVENT_CPUIRQSEL34_EV_M 0x0000007F -#define EVENT_CPUIRQSEL34_EV_S 0 -#define EVENT_CPUIRQSEL34_EV_OSC_COMB 0x00000006 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL35 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -#define EVENT_CPUIRQSEL35_EV_W 7 -#define EVENT_CPUIRQSEL35_EV_M 0x0000007F -#define EVENT_CPUIRQSEL35_EV_S 0 -#define EVENT_CPUIRQSEL35_EV_AUX_TIMER2_EV0 0x00000038 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL36 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART1_COMB UART1 combined interrupt, interrupt flags are -// found here UART1:MIS -#define EVENT_CPUIRQSEL36_EV_W 7 -#define EVENT_CPUIRQSEL36_EV_M 0x0000007F -#define EVENT_CPUIRQSEL36_EV_S 0 -#define EVENT_CPUIRQSEL36_EV_UART1_COMB 0x00000025 - -//***************************************************************************** -// -// Register: EVENT_O_CPUIRQSEL37 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// BATMON_COMB Combined event from battery monitor -#define EVENT_CPUIRQSEL37_EV_W 7 -#define EVENT_CPUIRQSEL37_EV_M 0x0000007F -#define EVENT_CPUIRQSEL37_EV_S 0 -#define EVENT_CPUIRQSEL37_EV_BATMON_COMB 0x00000005 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL0 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -#define EVENT_RFCSEL0_EV_W 7 -#define EVENT_RFCSEL0_EV_M 0x0000007F -#define EVENT_RFCSEL0_EV_S 0 -#define EVENT_RFCSEL0_EV_GPT0A_CMP 0x0000003D - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL1 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -#define EVENT_RFCSEL1_EV_W 7 -#define EVENT_RFCSEL1_EV_M 0x0000007F -#define EVENT_RFCSEL1_EV_S 0 -#define EVENT_RFCSEL1_EV_GPT0B_CMP 0x0000003E - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL2 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -#define EVENT_RFCSEL2_EV_W 7 -#define EVENT_RFCSEL2_EV_M 0x0000007F -#define EVENT_RFCSEL2_EV_S 0 -#define EVENT_RFCSEL2_EV_GPT1A_CMP 0x0000003F - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL3 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -#define EVENT_RFCSEL3_EV_W 7 -#define EVENT_RFCSEL3_EV_M 0x0000007F -#define EVENT_RFCSEL3_EV_S 0 -#define EVENT_RFCSEL3_EV_GPT1B_CMP 0x00000040 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL4 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -#define EVENT_RFCSEL4_EV_W 7 -#define EVENT_RFCSEL4_EV_M 0x0000007F -#define EVENT_RFCSEL4_EV_S 0 -#define EVENT_RFCSEL4_EV_GPT2A_CMP 0x00000041 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL5 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -#define EVENT_RFCSEL5_EV_W 7 -#define EVENT_RFCSEL5_EV_M 0x0000007F -#define EVENT_RFCSEL5_EV_S 0 -#define EVENT_RFCSEL5_EV_GPT2B_CMP 0x00000042 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL6 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -#define EVENT_RFCSEL6_EV_W 7 -#define EVENT_RFCSEL6_EV_M 0x0000007F -#define EVENT_RFCSEL6_EV_S 0 -#define EVENT_RFCSEL6_EV_GPT3A_CMP 0x00000043 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL7 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -#define EVENT_RFCSEL7_EV_W 7 -#define EVENT_RFCSEL7_EV_M 0x0000007F -#define EVENT_RFCSEL7_EV_S 0 -#define EVENT_RFCSEL7_EV_GPT3B_CMP 0x00000044 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL8 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -#define EVENT_RFCSEL8_EV_W 7 -#define EVENT_RFCSEL8_EV_M 0x0000007F -#define EVENT_RFCSEL8_EV_S 0 -#define EVENT_RFCSEL8_EV_AON_RTC_UPD 0x00000077 - -//***************************************************************************** -// -// Register: EVENT_O_RFCSEL9 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status -// flags are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and -// the AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here -// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV -// SWEV1 Software event 1, triggered by SWEV.SWEV1 -// SWEV0 Software event 0, triggered by SWEV.SWEV0 -// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the -// corresponding flag is found here -// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by -// CRYPTO:IRQSTAT.RESULT_AVAIL -// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -// DMA_DONE_COMB Combined DMA done, corresponding flags are here -// UDMA0:REQDONE -// UART1_COMB UART1 combined interrupt, interrupt flags are -// found here UART1:MIS -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// WDT_IRQ Watchdog interrupt event, controlled by -// WDT:CTL.INTEN -// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 -// I2S_IRQ Interrupt event from I2S -// AON_PROG1 AON programmable event 1. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV -// AON_PROG0 AON programmable event 0. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV -// NONE Always inactive -#define EVENT_RFCSEL9_EV_W 7 -#define EVENT_RFCSEL9_EV_M 0x0000007F -#define EVENT_RFCSEL9_EV_S 0 -#define EVENT_RFCSEL9_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_RFCSEL9_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_RFCSEL9_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_RFCSEL9_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_RFCSEL9_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_RFCSEL9_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_RFCSEL9_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_RFCSEL9_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_RFCSEL9_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_RFCSEL9_EV_AUX_COMPB 0x0000006B -#define EVENT_RFCSEL9_EV_AUX_COMPA 0x0000006A -#define EVENT_RFCSEL9_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_RFCSEL9_EV_SWEV1 0x00000065 -#define EVENT_RFCSEL9_EV_SWEV0 0x00000064 -#define EVENT_RFCSEL9_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D -#define EVENT_RFCSEL9_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_RFCSEL9_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_RFCSEL9_EV_DMA_DONE_COMB 0x00000027 -#define EVENT_RFCSEL9_EV_UART1_COMB 0x00000025 -#define EVENT_RFCSEL9_EV_UART0_COMB 0x00000024 -#define EVENT_RFCSEL9_EV_SSI1_COMB 0x00000023 -#define EVENT_RFCSEL9_EV_SSI0_COMB 0x00000022 -#define EVENT_RFCSEL9_EV_WDT_IRQ 0x00000018 -#define EVENT_RFCSEL9_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_RFCSEL9_EV_I2S_IRQ 0x00000008 -#define EVENT_RFCSEL9_EV_AON_PROG1 0x00000002 -#define EVENT_RFCSEL9_EV_AON_PROG0 0x00000001 -#define EVENT_RFCSEL9_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT0ACAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status -// flags are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and -// the AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here -// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV -// PORT_EVENT1 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT1 wil be routed here. -// PORT_EVENT0 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT0 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -// UART1_COMB UART1 combined interrupt, interrupt flags are -// found here UART1:MIS -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// OSC_COMB Combined event from Oscillator control -// BATMON_COMB Combined event from battery monitor -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT0ACAPTSEL_EV_W 7 -#define EVENT_GPT0ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT0ACAPTSEL_EV_S 0 -#define EVENT_GPT0ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT0ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT0ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT0ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT0ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT0ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_GPT0ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT0ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT0ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT0ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT0ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT0ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT0ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT0ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT0ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT0ACAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT0ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT0ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT0ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT0ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT0ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT0ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT0ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT0ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT0ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT0ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT0ACAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT0ACAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT0ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT0ACAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT0BCAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status -// flags are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and -// the AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here -// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV -// PORT_EVENT1 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT1 wil be routed here. -// PORT_EVENT0 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT0 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -// UART1_COMB UART1 combined interrupt, interrupt flags are -// found here UART1:MIS -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// OSC_COMB Combined event from Oscillator control -// BATMON_COMB Combined event from battery monitor -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT0BCAPTSEL_EV_W 7 -#define EVENT_GPT0BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT0BCAPTSEL_EV_S 0 -#define EVENT_GPT0BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT0BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT0BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT0BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT0BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT0BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_GPT0BCAPTSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_GPT0BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT0BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT0BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT0BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT0BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT0BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT0BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT0BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT0BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT0BCAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT0BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT0BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT0BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT0BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT0BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT0BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT0BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT0BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT0BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT0BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT0BCAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT0BCAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT0BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT0BCAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT1ACAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status -// flags are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and -// the AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here -// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV -// PORT_EVENT3 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT3 wil be routed here. -// PORT_EVENT2 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT2 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -// UART1_COMB UART1 combined interrupt, interrupt flags are -// found here UART1:MIS -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// OSC_COMB Combined event from Oscillator control -// BATMON_COMB Combined event from battery monitor -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT1ACAPTSEL_EV_W 7 -#define EVENT_GPT1ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT1ACAPTSEL_EV_S 0 -#define EVENT_GPT1ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT1ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT1ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT1ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT1ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT1ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_GPT1ACAPTSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_GPT1ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT1ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT1ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT1ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT1ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT1ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT1ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT1ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT1ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT1ACAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT1ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT1ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT1ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT1ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT1ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT1ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT1ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT1ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT1ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT1ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT1ACAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT1ACAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT1ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT1ACAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT1BCAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status -// flags are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and -// the AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here -// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV -// PORT_EVENT3 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT3 wil be routed here. -// PORT_EVENT2 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT2 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -// UART1_COMB UART1 combined interrupt, interrupt flags are -// found here UART1:MIS -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// OSC_COMB Combined event from Oscillator control -// BATMON_COMB Combined event from battery monitor -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT1BCAPTSEL_EV_W 7 -#define EVENT_GPT1BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT1BCAPTSEL_EV_S 0 -#define EVENT_GPT1BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT1BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT1BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT1BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT1BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT1BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_GPT1BCAPTSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_GPT1BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT1BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT1BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT1BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT1BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT1BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT1BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT1BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT1BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT1BCAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT1BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT1BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT1BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT1BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT1BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT1BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT1BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT1BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT1BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT1BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT1BCAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT1BCAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT1BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT1BCAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT2ACAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status -// flags are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and -// the AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here -// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV -// PORT_EVENT5 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT4 wil be routed here. -// PORT_EVENT4 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT4 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -// UART1_COMB UART1 combined interrupt, interrupt flags are -// found here UART1:MIS -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// OSC_COMB Combined event from Oscillator control -// BATMON_COMB Combined event from battery monitor -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT2ACAPTSEL_EV_W 7 -#define EVENT_GPT2ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT2ACAPTSEL_EV_S 0 -#define EVENT_GPT2ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT2ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT2ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT2ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT2ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT2ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_GPT2ACAPTSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_GPT2ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT2ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT2ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT2ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT2ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT2ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT2ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT2ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT2ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT2ACAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT2ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT2ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT2ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT2ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT2ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT2ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT2ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT2ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT2ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT2ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT2ACAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT2ACAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT2ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT2ACAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT2BCAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status -// flags are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and -// the AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here -// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV -// PORT_EVENT5 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT4 wil be routed here. -// PORT_EVENT4 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT4 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -// UART1_COMB UART1 combined interrupt, interrupt flags are -// found here UART1:MIS -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// OSC_COMB Combined event from Oscillator control -// BATMON_COMB Combined event from battery monitor -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT2BCAPTSEL_EV_W 7 -#define EVENT_GPT2BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT2BCAPTSEL_EV_S 0 -#define EVENT_GPT2BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT2BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT2BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT2BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT2BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT2BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_GPT2BCAPTSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_GPT2BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT2BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT2BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT2BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT2BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT2BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT2BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT2BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT2BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT2BCAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT2BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT2BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT2BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT2BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT2BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT2BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT2BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT2BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT2BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT2BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT2BCAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT2BCAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT2BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT2BCAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH1SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by -// UART0:DMACTL.RXDMAE -#define EVENT_UDMACH1SSEL_EV_W 7 -#define EVENT_UDMACH1SSEL_EV_M 0x0000007F -#define EVENT_UDMACH1SSEL_EV_S 0 -#define EVENT_UDMACH1SSEL_EV_UART0_RX_DMASREQ 0x00000031 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH1BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by -// UART0:DMACTL.RXDMAE -#define EVENT_UDMACH1BSEL_EV_W 7 -#define EVENT_UDMACH1BSEL_EV_M 0x0000007F -#define EVENT_UDMACH1BSEL_EV_S 0 -#define EVENT_UDMACH1BSEL_EV_UART0_RX_DMABREQ 0x00000030 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH2SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by -// UART0:DMACTL.TXDMAE -#define EVENT_UDMACH2SSEL_EV_W 7 -#define EVENT_UDMACH2SSEL_EV_M 0x0000007F -#define EVENT_UDMACH2SSEL_EV_S 0 -#define EVENT_UDMACH2SSEL_EV_UART0_TX_DMASREQ 0x00000033 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH2BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by -// UART0:DMACTL.TXDMAE -#define EVENT_UDMACH2BSEL_EV_W 7 -#define EVENT_UDMACH2BSEL_EV_M 0x0000007F -#define EVENT_UDMACH2BSEL_EV_S 0 -#define EVENT_UDMACH2BSEL_EV_UART0_TX_DMABREQ 0x00000032 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH3SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by -// SSI0:DMACR.RXDMAE -#define EVENT_UDMACH3SSEL_EV_W 7 -#define EVENT_UDMACH3SSEL_EV_M 0x0000007F -#define EVENT_UDMACH3SSEL_EV_S 0 -#define EVENT_UDMACH3SSEL_EV_SSI0_RX_DMASREQ 0x00000029 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH3BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by -// SSI0:DMACR.RXDMAE -#define EVENT_UDMACH3BSEL_EV_W 7 -#define EVENT_UDMACH3BSEL_EV_M 0x0000007F -#define EVENT_UDMACH3BSEL_EV_S 0 -#define EVENT_UDMACH3BSEL_EV_SSI0_RX_DMABREQ 0x00000028 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH4SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by -// SSI0:DMACR.TXDMAE -#define EVENT_UDMACH4SSEL_EV_W 7 -#define EVENT_UDMACH4SSEL_EV_M 0x0000007F -#define EVENT_UDMACH4SSEL_EV_S 0 -#define EVENT_UDMACH4SSEL_EV_SSI0_TX_DMASREQ 0x0000002B - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH4BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by -// SSI0:DMACR.TXDMAE -#define EVENT_UDMACH4BSEL_EV_W 7 -#define EVENT_UDMACH4BSEL_EV_M 0x0000007F -#define EVENT_UDMACH4BSEL_EV_S 0 -#define EVENT_UDMACH4BSEL_EV_SSI0_TX_DMABREQ 0x0000002A - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH5SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART1_RX_DMASREQ UART1 RX DMA single request, controlled by -// UART1:DMACTL.RXDMAE -#define EVENT_UDMACH5SSEL_EV_W 7 -#define EVENT_UDMACH5SSEL_EV_M 0x0000007F -#define EVENT_UDMACH5SSEL_EV_S 0 -#define EVENT_UDMACH5SSEL_EV_UART1_RX_DMASREQ 0x00000035 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH5BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART1_RX_DMABREQ UART1 RX DMA burst request, controlled by -// UART1:DMACTL.RXDMAE -#define EVENT_UDMACH5BSEL_EV_W 7 -#define EVENT_UDMACH5BSEL_EV_M 0x0000007F -#define EVENT_UDMACH5BSEL_EV_S 0 -#define EVENT_UDMACH5BSEL_EV_UART1_RX_DMABREQ 0x00000034 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH6SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART1_TX_DMASREQ UART1 TX DMA single request, controlled by -// UART1:DMACTL.TXDMAE -#define EVENT_UDMACH6SSEL_EV_W 7 -#define EVENT_UDMACH6SSEL_EV_M 0x0000007F -#define EVENT_UDMACH6SSEL_EV_S 0 -#define EVENT_UDMACH6SSEL_EV_UART1_TX_DMASREQ 0x00000037 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH6BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// UART1_TX_DMABREQ UART1 TX DMA burst request, controlled by -// UART1:DMACTL.TXDMAE -#define EVENT_UDMACH6BSEL_EV_W 7 -#define EVENT_UDMACH6BSEL_EV_M 0x0000007F -#define EVENT_UDMACH6BSEL_EV_S 0 -#define EVENT_UDMACH6BSEL_EV_UART1_TX_DMABREQ 0x00000036 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH7SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_DMASREQ DMA single request event from AUX, configured by -// AUX_EVCTL:DMACTL -#define EVENT_UDMACH7SSEL_EV_W 7 -#define EVENT_UDMACH7SSEL_EV_M 0x0000007F -#define EVENT_UDMACH7SSEL_EV_S 0 -#define EVENT_UDMACH7SSEL_EV_AUX_DMASREQ 0x00000075 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH7BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_DMABREQ DMA burst request event from AUX, configured by -// AUX_EVCTL:DMACTL -#define EVENT_UDMACH7BSEL_EV_W 7 -#define EVENT_UDMACH7BSEL_EV_M 0x0000007F -#define EVENT_UDMACH7BSEL_EV_S 0 -#define EVENT_UDMACH7BSEL_EV_AUX_DMABREQ 0x00000076 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH8SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by -// AUX_EVCTL:DMASWREQ.START -#define EVENT_UDMACH8SSEL_EV_W 7 -#define EVENT_UDMACH8SSEL_EV_M 0x0000007F -#define EVENT_UDMACH8SSEL_EV_S 0 -#define EVENT_UDMACH8SSEL_EV_AUX_SW_DMABREQ 0x00000074 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH8BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by -// AUX_EVCTL:DMASWREQ.START -#define EVENT_UDMACH8BSEL_EV_W 7 -#define EVENT_UDMACH8BSEL_EV_M 0x0000007F -#define EVENT_UDMACH8BSEL_EV_S 0 -#define EVENT_UDMACH8BSEL_EV_AUX_SW_DMABREQ 0x00000074 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH9SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// TIE_LOW Not used tied to 0 -// NONE Always inactive -#define EVENT_UDMACH9SSEL_EV_W 7 -#define EVENT_UDMACH9SSEL_EV_M 0x0000007F -#define EVENT_UDMACH9SSEL_EV_S 0 -#define EVENT_UDMACH9SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH9SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH9SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH9SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH9SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH9SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH9SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH9SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH9SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH9SSEL_EV_TIE_LOW 0x00000045 -#define EVENT_UDMACH9SSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH9BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// NONE Always inactive -#define EVENT_UDMACH9BSEL_EV_W 7 -#define EVENT_UDMACH9BSEL_EV_M 0x0000007F -#define EVENT_UDMACH9BSEL_EV_S 0 -#define EVENT_UDMACH9BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH9BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH9BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH9BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH9BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH9BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH9BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH9BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH9BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH9BSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH10SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// TIE_LOW Not used tied to 0 -// NONE Always inactive -#define EVENT_UDMACH10SSEL_EV_W 7 -#define EVENT_UDMACH10SSEL_EV_M 0x0000007F -#define EVENT_UDMACH10SSEL_EV_S 0 -#define EVENT_UDMACH10SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH10SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH10SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH10SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH10SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH10SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH10SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH10SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH10SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH10SSEL_EV_TIE_LOW 0x00000046 -#define EVENT_UDMACH10SSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH10BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// NONE Always inactive -#define EVENT_UDMACH10BSEL_EV_W 7 -#define EVENT_UDMACH10BSEL_EV_M 0x0000007F -#define EVENT_UDMACH10BSEL_EV_S 0 -#define EVENT_UDMACH10BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH10BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH10BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH10BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH10BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH10BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH10BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH10BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH10BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH10BSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH11SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// TIE_LOW Not used tied to 0 -// NONE Always inactive -#define EVENT_UDMACH11SSEL_EV_W 7 -#define EVENT_UDMACH11SSEL_EV_M 0x0000007F -#define EVENT_UDMACH11SSEL_EV_S 0 -#define EVENT_UDMACH11SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH11SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH11SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH11SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH11SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH11SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH11SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH11SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH11SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH11SSEL_EV_TIE_LOW 0x00000047 -#define EVENT_UDMACH11SSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH11BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// NONE Always inactive -#define EVENT_UDMACH11BSEL_EV_W 7 -#define EVENT_UDMACH11BSEL_EV_M 0x0000007F -#define EVENT_UDMACH11BSEL_EV_S 0 -#define EVENT_UDMACH11BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH11BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH11BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH11BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH11BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH11BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH11BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH11BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH11BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH11BSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH12SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// TIE_LOW Not used tied to 0 -// NONE Always inactive -#define EVENT_UDMACH12SSEL_EV_W 7 -#define EVENT_UDMACH12SSEL_EV_M 0x0000007F -#define EVENT_UDMACH12SSEL_EV_S 0 -#define EVENT_UDMACH12SSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH12SSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH12SSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH12SSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH12SSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH12SSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH12SSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH12SSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH12SSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH12SSEL_EV_TIE_LOW 0x00000048 -#define EVENT_UDMACH12SSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH12BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// NONE Always inactive -#define EVENT_UDMACH12BSEL_EV_W 7 -#define EVENT_UDMACH12BSEL_EV_M 0x0000007F -#define EVENT_UDMACH12BSEL_EV_S 0 -#define EVENT_UDMACH12BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH12BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH12BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH12BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH12BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH12BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH12BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH12BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH12BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH12BSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH13BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AON_PROG2 AON programmable event 2. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV -#define EVENT_UDMACH13BSEL_EV_W 7 -#define EVENT_UDMACH13BSEL_EV_M 0x0000007F -#define EVENT_UDMACH13BSEL_EV_S 0 -#define EVENT_UDMACH13BSEL_EV_AON_PROG2 0x00000003 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH14BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// CPU_HALTED CPU halted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_DMABREQ DMA burst request event from AUX, configured by -// AUX_EVCTL:DMACTL -// AUX_DMASREQ DMA single request event from AUX, configured by -// AUX_EVCTL:DMACTL -// AUX_SW_DMABREQ DMA sofware trigger from AUX, triggered by -// AUX_EVCTL:DMASWREQ.START -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status -// flags are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and -// the AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here -// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV -// TRNG_IRQ TRNG Interrupt event, controlled by TRNG:IRQEN.EN -// SWEV3 Software event 3, triggered by SWEV.SWEV3 -// SWEV2 Software event 2, triggered by SWEV.SWEV2 -// SWEV1 Software event 1, triggered by SWEV.SWEV1 -// SWEV0 Software event 0, triggered by SWEV.SWEV0 -// WDT_NMI Watchdog non maskable interrupt event, controlled -// by WDT:CTL.INTTYPE -// CRYPTO_DMA_DONE_IRQ CRYPTO DMA input done event, the correspondingg -// flag is CRYPTO:IRQSTAT.DMA_IN_DONE. Controlled -// by CRYPTO:IRQEN.DMA_IN_DONE -// CRYPTO_RESULT_AVAIL_IRQ CRYPTO result available interupt event, the -// corresponding flag is found here -// CRYPTO:IRQSTAT.RESULT_AVAIL. Controlled by -// CRYPTO:IRQSTAT.RESULT_AVAIL -// PORT_EVENT7 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT7 wil be routed here. -// PORT_EVENT6 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT6 wil be routed here. -// PORT_EVENT5 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT4 wil be routed here. -// PORT_EVENT4 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT4 wil be routed here. -// PORT_EVENT3 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT3 wil be routed here. -// PORT_EVENT2 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT2 wil be routed here. -// PORT_EVENT1 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT1 wil be routed here. -// PORT_EVENT0 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT0 wil be routed here. -// GPT3B_DMABREQ GPT3B DMA trigger event. Configured by GPT3:DMAEV -// GPT3A_DMABREQ GPT3A DMA trigger event. Configured by GPT3:DMAEV -// GPT2B_DMABREQ GPT2B DMA trigger event. Configured by GPT2:DMAEV -// GPT2A_DMABREQ GPT2A DMA trigger event. Configured by GPT2:DMAEV -// GPT1B_DMABREQ GPT1B DMA trigger event. Configured by GPT1:DMAEV -// GPT1A_DMABREQ GPT1A DMA trigger event. Configured by GPT1:DMAEV -// GPT0B_DMABREQ GPT0B DMA trigger event. Configured by GPT0:DMAEV -// GPT0A_DMABREQ GPT0A DMA trigger event. Configured by GPT0:DMAEV -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -// UART1_TX_DMASREQ UART1 TX DMA single request, controlled by -// UART1:DMACTL.TXDMAE -// UART1_TX_DMABREQ UART1 TX DMA burst request, controlled by -// UART1:DMACTL.TXDMAE -// UART1_RX_DMASREQ UART1 RX DMA single request, controlled by -// UART1:DMACTL.RXDMAE -// UART1_RX_DMABREQ UART1 RX DMA burst request, controlled by -// UART1:DMACTL.RXDMAE -// UART0_TX_DMASREQ UART0 TX DMA single request, controlled by -// UART0:DMACTL.TXDMAE -// UART0_TX_DMABREQ UART0 TX DMA burst request, controlled by -// UART0:DMACTL.TXDMAE -// UART0_RX_DMASREQ UART0 RX DMA single request, controlled by -// UART0:DMACTL.RXDMAE -// UART0_RX_DMABREQ UART0 RX DMA burst request, controlled by -// UART0:DMACTL.RXDMAE -// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by -// SSI0:DMACR.TXDMAE -// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by -// SSI0:DMACR.TXDMAE -// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by -// SSI0:DMACR.RXDMAE -// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by -// SSI0:DMACR.RXDMAE -// SSI0_TX_DMASREQ SSI0 TX DMA single request, controlled by -// SSI0:DMACR.TXDMAE -// SSI0_TX_DMABREQ SSI0 TX DMA burst request , controlled by -// SSI0:DMACR.TXDMAE -// SSI0_RX_DMASREQ SSI0 RX DMA single request, controlled by -// SSI0:DMACR.RXDMAE -// SSI0_RX_DMABREQ SSI0 RX DMA burst request , controlled by -// SSI0:DMACR.RXDMAE -// DMA_DONE_COMB Combined DMA done, corresponding flags are here -// UDMA0:REQDONE -// DMA_ERR DMA bus error, corresponds to UDMA0:ERROR.STATUS -// UART1_COMB UART1 combined interrupt, interrupt flags are -// found here UART1:MIS -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// PKA_IRQ PKA Interrupt event -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// AUX_SWEV1 AUX software event 1, triggered by -// AUX_EVCTL:SWEVSET.SWEV1, also available as -// AUX_EVENT2 AON wake up event. -// MCU domain wakeup control -// AON_EVENT:MCUWUSEL -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// WDT_IRQ Watchdog interrupt event, controlled by -// WDT:CTL.INTEN -// DMA_CH18_DONE DMA done for software tiggered UDMA channel 18, -// see UDMA0:SOFTREQ -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// DMA_CH0_DONE DMA done for software tiggered UDMA channel 0, see -// UDMA0:SOFTREQ -// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR -// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR -// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR -// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR -// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR -// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR -// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR -// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// AON_AUX_SWEV0 AUX Software event 0, AUX_EVCTL:SWEVSET.SWEV0 -// I2C_IRQ Interrupt event from I2C -// I2S_IRQ Interrupt event from I2S -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// OSC_COMB Combined event from Oscillator control -// BATMON_COMB Combined event from battery monitor -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// AON_PROG2 AON programmable event 2. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG2_EV -// AON_PROG1 AON programmable event 1. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG1_EV -// AON_PROG0 AON programmable event 0. Event selected by -// AON_EVENT MCU event selector, -// AON_EVENT:EVTOMCUSEL.AON_PROG0_EV -// NONE Always inactive -#define EVENT_UDMACH14BSEL_EV_W 7 -#define EVENT_UDMACH14BSEL_EV_M 0x0000007F -#define EVENT_UDMACH14BSEL_EV_S 0 -#define EVENT_UDMACH14BSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_UDMACH14BSEL_EV_CPU_HALTED 0x00000078 -#define EVENT_UDMACH14BSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_UDMACH14BSEL_EV_AUX_DMABREQ 0x00000076 -#define EVENT_UDMACH14BSEL_EV_AUX_DMASREQ 0x00000075 -#define EVENT_UDMACH14BSEL_EV_AUX_SW_DMABREQ 0x00000074 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_UDMACH14BSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_UDMACH14BSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_UDMACH14BSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_UDMACH14BSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_UDMACH14BSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_UDMACH14BSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_UDMACH14BSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_UDMACH14BSEL_EV_TRNG_IRQ 0x00000068 -#define EVENT_UDMACH14BSEL_EV_SWEV3 0x00000067 -#define EVENT_UDMACH14BSEL_EV_SWEV2 0x00000066 -#define EVENT_UDMACH14BSEL_EV_SWEV1 0x00000065 -#define EVENT_UDMACH14BSEL_EV_SWEV0 0x00000064 -#define EVENT_UDMACH14BSEL_EV_WDT_NMI 0x00000063 -#define EVENT_UDMACH14BSEL_EV_CRYPTO_DMA_DONE_IRQ 0x0000005E -#define EVENT_UDMACH14BSEL_EV_CRYPTO_RESULT_AVAIL_IRQ 0x0000005D -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT5 0x0000005A -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT4 0x00000059 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT3 0x00000058 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT2 0x00000057 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT1 0x00000056 -#define EVENT_UDMACH14BSEL_EV_PORT_EVENT0 0x00000055 -#define EVENT_UDMACH14BSEL_EV_GPT3B_DMABREQ 0x00000054 -#define EVENT_UDMACH14BSEL_EV_GPT3A_DMABREQ 0x00000053 -#define EVENT_UDMACH14BSEL_EV_GPT2B_DMABREQ 0x00000052 -#define EVENT_UDMACH14BSEL_EV_GPT2A_DMABREQ 0x00000051 -#define EVENT_UDMACH14BSEL_EV_GPT1B_DMABREQ 0x00000050 -#define EVENT_UDMACH14BSEL_EV_GPT1A_DMABREQ 0x0000004F -#define EVENT_UDMACH14BSEL_EV_GPT0B_DMABREQ 0x0000004E -#define EVENT_UDMACH14BSEL_EV_GPT0A_DMABREQ 0x0000004D -#define EVENT_UDMACH14BSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_UDMACH14BSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_UDMACH14BSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_UDMACH14BSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_UDMACH14BSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_UDMACH14BSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_UDMACH14BSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_UDMACH14BSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_UDMACH14BSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_UDMACH14BSEL_EV_UART1_TX_DMASREQ 0x00000037 -#define EVENT_UDMACH14BSEL_EV_UART1_TX_DMABREQ 0x00000036 -#define EVENT_UDMACH14BSEL_EV_UART1_RX_DMASREQ 0x00000035 -#define EVENT_UDMACH14BSEL_EV_UART1_RX_DMABREQ 0x00000034 -#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMASREQ 0x00000033 -#define EVENT_UDMACH14BSEL_EV_UART0_TX_DMABREQ 0x00000032 -#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMASREQ 0x00000031 -#define EVENT_UDMACH14BSEL_EV_UART0_RX_DMABREQ 0x00000030 -#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMASREQ 0x0000002F -#define EVENT_UDMACH14BSEL_EV_SSI1_TX_DMABREQ 0x0000002E -#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMASREQ 0x0000002D -#define EVENT_UDMACH14BSEL_EV_SSI1_RX_DMABREQ 0x0000002C -#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMASREQ 0x0000002B -#define EVENT_UDMACH14BSEL_EV_SSI0_TX_DMABREQ 0x0000002A -#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMASREQ 0x00000029 -#define EVENT_UDMACH14BSEL_EV_SSI0_RX_DMABREQ 0x00000028 -#define EVENT_UDMACH14BSEL_EV_DMA_DONE_COMB 0x00000027 -#define EVENT_UDMACH14BSEL_EV_DMA_ERR 0x00000026 -#define EVENT_UDMACH14BSEL_EV_UART1_COMB 0x00000025 -#define EVENT_UDMACH14BSEL_EV_UART0_COMB 0x00000024 -#define EVENT_UDMACH14BSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_UDMACH14BSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_UDMACH14BSEL_EV_PKA_IRQ 0x0000001F -#define EVENT_UDMACH14BSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_UDMACH14BSEL_EV_AUX_SWEV1 0x0000001D -#define EVENT_UDMACH14BSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_UDMACH14BSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_UDMACH14BSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_UDMACH14BSEL_EV_WDT_IRQ 0x00000018 -#define EVENT_UDMACH14BSEL_EV_DMA_CH18_DONE 0x00000016 -#define EVENT_UDMACH14BSEL_EV_FLASH 0x00000015 -#define EVENT_UDMACH14BSEL_EV_DMA_CH0_DONE 0x00000014 -#define EVENT_UDMACH14BSEL_EV_GPT1B 0x00000013 -#define EVENT_UDMACH14BSEL_EV_GPT1A 0x00000012 -#define EVENT_UDMACH14BSEL_EV_GPT0B 0x00000011 -#define EVENT_UDMACH14BSEL_EV_GPT0A 0x00000010 -#define EVENT_UDMACH14BSEL_EV_GPT3B 0x0000000F -#define EVENT_UDMACH14BSEL_EV_GPT3A 0x0000000E -#define EVENT_UDMACH14BSEL_EV_GPT2B 0x0000000D -#define EVENT_UDMACH14BSEL_EV_GPT2A 0x0000000C -#define EVENT_UDMACH14BSEL_EV_AUX_COMB 0x0000000B -#define EVENT_UDMACH14BSEL_EV_AON_AUX_SWEV0 0x0000000A -#define EVENT_UDMACH14BSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_UDMACH14BSEL_EV_I2S_IRQ 0x00000008 -#define EVENT_UDMACH14BSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_UDMACH14BSEL_EV_OSC_COMB 0x00000006 -#define EVENT_UDMACH14BSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_UDMACH14BSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_UDMACH14BSEL_EV_AON_PROG2 0x00000003 -#define EVENT_UDMACH14BSEL_EV_AON_PROG1 0x00000002 -#define EVENT_UDMACH14BSEL_EV_AON_PROG0 0x00000001 -#define EVENT_UDMACH14BSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH15BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -#define EVENT_UDMACH15BSEL_EV_W 7 -#define EVENT_UDMACH15BSEL_EV_M 0x0000007F -#define EVENT_UDMACH15BSEL_EV_S 0 -#define EVENT_UDMACH15BSEL_EV_AON_RTC_COMB 0x00000007 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH16SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI1_RX_DMASREQ SSI1 RX DMA single request, controlled by -// SSI0:DMACR.RXDMAE -#define EVENT_UDMACH16SSEL_EV_W 7 -#define EVENT_UDMACH16SSEL_EV_M 0x0000007F -#define EVENT_UDMACH16SSEL_EV_S 0 -#define EVENT_UDMACH16SSEL_EV_SSI1_RX_DMASREQ 0x0000002D - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH16BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI1_RX_DMABREQ SSI1 RX DMA burst request , controlled by -// SSI0:DMACR.RXDMAE -#define EVENT_UDMACH16BSEL_EV_W 7 -#define EVENT_UDMACH16BSEL_EV_M 0x0000007F -#define EVENT_UDMACH16BSEL_EV_S 0 -#define EVENT_UDMACH16BSEL_EV_SSI1_RX_DMABREQ 0x0000002C - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH17SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI1_TX_DMASREQ SSI1 TX DMA single request, controlled by -// SSI0:DMACR.TXDMAE -#define EVENT_UDMACH17SSEL_EV_W 7 -#define EVENT_UDMACH17SSEL_EV_M 0x0000007F -#define EVENT_UDMACH17SSEL_EV_S 0 -#define EVENT_UDMACH17SSEL_EV_SSI1_TX_DMASREQ 0x0000002F - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH17BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SSI1_TX_DMABREQ SSI1 TX DMA burst request , controlled by -// SSI0:DMACR.TXDMAE -#define EVENT_UDMACH17BSEL_EV_W 7 -#define EVENT_UDMACH17BSEL_EV_M 0x0000007F -#define EVENT_UDMACH17BSEL_EV_S 0 -#define EVENT_UDMACH17BSEL_EV_SSI1_TX_DMABREQ 0x0000002E - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH21SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_UDMACH21SSEL_EV_W 7 -#define EVENT_UDMACH21SSEL_EV_M 0x0000007F -#define EVENT_UDMACH21SSEL_EV_S 0 -#define EVENT_UDMACH21SSEL_EV_SWEV0 0x00000064 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH21BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV0 Software event 0, triggered by SWEV.SWEV0 -#define EVENT_UDMACH21BSEL_EV_W 7 -#define EVENT_UDMACH21BSEL_EV_M 0x0000007F -#define EVENT_UDMACH21BSEL_EV_S 0 -#define EVENT_UDMACH21BSEL_EV_SWEV0 0x00000064 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH22SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV1 Software event 1, triggered by SWEV.SWEV1 -#define EVENT_UDMACH22SSEL_EV_W 7 -#define EVENT_UDMACH22SSEL_EV_M 0x0000007F -#define EVENT_UDMACH22SSEL_EV_S 0 -#define EVENT_UDMACH22SSEL_EV_SWEV1 0x00000065 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH22BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV1 Software event 1, triggered by SWEV.SWEV1 -#define EVENT_UDMACH22BSEL_EV_W 7 -#define EVENT_UDMACH22BSEL_EV_M 0x0000007F -#define EVENT_UDMACH22BSEL_EV_S 0 -#define EVENT_UDMACH22BSEL_EV_SWEV1 0x00000065 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH23SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV2 Software event 2, triggered by SWEV.SWEV2 -#define EVENT_UDMACH23SSEL_EV_W 7 -#define EVENT_UDMACH23SSEL_EV_M 0x0000007F -#define EVENT_UDMACH23SSEL_EV_S 0 -#define EVENT_UDMACH23SSEL_EV_SWEV2 0x00000066 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH23BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV2 Software event 2, triggered by SWEV.SWEV2 -#define EVENT_UDMACH23BSEL_EV_W 7 -#define EVENT_UDMACH23BSEL_EV_M 0x0000007F -#define EVENT_UDMACH23BSEL_EV_S 0 -#define EVENT_UDMACH23BSEL_EV_SWEV2 0x00000066 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH24SSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV3 Software event 3, triggered by SWEV.SWEV3 -#define EVENT_UDMACH24SSEL_EV_W 7 -#define EVENT_UDMACH24SSEL_EV_M 0x0000007F -#define EVENT_UDMACH24SSEL_EV_S 0 -#define EVENT_UDMACH24SSEL_EV_SWEV3 0x00000067 - -//***************************************************************************** -// -// Register: EVENT_O_UDMACH24BSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// SWEV3 Software event 3, triggered by SWEV.SWEV3 -#define EVENT_UDMACH24BSEL_EV_W 7 -#define EVENT_UDMACH24BSEL_EV_M 0x0000007F -#define EVENT_UDMACH24BSEL_EV_S 0 -#define EVENT_UDMACH24BSEL_EV_SWEV3 0x00000067 - -//***************************************************************************** -// -// Register: EVENT_O_GPT3ACAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status -// flags are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and -// the AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here -// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV -// PORT_EVENT7 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT7 wil be routed here. -// PORT_EVENT6 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT6 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -// UART1_COMB UART1 combined interrupt, interrupt flags are -// found here UART1:MIS -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// OSC_COMB Combined event from Oscillator control -// BATMON_COMB Combined event from battery monitor -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT3ACAPTSEL_EV_W 7 -#define EVENT_GPT3ACAPTSEL_EV_M 0x0000007F -#define EVENT_GPT3ACAPTSEL_EV_S 0 -#define EVENT_GPT3ACAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT3ACAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT3ACAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT3ACAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT3ACAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT3ACAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_GPT3ACAPTSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_GPT3ACAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT3ACAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT3ACAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT3ACAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT3ACAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT3ACAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT3ACAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT3ACAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT3ACAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT3ACAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT3ACAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT3ACAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT3ACAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT3ACAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT3ACAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT3ACAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT3ACAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT3ACAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT3ACAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT3ACAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT3ACAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT3ACAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT3ACAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT3ACAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_GPT3BCAPTSEL -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// AON_RTC_UPD RTC periodic event controlled by -// AON_RTC:CTL.RTC_UPD_EN -// AUX_ADC_IRQ AUX ADC interrupt event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_IRQ. Status -// flags are found here AUX_EVCTL:EVTOMCUFLAGS -// AUX_OBSMUX0 Loopback of OBSMUX0 through AUX, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.MCU_OBSMUX0 -// AUX_ADC_FIFO_ALMOST_FULL AUX ADC FIFO watermark event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_FIFO_ALMOST_FULL -// AUX_ADC_DONE AUX ADC done, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_ADC_DONE -// AUX_SMPH_AUTOTAKE_DONE Autotake event from AUX semaphore, configured by -// AUX_SMPH:AUTOTAKE -// AUX_TIMER1_EV AUX timer 1 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER1_EV -// AUX_TIMER0_EV AUX timer 0 event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER0_EV -// AUX_TDC_DONE AUX TDC measurement done event, corresponds to the -// flag AUX_EVCTL:EVTOMCUFLAGS.AUX_TDC_DONE and -// the AUX_TDC status AUX_TDC:STAT.DONE -// AUX_COMPB AUX Compare B event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPB -// AUX_COMPA AUX Compare A event, corresponds to -// AUX_EVCTL:EVTOMCUFLAGS.AUX_COMPA -// AUX_AON_WU_EV AON wakeup event, the corresponding flag is here -// AUX_EVCTL:EVTOMCUFLAGS.AUX_WU_EV -// PORT_EVENT7 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT7 wil be routed here. -// PORT_EVENT6 Port capture event from IOC, configured by -// IOC:IOCFGn.PORT_ID. Events on ports configured -// with ENUM PORT_EVENT6 wil be routed here. -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// AUX_TIMER2_PULSE AUX Timer2 pulse, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_PULSE -// AUX_TIMER2_EV3 AUX Timer2 event 3, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV3 -// AUX_TIMER2_EV2 AUX Timer2 event 2, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV2 -// AUX_TIMER2_EV1 AUX Timer2 event 1, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV1 -// AUX_TIMER2_EV0 AUX Timer2 event 0, corresponding to flag -// AUX_EVCTL:EVTOMCUFLAGS.AUX_TIMER2_EV0 -// UART1_COMB UART1 combined interrupt, interrupt flags are -// found here UART1:MIS -// UART0_COMB UART0 combined interrupt, interrupt flags are -// found here UART0:MIS -// SSI1_COMB SSI1 combined interrupt, interrupt flags are found -// here SSI1:MIS -// SSI0_COMB SSI0 combined interrupt, interrupt flags are found -// here SSI0:MIS -// RFC_CPE_1 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE1 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_1 event -// RFC_CPE_0 Combined Interrupt for CPE Generated events. -// Corresponding flags are here -// RFC_DBELL:RFCPEIFG. Only interrupts selected -// with CPE0 in RFC_DBELL:RFCPEIFG can trigger a -// RFC_CPE_0 event -// RFC_HW_COMB Combined RFC hardware interrupt, corresponding -// flag is here RFC_DBELL:RFHWIFG -// RFC_CMD_ACK RFC Doorbell Command Acknowledgement Interrupt, -// equvialent to RFC_DBELL:RFACKIFG.ACKFLAG -// FLASH FLASH controller error event, the status flags -// are FLASH:FEDACSTAT.FSM_DONE and -// FLASH:FEDACSTAT.RVF_INT -// AUX_COMB AUX combined event, the corresponding flag -// register is here AUX_EVCTL:EVTOMCUFLAGS -// I2C_IRQ Interrupt event from I2C -// AON_RTC_COMB Event from AON_RTC, controlled by the -// AON_RTC:CTL.COMB_EV_MASK setting -// OSC_COMB Combined event from Oscillator control -// BATMON_COMB Combined event from battery monitor -// AON_GPIO_EDGE Edge detect event from IOC. Configureded by the -// IOC:IOCFGn.EDGE_IRQ_EN and IOC:IOCFGn.EDGE_DET -// settings -// NONE Always inactive -#define EVENT_GPT3BCAPTSEL_EV_W 7 -#define EVENT_GPT3BCAPTSEL_EV_M 0x0000007F -#define EVENT_GPT3BCAPTSEL_EV_S 0 -#define EVENT_GPT3BCAPTSEL_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_UPD 0x00000077 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_IRQ 0x00000073 -#define EVENT_GPT3BCAPTSEL_EV_AUX_OBSMUX0 0x00000072 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_FIFO_ALMOST_FULL 0x00000071 -#define EVENT_GPT3BCAPTSEL_EV_AUX_ADC_DONE 0x00000070 -#define EVENT_GPT3BCAPTSEL_EV_AUX_SMPH_AUTOTAKE_DONE 0x0000006F -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER1_EV 0x0000006E -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER0_EV 0x0000006D -#define EVENT_GPT3BCAPTSEL_EV_AUX_TDC_DONE 0x0000006C -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPB 0x0000006B -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMPA 0x0000006A -#define EVENT_GPT3BCAPTSEL_EV_AUX_AON_WU_EV 0x00000069 -#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT7 0x0000005C -#define EVENT_GPT3BCAPTSEL_EV_PORT_EVENT6 0x0000005B -#define EVENT_GPT3BCAPTSEL_EV_GPT3B_CMP 0x00000044 -#define EVENT_GPT3BCAPTSEL_EV_GPT3A_CMP 0x00000043 -#define EVENT_GPT3BCAPTSEL_EV_GPT2B_CMP 0x00000042 -#define EVENT_GPT3BCAPTSEL_EV_GPT2A_CMP 0x00000041 -#define EVENT_GPT3BCAPTSEL_EV_GPT1B_CMP 0x00000040 -#define EVENT_GPT3BCAPTSEL_EV_GPT1A_CMP 0x0000003F -#define EVENT_GPT3BCAPTSEL_EV_GPT0B_CMP 0x0000003E -#define EVENT_GPT3BCAPTSEL_EV_GPT0A_CMP 0x0000003D -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_PULSE 0x0000003C -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV3 0x0000003B -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV2 0x0000003A -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV1 0x00000039 -#define EVENT_GPT3BCAPTSEL_EV_AUX_TIMER2_EV0 0x00000038 -#define EVENT_GPT3BCAPTSEL_EV_UART1_COMB 0x00000025 -#define EVENT_GPT3BCAPTSEL_EV_UART0_COMB 0x00000024 -#define EVENT_GPT3BCAPTSEL_EV_SSI1_COMB 0x00000023 -#define EVENT_GPT3BCAPTSEL_EV_SSI0_COMB 0x00000022 -#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_1 0x0000001E -#define EVENT_GPT3BCAPTSEL_EV_RFC_CPE_0 0x0000001B -#define EVENT_GPT3BCAPTSEL_EV_RFC_HW_COMB 0x0000001A -#define EVENT_GPT3BCAPTSEL_EV_RFC_CMD_ACK 0x00000019 -#define EVENT_GPT3BCAPTSEL_EV_FLASH 0x00000015 -#define EVENT_GPT3BCAPTSEL_EV_AUX_COMB 0x0000000B -#define EVENT_GPT3BCAPTSEL_EV_I2C_IRQ 0x00000009 -#define EVENT_GPT3BCAPTSEL_EV_AON_RTC_COMB 0x00000007 -#define EVENT_GPT3BCAPTSEL_EV_OSC_COMB 0x00000006 -#define EVENT_GPT3BCAPTSEL_EV_BATMON_COMB 0x00000005 -#define EVENT_GPT3BCAPTSEL_EV_AON_GPIO_EDGE 0x00000004 -#define EVENT_GPT3BCAPTSEL_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_AUXSEL0 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// GPT3B_CMP GPT3B compare event. Configured by GPT3:TBMR.TCACT -// GPT3A_CMP GPT3A compare event. Configured by GPT3:TAMR.TCACT -// GPT2B_CMP GPT2B compare event. Configured by GPT2:TBMR.TCACT -// GPT2A_CMP GPT2A compare event. Configured by GPT2:TAMR.TCACT -// GPT1B_CMP GPT1B compare event. Configured by GPT1:TBMR.TCACT -// GPT1A_CMP GPT1A compare event. Configured by GPT1:TAMR.TCACT -// GPT0B_CMP GPT0B compare event. Configured by GPT0:TBMR.TCACT -// GPT0A_CMP GPT0A compare event. Configured by GPT0:TAMR.TCACT -// GPT1B GPT1B interrupt event, controlled by GPT1:TBMR -// GPT1A GPT1A interrupt event, controlled by GPT1:TAMR -// GPT0B GPT0B interrupt event, controlled by GPT0:TBMR -// GPT0A GPT0A interrupt event, controlled by GPT0:TAMR -// GPT3B GPT3B interrupt event, controlled by GPT3:TBMR -// GPT3A GPT3A interrupt event, controlled by GPT3:TAMR -// GPT2B GPT2B interrupt event, controlled by GPT2:TBMR -// GPT2A GPT2A interrupt event, controlled by GPT2:TAMR -// NONE Always inactive -#define EVENT_AUXSEL0_EV_W 7 -#define EVENT_AUXSEL0_EV_M 0x0000007F -#define EVENT_AUXSEL0_EV_S 0 -#define EVENT_AUXSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_AUXSEL0_EV_GPT3B_CMP 0x00000044 -#define EVENT_AUXSEL0_EV_GPT3A_CMP 0x00000043 -#define EVENT_AUXSEL0_EV_GPT2B_CMP 0x00000042 -#define EVENT_AUXSEL0_EV_GPT2A_CMP 0x00000041 -#define EVENT_AUXSEL0_EV_GPT1B_CMP 0x00000040 -#define EVENT_AUXSEL0_EV_GPT1A_CMP 0x0000003F -#define EVENT_AUXSEL0_EV_GPT0B_CMP 0x0000003E -#define EVENT_AUXSEL0_EV_GPT0A_CMP 0x0000003D -#define EVENT_AUXSEL0_EV_GPT1B 0x00000013 -#define EVENT_AUXSEL0_EV_GPT1A 0x00000012 -#define EVENT_AUXSEL0_EV_GPT0B 0x00000011 -#define EVENT_AUXSEL0_EV_GPT0A 0x00000010 -#define EVENT_AUXSEL0_EV_GPT3B 0x0000000F -#define EVENT_AUXSEL0_EV_GPT3A 0x0000000E -#define EVENT_AUXSEL0_EV_GPT2B 0x0000000D -#define EVENT_AUXSEL0_EV_GPT2A 0x0000000C -#define EVENT_AUXSEL0_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_CM3NMISEL0 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read only selection value -// ENUMs: -// WDT_NMI Watchdog non maskable interrupt event, controlled -// by WDT:CTL.INTTYPE -#define EVENT_CM3NMISEL0_EV_W 7 -#define EVENT_CM3NMISEL0_EV_M 0x0000007F -#define EVENT_CM3NMISEL0_EV_S 0 -#define EVENT_CM3NMISEL0_EV_WDT_NMI 0x00000063 - -//***************************************************************************** -// -// Register: EVENT_O_I2SSTMPSEL0 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// NONE Always inactive -#define EVENT_I2SSTMPSEL0_EV_W 7 -#define EVENT_I2SSTMPSEL0_EV_M 0x0000007F -#define EVENT_I2SSTMPSEL0_EV_S 0 -#define EVENT_I2SSTMPSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_I2SSTMPSEL0_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_FRZSEL0 -// -//***************************************************************************** -// Field: [6:0] EV -// -// Read/write selection value -// -// Writing any other value than values defined by a ENUM may result in -// undefined behavior. -// ENUMs: -// ALWAYS_ACTIVE Always asserted -// CPU_HALTED CPU halted -// NONE Always inactive -#define EVENT_FRZSEL0_EV_W 7 -#define EVENT_FRZSEL0_EV_M 0x0000007F -#define EVENT_FRZSEL0_EV_S 0 -#define EVENT_FRZSEL0_EV_ALWAYS_ACTIVE 0x00000079 -#define EVENT_FRZSEL0_EV_CPU_HALTED 0x00000078 -#define EVENT_FRZSEL0_EV_NONE 0x00000000 - -//***************************************************************************** -// -// Register: EVENT_O_SWEV -// -//***************************************************************************** -// Field: [24] SWEV3 -// -// Writing "1" to this bit when the value is "0" triggers the Software 3 event. -#define EVENT_SWEV_SWEV3 0x01000000 -#define EVENT_SWEV_SWEV3_BITN 24 -#define EVENT_SWEV_SWEV3_M 0x01000000 -#define EVENT_SWEV_SWEV3_S 24 - -// Field: [16] SWEV2 -// -// Writing "1" to this bit when the value is "0" triggers the Software 2 event. -#define EVENT_SWEV_SWEV2 0x00010000 -#define EVENT_SWEV_SWEV2_BITN 16 -#define EVENT_SWEV_SWEV2_M 0x00010000 -#define EVENT_SWEV_SWEV2_S 16 - -// Field: [8] SWEV1 -// -// Writing "1" to this bit when the value is "0" triggers the Software 1 event. -#define EVENT_SWEV_SWEV1 0x00000100 -#define EVENT_SWEV_SWEV1_BITN 8 -#define EVENT_SWEV_SWEV1_M 0x00000100 -#define EVENT_SWEV_SWEV1_S 8 - -// Field: [0] SWEV0 -// -// Writing "1" to this bit when the value is "0" triggers the Software 0 event. -#define EVENT_SWEV_SWEV0 0x00000001 -#define EVENT_SWEV_SWEV0_BITN 0 -#define EVENT_SWEV_SWEV0_M 0x00000001 -#define EVENT_SWEV_SWEV0_S 0 - - -#endif // __EVENT__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h deleted file mode 100644 index cd6cb570d98..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_fcfg1.h +++ /dev/null @@ -1,2904 +0,0 @@ -/****************************************************************************** -* Filename: hw_fcfg1_h -* Revised: 2018-11-06 14:08:24 +0100 (Tue, 06 Nov 2018) -* Revision: 53237 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_FCFG1_H__ -#define __HW_FCFG1_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// FCFG1 component -// -//***************************************************************************** -// Misc configurations -#define FCFG1_O_MISC_CONF_1 0x000000A0 - -// Internal -#define FCFG1_O_MISC_CONF_2 0x000000A4 - -// Internal -#define FCFG1_O_HPOSC_MEAS_5 0x000000B0 - -// Internal -#define FCFG1_O_HPOSC_MEAS_4 0x000000B4 - -// Internal -#define FCFG1_O_HPOSC_MEAS_3 0x000000B8 - -// Internal -#define FCFG1_O_HPOSC_MEAS_2 0x000000BC - -// Internal -#define FCFG1_O_HPOSC_MEAS_1 0x000000C0 - -// Internal -#define FCFG1_O_CONFIG_CC26_FE 0x000000C4 - -// Internal -#define FCFG1_O_CONFIG_CC13_FE 0x000000C8 - -// Internal -#define FCFG1_O_CONFIG_RF_COMMON 0x000000CC - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 0x000000D0 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 0x000000D4 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G 0x000000D8 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G 0x000000DC - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV4_CC26 0x000000E0 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV4_CC13 0x000000E4 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV5 0x000000E8 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV6_CC26 0x000000EC - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV6_CC13 0x000000F0 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV10 0x000000F4 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV12_CC26 0x000000F8 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV12_CC13 0x000000FC - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV15 0x00000100 - -// Internal -#define FCFG1_O_CONFIG_SYNTH_DIV30 0x00000104 - -// Flash information -#define FCFG1_O_FLASH_NUMBER 0x00000164 - -// Flash information -#define FCFG1_O_FLASH_COORDINATE 0x0000016C - -// Internal -#define FCFG1_O_FLASH_E_P 0x00000170 - -// Internal -#define FCFG1_O_FLASH_C_E_P_R 0x00000174 - -// Internal -#define FCFG1_O_FLASH_P_R_PV 0x00000178 - -// Internal -#define FCFG1_O_FLASH_EH_SEQ 0x0000017C - -// Internal -#define FCFG1_O_FLASH_VHV_E 0x00000180 - -// Internal -#define FCFG1_O_FLASH_PP 0x00000184 - -// Internal -#define FCFG1_O_FLASH_PROG_EP 0x00000188 - -// Internal -#define FCFG1_O_FLASH_ERA_PW 0x0000018C - -// Internal -#define FCFG1_O_FLASH_VHV 0x00000190 - -// Internal -#define FCFG1_O_FLASH_VHV_PV 0x00000194 - -// Internal -#define FCFG1_O_FLASH_V 0x00000198 - -// User Identification. -#define FCFG1_O_USER_ID 0x00000294 - -// Internal -#define FCFG1_O_FLASH_OTP_DATA3 0x000002B0 - -// Internal -#define FCFG1_O_ANA2_TRIM 0x000002B4 - -// Internal -#define FCFG1_O_LDO_TRIM 0x000002B8 - -// MAC BLE Address 0 -#define FCFG1_O_MAC_BLE_0 0x000002E8 - -// MAC BLE Address 1 -#define FCFG1_O_MAC_BLE_1 0x000002EC - -// MAC IEEE 802.15.4 Address 0 -#define FCFG1_O_MAC_15_4_0 0x000002F0 - -// MAC IEEE 802.15.4 Address 1 -#define FCFG1_O_MAC_15_4_1 0x000002F4 - -// Internal -#define FCFG1_O_FLASH_OTP_DATA4 0x00000308 - -// Miscellaneous Trim Parameters -#define FCFG1_O_MISC_TRIM 0x0000030C - -// Internal -#define FCFG1_O_RCOSC_HF_TEMPCOMP 0x00000310 - -// IcePick Device Identification -#define FCFG1_O_ICEPICK_DEVICE_ID 0x00000318 - -// Factory Configuration (FCFG1) Revision -#define FCFG1_O_FCFG1_REVISION 0x0000031C - -// Misc OTP Data -#define FCFG1_O_MISC_OTP_DATA 0x00000320 - -// IO Configuration -#define FCFG1_O_IOCONF 0x00000344 - -// Internal -#define FCFG1_O_CONFIG_IF_ADC 0x0000034C - -// Internal -#define FCFG1_O_CONFIG_OSC_TOP 0x00000350 - -// AUX_ADC Gain in Absolute Reference Mode -#define FCFG1_O_SOC_ADC_ABS_GAIN 0x0000035C - -// AUX_ADC Gain in Relative Reference Mode -#define FCFG1_O_SOC_ADC_REL_GAIN 0x00000360 - -// AUX_ADC Temperature Offsets in Absolute Reference Mode -#define FCFG1_O_SOC_ADC_OFFSET_INT 0x00000368 - -// Internal -#define FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT 0x0000036C - -// Internal -#define FCFG1_O_AMPCOMP_TH1 0x00000370 - -// Internal -#define FCFG1_O_AMPCOMP_TH2 0x00000374 - -// Internal -#define FCFG1_O_AMPCOMP_CTRL1 0x00000378 - -// Internal -#define FCFG1_O_ANABYPASS_VALUE2 0x0000037C - -// Internal -#define FCFG1_O_VOLT_TRIM 0x00000388 - -// OSC Configuration -#define FCFG1_O_OSC_CONF 0x0000038C - -// Internal -#define FCFG1_O_FREQ_OFFSET 0x00000390 - -// Internal -#define FCFG1_O_MISC_OTP_DATA_1 0x00000398 - -// Shadow of EFUSE:DIE_ID_0 register -#define FCFG1_O_SHDW_DIE_ID_0 0x000003D0 - -// Shadow of EFUSE:DIE_ID_1 register -#define FCFG1_O_SHDW_DIE_ID_1 0x000003D4 - -// Shadow of EFUSE:DIE_ID_2 register -#define FCFG1_O_SHDW_DIE_ID_2 0x000003D8 - -// Shadow of EFUSE:DIE_ID_3 register -#define FCFG1_O_SHDW_DIE_ID_3 0x000003DC - -// Internal -#define FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM 0x000003F8 - -// Internal -#define FCFG1_O_SHDW_ANA_TRIM 0x000003FC - -// Internal -#define FCFG1_O_DAC_BIAS_CNF 0x0000040C - -// Internal -#define FCFG1_O_TFW_PROBE 0x00000418 - -// Internal -#define FCFG1_O_TFW_FT 0x0000041C - -// Internal -#define FCFG1_O_DAC_CAL0 0x00000420 - -// Internal -#define FCFG1_O_DAC_CAL1 0x00000424 - -// Internal -#define FCFG1_O_DAC_CAL2 0x00000428 - -// Internal -#define FCFG1_O_DAC_CAL3 0x0000042C - -//***************************************************************************** -// -// Register: FCFG1_O_MISC_CONF_1 -// -//***************************************************************************** -// Field: [7:0] DEVICE_MINOR_REV -// -// HW minor revision number (a value of 0xFF shall be treated equally to 0x00). -// Any test of this field by SW should be implemented as a 'greater or equal' -// comparison as signed integer. -// Value may change without warning. -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_W 8 -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_M 0x000000FF -#define FCFG1_MISC_CONF_1_DEVICE_MINOR_REV_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MISC_CONF_2 -// -//***************************************************************************** -// Field: [7:0] HPOSC_COMP_P3 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_W 8 -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_M 0x000000FF -#define FCFG1_MISC_CONF_2_HPOSC_COMP_P3_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_HPOSC_MEAS_5 -// -//***************************************************************************** -// Field: [31:16] HPOSC_D5 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_W 16 -#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_M 0xFFFF0000 -#define FCFG1_HPOSC_MEAS_5_HPOSC_D5_S 16 - -// Field: [15:8] HPOSC_T5 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_W 8 -#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_M 0x0000FF00 -#define FCFG1_HPOSC_MEAS_5_HPOSC_T5_S 8 - -// Field: [7:0] HPOSC_DT5 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_W 8 -#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_M 0x000000FF -#define FCFG1_HPOSC_MEAS_5_HPOSC_DT5_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_HPOSC_MEAS_4 -// -//***************************************************************************** -// Field: [31:16] HPOSC_D4 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_W 16 -#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_M 0xFFFF0000 -#define FCFG1_HPOSC_MEAS_4_HPOSC_D4_S 16 - -// Field: [15:8] HPOSC_T4 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_W 8 -#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_M 0x0000FF00 -#define FCFG1_HPOSC_MEAS_4_HPOSC_T4_S 8 - -// Field: [7:0] HPOSC_DT4 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_W 8 -#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_M 0x000000FF -#define FCFG1_HPOSC_MEAS_4_HPOSC_DT4_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_HPOSC_MEAS_3 -// -//***************************************************************************** -// Field: [31:16] HPOSC_D3 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_W 16 -#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_M 0xFFFF0000 -#define FCFG1_HPOSC_MEAS_3_HPOSC_D3_S 16 - -// Field: [15:8] HPOSC_T3 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_W 8 -#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_M 0x0000FF00 -#define FCFG1_HPOSC_MEAS_3_HPOSC_T3_S 8 - -// Field: [7:0] HPOSC_DT3 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_W 8 -#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_M 0x000000FF -#define FCFG1_HPOSC_MEAS_3_HPOSC_DT3_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_HPOSC_MEAS_2 -// -//***************************************************************************** -// Field: [31:16] HPOSC_D2 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_W 16 -#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_M 0xFFFF0000 -#define FCFG1_HPOSC_MEAS_2_HPOSC_D2_S 16 - -// Field: [15:8] HPOSC_T2 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_W 8 -#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_M 0x0000FF00 -#define FCFG1_HPOSC_MEAS_2_HPOSC_T2_S 8 - -// Field: [7:0] HPOSC_DT2 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_W 8 -#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_M 0x000000FF -#define FCFG1_HPOSC_MEAS_2_HPOSC_DT2_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_HPOSC_MEAS_1 -// -//***************************************************************************** -// Field: [31:16] HPOSC_D1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_W 16 -#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_M 0xFFFF0000 -#define FCFG1_HPOSC_MEAS_1_HPOSC_D1_S 16 - -// Field: [15:8] HPOSC_T1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_W 8 -#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_M 0x0000FF00 -#define FCFG1_HPOSC_MEAS_1_HPOSC_T1_S 8 - -// Field: [7:0] HPOSC_DT1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_W 8 -#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_M 0x000000FF -#define FCFG1_HPOSC_MEAS_1_HPOSC_DT1_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_CC26_FE -// -//***************************************************************************** -// Field: [31:28] IFAMP_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_W 4 -#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_CC26_FE_IFAMP_IB_S 28 - -// Field: [27:24] LNA_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_LNA_IB_W 4 -#define FCFG1_CONFIG_CC26_FE_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_CC26_FE_LNA_IB_S 24 - -// Field: [23:19] IFAMP_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_CC26_FE_IFAMP_TRIM_S 19 - -// Field: [18:14] CTL_PA0_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_CC26_FE_CTL_PA0_TRIM_S 14 - -// Field: [13] PATRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N 0x00002000 -#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_BITN 13 -#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_M 0x00002000 -#define FCFG1_CONFIG_CC26_FE_PATRIMCOMPLETE_N_S 13 - -// Field: [12] RSSITRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N 0x00001000 -#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_BITN 12 -#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_M 0x00001000 -#define FCFG1_CONFIG_CC26_FE_RSSITRIMCOMPLETE_N_S 12 - -// Field: [7:0] RSSI_OFFSET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_M 0x000000FF -#define FCFG1_CONFIG_CC26_FE_RSSI_OFFSET_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_CC13_FE -// -//***************************************************************************** -// Field: [31:28] IFAMP_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_W 4 -#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_M 0xF0000000 -#define FCFG1_CONFIG_CC13_FE_IFAMP_IB_S 28 - -// Field: [27:24] LNA_IB -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_LNA_IB_W 4 -#define FCFG1_CONFIG_CC13_FE_LNA_IB_M 0x0F000000 -#define FCFG1_CONFIG_CC13_FE_LNA_IB_S 24 - -// Field: [23:19] IFAMP_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_W 5 -#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_M 0x00F80000 -#define FCFG1_CONFIG_CC13_FE_IFAMP_TRIM_S 19 - -// Field: [18:14] CTL_PA0_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_W 5 -#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_M 0x0007C000 -#define FCFG1_CONFIG_CC13_FE_CTL_PA0_TRIM_S 14 - -// Field: [13] PATRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N 0x00002000 -#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_BITN 13 -#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_M 0x00002000 -#define FCFG1_CONFIG_CC13_FE_PATRIMCOMPLETE_N_S 13 - -// Field: [12] RSSITRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N 0x00001000 -#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_BITN 12 -#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_M 0x00001000 -#define FCFG1_CONFIG_CC13_FE_RSSITRIMCOMPLETE_N_S 12 - -// Field: [7:0] RSSI_OFFSET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_W 8 -#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_M 0x000000FF -#define FCFG1_CONFIG_CC13_FE_RSSI_OFFSET_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_RF_COMMON -// -//***************************************************************************** -// Field: [31] DISABLE_CORNER_CAP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP 0x80000000 -#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_BITN 31 -#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_M 0x80000000 -#define FCFG1_CONFIG_RF_COMMON_DISABLE_CORNER_CAP_S 31 - -// Field: [30:25] SLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_M 0x7E000000 -#define FCFG1_CONFIG_RF_COMMON_SLDO_TRIM_OUTPUT_S 25 - -// Field: [21] PA20DBMTRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N 0x00200000 -#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_BITN 21 -#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_M 0x00200000 -#define FCFG1_CONFIG_RF_COMMON_PA20DBMTRIMCOMPLETE_N_S 21 - -// Field: [20:16] CTL_PA_20DBM_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_W 5 -#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_M 0x001F0000 -#define FCFG1_CONFIG_RF_COMMON_CTL_PA_20DBM_TRIM_S 16 - -// Field: [15:9] RFLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_W 7 -#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_M 0x0000FE00 -#define FCFG1_CONFIG_RF_COMMON_RFLDO_TRIM_OUTPUT_S 9 - -// Field: [8:6] QUANTCTLTHRES -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_W 3 -#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_M 0x000001C0 -#define FCFG1_CONFIG_RF_COMMON_QUANTCTLTHRES_S 6 - -// Field: [5:0] DACTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_RF_COMMON_DACTRIM_W 6 -#define FCFG1_CONFIG_RF_COMMON_DACTRIM_M 0x0000003F -#define FCFG1_CONFIG_RF_COMMON_DACTRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC26_2G4 -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC13_2G4 -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_2G4_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC26_1G -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV2_CC26_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV2_CC13_1G -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV2_CC13_1G_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV4_CC26 -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV4_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV4_CC13 -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV4_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV5 -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV5_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV5_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV5_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV6_CC26 -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV6_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV6_CC13 -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV6_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV10 -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV10_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV10_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV10_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV12_CC26 -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV12_CC26_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV12_CC13 -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV12_CC13_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV15 -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV15_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV15_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV15_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_SYNTH_DIV30 -// -//***************************************************************************** -// Field: [31:28] MIN_ALLOWED_RTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_W 4 -#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_M 0xF0000000 -#define FCFG1_CONFIG_SYNTH_DIV30_MIN_ALLOWED_RTRIM_S 28 - -// Field: [27:12] RFC_MDM_DEMIQMC0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_W 16 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_M 0x0FFFF000 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_S 12 - -// Field: [11:6] LDOVCO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_W 6 -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_M 0x00000FC0 -#define FCFG1_CONFIG_SYNTH_DIV30_LDOVCO_TRIM_OUTPUT_S 6 - -// Field: [5] RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_BITN \ - 5 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_M \ - 0x00000020 -#define FCFG1_CONFIG_SYNTH_DIV30_RFC_MDM_DEMIQMC0_TRIMCOMPLETE_N_S \ - 5 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_NUMBER -// -//***************************************************************************** -// Field: [31:0] LOT_NUMBER -// -// Number of the manufacturing lot that produced this unit. -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_W 32 -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_M 0xFFFFFFFF -#define FCFG1_FLASH_NUMBER_LOT_NUMBER_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_COORDINATE -// -//***************************************************************************** -// Field: [31:16] XCOORDINATE -// -// X coordinate of this unit on the wafer. -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_W 16 -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_M 0xFFFF0000 -#define FCFG1_FLASH_COORDINATE_XCOORDINATE_S 16 - -// Field: [15:0] YCOORDINATE -// -// Y coordinate of this unit on the wafer. -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_W 16 -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_M 0x0000FFFF -#define FCFG1_FLASH_COORDINATE_YCOORDINATE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_E_P -// -//***************************************************************************** -// Field: [31:24] PSU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_PSU_W 8 -#define FCFG1_FLASH_E_P_PSU_M 0xFF000000 -#define FCFG1_FLASH_E_P_PSU_S 24 - -// Field: [23:16] ESU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_ESU_W 8 -#define FCFG1_FLASH_E_P_ESU_M 0x00FF0000 -#define FCFG1_FLASH_E_P_ESU_S 16 - -// Field: [15:8] PVSU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_PVSU_W 8 -#define FCFG1_FLASH_E_P_PVSU_M 0x0000FF00 -#define FCFG1_FLASH_E_P_PVSU_S 8 - -// Field: [7:0] EVSU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_E_P_EVSU_W 8 -#define FCFG1_FLASH_E_P_EVSU_M 0x000000FF -#define FCFG1_FLASH_E_P_EVSU_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_C_E_P_R -// -//***************************************************************************** -// Field: [31:24] RVSU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_RVSU_W 8 -#define FCFG1_FLASH_C_E_P_R_RVSU_M 0xFF000000 -#define FCFG1_FLASH_C_E_P_R_RVSU_S 24 - -// Field: [23:16] PV_ACCESS -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_W 8 -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_M 0x00FF0000 -#define FCFG1_FLASH_C_E_P_R_PV_ACCESS_S 16 - -// Field: [15:12] A_EXEZ_SETUP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_W 4 -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_M 0x0000F000 -#define FCFG1_FLASH_C_E_P_R_A_EXEZ_SETUP_S 12 - -// Field: [11:0] CVSU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_C_E_P_R_CVSU_W 12 -#define FCFG1_FLASH_C_E_P_R_CVSU_M 0x00000FFF -#define FCFG1_FLASH_C_E_P_R_CVSU_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_P_R_PV -// -//***************************************************************************** -// Field: [31:24] PH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PH_W 8 -#define FCFG1_FLASH_P_R_PV_PH_M 0xFF000000 -#define FCFG1_FLASH_P_R_PV_PH_S 24 - -// Field: [23:16] RH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_RH_W 8 -#define FCFG1_FLASH_P_R_PV_RH_M 0x00FF0000 -#define FCFG1_FLASH_P_R_PV_RH_S 16 - -// Field: [15:8] PVH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PVH_W 8 -#define FCFG1_FLASH_P_R_PV_PVH_M 0x0000FF00 -#define FCFG1_FLASH_P_R_PV_PVH_S 8 - -// Field: [7:0] PVH2 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_P_R_PV_PVH2_W 8 -#define FCFG1_FLASH_P_R_PV_PVH2_M 0x000000FF -#define FCFG1_FLASH_P_R_PV_PVH2_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_EH_SEQ -// -//***************************************************************************** -// Field: [31:24] EH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_EH_W 8 -#define FCFG1_FLASH_EH_SEQ_EH_M 0xFF000000 -#define FCFG1_FLASH_EH_SEQ_EH_S 24 - -// Field: [23:16] SEQ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_SEQ_W 8 -#define FCFG1_FLASH_EH_SEQ_SEQ_M 0x00FF0000 -#define FCFG1_FLASH_EH_SEQ_SEQ_S 16 - -// Field: [15:12] VSTAT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_VSTAT_W 4 -#define FCFG1_FLASH_EH_SEQ_VSTAT_M 0x0000F000 -#define FCFG1_FLASH_EH_SEQ_VSTAT_S 12 - -// Field: [11:0] SM_FREQUENCY -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_W 12 -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_M 0x00000FFF -#define FCFG1_FLASH_EH_SEQ_SM_FREQUENCY_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_VHV_E -// -//***************************************************************************** -// Field: [31:16] VHV_E_START -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_E_VHV_E_START_W 16 -#define FCFG1_FLASH_VHV_E_VHV_E_START_M 0xFFFF0000 -#define FCFG1_FLASH_VHV_E_VHV_E_START_S 16 - -// Field: [15:0] VHV_E_STEP_HIGHT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_W 16 -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_M 0x0000FFFF -#define FCFG1_FLASH_VHV_E_VHV_E_STEP_HIGHT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_PP -// -//***************************************************************************** -// Field: [31:24] PUMP_SU -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PP_PUMP_SU_W 8 -#define FCFG1_FLASH_PP_PUMP_SU_M 0xFF000000 -#define FCFG1_FLASH_PP_PUMP_SU_S 24 - -// Field: [23:16] TRIM3P4 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PP_TRIM3P4_W 8 -#define FCFG1_FLASH_PP_TRIM3P4_M 0x00FF0000 -#define FCFG1_FLASH_PP_TRIM3P4_S 16 - -// Field: [15:0] MAX_PP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PP_MAX_PP_W 16 -#define FCFG1_FLASH_PP_MAX_PP_M 0x0000FFFF -#define FCFG1_FLASH_PP_MAX_PP_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_PROG_EP -// -//***************************************************************************** -// Field: [31:16] MAX_EP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PROG_EP_MAX_EP_W 16 -#define FCFG1_FLASH_PROG_EP_MAX_EP_M 0xFFFF0000 -#define FCFG1_FLASH_PROG_EP_MAX_EP_S 16 - -// Field: [15:0] PROGRAM_PW -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_W 16 -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_M 0x0000FFFF -#define FCFG1_FLASH_PROG_EP_PROGRAM_PW_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_ERA_PW -// -//***************************************************************************** -// Field: [31:0] ERASE_PW -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_ERA_PW_ERASE_PW_W 32 -#define FCFG1_FLASH_ERA_PW_ERASE_PW_M 0xFFFFFFFF -#define FCFG1_FLASH_ERA_PW_ERASE_PW_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_VHV -// -//***************************************************************************** -// Field: [27:24] TRIM13_P -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_TRIM13_P_W 4 -#define FCFG1_FLASH_VHV_TRIM13_P_M 0x0F000000 -#define FCFG1_FLASH_VHV_TRIM13_P_S 24 - -// Field: [19:16] VHV_P -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_VHV_P_W 4 -#define FCFG1_FLASH_VHV_VHV_P_M 0x000F0000 -#define FCFG1_FLASH_VHV_VHV_P_S 16 - -// Field: [11:8] TRIM13_E -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_TRIM13_E_W 4 -#define FCFG1_FLASH_VHV_TRIM13_E_M 0x00000F00 -#define FCFG1_FLASH_VHV_TRIM13_E_S 8 - -// Field: [3:0] VHV_E -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_VHV_E_W 4 -#define FCFG1_FLASH_VHV_VHV_E_M 0x0000000F -#define FCFG1_FLASH_VHV_VHV_E_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_VHV_PV -// -//***************************************************************************** -// Field: [27:24] TRIM13_PV -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_W 4 -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_M 0x0F000000 -#define FCFG1_FLASH_VHV_PV_TRIM13_PV_S 24 - -// Field: [19:16] VHV_PV -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VHV_PV_W 4 -#define FCFG1_FLASH_VHV_PV_VHV_PV_M 0x000F0000 -#define FCFG1_FLASH_VHV_PV_VHV_PV_S 16 - -// Field: [15:8] VCG2P5 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VCG2P5_W 8 -#define FCFG1_FLASH_VHV_PV_VCG2P5_M 0x0000FF00 -#define FCFG1_FLASH_VHV_PV_VCG2P5_S 8 - -// Field: [7:0] VINH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_VHV_PV_VINH_W 8 -#define FCFG1_FLASH_VHV_PV_VINH_M 0x000000FF -#define FCFG1_FLASH_VHV_PV_VINH_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_V -// -//***************************************************************************** -// Field: [31:24] VSL_P -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_VSL_P_W 8 -#define FCFG1_FLASH_V_VSL_P_M 0xFF000000 -#define FCFG1_FLASH_V_VSL_P_S 24 - -// Field: [23:16] VWL_P -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_VWL_P_W 8 -#define FCFG1_FLASH_V_VWL_P_M 0x00FF0000 -#define FCFG1_FLASH_V_VWL_P_S 16 - -// Field: [15:8] V_READ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_V_READ_W 8 -#define FCFG1_FLASH_V_V_READ_M 0x0000FF00 -#define FCFG1_FLASH_V_V_READ_S 8 - -// Field: [7:0] TRIM0P8 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_V_TRIM0P8_W 8 -#define FCFG1_FLASH_V_TRIM0P8_M 0x000000FF -#define FCFG1_FLASH_V_TRIM0P8_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_USER_ID -// -//***************************************************************************** -// Field: [31:28] PG_REV -// -// Field used to distinguish revisions of the device -#define FCFG1_USER_ID_PG_REV_W 4 -#define FCFG1_USER_ID_PG_REV_M 0xF0000000 -#define FCFG1_USER_ID_PG_REV_S 28 - -// Field: [27:26] VER -// -// Version number. -// -// 0x0: Bits [25:12] of this register has the stated meaning. -// -// Any other setting indicate a different encoding of these bits. -#define FCFG1_USER_ID_VER_W 2 -#define FCFG1_USER_ID_VER_M 0x0C000000 -#define FCFG1_USER_ID_VER_S 26 - -// Field: [25] PA -// -// 0: Does not support 20dBm PA -// 1: Supports 20dBM PA -#define FCFG1_USER_ID_PA 0x02000000 -#define FCFG1_USER_ID_PA_BITN 25 -#define FCFG1_USER_ID_PA_M 0x02000000 -#define FCFG1_USER_ID_PA_S 25 - -// Field: [23] CC13 -// -// 0: CC26xx device type -// 1: CC13xx device type -#define FCFG1_USER_ID_CC13 0x00800000 -#define FCFG1_USER_ID_CC13_BITN 23 -#define FCFG1_USER_ID_CC13_M 0x00800000 -#define FCFG1_USER_ID_CC13_S 23 - -// Field: [22:19] SEQUENCE -// -// Sequence. -// -// Used to differentiate between marketing/orderable product where other fields -// of this register are the same (temp range, flash size, voltage range etc) -#define FCFG1_USER_ID_SEQUENCE_W 4 -#define FCFG1_USER_ID_SEQUENCE_M 0x00780000 -#define FCFG1_USER_ID_SEQUENCE_S 19 - -// Field: [18:16] PKG -// -// Package type. -// -// 0x0: 4x4mm QFN (RHB) package -// 0x1: 5x5mm QFN (RSM) package -// 0x2: 7x7mm QFN (RGZ) package -// 0x3: Wafer sale package (naked die) -// 0x4: WCSP (YFV) -// 0x5: 7x7mm QFN package with Wettable Flanks -// -// Other values are reserved for future use. -// Packages available for a specific device are shown in the device datasheet. -#define FCFG1_USER_ID_PKG_W 3 -#define FCFG1_USER_ID_PKG_M 0x00070000 -#define FCFG1_USER_ID_PKG_S 16 - -// Field: [15:12] PROTOCOL -// -// Protocols supported. -// -// 0x1: BLE -// 0x2: RF4CE -// 0x4: Zigbee/6lowpan -// 0x8: Proprietary -// -// More than one protocol can be supported on same device - values above are -// then combined. -#define FCFG1_USER_ID_PROTOCOL_W 4 -#define FCFG1_USER_ID_PROTOCOL_M 0x0000F000 -#define FCFG1_USER_ID_PROTOCOL_S 12 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_OTP_DATA3 -// -//***************************************************************************** -// Field: [31:23] EC_STEP_SIZE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_W 9 -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_M 0xFF800000 -#define FCFG1_FLASH_OTP_DATA3_EC_STEP_SIZE_S 23 - -// Field: [22] DO_PRECOND -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND 0x00400000 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_BITN 22 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_M 0x00400000 -#define FCFG1_FLASH_OTP_DATA3_DO_PRECOND_S 22 - -// Field: [21:18] MAX_EC_LEVEL -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_W 4 -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_M 0x003C0000 -#define FCFG1_FLASH_OTP_DATA3_MAX_EC_LEVEL_S 18 - -// Field: [17:16] TRIM_1P7 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_W 2 -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_M 0x00030000 -#define FCFG1_FLASH_OTP_DATA3_TRIM_1P7_S 16 - -// Field: [15:8] FLASH_SIZE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_W 8 -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_M 0x0000FF00 -#define FCFG1_FLASH_OTP_DATA3_FLASH_SIZE_S 8 - -// Field: [7:0] WAIT_SYSCODE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_W 8 -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_M 0x000000FF -#define FCFG1_FLASH_OTP_DATA3_WAIT_SYSCODE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_ANA2_TRIM -// -//***************************************************************************** -// Field: [31] RCOSCHFCTRIMFRACT_EN -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN 0x80000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_BITN 31 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_M 0x80000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_EN_S 31 - -// Field: [30:26] RCOSCHFCTRIMFRACT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_W 5 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_M 0x7C000000 -#define FCFG1_ANA2_TRIM_RCOSCHFCTRIMFRACT_S 26 - -// Field: [24:23] SET_RCOSC_HF_FINE_RESISTOR -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_W 2 -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_M 0x01800000 -#define FCFG1_ANA2_TRIM_SET_RCOSC_HF_FINE_RESISTOR_S 23 - -// Field: [22] ATESTLF_UDIGLDO_IBIAS_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM 0x00400000 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_BITN 22 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_M 0x00400000 -#define FCFG1_ANA2_TRIM_ATESTLF_UDIGLDO_IBIAS_TRIM_S 22 - -// Field: [21:15] NANOAMP_RES_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_W 7 -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_M 0x003F8000 -#define FCFG1_ANA2_TRIM_NANOAMP_RES_TRIM_S 15 - -// Field: [11] DITHER_EN -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DITHER_EN 0x00000800 -#define FCFG1_ANA2_TRIM_DITHER_EN_BITN 11 -#define FCFG1_ANA2_TRIM_DITHER_EN_M 0x00000800 -#define FCFG1_ANA2_TRIM_DITHER_EN_S 11 - -// Field: [10:8] DCDC_IPEAK -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_W 3 -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_M 0x00000700 -#define FCFG1_ANA2_TRIM_DCDC_IPEAK_S 8 - -// Field: [7:6] DEAD_TIME_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_W 2 -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_M 0x000000C0 -#define FCFG1_ANA2_TRIM_DEAD_TIME_TRIM_S 6 - -// Field: [5:3] DCDC_LOW_EN_SEL -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_W 3 -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_M 0x00000038 -#define FCFG1_ANA2_TRIM_DCDC_LOW_EN_SEL_S 3 - -// Field: [2:0] DCDC_HIGH_EN_SEL -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_W 3 -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_M 0x00000007 -#define FCFG1_ANA2_TRIM_DCDC_HIGH_EN_SEL_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_LDO_TRIM -// -//***************************************************************************** -// Field: [28:24] VDDR_TRIM_SLEEP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_W 5 -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_M 0x1F000000 -#define FCFG1_LDO_TRIM_VDDR_TRIM_SLEEP_S 24 - -// Field: [18:16] GLDO_CURSRC -// -// Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_GLDO_CURSRC_W 3 -#define FCFG1_LDO_TRIM_GLDO_CURSRC_M 0x00070000 -#define FCFG1_LDO_TRIM_GLDO_CURSRC_S 16 - -// Field: [12:11] ITRIM_DIGLDO_LOAD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_W 2 -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_M 0x00001800 -#define FCFG1_LDO_TRIM_ITRIM_DIGLDO_LOAD_S 11 - -// Field: [10:8] ITRIM_UDIGLDO -// -// Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_W 3 -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_M 0x00000700 -#define FCFG1_LDO_TRIM_ITRIM_UDIGLDO_S 8 - -// Field: [2:0] VTRIM_DELTA -// -// Internal. Only to be used through TI provided API. -#define FCFG1_LDO_TRIM_VTRIM_DELTA_W 3 -#define FCFG1_LDO_TRIM_VTRIM_DELTA_M 0x00000007 -#define FCFG1_LDO_TRIM_VTRIM_DELTA_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MAC_BLE_0 -// -//***************************************************************************** -// Field: [31:0] ADDR_0_31 -// -// The first 32-bits of the 64-bit MAC BLE address -#define FCFG1_MAC_BLE_0_ADDR_0_31_W 32 -#define FCFG1_MAC_BLE_0_ADDR_0_31_M 0xFFFFFFFF -#define FCFG1_MAC_BLE_0_ADDR_0_31_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MAC_BLE_1 -// -//***************************************************************************** -// Field: [31:0] ADDR_32_63 -// -// The last 32-bits of the 64-bit MAC BLE address -#define FCFG1_MAC_BLE_1_ADDR_32_63_W 32 -#define FCFG1_MAC_BLE_1_ADDR_32_63_M 0xFFFFFFFF -#define FCFG1_MAC_BLE_1_ADDR_32_63_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MAC_15_4_0 -// -//***************************************************************************** -// Field: [31:0] ADDR_0_31 -// -// The first 32-bits of the 64-bit MAC 15.4 address -#define FCFG1_MAC_15_4_0_ADDR_0_31_W 32 -#define FCFG1_MAC_15_4_0_ADDR_0_31_M 0xFFFFFFFF -#define FCFG1_MAC_15_4_0_ADDR_0_31_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MAC_15_4_1 -// -//***************************************************************************** -// Field: [31:0] ADDR_32_63 -// -// The last 32-bits of the 64-bit MAC 15.4 address -#define FCFG1_MAC_15_4_1_ADDR_32_63_W 32 -#define FCFG1_MAC_15_4_1_ADDR_32_63_M 0xFFFFFFFF -#define FCFG1_MAC_15_4_1_ADDR_32_63_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FLASH_OTP_DATA4 -// -//***************************************************************************** -// Field: [31] STANDBY_MODE_SEL_INT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT 0x80000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_BITN 31 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_M 0x80000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_WRT_S 31 - -// Field: [30:29] STANDBY_PW_SEL_INT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_M 0x60000000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_WRT_S 29 - -// Field: [28] DIS_STANDBY_INT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT 0x10000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_BITN 28 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_M 0x10000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_WRT_S 28 - -// Field: [27] DIS_IDLE_INT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT 0x08000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_BITN 27 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_M 0x08000000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_WRT_S 27 - -// Field: [26:24] VIN_AT_X_INT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_M 0x07000000 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_WRT_S 24 - -// Field: [23] STANDBY_MODE_SEL_EXT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT 0x00800000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_BITN 23 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_M 0x00800000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_WRT_S 23 - -// Field: [22:21] STANDBY_PW_SEL_EXT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_M 0x00600000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_WRT_S 21 - -// Field: [20] DIS_STANDBY_EXT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT 0x00100000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_BITN 20 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_M 0x00100000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_WRT_S 20 - -// Field: [19] DIS_IDLE_EXT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT 0x00080000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_BITN 19 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_M 0x00080000 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_WRT_S 19 - -// Field: [18:16] VIN_AT_X_EXT_WRT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_M 0x00070000 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_WRT_S 16 - -// Field: [15] STANDBY_MODE_SEL_INT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD 0x00008000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_BITN 15 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_M 0x00008000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_INT_RD_S 15 - -// Field: [14:13] STANDBY_PW_SEL_INT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_M 0x00006000 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_INT_RD_S 13 - -// Field: [12] DIS_STANDBY_INT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD 0x00001000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_BITN 12 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_M 0x00001000 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_INT_RD_S 12 - -// Field: [11] DIS_IDLE_INT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD 0x00000800 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_BITN 11 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_M 0x00000800 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_INT_RD_S 11 - -// Field: [10:8] VIN_AT_X_INT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_M 0x00000700 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_INT_RD_S 8 - -// Field: [7] STANDBY_MODE_SEL_EXT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD 0x00000080 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_BITN 7 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_M 0x00000080 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_MODE_SEL_EXT_RD_S 7 - -// Field: [6:5] STANDBY_PW_SEL_EXT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_W 2 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_M 0x00000060 -#define FCFG1_FLASH_OTP_DATA4_STANDBY_PW_SEL_EXT_RD_S 5 - -// Field: [4] DIS_STANDBY_EXT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD 0x00000010 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_BITN 4 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_M 0x00000010 -#define FCFG1_FLASH_OTP_DATA4_DIS_STANDBY_EXT_RD_S 4 - -// Field: [3] DIS_IDLE_EXT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD 0x00000008 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_BITN 3 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_M 0x00000008 -#define FCFG1_FLASH_OTP_DATA4_DIS_IDLE_EXT_RD_S 3 - -// Field: [2:0] VIN_AT_X_EXT_RD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_W 3 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_M 0x00000007 -#define FCFG1_FLASH_OTP_DATA4_VIN_AT_X_EXT_RD_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MISC_TRIM -// -//***************************************************************************** -// Field: [16:12] TRIM_RECHARGE_COMP_OFFSET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_W 5 -#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_M 0x0001F000 -#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_OFFSET_S 12 - -// Field: [11:8] TRIM_RECHARGE_COMP_REFLEVEL -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_W 4 -#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_M 0x00000F00 -#define FCFG1_MISC_TRIM_TRIM_RECHARGE_COMP_REFLEVEL_S 8 - -// Field: [7:0] TEMPVSLOPE -// -// Signed byte value representing the TEMP slope with battery voltage, in -// degrees C / V, with four fractional bits. -#define FCFG1_MISC_TRIM_TEMPVSLOPE_W 8 -#define FCFG1_MISC_TRIM_TEMPVSLOPE_M 0x000000FF -#define FCFG1_MISC_TRIM_TEMPVSLOPE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_RCOSC_HF_TEMPCOMP -// -//***************************************************************************** -// Field: [31:24] FINE_RESISTOR -// -// Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_M 0xFF000000 -#define FCFG1_RCOSC_HF_TEMPCOMP_FINE_RESISTOR_S 24 - -// Field: [23:16] CTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_M 0x00FF0000 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIM_S 16 - -// Field: [15:8] CTRIMFRACT_QUAD -// -// Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_M 0x0000FF00 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_QUAD_S 8 - -// Field: [7:0] CTRIMFRACT_SLOPE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_W 8 -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_M 0x000000FF -#define FCFG1_RCOSC_HF_TEMPCOMP_CTRIMFRACT_SLOPE_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_ICEPICK_DEVICE_ID -// -//***************************************************************************** -// Field: [31:28] PG_REV -// -// Field used to distinguish revisions of the device. -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_W 4 -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_M 0xF0000000 -#define FCFG1_ICEPICK_DEVICE_ID_PG_REV_S 28 - -// Field: [27:12] WAFER_ID -// -// Field used to identify silicon die. -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_W 16 -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_M 0x0FFFF000 -#define FCFG1_ICEPICK_DEVICE_ID_WAFER_ID_S 12 - -// Field: [11:0] MANUFACTURER_ID -// -// Manufacturer code. -// -// 0x02F: Texas Instruments -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_W 12 -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_M 0x00000FFF -#define FCFG1_ICEPICK_DEVICE_ID_MANUFACTURER_ID_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FCFG1_REVISION -// -//***************************************************************************** -// Field: [31:0] REV -// -// The revision number of the FCFG1 layout. This value will be read by -// application SW in order to determine which FCFG1 parameters that have valid -// values. This revision number must be incremented by 1 before any devices are -// to be produced if the FCFG1 layout has changed since the previous production -// of devices. -// Value migth change without warning. -#define FCFG1_FCFG1_REVISION_REV_W 32 -#define FCFG1_FCFG1_REVISION_REV_M 0xFFFFFFFF -#define FCFG1_FCFG1_REVISION_REV_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MISC_OTP_DATA -// -//***************************************************************************** -// Field: [31:28] RCOSC_HF_ITUNE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_W 4 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_M 0xF0000000 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_ITUNE_S 28 - -// Field: [27:20] RCOSC_HF_CRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_W 8 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_M 0x0FF00000 -#define FCFG1_MISC_OTP_DATA_RCOSC_HF_CRIM_S 20 - -// Field: [19:15] PER_M -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_PER_M_W 5 -#define FCFG1_MISC_OTP_DATA_PER_M_M 0x000F8000 -#define FCFG1_MISC_OTP_DATA_PER_M_S 15 - -// Field: [14:12] PER_E -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_PER_E_W 3 -#define FCFG1_MISC_OTP_DATA_PER_E_M 0x00007000 -#define FCFG1_MISC_OTP_DATA_PER_E_S 12 - -//***************************************************************************** -// -// Register: FCFG1_O_IOCONF -// -//***************************************************************************** -// Field: [6:0] GPIO_CNT -// -// Number of available DIOs. -#define FCFG1_IOCONF_GPIO_CNT_W 7 -#define FCFG1_IOCONF_GPIO_CNT_M 0x0000007F -#define FCFG1_IOCONF_GPIO_CNT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_IF_ADC -// -//***************************************************************************** -// Field: [31:28] FF2ADJ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_M 0xF0000000 -#define FCFG1_CONFIG_IF_ADC_FF2ADJ_S 28 - -// Field: [27:24] FF3ADJ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_M 0x0F000000 -#define FCFG1_CONFIG_IF_ADC_FF3ADJ_S 24 - -// Field: [23:20] INT3ADJ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_M 0x00F00000 -#define FCFG1_CONFIG_IF_ADC_INT3ADJ_S 20 - -// Field: [19:16] FF1ADJ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_M 0x000F0000 -#define FCFG1_CONFIG_IF_ADC_FF1ADJ_S 16 - -// Field: [15:14] AAFCAP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_AAFCAP_W 2 -#define FCFG1_CONFIG_IF_ADC_AAFCAP_M 0x0000C000 -#define FCFG1_CONFIG_IF_ADC_AAFCAP_S 14 - -// Field: [13:10] INT2ADJ -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_W 4 -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_M 0x00003C00 -#define FCFG1_CONFIG_IF_ADC_INT2ADJ_S 10 - -// Field: [9:5] IFDIGLDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_W 5 -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_M 0x000003E0 -#define FCFG1_CONFIG_IF_ADC_IFDIGLDO_TRIM_OUTPUT_S 5 - -// Field: [4:0] IFANALDO_TRIM_OUTPUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_W 5 -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_M 0x0000001F -#define FCFG1_CONFIG_IF_ADC_IFANALDO_TRIM_OUTPUT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_CONFIG_OSC_TOP -// -//***************************************************************************** -// Field: [29:26] XOSC_HF_ROW_Q12 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_W 4 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_M 0x3C000000 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_ROW_Q12_S 26 - -// Field: [25:10] XOSC_HF_COLUMN_Q12 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_W 16 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_M 0x03FFFC00 -#define FCFG1_CONFIG_OSC_TOP_XOSC_HF_COLUMN_Q12_S 10 - -// Field: [9:2] RCOSCLF_CTUNE_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_W 8 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_M 0x000003FC -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_CTUNE_TRIM_S 2 - -// Field: [1:0] RCOSCLF_RTUNE_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_W 2 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_M 0x00000003 -#define FCFG1_CONFIG_OSC_TOP_RCOSCLF_RTUNE_TRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SOC_ADC_ABS_GAIN -// -//***************************************************************************** -// Field: [15:0] SOC_ADC_ABS_GAIN_TEMP1 -// -// SOC_ADC gain in absolute reference mode at temperature 1 (30C). Calculated -// in production test.. -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_W 16 -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_M 0x0000FFFF -#define FCFG1_SOC_ADC_ABS_GAIN_SOC_ADC_ABS_GAIN_TEMP1_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SOC_ADC_REL_GAIN -// -//***************************************************************************** -// Field: [15:0] SOC_ADC_REL_GAIN_TEMP1 -// -// SOC_ADC gain in relative reference mode at temperature 1 (30C). Calculated -// in production test.. -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_W 16 -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_M 0x0000FFFF -#define FCFG1_SOC_ADC_REL_GAIN_SOC_ADC_REL_GAIN_TEMP1_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SOC_ADC_OFFSET_INT -// -//***************************************************************************** -// Field: [23:16] SOC_ADC_REL_OFFSET_TEMP1 -// -// SOC_ADC offset in relative reference mode at temperature 1 (30C). Signed -// 8-bit number. Calculated in production test.. -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_W 8 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_M 0x00FF0000 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_REL_OFFSET_TEMP1_S 16 - -// Field: [7:0] SOC_ADC_ABS_OFFSET_TEMP1 -// -// SOC_ADC offset in absolute reference mode at temperature 1 (30C). Signed -// 8-bit number. Calculated in production test.. -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_W 8 -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_M 0x000000FF -#define FCFG1_SOC_ADC_OFFSET_INT_SOC_ADC_ABS_OFFSET_TEMP1_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SOC_ADC_REF_TRIM_AND_OFFSET_EXT -// -//***************************************************************************** -// Field: [5:0] SOC_ADC_REF_VOLTAGE_TRIM_TEMP1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_W \ - 6 -#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_M \ - 0x0000003F -#define FCFG1_SOC_ADC_REF_TRIM_AND_OFFSET_EXT_SOC_ADC_REF_VOLTAGE_TRIM_TEMP1_S \ - 0 - -//***************************************************************************** -// -// Register: FCFG1_O_AMPCOMP_TH1 -// -//***************************************************************************** -// Field: [23:18] HPMRAMP3_LTH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_M 0x00FC0000 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_LTH_S 18 - -// Field: [15:10] HPMRAMP3_HTH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_M 0x0000FC00 -#define FCFG1_AMPCOMP_TH1_HPMRAMP3_HTH_S 10 - -// Field: [9:6] IBIASCAP_LPTOHP_OL_CNT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_W 4 -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_M 0x000003C0 -#define FCFG1_AMPCOMP_TH1_IBIASCAP_LPTOHP_OL_CNT_S 6 - -// Field: [5:0] HPMRAMP1_TH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_W 6 -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_M 0x0000003F -#define FCFG1_AMPCOMP_TH1_HPMRAMP1_TH_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_AMPCOMP_TH2 -// -//***************************************************************************** -// Field: [31:26] LPMUPDATE_LTH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_W 6 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_M 0xFC000000 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_LTH_S 26 - -// Field: [23:18] LPMUPDATE_HTM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_W 6 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_M 0x00FC0000 -#define FCFG1_AMPCOMP_TH2_LPMUPDATE_HTM_S 18 - -// Field: [15:10] ADC_COMP_AMPTH_LPM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_W 6 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_M 0x0000FC00 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_LPM_S 10 - -// Field: [7:2] ADC_COMP_AMPTH_HPM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_W 6 -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_M 0x000000FC -#define FCFG1_AMPCOMP_TH2_ADC_COMP_AMPTH_HPM_S 2 - -//***************************************************************************** -// -// Register: FCFG1_O_AMPCOMP_CTRL1 -// -//***************************************************************************** -// Field: [30] AMPCOMP_REQ_MODE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE 0x40000000 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_BITN 30 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_M 0x40000000 -#define FCFG1_AMPCOMP_CTRL1_AMPCOMP_REQ_MODE_S 30 - -// Field: [23:20] IBIAS_OFFSET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_M 0x00F00000 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_OFFSET_S 20 - -// Field: [19:16] IBIAS_INIT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_M 0x000F0000 -#define FCFG1_AMPCOMP_CTRL1_IBIAS_INIT_S 16 - -// Field: [15:8] LPM_IBIAS_WAIT_CNT_FINAL -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_W 8 -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_M 0x0000FF00 -#define FCFG1_AMPCOMP_CTRL1_LPM_IBIAS_WAIT_CNT_FINAL_S 8 - -// Field: [7:4] CAP_STEP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_W 4 -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_M 0x000000F0 -#define FCFG1_AMPCOMP_CTRL1_CAP_STEP_S 4 - -// Field: [3:0] IBIASCAP_HPTOLP_OL_CNT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_W 4 -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_M 0x0000000F -#define FCFG1_AMPCOMP_CTRL1_IBIASCAP_HPTOLP_OL_CNT_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_ANABYPASS_VALUE2 -// -//***************************************************************************** -// Field: [13:0] XOSC_HF_IBIASTHERM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_W 14 -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_M 0x00003FFF -#define FCFG1_ANABYPASS_VALUE2_XOSC_HF_IBIASTHERM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_VOLT_TRIM -// -//***************************************************************************** -// Field: [28:24] VDDR_TRIM_HH -// -// Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_M 0x1F000000 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_HH_S 24 - -// Field: [20:16] VDDR_TRIM_H -// -// Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_M 0x001F0000 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_H_S 16 - -// Field: [12:8] VDDR_TRIM_SLEEP_H -// -// Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_W 5 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_M 0x00001F00 -#define FCFG1_VOLT_TRIM_VDDR_TRIM_SLEEP_H_S 8 - -// Field: [4:0] TRIMBOD_H -// -// Internal. Only to be used through TI provided API. -#define FCFG1_VOLT_TRIM_TRIMBOD_H_W 5 -#define FCFG1_VOLT_TRIM_TRIMBOD_H_M 0x0000001F -#define FCFG1_VOLT_TRIM_TRIMBOD_H_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_OSC_CONF -// -//***************************************************************************** -// Field: [29] ADC_SH_VBUF_EN -// -// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_VBUF_EN. -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN 0x20000000 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_BITN 29 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_M 0x20000000 -#define FCFG1_OSC_CONF_ADC_SH_VBUF_EN_S 29 - -// Field: [28] ADC_SH_MODE_EN -// -// Trim value for DDI_0_OSC:ADCDOUBLERNANOAMPCTL.ADC_SH_MODE_EN. -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN 0x10000000 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_BITN 28 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_M 0x10000000 -#define FCFG1_OSC_CONF_ADC_SH_MODE_EN_S 28 - -// Field: [27] ATESTLF_RCOSCLF_IBIAS_TRIM -// -// Trim value for DDI_0_OSC:ATESTCTL.ATESTLF_RCOSCLF_IBIAS_TRIM. -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM 0x08000000 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_BITN 27 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_M 0x08000000 -#define FCFG1_OSC_CONF_ATESTLF_RCOSCLF_IBIAS_TRIM_S 27 - -// Field: [26:25] XOSCLF_REGULATOR_TRIM -// -// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_REGULATOR_TRIM. -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_W 2 -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_M 0x06000000 -#define FCFG1_OSC_CONF_XOSCLF_REGULATOR_TRIM_S 25 - -// Field: [24:21] XOSCLF_CMIRRWR_RATIO -// -// Trim value for DDI_0_OSC:LFOSCCTL.XOSCLF_CMIRRWR_RATIO. -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_W 4 -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_M 0x01E00000 -#define FCFG1_OSC_CONF_XOSCLF_CMIRRWR_RATIO_S 21 - -// Field: [20:19] XOSC_HF_FAST_START -// -// Trim value for DDI_0_OSC:CTL1.XOSC_HF_FAST_START. -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_W 2 -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_M 0x00180000 -#define FCFG1_OSC_CONF_XOSC_HF_FAST_START_S 19 - -// Field: [18] XOSC_OPTION -// -// 0: XOSC_HF unavailable (may not be bonded out) -// 1: XOSC_HF available (default) -#define FCFG1_OSC_CONF_XOSC_OPTION 0x00040000 -#define FCFG1_OSC_CONF_XOSC_OPTION_BITN 18 -#define FCFG1_OSC_CONF_XOSC_OPTION_M 0x00040000 -#define FCFG1_OSC_CONF_XOSC_OPTION_S 18 - -// Field: [17] HPOSC_OPTION -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_OPTION 0x00020000 -#define FCFG1_OSC_CONF_HPOSC_OPTION_BITN 17 -#define FCFG1_OSC_CONF_HPOSC_OPTION_M 0x00020000 -#define FCFG1_OSC_CONF_HPOSC_OPTION_S 17 - -// Field: [16] HPOSC_BIAS_HOLD_MODE_EN -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN 0x00010000 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_BITN 16 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_M 0x00010000 -#define FCFG1_OSC_CONF_HPOSC_BIAS_HOLD_MODE_EN_S 16 - -// Field: [15:12] HPOSC_CURRMIRR_RATIO -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_W 4 -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_M 0x0000F000 -#define FCFG1_OSC_CONF_HPOSC_CURRMIRR_RATIO_S 12 - -// Field: [11:8] HPOSC_BIAS_RES_SET -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_W 4 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_M 0x00000F00 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RES_SET_S 8 - -// Field: [7] HPOSC_FILTER_EN -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN 0x00000080 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_BITN 7 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_M 0x00000080 -#define FCFG1_OSC_CONF_HPOSC_FILTER_EN_S 7 - -// Field: [6:5] HPOSC_BIAS_RECHARGE_DELAY -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_W 2 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_M 0x00000060 -#define FCFG1_OSC_CONF_HPOSC_BIAS_RECHARGE_DELAY_S 5 - -// Field: [2:1] HPOSC_SERIES_CAP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_W 2 -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_M 0x00000006 -#define FCFG1_OSC_CONF_HPOSC_SERIES_CAP_S 1 - -// Field: [0] HPOSC_DIV3_BYPASS -// -// Internal. Only to be used through TI provided API. -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS 0x00000001 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_BITN 0 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_M 0x00000001 -#define FCFG1_OSC_CONF_HPOSC_DIV3_BYPASS_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_FREQ_OFFSET -// -//***************************************************************************** -// Field: [31:16] HPOSC_COMP_P0 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_W 16 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_M 0xFFFF0000 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P0_S 16 - -// Field: [15:8] HPOSC_COMP_P1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_W 8 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_M 0x0000FF00 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P1_S 8 - -// Field: [7:0] HPOSC_COMP_P2 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_W 8 -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_M 0x000000FF -#define FCFG1_FREQ_OFFSET_HPOSC_COMP_P2_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_MISC_OTP_DATA_1 -// -//***************************************************************************** -// Field: [28:27] PEAK_DET_ITRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_W 2 -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_M 0x18000000 -#define FCFG1_MISC_OTP_DATA_1_PEAK_DET_ITRIM_S 27 - -// Field: [26:24] HP_BUF_ITRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_W 3 -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_M 0x07000000 -#define FCFG1_MISC_OTP_DATA_1_HP_BUF_ITRIM_S 24 - -// Field: [23:22] LP_BUF_ITRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_W 2 -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_M 0x00C00000 -#define FCFG1_MISC_OTP_DATA_1_LP_BUF_ITRIM_S 22 - -// Field: [21:20] DBLR_LOOP_FILTER_RESET_VOLTAGE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_W 2 -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_M 0x00300000 -#define FCFG1_MISC_OTP_DATA_1_DBLR_LOOP_FILTER_RESET_VOLTAGE_S 20 - -// Field: [19:10] HPM_IBIAS_WAIT_CNT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_W 10 -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_M 0x000FFC00 -#define FCFG1_MISC_OTP_DATA_1_HPM_IBIAS_WAIT_CNT_S 10 - -// Field: [9:4] LPM_IBIAS_WAIT_CNT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_W 6 -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_M 0x000003F0 -#define FCFG1_MISC_OTP_DATA_1_LPM_IBIAS_WAIT_CNT_S 4 - -// Field: [3:0] IDAC_STEP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_W 4 -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_M 0x0000000F -#define FCFG1_MISC_OTP_DATA_1_IDAC_STEP_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SHDW_DIE_ID_0 -// -//***************************************************************************** -// Field: [31:0] ID_31_0 -// -// Shadow of DIE_ID_0 register in eFuse row number 5 -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_W 32 -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_0_ID_31_0_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SHDW_DIE_ID_1 -// -//***************************************************************************** -// Field: [31:0] ID_63_32 -// -// Shadow of DIE_ID_1 register in eFuse row number 6 -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_W 32 -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_1_ID_63_32_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SHDW_DIE_ID_2 -// -//***************************************************************************** -// Field: [31:0] ID_95_64 -// -// Shadow of DIE_ID_2 register in eFuse row number 7 -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_W 32 -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_2_ID_95_64_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SHDW_DIE_ID_3 -// -//***************************************************************************** -// Field: [31:0] ID_127_96 -// -// Shadow of DIE_ID_3 register in eFuse row number 8 -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_W 32 -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_M 0xFFFFFFFF -#define FCFG1_SHDW_DIE_ID_3_ID_127_96_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SHDW_OSC_BIAS_LDO_TRIM -// -//***************************************************************************** -// Field: [26:23] TRIMMAG -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_M 0x07800000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMMAG_S 23 - -// Field: [22:18] TRIMIREF -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_W 5 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_M 0x007C0000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_TRIMIREF_S 18 - -// Field: [17:16] ITRIM_DIG_LDO -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_W 2 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_M 0x00030000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_ITRIM_DIG_LDO_S 16 - -// Field: [15:12] VTRIM_DIG -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_M 0x0000F000 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_DIG_S 12 - -// Field: [11:8] VTRIM_COARSE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_W 4 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_M 0x00000F00 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_VTRIM_COARSE_S 8 - -// Field: [7:0] RCOSCHF_CTRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_W 8 -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_M 0x000000FF -#define FCFG1_SHDW_OSC_BIAS_LDO_TRIM_RCOSCHF_CTRIM_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_SHDW_ANA_TRIM -// -//***************************************************************************** -// Field: [30] ALT_VDDR_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM 0x40000000 -#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_BITN 30 -#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_M 0x40000000 -#define FCFG1_SHDW_ANA_TRIM_ALT_VDDR_TRIM_S 30 - -// Field: [29] DET_LOGIC_DIS -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS 0x20000000 -#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_BITN 29 -#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_M 0x20000000 -#define FCFG1_SHDW_ANA_TRIM_DET_LOGIC_DIS_S 29 - -// Field: [28:27] BOD_BANDGAP_TRIM_CNF_EXT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_W 2 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_M 0x18000000 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_EXT_S 27 - -// Field: [26:25] BOD_BANDGAP_TRIM_CNF -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_W 2 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_M 0x06000000 -#define FCFG1_SHDW_ANA_TRIM_BOD_BANDGAP_TRIM_CNF_S 25 - -// Field: [24] VDDR_ENABLE_PG1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1 0x01000000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_BITN 24 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_M 0x01000000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_ENABLE_PG1_S 24 - -// Field: [23] VDDR_OK_HYS -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS 0x00800000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_BITN 23 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_M 0x00800000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_OK_HYS_S 23 - -// Field: [22:21] IPTAT_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_W 2 -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_M 0x00600000 -#define FCFG1_SHDW_ANA_TRIM_IPTAT_TRIM_S 21 - -// Field: [20:16] VDDR_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_W 5 -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_M 0x001F0000 -#define FCFG1_SHDW_ANA_TRIM_VDDR_TRIM_S 16 - -// Field: [15:11] TRIMBOD_INTMODE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_W 5 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_M 0x0000F800 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_INTMODE_S 11 - -// Field: [10:6] TRIMBOD_EXTMODE -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_W 5 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_M 0x000007C0 -#define FCFG1_SHDW_ANA_TRIM_TRIMBOD_EXTMODE_S 6 - -// Field: [5:0] TRIMTEMP -// -// Internal. Only to be used through TI provided API. -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_W 6 -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_M 0x0000003F -#define FCFG1_SHDW_ANA_TRIM_TRIMTEMP_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_DAC_BIAS_CNF -// -//***************************************************************************** -// Field: [17:12] LPM_TRIM_IOUT -// -// Internal. Only to be used through TI provided API. -#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_W 6 -#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_M 0x0003F000 -#define FCFG1_DAC_BIAS_CNF_LPM_TRIM_IOUT_S 12 - -// Field: [11:9] LPM_BIAS_WIDTH_TRIM -// -// Internal. Only to be used through TI provided API. -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_W 3 -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_M 0x00000E00 -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_WIDTH_TRIM_S 9 - -// Field: [8] LPM_BIAS_BACKUP_EN -// -// Internal. Only to be used through TI provided API. -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN 0x00000100 -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_BITN 8 -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_M 0x00000100 -#define FCFG1_DAC_BIAS_CNF_LPM_BIAS_BACKUP_EN_S 8 - -//***************************************************************************** -// -// Register: FCFG1_O_TFW_PROBE -// -//***************************************************************************** -// Field: [31:0] REV -// -// Internal. Only to be used through TI provided API. -#define FCFG1_TFW_PROBE_REV_W 32 -#define FCFG1_TFW_PROBE_REV_M 0xFFFFFFFF -#define FCFG1_TFW_PROBE_REV_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_TFW_FT -// -//***************************************************************************** -// Field: [31:0] REV -// -// Internal. Only to be used through TI provided API. -#define FCFG1_TFW_FT_REV_W 32 -#define FCFG1_TFW_FT_REV_M 0xFFFFFFFF -#define FCFG1_TFW_FT_REV_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_DAC_CAL0 -// -//***************************************************************************** -// Field: [31:16] SOC_DAC_VOUT_CAL_DECOUPLE_C2 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_W 16 -#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_M 0xFFFF0000 -#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C2_S 16 - -// Field: [15:0] SOC_DAC_VOUT_CAL_DECOUPLE_C1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_W 16 -#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_M 0x0000FFFF -#define FCFG1_DAC_CAL0_SOC_DAC_VOUT_CAL_DECOUPLE_C1_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_DAC_CAL1 -// -//***************************************************************************** -// Field: [31:16] SOC_DAC_VOUT_CAL_PRECH_C2 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_W 16 -#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_M 0xFFFF0000 -#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C2_S 16 - -// Field: [15:0] SOC_DAC_VOUT_CAL_PRECH_C1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_W 16 -#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_M 0x0000FFFF -#define FCFG1_DAC_CAL1_SOC_DAC_VOUT_CAL_PRECH_C1_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_DAC_CAL2 -// -//***************************************************************************** -// Field: [31:16] SOC_DAC_VOUT_CAL_ADCREF_C2 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_W 16 -#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_M 0xFFFF0000 -#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C2_S 16 - -// Field: [15:0] SOC_DAC_VOUT_CAL_ADCREF_C1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_W 16 -#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_M 0x0000FFFF -#define FCFG1_DAC_CAL2_SOC_DAC_VOUT_CAL_ADCREF_C1_S 0 - -//***************************************************************************** -// -// Register: FCFG1_O_DAC_CAL3 -// -//***************************************************************************** -// Field: [31:16] SOC_DAC_VOUT_CAL_VDDS_C2 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_W 16 -#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_M 0xFFFF0000 -#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C2_S 16 - -// Field: [15:0] SOC_DAC_VOUT_CAL_VDDS_C1 -// -// Internal. Only to be used through TI provided API. -#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_W 16 -#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_M 0x0000FFFF -#define FCFG1_DAC_CAL3_SOC_DAC_VOUT_CAL_VDDS_C1_S 0 - - -#endif // __FCFG1__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h deleted file mode 100644 index d7e03e79544..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_flash.h +++ /dev/null @@ -1,3498 +0,0 @@ -/****************************************************************************** -* Filename: hw_flash_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_FLASH_H__ -#define __HW_FLASH_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// FLASH component -// -//***************************************************************************** -// FMC and Efuse Status -#define FLASH_O_STAT 0x0000001C - -// Internal -#define FLASH_O_CFG 0x00000024 - -// Internal -#define FLASH_O_SYSCODE_START 0x00000028 - -// Internal -#define FLASH_O_FLASH_SIZE 0x0000002C - -// Internal -#define FLASH_O_FWLOCK 0x0000003C - -// Internal -#define FLASH_O_FWFLAG 0x00000040 - -// Internal -#define FLASH_O_EFUSE 0x00001000 - -// Internal -#define FLASH_O_EFUSEADDR 0x00001004 - -// Internal -#define FLASH_O_DATAUPPER 0x00001008 - -// Internal -#define FLASH_O_DATALOWER 0x0000100C - -// Internal -#define FLASH_O_EFUSECFG 0x00001010 - -// Internal -#define FLASH_O_EFUSESTAT 0x00001014 - -// Internal -#define FLASH_O_ACC 0x00001018 - -// Internal -#define FLASH_O_BOUNDARY 0x0000101C - -// Internal -#define FLASH_O_EFUSEFLAG 0x00001020 - -// Internal -#define FLASH_O_EFUSEKEY 0x00001024 - -// Internal -#define FLASH_O_EFUSERELEASE 0x00001028 - -// Internal -#define FLASH_O_EFUSEPINS 0x0000102C - -// Internal -#define FLASH_O_EFUSECRA 0x00001030 - -// Internal -#define FLASH_O_EFUSEREAD 0x00001034 - -// Internal -#define FLASH_O_EFUSEPROGRAM 0x00001038 - -// Internal -#define FLASH_O_EFUSEERROR 0x0000103C - -// Internal -#define FLASH_O_SINGLEBIT 0x00001040 - -// Internal -#define FLASH_O_TWOBIT 0x00001044 - -// Internal -#define FLASH_O_SELFTESTCYC 0x00001048 - -// Internal -#define FLASH_O_SELFTESTSIGN 0x0000104C - -// Internal -#define FLASH_O_FRDCTL 0x00002000 - -// Internal -#define FLASH_O_FSPRD 0x00002004 - -// Internal -#define FLASH_O_FEDACCTL1 0x00002008 - -// Internal -#define FLASH_O_FEDACSTAT 0x0000201C - -// Internal -#define FLASH_O_FBPROT 0x00002030 - -// Internal -#define FLASH_O_FBSE 0x00002034 - -// Internal -#define FLASH_O_FBBUSY 0x00002038 - -// Internal -#define FLASH_O_FBAC 0x0000203C - -// Internal -#define FLASH_O_FBFALLBACK 0x00002040 - -// Internal -#define FLASH_O_FBPRDY 0x00002044 - -// Internal -#define FLASH_O_FPAC1 0x00002048 - -// Internal -#define FLASH_O_FPAC2 0x0000204C - -// Internal -#define FLASH_O_FMAC 0x00002050 - -// Internal -#define FLASH_O_FMSTAT 0x00002054 - -// Internal -#define FLASH_O_FLOCK 0x00002064 - -// Internal -#define FLASH_O_FVREADCT 0x00002080 - -// Internal -#define FLASH_O_FVHVCT1 0x00002084 - -// Internal -#define FLASH_O_FVHVCT2 0x00002088 - -// Internal -#define FLASH_O_FVHVCT3 0x0000208C - -// Internal -#define FLASH_O_FVNVCT 0x00002090 - -// Internal -#define FLASH_O_FVSLP 0x00002094 - -// Internal -#define FLASH_O_FVWLCT 0x00002098 - -// Internal -#define FLASH_O_FEFUSECTL 0x0000209C - -// Internal -#define FLASH_O_FEFUSESTAT 0x000020A0 - -// Internal -#define FLASH_O_FEFUSEDATA 0x000020A4 - -// Internal -#define FLASH_O_FSEQPMP 0x000020A8 - -// Internal -#define FLASH_O_FBSTROBES 0x00002100 - -// Internal -#define FLASH_O_FPSTROBES 0x00002104 - -// Internal -#define FLASH_O_FBMODE 0x00002108 - -// Internal -#define FLASH_O_FTCR 0x0000210C - -// Internal -#define FLASH_O_FADDR 0x00002110 - -// Internal -#define FLASH_O_FTCTL 0x0000211C - -// Internal -#define FLASH_O_FWPWRITE0 0x00002120 - -// Internal -#define FLASH_O_FWPWRITE1 0x00002124 - -// Internal -#define FLASH_O_FWPWRITE2 0x00002128 - -// Internal -#define FLASH_O_FWPWRITE3 0x0000212C - -// Internal -#define FLASH_O_FWPWRITE4 0x00002130 - -// Internal -#define FLASH_O_FWPWRITE5 0x00002134 - -// Internal -#define FLASH_O_FWPWRITE6 0x00002138 - -// Internal -#define FLASH_O_FWPWRITE7 0x0000213C - -// Internal -#define FLASH_O_FWPWRITE_ECC 0x00002140 - -// Internal -#define FLASH_O_FSWSTAT 0x00002144 - -// Internal -#define FLASH_O_FSM_GLBCTL 0x00002200 - -// Internal -#define FLASH_O_FSM_STATE 0x00002204 - -// Internal -#define FLASH_O_FSM_STAT 0x00002208 - -// Internal -#define FLASH_O_FSM_CMD 0x0000220C - -// Internal -#define FLASH_O_FSM_PE_OSU 0x00002210 - -// Internal -#define FLASH_O_FSM_VSTAT 0x00002214 - -// Internal -#define FLASH_O_FSM_PE_VSU 0x00002218 - -// Internal -#define FLASH_O_FSM_CMP_VSU 0x0000221C - -// Internal -#define FLASH_O_FSM_EX_VAL 0x00002220 - -// Internal -#define FLASH_O_FSM_RD_H 0x00002224 - -// Internal -#define FLASH_O_FSM_P_OH 0x00002228 - -// Internal -#define FLASH_O_FSM_ERA_OH 0x0000222C - -// Internal -#define FLASH_O_FSM_SAV_PPUL 0x00002230 - -// Internal -#define FLASH_O_FSM_PE_VH 0x00002234 - -// Internal -#define FLASH_O_FSM_PRG_PW 0x00002240 - -// Internal -#define FLASH_O_FSM_ERA_PW 0x00002244 - -// Internal -#define FLASH_O_FSM_SAV_ERA_PUL 0x00002254 - -// Internal -#define FLASH_O_FSM_TIMER 0x00002258 - -// Internal -#define FLASH_O_FSM_MODE 0x0000225C - -// Internal -#define FLASH_O_FSM_PGM 0x00002260 - -// Internal -#define FLASH_O_FSM_ERA 0x00002264 - -// Internal -#define FLASH_O_FSM_PRG_PUL 0x00002268 - -// Internal -#define FLASH_O_FSM_ERA_PUL 0x0000226C - -// Internal -#define FLASH_O_FSM_STEP_SIZE 0x00002270 - -// Internal -#define FLASH_O_FSM_PUL_CNTR 0x00002274 - -// Internal -#define FLASH_O_FSM_EC_STEP_HEIGHT 0x00002278 - -// Internal -#define FLASH_O_FSM_ST_MACHINE 0x0000227C - -// Internal -#define FLASH_O_FSM_FLES 0x00002280 - -// Internal -#define FLASH_O_FSM_WR_ENA 0x00002288 - -// Internal -#define FLASH_O_FSM_ACC_PP 0x0000228C - -// Internal -#define FLASH_O_FSM_ACC_EP 0x00002290 - -// Internal -#define FLASH_O_FSM_ADDR 0x000022A0 - -// Internal -#define FLASH_O_FSM_SECTOR 0x000022A4 - -// Internal -#define FLASH_O_FMC_REV_ID 0x000022A8 - -// Internal -#define FLASH_O_FSM_ERR_ADDR 0x000022AC - -// Internal -#define FLASH_O_FSM_PGM_MAXPUL 0x000022B0 - -// Internal -#define FLASH_O_FSM_EXECUTE 0x000022B4 - -// Internal -#define FLASH_O_FSM_SECTOR1 0x000022C0 - -// Internal -#define FLASH_O_FSM_SECTOR2 0x000022C4 - -// Internal -#define FLASH_O_FSM_BSLE0 0x000022E0 - -// Internal -#define FLASH_O_FSM_BSLE1 0x000022E4 - -// Internal -#define FLASH_O_FSM_BSLP0 0x000022F0 - -// Internal -#define FLASH_O_FSM_BSLP1 0x000022F4 - -// FMC FSM Enable 128-bit Wide Programming -#define FLASH_O_FSM_PGM128 0x000022F8 - -// Internal -#define FLASH_O_FCFG_BANK 0x00002400 - -// Internal -#define FLASH_O_FCFG_WRAPPER 0x00002404 - -// Internal -#define FLASH_O_FCFG_BNK_TYPE 0x00002408 - -// Internal -#define FLASH_O_FCFG_B0_START 0x00002410 - -// Internal -#define FLASH_O_FCFG_B1_START 0x00002414 - -// Internal -#define FLASH_O_FCFG_B2_START 0x00002418 - -// Internal -#define FLASH_O_FCFG_B3_START 0x0000241C - -// Internal -#define FLASH_O_FCFG_B4_START 0x00002420 - -// Internal -#define FLASH_O_FCFG_B5_START 0x00002424 - -// Internal -#define FLASH_O_FCFG_B6_START 0x00002428 - -// Internal -#define FLASH_O_FCFG_B7_START 0x0000242C - -// Internal -#define FLASH_O_FCFG_B0_SSIZE0 0x00002430 - -//***************************************************************************** -// -// Register: FLASH_O_STAT -// -//***************************************************************************** -// Field: [15] EFUSE_BLANK -// -// Efuse scanning detected if fuse ROM is blank: -// 0 : Not blank -// 1 : Blank -#define FLASH_STAT_EFUSE_BLANK 0x00008000 -#define FLASH_STAT_EFUSE_BLANK_BITN 15 -#define FLASH_STAT_EFUSE_BLANK_M 0x00008000 -#define FLASH_STAT_EFUSE_BLANK_S 15 - -// Field: [14] EFUSE_TIMEOUT -// -// Efuse scanning resulted in timeout error. -// 0 : No Timeout error -// 1 : Timeout Error -#define FLASH_STAT_EFUSE_TIMEOUT 0x00004000 -#define FLASH_STAT_EFUSE_TIMEOUT_BITN 14 -#define FLASH_STAT_EFUSE_TIMEOUT_M 0x00004000 -#define FLASH_STAT_EFUSE_TIMEOUT_S 14 - -// Field: [13] SPRS_BYTE_NOT_OK -// -// Efuse scanning resulted in scan chain Sparse byte error. -// 0 : No Sparse error -// 1 : Sparse Error -#define FLASH_STAT_SPRS_BYTE_NOT_OK 0x00002000 -#define FLASH_STAT_SPRS_BYTE_NOT_OK_BITN 13 -#define FLASH_STAT_SPRS_BYTE_NOT_OK_M 0x00002000 -#define FLASH_STAT_SPRS_BYTE_NOT_OK_S 13 - -// Field: [12:8] EFUSE_ERRCODE -// -// Same as EFUSEERROR.CODE -#define FLASH_STAT_EFUSE_ERRCODE_W 5 -#define FLASH_STAT_EFUSE_ERRCODE_M 0x00001F00 -#define FLASH_STAT_EFUSE_ERRCODE_S 8 - -// Field: [2] SAMHOLD_DIS -// -// Status indicator of flash sample and hold sequencing logic. This bit will go -// to 1 some delay after CFG.DIS_IDLE is set to 1. -// 0: Not disabled -// 1: Sample and hold disabled and stable -#define FLASH_STAT_SAMHOLD_DIS 0x00000004 -#define FLASH_STAT_SAMHOLD_DIS_BITN 2 -#define FLASH_STAT_SAMHOLD_DIS_M 0x00000004 -#define FLASH_STAT_SAMHOLD_DIS_S 2 - -// Field: [1] BUSY -// -// Fast version of the FMC FMSTAT.BUSY bit. -// This flag is valid immediately after the operation setting it (FMSTAT.BUSY -// is delayed some cycles) -// 0 : Not busy -// 1 : Busy -#define FLASH_STAT_BUSY 0x00000002 -#define FLASH_STAT_BUSY_BITN 1 -#define FLASH_STAT_BUSY_M 0x00000002 -#define FLASH_STAT_BUSY_S 1 - -// Field: [0] POWER_MODE -// -// Power state of the flash sub-system. -// 0 : Active -// 1 : Low power -#define FLASH_STAT_POWER_MODE 0x00000001 -#define FLASH_STAT_POWER_MODE_BITN 0 -#define FLASH_STAT_POWER_MODE_M 0x00000001 -#define FLASH_STAT_POWER_MODE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_CFG -// -//***************************************************************************** -// Field: [8] STANDBY_MODE_SEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_STANDBY_MODE_SEL 0x00000100 -#define FLASH_CFG_STANDBY_MODE_SEL_BITN 8 -#define FLASH_CFG_STANDBY_MODE_SEL_M 0x00000100 -#define FLASH_CFG_STANDBY_MODE_SEL_S 8 - -// Field: [7:6] STANDBY_PW_SEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_STANDBY_PW_SEL_W 2 -#define FLASH_CFG_STANDBY_PW_SEL_M 0x000000C0 -#define FLASH_CFG_STANDBY_PW_SEL_S 6 - -// Field: [5] DIS_EFUSECLK -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_EFUSECLK 0x00000020 -#define FLASH_CFG_DIS_EFUSECLK_BITN 5 -#define FLASH_CFG_DIS_EFUSECLK_M 0x00000020 -#define FLASH_CFG_DIS_EFUSECLK_S 5 - -// Field: [4] DIS_READACCESS -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_READACCESS 0x00000010 -#define FLASH_CFG_DIS_READACCESS_BITN 4 -#define FLASH_CFG_DIS_READACCESS_M 0x00000010 -#define FLASH_CFG_DIS_READACCESS_S 4 - -// Field: [3] ENABLE_SWINTF -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_ENABLE_SWINTF 0x00000008 -#define FLASH_CFG_ENABLE_SWINTF_BITN 3 -#define FLASH_CFG_ENABLE_SWINTF_M 0x00000008 -#define FLASH_CFG_ENABLE_SWINTF_S 3 - -// Field: [1] DIS_STANDBY -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_STANDBY 0x00000002 -#define FLASH_CFG_DIS_STANDBY_BITN 1 -#define FLASH_CFG_DIS_STANDBY_M 0x00000002 -#define FLASH_CFG_DIS_STANDBY_S 1 - -// Field: [0] DIS_IDLE -// -// Internal. Only to be used through TI provided API. -#define FLASH_CFG_DIS_IDLE 0x00000001 -#define FLASH_CFG_DIS_IDLE_BITN 0 -#define FLASH_CFG_DIS_IDLE_M 0x00000001 -#define FLASH_CFG_DIS_IDLE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_SYSCODE_START -// -//***************************************************************************** -// Field: [5:0] SYSCODE_START -// -// Internal. Only to be used through TI provided API. -#define FLASH_SYSCODE_START_SYSCODE_START_W 6 -#define FLASH_SYSCODE_START_SYSCODE_START_M 0x0000003F -#define FLASH_SYSCODE_START_SYSCODE_START_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FLASH_SIZE -// -//***************************************************************************** -// Field: [7:0] SECTORS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FLASH_SIZE_SECTORS_W 8 -#define FLASH_FLASH_SIZE_SECTORS_M 0x000000FF -#define FLASH_FLASH_SIZE_SECTORS_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWLOCK -// -//***************************************************************************** -// Field: [2:0] FWLOCK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWLOCK_FWLOCK_W 3 -#define FLASH_FWLOCK_FWLOCK_M 0x00000007 -#define FLASH_FWLOCK_FWLOCK_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWFLAG -// -//***************************************************************************** -// Field: [2:0] FWFLAG -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWFLAG_FWFLAG_W 3 -#define FLASH_FWFLAG_FWFLAG_M 0x00000007 -#define FLASH_FWFLAG_FWFLAG_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSE -// -//***************************************************************************** -// Field: [28:24] INSTRUCTION -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSE_INSTRUCTION_W 5 -#define FLASH_EFUSE_INSTRUCTION_M 0x1F000000 -#define FLASH_EFUSE_INSTRUCTION_S 24 - -// Field: [15:0] DUMPWORD -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSE_DUMPWORD_W 16 -#define FLASH_EFUSE_DUMPWORD_M 0x0000FFFF -#define FLASH_EFUSE_DUMPWORD_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEADDR -// -//***************************************************************************** -// Field: [15:11] BLOCK -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEADDR_BLOCK_W 5 -#define FLASH_EFUSEADDR_BLOCK_M 0x0000F800 -#define FLASH_EFUSEADDR_BLOCK_S 11 - -// Field: [10:0] ROW -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEADDR_ROW_W 11 -#define FLASH_EFUSEADDR_ROW_M 0x000007FF -#define FLASH_EFUSEADDR_ROW_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_DATAUPPER -// -//***************************************************************************** -// Field: [7:3] SPARE -// -// Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_SPARE_W 5 -#define FLASH_DATAUPPER_SPARE_M 0x000000F8 -#define FLASH_DATAUPPER_SPARE_S 3 - -// Field: [2] P -// -// Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_P 0x00000004 -#define FLASH_DATAUPPER_P_BITN 2 -#define FLASH_DATAUPPER_P_M 0x00000004 -#define FLASH_DATAUPPER_P_S 2 - -// Field: [1] R -// -// Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_R 0x00000002 -#define FLASH_DATAUPPER_R_BITN 1 -#define FLASH_DATAUPPER_R_M 0x00000002 -#define FLASH_DATAUPPER_R_S 1 - -// Field: [0] EEN -// -// Internal. Only to be used through TI provided API. -#define FLASH_DATAUPPER_EEN 0x00000001 -#define FLASH_DATAUPPER_EEN_BITN 0 -#define FLASH_DATAUPPER_EEN_M 0x00000001 -#define FLASH_DATAUPPER_EEN_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_DATALOWER -// -//***************************************************************************** -// Field: [31:0] DATA -// -// Internal. Only to be used through TI provided API. -#define FLASH_DATALOWER_DATA_W 32 -#define FLASH_DATALOWER_DATA_M 0xFFFFFFFF -#define FLASH_DATALOWER_DATA_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSECFG -// -//***************************************************************************** -// Field: [8] IDLEGATING -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_IDLEGATING 0x00000100 -#define FLASH_EFUSECFG_IDLEGATING_BITN 8 -#define FLASH_EFUSECFG_IDLEGATING_M 0x00000100 -#define FLASH_EFUSECFG_IDLEGATING_S 8 - -// Field: [4:3] SLAVEPOWER -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_SLAVEPOWER_W 2 -#define FLASH_EFUSECFG_SLAVEPOWER_M 0x00000018 -#define FLASH_EFUSECFG_SLAVEPOWER_S 3 - -// Field: [0] GATING -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSECFG_GATING 0x00000001 -#define FLASH_EFUSECFG_GATING_BITN 0 -#define FLASH_EFUSECFG_GATING_M 0x00000001 -#define FLASH_EFUSECFG_GATING_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSESTAT -// -//***************************************************************************** -// Field: [0] RESETDONE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSESTAT_RESETDONE 0x00000001 -#define FLASH_EFUSESTAT_RESETDONE_BITN 0 -#define FLASH_EFUSESTAT_RESETDONE_M 0x00000001 -#define FLASH_EFUSESTAT_RESETDONE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_ACC -// -//***************************************************************************** -// Field: [23:0] ACCUMULATOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_ACC_ACCUMULATOR_W 24 -#define FLASH_ACC_ACCUMULATOR_M 0x00FFFFFF -#define FLASH_ACC_ACCUMULATOR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_BOUNDARY -// -//***************************************************************************** -// Field: [23] DISROW0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_DISROW0 0x00800000 -#define FLASH_BOUNDARY_DISROW0_BITN 23 -#define FLASH_BOUNDARY_DISROW0_M 0x00800000 -#define FLASH_BOUNDARY_DISROW0_S 23 - -// Field: [22] SPARE -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SPARE 0x00400000 -#define FLASH_BOUNDARY_SPARE_BITN 22 -#define FLASH_BOUNDARY_SPARE_M 0x00400000 -#define FLASH_BOUNDARY_SPARE_S 22 - -// Field: [21] EFC_SELF_TEST_ERROR -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR 0x00200000 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_BITN 21 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_M 0x00200000 -#define FLASH_BOUNDARY_EFC_SELF_TEST_ERROR_S 21 - -// Field: [20] EFC_INSTRUCTION_INFO -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO 0x00100000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_BITN 20 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_M 0x00100000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_INFO_S 20 - -// Field: [19] EFC_INSTRUCTION_ERROR -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR 0x00080000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_BITN 19 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_M 0x00080000 -#define FLASH_BOUNDARY_EFC_INSTRUCTION_ERROR_S 19 - -// Field: [18] EFC_AUTOLOAD_ERROR -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR 0x00040000 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_BITN 18 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_M 0x00040000 -#define FLASH_BOUNDARY_EFC_AUTOLOAD_ERROR_S 18 - -// Field: [17:14] OUTPUTENABLE -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_OUTPUTENABLE_W 4 -#define FLASH_BOUNDARY_OUTPUTENABLE_M 0x0003C000 -#define FLASH_BOUNDARY_OUTPUTENABLE_S 14 - -// Field: [13] SYS_ECC_SELF_TEST_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN 0x00002000 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_BITN 13 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_M 0x00002000 -#define FLASH_BOUNDARY_SYS_ECC_SELF_TEST_EN_S 13 - -// Field: [12] SYS_ECC_OVERRIDE_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN 0x00001000 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_BITN 12 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_M 0x00001000 -#define FLASH_BOUNDARY_SYS_ECC_OVERRIDE_EN_S 12 - -// Field: [11] EFC_FDI -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_EFC_FDI 0x00000800 -#define FLASH_BOUNDARY_EFC_FDI_BITN 11 -#define FLASH_BOUNDARY_EFC_FDI_M 0x00000800 -#define FLASH_BOUNDARY_EFC_FDI_S 11 - -// Field: [10] SYS_DIEID_AUTOLOAD_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN 0x00000400 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_BITN 10 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_M 0x00000400 -#define FLASH_BOUNDARY_SYS_DIEID_AUTOLOAD_EN_S 10 - -// Field: [9:8] SYS_REPAIR_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_REPAIR_EN_W 2 -#define FLASH_BOUNDARY_SYS_REPAIR_EN_M 0x00000300 -#define FLASH_BOUNDARY_SYS_REPAIR_EN_S 8 - -// Field: [7:4] SYS_WS_READ_STATES -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_W 4 -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_M 0x000000F0 -#define FLASH_BOUNDARY_SYS_WS_READ_STATES_S 4 - -// Field: [3:0] INPUTENABLE -// -// Internal. Only to be used through TI provided API. -#define FLASH_BOUNDARY_INPUTENABLE_W 4 -#define FLASH_BOUNDARY_INPUTENABLE_M 0x0000000F -#define FLASH_BOUNDARY_INPUTENABLE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEFLAG -// -//***************************************************************************** -// Field: [0] KEY -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEFLAG_KEY 0x00000001 -#define FLASH_EFUSEFLAG_KEY_BITN 0 -#define FLASH_EFUSEFLAG_KEY_M 0x00000001 -#define FLASH_EFUSEFLAG_KEY_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEKEY -// -//***************************************************************************** -// Field: [31:0] CODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEKEY_CODE_W 32 -#define FLASH_EFUSEKEY_CODE_M 0xFFFFFFFF -#define FLASH_EFUSEKEY_CODE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSERELEASE -// -//***************************************************************************** -// Field: [31:25] ODPYEAR -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPYEAR_W 7 -#define FLASH_EFUSERELEASE_ODPYEAR_M 0xFE000000 -#define FLASH_EFUSERELEASE_ODPYEAR_S 25 - -// Field: [24:21] ODPMONTH -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPMONTH_W 4 -#define FLASH_EFUSERELEASE_ODPMONTH_M 0x01E00000 -#define FLASH_EFUSERELEASE_ODPMONTH_S 21 - -// Field: [20:16] ODPDAY -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_ODPDAY_W 5 -#define FLASH_EFUSERELEASE_ODPDAY_M 0x001F0000 -#define FLASH_EFUSERELEASE_ODPDAY_S 16 - -// Field: [15:9] EFUSEYEAR -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEYEAR_W 7 -#define FLASH_EFUSERELEASE_EFUSEYEAR_M 0x0000FE00 -#define FLASH_EFUSERELEASE_EFUSEYEAR_S 9 - -// Field: [8:5] EFUSEMONTH -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEMONTH_W 4 -#define FLASH_EFUSERELEASE_EFUSEMONTH_M 0x000001E0 -#define FLASH_EFUSERELEASE_EFUSEMONTH_S 5 - -// Field: [4:0] EFUSEDAY -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSERELEASE_EFUSEDAY_W 5 -#define FLASH_EFUSERELEASE_EFUSEDAY_M 0x0000001F -#define FLASH_EFUSERELEASE_EFUSEDAY_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEPINS -// -//***************************************************************************** -// Field: [15] EFC_SELF_TEST_DONE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE 0x00008000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_BITN 15 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_M 0x00008000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_DONE_S 15 - -// Field: [14] EFC_SELF_TEST_ERROR -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR 0x00004000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_BITN 14 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_M 0x00004000 -#define FLASH_EFUSEPINS_EFC_SELF_TEST_ERROR_S 14 - -// Field: [13] SYS_ECC_SELF_TEST_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN 0x00002000 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_BITN 13 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_M 0x00002000 -#define FLASH_EFUSEPINS_SYS_ECC_SELF_TEST_EN_S 13 - -// Field: [12] EFC_INSTRUCTION_INFO -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO 0x00001000 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_BITN 12 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_M 0x00001000 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_INFO_S 12 - -// Field: [11] EFC_INSTRUCTION_ERROR -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR 0x00000800 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_BITN 11 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_M 0x00000800 -#define FLASH_EFUSEPINS_EFC_INSTRUCTION_ERROR_S 11 - -// Field: [10] EFC_AUTOLOAD_ERROR -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR 0x00000400 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_BITN 10 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_M 0x00000400 -#define FLASH_EFUSEPINS_EFC_AUTOLOAD_ERROR_S 10 - -// Field: [9] SYS_ECC_OVERRIDE_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN 0x00000200 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_BITN 9 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_M 0x00000200 -#define FLASH_EFUSEPINS_SYS_ECC_OVERRIDE_EN_S 9 - -// Field: [8] EFC_READY -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_READY 0x00000100 -#define FLASH_EFUSEPINS_EFC_READY_BITN 8 -#define FLASH_EFUSEPINS_EFC_READY_M 0x00000100 -#define FLASH_EFUSEPINS_EFC_READY_S 8 - -// Field: [7] EFC_FCLRZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_EFC_FCLRZ 0x00000080 -#define FLASH_EFUSEPINS_EFC_FCLRZ_BITN 7 -#define FLASH_EFUSEPINS_EFC_FCLRZ_M 0x00000080 -#define FLASH_EFUSEPINS_EFC_FCLRZ_S 7 - -// Field: [6] SYS_DIEID_AUTOLOAD_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN 0x00000040 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_BITN 6 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_M 0x00000040 -#define FLASH_EFUSEPINS_SYS_DIEID_AUTOLOAD_EN_S 6 - -// Field: [5:4] SYS_REPAIR_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_W 2 -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_M 0x00000030 -#define FLASH_EFUSEPINS_SYS_REPAIR_EN_S 4 - -// Field: [3:0] SYS_WS_READ_STATES -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_W 4 -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_M 0x0000000F -#define FLASH_EFUSEPINS_SYS_WS_READ_STATES_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSECRA -// -//***************************************************************************** -// Field: [5:0] DATA -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSECRA_DATA_W 6 -#define FLASH_EFUSECRA_DATA_M 0x0000003F -#define FLASH_EFUSECRA_DATA_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEREAD -// -//***************************************************************************** -// Field: [9:8] DATABIT -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_DATABIT_W 2 -#define FLASH_EFUSEREAD_DATABIT_M 0x00000300 -#define FLASH_EFUSEREAD_DATABIT_S 8 - -// Field: [7:4] READCLOCK -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_READCLOCK_W 4 -#define FLASH_EFUSEREAD_READCLOCK_M 0x000000F0 -#define FLASH_EFUSEREAD_READCLOCK_S 4 - -// Field: [3] DEBUG -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_DEBUG 0x00000008 -#define FLASH_EFUSEREAD_DEBUG_BITN 3 -#define FLASH_EFUSEREAD_DEBUG_M 0x00000008 -#define FLASH_EFUSEREAD_DEBUG_S 3 - -// Field: [2] SPARE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_SPARE 0x00000004 -#define FLASH_EFUSEREAD_SPARE_BITN 2 -#define FLASH_EFUSEREAD_SPARE_M 0x00000004 -#define FLASH_EFUSEREAD_SPARE_S 2 - -// Field: [1:0] MARGIN -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEREAD_MARGIN_W 2 -#define FLASH_EFUSEREAD_MARGIN_M 0x00000003 -#define FLASH_EFUSEREAD_MARGIN_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEPROGRAM -// -//***************************************************************************** -// Field: [30] COMPAREDISABLE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE 0x40000000 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_BITN 30 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_M 0x40000000 -#define FLASH_EFUSEPROGRAM_COMPAREDISABLE_S 30 - -// Field: [29:14] CLOCKSTALL -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_W 16 -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_M 0x3FFFC000 -#define FLASH_EFUSEPROGRAM_CLOCKSTALL_S 14 - -// Field: [13] VPPTOVDD -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_VPPTOVDD 0x00002000 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_BITN 13 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_M 0x00002000 -#define FLASH_EFUSEPROGRAM_VPPTOVDD_S 13 - -// Field: [12:9] ITERATIONS -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_ITERATIONS_W 4 -#define FLASH_EFUSEPROGRAM_ITERATIONS_M 0x00001E00 -#define FLASH_EFUSEPROGRAM_ITERATIONS_S 9 - -// Field: [8:0] WRITECLOCK -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEPROGRAM_WRITECLOCK_W 9 -#define FLASH_EFUSEPROGRAM_WRITECLOCK_M 0x000001FF -#define FLASH_EFUSEPROGRAM_WRITECLOCK_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_EFUSEERROR -// -//***************************************************************************** -// Field: [5] DONE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEERROR_DONE 0x00000020 -#define FLASH_EFUSEERROR_DONE_BITN 5 -#define FLASH_EFUSEERROR_DONE_M 0x00000020 -#define FLASH_EFUSEERROR_DONE_S 5 - -// Field: [4:0] CODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_EFUSEERROR_CODE_W 5 -#define FLASH_EFUSEERROR_CODE_M 0x0000001F -#define FLASH_EFUSEERROR_CODE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_SINGLEBIT -// -//***************************************************************************** -// Field: [31:1] FROMN -// -// Internal. Only to be used through TI provided API. -#define FLASH_SINGLEBIT_FROMN_W 31 -#define FLASH_SINGLEBIT_FROMN_M 0xFFFFFFFE -#define FLASH_SINGLEBIT_FROMN_S 1 - -// Field: [0] FROM0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_SINGLEBIT_FROM0 0x00000001 -#define FLASH_SINGLEBIT_FROM0_BITN 0 -#define FLASH_SINGLEBIT_FROM0_M 0x00000001 -#define FLASH_SINGLEBIT_FROM0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_TWOBIT -// -//***************************************************************************** -// Field: [31:1] FROMN -// -// Internal. Only to be used through TI provided API. -#define FLASH_TWOBIT_FROMN_W 31 -#define FLASH_TWOBIT_FROMN_M 0xFFFFFFFE -#define FLASH_TWOBIT_FROMN_S 1 - -// Field: [0] FROM0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_TWOBIT_FROM0 0x00000001 -#define FLASH_TWOBIT_FROM0_BITN 0 -#define FLASH_TWOBIT_FROM0_M 0x00000001 -#define FLASH_TWOBIT_FROM0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_SELFTESTCYC -// -//***************************************************************************** -// Field: [31:0] CYCLES -// -// Internal. Only to be used through TI provided API. -#define FLASH_SELFTESTCYC_CYCLES_W 32 -#define FLASH_SELFTESTCYC_CYCLES_M 0xFFFFFFFF -#define FLASH_SELFTESTCYC_CYCLES_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_SELFTESTSIGN -// -//***************************************************************************** -// Field: [31:0] SIGNATURE -// -// Internal. Only to be used through TI provided API. -#define FLASH_SELFTESTSIGN_SIGNATURE_W 32 -#define FLASH_SELFTESTSIGN_SIGNATURE_M 0xFFFFFFFF -#define FLASH_SELFTESTSIGN_SIGNATURE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FRDCTL -// -//***************************************************************************** -// Field: [11:8] RWAIT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FRDCTL_RWAIT_W 4 -#define FLASH_FRDCTL_RWAIT_M 0x00000F00 -#define FLASH_FRDCTL_RWAIT_S 8 - -//***************************************************************************** -// -// Register: FLASH_O_FSPRD -// -//***************************************************************************** -// Field: [15:8] RMBSEM -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RMBSEM_W 8 -#define FLASH_FSPRD_RMBSEM_M 0x0000FF00 -#define FLASH_FSPRD_RMBSEM_S 8 - -// Field: [1] RM1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RM1 0x00000002 -#define FLASH_FSPRD_RM1_BITN 1 -#define FLASH_FSPRD_RM1_M 0x00000002 -#define FLASH_FSPRD_RM1_S 1 - -// Field: [0] RM0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSPRD_RM0 0x00000001 -#define FLASH_FSPRD_RM0_BITN 0 -#define FLASH_FSPRD_RM0_M 0x00000001 -#define FLASH_FSPRD_RM0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FEDACCTL1 -// -//***************************************************************************** -// Field: [24] SUSP_IGNR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEDACCTL1_SUSP_IGNR 0x01000000 -#define FLASH_FEDACCTL1_SUSP_IGNR_BITN 24 -#define FLASH_FEDACCTL1_SUSP_IGNR_M 0x01000000 -#define FLASH_FEDACCTL1_SUSP_IGNR_S 24 - -//***************************************************************************** -// -// Register: FLASH_O_FEDACSTAT -// -//***************************************************************************** -// Field: [25] RVF_INT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEDACSTAT_RVF_INT 0x02000000 -#define FLASH_FEDACSTAT_RVF_INT_BITN 25 -#define FLASH_FEDACSTAT_RVF_INT_M 0x02000000 -#define FLASH_FEDACSTAT_RVF_INT_S 25 - -// Field: [24] FSM_DONE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEDACSTAT_FSM_DONE 0x01000000 -#define FLASH_FEDACSTAT_FSM_DONE_BITN 24 -#define FLASH_FEDACSTAT_FSM_DONE_M 0x01000000 -#define FLASH_FEDACSTAT_FSM_DONE_S 24 - -//***************************************************************************** -// -// Register: FLASH_O_FBPROT -// -//***************************************************************************** -// Field: [0] PROTL1DIS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBPROT_PROTL1DIS 0x00000001 -#define FLASH_FBPROT_PROTL1DIS_BITN 0 -#define FLASH_FBPROT_PROTL1DIS_M 0x00000001 -#define FLASH_FBPROT_PROTL1DIS_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FBSE -// -//***************************************************************************** -// Field: [15:0] BSE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSE_BSE_W 16 -#define FLASH_FBSE_BSE_M 0x0000FFFF -#define FLASH_FBSE_BSE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FBBUSY -// -//***************************************************************************** -// Field: [7:0] BUSY -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBBUSY_BUSY_W 8 -#define FLASH_FBBUSY_BUSY_M 0x000000FF -#define FLASH_FBBUSY_BUSY_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FBAC -// -//***************************************************************************** -// Field: [16] OTPPROTDIS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBAC_OTPPROTDIS 0x00010000 -#define FLASH_FBAC_OTPPROTDIS_BITN 16 -#define FLASH_FBAC_OTPPROTDIS_M 0x00010000 -#define FLASH_FBAC_OTPPROTDIS_S 16 - -// Field: [15:8] BAGP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBAC_BAGP_W 8 -#define FLASH_FBAC_BAGP_M 0x0000FF00 -#define FLASH_FBAC_BAGP_S 8 - -// Field: [7:0] VREADS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBAC_VREADS_W 8 -#define FLASH_FBAC_VREADS_M 0x000000FF -#define FLASH_FBAC_VREADS_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FBFALLBACK -// -//***************************************************************************** -// Field: [27:24] FSM_PWRSAV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_FSM_PWRSAV_W 4 -#define FLASH_FBFALLBACK_FSM_PWRSAV_M 0x0F000000 -#define FLASH_FBFALLBACK_FSM_PWRSAV_S 24 - -// Field: [19:16] REG_PWRSAV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_REG_PWRSAV_W 4 -#define FLASH_FBFALLBACK_REG_PWRSAV_M 0x000F0000 -#define FLASH_FBFALLBACK_REG_PWRSAV_S 16 - -// Field: [15:14] BANKPWR7 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR7_W 2 -#define FLASH_FBFALLBACK_BANKPWR7_M 0x0000C000 -#define FLASH_FBFALLBACK_BANKPWR7_S 14 - -// Field: [13:12] BANKPWR6 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR6_W 2 -#define FLASH_FBFALLBACK_BANKPWR6_M 0x00003000 -#define FLASH_FBFALLBACK_BANKPWR6_S 12 - -// Field: [11:10] BANKPWR5 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR5_W 2 -#define FLASH_FBFALLBACK_BANKPWR5_M 0x00000C00 -#define FLASH_FBFALLBACK_BANKPWR5_S 10 - -// Field: [9:8] BANKPWR4 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR4_W 2 -#define FLASH_FBFALLBACK_BANKPWR4_M 0x00000300 -#define FLASH_FBFALLBACK_BANKPWR4_S 8 - -// Field: [7:6] BANKPWR3 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR3_W 2 -#define FLASH_FBFALLBACK_BANKPWR3_M 0x000000C0 -#define FLASH_FBFALLBACK_BANKPWR3_S 6 - -// Field: [5:4] BANKPWR2 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR2_W 2 -#define FLASH_FBFALLBACK_BANKPWR2_M 0x00000030 -#define FLASH_FBFALLBACK_BANKPWR2_S 4 - -// Field: [3:2] BANKPWR1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR1_W 2 -#define FLASH_FBFALLBACK_BANKPWR1_M 0x0000000C -#define FLASH_FBFALLBACK_BANKPWR1_S 2 - -// Field: [1:0] BANKPWR0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBFALLBACK_BANKPWR0_W 2 -#define FLASH_FBFALLBACK_BANKPWR0_M 0x00000003 -#define FLASH_FBFALLBACK_BANKPWR0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FBPRDY -// -//***************************************************************************** -// Field: [16] BANKBUSY -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_BANKBUSY 0x00010000 -#define FLASH_FBPRDY_BANKBUSY_BITN 16 -#define FLASH_FBPRDY_BANKBUSY_M 0x00010000 -#define FLASH_FBPRDY_BANKBUSY_S 16 - -// Field: [15] PUMPRDY -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_PUMPRDY 0x00008000 -#define FLASH_FBPRDY_PUMPRDY_BITN 15 -#define FLASH_FBPRDY_PUMPRDY_M 0x00008000 -#define FLASH_FBPRDY_PUMPRDY_S 15 - -// Field: [0] BANKRDY -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBPRDY_BANKRDY 0x00000001 -#define FLASH_FBPRDY_BANKRDY_BITN 0 -#define FLASH_FBPRDY_BANKRDY_M 0x00000001 -#define FLASH_FBPRDY_BANKRDY_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FPAC1 -// -//***************************************************************************** -// Field: [27:16] PSLEEPTDIS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PSLEEPTDIS_W 12 -#define FLASH_FPAC1_PSLEEPTDIS_M 0x0FFF0000 -#define FLASH_FPAC1_PSLEEPTDIS_S 16 - -// Field: [15:4] PUMPRESET_PW -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PUMPRESET_PW_W 12 -#define FLASH_FPAC1_PUMPRESET_PW_M 0x0000FFF0 -#define FLASH_FPAC1_PUMPRESET_PW_S 4 - -// Field: [1:0] PUMPPWR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPAC1_PUMPPWR_W 2 -#define FLASH_FPAC1_PUMPPWR_M 0x00000003 -#define FLASH_FPAC1_PUMPPWR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FPAC2 -// -//***************************************************************************** -// Field: [15:0] PAGP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPAC2_PAGP_W 16 -#define FLASH_FPAC2_PAGP_M 0x0000FFFF -#define FLASH_FPAC2_PAGP_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FMAC -// -//***************************************************************************** -// Field: [2:0] BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMAC_BANK_W 3 -#define FLASH_FMAC_BANK_M 0x00000007 -#define FLASH_FMAC_BANK_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FMSTAT -// -//***************************************************************************** -// Field: [17] RVSUSP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RVSUSP 0x00020000 -#define FLASH_FMSTAT_RVSUSP_BITN 17 -#define FLASH_FMSTAT_RVSUSP_M 0x00020000 -#define FLASH_FMSTAT_RVSUSP_S 17 - -// Field: [16] RDVER -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RDVER 0x00010000 -#define FLASH_FMSTAT_RDVER_BITN 16 -#define FLASH_FMSTAT_RDVER_M 0x00010000 -#define FLASH_FMSTAT_RDVER_S 16 - -// Field: [15] RVF -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_RVF 0x00008000 -#define FLASH_FMSTAT_RVF_BITN 15 -#define FLASH_FMSTAT_RVF_M 0x00008000 -#define FLASH_FMSTAT_RVF_S 15 - -// Field: [14] ILA -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ILA 0x00004000 -#define FLASH_FMSTAT_ILA_BITN 14 -#define FLASH_FMSTAT_ILA_M 0x00004000 -#define FLASH_FMSTAT_ILA_S 14 - -// Field: [13] DBF -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_DBF 0x00002000 -#define FLASH_FMSTAT_DBF_BITN 13 -#define FLASH_FMSTAT_DBF_M 0x00002000 -#define FLASH_FMSTAT_DBF_S 13 - -// Field: [12] PGV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PGV 0x00001000 -#define FLASH_FMSTAT_PGV_BITN 12 -#define FLASH_FMSTAT_PGV_M 0x00001000 -#define FLASH_FMSTAT_PGV_S 12 - -// Field: [11] PCV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PCV 0x00000800 -#define FLASH_FMSTAT_PCV_BITN 11 -#define FLASH_FMSTAT_PCV_M 0x00000800 -#define FLASH_FMSTAT_PCV_S 11 - -// Field: [10] EV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_EV 0x00000400 -#define FLASH_FMSTAT_EV_BITN 10 -#define FLASH_FMSTAT_EV_M 0x00000400 -#define FLASH_FMSTAT_EV_S 10 - -// Field: [9] CV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_CV 0x00000200 -#define FLASH_FMSTAT_CV_BITN 9 -#define FLASH_FMSTAT_CV_M 0x00000200 -#define FLASH_FMSTAT_CV_S 9 - -// Field: [8] BUSY -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_BUSY 0x00000100 -#define FLASH_FMSTAT_BUSY_BITN 8 -#define FLASH_FMSTAT_BUSY_M 0x00000100 -#define FLASH_FMSTAT_BUSY_S 8 - -// Field: [7] ERS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ERS 0x00000080 -#define FLASH_FMSTAT_ERS_BITN 7 -#define FLASH_FMSTAT_ERS_M 0x00000080 -#define FLASH_FMSTAT_ERS_S 7 - -// Field: [6] PGM -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PGM 0x00000040 -#define FLASH_FMSTAT_PGM_BITN 6 -#define FLASH_FMSTAT_PGM_M 0x00000040 -#define FLASH_FMSTAT_PGM_S 6 - -// Field: [5] INVDAT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_INVDAT 0x00000020 -#define FLASH_FMSTAT_INVDAT_BITN 5 -#define FLASH_FMSTAT_INVDAT_M 0x00000020 -#define FLASH_FMSTAT_INVDAT_S 5 - -// Field: [4] CSTAT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_CSTAT 0x00000010 -#define FLASH_FMSTAT_CSTAT_BITN 4 -#define FLASH_FMSTAT_CSTAT_M 0x00000010 -#define FLASH_FMSTAT_CSTAT_S 4 - -// Field: [3] VOLSTAT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_VOLSTAT 0x00000008 -#define FLASH_FMSTAT_VOLSTAT_BITN 3 -#define FLASH_FMSTAT_VOLSTAT_M 0x00000008 -#define FLASH_FMSTAT_VOLSTAT_S 3 - -// Field: [2] ESUSP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_ESUSP 0x00000004 -#define FLASH_FMSTAT_ESUSP_BITN 2 -#define FLASH_FMSTAT_ESUSP_M 0x00000004 -#define FLASH_FMSTAT_ESUSP_S 2 - -// Field: [1] PSUSP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_PSUSP 0x00000002 -#define FLASH_FMSTAT_PSUSP_BITN 1 -#define FLASH_FMSTAT_PSUSP_M 0x00000002 -#define FLASH_FMSTAT_PSUSP_S 1 - -// Field: [0] SLOCK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMSTAT_SLOCK 0x00000001 -#define FLASH_FMSTAT_SLOCK_BITN 0 -#define FLASH_FMSTAT_SLOCK_M 0x00000001 -#define FLASH_FMSTAT_SLOCK_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FLOCK -// -//***************************************************************************** -// Field: [15:0] ENCOM -// -// Internal. Only to be used through TI provided API. -#define FLASH_FLOCK_ENCOM_W 16 -#define FLASH_FLOCK_ENCOM_M 0x0000FFFF -#define FLASH_FLOCK_ENCOM_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FVREADCT -// -//***************************************************************************** -// Field: [3:0] VREADCT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVREADCT_VREADCT_W 4 -#define FLASH_FVREADCT_VREADCT_M 0x0000000F -#define FLASH_FVREADCT_VREADCT_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FVHVCT1 -// -//***************************************************************************** -// Field: [23:20] TRIM13_E -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_TRIM13_E_W 4 -#define FLASH_FVHVCT1_TRIM13_E_M 0x00F00000 -#define FLASH_FVHVCT1_TRIM13_E_S 20 - -// Field: [19:16] VHVCT_E -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_VHVCT_E_W 4 -#define FLASH_FVHVCT1_VHVCT_E_M 0x000F0000 -#define FLASH_FVHVCT1_VHVCT_E_S 16 - -// Field: [7:4] TRIM13_PV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_TRIM13_PV_W 4 -#define FLASH_FVHVCT1_TRIM13_PV_M 0x000000F0 -#define FLASH_FVHVCT1_TRIM13_PV_S 4 - -// Field: [3:0] VHVCT_PV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT1_VHVCT_PV_W 4 -#define FLASH_FVHVCT1_VHVCT_PV_M 0x0000000F -#define FLASH_FVHVCT1_VHVCT_PV_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FVHVCT2 -// -//***************************************************************************** -// Field: [23:20] TRIM13_P -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT2_TRIM13_P_W 4 -#define FLASH_FVHVCT2_TRIM13_P_M 0x00F00000 -#define FLASH_FVHVCT2_TRIM13_P_S 20 - -// Field: [19:16] VHVCT_P -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT2_VHVCT_P_W 4 -#define FLASH_FVHVCT2_VHVCT_P_M 0x000F0000 -#define FLASH_FVHVCT2_VHVCT_P_S 16 - -//***************************************************************************** -// -// Register: FLASH_O_FVHVCT3 -// -//***************************************************************************** -// Field: [19:16] WCT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT3_WCT_W 4 -#define FLASH_FVHVCT3_WCT_M 0x000F0000 -#define FLASH_FVHVCT3_WCT_S 16 - -// Field: [3:0] VHVCT_READ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVHVCT3_VHVCT_READ_W 4 -#define FLASH_FVHVCT3_VHVCT_READ_M 0x0000000F -#define FLASH_FVHVCT3_VHVCT_READ_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FVNVCT -// -//***************************************************************************** -// Field: [12:8] VCG2P5CT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVNVCT_VCG2P5CT_W 5 -#define FLASH_FVNVCT_VCG2P5CT_M 0x00001F00 -#define FLASH_FVNVCT_VCG2P5CT_S 8 - -// Field: [4:0] VIN_CT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVNVCT_VIN_CT_W 5 -#define FLASH_FVNVCT_VIN_CT_M 0x0000001F -#define FLASH_FVNVCT_VIN_CT_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FVSLP -// -//***************************************************************************** -// Field: [15:12] VSL_P -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVSLP_VSL_P_W 4 -#define FLASH_FVSLP_VSL_P_M 0x0000F000 -#define FLASH_FVSLP_VSL_P_S 12 - -//***************************************************************************** -// -// Register: FLASH_O_FVWLCT -// -//***************************************************************************** -// Field: [4:0] VWLCT_P -// -// Internal. Only to be used through TI provided API. -#define FLASH_FVWLCT_VWLCT_P_W 5 -#define FLASH_FVWLCT_VWLCT_P_M 0x0000001F -#define FLASH_FVWLCT_VWLCT_P_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FEFUSECTL -// -//***************************************************************************** -// Field: [26:24] CHAIN_SEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_CHAIN_SEL_W 3 -#define FLASH_FEFUSECTL_CHAIN_SEL_M 0x07000000 -#define FLASH_FEFUSECTL_CHAIN_SEL_S 24 - -// Field: [17] WRITE_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_WRITE_EN 0x00020000 -#define FLASH_FEFUSECTL_WRITE_EN_BITN 17 -#define FLASH_FEFUSECTL_WRITE_EN_M 0x00020000 -#define FLASH_FEFUSECTL_WRITE_EN_S 17 - -// Field: [16] BP_SEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_BP_SEL 0x00010000 -#define FLASH_FEFUSECTL_BP_SEL_BITN 16 -#define FLASH_FEFUSECTL_BP_SEL_M 0x00010000 -#define FLASH_FEFUSECTL_BP_SEL_S 16 - -// Field: [8] EF_CLRZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EF_CLRZ 0x00000100 -#define FLASH_FEFUSECTL_EF_CLRZ_BITN 8 -#define FLASH_FEFUSECTL_EF_CLRZ_M 0x00000100 -#define FLASH_FEFUSECTL_EF_CLRZ_S 8 - -// Field: [4] EF_TEST -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EF_TEST 0x00000010 -#define FLASH_FEFUSECTL_EF_TEST_BITN 4 -#define FLASH_FEFUSECTL_EF_TEST_M 0x00000010 -#define FLASH_FEFUSECTL_EF_TEST_S 4 - -// Field: [3:0] EFUSE_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSECTL_EFUSE_EN_W 4 -#define FLASH_FEFUSECTL_EFUSE_EN_M 0x0000000F -#define FLASH_FEFUSECTL_EFUSE_EN_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FEFUSESTAT -// -//***************************************************************************** -// Field: [0] SHIFT_DONE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSESTAT_SHIFT_DONE 0x00000001 -#define FLASH_FEFUSESTAT_SHIFT_DONE_BITN 0 -#define FLASH_FEFUSESTAT_SHIFT_DONE_M 0x00000001 -#define FLASH_FEFUSESTAT_SHIFT_DONE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FEFUSEDATA -// -//***************************************************************************** -// Field: [31:0] FEFUSEDATA -// -// Internal. Only to be used through TI provided API. -#define FLASH_FEFUSEDATA_FEFUSEDATA_W 32 -#define FLASH_FEFUSEDATA_FEFUSEDATA_M 0xFFFFFFFF -#define FLASH_FEFUSEDATA_FEFUSEDATA_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSEQPMP -// -//***************************************************************************** -// Field: [27:24] TRIM_3P4 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_3P4_W 4 -#define FLASH_FSEQPMP_TRIM_3P4_M 0x0F000000 -#define FLASH_FSEQPMP_TRIM_3P4_S 24 - -// Field: [21:20] TRIM_1P7 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_1P7_W 2 -#define FLASH_FSEQPMP_TRIM_1P7_M 0x00300000 -#define FLASH_FSEQPMP_TRIM_1P7_S 20 - -// Field: [19:16] TRIM_0P8 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_TRIM_0P8_W 4 -#define FLASH_FSEQPMP_TRIM_0P8_M 0x000F0000 -#define FLASH_FSEQPMP_TRIM_0P8_S 16 - -// Field: [14:12] VIN_AT_X -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_VIN_AT_X_W 3 -#define FLASH_FSEQPMP_VIN_AT_X_M 0x00007000 -#define FLASH_FSEQPMP_VIN_AT_X_S 12 - -// Field: [8] VIN_BY_PASS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSEQPMP_VIN_BY_PASS 0x00000100 -#define FLASH_FSEQPMP_VIN_BY_PASS_BITN 8 -#define FLASH_FSEQPMP_VIN_BY_PASS_M 0x00000100 -#define FLASH_FSEQPMP_VIN_BY_PASS_S 8 - -//***************************************************************************** -// -// Register: FLASH_O_FBSTROBES -// -//***************************************************************************** -// Field: [24] ECBIT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_ECBIT 0x01000000 -#define FLASH_FBSTROBES_ECBIT_BITN 24 -#define FLASH_FBSTROBES_ECBIT_M 0x01000000 -#define FLASH_FBSTROBES_ECBIT_S 24 - -// Field: [18] RWAIT2_FLCLK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_RWAIT2_FLCLK 0x00040000 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_BITN 18 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_M 0x00040000 -#define FLASH_FBSTROBES_RWAIT2_FLCLK_S 18 - -// Field: [17] RWAIT_FLCLK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_RWAIT_FLCLK 0x00020000 -#define FLASH_FBSTROBES_RWAIT_FLCLK_BITN 17 -#define FLASH_FBSTROBES_RWAIT_FLCLK_M 0x00020000 -#define FLASH_FBSTROBES_RWAIT_FLCLK_S 17 - -// Field: [16] FLCLKEN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_FLCLKEN 0x00010000 -#define FLASH_FBSTROBES_FLCLKEN_BITN 16 -#define FLASH_FBSTROBES_FLCLKEN_M 0x00010000 -#define FLASH_FBSTROBES_FLCLKEN_S 16 - -// Field: [8] CTRLENZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_CTRLENZ 0x00000100 -#define FLASH_FBSTROBES_CTRLENZ_BITN 8 -#define FLASH_FBSTROBES_CTRLENZ_M 0x00000100 -#define FLASH_FBSTROBES_CTRLENZ_S 8 - -// Field: [6] NOCOLRED -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_NOCOLRED 0x00000040 -#define FLASH_FBSTROBES_NOCOLRED_BITN 6 -#define FLASH_FBSTROBES_NOCOLRED_M 0x00000040 -#define FLASH_FBSTROBES_NOCOLRED_S 6 - -// Field: [5] PRECOL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_PRECOL 0x00000020 -#define FLASH_FBSTROBES_PRECOL_BITN 5 -#define FLASH_FBSTROBES_PRECOL_M 0x00000020 -#define FLASH_FBSTROBES_PRECOL_S 5 - -// Field: [4] TI_OTP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_TI_OTP 0x00000010 -#define FLASH_FBSTROBES_TI_OTP_BITN 4 -#define FLASH_FBSTROBES_TI_OTP_M 0x00000010 -#define FLASH_FBSTROBES_TI_OTP_S 4 - -// Field: [3] OTP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_OTP 0x00000008 -#define FLASH_FBSTROBES_OTP_BITN 3 -#define FLASH_FBSTROBES_OTP_M 0x00000008 -#define FLASH_FBSTROBES_OTP_S 3 - -// Field: [2] TEZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBSTROBES_TEZ 0x00000004 -#define FLASH_FBSTROBES_TEZ_BITN 2 -#define FLASH_FBSTROBES_TEZ_M 0x00000004 -#define FLASH_FBSTROBES_TEZ_S 2 - -//***************************************************************************** -// -// Register: FLASH_O_FPSTROBES -// -//***************************************************************************** -// Field: [8] EXECUTEZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_EXECUTEZ 0x00000100 -#define FLASH_FPSTROBES_EXECUTEZ_BITN 8 -#define FLASH_FPSTROBES_EXECUTEZ_M 0x00000100 -#define FLASH_FPSTROBES_EXECUTEZ_S 8 - -// Field: [1] V3PWRDNZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_V3PWRDNZ 0x00000002 -#define FLASH_FPSTROBES_V3PWRDNZ_BITN 1 -#define FLASH_FPSTROBES_V3PWRDNZ_M 0x00000002 -#define FLASH_FPSTROBES_V3PWRDNZ_S 1 - -// Field: [0] V5PWRDNZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FPSTROBES_V5PWRDNZ 0x00000001 -#define FLASH_FPSTROBES_V5PWRDNZ_BITN 0 -#define FLASH_FPSTROBES_V5PWRDNZ_M 0x00000001 -#define FLASH_FPSTROBES_V5PWRDNZ_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FBMODE -// -//***************************************************************************** -// Field: [2:0] MODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FBMODE_MODE_W 3 -#define FLASH_FBMODE_MODE_M 0x00000007 -#define FLASH_FBMODE_MODE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FTCR -// -//***************************************************************************** -// Field: [6:0] TCR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FTCR_TCR_W 7 -#define FLASH_FTCR_TCR_M 0x0000007F -#define FLASH_FTCR_TCR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FADDR -// -//***************************************************************************** -// Field: [31:0] FADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FADDR_FADDR_W 32 -#define FLASH_FADDR_FADDR_M 0xFFFFFFFF -#define FLASH_FADDR_FADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FTCTL -// -//***************************************************************************** -// Field: [16] WDATA_BLK_CLR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FTCTL_WDATA_BLK_CLR 0x00010000 -#define FLASH_FTCTL_WDATA_BLK_CLR_BITN 16 -#define FLASH_FTCTL_WDATA_BLK_CLR_M 0x00010000 -#define FLASH_FTCTL_WDATA_BLK_CLR_S 16 - -// Field: [1] TEST_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FTCTL_TEST_EN 0x00000002 -#define FLASH_FTCTL_TEST_EN_BITN 1 -#define FLASH_FTCTL_TEST_EN_M 0x00000002 -#define FLASH_FTCTL_TEST_EN_S 1 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE0 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE0_FWPWRITE0_W 32 -#define FLASH_FWPWRITE0_FWPWRITE0_M 0xFFFFFFFF -#define FLASH_FWPWRITE0_FWPWRITE0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE1 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE1_FWPWRITE1_W 32 -#define FLASH_FWPWRITE1_FWPWRITE1_M 0xFFFFFFFF -#define FLASH_FWPWRITE1_FWPWRITE1_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE2 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE2 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE2_FWPWRITE2_W 32 -#define FLASH_FWPWRITE2_FWPWRITE2_M 0xFFFFFFFF -#define FLASH_FWPWRITE2_FWPWRITE2_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE3 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE3 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE3_FWPWRITE3_W 32 -#define FLASH_FWPWRITE3_FWPWRITE3_M 0xFFFFFFFF -#define FLASH_FWPWRITE3_FWPWRITE3_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE4 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE4 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE4_FWPWRITE4_W 32 -#define FLASH_FWPWRITE4_FWPWRITE4_M 0xFFFFFFFF -#define FLASH_FWPWRITE4_FWPWRITE4_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE5 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE5 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE5_FWPWRITE5_W 32 -#define FLASH_FWPWRITE5_FWPWRITE5_M 0xFFFFFFFF -#define FLASH_FWPWRITE5_FWPWRITE5_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE6 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE6 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE6_FWPWRITE6_W 32 -#define FLASH_FWPWRITE6_FWPWRITE6_M 0xFFFFFFFF -#define FLASH_FWPWRITE6_FWPWRITE6_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE7 -// -//***************************************************************************** -// Field: [31:0] FWPWRITE7 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE7_FWPWRITE7_W 32 -#define FLASH_FWPWRITE7_FWPWRITE7_M 0xFFFFFFFF -#define FLASH_FWPWRITE7_FWPWRITE7_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FWPWRITE_ECC -// -//***************************************************************************** -// Field: [31:24] ECCBYTES07_00 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_M 0xFF000000 -#define FLASH_FWPWRITE_ECC_ECCBYTES07_00_S 24 - -// Field: [23:16] ECCBYTES15_08 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_M 0x00FF0000 -#define FLASH_FWPWRITE_ECC_ECCBYTES15_08_S 16 - -// Field: [15:8] ECCBYTES23_16 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_M 0x0000FF00 -#define FLASH_FWPWRITE_ECC_ECCBYTES23_16_S 8 - -// Field: [7:0] ECCBYTES31_24 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_W 8 -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_M 0x000000FF -#define FLASH_FWPWRITE_ECC_ECCBYTES31_24_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSWSTAT -// -//***************************************************************************** -// Field: [0] SAFELV -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSWSTAT_SAFELV 0x00000001 -#define FLASH_FSWSTAT_SAFELV_BITN 0 -#define FLASH_FSWSTAT_SAFELV_M 0x00000001 -#define FLASH_FSWSTAT_SAFELV_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_GLBCTL -// -//***************************************************************************** -// Field: [0] CLKSEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_GLBCTL_CLKSEL 0x00000001 -#define FLASH_FSM_GLBCTL_CLKSEL_BITN 0 -#define FLASH_FSM_GLBCTL_CLKSEL_M 0x00000001 -#define FLASH_FSM_GLBCTL_CLKSEL_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_STATE -// -//***************************************************************************** -// Field: [11] CTRLENZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_CTRLENZ 0x00000800 -#define FLASH_FSM_STATE_CTRLENZ_BITN 11 -#define FLASH_FSM_STATE_CTRLENZ_M 0x00000800 -#define FLASH_FSM_STATE_CTRLENZ_S 11 - -// Field: [10] EXECUTEZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_EXECUTEZ 0x00000400 -#define FLASH_FSM_STATE_EXECUTEZ_BITN 10 -#define FLASH_FSM_STATE_EXECUTEZ_M 0x00000400 -#define FLASH_FSM_STATE_EXECUTEZ_S 10 - -// Field: [8] FSM_ACT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_FSM_ACT 0x00000100 -#define FLASH_FSM_STATE_FSM_ACT_BITN 8 -#define FLASH_FSM_STATE_FSM_ACT_M 0x00000100 -#define FLASH_FSM_STATE_FSM_ACT_S 8 - -// Field: [7] TIOTP_ACT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_TIOTP_ACT 0x00000080 -#define FLASH_FSM_STATE_TIOTP_ACT_BITN 7 -#define FLASH_FSM_STATE_TIOTP_ACT_M 0x00000080 -#define FLASH_FSM_STATE_TIOTP_ACT_S 7 - -// Field: [6] OTP_ACT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STATE_OTP_ACT 0x00000040 -#define FLASH_FSM_STATE_OTP_ACT_BITN 6 -#define FLASH_FSM_STATE_OTP_ACT_M 0x00000040 -#define FLASH_FSM_STATE_OTP_ACT_S 6 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_STAT -// -//***************************************************************************** -// Field: [2] NON_OP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_NON_OP 0x00000004 -#define FLASH_FSM_STAT_NON_OP_BITN 2 -#define FLASH_FSM_STAT_NON_OP_M 0x00000004 -#define FLASH_FSM_STAT_NON_OP_S 2 - -// Field: [1] OVR_PUL_CNT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_OVR_PUL_CNT 0x00000002 -#define FLASH_FSM_STAT_OVR_PUL_CNT_BITN 1 -#define FLASH_FSM_STAT_OVR_PUL_CNT_M 0x00000002 -#define FLASH_FSM_STAT_OVR_PUL_CNT_S 1 - -// Field: [0] INV_DAT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STAT_INV_DAT 0x00000001 -#define FLASH_FSM_STAT_INV_DAT_BITN 0 -#define FLASH_FSM_STAT_INV_DAT_M 0x00000001 -#define FLASH_FSM_STAT_INV_DAT_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_CMD -// -//***************************************************************************** -// Field: [5:0] FSMCMD -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_CMD_FSMCMD_W 6 -#define FLASH_FSM_CMD_FSMCMD_M 0x0000003F -#define FLASH_FSM_CMD_FSMCMD_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PE_OSU -// -//***************************************************************************** -// Field: [15:8] PGM_OSU -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_OSU_PGM_OSU_W 8 -#define FLASH_FSM_PE_OSU_PGM_OSU_M 0x0000FF00 -#define FLASH_FSM_PE_OSU_PGM_OSU_S 8 - -// Field: [7:0] ERA_OSU -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_OSU_ERA_OSU_W 8 -#define FLASH_FSM_PE_OSU_ERA_OSU_M 0x000000FF -#define FLASH_FSM_PE_OSU_ERA_OSU_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_VSTAT -// -//***************************************************************************** -// Field: [15:12] VSTAT_CNT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_VSTAT_VSTAT_CNT_W 4 -#define FLASH_FSM_VSTAT_VSTAT_CNT_M 0x0000F000 -#define FLASH_FSM_VSTAT_VSTAT_CNT_S 12 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PE_VSU -// -//***************************************************************************** -// Field: [15:8] PGM_VSU -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VSU_PGM_VSU_W 8 -#define FLASH_FSM_PE_VSU_PGM_VSU_M 0x0000FF00 -#define FLASH_FSM_PE_VSU_PGM_VSU_S 8 - -// Field: [7:0] ERA_VSU -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VSU_ERA_VSU_W 8 -#define FLASH_FSM_PE_VSU_ERA_VSU_M 0x000000FF -#define FLASH_FSM_PE_VSU_ERA_VSU_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_CMP_VSU -// -//***************************************************************************** -// Field: [15:12] ADD_EXZ -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_CMP_VSU_ADD_EXZ_W 4 -#define FLASH_FSM_CMP_VSU_ADD_EXZ_M 0x0000F000 -#define FLASH_FSM_CMP_VSU_ADD_EXZ_S 12 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_EX_VAL -// -//***************************************************************************** -// Field: [15:8] REP_VSU -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_EX_VAL_REP_VSU_W 8 -#define FLASH_FSM_EX_VAL_REP_VSU_M 0x0000FF00 -#define FLASH_FSM_EX_VAL_REP_VSU_S 8 - -// Field: [7:0] EXE_VALD -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_EX_VAL_EXE_VALD_W 8 -#define FLASH_FSM_EX_VAL_EXE_VALD_M 0x000000FF -#define FLASH_FSM_EX_VAL_EXE_VALD_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_RD_H -// -//***************************************************************************** -// Field: [7:0] RD_H -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_RD_H_RD_H_W 8 -#define FLASH_FSM_RD_H_RD_H_M 0x000000FF -#define FLASH_FSM_RD_H_RD_H_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_P_OH -// -//***************************************************************************** -// Field: [15:8] PGM_OH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_P_OH_PGM_OH_W 8 -#define FLASH_FSM_P_OH_PGM_OH_M 0x0000FF00 -#define FLASH_FSM_P_OH_PGM_OH_S 8 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ERA_OH -// -//***************************************************************************** -// Field: [15:0] ERA_OH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_OH_ERA_OH_W 16 -#define FLASH_FSM_ERA_OH_ERA_OH_M 0x0000FFFF -#define FLASH_FSM_ERA_OH_ERA_OH_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_SAV_PPUL -// -//***************************************************************************** -// Field: [11:0] SAV_P_PUL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_W 12 -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_M 0x00000FFF -#define FLASH_FSM_SAV_PPUL_SAV_P_PUL_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PE_VH -// -//***************************************************************************** -// Field: [15:8] PGM_VH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PE_VH_PGM_VH_W 8 -#define FLASH_FSM_PE_VH_PGM_VH_M 0x0000FF00 -#define FLASH_FSM_PE_VH_PGM_VH_S 8 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PRG_PW -// -//***************************************************************************** -// Field: [15:0] PROG_PUL_WIDTH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_W 16 -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_M 0x0000FFFF -#define FLASH_FSM_PRG_PW_PROG_PUL_WIDTH_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ERA_PW -// -//***************************************************************************** -// Field: [31:0] FSM_ERA_PW -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_W 32 -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_M 0xFFFFFFFF -#define FLASH_FSM_ERA_PW_FSM_ERA_PW_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_SAV_ERA_PUL -// -//***************************************************************************** -// Field: [11:0] SAV_ERA_PUL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_W 12 -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_M 0x00000FFF -#define FLASH_FSM_SAV_ERA_PUL_SAV_ERA_PUL_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_TIMER -// -//***************************************************************************** -// Field: [31:0] FSM_TIMER -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_TIMER_FSM_TIMER_W 32 -#define FLASH_FSM_TIMER_FSM_TIMER_M 0xFFFFFFFF -#define FLASH_FSM_TIMER_FSM_TIMER_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_MODE -// -//***************************************************************************** -// Field: [19:18] RDV_SUBMODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_RDV_SUBMODE_W 2 -#define FLASH_FSM_MODE_RDV_SUBMODE_M 0x000C0000 -#define FLASH_FSM_MODE_RDV_SUBMODE_S 18 - -// Field: [17:16] PGM_SUBMODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_PGM_SUBMODE_W 2 -#define FLASH_FSM_MODE_PGM_SUBMODE_M 0x00030000 -#define FLASH_FSM_MODE_PGM_SUBMODE_S 16 - -// Field: [15:14] ERA_SUBMODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_ERA_SUBMODE_W 2 -#define FLASH_FSM_MODE_ERA_SUBMODE_M 0x0000C000 -#define FLASH_FSM_MODE_ERA_SUBMODE_S 14 - -// Field: [13:12] SUBMODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SUBMODE_W 2 -#define FLASH_FSM_MODE_SUBMODE_M 0x00003000 -#define FLASH_FSM_MODE_SUBMODE_S 12 - -// Field: [11:9] SAV_PGM_CMD -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SAV_PGM_CMD_W 3 -#define FLASH_FSM_MODE_SAV_PGM_CMD_M 0x00000E00 -#define FLASH_FSM_MODE_SAV_PGM_CMD_S 9 - -// Field: [8:6] SAV_ERA_MODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_SAV_ERA_MODE_W 3 -#define FLASH_FSM_MODE_SAV_ERA_MODE_M 0x000001C0 -#define FLASH_FSM_MODE_SAV_ERA_MODE_S 6 - -// Field: [5:3] MODE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_MODE_W 3 -#define FLASH_FSM_MODE_MODE_M 0x00000038 -#define FLASH_FSM_MODE_MODE_S 3 - -// Field: [2:0] CMD -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_MODE_CMD_W 3 -#define FLASH_FSM_MODE_CMD_M 0x00000007 -#define FLASH_FSM_MODE_CMD_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PGM -// -//***************************************************************************** -// Field: [25:23] PGM_BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_PGM_BANK_W 3 -#define FLASH_FSM_PGM_PGM_BANK_M 0x03800000 -#define FLASH_FSM_PGM_PGM_BANK_S 23 - -// Field: [22:0] PGM_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_PGM_ADDR_W 23 -#define FLASH_FSM_PGM_PGM_ADDR_M 0x007FFFFF -#define FLASH_FSM_PGM_PGM_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ERA -// -//***************************************************************************** -// Field: [25:23] ERA_BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_ERA_BANK_W 3 -#define FLASH_FSM_ERA_ERA_BANK_M 0x03800000 -#define FLASH_FSM_ERA_ERA_BANK_S 23 - -// Field: [22:0] ERA_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_ERA_ADDR_W 23 -#define FLASH_FSM_ERA_ERA_ADDR_M 0x007FFFFF -#define FLASH_FSM_ERA_ERA_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PRG_PUL -// -//***************************************************************************** -// Field: [19:16] BEG_EC_LEVEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_W 4 -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_M 0x000F0000 -#define FLASH_FSM_PRG_PUL_BEG_EC_LEVEL_S 16 - -// Field: [11:0] MAX_PRG_PUL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_W 12 -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_M 0x00000FFF -#define FLASH_FSM_PRG_PUL_MAX_PRG_PUL_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ERA_PUL -// -//***************************************************************************** -// Field: [19:16] MAX_EC_LEVEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_W 4 -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_M 0x000F0000 -#define FLASH_FSM_ERA_PUL_MAX_EC_LEVEL_S 16 - -// Field: [11:0] MAX_ERA_PUL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_W 12 -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_M 0x00000FFF -#define FLASH_FSM_ERA_PUL_MAX_ERA_PUL_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_STEP_SIZE -// -//***************************************************************************** -// Field: [24:16] EC_STEP_SIZE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_W 9 -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_M 0x01FF0000 -#define FLASH_FSM_STEP_SIZE_EC_STEP_SIZE_S 16 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PUL_CNTR -// -//***************************************************************************** -// Field: [24:16] CUR_EC_LEVEL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_W 9 -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_M 0x01FF0000 -#define FLASH_FSM_PUL_CNTR_CUR_EC_LEVEL_S 16 - -// Field: [11:0] PUL_CNTR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_W 12 -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_M 0x00000FFF -#define FLASH_FSM_PUL_CNTR_PUL_CNTR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_EC_STEP_HEIGHT -// -//***************************************************************************** -// Field: [3:0] EC_STEP_HEIGHT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_W 4 -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_M 0x0000000F -#define FLASH_FSM_EC_STEP_HEIGHT_EC_STEP_HEIGHT_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ST_MACHINE -// -//***************************************************************************** -// Field: [23] DO_PRECOND -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DO_PRECOND 0x00800000 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_BITN 23 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_M 0x00800000 -#define FLASH_FSM_ST_MACHINE_DO_PRECOND_S 23 - -// Field: [22] FSM_INT_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN 0x00400000 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_BITN 22 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_M 0x00400000 -#define FLASH_FSM_ST_MACHINE_FSM_INT_EN_S 22 - -// Field: [21] ALL_BANKS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_ALL_BANKS 0x00200000 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_BITN 21 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_M 0x00200000 -#define FLASH_FSM_ST_MACHINE_ALL_BANKS_S 21 - -// Field: [20] CMPV_ALLOWED -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED 0x00100000 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_BITN 20 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_M 0x00100000 -#define FLASH_FSM_ST_MACHINE_CMPV_ALLOWED_S 20 - -// Field: [19] RANDOM -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RANDOM 0x00080000 -#define FLASH_FSM_ST_MACHINE_RANDOM_BITN 19 -#define FLASH_FSM_ST_MACHINE_RANDOM_M 0x00080000 -#define FLASH_FSM_ST_MACHINE_RANDOM_S 19 - -// Field: [18] RV_SEC_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN 0x00040000 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_BITN 18 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_M 0x00040000 -#define FLASH_FSM_ST_MACHINE_RV_SEC_EN_S 18 - -// Field: [17] RV_RES -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_RES 0x00020000 -#define FLASH_FSM_ST_MACHINE_RV_RES_BITN 17 -#define FLASH_FSM_ST_MACHINE_RV_RES_M 0x00020000 -#define FLASH_FSM_ST_MACHINE_RV_RES_S 17 - -// Field: [16] RV_INT_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_RV_INT_EN 0x00010000 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_BITN 16 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_M 0x00010000 -#define FLASH_FSM_ST_MACHINE_RV_INT_EN_S 16 - -// Field: [14] ONE_TIME_GOOD -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD 0x00004000 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_BITN 14 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_M 0x00004000 -#define FLASH_FSM_ST_MACHINE_ONE_TIME_GOOD_S 14 - -// Field: [11] DO_REDU_COL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL 0x00000800 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_BITN 11 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_M 0x00000800 -#define FLASH_FSM_ST_MACHINE_DO_REDU_COL_S 11 - -// Field: [10:7] DBG_SHORT_ROW -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_W 4 -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_M 0x00000780 -#define FLASH_FSM_ST_MACHINE_DBG_SHORT_ROW_S 7 - -// Field: [5] PGM_SEC_COF_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN 0x00000020 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_BITN 5 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_M 0x00000020 -#define FLASH_FSM_ST_MACHINE_PGM_SEC_COF_EN_S 5 - -// Field: [4] PREC_STOP_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN 0x00000010 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_BITN 4 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_M 0x00000010 -#define FLASH_FSM_ST_MACHINE_PREC_STOP_EN_S 4 - -// Field: [3] DIS_TST_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN 0x00000008 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_BITN 3 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_M 0x00000008 -#define FLASH_FSM_ST_MACHINE_DIS_TST_EN_S 3 - -// Field: [2] CMD_EN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_CMD_EN 0x00000004 -#define FLASH_FSM_ST_MACHINE_CMD_EN_BITN 2 -#define FLASH_FSM_ST_MACHINE_CMD_EN_M 0x00000004 -#define FLASH_FSM_ST_MACHINE_CMD_EN_S 2 - -// Field: [1] INV_DATA -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_INV_DATA 0x00000002 -#define FLASH_FSM_ST_MACHINE_INV_DATA_BITN 1 -#define FLASH_FSM_ST_MACHINE_INV_DATA_M 0x00000002 -#define FLASH_FSM_ST_MACHINE_INV_DATA_S 1 - -// Field: [0] OVERRIDE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ST_MACHINE_OVERRIDE 0x00000001 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_BITN 0 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_M 0x00000001 -#define FLASH_FSM_ST_MACHINE_OVERRIDE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_FLES -// -//***************************************************************************** -// Field: [11:8] BLK_TIOTP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_FLES_BLK_TIOTP_W 4 -#define FLASH_FSM_FLES_BLK_TIOTP_M 0x00000F00 -#define FLASH_FSM_FLES_BLK_TIOTP_S 8 - -// Field: [7:0] BLK_OTP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_FLES_BLK_OTP_W 8 -#define FLASH_FSM_FLES_BLK_OTP_M 0x000000FF -#define FLASH_FSM_FLES_BLK_OTP_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_WR_ENA -// -//***************************************************************************** -// Field: [2:0] WR_ENA -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_WR_ENA_WR_ENA_W 3 -#define FLASH_FSM_WR_ENA_WR_ENA_M 0x00000007 -#define FLASH_FSM_WR_ENA_WR_ENA_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ACC_PP -// -//***************************************************************************** -// Field: [31:0] FSM_ACC_PP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_W 32 -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_M 0xFFFFFFFF -#define FLASH_FSM_ACC_PP_FSM_ACC_PP_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ACC_EP -// -//***************************************************************************** -// Field: [15:0] ACC_EP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ACC_EP_ACC_EP_W 16 -#define FLASH_FSM_ACC_EP_ACC_EP_M 0x0000FFFF -#define FLASH_FSM_ACC_EP_ACC_EP_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ADDR -// -//***************************************************************************** -// Field: [30:28] BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ADDR_BANK_W 3 -#define FLASH_FSM_ADDR_BANK_M 0x70000000 -#define FLASH_FSM_ADDR_BANK_S 28 - -// Field: [27:0] CUR_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ADDR_CUR_ADDR_W 28 -#define FLASH_FSM_ADDR_CUR_ADDR_M 0x0FFFFFFF -#define FLASH_FSM_ADDR_CUR_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_SECTOR -// -//***************************************************************************** -// Field: [31:16] SECT_ERASED -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SECT_ERASED_W 16 -#define FLASH_FSM_SECTOR_SECT_ERASED_M 0xFFFF0000 -#define FLASH_FSM_SECTOR_SECT_ERASED_S 16 - -// Field: [15:8] FSM_SECTOR_EXTENSION -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_W 8 -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_M 0x0000FF00 -#define FLASH_FSM_SECTOR_FSM_SECTOR_EXTENSION_S 8 - -// Field: [7:4] SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SECTOR_W 4 -#define FLASH_FSM_SECTOR_SECTOR_M 0x000000F0 -#define FLASH_FSM_SECTOR_SECTOR_S 4 - -// Field: [3:0] SEC_OUT -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR_SEC_OUT_W 4 -#define FLASH_FSM_SECTOR_SEC_OUT_M 0x0000000F -#define FLASH_FSM_SECTOR_SEC_OUT_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FMC_REV_ID -// -//***************************************************************************** -// Field: [31:12] MOD_VERSION -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMC_REV_ID_MOD_VERSION_W 20 -#define FLASH_FMC_REV_ID_MOD_VERSION_M 0xFFFFF000 -#define FLASH_FMC_REV_ID_MOD_VERSION_S 12 - -// Field: [11:0] CONFIG_CRC -// -// Internal. Only to be used through TI provided API. -#define FLASH_FMC_REV_ID_CONFIG_CRC_W 12 -#define FLASH_FMC_REV_ID_CONFIG_CRC_M 0x00000FFF -#define FLASH_FMC_REV_ID_CONFIG_CRC_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_ERR_ADDR -// -//***************************************************************************** -// Field: [31:8] FSM_ERR_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_W 24 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_M 0xFFFFFF00 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_ADDR_S 8 - -// Field: [3:0] FSM_ERR_BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_W 4 -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_M 0x0000000F -#define FLASH_FSM_ERR_ADDR_FSM_ERR_BANK_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PGM_MAXPUL -// -//***************************************************************************** -// Field: [11:0] FSM_PGM_MAXPUL -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_W 12 -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_M 0x00000FFF -#define FLASH_FSM_PGM_MAXPUL_FSM_PGM_MAXPUL_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_EXECUTE -// -//***************************************************************************** -// Field: [19:16] SUSPEND_NOW -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_W 4 -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_M 0x000F0000 -#define FLASH_FSM_EXECUTE_SUSPEND_NOW_S 16 - -// Field: [4:0] FSMEXECUTE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_EXECUTE_FSMEXECUTE_W 5 -#define FLASH_FSM_EXECUTE_FSMEXECUTE_M 0x0000001F -#define FLASH_FSM_EXECUTE_FSMEXECUTE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_SECTOR1 -// -//***************************************************************************** -// Field: [31:0] FSM_SECTOR1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_W 32 -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_M 0xFFFFFFFF -#define FLASH_FSM_SECTOR1_FSM_SECTOR1_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_SECTOR2 -// -//***************************************************************************** -// Field: [31:0] FSM_SECTOR2 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_W 32 -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_M 0xFFFFFFFF -#define FLASH_FSM_SECTOR2_FSM_SECTOR2_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_BSLE0 -// -//***************************************************************************** -// Field: [31:0] FSM_BSLE0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLE0_FSM_BSLE0_W 32 -#define FLASH_FSM_BSLE0_FSM_BSLE0_M 0xFFFFFFFF -#define FLASH_FSM_BSLE0_FSM_BSLE0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_BSLE1 -// -//***************************************************************************** -// Field: [31:0] FSM_BSL1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLE1_FSM_BSL1_W 32 -#define FLASH_FSM_BSLE1_FSM_BSL1_M 0xFFFFFFFF -#define FLASH_FSM_BSLE1_FSM_BSL1_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_BSLP0 -// -//***************************************************************************** -// Field: [31:0] FSM_BSLP0 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLP0_FSM_BSLP0_W 32 -#define FLASH_FSM_BSLP0_FSM_BSLP0_M 0xFFFFFFFF -#define FLASH_FSM_BSLP0_FSM_BSLP0_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_BSLP1 -// -//***************************************************************************** -// Field: [31:0] FSM_BSL1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FSM_BSLP1_FSM_BSL1_W 32 -#define FLASH_FSM_BSLP1_FSM_BSL1_M 0xFFFFFFFF -#define FLASH_FSM_BSLP1_FSM_BSL1_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FSM_PGM128 -// -//***************************************************************************** -// Field: [0] EN_PGM128 -// -// 1: Enables 128-bit wide programming. This mode requires programming supply -// voltage to be greater than 2.5v at the Flash Pump. The primary use case for -// this mode is manufacturing test for test time reduction. -// -// 0: 64-bit wide programming. Valid at any programming voltage. A 128-bit -// word is divided into two 64-bit words for programming. [default] -// -// This register is write protected with the FSM_WR_ENA register. -#define FLASH_FSM_PGM128_EN_PGM128 0x00000001 -#define FLASH_FSM_PGM128_EN_PGM128_BITN 0 -#define FLASH_FSM_PGM128_EN_PGM128_M 0x00000001 -#define FLASH_FSM_PGM128_EN_PGM128_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_BANK -// -//***************************************************************************** -// Field: [31:20] EE_BANK_WIDTH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_W 12 -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_M 0xFFF00000 -#define FLASH_FCFG_BANK_EE_BANK_WIDTH_S 20 - -// Field: [19:16] EE_NUM_BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_EE_NUM_BANK_W 4 -#define FLASH_FCFG_BANK_EE_NUM_BANK_M 0x000F0000 -#define FLASH_FCFG_BANK_EE_NUM_BANK_S 16 - -// Field: [15:4] MAIN_BANK_WIDTH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_W 12 -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_M 0x0000FFF0 -#define FLASH_FCFG_BANK_MAIN_BANK_WIDTH_S 4 - -// Field: [3:0] MAIN_NUM_BANK -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_W 4 -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_M 0x0000000F -#define FLASH_FCFG_BANK_MAIN_NUM_BANK_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_WRAPPER -// -//***************************************************************************** -// Field: [31:24] FAMILY_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_W 8 -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_M 0xFF000000 -#define FLASH_FCFG_WRAPPER_FAMILY_TYPE_S 24 - -// Field: [20] MEM_MAP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_MEM_MAP 0x00100000 -#define FLASH_FCFG_WRAPPER_MEM_MAP_BITN 20 -#define FLASH_FCFG_WRAPPER_MEM_MAP_M 0x00100000 -#define FLASH_FCFG_WRAPPER_MEM_MAP_S 20 - -// Field: [19:16] CPU2 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_CPU2_W 4 -#define FLASH_FCFG_WRAPPER_CPU2_M 0x000F0000 -#define FLASH_FCFG_WRAPPER_CPU2_S 16 - -// Field: [15:12] EE_IN_MAIN -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_W 4 -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_M 0x0000F000 -#define FLASH_FCFG_WRAPPER_EE_IN_MAIN_S 12 - -// Field: [11] ROM -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_ROM 0x00000800 -#define FLASH_FCFG_WRAPPER_ROM_BITN 11 -#define FLASH_FCFG_WRAPPER_ROM_M 0x00000800 -#define FLASH_FCFG_WRAPPER_ROM_S 11 - -// Field: [10] IFLUSH -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_IFLUSH 0x00000400 -#define FLASH_FCFG_WRAPPER_IFLUSH_BITN 10 -#define FLASH_FCFG_WRAPPER_IFLUSH_M 0x00000400 -#define FLASH_FCFG_WRAPPER_IFLUSH_S 10 - -// Field: [9] SIL3 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_SIL3 0x00000200 -#define FLASH_FCFG_WRAPPER_SIL3_BITN 9 -#define FLASH_FCFG_WRAPPER_SIL3_M 0x00000200 -#define FLASH_FCFG_WRAPPER_SIL3_S 9 - -// Field: [8] ECCA -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_ECCA 0x00000100 -#define FLASH_FCFG_WRAPPER_ECCA_BITN 8 -#define FLASH_FCFG_WRAPPER_ECCA_M 0x00000100 -#define FLASH_FCFG_WRAPPER_ECCA_S 8 - -// Field: [7:6] AUTO_SUSP -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_W 2 -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_M 0x000000C0 -#define FLASH_FCFG_WRAPPER_AUTO_SUSP_S 6 - -// Field: [5:4] UERR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_UERR_W 2 -#define FLASH_FCFG_WRAPPER_UERR_M 0x00000030 -#define FLASH_FCFG_WRAPPER_UERR_S 4 - -// Field: [3:0] CPU_TYPE1 -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_W 4 -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_M 0x0000000F -#define FLASH_FCFG_WRAPPER_CPU_TYPE1_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_BNK_TYPE -// -//***************************************************************************** -// Field: [31:28] B7_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_M 0xF0000000 -#define FLASH_FCFG_BNK_TYPE_B7_TYPE_S 28 - -// Field: [27:24] B6_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_M 0x0F000000 -#define FLASH_FCFG_BNK_TYPE_B6_TYPE_S 24 - -// Field: [23:20] B5_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_M 0x00F00000 -#define FLASH_FCFG_BNK_TYPE_B5_TYPE_S 20 - -// Field: [19:16] B4_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_M 0x000F0000 -#define FLASH_FCFG_BNK_TYPE_B4_TYPE_S 16 - -// Field: [15:12] B3_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_M 0x0000F000 -#define FLASH_FCFG_BNK_TYPE_B3_TYPE_S 12 - -// Field: [11:8] B2_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_M 0x00000F00 -#define FLASH_FCFG_BNK_TYPE_B2_TYPE_S 8 - -// Field: [7:4] B1_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_M 0x000000F0 -#define FLASH_FCFG_BNK_TYPE_B1_TYPE_S 4 - -// Field: [3:0] B0_TYPE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_W 4 -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_M 0x0000000F -#define FLASH_FCFG_BNK_TYPE_B0_TYPE_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B0_START -// -//***************************************************************************** -// Field: [31:28] B0_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_W 4 -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B0_START_B0_MAX_SECTOR_S 28 - -// Field: [27:24] B0_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_W 4 -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B0_START_B0_MUX_FACTOR_S 24 - -// Field: [23:0] B0_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_START_B0_START_ADDR_W 24 -#define FLASH_FCFG_B0_START_B0_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B0_START_B0_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B1_START -// -//***************************************************************************** -// Field: [31:28] B1_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_W 4 -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B1_START_B1_MAX_SECTOR_S 28 - -// Field: [27:24] B1_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_W 4 -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B1_START_B1_MUX_FACTOR_S 24 - -// Field: [23:0] B1_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B1_START_B1_START_ADDR_W 24 -#define FLASH_FCFG_B1_START_B1_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B1_START_B1_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B2_START -// -//***************************************************************************** -// Field: [31:28] B2_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_W 4 -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B2_START_B2_MAX_SECTOR_S 28 - -// Field: [27:24] B2_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_W 4 -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B2_START_B2_MUX_FACTOR_S 24 - -// Field: [23:0] B2_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B2_START_B2_START_ADDR_W 24 -#define FLASH_FCFG_B2_START_B2_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B2_START_B2_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B3_START -// -//***************************************************************************** -// Field: [31:28] B3_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_W 4 -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B3_START_B3_MAX_SECTOR_S 28 - -// Field: [27:24] B3_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_W 4 -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B3_START_B3_MUX_FACTOR_S 24 - -// Field: [23:0] B3_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B3_START_B3_START_ADDR_W 24 -#define FLASH_FCFG_B3_START_B3_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B3_START_B3_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B4_START -// -//***************************************************************************** -// Field: [31:28] B4_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_W 4 -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B4_START_B4_MAX_SECTOR_S 28 - -// Field: [27:24] B4_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_W 4 -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B4_START_B4_MUX_FACTOR_S 24 - -// Field: [23:0] B4_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B4_START_B4_START_ADDR_W 24 -#define FLASH_FCFG_B4_START_B4_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B4_START_B4_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B5_START -// -//***************************************************************************** -// Field: [31:28] B5_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_W 4 -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B5_START_B5_MAX_SECTOR_S 28 - -// Field: [27:24] B5_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_W 4 -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B5_START_B5_MUX_FACTOR_S 24 - -// Field: [23:0] B5_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B5_START_B5_START_ADDR_W 24 -#define FLASH_FCFG_B5_START_B5_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B5_START_B5_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B6_START -// -//***************************************************************************** -// Field: [31:28] B6_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_W 4 -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B6_START_B6_MAX_SECTOR_S 28 - -// Field: [27:24] B6_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_W 4 -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B6_START_B6_MUX_FACTOR_S 24 - -// Field: [23:0] B6_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B6_START_B6_START_ADDR_W 24 -#define FLASH_FCFG_B6_START_B6_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B6_START_B6_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B7_START -// -//***************************************************************************** -// Field: [31:28] B7_MAX_SECTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_W 4 -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_M 0xF0000000 -#define FLASH_FCFG_B7_START_B7_MAX_SECTOR_S 28 - -// Field: [27:24] B7_MUX_FACTOR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_W 4 -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_M 0x0F000000 -#define FLASH_FCFG_B7_START_B7_MUX_FACTOR_S 24 - -// Field: [23:0] B7_START_ADDR -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B7_START_B7_START_ADDR_W 24 -#define FLASH_FCFG_B7_START_B7_START_ADDR_M 0x00FFFFFF -#define FLASH_FCFG_B7_START_B7_START_ADDR_S 0 - -//***************************************************************************** -// -// Register: FLASH_O_FCFG_B0_SSIZE0 -// -//***************************************************************************** -// Field: [27:16] B0_NUM_SECTORS -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_W 12 -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_M 0x0FFF0000 -#define FLASH_FCFG_B0_SSIZE0_B0_NUM_SECTORS_S 16 - -// Field: [3:0] B0_SECT_SIZE -// -// Internal. Only to be used through TI provided API. -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_W 4 -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_M 0x0000000F -#define FLASH_FCFG_B0_SSIZE0_B0_SECT_SIZE_S 0 - - -#endif // __FLASH__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h deleted file mode 100644 index 8ec4bfb7bea..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpio.h +++ /dev/null @@ -1,2247 +0,0 @@ -/****************************************************************************** -* Filename: hw_gpio_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// GPIO component -// -//***************************************************************************** -// Data Out 0 to 3 -#define GPIO_O_DOUT3_0 0x00000000 - -// Data Out 4 to 7 -#define GPIO_O_DOUT7_4 0x00000004 - -// Data Out 8 to 11 -#define GPIO_O_DOUT11_8 0x00000008 - -// Data Out 12 to 15 -#define GPIO_O_DOUT15_12 0x0000000C - -// Data Out 16 to 19 -#define GPIO_O_DOUT19_16 0x00000010 - -// Data Out 20 to 23 -#define GPIO_O_DOUT23_20 0x00000014 - -// Data Out 24 to 27 -#define GPIO_O_DOUT27_24 0x00000018 - -// Data Out 28 to 31 -#define GPIO_O_DOUT31_28 0x0000001C - -// Data Output for DIO 0 to 31 -#define GPIO_O_DOUT31_0 0x00000080 - -// Data Out Set -#define GPIO_O_DOUTSET31_0 0x00000090 - -// Data Out Clear -#define GPIO_O_DOUTCLR31_0 0x000000A0 - -// Data Out Toggle -#define GPIO_O_DOUTTGL31_0 0x000000B0 - -// Data Input from DIO 0 to 31 -#define GPIO_O_DIN31_0 0x000000C0 - -// Data Output Enable for DIO 0 to 31 -#define GPIO_O_DOE31_0 0x000000D0 - -// Event Register for DIO 0 to 31 -#define GPIO_O_EVFLAGS31_0 0x000000E0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT3_0 -// -//***************************************************************************** -// Field: [24] DIO3 -// -// Sets the state of the pin that is configured as DIO#3, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO3 0x01000000 -#define GPIO_DOUT3_0_DIO3_BITN 24 -#define GPIO_DOUT3_0_DIO3_M 0x01000000 -#define GPIO_DOUT3_0_DIO3_S 24 - -// Field: [16] DIO2 -// -// Sets the state of the pin that is configured as DIO#2, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO2 0x00010000 -#define GPIO_DOUT3_0_DIO2_BITN 16 -#define GPIO_DOUT3_0_DIO2_M 0x00010000 -#define GPIO_DOUT3_0_DIO2_S 16 - -// Field: [8] DIO1 -// -// Sets the state of the pin that is configured as DIO#1, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO1 0x00000100 -#define GPIO_DOUT3_0_DIO1_BITN 8 -#define GPIO_DOUT3_0_DIO1_M 0x00000100 -#define GPIO_DOUT3_0_DIO1_S 8 - -// Field: [0] DIO0 -// -// Sets the state of the pin that is configured as DIO#0, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT3_0_DIO0 0x00000001 -#define GPIO_DOUT3_0_DIO0_BITN 0 -#define GPIO_DOUT3_0_DIO0_M 0x00000001 -#define GPIO_DOUT3_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT7_4 -// -//***************************************************************************** -// Field: [24] DIO7 -// -// Sets the state of the pin that is configured as DIO#7, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO7 0x01000000 -#define GPIO_DOUT7_4_DIO7_BITN 24 -#define GPIO_DOUT7_4_DIO7_M 0x01000000 -#define GPIO_DOUT7_4_DIO7_S 24 - -// Field: [16] DIO6 -// -// Sets the state of the pin that is configured as DIO#6, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO6 0x00010000 -#define GPIO_DOUT7_4_DIO6_BITN 16 -#define GPIO_DOUT7_4_DIO6_M 0x00010000 -#define GPIO_DOUT7_4_DIO6_S 16 - -// Field: [8] DIO5 -// -// Sets the state of the pin that is configured as DIO#5, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO5 0x00000100 -#define GPIO_DOUT7_4_DIO5_BITN 8 -#define GPIO_DOUT7_4_DIO5_M 0x00000100 -#define GPIO_DOUT7_4_DIO5_S 8 - -// Field: [0] DIO4 -// -// Sets the state of the pin that is configured as DIO#4, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT7_4_DIO4 0x00000001 -#define GPIO_DOUT7_4_DIO4_BITN 0 -#define GPIO_DOUT7_4_DIO4_M 0x00000001 -#define GPIO_DOUT7_4_DIO4_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT11_8 -// -//***************************************************************************** -// Field: [24] DIO11 -// -// Sets the state of the pin that is configured as DIO#11, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO11 0x01000000 -#define GPIO_DOUT11_8_DIO11_BITN 24 -#define GPIO_DOUT11_8_DIO11_M 0x01000000 -#define GPIO_DOUT11_8_DIO11_S 24 - -// Field: [16] DIO10 -// -// Sets the state of the pin that is configured as DIO#10, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO10 0x00010000 -#define GPIO_DOUT11_8_DIO10_BITN 16 -#define GPIO_DOUT11_8_DIO10_M 0x00010000 -#define GPIO_DOUT11_8_DIO10_S 16 - -// Field: [8] DIO9 -// -// Sets the state of the pin that is configured as DIO#9, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO9 0x00000100 -#define GPIO_DOUT11_8_DIO9_BITN 8 -#define GPIO_DOUT11_8_DIO9_M 0x00000100 -#define GPIO_DOUT11_8_DIO9_S 8 - -// Field: [0] DIO8 -// -// Sets the state of the pin that is configured as DIO#8, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT11_8_DIO8 0x00000001 -#define GPIO_DOUT11_8_DIO8_BITN 0 -#define GPIO_DOUT11_8_DIO8_M 0x00000001 -#define GPIO_DOUT11_8_DIO8_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT15_12 -// -//***************************************************************************** -// Field: [24] DIO15 -// -// Sets the state of the pin that is configured as DIO#15, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO15 0x01000000 -#define GPIO_DOUT15_12_DIO15_BITN 24 -#define GPIO_DOUT15_12_DIO15_M 0x01000000 -#define GPIO_DOUT15_12_DIO15_S 24 - -// Field: [16] DIO14 -// -// Sets the state of the pin that is configured as DIO#14, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO14 0x00010000 -#define GPIO_DOUT15_12_DIO14_BITN 16 -#define GPIO_DOUT15_12_DIO14_M 0x00010000 -#define GPIO_DOUT15_12_DIO14_S 16 - -// Field: [8] DIO13 -// -// Sets the state of the pin that is configured as DIO#13, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO13 0x00000100 -#define GPIO_DOUT15_12_DIO13_BITN 8 -#define GPIO_DOUT15_12_DIO13_M 0x00000100 -#define GPIO_DOUT15_12_DIO13_S 8 - -// Field: [0] DIO12 -// -// Sets the state of the pin that is configured as DIO#12, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT15_12_DIO12 0x00000001 -#define GPIO_DOUT15_12_DIO12_BITN 0 -#define GPIO_DOUT15_12_DIO12_M 0x00000001 -#define GPIO_DOUT15_12_DIO12_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT19_16 -// -//***************************************************************************** -// Field: [24] DIO19 -// -// Sets the state of the pin that is configured as DIO#19, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO19 0x01000000 -#define GPIO_DOUT19_16_DIO19_BITN 24 -#define GPIO_DOUT19_16_DIO19_M 0x01000000 -#define GPIO_DOUT19_16_DIO19_S 24 - -// Field: [16] DIO18 -// -// Sets the state of the pin that is configured as DIO#18, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO18 0x00010000 -#define GPIO_DOUT19_16_DIO18_BITN 16 -#define GPIO_DOUT19_16_DIO18_M 0x00010000 -#define GPIO_DOUT19_16_DIO18_S 16 - -// Field: [8] DIO17 -// -// Sets the state of the pin that is configured as DIO#17, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO17 0x00000100 -#define GPIO_DOUT19_16_DIO17_BITN 8 -#define GPIO_DOUT19_16_DIO17_M 0x00000100 -#define GPIO_DOUT19_16_DIO17_S 8 - -// Field: [0] DIO16 -// -// Sets the state of the pin that is configured as DIO#16, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT19_16_DIO16 0x00000001 -#define GPIO_DOUT19_16_DIO16_BITN 0 -#define GPIO_DOUT19_16_DIO16_M 0x00000001 -#define GPIO_DOUT19_16_DIO16_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT23_20 -// -//***************************************************************************** -// Field: [24] DIO23 -// -// Sets the state of the pin that is configured as DIO#23, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO23 0x01000000 -#define GPIO_DOUT23_20_DIO23_BITN 24 -#define GPIO_DOUT23_20_DIO23_M 0x01000000 -#define GPIO_DOUT23_20_DIO23_S 24 - -// Field: [16] DIO22 -// -// Sets the state of the pin that is configured as DIO#22, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO22 0x00010000 -#define GPIO_DOUT23_20_DIO22_BITN 16 -#define GPIO_DOUT23_20_DIO22_M 0x00010000 -#define GPIO_DOUT23_20_DIO22_S 16 - -// Field: [8] DIO21 -// -// Sets the state of the pin that is configured as DIO#21, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO21 0x00000100 -#define GPIO_DOUT23_20_DIO21_BITN 8 -#define GPIO_DOUT23_20_DIO21_M 0x00000100 -#define GPIO_DOUT23_20_DIO21_S 8 - -// Field: [0] DIO20 -// -// Sets the state of the pin that is configured as DIO#20, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT23_20_DIO20 0x00000001 -#define GPIO_DOUT23_20_DIO20_BITN 0 -#define GPIO_DOUT23_20_DIO20_M 0x00000001 -#define GPIO_DOUT23_20_DIO20_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT27_24 -// -//***************************************************************************** -// Field: [24] DIO27 -// -// Sets the state of the pin that is configured as DIO#27, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO27 0x01000000 -#define GPIO_DOUT27_24_DIO27_BITN 24 -#define GPIO_DOUT27_24_DIO27_M 0x01000000 -#define GPIO_DOUT27_24_DIO27_S 24 - -// Field: [16] DIO26 -// -// Sets the state of the pin that is configured as DIO#26, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO26 0x00010000 -#define GPIO_DOUT27_24_DIO26_BITN 16 -#define GPIO_DOUT27_24_DIO26_M 0x00010000 -#define GPIO_DOUT27_24_DIO26_S 16 - -// Field: [8] DIO25 -// -// Sets the state of the pin that is configured as DIO#25, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO25 0x00000100 -#define GPIO_DOUT27_24_DIO25_BITN 8 -#define GPIO_DOUT27_24_DIO25_M 0x00000100 -#define GPIO_DOUT27_24_DIO25_S 8 - -// Field: [0] DIO24 -// -// Sets the state of the pin that is configured as DIO#24, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT27_24_DIO24 0x00000001 -#define GPIO_DOUT27_24_DIO24_BITN 0 -#define GPIO_DOUT27_24_DIO24_M 0x00000001 -#define GPIO_DOUT27_24_DIO24_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT31_28 -// -//***************************************************************************** -// Field: [24] DIO31 -// -// Sets the state of the pin that is configured as DIO#31, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO31 0x01000000 -#define GPIO_DOUT31_28_DIO31_BITN 24 -#define GPIO_DOUT31_28_DIO31_M 0x01000000 -#define GPIO_DOUT31_28_DIO31_S 24 - -// Field: [16] DIO30 -// -// Sets the state of the pin that is configured as DIO#30, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO30 0x00010000 -#define GPIO_DOUT31_28_DIO30_BITN 16 -#define GPIO_DOUT31_28_DIO30_M 0x00010000 -#define GPIO_DOUT31_28_DIO30_S 16 - -// Field: [8] DIO29 -// -// Sets the state of the pin that is configured as DIO#29, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO29 0x00000100 -#define GPIO_DOUT31_28_DIO29_BITN 8 -#define GPIO_DOUT31_28_DIO29_M 0x00000100 -#define GPIO_DOUT31_28_DIO29_S 8 - -// Field: [0] DIO28 -// -// Sets the state of the pin that is configured as DIO#28, if the corresponding -// DOE31_0 bitfield is set. -#define GPIO_DOUT31_28_DIO28 0x00000001 -#define GPIO_DOUT31_28_DIO28_BITN 0 -#define GPIO_DOUT31_28_DIO28_M 0x00000001 -#define GPIO_DOUT31_28_DIO28_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUT31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Data output for DIO 31 -#define GPIO_DOUT31_0_DIO31 0x80000000 -#define GPIO_DOUT31_0_DIO31_BITN 31 -#define GPIO_DOUT31_0_DIO31_M 0x80000000 -#define GPIO_DOUT31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Data output for DIO 30 -#define GPIO_DOUT31_0_DIO30 0x40000000 -#define GPIO_DOUT31_0_DIO30_BITN 30 -#define GPIO_DOUT31_0_DIO30_M 0x40000000 -#define GPIO_DOUT31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Data output for DIO 29 -#define GPIO_DOUT31_0_DIO29 0x20000000 -#define GPIO_DOUT31_0_DIO29_BITN 29 -#define GPIO_DOUT31_0_DIO29_M 0x20000000 -#define GPIO_DOUT31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Data output for DIO 28 -#define GPIO_DOUT31_0_DIO28 0x10000000 -#define GPIO_DOUT31_0_DIO28_BITN 28 -#define GPIO_DOUT31_0_DIO28_M 0x10000000 -#define GPIO_DOUT31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Data output for DIO 27 -#define GPIO_DOUT31_0_DIO27 0x08000000 -#define GPIO_DOUT31_0_DIO27_BITN 27 -#define GPIO_DOUT31_0_DIO27_M 0x08000000 -#define GPIO_DOUT31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Data output for DIO 26 -#define GPIO_DOUT31_0_DIO26 0x04000000 -#define GPIO_DOUT31_0_DIO26_BITN 26 -#define GPIO_DOUT31_0_DIO26_M 0x04000000 -#define GPIO_DOUT31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Data output for DIO 25 -#define GPIO_DOUT31_0_DIO25 0x02000000 -#define GPIO_DOUT31_0_DIO25_BITN 25 -#define GPIO_DOUT31_0_DIO25_M 0x02000000 -#define GPIO_DOUT31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Data output for DIO 24 -#define GPIO_DOUT31_0_DIO24 0x01000000 -#define GPIO_DOUT31_0_DIO24_BITN 24 -#define GPIO_DOUT31_0_DIO24_M 0x01000000 -#define GPIO_DOUT31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Data output for DIO 23 -#define GPIO_DOUT31_0_DIO23 0x00800000 -#define GPIO_DOUT31_0_DIO23_BITN 23 -#define GPIO_DOUT31_0_DIO23_M 0x00800000 -#define GPIO_DOUT31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Data output for DIO 22 -#define GPIO_DOUT31_0_DIO22 0x00400000 -#define GPIO_DOUT31_0_DIO22_BITN 22 -#define GPIO_DOUT31_0_DIO22_M 0x00400000 -#define GPIO_DOUT31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Data output for DIO 21 -#define GPIO_DOUT31_0_DIO21 0x00200000 -#define GPIO_DOUT31_0_DIO21_BITN 21 -#define GPIO_DOUT31_0_DIO21_M 0x00200000 -#define GPIO_DOUT31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Data output for DIO 20 -#define GPIO_DOUT31_0_DIO20 0x00100000 -#define GPIO_DOUT31_0_DIO20_BITN 20 -#define GPIO_DOUT31_0_DIO20_M 0x00100000 -#define GPIO_DOUT31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Data output for DIO 19 -#define GPIO_DOUT31_0_DIO19 0x00080000 -#define GPIO_DOUT31_0_DIO19_BITN 19 -#define GPIO_DOUT31_0_DIO19_M 0x00080000 -#define GPIO_DOUT31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Data output for DIO 18 -#define GPIO_DOUT31_0_DIO18 0x00040000 -#define GPIO_DOUT31_0_DIO18_BITN 18 -#define GPIO_DOUT31_0_DIO18_M 0x00040000 -#define GPIO_DOUT31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Data output for DIO 17 -#define GPIO_DOUT31_0_DIO17 0x00020000 -#define GPIO_DOUT31_0_DIO17_BITN 17 -#define GPIO_DOUT31_0_DIO17_M 0x00020000 -#define GPIO_DOUT31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Data output for DIO 16 -#define GPIO_DOUT31_0_DIO16 0x00010000 -#define GPIO_DOUT31_0_DIO16_BITN 16 -#define GPIO_DOUT31_0_DIO16_M 0x00010000 -#define GPIO_DOUT31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Data output for DIO 15 -#define GPIO_DOUT31_0_DIO15 0x00008000 -#define GPIO_DOUT31_0_DIO15_BITN 15 -#define GPIO_DOUT31_0_DIO15_M 0x00008000 -#define GPIO_DOUT31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Data output for DIO 14 -#define GPIO_DOUT31_0_DIO14 0x00004000 -#define GPIO_DOUT31_0_DIO14_BITN 14 -#define GPIO_DOUT31_0_DIO14_M 0x00004000 -#define GPIO_DOUT31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Data output for DIO 13 -#define GPIO_DOUT31_0_DIO13 0x00002000 -#define GPIO_DOUT31_0_DIO13_BITN 13 -#define GPIO_DOUT31_0_DIO13_M 0x00002000 -#define GPIO_DOUT31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Data output for DIO 12 -#define GPIO_DOUT31_0_DIO12 0x00001000 -#define GPIO_DOUT31_0_DIO12_BITN 12 -#define GPIO_DOUT31_0_DIO12_M 0x00001000 -#define GPIO_DOUT31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Data output for DIO 11 -#define GPIO_DOUT31_0_DIO11 0x00000800 -#define GPIO_DOUT31_0_DIO11_BITN 11 -#define GPIO_DOUT31_0_DIO11_M 0x00000800 -#define GPIO_DOUT31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Data output for DIO 10 -#define GPIO_DOUT31_0_DIO10 0x00000400 -#define GPIO_DOUT31_0_DIO10_BITN 10 -#define GPIO_DOUT31_0_DIO10_M 0x00000400 -#define GPIO_DOUT31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Data output for DIO 9 -#define GPIO_DOUT31_0_DIO9 0x00000200 -#define GPIO_DOUT31_0_DIO9_BITN 9 -#define GPIO_DOUT31_0_DIO9_M 0x00000200 -#define GPIO_DOUT31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Data output for DIO 8 -#define GPIO_DOUT31_0_DIO8 0x00000100 -#define GPIO_DOUT31_0_DIO8_BITN 8 -#define GPIO_DOUT31_0_DIO8_M 0x00000100 -#define GPIO_DOUT31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Data output for DIO 7 -#define GPIO_DOUT31_0_DIO7 0x00000080 -#define GPIO_DOUT31_0_DIO7_BITN 7 -#define GPIO_DOUT31_0_DIO7_M 0x00000080 -#define GPIO_DOUT31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Data output for DIO 6 -#define GPIO_DOUT31_0_DIO6 0x00000040 -#define GPIO_DOUT31_0_DIO6_BITN 6 -#define GPIO_DOUT31_0_DIO6_M 0x00000040 -#define GPIO_DOUT31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Data output for DIO 5 -#define GPIO_DOUT31_0_DIO5 0x00000020 -#define GPIO_DOUT31_0_DIO5_BITN 5 -#define GPIO_DOUT31_0_DIO5_M 0x00000020 -#define GPIO_DOUT31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Data output for DIO 4 -#define GPIO_DOUT31_0_DIO4 0x00000010 -#define GPIO_DOUT31_0_DIO4_BITN 4 -#define GPIO_DOUT31_0_DIO4_M 0x00000010 -#define GPIO_DOUT31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Data output for DIO 3 -#define GPIO_DOUT31_0_DIO3 0x00000008 -#define GPIO_DOUT31_0_DIO3_BITN 3 -#define GPIO_DOUT31_0_DIO3_M 0x00000008 -#define GPIO_DOUT31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Data output for DIO 2 -#define GPIO_DOUT31_0_DIO2 0x00000004 -#define GPIO_DOUT31_0_DIO2_BITN 2 -#define GPIO_DOUT31_0_DIO2_M 0x00000004 -#define GPIO_DOUT31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Data output for DIO 1 -#define GPIO_DOUT31_0_DIO1 0x00000002 -#define GPIO_DOUT31_0_DIO1_BITN 1 -#define GPIO_DOUT31_0_DIO1_M 0x00000002 -#define GPIO_DOUT31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Data output for DIO 0 -#define GPIO_DOUT31_0_DIO0 0x00000001 -#define GPIO_DOUT31_0_DIO0_BITN 0 -#define GPIO_DOUT31_0_DIO0_M 0x00000001 -#define GPIO_DOUT31_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUTSET31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Set bit 31 -#define GPIO_DOUTSET31_0_DIO31 0x80000000 -#define GPIO_DOUTSET31_0_DIO31_BITN 31 -#define GPIO_DOUTSET31_0_DIO31_M 0x80000000 -#define GPIO_DOUTSET31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Set bit 30 -#define GPIO_DOUTSET31_0_DIO30 0x40000000 -#define GPIO_DOUTSET31_0_DIO30_BITN 30 -#define GPIO_DOUTSET31_0_DIO30_M 0x40000000 -#define GPIO_DOUTSET31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Set bit 29 -#define GPIO_DOUTSET31_0_DIO29 0x20000000 -#define GPIO_DOUTSET31_0_DIO29_BITN 29 -#define GPIO_DOUTSET31_0_DIO29_M 0x20000000 -#define GPIO_DOUTSET31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Set bit 28 -#define GPIO_DOUTSET31_0_DIO28 0x10000000 -#define GPIO_DOUTSET31_0_DIO28_BITN 28 -#define GPIO_DOUTSET31_0_DIO28_M 0x10000000 -#define GPIO_DOUTSET31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Set bit 27 -#define GPIO_DOUTSET31_0_DIO27 0x08000000 -#define GPIO_DOUTSET31_0_DIO27_BITN 27 -#define GPIO_DOUTSET31_0_DIO27_M 0x08000000 -#define GPIO_DOUTSET31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Set bit 26 -#define GPIO_DOUTSET31_0_DIO26 0x04000000 -#define GPIO_DOUTSET31_0_DIO26_BITN 26 -#define GPIO_DOUTSET31_0_DIO26_M 0x04000000 -#define GPIO_DOUTSET31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Set bit 25 -#define GPIO_DOUTSET31_0_DIO25 0x02000000 -#define GPIO_DOUTSET31_0_DIO25_BITN 25 -#define GPIO_DOUTSET31_0_DIO25_M 0x02000000 -#define GPIO_DOUTSET31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Set bit 24 -#define GPIO_DOUTSET31_0_DIO24 0x01000000 -#define GPIO_DOUTSET31_0_DIO24_BITN 24 -#define GPIO_DOUTSET31_0_DIO24_M 0x01000000 -#define GPIO_DOUTSET31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Set bit 23 -#define GPIO_DOUTSET31_0_DIO23 0x00800000 -#define GPIO_DOUTSET31_0_DIO23_BITN 23 -#define GPIO_DOUTSET31_0_DIO23_M 0x00800000 -#define GPIO_DOUTSET31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Set bit 22 -#define GPIO_DOUTSET31_0_DIO22 0x00400000 -#define GPIO_DOUTSET31_0_DIO22_BITN 22 -#define GPIO_DOUTSET31_0_DIO22_M 0x00400000 -#define GPIO_DOUTSET31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Set bit 21 -#define GPIO_DOUTSET31_0_DIO21 0x00200000 -#define GPIO_DOUTSET31_0_DIO21_BITN 21 -#define GPIO_DOUTSET31_0_DIO21_M 0x00200000 -#define GPIO_DOUTSET31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Set bit 20 -#define GPIO_DOUTSET31_0_DIO20 0x00100000 -#define GPIO_DOUTSET31_0_DIO20_BITN 20 -#define GPIO_DOUTSET31_0_DIO20_M 0x00100000 -#define GPIO_DOUTSET31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Set bit 19 -#define GPIO_DOUTSET31_0_DIO19 0x00080000 -#define GPIO_DOUTSET31_0_DIO19_BITN 19 -#define GPIO_DOUTSET31_0_DIO19_M 0x00080000 -#define GPIO_DOUTSET31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Set bit 18 -#define GPIO_DOUTSET31_0_DIO18 0x00040000 -#define GPIO_DOUTSET31_0_DIO18_BITN 18 -#define GPIO_DOUTSET31_0_DIO18_M 0x00040000 -#define GPIO_DOUTSET31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Set bit 17 -#define GPIO_DOUTSET31_0_DIO17 0x00020000 -#define GPIO_DOUTSET31_0_DIO17_BITN 17 -#define GPIO_DOUTSET31_0_DIO17_M 0x00020000 -#define GPIO_DOUTSET31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Set bit 16 -#define GPIO_DOUTSET31_0_DIO16 0x00010000 -#define GPIO_DOUTSET31_0_DIO16_BITN 16 -#define GPIO_DOUTSET31_0_DIO16_M 0x00010000 -#define GPIO_DOUTSET31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Set bit 15 -#define GPIO_DOUTSET31_0_DIO15 0x00008000 -#define GPIO_DOUTSET31_0_DIO15_BITN 15 -#define GPIO_DOUTSET31_0_DIO15_M 0x00008000 -#define GPIO_DOUTSET31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Set bit 14 -#define GPIO_DOUTSET31_0_DIO14 0x00004000 -#define GPIO_DOUTSET31_0_DIO14_BITN 14 -#define GPIO_DOUTSET31_0_DIO14_M 0x00004000 -#define GPIO_DOUTSET31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Set bit 13 -#define GPIO_DOUTSET31_0_DIO13 0x00002000 -#define GPIO_DOUTSET31_0_DIO13_BITN 13 -#define GPIO_DOUTSET31_0_DIO13_M 0x00002000 -#define GPIO_DOUTSET31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Set bit 12 -#define GPIO_DOUTSET31_0_DIO12 0x00001000 -#define GPIO_DOUTSET31_0_DIO12_BITN 12 -#define GPIO_DOUTSET31_0_DIO12_M 0x00001000 -#define GPIO_DOUTSET31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Set bit 11 -#define GPIO_DOUTSET31_0_DIO11 0x00000800 -#define GPIO_DOUTSET31_0_DIO11_BITN 11 -#define GPIO_DOUTSET31_0_DIO11_M 0x00000800 -#define GPIO_DOUTSET31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Set bit 10 -#define GPIO_DOUTSET31_0_DIO10 0x00000400 -#define GPIO_DOUTSET31_0_DIO10_BITN 10 -#define GPIO_DOUTSET31_0_DIO10_M 0x00000400 -#define GPIO_DOUTSET31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Set bit 9 -#define GPIO_DOUTSET31_0_DIO9 0x00000200 -#define GPIO_DOUTSET31_0_DIO9_BITN 9 -#define GPIO_DOUTSET31_0_DIO9_M 0x00000200 -#define GPIO_DOUTSET31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Set bit 8 -#define GPIO_DOUTSET31_0_DIO8 0x00000100 -#define GPIO_DOUTSET31_0_DIO8_BITN 8 -#define GPIO_DOUTSET31_0_DIO8_M 0x00000100 -#define GPIO_DOUTSET31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Set bit 7 -#define GPIO_DOUTSET31_0_DIO7 0x00000080 -#define GPIO_DOUTSET31_0_DIO7_BITN 7 -#define GPIO_DOUTSET31_0_DIO7_M 0x00000080 -#define GPIO_DOUTSET31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Set bit 6 -#define GPIO_DOUTSET31_0_DIO6 0x00000040 -#define GPIO_DOUTSET31_0_DIO6_BITN 6 -#define GPIO_DOUTSET31_0_DIO6_M 0x00000040 -#define GPIO_DOUTSET31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Set bit 5 -#define GPIO_DOUTSET31_0_DIO5 0x00000020 -#define GPIO_DOUTSET31_0_DIO5_BITN 5 -#define GPIO_DOUTSET31_0_DIO5_M 0x00000020 -#define GPIO_DOUTSET31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Set bit 4 -#define GPIO_DOUTSET31_0_DIO4 0x00000010 -#define GPIO_DOUTSET31_0_DIO4_BITN 4 -#define GPIO_DOUTSET31_0_DIO4_M 0x00000010 -#define GPIO_DOUTSET31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Set bit 3 -#define GPIO_DOUTSET31_0_DIO3 0x00000008 -#define GPIO_DOUTSET31_0_DIO3_BITN 3 -#define GPIO_DOUTSET31_0_DIO3_M 0x00000008 -#define GPIO_DOUTSET31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Set bit 2 -#define GPIO_DOUTSET31_0_DIO2 0x00000004 -#define GPIO_DOUTSET31_0_DIO2_BITN 2 -#define GPIO_DOUTSET31_0_DIO2_M 0x00000004 -#define GPIO_DOUTSET31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Set bit 1 -#define GPIO_DOUTSET31_0_DIO1 0x00000002 -#define GPIO_DOUTSET31_0_DIO1_BITN 1 -#define GPIO_DOUTSET31_0_DIO1_M 0x00000002 -#define GPIO_DOUTSET31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Set bit 0 -#define GPIO_DOUTSET31_0_DIO0 0x00000001 -#define GPIO_DOUTSET31_0_DIO0_BITN 0 -#define GPIO_DOUTSET31_0_DIO0_M 0x00000001 -#define GPIO_DOUTSET31_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUTCLR31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Clears bit 31 -#define GPIO_DOUTCLR31_0_DIO31 0x80000000 -#define GPIO_DOUTCLR31_0_DIO31_BITN 31 -#define GPIO_DOUTCLR31_0_DIO31_M 0x80000000 -#define GPIO_DOUTCLR31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Clears bit 30 -#define GPIO_DOUTCLR31_0_DIO30 0x40000000 -#define GPIO_DOUTCLR31_0_DIO30_BITN 30 -#define GPIO_DOUTCLR31_0_DIO30_M 0x40000000 -#define GPIO_DOUTCLR31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Clears bit 29 -#define GPIO_DOUTCLR31_0_DIO29 0x20000000 -#define GPIO_DOUTCLR31_0_DIO29_BITN 29 -#define GPIO_DOUTCLR31_0_DIO29_M 0x20000000 -#define GPIO_DOUTCLR31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Clears bit 28 -#define GPIO_DOUTCLR31_0_DIO28 0x10000000 -#define GPIO_DOUTCLR31_0_DIO28_BITN 28 -#define GPIO_DOUTCLR31_0_DIO28_M 0x10000000 -#define GPIO_DOUTCLR31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Clears bit 27 -#define GPIO_DOUTCLR31_0_DIO27 0x08000000 -#define GPIO_DOUTCLR31_0_DIO27_BITN 27 -#define GPIO_DOUTCLR31_0_DIO27_M 0x08000000 -#define GPIO_DOUTCLR31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Clears bit 26 -#define GPIO_DOUTCLR31_0_DIO26 0x04000000 -#define GPIO_DOUTCLR31_0_DIO26_BITN 26 -#define GPIO_DOUTCLR31_0_DIO26_M 0x04000000 -#define GPIO_DOUTCLR31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Clears bit 25 -#define GPIO_DOUTCLR31_0_DIO25 0x02000000 -#define GPIO_DOUTCLR31_0_DIO25_BITN 25 -#define GPIO_DOUTCLR31_0_DIO25_M 0x02000000 -#define GPIO_DOUTCLR31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Clears bit 24 -#define GPIO_DOUTCLR31_0_DIO24 0x01000000 -#define GPIO_DOUTCLR31_0_DIO24_BITN 24 -#define GPIO_DOUTCLR31_0_DIO24_M 0x01000000 -#define GPIO_DOUTCLR31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Clears bit 23 -#define GPIO_DOUTCLR31_0_DIO23 0x00800000 -#define GPIO_DOUTCLR31_0_DIO23_BITN 23 -#define GPIO_DOUTCLR31_0_DIO23_M 0x00800000 -#define GPIO_DOUTCLR31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Clears bit 22 -#define GPIO_DOUTCLR31_0_DIO22 0x00400000 -#define GPIO_DOUTCLR31_0_DIO22_BITN 22 -#define GPIO_DOUTCLR31_0_DIO22_M 0x00400000 -#define GPIO_DOUTCLR31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Clears bit 21 -#define GPIO_DOUTCLR31_0_DIO21 0x00200000 -#define GPIO_DOUTCLR31_0_DIO21_BITN 21 -#define GPIO_DOUTCLR31_0_DIO21_M 0x00200000 -#define GPIO_DOUTCLR31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Clears bit 20 -#define GPIO_DOUTCLR31_0_DIO20 0x00100000 -#define GPIO_DOUTCLR31_0_DIO20_BITN 20 -#define GPIO_DOUTCLR31_0_DIO20_M 0x00100000 -#define GPIO_DOUTCLR31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Clears bit 19 -#define GPIO_DOUTCLR31_0_DIO19 0x00080000 -#define GPIO_DOUTCLR31_0_DIO19_BITN 19 -#define GPIO_DOUTCLR31_0_DIO19_M 0x00080000 -#define GPIO_DOUTCLR31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Clears bit 18 -#define GPIO_DOUTCLR31_0_DIO18 0x00040000 -#define GPIO_DOUTCLR31_0_DIO18_BITN 18 -#define GPIO_DOUTCLR31_0_DIO18_M 0x00040000 -#define GPIO_DOUTCLR31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Clears bit 17 -#define GPIO_DOUTCLR31_0_DIO17 0x00020000 -#define GPIO_DOUTCLR31_0_DIO17_BITN 17 -#define GPIO_DOUTCLR31_0_DIO17_M 0x00020000 -#define GPIO_DOUTCLR31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Clears bit 16 -#define GPIO_DOUTCLR31_0_DIO16 0x00010000 -#define GPIO_DOUTCLR31_0_DIO16_BITN 16 -#define GPIO_DOUTCLR31_0_DIO16_M 0x00010000 -#define GPIO_DOUTCLR31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Clears bit 15 -#define GPIO_DOUTCLR31_0_DIO15 0x00008000 -#define GPIO_DOUTCLR31_0_DIO15_BITN 15 -#define GPIO_DOUTCLR31_0_DIO15_M 0x00008000 -#define GPIO_DOUTCLR31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Clears bit 14 -#define GPIO_DOUTCLR31_0_DIO14 0x00004000 -#define GPIO_DOUTCLR31_0_DIO14_BITN 14 -#define GPIO_DOUTCLR31_0_DIO14_M 0x00004000 -#define GPIO_DOUTCLR31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Clears bit 13 -#define GPIO_DOUTCLR31_0_DIO13 0x00002000 -#define GPIO_DOUTCLR31_0_DIO13_BITN 13 -#define GPIO_DOUTCLR31_0_DIO13_M 0x00002000 -#define GPIO_DOUTCLR31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Clears bit 12 -#define GPIO_DOUTCLR31_0_DIO12 0x00001000 -#define GPIO_DOUTCLR31_0_DIO12_BITN 12 -#define GPIO_DOUTCLR31_0_DIO12_M 0x00001000 -#define GPIO_DOUTCLR31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Clears bit 11 -#define GPIO_DOUTCLR31_0_DIO11 0x00000800 -#define GPIO_DOUTCLR31_0_DIO11_BITN 11 -#define GPIO_DOUTCLR31_0_DIO11_M 0x00000800 -#define GPIO_DOUTCLR31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Clears bit 10 -#define GPIO_DOUTCLR31_0_DIO10 0x00000400 -#define GPIO_DOUTCLR31_0_DIO10_BITN 10 -#define GPIO_DOUTCLR31_0_DIO10_M 0x00000400 -#define GPIO_DOUTCLR31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Clears bit 9 -#define GPIO_DOUTCLR31_0_DIO9 0x00000200 -#define GPIO_DOUTCLR31_0_DIO9_BITN 9 -#define GPIO_DOUTCLR31_0_DIO9_M 0x00000200 -#define GPIO_DOUTCLR31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Clears bit 8 -#define GPIO_DOUTCLR31_0_DIO8 0x00000100 -#define GPIO_DOUTCLR31_0_DIO8_BITN 8 -#define GPIO_DOUTCLR31_0_DIO8_M 0x00000100 -#define GPIO_DOUTCLR31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Clears bit 7 -#define GPIO_DOUTCLR31_0_DIO7 0x00000080 -#define GPIO_DOUTCLR31_0_DIO7_BITN 7 -#define GPIO_DOUTCLR31_0_DIO7_M 0x00000080 -#define GPIO_DOUTCLR31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Clears bit 6 -#define GPIO_DOUTCLR31_0_DIO6 0x00000040 -#define GPIO_DOUTCLR31_0_DIO6_BITN 6 -#define GPIO_DOUTCLR31_0_DIO6_M 0x00000040 -#define GPIO_DOUTCLR31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Clears bit 5 -#define GPIO_DOUTCLR31_0_DIO5 0x00000020 -#define GPIO_DOUTCLR31_0_DIO5_BITN 5 -#define GPIO_DOUTCLR31_0_DIO5_M 0x00000020 -#define GPIO_DOUTCLR31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Clears bit 4 -#define GPIO_DOUTCLR31_0_DIO4 0x00000010 -#define GPIO_DOUTCLR31_0_DIO4_BITN 4 -#define GPIO_DOUTCLR31_0_DIO4_M 0x00000010 -#define GPIO_DOUTCLR31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Clears bit 3 -#define GPIO_DOUTCLR31_0_DIO3 0x00000008 -#define GPIO_DOUTCLR31_0_DIO3_BITN 3 -#define GPIO_DOUTCLR31_0_DIO3_M 0x00000008 -#define GPIO_DOUTCLR31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Clears bit 2 -#define GPIO_DOUTCLR31_0_DIO2 0x00000004 -#define GPIO_DOUTCLR31_0_DIO2_BITN 2 -#define GPIO_DOUTCLR31_0_DIO2_M 0x00000004 -#define GPIO_DOUTCLR31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Clears bit 1 -#define GPIO_DOUTCLR31_0_DIO1 0x00000002 -#define GPIO_DOUTCLR31_0_DIO1_BITN 1 -#define GPIO_DOUTCLR31_0_DIO1_M 0x00000002 -#define GPIO_DOUTCLR31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Clears bit 0 -#define GPIO_DOUTCLR31_0_DIO0 0x00000001 -#define GPIO_DOUTCLR31_0_DIO0_BITN 0 -#define GPIO_DOUTCLR31_0_DIO0_M 0x00000001 -#define GPIO_DOUTCLR31_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOUTTGL31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Toggles bit 31 -#define GPIO_DOUTTGL31_0_DIO31 0x80000000 -#define GPIO_DOUTTGL31_0_DIO31_BITN 31 -#define GPIO_DOUTTGL31_0_DIO31_M 0x80000000 -#define GPIO_DOUTTGL31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Toggles bit 30 -#define GPIO_DOUTTGL31_0_DIO30 0x40000000 -#define GPIO_DOUTTGL31_0_DIO30_BITN 30 -#define GPIO_DOUTTGL31_0_DIO30_M 0x40000000 -#define GPIO_DOUTTGL31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Toggles bit 29 -#define GPIO_DOUTTGL31_0_DIO29 0x20000000 -#define GPIO_DOUTTGL31_0_DIO29_BITN 29 -#define GPIO_DOUTTGL31_0_DIO29_M 0x20000000 -#define GPIO_DOUTTGL31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Toggles bit 28 -#define GPIO_DOUTTGL31_0_DIO28 0x10000000 -#define GPIO_DOUTTGL31_0_DIO28_BITN 28 -#define GPIO_DOUTTGL31_0_DIO28_M 0x10000000 -#define GPIO_DOUTTGL31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Toggles bit 27 -#define GPIO_DOUTTGL31_0_DIO27 0x08000000 -#define GPIO_DOUTTGL31_0_DIO27_BITN 27 -#define GPIO_DOUTTGL31_0_DIO27_M 0x08000000 -#define GPIO_DOUTTGL31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Toggles bit 26 -#define GPIO_DOUTTGL31_0_DIO26 0x04000000 -#define GPIO_DOUTTGL31_0_DIO26_BITN 26 -#define GPIO_DOUTTGL31_0_DIO26_M 0x04000000 -#define GPIO_DOUTTGL31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Toggles bit 25 -#define GPIO_DOUTTGL31_0_DIO25 0x02000000 -#define GPIO_DOUTTGL31_0_DIO25_BITN 25 -#define GPIO_DOUTTGL31_0_DIO25_M 0x02000000 -#define GPIO_DOUTTGL31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Toggles bit 24 -#define GPIO_DOUTTGL31_0_DIO24 0x01000000 -#define GPIO_DOUTTGL31_0_DIO24_BITN 24 -#define GPIO_DOUTTGL31_0_DIO24_M 0x01000000 -#define GPIO_DOUTTGL31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Toggles bit 23 -#define GPIO_DOUTTGL31_0_DIO23 0x00800000 -#define GPIO_DOUTTGL31_0_DIO23_BITN 23 -#define GPIO_DOUTTGL31_0_DIO23_M 0x00800000 -#define GPIO_DOUTTGL31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Toggles bit 22 -#define GPIO_DOUTTGL31_0_DIO22 0x00400000 -#define GPIO_DOUTTGL31_0_DIO22_BITN 22 -#define GPIO_DOUTTGL31_0_DIO22_M 0x00400000 -#define GPIO_DOUTTGL31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Toggles bit 21 -#define GPIO_DOUTTGL31_0_DIO21 0x00200000 -#define GPIO_DOUTTGL31_0_DIO21_BITN 21 -#define GPIO_DOUTTGL31_0_DIO21_M 0x00200000 -#define GPIO_DOUTTGL31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Toggles bit 20 -#define GPIO_DOUTTGL31_0_DIO20 0x00100000 -#define GPIO_DOUTTGL31_0_DIO20_BITN 20 -#define GPIO_DOUTTGL31_0_DIO20_M 0x00100000 -#define GPIO_DOUTTGL31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Toggles bit 19 -#define GPIO_DOUTTGL31_0_DIO19 0x00080000 -#define GPIO_DOUTTGL31_0_DIO19_BITN 19 -#define GPIO_DOUTTGL31_0_DIO19_M 0x00080000 -#define GPIO_DOUTTGL31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Toggles bit 18 -#define GPIO_DOUTTGL31_0_DIO18 0x00040000 -#define GPIO_DOUTTGL31_0_DIO18_BITN 18 -#define GPIO_DOUTTGL31_0_DIO18_M 0x00040000 -#define GPIO_DOUTTGL31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Toggles bit 17 -#define GPIO_DOUTTGL31_0_DIO17 0x00020000 -#define GPIO_DOUTTGL31_0_DIO17_BITN 17 -#define GPIO_DOUTTGL31_0_DIO17_M 0x00020000 -#define GPIO_DOUTTGL31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Toggles bit 16 -#define GPIO_DOUTTGL31_0_DIO16 0x00010000 -#define GPIO_DOUTTGL31_0_DIO16_BITN 16 -#define GPIO_DOUTTGL31_0_DIO16_M 0x00010000 -#define GPIO_DOUTTGL31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Toggles bit 15 -#define GPIO_DOUTTGL31_0_DIO15 0x00008000 -#define GPIO_DOUTTGL31_0_DIO15_BITN 15 -#define GPIO_DOUTTGL31_0_DIO15_M 0x00008000 -#define GPIO_DOUTTGL31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Toggles bit 14 -#define GPIO_DOUTTGL31_0_DIO14 0x00004000 -#define GPIO_DOUTTGL31_0_DIO14_BITN 14 -#define GPIO_DOUTTGL31_0_DIO14_M 0x00004000 -#define GPIO_DOUTTGL31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Toggles bit 13 -#define GPIO_DOUTTGL31_0_DIO13 0x00002000 -#define GPIO_DOUTTGL31_0_DIO13_BITN 13 -#define GPIO_DOUTTGL31_0_DIO13_M 0x00002000 -#define GPIO_DOUTTGL31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Toggles bit 12 -#define GPIO_DOUTTGL31_0_DIO12 0x00001000 -#define GPIO_DOUTTGL31_0_DIO12_BITN 12 -#define GPIO_DOUTTGL31_0_DIO12_M 0x00001000 -#define GPIO_DOUTTGL31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Toggles bit 11 -#define GPIO_DOUTTGL31_0_DIO11 0x00000800 -#define GPIO_DOUTTGL31_0_DIO11_BITN 11 -#define GPIO_DOUTTGL31_0_DIO11_M 0x00000800 -#define GPIO_DOUTTGL31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Toggles bit 10 -#define GPIO_DOUTTGL31_0_DIO10 0x00000400 -#define GPIO_DOUTTGL31_0_DIO10_BITN 10 -#define GPIO_DOUTTGL31_0_DIO10_M 0x00000400 -#define GPIO_DOUTTGL31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Toggles bit 9 -#define GPIO_DOUTTGL31_0_DIO9 0x00000200 -#define GPIO_DOUTTGL31_0_DIO9_BITN 9 -#define GPIO_DOUTTGL31_0_DIO9_M 0x00000200 -#define GPIO_DOUTTGL31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Toggles bit 8 -#define GPIO_DOUTTGL31_0_DIO8 0x00000100 -#define GPIO_DOUTTGL31_0_DIO8_BITN 8 -#define GPIO_DOUTTGL31_0_DIO8_M 0x00000100 -#define GPIO_DOUTTGL31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Toggles bit 7 -#define GPIO_DOUTTGL31_0_DIO7 0x00000080 -#define GPIO_DOUTTGL31_0_DIO7_BITN 7 -#define GPIO_DOUTTGL31_0_DIO7_M 0x00000080 -#define GPIO_DOUTTGL31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Toggles bit 6 -#define GPIO_DOUTTGL31_0_DIO6 0x00000040 -#define GPIO_DOUTTGL31_0_DIO6_BITN 6 -#define GPIO_DOUTTGL31_0_DIO6_M 0x00000040 -#define GPIO_DOUTTGL31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Toggles bit 5 -#define GPIO_DOUTTGL31_0_DIO5 0x00000020 -#define GPIO_DOUTTGL31_0_DIO5_BITN 5 -#define GPIO_DOUTTGL31_0_DIO5_M 0x00000020 -#define GPIO_DOUTTGL31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Toggles bit 4 -#define GPIO_DOUTTGL31_0_DIO4 0x00000010 -#define GPIO_DOUTTGL31_0_DIO4_BITN 4 -#define GPIO_DOUTTGL31_0_DIO4_M 0x00000010 -#define GPIO_DOUTTGL31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Toggles bit 3 -#define GPIO_DOUTTGL31_0_DIO3 0x00000008 -#define GPIO_DOUTTGL31_0_DIO3_BITN 3 -#define GPIO_DOUTTGL31_0_DIO3_M 0x00000008 -#define GPIO_DOUTTGL31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Toggles bit 2 -#define GPIO_DOUTTGL31_0_DIO2 0x00000004 -#define GPIO_DOUTTGL31_0_DIO2_BITN 2 -#define GPIO_DOUTTGL31_0_DIO2_M 0x00000004 -#define GPIO_DOUTTGL31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Toggles bit 1 -#define GPIO_DOUTTGL31_0_DIO1 0x00000002 -#define GPIO_DOUTTGL31_0_DIO1_BITN 1 -#define GPIO_DOUTTGL31_0_DIO1_M 0x00000002 -#define GPIO_DOUTTGL31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Toggles bit 0 -#define GPIO_DOUTTGL31_0_DIO0 0x00000001 -#define GPIO_DOUTTGL31_0_DIO0_BITN 0 -#define GPIO_DOUTTGL31_0_DIO0_M 0x00000001 -#define GPIO_DOUTTGL31_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DIN31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Data input from DIO 31 -#define GPIO_DIN31_0_DIO31 0x80000000 -#define GPIO_DIN31_0_DIO31_BITN 31 -#define GPIO_DIN31_0_DIO31_M 0x80000000 -#define GPIO_DIN31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Data input from DIO 30 -#define GPIO_DIN31_0_DIO30 0x40000000 -#define GPIO_DIN31_0_DIO30_BITN 30 -#define GPIO_DIN31_0_DIO30_M 0x40000000 -#define GPIO_DIN31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Data input from DIO 29 -#define GPIO_DIN31_0_DIO29 0x20000000 -#define GPIO_DIN31_0_DIO29_BITN 29 -#define GPIO_DIN31_0_DIO29_M 0x20000000 -#define GPIO_DIN31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Data input from DIO 28 -#define GPIO_DIN31_0_DIO28 0x10000000 -#define GPIO_DIN31_0_DIO28_BITN 28 -#define GPIO_DIN31_0_DIO28_M 0x10000000 -#define GPIO_DIN31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Data input from DIO 27 -#define GPIO_DIN31_0_DIO27 0x08000000 -#define GPIO_DIN31_0_DIO27_BITN 27 -#define GPIO_DIN31_0_DIO27_M 0x08000000 -#define GPIO_DIN31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Data input from DIO 26 -#define GPIO_DIN31_0_DIO26 0x04000000 -#define GPIO_DIN31_0_DIO26_BITN 26 -#define GPIO_DIN31_0_DIO26_M 0x04000000 -#define GPIO_DIN31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Data input from DIO 25 -#define GPIO_DIN31_0_DIO25 0x02000000 -#define GPIO_DIN31_0_DIO25_BITN 25 -#define GPIO_DIN31_0_DIO25_M 0x02000000 -#define GPIO_DIN31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Data input from DIO 24 -#define GPIO_DIN31_0_DIO24 0x01000000 -#define GPIO_DIN31_0_DIO24_BITN 24 -#define GPIO_DIN31_0_DIO24_M 0x01000000 -#define GPIO_DIN31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Data input from DIO 23 -#define GPIO_DIN31_0_DIO23 0x00800000 -#define GPIO_DIN31_0_DIO23_BITN 23 -#define GPIO_DIN31_0_DIO23_M 0x00800000 -#define GPIO_DIN31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Data input from DIO 22 -#define GPIO_DIN31_0_DIO22 0x00400000 -#define GPIO_DIN31_0_DIO22_BITN 22 -#define GPIO_DIN31_0_DIO22_M 0x00400000 -#define GPIO_DIN31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Data input from DIO 21 -#define GPIO_DIN31_0_DIO21 0x00200000 -#define GPIO_DIN31_0_DIO21_BITN 21 -#define GPIO_DIN31_0_DIO21_M 0x00200000 -#define GPIO_DIN31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Data input from DIO 20 -#define GPIO_DIN31_0_DIO20 0x00100000 -#define GPIO_DIN31_0_DIO20_BITN 20 -#define GPIO_DIN31_0_DIO20_M 0x00100000 -#define GPIO_DIN31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Data input from DIO 19 -#define GPIO_DIN31_0_DIO19 0x00080000 -#define GPIO_DIN31_0_DIO19_BITN 19 -#define GPIO_DIN31_0_DIO19_M 0x00080000 -#define GPIO_DIN31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Data input from DIO 18 -#define GPIO_DIN31_0_DIO18 0x00040000 -#define GPIO_DIN31_0_DIO18_BITN 18 -#define GPIO_DIN31_0_DIO18_M 0x00040000 -#define GPIO_DIN31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Data input from DIO 17 -#define GPIO_DIN31_0_DIO17 0x00020000 -#define GPIO_DIN31_0_DIO17_BITN 17 -#define GPIO_DIN31_0_DIO17_M 0x00020000 -#define GPIO_DIN31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Data input from DIO 16 -#define GPIO_DIN31_0_DIO16 0x00010000 -#define GPIO_DIN31_0_DIO16_BITN 16 -#define GPIO_DIN31_0_DIO16_M 0x00010000 -#define GPIO_DIN31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Data input from DIO 15 -#define GPIO_DIN31_0_DIO15 0x00008000 -#define GPIO_DIN31_0_DIO15_BITN 15 -#define GPIO_DIN31_0_DIO15_M 0x00008000 -#define GPIO_DIN31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Data input from DIO 14 -#define GPIO_DIN31_0_DIO14 0x00004000 -#define GPIO_DIN31_0_DIO14_BITN 14 -#define GPIO_DIN31_0_DIO14_M 0x00004000 -#define GPIO_DIN31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Data input from DIO 13 -#define GPIO_DIN31_0_DIO13 0x00002000 -#define GPIO_DIN31_0_DIO13_BITN 13 -#define GPIO_DIN31_0_DIO13_M 0x00002000 -#define GPIO_DIN31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Data input from DIO 12 -#define GPIO_DIN31_0_DIO12 0x00001000 -#define GPIO_DIN31_0_DIO12_BITN 12 -#define GPIO_DIN31_0_DIO12_M 0x00001000 -#define GPIO_DIN31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Data input from DIO 11 -#define GPIO_DIN31_0_DIO11 0x00000800 -#define GPIO_DIN31_0_DIO11_BITN 11 -#define GPIO_DIN31_0_DIO11_M 0x00000800 -#define GPIO_DIN31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Data input from DIO 10 -#define GPIO_DIN31_0_DIO10 0x00000400 -#define GPIO_DIN31_0_DIO10_BITN 10 -#define GPIO_DIN31_0_DIO10_M 0x00000400 -#define GPIO_DIN31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Data input from DIO 9 -#define GPIO_DIN31_0_DIO9 0x00000200 -#define GPIO_DIN31_0_DIO9_BITN 9 -#define GPIO_DIN31_0_DIO9_M 0x00000200 -#define GPIO_DIN31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Data input from DIO 8 -#define GPIO_DIN31_0_DIO8 0x00000100 -#define GPIO_DIN31_0_DIO8_BITN 8 -#define GPIO_DIN31_0_DIO8_M 0x00000100 -#define GPIO_DIN31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Data input from DIO 7 -#define GPIO_DIN31_0_DIO7 0x00000080 -#define GPIO_DIN31_0_DIO7_BITN 7 -#define GPIO_DIN31_0_DIO7_M 0x00000080 -#define GPIO_DIN31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Data input from DIO 6 -#define GPIO_DIN31_0_DIO6 0x00000040 -#define GPIO_DIN31_0_DIO6_BITN 6 -#define GPIO_DIN31_0_DIO6_M 0x00000040 -#define GPIO_DIN31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Data input from DIO 5 -#define GPIO_DIN31_0_DIO5 0x00000020 -#define GPIO_DIN31_0_DIO5_BITN 5 -#define GPIO_DIN31_0_DIO5_M 0x00000020 -#define GPIO_DIN31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Data input from DIO 4 -#define GPIO_DIN31_0_DIO4 0x00000010 -#define GPIO_DIN31_0_DIO4_BITN 4 -#define GPIO_DIN31_0_DIO4_M 0x00000010 -#define GPIO_DIN31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Data input from DIO 3 -#define GPIO_DIN31_0_DIO3 0x00000008 -#define GPIO_DIN31_0_DIO3_BITN 3 -#define GPIO_DIN31_0_DIO3_M 0x00000008 -#define GPIO_DIN31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Data input from DIO 2 -#define GPIO_DIN31_0_DIO2 0x00000004 -#define GPIO_DIN31_0_DIO2_BITN 2 -#define GPIO_DIN31_0_DIO2_M 0x00000004 -#define GPIO_DIN31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Data input from DIO 1 -#define GPIO_DIN31_0_DIO1 0x00000002 -#define GPIO_DIN31_0_DIO1_BITN 1 -#define GPIO_DIN31_0_DIO1_M 0x00000002 -#define GPIO_DIN31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Data input from DIO 0 -#define GPIO_DIN31_0_DIO0 0x00000001 -#define GPIO_DIN31_0_DIO0_BITN 0 -#define GPIO_DIN31_0_DIO0_M 0x00000001 -#define GPIO_DIN31_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_DOE31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Data output enable for DIO 31 -#define GPIO_DOE31_0_DIO31 0x80000000 -#define GPIO_DOE31_0_DIO31_BITN 31 -#define GPIO_DOE31_0_DIO31_M 0x80000000 -#define GPIO_DOE31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Data output enable for DIO 30 -#define GPIO_DOE31_0_DIO30 0x40000000 -#define GPIO_DOE31_0_DIO30_BITN 30 -#define GPIO_DOE31_0_DIO30_M 0x40000000 -#define GPIO_DOE31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Data output enable for DIO 29 -#define GPIO_DOE31_0_DIO29 0x20000000 -#define GPIO_DOE31_0_DIO29_BITN 29 -#define GPIO_DOE31_0_DIO29_M 0x20000000 -#define GPIO_DOE31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Data output enable for DIO 28 -#define GPIO_DOE31_0_DIO28 0x10000000 -#define GPIO_DOE31_0_DIO28_BITN 28 -#define GPIO_DOE31_0_DIO28_M 0x10000000 -#define GPIO_DOE31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Data output enable for DIO 27 -#define GPIO_DOE31_0_DIO27 0x08000000 -#define GPIO_DOE31_0_DIO27_BITN 27 -#define GPIO_DOE31_0_DIO27_M 0x08000000 -#define GPIO_DOE31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Data output enable for DIO 26 -#define GPIO_DOE31_0_DIO26 0x04000000 -#define GPIO_DOE31_0_DIO26_BITN 26 -#define GPIO_DOE31_0_DIO26_M 0x04000000 -#define GPIO_DOE31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Data output enable for DIO 25 -#define GPIO_DOE31_0_DIO25 0x02000000 -#define GPIO_DOE31_0_DIO25_BITN 25 -#define GPIO_DOE31_0_DIO25_M 0x02000000 -#define GPIO_DOE31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Data output enable for DIO 24 -#define GPIO_DOE31_0_DIO24 0x01000000 -#define GPIO_DOE31_0_DIO24_BITN 24 -#define GPIO_DOE31_0_DIO24_M 0x01000000 -#define GPIO_DOE31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Data output enable for DIO 23 -#define GPIO_DOE31_0_DIO23 0x00800000 -#define GPIO_DOE31_0_DIO23_BITN 23 -#define GPIO_DOE31_0_DIO23_M 0x00800000 -#define GPIO_DOE31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Data output enable for DIO 22 -#define GPIO_DOE31_0_DIO22 0x00400000 -#define GPIO_DOE31_0_DIO22_BITN 22 -#define GPIO_DOE31_0_DIO22_M 0x00400000 -#define GPIO_DOE31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Data output enable for DIO 21 -#define GPIO_DOE31_0_DIO21 0x00200000 -#define GPIO_DOE31_0_DIO21_BITN 21 -#define GPIO_DOE31_0_DIO21_M 0x00200000 -#define GPIO_DOE31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Data output enable for DIO 20 -#define GPIO_DOE31_0_DIO20 0x00100000 -#define GPIO_DOE31_0_DIO20_BITN 20 -#define GPIO_DOE31_0_DIO20_M 0x00100000 -#define GPIO_DOE31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Data output enable for DIO 19 -#define GPIO_DOE31_0_DIO19 0x00080000 -#define GPIO_DOE31_0_DIO19_BITN 19 -#define GPIO_DOE31_0_DIO19_M 0x00080000 -#define GPIO_DOE31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Data output enable for DIO 18 -#define GPIO_DOE31_0_DIO18 0x00040000 -#define GPIO_DOE31_0_DIO18_BITN 18 -#define GPIO_DOE31_0_DIO18_M 0x00040000 -#define GPIO_DOE31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Data output enable for DIO 17 -#define GPIO_DOE31_0_DIO17 0x00020000 -#define GPIO_DOE31_0_DIO17_BITN 17 -#define GPIO_DOE31_0_DIO17_M 0x00020000 -#define GPIO_DOE31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Data output enable for DIO 16 -#define GPIO_DOE31_0_DIO16 0x00010000 -#define GPIO_DOE31_0_DIO16_BITN 16 -#define GPIO_DOE31_0_DIO16_M 0x00010000 -#define GPIO_DOE31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Data output enable for DIO 15 -#define GPIO_DOE31_0_DIO15 0x00008000 -#define GPIO_DOE31_0_DIO15_BITN 15 -#define GPIO_DOE31_0_DIO15_M 0x00008000 -#define GPIO_DOE31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Data output enable for DIO 14 -#define GPIO_DOE31_0_DIO14 0x00004000 -#define GPIO_DOE31_0_DIO14_BITN 14 -#define GPIO_DOE31_0_DIO14_M 0x00004000 -#define GPIO_DOE31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Data output enable for DIO 13 -#define GPIO_DOE31_0_DIO13 0x00002000 -#define GPIO_DOE31_0_DIO13_BITN 13 -#define GPIO_DOE31_0_DIO13_M 0x00002000 -#define GPIO_DOE31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Data output enable for DIO 12 -#define GPIO_DOE31_0_DIO12 0x00001000 -#define GPIO_DOE31_0_DIO12_BITN 12 -#define GPIO_DOE31_0_DIO12_M 0x00001000 -#define GPIO_DOE31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Data output enable for DIO 11 -#define GPIO_DOE31_0_DIO11 0x00000800 -#define GPIO_DOE31_0_DIO11_BITN 11 -#define GPIO_DOE31_0_DIO11_M 0x00000800 -#define GPIO_DOE31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Data output enable for DIO 10 -#define GPIO_DOE31_0_DIO10 0x00000400 -#define GPIO_DOE31_0_DIO10_BITN 10 -#define GPIO_DOE31_0_DIO10_M 0x00000400 -#define GPIO_DOE31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Data output enable for DIO 9 -#define GPIO_DOE31_0_DIO9 0x00000200 -#define GPIO_DOE31_0_DIO9_BITN 9 -#define GPIO_DOE31_0_DIO9_M 0x00000200 -#define GPIO_DOE31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Data output enable for DIO 8 -#define GPIO_DOE31_0_DIO8 0x00000100 -#define GPIO_DOE31_0_DIO8_BITN 8 -#define GPIO_DOE31_0_DIO8_M 0x00000100 -#define GPIO_DOE31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Data output enable for DIO 7 -#define GPIO_DOE31_0_DIO7 0x00000080 -#define GPIO_DOE31_0_DIO7_BITN 7 -#define GPIO_DOE31_0_DIO7_M 0x00000080 -#define GPIO_DOE31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Data output enable for DIO 6 -#define GPIO_DOE31_0_DIO6 0x00000040 -#define GPIO_DOE31_0_DIO6_BITN 6 -#define GPIO_DOE31_0_DIO6_M 0x00000040 -#define GPIO_DOE31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Data output enable for DIO 5 -#define GPIO_DOE31_0_DIO5 0x00000020 -#define GPIO_DOE31_0_DIO5_BITN 5 -#define GPIO_DOE31_0_DIO5_M 0x00000020 -#define GPIO_DOE31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Data output enable for DIO 4 -#define GPIO_DOE31_0_DIO4 0x00000010 -#define GPIO_DOE31_0_DIO4_BITN 4 -#define GPIO_DOE31_0_DIO4_M 0x00000010 -#define GPIO_DOE31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Data output enable for DIO 3 -#define GPIO_DOE31_0_DIO3 0x00000008 -#define GPIO_DOE31_0_DIO3_BITN 3 -#define GPIO_DOE31_0_DIO3_M 0x00000008 -#define GPIO_DOE31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Data output enable for DIO 2 -#define GPIO_DOE31_0_DIO2 0x00000004 -#define GPIO_DOE31_0_DIO2_BITN 2 -#define GPIO_DOE31_0_DIO2_M 0x00000004 -#define GPIO_DOE31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Data output enable for DIO 1 -#define GPIO_DOE31_0_DIO1 0x00000002 -#define GPIO_DOE31_0_DIO1_BITN 1 -#define GPIO_DOE31_0_DIO1_M 0x00000002 -#define GPIO_DOE31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Data output enable for DIO 0 -#define GPIO_DOE31_0_DIO0 0x00000001 -#define GPIO_DOE31_0_DIO0_BITN 0 -#define GPIO_DOE31_0_DIO0_M 0x00000001 -#define GPIO_DOE31_0_DIO0_S 0 - -//***************************************************************************** -// -// Register: GPIO_O_EVFLAGS31_0 -// -//***************************************************************************** -// Field: [31] DIO31 -// -// Event for DIO 31 -#define GPIO_EVFLAGS31_0_DIO31 0x80000000 -#define GPIO_EVFLAGS31_0_DIO31_BITN 31 -#define GPIO_EVFLAGS31_0_DIO31_M 0x80000000 -#define GPIO_EVFLAGS31_0_DIO31_S 31 - -// Field: [30] DIO30 -// -// Event for DIO 30 -#define GPIO_EVFLAGS31_0_DIO30 0x40000000 -#define GPIO_EVFLAGS31_0_DIO30_BITN 30 -#define GPIO_EVFLAGS31_0_DIO30_M 0x40000000 -#define GPIO_EVFLAGS31_0_DIO30_S 30 - -// Field: [29] DIO29 -// -// Event for DIO 29 -#define GPIO_EVFLAGS31_0_DIO29 0x20000000 -#define GPIO_EVFLAGS31_0_DIO29_BITN 29 -#define GPIO_EVFLAGS31_0_DIO29_M 0x20000000 -#define GPIO_EVFLAGS31_0_DIO29_S 29 - -// Field: [28] DIO28 -// -// Event for DIO 28 -#define GPIO_EVFLAGS31_0_DIO28 0x10000000 -#define GPIO_EVFLAGS31_0_DIO28_BITN 28 -#define GPIO_EVFLAGS31_0_DIO28_M 0x10000000 -#define GPIO_EVFLAGS31_0_DIO28_S 28 - -// Field: [27] DIO27 -// -// Event for DIO 27 -#define GPIO_EVFLAGS31_0_DIO27 0x08000000 -#define GPIO_EVFLAGS31_0_DIO27_BITN 27 -#define GPIO_EVFLAGS31_0_DIO27_M 0x08000000 -#define GPIO_EVFLAGS31_0_DIO27_S 27 - -// Field: [26] DIO26 -// -// Event for DIO 26 -#define GPIO_EVFLAGS31_0_DIO26 0x04000000 -#define GPIO_EVFLAGS31_0_DIO26_BITN 26 -#define GPIO_EVFLAGS31_0_DIO26_M 0x04000000 -#define GPIO_EVFLAGS31_0_DIO26_S 26 - -// Field: [25] DIO25 -// -// Event for DIO 25 -#define GPIO_EVFLAGS31_0_DIO25 0x02000000 -#define GPIO_EVFLAGS31_0_DIO25_BITN 25 -#define GPIO_EVFLAGS31_0_DIO25_M 0x02000000 -#define GPIO_EVFLAGS31_0_DIO25_S 25 - -// Field: [24] DIO24 -// -// Event for DIO 24 -#define GPIO_EVFLAGS31_0_DIO24 0x01000000 -#define GPIO_EVFLAGS31_0_DIO24_BITN 24 -#define GPIO_EVFLAGS31_0_DIO24_M 0x01000000 -#define GPIO_EVFLAGS31_0_DIO24_S 24 - -// Field: [23] DIO23 -// -// Event for DIO 23 -#define GPIO_EVFLAGS31_0_DIO23 0x00800000 -#define GPIO_EVFLAGS31_0_DIO23_BITN 23 -#define GPIO_EVFLAGS31_0_DIO23_M 0x00800000 -#define GPIO_EVFLAGS31_0_DIO23_S 23 - -// Field: [22] DIO22 -// -// Event for DIO 22 -#define GPIO_EVFLAGS31_0_DIO22 0x00400000 -#define GPIO_EVFLAGS31_0_DIO22_BITN 22 -#define GPIO_EVFLAGS31_0_DIO22_M 0x00400000 -#define GPIO_EVFLAGS31_0_DIO22_S 22 - -// Field: [21] DIO21 -// -// Event for DIO 21 -#define GPIO_EVFLAGS31_0_DIO21 0x00200000 -#define GPIO_EVFLAGS31_0_DIO21_BITN 21 -#define GPIO_EVFLAGS31_0_DIO21_M 0x00200000 -#define GPIO_EVFLAGS31_0_DIO21_S 21 - -// Field: [20] DIO20 -// -// Event for DIO 20 -#define GPIO_EVFLAGS31_0_DIO20 0x00100000 -#define GPIO_EVFLAGS31_0_DIO20_BITN 20 -#define GPIO_EVFLAGS31_0_DIO20_M 0x00100000 -#define GPIO_EVFLAGS31_0_DIO20_S 20 - -// Field: [19] DIO19 -// -// Event for DIO 19 -#define GPIO_EVFLAGS31_0_DIO19 0x00080000 -#define GPIO_EVFLAGS31_0_DIO19_BITN 19 -#define GPIO_EVFLAGS31_0_DIO19_M 0x00080000 -#define GPIO_EVFLAGS31_0_DIO19_S 19 - -// Field: [18] DIO18 -// -// Event for DIO 18 -#define GPIO_EVFLAGS31_0_DIO18 0x00040000 -#define GPIO_EVFLAGS31_0_DIO18_BITN 18 -#define GPIO_EVFLAGS31_0_DIO18_M 0x00040000 -#define GPIO_EVFLAGS31_0_DIO18_S 18 - -// Field: [17] DIO17 -// -// Event for DIO 17 -#define GPIO_EVFLAGS31_0_DIO17 0x00020000 -#define GPIO_EVFLAGS31_0_DIO17_BITN 17 -#define GPIO_EVFLAGS31_0_DIO17_M 0x00020000 -#define GPIO_EVFLAGS31_0_DIO17_S 17 - -// Field: [16] DIO16 -// -// Event for DIO 16 -#define GPIO_EVFLAGS31_0_DIO16 0x00010000 -#define GPIO_EVFLAGS31_0_DIO16_BITN 16 -#define GPIO_EVFLAGS31_0_DIO16_M 0x00010000 -#define GPIO_EVFLAGS31_0_DIO16_S 16 - -// Field: [15] DIO15 -// -// Event for DIO 15 -#define GPIO_EVFLAGS31_0_DIO15 0x00008000 -#define GPIO_EVFLAGS31_0_DIO15_BITN 15 -#define GPIO_EVFLAGS31_0_DIO15_M 0x00008000 -#define GPIO_EVFLAGS31_0_DIO15_S 15 - -// Field: [14] DIO14 -// -// Event for DIO 14 -#define GPIO_EVFLAGS31_0_DIO14 0x00004000 -#define GPIO_EVFLAGS31_0_DIO14_BITN 14 -#define GPIO_EVFLAGS31_0_DIO14_M 0x00004000 -#define GPIO_EVFLAGS31_0_DIO14_S 14 - -// Field: [13] DIO13 -// -// Event for DIO 13 -#define GPIO_EVFLAGS31_0_DIO13 0x00002000 -#define GPIO_EVFLAGS31_0_DIO13_BITN 13 -#define GPIO_EVFLAGS31_0_DIO13_M 0x00002000 -#define GPIO_EVFLAGS31_0_DIO13_S 13 - -// Field: [12] DIO12 -// -// Event for DIO 12 -#define GPIO_EVFLAGS31_0_DIO12 0x00001000 -#define GPIO_EVFLAGS31_0_DIO12_BITN 12 -#define GPIO_EVFLAGS31_0_DIO12_M 0x00001000 -#define GPIO_EVFLAGS31_0_DIO12_S 12 - -// Field: [11] DIO11 -// -// Event for DIO 11 -#define GPIO_EVFLAGS31_0_DIO11 0x00000800 -#define GPIO_EVFLAGS31_0_DIO11_BITN 11 -#define GPIO_EVFLAGS31_0_DIO11_M 0x00000800 -#define GPIO_EVFLAGS31_0_DIO11_S 11 - -// Field: [10] DIO10 -// -// Event for DIO 10 -#define GPIO_EVFLAGS31_0_DIO10 0x00000400 -#define GPIO_EVFLAGS31_0_DIO10_BITN 10 -#define GPIO_EVFLAGS31_0_DIO10_M 0x00000400 -#define GPIO_EVFLAGS31_0_DIO10_S 10 - -// Field: [9] DIO9 -// -// Event for DIO 9 -#define GPIO_EVFLAGS31_0_DIO9 0x00000200 -#define GPIO_EVFLAGS31_0_DIO9_BITN 9 -#define GPIO_EVFLAGS31_0_DIO9_M 0x00000200 -#define GPIO_EVFLAGS31_0_DIO9_S 9 - -// Field: [8] DIO8 -// -// Event for DIO 8 -#define GPIO_EVFLAGS31_0_DIO8 0x00000100 -#define GPIO_EVFLAGS31_0_DIO8_BITN 8 -#define GPIO_EVFLAGS31_0_DIO8_M 0x00000100 -#define GPIO_EVFLAGS31_0_DIO8_S 8 - -// Field: [7] DIO7 -// -// Event for DIO 7 -#define GPIO_EVFLAGS31_0_DIO7 0x00000080 -#define GPIO_EVFLAGS31_0_DIO7_BITN 7 -#define GPIO_EVFLAGS31_0_DIO7_M 0x00000080 -#define GPIO_EVFLAGS31_0_DIO7_S 7 - -// Field: [6] DIO6 -// -// Event for DIO 6 -#define GPIO_EVFLAGS31_0_DIO6 0x00000040 -#define GPIO_EVFLAGS31_0_DIO6_BITN 6 -#define GPIO_EVFLAGS31_0_DIO6_M 0x00000040 -#define GPIO_EVFLAGS31_0_DIO6_S 6 - -// Field: [5] DIO5 -// -// Event for DIO 5 -#define GPIO_EVFLAGS31_0_DIO5 0x00000020 -#define GPIO_EVFLAGS31_0_DIO5_BITN 5 -#define GPIO_EVFLAGS31_0_DIO5_M 0x00000020 -#define GPIO_EVFLAGS31_0_DIO5_S 5 - -// Field: [4] DIO4 -// -// Event for DIO 4 -#define GPIO_EVFLAGS31_0_DIO4 0x00000010 -#define GPIO_EVFLAGS31_0_DIO4_BITN 4 -#define GPIO_EVFLAGS31_0_DIO4_M 0x00000010 -#define GPIO_EVFLAGS31_0_DIO4_S 4 - -// Field: [3] DIO3 -// -// Event for DIO 3 -#define GPIO_EVFLAGS31_0_DIO3 0x00000008 -#define GPIO_EVFLAGS31_0_DIO3_BITN 3 -#define GPIO_EVFLAGS31_0_DIO3_M 0x00000008 -#define GPIO_EVFLAGS31_0_DIO3_S 3 - -// Field: [2] DIO2 -// -// Event for DIO 2 -#define GPIO_EVFLAGS31_0_DIO2 0x00000004 -#define GPIO_EVFLAGS31_0_DIO2_BITN 2 -#define GPIO_EVFLAGS31_0_DIO2_M 0x00000004 -#define GPIO_EVFLAGS31_0_DIO2_S 2 - -// Field: [1] DIO1 -// -// Event for DIO 1 -#define GPIO_EVFLAGS31_0_DIO1 0x00000002 -#define GPIO_EVFLAGS31_0_DIO1_BITN 1 -#define GPIO_EVFLAGS31_0_DIO1_M 0x00000002 -#define GPIO_EVFLAGS31_0_DIO1_S 1 - -// Field: [0] DIO0 -// -// Event for DIO 0 -#define GPIO_EVFLAGS31_0_DIO0 0x00000001 -#define GPIO_EVFLAGS31_0_DIO0_BITN 0 -#define GPIO_EVFLAGS31_0_DIO0_M 0x00000001 -#define GPIO_EVFLAGS31_0_DIO0_S 0 - - -#endif // __GPIO__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h deleted file mode 100644 index 1042a0f1204..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpram.h +++ /dev/null @@ -1,48 +0,0 @@ -/****************************************************************************** -* Filename: hw_gpram_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_GPRAM_H__ -#define __HW_GPRAM_H__ - - -#define GPRAM_O_BANK0 0x00000000 -#define GPRAM_BANK0_BYTE_SIZE 8192 - -#define GPRAM_TOT_BYTE_SIZE 8192 - - - -#endif // __HW_GPRAM__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h deleted file mode 100644 index 5cf056ea56f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_gpt.h +++ /dev/null @@ -1,1697 +0,0 @@ -/****************************************************************************** -* Filename: hw_gpt_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_GPT_H__ -#define __HW_GPT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// GPT component -// -//***************************************************************************** -// Configuration -#define GPT_O_CFG 0x00000000 - -// Timer A Mode -#define GPT_O_TAMR 0x00000004 - -// Timer B Mode -#define GPT_O_TBMR 0x00000008 - -// Control -#define GPT_O_CTL 0x0000000C - -// Synch Register -#define GPT_O_SYNC 0x00000010 - -// Interrupt Mask -#define GPT_O_IMR 0x00000018 - -// Raw Interrupt Status -#define GPT_O_RIS 0x0000001C - -// Masked Interrupt Status -#define GPT_O_MIS 0x00000020 - -// Interrupt Clear -#define GPT_O_ICLR 0x00000024 - -// Timer A Interval Load Register -#define GPT_O_TAILR 0x00000028 - -// Timer B Interval Load Register -#define GPT_O_TBILR 0x0000002C - -// Timer A Match Register -#define GPT_O_TAMATCHR 0x00000030 - -// Timer B Match Register -#define GPT_O_TBMATCHR 0x00000034 - -// Timer A Pre-scale -#define GPT_O_TAPR 0x00000038 - -// Timer B Pre-scale -#define GPT_O_TBPR 0x0000003C - -// Timer A Pre-scale Match -#define GPT_O_TAPMR 0x00000040 - -// Timer B Pre-scale Match -#define GPT_O_TBPMR 0x00000044 - -// Timer A Register -#define GPT_O_TAR 0x00000048 - -// Timer B Register -#define GPT_O_TBR 0x0000004C - -// Timer A Value -#define GPT_O_TAV 0x00000050 - -// Timer B Value -#define GPT_O_TBV 0x00000054 - -// Timer A Pre-scale Snap-shot -#define GPT_O_TAPS 0x0000005C - -// Timer B Pre-scale Snap-shot -#define GPT_O_TBPS 0x00000060 - -// Timer A Pre-scale Value -#define GPT_O_TAPV 0x00000064 - -// Timer B Pre-scale Value -#define GPT_O_TBPV 0x00000068 - -// DMA Event -#define GPT_O_DMAEV 0x0000006C - -// Peripheral Version -#define GPT_O_VERSION 0x00000FB0 - -// Combined CCP Output -#define GPT_O_ANDCCP 0x00000FB4 - -//***************************************************************************** -// -// Register: GPT_O_CFG -// -//***************************************************************************** -// Field: [2:0] CFG -// -// GPT Configuration -// 0x2- 0x3 - Reserved -// 0x5- 0x7 - Reserved -// ENUMs: -// 16BIT_TIMER 16-bit timer configuration. -// Configure for two 16-bit -// timers. -// Also see TAMR.TAMR and -// TBMR.TBMR. -// 32BIT_TIMER 32-bit timer configuration -#define GPT_CFG_CFG_W 3 -#define GPT_CFG_CFG_M 0x00000007 -#define GPT_CFG_CFG_S 0 -#define GPT_CFG_CFG_16BIT_TIMER 0x00000004 -#define GPT_CFG_CFG_32BIT_TIMER 0x00000000 - -//***************************************************************************** -// -// Register: GPT_O_TAMR -// -//***************************************************************************** -// Field: [15:13] TCACT -// -// Timer Compare Action Select -// ENUMs: -// CLRSET_ON_TO Clear CCP output pin immediately and set on -// Time-Out -// SETCLR_ON_TO Set CCP output pin immediately and clear on -// Time-Out -// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on -// Time-Out -// SETTOG_ON_TO Set CCP output pin immediately and toggle on -// Time-Out -// SET_ON_TO Set CCP output pin on Time-Out -// CLR_ON_TO Clear CCP output pin on Time-Out -// TOG_ON_TO Toggle State on Time-Out -// DIS_CMP Disable compare operations -#define GPT_TAMR_TCACT_W 3 -#define GPT_TAMR_TCACT_M 0x0000E000 -#define GPT_TAMR_TCACT_S 13 -#define GPT_TAMR_TCACT_CLRSET_ON_TO 0x0000E000 -#define GPT_TAMR_TCACT_SETCLR_ON_TO 0x0000C000 -#define GPT_TAMR_TCACT_CLRTOG_ON_TO 0x0000A000 -#define GPT_TAMR_TCACT_SETTOG_ON_TO 0x00008000 -#define GPT_TAMR_TCACT_SET_ON_TO 0x00006000 -#define GPT_TAMR_TCACT_CLR_ON_TO 0x00004000 -#define GPT_TAMR_TCACT_TOG_ON_TO 0x00002000 -#define GPT_TAMR_TCACT_DIS_CMP 0x00000000 - -// Field: [12] TACINTD -// -// One-Shot/Periodic Interrupt Disable -// ENUMs: -// DIS_TO_INTR Time-out interrupt are disabled -// EN_TO_INTR Time-out interrupt function as normal -#define GPT_TAMR_TACINTD 0x00001000 -#define GPT_TAMR_TACINTD_BITN 12 -#define GPT_TAMR_TACINTD_M 0x00001000 -#define GPT_TAMR_TACINTD_S 12 -#define GPT_TAMR_TACINTD_DIS_TO_INTR 0x00001000 -#define GPT_TAMR_TACINTD_EN_TO_INTR 0x00000000 - -// Field: [11] TAPLO -// -// GPTM Timer A PWM Legacy Operation -// -// 0 Legacy operation with CCP pin driven Low when the TAILR -// register is reloaded after the timer reaches 0. -// -// 1 CCP is driven High when the TAILR register is reloaded after the timer -// reaches 0. -// -// This bit is only valid in PWM mode. -// ENUMs: -// CCP_ON_TO CCP output pin is set to 1 on time-out -// LEGACY Legacy operation -#define GPT_TAMR_TAPLO 0x00000800 -#define GPT_TAMR_TAPLO_BITN 11 -#define GPT_TAMR_TAPLO_M 0x00000800 -#define GPT_TAMR_TAPLO_S 11 -#define GPT_TAMR_TAPLO_CCP_ON_TO 0x00000800 -#define GPT_TAMR_TAPLO_LEGACY 0x00000000 - -// Field: [10] TAMRSU -// -// Timer A Match Register Update mode -// -// This bit defines when the TAMATCHR and TAPR registers are updated. -// -// If the timer is disabled (CTL.TAEN = 0) when this bit is set, TAMATCHR and -// TAPR are updated when the timer is enabled. -// If the timer is stalled (CTL.TASTALL = 1) when this bit is set, TAMATCHR and -// TAPR are updated according to the configuration of this bit. -// ENUMs: -// TOUPDATE Update TAMATCHR and TAPR, if used, on the next -// time-out. -// CYCLEUPDATE Update TAMATCHR and TAPR, if used, on the next -// cycle. -#define GPT_TAMR_TAMRSU 0x00000400 -#define GPT_TAMR_TAMRSU_BITN 10 -#define GPT_TAMR_TAMRSU_M 0x00000400 -#define GPT_TAMR_TAMRSU_S 10 -#define GPT_TAMR_TAMRSU_TOUPDATE 0x00000400 -#define GPT_TAMR_TAMRSU_CYCLEUPDATE 0x00000000 - -// Field: [9] TAPWMIE -// -// GPTM Timer A PWM Interrupt Enable -// This bit enables interrupts in PWM mode on rising, falling, or both edges of -// the CCP output, as defined by the CTL.TAEVENT -// In addition, when this bit is set and a capture event occurs, Timer A -// automatically generates triggers to the DMA if the trigger capability is -// enabled by setting the CTL.TAOTE bit and the DMAEV.CAEDMAEN bit -// respectively. -// -// 0 Capture event interrupt is disabled. -// 1 Capture event interrupt is enabled. -// This bit is only valid in PWM mode. -// ENUMs: -// EN Interrupt is enabled. This bit is only valid in -// PWM mode. -// DIS Interrupt is disabled. -#define GPT_TAMR_TAPWMIE 0x00000200 -#define GPT_TAMR_TAPWMIE_BITN 9 -#define GPT_TAMR_TAPWMIE_M 0x00000200 -#define GPT_TAMR_TAPWMIE_S 9 -#define GPT_TAMR_TAPWMIE_EN 0x00000200 -#define GPT_TAMR_TAPWMIE_DIS 0x00000000 - -// Field: [8] TAILD -// -// GPT Timer A PWM Interval Load Write -// ENUMs: -// TOUPDATE Update the TAR register with the value in the -// TAILR register on the next timeout. If the -// prescaler is used, update the TAPS register -// with the value in the TAPR register on the next -// timeout. -// CYCLEUPDATE Update the TAR register with the value in the -// TAILR register on the next clock cycle. If the -// pre-scaler is used, update the TAPS register -// with the value in the TAPR register on the next -// clock cycle. -#define GPT_TAMR_TAILD 0x00000100 -#define GPT_TAMR_TAILD_BITN 8 -#define GPT_TAMR_TAILD_M 0x00000100 -#define GPT_TAMR_TAILD_S 8 -#define GPT_TAMR_TAILD_TOUPDATE 0x00000100 -#define GPT_TAMR_TAILD_CYCLEUPDATE 0x00000000 - -// Field: [7] TASNAPS -// -// GPT Timer A Snap-Shot Mode -// ENUMs: -// EN If Timer A is configured in the periodic mode, the -// actual free-running value of Timer A is loaded -// at the time-out event into the GPT Timer A -// (TAR) register. -// DIS Snap-shot mode is disabled. -#define GPT_TAMR_TASNAPS 0x00000080 -#define GPT_TAMR_TASNAPS_BITN 7 -#define GPT_TAMR_TASNAPS_M 0x00000080 -#define GPT_TAMR_TASNAPS_S 7 -#define GPT_TAMR_TASNAPS_EN 0x00000080 -#define GPT_TAMR_TASNAPS_DIS 0x00000000 - -// Field: [6] TAWOT -// -// GPT Timer A Wait-On-Trigger -// ENUMs: -// WAIT If Timer A is enabled (CTL.TAEN = 1), Timer A does -// not begin counting until it receives a trigger -// from the timer in the previous position in the -// daisy chain. This bit must be clear for GPT -// Module 0, Timer A. This function is valid for -// one-shot, periodic, and PWM modes -// NOWAIT Timer A begins counting as soon as it is enabled. -#define GPT_TAMR_TAWOT 0x00000040 -#define GPT_TAMR_TAWOT_BITN 6 -#define GPT_TAMR_TAWOT_M 0x00000040 -#define GPT_TAMR_TAWOT_S 6 -#define GPT_TAMR_TAWOT_WAIT 0x00000040 -#define GPT_TAMR_TAWOT_NOWAIT 0x00000000 - -// Field: [5] TAMIE -// -// GPT Timer A Match Interrupt Enable -// ENUMs: -// EN An interrupt is generated when the match value in -// TAMATCHR is reached in the one-shot and -// periodic modes. -// DIS The match interrupt is disabled for match events. -// Additionally, output triggers on match events -// are prevented. -#define GPT_TAMR_TAMIE 0x00000020 -#define GPT_TAMR_TAMIE_BITN 5 -#define GPT_TAMR_TAMIE_M 0x00000020 -#define GPT_TAMR_TAMIE_S 5 -#define GPT_TAMR_TAMIE_EN 0x00000020 -#define GPT_TAMR_TAMIE_DIS 0x00000000 - -// Field: [4] TACDIR -// -// GPT Timer A Count Direction -// ENUMs: -// UP The timer counts up. When counting up, the timer -// starts from a value of 0x0. -// DOWN The timer counts down. -#define GPT_TAMR_TACDIR 0x00000010 -#define GPT_TAMR_TACDIR_BITN 4 -#define GPT_TAMR_TACDIR_M 0x00000010 -#define GPT_TAMR_TACDIR_S 4 -#define GPT_TAMR_TACDIR_UP 0x00000010 -#define GPT_TAMR_TACDIR_DOWN 0x00000000 - -// Field: [3] TAAMS -// -// GPT Timer A Alternate Mode -// -// Note: To enable PWM mode, you must also clear TACM and then configure TAMR -// field to 0x2. -// ENUMs: -// PWM PWM mode is enabled -// CAP_COMP Capture/Compare mode is enabled. -#define GPT_TAMR_TAAMS 0x00000008 -#define GPT_TAMR_TAAMS_BITN 3 -#define GPT_TAMR_TAAMS_M 0x00000008 -#define GPT_TAMR_TAAMS_S 3 -#define GPT_TAMR_TAAMS_PWM 0x00000008 -#define GPT_TAMR_TAAMS_CAP_COMP 0x00000000 - -// Field: [2] TACM -// -// GPT Timer A Capture Mode -// ENUMs: -// EDGTIME Edge-Time mode -// EDGCNT Edge-Count mode -#define GPT_TAMR_TACM 0x00000004 -#define GPT_TAMR_TACM_BITN 2 -#define GPT_TAMR_TACM_M 0x00000004 -#define GPT_TAMR_TACM_S 2 -#define GPT_TAMR_TACM_EDGTIME 0x00000004 -#define GPT_TAMR_TACM_EDGCNT 0x00000000 - -// Field: [1:0] TAMR -// -// GPT Timer A Mode -// -// 0x0 Reserved -// 0x1 One-Shot Timer mode -// 0x2 Periodic Timer mode -// 0x3 Capture mode -// The Timer mode is based on the timer configuration defined by bits 2:0 in -// the CFG register -// ENUMs: -// CAPTURE Capture mode -// PERIODIC Periodic Timer mode -// ONE_SHOT One-Shot Timer mode -#define GPT_TAMR_TAMR_W 2 -#define GPT_TAMR_TAMR_M 0x00000003 -#define GPT_TAMR_TAMR_S 0 -#define GPT_TAMR_TAMR_CAPTURE 0x00000003 -#define GPT_TAMR_TAMR_PERIODIC 0x00000002 -#define GPT_TAMR_TAMR_ONE_SHOT 0x00000001 - -//***************************************************************************** -// -// Register: GPT_O_TBMR -// -//***************************************************************************** -// Field: [15:13] TCACT -// -// Timer Compare Action Select -// ENUMs: -// CLRSET_ON_TO Clear CCP output pin immediately and set on -// Time-Out -// SETCLR_ON_TO Set CCP output pin immediately and clear on -// Time-Out -// CLRTOG_ON_TO Clear CCP output pin immediately and toggle on -// Time-Out -// SETTOG_ON_TO Set CCP output pin immediately and toggle on -// Time-Out -// SET_ON_TO Set CCP output pin on Time-Out -// CLR_ON_TO Clear CCP output pin on Time-Out -// TOG_ON_TO Toggle State on Time-Out -// DIS_CMP Disable compare operations -#define GPT_TBMR_TCACT_W 3 -#define GPT_TBMR_TCACT_M 0x0000E000 -#define GPT_TBMR_TCACT_S 13 -#define GPT_TBMR_TCACT_CLRSET_ON_TO 0x0000E000 -#define GPT_TBMR_TCACT_SETCLR_ON_TO 0x0000C000 -#define GPT_TBMR_TCACT_CLRTOG_ON_TO 0x0000A000 -#define GPT_TBMR_TCACT_SETTOG_ON_TO 0x00008000 -#define GPT_TBMR_TCACT_SET_ON_TO 0x00006000 -#define GPT_TBMR_TCACT_CLR_ON_TO 0x00004000 -#define GPT_TBMR_TCACT_TOG_ON_TO 0x00002000 -#define GPT_TBMR_TCACT_DIS_CMP 0x00000000 - -// Field: [12] TBCINTD -// -// One-Shot/Periodic Interrupt Mode -// ENUMs: -// DIS_TO_INTR Mask Time-Out Interrupt -// EN_TO_INTR Normal Time-Out Interrupt -#define GPT_TBMR_TBCINTD 0x00001000 -#define GPT_TBMR_TBCINTD_BITN 12 -#define GPT_TBMR_TBCINTD_M 0x00001000 -#define GPT_TBMR_TBCINTD_S 12 -#define GPT_TBMR_TBCINTD_DIS_TO_INTR 0x00001000 -#define GPT_TBMR_TBCINTD_EN_TO_INTR 0x00000000 - -// Field: [11] TBPLO -// -// GPTM Timer B PWM Legacy Operation -// -// 0 Legacy operation with CCP pin driven Low when the TBILR -// register is reloaded after the timer reaches 0. -// -// 1 CCP is driven High when the TBILR register is reloaded after the timer -// reaches 0. -// -// This bit is only valid in PWM mode. -// ENUMs: -// CCP_ON_TO CCP output pin is set to 1 on time-out -// LEGACY Legacy operation -#define GPT_TBMR_TBPLO 0x00000800 -#define GPT_TBMR_TBPLO_BITN 11 -#define GPT_TBMR_TBPLO_M 0x00000800 -#define GPT_TBMR_TBPLO_S 11 -#define GPT_TBMR_TBPLO_CCP_ON_TO 0x00000800 -#define GPT_TBMR_TBPLO_LEGACY 0x00000000 - -// Field: [10] TBMRSU -// -// Timer B Match Register Update mode -// -// This bit defines when the TBMATCHR and TBPR registers are updated -// -// If the timer is disabled (CTL.TBEN is clear) when this bit is set, TBMATCHR -// and TBPR are updated when the timer is enabled. -// If the timer is stalled (CTL.TBSTALL is set) when this bit is set, TBMATCHR -// and TBPR are updated according to the configuration of this bit. -// ENUMs: -// TOUPDATE Update TBMATCHR and TBPR, if used, on the next -// time-out. -// CYCLEUPDATE Update TBMATCHR and TBPR, if used, on the next -// cycle. -#define GPT_TBMR_TBMRSU 0x00000400 -#define GPT_TBMR_TBMRSU_BITN 10 -#define GPT_TBMR_TBMRSU_M 0x00000400 -#define GPT_TBMR_TBMRSU_S 10 -#define GPT_TBMR_TBMRSU_TOUPDATE 0x00000400 -#define GPT_TBMR_TBMRSU_CYCLEUPDATE 0x00000000 - -// Field: [9] TBPWMIE -// -// GPTM Timer B PWM Interrupt Enable -// This bit enables interrupts in PWM mode on rising, falling, or both edges of -// the CCP output, as defined by the CTL.TBEVENT -// In addition, when this bit is set and a capture event occurs, Timer A -// automatically generates triggers to the DMA if the trigger capability is -// enabled by setting the CTL.TBOTE bit and the DMAEV.CBEDMAEN bit -// respectively. -// -// 0 Capture event interrupt is disabled. -// 1 Capture event interrupt is enabled. -// This bit is only valid in PWM mode. -// ENUMs: -// EN Interrupt is enabled. This bit is only valid in -// PWM mode. -// DIS Interrupt is disabled. -#define GPT_TBMR_TBPWMIE 0x00000200 -#define GPT_TBMR_TBPWMIE_BITN 9 -#define GPT_TBMR_TBPWMIE_M 0x00000200 -#define GPT_TBMR_TBPWMIE_S 9 -#define GPT_TBMR_TBPWMIE_EN 0x00000200 -#define GPT_TBMR_TBPWMIE_DIS 0x00000000 - -// Field: [8] TBILD -// -// GPT Timer B PWM Interval Load Write -// ENUMs: -// TOUPDATE Update the TBR register with the value in the -// TBILR register on the next timeout. If the -// prescaler is used, update the TBPS register -// with the value in the TBPR register on the next -// timeout. -// CYCLEUPDATE Update the TBR register with the value in the -// TBILR register on the next clock cycle. If the -// pre-scaler is used, update the TBPS register -// with the value in the TBPR register on the next -// clock cycle. -#define GPT_TBMR_TBILD 0x00000100 -#define GPT_TBMR_TBILD_BITN 8 -#define GPT_TBMR_TBILD_M 0x00000100 -#define GPT_TBMR_TBILD_S 8 -#define GPT_TBMR_TBILD_TOUPDATE 0x00000100 -#define GPT_TBMR_TBILD_CYCLEUPDATE 0x00000000 - -// Field: [7] TBSNAPS -// -// GPT Timer B Snap-Shot Mode -// ENUMs: -// EN If Timer B is configured in the periodic mode -// DIS Snap-shot mode is disabled. -#define GPT_TBMR_TBSNAPS 0x00000080 -#define GPT_TBMR_TBSNAPS_BITN 7 -#define GPT_TBMR_TBSNAPS_M 0x00000080 -#define GPT_TBMR_TBSNAPS_S 7 -#define GPT_TBMR_TBSNAPS_EN 0x00000080 -#define GPT_TBMR_TBSNAPS_DIS 0x00000000 - -// Field: [6] TBWOT -// -// GPT Timer B Wait-On-Trigger -// ENUMs: -// WAIT If Timer B is enabled (CTL.TBEN is set), Timer B -// does not begin counting until it receives a -// trigger from the timer in the previous position -// in the daisy chain. This function is valid for -// one-shot, periodic, and PWM modes -// NOWAIT Timer B begins counting as soon as it is enabled. -#define GPT_TBMR_TBWOT 0x00000040 -#define GPT_TBMR_TBWOT_BITN 6 -#define GPT_TBMR_TBWOT_M 0x00000040 -#define GPT_TBMR_TBWOT_S 6 -#define GPT_TBMR_TBWOT_WAIT 0x00000040 -#define GPT_TBMR_TBWOT_NOWAIT 0x00000000 - -// Field: [5] TBMIE -// -// GPT Timer B Match Interrupt Enable. -// ENUMs: -// EN An interrupt is generated when the match value in -// the TBMATCHR register is reached in the -// one-shot and periodic modes. -// DIS The match interrupt is disabled for match events. -// Additionally, output triggers on match events -// are prevented. -#define GPT_TBMR_TBMIE 0x00000020 -#define GPT_TBMR_TBMIE_BITN 5 -#define GPT_TBMR_TBMIE_M 0x00000020 -#define GPT_TBMR_TBMIE_S 5 -#define GPT_TBMR_TBMIE_EN 0x00000020 -#define GPT_TBMR_TBMIE_DIS 0x00000000 - -// Field: [4] TBCDIR -// -// GPT Timer B Count Direction -// ENUMs: -// UP The timer counts up. When counting up, the timer -// starts from a value of 0x0. -// DOWN The timer counts down. -#define GPT_TBMR_TBCDIR 0x00000010 -#define GPT_TBMR_TBCDIR_BITN 4 -#define GPT_TBMR_TBCDIR_M 0x00000010 -#define GPT_TBMR_TBCDIR_S 4 -#define GPT_TBMR_TBCDIR_UP 0x00000010 -#define GPT_TBMR_TBCDIR_DOWN 0x00000000 - -// Field: [3] TBAMS -// -// GPT Timer B Alternate Mode -// -// Note: To enable PWM mode, you must also clear TBCM bit and configure TBMR -// field to 0x2. -// ENUMs: -// PWM PWM mode is enabled -// CAP_COMP Capture/Compare mode is enabled. -#define GPT_TBMR_TBAMS 0x00000008 -#define GPT_TBMR_TBAMS_BITN 3 -#define GPT_TBMR_TBAMS_M 0x00000008 -#define GPT_TBMR_TBAMS_S 3 -#define GPT_TBMR_TBAMS_PWM 0x00000008 -#define GPT_TBMR_TBAMS_CAP_COMP 0x00000000 - -// Field: [2] TBCM -// -// GPT Timer B Capture Mode -// ENUMs: -// EDGTIME Edge-Time mode -// EDGCNT Edge-Count mode -#define GPT_TBMR_TBCM 0x00000004 -#define GPT_TBMR_TBCM_BITN 2 -#define GPT_TBMR_TBCM_M 0x00000004 -#define GPT_TBMR_TBCM_S 2 -#define GPT_TBMR_TBCM_EDGTIME 0x00000004 -#define GPT_TBMR_TBCM_EDGCNT 0x00000000 - -// Field: [1:0] TBMR -// -// GPT Timer B Mode -// -// 0x0 Reserved -// 0x1 One-Shot Timer mode -// 0x2 Periodic Timer mode -// 0x3 Capture mode -// The Timer mode is based on the timer configuration defined by bits 2:0 in -// the CFG register -// ENUMs: -// CAPTURE Capture mode -// PERIODIC Periodic Timer mode -// ONE_SHOT One-Shot Timer mode -#define GPT_TBMR_TBMR_W 2 -#define GPT_TBMR_TBMR_M 0x00000003 -#define GPT_TBMR_TBMR_S 0 -#define GPT_TBMR_TBMR_CAPTURE 0x00000003 -#define GPT_TBMR_TBMR_PERIODIC 0x00000002 -#define GPT_TBMR_TBMR_ONE_SHOT 0x00000001 - -//***************************************************************************** -// -// Register: GPT_O_CTL -// -//***************************************************************************** -// Field: [14] TBPWML -// -// GPT Timer B PWM Output Level -// -// 0: Output is unaffected. -// 1: Output is inverted. -// ENUMs: -// INVERTED Inverted -// NORMAL Not inverted -#define GPT_CTL_TBPWML 0x00004000 -#define GPT_CTL_TBPWML_BITN 14 -#define GPT_CTL_TBPWML_M 0x00004000 -#define GPT_CTL_TBPWML_S 14 -#define GPT_CTL_TBPWML_INVERTED 0x00004000 -#define GPT_CTL_TBPWML_NORMAL 0x00000000 - -// Field: [11:10] TBEVENT -// -// GPT Timer B Event Mode -// -// The values in this register are defined as follows: -// Value Description -// 0x0 Positive edge -// 0x1 Negative edge -// 0x2 Reserved -// 0x3 Both edges -// Note: If PWM output inversion is enabled, edge detection interrupt -// behavior is reversed. Thus, if a positive-edge interrupt trigger -// has been set and the PWM inversion generates a postive -// edge, no event-trigger interrupt asserts. Instead, the interrupt -// is generated on the negative edge of the PWM signal. -// ENUMs: -// BOTH Both edges -// NEG Negative edge -// POS Positive edge -#define GPT_CTL_TBEVENT_W 2 -#define GPT_CTL_TBEVENT_M 0x00000C00 -#define GPT_CTL_TBEVENT_S 10 -#define GPT_CTL_TBEVENT_BOTH 0x00000C00 -#define GPT_CTL_TBEVENT_NEG 0x00000400 -#define GPT_CTL_TBEVENT_POS 0x00000000 - -// Field: [9] TBSTALL -// -// GPT Timer B Stall Enable -// ENUMs: -// EN Timer B freezes counting while the processor is -// halted by the debugger. -// DIS Timer B continues counting while the processor is -// halted by the debugger. -#define GPT_CTL_TBSTALL 0x00000200 -#define GPT_CTL_TBSTALL_BITN 9 -#define GPT_CTL_TBSTALL_M 0x00000200 -#define GPT_CTL_TBSTALL_S 9 -#define GPT_CTL_TBSTALL_EN 0x00000200 -#define GPT_CTL_TBSTALL_DIS 0x00000000 - -// Field: [8] TBEN -// -// GPT Timer B Enable -// ENUMs: -// EN Timer B is enabled and begins counting or the -// capture logic is enabled based on CFG register. -// DIS Timer B is disabled. -#define GPT_CTL_TBEN 0x00000100 -#define GPT_CTL_TBEN_BITN 8 -#define GPT_CTL_TBEN_M 0x00000100 -#define GPT_CTL_TBEN_S 8 -#define GPT_CTL_TBEN_EN 0x00000100 -#define GPT_CTL_TBEN_DIS 0x00000000 - -// Field: [6] TAPWML -// -// GPT Timer A PWM Output Level -// ENUMs: -// INVERTED Inverted -// NORMAL Not inverted -#define GPT_CTL_TAPWML 0x00000040 -#define GPT_CTL_TAPWML_BITN 6 -#define GPT_CTL_TAPWML_M 0x00000040 -#define GPT_CTL_TAPWML_S 6 -#define GPT_CTL_TAPWML_INVERTED 0x00000040 -#define GPT_CTL_TAPWML_NORMAL 0x00000000 - -// Field: [3:2] TAEVENT -// -// GPT Timer A Event Mode -// -// The values in this register are defined as follows: -// Value Description -// 0x0 Positive edge -// 0x1 Negative edge -// 0x2 Reserved -// 0x3 Both edges -// Note: If PWM output inversion is enabled, edge detection interrupt -// behavior is reversed. Thus, if a positive-edge interrupt trigger -// has been set and the PWM inversion generates a postive -// edge, no event-trigger interrupt asserts. Instead, the interrupt -// is generated on the negative edge of the PWM signal. -// ENUMs: -// BOTH Both edges -// NEG Negative edge -// POS Positive edge -#define GPT_CTL_TAEVENT_W 2 -#define GPT_CTL_TAEVENT_M 0x0000000C -#define GPT_CTL_TAEVENT_S 2 -#define GPT_CTL_TAEVENT_BOTH 0x0000000C -#define GPT_CTL_TAEVENT_NEG 0x00000004 -#define GPT_CTL_TAEVENT_POS 0x00000000 - -// Field: [1] TASTALL -// -// GPT Timer A Stall Enable -// ENUMs: -// EN Timer A freezes counting while the processor is -// halted by the debugger. -// DIS Timer A continues counting while the processor is -// halted by the debugger. -#define GPT_CTL_TASTALL 0x00000002 -#define GPT_CTL_TASTALL_BITN 1 -#define GPT_CTL_TASTALL_M 0x00000002 -#define GPT_CTL_TASTALL_S 1 -#define GPT_CTL_TASTALL_EN 0x00000002 -#define GPT_CTL_TASTALL_DIS 0x00000000 - -// Field: [0] TAEN -// -// GPT Timer A Enable -// ENUMs: -// EN Timer A is enabled and begins counting or the -// capture logic is enabled based on the CFG -// register. -// DIS Timer A is disabled. -#define GPT_CTL_TAEN 0x00000001 -#define GPT_CTL_TAEN_BITN 0 -#define GPT_CTL_TAEN_M 0x00000001 -#define GPT_CTL_TAEN_S 0 -#define GPT_CTL_TAEN_EN 0x00000001 -#define GPT_CTL_TAEN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: GPT_O_SYNC -// -//***************************************************************************** -// Field: [7:6] SYNC3 -// -// Synchronize GPT Timer 3. -// ENUMs: -// BOTH A timeout event for both Timer A and Timer B of -// GPT3 is triggered -// TIMERB A timeout event for Timer B of GPT3 is triggered -// TIMERA A timeout event for Timer A of GPT3 is triggered -// NOSYNC No Sync. GPT3 is not affected. -#define GPT_SYNC_SYNC3_W 2 -#define GPT_SYNC_SYNC3_M 0x000000C0 -#define GPT_SYNC_SYNC3_S 6 -#define GPT_SYNC_SYNC3_BOTH 0x000000C0 -#define GPT_SYNC_SYNC3_TIMERB 0x00000080 -#define GPT_SYNC_SYNC3_TIMERA 0x00000040 -#define GPT_SYNC_SYNC3_NOSYNC 0x00000000 - -// Field: [5:4] SYNC2 -// -// Synchronize GPT Timer 2. -// ENUMs: -// BOTH A timeout event for both Timer A and Timer B of -// GPT2 is triggered -// TIMERB A timeout event for Timer B of GPT2 is triggered -// TIMERA A timeout event for Timer A of GPT2 is triggered -// NOSYNC No Sync. GPT2 is not affected. -#define GPT_SYNC_SYNC2_W 2 -#define GPT_SYNC_SYNC2_M 0x00000030 -#define GPT_SYNC_SYNC2_S 4 -#define GPT_SYNC_SYNC2_BOTH 0x00000030 -#define GPT_SYNC_SYNC2_TIMERB 0x00000020 -#define GPT_SYNC_SYNC2_TIMERA 0x00000010 -#define GPT_SYNC_SYNC2_NOSYNC 0x00000000 - -// Field: [3:2] SYNC1 -// -// Synchronize GPT Timer 1 -// ENUMs: -// BOTH A timeout event for both Timer A and Timer B of -// GPT1 is triggered -// TIMERB A timeout event for Timer B of GPT1 is triggered -// TIMERA A timeout event for Timer A of GPT1 is triggered -// NOSYNC No Sync. GPT1 is not affected. -#define GPT_SYNC_SYNC1_W 2 -#define GPT_SYNC_SYNC1_M 0x0000000C -#define GPT_SYNC_SYNC1_S 2 -#define GPT_SYNC_SYNC1_BOTH 0x0000000C -#define GPT_SYNC_SYNC1_TIMERB 0x00000008 -#define GPT_SYNC_SYNC1_TIMERA 0x00000004 -#define GPT_SYNC_SYNC1_NOSYNC 0x00000000 - -// Field: [1:0] SYNC0 -// -// Synchronize GPT Timer 0 -// ENUMs: -// BOTH A timeout event for both Timer A and Timer B of -// GPT0 is triggered -// TIMERB A timeout event for Timer B of GPT0 is triggered -// TIMERA A timeout event for Timer A of GPT0 is triggered -// NOSYNC No Sync. GPT0 is not affected. -#define GPT_SYNC_SYNC0_W 2 -#define GPT_SYNC_SYNC0_M 0x00000003 -#define GPT_SYNC_SYNC0_S 0 -#define GPT_SYNC_SYNC0_BOTH 0x00000003 -#define GPT_SYNC_SYNC0_TIMERB 0x00000002 -#define GPT_SYNC_SYNC0_TIMERA 0x00000001 -#define GPT_SYNC_SYNC0_NOSYNC 0x00000000 - -//***************************************************************************** -// -// Register: GPT_O_IMR -// -//***************************************************************************** -// Field: [13] DMABIM -// -// Enabling this bit will make the RIS.DMABRIS interrupt propagate to -// MIS.DMABMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_DMABIM 0x00002000 -#define GPT_IMR_DMABIM_BITN 13 -#define GPT_IMR_DMABIM_M 0x00002000 -#define GPT_IMR_DMABIM_S 13 -#define GPT_IMR_DMABIM_EN 0x00002000 -#define GPT_IMR_DMABIM_DIS 0x00000000 - -// Field: [11] TBMIM -// -// Enabling this bit will make the RIS.TBMRIS interrupt propagate to MIS.TBMMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_TBMIM 0x00000800 -#define GPT_IMR_TBMIM_BITN 11 -#define GPT_IMR_TBMIM_M 0x00000800 -#define GPT_IMR_TBMIM_S 11 -#define GPT_IMR_TBMIM_EN 0x00000800 -#define GPT_IMR_TBMIM_DIS 0x00000000 - -// Field: [10] CBEIM -// -// Enabling this bit will make the RIS.CBERIS interrupt propagate to MIS.CBEMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_CBEIM 0x00000400 -#define GPT_IMR_CBEIM_BITN 10 -#define GPT_IMR_CBEIM_M 0x00000400 -#define GPT_IMR_CBEIM_S 10 -#define GPT_IMR_CBEIM_EN 0x00000400 -#define GPT_IMR_CBEIM_DIS 0x00000000 - -// Field: [9] CBMIM -// -// Enabling this bit will make the RIS.CBMRIS interrupt propagate to MIS.CBMMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_CBMIM 0x00000200 -#define GPT_IMR_CBMIM_BITN 9 -#define GPT_IMR_CBMIM_M 0x00000200 -#define GPT_IMR_CBMIM_S 9 -#define GPT_IMR_CBMIM_EN 0x00000200 -#define GPT_IMR_CBMIM_DIS 0x00000000 - -// Field: [8] TBTOIM -// -// Enabling this bit will make the RIS.TBTORIS interrupt propagate to -// MIS.TBTOMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_TBTOIM 0x00000100 -#define GPT_IMR_TBTOIM_BITN 8 -#define GPT_IMR_TBTOIM_M 0x00000100 -#define GPT_IMR_TBTOIM_S 8 -#define GPT_IMR_TBTOIM_EN 0x00000100 -#define GPT_IMR_TBTOIM_DIS 0x00000000 - -// Field: [5] DMAAIM -// -// Enabling this bit will make the RIS.DMAARIS interrupt propagate to -// MIS.DMAAMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_DMAAIM 0x00000020 -#define GPT_IMR_DMAAIM_BITN 5 -#define GPT_IMR_DMAAIM_M 0x00000020 -#define GPT_IMR_DMAAIM_S 5 -#define GPT_IMR_DMAAIM_EN 0x00000020 -#define GPT_IMR_DMAAIM_DIS 0x00000000 - -// Field: [4] TAMIM -// -// Enabling this bit will make the RIS.TAMRIS interrupt propagate to MIS.TAMMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_TAMIM 0x00000010 -#define GPT_IMR_TAMIM_BITN 4 -#define GPT_IMR_TAMIM_M 0x00000010 -#define GPT_IMR_TAMIM_S 4 -#define GPT_IMR_TAMIM_EN 0x00000010 -#define GPT_IMR_TAMIM_DIS 0x00000000 - -// Field: [2] CAEIM -// -// Enabling this bit will make the RIS.CAERIS interrupt propagate to MIS.CAEMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_CAEIM 0x00000004 -#define GPT_IMR_CAEIM_BITN 2 -#define GPT_IMR_CAEIM_M 0x00000004 -#define GPT_IMR_CAEIM_S 2 -#define GPT_IMR_CAEIM_EN 0x00000004 -#define GPT_IMR_CAEIM_DIS 0x00000000 - -// Field: [1] CAMIM -// -// Enabling this bit will make the RIS.CAMRIS interrupt propagate to MIS.CAMMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_CAMIM 0x00000002 -#define GPT_IMR_CAMIM_BITN 1 -#define GPT_IMR_CAMIM_M 0x00000002 -#define GPT_IMR_CAMIM_S 1 -#define GPT_IMR_CAMIM_EN 0x00000002 -#define GPT_IMR_CAMIM_DIS 0x00000000 - -// Field: [0] TATOIM -// -// Enabling this bit will make the RIS.TATORIS interrupt propagate to -// MIS.TATOMIS -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define GPT_IMR_TATOIM 0x00000001 -#define GPT_IMR_TATOIM_BITN 0 -#define GPT_IMR_TATOIM_M 0x00000001 -#define GPT_IMR_TATOIM_S 0 -#define GPT_IMR_TATOIM_EN 0x00000001 -#define GPT_IMR_TATOIM_DIS 0x00000000 - -//***************************************************************************** -// -// Register: GPT_O_RIS -// -//***************************************************************************** -// Field: [13] DMABRIS -// -// GPT Timer B DMA Done Raw Interrupt Status -// -// 0: Transfer has not completed -// 1: Transfer has completed -#define GPT_RIS_DMABRIS 0x00002000 -#define GPT_RIS_DMABRIS_BITN 13 -#define GPT_RIS_DMABRIS_M 0x00002000 -#define GPT_RIS_DMABRIS_S 13 - -// Field: [11] TBMRIS -// -// GPT Timer B Match Raw Interrupt -// -// 0: The match value has not been reached -// 1: The match value is reached. -// -// TBMR.TBMIE is set, and the match values in TBMATCHR and optionally TBPMR -// have been reached when configured in one-shot or periodic mode. -#define GPT_RIS_TBMRIS 0x00000800 -#define GPT_RIS_TBMRIS_BITN 11 -#define GPT_RIS_TBMRIS_M 0x00000800 -#define GPT_RIS_TBMRIS_S 11 - -// Field: [10] CBERIS -// -// GPT Timer B Capture Mode Event Raw Interrupt -// -// 0: The event has not occured. -// 1: The event has occured. -// -// This interrupt asserts when the subtimer is configured in Input Edge-Time -// mode -#define GPT_RIS_CBERIS 0x00000400 -#define GPT_RIS_CBERIS_BITN 10 -#define GPT_RIS_CBERIS_M 0x00000400 -#define GPT_RIS_CBERIS_S 10 - -// Field: [9] CBMRIS -// -// GPT Timer B Capture Mode Match Raw Interrupt -// -// 0: The capture mode match for Timer B has not occurred. -// 1: A capture mode match has occurred for Timer B. This interrupt -// asserts when the values in the TBR and TBPR -// match the values in the TBMATCHR and TBPMR -// when configured in Input Edge-Time mode. -// -// This bit is cleared by writing a 1 to the ICLR.CBMCINT bit. -#define GPT_RIS_CBMRIS 0x00000200 -#define GPT_RIS_CBMRIS_BITN 9 -#define GPT_RIS_CBMRIS_M 0x00000200 -#define GPT_RIS_CBMRIS_S 9 - -// Field: [8] TBTORIS -// -// GPT Timer B Time-out Raw Interrupt -// -// 0: Timer B has not timed out -// 1: Timer B has timed out. -// -// This interrupt is asserted when a one-shot or periodic mode timer reaches -// its count limit. The count limit is 0 or the value loaded into TBILR, -// depending on the count direction. -#define GPT_RIS_TBTORIS 0x00000100 -#define GPT_RIS_TBTORIS_BITN 8 -#define GPT_RIS_TBTORIS_M 0x00000100 -#define GPT_RIS_TBTORIS_S 8 - -// Field: [5] DMAARIS -// -// GPT Timer A DMA Done Raw Interrupt Status -// -// 0: Transfer has not completed -// 1: Transfer has completed -#define GPT_RIS_DMAARIS 0x00000020 -#define GPT_RIS_DMAARIS_BITN 5 -#define GPT_RIS_DMAARIS_M 0x00000020 -#define GPT_RIS_DMAARIS_S 5 - -// Field: [4] TAMRIS -// -// GPT Timer A Match Raw Interrupt -// -// 0: The match value has not been reached -// 1: The match value is reached. -// -// TAMR.TAMIE is set, and the match values in TAMATCHR and optionally TAPMR -// have been reached when configured in one-shot or periodic mode. -#define GPT_RIS_TAMRIS 0x00000010 -#define GPT_RIS_TAMRIS_BITN 4 -#define GPT_RIS_TAMRIS_M 0x00000010 -#define GPT_RIS_TAMRIS_S 4 - -// Field: [2] CAERIS -// -// GPT Timer A Capture Mode Event Raw Interrupt -// -// 0: The event has not occured. -// 1: The event has occured. -// -// This interrupt asserts when the subtimer is configured in Input Edge-Time -// mode -#define GPT_RIS_CAERIS 0x00000004 -#define GPT_RIS_CAERIS_BITN 2 -#define GPT_RIS_CAERIS_M 0x00000004 -#define GPT_RIS_CAERIS_S 2 - -// Field: [1] CAMRIS -// -// GPT Timer A Capture Mode Match Raw Interrupt -// -// 0: The capture mode match for Timer A has not occurred. -// 1: A capture mode match has occurred for Timer A. This interrupt -// asserts when the values in the TAR and TAPR -// match the values in the TAMATCHR and TAPMR -// when configured in Input Edge-Time mode. -// -// This bit is cleared by writing a 1 to the ICLR.CAMCINT bit. -#define GPT_RIS_CAMRIS 0x00000002 -#define GPT_RIS_CAMRIS_BITN 1 -#define GPT_RIS_CAMRIS_M 0x00000002 -#define GPT_RIS_CAMRIS_S 1 - -// Field: [0] TATORIS -// -// GPT Timer A Time-out Raw Interrupt -// -// 0: Timer A has not timed out -// 1: Timer A has timed out. -// -// This interrupt is asserted when a one-shot or periodic mode timer reaches -// its count limit. The count limit is 0 or the value loaded into TAILR, -// depending on the count direction. -#define GPT_RIS_TATORIS 0x00000001 -#define GPT_RIS_TATORIS_BITN 0 -#define GPT_RIS_TATORIS_M 0x00000001 -#define GPT_RIS_TATORIS_S 0 - -//***************************************************************************** -// -// Register: GPT_O_MIS -// -//***************************************************************************** -// Field: [13] DMABMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.DMABRIS = 1 && IMR.DMABIM = 1 -#define GPT_MIS_DMABMIS 0x00002000 -#define GPT_MIS_DMABMIS_BITN 13 -#define GPT_MIS_DMABMIS_M 0x00002000 -#define GPT_MIS_DMABMIS_S 13 - -// Field: [11] TBMMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.TBMRIS = 1 && IMR.TBMIM = 1 -#define GPT_MIS_TBMMIS 0x00000800 -#define GPT_MIS_TBMMIS_BITN 11 -#define GPT_MIS_TBMMIS_M 0x00000800 -#define GPT_MIS_TBMMIS_S 11 - -// Field: [10] CBEMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.CBERIS = 1 && IMR.CBEIM = 1 -#define GPT_MIS_CBEMIS 0x00000400 -#define GPT_MIS_CBEMIS_BITN 10 -#define GPT_MIS_CBEMIS_M 0x00000400 -#define GPT_MIS_CBEMIS_S 10 - -// Field: [9] CBMMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.CBMRIS = 1 && IMR.CBMIM = 1 -#define GPT_MIS_CBMMIS 0x00000200 -#define GPT_MIS_CBMMIS_BITN 9 -#define GPT_MIS_CBMMIS_M 0x00000200 -#define GPT_MIS_CBMMIS_S 9 - -// Field: [8] TBTOMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.TBTORIS = 1 && IMR.TBTOIM = 1 -#define GPT_MIS_TBTOMIS 0x00000100 -#define GPT_MIS_TBTOMIS_BITN 8 -#define GPT_MIS_TBTOMIS_M 0x00000100 -#define GPT_MIS_TBTOMIS_S 8 - -// Field: [5] DMAAMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.DMAARIS = 1 && IMR.DMAAIM = 1 -#define GPT_MIS_DMAAMIS 0x00000020 -#define GPT_MIS_DMAAMIS_BITN 5 -#define GPT_MIS_DMAAMIS_M 0x00000020 -#define GPT_MIS_DMAAMIS_S 5 - -// Field: [4] TAMMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.TAMRIS = 1 && IMR.TAMIM = 1 -#define GPT_MIS_TAMMIS 0x00000010 -#define GPT_MIS_TAMMIS_BITN 4 -#define GPT_MIS_TAMMIS_M 0x00000010 -#define GPT_MIS_TAMMIS_S 4 - -// Field: [2] CAEMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.CAERIS = 1 && IMR.CAEIM = 1 -#define GPT_MIS_CAEMIS 0x00000004 -#define GPT_MIS_CAEMIS_BITN 2 -#define GPT_MIS_CAEMIS_M 0x00000004 -#define GPT_MIS_CAEMIS_S 2 - -// Field: [1] CAMMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.CAMRIS = 1 && IMR.CAMIM = 1 -#define GPT_MIS_CAMMIS 0x00000002 -#define GPT_MIS_CAMMIS_BITN 1 -#define GPT_MIS_CAMMIS_M 0x00000002 -#define GPT_MIS_CAMMIS_S 1 - -// Field: [0] TATOMIS -// -// 0: No interrupt or interrupt not enabled -// 1: RIS.TATORIS = 1 && IMR.TATOIM = 1 -#define GPT_MIS_TATOMIS 0x00000001 -#define GPT_MIS_TATOMIS_BITN 0 -#define GPT_MIS_TATOMIS_M 0x00000001 -#define GPT_MIS_TATOMIS_S 0 - -//***************************************************************************** -// -// Register: GPT_O_ICLR -// -//***************************************************************************** -// Field: [13] DMABINT -// -// 0: Do nothing. -// 1: Clear RIS.DMABRIS and MIS.DMABMIS -#define GPT_ICLR_DMABINT 0x00002000 -#define GPT_ICLR_DMABINT_BITN 13 -#define GPT_ICLR_DMABINT_M 0x00002000 -#define GPT_ICLR_DMABINT_S 13 - -// Field: [11] TBMCINT -// -// 0: Do nothing. -// 1: Clear RIS.TBMRIS and MIS.TBMMIS -#define GPT_ICLR_TBMCINT 0x00000800 -#define GPT_ICLR_TBMCINT_BITN 11 -#define GPT_ICLR_TBMCINT_M 0x00000800 -#define GPT_ICLR_TBMCINT_S 11 - -// Field: [10] CBECINT -// -// 0: Do nothing. -// 1: Clear RIS.CBERIS and MIS.CBEMIS -#define GPT_ICLR_CBECINT 0x00000400 -#define GPT_ICLR_CBECINT_BITN 10 -#define GPT_ICLR_CBECINT_M 0x00000400 -#define GPT_ICLR_CBECINT_S 10 - -// Field: [9] CBMCINT -// -// 0: Do nothing. -// 1: Clear RIS.CBMRIS and MIS.CBMMIS -#define GPT_ICLR_CBMCINT 0x00000200 -#define GPT_ICLR_CBMCINT_BITN 9 -#define GPT_ICLR_CBMCINT_M 0x00000200 -#define GPT_ICLR_CBMCINT_S 9 - -// Field: [8] TBTOCINT -// -// 0: Do nothing. -// 1: Clear RIS.TBTORIS and MIS.TBTOMIS -#define GPT_ICLR_TBTOCINT 0x00000100 -#define GPT_ICLR_TBTOCINT_BITN 8 -#define GPT_ICLR_TBTOCINT_M 0x00000100 -#define GPT_ICLR_TBTOCINT_S 8 - -// Field: [5] DMAAINT -// -// 0: Do nothing. -// 1: Clear RIS.DMAARIS and MIS.DMAAMIS -#define GPT_ICLR_DMAAINT 0x00000020 -#define GPT_ICLR_DMAAINT_BITN 5 -#define GPT_ICLR_DMAAINT_M 0x00000020 -#define GPT_ICLR_DMAAINT_S 5 - -// Field: [4] TAMCINT -// -// 0: Do nothing. -// 1: Clear RIS.TAMRIS and MIS.TAMMIS -#define GPT_ICLR_TAMCINT 0x00000010 -#define GPT_ICLR_TAMCINT_BITN 4 -#define GPT_ICLR_TAMCINT_M 0x00000010 -#define GPT_ICLR_TAMCINT_S 4 - -// Field: [2] CAECINT -// -// 0: Do nothing. -// 1: Clear RIS.CAERIS and MIS.CAEMIS -#define GPT_ICLR_CAECINT 0x00000004 -#define GPT_ICLR_CAECINT_BITN 2 -#define GPT_ICLR_CAECINT_M 0x00000004 -#define GPT_ICLR_CAECINT_S 2 - -// Field: [1] CAMCINT -// -// 0: Do nothing. -// 1: Clear RIS.CAMRIS and MIS.CAMMIS -#define GPT_ICLR_CAMCINT 0x00000002 -#define GPT_ICLR_CAMCINT_BITN 1 -#define GPT_ICLR_CAMCINT_M 0x00000002 -#define GPT_ICLR_CAMCINT_S 1 - -// Field: [0] TATOCINT -// -// 0: Do nothing. -// 1: Clear RIS.TATORIS and MIS.TATOMIS -#define GPT_ICLR_TATOCINT 0x00000001 -#define GPT_ICLR_TATOCINT_BITN 0 -#define GPT_ICLR_TATOCINT_M 0x00000001 -#define GPT_ICLR_TATOCINT_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAILR -// -//***************************************************************************** -// Field: [31:0] TAILR -// -// GPT Timer A Interval Load Register -// -// Writing this field loads the counter for Timer A. A read returns the current -// value of TAILR. -#define GPT_TAILR_TAILR_W 32 -#define GPT_TAILR_TAILR_M 0xFFFFFFFF -#define GPT_TAILR_TAILR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBILR -// -//***************************************************************************** -// Field: [31:0] TBILR -// -// GPT Timer B Interval Load Register -// -// Writing this field loads the counter for Timer B. A read returns the current -// value of TBILR. -#define GPT_TBILR_TBILR_W 32 -#define GPT_TBILR_TBILR_M 0xFFFFFFFF -#define GPT_TBILR_TBILR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAMATCHR -// -//***************************************************************************** -// Field: [31:0] TAMATCHR -// -// GPT Timer A Match Register -#define GPT_TAMATCHR_TAMATCHR_W 32 -#define GPT_TAMATCHR_TAMATCHR_M 0xFFFFFFFF -#define GPT_TAMATCHR_TAMATCHR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBMATCHR -// -//***************************************************************************** -// Field: [15:0] TBMATCHR -// -// GPT Timer B Match Register -#define GPT_TBMATCHR_TBMATCHR_W 16 -#define GPT_TBMATCHR_TBMATCHR_M 0x0000FFFF -#define GPT_TBMATCHR_TBMATCHR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAPR -// -//***************************************************************************** -// Field: [7:0] TAPSR -// -// Timer A Pre-scale. -// -// Prescaler ratio in one-shot and periodic count mode is TAPSR + 1, that is: -// -// 0: Prescaler ratio = 1 -// 1: Prescaler ratio = 2 -// 2: Prescaler ratio = 3 -// ... -// 255: Prescaler ratio = 256 -#define GPT_TAPR_TAPSR_W 8 -#define GPT_TAPR_TAPSR_M 0x000000FF -#define GPT_TAPR_TAPSR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBPR -// -//***************************************************************************** -// Field: [7:0] TBPSR -// -// Timer B Pre-scale. -// -// Prescale ratio in one-shot and periodic count mode is TBPSR + 1, that is: -// -// 0: Prescaler ratio = 1 -// 1: Prescaler ratio = 2 -// 2: Prescaler ratio = 3 -// ... -// 255: Prescaler ratio = 256 -#define GPT_TBPR_TBPSR_W 8 -#define GPT_TBPR_TBPSR_M 0x000000FF -#define GPT_TBPR_TBPSR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAPMR -// -//***************************************************************************** -// Field: [7:0] TAPSMR -// -// GPT Timer A Pre-scale Match. In 16 bit mode this field holds bits 23 to 16. -#define GPT_TAPMR_TAPSMR_W 8 -#define GPT_TAPMR_TAPSMR_M 0x000000FF -#define GPT_TAPMR_TAPSMR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBPMR -// -//***************************************************************************** -// Field: [7:0] TBPSMR -// -// GPT Timer B Pre-scale Match Register. In 16 bit mode this field holds bits -// 23 to 16. -#define GPT_TBPMR_TBPSMR_W 8 -#define GPT_TBPMR_TBPSMR_M 0x000000FF -#define GPT_TBPMR_TBPSMR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAR -// -//***************************************************************************** -// Field: [31:0] TAR -// -// GPT Timer A Register -// -// Based on the value in the register field TAMR.TAILD, this register is -// updated with the value from TAILR register either on the next cycle or on -// the next timeout. -// -// A read returns the current value of the Timer A Count Register, in all cases -// except for Input Edge count and Timer modes. -// In the Input Edge Count Mode, this register contains the number of edges -// that have occurred. In the Input Edge Time mode, this register contains the -// time at which the last edge event took place. -#define GPT_TAR_TAR_W 32 -#define GPT_TAR_TAR_M 0xFFFFFFFF -#define GPT_TAR_TAR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBR -// -//***************************************************************************** -// Field: [31:0] TBR -// -// GPT Timer B Register -// -// Based on the value in the register field TBMR.TBILD, this register is -// updated with the value from TBILR register either on the next cycle or on -// the next timeout. -// -// A read returns the current value of the Timer B Count Register, in all cases -// except for Input Edge count and Timer modes. -// In the Input Edge Count Mode, this register contains the number of edges -// that have occurred. In the Input Edge Time mode, this register contains the -// time at which the last edge event took place. -#define GPT_TBR_TBR_W 32 -#define GPT_TBR_TBR_M 0xFFFFFFFF -#define GPT_TBR_TBR_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAV -// -//***************************************************************************** -// Field: [31:0] TAV -// -// GPT Timer A Register -// A read returns the current, free-running value of Timer A in all modes. -// When written, the value written into this register is loaded into the -// TAR register on the next clock cycle. -// Note: In 16-bit mode, only the lower 16-bits of this -// register can be written with a new value. Writes to the prescaler bits have -// no effect -#define GPT_TAV_TAV_W 32 -#define GPT_TAV_TAV_M 0xFFFFFFFF -#define GPT_TAV_TAV_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBV -// -//***************************************************************************** -// Field: [31:0] TBV -// -// GPT Timer B Register -// A read returns the current, free-running value of Timer B in all modes. -// When written, the value written into this register is loaded into the -// TBR register on the next clock cycle. -// Note: In 16-bit mode, only the lower 16-bits of this -// register can be written with a new value. Writes to the prescaler bits have -// no effect -#define GPT_TBV_TBV_W 32 -#define GPT_TBV_TBV_M 0xFFFFFFFF -#define GPT_TBV_TBV_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAPS -// -//***************************************************************************** -// Field: [7:0] PSS -// -// GPT Timer A Pre-scaler -#define GPT_TAPS_PSS_W 8 -#define GPT_TAPS_PSS_M 0x000000FF -#define GPT_TAPS_PSS_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBPS -// -//***************************************************************************** -// Field: [7:0] PSS -// -// GPT Timer B Pre-scaler -#define GPT_TBPS_PSS_W 8 -#define GPT_TBPS_PSS_M 0x000000FF -#define GPT_TBPS_PSS_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TAPV -// -//***************************************************************************** -// Field: [7:0] PSV -// -// GPT Timer A Pre-scaler Value -#define GPT_TAPV_PSV_W 8 -#define GPT_TAPV_PSV_M 0x000000FF -#define GPT_TAPV_PSV_S 0 - -//***************************************************************************** -// -// Register: GPT_O_TBPV -// -//***************************************************************************** -// Field: [7:0] PSV -// -// GPT Timer B Pre-scaler Value -#define GPT_TBPV_PSV_W 8 -#define GPT_TBPV_PSV_M 0x000000FF -#define GPT_TBPV_PSV_S 0 - -//***************************************************************************** -// -// Register: GPT_O_DMAEV -// -//***************************************************************************** -// Field: [11] TBMDMAEN -// -// GPT Timer B Match DMA Trigger Enable -#define GPT_DMAEV_TBMDMAEN 0x00000800 -#define GPT_DMAEV_TBMDMAEN_BITN 11 -#define GPT_DMAEV_TBMDMAEN_M 0x00000800 -#define GPT_DMAEV_TBMDMAEN_S 11 - -// Field: [10] CBEDMAEN -// -// GPT Timer B Capture Event DMA Trigger Enable -#define GPT_DMAEV_CBEDMAEN 0x00000400 -#define GPT_DMAEV_CBEDMAEN_BITN 10 -#define GPT_DMAEV_CBEDMAEN_M 0x00000400 -#define GPT_DMAEV_CBEDMAEN_S 10 - -// Field: [9] CBMDMAEN -// -// GPT Timer B Capture Match DMA Trigger Enable -#define GPT_DMAEV_CBMDMAEN 0x00000200 -#define GPT_DMAEV_CBMDMAEN_BITN 9 -#define GPT_DMAEV_CBMDMAEN_M 0x00000200 -#define GPT_DMAEV_CBMDMAEN_S 9 - -// Field: [8] TBTODMAEN -// -// GPT Timer B Time-Out DMA Trigger Enable -#define GPT_DMAEV_TBTODMAEN 0x00000100 -#define GPT_DMAEV_TBTODMAEN_BITN 8 -#define GPT_DMAEV_TBTODMAEN_M 0x00000100 -#define GPT_DMAEV_TBTODMAEN_S 8 - -// Field: [4] TAMDMAEN -// -// GPT Timer A Match DMA Trigger Enable -#define GPT_DMAEV_TAMDMAEN 0x00000010 -#define GPT_DMAEV_TAMDMAEN_BITN 4 -#define GPT_DMAEV_TAMDMAEN_M 0x00000010 -#define GPT_DMAEV_TAMDMAEN_S 4 - -// Field: [2] CAEDMAEN -// -// GPT Timer A Capture Event DMA Trigger Enable -#define GPT_DMAEV_CAEDMAEN 0x00000004 -#define GPT_DMAEV_CAEDMAEN_BITN 2 -#define GPT_DMAEV_CAEDMAEN_M 0x00000004 -#define GPT_DMAEV_CAEDMAEN_S 2 - -// Field: [1] CAMDMAEN -// -// GPT Timer A Capture Match DMA Trigger Enable -#define GPT_DMAEV_CAMDMAEN 0x00000002 -#define GPT_DMAEV_CAMDMAEN_BITN 1 -#define GPT_DMAEV_CAMDMAEN_M 0x00000002 -#define GPT_DMAEV_CAMDMAEN_S 1 - -// Field: [0] TATODMAEN -// -// GPT Timer A Time-Out DMA Trigger Enable -#define GPT_DMAEV_TATODMAEN 0x00000001 -#define GPT_DMAEV_TATODMAEN_BITN 0 -#define GPT_DMAEV_TATODMAEN_M 0x00000001 -#define GPT_DMAEV_TATODMAEN_S 0 - -//***************************************************************************** -// -// Register: GPT_O_VERSION -// -//***************************************************************************** -// Field: [31:0] VERSION -// -// Timer Revision. -#define GPT_VERSION_VERSION_W 32 -#define GPT_VERSION_VERSION_M 0xFFFFFFFF -#define GPT_VERSION_VERSION_S 0 - -//***************************************************************************** -// -// Register: GPT_O_ANDCCP -// -//***************************************************************************** -// Field: [1] LD_TO_EN -// -// PWM assertion would happen at timeout -// -// 0: PWM assertion happens when counter matches load value -// 1: PWM assertion happens at timeout of the counter -#define GPT_ANDCCP_LD_TO_EN 0x00000002 -#define GPT_ANDCCP_LD_TO_EN_BITN 1 -#define GPT_ANDCCP_LD_TO_EN_M 0x00000002 -#define GPT_ANDCCP_LD_TO_EN_S 1 - -// Field: [0] CCP_AND_EN -// -// Enables AND operation of the CCP outputs for timers A and B. -// -// 0 : PWM outputs of Timer A and Timer B are the internal generated PWM -// signals of the respective timers. -// 1 : PWM output of Timer A is ANDed version of Timer A and Timer B PWM -// signals and Timer B PWM ouput is Timer B PWM signal only. -#define GPT_ANDCCP_CCP_AND_EN 0x00000001 -#define GPT_ANDCCP_CCP_AND_EN_BITN 0 -#define GPT_ANDCCP_CCP_AND_EN_M 0x00000001 -#define GPT_ANDCCP_CCP_AND_EN_S 0 - - -#endif // __GPT__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h deleted file mode 100644 index 7408570c553..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_i2c.h +++ /dev/null @@ -1,728 +0,0 @@ -/****************************************************************************** -* Filename: hw_i2c_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// I2C component -// -//***************************************************************************** -// Slave Own Address -#define I2C_O_SOAR 0x00000000 - -// Slave Status -#define I2C_O_SSTAT 0x00000004 - -// Slave Control -#define I2C_O_SCTL 0x00000004 - -// Slave Data -#define I2C_O_SDR 0x00000008 - -// Slave Interrupt Mask -#define I2C_O_SIMR 0x0000000C - -// Slave Raw Interrupt Status -#define I2C_O_SRIS 0x00000010 - -// Slave Masked Interrupt Status -#define I2C_O_SMIS 0x00000014 - -// Slave Interrupt Clear -#define I2C_O_SICR 0x00000018 - -// Master Salve Address -#define I2C_O_MSA 0x00000800 - -// Master Status -#define I2C_O_MSTAT 0x00000804 - -// Master Control -#define I2C_O_MCTRL 0x00000804 - -// Master Data -#define I2C_O_MDR 0x00000808 - -// I2C Master Timer Period -#define I2C_O_MTPR 0x0000080C - -// Master Interrupt Mask -#define I2C_O_MIMR 0x00000810 - -// Master Raw Interrupt Status -#define I2C_O_MRIS 0x00000814 - -// Master Masked Interrupt Status -#define I2C_O_MMIS 0x00000818 - -// Master Interrupt Clear -#define I2C_O_MICR 0x0000081C - -// Master Configuration -#define I2C_O_MCR 0x00000820 - -//***************************************************************************** -// -// Register: I2C_O_SOAR -// -//***************************************************************************** -// Field: [6:0] OAR -// -// I2C slave own address -// This field specifies bits a6 through a0 of the slave address. -#define I2C_SOAR_OAR_W 7 -#define I2C_SOAR_OAR_M 0x0000007F -#define I2C_SOAR_OAR_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SSTAT -// -//***************************************************************************** -// Field: [2] FBR -// -// First byte received -// -// 0: The first byte has not been received. -// 1: The first byte following the slave's own address has been received. -// -// This bit is only valid when the RREQ bit is set and is automatically cleared -// when data has been read from the SDR register. -// Note: This bit is not used for slave transmit operations. -#define I2C_SSTAT_FBR 0x00000004 -#define I2C_SSTAT_FBR_BITN 2 -#define I2C_SSTAT_FBR_M 0x00000004 -#define I2C_SSTAT_FBR_S 2 - -// Field: [1] TREQ -// -// Transmit request -// -// 0: No outstanding transmit request. -// 1: The I2C controller has been addressed as a slave transmitter and is using -// clock stretching to delay the master until data has been written to the SDR -// register. -#define I2C_SSTAT_TREQ 0x00000002 -#define I2C_SSTAT_TREQ_BITN 1 -#define I2C_SSTAT_TREQ_M 0x00000002 -#define I2C_SSTAT_TREQ_S 1 - -// Field: [0] RREQ -// -// Receive request -// -// 0: No outstanding receive data -// 1: The I2C controller has outstanding receive data from the I2C master and -// is using clock stretching to delay the master until data has been read from -// the SDR register. -#define I2C_SSTAT_RREQ 0x00000001 -#define I2C_SSTAT_RREQ_BITN 0 -#define I2C_SSTAT_RREQ_M 0x00000001 -#define I2C_SSTAT_RREQ_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SCTL -// -//***************************************************************************** -// Field: [0] DA -// -// Device active -// -// 0: Disables the I2C slave operation -// 1: Enables the I2C slave operation -#define I2C_SCTL_DA 0x00000001 -#define I2C_SCTL_DA_BITN 0 -#define I2C_SCTL_DA_M 0x00000001 -#define I2C_SCTL_DA_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SDR -// -//***************************************************************************** -// Field: [7:0] DATA -// -// Data for transfer -// This field contains the data for transfer during a slave receive or transmit -// operation. When written the register data is used as transmit data. When -// read, this register returns the last data received. -// Data is stored until next update, either by a system write for transmit or -// by an external master for receive. -#define I2C_SDR_DATA_W 8 -#define I2C_SDR_DATA_M 0x000000FF -#define I2C_SDR_DATA_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SIMR -// -//***************************************************************************** -// Field: [2] STOPIM -// -// Stop condition interrupt mask -// -// 0: The SRIS.STOPRIS interrupt is suppressed and not sent to the interrupt -// controller. -// 1: The SRIS.STOPRIS interrupt is enabled and sent to the interrupt -// controller. -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define I2C_SIMR_STOPIM 0x00000004 -#define I2C_SIMR_STOPIM_BITN 2 -#define I2C_SIMR_STOPIM_M 0x00000004 -#define I2C_SIMR_STOPIM_S 2 -#define I2C_SIMR_STOPIM_EN 0x00000004 -#define I2C_SIMR_STOPIM_DIS 0x00000000 - -// Field: [1] STARTIM -// -// Start condition interrupt mask -// -// 0: The SRIS.STARTRIS interrupt is suppressed and not sent to the interrupt -// controller. -// 1: The SRIS.STARTRIS interrupt is enabled and sent to the interrupt -// controller. -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define I2C_SIMR_STARTIM 0x00000002 -#define I2C_SIMR_STARTIM_BITN 1 -#define I2C_SIMR_STARTIM_M 0x00000002 -#define I2C_SIMR_STARTIM_S 1 -#define I2C_SIMR_STARTIM_EN 0x00000002 -#define I2C_SIMR_STARTIM_DIS 0x00000000 - -// Field: [0] DATAIM -// -// Data interrupt mask -// -// 0: The SRIS.DATARIS interrupt is suppressed and not sent to the interrupt -// controller. -// 1: The SRIS.DATARIS interrupt is enabled and sent to the interrupt -// controller. -#define I2C_SIMR_DATAIM 0x00000001 -#define I2C_SIMR_DATAIM_BITN 0 -#define I2C_SIMR_DATAIM_M 0x00000001 -#define I2C_SIMR_DATAIM_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SRIS -// -//***************************************************************************** -// Field: [2] STOPRIS -// -// Stop condition raw interrupt status -// -// 0: No interrupt -// 1: A Stop condition interrupt is pending. -// -// This bit is cleared by writing a 1 to SICR.STOPIC. -#define I2C_SRIS_STOPRIS 0x00000004 -#define I2C_SRIS_STOPRIS_BITN 2 -#define I2C_SRIS_STOPRIS_M 0x00000004 -#define I2C_SRIS_STOPRIS_S 2 - -// Field: [1] STARTRIS -// -// Start condition raw interrupt status -// -// 0: No interrupt -// 1: A Start condition interrupt is pending. -// -// This bit is cleared by writing a 1 to SICR.STARTIC. -#define I2C_SRIS_STARTRIS 0x00000002 -#define I2C_SRIS_STARTRIS_BITN 1 -#define I2C_SRIS_STARTRIS_M 0x00000002 -#define I2C_SRIS_STARTRIS_S 1 - -// Field: [0] DATARIS -// -// Data raw interrupt status -// -// 0: No interrupt -// 1: A data received or data requested interrupt is pending. -// -// This bit is cleared by writing a 1 to the SICR.DATAIC. -#define I2C_SRIS_DATARIS 0x00000001 -#define I2C_SRIS_DATARIS_BITN 0 -#define I2C_SRIS_DATARIS_M 0x00000001 -#define I2C_SRIS_DATARIS_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SMIS -// -//***************************************************************************** -// Field: [2] STOPMIS -// -// Stop condition masked interrupt status -// -// 0: An interrupt has not occurred or is masked/disabled. -// 1: An unmasked Stop condition interrupt is pending. -// -// This bit is cleared by writing a 1 to the SICR.STOPIC. -#define I2C_SMIS_STOPMIS 0x00000004 -#define I2C_SMIS_STOPMIS_BITN 2 -#define I2C_SMIS_STOPMIS_M 0x00000004 -#define I2C_SMIS_STOPMIS_S 2 - -// Field: [1] STARTMIS -// -// Start condition masked interrupt status -// -// 0: An interrupt has not occurred or is masked/disabled. -// 1: An unmasked Start condition interrupt is pending. -// -// This bit is cleared by writing a 1 to the SICR.STARTIC. -#define I2C_SMIS_STARTMIS 0x00000002 -#define I2C_SMIS_STARTMIS_BITN 1 -#define I2C_SMIS_STARTMIS_M 0x00000002 -#define I2C_SMIS_STARTMIS_S 1 - -// Field: [0] DATAMIS -// -// Data masked interrupt status -// -// 0: An interrupt has not occurred or is masked/disabled. -// 1: An unmasked data received or data requested interrupt is pending. -// -// This bit is cleared by writing a 1 to the SICR.DATAIC. -#define I2C_SMIS_DATAMIS 0x00000001 -#define I2C_SMIS_DATAMIS_BITN 0 -#define I2C_SMIS_DATAMIS_M 0x00000001 -#define I2C_SMIS_DATAMIS_S 0 - -//***************************************************************************** -// -// Register: I2C_O_SICR -// -//***************************************************************************** -// Field: [2] STOPIC -// -// Stop condition interrupt clear -// -// Writing 1 to this bit clears SRIS.STOPRIS and SMIS.STOPMIS. -#define I2C_SICR_STOPIC 0x00000004 -#define I2C_SICR_STOPIC_BITN 2 -#define I2C_SICR_STOPIC_M 0x00000004 -#define I2C_SICR_STOPIC_S 2 - -// Field: [1] STARTIC -// -// Start condition interrupt clear -// -// Writing 1 to this bit clears SRIS.STARTRIS SMIS.STARTMIS. -#define I2C_SICR_STARTIC 0x00000002 -#define I2C_SICR_STARTIC_BITN 1 -#define I2C_SICR_STARTIC_M 0x00000002 -#define I2C_SICR_STARTIC_S 1 - -// Field: [0] DATAIC -// -// Data interrupt clear -// -// Writing 1 to this bit clears SRIS.DATARIS SMIS.DATAMIS. -#define I2C_SICR_DATAIC 0x00000001 -#define I2C_SICR_DATAIC_BITN 0 -#define I2C_SICR_DATAIC_M 0x00000001 -#define I2C_SICR_DATAIC_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MSA -// -//***************************************************************************** -// Field: [7:1] SA -// -// I2C master slave address -// Defines which slave is addressed for the transaction in master mode -#define I2C_MSA_SA_W 7 -#define I2C_MSA_SA_M 0x000000FE -#define I2C_MSA_SA_S 1 - -// Field: [0] RS -// -// Receive or Send -// This bit-field specifies if the next operation is a receive (high) or a -// transmit/send (low) from the addressed slave SA. -// ENUMs: -// RX Receive data from slave -// TX Transmit/send data to slave -#define I2C_MSA_RS 0x00000001 -#define I2C_MSA_RS_BITN 0 -#define I2C_MSA_RS_M 0x00000001 -#define I2C_MSA_RS_S 0 -#define I2C_MSA_RS_RX 0x00000001 -#define I2C_MSA_RS_TX 0x00000000 - -//***************************************************************************** -// -// Register: I2C_O_MSTAT -// -//***************************************************************************** -// Field: [6] BUSBSY -// -// Bus busy -// -// 0: The I2C bus is idle. -// 1: The I2C bus is busy. -// -// The bit changes based on the MCTRL.START and MCTRL.STOP conditions. -#define I2C_MSTAT_BUSBSY 0x00000040 -#define I2C_MSTAT_BUSBSY_BITN 6 -#define I2C_MSTAT_BUSBSY_M 0x00000040 -#define I2C_MSTAT_BUSBSY_S 6 - -// Field: [5] IDLE -// -// I2C idle -// -// 0: The I2C controller is not idle. -// 1: The I2C controller is idle. -#define I2C_MSTAT_IDLE 0x00000020 -#define I2C_MSTAT_IDLE_BITN 5 -#define I2C_MSTAT_IDLE_M 0x00000020 -#define I2C_MSTAT_IDLE_S 5 - -// Field: [4] ARBLST -// -// Arbitration lost -// -// 0: The I2C controller won arbitration. -// 1: The I2C controller lost arbitration. -#define I2C_MSTAT_ARBLST 0x00000010 -#define I2C_MSTAT_ARBLST_BITN 4 -#define I2C_MSTAT_ARBLST_M 0x00000010 -#define I2C_MSTAT_ARBLST_S 4 - -// Field: [3] DATACK_N -// -// Data Was Not Acknowledge -// -// 0: The transmitted data was acknowledged. -// 1: The transmitted data was not acknowledged. -#define I2C_MSTAT_DATACK_N 0x00000008 -#define I2C_MSTAT_DATACK_N_BITN 3 -#define I2C_MSTAT_DATACK_N_M 0x00000008 -#define I2C_MSTAT_DATACK_N_S 3 - -// Field: [2] ADRACK_N -// -// Address Was Not Acknowledge -// -// 0: The transmitted address was acknowledged. -// 1: The transmitted address was not acknowledged. -#define I2C_MSTAT_ADRACK_N 0x00000004 -#define I2C_MSTAT_ADRACK_N_BITN 2 -#define I2C_MSTAT_ADRACK_N_M 0x00000004 -#define I2C_MSTAT_ADRACK_N_S 2 - -// Field: [1] ERR -// -// Error -// -// 0: No error was detected on the last operation. -// 1: An error occurred on the last operation. -#define I2C_MSTAT_ERR 0x00000002 -#define I2C_MSTAT_ERR_BITN 1 -#define I2C_MSTAT_ERR_M 0x00000002 -#define I2C_MSTAT_ERR_S 1 - -// Field: [0] BUSY -// -// I2C busy -// -// 0: The controller is idle. -// 1: The controller is busy. -// -// When this bit-field is set, the other status bits are not valid. -// -// Note: The I2C controller requires four SYSBUS clock cycles to assert the -// BUSY status after I2C master operation has been initiated through MCTRL -// register. -// Hence after programming MCTRL register, application is requested to wait for -// four SYSBUS clock cycles before issuing a controller status inquiry through -// MSTAT register. -// Any prior inquiry would result in wrong status being reported. -#define I2C_MSTAT_BUSY 0x00000001 -#define I2C_MSTAT_BUSY_BITN 0 -#define I2C_MSTAT_BUSY_M 0x00000001 -#define I2C_MSTAT_BUSY_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MCTRL -// -//***************************************************************************** -// Field: [3] ACK -// -// Data acknowledge enable -// -// 0: The received data byte is not acknowledged automatically by the master. -// 1: The received data byte is acknowledged automatically by the master. -// -// This bit-field must be cleared when the I2C bus controller requires no -// further data to be transmitted from the slave transmitter. -// ENUMs: -// EN Enable acknowledge -// DIS Disable acknowledge -#define I2C_MCTRL_ACK 0x00000008 -#define I2C_MCTRL_ACK_BITN 3 -#define I2C_MCTRL_ACK_M 0x00000008 -#define I2C_MCTRL_ACK_S 3 -#define I2C_MCTRL_ACK_EN 0x00000008 -#define I2C_MCTRL_ACK_DIS 0x00000000 - -// Field: [2] STOP -// -// This bit-field determines if the cycle stops at the end of the data cycle or -// continues on to a repeated START condition. -// -// 0: The controller does not generate the Stop condition. -// 1: The controller generates the Stop condition. -// ENUMs: -// EN Enable STOP -// DIS Disable STOP -#define I2C_MCTRL_STOP 0x00000004 -#define I2C_MCTRL_STOP_BITN 2 -#define I2C_MCTRL_STOP_M 0x00000004 -#define I2C_MCTRL_STOP_S 2 -#define I2C_MCTRL_STOP_EN 0x00000004 -#define I2C_MCTRL_STOP_DIS 0x00000000 - -// Field: [1] START -// -// This bit-field generates the Start or Repeated Start condition. -// -// 0: The controller does not generate the Start condition. -// 1: The controller generates the Start condition. -// ENUMs: -// EN Enable START -// DIS Disable START -#define I2C_MCTRL_START 0x00000002 -#define I2C_MCTRL_START_BITN 1 -#define I2C_MCTRL_START_M 0x00000002 -#define I2C_MCTRL_START_S 1 -#define I2C_MCTRL_START_EN 0x00000002 -#define I2C_MCTRL_START_DIS 0x00000000 - -// Field: [0] RUN -// -// I2C master enable -// -// 0: The master is disabled. -// 1: The master is enabled to transmit or receive data. -// ENUMs: -// EN Enable Master -// DIS Disable Master -#define I2C_MCTRL_RUN 0x00000001 -#define I2C_MCTRL_RUN_BITN 0 -#define I2C_MCTRL_RUN_M 0x00000001 -#define I2C_MCTRL_RUN_S 0 -#define I2C_MCTRL_RUN_EN 0x00000001 -#define I2C_MCTRL_RUN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: I2C_O_MDR -// -//***************************************************************************** -// Field: [7:0] DATA -// -// When Read: Last RX Data is returned -// When Written: Data is transferred during TX transaction -#define I2C_MDR_DATA_W 8 -#define I2C_MDR_DATA_M 0x000000FF -#define I2C_MDR_DATA_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MTPR -// -//***************************************************************************** -// Field: [7] TPR_7 -// -// Must be set to 0 to set TPR. If set to 1, a write to TPR will be ignored. -#define I2C_MTPR_TPR_7 0x00000080 -#define I2C_MTPR_TPR_7_BITN 7 -#define I2C_MTPR_TPR_7_M 0x00000080 -#define I2C_MTPR_TPR_7_S 7 - -// Field: [6:0] TPR -// -// SCL clock period -// This field specifies the period of the SCL clock. -// SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD -// where: -// SCL_PRD is the SCL line period (I2C clock). -// TPR is the timer period register value (range of 1 to 127) -// SCL_LP is the SCL low period (fixed at 6). -// SCL_HP is the SCL high period (fixed at 4). -// CLK_PRD is the system clock period in ns. -#define I2C_MTPR_TPR_W 7 -#define I2C_MTPR_TPR_M 0x0000007F -#define I2C_MTPR_TPR_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MIMR -// -//***************************************************************************** -// Field: [0] IM -// -// Interrupt mask -// -// 0: The MRIS.RIS interrupt is suppressed and not sent to the interrupt -// controller. -// 1: The master interrupt is sent to the interrupt controller when the -// MRIS.RIS is set. -// ENUMs: -// EN Enable Interrupt -// DIS Disable Interrupt -#define I2C_MIMR_IM 0x00000001 -#define I2C_MIMR_IM_BITN 0 -#define I2C_MIMR_IM_M 0x00000001 -#define I2C_MIMR_IM_S 0 -#define I2C_MIMR_IM_EN 0x00000001 -#define I2C_MIMR_IM_DIS 0x00000000 - -//***************************************************************************** -// -// Register: I2C_O_MRIS -// -//***************************************************************************** -// Field: [0] RIS -// -// Raw interrupt status -// -// 0: No interrupt -// 1: A master interrupt is pending. -// -// This bit is cleared by writing 1 to the MICR.IC bit . -#define I2C_MRIS_RIS 0x00000001 -#define I2C_MRIS_RIS_BITN 0 -#define I2C_MRIS_RIS_M 0x00000001 -#define I2C_MRIS_RIS_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MMIS -// -//***************************************************************************** -// Field: [0] MIS -// -// Masked interrupt status -// -// 0: An interrupt has not occurred or is masked. -// 1: A master interrupt is pending. -// -// This bit is cleared by writing 1 to the MICR.IC bit . -#define I2C_MMIS_MIS 0x00000001 -#define I2C_MMIS_MIS_BITN 0 -#define I2C_MMIS_MIS_M 0x00000001 -#define I2C_MMIS_MIS_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MICR -// -//***************************************************************************** -// Field: [0] IC -// -// Interrupt clear -// Writing 1 to this bit clears MRIS.RIS and MMIS.MIS . -// -// Reading this register returns no meaningful data. -#define I2C_MICR_IC 0x00000001 -#define I2C_MICR_IC_BITN 0 -#define I2C_MICR_IC_M 0x00000001 -#define I2C_MICR_IC_S 0 - -//***************************************************************************** -// -// Register: I2C_O_MCR -// -//***************************************************************************** -// Field: [5] SFE -// -// I2C slave function enable -// ENUMs: -// EN Slave mode is enabled. -// DIS Slave mode is disabled. -#define I2C_MCR_SFE 0x00000020 -#define I2C_MCR_SFE_BITN 5 -#define I2C_MCR_SFE_M 0x00000020 -#define I2C_MCR_SFE_S 5 -#define I2C_MCR_SFE_EN 0x00000020 -#define I2C_MCR_SFE_DIS 0x00000000 - -// Field: [4] MFE -// -// I2C master function enable -// ENUMs: -// EN Master mode is enabled. -// DIS Master mode is disabled. -#define I2C_MCR_MFE 0x00000010 -#define I2C_MCR_MFE_BITN 4 -#define I2C_MCR_MFE_M 0x00000010 -#define I2C_MCR_MFE_S 4 -#define I2C_MCR_MFE_EN 0x00000010 -#define I2C_MCR_MFE_DIS 0x00000000 - -// Field: [0] LPBK -// -// I2C loopback -// -// 0: Normal operation -// 1: Loopback operation (test mode) -// ENUMs: -// EN Enable Test Mode -// DIS Disable Test Mode -#define I2C_MCR_LPBK 0x00000001 -#define I2C_MCR_LPBK_BITN 0 -#define I2C_MCR_LPBK_M 0x00000001 -#define I2C_MCR_LPBK_S 0 -#define I2C_MCR_LPBK_EN 0x00000001 -#define I2C_MCR_LPBK_DIS 0x00000000 - - -#endif // __I2C__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h deleted file mode 100644 index c7ed79aa217..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_i2s.h +++ /dev/null @@ -1,967 +0,0 @@ -/****************************************************************************** -* Filename: hw_i2s_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_I2S_H__ -#define __HW_I2S_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// I2S component -// -//***************************************************************************** -// WCLK Source Selection -#define I2S_O_AIFWCLKSRC 0x00000000 - -// DMA Buffer Size Configuration -#define I2S_O_AIFDMACFG 0x00000004 - -// Pin Direction -#define I2S_O_AIFDIRCFG 0x00000008 - -// Serial Interface Format Configuration -#define I2S_O_AIFFMTCFG 0x0000000C - -// Word Selection Bit Mask for Pin 0 -#define I2S_O_AIFWMASK0 0x00000010 - -// Word Selection Bit Mask for Pin 1 -#define I2S_O_AIFWMASK1 0x00000014 - -// Audio Interface PWM Debug Value -#define I2S_O_AIFPWMVALUE 0x0000001C - -// DMA Input Buffer Next Pointer -#define I2S_O_AIFINPTRNEXT 0x00000020 - -// DMA Input Buffer Current Pointer -#define I2S_O_AIFINPTR 0x00000024 - -// DMA Output Buffer Next Pointer -#define I2S_O_AIFOUTPTRNEXT 0x00000028 - -// DMA Output Buffer Current Pointer -#define I2S_O_AIFOUTPTR 0x0000002C - -// Samplestamp Generator Control Register -#define I2S_O_STMPCTL 0x00000034 - -// Captured XOSC Counter Value, Capture Channel 0 -#define I2S_O_STMPXCNTCAPT0 0x00000038 - -// XOSC Period Value -#define I2S_O_STMPXPER 0x0000003C - -// Captured WCLK Counter Value, Capture Channel 0 -#define I2S_O_STMPWCNTCAPT0 0x00000040 - -// WCLK Counter Period Value -#define I2S_O_STMPWPER 0x00000044 - -// WCLK Counter Trigger Value for Input Pins -#define I2S_O_STMPINTRIG 0x00000048 - -// WCLK Counter Trigger Value for Output Pins -#define I2S_O_STMPOUTTRIG 0x0000004C - -// WCLK Counter Set Operation -#define I2S_O_STMPWSET 0x00000050 - -// WCLK Counter Add Operation -#define I2S_O_STMPWADD 0x00000054 - -// XOSC Minimum Period Value -#define I2S_O_STMPXPERMIN 0x00000058 - -// Current Value of WCNT -#define I2S_O_STMPWCNT 0x0000005C - -// Current Value of XCNT -#define I2S_O_STMPXCNT 0x00000060 - -// Internal -#define I2S_O_STMPXCNTCAPT1 0x00000064 - -// Internal -#define I2S_O_STMPWCNTCAPT1 0x00000068 - -// Interrupt Mask Register -#define I2S_O_IRQMASK 0x00000070 - -// Raw Interrupt Status Register -#define I2S_O_IRQFLAGS 0x00000074 - -// Interrupt Set Register -#define I2S_O_IRQSET 0x00000078 - -// Interrupt Clear Register -#define I2S_O_IRQCLR 0x0000007C - -//***************************************************************************** -// -// Register: I2S_O_AIFWCLKSRC -// -//***************************************************************************** -// Field: [2] WCLK_INV -// -// Inverts WCLK source (pad or internal) when set. -// -// 0: Not inverted -// 1: Inverted -#define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 -#define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 -#define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 -#define I2S_AIFWCLKSRC_WCLK_INV_S 2 - -// Field: [1:0] WCLK_SRC -// -// Selects WCLK source for AIF (should be the same as the BCLK source). The -// BCLK source is defined in the PRCM:I2SBCLKSEL.SRC -// ENUMs: -// RESERVED Not supported. Will give same WCLK as 'NONE' -// ('00') -// INT Internal WCLK generator, from module PRCM -// EXT External WCLK generator, from pad -// NONE None ('0') -#define I2S_AIFWCLKSRC_WCLK_SRC_W 2 -#define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 -#define I2S_AIFWCLKSRC_WCLK_SRC_S 0 -#define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 -#define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 -#define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 -#define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 - -//***************************************************************************** -// -// Register: I2S_O_AIFDMACFG -// -//***************************************************************************** -// Field: [7:0] END_FRAME_IDX -// -// Defines the length of the DMA buffer. Writing a non-zero value to this -// register field enables and initializes AIF. Note that before doing so, all -// other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must -// have been loaded. -#define I2S_AIFDMACFG_END_FRAME_IDX_W 8 -#define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF -#define I2S_AIFDMACFG_END_FRAME_IDX_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFDIRCFG -// -//***************************************************************************** -// Field: [5:4] AD1 -// -// Configures the AD1 audio data pin usage: -// -// 0x3: Reserved -// ENUMs: -// OUT Output mode -// IN Input mode -// DIS Not in use (disabled) -#define I2S_AIFDIRCFG_AD1_W 2 -#define I2S_AIFDIRCFG_AD1_M 0x00000030 -#define I2S_AIFDIRCFG_AD1_S 4 -#define I2S_AIFDIRCFG_AD1_OUT 0x00000020 -#define I2S_AIFDIRCFG_AD1_IN 0x00000010 -#define I2S_AIFDIRCFG_AD1_DIS 0x00000000 - -// Field: [1:0] AD0 -// -// Configures the AD0 audio data pin usage: -// -// 0x3: Reserved -// ENUMs: -// OUT Output mode -// IN Input mode -// DIS Not in use (disabled) -#define I2S_AIFDIRCFG_AD0_W 2 -#define I2S_AIFDIRCFG_AD0_M 0x00000003 -#define I2S_AIFDIRCFG_AD0_S 0 -#define I2S_AIFDIRCFG_AD0_OUT 0x00000002 -#define I2S_AIFDIRCFG_AD0_IN 0x00000001 -#define I2S_AIFDIRCFG_AD0_DIS 0x00000000 - -//***************************************************************************** -// -// Register: I2S_O_AIFFMTCFG -// -//***************************************************************************** -// Field: [15:8] DATA_DELAY -// -// The number of BCLK periods between a WCLK edge and MSB of the first word in -// a phase: -// -// 0x00: LJF and DSP format -// 0x01: I2S and DSP format -// 0x02: RJF format -// ... -// 0xFF: RJF format -// -// Note: When 0, MSB of the next word will be output in the idle period between -// LSB of the previous word and the start of the next word. Otherwise logical 0 -// will be output until the data delay has expired. -#define I2S_AIFFMTCFG_DATA_DELAY_W 8 -#define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 -#define I2S_AIFFMTCFG_DATA_DELAY_S 8 - -// Field: [7] MEM_LEN_24 -// -// The size of each word stored to or loaded from memory: -// ENUMs: -// 24BIT 24-bit (one 8 bit and one 16 bit locked access per -// sample) -// 16BIT 16-bit (one 16 bit access per sample) -#define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 -#define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_S 7 -#define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 -#define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 - -// Field: [6] SMPL_EDGE -// -// On the serial audio interface, data (and wclk) is sampled and clocked out on -// opposite edges of BCLK. -// ENUMs: -// POS Data is sampled on the positive edge and clocked -// out on the negative edge. -// NEG Data is sampled on the negative edge and clocked -// out on the positive edge. -#define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 -#define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_S 6 -#define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 -#define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 - -// Field: [5] DUAL_PHASE -// -// Selects dual- or single-phase format. -// -// 0: Single-phase: DSP format -// 1: Dual-phase: I2S, LJF and RJF formats -#define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 -#define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 -#define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 -#define I2S_AIFFMTCFG_DUAL_PHASE_S 5 - -// Field: [4:0] WORD_LEN -// -// Number of bits per word (8-24): -// In single-phase format, this is the exact number of bits per word. -// In dual-phase format, this is the maximum number of bits per word. -// -// Values below 8 and above 24 give undefined behavior. Data written to memory -// is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that -// differ from this alignment will either be truncated or zero padded. -#define I2S_AIFFMTCFG_WORD_LEN_W 5 -#define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F -#define I2S_AIFFMTCFG_WORD_LEN_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFWMASK0 -// -//***************************************************************************** -// Field: [7:0] MASK -// -// Bit-mask indicating valid channels in a frame on AD0. -// -// In single-phase mode, each bit represents one channel, starting with LSB for -// the first word in the frame. A frame can contain up to 8 channels. Channels -// that are not included in the mask will not be sampled and stored in memory, -// and clocked out as '0'. -// -// In dual-phase mode, only the two LSBs are considered. For a stereo -// configuration, set both bits. For a mono configuration, set bit 0 only. In -// mono mode, only channel 0 will be sampled and stored to memory, and channel -// 0 will be repeated when clocked out. -// -// In mono mode, only channel 0 will be sampled and stored to memory, and -// channel 0 will be repeated in the second phase when clocked out. -// -// If all bits are zero, no input words will be stored to memory, and the -// output data lines will be constant '0'. This can be utilized when PWM debug -// output is desired without any actively used output pins. -#define I2S_AIFWMASK0_MASK_W 8 -#define I2S_AIFWMASK0_MASK_M 0x000000FF -#define I2S_AIFWMASK0_MASK_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFWMASK1 -// -//***************************************************************************** -// Field: [7:0] MASK -// -// Bit-mask indicating valid channels in a frame on AD1. -// -// In single-phase mode, each bit represents one channel, starting with LSB for -// the first word in the frame. A frame can contain up to 8 channels. Channels -// that are not included in the mask will not be sampled and stored in memory, -// and clocked out as '0'. -// -// In dual-phase mode, only the two LSBs are considered. For a stereo -// configuration, set both bits. For a mono configuration, set bit 0 only. In -// mono mode, only channel 0 will be sampled and stored to memory, and channel -// 0 will be repeated when clocked out. -// -// In mono mode, only channel 0 will be sampled and stored to memory, and -// channel 0 will be repeated in the second phase when clocked out. -// -// If all bits are zero, no input words will be stored to memory, and the -// output data lines will be constant '0'. This can be utilized when PWM debug -// output is desired without any actively used output pins. -#define I2S_AIFWMASK1_MASK_W 8 -#define I2S_AIFWMASK1_MASK_M 0x000000FF -#define I2S_AIFWMASK1_MASK_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFPWMVALUE -// -//***************************************************************************** -// Field: [15:0] PULSE_WIDTH -// -// The value written to this register determines the width of the active high -// PWM pulse (pwm_debug), which starts together with MSB of the first output -// word in a DMA buffer: -// -// 0x0000: Constant low -// 0x0001: Width of the pulse (number of BCLK cycles, here 1). -// ... -// 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). -// 0xFFFF: Constant high -#define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 -#define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF -#define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFINPTRNEXT -// -//***************************************************************************** -// Field: [31:0] PTR -// -// Pointer to the first byte in the next DMA input buffer. -// -// The read value equals the last written value until the currently used DMA -// input buffer is completed, and then becomes null when the last written value -// is transferred to the DMA controller to start on the next buffer. This event -// is signalized by IRQFLAGS.AIF_DMA_IN. -// -// At startup, the value must be written once before and once after configuring -// the DMA buffer size in AIFDMACFG. -// -// The next pointer must be written to this register while the DMA function -// uses the previously written pointer. If not written in time, -// IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. -#define I2S_AIFINPTRNEXT_PTR_W 32 -#define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF -#define I2S_AIFINPTRNEXT_PTR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFINPTR -// -//***************************************************************************** -// Field: [31:0] PTR -// -// Value of the DMA input buffer pointer currently used by the DMA controller. -// Incremented by 1 (byte) or 2 (word) for each AHB access. -#define I2S_AIFINPTR_PTR_W 32 -#define I2S_AIFINPTR_PTR_M 0xFFFFFFFF -#define I2S_AIFINPTR_PTR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFOUTPTRNEXT -// -//***************************************************************************** -// Field: [31:0] PTR -// -// Pointer to the first byte in the next DMA output buffer. -// -// The read value equals the last written value until the currently used DMA -// output buffer is completed, and then becomes null when the last written -// value is transferred to the DMA controller to start on the next buffer. This -// event is signalized by IRQFLAGS.AIF_DMA_OUT. -// -// At startup, the value must be written once before and once after configuring -// the DMA buffer size in AIFDMACFG. At this time, the first two samples will -// be fetched from memory. -// -// The next pointer must be written to this register while the DMA function -// uses the previously written pointer. If not written in time, -// IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. -#define I2S_AIFOUTPTRNEXT_PTR_W 32 -#define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF -#define I2S_AIFOUTPTRNEXT_PTR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_AIFOUTPTR -// -//***************************************************************************** -// Field: [31:0] PTR -// -// Value of the DMA output buffer pointer currently used by the DMA controller -// Incremented by 1 (byte) or 2 (word) for each AHB access. -#define I2S_AIFOUTPTR_PTR_W 32 -#define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF -#define I2S_AIFOUTPTR_PTR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPCTL -// -//***************************************************************************** -// Field: [2] OUT_RDY -// -// Low until the output pins are ready to be started by the samplestamp -// generator. When started (that is STMPOUTTRIG equals the WCLK counter) the -// bit goes back low. -#define I2S_STMPCTL_OUT_RDY 0x00000004 -#define I2S_STMPCTL_OUT_RDY_BITN 2 -#define I2S_STMPCTL_OUT_RDY_M 0x00000004 -#define I2S_STMPCTL_OUT_RDY_S 2 - -// Field: [1] IN_RDY -// -// Low until the input pins are ready to be started by the samplestamp -// generator. When started (that is STMPINTRIG equals the WCLK counter) the bit -// goes back low. -#define I2S_STMPCTL_IN_RDY 0x00000002 -#define I2S_STMPCTL_IN_RDY_BITN 1 -#define I2S_STMPCTL_IN_RDY_M 0x00000002 -#define I2S_STMPCTL_IN_RDY_S 1 - -// Field: [0] STMP_EN -// -// Enables the samplestamp generator. The samplestamp generator must only be -// enabled after it has been properly configured. -// When cleared, all samplestamp generator counters and capture values are -// cleared. -#define I2S_STMPCTL_STMP_EN 0x00000001 -#define I2S_STMPCTL_STMP_EN_BITN 0 -#define I2S_STMPCTL_STMP_EN_M 0x00000001 -#define I2S_STMPCTL_STMP_EN_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPXCNTCAPT0 -// -//***************************************************************************** -// Field: [15:0] CAPT_VALUE -// -// The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an -// event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for -// channel 0). This number corresponds to the number of 24 MHz clock cycles -// since the last positive edge of the selected WCLK. -// The value is cleared when STMPCTL.STMP_EN = 0. -// Note: Due to buffering and synchronization, WCLK is delayed by a small -// number of BCLK periods and clk periods. -// Note: When calculating the fractional part of the sample stamp, STMPXPER may -// be less than this bit field. -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPXPER -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// The number of 24 MHz clock cycles in the previous WCLK period (that is - -// the next value of the XOSC counter at the positive WCLK edge, had it not -// been reset to 0). -// The value is cleared when STMPCTL.STMP_EN = 0. -#define I2S_STMPXPER_VALUE_W 16 -#define I2S_STMPXPER_VALUE_M 0x0000FFFF -#define I2S_STMPXPER_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPWCNTCAPT0 -// -//***************************************************************************** -// Field: [15:0] CAPT_VALUE -// -// The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an -// event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel -// 0). This number corresponds to the number of positive WCLK edges since the -// samplestamp generator was enabled (not taking modification through -// STMPWADD/STMPWSET into account). -// The value is cleared when STMPCTL.STMP_EN = 0. -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPWPER -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Used to define when STMPWCNT is to be reset so number of WCLK edges are -// found for the size of the sample buffer. This is thus a modulo value for the -// WCLK counter. This number must correspond to the size of the sample buffer -// used by the system (that is the index of the last sample plus 1). -#define I2S_STMPWPER_VALUE_W 16 -#define I2S_STMPWPER_VALUE_M 0x0000FFFF -#define I2S_STMPWPER_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPINTRIG -// -//***************************************************************************** -// Field: [15:0] IN_START_WCNT -// -// Compare value used to start the incoming audio streams. -// This bit field shall equal the WCLK counter value during the WCLK period in -// which the first input word(s) are sampled and stored to memory (that is the -// sample at the start of the very first DMA input buffer). -// -// The value of this register takes effect when the following conditions are -// met: -// - One or more pins are configured as inputs in AIFDIRCFG. -// - AIFDMACFG has been configured for the correct buffer size, and at least 32 -// BCLK cycle ticks have happened. -// -// Note: To avoid false triggers, this bit field should be set higher than -// STMPWPER.VALUE. -#define I2S_STMPINTRIG_IN_START_WCNT_W 16 -#define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF -#define I2S_STMPINTRIG_IN_START_WCNT_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPOUTTRIG -// -//***************************************************************************** -// Field: [15:0] OUT_START_WCNT -// -// Compare value used to start the outgoing audio streams. -// -// This bit field must equal the WCLK counter value during the WCLK period in -// which the first output word(s) read from memory are clocked out (that is the -// sample at the start of the very first DMA output buffer). -// -// The value of this register takes effect when the following conditions are -// met: -// - One or more pins are configured as outputs in AIFDIRCFG. -// - AIFDMACFG has been configured for the correct buffer size, and 32 BCLK -// cycle ticks have happened. -// - 2 samples have been preloaded from memory (examine the AIFOUTPTR register -// if necessary). -// Note: The memory read access is only performed when required, that is -// channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. -// -// Note: To avoid false triggers, this bit field should be set higher than -// STMPWPER.VALUE. -#define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 -#define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF -#define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPWSET -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// WCLK counter modification: Sets the running WCLK counter equal to the -// written value. -#define I2S_STMPWSET_VALUE_W 16 -#define I2S_STMPWSET_VALUE_M 0x0000FFFF -#define I2S_STMPWSET_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPWADD -// -//***************************************************************************** -// Field: [15:0] VALUE_INC -// -// WCLK counter modification: Adds the written value to the running WCLK -// counter. If a positive edge of WCLK occurs at the same time as the -// operation, this will be taken into account. -// To add a negative value, write "STMPWPER.VALUE - value". -// -#define I2S_STMPWADD_VALUE_INC_W 16 -#define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF -#define I2S_STMPWADD_VALUE_INC_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPXPERMIN -// -//***************************************************************************** -// Field: [15:0] VALUE -// -// Each time STMPXPER is updated, the value is also loaded into this register, -// provided that the value is smaller than the current value in this register. -// When written, the register is reset to 0xFFFF (65535), regardless of the -// value written. -// The minimum value can be used to detect extra WCLK pulses (this registers -// value will be significantly smaller than STMPXPER.VALUE). -#define I2S_STMPXPERMIN_VALUE_W 16 -#define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF -#define I2S_STMPXPERMIN_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPWCNT -// -//***************************************************************************** -// Field: [15:0] CURR_VALUE -// -// Current value of the WCLK counter -#define I2S_STMPWCNT_CURR_VALUE_W 16 -#define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF -#define I2S_STMPWCNT_CURR_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPXCNT -// -//***************************************************************************** -// Field: [15:0] CURR_VALUE -// -// Current value of the XOSC counter, latched when reading STMPWCNT. -#define I2S_STMPXCNT_CURR_VALUE_W 16 -#define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF -#define I2S_STMPXCNT_CURR_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPXCNTCAPT1 -// -//***************************************************************************** -// Field: [15:0] CAPT_VALUE -// -// Internal. Only to be used through TI provided API. -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_STMPWCNTCAPT1 -// -//***************************************************************************** -// Field: [15:0] CAPT_VALUE -// -// Internal. Only to be used through TI provided API. -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF -#define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 - -//***************************************************************************** -// -// Register: I2S_O_IRQMASK -// -//***************************************************************************** -// Field: [5] AIF_DMA_IN -// -// IRQFLAGS.AIF_DMA_IN interrupt mask -// -// 0: Disable -// 1: Enable -#define I2S_IRQMASK_AIF_DMA_IN 0x00000020 -#define I2S_IRQMASK_AIF_DMA_IN_BITN 5 -#define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQMASK_AIF_DMA_IN_S 5 - -// Field: [4] AIF_DMA_OUT -// -// IRQFLAGS.AIF_DMA_OUT interrupt mask -// -// 0: Disable -// 1: Enable -#define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 -#define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 -#define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQMASK_AIF_DMA_OUT_S 4 - -// Field: [3] WCLK_TIMEOUT -// -// IRQFLAGS.WCLK_TIMEOUT interrupt mask -// -// 0: Disable -// 1: Enable -#define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQMASK_WCLK_TIMEOUT_S 3 - -// Field: [2] BUS_ERR -// -// IRQFLAGS.BUS_ERR interrupt mask -// -// 0: Disable -// 1: Enable -#define I2S_IRQMASK_BUS_ERR 0x00000004 -#define I2S_IRQMASK_BUS_ERR_BITN 2 -#define I2S_IRQMASK_BUS_ERR_M 0x00000004 -#define I2S_IRQMASK_BUS_ERR_S 2 - -// Field: [1] WCLK_ERR -// -// IRQFLAGS.WCLK_ERR interrupt mask -// -// 0: Disable -// 1: Enable -#define I2S_IRQMASK_WCLK_ERR 0x00000002 -#define I2S_IRQMASK_WCLK_ERR_BITN 1 -#define I2S_IRQMASK_WCLK_ERR_M 0x00000002 -#define I2S_IRQMASK_WCLK_ERR_S 1 - -// Field: [0] PTR_ERR -// -// IRQFLAGS.PTR_ERR interrupt mask. -// -// 0: Disable -// 1: Enable -#define I2S_IRQMASK_PTR_ERR 0x00000001 -#define I2S_IRQMASK_PTR_ERR_BITN 0 -#define I2S_IRQMASK_PTR_ERR_M 0x00000001 -#define I2S_IRQMASK_PTR_ERR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_IRQFLAGS -// -//***************************************************************************** -// Field: [5] AIF_DMA_IN -// -// Set when condition for this bit field event occurs (auto cleared when input -// pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register -// for details. -#define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 -#define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 -#define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQFLAGS_AIF_DMA_IN_S 5 - -// Field: [4] AIF_DMA_OUT -// -// Set when condition for this bit field event occurs (auto cleared when output -// pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT -// register for details -#define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 -#define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 -#define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 - -// Field: [3] WCLK_TIMEOUT -// -// Set when the sample stamp generator does not detect a positive WCLK edge for -// 65535 clk periods. This signalizes that the internal or external BCLK and -// WCLK generator source has been disabled. -// -// The bit is sticky and may only be cleared by software (by writing '1' to -// IRQCLR.WCLK_TIMEOUT). -#define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 - -// Field: [2] BUS_ERR -// -// Set when a DMA operation is not completed in time (that is audio output -// buffer underflow, or audio input buffer overflow). -// This error requires a complete restart since word synchronization has been -// lost. The bit is sticky and may only be cleared by software (by writing '1' -// to IRQCLR.BUS_ERR). -// -// Note that DMA initiated transactions to illegal addresses will not trigger -// an interrupt. The response to such transactions is undefined. -#define I2S_IRQFLAGS_BUS_ERR 0x00000004 -#define I2S_IRQFLAGS_BUS_ERR_BITN 2 -#define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 -#define I2S_IRQFLAGS_BUS_ERR_S 2 - -// Field: [1] WCLK_ERR -// -// Set when: -// - An unexpected WCLK edge occurs during the data delay period of a phase. -// Note unexpected WCLK edges during the word and idle periods of the phase are -// not detected. -// - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles -// apart. -// - In single-phase mode, when a WCLK pulse occurs before the last channel. -// This error requires a complete restart since word synchronization has been -// lost. The bit is sticky and may only be cleared by software (by writing '1' -// to IRQCLR.WCLK_ERR). -#define I2S_IRQFLAGS_WCLK_ERR 0x00000002 -#define I2S_IRQFLAGS_WCLK_ERR_BITN 1 -#define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 -#define I2S_IRQFLAGS_WCLK_ERR_S 1 - -// Field: [0] PTR_ERR -// -// Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next -// block address in time. -// This error requires a complete restart since word synchronization has been -// lost. The bit is sticky and may only be cleared by software (by writing '1' -// to IRQCLR.PTR_ERR). -#define I2S_IRQFLAGS_PTR_ERR 0x00000001 -#define I2S_IRQFLAGS_PTR_ERR_BITN 0 -#define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 -#define I2S_IRQFLAGS_PTR_ERR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_IRQSET -// -//***************************************************************************** -// Field: [5] AIF_DMA_IN -// -// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria -// was given at the same time, in which the set will be ignored) -#define I2S_IRQSET_AIF_DMA_IN 0x00000020 -#define I2S_IRQSET_AIF_DMA_IN_BITN 5 -#define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQSET_AIF_DMA_IN_S 5 - -// Field: [4] AIF_DMA_OUT -// -// 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria -// was given at the same time, in which the set will be ignored) -#define I2S_IRQSET_AIF_DMA_OUT 0x00000010 -#define I2S_IRQSET_AIF_DMA_OUT_BITN 4 -#define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQSET_AIF_DMA_OUT_S 4 - -// Field: [3] WCLK_TIMEOUT -// -// 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT -#define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQSET_WCLK_TIMEOUT_S 3 - -// Field: [2] BUS_ERR -// -// 1: Sets the interrupt of IRQFLAGS.BUS_ERR -#define I2S_IRQSET_BUS_ERR 0x00000004 -#define I2S_IRQSET_BUS_ERR_BITN 2 -#define I2S_IRQSET_BUS_ERR_M 0x00000004 -#define I2S_IRQSET_BUS_ERR_S 2 - -// Field: [1] WCLK_ERR -// -// 1: Sets the interrupt of IRQFLAGS.WCLK_ERR -#define I2S_IRQSET_WCLK_ERR 0x00000002 -#define I2S_IRQSET_WCLK_ERR_BITN 1 -#define I2S_IRQSET_WCLK_ERR_M 0x00000002 -#define I2S_IRQSET_WCLK_ERR_S 1 - -// Field: [0] PTR_ERR -// -// 1: Sets the interrupt of IRQFLAGS.PTR_ERR -#define I2S_IRQSET_PTR_ERR 0x00000001 -#define I2S_IRQSET_PTR_ERR_BITN 0 -#define I2S_IRQSET_PTR_ERR_M 0x00000001 -#define I2S_IRQSET_PTR_ERR_S 0 - -//***************************************************************************** -// -// Register: I2S_O_IRQCLR -// -//***************************************************************************** -// Field: [5] AIF_DMA_IN -// -// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was -// given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_AIF_DMA_IN 0x00000020 -#define I2S_IRQCLR_AIF_DMA_IN_BITN 5 -#define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 -#define I2S_IRQCLR_AIF_DMA_IN_S 5 - -// Field: [4] AIF_DMA_OUT -// -// 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was -// given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 -#define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 -#define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 -#define I2S_IRQCLR_AIF_DMA_OUT_S 4 - -// Field: [3] WCLK_TIMEOUT -// -// 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was -// given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 -#define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 -#define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 -#define I2S_IRQCLR_WCLK_TIMEOUT_S 3 - -// Field: [2] BUS_ERR -// -// 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given -// at the same time in which the clear will be ignored) -#define I2S_IRQCLR_BUS_ERR 0x00000004 -#define I2S_IRQCLR_BUS_ERR_BITN 2 -#define I2S_IRQCLR_BUS_ERR_M 0x00000004 -#define I2S_IRQCLR_BUS_ERR_S 2 - -// Field: [1] WCLK_ERR -// -// 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was -// given at the same time in which the clear will be ignored) -#define I2S_IRQCLR_WCLK_ERR 0x00000002 -#define I2S_IRQCLR_WCLK_ERR_BITN 1 -#define I2S_IRQCLR_WCLK_ERR_M 0x00000002 -#define I2S_IRQCLR_WCLK_ERR_S 1 - -// Field: [0] PTR_ERR -// -// 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given -// at the same time in which the clear will be ignored) -#define I2S_IRQCLR_PTR_ERR 0x00000001 -#define I2S_IRQCLR_PTR_ERR_BITN 0 -#define I2S_IRQCLR_PTR_ERR_M 0x00000001 -#define I2S_IRQCLR_PTR_ERR_S 0 - - -#endif // __I2S__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h deleted file mode 100644 index 940695ecac1..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ints.h +++ /dev/null @@ -1,120 +0,0 @@ -/****************************************************************************** -* Filename: hw_ints_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following are defines for the interrupt assignments. -// -//***************************************************************************** -#define INT_NMI_FAULT 2 // NMI Fault -#define INT_HARD_FAULT 3 // Hard Fault -#define INT_MEMMANAGE_FAULT 4 // Memory Management (MemManage) - // Fault -#define INT_BUS_FAULT 5 // Bus Fault -#define INT_USAGE_FAULT 6 // Usage Fault -#define INT_SVCALL 11 // Supervisor Call (SVCall) -#define INT_DEBUG 12 // Debug Monitor -#define INT_PENDSV 14 // Pending Service Call (PendSV) -#define INT_SYSTICK 15 // SysTick Interrupt from the - // System Timer in NVIC. -#define INT_AON_GPIO_EDGE 16 // Edge detect event from IOC -#define INT_I2C_IRQ 17 // Interrupt event from I2C -#define INT_RFC_CPE_1 18 // Combined Interrupt for CPE - // Generated events -#define INT_PKA_IRQ 19 // PKA Interrupt event -#define INT_AON_RTC_COMB 20 // Event from AON_RTC -#define INT_UART0_COMB 21 // UART0 combined interrupt -#define INT_AUX_SWEV0 22 // AUX software event 0 -#define INT_SSI0_COMB 23 // SSI0 combined interrupt -#define INT_SSI1_COMB 24 // SSI1 combined interrupt -#define INT_RFC_CPE_0 25 // Combined Interrupt for CPE - // Generated events -#define INT_RFC_HW_COMB 26 // Combined RFC hardware interrupt -#define INT_RFC_CMD_ACK 27 // RFC Doorbell Command - // Acknowledgement Interrupt -#define INT_I2S_IRQ 28 // Interrupt event from I2S -#define INT_AUX_SWEV1 29 // AUX software event 1 -#define INT_WDT_IRQ 30 // Watchdog interrupt event -#define INT_GPT0A 31 // GPT0A interrupt event -#define INT_GPT0B 32 // GPT0B interrupt event -#define INT_GPT1A 33 // GPT1A interrupt event -#define INT_GPT1B 34 // GPT1B interrupt event -#define INT_GPT2A 35 // GPT2A interrupt event -#define INT_GPT2B 36 // GPT2B interrupt event -#define INT_GPT3A 37 // GPT3A interrupt event -#define INT_GPT3B 38 // GPT3B interrupt event -#define INT_CRYPTO_RESULT_AVAIL_IRQ 39 // CRYPTO result available interupt - // event -#define INT_DMA_DONE_COMB 40 // Combined DMA done -#define INT_DMA_ERR 41 // DMA bus error -#define INT_FLASH 42 // FLASH controller error event -#define INT_SWEV0 43 // Software event 0 -#define INT_AUX_COMB 44 // AUX combined event -#define INT_AON_PROG0 45 // AON programmable event 0 -#define INT_PROG0 46 // Programmable Interrupt 0 -#define INT_AUX_COMPA 47 // AUX Compare A event -#define INT_AUX_ADC_IRQ 48 // AUX ADC interrupt event -#define INT_TRNG_IRQ 49 // TRNG Interrupt event -#define INT_OSC_COMB 50 // Combined event from Oscillator - // control -#define INT_AUX_TIMER2_EV0 51 // AUX Timer2 event 0 -#define INT_UART1_COMB 52 // UART1 combined interrupt -#define INT_BATMON_COMB 53 // Combined event from battery - // monitor - -//***************************************************************************** -// -// The following are defines for number of interrupts and priority levels. -// -//***************************************************************************** -#define NUM_INTERRUPTS 54 // Number of interrupts -#define NUM_PRIORITY_BITS 3 // Number of Priority bits -#define NUM_PRIORITY 8 // Number of priority levels - - -//***************************************************************************** -// -// Aliases for backwards compatibility with Sensor Controller Studio 1.1.0 -// -//***************************************************************************** - -#define INT_AON_AUX_SWEV0 INT_AUX_SWEV0 -#define INT_AON_AUX_SWEV1 INT_AUX_SWEV1 - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h deleted file mode 100644 index 9e7c982a812..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ioc.h +++ /dev/null @@ -1,11887 +0,0 @@ -/****************************************************************************** -* Filename: hw_ioc_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_IOC_H__ -#define __HW_IOC_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// IOC component -// -//***************************************************************************** -// Configuration of DIO0 -#define IOC_O_IOCFG0 0x00000000 - -// Configuration of DIO1 -#define IOC_O_IOCFG1 0x00000004 - -// Configuration of DIO2 -#define IOC_O_IOCFG2 0x00000008 - -// Configuration of DIO3 -#define IOC_O_IOCFG3 0x0000000C - -// Configuration of DIO4 -#define IOC_O_IOCFG4 0x00000010 - -// Configuration of DIO5 -#define IOC_O_IOCFG5 0x00000014 - -// Configuration of DIO6 -#define IOC_O_IOCFG6 0x00000018 - -// Configuration of DIO7 -#define IOC_O_IOCFG7 0x0000001C - -// Configuration of DIO8 -#define IOC_O_IOCFG8 0x00000020 - -// Configuration of DIO9 -#define IOC_O_IOCFG9 0x00000024 - -// Configuration of DIO10 -#define IOC_O_IOCFG10 0x00000028 - -// Configuration of DIO11 -#define IOC_O_IOCFG11 0x0000002C - -// Configuration of DIO12 -#define IOC_O_IOCFG12 0x00000030 - -// Configuration of DIO13 -#define IOC_O_IOCFG13 0x00000034 - -// Configuration of DIO14 -#define IOC_O_IOCFG14 0x00000038 - -// Configuration of DIO15 -#define IOC_O_IOCFG15 0x0000003C - -// Configuration of DIO16 -#define IOC_O_IOCFG16 0x00000040 - -// Configuration of DIO17 -#define IOC_O_IOCFG17 0x00000044 - -// Configuration of DIO18 -#define IOC_O_IOCFG18 0x00000048 - -// Configuration of DIO19 -#define IOC_O_IOCFG19 0x0000004C - -// Configuration of DIO20 -#define IOC_O_IOCFG20 0x00000050 - -// Configuration of DIO21 -#define IOC_O_IOCFG21 0x00000054 - -// Configuration of DIO22 -#define IOC_O_IOCFG22 0x00000058 - -// Configuration of DIO23 -#define IOC_O_IOCFG23 0x0000005C - -// Configuration of DIO24 -#define IOC_O_IOCFG24 0x00000060 - -// Configuration of DIO25 -#define IOC_O_IOCFG25 0x00000064 - -// Configuration of DIO26 -#define IOC_O_IOCFG26 0x00000068 - -// Configuration of DIO27 -#define IOC_O_IOCFG27 0x0000006C - -// Configuration of DIO28 -#define IOC_O_IOCFG28 0x00000070 - -// Configuration of DIO29 -#define IOC_O_IOCFG29 0x00000074 - -// Configuration of DIO30 -#define IOC_O_IOCFG30 0x00000078 - -// Configuration of DIO31 -#define IOC_O_IOCFG31 0x0000007C - -//***************************************************************************** -// -// Register: IOC_O_IOCFG0 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG0_HYST_EN 0x40000000 -#define IOC_IOCFG0_HYST_EN_BITN 30 -#define IOC_IOCFG0_HYST_EN_M 0x40000000 -#define IOC_IOCFG0_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG0_IE 0x20000000 -#define IOC_IOCFG0_IE_BITN 29 -#define IOC_IOCFG0_IE_M 0x20000000 -#define IOC_IOCFG0_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG0_WU_CFG_W 2 -#define IOC_IOCFG0_WU_CFG_M 0x18000000 -#define IOC_IOCFG0_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input/output -// OPENSRC Open Source -// Normal input / outut -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG0_IOMODE_W 3 -#define IOC_IOCFG0_IOMODE_M 0x07000000 -#define IOC_IOCFG0_IOMODE_S 24 -#define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG0_IOMODE_INV 0x01000000 -#define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG0_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG0_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG0_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG0_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG0_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG0_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG0_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG0_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG0_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG0_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG0_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG0_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG0_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG0_EDGE_DET_W 2 -#define IOC_IOCFG0_EDGE_DET_M 0x00030000 -#define IOC_IOCFG0_EDGE_DET_S 16 -#define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG0_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG0_PULL_CTL_W 2 -#define IOC_IOCFG0_PULL_CTL_M 0x00006000 -#define IOC_IOCFG0_PULL_CTL_S 13 -#define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG0_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG0_SLEW_RED 0x00001000 -#define IOC_IOCFG0_SLEW_RED_BITN 12 -#define IOC_IOCFG0_SLEW_RED_M 0x00001000 -#define IOC_IOCFG0_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG0_IOCURR_W 2 -#define IOC_IOCFG0_IOCURR_M 0x00000C00 -#define IOC_IOCFG0_IOCURR_S 10 -#define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG0_IOCURR_4MA 0x00000400 -#define IOC_IOCFG0_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG0_IOSTR_W 2 -#define IOC_IOCFG0_IOSTR_M 0x00000300 -#define IOC_IOCFG0_IOSTR_S 8 -#define IOC_IOCFG0_IOSTR_MAX 0x00000300 -#define IOC_IOCFG0_IOSTR_MED 0x00000200 -#define IOC_IOCFG0_IOSTR_MIN 0x00000100 -#define IOC_IOCFG0_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG0_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG0_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG0_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG0_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG0_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG0_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG0_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG0_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO0 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG0_PORT_ID_W 6 -#define IOC_IOCFG0_PORT_ID_M 0x0000003F -#define IOC_IOCFG0_PORT_ID_S 0 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG0_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG0_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG0_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG0_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG1 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG1_HYST_EN 0x40000000 -#define IOC_IOCFG1_HYST_EN_BITN 30 -#define IOC_IOCFG1_HYST_EN_M 0x40000000 -#define IOC_IOCFG1_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG1_IE 0x20000000 -#define IOC_IOCFG1_IE_BITN 29 -#define IOC_IOCFG1_IE_M 0x20000000 -#define IOC_IOCFG1_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG1_WU_CFG_W 2 -#define IOC_IOCFG1_WU_CFG_M 0x18000000 -#define IOC_IOCFG1_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG1_IOMODE_W 3 -#define IOC_IOCFG1_IOMODE_M 0x07000000 -#define IOC_IOCFG1_IOMODE_S 24 -#define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG1_IOMODE_INV 0x01000000 -#define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG1_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG1_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG1_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG1_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG1_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG1_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG1_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG1_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG1_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG1_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG1_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG1_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG1_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG1_EDGE_DET_W 2 -#define IOC_IOCFG1_EDGE_DET_M 0x00030000 -#define IOC_IOCFG1_EDGE_DET_S 16 -#define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG1_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG1_PULL_CTL_W 2 -#define IOC_IOCFG1_PULL_CTL_M 0x00006000 -#define IOC_IOCFG1_PULL_CTL_S 13 -#define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG1_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG1_SLEW_RED 0x00001000 -#define IOC_IOCFG1_SLEW_RED_BITN 12 -#define IOC_IOCFG1_SLEW_RED_M 0x00001000 -#define IOC_IOCFG1_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG1_IOCURR_W 2 -#define IOC_IOCFG1_IOCURR_M 0x00000C00 -#define IOC_IOCFG1_IOCURR_S 10 -#define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG1_IOCURR_4MA 0x00000400 -#define IOC_IOCFG1_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG1_IOSTR_W 2 -#define IOC_IOCFG1_IOSTR_M 0x00000300 -#define IOC_IOCFG1_IOSTR_S 8 -#define IOC_IOCFG1_IOSTR_MAX 0x00000300 -#define IOC_IOCFG1_IOSTR_MED 0x00000200 -#define IOC_IOCFG1_IOSTR_MIN 0x00000100 -#define IOC_IOCFG1_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG1_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG1_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG1_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG1_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG1_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG1_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG1_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG1_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO1 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG1_PORT_ID_W 6 -#define IOC_IOCFG1_PORT_ID_M 0x0000003F -#define IOC_IOCFG1_PORT_ID_S 0 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG1_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG1_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG1_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG1_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG2 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG2_HYST_EN 0x40000000 -#define IOC_IOCFG2_HYST_EN_BITN 30 -#define IOC_IOCFG2_HYST_EN_M 0x40000000 -#define IOC_IOCFG2_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG2_IE 0x20000000 -#define IOC_IOCFG2_IE_BITN 29 -#define IOC_IOCFG2_IE_M 0x20000000 -#define IOC_IOCFG2_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG2_WU_CFG_W 2 -#define IOC_IOCFG2_WU_CFG_M 0x18000000 -#define IOC_IOCFG2_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG2_IOMODE_W 3 -#define IOC_IOCFG2_IOMODE_M 0x07000000 -#define IOC_IOCFG2_IOMODE_S 24 -#define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG2_IOMODE_INV 0x01000000 -#define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG2_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG2_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG2_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG2_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG2_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG2_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG2_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG2_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG2_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG2_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG2_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG2_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG2_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG2_EDGE_DET_W 2 -#define IOC_IOCFG2_EDGE_DET_M 0x00030000 -#define IOC_IOCFG2_EDGE_DET_S 16 -#define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG2_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG2_PULL_CTL_W 2 -#define IOC_IOCFG2_PULL_CTL_M 0x00006000 -#define IOC_IOCFG2_PULL_CTL_S 13 -#define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG2_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG2_SLEW_RED 0x00001000 -#define IOC_IOCFG2_SLEW_RED_BITN 12 -#define IOC_IOCFG2_SLEW_RED_M 0x00001000 -#define IOC_IOCFG2_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG2_IOCURR_W 2 -#define IOC_IOCFG2_IOCURR_M 0x00000C00 -#define IOC_IOCFG2_IOCURR_S 10 -#define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG2_IOCURR_4MA 0x00000400 -#define IOC_IOCFG2_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG2_IOSTR_W 2 -#define IOC_IOCFG2_IOSTR_M 0x00000300 -#define IOC_IOCFG2_IOSTR_S 8 -#define IOC_IOCFG2_IOSTR_MAX 0x00000300 -#define IOC_IOCFG2_IOSTR_MED 0x00000200 -#define IOC_IOCFG2_IOSTR_MIN 0x00000100 -#define IOC_IOCFG2_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG2_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG2_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG2_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG2_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG2_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG2_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG2_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG2_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO2 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG2_PORT_ID_W 6 -#define IOC_IOCFG2_PORT_ID_M 0x0000003F -#define IOC_IOCFG2_PORT_ID_S 0 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG2_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG2_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG2_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG2_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG3 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG3_HYST_EN 0x40000000 -#define IOC_IOCFG3_HYST_EN_BITN 30 -#define IOC_IOCFG3_HYST_EN_M 0x40000000 -#define IOC_IOCFG3_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG3_IE 0x20000000 -#define IOC_IOCFG3_IE_BITN 29 -#define IOC_IOCFG3_IE_M 0x20000000 -#define IOC_IOCFG3_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG3_WU_CFG_W 2 -#define IOC_IOCFG3_WU_CFG_M 0x18000000 -#define IOC_IOCFG3_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG3_IOMODE_W 3 -#define IOC_IOCFG3_IOMODE_M 0x07000000 -#define IOC_IOCFG3_IOMODE_S 24 -#define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG3_IOMODE_INV 0x01000000 -#define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG3_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG3_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG3_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG3_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG3_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG3_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG3_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG3_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG3_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG3_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG3_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG3_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG3_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG3_EDGE_DET_W 2 -#define IOC_IOCFG3_EDGE_DET_M 0x00030000 -#define IOC_IOCFG3_EDGE_DET_S 16 -#define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG3_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG3_PULL_CTL_W 2 -#define IOC_IOCFG3_PULL_CTL_M 0x00006000 -#define IOC_IOCFG3_PULL_CTL_S 13 -#define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG3_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG3_SLEW_RED 0x00001000 -#define IOC_IOCFG3_SLEW_RED_BITN 12 -#define IOC_IOCFG3_SLEW_RED_M 0x00001000 -#define IOC_IOCFG3_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG3_IOCURR_W 2 -#define IOC_IOCFG3_IOCURR_M 0x00000C00 -#define IOC_IOCFG3_IOCURR_S 10 -#define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG3_IOCURR_4MA 0x00000400 -#define IOC_IOCFG3_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG3_IOSTR_W 2 -#define IOC_IOCFG3_IOSTR_M 0x00000300 -#define IOC_IOCFG3_IOSTR_S 8 -#define IOC_IOCFG3_IOSTR_MAX 0x00000300 -#define IOC_IOCFG3_IOSTR_MED 0x00000200 -#define IOC_IOCFG3_IOSTR_MIN 0x00000100 -#define IOC_IOCFG3_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG3_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG3_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG3_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG3_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG3_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG3_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG3_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG3_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO3 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG3_PORT_ID_W 6 -#define IOC_IOCFG3_PORT_ID_M 0x0000003F -#define IOC_IOCFG3_PORT_ID_S 0 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG3_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG3_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG3_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG3_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG4 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG4_HYST_EN 0x40000000 -#define IOC_IOCFG4_HYST_EN_BITN 30 -#define IOC_IOCFG4_HYST_EN_M 0x40000000 -#define IOC_IOCFG4_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG4_IE 0x20000000 -#define IOC_IOCFG4_IE_BITN 29 -#define IOC_IOCFG4_IE_M 0x20000000 -#define IOC_IOCFG4_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG4_WU_CFG_W 2 -#define IOC_IOCFG4_WU_CFG_M 0x18000000 -#define IOC_IOCFG4_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG4_IOMODE_W 3 -#define IOC_IOCFG4_IOMODE_M 0x07000000 -#define IOC_IOCFG4_IOMODE_S 24 -#define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG4_IOMODE_INV 0x01000000 -#define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG4_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG4_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG4_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG4_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG4_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG4_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG4_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG4_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG4_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG4_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG4_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG4_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG4_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG4_EDGE_DET_W 2 -#define IOC_IOCFG4_EDGE_DET_M 0x00030000 -#define IOC_IOCFG4_EDGE_DET_S 16 -#define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG4_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG4_PULL_CTL_W 2 -#define IOC_IOCFG4_PULL_CTL_M 0x00006000 -#define IOC_IOCFG4_PULL_CTL_S 13 -#define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG4_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG4_SLEW_RED 0x00001000 -#define IOC_IOCFG4_SLEW_RED_BITN 12 -#define IOC_IOCFG4_SLEW_RED_M 0x00001000 -#define IOC_IOCFG4_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG4_IOCURR_W 2 -#define IOC_IOCFG4_IOCURR_M 0x00000C00 -#define IOC_IOCFG4_IOCURR_S 10 -#define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG4_IOCURR_4MA 0x00000400 -#define IOC_IOCFG4_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG4_IOSTR_W 2 -#define IOC_IOCFG4_IOSTR_M 0x00000300 -#define IOC_IOCFG4_IOSTR_S 8 -#define IOC_IOCFG4_IOSTR_MAX 0x00000300 -#define IOC_IOCFG4_IOSTR_MED 0x00000200 -#define IOC_IOCFG4_IOSTR_MIN 0x00000100 -#define IOC_IOCFG4_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG4_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG4_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG4_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG4_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG4_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG4_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG4_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG4_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO4 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG4_PORT_ID_W 6 -#define IOC_IOCFG4_PORT_ID_M 0x0000003F -#define IOC_IOCFG4_PORT_ID_S 0 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG4_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG4_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG4_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG4_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG5 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG5_HYST_EN 0x40000000 -#define IOC_IOCFG5_HYST_EN_BITN 30 -#define IOC_IOCFG5_HYST_EN_M 0x40000000 -#define IOC_IOCFG5_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG5_IE 0x20000000 -#define IOC_IOCFG5_IE_BITN 29 -#define IOC_IOCFG5_IE_M 0x20000000 -#define IOC_IOCFG5_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG5_WU_CFG_W 2 -#define IOC_IOCFG5_WU_CFG_M 0x18000000 -#define IOC_IOCFG5_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG5_IOMODE_W 3 -#define IOC_IOCFG5_IOMODE_M 0x07000000 -#define IOC_IOCFG5_IOMODE_S 24 -#define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG5_IOMODE_INV 0x01000000 -#define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG5_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG5_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG5_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG5_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG5_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG5_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG5_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG5_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG5_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG5_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG5_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG5_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG5_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG5_EDGE_DET_W 2 -#define IOC_IOCFG5_EDGE_DET_M 0x00030000 -#define IOC_IOCFG5_EDGE_DET_S 16 -#define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG5_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG5_PULL_CTL_W 2 -#define IOC_IOCFG5_PULL_CTL_M 0x00006000 -#define IOC_IOCFG5_PULL_CTL_S 13 -#define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG5_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG5_SLEW_RED 0x00001000 -#define IOC_IOCFG5_SLEW_RED_BITN 12 -#define IOC_IOCFG5_SLEW_RED_M 0x00001000 -#define IOC_IOCFG5_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG5_IOCURR_W 2 -#define IOC_IOCFG5_IOCURR_M 0x00000C00 -#define IOC_IOCFG5_IOCURR_S 10 -#define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG5_IOCURR_4MA 0x00000400 -#define IOC_IOCFG5_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG5_IOSTR_W 2 -#define IOC_IOCFG5_IOSTR_M 0x00000300 -#define IOC_IOCFG5_IOSTR_S 8 -#define IOC_IOCFG5_IOSTR_MAX 0x00000300 -#define IOC_IOCFG5_IOSTR_MED 0x00000200 -#define IOC_IOCFG5_IOSTR_MIN 0x00000100 -#define IOC_IOCFG5_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG5_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG5_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG5_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG5_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG5_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG5_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG5_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG5_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO5 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG5_PORT_ID_W 6 -#define IOC_IOCFG5_PORT_ID_M 0x0000003F -#define IOC_IOCFG5_PORT_ID_S 0 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG5_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG5_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG5_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG5_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG6 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG6_HYST_EN 0x40000000 -#define IOC_IOCFG6_HYST_EN_BITN 30 -#define IOC_IOCFG6_HYST_EN_M 0x40000000 -#define IOC_IOCFG6_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG6_IE 0x20000000 -#define IOC_IOCFG6_IE_BITN 29 -#define IOC_IOCFG6_IE_M 0x20000000 -#define IOC_IOCFG6_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG6_WU_CFG_W 2 -#define IOC_IOCFG6_WU_CFG_M 0x18000000 -#define IOC_IOCFG6_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG6_IOMODE_W 3 -#define IOC_IOCFG6_IOMODE_M 0x07000000 -#define IOC_IOCFG6_IOMODE_S 24 -#define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG6_IOMODE_INV 0x01000000 -#define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG6_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG6_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG6_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG6_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG6_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG6_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG6_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG6_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG6_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG6_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG6_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG6_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG6_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG6_EDGE_DET_W 2 -#define IOC_IOCFG6_EDGE_DET_M 0x00030000 -#define IOC_IOCFG6_EDGE_DET_S 16 -#define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG6_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG6_PULL_CTL_W 2 -#define IOC_IOCFG6_PULL_CTL_M 0x00006000 -#define IOC_IOCFG6_PULL_CTL_S 13 -#define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG6_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG6_SLEW_RED 0x00001000 -#define IOC_IOCFG6_SLEW_RED_BITN 12 -#define IOC_IOCFG6_SLEW_RED_M 0x00001000 -#define IOC_IOCFG6_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG6_IOCURR_W 2 -#define IOC_IOCFG6_IOCURR_M 0x00000C00 -#define IOC_IOCFG6_IOCURR_S 10 -#define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG6_IOCURR_4MA 0x00000400 -#define IOC_IOCFG6_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG6_IOSTR_W 2 -#define IOC_IOCFG6_IOSTR_M 0x00000300 -#define IOC_IOCFG6_IOSTR_S 8 -#define IOC_IOCFG6_IOSTR_MAX 0x00000300 -#define IOC_IOCFG6_IOSTR_MED 0x00000200 -#define IOC_IOCFG6_IOSTR_MIN 0x00000100 -#define IOC_IOCFG6_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG6_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG6_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG6_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG6_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG6_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG6_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG6_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG6_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO6 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG6_PORT_ID_W 6 -#define IOC_IOCFG6_PORT_ID_M 0x0000003F -#define IOC_IOCFG6_PORT_ID_S 0 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG6_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG6_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG6_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG6_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG7 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG7_HYST_EN 0x40000000 -#define IOC_IOCFG7_HYST_EN_BITN 30 -#define IOC_IOCFG7_HYST_EN_M 0x40000000 -#define IOC_IOCFG7_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG7_IE 0x20000000 -#define IOC_IOCFG7_IE_BITN 29 -#define IOC_IOCFG7_IE_M 0x20000000 -#define IOC_IOCFG7_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG7_WU_CFG_W 2 -#define IOC_IOCFG7_WU_CFG_M 0x18000000 -#define IOC_IOCFG7_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG7_IOMODE_W 3 -#define IOC_IOCFG7_IOMODE_M 0x07000000 -#define IOC_IOCFG7_IOMODE_S 24 -#define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG7_IOMODE_INV 0x01000000 -#define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG7_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG7_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG7_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG7_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG7_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG7_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG7_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG7_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG7_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG7_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG7_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG7_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG7_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG7_EDGE_DET_W 2 -#define IOC_IOCFG7_EDGE_DET_M 0x00030000 -#define IOC_IOCFG7_EDGE_DET_S 16 -#define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG7_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG7_PULL_CTL_W 2 -#define IOC_IOCFG7_PULL_CTL_M 0x00006000 -#define IOC_IOCFG7_PULL_CTL_S 13 -#define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG7_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG7_SLEW_RED 0x00001000 -#define IOC_IOCFG7_SLEW_RED_BITN 12 -#define IOC_IOCFG7_SLEW_RED_M 0x00001000 -#define IOC_IOCFG7_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG7_IOCURR_W 2 -#define IOC_IOCFG7_IOCURR_M 0x00000C00 -#define IOC_IOCFG7_IOCURR_S 10 -#define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG7_IOCURR_4MA 0x00000400 -#define IOC_IOCFG7_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG7_IOSTR_W 2 -#define IOC_IOCFG7_IOSTR_M 0x00000300 -#define IOC_IOCFG7_IOSTR_S 8 -#define IOC_IOCFG7_IOSTR_MAX 0x00000300 -#define IOC_IOCFG7_IOSTR_MED 0x00000200 -#define IOC_IOCFG7_IOSTR_MIN 0x00000100 -#define IOC_IOCFG7_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG7_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG7_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG7_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG7_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG7_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG7_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG7_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG7_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO7 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG7_PORT_ID_W 6 -#define IOC_IOCFG7_PORT_ID_M 0x0000003F -#define IOC_IOCFG7_PORT_ID_S 0 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG7_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG7_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG7_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG7_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG8 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG8_HYST_EN 0x40000000 -#define IOC_IOCFG8_HYST_EN_BITN 30 -#define IOC_IOCFG8_HYST_EN_M 0x40000000 -#define IOC_IOCFG8_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG8_IE 0x20000000 -#define IOC_IOCFG8_IE_BITN 29 -#define IOC_IOCFG8_IE_M 0x20000000 -#define IOC_IOCFG8_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG8_WU_CFG_W 2 -#define IOC_IOCFG8_WU_CFG_M 0x18000000 -#define IOC_IOCFG8_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG8_IOMODE_W 3 -#define IOC_IOCFG8_IOMODE_M 0x07000000 -#define IOC_IOCFG8_IOMODE_S 24 -#define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG8_IOMODE_INV 0x01000000 -#define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG8_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG8_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG8_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG8_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG8_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG8_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG8_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG8_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG8_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG8_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG8_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG8_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG8_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG8_EDGE_DET_W 2 -#define IOC_IOCFG8_EDGE_DET_M 0x00030000 -#define IOC_IOCFG8_EDGE_DET_S 16 -#define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG8_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG8_PULL_CTL_W 2 -#define IOC_IOCFG8_PULL_CTL_M 0x00006000 -#define IOC_IOCFG8_PULL_CTL_S 13 -#define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG8_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG8_SLEW_RED 0x00001000 -#define IOC_IOCFG8_SLEW_RED_BITN 12 -#define IOC_IOCFG8_SLEW_RED_M 0x00001000 -#define IOC_IOCFG8_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG8_IOCURR_W 2 -#define IOC_IOCFG8_IOCURR_M 0x00000C00 -#define IOC_IOCFG8_IOCURR_S 10 -#define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG8_IOCURR_4MA 0x00000400 -#define IOC_IOCFG8_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG8_IOSTR_W 2 -#define IOC_IOCFG8_IOSTR_M 0x00000300 -#define IOC_IOCFG8_IOSTR_S 8 -#define IOC_IOCFG8_IOSTR_MAX 0x00000300 -#define IOC_IOCFG8_IOSTR_MED 0x00000200 -#define IOC_IOCFG8_IOSTR_MIN 0x00000100 -#define IOC_IOCFG8_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG8_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG8_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG8_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG8_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG8_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG8_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG8_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG8_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO8 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG8_PORT_ID_W 6 -#define IOC_IOCFG8_PORT_ID_M 0x0000003F -#define IOC_IOCFG8_PORT_ID_S 0 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG8_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG8_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG8_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG8_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG9 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG9_HYST_EN 0x40000000 -#define IOC_IOCFG9_HYST_EN_BITN 30 -#define IOC_IOCFG9_HYST_EN_M 0x40000000 -#define IOC_IOCFG9_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG9_IE 0x20000000 -#define IOC_IOCFG9_IE_BITN 29 -#define IOC_IOCFG9_IE_M 0x20000000 -#define IOC_IOCFG9_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG9_WU_CFG_W 2 -#define IOC_IOCFG9_WU_CFG_M 0x18000000 -#define IOC_IOCFG9_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG9_IOMODE_W 3 -#define IOC_IOCFG9_IOMODE_M 0x07000000 -#define IOC_IOCFG9_IOMODE_S 24 -#define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG9_IOMODE_INV 0x01000000 -#define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG9_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG9_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG9_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG9_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG9_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG9_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG9_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG9_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG9_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG9_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG9_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG9_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG9_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG9_EDGE_DET_W 2 -#define IOC_IOCFG9_EDGE_DET_M 0x00030000 -#define IOC_IOCFG9_EDGE_DET_S 16 -#define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG9_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG9_PULL_CTL_W 2 -#define IOC_IOCFG9_PULL_CTL_M 0x00006000 -#define IOC_IOCFG9_PULL_CTL_S 13 -#define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG9_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG9_SLEW_RED 0x00001000 -#define IOC_IOCFG9_SLEW_RED_BITN 12 -#define IOC_IOCFG9_SLEW_RED_M 0x00001000 -#define IOC_IOCFG9_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG9_IOCURR_W 2 -#define IOC_IOCFG9_IOCURR_M 0x00000C00 -#define IOC_IOCFG9_IOCURR_S 10 -#define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG9_IOCURR_4MA 0x00000400 -#define IOC_IOCFG9_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG9_IOSTR_W 2 -#define IOC_IOCFG9_IOSTR_M 0x00000300 -#define IOC_IOCFG9_IOSTR_S 8 -#define IOC_IOCFG9_IOSTR_MAX 0x00000300 -#define IOC_IOCFG9_IOSTR_MED 0x00000200 -#define IOC_IOCFG9_IOSTR_MIN 0x00000100 -#define IOC_IOCFG9_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG9_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG9_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG9_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG9_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG9_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG9_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG9_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG9_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO9 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG9_PORT_ID_W 6 -#define IOC_IOCFG9_PORT_ID_M 0x0000003F -#define IOC_IOCFG9_PORT_ID_S 0 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG9_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG9_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG9_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG9_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG10 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG10_HYST_EN 0x40000000 -#define IOC_IOCFG10_HYST_EN_BITN 30 -#define IOC_IOCFG10_HYST_EN_M 0x40000000 -#define IOC_IOCFG10_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG10_IE 0x20000000 -#define IOC_IOCFG10_IE_BITN 29 -#define IOC_IOCFG10_IE_M 0x20000000 -#define IOC_IOCFG10_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG10_WU_CFG_W 2 -#define IOC_IOCFG10_WU_CFG_M 0x18000000 -#define IOC_IOCFG10_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG10_IOMODE_W 3 -#define IOC_IOCFG10_IOMODE_M 0x07000000 -#define IOC_IOCFG10_IOMODE_S 24 -#define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG10_IOMODE_INV 0x01000000 -#define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG10_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG10_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG10_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG10_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG10_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG10_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG10_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG10_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG10_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG10_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG10_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG10_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG10_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG10_EDGE_DET_W 2 -#define IOC_IOCFG10_EDGE_DET_M 0x00030000 -#define IOC_IOCFG10_EDGE_DET_S 16 -#define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG10_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG10_PULL_CTL_W 2 -#define IOC_IOCFG10_PULL_CTL_M 0x00006000 -#define IOC_IOCFG10_PULL_CTL_S 13 -#define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG10_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG10_SLEW_RED 0x00001000 -#define IOC_IOCFG10_SLEW_RED_BITN 12 -#define IOC_IOCFG10_SLEW_RED_M 0x00001000 -#define IOC_IOCFG10_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG10_IOCURR_W 2 -#define IOC_IOCFG10_IOCURR_M 0x00000C00 -#define IOC_IOCFG10_IOCURR_S 10 -#define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG10_IOCURR_4MA 0x00000400 -#define IOC_IOCFG10_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG10_IOSTR_W 2 -#define IOC_IOCFG10_IOSTR_M 0x00000300 -#define IOC_IOCFG10_IOSTR_S 8 -#define IOC_IOCFG10_IOSTR_MAX 0x00000300 -#define IOC_IOCFG10_IOSTR_MED 0x00000200 -#define IOC_IOCFG10_IOSTR_MIN 0x00000100 -#define IOC_IOCFG10_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG10_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG10_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG10_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG10_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG10_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG10_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG10_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG10_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO10 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG10_PORT_ID_W 6 -#define IOC_IOCFG10_PORT_ID_M 0x0000003F -#define IOC_IOCFG10_PORT_ID_S 0 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG10_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG10_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG10_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG10_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG11 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG11_HYST_EN 0x40000000 -#define IOC_IOCFG11_HYST_EN_BITN 30 -#define IOC_IOCFG11_HYST_EN_M 0x40000000 -#define IOC_IOCFG11_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG11_IE 0x20000000 -#define IOC_IOCFG11_IE_BITN 29 -#define IOC_IOCFG11_IE_M 0x20000000 -#define IOC_IOCFG11_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG11_WU_CFG_W 2 -#define IOC_IOCFG11_WU_CFG_M 0x18000000 -#define IOC_IOCFG11_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG11_IOMODE_W 3 -#define IOC_IOCFG11_IOMODE_M 0x07000000 -#define IOC_IOCFG11_IOMODE_S 24 -#define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG11_IOMODE_INV 0x01000000 -#define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG11_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG11_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG11_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG11_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG11_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG11_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG11_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG11_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG11_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG11_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG11_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG11_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG11_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG11_EDGE_DET_W 2 -#define IOC_IOCFG11_EDGE_DET_M 0x00030000 -#define IOC_IOCFG11_EDGE_DET_S 16 -#define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG11_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG11_PULL_CTL_W 2 -#define IOC_IOCFG11_PULL_CTL_M 0x00006000 -#define IOC_IOCFG11_PULL_CTL_S 13 -#define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG11_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG11_SLEW_RED 0x00001000 -#define IOC_IOCFG11_SLEW_RED_BITN 12 -#define IOC_IOCFG11_SLEW_RED_M 0x00001000 -#define IOC_IOCFG11_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG11_IOCURR_W 2 -#define IOC_IOCFG11_IOCURR_M 0x00000C00 -#define IOC_IOCFG11_IOCURR_S 10 -#define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG11_IOCURR_4MA 0x00000400 -#define IOC_IOCFG11_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG11_IOSTR_W 2 -#define IOC_IOCFG11_IOSTR_M 0x00000300 -#define IOC_IOCFG11_IOSTR_S 8 -#define IOC_IOCFG11_IOSTR_MAX 0x00000300 -#define IOC_IOCFG11_IOSTR_MED 0x00000200 -#define IOC_IOCFG11_IOSTR_MIN 0x00000100 -#define IOC_IOCFG11_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG11_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG11_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG11_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG11_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG11_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG11_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG11_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG11_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO11 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG11_PORT_ID_W 6 -#define IOC_IOCFG11_PORT_ID_M 0x0000003F -#define IOC_IOCFG11_PORT_ID_S 0 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG11_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG11_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG11_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG11_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG12 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG12_HYST_EN 0x40000000 -#define IOC_IOCFG12_HYST_EN_BITN 30 -#define IOC_IOCFG12_HYST_EN_M 0x40000000 -#define IOC_IOCFG12_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG12_IE 0x20000000 -#define IOC_IOCFG12_IE_BITN 29 -#define IOC_IOCFG12_IE_M 0x20000000 -#define IOC_IOCFG12_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG12_WU_CFG_W 2 -#define IOC_IOCFG12_WU_CFG_M 0x18000000 -#define IOC_IOCFG12_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG12_IOMODE_W 3 -#define IOC_IOCFG12_IOMODE_M 0x07000000 -#define IOC_IOCFG12_IOMODE_S 24 -#define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG12_IOMODE_INV 0x01000000 -#define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG12_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG12_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG12_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG12_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG12_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG12_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG12_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG12_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG12_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG12_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG12_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG12_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG12_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG12_EDGE_DET_W 2 -#define IOC_IOCFG12_EDGE_DET_M 0x00030000 -#define IOC_IOCFG12_EDGE_DET_S 16 -#define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG12_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG12_PULL_CTL_W 2 -#define IOC_IOCFG12_PULL_CTL_M 0x00006000 -#define IOC_IOCFG12_PULL_CTL_S 13 -#define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG12_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG12_SLEW_RED 0x00001000 -#define IOC_IOCFG12_SLEW_RED_BITN 12 -#define IOC_IOCFG12_SLEW_RED_M 0x00001000 -#define IOC_IOCFG12_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG12_IOCURR_W 2 -#define IOC_IOCFG12_IOCURR_M 0x00000C00 -#define IOC_IOCFG12_IOCURR_S 10 -#define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG12_IOCURR_4MA 0x00000400 -#define IOC_IOCFG12_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG12_IOSTR_W 2 -#define IOC_IOCFG12_IOSTR_M 0x00000300 -#define IOC_IOCFG12_IOSTR_S 8 -#define IOC_IOCFG12_IOSTR_MAX 0x00000300 -#define IOC_IOCFG12_IOSTR_MED 0x00000200 -#define IOC_IOCFG12_IOSTR_MIN 0x00000100 -#define IOC_IOCFG12_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG12_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG12_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG12_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG12_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG12_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG12_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG12_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG12_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO12 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG12_PORT_ID_W 6 -#define IOC_IOCFG12_PORT_ID_M 0x0000003F -#define IOC_IOCFG12_PORT_ID_S 0 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG12_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG12_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG12_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG12_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG13 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG13_HYST_EN 0x40000000 -#define IOC_IOCFG13_HYST_EN_BITN 30 -#define IOC_IOCFG13_HYST_EN_M 0x40000000 -#define IOC_IOCFG13_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG13_IE 0x20000000 -#define IOC_IOCFG13_IE_BITN 29 -#define IOC_IOCFG13_IE_M 0x20000000 -#define IOC_IOCFG13_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG13_WU_CFG_W 2 -#define IOC_IOCFG13_WU_CFG_M 0x18000000 -#define IOC_IOCFG13_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG13_IOMODE_W 3 -#define IOC_IOCFG13_IOMODE_M 0x07000000 -#define IOC_IOCFG13_IOMODE_S 24 -#define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG13_IOMODE_INV 0x01000000 -#define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG13_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG13_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG13_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG13_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG13_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG13_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG13_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG13_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG13_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG13_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG13_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG13_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG13_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG13_EDGE_DET_W 2 -#define IOC_IOCFG13_EDGE_DET_M 0x00030000 -#define IOC_IOCFG13_EDGE_DET_S 16 -#define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG13_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG13_PULL_CTL_W 2 -#define IOC_IOCFG13_PULL_CTL_M 0x00006000 -#define IOC_IOCFG13_PULL_CTL_S 13 -#define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG13_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG13_SLEW_RED 0x00001000 -#define IOC_IOCFG13_SLEW_RED_BITN 12 -#define IOC_IOCFG13_SLEW_RED_M 0x00001000 -#define IOC_IOCFG13_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG13_IOCURR_W 2 -#define IOC_IOCFG13_IOCURR_M 0x00000C00 -#define IOC_IOCFG13_IOCURR_S 10 -#define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG13_IOCURR_4MA 0x00000400 -#define IOC_IOCFG13_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG13_IOSTR_W 2 -#define IOC_IOCFG13_IOSTR_M 0x00000300 -#define IOC_IOCFG13_IOSTR_S 8 -#define IOC_IOCFG13_IOSTR_MAX 0x00000300 -#define IOC_IOCFG13_IOSTR_MED 0x00000200 -#define IOC_IOCFG13_IOSTR_MIN 0x00000100 -#define IOC_IOCFG13_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG13_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG13_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG13_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG13_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG13_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG13_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG13_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG13_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO13 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG13_PORT_ID_W 6 -#define IOC_IOCFG13_PORT_ID_M 0x0000003F -#define IOC_IOCFG13_PORT_ID_S 0 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG13_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG13_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG13_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG13_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG14 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG14_HYST_EN 0x40000000 -#define IOC_IOCFG14_HYST_EN_BITN 30 -#define IOC_IOCFG14_HYST_EN_M 0x40000000 -#define IOC_IOCFG14_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG14_IE 0x20000000 -#define IOC_IOCFG14_IE_BITN 29 -#define IOC_IOCFG14_IE_M 0x20000000 -#define IOC_IOCFG14_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG14_WU_CFG_W 2 -#define IOC_IOCFG14_WU_CFG_M 0x18000000 -#define IOC_IOCFG14_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG14_IOMODE_W 3 -#define IOC_IOCFG14_IOMODE_M 0x07000000 -#define IOC_IOCFG14_IOMODE_S 24 -#define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG14_IOMODE_INV 0x01000000 -#define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG14_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG14_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG14_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG14_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG14_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG14_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG14_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG14_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG14_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG14_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG14_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG14_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG14_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG14_EDGE_DET_W 2 -#define IOC_IOCFG14_EDGE_DET_M 0x00030000 -#define IOC_IOCFG14_EDGE_DET_S 16 -#define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG14_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG14_PULL_CTL_W 2 -#define IOC_IOCFG14_PULL_CTL_M 0x00006000 -#define IOC_IOCFG14_PULL_CTL_S 13 -#define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG14_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG14_SLEW_RED 0x00001000 -#define IOC_IOCFG14_SLEW_RED_BITN 12 -#define IOC_IOCFG14_SLEW_RED_M 0x00001000 -#define IOC_IOCFG14_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG14_IOCURR_W 2 -#define IOC_IOCFG14_IOCURR_M 0x00000C00 -#define IOC_IOCFG14_IOCURR_S 10 -#define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG14_IOCURR_4MA 0x00000400 -#define IOC_IOCFG14_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG14_IOSTR_W 2 -#define IOC_IOCFG14_IOSTR_M 0x00000300 -#define IOC_IOCFG14_IOSTR_S 8 -#define IOC_IOCFG14_IOSTR_MAX 0x00000300 -#define IOC_IOCFG14_IOSTR_MED 0x00000200 -#define IOC_IOCFG14_IOSTR_MIN 0x00000100 -#define IOC_IOCFG14_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG14_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG14_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG14_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG14_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG14_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG14_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG14_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG14_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO14 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG14_PORT_ID_W 6 -#define IOC_IOCFG14_PORT_ID_M 0x0000003F -#define IOC_IOCFG14_PORT_ID_S 0 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG14_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG14_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG14_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG14_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG15 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG15_HYST_EN 0x40000000 -#define IOC_IOCFG15_HYST_EN_BITN 30 -#define IOC_IOCFG15_HYST_EN_M 0x40000000 -#define IOC_IOCFG15_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG15_IE 0x20000000 -#define IOC_IOCFG15_IE_BITN 29 -#define IOC_IOCFG15_IE_M 0x20000000 -#define IOC_IOCFG15_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG15_WU_CFG_W 2 -#define IOC_IOCFG15_WU_CFG_M 0x18000000 -#define IOC_IOCFG15_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG15_IOMODE_W 3 -#define IOC_IOCFG15_IOMODE_M 0x07000000 -#define IOC_IOCFG15_IOMODE_S 24 -#define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG15_IOMODE_INV 0x01000000 -#define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG15_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG15_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG15_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG15_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG15_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG15_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG15_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG15_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG15_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG15_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG15_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG15_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG15_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG15_EDGE_DET_W 2 -#define IOC_IOCFG15_EDGE_DET_M 0x00030000 -#define IOC_IOCFG15_EDGE_DET_S 16 -#define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG15_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG15_PULL_CTL_W 2 -#define IOC_IOCFG15_PULL_CTL_M 0x00006000 -#define IOC_IOCFG15_PULL_CTL_S 13 -#define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG15_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG15_SLEW_RED 0x00001000 -#define IOC_IOCFG15_SLEW_RED_BITN 12 -#define IOC_IOCFG15_SLEW_RED_M 0x00001000 -#define IOC_IOCFG15_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG15_IOCURR_W 2 -#define IOC_IOCFG15_IOCURR_M 0x00000C00 -#define IOC_IOCFG15_IOCURR_S 10 -#define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG15_IOCURR_4MA 0x00000400 -#define IOC_IOCFG15_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG15_IOSTR_W 2 -#define IOC_IOCFG15_IOSTR_M 0x00000300 -#define IOC_IOCFG15_IOSTR_S 8 -#define IOC_IOCFG15_IOSTR_MAX 0x00000300 -#define IOC_IOCFG15_IOSTR_MED 0x00000200 -#define IOC_IOCFG15_IOSTR_MIN 0x00000100 -#define IOC_IOCFG15_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG15_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG15_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG15_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG15_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG15_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG15_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG15_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG15_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO15 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG15_PORT_ID_W 6 -#define IOC_IOCFG15_PORT_ID_M 0x0000003F -#define IOC_IOCFG15_PORT_ID_S 0 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG15_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG15_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG15_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG15_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG16 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG16_HYST_EN 0x40000000 -#define IOC_IOCFG16_HYST_EN_BITN 30 -#define IOC_IOCFG16_HYST_EN_M 0x40000000 -#define IOC_IOCFG16_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG16_IE 0x20000000 -#define IOC_IOCFG16_IE_BITN 29 -#define IOC_IOCFG16_IE_M 0x20000000 -#define IOC_IOCFG16_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG16_WU_CFG_W 2 -#define IOC_IOCFG16_WU_CFG_M 0x18000000 -#define IOC_IOCFG16_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG16_IOMODE_W 3 -#define IOC_IOCFG16_IOMODE_M 0x07000000 -#define IOC_IOCFG16_IOMODE_S 24 -#define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG16_IOMODE_INV 0x01000000 -#define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG16_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG16_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG16_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG16_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG16_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG16_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG16_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG16_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG16_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG16_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG16_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG16_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG16_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG16_EDGE_DET_W 2 -#define IOC_IOCFG16_EDGE_DET_M 0x00030000 -#define IOC_IOCFG16_EDGE_DET_S 16 -#define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG16_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG16_PULL_CTL_W 2 -#define IOC_IOCFG16_PULL_CTL_M 0x00006000 -#define IOC_IOCFG16_PULL_CTL_S 13 -#define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG16_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG16_SLEW_RED 0x00001000 -#define IOC_IOCFG16_SLEW_RED_BITN 12 -#define IOC_IOCFG16_SLEW_RED_M 0x00001000 -#define IOC_IOCFG16_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG16_IOCURR_W 2 -#define IOC_IOCFG16_IOCURR_M 0x00000C00 -#define IOC_IOCFG16_IOCURR_S 10 -#define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG16_IOCURR_4MA 0x00000400 -#define IOC_IOCFG16_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG16_IOSTR_W 2 -#define IOC_IOCFG16_IOSTR_M 0x00000300 -#define IOC_IOCFG16_IOSTR_S 8 -#define IOC_IOCFG16_IOSTR_MAX 0x00000300 -#define IOC_IOCFG16_IOSTR_MED 0x00000200 -#define IOC_IOCFG16_IOSTR_MIN 0x00000100 -#define IOC_IOCFG16_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG16_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG16_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG16_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG16_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG16_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG16_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG16_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG16_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO16 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG16_PORT_ID_W 6 -#define IOC_IOCFG16_PORT_ID_M 0x0000003F -#define IOC_IOCFG16_PORT_ID_S 0 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG16_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG16_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG16_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG16_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG17 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG17_HYST_EN 0x40000000 -#define IOC_IOCFG17_HYST_EN_BITN 30 -#define IOC_IOCFG17_HYST_EN_M 0x40000000 -#define IOC_IOCFG17_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG17_IE 0x20000000 -#define IOC_IOCFG17_IE_BITN 29 -#define IOC_IOCFG17_IE_M 0x20000000 -#define IOC_IOCFG17_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG17_WU_CFG_W 2 -#define IOC_IOCFG17_WU_CFG_M 0x18000000 -#define IOC_IOCFG17_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG17_IOMODE_W 3 -#define IOC_IOCFG17_IOMODE_M 0x07000000 -#define IOC_IOCFG17_IOMODE_S 24 -#define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG17_IOMODE_INV 0x01000000 -#define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG17_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG17_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG17_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG17_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG17_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG17_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG17_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG17_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG17_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG17_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG17_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG17_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG17_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG17_EDGE_DET_W 2 -#define IOC_IOCFG17_EDGE_DET_M 0x00030000 -#define IOC_IOCFG17_EDGE_DET_S 16 -#define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG17_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG17_PULL_CTL_W 2 -#define IOC_IOCFG17_PULL_CTL_M 0x00006000 -#define IOC_IOCFG17_PULL_CTL_S 13 -#define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG17_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG17_SLEW_RED 0x00001000 -#define IOC_IOCFG17_SLEW_RED_BITN 12 -#define IOC_IOCFG17_SLEW_RED_M 0x00001000 -#define IOC_IOCFG17_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG17_IOCURR_W 2 -#define IOC_IOCFG17_IOCURR_M 0x00000C00 -#define IOC_IOCFG17_IOCURR_S 10 -#define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG17_IOCURR_4MA 0x00000400 -#define IOC_IOCFG17_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG17_IOSTR_W 2 -#define IOC_IOCFG17_IOSTR_M 0x00000300 -#define IOC_IOCFG17_IOSTR_S 8 -#define IOC_IOCFG17_IOSTR_MAX 0x00000300 -#define IOC_IOCFG17_IOSTR_MED 0x00000200 -#define IOC_IOCFG17_IOSTR_MIN 0x00000100 -#define IOC_IOCFG17_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG17_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG17_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG17_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG17_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG17_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG17_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG17_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG17_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO17 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG17_PORT_ID_W 6 -#define IOC_IOCFG17_PORT_ID_M 0x0000003F -#define IOC_IOCFG17_PORT_ID_S 0 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG17_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG17_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG17_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG17_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG18 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG18_HYST_EN 0x40000000 -#define IOC_IOCFG18_HYST_EN_BITN 30 -#define IOC_IOCFG18_HYST_EN_M 0x40000000 -#define IOC_IOCFG18_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG18_IE 0x20000000 -#define IOC_IOCFG18_IE_BITN 29 -#define IOC_IOCFG18_IE_M 0x20000000 -#define IOC_IOCFG18_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG18_WU_CFG_W 2 -#define IOC_IOCFG18_WU_CFG_M 0x18000000 -#define IOC_IOCFG18_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG18_IOMODE_W 3 -#define IOC_IOCFG18_IOMODE_M 0x07000000 -#define IOC_IOCFG18_IOMODE_S 24 -#define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG18_IOMODE_INV 0x01000000 -#define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG18_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG18_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG18_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG18_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG18_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG18_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG18_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG18_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG18_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG18_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG18_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG18_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG18_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG18_EDGE_DET_W 2 -#define IOC_IOCFG18_EDGE_DET_M 0x00030000 -#define IOC_IOCFG18_EDGE_DET_S 16 -#define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG18_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG18_PULL_CTL_W 2 -#define IOC_IOCFG18_PULL_CTL_M 0x00006000 -#define IOC_IOCFG18_PULL_CTL_S 13 -#define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG18_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG18_SLEW_RED 0x00001000 -#define IOC_IOCFG18_SLEW_RED_BITN 12 -#define IOC_IOCFG18_SLEW_RED_M 0x00001000 -#define IOC_IOCFG18_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG18_IOCURR_W 2 -#define IOC_IOCFG18_IOCURR_M 0x00000C00 -#define IOC_IOCFG18_IOCURR_S 10 -#define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG18_IOCURR_4MA 0x00000400 -#define IOC_IOCFG18_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG18_IOSTR_W 2 -#define IOC_IOCFG18_IOSTR_M 0x00000300 -#define IOC_IOCFG18_IOSTR_S 8 -#define IOC_IOCFG18_IOSTR_MAX 0x00000300 -#define IOC_IOCFG18_IOSTR_MED 0x00000200 -#define IOC_IOCFG18_IOSTR_MIN 0x00000100 -#define IOC_IOCFG18_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG18_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG18_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG18_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG18_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG18_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG18_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG18_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG18_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO18 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG18_PORT_ID_W 6 -#define IOC_IOCFG18_PORT_ID_M 0x0000003F -#define IOC_IOCFG18_PORT_ID_S 0 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG18_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG18_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG18_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG18_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG19 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG19_HYST_EN 0x40000000 -#define IOC_IOCFG19_HYST_EN_BITN 30 -#define IOC_IOCFG19_HYST_EN_M 0x40000000 -#define IOC_IOCFG19_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG19_IE 0x20000000 -#define IOC_IOCFG19_IE_BITN 29 -#define IOC_IOCFG19_IE_M 0x20000000 -#define IOC_IOCFG19_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG19_WU_CFG_W 2 -#define IOC_IOCFG19_WU_CFG_M 0x18000000 -#define IOC_IOCFG19_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG19_IOMODE_W 3 -#define IOC_IOCFG19_IOMODE_M 0x07000000 -#define IOC_IOCFG19_IOMODE_S 24 -#define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG19_IOMODE_INV 0x01000000 -#define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG19_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG19_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG19_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG19_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG19_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG19_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG19_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG19_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG19_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG19_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG19_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG19_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG19_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG19_EDGE_DET_W 2 -#define IOC_IOCFG19_EDGE_DET_M 0x00030000 -#define IOC_IOCFG19_EDGE_DET_S 16 -#define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG19_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG19_PULL_CTL_W 2 -#define IOC_IOCFG19_PULL_CTL_M 0x00006000 -#define IOC_IOCFG19_PULL_CTL_S 13 -#define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG19_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG19_SLEW_RED 0x00001000 -#define IOC_IOCFG19_SLEW_RED_BITN 12 -#define IOC_IOCFG19_SLEW_RED_M 0x00001000 -#define IOC_IOCFG19_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG19_IOCURR_W 2 -#define IOC_IOCFG19_IOCURR_M 0x00000C00 -#define IOC_IOCFG19_IOCURR_S 10 -#define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG19_IOCURR_4MA 0x00000400 -#define IOC_IOCFG19_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG19_IOSTR_W 2 -#define IOC_IOCFG19_IOSTR_M 0x00000300 -#define IOC_IOCFG19_IOSTR_S 8 -#define IOC_IOCFG19_IOSTR_MAX 0x00000300 -#define IOC_IOCFG19_IOSTR_MED 0x00000200 -#define IOC_IOCFG19_IOSTR_MIN 0x00000100 -#define IOC_IOCFG19_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG19_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG19_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG19_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG19_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG19_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG19_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG19_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG19_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO19 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG19_PORT_ID_W 6 -#define IOC_IOCFG19_PORT_ID_M 0x0000003F -#define IOC_IOCFG19_PORT_ID_S 0 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG19_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG19_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG19_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG19_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG20 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG20_HYST_EN 0x40000000 -#define IOC_IOCFG20_HYST_EN_BITN 30 -#define IOC_IOCFG20_HYST_EN_M 0x40000000 -#define IOC_IOCFG20_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG20_IE 0x20000000 -#define IOC_IOCFG20_IE_BITN 29 -#define IOC_IOCFG20_IE_M 0x20000000 -#define IOC_IOCFG20_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG20_WU_CFG_W 2 -#define IOC_IOCFG20_WU_CFG_M 0x18000000 -#define IOC_IOCFG20_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG20_IOMODE_W 3 -#define IOC_IOCFG20_IOMODE_M 0x07000000 -#define IOC_IOCFG20_IOMODE_S 24 -#define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG20_IOMODE_INV 0x01000000 -#define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG20_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG20_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG20_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG20_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG20_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG20_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG20_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG20_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG20_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG20_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG20_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG20_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG20_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG20_EDGE_DET_W 2 -#define IOC_IOCFG20_EDGE_DET_M 0x00030000 -#define IOC_IOCFG20_EDGE_DET_S 16 -#define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG20_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG20_PULL_CTL_W 2 -#define IOC_IOCFG20_PULL_CTL_M 0x00006000 -#define IOC_IOCFG20_PULL_CTL_S 13 -#define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG20_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG20_SLEW_RED 0x00001000 -#define IOC_IOCFG20_SLEW_RED_BITN 12 -#define IOC_IOCFG20_SLEW_RED_M 0x00001000 -#define IOC_IOCFG20_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG20_IOCURR_W 2 -#define IOC_IOCFG20_IOCURR_M 0x00000C00 -#define IOC_IOCFG20_IOCURR_S 10 -#define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG20_IOCURR_4MA 0x00000400 -#define IOC_IOCFG20_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG20_IOSTR_W 2 -#define IOC_IOCFG20_IOSTR_M 0x00000300 -#define IOC_IOCFG20_IOSTR_S 8 -#define IOC_IOCFG20_IOSTR_MAX 0x00000300 -#define IOC_IOCFG20_IOSTR_MED 0x00000200 -#define IOC_IOCFG20_IOSTR_MIN 0x00000100 -#define IOC_IOCFG20_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG20_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG20_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG20_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG20_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG20_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG20_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG20_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG20_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO20 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG20_PORT_ID_W 6 -#define IOC_IOCFG20_PORT_ID_M 0x0000003F -#define IOC_IOCFG20_PORT_ID_S 0 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG20_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG20_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG20_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG20_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG21 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG21_HYST_EN 0x40000000 -#define IOC_IOCFG21_HYST_EN_BITN 30 -#define IOC_IOCFG21_HYST_EN_M 0x40000000 -#define IOC_IOCFG21_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG21_IE 0x20000000 -#define IOC_IOCFG21_IE_BITN 29 -#define IOC_IOCFG21_IE_M 0x20000000 -#define IOC_IOCFG21_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG21_WU_CFG_W 2 -#define IOC_IOCFG21_WU_CFG_M 0x18000000 -#define IOC_IOCFG21_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG21_IOMODE_W 3 -#define IOC_IOCFG21_IOMODE_M 0x07000000 -#define IOC_IOCFG21_IOMODE_S 24 -#define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG21_IOMODE_INV 0x01000000 -#define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG21_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG21_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG21_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG21_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG21_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG21_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG21_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG21_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG21_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG21_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG21_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG21_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG21_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG21_EDGE_DET_W 2 -#define IOC_IOCFG21_EDGE_DET_M 0x00030000 -#define IOC_IOCFG21_EDGE_DET_S 16 -#define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG21_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG21_PULL_CTL_W 2 -#define IOC_IOCFG21_PULL_CTL_M 0x00006000 -#define IOC_IOCFG21_PULL_CTL_S 13 -#define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG21_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG21_SLEW_RED 0x00001000 -#define IOC_IOCFG21_SLEW_RED_BITN 12 -#define IOC_IOCFG21_SLEW_RED_M 0x00001000 -#define IOC_IOCFG21_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG21_IOCURR_W 2 -#define IOC_IOCFG21_IOCURR_M 0x00000C00 -#define IOC_IOCFG21_IOCURR_S 10 -#define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG21_IOCURR_4MA 0x00000400 -#define IOC_IOCFG21_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG21_IOSTR_W 2 -#define IOC_IOCFG21_IOSTR_M 0x00000300 -#define IOC_IOCFG21_IOSTR_S 8 -#define IOC_IOCFG21_IOSTR_MAX 0x00000300 -#define IOC_IOCFG21_IOSTR_MED 0x00000200 -#define IOC_IOCFG21_IOSTR_MIN 0x00000100 -#define IOC_IOCFG21_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG21_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG21_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG21_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG21_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG21_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG21_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG21_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG21_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO21 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG21_PORT_ID_W 6 -#define IOC_IOCFG21_PORT_ID_M 0x0000003F -#define IOC_IOCFG21_PORT_ID_S 0 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG21_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG21_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG21_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG21_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG22 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG22_HYST_EN 0x40000000 -#define IOC_IOCFG22_HYST_EN_BITN 30 -#define IOC_IOCFG22_HYST_EN_M 0x40000000 -#define IOC_IOCFG22_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG22_IE 0x20000000 -#define IOC_IOCFG22_IE_BITN 29 -#define IOC_IOCFG22_IE_M 0x20000000 -#define IOC_IOCFG22_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG22_WU_CFG_W 2 -#define IOC_IOCFG22_WU_CFG_M 0x18000000 -#define IOC_IOCFG22_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG22_IOMODE_W 3 -#define IOC_IOCFG22_IOMODE_M 0x07000000 -#define IOC_IOCFG22_IOMODE_S 24 -#define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG22_IOMODE_INV 0x01000000 -#define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG22_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG22_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG22_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG22_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG22_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG22_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG22_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG22_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG22_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG22_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG22_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG22_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG22_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG22_EDGE_DET_W 2 -#define IOC_IOCFG22_EDGE_DET_M 0x00030000 -#define IOC_IOCFG22_EDGE_DET_S 16 -#define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG22_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG22_PULL_CTL_W 2 -#define IOC_IOCFG22_PULL_CTL_M 0x00006000 -#define IOC_IOCFG22_PULL_CTL_S 13 -#define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG22_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG22_SLEW_RED 0x00001000 -#define IOC_IOCFG22_SLEW_RED_BITN 12 -#define IOC_IOCFG22_SLEW_RED_M 0x00001000 -#define IOC_IOCFG22_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG22_IOCURR_W 2 -#define IOC_IOCFG22_IOCURR_M 0x00000C00 -#define IOC_IOCFG22_IOCURR_S 10 -#define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG22_IOCURR_4MA 0x00000400 -#define IOC_IOCFG22_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG22_IOSTR_W 2 -#define IOC_IOCFG22_IOSTR_M 0x00000300 -#define IOC_IOCFG22_IOSTR_S 8 -#define IOC_IOCFG22_IOSTR_MAX 0x00000300 -#define IOC_IOCFG22_IOSTR_MED 0x00000200 -#define IOC_IOCFG22_IOSTR_MIN 0x00000100 -#define IOC_IOCFG22_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG22_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG22_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG22_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG22_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG22_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG22_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG22_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG22_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO22 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG22_PORT_ID_W 6 -#define IOC_IOCFG22_PORT_ID_M 0x0000003F -#define IOC_IOCFG22_PORT_ID_S 0 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG22_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG22_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG22_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG22_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG23 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG23_HYST_EN 0x40000000 -#define IOC_IOCFG23_HYST_EN_BITN 30 -#define IOC_IOCFG23_HYST_EN_M 0x40000000 -#define IOC_IOCFG23_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG23_IE 0x20000000 -#define IOC_IOCFG23_IE_BITN 29 -#define IOC_IOCFG23_IE_M 0x20000000 -#define IOC_IOCFG23_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG23_WU_CFG_W 2 -#define IOC_IOCFG23_WU_CFG_M 0x18000000 -#define IOC_IOCFG23_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG23_IOMODE_W 3 -#define IOC_IOCFG23_IOMODE_M 0x07000000 -#define IOC_IOCFG23_IOMODE_S 24 -#define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG23_IOMODE_INV 0x01000000 -#define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG23_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG23_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG23_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG23_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG23_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG23_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG23_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG23_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG23_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG23_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG23_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG23_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG23_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG23_EDGE_DET_W 2 -#define IOC_IOCFG23_EDGE_DET_M 0x00030000 -#define IOC_IOCFG23_EDGE_DET_S 16 -#define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG23_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG23_PULL_CTL_W 2 -#define IOC_IOCFG23_PULL_CTL_M 0x00006000 -#define IOC_IOCFG23_PULL_CTL_S 13 -#define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG23_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG23_SLEW_RED 0x00001000 -#define IOC_IOCFG23_SLEW_RED_BITN 12 -#define IOC_IOCFG23_SLEW_RED_M 0x00001000 -#define IOC_IOCFG23_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG23_IOCURR_W 2 -#define IOC_IOCFG23_IOCURR_M 0x00000C00 -#define IOC_IOCFG23_IOCURR_S 10 -#define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG23_IOCURR_4MA 0x00000400 -#define IOC_IOCFG23_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG23_IOSTR_W 2 -#define IOC_IOCFG23_IOSTR_M 0x00000300 -#define IOC_IOCFG23_IOSTR_S 8 -#define IOC_IOCFG23_IOSTR_MAX 0x00000300 -#define IOC_IOCFG23_IOSTR_MED 0x00000200 -#define IOC_IOCFG23_IOSTR_MIN 0x00000100 -#define IOC_IOCFG23_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG23_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG23_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG23_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG23_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG23_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG23_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG23_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG23_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO23 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG23_PORT_ID_W 6 -#define IOC_IOCFG23_PORT_ID_M 0x0000003F -#define IOC_IOCFG23_PORT_ID_S 0 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG23_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG23_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG23_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG23_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG24 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG24_HYST_EN 0x40000000 -#define IOC_IOCFG24_HYST_EN_BITN 30 -#define IOC_IOCFG24_HYST_EN_M 0x40000000 -#define IOC_IOCFG24_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG24_IE 0x20000000 -#define IOC_IOCFG24_IE_BITN 29 -#define IOC_IOCFG24_IE_M 0x20000000 -#define IOC_IOCFG24_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG24_WU_CFG_W 2 -#define IOC_IOCFG24_WU_CFG_M 0x18000000 -#define IOC_IOCFG24_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG24_IOMODE_W 3 -#define IOC_IOCFG24_IOMODE_M 0x07000000 -#define IOC_IOCFG24_IOMODE_S 24 -#define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG24_IOMODE_INV 0x01000000 -#define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG24_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG24_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG24_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG24_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG24_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG24_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG24_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG24_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG24_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG24_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG24_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG24_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG24_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG24_EDGE_DET_W 2 -#define IOC_IOCFG24_EDGE_DET_M 0x00030000 -#define IOC_IOCFG24_EDGE_DET_S 16 -#define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG24_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG24_PULL_CTL_W 2 -#define IOC_IOCFG24_PULL_CTL_M 0x00006000 -#define IOC_IOCFG24_PULL_CTL_S 13 -#define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG24_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG24_SLEW_RED 0x00001000 -#define IOC_IOCFG24_SLEW_RED_BITN 12 -#define IOC_IOCFG24_SLEW_RED_M 0x00001000 -#define IOC_IOCFG24_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG24_IOCURR_W 2 -#define IOC_IOCFG24_IOCURR_M 0x00000C00 -#define IOC_IOCFG24_IOCURR_S 10 -#define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG24_IOCURR_4MA 0x00000400 -#define IOC_IOCFG24_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG24_IOSTR_W 2 -#define IOC_IOCFG24_IOSTR_M 0x00000300 -#define IOC_IOCFG24_IOSTR_S 8 -#define IOC_IOCFG24_IOSTR_MAX 0x00000300 -#define IOC_IOCFG24_IOSTR_MED 0x00000200 -#define IOC_IOCFG24_IOSTR_MIN 0x00000100 -#define IOC_IOCFG24_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG24_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG24_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG24_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG24_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG24_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG24_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG24_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG24_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO24 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG24_PORT_ID_W 6 -#define IOC_IOCFG24_PORT_ID_M 0x0000003F -#define IOC_IOCFG24_PORT_ID_S 0 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG24_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG24_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG24_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG24_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG25 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG25_HYST_EN 0x40000000 -#define IOC_IOCFG25_HYST_EN_BITN 30 -#define IOC_IOCFG25_HYST_EN_M 0x40000000 -#define IOC_IOCFG25_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG25_IE 0x20000000 -#define IOC_IOCFG25_IE_BITN 29 -#define IOC_IOCFG25_IE_M 0x20000000 -#define IOC_IOCFG25_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG25_WU_CFG_W 2 -#define IOC_IOCFG25_WU_CFG_M 0x18000000 -#define IOC_IOCFG25_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG25_IOMODE_W 3 -#define IOC_IOCFG25_IOMODE_M 0x07000000 -#define IOC_IOCFG25_IOMODE_S 24 -#define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG25_IOMODE_INV 0x01000000 -#define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG25_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG25_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG25_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG25_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG25_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG25_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG25_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG25_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG25_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG25_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG25_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG25_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG25_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG25_EDGE_DET_W 2 -#define IOC_IOCFG25_EDGE_DET_M 0x00030000 -#define IOC_IOCFG25_EDGE_DET_S 16 -#define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG25_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG25_PULL_CTL_W 2 -#define IOC_IOCFG25_PULL_CTL_M 0x00006000 -#define IOC_IOCFG25_PULL_CTL_S 13 -#define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG25_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG25_SLEW_RED 0x00001000 -#define IOC_IOCFG25_SLEW_RED_BITN 12 -#define IOC_IOCFG25_SLEW_RED_M 0x00001000 -#define IOC_IOCFG25_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG25_IOCURR_W 2 -#define IOC_IOCFG25_IOCURR_M 0x00000C00 -#define IOC_IOCFG25_IOCURR_S 10 -#define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG25_IOCURR_4MA 0x00000400 -#define IOC_IOCFG25_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG25_IOSTR_W 2 -#define IOC_IOCFG25_IOSTR_M 0x00000300 -#define IOC_IOCFG25_IOSTR_S 8 -#define IOC_IOCFG25_IOSTR_MAX 0x00000300 -#define IOC_IOCFG25_IOSTR_MED 0x00000200 -#define IOC_IOCFG25_IOSTR_MIN 0x00000100 -#define IOC_IOCFG25_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG25_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG25_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG25_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG25_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG25_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG25_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG25_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG25_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO25 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG25_PORT_ID_W 6 -#define IOC_IOCFG25_PORT_ID_M 0x0000003F -#define IOC_IOCFG25_PORT_ID_S 0 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG25_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG25_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG25_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG25_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG26 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG26_HYST_EN 0x40000000 -#define IOC_IOCFG26_HYST_EN_BITN 30 -#define IOC_IOCFG26_HYST_EN_M 0x40000000 -#define IOC_IOCFG26_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG26_IE 0x20000000 -#define IOC_IOCFG26_IE_BITN 29 -#define IOC_IOCFG26_IE_M 0x20000000 -#define IOC_IOCFG26_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG26_WU_CFG_W 2 -#define IOC_IOCFG26_WU_CFG_M 0x18000000 -#define IOC_IOCFG26_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG26_IOMODE_W 3 -#define IOC_IOCFG26_IOMODE_M 0x07000000 -#define IOC_IOCFG26_IOMODE_S 24 -#define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG26_IOMODE_INV 0x01000000 -#define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG26_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG26_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG26_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG26_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG26_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG26_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG26_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG26_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG26_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG26_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG26_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG26_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG26_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG26_EDGE_DET_W 2 -#define IOC_IOCFG26_EDGE_DET_M 0x00030000 -#define IOC_IOCFG26_EDGE_DET_S 16 -#define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG26_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG26_PULL_CTL_W 2 -#define IOC_IOCFG26_PULL_CTL_M 0x00006000 -#define IOC_IOCFG26_PULL_CTL_S 13 -#define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG26_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG26_SLEW_RED 0x00001000 -#define IOC_IOCFG26_SLEW_RED_BITN 12 -#define IOC_IOCFG26_SLEW_RED_M 0x00001000 -#define IOC_IOCFG26_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG26_IOCURR_W 2 -#define IOC_IOCFG26_IOCURR_M 0x00000C00 -#define IOC_IOCFG26_IOCURR_S 10 -#define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG26_IOCURR_4MA 0x00000400 -#define IOC_IOCFG26_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG26_IOSTR_W 2 -#define IOC_IOCFG26_IOSTR_M 0x00000300 -#define IOC_IOCFG26_IOSTR_S 8 -#define IOC_IOCFG26_IOSTR_MAX 0x00000300 -#define IOC_IOCFG26_IOSTR_MED 0x00000200 -#define IOC_IOCFG26_IOSTR_MIN 0x00000100 -#define IOC_IOCFG26_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG26_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG26_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG26_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG26_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG26_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG26_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG26_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG26_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO26 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG26_PORT_ID_W 6 -#define IOC_IOCFG26_PORT_ID_M 0x0000003F -#define IOC_IOCFG26_PORT_ID_S 0 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG26_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG26_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG26_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG26_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG27 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG27_HYST_EN 0x40000000 -#define IOC_IOCFG27_HYST_EN_BITN 30 -#define IOC_IOCFG27_HYST_EN_M 0x40000000 -#define IOC_IOCFG27_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG27_IE 0x20000000 -#define IOC_IOCFG27_IE_BITN 29 -#define IOC_IOCFG27_IE_M 0x20000000 -#define IOC_IOCFG27_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG27_WU_CFG_W 2 -#define IOC_IOCFG27_WU_CFG_M 0x18000000 -#define IOC_IOCFG27_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG27_IOMODE_W 3 -#define IOC_IOCFG27_IOMODE_M 0x07000000 -#define IOC_IOCFG27_IOMODE_S 24 -#define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG27_IOMODE_INV 0x01000000 -#define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG27_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG27_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG27_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG27_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG27_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG27_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG27_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG27_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG27_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG27_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG27_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG27_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG27_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG27_EDGE_DET_W 2 -#define IOC_IOCFG27_EDGE_DET_M 0x00030000 -#define IOC_IOCFG27_EDGE_DET_S 16 -#define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG27_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG27_PULL_CTL_W 2 -#define IOC_IOCFG27_PULL_CTL_M 0x00006000 -#define IOC_IOCFG27_PULL_CTL_S 13 -#define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG27_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG27_SLEW_RED 0x00001000 -#define IOC_IOCFG27_SLEW_RED_BITN 12 -#define IOC_IOCFG27_SLEW_RED_M 0x00001000 -#define IOC_IOCFG27_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG27_IOCURR_W 2 -#define IOC_IOCFG27_IOCURR_M 0x00000C00 -#define IOC_IOCFG27_IOCURR_S 10 -#define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG27_IOCURR_4MA 0x00000400 -#define IOC_IOCFG27_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG27_IOSTR_W 2 -#define IOC_IOCFG27_IOSTR_M 0x00000300 -#define IOC_IOCFG27_IOSTR_S 8 -#define IOC_IOCFG27_IOSTR_MAX 0x00000300 -#define IOC_IOCFG27_IOSTR_MED 0x00000200 -#define IOC_IOCFG27_IOSTR_MIN 0x00000100 -#define IOC_IOCFG27_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG27_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG27_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG27_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG27_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG27_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG27_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG27_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG27_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO27 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG27_PORT_ID_W 6 -#define IOC_IOCFG27_PORT_ID_M 0x0000003F -#define IOC_IOCFG27_PORT_ID_S 0 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG27_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG27_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG27_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG27_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG28 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG28_HYST_EN 0x40000000 -#define IOC_IOCFG28_HYST_EN_BITN 30 -#define IOC_IOCFG28_HYST_EN_M 0x40000000 -#define IOC_IOCFG28_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG28_IE 0x20000000 -#define IOC_IOCFG28_IE_BITN 29 -#define IOC_IOCFG28_IE_M 0x20000000 -#define IOC_IOCFG28_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG28_WU_CFG_W 2 -#define IOC_IOCFG28_WU_CFG_M 0x18000000 -#define IOC_IOCFG28_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG28_IOMODE_W 3 -#define IOC_IOCFG28_IOMODE_M 0x07000000 -#define IOC_IOCFG28_IOMODE_S 24 -#define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG28_IOMODE_INV 0x01000000 -#define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG28_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG28_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG28_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG28_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG28_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG28_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG28_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG28_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG28_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG28_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG28_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG28_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG28_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG28_EDGE_DET_W 2 -#define IOC_IOCFG28_EDGE_DET_M 0x00030000 -#define IOC_IOCFG28_EDGE_DET_S 16 -#define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG28_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG28_PULL_CTL_W 2 -#define IOC_IOCFG28_PULL_CTL_M 0x00006000 -#define IOC_IOCFG28_PULL_CTL_S 13 -#define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG28_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG28_SLEW_RED 0x00001000 -#define IOC_IOCFG28_SLEW_RED_BITN 12 -#define IOC_IOCFG28_SLEW_RED_M 0x00001000 -#define IOC_IOCFG28_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG28_IOCURR_W 2 -#define IOC_IOCFG28_IOCURR_M 0x00000C00 -#define IOC_IOCFG28_IOCURR_S 10 -#define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG28_IOCURR_4MA 0x00000400 -#define IOC_IOCFG28_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG28_IOSTR_W 2 -#define IOC_IOCFG28_IOSTR_M 0x00000300 -#define IOC_IOCFG28_IOSTR_S 8 -#define IOC_IOCFG28_IOSTR_MAX 0x00000300 -#define IOC_IOCFG28_IOSTR_MED 0x00000200 -#define IOC_IOCFG28_IOSTR_MIN 0x00000100 -#define IOC_IOCFG28_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG28_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG28_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG28_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG28_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG28_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG28_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG28_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG28_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO28 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG28_PORT_ID_W 6 -#define IOC_IOCFG28_PORT_ID_M 0x0000003F -#define IOC_IOCFG28_PORT_ID_S 0 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG28_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG28_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG28_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG28_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG29 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG29_HYST_EN 0x40000000 -#define IOC_IOCFG29_HYST_EN_BITN 30 -#define IOC_IOCFG29_HYST_EN_M 0x40000000 -#define IOC_IOCFG29_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG29_IE 0x20000000 -#define IOC_IOCFG29_IE_BITN 29 -#define IOC_IOCFG29_IE_M 0x20000000 -#define IOC_IOCFG29_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG29_WU_CFG_W 2 -#define IOC_IOCFG29_WU_CFG_M 0x18000000 -#define IOC_IOCFG29_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG29_IOMODE_W 3 -#define IOC_IOCFG29_IOMODE_M 0x07000000 -#define IOC_IOCFG29_IOMODE_S 24 -#define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG29_IOMODE_INV 0x01000000 -#define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG29_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG29_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG29_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG29_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG29_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG29_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG29_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG29_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG29_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG29_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG29_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG29_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG29_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG29_EDGE_DET_W 2 -#define IOC_IOCFG29_EDGE_DET_M 0x00030000 -#define IOC_IOCFG29_EDGE_DET_S 16 -#define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG29_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG29_PULL_CTL_W 2 -#define IOC_IOCFG29_PULL_CTL_M 0x00006000 -#define IOC_IOCFG29_PULL_CTL_S 13 -#define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG29_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG29_SLEW_RED 0x00001000 -#define IOC_IOCFG29_SLEW_RED_BITN 12 -#define IOC_IOCFG29_SLEW_RED_M 0x00001000 -#define IOC_IOCFG29_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG29_IOCURR_W 2 -#define IOC_IOCFG29_IOCURR_M 0x00000C00 -#define IOC_IOCFG29_IOCURR_S 10 -#define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG29_IOCURR_4MA 0x00000400 -#define IOC_IOCFG29_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG29_IOSTR_W 2 -#define IOC_IOCFG29_IOSTR_M 0x00000300 -#define IOC_IOCFG29_IOSTR_S 8 -#define IOC_IOCFG29_IOSTR_MAX 0x00000300 -#define IOC_IOCFG29_IOSTR_MED 0x00000200 -#define IOC_IOCFG29_IOSTR_MIN 0x00000100 -#define IOC_IOCFG29_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG29_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG29_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG29_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG29_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG29_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG29_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG29_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG29_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO29 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG29_PORT_ID_W 6 -#define IOC_IOCFG29_PORT_ID_M 0x0000003F -#define IOC_IOCFG29_PORT_ID_S 0 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG29_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG29_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG29_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG29_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG30 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG30_HYST_EN 0x40000000 -#define IOC_IOCFG30_HYST_EN_BITN 30 -#define IOC_IOCFG30_HYST_EN_M 0x40000000 -#define IOC_IOCFG30_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG30_IE 0x20000000 -#define IOC_IOCFG30_IE_BITN 29 -#define IOC_IOCFG30_IE_M 0x20000000 -#define IOC_IOCFG30_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG30_WU_CFG_W 2 -#define IOC_IOCFG30_WU_CFG_M 0x18000000 -#define IOC_IOCFG30_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG30_IOMODE_W 3 -#define IOC_IOCFG30_IOMODE_M 0x07000000 -#define IOC_IOCFG30_IOMODE_S 24 -#define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG30_IOMODE_INV 0x01000000 -#define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG30_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG30_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG30_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG30_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG30_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG30_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG30_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG30_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG30_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG30_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG30_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG30_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG30_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG30_EDGE_DET_W 2 -#define IOC_IOCFG30_EDGE_DET_M 0x00030000 -#define IOC_IOCFG30_EDGE_DET_S 16 -#define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG30_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG30_PULL_CTL_W 2 -#define IOC_IOCFG30_PULL_CTL_M 0x00006000 -#define IOC_IOCFG30_PULL_CTL_S 13 -#define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG30_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG30_SLEW_RED 0x00001000 -#define IOC_IOCFG30_SLEW_RED_BITN 12 -#define IOC_IOCFG30_SLEW_RED_M 0x00001000 -#define IOC_IOCFG30_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG30_IOCURR_W 2 -#define IOC_IOCFG30_IOCURR_M 0x00000C00 -#define IOC_IOCFG30_IOCURR_S 10 -#define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG30_IOCURR_4MA 0x00000400 -#define IOC_IOCFG30_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG30_IOSTR_W 2 -#define IOC_IOCFG30_IOSTR_M 0x00000300 -#define IOC_IOCFG30_IOSTR_S 8 -#define IOC_IOCFG30_IOSTR_MAX 0x00000300 -#define IOC_IOCFG30_IOSTR_MED 0x00000200 -#define IOC_IOCFG30_IOSTR_MIN 0x00000100 -#define IOC_IOCFG30_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG30_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG30_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG30_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG30_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG30_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG30_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG30_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG30_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO30 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG30_PORT_ID_W 6 -#define IOC_IOCFG30_PORT_ID_M 0x0000003F -#define IOC_IOCFG30_PORT_ID_S 0 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG30_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG30_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG30_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG30_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 - -//***************************************************************************** -// -// Register: IOC_O_IOCFG31 -// -//***************************************************************************** -// Field: [30] HYST_EN -// -// 0: Input hysteresis disable -// 1: Input hysteresis enable -#define IOC_IOCFG31_HYST_EN 0x40000000 -#define IOC_IOCFG31_HYST_EN_BITN 30 -#define IOC_IOCFG31_HYST_EN_M 0x40000000 -#define IOC_IOCFG31_HYST_EN_S 30 - -// Field: [29] IE -// -// 0: Input disabled -// 1: Input enabled -// -// Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be -// ignored. -#define IOC_IOCFG31_IE 0x20000000 -#define IOC_IOCFG31_IE_BITN 29 -#define IOC_IOCFG31_IE_M 0x20000000 -#define IOC_IOCFG31_IE_S 29 - -// Field: [28:27] WU_CFG -// -// If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or -// >0x08: -// -// 00: No wake-up -// 01: No wake-up -// 10: Wakes up from shutdown if this pad is going low. -// 11: Wakes up from shutdown if this pad is going high. -// -// If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, -// this register only sets wakeup enable or not. -// -// 00, 01: Wakeup disabled -// 10, 11: Wakeup enabled -// -// Polarity is controlled from AON registers. -// -// Note:When the MSB is set, the IOC will deactivate the output enable for the -// DIO. -#define IOC_IOCFG31_WU_CFG_W 2 -#define IOC_IOCFG31_WU_CFG_M 0x18000000 -#define IOC_IOCFG31_WU_CFG_S 27 - -// Field: [26:24] IOMODE -// -// IO Mode -// Not applicable for IO configured for AON periph. signals and AUX PORT_ID -// 0x01-0x08 -// AUX has its own open_source/drain configuration. -// -// 0x2: Reserved. Undefined behavior. -// 0x3: Reserved. Undefined behavior. -// ENUMs: -// OPENSRC_INV Open Source -// Inverted input / output -// OPENSRC Open Source -// Normal input / output -// OPENDR_INV Open Drain -// Inverted input / output -// OPENDR Open Drain, -// Normal input / output -// INV Inverted input / ouput -// NORMAL Normal input / output -#define IOC_IOCFG31_IOMODE_W 3 -#define IOC_IOCFG31_IOMODE_M 0x07000000 -#define IOC_IOCFG31_IOMODE_S 24 -#define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 -#define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 -#define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 -#define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 -#define IOC_IOCFG31_IOMODE_INV 0x01000000 -#define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 - -// Field: [23] IOEV_AON_PROG2_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG2 event -// 1: Input edge detection asserts AON_PROG2 event -#define IOC_IOCFG31_IOEV_AON_PROG2_EN 0x00800000 -#define IOC_IOCFG31_IOEV_AON_PROG2_EN_BITN 23 -#define IOC_IOCFG31_IOEV_AON_PROG2_EN_M 0x00800000 -#define IOC_IOCFG31_IOEV_AON_PROG2_EN_S 23 - -// Field: [22] IOEV_AON_PROG1_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG1 event -// 1: Input edge detection asserts AON_PROG1 event -#define IOC_IOCFG31_IOEV_AON_PROG1_EN 0x00400000 -#define IOC_IOCFG31_IOEV_AON_PROG1_EN_BITN 22 -#define IOC_IOCFG31_IOEV_AON_PROG1_EN_M 0x00400000 -#define IOC_IOCFG31_IOEV_AON_PROG1_EN_S 22 - -// Field: [21] IOEV_AON_PROG0_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert AON_PROG0 event -// 1: Input edge detection asserts AON_PROG0 event -#define IOC_IOCFG31_IOEV_AON_PROG0_EN 0x00200000 -#define IOC_IOCFG31_IOEV_AON_PROG0_EN_BITN 21 -#define IOC_IOCFG31_IOEV_AON_PROG0_EN_M 0x00200000 -#define IOC_IOCFG31_IOEV_AON_PROG0_EN_S 21 - -// Field: [18] EDGE_IRQ_EN -// -// 0: No interrupt generation -// 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is -// enabled) -#define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 -#define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 -#define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 -#define IOC_IOCFG31_EDGE_IRQ_EN_S 18 - -// Field: [17:16] EDGE_DET -// -// Enable generation of edge detection events on this IO -// ENUMs: -// BOTH Positive and negative edge detection -// POS Positive edge detection -// NEG Negative edge detection -// NONE No edge detection -#define IOC_IOCFG31_EDGE_DET_W 2 -#define IOC_IOCFG31_EDGE_DET_M 0x00030000 -#define IOC_IOCFG31_EDGE_DET_S 16 -#define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 -#define IOC_IOCFG31_EDGE_DET_POS 0x00020000 -#define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 -#define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 - -// Field: [14:13] PULL_CTL -// -// Pull control -// ENUMs: -// DIS No pull -// UP Pull up -// DWN Pull down -#define IOC_IOCFG31_PULL_CTL_W 2 -#define IOC_IOCFG31_PULL_CTL_M 0x00006000 -#define IOC_IOCFG31_PULL_CTL_S 13 -#define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 -#define IOC_IOCFG31_PULL_CTL_UP 0x00004000 -#define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 - -// Field: [12] SLEW_RED -// -// 0: Normal slew rate -// 1: Enables reduced slew rate in output driver. -#define IOC_IOCFG31_SLEW_RED 0x00001000 -#define IOC_IOCFG31_SLEW_RED_BITN 12 -#define IOC_IOCFG31_SLEW_RED_M 0x00001000 -#define IOC_IOCFG31_SLEW_RED_S 12 - -// Field: [11:10] IOCURR -// -// Selects IO current mode of this IO. -// ENUMs: -// 4_8MA Extended-Current (EC) mode: Min 8 mA for double -// drive strength IOs (min 4 mA for normal IOs) -// when IOSTR is set to AUTO -// 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set -// to AUTO -// 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set -// to AUTO -#define IOC_IOCFG31_IOCURR_W 2 -#define IOC_IOCFG31_IOCURR_M 0x00000C00 -#define IOC_IOCFG31_IOCURR_S 10 -#define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 -#define IOC_IOCFG31_IOCURR_4MA 0x00000400 -#define IOC_IOCFG31_IOCURR_2MA 0x00000000 - -// Field: [9:8] IOSTR -// -// Select source for drive strength control of this IO. -// This setting controls the drive strength of the Low-Current (LC) mode. -// Higher drive strength can be selected in IOCURR -// ENUMs: -// MAX Maximum drive strength, controlled by -// AON_IOC:IOSTRMAX (min 2 mA @1.8V with default -// values) -// MED Medium drive strength, controlled by -// AON_IOC:IOSTRMED (min 2 mA @2.5V with default -// values) -// MIN Minimum drive strength, controlled by -// AON_IOC:IOSTRMIN (min 2 mA @3.3V with default -// values) -// AUTO Automatic drive strength, controlled by AON BATMON -// based on battery voltage. (min 2 mA @VDDS) -#define IOC_IOCFG31_IOSTR_W 2 -#define IOC_IOCFG31_IOSTR_M 0x00000300 -#define IOC_IOCFG31_IOSTR_S 8 -#define IOC_IOCFG31_IOSTR_MAX 0x00000300 -#define IOC_IOCFG31_IOSTR_MED 0x00000200 -#define IOC_IOCFG31_IOSTR_MIN 0x00000100 -#define IOC_IOCFG31_IOSTR_AUTO 0x00000000 - -// Field: [7] IOEV_RTC_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert RTC event -// 1: Input edge detection asserts RTC event -#define IOC_IOCFG31_IOEV_RTC_EN 0x00000080 -#define IOC_IOCFG31_IOEV_RTC_EN_BITN 7 -#define IOC_IOCFG31_IOEV_RTC_EN_M 0x00000080 -#define IOC_IOCFG31_IOEV_RTC_EN_S 7 - -// Field: [6] IOEV_MCU_WU_EN -// -// Event asserted by this IO when edge detection is enabled -// -// 0: Input edge detection does not assert MCU_WU event -// 1: Input edge detection asserts MCU_WU event -#define IOC_IOCFG31_IOEV_MCU_WU_EN 0x00000040 -#define IOC_IOCFG31_IOEV_MCU_WU_EN_BITN 6 -#define IOC_IOCFG31_IOEV_MCU_WU_EN_M 0x00000040 -#define IOC_IOCFG31_IOEV_MCU_WU_EN_S 6 - -// Field: [5:0] PORT_ID -// -// Selects usage for DIO31 -// ENUMs: -// RFC_SMI_CL_IN RF Core SMI Command Link In -// RFC_SMI_CL_OUT RF Core SMI Command Link Out -// RFC_SMI_DL_IN RF Core SMI Data Link In -// RFC_SMI_DL_OUT RF Core SMI Data Link Out -// RFC_GPI1 RF Core Data In 1 -// RFC_GPI0 RF Core Data In 0 -// RFC_GPO3 RF Core Data Out 3 -// RFC_GPO2 RF Core Data Out 2 -// RFC_GPO1 RF Core Data Out 1 -// RFC_GPO0 RF Core Data Out 0 -// RFC_TRC RF Core Trace -// I2S_MCLK I2S MCLK -// I2S_BCLK I2S BCLK -// I2S_WCLK I2S WCLK -// I2S_AD1 I2S Data 1 -// I2S_AD0 I2S Data 0 -// SSI1_CLK SSI1 CLK -// SSI1_FSS SSI1 FSS -// SSI1_TX SSI1 TX -// SSI1_RX SSI1 RX -// CPU_SWV CPU SWV -// PORT_EVENT7 PORT EVENT 7 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT6 PORT EVENT 6 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT5 PORT EVENT 5 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT4 PORT EVENT 4 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT3 PORT EVENT 3 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT2 PORT EVENT 2 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT1 PORT EVENT 1 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// PORT_EVENT0 PORT EVENT 0 -// Can be used as a general -// purpose IO event by selecting it through -// registers in the EVENT module, for example -// EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, -// and so on -// UART1_RTS UART1 RTS -// UART1_CTS UART1 CTS -// UART1_TX UART1 TX -// UART1_RX UART1 RX -// UART0_RTS UART0 RTS -// UART0_CTS UART0 CTS -// UART0_TX UART0 TX -// UART0_RX UART0 RX -// I2C_MSSCL I2C Clock -// I2C_MSSDA I2C Data -// SSI0_CLK SSI0 CLK -// SSI0_FSS SSI0 FSS -// SSI0_TX SSI0 TX -// SSI0_RX SSI0 RX -// AUX_IO AUX IO -// AON_CLK32K AON 32 KHz clock (SCLK_LF) -// GPIO General Purpose IO -#define IOC_IOCFG31_PORT_ID_W 6 -#define IOC_IOCFG31_PORT_ID_M 0x0000003F -#define IOC_IOCFG31_PORT_ID_S 0 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 -#define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 -#define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 -#define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 -#define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 -#define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 -#define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 -#define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F -#define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E -#define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 -#define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 -#define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 -#define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 -#define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 -#define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 -#define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 -#define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 -#define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 -#define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E -#define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D -#define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C -#define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B -#define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A -#define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 -#define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 -#define IOC_IOCFG31_PORT_ID_UART1_RTS 0x00000016 -#define IOC_IOCFG31_PORT_ID_UART1_CTS 0x00000015 -#define IOC_IOCFG31_PORT_ID_UART1_TX 0x00000014 -#define IOC_IOCFG31_PORT_ID_UART1_RX 0x00000013 -#define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 -#define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 -#define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 -#define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F -#define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E -#define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D -#define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C -#define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B -#define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A -#define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 -#define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 -#define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 -#define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 - - -#endif // __IOC__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h deleted file mode 100644 index e8a9e8bae8d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_memmap.h +++ /dev/null @@ -1,180 +0,0 @@ -/****************************************************************************** -* Filename: hw_memmap_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following are defines for the base address of the memories and -// peripherals on the CPU_MMAP interface -// -//***************************************************************************** -#define FLASHMEM_BASE 0x00000000 // FLASHMEM -#define BROM_BASE 0x10000000 // BROM -#define GPRAM_BASE 0x11000000 // GPRAM -#define SRAM_BASE 0x20000000 // SRAM -#define RFC_RAM_BASE 0x21000000 // RFC_RAM -#define RFC_ULLRAM_BASE 0x21004000 // RFC_ULLRAM -#define SSI0_BASE 0x40000000 // SSI -#define UART0_BASE 0x40001000 // UART -#define I2C0_BASE 0x40002000 // I2C -#define SSI1_BASE 0x40008000 // SSI -#define UART1_BASE 0x4000B000 // UART -#define GPT0_BASE 0x40010000 // GPT -#define GPT1_BASE 0x40011000 // GPT -#define GPT2_BASE 0x40012000 // GPT -#define GPT3_BASE 0x40013000 // GPT -#define UDMA0_BASE 0x40020000 // UDMA -#define I2S0_BASE 0x40021000 // I2S -#define GPIO_BASE 0x40022000 // GPIO -#define CRYPTO_BASE 0x40024000 // CRYPTO -#define PKA_BASE 0x40025000 // PKA -#define PKA_RAM_BASE 0x40026000 // PKA_RAM -#define PKA_INT_BASE 0x40027000 // PKA_INT -#define TRNG_BASE 0x40028000 // TRNG -#define FLASH_BASE 0x40030000 // FLASH -#define VIMS_BASE 0x40034000 // VIMS -#define SRAM_MMR_BASE 0x40035000 // SRAM_MMR -#define RFC_PWR_BASE 0x40040000 // RFC_PWR -#define RFC_DBELL_BASE 0x40041000 // RFC_DBELL -#define RFC_RAT_BASE 0x40043000 // RFC_RAT -#define RFC_FSCA_BASE 0x40044000 // RFC_FSCA -#define WDT_BASE 0x40080000 // WDT -#define IOC_BASE 0x40081000 // IOC -#define PRCM_BASE 0x40082000 // PRCM -#define EVENT_BASE 0x40083000 // EVENT -#define SMPH_BASE 0x40084000 // SMPH -#define ADI2_BASE 0x40086000 // ADI -#define ADI3_BASE 0x40086200 // ADI -#define AON_PMCTL_BASE 0x40090000 // AON_PMCTL -#define AON_RTC_BASE 0x40092000 // AON_RTC -#define AON_EVENT_BASE 0x40093000 // AON_EVENT -#define AON_IOC_BASE 0x40094000 // AON_IOC -#define AON_BATMON_BASE 0x40095000 // AON_BATMON -#define AUX_SPIM_BASE 0x400C1000 // AUX_SPIM -#define AUX_MAC_BASE 0x400C2000 // AUX_MAC -#define AUX_TIMER2_BASE 0x400C3000 // AUX_TIMER2 -#define AUX_TDC_BASE 0x400C4000 // AUX_TDC -#define AUX_EVCTL_BASE 0x400C5000 // AUX_EVCTL -#define AUX_SYSIF_BASE 0x400C6000 // AUX_SYSIF -#define AUX_TIMER01_BASE 0x400C7000 // AUX_TIMER01 -#define AUX_SMPH_BASE 0x400C8000 // AUX_SMPH -#define AUX_ANAIF_BASE 0x400C9000 // AUX_ANAIF -#define AUX_DDI0_OSC_BASE 0x400CA000 // DDI -#define AUX_ADI4_BASE 0x400CB000 // ADI -#define AUX_AIODIO0_BASE 0x400CC000 // AUX_AIODIO -#define AUX_AIODIO1_BASE 0x400CD000 // AUX_AIODIO -#define AUX_AIODIO2_BASE 0x400CE000 // AUX_AIODIO -#define AUX_AIODIO3_BASE 0x400CF000 // AUX_AIODIO -#define AUX_RAM_BASE 0x400E0000 // AUX_RAM -#define AUX_SCE_BASE 0x400E1000 // AUX_SCE -#define FLASH_CFG_BASE 0x50000000 // CC26_DUMMY_COMP -#define FCFG1_BASE 0x50001000 // FCFG1 -#define FCFG2_BASE 0x50002000 // FCFG2 -#ifndef CCFG_BASE -#define CCFG_BASE 0x50003000 // CCFG -#endif -#define CCFG_BASE_DEFAULT 0x50003000 // CCFG -#define SSI0_NONBUF_BASE 0x60000000 // SSI CPU nonbuf base -#define UART0_NONBUF_BASE 0x60001000 // UART CPU nonbuf base -#define I2C0_NONBUF_BASE 0x60002000 // I2C CPU nonbuf base -#define SSI1_NONBUF_BASE 0x60008000 // SSI CPU nonbuf base -#define UART1_NONBUF_BASE 0x6000B000 // UART CPU nonbuf base -#define GPT0_NONBUF_BASE 0x60010000 // GPT CPU nonbuf base -#define GPT1_NONBUF_BASE 0x60011000 // GPT CPU nonbuf base -#define GPT2_NONBUF_BASE 0x60012000 // GPT CPU nonbuf base -#define GPT3_NONBUF_BASE 0x60013000 // GPT CPU nonbuf base -#define UDMA0_NONBUF_BASE 0x60020000 // UDMA CPU nonbuf base -#define I2S0_NONBUF_BASE 0x60021000 // I2S CPU nonbuf base -#define GPIO_NONBUF_BASE 0x60022000 // GPIO CPU nonbuf base -#define CRYPTO_NONBUF_BASE 0x60024000 // CRYPTO CPU nonbuf base -#define PKA_NONBUF_BASE 0x60025000 // PKA CPU nonbuf base -#define PKA_RAM_NONBUF_BASE 0x60026000 // PKA_RAM CPU nonbuf base -#define PKA_INT_NONBUF_BASE 0x60027000 // PKA_INT CPU nonbuf base -#define TRNG_NONBUF_BASE 0x60028000 // TRNG CPU nonbuf base -#define FLASH_NONBUF_BASE 0x60030000 // FLASH CPU nonbuf base -#define VIMS_NONBUF_BASE 0x60034000 // VIMS CPU nonbuf base -#define SRAM_MMR_NONBUF_BASE 0x60035000 // SRAM_MMR CPU nonbuf base -#define RFC_PWR_NONBUF_BASE 0x60040000 // RFC_PWR CPU nonbuf base -#define RFC_DBELL_NONBUF_BASE 0x60041000 // RFC_DBELL CPU nonbuf base -#define RFC_RAT_NONBUF_BASE 0x60043000 // RFC_RAT CPU nonbuf base -#define RFC_FSCA_NONBUF_BASE 0x60044000 // RFC_FSCA CPU nonbuf base -#define WDT_NONBUF_BASE 0x60080000 // WDT CPU nonbuf base -#define IOC_NONBUF_BASE 0x60081000 // IOC CPU nonbuf base -#define PRCM_NONBUF_BASE 0x60082000 // PRCM CPU nonbuf base -#define EVENT_NONBUF_BASE 0x60083000 // EVENT CPU nonbuf base -#define SMPH_NONBUF_BASE 0x60084000 // SMPH CPU nonbuf base -#define ADI2_NONBUF_BASE 0x60086000 // ADI CPU nonbuf base -#define ADI3_NONBUF_BASE 0x60086200 // ADI CPU nonbuf base -#define AON_PMCTL_NONBUF_BASE 0x60090000 // AON_PMCTL CPU nonbuf base -#define AON_RTC_NONBUF_BASE 0x60092000 // AON_RTC CPU nonbuf base -#define AON_EVENT_NONBUF_BASE 0x60093000 // AON_EVENT CPU nonbuf base -#define AON_IOC_NONBUF_BASE 0x60094000 // AON_IOC CPU nonbuf base -#define AON_BATMON_NONBUF_BASE 0x60095000 // AON_BATMON CPU nonbuf base -#define AUX_SPIM_NONBUF_BASE 0x600C1000 // AUX_SPIM CPU nonbuf base -#define AUX_MAC_NONBUF_BASE 0x600C2000 // AUX_MAC CPU nonbuf base -#define AUX_TIMER2_NONBUF_BASE 0x600C3000 // AUX_TIMER2 CPU nonbuf base -#define AUX_TDC_NONBUF_BASE 0x600C4000 // AUX_TDC CPU nonbuf base -#define AUX_EVCTL_NONBUF_BASE 0x600C5000 // AUX_EVCTL CPU nonbuf base -#define AUX_SYSIF_NONBUF_BASE 0x600C6000 // AUX_SYSIF CPU nonbuf base -#define AUX_TIMER01_NONBUF_BASE \ - 0x600C7000 // AUX_TIMER01 CPU nonbuf base -#define AUX_SMPH_NONBUF_BASE 0x600C8000 // AUX_SMPH CPU nonbuf base -#define AUX_ANAIF_NONBUF_BASE 0x600C9000 // AUX_ANAIF CPU nonbuf base -#define AUX_DDI0_OSC_NONBUF_BASE \ - 0x600CA000 // DDI CPU nonbuf base -#define AUX_ADI4_NONBUF_BASE 0x600CB000 // ADI CPU nonbuf base -#define AUX_AIODIO0_NONBUF_BASE \ - 0x600CC000 // AUX_AIODIO CPU nonbuf base -#define AUX_AIODIO1_NONBUF_BASE \ - 0x600CD000 // AUX_AIODIO CPU nonbuf base -#define AUX_AIODIO2_NONBUF_BASE \ - 0x600CE000 // AUX_AIODIO CPU nonbuf base -#define AUX_AIODIO3_NONBUF_BASE \ - 0x600CF000 // AUX_AIODIO CPU nonbuf base -#define AUX_RAM_NONBUF_BASE 0x600E0000 // AUX_RAM CPU nonbuf base -#define AUX_SCE_NONBUF_BASE 0x600E1000 // AUX_SCE CPU nonbuf base -#define FLASHMEM_ALIAS_BASE 0xA0000000 // FLASHMEM Alias base -#define CPU_ITM_BASE 0xE0000000 // CPU_ITM -#define CPU_DWT_BASE 0xE0001000 // CPU_DWT -#define CPU_FPB_BASE 0xE0002000 // CPU_FPB -#define CPU_SCS_BASE 0xE000E000 // CPU_SCS -#define CPU_TPIU_BASE 0xE0040000 // CPU_TPIU -#define CPU_TIPROP_BASE 0xE00FE000 // CPU_TIPROP -#define CPU_ROM_TABLE_BASE 0xE00FF000 // CPU_ROM_TABLE - -#endif // __HW_MEMMAP__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h deleted file mode 100644 index 15c5224723e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_nvic.h +++ /dev/null @@ -1,1026 +0,0 @@ -/****************************************************************************** -* Filename: hw_nvic.h -* Revised: 2015-01-13 16:59:55 +0100 (Tue, 13 Jan 2015) -* Revision: 42365 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following are defines for the NVIC register addresses. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg -#define NVIC_ACTLR 0xE000E008 // Auxiliary Control -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status - // Register -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg -#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable -#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable -#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable -#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable -#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending -#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending -#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending -#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending -#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit -#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit -#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority -#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority -#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority -#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority -#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority -#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority -#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority -#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority -#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority -#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority -#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority -#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority -#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority -#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority -#define NVIC_CPUID 0xE000ED00 // CPU ID Base -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset -#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset - // Control -#define NVIC_SYS_CTRL 0xE000ED10 // System Control -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control -#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 -#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 -#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size -#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 -#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size - // Alias 1 -#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 -#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size - // Alias 2 -#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 -#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size - // Alias 3 -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTLR register. -// -//***************************************************************************** -#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding -#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer -#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple - // Cycle Instructions - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CURRENT -// register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask -#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask -#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask -#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask -#define NVIC_PRI0_INT3_S 29 -#define NVIC_PRI0_INT2_S 21 -#define NVIC_PRI0_INT1_S 13 -#define NVIC_PRI0_INT0_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask -#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask -#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask -#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask -#define NVIC_PRI1_INT7_S 29 -#define NVIC_PRI1_INT6_S 21 -#define NVIC_PRI1_INT5_S 13 -#define NVIC_PRI1_INT4_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask -#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask -#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask -#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask -#define NVIC_PRI2_INT11_S 29 -#define NVIC_PRI2_INT10_S 21 -#define NVIC_PRI2_INT9_S 13 -#define NVIC_PRI2_INT8_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask -#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask -#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask -#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask -#define NVIC_PRI3_INT15_S 29 -#define NVIC_PRI3_INT14_S 21 -#define NVIC_PRI3_INT13_S 13 -#define NVIC_PRI3_INT12_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask -#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask -#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask -#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask -#define NVIC_PRI4_INT19_S 29 -#define NVIC_PRI4_INT18_S 21 -#define NVIC_PRI4_INT17_S 13 -#define NVIC_PRI4_INT16_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask -#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask -#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask -#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask -#define NVIC_PRI5_INT23_S 29 -#define NVIC_PRI5_INT22_S 21 -#define NVIC_PRI5_INT21_S 13 -#define NVIC_PRI5_INT20_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask -#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask -#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask -#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask -#define NVIC_PRI6_INT27_S 29 -#define NVIC_PRI6_INT26_S 21 -#define NVIC_PRI6_INT25_S 13 -#define NVIC_PRI6_INT24_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask -#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask -#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask -#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask -#define NVIC_PRI7_INT31_S 29 -#define NVIC_PRI7_INT30_S 21 -#define NVIC_PRI7_INT29_S 13 -#define NVIC_PRI7_INT28_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask -#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask -#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask -#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask -#define NVIC_PRI8_INT35_S 29 -#define NVIC_PRI8_INT34_S 21 -#define NVIC_PRI8_INT33_S 13 -#define NVIC_PRI8_INT32_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask -#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask -#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask -#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask -#define NVIC_PRI9_INT39_S 29 -#define NVIC_PRI9_INT38_S 21 -#define NVIC_PRI9_INT37_S 13 -#define NVIC_PRI9_INT36_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask -#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask -#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask -#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask -#define NVIC_PRI10_INT43_S 29 -#define NVIC_PRI10_INT42_S 21 -#define NVIC_PRI10_INT41_S 13 -#define NVIC_PRI10_INT40_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI11 register. -// -//***************************************************************************** -#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask -#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask -#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask -#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask -#define NVIC_PRI11_INT47_S 29 -#define NVIC_PRI11_INT46_S 21 -#define NVIC_PRI11_INT45_S 13 -#define NVIC_PRI11_INT44_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI12 register. -// -//***************************************************************************** -#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask -#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask -#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask -#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask -#define NVIC_PRI12_INT51_S 29 -#define NVIC_PRI12_INT50_S 21 -#define NVIC_PRI12_INT49_S 13 -#define NVIC_PRI12_INT48_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI13 register. -// -//***************************************************************************** -#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask -#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask -#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask -#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask -#define NVIC_PRI13_INT55_S 29 -#define NVIC_PRI13_INT54_S 21 -#define NVIC_PRI13_INT53_S 13 -#define NVIC_PRI13_INT52_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code -#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number -#define NVIC_CPUID_CON_M 0x000F0000 // Constant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number -#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor -#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor -#define NVIC_CPUID_REV_M 0x0000000F // Revision Number - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number -#undef NVIC_INT_CTRL_VEC_PEN_M -#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_PEN_NMI \ - 0x00002000 // NMI -#define NVIC_INT_CTRL_VEC_PEN_HARD \ - 0x00003000 // Hard fault -#define NVIC_INT_CTRL_VEC_PEN_MEM \ - 0x00004000 // Memory management fault -#define NVIC_INT_CTRL_VEC_PEN_BUS \ - 0x00005000 // Bus fault -#define NVIC_INT_CTRL_VEC_PEN_USG \ - 0x00006000 // Usage fault -#define NVIC_INT_CTRL_VEC_PEN_SVC \ - 0x0000B000 // SVCall -#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ - 0x0000E000 // PendSV -#define NVIC_INT_CTRL_VEC_PEN_TICK \ - 0x0000F000 // SysTick -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base -#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number -#undef NVIC_INT_CTRL_VEC_ACT_M -#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset -#undef NVIC_VTABLE_OFFSET_M -#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset -#define NVIC_VTABLE_OFFSET_S 9 -#undef NVIC_VTABLE_OFFSET_S -#define NVIC_VTABLE_OFFSET_S 10 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault -#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception - // Entry -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and - // Fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority -#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority -#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority -#define NVIC_SYS_PRI1_USAGE_S 21 -#define NVIC_SYS_PRI1_BUS_S 13 -#define NVIC_SYS_PRI1_MEM_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority -#define NVIC_SYS_PRI2_SVC_S 29 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority -#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority -#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority -#define NVIC_SYS_PRI3_TICK_S 29 -#define NVIC_SYS_PRI3_PENDSV_S 21 -#define NVIC_SYS_PRI3_DEBUG_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL -// register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending -#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending -#define NVIC_SYS_HND_CTRL_USAGEP \ - 0x00001000 // Usage Fault Pending -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage - // Fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid -#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy - // State Preservation -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error -#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address - // Register Valid -#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on - // Floating-Point Lazy State - // Preservation -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_HFAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DEBUG_STAT -// register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_ADDR -// register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read -#define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction - // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available -#define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h deleted file mode 100644 index 377f08e1089..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka.h +++ /dev/null @@ -1,606 +0,0 @@ -/****************************************************************************** -* Filename: hw_pka_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_PKA_H__ -#define __HW_PKA_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// PKA component -// -//***************************************************************************** -// PKA Vector A Address -#define PKA_O_APTR 0x00000000 - -// PKA Vector B Address -#define PKA_O_BPTR 0x00000004 - -// PKA Vector C Address -#define PKA_O_CPTR 0x00000008 - -// PKA Vector D Address -#define PKA_O_DPTR 0x0000000C - -// PKA Vector A Length -#define PKA_O_ALENGTH 0x00000010 - -// PKA Vector B Length -#define PKA_O_BLENGTH 0x00000014 - -// PKA Bit Shift Value -#define PKA_O_SHIFT 0x00000018 - -// PKA Function -#define PKA_O_FUNCTION 0x0000001C - -// PKA compare result -#define PKA_O_COMPARE 0x00000020 - -// PKA most-significant-word of result vector -#define PKA_O_MSW 0x00000024 - -// PKA most-significant-word of divide remainder -#define PKA_O_DIVMSW 0x00000028 - -// PKA sequencer control and status register -#define PKA_O_SEQCTRL 0x000000C8 - -// PKA hardware options register -#define PKA_O_OPTIONS 0x000000F4 - -// PKA firmware revision and capabilities register -#define PKA_O_FWREV 0x000000F8 - -// PKA hardware revision register -#define PKA_O_HWREV 0x000000FC - -//***************************************************************************** -// -// Register: PKA_O_APTR -// -//***************************************************************************** -// Field: [10:0] APTR -// -// This register specifies the location of vector A within the PKA RAM. Vectors -// are identified through the location of their least-significant 32-bit word. -// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte -// boundary. -#define PKA_APTR_APTR_W 11 -#define PKA_APTR_APTR_M 0x000007FF -#define PKA_APTR_APTR_S 0 - -//***************************************************************************** -// -// Register: PKA_O_BPTR -// -//***************************************************************************** -// Field: [10:0] BPTR -// -// This register specifies the location of vector B within the PKA RAM. Vectors -// are identified through the location of their least-significant 32-bit word. -// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte -// boundary. -#define PKA_BPTR_BPTR_W 11 -#define PKA_BPTR_BPTR_M 0x000007FF -#define PKA_BPTR_BPTR_S 0 - -//***************************************************************************** -// -// Register: PKA_O_CPTR -// -//***************************************************************************** -// Field: [10:0] CPTR -// -// This register specifies the location of vector C within the PKA RAM. Vectors -// are identified through the location of their least-significant 32-bit word. -// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte -// boundary. -#define PKA_CPTR_CPTR_W 11 -#define PKA_CPTR_CPTR_M 0x000007FF -#define PKA_CPTR_CPTR_S 0 - -//***************************************************************************** -// -// Register: PKA_O_DPTR -// -//***************************************************************************** -// Field: [10:0] DPTR -// -// This register specifies the location of vector D within the PKA RAM. Vectors -// are identified through the location of their least-significant 32-bit word. -// Note that bit [0] must be zero to ensure that the vector starts at an 8-byte -// boundary. -#define PKA_DPTR_DPTR_W 11 -#define PKA_DPTR_DPTR_M 0x000007FF -#define PKA_DPTR_DPTR_S 0 - -//***************************************************************************** -// -// Register: PKA_O_ALENGTH -// -//***************************************************************************** -// Field: [8:0] ALENGTH -// -// This register specifies the length (in 32-bit words) of Vector A. -#define PKA_ALENGTH_ALENGTH_W 9 -#define PKA_ALENGTH_ALENGTH_M 0x000001FF -#define PKA_ALENGTH_ALENGTH_S 0 - -//***************************************************************************** -// -// Register: PKA_O_BLENGTH -// -//***************************************************************************** -// Field: [8:0] BLENGTH -// -// This register specifies the length (in 32-bit words) of Vector B. -#define PKA_BLENGTH_BLENGTH_W 9 -#define PKA_BLENGTH_BLENGTH_M 0x000001FF -#define PKA_BLENGTH_BLENGTH_S 0 - -//***************************************************************************** -// -// Register: PKA_O_SHIFT -// -//***************************************************************************** -// Field: [4:0] NUM_BITS_TO_SHIFT -// -// This register specifies the number of bits to shift the input vector (in the -// range 0-31) during a Rshift or Lshift operation. -#define PKA_SHIFT_NUM_BITS_TO_SHIFT_W 5 -#define PKA_SHIFT_NUM_BITS_TO_SHIFT_M 0x0000001F -#define PKA_SHIFT_NUM_BITS_TO_SHIFT_S 0 - -//***************************************************************************** -// -// Register: PKA_O_FUNCTION -// -//***************************************************************************** -// Field: [24] STALL_RESULT -// -// When written with a 1b, updating of the COMPARE bit, MSW and DIVMSW -// registers, as well as resetting the run bit is stalled beyond the point that -// a running operation is actually finished. Use this to allow software enough -// time to read results from a previous operation when the newly started -// operation is known to take only a short amount of time. If a result is -// waiting, the result registers is updated and the run bit is reset in the -// clock cycle following writing the stall result bit back to 0b. The Stall -// result function may only be used for basic PKCP operations. -#define PKA_FUNCTION_STALL_RESULT 0x01000000 -#define PKA_FUNCTION_STALL_RESULT_BITN 24 -#define PKA_FUNCTION_STALL_RESULT_M 0x01000000 -#define PKA_FUNCTION_STALL_RESULT_S 24 - -// Field: [15] RUN -// -// The host sets this bit to instruct the PKA module to begin processing the -// basic PKCP or complex sequencer operation. This bit is reset low -// automatically when the operation is complete. -// After a reset, the run bit is always set to 1b. Depending on the option, -// program ROM or program RAM, the following applies: -// Program ROM - The first sequencer instruction sets the bit to 0b. This is -// done immediately after the hardware reset is released. -// Program RAM - The sequencer must set the bit to 0b. As a valid firmware may -// not have been loaded, the sequencer is held in software reset after the -// hardware reset is released (the SEQCTRL.RESET bit is set to 1b). After the -// FW image is loaded and the Reset bit is cleared, the sequencer starts to -// execute the FW. The first instruction clears the run bit. -// In both cases a few clock cycles are needed before the first instruction is -// executed and the run bit state has been propagated. -#define PKA_FUNCTION_RUN 0x00008000 -#define PKA_FUNCTION_RUN_BITN 15 -#define PKA_FUNCTION_RUN_M 0x00008000 -#define PKA_FUNCTION_RUN_S 15 - -// Field: [14:12] SEQUENCER_OPERATIONS -// -// These bits select the complex sequencer operation to perform: -// 0x0: None -// 0x1: ExpMod-CRT -// 0x2: ECmontMUL -// 0x3: ECC-ADD (if available in firmware, otherwise reserved) -// 0x4: ExpMod-ACT2 -// 0x5: ECC-MUL (if available in firmware, otherwise reserved) -// 0x6: ExpMod-variable -// 0x7: ModInv (if available in firmware, otherwise reserved) -// The encoding of these operations is determined by sequencer firmware. -#define PKA_FUNCTION_SEQUENCER_OPERATIONS_W 3 -#define PKA_FUNCTION_SEQUENCER_OPERATIONS_M 0x00007000 -#define PKA_FUNCTION_SEQUENCER_OPERATIONS_S 12 - -// Field: [11] COPY -// -// Perform copy operation -#define PKA_FUNCTION_COPY 0x00000800 -#define PKA_FUNCTION_COPY_BITN 11 -#define PKA_FUNCTION_COPY_M 0x00000800 -#define PKA_FUNCTION_COPY_S 11 - -// Field: [10] COMPARE -// -// Perform compare operation -#define PKA_FUNCTION_COMPARE 0x00000400 -#define PKA_FUNCTION_COMPARE_BITN 10 -#define PKA_FUNCTION_COMPARE_M 0x00000400 -#define PKA_FUNCTION_COMPARE_S 10 - -// Field: [9] MODULO -// -// Perform modulo operation -#define PKA_FUNCTION_MODULO 0x00000200 -#define PKA_FUNCTION_MODULO_BITN 9 -#define PKA_FUNCTION_MODULO_M 0x00000200 -#define PKA_FUNCTION_MODULO_S 9 - -// Field: [8] DIVIDE -// -// Perform divide operation -#define PKA_FUNCTION_DIVIDE 0x00000100 -#define PKA_FUNCTION_DIVIDE_BITN 8 -#define PKA_FUNCTION_DIVIDE_M 0x00000100 -#define PKA_FUNCTION_DIVIDE_S 8 - -// Field: [7] LSHIFT -// -// Perform left shift operation -#define PKA_FUNCTION_LSHIFT 0x00000080 -#define PKA_FUNCTION_LSHIFT_BITN 7 -#define PKA_FUNCTION_LSHIFT_M 0x00000080 -#define PKA_FUNCTION_LSHIFT_S 7 - -// Field: [6] RSHIFT -// -// Perform right shift operation -#define PKA_FUNCTION_RSHIFT 0x00000040 -#define PKA_FUNCTION_RSHIFT_BITN 6 -#define PKA_FUNCTION_RSHIFT_M 0x00000040 -#define PKA_FUNCTION_RSHIFT_S 6 - -// Field: [5] SUBTRACT -// -// Perform subtract operation -#define PKA_FUNCTION_SUBTRACT 0x00000020 -#define PKA_FUNCTION_SUBTRACT_BITN 5 -#define PKA_FUNCTION_SUBTRACT_M 0x00000020 -#define PKA_FUNCTION_SUBTRACT_S 5 - -// Field: [4] ADD -// -// Perform add operation -#define PKA_FUNCTION_ADD 0x00000010 -#define PKA_FUNCTION_ADD_BITN 4 -#define PKA_FUNCTION_ADD_M 0x00000010 -#define PKA_FUNCTION_ADD_S 4 - -// Field: [3] MS_ONE -// -// Loads the location of the Most Significant one bit within the result word -// indicated in the MSW register into bits [4:0] of the DIVMSW.MSW_ADDRESS -// register - can only be used with basic PKCP operations, except for Divide, -// Modulo and Compare. -#define PKA_FUNCTION_MS_ONE 0x00000008 -#define PKA_FUNCTION_MS_ONE_BITN 3 -#define PKA_FUNCTION_MS_ONE_M 0x00000008 -#define PKA_FUNCTION_MS_ONE_S 3 - -// Field: [1] ADDSUB -// -// Perform combined add/subtract operation -#define PKA_FUNCTION_ADDSUB 0x00000002 -#define PKA_FUNCTION_ADDSUB_BITN 1 -#define PKA_FUNCTION_ADDSUB_M 0x00000002 -#define PKA_FUNCTION_ADDSUB_S 1 - -// Field: [0] MULTIPLY -// -// Perform multiply operation -#define PKA_FUNCTION_MULTIPLY 0x00000001 -#define PKA_FUNCTION_MULTIPLY_BITN 0 -#define PKA_FUNCTION_MULTIPLY_M 0x00000001 -#define PKA_FUNCTION_MULTIPLY_S 0 - -//***************************************************************************** -// -// Register: PKA_O_COMPARE -// -//***************************************************************************** -// Field: [2] A_GREATER_THAN_B -// -// Vector_A is greater than Vector_B -#define PKA_COMPARE_A_GREATER_THAN_B 0x00000004 -#define PKA_COMPARE_A_GREATER_THAN_B_BITN 2 -#define PKA_COMPARE_A_GREATER_THAN_B_M 0x00000004 -#define PKA_COMPARE_A_GREATER_THAN_B_S 2 - -// Field: [1] A_LESS_THAN_B -// -// Vector_A is less than Vector_B -#define PKA_COMPARE_A_LESS_THAN_B 0x00000002 -#define PKA_COMPARE_A_LESS_THAN_B_BITN 1 -#define PKA_COMPARE_A_LESS_THAN_B_M 0x00000002 -#define PKA_COMPARE_A_LESS_THAN_B_S 1 - -// Field: [0] A_EQUALS_B -// -// Vector_A is equal to Vector_B -#define PKA_COMPARE_A_EQUALS_B 0x00000001 -#define PKA_COMPARE_A_EQUALS_B_BITN 0 -#define PKA_COMPARE_A_EQUALS_B_M 0x00000001 -#define PKA_COMPARE_A_EQUALS_B_S 0 - -//***************************************************************************** -// -// Register: PKA_O_MSW -// -//***************************************************************************** -// Field: [15] RESULT_IS_ZERO -// -// The result vector is all zeroes, ignore the address returned in bits [10:0] -#define PKA_MSW_RESULT_IS_ZERO 0x00008000 -#define PKA_MSW_RESULT_IS_ZERO_BITN 15 -#define PKA_MSW_RESULT_IS_ZERO_M 0x00008000 -#define PKA_MSW_RESULT_IS_ZERO_S 15 - -// Field: [10:0] MSW_ADDRESS -// -// Address of the most-significant nonzero 32-bit word of the result vector in -// PKA RAM -#define PKA_MSW_MSW_ADDRESS_W 11 -#define PKA_MSW_MSW_ADDRESS_M 0x000007FF -#define PKA_MSW_MSW_ADDRESS_S 0 - -//***************************************************************************** -// -// Register: PKA_O_DIVMSW -// -//***************************************************************************** -// Field: [15] RESULT_IS_ZERO -// -// The result vector is all zeroes, ignore the address returned in bits [10:0] -#define PKA_DIVMSW_RESULT_IS_ZERO 0x00008000 -#define PKA_DIVMSW_RESULT_IS_ZERO_BITN 15 -#define PKA_DIVMSW_RESULT_IS_ZERO_M 0x00008000 -#define PKA_DIVMSW_RESULT_IS_ZERO_S 15 - -// Field: [10:0] MSW_ADDRESS -// -// Address of the most significant nonzero 32-bit word of the remainder result -// vector in PKA RAM -#define PKA_DIVMSW_MSW_ADDRESS_W 11 -#define PKA_DIVMSW_MSW_ADDRESS_M 0x000007FF -#define PKA_DIVMSW_MSW_ADDRESS_S 0 - -//***************************************************************************** -// -// Register: PKA_O_SEQCTRL -// -//***************************************************************************** -// Field: [31] RESET -// -// Option program ROM: Reset value = 0. Read/Write, reset value 0b (ZERO). -// Writing 1b resets the sequencer, write to 0b to restart operations again. As -// the reset value is 0b, the sequencer will automatically start operations -// executing from program ROM. This bit should always be written with zero and -// ignored when reading this register. -// -// Option Program RAM: Reset value =1. Read/Write, reset value 1b (ONE). When -// 1b, the sequencer is held in a reset state and the PKA_PROGRAM area is -// accessible for loading the sequencer program (while the PKA_DATA_RAM is -// inaccessible), write to 0b to (re)start sequencer operations and disable -// PKA_PROGRAM area accessibility (also enables the PKA_DATA_RAM accesses). -// Resetting the sequencer (in order to load other firmware) should only be -// done when the PKA Engine is not performing any operations (i.e. the -// FUNCTION.RUN bit should be zero). -#define PKA_SEQCTRL_RESET 0x80000000 -#define PKA_SEQCTRL_RESET_BITN 31 -#define PKA_SEQCTRL_RESET_M 0x80000000 -#define PKA_SEQCTRL_RESET_S 31 - -// Field: [15:8] SEQUENCER_STAT -// -// These read-only bits can be used by the sequencer to communicate status to -// the outside world. Bit [8] is also used as sequencer interrupt, with the -// complement of this bit ORed into the FUNCTION.RUN bit. This field should -// always be written with zeroes and ignored when reading this register. -#define PKA_SEQCTRL_SEQUENCER_STAT_W 8 -#define PKA_SEQCTRL_SEQUENCER_STAT_M 0x0000FF00 -#define PKA_SEQCTRL_SEQUENCER_STAT_S 8 - -// Field: [7:0] SW_CONTROL_STAT -// -// These bits can be used by software to trigger sequencer operations. External -// logic can set these bits by writing 1b, cannot reset them by writing 0b. The -// sequencer can reset these bits by writing 0b, cannot set them by writing 1b. -// Setting the FUNCTION.RUN bit together with a nonzero sequencer operations -// field automatically sets bit [0] here. This field should always be written -// with zeroes and ignored when reading this register. -#define PKA_SEQCTRL_SW_CONTROL_STAT_W 8 -#define PKA_SEQCTRL_SW_CONTROL_STAT_M 0x000000FF -#define PKA_SEQCTRL_SW_CONTROL_STAT_S 0 - -//***************************************************************************** -// -// Register: PKA_O_OPTIONS -// -//***************************************************************************** -// Field: [11] INT_MASKING -// -// Interrupt Masking -// 0x0: indicates that the main interrupt output (bit [1] of the interrupts -// output bus) is the direct complement of the run bit in the PKA_CONTROL -// register, 0x1 : indicates -// that interrupt masking logic is present for this output. -// Note: Reset value is undefined -#define PKA_OPTIONS_INT_MASKING 0x00000800 -#define PKA_OPTIONS_INT_MASKING_BITN 11 -#define PKA_OPTIONS_INT_MASKING_M 0x00000800 -#define PKA_OPTIONS_INT_MASKING_S 11 - -// Field: [10:8] PROTECTION_OPTION -// -// Protection Option -// 0x0: indicates no additional protection against side channel attacks, -// -// 0x1: indicates the SCAP option -// 0x2: Reserved -// 0x3: indicates the PROT option; -// Note: Reset value is undefined -#define PKA_OPTIONS_PROTECTION_OPTION_W 3 -#define PKA_OPTIONS_PROTECTION_OPTION_M 0x00000700 -#define PKA_OPTIONS_PROTECTION_OPTION_S 8 - -// Field: [7] PROGRAM_RAM -// -// Program RAM -// 0x1: indicates sequencer program storage in RAM, 0x0: -// indicates sequencer program storage in ROM. -// Note: Reset value is undefined -#define PKA_OPTIONS_PROGRAM_RAM 0x00000080 -#define PKA_OPTIONS_PROGRAM_RAM_BITN 7 -#define PKA_OPTIONS_PROGRAM_RAM_M 0x00000080 -#define PKA_OPTIONS_PROGRAM_RAM_S 7 - -// Field: [6:5] SEQUENCER_CONFIGURATION -// -// Sequencer Configuration -// 0x0: Reserved -// 0x1 : Indicates a standard sequencer -// 0x2: Reserved -// 0x3: Reserved -#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_W 2 -#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_M 0x00000060 -#define PKA_OPTIONS_SEQUENCER_CONFIGURATION_S 5 - -// Field: [1:0] PKCP_CONFIGURATION -// -// PKCP Configuration 0x0 -// : Reserved -// 0x1 : Indicates a PKCP with a 16x16 multiplier, 0x2: -// indicates a PKCP with a 32x32 multiplier, 0x3 : Reserved -// Note: Reset value is undefined. -#define PKA_OPTIONS_PKCP_CONFIGURATION_W 2 -#define PKA_OPTIONS_PKCP_CONFIGURATION_M 0x00000003 -#define PKA_OPTIONS_PKCP_CONFIGURATION_S 0 - -//***************************************************************************** -// -// Register: PKA_O_FWREV -// -//***************************************************************************** -// Field: [31:28] FW_CAPABILITIES -// -// Firmware Capabilities -// -// 4-bit binary encoding for the functionality implemented -// in the firmware. -// 0x0: indicates basic ModExp with/without CRT. 0x1: -// adds Modular Inversion, 0x2: value -// 2 adds Modular Inversion and ECC operations. -// 0x3-0xF : Reserved. -#define PKA_FWREV_FW_CAPABILITIES_W 4 -#define PKA_FWREV_FW_CAPABILITIES_M 0xF0000000 -#define PKA_FWREV_FW_CAPABILITIES_S 28 - -// Field: [27:24] MAJOR_FW_REVISION -// -// 4-bit binary encoding of the major firmware revision number -#define PKA_FWREV_MAJOR_FW_REVISION_W 4 -#define PKA_FWREV_MAJOR_FW_REVISION_M 0x0F000000 -#define PKA_FWREV_MAJOR_FW_REVISION_S 24 - -// Field: [23:20] MINOR_FW_REVISION -// -// 4-bit binary encoding of the minor firmware revision number -#define PKA_FWREV_MINOR_FW_REVISION_W 4 -#define PKA_FWREV_MINOR_FW_REVISION_M 0x00F00000 -#define PKA_FWREV_MINOR_FW_REVISION_S 20 - -// Field: [19:16] FW_PATCH_LEVEL -// -// 4-bit binary encoding of the firmware patch level, initial release will -// carry value zero -// Patches are used to remove bugs without changing the functionality or -// interface of a module. -#define PKA_FWREV_FW_PATCH_LEVEL_W 4 -#define PKA_FWREV_FW_PATCH_LEVEL_M 0x000F0000 -#define PKA_FWREV_FW_PATCH_LEVEL_S 16 - -//***************************************************************************** -// -// Register: PKA_O_HWREV -// -//***************************************************************************** -// Field: [27:24] MAJOR_HW_REVISION -// -// 4-bit binary encoding of the major hardware revision number -#define PKA_HWREV_MAJOR_HW_REVISION_W 4 -#define PKA_HWREV_MAJOR_HW_REVISION_M 0x0F000000 -#define PKA_HWREV_MAJOR_HW_REVISION_S 24 - -// Field: [23:20] MINOR_HW_REVISION -// -// 4-bit binary encoding of the minor hardware revision number -#define PKA_HWREV_MINOR_HW_REVISION_W 4 -#define PKA_HWREV_MINOR_HW_REVISION_M 0x00F00000 -#define PKA_HWREV_MINOR_HW_REVISION_S 20 - -// Field: [19:16] HW_PATCH_LEVEL -// -// 4-bit binary encoding of the hardware patch level, initial release will -// carry value zero -// Patches are used to remove bugs without changing the functionality or -// interface of a module. -#define PKA_HWREV_HW_PATCH_LEVEL_W 4 -#define PKA_HWREV_HW_PATCH_LEVEL_M 0x000F0000 -#define PKA_HWREV_HW_PATCH_LEVEL_S 16 - -// Field: [15:8] COMPLEMENT_OF_BASIC_EIP_NUMBER -// -// Bit-by-bit logic complement of bits [7:0], EIP-28 gives 0xE3 -#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_W 8 -#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_M 0x0000FF00 -#define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_S 8 - -// Field: [7:0] BASIC_EIP_NUMBER -// -// 8-bit binary encoding of the EIP number, EIP-28 gives 0x1C -#define PKA_HWREV_BASIC_EIP_NUMBER_W 8 -#define PKA_HWREV_BASIC_EIP_NUMBER_M 0x000000FF -#define PKA_HWREV_BASIC_EIP_NUMBER_S 0 - - -#endif // __PKA__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h deleted file mode 100644 index 159ea4c3b65..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_int.h +++ /dev/null @@ -1,157 +0,0 @@ -/****************************************************************************** -* Filename: hw_pka_int_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_PKA_INT_H__ -#define __HW_PKA_INT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// PKA_INT component -// -//***************************************************************************** -// PKA Options register -#define PKA_INT_O_OPTIONS 0x00000FF8 - -// PKA hardware revision register -#define PKA_INT_O_REVISION 0x00000FFC - -//***************************************************************************** -// -// Register: PKA_INT_O_OPTIONS -// -//***************************************************************************** -// Field: [10] AIC_PRESENT -// -// When set to '1', indicates that an EIP201 AIC is included in the EIP150 -#define PKA_INT_OPTIONS_AIC_PRESENT 0x00000400 -#define PKA_INT_OPTIONS_AIC_PRESENT_BITN 10 -#define PKA_INT_OPTIONS_AIC_PRESENT_M 0x00000400 -#define PKA_INT_OPTIONS_AIC_PRESENT_S 10 - -// Field: [9] EIP76_PRESENT -// -// When set to '1', indicates that the EIP76 TRNG is included in the EIP150 -#define PKA_INT_OPTIONS_EIP76_PRESENT 0x00000200 -#define PKA_INT_OPTIONS_EIP76_PRESENT_BITN 9 -#define PKA_INT_OPTIONS_EIP76_PRESENT_M 0x00000200 -#define PKA_INT_OPTIONS_EIP76_PRESENT_S 9 - -// Field: [8] EIP28_PRESENT -// -// When set to '1', indicates that the EIP28 PKA is included in the EIP150 -#define PKA_INT_OPTIONS_EIP28_PRESENT 0x00000100 -#define PKA_INT_OPTIONS_EIP28_PRESENT_BITN 8 -#define PKA_INT_OPTIONS_EIP28_PRESENT_M 0x00000100 -#define PKA_INT_OPTIONS_EIP28_PRESENT_S 8 - -// Field: [3] AXI_INTERFACE -// -// When set to '1', indicates that the EIP150 is equipped with a AXI interface -#define PKA_INT_OPTIONS_AXI_INTERFACE 0x00000008 -#define PKA_INT_OPTIONS_AXI_INTERFACE_BITN 3 -#define PKA_INT_OPTIONS_AXI_INTERFACE_M 0x00000008 -#define PKA_INT_OPTIONS_AXI_INTERFACE_S 3 - -// Field: [2] AHB_IS_ASYNC -// -// When set to '1', indicates that AHB interface is asynchronous Only -// applicable when AHB_INTERFACE is 1 -#define PKA_INT_OPTIONS_AHB_IS_ASYNC 0x00000004 -#define PKA_INT_OPTIONS_AHB_IS_ASYNC_BITN 2 -#define PKA_INT_OPTIONS_AHB_IS_ASYNC_M 0x00000004 -#define PKA_INT_OPTIONS_AHB_IS_ASYNC_S 2 - -// Field: [1] AHB_INTERFACE -// -// When set to '1', indicates that the EIP150 is equipped with a AHB interface -#define PKA_INT_OPTIONS_AHB_INTERFACE 0x00000002 -#define PKA_INT_OPTIONS_AHB_INTERFACE_BITN 1 -#define PKA_INT_OPTIONS_AHB_INTERFACE_M 0x00000002 -#define PKA_INT_OPTIONS_AHB_INTERFACE_S 1 - -// Field: [0] PLB_INTERFACE -// -// When set to '1', indicates that the EIP150 is equipped with a PLB interface -#define PKA_INT_OPTIONS_PLB_INTERFACE 0x00000001 -#define PKA_INT_OPTIONS_PLB_INTERFACE_BITN 0 -#define PKA_INT_OPTIONS_PLB_INTERFACE_M 0x00000001 -#define PKA_INT_OPTIONS_PLB_INTERFACE_S 0 - -//***************************************************************************** -// -// Register: PKA_INT_O_REVISION -// -//***************************************************************************** -// Field: [27:24] MAJOR_REVISION -// -// These bits encode the major version number for this module -#define PKA_INT_REVISION_MAJOR_REVISION_W 4 -#define PKA_INT_REVISION_MAJOR_REVISION_M 0x0F000000 -#define PKA_INT_REVISION_MAJOR_REVISION_S 24 - -// Field: [23:20] MINOR_REVISION -// -// These bits encode the minor version number for this module -#define PKA_INT_REVISION_MINOR_REVISION_W 4 -#define PKA_INT_REVISION_MINOR_REVISION_M 0x00F00000 -#define PKA_INT_REVISION_MINOR_REVISION_S 20 - -// Field: [19:16] PATCH_LEVEL -// -// These bits encode the hardware patch level for this module they start at -// value 0 on the first release -#define PKA_INT_REVISION_PATCH_LEVEL_W 4 -#define PKA_INT_REVISION_PATCH_LEVEL_M 0x000F0000 -#define PKA_INT_REVISION_PATCH_LEVEL_S 16 - -// Field: [15:8] COMP_EIP_NUM -// -// These bits simply contain the complement of bits [7:0], used by a driver to -// ascertain that the EIP150 revision register is indeed read -#define PKA_INT_REVISION_COMP_EIP_NUM_W 8 -#define PKA_INT_REVISION_COMP_EIP_NUM_M 0x0000FF00 -#define PKA_INT_REVISION_COMP_EIP_NUM_S 8 - -// Field: [7:0] EIP_NUM -// -// These bits encode the AuthenTec EIP number for the EIP150 -#define PKA_INT_REVISION_EIP_NUM_W 8 -#define PKA_INT_REVISION_EIP_NUM_M 0x000000FF -#define PKA_INT_REVISION_EIP_NUM_S 0 - - -#endif // __PKA_INT__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h deleted file mode 100644 index 3a9c12cd0ad..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_pka_ram.h +++ /dev/null @@ -1,48 +0,0 @@ -/****************************************************************************** -* Filename: hw_pka_ram_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_PKA_RAM_H__ -#define __HW_PKA_RAM_H__ - - -#define PKA_RAM_O_BANK0 0x00000000 -#define PKA_RAM_BANK0_BYTE_SIZE 2048 - -#define PKA_RAM_TOT_BYTE_SIZE 2048 - - - -#endif // __HW_PKA_RAM__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h deleted file mode 100644 index 1aa7f034ed2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_prcm.h +++ /dev/null @@ -1,2529 +0,0 @@ -/****************************************************************************** -* Filename: hw_prcm_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_PRCM_H__ -#define __HW_PRCM_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// PRCM component -// -//***************************************************************************** -// Infrastructure Clock Division Factor For Run Mode -#define PRCM_O_INFRCLKDIVR 0x00000000 - -// Infrastructure Clock Division Factor For Sleep Mode -#define PRCM_O_INFRCLKDIVS 0x00000004 - -// Infrastructure Clock Division Factor For DeepSleep Mode -#define PRCM_O_INFRCLKDIVDS 0x00000008 - -// MCU Voltage Domain Control -#define PRCM_O_VDCTL 0x0000000C - -// Load PRCM Settings To CLKCTRL Power Domain -#define PRCM_O_CLKLOADCTL 0x00000028 - -// RFC Clock Gate -#define PRCM_O_RFCCLKG 0x0000002C - -// VIMS Clock Gate -#define PRCM_O_VIMSCLKG 0x00000030 - -// SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes -#define PRCM_O_SECDMACLKGR 0x0000003C - -// SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode -#define PRCM_O_SECDMACLKGS 0x00000040 - -// SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode -#define PRCM_O_SECDMACLKGDS 0x00000044 - -// GPIO Clock Gate For Run And All Modes -#define PRCM_O_GPIOCLKGR 0x00000048 - -// GPIO Clock Gate For Sleep Mode -#define PRCM_O_GPIOCLKGS 0x0000004C - -// GPIO Clock Gate For Deep Sleep Mode -#define PRCM_O_GPIOCLKGDS 0x00000050 - -// GPT Clock Gate For Run And All Modes -#define PRCM_O_GPTCLKGR 0x00000054 - -// GPT Clock Gate For Sleep Mode -#define PRCM_O_GPTCLKGS 0x00000058 - -// GPT Clock Gate For Deep Sleep Mode -#define PRCM_O_GPTCLKGDS 0x0000005C - -// I2C Clock Gate For Run And All Modes -#define PRCM_O_I2CCLKGR 0x00000060 - -// I2C Clock Gate For Sleep Mode -#define PRCM_O_I2CCLKGS 0x00000064 - -// I2C Clock Gate For Deep Sleep Mode -#define PRCM_O_I2CCLKGDS 0x00000068 - -// UART Clock Gate For Run And All Modes -#define PRCM_O_UARTCLKGR 0x0000006C - -// UART Clock Gate For Sleep Mode -#define PRCM_O_UARTCLKGS 0x00000070 - -// UART Clock Gate For Deep Sleep Mode -#define PRCM_O_UARTCLKGDS 0x00000074 - -// SSI Clock Gate For Run And All Modes -#define PRCM_O_SSICLKGR 0x00000078 - -// SSI Clock Gate For Sleep Mode -#define PRCM_O_SSICLKGS 0x0000007C - -// SSI Clock Gate For Deep Sleep Mode -#define PRCM_O_SSICLKGDS 0x00000080 - -// I2S Clock Gate For Run And All Modes -#define PRCM_O_I2SCLKGR 0x00000084 - -// I2S Clock Gate For Sleep Mode -#define PRCM_O_I2SCLKGS 0x00000088 - -// I2S Clock Gate For Deep Sleep Mode -#define PRCM_O_I2SCLKGDS 0x0000008C - -// Internal -#define PRCM_O_SYSBUSCLKDIV 0x000000B4 - -// Internal -#define PRCM_O_CPUCLKDIV 0x000000B8 - -// Internal -#define PRCM_O_PERBUSCPUCLKDIV 0x000000BC - -// Internal -#define PRCM_O_PERDMACLKDIV 0x000000C4 - -// I2S Clock Control -#define PRCM_O_I2SBCLKSEL 0x000000C8 - -// GPT Scalar -#define PRCM_O_GPTCLKDIV 0x000000CC - -// I2S Clock Control -#define PRCM_O_I2SCLKCTL 0x000000D0 - -// MCLK Division Ratio -#define PRCM_O_I2SMCLKDIV 0x000000D4 - -// BCLK Division Ratio -#define PRCM_O_I2SBCLKDIV 0x000000D8 - -// WCLK Division Ratio -#define PRCM_O_I2SWCLKDIV 0x000000DC - -// RESET For SEC (PKA And TRNG And CRYPTO) And UDMA -#define PRCM_O_RESETSECDMA 0x000000F0 - -// RESET For GPIO IPs -#define PRCM_O_RESETGPIO 0x000000F4 - -// RESET For GPT Ips -#define PRCM_O_RESETGPT 0x000000F8 - -// RESET For I2C IPs -#define PRCM_O_RESETI2C 0x000000FC - -// RESET For UART IPs -#define PRCM_O_RESETUART 0x00000100 - -// RESET For SSI IPs -#define PRCM_O_RESETSSI 0x00000104 - -// RESET For I2S IP -#define PRCM_O_RESETI2S 0x00000108 - -// Power Domain Control -#define PRCM_O_PDCTL0 0x0000012C - -// RFC Power Domain Control -#define PRCM_O_PDCTL0RFC 0x00000130 - -// SERIAL Power Domain Control -#define PRCM_O_PDCTL0SERIAL 0x00000134 - -// PERIPH Power Domain Control -#define PRCM_O_PDCTL0PERIPH 0x00000138 - -// Power Domain Status -#define PRCM_O_PDSTAT0 0x00000140 - -// RFC Power Domain Status -#define PRCM_O_PDSTAT0RFC 0x00000144 - -// SERIAL Power Domain Status -#define PRCM_O_PDSTAT0SERIAL 0x00000148 - -// PERIPH Power Domain Status -#define PRCM_O_PDSTAT0PERIPH 0x0000014C - -// Power Domain Control -#define PRCM_O_PDCTL1 0x0000017C - -// CPU Power Domain Direct Control -#define PRCM_O_PDCTL1CPU 0x00000184 - -// RFC Power Domain Direct Control -#define PRCM_O_PDCTL1RFC 0x00000188 - -// VIMS Mode Direct Control -#define PRCM_O_PDCTL1VIMS 0x0000018C - -// Power Manager Status -#define PRCM_O_PDSTAT1 0x00000194 - -// BUS Power Domain Direct Read Status -#define PRCM_O_PDSTAT1BUS 0x00000198 - -// RFC Power Domain Direct Read Status -#define PRCM_O_PDSTAT1RFC 0x0000019C - -// CPU Power Domain Direct Read Status -#define PRCM_O_PDSTAT1CPU 0x000001A0 - -// VIMS Mode Direct Read Status -#define PRCM_O_PDSTAT1VIMS 0x000001A4 - -// Control To RFC -#define PRCM_O_RFCBITS 0x000001CC - -// Selected RFC Mode -#define PRCM_O_RFCMODESEL 0x000001D0 - -// Allowed RFC Modes -#define PRCM_O_RFCMODEHWOPT 0x000001D4 - -// Power Profiler Register -#define PRCM_O_PWRPROFSTAT 0x000001E0 - -// MCU SRAM configuration -#define PRCM_O_MCUSRAMCFG 0x0000021C - -// Memory Retention Control -#define PRCM_O_RAMRETEN 0x00000224 - -// Oscillator Interrupt Mask -#define PRCM_O_OSCIMSC 0x00000290 - -// Oscillator Raw Interrupt Status -#define PRCM_O_OSCRIS 0x00000294 - -// Oscillator Raw Interrupt Clear -#define PRCM_O_OSCICR 0x00000298 - -//***************************************************************************** -// -// Register: PRCM_O_INFRCLKDIVR -// -//***************************************************************************** -// Field: [1:0] RATIO -// -// Division rate for clocks driving modules in the MCU_AON domain when system -// CPU is in run mode. Division ratio affects both infrastructure clock and -// perbusull clock. -// ENUMs: -// DIV32 Divide by 32 -// DIV8 Divide by 8 -// DIV2 Divide by 2 -// DIV1 Divide by 1 -#define PRCM_INFRCLKDIVR_RATIO_W 2 -#define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVR_RATIO_S 0 -#define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_INFRCLKDIVS -// -//***************************************************************************** -// Field: [1:0] RATIO -// -// Division rate for clocks driving modules in the MCU_AON domain when system -// CPU is in sleep mode. Division ratio affects both infrastructure clock and -// perbusull clock. -// ENUMs: -// DIV32 Divide by 32 -// DIV8 Divide by 8 -// DIV2 Divide by 2 -// DIV1 Divide by 1 -#define PRCM_INFRCLKDIVS_RATIO_W 2 -#define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVS_RATIO_S 0 -#define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_INFRCLKDIVDS -// -//***************************************************************************** -// Field: [1:0] RATIO -// -// Division rate for clocks driving modules in the MCU_AON domain when system -// CPU is in seepsleep mode. Division ratio affects both infrastructure clock -// and perbusull clock. -// ENUMs: -// DIV32 Divide by 32 -// DIV8 Divide by 8 -// DIV2 Divide by 2 -// DIV1 Divide by 1 -#define PRCM_INFRCLKDIVDS_RATIO_W 2 -#define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 -#define PRCM_INFRCLKDIVDS_RATIO_S 0 -#define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 -#define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 -#define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 -#define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_VDCTL -// -//***************************************************************************** -// Field: [0] ULDO -// -// Request PMCTL to switch to uLDO. -// -// 0: No request -// 1: Assert request when possible -// -// The bit will have no effect before the following requirements are met: -// 1. PDCTL1.CPU_ON = 0 -// 2. PDCTL1.VIMS_MODE = x0 -// 3. SECDMACLKGDS.DMA_CLK_EN = 0 and S.CRYPTO_CLK_EN] = 0 and -// SECDMACLKGR.DMA_AM_CLK_EN = 0 (Note: Settings must be loaded with -// CLKLOADCTL.LOAD) -// 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 and SECDMACLKGR.CRYPTO_AM_CLK_EN = 0 -// (Note: Settings must be loaded with CLKLOADCTL.LOAD) -// 5. I2SCLKGDS.CLK_EN = 0 and I2SCLKGR.AM_CLK_EN = 0 (Note: Settings must be -// loaded with CLKLOADCTL.LOAD) -// 6. RFC do no request access to BUS -// 7. System CPU in deepsleep -#define PRCM_VDCTL_ULDO 0x00000001 -#define PRCM_VDCTL_ULDO_BITN 0 -#define PRCM_VDCTL_ULDO_M 0x00000001 -#define PRCM_VDCTL_ULDO_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_CLKLOADCTL -// -//***************************************************************************** -// Field: [1] LOAD_DONE -// -// Status of LOAD. -// Will be cleared to 0 when any of the registers requiring a LOAD is written -// to, and be set to 1 when a LOAD is done. -// Note that writing no change to a register will result in the LOAD_DONE being -// cleared. -// -// 0 : One or more registers have been write accessed after last LOAD -// 1 : No registers are write accessed after last LOAD -#define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 -#define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 -#define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 -#define PRCM_CLKLOADCTL_LOAD_DONE_S 1 - -// Field: [0] LOAD -// -// -// 0: No action -// 1: Load settings to CLKCTRL. Bit is HW cleared. -// -// Multiple changes to settings may be done before LOAD is written once so all -// changes takes place at the same time. LOAD can also be done after single -// setting updates. -// -// Registers that needs to be followed by LOAD before settings being applied -// are: -// - SYSBUSCLKDIV -// - CPUCLKDIV -// - PERBUSCPUCLKDIV -// - PERDMACLKDIV -// - PERBUSCPUCLKG -// - RFCCLKG -// - VIMSCLKG -// - SECDMACLKGR -// - SECDMACLKGS -// - SECDMACLKGDS -// - GPIOCLKGR -// - GPIOCLKGS -// - GPIOCLKGDS -// - GPTCLKGR -// - GPTCLKGS -// - GPTCLKGDS -// - GPTCLKDIV -// - I2CCLKGR -// - I2CCLKGS -// - I2CCLKGDS -// - SSICLKGR -// - SSICLKGS -// - SSICLKGDS -// - UARTCLKGR -// - UARTCLKGS -// - UARTCLKGDS -// - I2SCLKGR -// - I2SCLKGS -// - I2SCLKGDS -// - I2SBCLKSEL -// - I2SCLKCTL -// - I2SMCLKDIV -// - I2SBCLKDIV -// - I2SWCLKDIV -#define PRCM_CLKLOADCTL_LOAD 0x00000001 -#define PRCM_CLKLOADCTL_LOAD_BITN 0 -#define PRCM_CLKLOADCTL_LOAD_M 0x00000001 -#define PRCM_CLKLOADCTL_LOAD_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RFCCLKG -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable Clock -// 1: Enable clock if RFC power domain is on -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_RFCCLKG_CLK_EN 0x00000001 -#define PRCM_RFCCLKG_CLK_EN_BITN 0 -#define PRCM_RFCCLKG_CLK_EN_M 0x00000001 -#define PRCM_RFCCLKG_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_VIMSCLKG -// -//***************************************************************************** -// Field: [1:0] CLK_EN -// -// 00: Disable clock -// 01: Disable clock when SYSBUS clock is disabled -// 11: Enable clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_VIMSCLKG_CLK_EN_W 2 -#define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 -#define PRCM_VIMSCLKG_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_SECDMACLKGR -// -//***************************************************************************** -// Field: [24] DMA_AM_CLK_EN -// -// -// 0: No force -// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) -// -// Overrides DMA_CLK_EN, SECDMACLKGS.DMA_CLK_EN and SECDMACLKGDS.DMA_CLK_EN -// when enabled. -// -// SYSBUS clock will always run when enabled -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN 0x01000000 -#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_BITN 24 -#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_M 0x01000000 -#define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_S 24 - -// Field: [19] PKA_ZERIOZE_RESET_N -// -// Zeroization logic hardware reset. -// -// 0: pka_zeroize logic inactive. -// 1: pka_zeroize of memory is enabled. -// -// This register must remain active until the memory are completely zeroized -// which requires 256 periods on systembus clock. -#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N 0x00080000 -#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_BITN 19 -#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_M 0x00080000 -#define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_S 19 - -// Field: [18] PKA_AM_CLK_EN -// -// -// 0: No force -// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) -// -// Overrides PKA_CLK_EN, SECDMACLKGS.PKA_CLK_EN and SECDMACLKGDS.PKA_CLK_EN -// when enabled. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN 0x00040000 -#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_BITN 18 -#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_M 0x00040000 -#define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_S 18 - -// Field: [17] TRNG_AM_CLK_EN -// -// -// 0: No force -// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) -// -// Overrides TRNG_CLK_EN, SECDMACLKGS.TRNG_CLK_EN and SECDMACLKGDS.TRNG_CLK_EN -// when enabled. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN 0x00020000 -#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_BITN 17 -#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_M 0x00020000 -#define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_S 17 - -// Field: [16] CRYPTO_AM_CLK_EN -// -// -// 0: No force -// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) -// -// Overrides CRYPTO_CLK_EN, SECDMACLKGS.CRYPTO_CLK_EN and -// SECDMACLKGDS.CRYPTO_CLK_EN when enabled. -// -// SYSBUS clock will always run when enabled -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN 0x00010000 -#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_BITN 16 -#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_M 0x00010000 -#define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_S 16 - -// Field: [8] DMA_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by DMA_AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 - -// Field: [2] PKA_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by PKA_AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_PKA_CLK_EN 0x00000004 -#define PRCM_SECDMACLKGR_PKA_CLK_EN_BITN 2 -#define PRCM_SECDMACLKGR_PKA_CLK_EN_M 0x00000004 -#define PRCM_SECDMACLKGR_PKA_CLK_EN_S 2 - -// Field: [1] TRNG_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by TRNG_AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 - -// Field: [0] CRYPTO_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by CRYPTO_AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_SECDMACLKGS -// -//***************************************************************************** -// Field: [8] DMA_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 - -// Field: [2] PKA_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_PKA_CLK_EN 0x00000004 -#define PRCM_SECDMACLKGS_PKA_CLK_EN_BITN 2 -#define PRCM_SECDMACLKGS_PKA_CLK_EN_M 0x00000004 -#define PRCM_SECDMACLKGS_PKA_CLK_EN_S 2 - -// Field: [1] TRNG_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 - -// Field: [0] CRYPTO_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_SECDMACLKGDS -// -//***************************************************************************** -// Field: [8] DMA_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 -#define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 - -// Field: [2] PKA_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_PKA_CLK_EN 0x00000004 -#define PRCM_SECDMACLKGDS_PKA_CLK_EN_BITN 2 -#define PRCM_SECDMACLKGDS_PKA_CLK_EN_M 0x00000004 -#define PRCM_SECDMACLKGDS_PKA_CLK_EN_S 2 - -// Field: [1] TRNG_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// SYSBUS clock will always run when enabled -// -// Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 -#define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 - -// Field: [0] CRYPTO_CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// SYSBUS clock will always run when enabled -// -// Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 -#define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_GPIOCLKGR -// -//***************************************************************************** -// Field: [8] AM_CLK_EN -// -// -// 0: No force -// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) -// -// Overrides CLK_EN, GPIOCLKGS.CLK_EN and GPIOCLKGDS.CLK_EN when enabled. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGR_AM_CLK_EN 0x00000100 -#define PRCM_GPIOCLKGR_AM_CLK_EN_BITN 8 -#define PRCM_GPIOCLKGR_AM_CLK_EN_M 0x00000100 -#define PRCM_GPIOCLKGR_AM_CLK_EN_S 8 - -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGR_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGR_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGR_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_GPIOCLKGS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by GPIOCLKGR.AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGS_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGS_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_GPIOCLKGDS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by GPIOCLKGR.AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 -#define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 -#define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_GPIOCLKGDS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_GPTCLKGR -// -//***************************************************************************** -// Field: [11:8] AM_CLK_EN -// -// Each bit below has the following meaning: -// -// 0: No force -// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) -// -// Overrides CLK_EN, GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled. -// -// ENUMs can be combined -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// AM_GPT3 Enable clock for GPT3 in all modes -// AM_GPT2 Enable clock for GPT2 in all modes -// AM_GPT1 Enable clock for GPT1 in all modes -// AM_GPT0 Enable clock for GPT0 in all modes -#define PRCM_GPTCLKGR_AM_CLK_EN_W 4 -#define PRCM_GPTCLKGR_AM_CLK_EN_M 0x00000F00 -#define PRCM_GPTCLKGR_AM_CLK_EN_S 8 -#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT3 0x00000800 -#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT2 0x00000400 -#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT1 0x00000200 -#define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT0 0x00000100 - -// Field: [3:0] CLK_EN -// -// Each bit below has the following meaning: -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by AM_CLK_EN -// -// ENUMs can be combined -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// GPT3 Enable clock for GPT3 -// GPT2 Enable clock for GPT2 -// GPT1 Enable clock for GPT1 -// GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGR_CLK_EN_W 4 -#define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGR_CLK_EN_S 0 -#define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_GPTCLKGS -// -//***************************************************************************** -// Field: [3:0] CLK_EN -// -// Each bit below has the following meaning: -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by GPTCLKGR.AM_CLK_EN -// -// ENUMs can be combined -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// GPT3 Enable clock for GPT3 -// GPT2 Enable clock for GPT2 -// GPT1 Enable clock for GPT1 -// GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGS_CLK_EN_W 4 -#define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGS_CLK_EN_S 0 -#define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_GPTCLKGDS -// -//***************************************************************************** -// Field: [3:0] CLK_EN -// -// Each bit below has the following meaning: -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by GPTCLKGR.AM_CLK_EN -// -// ENUMs can be combined -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// GPT3 Enable clock for GPT3 -// GPT2 Enable clock for GPT2 -// GPT1 Enable clock for GPT1 -// GPT0 Enable clock for GPT0 -#define PRCM_GPTCLKGDS_CLK_EN_W 4 -#define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F -#define PRCM_GPTCLKGDS_CLK_EN_S 0 -#define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 -#define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 -#define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 -#define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_I2CCLKGR -// -//***************************************************************************** -// Field: [8] AM_CLK_EN -// -// -// 0: No force -// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) -// -// Overrides CLK_EN, I2CCLKGS.CLK_EN and I2CCLKGDS.CLK_EN when enabled. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGR_AM_CLK_EN 0x00000100 -#define PRCM_I2CCLKGR_AM_CLK_EN_BITN 8 -#define PRCM_I2CCLKGR_AM_CLK_EN_M 0x00000100 -#define PRCM_I2CCLKGR_AM_CLK_EN_S 8 - -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGR_CLK_EN 0x00000001 -#define PRCM_I2CCLKGR_CLK_EN_BITN 0 -#define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGR_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2CCLKGS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by I2CCLKGR.AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGS_CLK_EN 0x00000001 -#define PRCM_I2CCLKGS_CLK_EN_BITN 0 -#define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2CCLKGDS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by I2CCLKGR.AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2CCLKGDS_CLK_EN 0x00000001 -#define PRCM_I2CCLKGDS_CLK_EN_BITN 0 -#define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_I2CCLKGDS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_UARTCLKGR -// -//***************************************************************************** -// Field: [9:8] AM_CLK_EN -// -// -// 0: No force -// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) -// -// Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// AM_UART1 Enable clock for UART1 -// AM_UART0 Enable clock for UART0 -#define PRCM_UARTCLKGR_AM_CLK_EN_W 2 -#define PRCM_UARTCLKGR_AM_CLK_EN_M 0x00000300 -#define PRCM_UARTCLKGR_AM_CLK_EN_S 8 -#define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART1 0x00000200 -#define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART0 0x00000100 - -// Field: [1:0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// UART1 Enable clock for UART1 -// UART0 Enable clock for UART0 -#define PRCM_UARTCLKGR_CLK_EN_W 2 -#define PRCM_UARTCLKGR_CLK_EN_M 0x00000003 -#define PRCM_UARTCLKGR_CLK_EN_S 0 -#define PRCM_UARTCLKGR_CLK_EN_UART1 0x00000002 -#define PRCM_UARTCLKGR_CLK_EN_UART0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_UARTCLKGS -// -//***************************************************************************** -// Field: [1:0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by UARTCLKGR.AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// AM_UART1 Enable clock for UART1 -// AM_UART0 Enable clock for UART0 -#define PRCM_UARTCLKGS_CLK_EN_W 2 -#define PRCM_UARTCLKGS_CLK_EN_M 0x00000003 -#define PRCM_UARTCLKGS_CLK_EN_S 0 -#define PRCM_UARTCLKGS_CLK_EN_AM_UART1 0x00000002 -#define PRCM_UARTCLKGS_CLK_EN_AM_UART0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_UARTCLKGDS -// -//***************************************************************************** -// Field: [1:0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by UARTCLKGR.AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// AM_UART1 Enable clock for UART1 -// AM_UART0 Enable clock for UART0 -#define PRCM_UARTCLKGDS_CLK_EN_W 2 -#define PRCM_UARTCLKGDS_CLK_EN_M 0x00000003 -#define PRCM_UARTCLKGDS_CLK_EN_S 0 -#define PRCM_UARTCLKGDS_CLK_EN_AM_UART1 0x00000002 -#define PRCM_UARTCLKGDS_CLK_EN_AM_UART0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_SSICLKGR -// -//***************************************************************************** -// Field: [9:8] AM_CLK_EN -// -// -// 0: No force -// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) -// -// Overrides CLK_EN, SSICLKGS.CLK_EN and SSICLKGDS.CLK_EN when enabled. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// SSI1 Enable clock for SSI1 -// SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGR_AM_CLK_EN_W 2 -#define PRCM_SSICLKGR_AM_CLK_EN_M 0x00000300 -#define PRCM_SSICLKGR_AM_CLK_EN_S 8 -#define PRCM_SSICLKGR_AM_CLK_EN_SSI1 0x00000200 -#define PRCM_SSICLKGR_AM_CLK_EN_SSI0 0x00000100 - -// Field: [1:0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// SSI1 Enable clock for SSI1 -// SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGR_CLK_EN_W 2 -#define PRCM_SSICLKGR_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGR_CLK_EN_S 0 -#define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_SSICLKGS -// -//***************************************************************************** -// Field: [1:0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by SSICLKGR.AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// SSI1 Enable clock for SSI1 -// SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGS_CLK_EN_W 2 -#define PRCM_SSICLKGS_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGS_CLK_EN_S 0 -#define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_SSICLKGDS -// -//***************************************************************************** -// Field: [1:0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by SSICLKGR.AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -// ENUMs: -// SSI1 Enable clock for SSI1 -// SSI0 Enable clock for SSI0 -#define PRCM_SSICLKGDS_CLK_EN_W 2 -#define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 -#define PRCM_SSICLKGDS_CLK_EN_S 0 -#define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 -#define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_I2SCLKGR -// -//***************************************************************************** -// Field: [8] AM_CLK_EN -// -// -// 0: No force -// 1: Force clock on for all modes (Run, Sleep and Deep Sleep) -// -// Overrides CLK_EN, I2SCLKGS.CLK_EN and I2SCLKGDS.CLK_EN when enabled. -// SYSBUS clock will always run when enabled -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGR_AM_CLK_EN 0x00000100 -#define PRCM_I2SCLKGR_AM_CLK_EN_BITN 8 -#define PRCM_I2SCLKGR_AM_CLK_EN_M 0x00000100 -#define PRCM_I2SCLKGR_AM_CLK_EN_S 8 - -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGR_CLK_EN 0x00000001 -#define PRCM_I2SCLKGR_CLK_EN_BITN 0 -#define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGR_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2SCLKGS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// Can be forced on by I2SCLKGR.AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGS_CLK_EN 0x00000001 -#define PRCM_I2SCLKGS_CLK_EN_BITN 0 -#define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2SCLKGDS -// -//***************************************************************************** -// Field: [0] CLK_EN -// -// -// 0: Disable clock -// 1: Enable clock -// -// SYSBUS clock will always run when enabled -// -// Can be forced on by I2SCLKGR.AM_CLK_EN -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKGDS_CLK_EN 0x00000001 -#define PRCM_I2SCLKGDS_CLK_EN_BITN 0 -#define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 -#define PRCM_I2SCLKGDS_CLK_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_SYSBUSCLKDIV -// -//***************************************************************************** -// Field: [2:0] RATIO -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// DIV2 Internal. Only to be used through TI provided API. -// DIV1 Internal. Only to be used through TI provided API. -#define PRCM_SYSBUSCLKDIV_RATIO_W 3 -#define PRCM_SYSBUSCLKDIV_RATIO_M 0x00000007 -#define PRCM_SYSBUSCLKDIV_RATIO_S 0 -#define PRCM_SYSBUSCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_SYSBUSCLKDIV_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_CPUCLKDIV -// -//***************************************************************************** -// Field: [0] RATIO -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// DIV2 Internal. Only to be used through TI provided API. -// DIV1 Internal. Only to be used through TI provided API. -#define PRCM_CPUCLKDIV_RATIO 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_BITN 0 -#define PRCM_CPUCLKDIV_RATIO_M 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_S 0 -#define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_PERBUSCPUCLKDIV -// -//***************************************************************************** -// Field: [3:0] RATIO -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// DIV256 Internal. Only to be used through TI provided API. -// DIV128 Internal. Only to be used through TI provided API. -// DIV64 Internal. Only to be used through TI provided API. -// DIV32 Internal. Only to be used through TI provided API. -// DIV16 Internal. Only to be used through TI provided API. -// DIV8 Internal. Only to be used through TI provided API. -// DIV4 Internal. Only to be used through TI provided API. -// DIV2 Internal. Only to be used through TI provided API. -// DIV1 Internal. Only to be used through TI provided API. -#define PRCM_PERBUSCPUCLKDIV_RATIO_W 4 -#define PRCM_PERBUSCPUCLKDIV_RATIO_M 0x0000000F -#define PRCM_PERBUSCPUCLKDIV_RATIO_S 0 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV256 0x00000008 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV128 0x00000007 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV64 0x00000006 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV32 0x00000005 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV16 0x00000004 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV8 0x00000003 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV4 0x00000002 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_PERBUSCPUCLKDIV_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_PERDMACLKDIV -// -//***************************************************************************** -// Field: [3:0] RATIO -// -// Internal. Only to be used through TI provided API. -// ENUMs: -// DIV256 Internal. Only to be used through TI provided API. -// DIV128 Internal. Only to be used through TI provided API. -// DIV64 Internal. Only to be used through TI provided API. -// DIV32 Internal. Only to be used through TI provided API. -// DIV16 Internal. Only to be used through TI provided API. -// DIV8 Internal. Only to be used through TI provided API. -// DIV4 Internal. Only to be used through TI provided API. -// DIV2 Internal. Only to be used through TI provided API. -// DIV1 Internal. Only to be used through TI provided API. -#define PRCM_PERDMACLKDIV_RATIO_W 4 -#define PRCM_PERDMACLKDIV_RATIO_M 0x0000000F -#define PRCM_PERDMACLKDIV_RATIO_S 0 -#define PRCM_PERDMACLKDIV_RATIO_DIV256 0x00000008 -#define PRCM_PERDMACLKDIV_RATIO_DIV128 0x00000007 -#define PRCM_PERDMACLKDIV_RATIO_DIV64 0x00000006 -#define PRCM_PERDMACLKDIV_RATIO_DIV32 0x00000005 -#define PRCM_PERDMACLKDIV_RATIO_DIV16 0x00000004 -#define PRCM_PERDMACLKDIV_RATIO_DIV8 0x00000003 -#define PRCM_PERDMACLKDIV_RATIO_DIV4 0x00000002 -#define PRCM_PERDMACLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_PERDMACLKDIV_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_I2SBCLKSEL -// -//***************************************************************************** -// Field: [0] SRC -// -// BCLK source selector -// -// 0: Use external BCLK -// 1: Use internally generated clock -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SBCLKSEL_SRC 0x00000001 -#define PRCM_I2SBCLKSEL_SRC_BITN 0 -#define PRCM_I2SBCLKSEL_SRC_M 0x00000001 -#define PRCM_I2SBCLKSEL_SRC_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_GPTCLKDIV -// -//***************************************************************************** -// Field: [3:0] RATIO -// -// Scalar used for GPTs. The division rate will be constant and ungated for Run -// / Sleep / DeepSleep mode. For changes to take effect, CLKLOADCTL.LOAD -// needs to be written Other values are not supported. -// ENUMs: -// DIV256 Divide by 256 -// DIV128 Divide by 128 -// DIV64 Divide by 64 -// DIV32 Divide by 32 -// DIV16 Divide by 16 -// DIV8 Divide by 8 -// DIV4 Divide by 4 -// DIV2 Divide by 2 -// DIV1 Divide by 1 -#define PRCM_GPTCLKDIV_RATIO_W 4 -#define PRCM_GPTCLKDIV_RATIO_M 0x0000000F -#define PRCM_GPTCLKDIV_RATIO_S 0 -#define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 -#define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 -#define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 -#define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 -#define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 -#define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 -#define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 -#define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 -#define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_I2SCLKCTL -// -//***************************************************************************** -// Field: [3] SMPL_ON_POSEDGE -// -// On the I2S serial interface, data and WCLK is sampled and clocked out on -// opposite edges of BCLK. -// -// 0 - data and WCLK are sampled on the negative edge and clocked out on the -// positive edge. -// 1 - data and WCLK are sampled on the positive edge and clocked out on the -// negative edge. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 -#define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 - -// Field: [2:1] WCLK_PHASE -// -// Decides how the WCLK division ratio is calculated and used to generate -// different duty cycles (See I2SWCLKDIV.WDIV). -// -// 0: Single phase -// 1: Dual phase -// 2: User Defined -// 3: Reserved/Undefined -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 -#define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 -#define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 - -// Field: [0] EN -// -// -// 0: MCLK, BCLK and WCLK will be static low -// 1: Enables the generation of MCLK, BCLK and WCLK -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SCLKCTL_EN 0x00000001 -#define PRCM_I2SCLKCTL_EN_BITN 0 -#define PRCM_I2SCLKCTL_EN_M 0x00000001 -#define PRCM_I2SCLKCTL_EN_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2SMCLKDIV -// -//***************************************************************************** -// Field: [9:0] MDIV -// -// An unsigned factor of the division ratio used to generate MCLK [2-1024]: -// -// MCLK = MCUCLK/MDIV[Hz] -// MCUCLK is 48MHz. -// -// A value of 0 is interpreted as 1024. -// A value of 1 is invalid. -// If MDIV is odd the low phase of the clock is one MCUCLK period longer than -// the high phase. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SMCLKDIV_MDIV_W 10 -#define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF -#define PRCM_I2SMCLKDIV_MDIV_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2SBCLKDIV -// -//***************************************************************************** -// Field: [9:0] BDIV -// -// An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: -// -// BCLK = MCUCLK/BDIV[Hz] -// MCUCLK is 48MHz. -// -// A value of 0 is interpreted as 1024. -// A value of 1 is invalid. -// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock -// is one MCUCLK period longer than the high phase. -// If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the -// clock is one MCUCLK period longer than the low phase. -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SBCLKDIV_BDIV_W 10 -#define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF -#define PRCM_I2SBCLKDIV_BDIV_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_I2SWCLKDIV -// -//***************************************************************************** -// Field: [15:0] WDIV -// -// If I2SCLKCTL.WCLK_PHASE = 0, Single phase. -// WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK -// periods. -// -// WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] -// MCUCLK is 48MHz. -// -// If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. -// Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK -// periods. -// -// WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] -// -// If I2SCLKCTL.WCLK_PHASE = 2, User defined. -// WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] -// (unsigned, [1-255]) BCLK periods. -// -// WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] -// -// For changes to take effect, CLKLOADCTL.LOAD needs to be written -#define PRCM_I2SWCLKDIV_WDIV_W 16 -#define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF -#define PRCM_I2SWCLKDIV_WDIV_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RESETSECDMA -// -//***************************************************************************** -// Field: [8] DMA -// -// Write 1 to reset. HW cleared. -// Acess will only have effect when PERIPH power domain is on, -// PDSTAT0.PERIPH_ON = 1 -// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not -// activated while executing from flash. This means one cannot execute from -// flash when using the SW reset. -#define PRCM_RESETSECDMA_DMA 0x00000100 -#define PRCM_RESETSECDMA_DMA_BITN 8 -#define PRCM_RESETSECDMA_DMA_M 0x00000100 -#define PRCM_RESETSECDMA_DMA_S 8 - -// Field: [2] PKA -// -// Write 1 to reset. HW cleared. -// Acess will only have effect when PERIPH power domain is on, -// PDSTAT0.PERIPH_ON = 1 -// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not -// activated while executing from flash. This means one cannot execute from -// flash when using the SW reset. -#define PRCM_RESETSECDMA_PKA 0x00000004 -#define PRCM_RESETSECDMA_PKA_BITN 2 -#define PRCM_RESETSECDMA_PKA_M 0x00000004 -#define PRCM_RESETSECDMA_PKA_S 2 - -// Field: [1] TRNG -// -// Write 1 to reset. HW cleared. -// Acess will only have effect when PERIPH power domain is on, -// PDSTAT0.PERIPH_ON = 1 -// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not -// activated while executing from flash. This means one cannot execute from -// flash when using the SW reset. -#define PRCM_RESETSECDMA_TRNG 0x00000002 -#define PRCM_RESETSECDMA_TRNG_BITN 1 -#define PRCM_RESETSECDMA_TRNG_M 0x00000002 -#define PRCM_RESETSECDMA_TRNG_S 1 - -// Field: [0] CRYPTO -// -// Write 1 to reset. HW cleared. -// Acess will only have effect when PERIPH power domain is on, -// PDSTAT0.PERIPH_ON = 1 -// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not -// activated while executing from flash. This means one cannot execute from -// flash when using the SW reset. -#define PRCM_RESETSECDMA_CRYPTO 0x00000001 -#define PRCM_RESETSECDMA_CRYPTO_BITN 0 -#define PRCM_RESETSECDMA_CRYPTO_M 0x00000001 -#define PRCM_RESETSECDMA_CRYPTO_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RESETGPIO -// -//***************************************************************************** -// Field: [0] GPIO -// -// -// 0: No action -// 1: Reset GPIO. HW cleared. -// -// Acess will only have effect when PERIPH power domain is on, -// PDSTAT0.PERIPH_ON = 1 -// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not -// activated while executing from flash. This means one cannot execute from -// flash when using the SW reset. -#define PRCM_RESETGPIO_GPIO 0x00000001 -#define PRCM_RESETGPIO_GPIO_BITN 0 -#define PRCM_RESETGPIO_GPIO_M 0x00000001 -#define PRCM_RESETGPIO_GPIO_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RESETGPT -// -//***************************************************************************** -// Field: [0] GPT -// -// -// 0: No action -// 1: Reset all GPTs. HW cleared. -// -// Acess will only have effect when PERIPH power domain is on, -// PDSTAT0.PERIPH_ON = 1 -// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not -// activated while executing from flash. This means one cannot execute from -// flash when using the SW reset. -#define PRCM_RESETGPT_GPT 0x00000001 -#define PRCM_RESETGPT_GPT_BITN 0 -#define PRCM_RESETGPT_GPT_M 0x00000001 -#define PRCM_RESETGPT_GPT_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RESETI2C -// -//***************************************************************************** -// Field: [0] I2C -// -// -// 0: No action -// 1: Reset I2C. HW cleared. -// -// Acess will only have effect when SERIAL power domain is on, -// PDSTAT0.SERIAL_ON = 1 -// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not -// activated while executing from flash. This means one cannot execute from -// flash when using the SW reset. -#define PRCM_RESETI2C_I2C 0x00000001 -#define PRCM_RESETI2C_I2C_BITN 0 -#define PRCM_RESETI2C_I2C_M 0x00000001 -#define PRCM_RESETI2C_I2C_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RESETUART -// -//***************************************************************************** -// Field: [1] UART1 -// -// -// 0: No action -// 1: Reset UART1. HW cleared. -// -// Acess will only have effect when PERIPH power domain is on, -// PDSTAT0.PERIPH_ON = 1 -// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not -// activated while executing from flash. This means one cannot execute from -// flash when using the SW reset. -#define PRCM_RESETUART_UART1 0x00000002 -#define PRCM_RESETUART_UART1_BITN 1 -#define PRCM_RESETUART_UART1_M 0x00000002 -#define PRCM_RESETUART_UART1_S 1 - -// Field: [0] UART0 -// -// -// 0: No action -// 1: Reset UART0. HW cleared. -// -// Acess will only have effect when SERIAL power domain is on, -// PDSTAT0.SERIAL_ON = 1 -// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not -// activated while executing from flash. This means one cannot execute from -// flash when using the SW reset. -#define PRCM_RESETUART_UART0 0x00000001 -#define PRCM_RESETUART_UART0_BITN 0 -#define PRCM_RESETUART_UART0_M 0x00000001 -#define PRCM_RESETUART_UART0_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RESETSSI -// -//***************************************************************************** -// Field: [1:0] SSI -// -// SSI 0: -// -// 0: No action -// 1: Reset SSI. HW cleared. -// -// Acess will only have effect when SERIAL power domain is on, -// PDSTAT0.SERIAL_ON = 1 -// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not -// activated while executing from flash. This means one cannot execute from -// flash when using the SW reset. -// -// SSI 1: -// -// 0: No action -// 1: Reset SSI. HW cleared. -// -// Acess will only have effect when PERIPH power domain is on, -// PDSTAT0.PERIPH_ON = 1 -// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not -// activated while executing from flash. This means one cannot execute from -// flash when using the SW reset. -#define PRCM_RESETSSI_SSI_W 2 -#define PRCM_RESETSSI_SSI_M 0x00000003 -#define PRCM_RESETSSI_SSI_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RESETI2S -// -//***************************************************************************** -// Field: [0] I2S -// -// -// 0: No action -// 1: Reset module. HW cleared. -// -// Acess will only have effect when PERIPH power domain is on, -// PDSTAT0.PERIPH_ON = 1 -// Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not -// activated while executing from flash. This means one cannot execute from -// flash when using the SW reset. -#define PRCM_RESETI2S_I2S 0x00000001 -#define PRCM_RESETI2S_I2S_BITN 0 -#define PRCM_RESETI2S_I2S_M 0x00000001 -#define PRCM_RESETI2S_I2S_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL0 -// -//***************************************************************************** -// Field: [2] PERIPH_ON -// -// PERIPH Power domain. -// -// 0: PERIPH power domain is powered down -// 1: PERIPH power domain is powered up -#define PRCM_PDCTL0_PERIPH_ON 0x00000004 -#define PRCM_PDCTL0_PERIPH_ON_BITN 2 -#define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 -#define PRCM_PDCTL0_PERIPH_ON_S 2 - -// Field: [1] SERIAL_ON -// -// SERIAL Power domain. -// -// 0: SERIAL power domain is powered down -// 1: SERIAL power domain is powered up -#define PRCM_PDCTL0_SERIAL_ON 0x00000002 -#define PRCM_PDCTL0_SERIAL_ON_BITN 1 -#define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 -#define PRCM_PDCTL0_SERIAL_ON_S 1 - -// Field: [0] RFC_ON -// -// -// 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 -// 1: RFC power domain powered on -#define PRCM_PDCTL0_RFC_ON 0x00000001 -#define PRCM_PDCTL0_RFC_ON_BITN 0 -#define PRCM_PDCTL0_RFC_ON_M 0x00000001 -#define PRCM_PDCTL0_RFC_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL0RFC -// -//***************************************************************************** -// Field: [0] ON -// -// Alias for PDCTL0.RFC_ON -#define PRCM_PDCTL0RFC_ON 0x00000001 -#define PRCM_PDCTL0RFC_ON_BITN 0 -#define PRCM_PDCTL0RFC_ON_M 0x00000001 -#define PRCM_PDCTL0RFC_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL0SERIAL -// -//***************************************************************************** -// Field: [0] ON -// -// Alias for PDCTL0.SERIAL_ON -#define PRCM_PDCTL0SERIAL_ON 0x00000001 -#define PRCM_PDCTL0SERIAL_ON_BITN 0 -#define PRCM_PDCTL0SERIAL_ON_M 0x00000001 -#define PRCM_PDCTL0SERIAL_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL0PERIPH -// -//***************************************************************************** -// Field: [0] ON -// -// Alias for PDCTL0.PERIPH_ON -#define PRCM_PDCTL0PERIPH_ON 0x00000001 -#define PRCM_PDCTL0PERIPH_ON_BITN 0 -#define PRCM_PDCTL0PERIPH_ON_M 0x00000001 -#define PRCM_PDCTL0PERIPH_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT0 -// -//***************************************************************************** -// Field: [2] PERIPH_ON -// -// PERIPH Power domain. -// -// 0: Domain may be powered down -// 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_PERIPH_ON 0x00000004 -#define PRCM_PDSTAT0_PERIPH_ON_BITN 2 -#define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 -#define PRCM_PDSTAT0_PERIPH_ON_S 2 - -// Field: [1] SERIAL_ON -// -// SERIAL Power domain. -// -// 0: Domain may be powered down -// 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_SERIAL_ON 0x00000002 -#define PRCM_PDSTAT0_SERIAL_ON_BITN 1 -#define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 -#define PRCM_PDSTAT0_SERIAL_ON_S 1 - -// Field: [0] RFC_ON -// -// RFC Power domain -// -// 0: Domain may be powered down -// 1: Domain powered up (guaranteed) -#define PRCM_PDSTAT0_RFC_ON 0x00000001 -#define PRCM_PDSTAT0_RFC_ON_BITN 0 -#define PRCM_PDSTAT0_RFC_ON_M 0x00000001 -#define PRCM_PDSTAT0_RFC_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT0RFC -// -//***************************************************************************** -// Field: [0] ON -// -// Alias for PDSTAT0.RFC_ON -#define PRCM_PDSTAT0RFC_ON 0x00000001 -#define PRCM_PDSTAT0RFC_ON_BITN 0 -#define PRCM_PDSTAT0RFC_ON_M 0x00000001 -#define PRCM_PDSTAT0RFC_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT0SERIAL -// -//***************************************************************************** -// Field: [0] ON -// -// Alias for PDSTAT0.SERIAL_ON -#define PRCM_PDSTAT0SERIAL_ON 0x00000001 -#define PRCM_PDSTAT0SERIAL_ON_BITN 0 -#define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 -#define PRCM_PDSTAT0SERIAL_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT0PERIPH -// -//***************************************************************************** -// Field: [0] ON -// -// Alias for PDSTAT0.PERIPH_ON -#define PRCM_PDSTAT0PERIPH_ON 0x00000001 -#define PRCM_PDSTAT0PERIPH_ON_BITN 0 -#define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 -#define PRCM_PDSTAT0PERIPH_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL1 -// -//***************************************************************************** -// Field: [4:3] VIMS_MODE -// -// -// 00: VIMS power domain is only powered when CPU power domain is powered. -// 01: VIMS power domain is powered whenever the BUS power domain is powered. -// 1X: Block power up of VIMS power domain at next wake up. This mode only has -// effect when VIMS power domain is not powered. Used for Autonomous RF Core. -#define PRCM_PDCTL1_VIMS_MODE_W 2 -#define PRCM_PDCTL1_VIMS_MODE_M 0x00000018 -#define PRCM_PDCTL1_VIMS_MODE_S 3 - -// Field: [2] RFC_ON -// -// 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1: RFC power -// domain powered on Bit shall be used by RFC in autonomous mode but there is -// no HW restrictions fom system CPU to access the bit. -#define PRCM_PDCTL1_RFC_ON 0x00000004 -#define PRCM_PDCTL1_RFC_ON_BITN 2 -#define PRCM_PDCTL1_RFC_ON_M 0x00000004 -#define PRCM_PDCTL1_RFC_ON_S 2 - -// Field: [1] CPU_ON -// -// -// 0: Causes a power down of the CPU power domain when system CPU indicates it -// is idle. -// 1: Initiates power-on of the CPU power domain. -// -// This bit is automatically set by a WIC power-on event. -#define PRCM_PDCTL1_CPU_ON 0x00000002 -#define PRCM_PDCTL1_CPU_ON_BITN 1 -#define PRCM_PDCTL1_CPU_ON_M 0x00000002 -#define PRCM_PDCTL1_CPU_ON_S 1 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL1CPU -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDCTL1.CPU_ON -#define PRCM_PDCTL1CPU_ON 0x00000001 -#define PRCM_PDCTL1CPU_ON_BITN 0 -#define PRCM_PDCTL1CPU_ON_M 0x00000001 -#define PRCM_PDCTL1CPU_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL1RFC -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDCTL1.RFC_ON -#define PRCM_PDCTL1RFC_ON 0x00000001 -#define PRCM_PDCTL1RFC_ON_BITN 0 -#define PRCM_PDCTL1RFC_ON_M 0x00000001 -#define PRCM_PDCTL1RFC_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDCTL1VIMS -// -//***************************************************************************** -// Field: [1:0] MODE -// -// This is an alias for PDCTL1.VIMS_MODE -#define PRCM_PDCTL1VIMS_MODE_W 2 -#define PRCM_PDCTL1VIMS_MODE_M 0x00000003 -#define PRCM_PDCTL1VIMS_MODE_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT1 -// -//***************************************************************************** -// Field: [4] BUS_ON -// -// -// 0: BUS domain not accessible -// 1: BUS domain is currently accessible -#define PRCM_PDSTAT1_BUS_ON 0x00000010 -#define PRCM_PDSTAT1_BUS_ON_BITN 4 -#define PRCM_PDSTAT1_BUS_ON_M 0x00000010 -#define PRCM_PDSTAT1_BUS_ON_S 4 - -// Field: [3] VIMS_ON -// -// -// 0: VIMS domain not accessible -// 1: VIMS domain is currently accessible -#define PRCM_PDSTAT1_VIMS_ON 0x00000008 -#define PRCM_PDSTAT1_VIMS_ON_BITN 3 -#define PRCM_PDSTAT1_VIMS_ON_M 0x00000008 -#define PRCM_PDSTAT1_VIMS_ON_S 3 - -// Field: [2] RFC_ON -// -// -// 0: RFC domain not accessible -// 1: RFC domain is currently accessible -#define PRCM_PDSTAT1_RFC_ON 0x00000004 -#define PRCM_PDSTAT1_RFC_ON_BITN 2 -#define PRCM_PDSTAT1_RFC_ON_M 0x00000004 -#define PRCM_PDSTAT1_RFC_ON_S 2 - -// Field: [1] CPU_ON -// -// -// 0: CPU and BUS domain not accessible -// 1: CPU and BUS domains are both currently accessible -#define PRCM_PDSTAT1_CPU_ON 0x00000002 -#define PRCM_PDSTAT1_CPU_ON_BITN 1 -#define PRCM_PDSTAT1_CPU_ON_M 0x00000002 -#define PRCM_PDSTAT1_CPU_ON_S 1 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT1BUS -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDSTAT1.BUS_ON -#define PRCM_PDSTAT1BUS_ON 0x00000001 -#define PRCM_PDSTAT1BUS_ON_BITN 0 -#define PRCM_PDSTAT1BUS_ON_M 0x00000001 -#define PRCM_PDSTAT1BUS_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT1RFC -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDSTAT1.RFC_ON -#define PRCM_PDSTAT1RFC_ON 0x00000001 -#define PRCM_PDSTAT1RFC_ON_BITN 0 -#define PRCM_PDSTAT1RFC_ON_M 0x00000001 -#define PRCM_PDSTAT1RFC_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT1CPU -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDSTAT1.CPU_ON -#define PRCM_PDSTAT1CPU_ON 0x00000001 -#define PRCM_PDSTAT1CPU_ON_BITN 0 -#define PRCM_PDSTAT1CPU_ON_M 0x00000001 -#define PRCM_PDSTAT1CPU_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_PDSTAT1VIMS -// -//***************************************************************************** -// Field: [0] ON -// -// This is an alias for PDSTAT1.VIMS_ON -#define PRCM_PDSTAT1VIMS_ON 0x00000001 -#define PRCM_PDSTAT1VIMS_ON_BITN 0 -#define PRCM_PDSTAT1VIMS_ON_M 0x00000001 -#define PRCM_PDSTAT1VIMS_ON_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RFCBITS -// -//***************************************************************************** -// Field: [31:0] READ -// -// Control bits for RFC. The RF core CPE processor will automatically check -// this register when it boots, and it can be used to immediately instruct CPE -// to perform some tasks at its start-up. The supported functionality is -// ROM-defined and may vary. See the technical reference manual for more -// details. -#define PRCM_RFCBITS_READ_W 32 -#define PRCM_RFCBITS_READ_M 0xFFFFFFFF -#define PRCM_RFCBITS_READ_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RFCMODESEL -// -//***************************************************************************** -// Field: [2:0] CURR -// -// Selects the set of commands that the RFC will accept. Only modes permitted -// by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for -// details. -// ENUMs: -// MODE7 Select Mode 7 -// MODE6 Select Mode 6 -// MODE5 Select Mode 5 -// MODE4 Select Mode 4 -// MODE3 Select Mode 3 -// MODE2 Select Mode 2 -// MODE1 Select Mode 1 -// MODE0 Select Mode 0 -#define PRCM_RFCMODESEL_CURR_W 3 -#define PRCM_RFCMODESEL_CURR_M 0x00000007 -#define PRCM_RFCMODESEL_CURR_S 0 -#define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 -#define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 -#define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 -#define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 -#define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 -#define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 -#define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 -#define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 - -//***************************************************************************** -// -// Register: PRCM_O_RFCMODEHWOPT -// -//***************************************************************************** -// Field: [7:0] AVAIL -// -// Permitted RFC modes. More than one mode can be permitted. -// ENUMs: -// MODE7 Mode 7 permitted -// MODE6 Mode 6 permitted -// MODE5 Mode 5 permitted -// MODE4 Mode 4 permitted -// MODE3 Mode 3 permitted -// MODE2 Mode 2 permitted -// MODE1 Mode 1 permitted -// MODE0 Mode 0 permitted -#define PRCM_RFCMODEHWOPT_AVAIL_W 8 -#define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF -#define PRCM_RFCMODEHWOPT_AVAIL_S 0 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 -#define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 - -//***************************************************************************** -// -// Register: PRCM_O_PWRPROFSTAT -// -//***************************************************************************** -// Field: [7:0] VALUE -// -// SW can use these bits to timestamp the application. These bits are also -// available through the testtap and can thus be used by the emulator to -// profile in real time. -#define PRCM_PWRPROFSTAT_VALUE_W 8 -#define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF -#define PRCM_PWRPROFSTAT_VALUE_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_MCUSRAMCFG -// -//***************************************************************************** -// Field: [5] BM_OFF -// -// Burst Mode disable -// -// 0: Burst Mode enabled. -// 1: Burst Mode off. -#define PRCM_MCUSRAMCFG_BM_OFF 0x00000020 -#define PRCM_MCUSRAMCFG_BM_OFF_BITN 5 -#define PRCM_MCUSRAMCFG_BM_OFF_M 0x00000020 -#define PRCM_MCUSRAMCFG_BM_OFF_S 5 - -// Field: [4] PAGE -// -// Page Mode select -// -// 0: Page Mode disabled. Memory works in standard mode -// 1: Page Mode enabled. Only one half of butterfly array selected. Page Mode -// will select either LSB half or MSB half of the word based on PGS setting. -// -// This mode can be used for additional power saving -#define PRCM_MCUSRAMCFG_PAGE 0x00000010 -#define PRCM_MCUSRAMCFG_PAGE_BITN 4 -#define PRCM_MCUSRAMCFG_PAGE_M 0x00000010 -#define PRCM_MCUSRAMCFG_PAGE_S 4 - -// Field: [3] PGS -// -// 0: Select LSB half of word during Page Mode, PAGE = 1 -// 1: Select MSB half of word during Page Mode, PAGE = 1 -#define PRCM_MCUSRAMCFG_PGS 0x00000008 -#define PRCM_MCUSRAMCFG_PGS_BITN 3 -#define PRCM_MCUSRAMCFG_PGS_M 0x00000008 -#define PRCM_MCUSRAMCFG_PGS_S 3 - -// Field: [2] BM -// -// Burst Mode Enable -// -// 0: Burst Mode Disable. Memory works in standard mode. -// 1: Burst Mode Enable -// -// When in Burst Mode bitline precharge and wordline firing depends on PCH_F -// and PCH_L. -// Burst Mode results in reduction in active power. -#define PRCM_MCUSRAMCFG_BM 0x00000004 -#define PRCM_MCUSRAMCFG_BM_BITN 2 -#define PRCM_MCUSRAMCFG_BM_M 0x00000004 -#define PRCM_MCUSRAMCFG_BM_S 2 - -// Field: [1] PCH_F -// -// 0: No bitline precharge in second half of cycle -// 1: Bitline precharge in second half of cycle when in Burst Mode, BM = 1 -#define PRCM_MCUSRAMCFG_PCH_F 0x00000002 -#define PRCM_MCUSRAMCFG_PCH_F_BITN 1 -#define PRCM_MCUSRAMCFG_PCH_F_M 0x00000002 -#define PRCM_MCUSRAMCFG_PCH_F_S 1 - -// Field: [0] PCH_L -// -// 0: No bitline precharge in first half of cycle -// 1: Bitline precharge in first half of cycle when in Burst Mode, BM = 1 -#define PRCM_MCUSRAMCFG_PCH_L 0x00000001 -#define PRCM_MCUSRAMCFG_PCH_L_BITN 0 -#define PRCM_MCUSRAMCFG_PCH_L_M 0x00000001 -#define PRCM_MCUSRAMCFG_PCH_L_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_RAMRETEN -// -//***************************************************************************** -// Field: [3] RFCULL -// -// 0: Retention for RFC ULL SRAM disabled -// 1: Retention for RFC ULL SRAM enabled -// -// Memories controlled: -// CPEULLRAM -#define PRCM_RAMRETEN_RFCULL 0x00000008 -#define PRCM_RAMRETEN_RFCULL_BITN 3 -#define PRCM_RAMRETEN_RFCULL_M 0x00000008 -#define PRCM_RAMRETEN_RFCULL_S 3 - -// Field: [2] RFC -// -// 0: Retention for RFC SRAM disabled -// 1: Retention for RFC SRAM enabled -// -// Memories controlled: CPERAM MCERAM RFERAM DSBRAM -#define PRCM_RAMRETEN_RFC 0x00000004 -#define PRCM_RAMRETEN_RFC_BITN 2 -#define PRCM_RAMRETEN_RFC_M 0x00000004 -#define PRCM_RAMRETEN_RFC_S 2 - -// Field: [1:0] VIMS -// -// -// 0: Memory retention disabled -// 1: Memory retention enabled -// -// Bit 0: VIMS_TRAM -// Bit 1: VIMS_CRAM -// -// Legal modes depend on settings in VIMS:CTL.MODE -// -// 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to -// CACHE or SPLIT mode after waking up again -// 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in -// GPRAM mode after wake up, alternatively select OFF mode first and then CACHE -// or SPILT mode. -// 10: Illegal mode -// 11: No restrictions -#define PRCM_RAMRETEN_VIMS_W 2 -#define PRCM_RAMRETEN_VIMS_M 0x00000003 -#define PRCM_RAMRETEN_VIMS_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_OSCIMSC -// -//***************************************************************************** -// Field: [7] HFSRCPENDIM -// -// 0: Disable interrupt generation when HFSRCPEND is qualified -// 1: Enable interrupt generation when HFSRCPEND is qualified -#define PRCM_OSCIMSC_HFSRCPENDIM 0x00000080 -#define PRCM_OSCIMSC_HFSRCPENDIM_BITN 7 -#define PRCM_OSCIMSC_HFSRCPENDIM_M 0x00000080 -#define PRCM_OSCIMSC_HFSRCPENDIM_S 7 - -// Field: [6] LFSRCDONEIM -// -// 0: Disable interrupt generation when LFSRCDONE is qualified -// 1: Enable interrupt generation when LFSRCDONE is qualified -#define PRCM_OSCIMSC_LFSRCDONEIM 0x00000040 -#define PRCM_OSCIMSC_LFSRCDONEIM_BITN 6 -#define PRCM_OSCIMSC_LFSRCDONEIM_M 0x00000040 -#define PRCM_OSCIMSC_LFSRCDONEIM_S 6 - -// Field: [5] XOSCDLFIM -// -// 0: Disable interrupt generation when XOSCDLF is qualified -// 1: Enable interrupt generation when XOSCDLF is qualified -#define PRCM_OSCIMSC_XOSCDLFIM 0x00000020 -#define PRCM_OSCIMSC_XOSCDLFIM_BITN 5 -#define PRCM_OSCIMSC_XOSCDLFIM_M 0x00000020 -#define PRCM_OSCIMSC_XOSCDLFIM_S 5 - -// Field: [4] XOSCLFIM -// -// 0: Disable interrupt generation when XOSCLF is qualified -// 1: Enable interrupt generation when XOSCLF is qualified -#define PRCM_OSCIMSC_XOSCLFIM 0x00000010 -#define PRCM_OSCIMSC_XOSCLFIM_BITN 4 -#define PRCM_OSCIMSC_XOSCLFIM_M 0x00000010 -#define PRCM_OSCIMSC_XOSCLFIM_S 4 - -// Field: [3] RCOSCDLFIM -// -// 0: Disable interrupt generation when RCOSCDLF is qualified -// 1: Enable interrupt generation when RCOSCDLF is qualified -#define PRCM_OSCIMSC_RCOSCDLFIM 0x00000008 -#define PRCM_OSCIMSC_RCOSCDLFIM_BITN 3 -#define PRCM_OSCIMSC_RCOSCDLFIM_M 0x00000008 -#define PRCM_OSCIMSC_RCOSCDLFIM_S 3 - -// Field: [2] RCOSCLFIM -// -// 0: Disable interrupt generation when RCOSCLF is qualified -// 1: Enable interrupt generation when RCOSCLF is qualified -#define PRCM_OSCIMSC_RCOSCLFIM 0x00000004 -#define PRCM_OSCIMSC_RCOSCLFIM_BITN 2 -#define PRCM_OSCIMSC_RCOSCLFIM_M 0x00000004 -#define PRCM_OSCIMSC_RCOSCLFIM_S 2 - -// Field: [1] XOSCHFIM -// -// 0: Disable interrupt generation when XOSCHF is qualified -// 1: Enable interrupt generation when XOSCHF is qualified -#define PRCM_OSCIMSC_XOSCHFIM 0x00000002 -#define PRCM_OSCIMSC_XOSCHFIM_BITN 1 -#define PRCM_OSCIMSC_XOSCHFIM_M 0x00000002 -#define PRCM_OSCIMSC_XOSCHFIM_S 1 - -// Field: [0] RCOSCHFIM -// -// 0: Disable interrupt generation when RCOSCHF is qualified -// 1: Enable interrupt generation when RCOSCHF is qualified -#define PRCM_OSCIMSC_RCOSCHFIM 0x00000001 -#define PRCM_OSCIMSC_RCOSCHFIM_BITN 0 -#define PRCM_OSCIMSC_RCOSCHFIM_M 0x00000001 -#define PRCM_OSCIMSC_RCOSCHFIM_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_OSCRIS -// -//***************************************************************************** -// Field: [7] HFSRCPENDRIS -// -// 0: HFSRCPEND has not been qualified -// 1: HFSRCPEND has been qualified since last clear -// -// Interrupt is qualified regardless of OSCIMSC.HFSRCPENDIM setting. The order -// of qualifying raw interrupt and enable of interrupt mask is indifferent for -// generating an OSC Interrupt. -// -// Set by HW. Cleared by writing to OSCICR.HFSRCPENDC -#define PRCM_OSCRIS_HFSRCPENDRIS 0x00000080 -#define PRCM_OSCRIS_HFSRCPENDRIS_BITN 7 -#define PRCM_OSCRIS_HFSRCPENDRIS_M 0x00000080 -#define PRCM_OSCRIS_HFSRCPENDRIS_S 7 - -// Field: [6] LFSRCDONERIS -// -// 0: LFSRCDONE has not been qualified -// 1: LFSRCDONE has been qualified since last clear -// -// Interrupt is qualified regardless of OSCIMSC.LFSRCDONEIM setting. The order -// of qualifying raw interrupt and enable of interrupt mask is indifferent for -// generating an OSC Interrupt. -// -// Set by HW. Cleared by writing to OSCICR.LFSRCDONEC -#define PRCM_OSCRIS_LFSRCDONERIS 0x00000040 -#define PRCM_OSCRIS_LFSRCDONERIS_BITN 6 -#define PRCM_OSCRIS_LFSRCDONERIS_M 0x00000040 -#define PRCM_OSCRIS_LFSRCDONERIS_S 6 - -// Field: [5] XOSCDLFRIS -// -// 0: XOSCDLF has not been qualified -// 1: XOSCDLF has been qualified since last clear. -// -// Interrupt is qualified regardless of OSCIMSC.XOSCDLFIM setting. The order of -// qualifying raw interrupt and enable of interrupt mask is indifferent for -// generating an OSC Interrupt. -// -// Set by HW. Cleared by writing to OSCICR.XOSCDLFC -#define PRCM_OSCRIS_XOSCDLFRIS 0x00000020 -#define PRCM_OSCRIS_XOSCDLFRIS_BITN 5 -#define PRCM_OSCRIS_XOSCDLFRIS_M 0x00000020 -#define PRCM_OSCRIS_XOSCDLFRIS_S 5 - -// Field: [4] XOSCLFRIS -// -// 0: XOSCLF has not been qualified -// 1: XOSCLF has been qualified since last clear. -// -// Interrupt is qualified regardless of OSCIMSC.XOSCLFIM setting. The order of -// qualifying raw interrupt and enable of interrupt mask is indifferent for -// generating an OSC Interrupt. -// -// Set by HW. Cleared by writing to OSCICR.XOSCLFC -#define PRCM_OSCRIS_XOSCLFRIS 0x00000010 -#define PRCM_OSCRIS_XOSCLFRIS_BITN 4 -#define PRCM_OSCRIS_XOSCLFRIS_M 0x00000010 -#define PRCM_OSCRIS_XOSCLFRIS_S 4 - -// Field: [3] RCOSCDLFRIS -// -// 0: RCOSCDLF has not been qualified -// 1: RCOSCDLF has been qualified since last clear. -// -// Interrupt is qualified regardless of OSCIMSC.RCOSCDLFIM setting. The order -// of qualifying raw interrupt and enable of interrupt mask is indifferent for -// generating an OSC Interrupt. -// -// Set by HW. Cleared by writing to OSCICR.RCOSCDLFC -#define PRCM_OSCRIS_RCOSCDLFRIS 0x00000008 -#define PRCM_OSCRIS_RCOSCDLFRIS_BITN 3 -#define PRCM_OSCRIS_RCOSCDLFRIS_M 0x00000008 -#define PRCM_OSCRIS_RCOSCDLFRIS_S 3 - -// Field: [2] RCOSCLFRIS -// -// 0: RCOSCLF has not been qualified -// 1: RCOSCLF has been qualified since last clear. -// -// Interrupt is qualified regardless of OSCIMSC.RCOSCLFIM setting. The order of -// qualifying raw interrupt and enable of interrupt mask is indifferent for -// generating an OSC Interrupt. -// -// Set by HW. Cleared by writing to OSCICR.RCOSCLFC -#define PRCM_OSCRIS_RCOSCLFRIS 0x00000004 -#define PRCM_OSCRIS_RCOSCLFRIS_BITN 2 -#define PRCM_OSCRIS_RCOSCLFRIS_M 0x00000004 -#define PRCM_OSCRIS_RCOSCLFRIS_S 2 - -// Field: [1] XOSCHFRIS -// -// 0: XOSCHF has not been qualified -// 1: XOSCHF has been qualified since last clear. -// -// Interrupt is qualified regardless of OSCIMSC.XOSCHFIM setting. The order of -// qualifying raw interrupt and enable of interrupt mask is indifferent for -// generating an OSC Interrupt. -// -// Set by HW. Cleared by writing to OSCICR.XOSCHFC -#define PRCM_OSCRIS_XOSCHFRIS 0x00000002 -#define PRCM_OSCRIS_XOSCHFRIS_BITN 1 -#define PRCM_OSCRIS_XOSCHFRIS_M 0x00000002 -#define PRCM_OSCRIS_XOSCHFRIS_S 1 - -// Field: [0] RCOSCHFRIS -// -// 0: RCOSCHF has not been qualified -// 1: RCOSCHF has been qualified since last clear. -// -// Interrupt is qualified regardless of OSCIMSC.RCOSCHFIM setting. The order of -// qualifying raw interrupt and enable of interrupt mask is indifferent for -// generating an OSC Interrupt. -// -// Set by HW. Cleared by writing to OSCICR.RCOSCHFC -#define PRCM_OSCRIS_RCOSCHFRIS 0x00000001 -#define PRCM_OSCRIS_RCOSCHFRIS_BITN 0 -#define PRCM_OSCRIS_RCOSCHFRIS_M 0x00000001 -#define PRCM_OSCRIS_RCOSCHFRIS_S 0 - -//***************************************************************************** -// -// Register: PRCM_O_OSCICR -// -//***************************************************************************** -// Field: [7] HFSRCPENDC -// -// Writing 1 to this field clears the HFSRCPEND raw interrupt status. Writing 0 -// has no effect. -#define PRCM_OSCICR_HFSRCPENDC 0x00000080 -#define PRCM_OSCICR_HFSRCPENDC_BITN 7 -#define PRCM_OSCICR_HFSRCPENDC_M 0x00000080 -#define PRCM_OSCICR_HFSRCPENDC_S 7 - -// Field: [6] LFSRCDONEC -// -// Writing 1 to this field clears the LFSRCDONE raw interrupt status. Writing 0 -// has no effect. -#define PRCM_OSCICR_LFSRCDONEC 0x00000040 -#define PRCM_OSCICR_LFSRCDONEC_BITN 6 -#define PRCM_OSCICR_LFSRCDONEC_M 0x00000040 -#define PRCM_OSCICR_LFSRCDONEC_S 6 - -// Field: [5] XOSCDLFC -// -// Writing 1 to this field clears the XOSCDLF raw interrupt status. Writing 0 -// has no effect. -#define PRCM_OSCICR_XOSCDLFC 0x00000020 -#define PRCM_OSCICR_XOSCDLFC_BITN 5 -#define PRCM_OSCICR_XOSCDLFC_M 0x00000020 -#define PRCM_OSCICR_XOSCDLFC_S 5 - -// Field: [4] XOSCLFC -// -// Writing 1 to this field clears the XOSCLF raw interrupt status. Writing 0 -// has no effect. -#define PRCM_OSCICR_XOSCLFC 0x00000010 -#define PRCM_OSCICR_XOSCLFC_BITN 4 -#define PRCM_OSCICR_XOSCLFC_M 0x00000010 -#define PRCM_OSCICR_XOSCLFC_S 4 - -// Field: [3] RCOSCDLFC -// -// Writing 1 to this field clears the RCOSCDLF raw interrupt status. Writing 0 -// has no effect. -#define PRCM_OSCICR_RCOSCDLFC 0x00000008 -#define PRCM_OSCICR_RCOSCDLFC_BITN 3 -#define PRCM_OSCICR_RCOSCDLFC_M 0x00000008 -#define PRCM_OSCICR_RCOSCDLFC_S 3 - -// Field: [2] RCOSCLFC -// -// Writing 1 to this field clears the RCOSCLF raw interrupt status. Writing 0 -// has no effect. -#define PRCM_OSCICR_RCOSCLFC 0x00000004 -#define PRCM_OSCICR_RCOSCLFC_BITN 2 -#define PRCM_OSCICR_RCOSCLFC_M 0x00000004 -#define PRCM_OSCICR_RCOSCLFC_S 2 - -// Field: [1] XOSCHFC -// -// Writing 1 to this field clears the XOSCHF raw interrupt status. Writing 0 -// has no effect. -#define PRCM_OSCICR_XOSCHFC 0x00000002 -#define PRCM_OSCICR_XOSCHFC_BITN 1 -#define PRCM_OSCICR_XOSCHFC_M 0x00000002 -#define PRCM_OSCICR_XOSCHFC_S 1 - -// Field: [0] RCOSCHFC -// -// Writing 1 to this field clears the RCOSCHF raw interrupt status. Writing 0 -// has no effect. -#define PRCM_OSCICR_RCOSCHFC 0x00000001 -#define PRCM_OSCICR_RCOSCHFC_BITN 0 -#define PRCM_OSCICR_RCOSCHFC_M 0x00000001 -#define PRCM_OSCICR_RCOSCHFC_S 0 - - -#endif // __PRCM__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h deleted file mode 100644 index 612d3ec24a7..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_dbell.h +++ /dev/null @@ -1,1672 +0,0 @@ -/****************************************************************************** -* Filename: hw_rfc_dbell_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_RFC_DBELL_H__ -#define __HW_RFC_DBELL_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// RFC_DBELL component -// -//***************************************************************************** -// Doorbell Command Register -#define RFC_DBELL_O_CMDR 0x00000000 - -// Doorbell Command Status Register -#define RFC_DBELL_O_CMDSTA 0x00000004 - -// Interrupt Flags From RF Hardware Modules -#define RFC_DBELL_O_RFHWIFG 0x00000008 - -// Interrupt Enable For RF Hardware Modules -#define RFC_DBELL_O_RFHWIEN 0x0000000C - -// Interrupt Flags For Command and Packet Engine Generated Interrupts -#define RFC_DBELL_O_RFCPEIFG 0x00000010 - -// Interrupt Enable For Command and Packet Engine Generated Interrupts -#define RFC_DBELL_O_RFCPEIEN 0x00000014 - -// Interrupt Vector Selection For Command and Packet Engine Generated -// Interrupts -#define RFC_DBELL_O_RFCPEISL 0x00000018 - -// Doorbell Command Acknowledgement Interrupt Flag -#define RFC_DBELL_O_RFACKIFG 0x0000001C - -// RF Core General Purpose Output Control -#define RFC_DBELL_O_SYSGPOCTL 0x00000020 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_CMDR -// -//***************************************************************************** -// Field: [31:0] CMD -// -// Command register. Raises an interrupt to the Command and packet engine (CPE) -// upon write. -#define RFC_DBELL_CMDR_CMD_W 32 -#define RFC_DBELL_CMDR_CMD_M 0xFFFFFFFF -#define RFC_DBELL_CMDR_CMD_S 0 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_CMDSTA -// -//***************************************************************************** -// Field: [31:0] STAT -// -// Status of the last command used -#define RFC_DBELL_CMDSTA_STAT_W 32 -#define RFC_DBELL_CMDSTA_STAT_M 0xFFFFFFFF -#define RFC_DBELL_CMDSTA_STAT_S 0 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_RFHWIFG -// -//***************************************************************************** -// Field: [19] RATCH7 -// -// Radio timer channel 7 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH7 0x00080000 -#define RFC_DBELL_RFHWIFG_RATCH7_BITN 19 -#define RFC_DBELL_RFHWIFG_RATCH7_M 0x00080000 -#define RFC_DBELL_RFHWIFG_RATCH7_S 19 - -// Field: [18] RATCH6 -// -// Radio timer channel 6 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH6 0x00040000 -#define RFC_DBELL_RFHWIFG_RATCH6_BITN 18 -#define RFC_DBELL_RFHWIFG_RATCH6_M 0x00040000 -#define RFC_DBELL_RFHWIFG_RATCH6_S 18 - -// Field: [17] RATCH5 -// -// Radio timer channel 5 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH5 0x00020000 -#define RFC_DBELL_RFHWIFG_RATCH5_BITN 17 -#define RFC_DBELL_RFHWIFG_RATCH5_M 0x00020000 -#define RFC_DBELL_RFHWIFG_RATCH5_S 17 - -// Field: [16] RATCH4 -// -// Radio timer channel 4 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH4 0x00010000 -#define RFC_DBELL_RFHWIFG_RATCH4_BITN 16 -#define RFC_DBELL_RFHWIFG_RATCH4_M 0x00010000 -#define RFC_DBELL_RFHWIFG_RATCH4_S 16 - -// Field: [15] RATCH3 -// -// Radio timer channel 3 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH3 0x00008000 -#define RFC_DBELL_RFHWIFG_RATCH3_BITN 15 -#define RFC_DBELL_RFHWIFG_RATCH3_M 0x00008000 -#define RFC_DBELL_RFHWIFG_RATCH3_S 15 - -// Field: [14] RATCH2 -// -// Radio timer channel 2 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH2 0x00004000 -#define RFC_DBELL_RFHWIFG_RATCH2_BITN 14 -#define RFC_DBELL_RFHWIFG_RATCH2_M 0x00004000 -#define RFC_DBELL_RFHWIFG_RATCH2_S 14 - -// Field: [13] RATCH1 -// -// Radio timer channel 1 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH1 0x00002000 -#define RFC_DBELL_RFHWIFG_RATCH1_BITN 13 -#define RFC_DBELL_RFHWIFG_RATCH1_M 0x00002000 -#define RFC_DBELL_RFHWIFG_RATCH1_S 13 - -// Field: [12] RATCH0 -// -// Radio timer channel 0 interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_RATCH0 0x00001000 -#define RFC_DBELL_RFHWIFG_RATCH0_BITN 12 -#define RFC_DBELL_RFHWIFG_RATCH0_M 0x00001000 -#define RFC_DBELL_RFHWIFG_RATCH0_S 12 - -// Field: [11] RFESOFT2 -// -// RF engine software defined interrupt 2 flag. Write zero to clear flag. Write -// to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT2 0x00000800 -#define RFC_DBELL_RFHWIFG_RFESOFT2_BITN 11 -#define RFC_DBELL_RFHWIFG_RFESOFT2_M 0x00000800 -#define RFC_DBELL_RFHWIFG_RFESOFT2_S 11 - -// Field: [10] RFESOFT1 -// -// RF engine software defined interrupt 1 flag. Write zero to clear flag. Write -// to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT1 0x00000400 -#define RFC_DBELL_RFHWIFG_RFESOFT1_BITN 10 -#define RFC_DBELL_RFHWIFG_RFESOFT1_M 0x00000400 -#define RFC_DBELL_RFHWIFG_RFESOFT1_S 10 - -// Field: [9] RFESOFT0 -// -// RF engine software defined interrupt 0 flag. Write zero to clear flag. Write -// to one has no effect. -#define RFC_DBELL_RFHWIFG_RFESOFT0 0x00000200 -#define RFC_DBELL_RFHWIFG_RFESOFT0_BITN 9 -#define RFC_DBELL_RFHWIFG_RFESOFT0_M 0x00000200 -#define RFC_DBELL_RFHWIFG_RFESOFT0_S 9 - -// Field: [8] RFEDONE -// -// RF engine command done interrupt flag. Write zero to clear flag. Write to -// one has no effect. -#define RFC_DBELL_RFHWIFG_RFEDONE 0x00000100 -#define RFC_DBELL_RFHWIFG_RFEDONE_BITN 8 -#define RFC_DBELL_RFHWIFG_RFEDONE_M 0x00000100 -#define RFC_DBELL_RFHWIFG_RFEDONE_S 8 - -// Field: [6] TRCTK -// -// Debug tracer system tick interrupt flag. Write zero to clear flag. Write to -// one has no effect. -#define RFC_DBELL_RFHWIFG_TRCTK 0x00000040 -#define RFC_DBELL_RFHWIFG_TRCTK_BITN 6 -#define RFC_DBELL_RFHWIFG_TRCTK_M 0x00000040 -#define RFC_DBELL_RFHWIFG_TRCTK_S 6 - -// Field: [5] MDMSOFT -// -// Modem software defined interrupt flag. Write zero to clear flag. Write to -// one has no effect. -#define RFC_DBELL_RFHWIFG_MDMSOFT 0x00000020 -#define RFC_DBELL_RFHWIFG_MDMSOFT_BITN 5 -#define RFC_DBELL_RFHWIFG_MDMSOFT_M 0x00000020 -#define RFC_DBELL_RFHWIFG_MDMSOFT_S 5 - -// Field: [4] MDMOUT -// -// Modem FIFO output interrupt flag. Write zero to clear flag. Write to one has -// no effect. -#define RFC_DBELL_RFHWIFG_MDMOUT 0x00000010 -#define RFC_DBELL_RFHWIFG_MDMOUT_BITN 4 -#define RFC_DBELL_RFHWIFG_MDMOUT_M 0x00000010 -#define RFC_DBELL_RFHWIFG_MDMOUT_S 4 - -// Field: [3] MDMIN -// -// Modem FIFO input interrupt flag. Write zero to clear flag. Write to one has -// no effect. -#define RFC_DBELL_RFHWIFG_MDMIN 0x00000008 -#define RFC_DBELL_RFHWIFG_MDMIN_BITN 3 -#define RFC_DBELL_RFHWIFG_MDMIN_M 0x00000008 -#define RFC_DBELL_RFHWIFG_MDMIN_S 3 - -// Field: [2] MDMDONE -// -// Modem command done interrupt flag. Write zero to clear flag. Write to one -// has no effect. -#define RFC_DBELL_RFHWIFG_MDMDONE 0x00000004 -#define RFC_DBELL_RFHWIFG_MDMDONE_BITN 2 -#define RFC_DBELL_RFHWIFG_MDMDONE_M 0x00000004 -#define RFC_DBELL_RFHWIFG_MDMDONE_S 2 - -// Field: [1] FSCA -// -// Frequency synthesizer calibration accelerator interrupt flag. Write zero to -// clear flag. Write to one has no effect. -#define RFC_DBELL_RFHWIFG_FSCA 0x00000002 -#define RFC_DBELL_RFHWIFG_FSCA_BITN 1 -#define RFC_DBELL_RFHWIFG_FSCA_M 0x00000002 -#define RFC_DBELL_RFHWIFG_FSCA_S 1 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_RFHWIEN -// -//***************************************************************************** -// Field: [19] RATCH7 -// -// Interrupt enable for RFHWIFG.RATCH7. -#define RFC_DBELL_RFHWIEN_RATCH7 0x00080000 -#define RFC_DBELL_RFHWIEN_RATCH7_BITN 19 -#define RFC_DBELL_RFHWIEN_RATCH7_M 0x00080000 -#define RFC_DBELL_RFHWIEN_RATCH7_S 19 - -// Field: [18] RATCH6 -// -// Interrupt enable for RFHWIFG.RATCH6. -#define RFC_DBELL_RFHWIEN_RATCH6 0x00040000 -#define RFC_DBELL_RFHWIEN_RATCH6_BITN 18 -#define RFC_DBELL_RFHWIEN_RATCH6_M 0x00040000 -#define RFC_DBELL_RFHWIEN_RATCH6_S 18 - -// Field: [17] RATCH5 -// -// Interrupt enable for RFHWIFG.RATCH5. -#define RFC_DBELL_RFHWIEN_RATCH5 0x00020000 -#define RFC_DBELL_RFHWIEN_RATCH5_BITN 17 -#define RFC_DBELL_RFHWIEN_RATCH5_M 0x00020000 -#define RFC_DBELL_RFHWIEN_RATCH5_S 17 - -// Field: [16] RATCH4 -// -// Interrupt enable for RFHWIFG.RATCH4. -#define RFC_DBELL_RFHWIEN_RATCH4 0x00010000 -#define RFC_DBELL_RFHWIEN_RATCH4_BITN 16 -#define RFC_DBELL_RFHWIEN_RATCH4_M 0x00010000 -#define RFC_DBELL_RFHWIEN_RATCH4_S 16 - -// Field: [15] RATCH3 -// -// Interrupt enable for RFHWIFG.RATCH3. -#define RFC_DBELL_RFHWIEN_RATCH3 0x00008000 -#define RFC_DBELL_RFHWIEN_RATCH3_BITN 15 -#define RFC_DBELL_RFHWIEN_RATCH3_M 0x00008000 -#define RFC_DBELL_RFHWIEN_RATCH3_S 15 - -// Field: [14] RATCH2 -// -// Interrupt enable for RFHWIFG.RATCH2. -#define RFC_DBELL_RFHWIEN_RATCH2 0x00004000 -#define RFC_DBELL_RFHWIEN_RATCH2_BITN 14 -#define RFC_DBELL_RFHWIEN_RATCH2_M 0x00004000 -#define RFC_DBELL_RFHWIEN_RATCH2_S 14 - -// Field: [13] RATCH1 -// -// Interrupt enable for RFHWIFG.RATCH1. -#define RFC_DBELL_RFHWIEN_RATCH1 0x00002000 -#define RFC_DBELL_RFHWIEN_RATCH1_BITN 13 -#define RFC_DBELL_RFHWIEN_RATCH1_M 0x00002000 -#define RFC_DBELL_RFHWIEN_RATCH1_S 13 - -// Field: [12] RATCH0 -// -// Interrupt enable for RFHWIFG.RATCH0. -#define RFC_DBELL_RFHWIEN_RATCH0 0x00001000 -#define RFC_DBELL_RFHWIEN_RATCH0_BITN 12 -#define RFC_DBELL_RFHWIEN_RATCH0_M 0x00001000 -#define RFC_DBELL_RFHWIEN_RATCH0_S 12 - -// Field: [11] RFESOFT2 -// -// Interrupt enable for RFHWIFG.RFESOFT2. -#define RFC_DBELL_RFHWIEN_RFESOFT2 0x00000800 -#define RFC_DBELL_RFHWIEN_RFESOFT2_BITN 11 -#define RFC_DBELL_RFHWIEN_RFESOFT2_M 0x00000800 -#define RFC_DBELL_RFHWIEN_RFESOFT2_S 11 - -// Field: [10] RFESOFT1 -// -// Interrupt enable for RFHWIFG.RFESOFT1. -#define RFC_DBELL_RFHWIEN_RFESOFT1 0x00000400 -#define RFC_DBELL_RFHWIEN_RFESOFT1_BITN 10 -#define RFC_DBELL_RFHWIEN_RFESOFT1_M 0x00000400 -#define RFC_DBELL_RFHWIEN_RFESOFT1_S 10 - -// Field: [9] RFESOFT0 -// -// Interrupt enable for RFHWIFG.RFESOFT0. -#define RFC_DBELL_RFHWIEN_RFESOFT0 0x00000200 -#define RFC_DBELL_RFHWIEN_RFESOFT0_BITN 9 -#define RFC_DBELL_RFHWIEN_RFESOFT0_M 0x00000200 -#define RFC_DBELL_RFHWIEN_RFESOFT0_S 9 - -// Field: [8] RFEDONE -// -// Interrupt enable for RFHWIFG.RFEDONE. -#define RFC_DBELL_RFHWIEN_RFEDONE 0x00000100 -#define RFC_DBELL_RFHWIEN_RFEDONE_BITN 8 -#define RFC_DBELL_RFHWIEN_RFEDONE_M 0x00000100 -#define RFC_DBELL_RFHWIEN_RFEDONE_S 8 - -// Field: [6] TRCTK -// -// Interrupt enable for RFHWIFG.TRCTK. -#define RFC_DBELL_RFHWIEN_TRCTK 0x00000040 -#define RFC_DBELL_RFHWIEN_TRCTK_BITN 6 -#define RFC_DBELL_RFHWIEN_TRCTK_M 0x00000040 -#define RFC_DBELL_RFHWIEN_TRCTK_S 6 - -// Field: [5] MDMSOFT -// -// Interrupt enable for RFHWIFG.MDMSOFT. -#define RFC_DBELL_RFHWIEN_MDMSOFT 0x00000020 -#define RFC_DBELL_RFHWIEN_MDMSOFT_BITN 5 -#define RFC_DBELL_RFHWIEN_MDMSOFT_M 0x00000020 -#define RFC_DBELL_RFHWIEN_MDMSOFT_S 5 - -// Field: [4] MDMOUT -// -// Interrupt enable for RFHWIFG.MDMOUT. -#define RFC_DBELL_RFHWIEN_MDMOUT 0x00000010 -#define RFC_DBELL_RFHWIEN_MDMOUT_BITN 4 -#define RFC_DBELL_RFHWIEN_MDMOUT_M 0x00000010 -#define RFC_DBELL_RFHWIEN_MDMOUT_S 4 - -// Field: [3] MDMIN -// -// Interrupt enable for RFHWIFG.MDMIN. -#define RFC_DBELL_RFHWIEN_MDMIN 0x00000008 -#define RFC_DBELL_RFHWIEN_MDMIN_BITN 3 -#define RFC_DBELL_RFHWIEN_MDMIN_M 0x00000008 -#define RFC_DBELL_RFHWIEN_MDMIN_S 3 - -// Field: [2] MDMDONE -// -// Interrupt enable for RFHWIFG.MDMDONE. -#define RFC_DBELL_RFHWIEN_MDMDONE 0x00000004 -#define RFC_DBELL_RFHWIEN_MDMDONE_BITN 2 -#define RFC_DBELL_RFHWIEN_MDMDONE_M 0x00000004 -#define RFC_DBELL_RFHWIEN_MDMDONE_S 2 - -// Field: [1] FSCA -// -// Interrupt enable for RFHWIFG.FSCA. -#define RFC_DBELL_RFHWIEN_FSCA 0x00000002 -#define RFC_DBELL_RFHWIEN_FSCA_BITN 1 -#define RFC_DBELL_RFHWIEN_FSCA_M 0x00000002 -#define RFC_DBELL_RFHWIEN_FSCA_S 1 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_RFCPEIFG -// -//***************************************************************************** -// Field: [31] INTERNAL_ERROR -// -// Interrupt flag 31. The command and packet engine (CPE) has observed an -// unexpected error. A reset of the CPE is needed. This can be done by -// switching the RF Core power domain off and on in PRCM:PDCTL1RFC. Write zero -// to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEIFG_INTERNAL_ERROR_S 31 - -// Field: [30] BOOT_DONE -// -// Interrupt flag 30. The command and packet engine (CPE) boot is finished. -// Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEIFG_BOOT_DONE_S 30 - -// Field: [29] MODULES_UNLOCKED -// -// Interrupt flag 29. As part of command and packet engine (CPE) boot process, -// it has opened access to RF Core modules and memories. Write zero to clear -// flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEIFG_MODULES_UNLOCKED_S 29 - -// Field: [28] SYNTH_NO_LOCK -// -// Interrupt flag 28. The phase-locked loop in frequency synthesizer has -// reported loss of lock. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEIFG_SYNTH_NO_LOCK_S 28 - -// Field: [27] IRQ27 -// -// Interrupt flag 27. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEIFG_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEIFG_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEIFG_IRQ27_S 27 - -// Field: [26] RX_ABORTED -// -// Interrupt flag 26. Packet reception stopped before packet was done. Write -// zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEIFG_RX_ABORTED_S 26 - -// Field: [25] RX_N_DATA_WRITTEN -// -// Interrupt flag 25. Specified number of bytes written to partial read Rx -// buffer. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEIFG_RX_N_DATA_WRITTEN_S 25 - -// Field: [24] RX_DATA_WRITTEN -// -// Interrupt flag 24. Data written to partial read Rx buffer. Write zero to -// clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEIFG_RX_DATA_WRITTEN_S 24 - -// Field: [23] RX_ENTRY_DONE -// -// Interrupt flag 23. Rx queue data entry changing state to finished. Write -// zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEIFG_RX_ENTRY_DONE_S 23 - -// Field: [22] RX_BUF_FULL -// -// Interrupt flag 22. Packet received that did not fit in Rx queue. BLE mode: -// Packet received that did not fit in the Rx queue. IEEE 802.15.4 mode: Frame -// received that did not fit in the Rx queue. Write zero to clear flag. Write -// to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEIFG_RX_BUF_FULL_S 22 - -// Field: [21] RX_CTRL_ACK -// -// Interrupt flag 21. BLE mode only: LL control packet received with CRC OK, -// not to be ignored, then acknowledgement sent. Write zero to clear flag. -// Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_ACK_S 21 - -// Field: [20] RX_CTRL -// -// Interrupt flag 20. BLE mode only: LL control packet received with CRC OK, -// not to be ignored. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEIFG_RX_CTRL_S 20 - -// Field: [19] RX_EMPTY -// -// Interrupt flag 19. BLE mode only: Packet received with CRC OK, not to be -// ignored, no payload. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEIFG_RX_EMPTY_S 19 - -// Field: [18] RX_IGNORED -// -// Interrupt flag 18. Packet received, but can be ignored. BLE mode: Packet -// received with CRC OK, but to be ignored. IEEE 802.15.4 mode: Frame received -// with ignore flag set. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEIFG_RX_IGNORED_S 18 - -// Field: [17] RX_NOK -// -// Interrupt flag 17. Packet received with CRC error. BLE mode: Packet received -// with CRC error. IEEE 802.15.4 mode: Frame received with CRC error. Write -// zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEIFG_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEIFG_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEIFG_RX_NOK_S 17 - -// Field: [16] RX_OK -// -// Interrupt flag 16. Packet received correctly. BLE mode: Packet received with -// CRC OK, payload, and not to be ignored. IEEE 802.15.4 mode: Frame received -// with CRC OK. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEIFG_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEIFG_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEIFG_RX_OK_S 16 - -// Field: [15] IRQ15 -// -// Interrupt flag 15. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEIFG_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEIFG_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEIFG_IRQ15_S 15 - -// Field: [14] IRQ14 -// -// Interrupt flag 14. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEIFG_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEIFG_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEIFG_IRQ14_S 14 - -// Field: [13] FG_COMMAND_STARTED -// -// Interrupt flag 13. IEEE 802.15.4 mode only: A foreground radio operation -// command has gone into active state. -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED 0x00002000 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_BITN 13 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_M 0x00002000 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_STARTED_S 13 - -// Field: [12] COMMAND_STARTED -// -// Interrupt flag 12. A radio operation command has gone into active state. -#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED 0x00001000 -#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_BITN 12 -#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_M 0x00001000 -#define RFC_DBELL_RFCPEIFG_COMMAND_STARTED_S 12 - -// Field: [11] TX_BUFFER_CHANGED -// -// Interrupt flag 11. BLE mode only: A buffer change is complete after -// CMD_BLE_ADV_PAYLOAD. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEIFG_TX_BUFFER_CHANGED_S 11 - -// Field: [10] TX_ENTRY_DONE -// -// Interrupt flag 10. Tx queue data entry state changed to finished. Write zero -// to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEIFG_TX_ENTRY_DONE_S 10 - -// Field: [9] TX_RETRANS -// -// Interrupt flag 9. BLE mode only: Packet retransmitted. Write zero to clear -// flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEIFG_TX_RETRANS_S 9 - -// Field: [8] TX_CTRL_ACK_ACK -// -// Interrupt flag 8. BLE mode only: Acknowledgement received on a transmitted -// LL control packet, and acknowledgement transmitted for that packet. Write -// zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_ACK_S 8 - -// Field: [7] TX_CTRL_ACK -// -// Interrupt flag 7. BLE mode: Acknowledgement received on a transmitted LL -// control packet. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_ACK_S 7 - -// Field: [6] TX_CTRL -// -// Interrupt flag 6. BLE mode: Transmitted LL control packet. Write zero to -// clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEIFG_TX_CTRL_S 6 - -// Field: [5] TX_ACK -// -// Interrupt flag 5. BLE mode: Acknowledgement received on a transmitted -// packet. IEEE 802.15.4 mode: Transmitted automatic ACK frame. Write zero to -// clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEIFG_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEIFG_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEIFG_TX_ACK_S 5 - -// Field: [4] TX_DONE -// -// Interrupt flag 4. Packet transmitted. (BLE mode: A packet has been -// transmitted.) (IEEE 802.15.4 mode: A frame has been transmitted). Write zero -// to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEIFG_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEIFG_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEIFG_TX_DONE_S 4 - -// Field: [3] LAST_FG_COMMAND_DONE -// -// Interrupt flag 3. IEEE 802.15.4 mode only: The last foreground radio -// operation command in a chain of commands has finished. Write zero to clear -// flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEIFG_LAST_FG_COMMAND_DONE_S 3 - -// Field: [2] FG_COMMAND_DONE -// -// Interrupt flag 2. IEEE 802.15.4 mode only: A foreground radio operation -// command has finished. Write zero to clear flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEIFG_FG_COMMAND_DONE_S 2 - -// Field: [1] LAST_COMMAND_DONE -// -// Interrupt flag 1. The last radio operation command in a chain of commands -// has finished. (IEEE 802.15.4 mode: The last background level radio operation -// command in a chain of commands has finished.) Write zero to clear flag. -// Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEIFG_LAST_COMMAND_DONE_S 1 - -// Field: [0] COMMAND_DONE -// -// Interrupt flag 0. A radio operation has finished. (IEEE 802.15.4 mode: A -// background level radio operation command has finished.) Write zero to clear -// flag. Write to one has no effect. -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEIFG_COMMAND_DONE_S 0 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_RFCPEIEN -// -//***************************************************************************** -// Field: [31] INTERNAL_ERROR -// -// Interrupt enable for RFCPEIFG.INTERNAL_ERROR. -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEIEN_INTERNAL_ERROR_S 31 - -// Field: [30] BOOT_DONE -// -// Interrupt enable for RFCPEIFG.BOOT_DONE. -#define RFC_DBELL_RFCPEIEN_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEIEN_BOOT_DONE_S 30 - -// Field: [29] MODULES_UNLOCKED -// -// Interrupt enable for RFCPEIFG.MODULES_UNLOCKED. -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEIEN_MODULES_UNLOCKED_S 29 - -// Field: [28] SYNTH_NO_LOCK -// -// Interrupt enable for RFCPEIFG.SYNTH_NO_LOCK. -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEIEN_SYNTH_NO_LOCK_S 28 - -// Field: [27] IRQ27 -// -// Interrupt enable for RFCPEIFG.IRQ27. -#define RFC_DBELL_RFCPEIEN_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEIEN_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEIEN_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEIEN_IRQ27_S 27 - -// Field: [26] RX_ABORTED -// -// Interrupt enable for RFCPEIFG.RX_ABORTED. -#define RFC_DBELL_RFCPEIEN_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEIEN_RX_ABORTED_S 26 - -// Field: [25] RX_N_DATA_WRITTEN -// -// Interrupt enable for RFCPEIFG.RX_N_DATA_WRITTEN. -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEIEN_RX_N_DATA_WRITTEN_S 25 - -// Field: [24] RX_DATA_WRITTEN -// -// Interrupt enable for RFCPEIFG.RX_DATA_WRITTEN. -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEIEN_RX_DATA_WRITTEN_S 24 - -// Field: [23] RX_ENTRY_DONE -// -// Interrupt enable for RFCPEIFG.RX_ENTRY_DONE. -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEIEN_RX_ENTRY_DONE_S 23 - -// Field: [22] RX_BUF_FULL -// -// Interrupt enable for RFCPEIFG.RX_BUF_FULL. -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEIEN_RX_BUF_FULL_S 22 - -// Field: [21] RX_CTRL_ACK -// -// Interrupt enable for RFCPEIFG.RX_CTRL_ACK. -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_ACK_S 21 - -// Field: [20] RX_CTRL -// -// Interrupt enable for RFCPEIFG.RX_CTRL. -#define RFC_DBELL_RFCPEIEN_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEIEN_RX_CTRL_S 20 - -// Field: [19] RX_EMPTY -// -// Interrupt enable for RFCPEIFG.RX_EMPTY. -#define RFC_DBELL_RFCPEIEN_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEIEN_RX_EMPTY_S 19 - -// Field: [18] RX_IGNORED -// -// Interrupt enable for RFCPEIFG.RX_IGNORED. -#define RFC_DBELL_RFCPEIEN_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEIEN_RX_IGNORED_S 18 - -// Field: [17] RX_NOK -// -// Interrupt enable for RFCPEIFG.RX_NOK. -#define RFC_DBELL_RFCPEIEN_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEIEN_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEIEN_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEIEN_RX_NOK_S 17 - -// Field: [16] RX_OK -// -// Interrupt enable for RFCPEIFG.RX_OK. -#define RFC_DBELL_RFCPEIEN_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEIEN_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEIEN_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEIEN_RX_OK_S 16 - -// Field: [15] IRQ15 -// -// Interrupt enable for RFCPEIFG.IRQ15. -#define RFC_DBELL_RFCPEIEN_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEIEN_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEIEN_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEIEN_IRQ15_S 15 - -// Field: [14] IRQ14 -// -// Interrupt enable for RFCPEIFG.IRQ14. -#define RFC_DBELL_RFCPEIEN_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEIEN_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEIEN_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEIEN_IRQ14_S 14 - -// Field: [13] FG_COMMAND_STARTED -// -// Interrupt enable for RFCPEIFG.FG_COMMAND_STARTED. -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED 0x00002000 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_BITN 13 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_M 0x00002000 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_STARTED_S 13 - -// Field: [12] COMMAND_STARTED -// -// Interrupt enable for RFCPEIFG.COMMAND_STARTED. -#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED 0x00001000 -#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_BITN 12 -#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_M 0x00001000 -#define RFC_DBELL_RFCPEIEN_COMMAND_STARTED_S 12 - -// Field: [11] TX_BUFFER_CHANGED -// -// Interrupt enable for RFCPEIFG.TX_BUFFER_CHANGED. -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEIEN_TX_BUFFER_CHANGED_S 11 - -// Field: [10] TX_ENTRY_DONE -// -// Interrupt enable for RFCPEIFG.TX_ENTRY_DONE. -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEIEN_TX_ENTRY_DONE_S 10 - -// Field: [9] TX_RETRANS -// -// Interrupt enable for RFCPEIFG.TX_RETRANS. -#define RFC_DBELL_RFCPEIEN_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEIEN_TX_RETRANS_S 9 - -// Field: [8] TX_CTRL_ACK_ACK -// -// Interrupt enable for RFCPEIFG.TX_CTRL_ACK_ACK. -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_ACK_S 8 - -// Field: [7] TX_CTRL_ACK -// -// Interrupt enable for RFCPEIFG.TX_CTRL_ACK. -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_ACK_S 7 - -// Field: [6] TX_CTRL -// -// Interrupt enable for RFCPEIFG.TX_CTRL. -#define RFC_DBELL_RFCPEIEN_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEIEN_TX_CTRL_S 6 - -// Field: [5] TX_ACK -// -// Interrupt enable for RFCPEIFG.TX_ACK. -#define RFC_DBELL_RFCPEIEN_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEIEN_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEIEN_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEIEN_TX_ACK_S 5 - -// Field: [4] TX_DONE -// -// Interrupt enable for RFCPEIFG.TX_DONE. -#define RFC_DBELL_RFCPEIEN_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEIEN_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEIEN_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEIEN_TX_DONE_S 4 - -// Field: [3] LAST_FG_COMMAND_DONE -// -// Interrupt enable for RFCPEIFG.LAST_FG_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEIEN_LAST_FG_COMMAND_DONE_S 3 - -// Field: [2] FG_COMMAND_DONE -// -// Interrupt enable for RFCPEIFG.FG_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEIEN_FG_COMMAND_DONE_S 2 - -// Field: [1] LAST_COMMAND_DONE -// -// Interrupt enable for RFCPEIFG.LAST_COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEIEN_LAST_COMMAND_DONE_S 1 - -// Field: [0] COMMAND_DONE -// -// Interrupt enable for RFCPEIFG.COMMAND_DONE. -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEIEN_COMMAND_DONE_S 0 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_RFCPEISL -// -//***************************************************************************** -// Field: [31] INTERNAL_ERROR -// -// Select which CPU interrupt vector the RFCPEIFG.INTERNAL_ERROR interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_BITN 31 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_M 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_S 31 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE1 0x80000000 -#define RFC_DBELL_RFCPEISL_INTERNAL_ERROR_CPE0 0x00000000 - -// Field: [30] BOOT_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.BOOT_DONE interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_BOOT_DONE 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_BITN 30 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_M 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_S 30 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE1 0x40000000 -#define RFC_DBELL_RFCPEISL_BOOT_DONE_CPE0 0x00000000 - -// Field: [29] MODULES_UNLOCKED -// -// Select which CPU interrupt vector the RFCPEIFG.MODULES_UNLOCKED interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_BITN 29 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_M 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_S 29 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE1 0x20000000 -#define RFC_DBELL_RFCPEISL_MODULES_UNLOCKED_CPE0 0x00000000 - -// Field: [28] SYNTH_NO_LOCK -// -// Select which CPU interrupt vector the RFCPEIFG.SYNTH_NO_LOCK interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_BITN 28 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_M 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_S 28 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE1 0x10000000 -#define RFC_DBELL_RFCPEISL_SYNTH_NO_LOCK_CPE0 0x00000000 - -// Field: [27] IRQ27 -// -// Select which CPU interrupt vector the RFCPEIFG.IRQ27 interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ27 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_BITN 27 -#define RFC_DBELL_RFCPEISL_IRQ27_M 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_S 27 -#define RFC_DBELL_RFCPEISL_IRQ27_CPE1 0x08000000 -#define RFC_DBELL_RFCPEISL_IRQ27_CPE0 0x00000000 - -// Field: [26] RX_ABORTED -// -// Select which CPU interrupt vector the RFCPEIFG.RX_ABORTED interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_ABORTED 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_BITN 26 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_M 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_S 26 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE1 0x04000000 -#define RFC_DBELL_RFCPEISL_RX_ABORTED_CPE0 0x00000000 - -// Field: [25] RX_N_DATA_WRITTEN -// -// Select which CPU interrupt vector the RFCPEIFG.RX_N_DATA_WRITTEN interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_BITN 25 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_M 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_S 25 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE1 0x02000000 -#define RFC_DBELL_RFCPEISL_RX_N_DATA_WRITTEN_CPE0 0x00000000 - -// Field: [24] RX_DATA_WRITTEN -// -// Select which CPU interrupt vector the RFCPEIFG.RX_DATA_WRITTEN interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_BITN 24 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_M 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_S 24 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE1 0x01000000 -#define RFC_DBELL_RFCPEISL_RX_DATA_WRITTEN_CPE0 0x00000000 - -// Field: [23] RX_ENTRY_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.RX_ENTRY_DONE interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_BITN 23 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_M 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_S 23 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE1 0x00800000 -#define RFC_DBELL_RFCPEISL_RX_ENTRY_DONE_CPE0 0x00000000 - -// Field: [22] RX_BUF_FULL -// -// Select which CPU interrupt vector the RFCPEIFG.RX_BUF_FULL interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_BITN 22 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_M 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_S 22 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE1 0x00400000 -#define RFC_DBELL_RFCPEISL_RX_BUF_FULL_CPE0 0x00000000 - -// Field: [21] RX_CTRL_ACK -// -// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL_ACK interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_BITN 21 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_M 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_S 21 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE1 0x00200000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_ACK_CPE0 0x00000000 - -// Field: [20] RX_CTRL -// -// Select which CPU interrupt vector the RFCPEIFG.RX_CTRL interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_CTRL 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_BITN 20 -#define RFC_DBELL_RFCPEISL_RX_CTRL_M 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_S 20 -#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE1 0x00100000 -#define RFC_DBELL_RFCPEISL_RX_CTRL_CPE0 0x00000000 - -// Field: [19] RX_EMPTY -// -// Select which CPU interrupt vector the RFCPEIFG.RX_EMPTY interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_EMPTY 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_BITN 19 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_M 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_S 19 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE1 0x00080000 -#define RFC_DBELL_RFCPEISL_RX_EMPTY_CPE0 0x00000000 - -// Field: [18] RX_IGNORED -// -// Select which CPU interrupt vector the RFCPEIFG.RX_IGNORED interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_IGNORED 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_BITN 18 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_M 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_S 18 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE1 0x00040000 -#define RFC_DBELL_RFCPEISL_RX_IGNORED_CPE0 0x00000000 - -// Field: [17] RX_NOK -// -// Select which CPU interrupt vector the RFCPEIFG.RX_NOK interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_NOK 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_BITN 17 -#define RFC_DBELL_RFCPEISL_RX_NOK_M 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_S 17 -#define RFC_DBELL_RFCPEISL_RX_NOK_CPE1 0x00020000 -#define RFC_DBELL_RFCPEISL_RX_NOK_CPE0 0x00000000 - -// Field: [16] RX_OK -// -// Select which CPU interrupt vector the RFCPEIFG.RX_OK interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_RX_OK 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_BITN 16 -#define RFC_DBELL_RFCPEISL_RX_OK_M 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_S 16 -#define RFC_DBELL_RFCPEISL_RX_OK_CPE1 0x00010000 -#define RFC_DBELL_RFCPEISL_RX_OK_CPE0 0x00000000 - -// Field: [15] IRQ15 -// -// Select which CPU interrupt vector the RFCPEIFG.IRQ15 interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ15 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_BITN 15 -#define RFC_DBELL_RFCPEISL_IRQ15_M 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_S 15 -#define RFC_DBELL_RFCPEISL_IRQ15_CPE1 0x00008000 -#define RFC_DBELL_RFCPEISL_IRQ15_CPE0 0x00000000 - -// Field: [14] IRQ14 -// -// Select which CPU interrupt vector the RFCPEIFG.IRQ14 interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_IRQ14 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_BITN 14 -#define RFC_DBELL_RFCPEISL_IRQ14_M 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_S 14 -#define RFC_DBELL_RFCPEISL_IRQ14_CPE1 0x00004000 -#define RFC_DBELL_RFCPEISL_IRQ14_CPE0 0x00000000 - -// Field: [13] FG_COMMAND_STARTED -// -// Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_STARTED interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED 0x00002000 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_BITN 13 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_M 0x00002000 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_S 13 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE1 0x00002000 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_STARTED_CPE0 0x00000000 - -// Field: [12] COMMAND_STARTED -// -// Select which CPU interrupt vector the RFCPEIFG.COMMAND_STARTED interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_COMMAND_STARTED 0x00001000 -#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_BITN 12 -#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_M 0x00001000 -#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_S 12 -#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE1 0x00001000 -#define RFC_DBELL_RFCPEISL_COMMAND_STARTED_CPE0 0x00000000 - -// Field: [11] TX_BUFFER_CHANGED -// -// Select which CPU interrupt vector the RFCPEIFG.TX_BUFFER_CHANGED interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_BITN 11 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_M 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_S 11 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE1 0x00000800 -#define RFC_DBELL_RFCPEISL_TX_BUFFER_CHANGED_CPE0 0x00000000 - -// Field: [10] TX_ENTRY_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.TX_ENTRY_DONE interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_BITN 10 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_M 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_S 10 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE1 0x00000400 -#define RFC_DBELL_RFCPEISL_TX_ENTRY_DONE_CPE0 0x00000000 - -// Field: [9] TX_RETRANS -// -// Select which CPU interrupt vector the RFCPEIFG.TX_RETRANS interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_RETRANS 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_BITN 9 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_M 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_S 9 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE1 0x00000200 -#define RFC_DBELL_RFCPEISL_TX_RETRANS_CPE0 0x00000000 - -// Field: [8] TX_CTRL_ACK_ACK -// -// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK_ACK interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_BITN 8 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_M 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_S 8 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE1 0x00000100 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_ACK_CPE0 0x00000000 - -// Field: [7] TX_CTRL_ACK -// -// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL_ACK interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_BITN 7 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_M 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_S 7 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE1 0x00000080 -#define RFC_DBELL_RFCPEISL_TX_CTRL_ACK_CPE0 0x00000000 - -// Field: [6] TX_CTRL -// -// Select which CPU interrupt vector the RFCPEIFG.TX_CTRL interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_CTRL 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_BITN 6 -#define RFC_DBELL_RFCPEISL_TX_CTRL_M 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_S 6 -#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE1 0x00000040 -#define RFC_DBELL_RFCPEISL_TX_CTRL_CPE0 0x00000000 - -// Field: [5] TX_ACK -// -// Select which CPU interrupt vector the RFCPEIFG.TX_ACK interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_ACK 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_BITN 5 -#define RFC_DBELL_RFCPEISL_TX_ACK_M 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_S 5 -#define RFC_DBELL_RFCPEISL_TX_ACK_CPE1 0x00000020 -#define RFC_DBELL_RFCPEISL_TX_ACK_CPE0 0x00000000 - -// Field: [4] TX_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.TX_DONE interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_TX_DONE 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_BITN 4 -#define RFC_DBELL_RFCPEISL_TX_DONE_M 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_S 4 -#define RFC_DBELL_RFCPEISL_TX_DONE_CPE1 0x00000010 -#define RFC_DBELL_RFCPEISL_TX_DONE_CPE0 0x00000000 - -// Field: [3] LAST_FG_COMMAND_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.LAST_FG_COMMAND_DONE -// interrupt should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_BITN 3 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_M 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_S 3 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE1 0x00000008 -#define RFC_DBELL_RFCPEISL_LAST_FG_COMMAND_DONE_CPE0 0x00000000 - -// Field: [2] FG_COMMAND_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.FG_COMMAND_DONE interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_BITN 2 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_M 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_S 2 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE1 0x00000004 -#define RFC_DBELL_RFCPEISL_FG_COMMAND_DONE_CPE0 0x00000000 - -// Field: [1] LAST_COMMAND_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.LAST_COMMAND_DONE interrupt -// should use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_BITN 1 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_M 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_S 1 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE1 0x00000002 -#define RFC_DBELL_RFCPEISL_LAST_COMMAND_DONE_CPE0 0x00000000 - -// Field: [0] COMMAND_DONE -// -// Select which CPU interrupt vector the RFCPEIFG.COMMAND_DONE interrupt should -// use. -// ENUMs: -// CPE1 Associate this interrupt line with INT_RF_CPE1 -// interrupt vector -// CPE0 Associate this interrupt line with INT_RF_CPE0 -// interrupt vector -#define RFC_DBELL_RFCPEISL_COMMAND_DONE 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_BITN 0 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_M 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_S 0 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE1 0x00000001 -#define RFC_DBELL_RFCPEISL_COMMAND_DONE_CPE0 0x00000000 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_RFACKIFG -// -//***************************************************************************** -// Field: [0] ACKFLAG -// -// Interrupt flag for Command ACK -#define RFC_DBELL_RFACKIFG_ACKFLAG 0x00000001 -#define RFC_DBELL_RFACKIFG_ACKFLAG_BITN 0 -#define RFC_DBELL_RFACKIFG_ACKFLAG_M 0x00000001 -#define RFC_DBELL_RFACKIFG_ACKFLAG_S 0 - -//***************************************************************************** -// -// Register: RFC_DBELL_O_SYSGPOCTL -// -//***************************************************************************** -// Field: [15:12] GPOCTL3 -// -// RF Core GPO control bit 3. Selects which signal to output on the RF Core GPO -// line 3. -// ENUMs: -// RATGPO3 RAT GPO line 3 -// RATGPO2 RAT GPO line 2 -// RATGPO1 RAT GPO line 1 -// RATGPO0 RAT GPO line 0 -// RFEGPO3 RFE GPO line 3 -// RFEGPO2 RFE GPO line 2 -// RFEGPO1 RFE GPO line 1 -// RFEGPO0 RFE GPO line 0 -// MCEGPO3 MCE GPO line 3 -// MCEGPO2 MCE GPO line 2 -// MCEGPO1 MCE GPO line 1 -// MCEGPO0 MCE GPO line 0 -// CPEGPO3 CPE GPO line 3 -// CPEGPO2 CPE GPO line 2 -// CPEGPO1 CPE GPO line 1 -// CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_M 0x0000F000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_S 12 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO3 0x0000F000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO2 0x0000E000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO1 0x0000D000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RATGPO0 0x0000C000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO3 0x0000B000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO2 0x0000A000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO1 0x00009000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_RFEGPO0 0x00008000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO3 0x00007000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO2 0x00006000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO1 0x00005000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_MCEGPO0 0x00004000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO3 0x00003000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO2 0x00002000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO1 0x00001000 -#define RFC_DBELL_SYSGPOCTL_GPOCTL3_CPEGPO0 0x00000000 - -// Field: [11:8] GPOCTL2 -// -// RF Core GPO control bit 2. Selects which signal to output on the RF Core GPO -// line 2. -// ENUMs: -// RATGPO3 RAT GPO line 3 -// RATGPO2 RAT GPO line 2 -// RATGPO1 RAT GPO line 1 -// RATGPO0 RAT GPO line 0 -// RFEGPO3 RFE GPO line 3 -// RFEGPO2 RFE GPO line 2 -// RFEGPO1 RFE GPO line 1 -// RFEGPO0 RFE GPO line 0 -// MCEGPO3 MCE GPO line 3 -// MCEGPO2 MCE GPO line 2 -// MCEGPO1 MCE GPO line 1 -// MCEGPO0 MCE GPO line 0 -// CPEGPO3 CPE GPO line 3 -// CPEGPO2 CPE GPO line 2 -// CPEGPO1 CPE GPO line 1 -// CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_M 0x00000F00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_S 8 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO3 0x00000F00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO2 0x00000E00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO1 0x00000D00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RATGPO0 0x00000C00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO3 0x00000B00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO2 0x00000A00 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO1 0x00000900 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_RFEGPO0 0x00000800 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO3 0x00000700 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO2 0x00000600 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO1 0x00000500 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_MCEGPO0 0x00000400 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO3 0x00000300 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO2 0x00000200 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO1 0x00000100 -#define RFC_DBELL_SYSGPOCTL_GPOCTL2_CPEGPO0 0x00000000 - -// Field: [7:4] GPOCTL1 -// -// RF Core GPO control bit 1. Selects which signal to output on the RF Core GPO -// line 1. -// ENUMs: -// RATGPO3 RAT GPO line 3 -// RATGPO2 RAT GPO line 2 -// RATGPO1 RAT GPO line 1 -// RATGPO0 RAT GPO line 0 -// RFEGPO3 RFE GPO line 3 -// RFEGPO2 RFE GPO line 2 -// RFEGPO1 RFE GPO line 1 -// RFEGPO0 RFE GPO line 0 -// MCEGPO3 MCE GPO line 3 -// MCEGPO2 MCE GPO line 2 -// MCEGPO1 MCE GPO line 1 -// MCEGPO0 MCE GPO line 0 -// CPEGPO3 CPE GPO line 3 -// CPEGPO2 CPE GPO line 2 -// CPEGPO1 CPE GPO line 1 -// CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_M 0x000000F0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_S 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO3 0x000000F0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO2 0x000000E0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO1 0x000000D0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RATGPO0 0x000000C0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO3 0x000000B0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO2 0x000000A0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO1 0x00000090 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_RFEGPO0 0x00000080 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO3 0x00000070 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO2 0x00000060 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO1 0x00000050 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_MCEGPO0 0x00000040 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO3 0x00000030 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO2 0x00000020 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO1 0x00000010 -#define RFC_DBELL_SYSGPOCTL_GPOCTL1_CPEGPO0 0x00000000 - -// Field: [3:0] GPOCTL0 -// -// RF Core GPO control bit 0. Selects which signal to output on the RF Core GPO -// line 0. -// ENUMs: -// RATGPO3 RAT GPO line 3 -// RATGPO2 RAT GPO line 2 -// RATGPO1 RAT GPO line 1 -// RATGPO0 RAT GPO line 0 -// RFEGPO3 RFE GPO line 3 -// RFEGPO2 RFE GPO line 2 -// RFEGPO1 RFE GPO line 1 -// RFEGPO0 RFE GPO line 0 -// MCEGPO3 MCE GPO line 3 -// MCEGPO2 MCE GPO line 2 -// MCEGPO1 MCE GPO line 1 -// MCEGPO0 MCE GPO line 0 -// CPEGPO3 CPE GPO line 3 -// CPEGPO2 CPE GPO line 2 -// CPEGPO1 CPE GPO line 1 -// CPEGPO0 CPE GPO line 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_W 4 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_M 0x0000000F -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_S 0 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO3 0x0000000F -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO2 0x0000000E -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO1 0x0000000D -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RATGPO0 0x0000000C -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO3 0x0000000B -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO2 0x0000000A -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO1 0x00000009 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_RFEGPO0 0x00000008 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO3 0x00000007 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO2 0x00000006 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO1 0x00000005 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_MCEGPO0 0x00000004 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO3 0x00000003 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO2 0x00000002 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO1 0x00000001 -#define RFC_DBELL_SYSGPOCTL_GPOCTL0_CPEGPO0 0x00000000 - - -#endif // __RFC_DBELL__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h deleted file mode 100644 index 355626efd3a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_pwr.h +++ /dev/null @@ -1,153 +0,0 @@ -/****************************************************************************** -* Filename: hw_rfc_pwr_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_RFC_PWR_H__ -#define __HW_RFC_PWR_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// RFC_PWR component -// -//***************************************************************************** -// RF Core Power Management and Clock Enable -#define RFC_PWR_O_PWMCLKEN 0x00000000 - -//***************************************************************************** -// -// Register: RFC_PWR_O_PWMCLKEN -// -//***************************************************************************** -// Field: [10] RFCTRC -// -// Enable clock to the RF Core Tracer (RFCTRC) module. -#define RFC_PWR_PWMCLKEN_RFCTRC 0x00000400 -#define RFC_PWR_PWMCLKEN_RFCTRC_BITN 10 -#define RFC_PWR_PWMCLKEN_RFCTRC_M 0x00000400 -#define RFC_PWR_PWMCLKEN_RFCTRC_S 10 - -// Field: [9] FSCA -// -// Enable clock to the Frequency Synthesizer Calibration Accelerator (FSCA) -// module. -#define RFC_PWR_PWMCLKEN_FSCA 0x00000200 -#define RFC_PWR_PWMCLKEN_FSCA_BITN 9 -#define RFC_PWR_PWMCLKEN_FSCA_M 0x00000200 -#define RFC_PWR_PWMCLKEN_FSCA_S 9 - -// Field: [8] PHA -// -// Enable clock to the Packet Handling Accelerator (PHA) module. -#define RFC_PWR_PWMCLKEN_PHA 0x00000100 -#define RFC_PWR_PWMCLKEN_PHA_BITN 8 -#define RFC_PWR_PWMCLKEN_PHA_M 0x00000100 -#define RFC_PWR_PWMCLKEN_PHA_S 8 - -// Field: [7] RAT -// -// Enable clock to the Radio Timer (RAT) module. -#define RFC_PWR_PWMCLKEN_RAT 0x00000080 -#define RFC_PWR_PWMCLKEN_RAT_BITN 7 -#define RFC_PWR_PWMCLKEN_RAT_M 0x00000080 -#define RFC_PWR_PWMCLKEN_RAT_S 7 - -// Field: [6] RFERAM -// -// Enable clock to the RF Engine RAM module. -#define RFC_PWR_PWMCLKEN_RFERAM 0x00000040 -#define RFC_PWR_PWMCLKEN_RFERAM_BITN 6 -#define RFC_PWR_PWMCLKEN_RFERAM_M 0x00000040 -#define RFC_PWR_PWMCLKEN_RFERAM_S 6 - -// Field: [5] RFE -// -// Enable clock to the RF Engine (RFE) module. -#define RFC_PWR_PWMCLKEN_RFE 0x00000020 -#define RFC_PWR_PWMCLKEN_RFE_BITN 5 -#define RFC_PWR_PWMCLKEN_RFE_M 0x00000020 -#define RFC_PWR_PWMCLKEN_RFE_S 5 - -// Field: [4] MDMRAM -// -// Enable clock to the Modem RAM module. -#define RFC_PWR_PWMCLKEN_MDMRAM 0x00000010 -#define RFC_PWR_PWMCLKEN_MDMRAM_BITN 4 -#define RFC_PWR_PWMCLKEN_MDMRAM_M 0x00000010 -#define RFC_PWR_PWMCLKEN_MDMRAM_S 4 - -// Field: [3] MDM -// -// Enable clock to the Modem (MDM) module. -#define RFC_PWR_PWMCLKEN_MDM 0x00000008 -#define RFC_PWR_PWMCLKEN_MDM_BITN 3 -#define RFC_PWR_PWMCLKEN_MDM_M 0x00000008 -#define RFC_PWR_PWMCLKEN_MDM_S 3 - -// Field: [2] CPERAM -// -// Enable clock to the Command and Packet Engine (CPE) RAM module. As part of -// RF Core initialization, set this bit together with CPE bit to enable CPE to -// boot. -#define RFC_PWR_PWMCLKEN_CPERAM 0x00000004 -#define RFC_PWR_PWMCLKEN_CPERAM_BITN 2 -#define RFC_PWR_PWMCLKEN_CPERAM_M 0x00000004 -#define RFC_PWR_PWMCLKEN_CPERAM_S 2 - -// Field: [1] CPE -// -// Enable processor clock (hclk) to the Command and Packet Engine (CPE). As -// part of RF Core initialization, set this bit together with CPERAM bit to -// enable CPE to boot. -#define RFC_PWR_PWMCLKEN_CPE 0x00000002 -#define RFC_PWR_PWMCLKEN_CPE_BITN 1 -#define RFC_PWR_PWMCLKEN_CPE_M 0x00000002 -#define RFC_PWR_PWMCLKEN_CPE_S 1 - -// Field: [0] RFC -// -// Enable essential clocks for the RF Core interface. This includes the -// interconnect, the radio doorbell DBELL command interface, the power -// management (PWR) clock control module, and bus clock (sclk) for the CPE. To -// remove possibility of locking yourself out from the RF Core, this bit can -// not be cleared. If you need to disable all clocks to the RF Core, see the -// PRCM:RFCCLKG.CLK_EN register. -#define RFC_PWR_PWMCLKEN_RFC 0x00000001 -#define RFC_PWR_PWMCLKEN_RFC_BITN 0 -#define RFC_PWR_PWMCLKEN_RFC_M 0x00000001 -#define RFC_PWR_PWMCLKEN_RFC_S 0 - - -#endif // __RFC_PWR__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h deleted file mode 100644 index 4f68d8d2704..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_rat.h +++ /dev/null @@ -1,198 +0,0 @@ -/****************************************************************************** -* Filename: hw_rfc_rat_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_RFC_RAT_H__ -#define __HW_RFC_RAT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// RFC_RAT component -// -//***************************************************************************** -// Radio Timer Counter Value -#define RFC_RAT_O_RATCNT 0x00000004 - -// Timer Channel 0 Capture/Compare Register -#define RFC_RAT_O_RATCH0VAL 0x00000080 - -// Timer Channel 1 Capture/Compare Register -#define RFC_RAT_O_RATCH1VAL 0x00000084 - -// Timer Channel 2 Capture/Compare Register -#define RFC_RAT_O_RATCH2VAL 0x00000088 - -// Timer Channel 3 Capture/Compare Register -#define RFC_RAT_O_RATCH3VAL 0x0000008C - -// Timer Channel 4 Capture/Compare Register -#define RFC_RAT_O_RATCH4VAL 0x00000090 - -// Timer Channel 5 Capture/Compare Register -#define RFC_RAT_O_RATCH5VAL 0x00000094 - -// Timer Channel 6 Capture/Compare Register -#define RFC_RAT_O_RATCH6VAL 0x00000098 - -// Timer Channel 7 Capture/Compare Register -#define RFC_RAT_O_RATCH7VAL 0x0000009C - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCNT -// -//***************************************************************************** -// Field: [31:0] CNT -// -// Counter value. This is not writable while radio timer counter is enabled. -#define RFC_RAT_RATCNT_CNT_W 32 -#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF -#define RFC_RAT_RATCNT_CNT_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH0VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. Only writable when the channel is configured for -// compare mode. In compare mode, a write to this register will auto-arm the -// channel. -#define RFC_RAT_RATCH0VAL_VAL_W 32 -#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH0VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH1VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. Only writable when the channel is configured for -// compare mode. In compare mode, a write to this register will auto-arm the -// channel. -#define RFC_RAT_RATCH1VAL_VAL_W 32 -#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH1VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH2VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. Only writable when the channel is configured for -// compare mode. In compare mode, a write to this register will auto-arm the -// channel. -#define RFC_RAT_RATCH2VAL_VAL_W 32 -#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH2VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH3VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. Only writable when the channel is configured for -// compare mode. In compare mode, a write to this register will auto-arm the -// channel. -#define RFC_RAT_RATCH3VAL_VAL_W 32 -#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH3VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH4VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. Only writable when the channel is configured for -// compare mode. In compare mode, a write to this register will auto-arm the -// channel. -#define RFC_RAT_RATCH4VAL_VAL_W 32 -#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH4VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH5VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. Only writable when the channel is configured for -// compare mode. In compare mode, a write to this register will auto-arm the -// channel. -#define RFC_RAT_RATCH5VAL_VAL_W 32 -#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH5VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH6VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. Only writable when the channel is configured for -// compare mode. In compare mode, a write to this register will auto-arm the -// channel. -#define RFC_RAT_RATCH6VAL_VAL_W 32 -#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH6VAL_VAL_S 0 - -//***************************************************************************** -// -// Register: RFC_RAT_O_RATCH7VAL -// -//***************************************************************************** -// Field: [31:0] VAL -// -// Capture/compare value. Only writable when the channel is configured for -// compare mode. In compare mode, a write to this register will auto-arm the -// channel. -#define RFC_RAT_RATCH7VAL_VAL_W 32 -#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF -#define RFC_RAT_RATCH7VAL_VAL_S 0 - - -#endif // __RFC_RAT__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h deleted file mode 100644 index 0159b94b764..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_rfc_ullram.h +++ /dev/null @@ -1,30767 +0,0 @@ -/****************************************************************************** -* Filename: hw_rfc_ullram_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_RFC_ULLRAM_H__ -#define __HW_RFC_ULLRAM_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// RFC_ULLRAM component -// -//***************************************************************************** -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK10 0x00000000 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11 0x00000004 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12 0x00000008 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK13 0x0000000C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK14 0x00000010 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK15 0x00000014 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK16 0x00000018 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK17 0x0000001C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK18 0x00000020 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK19 0x00000024 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK110 0x00000028 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK111 0x0000002C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK112 0x00000030 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK113 0x00000034 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK114 0x00000038 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK115 0x0000003C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK116 0x00000040 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK117 0x00000044 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK118 0x00000048 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK119 0x0000004C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK120 0x00000050 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK121 0x00000054 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK122 0x00000058 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK123 0x0000005C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK124 0x00000060 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK125 0x00000064 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK126 0x00000068 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK127 0x0000006C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK128 0x00000070 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK129 0x00000074 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK130 0x00000078 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK131 0x0000007C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK132 0x00000080 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK133 0x00000084 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK134 0x00000088 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK135 0x0000008C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK136 0x00000090 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK137 0x00000094 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK138 0x00000098 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK139 0x0000009C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK140 0x000000A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK141 0x000000A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK142 0x000000A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK143 0x000000AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK144 0x000000B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK145 0x000000B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK146 0x000000B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK147 0x000000BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK148 0x000000C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK149 0x000000C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK150 0x000000C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK151 0x000000CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK152 0x000000D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK153 0x000000D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK154 0x000000D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK155 0x000000DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK156 0x000000E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK157 0x000000E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK158 0x000000E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK159 0x000000EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK160 0x000000F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK161 0x000000F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK162 0x000000F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK163 0x000000FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK164 0x00000100 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK165 0x00000104 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK166 0x00000108 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK167 0x0000010C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK168 0x00000110 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK169 0x00000114 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK170 0x00000118 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK171 0x0000011C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK172 0x00000120 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK173 0x00000124 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK174 0x00000128 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK175 0x0000012C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK176 0x00000130 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK177 0x00000134 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK178 0x00000138 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK179 0x0000013C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK180 0x00000140 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK181 0x00000144 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK182 0x00000148 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK183 0x0000014C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK184 0x00000150 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK185 0x00000154 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK186 0x00000158 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK187 0x0000015C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK188 0x00000160 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK189 0x00000164 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK190 0x00000168 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK191 0x0000016C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK192 0x00000170 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK193 0x00000174 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK194 0x00000178 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK195 0x0000017C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK196 0x00000180 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK197 0x00000184 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK198 0x00000188 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK199 0x0000018C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1100 0x00000190 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1101 0x00000194 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1102 0x00000198 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1103 0x0000019C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1104 0x000001A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1105 0x000001A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1106 0x000001A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1107 0x000001AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1108 0x000001B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1109 0x000001B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1110 0x000001B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1111 0x000001BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1112 0x000001C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1113 0x000001C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1114 0x000001C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1115 0x000001CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1116 0x000001D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1117 0x000001D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1118 0x000001D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1119 0x000001DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1120 0x000001E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1121 0x000001E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1122 0x000001E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1123 0x000001EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1124 0x000001F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1125 0x000001F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1126 0x000001F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1127 0x000001FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1128 0x00000200 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1129 0x00000204 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1130 0x00000208 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1131 0x0000020C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1132 0x00000210 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1133 0x00000214 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1134 0x00000218 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1135 0x0000021C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1136 0x00000220 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1137 0x00000224 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1138 0x00000228 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1139 0x0000022C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1140 0x00000230 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1141 0x00000234 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1142 0x00000238 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1143 0x0000023C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1144 0x00000240 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1145 0x00000244 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1146 0x00000248 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1147 0x0000024C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1148 0x00000250 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1149 0x00000254 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1150 0x00000258 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1151 0x0000025C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1152 0x00000260 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1153 0x00000264 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1154 0x00000268 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1155 0x0000026C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1156 0x00000270 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1157 0x00000274 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1158 0x00000278 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1159 0x0000027C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1160 0x00000280 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1161 0x00000284 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1162 0x00000288 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1163 0x0000028C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1164 0x00000290 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1165 0x00000294 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1166 0x00000298 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1167 0x0000029C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1168 0x000002A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1169 0x000002A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1170 0x000002A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1171 0x000002AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1172 0x000002B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1173 0x000002B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1174 0x000002B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1175 0x000002BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1176 0x000002C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1177 0x000002C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1178 0x000002C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1179 0x000002CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1180 0x000002D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1181 0x000002D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1182 0x000002D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1183 0x000002DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1184 0x000002E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1185 0x000002E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1186 0x000002E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1187 0x000002EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1188 0x000002F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1189 0x000002F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1190 0x000002F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1191 0x000002FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1192 0x00000300 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1193 0x00000304 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1194 0x00000308 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1195 0x0000030C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1196 0x00000310 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1197 0x00000314 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1198 0x00000318 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1199 0x0000031C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1200 0x00000320 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1201 0x00000324 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1202 0x00000328 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1203 0x0000032C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1204 0x00000330 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1205 0x00000334 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1206 0x00000338 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1207 0x0000033C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1208 0x00000340 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1209 0x00000344 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1210 0x00000348 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1211 0x0000034C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1212 0x00000350 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1213 0x00000354 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1214 0x00000358 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1215 0x0000035C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1216 0x00000360 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1217 0x00000364 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1218 0x00000368 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1219 0x0000036C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1220 0x00000370 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1221 0x00000374 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1222 0x00000378 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1223 0x0000037C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1224 0x00000380 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1225 0x00000384 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1226 0x00000388 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1227 0x0000038C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1228 0x00000390 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1229 0x00000394 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1230 0x00000398 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1231 0x0000039C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1232 0x000003A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1233 0x000003A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1234 0x000003A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1235 0x000003AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1236 0x000003B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1237 0x000003B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1238 0x000003B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1239 0x000003BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1240 0x000003C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1241 0x000003C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1242 0x000003C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1243 0x000003CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1244 0x000003D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1245 0x000003D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1246 0x000003D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1247 0x000003DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1248 0x000003E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1249 0x000003E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1250 0x000003E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1251 0x000003EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1252 0x000003F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1253 0x000003F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1254 0x000003F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1255 0x000003FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1256 0x00000400 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1257 0x00000404 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1258 0x00000408 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1259 0x0000040C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1260 0x00000410 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1261 0x00000414 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1262 0x00000418 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1263 0x0000041C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1264 0x00000420 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1265 0x00000424 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1266 0x00000428 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1267 0x0000042C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1268 0x00000430 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1269 0x00000434 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1270 0x00000438 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1271 0x0000043C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1272 0x00000440 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1273 0x00000444 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1274 0x00000448 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1275 0x0000044C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1276 0x00000450 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1277 0x00000454 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1278 0x00000458 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1279 0x0000045C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1280 0x00000460 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1281 0x00000464 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1282 0x00000468 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1283 0x0000046C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1284 0x00000470 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1285 0x00000474 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1286 0x00000478 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1287 0x0000047C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1288 0x00000480 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1289 0x00000484 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1290 0x00000488 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1291 0x0000048C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1292 0x00000490 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1293 0x00000494 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1294 0x00000498 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1295 0x0000049C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1296 0x000004A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1297 0x000004A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1298 0x000004A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1299 0x000004AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1300 0x000004B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1301 0x000004B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1302 0x000004B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1303 0x000004BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1304 0x000004C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1305 0x000004C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1306 0x000004C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1307 0x000004CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1308 0x000004D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1309 0x000004D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1310 0x000004D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1311 0x000004DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1312 0x000004E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1313 0x000004E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1314 0x000004E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1315 0x000004EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1316 0x000004F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1317 0x000004F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1318 0x000004F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1319 0x000004FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1320 0x00000500 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1321 0x00000504 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1322 0x00000508 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1323 0x0000050C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1324 0x00000510 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1325 0x00000514 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1326 0x00000518 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1327 0x0000051C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1328 0x00000520 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1329 0x00000524 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1330 0x00000528 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1331 0x0000052C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1332 0x00000530 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1333 0x00000534 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1334 0x00000538 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1335 0x0000053C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1336 0x00000540 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1337 0x00000544 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1338 0x00000548 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1339 0x0000054C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1340 0x00000550 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1341 0x00000554 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1342 0x00000558 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1343 0x0000055C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1344 0x00000560 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1345 0x00000564 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1346 0x00000568 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1347 0x0000056C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1348 0x00000570 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1349 0x00000574 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1350 0x00000578 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1351 0x0000057C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1352 0x00000580 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1353 0x00000584 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1354 0x00000588 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1355 0x0000058C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1356 0x00000590 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1357 0x00000594 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1358 0x00000598 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1359 0x0000059C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1360 0x000005A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1361 0x000005A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1362 0x000005A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1363 0x000005AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1364 0x000005B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1365 0x000005B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1366 0x000005B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1367 0x000005BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1368 0x000005C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1369 0x000005C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1370 0x000005C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1371 0x000005CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1372 0x000005D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1373 0x000005D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1374 0x000005D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1375 0x000005DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1376 0x000005E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1377 0x000005E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1378 0x000005E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1379 0x000005EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1380 0x000005F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1381 0x000005F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1382 0x000005F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1383 0x000005FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1384 0x00000600 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1385 0x00000604 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1386 0x00000608 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1387 0x0000060C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1388 0x00000610 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1389 0x00000614 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1390 0x00000618 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1391 0x0000061C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1392 0x00000620 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1393 0x00000624 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1394 0x00000628 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1395 0x0000062C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1396 0x00000630 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1397 0x00000634 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1398 0x00000638 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1399 0x0000063C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1400 0x00000640 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1401 0x00000644 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1402 0x00000648 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1403 0x0000064C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1404 0x00000650 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1405 0x00000654 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1406 0x00000658 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1407 0x0000065C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1408 0x00000660 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1409 0x00000664 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1410 0x00000668 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1411 0x0000066C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1412 0x00000670 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1413 0x00000674 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1414 0x00000678 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1415 0x0000067C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1416 0x00000680 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1417 0x00000684 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1418 0x00000688 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1419 0x0000068C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1420 0x00000690 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1421 0x00000694 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1422 0x00000698 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1423 0x0000069C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1424 0x000006A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1425 0x000006A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1426 0x000006A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1427 0x000006AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1428 0x000006B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1429 0x000006B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1430 0x000006B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1431 0x000006BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1432 0x000006C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1433 0x000006C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1434 0x000006C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1435 0x000006CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1436 0x000006D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1437 0x000006D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1438 0x000006D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1439 0x000006DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1440 0x000006E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1441 0x000006E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1442 0x000006E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1443 0x000006EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1444 0x000006F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1445 0x000006F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1446 0x000006F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1447 0x000006FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1448 0x00000700 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1449 0x00000704 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1450 0x00000708 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1451 0x0000070C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1452 0x00000710 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1453 0x00000714 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1454 0x00000718 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1455 0x0000071C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1456 0x00000720 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1457 0x00000724 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1458 0x00000728 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1459 0x0000072C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1460 0x00000730 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1461 0x00000734 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1462 0x00000738 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1463 0x0000073C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1464 0x00000740 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1465 0x00000744 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1466 0x00000748 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1467 0x0000074C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1468 0x00000750 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1469 0x00000754 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1470 0x00000758 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1471 0x0000075C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1472 0x00000760 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1473 0x00000764 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1474 0x00000768 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1475 0x0000076C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1476 0x00000770 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1477 0x00000774 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1478 0x00000778 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1479 0x0000077C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1480 0x00000780 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1481 0x00000784 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1482 0x00000788 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1483 0x0000078C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1484 0x00000790 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1485 0x00000794 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1486 0x00000798 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1487 0x0000079C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1488 0x000007A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1489 0x000007A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1490 0x000007A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1491 0x000007AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1492 0x000007B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1493 0x000007B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1494 0x000007B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1495 0x000007BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1496 0x000007C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1497 0x000007C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1498 0x000007C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1499 0x000007CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1500 0x000007D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1501 0x000007D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1502 0x000007D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1503 0x000007DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1504 0x000007E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1505 0x000007E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1506 0x000007E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1507 0x000007EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1508 0x000007F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1509 0x000007F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1510 0x000007F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1511 0x000007FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1512 0x00000800 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1513 0x00000804 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1514 0x00000808 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1515 0x0000080C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1516 0x00000810 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1517 0x00000814 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1518 0x00000818 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1519 0x0000081C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1520 0x00000820 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1521 0x00000824 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1522 0x00000828 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1523 0x0000082C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1524 0x00000830 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1525 0x00000834 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1526 0x00000838 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1527 0x0000083C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1528 0x00000840 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1529 0x00000844 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1530 0x00000848 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1531 0x0000084C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1532 0x00000850 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1533 0x00000854 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1534 0x00000858 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1535 0x0000085C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1536 0x00000860 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1537 0x00000864 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1538 0x00000868 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1539 0x0000086C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1540 0x00000870 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1541 0x00000874 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1542 0x00000878 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1543 0x0000087C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1544 0x00000880 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1545 0x00000884 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1546 0x00000888 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1547 0x0000088C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1548 0x00000890 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1549 0x00000894 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1550 0x00000898 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1551 0x0000089C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1552 0x000008A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1553 0x000008A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1554 0x000008A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1555 0x000008AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1556 0x000008B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1557 0x000008B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1558 0x000008B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1559 0x000008BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1560 0x000008C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1561 0x000008C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1562 0x000008C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1563 0x000008CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1564 0x000008D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1565 0x000008D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1566 0x000008D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1567 0x000008DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1568 0x000008E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1569 0x000008E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1570 0x000008E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1571 0x000008EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1572 0x000008F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1573 0x000008F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1574 0x000008F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1575 0x000008FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1576 0x00000900 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1577 0x00000904 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1578 0x00000908 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1579 0x0000090C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1580 0x00000910 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1581 0x00000914 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1582 0x00000918 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1583 0x0000091C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1584 0x00000920 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1585 0x00000924 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1586 0x00000928 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1587 0x0000092C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1588 0x00000930 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1589 0x00000934 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1590 0x00000938 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1591 0x0000093C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1592 0x00000940 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1593 0x00000944 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1594 0x00000948 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1595 0x0000094C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1596 0x00000950 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1597 0x00000954 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1598 0x00000958 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1599 0x0000095C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1600 0x00000960 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1601 0x00000964 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1602 0x00000968 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1603 0x0000096C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1604 0x00000970 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1605 0x00000974 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1606 0x00000978 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1607 0x0000097C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1608 0x00000980 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1609 0x00000984 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1610 0x00000988 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1611 0x0000098C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1612 0x00000990 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1613 0x00000994 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1614 0x00000998 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1615 0x0000099C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1616 0x000009A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1617 0x000009A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1618 0x000009A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1619 0x000009AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1620 0x000009B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1621 0x000009B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1622 0x000009B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1623 0x000009BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1624 0x000009C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1625 0x000009C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1626 0x000009C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1627 0x000009CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1628 0x000009D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1629 0x000009D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1630 0x000009D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1631 0x000009DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1632 0x000009E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1633 0x000009E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1634 0x000009E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1635 0x000009EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1636 0x000009F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1637 0x000009F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1638 0x000009F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1639 0x000009FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1640 0x00000A00 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1641 0x00000A04 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1642 0x00000A08 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1643 0x00000A0C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1644 0x00000A10 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1645 0x00000A14 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1646 0x00000A18 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1647 0x00000A1C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1648 0x00000A20 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1649 0x00000A24 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1650 0x00000A28 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1651 0x00000A2C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1652 0x00000A30 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1653 0x00000A34 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1654 0x00000A38 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1655 0x00000A3C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1656 0x00000A40 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1657 0x00000A44 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1658 0x00000A48 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1659 0x00000A4C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1660 0x00000A50 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1661 0x00000A54 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1662 0x00000A58 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1663 0x00000A5C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1664 0x00000A60 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1665 0x00000A64 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1666 0x00000A68 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1667 0x00000A6C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1668 0x00000A70 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1669 0x00000A74 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1670 0x00000A78 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1671 0x00000A7C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1672 0x00000A80 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1673 0x00000A84 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1674 0x00000A88 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1675 0x00000A8C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1676 0x00000A90 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1677 0x00000A94 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1678 0x00000A98 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1679 0x00000A9C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1680 0x00000AA0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1681 0x00000AA4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1682 0x00000AA8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1683 0x00000AAC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1684 0x00000AB0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1685 0x00000AB4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1686 0x00000AB8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1687 0x00000ABC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1688 0x00000AC0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1689 0x00000AC4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1690 0x00000AC8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1691 0x00000ACC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1692 0x00000AD0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1693 0x00000AD4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1694 0x00000AD8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1695 0x00000ADC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1696 0x00000AE0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1697 0x00000AE4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1698 0x00000AE8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1699 0x00000AEC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1700 0x00000AF0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1701 0x00000AF4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1702 0x00000AF8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1703 0x00000AFC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1704 0x00000B00 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1705 0x00000B04 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1706 0x00000B08 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1707 0x00000B0C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1708 0x00000B10 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1709 0x00000B14 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1710 0x00000B18 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1711 0x00000B1C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1712 0x00000B20 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1713 0x00000B24 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1714 0x00000B28 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1715 0x00000B2C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1716 0x00000B30 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1717 0x00000B34 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1718 0x00000B38 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1719 0x00000B3C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1720 0x00000B40 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1721 0x00000B44 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1722 0x00000B48 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1723 0x00000B4C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1724 0x00000B50 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1725 0x00000B54 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1726 0x00000B58 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1727 0x00000B5C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1728 0x00000B60 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1729 0x00000B64 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1730 0x00000B68 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1731 0x00000B6C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1732 0x00000B70 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1733 0x00000B74 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1734 0x00000B78 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1735 0x00000B7C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1736 0x00000B80 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1737 0x00000B84 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1738 0x00000B88 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1739 0x00000B8C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1740 0x00000B90 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1741 0x00000B94 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1742 0x00000B98 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1743 0x00000B9C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1744 0x00000BA0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1745 0x00000BA4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1746 0x00000BA8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1747 0x00000BAC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1748 0x00000BB0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1749 0x00000BB4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1750 0x00000BB8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1751 0x00000BBC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1752 0x00000BC0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1753 0x00000BC4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1754 0x00000BC8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1755 0x00000BCC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1756 0x00000BD0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1757 0x00000BD4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1758 0x00000BD8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1759 0x00000BDC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1760 0x00000BE0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1761 0x00000BE4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1762 0x00000BE8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1763 0x00000BEC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1764 0x00000BF0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1765 0x00000BF4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1766 0x00000BF8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1767 0x00000BFC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1768 0x00000C00 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1769 0x00000C04 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1770 0x00000C08 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1771 0x00000C0C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1772 0x00000C10 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1773 0x00000C14 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1774 0x00000C18 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1775 0x00000C1C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1776 0x00000C20 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1777 0x00000C24 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1778 0x00000C28 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1779 0x00000C2C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1780 0x00000C30 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1781 0x00000C34 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1782 0x00000C38 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1783 0x00000C3C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1784 0x00000C40 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1785 0x00000C44 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1786 0x00000C48 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1787 0x00000C4C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1788 0x00000C50 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1789 0x00000C54 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1790 0x00000C58 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1791 0x00000C5C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1792 0x00000C60 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1793 0x00000C64 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1794 0x00000C68 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1795 0x00000C6C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1796 0x00000C70 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1797 0x00000C74 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1798 0x00000C78 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1799 0x00000C7C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1800 0x00000C80 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1801 0x00000C84 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1802 0x00000C88 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1803 0x00000C8C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1804 0x00000C90 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1805 0x00000C94 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1806 0x00000C98 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1807 0x00000C9C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1808 0x00000CA0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1809 0x00000CA4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1810 0x00000CA8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1811 0x00000CAC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1812 0x00000CB0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1813 0x00000CB4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1814 0x00000CB8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1815 0x00000CBC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1816 0x00000CC0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1817 0x00000CC4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1818 0x00000CC8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1819 0x00000CCC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1820 0x00000CD0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1821 0x00000CD4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1822 0x00000CD8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1823 0x00000CDC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1824 0x00000CE0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1825 0x00000CE4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1826 0x00000CE8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1827 0x00000CEC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1828 0x00000CF0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1829 0x00000CF4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1830 0x00000CF8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1831 0x00000CFC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1832 0x00000D00 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1833 0x00000D04 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1834 0x00000D08 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1835 0x00000D0C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1836 0x00000D10 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1837 0x00000D14 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1838 0x00000D18 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1839 0x00000D1C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1840 0x00000D20 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1841 0x00000D24 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1842 0x00000D28 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1843 0x00000D2C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1844 0x00000D30 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1845 0x00000D34 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1846 0x00000D38 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1847 0x00000D3C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1848 0x00000D40 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1849 0x00000D44 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1850 0x00000D48 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1851 0x00000D4C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1852 0x00000D50 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1853 0x00000D54 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1854 0x00000D58 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1855 0x00000D5C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1856 0x00000D60 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1857 0x00000D64 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1858 0x00000D68 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1859 0x00000D6C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1860 0x00000D70 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1861 0x00000D74 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1862 0x00000D78 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1863 0x00000D7C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1864 0x00000D80 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1865 0x00000D84 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1866 0x00000D88 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1867 0x00000D8C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1868 0x00000D90 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1869 0x00000D94 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1870 0x00000D98 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1871 0x00000D9C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1872 0x00000DA0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1873 0x00000DA4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1874 0x00000DA8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1875 0x00000DAC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1876 0x00000DB0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1877 0x00000DB4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1878 0x00000DB8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1879 0x00000DBC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1880 0x00000DC0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1881 0x00000DC4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1882 0x00000DC8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1883 0x00000DCC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1884 0x00000DD0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1885 0x00000DD4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1886 0x00000DD8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1887 0x00000DDC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1888 0x00000DE0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1889 0x00000DE4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1890 0x00000DE8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1891 0x00000DEC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1892 0x00000DF0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1893 0x00000DF4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1894 0x00000DF8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1895 0x00000DFC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1896 0x00000E00 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1897 0x00000E04 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1898 0x00000E08 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1899 0x00000E0C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1900 0x00000E10 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1901 0x00000E14 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1902 0x00000E18 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1903 0x00000E1C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1904 0x00000E20 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1905 0x00000E24 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1906 0x00000E28 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1907 0x00000E2C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1908 0x00000E30 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1909 0x00000E34 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1910 0x00000E38 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1911 0x00000E3C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1912 0x00000E40 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1913 0x00000E44 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1914 0x00000E48 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1915 0x00000E4C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1916 0x00000E50 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1917 0x00000E54 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1918 0x00000E58 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1919 0x00000E5C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1920 0x00000E60 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1921 0x00000E64 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1922 0x00000E68 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1923 0x00000E6C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1924 0x00000E70 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1925 0x00000E74 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1926 0x00000E78 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1927 0x00000E7C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1928 0x00000E80 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1929 0x00000E84 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1930 0x00000E88 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1931 0x00000E8C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1932 0x00000E90 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1933 0x00000E94 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1934 0x00000E98 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1935 0x00000E9C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1936 0x00000EA0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1937 0x00000EA4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1938 0x00000EA8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1939 0x00000EAC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1940 0x00000EB0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1941 0x00000EB4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1942 0x00000EB8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1943 0x00000EBC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1944 0x00000EC0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1945 0x00000EC4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1946 0x00000EC8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1947 0x00000ECC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1948 0x00000ED0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1949 0x00000ED4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1950 0x00000ED8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1951 0x00000EDC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1952 0x00000EE0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1953 0x00000EE4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1954 0x00000EE8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1955 0x00000EEC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1956 0x00000EF0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1957 0x00000EF4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1958 0x00000EF8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1959 0x00000EFC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1960 0x00000F00 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1961 0x00000F04 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1962 0x00000F08 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1963 0x00000F0C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1964 0x00000F10 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1965 0x00000F14 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1966 0x00000F18 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1967 0x00000F1C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1968 0x00000F20 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1969 0x00000F24 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1970 0x00000F28 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1971 0x00000F2C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1972 0x00000F30 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1973 0x00000F34 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1974 0x00000F38 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1975 0x00000F3C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1976 0x00000F40 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1977 0x00000F44 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1978 0x00000F48 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1979 0x00000F4C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1980 0x00000F50 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1981 0x00000F54 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1982 0x00000F58 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1983 0x00000F5C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1984 0x00000F60 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1985 0x00000F64 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1986 0x00000F68 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1987 0x00000F6C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1988 0x00000F70 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1989 0x00000F74 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1990 0x00000F78 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1991 0x00000F7C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1992 0x00000F80 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1993 0x00000F84 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1994 0x00000F88 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1995 0x00000F8C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1996 0x00000F90 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1997 0x00000F94 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1998 0x00000F98 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK1999 0x00000F9C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11000 0x00000FA0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11001 0x00000FA4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11002 0x00000FA8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11003 0x00000FAC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11004 0x00000FB0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11005 0x00000FB4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11006 0x00000FB8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11007 0x00000FBC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11008 0x00000FC0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11009 0x00000FC4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11010 0x00000FC8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11011 0x00000FCC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11012 0x00000FD0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11013 0x00000FD4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11014 0x00000FD8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11015 0x00000FDC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11016 0x00000FE0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11017 0x00000FE4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11018 0x00000FE8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11019 0x00000FEC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11020 0x00000FF0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11021 0x00000FF4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11022 0x00000FF8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11023 0x00000FFC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11024 0x00001000 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11025 0x00001004 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11026 0x00001008 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11027 0x0000100C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11028 0x00001010 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11029 0x00001014 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11030 0x00001018 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11031 0x0000101C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11032 0x00001020 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11033 0x00001024 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11034 0x00001028 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11035 0x0000102C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11036 0x00001030 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11037 0x00001034 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11038 0x00001038 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11039 0x0000103C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11040 0x00001040 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11041 0x00001044 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11042 0x00001048 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11043 0x0000104C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11044 0x00001050 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11045 0x00001054 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11046 0x00001058 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11047 0x0000105C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11048 0x00001060 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11049 0x00001064 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11050 0x00001068 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11051 0x0000106C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11052 0x00001070 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11053 0x00001074 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11054 0x00001078 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11055 0x0000107C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11056 0x00001080 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11057 0x00001084 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11058 0x00001088 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11059 0x0000108C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11060 0x00001090 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11061 0x00001094 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11062 0x00001098 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11063 0x0000109C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11064 0x000010A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11065 0x000010A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11066 0x000010A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11067 0x000010AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11068 0x000010B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11069 0x000010B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11070 0x000010B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11071 0x000010BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11072 0x000010C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11073 0x000010C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11074 0x000010C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11075 0x000010CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11076 0x000010D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11077 0x000010D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11078 0x000010D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11079 0x000010DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11080 0x000010E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11081 0x000010E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11082 0x000010E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11083 0x000010EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11084 0x000010F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11085 0x000010F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11086 0x000010F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11087 0x000010FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11088 0x00001100 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11089 0x00001104 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11090 0x00001108 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11091 0x0000110C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11092 0x00001110 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11093 0x00001114 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11094 0x00001118 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11095 0x0000111C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11096 0x00001120 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11097 0x00001124 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11098 0x00001128 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11099 0x0000112C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11100 0x00001130 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11101 0x00001134 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11102 0x00001138 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11103 0x0000113C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11104 0x00001140 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11105 0x00001144 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11106 0x00001148 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11107 0x0000114C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11108 0x00001150 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11109 0x00001154 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11110 0x00001158 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11111 0x0000115C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11112 0x00001160 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11113 0x00001164 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11114 0x00001168 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11115 0x0000116C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11116 0x00001170 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11117 0x00001174 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11118 0x00001178 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11119 0x0000117C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11120 0x00001180 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11121 0x00001184 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11122 0x00001188 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11123 0x0000118C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11124 0x00001190 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11125 0x00001194 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11126 0x00001198 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11127 0x0000119C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11128 0x000011A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11129 0x000011A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11130 0x000011A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11131 0x000011AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11132 0x000011B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11133 0x000011B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11134 0x000011B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11135 0x000011BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11136 0x000011C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11137 0x000011C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11138 0x000011C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11139 0x000011CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11140 0x000011D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11141 0x000011D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11142 0x000011D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11143 0x000011DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11144 0x000011E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11145 0x000011E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11146 0x000011E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11147 0x000011EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11148 0x000011F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11149 0x000011F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11150 0x000011F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11151 0x000011FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11152 0x00001200 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11153 0x00001204 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11154 0x00001208 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11155 0x0000120C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11156 0x00001210 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11157 0x00001214 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11158 0x00001218 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11159 0x0000121C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11160 0x00001220 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11161 0x00001224 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11162 0x00001228 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11163 0x0000122C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11164 0x00001230 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11165 0x00001234 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11166 0x00001238 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11167 0x0000123C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11168 0x00001240 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11169 0x00001244 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11170 0x00001248 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11171 0x0000124C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11172 0x00001250 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11173 0x00001254 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11174 0x00001258 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11175 0x0000125C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11176 0x00001260 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11177 0x00001264 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11178 0x00001268 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11179 0x0000126C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11180 0x00001270 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11181 0x00001274 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11182 0x00001278 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11183 0x0000127C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11184 0x00001280 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11185 0x00001284 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11186 0x00001288 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11187 0x0000128C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11188 0x00001290 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11189 0x00001294 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11190 0x00001298 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11191 0x0000129C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11192 0x000012A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11193 0x000012A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11194 0x000012A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11195 0x000012AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11196 0x000012B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11197 0x000012B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11198 0x000012B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11199 0x000012BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11200 0x000012C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11201 0x000012C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11202 0x000012C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11203 0x000012CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11204 0x000012D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11205 0x000012D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11206 0x000012D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11207 0x000012DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11208 0x000012E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11209 0x000012E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11210 0x000012E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11211 0x000012EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11212 0x000012F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11213 0x000012F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11214 0x000012F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11215 0x000012FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11216 0x00001300 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11217 0x00001304 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11218 0x00001308 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11219 0x0000130C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11220 0x00001310 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11221 0x00001314 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11222 0x00001318 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11223 0x0000131C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11224 0x00001320 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11225 0x00001324 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11226 0x00001328 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11227 0x0000132C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11228 0x00001330 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11229 0x00001334 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11230 0x00001338 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11231 0x0000133C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11232 0x00001340 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11233 0x00001344 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11234 0x00001348 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11235 0x0000134C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11236 0x00001350 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11237 0x00001354 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11238 0x00001358 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11239 0x0000135C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11240 0x00001360 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11241 0x00001364 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11242 0x00001368 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11243 0x0000136C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11244 0x00001370 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11245 0x00001374 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11246 0x00001378 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11247 0x0000137C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11248 0x00001380 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11249 0x00001384 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11250 0x00001388 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11251 0x0000138C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11252 0x00001390 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11253 0x00001394 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11254 0x00001398 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11255 0x0000139C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11256 0x000013A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11257 0x000013A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11258 0x000013A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11259 0x000013AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11260 0x000013B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11261 0x000013B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11262 0x000013B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11263 0x000013BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11264 0x000013C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11265 0x000013C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11266 0x000013C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11267 0x000013CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11268 0x000013D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11269 0x000013D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11270 0x000013D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11271 0x000013DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11272 0x000013E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11273 0x000013E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11274 0x000013E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11275 0x000013EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11276 0x000013F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11277 0x000013F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11278 0x000013F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11279 0x000013FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11280 0x00001400 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11281 0x00001404 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11282 0x00001408 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11283 0x0000140C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11284 0x00001410 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11285 0x00001414 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11286 0x00001418 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11287 0x0000141C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11288 0x00001420 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11289 0x00001424 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11290 0x00001428 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11291 0x0000142C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11292 0x00001430 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11293 0x00001434 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11294 0x00001438 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11295 0x0000143C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11296 0x00001440 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11297 0x00001444 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11298 0x00001448 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11299 0x0000144C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11300 0x00001450 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11301 0x00001454 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11302 0x00001458 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11303 0x0000145C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11304 0x00001460 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11305 0x00001464 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11306 0x00001468 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11307 0x0000146C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11308 0x00001470 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11309 0x00001474 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11310 0x00001478 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11311 0x0000147C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11312 0x00001480 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11313 0x00001484 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11314 0x00001488 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11315 0x0000148C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11316 0x00001490 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11317 0x00001494 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11318 0x00001498 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11319 0x0000149C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11320 0x000014A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11321 0x000014A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11322 0x000014A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11323 0x000014AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11324 0x000014B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11325 0x000014B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11326 0x000014B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11327 0x000014BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11328 0x000014C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11329 0x000014C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11330 0x000014C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11331 0x000014CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11332 0x000014D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11333 0x000014D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11334 0x000014D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11335 0x000014DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11336 0x000014E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11337 0x000014E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11338 0x000014E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11339 0x000014EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11340 0x000014F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11341 0x000014F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11342 0x000014F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11343 0x000014FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11344 0x00001500 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11345 0x00001504 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11346 0x00001508 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11347 0x0000150C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11348 0x00001510 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11349 0x00001514 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11350 0x00001518 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11351 0x0000151C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11352 0x00001520 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11353 0x00001524 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11354 0x00001528 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11355 0x0000152C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11356 0x00001530 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11357 0x00001534 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11358 0x00001538 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11359 0x0000153C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11360 0x00001540 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11361 0x00001544 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11362 0x00001548 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11363 0x0000154C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11364 0x00001550 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11365 0x00001554 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11366 0x00001558 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11367 0x0000155C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11368 0x00001560 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11369 0x00001564 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11370 0x00001568 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11371 0x0000156C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11372 0x00001570 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11373 0x00001574 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11374 0x00001578 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11375 0x0000157C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11376 0x00001580 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11377 0x00001584 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11378 0x00001588 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11379 0x0000158C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11380 0x00001590 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11381 0x00001594 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11382 0x00001598 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11383 0x0000159C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11384 0x000015A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11385 0x000015A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11386 0x000015A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11387 0x000015AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11388 0x000015B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11389 0x000015B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11390 0x000015B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11391 0x000015BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11392 0x000015C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11393 0x000015C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11394 0x000015C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11395 0x000015CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11396 0x000015D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11397 0x000015D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11398 0x000015D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11399 0x000015DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11400 0x000015E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11401 0x000015E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11402 0x000015E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11403 0x000015EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11404 0x000015F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11405 0x000015F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11406 0x000015F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11407 0x000015FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11408 0x00001600 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11409 0x00001604 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11410 0x00001608 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11411 0x0000160C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11412 0x00001610 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11413 0x00001614 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11414 0x00001618 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11415 0x0000161C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11416 0x00001620 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11417 0x00001624 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11418 0x00001628 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11419 0x0000162C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11420 0x00001630 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11421 0x00001634 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11422 0x00001638 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11423 0x0000163C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11424 0x00001640 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11425 0x00001644 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11426 0x00001648 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11427 0x0000164C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11428 0x00001650 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11429 0x00001654 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11430 0x00001658 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11431 0x0000165C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11432 0x00001660 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11433 0x00001664 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11434 0x00001668 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11435 0x0000166C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11436 0x00001670 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11437 0x00001674 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11438 0x00001678 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11439 0x0000167C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11440 0x00001680 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11441 0x00001684 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11442 0x00001688 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11443 0x0000168C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11444 0x00001690 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11445 0x00001694 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11446 0x00001698 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11447 0x0000169C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11448 0x000016A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11449 0x000016A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11450 0x000016A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11451 0x000016AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11452 0x000016B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11453 0x000016B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11454 0x000016B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11455 0x000016BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11456 0x000016C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11457 0x000016C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11458 0x000016C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11459 0x000016CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11460 0x000016D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11461 0x000016D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11462 0x000016D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11463 0x000016DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11464 0x000016E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11465 0x000016E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11466 0x000016E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11467 0x000016EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11468 0x000016F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11469 0x000016F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11470 0x000016F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11471 0x000016FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11472 0x00001700 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11473 0x00001704 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11474 0x00001708 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11475 0x0000170C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11476 0x00001710 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11477 0x00001714 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11478 0x00001718 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11479 0x0000171C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11480 0x00001720 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11481 0x00001724 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11482 0x00001728 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11483 0x0000172C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11484 0x00001730 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11485 0x00001734 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11486 0x00001738 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11487 0x0000173C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11488 0x00001740 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11489 0x00001744 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11490 0x00001748 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11491 0x0000174C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11492 0x00001750 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11493 0x00001754 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11494 0x00001758 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11495 0x0000175C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11496 0x00001760 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11497 0x00001764 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11498 0x00001768 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11499 0x0000176C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11500 0x00001770 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11501 0x00001774 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11502 0x00001778 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11503 0x0000177C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11504 0x00001780 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11505 0x00001784 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11506 0x00001788 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11507 0x0000178C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11508 0x00001790 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11509 0x00001794 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11510 0x00001798 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11511 0x0000179C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11512 0x000017A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11513 0x000017A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11514 0x000017A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11515 0x000017AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11516 0x000017B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11517 0x000017B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11518 0x000017B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11519 0x000017BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11520 0x000017C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11521 0x000017C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11522 0x000017C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11523 0x000017CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11524 0x000017D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11525 0x000017D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11526 0x000017D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11527 0x000017DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11528 0x000017E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11529 0x000017E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11530 0x000017E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11531 0x000017EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11532 0x000017F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11533 0x000017F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11534 0x000017F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11535 0x000017FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11536 0x00001800 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11537 0x00001804 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11538 0x00001808 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11539 0x0000180C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11540 0x00001810 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11541 0x00001814 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11542 0x00001818 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11543 0x0000181C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11544 0x00001820 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11545 0x00001824 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11546 0x00001828 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11547 0x0000182C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11548 0x00001830 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11549 0x00001834 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11550 0x00001838 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11551 0x0000183C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11552 0x00001840 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11553 0x00001844 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11554 0x00001848 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11555 0x0000184C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11556 0x00001850 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11557 0x00001854 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11558 0x00001858 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11559 0x0000185C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11560 0x00001860 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11561 0x00001864 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11562 0x00001868 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11563 0x0000186C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11564 0x00001870 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11565 0x00001874 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11566 0x00001878 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11567 0x0000187C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11568 0x00001880 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11569 0x00001884 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11570 0x00001888 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11571 0x0000188C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11572 0x00001890 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11573 0x00001894 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11574 0x00001898 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11575 0x0000189C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11576 0x000018A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11577 0x000018A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11578 0x000018A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11579 0x000018AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11580 0x000018B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11581 0x000018B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11582 0x000018B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11583 0x000018BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11584 0x000018C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11585 0x000018C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11586 0x000018C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11587 0x000018CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11588 0x000018D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11589 0x000018D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11590 0x000018D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11591 0x000018DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11592 0x000018E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11593 0x000018E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11594 0x000018E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11595 0x000018EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11596 0x000018F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11597 0x000018F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11598 0x000018F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11599 0x000018FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11600 0x00001900 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11601 0x00001904 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11602 0x00001908 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11603 0x0000190C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11604 0x00001910 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11605 0x00001914 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11606 0x00001918 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11607 0x0000191C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11608 0x00001920 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11609 0x00001924 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11610 0x00001928 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11611 0x0000192C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11612 0x00001930 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11613 0x00001934 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11614 0x00001938 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11615 0x0000193C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11616 0x00001940 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11617 0x00001944 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11618 0x00001948 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11619 0x0000194C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11620 0x00001950 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11621 0x00001954 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11622 0x00001958 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11623 0x0000195C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11624 0x00001960 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11625 0x00001964 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11626 0x00001968 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11627 0x0000196C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11628 0x00001970 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11629 0x00001974 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11630 0x00001978 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11631 0x0000197C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11632 0x00001980 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11633 0x00001984 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11634 0x00001988 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11635 0x0000198C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11636 0x00001990 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11637 0x00001994 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11638 0x00001998 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11639 0x0000199C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11640 0x000019A0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11641 0x000019A4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11642 0x000019A8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11643 0x000019AC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11644 0x000019B0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11645 0x000019B4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11646 0x000019B8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11647 0x000019BC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11648 0x000019C0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11649 0x000019C4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11650 0x000019C8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11651 0x000019CC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11652 0x000019D0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11653 0x000019D4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11654 0x000019D8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11655 0x000019DC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11656 0x000019E0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11657 0x000019E4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11658 0x000019E8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11659 0x000019EC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11660 0x000019F0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11661 0x000019F4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11662 0x000019F8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11663 0x000019FC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11664 0x00001A00 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11665 0x00001A04 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11666 0x00001A08 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11667 0x00001A0C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11668 0x00001A10 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11669 0x00001A14 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11670 0x00001A18 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11671 0x00001A1C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11672 0x00001A20 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11673 0x00001A24 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11674 0x00001A28 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11675 0x00001A2C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11676 0x00001A30 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11677 0x00001A34 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11678 0x00001A38 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11679 0x00001A3C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11680 0x00001A40 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11681 0x00001A44 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11682 0x00001A48 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11683 0x00001A4C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11684 0x00001A50 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11685 0x00001A54 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11686 0x00001A58 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11687 0x00001A5C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11688 0x00001A60 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11689 0x00001A64 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11690 0x00001A68 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11691 0x00001A6C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11692 0x00001A70 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11693 0x00001A74 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11694 0x00001A78 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11695 0x00001A7C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11696 0x00001A80 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11697 0x00001A84 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11698 0x00001A88 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11699 0x00001A8C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11700 0x00001A90 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11701 0x00001A94 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11702 0x00001A98 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11703 0x00001A9C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11704 0x00001AA0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11705 0x00001AA4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11706 0x00001AA8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11707 0x00001AAC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11708 0x00001AB0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11709 0x00001AB4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11710 0x00001AB8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11711 0x00001ABC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11712 0x00001AC0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11713 0x00001AC4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11714 0x00001AC8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11715 0x00001ACC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11716 0x00001AD0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11717 0x00001AD4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11718 0x00001AD8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11719 0x00001ADC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11720 0x00001AE0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11721 0x00001AE4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11722 0x00001AE8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11723 0x00001AEC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11724 0x00001AF0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11725 0x00001AF4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11726 0x00001AF8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11727 0x00001AFC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11728 0x00001B00 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11729 0x00001B04 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11730 0x00001B08 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11731 0x00001B0C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11732 0x00001B10 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11733 0x00001B14 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11734 0x00001B18 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11735 0x00001B1C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11736 0x00001B20 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11737 0x00001B24 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11738 0x00001B28 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11739 0x00001B2C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11740 0x00001B30 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11741 0x00001B34 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11742 0x00001B38 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11743 0x00001B3C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11744 0x00001B40 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11745 0x00001B44 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11746 0x00001B48 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11747 0x00001B4C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11748 0x00001B50 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11749 0x00001B54 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11750 0x00001B58 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11751 0x00001B5C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11752 0x00001B60 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11753 0x00001B64 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11754 0x00001B68 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11755 0x00001B6C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11756 0x00001B70 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11757 0x00001B74 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11758 0x00001B78 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11759 0x00001B7C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11760 0x00001B80 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11761 0x00001B84 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11762 0x00001B88 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11763 0x00001B8C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11764 0x00001B90 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11765 0x00001B94 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11766 0x00001B98 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11767 0x00001B9C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11768 0x00001BA0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11769 0x00001BA4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11770 0x00001BA8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11771 0x00001BAC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11772 0x00001BB0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11773 0x00001BB4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11774 0x00001BB8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11775 0x00001BBC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11776 0x00001BC0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11777 0x00001BC4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11778 0x00001BC8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11779 0x00001BCC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11780 0x00001BD0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11781 0x00001BD4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11782 0x00001BD8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11783 0x00001BDC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11784 0x00001BE0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11785 0x00001BE4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11786 0x00001BE8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11787 0x00001BEC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11788 0x00001BF0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11789 0x00001BF4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11790 0x00001BF8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11791 0x00001BFC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11792 0x00001C00 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11793 0x00001C04 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11794 0x00001C08 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11795 0x00001C0C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11796 0x00001C10 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11797 0x00001C14 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11798 0x00001C18 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11799 0x00001C1C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11800 0x00001C20 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11801 0x00001C24 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11802 0x00001C28 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11803 0x00001C2C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11804 0x00001C30 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11805 0x00001C34 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11806 0x00001C38 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11807 0x00001C3C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11808 0x00001C40 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11809 0x00001C44 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11810 0x00001C48 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11811 0x00001C4C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11812 0x00001C50 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11813 0x00001C54 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11814 0x00001C58 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11815 0x00001C5C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11816 0x00001C60 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11817 0x00001C64 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11818 0x00001C68 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11819 0x00001C6C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11820 0x00001C70 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11821 0x00001C74 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11822 0x00001C78 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11823 0x00001C7C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11824 0x00001C80 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11825 0x00001C84 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11826 0x00001C88 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11827 0x00001C8C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11828 0x00001C90 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11829 0x00001C94 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11830 0x00001C98 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11831 0x00001C9C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11832 0x00001CA0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11833 0x00001CA4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11834 0x00001CA8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11835 0x00001CAC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11836 0x00001CB0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11837 0x00001CB4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11838 0x00001CB8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11839 0x00001CBC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11840 0x00001CC0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11841 0x00001CC4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11842 0x00001CC8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11843 0x00001CCC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11844 0x00001CD0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11845 0x00001CD4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11846 0x00001CD8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11847 0x00001CDC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11848 0x00001CE0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11849 0x00001CE4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11850 0x00001CE8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11851 0x00001CEC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11852 0x00001CF0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11853 0x00001CF4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11854 0x00001CF8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11855 0x00001CFC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11856 0x00001D00 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11857 0x00001D04 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11858 0x00001D08 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11859 0x00001D0C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11860 0x00001D10 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11861 0x00001D14 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11862 0x00001D18 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11863 0x00001D1C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11864 0x00001D20 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11865 0x00001D24 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11866 0x00001D28 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11867 0x00001D2C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11868 0x00001D30 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11869 0x00001D34 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11870 0x00001D38 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11871 0x00001D3C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11872 0x00001D40 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11873 0x00001D44 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11874 0x00001D48 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11875 0x00001D4C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11876 0x00001D50 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11877 0x00001D54 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11878 0x00001D58 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11879 0x00001D5C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11880 0x00001D60 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11881 0x00001D64 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11882 0x00001D68 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11883 0x00001D6C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11884 0x00001D70 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11885 0x00001D74 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11886 0x00001D78 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11887 0x00001D7C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11888 0x00001D80 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11889 0x00001D84 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11890 0x00001D88 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11891 0x00001D8C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11892 0x00001D90 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11893 0x00001D94 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11894 0x00001D98 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11895 0x00001D9C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11896 0x00001DA0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11897 0x00001DA4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11898 0x00001DA8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11899 0x00001DAC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11900 0x00001DB0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11901 0x00001DB4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11902 0x00001DB8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11903 0x00001DBC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11904 0x00001DC0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11905 0x00001DC4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11906 0x00001DC8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11907 0x00001DCC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11908 0x00001DD0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11909 0x00001DD4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11910 0x00001DD8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11911 0x00001DDC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11912 0x00001DE0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11913 0x00001DE4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11914 0x00001DE8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11915 0x00001DEC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11916 0x00001DF0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11917 0x00001DF4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11918 0x00001DF8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11919 0x00001DFC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11920 0x00001E00 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11921 0x00001E04 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11922 0x00001E08 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11923 0x00001E0C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11924 0x00001E10 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11925 0x00001E14 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11926 0x00001E18 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11927 0x00001E1C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11928 0x00001E20 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11929 0x00001E24 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11930 0x00001E28 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11931 0x00001E2C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11932 0x00001E30 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11933 0x00001E34 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11934 0x00001E38 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11935 0x00001E3C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11936 0x00001E40 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11937 0x00001E44 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11938 0x00001E48 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11939 0x00001E4C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11940 0x00001E50 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11941 0x00001E54 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11942 0x00001E58 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11943 0x00001E5C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11944 0x00001E60 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11945 0x00001E64 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11946 0x00001E68 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11947 0x00001E6C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11948 0x00001E70 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11949 0x00001E74 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11950 0x00001E78 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11951 0x00001E7C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11952 0x00001E80 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11953 0x00001E84 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11954 0x00001E88 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11955 0x00001E8C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11956 0x00001E90 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11957 0x00001E94 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11958 0x00001E98 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11959 0x00001E9C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11960 0x00001EA0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11961 0x00001EA4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11962 0x00001EA8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11963 0x00001EAC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11964 0x00001EB0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11965 0x00001EB4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11966 0x00001EB8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11967 0x00001EBC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11968 0x00001EC0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11969 0x00001EC4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11970 0x00001EC8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11971 0x00001ECC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11972 0x00001ED0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11973 0x00001ED4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11974 0x00001ED8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11975 0x00001EDC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11976 0x00001EE0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11977 0x00001EE4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11978 0x00001EE8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11979 0x00001EEC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11980 0x00001EF0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11981 0x00001EF4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11982 0x00001EF8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11983 0x00001EFC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11984 0x00001F00 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11985 0x00001F04 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11986 0x00001F08 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11987 0x00001F0C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11988 0x00001F10 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11989 0x00001F14 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11990 0x00001F18 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11991 0x00001F1C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11992 0x00001F20 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11993 0x00001F24 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11994 0x00001F28 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11995 0x00001F2C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11996 0x00001F30 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11997 0x00001F34 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11998 0x00001F38 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK11999 0x00001F3C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12000 0x00001F40 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12001 0x00001F44 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12002 0x00001F48 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12003 0x00001F4C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12004 0x00001F50 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12005 0x00001F54 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12006 0x00001F58 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12007 0x00001F5C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12008 0x00001F60 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12009 0x00001F64 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12010 0x00001F68 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12011 0x00001F6C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12012 0x00001F70 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12013 0x00001F74 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12014 0x00001F78 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12015 0x00001F7C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12016 0x00001F80 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12017 0x00001F84 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12018 0x00001F88 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12019 0x00001F8C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12020 0x00001F90 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12021 0x00001F94 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12022 0x00001F98 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12023 0x00001F9C - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12024 0x00001FA0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12025 0x00001FA4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12026 0x00001FA8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12027 0x00001FAC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12028 0x00001FB0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12029 0x00001FB4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12030 0x00001FB8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12031 0x00001FBC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12032 0x00001FC0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12033 0x00001FC4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12034 0x00001FC8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12035 0x00001FCC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12036 0x00001FD0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12037 0x00001FD4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12038 0x00001FD8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12039 0x00001FDC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12040 0x00001FE0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12041 0x00001FE4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12042 0x00001FE8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12043 0x00001FEC - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12044 0x00001FF0 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12045 0x00001FF4 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12046 0x00001FF8 - -// 8 kB ULL SRAM -#define RFC_ULLRAM_O_BANK12047 0x00001FFC - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK10 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK10_DATA_W 32 -#define RFC_ULLRAM_BANK10_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK10_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11_DATA_W 32 -#define RFC_ULLRAM_BANK11_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12_DATA_W 32 -#define RFC_ULLRAM_BANK12_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK13 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK13_DATA_W 32 -#define RFC_ULLRAM_BANK13_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK13_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK14 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK14_DATA_W 32 -#define RFC_ULLRAM_BANK14_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK14_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK15 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK15_DATA_W 32 -#define RFC_ULLRAM_BANK15_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK15_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK16 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK16_DATA_W 32 -#define RFC_ULLRAM_BANK16_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK16_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK17 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK17_DATA_W 32 -#define RFC_ULLRAM_BANK17_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK17_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK18 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK18_DATA_W 32 -#define RFC_ULLRAM_BANK18_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK18_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK19 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK19_DATA_W 32 -#define RFC_ULLRAM_BANK19_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK19_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK110 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK110_DATA_W 32 -#define RFC_ULLRAM_BANK110_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK110_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK111 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK111_DATA_W 32 -#define RFC_ULLRAM_BANK111_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK111_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK112 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK112_DATA_W 32 -#define RFC_ULLRAM_BANK112_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK112_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK113 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK113_DATA_W 32 -#define RFC_ULLRAM_BANK113_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK113_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK114 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK114_DATA_W 32 -#define RFC_ULLRAM_BANK114_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK114_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK115 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK115_DATA_W 32 -#define RFC_ULLRAM_BANK115_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK115_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK116 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK116_DATA_W 32 -#define RFC_ULLRAM_BANK116_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK116_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK117 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK117_DATA_W 32 -#define RFC_ULLRAM_BANK117_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK117_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK118 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK118_DATA_W 32 -#define RFC_ULLRAM_BANK118_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK118_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK119 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK119_DATA_W 32 -#define RFC_ULLRAM_BANK119_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK119_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK120 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK120_DATA_W 32 -#define RFC_ULLRAM_BANK120_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK120_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK121 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK121_DATA_W 32 -#define RFC_ULLRAM_BANK121_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK121_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK122 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK122_DATA_W 32 -#define RFC_ULLRAM_BANK122_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK122_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK123 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK123_DATA_W 32 -#define RFC_ULLRAM_BANK123_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK123_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK124 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK124_DATA_W 32 -#define RFC_ULLRAM_BANK124_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK124_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK125 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK125_DATA_W 32 -#define RFC_ULLRAM_BANK125_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK125_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK126 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK126_DATA_W 32 -#define RFC_ULLRAM_BANK126_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK126_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK127 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK127_DATA_W 32 -#define RFC_ULLRAM_BANK127_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK127_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK128 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK128_DATA_W 32 -#define RFC_ULLRAM_BANK128_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK128_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK129 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK129_DATA_W 32 -#define RFC_ULLRAM_BANK129_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK129_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK130 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK130_DATA_W 32 -#define RFC_ULLRAM_BANK130_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK130_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK131 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK131_DATA_W 32 -#define RFC_ULLRAM_BANK131_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK131_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK132 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK132_DATA_W 32 -#define RFC_ULLRAM_BANK132_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK132_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK133 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK133_DATA_W 32 -#define RFC_ULLRAM_BANK133_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK133_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK134 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK134_DATA_W 32 -#define RFC_ULLRAM_BANK134_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK134_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK135 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK135_DATA_W 32 -#define RFC_ULLRAM_BANK135_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK135_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK136 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK136_DATA_W 32 -#define RFC_ULLRAM_BANK136_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK136_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK137 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK137_DATA_W 32 -#define RFC_ULLRAM_BANK137_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK137_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK138 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK138_DATA_W 32 -#define RFC_ULLRAM_BANK138_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK138_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK139 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK139_DATA_W 32 -#define RFC_ULLRAM_BANK139_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK139_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK140 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK140_DATA_W 32 -#define RFC_ULLRAM_BANK140_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK140_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK141 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK141_DATA_W 32 -#define RFC_ULLRAM_BANK141_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK141_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK142 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK142_DATA_W 32 -#define RFC_ULLRAM_BANK142_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK142_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK143 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK143_DATA_W 32 -#define RFC_ULLRAM_BANK143_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK143_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK144 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK144_DATA_W 32 -#define RFC_ULLRAM_BANK144_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK144_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK145 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK145_DATA_W 32 -#define RFC_ULLRAM_BANK145_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK145_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK146 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK146_DATA_W 32 -#define RFC_ULLRAM_BANK146_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK146_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK147 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK147_DATA_W 32 -#define RFC_ULLRAM_BANK147_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK147_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK148 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK148_DATA_W 32 -#define RFC_ULLRAM_BANK148_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK148_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK149 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK149_DATA_W 32 -#define RFC_ULLRAM_BANK149_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK149_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK150 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK150_DATA_W 32 -#define RFC_ULLRAM_BANK150_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK150_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK151 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK151_DATA_W 32 -#define RFC_ULLRAM_BANK151_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK151_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK152 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK152_DATA_W 32 -#define RFC_ULLRAM_BANK152_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK152_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK153 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK153_DATA_W 32 -#define RFC_ULLRAM_BANK153_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK153_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK154 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK154_DATA_W 32 -#define RFC_ULLRAM_BANK154_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK154_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK155 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK155_DATA_W 32 -#define RFC_ULLRAM_BANK155_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK155_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK156 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK156_DATA_W 32 -#define RFC_ULLRAM_BANK156_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK156_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK157 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK157_DATA_W 32 -#define RFC_ULLRAM_BANK157_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK157_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK158 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK158_DATA_W 32 -#define RFC_ULLRAM_BANK158_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK158_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK159 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK159_DATA_W 32 -#define RFC_ULLRAM_BANK159_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK159_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK160 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK160_DATA_W 32 -#define RFC_ULLRAM_BANK160_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK160_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK161 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK161_DATA_W 32 -#define RFC_ULLRAM_BANK161_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK161_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK162 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK162_DATA_W 32 -#define RFC_ULLRAM_BANK162_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK162_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK163 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK163_DATA_W 32 -#define RFC_ULLRAM_BANK163_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK163_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK164 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK164_DATA_W 32 -#define RFC_ULLRAM_BANK164_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK164_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK165 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK165_DATA_W 32 -#define RFC_ULLRAM_BANK165_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK165_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK166 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK166_DATA_W 32 -#define RFC_ULLRAM_BANK166_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK166_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK167 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK167_DATA_W 32 -#define RFC_ULLRAM_BANK167_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK167_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK168 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK168_DATA_W 32 -#define RFC_ULLRAM_BANK168_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK168_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK169 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK169_DATA_W 32 -#define RFC_ULLRAM_BANK169_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK169_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK170 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK170_DATA_W 32 -#define RFC_ULLRAM_BANK170_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK170_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK171 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK171_DATA_W 32 -#define RFC_ULLRAM_BANK171_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK171_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK172 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK172_DATA_W 32 -#define RFC_ULLRAM_BANK172_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK172_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK173 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK173_DATA_W 32 -#define RFC_ULLRAM_BANK173_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK173_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK174 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK174_DATA_W 32 -#define RFC_ULLRAM_BANK174_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK174_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK175 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK175_DATA_W 32 -#define RFC_ULLRAM_BANK175_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK175_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK176 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK176_DATA_W 32 -#define RFC_ULLRAM_BANK176_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK176_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK177 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK177_DATA_W 32 -#define RFC_ULLRAM_BANK177_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK177_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK178 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK178_DATA_W 32 -#define RFC_ULLRAM_BANK178_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK178_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK179 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK179_DATA_W 32 -#define RFC_ULLRAM_BANK179_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK179_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK180 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK180_DATA_W 32 -#define RFC_ULLRAM_BANK180_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK180_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK181 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK181_DATA_W 32 -#define RFC_ULLRAM_BANK181_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK181_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK182 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK182_DATA_W 32 -#define RFC_ULLRAM_BANK182_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK182_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK183 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK183_DATA_W 32 -#define RFC_ULLRAM_BANK183_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK183_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK184 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK184_DATA_W 32 -#define RFC_ULLRAM_BANK184_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK184_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK185 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK185_DATA_W 32 -#define RFC_ULLRAM_BANK185_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK185_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK186 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK186_DATA_W 32 -#define RFC_ULLRAM_BANK186_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK186_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK187 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK187_DATA_W 32 -#define RFC_ULLRAM_BANK187_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK187_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK188 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK188_DATA_W 32 -#define RFC_ULLRAM_BANK188_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK188_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK189 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK189_DATA_W 32 -#define RFC_ULLRAM_BANK189_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK189_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK190 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK190_DATA_W 32 -#define RFC_ULLRAM_BANK190_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK190_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK191 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK191_DATA_W 32 -#define RFC_ULLRAM_BANK191_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK191_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK192 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK192_DATA_W 32 -#define RFC_ULLRAM_BANK192_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK192_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK193 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK193_DATA_W 32 -#define RFC_ULLRAM_BANK193_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK193_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK194 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK194_DATA_W 32 -#define RFC_ULLRAM_BANK194_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK194_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK195 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK195_DATA_W 32 -#define RFC_ULLRAM_BANK195_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK195_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK196 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK196_DATA_W 32 -#define RFC_ULLRAM_BANK196_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK196_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK197 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK197_DATA_W 32 -#define RFC_ULLRAM_BANK197_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK197_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK198 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK198_DATA_W 32 -#define RFC_ULLRAM_BANK198_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK198_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK199 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK199_DATA_W 32 -#define RFC_ULLRAM_BANK199_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK199_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1100 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1100_DATA_W 32 -#define RFC_ULLRAM_BANK1100_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1100_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1101 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1101_DATA_W 32 -#define RFC_ULLRAM_BANK1101_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1101_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1102 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1102_DATA_W 32 -#define RFC_ULLRAM_BANK1102_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1102_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1103 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1103_DATA_W 32 -#define RFC_ULLRAM_BANK1103_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1103_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1104 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1104_DATA_W 32 -#define RFC_ULLRAM_BANK1104_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1104_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1105 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1105_DATA_W 32 -#define RFC_ULLRAM_BANK1105_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1105_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1106 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1106_DATA_W 32 -#define RFC_ULLRAM_BANK1106_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1106_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1107 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1107_DATA_W 32 -#define RFC_ULLRAM_BANK1107_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1107_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1108 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1108_DATA_W 32 -#define RFC_ULLRAM_BANK1108_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1108_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1109 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1109_DATA_W 32 -#define RFC_ULLRAM_BANK1109_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1109_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1110 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1110_DATA_W 32 -#define RFC_ULLRAM_BANK1110_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1110_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1111 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1111_DATA_W 32 -#define RFC_ULLRAM_BANK1111_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1111_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1112 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1112_DATA_W 32 -#define RFC_ULLRAM_BANK1112_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1112_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1113 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1113_DATA_W 32 -#define RFC_ULLRAM_BANK1113_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1113_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1114 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1114_DATA_W 32 -#define RFC_ULLRAM_BANK1114_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1114_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1115 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1115_DATA_W 32 -#define RFC_ULLRAM_BANK1115_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1115_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1116 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1116_DATA_W 32 -#define RFC_ULLRAM_BANK1116_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1116_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1117 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1117_DATA_W 32 -#define RFC_ULLRAM_BANK1117_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1117_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1118 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1118_DATA_W 32 -#define RFC_ULLRAM_BANK1118_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1118_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1119 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1119_DATA_W 32 -#define RFC_ULLRAM_BANK1119_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1119_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1120 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1120_DATA_W 32 -#define RFC_ULLRAM_BANK1120_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1120_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1121 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1121_DATA_W 32 -#define RFC_ULLRAM_BANK1121_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1121_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1122 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1122_DATA_W 32 -#define RFC_ULLRAM_BANK1122_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1122_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1123 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1123_DATA_W 32 -#define RFC_ULLRAM_BANK1123_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1123_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1124 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1124_DATA_W 32 -#define RFC_ULLRAM_BANK1124_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1124_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1125 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1125_DATA_W 32 -#define RFC_ULLRAM_BANK1125_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1125_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1126 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1126_DATA_W 32 -#define RFC_ULLRAM_BANK1126_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1126_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1127 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1127_DATA_W 32 -#define RFC_ULLRAM_BANK1127_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1127_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1128 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1128_DATA_W 32 -#define RFC_ULLRAM_BANK1128_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1128_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1129 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1129_DATA_W 32 -#define RFC_ULLRAM_BANK1129_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1129_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1130 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1130_DATA_W 32 -#define RFC_ULLRAM_BANK1130_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1130_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1131 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1131_DATA_W 32 -#define RFC_ULLRAM_BANK1131_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1131_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1132 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1132_DATA_W 32 -#define RFC_ULLRAM_BANK1132_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1132_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1133 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1133_DATA_W 32 -#define RFC_ULLRAM_BANK1133_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1133_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1134 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1134_DATA_W 32 -#define RFC_ULLRAM_BANK1134_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1134_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1135 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1135_DATA_W 32 -#define RFC_ULLRAM_BANK1135_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1135_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1136 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1136_DATA_W 32 -#define RFC_ULLRAM_BANK1136_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1136_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1137 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1137_DATA_W 32 -#define RFC_ULLRAM_BANK1137_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1137_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1138 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1138_DATA_W 32 -#define RFC_ULLRAM_BANK1138_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1138_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1139 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1139_DATA_W 32 -#define RFC_ULLRAM_BANK1139_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1139_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1140 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1140_DATA_W 32 -#define RFC_ULLRAM_BANK1140_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1140_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1141 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1141_DATA_W 32 -#define RFC_ULLRAM_BANK1141_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1141_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1142 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1142_DATA_W 32 -#define RFC_ULLRAM_BANK1142_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1142_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1143 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1143_DATA_W 32 -#define RFC_ULLRAM_BANK1143_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1143_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1144 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1144_DATA_W 32 -#define RFC_ULLRAM_BANK1144_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1144_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1145 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1145_DATA_W 32 -#define RFC_ULLRAM_BANK1145_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1145_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1146 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1146_DATA_W 32 -#define RFC_ULLRAM_BANK1146_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1146_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1147 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1147_DATA_W 32 -#define RFC_ULLRAM_BANK1147_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1147_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1148 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1148_DATA_W 32 -#define RFC_ULLRAM_BANK1148_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1148_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1149 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1149_DATA_W 32 -#define RFC_ULLRAM_BANK1149_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1149_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1150 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1150_DATA_W 32 -#define RFC_ULLRAM_BANK1150_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1150_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1151 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1151_DATA_W 32 -#define RFC_ULLRAM_BANK1151_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1151_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1152 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1152_DATA_W 32 -#define RFC_ULLRAM_BANK1152_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1152_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1153 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1153_DATA_W 32 -#define RFC_ULLRAM_BANK1153_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1153_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1154 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1154_DATA_W 32 -#define RFC_ULLRAM_BANK1154_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1154_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1155 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1155_DATA_W 32 -#define RFC_ULLRAM_BANK1155_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1155_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1156 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1156_DATA_W 32 -#define RFC_ULLRAM_BANK1156_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1156_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1157 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1157_DATA_W 32 -#define RFC_ULLRAM_BANK1157_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1157_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1158 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1158_DATA_W 32 -#define RFC_ULLRAM_BANK1158_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1158_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1159 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1159_DATA_W 32 -#define RFC_ULLRAM_BANK1159_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1159_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1160 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1160_DATA_W 32 -#define RFC_ULLRAM_BANK1160_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1160_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1161 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1161_DATA_W 32 -#define RFC_ULLRAM_BANK1161_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1161_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1162 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1162_DATA_W 32 -#define RFC_ULLRAM_BANK1162_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1162_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1163 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1163_DATA_W 32 -#define RFC_ULLRAM_BANK1163_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1163_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1164 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1164_DATA_W 32 -#define RFC_ULLRAM_BANK1164_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1164_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1165 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1165_DATA_W 32 -#define RFC_ULLRAM_BANK1165_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1165_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1166 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1166_DATA_W 32 -#define RFC_ULLRAM_BANK1166_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1166_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1167 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1167_DATA_W 32 -#define RFC_ULLRAM_BANK1167_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1167_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1168 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1168_DATA_W 32 -#define RFC_ULLRAM_BANK1168_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1168_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1169 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1169_DATA_W 32 -#define RFC_ULLRAM_BANK1169_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1169_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1170 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1170_DATA_W 32 -#define RFC_ULLRAM_BANK1170_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1170_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1171 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1171_DATA_W 32 -#define RFC_ULLRAM_BANK1171_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1171_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1172 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1172_DATA_W 32 -#define RFC_ULLRAM_BANK1172_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1172_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1173 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1173_DATA_W 32 -#define RFC_ULLRAM_BANK1173_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1173_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1174 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1174_DATA_W 32 -#define RFC_ULLRAM_BANK1174_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1174_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1175 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1175_DATA_W 32 -#define RFC_ULLRAM_BANK1175_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1175_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1176 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1176_DATA_W 32 -#define RFC_ULLRAM_BANK1176_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1176_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1177 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1177_DATA_W 32 -#define RFC_ULLRAM_BANK1177_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1177_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1178 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1178_DATA_W 32 -#define RFC_ULLRAM_BANK1178_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1178_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1179 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1179_DATA_W 32 -#define RFC_ULLRAM_BANK1179_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1179_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1180 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1180_DATA_W 32 -#define RFC_ULLRAM_BANK1180_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1180_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1181 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1181_DATA_W 32 -#define RFC_ULLRAM_BANK1181_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1181_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1182 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1182_DATA_W 32 -#define RFC_ULLRAM_BANK1182_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1182_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1183 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1183_DATA_W 32 -#define RFC_ULLRAM_BANK1183_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1183_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1184 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1184_DATA_W 32 -#define RFC_ULLRAM_BANK1184_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1184_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1185 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1185_DATA_W 32 -#define RFC_ULLRAM_BANK1185_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1185_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1186 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1186_DATA_W 32 -#define RFC_ULLRAM_BANK1186_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1186_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1187 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1187_DATA_W 32 -#define RFC_ULLRAM_BANK1187_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1187_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1188 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1188_DATA_W 32 -#define RFC_ULLRAM_BANK1188_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1188_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1189 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1189_DATA_W 32 -#define RFC_ULLRAM_BANK1189_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1189_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1190 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1190_DATA_W 32 -#define RFC_ULLRAM_BANK1190_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1190_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1191 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1191_DATA_W 32 -#define RFC_ULLRAM_BANK1191_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1191_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1192 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1192_DATA_W 32 -#define RFC_ULLRAM_BANK1192_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1192_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1193 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1193_DATA_W 32 -#define RFC_ULLRAM_BANK1193_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1193_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1194 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1194_DATA_W 32 -#define RFC_ULLRAM_BANK1194_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1194_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1195 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1195_DATA_W 32 -#define RFC_ULLRAM_BANK1195_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1195_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1196 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1196_DATA_W 32 -#define RFC_ULLRAM_BANK1196_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1196_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1197 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1197_DATA_W 32 -#define RFC_ULLRAM_BANK1197_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1197_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1198 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1198_DATA_W 32 -#define RFC_ULLRAM_BANK1198_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1198_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1199 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1199_DATA_W 32 -#define RFC_ULLRAM_BANK1199_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1199_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1200 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1200_DATA_W 32 -#define RFC_ULLRAM_BANK1200_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1200_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1201 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1201_DATA_W 32 -#define RFC_ULLRAM_BANK1201_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1201_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1202 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1202_DATA_W 32 -#define RFC_ULLRAM_BANK1202_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1202_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1203 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1203_DATA_W 32 -#define RFC_ULLRAM_BANK1203_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1203_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1204 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1204_DATA_W 32 -#define RFC_ULLRAM_BANK1204_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1204_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1205 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1205_DATA_W 32 -#define RFC_ULLRAM_BANK1205_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1205_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1206 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1206_DATA_W 32 -#define RFC_ULLRAM_BANK1206_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1206_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1207 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1207_DATA_W 32 -#define RFC_ULLRAM_BANK1207_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1207_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1208 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1208_DATA_W 32 -#define RFC_ULLRAM_BANK1208_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1208_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1209 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1209_DATA_W 32 -#define RFC_ULLRAM_BANK1209_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1209_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1210 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1210_DATA_W 32 -#define RFC_ULLRAM_BANK1210_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1210_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1211 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1211_DATA_W 32 -#define RFC_ULLRAM_BANK1211_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1211_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1212 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1212_DATA_W 32 -#define RFC_ULLRAM_BANK1212_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1212_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1213 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1213_DATA_W 32 -#define RFC_ULLRAM_BANK1213_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1213_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1214 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1214_DATA_W 32 -#define RFC_ULLRAM_BANK1214_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1214_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1215 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1215_DATA_W 32 -#define RFC_ULLRAM_BANK1215_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1215_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1216 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1216_DATA_W 32 -#define RFC_ULLRAM_BANK1216_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1216_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1217 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1217_DATA_W 32 -#define RFC_ULLRAM_BANK1217_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1217_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1218 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1218_DATA_W 32 -#define RFC_ULLRAM_BANK1218_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1218_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1219 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1219_DATA_W 32 -#define RFC_ULLRAM_BANK1219_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1219_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1220 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1220_DATA_W 32 -#define RFC_ULLRAM_BANK1220_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1220_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1221 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1221_DATA_W 32 -#define RFC_ULLRAM_BANK1221_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1221_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1222 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1222_DATA_W 32 -#define RFC_ULLRAM_BANK1222_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1222_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1223 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1223_DATA_W 32 -#define RFC_ULLRAM_BANK1223_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1223_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1224 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1224_DATA_W 32 -#define RFC_ULLRAM_BANK1224_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1224_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1225 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1225_DATA_W 32 -#define RFC_ULLRAM_BANK1225_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1225_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1226 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1226_DATA_W 32 -#define RFC_ULLRAM_BANK1226_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1226_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1227 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1227_DATA_W 32 -#define RFC_ULLRAM_BANK1227_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1227_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1228 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1228_DATA_W 32 -#define RFC_ULLRAM_BANK1228_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1228_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1229 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1229_DATA_W 32 -#define RFC_ULLRAM_BANK1229_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1229_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1230 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1230_DATA_W 32 -#define RFC_ULLRAM_BANK1230_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1230_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1231 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1231_DATA_W 32 -#define RFC_ULLRAM_BANK1231_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1231_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1232 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1232_DATA_W 32 -#define RFC_ULLRAM_BANK1232_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1232_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1233 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1233_DATA_W 32 -#define RFC_ULLRAM_BANK1233_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1233_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1234 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1234_DATA_W 32 -#define RFC_ULLRAM_BANK1234_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1234_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1235 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1235_DATA_W 32 -#define RFC_ULLRAM_BANK1235_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1235_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1236 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1236_DATA_W 32 -#define RFC_ULLRAM_BANK1236_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1236_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1237 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1237_DATA_W 32 -#define RFC_ULLRAM_BANK1237_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1237_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1238 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1238_DATA_W 32 -#define RFC_ULLRAM_BANK1238_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1238_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1239 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1239_DATA_W 32 -#define RFC_ULLRAM_BANK1239_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1239_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1240 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1240_DATA_W 32 -#define RFC_ULLRAM_BANK1240_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1240_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1241 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1241_DATA_W 32 -#define RFC_ULLRAM_BANK1241_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1241_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1242 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1242_DATA_W 32 -#define RFC_ULLRAM_BANK1242_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1242_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1243 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1243_DATA_W 32 -#define RFC_ULLRAM_BANK1243_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1243_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1244 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1244_DATA_W 32 -#define RFC_ULLRAM_BANK1244_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1244_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1245 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1245_DATA_W 32 -#define RFC_ULLRAM_BANK1245_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1245_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1246 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1246_DATA_W 32 -#define RFC_ULLRAM_BANK1246_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1246_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1247 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1247_DATA_W 32 -#define RFC_ULLRAM_BANK1247_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1247_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1248 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1248_DATA_W 32 -#define RFC_ULLRAM_BANK1248_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1248_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1249 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1249_DATA_W 32 -#define RFC_ULLRAM_BANK1249_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1249_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1250 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1250_DATA_W 32 -#define RFC_ULLRAM_BANK1250_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1250_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1251 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1251_DATA_W 32 -#define RFC_ULLRAM_BANK1251_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1251_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1252 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1252_DATA_W 32 -#define RFC_ULLRAM_BANK1252_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1252_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1253 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1253_DATA_W 32 -#define RFC_ULLRAM_BANK1253_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1253_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1254 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1254_DATA_W 32 -#define RFC_ULLRAM_BANK1254_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1254_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1255 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1255_DATA_W 32 -#define RFC_ULLRAM_BANK1255_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1255_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1256 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1256_DATA_W 32 -#define RFC_ULLRAM_BANK1256_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1256_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1257 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1257_DATA_W 32 -#define RFC_ULLRAM_BANK1257_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1257_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1258 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1258_DATA_W 32 -#define RFC_ULLRAM_BANK1258_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1258_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1259 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1259_DATA_W 32 -#define RFC_ULLRAM_BANK1259_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1259_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1260 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1260_DATA_W 32 -#define RFC_ULLRAM_BANK1260_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1260_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1261 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1261_DATA_W 32 -#define RFC_ULLRAM_BANK1261_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1261_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1262 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1262_DATA_W 32 -#define RFC_ULLRAM_BANK1262_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1262_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1263 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1263_DATA_W 32 -#define RFC_ULLRAM_BANK1263_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1263_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1264 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1264_DATA_W 32 -#define RFC_ULLRAM_BANK1264_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1264_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1265 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1265_DATA_W 32 -#define RFC_ULLRAM_BANK1265_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1265_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1266 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1266_DATA_W 32 -#define RFC_ULLRAM_BANK1266_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1266_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1267 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1267_DATA_W 32 -#define RFC_ULLRAM_BANK1267_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1267_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1268 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1268_DATA_W 32 -#define RFC_ULLRAM_BANK1268_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1268_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1269 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1269_DATA_W 32 -#define RFC_ULLRAM_BANK1269_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1269_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1270 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1270_DATA_W 32 -#define RFC_ULLRAM_BANK1270_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1270_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1271 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1271_DATA_W 32 -#define RFC_ULLRAM_BANK1271_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1271_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1272 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1272_DATA_W 32 -#define RFC_ULLRAM_BANK1272_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1272_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1273 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1273_DATA_W 32 -#define RFC_ULLRAM_BANK1273_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1273_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1274 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1274_DATA_W 32 -#define RFC_ULLRAM_BANK1274_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1274_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1275 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1275_DATA_W 32 -#define RFC_ULLRAM_BANK1275_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1275_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1276 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1276_DATA_W 32 -#define RFC_ULLRAM_BANK1276_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1276_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1277 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1277_DATA_W 32 -#define RFC_ULLRAM_BANK1277_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1277_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1278 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1278_DATA_W 32 -#define RFC_ULLRAM_BANK1278_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1278_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1279 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1279_DATA_W 32 -#define RFC_ULLRAM_BANK1279_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1279_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1280 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1280_DATA_W 32 -#define RFC_ULLRAM_BANK1280_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1280_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1281 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1281_DATA_W 32 -#define RFC_ULLRAM_BANK1281_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1281_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1282 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1282_DATA_W 32 -#define RFC_ULLRAM_BANK1282_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1282_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1283 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1283_DATA_W 32 -#define RFC_ULLRAM_BANK1283_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1283_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1284 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1284_DATA_W 32 -#define RFC_ULLRAM_BANK1284_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1284_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1285 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1285_DATA_W 32 -#define RFC_ULLRAM_BANK1285_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1285_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1286 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1286_DATA_W 32 -#define RFC_ULLRAM_BANK1286_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1286_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1287 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1287_DATA_W 32 -#define RFC_ULLRAM_BANK1287_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1287_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1288 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1288_DATA_W 32 -#define RFC_ULLRAM_BANK1288_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1288_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1289 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1289_DATA_W 32 -#define RFC_ULLRAM_BANK1289_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1289_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1290 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1290_DATA_W 32 -#define RFC_ULLRAM_BANK1290_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1290_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1291 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1291_DATA_W 32 -#define RFC_ULLRAM_BANK1291_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1291_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1292 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1292_DATA_W 32 -#define RFC_ULLRAM_BANK1292_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1292_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1293 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1293_DATA_W 32 -#define RFC_ULLRAM_BANK1293_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1293_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1294 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1294_DATA_W 32 -#define RFC_ULLRAM_BANK1294_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1294_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1295 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1295_DATA_W 32 -#define RFC_ULLRAM_BANK1295_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1295_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1296 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1296_DATA_W 32 -#define RFC_ULLRAM_BANK1296_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1296_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1297 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1297_DATA_W 32 -#define RFC_ULLRAM_BANK1297_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1297_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1298 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1298_DATA_W 32 -#define RFC_ULLRAM_BANK1298_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1298_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1299 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1299_DATA_W 32 -#define RFC_ULLRAM_BANK1299_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1299_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1300 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1300_DATA_W 32 -#define RFC_ULLRAM_BANK1300_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1300_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1301 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1301_DATA_W 32 -#define RFC_ULLRAM_BANK1301_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1301_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1302 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1302_DATA_W 32 -#define RFC_ULLRAM_BANK1302_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1302_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1303 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1303_DATA_W 32 -#define RFC_ULLRAM_BANK1303_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1303_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1304 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1304_DATA_W 32 -#define RFC_ULLRAM_BANK1304_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1304_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1305 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1305_DATA_W 32 -#define RFC_ULLRAM_BANK1305_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1305_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1306 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1306_DATA_W 32 -#define RFC_ULLRAM_BANK1306_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1306_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1307 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1307_DATA_W 32 -#define RFC_ULLRAM_BANK1307_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1307_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1308 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1308_DATA_W 32 -#define RFC_ULLRAM_BANK1308_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1308_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1309 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1309_DATA_W 32 -#define RFC_ULLRAM_BANK1309_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1309_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1310 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1310_DATA_W 32 -#define RFC_ULLRAM_BANK1310_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1310_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1311 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1311_DATA_W 32 -#define RFC_ULLRAM_BANK1311_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1311_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1312 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1312_DATA_W 32 -#define RFC_ULLRAM_BANK1312_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1312_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1313 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1313_DATA_W 32 -#define RFC_ULLRAM_BANK1313_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1313_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1314 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1314_DATA_W 32 -#define RFC_ULLRAM_BANK1314_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1314_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1315 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1315_DATA_W 32 -#define RFC_ULLRAM_BANK1315_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1315_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1316 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1316_DATA_W 32 -#define RFC_ULLRAM_BANK1316_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1316_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1317 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1317_DATA_W 32 -#define RFC_ULLRAM_BANK1317_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1317_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1318 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1318_DATA_W 32 -#define RFC_ULLRAM_BANK1318_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1318_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1319 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1319_DATA_W 32 -#define RFC_ULLRAM_BANK1319_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1319_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1320 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1320_DATA_W 32 -#define RFC_ULLRAM_BANK1320_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1320_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1321 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1321_DATA_W 32 -#define RFC_ULLRAM_BANK1321_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1321_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1322 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1322_DATA_W 32 -#define RFC_ULLRAM_BANK1322_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1322_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1323 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1323_DATA_W 32 -#define RFC_ULLRAM_BANK1323_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1323_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1324 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1324_DATA_W 32 -#define RFC_ULLRAM_BANK1324_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1324_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1325 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1325_DATA_W 32 -#define RFC_ULLRAM_BANK1325_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1325_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1326 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1326_DATA_W 32 -#define RFC_ULLRAM_BANK1326_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1326_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1327 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1327_DATA_W 32 -#define RFC_ULLRAM_BANK1327_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1327_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1328 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1328_DATA_W 32 -#define RFC_ULLRAM_BANK1328_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1328_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1329 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1329_DATA_W 32 -#define RFC_ULLRAM_BANK1329_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1329_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1330 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1330_DATA_W 32 -#define RFC_ULLRAM_BANK1330_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1330_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1331 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1331_DATA_W 32 -#define RFC_ULLRAM_BANK1331_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1331_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1332 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1332_DATA_W 32 -#define RFC_ULLRAM_BANK1332_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1332_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1333 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1333_DATA_W 32 -#define RFC_ULLRAM_BANK1333_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1333_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1334 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1334_DATA_W 32 -#define RFC_ULLRAM_BANK1334_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1334_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1335 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1335_DATA_W 32 -#define RFC_ULLRAM_BANK1335_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1335_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1336 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1336_DATA_W 32 -#define RFC_ULLRAM_BANK1336_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1336_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1337 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1337_DATA_W 32 -#define RFC_ULLRAM_BANK1337_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1337_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1338 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1338_DATA_W 32 -#define RFC_ULLRAM_BANK1338_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1338_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1339 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1339_DATA_W 32 -#define RFC_ULLRAM_BANK1339_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1339_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1340 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1340_DATA_W 32 -#define RFC_ULLRAM_BANK1340_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1340_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1341 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1341_DATA_W 32 -#define RFC_ULLRAM_BANK1341_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1341_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1342 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1342_DATA_W 32 -#define RFC_ULLRAM_BANK1342_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1342_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1343 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1343_DATA_W 32 -#define RFC_ULLRAM_BANK1343_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1343_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1344 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1344_DATA_W 32 -#define RFC_ULLRAM_BANK1344_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1344_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1345 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1345_DATA_W 32 -#define RFC_ULLRAM_BANK1345_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1345_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1346 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1346_DATA_W 32 -#define RFC_ULLRAM_BANK1346_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1346_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1347 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1347_DATA_W 32 -#define RFC_ULLRAM_BANK1347_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1347_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1348 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1348_DATA_W 32 -#define RFC_ULLRAM_BANK1348_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1348_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1349 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1349_DATA_W 32 -#define RFC_ULLRAM_BANK1349_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1349_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1350 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1350_DATA_W 32 -#define RFC_ULLRAM_BANK1350_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1350_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1351 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1351_DATA_W 32 -#define RFC_ULLRAM_BANK1351_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1351_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1352 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1352_DATA_W 32 -#define RFC_ULLRAM_BANK1352_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1352_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1353 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1353_DATA_W 32 -#define RFC_ULLRAM_BANK1353_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1353_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1354 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1354_DATA_W 32 -#define RFC_ULLRAM_BANK1354_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1354_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1355 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1355_DATA_W 32 -#define RFC_ULLRAM_BANK1355_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1355_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1356 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1356_DATA_W 32 -#define RFC_ULLRAM_BANK1356_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1356_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1357 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1357_DATA_W 32 -#define RFC_ULLRAM_BANK1357_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1357_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1358 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1358_DATA_W 32 -#define RFC_ULLRAM_BANK1358_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1358_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1359 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1359_DATA_W 32 -#define RFC_ULLRAM_BANK1359_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1359_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1360 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1360_DATA_W 32 -#define RFC_ULLRAM_BANK1360_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1360_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1361 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1361_DATA_W 32 -#define RFC_ULLRAM_BANK1361_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1361_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1362 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1362_DATA_W 32 -#define RFC_ULLRAM_BANK1362_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1362_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1363 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1363_DATA_W 32 -#define RFC_ULLRAM_BANK1363_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1363_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1364 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1364_DATA_W 32 -#define RFC_ULLRAM_BANK1364_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1364_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1365 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1365_DATA_W 32 -#define RFC_ULLRAM_BANK1365_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1365_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1366 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1366_DATA_W 32 -#define RFC_ULLRAM_BANK1366_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1366_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1367 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1367_DATA_W 32 -#define RFC_ULLRAM_BANK1367_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1367_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1368 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1368_DATA_W 32 -#define RFC_ULLRAM_BANK1368_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1368_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1369 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1369_DATA_W 32 -#define RFC_ULLRAM_BANK1369_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1369_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1370 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1370_DATA_W 32 -#define RFC_ULLRAM_BANK1370_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1370_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1371 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1371_DATA_W 32 -#define RFC_ULLRAM_BANK1371_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1371_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1372 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1372_DATA_W 32 -#define RFC_ULLRAM_BANK1372_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1372_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1373 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1373_DATA_W 32 -#define RFC_ULLRAM_BANK1373_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1373_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1374 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1374_DATA_W 32 -#define RFC_ULLRAM_BANK1374_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1374_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1375 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1375_DATA_W 32 -#define RFC_ULLRAM_BANK1375_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1375_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1376 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1376_DATA_W 32 -#define RFC_ULLRAM_BANK1376_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1376_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1377 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1377_DATA_W 32 -#define RFC_ULLRAM_BANK1377_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1377_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1378 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1378_DATA_W 32 -#define RFC_ULLRAM_BANK1378_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1378_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1379 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1379_DATA_W 32 -#define RFC_ULLRAM_BANK1379_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1379_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1380 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1380_DATA_W 32 -#define RFC_ULLRAM_BANK1380_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1380_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1381 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1381_DATA_W 32 -#define RFC_ULLRAM_BANK1381_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1381_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1382 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1382_DATA_W 32 -#define RFC_ULLRAM_BANK1382_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1382_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1383 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1383_DATA_W 32 -#define RFC_ULLRAM_BANK1383_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1383_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1384 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1384_DATA_W 32 -#define RFC_ULLRAM_BANK1384_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1384_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1385 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1385_DATA_W 32 -#define RFC_ULLRAM_BANK1385_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1385_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1386 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1386_DATA_W 32 -#define RFC_ULLRAM_BANK1386_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1386_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1387 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1387_DATA_W 32 -#define RFC_ULLRAM_BANK1387_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1387_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1388 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1388_DATA_W 32 -#define RFC_ULLRAM_BANK1388_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1388_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1389 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1389_DATA_W 32 -#define RFC_ULLRAM_BANK1389_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1389_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1390 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1390_DATA_W 32 -#define RFC_ULLRAM_BANK1390_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1390_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1391 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1391_DATA_W 32 -#define RFC_ULLRAM_BANK1391_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1391_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1392 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1392_DATA_W 32 -#define RFC_ULLRAM_BANK1392_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1392_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1393 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1393_DATA_W 32 -#define RFC_ULLRAM_BANK1393_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1393_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1394 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1394_DATA_W 32 -#define RFC_ULLRAM_BANK1394_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1394_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1395 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1395_DATA_W 32 -#define RFC_ULLRAM_BANK1395_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1395_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1396 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1396_DATA_W 32 -#define RFC_ULLRAM_BANK1396_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1396_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1397 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1397_DATA_W 32 -#define RFC_ULLRAM_BANK1397_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1397_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1398 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1398_DATA_W 32 -#define RFC_ULLRAM_BANK1398_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1398_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1399 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1399_DATA_W 32 -#define RFC_ULLRAM_BANK1399_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1399_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1400 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1400_DATA_W 32 -#define RFC_ULLRAM_BANK1400_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1400_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1401 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1401_DATA_W 32 -#define RFC_ULLRAM_BANK1401_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1401_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1402 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1402_DATA_W 32 -#define RFC_ULLRAM_BANK1402_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1402_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1403 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1403_DATA_W 32 -#define RFC_ULLRAM_BANK1403_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1403_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1404 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1404_DATA_W 32 -#define RFC_ULLRAM_BANK1404_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1404_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1405 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1405_DATA_W 32 -#define RFC_ULLRAM_BANK1405_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1405_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1406 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1406_DATA_W 32 -#define RFC_ULLRAM_BANK1406_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1406_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1407 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1407_DATA_W 32 -#define RFC_ULLRAM_BANK1407_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1407_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1408 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1408_DATA_W 32 -#define RFC_ULLRAM_BANK1408_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1408_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1409 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1409_DATA_W 32 -#define RFC_ULLRAM_BANK1409_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1409_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1410 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1410_DATA_W 32 -#define RFC_ULLRAM_BANK1410_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1410_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1411 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1411_DATA_W 32 -#define RFC_ULLRAM_BANK1411_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1411_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1412 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1412_DATA_W 32 -#define RFC_ULLRAM_BANK1412_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1412_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1413 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1413_DATA_W 32 -#define RFC_ULLRAM_BANK1413_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1413_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1414 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1414_DATA_W 32 -#define RFC_ULLRAM_BANK1414_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1414_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1415 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1415_DATA_W 32 -#define RFC_ULLRAM_BANK1415_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1415_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1416 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1416_DATA_W 32 -#define RFC_ULLRAM_BANK1416_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1416_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1417 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1417_DATA_W 32 -#define RFC_ULLRAM_BANK1417_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1417_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1418 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1418_DATA_W 32 -#define RFC_ULLRAM_BANK1418_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1418_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1419 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1419_DATA_W 32 -#define RFC_ULLRAM_BANK1419_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1419_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1420 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1420_DATA_W 32 -#define RFC_ULLRAM_BANK1420_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1420_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1421 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1421_DATA_W 32 -#define RFC_ULLRAM_BANK1421_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1421_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1422 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1422_DATA_W 32 -#define RFC_ULLRAM_BANK1422_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1422_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1423 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1423_DATA_W 32 -#define RFC_ULLRAM_BANK1423_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1423_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1424 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1424_DATA_W 32 -#define RFC_ULLRAM_BANK1424_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1424_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1425 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1425_DATA_W 32 -#define RFC_ULLRAM_BANK1425_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1425_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1426 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1426_DATA_W 32 -#define RFC_ULLRAM_BANK1426_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1426_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1427 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1427_DATA_W 32 -#define RFC_ULLRAM_BANK1427_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1427_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1428 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1428_DATA_W 32 -#define RFC_ULLRAM_BANK1428_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1428_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1429 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1429_DATA_W 32 -#define RFC_ULLRAM_BANK1429_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1429_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1430 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1430_DATA_W 32 -#define RFC_ULLRAM_BANK1430_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1430_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1431 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1431_DATA_W 32 -#define RFC_ULLRAM_BANK1431_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1431_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1432 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1432_DATA_W 32 -#define RFC_ULLRAM_BANK1432_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1432_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1433 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1433_DATA_W 32 -#define RFC_ULLRAM_BANK1433_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1433_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1434 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1434_DATA_W 32 -#define RFC_ULLRAM_BANK1434_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1434_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1435 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1435_DATA_W 32 -#define RFC_ULLRAM_BANK1435_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1435_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1436 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1436_DATA_W 32 -#define RFC_ULLRAM_BANK1436_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1436_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1437 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1437_DATA_W 32 -#define RFC_ULLRAM_BANK1437_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1437_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1438 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1438_DATA_W 32 -#define RFC_ULLRAM_BANK1438_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1438_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1439 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1439_DATA_W 32 -#define RFC_ULLRAM_BANK1439_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1439_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1440 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1440_DATA_W 32 -#define RFC_ULLRAM_BANK1440_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1440_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1441 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1441_DATA_W 32 -#define RFC_ULLRAM_BANK1441_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1441_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1442 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1442_DATA_W 32 -#define RFC_ULLRAM_BANK1442_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1442_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1443 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1443_DATA_W 32 -#define RFC_ULLRAM_BANK1443_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1443_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1444 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1444_DATA_W 32 -#define RFC_ULLRAM_BANK1444_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1444_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1445 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1445_DATA_W 32 -#define RFC_ULLRAM_BANK1445_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1445_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1446 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1446_DATA_W 32 -#define RFC_ULLRAM_BANK1446_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1446_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1447 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1447_DATA_W 32 -#define RFC_ULLRAM_BANK1447_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1447_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1448 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1448_DATA_W 32 -#define RFC_ULLRAM_BANK1448_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1448_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1449 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1449_DATA_W 32 -#define RFC_ULLRAM_BANK1449_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1449_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1450 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1450_DATA_W 32 -#define RFC_ULLRAM_BANK1450_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1450_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1451 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1451_DATA_W 32 -#define RFC_ULLRAM_BANK1451_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1451_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1452 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1452_DATA_W 32 -#define RFC_ULLRAM_BANK1452_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1452_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1453 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1453_DATA_W 32 -#define RFC_ULLRAM_BANK1453_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1453_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1454 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1454_DATA_W 32 -#define RFC_ULLRAM_BANK1454_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1454_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1455 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1455_DATA_W 32 -#define RFC_ULLRAM_BANK1455_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1455_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1456 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1456_DATA_W 32 -#define RFC_ULLRAM_BANK1456_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1456_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1457 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1457_DATA_W 32 -#define RFC_ULLRAM_BANK1457_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1457_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1458 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1458_DATA_W 32 -#define RFC_ULLRAM_BANK1458_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1458_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1459 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1459_DATA_W 32 -#define RFC_ULLRAM_BANK1459_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1459_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1460 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1460_DATA_W 32 -#define RFC_ULLRAM_BANK1460_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1460_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1461 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1461_DATA_W 32 -#define RFC_ULLRAM_BANK1461_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1461_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1462 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1462_DATA_W 32 -#define RFC_ULLRAM_BANK1462_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1462_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1463 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1463_DATA_W 32 -#define RFC_ULLRAM_BANK1463_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1463_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1464 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1464_DATA_W 32 -#define RFC_ULLRAM_BANK1464_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1464_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1465 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1465_DATA_W 32 -#define RFC_ULLRAM_BANK1465_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1465_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1466 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1466_DATA_W 32 -#define RFC_ULLRAM_BANK1466_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1466_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1467 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1467_DATA_W 32 -#define RFC_ULLRAM_BANK1467_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1467_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1468 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1468_DATA_W 32 -#define RFC_ULLRAM_BANK1468_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1468_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1469 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1469_DATA_W 32 -#define RFC_ULLRAM_BANK1469_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1469_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1470 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1470_DATA_W 32 -#define RFC_ULLRAM_BANK1470_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1470_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1471 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1471_DATA_W 32 -#define RFC_ULLRAM_BANK1471_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1471_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1472 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1472_DATA_W 32 -#define RFC_ULLRAM_BANK1472_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1472_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1473 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1473_DATA_W 32 -#define RFC_ULLRAM_BANK1473_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1473_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1474 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1474_DATA_W 32 -#define RFC_ULLRAM_BANK1474_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1474_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1475 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1475_DATA_W 32 -#define RFC_ULLRAM_BANK1475_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1475_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1476 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1476_DATA_W 32 -#define RFC_ULLRAM_BANK1476_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1476_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1477 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1477_DATA_W 32 -#define RFC_ULLRAM_BANK1477_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1477_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1478 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1478_DATA_W 32 -#define RFC_ULLRAM_BANK1478_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1478_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1479 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1479_DATA_W 32 -#define RFC_ULLRAM_BANK1479_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1479_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1480 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1480_DATA_W 32 -#define RFC_ULLRAM_BANK1480_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1480_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1481 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1481_DATA_W 32 -#define RFC_ULLRAM_BANK1481_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1481_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1482 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1482_DATA_W 32 -#define RFC_ULLRAM_BANK1482_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1482_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1483 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1483_DATA_W 32 -#define RFC_ULLRAM_BANK1483_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1483_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1484 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1484_DATA_W 32 -#define RFC_ULLRAM_BANK1484_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1484_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1485 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1485_DATA_W 32 -#define RFC_ULLRAM_BANK1485_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1485_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1486 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1486_DATA_W 32 -#define RFC_ULLRAM_BANK1486_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1486_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1487 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1487_DATA_W 32 -#define RFC_ULLRAM_BANK1487_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1487_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1488 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1488_DATA_W 32 -#define RFC_ULLRAM_BANK1488_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1488_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1489 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1489_DATA_W 32 -#define RFC_ULLRAM_BANK1489_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1489_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1490 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1490_DATA_W 32 -#define RFC_ULLRAM_BANK1490_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1490_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1491 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1491_DATA_W 32 -#define RFC_ULLRAM_BANK1491_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1491_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1492 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1492_DATA_W 32 -#define RFC_ULLRAM_BANK1492_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1492_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1493 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1493_DATA_W 32 -#define RFC_ULLRAM_BANK1493_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1493_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1494 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1494_DATA_W 32 -#define RFC_ULLRAM_BANK1494_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1494_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1495 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1495_DATA_W 32 -#define RFC_ULLRAM_BANK1495_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1495_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1496 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1496_DATA_W 32 -#define RFC_ULLRAM_BANK1496_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1496_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1497 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1497_DATA_W 32 -#define RFC_ULLRAM_BANK1497_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1497_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1498 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1498_DATA_W 32 -#define RFC_ULLRAM_BANK1498_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1498_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1499 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1499_DATA_W 32 -#define RFC_ULLRAM_BANK1499_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1499_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1500 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1500_DATA_W 32 -#define RFC_ULLRAM_BANK1500_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1500_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1501 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1501_DATA_W 32 -#define RFC_ULLRAM_BANK1501_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1501_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1502 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1502_DATA_W 32 -#define RFC_ULLRAM_BANK1502_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1502_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1503 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1503_DATA_W 32 -#define RFC_ULLRAM_BANK1503_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1503_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1504 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1504_DATA_W 32 -#define RFC_ULLRAM_BANK1504_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1504_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1505 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1505_DATA_W 32 -#define RFC_ULLRAM_BANK1505_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1505_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1506 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1506_DATA_W 32 -#define RFC_ULLRAM_BANK1506_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1506_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1507 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1507_DATA_W 32 -#define RFC_ULLRAM_BANK1507_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1507_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1508 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1508_DATA_W 32 -#define RFC_ULLRAM_BANK1508_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1508_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1509 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1509_DATA_W 32 -#define RFC_ULLRAM_BANK1509_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1509_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1510 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1510_DATA_W 32 -#define RFC_ULLRAM_BANK1510_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1510_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1511 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1511_DATA_W 32 -#define RFC_ULLRAM_BANK1511_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1511_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1512 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1512_DATA_W 32 -#define RFC_ULLRAM_BANK1512_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1512_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1513 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1513_DATA_W 32 -#define RFC_ULLRAM_BANK1513_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1513_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1514 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1514_DATA_W 32 -#define RFC_ULLRAM_BANK1514_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1514_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1515 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1515_DATA_W 32 -#define RFC_ULLRAM_BANK1515_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1515_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1516 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1516_DATA_W 32 -#define RFC_ULLRAM_BANK1516_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1516_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1517 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1517_DATA_W 32 -#define RFC_ULLRAM_BANK1517_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1517_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1518 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1518_DATA_W 32 -#define RFC_ULLRAM_BANK1518_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1518_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1519 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1519_DATA_W 32 -#define RFC_ULLRAM_BANK1519_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1519_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1520 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1520_DATA_W 32 -#define RFC_ULLRAM_BANK1520_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1520_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1521 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1521_DATA_W 32 -#define RFC_ULLRAM_BANK1521_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1521_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1522 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1522_DATA_W 32 -#define RFC_ULLRAM_BANK1522_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1522_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1523 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1523_DATA_W 32 -#define RFC_ULLRAM_BANK1523_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1523_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1524 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1524_DATA_W 32 -#define RFC_ULLRAM_BANK1524_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1524_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1525 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1525_DATA_W 32 -#define RFC_ULLRAM_BANK1525_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1525_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1526 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1526_DATA_W 32 -#define RFC_ULLRAM_BANK1526_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1526_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1527 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1527_DATA_W 32 -#define RFC_ULLRAM_BANK1527_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1527_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1528 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1528_DATA_W 32 -#define RFC_ULLRAM_BANK1528_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1528_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1529 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1529_DATA_W 32 -#define RFC_ULLRAM_BANK1529_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1529_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1530 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1530_DATA_W 32 -#define RFC_ULLRAM_BANK1530_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1530_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1531 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1531_DATA_W 32 -#define RFC_ULLRAM_BANK1531_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1531_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1532 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1532_DATA_W 32 -#define RFC_ULLRAM_BANK1532_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1532_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1533 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1533_DATA_W 32 -#define RFC_ULLRAM_BANK1533_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1533_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1534 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1534_DATA_W 32 -#define RFC_ULLRAM_BANK1534_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1534_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1535 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1535_DATA_W 32 -#define RFC_ULLRAM_BANK1535_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1535_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1536 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1536_DATA_W 32 -#define RFC_ULLRAM_BANK1536_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1536_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1537 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1537_DATA_W 32 -#define RFC_ULLRAM_BANK1537_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1537_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1538 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1538_DATA_W 32 -#define RFC_ULLRAM_BANK1538_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1538_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1539 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1539_DATA_W 32 -#define RFC_ULLRAM_BANK1539_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1539_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1540 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1540_DATA_W 32 -#define RFC_ULLRAM_BANK1540_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1540_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1541 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1541_DATA_W 32 -#define RFC_ULLRAM_BANK1541_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1541_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1542 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1542_DATA_W 32 -#define RFC_ULLRAM_BANK1542_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1542_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1543 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1543_DATA_W 32 -#define RFC_ULLRAM_BANK1543_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1543_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1544 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1544_DATA_W 32 -#define RFC_ULLRAM_BANK1544_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1544_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1545 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1545_DATA_W 32 -#define RFC_ULLRAM_BANK1545_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1545_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1546 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1546_DATA_W 32 -#define RFC_ULLRAM_BANK1546_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1546_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1547 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1547_DATA_W 32 -#define RFC_ULLRAM_BANK1547_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1547_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1548 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1548_DATA_W 32 -#define RFC_ULLRAM_BANK1548_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1548_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1549 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1549_DATA_W 32 -#define RFC_ULLRAM_BANK1549_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1549_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1550 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1550_DATA_W 32 -#define RFC_ULLRAM_BANK1550_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1550_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1551 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1551_DATA_W 32 -#define RFC_ULLRAM_BANK1551_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1551_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1552 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1552_DATA_W 32 -#define RFC_ULLRAM_BANK1552_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1552_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1553 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1553_DATA_W 32 -#define RFC_ULLRAM_BANK1553_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1553_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1554 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1554_DATA_W 32 -#define RFC_ULLRAM_BANK1554_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1554_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1555 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1555_DATA_W 32 -#define RFC_ULLRAM_BANK1555_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1555_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1556 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1556_DATA_W 32 -#define RFC_ULLRAM_BANK1556_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1556_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1557 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1557_DATA_W 32 -#define RFC_ULLRAM_BANK1557_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1557_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1558 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1558_DATA_W 32 -#define RFC_ULLRAM_BANK1558_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1558_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1559 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1559_DATA_W 32 -#define RFC_ULLRAM_BANK1559_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1559_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1560 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1560_DATA_W 32 -#define RFC_ULLRAM_BANK1560_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1560_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1561 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1561_DATA_W 32 -#define RFC_ULLRAM_BANK1561_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1561_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1562 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1562_DATA_W 32 -#define RFC_ULLRAM_BANK1562_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1562_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1563 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1563_DATA_W 32 -#define RFC_ULLRAM_BANK1563_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1563_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1564 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1564_DATA_W 32 -#define RFC_ULLRAM_BANK1564_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1564_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1565 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1565_DATA_W 32 -#define RFC_ULLRAM_BANK1565_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1565_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1566 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1566_DATA_W 32 -#define RFC_ULLRAM_BANK1566_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1566_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1567 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1567_DATA_W 32 -#define RFC_ULLRAM_BANK1567_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1567_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1568 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1568_DATA_W 32 -#define RFC_ULLRAM_BANK1568_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1568_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1569 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1569_DATA_W 32 -#define RFC_ULLRAM_BANK1569_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1569_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1570 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1570_DATA_W 32 -#define RFC_ULLRAM_BANK1570_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1570_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1571 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1571_DATA_W 32 -#define RFC_ULLRAM_BANK1571_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1571_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1572 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1572_DATA_W 32 -#define RFC_ULLRAM_BANK1572_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1572_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1573 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1573_DATA_W 32 -#define RFC_ULLRAM_BANK1573_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1573_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1574 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1574_DATA_W 32 -#define RFC_ULLRAM_BANK1574_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1574_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1575 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1575_DATA_W 32 -#define RFC_ULLRAM_BANK1575_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1575_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1576 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1576_DATA_W 32 -#define RFC_ULLRAM_BANK1576_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1576_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1577 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1577_DATA_W 32 -#define RFC_ULLRAM_BANK1577_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1577_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1578 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1578_DATA_W 32 -#define RFC_ULLRAM_BANK1578_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1578_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1579 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1579_DATA_W 32 -#define RFC_ULLRAM_BANK1579_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1579_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1580 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1580_DATA_W 32 -#define RFC_ULLRAM_BANK1580_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1580_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1581 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1581_DATA_W 32 -#define RFC_ULLRAM_BANK1581_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1581_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1582 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1582_DATA_W 32 -#define RFC_ULLRAM_BANK1582_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1582_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1583 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1583_DATA_W 32 -#define RFC_ULLRAM_BANK1583_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1583_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1584 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1584_DATA_W 32 -#define RFC_ULLRAM_BANK1584_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1584_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1585 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1585_DATA_W 32 -#define RFC_ULLRAM_BANK1585_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1585_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1586 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1586_DATA_W 32 -#define RFC_ULLRAM_BANK1586_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1586_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1587 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1587_DATA_W 32 -#define RFC_ULLRAM_BANK1587_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1587_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1588 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1588_DATA_W 32 -#define RFC_ULLRAM_BANK1588_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1588_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1589 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1589_DATA_W 32 -#define RFC_ULLRAM_BANK1589_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1589_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1590 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1590_DATA_W 32 -#define RFC_ULLRAM_BANK1590_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1590_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1591 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1591_DATA_W 32 -#define RFC_ULLRAM_BANK1591_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1591_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1592 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1592_DATA_W 32 -#define RFC_ULLRAM_BANK1592_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1592_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1593 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1593_DATA_W 32 -#define RFC_ULLRAM_BANK1593_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1593_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1594 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1594_DATA_W 32 -#define RFC_ULLRAM_BANK1594_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1594_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1595 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1595_DATA_W 32 -#define RFC_ULLRAM_BANK1595_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1595_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1596 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1596_DATA_W 32 -#define RFC_ULLRAM_BANK1596_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1596_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1597 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1597_DATA_W 32 -#define RFC_ULLRAM_BANK1597_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1597_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1598 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1598_DATA_W 32 -#define RFC_ULLRAM_BANK1598_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1598_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1599 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1599_DATA_W 32 -#define RFC_ULLRAM_BANK1599_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1599_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1600 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1600_DATA_W 32 -#define RFC_ULLRAM_BANK1600_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1600_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1601 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1601_DATA_W 32 -#define RFC_ULLRAM_BANK1601_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1601_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1602 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1602_DATA_W 32 -#define RFC_ULLRAM_BANK1602_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1602_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1603 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1603_DATA_W 32 -#define RFC_ULLRAM_BANK1603_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1603_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1604 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1604_DATA_W 32 -#define RFC_ULLRAM_BANK1604_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1604_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1605 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1605_DATA_W 32 -#define RFC_ULLRAM_BANK1605_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1605_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1606 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1606_DATA_W 32 -#define RFC_ULLRAM_BANK1606_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1606_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1607 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1607_DATA_W 32 -#define RFC_ULLRAM_BANK1607_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1607_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1608 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1608_DATA_W 32 -#define RFC_ULLRAM_BANK1608_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1608_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1609 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1609_DATA_W 32 -#define RFC_ULLRAM_BANK1609_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1609_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1610 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1610_DATA_W 32 -#define RFC_ULLRAM_BANK1610_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1610_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1611 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1611_DATA_W 32 -#define RFC_ULLRAM_BANK1611_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1611_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1612 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1612_DATA_W 32 -#define RFC_ULLRAM_BANK1612_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1612_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1613 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1613_DATA_W 32 -#define RFC_ULLRAM_BANK1613_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1613_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1614 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1614_DATA_W 32 -#define RFC_ULLRAM_BANK1614_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1614_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1615 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1615_DATA_W 32 -#define RFC_ULLRAM_BANK1615_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1615_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1616 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1616_DATA_W 32 -#define RFC_ULLRAM_BANK1616_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1616_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1617 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1617_DATA_W 32 -#define RFC_ULLRAM_BANK1617_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1617_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1618 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1618_DATA_W 32 -#define RFC_ULLRAM_BANK1618_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1618_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1619 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1619_DATA_W 32 -#define RFC_ULLRAM_BANK1619_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1619_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1620 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1620_DATA_W 32 -#define RFC_ULLRAM_BANK1620_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1620_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1621 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1621_DATA_W 32 -#define RFC_ULLRAM_BANK1621_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1621_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1622 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1622_DATA_W 32 -#define RFC_ULLRAM_BANK1622_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1622_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1623 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1623_DATA_W 32 -#define RFC_ULLRAM_BANK1623_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1623_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1624 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1624_DATA_W 32 -#define RFC_ULLRAM_BANK1624_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1624_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1625 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1625_DATA_W 32 -#define RFC_ULLRAM_BANK1625_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1625_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1626 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1626_DATA_W 32 -#define RFC_ULLRAM_BANK1626_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1626_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1627 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1627_DATA_W 32 -#define RFC_ULLRAM_BANK1627_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1627_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1628 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1628_DATA_W 32 -#define RFC_ULLRAM_BANK1628_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1628_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1629 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1629_DATA_W 32 -#define RFC_ULLRAM_BANK1629_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1629_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1630 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1630_DATA_W 32 -#define RFC_ULLRAM_BANK1630_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1630_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1631 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1631_DATA_W 32 -#define RFC_ULLRAM_BANK1631_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1631_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1632 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1632_DATA_W 32 -#define RFC_ULLRAM_BANK1632_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1632_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1633 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1633_DATA_W 32 -#define RFC_ULLRAM_BANK1633_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1633_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1634 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1634_DATA_W 32 -#define RFC_ULLRAM_BANK1634_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1634_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1635 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1635_DATA_W 32 -#define RFC_ULLRAM_BANK1635_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1635_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1636 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1636_DATA_W 32 -#define RFC_ULLRAM_BANK1636_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1636_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1637 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1637_DATA_W 32 -#define RFC_ULLRAM_BANK1637_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1637_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1638 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1638_DATA_W 32 -#define RFC_ULLRAM_BANK1638_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1638_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1639 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1639_DATA_W 32 -#define RFC_ULLRAM_BANK1639_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1639_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1640 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1640_DATA_W 32 -#define RFC_ULLRAM_BANK1640_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1640_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1641 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1641_DATA_W 32 -#define RFC_ULLRAM_BANK1641_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1641_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1642 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1642_DATA_W 32 -#define RFC_ULLRAM_BANK1642_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1642_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1643 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1643_DATA_W 32 -#define RFC_ULLRAM_BANK1643_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1643_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1644 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1644_DATA_W 32 -#define RFC_ULLRAM_BANK1644_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1644_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1645 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1645_DATA_W 32 -#define RFC_ULLRAM_BANK1645_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1645_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1646 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1646_DATA_W 32 -#define RFC_ULLRAM_BANK1646_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1646_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1647 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1647_DATA_W 32 -#define RFC_ULLRAM_BANK1647_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1647_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1648 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1648_DATA_W 32 -#define RFC_ULLRAM_BANK1648_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1648_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1649 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1649_DATA_W 32 -#define RFC_ULLRAM_BANK1649_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1649_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1650 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1650_DATA_W 32 -#define RFC_ULLRAM_BANK1650_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1650_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1651 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1651_DATA_W 32 -#define RFC_ULLRAM_BANK1651_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1651_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1652 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1652_DATA_W 32 -#define RFC_ULLRAM_BANK1652_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1652_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1653 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1653_DATA_W 32 -#define RFC_ULLRAM_BANK1653_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1653_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1654 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1654_DATA_W 32 -#define RFC_ULLRAM_BANK1654_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1654_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1655 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1655_DATA_W 32 -#define RFC_ULLRAM_BANK1655_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1655_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1656 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1656_DATA_W 32 -#define RFC_ULLRAM_BANK1656_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1656_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1657 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1657_DATA_W 32 -#define RFC_ULLRAM_BANK1657_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1657_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1658 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1658_DATA_W 32 -#define RFC_ULLRAM_BANK1658_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1658_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1659 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1659_DATA_W 32 -#define RFC_ULLRAM_BANK1659_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1659_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1660 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1660_DATA_W 32 -#define RFC_ULLRAM_BANK1660_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1660_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1661 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1661_DATA_W 32 -#define RFC_ULLRAM_BANK1661_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1661_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1662 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1662_DATA_W 32 -#define RFC_ULLRAM_BANK1662_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1662_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1663 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1663_DATA_W 32 -#define RFC_ULLRAM_BANK1663_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1663_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1664 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1664_DATA_W 32 -#define RFC_ULLRAM_BANK1664_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1664_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1665 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1665_DATA_W 32 -#define RFC_ULLRAM_BANK1665_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1665_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1666 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1666_DATA_W 32 -#define RFC_ULLRAM_BANK1666_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1666_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1667 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1667_DATA_W 32 -#define RFC_ULLRAM_BANK1667_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1667_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1668 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1668_DATA_W 32 -#define RFC_ULLRAM_BANK1668_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1668_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1669 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1669_DATA_W 32 -#define RFC_ULLRAM_BANK1669_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1669_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1670 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1670_DATA_W 32 -#define RFC_ULLRAM_BANK1670_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1670_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1671 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1671_DATA_W 32 -#define RFC_ULLRAM_BANK1671_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1671_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1672 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1672_DATA_W 32 -#define RFC_ULLRAM_BANK1672_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1672_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1673 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1673_DATA_W 32 -#define RFC_ULLRAM_BANK1673_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1673_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1674 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1674_DATA_W 32 -#define RFC_ULLRAM_BANK1674_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1674_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1675 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1675_DATA_W 32 -#define RFC_ULLRAM_BANK1675_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1675_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1676 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1676_DATA_W 32 -#define RFC_ULLRAM_BANK1676_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1676_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1677 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1677_DATA_W 32 -#define RFC_ULLRAM_BANK1677_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1677_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1678 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1678_DATA_W 32 -#define RFC_ULLRAM_BANK1678_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1678_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1679 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1679_DATA_W 32 -#define RFC_ULLRAM_BANK1679_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1679_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1680 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1680_DATA_W 32 -#define RFC_ULLRAM_BANK1680_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1680_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1681 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1681_DATA_W 32 -#define RFC_ULLRAM_BANK1681_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1681_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1682 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1682_DATA_W 32 -#define RFC_ULLRAM_BANK1682_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1682_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1683 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1683_DATA_W 32 -#define RFC_ULLRAM_BANK1683_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1683_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1684 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1684_DATA_W 32 -#define RFC_ULLRAM_BANK1684_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1684_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1685 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1685_DATA_W 32 -#define RFC_ULLRAM_BANK1685_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1685_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1686 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1686_DATA_W 32 -#define RFC_ULLRAM_BANK1686_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1686_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1687 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1687_DATA_W 32 -#define RFC_ULLRAM_BANK1687_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1687_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1688 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1688_DATA_W 32 -#define RFC_ULLRAM_BANK1688_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1688_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1689 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1689_DATA_W 32 -#define RFC_ULLRAM_BANK1689_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1689_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1690 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1690_DATA_W 32 -#define RFC_ULLRAM_BANK1690_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1690_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1691 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1691_DATA_W 32 -#define RFC_ULLRAM_BANK1691_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1691_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1692 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1692_DATA_W 32 -#define RFC_ULLRAM_BANK1692_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1692_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1693 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1693_DATA_W 32 -#define RFC_ULLRAM_BANK1693_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1693_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1694 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1694_DATA_W 32 -#define RFC_ULLRAM_BANK1694_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1694_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1695 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1695_DATA_W 32 -#define RFC_ULLRAM_BANK1695_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1695_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1696 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1696_DATA_W 32 -#define RFC_ULLRAM_BANK1696_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1696_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1697 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1697_DATA_W 32 -#define RFC_ULLRAM_BANK1697_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1697_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1698 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1698_DATA_W 32 -#define RFC_ULLRAM_BANK1698_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1698_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1699 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1699_DATA_W 32 -#define RFC_ULLRAM_BANK1699_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1699_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1700 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1700_DATA_W 32 -#define RFC_ULLRAM_BANK1700_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1700_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1701 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1701_DATA_W 32 -#define RFC_ULLRAM_BANK1701_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1701_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1702 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1702_DATA_W 32 -#define RFC_ULLRAM_BANK1702_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1702_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1703 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1703_DATA_W 32 -#define RFC_ULLRAM_BANK1703_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1703_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1704 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1704_DATA_W 32 -#define RFC_ULLRAM_BANK1704_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1704_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1705 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1705_DATA_W 32 -#define RFC_ULLRAM_BANK1705_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1705_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1706 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1706_DATA_W 32 -#define RFC_ULLRAM_BANK1706_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1706_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1707 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1707_DATA_W 32 -#define RFC_ULLRAM_BANK1707_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1707_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1708 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1708_DATA_W 32 -#define RFC_ULLRAM_BANK1708_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1708_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1709 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1709_DATA_W 32 -#define RFC_ULLRAM_BANK1709_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1709_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1710 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1710_DATA_W 32 -#define RFC_ULLRAM_BANK1710_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1710_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1711 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1711_DATA_W 32 -#define RFC_ULLRAM_BANK1711_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1711_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1712 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1712_DATA_W 32 -#define RFC_ULLRAM_BANK1712_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1712_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1713 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1713_DATA_W 32 -#define RFC_ULLRAM_BANK1713_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1713_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1714 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1714_DATA_W 32 -#define RFC_ULLRAM_BANK1714_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1714_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1715 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1715_DATA_W 32 -#define RFC_ULLRAM_BANK1715_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1715_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1716 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1716_DATA_W 32 -#define RFC_ULLRAM_BANK1716_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1716_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1717 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1717_DATA_W 32 -#define RFC_ULLRAM_BANK1717_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1717_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1718 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1718_DATA_W 32 -#define RFC_ULLRAM_BANK1718_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1718_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1719 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1719_DATA_W 32 -#define RFC_ULLRAM_BANK1719_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1719_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1720 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1720_DATA_W 32 -#define RFC_ULLRAM_BANK1720_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1720_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1721 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1721_DATA_W 32 -#define RFC_ULLRAM_BANK1721_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1721_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1722 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1722_DATA_W 32 -#define RFC_ULLRAM_BANK1722_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1722_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1723 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1723_DATA_W 32 -#define RFC_ULLRAM_BANK1723_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1723_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1724 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1724_DATA_W 32 -#define RFC_ULLRAM_BANK1724_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1724_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1725 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1725_DATA_W 32 -#define RFC_ULLRAM_BANK1725_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1725_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1726 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1726_DATA_W 32 -#define RFC_ULLRAM_BANK1726_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1726_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1727 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1727_DATA_W 32 -#define RFC_ULLRAM_BANK1727_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1727_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1728 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1728_DATA_W 32 -#define RFC_ULLRAM_BANK1728_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1728_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1729 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1729_DATA_W 32 -#define RFC_ULLRAM_BANK1729_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1729_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1730 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1730_DATA_W 32 -#define RFC_ULLRAM_BANK1730_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1730_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1731 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1731_DATA_W 32 -#define RFC_ULLRAM_BANK1731_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1731_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1732 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1732_DATA_W 32 -#define RFC_ULLRAM_BANK1732_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1732_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1733 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1733_DATA_W 32 -#define RFC_ULLRAM_BANK1733_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1733_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1734 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1734_DATA_W 32 -#define RFC_ULLRAM_BANK1734_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1734_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1735 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1735_DATA_W 32 -#define RFC_ULLRAM_BANK1735_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1735_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1736 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1736_DATA_W 32 -#define RFC_ULLRAM_BANK1736_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1736_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1737 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1737_DATA_W 32 -#define RFC_ULLRAM_BANK1737_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1737_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1738 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1738_DATA_W 32 -#define RFC_ULLRAM_BANK1738_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1738_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1739 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1739_DATA_W 32 -#define RFC_ULLRAM_BANK1739_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1739_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1740 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1740_DATA_W 32 -#define RFC_ULLRAM_BANK1740_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1740_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1741 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1741_DATA_W 32 -#define RFC_ULLRAM_BANK1741_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1741_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1742 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1742_DATA_W 32 -#define RFC_ULLRAM_BANK1742_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1742_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1743 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1743_DATA_W 32 -#define RFC_ULLRAM_BANK1743_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1743_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1744 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1744_DATA_W 32 -#define RFC_ULLRAM_BANK1744_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1744_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1745 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1745_DATA_W 32 -#define RFC_ULLRAM_BANK1745_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1745_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1746 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1746_DATA_W 32 -#define RFC_ULLRAM_BANK1746_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1746_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1747 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1747_DATA_W 32 -#define RFC_ULLRAM_BANK1747_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1747_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1748 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1748_DATA_W 32 -#define RFC_ULLRAM_BANK1748_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1748_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1749 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1749_DATA_W 32 -#define RFC_ULLRAM_BANK1749_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1749_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1750 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1750_DATA_W 32 -#define RFC_ULLRAM_BANK1750_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1750_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1751 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1751_DATA_W 32 -#define RFC_ULLRAM_BANK1751_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1751_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1752 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1752_DATA_W 32 -#define RFC_ULLRAM_BANK1752_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1752_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1753 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1753_DATA_W 32 -#define RFC_ULLRAM_BANK1753_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1753_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1754 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1754_DATA_W 32 -#define RFC_ULLRAM_BANK1754_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1754_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1755 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1755_DATA_W 32 -#define RFC_ULLRAM_BANK1755_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1755_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1756 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1756_DATA_W 32 -#define RFC_ULLRAM_BANK1756_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1756_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1757 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1757_DATA_W 32 -#define RFC_ULLRAM_BANK1757_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1757_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1758 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1758_DATA_W 32 -#define RFC_ULLRAM_BANK1758_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1758_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1759 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1759_DATA_W 32 -#define RFC_ULLRAM_BANK1759_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1759_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1760 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1760_DATA_W 32 -#define RFC_ULLRAM_BANK1760_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1760_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1761 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1761_DATA_W 32 -#define RFC_ULLRAM_BANK1761_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1761_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1762 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1762_DATA_W 32 -#define RFC_ULLRAM_BANK1762_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1762_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1763 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1763_DATA_W 32 -#define RFC_ULLRAM_BANK1763_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1763_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1764 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1764_DATA_W 32 -#define RFC_ULLRAM_BANK1764_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1764_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1765 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1765_DATA_W 32 -#define RFC_ULLRAM_BANK1765_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1765_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1766 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1766_DATA_W 32 -#define RFC_ULLRAM_BANK1766_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1766_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1767 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1767_DATA_W 32 -#define RFC_ULLRAM_BANK1767_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1767_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1768 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1768_DATA_W 32 -#define RFC_ULLRAM_BANK1768_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1768_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1769 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1769_DATA_W 32 -#define RFC_ULLRAM_BANK1769_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1769_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1770 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1770_DATA_W 32 -#define RFC_ULLRAM_BANK1770_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1770_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1771 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1771_DATA_W 32 -#define RFC_ULLRAM_BANK1771_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1771_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1772 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1772_DATA_W 32 -#define RFC_ULLRAM_BANK1772_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1772_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1773 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1773_DATA_W 32 -#define RFC_ULLRAM_BANK1773_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1773_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1774 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1774_DATA_W 32 -#define RFC_ULLRAM_BANK1774_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1774_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1775 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1775_DATA_W 32 -#define RFC_ULLRAM_BANK1775_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1775_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1776 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1776_DATA_W 32 -#define RFC_ULLRAM_BANK1776_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1776_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1777 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1777_DATA_W 32 -#define RFC_ULLRAM_BANK1777_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1777_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1778 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1778_DATA_W 32 -#define RFC_ULLRAM_BANK1778_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1778_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1779 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1779_DATA_W 32 -#define RFC_ULLRAM_BANK1779_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1779_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1780 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1780_DATA_W 32 -#define RFC_ULLRAM_BANK1780_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1780_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1781 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1781_DATA_W 32 -#define RFC_ULLRAM_BANK1781_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1781_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1782 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1782_DATA_W 32 -#define RFC_ULLRAM_BANK1782_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1782_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1783 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1783_DATA_W 32 -#define RFC_ULLRAM_BANK1783_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1783_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1784 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1784_DATA_W 32 -#define RFC_ULLRAM_BANK1784_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1784_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1785 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1785_DATA_W 32 -#define RFC_ULLRAM_BANK1785_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1785_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1786 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1786_DATA_W 32 -#define RFC_ULLRAM_BANK1786_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1786_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1787 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1787_DATA_W 32 -#define RFC_ULLRAM_BANK1787_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1787_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1788 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1788_DATA_W 32 -#define RFC_ULLRAM_BANK1788_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1788_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1789 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1789_DATA_W 32 -#define RFC_ULLRAM_BANK1789_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1789_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1790 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1790_DATA_W 32 -#define RFC_ULLRAM_BANK1790_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1790_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1791 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1791_DATA_W 32 -#define RFC_ULLRAM_BANK1791_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1791_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1792 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1792_DATA_W 32 -#define RFC_ULLRAM_BANK1792_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1792_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1793 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1793_DATA_W 32 -#define RFC_ULLRAM_BANK1793_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1793_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1794 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1794_DATA_W 32 -#define RFC_ULLRAM_BANK1794_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1794_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1795 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1795_DATA_W 32 -#define RFC_ULLRAM_BANK1795_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1795_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1796 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1796_DATA_W 32 -#define RFC_ULLRAM_BANK1796_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1796_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1797 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1797_DATA_W 32 -#define RFC_ULLRAM_BANK1797_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1797_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1798 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1798_DATA_W 32 -#define RFC_ULLRAM_BANK1798_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1798_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1799 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1799_DATA_W 32 -#define RFC_ULLRAM_BANK1799_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1799_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1800 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1800_DATA_W 32 -#define RFC_ULLRAM_BANK1800_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1800_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1801 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1801_DATA_W 32 -#define RFC_ULLRAM_BANK1801_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1801_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1802 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1802_DATA_W 32 -#define RFC_ULLRAM_BANK1802_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1802_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1803 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1803_DATA_W 32 -#define RFC_ULLRAM_BANK1803_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1803_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1804 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1804_DATA_W 32 -#define RFC_ULLRAM_BANK1804_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1804_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1805 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1805_DATA_W 32 -#define RFC_ULLRAM_BANK1805_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1805_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1806 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1806_DATA_W 32 -#define RFC_ULLRAM_BANK1806_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1806_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1807 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1807_DATA_W 32 -#define RFC_ULLRAM_BANK1807_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1807_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1808 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1808_DATA_W 32 -#define RFC_ULLRAM_BANK1808_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1808_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1809 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1809_DATA_W 32 -#define RFC_ULLRAM_BANK1809_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1809_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1810 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1810_DATA_W 32 -#define RFC_ULLRAM_BANK1810_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1810_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1811 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1811_DATA_W 32 -#define RFC_ULLRAM_BANK1811_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1811_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1812 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1812_DATA_W 32 -#define RFC_ULLRAM_BANK1812_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1812_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1813 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1813_DATA_W 32 -#define RFC_ULLRAM_BANK1813_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1813_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1814 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1814_DATA_W 32 -#define RFC_ULLRAM_BANK1814_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1814_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1815 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1815_DATA_W 32 -#define RFC_ULLRAM_BANK1815_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1815_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1816 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1816_DATA_W 32 -#define RFC_ULLRAM_BANK1816_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1816_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1817 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1817_DATA_W 32 -#define RFC_ULLRAM_BANK1817_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1817_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1818 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1818_DATA_W 32 -#define RFC_ULLRAM_BANK1818_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1818_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1819 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1819_DATA_W 32 -#define RFC_ULLRAM_BANK1819_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1819_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1820 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1820_DATA_W 32 -#define RFC_ULLRAM_BANK1820_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1820_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1821 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1821_DATA_W 32 -#define RFC_ULLRAM_BANK1821_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1821_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1822 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1822_DATA_W 32 -#define RFC_ULLRAM_BANK1822_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1822_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1823 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1823_DATA_W 32 -#define RFC_ULLRAM_BANK1823_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1823_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1824 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1824_DATA_W 32 -#define RFC_ULLRAM_BANK1824_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1824_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1825 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1825_DATA_W 32 -#define RFC_ULLRAM_BANK1825_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1825_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1826 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1826_DATA_W 32 -#define RFC_ULLRAM_BANK1826_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1826_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1827 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1827_DATA_W 32 -#define RFC_ULLRAM_BANK1827_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1827_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1828 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1828_DATA_W 32 -#define RFC_ULLRAM_BANK1828_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1828_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1829 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1829_DATA_W 32 -#define RFC_ULLRAM_BANK1829_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1829_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1830 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1830_DATA_W 32 -#define RFC_ULLRAM_BANK1830_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1830_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1831 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1831_DATA_W 32 -#define RFC_ULLRAM_BANK1831_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1831_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1832 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1832_DATA_W 32 -#define RFC_ULLRAM_BANK1832_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1832_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1833 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1833_DATA_W 32 -#define RFC_ULLRAM_BANK1833_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1833_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1834 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1834_DATA_W 32 -#define RFC_ULLRAM_BANK1834_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1834_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1835 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1835_DATA_W 32 -#define RFC_ULLRAM_BANK1835_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1835_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1836 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1836_DATA_W 32 -#define RFC_ULLRAM_BANK1836_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1836_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1837 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1837_DATA_W 32 -#define RFC_ULLRAM_BANK1837_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1837_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1838 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1838_DATA_W 32 -#define RFC_ULLRAM_BANK1838_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1838_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1839 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1839_DATA_W 32 -#define RFC_ULLRAM_BANK1839_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1839_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1840 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1840_DATA_W 32 -#define RFC_ULLRAM_BANK1840_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1840_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1841 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1841_DATA_W 32 -#define RFC_ULLRAM_BANK1841_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1841_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1842 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1842_DATA_W 32 -#define RFC_ULLRAM_BANK1842_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1842_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1843 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1843_DATA_W 32 -#define RFC_ULLRAM_BANK1843_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1843_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1844 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1844_DATA_W 32 -#define RFC_ULLRAM_BANK1844_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1844_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1845 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1845_DATA_W 32 -#define RFC_ULLRAM_BANK1845_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1845_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1846 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1846_DATA_W 32 -#define RFC_ULLRAM_BANK1846_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1846_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1847 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1847_DATA_W 32 -#define RFC_ULLRAM_BANK1847_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1847_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1848 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1848_DATA_W 32 -#define RFC_ULLRAM_BANK1848_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1848_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1849 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1849_DATA_W 32 -#define RFC_ULLRAM_BANK1849_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1849_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1850 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1850_DATA_W 32 -#define RFC_ULLRAM_BANK1850_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1850_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1851 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1851_DATA_W 32 -#define RFC_ULLRAM_BANK1851_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1851_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1852 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1852_DATA_W 32 -#define RFC_ULLRAM_BANK1852_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1852_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1853 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1853_DATA_W 32 -#define RFC_ULLRAM_BANK1853_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1853_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1854 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1854_DATA_W 32 -#define RFC_ULLRAM_BANK1854_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1854_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1855 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1855_DATA_W 32 -#define RFC_ULLRAM_BANK1855_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1855_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1856 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1856_DATA_W 32 -#define RFC_ULLRAM_BANK1856_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1856_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1857 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1857_DATA_W 32 -#define RFC_ULLRAM_BANK1857_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1857_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1858 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1858_DATA_W 32 -#define RFC_ULLRAM_BANK1858_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1858_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1859 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1859_DATA_W 32 -#define RFC_ULLRAM_BANK1859_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1859_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1860 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1860_DATA_W 32 -#define RFC_ULLRAM_BANK1860_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1860_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1861 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1861_DATA_W 32 -#define RFC_ULLRAM_BANK1861_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1861_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1862 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1862_DATA_W 32 -#define RFC_ULLRAM_BANK1862_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1862_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1863 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1863_DATA_W 32 -#define RFC_ULLRAM_BANK1863_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1863_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1864 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1864_DATA_W 32 -#define RFC_ULLRAM_BANK1864_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1864_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1865 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1865_DATA_W 32 -#define RFC_ULLRAM_BANK1865_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1865_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1866 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1866_DATA_W 32 -#define RFC_ULLRAM_BANK1866_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1866_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1867 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1867_DATA_W 32 -#define RFC_ULLRAM_BANK1867_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1867_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1868 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1868_DATA_W 32 -#define RFC_ULLRAM_BANK1868_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1868_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1869 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1869_DATA_W 32 -#define RFC_ULLRAM_BANK1869_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1869_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1870 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1870_DATA_W 32 -#define RFC_ULLRAM_BANK1870_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1870_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1871 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1871_DATA_W 32 -#define RFC_ULLRAM_BANK1871_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1871_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1872 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1872_DATA_W 32 -#define RFC_ULLRAM_BANK1872_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1872_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1873 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1873_DATA_W 32 -#define RFC_ULLRAM_BANK1873_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1873_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1874 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1874_DATA_W 32 -#define RFC_ULLRAM_BANK1874_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1874_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1875 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1875_DATA_W 32 -#define RFC_ULLRAM_BANK1875_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1875_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1876 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1876_DATA_W 32 -#define RFC_ULLRAM_BANK1876_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1876_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1877 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1877_DATA_W 32 -#define RFC_ULLRAM_BANK1877_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1877_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1878 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1878_DATA_W 32 -#define RFC_ULLRAM_BANK1878_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1878_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1879 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1879_DATA_W 32 -#define RFC_ULLRAM_BANK1879_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1879_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1880 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1880_DATA_W 32 -#define RFC_ULLRAM_BANK1880_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1880_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1881 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1881_DATA_W 32 -#define RFC_ULLRAM_BANK1881_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1881_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1882 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1882_DATA_W 32 -#define RFC_ULLRAM_BANK1882_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1882_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1883 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1883_DATA_W 32 -#define RFC_ULLRAM_BANK1883_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1883_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1884 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1884_DATA_W 32 -#define RFC_ULLRAM_BANK1884_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1884_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1885 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1885_DATA_W 32 -#define RFC_ULLRAM_BANK1885_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1885_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1886 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1886_DATA_W 32 -#define RFC_ULLRAM_BANK1886_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1886_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1887 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1887_DATA_W 32 -#define RFC_ULLRAM_BANK1887_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1887_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1888 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1888_DATA_W 32 -#define RFC_ULLRAM_BANK1888_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1888_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1889 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1889_DATA_W 32 -#define RFC_ULLRAM_BANK1889_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1889_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1890 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1890_DATA_W 32 -#define RFC_ULLRAM_BANK1890_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1890_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1891 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1891_DATA_W 32 -#define RFC_ULLRAM_BANK1891_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1891_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1892 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1892_DATA_W 32 -#define RFC_ULLRAM_BANK1892_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1892_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1893 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1893_DATA_W 32 -#define RFC_ULLRAM_BANK1893_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1893_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1894 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1894_DATA_W 32 -#define RFC_ULLRAM_BANK1894_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1894_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1895 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1895_DATA_W 32 -#define RFC_ULLRAM_BANK1895_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1895_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1896 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1896_DATA_W 32 -#define RFC_ULLRAM_BANK1896_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1896_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1897 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1897_DATA_W 32 -#define RFC_ULLRAM_BANK1897_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1897_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1898 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1898_DATA_W 32 -#define RFC_ULLRAM_BANK1898_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1898_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1899 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1899_DATA_W 32 -#define RFC_ULLRAM_BANK1899_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1899_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1900 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1900_DATA_W 32 -#define RFC_ULLRAM_BANK1900_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1900_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1901 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1901_DATA_W 32 -#define RFC_ULLRAM_BANK1901_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1901_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1902 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1902_DATA_W 32 -#define RFC_ULLRAM_BANK1902_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1902_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1903 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1903_DATA_W 32 -#define RFC_ULLRAM_BANK1903_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1903_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1904 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1904_DATA_W 32 -#define RFC_ULLRAM_BANK1904_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1904_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1905 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1905_DATA_W 32 -#define RFC_ULLRAM_BANK1905_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1905_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1906 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1906_DATA_W 32 -#define RFC_ULLRAM_BANK1906_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1906_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1907 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1907_DATA_W 32 -#define RFC_ULLRAM_BANK1907_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1907_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1908 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1908_DATA_W 32 -#define RFC_ULLRAM_BANK1908_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1908_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1909 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1909_DATA_W 32 -#define RFC_ULLRAM_BANK1909_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1909_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1910 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1910_DATA_W 32 -#define RFC_ULLRAM_BANK1910_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1910_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1911 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1911_DATA_W 32 -#define RFC_ULLRAM_BANK1911_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1911_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1912 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1912_DATA_W 32 -#define RFC_ULLRAM_BANK1912_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1912_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1913 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1913_DATA_W 32 -#define RFC_ULLRAM_BANK1913_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1913_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1914 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1914_DATA_W 32 -#define RFC_ULLRAM_BANK1914_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1914_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1915 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1915_DATA_W 32 -#define RFC_ULLRAM_BANK1915_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1915_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1916 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1916_DATA_W 32 -#define RFC_ULLRAM_BANK1916_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1916_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1917 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1917_DATA_W 32 -#define RFC_ULLRAM_BANK1917_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1917_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1918 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1918_DATA_W 32 -#define RFC_ULLRAM_BANK1918_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1918_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1919 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1919_DATA_W 32 -#define RFC_ULLRAM_BANK1919_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1919_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1920 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1920_DATA_W 32 -#define RFC_ULLRAM_BANK1920_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1920_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1921 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1921_DATA_W 32 -#define RFC_ULLRAM_BANK1921_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1921_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1922 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1922_DATA_W 32 -#define RFC_ULLRAM_BANK1922_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1922_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1923 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1923_DATA_W 32 -#define RFC_ULLRAM_BANK1923_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1923_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1924 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1924_DATA_W 32 -#define RFC_ULLRAM_BANK1924_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1924_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1925 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1925_DATA_W 32 -#define RFC_ULLRAM_BANK1925_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1925_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1926 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1926_DATA_W 32 -#define RFC_ULLRAM_BANK1926_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1926_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1927 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1927_DATA_W 32 -#define RFC_ULLRAM_BANK1927_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1927_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1928 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1928_DATA_W 32 -#define RFC_ULLRAM_BANK1928_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1928_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1929 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1929_DATA_W 32 -#define RFC_ULLRAM_BANK1929_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1929_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1930 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1930_DATA_W 32 -#define RFC_ULLRAM_BANK1930_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1930_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1931 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1931_DATA_W 32 -#define RFC_ULLRAM_BANK1931_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1931_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1932 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1932_DATA_W 32 -#define RFC_ULLRAM_BANK1932_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1932_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1933 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1933_DATA_W 32 -#define RFC_ULLRAM_BANK1933_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1933_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1934 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1934_DATA_W 32 -#define RFC_ULLRAM_BANK1934_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1934_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1935 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1935_DATA_W 32 -#define RFC_ULLRAM_BANK1935_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1935_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1936 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1936_DATA_W 32 -#define RFC_ULLRAM_BANK1936_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1936_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1937 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1937_DATA_W 32 -#define RFC_ULLRAM_BANK1937_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1937_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1938 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1938_DATA_W 32 -#define RFC_ULLRAM_BANK1938_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1938_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1939 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1939_DATA_W 32 -#define RFC_ULLRAM_BANK1939_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1939_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1940 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1940_DATA_W 32 -#define RFC_ULLRAM_BANK1940_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1940_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1941 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1941_DATA_W 32 -#define RFC_ULLRAM_BANK1941_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1941_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1942 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1942_DATA_W 32 -#define RFC_ULLRAM_BANK1942_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1942_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1943 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1943_DATA_W 32 -#define RFC_ULLRAM_BANK1943_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1943_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1944 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1944_DATA_W 32 -#define RFC_ULLRAM_BANK1944_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1944_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1945 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1945_DATA_W 32 -#define RFC_ULLRAM_BANK1945_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1945_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1946 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1946_DATA_W 32 -#define RFC_ULLRAM_BANK1946_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1946_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1947 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1947_DATA_W 32 -#define RFC_ULLRAM_BANK1947_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1947_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1948 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1948_DATA_W 32 -#define RFC_ULLRAM_BANK1948_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1948_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1949 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1949_DATA_W 32 -#define RFC_ULLRAM_BANK1949_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1949_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1950 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1950_DATA_W 32 -#define RFC_ULLRAM_BANK1950_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1950_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1951 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1951_DATA_W 32 -#define RFC_ULLRAM_BANK1951_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1951_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1952 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1952_DATA_W 32 -#define RFC_ULLRAM_BANK1952_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1952_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1953 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1953_DATA_W 32 -#define RFC_ULLRAM_BANK1953_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1953_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1954 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1954_DATA_W 32 -#define RFC_ULLRAM_BANK1954_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1954_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1955 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1955_DATA_W 32 -#define RFC_ULLRAM_BANK1955_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1955_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1956 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1956_DATA_W 32 -#define RFC_ULLRAM_BANK1956_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1956_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1957 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1957_DATA_W 32 -#define RFC_ULLRAM_BANK1957_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1957_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1958 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1958_DATA_W 32 -#define RFC_ULLRAM_BANK1958_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1958_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1959 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1959_DATA_W 32 -#define RFC_ULLRAM_BANK1959_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1959_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1960 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1960_DATA_W 32 -#define RFC_ULLRAM_BANK1960_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1960_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1961 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1961_DATA_W 32 -#define RFC_ULLRAM_BANK1961_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1961_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1962 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1962_DATA_W 32 -#define RFC_ULLRAM_BANK1962_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1962_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1963 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1963_DATA_W 32 -#define RFC_ULLRAM_BANK1963_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1963_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1964 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1964_DATA_W 32 -#define RFC_ULLRAM_BANK1964_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1964_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1965 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1965_DATA_W 32 -#define RFC_ULLRAM_BANK1965_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1965_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1966 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1966_DATA_W 32 -#define RFC_ULLRAM_BANK1966_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1966_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1967 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1967_DATA_W 32 -#define RFC_ULLRAM_BANK1967_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1967_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1968 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1968_DATA_W 32 -#define RFC_ULLRAM_BANK1968_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1968_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1969 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1969_DATA_W 32 -#define RFC_ULLRAM_BANK1969_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1969_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1970 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1970_DATA_W 32 -#define RFC_ULLRAM_BANK1970_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1970_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1971 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1971_DATA_W 32 -#define RFC_ULLRAM_BANK1971_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1971_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1972 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1972_DATA_W 32 -#define RFC_ULLRAM_BANK1972_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1972_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1973 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1973_DATA_W 32 -#define RFC_ULLRAM_BANK1973_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1973_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1974 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1974_DATA_W 32 -#define RFC_ULLRAM_BANK1974_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1974_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1975 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1975_DATA_W 32 -#define RFC_ULLRAM_BANK1975_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1975_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1976 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1976_DATA_W 32 -#define RFC_ULLRAM_BANK1976_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1976_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1977 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1977_DATA_W 32 -#define RFC_ULLRAM_BANK1977_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1977_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1978 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1978_DATA_W 32 -#define RFC_ULLRAM_BANK1978_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1978_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1979 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1979_DATA_W 32 -#define RFC_ULLRAM_BANK1979_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1979_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1980 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1980_DATA_W 32 -#define RFC_ULLRAM_BANK1980_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1980_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1981 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1981_DATA_W 32 -#define RFC_ULLRAM_BANK1981_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1981_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1982 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1982_DATA_W 32 -#define RFC_ULLRAM_BANK1982_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1982_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1983 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1983_DATA_W 32 -#define RFC_ULLRAM_BANK1983_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1983_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1984 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1984_DATA_W 32 -#define RFC_ULLRAM_BANK1984_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1984_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1985 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1985_DATA_W 32 -#define RFC_ULLRAM_BANK1985_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1985_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1986 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1986_DATA_W 32 -#define RFC_ULLRAM_BANK1986_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1986_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1987 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1987_DATA_W 32 -#define RFC_ULLRAM_BANK1987_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1987_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1988 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1988_DATA_W 32 -#define RFC_ULLRAM_BANK1988_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1988_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1989 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1989_DATA_W 32 -#define RFC_ULLRAM_BANK1989_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1989_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1990 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1990_DATA_W 32 -#define RFC_ULLRAM_BANK1990_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1990_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1991 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1991_DATA_W 32 -#define RFC_ULLRAM_BANK1991_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1991_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1992 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1992_DATA_W 32 -#define RFC_ULLRAM_BANK1992_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1992_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1993 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1993_DATA_W 32 -#define RFC_ULLRAM_BANK1993_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1993_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1994 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1994_DATA_W 32 -#define RFC_ULLRAM_BANK1994_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1994_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1995 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1995_DATA_W 32 -#define RFC_ULLRAM_BANK1995_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1995_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1996 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1996_DATA_W 32 -#define RFC_ULLRAM_BANK1996_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1996_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1997 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1997_DATA_W 32 -#define RFC_ULLRAM_BANK1997_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1997_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1998 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1998_DATA_W 32 -#define RFC_ULLRAM_BANK1998_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1998_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK1999 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK1999_DATA_W 32 -#define RFC_ULLRAM_BANK1999_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK1999_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11000 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11000_DATA_W 32 -#define RFC_ULLRAM_BANK11000_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11000_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11001 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11001_DATA_W 32 -#define RFC_ULLRAM_BANK11001_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11001_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11002 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11002_DATA_W 32 -#define RFC_ULLRAM_BANK11002_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11002_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11003 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11003_DATA_W 32 -#define RFC_ULLRAM_BANK11003_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11003_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11004 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11004_DATA_W 32 -#define RFC_ULLRAM_BANK11004_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11004_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11005 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11005_DATA_W 32 -#define RFC_ULLRAM_BANK11005_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11005_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11006 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11006_DATA_W 32 -#define RFC_ULLRAM_BANK11006_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11006_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11007 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11007_DATA_W 32 -#define RFC_ULLRAM_BANK11007_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11007_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11008 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11008_DATA_W 32 -#define RFC_ULLRAM_BANK11008_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11008_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11009 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11009_DATA_W 32 -#define RFC_ULLRAM_BANK11009_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11009_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11010 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11010_DATA_W 32 -#define RFC_ULLRAM_BANK11010_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11010_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11011 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11011_DATA_W 32 -#define RFC_ULLRAM_BANK11011_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11011_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11012 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11012_DATA_W 32 -#define RFC_ULLRAM_BANK11012_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11012_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11013 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11013_DATA_W 32 -#define RFC_ULLRAM_BANK11013_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11013_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11014 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11014_DATA_W 32 -#define RFC_ULLRAM_BANK11014_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11014_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11015 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11015_DATA_W 32 -#define RFC_ULLRAM_BANK11015_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11015_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11016 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11016_DATA_W 32 -#define RFC_ULLRAM_BANK11016_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11016_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11017 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11017_DATA_W 32 -#define RFC_ULLRAM_BANK11017_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11017_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11018 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11018_DATA_W 32 -#define RFC_ULLRAM_BANK11018_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11018_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11019 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11019_DATA_W 32 -#define RFC_ULLRAM_BANK11019_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11019_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11020 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11020_DATA_W 32 -#define RFC_ULLRAM_BANK11020_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11020_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11021 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11021_DATA_W 32 -#define RFC_ULLRAM_BANK11021_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11021_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11022 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11022_DATA_W 32 -#define RFC_ULLRAM_BANK11022_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11022_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11023 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11023_DATA_W 32 -#define RFC_ULLRAM_BANK11023_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11023_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11024 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11024_DATA_W 32 -#define RFC_ULLRAM_BANK11024_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11024_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11025 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11025_DATA_W 32 -#define RFC_ULLRAM_BANK11025_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11025_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11026 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11026_DATA_W 32 -#define RFC_ULLRAM_BANK11026_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11026_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11027 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11027_DATA_W 32 -#define RFC_ULLRAM_BANK11027_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11027_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11028 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11028_DATA_W 32 -#define RFC_ULLRAM_BANK11028_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11028_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11029 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11029_DATA_W 32 -#define RFC_ULLRAM_BANK11029_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11029_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11030 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11030_DATA_W 32 -#define RFC_ULLRAM_BANK11030_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11030_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11031 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11031_DATA_W 32 -#define RFC_ULLRAM_BANK11031_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11031_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11032 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11032_DATA_W 32 -#define RFC_ULLRAM_BANK11032_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11032_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11033 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11033_DATA_W 32 -#define RFC_ULLRAM_BANK11033_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11033_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11034 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11034_DATA_W 32 -#define RFC_ULLRAM_BANK11034_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11034_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11035 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11035_DATA_W 32 -#define RFC_ULLRAM_BANK11035_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11035_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11036 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11036_DATA_W 32 -#define RFC_ULLRAM_BANK11036_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11036_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11037 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11037_DATA_W 32 -#define RFC_ULLRAM_BANK11037_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11037_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11038 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11038_DATA_W 32 -#define RFC_ULLRAM_BANK11038_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11038_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11039 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11039_DATA_W 32 -#define RFC_ULLRAM_BANK11039_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11039_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11040 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11040_DATA_W 32 -#define RFC_ULLRAM_BANK11040_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11040_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11041 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11041_DATA_W 32 -#define RFC_ULLRAM_BANK11041_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11041_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11042 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11042_DATA_W 32 -#define RFC_ULLRAM_BANK11042_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11042_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11043 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11043_DATA_W 32 -#define RFC_ULLRAM_BANK11043_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11043_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11044 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11044_DATA_W 32 -#define RFC_ULLRAM_BANK11044_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11044_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11045 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11045_DATA_W 32 -#define RFC_ULLRAM_BANK11045_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11045_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11046 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11046_DATA_W 32 -#define RFC_ULLRAM_BANK11046_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11046_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11047 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11047_DATA_W 32 -#define RFC_ULLRAM_BANK11047_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11047_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11048 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11048_DATA_W 32 -#define RFC_ULLRAM_BANK11048_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11048_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11049 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11049_DATA_W 32 -#define RFC_ULLRAM_BANK11049_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11049_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11050 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11050_DATA_W 32 -#define RFC_ULLRAM_BANK11050_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11050_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11051 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11051_DATA_W 32 -#define RFC_ULLRAM_BANK11051_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11051_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11052 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11052_DATA_W 32 -#define RFC_ULLRAM_BANK11052_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11052_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11053 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11053_DATA_W 32 -#define RFC_ULLRAM_BANK11053_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11053_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11054 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11054_DATA_W 32 -#define RFC_ULLRAM_BANK11054_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11054_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11055 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11055_DATA_W 32 -#define RFC_ULLRAM_BANK11055_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11055_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11056 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11056_DATA_W 32 -#define RFC_ULLRAM_BANK11056_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11056_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11057 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11057_DATA_W 32 -#define RFC_ULLRAM_BANK11057_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11057_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11058 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11058_DATA_W 32 -#define RFC_ULLRAM_BANK11058_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11058_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11059 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11059_DATA_W 32 -#define RFC_ULLRAM_BANK11059_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11059_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11060 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11060_DATA_W 32 -#define RFC_ULLRAM_BANK11060_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11060_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11061 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11061_DATA_W 32 -#define RFC_ULLRAM_BANK11061_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11061_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11062 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11062_DATA_W 32 -#define RFC_ULLRAM_BANK11062_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11062_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11063 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11063_DATA_W 32 -#define RFC_ULLRAM_BANK11063_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11063_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11064 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11064_DATA_W 32 -#define RFC_ULLRAM_BANK11064_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11064_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11065 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11065_DATA_W 32 -#define RFC_ULLRAM_BANK11065_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11065_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11066 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11066_DATA_W 32 -#define RFC_ULLRAM_BANK11066_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11066_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11067 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11067_DATA_W 32 -#define RFC_ULLRAM_BANK11067_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11067_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11068 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11068_DATA_W 32 -#define RFC_ULLRAM_BANK11068_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11068_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11069 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11069_DATA_W 32 -#define RFC_ULLRAM_BANK11069_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11069_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11070 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11070_DATA_W 32 -#define RFC_ULLRAM_BANK11070_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11070_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11071 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11071_DATA_W 32 -#define RFC_ULLRAM_BANK11071_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11071_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11072 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11072_DATA_W 32 -#define RFC_ULLRAM_BANK11072_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11072_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11073 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11073_DATA_W 32 -#define RFC_ULLRAM_BANK11073_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11073_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11074 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11074_DATA_W 32 -#define RFC_ULLRAM_BANK11074_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11074_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11075 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11075_DATA_W 32 -#define RFC_ULLRAM_BANK11075_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11075_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11076 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11076_DATA_W 32 -#define RFC_ULLRAM_BANK11076_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11076_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11077 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11077_DATA_W 32 -#define RFC_ULLRAM_BANK11077_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11077_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11078 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11078_DATA_W 32 -#define RFC_ULLRAM_BANK11078_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11078_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11079 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11079_DATA_W 32 -#define RFC_ULLRAM_BANK11079_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11079_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11080 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11080_DATA_W 32 -#define RFC_ULLRAM_BANK11080_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11080_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11081 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11081_DATA_W 32 -#define RFC_ULLRAM_BANK11081_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11081_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11082 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11082_DATA_W 32 -#define RFC_ULLRAM_BANK11082_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11082_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11083 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11083_DATA_W 32 -#define RFC_ULLRAM_BANK11083_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11083_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11084 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11084_DATA_W 32 -#define RFC_ULLRAM_BANK11084_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11084_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11085 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11085_DATA_W 32 -#define RFC_ULLRAM_BANK11085_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11085_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11086 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11086_DATA_W 32 -#define RFC_ULLRAM_BANK11086_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11086_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11087 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11087_DATA_W 32 -#define RFC_ULLRAM_BANK11087_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11087_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11088 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11088_DATA_W 32 -#define RFC_ULLRAM_BANK11088_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11088_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11089 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11089_DATA_W 32 -#define RFC_ULLRAM_BANK11089_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11089_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11090 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11090_DATA_W 32 -#define RFC_ULLRAM_BANK11090_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11090_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11091 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11091_DATA_W 32 -#define RFC_ULLRAM_BANK11091_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11091_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11092 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11092_DATA_W 32 -#define RFC_ULLRAM_BANK11092_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11092_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11093 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11093_DATA_W 32 -#define RFC_ULLRAM_BANK11093_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11093_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11094 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11094_DATA_W 32 -#define RFC_ULLRAM_BANK11094_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11094_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11095 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11095_DATA_W 32 -#define RFC_ULLRAM_BANK11095_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11095_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11096 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11096_DATA_W 32 -#define RFC_ULLRAM_BANK11096_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11096_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11097 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11097_DATA_W 32 -#define RFC_ULLRAM_BANK11097_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11097_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11098 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11098_DATA_W 32 -#define RFC_ULLRAM_BANK11098_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11098_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11099 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11099_DATA_W 32 -#define RFC_ULLRAM_BANK11099_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11099_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11100 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11100_DATA_W 32 -#define RFC_ULLRAM_BANK11100_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11100_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11101 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11101_DATA_W 32 -#define RFC_ULLRAM_BANK11101_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11101_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11102 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11102_DATA_W 32 -#define RFC_ULLRAM_BANK11102_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11102_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11103 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11103_DATA_W 32 -#define RFC_ULLRAM_BANK11103_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11103_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11104 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11104_DATA_W 32 -#define RFC_ULLRAM_BANK11104_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11104_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11105 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11105_DATA_W 32 -#define RFC_ULLRAM_BANK11105_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11105_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11106 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11106_DATA_W 32 -#define RFC_ULLRAM_BANK11106_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11106_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11107 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11107_DATA_W 32 -#define RFC_ULLRAM_BANK11107_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11107_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11108 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11108_DATA_W 32 -#define RFC_ULLRAM_BANK11108_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11108_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11109 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11109_DATA_W 32 -#define RFC_ULLRAM_BANK11109_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11109_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11110 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11110_DATA_W 32 -#define RFC_ULLRAM_BANK11110_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11110_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11111 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11111_DATA_W 32 -#define RFC_ULLRAM_BANK11111_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11111_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11112 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11112_DATA_W 32 -#define RFC_ULLRAM_BANK11112_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11112_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11113 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11113_DATA_W 32 -#define RFC_ULLRAM_BANK11113_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11113_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11114 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11114_DATA_W 32 -#define RFC_ULLRAM_BANK11114_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11114_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11115 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11115_DATA_W 32 -#define RFC_ULLRAM_BANK11115_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11115_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11116 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11116_DATA_W 32 -#define RFC_ULLRAM_BANK11116_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11116_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11117 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11117_DATA_W 32 -#define RFC_ULLRAM_BANK11117_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11117_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11118 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11118_DATA_W 32 -#define RFC_ULLRAM_BANK11118_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11118_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11119 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11119_DATA_W 32 -#define RFC_ULLRAM_BANK11119_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11119_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11120 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11120_DATA_W 32 -#define RFC_ULLRAM_BANK11120_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11120_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11121 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11121_DATA_W 32 -#define RFC_ULLRAM_BANK11121_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11121_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11122 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11122_DATA_W 32 -#define RFC_ULLRAM_BANK11122_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11122_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11123 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11123_DATA_W 32 -#define RFC_ULLRAM_BANK11123_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11123_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11124 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11124_DATA_W 32 -#define RFC_ULLRAM_BANK11124_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11124_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11125 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11125_DATA_W 32 -#define RFC_ULLRAM_BANK11125_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11125_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11126 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11126_DATA_W 32 -#define RFC_ULLRAM_BANK11126_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11126_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11127 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11127_DATA_W 32 -#define RFC_ULLRAM_BANK11127_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11127_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11128 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11128_DATA_W 32 -#define RFC_ULLRAM_BANK11128_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11128_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11129 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11129_DATA_W 32 -#define RFC_ULLRAM_BANK11129_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11129_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11130 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11130_DATA_W 32 -#define RFC_ULLRAM_BANK11130_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11130_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11131 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11131_DATA_W 32 -#define RFC_ULLRAM_BANK11131_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11131_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11132 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11132_DATA_W 32 -#define RFC_ULLRAM_BANK11132_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11132_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11133 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11133_DATA_W 32 -#define RFC_ULLRAM_BANK11133_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11133_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11134 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11134_DATA_W 32 -#define RFC_ULLRAM_BANK11134_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11134_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11135 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11135_DATA_W 32 -#define RFC_ULLRAM_BANK11135_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11135_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11136 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11136_DATA_W 32 -#define RFC_ULLRAM_BANK11136_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11136_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11137 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11137_DATA_W 32 -#define RFC_ULLRAM_BANK11137_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11137_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11138 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11138_DATA_W 32 -#define RFC_ULLRAM_BANK11138_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11138_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11139 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11139_DATA_W 32 -#define RFC_ULLRAM_BANK11139_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11139_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11140 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11140_DATA_W 32 -#define RFC_ULLRAM_BANK11140_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11140_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11141 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11141_DATA_W 32 -#define RFC_ULLRAM_BANK11141_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11141_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11142 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11142_DATA_W 32 -#define RFC_ULLRAM_BANK11142_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11142_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11143 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11143_DATA_W 32 -#define RFC_ULLRAM_BANK11143_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11143_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11144 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11144_DATA_W 32 -#define RFC_ULLRAM_BANK11144_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11144_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11145 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11145_DATA_W 32 -#define RFC_ULLRAM_BANK11145_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11145_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11146 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11146_DATA_W 32 -#define RFC_ULLRAM_BANK11146_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11146_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11147 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11147_DATA_W 32 -#define RFC_ULLRAM_BANK11147_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11147_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11148 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11148_DATA_W 32 -#define RFC_ULLRAM_BANK11148_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11148_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11149 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11149_DATA_W 32 -#define RFC_ULLRAM_BANK11149_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11149_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11150 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11150_DATA_W 32 -#define RFC_ULLRAM_BANK11150_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11150_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11151 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11151_DATA_W 32 -#define RFC_ULLRAM_BANK11151_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11151_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11152 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11152_DATA_W 32 -#define RFC_ULLRAM_BANK11152_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11152_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11153 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11153_DATA_W 32 -#define RFC_ULLRAM_BANK11153_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11153_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11154 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11154_DATA_W 32 -#define RFC_ULLRAM_BANK11154_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11154_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11155 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11155_DATA_W 32 -#define RFC_ULLRAM_BANK11155_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11155_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11156 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11156_DATA_W 32 -#define RFC_ULLRAM_BANK11156_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11156_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11157 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11157_DATA_W 32 -#define RFC_ULLRAM_BANK11157_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11157_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11158 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11158_DATA_W 32 -#define RFC_ULLRAM_BANK11158_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11158_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11159 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11159_DATA_W 32 -#define RFC_ULLRAM_BANK11159_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11159_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11160 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11160_DATA_W 32 -#define RFC_ULLRAM_BANK11160_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11160_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11161 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11161_DATA_W 32 -#define RFC_ULLRAM_BANK11161_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11161_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11162 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11162_DATA_W 32 -#define RFC_ULLRAM_BANK11162_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11162_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11163 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11163_DATA_W 32 -#define RFC_ULLRAM_BANK11163_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11163_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11164 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11164_DATA_W 32 -#define RFC_ULLRAM_BANK11164_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11164_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11165 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11165_DATA_W 32 -#define RFC_ULLRAM_BANK11165_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11165_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11166 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11166_DATA_W 32 -#define RFC_ULLRAM_BANK11166_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11166_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11167 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11167_DATA_W 32 -#define RFC_ULLRAM_BANK11167_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11167_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11168 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11168_DATA_W 32 -#define RFC_ULLRAM_BANK11168_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11168_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11169 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11169_DATA_W 32 -#define RFC_ULLRAM_BANK11169_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11169_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11170 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11170_DATA_W 32 -#define RFC_ULLRAM_BANK11170_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11170_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11171 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11171_DATA_W 32 -#define RFC_ULLRAM_BANK11171_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11171_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11172 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11172_DATA_W 32 -#define RFC_ULLRAM_BANK11172_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11172_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11173 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11173_DATA_W 32 -#define RFC_ULLRAM_BANK11173_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11173_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11174 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11174_DATA_W 32 -#define RFC_ULLRAM_BANK11174_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11174_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11175 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11175_DATA_W 32 -#define RFC_ULLRAM_BANK11175_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11175_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11176 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11176_DATA_W 32 -#define RFC_ULLRAM_BANK11176_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11176_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11177 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11177_DATA_W 32 -#define RFC_ULLRAM_BANK11177_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11177_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11178 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11178_DATA_W 32 -#define RFC_ULLRAM_BANK11178_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11178_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11179 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11179_DATA_W 32 -#define RFC_ULLRAM_BANK11179_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11179_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11180 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11180_DATA_W 32 -#define RFC_ULLRAM_BANK11180_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11180_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11181 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11181_DATA_W 32 -#define RFC_ULLRAM_BANK11181_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11181_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11182 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11182_DATA_W 32 -#define RFC_ULLRAM_BANK11182_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11182_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11183 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11183_DATA_W 32 -#define RFC_ULLRAM_BANK11183_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11183_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11184 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11184_DATA_W 32 -#define RFC_ULLRAM_BANK11184_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11184_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11185 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11185_DATA_W 32 -#define RFC_ULLRAM_BANK11185_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11185_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11186 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11186_DATA_W 32 -#define RFC_ULLRAM_BANK11186_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11186_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11187 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11187_DATA_W 32 -#define RFC_ULLRAM_BANK11187_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11187_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11188 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11188_DATA_W 32 -#define RFC_ULLRAM_BANK11188_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11188_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11189 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11189_DATA_W 32 -#define RFC_ULLRAM_BANK11189_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11189_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11190 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11190_DATA_W 32 -#define RFC_ULLRAM_BANK11190_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11190_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11191 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11191_DATA_W 32 -#define RFC_ULLRAM_BANK11191_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11191_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11192 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11192_DATA_W 32 -#define RFC_ULLRAM_BANK11192_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11192_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11193 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11193_DATA_W 32 -#define RFC_ULLRAM_BANK11193_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11193_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11194 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11194_DATA_W 32 -#define RFC_ULLRAM_BANK11194_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11194_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11195 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11195_DATA_W 32 -#define RFC_ULLRAM_BANK11195_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11195_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11196 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11196_DATA_W 32 -#define RFC_ULLRAM_BANK11196_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11196_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11197 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11197_DATA_W 32 -#define RFC_ULLRAM_BANK11197_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11197_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11198 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11198_DATA_W 32 -#define RFC_ULLRAM_BANK11198_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11198_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11199 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11199_DATA_W 32 -#define RFC_ULLRAM_BANK11199_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11199_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11200 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11200_DATA_W 32 -#define RFC_ULLRAM_BANK11200_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11200_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11201 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11201_DATA_W 32 -#define RFC_ULLRAM_BANK11201_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11201_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11202 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11202_DATA_W 32 -#define RFC_ULLRAM_BANK11202_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11202_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11203 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11203_DATA_W 32 -#define RFC_ULLRAM_BANK11203_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11203_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11204 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11204_DATA_W 32 -#define RFC_ULLRAM_BANK11204_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11204_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11205 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11205_DATA_W 32 -#define RFC_ULLRAM_BANK11205_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11205_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11206 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11206_DATA_W 32 -#define RFC_ULLRAM_BANK11206_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11206_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11207 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11207_DATA_W 32 -#define RFC_ULLRAM_BANK11207_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11207_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11208 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11208_DATA_W 32 -#define RFC_ULLRAM_BANK11208_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11208_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11209 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11209_DATA_W 32 -#define RFC_ULLRAM_BANK11209_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11209_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11210 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11210_DATA_W 32 -#define RFC_ULLRAM_BANK11210_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11210_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11211 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11211_DATA_W 32 -#define RFC_ULLRAM_BANK11211_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11211_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11212 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11212_DATA_W 32 -#define RFC_ULLRAM_BANK11212_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11212_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11213 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11213_DATA_W 32 -#define RFC_ULLRAM_BANK11213_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11213_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11214 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11214_DATA_W 32 -#define RFC_ULLRAM_BANK11214_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11214_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11215 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11215_DATA_W 32 -#define RFC_ULLRAM_BANK11215_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11215_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11216 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11216_DATA_W 32 -#define RFC_ULLRAM_BANK11216_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11216_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11217 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11217_DATA_W 32 -#define RFC_ULLRAM_BANK11217_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11217_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11218 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11218_DATA_W 32 -#define RFC_ULLRAM_BANK11218_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11218_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11219 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11219_DATA_W 32 -#define RFC_ULLRAM_BANK11219_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11219_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11220 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11220_DATA_W 32 -#define RFC_ULLRAM_BANK11220_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11220_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11221 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11221_DATA_W 32 -#define RFC_ULLRAM_BANK11221_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11221_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11222 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11222_DATA_W 32 -#define RFC_ULLRAM_BANK11222_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11222_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11223 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11223_DATA_W 32 -#define RFC_ULLRAM_BANK11223_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11223_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11224 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11224_DATA_W 32 -#define RFC_ULLRAM_BANK11224_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11224_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11225 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11225_DATA_W 32 -#define RFC_ULLRAM_BANK11225_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11225_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11226 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11226_DATA_W 32 -#define RFC_ULLRAM_BANK11226_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11226_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11227 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11227_DATA_W 32 -#define RFC_ULLRAM_BANK11227_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11227_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11228 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11228_DATA_W 32 -#define RFC_ULLRAM_BANK11228_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11228_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11229 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11229_DATA_W 32 -#define RFC_ULLRAM_BANK11229_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11229_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11230 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11230_DATA_W 32 -#define RFC_ULLRAM_BANK11230_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11230_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11231 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11231_DATA_W 32 -#define RFC_ULLRAM_BANK11231_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11231_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11232 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11232_DATA_W 32 -#define RFC_ULLRAM_BANK11232_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11232_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11233 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11233_DATA_W 32 -#define RFC_ULLRAM_BANK11233_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11233_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11234 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11234_DATA_W 32 -#define RFC_ULLRAM_BANK11234_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11234_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11235 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11235_DATA_W 32 -#define RFC_ULLRAM_BANK11235_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11235_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11236 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11236_DATA_W 32 -#define RFC_ULLRAM_BANK11236_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11236_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11237 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11237_DATA_W 32 -#define RFC_ULLRAM_BANK11237_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11237_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11238 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11238_DATA_W 32 -#define RFC_ULLRAM_BANK11238_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11238_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11239 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11239_DATA_W 32 -#define RFC_ULLRAM_BANK11239_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11239_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11240 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11240_DATA_W 32 -#define RFC_ULLRAM_BANK11240_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11240_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11241 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11241_DATA_W 32 -#define RFC_ULLRAM_BANK11241_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11241_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11242 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11242_DATA_W 32 -#define RFC_ULLRAM_BANK11242_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11242_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11243 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11243_DATA_W 32 -#define RFC_ULLRAM_BANK11243_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11243_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11244 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11244_DATA_W 32 -#define RFC_ULLRAM_BANK11244_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11244_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11245 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11245_DATA_W 32 -#define RFC_ULLRAM_BANK11245_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11245_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11246 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11246_DATA_W 32 -#define RFC_ULLRAM_BANK11246_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11246_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11247 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11247_DATA_W 32 -#define RFC_ULLRAM_BANK11247_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11247_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11248 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11248_DATA_W 32 -#define RFC_ULLRAM_BANK11248_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11248_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11249 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11249_DATA_W 32 -#define RFC_ULLRAM_BANK11249_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11249_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11250 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11250_DATA_W 32 -#define RFC_ULLRAM_BANK11250_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11250_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11251 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11251_DATA_W 32 -#define RFC_ULLRAM_BANK11251_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11251_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11252 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11252_DATA_W 32 -#define RFC_ULLRAM_BANK11252_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11252_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11253 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11253_DATA_W 32 -#define RFC_ULLRAM_BANK11253_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11253_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11254 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11254_DATA_W 32 -#define RFC_ULLRAM_BANK11254_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11254_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11255 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11255_DATA_W 32 -#define RFC_ULLRAM_BANK11255_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11255_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11256 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11256_DATA_W 32 -#define RFC_ULLRAM_BANK11256_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11256_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11257 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11257_DATA_W 32 -#define RFC_ULLRAM_BANK11257_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11257_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11258 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11258_DATA_W 32 -#define RFC_ULLRAM_BANK11258_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11258_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11259 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11259_DATA_W 32 -#define RFC_ULLRAM_BANK11259_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11259_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11260 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11260_DATA_W 32 -#define RFC_ULLRAM_BANK11260_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11260_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11261 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11261_DATA_W 32 -#define RFC_ULLRAM_BANK11261_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11261_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11262 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11262_DATA_W 32 -#define RFC_ULLRAM_BANK11262_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11262_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11263 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11263_DATA_W 32 -#define RFC_ULLRAM_BANK11263_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11263_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11264 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11264_DATA_W 32 -#define RFC_ULLRAM_BANK11264_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11264_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11265 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11265_DATA_W 32 -#define RFC_ULLRAM_BANK11265_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11265_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11266 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11266_DATA_W 32 -#define RFC_ULLRAM_BANK11266_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11266_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11267 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11267_DATA_W 32 -#define RFC_ULLRAM_BANK11267_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11267_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11268 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11268_DATA_W 32 -#define RFC_ULLRAM_BANK11268_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11268_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11269 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11269_DATA_W 32 -#define RFC_ULLRAM_BANK11269_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11269_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11270 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11270_DATA_W 32 -#define RFC_ULLRAM_BANK11270_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11270_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11271 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11271_DATA_W 32 -#define RFC_ULLRAM_BANK11271_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11271_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11272 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11272_DATA_W 32 -#define RFC_ULLRAM_BANK11272_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11272_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11273 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11273_DATA_W 32 -#define RFC_ULLRAM_BANK11273_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11273_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11274 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11274_DATA_W 32 -#define RFC_ULLRAM_BANK11274_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11274_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11275 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11275_DATA_W 32 -#define RFC_ULLRAM_BANK11275_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11275_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11276 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11276_DATA_W 32 -#define RFC_ULLRAM_BANK11276_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11276_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11277 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11277_DATA_W 32 -#define RFC_ULLRAM_BANK11277_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11277_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11278 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11278_DATA_W 32 -#define RFC_ULLRAM_BANK11278_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11278_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11279 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11279_DATA_W 32 -#define RFC_ULLRAM_BANK11279_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11279_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11280 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11280_DATA_W 32 -#define RFC_ULLRAM_BANK11280_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11280_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11281 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11281_DATA_W 32 -#define RFC_ULLRAM_BANK11281_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11281_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11282 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11282_DATA_W 32 -#define RFC_ULLRAM_BANK11282_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11282_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11283 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11283_DATA_W 32 -#define RFC_ULLRAM_BANK11283_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11283_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11284 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11284_DATA_W 32 -#define RFC_ULLRAM_BANK11284_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11284_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11285 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11285_DATA_W 32 -#define RFC_ULLRAM_BANK11285_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11285_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11286 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11286_DATA_W 32 -#define RFC_ULLRAM_BANK11286_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11286_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11287 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11287_DATA_W 32 -#define RFC_ULLRAM_BANK11287_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11287_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11288 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11288_DATA_W 32 -#define RFC_ULLRAM_BANK11288_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11288_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11289 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11289_DATA_W 32 -#define RFC_ULLRAM_BANK11289_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11289_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11290 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11290_DATA_W 32 -#define RFC_ULLRAM_BANK11290_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11290_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11291 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11291_DATA_W 32 -#define RFC_ULLRAM_BANK11291_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11291_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11292 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11292_DATA_W 32 -#define RFC_ULLRAM_BANK11292_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11292_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11293 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11293_DATA_W 32 -#define RFC_ULLRAM_BANK11293_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11293_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11294 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11294_DATA_W 32 -#define RFC_ULLRAM_BANK11294_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11294_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11295 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11295_DATA_W 32 -#define RFC_ULLRAM_BANK11295_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11295_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11296 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11296_DATA_W 32 -#define RFC_ULLRAM_BANK11296_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11296_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11297 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11297_DATA_W 32 -#define RFC_ULLRAM_BANK11297_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11297_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11298 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11298_DATA_W 32 -#define RFC_ULLRAM_BANK11298_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11298_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11299 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11299_DATA_W 32 -#define RFC_ULLRAM_BANK11299_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11299_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11300 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11300_DATA_W 32 -#define RFC_ULLRAM_BANK11300_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11300_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11301 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11301_DATA_W 32 -#define RFC_ULLRAM_BANK11301_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11301_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11302 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11302_DATA_W 32 -#define RFC_ULLRAM_BANK11302_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11302_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11303 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11303_DATA_W 32 -#define RFC_ULLRAM_BANK11303_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11303_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11304 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11304_DATA_W 32 -#define RFC_ULLRAM_BANK11304_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11304_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11305 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11305_DATA_W 32 -#define RFC_ULLRAM_BANK11305_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11305_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11306 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11306_DATA_W 32 -#define RFC_ULLRAM_BANK11306_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11306_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11307 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11307_DATA_W 32 -#define RFC_ULLRAM_BANK11307_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11307_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11308 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11308_DATA_W 32 -#define RFC_ULLRAM_BANK11308_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11308_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11309 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11309_DATA_W 32 -#define RFC_ULLRAM_BANK11309_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11309_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11310 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11310_DATA_W 32 -#define RFC_ULLRAM_BANK11310_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11310_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11311 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11311_DATA_W 32 -#define RFC_ULLRAM_BANK11311_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11311_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11312 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11312_DATA_W 32 -#define RFC_ULLRAM_BANK11312_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11312_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11313 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11313_DATA_W 32 -#define RFC_ULLRAM_BANK11313_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11313_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11314 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11314_DATA_W 32 -#define RFC_ULLRAM_BANK11314_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11314_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11315 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11315_DATA_W 32 -#define RFC_ULLRAM_BANK11315_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11315_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11316 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11316_DATA_W 32 -#define RFC_ULLRAM_BANK11316_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11316_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11317 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11317_DATA_W 32 -#define RFC_ULLRAM_BANK11317_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11317_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11318 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11318_DATA_W 32 -#define RFC_ULLRAM_BANK11318_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11318_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11319 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11319_DATA_W 32 -#define RFC_ULLRAM_BANK11319_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11319_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11320 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11320_DATA_W 32 -#define RFC_ULLRAM_BANK11320_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11320_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11321 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11321_DATA_W 32 -#define RFC_ULLRAM_BANK11321_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11321_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11322 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11322_DATA_W 32 -#define RFC_ULLRAM_BANK11322_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11322_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11323 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11323_DATA_W 32 -#define RFC_ULLRAM_BANK11323_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11323_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11324 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11324_DATA_W 32 -#define RFC_ULLRAM_BANK11324_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11324_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11325 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11325_DATA_W 32 -#define RFC_ULLRAM_BANK11325_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11325_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11326 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11326_DATA_W 32 -#define RFC_ULLRAM_BANK11326_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11326_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11327 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11327_DATA_W 32 -#define RFC_ULLRAM_BANK11327_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11327_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11328 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11328_DATA_W 32 -#define RFC_ULLRAM_BANK11328_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11328_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11329 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11329_DATA_W 32 -#define RFC_ULLRAM_BANK11329_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11329_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11330 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11330_DATA_W 32 -#define RFC_ULLRAM_BANK11330_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11330_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11331 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11331_DATA_W 32 -#define RFC_ULLRAM_BANK11331_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11331_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11332 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11332_DATA_W 32 -#define RFC_ULLRAM_BANK11332_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11332_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11333 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11333_DATA_W 32 -#define RFC_ULLRAM_BANK11333_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11333_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11334 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11334_DATA_W 32 -#define RFC_ULLRAM_BANK11334_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11334_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11335 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11335_DATA_W 32 -#define RFC_ULLRAM_BANK11335_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11335_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11336 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11336_DATA_W 32 -#define RFC_ULLRAM_BANK11336_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11336_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11337 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11337_DATA_W 32 -#define RFC_ULLRAM_BANK11337_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11337_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11338 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11338_DATA_W 32 -#define RFC_ULLRAM_BANK11338_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11338_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11339 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11339_DATA_W 32 -#define RFC_ULLRAM_BANK11339_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11339_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11340 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11340_DATA_W 32 -#define RFC_ULLRAM_BANK11340_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11340_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11341 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11341_DATA_W 32 -#define RFC_ULLRAM_BANK11341_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11341_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11342 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11342_DATA_W 32 -#define RFC_ULLRAM_BANK11342_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11342_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11343 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11343_DATA_W 32 -#define RFC_ULLRAM_BANK11343_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11343_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11344 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11344_DATA_W 32 -#define RFC_ULLRAM_BANK11344_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11344_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11345 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11345_DATA_W 32 -#define RFC_ULLRAM_BANK11345_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11345_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11346 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11346_DATA_W 32 -#define RFC_ULLRAM_BANK11346_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11346_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11347 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11347_DATA_W 32 -#define RFC_ULLRAM_BANK11347_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11347_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11348 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11348_DATA_W 32 -#define RFC_ULLRAM_BANK11348_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11348_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11349 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11349_DATA_W 32 -#define RFC_ULLRAM_BANK11349_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11349_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11350 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11350_DATA_W 32 -#define RFC_ULLRAM_BANK11350_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11350_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11351 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11351_DATA_W 32 -#define RFC_ULLRAM_BANK11351_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11351_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11352 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11352_DATA_W 32 -#define RFC_ULLRAM_BANK11352_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11352_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11353 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11353_DATA_W 32 -#define RFC_ULLRAM_BANK11353_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11353_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11354 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11354_DATA_W 32 -#define RFC_ULLRAM_BANK11354_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11354_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11355 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11355_DATA_W 32 -#define RFC_ULLRAM_BANK11355_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11355_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11356 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11356_DATA_W 32 -#define RFC_ULLRAM_BANK11356_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11356_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11357 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11357_DATA_W 32 -#define RFC_ULLRAM_BANK11357_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11357_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11358 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11358_DATA_W 32 -#define RFC_ULLRAM_BANK11358_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11358_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11359 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11359_DATA_W 32 -#define RFC_ULLRAM_BANK11359_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11359_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11360 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11360_DATA_W 32 -#define RFC_ULLRAM_BANK11360_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11360_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11361 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11361_DATA_W 32 -#define RFC_ULLRAM_BANK11361_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11361_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11362 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11362_DATA_W 32 -#define RFC_ULLRAM_BANK11362_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11362_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11363 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11363_DATA_W 32 -#define RFC_ULLRAM_BANK11363_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11363_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11364 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11364_DATA_W 32 -#define RFC_ULLRAM_BANK11364_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11364_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11365 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11365_DATA_W 32 -#define RFC_ULLRAM_BANK11365_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11365_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11366 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11366_DATA_W 32 -#define RFC_ULLRAM_BANK11366_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11366_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11367 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11367_DATA_W 32 -#define RFC_ULLRAM_BANK11367_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11367_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11368 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11368_DATA_W 32 -#define RFC_ULLRAM_BANK11368_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11368_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11369 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11369_DATA_W 32 -#define RFC_ULLRAM_BANK11369_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11369_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11370 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11370_DATA_W 32 -#define RFC_ULLRAM_BANK11370_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11370_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11371 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11371_DATA_W 32 -#define RFC_ULLRAM_BANK11371_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11371_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11372 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11372_DATA_W 32 -#define RFC_ULLRAM_BANK11372_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11372_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11373 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11373_DATA_W 32 -#define RFC_ULLRAM_BANK11373_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11373_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11374 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11374_DATA_W 32 -#define RFC_ULLRAM_BANK11374_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11374_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11375 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11375_DATA_W 32 -#define RFC_ULLRAM_BANK11375_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11375_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11376 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11376_DATA_W 32 -#define RFC_ULLRAM_BANK11376_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11376_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11377 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11377_DATA_W 32 -#define RFC_ULLRAM_BANK11377_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11377_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11378 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11378_DATA_W 32 -#define RFC_ULLRAM_BANK11378_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11378_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11379 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11379_DATA_W 32 -#define RFC_ULLRAM_BANK11379_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11379_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11380 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11380_DATA_W 32 -#define RFC_ULLRAM_BANK11380_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11380_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11381 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11381_DATA_W 32 -#define RFC_ULLRAM_BANK11381_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11381_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11382 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11382_DATA_W 32 -#define RFC_ULLRAM_BANK11382_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11382_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11383 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11383_DATA_W 32 -#define RFC_ULLRAM_BANK11383_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11383_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11384 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11384_DATA_W 32 -#define RFC_ULLRAM_BANK11384_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11384_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11385 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11385_DATA_W 32 -#define RFC_ULLRAM_BANK11385_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11385_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11386 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11386_DATA_W 32 -#define RFC_ULLRAM_BANK11386_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11386_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11387 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11387_DATA_W 32 -#define RFC_ULLRAM_BANK11387_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11387_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11388 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11388_DATA_W 32 -#define RFC_ULLRAM_BANK11388_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11388_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11389 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11389_DATA_W 32 -#define RFC_ULLRAM_BANK11389_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11389_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11390 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11390_DATA_W 32 -#define RFC_ULLRAM_BANK11390_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11390_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11391 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11391_DATA_W 32 -#define RFC_ULLRAM_BANK11391_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11391_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11392 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11392_DATA_W 32 -#define RFC_ULLRAM_BANK11392_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11392_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11393 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11393_DATA_W 32 -#define RFC_ULLRAM_BANK11393_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11393_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11394 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11394_DATA_W 32 -#define RFC_ULLRAM_BANK11394_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11394_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11395 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11395_DATA_W 32 -#define RFC_ULLRAM_BANK11395_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11395_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11396 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11396_DATA_W 32 -#define RFC_ULLRAM_BANK11396_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11396_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11397 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11397_DATA_W 32 -#define RFC_ULLRAM_BANK11397_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11397_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11398 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11398_DATA_W 32 -#define RFC_ULLRAM_BANK11398_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11398_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11399 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11399_DATA_W 32 -#define RFC_ULLRAM_BANK11399_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11399_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11400 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11400_DATA_W 32 -#define RFC_ULLRAM_BANK11400_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11400_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11401 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11401_DATA_W 32 -#define RFC_ULLRAM_BANK11401_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11401_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11402 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11402_DATA_W 32 -#define RFC_ULLRAM_BANK11402_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11402_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11403 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11403_DATA_W 32 -#define RFC_ULLRAM_BANK11403_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11403_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11404 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11404_DATA_W 32 -#define RFC_ULLRAM_BANK11404_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11404_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11405 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11405_DATA_W 32 -#define RFC_ULLRAM_BANK11405_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11405_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11406 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11406_DATA_W 32 -#define RFC_ULLRAM_BANK11406_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11406_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11407 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11407_DATA_W 32 -#define RFC_ULLRAM_BANK11407_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11407_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11408 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11408_DATA_W 32 -#define RFC_ULLRAM_BANK11408_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11408_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11409 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11409_DATA_W 32 -#define RFC_ULLRAM_BANK11409_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11409_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11410 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11410_DATA_W 32 -#define RFC_ULLRAM_BANK11410_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11410_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11411 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11411_DATA_W 32 -#define RFC_ULLRAM_BANK11411_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11411_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11412 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11412_DATA_W 32 -#define RFC_ULLRAM_BANK11412_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11412_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11413 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11413_DATA_W 32 -#define RFC_ULLRAM_BANK11413_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11413_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11414 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11414_DATA_W 32 -#define RFC_ULLRAM_BANK11414_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11414_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11415 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11415_DATA_W 32 -#define RFC_ULLRAM_BANK11415_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11415_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11416 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11416_DATA_W 32 -#define RFC_ULLRAM_BANK11416_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11416_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11417 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11417_DATA_W 32 -#define RFC_ULLRAM_BANK11417_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11417_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11418 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11418_DATA_W 32 -#define RFC_ULLRAM_BANK11418_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11418_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11419 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11419_DATA_W 32 -#define RFC_ULLRAM_BANK11419_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11419_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11420 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11420_DATA_W 32 -#define RFC_ULLRAM_BANK11420_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11420_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11421 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11421_DATA_W 32 -#define RFC_ULLRAM_BANK11421_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11421_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11422 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11422_DATA_W 32 -#define RFC_ULLRAM_BANK11422_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11422_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11423 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11423_DATA_W 32 -#define RFC_ULLRAM_BANK11423_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11423_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11424 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11424_DATA_W 32 -#define RFC_ULLRAM_BANK11424_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11424_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11425 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11425_DATA_W 32 -#define RFC_ULLRAM_BANK11425_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11425_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11426 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11426_DATA_W 32 -#define RFC_ULLRAM_BANK11426_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11426_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11427 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11427_DATA_W 32 -#define RFC_ULLRAM_BANK11427_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11427_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11428 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11428_DATA_W 32 -#define RFC_ULLRAM_BANK11428_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11428_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11429 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11429_DATA_W 32 -#define RFC_ULLRAM_BANK11429_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11429_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11430 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11430_DATA_W 32 -#define RFC_ULLRAM_BANK11430_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11430_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11431 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11431_DATA_W 32 -#define RFC_ULLRAM_BANK11431_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11431_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11432 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11432_DATA_W 32 -#define RFC_ULLRAM_BANK11432_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11432_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11433 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11433_DATA_W 32 -#define RFC_ULLRAM_BANK11433_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11433_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11434 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11434_DATA_W 32 -#define RFC_ULLRAM_BANK11434_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11434_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11435 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11435_DATA_W 32 -#define RFC_ULLRAM_BANK11435_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11435_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11436 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11436_DATA_W 32 -#define RFC_ULLRAM_BANK11436_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11436_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11437 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11437_DATA_W 32 -#define RFC_ULLRAM_BANK11437_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11437_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11438 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11438_DATA_W 32 -#define RFC_ULLRAM_BANK11438_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11438_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11439 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11439_DATA_W 32 -#define RFC_ULLRAM_BANK11439_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11439_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11440 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11440_DATA_W 32 -#define RFC_ULLRAM_BANK11440_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11440_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11441 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11441_DATA_W 32 -#define RFC_ULLRAM_BANK11441_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11441_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11442 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11442_DATA_W 32 -#define RFC_ULLRAM_BANK11442_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11442_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11443 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11443_DATA_W 32 -#define RFC_ULLRAM_BANK11443_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11443_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11444 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11444_DATA_W 32 -#define RFC_ULLRAM_BANK11444_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11444_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11445 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11445_DATA_W 32 -#define RFC_ULLRAM_BANK11445_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11445_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11446 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11446_DATA_W 32 -#define RFC_ULLRAM_BANK11446_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11446_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11447 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11447_DATA_W 32 -#define RFC_ULLRAM_BANK11447_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11447_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11448 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11448_DATA_W 32 -#define RFC_ULLRAM_BANK11448_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11448_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11449 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11449_DATA_W 32 -#define RFC_ULLRAM_BANK11449_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11449_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11450 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11450_DATA_W 32 -#define RFC_ULLRAM_BANK11450_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11450_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11451 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11451_DATA_W 32 -#define RFC_ULLRAM_BANK11451_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11451_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11452 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11452_DATA_W 32 -#define RFC_ULLRAM_BANK11452_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11452_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11453 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11453_DATA_W 32 -#define RFC_ULLRAM_BANK11453_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11453_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11454 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11454_DATA_W 32 -#define RFC_ULLRAM_BANK11454_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11454_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11455 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11455_DATA_W 32 -#define RFC_ULLRAM_BANK11455_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11455_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11456 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11456_DATA_W 32 -#define RFC_ULLRAM_BANK11456_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11456_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11457 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11457_DATA_W 32 -#define RFC_ULLRAM_BANK11457_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11457_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11458 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11458_DATA_W 32 -#define RFC_ULLRAM_BANK11458_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11458_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11459 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11459_DATA_W 32 -#define RFC_ULLRAM_BANK11459_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11459_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11460 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11460_DATA_W 32 -#define RFC_ULLRAM_BANK11460_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11460_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11461 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11461_DATA_W 32 -#define RFC_ULLRAM_BANK11461_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11461_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11462 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11462_DATA_W 32 -#define RFC_ULLRAM_BANK11462_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11462_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11463 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11463_DATA_W 32 -#define RFC_ULLRAM_BANK11463_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11463_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11464 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11464_DATA_W 32 -#define RFC_ULLRAM_BANK11464_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11464_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11465 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11465_DATA_W 32 -#define RFC_ULLRAM_BANK11465_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11465_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11466 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11466_DATA_W 32 -#define RFC_ULLRAM_BANK11466_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11466_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11467 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11467_DATA_W 32 -#define RFC_ULLRAM_BANK11467_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11467_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11468 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11468_DATA_W 32 -#define RFC_ULLRAM_BANK11468_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11468_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11469 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11469_DATA_W 32 -#define RFC_ULLRAM_BANK11469_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11469_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11470 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11470_DATA_W 32 -#define RFC_ULLRAM_BANK11470_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11470_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11471 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11471_DATA_W 32 -#define RFC_ULLRAM_BANK11471_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11471_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11472 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11472_DATA_W 32 -#define RFC_ULLRAM_BANK11472_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11472_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11473 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11473_DATA_W 32 -#define RFC_ULLRAM_BANK11473_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11473_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11474 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11474_DATA_W 32 -#define RFC_ULLRAM_BANK11474_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11474_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11475 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11475_DATA_W 32 -#define RFC_ULLRAM_BANK11475_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11475_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11476 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11476_DATA_W 32 -#define RFC_ULLRAM_BANK11476_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11476_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11477 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11477_DATA_W 32 -#define RFC_ULLRAM_BANK11477_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11477_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11478 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11478_DATA_W 32 -#define RFC_ULLRAM_BANK11478_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11478_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11479 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11479_DATA_W 32 -#define RFC_ULLRAM_BANK11479_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11479_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11480 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11480_DATA_W 32 -#define RFC_ULLRAM_BANK11480_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11480_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11481 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11481_DATA_W 32 -#define RFC_ULLRAM_BANK11481_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11481_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11482 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11482_DATA_W 32 -#define RFC_ULLRAM_BANK11482_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11482_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11483 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11483_DATA_W 32 -#define RFC_ULLRAM_BANK11483_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11483_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11484 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11484_DATA_W 32 -#define RFC_ULLRAM_BANK11484_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11484_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11485 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11485_DATA_W 32 -#define RFC_ULLRAM_BANK11485_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11485_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11486 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11486_DATA_W 32 -#define RFC_ULLRAM_BANK11486_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11486_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11487 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11487_DATA_W 32 -#define RFC_ULLRAM_BANK11487_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11487_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11488 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11488_DATA_W 32 -#define RFC_ULLRAM_BANK11488_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11488_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11489 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11489_DATA_W 32 -#define RFC_ULLRAM_BANK11489_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11489_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11490 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11490_DATA_W 32 -#define RFC_ULLRAM_BANK11490_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11490_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11491 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11491_DATA_W 32 -#define RFC_ULLRAM_BANK11491_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11491_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11492 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11492_DATA_W 32 -#define RFC_ULLRAM_BANK11492_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11492_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11493 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11493_DATA_W 32 -#define RFC_ULLRAM_BANK11493_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11493_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11494 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11494_DATA_W 32 -#define RFC_ULLRAM_BANK11494_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11494_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11495 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11495_DATA_W 32 -#define RFC_ULLRAM_BANK11495_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11495_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11496 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11496_DATA_W 32 -#define RFC_ULLRAM_BANK11496_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11496_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11497 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11497_DATA_W 32 -#define RFC_ULLRAM_BANK11497_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11497_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11498 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11498_DATA_W 32 -#define RFC_ULLRAM_BANK11498_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11498_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11499 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11499_DATA_W 32 -#define RFC_ULLRAM_BANK11499_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11499_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11500 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11500_DATA_W 32 -#define RFC_ULLRAM_BANK11500_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11500_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11501 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11501_DATA_W 32 -#define RFC_ULLRAM_BANK11501_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11501_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11502 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11502_DATA_W 32 -#define RFC_ULLRAM_BANK11502_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11502_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11503 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11503_DATA_W 32 -#define RFC_ULLRAM_BANK11503_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11503_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11504 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11504_DATA_W 32 -#define RFC_ULLRAM_BANK11504_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11504_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11505 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11505_DATA_W 32 -#define RFC_ULLRAM_BANK11505_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11505_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11506 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11506_DATA_W 32 -#define RFC_ULLRAM_BANK11506_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11506_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11507 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11507_DATA_W 32 -#define RFC_ULLRAM_BANK11507_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11507_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11508 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11508_DATA_W 32 -#define RFC_ULLRAM_BANK11508_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11508_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11509 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11509_DATA_W 32 -#define RFC_ULLRAM_BANK11509_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11509_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11510 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11510_DATA_W 32 -#define RFC_ULLRAM_BANK11510_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11510_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11511 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11511_DATA_W 32 -#define RFC_ULLRAM_BANK11511_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11511_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11512 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11512_DATA_W 32 -#define RFC_ULLRAM_BANK11512_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11512_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11513 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11513_DATA_W 32 -#define RFC_ULLRAM_BANK11513_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11513_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11514 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11514_DATA_W 32 -#define RFC_ULLRAM_BANK11514_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11514_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11515 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11515_DATA_W 32 -#define RFC_ULLRAM_BANK11515_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11515_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11516 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11516_DATA_W 32 -#define RFC_ULLRAM_BANK11516_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11516_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11517 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11517_DATA_W 32 -#define RFC_ULLRAM_BANK11517_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11517_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11518 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11518_DATA_W 32 -#define RFC_ULLRAM_BANK11518_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11518_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11519 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11519_DATA_W 32 -#define RFC_ULLRAM_BANK11519_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11519_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11520 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11520_DATA_W 32 -#define RFC_ULLRAM_BANK11520_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11520_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11521 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11521_DATA_W 32 -#define RFC_ULLRAM_BANK11521_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11521_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11522 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11522_DATA_W 32 -#define RFC_ULLRAM_BANK11522_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11522_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11523 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11523_DATA_W 32 -#define RFC_ULLRAM_BANK11523_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11523_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11524 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11524_DATA_W 32 -#define RFC_ULLRAM_BANK11524_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11524_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11525 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11525_DATA_W 32 -#define RFC_ULLRAM_BANK11525_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11525_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11526 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11526_DATA_W 32 -#define RFC_ULLRAM_BANK11526_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11526_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11527 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11527_DATA_W 32 -#define RFC_ULLRAM_BANK11527_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11527_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11528 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11528_DATA_W 32 -#define RFC_ULLRAM_BANK11528_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11528_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11529 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11529_DATA_W 32 -#define RFC_ULLRAM_BANK11529_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11529_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11530 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11530_DATA_W 32 -#define RFC_ULLRAM_BANK11530_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11530_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11531 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11531_DATA_W 32 -#define RFC_ULLRAM_BANK11531_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11531_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11532 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11532_DATA_W 32 -#define RFC_ULLRAM_BANK11532_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11532_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11533 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11533_DATA_W 32 -#define RFC_ULLRAM_BANK11533_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11533_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11534 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11534_DATA_W 32 -#define RFC_ULLRAM_BANK11534_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11534_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11535 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11535_DATA_W 32 -#define RFC_ULLRAM_BANK11535_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11535_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11536 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11536_DATA_W 32 -#define RFC_ULLRAM_BANK11536_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11536_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11537 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11537_DATA_W 32 -#define RFC_ULLRAM_BANK11537_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11537_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11538 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11538_DATA_W 32 -#define RFC_ULLRAM_BANK11538_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11538_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11539 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11539_DATA_W 32 -#define RFC_ULLRAM_BANK11539_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11539_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11540 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11540_DATA_W 32 -#define RFC_ULLRAM_BANK11540_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11540_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11541 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11541_DATA_W 32 -#define RFC_ULLRAM_BANK11541_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11541_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11542 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11542_DATA_W 32 -#define RFC_ULLRAM_BANK11542_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11542_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11543 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11543_DATA_W 32 -#define RFC_ULLRAM_BANK11543_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11543_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11544 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11544_DATA_W 32 -#define RFC_ULLRAM_BANK11544_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11544_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11545 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11545_DATA_W 32 -#define RFC_ULLRAM_BANK11545_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11545_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11546 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11546_DATA_W 32 -#define RFC_ULLRAM_BANK11546_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11546_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11547 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11547_DATA_W 32 -#define RFC_ULLRAM_BANK11547_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11547_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11548 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11548_DATA_W 32 -#define RFC_ULLRAM_BANK11548_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11548_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11549 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11549_DATA_W 32 -#define RFC_ULLRAM_BANK11549_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11549_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11550 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11550_DATA_W 32 -#define RFC_ULLRAM_BANK11550_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11550_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11551 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11551_DATA_W 32 -#define RFC_ULLRAM_BANK11551_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11551_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11552 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11552_DATA_W 32 -#define RFC_ULLRAM_BANK11552_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11552_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11553 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11553_DATA_W 32 -#define RFC_ULLRAM_BANK11553_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11553_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11554 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11554_DATA_W 32 -#define RFC_ULLRAM_BANK11554_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11554_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11555 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11555_DATA_W 32 -#define RFC_ULLRAM_BANK11555_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11555_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11556 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11556_DATA_W 32 -#define RFC_ULLRAM_BANK11556_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11556_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11557 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11557_DATA_W 32 -#define RFC_ULLRAM_BANK11557_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11557_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11558 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11558_DATA_W 32 -#define RFC_ULLRAM_BANK11558_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11558_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11559 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11559_DATA_W 32 -#define RFC_ULLRAM_BANK11559_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11559_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11560 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11560_DATA_W 32 -#define RFC_ULLRAM_BANK11560_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11560_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11561 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11561_DATA_W 32 -#define RFC_ULLRAM_BANK11561_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11561_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11562 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11562_DATA_W 32 -#define RFC_ULLRAM_BANK11562_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11562_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11563 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11563_DATA_W 32 -#define RFC_ULLRAM_BANK11563_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11563_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11564 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11564_DATA_W 32 -#define RFC_ULLRAM_BANK11564_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11564_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11565 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11565_DATA_W 32 -#define RFC_ULLRAM_BANK11565_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11565_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11566 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11566_DATA_W 32 -#define RFC_ULLRAM_BANK11566_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11566_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11567 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11567_DATA_W 32 -#define RFC_ULLRAM_BANK11567_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11567_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11568 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11568_DATA_W 32 -#define RFC_ULLRAM_BANK11568_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11568_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11569 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11569_DATA_W 32 -#define RFC_ULLRAM_BANK11569_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11569_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11570 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11570_DATA_W 32 -#define RFC_ULLRAM_BANK11570_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11570_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11571 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11571_DATA_W 32 -#define RFC_ULLRAM_BANK11571_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11571_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11572 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11572_DATA_W 32 -#define RFC_ULLRAM_BANK11572_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11572_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11573 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11573_DATA_W 32 -#define RFC_ULLRAM_BANK11573_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11573_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11574 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11574_DATA_W 32 -#define RFC_ULLRAM_BANK11574_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11574_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11575 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11575_DATA_W 32 -#define RFC_ULLRAM_BANK11575_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11575_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11576 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11576_DATA_W 32 -#define RFC_ULLRAM_BANK11576_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11576_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11577 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11577_DATA_W 32 -#define RFC_ULLRAM_BANK11577_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11577_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11578 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11578_DATA_W 32 -#define RFC_ULLRAM_BANK11578_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11578_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11579 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11579_DATA_W 32 -#define RFC_ULLRAM_BANK11579_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11579_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11580 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11580_DATA_W 32 -#define RFC_ULLRAM_BANK11580_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11580_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11581 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11581_DATA_W 32 -#define RFC_ULLRAM_BANK11581_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11581_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11582 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11582_DATA_W 32 -#define RFC_ULLRAM_BANK11582_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11582_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11583 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11583_DATA_W 32 -#define RFC_ULLRAM_BANK11583_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11583_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11584 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11584_DATA_W 32 -#define RFC_ULLRAM_BANK11584_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11584_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11585 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11585_DATA_W 32 -#define RFC_ULLRAM_BANK11585_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11585_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11586 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11586_DATA_W 32 -#define RFC_ULLRAM_BANK11586_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11586_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11587 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11587_DATA_W 32 -#define RFC_ULLRAM_BANK11587_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11587_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11588 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11588_DATA_W 32 -#define RFC_ULLRAM_BANK11588_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11588_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11589 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11589_DATA_W 32 -#define RFC_ULLRAM_BANK11589_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11589_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11590 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11590_DATA_W 32 -#define RFC_ULLRAM_BANK11590_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11590_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11591 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11591_DATA_W 32 -#define RFC_ULLRAM_BANK11591_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11591_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11592 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11592_DATA_W 32 -#define RFC_ULLRAM_BANK11592_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11592_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11593 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11593_DATA_W 32 -#define RFC_ULLRAM_BANK11593_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11593_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11594 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11594_DATA_W 32 -#define RFC_ULLRAM_BANK11594_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11594_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11595 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11595_DATA_W 32 -#define RFC_ULLRAM_BANK11595_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11595_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11596 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11596_DATA_W 32 -#define RFC_ULLRAM_BANK11596_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11596_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11597 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11597_DATA_W 32 -#define RFC_ULLRAM_BANK11597_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11597_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11598 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11598_DATA_W 32 -#define RFC_ULLRAM_BANK11598_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11598_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11599 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11599_DATA_W 32 -#define RFC_ULLRAM_BANK11599_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11599_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11600 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11600_DATA_W 32 -#define RFC_ULLRAM_BANK11600_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11600_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11601 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11601_DATA_W 32 -#define RFC_ULLRAM_BANK11601_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11601_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11602 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11602_DATA_W 32 -#define RFC_ULLRAM_BANK11602_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11602_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11603 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11603_DATA_W 32 -#define RFC_ULLRAM_BANK11603_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11603_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11604 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11604_DATA_W 32 -#define RFC_ULLRAM_BANK11604_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11604_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11605 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11605_DATA_W 32 -#define RFC_ULLRAM_BANK11605_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11605_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11606 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11606_DATA_W 32 -#define RFC_ULLRAM_BANK11606_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11606_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11607 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11607_DATA_W 32 -#define RFC_ULLRAM_BANK11607_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11607_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11608 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11608_DATA_W 32 -#define RFC_ULLRAM_BANK11608_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11608_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11609 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11609_DATA_W 32 -#define RFC_ULLRAM_BANK11609_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11609_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11610 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11610_DATA_W 32 -#define RFC_ULLRAM_BANK11610_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11610_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11611 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11611_DATA_W 32 -#define RFC_ULLRAM_BANK11611_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11611_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11612 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11612_DATA_W 32 -#define RFC_ULLRAM_BANK11612_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11612_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11613 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11613_DATA_W 32 -#define RFC_ULLRAM_BANK11613_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11613_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11614 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11614_DATA_W 32 -#define RFC_ULLRAM_BANK11614_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11614_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11615 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11615_DATA_W 32 -#define RFC_ULLRAM_BANK11615_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11615_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11616 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11616_DATA_W 32 -#define RFC_ULLRAM_BANK11616_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11616_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11617 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11617_DATA_W 32 -#define RFC_ULLRAM_BANK11617_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11617_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11618 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11618_DATA_W 32 -#define RFC_ULLRAM_BANK11618_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11618_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11619 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11619_DATA_W 32 -#define RFC_ULLRAM_BANK11619_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11619_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11620 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11620_DATA_W 32 -#define RFC_ULLRAM_BANK11620_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11620_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11621 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11621_DATA_W 32 -#define RFC_ULLRAM_BANK11621_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11621_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11622 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11622_DATA_W 32 -#define RFC_ULLRAM_BANK11622_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11622_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11623 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11623_DATA_W 32 -#define RFC_ULLRAM_BANK11623_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11623_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11624 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11624_DATA_W 32 -#define RFC_ULLRAM_BANK11624_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11624_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11625 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11625_DATA_W 32 -#define RFC_ULLRAM_BANK11625_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11625_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11626 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11626_DATA_W 32 -#define RFC_ULLRAM_BANK11626_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11626_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11627 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11627_DATA_W 32 -#define RFC_ULLRAM_BANK11627_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11627_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11628 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11628_DATA_W 32 -#define RFC_ULLRAM_BANK11628_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11628_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11629 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11629_DATA_W 32 -#define RFC_ULLRAM_BANK11629_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11629_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11630 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11630_DATA_W 32 -#define RFC_ULLRAM_BANK11630_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11630_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11631 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11631_DATA_W 32 -#define RFC_ULLRAM_BANK11631_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11631_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11632 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11632_DATA_W 32 -#define RFC_ULLRAM_BANK11632_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11632_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11633 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11633_DATA_W 32 -#define RFC_ULLRAM_BANK11633_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11633_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11634 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11634_DATA_W 32 -#define RFC_ULLRAM_BANK11634_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11634_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11635 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11635_DATA_W 32 -#define RFC_ULLRAM_BANK11635_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11635_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11636 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11636_DATA_W 32 -#define RFC_ULLRAM_BANK11636_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11636_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11637 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11637_DATA_W 32 -#define RFC_ULLRAM_BANK11637_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11637_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11638 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11638_DATA_W 32 -#define RFC_ULLRAM_BANK11638_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11638_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11639 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11639_DATA_W 32 -#define RFC_ULLRAM_BANK11639_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11639_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11640 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11640_DATA_W 32 -#define RFC_ULLRAM_BANK11640_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11640_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11641 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11641_DATA_W 32 -#define RFC_ULLRAM_BANK11641_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11641_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11642 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11642_DATA_W 32 -#define RFC_ULLRAM_BANK11642_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11642_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11643 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11643_DATA_W 32 -#define RFC_ULLRAM_BANK11643_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11643_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11644 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11644_DATA_W 32 -#define RFC_ULLRAM_BANK11644_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11644_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11645 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11645_DATA_W 32 -#define RFC_ULLRAM_BANK11645_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11645_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11646 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11646_DATA_W 32 -#define RFC_ULLRAM_BANK11646_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11646_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11647 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11647_DATA_W 32 -#define RFC_ULLRAM_BANK11647_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11647_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11648 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11648_DATA_W 32 -#define RFC_ULLRAM_BANK11648_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11648_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11649 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11649_DATA_W 32 -#define RFC_ULLRAM_BANK11649_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11649_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11650 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11650_DATA_W 32 -#define RFC_ULLRAM_BANK11650_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11650_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11651 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11651_DATA_W 32 -#define RFC_ULLRAM_BANK11651_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11651_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11652 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11652_DATA_W 32 -#define RFC_ULLRAM_BANK11652_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11652_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11653 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11653_DATA_W 32 -#define RFC_ULLRAM_BANK11653_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11653_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11654 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11654_DATA_W 32 -#define RFC_ULLRAM_BANK11654_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11654_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11655 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11655_DATA_W 32 -#define RFC_ULLRAM_BANK11655_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11655_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11656 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11656_DATA_W 32 -#define RFC_ULLRAM_BANK11656_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11656_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11657 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11657_DATA_W 32 -#define RFC_ULLRAM_BANK11657_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11657_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11658 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11658_DATA_W 32 -#define RFC_ULLRAM_BANK11658_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11658_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11659 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11659_DATA_W 32 -#define RFC_ULLRAM_BANK11659_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11659_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11660 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11660_DATA_W 32 -#define RFC_ULLRAM_BANK11660_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11660_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11661 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11661_DATA_W 32 -#define RFC_ULLRAM_BANK11661_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11661_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11662 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11662_DATA_W 32 -#define RFC_ULLRAM_BANK11662_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11662_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11663 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11663_DATA_W 32 -#define RFC_ULLRAM_BANK11663_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11663_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11664 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11664_DATA_W 32 -#define RFC_ULLRAM_BANK11664_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11664_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11665 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11665_DATA_W 32 -#define RFC_ULLRAM_BANK11665_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11665_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11666 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11666_DATA_W 32 -#define RFC_ULLRAM_BANK11666_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11666_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11667 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11667_DATA_W 32 -#define RFC_ULLRAM_BANK11667_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11667_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11668 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11668_DATA_W 32 -#define RFC_ULLRAM_BANK11668_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11668_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11669 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11669_DATA_W 32 -#define RFC_ULLRAM_BANK11669_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11669_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11670 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11670_DATA_W 32 -#define RFC_ULLRAM_BANK11670_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11670_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11671 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11671_DATA_W 32 -#define RFC_ULLRAM_BANK11671_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11671_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11672 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11672_DATA_W 32 -#define RFC_ULLRAM_BANK11672_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11672_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11673 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11673_DATA_W 32 -#define RFC_ULLRAM_BANK11673_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11673_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11674 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11674_DATA_W 32 -#define RFC_ULLRAM_BANK11674_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11674_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11675 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11675_DATA_W 32 -#define RFC_ULLRAM_BANK11675_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11675_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11676 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11676_DATA_W 32 -#define RFC_ULLRAM_BANK11676_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11676_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11677 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11677_DATA_W 32 -#define RFC_ULLRAM_BANK11677_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11677_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11678 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11678_DATA_W 32 -#define RFC_ULLRAM_BANK11678_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11678_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11679 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11679_DATA_W 32 -#define RFC_ULLRAM_BANK11679_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11679_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11680 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11680_DATA_W 32 -#define RFC_ULLRAM_BANK11680_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11680_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11681 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11681_DATA_W 32 -#define RFC_ULLRAM_BANK11681_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11681_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11682 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11682_DATA_W 32 -#define RFC_ULLRAM_BANK11682_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11682_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11683 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11683_DATA_W 32 -#define RFC_ULLRAM_BANK11683_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11683_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11684 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11684_DATA_W 32 -#define RFC_ULLRAM_BANK11684_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11684_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11685 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11685_DATA_W 32 -#define RFC_ULLRAM_BANK11685_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11685_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11686 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11686_DATA_W 32 -#define RFC_ULLRAM_BANK11686_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11686_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11687 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11687_DATA_W 32 -#define RFC_ULLRAM_BANK11687_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11687_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11688 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11688_DATA_W 32 -#define RFC_ULLRAM_BANK11688_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11688_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11689 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11689_DATA_W 32 -#define RFC_ULLRAM_BANK11689_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11689_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11690 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11690_DATA_W 32 -#define RFC_ULLRAM_BANK11690_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11690_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11691 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11691_DATA_W 32 -#define RFC_ULLRAM_BANK11691_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11691_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11692 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11692_DATA_W 32 -#define RFC_ULLRAM_BANK11692_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11692_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11693 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11693_DATA_W 32 -#define RFC_ULLRAM_BANK11693_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11693_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11694 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11694_DATA_W 32 -#define RFC_ULLRAM_BANK11694_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11694_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11695 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11695_DATA_W 32 -#define RFC_ULLRAM_BANK11695_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11695_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11696 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11696_DATA_W 32 -#define RFC_ULLRAM_BANK11696_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11696_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11697 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11697_DATA_W 32 -#define RFC_ULLRAM_BANK11697_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11697_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11698 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11698_DATA_W 32 -#define RFC_ULLRAM_BANK11698_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11698_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11699 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11699_DATA_W 32 -#define RFC_ULLRAM_BANK11699_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11699_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11700 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11700_DATA_W 32 -#define RFC_ULLRAM_BANK11700_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11700_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11701 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11701_DATA_W 32 -#define RFC_ULLRAM_BANK11701_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11701_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11702 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11702_DATA_W 32 -#define RFC_ULLRAM_BANK11702_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11702_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11703 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11703_DATA_W 32 -#define RFC_ULLRAM_BANK11703_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11703_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11704 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11704_DATA_W 32 -#define RFC_ULLRAM_BANK11704_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11704_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11705 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11705_DATA_W 32 -#define RFC_ULLRAM_BANK11705_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11705_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11706 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11706_DATA_W 32 -#define RFC_ULLRAM_BANK11706_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11706_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11707 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11707_DATA_W 32 -#define RFC_ULLRAM_BANK11707_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11707_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11708 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11708_DATA_W 32 -#define RFC_ULLRAM_BANK11708_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11708_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11709 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11709_DATA_W 32 -#define RFC_ULLRAM_BANK11709_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11709_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11710 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11710_DATA_W 32 -#define RFC_ULLRAM_BANK11710_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11710_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11711 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11711_DATA_W 32 -#define RFC_ULLRAM_BANK11711_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11711_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11712 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11712_DATA_W 32 -#define RFC_ULLRAM_BANK11712_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11712_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11713 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11713_DATA_W 32 -#define RFC_ULLRAM_BANK11713_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11713_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11714 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11714_DATA_W 32 -#define RFC_ULLRAM_BANK11714_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11714_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11715 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11715_DATA_W 32 -#define RFC_ULLRAM_BANK11715_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11715_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11716 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11716_DATA_W 32 -#define RFC_ULLRAM_BANK11716_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11716_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11717 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11717_DATA_W 32 -#define RFC_ULLRAM_BANK11717_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11717_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11718 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11718_DATA_W 32 -#define RFC_ULLRAM_BANK11718_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11718_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11719 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11719_DATA_W 32 -#define RFC_ULLRAM_BANK11719_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11719_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11720 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11720_DATA_W 32 -#define RFC_ULLRAM_BANK11720_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11720_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11721 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11721_DATA_W 32 -#define RFC_ULLRAM_BANK11721_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11721_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11722 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11722_DATA_W 32 -#define RFC_ULLRAM_BANK11722_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11722_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11723 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11723_DATA_W 32 -#define RFC_ULLRAM_BANK11723_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11723_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11724 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11724_DATA_W 32 -#define RFC_ULLRAM_BANK11724_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11724_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11725 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11725_DATA_W 32 -#define RFC_ULLRAM_BANK11725_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11725_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11726 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11726_DATA_W 32 -#define RFC_ULLRAM_BANK11726_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11726_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11727 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11727_DATA_W 32 -#define RFC_ULLRAM_BANK11727_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11727_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11728 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11728_DATA_W 32 -#define RFC_ULLRAM_BANK11728_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11728_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11729 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11729_DATA_W 32 -#define RFC_ULLRAM_BANK11729_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11729_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11730 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11730_DATA_W 32 -#define RFC_ULLRAM_BANK11730_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11730_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11731 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11731_DATA_W 32 -#define RFC_ULLRAM_BANK11731_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11731_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11732 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11732_DATA_W 32 -#define RFC_ULLRAM_BANK11732_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11732_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11733 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11733_DATA_W 32 -#define RFC_ULLRAM_BANK11733_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11733_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11734 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11734_DATA_W 32 -#define RFC_ULLRAM_BANK11734_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11734_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11735 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11735_DATA_W 32 -#define RFC_ULLRAM_BANK11735_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11735_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11736 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11736_DATA_W 32 -#define RFC_ULLRAM_BANK11736_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11736_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11737 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11737_DATA_W 32 -#define RFC_ULLRAM_BANK11737_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11737_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11738 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11738_DATA_W 32 -#define RFC_ULLRAM_BANK11738_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11738_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11739 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11739_DATA_W 32 -#define RFC_ULLRAM_BANK11739_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11739_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11740 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11740_DATA_W 32 -#define RFC_ULLRAM_BANK11740_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11740_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11741 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11741_DATA_W 32 -#define RFC_ULLRAM_BANK11741_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11741_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11742 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11742_DATA_W 32 -#define RFC_ULLRAM_BANK11742_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11742_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11743 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11743_DATA_W 32 -#define RFC_ULLRAM_BANK11743_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11743_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11744 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11744_DATA_W 32 -#define RFC_ULLRAM_BANK11744_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11744_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11745 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11745_DATA_W 32 -#define RFC_ULLRAM_BANK11745_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11745_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11746 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11746_DATA_W 32 -#define RFC_ULLRAM_BANK11746_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11746_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11747 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11747_DATA_W 32 -#define RFC_ULLRAM_BANK11747_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11747_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11748 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11748_DATA_W 32 -#define RFC_ULLRAM_BANK11748_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11748_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11749 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11749_DATA_W 32 -#define RFC_ULLRAM_BANK11749_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11749_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11750 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11750_DATA_W 32 -#define RFC_ULLRAM_BANK11750_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11750_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11751 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11751_DATA_W 32 -#define RFC_ULLRAM_BANK11751_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11751_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11752 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11752_DATA_W 32 -#define RFC_ULLRAM_BANK11752_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11752_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11753 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11753_DATA_W 32 -#define RFC_ULLRAM_BANK11753_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11753_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11754 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11754_DATA_W 32 -#define RFC_ULLRAM_BANK11754_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11754_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11755 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11755_DATA_W 32 -#define RFC_ULLRAM_BANK11755_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11755_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11756 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11756_DATA_W 32 -#define RFC_ULLRAM_BANK11756_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11756_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11757 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11757_DATA_W 32 -#define RFC_ULLRAM_BANK11757_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11757_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11758 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11758_DATA_W 32 -#define RFC_ULLRAM_BANK11758_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11758_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11759 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11759_DATA_W 32 -#define RFC_ULLRAM_BANK11759_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11759_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11760 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11760_DATA_W 32 -#define RFC_ULLRAM_BANK11760_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11760_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11761 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11761_DATA_W 32 -#define RFC_ULLRAM_BANK11761_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11761_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11762 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11762_DATA_W 32 -#define RFC_ULLRAM_BANK11762_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11762_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11763 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11763_DATA_W 32 -#define RFC_ULLRAM_BANK11763_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11763_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11764 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11764_DATA_W 32 -#define RFC_ULLRAM_BANK11764_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11764_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11765 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11765_DATA_W 32 -#define RFC_ULLRAM_BANK11765_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11765_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11766 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11766_DATA_W 32 -#define RFC_ULLRAM_BANK11766_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11766_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11767 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11767_DATA_W 32 -#define RFC_ULLRAM_BANK11767_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11767_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11768 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11768_DATA_W 32 -#define RFC_ULLRAM_BANK11768_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11768_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11769 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11769_DATA_W 32 -#define RFC_ULLRAM_BANK11769_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11769_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11770 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11770_DATA_W 32 -#define RFC_ULLRAM_BANK11770_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11770_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11771 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11771_DATA_W 32 -#define RFC_ULLRAM_BANK11771_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11771_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11772 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11772_DATA_W 32 -#define RFC_ULLRAM_BANK11772_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11772_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11773 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11773_DATA_W 32 -#define RFC_ULLRAM_BANK11773_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11773_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11774 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11774_DATA_W 32 -#define RFC_ULLRAM_BANK11774_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11774_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11775 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11775_DATA_W 32 -#define RFC_ULLRAM_BANK11775_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11775_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11776 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11776_DATA_W 32 -#define RFC_ULLRAM_BANK11776_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11776_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11777 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11777_DATA_W 32 -#define RFC_ULLRAM_BANK11777_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11777_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11778 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11778_DATA_W 32 -#define RFC_ULLRAM_BANK11778_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11778_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11779 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11779_DATA_W 32 -#define RFC_ULLRAM_BANK11779_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11779_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11780 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11780_DATA_W 32 -#define RFC_ULLRAM_BANK11780_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11780_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11781 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11781_DATA_W 32 -#define RFC_ULLRAM_BANK11781_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11781_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11782 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11782_DATA_W 32 -#define RFC_ULLRAM_BANK11782_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11782_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11783 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11783_DATA_W 32 -#define RFC_ULLRAM_BANK11783_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11783_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11784 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11784_DATA_W 32 -#define RFC_ULLRAM_BANK11784_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11784_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11785 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11785_DATA_W 32 -#define RFC_ULLRAM_BANK11785_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11785_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11786 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11786_DATA_W 32 -#define RFC_ULLRAM_BANK11786_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11786_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11787 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11787_DATA_W 32 -#define RFC_ULLRAM_BANK11787_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11787_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11788 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11788_DATA_W 32 -#define RFC_ULLRAM_BANK11788_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11788_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11789 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11789_DATA_W 32 -#define RFC_ULLRAM_BANK11789_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11789_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11790 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11790_DATA_W 32 -#define RFC_ULLRAM_BANK11790_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11790_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11791 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11791_DATA_W 32 -#define RFC_ULLRAM_BANK11791_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11791_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11792 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11792_DATA_W 32 -#define RFC_ULLRAM_BANK11792_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11792_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11793 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11793_DATA_W 32 -#define RFC_ULLRAM_BANK11793_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11793_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11794 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11794_DATA_W 32 -#define RFC_ULLRAM_BANK11794_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11794_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11795 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11795_DATA_W 32 -#define RFC_ULLRAM_BANK11795_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11795_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11796 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11796_DATA_W 32 -#define RFC_ULLRAM_BANK11796_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11796_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11797 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11797_DATA_W 32 -#define RFC_ULLRAM_BANK11797_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11797_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11798 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11798_DATA_W 32 -#define RFC_ULLRAM_BANK11798_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11798_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11799 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11799_DATA_W 32 -#define RFC_ULLRAM_BANK11799_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11799_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11800 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11800_DATA_W 32 -#define RFC_ULLRAM_BANK11800_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11800_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11801 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11801_DATA_W 32 -#define RFC_ULLRAM_BANK11801_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11801_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11802 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11802_DATA_W 32 -#define RFC_ULLRAM_BANK11802_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11802_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11803 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11803_DATA_W 32 -#define RFC_ULLRAM_BANK11803_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11803_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11804 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11804_DATA_W 32 -#define RFC_ULLRAM_BANK11804_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11804_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11805 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11805_DATA_W 32 -#define RFC_ULLRAM_BANK11805_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11805_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11806 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11806_DATA_W 32 -#define RFC_ULLRAM_BANK11806_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11806_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11807 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11807_DATA_W 32 -#define RFC_ULLRAM_BANK11807_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11807_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11808 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11808_DATA_W 32 -#define RFC_ULLRAM_BANK11808_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11808_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11809 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11809_DATA_W 32 -#define RFC_ULLRAM_BANK11809_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11809_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11810 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11810_DATA_W 32 -#define RFC_ULLRAM_BANK11810_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11810_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11811 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11811_DATA_W 32 -#define RFC_ULLRAM_BANK11811_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11811_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11812 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11812_DATA_W 32 -#define RFC_ULLRAM_BANK11812_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11812_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11813 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11813_DATA_W 32 -#define RFC_ULLRAM_BANK11813_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11813_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11814 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11814_DATA_W 32 -#define RFC_ULLRAM_BANK11814_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11814_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11815 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11815_DATA_W 32 -#define RFC_ULLRAM_BANK11815_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11815_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11816 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11816_DATA_W 32 -#define RFC_ULLRAM_BANK11816_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11816_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11817 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11817_DATA_W 32 -#define RFC_ULLRAM_BANK11817_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11817_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11818 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11818_DATA_W 32 -#define RFC_ULLRAM_BANK11818_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11818_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11819 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11819_DATA_W 32 -#define RFC_ULLRAM_BANK11819_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11819_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11820 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11820_DATA_W 32 -#define RFC_ULLRAM_BANK11820_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11820_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11821 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11821_DATA_W 32 -#define RFC_ULLRAM_BANK11821_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11821_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11822 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11822_DATA_W 32 -#define RFC_ULLRAM_BANK11822_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11822_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11823 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11823_DATA_W 32 -#define RFC_ULLRAM_BANK11823_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11823_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11824 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11824_DATA_W 32 -#define RFC_ULLRAM_BANK11824_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11824_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11825 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11825_DATA_W 32 -#define RFC_ULLRAM_BANK11825_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11825_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11826 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11826_DATA_W 32 -#define RFC_ULLRAM_BANK11826_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11826_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11827 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11827_DATA_W 32 -#define RFC_ULLRAM_BANK11827_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11827_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11828 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11828_DATA_W 32 -#define RFC_ULLRAM_BANK11828_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11828_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11829 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11829_DATA_W 32 -#define RFC_ULLRAM_BANK11829_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11829_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11830 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11830_DATA_W 32 -#define RFC_ULLRAM_BANK11830_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11830_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11831 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11831_DATA_W 32 -#define RFC_ULLRAM_BANK11831_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11831_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11832 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11832_DATA_W 32 -#define RFC_ULLRAM_BANK11832_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11832_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11833 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11833_DATA_W 32 -#define RFC_ULLRAM_BANK11833_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11833_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11834 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11834_DATA_W 32 -#define RFC_ULLRAM_BANK11834_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11834_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11835 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11835_DATA_W 32 -#define RFC_ULLRAM_BANK11835_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11835_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11836 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11836_DATA_W 32 -#define RFC_ULLRAM_BANK11836_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11836_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11837 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11837_DATA_W 32 -#define RFC_ULLRAM_BANK11837_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11837_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11838 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11838_DATA_W 32 -#define RFC_ULLRAM_BANK11838_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11838_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11839 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11839_DATA_W 32 -#define RFC_ULLRAM_BANK11839_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11839_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11840 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11840_DATA_W 32 -#define RFC_ULLRAM_BANK11840_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11840_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11841 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11841_DATA_W 32 -#define RFC_ULLRAM_BANK11841_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11841_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11842 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11842_DATA_W 32 -#define RFC_ULLRAM_BANK11842_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11842_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11843 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11843_DATA_W 32 -#define RFC_ULLRAM_BANK11843_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11843_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11844 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11844_DATA_W 32 -#define RFC_ULLRAM_BANK11844_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11844_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11845 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11845_DATA_W 32 -#define RFC_ULLRAM_BANK11845_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11845_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11846 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11846_DATA_W 32 -#define RFC_ULLRAM_BANK11846_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11846_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11847 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11847_DATA_W 32 -#define RFC_ULLRAM_BANK11847_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11847_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11848 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11848_DATA_W 32 -#define RFC_ULLRAM_BANK11848_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11848_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11849 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11849_DATA_W 32 -#define RFC_ULLRAM_BANK11849_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11849_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11850 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11850_DATA_W 32 -#define RFC_ULLRAM_BANK11850_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11850_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11851 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11851_DATA_W 32 -#define RFC_ULLRAM_BANK11851_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11851_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11852 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11852_DATA_W 32 -#define RFC_ULLRAM_BANK11852_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11852_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11853 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11853_DATA_W 32 -#define RFC_ULLRAM_BANK11853_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11853_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11854 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11854_DATA_W 32 -#define RFC_ULLRAM_BANK11854_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11854_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11855 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11855_DATA_W 32 -#define RFC_ULLRAM_BANK11855_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11855_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11856 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11856_DATA_W 32 -#define RFC_ULLRAM_BANK11856_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11856_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11857 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11857_DATA_W 32 -#define RFC_ULLRAM_BANK11857_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11857_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11858 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11858_DATA_W 32 -#define RFC_ULLRAM_BANK11858_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11858_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11859 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11859_DATA_W 32 -#define RFC_ULLRAM_BANK11859_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11859_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11860 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11860_DATA_W 32 -#define RFC_ULLRAM_BANK11860_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11860_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11861 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11861_DATA_W 32 -#define RFC_ULLRAM_BANK11861_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11861_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11862 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11862_DATA_W 32 -#define RFC_ULLRAM_BANK11862_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11862_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11863 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11863_DATA_W 32 -#define RFC_ULLRAM_BANK11863_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11863_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11864 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11864_DATA_W 32 -#define RFC_ULLRAM_BANK11864_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11864_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11865 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11865_DATA_W 32 -#define RFC_ULLRAM_BANK11865_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11865_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11866 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11866_DATA_W 32 -#define RFC_ULLRAM_BANK11866_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11866_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11867 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11867_DATA_W 32 -#define RFC_ULLRAM_BANK11867_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11867_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11868 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11868_DATA_W 32 -#define RFC_ULLRAM_BANK11868_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11868_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11869 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11869_DATA_W 32 -#define RFC_ULLRAM_BANK11869_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11869_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11870 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11870_DATA_W 32 -#define RFC_ULLRAM_BANK11870_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11870_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11871 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11871_DATA_W 32 -#define RFC_ULLRAM_BANK11871_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11871_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11872 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11872_DATA_W 32 -#define RFC_ULLRAM_BANK11872_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11872_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11873 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11873_DATA_W 32 -#define RFC_ULLRAM_BANK11873_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11873_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11874 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11874_DATA_W 32 -#define RFC_ULLRAM_BANK11874_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11874_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11875 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11875_DATA_W 32 -#define RFC_ULLRAM_BANK11875_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11875_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11876 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11876_DATA_W 32 -#define RFC_ULLRAM_BANK11876_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11876_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11877 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11877_DATA_W 32 -#define RFC_ULLRAM_BANK11877_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11877_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11878 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11878_DATA_W 32 -#define RFC_ULLRAM_BANK11878_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11878_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11879 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11879_DATA_W 32 -#define RFC_ULLRAM_BANK11879_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11879_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11880 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11880_DATA_W 32 -#define RFC_ULLRAM_BANK11880_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11880_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11881 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11881_DATA_W 32 -#define RFC_ULLRAM_BANK11881_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11881_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11882 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11882_DATA_W 32 -#define RFC_ULLRAM_BANK11882_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11882_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11883 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11883_DATA_W 32 -#define RFC_ULLRAM_BANK11883_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11883_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11884 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11884_DATA_W 32 -#define RFC_ULLRAM_BANK11884_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11884_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11885 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11885_DATA_W 32 -#define RFC_ULLRAM_BANK11885_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11885_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11886 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11886_DATA_W 32 -#define RFC_ULLRAM_BANK11886_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11886_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11887 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11887_DATA_W 32 -#define RFC_ULLRAM_BANK11887_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11887_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11888 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11888_DATA_W 32 -#define RFC_ULLRAM_BANK11888_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11888_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11889 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11889_DATA_W 32 -#define RFC_ULLRAM_BANK11889_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11889_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11890 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11890_DATA_W 32 -#define RFC_ULLRAM_BANK11890_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11890_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11891 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11891_DATA_W 32 -#define RFC_ULLRAM_BANK11891_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11891_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11892 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11892_DATA_W 32 -#define RFC_ULLRAM_BANK11892_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11892_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11893 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11893_DATA_W 32 -#define RFC_ULLRAM_BANK11893_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11893_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11894 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11894_DATA_W 32 -#define RFC_ULLRAM_BANK11894_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11894_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11895 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11895_DATA_W 32 -#define RFC_ULLRAM_BANK11895_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11895_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11896 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11896_DATA_W 32 -#define RFC_ULLRAM_BANK11896_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11896_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11897 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11897_DATA_W 32 -#define RFC_ULLRAM_BANK11897_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11897_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11898 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11898_DATA_W 32 -#define RFC_ULLRAM_BANK11898_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11898_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11899 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11899_DATA_W 32 -#define RFC_ULLRAM_BANK11899_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11899_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11900 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11900_DATA_W 32 -#define RFC_ULLRAM_BANK11900_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11900_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11901 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11901_DATA_W 32 -#define RFC_ULLRAM_BANK11901_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11901_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11902 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11902_DATA_W 32 -#define RFC_ULLRAM_BANK11902_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11902_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11903 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11903_DATA_W 32 -#define RFC_ULLRAM_BANK11903_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11903_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11904 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11904_DATA_W 32 -#define RFC_ULLRAM_BANK11904_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11904_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11905 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11905_DATA_W 32 -#define RFC_ULLRAM_BANK11905_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11905_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11906 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11906_DATA_W 32 -#define RFC_ULLRAM_BANK11906_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11906_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11907 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11907_DATA_W 32 -#define RFC_ULLRAM_BANK11907_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11907_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11908 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11908_DATA_W 32 -#define RFC_ULLRAM_BANK11908_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11908_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11909 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11909_DATA_W 32 -#define RFC_ULLRAM_BANK11909_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11909_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11910 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11910_DATA_W 32 -#define RFC_ULLRAM_BANK11910_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11910_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11911 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11911_DATA_W 32 -#define RFC_ULLRAM_BANK11911_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11911_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11912 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11912_DATA_W 32 -#define RFC_ULLRAM_BANK11912_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11912_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11913 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11913_DATA_W 32 -#define RFC_ULLRAM_BANK11913_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11913_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11914 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11914_DATA_W 32 -#define RFC_ULLRAM_BANK11914_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11914_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11915 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11915_DATA_W 32 -#define RFC_ULLRAM_BANK11915_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11915_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11916 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11916_DATA_W 32 -#define RFC_ULLRAM_BANK11916_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11916_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11917 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11917_DATA_W 32 -#define RFC_ULLRAM_BANK11917_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11917_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11918 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11918_DATA_W 32 -#define RFC_ULLRAM_BANK11918_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11918_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11919 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11919_DATA_W 32 -#define RFC_ULLRAM_BANK11919_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11919_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11920 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11920_DATA_W 32 -#define RFC_ULLRAM_BANK11920_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11920_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11921 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11921_DATA_W 32 -#define RFC_ULLRAM_BANK11921_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11921_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11922 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11922_DATA_W 32 -#define RFC_ULLRAM_BANK11922_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11922_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11923 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11923_DATA_W 32 -#define RFC_ULLRAM_BANK11923_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11923_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11924 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11924_DATA_W 32 -#define RFC_ULLRAM_BANK11924_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11924_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11925 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11925_DATA_W 32 -#define RFC_ULLRAM_BANK11925_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11925_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11926 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11926_DATA_W 32 -#define RFC_ULLRAM_BANK11926_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11926_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11927 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11927_DATA_W 32 -#define RFC_ULLRAM_BANK11927_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11927_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11928 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11928_DATA_W 32 -#define RFC_ULLRAM_BANK11928_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11928_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11929 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11929_DATA_W 32 -#define RFC_ULLRAM_BANK11929_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11929_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11930 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11930_DATA_W 32 -#define RFC_ULLRAM_BANK11930_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11930_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11931 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11931_DATA_W 32 -#define RFC_ULLRAM_BANK11931_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11931_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11932 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11932_DATA_W 32 -#define RFC_ULLRAM_BANK11932_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11932_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11933 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11933_DATA_W 32 -#define RFC_ULLRAM_BANK11933_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11933_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11934 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11934_DATA_W 32 -#define RFC_ULLRAM_BANK11934_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11934_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11935 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11935_DATA_W 32 -#define RFC_ULLRAM_BANK11935_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11935_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11936 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11936_DATA_W 32 -#define RFC_ULLRAM_BANK11936_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11936_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11937 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11937_DATA_W 32 -#define RFC_ULLRAM_BANK11937_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11937_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11938 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11938_DATA_W 32 -#define RFC_ULLRAM_BANK11938_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11938_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11939 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11939_DATA_W 32 -#define RFC_ULLRAM_BANK11939_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11939_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11940 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11940_DATA_W 32 -#define RFC_ULLRAM_BANK11940_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11940_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11941 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11941_DATA_W 32 -#define RFC_ULLRAM_BANK11941_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11941_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11942 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11942_DATA_W 32 -#define RFC_ULLRAM_BANK11942_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11942_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11943 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11943_DATA_W 32 -#define RFC_ULLRAM_BANK11943_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11943_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11944 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11944_DATA_W 32 -#define RFC_ULLRAM_BANK11944_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11944_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11945 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11945_DATA_W 32 -#define RFC_ULLRAM_BANK11945_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11945_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11946 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11946_DATA_W 32 -#define RFC_ULLRAM_BANK11946_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11946_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11947 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11947_DATA_W 32 -#define RFC_ULLRAM_BANK11947_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11947_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11948 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11948_DATA_W 32 -#define RFC_ULLRAM_BANK11948_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11948_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11949 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11949_DATA_W 32 -#define RFC_ULLRAM_BANK11949_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11949_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11950 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11950_DATA_W 32 -#define RFC_ULLRAM_BANK11950_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11950_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11951 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11951_DATA_W 32 -#define RFC_ULLRAM_BANK11951_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11951_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11952 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11952_DATA_W 32 -#define RFC_ULLRAM_BANK11952_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11952_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11953 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11953_DATA_W 32 -#define RFC_ULLRAM_BANK11953_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11953_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11954 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11954_DATA_W 32 -#define RFC_ULLRAM_BANK11954_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11954_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11955 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11955_DATA_W 32 -#define RFC_ULLRAM_BANK11955_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11955_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11956 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11956_DATA_W 32 -#define RFC_ULLRAM_BANK11956_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11956_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11957 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11957_DATA_W 32 -#define RFC_ULLRAM_BANK11957_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11957_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11958 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11958_DATA_W 32 -#define RFC_ULLRAM_BANK11958_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11958_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11959 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11959_DATA_W 32 -#define RFC_ULLRAM_BANK11959_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11959_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11960 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11960_DATA_W 32 -#define RFC_ULLRAM_BANK11960_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11960_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11961 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11961_DATA_W 32 -#define RFC_ULLRAM_BANK11961_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11961_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11962 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11962_DATA_W 32 -#define RFC_ULLRAM_BANK11962_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11962_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11963 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11963_DATA_W 32 -#define RFC_ULLRAM_BANK11963_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11963_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11964 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11964_DATA_W 32 -#define RFC_ULLRAM_BANK11964_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11964_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11965 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11965_DATA_W 32 -#define RFC_ULLRAM_BANK11965_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11965_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11966 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11966_DATA_W 32 -#define RFC_ULLRAM_BANK11966_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11966_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11967 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11967_DATA_W 32 -#define RFC_ULLRAM_BANK11967_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11967_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11968 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11968_DATA_W 32 -#define RFC_ULLRAM_BANK11968_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11968_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11969 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11969_DATA_W 32 -#define RFC_ULLRAM_BANK11969_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11969_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11970 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11970_DATA_W 32 -#define RFC_ULLRAM_BANK11970_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11970_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11971 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11971_DATA_W 32 -#define RFC_ULLRAM_BANK11971_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11971_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11972 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11972_DATA_W 32 -#define RFC_ULLRAM_BANK11972_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11972_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11973 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11973_DATA_W 32 -#define RFC_ULLRAM_BANK11973_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11973_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11974 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11974_DATA_W 32 -#define RFC_ULLRAM_BANK11974_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11974_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11975 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11975_DATA_W 32 -#define RFC_ULLRAM_BANK11975_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11975_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11976 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11976_DATA_W 32 -#define RFC_ULLRAM_BANK11976_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11976_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11977 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11977_DATA_W 32 -#define RFC_ULLRAM_BANK11977_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11977_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11978 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11978_DATA_W 32 -#define RFC_ULLRAM_BANK11978_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11978_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11979 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11979_DATA_W 32 -#define RFC_ULLRAM_BANK11979_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11979_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11980 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11980_DATA_W 32 -#define RFC_ULLRAM_BANK11980_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11980_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11981 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11981_DATA_W 32 -#define RFC_ULLRAM_BANK11981_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11981_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11982 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11982_DATA_W 32 -#define RFC_ULLRAM_BANK11982_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11982_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11983 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11983_DATA_W 32 -#define RFC_ULLRAM_BANK11983_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11983_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11984 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11984_DATA_W 32 -#define RFC_ULLRAM_BANK11984_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11984_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11985 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11985_DATA_W 32 -#define RFC_ULLRAM_BANK11985_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11985_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11986 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11986_DATA_W 32 -#define RFC_ULLRAM_BANK11986_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11986_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11987 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11987_DATA_W 32 -#define RFC_ULLRAM_BANK11987_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11987_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11988 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11988_DATA_W 32 -#define RFC_ULLRAM_BANK11988_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11988_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11989 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11989_DATA_W 32 -#define RFC_ULLRAM_BANK11989_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11989_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11990 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11990_DATA_W 32 -#define RFC_ULLRAM_BANK11990_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11990_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11991 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11991_DATA_W 32 -#define RFC_ULLRAM_BANK11991_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11991_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11992 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11992_DATA_W 32 -#define RFC_ULLRAM_BANK11992_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11992_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11993 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11993_DATA_W 32 -#define RFC_ULLRAM_BANK11993_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11993_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11994 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11994_DATA_W 32 -#define RFC_ULLRAM_BANK11994_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11994_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11995 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11995_DATA_W 32 -#define RFC_ULLRAM_BANK11995_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11995_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11996 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11996_DATA_W 32 -#define RFC_ULLRAM_BANK11996_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11996_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11997 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11997_DATA_W 32 -#define RFC_ULLRAM_BANK11997_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11997_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11998 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11998_DATA_W 32 -#define RFC_ULLRAM_BANK11998_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11998_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK11999 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK11999_DATA_W 32 -#define RFC_ULLRAM_BANK11999_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK11999_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12000 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12000_DATA_W 32 -#define RFC_ULLRAM_BANK12000_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12000_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12001 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12001_DATA_W 32 -#define RFC_ULLRAM_BANK12001_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12001_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12002 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12002_DATA_W 32 -#define RFC_ULLRAM_BANK12002_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12002_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12003 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12003_DATA_W 32 -#define RFC_ULLRAM_BANK12003_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12003_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12004 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12004_DATA_W 32 -#define RFC_ULLRAM_BANK12004_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12004_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12005 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12005_DATA_W 32 -#define RFC_ULLRAM_BANK12005_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12005_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12006 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12006_DATA_W 32 -#define RFC_ULLRAM_BANK12006_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12006_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12007 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12007_DATA_W 32 -#define RFC_ULLRAM_BANK12007_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12007_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12008 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12008_DATA_W 32 -#define RFC_ULLRAM_BANK12008_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12008_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12009 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12009_DATA_W 32 -#define RFC_ULLRAM_BANK12009_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12009_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12010 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12010_DATA_W 32 -#define RFC_ULLRAM_BANK12010_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12010_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12011 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12011_DATA_W 32 -#define RFC_ULLRAM_BANK12011_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12011_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12012 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12012_DATA_W 32 -#define RFC_ULLRAM_BANK12012_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12012_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12013 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12013_DATA_W 32 -#define RFC_ULLRAM_BANK12013_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12013_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12014 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12014_DATA_W 32 -#define RFC_ULLRAM_BANK12014_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12014_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12015 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12015_DATA_W 32 -#define RFC_ULLRAM_BANK12015_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12015_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12016 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12016_DATA_W 32 -#define RFC_ULLRAM_BANK12016_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12016_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12017 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12017_DATA_W 32 -#define RFC_ULLRAM_BANK12017_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12017_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12018 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12018_DATA_W 32 -#define RFC_ULLRAM_BANK12018_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12018_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12019 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12019_DATA_W 32 -#define RFC_ULLRAM_BANK12019_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12019_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12020 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12020_DATA_W 32 -#define RFC_ULLRAM_BANK12020_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12020_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12021 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12021_DATA_W 32 -#define RFC_ULLRAM_BANK12021_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12021_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12022 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12022_DATA_W 32 -#define RFC_ULLRAM_BANK12022_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12022_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12023 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12023_DATA_W 32 -#define RFC_ULLRAM_BANK12023_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12023_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12024 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12024_DATA_W 32 -#define RFC_ULLRAM_BANK12024_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12024_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12025 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12025_DATA_W 32 -#define RFC_ULLRAM_BANK12025_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12025_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12026 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12026_DATA_W 32 -#define RFC_ULLRAM_BANK12026_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12026_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12027 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12027_DATA_W 32 -#define RFC_ULLRAM_BANK12027_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12027_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12028 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12028_DATA_W 32 -#define RFC_ULLRAM_BANK12028_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12028_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12029 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12029_DATA_W 32 -#define RFC_ULLRAM_BANK12029_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12029_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12030 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12030_DATA_W 32 -#define RFC_ULLRAM_BANK12030_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12030_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12031 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12031_DATA_W 32 -#define RFC_ULLRAM_BANK12031_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12031_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12032 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12032_DATA_W 32 -#define RFC_ULLRAM_BANK12032_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12032_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12033 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12033_DATA_W 32 -#define RFC_ULLRAM_BANK12033_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12033_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12034 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12034_DATA_W 32 -#define RFC_ULLRAM_BANK12034_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12034_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12035 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12035_DATA_W 32 -#define RFC_ULLRAM_BANK12035_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12035_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12036 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12036_DATA_W 32 -#define RFC_ULLRAM_BANK12036_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12036_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12037 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12037_DATA_W 32 -#define RFC_ULLRAM_BANK12037_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12037_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12038 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12038_DATA_W 32 -#define RFC_ULLRAM_BANK12038_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12038_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12039 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12039_DATA_W 32 -#define RFC_ULLRAM_BANK12039_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12039_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12040 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12040_DATA_W 32 -#define RFC_ULLRAM_BANK12040_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12040_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12041 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12041_DATA_W 32 -#define RFC_ULLRAM_BANK12041_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12041_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12042 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12042_DATA_W 32 -#define RFC_ULLRAM_BANK12042_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12042_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12043 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12043_DATA_W 32 -#define RFC_ULLRAM_BANK12043_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12043_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12044 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12044_DATA_W 32 -#define RFC_ULLRAM_BANK12044_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12044_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12045 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12045_DATA_W 32 -#define RFC_ULLRAM_BANK12045_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12045_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12046 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12046_DATA_W 32 -#define RFC_ULLRAM_BANK12046_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12046_DATA_S 0 - -//***************************************************************************** -// -// Register: RFC_ULLRAM_O_BANK12047 -// -//***************************************************************************** -// Field: [31:0] DATA -// -// SRAM data -#define RFC_ULLRAM_BANK12047_DATA_W 32 -#define RFC_ULLRAM_BANK12047_DATA_M 0xFFFFFFFF -#define RFC_ULLRAM_BANK12047_DATA_S 0 - - -#endif // __RFC_ULLRAM__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h deleted file mode 100644 index 7bbdcd6101a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_smph.h +++ /dev/null @@ -1,1455 +0,0 @@ -/****************************************************************************** -* Filename: hw_smph_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_SMPH_H__ -#define __HW_SMPH_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// SMPH component -// -//***************************************************************************** -// MCU SEMAPHORE 0 -#define SMPH_O_SMPH0 0x00000000 - -// MCU SEMAPHORE 1 -#define SMPH_O_SMPH1 0x00000004 - -// MCU SEMAPHORE 2 -#define SMPH_O_SMPH2 0x00000008 - -// MCU SEMAPHORE 3 -#define SMPH_O_SMPH3 0x0000000C - -// MCU SEMAPHORE 4 -#define SMPH_O_SMPH4 0x00000010 - -// MCU SEMAPHORE 5 -#define SMPH_O_SMPH5 0x00000014 - -// MCU SEMAPHORE 6 -#define SMPH_O_SMPH6 0x00000018 - -// MCU SEMAPHORE 7 -#define SMPH_O_SMPH7 0x0000001C - -// MCU SEMAPHORE 8 -#define SMPH_O_SMPH8 0x00000020 - -// MCU SEMAPHORE 9 -#define SMPH_O_SMPH9 0x00000024 - -// MCU SEMAPHORE 10 -#define SMPH_O_SMPH10 0x00000028 - -// MCU SEMAPHORE 11 -#define SMPH_O_SMPH11 0x0000002C - -// MCU SEMAPHORE 12 -#define SMPH_O_SMPH12 0x00000030 - -// MCU SEMAPHORE 13 -#define SMPH_O_SMPH13 0x00000034 - -// MCU SEMAPHORE 14 -#define SMPH_O_SMPH14 0x00000038 - -// MCU SEMAPHORE 15 -#define SMPH_O_SMPH15 0x0000003C - -// MCU SEMAPHORE 16 -#define SMPH_O_SMPH16 0x00000040 - -// MCU SEMAPHORE 17 -#define SMPH_O_SMPH17 0x00000044 - -// MCU SEMAPHORE 18 -#define SMPH_O_SMPH18 0x00000048 - -// MCU SEMAPHORE 19 -#define SMPH_O_SMPH19 0x0000004C - -// MCU SEMAPHORE 20 -#define SMPH_O_SMPH20 0x00000050 - -// MCU SEMAPHORE 21 -#define SMPH_O_SMPH21 0x00000054 - -// MCU SEMAPHORE 22 -#define SMPH_O_SMPH22 0x00000058 - -// MCU SEMAPHORE 23 -#define SMPH_O_SMPH23 0x0000005C - -// MCU SEMAPHORE 24 -#define SMPH_O_SMPH24 0x00000060 - -// MCU SEMAPHORE 25 -#define SMPH_O_SMPH25 0x00000064 - -// MCU SEMAPHORE 26 -#define SMPH_O_SMPH26 0x00000068 - -// MCU SEMAPHORE 27 -#define SMPH_O_SMPH27 0x0000006C - -// MCU SEMAPHORE 28 -#define SMPH_O_SMPH28 0x00000070 - -// MCU SEMAPHORE 29 -#define SMPH_O_SMPH29 0x00000074 - -// MCU SEMAPHORE 30 -#define SMPH_O_SMPH30 0x00000078 - -// MCU SEMAPHORE 31 -#define SMPH_O_SMPH31 0x0000007C - -// MCU SEMAPHORE 0 ALIAS -#define SMPH_O_PEEK0 0x00000800 - -// MCU SEMAPHORE 1 ALIAS -#define SMPH_O_PEEK1 0x00000804 - -// MCU SEMAPHORE 2 ALIAS -#define SMPH_O_PEEK2 0x00000808 - -// MCU SEMAPHORE 3 ALIAS -#define SMPH_O_PEEK3 0x0000080C - -// MCU SEMAPHORE 4 ALIAS -#define SMPH_O_PEEK4 0x00000810 - -// MCU SEMAPHORE 5 ALIAS -#define SMPH_O_PEEK5 0x00000814 - -// MCU SEMAPHORE 6 ALIAS -#define SMPH_O_PEEK6 0x00000818 - -// MCU SEMAPHORE 7 ALIAS -#define SMPH_O_PEEK7 0x0000081C - -// MCU SEMAPHORE 8 ALIAS -#define SMPH_O_PEEK8 0x00000820 - -// MCU SEMAPHORE 9 ALIAS -#define SMPH_O_PEEK9 0x00000824 - -// MCU SEMAPHORE 10 ALIAS -#define SMPH_O_PEEK10 0x00000828 - -// MCU SEMAPHORE 11 ALIAS -#define SMPH_O_PEEK11 0x0000082C - -// MCU SEMAPHORE 12 ALIAS -#define SMPH_O_PEEK12 0x00000830 - -// MCU SEMAPHORE 13 ALIAS -#define SMPH_O_PEEK13 0x00000834 - -// MCU SEMAPHORE 14 ALIAS -#define SMPH_O_PEEK14 0x00000838 - -// MCU SEMAPHORE 15 ALIAS -#define SMPH_O_PEEK15 0x0000083C - -// MCU SEMAPHORE 16 ALIAS -#define SMPH_O_PEEK16 0x00000840 - -// MCU SEMAPHORE 17 ALIAS -#define SMPH_O_PEEK17 0x00000844 - -// MCU SEMAPHORE 18 ALIAS -#define SMPH_O_PEEK18 0x00000848 - -// MCU SEMAPHORE 19 ALIAS -#define SMPH_O_PEEK19 0x0000084C - -// MCU SEMAPHORE 20 ALIAS -#define SMPH_O_PEEK20 0x00000850 - -// MCU SEMAPHORE 21 ALIAS -#define SMPH_O_PEEK21 0x00000854 - -// MCU SEMAPHORE 22 ALIAS -#define SMPH_O_PEEK22 0x00000858 - -// MCU SEMAPHORE 23 ALIAS -#define SMPH_O_PEEK23 0x0000085C - -// MCU SEMAPHORE 24 ALIAS -#define SMPH_O_PEEK24 0x00000860 - -// MCU SEMAPHORE 25 ALIAS -#define SMPH_O_PEEK25 0x00000864 - -// MCU SEMAPHORE 26 ALIAS -#define SMPH_O_PEEK26 0x00000868 - -// MCU SEMAPHORE 27 ALIAS -#define SMPH_O_PEEK27 0x0000086C - -// MCU SEMAPHORE 28 ALIAS -#define SMPH_O_PEEK28 0x00000870 - -// MCU SEMAPHORE 29 ALIAS -#define SMPH_O_PEEK29 0x00000874 - -// MCU SEMAPHORE 30 ALIAS -#define SMPH_O_PEEK30 0x00000878 - -// MCU SEMAPHORE 31 ALIAS -#define SMPH_O_PEEK31 0x0000087C - -//***************************************************************************** -// -// Register: SMPH_O_SMPH0 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH0_STAT 0x00000001 -#define SMPH_SMPH0_STAT_BITN 0 -#define SMPH_SMPH0_STAT_M 0x00000001 -#define SMPH_SMPH0_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH1 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH1_STAT 0x00000001 -#define SMPH_SMPH1_STAT_BITN 0 -#define SMPH_SMPH1_STAT_M 0x00000001 -#define SMPH_SMPH1_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH2 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH2_STAT 0x00000001 -#define SMPH_SMPH2_STAT_BITN 0 -#define SMPH_SMPH2_STAT_M 0x00000001 -#define SMPH_SMPH2_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH3 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH3_STAT 0x00000001 -#define SMPH_SMPH3_STAT_BITN 0 -#define SMPH_SMPH3_STAT_M 0x00000001 -#define SMPH_SMPH3_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH4 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH4_STAT 0x00000001 -#define SMPH_SMPH4_STAT_BITN 0 -#define SMPH_SMPH4_STAT_M 0x00000001 -#define SMPH_SMPH4_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH5 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH5_STAT 0x00000001 -#define SMPH_SMPH5_STAT_BITN 0 -#define SMPH_SMPH5_STAT_M 0x00000001 -#define SMPH_SMPH5_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH6 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH6_STAT 0x00000001 -#define SMPH_SMPH6_STAT_BITN 0 -#define SMPH_SMPH6_STAT_M 0x00000001 -#define SMPH_SMPH6_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH7 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH7_STAT 0x00000001 -#define SMPH_SMPH7_STAT_BITN 0 -#define SMPH_SMPH7_STAT_M 0x00000001 -#define SMPH_SMPH7_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH8 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH8_STAT 0x00000001 -#define SMPH_SMPH8_STAT_BITN 0 -#define SMPH_SMPH8_STAT_M 0x00000001 -#define SMPH_SMPH8_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH9 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH9_STAT 0x00000001 -#define SMPH_SMPH9_STAT_BITN 0 -#define SMPH_SMPH9_STAT_M 0x00000001 -#define SMPH_SMPH9_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH10 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH10_STAT 0x00000001 -#define SMPH_SMPH10_STAT_BITN 0 -#define SMPH_SMPH10_STAT_M 0x00000001 -#define SMPH_SMPH10_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH11 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH11_STAT 0x00000001 -#define SMPH_SMPH11_STAT_BITN 0 -#define SMPH_SMPH11_STAT_M 0x00000001 -#define SMPH_SMPH11_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH12 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH12_STAT 0x00000001 -#define SMPH_SMPH12_STAT_BITN 0 -#define SMPH_SMPH12_STAT_M 0x00000001 -#define SMPH_SMPH12_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH13 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH13_STAT 0x00000001 -#define SMPH_SMPH13_STAT_BITN 0 -#define SMPH_SMPH13_STAT_M 0x00000001 -#define SMPH_SMPH13_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH14 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH14_STAT 0x00000001 -#define SMPH_SMPH14_STAT_BITN 0 -#define SMPH_SMPH14_STAT_M 0x00000001 -#define SMPH_SMPH14_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH15 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH15_STAT 0x00000001 -#define SMPH_SMPH15_STAT_BITN 0 -#define SMPH_SMPH15_STAT_M 0x00000001 -#define SMPH_SMPH15_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH16 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH16_STAT 0x00000001 -#define SMPH_SMPH16_STAT_BITN 0 -#define SMPH_SMPH16_STAT_M 0x00000001 -#define SMPH_SMPH16_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH17 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH17_STAT 0x00000001 -#define SMPH_SMPH17_STAT_BITN 0 -#define SMPH_SMPH17_STAT_M 0x00000001 -#define SMPH_SMPH17_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH18 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH18_STAT 0x00000001 -#define SMPH_SMPH18_STAT_BITN 0 -#define SMPH_SMPH18_STAT_M 0x00000001 -#define SMPH_SMPH18_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH19 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH19_STAT 0x00000001 -#define SMPH_SMPH19_STAT_BITN 0 -#define SMPH_SMPH19_STAT_M 0x00000001 -#define SMPH_SMPH19_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH20 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH20_STAT 0x00000001 -#define SMPH_SMPH20_STAT_BITN 0 -#define SMPH_SMPH20_STAT_M 0x00000001 -#define SMPH_SMPH20_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH21 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH21_STAT 0x00000001 -#define SMPH_SMPH21_STAT_BITN 0 -#define SMPH_SMPH21_STAT_M 0x00000001 -#define SMPH_SMPH21_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH22 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH22_STAT 0x00000001 -#define SMPH_SMPH22_STAT_BITN 0 -#define SMPH_SMPH22_STAT_M 0x00000001 -#define SMPH_SMPH22_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH23 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH23_STAT 0x00000001 -#define SMPH_SMPH23_STAT_BITN 0 -#define SMPH_SMPH23_STAT_M 0x00000001 -#define SMPH_SMPH23_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH24 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH24_STAT 0x00000001 -#define SMPH_SMPH24_STAT_BITN 0 -#define SMPH_SMPH24_STAT_M 0x00000001 -#define SMPH_SMPH24_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH25 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH25_STAT 0x00000001 -#define SMPH_SMPH25_STAT_BITN 0 -#define SMPH_SMPH25_STAT_M 0x00000001 -#define SMPH_SMPH25_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH26 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH26_STAT 0x00000001 -#define SMPH_SMPH26_STAT_BITN 0 -#define SMPH_SMPH26_STAT_M 0x00000001 -#define SMPH_SMPH26_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH27 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH27_STAT 0x00000001 -#define SMPH_SMPH27_STAT_BITN 0 -#define SMPH_SMPH27_STAT_M 0x00000001 -#define SMPH_SMPH27_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH28 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH28_STAT 0x00000001 -#define SMPH_SMPH28_STAT_BITN 0 -#define SMPH_SMPH28_STAT_M 0x00000001 -#define SMPH_SMPH28_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH29 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH29_STAT 0x00000001 -#define SMPH_SMPH29_STAT_BITN 0 -#define SMPH_SMPH29_STAT_M 0x00000001 -#define SMPH_SMPH29_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH30 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH30_STAT 0x00000001 -#define SMPH_SMPH30_STAT_BITN 0 -#define SMPH_SMPH30_STAT_M 0x00000001 -#define SMPH_SMPH30_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_SMPH31 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Reading the register causes it to change value to 0. Releasing the semaphore -// is done by writing 1. -#define SMPH_SMPH31_STAT 0x00000001 -#define SMPH_SMPH31_STAT_BITN 0 -#define SMPH_SMPH31_STAT_M 0x00000001 -#define SMPH_SMPH31_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK0 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK0_STAT 0x00000001 -#define SMPH_PEEK0_STAT_BITN 0 -#define SMPH_PEEK0_STAT_M 0x00000001 -#define SMPH_PEEK0_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK1 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK1_STAT 0x00000001 -#define SMPH_PEEK1_STAT_BITN 0 -#define SMPH_PEEK1_STAT_M 0x00000001 -#define SMPH_PEEK1_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK2 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK2_STAT 0x00000001 -#define SMPH_PEEK2_STAT_BITN 0 -#define SMPH_PEEK2_STAT_M 0x00000001 -#define SMPH_PEEK2_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK3 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK3_STAT 0x00000001 -#define SMPH_PEEK3_STAT_BITN 0 -#define SMPH_PEEK3_STAT_M 0x00000001 -#define SMPH_PEEK3_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK4 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK4_STAT 0x00000001 -#define SMPH_PEEK4_STAT_BITN 0 -#define SMPH_PEEK4_STAT_M 0x00000001 -#define SMPH_PEEK4_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK5 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK5_STAT 0x00000001 -#define SMPH_PEEK5_STAT_BITN 0 -#define SMPH_PEEK5_STAT_M 0x00000001 -#define SMPH_PEEK5_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK6 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK6_STAT 0x00000001 -#define SMPH_PEEK6_STAT_BITN 0 -#define SMPH_PEEK6_STAT_M 0x00000001 -#define SMPH_PEEK6_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK7 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK7_STAT 0x00000001 -#define SMPH_PEEK7_STAT_BITN 0 -#define SMPH_PEEK7_STAT_M 0x00000001 -#define SMPH_PEEK7_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK8 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK8_STAT 0x00000001 -#define SMPH_PEEK8_STAT_BITN 0 -#define SMPH_PEEK8_STAT_M 0x00000001 -#define SMPH_PEEK8_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK9 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK9_STAT 0x00000001 -#define SMPH_PEEK9_STAT_BITN 0 -#define SMPH_PEEK9_STAT_M 0x00000001 -#define SMPH_PEEK9_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK10 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK10_STAT 0x00000001 -#define SMPH_PEEK10_STAT_BITN 0 -#define SMPH_PEEK10_STAT_M 0x00000001 -#define SMPH_PEEK10_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK11 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK11_STAT 0x00000001 -#define SMPH_PEEK11_STAT_BITN 0 -#define SMPH_PEEK11_STAT_M 0x00000001 -#define SMPH_PEEK11_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK12 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK12_STAT 0x00000001 -#define SMPH_PEEK12_STAT_BITN 0 -#define SMPH_PEEK12_STAT_M 0x00000001 -#define SMPH_PEEK12_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK13 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK13_STAT 0x00000001 -#define SMPH_PEEK13_STAT_BITN 0 -#define SMPH_PEEK13_STAT_M 0x00000001 -#define SMPH_PEEK13_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK14 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK14_STAT 0x00000001 -#define SMPH_PEEK14_STAT_BITN 0 -#define SMPH_PEEK14_STAT_M 0x00000001 -#define SMPH_PEEK14_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK15 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK15_STAT 0x00000001 -#define SMPH_PEEK15_STAT_BITN 0 -#define SMPH_PEEK15_STAT_M 0x00000001 -#define SMPH_PEEK15_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK16 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK16_STAT 0x00000001 -#define SMPH_PEEK16_STAT_BITN 0 -#define SMPH_PEEK16_STAT_M 0x00000001 -#define SMPH_PEEK16_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK17 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK17_STAT 0x00000001 -#define SMPH_PEEK17_STAT_BITN 0 -#define SMPH_PEEK17_STAT_M 0x00000001 -#define SMPH_PEEK17_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK18 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK18_STAT 0x00000001 -#define SMPH_PEEK18_STAT_BITN 0 -#define SMPH_PEEK18_STAT_M 0x00000001 -#define SMPH_PEEK18_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK19 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK19_STAT 0x00000001 -#define SMPH_PEEK19_STAT_BITN 0 -#define SMPH_PEEK19_STAT_M 0x00000001 -#define SMPH_PEEK19_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK20 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK20_STAT 0x00000001 -#define SMPH_PEEK20_STAT_BITN 0 -#define SMPH_PEEK20_STAT_M 0x00000001 -#define SMPH_PEEK20_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK21 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK21_STAT 0x00000001 -#define SMPH_PEEK21_STAT_BITN 0 -#define SMPH_PEEK21_STAT_M 0x00000001 -#define SMPH_PEEK21_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK22 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK22_STAT 0x00000001 -#define SMPH_PEEK22_STAT_BITN 0 -#define SMPH_PEEK22_STAT_M 0x00000001 -#define SMPH_PEEK22_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK23 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK23_STAT 0x00000001 -#define SMPH_PEEK23_STAT_BITN 0 -#define SMPH_PEEK23_STAT_M 0x00000001 -#define SMPH_PEEK23_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK24 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK24_STAT 0x00000001 -#define SMPH_PEEK24_STAT_BITN 0 -#define SMPH_PEEK24_STAT_M 0x00000001 -#define SMPH_PEEK24_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK25 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK25_STAT 0x00000001 -#define SMPH_PEEK25_STAT_BITN 0 -#define SMPH_PEEK25_STAT_M 0x00000001 -#define SMPH_PEEK25_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK26 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK26_STAT 0x00000001 -#define SMPH_PEEK26_STAT_BITN 0 -#define SMPH_PEEK26_STAT_M 0x00000001 -#define SMPH_PEEK26_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK27 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK27_STAT 0x00000001 -#define SMPH_PEEK27_STAT_BITN 0 -#define SMPH_PEEK27_STAT_M 0x00000001 -#define SMPH_PEEK27_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK28 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK28_STAT 0x00000001 -#define SMPH_PEEK28_STAT_BITN 0 -#define SMPH_PEEK28_STAT_M 0x00000001 -#define SMPH_PEEK28_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK29 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK29_STAT 0x00000001 -#define SMPH_PEEK29_STAT_BITN 0 -#define SMPH_PEEK29_STAT_M 0x00000001 -#define SMPH_PEEK29_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK30 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK30_STAT 0x00000001 -#define SMPH_PEEK30_STAT_BITN 0 -#define SMPH_PEEK30_STAT_M 0x00000001 -#define SMPH_PEEK30_STAT_S 0 - -//***************************************************************************** -// -// Register: SMPH_O_PEEK31 -// -//***************************************************************************** -// Field: [0] STAT -// -// Status when reading: -// -// 0: Semaphore is taken -// 1: Semaphore is available -// -// Used for semaphore debugging. A read operation will not change register -// value. Register writing is not possible. -#define SMPH_PEEK31_STAT 0x00000001 -#define SMPH_PEEK31_STAT_BITN 0 -#define SMPH_PEEK31_STAT_M 0x00000001 -#define SMPH_PEEK31_STAT_S 0 - - -#endif // __SMPH__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h deleted file mode 100644 index 80d642200c4..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_sram_mmr.h +++ /dev/null @@ -1,150 +0,0 @@ -/****************************************************************************** -* Filename: hw_sram_mmr_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_SRAM_MMR_H__ -#define __HW_SRAM_MMR_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// SRAM_MMR component -// -//***************************************************************************** -// Parity Error Control -#define SRAM_MMR_O_PER_CTL 0x00000000 - -// Parity Error Check -#define SRAM_MMR_O_PER_CHK 0x00000004 - -// Parity Error Debug -#define SRAM_MMR_O_PER_DBG 0x00000008 - -// Memory Control -#define SRAM_MMR_O_MEM_CTL 0x0000000C - -//***************************************************************************** -// -// Register: SRAM_MMR_O_PER_CTL -// -//***************************************************************************** -// Field: [8] PER_DISABLE -// -// Parity Status Disable -// -// 0: A parity error will update PER_CHK.PER_ADDR field -// 1: Parity error does not update PER_CHK.PER_ADDR field -#define SRAM_MMR_PER_CTL_PER_DISABLE 0x00000100 -#define SRAM_MMR_PER_CTL_PER_DISABLE_BITN 8 -#define SRAM_MMR_PER_CTL_PER_DISABLE_M 0x00000100 -#define SRAM_MMR_PER_CTL_PER_DISABLE_S 8 - -// Field: [0] PER_DEBUG_ENABLE -// -// Parity Error Debug Enable -// -// 0: Normal operation -// 1: An address offset can be written to PER_DBG.PER_DEBUG_ADDR and parity -// errors will be generated on reads from within this offset -#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE 0x00000001 -#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_BITN 0 -#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_M 0x00000001 -#define SRAM_MMR_PER_CTL_PER_DEBUG_ENABLE_S 0 - -//***************************************************************************** -// -// Register: SRAM_MMR_O_PER_CHK -// -//***************************************************************************** -// Field: [23:0] PER_ADDR -// -// Parity Error Address Offset -// Returns the last address offset which resulted in a parity error during an -// SRAM read. The address offset returned is always the word-aligned address -// that contains the location with the parity error. For parity faults on non -// word-aligned accesses, CPU_SCS:BFAR.ADDRESS will hold the address of the -// location that resulted in parity error. -#define SRAM_MMR_PER_CHK_PER_ADDR_W 24 -#define SRAM_MMR_PER_CHK_PER_ADDR_M 0x00FFFFFF -#define SRAM_MMR_PER_CHK_PER_ADDR_S 0 - -//***************************************************************************** -// -// Register: SRAM_MMR_O_PER_DBG -// -//***************************************************************************** -// Field: [23:0] PER_DEBUG_ADDR -// -// Debug Parity Error Address Offset -// When PER_CTL.PER_DEBUG is 1, this field is used to set a parity debug -// address offset. The address offset must be a word-aligned address. Writes -// within this address offset will force incorrect parity bits to be stored -// together with the data written. The following reads within this same address -// offset will thus result in parity errors to be generated. -#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_W 24 -#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_M 0x00FFFFFF -#define SRAM_MMR_PER_DBG_PER_DEBUG_ADDR_S 0 - -//***************************************************************************** -// -// Register: SRAM_MMR_O_MEM_CTL -// -//***************************************************************************** -// Field: [1] MEM_BUSY -// -// Memory Busy status -// -// 0: Memory accepts transfers -// 1: Memory controller is busy during initialization. Read and write transfers -// are not performed. -#define SRAM_MMR_MEM_CTL_MEM_BUSY 0x00000002 -#define SRAM_MMR_MEM_CTL_MEM_BUSY_BITN 1 -#define SRAM_MMR_MEM_CTL_MEM_BUSY_M 0x00000002 -#define SRAM_MMR_MEM_CTL_MEM_BUSY_S 1 - -// Field: [0] MEM_CLR_EN -// -// Memory Contents Initialization enable -// -// Writing 1 to MEM_CLR_EN will start memory initialization. The contents of -// all byte locations will be initialized to 0x00. MEM_BUSY will be 1 until -// memory initialization has completed. -#define SRAM_MMR_MEM_CTL_MEM_CLR_EN 0x00000001 -#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_BITN 0 -#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_M 0x00000001 -#define SRAM_MMR_MEM_CTL_MEM_CLR_EN_S 0 - - -#endif // __SRAM_MMR__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h deleted file mode 100644 index 403d6620a18..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_ssi.h +++ /dev/null @@ -1,544 +0,0 @@ -/****************************************************************************** -* Filename: hw_ssi_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_SSI_H__ -#define __HW_SSI_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// SSI component -// -//***************************************************************************** -// Control 0 -#define SSI_O_CR0 0x00000000 - -// Control 1 -#define SSI_O_CR1 0x00000004 - -// Data -#define SSI_O_DR 0x00000008 - -// Status -#define SSI_O_SR 0x0000000C - -// Clock Prescale -#define SSI_O_CPSR 0x00000010 - -// Interrupt Mask Set and Clear -#define SSI_O_IMSC 0x00000014 - -// Raw Interrupt Status -#define SSI_O_RIS 0x00000018 - -// Masked Interrupt Status -#define SSI_O_MIS 0x0000001C - -// Interrupt Clear -#define SSI_O_ICR 0x00000020 - -// DMA Control -#define SSI_O_DMACR 0x00000024 - -//***************************************************************************** -// -// Register: SSI_O_CR0 -// -//***************************************************************************** -// Field: [15:8] SCR -// -// Serial clock rate: -// This is used to generate the transmit and receive bit rate of the SSI. The -// bit rate is -// (SSI's clock frequency)/((SCR+1)*CPSR.CPSDVSR). -// SCR is a value from 0-255. -#define SSI_CR0_SCR_W 8 -#define SSI_CR0_SCR_M 0x0000FF00 -#define SSI_CR0_SCR_S 8 - -// Field: [7] SPH -// -// CLKOUT phase (Motorola SPI frame format only) -// This bit selects the clock edge that captures data and enables it to change -// state. It -// has the most impact on the first bit transmitted by either permitting or not -// permitting a clock transition before the first data capture edge. -// ENUMs: -// 2ND_CLK_EDGE Data is captured on the second clock edge -// transition. -// 1ST_CLK_EDGE Data is captured on the first clock edge -// transition. -#define SSI_CR0_SPH 0x00000080 -#define SSI_CR0_SPH_BITN 7 -#define SSI_CR0_SPH_M 0x00000080 -#define SSI_CR0_SPH_S 7 -#define SSI_CR0_SPH_2ND_CLK_EDGE 0x00000080 -#define SSI_CR0_SPH_1ST_CLK_EDGE 0x00000000 - -// Field: [6] SPO -// -// CLKOUT polarity (Motorola SPI frame format only) -// ENUMs: -// HIGH SSI produces a steady state HIGH value on the -// CLKOUT pin when data is not being transferred. -// LOW SSI produces a steady state LOW value on the -// CLKOUT pin when data is -// not being transferred. -#define SSI_CR0_SPO 0x00000040 -#define SSI_CR0_SPO_BITN 6 -#define SSI_CR0_SPO_M 0x00000040 -#define SSI_CR0_SPO_S 6 -#define SSI_CR0_SPO_HIGH 0x00000040 -#define SSI_CR0_SPO_LOW 0x00000000 - -// Field: [5:4] FRF -// -// Frame format. -// The supported frame formats are Motorola SPI, TI synchronous serial and -// National Microwire. -// Value 0'b11 is reserved and shall not be used. -// ENUMs: -// NATIONAL_MICROWIRE National Microwire frame format -// TI_SYNC_SERIAL TI synchronous serial frame format -// MOTOROLA_SPI Motorola SPI frame format -#define SSI_CR0_FRF_W 2 -#define SSI_CR0_FRF_M 0x00000030 -#define SSI_CR0_FRF_S 4 -#define SSI_CR0_FRF_NATIONAL_MICROWIRE 0x00000020 -#define SSI_CR0_FRF_TI_SYNC_SERIAL 0x00000010 -#define SSI_CR0_FRF_MOTOROLA_SPI 0x00000000 - -// Field: [3:0] DSS -// -// Data Size Select. -// Values 0b0000, 0b0001, 0b0010 are reserved and shall not be used. -// ENUMs: -// 16_BIT 16-bit data -// 15_BIT 15-bit data -// 14_BIT 14-bit data -// 13_BIT 13-bit data -// 12_BIT 12-bit data -// 11_BIT 11-bit data -// 10_BIT 10-bit data -// 9_BIT 9-bit data -// 8_BIT 8-bit data -// 7_BIT 7-bit data -// 6_BIT 6-bit data -// 5_BIT 5-bit data -// 4_BIT 4-bit data -#define SSI_CR0_DSS_W 4 -#define SSI_CR0_DSS_M 0x0000000F -#define SSI_CR0_DSS_S 0 -#define SSI_CR0_DSS_16_BIT 0x0000000F -#define SSI_CR0_DSS_15_BIT 0x0000000E -#define SSI_CR0_DSS_14_BIT 0x0000000D -#define SSI_CR0_DSS_13_BIT 0x0000000C -#define SSI_CR0_DSS_12_BIT 0x0000000B -#define SSI_CR0_DSS_11_BIT 0x0000000A -#define SSI_CR0_DSS_10_BIT 0x00000009 -#define SSI_CR0_DSS_9_BIT 0x00000008 -#define SSI_CR0_DSS_8_BIT 0x00000007 -#define SSI_CR0_DSS_7_BIT 0x00000006 -#define SSI_CR0_DSS_6_BIT 0x00000005 -#define SSI_CR0_DSS_5_BIT 0x00000004 -#define SSI_CR0_DSS_4_BIT 0x00000003 - -//***************************************************************************** -// -// Register: SSI_O_CR1 -// -//***************************************************************************** -// Field: [3] SOD -// -// Slave-mode output disabled -// This bit is relevant only in the slave mode, MS=1. In multiple-slave -// systems, it is possible for an SSI master to broadcast a message to all -// slaves in the system while ensuring that only one slave drives data onto its -// serial output line. In such systems the RXD lines from multiple slaves could -// be tied together. To operate in such systems, this bitfield can be set if -// the SSI slave is not supposed to drive the TXD line: -// -// 0: SSI can drive the TXD output in slave mode. -// 1: SSI cannot drive the TXD output in slave mode. -#define SSI_CR1_SOD 0x00000008 -#define SSI_CR1_SOD_BITN 3 -#define SSI_CR1_SOD_M 0x00000008 -#define SSI_CR1_SOD_S 3 - -// Field: [2] MS -// -// Master or slave mode select. This bit can be modified only when SSI is -// disabled, SSE=0. -// ENUMs: -// SLAVE Device configured as slave -// MASTER Device configured as master -#define SSI_CR1_MS 0x00000004 -#define SSI_CR1_MS_BITN 2 -#define SSI_CR1_MS_M 0x00000004 -#define SSI_CR1_MS_S 2 -#define SSI_CR1_MS_SLAVE 0x00000004 -#define SSI_CR1_MS_MASTER 0x00000000 - -// Field: [1] SSE -// -// Synchronous serial interface enable. -// ENUMs: -// SSI_ENABLED Operation enabled -// SSI_DISABLED Operation disabled -#define SSI_CR1_SSE 0x00000002 -#define SSI_CR1_SSE_BITN 1 -#define SSI_CR1_SSE_M 0x00000002 -#define SSI_CR1_SSE_S 1 -#define SSI_CR1_SSE_SSI_ENABLED 0x00000002 -#define SSI_CR1_SSE_SSI_DISABLED 0x00000000 - -// Field: [0] LBM -// -// Loop back mode: -// -// 0: Normal serial port operation enabled. -// 1: Output of transmit serial shifter is connected to input of receive serial -// shifter internally. -#define SSI_CR1_LBM 0x00000001 -#define SSI_CR1_LBM_BITN 0 -#define SSI_CR1_LBM_M 0x00000001 -#define SSI_CR1_LBM_S 0 - -//***************************************************************************** -// -// Register: SSI_O_DR -// -//***************************************************************************** -// Field: [15:0] DATA -// -// Transmit/receive data -// The values read from this field or written to this field must be -// right-justified when SSI is programmed for a data size that is less than 16 -// bits (CR0.DSS != 0b1111). Unused bits at the top are ignored by transmit -// logic. The receive logic automatically right-justifies. -#define SSI_DR_DATA_W 16 -#define SSI_DR_DATA_M 0x0000FFFF -#define SSI_DR_DATA_S 0 - -//***************************************************************************** -// -// Register: SSI_O_SR -// -//***************************************************************************** -// Field: [4] BSY -// -// Serial interface busy: -// -// 0: SSI is idle -// 1: SSI is currently transmitting and/or receiving a frame or the transmit -// FIFO is not empty. -#define SSI_SR_BSY 0x00000010 -#define SSI_SR_BSY_BITN 4 -#define SSI_SR_BSY_M 0x00000010 -#define SSI_SR_BSY_S 4 - -// Field: [3] RFF -// -// Receive FIFO full: -// -// 0: Receive FIFO is not full. -// 1: Receive FIFO is full. -#define SSI_SR_RFF 0x00000008 -#define SSI_SR_RFF_BITN 3 -#define SSI_SR_RFF_M 0x00000008 -#define SSI_SR_RFF_S 3 - -// Field: [2] RNE -// -// Receive FIFO not empty -// -// 0: Receive FIFO is empty. -// 1: Receive FIFO is not empty. -#define SSI_SR_RNE 0x00000004 -#define SSI_SR_RNE_BITN 2 -#define SSI_SR_RNE_M 0x00000004 -#define SSI_SR_RNE_S 2 - -// Field: [1] TNF -// -// Transmit FIFO not full: -// -// 0: Transmit FIFO is full. -// 1: Transmit FIFO is not full. -#define SSI_SR_TNF 0x00000002 -#define SSI_SR_TNF_BITN 1 -#define SSI_SR_TNF_M 0x00000002 -#define SSI_SR_TNF_S 1 - -// Field: [0] TFE -// -// Transmit FIFO empty: -// -// 0: Transmit FIFO is not empty. -// 1: Transmit FIFO is empty. -#define SSI_SR_TFE 0x00000001 -#define SSI_SR_TFE_BITN 0 -#define SSI_SR_TFE_M 0x00000001 -#define SSI_SR_TFE_S 0 - -//***************************************************************************** -// -// Register: SSI_O_CPSR -// -//***************************************************************************** -// Field: [7:0] CPSDVSR -// -// Clock prescale divisor: -// This field specifies the division factor by which the input system clock to -// SSI must be internally divided before further use. -// The value programmed into this field must be an even non-zero number -// (2-254). The least significant bit of the programmed number is hard-coded to -// zero. If an odd number is written to this register, data read back from -// this register has the least significant bit as zero. -#define SSI_CPSR_CPSDVSR_W 8 -#define SSI_CPSR_CPSDVSR_M 0x000000FF -#define SSI_CPSR_CPSDVSR_S 0 - -//***************************************************************************** -// -// Register: SSI_O_IMSC -// -//***************************************************************************** -// Field: [3] TXIM -// -// Transmit FIFO interrupt mask: -// A read returns the current mask for transmit FIFO interrupt. On a write of -// 1, the mask for transmit FIFO interrupt is set which means the interrupt -// state will be reflected in MIS.TXMIS. A write of 0 clears the mask which -// means MIS.TXMIS will not reflect the interrupt. -#define SSI_IMSC_TXIM 0x00000008 -#define SSI_IMSC_TXIM_BITN 3 -#define SSI_IMSC_TXIM_M 0x00000008 -#define SSI_IMSC_TXIM_S 3 - -// Field: [2] RXIM -// -// Receive FIFO interrupt mask: -// A read returns the current mask for receive FIFO interrupt. On a write of 1, -// the mask for receive FIFO interrupt is set which means the interrupt state -// will be reflected in MIS.RXMIS. A write of 0 clears the mask which means -// MIS.RXMIS will not reflect the interrupt. -#define SSI_IMSC_RXIM 0x00000004 -#define SSI_IMSC_RXIM_BITN 2 -#define SSI_IMSC_RXIM_M 0x00000004 -#define SSI_IMSC_RXIM_S 2 - -// Field: [1] RTIM -// -// Receive timeout interrupt mask: -// A read returns the current mask for receive timeout interrupt. On a write of -// 1, the mask for receive timeout interrupt is set which means the interrupt -// state will be reflected in MIS.RTMIS. A write of 0 clears the mask which -// means MIS.RTMIS will not reflect the interrupt. -#define SSI_IMSC_RTIM 0x00000002 -#define SSI_IMSC_RTIM_BITN 1 -#define SSI_IMSC_RTIM_M 0x00000002 -#define SSI_IMSC_RTIM_S 1 - -// Field: [0] RORIM -// -// Receive overrun interrupt mask: -// A read returns the current mask for receive overrun interrupt. On a write of -// 1, the mask for receive overrun interrupt is set which means the interrupt -// state will be reflected in MIS.RORMIS. A write of 0 clears the mask which -// means MIS.RORMIS will not reflect the interrupt. -#define SSI_IMSC_RORIM 0x00000001 -#define SSI_IMSC_RORIM_BITN 0 -#define SSI_IMSC_RORIM_M 0x00000001 -#define SSI_IMSC_RORIM_S 0 - -//***************************************************************************** -// -// Register: SSI_O_RIS -// -//***************************************************************************** -// Field: [3] TXRIS -// -// Raw transmit FIFO interrupt status: -// The transmit interrupt is asserted when there are four or fewer valid -// entries in the transmit FIFO. The transmit interrupt is not qualified with -// the SSI enable signal. Therefore one of the following ways can be used: -// - data can be written to the transmit FIFO prior to enabling the SSI and -// the -// interrupts. -// - SSI and interrupts can be enabled so that data can be written to the -// transmit FIFO by an interrupt service routine. -#define SSI_RIS_TXRIS 0x00000008 -#define SSI_RIS_TXRIS_BITN 3 -#define SSI_RIS_TXRIS_M 0x00000008 -#define SSI_RIS_TXRIS_S 3 - -// Field: [2] RXRIS -// -// Raw interrupt state of receive FIFO interrupt: -// The receive interrupt is asserted when there are four or more valid entries -// in the receive FIFO. -#define SSI_RIS_RXRIS 0x00000004 -#define SSI_RIS_RXRIS_BITN 2 -#define SSI_RIS_RXRIS_M 0x00000004 -#define SSI_RIS_RXRIS_S 2 - -// Field: [1] RTRIS -// -// Raw interrupt state of receive timeout interrupt: -// The receive timeout interrupt is asserted when the receive FIFO is not empty -// and SSI has remained idle for a fixed 32 bit period. This mechanism can be -// used to notify the user that data is still present in the receive FIFO and -// requires servicing. This interrupt is deasserted if the receive FIFO becomes -// empty by subsequent reads, or if new data is received on RXD. -// It can also be cleared by writing to ICR.RTIC. -#define SSI_RIS_RTRIS 0x00000002 -#define SSI_RIS_RTRIS_BITN 1 -#define SSI_RIS_RTRIS_M 0x00000002 -#define SSI_RIS_RTRIS_S 1 - -// Field: [0] RORRIS -// -// Raw interrupt state of receive overrun interrupt: -// The receive overrun interrupt is asserted when the FIFO is already full and -// an additional data frame is received, causing an overrun of the FIFO. Data -// is over-written in the -// receive shift register, but not the FIFO so the FIFO contents stay valid. -// It can also be cleared by writing to ICR.RORIC. -#define SSI_RIS_RORRIS 0x00000001 -#define SSI_RIS_RORRIS_BITN 0 -#define SSI_RIS_RORRIS_M 0x00000001 -#define SSI_RIS_RORRIS_S 0 - -//***************************************************************************** -// -// Register: SSI_O_MIS -// -//***************************************************************************** -// Field: [3] TXMIS -// -// Masked interrupt state of transmit FIFO interrupt: -// This field returns the masked interrupt state of transmit FIFO interrupt -// which is the AND product of raw interrupt state RIS.TXRIS and the mask -// setting IMSC.TXIM. -#define SSI_MIS_TXMIS 0x00000008 -#define SSI_MIS_TXMIS_BITN 3 -#define SSI_MIS_TXMIS_M 0x00000008 -#define SSI_MIS_TXMIS_S 3 - -// Field: [2] RXMIS -// -// Masked interrupt state of receive FIFO interrupt: -// This field returns the masked interrupt state of receive FIFO interrupt -// which is the AND product of raw interrupt state RIS.RXRIS and the mask -// setting IMSC.RXIM. -#define SSI_MIS_RXMIS 0x00000004 -#define SSI_MIS_RXMIS_BITN 2 -#define SSI_MIS_RXMIS_M 0x00000004 -#define SSI_MIS_RXMIS_S 2 - -// Field: [1] RTMIS -// -// Masked interrupt state of receive timeout interrupt: -// This field returns the masked interrupt state of receive timeout interrupt -// which is the AND product of raw interrupt state RIS.RTRIS and the mask -// setting IMSC.RTIM. -#define SSI_MIS_RTMIS 0x00000002 -#define SSI_MIS_RTMIS_BITN 1 -#define SSI_MIS_RTMIS_M 0x00000002 -#define SSI_MIS_RTMIS_S 1 - -// Field: [0] RORMIS -// -// Masked interrupt state of receive overrun interrupt: -// This field returns the masked interrupt state of receive overrun interrupt -// which is the AND product of raw interrupt state RIS.RORRIS and the mask -// setting IMSC.RORIM. -#define SSI_MIS_RORMIS 0x00000001 -#define SSI_MIS_RORMIS_BITN 0 -#define SSI_MIS_RORMIS_M 0x00000001 -#define SSI_MIS_RORMIS_S 0 - -//***************************************************************************** -// -// Register: SSI_O_ICR -// -//***************************************************************************** -// Field: [1] RTIC -// -// Clear the receive timeout interrupt: -// Writing 1 to this field clears the timeout interrupt (RIS.RTRIS). Writing 0 -// has no effect. -#define SSI_ICR_RTIC 0x00000002 -#define SSI_ICR_RTIC_BITN 1 -#define SSI_ICR_RTIC_M 0x00000002 -#define SSI_ICR_RTIC_S 1 - -// Field: [0] RORIC -// -// Clear the receive overrun interrupt: -// Writing 1 to this field clears the overrun error interrupt (RIS.RORRIS). -// Writing 0 has no effect. -#define SSI_ICR_RORIC 0x00000001 -#define SSI_ICR_RORIC_BITN 0 -#define SSI_ICR_RORIC_M 0x00000001 -#define SSI_ICR_RORIC_S 0 - -//***************************************************************************** -// -// Register: SSI_O_DMACR -// -//***************************************************************************** -// Field: [1] TXDMAE -// -// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is -// enabled. -#define SSI_DMACR_TXDMAE 0x00000002 -#define SSI_DMACR_TXDMAE_BITN 1 -#define SSI_DMACR_TXDMAE_M 0x00000002 -#define SSI_DMACR_TXDMAE_S 1 - -// Field: [0] RXDMAE -// -// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is -// enabled. -#define SSI_DMACR_RXDMAE 0x00000001 -#define SSI_DMACR_RXDMAE_BITN 0 -#define SSI_DMACR_RXDMAE_M 0x00000001 -#define SSI_DMACR_RXDMAE_S 0 - - -#endif // __SSI__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h deleted file mode 100644 index 3fdb02f3c1d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_sysctl.h +++ /dev/null @@ -1,49 +0,0 @@ -/****************************************************************************** -* Filename: hw_sysctl.h -* Revised: 2015-03-16 14:43:45 +0100 (Mon, 16 Mar 2015) -* Revision: 42989 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_SYSCTL_H__ -#define __HW_SYSCTL_H__ - - -//***************************************************************************** -// -// The following are initial defines for the MCU clock -// -//***************************************************************************** -#define GET_MCU_CLOCK 48000000 - - -#endif // __HW_SYSCTL_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h deleted file mode 100644 index 44d4eb26d42..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_trng.h +++ /dev/null @@ -1,609 +0,0 @@ -/****************************************************************************** -* Filename: hw_trng_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_TRNG_H__ -#define __HW_TRNG_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// TRNG component -// -//***************************************************************************** -// Random Number Lower Word Readout Value -#define TRNG_O_OUT0 0x00000000 - -// Random Number Upper Word Readout Value -#define TRNG_O_OUT1 0x00000004 - -// Interrupt Status -#define TRNG_O_IRQFLAGSTAT 0x00000008 - -// Interrupt Mask -#define TRNG_O_IRQFLAGMASK 0x0000000C - -// Interrupt Flag Clear -#define TRNG_O_IRQFLAGCLR 0x00000010 - -// Control -#define TRNG_O_CTL 0x00000014 - -// Configuration 0 -#define TRNG_O_CFG0 0x00000018 - -// Alarm Control -#define TRNG_O_ALARMCNT 0x0000001C - -// FRO Enable -#define TRNG_O_FROEN 0x00000020 - -// FRO De-tune Bit -#define TRNG_O_FRODETUNE 0x00000024 - -// Alarm Event -#define TRNG_O_ALARMMASK 0x00000028 - -// Alarm Shutdown -#define TRNG_O_ALARMSTOP 0x0000002C - -// LFSR Readout Value -#define TRNG_O_LFSR0 0x00000030 - -// LFSR Readout Value -#define TRNG_O_LFSR1 0x00000034 - -// LFSR Readout Value -#define TRNG_O_LFSR2 0x00000038 - -// TRNG Engine Options Information -#define TRNG_O_HWOPT 0x00000078 - -// HW Version 0 -#define TRNG_O_HWVER0 0x0000007C - -// Interrupt Status After Masking -#define TRNG_O_IRQSTATMASK 0x00001FD8 - -// HW Version 1 -#define TRNG_O_HWVER1 0x00001FE0 - -// Interrupt Set -#define TRNG_O_IRQSET 0x00001FEC - -// SW Reset Control -#define TRNG_O_SWRESET 0x00001FF0 - -// Interrupt Status -#define TRNG_O_IRQSTAT 0x00001FF8 - -//***************************************************************************** -// -// Register: TRNG_O_OUT0 -// -//***************************************************************************** -// Field: [31:0] VALUE_31_0 -// -// LSW of 64- bit random value. New value ready when IRQFLAGSTAT.RDY = 1. -#define TRNG_OUT0_VALUE_31_0_W 32 -#define TRNG_OUT0_VALUE_31_0_M 0xFFFFFFFF -#define TRNG_OUT0_VALUE_31_0_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_OUT1 -// -//***************************************************************************** -// Field: [31:0] VALUE_63_32 -// -// MSW of 64-bit random value. New value ready when IRQFLAGSTAT.RDY = 1. -#define TRNG_OUT1_VALUE_63_32_W 32 -#define TRNG_OUT1_VALUE_63_32_M 0xFFFFFFFF -#define TRNG_OUT1_VALUE_63_32_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_IRQFLAGSTAT -// -//***************************************************************************** -// Field: [31] NEED_CLOCK -// -// 1: Indicates that the TRNG is busy generating entropy or is in one of its -// test modes - clocks may not be turned off and the power supply voltage must -// be kept stable. -// 0: TRNG is idle and can be shut down -#define TRNG_IRQFLAGSTAT_NEED_CLOCK 0x80000000 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_BITN 31 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_M 0x80000000 -#define TRNG_IRQFLAGSTAT_NEED_CLOCK_S 31 - -// Field: [1] SHUTDOWN_OVF -// -// 1: The number of FROs shut down (i.e. the number of '1' bits in the -// ALARMSTOP register) has exceeded the threshold set by ALARMCNT.SHUTDOWN_THR -// -// Writing '1' to IRQFLAGCLR.SHUTDOWN_OVF clears this bit to '0' again. -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGSTAT_SHUTDOWN_OVF_S 1 - -// Field: [0] RDY -// -// 1: Data are available in OUT0 and OUT1. -// -// Acknowledging this state by writing '1' to IRQFLAGCLR.RDY clears this bit to -// '0'. -// If a new number is already available in the internal register of the TRNG, -// the number is directly clocked into the result register. In this case the -// status bit is asserted again, after one clock cycle. -#define TRNG_IRQFLAGSTAT_RDY 0x00000001 -#define TRNG_IRQFLAGSTAT_RDY_BITN 0 -#define TRNG_IRQFLAGSTAT_RDY_M 0x00000001 -#define TRNG_IRQFLAGSTAT_RDY_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_IRQFLAGMASK -// -//***************************************************************************** -// Field: [1] SHUTDOWN_OVF -// -// 1: Allow IRQFLAGSTAT.SHUTDOWN_OVF to activate the interrupt from this -// module. -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGMASK_SHUTDOWN_OVF_S 1 - -// Field: [0] RDY -// -// 1: Allow IRQFLAGSTAT.RDY to activate the interrupt from this module. -#define TRNG_IRQFLAGMASK_RDY 0x00000001 -#define TRNG_IRQFLAGMASK_RDY_BITN 0 -#define TRNG_IRQFLAGMASK_RDY_M 0x00000001 -#define TRNG_IRQFLAGMASK_RDY_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_IRQFLAGCLR -// -//***************************************************************************** -// Field: [1] SHUTDOWN_OVF -// -// 1: Clear IRQFLAGSTAT.SHUTDOWN_OVF. -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQFLAGCLR_SHUTDOWN_OVF_S 1 - -// Field: [0] RDY -// -// 1: Clear IRQFLAGSTAT.RDY. -#define TRNG_IRQFLAGCLR_RDY 0x00000001 -#define TRNG_IRQFLAGCLR_RDY_BITN 0 -#define TRNG_IRQFLAGCLR_RDY_M 0x00000001 -#define TRNG_IRQFLAGCLR_RDY_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_CTL -// -//***************************************************************************** -// Field: [31:16] STARTUP_CYCLES -// -// This field determines the number of samples (between 2^8 and 2^24) taken to -// gather entropy from the FROs during startup. If the written value of this -// field is zero, the number of samples is 2^24, otherwise the number of -// samples equals the written value times 2^8. -// -// 0x0000: 2^24 samples -// 0x0001: 1*2^8 samples -// 0x0002: 2*2^8 samples -// 0x0003: 3*2^8 samples -// ... -// 0x8000: 32768*2^8 samples -// 0xC000: 49152*2^8 samples -// ... -// 0xFFFF: 65535*2^8 samples -// -// This field can only be modified while TRNG_EN is 0. If 1 an update will be -// ignored. -#define TRNG_CTL_STARTUP_CYCLES_W 16 -#define TRNG_CTL_STARTUP_CYCLES_M 0xFFFF0000 -#define TRNG_CTL_STARTUP_CYCLES_S 16 - -// Field: [10] TRNG_EN -// -// 0: Forces all TRNG logic back into the idle state immediately. -// 1: Starts TRNG, gathering entropy from the FROs for the number of samples -// determined by STARTUP_CYCLES. -#define TRNG_CTL_TRNG_EN 0x00000400 -#define TRNG_CTL_TRNG_EN_BITN 10 -#define TRNG_CTL_TRNG_EN_M 0x00000400 -#define TRNG_CTL_TRNG_EN_S 10 - -// Field: [2] NO_LFSR_FB -// -// 1: Remove XNOR feedback from the main LFSR, converting it into a normal -// shift register for the XOR-ed outputs of the FROs (shifting data in on the -// LSB side). A '1' also forces the LFSR to sample continuously. -// -// This bit can only be set to '1' when TEST_MODE is also set to '1' and should -// not be used for other than test purposes -#define TRNG_CTL_NO_LFSR_FB 0x00000004 -#define TRNG_CTL_NO_LFSR_FB_BITN 2 -#define TRNG_CTL_NO_LFSR_FB_M 0x00000004 -#define TRNG_CTL_NO_LFSR_FB_S 2 - -// Field: [1] TEST_MODE -// -// 1: Enables access to the TESTCNT and LFSR0/LFSR1/LFSR2 registers (the latter -// are automatically cleared before enabling access) and keeps -// IRQFLAGSTAT.NEED_CLOCK at '1'. -// -// This bit shall not be used unless you need to change the LFSR seed prior to -// creating a new random value. All other testing is done external to register -// control. -#define TRNG_CTL_TEST_MODE 0x00000002 -#define TRNG_CTL_TEST_MODE_BITN 1 -#define TRNG_CTL_TEST_MODE_M 0x00000002 -#define TRNG_CTL_TEST_MODE_S 1 - -//***************************************************************************** -// -// Register: TRNG_O_CFG0 -// -//***************************************************************************** -// Field: [31:16] MAX_REFILL_CYCLES -// -// This field determines the maximum number of samples (between 2^8 and 2^24) -// taken to re-generate entropy from the FROs after reading out a 64 bits -// random number. If the written value of this field is zero, the number of -// samples is 2^24, otherwise the number of samples equals the written value -// times 2^8. -// -// 0x0000: 2^24 samples -// 0x0001: 1*2^8 samples -// 0x0002: 2*2^8 samples -// 0x0003: 3*2^8 samples -// ... -// 0x8000: 32768*2^8 samples -// 0xC000: 49152*2^8 samples -// ... -// 0xFFFF: 65535*2^8 samples -// -// This field can only be modified while CTL.TRNG_EN is 0. -#define TRNG_CFG0_MAX_REFILL_CYCLES_W 16 -#define TRNG_CFG0_MAX_REFILL_CYCLES_M 0xFFFF0000 -#define TRNG_CFG0_MAX_REFILL_CYCLES_S 16 - -// Field: [11:8] SMPL_DIV -// -// This field directly controls the number of clock cycles between samples -// taken from the FROs. Default value 0 indicates that samples are taken every -// clock cycle, -// maximum value 0xF takes one sample every 16 clock cycles. -// This field must be set to a value such that the slowest FRO (even under -// worst-case -// conditions) has a cycle time less than twice the sample period. -// -// This field can only be modified while CTL.TRNG_EN is '0'. -#define TRNG_CFG0_SMPL_DIV_W 4 -#define TRNG_CFG0_SMPL_DIV_M 0x00000F00 -#define TRNG_CFG0_SMPL_DIV_S 8 - -// Field: [7:0] MIN_REFILL_CYCLES -// -// This field determines the minimum number of samples (between 2^6 and 2^14) -// taken to re-generate entropy from the FROs after reading out a 64 bits -// random number. If the value of this field is zero, the number of samples is -// fixed to the value determined by the MAX_REFILL_CYCLES field, otherwise the -// minimum number of samples equals the written value times 64 (which can be up -// to 2^14). To ensure same entropy in all generated random numbers the value 0 -// should be used. Then MAX_REFILL_CYCLES controls the minimum refill interval. -// The number of samples defined here cannot be higher than the number defined -// by the 'max_refill_cycles' field (i.e. that field takes precedence). No -// random value will be created if min refill > max refill. -// -// This field can only be modified while CTL.TRNG_EN = 0. -// -// 0x00: Minimum samples = MAX_REFILL_CYCLES (all numbers have same entropy) -// 0x01: 1*2^6 samples -// 0x02: 2*2^6 samples -// ... -// 0xFF: 255*2^6 samples -#define TRNG_CFG0_MIN_REFILL_CYCLES_W 8 -#define TRNG_CFG0_MIN_REFILL_CYCLES_M 0x000000FF -#define TRNG_CFG0_MIN_REFILL_CYCLES_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_ALARMCNT -// -//***************************************************************************** -// Field: [29:24] SHUTDOWN_CNT -// -// Read-only, indicates the number of '1' bits in ALARMSTOP register. -// The maximum value equals the number of FROs. -#define TRNG_ALARMCNT_SHUTDOWN_CNT_W 6 -#define TRNG_ALARMCNT_SHUTDOWN_CNT_M 0x3F000000 -#define TRNG_ALARMCNT_SHUTDOWN_CNT_S 24 - -// Field: [20:16] SHUTDOWN_THR -// -// Threshold setting for generating IRQFLAGSTAT.SHUTDOWN_OVF interrupt. The -// interrupt is triggered when SHUTDOWN_CNT value exceeds this bit field. -#define TRNG_ALARMCNT_SHUTDOWN_THR_W 5 -#define TRNG_ALARMCNT_SHUTDOWN_THR_M 0x001F0000 -#define TRNG_ALARMCNT_SHUTDOWN_THR_S 16 - -// Field: [7:0] ALARM_THR -// -// Alarm detection threshold for the repeating pattern detectors on each FRO. -// An FRO 'alarm event' is declared when a repeating pattern (of up to four -// samples length) is detected continuously for the number of samples defined -// by this field's value. Reset value 0xFF should keep the number of 'alarm -// events' to a manageable level. -#define TRNG_ALARMCNT_ALARM_THR_W 8 -#define TRNG_ALARMCNT_ALARM_THR_M 0x000000FF -#define TRNG_ALARMCNT_ALARM_THR_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_FROEN -// -//***************************************************************************** -// Field: [23:0] FRO_MASK -// -// Enable bits for the individual FROs. A '1' in bit [n] enables FRO 'n'. -// Default state is all '1's to enable all FROs after power-up. Note that they -// are not actually started up before the CTL.TRNG_EN bit is set to '1'. -// -// Bits are automatically forced to '0' here (and cannot be written to '1') -// while the corresponding bit in ALARMSTOP.FRO_FLAGS has value '1'. -#define TRNG_FROEN_FRO_MASK_W 24 -#define TRNG_FROEN_FRO_MASK_M 0x00FFFFFF -#define TRNG_FROEN_FRO_MASK_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_FRODETUNE -// -//***************************************************************************** -// Field: [23:0] FRO_MASK -// -// De-tune bits for the individual FROs. A '1' in bit [n] lets FRO 'n' run -// approximately 5% faster. The value of one of these bits may only be changed -// while the corresponding FRO is turned off (by temporarily writing a '0' in -// the corresponding -// bit of the FROEN.FRO_MASK register). -#define TRNG_FRODETUNE_FRO_MASK_W 24 -#define TRNG_FRODETUNE_FRO_MASK_M 0x00FFFFFF -#define TRNG_FRODETUNE_FRO_MASK_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_ALARMMASK -// -//***************************************************************************** -// Field: [23:0] FRO_MASK -// -// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] -// indicates FRO 'n' experienced an 'alarm event'. -#define TRNG_ALARMMASK_FRO_MASK_W 24 -#define TRNG_ALARMMASK_FRO_MASK_M 0x00FFFFFF -#define TRNG_ALARMMASK_FRO_MASK_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_ALARMSTOP -// -//***************************************************************************** -// Field: [23:0] FRO_FLAGS -// -// Logging bits for the 'alarm events' of individual FROs. A '1' in bit [n] -// indicates FRO 'n' experienced more than one 'alarm event' in quick -// succession and has been turned off. A '1' in this field forces the -// corresponding bit in FROEN.FRO_MASK to '0'. -#define TRNG_ALARMSTOP_FRO_FLAGS_W 24 -#define TRNG_ALARMSTOP_FRO_FLAGS_M 0x00FFFFFF -#define TRNG_ALARMSTOP_FRO_FLAGS_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_LFSR0 -// -//***************************************************************************** -// Field: [31:0] LFSR_31_0 -// -// Bits [31:0] of the main entropy accumulation LFSR. Register can only be -// accessed when CTL.TEST_MODE = 1. -// Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR0_LFSR_31_0_W 32 -#define TRNG_LFSR0_LFSR_31_0_M 0xFFFFFFFF -#define TRNG_LFSR0_LFSR_31_0_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_LFSR1 -// -//***************************************************************************** -// Field: [31:0] LFSR_63_32 -// -// Bits [63:32] of the main entropy accumulation LFSR. Register can only be -// accessed when CTL.TEST_MODE = 1. -// Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR1_LFSR_63_32_W 32 -#define TRNG_LFSR1_LFSR_63_32_M 0xFFFFFFFF -#define TRNG_LFSR1_LFSR_63_32_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_LFSR2 -// -//***************************************************************************** -// Field: [16:0] LFSR_80_64 -// -// Bits [80:64] of the main entropy accumulation LFSR. Register can only be -// accessed when CTL.TEST_MODE = 1. -// Register contents will be cleared to zero before access is enabled. -#define TRNG_LFSR2_LFSR_80_64_W 17 -#define TRNG_LFSR2_LFSR_80_64_M 0x0001FFFF -#define TRNG_LFSR2_LFSR_80_64_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_HWOPT -// -//***************************************************************************** -// Field: [11:6] NR_OF_FROS -// -// Number of FROs implemented in this TRNG, value 24 (decimal). -#define TRNG_HWOPT_NR_OF_FROS_W 6 -#define TRNG_HWOPT_NR_OF_FROS_M 0x00000FC0 -#define TRNG_HWOPT_NR_OF_FROS_S 6 - -//***************************************************************************** -// -// Register: TRNG_O_HWVER0 -// -//***************************************************************************** -// Field: [27:24] HW_MAJOR_VER -// -// 4 bits binary encoding of the major hardware revision number. -#define TRNG_HWVER0_HW_MAJOR_VER_W 4 -#define TRNG_HWVER0_HW_MAJOR_VER_M 0x0F000000 -#define TRNG_HWVER0_HW_MAJOR_VER_S 24 - -// Field: [23:20] HW_MINOR_VER -// -// 4 bits binary encoding of the minor hardware revision number. -#define TRNG_HWVER0_HW_MINOR_VER_W 4 -#define TRNG_HWVER0_HW_MINOR_VER_M 0x00F00000 -#define TRNG_HWVER0_HW_MINOR_VER_S 20 - -// Field: [19:16] HW_PATCH_LVL -// -// 4 bits binary encoding of the hardware patch level, initial release will -// carry value zero. -#define TRNG_HWVER0_HW_PATCH_LVL_W 4 -#define TRNG_HWVER0_HW_PATCH_LVL_M 0x000F0000 -#define TRNG_HWVER0_HW_PATCH_LVL_S 16 - -// Field: [15:8] EIP_NUM_COMPL -// -// Bit-by-bit logic complement of bits [7:0]. This TRNG gives 0xB4. -#define TRNG_HWVER0_EIP_NUM_COMPL_W 8 -#define TRNG_HWVER0_EIP_NUM_COMPL_M 0x0000FF00 -#define TRNG_HWVER0_EIP_NUM_COMPL_S 8 - -// Field: [7:0] EIP_NUM -// -// 8 bits binary encoding of the module number. This TRNG gives 0x4B. -#define TRNG_HWVER0_EIP_NUM_W 8 -#define TRNG_HWVER0_EIP_NUM_M 0x000000FF -#define TRNG_HWVER0_EIP_NUM_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_IRQSTATMASK -// -//***************************************************************************** -// Field: [1] SHUTDOWN_OVF -// -// Shutdown Overflow (result of IRQFLAGSTAT.SHUTDOWN_OVF AND'ed with -// IRQFLAGMASK.SHUTDOWN_OVF) -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF 0x00000002 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_BITN 1 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_M 0x00000002 -#define TRNG_IRQSTATMASK_SHUTDOWN_OVF_S 1 - -// Field: [0] RDY -// -// New random value available (result of IRQFLAGSTAT.RDY AND'ed with -// IRQFLAGMASK.RDY) -#define TRNG_IRQSTATMASK_RDY 0x00000001 -#define TRNG_IRQSTATMASK_RDY_BITN 0 -#define TRNG_IRQSTATMASK_RDY_M 0x00000001 -#define TRNG_IRQSTATMASK_RDY_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_HWVER1 -// -//***************************************************************************** -// Field: [7:0] REV -// -// The revision number of this module is Rev 2.0. -#define TRNG_HWVER1_REV_W 8 -#define TRNG_HWVER1_REV_M 0x000000FF -#define TRNG_HWVER1_REV_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_IRQSET -// -//***************************************************************************** -//***************************************************************************** -// -// Register: TRNG_O_SWRESET -// -//***************************************************************************** -// Field: [0] RESET -// -// Write '1' to soft reset , reset will be low for 4-5 clock cycles. Poll to 0 -// for reset to be completed. -#define TRNG_SWRESET_RESET 0x00000001 -#define TRNG_SWRESET_RESET_BITN 0 -#define TRNG_SWRESET_RESET_M 0x00000001 -#define TRNG_SWRESET_RESET_S 0 - -//***************************************************************************** -// -// Register: TRNG_O_IRQSTAT -// -//***************************************************************************** -// Field: [0] STAT -// -// TRNG Interrupt status. OR'ed version of IRQFLAGSTAT.SHUTDOWN_OVF and -// IRQFLAGSTAT.RDY -#define TRNG_IRQSTAT_STAT 0x00000001 -#define TRNG_IRQSTAT_STAT_BITN 0 -#define TRNG_IRQSTAT_STAT_M 0x00000001 -#define TRNG_IRQSTAT_STAT_S 0 - - -#endif // __TRNG__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h deleted file mode 100644 index 3f6fe142270..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_types.h +++ /dev/null @@ -1,123 +0,0 @@ -/****************************************************************************** -* Filename: hw_types.h -* Revised: 2016-09-13 14:21:40 +0200 (Tue, 13 Sep 2016) -* Revision: 47152 -* -* Description: Common types and macros. -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -#include -#include -#include "../inc/hw_chip_def.h" - -//***************************************************************************** -// -// Common driverlib types -// -//***************************************************************************** -typedef void (* FPTR_VOID_VOID_T) (void); -typedef void (* FPTR_VOID_UINT8_T) (uint8_t); - -//***************************************************************************** -// -// This symbol forces simple driverlib functions to be inlined in the code -// instead of using function calls. -// -//***************************************************************************** -#ifndef __STATIC_INLINE -#define __STATIC_INLINE static inline -#endif - -//***************************************************************************** -// -// C99 types only allows bitfield defintions on certain datatypes. -// -//***************************************************************************** -typedef unsigned int __UINT32; - -//***************************************************************************** -// -// Macros for direct hardware access. -// -// If using these macros the programmer should be aware of any limitations to -// the address accessed i.e. if it supports word and/or byte access. -// -//***************************************************************************** -// Word (32 bit) access to address x -// Read example : my32BitVar = HWREG(base_addr + offset) ; -// Write example : HWREG(base_addr + offset) = my32BitVar ; -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) - -// Half word (16 bit) access to address x -// Read example : my16BitVar = HWREGH(base_addr + offset) ; -// Write example : HWREGH(base_addr + offset) = my16BitVar ; -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) - -// Byte (8 bit) access to address x -// Read example : my8BitVar = HWREGB(base_addr + offset) ; -// Write example : HWREGB(base_addr + offset) = my8BitVar ; -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) - -//***************************************************************************** -// -// Macros for hardware access to bit-band supported addresses via the bit-band region. -// -// Macros calculate the corresponding address to access in the bit-band region -// based on the actual address of the memory/register and the bit number. -// -// Do NOT use these macros to access the bit-band region directly! -// -//***************************************************************************** -// Bit-band access to address x bit number b using word access (32 bit) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -// Bit-band access to address x bit number b using half word access (16 bit) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - -// Bit-band access to address x bit number b using byte access (8 bit) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - - -#endif // __HW_TYPES_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h deleted file mode 100644 index b35541fb856..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_uart.h +++ /dev/null @@ -1,1087 +0,0 @@ -/****************************************************************************** -* Filename: hw_uart_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// UART component -// -//***************************************************************************** -// Data -#define UART_O_DR 0x00000000 - -// Status -#define UART_O_RSR 0x00000004 - -// Error Clear -#define UART_O_ECR 0x00000004 - -// Flag -#define UART_O_FR 0x00000018 - -// Integer Baud-Rate Divisor -#define UART_O_IBRD 0x00000024 - -// Fractional Baud-Rate Divisor -#define UART_O_FBRD 0x00000028 - -// Line Control -#define UART_O_LCRH 0x0000002C - -// Control -#define UART_O_CTL 0x00000030 - -// Interrupt FIFO Level Select -#define UART_O_IFLS 0x00000034 - -// Interrupt Mask Set/Clear -#define UART_O_IMSC 0x00000038 - -// Raw Interrupt Status -#define UART_O_RIS 0x0000003C - -// Masked Interrupt Status -#define UART_O_MIS 0x00000040 - -// Interrupt Clear -#define UART_O_ICR 0x00000044 - -// DMA Control -#define UART_O_DMACTL 0x00000048 - -//***************************************************************************** -// -// Register: UART_O_DR -// -//***************************************************************************** -// Field: [11] OE -// -// UART Overrun Error: -// This bit is set to 1 if data is received and the receive FIFO is already -// full. The FIFO contents remain valid because no more data is written when -// the FIFO is full, , only the contents of the shift register are overwritten. -// This is cleared to 0 once there is an empty space in the FIFO and a new -// character can be written to it. -#define UART_DR_OE 0x00000800 -#define UART_DR_OE_BITN 11 -#define UART_DR_OE_M 0x00000800 -#define UART_DR_OE_S 11 - -// Field: [10] BE -// -// UART Break Error: -// This bit is set to 1 if a break condition was detected, indicating that the -// received data input (UARTRXD input pin) was held LOW for longer than a -// full-word transmission time (defined as start, data, parity and stop bits). -// In FIFO mode, this error is associated with the character at the top of the -// FIFO (that is., the oldest received data character since last read). When a -// break occurs, a 0 character is loaded into the FIFO. The next character is -// enabled after the receive data input (UARTRXD input pin) goes to a 1 -// (marking state), and the next valid start bit is received. -#define UART_DR_BE 0x00000400 -#define UART_DR_BE_BITN 10 -#define UART_DR_BE_M 0x00000400 -#define UART_DR_BE_S 10 - -// Field: [9] PE -// -// UART Parity Error: -// When set to 1, it indicates that the parity of the received data character -// does not match the parity that the LCRH.EPS and LCRH.SPS select. -// In FIFO mode, this error is associated with the character at the top of the -// FIFO (that is, the oldest received data character since last read). -#define UART_DR_PE 0x00000200 -#define UART_DR_PE_BITN 9 -#define UART_DR_PE_M 0x00000200 -#define UART_DR_PE_S 9 - -// Field: [8] FE -// -// UART Framing Error: -// When set to 1, it indicates that the received character did not have a valid -// stop bit (a valid stop bit is 1). -// In FIFO mode, this error is associated with the character at the top of the -// FIFO (that is., the oldest received data character since last read). -#define UART_DR_FE 0x00000100 -#define UART_DR_FE_BITN 8 -#define UART_DR_FE_M 0x00000100 -#define UART_DR_FE_S 8 - -// Field: [7:0] DATA -// -// Data transmitted or received: -// On writes, the transmit data character is pushed into the FIFO. -// On reads, the oldest received data character since the last read is -// returned. -#define UART_DR_DATA_W 8 -#define UART_DR_DATA_M 0x000000FF -#define UART_DR_DATA_S 0 - -//***************************************************************************** -// -// Register: UART_O_RSR -// -//***************************************************************************** -// Field: [3] OE -// -// UART Overrun Error: -// This bit is set to 1 if data is received and the receive FIFO is already -// full. The FIFO contents remain valid because no more data is written when -// the FIFO is full, , only the contents of the shift register are overwritten. -// This is cleared to 0 once there is an empty space in the FIFO and a new -// character can be written to it. -#define UART_RSR_OE 0x00000008 -#define UART_RSR_OE_BITN 3 -#define UART_RSR_OE_M 0x00000008 -#define UART_RSR_OE_S 3 - -// Field: [2] BE -// -// UART Break Error: -// This bit is set to 1 if a break condition was detected, indicating that the -// received data input (UARTRXD input pin) was held LOW for longer than a -// full-word transmission time (defined as start, data, parity and stop bits). -// When a break occurs, a 0 character is loaded into the FIFO. The next -// character is enabled after the receive data input (UARTRXD input pin) goes -// to a 1 (marking state), and the next valid start bit is received. -#define UART_RSR_BE 0x00000004 -#define UART_RSR_BE_BITN 2 -#define UART_RSR_BE_M 0x00000004 -#define UART_RSR_BE_S 2 - -// Field: [1] PE -// -// UART Parity Error: -// When set to 1, it indicates that the parity of the received data character -// does not match the parity that the LCRH.EPS and LCRH.SPS select. -#define UART_RSR_PE 0x00000002 -#define UART_RSR_PE_BITN 1 -#define UART_RSR_PE_M 0x00000002 -#define UART_RSR_PE_S 1 - -// Field: [0] FE -// -// UART Framing Error: -// When set to 1, it indicates that the received character did not have a valid -// stop bit (a valid stop bit is 1). -#define UART_RSR_FE 0x00000001 -#define UART_RSR_FE_BITN 0 -#define UART_RSR_FE_M 0x00000001 -#define UART_RSR_FE_S 0 - -//***************************************************************************** -// -// Register: UART_O_ECR -// -//***************************************************************************** -// Field: [3] OE -// -// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are -// cleared to 0 by any write to this register. -#define UART_ECR_OE 0x00000008 -#define UART_ECR_OE_BITN 3 -#define UART_ECR_OE_M 0x00000008 -#define UART_ECR_OE_S 3 - -// Field: [2] BE -// -// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are -// cleared to 0 by any write to this register. -#define UART_ECR_BE 0x00000004 -#define UART_ECR_BE_BITN 2 -#define UART_ECR_BE_M 0x00000004 -#define UART_ECR_BE_S 2 - -// Field: [1] PE -// -// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are -// cleared to 0 by any write to this register. -#define UART_ECR_PE 0x00000002 -#define UART_ECR_PE_BITN 1 -#define UART_ECR_PE_M 0x00000002 -#define UART_ECR_PE_S 1 - -// Field: [0] FE -// -// The framing (FE), parity (PE), break (BE) and overrun (OE) errors are -// cleared to 0 by any write to this register. -#define UART_ECR_FE 0x00000001 -#define UART_ECR_FE_BITN 0 -#define UART_ECR_FE_M 0x00000001 -#define UART_ECR_FE_S 0 - -//***************************************************************************** -// -// Register: UART_O_FR -// -//***************************************************************************** -// Field: [7] TXFE -// -// UART Transmit FIFO Empty: -// The meaning of this bit depends on the state of LCRH.FEN . -// - If the FIFO is disabled, this bit is set when the transmit holding -// register is empty. -// - If the FIFO is enabled, this bit is set when the transmit FIFO is empty. -// This bit does not indicate if there is data in the transmit shift register. -#define UART_FR_TXFE 0x00000080 -#define UART_FR_TXFE_BITN 7 -#define UART_FR_TXFE_M 0x00000080 -#define UART_FR_TXFE_S 7 - -// Field: [6] RXFF -// -// UART Receive FIFO Full: -// The meaning of this bit depends on the state of LCRH.FEN. -// - If the FIFO is disabled, this bit is set when the receive holding -// register is full. -// - If the FIFO is enabled, this bit is set when the receive FIFO is full. -#define UART_FR_RXFF 0x00000040 -#define UART_FR_RXFF_BITN 6 -#define UART_FR_RXFF_M 0x00000040 -#define UART_FR_RXFF_S 6 - -// Field: [5] TXFF -// -// UART Transmit FIFO Full: -// Transmit FIFO full. The meaning of this bit depends on the state of -// LCRH.FEN. -// - If the FIFO is disabled, this bit is set when the transmit holding -// register is full. -// - If the FIFO is enabled, this bit is set when the transmit FIFO is full. -#define UART_FR_TXFF 0x00000020 -#define UART_FR_TXFF_BITN 5 -#define UART_FR_TXFF_M 0x00000020 -#define UART_FR_TXFF_S 5 - -// Field: [4] RXFE -// -// UART Receive FIFO Empty: -// Receive FIFO empty. The meaning of this bit depends on the state of -// LCRH.FEN. -// - If the FIFO is disabled, this bit is set when the receive holding -// register is empty. -// - If the FIFO is enabled, this bit is set when the receive FIFO is empty. -#define UART_FR_RXFE 0x00000010 -#define UART_FR_RXFE_BITN 4 -#define UART_FR_RXFE_M 0x00000010 -#define UART_FR_RXFE_S 4 - -// Field: [3] BUSY -// -// UART Busy: -// If this bit is set to 1, the UART is busy transmitting data. This bit -// remains set until the complete byte, including all the stop bits, has been -// sent from the shift register. -// This bit is set as soon as the transmit FIFO becomes non-empty, regardless -// of whether the UART is enabled or not. -#define UART_FR_BUSY 0x00000008 -#define UART_FR_BUSY_BITN 3 -#define UART_FR_BUSY_M 0x00000008 -#define UART_FR_BUSY_S 3 - -// Field: [0] CTS -// -// Clear To Send: -// This bit is the complement of the active-low UART CTS input pin. -// That is, the bit is 1 when CTS input pin is LOW. -#define UART_FR_CTS 0x00000001 -#define UART_FR_CTS_BITN 0 -#define UART_FR_CTS_M 0x00000001 -#define UART_FR_CTS_S 0 - -//***************************************************************************** -// -// Register: UART_O_IBRD -// -//***************************************************************************** -// Field: [15:0] DIVINT -// -// The integer baud rate divisor: -// The baud rate divisor is calculated using the formula below: -// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) -// Baud rate divisor must be minimum 1 and maximum 65535. -// That is, DIVINT=0 does not give a valid baud rate. -// Similarly, if DIVINT=0xFFFF, any non-zero values in FBRD.DIVFRAC will be -// illegal. -// A valid value must be written to this field before the UART can be used for -// RX or TX operations. -#define UART_IBRD_DIVINT_W 16 -#define UART_IBRD_DIVINT_M 0x0000FFFF -#define UART_IBRD_DIVINT_S 0 - -//***************************************************************************** -// -// Register: UART_O_FBRD -// -//***************************************************************************** -// Field: [5:0] DIVFRAC -// -// Fractional Baud-Rate Divisor: -// The baud rate divisor is calculated using the formula below: -// Baud rate divisor = (UART reference clock frequency) / (16 * Baud rate) -// Baud rate divisor must be minimum 1 and maximum 65535. -// That is, IBRD.DIVINT=0 does not give a valid baud rate. -// Similarly, if IBRD.DIVINT=0xFFFF, any non-zero values in DIVFRAC will be -// illegal. -// A valid value must be written to this field before the UART can be used for -// RX or TX operations. -#define UART_FBRD_DIVFRAC_W 6 -#define UART_FBRD_DIVFRAC_M 0x0000003F -#define UART_FBRD_DIVFRAC_S 0 - -//***************************************************************************** -// -// Register: UART_O_LCRH -// -//***************************************************************************** -// Field: [7] SPS -// -// UART Stick Parity Select: -// -// 0: Stick parity is disabled -// 1: The parity bit is transmitted and checked as invert of EPS field (i.e. -// the parity bit is transmitted and checked as 1 when EPS = 0). -// -// This bit has no effect when PEN disables parity checking and generation. -#define UART_LCRH_SPS 0x00000080 -#define UART_LCRH_SPS_BITN 7 -#define UART_LCRH_SPS_M 0x00000080 -#define UART_LCRH_SPS_S 7 - -// Field: [6:5] WLEN -// -// UART Word Length: -// These bits indicate the number of data bits transmitted or received in a -// frame. -// ENUMs: -// 8 Word Length 8 bits -// 7 Word Length 7 bits -// 6 Word Length 6 bits -// 5 Word Length 5 bits -#define UART_LCRH_WLEN_W 2 -#define UART_LCRH_WLEN_M 0x00000060 -#define UART_LCRH_WLEN_S 5 -#define UART_LCRH_WLEN_8 0x00000060 -#define UART_LCRH_WLEN_7 0x00000040 -#define UART_LCRH_WLEN_6 0x00000020 -#define UART_LCRH_WLEN_5 0x00000000 - -// Field: [4] FEN -// -// UART Enable FIFOs -// ENUMs: -// EN Transmit and receive FIFO buffers are enabled -// (FIFO mode) -// DIS FIFOs are disabled (character mode) that is, the -// FIFOs become 1-byte-deep holding registers. -#define UART_LCRH_FEN 0x00000010 -#define UART_LCRH_FEN_BITN 4 -#define UART_LCRH_FEN_M 0x00000010 -#define UART_LCRH_FEN_S 4 -#define UART_LCRH_FEN_EN 0x00000010 -#define UART_LCRH_FEN_DIS 0x00000000 - -// Field: [3] STP2 -// -// UART Two Stop Bits Select: -// If this bit is set to 1, two stop bits are transmitted at the end of the -// frame. The receive logic does not check for two stop bits being received. -#define UART_LCRH_STP2 0x00000008 -#define UART_LCRH_STP2_BITN 3 -#define UART_LCRH_STP2_M 0x00000008 -#define UART_LCRH_STP2_S 3 - -// Field: [2] EPS -// -// UART Even Parity Select -// ENUMs: -// EVEN Even parity: The UART generates or checks for an -// even number of 1s in the data and parity bits. -// ODD Odd parity: The UART generates or checks for an -// odd number of 1s in the data and parity bits. -#define UART_LCRH_EPS 0x00000004 -#define UART_LCRH_EPS_BITN 2 -#define UART_LCRH_EPS_M 0x00000004 -#define UART_LCRH_EPS_S 2 -#define UART_LCRH_EPS_EVEN 0x00000004 -#define UART_LCRH_EPS_ODD 0x00000000 - -// Field: [1] PEN -// -// UART Parity Enable -// This bit controls generation and checking of parity bit. -// ENUMs: -// EN Parity checking and generation is enabled. -// DIS Parity is disabled and no parity bit is added to -// the data frame -#define UART_LCRH_PEN 0x00000002 -#define UART_LCRH_PEN_BITN 1 -#define UART_LCRH_PEN_M 0x00000002 -#define UART_LCRH_PEN_S 1 -#define UART_LCRH_PEN_EN 0x00000002 -#define UART_LCRH_PEN_DIS 0x00000000 - -// Field: [0] BRK -// -// UART Send Break -// If this bit is set to 1, a low-level is continually output on the UARTTXD -// output pin, after completing transmission of the current character. For the -// proper execution of the break command, the -// software must set this bit for at least two complete frames. For normal use, -// this bit must be cleared to 0. -#define UART_LCRH_BRK 0x00000001 -#define UART_LCRH_BRK_BITN 0 -#define UART_LCRH_BRK_M 0x00000001 -#define UART_LCRH_BRK_S 0 - -//***************************************************************************** -// -// Register: UART_O_CTL -// -//***************************************************************************** -// Field: [15] CTSEN -// -// CTS hardware flow control enable -// ENUMs: -// EN CTS hardware flow control enabled -// DIS CTS hardware flow control disabled -#define UART_CTL_CTSEN 0x00008000 -#define UART_CTL_CTSEN_BITN 15 -#define UART_CTL_CTSEN_M 0x00008000 -#define UART_CTL_CTSEN_S 15 -#define UART_CTL_CTSEN_EN 0x00008000 -#define UART_CTL_CTSEN_DIS 0x00000000 - -// Field: [14] RTSEN -// -// RTS hardware flow control enable -// ENUMs: -// EN RTS hardware flow control enabled -// DIS RTS hardware flow control disabled -#define UART_CTL_RTSEN 0x00004000 -#define UART_CTL_RTSEN_BITN 14 -#define UART_CTL_RTSEN_M 0x00004000 -#define UART_CTL_RTSEN_S 14 -#define UART_CTL_RTSEN_EN 0x00004000 -#define UART_CTL_RTSEN_DIS 0x00000000 - -// Field: [11] RTS -// -// Request to Send -// This bit is the complement of the active-low UART RTS output. That is, when -// the bit is programmed to a 1 then RTS output on the pins is LOW. -#define UART_CTL_RTS 0x00000800 -#define UART_CTL_RTS_BITN 11 -#define UART_CTL_RTS_M 0x00000800 -#define UART_CTL_RTS_S 11 - -// Field: [9] RXE -// -// UART Receive Enable -// If the UART is disabled in the middle of reception, it completes the current -// character before stopping. -// ENUMs: -// EN UART Receive enabled -// DIS UART Receive disabled -#define UART_CTL_RXE 0x00000200 -#define UART_CTL_RXE_BITN 9 -#define UART_CTL_RXE_M 0x00000200 -#define UART_CTL_RXE_S 9 -#define UART_CTL_RXE_EN 0x00000200 -#define UART_CTL_RXE_DIS 0x00000000 - -// Field: [8] TXE -// -// UART Transmit Enable -// If the UART is disabled in the middle of transmission, it completes the -// current character before stopping. -// ENUMs: -// EN UART Transmit enabled -// DIS UART Transmit disabled -#define UART_CTL_TXE 0x00000100 -#define UART_CTL_TXE_BITN 8 -#define UART_CTL_TXE_M 0x00000100 -#define UART_CTL_TXE_S 8 -#define UART_CTL_TXE_EN 0x00000100 -#define UART_CTL_TXE_DIS 0x00000000 - -// Field: [7] LBE -// -// UART Loop Back Enable: -// Enabling the loop-back mode connects the UARTTXD output from the UART to -// UARTRXD input of the UART. -// ENUMs: -// EN Loop Back enabled -// DIS Loop Back disabled -#define UART_CTL_LBE 0x00000080 -#define UART_CTL_LBE_BITN 7 -#define UART_CTL_LBE_M 0x00000080 -#define UART_CTL_LBE_S 7 -#define UART_CTL_LBE_EN 0x00000080 -#define UART_CTL_LBE_DIS 0x00000000 - -// Field: [0] UARTEN -// -// UART Enable -// ENUMs: -// EN UART enabled -// DIS UART disabled -#define UART_CTL_UARTEN 0x00000001 -#define UART_CTL_UARTEN_BITN 0 -#define UART_CTL_UARTEN_M 0x00000001 -#define UART_CTL_UARTEN_S 0 -#define UART_CTL_UARTEN_EN 0x00000001 -#define UART_CTL_UARTEN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: UART_O_IFLS -// -//***************************************************************************** -// Field: [5:3] RXSEL -// -// Receive interrupt FIFO level select: -// This field sets the trigger points for the receive interrupt. Values -// 0b101-0b111 are reserved. -// ENUMs: -// 7_8 Receive FIFO becomes >= 7/8 full -// 6_8 Receive FIFO becomes >= 3/4 full -// 4_8 Receive FIFO becomes >= 1/2 full -// 2_8 Receive FIFO becomes >= 1/4 full -// 1_8 Receive FIFO becomes >= 1/8 full -#define UART_IFLS_RXSEL_W 3 -#define UART_IFLS_RXSEL_M 0x00000038 -#define UART_IFLS_RXSEL_S 3 -#define UART_IFLS_RXSEL_7_8 0x00000020 -#define UART_IFLS_RXSEL_6_8 0x00000018 -#define UART_IFLS_RXSEL_4_8 0x00000010 -#define UART_IFLS_RXSEL_2_8 0x00000008 -#define UART_IFLS_RXSEL_1_8 0x00000000 - -// Field: [2:0] TXSEL -// -// Transmit interrupt FIFO level select: -// This field sets the trigger points for the transmit interrupt. Values -// 0b101-0b111 are reserved. -// ENUMs: -// 7_8 Transmit FIFO becomes <= 7/8 full -// 6_8 Transmit FIFO becomes <= 3/4 full -// 4_8 Transmit FIFO becomes <= 1/2 full -// 2_8 Transmit FIFO becomes <= 1/4 full -// 1_8 Transmit FIFO becomes <= 1/8 full -#define UART_IFLS_TXSEL_W 3 -#define UART_IFLS_TXSEL_M 0x00000007 -#define UART_IFLS_TXSEL_S 0 -#define UART_IFLS_TXSEL_7_8 0x00000004 -#define UART_IFLS_TXSEL_6_8 0x00000003 -#define UART_IFLS_TXSEL_4_8 0x00000002 -#define UART_IFLS_TXSEL_2_8 0x00000001 -#define UART_IFLS_TXSEL_1_8 0x00000000 - -//***************************************************************************** -// -// Register: UART_O_IMSC -// -//***************************************************************************** -// Field: [11] EOTIM -// -// End of Transmission interrupt mask. A read returns the current mask for -// UART's EoT interrupt. On a write of 1, the mask of the EoT interrupt is set -// which means the interrupt state will be reflected in MIS.EOTMIS. A write of -// 0 clears the mask which means MIS.EOTMIS will not reflect the interrupt. -#define UART_IMSC_EOTIM 0x00000800 -#define UART_IMSC_EOTIM_BITN 11 -#define UART_IMSC_EOTIM_M 0x00000800 -#define UART_IMSC_EOTIM_S 11 - -// Field: [10] OEIM -// -// Overrun error interrupt mask. A read returns the current mask for UART's -// overrun error interrupt. On a write of 1, the mask of the overrun error -// interrupt is set which means the interrupt state will be reflected in -// MIS.OEMIS. A write of 0 clears the mask which means MIS.OEMIS will not -// reflect the interrupt. -#define UART_IMSC_OEIM 0x00000400 -#define UART_IMSC_OEIM_BITN 10 -#define UART_IMSC_OEIM_M 0x00000400 -#define UART_IMSC_OEIM_S 10 - -// Field: [9] BEIM -// -// Break error interrupt mask. A read returns the current mask for UART's break -// error interrupt. On a write of 1, the mask of the overrun error interrupt is -// set which means the interrupt state will be reflected in MIS.BEMIS. A write -// of 0 clears the mask which means MIS.BEMIS will not reflect the interrupt. -#define UART_IMSC_BEIM 0x00000200 -#define UART_IMSC_BEIM_BITN 9 -#define UART_IMSC_BEIM_M 0x00000200 -#define UART_IMSC_BEIM_S 9 - -// Field: [8] PEIM -// -// Parity error interrupt mask. A read returns the current mask for UART's -// parity error interrupt. On a write of 1, the mask of the overrun error -// interrupt is set which means the interrupt state will be reflected in -// MIS.PEMIS. A write of 0 clears the mask which means MIS.PEMIS will not -// reflect the interrupt. -#define UART_IMSC_PEIM 0x00000100 -#define UART_IMSC_PEIM_BITN 8 -#define UART_IMSC_PEIM_M 0x00000100 -#define UART_IMSC_PEIM_S 8 - -// Field: [7] FEIM -// -// Framing error interrupt mask. A read returns the current mask for UART's -// framing error interrupt. On a write of 1, the mask of the overrun error -// interrupt is set which means the interrupt state will be reflected in -// MIS.FEMIS. A write of 0 clears the mask which means MIS.FEMIS will not -// reflect the interrupt. -#define UART_IMSC_FEIM 0x00000080 -#define UART_IMSC_FEIM_BITN 7 -#define UART_IMSC_FEIM_M 0x00000080 -#define UART_IMSC_FEIM_S 7 - -// Field: [6] RTIM -// -// Receive timeout interrupt mask. A read returns the current mask for UART's -// receive timeout interrupt. On a write of 1, the mask of the overrun error -// interrupt is set which means the interrupt state will be reflected in -// MIS.RTMIS. A write of 0 clears the mask which means this bitfield will not -// reflect the interrupt. -// The raw interrupt for receive timeout RIS.RTRIS cannot be set unless the -// mask is set (RTIM = 1). This is because the mask acts as an enable for power -// saving. That is, the same status can be read from MIS.RTMIS and RIS.RTRIS. -#define UART_IMSC_RTIM 0x00000040 -#define UART_IMSC_RTIM_BITN 6 -#define UART_IMSC_RTIM_M 0x00000040 -#define UART_IMSC_RTIM_S 6 - -// Field: [5] TXIM -// -// Transmit interrupt mask. A read returns the current mask for UART's transmit -// interrupt. On a write of 1, the mask of the overrun error interrupt is set -// which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 -// clears the mask which means MIS.TXMIS will not reflect the interrupt. -#define UART_IMSC_TXIM 0x00000020 -#define UART_IMSC_TXIM_BITN 5 -#define UART_IMSC_TXIM_M 0x00000020 -#define UART_IMSC_TXIM_S 5 - -// Field: [4] RXIM -// -// Receive interrupt mask. A read returns the current mask for UART's receive -// interrupt. On a write of 1, the mask of the overrun error interrupt is set -// which means the interrupt state will be reflected in MIS.RXMIS. A write of 0 -// clears the mask which means MIS.RXMIS will not reflect the interrupt. -#define UART_IMSC_RXIM 0x00000010 -#define UART_IMSC_RXIM_BITN 4 -#define UART_IMSC_RXIM_M 0x00000010 -#define UART_IMSC_RXIM_S 4 - -// Field: [1] CTSMIM -// -// Clear to Send (CTS) modem interrupt mask. A read returns the current mask -// for UART's clear to send interrupt. On a write of 1, the mask of the overrun -// error interrupt is set which means the interrupt state will be reflected in -// MIS.CTSMMIS. A write of 0 clears the mask which means MIS.CTSMMIS will not -// reflect the interrupt. -#define UART_IMSC_CTSMIM 0x00000002 -#define UART_IMSC_CTSMIM_BITN 1 -#define UART_IMSC_CTSMIM_M 0x00000002 -#define UART_IMSC_CTSMIM_S 1 - -//***************************************************************************** -// -// Register: UART_O_RIS -// -//***************************************************************************** -// Field: [11] EOTRIS -// -// End of Transmission interrupt status: -// This field returns the raw interrupt state of UART's end of transmission -// interrupt. End of transmission flag is set when all the Transmit data in the -// FIFO and on the TX Line is tranmitted. -#define UART_RIS_EOTRIS 0x00000800 -#define UART_RIS_EOTRIS_BITN 11 -#define UART_RIS_EOTRIS_M 0x00000800 -#define UART_RIS_EOTRIS_S 11 - -// Field: [10] OERIS -// -// Overrun error interrupt status: -// This field returns the raw interrupt state of UART's overrun error -// interrupt. Overrun error occurs if data is received and the receive FIFO is -// full. -#define UART_RIS_OERIS 0x00000400 -#define UART_RIS_OERIS_BITN 10 -#define UART_RIS_OERIS_M 0x00000400 -#define UART_RIS_OERIS_S 10 - -// Field: [9] BERIS -// -// Break error interrupt status: -// This field returns the raw interrupt state of UART's break error interrupt. -// Break error is set when a break condition is detected, indicating that the -// received data input (UARTRXD input pin) was held LOW for longer than a -// full-word transmission time (defined as start, data, parity and stop bits). -#define UART_RIS_BERIS 0x00000200 -#define UART_RIS_BERIS_BITN 9 -#define UART_RIS_BERIS_M 0x00000200 -#define UART_RIS_BERIS_S 9 - -// Field: [8] PERIS -// -// Parity error interrupt status: -// This field returns the raw interrupt state of UART's parity error interrupt. -// Parity error is set if the parity of the received data character does not -// match the parity that the LCRH.EPS and LCRH.SPS select. -#define UART_RIS_PERIS 0x00000100 -#define UART_RIS_PERIS_BITN 8 -#define UART_RIS_PERIS_M 0x00000100 -#define UART_RIS_PERIS_S 8 - -// Field: [7] FERIS -// -// Framing error interrupt status: -// This field returns the raw interrupt state of UART's framing error -// interrupt. Framing error is set if the received character does not have a -// valid stop bit (a valid stop bit is 1). -#define UART_RIS_FERIS 0x00000080 -#define UART_RIS_FERIS_BITN 7 -#define UART_RIS_FERIS_M 0x00000080 -#define UART_RIS_FERIS_S 7 - -// Field: [6] RTRIS -// -// Receive timeout interrupt status: -// This field returns the raw interrupt state of UART's receive timeout -// interrupt. The receive timeout interrupt is asserted when the receive FIFO -// is not empty, and no more data is received during a 32-bit period. The -// receive timeout interrupt is cleared either when the FIFO becomes empty -// through reading all the data, or when a 1 is written to ICR.RTIC. -// The raw interrupt for receive timeout cannot be set unless the mask is set -// (IMSC.RTIM = 1). This is because the mask acts as an enable for power -// saving. That is, the same status can be read from MIS.RTMIS and RTRIS. -#define UART_RIS_RTRIS 0x00000040 -#define UART_RIS_RTRIS_BITN 6 -#define UART_RIS_RTRIS_M 0x00000040 -#define UART_RIS_RTRIS_S 6 - -// Field: [5] TXRIS -// -// Transmit interrupt status: -// This field returns the raw interrupt state of UART's transmit interrupt. -// When FIFOs are enabled (LCRH.FEN = 1), the transmit interrupt is asserted if -// the number of bytes in transmit FIFO is equal to or lower than the -// programmed trigger level (IFLS.TXSEL). The transmit interrupt is cleared by -// writing data to the transmit FIFO until it becomes greater than the trigger -// level, or by clearing the interrupt through ICR.TXIC. -// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one -// location, the transmit interrupt is asserted if there is no data present in -// the transmitters single location. It is cleared by performing a single write -// to the transmit FIFO, or by clearing the interrupt through ICR.TXIC. -#define UART_RIS_TXRIS 0x00000020 -#define UART_RIS_TXRIS_BITN 5 -#define UART_RIS_TXRIS_M 0x00000020 -#define UART_RIS_TXRIS_S 5 - -// Field: [4] RXRIS -// -// Receive interrupt status: -// This field returns the raw interrupt state of UART's receive interrupt. -// When FIFOs are enabled (LCRH.FEN = 1), the receive interrupt is asserted if -// the receive FIFO reaches the programmed trigger -// level (IFLS.RXSEL). The receive interrupt is cleared by reading data from -// the receive FIFO until it becomes less than the trigger level, or by -// clearing the interrupt through ICR.RXIC. -// When FIFOs are disabled (LCRH.FEN = 0), that is they have a depth of one -// location, the receive interrupt is asserted if data is received -// thereby filling the location. The receive interrupt is cleared by performing -// a single read of the receive FIFO, or by clearing the interrupt through -// ICR.RXIC. -#define UART_RIS_RXRIS 0x00000010 -#define UART_RIS_RXRIS_BITN 4 -#define UART_RIS_RXRIS_M 0x00000010 -#define UART_RIS_RXRIS_S 4 - -// Field: [1] CTSRMIS -// -// Clear to Send (CTS) modem interrupt status: -// This field returns the raw interrupt state of UART's clear to send -// interrupt. -#define UART_RIS_CTSRMIS 0x00000002 -#define UART_RIS_CTSRMIS_BITN 1 -#define UART_RIS_CTSRMIS_M 0x00000002 -#define UART_RIS_CTSRMIS_S 1 - -//***************************************************************************** -// -// Register: UART_O_MIS -// -//***************************************************************************** -// Field: [11] EOTMIS -// -// End of Transmission interrupt status: -// This field returns the masked interrupt state of the overrun interrupt which -// is the AND product of raw interrupt state RIS.EOTRIS and the mask setting -// IMSC.EOTIM. -#define UART_MIS_EOTMIS 0x00000800 -#define UART_MIS_EOTMIS_BITN 11 -#define UART_MIS_EOTMIS_M 0x00000800 -#define UART_MIS_EOTMIS_S 11 - -// Field: [10] OEMIS -// -// Overrun error masked interrupt status: -// This field returns the masked interrupt state of the overrun interrupt which -// is the AND product of raw interrupt state RIS.OERIS and the mask setting -// IMSC.OEIM. -#define UART_MIS_OEMIS 0x00000400 -#define UART_MIS_OEMIS_BITN 10 -#define UART_MIS_OEMIS_M 0x00000400 -#define UART_MIS_OEMIS_S 10 - -// Field: [9] BEMIS -// -// Break error masked interrupt status: -// This field returns the masked interrupt state of the break error interrupt -// which is the AND product of raw interrupt state RIS.BERIS and the mask -// setting IMSC.BEIM. -#define UART_MIS_BEMIS 0x00000200 -#define UART_MIS_BEMIS_BITN 9 -#define UART_MIS_BEMIS_M 0x00000200 -#define UART_MIS_BEMIS_S 9 - -// Field: [8] PEMIS -// -// Parity error masked interrupt status: -// This field returns the masked interrupt state of the parity error interrupt -// which is the AND product of raw interrupt state RIS.PERIS and the mask -// setting IMSC.PEIM. -#define UART_MIS_PEMIS 0x00000100 -#define UART_MIS_PEMIS_BITN 8 -#define UART_MIS_PEMIS_M 0x00000100 -#define UART_MIS_PEMIS_S 8 - -// Field: [7] FEMIS -// -// Framing error masked interrupt status: Returns the masked interrupt state of -// the framing error interrupt which is the AND product of raw interrupt state -// RIS.FERIS and the mask setting IMSC.FEIM. -#define UART_MIS_FEMIS 0x00000080 -#define UART_MIS_FEMIS_BITN 7 -#define UART_MIS_FEMIS_M 0x00000080 -#define UART_MIS_FEMIS_S 7 - -// Field: [6] RTMIS -// -// Receive timeout masked interrupt status: -// Returns the masked interrupt state of the receive timeout interrupt. -// The raw interrupt for receive timeout cannot be set unless the mask is set -// (IMSC.RTIM = 1). This is because the mask acts as an enable for power -// saving. That is, the same status can be read from RTMIS and RIS.RTRIS. -#define UART_MIS_RTMIS 0x00000040 -#define UART_MIS_RTMIS_BITN 6 -#define UART_MIS_RTMIS_M 0x00000040 -#define UART_MIS_RTMIS_S 6 - -// Field: [5] TXMIS -// -// Transmit masked interrupt status: -// This field returns the masked interrupt state of the transmit interrupt -// which is the AND product of raw interrupt state RIS.TXRIS and the mask -// setting IMSC.TXIM. -#define UART_MIS_TXMIS 0x00000020 -#define UART_MIS_TXMIS_BITN 5 -#define UART_MIS_TXMIS_M 0x00000020 -#define UART_MIS_TXMIS_S 5 - -// Field: [4] RXMIS -// -// Receive masked interrupt status: -// This field returns the masked interrupt state of the receive interrupt -// which is the AND product of raw interrupt state RIS.RXRIS and the mask -// setting IMSC.RXIM. -#define UART_MIS_RXMIS 0x00000010 -#define UART_MIS_RXMIS_BITN 4 -#define UART_MIS_RXMIS_M 0x00000010 -#define UART_MIS_RXMIS_S 4 - -// Field: [1] CTSMMIS -// -// Clear to Send (CTS) modem masked interrupt status: -// This field returns the masked interrupt state of the clear to send interrupt -// which is the AND product of raw interrupt state RIS.CTSRMIS and the mask -// setting IMSC.CTSMIM. -#define UART_MIS_CTSMMIS 0x00000002 -#define UART_MIS_CTSMMIS_BITN 1 -#define UART_MIS_CTSMMIS_M 0x00000002 -#define UART_MIS_CTSMMIS_S 1 - -//***************************************************************************** -// -// Register: UART_O_ICR -// -//***************************************************************************** -// Field: [11] EOTIC -// -// End of Transmission interrupt clear: -// Writing 1 to this field clears the overrun error interrupt (RIS.EOTRIS). -// Writing 0 has no effect. -#define UART_ICR_EOTIC 0x00000800 -#define UART_ICR_EOTIC_BITN 11 -#define UART_ICR_EOTIC_M 0x00000800 -#define UART_ICR_EOTIC_S 11 - -// Field: [10] OEIC -// -// Overrun error interrupt clear: -// Writing 1 to this field clears the overrun error interrupt (RIS.OERIS). -// Writing 0 has no effect. -#define UART_ICR_OEIC 0x00000400 -#define UART_ICR_OEIC_BITN 10 -#define UART_ICR_OEIC_M 0x00000400 -#define UART_ICR_OEIC_S 10 - -// Field: [9] BEIC -// -// Break error interrupt clear: -// Writing 1 to this field clears the break error interrupt (RIS.BERIS). -// Writing 0 has no effect. -#define UART_ICR_BEIC 0x00000200 -#define UART_ICR_BEIC_BITN 9 -#define UART_ICR_BEIC_M 0x00000200 -#define UART_ICR_BEIC_S 9 - -// Field: [8] PEIC -// -// Parity error interrupt clear: -// Writing 1 to this field clears the parity error interrupt (RIS.PERIS). -// Writing 0 has no effect. -#define UART_ICR_PEIC 0x00000100 -#define UART_ICR_PEIC_BITN 8 -#define UART_ICR_PEIC_M 0x00000100 -#define UART_ICR_PEIC_S 8 - -// Field: [7] FEIC -// -// Framing error interrupt clear: -// Writing 1 to this field clears the framing error interrupt (RIS.FERIS). -// Writing 0 has no effect. -#define UART_ICR_FEIC 0x00000080 -#define UART_ICR_FEIC_BITN 7 -#define UART_ICR_FEIC_M 0x00000080 -#define UART_ICR_FEIC_S 7 - -// Field: [6] RTIC -// -// Receive timeout interrupt clear: -// Writing 1 to this field clears the receive timeout interrupt (RIS.RTRIS). -// Writing 0 has no effect. -#define UART_ICR_RTIC 0x00000040 -#define UART_ICR_RTIC_BITN 6 -#define UART_ICR_RTIC_M 0x00000040 -#define UART_ICR_RTIC_S 6 - -// Field: [5] TXIC -// -// Transmit interrupt clear: -// Writing 1 to this field clears the transmit interrupt (RIS.TXRIS). Writing 0 -// has no effect. -#define UART_ICR_TXIC 0x00000020 -#define UART_ICR_TXIC_BITN 5 -#define UART_ICR_TXIC_M 0x00000020 -#define UART_ICR_TXIC_S 5 - -// Field: [4] RXIC -// -// Receive interrupt clear: -// Writing 1 to this field clears the receive interrupt (RIS.RXRIS). Writing 0 -// has no effect. -#define UART_ICR_RXIC 0x00000010 -#define UART_ICR_RXIC_BITN 4 -#define UART_ICR_RXIC_M 0x00000010 -#define UART_ICR_RXIC_S 4 - -// Field: [1] CTSMIC -// -// Clear to Send (CTS) modem interrupt clear: -// Writing 1 to this field clears the clear to send interrupt (RIS.CTSRMIS). -// Writing 0 has no effect. -#define UART_ICR_CTSMIC 0x00000002 -#define UART_ICR_CTSMIC_BITN 1 -#define UART_ICR_CTSMIC_M 0x00000002 -#define UART_ICR_CTSMIC_S 1 - -//***************************************************************************** -// -// Register: UART_O_DMACTL -// -//***************************************************************************** -// Field: [2] DMAONERR -// -// DMA on error. If this bit is set to 1, the DMA receive request outputs (for -// single and burst requests) are disabled when the UART error interrupt is -// asserted (more specifically if any of the error interrupts RIS.PERIS, -// RIS.BERIS, RIS.FERIS or RIS.OERIS are asserted). -#define UART_DMACTL_DMAONERR 0x00000004 -#define UART_DMACTL_DMAONERR_BITN 2 -#define UART_DMACTL_DMAONERR_M 0x00000004 -#define UART_DMACTL_DMAONERR_S 2 - -// Field: [1] TXDMAE -// -// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is -// enabled. -#define UART_DMACTL_TXDMAE 0x00000002 -#define UART_DMACTL_TXDMAE_BITN 1 -#define UART_DMACTL_TXDMAE_M 0x00000002 -#define UART_DMACTL_TXDMAE_S 1 - -// Field: [0] RXDMAE -// -// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is -// enabled. -#define UART_DMACTL_RXDMAE 0x00000001 -#define UART_DMACTL_RXDMAE_BITN 0 -#define UART_DMACTL_RXDMAE_M 0x00000001 -#define UART_DMACTL_RXDMAE_S 0 - - -#endif // __UART__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h deleted file mode 100644 index 2a4b161e3e2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_udma.h +++ /dev/null @@ -1,575 +0,0 @@ -/****************************************************************************** -* Filename: hw_udma_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_UDMA_H__ -#define __HW_UDMA_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// UDMA component -// -//***************************************************************************** -// Status -#define UDMA_O_STATUS 0x00000000 - -// Configuration -#define UDMA_O_CFG 0x00000004 - -// Channel Control Data Base Pointer -#define UDMA_O_CTRL 0x00000008 - -// Channel Alternate Control Data Base Pointer -#define UDMA_O_ALTCTRL 0x0000000C - -// Channel Wait On Request Status -#define UDMA_O_WAITONREQ 0x00000010 - -// Channel Software Request -#define UDMA_O_SOFTREQ 0x00000014 - -// Channel Set UseBurst -#define UDMA_O_SETBURST 0x00000018 - -// Channel Clear UseBurst -#define UDMA_O_CLEARBURST 0x0000001C - -// Channel Set Request Mask -#define UDMA_O_SETREQMASK 0x00000020 - -// Clear Channel Request Mask -#define UDMA_O_CLEARREQMASK 0x00000024 - -// Set Channel Enable -#define UDMA_O_SETCHANNELEN 0x00000028 - -// Clear Channel Enable -#define UDMA_O_CLEARCHANNELEN 0x0000002C - -// Channel Set Primary-Alternate -#define UDMA_O_SETCHNLPRIALT 0x00000030 - -// Channel Clear Primary-Alternate -#define UDMA_O_CLEARCHNLPRIALT 0x00000034 - -// Set Channel Priority -#define UDMA_O_SETCHNLPRIORITY 0x00000038 - -// Clear Channel Priority -#define UDMA_O_CLEARCHNLPRIORITY 0x0000003C - -// Error Status and Clear -#define UDMA_O_ERROR 0x0000004C - -// Channel Request Done -#define UDMA_O_REQDONE 0x00000504 - -// Channel Request Done Mask -#define UDMA_O_DONEMASK 0x00000520 - -//***************************************************************************** -// -// Register: UDMA_O_STATUS -// -//***************************************************************************** -// Field: [31:28] TEST -// -// -// 0x0: Controller does not include the integration test logic -// 0x1: Controller includes the integration test logic -// 0x2: Undefined -// ... -// 0xF: Undefined -#define UDMA_STATUS_TEST_W 4 -#define UDMA_STATUS_TEST_M 0xF0000000 -#define UDMA_STATUS_TEST_S 28 - -// Field: [20:16] TOTALCHANNELS -// -// Register value returns number of available uDMA channels minus one. For -// example a read out value of: -// -// 0x00: Show that the controller is configured to use 1 uDMA channel -// 0x01: Shows that the controller is configured to use 2 uDMA channels -// ... -// 0x1F: Shows that the controller is configured to use 32 uDMA channels -// (32-1=31=0x1F) -#define UDMA_STATUS_TOTALCHANNELS_W 5 -#define UDMA_STATUS_TOTALCHANNELS_M 0x001F0000 -#define UDMA_STATUS_TOTALCHANNELS_S 16 - -// Field: [7:4] STATE -// -// Current state of the control state machine. State can be one of the -// following: -// -// 0x0: Idle -// 0x1: Reading channel controller data -// 0x2: Reading source data end pointer -// 0x3: Reading destination data end pointer -// 0x4: Reading source data -// 0x5: Writing destination data -// 0x6: Waiting for uDMA request to clear -// 0x7: Writing channel controller data -// 0x8: Stalled -// 0x9: Done -// 0xA: Peripheral scatter-gather transition -// 0xB: Undefined -// ... -// 0xF: Undefined. -#define UDMA_STATUS_STATE_W 4 -#define UDMA_STATUS_STATE_M 0x000000F0 -#define UDMA_STATUS_STATE_S 4 - -// Field: [0] MASTERENABLE -// -// Shows the enable status of the controller as configured by CFG.MASTERENABLE: -// -// 0: Controller is disabled -// 1: Controller is enabled -#define UDMA_STATUS_MASTERENABLE 0x00000001 -#define UDMA_STATUS_MASTERENABLE_BITN 0 -#define UDMA_STATUS_MASTERENABLE_M 0x00000001 -#define UDMA_STATUS_MASTERENABLE_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CFG -// -//***************************************************************************** -// Field: [7:5] PRTOCTRL -// -// Sets the AHB-Lite bus protocol protection state by controlling the AHB -// signal HProt[3:1] as follows: -// -// Bit [7] Controls HProt[3] to indicate if a cacheable access is occurring. -// Bit [6] Controls HProt[2] to indicate if a bufferable access is occurring. -// Bit [5] Controls HProt[1] to indicate if a privileged access is occurring. -// -// When bit [n] = 1 then the corresponding HProt bit is high. -// When bit [n] = 0 then the corresponding HProt bit is low. -// -// This field controls HProt[3:1] signal for all transactions initiated by uDMA -// except two transactions below: -// - the read from the address indicated by source address pointer -// - the write to the address indicated by destination address pointer -// HProt[3:1] for these two exceptions can be controlled by dedicated fields in -// the channel configutation descriptor. -#define UDMA_CFG_PRTOCTRL_W 3 -#define UDMA_CFG_PRTOCTRL_M 0x000000E0 -#define UDMA_CFG_PRTOCTRL_S 5 - -// Field: [0] MASTERENABLE -// -// Enables the controller: -// -// 0: Disables the controller -// 1: Enables the controller -#define UDMA_CFG_MASTERENABLE 0x00000001 -#define UDMA_CFG_MASTERENABLE_BITN 0 -#define UDMA_CFG_MASTERENABLE_M 0x00000001 -#define UDMA_CFG_MASTERENABLE_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CTRL -// -//***************************************************************************** -// Field: [31:10] BASEPTR -// -// This register point to the base address for the primary data structures of -// each DMA channel. This is not stored in module, but in system memory, thus -// space must be allocated for this usage when DMA is in usage -#define UDMA_CTRL_BASEPTR_W 22 -#define UDMA_CTRL_BASEPTR_M 0xFFFFFC00 -#define UDMA_CTRL_BASEPTR_S 10 - -//***************************************************************************** -// -// Register: UDMA_O_ALTCTRL -// -//***************************************************************************** -// Field: [31:0] BASEPTR -// -// This register shows the base address for the alternate data structures and -// is calculated by module, thus read only -#define UDMA_ALTCTRL_BASEPTR_W 32 -#define UDMA_ALTCTRL_BASEPTR_M 0xFFFFFFFF -#define UDMA_ALTCTRL_BASEPTR_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_WAITONREQ -// -//***************************************************************************** -// Field: [31:0] CHNLSTATUS -// -// Channel wait on request status: -// -// Bit [Ch] = 0: Once uDMA receives a single or burst request on channel Ch, -// this channel may come out of active state even if request is still present. -// Bit [Ch] = 1: Once uDMA receives a single or burst request on channel Ch, it -// keeps channel Ch in active state until the requests are deasserted. This -// handshake is necessary for channels where the requester is in an -// asynchronous domain or can run at slower clock speed than uDMA -#define UDMA_WAITONREQ_CHNLSTATUS_W 32 -#define UDMA_WAITONREQ_CHNLSTATUS_M 0xFFFFFFFF -#define UDMA_WAITONREQ_CHNLSTATUS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_SOFTREQ -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Set the appropriate bit to generate a software uDMA request on the -// corresponding uDMA channel -// -// Bit [Ch] = 0: Does not create a uDMA request for channel Ch -// Bit [Ch] = 1: Creates a uDMA request for channel Ch -// -// Writing to a bit where a uDMA channel is not implemented does not create a -// uDMA request for that channel -#define UDMA_SOFTREQ_CHNLS_W 32 -#define UDMA_SOFTREQ_CHNLS_M 0xFFFFFFFF -#define UDMA_SOFTREQ_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_SETBURST -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Returns the useburst status, or disables individual channels from generating -// single uDMA requests. The value R is the arbitration rate and stored in the -// controller data structure. -// -// Read as: -// -// Bit [Ch] = 0: uDMA channel Ch responds to both burst and single requests on -// channel C. The controller performs 2^R, or single, bus transfers. -// -// Bit [Ch] = 1: uDMA channel Ch does not respond to single transfer requests. -// The controller only responds to burst transfer requests and performs 2^R -// transfers. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the CLEARBURST.CHNLS to set bit [Ch] to 0. -// Bit [Ch] = 1: Disables single transfer requests on channel Ch. The -// controller performs 2^R transfers for burst requests. -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETBURST_CHNLS_W 32 -#define UDMA_SETBURST_CHNLS_M 0xFFFFFFFF -#define UDMA_SETBURST_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CLEARBURST -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Set the appropriate bit to enable single transfer requests. -// -// Write as: -// -// Bit [Ch] = 0: No effect. Use the SETBURST.CHNLS to disable single transfer -// requests. -// -// Bit [Ch] = 1: Enables single transfer requests on channel Ch. -// -// Writing to a bit where a DMA channel is not implemented has no effect. -#define UDMA_CLEARBURST_CHNLS_W 32 -#define UDMA_CLEARBURST_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARBURST_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_SETREQMASK -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Returns the burst and single request mask status, or disables the -// corresponding channel from generating uDMA requests. -// -// Read as: -// Bit [Ch] = 0: External requests are enabled for channel Ch. -// Bit [Ch] = 1: External requests are disabled for channel Ch. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the CLEARREQMASK.CHNLS to enable uDMA requests. -// Bit [Ch] = 1: Disables uDMA burst request channel [C] and uDMA single -// request channel [C] input from generating uDMA requests. -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETREQMASK_CHNLS_W 32 -#define UDMA_SETREQMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_SETREQMASK_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CLEARREQMASK -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Set the appropriate bit to enable DMA request for the channel. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the SETREQMASK.CHNLS to disable channel C from -// generating requests. -// Bit [Ch] = 1: Enables channel [C] to generate DMA requests. -// -// Writing to a bit where a DMA channel is not implemented has no effect. -#define UDMA_CLEARREQMASK_CHNLS_W 32 -#define UDMA_CLEARREQMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARREQMASK_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_SETCHANNELEN -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Returns the enable status of the channels, or enables the corresponding -// channels. -// -// Read as: -// Bit [Ch] = 0: Channel Ch is disabled. -// Bit [Ch] = 1: Channel Ch is enabled. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the CLEARCHANNELEN.CHNLS to disable a channel -// Bit [Ch] = 1: Enables channel Ch -// -// Writing to a bit where a DMA channel is not implemented has no effect -#define UDMA_SETCHANNELEN_CHNLS_W 32 -#define UDMA_SETCHANNELEN_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHANNELEN_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CLEARCHANNELEN -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Set the appropriate bit to disable the corresponding uDMA channel. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the SETCHANNELEN.CHNLS to enable uDMA channels. -// Bit [Ch] = 1: Disables channel Ch -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHANNELEN_CHNLS_W 32 -#define UDMA_CLEARCHANNELEN_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHANNELEN_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_SETCHNLPRIALT -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Returns the channel control data structure status, or selects the alternate -// data structure for the corresponding uDMA channel. -// -// Read as: -// Bit [Ch] = 0: uDMA channel Ch is using the primary data structure. -// Bit [Ch] = 1: uDMA channel Ch is using the alternate data structure. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIALT.CHNLS to disable a channel -// Bit [Ch] = 1: Selects the alternate data structure for channel Ch -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETCHNLPRIALT_CHNLS_W 32 -#define UDMA_SETCHNLPRIALT_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHNLPRIALT_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CLEARCHNLPRIALT -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Clears the appropriate bit to select the primary data structure for the -// corresponding uDMA channel. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the SETCHNLPRIALT.CHNLS to select the alternate -// data structure. -// Bit [Ch] = 1: Selects the primary data structure for channel Ch. -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHNLPRIALT_CHNLS_W 32 -#define UDMA_CLEARCHNLPRIALT_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHNLPRIALT_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_SETCHNLPRIORITY -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Returns the channel priority mask status, or sets the channel priority to -// high. -// -// Read as: -// Bit [Ch] = 0: uDMA channel Ch is using the default priority level. -// Bit [Ch] = 1: uDMA channel Ch is using a high priority level. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the CLEARCHNLPRIORITY.CHNLS to set channel Ch -// to the default priority level. -// Bit [Ch] = 1: Channel Ch uses the high priority level. -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_SETCHNLPRIORITY_CHNLS_W 32 -#define UDMA_SETCHNLPRIORITY_CHNLS_M 0xFFFFFFFF -#define UDMA_SETCHNLPRIORITY_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_CLEARCHNLPRIORITY -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Clear the appropriate bit to select the default priority level for the -// specified uDMA channel. -// -// Write as: -// Bit [Ch] = 0: No effect. Use the SETCHNLPRIORITY.CHNLS to set channel Ch to -// the high priority level. -// Bit [Ch] = 1: Channel Ch uses the default priority level. -// -// Writing to a bit where a uDMA channel is not implemented has no effect -#define UDMA_CLEARCHNLPRIORITY_CHNLS_W 32 -#define UDMA_CLEARCHNLPRIORITY_CHNLS_M 0xFFFFFFFF -#define UDMA_CLEARCHNLPRIORITY_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_ERROR -// -//***************************************************************************** -// Field: [0] STATUS -// -// Returns the status of bus error flag in uDMA, or clears this bit -// -// Read as: -// -// 0: No bus error detected -// 1: Bus error detected -// -// Write as: -// -// 0: No effect, status of bus error flag is unchanged. -// 1: Clears the bus error flag. -#define UDMA_ERROR_STATUS 0x00000001 -#define UDMA_ERROR_STATUS_BITN 0 -#define UDMA_ERROR_STATUS_M 0x00000001 -#define UDMA_ERROR_STATUS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_REQDONE -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Reflects the uDMA done status for the given channel, channel [Ch]. It's a -// sticky done bit. Unless cleared by writing a 1, it holds the value of 1. -// -// Read as: -// Bit [Ch] = 0: Request has not completed for channel Ch -// Bit [Ch] = 1: Request has completed for the channel Ch -// -// Writing a 1 to individual bits would clear the corresponding bit. -// -// Write as: -// Bit [Ch] = 0: No effect. -// Bit [Ch] = 1: The corresponding [Ch] bit is cleared and is set to 0 -#define UDMA_REQDONE_CHNLS_W 32 -#define UDMA_REQDONE_CHNLS_M 0xFFFFFFFF -#define UDMA_REQDONE_CHNLS_S 0 - -//***************************************************************************** -// -// Register: UDMA_O_DONEMASK -// -//***************************************************************************** -// Field: [31:0] CHNLS -// -// Controls the propagation of the uDMA done and active state to the assigned -// peripheral. Specifically used for software channels. -// -// Read as: -// Bit [Ch] = 0: uDMA done and active state for channel Ch is not blocked from -// reaching to the peripherals. -// Note that the uDMA done state for channel [Ch] is blocked from contributing -// to generation of combined uDMA done signal -// -// Bit [Ch] = 1: uDMA done and active state for channel Ch is blocked from -// reaching to the peripherals. -// Note that the uDMA done state for channel [Ch] is not blocked from -// contributing to generation of combined uDMA done signal -// -// Write as: -// Bit [Ch] = 0: Allows uDMA done and active stat to propagate to the -// peripherals. -// Note that this disables uDMA done state for channel [Ch] from contributing -// to generation of combined uDMA done signal -// -// Bit [Ch] = 1: Blocks uDMA done and active state to propagate to the -// peripherals. -// Note that this enables uDMA done for channel [Ch] to contribute to -// generation of combined uDMA done signal. -#define UDMA_DONEMASK_CHNLS_W 32 -#define UDMA_DONEMASK_CHNLS_M 0xFFFFFFFF -#define UDMA_DONEMASK_CHNLS_S 0 - - -#endif // __UDMA__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h deleted file mode 100644 index e3de5ea6e3d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_vims.h +++ /dev/null @@ -1,204 +0,0 @@ -/****************************************************************************** -* Filename: hw_vims_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_VIMS_H__ -#define __HW_VIMS_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// VIMS component -// -//***************************************************************************** -// Status -#define VIMS_O_STAT 0x00000000 - -// Control -#define VIMS_O_CTL 0x00000004 - -//***************************************************************************** -// -// Register: VIMS_O_STAT -// -//***************************************************************************** -// Field: [5] IDCODE_LB_DIS -// -// Icode/Dcode flash line buffer status -// -// 0: Enabled or in transition to disabled -// 1: Disabled and flushed -#define VIMS_STAT_IDCODE_LB_DIS 0x00000020 -#define VIMS_STAT_IDCODE_LB_DIS_BITN 5 -#define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 -#define VIMS_STAT_IDCODE_LB_DIS_S 5 - -// Field: [4] SYSBUS_LB_DIS -// -// Sysbus flash line buffer control -// -// 0: Enabled or in transition to disabled -// 1: Disabled and flushed -#define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 -#define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 -#define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 -#define VIMS_STAT_SYSBUS_LB_DIS_S 4 - -// Field: [3] MODE_CHANGING -// -// VIMS mode change status -// -// 0: VIMS is in the mode defined by MODE -// 1: VIMS is in the process of changing to the mode given in CTL.MODE -#define VIMS_STAT_MODE_CHANGING 0x00000008 -#define VIMS_STAT_MODE_CHANGING_BITN 3 -#define VIMS_STAT_MODE_CHANGING_M 0x00000008 -#define VIMS_STAT_MODE_CHANGING_S 3 - -// Field: [2] INV -// -// This bit is set when invalidation of the cache memory is active / ongoing -#define VIMS_STAT_INV 0x00000004 -#define VIMS_STAT_INV_BITN 2 -#define VIMS_STAT_INV_M 0x00000004 -#define VIMS_STAT_INV_S 2 - -// Field: [1:0] MODE -// -// Current VIMS mode -// ENUMs: -// OFF VIMS Off mode -// CACHE VIMS Cache mode -// GPRAM VIMS GPRAM mode -#define VIMS_STAT_MODE_W 2 -#define VIMS_STAT_MODE_M 0x00000003 -#define VIMS_STAT_MODE_S 0 -#define VIMS_STAT_MODE_OFF 0x00000003 -#define VIMS_STAT_MODE_CACHE 0x00000001 -#define VIMS_STAT_MODE_GPRAM 0x00000000 - -//***************************************************************************** -// -// Register: VIMS_O_CTL -// -//***************************************************************************** -// Field: [31] STATS_CLR -// -// Set this bit to clear statistic counters. -#define VIMS_CTL_STATS_CLR 0x80000000 -#define VIMS_CTL_STATS_CLR_BITN 31 -#define VIMS_CTL_STATS_CLR_M 0x80000000 -#define VIMS_CTL_STATS_CLR_S 31 - -// Field: [30] STATS_EN -// -// Set this bit to enable statistic counters. -#define VIMS_CTL_STATS_EN 0x40000000 -#define VIMS_CTL_STATS_EN_BITN 30 -#define VIMS_CTL_STATS_EN_M 0x40000000 -#define VIMS_CTL_STATS_EN_S 30 - -// Field: [29] DYN_CG_EN -// -// 0: The in-built clock gate functionality is bypassed. -// 1: The in-built clock gate functionality is enabled, automatically gating -// the clock when not needed. -#define VIMS_CTL_DYN_CG_EN 0x20000000 -#define VIMS_CTL_DYN_CG_EN_BITN 29 -#define VIMS_CTL_DYN_CG_EN_M 0x20000000 -#define VIMS_CTL_DYN_CG_EN_S 29 - -// Field: [5] IDCODE_LB_DIS -// -// Icode/Dcode flash line buffer control -// -// 0: Enable -// 1: Disable -#define VIMS_CTL_IDCODE_LB_DIS 0x00000020 -#define VIMS_CTL_IDCODE_LB_DIS_BITN 5 -#define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 -#define VIMS_CTL_IDCODE_LB_DIS_S 5 - -// Field: [4] SYSBUS_LB_DIS -// -// Sysbus flash line buffer control -// -// 0: Enable -// 1: Disable -#define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 -#define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 -#define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 -#define VIMS_CTL_SYSBUS_LB_DIS_S 4 - -// Field: [3] ARB_CFG -// -// Icode/Dcode and sysbus arbitation scheme -// -// 0: Static arbitration (icode/docde > sysbus) -// 1: Round-robin arbitration -#define VIMS_CTL_ARB_CFG 0x00000008 -#define VIMS_CTL_ARB_CFG_BITN 3 -#define VIMS_CTL_ARB_CFG_M 0x00000008 -#define VIMS_CTL_ARB_CFG_S 3 - -// Field: [2] PREF_EN -// -// Tag prefetch control -// -// 0: Disabled -// 1: Enabled -#define VIMS_CTL_PREF_EN 0x00000004 -#define VIMS_CTL_PREF_EN_BITN 2 -#define VIMS_CTL_PREF_EN_M 0x00000004 -#define VIMS_CTL_PREF_EN_S 2 - -// Field: [1:0] MODE -// -// VIMS mode request. -// Write accesses to this field will be blocked while STAT.MODE_CHANGING is set -// to 1. -// ENUMs: -// OFF VIMS Off mode -// CACHE VIMS Cache mode -// GPRAM VIMS GPRAM mode -#define VIMS_CTL_MODE_W 2 -#define VIMS_CTL_MODE_M 0x00000003 -#define VIMS_CTL_MODE_S 0 -#define VIMS_CTL_MODE_OFF 0x00000003 -#define VIMS_CTL_MODE_CACHE 0x00000001 -#define VIMS_CTL_MODE_GPRAM 0x00000000 - - -#endif // __VIMS__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h deleted file mode 100644 index 2c826ea813e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/inc/hw_wdt.h +++ /dev/null @@ -1,290 +0,0 @@ -/****************************************************************************** -* Filename: hw_wdt_h -* Revised: 2018-05-14 12:24:52 +0200 (Mon, 14 May 2018) -* Revision: 51990 -* -* Copyright (c) 2015 - 2017, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __HW_WDT_H__ -#define __HW_WDT_H__ - -//***************************************************************************** -// -// This section defines the register offsets of -// WDT component -// -//***************************************************************************** -// Configuration -#define WDT_O_LOAD 0x00000000 - -// Current Count Value -#define WDT_O_VALUE 0x00000004 - -// Control -#define WDT_O_CTL 0x00000008 - -// Interrupt Clear -#define WDT_O_ICR 0x0000000C - -// Raw Interrupt Status -#define WDT_O_RIS 0x00000010 - -// Masked Interrupt Status -#define WDT_O_MIS 0x00000014 - -// Test Mode -#define WDT_O_TEST 0x00000418 - -// Interrupt Cause Test Mode -#define WDT_O_INT_CAUS 0x0000041C - -// Lock -#define WDT_O_LOCK 0x00000C00 - -//***************************************************************************** -// -// Register: WDT_O_LOAD -// -//***************************************************************************** -// Field: [31:0] WDTLOAD -// -// This register is the 32-bit interval value used by the 32-bit counter. When -// this register is written, the value is immediately loaded and the counter is -// restarted to count down from the new value. If this register is loaded with -// 0x0000.0000, an interrupt is immediately generated. -#define WDT_LOAD_WDTLOAD_W 32 -#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF -#define WDT_LOAD_WDTLOAD_S 0 - -//***************************************************************************** -// -// Register: WDT_O_VALUE -// -//***************************************************************************** -// Field: [31:0] WDTVALUE -// -// This register contains the current count value of the timer. -#define WDT_VALUE_WDTVALUE_W 32 -#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF -#define WDT_VALUE_WDTVALUE_S 0 - -//***************************************************************************** -// -// Register: WDT_O_CTL -// -//***************************************************************************** -// Field: [2] INTTYPE -// -// WDT Interrupt Type -// -// 0: WDT interrupt is a standard interrupt. -// 1: WDT interrupt is a non-maskable interrupt. -// ENUMs: -// NONMASKABLE Non-maskable interrupt -// MASKABLE Maskable interrupt -#define WDT_CTL_INTTYPE 0x00000004 -#define WDT_CTL_INTTYPE_BITN 2 -#define WDT_CTL_INTTYPE_M 0x00000004 -#define WDT_CTL_INTTYPE_S 2 -#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004 -#define WDT_CTL_INTTYPE_MASKABLE 0x00000000 - -// Field: [1] RESEN -// -// WDT Reset Enable. Defines the function of the WDT reset source (see -// PRCM:WARMRESET.WDT_STAT if enabled) -// -// 0: Disabled. -// 1: Enable the Watchdog reset output. -// ENUMs: -// EN Reset output Enabled -// DIS Reset output Disabled -#define WDT_CTL_RESEN 0x00000002 -#define WDT_CTL_RESEN_BITN 1 -#define WDT_CTL_RESEN_M 0x00000002 -#define WDT_CTL_RESEN_S 1 -#define WDT_CTL_RESEN_EN 0x00000002 -#define WDT_CTL_RESEN_DIS 0x00000000 - -// Field: [0] INTEN -// -// WDT Interrupt Enable -// -// 0: Interrupt event disabled. -// 1: Interrupt event enabled. Once set, this bit can only be cleared by a -// hardware reset. -// ENUMs: -// EN Interrupt Enabled -// DIS Interrupt Disabled -#define WDT_CTL_INTEN 0x00000001 -#define WDT_CTL_INTEN_BITN 0 -#define WDT_CTL_INTEN_M 0x00000001 -#define WDT_CTL_INTEN_S 0 -#define WDT_CTL_INTEN_EN 0x00000001 -#define WDT_CTL_INTEN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: WDT_O_ICR -// -//***************************************************************************** -// Field: [31:0] WDTICR -// -// This register is the interrupt clear register. A write of any value to this -// register clears the WDT interrupt and reloads the 32-bit counter from the -// LOAD register. -#define WDT_ICR_WDTICR_W 32 -#define WDT_ICR_WDTICR_M 0xFFFFFFFF -#define WDT_ICR_WDTICR_S 0 - -//***************************************************************************** -// -// Register: WDT_O_RIS -// -//***************************************************************************** -// Field: [0] WDTRIS -// -// This register is the raw interrupt status register. WDT interrupt events can -// be monitored via this register if the controller interrupt is masked. -// -// Value Description -// -// 0: The WDT has not timed out -// 1: A WDT time-out event has occurred -// -#define WDT_RIS_WDTRIS 0x00000001 -#define WDT_RIS_WDTRIS_BITN 0 -#define WDT_RIS_WDTRIS_M 0x00000001 -#define WDT_RIS_WDTRIS_S 0 - -//***************************************************************************** -// -// Register: WDT_O_MIS -// -//***************************************************************************** -// Field: [0] WDTMIS -// -// This register is the masked interrupt status register. The value of this -// register is the logical AND of the raw interrupt bit and the WDT interrupt -// enable bit CTL.INTEN. -// -// Value Description -// -// 0: The WDT has not timed out or is masked. -// 1: An unmasked WDT time-out event has occurred. -#define WDT_MIS_WDTMIS 0x00000001 -#define WDT_MIS_WDTMIS_BITN 0 -#define WDT_MIS_WDTMIS_M 0x00000001 -#define WDT_MIS_WDTMIS_S 0 - -//***************************************************************************** -// -// Register: WDT_O_TEST -// -//***************************************************************************** -// Field: [8] STALL -// -// WDT Stall Enable -// -// 0: The WDT timer continues counting if the CPU is stopped with a debugger. -// 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the -// CPU is restarted, the WDT resumes counting. -// ENUMs: -// EN Enable STALL -// DIS Disable STALL -#define WDT_TEST_STALL 0x00000100 -#define WDT_TEST_STALL_BITN 8 -#define WDT_TEST_STALL_M 0x00000100 -#define WDT_TEST_STALL_S 8 -#define WDT_TEST_STALL_EN 0x00000100 -#define WDT_TEST_STALL_DIS 0x00000000 - -// Field: [0] TEST_EN -// -// The test enable bit -// -// 0: Enable external reset -// 1: Disables the generation of an external reset. Instead bit 1 of the -// INT_CAUS register is set and an interrupt is generated -// ENUMs: -// EN Test mode Enabled -// DIS Test mode Disabled -#define WDT_TEST_TEST_EN 0x00000001 -#define WDT_TEST_TEST_EN_BITN 0 -#define WDT_TEST_TEST_EN_M 0x00000001 -#define WDT_TEST_TEST_EN_S 0 -#define WDT_TEST_TEST_EN_EN 0x00000001 -#define WDT_TEST_TEST_EN_DIS 0x00000000 - -//***************************************************************************** -// -// Register: WDT_O_INT_CAUS -// -//***************************************************************************** -// Field: [1] CAUSE_RESET -// -// Indicates that the cause of an interrupt was a reset generated but blocked -// due to TEST.TEST_EN (only possible when TEST.TEST_EN is set). -#define WDT_INT_CAUS_CAUSE_RESET 0x00000002 -#define WDT_INT_CAUS_CAUSE_RESET_BITN 1 -#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002 -#define WDT_INT_CAUS_CAUSE_RESET_S 1 - -// Field: [0] CAUSE_INTR -// -// Replica of RIS.WDTRIS -#define WDT_INT_CAUS_CAUSE_INTR 0x00000001 -#define WDT_INT_CAUS_CAUSE_INTR_BITN 0 -#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001 -#define WDT_INT_CAUS_CAUSE_INTR_S 0 - -//***************************************************************************** -// -// Register: WDT_O_LOCK -// -//***************************************************************************** -// Field: [31:0] WDTLOCK -// -// WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers -// for write access. A write of any other value reapplies the lock, preventing -// any register updates (NOTE: TEST.TEST_EN bit is not lockable). -// -// A read of this register returns the following values: -// -// 0x0000.0000: Unlocked -// 0x0000.0001: Locked -#define WDT_LOCK_WDTLOCK_W 32 -#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF -#define WDT_LOCK_WDTLOCK_S 0 - - -#endif // __WDT__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h deleted file mode 100644 index b293749a203..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_bt5.h +++ /dev/null @@ -1,218 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_cpe_bt5.h -* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ -* Revision: $Revision: 18889 $ -* -* Description: RF core patch for Bluetooth 5 support ("BLE" and "BLE5" API command sets) in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -#ifndef _RF_PATCH_CPE_BT5_H -#define _RF_PATCH_CPE_BT5_H - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#ifndef CPE_PATCH_TYPE -#define CPE_PATCH_TYPE static const uint32_t -#endif - -#ifndef SYS_PATCH_TYPE -#define SYS_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef _APPLY_PATCH_TAB -#define _APPLY_PATCH_TAB -#endif - - -CPE_PATCH_TYPE patchImageBt5[] = { - 0x21004059, - 0x210040a5, - 0x21004085, - 0x79654c07, - 0xf809f000, - 0x40697961, - 0xd5030749, - 0x4a042101, - 0x60110389, - 0xb570bd70, - 0x47084902, - 0x21000380, - 0x40041108, - 0x0000592d, - 0x21014805, - 0x438a6802, - 0x6b836002, - 0x6383438b, - 0x6002430a, - 0x47004801, - 0x40046000, - 0x00005b3f, - 0x490cb510, - 0x4a0c4788, - 0x5e512106, - 0xd0072900, - 0xd0052902, - 0xd0032909, - 0xd0012910, - 0xd1072911, - 0x43c92177, - 0xdd014288, - 0xdd012800, - 0x43c0207f, - 0x0000bd10, - 0x000065a9, - 0x21000380, -}; -#define _NWORD_PATCHIMAGE_BT5 37 - -#define _NWORD_PATCHCPEHD_BT5 0 - -#define _NWORD_PATCHSYS_BT5 0 - - - -#ifndef _BT5_SYSRAM_START -#define _BT5_SYSRAM_START 0x20000000 -#endif - -#ifndef _BT5_CPERAM_START -#define _BT5_CPERAM_START 0x21000000 -#endif - -#define _BT5_SYS_PATCH_FIXED_ADDR 0x20000000 - -#define _BT5_PATCH_VEC_ADDR_OFFSET 0x03D0 -#define _BT5_PATCH_TAB_OFFSET 0x03D4 -#define _BT5_IRQPATCH_OFFSET 0x0480 -#define _BT5_PATCH_VEC_OFFSET 0x404C - -#define _BT5_PATCH_CPEHD_OFFSET 0x04E0 - -#ifndef _BT5_NO_PROG_STATE_VAR -static uint8_t bBt5PatchEntered = 0; -#endif - -PATCH_FUN_SPEC void enterBt5CpePatch(void) -{ -#if (_NWORD_PATCHIMAGE_BT5 > 0) - uint32_t *pPatchVec = (uint32_t *) (_BT5_CPERAM_START + _BT5_PATCH_VEC_OFFSET); - - memcpy(pPatchVec, patchImageBt5, sizeof(patchImageBt5)); -#endif -} - -PATCH_FUN_SPEC void enterBt5CpeHdPatch(void) -{ -#if (_NWORD_PATCHCPEHD_BT5 > 0) - uint32_t *pPatchCpeHd = (uint32_t *) (_BT5_CPERAM_START + _BT5_PATCH_CPEHD_OFFSET); - - memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); -#endif -} - -PATCH_FUN_SPEC void enterBt5SysPatch(void) -{ -} - -PATCH_FUN_SPEC void configureBt5Patch(void) -{ - uint8_t *pPatchTab = (uint8_t *) (_BT5_CPERAM_START + _BT5_PATCH_TAB_OFFSET); - - - pPatchTab[76] = 0; - pPatchTab[91] = 1; - pPatchTab[79] = 2; -} - -PATCH_FUN_SPEC void applyBt5Patch(void) -{ -#ifdef _BT5_NO_PROG_STATE_VAR - enterBt5SysPatch(); - enterBt5CpePatch(); -#else - if (!bBt5PatchEntered) - { - enterBt5SysPatch(); - enterBt5CpePatch(); - bBt5PatchEntered = 1; - } -#endif - enterBt5CpeHdPatch(); - configureBt5Patch(); -} - -PATCH_FUN_SPEC void refreshBt5Patch(void) -{ - enterBt5CpeHdPatch(); - configureBt5Patch(); -} - -#ifndef _BT5_NO_PROG_STATE_VAR -PATCH_FUN_SPEC void cleanBt5Patch(void) -{ - bBt5PatchEntered = 0; -} -#endif - -PATCH_FUN_SPEC void rf_patch_cpe_bt5(void) -{ - applyBt5Patch(); -} - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // _RF_PATCH_CPE_BT5_H - diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h deleted file mode 100644 index 855993da2df..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_ieee_802_15_4.h +++ /dev/null @@ -1,191 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_cpe_ieee_802_15_4.h -* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ -* Revision: $Revision: 18889 $ -* -* Description: RF core patch for IEEE 802.15.4-2006 support ("IEEE" API command set) in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -#ifndef _RF_PATCH_CPE_IEEE_802_15_4_H -#define _RF_PATCH_CPE_IEEE_802_15_4_H - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#ifndef CPE_PATCH_TYPE -#define CPE_PATCH_TYPE static const uint32_t -#endif - -#ifndef SYS_PATCH_TYPE -#define SYS_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef _APPLY_PATCH_TAB -#define _APPLY_PATCH_TAB -#endif - - -CPE_PATCH_TYPE patchImageIeee802154[] = { - 0x21004051, - 0x79654c07, - 0xf809f000, - 0x40697961, - 0xd5030749, - 0x4a042101, - 0x60110389, - 0xb570bd70, - 0x47084902, - 0x21000380, - 0x40041108, - 0x0000592d, -}; -#define _NWORD_PATCHIMAGE_IEEE_802_15_4 12 - -#define _NWORD_PATCHCPEHD_IEEE_802_15_4 0 - -#define _NWORD_PATCHSYS_IEEE_802_15_4 0 - - - -#ifndef _IEEE_802_15_4_SYSRAM_START -#define _IEEE_802_15_4_SYSRAM_START 0x20000000 -#endif - -#ifndef _IEEE_802_15_4_CPERAM_START -#define _IEEE_802_15_4_CPERAM_START 0x21000000 -#endif - -#define _IEEE_802_15_4_SYS_PATCH_FIXED_ADDR 0x20000000 - -#define _IEEE_802_15_4_PATCH_VEC_ADDR_OFFSET 0x03D0 -#define _IEEE_802_15_4_PATCH_TAB_OFFSET 0x03D4 -#define _IEEE_802_15_4_IRQPATCH_OFFSET 0x0480 -#define _IEEE_802_15_4_PATCH_VEC_OFFSET 0x404C - -#define _IEEE_802_15_4_PATCH_CPEHD_OFFSET 0x04E0 - -#ifndef _IEEE_802_15_4_NO_PROG_STATE_VAR -static uint8_t bIeee802154PatchEntered = 0; -#endif - -PATCH_FUN_SPEC void enterIeee802154CpePatch(void) -{ -#if (_NWORD_PATCHIMAGE_IEEE_802_15_4 > 0) - uint32_t *pPatchVec = (uint32_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_VEC_OFFSET); - - memcpy(pPatchVec, patchImageIeee802154, sizeof(patchImageIeee802154)); -#endif -} - -PATCH_FUN_SPEC void enterIeee802154CpeHdPatch(void) -{ -#if (_NWORD_PATCHCPEHD_IEEE_802_15_4 > 0) - uint32_t *pPatchCpeHd = (uint32_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_CPEHD_OFFSET); - - memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); -#endif -} - -PATCH_FUN_SPEC void enterIeee802154SysPatch(void) -{ -} - -PATCH_FUN_SPEC void configureIeee802154Patch(void) -{ - uint8_t *pPatchTab = (uint8_t *) (_IEEE_802_15_4_CPERAM_START + _IEEE_802_15_4_PATCH_TAB_OFFSET); - - - pPatchTab[76] = 0; -} - -PATCH_FUN_SPEC void applyIeee802154Patch(void) -{ -#ifdef _IEEE_802_15_4_NO_PROG_STATE_VAR - enterIeee802154SysPatch(); - enterIeee802154CpePatch(); -#else - if (!bIeee802154PatchEntered) - { - enterIeee802154SysPatch(); - enterIeee802154CpePatch(); - bIeee802154PatchEntered = 1; - } -#endif - enterIeee802154CpeHdPatch(); - configureIeee802154Patch(); -} - -PATCH_FUN_SPEC void refreshIeee802154Patch(void) -{ - enterIeee802154CpeHdPatch(); - configureIeee802154Patch(); -} - -#ifndef _IEEE_802_15_4_NO_PROG_STATE_VAR -PATCH_FUN_SPEC void cleanIeee802154Patch(void) -{ - bIeee802154PatchEntered = 0; -} -#endif - -PATCH_FUN_SPEC void rf_patch_cpe_ieee_802_15_4(void) -{ - applyIeee802154Patch(); -} - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // _RF_PATCH_CPE_IEEE_802_15_4_H - diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h deleted file mode 100644 index 6a197337c44..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol.h +++ /dev/null @@ -1,246 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_cpe_multi_protocol.h -* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ -* Revision: $Revision: 18889 $ -* -* Description: RF core patch for multi-protocol support (all available API command sets) in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -#ifndef _RF_PATCH_CPE_MULTI_PROTOCOL_H -#define _RF_PATCH_CPE_MULTI_PROTOCOL_H - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#ifndef CPE_PATCH_TYPE -#define CPE_PATCH_TYPE static const uint32_t -#endif - -#ifndef SYS_PATCH_TYPE -#define SYS_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef _APPLY_PATCH_TAB -#define _APPLY_PATCH_TAB -#endif - - -CPE_PATCH_TYPE patchImageMultiProtocol[] = { - 0x21004061, - 0x210040cb, - 0x2100408d, - 0x2100410d, - 0x210040ed, - 0x79654c07, - 0xf809f000, - 0x40697961, - 0xd5030749, - 0x4a042101, - 0x60110389, - 0xb570bd70, - 0x47084902, - 0x21000380, - 0x40041108, - 0x0000592d, - 0xf819f000, - 0x296cb2e1, - 0x2804d00b, - 0x2806d001, - 0x490ed107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490b2002, - 0x210c780a, - 0xd0024211, - 0x22804909, - 0xb003600a, - 0xb5f0bdf0, - 0x4907b083, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000133, - 0xe000e200, - 0x00031641, - 0x00031b23, - 0x21014805, - 0x438a6802, - 0x6b836002, - 0x6383438b, - 0x6002430a, - 0x47004801, - 0x40046000, - 0x00005b3f, - 0x490cb510, - 0x4a0c4788, - 0x5e512106, - 0xd0072900, - 0xd0052902, - 0xd0032909, - 0xd0012910, - 0xd1072911, - 0x43c92177, - 0xdd014288, - 0xdd012800, - 0x43c0207f, - 0x0000bd10, - 0x000065a9, - 0x21000380, -}; -#define _NWORD_PATCHIMAGE_MULTI_PROTOCOL 63 - -#define _NWORD_PATCHCPEHD_MULTI_PROTOCOL 0 - -#define _NWORD_PATCHSYS_MULTI_PROTOCOL 0 - - - -#ifndef _MULTI_PROTOCOL_SYSRAM_START -#define _MULTI_PROTOCOL_SYSRAM_START 0x20000000 -#endif - -#ifndef _MULTI_PROTOCOL_CPERAM_START -#define _MULTI_PROTOCOL_CPERAM_START 0x21000000 -#endif - -#define _MULTI_PROTOCOL_SYS_PATCH_FIXED_ADDR 0x20000000 - -#define _MULTI_PROTOCOL_PATCH_VEC_ADDR_OFFSET 0x03D0 -#define _MULTI_PROTOCOL_PATCH_TAB_OFFSET 0x03D4 -#define _MULTI_PROTOCOL_IRQPATCH_OFFSET 0x0480 -#define _MULTI_PROTOCOL_PATCH_VEC_OFFSET 0x404C - -#define _MULTI_PROTOCOL_PATCH_CPEHD_OFFSET 0x04E0 - -#ifndef _MULTI_PROTOCOL_NO_PROG_STATE_VAR -static uint8_t bMultiProtocolPatchEntered = 0; -#endif - -PATCH_FUN_SPEC void enterMultiProtocolCpePatch(void) -{ -#if (_NWORD_PATCHIMAGE_MULTI_PROTOCOL > 0) - uint32_t *pPatchVec = (uint32_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_VEC_OFFSET); - - memcpy(pPatchVec, patchImageMultiProtocol, sizeof(patchImageMultiProtocol)); -#endif -} - -PATCH_FUN_SPEC void enterMultiProtocolCpeHdPatch(void) -{ -#if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL > 0) - uint32_t *pPatchCpeHd = (uint32_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_CPEHD_OFFSET); - - memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); -#endif -} - -PATCH_FUN_SPEC void enterMultiProtocolSysPatch(void) -{ -} - -PATCH_FUN_SPEC void configureMultiProtocolPatch(void) -{ - uint8_t *pPatchTab = (uint8_t *) (_MULTI_PROTOCOL_CPERAM_START + _MULTI_PROTOCOL_PATCH_TAB_OFFSET); - - - pPatchTab[76] = 0; - pPatchTab[62] = 1; - pPatchTab[64] = 2; - pPatchTab[91] = 3; - pPatchTab[79] = 4; -} - -PATCH_FUN_SPEC void applyMultiProtocolPatch(void) -{ -#ifdef _MULTI_PROTOCOL_NO_PROG_STATE_VAR - enterMultiProtocolSysPatch(); - enterMultiProtocolCpePatch(); -#else - if (!bMultiProtocolPatchEntered) - { - enterMultiProtocolSysPatch(); - enterMultiProtocolCpePatch(); - bMultiProtocolPatchEntered = 1; - } -#endif - enterMultiProtocolCpeHdPatch(); - configureMultiProtocolPatch(); -} - -PATCH_FUN_SPEC void refreshMultiProtocolPatch(void) -{ - enterMultiProtocolCpeHdPatch(); - configureMultiProtocolPatch(); -} - -#ifndef _MULTI_PROTOCOL_NO_PROG_STATE_VAR -PATCH_FUN_SPEC void cleanMultiProtocolPatch(void) -{ - bMultiProtocolPatchEntered = 0; -} -#endif - -PATCH_FUN_SPEC void rf_patch_cpe_multi_protocol(void) -{ - applyMultiProtocolPatch(); -} - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // _RF_PATCH_CPE_MULTI_PROTOCOL_H - diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h deleted file mode 100644 index 6c6ddc9b579..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_multi_protocol_rtls.h +++ /dev/null @@ -1,1452 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_cpe_multi_protocol_rtls.h -* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ -* Revision: $Revision: 18889 $ -* -* Description: RF core patch for multi-protocol support (all available API command sets) with RTLS components in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -#ifndef _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H -#define _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#ifndef CPE_PATCH_TYPE -#define CPE_PATCH_TYPE static const uint32_t -#endif - -#ifndef SYS_PATCH_TYPE -#define SYS_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef _APPLY_PATCH_TAB -#define _APPLY_PATCH_TAB -#endif - - -CPE_PATCH_TYPE patchImageMultiProtocolRtls[] = { - 0x21004631, - 0x21004683, - 0x21004075, - 0x2100486f, - 0x210040ad, - 0x21004117, - 0x210040d9, - 0x2100492d, - 0x21004139, - 0x21005349, - 0x68084908, - 0x43902221, - 0x48076008, - 0x68c34700, - 0x230260c3, - 0xd1fd1e5b, - 0x68c32210, - 0x60c34393, - 0x4770618a, - 0x40048000, - 0x00005c01, - 0x4801b430, - 0x00004700, - 0x00020efd, - 0x79654c07, - 0xf809f000, - 0x40697961, - 0xd5030749, - 0x4a042101, - 0x60110389, - 0xb570bd70, - 0x47084902, - 0x21000380, - 0x40041108, - 0x0000592d, - 0xf819f000, - 0x296cb2e1, - 0x2804d00b, - 0x2806d001, - 0x490ed107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490b2002, - 0x210c780a, - 0xd0024211, - 0x22804909, - 0xb003600a, - 0xb5f0bdf0, - 0x4907b083, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000133, - 0xe000e200, - 0x00031641, - 0x00031b23, - 0x21014805, - 0x438a6802, - 0x6b836002, - 0x6383438b, - 0x6002430a, - 0x47004801, - 0x40046000, - 0x00005b3f, - 0x4803b510, - 0x30106800, - 0xfe72f000, - 0x47084901, - 0x21000108, - 0x000095e3, - 0x4cffb570, - 0x5d002044, - 0x008049fe, - 0x68801840, - 0x46054780, - 0xd0112801, - 0x5d00207e, - 0xd30d2805, - 0x06002021, - 0x00897e41, - 0x7f0a1809, - 0xd0072a02, - 0x77082003, - 0x49f43480, - 0x478888a0, - 0xbd704628, - 0x77012104, - 0x700148f1, - 0xb5ffe7f4, - 0x7e934aec, - 0x49ef185b, - 0x3280600b, - 0x09897891, - 0x49edd16e, - 0x29006909, - 0x680bd06a, - 0x041bb2da, - 0x4be40e1c, - 0x7edb3360, - 0xd01b2c01, - 0x005b2410, - 0x1edb46a6, - 0x4be5469c, - 0x681b684d, - 0x00923108, - 0x1f121852, - 0x9202402b, - 0x4ae13030, - 0x93002401, - 0x60549103, - 0x26224adf, - 0x27106914, - 0x6114433c, - 0xe0302200, - 0x009b2408, - 0x1f9b46a6, - 0xc910e7e2, - 0x40634fd9, - 0x9301402b, - 0x24014623, - 0x603c0364, - 0x34404cd3, - 0x4cd26060, - 0x68643c40, - 0xd5061a24, - 0x3c804cd1, - 0x04bf6827, - 0xbf20d401, - 0x4fcbe7fa, - 0x633c9c01, - 0x44709c02, - 0xd90042a1, - 0x4cc59903, - 0x42346864, - 0x4cc3d006, - 0x68263c80, - 0x43be2702, - 0x26006026, - 0x45621c52, - 0x9c00d3d1, - 0x405c49c0, - 0x3940402c, - 0x1a12684a, - 0x48bcd4fc, - 0x48bc6304, - 0x60412100, - 0x690248bb, - 0x438a2110, - 0xbdff6102, - 0x212248b4, - 0x420a6842, - 0x4ab2d0fc, - 0x68103a80, - 0x43882102, - 0xbdff6010, - 0x4daab5f3, - 0x5d46202f, - 0xb08148b2, - 0x05806900, - 0x2e011600, - 0x1c40d002, - 0xe0001040, - 0x49ad301e, - 0x6a093140, - 0x4ba14aac, - 0x691a4351, - 0x6a1b0e09, - 0xd0222e01, - 0x01591852, - 0x316731ff, - 0x18544b9f, - 0x68d93340, - 0xb2894fa0, - 0xb2821a08, - 0x68783f40, - 0xd4fc1b00, - 0x462860da, - 0x90003060, - 0x49958381, - 0x31122050, - 0x35804788, - 0x980180a8, - 0xd0082800, - 0x990278aa, - 0xfabef000, - 0x1852e007, - 0x31ce0119, - 0x4896e7dc, - 0x99006ac0, - 0x489577c8, - 0x68407829, - 0x08c14348, - 0xd00b2e01, - 0x38134620, - 0x687a340e, - 0xd4fc1b12, - 0x0c0b4a8f, - 0xb2896193, - 0xbdfe6151, - 0x38114620, - 0xe7f23409, - 0x4c7cb570, - 0x35604625, - 0x1e407fa8, - 0xd80d2802, - 0x28006aa0, - 0x2182d004, - 0x70015d09, - 0x62a01c40, - 0x1e406a60, - 0x7fa86260, - 0x77a81cc0, - 0x28057fa8, - 0xd112d322, - 0x28026a60, - 0x497ddd08, - 0x47881e80, - 0x62611c81, - 0xd0012800, - 0xbd702001, - 0x46082100, - 0xff7af7ff, - 0xf7ff2110, - 0x486afef2, - 0x6ac13840, - 0xd0fc07c9, - 0x38804867, - 0x22026801, - 0x60014311, - 0x8ba84964, - 0x60c83140, - 0x36404626, - 0x495e7930, - 0x18400080, - 0x47806880, - 0xd1de2800, - 0x29057fa9, - 0x7fead301, - 0x29047172, - 0x7de1d3d7, - 0xd1022900, - 0x29007e21, - 0x7eead0d1, - 0x015268e1, - 0x60e11889, - 0xb570bd70, - 0x20444d4f, - 0x48535d46, - 0x3820494e, - 0x00b07ec4, - 0x68801840, - 0x4b5a4780, - 0x781a09a1, - 0xd10a4211, - 0x21ff2221, - 0x76510612, - 0x22004948, - 0x600a1f09, - 0x2101604a, - 0x212f7019, - 0x29025d49, - 0x2e31d008, - 0x07e1d003, - 0xd0032900, - 0x0861e003, - 0xe7f907c9, - 0x35802400, - 0xbd70706c, - 0x4c39b5f8, - 0x46272500, - 0x723d3760, - 0x5d00202f, - 0xd03a2802, - 0x47804845, - 0x36404626, - 0x7ff04937, - 0x62203920, - 0x43087849, - 0x48347560, - 0x38406265, - 0x2d007fc5, - 0x7d20d006, - 0x43082120, - 0x06e87520, - 0x72380ec0, - 0x7f30493a, - 0x4a3a4788, - 0xd0112d00, - 0x61c54839, - 0x20074b28, - 0x63983b40, - 0x21054d26, - 0x07806950, - 0x6868d1fc, - 0xd0f94208, - 0x30404831, - 0x63186800, - 0x28007f30, - 0x6e60d001, - 0x6be16210, - 0x47882039, - 0x20006420, - 0x482cbdf8, - 0xb5f0e7fa, - 0x20444915, - 0x2b045c43, - 0x460ad00a, - 0x78103268, - 0x28004f12, - 0x28ffd070, - 0x2b04d012, - 0xe006d003, - 0x327b460a, - 0x68cce7f3, - 0x19640145, - 0x242f60cc, - 0x2c015c64, - 0x0640d101, - 0x62480e00, - 0x701020ff, - 0x4c09202f, - 0x60200200, - 0x6a484d07, - 0x68623d40, - 0xd03f07d2, - 0xe02b220f, - 0x21000160, - 0x00025500, - 0x0000423d, - 0x21000020, - 0x40045080, - 0x210000e8, - 0x40022080, - 0x40043040, - 0xe000ed00, - 0xe000e280, - 0x400452c0, - 0x00155556, - 0x40046040, - 0x210002c0, - 0x40045180, - 0x0002175f, - 0x210004e0, - 0x00020749, - 0x00020e45, - 0x40042000, - 0x40042100, - 0x0002469d, - 0x4ec363aa, - 0x2801e003, - 0x632edd07, - 0x28001e80, - 0x6862dd1a, - 0xd1f607d2, - 0x2007e006, - 0x20ff63a8, - 0xe0116328, - 0xdd0f2800, - 0x26146862, - 0xd0b64232, - 0x7b524ab8, - 0x60220212, - 0x22084bb7, - 0x4bb7601a, - 0x6248601a, - 0xbdf02001, - 0x19c00098, - 0x64086880, - 0xbdf02000, - 0x460148b2, - 0x7bca3120, - 0x76823060, - 0x73c82002, - 0x470048af, - 0xb50049ad, - 0x71083140, - 0xd01c2831, - 0x4603dc08, - 0xfec0f000, - 0x0e13190a, - 0x0e0e150e, - 0x0e1d1b0e, - 0xd0122835, - 0xd0122836, - 0xd00a2838, - 0xd006283b, - 0x008049a3, - 0x68801840, - 0x48a2bd00, - 0x48a2bd00, - 0x48a2bd00, - 0x48a2bd00, - 0x48a2bd00, - 0x48a2bd00, - 0xb5f0bd00, - 0xb0854c98, - 0x31204621, - 0x7bce9103, - 0x5d092144, - 0xd0012907, - 0xd17e2934, - 0x35804625, - 0x2a00786a, - 0x7d21d07a, - 0xd5770689, - 0x3180498b, - 0x7f09468e, - 0xd0282e01, - 0x0f090709, - 0x702b004b, - 0x025b2301, - 0x2300469c, - 0x93029300, - 0xd0302900, - 0x4f8e0993, - 0xd00b07db, - 0x2b007f3b, - 0x23f7d001, - 0x4b8a401a, - 0x781b3320, - 0xd0012b00, - 0x401a23ef, - 0x0f5b0693, - 0xd00b2b07, - 0x07db08d3, - 0x2200d00c, - 0x4a82767a, - 0x9200321c, - 0x0909e013, - 0xe7d77029, - 0x02922201, - 0xe7f24694, - 0x07d20912, - 0x2201d008, - 0x4a7a767a, - 0x92003220, - 0x02522201, - 0xe0009202, - 0x4a772100, - 0x63d32307, - 0x4a752322, - 0x68523240, - 0xd0fa421a, - 0x6b524a72, - 0x61da4b72, - 0x693b4f72, - 0x43932210, - 0x4b71613b, - 0x0792695a, - 0x4a6fd1fc, - 0x68123240, - 0x06d370aa, - 0x1e9a0edb, - 0xd3002a13, - 0x46222302, - 0x92013260, - 0x76d33008, - 0xd0552900, - 0x7f7f4677, - 0x469600da, - 0x2a041bd2, - 0x2204da00, - 0xd0232e01, - 0x330e0093, - 0xe052e001, - 0x4e60e04e, - 0x467362b3, - 0x485a181b, - 0x434a6203, - 0x45624617, - 0x4667dd00, - 0x9902485b, - 0x99026041, - 0x1e4919c9, - 0x68016081, - 0x43112221, - 0x6a266001, - 0x62261c76, - 0x98036266, - 0x28017bc0, - 0xe00ad006, - 0x4f5000d6, - 0x62be3616, - 0xe7dd011b, - 0x494f4849, - 0xf7ff3040, - 0x2e02fc48, - 0x78aadd06, - 0x98004639, - 0xf85cf000, - 0xe00f2102, - 0x98004639, - 0xfd5cf7ff, - 0x31404946, - 0x9a016ac9, - 0x210077d1, - 0xd0002e01, - 0xf7ff2108, - 0x2103fccc, - 0x77819801, - 0xbdf0b005, - 0x21019a01, - 0x6a217791, - 0x62211c49, - 0xe0026261, - 0x34602100, - 0x4a3777a1, - 0x62912100, - 0x62084931, - 0x7bc09803, - 0xd1e92801, - 0x3040482e, - 0x06c968c1, - 0x2100d5fc, - 0x29021c49, - 0x4930dbfc, - 0xfc0bf7ff, - 0x481ee7dc, - 0x4601b510, - 0x460a3160, - 0x232f7e89, - 0x29025419, - 0x7d01d010, - 0xd5130689, - 0x29016a01, - 0x6ec1dd10, - 0x06c97849, - 0x1e8b0ec9, - 0xd8092b12, - 0x1e5b7d43, - 0xe0067543, - 0xfbfcf7ff, - 0xd0002800, - 0xbd102001, - 0x76d12100, - 0xbd102000, - 0x33804b1b, - 0x7083695b, - 0x22017042, - 0x42910252, - 0x2102dd03, - 0x71017001, - 0x21014770, - 0x47707001, - 0x0000ffff, - 0x21000048, - 0xe000e280, - 0xe000e100, - 0x21000160, - 0x00020f47, - 0x00025500, - 0x2100461d, - 0x21004517, - 0x21004489, - 0x2100442f, - 0x2100437d, - 0x21004171, - 0x21000000, - 0x40045040, - 0x40042100, - 0x400451c0, - 0x40042000, - 0x40045300, - 0x40048000, - 0x40046000, - 0x490cb510, - 0x4a0c4788, - 0x5e512106, - 0xd0072900, - 0xd0052902, - 0xd0032909, - 0xd0012910, - 0xd1072911, - 0x43c92177, - 0xdd014288, - 0xdd012800, - 0x43c0207f, - 0x0000bd10, - 0x000065a9, - 0x21000380, - 0x2500b570, - 0x614548ff, - 0xf000207d, - 0x4cfefcfd, - 0x07c06ae0, - 0x62e5d0fc, - 0xf0002082, - 0x48fbfcf5, - 0x07c96ac1, - 0x62c5d0fc, - 0x60a12101, - 0x60a56025, - 0x384048f6, - 0x60056081, - 0xbd706085, - 0x4bf4b530, - 0x68db685b, - 0xd00d2b00, - 0x189c0852, - 0x4def4aef, - 0xe0053240, - 0x079b6853, - 0x6b6bd5fc, - 0x1c405423, - 0xdbf74288, - 0xb5f7bd30, - 0x2400468e, - 0x00c9214b, - 0x49e8468c, - 0x684e4627, - 0x46254623, - 0x62544ae6, - 0x6ad24ae1, - 0x4ae307d1, - 0x68520fc9, - 0x42821b92, - 0x2701d900, - 0x6a524ae0, - 0xd006429a, - 0x684648dd, - 0x46604bde, - 0xb29d6adb, - 0x29014613, - 0x2f00d001, - 0x4ad6d0e6, - 0x6ad16ad0, - 0x0fc006c0, - 0x0fc90689, - 0x29014ed3, - 0x2801d101, - 0x210fd011, - 0x020968b0, - 0x1d404008, - 0x48cc6190, - 0x62c12100, - 0x62012101, - 0x68784fcc, - 0x99026130, - 0xd00e2902, - 0x9802e013, - 0xd1032802, - 0x684048c7, - 0x61486871, - 0x20004671, - 0xf7ff9a02, - 0x2401ff9b, - 0x6871e7ea, - 0x8d892c01, - 0x1a40d01c, - 0x48c160f0, - 0x0a2a6ac0, - 0x0a08b281, - 0xb2c91880, - 0x1889b2ea, - 0x084a0840, - 0x23ff1811, - 0x1a103301, - 0x02001a59, - 0xfc6cf000, - 0x68706170, - 0x8d828873, - 0x18d56931, - 0xe00468f0, - 0x30f01a40, - 0x6879e7e0, - 0x1a096131, - 0xd3fa42a9, - 0x21009d02, - 0xd0052d02, - 0xd1032c01, - 0x1a086931, - 0x1ac11a80, - 0x1a406930, - 0x2c0160f0, - 0x2000d002, - 0xbdfe43c0, - 0xbdfe2000, - 0x4ba6b510, - 0x2402499e, - 0x28002201, - 0x48a4d007, - 0x694861d8, - 0x61484390, - 0x43206948, - 0x48a1e006, - 0x694861d8, - 0x61484310, - 0x43a06948, - 0x499b6148, - 0x6bc83940, - 0x40184b9c, - 0x43032303, - 0x431063cb, - 0xbd1063c8, - 0x9c02b510, - 0x02240112, - 0x3c013cff, - 0x43143a10, - 0x430c1e49, - 0x61cc498b, - 0x4b8a624b, - 0x3b402202, - 0x2200605a, - 0x620a62ca, - 0x02004a87, - 0x79926852, - 0xd0022a02, - 0x61881cc0, - 0x1d00bd10, - 0x7808e7fb, - 0x62c84983, - 0x49804770, - 0x68896849, - 0xd0042900, - 0x18080840, - 0x7800497e, - 0x487a62c8, - 0x38402103, - 0x60416001, - 0x20014976, - 0x60486008, - 0xb5384770, - 0xf7ff4605, - 0x4872ffe8, - 0x62c12100, - 0x62012108, - 0x78234c71, - 0x68a09300, - 0x05004b77, - 0x78620f00, - 0xffb6f7ff, - 0xf7ff2000, - 0x6861ff91, - 0x68082d02, - 0x8dc8d100, - 0x2101462a, - 0xfef9f7ff, - 0xb5f7bd38, - 0x46154966, - 0x684a2000, - 0x46944607, - 0x6ac94960, - 0x496207ce, - 0x68490ff6, - 0x1a8a4662, - 0x428a9900, - 0x2701d900, - 0x6a4c495e, - 0xd0074284, - 0xd0012c00, - 0xe0002001, - 0xf7ff2000, - 0x4620ff69, - 0xd0012e01, - 0xd0e32f00, - 0x21004851, - 0x4a526141, - 0x4e526ad0, - 0x0fc006c0, - 0xd1032d00, - 0x685b4b50, - 0x61636874, - 0xd0012f00, - 0xd01d2800, - 0x462a2401, - 0x99012000, - 0xfea8f7ff, - 0x6ac0484b, - 0xb2810223, - 0xb2ca0a08, - 0x1a101811, - 0x02001a59, - 0xfb88f000, - 0x4a436170, - 0x61316851, - 0x79836870, - 0x432f461f, - 0x2b01d00e, - 0xe01ad014, - 0x68b0230f, - 0x4018021b, - 0x61901d40, - 0x62c14837, - 0x62012101, - 0xe7e82400, - 0x2c008d83, - 0x1ac9d002, - 0xe00731f0, - 0xe0051ac9, - 0xd1042d00, - 0x1ac98d83, - 0x310531ff, - 0x8d8160f1, - 0x23008877, - 0x19c9468c, - 0x68f06932, - 0x4a2ce002, - 0x61326852, - 0x428a1a12, - 0x2d00d3f9, - 0x2c00d006, - 0x6931d004, - 0x46601a09, - 0x1bc31a08, - 0x1ac06930, - 0x2c0060f0, - 0x2000d001, - 0x2000bdfe, - 0xbdfe43c0, - 0x4605b538, - 0xff39f7ff, - 0x2100481a, - 0x210862c1, - 0x4c1a6201, - 0x93007823, - 0x4b2068a0, - 0x0f000500, - 0xf7ff7862, - 0x2000ff07, - 0xfee2f7ff, - 0x2d006861, - 0xd1006808, - 0x462a8dc8, - 0xf7ff2101, - 0xbd38ff52, - 0x4c0db530, - 0x62e52500, - 0x3a100112, - 0x430a1e49, - 0x626361e2, - 0x1c800200, - 0x480961a0, - 0x60012101, - 0x61456942, - 0x32404a06, - 0x68406011, - 0xe0173028, - 0x40041100, - 0x40046000, - 0x40045040, - 0x210053e8, - 0x40043000, - 0x40045300, - 0x400451c0, - 0x40044040, - 0x08180532, - 0x0818070e, - 0xfff000ff, - 0x0000aaaa, - 0x318049ff, - 0xbd306008, - 0x4605b538, - 0xfee5f7ff, - 0x210048fc, - 0x210662c1, - 0x4cfb6201, - 0x78232108, - 0x68a09300, - 0x05004bf9, - 0x78620f00, - 0xffb8f7ff, - 0x48f749f8, - 0x200161c8, - 0xfe8af7ff, - 0x462a6860, - 0x21016800, - 0xfefdf7ff, - 0xb530bd38, - 0x4bf24df2, - 0x35804cf2, - 0xd00e2a40, - 0x58420089, - 0x625a0c12, - 0xb2925842, - 0x1808629a, - 0x0c096841, - 0x684062a1, - 0x6328b280, - 0x00c9bd30, - 0x0c125842, - 0x584262da, - 0x631ab292, - 0x68411808, - 0x62590c09, - 0xb2896841, - 0x68816299, - 0x49e00c0a, - 0x634a31c0, - 0xb2926882, - 0x68c1638a, - 0x62a10c09, - 0xe7e168c0, - 0x4606b5f0, - 0x2080b089, - 0xfa8ef000, - 0x2500b662, - 0x204f4cd2, - 0x60e56066, - 0x00c049d6, - 0x47889501, - 0x68606125, - 0x290079c1, - 0x21ffd001, - 0x30203101, - 0x4acf60a1, - 0x62117901, - 0x21207902, - 0xd1002a00, - 0x70212140, - 0x21027980, - 0xd1002800, - 0x48ca2101, - 0x47807061, - 0x49c06860, - 0x79403020, - 0x62c83180, - 0x478048c6, - 0x80602000, - 0x384048bf, - 0x48c56bc0, - 0x610149c3, - 0x90002000, - 0x684849b8, - 0x24003020, - 0x46267c40, - 0x46259405, - 0x90029403, - 0x48b3e20c, - 0x4ab02700, - 0x68506147, - 0x31504601, - 0x48ade001, - 0x42886840, - 0x48b8d3fb, - 0x48b64780, - 0x48b76147, - 0x7ac07ac1, - 0x0fc907c9, - 0x40102202, - 0xd0024301, - 0xb00948b3, - 0x48a5bdf0, - 0x80412100, - 0x97076847, - 0x7cf93720, - 0x90060860, - 0xfa32f000, - 0xd1142900, - 0x42a09805, - 0x9802d011, - 0xd03b2800, - 0x07c09902, - 0x0fc00849, - 0x28009102, - 0x7cb8d002, - 0x90024048, - 0x98027c39, - 0xfa1cf000, - 0x9807460d, - 0x6b409405, - 0x5bc200ef, - 0x428a9900, - 0x1db9d02e, - 0x1d395a43, - 0x5c439300, - 0x5c421cb9, - 0x5c411cf9, - 0xf000200e, - 0x488afa0d, - 0x68402201, - 0x6b402300, - 0x5bc04611, - 0xf0000400, - 0x488dfa09, - 0x48924780, - 0x29037801, - 0x4882d1fc, - 0x8f096841, - 0x497e8041, - 0x46026848, - 0xe0073238, - 0x7c381c6d, - 0x42a8b2ed, - 0x2500d8cd, - 0x6848e7cb, - 0xd3fc4290, - 0x68404878, - 0x5bc06b40, - 0x48799000, - 0x68813840, - 0xf000207e, - 0x4873f9eb, - 0x6a386847, - 0xd0062800, - 0x46200041, - 0xf9d0f000, - 0xd0052900, - 0x496de014, - 0x780a69b8, - 0xe0334621, - 0xd00b2c00, - 0x30204638, - 0x07ca7fc1, - 0x2201d018, - 0x43917782, - 0x496f77c1, - 0x608802d0, - 0x900469b8, - 0x90076a38, - 0x46200041, - 0xf9b2f000, - 0x42819807, - 0x2c00d113, - 0x4638d00f, - 0x7fc13020, - 0xd401078a, - 0xe7664869, - 0x77822202, - 0x401122fd, - 0x200177c1, - 0x02c04960, - 0x69f86088, - 0x46209004, - 0xf0006a39, - 0x4852f997, - 0x98047802, - 0xfec1f7ff, - 0xd1042c00, - 0x6840484e, - 0x28027980, - 0x9806d00c, - 0x484b9001, - 0x79806840, - 0xd0072801, - 0x28004f48, - 0x2802d058, - 0xe078d07e, - 0xe12f2402, - 0xf7ff4620, - 0xb280fe87, - 0x48414684, - 0x6ac33040, - 0x68504a40, - 0x98016907, - 0x1d4800c1, - 0x6850543b, - 0x1d086903, - 0x4660541d, - 0xd00e2800, - 0x20006852, - 0x691243c0, - 0x50502c00, - 0xe002d167, - 0xb2a41ca4, - 0x9803e053, - 0x90031c40, - 0x6857e04f, - 0x5dc02027, - 0xd0012801, - 0xe0146950, - 0x30804832, - 0x071b6a83, - 0x61530f1b, - 0x05806a80, - 0x2b070e80, - 0x3b10dd01, - 0x281f6153, - 0x3840dd01, - 0x0100b200, - 0x010018c0, - 0x30ff6150, - 0x30014b33, - 0xd3014298, - 0x61502000, - 0x30804824, - 0x69536a40, - 0x18c00200, - 0x5058693b, - 0xb2816950, - 0xe0ca207f, - 0xf7ff4620, - 0xb281fddf, - 0x30404817, - 0x48176ac3, - 0x69076840, - 0x00c09801, - 0x54bb1d42, - 0x1d034a13, - 0x29006852, - 0x54d56912, - 0x4910d04e, - 0x68492200, - 0x690943d2, - 0x500a2c00, - 0x1c76d0af, - 0x2c01b2b6, - 0xf7ffd8a8, - 0x4809fbf5, - 0x8d386847, - 0xe00042b0, - 0xd303e040, - 0x99038d7a, - 0xd27e428a, - 0x42884914, - 0xe054e028, - 0x40043000, - 0x40046000, - 0x210053e8, - 0x0000aaaa, - 0x08180532, - 0x40044040, - 0x40045140, - 0x40045300, - 0x0000424f, - 0x00009083, - 0x00004be3, - 0x0000c210, - 0x40041100, - 0x00000de5, - 0x21000128, - 0x04040003, - 0x210002e4, - 0x04060003, - 0x00000201, - 0x0000ffff, - 0x8d78d102, - 0xd06f4288, - 0x484d2101, - 0x60810449, - 0xe684484c, - 0x21004a4c, - 0x69126852, - 0xe75f5011, - 0xf7ff4620, - 0xb282fcc6, - 0x46946878, - 0x98016903, - 0x00c04639, - 0x549d1d02, - 0x6ad34a44, - 0x6917687a, - 0x54bb1d42, - 0x2a004662, - 0x6849d00a, - 0x43d22200, - 0x2c026909, - 0xd800500a, - 0x1c76e745, - 0xe73fb2b6, - 0x68494939, - 0x3120468c, - 0x290179c9, - 0x4938d125, - 0x07136a8a, - 0x0f1b4a37, - 0x6a896997, - 0x0f3f073f, - 0x69920589, - 0x05920e89, - 0x2b070e92, - 0x3b10dd00, - 0xdd002f07, - 0x291f3f10, - 0x3940dd01, - 0x2a1fb209, - 0x3a40dd03, - 0xe01fe000, - 0x0109b212, - 0x19c918c9, - 0x18890112, - 0x4924010a, - 0x4923614a, - 0x694a4b26, - 0x320132ff, - 0xd301429a, - 0x614a2200, - 0x6a524a20, - 0x0212694b, - 0x466218d3, - 0x50136912, - 0xb2816948, - 0xf0002083, - 0xe6fbf873, - 0x98018fb9, - 0xf856f000, - 0xd1072900, - 0x28009801, - 0x8778d004, - 0x48102101, - 0x608103c9, - 0x68414810, - 0x42a18889, - 0xe5ecd900, - 0x480b2101, - 0x60810409, - 0x1e49480b, - 0x8d026840, - 0xd103428a, - 0x42888d40, - 0xe5d3d100, - 0x98014906, - 0x87486849, - 0xf0002081, - 0x2000f825, - 0x0000e5ef, - 0x40041100, - 0x04030003, - 0x210053e8, - 0x40046040, - 0x400451c0, - 0x40045080, - 0x00000201, - 0x49068800, - 0xd1064288, - 0x21004805, - 0x49058501, - 0x20016241, - 0x20824770, - 0x00004770, - 0x00006801, - 0x21000108, - 0x21004159, - 0x4801b403, - 0xbd019001, - 0x00003cc3, - 0x4801b403, - 0xbd019001, - 0x0000937d, - 0x4801b403, - 0xbd019001, - 0x00009361, - 0x4801b403, - 0xbd019001, - 0x0000867b, - 0x4801b403, - 0xbd019001, - 0x000049a3, - 0x4801b403, - 0xbd019001, - 0x00003c8f, - 0x4801b403, - 0xbd019001, - 0x00003ca9, - 0x4674b430, - 0x78251e64, - 0x42ab1c64, - 0x461dd200, - 0x005b5d63, - 0xbc3018e3, - 0x00004718, - 0x08180532, - 0x0818070e, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; -#define _NWORD_PATCHIMAGE_MULTI_PROTOCOL_RTLS 1261 - -CPE_PATCH_TYPE patchCpeHd[] = { - 0x00000000, -}; -#define _NWORD_PATCHCPEHD_MULTI_PROTOCOL_RTLS 1 - -#define _NWORD_PATCHSYS_MULTI_PROTOCOL_RTLS 0 - - - -#ifndef _MULTI_PROTOCOL_RTLS_SYSRAM_START -#define _MULTI_PROTOCOL_RTLS_SYSRAM_START 0x20000000 -#endif - -#ifndef _MULTI_PROTOCOL_RTLS_CPERAM_START -#define _MULTI_PROTOCOL_RTLS_CPERAM_START 0x21000000 -#endif - -#define _MULTI_PROTOCOL_RTLS_SYS_PATCH_FIXED_ADDR 0x20000000 - -#define _MULTI_PROTOCOL_RTLS_PATCH_VEC_ADDR_OFFSET 0x03D0 -#define _MULTI_PROTOCOL_RTLS_PATCH_TAB_OFFSET 0x03D4 -#define _MULTI_PROTOCOL_RTLS_IRQPATCH_OFFSET 0x0480 -#define _MULTI_PROTOCOL_RTLS_PATCH_VEC_OFFSET 0x404C - -#define _MULTI_PROTOCOL_RTLS_PATCH_CPEHD_OFFSET 0x04E0 - -#ifndef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR -static uint8_t bMultiProtocolRtlsPatchEntered = 0; -#endif - -PATCH_FUN_SPEC void enterMultiProtocolRtlsCpePatch(void) -{ -#if (_NWORD_PATCHIMAGE_MULTI_PROTOCOL_RTLS > 0) - uint32_t *pPatchVec = (uint32_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_VEC_OFFSET); - - memcpy(pPatchVec, patchImageMultiProtocolRtls, sizeof(patchImageMultiProtocolRtls)); -#endif -} - -PATCH_FUN_SPEC void enterMultiProtocolRtlsCpeHdPatch(void) -{ -#if (_NWORD_PATCHCPEHD_MULTI_PROTOCOL_RTLS > 0) - uint32_t *pPatchCpeHd = (uint32_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_CPEHD_OFFSET); - - memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); -#endif -} - -PATCH_FUN_SPEC void enterMultiProtocolRtlsSysPatch(void) -{ -} - -PATCH_FUN_SPEC void configureMultiProtocolRtlsPatch(void) -{ - uint8_t *pPatchTab = (uint8_t *) (_MULTI_PROTOCOL_RTLS_CPERAM_START + _MULTI_PROTOCOL_RTLS_PATCH_TAB_OFFSET); - - - pPatchTab[1] = 0; - pPatchTab[18] = 1; - pPatchTab[81] = 2; - pPatchTab[26] = 3; - pPatchTab[76] = 4; - pPatchTab[62] = 5; - pPatchTab[64] = 6; - pPatchTab[91] = 7; - pPatchTab[79] = 8; - pPatchTab[168] = 9; -} - -PATCH_FUN_SPEC void applyMultiProtocolRtlsPatch(void) -{ -#ifdef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR - enterMultiProtocolRtlsSysPatch(); - enterMultiProtocolRtlsCpePatch(); -#else - if (!bMultiProtocolRtlsPatchEntered) - { - enterMultiProtocolRtlsSysPatch(); - enterMultiProtocolRtlsCpePatch(); - bMultiProtocolRtlsPatchEntered = 1; - } -#endif - enterMultiProtocolRtlsCpeHdPatch(); - configureMultiProtocolRtlsPatch(); -} - -PATCH_FUN_SPEC void refreshMultiProtocolRtlsPatch(void) -{ - enterMultiProtocolRtlsCpeHdPatch(); - configureMultiProtocolRtlsPatch(); -} - -#ifndef _MULTI_PROTOCOL_RTLS_NO_PROG_STATE_VAR -PATCH_FUN_SPEC void cleanMultiProtocolRtlsPatch(void) -{ - bMultiProtocolRtlsPatchEntered = 0; -} -#endif - -PATCH_FUN_SPEC void rf_patch_cpe_multi_protocol_rtls(void) -{ - applyMultiProtocolRtlsPatch(); -} - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // _RF_PATCH_CPE_MULTI_PROTOCOL_RTLS_H - diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h deleted file mode 100644 index e9baefae11c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_cpe_prop.h +++ /dev/null @@ -1,219 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_cpe_prop.h -* Revised: $Date: 2019-02-27 16:13:01 +0100 (on, 27 feb 2019) $ -* Revision: $Revision: 18889 $ -* -* Description: RF core patch for proprietary radio support ("PROP" API command set) in CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ -#ifndef _RF_PATCH_CPE_PROP_H -#define _RF_PATCH_CPE_PROP_H - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#ifndef CPE_PATCH_TYPE -#define CPE_PATCH_TYPE static const uint32_t -#endif - -#ifndef SYS_PATCH_TYPE -#define SYS_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef _APPLY_PATCH_TAB -#define _APPLY_PATCH_TAB -#endif - - -CPE_PATCH_TYPE patchImageProp[] = { - 0x21004059, - 0x210040c3, - 0x21004085, - 0x79654c07, - 0xf809f000, - 0x40697961, - 0xd5030749, - 0x4a042101, - 0x60110389, - 0xb570bd70, - 0x47084902, - 0x21000380, - 0x40041108, - 0x0000592d, - 0xf819f000, - 0x296cb2e1, - 0x2804d00b, - 0x2806d001, - 0x490ed107, - 0x07c97809, - 0x7821d103, - 0xd4000709, - 0x490b2002, - 0x210c780a, - 0xd0024211, - 0x22804909, - 0xb003600a, - 0xb5f0bdf0, - 0x4907b083, - 0x48044708, - 0x22407801, - 0x70014391, - 0x47004804, - 0x210000c8, - 0x21000133, - 0xe000e200, - 0x00031641, - 0x00031b23, -}; -#define _NWORD_PATCHIMAGE_PROP 38 - -#define _NWORD_PATCHCPEHD_PROP 0 - -#define _NWORD_PATCHSYS_PROP 0 - - - -#ifndef _PROP_SYSRAM_START -#define _PROP_SYSRAM_START 0x20000000 -#endif - -#ifndef _PROP_CPERAM_START -#define _PROP_CPERAM_START 0x21000000 -#endif - -#define _PROP_SYS_PATCH_FIXED_ADDR 0x20000000 - -#define _PROP_PATCH_VEC_ADDR_OFFSET 0x03D0 -#define _PROP_PATCH_TAB_OFFSET 0x03D4 -#define _PROP_IRQPATCH_OFFSET 0x0480 -#define _PROP_PATCH_VEC_OFFSET 0x404C - -#define _PROP_PATCH_CPEHD_OFFSET 0x04E0 - -#ifndef _PROP_NO_PROG_STATE_VAR -static uint8_t bPropPatchEntered = 0; -#endif - -PATCH_FUN_SPEC void enterPropCpePatch(void) -{ -#if (_NWORD_PATCHIMAGE_PROP > 0) - uint32_t *pPatchVec = (uint32_t *) (_PROP_CPERAM_START + _PROP_PATCH_VEC_OFFSET); - - memcpy(pPatchVec, patchImageProp, sizeof(patchImageProp)); -#endif -} - -PATCH_FUN_SPEC void enterPropCpeHdPatch(void) -{ -#if (_NWORD_PATCHCPEHD_PROP > 0) - uint32_t *pPatchCpeHd = (uint32_t *) (_PROP_CPERAM_START + _PROP_PATCH_CPEHD_OFFSET); - - memcpy(pPatchCpeHd, patchCpeHd, sizeof(patchCpeHd)); -#endif -} - -PATCH_FUN_SPEC void enterPropSysPatch(void) -{ -} - -PATCH_FUN_SPEC void configurePropPatch(void) -{ - uint8_t *pPatchTab = (uint8_t *) (_PROP_CPERAM_START + _PROP_PATCH_TAB_OFFSET); - - - pPatchTab[76] = 0; - pPatchTab[62] = 1; - pPatchTab[64] = 2; -} - -PATCH_FUN_SPEC void applyPropPatch(void) -{ -#ifdef _PROP_NO_PROG_STATE_VAR - enterPropSysPatch(); - enterPropCpePatch(); -#else - if (!bPropPatchEntered) - { - enterPropSysPatch(); - enterPropCpePatch(); - bPropPatchEntered = 1; - } -#endif - enterPropCpeHdPatch(); - configurePropPatch(); -} - -PATCH_FUN_SPEC void refreshPropPatch(void) -{ - enterPropCpeHdPatch(); - configurePropPatch(); -} - -#ifndef _PROP_NO_PROG_STATE_VAR -PATCH_FUN_SPEC void cleanPropPatch(void) -{ - bPropPatchEntered = 0; -} -#endif - -PATCH_FUN_SPEC void rf_patch_cpe_prop(void) -{ - applyPropPatch(); -} - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // _RF_PATCH_CPE_PROP_H - diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h deleted file mode 100644 index 12390d3b2ae..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_iqdump.h +++ /dev/null @@ -1,438 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_mce_iqdump.h -* Revised: $Date: 2019-01-31 15:04:25 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18842 $ -* -* Description: RF core patch for IQ-dump support in CC13x2 PG2.1 and CC26x2 PG2.1 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _RF_PATCH_MCE_IQDUMP_H -#define _RF_PATCH_MCE_IQDUMP_H - -#include -#include "../inc/hw_types.h" - -#ifndef MCE_PATCH_TYPE -#define MCE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_MCERAM_BASE -#define RFC_MCERAM_BASE 0x21008000 -#endif - -#ifndef MCE_PATCH_MODE -#define MCE_PATCH_MODE 0 -#endif - -MCE_PATCH_TYPE patchIqdumpMce[337] = { - 0x2fcf6030, - 0x00013f9d, - 0xff00003f, - 0x07ff0fff, - 0x0300f800, - 0x00068080, - 0x00170003, - 0x00003d1f, - 0x08000000, - 0x0000000f, - 0x00000387, - 0x00434074, - 0x00828000, - 0x06f00080, - 0x091e0000, - 0x00540510, - 0x00000007, - 0x00505014, - 0xc02f0000, - 0x017f0c30, - 0x00000000, - 0x00000000, - 0x00000000, - 0x0000aa00, - 0x66957223, - 0xa4e5a35d, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72917391, - 0xffc0b008, - 0xa0089010, - 0x720e720d, - 0x7210720f, - 0x7100b0d0, - 0xa0d0b110, - 0x8162721b, - 0x39521020, - 0x00200670, - 0x11011630, - 0x6c011401, - 0x60816080, - 0x610b60fd, - 0x60806080, - 0x60806080, - 0x60816080, - 0x61af60fd, - 0x60806080, - 0x60806080, - 0x60816080, - 0x611b60fd, - 0x60806080, - 0x60806080, - 0x60816080, - 0x61cb60fd, - 0x60806080, - 0x60806080, - 0x60816080, - 0x615360fd, - 0x72231210, - 0x73127311, - 0x81b17313, - 0x91b00010, - 0x6044b070, - 0xc0306076, - 0xc0c1669b, - 0xc4e0c2b2, - 0x6f131820, - 0x16116e23, - 0x68871612, - 0x99c07830, - 0x948078a0, - 0xc4f29490, - 0x1820c750, - 0x12034099, - 0x16126e23, - 0x78b06896, - 0x72639990, - 0x6076b63c, - 0x96408190, - 0x39808170, - 0x10012a70, - 0x84a21611, - 0xc0f384b4, - 0xc200c0f5, - 0x40c21c01, - 0x1c10c100, - 0x4cba40b8, - 0x18031013, - 0x1a131830, - 0x39121a10, - 0x60c268b5, - 0x60c213f3, - 0x101513f3, - 0x1850c100, - 0x1a101a15, - 0x68c03914, - 0x7100b0e8, - 0xa0e8b128, - 0xb910b230, - 0x99308990, - 0xb0d1b111, - 0xb0027100, - 0xb111b012, - 0x7291a0d1, - 0xb003b630, - 0x722cb013, - 0x7100b0e0, - 0x8170b120, - 0x710092c0, - 0x8170b120, - 0x44db22f0, - 0x1c0313f0, - 0x92c340e7, - 0x71009642, - 0x92c5b120, - 0x71009644, - 0xb0e0b120, - 0x7000a630, - 0xc030a0e1, - 0xc0409910, - 0xb1119930, - 0x7100b0d1, - 0xa0d1b111, - 0xa0037291, - 0xa230a002, - 0x73117000, - 0xc0407312, - 0xc100669b, - 0x649e91f0, - 0xb113b633, - 0x7100b0d3, - 0x64eea0d3, - 0xa0d26076, - 0xa0f3a0f0, - 0x73127311, - 0xc050660f, - 0xb0d2669b, - 0x7100c035, - 0xba389b75, - 0xb112b074, - 0xa0d26115, - 0xa0f3a0f0, - 0x73127311, - 0xc18b660f, - 0x91e0c000, - 0x1218120c, - 0x787d786a, - 0x10a9788e, - 0xb0d2b074, - 0xb112c020, - 0x692d7100, - 0x669bc060, - 0xb112c035, - 0x9b757100, - 0x65a48bf0, - 0x22018ca1, - 0x10804140, - 0x453f1ca8, - 0x16181208, - 0x8c00659b, - 0x8ca165a4, - 0x414b2201, - 0x1a191090, - 0x454b1e09, - 0x659b10a9, - 0x1e048184, - 0x14bc4133, - 0x4e7e1c4c, - 0xa0d26133, - 0xa0f3a0f0, - 0x73127311, - 0x721e660f, - 0x1205120c, - 0xb0d2b074, - 0xb112c020, - 0x695f7100, - 0x669bc070, - 0x89ce789d, - 0x7100b112, - 0x22008c90, - 0x8230416f, - 0x456f2210, - 0x9a3db231, - 0x31828ab2, - 0x8af03d82, - 0x3d803180, - 0x063e1802, - 0x41911e0e, - 0x41831e2e, - 0x418a1e3e, - 0x14261056, - 0x10653d16, - 0x10566192, - 0x18563126, - 0x3d261426, - 0x61921065, - 0x31361056, - 0x14261856, - 0x10653d36, - 0x10266192, - 0x91c63976, - 0x1e048184, - 0x161c4166, - 0x4e7e1c4c, - 0x10016166, - 0x91c1c0b0, - 0x10003911, - 0x10001000, - 0x7000699d, - 0x3d303130, - 0x4dab1cd0, - 0x49ad1ce0, - 0x10d07000, - 0x10e07000, - 0xc0807000, - 0xa0d2669b, - 0xa0f3a0f0, - 0x73127311, - 0xb130660f, - 0x7100b0f0, - 0x220080b0, - 0x61b945be, - 0xc090b231, - 0xb130669b, - 0xb0d2a0f0, - 0x7100c035, - 0xba389b75, - 0xb112b074, - 0xc0a061c5, - 0xa0d2669b, - 0xa0f3a0f0, - 0x73127311, - 0xc18b660f, - 0x91e0c000, - 0x1218120c, - 0x787d786a, - 0x10a9788e, - 0xb0f0b130, - 0x80b07100, - 0x45e32200, - 0xb07461de, - 0xc0b0b231, - 0xb130669b, - 0xb0d2a0f0, - 0xb112c020, - 0x69eb7100, - 0xb112c035, - 0x9b757100, - 0x65a48bf0, - 0x22018ca1, - 0x108041fc, - 0x45fb1ca8, - 0x16181208, - 0x8c00659b, - 0x8ca165a4, - 0x42072201, - 0x1a191090, - 0x46071e09, - 0x659b10a9, - 0x1e048184, - 0x14bc41ef, - 0x4e7e1c4c, - 0x824061ef, - 0x46172230, - 0x7100b0d5, - 0xa0d5b115, - 0xc0c0620f, - 0xb118669b, - 0xb016b006, - 0xb014b004, - 0xb012b002, - 0x78428440, - 0x81730420, - 0x2a733983, - 0xc1f294e3, - 0x31621832, - 0x31511021, - 0x00200012, - 0x10309440, - 0x39301610, - 0x42352210, - 0x31501220, - 0x31801003, - 0x93801630, - 0x12041202, - 0x42472273, - 0x997084a0, - 0x1a828982, - 0x997084c0, - 0x1a848984, - 0x22636249, - 0x84b04254, - 0x89809970, - 0x14021a80, - 0x997084d0, - 0x1a808980, - 0x62601404, - 0x785184b0, - 0x99700410, - 0x1a428982, - 0x785184d0, - 0x99700410, - 0x1a448984, - 0x31543152, - 0x06333963, - 0x38321613, - 0x31823834, - 0x31843982, - 0x97220042, - 0x959084a0, - 0x95a084b0, - 0x95b084c0, - 0x95c084d0, - 0x90307810, - 0x78209050, - 0x90609040, - 0xcd90b235, - 0x70009170, - 0xb112a235, - 0xa0d27100, - 0xba3cb112, - 0x8b5481b0, - 0x31843924, - 0x91b40004, - 0x669bc0d0, - 0x72917391, - 0x72066695, - 0x72047202, - 0x73067305, - 0x86306076, - 0x3151c801, - 0x96300410, - 0x9a007000, - 0x220089f0, - 0xb9e0469c, - 0x00007000 -}; - -PATCH_FUN_SPEC void rf_patch_mce_iqdump(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 337; i++) { - HWREG(RFC_MCERAM_BASE + 4 * i) = patchIqdumpMce[i]; - } -#else - const uint32_t *pS = patchIqdumpMce; - volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 42; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); - - t1 = *pS++; - *pD++ = t1; -#endif -} - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h deleted file mode 100644 index eeabf348dff..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_mce_tof.h +++ /dev/null @@ -1,609 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_mce_tof.h -* Revised: $Date: 2019-01-31 15:04:59 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18843 $ -* -* Description: RF core MCE patch for time of flight 2Mbps PHY for CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef _RF_PATCH_MCE_TOF_H -#define _RF_PATCH_MCE_TOF_H - -#include -#include "../inc/hw_types.h" - -#ifndef MCE_PATCH_TYPE -#define MCE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_MCERAM_BASE -#define RFC_MCERAM_BASE 0x21008000 -#endif - -#ifndef MCE_PATCH_MODE -#define MCE_PATCH_MODE 0 -#endif - -MCE_PATCH_TYPE patchTofMce[506] = { - 0x0003605b, - 0x00f1000f, - 0x00000000, - 0x000c8000, - 0x00000000, - 0x0c650000, - 0x80000000, - 0x00800010, - 0x00000000, - 0x0594091e, - 0x00000350, - 0x7c200000, - 0x000000c2, - 0x34340013, - 0x0003005a, - 0x00000032, - 0xfe6b2840, - 0xdeade8ca, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x07d00011, - 0x6fdd2fea, - 0x0fb00ff0, - 0xf80f0003, - 0x007f7f30, - 0x3434001f, - 0x8010005a, - 0x01900000, - 0x40000800, - 0xc0300c65, - 0x722367ee, - 0xa35d7263, - 0x73057303, - 0x73047203, - 0x72047306, - 0x72917391, - 0x8001c7c0, - 0x90010001, - 0x08019010, - 0x720d9001, - 0x720f720e, - 0xb0d07210, - 0xc0407100, - 0xa0d067ee, - 0x721bb110, - 0x10208162, - 0x06703952, - 0x16300020, - 0x14011101, - 0x60936c01, - 0x60c260a4, - 0x6219617b, - 0x60936093, - 0x60936093, - 0x60c260a4, - 0x6219617b, - 0x60936093, - 0x60976093, - 0x12206095, - 0xc050609a, - 0x121267ee, - 0x73117223, - 0x73137312, - 0x81b17314, - 0x91b20012, - 0x6073b070, - 0xc2b2c011, - 0x1820c710, - 0x6e236f13, - 0x16121611, - 0x7d7068a8, - 0xc0229990, - 0x39818161, - 0xd0601812, - 0x67ee9a12, - 0x40971e01, - 0x99907d80, - 0x93807d50, - 0x93307d60, - 0x93007d90, - 0x6097b360, - 0xc07067e5, - 0x677e67ee, - 0x91f0c070, - 0x670bb750, - 0xb233b914, - 0xa750672d, - 0x95b488d4, - 0x95c488e4, - 0x95948ca4, - 0x95a487c4, - 0x2a007cb0, - 0x88d49060, - 0x88e495d4, - 0xc0f495e4, - 0x91449134, - 0x22008c80, - 0xb0f040e5, - 0xb0f6b130, - 0xb0d5b0d0, - 0xb110b136, - 0xb140b100, - 0x73137314, - 0x2a007cb0, - 0xc0f19060, - 0x40f51e0e, - 0x99311611, - 0xc037b912, - 0xb115b041, - 0xa910c031, - 0xb0737100, - 0xba3eb910, - 0x22008090, - 0x80b24574, - 0x45182262, - 0x220280c2, - 0xb061410b, - 0x2250b140, - 0x824040f9, - 0x45152200, - 0x40f9220f, - 0x679e100f, - 0x100f60f9, - 0x60f967b4, - 0xb234a913, - 0x93acba39, - 0xa0d58462, - 0xb0d1720f, - 0x7100b111, - 0xb1119937, - 0xb35d7100, - 0x9930c3f0, - 0xc0d0b074, - 0x894193f0, - 0x67bf9791, - 0x14018941, - 0x7100b111, - 0xba3aba3b, - 0xc210b078, - 0xa2329930, - 0xb111b235, - 0xa35d7100, - 0x7291b06e, - 0x8af2a0d1, - 0x3d823182, - 0x67eec080, - 0x8c528c33, - 0x8c441423, - 0x14248c62, - 0x06f28b32, - 0x31418b21, - 0x97a20012, - 0x0424cff2, - 0x31433143, - 0x97b40034, - 0x6957c8f0, - 0xb130b235, - 0xb136a0f0, - 0xb140a0f6, - 0xb914a100, - 0xa7507291, - 0xa002a003, - 0x9010c7c0, - 0x72047203, - 0x73067305, - 0xa23267e5, - 0x8242b235, - 0x456b1e02, - 0xc0907223, - 0x609767ee, - 0xa232b235, - 0xd0a08942, - 0x67ee9a12, - 0x67e56159, - 0x677ec00f, - 0x91f0c070, - 0xc0b0670b, - 0xb01367ee, - 0x22008c80, - 0xb0f04189, - 0xb0f6b130, - 0xb0d5b0d0, - 0xb136b111, - 0x72917313, - 0xc0e1b912, - 0x41951e0e, - 0x99311611, - 0xb041c037, - 0xc031b232, - 0xb115a910, - 0xb0737100, - 0xba3eb910, - 0x22008090, - 0x80b24614, - 0x45b32262, - 0x41992250, - 0x22008240, - 0x220f45b0, - 0x100f4199, - 0x6199679e, - 0x67b4100f, - 0xb9136199, - 0xba39b234, - 0xa0d593ac, - 0x7313720f, - 0x73147210, - 0x264081b0, - 0xb0d191b0, - 0x7100b111, - 0x9937b041, - 0x7100b111, - 0xc3f0b35d, - 0xb0749930, - 0x93f0c0d0, - 0x7100b111, - 0xc210b078, - 0xa2329930, - 0x7100b111, - 0xb06ea35d, - 0xa0d1a910, - 0x899167bf, - 0x81a01401, - 0x99311401, - 0xb0d6b116, - 0xb1167100, - 0x8090a0d6, - 0x46142200, - 0x88d4b012, - 0x88e495b4, - 0x8ca495c4, - 0x87c49594, - 0x729195a4, - 0x2a208230, - 0x92302630, - 0xc070672d, - 0x8af287b1, - 0x3d823182, - 0x69fbc310, - 0xb111b064, - 0xa0f6b136, - 0xa0f0b130, - 0x8242b235, - 0x46021e02, - 0x7291b914, - 0xa002a003, - 0x9010c7c0, - 0x72047203, - 0x73067305, - 0x67eec0c0, - 0x609767e5, - 0x67eec0d0, - 0x7291b235, - 0x677e6202, - 0xc070c00b, - 0x670b91f0, - 0x67eec0e0, - 0x727ab914, - 0xb0137226, - 0x73147313, - 0x8c8072c9, - 0x422d2200, - 0xb130b0f0, - 0x85b06231, - 0x95d085c1, - 0xb10095e1, - 0xb110b140, - 0xb0f6b064, - 0xb0d5b0d0, - 0x7313b136, - 0xb041b061, - 0x42411e1b, - 0xb9127291, - 0xc13772c9, - 0x1e0ec070, - 0x16104247, - 0x9930c0b7, - 0xb115b232, - 0xa910c031, - 0xb0737100, - 0xba3eb910, - 0x22008090, - 0x80b24705, - 0x46682262, - 0x220280c2, - 0xb061425b, - 0x2250b140, - 0x82404249, - 0x46652200, - 0x4249220f, - 0x679e100f, - 0x100f6249, - 0x624967b4, - 0x1e1bb234, - 0xa9154285, - 0xb913b916, - 0x8b33ba3b, - 0x8b2406f3, - 0x00433144, - 0x8c3397a3, - 0x14038c50, - 0x8c448c60, - 0x31431404, - 0x00343143, - 0x81b097b4, - 0x91b02650, - 0x67eec0f0, - 0xa91362bf, - 0x264081b0, - 0x993791b0, - 0x93acba39, - 0x720fa0d5, - 0xb111b0d1, - 0x7100b111, - 0xc3e0b35d, - 0xb0749930, - 0x93f0c0d0, - 0x97918941, - 0xb11167bf, - 0xb0787100, - 0x9930c210, - 0xb235a232, - 0x7100b111, - 0xb06ea35d, - 0xa0d17291, - 0x31828af2, - 0xba3b3d82, - 0x06f38b33, - 0x31448b24, - 0x92630043, - 0x8c508c33, - 0x8c601403, - 0x14048c44, - 0x31433143, - 0x97b40034, - 0x6abdc8f0, - 0xbc9062e3, - 0x95b488d4, - 0x95c488e4, - 0x95948ca4, - 0x95a487c4, - 0x85b0c01b, - 0x95d085c1, - 0x731195e1, - 0x73137312, - 0xb1007314, - 0xb0f6b140, - 0xb110b136, - 0xa232b064, - 0x22628242, - 0x722342d7, - 0xb115b064, - 0xc410b232, - 0x679e6ae0, - 0xb2356249, - 0xa100b140, - 0xa0f6b136, - 0x7291b914, - 0xa003a750, - 0xc7c0a002, - 0x72039010, - 0x73057204, - 0x73117306, - 0x73137312, - 0x720f7314, - 0x7210720d, - 0x7223720e, - 0xb235a232, - 0x1e028242, - 0x722346fc, - 0x67eec100, - 0xc1106097, - 0xb23567ee, - 0x8942a232, - 0x824262e4, - 0x430b2212, - 0xb016b006, - 0xb002b012, - 0xb014b004, - 0x90307ca0, - 0x7cb09050, - 0x90609040, - 0x73127311, - 0x73147313, - 0x720e720d, - 0x7210720f, - 0xb0e1b121, - 0xb0727100, - 0xd680a0e1, - 0x679e6b28, - 0x93f0c090, - 0xbc907000, - 0x9930c040, - 0xb910b911, - 0xb111b0d1, - 0x72917100, - 0xb111a0d1, - 0x9635722c, - 0xc0f38c82, - 0xb013b003, - 0x92c08170, - 0x96408190, - 0xb120b0e0, - 0x22027100, - 0x85b04750, - 0x92c39640, - 0x7100b120, - 0x964085c0, - 0x7100b120, - 0x96408590, - 0xb12092c3, - 0x85a07100, - 0xb1209640, - 0x8cb07100, - 0x0410cff1, - 0xb1209640, - 0x96367100, - 0x9930c040, - 0xb910b911, - 0xb111b0d1, - 0xb120a0e0, - 0x72917100, - 0xb111a0d1, - 0x1e108750, - 0xb2354371, - 0xa9156378, - 0xb913b916, - 0x2a308230, - 0x92302620, - 0x6b79c090, - 0xc120ac90, - 0x700067ee, - 0x721b7223, - 0x92c0c0f0, - 0xc1f1722f, - 0xc01592d1, - 0x7c977c86, - 0x8c807ccc, - 0x43912200, - 0x94407cf0, - 0x94607d10, - 0x7d206393, - 0xac909440, - 0xc1009636, - 0x816e91e0, - 0xc01d398e, - 0x439d1e0e, - 0x7000c03d, - 0x726a7269, - 0xb0537ce2, - 0xc76093a2, - 0x73a36ba4, - 0x96908a40, - 0x96a18a51, - 0x7cd093a6, - 0x8a4393a0, - 0x31338a54, - 0x31343d33, - 0x70003d34, - 0x8a439a31, - 0x31338a54, - 0x31343d63, - 0x96933d64, - 0xb05396a4, - 0x1e0e7000, - 0x8c3143d6, - 0x18108c40, - 0xc0024fd0, - 0x161110d1, - 0x16201812, - 0x1c203d20, - 0x10204fe4, - 0x63e41610, - 0x3d201620, - 0x4be41cd0, - 0x63e410d0, - 0xc082c000, - 0x8c448c33, - 0x1c241834, - 0x14424fe0, - 0x63e44be2, - 0x63e410d0, - 0x18d0c000, - 0x720d7000, - 0x720f720e, - 0x73117210, - 0x73137312, - 0x70007314, - 0x89f09a00, - 0x47ef2200, - 0x7000b9e0 -}; - -PATCH_FUN_SPEC void rf_patch_mce_tof(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 506; i++) { - HWREG(RFC_MCERAM_BASE + 4 * i) = patchTofMce[i]; - } -#else - const uint32_t *pS = patchTofMce; - volatile unsigned long *pD = &HWREG(RFC_MCERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 63; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); - - t1 = *pS++; - t2 = *pS++; - *pD++ = t1; - *pD++ = t2; -#endif -} - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h deleted file mode 100644 index d09cb4ad8c3..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/rf_patches/rf_patch_rfe_tof.h +++ /dev/null @@ -1,571 +0,0 @@ -/****************************************************************************** -* Filename: rf_patch_rfe_tof.h -* Revised: $Date: 2019-01-31 15:04:59 +0100 (to, 31 jan 2019) $ -* Revision: $Revision: 18843 $ -* -* Description: RF core RFE patch for time of flight 2Mbps PHY for CC13x2 and CC26x2 -* -* Copyright (c) 2015-2019, Texas Instruments Incorporated -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions are met: -* -* 1) Redistributions of source code must retain the above copyright notice, -* this list of conditions and the following disclaimer. -* -* 2) Redistributions in binary form must reproduce the above copyright notice, -* this list of conditions and the following disclaimer in the documentation -* and/or other materials provided with the distribution. -* -* 3) Neither the name of the ORGANIZATION nor the names of its contributors may -* be used to endorse or promote products derived from this software without -* specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - - -#ifndef _RF_PATCH_RFE_TOF_H -#define _RF_PATCH_RFE_TOF_H - -#include -#include "../inc/hw_types.h" - -#ifndef RFE_PATCH_TYPE -#define RFE_PATCH_TYPE static const uint32_t -#endif - -#ifndef PATCH_FUN_SPEC -#define PATCH_FUN_SPEC static inline -#endif - -#ifndef RFC_RFERAM_BASE -#define RFC_RFERAM_BASE 0x2100C000 -#endif - -#ifndef RFE_PATCH_MODE -#define RFE_PATCH_MODE 0 -#endif - -RFE_PATCH_TYPE patchTofRfe[461] = { - 0x00006194, - 0x004535aa, - 0x0421a355, - 0x1f40004c, - 0x0000003f, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x43cf41cf, - 0x4fcf47cf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x40004030, - 0x40034001, - 0x400f4007, - 0x40cf404f, - 0x6fcf7fcf, - 0x4fcf5fcf, - 0x2fcf3fcf, - 0x0fcf1fcf, - 0x00000000, - 0x00000000, - 0x9100c050, - 0xc0707000, - 0x70009100, - 0x00213182, - 0xb1109131, - 0x81017000, - 0xa100b101, - 0x91323182, - 0x9101b110, - 0x81411011, - 0x40772241, - 0x700006f1, - 0x9150c050, - 0xc0707000, - 0x70009150, - 0x00213182, - 0xb1609181, - 0x10257000, - 0x9100c050, - 0xc140c3f4, - 0x6f031420, - 0x04411031, - 0x22f082a0, - 0x26514094, - 0x3182c022, - 0x91310021, - 0x3963b110, - 0x04411031, - 0x3182c082, - 0x91310021, - 0x3963b110, - 0xc0a21031, - 0x00213182, - 0xb1109131, - 0x31151050, - 0x92551405, - 0x64677000, - 0x1031c2b2, - 0x31610631, - 0x646a02c1, - 0x1031c112, - 0x06713921, - 0x02e13151, - 0x7000646a, - 0x82b16464, - 0x39813181, - 0x646ac0e2, - 0xc1116467, - 0x646ac122, - 0x68c7c470, - 0xc0c2c111, - 0x64e0646a, - 0x700064f3, - 0x82b1647c, - 0x39813181, - 0x6482c182, - 0xc111647f, - 0x6482c0a2, - 0x68d9c470, - 0xc162c331, - 0x64e06482, - 0x700064f3, - 0xb054b050, - 0x80407100, - 0x44ed2240, - 0x40e02200, - 0x8081b060, - 0x44e01e11, - 0xa0547000, - 0x80f0b064, - 0x40e02200, - 0x12407000, - 0xb03290b0, - 0x395382a3, - 0x64ad3953, - 0x68fbc2f0, - 0xc1f18080, - 0xc1510410, - 0x41071c10, - 0xc2216467, - 0x646ac0c2, - 0x647f610b, - 0xc162c441, - 0xce306482, - 0x1280690c, - 0xb03290b0, - 0x64677000, - 0xc0c2c201, - 0x80a0646a, - 0x39403180, - 0xc1016918, - 0x646ac0c2, - 0xc122c101, - 0x82a3646a, - 0x12c064ad, - 0xb03290b0, - 0x647f7000, - 0xc162c401, - 0x80a06482, - 0x39403180, - 0xc301692c, - 0x6482c162, - 0xc0a2c101, - 0x82a36482, - 0x12c064ad, - 0xb03290b0, - 0x64677000, - 0xc081c272, - 0xc122646a, - 0x646ac111, - 0xc111c002, - 0xc062646a, - 0x646ac331, - 0xc111c362, - 0xc302646a, - 0x646ac111, - 0x395382a3, - 0xc3e264ad, - 0x2211646f, - 0xc242414f, - 0x646ac881, - 0xc111c252, - 0xc272646a, - 0x646acee1, - 0xc881c202, - 0xc202646a, - 0x646ac801, - 0x6963c170, - 0x64677000, - 0xc801c242, - 0xc252646a, - 0x646ac011, - 0xc0e1c272, - 0xc002646a, - 0x646ac101, - 0xc301c062, - 0xc122646a, - 0x646ac101, - 0xc101c362, - 0xc302646a, - 0x646ac101, - 0x64ad82a3, - 0x80817000, - 0x418f1e11, - 0xb054b050, - 0x80407100, - 0x41902240, - 0xb064a054, - 0x220180f1, - 0x70004584, - 0x41842200, - 0x6181b060, - 0x72057306, - 0x720e720b, - 0x7100b050, - 0xa050b060, - 0x80928081, - 0x45b32241, - 0xc1f18080, - 0x16300410, - 0x14011101, - 0x61c66c01, - 0x61c661c6, - 0x61c661c6, - 0x61e661c6, - 0x61e661c6, - 0x61c661c6, - 0x809161c6, - 0x0421c0f2, - 0x80823121, - 0x14122a42, - 0x11011632, - 0x6c011421, - 0x61c661cf, - 0x61c661cf, - 0x61c661c6, - 0x61c661c6, - 0x61c861c8, - 0x61cbb0b0, - 0x7306b0b1, - 0xb0307205, - 0x78206198, - 0x78427831, - 0x78547873, - 0x78667885, - 0x92719260, - 0x92939282, - 0x92b592a4, - 0xc01f91a6, - 0x3940924f, - 0x100106f0, - 0x14103110, - 0x61c89250, - 0xcff0b060, - 0x66306793, - 0xb0e16624, - 0xb054b050, - 0x8262b064, - 0x39823182, - 0x64873942, - 0x7100b0e1, - 0x22008040, - 0xb0644621, - 0x225280f2, - 0x22224611, - 0x22324608, - 0x1e02460f, - 0xdfe041f5, - 0x67939342, - 0x61f56511, - 0x663f663a, - 0x80f0b064, - 0x46112250, - 0x663561f5, - 0xcfd061f5, - 0xa0546793, - 0xa050b064, - 0xa052b060, - 0xa053b062, - 0x6565b063, - 0xcfc06511, - 0x720e6793, - 0xcfb061c8, - 0x62116793, - 0x82b16464, - 0x39813181, - 0x646ac0e2, - 0xc1116467, - 0x646ac122, - 0x700064f3, - 0x70006539, - 0x70006511, - 0x64676565, - 0xc0c2c111, - 0x7000646a, - 0xc1016467, - 0x646ac0c2, - 0xc8007000, - 0x81a991b0, - 0x8091b050, - 0x46b02241, - 0x31828262, - 0x39423982, - 0x82626487, - 0x102f06f2, - 0x142f311f, - 0x22d68266, - 0xc1404655, - 0xc5006256, - 0x6f0d1420, - 0x10de396d, - 0x044ec3f4, - 0x3182c082, - 0x396d002e, - 0x3182c0a2, - 0x826a002d, - 0x06fa398a, - 0x31808270, - 0xc00b3980, - 0x10bc180b, - 0x825318ac, - 0x149b1439, - 0x06f08260, - 0x31101001, - 0x81a11410, - 0x140c1410, - 0x46ea22c6, - 0x39408280, - 0x100206f0, - 0x3001c011, - 0x1801c010, - 0x31821802, - 0x26c10021, - 0xb00391e1, - 0xb063b013, - 0x8041b053, - 0x46e12201, - 0x92148204, - 0x1cb58225, - 0x18954e99, - 0x80f091b5, - 0x428b2240, - 0x913d62ae, - 0x913eb110, - 0x80e0b110, - 0x46a32200, - 0x42a322e6, - 0x1895b0e0, - 0x925f91b5, - 0x14f981a9, - 0x225080f0, - 0x224046e1, - 0x637646ae, - 0x6793cfa0, - 0xa052b063, - 0xc0f28280, - 0x10020420, - 0x3001c011, - 0x1801c010, - 0x31821802, - 0x26c10021, - 0x720e91e1, - 0xb01391e1, - 0xb063b003, - 0xb064b053, - 0x7100b054, - 0x22018041, - 0xb06346e1, - 0x80f0b064, - 0x42e12220, - 0x92118201, - 0x18918221, - 0xb03191b1, - 0x674e62c7, - 0x81a9a0e0, - 0x14598255, - 0x7100c080, - 0x6addb063, - 0xb0e6628b, - 0xa053a052, - 0x81b28251, - 0x3d823182, - 0x7000a003, - 0x39478287, - 0x82803987, - 0x06f03980, - 0xc0111002, - 0xc0103001, - 0x18021801, - 0x00213182, - 0x91d126c1, - 0xb012b002, - 0x39408280, - 0x100206f0, - 0x3001c011, - 0x1801c010, - 0x31821802, - 0x26c10021, - 0xb00391e1, - 0xb063b013, - 0x7100b053, - 0xb062a053, - 0x8041b052, - 0x46e12201, - 0x921481f4, - 0x82048225, - 0x4f201cb5, - 0x91b51895, - 0x224080f0, - 0x62ae4311, - 0x92148204, - 0x10408224, - 0x91b01890, - 0x1c751845, - 0x80f04f2d, - 0x43112240, - 0x913d62ae, - 0x913eb110, - 0x80e0b110, - 0x47372200, - 0x433722e6, - 0x91b5b0e0, - 0x81a9925f, - 0x80f014f9, - 0x463f2250, - 0x46ae2240, - 0x674e6355, - 0x81a9a0e0, - 0x14598255, - 0x7100c140, - 0x6b47b062, - 0x80a26311, - 0x61c86487, - 0x39428262, - 0x608706f2, - 0x7100b050, - 0x829061c8, - 0x22018041, - 0x81f446e1, - 0x82259214, - 0x91b51895, - 0x224180f1, - 0x6b5646ae, - 0x318181b1, - 0xdf903d81, - 0x67939341, - 0x22018041, - 0x81f446e1, - 0x82259214, - 0x4b411cc5, - 0x91b51895, - 0x224080f0, - 0x62ae4362, - 0x6793cf80, - 0x80418290, - 0x46e12201, - 0x92148204, - 0x18958225, - 0x80f191b5, - 0x46ae2241, - 0x80416b79, - 0x46e12201, - 0x92148204, - 0x1cc58225, - 0x18954ad7, - 0x80f091b5, - 0x43852240, - 0x933062ae, - 0x22008320, - 0xb3104794, - 0x00007000 -}; - -PATCH_FUN_SPEC void rf_patch_rfe_tof(void) -{ -#ifdef __PATCH_NO_UNROLLING - uint32_t i; - for (i = 0; i < 461; i++) { - HWREG(RFC_RFERAM_BASE + 4 * i) = patchTofRfe[i]; - } -#else - const uint32_t *pS = patchTofRfe; - volatile unsigned long *pD = &HWREG(RFC_RFERAM_BASE); - uint32_t t1, t2, t3, t4, t5, t6, t7, t8; - uint32_t nIterations = 57; - - do { - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - t6 = *pS++; - t7 = *pS++; - t8 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; - *pD++ = t6; - *pD++ = t7; - *pD++ = t8; - } while (--nIterations); - - t1 = *pS++; - t2 = *pS++; - t3 = *pS++; - t4 = *pS++; - t5 = *pS++; - *pD++ = t1; - *pD++ = t2; - *pD++ = t3; - *pD++ = t4; - *pD++ = t5; -#endif -} - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c b/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c deleted file mode 100644 index b81de47cb73..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/startup_files/ccfg.c +++ /dev/null @@ -1,536 +0,0 @@ -/****************************************************************************** -* Filename: ccfg.c -* Revised: $Date: 2017-11-02 11:36:28 +0100 (Thu, 02 Nov 2017) $ -* Revision: $Revision: 18030 $ -* -* Description: Customer Configuration for: -* CC13x2, CC13x4, CC26x2, CC26x4 device family (HW rev 2). -* -* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ -* -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -******************************************************************************/ - -#ifndef __CCFC_C__ -#define __CCFC_C__ - -#include -#include "../inc/hw_types.h" -#include "../inc/hw_ccfg.h" -#include "../inc/hw_ccfg_simple_struct.h" - -/* Required for Zephyr __ti_ccfg_section macro */ -#include - -//***************************************************************************** -// -// Introduction -// -// This file contains fields used by Boot ROM, startup code, and SW radio -// stacks to configure chip behavior. -// -// Fields are documented in more details in hw_ccfg.h and CCFG.html in -// DriverLib documentation (doc_overview.html -> CPU Domain Memory Map -> CCFG). -// -// PLEASE NOTE: -// It is not recommended to do modifications inside the ccfg.c file. -// This file is part of the CoreSDK release and future releases may have -// important modifications and new fields added without notice. -// The recommended method to modify the CCFG settings is to have a separate -// .c file that defines the specific CCFG values to be -// overridden and then include the TI provided ccfg.c at the very end, -// giving default values for non-overriden settings. -// -// Example: -// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader -// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC -// //---- Use default values for all others ---- -// #include "/source/ti/devices//startup_files/ccfg.c" -// -//***************************************************************************** - -//***************************************************************************** -// -// Internal settings, forcing several bit-fields to be set to a specific value. -// -//***************************************************************************** - -//##################################### -// Force VDDR high setting (Higher output power but also higher power consumption) -// This is also called "boost mode" -//##################################### - -#ifndef CCFG_FORCE_VDDR_HH -#define CCFG_FORCE_VDDR_HH 0x0 // Use default VDDR trim -// #define CCFG_FORCE_VDDR_HH 0x1 // Force VDDR voltage to the factory HH setting (FCFG1..VDDR_TRIM_HH) -#endif - -//***************************************************************************** -// -// Set the values of the individual bit fields. -// -//***************************************************************************** - -//##################################### -// Alternative DC/DC settings -//##################################### - -#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING -#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x0 // Alternative DC/DC setting enabled -// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x1 // Alternative DC/DC setting disabled -#endif - -#if ( CCFG_FORCE_VDDR_HH ) -#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0xC // Special VMIN level (2.5V) when forced VDDR HH voltage -#else -#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN -#define SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN 0x8 // 2.25V -#endif -#endif - -#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN -#define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x0 // Dithering disabled -// #define SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN 0x1 // Dithering enabled -#endif - -#ifndef SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK -#define SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK 0x0 // Peak current -#endif - -//##################################### -// XOSC override settings -//##################################### - -#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR -// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x0 // Enable override -#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR 0x1 // Disable override -#endif - -#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT -#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT 0x0 // Delta = 0 -#endif - -#ifndef SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET -#define SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET 0x0 // Delta = 0 -#endif - -#ifndef SET_CCFG_MODE_CONF_1_XOSC_MAX_START -#define SET_CCFG_MODE_CONF_1_XOSC_MAX_START 0x10 // 1600us -#endif - -//##################################### -// Power settings -//##################################### - -#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA -#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA 0xF // Signed delta value +1 to apply to the VDDR_TRIM_SLEEP target (0xF=-1=default=no compensation) -#endif - -#ifndef SET_CCFG_MODE_CONF_DCDC_RECHARGE -#define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x0 // Use the DC/DC during recharge in powerdown -// #define SET_CCFG_MODE_CONF_DCDC_RECHARGE 0x1 // Do not use the DC/DC during recharge in powerdown -#endif - -#ifndef SET_CCFG_MODE_CONF_DCDC_ACTIVE -#define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x0 // Use the DC/DC during active mode -// #define SET_CCFG_MODE_CONF_DCDC_ACTIVE 0x1 // Do not use the DC/DC during active mode -#endif - -#if ( CCFG_FORCE_VDDR_HH ) -#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // Special setting to enable forced VDDR HH voltage -#else -#ifndef SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL -// #define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x0 // VDDS BOD level is 2.0V -#define SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x1 // VDDS BOD level is 1.8V (or 1.65V for external regulator mode) -#endif -#endif - -#ifndef SET_CCFG_MODE_CONF_VDDR_CAP -#define SET_CCFG_MODE_CONF_VDDR_CAP 0x3A // Unsigned 8-bit integer representing the min. decoupling capacitance on VDDR in units of 100nF -#endif - -#ifndef SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC -#define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x1 // Temperature compensation on VDDR sleep trim disabled (default) -// #define SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC 0x0 // Temperature compensation on VDDR sleep trim enabled -#endif - -//##################################### -// Clock settings -//##################################### - -#ifndef SET_CCFG_MODE_CONF_SCLK_LF_OPTION -// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x0 // LF clock derived from High Frequency XOSC -// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x1 // External LF clock -#define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x2 // LF XOSC -// #define SET_CCFG_MODE_CONF_SCLK_LF_OPTION 0x3 // LF RCOSC -#endif - -#ifndef SET_CCFG_MODE_CONF_XOSC_CAP_MOD -// #define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x0 // Apply cap-array delta -#define SET_CCFG_MODE_CONF_XOSC_CAP_MOD 0x1 // Don't apply cap-array delta -#endif - -#ifndef SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA -#define SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA 0xFF // Signed 8-bit value, directly modifying trimmed XOSC cap-array value -#endif - -#ifndef SET_CCFG_EXT_LF_CLK_DIO -#define SET_CCFG_EXT_LF_CLK_DIO 0x01 // DIO number if using external LF clock -#endif - -#ifndef SET_CCFG_EXT_LF_CLK_RTC_INCREMENT -#define SET_CCFG_EXT_LF_CLK_RTC_INCREMENT 0x800000 // RTC increment representing the external LF clock frequency -#endif - -//##################################### -// Special HF clock source setting -//##################################### -#ifndef SET_CCFG_MODE_CONF_XOSC_FREQ -// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x1 // Use HPOSC as HF source (if executing on a HPOSC chip, otherwise using default (=0x3)) -#define SET_CCFG_MODE_CONF_XOSC_FREQ 0x2 // HF source is a 48 MHz xtal (default on x2/x4 chips) -// #define SET_CCFG_MODE_CONF_XOSC_FREQ 0x3 // HF source is a 24 MHz xtal (default on x0 chips) -#endif - -//##################################### -// Bootloader settings -//##################################### - -#ifndef SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE -#define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0x00 // Disable ROM boot loader -// #define SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE 0xC5 // Enable ROM boot loader -#endif - -#ifndef SET_CCFG_BL_CONFIG_BL_LEVEL -// #define SET_CCFG_BL_CONFIG_BL_LEVEL 0x0 // Active low to open boot loader backdoor -#define SET_CCFG_BL_CONFIG_BL_LEVEL 0x1 // Active high to open boot loader backdoor -#endif - -#ifndef SET_CCFG_BL_CONFIG_BL_PIN_NUMBER -#define SET_CCFG_BL_CONFIG_BL_PIN_NUMBER 0xFF // DIO number for boot loader backdoor -#endif - -#ifndef SET_CCFG_BL_CONFIG_BL_ENABLE -// #define SET_CCFG_BL_CONFIG_BL_ENABLE 0xC5 // Enabled boot loader backdoor -#define SET_CCFG_BL_CONFIG_BL_ENABLE 0xFF // Disabled boot loader backdoor -#endif - -//##################################### -// Debug access settings -//##################################### - -#ifndef SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE -#define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0x00 // Disable unlocking of TI FA option. -// #define SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE 0xC5 // Enable unlocking of TI FA option with the unlock code -#endif - -#ifndef SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE -// #define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0x00 // Access disabled -#define SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG -#endif - -#ifndef SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE -//#define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0x00 // Access disabled -#define SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG -#endif - -#ifndef SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE -#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0x00 // Access disabled -//#define SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG -#endif - -#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE -#define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0x00 // Access disabled -// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG -#endif - -#ifndef SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE -#define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0x00 // Access disabled -// #define SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG -#endif - -#ifndef SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE -#define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0x00 // Access disabled -// #define SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE 0xC5 // Access enabled if also enabled in FCFG -#endif - -//##################################### -// Alternative IEEE 802.15.4 MAC address -//##################################### -#ifndef SET_CCFG_IEEE_MAC_0 -#define SET_CCFG_IEEE_MAC_0 0xFFFFFFFF // Bits [31:0] -#endif - -#ifndef SET_CCFG_IEEE_MAC_1 -#define SET_CCFG_IEEE_MAC_1 0xFFFFFFFF // Bits [63:32] -#endif - -//##################################### -// Alternative BLE address -//##################################### -#ifndef SET_CCFG_IEEE_BLE_0 -#define SET_CCFG_IEEE_BLE_0 0xFFFFFFFF // Bits [31:0] -#endif - -#ifndef SET_CCFG_IEEE_BLE_1 -#define SET_CCFG_IEEE_BLE_1 0xFFFFFFFF // Bits [63:32] -#endif - -//##################################### -// Flash erase settings -//##################################### - -#ifndef SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N -// #define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x0 // Any chip erase request detected during boot will be ignored -#define SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N 0x1 // Any chip erase request detected during boot will be performed by the boot FW -#endif - -#ifndef SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N -// #define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x0 // Disable the boot loader bank erase function -#define SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N 0x1 // Enable the boot loader bank erase function -#endif - -//##################################### -// Flash image valid -//##################################### -#ifndef SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID -#define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID 0x00000000 // Flash image vector table is at address 0x00000000 (default) -// #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID // Flash image vector table is at address -// #define SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID // Flash image vector table address is invalid. ROM boot loader is called. -#endif - -//##################################### -// Flash sector write protection -//##################################### -#ifndef SET_CCFG_CCFG_PROT_31_0 -#define SET_CCFG_CCFG_PROT_31_0 0xFFFFFFFF -#endif - -#ifndef SET_CCFG_CCFG_PROT_63_32 -#define SET_CCFG_CCFG_PROT_63_32 0xFFFFFFFF -#endif - -#ifndef SET_CCFG_CCFG_PROT_95_64 -#define SET_CCFG_CCFG_PROT_95_64 0xFFFFFFFF -#endif - -#ifndef SET_CCFG_CCFG_PROT_127_96 -#define SET_CCFG_CCFG_PROT_127_96 0xFFFFFFFF -#endif - -//##################################### -// Select between cache or GPRAM -//##################################### -#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM -// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x0 // Cache is disabled and GPRAM is available at 0x11000000-0x11001FFF -#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x1 // Cache is enabled and GPRAM is disabled (unavailable) -#endif - -//##################################### -// Select TCXO -//##################################### -#ifndef SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO -#define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x1 // Disable TCXO -// #define SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO 0x0 // Enable TXCO -#endif - -//***************************************************************************** -// -// CCFG values that should not be modified. -// -//***************************************************************************** -#define SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG 0x0058 -#define SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS (CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M >> CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S) - -#if ( CCFG_FORCE_VDDR_HH ) -#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x0 // Special setting to enable forced VDDR HH voltage -#else -#define SET_CCFG_MODE_CONF_VDDR_EXT_LOAD 0x1 -#endif - -#define SET_CCFG_MODE_CONF_RTC_COMP 0x1 -#define SET_CCFG_MODE_CONF_HF_COMP 0x1 - -#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 0xFF -#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 0xFF -#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 0xFF -#define SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 0xFF - -#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 0xFF -#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 0xFF -#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 0xFF -#define SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 0xFF - -#define SET_CCFG_RTC_OFFSET_RTC_COMP_P0 0xFFFF -#define SET_CCFG_RTC_OFFSET_RTC_COMP_P1 0xFF -#define SET_CCFG_RTC_OFFSET_RTC_COMP_P2 0xFF - -#define SET_CCFG_FREQ_OFFSET_HF_COMP_P0 0xFFFF -#define SET_CCFG_FREQ_OFFSET_HF_COMP_P1 0xFF -#define SET_CCFG_FREQ_OFFSET_HF_COMP_P2 0xFF - -//***************************************************************************** -// -// Concatenate bit fields to words. -// DO NOT EDIT! -// -//***************************************************************************** -#define DEFAULT_CCFG_EXT_LF_CLK ( \ - ((((uint32_t)( SET_CCFG_EXT_LF_CLK_DIO )) << CCFG_EXT_LF_CLK_DIO_S ) | ~CCFG_EXT_LF_CLK_DIO_M ) & \ - ((((uint32_t)( SET_CCFG_EXT_LF_CLK_RTC_INCREMENT )) << CCFG_EXT_LF_CLK_RTC_INCREMENT_S ) | ~CCFG_EXT_LF_CLK_RTC_INCREMENT_M ) ) - -#define DEFAULT_CCFG_MODE_CONF_1 ( \ - ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_VMIN )) << CCFG_MODE_CONF_1_ALT_DCDC_VMIN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_VMIN_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN )) << CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_DITHER_EN_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_1_ALT_DCDC_IPEAK )) << CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_S ) | ~CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_INIT )) << CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_INIT_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET )) << CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_S ) | ~CCFG_MODE_CONF_1_DELTA_IBIAS_OFFSET_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_1_XOSC_MAX_START )) << CCFG_MODE_CONF_1_XOSC_MAX_START_S ) | ~CCFG_MODE_CONF_1_XOSC_MAX_START_M ) ) - -#define DEFAULT_CCFG_SIZE_AND_DIS_FLAGS ( \ - ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG )) << CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_SIZE_OF_CCFG_M ) & \ - ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS )) << CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DISABLE_FLAGS_M ) & \ - ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_TCXO_M ) & \ - ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM_M ) & \ - ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING_M ) & \ - ((((uint32_t)( SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR )) << CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_S ) | ~CCFG_SIZE_AND_DIS_FLAGS_DIS_XOSC_OVR_M ) ) - -#define DEFAULT_CCFG_MODE_CONF ( \ - ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_DELTA_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_RECHARGE )) << CCFG_MODE_CONF_DCDC_RECHARGE_S ) | ~CCFG_MODE_CONF_DCDC_RECHARGE_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_DCDC_ACTIVE )) << CCFG_MODE_CONF_DCDC_ACTIVE_S ) | ~CCFG_MODE_CONF_DCDC_ACTIVE_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_EXT_LOAD )) << CCFG_MODE_CONF_VDDR_EXT_LOAD_S ) | ~CCFG_MODE_CONF_VDDR_EXT_LOAD_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_VDDS_BOD_LEVEL )) << CCFG_MODE_CONF_VDDS_BOD_LEVEL_S ) | ~CCFG_MODE_CONF_VDDS_BOD_LEVEL_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_SCLK_LF_OPTION )) << CCFG_MODE_CONF_SCLK_LF_OPTION_S ) | ~CCFG_MODE_CONF_SCLK_LF_OPTION_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC )) << CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_S ) | ~CCFG_MODE_CONF_VDDR_TRIM_SLEEP_TC_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_RTC_COMP )) << CCFG_MODE_CONF_RTC_COMP_S ) | ~CCFG_MODE_CONF_RTC_COMP_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_FREQ )) << CCFG_MODE_CONF_XOSC_FREQ_S ) | ~CCFG_MODE_CONF_XOSC_FREQ_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAP_MOD )) << CCFG_MODE_CONF_XOSC_CAP_MOD_S ) | ~CCFG_MODE_CONF_XOSC_CAP_MOD_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_HF_COMP )) << CCFG_MODE_CONF_HF_COMP_S ) | ~CCFG_MODE_CONF_HF_COMP_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA )) << CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_S ) | ~CCFG_MODE_CONF_XOSC_CAPARRAY_DELTA_M ) & \ - ((((uint32_t)( SET_CCFG_MODE_CONF_VDDR_CAP )) << CCFG_MODE_CONF_VDDR_CAP_S ) | ~CCFG_MODE_CONF_VDDR_CAP_M ) ) - -#define DEFAULT_CCFG_VOLT_LOAD_0 ( \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP45 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP45_M ) & \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP25 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP25_M ) & \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TP5 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TP5_M ) & \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_0_VDDR_EXT_TM15 )) << CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_S ) | ~CCFG_VOLT_LOAD_0_VDDR_EXT_TM15_M ) ) - -#define DEFAULT_CCFG_VOLT_LOAD_1 ( \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP125 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP125_M ) & \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP105 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP105_M ) & \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP85 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP85_M ) & \ - ((((uint32_t)( SET_CCFG_VOLT_LOAD_1_VDDR_EXT_TP65 )) << CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_S ) | ~CCFG_VOLT_LOAD_1_VDDR_EXT_TP65_M ) ) - -#define DEFAULT_CCFG_RTC_OFFSET ( \ - ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P0 )) << CCFG_RTC_OFFSET_RTC_COMP_P0_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P0_M ) & \ - ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P1 )) << CCFG_RTC_OFFSET_RTC_COMP_P1_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P1_M ) & \ - ((((uint32_t)( SET_CCFG_RTC_OFFSET_RTC_COMP_P2 )) << CCFG_RTC_OFFSET_RTC_COMP_P2_S ) | ~CCFG_RTC_OFFSET_RTC_COMP_P2_M ) ) - -#define DEFAULT_CCFG_FREQ_OFFSET ( \ - ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P0 )) << CCFG_FREQ_OFFSET_HF_COMP_P0_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P0_M ) & \ - ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P1 )) << CCFG_FREQ_OFFSET_HF_COMP_P1_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P1_M ) & \ - ((((uint32_t)( SET_CCFG_FREQ_OFFSET_HF_COMP_P2 )) << CCFG_FREQ_OFFSET_HF_COMP_P2_S ) | ~CCFG_FREQ_OFFSET_HF_COMP_P2_M ) ) - -#define DEFAULT_CCFG_IEEE_MAC_0 SET_CCFG_IEEE_MAC_0 -#define DEFAULT_CCFG_IEEE_MAC_1 SET_CCFG_IEEE_MAC_1 -#define DEFAULT_CCFG_IEEE_BLE_0 SET_CCFG_IEEE_BLE_0 -#define DEFAULT_CCFG_IEEE_BLE_1 SET_CCFG_IEEE_BLE_1 - -#define DEFAULT_CCFG_BL_CONFIG ( \ - ((((uint32_t)( SET_CCFG_BL_CONFIG_BOOTLOADER_ENABLE )) << CCFG_BL_CONFIG_BOOTLOADER_ENABLE_S ) | ~CCFG_BL_CONFIG_BOOTLOADER_ENABLE_M ) & \ - ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_LEVEL )) << CCFG_BL_CONFIG_BL_LEVEL_S ) | ~CCFG_BL_CONFIG_BL_LEVEL_M ) & \ - ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_PIN_NUMBER )) << CCFG_BL_CONFIG_BL_PIN_NUMBER_S ) | ~CCFG_BL_CONFIG_BL_PIN_NUMBER_M ) & \ - ((((uint32_t)( SET_CCFG_BL_CONFIG_BL_ENABLE )) << CCFG_BL_CONFIG_BL_ENABLE_S ) | ~CCFG_BL_CONFIG_BL_ENABLE_M ) ) - -#define DEFAULT_CCFG_ERASE_CONF ( \ - ((((uint32_t)( SET_CCFG_ERASE_CONF_CHIP_ERASE_DIS_N )) << CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_CHIP_ERASE_DIS_N_M ) & \ - ((((uint32_t)( SET_CCFG_ERASE_CONF_BANK_ERASE_DIS_N )) << CCFG_ERASE_CONF_BANK_ERASE_DIS_N_S ) | ~CCFG_ERASE_CONF_BANK_ERASE_DIS_N_M ) ) - -#define DEFAULT_CCFG_CCFG_TI_OPTIONS ( \ - ((((uint32_t)( SET_CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE )) << CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_S ) | ~CCFG_CCFG_TI_OPTIONS_TI_FA_ENABLE_M ) ) - -#define DEFAULT_CCFG_CCFG_TAP_DAP_0 ( \ - ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_CPU_DAP_ENABLE_M ) & \ - ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_PWRPROF_TAP_ENABLE_M ) & \ - ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_0_TEST_TAP_ENABLE_M ) ) - -#define DEFAULT_CCFG_CCFG_TAP_DAP_1 ( \ - ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST2_TAP_ENABLE_M ) & \ - ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_PBIST1_TAP_ENABLE_M ) & \ - ((((uint32_t)( SET_CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE )) << CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_S ) | ~CCFG_CCFG_TAP_DAP_1_AON_TAP_ENABLE_M ) ) - -#define DEFAULT_CCFG_IMAGE_VALID_CONF SET_CCFG_IMAGE_VALID_CONF_IMAGE_VALID - -#define DEFAULT_CCFG_CCFG_PROT_31_0 SET_CCFG_CCFG_PROT_31_0 -#define DEFAULT_CCFG_CCFG_PROT_63_32 SET_CCFG_CCFG_PROT_63_32 -#define DEFAULT_CCFG_CCFG_PROT_95_64 SET_CCFG_CCFG_PROT_95_64 -#define DEFAULT_CCFG_CCFG_PROT_127_96 SET_CCFG_CCFG_PROT_127_96 - -//***************************************************************************** -// -// Customer Configuration Area in Lock Page -// -//***************************************************************************** -#if defined(__IAR_SYSTEMS_ICC__) -__root const ccfg_t __ccfg @ ".ccfg" = -#elif defined(__TI_COMPILER_VERSION__) -#pragma DATA_SECTION(__ccfg, ".ccfg") -#pragma RETAIN(__ccfg) -const ccfg_t __ccfg = -#else -/* Modified for Zephyr to use __ti_ccfg_section */ -const ccfg_t __ti_ccfg_section __ccfg = -#endif -{ // Mapped to address - DEFAULT_CCFG_EXT_LF_CLK , // 0x50003FA8 (0x50003xxx maps to last - DEFAULT_CCFG_MODE_CONF_1 , // 0x50003FAC sector in FLASH. - DEFAULT_CCFG_SIZE_AND_DIS_FLAGS , // 0x50003FB0 Independent of FLASH size) - DEFAULT_CCFG_MODE_CONF , // 0x50003FB4 - DEFAULT_CCFG_VOLT_LOAD_0 , // 0x50003FB8 - DEFAULT_CCFG_VOLT_LOAD_1 , // 0x50003FBC - DEFAULT_CCFG_RTC_OFFSET , // 0x50003FC0 - DEFAULT_CCFG_FREQ_OFFSET , // 0x50003FC4 - DEFAULT_CCFG_IEEE_MAC_0 , // 0x50003FC8 - DEFAULT_CCFG_IEEE_MAC_1 , // 0x50003FCC - DEFAULT_CCFG_IEEE_BLE_0 , // 0x50003FD0 - DEFAULT_CCFG_IEEE_BLE_1 , // 0x50003FD4 - DEFAULT_CCFG_BL_CONFIG , // 0x50003FD8 - DEFAULT_CCFG_ERASE_CONF , // 0x50003FDC - DEFAULT_CCFG_CCFG_TI_OPTIONS , // 0x50003FE0 - DEFAULT_CCFG_CCFG_TAP_DAP_0 , // 0x50003FE4 - DEFAULT_CCFG_CCFG_TAP_DAP_1 , // 0x50003FE8 - DEFAULT_CCFG_IMAGE_VALID_CONF , // 0x50003FEC - DEFAULT_CCFG_CCFG_PROT_31_0 , // 0x50003FF0 - DEFAULT_CCFG_CCFG_PROT_63_32 , // 0x50003FF4 - DEFAULT_CCFG_CCFG_PROT_95_64 , // 0x50003FF8 - DEFAULT_CCFG_CCFG_PROT_127_96 , // 0x50003FFC -}; - -#endif // __CCFC_C__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/CMakeLists.txt b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/CMakeLists.txt deleted file mode 100644 index a714f725e92..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -zephyr_include_directories( - . - inc - driverlib - ) -zephyr_compile_definitions( - USE_CC3220_ROM_DRV_API - ) - -zephyr_library() -zephyr_library_compile_definitions(${COMPILER}) -# pin.c required by ti/drivers/spi/SPICC32XXDMA.c -# prcm.c required by rom_patch.h (i.e., can't use ROM version). -# utils.c required by prcm.c (calling UtilsDelay). -zephyr_library_sources( - driverlib/utils.c - driverlib/prcm.c - driverlib/pin.c - ) diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/adc.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/adc.c deleted file mode 100644 index c36561c9553..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/adc.c +++ /dev/null @@ -1,693 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// adc.c -// -// Driver for the ADC module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup ADC_Analog_to_Digital_Converter_api -//! @{ -// -//***************************************************************************** -#include "inc/hw_types.h" -#include "inc/hw_memmap.h" -#include "inc/hw_ints.h" -#include "inc/hw_adc.h" -#include "inc/hw_apps_config.h" -#include "interrupt.h" -#include "adc.h" - - -//***************************************************************************** -// -//! Enables the ADC -//! -//! \param ulBase is the base address of the ADC -//! -//! This function sets the ADC global enable -//! -//! \return None. -// -//***************************************************************************** -void ADCEnable(unsigned long ulBase) -{ - // - // Set the global enable bit in the control register. - // - HWREG(ulBase + ADC_O_ADC_CTRL) |= 0x1; -} - -//***************************************************************************** -// -//! Disable the ADC -//! -//! \param ulBase is the base address of the ADC -//! -//! This function clears the ADC global enable -//! -//! \return None. -// -//***************************************************************************** -void ADCDisable(unsigned long ulBase) -{ - // - // Clear the global enable bit in the control register. - // - HWREG(ulBase + ADC_O_ADC_CTRL) &= ~0x1 ; -} - -//***************************************************************************** -// -//! Enables specified ADC channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! -//! This function enables specified ADC channel and configures the -//! pin as analog pin. -//! -//! \return None. -// -//***************************************************************************** -void ADCChannelEnable(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulCh; - - ulCh = (ulChannel == ADC_CH_0)? 0x02 : - (ulChannel == ADC_CH_1)? 0x04 : - (ulChannel == ADC_CH_2)? 0x08 : 0x10; - - HWREG(ulBase + ADC_O_ADC_CH_ENABLE) |= ulCh; -} - -//***************************************************************************** -// -//! Disables specified ADC channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channelsber -//! -//! This function disables specified ADC channel. -//! -//! \return None. -// -//***************************************************************************** -void ADCChannelDisable(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulCh; - - ulCh = (ulChannel == ADC_CH_0)? 0x02 : - (ulChannel == ADC_CH_1)? 0x04 : - (ulChannel == ADC_CH_2)? 0x08 : 0x10; - - HWREG(ulBase + ADC_O_ADC_CH_ENABLE) &= ~ulCh; -} - -//***************************************************************************** -// -//! Enables and registers ADC interrupt handler for specified channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! \param pfnHandler is a pointer to the function to be called when the -//! ADC channel interrupt occurs. -//! -//! This function enables and registers ADC interrupt handler for specified -//! channel. Individual interrupt for each channel should be enabled using -//! \sa ADCIntEnable(). It is the interrupt handler's responsibility to clear -//! the interrupt source. -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! \return None. -// -//***************************************************************************** -void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel, - void (*pfnHandler)(void)) -{ - unsigned long ulIntNo; - - // - // Get the interrupt number associted with the specified channel - // - ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 : - (ulChannel == ADC_CH_1)? INT_ADCCH1 : - (ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3; - - // - // Register the interrupt handler - // - IntRegister(ulIntNo,pfnHandler); - - // - // Enable ADC interrupt - // - IntEnable(ulIntNo); -} - - -//***************************************************************************** -// -//! Disables and unregisters ADC interrupt handler for specified channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! -//! This function disables and unregisters ADC interrupt handler for specified -//! channel. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! \return None. -// -//***************************************************************************** -void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulIntNo; - - // - // Get the interrupt number associted with the specified channel - // - ulIntNo = (ulChannel == ADC_CH_0)? INT_ADCCH0 : - (ulChannel == ADC_CH_1)? INT_ADCCH1 : - (ulChannel == ADC_CH_2)? INT_ADCCH2 : INT_ADCCH3; - - // - // Disable ADC interrupt - // - IntDisable(ulIntNo); - - // - // Unregister the interrupt handler - // - IntUnregister(ulIntNo); -} - -//***************************************************************************** -// -//! Enables individual interrupt sources for specified channel -//! -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated ADC interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! - \b ADC_DMA_DONE for DMA done -//! - \b ADC_FIFO_OVERFLOW for FIFO over flow -//! - \b ADC_FIFO_UNDERFLOW for FIFO under flow -//! - \b ADC_FIFO_EMPTY for FIFO empty -//! - \b ADC_FIFO_FULL for FIFO full -//! -//! \return None. -// -//***************************************************************************** -void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel, - unsigned long ulIntFlags) -{ - unsigned long ulOffset; - unsigned long ulDmaMsk; - - // - // Enable DMA Done interrupt - // - if(ulIntFlags & ADC_DMA_DONE) - { - ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000: - (ulChannel == ADC_CH_1)?0x00002000: - (ulChannel == ADC_CH_2)?0x00004000:0x00008000; - - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk; - } - - ulIntFlags = ulIntFlags & 0x0F; - // - // Get the interrupt enable register offset for specified channel - // - ulOffset = ADC_O_adc_ch0_irq_en + ulChannel; - - // - // Unmask the specified interrupts - // - HWREG(ulBase + ulOffset) |= (ulIntFlags & 0xf); -} - - -//***************************************************************************** -// -//! Disables individual interrupt sources for specified channel -//! -//! -//! \param ulBase is the base address of the ADC. -//! \param ulChannel is one of the valid ADC channels -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function disables the indicated ADC interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The parameters\e ulIntFlags and \e ulChannel should be as explained in -//! ADCIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel, - unsigned long ulIntFlags) -{ - unsigned long ulOffset; - unsigned long ulDmaMsk; - - // - // Disable DMA Done interrupt - // - if(ulIntFlags & ADC_DMA_DONE) - { - ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000: - (ulChannel == ADC_CH_1)?0x00002000: - (ulChannel == ADC_CH_2)?0x00004000:0x00008000; - - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk; - } - - // - // Get the interrupt enable register offset for specified channel - // - ulOffset = ADC_O_adc_ch0_irq_en + ulChannel; - - // - // Unmask the specified interrupts - // - HWREG(ulBase + ulOffset) &= ~ulIntFlags; -} - - -//***************************************************************************** -// -//! Gets the current channel interrupt status -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! -//! This function returns the interrupt status of the specified ADC channel. -//! -//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable(). -//! -//! \return Return the ADC channel interrupt status, enumerated as a bit -//! field of values described in ADCIntEnable() -// -//***************************************************************************** -unsigned long ADCIntStatus(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulOffset; - unsigned long ulDmaMsk; - unsigned long ulIntStatus; - - // - // Get DMA Done interrupt status - // - ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000: - (ulChannel == ADC_CH_1)?0x00002000: - (ulChannel == ADC_CH_2)?0x00004000:0x00008000; - - ulIntStatus = HWREG(APPS_CONFIG_BASE + - APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED)& ulDmaMsk; - - - // - // Get the interrupt enable register offset for specified channel - // - ulOffset = ADC_O_adc_ch0_irq_status + ulChannel; - - // - // Read ADC interrupt status - // - ulIntStatus |= HWREG(ulBase + ulOffset) & 0xf; - - // - // Return the current interrupt status - // - return(ulIntStatus); -} - - -//***************************************************************************** -// -//! Clears the current channel interrupt sources -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. -//! -//! This function clears individual interrupt source for the specified -//! ADC channel. -//! -//! The parameter \e ulChannel should be as explained in \sa ADCIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void ADCIntClear(unsigned long ulBase, unsigned long ulChannel, - unsigned long ulIntFlags) -{ - unsigned long ulOffset; - unsigned long ulDmaMsk; - - // - // Clear DMA Done interrupt - // - if(ulIntFlags & ADC_DMA_DONE) - { - ulDmaMsk = (ulChannel == ADC_CH_0)?0x00001000: - (ulChannel == ADC_CH_1)?0x00002000: - (ulChannel == ADC_CH_2)?0x00004000:0x00008000; - - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk; - } - - // - // Get the interrupt enable register offset for specified channel - // - ulOffset = ADC_O_adc_ch0_irq_status + ulChannel; - - // - // Clear the specified interrupts - // - HWREG(ulBase + ulOffset) = (ulIntFlags & ~(ADC_DMA_DONE)); -} - -//***************************************************************************** -// -//! Enables the ADC DMA operation for specified channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! -//! This function enables the DMA operation for specified ADC channel -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! \return None. -// -//***************************************************************************** -void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulBitMask; - - // - // Get the bit mask for enabling DMA for specified channel - // - ulBitMask = (ulChannel == ADC_CH_0)?0x01: - (ulChannel == ADC_CH_1)?0x04: - (ulChannel == ADC_CH_2)?0x10:0x40; - - // - // Enable DMA request for the specified channel - // - HWREG(ulBase + ADC_O_adc_dma_mode_en) |= ulBitMask; -} - -//***************************************************************************** -// -//! Disables the ADC DMA operation for specified channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels -//! -//! This function disables the DMA operation for specified ADC channel -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! \return None. -// -//***************************************************************************** -void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulBitMask; - - // - // Get the bit mask for disabling DMA for specified channel - // - ulBitMask = (ulChannel == ADC_CH_0)?0x01: - (ulChannel == ADC_CH_1)?0x04: - (ulChannel == ADC_CH_2)?0x10:0x40; - - // - // Disable DMA request for the specified channel - // - HWREG(ulBase + ADC_O_adc_dma_mode_en) &= ~ulBitMask; -} - -//***************************************************************************** -// -//! Configures the ADC internal timer -//! -//! \param ulBase is the base address of the ADC -//! \param ulValue is wrap arround value of the timer -//! -//! This function Configures the ADC internal timer. The ADC timer is a 17 bit -//! used to timestamp the ADC data samples internally. -//! User can read the timestamp along with the sample from the FIFO register(s). -//! Each sample in the FIFO contains 14 bit actual data and 18 bit timestamp -//! -//! The parameter \e ulValue can take any value between 0 - 2^17 -//! -//! \returns None. -// -//***************************************************************************** -void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue) -{ - unsigned long ulReg; - - // - // Read the currrent config - // - ulReg = HWREG(ulBase + ADC_O_adc_timer_configuration); - - // - // Mask and set timer count field - // - ulReg = ((ulReg & ~0x1FFFF) | (ulValue & 0x1FFFF)); - - // - // Set the timer count value - // - HWREG(ulBase + ADC_O_adc_timer_configuration) = ulReg; -} - -//***************************************************************************** -// -//! Resets ADC internal timer -//! -//! \param ulBase is the base address of the ADC -//! -//! This function resets 17-bit ADC internal timer -//! -//! \returns None. -// -//***************************************************************************** -void ADCTimerReset(unsigned long ulBase) -{ - // - // Reset the timer - // - HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 24); -} - -//***************************************************************************** -// -//! Enables ADC internal timer -//! -//! \param ulBase is the base address of the ADC -//! -//! This function enables 17-bit ADC internal timer -//! -//! \returns None. -// -//***************************************************************************** -void ADCTimerEnable(unsigned long ulBase) -{ - // - // Enable the timer - // - HWREG(ulBase + ADC_O_adc_timer_configuration) |= (1 << 25); -} - -//***************************************************************************** -// -//! Disables ADC internal timer -//! -//! \param ulBase is the base address of the ADC -//! -//! This function disables 17-bit ADC internal timer -//! -//! \returns None. -// -//***************************************************************************** -void ADCTimerDisable(unsigned long ulBase) -{ - // - // Disable the timer - // - HWREG(ulBase + ADC_O_adc_timer_configuration) &= ~(1 << 25); -} - -//***************************************************************************** -// -//! Gets the current value of ADC internal timer -//! -//! \param ulBase is the base address of the ADC -//! -//! This function the current value of 17-bit ADC internal timer -//! -//! \returns Return the current value of ADC internal timer. -// -//***************************************************************************** -unsigned long ADCTimerValueGet(unsigned long ulBase) -{ - return(HWREG(ulBase + ADC_O_adc_timer_current_count)); -} - -//***************************************************************************** -// -//! Gets the current FIFO level for specified ADC channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels. -//! -//! This function returns the current FIFO level for specified ADC channel. -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! \returns Return the current FIFO level for specified channel -// -//***************************************************************************** -unsigned char ADCFIFOLvlGet(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulOffset; - - // - // Get the fifo level register offset for specified channel - // - ulOffset = ADC_O_adc_ch0_fifo_lvl + ulChannel; - - // - // Return FIFO level - // - return(HWREG(ulBase + ulOffset) & 0x7); -} - -//***************************************************************************** -// -//! Reads FIFO for specified ADC channel -//! -//! \param ulBase is the base address of the ADC -//! \param ulChannel is one of the valid ADC channels. -//! -//! This function returns one data sample from the channel fifo as specified by -//! \e ulChannel parameter. -//! -//! The parameter \e ulChannel should be one of the following -//! -//! - \b ADC_CH_0 for channel 0 -//! - \b ADC_CH_1 for channel 1 -//! - \b ADC_CH_2 for channel 2 -//! - \b ADC_CH_3 for channel 3 -//! -//! \returns Return one data sample from the channel fifo. -// -//***************************************************************************** -unsigned long ADCFIFORead(unsigned long ulBase, unsigned long ulChannel) -{ - unsigned long ulOffset; - - // - // Get the fifo register offset for specified channel - // - ulOffset = ADC_O_channel0FIFODATA + ulChannel; - - // - // Return FIFO level - // - return(HWREG(ulBase + ulOffset)); -} - - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/adc.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/adc.h deleted file mode 100644 index 6f7095050de..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/adc.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// adc.h -// -// Defines and Macros for the ADC. -// -//***************************************************************************** - -#ifndef __ADC_H__ -#define __ADC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// Values that can be passed to APIs as ulChannel parameter -//***************************************************************************** -#define ADC_CH_0 0x00000000 -#define ADC_CH_1 0x00000008 -#define ADC_CH_2 0x00000010 -#define ADC_CH_3 0x00000018 - - -//***************************************************************************** -// -// Values that can be passed to ADCIntEnable(), ADCIntDisable() -// and ADCIntClear() as ulIntFlags, and returned from ADCIntStatus() -// -//***************************************************************************** -#define ADC_DMA_DONE 0x00000010 -#define ADC_FIFO_OVERFLOW 0x00000008 -#define ADC_FIFO_UNDERFLOW 0x00000004 -#define ADC_FIFO_EMPTY 0x00000002 -#define ADC_FIFO_FULL 0x00000001 - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void ADCEnable(unsigned long ulBase); -extern void ADCDisable(unsigned long ulBase); -extern void ADCChannelEnable(unsigned long ulBase,unsigned long ulChannel); -extern void ADCChannelDisable(unsigned long ulBase,unsigned long ulChannel); -extern void ADCIntRegister(unsigned long ulBase, unsigned long ulChannel, - void (*pfnHandler)(void)); -extern void ADCIntUnregister(unsigned long ulBase, unsigned long ulChannel); -extern void ADCIntEnable(unsigned long ulBase, unsigned long ulChannel, - unsigned long ulIntFlags); -extern void ADCIntDisable(unsigned long ulBase, unsigned long ulChannel, - unsigned long ulIntFlags); -extern unsigned long ADCIntStatus(unsigned long ulBase,unsigned long ulChannel); -extern void ADCIntClear(unsigned long ulBase, unsigned long ulChannel, - unsigned long ulIntFlags); -extern void ADCDMAEnable(unsigned long ulBase, unsigned long ulChannel); -extern void ADCDMADisable(unsigned long ulBase, unsigned long ulChannel); -extern void ADCTimerConfig(unsigned long ulBase, unsigned long ulValue); -extern void ADCTimerEnable(unsigned long ulBase); -extern void ADCTimerDisable(unsigned long ulBase); -extern void ADCTimerReset(unsigned long ulBase); -extern unsigned long ADCTimerValueGet(unsigned long ulBase); -extern unsigned char ADCFIFOLvlGet(unsigned long ulBase, - unsigned long ulChannel); -extern unsigned long ADCFIFORead(unsigned long ulBase, - unsigned long ulChannel); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __ADC_H__ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/aes.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/aes.c deleted file mode 100644 index dacc7914457..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/aes.c +++ /dev/null @@ -1,1361 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// aes.c -// -// Driver for the AES module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup AES_Advanced_Encryption_Standard_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_aes.h" -#include "inc/hw_dthe.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "aes.h" -#include "debug.h" -#include "interrupt.h" - -#define AES_BLOCK_SIZE_IN_BYTES 16 - -//***************************************************************************** -// -//! Configures the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Config is the configuration of the AES module. -//! -//! This function configures the AES module based on the specified parameters. -//! It does not change any DMA- or interrupt-related parameters. -//! -//! The ui32Config parameter is a bit-wise OR of a number of configuration -//! flags. The valid flags are grouped based on their function. -//! -//! The direction of the operation is specified with only of following flags: -//! -//! - \b AES_CFG_DIR_ENCRYPT - Encryption mode -//! - \b AES_CFG_DIR_DECRYPT - Decryption mode -//! -//! The key size is specified with only one of the following flags: -//! -//! - \b AES_CFG_KEY_SIZE_128BIT - Key size of 128 bits -//! - \b AES_CFG_KEY_SIZE_192BIT - Key size of 192 bits -//! - \b AES_CFG_KEY_SIZE_256BIT - Key size of 256 bits -//! -//! The mode of operation is specified with only one of the following flags. -//! -//! - \b AES_CFG_MODE_ECB - Electronic codebook mode -//! - \b AES_CFG_MODE_CBC - Cipher-block chaining mode -//! - \b AES_CFG_MODE_CFB - Cipher feedback mode -//! - \b AES_CFG_MODE_CTR - Counter mode -//! - \b AES_CFG_MODE_ICM - Integer counter mode -//! - \b AES_CFG_MODE_XTS - Ciphertext stealing mode -//! - \b AES_CFG_MODE_XTS_TWEAKJL - XEX-based tweaked-codebook mode with -//! ciphertext stealing with previous/intermediate tweak value and j loaded -//! - \b AES_CFG_MODE_XTS_K2IJL - XEX-based tweaked-codebook mode with -//! ciphertext stealing with key2, i and j loaded -//! - \b AES_CFG_MODE_XTS_K2ILJ0 - XEX-based tweaked-codebook mode with -//! ciphertext stealing with key2 and i loaded, j = 0 -//! - \b AES_CFG_MODE_F8 - F8 mode -//! - \b AES_CFG_MODE_F9 - F9 mode -//! - \b AES_CFG_MODE_CBCMAC - Cipher block chaining message authentication -//! code mode -//! - \b AES_CFG_MODE_GCM - Galois/counter mode -//! - \b AES_CFG_MODE_GCM_HLY0ZERO - Galois/counter mode with GHASH with H -//! loaded and Y0-encrypted forced to zero -//! - \b AES_CFG_MODE_GCM_HLY0CALC - Galois/counter mode with GHASH with H -//! loaded and Y0-encrypted calculated internally -//! - \b AES_CFG_MODE_GCM_HY0CALC - Galois/Counter mode with autonomous GHASH -//! (both H and Y0-encrypted calculated internally) -//! - \b AES_CFG_MODE_CCM - Counter with CBC-MAC mode -//! -//! The following defines are used to specify the counter width. It is only -//! required to be defined when using CTR, CCM, or GCM modes, only one of the -//! following defines must be used to specify the counter width length: -//! -//! - \b AES_CFG_CTR_WIDTH_32 - Counter is 32 bits -//! - \b AES_CFG_CTR_WIDTH_64 - Counter is 64 bits -//! - \b AES_CFG_CTR_WIDTH_96 - Counter is 96 bits -//! - \b AES_CFG_CTR_WIDTH_128 - Counter is 128 bits -//! -//! Only one of the following defines must be used to specify the length field -//! for CCM operations (L): -//! -//! - \b AES_CFG_CCM_L_2 - 2 bytes -//! - \b AES_CFG_CCM_L_4 - 4 bytes -//! - \b AES_CFG_CCM_L_8 - 8 bytes -//! -//! Only one of the following defines must be used to specify the length of the -//! authentication field for CCM operations (M) through the \e ui32Config -//! argument in the AESConfigSet() function: -//! -//! - \b AES_CFG_CCM_M_4 - 4 bytes -//! - \b AES_CFG_CCM_M_6 - 6 bytes -//! - \b AES_CFG_CCM_M_8 - 8 bytes -//! - \b AES_CFG_CCM_M_10 - 10 bytes -//! - \b AES_CFG_CCM_M_12 - 12 bytes -//! - \b AES_CFG_CCM_M_14 - 14 bytes -//! - \b AES_CFG_CCM_M_16 - 16 bytes -//! -//! \return None. -// -//***************************************************************************** -void -AESConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Config & AES_CFG_DIR_ENCRYPT) || - (ui32Config & AES_CFG_DIR_DECRYPT)); - ASSERT((ui32Config & AES_CFG_KEY_SIZE_128BIT) || - (ui32Config & AES_CFG_KEY_SIZE_192BIT) || - (ui32Config & AES_CFG_KEY_SIZE_256BIT)); - ASSERT((ui32Config & AES_CFG_MODE_ECB) || - (ui32Config & AES_CFG_MODE_CBC) || - (ui32Config & AES_CFG_MODE_CTR) || - (ui32Config & AES_CFG_MODE_ICM) || - (ui32Config & AES_CFG_MODE_CFB) || - (ui32Config & AES_CFG_MODE_XTS_TWEAKJL) || - (ui32Config & AES_CFG_MODE_XTS_K2IJL) || - (ui32Config & AES_CFG_MODE_XTS_K2ILJ0) || - (ui32Config & AES_CFG_MODE_F8) || - (ui32Config & AES_CFG_MODE_F9) || - (ui32Config & AES_CFG_MODE_CTR) || - (ui32Config & AES_CFG_MODE_CBCMAC) || - (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) || - (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) || - (ui32Config & AES_CFG_MODE_GCM_HY0CALC) || - (ui32Config & AES_CFG_MODE_CCM)); - ASSERT(((ui32Config & AES_CFG_MODE_CTR) || - (ui32Config & AES_CFG_MODE_GCM_HLY0ZERO) || - (ui32Config & AES_CFG_MODE_GCM_HLY0CALC) || - (ui32Config & AES_CFG_MODE_GCM_HY0CALC) || - (ui32Config & AES_CFG_MODE_CCM)) && - ((ui32Config & AES_CFG_CTR_WIDTH_32) || - (ui32Config & AES_CFG_CTR_WIDTH_64) || - (ui32Config & AES_CFG_CTR_WIDTH_96) || - (ui32Config & AES_CFG_CTR_WIDTH_128))); - ASSERT((ui32Config & AES_CFG_MODE_CCM) && - ((ui32Config & AES_CFG_CCM_L_2) || - (ui32Config & AES_CFG_CCM_L_4) || - (ui32Config & AES_CFG_CCM_L_8)) && - ((ui32Config & AES_CFG_CCM_M_4) || - (ui32Config & AES_CFG_CCM_M_6) || - (ui32Config & AES_CFG_CCM_M_8) || - (ui32Config & AES_CFG_CCM_M_10) || - (ui32Config & AES_CFG_CCM_M_12) || - (ui32Config & AES_CFG_CCM_M_14) || - (ui32Config & AES_CFG_CCM_M_16))); - - // - // Backup the save context field before updating the register. - // - if(HWREG(ui32Base + AES_O_CTRL) & AES_CTRL_SAVE_CONTEXT) - { - ui32Config |= AES_CTRL_SAVE_CONTEXT; - } - - // - // Write the CTRL register with the new value - // - HWREG(ui32Base + AES_O_CTRL) = ui32Config; -} - -//***************************************************************************** -// -//! Writes the key 1 configuration registers, which are used for encryption or -//! decryption. -//! -//! \param ui32Base is the base address for the AES module. -//! \param pui8Key is an array of bytes, containing the key to be -//! configured. The least significant word in the 0th index. -//! \param ui32Keysize is the size of the key, which must be one of the -//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or -//! \b AES_CFG_KEY_SIZE_256. -//! -//! This function writes key 1 configuration registers based on the key -//! size. This function is used in all modes. -//! -//! \return None. -// -//***************************************************************************** -void -AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key, uint32_t ui32Keysize) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_256BIT)); - - // - // With all key sizes, the first 4 words are written. - // - HWREG(ui32Base + AES_O_KEY1_0) = * ((uint32_t *)(pui8Key + 0)); - HWREG(ui32Base + AES_O_KEY1_1) = * ((uint32_t *)(pui8Key + 4)); - HWREG(ui32Base + AES_O_KEY1_2) = * ((uint32_t *)(pui8Key + 8)); - HWREG(ui32Base + AES_O_KEY1_3) = * ((uint32_t *)(pui8Key + 12)); - - // - // The key is 192 or 256 bits. Write the next 2 words. - // - if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT) - { - HWREG(ui32Base + AES_O_KEY1_4) = * ((uint32_t *)(pui8Key + 16)); - HWREG(ui32Base + AES_O_KEY1_5) = * ((uint32_t *)(pui8Key + 20)); - } - - // - // The key is 256 bits. Write the last 2 words. - // - if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) - { - HWREG(ui32Base + AES_O_KEY1_6) = * ((uint32_t *)(pui8Key + 24)); - HWREG(ui32Base + AES_O_KEY1_7) = * ((uint32_t *)(pui8Key + 28)); - } -} - -//***************************************************************************** -// -//! Writes the key 2 configuration registers, which are used for encryption or -//! decryption. -//! -//! \param ui32Base is the base address for the AES module. -//! \param pui8Key is an array of bytes, containing the key to be -//! configured. The least significant word in the 0th index. -//! \param ui32Keysize is the size of the key, which must be one of the -//! following values: \b AES_CFG_KEY_SIZE_128, \b AES_CFG_KEY_SIZE_192, or -//! \b AES_CFG_KEY_SIZE_256. -//! -//! This function writes the key 2 configuration registers based on the key -//! size. This function is used in the F8, F9, XTS, CCM, and CBC-MAC modes. -//! -//! \return None. -// -//***************************************************************************** -void -AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key, uint32_t ui32Keysize) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Keysize == AES_CFG_KEY_SIZE_128BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_192BIT) || - (ui32Keysize == AES_CFG_KEY_SIZE_256BIT)); - - // - // With all key sizes, the first 4 words are written. - // - HWREG(ui32Base + AES_O_KEY2_0) = * ((uint32_t *)(pui8Key + 0)); - HWREG(ui32Base + AES_O_KEY2_1) = * ((uint32_t *)(pui8Key + 4)); - HWREG(ui32Base + AES_O_KEY2_2) = * ((uint32_t *)(pui8Key + 8)); - HWREG(ui32Base + AES_O_KEY2_3) = * ((uint32_t *)(pui8Key + 12)); - - // - // The key is 192 or 256 bits. Write the next 2 words. - // - if(ui32Keysize != AES_CFG_KEY_SIZE_128BIT) - { - HWREG(ui32Base + AES_O_KEY2_4) = * ((uint32_t *)(pui8Key + 16)); - HWREG(ui32Base + AES_O_KEY2_5) = * ((uint32_t *)(pui8Key + 20)); - } - - // - // The key is 256 bits. Write the last 2 words. - // - if(ui32Keysize == AES_CFG_KEY_SIZE_256BIT) - { - HWREG(ui32Base + AES_O_KEY2_6) = * ((uint32_t *)(pui8Key + 24)); - HWREG(ui32Base + AES_O_KEY2_7) = * ((uint32_t *)(pui8Key + 28)); - } -} - -//***************************************************************************** -// -//! Writes key 3 configuration registers, which are used for encryption or -//! decryption. -//! -//! \param ui32Base is the base address for the AES module. -//! \param pui8Key is a pointer to an array bytes, containing -//! the key to be configured. The least significant word is in the 0th index. -//! -//! This function writes the key 2 configuration registers with key 3 data -//! used in CBC-MAC and F8 modes. This key is always 128 bits. -//! -//! \return None. -// -//***************************************************************************** -void -AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the key into the upper 4 key registers - // - HWREG(ui32Base + AES_O_KEY2_4) = * ((uint32_t *)(pui8Key + 0)); - HWREG(ui32Base + AES_O_KEY2_5) = * ((uint32_t *)(pui8Key + 4)); - HWREG(ui32Base + AES_O_KEY2_6) = * ((uint32_t *)(pui8Key + 8)); - HWREG(ui32Base + AES_O_KEY2_7) = * ((uint32_t *)(pui8Key + 12)); -} - -//***************************************************************************** -// -//! Writes the Initial Vector (IV) register, needed in some of the AES Modes. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8IVdata is an array of 16 bytes (128 bits), containing the IV -//! value to be configured. The least significant word is in the 0th index. -//! -//! This functions writes the initial vector registers in the AES module. -//! -//! \return None. -// -//***************************************************************************** -void -AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the initial vector registers. - // - HWREG(ui32Base + AES_O_IV_IN_0) = *((uint32_t *)(pui8IVdata+0)); - HWREG(ui32Base + AES_O_IV_IN_1) = *((uint32_t *)(pui8IVdata+4)); - HWREG(ui32Base + AES_O_IV_IN_2) = *((uint32_t *)(pui8IVdata+8)); - HWREG(ui32Base + AES_O_IV_IN_3) = *((uint32_t *)(pui8IVdata+12)); -} - - -//***************************************************************************** -// -//! Reads the Initial Vector (IV) register, needed in some of the AES Modes. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8IVdata is pointer to an array of 16 bytes. -//! -//! This functions reads the initial vector registers in the AES module. -//! -//! \return None. -// -//***************************************************************************** -void -AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the initial vector registers. - // - *((uint32_t *)(pui8IVdata+ 0)) = HWREG(ui32Base + AES_O_IV_IN_0); - *((uint32_t *)(pui8IVdata+ 4)) = HWREG(ui32Base + AES_O_IV_IN_1); - *((uint32_t *)(pui8IVdata+ 8)) = HWREG(ui32Base + AES_O_IV_IN_2); - *((uint32_t *)(pui8IVdata+12)) = HWREG(ui32Base + AES_O_IV_IN_3); -} - -//***************************************************************************** -// -//! Saves the tag registers to a user-defined location. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8TagData is pointer to the location that stores the tag data. -//! -//! This function stores the tag data for use authenticated encryption and -//! decryption operations. -//! -//! \return None. -// -//***************************************************************************** -void -AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Read the tag data. - // - *((uint32_t *)(pui8TagData+0)) = HWREG((ui32Base + AES_O_TAG_OUT_0)); - *((uint32_t *)(pui8TagData+4)) = HWREG((ui32Base + AES_O_TAG_OUT_1)); - *((uint32_t *)(pui8TagData+8)) = HWREG((ui32Base + AES_O_TAG_OUT_2)); - *((uint32_t *)(pui8TagData+12)) = HWREG((ui32Base + AES_O_TAG_OUT_3)); -} - -//***************************************************************************** -// -//! Used to set the write crypto data length in the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui64Length is the crypto data length in bytes. -//! -//! This function stores the cryptographic data length in blocks for all modes. -//! Data lengths up to (2^61 - 1) bytes are allowed. For GCM, any value up -//! to (2^36 - 2) bytes are allowed because a 32-bit block counter is used. For -//! basic modes (ECB/CBC/CTR/ICM/CFB128), zero can be programmed into the -//! length field, indicating that the length is infinite. -//! -//! When this function is called, the engine is triggered to start using -//! this context. -//! -//! \note This length does not include the authentication-only data used in -//! some modes. Use the AESAuthLengthSet() function to specify the -//! authentication data length. -//! -//! \return None -// -//***************************************************************************** -void -AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length register by shifting the 64-bit ui64Length. - // - HWREG(ui32Base + AES_O_C_LENGTH_0) = (uint32_t)(ui64Length); - HWREG(ui32Base + AES_O_C_LENGTH_1) = (uint32_t)(ui64Length >> 32); -} - -//***************************************************************************** -// -//! Sets the optional additional authentication data (AAD) length. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Length is the length in bytes. -//! -//! This function is only used to write the authentication data length in the -//! combined modes (GCM or CCM) and XTS mode. Supported AAD lengths for CCM -//! are from 0 to (2^16 - 28) bytes. For GCM, any value up to (2^32 - 1) can -//! be used. For XTS mode, this register is used to load j. Loading of j is -//! only required if j != 0. j represents the sequential number of the 128-bit -//! blocks inside the data unit. Consequently, j must be multiplied by 16 -//! when passed to this function, thereby placing the block number in -//! bits [31:4] of the register. -//! -//! When this function is called, the engine is triggered to start using -//! this context for GCM and CCM. -//! -//! \return None -// -//***************************************************************************** -void -AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length into the register. - // - HWREG(ui32Base + AES_O_AUTH_LENGTH) = ui32Length; -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers without blocking. -//! This api writes data in blocks -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Dest is a pointer to an array of words of data. -//! \param ui8Length the length can be from 1 to 16 -//! -//! This function reads a block of either plaintext or ciphertext out of the -//! AES module. If the output data is not ready, the function returns -//! false. If the read completed successfully, the function returns true. -//! A block is 16 bytes or 4 words. -//! -//! \return true or false. -// -//***************************************************************************** -bool -AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length) -{ - volatile uint32_t pui32Dest[4]; - uint8_t ui8BytCnt; - uint8_t *pui8DestTemp; - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - if((ui8Length == 0)||(ui8Length>16)) - { - return(false); - } - - // - // Check if the output is ready before reading the data. If it not ready, - // return false. - // - if((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - return(false); - } - - // - // Read a block of data from the data registers - // - pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3); - pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2); - pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1); - pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0); - - // - //Copy the data to a block memory - // - pui8DestTemp = (uint8_t *)pui32Dest; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt); - } - // - // Read successful, return true. - // - return(true); -} - - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers with blocking. -//! This api writes data in blocks -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Dest is a pointer to an array of words. -//! \param ui8Length is the length of data in bytes to be read. -//! ui8Length can be from 1 to 16 -//! -//! This function reads a block of either plaintext or ciphertext out of the -//! AES module. If the output is not ready, the function waits until it -//! is ready. A block is 16 bytes or 4 words. -//! -//! \return None. -// -//***************************************************************************** - -void -AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length) -{ - volatile uint32_t pui32Dest[4]; - uint8_t ui8BytCnt; - uint8_t *pui8DestTemp; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - if((ui8Length == 0)||(ui8Length>16)) - { - return; - } - - - // - // Wait for the output to be ready before reading the data. - // - while((AES_CTRL_OUTPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - } - - // - // Read a block of data from the data registers - // - pui32Dest[0] = HWREG(ui32Base + AES_O_DATA_IN_3); - pui32Dest[1] = HWREG(ui32Base + AES_O_DATA_IN_2); - pui32Dest[2] = HWREG(ui32Base + AES_O_DATA_IN_1); - pui32Dest[3] = HWREG(ui32Base + AES_O_DATA_IN_0); - // - //Copy the data to a block memory - // - pui8DestTemp = (uint8_t *)pui32Dest; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt); - } - - return; -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers without blocking. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Src is a pointer to an array of words of data. -//! \param ui8Length the length can be from 1 to 16 -//! -//! This function writes a block of either plaintext or ciphertext into the -//! AES module. If the input is not ready, the function returns false -//! If the write completed successfully, the function returns true. -//! -//! \return True or false. -// -//***************************************************************************** -bool -AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length) -{ - volatile uint32_t pui32Src[4]={0,0,0,0}; - uint8_t ui8BytCnt; - uint8_t *pui8SrcTemp; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - if((ui8Length == 0)||(ui8Length>16)) - { - return(false); - } - - // - // Check if the input is ready. If not, then return false. - // - if(!(AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL)))) - { - return(false); - } - - - // - //Copy the data to a block memory - // - pui8SrcTemp = (uint8_t *)pui32Src; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt); - } - // - // Write a block of data into the data registers. - // - HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0]; - HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1]; - HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2]; - HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3]; - - // - // Write successful, return true. - // - return(true); -} - - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers with blocking. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Src is a pointer to an array of bytes. -//! \param ui8Length the length can be from 1 to 16 -//! -//! This function writes a block of either plaintext or ciphertext into the -//! AES module. If the input is not ready, the function waits until it is -//! ready before performing the write. -//! -//! \return None. -// -//***************************************************************************** - -void -AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length) -{ - volatile uint32_t pui32Src[4]={0,0,0,0}; - uint8_t ui8BytCnt; - uint8_t *pui8SrcTemp; - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - if((ui8Length == 0)||(ui8Length>16)) - { - return; - } - // - // Wait for input ready. - // - while((AES_CTRL_INPUT_READY & (HWREG(ui32Base + AES_O_CTRL))) == 0) - { - } - - // - //Copy the data to a block memory - // - pui8SrcTemp = (uint8_t *)pui32Src; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt); - } - - // - // Write a block of data into the data registers. - // - HWREG(ui32Base + AES_O_DATA_IN_3) = pui32Src[0]; - HWREG(ui32Base + AES_O_DATA_IN_2) = pui32Src[1]; - HWREG(ui32Base + AES_O_DATA_IN_1) = pui32Src[2]; - HWREG(ui32Base + AES_O_DATA_IN_0) = pui32Src[3]; -} - - -//***************************************************************************** -// -//! Used to process(transform) blocks of data, either encrypt or decrypt it. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Src is a pointer to the memory location where the input data -//! is stored. -//! \param pui8Dest is a pointer to the memory location output is written. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! -//! This function iterates the encryption or decryption mechanism number over -//! the data length. Before calling this function, ensure that the AES -//! module is properly configured the key, data size, mode, etc. Only ECB, -//! CBC, CTR, ICM, CFB, XTS and F8 operating modes should be used. The data -//! is processed in 4-word (16-byte) blocks. -//! -//! \note This function only supports values of \e ui32Length less than 2^32, -//! because the memory size is restricted to between 0 to 2^32 bytes. -//! -//! \return Returns true if data was processed successfully. Returns false -//! if data processing failed. -// -//***************************************************************************** -bool -AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest, - uint32_t ui32Length) -{ - uint32_t ui32Count, ui32BlkCount, ui32ByteCount; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length register first, which triggers the engine to start - // using this context. - // - AESDataLengthSet(AES_BASE, (uint64_t) ui32Length); - - // - // Now loop until the blocks are written. - // - ui32BlkCount = ui32Length/16; - for(ui32Count = 0; ui32Count < ui32BlkCount; ui32Count += 1) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui8Src + (ui32Count*16) ,16); - - // - // Read the data registers. - // - AESDataRead(ui32Base, pui8Dest + (ui32Count*16) ,16); - - } - - // - //Now handle the residue bytes - // - ui32ByteCount = ui32Length%16; - if(ui32ByteCount) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui8Src + (16*ui32BlkCount) ,ui32ByteCount); - - // - // Read the data registers. - // - AESDataRead(ui32Base, pui8Dest + (16*ui32BlkCount) ,ui32ByteCount); - } - - - - // - // Return true to indicate successful completion of the function. - // - return(true); -} -//***************************************************************************** -// -//! Used to generate message authentication code (MAC) using CBC-MAC and F9 mode. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Src is a pointer to the memory location where the input data -//! is stored. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! \param pui8Tag is a pointer to a 4-word array where the hash tag is -//! written. -//! -//! This function processes data to produce a hash tag that can be used tor -//! authentication. Before calling this function, ensure that the AES -//! module is properly configured the key, data size, mode, etc. Only -//! CBC-MAC and F9 modes should be used. -//! -//! \return Returns true if data was processed successfully. Returns false -//! if data processing failed. -// -//***************************************************************************** -bool -AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src, uint32_t ui32Length, - uint8_t *pui8Tag) -{ - uint32_t ui32Count, ui32BlkCount, ui32ByteCount; - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Write the length register first, which triggers the engine to start - // using this context. - // - AESDataLengthSet(AES_BASE, (uint64_t) ui32Length); - - // - // Write the data registers. - // - - // - // Now loop until the blocks are written. - // - ui32BlkCount = ui32Length/16; - for(ui32Count = 0; ui32Count < ui32BlkCount; ui32Count += 1) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui8Src + ui32Count*16 ,16); - } - - // - //Now handle the residue bytes - // - ui32ByteCount = ui32Length%16; - if(ui32ByteCount) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui8Src + (ui32Count*ui32BlkCount) ,ui32ByteCount); - } - - // - // Wait for the context data regsiters to be ready. - // - while((AES_CTRL_SVCTXTRDY & (HWREG(AES_BASE + AES_O_CTRL))) == 0) - { - } - - // - // Read the hash tag value. - // - AESTagRead(AES_BASE, pui8Tag); - - // - // Return true to indicate successful completion of the function. - // - return(true); -} - -//***************************************************************************** -// -//! Used for Authenticated encryption (AE) of the data. Processes and authenticates blocks of data, -//! either encrypt the data or decrypt the data. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pui8Src is a pointer to the memory location where the input data -//! is stored. The data must be padded to the 16-byte boundary. -//! \param pui8Dest is a pointer to the memory location output is written. -//! The space for written data must be rounded up to the 16-byte boundary. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! \param pui8AuthSrc is a pointer to the memory location where the -//! additional authentication data is stored. The data must be padded to the -//! 16-byte boundary. -//! \param ui32AuthLength is the length of the additional authentication -//! data in bytes. -//! \param pui8Tag is a pointer to a 4-word array where the hash tag is -//! written. -//! -//! This function encrypts or decrypts blocks of data in addition to -//! authentication data. A hash tag is also produced. Before calling this -//! function, ensure that the AES module is properly configured the key, -//! data size, mode, etc. Only CCM and GCM modes should be used. -//! -//! \return Returns true if data was processed successfully. Returns false -//! if data processing failed. -// -//***************************************************************************** -bool -AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest, - uint32_t ui32Length, uint8_t *pui8AuthSrc, - uint32_t ui32AuthLength, uint8_t *pui8Tag) -{ - uint32_t ui32Count; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Set the data length. - // - AESDataLengthSet(AES_BASE, (uint64_t) ui32Length); - - // - // Set the additional authentication data length. - // - AESAuthDataLengthSet(AES_BASE, ui32AuthLength); - - // - // Now loop until the authentication data blocks are written. - // - for(ui32Count = 0; ui32Count < ui32AuthLength; ui32Count += 16) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui8AuthSrc + (ui32Count),16); - } - - // - // Now loop until the data blocks are written. - // - for(ui32Count = 0; ui32Count < ui32Length; ui32Count += 16) - { - // - // Write the data registers. - // - AESDataWrite(ui32Base, pui8Src + (ui32Count),16); - - // - // - // Read the data registers. - // - AESDataRead(ui32Base, pui8Dest + (ui32Count),16); - } - - // - // Wait for the context data regsiters to be ready. - // - while((AES_CTRL_SVCTXTRDY & (HWREG(AES_BASE + AES_O_CTRL))) == 0) - { - } - - // - // Read the hash tag value. - // - AESTagRead(AES_BASE, pui8Tag); - - // - // Return true to indicate successful completion of the function. - // - return(true); -} - -//***************************************************************************** -// -//! Returns the current AES module interrupt status. -//! -//! \param ui32Base is the base address of the AES module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! \return Returns a bit mask of the interrupt sources, which is a logical OR -//! of any of the following: -//! -//! - \b AES_INT_CONTEXT_IN - Context interrupt -//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt. -//! - \b AES_INT_DATA_IN - Data input interrupt -//! - \b AES_INT_DATA_OUT - Data output interrupt -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -// -//***************************************************************************** -uint32_t -AESIntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Temp; - uint32_t ui32IrqEnable; - - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Read the IRQ status register and return the value. - // - if(bMasked) - { - ui32Temp = HWREG(DTHE_BASE + DTHE_O_AES_MIS); - ui32IrqEnable = HWREG(ui32Base + AES_O_IRQENABLE); - return((HWREG(ui32Base + AES_O_IRQSTATUS) & - ui32IrqEnable) | ((ui32Temp & 0x0000000F) << 16)); - } - else - { - ui32Temp = HWREG(DTHE_BASE + DTHE_O_AES_RIS); - return(HWREG(ui32Base + AES_O_IRQSTATUS) | - ((ui32Temp & 0x0000000F) << 16)); - } -} - -//***************************************************************************** -// -//! Enables AES module interrupts. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to enable. -//! -//! This function enables the interrupts in the AES module. The \e ui32IntFlags -//! parameter is the logical OR of any of the following: -//! -//! - \b AES_INT_CONTEXT_IN - Context interrupt -//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt -//! - \b AES_INT_DATA_IN - Data input interrupt -//! - \b AES_INT_DATA_OUT - Data output interrupt -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \note Interrupts that have been previously been enabled are not disabled -//! when this function is called. -//! -//! \return None. -// -//***************************************************************************** -void -AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) || - (ui32IntFlags == AES_INT_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DATA_IN) || - (ui32IntFlags == AES_INT_DATA_OUT) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DMA_DATA_IN) || - (ui32IntFlags == AES_INT_DMA_DATA_OUT)); - - // - // Set the flags. - // - HWREG(DTHE_BASE + DTHE_O_AES_IM) &= ~((ui32IntFlags & 0x000F0000) >> 16); - HWREG(ui32Base + AES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; -} - -//***************************************************************************** -// -//! Disables AES module interrupts. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to disable. -//! -//! This function disables the interrupt sources in the AES module. The -//! \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b AES_INT_CONTEXT_IN - Context interrupt -//! - \b AES_INT_CONTEXT_OUT - Authentication tag (and IV) interrupt -//! - \b AES_INT_DATA_IN - Data input interrupt -//! - \b AES_INT_DATA_OUT - Data output interrupt -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \note The DMA done interrupts are the only interrupts that can be cleared. -//! The remaining interrupts can be disabled instead using AESIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32IntFlags == AES_INT_CONTEXT_IN) || - (ui32IntFlags == AES_INT_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DATA_IN) || - (ui32IntFlags == AES_INT_DATA_OUT) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DMA_DATA_IN) || - (ui32IntFlags == AES_INT_DMA_DATA_OUT)); - - // - // Clear the flags. - // - HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x000F0000) >> 16); - HWREG(ui32Base + AES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); -} - -//***************************************************************************** -// -//! Clears AES module interrupts. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to disable. -//! -//! This function clears the interrupt sources in the AES module. The -//! \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b AES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b AES_INT_DMA_CONTEXT_OUT - Authentication tag (and IV) DMA done -//! interrupt -//! - \b AES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b AES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \note Only the DMA done interrupts can be cleared. The remaining -//! interrupts should be disabled with AESIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32IntFlags == AES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags == AES_INT_DMA_CONTEXT_OUT) || - (ui32IntFlags == AES_INT_DMA_DATA_IN) || - (ui32IntFlags == AES_INT_DMA_DATA_OUT)); - - HWREG(DTHE_BASE + DTHE_O_AES_IC) = ((ui32IntFlags >> 16) & 0x0000000F); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled AES interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables AES interrupts on the interrupt controller; specific AES -//! interrupt sources must be enabled using AESIntEnable(). The interrupt -//! handler being registered must clear the source of the interrupt using -//! AESIntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() is used to enable AES interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_AES, pfnHandler); - - // - // Enable the interrupt - // - IntEnable(INT_AES); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -AESIntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_AES); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_AES); -} - -//***************************************************************************** -// -//! Enables uDMA requests for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Flags is a bit mask of the uDMA requests to be enabled. -//! -//! This function enables the uDMA request sources in the AES module. -//! The \e ui32Flags parameter is the logical OR of any of the following: -//! -//! - \b AES_DMA_DATA_IN -//! - \b AES_DMA_DATA_OUT -//! - \b AES_DMA_CONTEXT_IN -//! - \b AES_DMA_CONTEXT_OUT -//! -//! \return None. -// -//***************************************************************************** -void -AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Flags == AES_DMA_DATA_IN) || - (ui32Flags == AES_DMA_DATA_OUT) || - (ui32Flags == AES_DMA_CONTEXT_IN) || - (ui32Flags == AES_DMA_CONTEXT_OUT)); - - // - // Set the flags in the current register value. - // - HWREG(ui32Base + AES_O_SYSCONFIG) |= ui32Flags; -} - -//***************************************************************************** -// -//! Disables uDMA requests for the AES module. -//! -//! \param ui32Base is the base address of the AES module. -//! \param ui32Flags is a bit mask of the uDMA requests to be disabled. -//! -//! This function disables the uDMA request sources in the AES module. -//! The \e ui32Flags parameter is the logical OR of any of the -//! following: -//! -//! - \b AES_DMA_DATA_IN -//! - \b AES_DMA_DATA_OUT -//! - \b AES_DMA_CONTEXT_IN -//! - \b AES_DMA_CONTEXT_OUT -//! -//! \return None. -// -//***************************************************************************** -void -AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == AES_BASE); - ASSERT((ui32Flags == AES_DMA_DATA_IN) || - (ui32Flags == AES_DMA_DATA_OUT) || - (ui32Flags == AES_DMA_CONTEXT_IN) || - (ui32Flags == AES_DMA_CONTEXT_OUT)); - - // - // Clear the flags in the current register value. - // - HWREG(ui32Base + AES_O_SYSCONFIG) &= ~ui32Flags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/aes.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/aes.h deleted file mode 100644 index de5d2c68b8f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/aes.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// aes.h -// -// Defines and Macros for the AES module. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_AES_H__ -#define __DRIVERLIB_AES_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used to specify the operation direction in the -// ui32Config argument in the AESConfig function. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_DIR_ENCRYPT 0x00000004 -#define AES_CFG_DIR_DECRYPT 0x00000000 - -//***************************************************************************** -// -// The following defines are used to specify the key size in the ui32Config -// argument in the AESConfig function. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_KEY_SIZE_128BIT 0x00000008 -#define AES_CFG_KEY_SIZE_192BIT 0x00000010 -#define AES_CFG_KEY_SIZE_256BIT 0x00000018 - -//***************************************************************************** -// -// The following defines are used to specify the mode of operation in the -// ui32Config argument in the AESConfig function. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_MODE_M 0x2007fe60 -#define AES_CFG_MODE_ECB 0x00000000 -#define AES_CFG_MODE_CBC 0x00000020 -#define AES_CFG_MODE_CTR 0x00000040 -#define AES_CFG_MODE_ICM 0x00000200 -#define AES_CFG_MODE_CFB 0x00000400 -#define AES_CFG_MODE_XTS_TWEAKJL \ - 0x00000800 -#define AES_CFG_MODE_XTS_K2IJL \ - 0x00001000 -#define AES_CFG_MODE_XTS_K2ILJ0 \ - 0x00001800 -#define AES_CFG_MODE_F8 0x00002000 -#define AES_CFG_MODE_F9 0x20004000 -#define AES_CFG_MODE_CBCMAC 0x20008000 -#define AES_CFG_MODE_GCM_HLY0ZERO \ - 0x20010040 -#define AES_CFG_MODE_GCM_HLY0CALC \ - 0x20020040 -#define AES_CFG_MODE_GCM_HY0CALC \ - 0x20030040 -#define AES_CFG_MODE_CCM 0x20040040 - -//***************************************************************************** -// -// The following defines are used to specify the counter width in the -// ui32Config argument in the AESConfig function. It is only required to -// be defined when using CTR, CCM, or GCM modes. Only one length is permitted. -// -//***************************************************************************** -#define AES_CFG_CTR_WIDTH_32 0x00000000 -#define AES_CFG_CTR_WIDTH_64 0x00000080 -#define AES_CFG_CTR_WIDTH_96 0x00000100 -#define AES_CFG_CTR_WIDTH_128 0x00000180 - -//***************************************************************************** -// -// The following defines are used to define the width of the length field for -// CCM operation through the ui32Config argument in the AESConfig function. -// This value is also known as L. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_CCM_L_2 0x00080000 -#define AES_CFG_CCM_L_4 0x00180000 -#define AES_CFG_CCM_L_8 0x00380000 - -//***************************************************************************** -// -// The following defines are used to define the length of the authentication -// field for CCM operations through the ui32Config argument in the AESConfig -// function. This value is also known as M. Only one is permitted. -// -//***************************************************************************** -#define AES_CFG_CCM_M_4 0x00400000 -#define AES_CFG_CCM_M_6 0x00800000 -#define AES_CFG_CCM_M_8 0x00c00000 -#define AES_CFG_CCM_M_10 0x01000000 -#define AES_CFG_CCM_M_12 0x01400000 -#define AES_CFG_CCM_M_14 0x01800000 -#define AES_CFG_CCM_M_16 0x01c00000 - -//***************************************************************************** -// -// Interrupt flags for use with the AESIntEnable, AESIntDisable, and -// AESIntStatus functions. -// -//***************************************************************************** -#define AES_INT_CONTEXT_IN 0x00000001 -#define AES_INT_CONTEXT_OUT 0x00000008 -#define AES_INT_DATA_IN 0x00000002 -#define AES_INT_DATA_OUT 0x00000004 -#define AES_INT_DMA_CONTEXT_IN 0x00010000 -#define AES_INT_DMA_CONTEXT_OUT 0x00020000 -#define AES_INT_DMA_DATA_IN 0x00040000 -#define AES_INT_DMA_DATA_OUT 0x00080000 - -//***************************************************************************** -// -// Defines used when enabling and disabling DMA requests in the -// AESEnableDMA and AESDisableDMA functions. -// -//***************************************************************************** -#define AES_DMA_DATA_IN 0x00000040 -#define AES_DMA_DATA_OUT 0x00000020 -#define AES_DMA_CONTEXT_IN 0x00000080 -#define AES_DMA_CONTEXT_OUT 0x00000100 - -//***************************************************************************** -// -// Function prototypes. -// -//***************************************************************************** -extern void AESConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void AESKey1Set(uint32_t ui32Base, uint8_t *pui8Key, - uint32_t ui32Keysize); -extern void AESKey2Set(uint32_t ui32Base, uint8_t *pui8Key, - uint32_t ui32Keysize); -extern void AESKey3Set(uint32_t ui32Base, uint8_t *pui8Key); -extern void AESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata); -extern void AESIVGet(uint32_t ui32Base, uint8_t *pui8IVdata); -extern void AESTagRead(uint32_t ui32Base, uint8_t *pui8TagData); -extern void AESDataLengthSet(uint32_t ui32Base, uint64_t ui64Length); -extern void AESAuthDataLengthSet(uint32_t ui32Base, uint32_t ui32Length); -extern bool AESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, - uint8_t ui8Length); -extern void AESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, - uint8_t ui8Length); -extern bool AESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t ui8Length); -extern void AESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t ui8Length); -extern bool AESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t *pui8Dest, - uint32_t ui32Length); -extern bool AESDataMAC(uint32_t ui32Base, uint8_t *pui8Src, - uint32_t ui32Length, - uint8_t *pui8Tag); -extern bool AESDataProcessAE(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t *pui8Dest, uint32_t ui32Length, - uint8_t *pui8AuthSrc, uint32_t ui32AuthLength, - uint8_t *pui8Tag); -extern uint32_t AESIntStatus(uint32_t ui32Base, bool bMasked); -extern void AESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void AESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void AESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void AESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); -extern void AESIntUnregister(uint32_t ui32Base); -extern void AESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); -extern void AESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_AES_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/camera.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/camera.c deleted file mode 100644 index 4033f1501c6..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/camera.c +++ /dev/null @@ -1,603 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// camera.c -// -// Driver for the camera controller module -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup camera_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_types.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_camera.h" -#include "inc/hw_apps_config.h" -#include "interrupt.h" -#include "camera.h" - -//****************************************************************************** -// -//! Resets the Camera core -//! -//! \param ulBase is the base address of the camera module. -//! -//! This function resets the camera core -//! -//! \return None. -// -//****************************************************************************** -void CameraReset(unsigned long ulBase) -{ - // - // Reset the camera - // - HWREG(ulBase + CAMERA_O_CC_SYSCONFIG) = CAMERA_CC_SYSCONFIG_SOFT_RESET; - - // - // Wait for reset completion - // - while(!(HWREG(ulBase + CAMERA_O_CC_SYSSTATUS)& - CAMERA_CC_SYSSTATUS_RESET_DONE2)) - { - - } - -} - -//****************************************************************************** -// -//! Configures camera parameters -//! -//! \param ulBase is the base address of the camera module. -//! \param ulHSPol sets the HSync polarity -//! \param ulVSPol sets the VSync polarity -//! \param ulFlags are configuration flags -//! -//! This function sets different camera parameters. -//! -//! The parameter \e ulHSPol should be on the follwoing: -//! - \b CAM_HS_POL_HI -//! - \b CAM_HS_POL_LO -//! -//! The parameter \e ulVSPol should be on the follwoing: -//! - \b CAM_VS_POL_HI -//! - \b CAM_VS_POL_LO -//! -//! The parameter \e ulFlags can be logical OR of one or more of the follwoing -//! or 0: -//! - \b CAM_PCLK_RISE_EDGE -//! - \b CAM_PCLK_FALL_EDGE -//! - \b CAM_ORDERCAM_SWAP -//! - \b CAM_NOBT_SYNCHRO -//! - \b CAM_IF_SYNCHRO -//! -//! \return None. -// -//****************************************************************************** -void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol, - unsigned long ulVSPol, unsigned long ulFlags) -{ - unsigned long ulReg; - - // - // Read the register - // - ulReg = HWREG(ulBase + CAMERA_O_CC_CTRL); - - // - // Set the requested parameter - // - ulFlags = (ulFlags|ulHSPol|ulVSPol); - ulReg = ((ulReg & ~(CAMERA_CC_CTRL_NOBT_SYNCHRO | - CAMERA_CC_CTRL_NOBT_HS_POL | - CAMERA_CC_CTRL_NOBT_VS_POL | - CAMERA_CC_CTRL_BT_CORRECT | - CAMERA_CC_CTRL_PAR_ORDERCAM | - CAMERA_CC_CTRL_PAR_CLK_POL )) | ulFlags); - - // - // Write the configuration - // - HWREG(ulBase + CAMERA_O_CC_CTRL)=ulReg; -} - - -//****************************************************************************** -// -//! Set the internal clock divider -//! -//! \param ulBase is the base address of the camera module. -//! \param ulCamClkIn is input to camera module -//! \param ulXClk defines the output required -//! -//! This function sets the internal clock divider based on \e ulCamClkIn to -//! generate XCLK as specified be \e ulXClk. Maximum suppoter division is 30 -//! -//! \return None. -// -//****************************************************************************** -void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn, - unsigned long ulXClk) -{ - unsigned long ulReg; - unsigned long ucDiv; - - // - // Read the register - // - ulReg = HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK); - - // - // Mask XCLK divider value - // - ulReg &= ~(CAMERA_CC_CTRL_XCLK_XCLK_DIV_M); - - // - // Compute the divider - // - ucDiv = ((ulCamClkIn)/ulXClk); - - // - // Max supported division is 30 - // - if(ucDiv > 30) - { - return; - } - - // - // Set and write back the configuration - // - ulReg |= ucDiv; - HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) = ulReg; -} - - -//****************************************************************************** -// -//! Sets the internal divide in specified mode -//! -//! \param ulBase is the base address of the camera module. -//! \param bXClkFlags decides the divide mode -//! -//! This function sets the internal divide in specified mode. -//! -//! The parameter \e bXClkFlags should be one of the following : -//! -//! - \b CAM_XCLK_STABLE_LO -//! - \b CAM_XCLK_STABLE_HI -//! - \b CAM_XCLK_DIV_BYPASS -//! -//! \return None. -// -//****************************************************************************** -void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags) -{ - unsigned long ulReg; - - // - // Read and Mask XTAL Divider config. - // - ulReg = (HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) & - ~(CAMERA_CC_CTRL_XCLK_XCLK_DIV_M)); - - // - // Set config. base on parameter flag - // - switch(bXClkFlags) - { - - case CAM_XCLK_STABLE_HI : ulReg |= 0x00000001; - break; - - case CAM_XCLK_DIV_BYPASS: ulReg |= 0x0000001F; - break; - } - - // - // Write the config. - // - HWREG(ulBase + CAMERA_O_CC_CTRL_XCLK) = ulReg; -} - - -//****************************************************************************** -// -//! Enable camera DMA -//! -//! \param ulBase is the base address of the camera module. -//! -//! This function enables transfer request to DMA from camera. DMA specific -//! configuration has to be done seperately. -//! -//! \return None. -// -//****************************************************************************** -void CameraDMAEnable(unsigned long ulBase) -{ - // - // Enable DMA - // - HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) |= CAMERA_CC_CTRL_DMA_DMA_EN; -} - - -//****************************************************************************** -// -//! Disable camera DMA -//! -//! \param ulBase is the base address of the camera module. -//! -//! This function masks transfer request to DMA from camera. -//! -//! \return None. -// -//****************************************************************************** -void CameraDMADisable(unsigned long ulBase) -{ - // - // Disable DMA - // - HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) &= ~CAMERA_CC_CTRL_DMA_DMA_EN; -} - - - -//****************************************************************************** -// -//! Sets the FIFO threshold for DMA transfer request -//! -//! \param ulBase is the base address of the camera module. -//! \param ulThreshold specifies the FIFO threshold -//! -//! This function sets the FIFO threshold for DMA transfer request. -//! Parameter \e ulThreshold can range from 1 - 64 -//! -//! \return None. -// -//****************************************************************************** -void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold) -{ - // - // Read and Mask DMA threshold field - // - HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) &= ~CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M; - // - // Write the new threshold value - // - HWREG(ulBase + CAMERA_O_CC_CTRL_DMA) |= (ulThreshold -1); -} - - -//****************************************************************************** -// -//! Register camera interrupt handler -//! -//! \param ulBase is the base address of the camera module. -//! \param pfnHandler hold pointer to interrupt handler -//! -//! This function registers and enables global camera interrupt from the -//! interrupt controller. Individual camera interrupts source -//! should be enabled using \sa CameraIntEnable(). -//! -//! \return None. -// -//****************************************************************************** -void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler. - // - IntRegister(INT_CAMERA, pfnHandler); - - // - // Enable the Camera interrupt. - // - IntEnable(INT_CAMERA); -} - - -//****************************************************************************** -// -//! Un-Register camera interrupt handler -//! -//! \param ulBase is the base address of the camera module. -//! -//! This function unregisters and disables global camera interrupt from the -//! interrupt controller. -//! -//! \return None. -// -//****************************************************************************** -void CameraIntUnregister(unsigned long ulBase) -{ - // - // Disable the interrupt. - // - IntDisable(INT_CAMERA); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_CAMERA); -} - - -//****************************************************************************** -//! Enables individual camera interrupt sources. -//! -//! \param ulBase is the base address of the camera module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables individual camera interrupt sources. -//! -//! the parameter \e ulIntFlags should be logical OR of one or more of the -//! following: -//! -//! - \b CAM_INT_DMA -//! - \b CAM_INT_FE -//! - \b CAM_INT_FSC_ERR -//! - \b CAM_INT_FIFO_NOEMPTY -//! - \b CAM_INT_FIFO_FULL -//! - \b CAM_INT_FIFO_THR -//! - \b CAM_INT_FIFO_OF -//! - \b CAN_INT_FIFO_UR -//! -//! \return None. -// -//****************************************************************************** -void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // unmask Camera DMA done interrupt - // - if(ulIntFlags & CAM_INT_DMA) - { - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ((1<<8)); - } - - // - // Enable specific camera interrupts - // - HWREG(ulBase + CAMERA_O_CC_IRQENABLE) |= ulIntFlags; -} - - -//****************************************************************************** -//! Disables individual camera interrupt sources. -//! -//! \param ulBase is the base address of the camera module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! This function disables individual camera interrupt sources. -//! -//! The parameter \e ulIntFlags should be logical OR of one or more of the -//! values as defined in CameraIntEnable(). -//! -//! \return None. -// -//****************************************************************************** -void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Mask Camera DMA done interrupt - // - if(ulIntFlags & CAM_INT_DMA) - { - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ((1<<8)); - } - - // - // Disable specific camera interrupts - // - HWREG(ulBase + CAMERA_O_CC_IRQENABLE) &= ~ulIntFlags; -} - -//****************************************************************************** -// -//! Returns the current interrupt status, -//! -//! \param ulBase is the base address of the camera module. -//! \param ulBase is the base address of the camera module. -//! -//! This functions returns the current interrupt status for the camera. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in CameraIntEnable(). -//****************************************************************************** -unsigned long CameraIntStatus(unsigned long ulBase) -{ - unsigned ulIntFlag; - - // - // Read camera interrupt - // - ulIntFlag = HWREG(ulBase + CAMERA_O_CC_IRQSTATUS); - - // - // - // Read camera DMA doner interrupt - // - if(HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED) & (1<<8)) - { - ulIntFlag |= CAM_INT_DMA; - } - - // - // Return status - // - return(ulIntFlag); -} - - -//****************************************************************************** -//! Clears individual camera interrupt sources. -//! -//! \param ulBase is the base address of the camera module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be Clears. -//! -//! This function Clears individual camera interrupt sources. -//! -//! The parameter \e ulIntFlags should be logical OR of one or more of the -//! values as defined in CameraIntEnable(). -//! -//! \return None. -// -//****************************************************************************** -void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Clear DMA done int status - // - if(ulIntFlags & CAM_INT_DMA) - { - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ((1<<8)); - } - - // - // Clear the interrupts - // - HWREG(ulBase + CAMERA_O_CC_IRQSTATUS) = ulIntFlags; -} - -//****************************************************************************** -// -//! Starts image capture -//! -//! \param ulBase is the base address of the camera module. -//! -//! This function starts the image capture over the configured camera interface -//! This function should be called after configuring the camera module -//! completele -//! -//! \return None. -// -//****************************************************************************** -void CameraCaptureStart(unsigned long ulBase) -{ - // - // Set the mode - // - HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~0xF; - - // - // Enable image capture - // - HWREG(ulBase + CAMERA_O_CC_CTRL) |= CAMERA_CC_CTRL_CC_EN; -} - -//****************************************************************************** -// -//! Stops image capture -//! -//! \param ulBase is the base address of the camera module. -//! \param bImmediate is \b true to stop capture imeediately else \b flase. -//! -//! This function stops the image capture over the camera interface. -//! The capture is stopped either immediatelt or at the end of current frame -//! based on \e bImmediate parameter. -//! -//! \return None. -// -//****************************************************************************** -void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate) -{ - if(bImmediate) - { - // - // Stop capture immediately - // - HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~CAMERA_CC_CTRL_CC_FRAME_TRIG; - } - else - { - // - // Stop capture at the end of frame - // - HWREG(ulBase + CAMERA_O_CC_CTRL) |= CAMERA_CC_CTRL_CC_FRAME_TRIG; - } - - // - // Request camera to stop capture - // - HWREG(ulBase + CAMERA_O_CC_CTRL) &= ~CAMERA_CC_CTRL_CC_EN; -} - - -//****************************************************************************** -// -//! Reads the camera buffer (FIFO) -//! -//! \param ulBase is the base address of the camera module. -//! \param pBuffer is the pointer to the read buffer -//! \param ucSize specifies the size to data to be read -//! -//! This function reads the camera buffer (FIFO). -//! -//! \return None. -// -//****************************************************************************** -void CameraBufferRead(unsigned long ulBase, unsigned long *pBuffer, - unsigned char ucSize) -{ - unsigned char *pCamBuff; - unsigned char i; - - // - // Initilize a pointer to ecamera buffer - // - pCamBuff = (unsigned char *)CAM_BUFFER_ADDR; - - // - // Read out requested data - // - for(i=0; i < ucSize; i++) - { - *(pBuffer+i) = *(pCamBuff + i); - } -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/camera.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/camera.h deleted file mode 100644 index a3c08f91bae..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/camera.h +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// camera.h -// -// Prototypes and macros for the camera controller module. -// -//***************************************************************************** - -#ifndef __CAMERA_H__ -#define __CAMERA_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// Macro defining Camera buffer address -//***************************************************************************** -#define CAM_BUFFER_ADDR 0x44018100 - - -//***************************************************************************** -// Value that can be passed to CameraXClkSet(). -//***************************************************************************** -#define CAM_XCLK_STABLE_LO 0x00 -#define CAM_XCLK_STABLE_HI 0x01 -#define CAM_XCLK_DIV_BYPASS 0x02 - - -//***************************************************************************** -// Value that can be passed to CameraIntEnable(), CameraIntDisable, -// CameraIntClear() or returned from CameraIntStatus(). -//***************************************************************************** -#define CAM_INT_DMA 0x80000000 -#define CAM_INT_FE 0x00010000 -#define CAM_INT_FIFO_NOEMPTY 0x00000010 -#define CAM_INT_FIFO_FULL 0x00000008 -#define CAM_INT_FIFO_THR 0x00000004 -#define CAM_INT_FIFO_OF 0x00000002 -#define CAN_INT_FIFO_UR 0x00000001 - - -//***************************************************************************** -// Value that can be passed to CameraXClkConfig(). -//***************************************************************************** -#define CAM_HS_POL_HI 0x00000000 -#define CAM_HS_POL_LO 0x00000200 -#define CAM_VS_POL_HI 0x00000000 -#define CAM_VS_POL_LO 0x00000100 - -#define CAM_PCLK_RISE_EDGE 0x00000000 -#define CAM_PCLK_FALL_EDGE 0x00000400 - -#define CAM_ORDERCAM_SWAP 0x00000800 -#define CAM_NOBT_SYNCHRO 0x00002000 -#define CAM_IF_SYNCHRO 0x00080000 - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void CameraReset(unsigned long ulBase); -extern void CameraParamsConfig(unsigned long ulBase, unsigned long ulHSPol, - unsigned long ulVSPol, unsigned long ulFlags); -extern void CameraXClkConfig(unsigned long ulBase, unsigned long ulCamClkIn, - unsigned long ulXClk); -extern void CameraXClkSet(unsigned long ulBase, unsigned char bXClkFlags); -extern void CameraDMAEnable(unsigned long ulBase); -extern void CameraDMADisable(unsigned long ulBase); -extern void CameraThresholdSet(unsigned long ulBase, unsigned long ulThreshold); -extern void CameraIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void CameraIntUnregister(unsigned long ulBase); -extern void CameraIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void CameraIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long CameraIntStatus(unsigned long ulBase); -extern void CameraIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void CameraCaptureStop(unsigned long ulBase, tBoolean bImmediate); -extern void CameraCaptureStart(unsigned long ulBase); -extern void CameraBufferRead(unsigned long ulBase,unsigned long *pBuffer, - unsigned char ucSize); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif //__CAMERA_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/cpu.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/cpu.c deleted file mode 100644 index 3a5f3a96651..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/cpu.c +++ /dev/null @@ -1,413 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// cpu.c -// -// Instruction wrappers for special CPU instructions needed by the -// -// -//***************************************************************************** -#include "cpu.h" - -//***************************************************************************** -// -// Wrapper function for the CPSID instruction. Returns the state of PRIMASK -// on entry. -// -//***************************************************************************** -#if defined(gcc) -unsigned long __attribute__((naked)) -CPUcpsid(void) -{ - unsigned long ulRet; - - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " dsb \n" - " isb \n" - " bx lr\n" - : "=r" (ulRet)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ulRet); -} -#endif -#if defined(ewarm) -unsigned long -CPUcpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " dsb \n" - " isb \n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(ccs) -unsigned long -CPUcpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " dsb \n" - " isb \n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function returning the state of PRIMASK (indicating whether -// interrupts are enabled or disabled). -// -//***************************************************************************** -#if defined(gcc) -unsigned long __attribute__((naked)) -CPUprimask(void) -{ - unsigned long ulRet; - - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " bx lr\n" - : "=r" (ulRet)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ulRet); -} -#endif -#if defined(ewarm) -unsigned long -CPUprimask(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(ccs) -unsigned long -CPUprimask(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK -// on entry. -// -//***************************************************************************** -#if defined(gcc) -unsigned long __attribute__((naked)) -CPUcpsie(void) -{ - unsigned long ulRet; - - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " dsb \n" - " isb \n" - " bx lr\n" - : "=r" (ulRet)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ulRet); -} -#endif -#if defined(ewarm) -unsigned long -CPUcpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " dsb \n" - " isb \n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(ccs) -unsigned long -CPUcpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " dsb \n" - " isb \n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function for the WFI instruction. -// -//***************************************************************************** -#if defined(gcc) -void __attribute__((naked)) -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" dsb \n" - " isb \n" - " wfi \n" - " bx lr\n"); -} -#endif -#if defined(ewarm) -void -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" dsb \n" - " isb \n" - " wfi \n"); -} -#endif -#if defined(ccs) -void -CPUwfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" dsb \n" - " isb \n" - " wfi \n"); -} -#endif - -//***************************************************************************** -// -// Wrapper function for writing the BASEPRI register. -// -//***************************************************************************** -#if defined(gcc) -void __attribute__((naked)) -CPUbasepriSet(unsigned long ulNewBasepri) -{ - - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n" - " dsb \n" - " isb \n" - " bx lr\n"); -} -#endif -#if defined(ewarm) -void -CPUbasepriSet(unsigned long ulNewBasepri) -{ - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n" - " dsb \n" - " isb \n"); -} -#endif -#if defined(ccs) -void -CPUbasepriSet(unsigned long ulNewBasepri) -{ - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n" - " dsb \n" - " isb \n"); -} -#endif - -//***************************************************************************** -// -// Wrapper function for reading the BASEPRI register. -// -//***************************************************************************** -#if defined(gcc) -unsigned long __attribute__((naked)) -CPUbasepriGet(void) -{ - unsigned long ulRet; - - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n" - " bx lr\n" - : "=r" (ulRet)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ulRet); -} -#endif -#if defined(ewarm) -unsigned long -CPUbasepriGet(void) -{ - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(ccs) -unsigned long -CPUbasepriGet(void) -{ - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/cpu.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/cpu.h deleted file mode 100644 index d676276408d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/cpu.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// cpu.h -// -// Prototypes for the CPU instruction wrapper functions. -// -//***************************************************************************** - -#ifndef __CPU_H__ -#define __CPU_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern unsigned long CPUcpsid(void); -extern unsigned long CPUcpsie(void); -extern unsigned long CPUprimask(void); -extern void CPUwfi(void); -extern unsigned long CPUbasepriGet(void); -extern void CPUbasepriSet(unsigned long ulNewBasepri); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __CPU_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/crc.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/crc.c deleted file mode 100644 index 46f31aae3c9..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/crc.c +++ /dev/null @@ -1,306 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// crc.c -// -// Driver for the CRC module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup CRC_Cyclic_Redundancy_Check_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_dthe.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "driverlib/crc.h" -#include "driverlib/debug.h" - -//***************************************************************************** -// -//! Set the configuration of CRC functionality with the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param ui32CRCConfig is the configuration of the CRC engine. -//! -//! This function configures the operation of the CRC engine within the EC -//! module. The configuration is specified with the \e ui32CRCConfig argument. -//! It is the logical OR of any of the following options: -//! -//! CRC Initialization Value -//! - \b EC_CRC_CFG_INIT_SEED - Initialize with seed value -//! - \b EC_CRC_CFG_INIT_0 - Initialize to all '0s' -//! - \b EC_CRC_CFG_INIT_1 - Initialize to all '1s' -//! -//! Input Data Size -//! - \b EC_CRC_CFG_SIZE_8BIT - Input data size of 8 bits -//! - \b EC_CRC_CFG_SIZE_32BIT - Input data size of 32 bits -//! -//! Post Process Reverse/Inverse -//! - \b EC_CRC_CFG_RESINV - Result inverse enable -//! - \b EC_CRC_CFG_OBR - Output reverse enable -//! -//! Input Bit Reverse -//! - \b EC_CRC_CFG_IBR - Bit reverse enable -//! -//! Endian Control -//! - \b EC_CRC_CFG_ENDIAN_SBHW - Swap byte in half-word -//! - \b EC_CRC_CFG_ENDIAN_SHW - Swap half-word -//! -//! Operation Type -//! - \b EC_CRC_CFG_TYPE_P8005 - Polynomial 0x8005 -//! - \b EC_CRC_CFG_TYPE_P1021 - Polynomial 0x1021 -//! - \b EC_CRC_CFG_TYPE_P4C11DB7 - Polynomial 0x4C11DB7 -//! - \b EC_CRC_CFG_TYPE_P1EDC6F41 - Polynomial 0x1EDC6F41 -//! - \b EC_CRC_CFG_TYPE_TCPCHKSUM - TCP checksum -//! -//! \return None. -// -//***************************************************************************** -void -CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DTHE_BASE); - ASSERT((ui32CRCConfig & CRC_CFG_INIT_SEED) || - (ui32CRCConfig & CRC_CFG_INIT_0) || - (ui32CRCConfig & CRC_CFG_INIT_1) || - (ui32CRCConfig & CRC_CFG_SIZE_8BIT) || - (ui32CRCConfig & CRC_CFG_SIZE_32BIT) || - (ui32CRCConfig & CRC_CFG_RESINV) || - (ui32CRCConfig & CRC_CFG_OBR) || - (ui32CRCConfig & CRC_CFG_IBR) || - (ui32CRCConfig & CRC_CFG_ENDIAN_SBHW) || - (ui32CRCConfig & CRC_CFG_ENDIAN_SHW) || - (ui32CRCConfig & CRC_CFG_TYPE_P8005) || - (ui32CRCConfig & CRC_CFG_TYPE_P1021) || - (ui32CRCConfig & CRC_CFG_TYPE_P4C11DB7) || - (ui32CRCConfig & CRC_CFG_TYPE_P1EDC6F41) || - (ui32CRCConfig & CRC_CFG_TYPE_TCPCHKSUM)); - - // - // Write the control register with the configuration. - // - HWREG(ui32Base + DTHE_O_CRC_CTRL) = ui32CRCConfig; -} - -//***************************************************************************** -// -//! Write the seed value for CRC operations in the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param ui32Seed is the seed value. -//! -//! This function writes the seed value for use with CRC operations in the -//! EC module. This value is the start value for CRC operations. If this -//! value is not written, then the residual seed from the previous operation -//! is used as the starting value. -//! -//! \note The seed must be written only if \b EC_CRC_CFG_INIT_SEED is -//! set with the CRCConfigSet() function. -// -//***************************************************************************** -void -CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DTHE_BASE); - - // - // Write the seed value to the seed register. - // - HWREG(ui32Base + DTHE_O_CRC_SEED) = ui32Seed; -} - -//***************************************************************************** -// -//! Write data into the EC module for CRC operations. -//! -//! \param ui32Base is the base address of the EC module. -//! \param ui32Data is the data to be written. -//! -//! This function writes either 8 or 32 bits of data into the EC module for -//! CRC operations. The distinction between 8 and 32 bits of data is made -//! when the \b EC_CRC_CFG_SIZE_8BIT or \b EC_CRC_CFG_SIZE_32BIT flag -//! is set using the CRCConfigSet() function. -//! -//! When writing 8 bits of data, ensure the data is in the least signficant -//! byte position. The remaining bytes should be written with zero. For -//! example, when writing 0xAB, \e ui32Data should be 0x000000AB. -//! -//! \return None -// -//***************************************************************************** -void -CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DTHE_BASE); - - // - // Write the data - // - HWREG(DTHE_BASE + DTHE_O_CRC_DIN) = ui32Data; -} - -//***************************************************************************** -// -//! Reads the result of a CRC operation in the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! -//! This function reads either the unmodified CRC result or the post -//! processed CRC result from the EC module. The post-processing options -//! are selectable through \b EC_CRC_CFG_RESINV and \b EC_CRC_CFG_OBR -//! parameters in the CRCConfigSet() function. -//! -//! \return The CRC result. -// -//***************************************************************************** -uint32_t -CRCResultRead(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DTHE_BASE); - - // - // return value. - // - return(HWREG(DTHE_BASE + DTHE_O_CRC_RSLT_PP)); - -} - -//***************************************************************************** -// -//! Process data to generate a CRC with the EC module. -//! -//! \param ui32Base is the base address of the EC module. -//! \param puiDataIn is a pointer to an array of data that is processed. -//! \param ui32DataLength is the number of data items that are processed -//! to produce the CRC. -//! \param ui32Config the config parameter to determine the CRC mode -//! -//! This function processes an array of data to produce a CRC result. -//! This function takes the CRC mode as the parameter. -//! -//! The data in the array pointed to be \e pui32DataIn is either an array -//! of bytes or an array or words depending on the selection of the input -//! data size options \b EC_CRC_CFG_SIZE_8BIT and -//! \b EC_CRC_CFG_SIZE_32BIT. -//! -//! This function returns either the unmodified CRC result or the -//! post- processed CRC result from the EC module. The post-processing -//! options are selectable through \b EC_CRC_CFG_RESINV and -//! \b EC_CRC_CFG_OBR parameters. -//! -//! \return The CRC result. -// -//***************************************************************************** -uint32_t -CRCDataProcess(uint32_t ui32Base, void *puiDataIn, - uint32_t ui32DataLength, uint32_t ui32Config) -{ - uint8_t *pui8DataIn; - uint32_t *pui32DataIn; - - // - // Check the arguments. - // - ASSERT(ui32Base == DTHE_BASE); - - // - // See if the CRC is operating in 8-bit or 32-bit mode. - // - if(ui32Config & DTHE_CRC_CTRL_SIZE) - { - // - // The CRC is operating in 8-bit mode, so create an 8-bit pointer to - // the data. - // - pui8DataIn = (uint8_t *)puiDataIn; - - // - // Loop through the input data. - // - while(ui32DataLength--) - { - // - // Write the next data byte. - // - HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui8DataIn++; - } - } - else - { - // - // The CRC is operating in 32-bit mode, so loop through the input data. - // - pui32DataIn = (uint32_t *)puiDataIn; - while(ui32DataLength--) - { - // - // Write the next data word. - // - HWREG(ui32Base + DTHE_O_CRC_DIN) = *pui32DataIn++; - } - } - - // - // Return the result. - // - return(CRCResultRead(ui32Base)); -} - - - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/crc.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/crc.h deleted file mode 100644 index 5e8d3f5e74c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/crc.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// crc.h -// -// Defines and Macros for CRC module. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_CRC_H__ -#define __DRIVERLIB_CRC_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used in the ui32Config argument of the -// ECConfig function. -// -//***************************************************************************** -#define CRC_CFG_INIT_SEED 0x00000000 // Initialize with seed -#define CRC_CFG_INIT_0 0x00004000 // Initialize to all '0s' -#define CRC_CFG_INIT_1 0x00006000 // Initialize to all '1s' -#define CRC_CFG_SIZE_8BIT 0x00001000 // Input Data Size -#define CRC_CFG_SIZE_32BIT 0x00000000 // Input Data Size -#define CRC_CFG_RESINV 0x00000200 // Result Inverse Enable -#define CRC_CFG_OBR 0x00000100 // Output Reverse Enable -#define CRC_CFG_IBR 0x00000080 // Bit reverse enable -#define CRC_CFG_ENDIAN_SBHW 0x00000000 // Swap byte in half-word -#define CRC_CFG_ENDIAN_SHW 0x00000010 // Swap half-word -#define CRC_CFG_TYPE_P8005 0x00000000 // Polynomial 0x8005 -#define CRC_CFG_TYPE_P1021 0x00000001 // Polynomial 0x1021 -#define CRC_CFG_TYPE_P4C11DB7 0x00000002 // Polynomial 0x4C11DB7 -#define CRC_CFG_TYPE_P1EDC6F41 0x00000003 // Polynomial 0x1EDC6F41 -#define CRC_CFG_TYPE_TCPCHKSUM 0x00000008 // TCP checksum - -//***************************************************************************** -// -// Function prototypes. -// -//***************************************************************************** -extern void CRCConfigSet(uint32_t ui32Base, uint32_t ui32CRCConfig); -extern uint32_t CRCDataProcess(uint32_t ui32Base, void *puiDataIn, - uint32_t ui32DataLength, uint32_t ui32Config); -extern void CRCDataWrite(uint32_t ui32Base, uint32_t ui32Data); -extern uint32_t CRCResultRead(uint32_t ui32Base); -extern void CRCSeedSet(uint32_t ui32Base, uint32_t ui32Seed); - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_CRC_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/debug.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/debug.h deleted file mode 100644 index cef10a43ab9..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/debug.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// debug.h -// -// Macros for assisting debug of the driver library. -// -//***************************************************************************** -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long ulLine); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - -#else -#define ASSERT(expr) -#endif - -#endif // __DEBUG_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/des.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/des.c deleted file mode 100644 index 0285d0818a1..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/des.c +++ /dev/null @@ -1,888 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// des.c -// -// Driver for the DES data transformation. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup DES_Data_Encryption_Standard_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_des.h" -#include "inc/hw_dthe.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "debug.h" -#include "des.h" -#include "interrupt.h" - - -//***************************************************************************** -// -//! Configures the DES module for operation. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Config is the configuration of the DES module. -//! -//! This function configures the DES module for operation. -//! -//! The \e ui32Config parameter is a bit-wise OR of a number of configuration -//! flags. The valid flags are grouped below based on their function. -//! -//! The direction of the operation is specified with one of the following two -//! flags. Only one is permitted. -//! -//! - \b DES_CFG_DIR_ENCRYPT - Encryption -//! - \b DES_CFG_DIR_DECRYPT - Decryption -//! -//! The operational mode of the DES engine is specified with one of the -//! following flags. Only one is permitted. -//! -//! - \b DES_CFG_MODE_ECB - Electronic Codebook Mode -//! - \b DES_CFG_MODE_CBC - Cipher-Block Chaining Mode -//! - \b DES_CFG_MODE_CFB - Cipher Feedback Mode -//! -//! The selection of single DES or triple DES is specified with one of the -//! following two flags. Only one is permitted. -//! -//! - \b DES_CFG_SINGLE - Single DES -//! - \b DES_CFG_TRIPLE - Triple DES -//! -//! \return None. -// -//***************************************************************************** -void -DESConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Backup the save context field. - // - ui32Config |= (HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT); - - // - // Write the control register. - // - HWREG(ui32Base + DES_O_CTRL) = ui32Config; -} - -//***************************************************************************** -// -//! Sets the key used for DES operations. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8Key is a pointer to an array that holds the key -//! -//! This function sets the key used for DES operations. -//! -//! \e pui8Key should be 64 bits long (2 words) if single DES is being used or -//! 192 bits (6 words) if triple DES is being used. -//! -//! \return None. -// -//***************************************************************************** -void -DESKeySet(uint32_t ui32Base, uint8_t *pui8Key) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Write the first part of the key. - // - HWREG(ui32Base + DES_O_KEY1_L) = * ((uint32_t *)(pui8Key + 0)); - HWREG(ui32Base + DES_O_KEY1_H) = * ((uint32_t *)(pui8Key + 4)); - - // - // If we are performing triple DES, then write the key registers for - // the second and third rounds. - // - if(HWREG(ui32Base + DES_O_CTRL) & DES_CFG_TRIPLE) - { - HWREG(ui32Base + DES_O_KEY2_L) = * ((uint32_t *)(pui8Key + 8)); - HWREG(ui32Base + DES_O_KEY2_H) = * ((uint32_t *)(pui8Key + 12)); - HWREG(ui32Base + DES_O_KEY3_L) = * ((uint32_t *)(pui8Key + 16)); - HWREG(ui32Base + DES_O_KEY3_H) = * ((uint32_t *)(pui8Key + 20)); - } -} - -//***************************************************************************** -// -//! Sets the initialization vector in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8IVdata is a pointer to an array of 64 bits (2 words) of data to -//! be written into the initialization vectors registers. -//! -//! This function sets the initialization vector in the DES module. It returns -//! true if the registers were successfully written. If the context registers -//! cannot be written at the time the function was called, then false is -//! returned. -//! -//! \return True or false. -// -//***************************************************************************** -bool -DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Check to see if context registers can be overwritten. If not, return - // false. - // - if((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_CONTEXT) == 0) - { - return(false); - } - - // - // Write the initialization vector registers. - // - HWREG(ui32Base + DES_O_IV_L) = *((uint32_t *) (pui8IVdata + 0)); - HWREG(ui32Base + DES_O_IV_H) = *((uint32_t *) (pui8IVdata + 4)); - - // - // Return true to indicate the write was successful. - // - return(true); -} - -//***************************************************************************** -// -//! Sets the crytographic data length in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Length is the length of the data in bytes. -//! -//! This function writes the cryptographic data length into the DES module. -//! When this register is written, the engine is triggersed to start using -//! this context. -//! -//! \note Data lengths up to (2^32 - 1) bytes are allowed. -//! -//! \return None. -// -//***************************************************************************** -void -DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Write the length register. - // - HWREG(ui32Base + DES_O_LENGTH) = ui32Length; -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers without blocking -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8Dest is a pointer to an array of 2 words. -//! \param ui8Length the length can be from 1 to 8 -//! -//! This function returns true if the data was ready when the function was -//! called. If the data was not ready, false is returned. -//! -//! \return True or false. -// -//***************************************************************************** -bool -DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length) -{ - volatile uint32_t pui32Dest[2]; - uint8_t ui8BytCnt; - uint8_t *pui8DestTemp; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - if((ui8Length == 0)||(ui8Length>8)) - { - return(false); - } - - // - // Check to see if the data is ready to be read. - // - if((DES_CTRL_OUTPUT_READY & (HWREG(ui32Base + DES_O_CTRL))) == 0) - { - return(false); - } - - // - // Read two words of data from the data registers. - // - pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L); - pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H); - - // - //Copy the data to a block memory - // - pui8DestTemp = (uint8_t *)pui32Dest; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt); - } - - // - // Return true to indicate a successful write. - // - return(true); -} - -//***************************************************************************** -// -//! Reads plaintext/ciphertext from data registers with blocking. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8Dest is a pointer to an array of bytes. -//! \param ui8Length the length can be from 1 to 8 -//! -//! This function waits until the DES module is finished and encrypted or -//! decrypted data is ready. The output data is then stored in the pui8Dest -//! array. -//! -//! \return None -// -//***************************************************************************** -void -DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, uint8_t ui8Length) -{ - volatile uint32_t pui32Dest[2]; - uint8_t ui8BytCnt; - uint8_t *pui8DestTemp; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - if((ui8Length == 0)||(ui8Length>8)) - { - return; - } - // - // Wait for data output to be ready. - // - while((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_OUTPUT_READY) == 0) - { - } - - // - // Read two words of data from the data registers. - // - pui32Dest[0] = HWREG(DES_BASE + DES_O_DATA_L); - pui32Dest[1] = HWREG(DES_BASE + DES_O_DATA_H); - - // - //Copy the data to a block memory - // - pui8DestTemp = (uint8_t *)pui32Dest; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8Dest+ui8BytCnt) = *(pui8DestTemp+ui8BytCnt); - } -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers without blocking -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8Src is a pointer to an array of 2 words. -//! \param ui8Length the length can be from 1 to 8 -//! -//! This function returns false if the DES module is not ready to accept -//! data. It returns true if the data was written successfully. -//! -//! \return true or false. -// -//***************************************************************************** -bool -DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length) -{ - - volatile uint32_t pui32Src[2]={0,0}; - uint8_t ui8BytCnt; - uint8_t *pui8SrcTemp; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - if((ui8Length == 0)||(ui8Length>8)) - { - return(false); - } - - // - // Check if the DES module is ready to encrypt or decrypt data. If it - // is not, return false. - // - if(!(DES_CTRL_INPUT_READY & (HWREG(ui32Base + DES_O_CTRL)))) - { - return(false); - } - - // - // Copy the data to a block memory - // - pui8SrcTemp = (uint8_t *)pui32Src; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt); - } - - // - // Write the data. - // - HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0]; - HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1]; - - // - // Return true to indicate a successful write. - // - return(true); -} - -//***************************************************************************** -// -//! Writes plaintext/ciphertext to data registers without blocking -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8Src is a pointer to an array of bytes. -//! \param ui8Length the length can be from 1 to 8 -//! -//! This function waits until the DES module is ready before writing the -//! data contained in the pui8Src array. -//! -//! \return None. -// -//***************************************************************************** -void -DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, uint8_t ui8Length) -{ - volatile uint32_t pui32Src[2]={0,0}; - uint8_t ui8BytCnt; - uint8_t *pui8SrcTemp; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - if((ui8Length == 0)||(ui8Length>8)) - { - return; - } - - // - // Wait for the input ready bit to go high. - // - while(((HWREG(ui32Base + DES_O_CTRL) & DES_CTRL_INPUT_READY)) == 0) - { - } - - // - //Copy the data to a block memory - // - pui8SrcTemp = (uint8_t *)pui32Src; - for(ui8BytCnt = 0; ui8BytCnt < ui8Length ; ui8BytCnt++) - { - *(pui8SrcTemp+ui8BytCnt) = *(pui8Src+ui8BytCnt); - } - - // - // Write the data. - // - HWREG(DES_BASE + DES_O_DATA_L) = pui32Src[0]; - HWREG(DES_BASE + DES_O_DATA_H) = pui32Src[1]; -} - -//***************************************************************************** -// -//! Processes blocks of data through the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pui8Src is a pointer to an array of words that contains the -//! source data for processing. -//! \param pui8Dest is a pointer to an array of words consisting of the -//! processed data. -//! \param ui32Length is the length of the cryptographic data in bytes. -//! It must be a multiple of eight. -//! -//! This function takes the data contained in the pui8Src array and processes -//! it using the DES engine. The resulting data is stored in the -//! pui8Dest array. The function blocks until all of the data has been -//! processed. If processing is successful, the function returns true. -//! -//! \note This functions assumes that the DES module has been configured, -//! and initialization values and keys have been written. -//! -//! \return true or false. -// -//***************************************************************************** -bool -DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, uint8_t *pui8Dest, - uint32_t ui32Length) -{ - uint32_t ui32Count, ui32BlkCount, ui32ByteCount; - - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32Length % 8) == 0); - - // - // Write the length register first. This triggers the engine to start - // using this context. - // - HWREG(ui32Base + DES_O_LENGTH) = ui32Length; - - - // - // Now loop until the blocks are written. - // - ui32BlkCount = ui32Length/8; - for(ui32Count = 0; ui32Count > 16); - HWREG(ui32Base + DES_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; -} - -//***************************************************************************** -// -//! Disables interrupts in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32IntFlags is a bit mask of the interrupts to be disabled. -//! -//! This function disables interrupt sources in the DES module. -//! \e ui32IntFlags should be a logical OR of one or more of the following -//! values: -//! -//! - \b DES_INT_CONTEXT_IN - Context interrupt -//! - \b DES_INT_DATA_IN - Data input interrupt -//! - \b DES_INT_DATA_OUT - Data output interrupt -//! - \b DES_INT_DMA_CONTEXT_IN - Context DMA done interrupt -//! - \b DES_INT_DMA_DATA_IN - Data input DMA done interrupt -//! - \b DES_INT_DMA_DATA_OUT - Data output DMA done interrupt -//! -//! \return None. -// -//***************************************************************************** -void -DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32IntFlags & DES_INT_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DATA_IN) || - (ui32IntFlags & DES_INT_DATA_OUT) || - (ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_OUT)); - - // - // Clear the interrupts from the flags. - // - HWREG(DTHE_BASE + DTHE_O_AES_IM) |= ((ui32IntFlags & 0x00070000) >> 16); - HWREG(ui32Base + DES_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); -} - -//***************************************************************************** -// -//! Clears interrupts in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32IntFlags is a bit mask of the interrupts to be disabled. -//! -//! This function disables interrupt sources in the DES module. -//! \e ui32IntFlags should be a logical OR of one or more of the following -//! values: -//! -//! - \b DES_INT_DMA_CONTEXT_IN - Context interrupt -//! - \b DES_INT_DMA_DATA_IN - Data input interrupt -//! - \b DES_INT_DMA_DATA_OUT - Data output interrupt -//! -//! \note The DMA done interrupts are the only interrupts that can be cleared. -//! The remaining interrupts can be disabled instead using DESIntDisable(). -//! -//! \return None. -// -//***************************************************************************** -void -DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32IntFlags & DES_INT_DMA_CONTEXT_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_IN) || - (ui32IntFlags & DES_INT_DMA_DATA_OUT)); - - HWREG(DTHE_BASE + DTHE_O_DES_IC) = ((ui32IntFlags & 0x00070000) >> 16); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled DES interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables DES interrupts on the interrupt controller; specific DES -//! interrupt sources must be enabled using DESIntEnable(). The interrupt -//! handler being registered must clear the source of the interrupt using -//! DESIntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() should be used to enable DES interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_DES, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(INT_DES); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -DESIntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_DES); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_DES); -} - -//***************************************************************************** -// -//! Enables DMA request sources in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Flags is a bit mask of the DMA requests to be enabled. -//! -//! This function enables DMA request sources in the DES module. The -//! \e ui32Flags parameter should be the logical OR of any of the following: -//! -//! - \b DES_DMA_CONTEXT_IN - Context In -//! - \b DES_DMA_DATA_OUT - Data Out -//! - \b DES_DMA_DATA_IN - Data In -//! -//! \return None. -// -//***************************************************************************** -void -DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) || - (ui32Flags & DES_DMA_DATA_OUT) || - (ui32Flags & DES_DMA_DATA_IN)); - - // - // Set the data in and data out DMA request enable bits. - // - HWREG(ui32Base + DES_O_SYSCONFIG) |= ui32Flags; -} - -//***************************************************************************** -// -//! Disables DMA request sources in the DES module. -//! -//! \param ui32Base is the base address of the DES module. -//! \param ui32Flags is a bit mask of the DMA requests to be disabled. -//! -//! This function disables DMA request sources in the DES module. The -//! \e ui32Flags parameter should be the logical OR of any of the following: -//! -//! - \b DES_DMA_CONTEXT_IN - Context In -//! - \b DES_DMA_DATA_OUT - Data Out -//! - \b DES_DMA_DATA_IN - Data In -//! -//! \return None. -// -//***************************************************************************** -void -DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == DES_BASE); - ASSERT((ui32Flags & DES_DMA_CONTEXT_IN) || - (ui32Flags & DES_DMA_DATA_OUT) || - (ui32Flags & DES_DMA_DATA_IN)); - - // - // Disable the DMA sources. - // - HWREG(ui32Base + DES_O_SYSCONFIG) &= ~ui32Flags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/des.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/des.h deleted file mode 100644 index ecd6ab61a5d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/des.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// des.h -// -// Defines and Macros for the DES module. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_DES_H__ -#define __DRIVERLIB_DES_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following defines are used to specify the direction with the -// ui32Config argument in the DESConfig() function. Only one is permitted. -// -//***************************************************************************** -#define DES_CFG_DIR_DECRYPT 0x00000000 -#define DES_CFG_DIR_ENCRYPT 0x00000004 - -//***************************************************************************** -// -// The following defines are used to specify the operational with the -// ui32Config argument in the DESConfig() function. Only one is permitted. -// -//***************************************************************************** -#define DES_CFG_MODE_ECB 0x00000000 -#define DES_CFG_MODE_CBC 0x00000010 -#define DES_CFG_MODE_CFB 0x00000020 - -//***************************************************************************** -// -// The following defines are used to select between single DES and triple DES -// with the ui32Config argument in the DESConfig() function. Only one is -// permitted. -// -//***************************************************************************** -#define DES_CFG_SINGLE 0x00000000 -#define DES_CFG_TRIPLE 0x00000008 - -//***************************************************************************** -// -// The following defines are used with the DESIntEnable(), DESIntDisable() and -// DESIntStatus() functions. -// -//***************************************************************************** -#define DES_INT_CONTEXT_IN 0x00000001 -#define DES_INT_DATA_IN 0x00000002 -#define DES_INT_DATA_OUT 0x00000004 -#define DES_INT_DMA_CONTEXT_IN 0x00010000 -#define DES_INT_DMA_DATA_IN 0x00020000 -#define DES_INT_DMA_DATA_OUT 0x00040000 - -//***************************************************************************** -// -// The following defines are used with the DESEnableDMA() and DESDisableDMA() -// functions. -// -//***************************************************************************** -#define DES_DMA_CONTEXT_IN 0x00000080 -#define DES_DMA_DATA_OUT 0x00000040 -#define DES_DMA_DATA_IN 0x00000020 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void DESConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void DESDataRead(uint32_t ui32Base, uint8_t *pui8Dest, - uint8_t ui8Length); -extern bool DESDataReadNonBlocking(uint32_t ui32Base, uint8_t *pui8Dest, - uint8_t ui8Length); -extern bool DESDataProcess(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t *pui8Dest, uint32_t ui32Length); -extern void DESDataWrite(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t ui8Length); -extern bool DESDataWriteNonBlocking(uint32_t ui32Base, uint8_t *pui8Src, - uint8_t ui8Length); -extern void DESDMADisable(uint32_t ui32Base, uint32_t ui32Flags); -extern void DESDMAEnable(uint32_t ui32Base, uint32_t ui32Flags); -extern void DESIntClear(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void DESIntDisable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void DESIntEnable(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void DESIntRegister(uint32_t ui32Base, void(*pfnHandler)(void)); -extern uint32_t DESIntStatus(uint32_t ui32Base, bool bMasked); -extern void DESIntUnregister(uint32_t ui32Base); -extern bool DESIVSet(uint32_t ui32Base, uint8_t *pui8IVdata); -extern void DESKeySet(uint32_t ui32Base, uint8_t *pui8Key); -extern void DESDataLengthSet(uint32_t ui32Base, uint32_t ui32Length); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_DES_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/flash.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/flash.c deleted file mode 100644 index 890a0447728..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/flash.c +++ /dev/null @@ -1,864 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// flash.c -// -// Driver for programming the on-chip flash. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup flash_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_types.h" -#include "inc/hw_flash_ctrl.h" -#include "inc/hw_memmap.h" -#include "inc/hw_ints.h" -#include "inc/hw_gprcm.h" -#include "inc/hw_hib1p2.h" -#include "inc/hw_hib3p3.h" -#include "inc/hw_common_reg.h" -#include "inc/hw_stack_die_ctrl.h" -#include "debug.h" -#include "flash.h" -#include "utils.h" -#include "interrupt.h" - -#define HAVE_WRITE_BUFFER 1 - - - -//***************************************************************************** -// -// An array that maps the specified memory bank to the appropriate Flash -// Memory Protection Program Enable (FMPPE) register. -// -//***************************************************************************** -static const unsigned long g_pulFMPPERegs[] = -{ - FLASH_FMPPE0, - FLASH_FMPPE1, - FLASH_FMPPE2, - FLASH_FMPPE3, - FLASH_FMPPE4, - FLASH_FMPPE5, - FLASH_FMPPE6, - FLASH_FMPPE7, - FLASH_FMPPE8, - FLASH_FMPPE9, - FLASH_FMPPE10, - FLASH_FMPPE11, - FLASH_FMPPE12, - FLASH_FMPPE13, - FLASH_FMPPE14, - FLASH_FMPPE15 - - -}; - -//***************************************************************************** -// -// An array that maps the specified memory bank to the appropriate Flash -// Memory Protection Read Enable (FMPRE) register. -// -//***************************************************************************** -static const unsigned long g_pulFMPRERegs[] = -{ - FLASH_FMPRE0, - FLASH_FMPRE1, - FLASH_FMPRE2, - FLASH_FMPRE3, - FLASH_FMPRE4, - FLASH_FMPRE5, - FLASH_FMPRE6, - FLASH_FMPRE7, - FLASH_FMPRE8, - FLASH_FMPRE9, - FLASH_FMPRE10, - FLASH_FMPRE11, - FLASH_FMPRE12, - FLASH_FMPRE13, - FLASH_FMPRE14, - FLASH_FMPRE15, -}; - -//***************************************************************************** -// -//! Flash Disable -//! -//! This function Disables the internal Flash. -//! -//! \return None. -// -//***************************************************************************** -void -FlashDisable() -{ - - // - // Wait for Flash Busy to get cleared - // - while((HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) - & GPRCM_TOP_DIE_ENABLE_FLASH_BUSY)) - { - - } - - // - // Assert reset - // - HWREG(HIB1P2_BASE + HIB1P2_O_PORPOL_SPARE) = 0xFFFF0000; - - // - // 50 usec Delay Loop - // - UtilsDelay((50*80)/3); - - // - // Disable TDFlash - // - HWREG(GPRCM_BASE + GPRCM_O_TOP_DIE_ENABLE) = 0x0; - - // - // 50 usec Delay Loop - // - UtilsDelay((50*80)/3); - - HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; - - // - // 50 usec Delay Loop - // - UtilsDelay((50*80)/3); -} - - -//***************************************************************************** -// -//! Erases a block of flash. -//! -//! \param ulAddress is the start address of the flash block to be erased. -//! -//! This function will erase a 2 kB block of the on-chip flash. After erasing, -//! the block will be filled with 0xFF bytes. Read-only and execute-only -//! blocks cannot be erased. -//! -//! This function will not return until the block has been erased. -//! -//! \return Returns 0 on success, or -1 if an invalid block address was -//! specified or the block is write-protected. -// -//***************************************************************************** -long -FlashErase(unsigned long ulAddress) -{ - // - // Check the arguments. - // - ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1))); - - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) - = (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | - FLASH_CTRL_FCMISC_ERMISC); - - // Erase the block. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) - = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE; - - // - // Wait until the block has been erased. - // - while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_ERASE) - { - } - - // - // Return an error if an access violation or erase error occurred. - // - if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) - & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS | - FLASH_CTRL_FCRIS_ERRIS)) - - - { - return(-1); - } - - // - // Success. - // - return(0); -} - - -//***************************************************************************** -// -//! Erases a block of flash but does not wait for completion. -//! -//! \param ulAddress is the start address of the flash block to be erased. -//! -//! This function will erase a 2 kB block of the on-chip flash. After erasing, -//! the block will be filled with 0xFF bytes. Read-only and execute-only -//! blocks cannot be erased. -//! -//! This function will return immediately after commanding the erase operation. -//! Applications making use of the function can determine completion state by -//! using a flash interrupt handler or by polling FlashIntStatus. -//! -//! \return None. -// -//***************************************************************************** -void -FlashEraseNonBlocking(unsigned long ulAddress) -{ - // - // Check the arguments. - // - ASSERT(!(ulAddress & (FLASH_CTRL_ERASE_SIZE - 1))); - - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = - (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | - FLASH_CTRL_FCMISC_ERMISC); - - // - // Command the flash controller to erase the block. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_ERASE; -} - - -//***************************************************************************** -// -//! Erases a complele flash at shot. -//! -//! This function erases a complele flash at shot -//! -//! \return Returns 0 on success, or -1 if the block is write-protected. -// -//***************************************************************************** -long -FlashMassErase() -{ - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = - (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | - FLASH_CTRL_FCMISC_ERMISC); - - // - // Command the flash controller for mass erase. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = - FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1; - - // - // Wait until mass erase completes. - // - while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_MERASE1) - { - - } - - // - // Return an error if an access violation or erase error occurred. - // - if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) - & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS | - FLASH_CTRL_FCRIS_ERRIS)) - { - return -1; - } - - // - // Success. - // - return 0; -} - -//***************************************************************************** -// -//! Erases a complele flash at shot but does not wait for completion. -//! -//! -//! This function will not return until the Flash has been erased. -//! -//! \return None. -// -//***************************************************************************** -void -FlashMassEraseNonBlocking() -{ - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = - (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | - FLASH_CTRL_FCMISC_ERMISC); - - // - // Command the flash controller for mass erase. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = - FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_MERASE1; - -} - -//***************************************************************************** -// -//! Programs flash. -//! -//! \param pulData is a pointer to the data to be programmed. -//! \param ulAddress is the starting address in flash to be programmed. Must -//! be a multiple of four. -//! \param ulCount is the number of bytes to be programmed. Must be a multiple -//! of four. -//! -//! This function will program a sequence of words into the on-chip flash. -//! Each word in a page of flash can only be programmed one time between an -//! erase of that page; programming a word multiple times will result in an -//! unpredictable value in that word of flash. -//! -//! Since the flash is programmed one word at a time, the starting address and -//! byte count must both be multiples of four. It is up to the caller to -//! verify the programmed contents, if such verification is required. -//! -//! This function will not return until the data has been programmed. -//! -//! \return Returns 0 on success, or -1 if a programming error is encountered. -// -//***************************************************************************** -long -FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount) -{ - // - // Check the arguments. - // - ASSERT(!(ulAddress & 3)); - ASSERT(!(ulCount & 3)); - - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) - = (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | - FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC); - - - // - // See if this device has a write buffer. - // - -#if HAVE_WRITE_BUFFER - { - // - // Loop over the words to be programmed. - // - while(ulCount) - { - // - // Set the address of this block of words. for 1 MB - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F); - - // - // Loop over the words in this 32-word block. - // - while(((ulAddress & 0x7C) || - (HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) && - (ulCount != 0)) - { - // - // Write this word into the write buffer. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN - + (ulAddress & 0x7C)) = *pulData++; - ulAddress += 4; - ulCount -= 4; - } - - // - // Program the contents of the write buffer into flash. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) - = FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF; - - // - // Wait until the write buffer has been programmed. - // - while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) & FLASH_CTRL_FMC2_WRBUF) - { - } - } - } -#else - { - // - // Loop over the words to be programmed. - // - while(ulCount) - { - // - // Program the next word. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData; - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE; - - // - // Wait until the word has been programmed. - // - while(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) & FLASH_CTRL_FMC_WRITE) - { - } - - // - // Increment to the next word. - // - pulData++; - ulAddress += 4; - ulCount -= 4; - } - } -#endif - // - // Return an error if an access violation occurred. - // - - if(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS) & (FLASH_CTRL_FCRIS_ARIS | FLASH_CTRL_FCRIS_VOLTRIS | - FLASH_CTRL_FCRIS_INVDRIS | FLASH_CTRL_FCRIS_PROGRIS)) - - { - return(-1); - } - - // - // Success. - // - return(0); -} - - -//***************************************************************************** -// -//! Programs flash but does not poll for completion. -//! -//! \param pulData is a pointer to the data to be programmed. -//! \param ulAddress is the starting address in flash to be programmed. Must -//! be a multiple of four. -//! \param ulCount is the number of bytes to be programmed. Must be a multiple -//! of four. -//! -//! This function will start programming one or more words into the on-chip -//! flash and return immediately. The number of words that can be programmed -//! in a single call depends the part on which the function is running. For -//! parts without support for a flash write buffer, only a single word may be -//! programmed on each call to this function (\e ulCount must be 1). If a -//! write buffer is present, up to 32 words may be programmed on condition -//! that the block being programmed does not straddle a 32 word address -//! boundary. For example, wherease 32 words can be programmed if the address -//! passed is 0x100 (a multiple of 128 bytes or 32 words), only 31 words could -//! be programmed at 0x104 since attempting to write 32 would cross the 32 -//! word boundary at 0x180. -//! -//! Since the flash is programmed one word at a time, the starting address and -//! byte count must both be multiples of four. It is up to the caller to -//! verify the programmed contents, if such verification is required. -//! -//! This function will return immediately after commanding the erase operation. -//! Applications making use of the function can determine completion state by -//! using a flash interrupt handler or by polling FlashIntStatus. -//! -//! \return 0 if the write was started successfully, -1 if there was an error. -// -//***************************************************************************** -long -FlashProgramNonBlocking(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount) -{ - // - // Check the arguments. - // - ASSERT(!(ulAddress & 3)); - ASSERT(!(ulCount & 3)); - - // - // Clear the flash access and error interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) - = (FLASH_CTRL_FCMISC_AMISC | FLASH_CTRL_FCMISC_VOLTMISC | - FLASH_CTRL_FCMISC_INVDMISC | FLASH_CTRL_FCMISC_PROGMISC); - - // - // See if this device has a write buffer. - // - -#if HAVE_WRITE_BUFFER - { - // - // Make sure the address/count specified doesn't straddle a 32 word - // boundary. - // - if(((ulAddress + (ulCount - 1)) & ~0x7F) != (ulAddress & ~0x7F)) - { - return(-1); - } - - // - // Loop over the words to be programmed. - // - while(ulCount) - { - // - // Set the address of this block of words. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress & ~(0x7F); - - // - // Loop over the words in this 32-word block. - // - while(((ulAddress & 0x7C) || (HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBVAL) == 0)) && - (ulCount != 0)) - { - // - // Write this word into the write buffer. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FWBN + (ulAddress & 0x7C)) = *pulData++; - ulAddress += 4; - ulCount -= 4; - } - - // - // Program the contents of the write buffer into flash. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC2) = FLASH_CTRL_FMC2_WRKEY | FLASH_CTRL_FMC2_WRBUF; - } - } -#else - { - // - // We don't have a write buffer so we can only write a single word. - // - if(ulCount > 1) - { - return(-1); - } - - // - // Write a single word. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMA) = ulAddress; - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMD) = *pulData; - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FMC) = FLASH_CTRL_FMC_WRKEY | FLASH_CTRL_FMC_WRITE; - } -#endif - // - // Success. - // - return(0); -} - - -//***************************************************************************** -// -//! Gets the protection setting for a block of flash. -//! -//! \param ulAddress is the start address of the flash block to be queried. -//! -//! This function gets the current protection for the specified 2-kB block -//! of flash. Each block can be read/write, read-only, or execute-only. -//! Read/write blocks can be read, executed, erased, and programmed. Read-only -//! blocks can be read and executed. Execute-only blocks can only be executed; -//! processor and debugger data reads are not allowed. -//! -//! \return Returns the protection setting for this block. See -//! FlashProtectSet() for possible values. -// -//***************************************************************************** -tFlashProtection -FlashProtectGet(unsigned long ulAddress) -{ - unsigned long ulFMPRE, ulFMPPE; - unsigned long ulBank; - - // - // Check the argument. - // - ASSERT(!(ulAddress & (FLASH_PROTECT_SIZE - 1))); - - // - // Calculate the Flash Bank from Base Address, and mask off the Bank - // from ulAddress for subsequent reference. - // - ulBank = (((ulAddress / FLASH_PROTECT_SIZE) / 32) % 16); - ulAddress &= ((FLASH_PROTECT_SIZE * 32) - 1); - - // - // Read the appropriate flash protection registers for the specified - // flash bank. - // - ulFMPRE = HWREG(g_pulFMPRERegs[ulBank]); - ulFMPPE = HWREG(g_pulFMPPERegs[ulBank]); - - // - // Check the appropriate protection bits for the block of memory that - // is specified by the address. - // - switch((((ulFMPRE >> (ulAddress / FLASH_PROTECT_SIZE)) & - FLASH_FMP_BLOCK_0) << 1) | - ((ulFMPPE >> (ulAddress / FLASH_PROTECT_SIZE)) & FLASH_FMP_BLOCK_0)) - { - // - // This block is marked as execute only (that is, it can not be erased - // or programmed, and the only reads allowed are via the instruction - // fetch interface). - // - case 0: - case 1: - { - return(FlashExecuteOnly); - } - - // - // This block is marked as read only (that is, it can not be erased or - // programmed). - // - case 2: - { - return(FlashReadOnly); - } - - // - // This block is read/write; it can be read, erased, and programmed. - // - case 3: - default: - { - return(FlashReadWrite); - } - } -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the flash interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the flash -//! interrupt occurs. -//! -//! This sets the handler to be called when the flash interrupt occurs. The -//! flash controller can generate an interrupt when an invalid flash access -//! occurs, such as trying to program or erase a read-only block, or trying to -//! read from an execute-only block. It can also generate an interrupt when a -//! program or erase operation has completed. The interrupt will be -//! automatically enabled when the handler is registered. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(INT_FLASH, pfnHandler); - - // - // Enable the flash interrupt. - // - IntEnable(INT_FLASH); -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the flash interrupt. -//! -//! This function will clear the handler to be called when the flash interrupt -//! occurs. This will also mask off the interrupt in the interrupt controller -//! so that the interrupt handler is no longer called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntUnregister(void) -{ - // - // Disable the interrupt. - // - IntDisable(INT_FLASH); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_FLASH); -} - -//***************************************************************************** -// -//! Enables individual flash controller interrupt sources. -//! -//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. -//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values. -//! -//! Enables the indicated flash controller interrupt sources. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntEnable(unsigned long ulIntFlags) -{ - // - // Enable the specified interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) |= ulIntFlags; -} - -//***************************************************************************** -// -//! Disables individual flash controller interrupt sources. -//! -//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled. -//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_ACCESS values. -//! -//! Disables the indicated flash controller interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntDisable(unsigned long ulIntFlags) -{ - // - // Disable the specified interrupts. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCIM) &= ~(ulIntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This returns the interrupt status for the flash controller. Either the raw -//! interrupt status or the status of interrupts that are allowed to reflect to -//! the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! \b FLASH_CTRL_PROGRAM and \b FLASH_CTRL_ACCESS. -// -//***************************************************************************** -unsigned long -FlashIntStatus(tBoolean bMasked) -{ - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC)); - } - else - { - return(HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCRIS)); - } -} - -//***************************************************************************** -// -//! Clears flash controller interrupt sources. -//! -//! \param ulIntFlags is the bit mask of the interrupt sources to be cleared. -//! Can be any of the \b FLASH_CTRL_PROGRAM or \b FLASH_CTRL_AMISC values. -//! -//! The specified flash controller interrupt sources are cleared, so that they -//! no longer assert. This must be done in the interrupt handler to keep it -//! from being called again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -FlashIntClear(unsigned long ulIntFlags) -{ - // - // Clear the flash interrupt. - // - HWREG(FLASH_CONTROL_BASE + FLASH_CTRL_O_FCMISC) = ulIntFlags; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/flash.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/flash.h deleted file mode 100644 index 75cf0cfd8db..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/flash.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// flash.h -// -// Prototypes for the flash driver. -// -//***************************************************************************** - -#ifndef __FLASH_H__ -#define __FLASH_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to FlashProtectSet(), and returned by -// FlashProtectGet(). -// -//***************************************************************************** -typedef enum -{ - FlashReadWrite, // Flash can be read and written - FlashReadOnly, // Flash can only be read - FlashExecuteOnly // Flash can only be executed -} -tFlashProtection; - -//***************************************************************************** -// -// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and -// returned from FlashIntStatus(). -// -//***************************************************************************** -#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask -#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask -#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask -#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask -#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask -#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask -#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask - - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void FlashDisable(void); -extern long FlashErase(unsigned long ulAddress); -extern void FlashEraseNonBlocking(unsigned long ulAddress); -extern long FlashMassErase(void); -extern void FlashMassEraseNonBlocking(void); -extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, - unsigned long ulCount); -extern long FlashProgramNonBlocking(unsigned long *pulData, - unsigned long ulAddress, - unsigned long ulCount); -extern void FlashIntRegister(void (*pfnHandler)(void)); -extern void FlashIntUnregister(void); -extern void FlashIntEnable(unsigned long ulIntFlags); -extern void FlashIntDisable(unsigned long ulIntFlags); -extern unsigned long FlashIntStatus(tBoolean bMasked); -extern void FlashIntClear(unsigned long ulIntFlags); -extern tFlashProtection FlashProtectGet(unsigned long ulAddress); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __FLASH_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/gpio.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/gpio.c deleted file mode 100644 index 2aa892b6779..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/gpio.c +++ /dev/null @@ -1,717 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// gpio.c -// -// Driver for the GPIO module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup GPIO_General_Purpose_InputOutput_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_types.h" -#include "inc/hw_gpio.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_common_reg.h" -#include "debug.h" -#include "gpio.h" -#include "interrupt.h" - - -//***************************************************************************** -// -//! \internal -//! Checks a GPIO base address. -//! -//! \param ulPort is the base address of the GPIO port. -//! -//! This function determines if a GPIO port base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static tBoolean -GPIOBaseValid(unsigned long ulPort) -{ - return((ulPort == GPIOA0_BASE) || - (ulPort == GPIOA1_BASE) || - (ulPort == GPIOA2_BASE) || - (ulPort == GPIOA3_BASE) || - (ulPort == GPIOA4_BASE)); -} -#endif - -//***************************************************************************** -// -//! \internal -//! Gets the GPIO interrupt number. -//! -//! \param ulPort is the base address of the GPIO port. -//! -//! Given a GPIO base address, returns the corresponding interrupt number. -//! -//! \return Returns a GPIO interrupt number, or -1 if \e ulPort is invalid. -// -//***************************************************************************** -static long -GPIOGetIntNumber(unsigned long ulPort) -{ - unsigned int ulInt; - - // - // Determine the GPIO interrupt number for the given module. - // - switch(ulPort) - { - case GPIOA0_BASE: - { - ulInt = INT_GPIOA0; - break; - } - - case GPIOA1_BASE: - { - ulInt = INT_GPIOA1; - break; - } - - case GPIOA2_BASE: - { - ulInt = INT_GPIOA2; - break; - } - - case GPIOA3_BASE: - { - ulInt = INT_GPIOA3; - break; - } - - default: - { - return(-1); - } - } - - // - // Return GPIO interrupt number. - // - return(ulInt); -} - -//***************************************************************************** -// -//! Sets the direction and mode of the specified pin(s). -//! -//! \param ulPort is the base address of the GPIO port -//! \param ucPins is the bit-packed representation of the pin(s). -//! \param ulPinIO is the pin direction and/or mode. -//! -//! This function will set the specified pin(s) on the selected GPIO port -//! as either an input or output under software control, or it will set the -//! pin to be under hardware control. -//! -//! The parameter \e ulPinIO is an enumerated data type that can be one of -//! the following values: -//! -//! - \b GPIO_DIR_MODE_IN -//! - \b GPIO_DIR_MODE_OUT -//! -//! where \b GPIO_DIR_MODE_IN specifies that the pin will be programmed as -//! a software controlled input, \b GPIO_DIR_MODE_OUT specifies that the pin -//! will be programmed as a software controlled output. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note GPIOPadConfigSet() must also be used to configure the corresponding -//! pad(s) in order for them to propagate the signal to/from the GPIO. -//! -//! \return None. -// -//***************************************************************************** -void -GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - ASSERT((ulPinIO == GPIO_DIR_MODE_IN) || (ulPinIO == GPIO_DIR_MODE_OUT)); - - // - // Set the pin direction and mode. - // - HWREG(ulPort + GPIO_O_GPIO_DIR) = ((ulPinIO & 1) ? - (HWREG(ulPort + GPIO_O_GPIO_DIR) | ucPins) : - (HWREG(ulPort + GPIO_O_GPIO_DIR) & ~(ucPins))); -} - -//***************************************************************************** -// -//! Gets the direction and mode of a pin. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPin is the pin number. -//! -//! This function gets the direction and control mode for a specified pin on -//! the selected GPIO port. The pin can be configured as either an input or -//! output under software control, or it can be under hardware control. The -//! type of control and direction are returned as an enumerated data type. -//! -//! \return Returns one of the enumerated data types described for -//! GPIODirModeSet(). -// -//***************************************************************************** -unsigned long -GPIODirModeGet(unsigned long ulPort, unsigned char ucPin) -{ - unsigned long ulDir; - - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - ASSERT(ucPin < 8); - - // - // Convert from a pin number to a bit position. - // - ucPin = 1 << ucPin; - - // - // Return the pin direction and mode. - // - ulDir = HWREG(ulPort + GPIO_O_GPIO_DIR); - return(((ulDir & ucPin) ? 1 : 0)); -} - -//***************************************************************************** -// -//! Sets the interrupt type for the specified pin(s). -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPins is the bit-packed representation of the pin(s). -//! \param ulIntType specifies the type of interrupt trigger mechanism. -//! -//! This function sets up the various interrupt trigger mechanisms for the -//! specified pin(s) on the selected GPIO port. -//! -//! The parameter \e ulIntType is an enumerated data type that can be one of -//! the following values: -//! -//! - \b GPIO_FALLING_EDGE -//! - \b GPIO_RISING_EDGE -//! - \b GPIO_BOTH_EDGES -//! - \b GPIO_LOW_LEVEL -//! - \b GPIO_HIGH_LEVEL -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \note In order to avoid any spurious interrupts, the user must -//! ensure that the GPIO inputs remain stable for the duration of -//! this function. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - ASSERT((ulIntType == GPIO_FALLING_EDGE) || - (ulIntType == GPIO_RISING_EDGE) || (ulIntType == GPIO_BOTH_EDGES) || - (ulIntType == GPIO_LOW_LEVEL) || (ulIntType == GPIO_HIGH_LEVEL)); - - // - // Set the pin interrupt type. - // - HWREG(ulPort + GPIO_O_GPIO_IBE) = ((ulIntType & 1) ? - (HWREG(ulPort + GPIO_O_GPIO_IBE) | ucPins) : - (HWREG(ulPort + GPIO_O_GPIO_IBE) & ~(ucPins))); - HWREG(ulPort + GPIO_O_GPIO_IS) = ((ulIntType & 2) ? - (HWREG(ulPort + GPIO_O_GPIO_IS) | ucPins) : - (HWREG(ulPort + GPIO_O_GPIO_IS) & ~(ucPins))); - HWREG(ulPort + GPIO_O_GPIO_IEV) = ((ulIntType & 4) ? - (HWREG(ulPort + GPIO_O_GPIO_IEV) | ucPins) : - (HWREG(ulPort + GPIO_O_GPIO_IEV) & ~(ucPins))); -} - -//***************************************************************************** -// -//! Gets the interrupt type for a pin. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPin is the pin number. -//! -//! This function gets the interrupt type for a specified pin on the selected -//! GPIO port. The pin can be configured as a falling edge, rising edge, or -//! both edge detected interrupt, or it can be configured as a low level or -//! high level detected interrupt. The type of interrupt detection mechanism -//! is returned as an enumerated data type. -//! -//! \return Returns one of the enumerated data types described for -//! GPIOIntTypeSet(). -// -//***************************************************************************** -unsigned long -GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin) -{ - unsigned long ulIBE, ulIS, ulIEV; - - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - ASSERT(ucPin < 8); - - // - // Convert from a pin number to a bit position. - // - ucPin = 1 << ucPin; - - // - // Return the pin interrupt type. - // - ulIBE = HWREG(ulPort + GPIO_O_GPIO_IBE); - ulIS = HWREG(ulPort + GPIO_O_GPIO_IS); - ulIEV = HWREG(ulPort + GPIO_O_GPIO_IEV); - return(((ulIBE & ucPin) ? 1 : 0) | ((ulIS & ucPin) ? 2 : 0) | - ((ulIEV & ucPin) ? 4 : 0)); -} - -//***************************************************************************** -// -//! Enables the specified GPIO interrupts. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ulIntFlags is the bit mask of the interrupt sources to enable. -//! -//! This function enables the indicated GPIO interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! -//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done -//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. -//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. -//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. -//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. -//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. -//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. -//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. -//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Enable the interrupts. - // - HWREG(ulPort + GPIO_O_GPIO_IM) |= ulIntFlags; -} - -//***************************************************************************** -// -//! Disables the specified GPIO interrupts. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ulIntFlags is the bit mask of the interrupt sources to disable. -//! -//! This function disables the indicated GPIO interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! -//! - \b GPIO_INT_DMA - interrupt due to GPIO triggered DMA Done -//! - \b GPIO_INT_PIN_0 - interrupt due to activity on Pin 0. -//! - \b GPIO_INT_PIN_1 - interrupt due to activity on Pin 1. -//! - \b GPIO_INT_PIN_2 - interrupt due to activity on Pin 2. -//! - \b GPIO_INT_PIN_3 - interrupt due to activity on Pin 3. -//! - \b GPIO_INT_PIN_4 - interrupt due to activity on Pin 4. -//! - \b GPIO_INT_PIN_5 - interrupt due to activity on Pin 5. -//! - \b GPIO_INT_PIN_6 - interrupt due to activity on Pin 6. -//! - \b GPIO_INT_PIN_7 - interrupt due to activity on Pin 7. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Disable the interrupts. - // - HWREG(ulPort + GPIO_O_GPIO_IM) &= ~(ulIntFlags); -} - -//***************************************************************************** -// -//! Gets interrupt status for the specified GPIO port. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param bMasked specifies whether masked or raw interrupt status is -//! returned. -//! -//! If \e bMasked is set as \b true, then the masked interrupt status is -//! returned; otherwise, the raw interrupt status will be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in GPIOIntEnable(). -// -//***************************************************************************** -long -GPIOIntStatus(unsigned long ulPort, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Return the interrupt status. - // - if(bMasked) - { - return(HWREG(ulPort + GPIO_O_GPIO_MIS)); - } - else - { - return(HWREG(ulPort + GPIO_O_GPIO_RIS)); - } -} - -//***************************************************************************** -// -//! Clears the interrupt for the specified pin(s). -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! Clears the interrupt for the specified pin(s). -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to GPIOIntEnable(). -//! -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Clear the interrupts. - // - HWREG(ulPort + GPIO_O_GPIO_ICR) = ulIntFlags; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a GPIO port. -//! -//! \param ulPort is the base address of the GPIO port. -//! \param pfnIntHandler is a pointer to the GPIO port interrupt handling -//! function. -//! -//! This function will ensure that the interrupt handler specified by -//! \e pfnIntHandler is called when an interrupt is detected from the selected -//! GPIO port. This function will also enable the corresponding GPIO interrupt -//! in the interrupt controller; individual pin interrupts and interrupt -//! sources must be enabled with GPIOIntEnable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntRegister(unsigned long ulPort, void (*pfnIntHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ulPort = GPIOGetIntNumber(ulPort); - - // - // Register the interrupt handler. - // - IntRegister(ulPort, pfnIntHandler); - - // - // Enable the GPIO interrupt. - // - IntEnable(ulPort); -} - -//***************************************************************************** -// -//! Removes an interrupt handler for a GPIO port. -//! -//! \param ulPort is the base address of the GPIO port. -//! -//! This function will unregister the interrupt handler for the specified -//! GPIO port. This function will also disable the corresponding -//! GPIO port interrupt in the interrupt controller; individual GPIO interrupts -//! and interrupt sources must be disabled with GPIOIntDisable(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOIntUnregister(unsigned long ulPort) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Get the interrupt number associated with the specified GPIO. - // - ulPort = GPIOGetIntNumber(ulPort); - - // - // Disable the GPIO interrupt. - // - IntDisable(ulPort); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulPort); -} - -//***************************************************************************** -// -//! Reads the values present of the specified pin(s). -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPins is the bit-packed representation of the pin(s). -//! -//! The values at the specified pin(s) are read, as specified by \e ucPins. -//! Values are returned for both input and output pin(s), and the value -//! for pin(s) that are not specified by \e ucPins are set to 0. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return Returns a bit-packed byte providing the state of the specified -//! pin, where bit 0 of the byte represents GPIO port pin 0, bit 1 represents -//! GPIO port pin 1, and so on. Any bit that is not specified by \e ucPins -//! is returned as a 0. Bits 31:8 should be ignored. -// -//***************************************************************************** -long -GPIOPinRead(unsigned long ulPort, unsigned char ucPins) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Return the pin value(s). - // - return(HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2)))); -} - -//***************************************************************************** -// -//! Writes a value to the specified pin(s). -//! -//! \param ulPort is the base address of the GPIO port. -//! \param ucPins is the bit-packed representation of the pin(s). -//! \param ucVal is the value to write to the pin(s). -//! -//! Writes the corresponding bit values to the output pin(s) specified by -//! \e ucPins. Writing to a pin configured as an input pin has no effect. -//! -//! The pin(s) are specified using a bit-packed byte, where each bit that is -//! set identifies the pin to be accessed, and where bit 0 of the byte -//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. -//! -//! \return None. -// -//***************************************************************************** -void -GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, unsigned char ucVal) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Write the pins. - // - HWREG(ulPort + (GPIO_O_GPIO_DATA + (ucPins << 2))) = ucVal; -} - -//***************************************************************************** -// -//! Enables a GPIO port as a trigger to start a DMA transaction. -//! -//! \param ulPort is the base address of the GPIO port. -//! -//! This function enables a GPIO port to be used as a trigger to start a uDMA -//! transaction. The GPIO pin will still generate interrupts if the interrupt is -//! enabled for the selected pin. -//! -//! \return None. -// -//***************************************************************************** -void -GPIODMATriggerEnable(unsigned long ulPort) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Set the pin as a DMA trigger. - // - if(ulPort == GPIOA0_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x1; - } - else if(ulPort == GPIOA1_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x2; - } - else if(ulPort == GPIOA2_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x4; - } - else if(ulPort == GPIOA3_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) |= 0x8; - } -} - -//***************************************************************************** -// -//! Disables a GPIO port as a trigger to start a DMA transaction. -//! -//! \param ulPort is the base address of the GPIO port. -//! -//! This function disables a GPIO port to be used as a trigger to start a uDMA -//! transaction. This function can be used to disable this feature if it was -//! enabled via a call to GPIODMATriggerEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -GPIODMATriggerDisable(unsigned long ulPort) -{ - // - // Check the arguments. - // - ASSERT(GPIOBaseValid(ulPort)); - - // - // Set the pin as a DMA trigger. - // - if(ulPort == GPIOA0_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x1; - } - else if(ulPort == GPIOA1_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x2; - } - else if(ulPort == GPIOA2_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x4; - } - else if(ulPort == GPIOA3_BASE) - { - HWREG(COMMON_REG_BASE + COMMON_REG_O_APPS_GPIO_TRIG_EN) &= ~0x8; - } -} - - -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/gpio.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/gpio.h deleted file mode 100644 index 525bf4e79ea..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/gpio.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// gpio.h -// -// Defines and Macros for GPIO API. -// -//***************************************************************************** - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following values define the bit field for the ucPins argument to several -// of the APIs. -// -//***************************************************************************** -#define GPIO_PIN_0 0x00000001 // GPIO pin 0 -#define GPIO_PIN_1 0x00000002 // GPIO pin 1 -#define GPIO_PIN_2 0x00000004 // GPIO pin 2 -#define GPIO_PIN_3 0x00000008 // GPIO pin 3 -#define GPIO_PIN_4 0x00000010 // GPIO pin 4 -#define GPIO_PIN_5 0x00000020 // GPIO pin 5 -#define GPIO_PIN_6 0x00000040 // GPIO pin 6 -#define GPIO_PIN_7 0x00000080 // GPIO pin 7 - -//***************************************************************************** -// -// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and -// returned from GPIODirModeGet. -// -//***************************************************************************** -#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input -#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output - -//***************************************************************************** -// -// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and -// returned from GPIOIntTypeGet. -// -//***************************************************************************** -#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge -#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge -#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges -#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level -#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level - -//***************************************************************************** -// -// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions -// in the ulIntFlags parameter. -// -//***************************************************************************** -#define GPIO_INT_DMA 0x00000100 -#define GPIO_INT_PIN_0 0x00000001 -#define GPIO_INT_PIN_1 0x00000002 -#define GPIO_INT_PIN_2 0x00000004 -#define GPIO_INT_PIN_3 0x00000008 -#define GPIO_INT_PIN_4 0x00000010 -#define GPIO_INT_PIN_5 0x00000020 -#define GPIO_INT_PIN_6 0x00000040 -#define GPIO_INT_PIN_7 0x00000080 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulPinIO); -extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, - unsigned long ulIntType); -extern void GPIODMATriggerEnable(unsigned long ulPort); -extern void GPIODMATriggerDisable(unsigned long ulPort); -extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); -extern void GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags); -extern void GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags); -extern long GPIOIntStatus(unsigned long ulPort, tBoolean bMasked); -extern void GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags); -extern void GPIOIntRegister(unsigned long ulPort, - void (*pfnIntHandler)(void)); -extern void GPIOIntUnregister(unsigned long ulPort); -extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); -extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, - unsigned char ucVal); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __GPIO_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/hwspinlock.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/hwspinlock.c deleted file mode 100644 index d483688b08d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/hwspinlock.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// hwspinlock.c -// -// Driver for the Apps-NWP spinlock -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup HwSpinLock_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_types.h" -#include "inc/hw_memmap.h" -#include "inc/hw_ints.h" -#include "inc/hw_common_reg.h" -#include "hwspinlock.h" - -//***************************************************************************** -// Global semaphore register list -//***************************************************************************** -static const uint32_t HwSpinLock_RegLst[]= -{ - COMMON_REG_BASE + COMMON_REG_O_SPI_Properties_Register -}; - -//***************************************************************************** -// -//! Acquire specified spin lock. -//! -//! \param ui32LockID is one of the valid spin lock. -//! -//! This function acquires specified spin lock and will not retun util the -//! specified lock is acquired. -//! -//! The parameter \e ui32LockID should \b HWSPINLOCK_MCSPIS0. -//! -//! return None. -// -//***************************************************************************** -void HwSpinLockAcquire(uint32_t ui32LockID) -{ - uint32_t ui32BitPos; - uint32_t ui32SemVal; - uint32_t ui32RegAddr; - - // - // Extract the bit position from the - // LockID - // - ui32BitPos = ((ui32LockID >> 16) & 0x0FFF); - ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF]; - - // - // Set the corresponding - // ownership bits to 'b01 - // - ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos)); - - // - // Retry untill we succeed - // - do - { - HWREG(ui32RegAddr) = ui32SemVal; - } - while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) ); - -} - -//***************************************************************************** -// -//! Try to acquire specified spin lock. -//! -//! \param ui32LockID is one of the valid spin lock. -//! \param ui32Retry is the number of reties. -//! -//! This function tries acquire specified spin lock in \e ui32Retry retries. -//! -//! The parameter \e ui32Retry can be any value between 0 and 2^32. -//! -//! return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry) -{ - uint32_t ui32BitPos; - uint32_t ui32SemVal; - uint32_t ui32RegAddr; - - // - // Extract the bit position from the - // LockID - // - ui32BitPos = ((ui32LockID >> 16) & 0x0FFF); - ui32RegAddr = HwSpinLock_RegLst[ui32LockID & 0xF]; - - // - // Set the corresponding - // ownership bits to 'b01 - // - ui32SemVal = (0xFFFFFFFF ^ (0x2 << ui32BitPos)); - - // - // Check for 0 retry. - // - if(ui32Retry == 0) - { - ui32Retry = 1; - } - - // - // Retry the number of times specified - // - do - { - HWREG(ui32RegAddr) = ui32SemVal; - ui32Retry--; - } - while( !(HWREG(ui32RegAddr) & (1 << ui32BitPos )) && ui32Retry ); - - - // - // Check the semaphore status - // - if(HWREG(ui32RegAddr) & (1 << ui32BitPos )) - { - return 0; - } - else - { - return -1; - } -} - -//***************************************************************************** -// -//! Release a previously owned spin lock -//! -//! \param ui32LockID is one of the valid spin lock. -//! -//! This function releases previously owned spin lock. -//! -//! \return None. -// -//***************************************************************************** -void HwSpinLockRelease(uint32_t ui32LockID) -{ - uint32_t ui32BitPos; - uint32_t ui32SemVal; - - // - // Extract the bit position from the - // lock id. - // - ui32BitPos = ((ui32LockID >> 16) & 0x00FF); - - // - // Release the spin lock, only if already owned - // - if(HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) & (1 << ui32BitPos )) - { - ui32SemVal = (0xFFFFFFFF & ~(0x3 << ui32BitPos)); - HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) = ui32SemVal; - } -} - -//***************************************************************************** -// -//! Get the current or previous ownership status. -//! -//! \param ui32LockID is one of the valid spin lock. -//! \param bCurrentStatus is \b true for current status, \b flase otherwise -//! -//! This function gets the current or previous ownership status of the -//! specified spin lock based on \e bCurrentStatus parameter. -//! -//! \return Returns \b HWSPINLOCK_OWNER_APPS, \b HWSPINLOCK_OWNER_NWP or -//! \b HWSPINLOCK_OWNER_NONE. -// -//***************************************************************************** -uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus) -{ - uint32_t ui32BitPos; - uint32_t ui32SemVal; - - if(bCurrentStatus) - { - // - // Extract the bit position from the - // lock id. - // - ui32BitPos = ((ui32LockID >> 16) & 0x00FF); - - // - // return semaphore - // - return((HWREG(HwSpinLock_RegLst[ui32LockID & 0xF]) >> ui32BitPos ) & 0x3 ); - } - else - { - // - // Extract the bit position - // - ui32BitPos = ((ui32LockID >> 24) & 0xFF); - - // - // Identify which register to read - // - if(ui32LockID & 0xF > 4) - { - ui32SemVal = ((HWREG(COMMON_REG_BASE + - COMMON_REG_O_SEMAPHORE_PREV_OWNER1) >> ui32BitPos ) & 0x3); - } - else - { - ui32SemVal = ((HWREG(COMMON_REG_BASE + - COMMON_REG_O_SEMAPHORE_PREV_OWNER2) >> ui32BitPos ) & 0x3); - } - - // - // return the owner - // - return ui32SemVal; - } -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/hwspinlock.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/hwspinlock.h deleted file mode 100644 index 70277321208..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/hwspinlock.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// hwspinlock.h -// -// Prototypes for the Apps-NWP spinlock. -// -//***************************************************************************** - -#ifndef __HWSPINLOCK_H__ -#define __HWSPINLOCK_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// values that can be passed to API as ui32LockID parameter -//***************************************************************************** -#define HWSPINLOCK_SSPI 0x02000000 - -//***************************************************************************** -// Values that are returned from HwSpinLockTest() -//***************************************************************************** -#define HWSPINLOCK_OWNER_APPS 0x00000001 -#define HWSPINLOCK_OWNER_NWP 0x00000002 -#define HWSPINLOCK_OWNER_NONE 0x00000000 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void HwSpinLockAcquire(uint32_t ui32LockID); -extern int32_t HwSpinLockTryAcquire(uint32_t ui32LockID, uint32_t ui32Retry); -extern void HwSpinLockRelease(uint32_t ui32LockID); -extern uint32_t HwSpinLockTest(uint32_t ui32LockID, bool bCurrentStatus); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __HWSPINLOCK_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2c.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2c.c deleted file mode 100644 index 3c7f26af69b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2c.c +++ /dev/null @@ -1,2053 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// i2c.c -// -// Driver for Inter-IC (I2C) bus block. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup I2C_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_i2c.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "debug.h" -#include "i2c.h" -#include "interrupt.h" - -//***************************************************************************** -// -// A mapping of I2C base address to interrupt number. -// -//***************************************************************************** -static const uint32_t g_ppui32I2CIntMap[][2] = -{ - { I2CA0_BASE, INT_I2CA0}, -}; - -static const int_fast8_t g_i8I2CIntMapRows = - sizeof(g_ppui32I2CIntMap) / sizeof(g_ppui32I2CIntMap[0]); - -//***************************************************************************** -// -//! \internal -//! Checks an I2C base address. -//! -//! \param ui32Base is the base address of the I2C module. -//! -//! This function determines if a I2C module base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static bool -_I2CBaseValid(uint32_t ui32Base) -{ - return((ui32Base == I2CA0_BASE)); -} -#endif - -//***************************************************************************** -// -//! \internal -//! Gets the I2C interrupt number. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! Given a I2C base address, this function returns the corresponding -//! interrupt number. -//! -//! \return Returns an I2C interrupt number, or 0 if \e ui32Base is invalid. -// -//***************************************************************************** -static uint32_t -_I2CIntNumberGet(uint32_t ui32Base) -{ - int_fast8_t i8Idx, i8Rows; - const uint32_t (*ppui32I2CIntMap)[2]; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - ppui32I2CIntMap = g_ppui32I2CIntMap; - i8Rows = g_i8I2CIntMapRows; - - // - // Loop through the table that maps I2C base addresses to interrupt - // numbers. - // - for(i8Idx = 0; i8Idx < i8Rows; i8Idx++) - { - // - // See if this base address matches. - // - if(ppui32I2CIntMap[i8Idx][0] == ui32Base) - { - // - // Return the corresponding interrupt number. - // - return(ppui32I2CIntMap[i8Idx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(0); -} - -//***************************************************************************** -// -//! Initializes the I2C Master block. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32I2CClk is the rate of the clock supplied to the I2C module. -//! \param bFast set up for fast data transfers. -//! -//! This function initializes operation of the I2C Master block by configuring -//! the bus speed for the master and enabling the I2C Master block. -//! -//! If the parameter \e bFast is \b true, then the master block is set up to -//! transfer data at 400 Kbps; otherwise, it is set up to transfer data at -//! 100 Kbps. If Fast Mode Plus (1 Mbps) is desired, software should manually -//! write the I2CMTPR after calling this function. For High Speed (3.4 Mbps) -//! mode, a specific command is used to switch to the faster clocks after the -//! initial communication with the slave is done at either 100 Kbps or -//! 400 Kbps. -//! -//! The peripheral clock frequency is returned by PRCMPeripheralClockGet(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, - bool bFast) -{ - uint32_t ui32SCLFreq; - uint32_t ui32TPR; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Must enable the device before doing anything else. - // - I2CMasterEnable(ui32Base); - - // - // Get the desired SCL speed. - // - if(bFast == true) - { - ui32SCLFreq = 400000; - } - else - { - ui32SCLFreq = 100000; - } - - // - // Compute the clock divider that achieves the fastest speed less than or - // equal to the desired speed. The numerator is biased to favor a larger - // clock divider so that the resulting clock is always less than or equal - // to the desired clock, never greater. - // - ui32TPR = ((ui32I2CClk + (2 * 10 * ui32SCLFreq) - 1) / - (2 * 10 * ui32SCLFreq)) - 1; - HWREG(ui32Base + I2C_O_MTPR) = ui32TPR; - - // - // Check to see if this I2C peripheral is High-Speed enabled. If yes, also - // choose the fastest speed that is less than or equal to 3.4 Mbps. - // - if(HWREG(ui32Base + I2C_O_PP) & I2C_PP_HS) - { - ui32TPR = ((ui32I2CClk + (2 * 3 * 3400000) - 1) / - (2 * 3 * 3400000)) - 1; - HWREG(ui32Base + I2C_O_MTPR) = I2C_MTPR_HS | ui32TPR; - } -} - -//***************************************************************************** -// -//! Initializes the I2C Slave block. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui8SlaveAddr 7-bit slave address -//! -//! This function initializes operation of the I2C Slave block by configuring -//! the slave address and enabling the I2C Slave block. -//! -//! The parameter \e ui8SlaveAddr is the value that is compared against the -//! slave address sent by an I2C master. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // - // Must enable the device before doing anything else. - // - I2CSlaveEnable(ui32Base); - - // - // Set up the slave address. - // - HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; -} - -//***************************************************************************** -// -//! Sets the I2C slave address. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui8AddrNum determines which slave address is set. -//! \param ui8SlaveAddr is the 7-bit slave address -//! -//! This function writes the specified slave address. The \e ui32AddrNum field -//! dictates which slave address is configured. For example, a value of 0 -//! configures the primary address and a value of 1 configures the secondary. -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, uint8_t ui8SlaveAddr) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT(!(ui8AddrNum > 1)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // - // Determine which slave address is being set. - // - switch(ui8AddrNum) - { - // - // Set up the primary slave address. - // - case 0: - { - HWREG(ui32Base + I2C_O_SOAR) = ui8SlaveAddr; - break; - } - - // - // Set up and enable the secondary slave address. - // - case 1: - { - HWREG(ui32Base + I2C_O_SOAR2) = I2C_SOAR2_OAR2EN | ui8SlaveAddr; - break; - } - } -} - -//***************************************************************************** -// -//! Enables the I2C Master block. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function enables operation of the I2C Master block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the master block. - // - HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_MFE; -} - -//***************************************************************************** -// -//! Enables the I2C Slave block. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This fucntion enables operation of the I2C Slave block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the clock to the slave block. - // - HWREG(ui32Base + I2C_O_MCR) |= I2C_MCR_SFE; - - // - // Enable the slave. - // - HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; -} - -//***************************************************************************** -// -//! Disables the I2C master block. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function disables operation of the I2C master block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the master block. - // - HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_MFE); -} - -//***************************************************************************** -// -//! Disables the I2C slave block. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This function disables operation of the I2C slave block. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the slave. - // - HWREG(ui32Base + I2C_O_SCSR) = 0; - - // - // Disable the clock to the slave block. - // - HWREG(ui32Base + I2C_O_MCR) &= ~(I2C_MCR_SFE); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the I2C module. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param pfnHandler is a pointer to the function to be called when the -//! I2C interrupt occurs. -//! -//! This function sets the handler to be called when an I2C interrupt occurs. -//! This function enables the global interrupt in the interrupt controller; -//! specific I2C interrupts must be enabled via I2CMasterIntEnable() and -//! I2CSlaveIntEnable(). If necessary, it is the interrupt handler's -//! responsibility to clear the interrupt source via I2CMasterIntClear() and -//! I2CSlaveIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -I2CIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the I2C port. - // - ui32Int = _I2CIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the I2C interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the I2C module. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function clears the handler to be called when an I2C interrupt -//! occurs. This function also masks off the interrupt in the interrupt r -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -I2CIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Determine the interrupt number based on the I2C port. - // - ui32Int = _I2CIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Enables the I2C Master interrupt. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function enables the I2C Master interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) = 1; -} - -//***************************************************************************** -// -//! Enables individual I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated I2C Master interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b I2C_MASTER_INT_RX_FIFO_FULL - RX FIFO Full interrupt -//! - \b I2C_MASTER_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt -//! - \b I2C_MASTER_INT_RX_FIFO_REQ - RX FIFO Request interrupt -//! - \b I2C_MASTER_INT_TX_FIFO_REQ - TX FIFO Request interrupt -//! - \b I2C_MASTER_INT_ARB_LOST - Arbitration Lost interrupt -//! - \b I2C_MASTER_INT_STOP - Stop Condition interrupt -//! - \b I2C_MASTER_INT_START - Start Condition interrupt -//! - \b I2C_MASTER_INT_NACK - Address/Data NACK interrupt -//! - \b I2C_MASTER_INT_TX_DMA_DONE - TX DMA Complete interrupt -//! - \b I2C_MASTER_INT_RX_DMA_DONE - RX DMA Complete interrupt -//! - \b I2C_MASTER_INT_TIMEOUT - Clock Timeout interrupt -//! - \b I2C_MASTER_INT_DATA - Data interrupt -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Enables the I2C Slave interrupt. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This function enables the I2C Slave interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) |= I2C_SLAVE_INT_DATA; -} - -//***************************************************************************** -// -//! Enables individual I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated I2C Slave interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter is the logical OR of any of the following: -//! -//! - \b I2C_SLAVE_INT_RX_FIFO_FULL - RX FIFO Full interrupt -//! - \b I2C_SLAVE_INT_TX_FIFO_EMPTY - TX FIFO Empty interrupt -//! - \b I2C_SLAVE_INT_RX_FIFO_REQ - RX FIFO Request interrupt -//! - \b I2C_SLAVE_INT_TX_FIFO_REQ - TX FIFO Request interrupt -//! - \b I2C_SLAVE_INT_TX_DMA_DONE - TX DMA Complete interrupt -//! - \b I2C_SLAVE_INT_RX_DMA_DONE - RX DMA Complete interrupt -//! - \b I2C_SLAVE_INT_STOP - Stop condition detected interrupt -//! - \b I2C_SLAVE_INT_START - Start condition detected interrupt -//! - \b I2C_SLAVE_INT_DATA - Data interrupt -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) |= ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables the I2C Master interrupt. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function disables the I2C Master interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) = 0; -} - -//***************************************************************************** -// -//! Disables individual I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated I2C Master interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CMasterIntEnableEx(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the master interrupt. - // - HWREG(ui32Base + I2C_O_MIMR) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Disables the I2C Slave interrupt. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This function disables the I2C Slave interrupt source. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) &= ~I2C_SLAVE_INT_DATA; -} - -//***************************************************************************** -// -//! Disables individual I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui32IntFlags is the bit mask of the interrupt sources to be -//! disabled. -//! -//! This function disables the indicated I2C Slave interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntDisableEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable the slave interrupt. - // - HWREG(ui32Base + I2C_O_SIMR) &= ~ui32IntFlags; -} - -//***************************************************************************** -// -//! Gets the current I2C Master interrupt status. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C Master module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, returned as \b true if active -//! or \b false if not active. -// -//***************************************************************************** -bool -I2CMasterIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return((HWREG(ui32Base + I2C_O_MMIS)) ? true : false); - } - else - { - return((HWREG(ui32Base + I2C_O_MRIS)) ? true : false); - } -} - -//***************************************************************************** -// -//! Gets the current I2C Master interrupt status. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C Master module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in I2CMasterIntEnableEx(). -// -//***************************************************************************** -uint32_t -I2CMasterIntStatusEx(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + I2C_O_MMIS)); - } - else - { - return(HWREG(ui32Base + I2C_O_MRIS)); - } -} - -//***************************************************************************** -// -//! Gets the current I2C Slave interrupt status. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C Slave module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return The current interrupt status, returned as \b true if active -//! or \b false if not active. -// -//***************************************************************************** -bool -I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return((HWREG(ui32Base + I2C_O_SMIS)) ? true : false); - } - else - { - return((HWREG(ui32Base + I2C_O_SRIS)) ? true : false); - } -} - -//***************************************************************************** -// -//! Gets the current I2C Slave interrupt status. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param bMasked is false if the raw interrupt status is requested and -//! true if the masked interrupt status is requested. -//! -//! This function returns the interrupt status for the I2C Slave module. -//! Either the raw interrupt status or the status of interrupts that are -//! allowed to reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in I2CSlaveIntEnableEx(). -// -//***************************************************************************** -uint32_t -I2CSlaveIntStatusEx(uint32_t ui32Base, bool bMasked) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ui32Base + I2C_O_SMIS)); - } - else - { - return(HWREG(ui32Base + I2C_O_SRIS)); - } -} - -//***************************************************************************** -// -//! Clears I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! The I2C Master interrupt source is cleared, so that it no longer -//! asserts. This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C master interrupt source. - // - HWREG(ui32Base + I2C_O_MICR) = I2C_MICR_IC; - - // - // Workaround for I2C master interrupt clear errata for some - // devices. For later devices, this write is ignored and therefore - // harmless (other than the slight performance hit). - // - HWREG(ui32Base + I2C_O_MMIS) = I2C_MICR_IC; -} - -//***************************************************************************** -// -//! Clears I2C Master interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified I2C Master interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CMasterIntEnableEx(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C master interrupt source. - // - HWREG(ui32Base + I2C_O_MICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Clears I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! The I2C Slave interrupt source is cleared, so that it no longer asserts. -//! This function must be called in the interrupt handler to keep the interrupt -//! from being triggered again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntClear(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C slave interrupt source. - // - HWREG(ui32Base + I2C_O_SICR) = I2C_SICR_DATAIC; -} - -//***************************************************************************** -// -//! Clears I2C Slave interrupt sources. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui32IntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified I2C Slave interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep the interrupt from being triggered again immediately upon exit. -//! -//! The \e ui32IntFlags parameter has the same definition as the -//! \e ui32IntFlags parameter to I2CSlaveIntEnableEx(). -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear the I2C slave interrupt source. - // - HWREG(ui32Base + I2C_O_SICR) = ui32IntFlags; -} - -//***************************************************************************** -// -//! Sets the address that the I2C Master places on the bus. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui8SlaveAddr 7-bit slave address -//! \param bReceive flag indicating the type of communication with the slave -//! -//! This function configures the address that the I2C Master places on the -//! bus when initiating a transaction. When the \e bReceive parameter is set -//! to \b true, the address indicates that the I2C Master is initiating a -//! read from the slave; otherwise the address indicates that the I2C -//! Master is initiating a write to the slave. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterSlaveAddrSet(uint32_t ui32Base, uint8_t ui8SlaveAddr, - bool bReceive) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT(!(ui8SlaveAddr & 0x80)); - - // - // Set the address of the slave with which the master will communicate. - // - HWREG(ui32Base + I2C_O_MSA) = (ui8SlaveAddr << 1) | bReceive; -} - -//***************************************************************************** -// -//! Reads the state of the SDA and SCL pins. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function returns the state of the I2C bus by providing the real time -//! values of the SDA and SCL pins. -//! -//! -//! \return Returns the state of the bus with SDA in bit position 1 and SCL in -//! bit position 0. -// -//***************************************************************************** -uint32_t -I2CMasterLineStateGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the line state. - // - return(HWREG(ui32Base + I2C_O_MBMON)); -} - -//***************************************************************************** -// -//! Indicates whether or not the I2C Master is busy. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function returns an indication of whether or not the I2C Master is -//! busy transmitting or receiving data. -//! -//! \return Returns \b true if the I2C Master is busy; otherwise, returns -//! \b false. -// -//***************************************************************************** -bool -I2CMasterBusy(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the busy status. - // - if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSY) - { - return(true); - } - else - { - return(false); - } -} - -//***************************************************************************** -// -//! Indicates whether or not the I2C bus is busy. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function returns an indication of whether or not the I2C bus is busy. -//! This function can be used in a multi-master environment to determine if -//! another master is currently using the bus. -//! -//! \return Returns \b true if the I2C bus is busy; otherwise, returns -//! \b false. -// -//***************************************************************************** -bool -I2CMasterBusBusy(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the bus busy status. - // - if(HWREG(ui32Base + I2C_O_MCS) & I2C_MCS_BUSBSY) - { - return(true); - } - else - { - return(false); - } -} - -//***************************************************************************** -// -//! Controls the state of the I2C Master module. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32Cmd command to be issued to the I2C Master module. -//! -//! This function is used to control the state of the Master module send and -//! receive operations. The \e ui8Cmd parameter can be one of the following -//! values: -//! -//! - \b I2C_MASTER_CMD_SINGLE_SEND -//! - \b I2C_MASTER_CMD_SINGLE_RECEIVE -//! - \b I2C_MASTER_CMD_BURST_SEND_START -//! - \b I2C_MASTER_CMD_BURST_SEND_CONT -//! - \b I2C_MASTER_CMD_BURST_SEND_FINISH -//! - \b I2C_MASTER_CMD_BURST_SEND_ERROR_STOP -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_START -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_CONT -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_FINISH -//! - \b I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP -//! - \b I2C_MASTER_CMD_QUICK_COMMAND -//! - \b I2C_MASTER_CMD_HS_MASTER_CODE_SEND -//! - \b I2C_MASTER_CMD_FIFO_SINGLE_SEND -//! - \b I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_START -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_CONT -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH -//! - \b I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH -//! - \b I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - ASSERT((ui32Cmd == I2C_MASTER_CMD_SINGLE_SEND) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_START) || - (ui32Cmd == I2C_MASTER_CMD_SINGLE_RECEIVE) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_CONT) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_BURST_SEND_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_START) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_CONT) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_QUICK_COMMAND) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_SEND) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_START) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_CONT) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH) || - (ui32Cmd == I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP) || - (ui32Cmd == I2C_MASTER_CMD_HS_MASTER_CODE_SEND)); - - // - // Send the command. - // - HWREG(ui32Base + I2C_O_MCS) = ui32Cmd; -} - -//***************************************************************************** -// -//! Gets the error status of the I2C Master module. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function is used to obtain the error status of the Master module send -//! and receive operations. -//! -//! \return Returns the error status, as one of \b I2C_MASTER_ERR_NONE, -//! \b I2C_MASTER_ERR_ADDR_ACK, \b I2C_MASTER_ERR_DATA_ACK, or -//! \b I2C_MASTER_ERR_ARB_LOST. -// -//***************************************************************************** -uint32_t -I2CMasterErr(uint32_t ui32Base) -{ - uint32_t ui32Err; - - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Get the raw error state - // - ui32Err = HWREG(ui32Base + I2C_O_MCS); - - // - // If the I2C master is busy, then all the other bit are invalid, and - // don't have an error to report. - // - if(ui32Err & I2C_MCS_BUSY) - { - return(I2C_MASTER_ERR_NONE); - } - - // - // Check for errors. - // - if(ui32Err & (I2C_MCS_ERROR | I2C_MCS_ARBLST)) - { - return(ui32Err & (I2C_MCS_ARBLST | I2C_MCS_ACK | I2C_MCS_ADRACK)); - } - else - { - return(I2C_MASTER_ERR_NONE); - } -} - -//***************************************************************************** -// -//! Transmits a byte from the I2C Master. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui8Data data to be transmitted from the I2C Master. -//! -//! This function places the supplied data into I2C Master Data Register. -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the byte. - // - HWREG(ui32Base + I2C_O_MDR) = ui8Data; -} - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Master. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function reads a byte of data from the I2C Master Data Register. -//! -//! \return Returns the byte received from by the I2C Master, cast as an -//! uint32_t. -// -//***************************************************************************** -uint32_t -I2CMasterDataGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Read a byte. - // - return(HWREG(ui32Base + I2C_O_MDR)); -} - -//***************************************************************************** -// -//! Sets the Master clock timeout value. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32Value is the number of I2C clocks before the timeout is -//! asserted. -//! -//! This function enables and configures the clock low timeout feature in the -//! I2C peripheral. This feature is implemented as a 12-bit counter, with the -//! upper 8-bits being programmable. For example, to program a timeout of 20ms -//! with a 100kHz SCL frequency, \e ui32Value would be 0x7d. -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the timeout value. - // - HWREG(ui32Base + I2C_O_MCLKOCNT) = ui32Value; -} - -//***************************************************************************** -// -//! Configures ACK override behavior of the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param bEnable enables or disables ACK override. -//! -//! This function enables or disables ACK override, allowing the user -//! application to drive the value on SDA during the ACK cycle. -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable or disable based on bEnable. - // - if(bEnable) - { - HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOEN; - } - else - { - HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOEN; - } -} - -//***************************************************************************** -// -//! Writes the ACK value. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param bACK chooses whether to ACK (true) or NACK (false) the transfer. -//! -//! This function puts the desired ACK value on SDA during the ACK cycle. The -//! value written is only valid when ACK override is enabled using -//! I2CSlaveACKOverride(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // ACK or NACK based on the value of bACK. - // - if(bACK) - { - HWREG(ui32Base + I2C_O_SACKCTL) &= ~I2C_SACKCTL_ACKOVAL; - } - else - { - HWREG(ui32Base + I2C_O_SACKCTL) |= I2C_SACKCTL_ACKOVAL; - } -} - -//***************************************************************************** -// -//! Gets the I2C Slave module status -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This function returns the action requested from a master, if any. -//! Possible values are: -//! -//! - \b I2C_SLAVE_ACT_NONE -//! - \b I2C_SLAVE_ACT_RREQ -//! - \b I2C_SLAVE_ACT_TREQ -//! - \b I2C_SLAVE_ACT_RREQ_FBR -//! - \b I2C_SLAVE_ACT_OWN2SEL -//! - \b I2C_SLAVE_ACT_QCMD -//! - \b I2C_SLAVE_ACT_QCMD_DATA -//! -//! \note Not all devices support the second I2C slave's own address -//! or the quick command function. Please consult the device data sheet to -//! determine if these features are supported. -//! -//! \return Returns \b I2C_SLAVE_ACT_NONE to indicate that no action has been -//! requested of the I2C Slave module, \b I2C_SLAVE_ACT_RREQ to indicate that -//! an I2C master has sent data to the I2C Slave module, \b I2C_SLAVE_ACT_TREQ -//! to indicate that an I2C master has requested that the I2C Slave module send -//! data, \b I2C_SLAVE_ACT_RREQ_FBR to indicate that an I2C master has sent -//! data to the I2C slave and the first byte following the slave's own address -//! has been received, \b I2C_SLAVE_ACT_OWN2SEL to indicate that the second I2C -//! slave address was matched, \b I2C_SLAVE_ACT_QCMD to indicate that a quick -//! command was received, and \b I2C_SLAVE_ACT_QCMD_DATA to indicate that the -//! data bit was set when the quick command was received. -// -//***************************************************************************** -uint32_t -I2CSlaveStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the slave status. - // - return(HWREG(ui32Base + I2C_O_SCSR)); -} - -//***************************************************************************** -// -//! Transmits a byte from the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui8Data is the data to be transmitted from the I2C Slave -//! -//! This function places the supplied data into I2C Slave Data Register. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Write the byte. - // - HWREG(ui32Base + I2C_O_SDR) = ui8Data; -} - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Slave. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This function reads a byte of data from the I2C Slave Data Register. -//! -//! \return Returns the byte received from by the I2C Slave, cast as an -//! uint32_t. -// -//***************************************************************************** -uint32_t -I2CSlaveDataGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Read a byte. - // - return(HWREG(ui32Base + I2C_O_SDR)); -} - -//***************************************************************************** -// -//! Configures the I2C transmit (TX) FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! \param ui32Config is the configuration of the FIFO using specified macros. -//! -//! This configures the I2C peripheral's transmit FIFO. The transmit FIFO can -//! be used by the master or slave, but not both. The following macros are -//! used to configure the TX FIFO behavior for master or slave, with or without -//! DMA: -//! -//! \b I2C_FIFO_CFG_TX_MASTER, \b I2C_FIFO_CFG_TX_SLAVE, -//! \b I2C_FIFO_CFG_TX_MASTER_DMA, \b I2C_FIFO_CFG_TX_SLAVE_DMA -//! -//! To select the trigger level, one of the following macros should be used: -//! -//! \b I2C_FIFO_CFG_TX_TRIG_1, \b I2C_FIFO_CFG_TX_TRIG_2, -//! \b I2C_FIFO_CFG_TX_TRIG_3, \b I2C_FIFO_CFG_TX_TRIG_4, -//! \b I2C_FIFO_CFG_TX_TRIG_5, \b I2C_FIFO_CFG_TX_TRIG_6, -//! \b I2C_FIFO_CFG_TX_TRIG_7, \b I2C_FIFO_CFG_TX_TRIG_8 -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear transmit configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) &= 0xffff0000; - - // - // Store new transmit configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; -} - -//***************************************************************************** -// -//! Flushes the transmit (TX) FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! -//! This function flushes the I2C transmit FIFO. -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CTxFIFOFlush(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Flush the TX FIFO. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_TXFLUSH; -} - -//***************************************************************************** -// -//! Configures the I2C receive (RX) FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! \param ui32Config is the configuration of the FIFO using specified macros. -//! -//! This configures the I2C peripheral's receive FIFO. The receive FIFO can be -//! used by the master or slave, but not both. The following macros are used -//! to configure the RX FIFO behavior for master or slave, with or without DMA: -//! -//! \b I2C_FIFO_CFG_RX_MASTER, \b I2C_FIFO_CFG_RX_SLAVE, -//! \b I2C_FIFO_CFG_RX_MASTER_DMA, \b I2C_FIFO_CFG_RX_SLAVE_DMA -//! -//! To select the trigger level, one of the following macros should be used: -//! -//! \b I2C_FIFO_CFG_RX_TRIG_1, \b I2C_FIFO_CFG_RX_TRIG_2, -//! \b I2C_FIFO_CFG_RX_TRIG_3, \b I2C_FIFO_CFG_RX_TRIG_4, -//! \b I2C_FIFO_CFG_RX_TRIG_5, \b I2C_FIFO_CFG_RX_TRIG_6, -//! \b I2C_FIFO_CFG_RX_TRIG_7, \b I2C_FIFO_CFG_RX_TRIG_8 -//! -//! -//! \return None. -// -//***************************************************************************** -void -I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Clear receive configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) &= 0x0000ffff; - - // - // Store new receive configuration data. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= ui32Config; -} - -//***************************************************************************** -// -//! Flushes the receive (RX) FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! -//! This function flushes the I2C receive FIFO. -//! -//! \return None. -// -//***************************************************************************** -void -I2CRxFIFOFlush(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Flush the TX FIFO. - // - HWREG(ui32Base + I2C_O_FIFOCTL) |= I2C_FIFOCTL_RXFLUSH; -} - -//***************************************************************************** -// -//! Gets the current FIFO status. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! -//! This function retrieves the status for both the transmit (TX) and receive -//! (RX) FIFOs. The trigger level for the transmit FIFO is set using -//! I2CTxFIFOConfigSet() and for the receive FIFO using I2CTxFIFOConfigSet(). -//! -//! \return Returns the FIFO status, enumerated as a bit field containing -//! \b I2C_FIFO_RX_BELOW_TRIG_LEVEL, \b I2C_FIFO_RX_FULL, \b I2C_FIFO_RX_EMPTY, -//! \b I2C_FIFO_TX_BELOW_TRIG_LEVEL, \b I2C_FIFO_TX_FULL, and -//! \b I2C_FIFO_TX_EMPTY. -// -//***************************************************************************** -uint32_t -I2CFIFOStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Return the contents of the FIFO status register. - // - return(HWREG(ui32Base + I2C_O_FIFOSTATUS)); -} - -//***************************************************************************** -// -//! Writes a data byte to the I2C transmit FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! \param ui8Data is the data to be placed into the transmit FIFO. -//! -//! This function adds a byte of data to the I2C transmit FIFO. If there is -//! no space available in the FIFO, this function waits for space to become -//! available before returning. -//! -//! \return None. -// -//***************************************************************************** -void -I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Wait until there is space. - // - while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) - { - } - - // - // Place data into the FIFO. - // - HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; -} - -//***************************************************************************** -// -//! Writes a data byte to the I2C transmit FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! \param ui8Data is the data to be placed into the transmit FIFO. -//! -//! This function adds a byte of data to the I2C transmit FIFO. If there is -//! no space available in the FIFO, this function returns a zero. -//! -//! \return The number of elements added to the I2C transmit FIFO. -// -//***************************************************************************** -uint32_t -I2CFIFODataPutNonBlocking(uint32_t ui32Base, uint8_t ui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // If FIFO is full, return zero. - // - if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_TXFF) - { - return(0); - } - else - { - HWREG(ui32Base + I2C_O_FIFODATA) = ui8Data; - return(1); - } -} - -//***************************************************************************** -// -//! Reads a byte from the I2C receive FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! -//! This function reads a byte of data from I2C receive FIFO and places it in -//! the location specified by the \e pui8Data parameter. If there is no data -//! available, this function waits until data is received before returning. -//! -//! \return The data byte. -// -//***************************************************************************** -uint32_t -I2CFIFODataGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Wait until there is data to read. - // - while(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) - { - } - - // - // Read a byte. - // - return(HWREG(ui32Base + I2C_O_FIFODATA)); -} - -//***************************************************************************** -// -//! Reads a byte from the I2C receive FIFO. -//! -//! \param ui32Base is the base address of the I2C Master or Slave module. -//! \param pui8Data is a pointer where the read data is stored. -//! -//! This function reads a byte of data from I2C receive FIFO and places it in -//! the location specified by the \e pui8Data parameter. If there is no data -//! available, this functions returns 0. -//! -//! \return The number of elements read from the I2C receive FIFO. -// -//***************************************************************************** -uint32_t -I2CFIFODataGetNonBlocking(uint32_t ui32Base, uint8_t *pui8Data) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // If nothing in the FIFO, return zero. - // - if(HWREG(ui32Base + I2C_O_FIFOSTATUS) & I2C_FIFOSTATUS_RXFE) - { - return(0); - } - else - { - *pui8Data = HWREG(ui32Base + I2C_O_FIFODATA); - return(1); - } -} - -//***************************************************************************** -// -//! Set the burst length for a I2C master FIFO operation. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui8Length is the length of the burst transfer. -//! -//! This function configures the burst length for a I2C Master FIFO operation. -//! The burst field is limited to 8 bits or 256 bytes. The burst length -//! applies to a single I2CMCS BURST operation meaning that it specifies the -//! burst length for only the current operation (can be TX or RX). Each burst -//! operation must configure the burst length prior to writing the BURST bit -//! in the I2CMCS using I2CMasterControl(). -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterBurstLengthSet(uint32_t ui32Base, uint8_t ui8Length) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base) && (ui8Length < 255)); - - // - // Set the burst length. - // - HWREG(ui32Base + I2C_O_MBLEN) = ui8Length; -} - -//***************************************************************************** -// -//! Returns the current value of the burst transfer counter. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! -//! This function returns the current value of the burst transfer counter that -//! is used by the FIFO mechanism. Software can use this value to determine -//! how many bytes remain in a transfer, or where in the transfer the burst -//! operation was if an error has occurred. -//! -//! \return None. -// -//***************************************************************************** -uint32_t -I2CMasterBurstCountGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Get burst count. - // - return(HWREG(ui32Base + I2C_O_MBCNT)); -} - -//***************************************************************************** -// -//! Configures the I2C Master glitch filter. -//! -//! \param ui32Base is the base address of the I2C Master module. -//! \param ui32Config is the glitch filter configuration. -//! -//! This function configures the I2C Master glitch filter. The value passed in -//! to \e ui32Config determines the sampling range of the glitch filter, which -//! is configurable between 1 and 32 system clock cycles. The default -//! configuration of the glitch filter is 0 system clock cycles, which means -//! that it's disabled. -//! -//! The \e ui32Config field should be any of the following values: -//! -//! - \b I2C_MASTER_GLITCH_FILTER_DISABLED -//! - \b I2C_MASTER_GLITCH_FILTER_1 -//! - \b I2C_MASTER_GLITCH_FILTER_2 -//! - \b I2C_MASTER_GLITCH_FILTER_3 -//! - \b I2C_MASTER_GLITCH_FILTER_4 -//! - \b I2C_MASTER_GLITCH_FILTER_8 -//! - \b I2C_MASTER_GLITCH_FILTER_16 -//! - \b I2C_MASTER_GLITCH_FILTER_32 -//! -//! \return None. -// -//***************************************************************************** -void -I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Configure the glitch filter field of MTPR. - // - HWREG(ui32Base + I2C_O_MTPR) |= ui32Config; -} - -//***************************************************************************** -// -//! Enables FIFO usage for the I2C Slave module. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! \param ui32Config is the desired FIFO configuration of the I2C Slave. -//! -//! This function configures the I2C Slave module to use the FIFO(s). This -//! function should be used in combination with I2CTxFIFOConfigSet() and/or -//! I2CRxFIFOConfigSet(), which configure the FIFO trigger level and tell -//! the FIFO hardware whether to interact with the I2C Master or Slave. The -//! application appropriate combination of \b I2C_SLAVE_TX_FIFO_ENABLE and -//! \b I2C_SLAVE_RX_FIFO_ENABLE should be passed in to the \e ui32Config -//! field. -//! -//! The Slave I2CSCSR register is write-only, so any call to I2CSlaveEnable(), -//! I2CSlaveDisable or I2CSlaveFIFOEnable() overwrites the slave configuration. -//! Therefore, application software should call I2CSlaveEnable() followed by -//! I2CSlaveFIFOEnable() with the desired FIFO configuration. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Enable the FIFOs for the slave. - // - HWREG(ui32Base + I2C_O_SCSR) = ui32Config | I2C_SCSR_DA; -} - -//***************************************************************************** -// -//! Disable FIFO usage for the I2C Slave module. -//! -//! \param ui32Base is the base address of the I2C Slave module. -//! -//! This function disables the FIFOs for the I2C Slave. After calling this -//! this function, the FIFOs are disabled, but the Slave remains active. -//! -//! \return None. -// -//***************************************************************************** -void -I2CSlaveFIFODisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(_I2CBaseValid(ui32Base)); - - // - // Disable slave FIFOs. - // - HWREG(ui32Base + I2C_O_SCSR) = I2C_SCSR_DA; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2c.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2c.h deleted file mode 100644 index bd4ee41cc28..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2c.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// i2c.h -// -// Prototypes for the I2C Driver. -// -//***************************************************************************** - -#ifndef __DRIVERLIB_I2C_H__ -#define __DRIVERLIB_I2C_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Defines for the API. -// -//***************************************************************************** - -//***************************************************************************** -// -// Interrupt defines. -// -//***************************************************************************** -#define I2C_INT_MASTER 0x00000001 -#define I2C_INT_SLAVE 0x00000002 - -//***************************************************************************** -// -// I2C Master commands. -// -//***************************************************************************** -#define I2C_MASTER_CMD_SINGLE_SEND \ - 0x00000007 -#define I2C_MASTER_CMD_SINGLE_RECEIVE \ - 0x00000007 -#define I2C_MASTER_CMD_BURST_SEND_START \ - 0x00000003 -#define I2C_MASTER_CMD_BURST_SEND_CONT \ - 0x00000001 -#define I2C_MASTER_CMD_BURST_SEND_FINISH \ - 0x00000005 -#define I2C_MASTER_CMD_BURST_SEND_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_BURST_RECEIVE_START \ - 0x0000000b -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT \ - 0x00000009 -#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH \ - 0x00000005 -#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_QUICK_COMMAND \ - 0x00000027 -#define I2C_MASTER_CMD_HS_MASTER_CODE_SEND \ - 0x00000013 -#define I2C_MASTER_CMD_FIFO_SINGLE_SEND \ - 0x00000046 -#define I2C_MASTER_CMD_FIFO_SINGLE_RECEIVE \ - 0x00000046 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_START \ - 0x00000042 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_CONT \ - 0x00000040 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_FINISH \ - 0x00000044 -#define I2C_MASTER_CMD_FIFO_BURST_SEND_ERROR_STOP \ - 0x00000004 -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_START \ - 0x0000004a -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_CONT \ - 0x00000048 -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_FINISH \ - 0x00000044 -#define I2C_MASTER_CMD_FIFO_BURST_RECEIVE_ERROR_STOP \ - 0x00000004 - -//***************************************************************************** -// -// I2C Master glitch filter configuration. -// -//***************************************************************************** -#define I2C_MASTER_GLITCH_FILTER_DISABLED \ - 0 -#define I2C_MASTER_GLITCH_FILTER_1 \ - 0x00010000 -#define I2C_MASTER_GLITCH_FILTER_2 \ - 0x00020000 -#define I2C_MASTER_GLITCH_FILTER_3 \ - 0x00030000 -#define I2C_MASTER_GLITCH_FILTER_4 \ - 0x00040000 -#define I2C_MASTER_GLITCH_FILTER_8 \ - 0x00050000 -#define I2C_MASTER_GLITCH_FILTER_16 \ - 0x00060000 -#define I2C_MASTER_GLITCH_FILTER_32 \ - 0x00070000 - -//***************************************************************************** -// -// I2C Master error status. -// -//***************************************************************************** -#define I2C_MASTER_ERR_NONE 0 -#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 -#define I2C_MASTER_ERR_DATA_ACK 0x00000008 -#define I2C_MASTER_ERR_ARB_LOST 0x00000010 -#define I2C_MASTER_ERR_CLK_TOUT 0x00000080 - -//***************************************************************************** -// -// I2C Slave action requests -// -//***************************************************************************** -#define I2C_SLAVE_ACT_NONE 0 -#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data -#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data -#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte -#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave -#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command -#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value - -//***************************************************************************** -// -// Miscellaneous I2C driver definitions. -// -//***************************************************************************** -#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries - -//***************************************************************************** -// -// I2C Master interrupts. -// -//***************************************************************************** -#define I2C_MASTER_INT_RX_FIFO_FULL \ - 0x00000800 // RX FIFO Full Interrupt -#define I2C_MASTER_INT_TX_FIFO_EMPTY \ - 0x00000400 // TX FIFO Empty Interrupt -#define I2C_MASTER_INT_RX_FIFO_REQ \ - 0x00000200 // RX FIFO Request Interrupt -#define I2C_MASTER_INT_TX_FIFO_REQ \ - 0x00000100 // TX FIFO Request Interrupt -#define I2C_MASTER_INT_ARB_LOST \ - 0x00000080 // Arb Lost Interrupt -#define I2C_MASTER_INT_STOP 0x00000040 // Stop Condition Interrupt -#define I2C_MASTER_INT_START 0x00000020 // Start Condition Interrupt -#define I2C_MASTER_INT_NACK 0x00000010 // Addr/Data NACK Interrupt -#define I2C_MASTER_INT_TX_DMA_DONE \ - 0x00000008 // TX DMA Complete Interrupt -#define I2C_MASTER_INT_RX_DMA_DONE \ - 0x00000004 // RX DMA Complete Interrupt -#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt -#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt - -//***************************************************************************** -// -// I2C Slave interrupts. -// -//***************************************************************************** -#define I2C_SLAVE_INT_RX_FIFO_FULL \ - 0x00000100 // RX FIFO Full Interrupt -#define I2C_SLAVE_INT_TX_FIFO_EMPTY \ - 0x00000080 // TX FIFO Empty Interrupt -#define I2C_SLAVE_INT_RX_FIFO_REQ \ - 0x00000040 // RX FIFO Request Interrupt -#define I2C_SLAVE_INT_TX_FIFO_REQ \ - 0x00000020 // TX FIFO Request Interrupt -#define I2C_SLAVE_INT_TX_DMA_DONE \ - 0x00000010 // TX DMA Complete Interrupt -#define I2C_SLAVE_INT_RX_DMA_DONE \ - 0x00000008 // RX DMA Complete Interrupt -#define I2C_SLAVE_INT_STOP 0x00000004 // Stop Condition Interrupt -#define I2C_SLAVE_INT_START 0x00000002 // Start Condition Interrupt -#define I2C_SLAVE_INT_DATA 0x00000001 // Data Interrupt - -//***************************************************************************** -// -// I2C Slave FIFO configuration macros. -// -//***************************************************************************** -#define I2C_SLAVE_TX_FIFO_ENABLE \ - 0x00000002 -#define I2C_SLAVE_RX_FIFO_ENABLE \ - 0x00000004 - -//***************************************************************************** -// -// I2C FIFO configuration macros. -// -//***************************************************************************** -#define I2C_FIFO_CFG_TX_MASTER 0x00000000 -#define I2C_FIFO_CFG_TX_SLAVE 0x00008000 -#define I2C_FIFO_CFG_RX_MASTER 0x00000000 -#define I2C_FIFO_CFG_RX_SLAVE 0x80000000 -#define I2C_FIFO_CFG_TX_MASTER_DMA \ - 0x00002000 -#define I2C_FIFO_CFG_TX_SLAVE_DMA \ - 0x0000a000 -#define I2C_FIFO_CFG_RX_MASTER_DMA \ - 0x20000000 -#define I2C_FIFO_CFG_RX_SLAVE_DMA \ - 0xa0000000 -#define I2C_FIFO_CFG_TX_NO_TRIG 0x00000000 -#define I2C_FIFO_CFG_TX_TRIG_1 0x00000001 -#define I2C_FIFO_CFG_TX_TRIG_2 0x00000002 -#define I2C_FIFO_CFG_TX_TRIG_3 0x00000003 -#define I2C_FIFO_CFG_TX_TRIG_4 0x00000004 -#define I2C_FIFO_CFG_TX_TRIG_5 0x00000005 -#define I2C_FIFO_CFG_TX_TRIG_6 0x00000006 -#define I2C_FIFO_CFG_TX_TRIG_7 0x00000007 -#define I2C_FIFO_CFG_TX_TRIG_8 0x00000008 -#define I2C_FIFO_CFG_RX_NO_TRIG 0x00000000 -#define I2C_FIFO_CFG_RX_TRIG_1 0x00010000 -#define I2C_FIFO_CFG_RX_TRIG_2 0x00020000 -#define I2C_FIFO_CFG_RX_TRIG_3 0x00030000 -#define I2C_FIFO_CFG_RX_TRIG_4 0x00040000 -#define I2C_FIFO_CFG_RX_TRIG_5 0x00050000 -#define I2C_FIFO_CFG_RX_TRIG_6 0x00060000 -#define I2C_FIFO_CFG_RX_TRIG_7 0x00070000 -#define I2C_FIFO_CFG_RX_TRIG_8 0x00080000 - -//***************************************************************************** -// -// I2C FIFO status. -// -//***************************************************************************** -#define I2C_FIFO_RX_BELOW_TRIG_LEVEL \ - 0x00040000 -#define I2C_FIFO_RX_FULL 0x00020000 -#define I2C_FIFO_RX_EMPTY 0x00010000 -#define I2C_FIFO_TX_BELOW_TRIG_LEVEL \ - 0x00000004 -#define I2C_FIFO_TX_FULL 0x00000002 -#define I2C_FIFO_TX_EMPTY 0x00000001 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void I2CIntRegister(uint32_t ui32Base, void(pfnHandler)(void)); -extern void I2CIntUnregister(uint32_t ui32Base); -extern void I2CTxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void I2CTxFIFOFlush(uint32_t ui32Base); -extern void I2CRxFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Config); -extern void I2CRxFIFOFlush(uint32_t ui32Base); -extern uint32_t I2CFIFOStatus(uint32_t ui32Base); -extern void I2CFIFODataPut(uint32_t ui32Base, uint8_t ui8Data); -extern uint32_t I2CFIFODataPutNonBlocking(uint32_t ui32Base, - uint8_t ui8Data); -extern uint32_t I2CFIFODataGet(uint32_t ui32Base); -extern uint32_t I2CFIFODataGetNonBlocking(uint32_t ui32Base, - uint8_t *pui8Data); -extern void I2CMasterBurstLengthSet(uint32_t ui32Base, - uint8_t ui8Length); -extern uint32_t I2CMasterBurstCountGet(uint32_t ui32Base); -extern void I2CMasterGlitchFilterConfigSet(uint32_t ui32Base, - uint32_t ui32Config); -extern void I2CSlaveFIFOEnable(uint32_t ui32Base, uint32_t ui32Config); -extern void I2CSlaveFIFODisable(uint32_t ui32Base); -extern bool I2CMasterBusBusy(uint32_t ui32Base); -extern bool I2CMasterBusy(uint32_t ui32Base); -extern void I2CMasterControl(uint32_t ui32Base, uint32_t ui32Cmd); -extern uint32_t I2CMasterDataGet(uint32_t ui32Base); -extern void I2CMasterDataPut(uint32_t ui32Base, uint8_t ui8Data); -extern void I2CMasterDisable(uint32_t ui32Base); -extern void I2CMasterEnable(uint32_t ui32Base); -extern uint32_t I2CMasterErr(uint32_t ui32Base); -extern void I2CMasterInitExpClk(uint32_t ui32Base, uint32_t ui32I2CClk, - bool bFast); -extern void I2CMasterIntClear(uint32_t ui32Base); -extern void I2CMasterIntDisable(uint32_t ui32Base); -extern void I2CMasterIntEnable(uint32_t ui32Base); -extern bool I2CMasterIntStatus(uint32_t ui32Base, bool bMasked); -extern void I2CMasterIntEnableEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern void I2CMasterIntDisableEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern uint32_t I2CMasterIntStatusEx(uint32_t ui32Base, - bool bMasked); -extern void I2CMasterIntClearEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern void I2CMasterTimeoutSet(uint32_t ui32Base, uint32_t ui32Value); -extern void I2CSlaveACKOverride(uint32_t ui32Base, bool bEnable); -extern void I2CSlaveACKValueSet(uint32_t ui32Base, bool bACK); -extern uint32_t I2CMasterLineStateGet(uint32_t ui32Base); -extern void I2CMasterSlaveAddrSet(uint32_t ui32Base, - uint8_t ui8SlaveAddr, - bool bReceive); -extern uint32_t I2CSlaveDataGet(uint32_t ui32Base); -extern void I2CSlaveDataPut(uint32_t ui32Base, uint8_t ui8Data); -extern void I2CSlaveDisable(uint32_t ui32Base); -extern void I2CSlaveEnable(uint32_t ui32Base); -extern void I2CSlaveInit(uint32_t ui32Base, uint8_t ui8SlaveAddr); -extern void I2CSlaveAddressSet(uint32_t ui32Base, uint8_t ui8AddrNum, - uint8_t ui8SlaveAddr); -extern void I2CSlaveIntClear(uint32_t ui32Base); -extern void I2CSlaveIntDisable(uint32_t ui32Base); -extern void I2CSlaveIntEnable(uint32_t ui32Base); -extern void I2CSlaveIntClearEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void I2CSlaveIntDisableEx(uint32_t ui32Base, - uint32_t ui32IntFlags); -extern void I2CSlaveIntEnableEx(uint32_t ui32Base, uint32_t ui32IntFlags); -extern bool I2CSlaveIntStatus(uint32_t ui32Base, bool bMasked); -extern uint32_t I2CSlaveIntStatusEx(uint32_t ui32Base, - bool bMasked); -extern uint32_t I2CSlaveStatus(uint32_t ui32Base); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_I2C_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2s.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2s.c deleted file mode 100644 index 8f4c00a17d8..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2s.c +++ /dev/null @@ -1,1013 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// i2s.c -// -// Driver for the I2S interface. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup I2S_api -//! @{ -// -//***************************************************************************** -#include "inc/hw_types.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_mcasp.h" -#include "inc/hw_apps_config.h" -#include "interrupt.h" -#include "i2s.h" - -//***************************************************************************** -// Macros -//***************************************************************************** -#define MCASP_GBL_RCLK 0x00000001 -#define MCASP_GBL_RHCLK 0x00000002 -#define MCASP_GBL_RSER 0x00000004 -#define MCASP_GBL_RSM 0x00000008 -#define MCASP_GBL_RFSYNC 0x00000010 -#define MCASP_GBL_XCLK 0x00000100 -#define MCASP_GBL_XHCLK 0x00000200 -#define MCASP_GBL_XSER 0x00000400 -#define MCASP_GBL_XSM 0x00000800 -#define MCASP_GBL_XFSYNC 0x00001000 - - -//***************************************************************************** -// -//! \internal -//! Releases the specifed submodule out of reset. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulFlag is one of the valid sub module. -//! -//! This function Releases the specifed submodule out of reset. -//! -//! \return None. -// -//***************************************************************************** -static void I2SGBLEnable(unsigned long ulBase, unsigned long ulFlag) -{ - unsigned long ulReg; - - // - // Read global control register - // - ulReg = HWREG(ulBase + MCASP_O_GBLCTL); - - // - // Remove the sub modules reset as specified by ulFlag parameter - // - ulReg |= ulFlag; - - // - // Write the configuration - // - HWREG(ulBase + MCASP_O_GBLCTL) = ulReg; - - // - // Wait for write completeion - // - while(HWREG(ulBase + MCASP_O_GBLCTL) != ulReg) - { - - } - -} - -//***************************************************************************** -// -//! Enables transmit and/or receive. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulMode is one of the valid modes. -//! -//! This function enables the I2S module in specified mode. The parameter -//! \e ulMode should be one of the following -//! -//! -\b I2S_MODE_TX_ONLY -//! -\b I2S_MODE_TX_RX_SYNC -//! -//! \return None. -// -//***************************************************************************** -void I2SEnable(unsigned long ulBase, unsigned long ulMode) -{ - // - // FSYNC and Bit clock are output only in master mode - // - if( HWREG(ulBase + MCASP_O_ACLKXCTL) & 0x20) - { - // - // Set FSYNC anc BitClk as output - // - HWREG(ulBase + MCASP_O_PDIR) |= 0x14000000; - } - - - if(ulMode & 0x2) - { - // - // Remove Rx HCLK reset - // - I2SGBLEnable(ulBase, MCASP_GBL_RHCLK); - - // - // Remove Rx XCLK reset - // - I2SGBLEnable(ulBase, MCASP_GBL_RCLK); - - // - // Enable Rx SERDES(s) - // - I2SGBLEnable(ulBase, MCASP_GBL_RSER); - - // - // Enable Rx state machine - // - I2SGBLEnable(ulBase, MCASP_GBL_RSM); - - // - // Enable FSync generator - // - I2SGBLEnable(ulBase, MCASP_GBL_RFSYNC); - } - - - // - // Remove Tx HCLK reset - // - I2SGBLEnable(ulBase, MCASP_GBL_XHCLK); - - // - // Remove Tx XCLK reset - // - I2SGBLEnable(ulBase, MCASP_GBL_XCLK); - - - if(ulMode & 0x1) - { - // - // Enable Tx SERDES(s) - // - I2SGBLEnable(ulBase, MCASP_GBL_XSER); - - // - // Enable Tx state machine - // - I2SGBLEnable(ulBase, MCASP_GBL_XSM); - } - - // - // Enable FSync generator - // - I2SGBLEnable(ulBase, MCASP_GBL_XFSYNC); -} - -//***************************************************************************** -// -//! Disables transmit and/or receive. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function disables transmit and/or receive from I2S module. -//! -//! \return None. -// -//***************************************************************************** -void I2SDisable(unsigned long ulBase) -{ - // - // Reset all sub modules - // - HWREG(ulBase + MCASP_O_GBLCTL) = 0; - - // - // Wait for write to complete - // - while( HWREG(ulBase + MCASP_O_GBLCTL) != 0) - { - - } -} - -//***************************************************************************** -// -//! Waits to send data over the specified data line -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulDataLine is one of the valid data lines. -//! \param ulData is the data to be transmitted. -//! -//! This function sends the \e ucData to the transmit register for the -//! specified data line. If there is no space available, this -//! function waits until there is space available before returning. -//! -//! \return None. -// -//***************************************************************************** -void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine, - unsigned long ulData) -{ - // - // Compute register the offeset - // - ulDataLine = (ulDataLine-1) << 2; - - // - // Wait for free space in fifo - // - while(!( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA)) - { - - } - - // - // Write Data into the FIFO - // - HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData; -} - -//***************************************************************************** -// -//! Sends data over the specified data line -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulDataLine is one of the valid data lines. -//! \param ulData is the data to be transmitted. -//! -//! This function writes the \e ucData to the transmit register for -//! the specified data line. This function does not block, so if there is no -//! space available, then \b -1 is returned, and the application must retry the -//! function later. -//! -//! \return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -long I2SDataPutNonBlocking(unsigned long ulBase, unsigned long ulDataLine, - unsigned long ulData) -{ - - // - // Compute register the offeset - // - ulDataLine = (ulDataLine-1) << 2; - - // - // Send Data if fifo has free space - // - if( HWREG(ulBase + MCASP_O_TXSTAT) & MCASP_TXSTAT_XDATA) - { - // - // Write data into the FIFO - // - HWREG(ulBase + MCASP_O_TXBUF0 + ulDataLine) = ulData; - return 0; - } - - // - // FIFO is full - // - return(-1); -} - -//***************************************************************************** -// -//! Waits for data from the specified data line. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulDataLine is one of the valid data lines. -//! \param pulData is pointer to receive data variable. -//! -//! This function gets data from the receive register for the specified -//! data line. If there are no data available, this function waits until a -//! receive before returning. -//! -//! \return None. -// -//***************************************************************************** -void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine, - unsigned long *pulData) -{ - - // - // Compute register the offeset - // - ulDataLine = (ulDataLine-1) << 2; - - // - // Wait for atleat on word in FIFO - // - while(!(HWREG(ulBase + MCASP_O_RXSTAT) & MCASP_RXSTAT_RDATA)) - { - - } - - // - // Read the Data - // - *pulData = HWREG(ulBase + MCASP_O_RXBUF0 + ulDataLine); -} - - -//***************************************************************************** -// -//! Receives data from the specified data line. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulDataLine is one of the valid data lines. -//! \param pulData is pointer to receive data variable. -//! -//! This function gets data from the receive register for the specified -//! data line. -//! -//! -//! \return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -long I2SDataGetNonBlocking(unsigned long ulBase, unsigned long ulDataLine, - unsigned long *pulData) -{ - - // - // Compute register the offeset - // - ulDataLine = (ulDataLine-1) << 2; - - // - // Check if data is available in FIFO - // - if(HWREG(ulBase + MCASP_O_RXSTAT) & MCASP_RXSTAT_RDATA) - { - // - // Read the Data - // - *pulData = HWREG(ulBase + MCASP_O_RXBUF0 + ulDataLine); - return 0; - } - - // - // FIFO is empty - // - return -1; -} - - -//***************************************************************************** -// -//! Sets the configuration of the I2S module. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulI2SClk is the rate of the clock supplied to the I2S module. -//! \param ulBitClk is the desired bit rate. -//! \param ulConfig is the data format. -//! -//! This function configures the I2S for operation in the specified data -//! format. The bit rate is provided in the \e ulBitClk parameter and the data -//! format in the \e ulConfig parameter. -//! -//! The \e ulConfig parameter is the logical OR of three values: the slot size -//! the data read/write port select, Master or Slave mode -//! -//! Follwoing selects the Master-Slave mode -//! -\b I2S_MODE_MASTER -//! -\b I2S_MODE_SLAVE -//! -//! Following selects the slot size: -//! -\b I2S_SLOT_SIZE_24 -//! -\b I2S_SLOT_SIZE_16 -//! -//! Following selects the data read/write port: -//! -\b I2S_PORT_DMA -//! -\b I2S_PORT_CPU -//! -//! \return None. -// -//***************************************************************************** -void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk, - unsigned long ulBitClk, unsigned long ulConfig) -{ - unsigned long ulHClkDiv; - unsigned long ulClkDiv; - unsigned long ulSlotSize; - unsigned long ulBitMask; - - // - // Calculate clock dividers - // - ulHClkDiv = ((ulI2SClk/ulBitClk)-1); - ulClkDiv = 0; - - // - // Check if HCLK divider is overflowing - // - if(ulHClkDiv > 0xFFF) - { - ulHClkDiv = 0xFFF; - - // - // Calculate clock divider - // - ulClkDiv = ((ulI2SClk/(ulBitClk * (ulHClkDiv + 1))) & 0x1F); - } - - // - // - // - ulClkDiv = ((ulConfig & I2S_MODE_SLAVE )?0x80:0xA0|ulClkDiv); - - HWREG(ulBase + MCASP_O_ACLKXCTL) = ulClkDiv; - - HWREG(ulBase + MCASP_O_AHCLKXCTL) = (0x8000|ulHClkDiv); - - // - // Write the Tx format register - // - HWREG(ulBase + MCASP_O_TXFMT) = (0x18000 | (ulConfig & 0x7FFF)); - - // - // Write the Rx format register - // - HWREG(ulBase + MCASP_O_RXFMT) = (0x18000 | ((ulConfig >> 16) &0x7FFF)); - - // - // Check if in master mode - // - if( ulConfig & I2S_MODE_SLAVE) - { - // - // Configure Tx FSync generator in I2S mode - // - HWREG(ulBase + MCASP_O_TXFMCTL) = 0x111; - - // - // Configure Rx FSync generator in I2S mode - // - HWREG(ulBase + MCASP_O_RXFMCTL) = 0x111; - } - else - { - // - // Configure Tx FSync generator in I2S mode - // - HWREG(ulBase + MCASP_O_TXFMCTL) = 0x113; - - // - // Configure Rx FSync generator in I2S mode - // - HWREG(ulBase + MCASP_O_RXFMCTL) = 0x113; - } - - // - // Compute Slot Size - // - ulSlotSize = ((((ulConfig & 0xFF) >> 4) + 1) * 2); - - // - // Creat the bit mask - // - ulBitMask = (0xFFFFFFFF >> (32 - ulSlotSize)); - - // - // Set Tx bit valid mask - // - HWREG(ulBase + MCASP_O_TXMASK) = ulBitMask; - - // - // Set Rx bit valid mask - // - HWREG(ulBase + MCASP_O_RXMASK) = ulBitMask; - - // - // Set Tx slot valid mask - // - HWREG(ulBase + MCASP_O_TXTDM) = 0x3; - - // - // Set Rx slot valid mask - // - HWREG(ulBase + MCASP_O_RXTDM) = 0x3; -} - -//***************************************************************************** -// -//! Configure and enable transmit FIFO. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulTxLevel is the transmit FIFO DMA request level. -//! \param ulWordsPerTransfer is the nuber of words transferred from the FIFO. -//! -//! This function configures and enable I2S transmit FIFO. -//! -//! The parameter \e ulTxLevel sets the level at which transmit DMA requests -//! are generated. This should be non-zero integer multiple of number of -//! serializers enabled as transmitters -//! -//! The parameter \e ulWordsPerTransfer sets the number of words that are -//! transferred from the transmit FIFO to the data line(s). This value must -//! equal the number of serializers used as transmitters. -//! -//! \return None. -// -//***************************************************************************** -void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel, - unsigned long ulWordsPerTransfer) -{ - // - // Set transmit FIFO configuration and - // enable it - // - HWREG(ulBase + MCASP_0_WFIFOCTL) = ((1 <<16) | ((ulTxLevel & 0xFF) << 8) - | (ulWordsPerTransfer & 0x1F)); - -} - -//***************************************************************************** -// -//! Disables transmit FIFO. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function disables the I2S transmit FIFO. -//! -//! \return None. -// -//***************************************************************************** -void I2STxFIFODisable(unsigned long ulBase) -{ - // - // Disable transmit FIFO. - // - HWREG(ulBase + MCASP_0_WFIFOCTL) = 0; -} - -//***************************************************************************** -// -//! Configure and enable receive FIFO. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulRxLevel is the receive FIFO DMA request level. -//! \param ulWordsPerTransfer is the nuber of words transferred from the FIFO. -//! -//! This function configures and enable I2S receive FIFO. -//! -//! The parameter \e ulRxLevel sets the level at which receive DMA requests -//! are generated. This should be non-zero integer multiple of number of -//! serializers enabled as receivers. -//! -//! The parameter \e ulWordsPerTransfer sets the number of words that are -//! transferred to the receive FIFO from the data line(s). This value must -//! equal the number of serializers used as receivers. -//! -//! \return None. -// -//***************************************************************************** -void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel, - unsigned long ulWordsPerTransfer) -{ - // - // Set FIFO configuration - // - HWREG(ulBase + MCASP_0_RFIFOCTL) = ( (1 <<16) | ((ulRxLevel & 0xFF) << 8) - | (ulWordsPerTransfer & 0x1F)); - -} - -//***************************************************************************** -// -//! Disables receive FIFO. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function disables the I2S receive FIFO. -//! -//! \return None. -// -//***************************************************************************** -void I2SRxFIFODisable(unsigned long ulBase) -{ - // - // Disable receive FIFO. - // - HWREG(ulBase + MCASP_0_RFIFOCTL) = 0; -} - -//***************************************************************************** -// -//! Get the transmit FIFO status. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function gets the number of 32-bit words currently in the transmit -//! FIFO. -//! -//! \return Returns transmit FIFO status. -// -//***************************************************************************** -unsigned long I2STxFIFOStatusGet(unsigned long ulBase) -{ - // - // Return transmit FIFO level - // - return HWREG(ulBase + MCASP_0_WFIFOSTS); -} - -//***************************************************************************** -// -//! Get the receive FIFO status. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function gets the number of 32-bit words currently in the receive -//! FIFO. -//! -//! \return Returns receive FIFO status. -// -//***************************************************************************** -unsigned long I2SRxFIFOStatusGet(unsigned long ulBase) -{ - // - // Return receive FIFO level - // - return HWREG(ulBase + MCASP_0_RFIFOSTS); -} - -//***************************************************************************** -// -//! Configure the serializer in specified mode. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulDataLine is the data line (serilizer) to be configured. -//! \param ulSerMode is the required serializer mode. -//! \param ulInActState sets the inactive state of the data line. -//! -//! This function configure and enable the serializer associated with the given -//! data line in specified mode. -//! -//! The paramenter \e ulDataLine selects to data line to be configured and -//! can be one of the following: -//! -\b I2S_DATA_LINE_0 -//! -\b I2S_DATA_LINE_1 -//! -//! The parameter \e ulSerMode can be one of the following: -//! -\b I2S_SER_MODE_TX -//! -\b I2S_SER_MODE_RX -//! -\b I2S_SER_MODE_DISABLE -//! -//! The parameter \e ulInActState can be one of the following -//! -\b I2S_INACT_TRI_STATE -//! -\b I2S_INACT_LOW_LEVEL -//! -\b I2S_INACT_LOW_HIGH -//! -//! \return Returns receive FIFO status. -// -//***************************************************************************** -void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine, - unsigned long ulSerMode, unsigned long ulInActState) -{ - if( ulSerMode == I2S_SER_MODE_TX) - { - // - // Set the data line in output mode - // - HWREG(ulBase + MCASP_O_PDIR) |= ulDataLine; - } - else - { - // - // Set the data line in input mode - // - HWREG(ulBase + MCASP_O_PDIR) &= ~ulDataLine; - } - - // - // Set the serializer configuration. - // - HWREG(ulBase + MCASP_O_XRSRCTL0 + ((ulDataLine-1) << 2)) - = (ulSerMode | ulInActState); -} - -//***************************************************************************** -// -//! Enables individual I2S interrupt sources. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated I2S interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! -//! -\b I2S_INT_XUNDRN -//! -\b I2S_INT_XSYNCERR -//! -\b I2S_INT_XLAST -//! -\b I2S_INT_XDATA -//! -\b I2S_INT_XSTAFRM -//! -\b I2S_INT_XDMA -//! -\b I2S_INT_ROVRN -//! -\b I2S_INT_RSYNCERR -//! -\b I2S_INT_RLAST -//! -\b I2S_INT_RDATA -//! -\b I2S_INT_RSTAFRM -//! -\b I2S_INT_RDMA -//! -//! \return None. -// -//***************************************************************************** -void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - - // - // Enable DMA done interrupts - // - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR ) - |= ((ulIntFlags &0xC0000000) >> 20); - - // - // Enable specific Tx Interrupts - // - HWREG(ulBase + MCASP_O_EVTCTLX) |= (ulIntFlags & 0xFF); - - // - // Enable specific Rx Interrupts - // - HWREG(ulBase + MCASP_O_EVTCTLR) |= ((ulIntFlags >> 16) & 0xFF); -} - -//***************************************************************************** -// -//! Disables individual I2S interrupt sources. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated I2S interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to I2SIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Disable DMA done interrupts - // - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) - |= ((ulIntFlags &0xC0000000) >> 20); - - // - // Disable specific Tx Interrupts - // - HWREG(ulBase + MCASP_O_EVTCTLX) &= ~(ulIntFlags & 0xFF); - - // - // Disable specific Rx Interrupts - // - HWREG(ulBase + MCASP_O_EVTCTLR) &= ~((ulIntFlags >> 16) & 0xFF); -} - - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function returns the raw interrupt status for I2S enumerated -//! as a bit field of values: -//! -\b I2S_STS_XERR -//! -\b I2S_STS_XDMAERR -//! -\b I2S_STS_XSTAFRM -//! -\b I2S_STS_XDATA -//! -\b I2S_STS_XLAST -//! -\b I2S_STS_XSYNCERR -//! -\b I2S_STS_XUNDRN -//! -\b I2S_STS_XDMA -//! -\b I2S_STS_RERR -//! -\b I2S_STS_RDMAERR -//! -\b I2S_STS_RSTAFRM -//! -\b I2S_STS_RDATA -//! -\b I2S_STS_RLAST -//! -\b I2S_STS_RSYNCERR -//! -\b I2S_STS_ROVERN -//! -\b I2S_STS_RDMA -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described above. -// -//***************************************************************************** -unsigned long I2SIntStatus(unsigned long ulBase) -{ - unsigned long ulStatus; - - // - // Get DMA interrupt status - // - ulStatus = - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW) << 20; - - ulStatus &= 0xC0000000; - - // - // Read Tx Interrupt status - // - ulStatus |= HWREG(ulBase + MCASP_O_TXSTAT); - - // - // Read Rx Interrupt status - // - ulStatus |= HWREG(ulBase + MCASP_O_RXSTAT) << 16; - - // - // Return the status - // - return ulStatus; -} - -//***************************************************************************** -// -//! Clears I2S interrupt sources. -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulStatFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified I2S interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the value -//! describe in I2SIntStatus(). -//! -//! \return None. -// -//***************************************************************************** -void I2SIntClear(unsigned long ulBase, unsigned long ulStatFlags) -{ - // - // Clear DMA done interrupts - // - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) - |= ((ulStatFlags &0xC0000000) >> 20); - - // - // Clear Tx Interrupt - // - HWREG(ulBase + MCASP_O_TXSTAT) = ulStatFlags & 0x1FF ; - - // - // Clear Rx Interrupt - // - HWREG(ulBase + MCASP_O_RXSTAT) = (ulStatFlags >> 16) & 0x1FF; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a I2S interrupt. -//! -//! \param ulBase is the base address of the I2S module. -//! \param pfnHandler is a pointer to the function to be called when the -//! I2S interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; specific -//! I2S interrupts must be enabled via I2SIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler - // - IntRegister(INT_I2S,pfnHandler); - - // - // Enable the interrupt - // - IntEnable(INT_I2S); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a I2S interrupt. -//! -//! \param ulBase is the base address of the I2S module. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a I2S interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void I2SIntUnregister(unsigned long ulBase) -{ - // - // Disable interrupt - // - IntDisable(INT_I2S); - - // - // Unregister the handler - // - IntUnregister(INT_I2S); - -} - -//***************************************************************************** -// -//! Set the active slots for Trasmitter -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulActSlot is the bit-mask of activ slots -//! -//! This function sets the active slots for the transmitter. By default both -//! the slots are active. The parameter \e ulActSlot is logical OR follwoing -//! values: -//! -\b I2S_ACT_SLOT_EVEN -//! -\b I2S_ACT_SLOT_ODD -//! -//! \return None. -// -//***************************************************************************** -void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot) -{ - HWREG(ulBase + MCASP_O_TXTDM) = ulActSlot; -} - -//***************************************************************************** -// -//! Set the active slots for Receiver -//! -//! \param ulBase is the base address of the I2S module. -//! \param ulActSlot is the bit-mask of activ slots -//! -//! This function sets the active slots for the receiver. By default both -//! the slots are active. The parameter \e ulActSlot is logical OR follwoing -//! values: -//! -\b I2S_ACT_SLOT_EVEN -//! -\b I2S_ACT_SLOT_ODD -//! -//! \return None. -// -//***************************************************************************** -void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot) -{ - HWREG(ulBase + MCASP_O_RXTDM) = ulActSlot; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2s.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2s.h deleted file mode 100644 index 260308fe7e1..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/i2s.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// i2s.h -// -// Defines and Macros for the I2S. -// -//***************************************************************************** - -#ifndef __I2S_H__ -#define __I2S_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// I2S DMA ports. -// -//***************************************************************************** -#define I2S_TX_DMA_PORT 0x4401E200 -#define I2S_RX_DMA_PORT 0x4401E280 - -//***************************************************************************** -// -// Values that can be passed to I2SConfigSetExpClk() as the ulConfig parameter. -// -//***************************************************************************** -#define I2S_SLOT_SIZE_8 0x00300032 -#define I2S_SLOT_SIZE_16 0x00700074 -#define I2S_SLOT_SIZE_24 0x00B000B6 - - -#define I2S_PORT_CPU 0x00080008 -#define I2S_PORT_DMA 0x00000000 - -#define I2S_MODE_MASTER 0x00000000 -#define I2S_MODE_SLAVE 0x00008000 - -//***************************************************************************** -// -// Values that can be passed as ulDataLine parameter. -// -//***************************************************************************** -#define I2S_DATA_LINE_0 0x00000001 -#define I2S_DATA_LINE_1 0x00000002 - -//***************************************************************************** -// -// Values that can be passed to I2SSerializerConfig() as the ulSerMode -// parameter. -// -//***************************************************************************** -#define I2S_SER_MODE_TX 0x00000001 -#define I2S_SER_MODE_RX 0x00000002 -#define I2S_SER_MODE_DISABLE 0x00000000 - -//***************************************************************************** -// -// Values that can be passed to I2SSerializerConfig() as the ulInActState -// parameter. -// -//***************************************************************************** -#define I2S_INACT_TRI_STATE 0x00000000 -#define I2S_INACT_LOW_LEVEL 0x00000008 -#define I2S_INACT_HIGH_LEVEL 0x0000000C - -//***************************************************************************** -// -// Values that can be passed to I2SIntEnable() and I2SIntDisable() as the -// ulIntFlags parameter. -// -//***************************************************************************** -#define I2S_INT_XUNDRN 0x00000001 -#define I2S_INT_XSYNCERR 0x00000002 -#define I2S_INT_XLAST 0x00000010 -#define I2S_INT_XDATA 0x00000020 -#define I2S_INT_XSTAFRM 0x00000080 -#define I2S_INT_XDMA 0x80000000 -#define I2S_INT_ROVRN 0x00010000 -#define I2S_INT_RSYNCERR 0x00020000 -#define I2S_INT_RLAST 0x00100000 -#define I2S_INT_RDATA 0x00200000 -#define I2S_INT_RSTAFRM 0x00800000 -#define I2S_INT_RDMA 0x40000000 - - -//***************************************************************************** -// -// Values that can be passed to I2SRxActiveSlotSet() and I2STxActiveSlotSet -// -//***************************************************************************** -#define I2S_ACT_SLOT_EVEN 0x00000001 -#define I2S_ACT_SLOT_ODD 0x00000002 - -//***************************************************************************** -// -// Values that can be passed to I2SIntClear() as the -// ulIntFlags parameter and returned from I2SIntStatus(). -// -//***************************************************************************** -#define I2S_STS_XERR 0x00000100 -#define I2S_STS_XDMAERR 0x00000080 -#define I2S_STS_XSTAFRM 0x00000040 -#define I2S_STS_XDATA 0x00000020 -#define I2S_STS_XLAST 0x00000010 -#define I2S_STS_XSYNCERR 0x00000002 -#define I2S_STS_XUNDRN 0x00000001 -#define I2S_STS_XDMA 0x80000000 -#define I2S_STS_RERR 0x01000000 -#define I2S_STS_RDMAERR 0x00800000 -#define I2S_STS_RSTAFRM 0x00400000 -#define I2S_STS_RDATA 0x00200000 -#define I2S_STS_RLAST 0x00100000 -#define I2S_STS_RSYNCERR 0x00020000 -#define I2S_STS_ROVERN 0x00010000 -#define I2S_STS_RDMA 0x40000000 - -//***************************************************************************** -// -// Values that can be passed to I2SEnable() as the ulMode parameter. -// -//***************************************************************************** -#define I2S_MODE_TX_ONLY 0x00000001 -#define I2S_MODE_TX_RX_SYNC 0x00000003 - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void I2SEnable(unsigned long ulBase, unsigned long ulMode); -extern void I2SDisable(unsigned long ulBase); - -extern void I2SDataPut(unsigned long ulBase, unsigned long ulDataLine, - unsigned long ulData); -extern long I2SDataPutNonBlocking(unsigned long ulBase, - unsigned long ulDataLine, unsigned long ulData); - -extern void I2SDataGet(unsigned long ulBase, unsigned long ulDataLine, - unsigned long *pulData); -extern long I2SDataGetNonBlocking(unsigned long ulBase, - unsigned long ulDataLine, unsigned long *pulData); - -extern void I2SConfigSetExpClk(unsigned long ulBase, unsigned long ulI2SClk, - unsigned long ulBitClk, unsigned long ulConfig); - -extern void I2STxFIFOEnable(unsigned long ulBase, unsigned long ulTxLevel, - unsigned long ulWordsPerTransfer); -extern void I2STxFIFODisable(unsigned long ulBase); -extern void I2SRxFIFOEnable(unsigned long ulBase, unsigned long ulRxLevel, - unsigned long ulWordsPerTransfer); -extern void I2SRxFIFODisable(unsigned long ulBase); -extern unsigned long I2STxFIFOStatusGet(unsigned long ulBase); -extern unsigned long I2SRxFIFOStatusGet(unsigned long ulBase); - -extern void I2SSerializerConfig(unsigned long ulBase, unsigned long ulDataLine, - unsigned long ulSerMode, unsigned long ulInActState); - -extern void I2SIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void I2SIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long I2SIntStatus(unsigned long ulBase); -extern void I2SIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void I2SIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void I2SIntUnregister(unsigned long ulBase); -extern void I2STxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot); -extern void I2SRxActiveSlotSet(unsigned long ulBase, unsigned long ulActSlot); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif //__I2S_H__ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/interrupt.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/interrupt.c deleted file mode 100644 index a4a447129b0..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/interrupt.c +++ /dev/null @@ -1,770 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// interrupt.c -// -// Driver for the NVIC Interrupt Controller. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup interrupt_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_ints.h" -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "cpu.h" -#include "debug.h" -#include "interrupt.h" - -//***************************************************************************** -// -// This is a mapping between priority grouping encodings and the number of -// preemption priority bits. -// -//***************************************************************************** -static const unsigned long g_pulPriority[] = -{ - NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, - NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, NVIC_APINT_PRIGROUP_5_3, - NVIC_APINT_PRIGROUP_6_2, NVIC_APINT_PRIGROUP_7_1 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number and the register that contains -// the priority encoding for that interrupt. -// -//***************************************************************************** -static const unsigned long g_pulRegs[] = -{ - 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1, - NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7, - NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13, - NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19, - NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25, - NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31, - NVIC_PRI32, NVIC_PRI33, NVIC_PRI34, NVIC_PRI35, NVIC_PRI36, NVIC_PRI37, - NVIC_PRI38, NVIC_PRI39, NVIC_PRI40, NVIC_PRI41, NVIC_PRI42, NVIC_PRI43, - NVIC_PRI44, NVIC_PRI45, NVIC_PRI46, NVIC_PRI47, NVIC_PRI48 - -}; - - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt enable for that -// interrupt. -// -//***************************************************************************** -static const unsigned long g_pulEnRegs[] = -{ - NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4, NVIC_EN5 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt disable for that -// interrupt. -// -//***************************************************************************** -static const unsigned long g_pulDisRegs[] = -{ - NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4, NVIC_DIS5 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt pend for that interrupt. -// -//***************************************************************************** -static const unsigned long g_pulPendRegs[] = -{ - NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4, NVIC_PEND5 -}; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt unpend for that -// interrupt. -// -//***************************************************************************** -static const unsigned long g_pulUnpendRegs[] = -{ - NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4, - NVIC_UNPEND5 -}; - - -//***************************************************************************** -// -//! \internal -//! The default interrupt handler. -//! -//! This is the default interrupt handler for all interrupts. It simply loops -//! forever so that the system state is preserved for observation by a -//! debugger. Since interrupts should be disabled before unregistering the -//! corresponding handler, this should never be called. -//! -//! \return None. -// -//***************************************************************************** -static void -IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while(1) - { - } -} - -//***************************************************************************** -// -//! Enables the processor interrupt. -//! -//! Allows the processor to respond to interrupts. This does not affect the -//! set of interrupts enabled in the interrupt controller; it just gates the -//! single interrupt from the controller to the processor. -//! -//! \note Previously, this function had no return value. As such, it was -//! possible to include interrupt.h and call this function without -//! having included hw_types.h. Now that the return is a -//! tBoolean, a compiler error will occur in this case. The solution -//! is to include hw_types.h before including interrupt.h. -//! -//! \return Returns \b true if interrupts were disabled when the function was -//! called or \b false if they were initially enabled. -// -//***************************************************************************** -tBoolean -IntMasterEnable(void) -{ - // - // Enable processor interrupts. - // - return(CPUcpsie()); -} - -//***************************************************************************** -// -//! Disables the processor interrupt. -//! -//! Prevents the processor from receiving interrupts. This does not affect the -//! set of interrupts enabled in the interrupt controller; it just gates the -//! single interrupt from the controller to the processor. -//! -//! \note Previously, this function had no return value. As such, it was -//! possible to include interrupt.h and call this function without -//! having included hw_types.h. Now that the return is a -//! tBoolean, a compiler error will occur in this case. The solution -//! is to include hw_types.h before including interrupt.h. -//! -//! \return Returns \b true if interrupts were already disabled when the -//! function was called or \b false if they were initially enabled. -// -//***************************************************************************** -tBoolean -IntMasterDisable(void) -{ - // - // Disable processor interrupts. - // - return(CPUcpsid()); -} -//***************************************************************************** -// -//! Sets the NVIC VTable base. -//! -//! \param ulVtableBase specifies the new base address of VTable -//! -//! This function is used to specify a new base address for the VTable. -//! This function must be called before using IntRegister() for registering -//! any interrupt handler. -//! -//! -//! \return None. -// -//***************************************************************************** -void -IntVTableBaseSet(unsigned long ulVtableBase) -{ - HWREG(NVIC_VTABLE) = ulVtableBase; -} - -//***************************************************************************** -// -//! Registers a function to be called when an interrupt occurs. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! \param pfnHandler is a pointer to the function to be called. -//! -//! This function is used to specify the handler function to be called when the -//! given interrupt is asserted to the processor. When the interrupt occurs, -//! if it is enabled (via IntEnable()), the handler function will be called in -//! interrupt context. Since the handler function can preempt other code, care -//! must be taken to protect memory or peripherals that are accessed by the -//! handler and other non-handler code. -//! -//! -//! \return None. -// -//***************************************************************************** -void -IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)) -{ - unsigned long *ulNvicTbl; - - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE); - ulNvicTbl[ulInterrupt]= (unsigned long)pfnHandler; -} - -//***************************************************************************** -// -//! Unregisters the function to be called when an interrupt occurs. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! -//! This function is used to indicate that no handler should be called when the -//! given interrupt is asserted to the processor. The interrupt source will be -//! automatically disabled (via IntDisable()) if necessary. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -IntUnregister(unsigned long ulInterrupt) -{ - unsigned long *ulNvicTbl; - - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - ulNvicTbl = (unsigned long *)HWREG(NVIC_VTABLE); - ulNvicTbl[ulInterrupt]= (unsigned long)IntDefaultHandler; -} - -//***************************************************************************** -// -//! Sets the priority grouping of the interrupt controller. -//! -//! \param ulBits specifies the number of bits of preemptable priority. -//! -//! This function specifies the split between preemptable priority levels and -//! subpriority levels in the interrupt priority specification. The range of -//! the grouping values are dependent upon the hardware implementation; on -//! the CC3200 , three bits are available for hardware interrupt -//! prioritization and therefore priority grouping values of three through -//! seven have the same effect. -//! -//! \return None. -// -//***************************************************************************** -void -IntPriorityGroupingSet(unsigned long ulBits) -{ - // - // Check the arguments. - // - ASSERT(ulBits < NUM_PRIORITY); - - // - // Set the priority grouping. - // - HWREG(NVIC_APINT) = NVIC_APINT_VECTKEY | g_pulPriority[ulBits]; -} - -//***************************************************************************** -// -//! Gets the priority grouping of the interrupt controller. -//! -//! This function returns the split between preemptable priority levels and -//! subpriority levels in the interrupt priority specification. -//! -//! \return The number of bits of preemptable priority. -// -//***************************************************************************** -unsigned long -IntPriorityGroupingGet(void) -{ - unsigned long ulLoop, ulValue; - - // - // Read the priority grouping. - // - ulValue = HWREG(NVIC_APINT) & NVIC_APINT_PRIGROUP_M; - - // - // Loop through the priority grouping values. - // - for(ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++) - { - // - // Stop looping if this value matches. - // - if(ulValue == g_pulPriority[ulLoop]) - { - break; - } - } - - // - // Return the number of priority bits. - // - return(ulLoop); -} - -//***************************************************************************** -// -//! Sets the priority of an interrupt. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! \param ucPriority specifies the priority of the interrupt. -//! -//! This function is used to set the priority of an interrupt. When multiple -//! interrupts are asserted simultaneously, the ones with the highest priority -//! are processed before the lower priority interrupts. Smaller numbers -//! correspond to higher interrupt priorities; priority 0 is the highest -//! interrupt priority. -//! -//! The hardware priority mechanism will only look at the upper N bits of the -//! priority level (where N is 3), so any prioritization must be performed in -//! those bits. The remaining bits can be used to sub-prioritize the interrupt -//! sources, and may be used by the hardware priority mechanism on a future -//! part. This arrangement allows priorities to migrate to different NVIC -//! implementations without changing the gross prioritization of the -//! interrupts. -//! -//! The parameter \e ucPriority can be any one of the following -//! -\b INT_PRIORITY_LVL_0 -//! -\b INT_PRIORITY_LVL_1 -//! -\b INT_PRIORITY_LVL_2 -//! -\b INT_PRIORITY_LVL_3 -//! -\b INT_PRIORITY_LVL_4 -//! -\b INT_PRIORITY_LVL_5 -//! -\b INT_PRIORITY_LVL_6 -//! -\b INT_PRIORITY_LVL_7 -//! -//! \return None. -// -//***************************************************************************** -void -IntPrioritySet(unsigned long ulInterrupt, unsigned char ucPriority) -{ - unsigned long ulTemp; - - // - // Check the arguments. - // - ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); - - // - // Set the interrupt priority. - // - ulTemp = HWREG(g_pulRegs[ulInterrupt >> 2]); - ulTemp &= ~(0xFF << (8 * (ulInterrupt & 3))); - ulTemp |= ucPriority << (8 * (ulInterrupt & 3)); - HWREG(g_pulRegs[ulInterrupt >> 2]) = ulTemp; -} - -//***************************************************************************** -// -//! Gets the priority of an interrupt. -//! -//! \param ulInterrupt specifies the interrupt in question. -//! -//! This function gets the priority of an interrupt. See IntPrioritySet() for -//! a definition of the priority value. -//! -//! \return Returns the interrupt priority, or -1 if an invalid interrupt was -//! specified. -// -//***************************************************************************** -long -IntPriorityGet(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT((ulInterrupt >= 4) && (ulInterrupt < NUM_INTERRUPTS)); - - // - // Return the interrupt priority. - // - return((HWREG(g_pulRegs[ulInterrupt >> 2]) >> (8 * (ulInterrupt & 3))) & - 0xFF); -} - -//***************************************************************************** -// -//! Enables an interrupt. -//! -//! \param ulInterrupt specifies the interrupt to be enabled. -//! -//! The specified interrupt is enabled in the interrupt controller. Other -//! enables for the interrupt (such as at the peripheral level) are unaffected -//! by this function. -//! -//! \return None. -// -//***************************************************************************** -void -IntEnable(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to enable. - // - if(ulInterrupt == FAULT_MPU) - { - // - // Enable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_MEM; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_BUS) - { - // - // Enable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_BUS; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_USAGE) - { - // - // Enable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) |= NVIC_SYS_HND_CTRL_USAGE; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_SYSTICK) - { - // - // Enable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt >= 16) - { - // - // Enable the general interrupt. - // - HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) = - 1 << ((ulInterrupt - 16) & 31); - __asm(" dsb "); - __asm(" isb "); - } -} - -//***************************************************************************** -// -//! Disables an interrupt. -//! -//! \param ulInterrupt specifies the interrupt to be disabled. -//! -//! The specified interrupt is disabled in the interrupt controller. Other -//! enables for the interrupt (such as at the peripheral level) are unaffected -//! by this function. -//! -//! \return None. -// -//***************************************************************************** -void -IntDisable(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to disable. - // - if(ulInterrupt == FAULT_MPU) - { - // - // Disable the MemManage interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_MEM); - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_BUS) - { - // - // Disable the bus fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_BUS); - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_USAGE) - { - // - // Disable the usage fault interrupt. - // - HWREG(NVIC_SYS_HND_CTRL) &= ~(NVIC_SYS_HND_CTRL_USAGE); - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_SYSTICK) - { - // - // Disable the System Tick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt >= 16) - { - // - // Disable the general interrupt. - // - HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) = - 1 << ((ulInterrupt - 16) & 31); - __asm(" dsb "); - __asm(" isb "); - } - -} - -//***************************************************************************** -// -//! Pends an interrupt. -//! -//! \param ulInterrupt specifies the interrupt to be pended. -//! -//! The specified interrupt is pended in the interrupt controller. This will -//! cause the interrupt controller to execute the corresponding interrupt -//! handler at the next available time, based on the current interrupt state -//! priorities. For example, if called by a higher priority interrupt handler, -//! the specified interrupt handler will not be called until after the current -//! interrupt handler has completed execution. The interrupt must have been -//! enabled for it to be called. -//! -//! \return None. -// -//***************************************************************************** -void -IntPendSet(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to pend. - // - if(ulInterrupt == FAULT_NMI) - { - // - // Pend the NMI interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_NMI_SET; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_PENDSV) - { - // - // Pend the PendSV interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PEND_SV; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt == FAULT_SYSTICK) - { - // - // Pend the SysTick interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET; - __asm(" dsb "); - __asm(" isb "); - } - else if(ulInterrupt >= 16) - { - // - // Pend the general interrupt. - // - HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) = - 1 << ((ulInterrupt - 16) & 31); - __asm(" dsb "); - __asm(" isb "); - } - -} - -//***************************************************************************** -// -//! Unpends an interrupt. -//! -//! \param ulInterrupt specifies the interrupt to be unpended. -//! -//! The specified interrupt is unpended in the interrupt controller. This will -//! cause any previously generated interrupts that have not been handled yet -//! (due to higher priority interrupts or the interrupt no having been enabled -//! yet) to be discarded. -//! -//! \return None. -// -//***************************************************************************** -void -IntPendClear(unsigned long ulInterrupt) -{ - // - // Check the arguments. - // - ASSERT(ulInterrupt < NUM_INTERRUPTS); - - // - // Determine the interrupt to unpend. - // - if(ulInterrupt == FAULT_PENDSV) - { - // - // Unpend the PendSV interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_UNPEND_SV; - } - else if(ulInterrupt == FAULT_SYSTICK) - { - // - // Unpend the SysTick interrupt. - // - HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR; - } - else if(ulInterrupt >= 16) - { - // - // Unpend the general interrupt. - // - HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) = - 1 << ((ulInterrupt - 16) & 31); - } -} - -//***************************************************************************** -// -//! Sets the priority masking level -//! -//! \param ulPriorityMask is the priority level that will be masked. -//! -//! This function sets the interrupt priority masking level so that all -//! interrupts at the specified or lesser priority level is masked. This -//! can be used to globally disable a set of interrupts with priority below -//! a predetermined threshold. A value of 0 disables priority -//! masking. -//! -//! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 will allow interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater will be blocked. -//! -//! The hardware priority mechanism will only look at the upper N bits of the -//! priority level (where N is 3), so any -//! prioritization must be performed in those bits. -//! -//! \return None. -// -//***************************************************************************** -void -IntPriorityMaskSet(unsigned long ulPriorityMask) -{ - CPUbasepriSet(ulPriorityMask); -} - -//***************************************************************************** -// -//! Gets the priority masking level -//! -//! This function gets the current setting of the interrupt priority masking -//! level. The value returned is the priority level such that all interrupts -//! of that and lesser priority are masked. A value of 0 means that priority -//! masking is disabled. -//! -//! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 will allow interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater will be blocked. -//! -//! The hardware priority mechanism will only look at the upper N bits of the -//! priority level (where N is 3), so any -//! prioritization must be performed in those bits. -//! -//! \return Returns the value of the interrupt priority level mask. -// -//***************************************************************************** -unsigned long -IntPriorityMaskGet(void) -{ - return(CPUbasepriGet()); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/interrupt.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/interrupt.h deleted file mode 100644 index 876f7a4e0e1..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/interrupt.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// interrupt.h -// -// Prototypes for the NVIC Interrupt Controller Driver. -// -//***************************************************************************** - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// A union that describes the entries of the vector table. The union is needed -// since the first entry is the stack pointer and the remainder are function -// pointers. -// -//***************************************************************************** -typedef union -{ - void (*pfnHandler)(void); - unsigned long ulPtr; -} -uVectorEntry; - - -//***************************************************************************** -// -// Macro to generate an interrupt priority mask based on the number of bits -// of priority supported by the hardware. -// -//***************************************************************************** -#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) - -//***************************************************************************** -// Interrupt priority levels -//***************************************************************************** -#define INT_PRIORITY_LVL_0 0x00 -#define INT_PRIORITY_LVL_1 0x20 -#define INT_PRIORITY_LVL_2 0x40 -#define INT_PRIORITY_LVL_3 0x60 -#define INT_PRIORITY_LVL_4 0x80 -#define INT_PRIORITY_LVL_5 0xA0 -#define INT_PRIORITY_LVL_6 0xC0 -#define INT_PRIORITY_LVL_7 0xE0 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean IntMasterEnable(void); -extern tBoolean IntMasterDisable(void); -extern void IntVTableBaseSet(unsigned long ulVtableBase); -extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); -extern void IntUnregister(unsigned long ulInterrupt); -extern void IntPriorityGroupingSet(unsigned long ulBits); -extern unsigned long IntPriorityGroupingGet(void); -extern void IntPrioritySet(unsigned long ulInterrupt, - unsigned char ucPriority); -extern long IntPriorityGet(unsigned long ulInterrupt); -extern void IntEnable(unsigned long ulInterrupt); -extern void IntDisable(unsigned long ulInterrupt); -extern void IntPendSet(unsigned long ulInterrupt); -extern void IntPendClear(unsigned long ulInterrupt); -extern void IntPriorityMaskSet(unsigned long ulPriorityMask); -extern unsigned long IntPriorityMaskGet(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __INTERRUPT_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/pin.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/pin.c deleted file mode 100644 index 03f9b999530..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/pin.c +++ /dev/null @@ -1,884 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// pin.c -// -// Mapping of peripherals to pins. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup pin_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_types.h" -#include "inc/hw_memmap.h" -#include "inc/hw_ocp_shared.h" -#include "pin.h" - -//***************************************************************************** -// Macros -//***************************************************************************** -#define PAD_MODE_MASK 0x0000000F -#define PAD_STRENGTH_MASK 0x000000E0 -#define PAD_TYPE_MASK 0x00000310 -#define PAD_CONFIG_BASE ((OCP_SHARED_BASE + \ - OCP_SHARED_O_GPIO_PAD_CONFIG_0)) - -//***************************************************************************** -// PIN to PAD matrix -//***************************************************************************** -static const unsigned long g_ulPinToPadMap[64] = -{ - 10,11,12,13,14,15,16,17,255,255,18, - 19,20,21,22,23,24,40,28,29,25,255, - 255,255,255,255,255,255,26,27,255,255,255, - 255,255,255,255,255,255,255,255,255,255,255, - 31,255,255,255,255,0,255,32,30,255,1, - 255,2,3,4,5,6,7,8,9 -}; - - -//***************************************************************************** -// -//! Configures pin mux for the specified pin. -//! -//! \param ulPin is a valid pin. -//! \param ulPinMode is one of the valid mode -//! -//! This function configures the pin mux that selects the peripheral function -//! associated with a particular SOC pin. Only one peripheral function at a -//! time can be associated with a pin, and each peripheral function should -//! only be associated with a single pin at a time. -//! -//! \return none -// -//***************************************************************************** -void PinModeSet(unsigned long ulPin,unsigned long ulPinMode) -{ - - unsigned long ulPad; - - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); - - // - // Set the mode. - // - HWREG(ulPad) = (((HWREG(ulPad) & ~PAD_MODE_MASK) | ulPinMode) & ~(3<<10)); - -} - -//***************************************************************************** -// -//! Gets current pin mux configuration of specified pin. -//! -//! \param ulPin is a valid pin. -//! -//! This function get the current configuration of the pin mux. -//! -//! \return Returns current pin mode if \e ulPin is valid, 0xFF otherwise. -// -//***************************************************************************** -unsigned long PinModeGet(unsigned long ulPin) -{ - - unsigned long ulPad; - - - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE) ; - - // - // return the mode. - // - return (HWREG(ulPad) & PAD_MODE_MASK); - -} - -//***************************************************************************** -// -//! Sets the direction of the specified pin(s). -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinIO is the pin direction and/or mode. -//! -//! This function configures the specified pin(s) as either input only or -//! output only or it configures the pin to be under hardware control. -//! -//! The parameter \e ulPinIO is an enumerated data type that can be one of -//! the following values: -//! -//! - \b PIN_DIR_MODE_IN -//! - \b PIN_DIR_MODE_OUT -//! - \b PIN_DIR_MODE_HW -//! -//! where \b PIN_DIR_MODE_IN specifies that the pin is programmed as a -//! input only, \b PIN_DIR_MODE_OUT specifies that the pin is -//! programmed output only, and \b PIN_DIR_MODE_HW specifies that the pin is -//! placed under hardware control. -//! -//! -//! \return None. -// -//***************************************************************************** -void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO) -{ - unsigned long ulPad; - - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); - - // - // Set the direction - // - HWREG(ulPad) = ((HWREG(ulPad) & ~0xC00) | ulPinIO); -} - -//***************************************************************************** -// -//! Gets the direction of a pin. -//! -//! \param ulPin is one of the valid pin. -//! -//! This function gets the direction and control mode for a specified pin on -//! the selected GPIO port. The pin can be configured as either an input only -//! or output only, or it can be under hardware control. The type of control -//! and direction are returned as an enumerated data type. -//! -//! \return Returns one of the enumerated data types described for -//! GPIODirModeSet(). -// -//***************************************************************************** -unsigned long PinDirModeGet(unsigned long ulPin) -{ - unsigned long ulPad; - - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); - - // - // Return the direction - // - return ((HWREG(ulPad) & 0xC00)); -} - -//***************************************************************************** -// -//! Gets Pin output drive strength and Type -//! -//! \param ulPin is one of the valid pin -//! \param pulPinStrength is pointer to storage for output drive strength -//! \param pulPinType is pinter to storage for pin type -//! -//! This function gets the pin type and output drive strength for the pin -//! specified by \e ulPin parameter. Parameters \e pulPinStrength and -//! \e pulPinType corresponds to the values used in PinConfigSet(). -//! -//! -//! \return None. -// -//***************************************************************************** -void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength, - unsigned long *pulPinType) -{ - - unsigned long ulPad; - - - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); - - - // - // Get the type - // - *pulPinType = (HWREG(ulPad) & PAD_TYPE_MASK); - - // - // Get the output drive strength - // - *pulPinStrength = (HWREG(ulPad) & PAD_STRENGTH_MASK); - -} - -//***************************************************************************** -// -//! Configure Pin output drive strength and Type -//! -//! \param ulPin is one of the valid pin -//! \param ulPinStrength is logical OR of valid output drive strengths. -//! \param ulPinType is one of the valid pin type. -//! -//! This function sets the pin type and strength for the pin specified by -//! \e ulPin parameter. -//! -//! The parameter \e ulPinStrength should be one of the following -//! - \b PIN_STRENGTH_2MA -//! - \b PIN_STRENGTH_4MA -//! - \b PIN_STRENGTH_6MA -//! -//! -//! The parameter \e ulPinType should be one of the following -//! For standard type -//! -//! - \b PIN_TYPE_STD -//! - \b PIN_TYPE_STD_PU -//! - \b PIN_TYPE_STD_PD -//! -//! And for Open drain type -//! -//! - \b PIN_TYPE_OD -//! - \b PIN_TYPE_OD_PU -//! - \b PIN_TYPE_OD_PD -//! -//! \return None. -// -//***************************************************************************** -void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength, - unsigned long ulPinType) -{ - - unsigned long ulPad; - - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - // - // Write the register - // - if(ulPinType == PIN_TYPE_ANALOG) - { - // - // Isolate the input - // - HWREG(0x4402E144) |= ((0x80 << ulPad) & (0x1E << 8)); - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); - - // - // Isolate the output - // - HWREG(ulPad) = 0xC00; - - } - else - { - // - // Enable the input - // - HWREG(0x4402E144) &= ~((0x80 << ulPad) & (0x1E << 8)); - - // - // Calculate the register address - // - ulPad = ((ulPad << 2) + PAD_CONFIG_BASE); - - // - // Write the configuration - // - HWREG(ulPad) = ((HWREG(ulPad) & ~(PAD_STRENGTH_MASK | PAD_TYPE_MASK)) | - (ulPinStrength | ulPinType )); - } - - -} - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by UART peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The UART pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin(s); other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! -//! \note This function cannot be used to turn any pin into a UART pin; it -//! only sets the pin mode and configures it for proper UART operation. -//! -//! -//! \return None. -// -//***************************************************************************** -void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode) -{ - // - // Set the pin to specified mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Set the pin for standard operation - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD); -} - - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by I2C peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The I2C pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! the pin. -//! -//! -//! \note This function cannot be used to turn any pin into a I2C pin; it -//! only sets the pin mode and configures it for proper I2C operation. -//! -//! -//! \return None. -// -//***************************************************************************** -void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode) -{ - // - // Set the pin to specified mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Set the pin for open-drain operation with a weak pull-up. - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_OD_PU); -} - - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by SPI peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The SPI pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin. -//! -//! -//! \note This function cannot be used to turn any pin into a SPI pin; it -//! only sets the pin mode and configures it for proper SPI operation. -//! -//! -//! \return None. -// -//***************************************************************************** -void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode) -{ - - // - // Set the pin to specified mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Set the pin for standard operation - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); - -} - - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by I2S peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The I2S pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin. -//! -//! -//! \note This function cannot be used to turn any pin into a I2S pin; it -//! only sets the pin mode and configures it for proper I2S operation. -//! -//! \return None. -// -//***************************************************************************** -void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode) -{ - - // - // Set the pin to specified mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Set the pin for standard operation - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); - -} - - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by Timer peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The timer PWM pins must be properly configured for the Timer peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin; other configurations may work as well depending upon the -//! board setup (for example, using the on-chip pull-ups). -//! -//! -//! \note This function cannot be used to turn any pin into a timer PWM pin; it -//! only sets the pin mode and configures it for proper timer PWM operation. -//! -//! \return None. -// -//***************************************************************************** -void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode) -{ - - // - // Set the pin to specified mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Set the pin for standard operation - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); -} - - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by Camera peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The Camera pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin. -//! -//! -//! \note This function cannot be used to turn any pin into a Camera pin; it -//! only sets the pin mode and configures it for proper Camera operation. -//! -//! \return None. -// -//***************************************************************************** -void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode) -{ - - // - // Set the pin to specified mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Set the pin for standard operation - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA|PIN_STRENGTH_4MA,PIN_TYPE_STD); - -} - - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by GPIO peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! \param bOpenDrain is one to decide either OpenDrain or STD -//! -//! The GPIO pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin. -//! -//! -//! \return None. -// -//***************************************************************************** -void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,tBoolean bOpenDrain) -{ - - // - // Set the pin for standard push-pull operation. - // - if(bOpenDrain) - { - PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_OD); - } - else - { - PinConfigSet(ulPin, PIN_STRENGTH_2MA, PIN_TYPE_STD); - } - - // - // Set the pin to specified mode - // - PinModeSet(ulPin, ulPinMode); - -} - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by ADC -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The ADC pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin. -//! -//! -//! \note This function cannot be used to turn any pin into a ADC pin; it -//! only sets the pin mode and configures it for proper ADC operation. -//! -//! \return None. -// -//***************************************************************************** -void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode) -{ - // - // Configure the Pin - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_ANALOG); -} - -//***************************************************************************** -// -//! Sets the pin mode and configures the pin for use by SD Host peripheral -//! -//! \param ulPin is one of the valid pin. -//! \param ulPinMode is one of the valid pin mode. -//! -//! The MMC pins must be properly configured for the peripheral to -//! function correctly. This function provides a typical configuration for -//! those pin. -//! -//! -//! \note This function cannot be used to turn any pin into a SD Host pin; it -//! only sets the pin mode and configures it for proper SD Host operation. -//! -//! \return None. -// -//***************************************************************************** -void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode) -{ - // - // Set pin mode - // - PinModeSet(ulPin,ulPinMode); - - // - // Configure the Pin - // - PinConfigSet(ulPin,PIN_STRENGTH_2MA,PIN_TYPE_STD); - -} - - -//***************************************************************************** -// -//! Sets the hysteresis for all the pins -//! -//! \param ulHysteresis is one of the valid predefined hysterisys values -//! -//! This function sets the hysteresis vlaue for all the pins. The parameter -//! \e ulHysteresis can be on one the following: -//! -\b PIN_HYSTERESIS_OFF - To turn Off hysteresis, default on POR -//! -\b PIN_HYSTERESIS_10 - To turn On hysteresis, 10% -//! -\b PIN_HYSTERESIS_20 - To turn On hysteresis, 20% -//! -\b PIN_HYSTERESIS_30 - To turn On hysteresis, 30% -//! -\b PIN_HYSTERESIS_40 - To turn On hysteresis, 40% -//! -//! \return None. -// -//***************************************************************************** -void PinHysteresisSet(unsigned long ulHysteresis) -{ - unsigned long ulRegValue; - - // - // Read the current value - // - ulRegValue = (HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG ) - & ~(0x0000001C)); - - // - // Set the new Hysteresis - // - if( ulHysteresis != PIN_HYSTERESIS_OFF ) - { - ulRegValue |= (ulHysteresis & 0x0000001C); - } - - // - // Write the new value - // - HWREG( OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG ) = ulRegValue; -} - -//***************************************************************************** -// -//! Sets the level of the pin when locked -//! -//! \param ulPin is one of the valid pin. -//! \param ucLevel is the level the pin drives when locked -//! -//! This function sets the pin level when the pin is locked using -//! \sa PinLock() API. -//! -//! By default all pins are set to drive 0. -//! -//! \note Use case is to park the pins when entering LPDS -//! -//! \return None. -// -//***************************************************************************** -void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel) -{ - unsigned long ulPad; - - // - // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - // - // Get the corresponding Pad - // - ulPad = g_ulPinToPadMap[ulPin & 0x3F]; - - // - // Get the required bit - // - ulPad = 1 << ulPad; - - if(ucLevel) - { - HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) |= ulPad; - } - else - { - HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_6 ) &= ~ulPad; - } - } -} - -//***************************************************************************** -// -//! Locks all the pins to configured level(s). -//! -//! \param ulOutEnable the bit-packed representation of pins to be set as output -//! -//! This function locks all the pins to the pre-configure level. By default -//! the pins are set to drive 0. Default level can be changed using -//! \sa PinLockLevelSet() API. -//! -//! The \e ulOutEnable paramter is bit-packed representation of pins that -//! are required to be enabled as output. If a bit is set 1, the corresponding -//! pin (as shown below) are set and locked as output. -//! -//! |------|-----------------------------------------------| -//! | Bit |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| -//! |------|-----------------------------------------------| -//! | Pin |xx|xx|20|19|30|29|21|17|16|15|14|13|12|11|08|07| -//! |------|-----------------------------------------------| -//! -//! |------|-----------------------------------------------| -//! | Bit |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -//! |------|-----------------------------------------------| -//! | Pin |06|05|04|03|02|01|64|63|62|61|60|59|58|57|55|50| -//! |------|-----------------------------------------------| -//! -//! -//! \note Use case is to park the pins when entering LPDS -//! -//! \return None. -// -//***************************************************************************** -void PinLock(unsigned long ulOutEnable) -{ - // - // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - // - // Enable/disable the pin(s) output - // - HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_7 ) = ~ulOutEnable; - - // - // Lock the pins to selected levels - // - HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) |= (3 << 24); - } -} - -//***************************************************************************** -// -//! Unlocks all the pins. -//! -//! This function unlocks all the pins and can be used for peripheral function. -//! -//! By default all the pins are in unlocked state. -//! -//! \note Use case is to un-park the pins when exiting LPDS -//! -//! \return None. -// -//***************************************************************************** -void PinUnlock() -{ - // - // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - // - // Unlock the pins - // - HWREG( OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5 ) &= ~(3 << 24); - } -} - -//***************************************************************************** -// -// Gets pad number from pin number -// -// \param ulPin is a valid pin number -// -// This function return the pad corresponding to the specified pin -// -// \return Pad number on success, 0xFF otherwise -// -//***************************************************************************** -unsigned long PinToPadGet(unsigned long ulPin) -{ - // - // Return the corresponding Pad - // - return g_ulPinToPadMap[ulPin & 0x3F]; -} - - -//***************************************************************************** -// -// Gets pin number from pad number -// -// \param ulPad is a valid pad number -// -// This function return the pin corresponding to the specified pad -// -// \return Pin number on success, 0xFF otherwise -// -//***************************************************************************** -unsigned long PinFromPadGet(unsigned long ulPad) -{ - unsigned long ulPin; - - // - // search and return the pin number - // - for(ulPin=0; ulPin < sizeof(g_ulPinToPadMap)/4; ulPin++) - { - if(g_ulPinToPadMap[ulPin] == ulPad) - { - return ulPin; - } - } - - return 0xFF; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/pin.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/pin.h deleted file mode 100644 index d9ec773cec6..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/pin.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// pin.h -// -// Defines and Macros for the pin mux module -// -//***************************************************************************** - -#ifndef __PIN_H__ -#define __PIN_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// Macros Defining Pins -//***************************************************************************** - -#define PIN_01 0x00000000 -#define PIN_02 0x00000001 -#define PIN_03 0x00000002 -#define PIN_04 0x00000003 -#define PIN_05 0x00000004 -#define PIN_06 0x00000005 -#define PIN_07 0x00000006 -#define PIN_08 0x00000007 -#define PIN_11 0x0000000A -#define PIN_12 0x0000000B -#define PIN_13 0x0000000C -#define PIN_14 0x0000000D -#define PIN_15 0x0000000E -#define PIN_16 0x0000000F -#define PIN_17 0x00000010 -#define PIN_18 0x00000011 -#define PIN_19 0x00000012 -#define PIN_20 0x00000013 -#define PIN_21 0x00000014 -#define PIN_29 0x0000001C -#define PIN_30 0x0000001D -#define PIN_45 0x0000002C -#define PIN_46 0x0000002D -#define PIN_47 0x0000002E -#define PIN_48 0x0000002F -#define PIN_49 0x00000030 -#define PIN_50 0x00000031 -#define PIN_52 0x00000033 -#define PIN_53 0x00000034 -#define PIN_55 0x00000036 -#define PIN_56 0x00000037 -#define PIN_57 0x00000038 -#define PIN_58 0x00000039 -#define PIN_59 0x0000003A -#define PIN_60 0x0000003B -#define PIN_61 0x0000003C -#define PIN_62 0x0000003D -#define PIN_63 0x0000003E -#define PIN_64 0x0000003F - - - -//***************************************************************************** -// Macros that can be used with PinConfigSet(), PinTypeGet(), PinStrengthGet() -//***************************************************************************** - -#define PIN_MODE_0 0x00000000 -#define PIN_MODE_1 0x00000001 -#define PIN_MODE_2 0x00000002 -#define PIN_MODE_3 0x00000003 -#define PIN_MODE_4 0x00000004 -#define PIN_MODE_5 0x00000005 -#define PIN_MODE_6 0x00000006 -#define PIN_MODE_7 0x00000007 -#define PIN_MODE_8 0x00000008 -#define PIN_MODE_9 0x00000009 -#define PIN_MODE_10 0x0000000A -#define PIN_MODE_11 0x0000000B -#define PIN_MODE_12 0x0000000C -#define PIN_MODE_13 0x0000000D -#define PIN_MODE_14 0x0000000E -#define PIN_MODE_15 0x0000000F -// Note : PIN_MODE_255 is a dummy define for pinmux utility code generation -// PIN_MODE_255 should never be used in any user code. -#define PIN_MODE_255 0x000000FF - -//***************************************************************************** -// Macros that can be used with PinDirModeSet() and returned from -// PinDirModeGet(). -//***************************************************************************** -#define PIN_DIR_MODE_IN 0x00000C00 // Pin is input -#define PIN_DIR_MODE_OUT 0x00000800 // Pin is output -#define PIN_DIR_MODE_HW 0x00000000 // Pin is peripheral function - -//***************************************************************************** -// Macros that can be used with PinConfigSet() -//***************************************************************************** -#define PIN_STRENGTH_2MA 0x00000020 -#define PIN_STRENGTH_4MA 0x00000040 -#define PIN_STRENGTH_6MA 0x00000060 - -#define PIN_TYPE_STD 0x00000000 -#define PIN_TYPE_STD_PU 0x00000100 -#define PIN_TYPE_STD_PD 0x00000200 - -#define PIN_TYPE_OD 0x00000010 -#define PIN_TYPE_OD_PU 0x00000110 -#define PIN_TYPE_OD_PD 0x00000210 -#define PIN_TYPE_ANALOG 0x10000000 - -//***************************************************************************** -// Macros that can be used with PinHysteresisSet() -//***************************************************************************** -#define PIN_HYSTERESIS_OFF 0x00000000 -#define PIN_HYSTERESIS_10 0x00000004 -#define PIN_HYSTERESIS_20 0x0000000C -#define PIN_HYSTERESIS_30 0x00000014 -#define PIN_HYSTERESIS_40 0x0000001C - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PinModeSet(unsigned long ulPin, unsigned long ulPinMode); -extern void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO); -extern unsigned long PinDirModeGet(unsigned long ulPin); -extern unsigned long PinModeGet(unsigned long ulPin); -extern void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength, - unsigned long *pulPinType); -extern void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength, - unsigned long ulPinType); -extern void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode, - tBoolean bOpenDrain); -extern void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode); -extern void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode); -extern void PinHysteresisSet(unsigned long ulHysteresis); -extern void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel); -extern void PinLock(unsigned long ulOutEnable); -extern void PinUnlock(void); -extern unsigned long PinToPadGet(unsigned long ulPin); -extern unsigned long PinFromPadGet(unsigned long ulPad); - -#ifdef __cplusplus -} -#endif - -#endif //__PIN_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/prcm.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/prcm.c deleted file mode 100644 index 2946666b009..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/prcm.c +++ /dev/null @@ -1,2741 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -//***************************************************************************** -// -//! \addtogroup PRCM_Power_Reset_Clock_Module_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_types.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_apps_rcm.h" -#include "inc/hw_gprcm.h" -#include "inc/hw_hib1p2.h" -#include "inc/hw_hib3p3.h" -#include "inc/hw_ocp_shared.h" -#include "inc/hw_common_reg.h" -#include "prcm.h" -#include "interrupt.h" -#include "cpu.h" -#include "flash.h" -#include "utils.h" -#include "pin.h" - - -//***************************************************************************** -// Macro definition -//***************************************************************************** -#define PRCM_SOFT_RESET 0x00000001 -#define PRCM_ENABLE_STATUS 0x00000002 -#define SYS_CLK 80000000 -#define XTAL_CLK 40000000 -#define PLL_DIV_8 30000000 - - -//***************************************************************************** -// CC3200 does not have a true RTC capability. However, API(s) in this file -// provide an effective mechanism to support RTC feature in the device. -// -// The implementation to support RTC has been kept very simple. A set of -// HIB Memory Registers in conjunction with Slow Clock Counter are used -// to render RTC information to users. Core principle of design involves -// two steps (a) establish an association between user provided wall-clock -// and slow clock counter. (b) store reference value of this associattion -// in HIB Registers. This reference value and SCC value are then combined -// to create real-world calendar time. -// -// Across HIB cycles, value stored in HIB Registers is retained and slow -// clock counter continues to tick, thereby, this arragement is relevant -// and valid as long as device has a (tickle) battery power. -// -// Further, provision also has been made to set an alarm. When it RTC value -// matches that of set for alarm, an interrupt is generated. -// -// HIB MEM REG0 and REG1 are reserved for TI. -// -// If RTC feature is not used, then HIB REG2 & REG3 are available to user. -// -// Lower half of REG0 is used for TI HW ECO. -//***************************************************************************** -#define RTC_U64MSEC_MK(u32Secs, u16Msec) (((unsigned long long)u32Secs << 10)|\ - (u16Msec & 0x3FF)) - -#define RTC_SECS_IN_U64MSEC(u64Msec) ((unsigned long)(u64Msec >> 10)) -#define RTC_MSEC_IN_U64MSEC(u64Msec) ((unsigned short)(u64Msec & 0x3FF)) - -#define RTC_SECS_U32_REG_ADDR (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG3) -#define RTC_MSEC_U16_REG_ADDR (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2+2) - -#define RTC_U32SECS_REG (HWREG(RTC_SECS_U32_REG_ADDR)) -#define RTC_U16MSEC_REG (*(unsigned short*)RTC_MSEC_U16_REG_ADDR) - -//***************************************************************************** -// Register Access and Updates -// -// Tick of SCC has a resolution of 32768Hz, meaning 1 sec is equal to 32768 -// clock ticks. Ideal way of getting time in millisecond will involve floating -// point arithmetic (division by 32.768). To avoid this, we simply divide it by -// 32, which will give a range from 0 -1023(instead of 0-999). To use this -// output correctly we have to take care of this inaccuracy externally. -// following wrapper can be used to convert the value from cycles to -// millisecond: -// -// CYCLES_U16MS(cycles) ((cycles *1000)/ 1024), -// -// Similarly, before setting the value, it must be first converted (from ms to -// cycles). -// -// U16MS_CYCLES(msec) ((msec *1024)/1000) -// -// Note: There is a precision loss of 1 ms with the above scheme. -// -//***************************************************************************** -#define SCC_U64MSEC_GET() (PRCMSlowClkCtrGet() >> 5) -#define SCC_U64MSEC_MATCH_SET(u64Msec) (PRCMSlowClkCtrMatchSet(u64Msec << 5)) -#define SCC_U64MSEC_MATCH_GET() (PRCMSlowClkCtrMatchGet() >> 5) - -//***************************************************************************** -// -// Bit: 31 is used to indicate use of RTC. If set as '1', RTC feature is used. -// Bits: 30 to 26 are reserved, available to software for use -// Bits: 25 to 16 are used to save millisecond part of RTC reference. -// Bits: 15 to 0 are being used for HW Changes / ECO -// -//***************************************************************************** - -//***************************************************************************** -// Set RTC USE Bit -//***************************************************************************** -static void RTCUseSet(void) -{ - unsigned short usRegValue; - - usRegValue = RTC_U16MSEC_REG | (1 << 15); - - UtilsDelay((80*200)/3); - - RTC_U16MSEC_REG = usRegValue; -} - -//***************************************************************************** -// Checks if RTC-USE bit is set -//***************************************************************************** -static tBoolean IsRTCUsed(void) -{ - unsigned short usRegValue; - - usRegValue = RTC_U16MSEC_REG; - - UtilsDelay((80*200)/3); - - return ((usRegValue & (1 << 15))? true : false); -} - -//***************************************************************************** -// Read 16-bit mSecs -//***************************************************************************** -static unsigned short RTCU16MSecRegRead(void) -{ - unsigned short usRegValue; - - usRegValue = RTC_U16MSEC_REG; - - UtilsDelay((80*200)/3); - - return (usRegValue & 0x3FF); -} - -//***************************************************************************** -// Write 16-bit mSecs -//***************************************************************************** -static void RTCU16MSecRegWrite(unsigned short u16Msec) -{ - unsigned short usRegValue; - - usRegValue = RTC_U16MSEC_REG; - - UtilsDelay((80*200)/3); - - RTC_U16MSEC_REG = ((usRegValue & ~0x3FF) |u16Msec); -} - -//***************************************************************************** -// Read 32-bit Secs -//***************************************************************************** -static unsigned long RTCU32SecRegRead(void) -{ - return (PRCMHIBRegRead(RTC_SECS_U32_REG_ADDR)); -} - -//***************************************************************************** -// Write 32-bit Secs -//***************************************************************************** -static void RTCU32SecRegWrite(unsigned long u32Msec) -{ - PRCMHIBRegWrite(RTC_SECS_U32_REG_ADDR, u32Msec); -} - -//***************************************************************************** -// Macros -//***************************************************************************** -#define IS_RTC_USED() IsRTCUsed() -#define RTC_USE_SET() RTCUseSet() - -#define RTC_U16MSEC_REG_RD() RTCU16MSecRegRead() -#define RTC_U16MSEC_REG_WR(u16Msec) RTCU16MSecRegWrite(u16Msec) - -#define RTC_U32SECS_REG_RD() RTCU32SecRegRead() -#define RTC_U32SECS_REG_WR(u32Secs) RTCU32SecRegWrite(u32Secs) - -#define SELECT_SCC_U42BITS(u64Msec) (u64Msec & 0x3ffffffffff) - -//***************************************************************************** -// Global Peripheral clock and rest Registers -//***************************************************************************** -static const PRCM_PeriphRegs_t PRCM_PeriphRegsList[] = -{ - - {APPS_RCM_O_CAMERA_CLK_GATING, APPS_RCM_O_CAMERA_SOFT_RESET }, - {APPS_RCM_O_MCASP_CLK_GATING, APPS_RCM_O_MCASP_SOFT_RESET }, - {APPS_RCM_O_MMCHS_CLK_GATING, APPS_RCM_O_MMCHS_SOFT_RESET }, - {APPS_RCM_O_MCSPI_A1_CLK_GATING, APPS_RCM_O_MCSPI_A1_SOFT_RESET }, - {APPS_RCM_O_MCSPI_A2_CLK_GATING, APPS_RCM_O_MCSPI_A2_SOFT_RESET }, - {APPS_RCM_O_UDMA_A_CLK_GATING, APPS_RCM_O_UDMA_A_SOFT_RESET }, - {APPS_RCM_O_GPIO_A_CLK_GATING, APPS_RCM_O_GPIO_A_SOFT_RESET }, - {APPS_RCM_O_GPIO_B_CLK_GATING, APPS_RCM_O_GPIO_B_SOFT_RESET }, - {APPS_RCM_O_GPIO_C_CLK_GATING, APPS_RCM_O_GPIO_C_SOFT_RESET }, - {APPS_RCM_O_GPIO_D_CLK_GATING, APPS_RCM_O_GPIO_D_SOFT_RESET }, - {APPS_RCM_O_GPIO_E_CLK_GATING, APPS_RCM_O_GPIO_E_SOFT_RESET }, - {APPS_RCM_O_WDOG_A_CLK_GATING, APPS_RCM_O_WDOG_A_SOFT_RESET }, - {APPS_RCM_O_UART_A0_CLK_GATING, APPS_RCM_O_UART_A0_SOFT_RESET }, - {APPS_RCM_O_UART_A1_CLK_GATING, APPS_RCM_O_UART_A1_SOFT_RESET }, - {APPS_RCM_O_GPT_A0_CLK_GATING , APPS_RCM_O_GPT_A0_SOFT_RESET }, - {APPS_RCM_O_GPT_A1_CLK_GATING, APPS_RCM_O_GPT_A1_SOFT_RESET }, - {APPS_RCM_O_GPT_A2_CLK_GATING, APPS_RCM_O_GPT_A2_SOFT_RESET }, - {APPS_RCM_O_GPT_A3_CLK_GATING, APPS_RCM_O_GPT_A3_SOFT_RESET }, - {APPS_RCM_O_CRYPTO_CLK_GATING, APPS_RCM_O_CRYPTO_SOFT_RESET }, - {APPS_RCM_O_MCSPI_S0_CLK_GATING, APPS_RCM_O_MCSPI_S0_SOFT_RESET }, - {APPS_RCM_O_I2C_CLK_GATING, APPS_RCM_O_I2C_SOFT_RESET } - -}; - -//***************************************************************************** -// -//! Performs a software reset of a MCU and associated peripherals -//! -//! \param bIncludeSubsystem is \b true to reset associated peripherals. -//! -//! This function performs a software reset of a MCU and associated peripherals. -//! To reset the associated peripheral, the parameter \e bIncludeSubsystem -//! should be set to \b true. -//! -//! \return None. -// -//***************************************************************************** -void PRCMMCUReset(tBoolean bIncludeSubsystem) -{ - if(bIncludeSubsystem) - { - // - // Reset Apps processor and associated peripheral - // - HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x2; - } - else - { - // - // Reset Apps processor only - // - HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x1; - } - - // - // Wait for system to enter hibernate - // - __asm(" wfi\n"); - - // - // Infinite loop - // - while(1) - { - - } -} - -//***************************************************************************** -// -//! Gets the reason for a reset. -//! -//! This function returns the reason(s) for a reset. The reset reason are:- -//! -\b PRCM_POWER_ON - Device is powering up. -//! -\b PRCM_LPDS_EXIT - Device is exiting from LPDS. -//! -\b PRCM_CORE_RESET - Device is exiting soft core only reset -//! -\b PRCM_MCU_RESET - Device is exiting soft subsystem reset. -//! -\b PRCM_WDT_RESET - Device was reset by watchdog. -//! -\b PRCM_SOC_RESET - Device is exting SOC reset. -//! -\b PRCM_HIB_EXIT - Device is exiting hibernate. -//! -//! \return Returns one of the cause defined above. -// -//***************************************************************************** -unsigned long PRCMSysResetCauseGet() -{ - unsigned long ulWakeupStatus; - - // - // Read the Reset status - // - ulWakeupStatus = (HWREG(GPRCM_BASE+ GPRCM_O_APPS_RESET_CAUSE) & 0xFF); - - // - // For hibernate do additional check. - // - if(ulWakeupStatus == PRCM_POWER_ON) - { - if(PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_WAKE_STATUS) & 0x1) - { - ulWakeupStatus = PRCM_HIB_EXIT; - - if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000280)) == 0x00000280 ) - { - ulWakeupStatus = PRCM_WDT_RESET; - } - } - } - else if((ulWakeupStatus == PRCM_LPDS_EXIT) && - !(HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG1) & (1 <<2)) ) - { - if(HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x1<<8)) - { - ulWakeupStatus = PRCM_POWER_ON; - } - } - - // - // Return status. - // - return ulWakeupStatus; -} - -//***************************************************************************** -// -//! Enable clock(s) to peripheral. -//! -//! \param ulPeripheral is one of the valid peripherals -//! \param ulClkFlags are bitmask of clock(s) to be enabled. -//! -//! This function enables the clock for the specified peripheral. Peripherals -//! are by default clock gated (disabled) and generates a bus fault if -//! accessed. -//! -//! The parameter \e ulClkFlags can be logical OR of the following: -//! -\b PRCM_RUN_MODE_CLK - Ungates clock to the peripheral -//! -\b PRCM_SLP_MODE_CLK - Keeps the clocks ungated in sleep. -//! -//! \return None. -// -//***************************************************************************** -void -PRCMPeripheralClkEnable(unsigned long ulPeripheral, unsigned long ulClkFlags) -{ - // - // Enable the specified peripheral clocks, Nothing to be done for PRCM_ADC - // as it is a dummy define for pinmux utility code generation - // - if(ulPeripheral != PRCM_ADC) - { - HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) |= ulClkFlags; - } - - // - // Checking ROM Version less than 2.x.x. - // Only for driverlib backward compatibility - // - if( (HWREG(0x00000400) & 0xFFFF) < 2 ) - { - // - // Set the default clock for camera - // - if(ulPeripheral == PRCM_CAMERA) - { - HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) = 0x0404; - } - } -} - -//***************************************************************************** -// -//! Disables clock(s) to peripheral. -//! -//! \param ulPeripheral is one of the valid peripherals -//! \param ulClkFlags are bitmask of clock(s) to be enabled. -//! -//! This function disable the clock for the specified peripheral. Peripherals -//! are by default clock gated (disabled) and generated a bus fault if -//! accessed. -//! -//! The parameter \e ulClkFlags can be logical OR bit fields as defined in -//! PRCMEnablePeripheral(). -//! -//! \return None. -// -//***************************************************************************** -void -PRCMPeripheralClkDisable(unsigned long ulPeripheral, unsigned long ulClkFlags) -{ - // - // Disable the specified peripheral clocks - // - HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) &= ~ulClkFlags; -} - -//***************************************************************************** -// -//! Gets the input clock for the specified peripheral. -//! -//! \param ulPeripheral is one of the valid peripherals. -//! -//! This function gets the input clock for the specified peripheral. -//! -//! The parameter \e ulPeripheral has the same definition as that in -//! PRCMPeripheralClkEnable(); -//! -//! \return Returns input clock frequency for specified peripheral. -// -//***************************************************************************** -unsigned long -PRCMPeripheralClockGet(unsigned long ulPeripheral) -{ - unsigned long ulClockFreq; - unsigned long ulHiPulseDiv; - unsigned long ulLoPulseDiv; - - // - // Get the clock based on specified peripheral. - // - if((ulPeripheral == PRCM_GSPI) | (ulPeripheral == PRCM_SSPI)) - { - return XTAL_CLK; - } - else if(ulPeripheral == PRCM_LSPI) - { - // - // Check NWP generation. - // - if((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_DIEID_READ_REG4) >> 24) & 0x02) - { - return PLL_DIV_8; - } - else - { - return XTAL_CLK; - } - } - else if(ulPeripheral == PRCM_CAMERA) - { - ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) >> 8) & 0x07); - ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) & 0xFF); - } - else if(ulPeripheral == PRCM_SDHOST) - { - ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN) >> 8) & 0x07); - ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN) & 0xFF); - } - else - { - return SYS_CLK; - } - - // - // Compute the clock freq. from the divider value - // - ulClockFreq = (240000000/((ulHiPulseDiv + 1) + (ulLoPulseDiv + 1))); - - // - // Return the clock rate. - // - return ulClockFreq; -} - -//***************************************************************************** -// -//! Performs a software reset of a peripheral. -//! -//! \param ulPeripheral is one of the valid peripheral. -//! -//! This function does soft reset of the specified peripheral -//! -//! \return None. -// -//***************************************************************************** -void -PRCMPeripheralReset(unsigned long ulPeripheral) -{ - volatile unsigned long ulDelay; - - if( ulPeripheral != PRCM_DTHE) - { - // - // Assert the reset - // - HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg) - |= PRCM_SOFT_RESET; - // - // Delay a little bit. - // - for(ulDelay = 0; ulDelay < 16; ulDelay++) - { - } - - // - // Deassert the reset - // - HWREG(ARCM_BASE+PRCM_PeriphRegsList[ulPeripheral].ulRstReg) - &= ~PRCM_SOFT_RESET; - } -} - -//***************************************************************************** -// -//! Determines if a peripheral is ready. -//! -//! \param ulPeripheral is one of the valid modules -//! -//! This function determines if a particular peripheral is ready to be -//! accessed. The peripheral may be in a non-ready state if it is not enabled, -//! is being held in reset, or is in the process of becoming ready after being -//! enabled or taken out of reset. -//! -//! \return Returns \b true if the peripheral is ready, \b false otherwise. -// -//***************************************************************************** -tBoolean -PRCMPeripheralStatusGet(unsigned long ulPeripheral) -{ - unsigned long ReadyBit; - - // - // Read the ready bit status - // - ReadyBit = HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg); - ReadyBit = ReadyBit & PRCM_ENABLE_STATUS; - - if (ReadyBit) - { - // - // Module is ready - // - return(true); - } - else - { - // - // Module is not ready - // - return(false); - } -} - -//***************************************************************************** -// -//! Configure I2S fracactional divider -//! -//! \param ulI2CClkFreq is the required input clock for McAPS module -//! -//! This function configures I2S fractional divider. By default this -//! divider is set to output 24 Mhz clock to I2S module. -//! -//! The minimum frequency that can be obtained by configuring this divider is -//! -//! (240000KHz/1023.99) = 234.377 KHz -//! -//! \return None. -// -//***************************************************************************** -void -PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq) -{ - unsigned long long ullDiv; - unsigned short usInteger; - unsigned short usFrac; - - ullDiv = (((unsigned long long)240000000 * 65536)/ulI2CClkFreq); - - usInteger = (ullDiv/65536); - usFrac = (ullDiv%65536); - - HWREG(ARCM_BASE + APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0) = - ((usInteger & 0x3FF) << 16 | usFrac); -} - -//***************************************************************************** -// -//! Sets the LPDS exit PC and SP restore vlaues. -//! -//! \param ulStackPtr is the SP restore value. -//! \param ulProgCntr is the PC restore value -//! -//! This function sets the LPDS exit PC and SP restore vlaues. Setting -//! \e ulProgCntr to a non-zero value, forces bootloader to jump to that -//! address with Stack Pointer initialized to \e ulStackPtr on LPDS exit, -//! otherwise the application's vector table entries are used. -//! -//! \return None. -// -//***************************************************************************** -void -PRCMLPDSRestoreInfoSet(unsigned long ulStackPtr, unsigned long ulProgCntr) -{ - // - // ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - // - // Set The SP Value - // - HWREG(0x4402E160) = ulStackPtr; - - // - // Set The PC Value - // - HWREG(0x4402E198) = ulProgCntr; - - } - else - { - // - // Set The SP Value - // - HWREG(0x4402E18C) = ulStackPtr; - - // - // Set The PC Value - // - HWREG(0x4402E190) = ulProgCntr; - } -} - -//***************************************************************************** -// -//! Puts the system into Low Power Deel Sleep (LPDS) power mode. -//! -//! This function puts the system into Low Power Deel Sleep (LPDS) power mode. -//! A call to this function never returns and the execution starts from Reset. -//! \sa PRCMLPDSRestoreInfoSet(). -//! -//! \return None. -//! -//! \note External debugger will always disconnect whenever the system -//! enters LPDS and debug interface is shutdown until next POR reset. In order -//! to avoid this and allow for connecting back the debugger after waking up -//! from LPDS \sa PRCMLPDSEnterKeepDebugIf(). -//! -// -//***************************************************************************** -void -PRCMLPDSEnter() -{ - unsigned long ulChipId; - - // - // Read the Chip ID - // - ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); - - // - // Check if flash exists - // - if( (0x11 == ulChipId) || (0x19 == ulChipId)) - { - - // - // Disable the flash - // - FlashDisable(); - } - -#ifndef KEEP_TESTPD_ALIVE - - // - // Disable TestPD - // - HWREG(0x4402E168) |= (1<<9); -#endif - - // - // Set bandgap duty cycle to 1 - // - HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; - - // - // Request LPDS - // - HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ) - = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ; - - // - // Wait for system to enter LPDS - // - __asm(" wfi\n"); - - // - // Infinite loop - // - while(1) - { - - } - -} - - -//***************************************************************************** -// -//! Puts the system into Low Power Deel Sleep (LPDS) power mode keeping -//! debug interface alive. -//! -//! This function puts the system into Low Power Deel Sleep (LPDS) power mode -//! keeping debug interface alive. A call to this function never returns and the -//! execution starts from Reset \sa PRCMLPDSRestoreInfoSet(). -//! -//! \return None. -//! -//! \note External debugger will always disconnect whenever the system -//! enters LPDS, using this API will allow connecting back the debugger after -//! waking up from LPDS. This API is recommended for development purposes -//! only as it adds to the current consumption of the system. -//! -// -//***************************************************************************** -void -PRCMLPDSEnterKeepDebugIf() -{ - unsigned long ulChipId; - - // - // Read the Chip ID - // - ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); - - // - // Check if flash exists - // - if( (0x11 == ulChipId) || (0x19 == ulChipId)) - { - - // - // Disable the flash - // - FlashDisable(); - } - - // - // Set bandgap duty cycle to 1 - // - HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1; - - // - // Request LPDS - // - HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ) - = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ; - - // - // Wait for system to enter LPDS - // - __asm(" wfi\n"); - - // - // Infinite loop - // - while(1) - { - - } - -} - -//***************************************************************************** -// -//! Enable the individual LPDS wakeup source(s). -//! -//! \param ulLpdsWakeupSrc is logical OR of wakeup sources. -//! -//! This function enable the individual LPDS wakeup source(s) and following -//! three wakeup sources (\e ulLpdsWakeupSrc ) are supported by the device. -//! -\b PRCM_LPDS_HOST_IRQ -//! -\b PRCM_LPDS_GPIO -//! -\b PRCM_LPDS_TIMER -//! -//! \return None. -// -//***************************************************************************** -void -PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc) -{ - unsigned long ulRegVal; - - // - // Read the current wakup sources - // - ulRegVal = HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG); - - // - // Enable individual wakeup source - // - ulRegVal = ((ulRegVal | ulLpdsWakeupSrc) & 0x91); - - // - // Set the configuration in the register - // - HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) = ulRegVal; -} - -//***************************************************************************** -// -//! Disable the individual LPDS wakeup source(s). -//! -//! \param ulLpdsWakeupSrc is logical OR of wakeup sources. -//! -//! This function enable the individual LPDS wakeup source(s) and following -//! three wake up sources (\e ulLpdsWakeupSrc ) are supported by the device. -//! -\b PRCM_LPDS_HOST_IRQ -//! -\b PRCM_LPDS_GPIO -//! -\b PRCM_LPDS_TIMER -//! -//! \return None. -// -//***************************************************************************** -void -PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc) -{ - HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) &= ~ulLpdsWakeupSrc; -} - - -//***************************************************************************** -// -//! Get LPDS wakeup cause -//! -//! This function gets LPDS wakeup caouse -//! -//! \return Returns values enumerated as described in -//! PRCMLPDSWakeupSourceEnable(). -// -//***************************************************************************** -unsigned long -PRCMLPDSWakeupCauseGet() -{ - return (HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_SRC)); -} - -//***************************************************************************** -// -//! Sets LPDS wakeup Timer -//! -//! \param ulTicks is number of 32.768 KHz clocks -//! -//! This function sets internal LPDS wakeup timer running at 32.768 KHz. The -//! timer is only configured if the parameter \e ulTicks is in valid range i.e. -//! from 21 to 2^32. -//! -//! \return Returns \b true on success, \b false otherwise. -// -//***************************************************************************** -void -PRCMLPDSIntervalSet(unsigned long ulTicks) -{ - // - // Check sleep is atleast for 21 cycles - // If not set the sleep time to 21 cycles - // - if( ulTicks < 21) - { - ulTicks = 21; - } - - HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG) = ulTicks; - HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG) = ulTicks-20; -} - -//***************************************************************************** -// -//! Selects the GPIO for LPDS wakeup -//! -//! \param ulGPIOPin is one of the valid GPIO fro LPDS wakeup. -//! \param ulType is the wakeup trigger type. -//! -//! This function setects the wakeup GPIO for LPDS wakeup and can be -//! used to select one out of 7 pre-defined GPIO(s). -//! -//! The parameter \e ulLpdsGPIOSel should be one of the following:- -//! -\b PRCM_LPDS_GPIO2 -//! -\b PRCM_LPDS_GPIO4 -//! -\b PRCM_LPDS_GPIO13 -//! -\b PRCM_LPDS_GPIO17 -//! -\b PRCM_LPDS_GPIO11 -//! -\b PRCM_LPDS_GPIO24 -//! -\b PRCM_LPDS_GPIO26 -//! -//! The parameter \e ulType sets the trigger type and can be one of the -//! following: -//! - \b PRCM_LPDS_LOW_LEVEL -//! - \b PRCM_LPDS_HIGH_LEVEL -//! - \b PRCM_LPDS_FALL_EDGE -//! - \b PRCM_LPDS_RISE_EDGE -//! -//! \return None. -// -//***************************************************************************** -void -PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, unsigned long ulType) -{ - // - // Set the wakeup GPIO - // - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL, ulGPIOPin); - - // - // Set the trigger type. - // - HWREG(GPRCM_BASE + GPRCM_O_APPS_GPIO_WAKE_CONF) = (ulType & 0x3); -} - -//***************************************************************************** -// -//! Puts the system into Sleep. -//! -//! This function puts the system into sleep power mode. System exits the power -//! state on any one of the available interrupt. On exit from sleep mode the -//! function returns to the calling function with all the processor core -//! registers retained. -//! -//! \return None. -// -//***************************************************************************** -void -PRCMSleepEnter() -{ - // - // Request Sleep - // - CPUwfi(); -} - -//***************************************************************************** -// -//! Enable SRAM column retention during LPDS Power mode(s) -//! -//! \param ulSramColSel is bit mask of valid SRAM columns. -//! \param ulModeFlags is the bit mask of power modes. -//! -//! This functions enables the SRAM retention. The device supports configurable -//! SRAM column retention in Low Power Deep Sleep (LPDS). Each column is of -//! 64 KB size. -//! -//! The parameter \e ulSramColSel should be logical OR of the following:- -//! -\b PRCM_SRAM_COL_1 -//! -\b PRCM_SRAM_COL_2 -//! -\b PRCM_SRAM_COL_3 -//! -\b PRCM_SRAM_COL_4 -//! -//! The parameter \e ulModeFlags selects the power modes and sholud be logical -//! OR of one or more of the following -//! -\b PRCM_SRAM_LPDS_RET -//! -//! \return None. -// -//**************************************************************************** -void -PRCMSRAMRetentionEnable(unsigned long ulSramColSel, unsigned long ulModeFlags) -{ - if(ulModeFlags & PRCM_SRAM_LPDS_RET) - { - // - // Configure LPDS SRAM retention register - // - HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) = (ulSramColSel & 0xF); - } -} - -//***************************************************************************** -// -//! Disable SRAM column retention during LPDS Power mode(s). -//! -//! \param ulSramColSel is bit mask of valid SRAM columns. -//! \param ulFlags is the bit mask of power modes. -//! -//! This functions disable the SRAM retention. The device supports configurable -//! SRAM column retention in Low Power Deep Sleep (LPDS). Each column is -//! of 64 KB size. -//! -//! The parameter \e ulSramColSel should be logical OR of the following:- -//! -\b PRCM_SRAM_COL_1 -//! -\b PRCM_SRAM_COL_2 -//! -\b PRCM_SRAM_COL_3 -//! -\b PRCM_SRAM_COL_4 -//! -//! The parameter \e ulFlags selects the power modes and sholud be logical OR -//! of one or more of the following -//! -\b PRCM_SRAM_LPDS_RET -//! -//! \return None. -// -//**************************************************************************** -void -PRCMSRAMRetentionDisable(unsigned long ulSramColSel, unsigned long ulFlags) -{ - if(ulFlags & PRCM_SRAM_LPDS_RET) - { - // - // Configure LPDS SRAM retention register - // - HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) &= ~(ulSramColSel & 0xF); - } -} - - -//***************************************************************************** -// -//! Enables individual HIB wakeup source(s). -//! -//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources. -//! -//! This function enables individual HIB wakeup source(s). The paramter -//! \e ulHIBWakupSrc is the bit mask of HIB wakeup sources and should be -//! logical OR of one or more of the follwoing :- -//! -\b PRCM_HIB_SLOW_CLK_CTR -//! -\b PRCM_HIB_GPIO2 -//! -\b PRCM_HIB_GPIO4 -//! -\b PRCM_HIB_GPIO13 -//! -\b PRCM_HIB_GPIO17 -//! -\b PRCM_HIB_GPIO11 -//! -\b PRCM_HIB_GPIO24 -//! -\b PRCM_HIB_GPIO26 -//! -//! \return None. -// -//***************************************************************************** -void -PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc) -{ - unsigned long ulRegValue; - - // - // Read the RTC register - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN); - - // - // Enable the RTC as wakeup source if specified - // - ulRegValue |= (ulHIBWakupSrc & 0x1); - - // - // Enable HIB wakeup sources - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue); - - // - // REad the GPIO wakeup configuration register - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN); - - // - // Enable the specified GPIOs a wakeup sources - // - ulRegValue |= ((ulHIBWakupSrc>>16)&0xFF); - - // - // Write the new register configuration - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue); -} - -//***************************************************************************** -// -//! Disable individual HIB wakeup source(s). -//! -//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources. -//! -//! This function disable individual HIB wakeup source(s). The paramter -//! \e ulHIBWakupSrc is same as bit fileds defined in -//! PRCMEnableHibernateWakeupSource() -//! -//! \return None. -// -//***************************************************************************** -void -PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc) -{ - unsigned long ulRegValue; - - // - // Read the RTC register - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN); - - // - // Disable the RTC as wakeup source if specified - // - ulRegValue &= ~(ulHIBWakupSrc & 0x1); - - // - // Disable HIB wakeup sources - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue); - - // - // Read the GPIO wakeup configuration register - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN); - - // - // Enable the specified GPIOs a wakeup sources - // - ulRegValue &= ~((ulHIBWakupSrc>>16)&0xFF); - - // - // Write the new register configuration - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue); -} - - -//***************************************************************************** -// -//! Get hibernate wakeup cause -//! -//! This function gets the hibernate wakeup cause. -//! -//! \return Returns \b PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK or -//! \b PRCM_HIB_WAKEUP_CAUSE_GPIO -// -//***************************************************************************** -unsigned long -PRCMHibernateWakeupCauseGet() -{ - // - // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - return ((PRCMHIBRegRead((OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8))>>2)&0x7); - } - else - { - return(0); - } -} - -//***************************************************************************** -// -//! Sets Hibernate wakeup Timer -//! -//! \param ullTicks is number of 32.768 KHz clocks -//! -//! This function sets internal hibernate wakeup timer running at 32.768 KHz. -//! -//! \return Returns \b true on success, \b false otherwise. -// -//***************************************************************************** -void -PRCMHibernateIntervalSet(unsigned long long ullTicks) -{ - unsigned long long ullRTCVal; - - // - // Latch the RTC vlaue - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ ,0x1); - - // - // Read latched values as 2 32-bit vlaues - // - ullRTCVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW); - ullRTCVal = ullRTCVal << 32; - ullRTCVal |= PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW); - - // - // Add the interval - // - ullRTCVal = ullRTCVal + ullTicks; - - // - // Set RTC match value - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF, - (unsigned long)(ullRTCVal)); - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF, - (unsigned long)(ullRTCVal>>32)); -} - - -//***************************************************************************** -// -//! Selects the GPIO(s) for hibernate wakeup -//! -//! \param ulGPIOBitMap is the bit-map of valid hibernate wakeup GPIO. -//! \param ulType is the wakeup trigger type. -//! -//! This function setects the wakeup GPIO for hibernate and can be -//! used to select any combination of 7 pre-defined GPIO(s). -//! -//! This function enables individual HIB wakeup source(s). The paramter -//! \e ulGPIOBitMap should be one of the follwoing :- -//! -\b PRCM_HIB_GPIO2 -//! -\b PRCM_HIB_GPIO4 -//! -\b PRCM_HIB_GPIO13 -//! -\b PRCM_HIB_GPIO17 -//! -\b PRCM_HIB_GPIO11 -//! -\b PRCM_HIB_GPIO24 -//! -\b PRCM_HIB_GPIO26 -//! -//! The parameter \e ulType sets the trigger type and can be one of the -//! following: -//! - \b PRCM_HIB_LOW_LEVEL -//! - \b PRCM_HIB_HIGH_LEVEL -//! - \b PRCM_HIB_FALL_EDGE -//! - \b PRCM_HIB_RISE_EDGE -//! -//! \return None. -// -//***************************************************************************** -void -PRCMHibernateWakeUpGPIOSelect(unsigned long ulGPIOBitMap, unsigned long ulType) -{ - unsigned char ucLoop; - unsigned long ulRegValue; - - // - // Shift the bits to extract the GPIO selection - // - ulGPIOBitMap >>= 16; - - // - // Set the configuration for each GPIO - // - for(ucLoop=0; ucLoop < 7; ucLoop++) - { - if(ulGPIOBitMap & (1<>32)); -} - -//***************************************************************************** -// -//! Gets slow clock counter match value. -//! -//! This function gets the match value for slow clock counter. This is use -//! to interrupt the processor when RTC counts to the specified value. -//! -//! \return None. -// -//***************************************************************************** -unsigned long long PRCMSlowClkCtrMatchGet() -{ - unsigned long long ullValue; - - // - // Get RTC match value - // - ullValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF); - ullValue = ullValue<<32; - ullValue |= PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF); - - // - // Return the value - // - return ullValue; -} - - -//***************************************************************************** -// -//! Write to On-Chip Retention (OCR) register. -//! -//! This function writes to On-Chip retention register. The device supports two -//! 4-byte OCR register which are retained across all power mode. -//! -//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1. -//! -//! These registers are shared by the RTC implementation (if Driverlib RTC -//! APIs are used), ROM, and user application. -//! -//! When RTC APIs in use: -//! -//! |-----------------------------------------------| -//! | INDEX 1 | -//! |-----------------------------------------------| -//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| -//! |-----------------------------------------------| -//! | Reserved by RTC APIs - YY | -//! |-----------------------------------------------| -//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -//! |-----------------------------------------------| -//! | Reserved by RTC APIs - YY | -//! |-----------------------------------------------| -//! -//! -//! |-----------------------------------------------| -//! | INDEX 0 | -//! |-----------------------------------------------| -//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| -//! |-----------------------------------------------| -//! | Reserved by RTC APIs - YY | -//! |-----------------------------------------------| -//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -//! |-----------------------------------------------| -//! |YY| For User Application |XX| -//! |-----------------------------------------------| -//! -//! YY => Reserved by RTC APIs. If Driverlib RTC APIs are used -//! XX => Reserved by ROM -//! -//! -//! When RTC APIs are not in use: -//! -//! |-----------------------------------------------| -//! | INDEX 1 | -//! |-----------------------------------------------| -//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| -//! |-----------------------------------------------| -//! | For User Application | -//! |-----------------------------------------------| -//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -//! |-----------------------------------------------| -//! | For User Application | -//! |-----------------------------------------------| -//! -//! -//! |-----------------------------------------------| -//! | INDEX 0 | -//! |-----------------------------------------------| -//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16| -//! |-----------------------------------------------| -//! | For User Application | -//! |-----------------------------------------------| -//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| -//! |-----------------------------------------------| -//! | For User Application |XX| -//! |-----------------------------------------------| -//! -//! XX => Reserved by ROM -//! -//! -//! -//! \return None. -// -//***************************************************************************** -void PRCMOCRRegisterWrite(unsigned char ucIndex, unsigned long ulRegValue) -{ - unsigned long ulVal; - - // - // Compuitr the offset - // - ucIndex = ucIndex << 2; - - // - // If bit 0 is reserved - // - if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) && - (ucIndex == 0) ) - { - ulVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2 + ucIndex); - ulRegValue = ((ulRegValue << 0x1) | (ulVal & (0x1))); - } - - // - // Write thr value - // - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2 + ucIndex,ulRegValue); - -} - -//***************************************************************************** -// -//! Read from On-Chip Retention (OCR) register. -//! -//! This function reads from On-Chip retention register. The device supports two -//! 4-byte OCR register which are retained across all power mode. -//! -//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1. -//! -//! \sa PRCMOCRRegisterWrite() for the register usage details. -//! -//! \return None. -// -//***************************************************************************** -unsigned long PRCMOCRRegisterRead(unsigned char ucIndex) -{ - unsigned long ulRet; - - // - // Read the OCR register - // - ulRet = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_REG2 + (ucIndex << 2)); - - // - // If bit 0 is reserved - // - if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) && - (ucIndex == 0) ) - { - ulRet = ulRet >> 0x1; - } - - // - // Return the read value. - // - return ulRet; -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the PRCM. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! interrupt is activated. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; -//! -//! \return None. -// -//***************************************************************************** -void PRCMIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler. - // - IntRegister(INT_PRCM, pfnHandler); - - // - // Enable the PRCM interrupt. - // - IntEnable(INT_PRCM); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the PRCM. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a PRCM interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \return None. -// -//***************************************************************************** -void PRCMIntUnregister() -{ - // - // Enable the UART interrupt. - // - IntDisable(INT_PRCM); - - // - // Register the interrupt handler. - // - IntUnregister(INT_PRCM); -} - -//***************************************************************************** -// -//! Enables individual PRCM interrupt sources. -//! -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated ARCM interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! -\b PRCM_INT_SLOW_CLK_CTR -//! -// -//***************************************************************************** -void PRCMIntEnable(unsigned long ulIntFlags) -{ - unsigned long ulRegValue; - - if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR ) - { - // - // Enable PRCM interrupt - // - HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) |= 0x4; - - // - // Enable RTC interrupt - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE); - ulRegValue |= 0x1; - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue); - } -} - -//***************************************************************************** -// -//! Disables individual PRCM interrupt sources. -//! -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated ARCM interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to PRCMEnableInterrupt(). -//! -//! \return None. -// -//***************************************************************************** -void PRCMIntDisable(unsigned long ulIntFlags) -{ - unsigned long ulRegValue; - - if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR ) - { - // - // Disable PRCM interrupt - // - HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) &= ~0x4; - - // - // Disable RTC interrupt - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE); - ulRegValue &= ~0x1; - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue); - } -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! This function returns the PRCM interrupt status of interrupts that are -//! allowed to reflect to the processor. The interrupts are cleared on read. -//! -//! \return Returns the current interrupt status. -// -//***************************************************************************** -unsigned long PRCMIntStatus() -{ - return HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS); -} - -//***************************************************************************** -// -//! Mark the function of RTC as being used -//! -//! This function marks in HW that feature to maintain calendar time in device -//! is being used. -//! -//! Specifically, this feature reserves user's HIB Register-1 accessed through -//! PRCMOCRRegisterWrite(1) for internal work / purpose, therefore, the stated -//! register is not available to user. Also, users must not excercise the Slow -//! Clock Counter API(s), if RTC has been set for use. -//! -//! The RTC feature, if set or marked, can be only reset either through reboot -//! or power cycle. -//! -//! \return None. -// -//***************************************************************************** -void PRCMRTCInUseSet() -{ - RTC_USE_SET(); - return; -} - -//***************************************************************************** -// -//! Ascertain whether function of RTC is being used -//! -//! This function indicates whether function of RTC is being used on the device -//! or not. -//! -//! This routine should be utilized by the application software, when returning -//! from low-power, to confirm that RTC has been put to use and may not need to -//! set the value of the RTC. -//! -//! The RTC feature, if set or marked, can be only reset either through reboot -//! or power cycle. -//! -//! \return None. -// -//***************************************************************************** -tBoolean PRCMRTCInUseGet() -{ - return IS_RTC_USED()? true : false; -} - -//***************************************************************************** -// -//! Set the calendar time in the device. -//! -//! \param ulSecs refers to the seconds part of the calendar time -//! \param usMsec refers to the fractional (ms) part of the second -//! -//! This function sets the specified calendar time in the device. The calendar -//! time is outlined in terms of seconds and milliseconds. However, the device -//! makes no assumption about the origin or reference of the calendar time. -//! -//! The device uses the indicated calendar value to update and maintain the -//! wall-clock time across active and low power states. -//! -//! The function PRCMRTCInUseSet() must be invoked prior to use of this feature. -//! -//! \return None. -// -//***************************************************************************** -void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec) -{ - unsigned long long ullMsec = 0; - - if(IS_RTC_USED()) { - ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec) - SCC_U64MSEC_GET(); - - RTC_U32SECS_REG_WR(RTC_SECS_IN_U64MSEC(ullMsec)); - RTC_U16MSEC_REG_WR(RTC_MSEC_IN_U64MSEC(ullMsec)); - } - - return; -} - -//***************************************************************************** -// -//! Get the instantaneous calendar time from the device. -//! -//! \param ulSecs refers to the seconds part of the calendar time -//! \param usMsec refers to the fractional (ms) part of the second -//! -//! This function fetches the instantaneous value of the ticking calendar time -//! from the device. The calendar time is outlined in terms of seconds and -//! milliseconds. -//! -//! The device provides the calendar value that has been maintained across -//! active and low power states. -//! -//! The function PRCMRTCSet() must have been invoked once to set a reference. -//! -//! \return None. -// -//***************************************************************************** -void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec) -{ - unsigned long long ullMsec = 0; - - if(IS_RTC_USED()) { - ullMsec = RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(), - RTC_U16MSEC_REG_RD()); - ullMsec += SCC_U64MSEC_GET(); - } - - *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec); - *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec); - - return; -} - -//***************************************************************************** -// -//! Set a calendar time alarm. -//! -//! \param ulSecs refers to the seconds part of the calendar time -//! \param usMsec refers to the fractional (ms) part of the second -//! -//! This function sets an wall-clock alarm in the device to be reported for a -//! futuristic calendar time. The calendar time is outlined in terms of seconds -//! and milliseconds. -//! -//! The device provides uses the calendar value that has been maintained across -//! active and low power states to report attainment of alarm time. -//! -//! The function PRCMRTCSet() must have been invoked once to set a reference. -//! -//! \return None. -// -//***************************************************************************** -void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec) -{ - unsigned long long ullMsec = 0; - - if(IS_RTC_USED()) { - ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec); - ullMsec -= RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(), - RTC_U16MSEC_REG_RD()); - SCC_U64MSEC_MATCH_SET(SELECT_SCC_U42BITS(ullMsec)); - } - - return; -} - -//***************************************************************************** -// -//! Get a previously set calendar time alarm. -//! -//! \param ulSecs refers to the seconds part of the calendar time -//! \param usMsec refers to the fractional (ms) part of the second -//! -//! This function fetches from the device a wall-clock alarm that would have -//! been previously set in the device. The calendar time is outlined in terms -//! of seconds and milliseconds. -//! -//! If no alarm was set in the past, then this function would fetch a random -//! information. -//! -//! The function PRCMRTCMatchSet() must have been invoked once to set an alarm. -//! -//! \return None. -// -//***************************************************************************** -void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec) -{ - unsigned long long ullMsec = 0; - - if(IS_RTC_USED()) { - ullMsec = SCC_U64MSEC_MATCH_GET(); - ullMsec += RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(), - RTC_U16MSEC_REG_RD()); - } - - *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec); - *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec); - - return; -} - -//***************************************************************************** -// -//! MCU Initialization Routine -//! -//! This function contains all the mandatory bug fixes, ECO enables, -//! initializations for both CC3200 and CC3220. -//! -//! \note \b ###IMPORTANT### : This is a routine which should be one of the -//! first things to be executed after control comes to MCU Application code. -//! -//! \return None -// -//***************************************************************************** -void PRCMCC3200MCUInit() -{ - - if( PRCMSysResetCauseGet() != PRCM_LPDS_EXIT ) - { - if( 0x00010001 == HWREG(0x00000400) ) - { - -#ifndef REMOVE_CC3200_ES_1_2_1_CODE - - unsigned long ulRegVal; - - // - // DIG DCDC NFET SEL and COT mode disable - // - HWREG(0x4402F010) = 0x30031820; - HWREG(0x4402F00C) = 0x04000000; - - UtilsDelay(32000); - - // - // ANA DCDC clock config - // - HWREG(0x4402F11C) = 0x099; - HWREG(0x4402F11C) = 0x0AA; - HWREG(0x4402F11C) = 0x1AA; - - // - // PA DCDC clock config - // - HWREG(0x4402F124) = 0x099; - HWREG(0x4402F124) = 0x0AA; - HWREG(0x4402F124) = 0x1AA; - - // - // TD Flash timing configurations in case of MCU WDT reset - // - if((HWREG(0x4402D00C) & 0xFF) == 0x00000005) - { - HWREG(0x400F707C) |= 0x01840082; - HWREG(0x400F70C4)= 0x1; - HWREG(0x400F70C4)= 0x0; - } - - // - // Take I2C semaphore - // - ulRegVal = HWREG(0x400F7000); - ulRegVal = (ulRegVal & ~0x3) | 0x1; - HWREG(0x400F7000) = ulRegVal; - - // - // Take GPIO semaphore - // - ulRegVal = HWREG(0x400F703C); - ulRegVal = (ulRegVal & ~0x3FF) | 0x155; - HWREG(0x400F703C) = ulRegVal; - - // - // Enable 32KHz internal RC oscillator - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_INT_OSC_CONF, 0x00000101); - - // - // Delay for a little bit. - // - UtilsDelay(8000); - - // - // Enable 16MHz clock - // - HWREG(HIB1P2_BASE+HIB1P2_O_CM_OSC_16M_CONFIG) = 0x00010008; - - // - // Delay for a little bit. - // - UtilsDelay(8000); - -#endif // REMOVE_CC3200_ES_1_2_1_CODE - - } - else - { - - unsigned long ulRegValue; - - // - // DIG DCDC LPDS ECO Enable - // - HWREG(0x4402F064) |= 0x800000; - - // - // Enable hibernate ECO for PG 1.32 devices only. With this ECO enabled, - // any hibernate wakeup source will be kept maked until the device enters - // hibernate completely (analog + digital) - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0); - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0, ulRegValue | (1<<4)); - - // - // Handling the clock switching (for 1.32 only) - // - HWREG(0x4402E16C) |= 0x3C; - } - - - // - // Enable uDMA - // - PRCMPeripheralClkEnable(PRCM_UDMA,PRCM_RUN_MODE_CLK); - - // - // Reset uDMA - // - PRCMPeripheralReset(PRCM_UDMA); - - // - // Disable uDMA - // - PRCMPeripheralClkDisable(PRCM_UDMA,PRCM_RUN_MODE_CLK); - - // - // Enable RTC - // - if(PRCMSysResetCauseGet()== PRCM_POWER_ON) - { - PRCMHIBRegWrite(0x4402F804,0x1); - } - - // - // SWD mode - // - if(((HWREG(0x4402F0C8) & 0xFF) == 0x2)) - { - HWREG(0x4402E110) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2); - HWREG(0x4402E114) = ((HWREG(0x4402E114) & ~0xC0F) | 0x2); - } - - // - // Override JTAG mux - // - HWREG(0x4402E184) |= 0x2; - - // - // Change UART pins(55,57) mode to PIN_MODE_0 if they are in PIN_MODE_1 - // - if (PinModeGet(PIN_55) == PIN_MODE_1) - { - PinModeSet(PIN_55,PIN_MODE_0); - } - if (PinModeGet(PIN_57) == PIN_MODE_1) - { - PinModeSet(PIN_57,PIN_MODE_0); - } - - // - // Change I2C pins(1,2) mode to PIN_MODE_0 if they are in PIN_MODE_1 - // - if (PinModeGet(PIN_01) == PIN_MODE_1) - { - PinModeSet(PIN_01,PIN_MODE_0); - } - if (PinModeGet(PIN_02) == PIN_MODE_1) - { - PinModeSet(PIN_02,PIN_MODE_0); - } - - // - // DIG DCDC VOUT trim settings based on PROCESS INDICATOR - // - if(((HWREG(0x4402DC78) >> 22) & 0xF) == 0xE) - { - HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x32 << 18)); - } - else - { - HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x29 << 18)); - } - - // - // Enable SOFT RESTART in case of DIG DCDC collapse - // - HWREG(0x4402FC74) &= ~(0x10000000); - - // - // Required only if ROM version is lower than 2.x.x - // - if( (HWREG(0x00000400) & 0xFFFF) < 2 ) - { - // - // Disable the sleep for ANA DCDC - // - HWREG(0x4402F0A8) |= 0x00000004 ; - } - else if( (HWREG(0x00000400) >> 16) >= 1 ) - { - // - // Enable NWP force reset and HIB on WDT reset - // Enable direct boot path for flash - // - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= ((7<<5) | 0x1); - if((HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2) & 0x1) ) - { - HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2) &= ~0x1; - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= (1<<9); - - // - // Clear the RTC hib wake up source - // - HWREG(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN) &= ~0x1; - - // - // Reset RTC match value - // - HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF) = 0; - HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF) = 0; - - } - } - - unsigned long efuse_reg2; - unsigned long ulDevMajorVer, ulDevMinorVer; - // - // Read the device identification register - // - efuse_reg2= HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2); - - // - // Read the ROM mojor and minor version - // - ulDevMajorVer = ((efuse_reg2 >> 28) & 0xF); - ulDevMinorVer = ((efuse_reg2 >> 24) & 0xF); - - if(((ulDevMajorVer == 0x3) && (ulDevMinorVer == 0)) || (ulDevMajorVer < 0x3)) - { - unsigned int Scratch, PreRegulatedMode; - - // 0x4402F840 => 6th bit “1†indicates device is in pre-regulated mode. - PreRegulatedMode = (HWREG(0x4402F840) >> 6) & 1; - - if( PreRegulatedMode) - { - Scratch = HWREG(0x4402F028); - Scratch &= 0xFFFFFF7F; // <7:7> = 0 - HWREG(0x4402F028) = Scratch; - - Scratch = HWREG(0x4402F010); - Scratch &= 0x0FFFFFFF; // <31:28> = 0 - Scratch |= 0x10000000; // <31:28> = 1 - HWREG(0x4402F010) = Scratch; - } - else - { - Scratch = HWREG(0x4402F024); - - Scratch &= 0xFFFFFFF0; // <3:0> = 0 - Scratch |= 0x00000001; // <3:0> = 1 - Scratch &= 0xFFFFF0FF; // <11:8> = 0000 - Scratch |= 0x00000500; // <11:8> = 0101 - Scratch &= 0xFFFE7FFF; // <16:15> = 0000 - Scratch |= 0x00010000; // <16:15> = 10 - - HWREG(0x4402F024) = Scratch; - - Scratch = HWREG(0x4402F028); - - Scratch &= 0xFFFFFF7F; // <7:7> = 0 - Scratch &= 0x0FFFFFFF; // <31:28> = 0 - Scratch &= 0xFF0FFFFF; // <23:20> = 0 - Scratch |= 0x00300000; // <23:20> = 0011 - Scratch &= 0xFFF0FFFF; // <19:16> = 0 - Scratch |= 0x00030000; // <19:16> = 0011 - - HWREG(0x4402F028) = Scratch; - HWREG(0x4402F010) &= 0x0FFFFFFF; // <31:28> = 0 - } - } - else - { - unsigned int Scratch, PreRegulatedMode; - - // 0x4402F840 => 6th bit “1†indicates device is in pre-regulated mode. - PreRegulatedMode = (HWREG(0x4402F840) >> 6) & 1; - - Scratch = HWREG(0x4402F028); - Scratch &= 0xFFFFFF7F; // <7:7> = 0 - HWREG(0x4402F028) = Scratch; - - HWREG(0x4402F010) &= 0x0FFFFFFF; // <31:28> = 0 - if( PreRegulatedMode) - { - HWREG(0x4402F010) |= 0x10000000; // <31:28> = 1 - } - } - } - else - { - unsigned long ulRegVal; - - // - // I2C Configuration - // - ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register); - ulRegVal = (ulRegVal & ~0x3) | 0x1; - HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register) = ulRegVal; - - // - // GPIO configuration - // - ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register); - ulRegVal = (ulRegVal & ~0x3FF) | 0x155; - HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register) = ulRegVal; - - } -} - -//***************************************************************************** -// -//! Reads 32-bit value from register at specified address -//! -//! \param ulRegAddr is the address of register to be read. -//! -//! This function reads 32-bit value from the register as specified by -//! \e ulRegAddr. -//! -//! \return Return the value of the register. -// -//***************************************************************************** -unsigned long PRCMHIBRegRead(unsigned long ulRegAddr) -{ - unsigned long ulValue; - - // - // Read the Reg value - // - ulValue = HWREG(ulRegAddr); - - // - // Wait for 200 uSec - // - UtilsDelay((80*200)/3); - - // - // Return the value - // - return ulValue; -} - -//***************************************************************************** -// -//! Writes 32-bit value to register at specified address -//! -//! \param ulRegAddr is the address of register to be read. -//! \param ulValue is the 32-bit value to be written. -//! -//! This function writes 32-bit value passed as \e ulValue to the register as -//! specified by \e ulRegAddr -//! -//! \return None -// -//***************************************************************************** -void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue) -{ - // - // Read the Reg value - // - HWREG(ulRegAddr) = ulValue; - - // - // Wait for 200 uSec - // - UtilsDelay((80*200)/3); -} - -//***************************************************************************** -// -//! \param ulDivider is clock frequency divider value -//! \param ulWidth is the width of the high pulse -//! -//! This function sets the input frequency for camera module. -//! -//! The frequency is calculated as follows: -//! -//! f_out = 240MHz/ulDivider; -//! -//! The parameter \e ulWidth sets the width of the high pulse. -//! -//! For e.g.: -//! -//! ulDivider = 4; -//! ulWidth = 2; -//! -//! f_out = 30 MHz and 50% duty cycle -//! -//! And, -//! -//! ulDivider = 4; -//! ulWidth = 1; -//! -//! f_out = 30 MHz and 25% duty cycle -//! -//! \return 0 on success, 1 on error -// -//***************************************************************************** -unsigned long PRCMCameraFreqSet(unsigned char ulDivider, unsigned char ulWidth) -{ - if(ulDivider > ulWidth && ulWidth != 0 ) - { - // - // Set the hifh pulse width - // - HWREG(ARCM_BASE + - APPS_RCM_O_CAMERA_CLK_GEN) = (((ulWidth & 0x07) -1) << 8); - - // - // Set the low pulse width - // - HWREG(ARCM_BASE + - APPS_RCM_O_CAMERA_CLK_GEN) = ((ulDivider - ulWidth - 1) & 0x07); - // - // Return success - // - return 0; - } - - // - // Success; - // - return 1; -} - -//***************************************************************************** -// -//! Enable the IO value retention -//! -//! \param ulIORetGrpFlags is one of the valid IO groups. -//! -//! This function enables the IO retention for group of pins as specified by -//! \e ulIORetGrpFlags parameter. Enabling retention will immediately lock the -//! digital pins, in the specified group, to their current state (0 or 1). -//! Output pins can only be driven when retention is disabled. -//! -//! The parameter \e ulIORetGrpFlags can be logical OR of one or -//! more of the following: -//! -\b PRCM_IO_RET_GRP_0 - All the pins except sFlash and JTAG interface -//! -\b PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14 -//! -\b PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17 -//! -\b PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20 -//! -//! \note Use case is to park the pins when entering HIB. -//! -//! \return None. -// -//***************************************************************************** -void PRCMIORetentionEnable(unsigned long ulIORetGrpFlags) -{ - unsigned long ulRegVal; - - // - // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - // - // Disable IO Pad to ODI Path - // - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00001D00; - - // - // 0b'0 in bit 5 for JTAG PADS - // 0b'0 in bit 0 for all other IOs - // - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00000023); - - // - // Enable retention for GRP0 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_0 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF); - ulRegVal |= 0x5; - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF,ulRegVal); - } - - // - // Enable retention for GRP1 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_1 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0); - ulRegVal |= ((0x3<<5)); - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0,ulRegVal); - } - - // - // Enable retention for GRP2 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_2 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF); - ulRegVal |= 0x00000101; - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal); - } - - // - // Enable retention for GRP3 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_3 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF); - ulRegVal |= 0x00000204; - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal); - } - } -} - -//***************************************************************************** -// -//! Disable the IO value retention -//! -//! \param ulIORetGrpFlags is one of the valid IO groups. -//! -//! This function disable the IO retention for group of pins as specified by -//! \e ulIORetGrpFlags parameter. Disabling retention will unlock the -//! digital pins in the specified group. Output pins can only be driven when -//! retention is disabled. -//! -//! The parameter \e ulIORetGrpFlags can be logical OR of one or -//! more of the following: -//! -\b PRCM_IO_RET_GRP_0 - All the pins except sFlash and JTAG interface -//! -\b PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14 -//! -\b PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17 -//! -\b PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20 -//! -//! \note Use case is to un-park the pins when exiting HIB -//! -//! \return None. -// -//***************************************************************************** -void PRCMIORetentionDisable(unsigned long ulIORetGrpFlags) -{ - unsigned long ulRegVal; - - // - // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater - // - if( (HWREG(0x00000400) & 0xFFFF) >= 2 ) - { - - // - // Enable IO Pad to ODI Path - // - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00001D00); - - // - // 0b'1 in bit 5 for JTAG PADS - // 0b'1 in bit 0 for all other IOs - // - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00000023; - - // - // Disable retention for GRP0 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_0 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF); - ulRegVal &= ~0x5; - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF,ulRegVal); - } - - // - // Disable retention for GRP1 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_1 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0); - ulRegVal &= ~((0x3<<5)); - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0,ulRegVal); - } - - // - // Disable retention for GRP2 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_2 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF); - ulRegVal &= ~0x00000101; - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal); - - } - - // - // Disable retention for GRP3 - // - if( ulIORetGrpFlags & PRCM_IO_RET_GRP_3 ) - { - ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF); - ulRegVal &= ~0x00000204; - PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal); - } - - } -} - -//***************************************************************************** -// -//! Gets the device type -//! -//! This function returns bit-packed value representing the device type -//! -//! The returned value is logical OR of one or more of the following:- -//! -//! -\b PRCM_DEV_TYPE_FLAG_R - R variant -//! -\b PRCM_DEV_TYPE_FLAG_F - F variant -//! -\b PRCM_DEV_TYPE_FLAG_Z - Z variant -//! -\b PRCM_DEV_TYPE_FLAG_SECURE - Device is secure -//! -\b PRCM_DEV_TYPE_FLAG_PRE_PROD - Device is a pre-production part -//! -\b PRCM_DEV_TYPE_FLAG_3200 - Device is CC3200 -//! -\b PRCM_DEV_TYPE_FLAG_3220 - Device is CC3220 -//! -\b PRCM_DEV_TYPE_FLAG_REV1 - Device Rev 1 -//! -\b PRCM_DEV_TYPE_FLAG_REV2 - Device Rev 2 -//! -//! Pre-defined helper macros:- -//! -//! -\b PRCM_DEV_TYPE_PRE_CC3200R - Pre-Production CC3200R -//! -\b PRCM_DEV_TYPE_PRE_CC3200F - Pre-Production CC3200F -//! -\b PRCM_DEV_TYPE_PRE_CC3200Z - Pre-Production CC3200Z -//! -\b PRCM_DEV_TYPE_CC3200R - Production CC3200R -//! -\b PRCM_DEV_TYPE_PRE_CC3220R - Pre-Production CC3220R -//! -\b PRCM_DEV_TYPE_PRE_CC3220F - Pre-Production CC3220F -//! -\b PRCM_DEV_TYPE_PRE_CC3220Z - Pre-Production CC3220Z -//! -\b PRCM_DEV_TYPE_CC3220R - Production CC3220R -//! -\b PRCM_DEV_TYPE_PRE_CC3220RS - Pre-Production CC3220RS -//! -\b PRCM_DEV_TYPE_PRE_CC3220FS - Pre-Production CC3220FS -//! -\b PRCM_DEV_TYPE_PRE_CC3220ZS - Pre-Production CC3220ZS -//! -\b PRCM_DEV_TYPE_CC3220RS - Production CC3220RS -//! -\b PRCM_DEV_TYPE_CC3220FS - Production CC3220FS -//! -//! \return Returns, bit-packed value representing the device type, -//! or 0 if device is unknown -// -//***************************************************************************** -unsigned long PRCMDeviceTypeGet() -{ - unsigned long ulDevType; - unsigned long ulChipId; - unsigned long ulDevMajorVer; - unsigned long ulDevMinorVer; - - // - // Read the device identification register - // - ulChipId = HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2); - - // - // Read the ROM mojor and minor version - // - ulDevMajorVer = ((ulChipId >> 28) & 0xF); - ulDevMinorVer = ((ulChipId >> 24) & 0xF); - - - ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F); - - // - // Get the device variant from the chip id - // - switch((ulChipId & 0xF)) - { - // - // It is R variant - // - case 0x0: - ulDevType = PRCM_DEV_TYPE_FLAG_R; - break; - - // - // It is F variant, non secure F variant is always Pre-Production - // - case 0x1: - ulDevType = PRCM_DEV_TYPE_FLAG_F|PRCM_DEV_TYPE_FLAG_PRE_PROD; - break; - - // - // It is Z variant and is always Pre-Production - // - case 0x3: - ulDevType = PRCM_DEV_TYPE_FLAG_Z|PRCM_DEV_TYPE_FLAG_PRE_PROD; - break; - - // - // It is Secure R - // - case 0x8: - ulDevType = PRCM_DEV_TYPE_FLAG_R|PRCM_DEV_TYPE_FLAG_SECURE; - break; - - // - // It is Secure F - // - case 0x9: - ulDevType = PRCM_DEV_TYPE_FLAG_F|PRCM_DEV_TYPE_FLAG_SECURE; - break; - - // - // It is secure Z variant and variant is always Pre-Production - // - case 0xB: - ulDevType = PRCM_DEV_TYPE_FLAG_Z|PRCM_DEV_TYPE_FLAG_SECURE| - PRCM_DEV_TYPE_FLAG_PRE_PROD; - break; - - // - // Undefined variant - // - default: - ulDevType = 0x0; - } - - if( ulDevType != 0 ) - { - if( ulDevMajorVer == 0x3 ) - { - ulDevType |= PRCM_DEV_TYPE_FLAG_3220; - } - else if( ulDevMajorVer == 0x2 ) - { - ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3220); - - if( ((ulDevType & PRCM_DEV_TYPE_FLAG_Z) != 0) ) - { - if((ulDevMinorVer == 0x0)) - { - ulDevType |= PRCM_DEV_TYPE_FLAG_REV1; - } - else - { - ulDevType |= PRCM_DEV_TYPE_FLAG_REV2; - } - } - else - { - if((ulDevMinorVer == 0x1)) - { - ulDevType |= PRCM_DEV_TYPE_FLAG_REV1; - } - } - } - else - { - if( (ulDevMinorVer == 0x4)) - { - if( ((ulDevType & PRCM_DEV_TYPE_FLAG_Z) != 0)) - { - ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3220); - } - else - { - ulDevType |= PRCM_DEV_TYPE_FLAG_3200; - } - } - else - { - ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3200); - } - } - } - - - return ulDevType; -} - - - -//**************************************************************************** -// -//! Used to trigger a hibernate cycle for the device using RTC -//! -//! This API can be used to do a clean reboot of device. -//! -//! \note This routine should only be exercised after all the network processing -//! has been stopped. To stop network processing use \b sl_stop API from -//! simplelink library. -//! -//! \return None -// -//**************************************************************************** -void PRCMHibernateCycleTrigger() -{ - unsigned long ulRegValue; - unsigned long long ullRTCVal; - - // - // Read the RTC register - // - ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN); - - // - // Enable the RTC as wakeup source if specified - // - ulRegValue |= (PRCM_HIB_SLOW_CLK_CTR & 0x1); - - // - // Enable HIB wakeup sources - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue); - - // - // Latch the RTC vlaue - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ ,0x1); - - // - // Read latched values as 2 32-bit vlaues - // - ullRTCVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW); - ullRTCVal = ullRTCVal << 32; - ullRTCVal |= PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW); - - // - //Considering worst case execution times of ROM,RAM,Flash value of 160 is used - // - ullRTCVal = ullRTCVal + 160; - - // - // Set RTC match value - // - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF, - (unsigned long)(ullRTCVal)); - PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF, - (unsigned long)(ullRTCVal>>32)); - // - // Note : Any addition of code after this line would need a change in - // ullTicks Interval currently set to 160 - // - - // - // Request hibernate. - // - PRCMHIBRegWrite((HIB3P3_BASE+HIB3P3_O_MEM_HIB_REQ),0x1); - - // - // Wait for system to enter hibernate - // - __asm(" wfi\n"); - - // - // Infinite loop - // - while(1) - { - - } -} - - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/prcm.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/prcm.h deleted file mode 100644 index 73785aa9756..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/prcm.h +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// prcm.h -// -// Prototypes for the PRCM control driver. -// -//***************************************************************************** - -#ifndef __PRCM_H__ -#define __PRCM_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Peripheral clock and reset control registers -// -//***************************************************************************** -typedef struct _PRCM_PeripheralRegs_ -{ - -unsigned long ulClkReg; -unsigned long ulRstReg; - -}PRCM_PeriphRegs_t; - -//***************************************************************************** -// Values that can be passed to PRCMPeripheralEnable() and -// PRCMPeripheralDisable() -//***************************************************************************** -#define PRCM_RUN_MODE_CLK 0x00000001 -#define PRCM_SLP_MODE_CLK 0x00000100 - -//***************************************************************************** -// Values that can be passed to PRCMSRAMRetentionEnable() and -// PRCMSRAMRetentionDisable() as ulSramColSel. -//***************************************************************************** -#define PRCM_SRAM_COL_1 0x00000001 -#define PRCM_SRAM_COL_2 0x00000002 -#define PRCM_SRAM_COL_3 0x00000004 -#define PRCM_SRAM_COL_4 0x00000008 - -//***************************************************************************** -// Values that can be passed to PRCMSRAMRetentionEnable() and -// PRCMSRAMRetentionDisable() as ulModeFlags. -//***************************************************************************** -#define PRCM_SRAM_LPDS_RET 0x00000002 - -//***************************************************************************** -// Values that can be passed to PRCMLPDSWakeupSourceEnable(), -// PRCMLPDSWakeupCauseGet() and PRCMLPDSWakeupSourceDisable(). -//***************************************************************************** -#define PRCM_LPDS_HOST_IRQ 0x00000080 -#define PRCM_LPDS_GPIO 0x00000010 -#define PRCM_LPDS_TIMER 0x00000001 - -//***************************************************************************** -// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() as Type -//***************************************************************************** -#define PRCM_LPDS_LOW_LEVEL 0x00000002 -#define PRCM_LPDS_HIGH_LEVEL 0x00000000 -#define PRCM_LPDS_FALL_EDGE 0x00000001 -#define PRCM_LPDS_RISE_EDGE 0x00000003 - -//***************************************************************************** -// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() -//***************************************************************************** -#define PRCM_LPDS_GPIO2 0x00000000 -#define PRCM_LPDS_GPIO4 0x00000001 -#define PRCM_LPDS_GPIO13 0x00000002 -#define PRCM_LPDS_GPIO17 0x00000003 -#define PRCM_LPDS_GPIO11 0x00000004 -#define PRCM_LPDS_GPIO24 0x00000005 -#define PRCM_LPDS_GPIO26 0x00000006 - -//***************************************************************************** -// Values that can be passed to PRCMHibernateWakeupSourceEnable(), -// PRCMHibernateWakeupSourceDisable(). -//***************************************************************************** -#define PRCM_HIB_SLOW_CLK_CTR 0x00000001 - -//***************************************************************************** -// Values that can be passed to PRCMHibernateWakeUpGPIOSelect() as ulType -//***************************************************************************** -#define PRCM_HIB_LOW_LEVEL 0x00000000 -#define PRCM_HIB_HIGH_LEVEL 0x00000001 -#define PRCM_HIB_FALL_EDGE 0x00000002 -#define PRCM_HIB_RISE_EDGE 0x00000003 - -//***************************************************************************** -// Values that can be passed to PRCMHibernateWakeupSourceEnable(), -// PRCMHibernateWakeupSourceDisable(), PRCMHibernateWakeUpGPIOSelect() -//***************************************************************************** -#define PRCM_HIB_GPIO2 0x00010000 -#define PRCM_HIB_GPIO4 0x00020000 -#define PRCM_HIB_GPIO13 0x00040000 -#define PRCM_HIB_GPIO17 0x00080000 -#define PRCM_HIB_GPIO11 0x00100000 -#define PRCM_HIB_GPIO24 0x00200000 -#define PRCM_HIB_GPIO26 0x00400000 - -//***************************************************************************** -// Values that will be returned from PRCMSysResetCauseGet(). -//***************************************************************************** -#define PRCM_POWER_ON 0x00000000 -#define PRCM_LPDS_EXIT 0x00000001 -#define PRCM_CORE_RESET 0x00000003 -#define PRCM_MCU_RESET 0x00000004 -#define PRCM_WDT_RESET 0x00000005 -#define PRCM_SOC_RESET 0x00000006 -#define PRCM_HIB_EXIT 0x00000007 - -//***************************************************************************** -// Values that can be passed to PRCMHibernateWakeupCauseGet(). -//***************************************************************************** -#define PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK 0x00000002 -#define PRCM_HIB_WAKEUP_CAUSE_GPIO 0x00000004 - -//***************************************************************************** -// Values that can be passed to PRCMSEnableInterrupt -//***************************************************************************** -#define PRCM_INT_SLOW_CLK_CTR 0x00004000 - -//***************************************************************************** -// Values that can be passed to PRCMPeripheralClkEnable(), -// PRCMPeripheralClkDisable(), PRCMPeripheralReset() -//***************************************************************************** -#define PRCM_CAMERA 0x00000000 -#define PRCM_I2S 0x00000001 -#define PRCM_SDHOST 0x00000002 -#define PRCM_GSPI 0x00000003 -#define PRCM_LSPI 0x00000004 -#define PRCM_UDMA 0x00000005 -#define PRCM_GPIOA0 0x00000006 -#define PRCM_GPIOA1 0x00000007 -#define PRCM_GPIOA2 0x00000008 -#define PRCM_GPIOA3 0x00000009 -#define PRCM_GPIOA4 0x0000000A -#define PRCM_WDT 0x0000000B -#define PRCM_UARTA0 0x0000000C -#define PRCM_UARTA1 0x0000000D -#define PRCM_TIMERA0 0x0000000E -#define PRCM_TIMERA1 0x0000000F -#define PRCM_TIMERA2 0x00000010 -#define PRCM_TIMERA3 0x00000011 -#define PRCM_DTHE 0x00000012 -#define PRCM_SSPI 0x00000013 -#define PRCM_I2CA0 0x00000014 -// Note : PRCM_ADC is a dummy define for pinmux utility code generation -// PRCM_ADC should never be used in any user code. -#define PRCM_ADC 0x000000FF - - -//***************************************************************************** -// Values that can be passed to PRCMIORetEnable() and PRCMIORetDisable() -//***************************************************************************** -#define PRCM_IO_RET_GRP_0 0x00000001 -#define PRCM_IO_RET_GRP_1 0x00000002 -#define PRCM_IO_RET_GRP_2 0x00000004 -#define PRCM_IO_RET_GRP_3 0x00000008 - -//***************************************************************************** -// Macros definig the device type -//***************************************************************************** -#define PRCM_DEV_TYPE_FLAG_R 0x00000001 -#define PRCM_DEV_TYPE_FLAG_F 0x00000002 -#define PRCM_DEV_TYPE_FLAG_Z 0x00000004 -#define PRCM_DEV_TYPE_FLAG_SECURE 0x00000008 -#define PRCM_DEV_TYPE_FLAG_PRE_PROD 0x00000010 -#define PRCM_DEV_TYPE_FLAG_3200 0x00000020 -#define PRCM_DEV_TYPE_FLAG_3220 0x00000040 -#define PRCM_DEV_TYPE_FLAG_REV1 0x00010000 -#define PRCM_DEV_TYPE_FLAG_REV2 0x00020000 - -//***************************************************************************** -// Pre-defined helper macros -//***************************************************************************** -#define PRCM_DEV_TYPE_PRE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3200| \ - PRCM_DEV_TYPE_FLAG_R) - -#define PRCM_DEV_TYPE_PRE_CC3200F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3200| \ - PRCM_DEV_TYPE_FLAG_F) - -#define PRCM_DEV_TYPE_PRE_CC3200Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3200| \ - PRCM_DEV_TYPE_FLAG_Z) - -#define PRCM_DEV_TYPE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3200| \ - PRCM_DEV_TYPE_FLAG_R) - -#define PRCM_DEV_TYPE_PRE_CC3220R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_R) - -#define PRCM_DEV_TYPE_PRE_CC3220F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_F) - -#define PRCM_DEV_TYPE_PRE_CC3220Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_Z) - -#define PRCM_DEV_TYPE_CC3220R (PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_R) - - -#define PRCM_DEV_TYPE_PRE_CC3220RS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_R| \ - PRCM_DEV_TYPE_FLAG_SECURE) - -#define PRCM_DEV_TYPE_PRE_CC3220FS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_F| \ - PRCM_DEV_TYPE_FLAG_SECURE) - -#define PRCM_DEV_TYPE_PRE_CC3220ZS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_Z| \ - PRCM_DEV_TYPE_FLAG_SECURE) - -#define PRCM_DEV_TYPE_CC3220RS (PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_R| \ - PRCM_DEV_TYPE_FLAG_SECURE) - -#define PRCM_DEV_TYPE_CC3220FS (PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_F| \ - PRCM_DEV_TYPE_FLAG_SECURE) - - -#define PRCM_DEV_TYPE_PRE_CC3220Z1 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_Z| \ - PRCM_DEV_TYPE_FLAG_REV1) - -#define PRCM_DEV_TYPE_PRE_CC3220Z2 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \ - PRCM_DEV_TYPE_FLAG_3220| \ - PRCM_DEV_TYPE_FLAG_Z| \ - PRCM_DEV_TYPE_FLAG_REV2) - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void PRCMMCUReset(tBoolean bIncludeSubsystem); -extern unsigned long PRCMSysResetCauseGet(void); - -extern void PRCMPeripheralClkEnable(unsigned long ulPeripheral, - unsigned long ulClkFlags); -extern void PRCMPeripheralClkDisable(unsigned long ulPeripheral, - unsigned long ulClkFlags); -extern void PRCMPeripheralReset(unsigned long ulPeripheral); -extern tBoolean PRCMPeripheralStatusGet(unsigned long ulPeripheral); - -extern void PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq); -extern unsigned long PRCMPeripheralClockGet(unsigned long ulPeripheral); - -extern void PRCMSleepEnter(void); - -extern void PRCMSRAMRetentionEnable(unsigned long ulSramColSel, - unsigned long ulFlags); -extern void PRCMSRAMRetentionDisable(unsigned long ulSramColSel, - unsigned long ulFlags); -extern void PRCMLPDSRestoreInfoSet(unsigned long ulRestoreSP, - unsigned long ulRestorePC); -extern void PRCMLPDSEnter(void); -extern void PRCMLPDSIntervalSet(unsigned long ulTicks); -extern void PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc); -extern unsigned long PRCMLPDSWakeupCauseGet(void); -extern void PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, - unsigned long ulType); -extern void PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc); - -extern void PRCMHibernateEnter(void); -extern void PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc); -extern unsigned long PRCMHibernateWakeupCauseGet(void); -extern void PRCMHibernateWakeUpGPIOSelect(unsigned long ulMultiGPIOBitMap, - unsigned long ulType); -extern void PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc); -extern void PRCMHibernateIntervalSet(unsigned long long ullTicks); - -extern unsigned long long PRCMSlowClkCtrGet(void); -extern unsigned long long PRCMSlowClkCtrFastGet(void); -extern void PRCMSlowClkCtrMatchSet(unsigned long long ullTicks); -extern unsigned long long PRCMSlowClkCtrMatchGet(void); - -extern void PRCMOCRRegisterWrite(unsigned char ucIndex, - unsigned long ulRegValue); -extern unsigned long PRCMOCRRegisterRead(unsigned char ucIndex); - -extern void PRCMIntRegister(void (*pfnHandler)(void)); -extern void PRCMIntUnregister(void); -extern void PRCMIntEnable(unsigned long ulIntFlags); -extern void PRCMIntDisable(unsigned long ulIntFlags); -extern unsigned long PRCMIntStatus(void); -extern void PRCMRTCInUseSet(void); -extern tBoolean PRCMRTCInUseGet(void); -extern void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec); -extern void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec); -extern void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec); -extern void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec); -extern void PRCMCC3200MCUInit(void); -extern unsigned long PRCMHIBRegRead(unsigned long ulRegAddr); -extern void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue); -extern unsigned long PRCMCameraFreqSet(unsigned char ulDivider, - unsigned char ulWidth); -extern void PRCMIORetentionEnable(unsigned long ulIORetGrpFlags); -extern void PRCMIORetentionDisable(unsigned long ulIORetGrpFlags); -extern unsigned long PRCMDeviceTypeGet(void); -extern void PRCMLPDSEnterKeepDebugIf(void); -extern void PRCMHibernateCycleTrigger(void); - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __PRCM_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/rom.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/rom.h deleted file mode 100644 index cac74cdde17..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/rom.h +++ /dev/null @@ -1,2787 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// rom.h - Macros to facilitate calling functions in the ROM. -// -// -//***************************************************************************** -// -// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND. -// -//***************************************************************************** - -#ifndef __ROM_H__ -#define __ROM_H__ - -//***************************************************************************** -// -// For backward compatibility with older Driverlib versions -// -//***************************************************************************** -#ifdef TARGET_IS_CC3200 -#define USE_CC3200_ROM_DRV_API -#endif - -//***************************************************************************** -// -// Pointers to the main API tables. -// -//***************************************************************************** -#define ROM_APITABLE ((unsigned long *)0x0000040C) -#define ROM_VERSION (ROM_APITABLE[0]) -#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1])) -#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[2])) -#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[3])) -#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[4])) -#define ROM_UDMATABLE ((unsigned long *)(ROM_APITABLE[5])) -#define ROM_PRCMTABLE ((unsigned long *)(ROM_APITABLE[6])) -#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[7])) -#define ROM_SPITABLE ((unsigned long *)(ROM_APITABLE[8])) -#define ROM_CAMERATABLE ((unsigned long *)(ROM_APITABLE[9])) -#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[10])) -#define ROM_PINTABLE ((unsigned long *)(ROM_APITABLE[11])) -#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[12])) -#define ROM_UTILSTABLE ((unsigned long *)(ROM_APITABLE[13])) -#define ROM_I2STABLE ((unsigned long *)(ROM_APITABLE[14])) -#define ROM_HWSPINLOCKTABLE ((unsigned long *)(ROM_APITABLE[15])) -#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[16])) -#define ROM_AESTABLE ((unsigned long *)(ROM_APITABLE[17])) -#define ROM_DESTABLE ((unsigned long *)(ROM_APITABLE[18])) -#define ROM_SHAMD5TABLE ((unsigned long *)(ROM_APITABLE[19])) -#define ROM_CRCTABLE ((unsigned long *)(ROM_APITABLE[20])) -#define ROM_SDHOSTTABLE ((unsigned long *)(ROM_APITABLE[21])) -#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[22])) -#define ROM_CPUTABLE ((unsigned long *)(ROM_APITABLE[23])) - -//***************************************************************************** -// -// Macros for calling ROM functions in the Interrupt API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntEnable \ - ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntMasterEnable \ - ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntMasterDisable \ - ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntDisable \ - ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPriorityGroupingSet \ - ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPriorityGroupingGet \ - ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPrioritySet \ - ((void (*)(unsigned long ulInterrupt, \ - unsigned char ucPriority))ROM_INTERRUPTTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPriorityGet \ - ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPendSet \ - ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPendClear \ - ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPriorityMaskSet \ - ((void (*)(unsigned long ulPriorityMask))ROM_INTERRUPTTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntPriorityMaskGet \ - ((unsigned long (*)(void))ROM_INTERRUPTTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntRegister \ - ((void (*)(unsigned long ulInterrupt, \ - void (*pfnHandler)(void)))ROM_INTERRUPTTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntUnregister \ - ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_IntVTableBaseSet \ - ((void (*)(unsigned long ulVtableBase))ROM_INTERRUPTTABLE[14]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Timer API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerConfigure \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulConfig))ROM_TIMERTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerControlLevel \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - tBoolean bInvert))ROM_TIMERTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerControlEvent \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - unsigned long ulEvent))ROM_TIMERTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerControlStall \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - tBoolean bStall))ROM_TIMERTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerPrescaleSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - unsigned long ulValue))ROM_TIMERTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerPrescaleGet \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerPrescaleMatchSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - unsigned long ulValue))ROM_TIMERTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerPrescaleMatchGet \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerLoadSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - unsigned long ulValue))ROM_TIMERTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerLoadGet \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerValueGet \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerMatchSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - unsigned long ulValue))ROM_TIMERTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerMatchGet \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerIntRegister \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - void (*pfnHandler)(void)))ROM_TIMERTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerIntUnregister \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer))ROM_TIMERTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_TIMERTABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_TIMERTABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerIntStatus \ - ((unsigned long (*)(unsigned long ulBase, \ - tBoolean bMasked))ROM_TIMERTABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_TIMERTABLE[20]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerValueSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTimer, \ - unsigned long ulValue))ROM_TIMERTABLE[22]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerDMAEventSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulDMAEvent))ROM_TIMERTABLE[23]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_TimerDMAEventGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_TIMERTABLE[24]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the UART API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTParityModeSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulParity))ROM_UARTTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTParityModeGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTFIFOLevelSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTxLevel, \ - unsigned long ulRxLevel))ROM_UARTTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTFIFOLevelGet \ - ((void (*)(unsigned long ulBase, \ - unsigned long *pulTxLevel, \ - unsigned long *pulRxLevel))ROM_UARTTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTConfigSetExpClk \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulUARTClk, \ - unsigned long ulBaud, \ - unsigned long ulConfig))ROM_UARTTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTConfigGetExpClk \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulUARTClk, \ - unsigned long *pulBaud, \ - unsigned long *pulConfig))ROM_UARTTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTEnable \ - ((void (*)(unsigned long ulBase))ROM_UARTTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTDisable \ - ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTFIFOEnable \ - ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTFIFODisable \ - ((void (*)(unsigned long ulBase))ROM_UARTTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTCharsAvail \ - ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTSpaceAvail \ - ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTCharGetNonBlocking \ - ((long (*)(unsigned long ulBase))ROM_UARTTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTCharGet \ - ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTCharPutNonBlocking \ - ((tBoolean (*)(unsigned long ulBase, \ - unsigned char ucData))ROM_UARTTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTCharPut \ - ((void (*)(unsigned long ulBase, \ - unsigned char ucData))ROM_UARTTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTBreakCtl \ - ((void (*)(unsigned long ulBase, \ - tBoolean bBreakState))ROM_UARTTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTBusy \ - ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTIntRegister \ - ((void (*)(unsigned long ulBase, \ - void(*pfnHandler)(void)))ROM_UARTTABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTIntUnregister \ - ((void (*)(unsigned long ulBase))ROM_UARTTABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_UARTTABLE[20]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_UARTTABLE[21]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTIntStatus \ - ((unsigned long (*)(unsigned long ulBase, \ - tBoolean bMasked))ROM_UARTTABLE[22]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_UARTTABLE[23]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTDMAEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulDMAFlags))ROM_UARTTABLE[24]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTDMADisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulDMAFlags))ROM_UARTTABLE[25]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTRxErrorGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[26]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTRxErrorClear \ - ((void (*)(unsigned long ulBase))ROM_UARTTABLE[27]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTModemControlSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulControl))ROM_UARTTABLE[28]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTModemControlClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulControl))ROM_UARTTABLE[29]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTModemControlGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[30]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTModemStatusGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[31]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTFlowControlSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulMode))ROM_UARTTABLE[32]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTFlowControlGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[33]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTTxIntModeSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulMode))ROM_UARTTABLE[34]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UARTTxIntModeGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[35]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the uDMA API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelTransferSet \ - ((void (*)(unsigned long ulChannelStructIndex, \ - unsigned long ulMode, \ - void *pvSrcAddr, \ - void *pvDstAddr, \ - unsigned long ulTransferSize))ROM_UDMATABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAEnable \ - ((void (*)(void))ROM_UDMATABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMADisable \ - ((void (*)(void))ROM_UDMATABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAErrorStatusGet \ - ((unsigned long (*)(void))ROM_UDMATABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAErrorStatusClear \ - ((void (*)(void))ROM_UDMATABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelEnable \ - ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelDisable \ - ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelIsEnabled \ - ((tBoolean (*)(unsigned long ulChannelNum))ROM_UDMATABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAControlBaseSet \ - ((void (*)(void *pControlTable))ROM_UDMATABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAControlBaseGet \ - ((void * (*)(void))ROM_UDMATABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelRequest \ - ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelAttributeEnable \ - ((void (*)(unsigned long ulChannelNum, \ - unsigned long ulAttr))ROM_UDMATABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelAttributeDisable \ - ((void (*)(unsigned long ulChannelNum, \ - unsigned long ulAttr))ROM_UDMATABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelAttributeGet \ - ((unsigned long (*)(unsigned long ulChannelNum))ROM_UDMATABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelControlSet \ - ((void (*)(unsigned long ulChannelStructIndex, \ - unsigned long ulControl))ROM_UDMATABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelSizeGet \ - ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelModeGet \ - ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAIntStatus \ - ((unsigned long (*)(void))ROM_UDMATABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAIntClear \ - ((void (*)(unsigned long ulChanMask))ROM_UDMATABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAControlAlternateBaseGet \ - ((void * (*)(void))ROM_UDMATABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelScatterGatherSet \ - ((void (*)(unsigned long ulChannelNum, \ - unsigned ulTaskCount, \ - void *pvTaskList, \ - unsigned long ulIsPeriphSG))ROM_UDMATABLE[20]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAChannelAssign \ - ((void (*)(unsigned long ulMapping))ROM_UDMATABLE[21]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAIntRegister \ - ((void (*)(unsigned long ulIntChannel, \ - void (*pfnHandler)(void)))ROM_UDMATABLE[22]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_uDMAIntUnregister \ - ((void (*)(unsigned long ulIntChannel))ROM_UDMATABLE[23]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Watchdog API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogIntClear \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogRunning \ - ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogEnable \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogLock \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogUnlock \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogLockState \ - ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogReloadSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulLoadVal))ROM_WATCHDOGTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogReloadGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogValueGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogIntStatus \ - ((unsigned long (*)(unsigned long ulBase, \ - tBoolean bMasked))ROM_WATCHDOGTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogStallEnable \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogStallDisable \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogIntRegister \ - ((void (*)(unsigned long ulBase, \ - void(*pfnHandler)(void)))ROM_WATCHDOGTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_WatchdogIntUnregister \ - ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the I2C API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CIntRegister \ - ((void (*)(uint32_t ui32Base, \ - void(pfnHandler)(void)))ROM_I2CTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CIntUnregister \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CTxFIFOConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CTxFIFOFlush \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CRxFIFOConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CRxFIFOFlush \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CFIFOStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CFIFODataPut \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CFIFODataPutNonBlocking \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CFIFODataGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CFIFODataGetNonBlocking \ - ((uint32_t (*)(uint32_t ui32Base, \ - uint8_t *pui8Data))ROM_I2CTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterBurstLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Length))ROM_I2CTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterBurstCountGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterGlitchFilterConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveFIFOEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_I2CTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveFIFODisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterBusBusy \ - ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterBusy \ - ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterControl \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Cmd))ROM_I2CTABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterDataGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterDataPut \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[20]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[21]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[22]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterErr \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntClear \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[24]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[25]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[26]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntStatus \ - ((bool (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[27]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntEnableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[28]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntDisableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[29]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntStatusEx \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[30]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterIntClearEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[31]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterTimeoutSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Value))ROM_I2CTABLE[32]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveACKOverride \ - ((void (*)(uint32_t ui32Base, \ - bool bEnable))ROM_I2CTABLE[33]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveACKValueSet \ - ((void (*)(uint32_t ui32Base, \ - bool bACK))ROM_I2CTABLE[34]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterLineStateGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[35]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterSlaveAddrSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8SlaveAddr, \ - bool bReceive))ROM_I2CTABLE[36]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveDataGet \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[37]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveDataPut \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8Data))ROM_I2CTABLE[38]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[39]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveInit \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8SlaveAddr))ROM_I2CTABLE[41]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveAddressSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t ui8AddrNum, \ - uint8_t ui8SlaveAddr))ROM_I2CTABLE[42]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntClear \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[43]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntDisable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[44]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntEnable \ - ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[45]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntClearEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[46]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntDisableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[47]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntEnableEx \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_I2CTABLE[48]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntStatus \ - ((bool (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[49]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveIntStatusEx \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_I2CTABLE[50]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CSlaveStatus \ - ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[51]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2CMasterInitExpClk \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32I2CClk, \ - bool bFast))ROM_I2CTABLE[52]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SPI API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIEnable \ - ((void (*)(unsigned long ulBase))ROM_SPITABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDisable \ - ((void (*)(unsigned long ulBase))ROM_SPITABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIReset \ - ((void (*)(unsigned long ulBase))ROM_SPITABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIConfigSetExpClk \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulSPIClk, \ - unsigned long ulBitRate, \ - unsigned long ulMode, \ - unsigned long ulSubMode, \ - unsigned long ulConfig))ROM_SPITABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDataGetNonBlocking \ - ((long (*)(unsigned long ulBase, \ - unsigned long * pulData))ROM_SPITABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDataGet \ - ((void (*)(unsigned long ulBase, \ - unsigned long *pulData))ROM_SPITABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDataPutNonBlocking \ - ((long (*)(unsigned long ulBase, \ - unsigned long ulData))ROM_SPITABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDataPut \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulData))ROM_SPITABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIFIFOEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulFlags))ROM_SPITABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIFIFODisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulFlags))ROM_SPITABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIFIFOLevelSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTxLevel, \ - unsigned long ulRxLevel))ROM_SPITABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIFIFOLevelGet \ - ((void (*)(unsigned long ulBase, \ - unsigned long *pulTxLevel, \ - unsigned long *pulRxLevel))ROM_SPITABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIWordCountSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulWordCount))ROM_SPITABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIIntRegister \ - ((void (*)(unsigned long ulBase, \ - void(*pfnHandler)(void)))ROM_SPITABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIIntUnregister \ - ((void (*)(unsigned long ulBase))ROM_SPITABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_SPITABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_SPITABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIIntStatus \ - ((unsigned long (*)(unsigned long ulBase, \ - tBoolean bMasked))ROM_SPITABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_SPITABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDmaEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulFlags))ROM_SPITABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPIDmaDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulFlags))ROM_SPITABLE[20]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPICSEnable \ - ((void (*)(unsigned long ulBase))ROM_SPITABLE[21]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPICSDisable \ - ((void (*)(unsigned long ulBase))ROM_SPITABLE[22]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SPITransfer \ - ((long (*)(unsigned long ulBase, \ - unsigned char *ucDout, \ - unsigned char *ucDin, \ - unsigned long ulSize, \ - unsigned long ulFlags))ROM_SPITABLE[23]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the CAM API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraReset \ - ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraParamsConfig \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulHSPol, \ - unsigned long ulVSPol, \ - unsigned long ulFlags))ROM_CAMERATABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraXClkConfig \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulCamClkIn, \ - unsigned long ulXClk))ROM_CAMERATABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraXClkSet \ - ((void (*)(unsigned long ulBase, \ - unsigned char bXClkFlags))ROM_CAMERATABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraDMAEnable \ - ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraDMADisable \ - ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraThresholdSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulThreshold))ROM_CAMERATABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraIntRegister \ - ((void (*)(unsigned long ulBase, \ - void (*pfnHandler)(void)))ROM_CAMERATABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraIntUnregister \ - ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_CAMERATABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_CAMERATABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraIntStatus \ - ((unsigned long (*)(unsigned long ulBase))ROM_CAMERATABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_CAMERATABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraCaptureStop \ - ((void (*)(unsigned long ulBase, \ - tBoolean bImmediate))ROM_CAMERATABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraCaptureStart \ - ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CameraBufferRead \ - ((void (*)(unsigned long ulBase, \ - unsigned long *pBuffer, \ - unsigned char ucSize))ROM_CAMERATABLE[15]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the FLASH API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashDisable \ - ((void (*)(void))ROM_FLASHTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashErase \ - ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashMassErase \ - ((long (*)(void))ROM_FLASHTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashMassEraseNonBlocking \ - ((void (*)(void))ROM_FLASHTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashEraseNonBlocking \ - ((void (*)(unsigned long ulAddress))ROM_FLASHTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashProgram \ - ((long (*)(unsigned long *pulData, \ - unsigned long ulAddress, \ - unsigned long ulCount))ROM_FLASHTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashProgramNonBlocking \ - ((long (*)(unsigned long *pulData, \ - unsigned long ulAddress, \ - unsigned long ulCount))ROM_FLASHTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashIntRegister \ - ((void (*)(void (*pfnHandler)(void)))ROM_FLASHTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashIntUnregister \ - ((void (*)(void))ROM_FLASHTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashIntEnable \ - ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashIntDisable \ - ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashIntStatus \ - ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashIntClear \ - ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_FlashProtectGet \ - ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[13]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Pin API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinModeSet \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinDirModeSet \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinIO))ROM_PINTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinDirModeGet \ - ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinModeGet \ - ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinConfigGet \ - ((void (*)(unsigned long ulPin, \ - unsigned long *pulPinStrength, \ - unsigned long *pulPinType))ROM_PINTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinConfigSet \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinStrength, \ - unsigned long ulPinType))ROM_PINTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeUART \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeI2C \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeSPI \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeI2S \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeTimer \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeCamera \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeGPIO \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode, \ - tBoolean bOpenDrain))ROM_PINTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeADC \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinTypeSDHost \ - ((void (*)(unsigned long ulPin, \ - unsigned long ulPinMode))ROM_PINTABLE[14]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinHysteresisSet \ - ((void (*)(unsigned long ulHysteresis))ROM_PINTABLE[15]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinLockLevelSet \ - ((void (*)(unsigned long ulPin, \ - unsigned char ucLevel))ROM_PINTABLE[16]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinLock \ - ((void (*)(unsigned long ulOutEnable))ROM_PINTABLE[17]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PinUnlock \ - ((void (*)(void))ROM_PINTABLE[18]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SYSTICK API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickEnable \ - ((void (*)(void))ROM_SYSTICKTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickDisable \ - ((void (*)(void))ROM_SYSTICKTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickIntRegister \ - ((void (*)(void (*pfnHandler)(void)))ROM_SYSTICKTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickIntUnregister \ - ((void (*)(void))ROM_SYSTICKTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickIntEnable \ - ((void (*)(void))ROM_SYSTICKTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickIntDisable \ - ((void (*)(void))ROM_SYSTICKTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickPeriodSet \ - ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickPeriodGet \ - ((unsigned long (*)(void))ROM_SYSTICKTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SysTickValueGet \ - ((unsigned long (*)(void))ROM_SYSTICKTABLE[8]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the UTILS API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_UtilsDelay \ - ((void (*)(unsigned long ulCount))ROM_UTILSTABLE[0]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the I2S API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulMode))ROM_I2STABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SDisable \ - ((void (*)(unsigned long ulBase))ROM_I2STABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SDataPut \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulDataLine, \ - unsigned long ulData))ROM_I2STABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SDataPutNonBlocking \ - ((long (*)(unsigned long ulBase, \ - unsigned long ulDataLine, \ - unsigned long ulData))ROM_I2STABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SDataGet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulDataLine, \ - unsigned long *pulData))ROM_I2STABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SDataGetNonBlocking \ - ((long (*)(unsigned long ulBase, \ - unsigned long ulDataLine, \ - unsigned long *pulData))ROM_I2STABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SConfigSetExpClk \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulI2SClk, \ - unsigned long ulBitClk, \ - unsigned long ulConfig))ROM_I2STABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2STxFIFOEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulTxLevel, \ - unsigned long ulWordsPerTransfer))ROM_I2STABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2STxFIFODisable \ - ((void (*)(unsigned long ulBase))ROM_I2STABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SRxFIFOEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulRxLevel, \ - unsigned long ulWordsPerTransfer))ROM_I2STABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SRxFIFODisable \ - ((void (*)(unsigned long ulBase))ROM_I2STABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2STxFIFOStatusGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SRxFIFOStatusGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SSerializerConfig \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulDataLine, \ - unsigned long ulSerMode, \ - unsigned long ulInActState))ROM_I2STABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_I2STABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_I2STABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SIntStatus \ - ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_I2STABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SIntRegister \ - ((void (*)(unsigned long ulBase, \ - void (*pfnHandler)(void)))ROM_I2STABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SIntUnregister \ - ((void (*)(unsigned long ulBase))ROM_I2STABLE[19]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2STxActiveSlotSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulActSlot))ROM_I2STABLE[20]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_I2SRxActiveSlotSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulActSlot))ROM_I2STABLE[21]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the GPIO API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIODirModeSet \ - ((void (*)(unsigned long ulPort, \ - unsigned char ucPins, \ - unsigned long ulPinIO))ROM_GPIOTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIODirModeGet \ - ((unsigned long (*)(unsigned long ulPort, \ - unsigned char ucPin))ROM_GPIOTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntTypeSet \ - ((void (*)(unsigned long ulPort, \ - unsigned char ucPins, \ - unsigned long ulIntType))ROM_GPIOTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIODMATriggerEnable \ - ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIODMATriggerDisable \ - ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntTypeGet \ - ((unsigned long (*)(unsigned long ulPort, \ - unsigned char ucPin))ROM_GPIOTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntEnable \ - ((void (*)(unsigned long ulPort, \ - unsigned long ulIntFlags))ROM_GPIOTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntDisable \ - ((void (*)(unsigned long ulPort, \ - unsigned long ulIntFlags))ROM_GPIOTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntStatus \ - ((long (*)(unsigned long ulPort, \ - tBoolean bMasked))ROM_GPIOTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntClear \ - ((void (*)(unsigned long ulPort, \ - unsigned long ulIntFlags))ROM_GPIOTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntRegister \ - ((void (*)(unsigned long ulPort, \ - void (*pfnIntHandler)(void)))ROM_GPIOTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOIntUnregister \ - ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOPinRead \ - ((long (*)(unsigned long ulPort, \ - unsigned char ucPins))ROM_GPIOTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_GPIOPinWrite \ - ((void (*)(unsigned long ulPort, \ - unsigned char ucPins, \ - unsigned char ucVal))ROM_GPIOTABLE[13]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the AES API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_AESTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESKey1Set \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Key, \ - uint32_t ui32Keysize))ROM_AESTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESKey2Set \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Key, \ - uint32_t ui32Keysize))ROM_AESTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESKey3Set \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Key))ROM_AESTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIVSet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8IVdata))ROM_AESTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESTagRead \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8TagData))ROM_AESTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint64_t ui64Length))ROM_AESTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESAuthDataLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Length))ROM_AESTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataReadNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Dest, \ - uint8_t ui8Length))ROM_AESTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataRead \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Dest, \ - uint8_t ui8Length))ROM_AESTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataWriteNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t ui8Length))ROM_AESTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t ui8Length))ROM_AESTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataProcess \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t *pui8Dest, \ - uint32_t ui32Length))ROM_AESTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataMAC \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint32_t ui32Length, \ - uint8_t *pui8Tag))ROM_AESTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDataProcessAE \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t *pui8Dest, \ - uint32_t ui32Length, \ - uint8_t *pui8AuthSrc, \ - uint32_t ui32AuthLength, \ - uint8_t *pui8Tag))ROM_AESTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_AESTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_AESTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_AESTABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_AESTABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIntRegister \ - ((void (*)(uint32_t ui32Base, \ - void(*pfnHandler)(void)))ROM_AESTABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIntUnregister \ - ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_AESTABLE[21]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_AESTABLE[22]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_AESIVGet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8IVdata))ROM_AESTABLE[23]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the DES API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Config))ROM_DESTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDataRead \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Dest, \ - uint8_t ui8Length))ROM_DESTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDataReadNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Dest, \ - uint8_t ui8Length))ROM_DESTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDataProcess \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t *pui8Dest, \ - uint32_t ui32Length))ROM_DESTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t ui8Length))ROM_DESTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDataWriteNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src, \ - uint8_t ui8Length))ROM_DESTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDMADisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_DESTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDMAEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Flags))ROM_DESTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_DESTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_DESTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_DESTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIntRegister \ - ((void (*)(uint32_t ui32Base, \ - void(*pfnHandler)(void)))ROM_DESTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_DESTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIntUnregister \ - ((void (*)(uint32_t ui32Base))ROM_DESTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESIVSet \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8IVdata))ROM_DESTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESKeySet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Key))ROM_DESTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_DESDataLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Length))ROM_DESTABLE[16]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SHAMD5 API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5ConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Mode))ROM_SHAMD5TABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5DataProcess \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8DataSrc, \ - uint32_t ui32DataLength, \ - uint8_t *pui8HashResult))ROM_SHAMD5TABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5DataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Src))ROM_SHAMD5TABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5DataWriteNonBlocking \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8Src))ROM_SHAMD5TABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5DMADisable \ - ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5DMAEnable \ - ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5DataLengthSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Length))ROM_SHAMD5TABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5HMACKeySet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Src))ROM_SHAMD5TABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5HMACPPKeyGenerate \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Key, \ - uint8_t *pui8PPKey))ROM_SHAMD5TABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5HMACPPKeySet \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Src))ROM_SHAMD5TABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5HMACProcess \ - ((bool (*)(uint32_t ui32Base, \ - uint8_t *pui8DataSrc, \ - uint32_t ui32DataLength, \ - uint8_t *pui8HashResult))ROM_SHAMD5TABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5IntClear \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SHAMD5TABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5IntDisable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5IntEnable \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5IntRegister \ - ((void (*)(uint32_t ui32Base, \ - void(*pfnHandler)(void)))ROM_SHAMD5TABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5IntStatus \ - ((uint32_t (*)(uint32_t ui32Base, \ - bool bMasked))ROM_SHAMD5TABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5IntUnregister \ - ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SHAMD5ResultRead \ - ((void (*)(uint32_t ui32Base, \ - uint8_t *pui8Dest))ROM_SHAMD5TABLE[17]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the CRC API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CRCConfigSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32CRCConfig))ROM_CRCTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CRCDataProcess \ - ((uint32_t (*)(uint32_t ui32Base, \ - void *puiDataIn, \ - uint32_t ui32DataLength, \ - uint32_t ui32Config))ROM_CRCTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CRCDataWrite \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Data))ROM_CRCTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CRCResultRead \ - ((uint32_t (*)(uint32_t ui32Base))ROM_CRCTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_CRCSeedSet \ - ((void (*)(uint32_t ui32Base, \ - uint32_t ui32Seed))ROM_CRCTABLE[4]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SDHOST API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostCmdReset \ - ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostInit \ - ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostCmdSend \ - ((long (*)(unsigned long ulBase, \ - unsigned long ulCmd, \ - unsigned ulArg))ROM_SDHOSTTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostIntRegister \ - ((void (*)(unsigned long ulBase, \ - void (*pfnHandler)(void)))ROM_SDHOSTTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostIntUnregister \ - ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_SDHOSTTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_SDHOSTTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostIntStatus \ - ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulIntFlags))ROM_SDHOSTTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostRespGet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulRespnse[4]))ROM_SDHOSTTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostBlockSizeSet \ - ((void (*)(unsigned long ulBase, \ - unsigned short ulBlkSize))ROM_SDHOSTTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostBlockCountSet \ - ((void (*)(unsigned long ulBase, \ - unsigned short ulBlkCount))ROM_SDHOSTTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostDataNonBlockingWrite \ - ((tBoolean (*)(unsigned long ulBase, \ - unsigned long ulData))ROM_SDHOSTTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostDataNonBlockingRead \ - ((tBoolean (*)(unsigned long ulBase, \ - unsigned long *pulData))ROM_SDHOSTTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostDataWrite \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulData))ROM_SDHOSTTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostDataRead \ - ((void (*)(unsigned long ulBase, \ - unsigned long *ulData))ROM_SDHOSTTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostSetExpClk \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulSDHostClk, \ - unsigned long ulCardClk))ROM_SDHOSTTABLE[17]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostCardErrorMaskSet \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulErrMask))ROM_SDHOSTTABLE[18]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_SDHostCardErrorMaskGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[19]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the PRCM API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMMCUReset \ - ((void (*)(tBoolean bIncludeSubsystem))ROM_PRCMTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSysResetCauseGet \ - ((unsigned long (*)(void))ROM_PRCMTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMPeripheralClkEnable \ - ((void (*)(unsigned long ulPeripheral, \ - unsigned long ulClkFlags))ROM_PRCMTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMPeripheralClkDisable \ - ((void (*)(unsigned long ulPeripheral, \ - unsigned long ulClkFlags))ROM_PRCMTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMPeripheralReset \ - ((void (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMPeripheralStatusGet \ - ((tBoolean (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMI2SClockFreqSet \ - ((void (*)(unsigned long ulI2CClkFreq))ROM_PRCMTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMPeripheralClockGet \ - ((unsigned long (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSleepEnter \ - ((void (*)(void))ROM_PRCMTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSRAMRetentionEnable \ - ((void (*)(unsigned long ulSramColSel, \ - unsigned long ulFlags))ROM_PRCMTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSRAMRetentionDisable \ - ((void (*)(unsigned long ulSramColSel, \ - unsigned long ulFlags))ROM_PRCMTABLE[12]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSEnter \ - ((void (*)(void))ROM_PRCMTABLE[13]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSIntervalSet \ - ((void (*)(unsigned long ulTicks))ROM_PRCMTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSWakeupSourceEnable \ - ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSWakeupCauseGet \ - ((unsigned long (*)(void))ROM_PRCMTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSWakeUpGPIOSelect \ - ((void (*)(unsigned long ulGPIOPin, \ - unsigned long ulType))ROM_PRCMTABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSWakeupSourceDisable \ - ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateEnter \ - ((void (*)(void))ROM_PRCMTABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateWakeupSourceEnable \ - ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[20]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateWakeupCauseGet \ - ((unsigned long (*)(void))ROM_PRCMTABLE[21]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateWakeUpGPIOSelect \ - ((void (*)(unsigned long ulMultiGPIOBitMap, \ - unsigned long ulType))ROM_PRCMTABLE[22]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateWakeupSourceDisable \ - ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[23]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateIntervalSet \ - ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[24]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSlowClkCtrGet \ - ((unsigned long long (*)(void))ROM_PRCMTABLE[25]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSlowClkCtrMatchSet \ - ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[26]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSlowClkCtrMatchGet \ - ((unsigned long long (*)(void))ROM_PRCMTABLE[27]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMOCRRegisterWrite \ - ((void (*)(unsigned char ucIndex, \ - unsigned long ulRegValue))ROM_PRCMTABLE[28]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMOCRRegisterRead \ - ((unsigned long (*)(unsigned char ucIndex))ROM_PRCMTABLE[29]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIntRegister \ - ((void (*)(void (*pfnHandler)(void)))ROM_PRCMTABLE[30]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIntUnregister \ - ((void (*)(void))ROM_PRCMTABLE[31]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIntEnable \ - ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[32]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIntDisable \ - ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[33]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIntStatus \ - ((unsigned long (*)(void))ROM_PRCMTABLE[34]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMRTCInUseSet \ - ((void (*)(void))ROM_PRCMTABLE[35]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMRTCInUseGet \ - ((tBoolean (*)(void))ROM_PRCMTABLE[36]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMRTCSet \ - ((void (*)(unsigned long ulSecs, \ - unsigned short usMsec))ROM_PRCMTABLE[37]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMRTCGet \ - ((void (*)(unsigned long *ulSecs, \ - unsigned short *usMsec))ROM_PRCMTABLE[38]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMRTCMatchSet \ - ((void (*)(unsigned long ulSecs, \ - unsigned short usMsec))ROM_PRCMTABLE[39]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMRTCMatchGet \ - ((void (*)(unsigned long *ulSecs, \ - unsigned short *usMsec))ROM_PRCMTABLE[40]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSRestoreInfoSet \ - ((void (*)(unsigned long ulRestoreSP, \ - unsigned long ulRestorePC))ROM_PRCMTABLE[41]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMSlowClkCtrFastGet \ - ((unsigned long long (*)(void))ROM_PRCMTABLE[42]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMCC3200MCUInit \ - ((void (*)(void))ROM_PRCMTABLE[43]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHIBRegRead \ - ((unsigned long (*)(unsigned long ulRegAddr))ROM_PRCMTABLE[44]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHIBRegWrite \ - ((void (*)(unsigned long ulRegAddr, \ - unsigned long ulValue))ROM_PRCMTABLE[45]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMCameraFreqSet \ - ((unsigned long (*)(unsigned char ulDivider, \ - unsigned char ulWidth))ROM_PRCMTABLE[46]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIORetentionEnable \ - ((void (*)(unsigned long ulIORetGrpFlags))ROM_PRCMTABLE[47]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMIORetentionDisable \ - ((void (*)(unsigned long ulIORetGrpFlags))ROM_PRCMTABLE[48]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMDeviceTypeGet \ - ((unsigned long (*)(void))ROM_PRCMTABLE[49]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMLPDSEnterKeepDebugIf \ - ((void (*)(void))ROM_PRCMTABLE[50]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_PRCMHibernateCycleTrigger \ - ((void (*)(void))ROM_PRCMTABLE[51]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the HWSPINLOCK API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_HwSpinLockAcquire \ - ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_HwSpinLockTryAcquire \ - ((int32_t (*)(uint32_t ui32LockID, \ - uint32_t ui32Retry))ROM_HWSPINLOCKTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_HwSpinLockRelease \ - ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_HwSpinLockTest \ - ((uint32_t (*)(uint32_t ui32LockID, \ - bool bCurrentStatus))ROM_HWSPINLOCKTABLE[3]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the ADC API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCEnable \ - ((void (*)(unsigned long ulBase))ROM_ADCTABLE[0]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCDisable \ - ((void (*)(unsigned long ulBase))ROM_ADCTABLE[1]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCChannelEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[2]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCChannelDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[3]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCIntRegister \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel, \ - void (*pfnHandler)(void)))ROM_ADCTABLE[4]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCIntUnregister \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[5]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCIntEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel, \ - unsigned long ulIntFlags))ROM_ADCTABLE[6]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCIntDisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel, \ - unsigned long ulIntFlags))ROM_ADCTABLE[7]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCIntStatus \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[8]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCIntClear \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel, \ - unsigned long ulIntFlags))ROM_ADCTABLE[9]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCDMAEnable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[10]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCDMADisable \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[11]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCTimerConfig \ - ((void (*)(unsigned long ulBase, \ - unsigned long ulValue))ROM_ADCTABLE[14]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCTimerEnable \ - ((void (*)(unsigned long ulBase))ROM_ADCTABLE[15]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCTimerDisable \ - ((void (*)(unsigned long ulBase))ROM_ADCTABLE[16]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCTimerReset \ - ((void (*)(unsigned long ulBase))ROM_ADCTABLE[17]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCTimerValueGet \ - ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[18]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCFIFOLvlGet \ - ((unsigned char (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[19]) -#endif -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define ROM_ADCFIFORead \ - ((unsigned long (*)(unsigned long ulBase, \ - unsigned long ulChannel))ROM_ADCTABLE[20]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the CPU API. -// -//***************************************************************************** -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_CPUcpsid \ - ((unsigned long (*)(void))ROM_CPUTABLE[0]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_CPUcpsie \ - ((unsigned long (*)(void))ROM_CPUTABLE[1]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_CPUprimask \ - ((unsigned long (*)(void))ROM_CPUTABLE[2]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_CPUwfi \ - ((void (*)(void))ROM_CPUTABLE[3]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_CPUbasepriGet \ - ((unsigned long (*)(void))ROM_CPUTABLE[4]) -#endif -#if defined(USE_CC3220_ROM_DRV_API) -#define ROM_CPUbasepriSet \ - ((void (*)(unsigned long ulNewBasepri))ROM_CPUTABLE[5]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions Directly. -// -//***************************************************************************** -#define ROM_UtilsDelayDirect \ - ((void (*)(unsigned long ulCount))ROM_UTILSTABLE[0]) - -#define ROM_PRCMLPDSEnterDirect \ - ((void (*)(void))ROM_PRCMTABLE[13]) - -#define ROM_PRCMLPDSEnterKeepDebugIfDirect \ - ((void (*)(void))ROM_PRCMTABLE[50]) - -#endif // __ROM_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/rom_map.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/rom_map.h deleted file mode 100644 index cb2e07e1fc5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/rom_map.h +++ /dev/null @@ -1,3321 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// rom_map.h - Macros to facilitate calling functions in the ROM when they are -// available. -// -//***************************************************************************** -//***************************************************************************** -// -// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND. -// -//***************************************************************************** - -#ifndef __ROM_MAP_H__ -#define __ROM_MAP_H__ - -//***************************************************************************** -// Patched ROM APIs -//***************************************************************************** -#include "rom_patch.h" - -//***************************************************************************** -// -// Macros for the Interrupt API. -// -//***************************************************************************** -#ifdef ROM_IntEnable -#define MAP_IntEnable \ - ROM_IntEnable -#else -#define MAP_IntEnable \ - IntEnable -#endif -#ifdef ROM_IntMasterEnable -#define MAP_IntMasterEnable \ - ROM_IntMasterEnable -#else -#define MAP_IntMasterEnable \ - IntMasterEnable -#endif -#ifdef ROM_IntMasterDisable -#define MAP_IntMasterDisable \ - ROM_IntMasterDisable -#else -#define MAP_IntMasterDisable \ - IntMasterDisable -#endif -#ifdef ROM_IntDisable -#define MAP_IntDisable \ - ROM_IntDisable -#else -#define MAP_IntDisable \ - IntDisable -#endif -#ifdef ROM_IntPriorityGroupingSet -#define MAP_IntPriorityGroupingSet \ - ROM_IntPriorityGroupingSet -#else -#define MAP_IntPriorityGroupingSet \ - IntPriorityGroupingSet -#endif -#ifdef ROM_IntPriorityGroupingGet -#define MAP_IntPriorityGroupingGet \ - ROM_IntPriorityGroupingGet -#else -#define MAP_IntPriorityGroupingGet \ - IntPriorityGroupingGet -#endif -#ifdef ROM_IntPrioritySet -#define MAP_IntPrioritySet \ - ROM_IntPrioritySet -#else -#define MAP_IntPrioritySet \ - IntPrioritySet -#endif -#ifdef ROM_IntPriorityGet -#define MAP_IntPriorityGet \ - ROM_IntPriorityGet -#else -#define MAP_IntPriorityGet \ - IntPriorityGet -#endif -#ifdef ROM_IntPendSet -#define MAP_IntPendSet \ - ROM_IntPendSet -#else -#define MAP_IntPendSet \ - IntPendSet -#endif -#ifdef ROM_IntPendClear -#define MAP_IntPendClear \ - ROM_IntPendClear -#else -#define MAP_IntPendClear \ - IntPendClear -#endif -#ifdef ROM_IntPriorityMaskSet -#define MAP_IntPriorityMaskSet \ - ROM_IntPriorityMaskSet -#else -#define MAP_IntPriorityMaskSet \ - IntPriorityMaskSet -#endif -#ifdef ROM_IntPriorityMaskGet -#define MAP_IntPriorityMaskGet \ - ROM_IntPriorityMaskGet -#else -#define MAP_IntPriorityMaskGet \ - IntPriorityMaskGet -#endif -#ifdef ROM_IntRegister -#define MAP_IntRegister \ - ROM_IntRegister -#else -#define MAP_IntRegister \ - IntRegister -#endif -#ifdef ROM_IntUnregister -#define MAP_IntUnregister \ - ROM_IntUnregister -#else -#define MAP_IntUnregister \ - IntUnregister -#endif -#ifdef ROM_IntVTableBaseSet -#define MAP_IntVTableBaseSet \ - ROM_IntVTableBaseSet -#else -#define MAP_IntVTableBaseSet \ - IntVTableBaseSet -#endif - -//***************************************************************************** -// -// Macros for the Timer API. -// -//***************************************************************************** -#ifdef ROM_TimerEnable -#define MAP_TimerEnable \ - ROM_TimerEnable -#else -#define MAP_TimerEnable \ - TimerEnable -#endif -#ifdef ROM_TimerDisable -#define MAP_TimerDisable \ - ROM_TimerDisable -#else -#define MAP_TimerDisable \ - TimerDisable -#endif -#ifdef ROM_TimerConfigure -#define MAP_TimerConfigure \ - ROM_TimerConfigure -#else -#define MAP_TimerConfigure \ - TimerConfigure -#endif -#ifdef ROM_TimerControlLevel -#define MAP_TimerControlLevel \ - ROM_TimerControlLevel -#else -#define MAP_TimerControlLevel \ - TimerControlLevel -#endif -#ifdef ROM_TimerControlEvent -#define MAP_TimerControlEvent \ - ROM_TimerControlEvent -#else -#define MAP_TimerControlEvent \ - TimerControlEvent -#endif -#ifdef ROM_TimerControlStall -#define MAP_TimerControlStall \ - ROM_TimerControlStall -#else -#define MAP_TimerControlStall \ - TimerControlStall -#endif -#ifdef ROM_TimerPrescaleSet -#define MAP_TimerPrescaleSet \ - ROM_TimerPrescaleSet -#else -#define MAP_TimerPrescaleSet \ - TimerPrescaleSet -#endif -#ifdef ROM_TimerPrescaleGet -#define MAP_TimerPrescaleGet \ - ROM_TimerPrescaleGet -#else -#define MAP_TimerPrescaleGet \ - TimerPrescaleGet -#endif -#ifdef ROM_TimerPrescaleMatchSet -#define MAP_TimerPrescaleMatchSet \ - ROM_TimerPrescaleMatchSet -#else -#define MAP_TimerPrescaleMatchSet \ - TimerPrescaleMatchSet -#endif -#ifdef ROM_TimerPrescaleMatchGet -#define MAP_TimerPrescaleMatchGet \ - ROM_TimerPrescaleMatchGet -#else -#define MAP_TimerPrescaleMatchGet \ - TimerPrescaleMatchGet -#endif -#ifdef ROM_TimerLoadSet -#define MAP_TimerLoadSet \ - ROM_TimerLoadSet -#else -#define MAP_TimerLoadSet \ - TimerLoadSet -#endif -#ifdef ROM_TimerLoadGet -#define MAP_TimerLoadGet \ - ROM_TimerLoadGet -#else -#define MAP_TimerLoadGet \ - TimerLoadGet -#endif -#ifdef ROM_TimerValueGet -#define MAP_TimerValueGet \ - ROM_TimerValueGet -#else -#define MAP_TimerValueGet \ - TimerValueGet -#endif -#ifdef ROM_TimerMatchSet -#define MAP_TimerMatchSet \ - ROM_TimerMatchSet -#else -#define MAP_TimerMatchSet \ - TimerMatchSet -#endif -#ifdef ROM_TimerMatchGet -#define MAP_TimerMatchGet \ - ROM_TimerMatchGet -#else -#define MAP_TimerMatchGet \ - TimerMatchGet -#endif -#ifdef ROM_TimerIntRegister -#define MAP_TimerIntRegister \ - ROM_TimerIntRegister -#else -#define MAP_TimerIntRegister \ - TimerIntRegister -#endif -#ifdef ROM_TimerIntUnregister -#define MAP_TimerIntUnregister \ - ROM_TimerIntUnregister -#else -#define MAP_TimerIntUnregister \ - TimerIntUnregister -#endif -#ifdef ROM_TimerIntEnable -#define MAP_TimerIntEnable \ - ROM_TimerIntEnable -#else -#define MAP_TimerIntEnable \ - TimerIntEnable -#endif -#ifdef ROM_TimerIntDisable -#define MAP_TimerIntDisable \ - ROM_TimerIntDisable -#else -#define MAP_TimerIntDisable \ - TimerIntDisable -#endif -#ifdef ROM_TimerIntStatus -#define MAP_TimerIntStatus \ - ROM_TimerIntStatus -#else -#define MAP_TimerIntStatus \ - TimerIntStatus -#endif -#ifdef ROM_TimerIntClear -#define MAP_TimerIntClear \ - ROM_TimerIntClear -#else -#define MAP_TimerIntClear \ - TimerIntClear -#endif -#ifdef ROM_TimerValueSet -#define MAP_TimerValueSet \ - ROM_TimerValueSet -#else -#define MAP_TimerValueSet \ - TimerValueSet -#endif -#ifdef ROM_TimerDMAEventSet -#define MAP_TimerDMAEventSet \ - ROM_TimerDMAEventSet -#else -#define MAP_TimerDMAEventSet \ - TimerDMAEventSet -#endif -#ifdef ROM_TimerDMAEventGet -#define MAP_TimerDMAEventGet \ - ROM_TimerDMAEventGet -#else -#define MAP_TimerDMAEventGet \ - TimerDMAEventGet -#endif - -//***************************************************************************** -// -// Macros for the UART API. -// -//***************************************************************************** -#ifdef ROM_UARTParityModeSet -#define MAP_UARTParityModeSet \ - ROM_UARTParityModeSet -#else -#define MAP_UARTParityModeSet \ - UARTParityModeSet -#endif -#ifdef ROM_UARTParityModeGet -#define MAP_UARTParityModeGet \ - ROM_UARTParityModeGet -#else -#define MAP_UARTParityModeGet \ - UARTParityModeGet -#endif -#ifdef ROM_UARTFIFOLevelSet -#define MAP_UARTFIFOLevelSet \ - ROM_UARTFIFOLevelSet -#else -#define MAP_UARTFIFOLevelSet \ - UARTFIFOLevelSet -#endif -#ifdef ROM_UARTFIFOLevelGet -#define MAP_UARTFIFOLevelGet \ - ROM_UARTFIFOLevelGet -#else -#define MAP_UARTFIFOLevelGet \ - UARTFIFOLevelGet -#endif -#ifdef ROM_UARTConfigSetExpClk -#define MAP_UARTConfigSetExpClk \ - ROM_UARTConfigSetExpClk -#else -#define MAP_UARTConfigSetExpClk \ - UARTConfigSetExpClk -#endif -#ifdef ROM_UARTConfigGetExpClk -#define MAP_UARTConfigGetExpClk \ - ROM_UARTConfigGetExpClk -#else -#define MAP_UARTConfigGetExpClk \ - UARTConfigGetExpClk -#endif -#ifdef ROM_UARTEnable -#define MAP_UARTEnable \ - ROM_UARTEnable -#else -#define MAP_UARTEnable \ - UARTEnable -#endif -#ifdef ROM_UARTDisable -#define MAP_UARTDisable \ - ROM_UARTDisable -#else -#define MAP_UARTDisable \ - UARTDisable -#endif -#ifdef ROM_UARTFIFOEnable -#define MAP_UARTFIFOEnable \ - ROM_UARTFIFOEnable -#else -#define MAP_UARTFIFOEnable \ - UARTFIFOEnable -#endif -#ifdef ROM_UARTFIFODisable -#define MAP_UARTFIFODisable \ - ROM_UARTFIFODisable -#else -#define MAP_UARTFIFODisable \ - UARTFIFODisable -#endif -#ifdef ROM_UARTCharsAvail -#define MAP_UARTCharsAvail \ - ROM_UARTCharsAvail -#else -#define MAP_UARTCharsAvail \ - UARTCharsAvail -#endif -#ifdef ROM_UARTSpaceAvail -#define MAP_UARTSpaceAvail \ - ROM_UARTSpaceAvail -#else -#define MAP_UARTSpaceAvail \ - UARTSpaceAvail -#endif -#ifdef ROM_UARTCharGetNonBlocking -#define MAP_UARTCharGetNonBlocking \ - ROM_UARTCharGetNonBlocking -#else -#define MAP_UARTCharGetNonBlocking \ - UARTCharGetNonBlocking -#endif -#ifdef ROM_UARTCharGet -#define MAP_UARTCharGet \ - ROM_UARTCharGet -#else -#define MAP_UARTCharGet \ - UARTCharGet -#endif -#ifdef ROM_UARTCharPutNonBlocking -#define MAP_UARTCharPutNonBlocking \ - ROM_UARTCharPutNonBlocking -#else -#define MAP_UARTCharPutNonBlocking \ - UARTCharPutNonBlocking -#endif -#ifdef ROM_UARTCharPut -#define MAP_UARTCharPut \ - ROM_UARTCharPut -#else -#define MAP_UARTCharPut \ - UARTCharPut -#endif -#ifdef ROM_UARTBreakCtl -#define MAP_UARTBreakCtl \ - ROM_UARTBreakCtl -#else -#define MAP_UARTBreakCtl \ - UARTBreakCtl -#endif -#ifdef ROM_UARTBusy -#define MAP_UARTBusy \ - ROM_UARTBusy -#else -#define MAP_UARTBusy \ - UARTBusy -#endif -#ifdef ROM_UARTIntRegister -#define MAP_UARTIntRegister \ - ROM_UARTIntRegister -#else -#define MAP_UARTIntRegister \ - UARTIntRegister -#endif -#ifdef ROM_UARTIntUnregister -#define MAP_UARTIntUnregister \ - ROM_UARTIntUnregister -#else -#define MAP_UARTIntUnregister \ - UARTIntUnregister -#endif -#ifdef ROM_UARTIntEnable -#define MAP_UARTIntEnable \ - ROM_UARTIntEnable -#else -#define MAP_UARTIntEnable \ - UARTIntEnable -#endif -#ifdef ROM_UARTIntDisable -#define MAP_UARTIntDisable \ - ROM_UARTIntDisable -#else -#define MAP_UARTIntDisable \ - UARTIntDisable -#endif -#ifdef ROM_UARTIntStatus -#define MAP_UARTIntStatus \ - ROM_UARTIntStatus -#else -#define MAP_UARTIntStatus \ - UARTIntStatus -#endif -#ifdef ROM_UARTIntClear -#define MAP_UARTIntClear \ - ROM_UARTIntClear -#else -#define MAP_UARTIntClear \ - UARTIntClear -#endif -#ifdef ROM_UARTDMAEnable -#define MAP_UARTDMAEnable \ - ROM_UARTDMAEnable -#else -#define MAP_UARTDMAEnable \ - UARTDMAEnable -#endif -#ifdef ROM_UARTDMADisable -#define MAP_UARTDMADisable \ - ROM_UARTDMADisable -#else -#define MAP_UARTDMADisable \ - UARTDMADisable -#endif -#ifdef ROM_UARTRxErrorGet -#define MAP_UARTRxErrorGet \ - ROM_UARTRxErrorGet -#else -#define MAP_UARTRxErrorGet \ - UARTRxErrorGet -#endif -#ifdef ROM_UARTRxErrorClear -#define MAP_UARTRxErrorClear \ - ROM_UARTRxErrorClear -#else -#define MAP_UARTRxErrorClear \ - UARTRxErrorClear -#endif -#ifdef ROM_UARTModemControlSet -#define MAP_UARTModemControlSet \ - ROM_UARTModemControlSet -#else -#define MAP_UARTModemControlSet \ - UARTModemControlSet -#endif -#ifdef ROM_UARTModemControlClear -#define MAP_UARTModemControlClear \ - ROM_UARTModemControlClear -#else -#define MAP_UARTModemControlClear \ - UARTModemControlClear -#endif -#ifdef ROM_UARTModemControlGet -#define MAP_UARTModemControlGet \ - ROM_UARTModemControlGet -#else -#define MAP_UARTModemControlGet \ - UARTModemControlGet -#endif -#ifdef ROM_UARTModemStatusGet -#define MAP_UARTModemStatusGet \ - ROM_UARTModemStatusGet -#else -#define MAP_UARTModemStatusGet \ - UARTModemStatusGet -#endif -#ifdef ROM_UARTFlowControlSet -#define MAP_UARTFlowControlSet \ - ROM_UARTFlowControlSet -#else -#define MAP_UARTFlowControlSet \ - UARTFlowControlSet -#endif -#ifdef ROM_UARTFlowControlGet -#define MAP_UARTFlowControlGet \ - ROM_UARTFlowControlGet -#else -#define MAP_UARTFlowControlGet \ - UARTFlowControlGet -#endif -#ifdef ROM_UARTTxIntModeSet -#define MAP_UARTTxIntModeSet \ - ROM_UARTTxIntModeSet -#else -#define MAP_UARTTxIntModeSet \ - UARTTxIntModeSet -#endif -#ifdef ROM_UARTTxIntModeGet -#define MAP_UARTTxIntModeGet \ - ROM_UARTTxIntModeGet -#else -#define MAP_UARTTxIntModeGet \ - UARTTxIntModeGet -#endif - -//***************************************************************************** -// -// Macros for the uDMA API. -// -//***************************************************************************** -#ifdef ROM_uDMAChannelTransferSet -#define MAP_uDMAChannelTransferSet \ - ROM_uDMAChannelTransferSet -#else -#define MAP_uDMAChannelTransferSet \ - uDMAChannelTransferSet -#endif -#ifdef ROM_uDMAEnable -#define MAP_uDMAEnable \ - ROM_uDMAEnable -#else -#define MAP_uDMAEnable \ - uDMAEnable -#endif -#ifdef ROM_uDMADisable -#define MAP_uDMADisable \ - ROM_uDMADisable -#else -#define MAP_uDMADisable \ - uDMADisable -#endif -#ifdef ROM_uDMAErrorStatusGet -#define MAP_uDMAErrorStatusGet \ - ROM_uDMAErrorStatusGet -#else -#define MAP_uDMAErrorStatusGet \ - uDMAErrorStatusGet -#endif -#ifdef ROM_uDMAErrorStatusClear -#define MAP_uDMAErrorStatusClear \ - ROM_uDMAErrorStatusClear -#else -#define MAP_uDMAErrorStatusClear \ - uDMAErrorStatusClear -#endif -#ifdef ROM_uDMAChannelEnable -#define MAP_uDMAChannelEnable \ - ROM_uDMAChannelEnable -#else -#define MAP_uDMAChannelEnable \ - uDMAChannelEnable -#endif -#ifdef ROM_uDMAChannelDisable -#define MAP_uDMAChannelDisable \ - ROM_uDMAChannelDisable -#else -#define MAP_uDMAChannelDisable \ - uDMAChannelDisable -#endif -#ifdef ROM_uDMAChannelIsEnabled -#define MAP_uDMAChannelIsEnabled \ - ROM_uDMAChannelIsEnabled -#else -#define MAP_uDMAChannelIsEnabled \ - uDMAChannelIsEnabled -#endif -#ifdef ROM_uDMAControlBaseSet -#define MAP_uDMAControlBaseSet \ - ROM_uDMAControlBaseSet -#else -#define MAP_uDMAControlBaseSet \ - uDMAControlBaseSet -#endif -#ifdef ROM_uDMAControlBaseGet -#define MAP_uDMAControlBaseGet \ - ROM_uDMAControlBaseGet -#else -#define MAP_uDMAControlBaseGet \ - uDMAControlBaseGet -#endif -#ifdef ROM_uDMAChannelRequest -#define MAP_uDMAChannelRequest \ - ROM_uDMAChannelRequest -#else -#define MAP_uDMAChannelRequest \ - uDMAChannelRequest -#endif -#ifdef ROM_uDMAChannelAttributeEnable -#define MAP_uDMAChannelAttributeEnable \ - ROM_uDMAChannelAttributeEnable -#else -#define MAP_uDMAChannelAttributeEnable \ - uDMAChannelAttributeEnable -#endif -#ifdef ROM_uDMAChannelAttributeDisable -#define MAP_uDMAChannelAttributeDisable \ - ROM_uDMAChannelAttributeDisable -#else -#define MAP_uDMAChannelAttributeDisable \ - uDMAChannelAttributeDisable -#endif -#ifdef ROM_uDMAChannelAttributeGet -#define MAP_uDMAChannelAttributeGet \ - ROM_uDMAChannelAttributeGet -#else -#define MAP_uDMAChannelAttributeGet \ - uDMAChannelAttributeGet -#endif -#ifdef ROM_uDMAChannelControlSet -#define MAP_uDMAChannelControlSet \ - ROM_uDMAChannelControlSet -#else -#define MAP_uDMAChannelControlSet \ - uDMAChannelControlSet -#endif -#ifdef ROM_uDMAChannelSizeGet -#define MAP_uDMAChannelSizeGet \ - ROM_uDMAChannelSizeGet -#else -#define MAP_uDMAChannelSizeGet \ - uDMAChannelSizeGet -#endif -#ifdef ROM_uDMAChannelModeGet -#define MAP_uDMAChannelModeGet \ - ROM_uDMAChannelModeGet -#else -#define MAP_uDMAChannelModeGet \ - uDMAChannelModeGet -#endif -#ifdef ROM_uDMAIntStatus -#define MAP_uDMAIntStatus \ - ROM_uDMAIntStatus -#else -#define MAP_uDMAIntStatus \ - uDMAIntStatus -#endif -#ifdef ROM_uDMAIntClear -#define MAP_uDMAIntClear \ - ROM_uDMAIntClear -#else -#define MAP_uDMAIntClear \ - uDMAIntClear -#endif -#ifdef ROM_uDMAControlAlternateBaseGet -#define MAP_uDMAControlAlternateBaseGet \ - ROM_uDMAControlAlternateBaseGet -#else -#define MAP_uDMAControlAlternateBaseGet \ - uDMAControlAlternateBaseGet -#endif -#ifdef ROM_uDMAChannelScatterGatherSet -#define MAP_uDMAChannelScatterGatherSet \ - ROM_uDMAChannelScatterGatherSet -#else -#define MAP_uDMAChannelScatterGatherSet \ - uDMAChannelScatterGatherSet -#endif -#ifdef ROM_uDMAChannelAssign -#define MAP_uDMAChannelAssign \ - ROM_uDMAChannelAssign -#else -#define MAP_uDMAChannelAssign \ - uDMAChannelAssign -#endif -#ifdef ROM_uDMAIntRegister -#define MAP_uDMAIntRegister \ - ROM_uDMAIntRegister -#else -#define MAP_uDMAIntRegister \ - uDMAIntRegister -#endif -#ifdef ROM_uDMAIntUnregister -#define MAP_uDMAIntUnregister \ - ROM_uDMAIntUnregister -#else -#define MAP_uDMAIntUnregister \ - uDMAIntUnregister -#endif - -//***************************************************************************** -// -// Macros for the Watchdog API. -// -//***************************************************************************** -#ifdef ROM_WatchdogIntClear -#define MAP_WatchdogIntClear \ - ROM_WatchdogIntClear -#else -#define MAP_WatchdogIntClear \ - WatchdogIntClear -#endif -#ifdef ROM_WatchdogRunning -#define MAP_WatchdogRunning \ - ROM_WatchdogRunning -#else -#define MAP_WatchdogRunning \ - WatchdogRunning -#endif -#ifdef ROM_WatchdogEnable -#define MAP_WatchdogEnable \ - ROM_WatchdogEnable -#else -#define MAP_WatchdogEnable \ - WatchdogEnable -#endif -#ifdef ROM_WatchdogLock -#define MAP_WatchdogLock \ - ROM_WatchdogLock -#else -#define MAP_WatchdogLock \ - WatchdogLock -#endif -#ifdef ROM_WatchdogUnlock -#define MAP_WatchdogUnlock \ - ROM_WatchdogUnlock -#else -#define MAP_WatchdogUnlock \ - WatchdogUnlock -#endif -#ifdef ROM_WatchdogLockState -#define MAP_WatchdogLockState \ - ROM_WatchdogLockState -#else -#define MAP_WatchdogLockState \ - WatchdogLockState -#endif -#ifdef ROM_WatchdogReloadSet -#define MAP_WatchdogReloadSet \ - ROM_WatchdogReloadSet -#else -#define MAP_WatchdogReloadSet \ - WatchdogReloadSet -#endif -#ifdef ROM_WatchdogReloadGet -#define MAP_WatchdogReloadGet \ - ROM_WatchdogReloadGet -#else -#define MAP_WatchdogReloadGet \ - WatchdogReloadGet -#endif -#ifdef ROM_WatchdogValueGet -#define MAP_WatchdogValueGet \ - ROM_WatchdogValueGet -#else -#define MAP_WatchdogValueGet \ - WatchdogValueGet -#endif -#ifdef ROM_WatchdogIntStatus -#define MAP_WatchdogIntStatus \ - ROM_WatchdogIntStatus -#else -#define MAP_WatchdogIntStatus \ - WatchdogIntStatus -#endif -#ifdef ROM_WatchdogStallEnable -#define MAP_WatchdogStallEnable \ - ROM_WatchdogStallEnable -#else -#define MAP_WatchdogStallEnable \ - WatchdogStallEnable -#endif -#ifdef ROM_WatchdogStallDisable -#define MAP_WatchdogStallDisable \ - ROM_WatchdogStallDisable -#else -#define MAP_WatchdogStallDisable \ - WatchdogStallDisable -#endif -#ifdef ROM_WatchdogIntRegister -#define MAP_WatchdogIntRegister \ - ROM_WatchdogIntRegister -#else -#define MAP_WatchdogIntRegister \ - WatchdogIntRegister -#endif -#ifdef ROM_WatchdogIntUnregister -#define MAP_WatchdogIntUnregister \ - ROM_WatchdogIntUnregister -#else -#define MAP_WatchdogIntUnregister \ - WatchdogIntUnregister -#endif - -//***************************************************************************** -// -// Macros for the I2C API. -// -//***************************************************************************** -#ifdef ROM_I2CIntRegister -#define MAP_I2CIntRegister \ - ROM_I2CIntRegister -#else -#define MAP_I2CIntRegister \ - I2CIntRegister -#endif -#ifdef ROM_I2CIntUnregister -#define MAP_I2CIntUnregister \ - ROM_I2CIntUnregister -#else -#define MAP_I2CIntUnregister \ - I2CIntUnregister -#endif -#ifdef ROM_I2CTxFIFOConfigSet -#define MAP_I2CTxFIFOConfigSet \ - ROM_I2CTxFIFOConfigSet -#else -#define MAP_I2CTxFIFOConfigSet \ - I2CTxFIFOConfigSet -#endif -#ifdef ROM_I2CTxFIFOFlush -#define MAP_I2CTxFIFOFlush \ - ROM_I2CTxFIFOFlush -#else -#define MAP_I2CTxFIFOFlush \ - I2CTxFIFOFlush -#endif -#ifdef ROM_I2CRxFIFOConfigSet -#define MAP_I2CRxFIFOConfigSet \ - ROM_I2CRxFIFOConfigSet -#else -#define MAP_I2CRxFIFOConfigSet \ - I2CRxFIFOConfigSet -#endif -#ifdef ROM_I2CRxFIFOFlush -#define MAP_I2CRxFIFOFlush \ - ROM_I2CRxFIFOFlush -#else -#define MAP_I2CRxFIFOFlush \ - I2CRxFIFOFlush -#endif -#ifdef ROM_I2CFIFOStatus -#define MAP_I2CFIFOStatus \ - ROM_I2CFIFOStatus -#else -#define MAP_I2CFIFOStatus \ - I2CFIFOStatus -#endif -#ifdef ROM_I2CFIFODataPut -#define MAP_I2CFIFODataPut \ - ROM_I2CFIFODataPut -#else -#define MAP_I2CFIFODataPut \ - I2CFIFODataPut -#endif -#ifdef ROM_I2CFIFODataPutNonBlocking -#define MAP_I2CFIFODataPutNonBlocking \ - ROM_I2CFIFODataPutNonBlocking -#else -#define MAP_I2CFIFODataPutNonBlocking \ - I2CFIFODataPutNonBlocking -#endif -#ifdef ROM_I2CFIFODataGet -#define MAP_I2CFIFODataGet \ - ROM_I2CFIFODataGet -#else -#define MAP_I2CFIFODataGet \ - I2CFIFODataGet -#endif -#ifdef ROM_I2CFIFODataGetNonBlocking -#define MAP_I2CFIFODataGetNonBlocking \ - ROM_I2CFIFODataGetNonBlocking -#else -#define MAP_I2CFIFODataGetNonBlocking \ - I2CFIFODataGetNonBlocking -#endif -#ifdef ROM_I2CMasterBurstLengthSet -#define MAP_I2CMasterBurstLengthSet \ - ROM_I2CMasterBurstLengthSet -#else -#define MAP_I2CMasterBurstLengthSet \ - I2CMasterBurstLengthSet -#endif -#ifdef ROM_I2CMasterBurstCountGet -#define MAP_I2CMasterBurstCountGet \ - ROM_I2CMasterBurstCountGet -#else -#define MAP_I2CMasterBurstCountGet \ - I2CMasterBurstCountGet -#endif -#ifdef ROM_I2CMasterGlitchFilterConfigSet -#define MAP_I2CMasterGlitchFilterConfigSet \ - ROM_I2CMasterGlitchFilterConfigSet -#else -#define MAP_I2CMasterGlitchFilterConfigSet \ - I2CMasterGlitchFilterConfigSet -#endif -#ifdef ROM_I2CSlaveFIFOEnable -#define MAP_I2CSlaveFIFOEnable \ - ROM_I2CSlaveFIFOEnable -#else -#define MAP_I2CSlaveFIFOEnable \ - I2CSlaveFIFOEnable -#endif -#ifdef ROM_I2CSlaveFIFODisable -#define MAP_I2CSlaveFIFODisable \ - ROM_I2CSlaveFIFODisable -#else -#define MAP_I2CSlaveFIFODisable \ - I2CSlaveFIFODisable -#endif -#ifdef ROM_I2CMasterBusBusy -#define MAP_I2CMasterBusBusy \ - ROM_I2CMasterBusBusy -#else -#define MAP_I2CMasterBusBusy \ - I2CMasterBusBusy -#endif -#ifdef ROM_I2CMasterBusy -#define MAP_I2CMasterBusy \ - ROM_I2CMasterBusy -#else -#define MAP_I2CMasterBusy \ - I2CMasterBusy -#endif -#ifdef ROM_I2CMasterControl -#define MAP_I2CMasterControl \ - ROM_I2CMasterControl -#else -#define MAP_I2CMasterControl \ - I2CMasterControl -#endif -#ifdef ROM_I2CMasterDataGet -#define MAP_I2CMasterDataGet \ - ROM_I2CMasterDataGet -#else -#define MAP_I2CMasterDataGet \ - I2CMasterDataGet -#endif -#ifdef ROM_I2CMasterDataPut -#define MAP_I2CMasterDataPut \ - ROM_I2CMasterDataPut -#else -#define MAP_I2CMasterDataPut \ - I2CMasterDataPut -#endif -#ifdef ROM_I2CMasterDisable -#define MAP_I2CMasterDisable \ - ROM_I2CMasterDisable -#else -#define MAP_I2CMasterDisable \ - I2CMasterDisable -#endif -#ifdef ROM_I2CMasterEnable -#define MAP_I2CMasterEnable \ - ROM_I2CMasterEnable -#else -#define MAP_I2CMasterEnable \ - I2CMasterEnable -#endif -#ifdef ROM_I2CMasterErr -#define MAP_I2CMasterErr \ - ROM_I2CMasterErr -#else -#define MAP_I2CMasterErr \ - I2CMasterErr -#endif -#ifdef ROM_I2CMasterIntClear -#define MAP_I2CMasterIntClear \ - ROM_I2CMasterIntClear -#else -#define MAP_I2CMasterIntClear \ - I2CMasterIntClear -#endif -#ifdef ROM_I2CMasterIntDisable -#define MAP_I2CMasterIntDisable \ - ROM_I2CMasterIntDisable -#else -#define MAP_I2CMasterIntDisable \ - I2CMasterIntDisable -#endif -#ifdef ROM_I2CMasterIntEnable -#define MAP_I2CMasterIntEnable \ - ROM_I2CMasterIntEnable -#else -#define MAP_I2CMasterIntEnable \ - I2CMasterIntEnable -#endif -#ifdef ROM_I2CMasterIntStatus -#define MAP_I2CMasterIntStatus \ - ROM_I2CMasterIntStatus -#else -#define MAP_I2CMasterIntStatus \ - I2CMasterIntStatus -#endif -#ifdef ROM_I2CMasterIntEnableEx -#define MAP_I2CMasterIntEnableEx \ - ROM_I2CMasterIntEnableEx -#else -#define MAP_I2CMasterIntEnableEx \ - I2CMasterIntEnableEx -#endif -#ifdef ROM_I2CMasterIntDisableEx -#define MAP_I2CMasterIntDisableEx \ - ROM_I2CMasterIntDisableEx -#else -#define MAP_I2CMasterIntDisableEx \ - I2CMasterIntDisableEx -#endif -#ifdef ROM_I2CMasterIntStatusEx -#define MAP_I2CMasterIntStatusEx \ - ROM_I2CMasterIntStatusEx -#else -#define MAP_I2CMasterIntStatusEx \ - I2CMasterIntStatusEx -#endif -#ifdef ROM_I2CMasterIntClearEx -#define MAP_I2CMasterIntClearEx \ - ROM_I2CMasterIntClearEx -#else -#define MAP_I2CMasterIntClearEx \ - I2CMasterIntClearEx -#endif -#ifdef ROM_I2CMasterTimeoutSet -#define MAP_I2CMasterTimeoutSet \ - ROM_I2CMasterTimeoutSet -#else -#define MAP_I2CMasterTimeoutSet \ - I2CMasterTimeoutSet -#endif -#ifdef ROM_I2CSlaveACKOverride -#define MAP_I2CSlaveACKOverride \ - ROM_I2CSlaveACKOverride -#else -#define MAP_I2CSlaveACKOverride \ - I2CSlaveACKOverride -#endif -#ifdef ROM_I2CSlaveACKValueSet -#define MAP_I2CSlaveACKValueSet \ - ROM_I2CSlaveACKValueSet -#else -#define MAP_I2CSlaveACKValueSet \ - I2CSlaveACKValueSet -#endif -#ifdef ROM_I2CMasterLineStateGet -#define MAP_I2CMasterLineStateGet \ - ROM_I2CMasterLineStateGet -#else -#define MAP_I2CMasterLineStateGet \ - I2CMasterLineStateGet -#endif -#ifdef ROM_I2CMasterSlaveAddrSet -#define MAP_I2CMasterSlaveAddrSet \ - ROM_I2CMasterSlaveAddrSet -#else -#define MAP_I2CMasterSlaveAddrSet \ - I2CMasterSlaveAddrSet -#endif -#ifdef ROM_I2CSlaveDataGet -#define MAP_I2CSlaveDataGet \ - ROM_I2CSlaveDataGet -#else -#define MAP_I2CSlaveDataGet \ - I2CSlaveDataGet -#endif -#ifdef ROM_I2CSlaveDataPut -#define MAP_I2CSlaveDataPut \ - ROM_I2CSlaveDataPut -#else -#define MAP_I2CSlaveDataPut \ - I2CSlaveDataPut -#endif -#ifdef ROM_I2CSlaveDisable -#define MAP_I2CSlaveDisable \ - ROM_I2CSlaveDisable -#else -#define MAP_I2CSlaveDisable \ - I2CSlaveDisable -#endif -#ifdef ROM_I2CSlaveEnable -#define MAP_I2CSlaveEnable \ - ROM_I2CSlaveEnable -#else -#define MAP_I2CSlaveEnable \ - I2CSlaveEnable -#endif -#ifdef ROM_I2CSlaveInit -#define MAP_I2CSlaveInit \ - ROM_I2CSlaveInit -#else -#define MAP_I2CSlaveInit \ - I2CSlaveInit -#endif -#ifdef ROM_I2CSlaveAddressSet -#define MAP_I2CSlaveAddressSet \ - ROM_I2CSlaveAddressSet -#else -#define MAP_I2CSlaveAddressSet \ - I2CSlaveAddressSet -#endif -#ifdef ROM_I2CSlaveIntClear -#define MAP_I2CSlaveIntClear \ - ROM_I2CSlaveIntClear -#else -#define MAP_I2CSlaveIntClear \ - I2CSlaveIntClear -#endif -#ifdef ROM_I2CSlaveIntDisable -#define MAP_I2CSlaveIntDisable \ - ROM_I2CSlaveIntDisable -#else -#define MAP_I2CSlaveIntDisable \ - I2CSlaveIntDisable -#endif -#ifdef ROM_I2CSlaveIntEnable -#define MAP_I2CSlaveIntEnable \ - ROM_I2CSlaveIntEnable -#else -#define MAP_I2CSlaveIntEnable \ - I2CSlaveIntEnable -#endif -#ifdef ROM_I2CSlaveIntClearEx -#define MAP_I2CSlaveIntClearEx \ - ROM_I2CSlaveIntClearEx -#else -#define MAP_I2CSlaveIntClearEx \ - I2CSlaveIntClearEx -#endif -#ifdef ROM_I2CSlaveIntDisableEx -#define MAP_I2CSlaveIntDisableEx \ - ROM_I2CSlaveIntDisableEx -#else -#define MAP_I2CSlaveIntDisableEx \ - I2CSlaveIntDisableEx -#endif -#ifdef ROM_I2CSlaveIntEnableEx -#define MAP_I2CSlaveIntEnableEx \ - ROM_I2CSlaveIntEnableEx -#else -#define MAP_I2CSlaveIntEnableEx \ - I2CSlaveIntEnableEx -#endif -#ifdef ROM_I2CSlaveIntStatus -#define MAP_I2CSlaveIntStatus \ - ROM_I2CSlaveIntStatus -#else -#define MAP_I2CSlaveIntStatus \ - I2CSlaveIntStatus -#endif -#ifdef ROM_I2CSlaveIntStatusEx -#define MAP_I2CSlaveIntStatusEx \ - ROM_I2CSlaveIntStatusEx -#else -#define MAP_I2CSlaveIntStatusEx \ - I2CSlaveIntStatusEx -#endif -#ifdef ROM_I2CSlaveStatus -#define MAP_I2CSlaveStatus \ - ROM_I2CSlaveStatus -#else -#define MAP_I2CSlaveStatus \ - I2CSlaveStatus -#endif -#ifdef ROM_I2CMasterInitExpClk -#define MAP_I2CMasterInitExpClk \ - ROM_I2CMasterInitExpClk -#else -#define MAP_I2CMasterInitExpClk \ - I2CMasterInitExpClk -#endif - -//***************************************************************************** -// -// Macros for the SPI API. -// -//***************************************************************************** -#ifdef ROM_SPIEnable -#define MAP_SPIEnable \ - ROM_SPIEnable -#else -#define MAP_SPIEnable \ - SPIEnable -#endif -#ifdef ROM_SPIDisable -#define MAP_SPIDisable \ - ROM_SPIDisable -#else -#define MAP_SPIDisable \ - SPIDisable -#endif -#ifdef ROM_SPIReset -#define MAP_SPIReset \ - ROM_SPIReset -#else -#define MAP_SPIReset \ - SPIReset -#endif -#ifdef ROM_SPIConfigSetExpClk -#define MAP_SPIConfigSetExpClk \ - ROM_SPIConfigSetExpClk -#else -#define MAP_SPIConfigSetExpClk \ - SPIConfigSetExpClk -#endif -#ifdef ROM_SPIDataGetNonBlocking -#define MAP_SPIDataGetNonBlocking \ - ROM_SPIDataGetNonBlocking -#else -#define MAP_SPIDataGetNonBlocking \ - SPIDataGetNonBlocking -#endif -#ifdef ROM_SPIDataGet -#define MAP_SPIDataGet \ - ROM_SPIDataGet -#else -#define MAP_SPIDataGet \ - SPIDataGet -#endif -#ifdef ROM_SPIDataPutNonBlocking -#define MAP_SPIDataPutNonBlocking \ - ROM_SPIDataPutNonBlocking -#else -#define MAP_SPIDataPutNonBlocking \ - SPIDataPutNonBlocking -#endif -#ifdef ROM_SPIDataPut -#define MAP_SPIDataPut \ - ROM_SPIDataPut -#else -#define MAP_SPIDataPut \ - SPIDataPut -#endif -#ifdef ROM_SPIFIFOEnable -#define MAP_SPIFIFOEnable \ - ROM_SPIFIFOEnable -#else -#define MAP_SPIFIFOEnable \ - SPIFIFOEnable -#endif -#ifdef ROM_SPIFIFODisable -#define MAP_SPIFIFODisable \ - ROM_SPIFIFODisable -#else -#define MAP_SPIFIFODisable \ - SPIFIFODisable -#endif -#ifdef ROM_SPIFIFOLevelSet -#define MAP_SPIFIFOLevelSet \ - ROM_SPIFIFOLevelSet -#else -#define MAP_SPIFIFOLevelSet \ - SPIFIFOLevelSet -#endif -#ifdef ROM_SPIFIFOLevelGet -#define MAP_SPIFIFOLevelGet \ - ROM_SPIFIFOLevelGet -#else -#define MAP_SPIFIFOLevelGet \ - SPIFIFOLevelGet -#endif -#ifdef ROM_SPIWordCountSet -#define MAP_SPIWordCountSet \ - ROM_SPIWordCountSet -#else -#define MAP_SPIWordCountSet \ - SPIWordCountSet -#endif -#ifdef ROM_SPIIntRegister -#define MAP_SPIIntRegister \ - ROM_SPIIntRegister -#else -#define MAP_SPIIntRegister \ - SPIIntRegister -#endif -#ifdef ROM_SPIIntUnregister -#define MAP_SPIIntUnregister \ - ROM_SPIIntUnregister -#else -#define MAP_SPIIntUnregister \ - SPIIntUnregister -#endif -#ifdef ROM_SPIIntEnable -#define MAP_SPIIntEnable \ - ROM_SPIIntEnable -#else -#define MAP_SPIIntEnable \ - SPIIntEnable -#endif -#ifdef ROM_SPIIntDisable -#define MAP_SPIIntDisable \ - ROM_SPIIntDisable -#else -#define MAP_SPIIntDisable \ - SPIIntDisable -#endif -#ifdef ROM_SPIIntStatus -#define MAP_SPIIntStatus \ - ROM_SPIIntStatus -#else -#define MAP_SPIIntStatus \ - SPIIntStatus -#endif -#ifdef ROM_SPIIntClear -#define MAP_SPIIntClear \ - ROM_SPIIntClear -#else -#define MAP_SPIIntClear \ - SPIIntClear -#endif -#ifdef ROM_SPIDmaEnable -#define MAP_SPIDmaEnable \ - ROM_SPIDmaEnable -#else -#define MAP_SPIDmaEnable \ - SPIDmaEnable -#endif -#ifdef ROM_SPIDmaDisable -#define MAP_SPIDmaDisable \ - ROM_SPIDmaDisable -#else -#define MAP_SPIDmaDisable \ - SPIDmaDisable -#endif -#ifdef ROM_SPICSEnable -#define MAP_SPICSEnable \ - ROM_SPICSEnable -#else -#define MAP_SPICSEnable \ - SPICSEnable -#endif -#ifdef ROM_SPICSDisable -#define MAP_SPICSDisable \ - ROM_SPICSDisable -#else -#define MAP_SPICSDisable \ - SPICSDisable -#endif -#ifdef ROM_SPITransfer -#define MAP_SPITransfer \ - ROM_SPITransfer -#else -#define MAP_SPITransfer \ - SPITransfer -#endif - -//***************************************************************************** -// -// Macros for the CAM API. -// -//***************************************************************************** -#ifdef ROM_CameraReset -#define MAP_CameraReset \ - ROM_CameraReset -#else -#define MAP_CameraReset \ - CameraReset -#endif -#ifdef ROM_CameraParamsConfig -#define MAP_CameraParamsConfig \ - ROM_CameraParamsConfig -#else -#define MAP_CameraParamsConfig \ - CameraParamsConfig -#endif -#ifdef ROM_CameraXClkConfig -#define MAP_CameraXClkConfig \ - ROM_CameraXClkConfig -#else -#define MAP_CameraXClkConfig \ - CameraXClkConfig -#endif -#ifdef ROM_CameraXClkSet -#define MAP_CameraXClkSet \ - ROM_CameraXClkSet -#else -#define MAP_CameraXClkSet \ - CameraXClkSet -#endif -#ifdef ROM_CameraDMAEnable -#define MAP_CameraDMAEnable \ - ROM_CameraDMAEnable -#else -#define MAP_CameraDMAEnable \ - CameraDMAEnable -#endif -#ifdef ROM_CameraDMADisable -#define MAP_CameraDMADisable \ - ROM_CameraDMADisable -#else -#define MAP_CameraDMADisable \ - CameraDMADisable -#endif -#ifdef ROM_CameraThresholdSet -#define MAP_CameraThresholdSet \ - ROM_CameraThresholdSet -#else -#define MAP_CameraThresholdSet \ - CameraThresholdSet -#endif -#ifdef ROM_CameraIntRegister -#define MAP_CameraIntRegister \ - ROM_CameraIntRegister -#else -#define MAP_CameraIntRegister \ - CameraIntRegister -#endif -#ifdef ROM_CameraIntUnregister -#define MAP_CameraIntUnregister \ - ROM_CameraIntUnregister -#else -#define MAP_CameraIntUnregister \ - CameraIntUnregister -#endif -#ifdef ROM_CameraIntEnable -#define MAP_CameraIntEnable \ - ROM_CameraIntEnable -#else -#define MAP_CameraIntEnable \ - CameraIntEnable -#endif -#ifdef ROM_CameraIntDisable -#define MAP_CameraIntDisable \ - ROM_CameraIntDisable -#else -#define MAP_CameraIntDisable \ - CameraIntDisable -#endif -#ifdef ROM_CameraIntStatus -#define MAP_CameraIntStatus \ - ROM_CameraIntStatus -#else -#define MAP_CameraIntStatus \ - CameraIntStatus -#endif -#ifdef ROM_CameraIntClear -#define MAP_CameraIntClear \ - ROM_CameraIntClear -#else -#define MAP_CameraIntClear \ - CameraIntClear -#endif -#ifdef ROM_CameraCaptureStop -#define MAP_CameraCaptureStop \ - ROM_CameraCaptureStop -#else -#define MAP_CameraCaptureStop \ - CameraCaptureStop -#endif -#ifdef ROM_CameraCaptureStart -#define MAP_CameraCaptureStart \ - ROM_CameraCaptureStart -#else -#define MAP_CameraCaptureStart \ - CameraCaptureStart -#endif -#ifdef ROM_CameraBufferRead -#define MAP_CameraBufferRead \ - ROM_CameraBufferRead -#else -#define MAP_CameraBufferRead \ - CameraBufferRead -#endif - -//***************************************************************************** -// -// Macros for the FLASH API. -// -//***************************************************************************** -#ifdef ROM_FlashDisable -#define MAP_FlashDisable \ - ROM_FlashDisable -#else -#define MAP_FlashDisable \ - FlashDisable -#endif -#ifdef ROM_FlashErase -#define MAP_FlashErase \ - ROM_FlashErase -#else -#define MAP_FlashErase \ - FlashErase -#endif -#ifdef ROM_FlashMassErase -#define MAP_FlashMassErase \ - ROM_FlashMassErase -#else -#define MAP_FlashMassErase \ - FlashMassErase -#endif -#ifdef ROM_FlashMassEraseNonBlocking -#define MAP_FlashMassEraseNonBlocking \ - ROM_FlashMassEraseNonBlocking -#else -#define MAP_FlashMassEraseNonBlocking \ - FlashMassEraseNonBlocking -#endif -#ifdef ROM_FlashEraseNonBlocking -#define MAP_FlashEraseNonBlocking \ - ROM_FlashEraseNonBlocking -#else -#define MAP_FlashEraseNonBlocking \ - FlashEraseNonBlocking -#endif -#ifdef ROM_FlashProgram -#define MAP_FlashProgram \ - ROM_FlashProgram -#else -#define MAP_FlashProgram \ - FlashProgram -#endif -#ifdef ROM_FlashProgramNonBlocking -#define MAP_FlashProgramNonBlocking \ - ROM_FlashProgramNonBlocking -#else -#define MAP_FlashProgramNonBlocking \ - FlashProgramNonBlocking -#endif -#ifdef ROM_FlashIntRegister -#define MAP_FlashIntRegister \ - ROM_FlashIntRegister -#else -#define MAP_FlashIntRegister \ - FlashIntRegister -#endif -#ifdef ROM_FlashIntUnregister -#define MAP_FlashIntUnregister \ - ROM_FlashIntUnregister -#else -#define MAP_FlashIntUnregister \ - FlashIntUnregister -#endif -#ifdef ROM_FlashIntEnable -#define MAP_FlashIntEnable \ - ROM_FlashIntEnable -#else -#define MAP_FlashIntEnable \ - FlashIntEnable -#endif -#ifdef ROM_FlashIntDisable -#define MAP_FlashIntDisable \ - ROM_FlashIntDisable -#else -#define MAP_FlashIntDisable \ - FlashIntDisable -#endif -#ifdef ROM_FlashIntStatus -#define MAP_FlashIntStatus \ - ROM_FlashIntStatus -#else -#define MAP_FlashIntStatus \ - FlashIntStatus -#endif -#ifdef ROM_FlashIntClear -#define MAP_FlashIntClear \ - ROM_FlashIntClear -#else -#define MAP_FlashIntClear \ - FlashIntClear -#endif -#ifdef ROM_FlashProtectGet -#define MAP_FlashProtectGet \ - ROM_FlashProtectGet -#else -#define MAP_FlashProtectGet \ - FlashProtectGet -#endif - -//***************************************************************************** -// -// Macros for the Pin API. -// -//***************************************************************************** -#ifdef ROM_PinModeSet -#define MAP_PinModeSet \ - ROM_PinModeSet -#else -#define MAP_PinModeSet \ - PinModeSet -#endif -#ifdef ROM_PinDirModeSet -#define MAP_PinDirModeSet \ - ROM_PinDirModeSet -#else -#define MAP_PinDirModeSet \ - PinDirModeSet -#endif -#ifdef ROM_PinDirModeGet -#define MAP_PinDirModeGet \ - ROM_PinDirModeGet -#else -#define MAP_PinDirModeGet \ - PinDirModeGet -#endif -#ifdef ROM_PinModeGet -#define MAP_PinModeGet \ - ROM_PinModeGet -#else -#define MAP_PinModeGet \ - PinModeGet -#endif -#ifdef ROM_PinConfigGet -#define MAP_PinConfigGet \ - ROM_PinConfigGet -#else -#define MAP_PinConfigGet \ - PinConfigGet -#endif -#ifdef ROM_PinConfigSet -#define MAP_PinConfigSet \ - ROM_PinConfigSet -#else -#define MAP_PinConfigSet \ - PinConfigSet -#endif -#ifdef ROM_PinTypeUART -#define MAP_PinTypeUART \ - ROM_PinTypeUART -#else -#define MAP_PinTypeUART \ - PinTypeUART -#endif -#ifdef ROM_PinTypeI2C -#define MAP_PinTypeI2C \ - ROM_PinTypeI2C -#else -#define MAP_PinTypeI2C \ - PinTypeI2C -#endif -#ifdef ROM_PinTypeSPI -#define MAP_PinTypeSPI \ - ROM_PinTypeSPI -#else -#define MAP_PinTypeSPI \ - PinTypeSPI -#endif -#ifdef ROM_PinTypeI2S -#define MAP_PinTypeI2S \ - ROM_PinTypeI2S -#else -#define MAP_PinTypeI2S \ - PinTypeI2S -#endif -#ifdef ROM_PinTypeTimer -#define MAP_PinTypeTimer \ - ROM_PinTypeTimer -#else -#define MAP_PinTypeTimer \ - PinTypeTimer -#endif -#ifdef ROM_PinTypeCamera -#define MAP_PinTypeCamera \ - ROM_PinTypeCamera -#else -#define MAP_PinTypeCamera \ - PinTypeCamera -#endif -#ifdef ROM_PinTypeGPIO -#define MAP_PinTypeGPIO \ - ROM_PinTypeGPIO -#else -#define MAP_PinTypeGPIO \ - PinTypeGPIO -#endif -#ifdef ROM_PinTypeADC -#define MAP_PinTypeADC \ - ROM_PinTypeADC -#else -#define MAP_PinTypeADC \ - PinTypeADC -#endif -#ifdef ROM_PinTypeSDHost -#define MAP_PinTypeSDHost \ - ROM_PinTypeSDHost -#else -#define MAP_PinTypeSDHost \ - PinTypeSDHost -#endif -#ifdef ROM_PinHysteresisSet -#define MAP_PinHysteresisSet \ - ROM_PinHysteresisSet -#else -#define MAP_PinHysteresisSet \ - PinHysteresisSet -#endif -#ifdef ROM_PinLockLevelSet -#define MAP_PinLockLevelSet \ - ROM_PinLockLevelSet -#else -#define MAP_PinLockLevelSet \ - PinLockLevelSet -#endif -#ifdef ROM_PinLock -#define MAP_PinLock \ - ROM_PinLock -#else -#define MAP_PinLock \ - PinLock -#endif -#ifdef ROM_PinUnlock -#define MAP_PinUnlock \ - ROM_PinUnlock -#else -#define MAP_PinUnlock \ - PinUnlock -#endif - -//***************************************************************************** -// -// Macros for the SYSTICK API. -// -//***************************************************************************** -#ifdef ROM_SysTickEnable -#define MAP_SysTickEnable \ - ROM_SysTickEnable -#else -#define MAP_SysTickEnable \ - SysTickEnable -#endif -#ifdef ROM_SysTickDisable -#define MAP_SysTickDisable \ - ROM_SysTickDisable -#else -#define MAP_SysTickDisable \ - SysTickDisable -#endif -#ifdef ROM_SysTickIntRegister -#define MAP_SysTickIntRegister \ - ROM_SysTickIntRegister -#else -#define MAP_SysTickIntRegister \ - SysTickIntRegister -#endif -#ifdef ROM_SysTickIntUnregister -#define MAP_SysTickIntUnregister \ - ROM_SysTickIntUnregister -#else -#define MAP_SysTickIntUnregister \ - SysTickIntUnregister -#endif -#ifdef ROM_SysTickIntEnable -#define MAP_SysTickIntEnable \ - ROM_SysTickIntEnable -#else -#define MAP_SysTickIntEnable \ - SysTickIntEnable -#endif -#ifdef ROM_SysTickIntDisable -#define MAP_SysTickIntDisable \ - ROM_SysTickIntDisable -#else -#define MAP_SysTickIntDisable \ - SysTickIntDisable -#endif -#ifdef ROM_SysTickPeriodSet -#define MAP_SysTickPeriodSet \ - ROM_SysTickPeriodSet -#else -#define MAP_SysTickPeriodSet \ - SysTickPeriodSet -#endif -#ifdef ROM_SysTickPeriodGet -#define MAP_SysTickPeriodGet \ - ROM_SysTickPeriodGet -#else -#define MAP_SysTickPeriodGet \ - SysTickPeriodGet -#endif -#ifdef ROM_SysTickValueGet -#define MAP_SysTickValueGet \ - ROM_SysTickValueGet -#else -#define MAP_SysTickValueGet \ - SysTickValueGet -#endif - -//***************************************************************************** -// -// Macros for the UTILS API. -// -//***************************************************************************** -#if defined(USE_CC3200_ROM_DRV_API) || \ - defined(USE_CC3220_ROM_DRV_API) -#define MAP_UtilsDelay \ - ROM_UtilsDelay -#else -#define MAP_UtilsDelay \ - UtilsDelay -#endif - -//***************************************************************************** -// -// Macros for the I2S API. -// -//***************************************************************************** -#ifdef ROM_I2SEnable -#define MAP_I2SEnable \ - ROM_I2SEnable -#else -#define MAP_I2SEnable \ - I2SEnable -#endif -#ifdef ROM_I2SDisable -#define MAP_I2SDisable \ - ROM_I2SDisable -#else -#define MAP_I2SDisable \ - I2SDisable -#endif -#ifdef ROM_I2SDataPut -#define MAP_I2SDataPut \ - ROM_I2SDataPut -#else -#define MAP_I2SDataPut \ - I2SDataPut -#endif -#ifdef ROM_I2SDataPutNonBlocking -#define MAP_I2SDataPutNonBlocking \ - ROM_I2SDataPutNonBlocking -#else -#define MAP_I2SDataPutNonBlocking \ - I2SDataPutNonBlocking -#endif -#ifdef ROM_I2SDataGet -#define MAP_I2SDataGet \ - ROM_I2SDataGet -#else -#define MAP_I2SDataGet \ - I2SDataGet -#endif -#ifdef ROM_I2SDataGetNonBlocking -#define MAP_I2SDataGetNonBlocking \ - ROM_I2SDataGetNonBlocking -#else -#define MAP_I2SDataGetNonBlocking \ - I2SDataGetNonBlocking -#endif -#ifdef ROM_I2SConfigSetExpClk -#define MAP_I2SConfigSetExpClk \ - ROM_I2SConfigSetExpClk -#else -#define MAP_I2SConfigSetExpClk \ - I2SConfigSetExpClk -#endif -#ifdef ROM_I2STxFIFOEnable -#define MAP_I2STxFIFOEnable \ - ROM_I2STxFIFOEnable -#else -#define MAP_I2STxFIFOEnable \ - I2STxFIFOEnable -#endif -#ifdef ROM_I2STxFIFODisable -#define MAP_I2STxFIFODisable \ - ROM_I2STxFIFODisable -#else -#define MAP_I2STxFIFODisable \ - I2STxFIFODisable -#endif -#ifdef ROM_I2SRxFIFOEnable -#define MAP_I2SRxFIFOEnable \ - ROM_I2SRxFIFOEnable -#else -#define MAP_I2SRxFIFOEnable \ - I2SRxFIFOEnable -#endif -#ifdef ROM_I2SRxFIFODisable -#define MAP_I2SRxFIFODisable \ - ROM_I2SRxFIFODisable -#else -#define MAP_I2SRxFIFODisable \ - I2SRxFIFODisable -#endif -#ifdef ROM_I2STxFIFOStatusGet -#define MAP_I2STxFIFOStatusGet \ - ROM_I2STxFIFOStatusGet -#else -#define MAP_I2STxFIFOStatusGet \ - I2STxFIFOStatusGet -#endif -#ifdef ROM_I2SRxFIFOStatusGet -#define MAP_I2SRxFIFOStatusGet \ - ROM_I2SRxFIFOStatusGet -#else -#define MAP_I2SRxFIFOStatusGet \ - I2SRxFIFOStatusGet -#endif -#ifdef ROM_I2SSerializerConfig -#define MAP_I2SSerializerConfig \ - ROM_I2SSerializerConfig -#else -#define MAP_I2SSerializerConfig \ - I2SSerializerConfig -#endif -#ifdef ROM_I2SIntEnable -#define MAP_I2SIntEnable \ - ROM_I2SIntEnable -#else -#define MAP_I2SIntEnable \ - I2SIntEnable -#endif -#ifdef ROM_I2SIntDisable -#define MAP_I2SIntDisable \ - ROM_I2SIntDisable -#else -#define MAP_I2SIntDisable \ - I2SIntDisable -#endif -#ifdef ROM_I2SIntStatus -#define MAP_I2SIntStatus \ - ROM_I2SIntStatus -#else -#define MAP_I2SIntStatus \ - I2SIntStatus -#endif -#ifdef ROM_I2SIntClear -#define MAP_I2SIntClear \ - ROM_I2SIntClear -#else -#define MAP_I2SIntClear \ - I2SIntClear -#endif -#ifdef ROM_I2SIntRegister -#define MAP_I2SIntRegister \ - ROM_I2SIntRegister -#else -#define MAP_I2SIntRegister \ - I2SIntRegister -#endif -#ifdef ROM_I2SIntUnregister -#define MAP_I2SIntUnregister \ - ROM_I2SIntUnregister -#else -#define MAP_I2SIntUnregister \ - I2SIntUnregister -#endif -#ifdef ROM_I2STxActiveSlotSet -#define MAP_I2STxActiveSlotSet \ - ROM_I2STxActiveSlotSet -#else -#define MAP_I2STxActiveSlotSet \ - I2STxActiveSlotSet -#endif -#ifdef ROM_I2SRxActiveSlotSet -#define MAP_I2SRxActiveSlotSet \ - ROM_I2SRxActiveSlotSet -#else -#define MAP_I2SRxActiveSlotSet \ - I2SRxActiveSlotSet -#endif - -//***************************************************************************** -// -// Macros for the GPIO API. -// -//***************************************************************************** -#ifdef ROM_GPIODirModeSet -#define MAP_GPIODirModeSet \ - ROM_GPIODirModeSet -#else -#define MAP_GPIODirModeSet \ - GPIODirModeSet -#endif -#ifdef ROM_GPIODirModeGet -#define MAP_GPIODirModeGet \ - ROM_GPIODirModeGet -#else -#define MAP_GPIODirModeGet \ - GPIODirModeGet -#endif -#ifdef ROM_GPIOIntTypeSet -#define MAP_GPIOIntTypeSet \ - ROM_GPIOIntTypeSet -#else -#define MAP_GPIOIntTypeSet \ - GPIOIntTypeSet -#endif -#ifdef ROM_GPIODMATriggerEnable -#define MAP_GPIODMATriggerEnable \ - ROM_GPIODMATriggerEnable -#else -#define MAP_GPIODMATriggerEnable \ - GPIODMATriggerEnable -#endif -#ifdef ROM_GPIODMATriggerDisable -#define MAP_GPIODMATriggerDisable \ - ROM_GPIODMATriggerDisable -#else -#define MAP_GPIODMATriggerDisable \ - GPIODMATriggerDisable -#endif -#ifdef ROM_GPIOIntTypeGet -#define MAP_GPIOIntTypeGet \ - ROM_GPIOIntTypeGet -#else -#define MAP_GPIOIntTypeGet \ - GPIOIntTypeGet -#endif -#ifdef ROM_GPIOIntEnable -#define MAP_GPIOIntEnable \ - ROM_GPIOIntEnable -#else -#define MAP_GPIOIntEnable \ - GPIOIntEnable -#endif -#ifdef ROM_GPIOIntDisable -#define MAP_GPIOIntDisable \ - ROM_GPIOIntDisable -#else -#define MAP_GPIOIntDisable \ - GPIOIntDisable -#endif -#ifdef ROM_GPIOIntStatus -#define MAP_GPIOIntStatus \ - ROM_GPIOIntStatus -#else -#define MAP_GPIOIntStatus \ - GPIOIntStatus -#endif -#ifdef ROM_GPIOIntClear -#define MAP_GPIOIntClear \ - ROM_GPIOIntClear -#else -#define MAP_GPIOIntClear \ - GPIOIntClear -#endif -#ifdef ROM_GPIOIntRegister -#define MAP_GPIOIntRegister \ - ROM_GPIOIntRegister -#else -#define MAP_GPIOIntRegister \ - GPIOIntRegister -#endif -#ifdef ROM_GPIOIntUnregister -#define MAP_GPIOIntUnregister \ - ROM_GPIOIntUnregister -#else -#define MAP_GPIOIntUnregister \ - GPIOIntUnregister -#endif -#ifdef ROM_GPIOPinRead -#define MAP_GPIOPinRead \ - ROM_GPIOPinRead -#else -#define MAP_GPIOPinRead \ - GPIOPinRead -#endif -#ifdef ROM_GPIOPinWrite -#define MAP_GPIOPinWrite \ - ROM_GPIOPinWrite -#else -#define MAP_GPIOPinWrite \ - GPIOPinWrite -#endif - -//***************************************************************************** -// -// Macros for the AES API. -// -//***************************************************************************** -#ifdef ROM_AESConfigSet -#define MAP_AESConfigSet \ - ROM_AESConfigSet -#else -#define MAP_AESConfigSet \ - AESConfigSet -#endif -#ifdef ROM_AESKey1Set -#define MAP_AESKey1Set \ - ROM_AESKey1Set -#else -#define MAP_AESKey1Set \ - AESKey1Set -#endif -#ifdef ROM_AESKey2Set -#define MAP_AESKey2Set \ - ROM_AESKey2Set -#else -#define MAP_AESKey2Set \ - AESKey2Set -#endif -#ifdef ROM_AESKey3Set -#define MAP_AESKey3Set \ - ROM_AESKey3Set -#else -#define MAP_AESKey3Set \ - AESKey3Set -#endif -#ifdef ROM_AESIVSet -#define MAP_AESIVSet \ - ROM_AESIVSet -#else -#define MAP_AESIVSet \ - AESIVSet -#endif -#ifdef ROM_AESTagRead -#define MAP_AESTagRead \ - ROM_AESTagRead -#else -#define MAP_AESTagRead \ - AESTagRead -#endif -#ifdef ROM_AESDataLengthSet -#define MAP_AESDataLengthSet \ - ROM_AESDataLengthSet -#else -#define MAP_AESDataLengthSet \ - AESDataLengthSet -#endif -#ifdef ROM_AESAuthDataLengthSet -#define MAP_AESAuthDataLengthSet \ - ROM_AESAuthDataLengthSet -#else -#define MAP_AESAuthDataLengthSet \ - AESAuthDataLengthSet -#endif -#ifdef ROM_AESDataReadNonBlocking -#define MAP_AESDataReadNonBlocking \ - ROM_AESDataReadNonBlocking -#else -#define MAP_AESDataReadNonBlocking \ - AESDataReadNonBlocking -#endif -#ifdef ROM_AESDataRead -#define MAP_AESDataRead \ - ROM_AESDataRead -#else -#define MAP_AESDataRead \ - AESDataRead -#endif -#ifdef ROM_AESDataWriteNonBlocking -#define MAP_AESDataWriteNonBlocking \ - ROM_AESDataWriteNonBlocking -#else -#define MAP_AESDataWriteNonBlocking \ - AESDataWriteNonBlocking -#endif -#ifdef ROM_AESDataWrite -#define MAP_AESDataWrite \ - ROM_AESDataWrite -#else -#define MAP_AESDataWrite \ - AESDataWrite -#endif -#ifdef ROM_AESDataProcess -#define MAP_AESDataProcess \ - ROM_AESDataProcess -#else -#define MAP_AESDataProcess \ - AESDataProcess -#endif -#ifdef ROM_AESDataMAC -#define MAP_AESDataMAC \ - ROM_AESDataMAC -#else -#define MAP_AESDataMAC \ - AESDataMAC -#endif -#ifdef ROM_AESDataProcessAE -#define MAP_AESDataProcessAE \ - ROM_AESDataProcessAE -#else -#define MAP_AESDataProcessAE \ - AESDataProcessAE -#endif -#ifdef ROM_AESIntStatus -#define MAP_AESIntStatus \ - ROM_AESIntStatus -#else -#define MAP_AESIntStatus \ - AESIntStatus -#endif -#ifdef ROM_AESIntEnable -#define MAP_AESIntEnable \ - ROM_AESIntEnable -#else -#define MAP_AESIntEnable \ - AESIntEnable -#endif -#ifdef ROM_AESIntDisable -#define MAP_AESIntDisable \ - ROM_AESIntDisable -#else -#define MAP_AESIntDisable \ - AESIntDisable -#endif -#ifdef ROM_AESIntClear -#define MAP_AESIntClear \ - ROM_AESIntClear -#else -#define MAP_AESIntClear \ - AESIntClear -#endif -#ifdef ROM_AESIntRegister -#define MAP_AESIntRegister \ - ROM_AESIntRegister -#else -#define MAP_AESIntRegister \ - AESIntRegister -#endif -#ifdef ROM_AESIntUnregister -#define MAP_AESIntUnregister \ - ROM_AESIntUnregister -#else -#define MAP_AESIntUnregister \ - AESIntUnregister -#endif -#ifdef ROM_AESDMAEnable -#define MAP_AESDMAEnable \ - ROM_AESDMAEnable -#else -#define MAP_AESDMAEnable \ - AESDMAEnable -#endif -#ifdef ROM_AESDMADisable -#define MAP_AESDMADisable \ - ROM_AESDMADisable -#else -#define MAP_AESDMADisable \ - AESDMADisable -#endif -#ifdef ROM_AESIVGet -#define MAP_AESIVGet \ - ROM_AESIVGet -#else -#define MAP_AESIVGet \ - AESIVGet -#endif - -//***************************************************************************** -// -// Macros for the DES API. -// -//***************************************************************************** -#ifdef ROM_DESConfigSet -#define MAP_DESConfigSet \ - ROM_DESConfigSet -#else -#define MAP_DESConfigSet \ - DESConfigSet -#endif -#ifdef ROM_DESDataRead -#define MAP_DESDataRead \ - ROM_DESDataRead -#else -#define MAP_DESDataRead \ - DESDataRead -#endif -#ifdef ROM_DESDataReadNonBlocking -#define MAP_DESDataReadNonBlocking \ - ROM_DESDataReadNonBlocking -#else -#define MAP_DESDataReadNonBlocking \ - DESDataReadNonBlocking -#endif -#ifdef ROM_DESDataProcess -#define MAP_DESDataProcess \ - ROM_DESDataProcess -#else -#define MAP_DESDataProcess \ - DESDataProcess -#endif -#ifdef ROM_DESDataWrite -#define MAP_DESDataWrite \ - ROM_DESDataWrite -#else -#define MAP_DESDataWrite \ - DESDataWrite -#endif -#ifdef ROM_DESDataWriteNonBlocking -#define MAP_DESDataWriteNonBlocking \ - ROM_DESDataWriteNonBlocking -#else -#define MAP_DESDataWriteNonBlocking \ - DESDataWriteNonBlocking -#endif -#ifdef ROM_DESDMADisable -#define MAP_DESDMADisable \ - ROM_DESDMADisable -#else -#define MAP_DESDMADisable \ - DESDMADisable -#endif -#ifdef ROM_DESDMAEnable -#define MAP_DESDMAEnable \ - ROM_DESDMAEnable -#else -#define MAP_DESDMAEnable \ - DESDMAEnable -#endif -#ifdef ROM_DESIntClear -#define MAP_DESIntClear \ - ROM_DESIntClear -#else -#define MAP_DESIntClear \ - DESIntClear -#endif -#ifdef ROM_DESIntDisable -#define MAP_DESIntDisable \ - ROM_DESIntDisable -#else -#define MAP_DESIntDisable \ - DESIntDisable -#endif -#ifdef ROM_DESIntEnable -#define MAP_DESIntEnable \ - ROM_DESIntEnable -#else -#define MAP_DESIntEnable \ - DESIntEnable -#endif -#ifdef ROM_DESIntRegister -#define MAP_DESIntRegister \ - ROM_DESIntRegister -#else -#define MAP_DESIntRegister \ - DESIntRegister -#endif -#ifdef ROM_DESIntStatus -#define MAP_DESIntStatus \ - ROM_DESIntStatus -#else -#define MAP_DESIntStatus \ - DESIntStatus -#endif -#ifdef ROM_DESIntUnregister -#define MAP_DESIntUnregister \ - ROM_DESIntUnregister -#else -#define MAP_DESIntUnregister \ - DESIntUnregister -#endif -#ifdef ROM_DESIVSet -#define MAP_DESIVSet \ - ROM_DESIVSet -#else -#define MAP_DESIVSet \ - DESIVSet -#endif -#ifdef ROM_DESKeySet -#define MAP_DESKeySet \ - ROM_DESKeySet -#else -#define MAP_DESKeySet \ - DESKeySet -#endif -#ifdef ROM_DESDataLengthSet -#define MAP_DESDataLengthSet \ - ROM_DESDataLengthSet -#else -#define MAP_DESDataLengthSet \ - DESDataLengthSet -#endif - -//***************************************************************************** -// -// Macros for the SHAMD5 API. -// -//***************************************************************************** -#ifdef ROM_SHAMD5ConfigSet -#define MAP_SHAMD5ConfigSet \ - ROM_SHAMD5ConfigSet -#else -#define MAP_SHAMD5ConfigSet \ - SHAMD5ConfigSet -#endif -#ifdef ROM_SHAMD5DataProcess -#define MAP_SHAMD5DataProcess \ - ROM_SHAMD5DataProcess -#else -#define MAP_SHAMD5DataProcess \ - SHAMD5DataProcess -#endif -#ifdef ROM_SHAMD5DataWrite -#define MAP_SHAMD5DataWrite \ - ROM_SHAMD5DataWrite -#else -#define MAP_SHAMD5DataWrite \ - SHAMD5DataWrite -#endif -#ifdef ROM_SHAMD5DataWriteNonBlocking -#define MAP_SHAMD5DataWriteNonBlocking \ - ROM_SHAMD5DataWriteNonBlocking -#else -#define MAP_SHAMD5DataWriteNonBlocking \ - SHAMD5DataWriteNonBlocking -#endif -#ifdef ROM_SHAMD5DMADisable -#define MAP_SHAMD5DMADisable \ - ROM_SHAMD5DMADisable -#else -#define MAP_SHAMD5DMADisable \ - SHAMD5DMADisable -#endif -#ifdef ROM_SHAMD5DMAEnable -#define MAP_SHAMD5DMAEnable \ - ROM_SHAMD5DMAEnable -#else -#define MAP_SHAMD5DMAEnable \ - SHAMD5DMAEnable -#endif -#ifdef ROM_SHAMD5DataLengthSet -#define MAP_SHAMD5DataLengthSet \ - ROM_SHAMD5DataLengthSet -#else -#define MAP_SHAMD5DataLengthSet \ - SHAMD5DataLengthSet -#endif -#ifdef ROM_SHAMD5HMACKeySet -#define MAP_SHAMD5HMACKeySet \ - ROM_SHAMD5HMACKeySet -#else -#define MAP_SHAMD5HMACKeySet \ - SHAMD5HMACKeySet -#endif -#ifdef ROM_SHAMD5HMACPPKeyGenerate -#define MAP_SHAMD5HMACPPKeyGenerate \ - ROM_SHAMD5HMACPPKeyGenerate -#else -#define MAP_SHAMD5HMACPPKeyGenerate \ - SHAMD5HMACPPKeyGenerate -#endif -#ifdef ROM_SHAMD5HMACPPKeySet -#define MAP_SHAMD5HMACPPKeySet \ - ROM_SHAMD5HMACPPKeySet -#else -#define MAP_SHAMD5HMACPPKeySet \ - SHAMD5HMACPPKeySet -#endif -#ifdef ROM_SHAMD5HMACProcess -#define MAP_SHAMD5HMACProcess \ - ROM_SHAMD5HMACProcess -#else -#define MAP_SHAMD5HMACProcess \ - SHAMD5HMACProcess -#endif -#ifdef ROM_SHAMD5IntClear -#define MAP_SHAMD5IntClear \ - ROM_SHAMD5IntClear -#else -#define MAP_SHAMD5IntClear \ - SHAMD5IntClear -#endif -#ifdef ROM_SHAMD5IntDisable -#define MAP_SHAMD5IntDisable \ - ROM_SHAMD5IntDisable -#else -#define MAP_SHAMD5IntDisable \ - SHAMD5IntDisable -#endif -#ifdef ROM_SHAMD5IntEnable -#define MAP_SHAMD5IntEnable \ - ROM_SHAMD5IntEnable -#else -#define MAP_SHAMD5IntEnable \ - SHAMD5IntEnable -#endif -#ifdef ROM_SHAMD5IntRegister -#define MAP_SHAMD5IntRegister \ - ROM_SHAMD5IntRegister -#else -#define MAP_SHAMD5IntRegister \ - SHAMD5IntRegister -#endif -#ifdef ROM_SHAMD5IntStatus -#define MAP_SHAMD5IntStatus \ - ROM_SHAMD5IntStatus -#else -#define MAP_SHAMD5IntStatus \ - SHAMD5IntStatus -#endif -#ifdef ROM_SHAMD5IntUnregister -#define MAP_SHAMD5IntUnregister \ - ROM_SHAMD5IntUnregister -#else -#define MAP_SHAMD5IntUnregister \ - SHAMD5IntUnregister -#endif -#ifdef ROM_SHAMD5ResultRead -#define MAP_SHAMD5ResultRead \ - ROM_SHAMD5ResultRead -#else -#define MAP_SHAMD5ResultRead \ - SHAMD5ResultRead -#endif - -//***************************************************************************** -// -// Macros for the CRC API. -// -//***************************************************************************** -#ifdef ROM_CRCConfigSet -#define MAP_CRCConfigSet \ - ROM_CRCConfigSet -#else -#define MAP_CRCConfigSet \ - CRCConfigSet -#endif -#ifdef ROM_CRCDataProcess -#define MAP_CRCDataProcess \ - ROM_CRCDataProcess -#else -#define MAP_CRCDataProcess \ - CRCDataProcess -#endif -#ifdef ROM_CRCDataWrite -#define MAP_CRCDataWrite \ - ROM_CRCDataWrite -#else -#define MAP_CRCDataWrite \ - CRCDataWrite -#endif -#ifdef ROM_CRCResultRead -#define MAP_CRCResultRead \ - ROM_CRCResultRead -#else -#define MAP_CRCResultRead \ - CRCResultRead -#endif -#ifdef ROM_CRCSeedSet -#define MAP_CRCSeedSet \ - ROM_CRCSeedSet -#else -#define MAP_CRCSeedSet \ - CRCSeedSet -#endif - -//***************************************************************************** -// -// Macros for the SDHOST API. -// -//***************************************************************************** -#ifdef ROM_SDHostCmdReset -#define MAP_SDHostCmdReset \ - ROM_SDHostCmdReset -#else -#define MAP_SDHostCmdReset \ - SDHostCmdReset -#endif -#ifdef ROM_SDHostInit -#define MAP_SDHostInit \ - ROM_SDHostInit -#else -#define MAP_SDHostInit \ - SDHostInit -#endif -#ifdef ROM_SDHostCmdSend -#define MAP_SDHostCmdSend \ - ROM_SDHostCmdSend -#else -#define MAP_SDHostCmdSend \ - SDHostCmdSend -#endif -#ifdef ROM_SDHostIntRegister -#define MAP_SDHostIntRegister \ - ROM_SDHostIntRegister -#else -#define MAP_SDHostIntRegister \ - SDHostIntRegister -#endif -#ifdef ROM_SDHostIntUnregister -#define MAP_SDHostIntUnregister \ - ROM_SDHostIntUnregister -#else -#define MAP_SDHostIntUnregister \ - SDHostIntUnregister -#endif -#ifdef ROM_SDHostIntEnable -#define MAP_SDHostIntEnable \ - ROM_SDHostIntEnable -#else -#define MAP_SDHostIntEnable \ - SDHostIntEnable -#endif -#ifdef ROM_SDHostIntDisable -#define MAP_SDHostIntDisable \ - ROM_SDHostIntDisable -#else -#define MAP_SDHostIntDisable \ - SDHostIntDisable -#endif -#ifdef ROM_SDHostIntStatus -#define MAP_SDHostIntStatus \ - ROM_SDHostIntStatus -#else -#define MAP_SDHostIntStatus \ - SDHostIntStatus -#endif -#ifdef ROM_SDHostIntClear -#define MAP_SDHostIntClear \ - ROM_SDHostIntClear -#else -#define MAP_SDHostIntClear \ - SDHostIntClear -#endif -#ifdef ROM_SDHostRespGet -#define MAP_SDHostRespGet \ - ROM_SDHostRespGet -#else -#define MAP_SDHostRespGet \ - SDHostRespGet -#endif -#ifdef ROM_SDHostBlockSizeSet -#define MAP_SDHostBlockSizeSet \ - ROM_SDHostBlockSizeSet -#else -#define MAP_SDHostBlockSizeSet \ - SDHostBlockSizeSet -#endif -#ifdef ROM_SDHostBlockCountSet -#define MAP_SDHostBlockCountSet \ - ROM_SDHostBlockCountSet -#else -#define MAP_SDHostBlockCountSet \ - SDHostBlockCountSet -#endif -#ifdef ROM_SDHostDataNonBlockingWrite -#define MAP_SDHostDataNonBlockingWrite \ - ROM_SDHostDataNonBlockingWrite -#else -#define MAP_SDHostDataNonBlockingWrite \ - SDHostDataNonBlockingWrite -#endif -#ifdef ROM_SDHostDataNonBlockingRead -#define MAP_SDHostDataNonBlockingRead \ - ROM_SDHostDataNonBlockingRead -#else -#define MAP_SDHostDataNonBlockingRead \ - SDHostDataNonBlockingRead -#endif -#ifdef ROM_SDHostDataWrite -#define MAP_SDHostDataWrite \ - ROM_SDHostDataWrite -#else -#define MAP_SDHostDataWrite \ - SDHostDataWrite -#endif -#ifdef ROM_SDHostDataRead -#define MAP_SDHostDataRead \ - ROM_SDHostDataRead -#else -#define MAP_SDHostDataRead \ - SDHostDataRead -#endif -#ifdef ROM_SDHostSetExpClk -#define MAP_SDHostSetExpClk \ - ROM_SDHostSetExpClk -#else -#define MAP_SDHostSetExpClk \ - SDHostSetExpClk -#endif -#ifdef ROM_SDHostCardErrorMaskSet -#define MAP_SDHostCardErrorMaskSet \ - ROM_SDHostCardErrorMaskSet -#else -#define MAP_SDHostCardErrorMaskSet \ - SDHostCardErrorMaskSet -#endif -#ifdef ROM_SDHostCardErrorMaskGet -#define MAP_SDHostCardErrorMaskGet \ - ROM_SDHostCardErrorMaskGet -#else -#define MAP_SDHostCardErrorMaskGet \ - SDHostCardErrorMaskGet -#endif - -//***************************************************************************** -// -// Macros for the PRCM API. -// -//***************************************************************************** -#ifdef ROM_PRCMMCUReset -#define MAP_PRCMMCUReset \ - ROM_PRCMMCUReset -#else -#define MAP_PRCMMCUReset \ - PRCMMCUReset -#endif -#ifdef ROM_PRCMSysResetCauseGet -#define MAP_PRCMSysResetCauseGet \ - ROM_PRCMSysResetCauseGet -#else -#define MAP_PRCMSysResetCauseGet \ - PRCMSysResetCauseGet -#endif -#ifdef ROM_PRCMPeripheralClkEnable -#define MAP_PRCMPeripheralClkEnable \ - ROM_PRCMPeripheralClkEnable -#else -#define MAP_PRCMPeripheralClkEnable \ - PRCMPeripheralClkEnable -#endif -#ifdef ROM_PRCMPeripheralClkDisable -#define MAP_PRCMPeripheralClkDisable \ - ROM_PRCMPeripheralClkDisable -#else -#define MAP_PRCMPeripheralClkDisable \ - PRCMPeripheralClkDisable -#endif -#ifdef ROM_PRCMPeripheralReset -#define MAP_PRCMPeripheralReset \ - ROM_PRCMPeripheralReset -#else -#define MAP_PRCMPeripheralReset \ - PRCMPeripheralReset -#endif -#ifdef ROM_PRCMPeripheralStatusGet -#define MAP_PRCMPeripheralStatusGet \ - ROM_PRCMPeripheralStatusGet -#else -#define MAP_PRCMPeripheralStatusGet \ - PRCMPeripheralStatusGet -#endif -#ifdef ROM_PRCMI2SClockFreqSet -#define MAP_PRCMI2SClockFreqSet \ - ROM_PRCMI2SClockFreqSet -#else -#define MAP_PRCMI2SClockFreqSet \ - PRCMI2SClockFreqSet -#endif -#ifdef ROM_PRCMPeripheralClockGet -#define MAP_PRCMPeripheralClockGet \ - ROM_PRCMPeripheralClockGet -#else -#define MAP_PRCMPeripheralClockGet \ - PRCMPeripheralClockGet -#endif -#ifdef ROM_PRCMSleepEnter -#define MAP_PRCMSleepEnter \ - ROM_PRCMSleepEnter -#else -#define MAP_PRCMSleepEnter \ - PRCMSleepEnter -#endif -#ifdef ROM_PRCMSRAMRetentionEnable -#define MAP_PRCMSRAMRetentionEnable \ - ROM_PRCMSRAMRetentionEnable -#else -#define MAP_PRCMSRAMRetentionEnable \ - PRCMSRAMRetentionEnable -#endif -#ifdef ROM_PRCMSRAMRetentionDisable -#define MAP_PRCMSRAMRetentionDisable \ - ROM_PRCMSRAMRetentionDisable -#else -#define MAP_PRCMSRAMRetentionDisable \ - PRCMSRAMRetentionDisable -#endif -#ifdef ROM_PRCMLPDSEnter -#define MAP_PRCMLPDSEnter \ - ROM_PRCMLPDSEnter -#else -#define MAP_PRCMLPDSEnter \ - PRCMLPDSEnter -#endif -#ifdef ROM_PRCMLPDSIntervalSet -#define MAP_PRCMLPDSIntervalSet \ - ROM_PRCMLPDSIntervalSet -#else -#define MAP_PRCMLPDSIntervalSet \ - PRCMLPDSIntervalSet -#endif -#ifdef ROM_PRCMLPDSWakeupSourceEnable -#define MAP_PRCMLPDSWakeupSourceEnable \ - ROM_PRCMLPDSWakeupSourceEnable -#else -#define MAP_PRCMLPDSWakeupSourceEnable \ - PRCMLPDSWakeupSourceEnable -#endif -#ifdef ROM_PRCMLPDSWakeupCauseGet -#define MAP_PRCMLPDSWakeupCauseGet \ - ROM_PRCMLPDSWakeupCauseGet -#else -#define MAP_PRCMLPDSWakeupCauseGet \ - PRCMLPDSWakeupCauseGet -#endif -#ifdef ROM_PRCMLPDSWakeUpGPIOSelect -#define MAP_PRCMLPDSWakeUpGPIOSelect \ - ROM_PRCMLPDSWakeUpGPIOSelect -#else -#define MAP_PRCMLPDSWakeUpGPIOSelect \ - PRCMLPDSWakeUpGPIOSelect -#endif -#ifdef ROM_PRCMLPDSWakeupSourceDisable -#define MAP_PRCMLPDSWakeupSourceDisable \ - ROM_PRCMLPDSWakeupSourceDisable -#else -#define MAP_PRCMLPDSWakeupSourceDisable \ - PRCMLPDSWakeupSourceDisable -#endif -#ifdef ROM_PRCMHibernateEnter -#define MAP_PRCMHibernateEnter \ - ROM_PRCMHibernateEnter -#else -#define MAP_PRCMHibernateEnter \ - PRCMHibernateEnter -#endif -#ifdef ROM_PRCMHibernateWakeupSourceEnable -#define MAP_PRCMHibernateWakeupSourceEnable \ - ROM_PRCMHibernateWakeupSourceEnable -#else -#define MAP_PRCMHibernateWakeupSourceEnable \ - PRCMHibernateWakeupSourceEnable -#endif -#ifdef ROM_PRCMHibernateWakeupCauseGet -#define MAP_PRCMHibernateWakeupCauseGet \ - ROM_PRCMHibernateWakeupCauseGet -#else -#define MAP_PRCMHibernateWakeupCauseGet \ - PRCMHibernateWakeupCauseGet -#endif -#ifdef ROM_PRCMHibernateWakeUpGPIOSelect -#define MAP_PRCMHibernateWakeUpGPIOSelect \ - ROM_PRCMHibernateWakeUpGPIOSelect -#else -#define MAP_PRCMHibernateWakeUpGPIOSelect \ - PRCMHibernateWakeUpGPIOSelect -#endif -#ifdef ROM_PRCMHibernateWakeupSourceDisable -#define MAP_PRCMHibernateWakeupSourceDisable \ - ROM_PRCMHibernateWakeupSourceDisable -#else -#define MAP_PRCMHibernateWakeupSourceDisable \ - PRCMHibernateWakeupSourceDisable -#endif -#ifdef ROM_PRCMHibernateIntervalSet -#define MAP_PRCMHibernateIntervalSet \ - ROM_PRCMHibernateIntervalSet -#else -#define MAP_PRCMHibernateIntervalSet \ - PRCMHibernateIntervalSet -#endif -#ifdef ROM_PRCMSlowClkCtrGet -#define MAP_PRCMSlowClkCtrGet \ - ROM_PRCMSlowClkCtrGet -#else -#define MAP_PRCMSlowClkCtrGet \ - PRCMSlowClkCtrGet -#endif -#ifdef ROM_PRCMSlowClkCtrMatchSet -#define MAP_PRCMSlowClkCtrMatchSet \ - ROM_PRCMSlowClkCtrMatchSet -#else -#define MAP_PRCMSlowClkCtrMatchSet \ - PRCMSlowClkCtrMatchSet -#endif -#ifdef ROM_PRCMSlowClkCtrMatchGet -#define MAP_PRCMSlowClkCtrMatchGet \ - ROM_PRCMSlowClkCtrMatchGet -#else -#define MAP_PRCMSlowClkCtrMatchGet \ - PRCMSlowClkCtrMatchGet -#endif -#ifdef ROM_PRCMOCRRegisterWrite -#define MAP_PRCMOCRRegisterWrite \ - ROM_PRCMOCRRegisterWrite -#else -#define MAP_PRCMOCRRegisterWrite \ - PRCMOCRRegisterWrite -#endif -#ifdef ROM_PRCMOCRRegisterRead -#define MAP_PRCMOCRRegisterRead \ - ROM_PRCMOCRRegisterRead -#else -#define MAP_PRCMOCRRegisterRead \ - PRCMOCRRegisterRead -#endif -#ifdef ROM_PRCMIntRegister -#define MAP_PRCMIntRegister \ - ROM_PRCMIntRegister -#else -#define MAP_PRCMIntRegister \ - PRCMIntRegister -#endif -#ifdef ROM_PRCMIntUnregister -#define MAP_PRCMIntUnregister \ - ROM_PRCMIntUnregister -#else -#define MAP_PRCMIntUnregister \ - PRCMIntUnregister -#endif -#ifdef ROM_PRCMIntEnable -#define MAP_PRCMIntEnable \ - ROM_PRCMIntEnable -#else -#define MAP_PRCMIntEnable \ - PRCMIntEnable -#endif -#ifdef ROM_PRCMIntDisable -#define MAP_PRCMIntDisable \ - ROM_PRCMIntDisable -#else -#define MAP_PRCMIntDisable \ - PRCMIntDisable -#endif -#ifdef ROM_PRCMIntStatus -#define MAP_PRCMIntStatus \ - ROM_PRCMIntStatus -#else -#define MAP_PRCMIntStatus \ - PRCMIntStatus -#endif -#ifdef ROM_PRCMRTCInUseSet -#define MAP_PRCMRTCInUseSet \ - ROM_PRCMRTCInUseSet -#else -#define MAP_PRCMRTCInUseSet \ - PRCMRTCInUseSet -#endif -#ifdef ROM_PRCMRTCInUseGet -#define MAP_PRCMRTCInUseGet \ - ROM_PRCMRTCInUseGet -#else -#define MAP_PRCMRTCInUseGet \ - PRCMRTCInUseGet -#endif -#ifdef ROM_PRCMRTCSet -#define MAP_PRCMRTCSet \ - ROM_PRCMRTCSet -#else -#define MAP_PRCMRTCSet \ - PRCMRTCSet -#endif -#ifdef ROM_PRCMRTCGet -#define MAP_PRCMRTCGet \ - ROM_PRCMRTCGet -#else -#define MAP_PRCMRTCGet \ - PRCMRTCGet -#endif -#ifdef ROM_PRCMRTCMatchSet -#define MAP_PRCMRTCMatchSet \ - ROM_PRCMRTCMatchSet -#else -#define MAP_PRCMRTCMatchSet \ - PRCMRTCMatchSet -#endif -#ifdef ROM_PRCMRTCMatchGet -#define MAP_PRCMRTCMatchGet \ - ROM_PRCMRTCMatchGet -#else -#define MAP_PRCMRTCMatchGet \ - PRCMRTCMatchGet -#endif -#ifdef ROM_PRCMLPDSRestoreInfoSet -#define MAP_PRCMLPDSRestoreInfoSet \ - ROM_PRCMLPDSRestoreInfoSet -#else -#define MAP_PRCMLPDSRestoreInfoSet \ - PRCMLPDSRestoreInfoSet -#endif -#ifdef ROM_PRCMSlowClkCtrFastGet -#define MAP_PRCMSlowClkCtrFastGet \ - ROM_PRCMSlowClkCtrFastGet -#else -#define MAP_PRCMSlowClkCtrFastGet \ - PRCMSlowClkCtrFastGet -#endif -#ifdef ROM_PRCMCC3200MCUInit -#define MAP_PRCMCC3200MCUInit \ - ROM_PRCMCC3200MCUInit -#else -#define MAP_PRCMCC3200MCUInit \ - PRCMCC3200MCUInit -#endif -#ifdef ROM_PRCMHIBRegRead -#define MAP_PRCMHIBRegRead \ - ROM_PRCMHIBRegRead -#else -#define MAP_PRCMHIBRegRead \ - PRCMHIBRegRead -#endif -#ifdef ROM_PRCMHIBRegWrite -#define MAP_PRCMHIBRegWrite \ - ROM_PRCMHIBRegWrite -#else -#define MAP_PRCMHIBRegWrite \ - PRCMHIBRegWrite -#endif -#ifdef ROM_PRCMCameraFreqSet -#define MAP_PRCMCameraFreqSet \ - ROM_PRCMCameraFreqSet -#else -#define MAP_PRCMCameraFreqSet \ - PRCMCameraFreqSet -#endif -#ifdef ROM_PRCMIORetentionEnable -#define MAP_PRCMIORetentionEnable \ - ROM_PRCMIORetentionEnable -#else -#define MAP_PRCMIORetentionEnable \ - PRCMIORetentionEnable -#endif -#ifdef ROM_PRCMIORetentionDisable -#define MAP_PRCMIORetentionDisable \ - ROM_PRCMIORetentionDisable -#else -#define MAP_PRCMIORetentionDisable \ - PRCMIORetentionDisable -#endif -#ifdef ROM_PRCMDeviceTypeGet -#define MAP_PRCMDeviceTypeGet \ - ROM_PRCMDeviceTypeGet -#else -#define MAP_PRCMDeviceTypeGet \ - PRCMDeviceTypeGet -#endif -#ifdef ROM_PRCMLPDSEnterKeepDebugIf -#define MAP_PRCMLPDSEnterKeepDebugIf \ - ROM_PRCMLPDSEnterKeepDebugIf -#else -#define MAP_PRCMLPDSEnterKeepDebugIf \ - PRCMLPDSEnterKeepDebugIf -#endif -#ifdef ROM_PRCMHibernateCycleTrigger -#define MAP_PRCMHibernateCycleTrigger \ - ROM_PRCMHibernateCycleTrigger -#else -#define MAP_PRCMHibernateCycleTrigger \ - PRCMHibernateCycleTrigger -#endif - -//***************************************************************************** -// -// Macros for the HWSPINLOCK API. -// -//***************************************************************************** -#ifdef ROM_HwSpinLockAcquire -#define MAP_HwSpinLockAcquire \ - ROM_HwSpinLockAcquire -#else -#define MAP_HwSpinLockAcquire \ - HwSpinLockAcquire -#endif -#ifdef ROM_HwSpinLockTryAcquire -#define MAP_HwSpinLockTryAcquire \ - ROM_HwSpinLockTryAcquire -#else -#define MAP_HwSpinLockTryAcquire \ - HwSpinLockTryAcquire -#endif -#ifdef ROM_HwSpinLockRelease -#define MAP_HwSpinLockRelease \ - ROM_HwSpinLockRelease -#else -#define MAP_HwSpinLockRelease \ - HwSpinLockRelease -#endif -#ifdef ROM_HwSpinLockTest -#define MAP_HwSpinLockTest \ - ROM_HwSpinLockTest -#else -#define MAP_HwSpinLockTest \ - HwSpinLockTest -#endif - -//***************************************************************************** -// -// Macros for the ADC API. -// -//***************************************************************************** -#ifdef ROM_ADCEnable -#define MAP_ADCEnable \ - ROM_ADCEnable -#else -#define MAP_ADCEnable \ - ADCEnable -#endif -#ifdef ROM_ADCDisable -#define MAP_ADCDisable \ - ROM_ADCDisable -#else -#define MAP_ADCDisable \ - ADCDisable -#endif -#ifdef ROM_ADCChannelEnable -#define MAP_ADCChannelEnable \ - ROM_ADCChannelEnable -#else -#define MAP_ADCChannelEnable \ - ADCChannelEnable -#endif -#ifdef ROM_ADCChannelDisable -#define MAP_ADCChannelDisable \ - ROM_ADCChannelDisable -#else -#define MAP_ADCChannelDisable \ - ADCChannelDisable -#endif -#ifdef ROM_ADCIntRegister -#define MAP_ADCIntRegister \ - ROM_ADCIntRegister -#else -#define MAP_ADCIntRegister \ - ADCIntRegister -#endif -#ifdef ROM_ADCIntUnregister -#define MAP_ADCIntUnregister \ - ROM_ADCIntUnregister -#else -#define MAP_ADCIntUnregister \ - ADCIntUnregister -#endif -#ifdef ROM_ADCIntEnable -#define MAP_ADCIntEnable \ - ROM_ADCIntEnable -#else -#define MAP_ADCIntEnable \ - ADCIntEnable -#endif -#ifdef ROM_ADCIntDisable -#define MAP_ADCIntDisable \ - ROM_ADCIntDisable -#else -#define MAP_ADCIntDisable \ - ADCIntDisable -#endif -#ifdef ROM_ADCIntStatus -#define MAP_ADCIntStatus \ - ROM_ADCIntStatus -#else -#define MAP_ADCIntStatus \ - ADCIntStatus -#endif -#ifdef ROM_ADCIntClear -#define MAP_ADCIntClear \ - ROM_ADCIntClear -#else -#define MAP_ADCIntClear \ - ADCIntClear -#endif -#ifdef ROM_ADCDMAEnable -#define MAP_ADCDMAEnable \ - ROM_ADCDMAEnable -#else -#define MAP_ADCDMAEnable \ - ADCDMAEnable -#endif -#ifdef ROM_ADCDMADisable -#define MAP_ADCDMADisable \ - ROM_ADCDMADisable -#else -#define MAP_ADCDMADisable \ - ADCDMADisable -#endif -#ifdef ROM_ADCTimerConfig -#define MAP_ADCTimerConfig \ - ROM_ADCTimerConfig -#else -#define MAP_ADCTimerConfig \ - ADCTimerConfig -#endif -#ifdef ROM_ADCTimerEnable -#define MAP_ADCTimerEnable \ - ROM_ADCTimerEnable -#else -#define MAP_ADCTimerEnable \ - ADCTimerEnable -#endif -#ifdef ROM_ADCTimerDisable -#define MAP_ADCTimerDisable \ - ROM_ADCTimerDisable -#else -#define MAP_ADCTimerDisable \ - ADCTimerDisable -#endif -#ifdef ROM_ADCTimerReset -#define MAP_ADCTimerReset \ - ROM_ADCTimerReset -#else -#define MAP_ADCTimerReset \ - ADCTimerReset -#endif -#ifdef ROM_ADCTimerValueGet -#define MAP_ADCTimerValueGet \ - ROM_ADCTimerValueGet -#else -#define MAP_ADCTimerValueGet \ - ADCTimerValueGet -#endif -#ifdef ROM_ADCFIFOLvlGet -#define MAP_ADCFIFOLvlGet \ - ROM_ADCFIFOLvlGet -#else -#define MAP_ADCFIFOLvlGet \ - ADCFIFOLvlGet -#endif -#ifdef ROM_ADCFIFORead -#define MAP_ADCFIFORead \ - ROM_ADCFIFORead -#else -#define MAP_ADCFIFORead \ - ADCFIFORead -#endif - -//***************************************************************************** -// -// Macros for the CPU API. -// -//***************************************************************************** -#ifdef ROM_CPUcpsid -#define MAP_CPUcpsid \ - ROM_CPUcpsid -#else -#define MAP_CPUcpsid \ - CPUcpsid -#endif -#ifdef ROM_CPUcpsie -#define MAP_CPUcpsie \ - ROM_CPUcpsie -#else -#define MAP_CPUcpsie \ - CPUcpsie -#endif -#ifdef ROM_CPUprimask -#define MAP_CPUprimask \ - ROM_CPUprimask -#else -#define MAP_CPUprimask \ - CPUprimask -#endif -#ifdef ROM_CPUwfi -#define MAP_CPUwfi \ - ROM_CPUwfi -#else -#define MAP_CPUwfi \ - CPUwfi -#endif -#ifdef ROM_CPUbasepriGet -#define MAP_CPUbasepriGet \ - ROM_CPUbasepriGet -#else -#define MAP_CPUbasepriGet \ - CPUbasepriGet -#endif -#ifdef ROM_CPUbasepriSet -#define MAP_CPUbasepriSet \ - ROM_CPUbasepriSet -#else -#define MAP_CPUbasepriSet \ - CPUbasepriSet -#endif - -#endif // __ROM_MAP_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/rom_patch.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/rom_patch.h deleted file mode 100644 index 241bce28b9d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/rom_patch.h +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// rom_patch.h - Macros to facilitate patching driverlib API's in the ROM. -// -// - -//***************************************************************************** -// -// List of API's in the ROM that need to be patched. -// For e.g. to patch ROM_UARTCharPut add the line #undef ROM_UARTCharPut -//***************************************************************************** - -#ifndef __ROM_PATCH_H__ -#define __ROM_PATCH_H__ - -#if defined(TARGET_IS_CC3200) || defined(USE_CC3200_ROM_DRV_API) -#undef ROM_ADCIntClear -#undef ROM_IntEnable -#undef ROM_IntDisable -#undef ROM_IntPendSet -#undef ROM_SDHostCardErrorMaskSet -#undef ROM_SDHostCardErrorMaskGet -#undef ROM_TimerConfigure -#undef ROM_TimerDMAEventSet -#undef ROM_TimerDMAEventGet -#undef ROM_SDHostDataNonBlockingWrite -#undef ROM_SDHostDataWrite -#undef ROM_SDHostDataRead -#undef ROM_SDHostDataNonBlockingRead -#undef ROM_PRCMSysResetCauseGet -#undef ROM_PRCMPeripheralClkEnable -#undef ROM_PRCMLPDSWakeUpGPIOSelect -#undef ROM_PRCMHibernateWakeupSourceEnable -#undef ROM_PRCMHibernateWakeupSourceDisable -#undef ROM_PRCMHibernateWakeupCauseGet -#undef ROM_PRCMHibernateIntervalSet -#undef ROM_PRCMHibernateWakeUpGPIOSelect -#undef ROM_PRCMHibernateEnter -#undef ROM_PRCMSlowClkCtrGet -#undef ROM_PRCMSlowClkCtrMatchSet -#undef ROM_PRCMSlowClkCtrMatchGet -#undef ROM_PRCMOCRRegisterWrite -#undef ROM_PRCMOCRRegisterRead -#undef ROM_PRCMIntEnable -#undef ROM_PRCMIntDisable -#undef ROM_PRCMRTCInUseSet -#undef ROM_PRCMRTCInUseGet -#undef ROM_PRCMRTCSet -#undef ROM_PRCMRTCGet -#undef ROM_PRCMRTCMatchSet -#undef ROM_PRCMRTCMatchGet -#undef ROM_PRCMPeripheralClkDisable -#undef ROM_PRCMPeripheralReset -#undef ROM_PRCMPeripheralStatusGet -#undef ROM_SPIConfigSetExpClk -#undef ROM_AESDataProcess -#undef ROM_DESDataProcess -#undef ROM_I2SEnable -#undef ROM_I2SConfigSetExpClk -#undef ROM_PinConfigSet -#undef ROM_PRCMLPDSEnter -#undef ROM_PRCMCC3200MCUInit -#undef ROM_SDHostIntStatus -#undef ROM_SDHostBlockCountSet -#undef ROM_UARTModemControlSet -#undef ROM_UARTModemControlClear -#undef ROM_CameraXClkSet -#undef ROM_PRCMMCUReset -#undef ROM_PRCMPeripheralClkEnable -#undef ROM_SPIDmaDisable -#undef ROM_PRCMPeripheralClockGet -#endif - -#if defined(USE_CC3220_ROM_DRV_API) -#undef ROM_PRCMDeviceTypeGet -#undef ROM_SDHostDataNonBlockingRead -#undef ROM_PRCMIORetentionEnable -#undef ROM_PRCMIORetentionDisable -#undef ROM_PRCMPeripheralClockGet -#undef ROM_PRCMCC3200MCUInit -#undef ROM_SHAMD5ConfigSet -#undef ROM_SHAMD5HMACKeySet -#undef ROM_PinConfigSet -#undef ROM_PinModeSet -#endif - -#endif // __ROM_PATCH_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/sdhost.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/sdhost.c deleted file mode 100644 index 722f46285b7..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/sdhost.c +++ /dev/null @@ -1,745 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// sdhost.c -// -// Driver for the SD Host (SDHost) Interface -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup Secure_Digital_Host_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_types.h" -#include "inc/hw_memmap.h" -#include "inc/hw_mmchs.h" -#include "inc/hw_ints.h" -#include "inc/hw_apps_config.h" -#include "interrupt.h" -#include "sdhost.h" - - -//***************************************************************************** -// -//! Configures SDHost module. -//! -//! \param ulBase is the base address of SDHost module. -//! -//! This function configures the SDHost module, enabling internal sub-modules. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostInit(unsigned long ulBase) -{ - // - // Assert module reset - // - HWREG(ulBase + MMCHS_O_SYSCONFIG) = 0x2; - - // - // Wait for soft reset to complete - // - while( !(HWREG(ulBase + MMCHS_O_SYSCONFIG) & 0x1) ) - { - - } - - // - // Assert internal reset - // - HWREG(ulBase + MMCHS_O_SYSCTL) |= (1 << 24); - - // - // Wait for Reset to complete - // - while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (0x1 << 24)) ) - { - - } - - // - // Set capability register, 1.8 and 3.0 V - // - HWREG(ulBase + MMCHS_O_CAPA) = (0x7 <<24); - - // - // Select bus voltage, 3.0 V - // - HWREG(ulBase + MMCHS_O_HCTL) |= 0x7 << 9; - - // - // Power up the bus - // - HWREG(ulBase + MMCHS_O_HCTL) |= 1 << 8; - - // - // Wait for power on - // - while( !(HWREG(ulBase + MMCHS_O_HCTL) & (1<<8)) ) - { - - } - - HWREG(ulBase + MMCHS_O_CON) |= 1 << 21; - - // - // Un-mask all events - // - HWREG(ulBase + MMCHS_O_IE) = 0xFFFFFFFF; -} - - -//***************************************************************************** -// -//! Resets SDHost command line -//! -//! \param ulBase is the base address of SDHost module. -//! -//! This function assers a soft reset for the command line -//! -//! \return None. -// -//***************************************************************************** -void -SDHostCmdReset(unsigned long ulBase) -{ - HWREG(ulBase + MMCHS_O_SYSCTL) |= 1 << 25; - while( (HWREG(ulBase + MMCHS_O_SYSCTL) & (1 << 25)) ) - { - - } -} - -//***************************************************************************** -// -//! Sends command over SDHost interface -//! -//! \param ulBase is the base address of SDHost module. -//! \param ulCmd is the command to send. -//! \param ulArg is the argument for the command. -//! -//! This function send command to the attached card over the SDHost interface. -//! -//! The \e ulCmd parameter can be one of \b SDHOST_CMD_0 to \b SDHOST_CMD_63. -//! It can be logically ORed with one or more of the following: -//! - \b SDHOST_MULTI_BLK for multi-block transfer -//! - \b SDHOST_WR_CMD if command is followed by write data -//! - \b SDHOST_RD_CMD if command is followed by read data -//! - \b SDHOST_DMA_EN if SDHost need to generate DMA request. -//! - \b SDHOST_RESP_LEN_136 if 136 bit response is expected -//! - \b SDHOST_RESP_LEN_48 if 48 bit response is expected -//! - \b SDHOST_RESP_LEN_48B if 48 bit response with busy bit is expected -//! -//! The parameter \e ulArg is the argument for the command -//! -//! \return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -long -SDHostCmdSend(unsigned long ulBase, unsigned long ulCmd, unsigned ulArg) -{ - // - // Set Data Timeout - // - HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x000E0000; - - // - // Check for cmd inhabit - // - if( (HWREG(ulBase + MMCHS_O_PSTATE) & 0x1)) - { - return -1; - } - - // - // Set the argument - // - HWREG(ulBase + MMCHS_O_ARG) = ulArg; - - // - // Send the command - // - HWREG(ulBase + MMCHS_O_CMD) = ulCmd; - - return 0; -} - -//***************************************************************************** -// -//! Writes a data word into the SDHost write buffer. -//! -//! \param ulBase is the base address of SDHost module. -//! \param ulData is data word to be transfered. -//! -//! This function writes a single data word into the SDHost write buffer. The -//! function returns \b true if there was a space available in the buffer else -//! returns \b false. -//! -//! \return Return \b true on success, \b false otherwise. -// -//***************************************************************************** -tBoolean -SDHostDataNonBlockingWrite(unsigned long ulBase, unsigned long ulData) -{ - - // - // See if there is a space in the write buffer - // - if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) ) - { - // - // Write the data into the buffer - // - HWREG(ulBase + MMCHS_O_DATA) = ulData; - - // - // Success. - // - return(true); - } - else - { - // - // No free sapce, failure. - // - return(false); - } -} - -//***************************************************************************** -// -//! Waits to write a data word into the SDHost write buffer. -//! -//! \param ulBase is the base address of SDHost module. -//! \param ulData is data word to be transfered. -//! -//! This function writes \e ulData into the SDHost write buffer. If there is no -//! space in the write buffer this function waits until there is a space -//! available before returning. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostDataWrite(unsigned long ulBase, unsigned long ulData) -{ - // - // Wait until space is available - // - while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<10)) ) - { - - } - - // - // Write the data - // - HWREG(ulBase + MMCHS_O_DATA) = ulData; -} - - -//***************************************************************************** -// -//! Waits for a data word from the SDHost read buffer -//! -//! \param ulBase is the base address of SDHost module. -//! \param pulData is pointer to read data variable. -//! -//! This function reads a single data word from the SDHost read buffer. If there -//! is no data available in the buffer the function will wait until a data -//! word is received before returning. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostDataRead(unsigned long ulBase, unsigned long *pulData) -{ - // - // Wait until data is available - // - while( !(HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) ) - { - - } - - // - // Read the data - // - *pulData = HWREG(ulBase + MMCHS_O_DATA); -} - -//***************************************************************************** -// -//! Reads single data word from the SDHost read buffer -//! -//! \param ulBase is the base address of SDHost module. -//! \param pulData is pointer to read data variable. -//! -//! This function reads a data word from the SDHost read buffer. The -//! function returns \b true if there was data available in to buffer else -//! returns \b false. -//! -//! \return Return \b true on success, \b false otherwise. -// -//***************************************************************************** -tBoolean -SDHostDataNonBlockingRead(unsigned long ulBase, unsigned long *pulData) -{ - - // - // See if there is any data in the read buffer. - // - if( (HWREG(ulBase + MMCHS_O_PSTATE) & (1<<11)) ) - { - // - // Read the data word. - // - *pulData = HWREG(ulBase + MMCHS_O_DATA); - - // - // Success - // - return(true); - } - else - { - // - // No data available, failure. - // - return(false); - } -} - - -//***************************************************************************** -// -//! Registers the interrupt handler for SDHost interrupt -//! -//! \param ulBase is the base address of SDHost module -//! \param pfnHandler is a pointer to the function to be called when the -//! SDHost interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; specific -//! SDHost interrupts must be enabled via SDHostIntEnable(). It is the -//! interrupt handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler. - // - IntRegister(INT_MMCHS, pfnHandler); - - // - // Enable the SDHost interrupt. - // - IntEnable(INT_MMCHS); -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for SDHost interrupt -//! -//! \param ulBase is the base address of SDHost module -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a SDHost interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostIntUnregister(unsigned long ulBase) -{ - // - // Disable the SDHost interrupt. - // - IntDisable(INT_MMCHS); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_MMCHS); -} - -//***************************************************************************** -// -//! Enable individual interrupt source for the specified SDHost -//! -//! \param ulBase is the base address of SDHost module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated SDHost interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! - \b SDHOST_INT_CC Command Complete interrupt -//! - \b SDHOST_INT_TC Transfer Complete interrupt -//! - \b SDHOST_INT_BWR Buffer Write Ready interrupt -//! - \b SDHOST_INT_BRR Buffer Read Ready interrupt -//! - \b SDHOST_INT_ERRI Error interrupt -//! - \b SDHOST_INT_CTO Command Timeout error interrupt -//! - \b SDHOST_INT_CEB Command End Bit error interrupt -//! - \b SDHOST_INT_DTO Data Timeout error interrupt -//! - \b SDHOST_INT_DCRC Data CRC error interrupt -//! - \b SDHOST_INT_DEB Data End Bit error -//! - \b SDHOST_INT_CERR Cart Status Error interrupt -//! - \b SDHOST_INT_BADA Bad Data error interrupt -//! - \b SDHOST_INT_DMARD Read DMA done interrupt -//! - \b SDHOST_INT_DMAWR Write DMA done interrupt -//! -//! Note that SDHOST_INT_ERRI can only be used with \sa SDHostIntStatus() -//! and is internally logical OR of all error status bits. Setting this bit -//! alone as \e ulIntFlags doesn't generates any interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags) -{ - // - // Enable DMA done interrupts - // - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = - (ulIntFlags >> 30); - - // - // Enable the individual interrupt sources - // - HWREG(ulBase + MMCHS_O_ISE) |= (ulIntFlags & 0x3FFFFFFF); -} - -//***************************************************************************** -// -//! Enable individual interrupt source for the specified SDHost -//! -//! \param ulBase is the base address of SDHost module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled. -//! -//! This function disables the indicated SDHost interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to SDHostIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags) -{ - // - // Disable DMA done interrupts - // - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = - (ulIntFlags >> 30); - // - // Disable the individual interrupt sources - // - HWREG(ulBase + MMCHS_O_ISE) &= ~(ulIntFlags & 0x3FFFFFFF); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of SDHost module. -//! -//! This function returns the interrupt status for the specified SDHost. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in SDHostIntEnable(). -// -//***************************************************************************** -unsigned long -SDHostIntStatus(unsigned long ulBase) -{ - unsigned long ulIntStatus; - - // - // Get DMA done interrupt status - // - ulIntStatus = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW); - ulIntStatus = (ulIntStatus << 30); - - // - // Return the status of individual interrupt sources - // - ulIntStatus |= (HWREG(ulBase + MMCHS_O_STAT) & 0x3FFFFFFF); - - return(ulIntStatus); -} - -//***************************************************************************** -// -//! Clears the individual interrupt sources. -//! -//! \param ulBase is the base address of SDHost module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified SDHost interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to SDHostIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags) -{ - // - // Clear DMA done interrupts - // - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = - (ulIntFlags >> 30); - // - // Clear the individual interrupt sources - // - HWREG(ulBase + MMCHS_O_STAT) = (ulIntFlags & 0x3FFFFFFF); -} - -//***************************************************************************** -// -//! Sets the card status error mask. -//! -//! \param ulBase is the base address of SDHost module -//! \param ulErrMask is the bit mask of card status errors to be enabled -//! -//! This function sets the card status error mask for response type R1, R1b, -//! R5, R5b and R6 response. The parameter \e ulErrMask is the bit mask of card -//! status errors to be enabled, if the corresponding bits in the 'card status' -//! field of a respose are set then the host controller indicates a card error -//! interrupt status. Only bits referenced as type E (error) in status field in -//! the response can set a card status error. -//! -//! \return None -// -//***************************************************************************** -void -SDHostCardErrorMaskSet(unsigned long ulBase, unsigned long ulErrMask) -{ - // - // Set the card status error mask - // - HWREG(ulBase + MMCHS_O_CSRE) = ulErrMask; -} - - -//***************************************************************************** -// -//! Gets the card status error mask. -//! -//! \param ulBase is the base address of SDHost module -//! -//! This function gets the card status error mask for response type R1, R1b, -//! R5, R5b and R6 response. -//! -//! \return Returns the current card status error. -// -//***************************************************************************** -unsigned long -SDHostCardErrorMaskGet(unsigned long ulBase) -{ - // - // Return the card status error mask - // - return(HWREG(ulBase + MMCHS_O_CSRE)); -} - -//***************************************************************************** -// -//! Sets the SD Card clock. -//! -//! \param ulBase is the base address of SDHost module -//! \param ulSDHostClk is the rate of clock supplied to SDHost module -//! \param ulCardClk is the required SD interface clock -//! -//! This function configures the SDHost interface to supply the specified clock -//! to the connected card. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk, - unsigned long ulCardClk) -{ - unsigned long ulDiv; - - // - // Disable card clock - // - HWREG(ulBase + MMCHS_O_SYSCTL) &= ~0x4; - - // - // Enable internal clock - // - HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x1; - - ulDiv = ((ulSDHostClk/ulCardClk) & 0x3FF); - - // - // Set clock divider, - // - HWREG(ulBase + MMCHS_O_SYSCTL) = ((HWREG(ulBase + MMCHS_O_SYSCTL) & - ~0x0000FFC0)| (ulDiv) << 6); - - // - // Wait for clock to stablize - // - while( !(HWREG(ulBase + MMCHS_O_SYSCTL) & 0x2) ) - { - - } - - // - // Enable card clock - // - HWREG(ulBase + MMCHS_O_SYSCTL) |= 0x4; -} - -//***************************************************************************** -// -//! Get the response for the last command. -//! -//! \param ulBase is the base address of SDHost module -//! \param ulRespnse is 128-bit response. -//! -//! This function gets the response from the SD card for the last command -//! send. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]) -{ - - // - // Read the responses. - // - ulRespnse[0] = HWREG(ulBase + MMCHS_O_RSP10); - ulRespnse[1] = HWREG(ulBase + MMCHS_O_RSP32); - ulRespnse[2] = HWREG(ulBase + MMCHS_O_RSP54); - ulRespnse[3] = HWREG(ulBase + MMCHS_O_RSP76); - -} - -//***************************************************************************** -// -//! Set the block size for data transfer -//! -//! \param ulBase is the base address of SDHost module -//! \param ulBlkSize is the transfer block size in bytes -//! -//! This function sets the block size the data transfer. -//! -//! The parameter \e ulBlkSize is size of each data block in bytes. -//! This should be in range 0 - 2^10. -//! -//! \return None. -// -//***************************************************************************** -void -SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize) -{ - // - // Set the block size - // - HWREG(ulBase + MMCHS_O_BLK) = ((HWREG(ulBase + MMCHS_O_BLK) & 0x00000FFF)| - (ulBlkSize & 0xFFF)); -} - -//***************************************************************************** -// -//! Set the block size and count for data transfer -//! -//! \param ulBase is the base address of SDHost module -//! \param ulBlkCount is the number of blocks -//! -//! This function sets block count for the data transfer. This needs to be set -//! for each block transfer. \sa SDHostBlockSizeSet() -//! -//! \return None. -// -//***************************************************************************** -void -SDHostBlockCountSet(unsigned long ulBase, unsigned short ulBlkCount) -{ - unsigned long ulRegVal; - - // - // Read the current value - // - ulRegVal = HWREG(ulBase + MMCHS_O_BLK); - - // - // Set the number of blocks - // - HWREG(ulBase + MMCHS_O_BLK) = ((ulRegVal & 0x0000FFFF)| - (ulBlkCount << 16)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/sdhost.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/sdhost.h deleted file mode 100644 index 456f95865fe..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/sdhost.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// sdhost.h -// -// Defines and Macros for the SDHost. -// -//***************************************************************************** - -#ifndef __SDHOST_H__ -#define __SDHOST_H__ - - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -//{ -#endif - - -//***************************************************************************** -// Values that can be passed to SDHostRespGet(). -//***************************************************************************** -#define SDHOST_RESP_10 0x00000003 -#define SDHOST_RESP_32 0x00000002 -#define SDHOST_RESP_54 0x00000001 -#define SDHOST_RESP_76 0x00000000 - - -//***************************************************************************** -// Values that can be passed to SDHostIntEnable(), SDHostIntDisable(), -// SDHostIntClear() ,and returned from SDHostIntStatus(). -//***************************************************************************** -#define SDHOST_INT_CC 0x00000001 -#define SDHOST_INT_TC 0x00000002 -#define SDHOST_INT_BWR 0x00000010 -#define SDHOST_INT_BRR 0x00000020 -#define SDHOST_INT_ERRI 0x00008000 -#define SDHOST_INT_CTO 0x00010000 -#define SDHOST_INT_CEB 0x00040000 -#define SDHOST_INT_DTO 0x00100000 -#define SDHOST_INT_DCRC 0x00200000 -#define SDHOST_INT_DEB 0x00400000 -#define SDHOST_INT_CERR 0x10000000 -#define SDHOST_INT_BADA 0x20000000 -#define SDHOST_INT_DMARD 0x40000000 -#define SDHOST_INT_DMAWR 0x80000000 - -//***************************************************************************** -// Values that can be passed to SDHostCmdSend(). -//***************************************************************************** -#define SDHOST_CMD_0 0x00000000 -#define SDHOST_CMD_1 0x01000000 -#define SDHOST_CMD_2 0x02000000 -#define SDHOST_CMD_3 0x03000000 -#define SDHOST_CMD_4 0x04000000 -#define SDHOST_CMD_5 0x05000000 -#define SDHOST_CMD_6 0x06000000 -#define SDHOST_CMD_7 0x07000000 -#define SDHOST_CMD_8 0x08000000 -#define SDHOST_CMD_9 0x09000000 -#define SDHOST_CMD_10 0x0A000000 -#define SDHOST_CMD_11 0x0B000000 -#define SDHOST_CMD_12 0x0C000000 -#define SDHOST_CMD_13 0x0D000000 -#define SDHOST_CMD_14 0x0E000000 -#define SDHOST_CMD_15 0x0F000000 -#define SDHOST_CMD_16 0x10000000 -#define SDHOST_CMD_17 0x11000000 -#define SDHOST_CMD_18 0x12000000 -#define SDHOST_CMD_19 0x13000000 -#define SDHOST_CMD_20 0x14000000 -#define SDHOST_CMD_21 0x15000000 -#define SDHOST_CMD_22 0x16000000 -#define SDHOST_CMD_23 0x17000000 -#define SDHOST_CMD_24 0x18000000 -#define SDHOST_CMD_25 0x19000000 -#define SDHOST_CMD_26 0x1A000000 -#define SDHOST_CMD_27 0x1B000000 -#define SDHOST_CMD_28 0x1C000000 -#define SDHOST_CMD_29 0x1D000000 -#define SDHOST_CMD_30 0x1E000000 -#define SDHOST_CMD_31 0x1F000000 -#define SDHOST_CMD_32 0x20000000 -#define SDHOST_CMD_33 0x21000000 -#define SDHOST_CMD_34 0x22000000 -#define SDHOST_CMD_35 0x23000000 -#define SDHOST_CMD_36 0x24000000 -#define SDHOST_CMD_37 0x25000000 -#define SDHOST_CMD_38 0x26000000 -#define SDHOST_CMD_39 0x27000000 -#define SDHOST_CMD_40 0x28000000 -#define SDHOST_CMD_41 0x29000000 -#define SDHOST_CMD_42 0x2A000000 -#define SDHOST_CMD_43 0x2B000000 -#define SDHOST_CMD_44 0x2C000000 -#define SDHOST_CMD_45 0x2D000000 -#define SDHOST_CMD_46 0x2E000000 -#define SDHOST_CMD_47 0x2F000000 -#define SDHOST_CMD_48 0x30000000 -#define SDHOST_CMD_49 0x31000000 -#define SDHOST_CMD_50 0x32000000 -#define SDHOST_CMD_51 0x33000000 -#define SDHOST_CMD_52 0x34000000 -#define SDHOST_CMD_53 0x35000000 -#define SDHOST_CMD_54 0x36000000 -#define SDHOST_CMD_55 0x37000000 -#define SDHOST_CMD_56 0x38000000 -#define SDHOST_CMD_57 0x39000000 -#define SDHOST_CMD_58 0x3A000000 -#define SDHOST_CMD_59 0x3B000000 -#define SDHOST_CMD_60 0x3C000000 -#define SDHOST_CMD_61 0x3D000000 -#define SDHOST_CMD_62 0x3E000000 -#define SDHOST_CMD_63 0x3F000000 - -//***************************************************************************** -// Values that can be logically ORed with ulCmd parameter for SDHostCmdSend(). -//***************************************************************************** -#define SDHOST_MULTI_BLK 0x00000022 -#define SDHOST_DMA_EN 0x00000001 -#define SDHOST_WR_CMD 0x00200000 -#define SDHOST_RD_CMD 0x00200010 -#define SDHOST_RESP_LEN_136 0x00010000 -#define SDHOST_RESP_LEN_48 0x00020000 -#define SDHOST_RESP_LEN_48B 0x00030000 - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void SDHostCmdReset(unsigned long ulBase); -extern void SDHostInit(unsigned long ulBase); -extern long SDHostCmdSend(unsigned long ulBase,unsigned long ulCmd, - unsigned ulArg); -extern void SDHostIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); -extern void SDHostIntUnregister(unsigned long ulBase); -extern void SDHostIntEnable(unsigned long ulBase,unsigned long ulIntFlags); -extern void SDHostIntDisable(unsigned long ulBase,unsigned long ulIntFlags); -extern unsigned long SDHostIntStatus(unsigned long ulBase); -extern void SDHostIntClear(unsigned long ulBase,unsigned long ulIntFlags); -extern void SDHostCardErrorMaskSet(unsigned long ulBase, - unsigned long ulErrMask); -extern unsigned long SDHostCardErrorMaskGet(unsigned long ulBase); -extern void SDHostSetExpClk(unsigned long ulBase, unsigned long ulSDHostClk, - unsigned long ulCardClk); -extern void SDHostRespGet(unsigned long ulBase, unsigned long ulRespnse[4]); -extern void SDHostBlockSizeSet(unsigned long ulBase, unsigned short ulBlkSize); -extern void SDHostBlockCountSet(unsigned long ulBase, - unsigned short ulBlkCount); -extern tBoolean SDHostDataNonBlockingWrite(unsigned long ulBase, - unsigned long ulData); -extern tBoolean SDHostDataNonBlockingRead(unsigned long ulBase, - unsigned long *pulData); -extern void SDHostDataWrite(unsigned long ulBase, unsigned long ulData); -extern void SDHostDataRead(unsigned long ulBase, unsigned long *ulData); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -//} -#endif - -#endif // __SDHOST_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/shamd5.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/shamd5.c deleted file mode 100644 index bf0b20621ed..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/shamd5.c +++ /dev/null @@ -1,1249 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// shamd5.c -// -// Driver for the SHA/MD5 module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup SHA_Secure_Hash_Algorithm_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_dthe.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_nvic.h" -#include "inc/hw_shamd5.h" -#include "inc/hw_types.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/shamd5.h" - -//***************************************************************************** -// -//! Enables the uDMA requests in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function configures the DMA options of the SHA/MD5 module. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5DMAEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Write the new configuration into the register. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= - SHAMD5_SYSCONFIG_PADVANCED | SHAMD5_SYSCONFIG_PDMA_EN; -} - -//***************************************************************************** -// -//! Disables the uDMA requests in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function configures the DMA options of the SHA/MD5 module. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5DMADisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Write the new configuration into the register. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= - ~(SHAMD5_SYSCONFIG_PADVANCED | SHAMD5_SYSCONFIG_PDMA_EN); -} - -//***************************************************************************** -// -//! Get the interrupt status of the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the current value of the IRQSTATUS register. The -//! value will be a logical OR of the following: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return Interrupt status -// -//***************************************************************************** -uint32_t -SHAMD5IntStatus(uint32_t ui32Base, bool bMasked) -{ - uint32_t ui32Temp; - uint32_t ui32IrqEnable; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Return the value of the IRQSTATUS register. - // - if(bMasked) - { - ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_MIS); - ui32IrqEnable = HWREG(ui32Base + SHAMD5_O_IRQENABLE); - return((HWREG(ui32Base + SHAMD5_O_IRQSTATUS) & - ui32IrqEnable) | (ui32Temp & 0x00000007) << 16); - } - else - { - ui32Temp = HWREG(DTHE_BASE + DTHE_O_SHA_RIS); - return(HWREG(ui32Base + SHAMD5_O_IRQSTATUS) | - (ui32Temp & 0x00000007) << 16); - - } -} - -//***************************************************************************** -// -//! Enable interrupt sources in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32IntFlags contains desired interrupts to enable. -//! -//! This function enables interrupt sources in the SHA/MD5 module. -//! ui32IntFlags must be a logical OR of one or more of the following -//! values: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntEnable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || - (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || - (ui32IntFlags == SHAMD5_INT_INPUT_READY) || - (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); - - // - // Enable the interrupt sources. - // - HWREG(DTHE_BASE + DTHE_O_SHA_IM) &= ~((ui32IntFlags & 0x00070000) >> 16); - HWREG(ui32Base + SHAMD5_O_IRQENABLE) |= ui32IntFlags & 0x0000ffff; - - // - // Enable all interrupts. - // - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) |= SHAMD5_SYSCONFIG_PIT_EN; -} - -//***************************************************************************** -// -//! Disable interrupt sources in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32IntFlags contains desired interrupts to disable. -//! -//! \e ui32IntFlags must be a logical OR of one or more of the following -//! values: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntDisable(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || - (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || - (ui32IntFlags == SHAMD5_INT_INPUT_READY) || - (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); - - // - // Clear the corresponding flags disabling the interrupt sources. - // - HWREG(DTHE_BASE + DTHE_O_SHA_IM) |= ((ui32IntFlags & 0x00070000) >> 16); - HWREG(ui32Base + SHAMD5_O_IRQENABLE) &= ~(ui32IntFlags & 0x0000ffff); - - // - // If there are no interrupts enabled, then disable all interrupts. - // - if(HWREG(ui32Base + SHAMD5_O_IRQENABLE) == 0x0) - { - HWREG(ui32Base + SHAMD5_O_SYSCONFIG) &= ~SHAMD5_SYSCONFIG_PIT_EN; - } -} - -//***************************************************************************** -// -//! Clears interrupt sources in the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32IntFlags contains desired interrupts to disable. -//! -//! \e ui32IntFlags must be a logical OR of one or more of the following -//! values: -//! -//! - \b SHAMD5_INT_CONTEXT_READY - Context input registers are ready. -//! - \b SHAMD5_INT_PARTHASH_READY - Context output registers are ready after -//! a context switch. -//! - \b SHAMD5_INT_INPUT_READY - Data FIFO is ready to receive data. -//! - \b SHAMD5_INT_OUTPUT_READY - Context output registers are ready. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntClear(uint32_t ui32Base, uint32_t ui32IntFlags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32IntFlags == SHAMD5_INT_CONTEXT_READY) || - (ui32IntFlags == SHAMD5_INT_PARTHASH_READY) || - (ui32IntFlags == SHAMD5_INT_INPUT_READY) || - (ui32IntFlags == SHAMD5_INT_OUTPUT_READY)); - - // - // Clear the corresponding flags disabling the interrupt sources. - // - HWREG(DTHE_BASE + DTHE_O_SHA_IC) = ((ui32IntFlags & 0x00070000) >> 16); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param pfnHandler is a pointer to the function to be called when the -//! enabled SHA/MD5 interrupts occur. -//! -//! This function registers the interrupt handler in the interrupt vector -//! table, and enables SHA/MD5 interrupts on the interrupt controller; -//! specific SHA/MD5 interrupt sources must be enabled using -//! SHAMD5IntEnable(). The interrupt handler being registered must clear -//! the source of the interrupt using SHAMD5IntClear(). -//! -//! If the application is using a static interrupt vector table stored in -//! flash, then it is not necessary to register the interrupt handler this way. -//! Instead, IntEnable() should be used to enable SHA/MD5 interrupts on the -//! interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntRegister(uint32_t ui32Base, void(*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Register the interrupt handler. - // - IntRegister(INT_SHA, pfnHandler); - - // - // Enable the interrupt - // - IntEnable(INT_SHA); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! -//! This function unregisters the previously registered interrupt handler and -//! disables the interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5IntUnregister(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Disable the interrupt. - // - IntDisable(INT_SHA); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_SHA); -} - -//***************************************************************************** -// -//! Write the hash length to the SHA/MD5 module. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32Length is the hash length in bytes. -//! -//! This function writes the length of the hash data of the current operation -//! to the SHA/MD5 module. The value must be a multiple of 64 if the close -//! hash is not set in the mode register. -//! -//! \note When this register is written, hash processing is triggered. -//! -//! \return None. -// -//***************************************************************************** -void -SHAMD5DataLengthSet(uint32_t ui32Base, uint32_t ui32Length) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - - // - // Set the LENGTH register and start processing. - // - HWREG(ui32Base + SHAMD5_O_LENGTH) = ui32Length; -} - -//***************************************************************************** -// -//! Writes the mode in the SHA/MD5 module. -//! Sets the request value to SHAMD5_O_MODE register. -//! Each parameter defines one of the bit fields in the SHAMD5_O_MODE register. -//! -//! \param ui32Base is the base address of the SHA/MD5 module. -//! \param ui32CryptoMode sets the hash algorithm to be used. -//! \param algConstFlag sets the requested value to -//! SHAMD5_MODE_ALGO_CONSTANT bit field. -//! \param closeHashFlag sets the requested value to -//! SHAMD5_MODE_CLOSE_HASH bit field. -//! \param HMACKeyFlag sets the requested value to -//! SHAMD5_MODE_HMAC_KEY_PROC bit field. -//! \param HMACOuterHashFlag sets the requested value to -//! SHAMD5_MODE_HMAC_OUTER_HASH bit field. -//! -//! \return None -// -//***************************************************************************** -void -SHAMD5ConfigSet(uint32_t ui32Base, uint32_t ui32CryptoMode, uint8_t algConstFlag, uint8_t closeHashFlag, - uint8_t HMACKeyFlag, uint8_t HMACOuterHashFlag) -{ - uint32_t RegData = 0; - - // - // Check the arguments. - // - ASSERT(ui32Base == SHAMD5_BASE); - ASSERT((ui32CryptoMode == SHAMD5_ALGO_MD5) || - (ui32CryptoMode == SHAMD5_ALGO_SHA1) || - (ui32CryptoMode == SHAMD5_ALGO_SHA224) || - (ui32CryptoMode == SHAMD5_ALGO_SHA256)); - - RegData = (uint32_t)( ui32CryptoMode | ((algConstFlag&0x1)< -//! Polarity Phase Sub-Mode -//! 0 0 0 -//! 0 1 1 -//! 1 0 2 -//! 1 1 3 -//! -//! -//! Required sub mode can be select by setting \e ulSubMode parameter to one -//! of the following -//! - \b SPI_SUB_MODE_0 -//! - \b SPI_SUB_MODE_1 -//! - \b SPI_SUB_MODE_2 -//! - \b SPI_SUB_MODE_3 -//! -//! The parameter \e ulConfig is logical OR of five values: the word length, -//! active level for chip select, software or hardware controled chip select, -//! 3 or 4 pin mode and turbo mode. -//! mode. -//! -//! SPI support 8, 16 and 32 bit word lengths defined by:- -//! - \b SPI_WL_8 -//! - \b SPI_WL_16 -//! - \b SPI_WL_32 -//! -//! Active state of Chip[ Selece can be defined by:- -//! - \b SPI_CS_ACTIVELOW -//! - \b SPI_CS_ACTIVEHIGH -//! -//! SPI chip select can be configured to be controlled either by hardware or -//! software:- -//! - \b SPI_SW_CS -//! - \b SPI_HW_CS -//! -//! The module can work in 3 or 4 pin mode defined by:- -//! - \b SPI_3PIN_MODE -//! - \b SPI_4PIN_MODE -//! -//! Turbo mode can be set on or turned off using:- -//! - \b SPI_TURBO_MODE_ON -//! - \b SPI_TURBO_MODE_OFF -//! -//! \return None. -// -//***************************************************************************** -void -SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk, - unsigned long ulBitRate, unsigned long ulMode, - unsigned long ulSubMode, unsigned long ulConfig) -{ - - unsigned long ulRegData; - unsigned long ulDivider; - - // - // Read MODULCTRL register - // - ulRegData = HWREG(ulBase + MCSPI_O_MODULCTRL); - - // - // Set Master mode with h/w chip select - // - ulRegData &= ~(MCSPI_MODULCTRL_MS | - MCSPI_MODULCTRL_SINGLE); - - // - // Enable software control Chip Select, Init delay - // and 3-pin mode - // - ulRegData |= (((ulConfig >> 24) | ulMode) & 0xFF); - - // - // Write the configuration - // - HWREG(ulBase + MCSPI_O_MODULCTRL) = ulRegData; - - // - // Set IS, DPE0, DPE1 based on master or slave mode - // - if(ulMode == SPI_MODE_MASTER) - { - ulRegData = 0x1 << 16; - } - else - { - ulRegData = 0x6 << 16; - } - - // - // Mask the configurations and set clock divider granularity - // to 1 cycle - // - ulRegData = (ulRegData & ~(MCSPI_CH0CONF_WL_M | - MCSPI_CH0CONF_EPOL | - MCSPI_CH0CONF_POL | - MCSPI_CH0CONF_PHA | - MCSPI_CH0CONF_TURBO ) | - MCSPI_CH0CONF_CLKG); - - // - // Get the divider value - // - ulDivider = ((ulSPIClk/ulBitRate) - 1); - - // - // The least significant four bits of the divider is used fo configure - // CLKD in MCSPI_CHCONF next eight least significant bits are used to - // configure the EXTCLK in MCSPI_CHCTRL - // - ulRegData |= ((ulDivider & 0x0000000F) << 2); - HWREG(ulBase + MCSPI_O_CH0CTRL) = ((ulDivider & 0x00000FF0) << 4); - - // - // Set the protocol, CS polarity, word length - // and turbo mode - // - ulRegData = ((ulRegData | - ulSubMode) | (ulConfig & 0x0008FFFF)); - - // - // Write back the CONF register - // - HWREG(ulBase + MCSPI_O_CH0CONF) = ulRegData; - -} - -//***************************************************************************** -// -//! Receives a word from the specified port. -//! -//! \param ulBase is the base address of the SPI module. -//! \param pulData is pointer to receive data variable. -//! -//! This function gets a SPI word from the receive FIFO for the specified -//! port. -//! -//! \return Returns the number of elements read from the receive FIFO. -// -//***************************************************************************** -long -SPIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData) -{ - unsigned long ulRegVal; - - // - // Read register status register - // - ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT); - - // - // Check is data is available - // - if(ulRegVal & MCSPI_CH0STAT_RXS) - { - *pulData = HWREG(ulBase + MCSPI_O_RX0); - return(1); - } - - return(0); -} - -//***************************************************************************** -// -//! Waits for the word to be received on the specified port. -//! -//! \param ulBase is the base address of the SPI module. -//! \param pulData is pointer to receive data variable. -//! -//! This function gets a SPI word from the receive FIFO for the specified -//! port. If there is no word available, this function waits until a -//! word is received before returning. -//! -//! \return Returns the word read from the specified port, cast as an -//! \e unsigned long. -// -//***************************************************************************** -void -SPIDataGet(unsigned long ulBase, unsigned long *pulData) -{ - // - // Wait for Rx data - // - while(!(HWREG(ulBase + MCSPI_O_CH0STAT) & MCSPI_CH0STAT_RXS)) - { - } - - // - // Read the value - // - *pulData = HWREG(ulBase + MCSPI_O_RX0); -} - -//***************************************************************************** -// -//! Transmits a word on the specified port. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulData is data to be transmitted. -//! -//! This function transmits a SPI word on the transmit FIFO for the specified -//! port. -//! -//! \return Returns the number of elements written to the transmit FIFO. -//! -//***************************************************************************** -long -SPIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData) -{ - unsigned long ulRegVal; - - // - // Read status register - // - ulRegVal = HWREG(ulBase + MCSPI_O_CH0STAT); - - // - // Write value into Tx register/FIFO - // if space is available - // - if(ulRegVal & MCSPI_CH0STAT_TXS) - { - HWREG(ulBase + MCSPI_O_TX0) = ulData; - return(1); - } - - return(0); -} - -//***************************************************************************** -// -//! Waits until the word is transmitted on the specified port. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulData is data to be transmitted. -//! -//! This function transmits a SPI word on the transmit FIFO for the specified -//! port. This function waits until the space is available on transmit FIFO -//! -//! \return None -//! -//***************************************************************************** -void -SPIDataPut(unsigned long ulBase, unsigned long ulData) -{ - // - // Wait for space in FIFO - // - while(!(HWREG(ulBase + MCSPI_O_CH0STAT)&MCSPI_CH0STAT_TXS)) - { - } - - // - // Write the data - // - HWREG(ulBase + MCSPI_O_TX0) = ulData; -} - -//***************************************************************************** -// -//! Enables the transmit and/or receive FIFOs. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulFlags selects the FIFO(s) to be enabled -//! -//! This function enables the transmit and/or receive FIFOs as specified by -//! \e ulFlags. -//! The parameter \e ulFlags shoulde be logical OR of one or more of the -//! following: -//! - \b SPI_TX_FIFO -//! - \b SPI_RX_FIFO -//! -//! \return None. -// -//***************************************************************************** -void -SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags) -{ - // - // Set FIFO enable bits. - // - HWREG(ulBase + MCSPI_O_CH0CONF) |= ulFlags; -} - -//***************************************************************************** -// -//! Disables the transmit and/or receive FIFOs. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulFlags selects the FIFO(s) to be enabled -//! -//! This function disables transmit and/or receive FIFOs. as specified by -//! \e ulFlags. -//! The parameter \e ulFlags shoulde be logical OR of one or more of the -//! following: -//! - \b SPI_TX_FIFO -//! - \b SPI_RX_FIFO -//! -//! \return None. -// -//***************************************************************************** -void -SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags) -{ - // - // Reset FIFO Enable bits. - // - HWREG(ulBase + MCSPI_O_CH0CONF) &= ~(ulFlags); -} - -//***************************************************************************** -// -//! Sets the FIFO level at which DMA requests or interrupts are generated. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulTxLevel is the Almost Empty Level for transmit FIFO. -//! \param ulRxLevel is the Almost Full Level for the receive FIFO. -//! -//! This function Sets the FIFO level at which DMA requests or interrupts -//! are generated. -//! -//! \return None. -// -//***************************************************************************** -void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, - unsigned long ulRxLevel) -{ - unsigned long ulRegVal; - - // - // Read the current configuration - // - ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL); - - // - // Mask and set new FIFO thresholds. - // - ulRegVal = ((ulRegVal & 0xFFFF0000) | (((ulRxLevel-1) << 8) | (ulTxLevel-1))); - - // - // Set the transmit and receive FIFO thresholds. - // - HWREG(ulBase + MCSPI_O_XFERLEVEL) = ulRegVal; - -} - -//***************************************************************************** -// -//! Gets the FIFO level at which DMA requests or interrupts are generated. -//! -//! \param ulBase is the base address of the SPI module -//! \param pulTxLevel is a pointer to storage for the transmit FIFO level -//! \param pulRxLevel is a pointer to storage for the receive FIFO level -//! -//! This function gets the FIFO level at which DMA requests or interrupts -//! are generated. -//! -//! \return None. -// -//***************************************************************************** -void -SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, - unsigned long *pulRxLevel) -{ - unsigned long ulRegVal; - - // - // Read the current configuration - // - ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL); - - *pulTxLevel = (ulRegVal & 0xFF); - - *pulRxLevel = ((ulRegVal >> 8) & 0xFF); - -} - -//***************************************************************************** -// -//! Sets the word count. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulWordCount is number of SPI words to be transmitted. -//! -//! This function sets the word count, which is the number of SPI word to -//! be transferred on channel when using the FIFO buffer. -//! -//! \return None. -// -//***************************************************************************** -void -SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount) -{ - unsigned long ulRegVal; - - // - // Read the current configuration - // - ulRegVal = HWREG(ulBase + MCSPI_O_XFERLEVEL); - - // - // Mask and set the word count - // - HWREG(ulBase + MCSPI_O_XFERLEVEL) = ((ulRegVal & 0x0000FFFF)| - (ulWordCount & 0xFFFF) << 16); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a SPI interrupt. -//! -//! \param ulBase is the base address of the SPI module -//! \param pfnHandler is a pointer to the function to be called when the -//! SPI interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; specific -//! SPI interrupts must be enabled via SPIIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)) -{ - unsigned long ulInt; - - // - // Determine the interrupt number based on the SPI module - // - ulInt = SPIIntNumberGet(ulBase); - - // - // Register the interrupt handler. - // - IntRegister(ulInt, pfnHandler); - - // - // Enable the SPI interrupt. - // - IntEnable(ulInt); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a SPI interrupt. -//! -//! \param ulBase is the base address of the SPI module -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a SPI interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SPIIntUnregister(unsigned long ulBase) -{ - unsigned long ulInt; - - // - // Determine the interrupt number based on the SPI module - // - ulInt = SPIIntNumberGet(ulBase); - - // - // Disable the interrupt. - // - IntDisable(ulInt); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulInt); -} - -//***************************************************************************** -// -//! Enables individual SPI interrupt sources. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated SPI interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! -//! - \b SPI_INT_DMATX -//! - \b SPI_INT_DMARX -//! - \b SPI_INT_EOW -//! - \b SPI_INT_RX_OVRFLOW -//! - \b SPI_INT_RX_FULL -//! - \b SPI_INT_TX_UDRFLOW -//! - \b SPI_INT_TX_EMPTY -//! -//! \return None. -// -//***************************************************************************** -void -SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - unsigned long ulDmaMsk; - - // - // Enable DMA Tx Interrupt - // - if(ulIntFlags & SPI_INT_DMATX) - { - ulDmaMsk = SPIDmaMaskGet(ulBase); - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk; - } - - // - // Enable DMA Rx Interrupt - // - if(ulIntFlags & SPI_INT_DMARX) - { - ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1); - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR) = ulDmaMsk; - } - - // - // Enable the specific Interrupts - // - HWREG(ulBase + MCSPI_O_IRQENABLE) |= (ulIntFlags & 0x0003000F); -} - - -//***************************************************************************** -// -//! Disables individual SPI interrupt sources. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated SPI interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to SPIIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - unsigned long ulDmaMsk; - - // - // Disable DMA Tx Interrupt - // - if(ulIntFlags & SPI_INT_DMATX) - { - ulDmaMsk = SPIDmaMaskGet(ulBase); - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk; - } - - // - // Disable DMA Tx Interrupt - // - if(ulIntFlags & SPI_INT_DMARX) - { - ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1); - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_MASK_SET) = ulDmaMsk; - } - - // - // Disable the specific Interrupts - // - HWREG(ulBase + MCSPI_O_IRQENABLE) &= ~(ulIntFlags & 0x0003000F); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the SPI module -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the specified SPI. -//! The status of interrupts that are allowed to reflect to the processor can -//! be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in SPIIntEnable(). -// -//***************************************************************************** -unsigned long -SPIIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - unsigned long ulIntStat; - unsigned long ulIntFlag; - unsigned long ulDmaMsk; - - // - // Get SPI interrupt status - // - ulIntFlag = HWREG(ulBase + MCSPI_O_IRQSTATUS) & 0x0003000F; - - if(bMasked) - { - ulIntFlag &= HWREG(ulBase + MCSPI_O_IRQENABLE); - } - - // - // Get the interrupt bit - // - ulDmaMsk = SPIDmaMaskGet(ulBase); - - // - // Get the DMA interrupt status - // - if(bMasked) - { - ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED); - } - else - { - ulIntStat = HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_STS_RAW); - } - - // - // Get SPI Tx DMA done status - // - if(ulIntStat & ulDmaMsk) - { - ulIntFlag |= SPI_INT_DMATX; - } - - // - // Get SPI Rx DMA done status - // - if(ulIntStat & (ulDmaMsk >> 1)) - { - ulIntFlag |= SPI_INT_DMARX; - } - - // - // Return status - // - return(ulIntFlag); -} - -//***************************************************************************** -// -//! Clears SPI interrupt sources. -//! -//! \param ulBase is the base address of the SPI module -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified SPI interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to SPIIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - unsigned long ulDmaMsk; - - // - // Disable DMA Tx Interrupt - // - if(ulIntFlags & SPI_INT_DMATX) - { - ulDmaMsk = SPIDmaMaskGet(ulBase); - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk; - } - - // - // Disable DMA Tx Interrupt - // - if(ulIntFlags & SPI_INT_DMARX) - { - ulDmaMsk = (SPIDmaMaskGet(ulBase) >> 1); - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_DMA_DONE_INT_ACK) = ulDmaMsk; - } - - // - // Clear Interrupts - // - HWREG(ulBase + MCSPI_O_IRQSTATUS) = (ulIntFlags & 0x0003000F); -} - -//***************************************************************************** -// -//! Enables the chip select in software controlled mode -//! -//! \param ulBase is the base address of the SPI module. -//! -//! This function enables the Chip select in software controlled mode. The -//! active state of CS will depend on the configuration done via -//! \sa SPIConfigExpClkSet(). -//! -//! \return None. -// -//***************************************************************************** -void SPICSEnable(unsigned long ulBase) -{ - // - // Set Chip Select enable bit. - // - HWREG( ulBase+MCSPI_O_CH0CONF) |= MCSPI_CH0CONF_FORCE; -} - -//***************************************************************************** -// -//! Disables the chip select in software controlled mode -//! -//! \param ulBase is the base address of the SPI module. -//! -//! This function disables the Chip select in software controlled mode. The -//! active state of CS will depend on the configuration done via -//! sa SPIConfigSetExpClk(). -//! -//! \return None. -// -//***************************************************************************** -void SPICSDisable(unsigned long ulBase) -{ - // - // Reset Chip Select enable bit. - // - HWREG( ulBase+MCSPI_O_CH0CONF) &= ~MCSPI_CH0CONF_FORCE; -} - -//***************************************************************************** -// -//! Send/Receive data buffer over SPI channel -//! -//! \param ulBase is the base address of SPI module -//! \param ucDout is the pointer to Tx data buffer or 0. -//! \param ucDin is pointer to Rx data buffer or 0 -//! \param ulCount is the size of data in bytes. -//! \param ulFlags controlls chip select toggling. -//! -//! This function transfers \e ulCount bytes of data over SPI channel. Since -//! the API sends a SPI word at a time \e ulCount should be a multiple of -//! word length set using SPIConfigSetExpClk(). -//! -//! If the \e ucDout parameter is set to 0, the function will send 0xFF over -//! the SPI MOSI line. -//! -//! If the \e ucDin parameter is set to 0, the function will ignore data on SPI -//! MISO line. -//! -//! The parameter \e ulFlags is logical OR of one or more of the following -//! -//! - \b SPI_CS_ENABLE if CS needs to be enabled at start of transfer. -//! - \b SPI_CS_DISABLE if CS need to be disabled at the end of transfer. -//! -//! This function will not return until data has been transmitted -//! -//! \return Returns 0 on success, -1 otherwise. -// -//***************************************************************************** -long SPITransfer(unsigned long ulBase, unsigned char *ucDout, - unsigned char *ucDin, unsigned long ulCount, - unsigned long ulFlags) -{ - unsigned long ulWordLength; - long lRet; - - // - // Get the word length - // - ulWordLength = (HWREG(ulBase + MCSPI_O_CH0CONF) & MCSPI_CH0CONF_WL_M); - - // - // Check for word length. - // - if( !((ulWordLength == SPI_WL_8) || (ulWordLength == SPI_WL_16) || - (ulWordLength == SPI_WL_32)) ) - { - return -1; - } - - if( ulWordLength == SPI_WL_8 ) - { - // - // Do byte transfer - // - lRet = SPITransfer8(ulBase,ucDout,ucDin,ulCount,ulFlags); - } - else if( ulWordLength == SPI_WL_16 ) - { - - // - // Do half-word transfer - // - lRet = SPITransfer16(ulBase,(unsigned short *)ucDout, - (unsigned short *)ucDin,ulCount,ulFlags); - } - else - { - // - // Do word transfer - // - lRet = SPITransfer32(ulBase,(unsigned long *)ucDout, - (unsigned long *)ucDin,ulCount,ulFlags); - } - - // - // return - // - return lRet; - -} -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/spi.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/spi.h deleted file mode 100644 index 6a2aa50c90f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/spi.h +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// spi.h -// -// Defines and Macros for the SPI. -// -//***************************************************************************** - -#ifndef __SPI_H__ -#define __SPI_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// Values that can be passed to SPIConfigSetExpClk() as ulMode parameter -//***************************************************************************** -#define SPI_MODE_MASTER 0x00000000 -#define SPI_MODE_SLAVE 0x00000004 - -//***************************************************************************** -// Values that can be passed to SPIConfigSetExpClk() as ulSubMode parameter -//***************************************************************************** -#define SPI_SUB_MODE_0 0x00000000 -#define SPI_SUB_MODE_1 0x00000001 -#define SPI_SUB_MODE_2 0x00000002 -#define SPI_SUB_MODE_3 0x00000003 - - -//***************************************************************************** -// Values that can be passed to SPIConfigSetExpClk() as ulConfigFlags parameter -//***************************************************************************** -#define SPI_SW_CTRL_CS 0x01000000 -#define SPI_HW_CTRL_CS 0x00000000 -#define SPI_3PIN_MODE 0x02000000 -#define SPI_4PIN_MODE 0x00000000 -#define SPI_TURBO_ON 0x00080000 -#define SPI_TURBO_OFF 0x00000000 -#define SPI_CS_ACTIVEHIGH 0x00000000 -#define SPI_CS_ACTIVELOW 0x00000040 -#define SPI_WL_8 0x00000380 -#define SPI_WL_16 0x00000780 -#define SPI_WL_32 0x00000F80 - -//***************************************************************************** -// Values that can be passed to SPIFIFOEnable() and SPIFIFODisable() -//***************************************************************************** -#define SPI_TX_FIFO 0x08000000 -#define SPI_RX_FIFO 0x10000000 - -//***************************************************************************** -// Values that can be passed to SPIDMAEnable() and SPIDMADisable() -//***************************************************************************** -#define SPI_RX_DMA 0x00008000 -#define SPI_TX_DMA 0x00004000 - -//***************************************************************************** -// Values that can be passed to SPIIntEnable(), SPIIntDiasble(), -// SPIIntClear() or returned from SPIStatus() -//***************************************************************************** -#define SPI_INT_DMATX 0x20000000 -#define SPI_INT_DMARX 0x10000000 -#define SPI_INT_EOW 0x00020000 -#define SPI_INT_WKS 0x00010000 -#define SPI_INT_RX_OVRFLOW 0x00000008 -#define SPI_INT_RX_FULL 0x00000004 -#define SPI_INT_TX_UDRFLOW 0x00000002 -#define SPI_INT_TX_EMPTY 0x00000001 - -//***************************************************************************** -// Values that can be passed to SPITransfer() -//***************************************************************************** -#define SPI_CS_ENABLE 0x00000001 -#define SPI_CS_DISABLE 0x00000002 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void SPIEnable(unsigned long ulBase); -extern void SPIDisable(unsigned long ulBase); -extern void SPIReset(unsigned long ulBase); -extern void SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk, - unsigned long ulBitRate, unsigned long ulMode, - unsigned long ulSubMode, unsigned long ulConfig); -extern long SPIDataGetNonBlocking(unsigned long ulBase, - unsigned long * pulData); -extern void SPIDataGet(unsigned long ulBase, unsigned long *pulData); -extern long SPIDataPutNonBlocking(unsigned long ulBase, - unsigned long ulData); -extern void SPIDataPut(unsigned long ulBase, unsigned long ulData); -extern void SPIFIFOEnable(unsigned long ulBase, unsigned long ulFlags); -extern void SPIFIFODisable(unsigned long ulBase, unsigned long ulFlags); -extern void SPIFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, - unsigned long ulRxLevel); -extern void SPIFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, - unsigned long *pulRxLevel); -extern void SPIWordCountSet(unsigned long ulBase, unsigned long ulWordCount); -extern void SPIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void SPIIntUnregister(unsigned long ulBase); -extern void SPIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void SPIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long SPIIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void SPIIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void SPIDmaEnable(unsigned long ulBase, unsigned long ulFlags); -extern void SPIDmaDisable(unsigned long ulBase, unsigned long ulFlags); -extern void SPICSEnable(unsigned long ulBase); -extern void SPICSDisable(unsigned long ulBase); -extern long SPITransfer(unsigned long ulBase, unsigned char *ucDout, - unsigned char *ucDin, unsigned long ulSize, - unsigned long ulFlags); - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SPI_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/systick.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/systick.c deleted file mode 100644 index 475d3c7a96d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/systick.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// systick.c -// -// Driver for the SysTick timer in NVIC. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup systick_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_ints.h" -#include "inc/hw_nvic.h" -#include "inc/hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "systick.h" - -//***************************************************************************** -// -//! Enables the SysTick counter. -//! -//! This function starts the SysTick counter. If an interrupt handler has been -//! registered, it is called when the SysTick counter rolls over. -//! -//! \note Calling this function causes the SysTick counter to (re)commence -//! counting from its current value. The counter is not automatically reloaded -//! with the period as specified in a previous call to SysTickPeriodSet(). If -//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be -//! written to force the reload. Any write to this register clears the SysTick -//! counter to 0 and causes a reload with the supplied period on the next -//! clock. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickEnable(void) -{ - // - // Enable SysTick. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE; -} - -//***************************************************************************** -// -//! Disables the SysTick counter. -//! -//! This function stops the SysTick counter. If an interrupt handler has been -//! registered, it is not called until SysTick is restarted. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickDisable(void) -{ - // - // Disable SysTick. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the SysTick interrupt. -//! -//! \param pfnHandler is a pointer to the function to be called when the -//! SysTick interrupt occurs. -//! -//! This function registers the handler to be called when a SysTick interrupt -//! occurs. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickIntRegister(void (*pfnHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - IntRegister(FAULT_SYSTICK, pfnHandler); - - // - // Enable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; -} - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the SysTick interrupt. -//! -//! This function unregisters the handler to be called when a SysTick interrupt -//! occurs. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickIntUnregister(void) -{ - // - // Disable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); - - // - // Unregister the interrupt handler. - // - IntUnregister(FAULT_SYSTICK); -} - -//***************************************************************************** -// -//! Enables the SysTick interrupt. -//! -//! This function enables the SysTick interrupt, allowing it to be -//! reflected to the processor. -//! -//! \note The SysTick interrupt handler is not required to clear the SysTick -//! interrupt source because it is cleared automatically by the NVIC when the -//! interrupt handler is called. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickIntEnable(void) -{ - // - // Enable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN; -} - -//***************************************************************************** -// -//! Disables the SysTick interrupt. -//! -//! This function disables the SysTick interrupt, preventing it from being -//! reflected to the processor. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickIntDisable(void) -{ - // - // Disable the SysTick interrupt. - // - HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN); -} - -//***************************************************************************** -// -//! Sets the period of the SysTick counter. -//! -//! \param ulPeriod is the number of clock ticks in each period of the SysTick -//! counter and must be between 1 and 16,777,216, inclusive. -//! -//! This function sets the rate at which the SysTick counter wraps, which -//! equates to the number of processor clocks between interrupts. -//! -//! \note Calling this function does not cause the SysTick counter to reload -//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT -//! register must be written. Any write to this register clears the SysTick -//! counter to 0 and causes a reload with the \e ulPeriod supplied here on -//! the next clock after SysTick is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -SysTickPeriodSet(unsigned long ulPeriod) -{ - // - // Check the arguments. - // - ASSERT((ulPeriod > 0) && (ulPeriod <= 16777216)); - - // - // Set the period of the SysTick counter. - // - HWREG(NVIC_ST_RELOAD) = ulPeriod - 1; -} - -//***************************************************************************** -// -//! Gets the period of the SysTick counter. -//! -//! This function returns the rate at which the SysTick counter wraps, which -//! equates to the number of processor clocks between interrupts. -//! -//! \return Returns the period of the SysTick counter. -// -//***************************************************************************** -unsigned long -SysTickPeriodGet(void) -{ - // - // Return the period of the SysTick counter. - // - return(HWREG(NVIC_ST_RELOAD) + 1); -} - -//***************************************************************************** -// -//! Gets the current value of the SysTick counter. -//! -//! This function returns the current value of the SysTick counter, which is -//! a value between the period - 1 and zero, inclusive. -//! -//! \return Returns the current value of the SysTick counter. -// -//***************************************************************************** -unsigned long -SysTickValueGet(void) -{ - // - // Return the current value of the SysTick counter. - // - return(HWREG(NVIC_ST_CURRENT)); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/systick.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/systick.h deleted file mode 100644 index b09e26e4099..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/systick.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// systick.h -// -// Prototypes for the SysTick driver. -// -//***************************************************************************** - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/timer.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/timer.c deleted file mode 100644 index 6daee1c27fe..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/timer.c +++ /dev/null @@ -1,1105 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// timer.c -// -// Driver for the timer module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup GPT_General_Purpose_Timer_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_timer.h" -#include "inc/hw_types.h" -#include "debug.h" -#include "interrupt.h" -#include "timer.h" - - -//***************************************************************************** -// -//! \internal -//! Checks a timer base address. -//! -//! \param ulBase is the base address of the timer module. -//! -//! This function determines if a timer module base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static tBoolean -TimerBaseValid(unsigned long ulBase) -{ - return((ulBase == TIMERA0_BASE) || (ulBase == TIMERA1_BASE) || - (ulBase == TIMERA2_BASE) || (ulBase == TIMERA3_BASE)); -} -#endif - -//***************************************************************************** -// -//! Enables the timer(s). -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to enable; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function enables operation of the timer module. The timer must be -//! configured before it is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -TimerEnable(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Enable the timer(s) module. - // - HWREG(ulBase + TIMER_O_CTL) |= ulTimer & (TIMER_CTL_TAEN | TIMER_CTL_TBEN); -} - -//***************************************************************************** -// -//! Disables the timer(s). -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to disable; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function disables operation of the timer module. -//! -//! \return None. -// -//***************************************************************************** -void -TimerDisable(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Disable the timer module. - // - HWREG(ulBase + TIMER_O_CTL) &= ~(ulTimer & - (TIMER_CTL_TAEN | TIMER_CTL_TBEN)); -} - -//***************************************************************************** -// -//! Configures the timer(s). -//! -//! \param ulBase is the base address of the timer module. -//! \param ulConfig is the configuration for the timer. -//! -//! This function configures the operating mode of the timer(s). The timer -//! module is disabled before being configured, and is left in the disabled -//! state. The 16/32-bit timer is comprised of two 16-bit timers that can -//! operate independently or be concatenated to form a 32-bit timer. -//! -//! The configuration is specified in \e ulConfig as one of the following -//! values: -//! -//! - \b TIMER_CFG_ONE_SHOT - Full-width one-shot timer -//! - \b TIMER_CFG_ONE_SHOT_UP - Full-width one-shot timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_PERIODIC - Full-width periodic timer -//! - \b TIMER_CFG_PERIODIC_UP - Full-width periodic timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_SPLIT_PAIR - Two half-width timers -//! -//! When configured for a pair of half-width timers, each timer is separately -//! configured. The first timer is configured by setting \e ulConfig to -//! the result of a logical OR operation between one of the following values -//! and \e ulConfig: -//! -//! - \b TIMER_CFG_A_ONE_SHOT - Half-width one-shot timer -//! - \b TIMER_CFG_A_ONE_SHOT_UP - Half-width one-shot timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_A_PERIODIC - Half-width periodic timer -//! - \b TIMER_CFG_A_PERIODIC_UP - Half-width periodic timer that counts up -//! instead of down (not available on all parts) -//! - \b TIMER_CFG_A_CAP_COUNT - Half-width edge count capture -//! - \b TIMER_CFG_A_CAP_TIME - Half-width edge time capture -//! - \b TIMER_CFG_A_PWM - Half-width PWM output -//! -//! Similarly, the second timer is configured by setting \e ulConfig to -//! the result of a logical OR operation between one of the corresponding -//! \b TIMER_CFG_B_* values and \e ulConfig. -//! -//! \return None. -// -//***************************************************************************** -void -TimerConfigure(unsigned long ulBase, unsigned long ulConfig) -{ - - ASSERT( (ulConfig == TIMER_CFG_ONE_SHOT) || - (ulConfig == TIMER_CFG_ONE_SHOT_UP) || - (ulConfig == TIMER_CFG_PERIODIC) || - (ulConfig == TIMER_CFG_PERIODIC_UP) || - (((ulConfig & 0xff000000) == TIMER_CFG_SPLIT_PAIR) && - ((((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_ONE_SHOT_UP) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_PERIODIC_UP) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_COUNT) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_CAP_TIME) || - ((ulConfig & 0x000000ff) == TIMER_CFG_A_PWM)) || - (((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_ONE_SHOT_UP) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PERIODIC_UP) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_COUNT) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_CAP_TIME) || - ((ulConfig & 0x0000ff00) == TIMER_CFG_B_PWM))))); - - - // - // Enable CCP to IO path - // - HWREG(0x440260B0) = 0xFF; - - // - // Disable the timers. - // - HWREG(ulBase + TIMER_O_CTL) &= ~(TIMER_CTL_TAEN | TIMER_CTL_TBEN); - - // - // Set the global timer configuration. - // - HWREG(ulBase + TIMER_O_CFG) = ulConfig >> 24; - - // - // Set the configuration of the A and B timers. Note that the B timer - // configuration is ignored by the hardware in 32-bit modes. - // - HWREG(ulBase + TIMER_O_TAMR) = ulConfig & 255; - HWREG(ulBase + TIMER_O_TBMR) = (ulConfig >> 8) & 255; -} - -//***************************************************************************** -// -//! Controls the output level. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param bInvert specifies the output level. -//! -//! This function sets the PWM output level for the specified timer. If the -//! \e bInvert parameter is \b true, then the timer's output is made active -//! low; otherwise, it is made active high. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the output levels as requested. - // - ulTimer &= TIMER_CTL_TAPWML | TIMER_CTL_TBPWML; - HWREG(ulBase + TIMER_O_CTL) = (bInvert ? - (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : - (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); -} - -//***************************************************************************** -// -//! Controls the event type. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param ulEvent specifies the type of event; must be one of -//! \b TIMER_EVENT_POS_EDGE, \b TIMER_EVENT_NEG_EDGE, or -//! \b TIMER_EVENT_BOTH_EDGES. -//! -//! This function sets the signal edge(s) that triggers the timer when in -//! capture mode. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the event type. - // - ulEvent &= ulTimer & (TIMER_CTL_TAEVENT_M | TIMER_CTL_TBEVENT_M); - HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & - ~(TIMER_CTL_TAEVENT_M | - TIMER_CTL_TBEVENT_M)) | ulEvent); -} - -//***************************************************************************** -// -//! Controls the stall handling. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to be adjusted; must be one of -//! \b TIMER_A, \b TIMER_B, or \b TIMER_BOTH. -//! \param bStall specifies the response to a stall signal. -//! -//! This function controls the stall response for the specified timer. If the -//! \e bStall parameter is \b true, then the timer stops counting if the -//! processor enters debug mode; otherwise the timer keeps running while in -//! debug mode. -//! -//! \return None. -// -//***************************************************************************** -void -TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the stall mode. - // - ulTimer &= TIMER_CTL_TASTALL | TIMER_CTL_TBSTALL; - HWREG(ulBase + TIMER_O_CTL) = (bStall ? - (HWREG(ulBase + TIMER_O_CTL) | ulTimer) : - (HWREG(ulBase + TIMER_O_CTL) & ~(ulTimer))); -} - -//***************************************************************************** -// -//! Set the timer prescale value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param ulValue is the timer prescale value which must be between 0 and 255 -//! (inclusive) for 16/32-bit timers. -//! -//! This function sets the value of the input clock prescaler. The prescaler -//! is only operational when in half-width mode and is used to extend the range -//! of the half-width timer modes. -//! -//! \return None. -// -//***************************************************************************** -void -TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - ASSERT(ulValue < 256); - - // - // Set the timer A prescaler if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAPR) = ulValue; - } - - // - // Set the timer B prescaler if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBPR) = ulValue; - } -} - - -//***************************************************************************** -// -//! Get the timer prescale value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. -//! -//! This function gets the value of the input clock prescaler. The prescaler -//! is only operational when in half-width mode and is used to extend the range -//! of the half-width timer modes. -//! -//! \return The value of the timer prescaler. -// -//***************************************************************************** - -unsigned long -TimerPrescaleGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Return the appropriate prescale value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPR) : - HWREG(ulBase + TIMER_O_TBPR)); -} - -//***************************************************************************** -// -//! Set the timer prescale match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param ulValue is the timer prescale match value which must be between 0 -//! and 255 (inclusive) for 16/32-bit timers. -//! -//! This function sets the value of the input clock prescaler match value. -//! When in a half-width mode that uses the counter match and the prescaler, -//! the prescale match effectively extends the range of the match. -//! -//! \note The availability of the prescaler match varies with the -//! part and timer mode in use. Please consult the datasheet for the part you -//! are using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - ASSERT(ulValue < 256); - - // - // Set the timer A prescale match if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAPMR) = ulValue; - } - - // - // Set the timer B prescale match if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBPMR) = ulValue; - } -} - -//***************************************************************************** -// -//! Get the timer prescale match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. -//! -//! This function gets the value of the input clock prescaler match value. -//! When in a half-width mode that uses the counter match and prescaler, the -//! prescale match effectively extends the range of the match. -//! -//! \note The availability of the prescaler match varies with the -//! part and timer mode in use. Please consult the datasheet for the part you -//! are using to determine whether this support is available. -//! -//! \return The value of the timer prescale match. -// -//***************************************************************************** -unsigned long -TimerPrescaleMatchGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Return the appropriate prescale match value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAPMR) : - HWREG(ulBase + TIMER_O_TBPMR)); -} - -//***************************************************************************** -// -//! Sets the timer load value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the -//! timer is configured for full-width operation. -//! \param ulValue is the load value. -//! -//! This function sets the timer load value; if the timer is running then the -//! value is immediately loaded into the timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the timer A load value if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAILR) = ulValue; - } - - // - // Set the timer B load value if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBILR) = ulValue; - } -} - -//***************************************************************************** -// -//! Gets the timer load value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for full-width operation. -//! -//! This function gets the currently programmed interval load value for the -//! specified timer. -//! -//! \note This function can be used for both full- and half-width modes of -//! 16/32-bit timers. -//! -//! \return Returns the load value for the timer. -// -//***************************************************************************** -unsigned long -TimerLoadGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Return the appropriate load value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAILR) : - HWREG(ulBase + TIMER_O_TBILR)); -} - -//***************************************************************************** -// -//! Gets the current timer value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. -//! -//! This function reads the current value of the specified timer. -//! -//! \return Returns the current value of the timer. -// -//***************************************************************************** -unsigned long -TimerValueGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Return the appropriate timer value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAR) : - HWREG(ulBase + TIMER_O_TBR)); -} - -//***************************************************************************** -// -//! Sets the current timer value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. -//! \param ulValue is the new value of the timer to be set. -//! -//! This function sets the current value of the specified timer. -//! -//! \return None. -// -//***************************************************************************** -void -TimerValueSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Set the appropriate timer value. - // - if( (ulTimer == TIMER_A) ) - { - HWREG(ulBase + TIMER_O_TAV) = ulValue; - } - else - { - HWREG(ulBase + TIMER_O_TBV) = ulValue; - } -} - - -//***************************************************************************** -// -//! Sets the timer match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s) to adjust; must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. Only \b TIMER_A should be used when the -//! timer is configured for 32-bit operation. -//! \param ulValue is the match value. -//! -//! This function sets the match value for a timer. This is used in capture -//! count mode to determine when to interrupt the processor and in PWM mode to -//! determine the duty cycle of the output signal. -//! -//! \return None. -// -//***************************************************************************** -void -TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Set the timer A match value if requested. - // - if(ulTimer & TIMER_A) - { - HWREG(ulBase + TIMER_O_TAMATCHR) = ulValue; - } - - // - // Set the timer B match value if requested. - // - if(ulTimer & TIMER_B) - { - HWREG(ulBase + TIMER_O_TBMATCHR) = ulValue; - } -} - -//***************************************************************************** -// -//! Gets the timer match value. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer; must be one of \b TIMER_A or -//! \b TIMER_B. Only \b TIMER_A should be used when the timer is configured -//! for 32-bit operation. -//! -//! This function gets the match value for the specified timer. -//! -//! \return Returns the match value for the timer. -// -//******************************************************************************** -unsigned long -TimerMatchGet(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B)); - - // - // Return the appropriate match value. - // - return((ulTimer == TIMER_A) ? HWREG(ulBase + TIMER_O_TAMATCHR) : - HWREG(ulBase + TIMER_O_TBMATCHR)); -} - - -//***************************************************************************** -// -//! Registers an interrupt handler for the timer interrupt. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! \param pfnHandler is a pointer to the function to be called when the timer -//! interrupt occurs. -//! -//! This function sets the handler to be called when a timer interrupt occurs. -//! In addition, this function enables the global interrupt in the interrupt -//! controller; specific timer interrupts must be enabled via TimerIntEnable(). -//! It is the interrupt handler's responsibility to clear the interrupt source -//! via TimerIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - ulBase = ((ulBase == TIMERA0_BASE) ? INT_TIMERA0A : - ((ulBase == TIMERA1_BASE) ? INT_TIMERA1A : - ((ulBase == TIMERA2_BASE) ? INT_TIMERA2A : INT_TIMERA3A))); - - // - // Register an interrupt handler for timer A if requested. - // - if(ulTimer & TIMER_A) - { - // - // Register the interrupt handler. - // - IntRegister(ulBase, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(ulBase); - } - - // - // Register an interrupt handler for timer B if requested. - // - if(ulTimer & TIMER_B) - { - // - // Register the interrupt handler. - // - IntRegister(ulBase + 1, pfnHandler); - - // - // Enable the interrupt. - // - IntEnable(ulBase + 1); - } -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the timer interrupt. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulTimer specifies the timer(s); must be one of \b TIMER_A, -//! \b TIMER_B, or \b TIMER_BOTH. -//! -//! This function clears the handler to be called when a timer interrupt -//! occurs. This function also masks off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - ASSERT((ulTimer == TIMER_A) || (ulTimer == TIMER_B) || - (ulTimer == TIMER_BOTH)); - - // - // Get the interrupt number for this timer module. - // - - ulBase = ((ulBase == TIMERA0_BASE) ? INT_TIMERA0A : - ((ulBase == TIMERA1_BASE) ? INT_TIMERA1A : - ((ulBase == TIMERA2_BASE) ? INT_TIMERA2A : INT_TIMERA3A))); - - - - // - // Unregister the interrupt handler for timer A if requested. - // - if(ulTimer & TIMER_A) - { - // - // Disable the interrupt. - // - IntDisable(ulBase); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulBase); - } - - // - // Unregister the interrupt handler for timer B if requested. - // - if(ulTimer & TIMER_B) - { - // - // Disable the interrupt. - // - IntDisable(ulBase + 1); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulBase + 1); - } -} - -//***************************************************************************** -// -//! Enables individual timer interrupt sources. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! Enables the indicated timer interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! The \e ulIntFlags parameter must be the logical OR of any combination of -//! the following: -//! -//! - \b TIMER_CAPB_EVENT - Capture B event interrupt -//! - \b TIMER_CAPB_MATCH - Capture B match interrupt -//! - \b TIMER_TIMB_TIMEOUT - Timer B timeout interrupt -//! - \b TIMER_CAPA_EVENT - Capture A event interrupt -//! - \b TIMER_CAPA_MATCH - Capture A match interrupt -//! - \b TIMER_TIMA_TIMEOUT - Timer A timeout interrupt -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - - // - // Enable the specified interrupts. - // - HWREG(ulBase + TIMER_O_IMR) |= ulIntFlags; -} - -//***************************************************************************** -// -//! Disables individual timer interrupt sources. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! Disables the indicated timer interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to TimerIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - - // - // Disable the specified interrupts. - // - HWREG(ulBase + TIMER_O_IMR) &= ~(ulIntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the timer module. -//! \param bMasked is false if the raw interrupt status is required and true if -//! the masked interrupt status is required. -//! -//! This function returns the interrupt status for the timer module. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! values described in TimerIntEnable(). -// -//***************************************************************************** -unsigned long -TimerIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - return(bMasked ? HWREG(ulBase + TIMER_O_MIS) : - HWREG(ulBase + TIMER_O_RIS)); -} - -//***************************************************************************** -// -//! Clears timer interrupt sources. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified timer interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being triggered again immediately upon exit. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to TimerIntEnable(). -//! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - - // - // Clear the requested interrupt sources. - // - HWREG(ulBase + TIMER_O_ICR) = ulIntFlags; -} - -//***************************************************************************** -// -//! Enables the events that can trigger a DMA request. -//! -//! \param ulBase is the base address of the timer module. -//! \param ulDMAEvent is a bit mask of the events that can trigger DMA. -//! -//! This function enables the timer events that can trigger the start of a DMA -//! sequence. The DMA trigger events are specified in the \e ui32DMAEvent -//! parameter by passing in the logical OR of the following values: -//! -//! - \b TIMER_DMA_MODEMATCH_B - The mode match DMA trigger for timer B is -//! enabled. -//! - \b TIMER_DMA_CAPEVENT_B - The capture event DMA trigger for timer B is -//! enabled. -//! - \b TIMER_DMA_CAPMATCH_B - The capture match DMA trigger for timer B is -//! enabled. -//! - \b TIMER_DMA_TIMEOUT_B - The timeout DMA trigger for timer B is enabled. -//! - \b TIMER_DMA_MODEMATCH_A - The mode match DMA trigger for timer A is -//! enabled. -//! - \b TIMER_DMA_CAPEVENT_A - The capture event DMA trigger for timer A is -//! enabled. -//! - \b TIMER_DMA_CAPMATCH_A - The capture match DMA trigger for timer A is -//! enabled. -//! - \b TIMER_DMA_TIMEOUT_A - The timeout DMA trigger for timer A is enabled. -//! -//! \return None. -// -//***************************************************************************** -void -TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - - // - // Set the DMA triggers. - // - HWREG(ulBase + TIMER_O_DMAEV) = ulDMAEvent; -} - -//***************************************************************************** -// -//! Returns the events that can trigger a DMA request. -//! -//! \param ulBase is the base address of the timer module. -//! -//! This function returns the timer events that can trigger the start of a DMA -//! sequence. The DMA trigger events are the logical OR of the following -//! values: -//! -//! - \b TIMER_DMA_MODEMATCH_B - Enables the mode match DMA trigger for timer -//! B. -//! - \b TIMER_DMA_CAPEVENT_B - Enables the capture event DMA trigger for -//! timer B. -//! - \b TIMER_DMA_CAPMATCH_B - Enables the capture match DMA trigger for -//! timer B. -//! - \b TIMER_DMA_TIMEOUT_B - Enables the timeout DMA trigger for timer B. -//! - \b TIMER_DMA_MODEMATCH_A - Enables the mode match DMA trigger for timer -//! A. -//! - \b TIMER_DMA_CAPEVENT_A - Enables the capture event DMA trigger for -//! timer A. -//! - \b TIMER_DMA_CAPMATCH_A - Enables the capture match DMA trigger for -//! timer A. -//! - \b TIMER_DMA_TIMEOUT_A - Enables the timeout DMA trigger for timer A. -//! -//! \return The timer events that trigger the uDMA. -// -//***************************************************************************** -unsigned long -TimerDMAEventGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(TimerBaseValid(ulBase)); - - // - // Return the current DMA triggers. - // - return(HWREG(ulBase + TIMER_O_DMAEV)); -} -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/timer.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/timer.h deleted file mode 100644 index cd4275a164a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/timer.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// timer.h -// -// Prototypes for the timer module -// -//***************************************************************************** - -#ifndef __TIMER_H__ -#define __TIMER_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to TimerConfigure as the ulConfig parameter. -// -//***************************************************************************** - -#define TIMER_CFG_ONE_SHOT 0x00000021 // Full-width one-shot timer -#define TIMER_CFG_ONE_SHOT_UP 0x00000031 // Full-width one-shot up-count - // timer -#define TIMER_CFG_PERIODIC 0x00000022 // Full-width periodic timer -#define TIMER_CFG_PERIODIC_UP 0x00000032 // Full-width periodic up-count - // timer -#define TIMER_CFG_SPLIT_PAIR 0x04000000 // Two half-width timers - -#define TIMER_CFG_A_ONE_SHOT 0x00000021 // Timer A one-shot timer -#define TIMER_CFG_A_ONE_SHOT_UP 0x00000031 // Timer A one-shot up-count timer -#define TIMER_CFG_A_PERIODIC 0x00000022 // Timer A periodic timer -#define TIMER_CFG_A_PERIODIC_UP 0x00000032 // Timer A periodic up-count timer -#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter -#define TIMER_CFG_A_CAP_COUNT_UP 0x00000013 // Timer A event up-counter -#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer -#define TIMER_CFG_A_CAP_TIME_UP 0x00000017 // Timer A event up-count timer -#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output -#define TIMER_CFG_B_ONE_SHOT 0x00002100 // Timer B one-shot timer -#define TIMER_CFG_B_ONE_SHOT_UP 0x00003100 // Timer B one-shot up-count timer -#define TIMER_CFG_B_PERIODIC 0x00002200 // Timer B periodic timer -#define TIMER_CFG_B_PERIODIC_UP 0x00003200 // Timer B periodic up-count timer -#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter -#define TIMER_CFG_B_CAP_COUNT_UP 0x00001300 // Timer B event up-counter -#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer -#define TIMER_CFG_B_CAP_TIME_UP 0x00001700 // Timer B event up-count timer -#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output - -//***************************************************************************** -// -// Values that can be passed to TimerIntEnable, TimerIntDisable, and -// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. -// -//***************************************************************************** - -#define TIMER_TIMB_DMA 0x00002000 // TimerB DMA Done interrupt -#define TIMER_TIMB_MATCH 0x00000800 // TimerB match interrupt -#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt -#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt -#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt -#define TIMER_TIMA_DMA 0x00000020 // TimerA DMA Done interrupt -#define TIMER_TIMA_MATCH 0x00000010 // TimerA match interrupt -#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt -#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt -#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt - -//***************************************************************************** -// -// Values that can be passed to TimerControlEvent as the ulEvent parameter. -// -//***************************************************************************** -#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges -#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges -#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges - -//***************************************************************************** -// -// Values that can be passed to most of the timer APIs as the ulTimer -// parameter. -// -//***************************************************************************** -#define TIMER_A 0x000000ff // Timer A -#define TIMER_B 0x0000ff00 // Timer B -#define TIMER_BOTH 0x0000ffff // Timer Both - - -//***************************************************************************** -// -// Values that can be passed to TimerSynchronize as the ulTimers parameter. -// -//***************************************************************************** -#define TIMER_0A_SYNC 0x00000001 // Synchronize Timer 0A -#define TIMER_0B_SYNC 0x00000002 // Synchronize Timer 0B -#define TIMER_1A_SYNC 0x00000004 // Synchronize Timer 1A -#define TIMER_1B_SYNC 0x00000008 // Synchronize Timer 1B -#define TIMER_2A_SYNC 0x00000010 // Synchronize Timer 2A -#define TIMER_2B_SYNC 0x00000020 // Synchronize Timer 2B -#define TIMER_3A_SYNC 0x00000040 // Synchronize Timer 3A -#define TIMER_3B_SYNC 0x00000080 // Synchronize Timer 3B - -//***************************************************************************** -// -// Values that can be passed to TimerDMAEventSet() or returned from -// TimerDMAEventGet(). -// -//***************************************************************************** -#define TIMER_DMA_MODEMATCH_B 0x00000800 -#define TIMER_DMA_CAPEVENT_B 0x00000400 -#define TIMER_DMA_CAPMATCH_B 0x00000200 -#define TIMER_DMA_TIMEOUT_B 0x00000100 -#define TIMER_DMA_MODEMATCH_A 0x00000010 -#define TIMER_DMA_CAPEVENT_A 0x00000004 -#define TIMER_DMA_CAPMATCH_A 0x00000002 -#define TIMER_DMA_TIMEOUT_A 0x00000001 - - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); -extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); -extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, - tBoolean bInvert); -extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulEvent); -extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, - tBoolean bStall); -extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); - -extern unsigned long TimerValueGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerValueSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); - -extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, - unsigned long ulValue); -extern unsigned long TimerMatchGet(unsigned long ulBase, - unsigned long ulTimer); -extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, - void (*pfnHandler)(void)); -extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); -extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void TimerDMAEventSet(unsigned long ulBase, unsigned long ulDMAEvent); -extern unsigned long TimerDMAEventGet(unsigned long ulBase); - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __TIMER_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/uart.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/uart.c deleted file mode 100644 index b7c215f7fe8..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/uart.c +++ /dev/null @@ -1,1501 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// uart.c -// -// Driver for the UART. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup UART_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_uart.h" -#include "debug.h" -#include "interrupt.h" -#include "uart.h" - - -//***************************************************************************** -// -// A mapping of UART base address to interupt number. -// -//***************************************************************************** -static const unsigned long g_ppulUARTIntMap[][2] = -{ - { UARTA0_BASE, INT_UARTA0 }, - { UARTA1_BASE, INT_UARTA1 }, -}; - -//***************************************************************************** -// -//! \internal -//! Checks a UART base address. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function determines if a UART port base address is valid. -//! -//! \return Returns \b true if the base address is valid and \b false -//! otherwise. -// -//***************************************************************************** -#ifdef DEBUG -static tBoolean -UARTBaseValid(unsigned long ulBase) -{ - return((ulBase == UARTA0_BASE) || (ulBase == UARTA1_BASE)); -} -#endif - -//***************************************************************************** -// -//! \internal -//! Gets the UART interrupt number. -//! -//! \param ulBase is the base address of the UART port. -//! -//! Given a UART base address, returns the corresponding interrupt number. -//! -//! \return Returns a UART interrupt number, or -1 if \e ulBase is invalid. -// -//***************************************************************************** -static long -UARTIntNumberGet(unsigned long ulBase) -{ - unsigned long ulIdx; - - // - // Loop through the table that maps UART base addresses to interrupt - // numbers. - // - for(ulIdx = 0; ulIdx < (sizeof(g_ppulUARTIntMap) / - sizeof(g_ppulUARTIntMap[0])); ulIdx++) - { - // - // See if this base address matches. - // - if(g_ppulUARTIntMap[ulIdx][0] == ulBase) - { - // - // Return the corresponding interrupt number. - // - return(g_ppulUARTIntMap[ulIdx][1]); - } - } - - // - // The base address could not be found, so return an error. - // - return(-1); -} - -//***************************************************************************** -// -//! Sets the type of parity. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulParity specifies the type of parity to use. -//! -//! This function sets the type of parity to use for transmitting and expect -//! when receiving. The \e ulParity parameter must be one of -//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, -//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. The last two allow -//! direct control of the parity bit; it is always either one or zero based on -//! the mode. -//! -//! \return None. -// -//***************************************************************************** -void -UARTParityModeSet(unsigned long ulBase, unsigned long ulParity) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - ASSERT((ulParity == UART_CONFIG_PAR_NONE) || - (ulParity == UART_CONFIG_PAR_EVEN) || - (ulParity == UART_CONFIG_PAR_ODD) || - (ulParity == UART_CONFIG_PAR_ONE) || - (ulParity == UART_CONFIG_PAR_ZERO)); - - // - // Set the parity mode. - // - HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) & - ~(UART_LCRH_SPS | UART_LCRH_EPS | - UART_LCRH_PEN)) | ulParity); -} - -//***************************************************************************** -// -//! Gets the type of parity currently being used. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function gets the type of parity used for transmitting data and -//! expected when receiving data. -//! -//! \return Returns the current parity settings, specified as one of -//! \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, \b UART_CONFIG_PAR_ODD, -//! \b UART_CONFIG_PAR_ONE, or \b UART_CONFIG_PAR_ZERO. -// -//***************************************************************************** -unsigned long -UARTParityModeGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Return the current parity setting. - // - return(HWREG(ulBase + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_EPS | UART_LCRH_PEN)); -} - -//***************************************************************************** -// -//! Sets the FIFO level at which interrupts are generated. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulTxLevel is the transmit FIFO interrupt level, specified as one of -//! \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, \b UART_FIFO_TX4_8, -//! \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. -//! \param ulRxLevel is the receive FIFO interrupt level, specified as one of -//! \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, \b UART_FIFO_RX4_8, -//! \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. -//! -//! This function sets the FIFO level at which transmit and receive interrupts -//! are generated. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, - unsigned long ulRxLevel) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - ASSERT((ulTxLevel == UART_FIFO_TX1_8) || - (ulTxLevel == UART_FIFO_TX2_8) || - (ulTxLevel == UART_FIFO_TX4_8) || - (ulTxLevel == UART_FIFO_TX6_8) || - (ulTxLevel == UART_FIFO_TX7_8)); - ASSERT((ulRxLevel == UART_FIFO_RX1_8) || - (ulRxLevel == UART_FIFO_RX2_8) || - (ulRxLevel == UART_FIFO_RX4_8) || - (ulRxLevel == UART_FIFO_RX6_8) || - (ulRxLevel == UART_FIFO_RX7_8)); - - // - // Set the FIFO interrupt levels. - // - HWREG(ulBase + UART_O_IFLS) = ulTxLevel | ulRxLevel; -} - -//***************************************************************************** -// -//! Gets the FIFO level at which interrupts are generated. -//! -//! \param ulBase is the base address of the UART port. -//! \param pulTxLevel is a pointer to storage for the transmit FIFO level, -//! returned as one of \b UART_FIFO_TX1_8, \b UART_FIFO_TX2_8, -//! \b UART_FIFO_TX4_8, \b UART_FIFO_TX6_8, or \b UART_FIFO_TX7_8. -//! \param pulRxLevel is a pointer to storage for the receive FIFO level, -//! returned as one of \b UART_FIFO_RX1_8, \b UART_FIFO_RX2_8, -//! \b UART_FIFO_RX4_8, \b UART_FIFO_RX6_8, or \b UART_FIFO_RX7_8. -//! -//! This function gets the FIFO level at which transmit and receive interrupts -//! are generated. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, - unsigned long *pulRxLevel) -{ - unsigned long ulTemp; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Read the FIFO level register. - // - ulTemp = HWREG(ulBase + UART_O_IFLS); - - // - // Extract the transmit and receive FIFO levels. - // - *pulTxLevel = ulTemp & UART_IFLS_TX_M; - *pulRxLevel = ulTemp & UART_IFLS_RX_M; -} - -//***************************************************************************** -// -//! Sets the configuration of a UART. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulUARTClk is the rate of the clock supplied to the UART module. -//! \param ulBaud is the desired baud rate. -//! \param ulConfig is the data format for the port (number of data bits, -//! number of stop bits, and parity). -//! -//! This function configures the UART for operation in the specified data -//! format. The baud rate is provided in the \e ulBaud parameter and the data -//! format in the \e ulConfig parameter. -//! -//! The \e ulConfig parameter is the logical OR of three values: the number of -//! data bits, the number of stop bits, and the parity. \b UART_CONFIG_WLEN_8, -//! \b UART_CONFIG_WLEN_7, \b UART_CONFIG_WLEN_6, and \b UART_CONFIG_WLEN_5 -//! select from eight to five data bits per byte (respectively). -//! \b UART_CONFIG_STOP_ONE and \b UART_CONFIG_STOP_TWO select one or two stop -//! bits (respectively). \b UART_CONFIG_PAR_NONE, \b UART_CONFIG_PAR_EVEN, -//! \b UART_CONFIG_PAR_ODD, \b UART_CONFIG_PAR_ONE, and \b UART_CONFIG_PAR_ZERO -//! select the parity mode (no parity bit, even parity bit, odd parity bit, -//! parity bit always one, and parity bit always zero, respectively). -//! -//! The peripheral clock frequency is returned by PRCMPeripheralClockGet(). -//! -//! -//! \return None. -// -//***************************************************************************** -void -UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, - unsigned long ulBaud, unsigned long ulConfig) -{ - unsigned long ulDiv; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - ASSERT(ulBaud != 0); - - // - // Stop the UART. - // - UARTDisable(ulBase); - - // - // Is the required baud rate greater than the maximum rate supported - // without the use of high speed mode? - // - if((ulBaud * 16) > ulUARTClk) - { - // - // Enable high speed mode. - // - HWREG(ulBase + UART_O_CTL) |= UART_CTL_HSE; - - // - // Half the supplied baud rate to compensate for enabling high speed - // mode. This allows the following code to be common to both cases. - // - ulBaud /= 2; - } - else - { - // - // Disable high speed mode. - // - HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_HSE); - } - - // - // Compute the fractional baud rate divider. - // - ulDiv = (((ulUARTClk * 8) / ulBaud) + 1) / 2; - - // - // Set the baud rate. - // - HWREG(ulBase + UART_O_IBRD) = ulDiv / 64; - HWREG(ulBase + UART_O_FBRD) = ulDiv % 64; - - // - // Set parity, data length, and number of stop bits. - // - HWREG(ulBase + UART_O_LCRH) = ulConfig; - - // - // Clear the flags register. - // - HWREG(ulBase + UART_O_FR) = 0; - - // - // Start the UART. - // - UARTEnable(ulBase); -} - -//***************************************************************************** -// -//! Gets the current configuration of a UART. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulUARTClk is the rate of the clock supplied to the UART module. -//! \param pulBaud is a pointer to storage for the baud rate. -//! \param pulConfig is a pointer to storage for the data format. -//! -//! The baud rate and data format for the UART is determined, given an -//! explicitly provided peripheral clock (hence the ExpClk suffix). The -//! returned baud rate is the actual baud rate; it may not be the exact baud -//! rate requested or an ``official'' baud rate. The data format returned in -//! \e pulConfig is enumerated the same as the \e ulConfig parameter of -//! UARTConfigSetExpClk(). -//! -//! The peripheral clock frequency is returned by PRCMPeripheralClockGet(). -//! -//! -//! \return None. -// -//***************************************************************************** -void -UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, - unsigned long *pulBaud, unsigned long *pulConfig) -{ - unsigned long ulInt, ulFrac; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Compute the baud rate. - // - ulInt = HWREG(ulBase + UART_O_IBRD); - ulFrac = HWREG(ulBase + UART_O_FBRD); - *pulBaud = (ulUARTClk * 4) / ((64 * ulInt) + ulFrac); - - // - // See if high speed mode enabled. - // - if(HWREG(ulBase + UART_O_CTL) & UART_CTL_HSE) - { - // - // High speed mode is enabled so the actual baud rate is actually - // double what was just calculated. - // - *pulBaud *= 2; - } - - // - // Get the parity, data length, and number of stop bits. - // - *pulConfig = (HWREG(ulBase + UART_O_LCRH) & - (UART_LCRH_SPS | UART_LCRH_WLEN_M | UART_LCRH_STP2 | - UART_LCRH_EPS | UART_LCRH_PEN)); -} - -//***************************************************************************** -// -//! Enables transmitting and receiving. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function sets the UARTEN, TXE, and RXE bits, and enables the transmit -//! and receive FIFOs. -//! -//! \return None. -// -//***************************************************************************** -void -UARTEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Enable the FIFO. - // - HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; - - // - // Enable RX, TX, and the UART. - // - HWREG(ulBase + UART_O_CTL) |= (UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} - -//***************************************************************************** -// -//! Disables transmitting and receiving. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function clears the UARTEN, TXE, and RXE bits, waits for the end of -//! transmission of the current character, and flushes the transmit FIFO. -//! -//! \return None. -// -//***************************************************************************** -void -UARTDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Wait for end of TX. - // - while(HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) - { - } - - // - // Disable the FIFO. - // - HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); - - // - // Disable the UART. - // - HWREG(ulBase + UART_O_CTL) &= ~(UART_CTL_UARTEN | UART_CTL_TXE | - UART_CTL_RXE); -} - -//***************************************************************************** -// -//! Enables the transmit and receive FIFOs. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This functions enables the transmit and receive FIFOs in the UART. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFOEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Enable the FIFO. - // - HWREG(ulBase + UART_O_LCRH) |= UART_LCRH_FEN; -} - -//***************************************************************************** -// -//! Disables the transmit and receive FIFOs. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This functions disables the transmit and receive FIFOs in the UART. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFIFODisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Disable the FIFO. - // - HWREG(ulBase + UART_O_LCRH) &= ~(UART_LCRH_FEN); -} - -//***************************************************************************** -// -//! Sets the states of the RTS modem control signals. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulControl is a bit-mapped flag indicating which modem control bits -//! should be set. -//! -//! This function sets the states of the RTS modem handshake outputs -//! from the UART. -//! -//! The \e ulControl parameter is the logical OR of any of the following: -//! -//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal -//! -//! \note The availability of hardware modem handshake signals varies with the -//! part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTModemControlSet(unsigned long ulBase, unsigned long ulControl) -{ - unsigned long ulTemp; - - // - // Check the arguments. - // - - ASSERT(ulBase == UARTA1_BASE); - ASSERT((ulControl & ~(UART_OUTPUT_RTS)) == 0); - - // - // Set the appropriate modem control output bits. - // - ulTemp = HWREG(ulBase + UART_O_CTL); - ulTemp |= (ulControl & (UART_OUTPUT_RTS)); - HWREG(ulBase + UART_O_CTL) = ulTemp; -} - -//***************************************************************************** -// -//! Clears the states of the RTS modem control signals. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulControl is a bit-mapped flag indicating which modem control bits -//! should be set. -//! -//! This function clears the states of the RTS modem handshake outputs -//! from the UART. -//! -//! The \e ulControl parameter is the logical OR of any of the following: -//! -//! - \b UART_OUTPUT_RTS - The Modem Control RTS signal -//! -//! \note The availability of hardware modem handshake signals varies with the -//! part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTModemControlClear(unsigned long ulBase, unsigned long ulControl) -{ - unsigned long ulTemp; - - // - // Check the arguments. - // - ASSERT(ulBase == UARTA1_BASE); - ASSERT((ulControl & ~(UART_OUTPUT_RTS)) == 0); - - // - // Set the appropriate modem control output bits. - // - ulTemp = HWREG(ulBase + UART_O_CTL); - ulTemp &= ~(ulControl & (UART_OUTPUT_RTS)); - HWREG(ulBase + UART_O_CTL) = ulTemp; -} - -//***************************************************************************** -// -//! Gets the states of the RTS modem control signals. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns the current states of each of the UART modem -//! control signal, RTS. -//! -//! \note The availability of hardware modem handshake signals varies with the -//! part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return Returns the states of the handshake output signal. -// -//***************************************************************************** -unsigned long -UARTModemControlGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(ulBase == UARTA1_BASE); - - return(HWREG(ulBase + UART_O_CTL) & (UART_OUTPUT_RTS)); -} - -//***************************************************************************** -// -//! Gets the states of the CTS modem status signal. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns the current states of the UART modem status signal, -//! CTS. -//! -//! \note The availability of hardware modem handshake signals varies with the -//! part and UART in use. Please consult the datasheet for the part -//! you are using to determine whether this support is available. -//! -//! \return Returns the states of the handshake output signal -// -//***************************************************************************** -unsigned long -UARTModemStatusGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - - ASSERT(ulBase == UARTA1_BASE); - - return(HWREG(ulBase + UART_O_FR) & (UART_INPUT_CTS)); -} - -//***************************************************************************** -// -//! Sets the UART hardware flow control mode to be used. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulMode indicates the flow control modes to be used. This parameter -//! is a logical OR combination of values \b UART_FLOWCONTROL_TX and -//! \b UART_FLOWCONTROL_RX to enable hardware transmit (CTS) and receive (RTS) -//! flow control or \b UART_FLOWCONTROL_NONE to disable hardware flow control. -//! -//! This function sets the required hardware flow control modes. If \e ulMode -//! contains flag \b UART_FLOWCONTROL_TX, data is only transmitted if the -//! incoming CTS signal is asserted. If \e ulMode contains flag -//! \b UART_FLOWCONTROL_RX, the RTS output is controlled by the hardware and is -//! asserted only when there is space available in the receive FIFO. If no -//! hardware flow control is required, \b UART_FLOWCONTROL_NONE should be -//! passed. -//! -//! \note The availability of hardware flow control varies with the -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode) -{ - // - // Check the arguments. - // - - ASSERT(UARTBaseValid(ulBase)); - ASSERT((ulMode & ~(UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX)) == 0); - - // - // Set the flow control mode as requested. - // - HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & - ~(UART_FLOWCONTROL_TX | - UART_FLOWCONTROL_RX)) | ulMode); -} - -//***************************************************************************** -// -//! Returns the UART hardware flow control mode currently in use. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns the current hardware flow control mode. -//! -//! \note The availability of hardware flow control varies with the -//! part and UART in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return Returns the current flow control mode in use. This is a -//! logical OR combination of values \b UART_FLOWCONTROL_TX if transmit -//! (CTS) flow control is enabled and \b UART_FLOWCONTROL_RX if receive (RTS) -//! flow control is in use. If hardware flow control is disabled, -//! \b UART_FLOWCONTROL_NONE is returned. -// -//***************************************************************************** -unsigned long -UARTFlowControlGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - - ASSERT(UARTBaseValid(ulBase)); - - return(HWREG(ulBase + UART_O_CTL) & (UART_FLOWCONTROL_TX | - UART_FLOWCONTROL_RX)); -} - -//***************************************************************************** -// -//! Sets the operating mode for the UART transmit interrupt. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulMode is the operating mode for the transmit interrupt. It may be -//! \b UART_TXINT_MODE_EOT to trigger interrupts when the transmitter is idle -//! or \b UART_TXINT_MODE_FIFO to trigger based on the current transmit FIFO -//! level. -//! -//! This function allows the mode of the UART transmit interrupt to be set. By -//! default, the transmit interrupt is asserted when the FIFO level falls past -//! a threshold set via a call to UARTFIFOLevelSet(). Alternatively, if this -//! function is called with \e ulMode set to \b UART_TXINT_MODE_EOT, the -//! transmit interrupt is asserted once the transmitter is completely idle - -//! the transmit FIFO is empty and all bits, including any stop bits, have -//! cleared the transmitter. -//! -//! \note The availability of end-of-transmission mode varies with the -//! part in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return None. -// -//***************************************************************************** -void -UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - ASSERT((ulMode == UART_TXINT_MODE_EOT) || - (ulMode == UART_TXINT_MODE_FIFO)); - - // - // Set or clear the EOT bit of the UART control register as appropriate. - // - HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & - ~(UART_TXINT_MODE_EOT | - UART_TXINT_MODE_FIFO)) | ulMode); -} - -//***************************************************************************** -// -//! Returns the current operating mode for the UART transmit interrupt. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns the current operating mode for the UART transmit -//! interrupt. The return value is \b UART_TXINT_MODE_EOT if the transmit -//! interrupt is currently set to be asserted once the transmitter is -//! completely idle - the transmit FIFO is empty and all bits, including any -//! stop bits, have cleared the transmitter. The return value is -//! \b UART_TXINT_MODE_FIFO if the interrupt is set to be asserted based upon -//! the level of the transmit FIFO. -//! -//! \note The availability of end-of-transmission mode varies with the -//! part in use. Please consult the datasheet for the part you are -//! using to determine whether this support is available. -//! -//! \return Returns \b UART_TXINT_MODE_FIFO or \b UART_TXINT_MODE_EOT. -// -//***************************************************************************** -unsigned long -UARTTxIntModeGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Return the current transmit interrupt mode. - // - return(HWREG(ulBase + UART_O_CTL) & (UART_TXINT_MODE_EOT | - UART_TXINT_MODE_FIFO)); -} - -//***************************************************************************** -// -//! Determines if there are any characters in the receive FIFO. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns a flag indicating whether or not there is data -//! available in the receive FIFO. -//! -//! \return Returns \b true if there is data in the receive FIFO or \b false -//! if there is no data in the receive FIFO. -// -//***************************************************************************** -tBoolean -UARTCharsAvail(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Return the availability of characters. - // - return((HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) ? false : true); -} - -//***************************************************************************** -// -//! Determines if there is any space in the transmit FIFO. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns a flag indicating whether or not there is space -//! available in the transmit FIFO. -//! -//! \return Returns \b true if there is space available in the transmit FIFO -//! or \b false if there is no space available in the transmit FIFO. -// -//***************************************************************************** -tBoolean -UARTSpaceAvail(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Return the availability of space. - // - return((HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) ? false : true); -} - -//***************************************************************************** -// -//! Receives a character from the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function gets a character from the receive FIFO for the specified -//! port. -//! -//! -//! \return Returns the character read from the specified port, cast as a -//! \e long. A \b -1 is returned if there are no characters present in the -//! receive FIFO. The UARTCharsAvail() function should be called before -//! attempting to call this function. -// -//***************************************************************************** -long -UARTCharGetNonBlocking(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // See if there are any characters in the receive FIFO. - // - if(!(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE)) - { - // - // Read and return the next character. - // - return(HWREG(ulBase + UART_O_DR)); - } - else - { - // - // There are no characters, so return a failure. - // - return(-1); - } -} - -//***************************************************************************** -// -//! Waits for a character from the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function gets a character from the receive FIFO for the specified -//! port. If there are no characters available, this function waits until a -//! character is received before returning. -//! -//! \return Returns the character read from the specified port, cast as a -//! \e long. -// -//***************************************************************************** -long -UARTCharGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Wait until a char is available. - // - while(HWREG(ulBase + UART_O_FR) & UART_FR_RXFE) - { - } - - // - // Now get the char. - // - return(HWREG(ulBase + UART_O_DR)); -} - -//***************************************************************************** -// -//! Sends a character to the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! \param ucData is the character to be transmitted. -//! -//! This function writes the character \e ucData to the transmit FIFO for the -//! specified port. This function does not block, so if there is no space -//! available, then a \b false is returned, and the application must retry the -//! function later. -//! -//! \return Returns \b true if the character was successfully placed in the -//! transmit FIFO or \b false if there was no space available in the transmit -//! FIFO. -// -//***************************************************************************** -tBoolean -UARTCharPutNonBlocking(unsigned long ulBase, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // See if there is space in the transmit FIFO. - // - if(!(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF)) - { - // - // Write this character to the transmit FIFO. - // - HWREG(ulBase + UART_O_DR) = ucData; - - // - // Success. - // - return(true); - } - else - { - // - // There is no space in the transmit FIFO, so return a failure. - // - return(false); - } -} - -//***************************************************************************** -// -//! Waits to send a character from the specified port. -//! -//! \param ulBase is the base address of the UART port. -//! \param ucData is the character to be transmitted. -//! -//! This function sends the character \e ucData to the transmit FIFO for the -//! specified port. If there is no space available in the transmit FIFO, this -//! function waits until there is space available before returning. -//! -//! \return None. -// -//***************************************************************************** -void -UARTCharPut(unsigned long ulBase, unsigned char ucData) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Wait until space is available. - // - while(HWREG(ulBase + UART_O_FR) & UART_FR_TXFF) - { - } - - // - // Send the char. - // - HWREG(ulBase + UART_O_DR) = ucData; -} - -//***************************************************************************** -// -//! Causes a BREAK to be sent. -//! -//! \param ulBase is the base address of the UART port. -//! \param bBreakState controls the output level. -//! -//! Calling this function with \e bBreakState set to \b true asserts a break -//! condition on the UART. Calling this function with \e bBreakState set to -//! \b false removes the break condition. For proper transmission of a break -//! command, the break must be asserted for at least two complete frames. -//! -//! \return None. -// -//***************************************************************************** -void -UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Set the break condition as requested. - // - HWREG(ulBase + UART_O_LCRH) = - (bBreakState ? - (HWREG(ulBase + UART_O_LCRH) | UART_LCRH_BRK) : - (HWREG(ulBase + UART_O_LCRH) & ~(UART_LCRH_BRK))); -} - -//***************************************************************************** -// -//! Determines whether the UART transmitter is busy or not. -//! -//! \param ulBase is the base address of the UART port. -//! -//! Allows the caller to determine whether all transmitted bytes have cleared -//! the transmitter hardware. If \b false is returned, the transmit FIFO is -//! empty and all bits of the last transmitted character, including all stop -//! bits, have left the hardware shift register. -//! -//! \return Returns \b true if the UART is transmitting or \b false if all -//! transmissions are complete. -// -//***************************************************************************** -tBoolean -UARTBusy(unsigned long ulBase) -{ - // - // Check the argument. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Determine if the UART is busy. - // - return((HWREG(ulBase + UART_O_FR) & UART_FR_BUSY) ? true : false); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for a UART interrupt. -//! -//! \param ulBase is the base address of the UART port. -//! \param pfnHandler is a pointer to the function to be called when the -//! UART interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! function enables the global interrupt in the interrupt controller; specific -//! UART interrupts must be enabled via UARTIntEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Determine the interrupt number based on the UART port. - // - - ulInt = UARTIntNumberGet(ulBase); - - // - // Register the interrupt handler. - // - IntRegister(ulInt, pfnHandler); - - // - // Enable the UART interrupt. - // - IntEnable(ulInt); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for a UART interrupt. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function does the actual unregistering of the interrupt handler. It -//! clears the handler to be called when a UART interrupt occurs. This -//! function also masks off the interrupt in the interrupt controller so that -//! the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntUnregister(unsigned long ulBase) -{ - unsigned long ulInt; - - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Determine the interrupt number based on the UART port. - // - ulInt = UARTIntNumberGet(ulBase); - - // - // Disable the interrupt. - // - IntDisable(ulInt); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulInt); -} - -//***************************************************************************** -// -//! Enables individual UART interrupt sources. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled. -//! -//! This function enables the indicated UART interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter is the logical OR of any of the following: -//! -//! - \b UART_INT_OE - Overrun Error interrupt -//! - \b UART_INT_BE - Break Error interrupt -//! - \b UART_INT_PE - Parity Error interrupt -//! - \b UART_INT_FE - Framing Error interrupt -//! - \b UART_INT_RT - Receive Timeout interrupt -//! - \b UART_INT_TX - Transmit interrupt -//! - \b UART_INT_RX - Receive interrupt -//! - \b UART_INT_CTS - CTS interrupt -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Enable the specified interrupts. - // - HWREG(ulBase + UART_O_IM) |= ulIntFlags; -} - -//***************************************************************************** -// -//! Disables individual UART interrupt sources. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled. -//! -//! This function disables the indicated UART interrupt sources. Only the -//! sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to UARTIntEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Disable the specified interrupts. - // - HWREG(ulBase + UART_O_IM) &= ~(ulIntFlags); -} - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \param ulBase is the base address of the UART port. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This function returns the interrupt status for the specified UART. Either -//! the raw interrupt status or the status of interrupts that are allowed to -//! reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, enumerated as a bit field of -//! values described in UARTIntEnable(). -// -//***************************************************************************** -unsigned long -UARTIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + UART_O_MIS)); - } - else - { - return(HWREG(ulBase + UART_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears UART interrupt sources. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared. -//! -//! The specified UART interrupt sources are cleared, so that they no longer -//! assert. This function must be called in the interrupt handler to keep the -//! interrupt from being recognized again immediately upon exit. -//! -//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags -//! parameter to UARTIntEnable(). -//! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Clear the requested interrupt sources. - // - HWREG(ulBase + UART_O_ICR) = ulIntFlags; -} - -//***************************************************************************** -// -//! Enable UART DMA operation. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulDMAFlags is a bit mask of the DMA features to enable. -//! -//! The specified UART DMA features are enabled. The UART can be -//! configured to use DMA for transmit or receive, and to disable -//! receive if an error occurs. The \e ulDMAFlags parameter is the -//! logical OR of any of the following values: -//! -//! - UART_DMA_RX - enable DMA for receive -//! - UART_DMA_TX - enable DMA for transmit -//! - UART_DMA_ERR_RXSTOP - disable DMA receive on UART error -//! -//! \note The uDMA controller must also be set up before DMA can be used -//! with the UART. -//! -//! \return None. -// -//***************************************************************************** -void -UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Set the requested bits in the UART DMA control register. - // - HWREG(ulBase + UART_O_DMACTL) |= ulDMAFlags; -} - -//***************************************************************************** -// -//! Disable UART DMA operation. -//! -//! \param ulBase is the base address of the UART port. -//! \param ulDMAFlags is a bit mask of the DMA features to disable. -//! -//! This function is used to disable UART DMA features that were enabled -//! by UARTDMAEnable(). The specified UART DMA features are disabled. The -//! \e ulDMAFlags parameter is the logical OR of any of the following values: -//! -//! - UART_DMA_RX - disable DMA for receive -//! - UART_DMA_TX - disable DMA for transmit -//! - UART_DMA_ERR_RXSTOP - do not disable DMA receive on UART error -//! -//! \return None. -// -//***************************************************************************** -void -UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Clear the requested bits in the UART DMA control register. - // - HWREG(ulBase + UART_O_DMACTL) &= ~ulDMAFlags; -} - -//***************************************************************************** -// -//! Gets current receiver errors. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function returns the current state of each of the 4 receiver error -//! sources. The returned errors are equivalent to the four error bits -//! returned via the previous call to UARTCharGet() or UARTCharGetNonBlocking() -//! with the exception that the overrun error is set immediately the overrun -//! occurs rather than when a character is next read. -//! -//! \return Returns a logical OR combination of the receiver error flags, -//! \b UART_RXERROR_FRAMING, \b UART_RXERROR_PARITY, \b UART_RXERROR_BREAK -//! and \b UART_RXERROR_OVERRUN. -// -//***************************************************************************** -unsigned long -UARTRxErrorGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Return the current value of the receive status register. - // - return(HWREG(ulBase + UART_O_RSR) & 0x0000000F); -} - -//***************************************************************************** -// -//! Clears all reported receiver errors. -//! -//! \param ulBase is the base address of the UART port. -//! -//! This function is used to clear all receiver error conditions reported via -//! UARTRxErrorGet(). If using the overrun, framing error, parity error or -//! break interrupts, this function must be called after clearing the interrupt -//! to ensure that later errors of the same type trigger another interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -UARTRxErrorClear(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT(UARTBaseValid(ulBase)); - - // - // Any write to the Error Clear Register will clear all bits which are - // currently set. - // - HWREG(ulBase + UART_O_ECR) = 0; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/uart.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/uart.h deleted file mode 100644 index ba03c2fb515..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/uart.h +++ /dev/null @@ -1,235 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// uart.h -// -// Defines and Macros for the UART. -// -//***************************************************************************** - -#ifndef __UART_H__ -#define __UART_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear -// as the ulIntFlags parameter, and returned from UARTIntStatus. -// -//***************************************************************************** -#define UART_INT_DMATX 0x20000 // DMA Tx Done interrupt Mask -#define UART_INT_DMARX 0x10000 // DMA Rx Done interrupt Mask -#define UART_INT_EOT 0x800 // End of transfer interrupt Mask -#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask -#define UART_INT_BE 0x200 // Break Error Interrupt Mask -#define UART_INT_PE 0x100 // Parity Error Interrupt Mask -#define UART_INT_FE 0x080 // Framing Error Interrupt Mask -#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask -#define UART_INT_TX 0x020 // Transmit Interrupt Mask -#define UART_INT_RX 0x010 // Receive Interrupt Mask -#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask - - -//***************************************************************************** -// -// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter -// and returned by UARTConfigGetExpClk in the pulConfig parameter. -// Additionally, the UART_CONFIG_PAR_* subset can be passed to -// UARTParityModeSet as the ulParity parameter, and are returned by -// UARTParityModeGet. -// -//***************************************************************************** -#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length -#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data -#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data -#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data -#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data -#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits -#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit -#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits -#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity -#define UART_CONFIG_PAR_NONE 0x00000000 // No parity -#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity -#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity -#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one -#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero - -//***************************************************************************** -// -// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and -// returned by UARTFIFOLevelGet in the pulTxLevel. -// -//***************************************************************************** -#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full -#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full -#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full -#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full -#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full - -//***************************************************************************** -// -// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and -// returned by UARTFIFOLevelGet in the pulRxLevel. -// -//***************************************************************************** -#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full -#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full -#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full -#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full -#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full - -//***************************************************************************** -// -// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). -// -//***************************************************************************** -#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error -#define UART_DMA_TX 0x00000002 // Enable DMA for transmit -#define UART_DMA_RX 0x00000001 // Enable DMA for receive - -//***************************************************************************** -// -// Values returned from UARTRxErrorGet(). -// -//***************************************************************************** -#define UART_RXERROR_OVERRUN 0x00000008 -#define UART_RXERROR_BREAK 0x00000004 -#define UART_RXERROR_PARITY 0x00000002 -#define UART_RXERROR_FRAMING 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to UARTModemControlSet()and UARTModemControlClear() -// or returned from UARTModemControlGet(). -// -//***************************************************************************** -#define UART_OUTPUT_RTS 0x00000800 - -//***************************************************************************** -// -// Values that can be returned from UARTModemStatusGet(). -// -//***************************************************************************** -#define UART_INPUT_CTS 0x00000001 - -//***************************************************************************** -// -// Values that can be passed to UARTFlowControl() or returned from -// UARTFlowControlGet(). -// -//***************************************************************************** -#define UART_FLOWCONTROL_TX 0x00008000 -#define UART_FLOWCONTROL_RX 0x00004000 -#define UART_FLOWCONTROL_NONE 0x00000000 - -//***************************************************************************** -// -// Values that can be passed to UARTTxIntModeSet() or returned from -// UARTTxIntModeGet(). -// -//***************************************************************************** -#define UART_TXINT_MODE_FIFO 0x00000000 -#define UART_TXINT_MODE_EOT 0x00000010 - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); -extern unsigned long UARTParityModeGet(unsigned long ulBase); -extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, - unsigned long ulRxLevel); -extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, - unsigned long *pulRxLevel); -extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, - unsigned long ulBaud, unsigned long ulConfig); -extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, - unsigned long *pulBaud, - unsigned long *pulConfig); -extern void UARTEnable(unsigned long ulBase); -extern void UARTDisable(unsigned long ulBase); -extern void UARTFIFOEnable(unsigned long ulBase); -extern void UARTFIFODisable(unsigned long ulBase); -extern tBoolean UARTCharsAvail(unsigned long ulBase); -extern tBoolean UARTSpaceAvail(unsigned long ulBase); -extern long UARTCharGetNonBlocking(unsigned long ulBase); -extern long UARTCharGet(unsigned long ulBase); -extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase, - unsigned char ucData); -extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); -extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); -extern tBoolean UARTBusy(unsigned long ulBase); -extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void UARTIntUnregister(unsigned long ulBase); -extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); -extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); -extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); -extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); -extern unsigned long UARTRxErrorGet(unsigned long ulBase); -extern void UARTRxErrorClear(unsigned long ulBase); -extern void UARTModemControlSet(unsigned long ulBase, - unsigned long ulControl); -extern void UARTModemControlClear(unsigned long ulBase, - unsigned long ulControl); -extern unsigned long UARTModemControlGet(unsigned long ulBase); -extern unsigned long UARTModemStatusGet(unsigned long ulBase); -extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode); -extern unsigned long UARTFlowControlGet(unsigned long ulBase); -extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode); -extern unsigned long UARTTxIntModeGet(unsigned long ulBase); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __UART_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/udma.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/udma.c deleted file mode 100644 index 001cbb8793a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/udma.c +++ /dev/null @@ -1,1257 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// udma.c -// -// Driver for the micro-DMA controller. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup uDMA_Micro_Direct_Memory_Access_api -//! @{ -// -//***************************************************************************** - - -#include "inc/hw_types.h" -#include "inc/hw_udma.h" -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "debug.h" -#include "interrupt.h" -#include "udma.h" - - -//***************************************************************************** -// -//! Enables the uDMA controller for use. -//! -//! This function enables the uDMA controller. The uDMA controller must be -//! enabled before it can be configured and used. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAEnable(void) -{ - // - // Set the master enable bit in the config register. - // - HWREG(UDMA_BASE + UDMA_O_CFG) = UDMA_CFG_MASTEN; -} - -//***************************************************************************** -// -//! Disables the uDMA controller for use. -//! -//! This function disables the uDMA controller. Once disabled, the uDMA -//! controller cannot operate until re-enabled with uDMAEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -uDMADisable(void) -{ - // - // Clear the master enable bit in the config register. - // - HWREG(UDMA_BASE + UDMA_O_CFG) = 0; -} - -//***************************************************************************** -// -//! Gets the uDMA error status. -//! -//! This function returns the uDMA error status. It should be called from -//! within the uDMA error interrupt handler to determine if a uDMA error -//! occurred. -//! -//! \return Returns non-zero if a uDMA error is pending. -// -//***************************************************************************** -unsigned long -uDMAErrorStatusGet(void) -{ - // - // Return the uDMA error status. - // - return(HWREG(UDMA_BASE + UDMA_O_ERRCLR)); -} - -//***************************************************************************** -// -//! Clears the uDMA error interrupt. -//! -//! This function clears a pending uDMA error interrupt. This function should -//! be called from within the uDMA error interrupt handler to clear the -//! interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAErrorStatusClear(void) -{ - // - // Clear the uDMA error interrupt. - // - HWREG(UDMA_BASE + UDMA_O_ERRCLR) = 1; -} - -//***************************************************************************** -// -//! Enables a uDMA channel for operation. -//! -//! \param ulChannelNum is the channel number to enable. -//! -//! This function enables a specific uDMA channel for use. This function must -//! be used to enable a channel before it can be used to perform a uDMA -//! transfer. -//! -//! When a uDMA transfer is completed, the channel is automatically disabled by -//! the uDMA controller. Therefore, this function should be called prior to -//! starting up any new transfer. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelEnable(unsigned long ulChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - - // - // Set the bit for this channel in the enable set register. - // - HWREG(UDMA_BASE + UDMA_O_ENASET) = 1 << (ulChannelNum & 0x1f); -} - -//***************************************************************************** -// -//! Disables a uDMA channel for operation. -//! -//! \param ulChannelNum is the channel number to disable. -//! -//! This function disables a specific uDMA channel. Once disabled, a channel -//! cannot respond to uDMA transfer requests until re-enabled via -//! uDMAChannelEnable(). -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelDisable(unsigned long ulChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - - // - // Set the bit for this channel in the enable clear register. - // - HWREG(UDMA_BASE + UDMA_O_ENACLR) = 1 << (ulChannelNum & 0x1f); -} - -//***************************************************************************** -// -//! Checks if a uDMA channel is enabled for operation. -//! -//! \param ulChannelNum is the channel number to check. -//! -//! This function checks to see if a specific uDMA channel is enabled. This -//! function can be used to check the status of a transfer, as the channel is -//! automatically disabled at the end of a transfer. -//! -//! \return Returns \b true if the channel is enabled, \b false if disabled. -// -//***************************************************************************** -tBoolean -uDMAChannelIsEnabled(unsigned long ulChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - - // - // AND the specified channel bit with the enable register and return the - // result. - // - return((HWREG(UDMA_BASE + UDMA_O_ENASET) & - (1 << (ulChannelNum & 0x1f))) ? true : false); -} - -//***************************************************************************** -// -//! Sets the base address for the channel control table. -//! -//! \param pControlTable is a pointer to the 1024-byte-aligned base address -//! of the uDMA channel control table. -//! -//! This function configures the base address of the channel control table. -//! This table resides in system memory and holds control information for each -//! uDMA channel. The table must be aligned on a 1024-byte boundary. The base -//! address must be configured before any of the channel functions can be used. -//! -//! The size of the channel control table depends on the number of uDMA -//! channels and the transfer modes that are used. Refer to the introductory -//! text and the microcontroller datasheet for more information about the -//! channel control table. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAControlBaseSet(void *pControlTable) -{ - // - // Check the arguments. - // - ASSERT(((unsigned long)pControlTable & ~0x3FF) == - (unsigned long)pControlTable); - ASSERT((unsigned long)pControlTable >= 0x20000000); - - // - // Program the base address into the register. - // - HWREG(UDMA_BASE + UDMA_O_CTLBASE) = (unsigned long)pControlTable; -} - -//***************************************************************************** -// -//! Gets the base address for the channel control table. -//! -//! This function gets the base address of the channel control table. This -//! table resides in system memory and holds control information for each uDMA -//! channel. -//! -//! \return Returns a pointer to the base address of the channel control table. -// -//***************************************************************************** -void * -uDMAControlBaseGet(void) -{ - // - // Read the current value of the control base register and return it to - // the caller. - // - return((void *)HWREG(UDMA_BASE + UDMA_O_CTLBASE)); -} - -//***************************************************************************** -// -//! Gets the base address for the channel control table alternate structures. -//! -//! This function gets the base address of the second half of the channel -//! control table that holds the alternate control structures for each channel. -//! -//! \return Returns a pointer to the base address of the second half of the -//! channel control table. -// -//***************************************************************************** -void * -uDMAControlAlternateBaseGet(void) -{ - // - // Read the current value of the control base register and return it to - // the caller. - // - return((void *)HWREG(UDMA_BASE + UDMA_O_ALTBASE)); -} - -//***************************************************************************** -// -//! Requests a uDMA channel to start a transfer. -//! -//! \param ulChannelNum is the channel number on which to request a uDMA -//! transfer. -//! -//! This function allows software to request a uDMA channel to begin a -//! transfer. This function could be used for performing a memory-to-memory -//! transfer or if for some reason, a transfer needs to be initiated by software -//! instead of the peripheral associated with that channel. -//! -//! \note If the channel is \b UDMA_CHANNEL_SW and interrupts are used, then -//! the completion is signaled on the uDMA dedicated interrupt. If a -//! peripheral channel is used, then the completion is signaled on the -//! peripheral's interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelRequest(unsigned long ulChannelNum) -{ - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - - // - // Set the bit for this channel in the software uDMA request register. - // - HWREG(UDMA_BASE + UDMA_O_SWREQ) = 1 << (ulChannelNum & 0x1f); -} - -//***************************************************************************** -// -//! Enables attributes of a uDMA channel. -//! -//! \param ulChannelNum is the channel to configure. -//! \param ulAttr is a combination of attributes for the channel. -//! -//! This function is used to enable attributes of a uDMA channel. -//! -//! The \e ulAttr parameter is the logical OR of any of the following: -//! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel (it is very unlikely that this flag should be used). -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelAttributeEnable(unsigned long ulChannelNum, unsigned long ulAttr) -{ - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelNum parameter, extract just the channel number - // from this parameter. - // - ulChannelNum &= 0x1f; - - // - // Set the useburst bit for this channel if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_USEBURST) - { - HWREG(UDMA_BASE + UDMA_O_USEBURSTSET) = 1 << ulChannelNum; - } - - // - // Set the alternate control select bit for this channel, - // if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_ALTSELECT) - { - HWREG(UDMA_BASE + UDMA_O_ALTSET) = 1 << ulChannelNum; - } - - // - // Set the high priority bit for this channel, if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(UDMA_BASE + UDMA_O_PRIOSET) = 1 << ulChannelNum; - } - - // - // Set the request mask bit for this channel, if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_REQMASK) - { - HWREG(UDMA_BASE + UDMA_O_REQMASKSET) = 1 << ulChannelNum; - } -} - -//***************************************************************************** -// -//! Disables attributes of a uDMA channel. -//! -//! \param ulChannelNum is the channel to configure. -//! \param ulAttr is a combination of attributes for the channel. -//! -//! This function is used to disable attributes of a uDMA channel. -//! -//! The \e ulAttr parameter is the logical OR of any of the following: -//! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel. -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelAttributeDisable(unsigned long ulChannelNum, unsigned long ulAttr) -{ - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - ASSERT((ulAttr & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT | - UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) == 0); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelNum parameter, extract just the channel number - // from this parameter. - // - ulChannelNum &= 0x1f; - - // - // Clear the useburst bit for this channel if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_USEBURST) - { - HWREG(UDMA_BASE + UDMA_O_USEBURSTCLR) = 1 << ulChannelNum; - } - - // - // Clear the alternate control select bit for this channel, if set in - // ulConfig. - // - if(ulAttr & UDMA_ATTR_ALTSELECT) - { - HWREG(UDMA_BASE + UDMA_O_ALTCLR) = 1 << ulChannelNum; - } - - // - // Clear the high priority bit for this channel, if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_HIGH_PRIORITY) - { - HWREG(UDMA_BASE + UDMA_O_PRIOCLR) = 1 << ulChannelNum; - } - - // - // Clear the request mask bit for this channel, if set in ulConfig. - // - if(ulAttr & UDMA_ATTR_REQMASK) - { - HWREG(UDMA_BASE + UDMA_O_REQMASKCLR) = 1 << ulChannelNum; - } -} - -//***************************************************************************** -// -//! Gets the enabled attributes of a uDMA channel. -//! -//! \param ulChannelNum is the channel to configure. -//! -//! This function returns a combination of flags representing the attributes of -//! the uDMA channel. -//! -//! \return Returns the logical OR of the attributes of the uDMA channel, which -//! can be any of the following: -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel. -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -// -//***************************************************************************** -unsigned long -uDMAChannelAttributeGet(unsigned long ulChannelNum) -{ - unsigned long ulAttr = 0; - - // - // Check the arguments. - // - ASSERT((ulChannelNum & 0xffff) < 32); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelNum parameter, extract just the channel number - // from this parameter. - // - ulChannelNum &= 0x1f; - - // - // Check to see if useburst bit is set for this channel. - // - if(HWREG(UDMA_BASE + UDMA_O_USEBURSTSET) & (1 << ulChannelNum)) - { - ulAttr |= UDMA_ATTR_USEBURST; - } - - // - // Check to see if the alternate control bit is set for this channel. - // - if(HWREG(UDMA_BASE + UDMA_O_ALTSET) & (1 << ulChannelNum)) - { - ulAttr |= UDMA_ATTR_ALTSELECT; - } - - // - // Check to see if the high priority bit is set for this channel. - // - if(HWREG(UDMA_BASE + UDMA_O_PRIOSET) & (1 << ulChannelNum)) - { - ulAttr |= UDMA_ATTR_HIGH_PRIORITY; - } - - // - // Check to see if the request mask bit is set for this channel. - // - if(HWREG(UDMA_BASE + UDMA_O_REQMASKSET) & (1 << ulChannelNum)) - { - ulAttr |= UDMA_ATTR_REQMASK; - } - - // - // Return the configuration flags. - // - return(ulAttr); -} - -//***************************************************************************** -// -//! Sets the control parameters for a uDMA channel control structure. -//! -//! \param ulChannelStructIndex is the logical OR of the uDMA channel number -//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! \param ulControl is logical OR of several control values to set the control -//! parameters for the channel. -//! -//! This function is used to set control parameters for a uDMA transfer. These -//! parameters are typically not changed often. -//! -//! The \e ulChannelStructIndex parameter should be the logical OR of the -//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to -//! choose whether the primary or alternate data structure is used. -//! -//! The \e ulControl parameter is the logical OR of five values: the data size, -//! the source address increment, the destination address increment, the -//! arbitration size, and the use burst flag. The choices available for each -//! of these values is described below. -//! -//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or -//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits. -//! -//! Choose the source address increment from one of \b UDMA_SRC_INC_8, -//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select -//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or -//! to select non-incrementing. -//! -//! Choose the destination address increment from one of \b UDMA_DST_INC_8, -//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE to select -//! an address increment of 8-bit bytes, 16-bit halfwords, 32-bit words, or -//! to select non-incrementing. -//! -//! The arbitration size determines how many items are transferred before -//! the uDMA controller re-arbitrates for the bus. Choose the arbitration size -//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8, -//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024 -//! items, in powers of 2. -//! -//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only -//! respond to burst requests at the tail end of a scatter-gather transfer. -//! -//! \note The address increment cannot be smaller than the data size. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelControlSet(unsigned long ulChannelStructIndex, - unsigned long ulControl) -{ - tDMAControlTable *pCtl; - - // - // Check the arguments. - // - ASSERT((ulChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ulChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - pCtl = (tDMAControlTable *)HWREG(UDMA_BASE+UDMA_O_CTLBASE); - - // - // Get the current control word value and mask off the fields to be - // changed, then OR in the new settings. - // - pCtl[ulChannelStructIndex].ulControl = - ((pCtl[ulChannelStructIndex].ulControl & - ~(UDMA_CHCTL_DSTINC_M | - UDMA_CHCTL_DSTSIZE_M | - UDMA_CHCTL_SRCINC_M | - UDMA_CHCTL_SRCSIZE_M | - UDMA_CHCTL_ARBSIZE_M | - UDMA_CHCTL_NXTUSEBURST)) | - ulControl); -} - -//***************************************************************************** -// -//! Sets the transfer parameters for a uDMA channel control structure. -//! -//! \param ulChannelStructIndex is the logical OR of the uDMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! \param ulMode is the type of uDMA transfer. -//! \param pvSrcAddr is the source address for the transfer. -//! \param pvDstAddr is the destination address for the transfer. -//! \param ulTransferSize is the number of data items to transfer. -//! -//! This function is used to configure the parameters for a uDMA transfer. -//! These parameters are typically changed often. The function -//! uDMAChannelControlSet() MUST be called at least once for this channel prior -//! to calling this function. -//! -//! The \e ulChannelStructIndex parameter should be the logical OR of the -//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to -//! choose whether the primary or alternate data structure is used. -//! -//! The \e ulMode parameter should be one of the following values: -//! -//! - \b UDMA_MODE_STOP stops the uDMA transfer. The controller sets the mode -//! to this value at the end of a transfer. -//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request. -//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once -//! started even if the request is removed. -//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the -//! primary and alternate control structures for the channel. This mode -//! allows use of ping-pong buffering for uDMA transfers. -//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather -//! transfer. -//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather -//! transfer. -//! -//! The \e pvSrcAddr and \e pvDstAddr parameters are pointers to the first -//! location of the data to be transferred. These addresses should be aligned -//! according to the item size. For example, if the item size is set to 4-bytes, -//! these addresses must be 4-byte aligned. The compiler can take care of this -//! alignment if the pointers are pointing to storage of the appropriate -//! data type. -//! -//! The \e ulTransferSize parameter is the number of data items, not the number -//! of bytes. The value of this parameter should not exceed 1024. -//! -//! The two scatter-gather modes, memory and peripheral, are actually different -//! depending on whether the primary or alternate control structure is -//! selected. This function looks for the \b UDMA_PRI_SELECT and -//! \b UDMA_ALT_SELECT flag along with the channel number and sets the -//! scatter-gather mode as appropriate for the primary or alternate control -//! structure. -//! -//! The channel must also be enabled using uDMAChannelEnable() after calling -//! this function. The transfer does not begin until the channel has been -//! configured and enabled. Note that the channel is automatically disabled -//! after the transfer is completed, meaning that uDMAChannelEnable() must be -//! called again after setting up the next transfer. -//! -//! \note Great care must be taken to not modify a channel control structure -//! that is in use or else the results are unpredictable, including the -//! possibility of undesired data transfers to or from memory or peripherals. -//! For BASIC and AUTO modes, it is safe to make changes when the channel is -//! disabled, or the uDMAChannelModeGet() returns \b UDMA_MODE_STOP. For -//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the -//! primary or alternate control structure only when the other is being used. -//! The uDMAChannelModeGet() function returns \b UDMA_MODE_STOP when a -//! channel control structure is inactive and safe to modify. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelTransferSet(unsigned long ulChannelStructIndex, - unsigned long ulMode, void *pvSrcAddr, void *pvDstAddr, - unsigned long ulTransferSize) -{ - tDMAControlTable *pControlTable; - unsigned long ulControl; - unsigned long ulInc; - unsigned long ulBufferBytes; - - // - // Check the arguments. - // - ASSERT((ulChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); - ASSERT(ulMode <= UDMA_MODE_PER_SCATTER_GATHER); - ASSERT((unsigned long)pvSrcAddr >= 0x20000000); - ASSERT((unsigned long)pvDstAddr >= 0x20000000); - ASSERT((ulTransferSize != 0) && (ulTransferSize <= 1024)); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ulChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); - - // - // Get the current control word value and mask off the mode and size - // fields. - // - ulControl = (pControlTable[ulChannelStructIndex].ulControl & - ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); - - // - // Adjust the mode if the alt control structure is selected. - // - if(ulChannelStructIndex & UDMA_ALT_SELECT) - { - if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) - { - ulMode |= UDMA_MODE_ALT_SELECT; - } - } - - // - // Set the transfer size and mode in the control word (but don't write the - // control word yet as it could kick off a transfer). - // - ulControl |= ulMode | ((ulTransferSize - 1) << 4); - - // - // Get the address increment value for the source, from the control word. - // - ulInc = (ulControl & UDMA_CHCTL_SRCINC_M); - - // - // Compute the ending source address of the transfer. If the source - // increment is set to none, then the ending address is the same as the - // beginning. - // - if(ulInc != UDMA_SRC_INC_NONE) - { - ulInc = ulInc >> 26; - ulBufferBytes = ulTransferSize << ulInc; - pvSrcAddr = (void *)((unsigned long)pvSrcAddr + ulBufferBytes - 1); - } - - // - // Load the source ending address into the control block. - // - pControlTable[ulChannelStructIndex].pvSrcEndAddr = pvSrcAddr; - - // - // Get the address increment value for the destination, from the control - // word. - // - ulInc = ulControl & UDMA_CHCTL_DSTINC_M; - - // - // Compute the ending destination address of the transfer. If the - // destination increment is set to none, then the ending address is the - // same as the beginning. - // - if(ulInc != UDMA_DST_INC_NONE) - { - // - // There is a special case if this is setting up a scatter-gather - // transfer. The destination pointer must point to the end of - // the alternate structure for this channel instead of calculating - // the end of the buffer in the normal way. - // - if((ulMode == UDMA_MODE_MEM_SCATTER_GATHER) || - (ulMode == UDMA_MODE_PER_SCATTER_GATHER)) - { - pvDstAddr = - (void *)&pControlTable[ulChannelStructIndex | - UDMA_ALT_SELECT].ulSpare; - } - // - // Not a scatter-gather transfer, calculate end pointer normally. - // - else - { - ulInc = ulInc >> 30; - ulBufferBytes = ulTransferSize << ulInc; - pvDstAddr = (void *)((unsigned long)pvDstAddr + ulBufferBytes - 1); - } - } - - // - // Load the destination ending address into the control block. - // - pControlTable[ulChannelStructIndex].pvDstEndAddr = pvDstAddr; - - // - // Write the new control word value. - // - pControlTable[ulChannelStructIndex].ulControl = ulControl; -} - -//***************************************************************************** -// -//! Configures a uDMA channel for scatter-gather mode. -//! -//! \param ulChannelNum is the uDMA channel number. -//! \param ulTaskCount is the number of scatter-gather tasks to execute. -//! \param pvTaskList is a pointer to the beginning of the scatter-gather -//! task list. -//! \param ulIsPeriphSG is a flag to indicate it is a peripheral scatter-gather -//! transfer (else it is memory scatter-gather transfer) -//! -//! This function is used to configure a channel for scatter-gather mode. -//! The caller must have already set up a task list and must pass a pointer to -//! the start of the task list as the \e pvTaskList parameter. The -//! \e ulTaskCount parameter is the count of tasks in the task list, not the -//! size of the task list. The flag \e bIsPeriphSG should be used to indicate -//! if scatter-gather should be configured for peripheral or memory -//! operation. -//! -//! \sa uDMATaskStructEntry -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelScatterGatherSet(unsigned long ulChannelNum, unsigned ulTaskCount, - void *pvTaskList, unsigned long ulIsPeriphSG) -{ - tDMAControlTable *pControlTable; - tDMAControlTable *pTaskTable; - - // - // Check the parameters - // - ASSERT((ulChannelNum & 0xffff) < 32); - ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); - ASSERT(pvTaskList != 0); - ASSERT(ulTaskCount <= 1024); - ASSERT(ulTaskCount != 0); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelNum parameter, extract just the channel number - // from this parameter. - // - ulChannelNum &= 0x1f; - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); - - // - // Get a handy pointer to the task list - // - pTaskTable = (tDMAControlTable *)pvTaskList; - - // - // Compute the ending address for the source pointer. This address is the - // last element of the last task in the task table - // - pControlTable[ulChannelNum].pvSrcEndAddr = - &pTaskTable[ulTaskCount - 1].ulSpare; - - // - // Compute the ending address for the destination pointer. This address - // is the end of the alternate structure for this channel. - // - pControlTable[ulChannelNum].pvDstEndAddr = - &pControlTable[ulChannelNum | UDMA_ALT_SELECT].ulSpare; - - // - // Compute the control word. Most configurable items are fixed for - // scatter-gather. Item and increment sizes are all 32-bit and arb - // size must be 4. The count is the number of items in the task list - // times 4 (4 words per task). - // - pControlTable[ulChannelNum].ulControl = - (UDMA_CHCTL_DSTINC_32 | UDMA_CHCTL_DSTSIZE_32 | - UDMA_CHCTL_SRCINC_32 | UDMA_CHCTL_SRCSIZE_32 | - UDMA_CHCTL_ARBSIZE_4 | - (((ulTaskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) | - (ulIsPeriphSG ? UDMA_CHCTL_XFERMODE_PER_SG : - UDMA_CHCTL_XFERMODE_MEM_SG)); -} - -//***************************************************************************** -// -//! Gets the current transfer size for a uDMA channel control structure. -//! -//! \param ulChannelStructIndex is the logical OR of the uDMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! -//! This function is used to get the uDMA transfer size for a channel. The -//! transfer size is the number of items to transfer, where the size of an item -//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, -//! then the number of remaining items is returned. If the transfer is -//! complete, then 0 is returned. -//! -//! \return Returns the number of items remaining to transfer. -// -//***************************************************************************** -unsigned long -uDMAChannelSizeGet(unsigned long ulChannelStructIndex) -{ - tDMAControlTable *pControlTable; - unsigned long ulControl; - - // - // Check the arguments. - // - ASSERT((ulChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_BASE + UDMA_O_CTLBASE) != 0); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ulChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); - - // - // Get the current control word value and mask off all but the size field - // and the mode field. - // - ulControl = (pControlTable[ulChannelStructIndex].ulControl & - (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); - - // - // If the size field and mode field are 0 then the transfer is finished - // and there are no more items to transfer - // - if(ulControl == 0) - { - return(0); - } - - // - // Otherwise, if either the size field or more field is non-zero, then - // not all the items have been transferred. - // - else - { - // - // Shift the size field and add one, then return to user. - // - return((ulControl >> 4) + 1); - } -} - -//***************************************************************************** -// -//! Gets the transfer mode for a uDMA channel control structure. -//! -//! \param ulChannelStructIndex is the logical OR of the uDMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! -//! This function is used to get the transfer mode for the uDMA channel and -//! to query the status of a transfer on a channel. When the transfer is -//! complete the mode is \b UDMA_MODE_STOP. -//! -//! \return Returns the transfer mode of the specified channel and control -//! structure, which is one of the following values: \b UDMA_MODE_STOP, -//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG, -//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. -// -//***************************************************************************** -unsigned long -uDMAChannelModeGet(unsigned long ulChannelStructIndex) -{ - tDMAControlTable *pControlTable; - unsigned long ulControl; - - // - // Check the arguments. - // - ASSERT((ulChannelStructIndex & 0xffff) < 64); - ASSERT(HWREG(UDMA_O_CTLBASE) != 0); - - // - // In case a channel selector macro (like UDMA_CH0_TIMERA0_A) was - // passed as the ulChannelStructIndex parameter, extract just the channel - // index from this parameter. - // - ulChannelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - pControlTable = (tDMAControlTable *)HWREG(UDMA_BASE + UDMA_O_CTLBASE); - - // - // Get the current control word value and mask off all but the mode field. - // - ulControl = (pControlTable[ulChannelStructIndex].ulControl & - UDMA_CHCTL_XFERMODE_M); - - // - // Check if scatter/gather mode, and if so, mask off the alt bit. - // - if(((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) || - ((ulControl & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_PER_SCATTER_GATHER)) - { - ulControl &= ~UDMA_MODE_ALT_SELECT; - } - - // - // Return the mode to the caller. - // - return(ulControl); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the uDMA controller. -//! -//! \param ulIntChannel identifies which uDMA interrupt is to be registered. -//! \param pfnHandler is a pointer to the function to be called when the -//! interrupt is activated. -//! -//! This function registers and enables the handler to be called when the uDMA -//! controller generates an interrupt. The \e ulIntChannel parameter should be -//! one of the following: -//! -//! - \b UDMA_INT_SW to register an interrupt handler to process interrupts -//! from the uDMA software channel (UDMA_CHANNEL_SW) -//! - \b UDMA_INT_ERR to register an interrupt handler to process uDMA error -//! interrupts -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note The interrupt handler for the uDMA is for transfer completion when -//! the channel UDMA_CHANNEL_SW is used and for error interrupts. The -//! interrupts for each peripheral channel are handled through the individual -//! peripheral interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAIntRegister(unsigned long ulIntChannel, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(pfnHandler); - ASSERT((ulIntChannel == UDMA_INT_SW) || (ulIntChannel == UDMA_INT_ERR)); - - // - // Register the interrupt handler. - // - IntRegister(ulIntChannel, pfnHandler); - - // - // Enable the memory management fault. - // - IntEnable(ulIntChannel); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the uDMA controller. -//! -//! \param ulIntChannel identifies which uDMA interrupt to unregister. -//! -//! This function disables and unregisters the handler to be called for the -//! specified uDMA interrupt. The \e ulIntChannel parameter should be one of -//! \b UDMA_INT_SW or \b UDMA_INT_ERR as documented for the function -//! uDMAIntRegister(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAIntUnregister(unsigned long ulIntChannel) -{ - // - // Disable the interrupt. - // - IntDisable(ulIntChannel); - - // - // Unregister the interrupt handler. - // - IntUnregister(ulIntChannel); -} - -//***************************************************************************** -// -//! Gets the uDMA controller channel interrupt status. -//! -//! This function is used to get the interrupt status of the uDMA controller. -//! The returned value is a 32-bit bit mask that indicates which channels are -//! requesting an interrupt. This function can be used from within an -//! interrupt handler to determine or confirm which uDMA channel has requested -//! an interrupt. -//! -//! \note This function is only available on devices that have the DMA Channel -//! Interrupt Status Register (DMACHIS). Please consult the data sheet for -//! your part. -//! -//! \return Returns a 32-bit mask which indicates requesting uDMA channels. -//! There is a bit for each channel and a 1 indicates that the channel -//! is requesting an interrupt. Multiple bits can be set. -// -//***************************************************************************** -unsigned long -uDMAIntStatus(void) -{ - - - // - // Return the value of the uDMA interrupt status register - // - return(HWREG(UDMA_BASE + UDMA_O_CHIS)); -} - -//***************************************************************************** -// -//! Clears uDMA interrupt status. -//! -//! \param ulChanMask is a 32-bit mask with one bit for each uDMA channel. -//! -//! This function clears bits in the uDMA interrupt status register according -//! to which bits are set in \e ulChanMask. There is one bit for each channel. -//! If a a bit is set in \e ulChanMask, then that corresponding channel's -//! interrupt status is cleared (if it was set). -//! -//! \note This function is only available on devices that have the DMA Channel -//! Interrupt Status Register (DMACHIS). Please consult the data sheet for -//! your part. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAIntClear(unsigned long ulChanMask) -{ - - // - // Clear the requested bits in the uDMA interrupt status register - // - HWREG(UDMA_BASE + UDMA_O_CHIS) = ulChanMask; -} - -//***************************************************************************** -// -//! Assigns a peripheral mapping for a uDMA channel. -//! -//! \param ulMapping is a macro specifying the peripheral assignment for -//! a channel. -//! -//! This function assigns a peripheral mapping to a uDMA channel. It is -//! used to select which peripheral is used for a uDMA channel. The parameter -//! \e ulMapping should be one of the macros named \b UDMA_CHn_tttt from the -//! header file \e udma.h. For example, to assign uDMA channel 8 to the -//! UARTA0 RX channel, the parameter should be the macro \b UDMA_CH8_UARTA0_RX. -//! -//! Please consult the data sheet for a table showing all the -//! possible peripheral assignments for the uDMA channels for a particular -//! device. -//! -//! \note This function is only available on devices that have the DMA Channel -//! Map Select registers (DMACHMAP0-3). Please consult the data sheet for -//! your part. -//! -//! \return None. -// -//***************************************************************************** -void -uDMAChannelAssign(unsigned long ulMapping) -{ - unsigned long ulMapReg; - unsigned long ulMapShift; - unsigned long ulChannelNum; - - // - // Check the parameters - // - ASSERT((ulMapping & 0xffffff00) < 0x00050000); - - - // - // Extract the channel number and map encoding value from the parameter. - // - ulChannelNum = ulMapping & 0x1f; - ulMapping = ulMapping >> 16; - - // - // Find the uDMA channel mapping register and shift value to use for this - // channel - // - ulMapReg = UDMA_BASE + UDMA_O_CHMAP0 + ((ulChannelNum / 8) * 4); - ulMapShift = (ulChannelNum % 8) * 4; - - // - // Set the channel map encoding for this channel - // - HWREG(ulMapReg) = (HWREG(ulMapReg) & ~(0xf << ulMapShift)) | - ulMapping << ulMapShift; -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/udma.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/udma.h deleted file mode 100644 index ca95de0d525..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/udma.h +++ /dev/null @@ -1,664 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// udma.h -// -// Prototypes and macros for the uDMA controller. -// -//***************************************************************************** - -#ifndef __UDMA_H__ -#define __UDMA_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//! \addtogroup uDMA_Micro_Direct_Memory_Access_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// A structure that defines an entry in the channel control table. These -// fields are used by the uDMA controller and normally it is not necessary for -// software to directly read or write fields in the table. -// -//***************************************************************************** -typedef struct -{ - // - // The ending source address of the data transfer. - // - volatile void *pvSrcEndAddr; - - // - // The ending destination address of the data transfer. - // - volatile void *pvDstEndAddr; - - // - // The channel control mode. - // - volatile unsigned long ulControl; - - // - // An unused location. - // - volatile unsigned long ulSpare; -} -tDMAControlTable; - -//***************************************************************************** -// -//! A helper macro for building scatter-gather task table entries. -//! -//! \param ulTransferCount is the count of items to transfer for this task. -//! \param ulItemSize is the bit size of the items to transfer for this task. -//! \param ulSrcIncrement is the bit size increment for source data. -//! \param pvSrcAddr is the starting address of the data to transfer. -//! \param ulDstIncrement is the bit size increment for destination data. -//! \param pvDstAddr is the starting address of the destination data. -//! \param ulArbSize is the arbitration size to use for the transfer task. -//! \param ulMode is the transfer mode for this task. -//! -//! This macro is intended to be used to help populate a table of uDMA tasks -//! for a scatter-gather transfer. This macro will calculate the values for -//! the fields of a task structure entry based on the input parameters. -//! -//! There are specific requirements for the values of each parameter. No -//! checking is done so it is up to the caller to ensure that correct values -//! are used for the parameters. -//! -//! The \e ulTransferCount parameter is the number of items that will be -//! transferred by this task. It must be in the range 1-1024. -//! -//! The \e ulItemSize parameter is the bit size of the transfer data. It must -//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. -//! -//! The \e ulSrcIncrement parameter is the increment size for the source data. -//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, -//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. -//! -//! The \e pvSrcAddr parameter is a void pointer to the beginning of the source -//! data. -//! -//! The \e ulDstIncrement parameter is the increment size for the destination -//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, -//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. -//! -//! The \e pvDstAddr parameter is a void pointer to the beginning of the -//! location where the data will be transferred. -//! -//! The \e ulArbSize parameter is the arbitration size for the transfer, and -//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on -//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in -//! powers of 2, from 1 to 1024. -//! -//! The \e ulMode parameter is the mode to use for this transfer task. It -//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, -//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note -//! that normally all tasks will be one of the scatter-gather modes while the -//! last task is a task list will be AUTO or BASIC. -//! -//! This macro is intended to be used to initialize individual entries of -//! a structure of tDMAControlTable type, like this: -//! -//! \verbatim -//! tDMAControlTable MyTaskList[] = -//! { -//! uDMATaskStructEntry(Task1Count, UDMA_SIZE_8, -//! UDMA_SRC_INC_8, MySourceBuf, -//! UDMA_DST_INC_8, MyDestBuf, -//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), -//! uDMATaskStructEntry(Task2Count, ... ), -//! } -//! \endverbatim -//! -//! \return Nothing; this is not a function. -// -//***************************************************************************** -#define uDMATaskStructEntry(ulTransferCount, \ - ulItemSize, \ - ulSrcIncrement, \ - pvSrcAddr, \ - ulDstIncrement, \ - pvDstAddr, \ - ulArbSize, \ - ulMode) \ - { \ - (((ulSrcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(pvSrcAddr) : \ - ((void *)(&((unsigned char *)(pvSrcAddr))[((ulTransferCount) << \ - ((ulSrcIncrement) >> 26)) - 1]))), \ - (((ulDstIncrement) == UDMA_DST_INC_NONE) ? (void *)(pvDstAddr) : \ - ((void *)(&((unsigned char *)(pvDstAddr))[((ulTransferCount) << \ - ((ulDstIncrement) >> 30)) - 1]))), \ - (ulSrcIncrement) | (ulDstIncrement) | (ulItemSize) | (ulArbSize) | \ - (((ulTransferCount) - 1) << 4) | \ - ((((ulMode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ - ((ulMode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ - (ulMode) | UDMA_MODE_ALT_SELECT : (ulMode)), 0 \ - } - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -//***************************************************************************** -// -// Flags that can be passed to uDMAChannelAttributeEnable(), -// uDMAChannelAttributeDisable(), and returned from uDMAChannelAttributeGet(). -// -//***************************************************************************** -#define UDMA_ATTR_USEBURST 0x00000001 -#define UDMA_ATTR_ALTSELECT 0x00000002 -#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 -#define UDMA_ATTR_REQMASK 0x00000008 -#define UDMA_ATTR_ALL 0x0000000F - -//***************************************************************************** -// -// DMA control modes that can be passed to uDMAModeSet() and returned -// uDMAModeGet(). -// -//***************************************************************************** -#define UDMA_MODE_STOP 0x00000000 -#define UDMA_MODE_BASIC 0x00000001 -#define UDMA_MODE_AUTO 0x00000002 -#define UDMA_MODE_PINGPONG 0x00000003 -#define UDMA_MODE_MEM_SCATTER_GATHER \ - 0x00000004 -#define UDMA_MODE_PER_SCATTER_GATHER \ - 0x00000006 -#define UDMA_MODE_ALT_SELECT 0x00000001 - -//***************************************************************************** -// -// Flags to be OR'd with the channel ID to indicate if the primary or alternate -// control structure should be used. -// -//***************************************************************************** -#define UDMA_PRI_SELECT 0x00000000 -#define UDMA_ALT_SELECT 0x00000020 - -//***************************************************************************** -// -// uDMA interrupt sources, to be passed to uDMAIntRegister() and -// uDMAIntUnregister(). -// -//***************************************************************************** -#define UDMA_INT_SW INT_UDMA -#define UDMA_INT_ERR INT_UDMAERR - -//***************************************************************************** - -//***************************************************************************** -// -// Channel configuration values that can be passed to uDMAControlSet(). -// -//***************************************************************************** -#define UDMA_DST_INC_8 0x00000000 -#define UDMA_DST_INC_16 0x40000000 -#define UDMA_DST_INC_32 0x80000000 -#define UDMA_DST_INC_NONE 0xc0000000 -#define UDMA_SRC_INC_8 0x00000000 -#define UDMA_SRC_INC_16 0x04000000 -#define UDMA_SRC_INC_32 0x08000000 -#define UDMA_SRC_INC_NONE 0x0c000000 -#define UDMA_SIZE_8 0x00000000 -#define UDMA_SIZE_16 0x11000000 -#define UDMA_SIZE_32 0x22000000 -#define UDMA_ARB_1 0x00000000 -#define UDMA_ARB_2 0x00004000 -#define UDMA_ARB_4 0x00008000 -#define UDMA_ARB_8 0x0000c000 -#define UDMA_ARB_16 0x00010000 -#define UDMA_ARB_32 0x00014000 -#define UDMA_ARB_64 0x00018000 -#define UDMA_ARB_128 0x0001c000 -#define UDMA_ARB_256 0x00020000 -#define UDMA_ARB_512 0x00024000 -#define UDMA_ARB_1024 0x00028000 -#define UDMA_NEXT_USEBURST 0x00000008 - -//***************************************************************************** -// -// Values that can be passed to uDMAChannelAssign() to select peripheral -// mapping for each channel. The channels named RESERVED may be assigned -// to a peripheral in future parts. -// -//***************************************************************************** -// -// Channel 0 -// -#define UDMA_CH0_TIMERA0_A 0x00000000 -#define UDMA_CH0_SHAMD5_CIN 0x00010000 -#define UDMA_CH0_SW 0x00030000 - -// -// Channel 1 -// -#define UDMA_CH1_TIMERA0_B 0x00000001 -#define UDMA_CH1_SHAMD5_DIN 0x00010001 -#define UDMA_CH1_SW 0x00030001 - -// -// Channel 2 -// -#define UDMA_CH2_TIMERA1_A 0x00000002 -#define UDMA_CH2_SHAMD5_COUT 0x00010002 -#define UDMA_CH2_SW 0x00030002 - -// -// Channel 3 -// -#define UDMA_CH3_TIMERA1_B 0x00000003 -#define UDMA_CH3_DES_CIN 0x00010003 -#define UDMA_CH3_SW 0x00030003 - -// -// Channel 4 -// -#define UDMA_CH4_TIMERA2_A 0x00000004 -#define UDMA_CH4_DES_DIN 0x00010004 -#define UDMA_CH4_I2S_RX 0x00020004 -#define UDMA_CH4_SW 0x00030004 - -// -// Channel 5 -// -#define UDMA_CH5_TIMERA2_B 0x00000005 -#define UDMA_CH5_DES_DOUT 0x00010005 -#define UDMA_CH5_I2S_TX 0x00020005 -#define UDMA_CH5_SW 0x00030005 - -// -// Channel 6 -// -#define UDMA_CH6_TIMERA3_A 0x00000006 -#define UDMA_CH6_GSPI_RX 0x00010006 -#define UDMA_CH6_GPIOA2 0x00020006 -#define UDMA_CH6_SW 0x00030006 - -// -// Channel 7 -// -#define UDMA_CH7_TIMERA3_B 0x00000007 -#define UDMA_CH7_GSPI_TX 0x00010007 -#define UDMA_CH7_GPIOA3 0x00020007 -#define UDMA_CH7_SW 0x00030007 - - -// -// Channel 8 -// -#define UDMA_CH8_UARTA0_RX 0x00000008 -#define UDMA_CH8_TIMERA0_A 0x00010008 -#define UDMA_CH8_TIMERA2_A 0x00020008 -#define UDMA_CH8_SW 0x00030008 - - -// -// Channel 9 -// -#define UDMA_CH9_UARTA0_TX 0x00000009 -#define UDMA_CH9_TIMERA0_B 0x00010009 -#define UDMA_CH9_TIMERA2_B 0x00020009 -#define UDMA_CH9_SW 0x00030009 - - -// -// Channel 10 -// -#define UDMA_CH10_UARTA1_RX 0x0000000A -#define UDMA_CH10_TIMERA1_A 0x0001000A -#define UDMA_CH10_TIMERA3_A 0x0002000A -#define UDMA_CH10_SW 0x0003000A - -// -// Channel 11 -// -#define UDMA_CH11_UARTA1_TX 0x0000000B -#define UDMA_CH11_TIMERA1_B 0x0001000B -#define UDMA_CH11_TIMERA3_B 0x0002000B -#define UDMA_CH11_SW 0x0003000B - - -// -// Channel 12 -// -#define UDMA_CH12_LSPI_RX 0x0000000C -#define UDMA_CH12_SW 0x0003000C - - -// -// Channel 13 -// -#define UDMA_CH13_LSPI_TX 0x0000000D -#define UDMA_CH13_SW 0x0003000D - - -// -// Channel 14 -// -#define UDMA_CH14_ADC_CH0 0x0000000E -#define UDMA_CH14_SDHOST_RX 0x0002000E -#define UDMA_CH14_SW 0x0003000E - - -// -// Channel 15 -// -#define UDMA_CH15_ADC_CH1 0x0000000F -#define UDMA_CH15_SDHOST_TX 0x0002000F -#define UDMA_CH15_SW 0x0003000F - - -// -// Channel 16 -// -#define UDMA_CH16_ADC_CH2 0x00000010 -#define UDMA_CH16_TIMERA2_A 0x00010010 -#define UDMA_CH16_SW 0x00030010 - - -// -// Channel 17 -// -#define UDMA_CH17_ADC_CH3 0x00000011 -#define UDMA_CH17_TIMERA2_B 0x00010011 -#define UDMA_CH17_SW 0x00030011 - -// -// Channel 18 -// -#define UDMA_CH18_GPIOA0 0x00000012 -#define UDMA_CH18_AES_CIN 0x00010012 -#define UDMA_CH18_I2S_RX 0x00020012 -#define UDMA_CH18_SW 0x00030012 - - -// -// Channel 19 -// -#define UDMA_CH19_GPOIA1 0x00000013 -#define UDMA_CH19_AES_COUT 0x00010013 -#define UDMA_CH19_I2S_TX 0x00020013 -#define UDMA_CH19_SW 0x00030013 - - -// -// Channel 20 -// -#define UDMA_CH20_GPIOA2 0x00000014 -#define UDMA_CH20_AES_DIN 0x00010014 -#define UDMA_CH20_SW 0x00030014 - - -// -// Channel 21 -// -#define UDMA_CH21_GPIOA3 0x00000015 -#define UDMA_CH21_AES_DOUT 0x00010015 -#define UDMA_CH21_SW 0x00030015 - - -// -// Channel 22 -// -#define UDMA_CH22_CAMERA 0x00000016 -#define UDMA_CH22_GPIOA4 0x00010016 -#define UDMA_CH22_SW 0x00030016 - - -// -// Channel 23 -// -#define UDMA_CH23_SDHOST_RX 0x00000017 -#define UDMA_CH23_TIMERA3_A 0x00010017 -#define UDMA_CH23_TIMERA2_A 0x00020017 -#define UDMA_CH23_SW 0x00030017 - - -// -// Channel 24 -// -#define UDMA_CH24_SDHOST_TX 0x00000018 -#define UDMA_CH24_TIMERA3_B 0x00010018 -#define UDMA_CH24_TIMERA2_B 0x00020018 -#define UDMA_CH24_SW 0x00030018 - - -// -// Channel 25 -// -#define UDMA_CH25_SSPI_RX 0x00000019 -#define UDMA_CH25_I2CA0_RX 0x00010019 -#define UDMA_CH25_SW 0x00030019 - - -// -// Channel 26 -// -#define UDMA_CH26_SSPI_TX 0x0000001A -#define UDMA_CH26_I2CA0_TX 0x0001001A -#define UDMA_CH26_SW 0x0003001A - - -// -// Channel 27 -// -#define UDMA_CH27_GPIOA0 0x0001001B -#define UDMA_CH27_SW 0x0003001B - - -// -// Channel 28 -// -#define UDMA_CH28_GPIOA1 0x0001001C -#define UDMA_CH28_SW 0x0003001C - - -// -// Channel 29 -// -#define UDMA_CH29_GPIOA4 0x0000001D -#define UDMA_CH29_SW 0x0003001D - - -// -// Channel 30 -// -#define UDMA_CH30_GSPI_RX 0x0000001E -#define UDMA_CH30_SDHOST_RX 0x0001001E -#define UDMA_CH30_I2CA0_RX 0x0002001E -#define UDMA_CH30_SW 0x0003001E - - -// -// Channel 31 -// -#define UDMA_CH31_GSPI_TX 0x0000001F -#define UDMA_CH31_SDHOST_TX 0x0001001F -#define UDMA_CH31_I2CA0_RX 0x0002001F -#define UDMA_CH31_SW 0x0003001F - -//***************************************************************************** -// -// The following are defines for the Micro Direct Memory Access (uDMA) offsets. -// -//***************************************************************************** -#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End - // Pointer -#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address - // End Pointer -#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_SRCENDP register. -// -//***************************************************************************** -#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer -#define UDMA_SRCENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_DSTENDP register. -// -//***************************************************************************** -#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer -#define UDMA_DSTENDP_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHCTL register. -// -//***************************************************************************** -#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment -#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word -#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word -#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment -#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word -#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment -#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word -#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word -#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment -#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word -#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers -#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst -#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode -#define UDMA_CHCTL_XFERMODE_STOP \ - 0x00000000 // Stop -#define UDMA_CHCTL_XFERMODE_BASIC \ - 0x00000001 // Basic -#define UDMA_CHCTL_XFERMODE_AUTO \ - 0x00000002 // Auto-Request -#define UDMA_CHCTL_XFERMODE_PINGPONG \ - 0x00000003 // Ping-Pong -#define UDMA_CHCTL_XFERMODE_MEM_SG \ - 0x00000004 // Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_MEM_SGA \ - 0x00000005 // Alternate Memory Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SG \ - 0x00000006 // Peripheral Scatter-Gather -#define UDMA_CHCTL_XFERMODE_PER_SGA \ - 0x00000007 // Alternate Peripheral - // Scatter-Gather -#define UDMA_CHCTL_XFERSIZE_S 4 - - - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void uDMAEnable(void); -extern void uDMADisable(void); -extern unsigned long uDMAErrorStatusGet(void); -extern void uDMAErrorStatusClear(void); -extern void uDMAChannelEnable(unsigned long ulChannelNum); -extern void uDMAChannelDisable(unsigned long ulChannelNum); -extern tBoolean uDMAChannelIsEnabled(unsigned long ulChannelNum); -extern void uDMAControlBaseSet(void *pControlTable); -extern void *uDMAControlBaseGet(void); -extern void *uDMAControlAlternateBaseGet(void); -extern void uDMAChannelRequest(unsigned long ulChannelNum); -extern void uDMAChannelAttributeEnable(unsigned long ulChannelNum, - unsigned long ulAttr); -extern void uDMAChannelAttributeDisable(unsigned long ulChannelNum, - unsigned long ulAttr); -extern unsigned long uDMAChannelAttributeGet(unsigned long ulChannelNum); -extern void uDMAChannelControlSet(unsigned long ulChannelStructIndex, - unsigned long ulControl); -extern void uDMAChannelTransferSet(unsigned long ulChannelStructIndex, - unsigned long ulMode, void *pvSrcAddr, - void *pvDstAddr, - unsigned long ulTransferSize); -extern void uDMAChannelScatterGatherSet(unsigned long ulChannelNum, - unsigned ulTaskCount, void *pvTaskList, - unsigned long ulIsPeriphSG); -extern unsigned long uDMAChannelSizeGet(unsigned long ulChannelStructIndex); -extern unsigned long uDMAChannelModeGet(unsigned long ulChannelStructIndex); -extern void uDMAIntRegister(unsigned long ulIntChannel, - void (*pfnHandler)(void)); -extern void uDMAIntUnregister(unsigned long ulIntChannel); -extern unsigned long uDMAIntStatus(void); -extern void uDMAIntClear(unsigned long ulChanMask); -extern void uDMAChannelAssign(unsigned long ulMapping); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __UDMA_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/utils.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/utils.c deleted file mode 100644 index 7ef7b63d5cc..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/utils.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// utils.c -// -// Utility APIs -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup Utils_api -//! @{ -// -//***************************************************************************** -#include "utils.h" - - -//***************************************************************************** -// -//! Provides a small delay. -//! -//! \param ulCount is the number of delay loop iterations to perform. -//! -//! This function provides a means of generating a constant length delay. It -//! is written in assembly to keep the delay consistent across tool chains, -//! avoiding the need to tune the delay based on the tool chain in use. -//! -//! The loop takes 3 cycles/loop. -//! -//! \return None. -// -//***************************************************************************** -#if defined(ewarm) || defined(DOXYGEN) -void -UtilsDelay(unsigned long ulCount) -{ - __asm(" subs r0, #1\n" - " bne.n UtilsDelay\n"); -} -#endif - -#if defined(gcc) -void __attribute__((naked)) -UtilsDelay(unsigned long ulCount) -{ - __asm(" subs r0, #1\n" - " bne UtilsDelay\n" - " bx lr"); -} -#endif - -// -// For CCS implement this function in pure assembly. This prevents the TI -// compiler from doing funny things with the optimizer. -// -#if defined(ccs) - __asm(" .sect \".text:UtilsDelay\"\n" - " .clink\n" - " .thumbfunc UtilsDelay\n" - " .thumb\n" - " .global UtilsDelay\n" - "UtilsDelay:\n" - " subs r0, #1\n" - " bne.n UtilsDelay\n" - " bx lr\n"); -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/utils.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/utils.h deleted file mode 100644 index ded80647155..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/utils.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// utils.h -// -// Prototypes and macros for utility APIs -// -//***************************************************************************** - -#ifndef __UTILS_H__ -#define __UTILS_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** -extern void UtilsDelay(unsigned long ulCount); - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif //__UTILS_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/version.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/version.h deleted file mode 100644 index 581b9617c99..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/version.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// version.h -// -// Contains Driverlib version details -// -//***************************************************************************** - -#ifndef __DRIVERLIB_VERSION_H__ -#define __DRIVERLIB_VERSION_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#define DRIVERLIB_MAJOR_VERSION_NUM 01 -#define DRIVERLIB_MINOR_VERSION_NUM 51 -#define DRIVERLIB_PATCH_VERSION_NUM 04 -#define DRIVERLIB_BUILD_VERSION_NUM 00 -#define DRIVERLIB_RELEASE_DAY 15 -#define DRIVERLIB_RELEASE_MONTH 04 -#define DRIVERLIB_RELEASE_YEAR 2018 - -///////////////////////////////////////////// -// !!! Please update the changes.log file !!! -///////////////////////////////////////////// - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_VERSION_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/wdt.c b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/wdt.c deleted file mode 100644 index c0358b1691f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/wdt.c +++ /dev/null @@ -1,492 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// wdt.c -// -// Driver for the Watchdog Timer Module. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \addtogroup WDT_Watchdog_Timer_api -//! @{ -// -//***************************************************************************** - -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_wdt.h" -#include "debug.h" -#include "interrupt.h" -#include "wdt.h" - -//***************************************************************************** -// -//! Determines if the watchdog timer is enabled. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This will check to see if the watchdog timer is enabled. -//! -//! \return Returns \b true if the watchdog timer is enabled, and \b false -//! if it is not. -// -//***************************************************************************** -tBoolean -WatchdogRunning(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // See if the watchdog timer module is enabled, and return. - // - return(HWREG(ulBase + WDT_O_CTL) & WDT_CTL_INTEN); -} - -//***************************************************************************** -// -//! Enables the watchdog timer. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This will enable the watchdog timer counter and interrupt. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock() -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Enable the watchdog timer module. - // - HWREG(ulBase + WDT_O_CTL) |= WDT_CTL_INTEN; -} - -//***************************************************************************** -// -//! Enables the watchdog timer lock mechanism. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Locks out write access to the watchdog timer configuration registers. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogLock(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Lock out watchdog register writes. Writing anything to the WDT_O_LOCK - // register causes the lock to go into effect. - // - HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_LOCKED; -} - -//***************************************************************************** -// -//! Disables the watchdog timer lock mechanism. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Enables write access to the watchdog timer configuration registers. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogUnlock(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Unlock watchdog register writes. - // - HWREG(ulBase + WDT_O_LOCK) = WDT_LOCK_UNLOCK; -} - -//***************************************************************************** -// -//! Gets the state of the watchdog timer lock mechanism. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! Returns the lock state of the watchdog timer registers. -//! -//! \return Returns \b true if the watchdog timer registers are locked, and -//! \b false if they are not locked. -// -//***************************************************************************** -tBoolean -WatchdogLockState(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Get the lock state. - // - return((HWREG(ulBase + WDT_O_LOCK) == WDT_LOCK_LOCKED) ? true : false); -} - -//***************************************************************************** -// -//! Sets the watchdog timer reload value. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! \param ulLoadVal is the load value for the watchdog timer. -//! -//! This function sets the value to load into the watchdog timer when the count -//! reaches zero for the first time; if the watchdog timer is running when this -//! function is called, then the value will be immediately loaded into the -//! watchdog timer counter. If the \e ulLoadVal parameter is 0, then an -//! interrupt is immediately generated. -//! -//! \note This function will have no effect if the watchdog timer has -//! been locked. -//! -//! \sa WatchdogLock(), WatchdogUnlock(), WatchdogReloadGet() -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Set the load register. - // - HWREG(ulBase + WDT_O_LOAD) = ulLoadVal; -} - -//***************************************************************************** -// -//! Gets the watchdog timer reload value. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function gets the value that is loaded into the watchdog timer when -//! the count reaches zero for the first time. -//! -//! \sa WatchdogReloadSet() -//! -//! \return None. -// -//***************************************************************************** -unsigned long -WatchdogReloadGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Get the load register. - // - return(HWREG(ulBase + WDT_O_LOAD)); -} - -//***************************************************************************** -// -//! Gets the current watchdog timer value. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function reads the current value of the watchdog timer. -//! -//! \return Returns the current value of the watchdog timer. -// -//***************************************************************************** -unsigned long -WatchdogValueGet(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Get the current watchdog timer register value. - // - return(HWREG(ulBase + WDT_O_VALUE)); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! \param pfnHandler is a pointer to the function to be called when the -//! watchdog timer interrupt occurs. -//! -//! This function does the actual registering of the interrupt handler. This -//! will enable the global interrupt in the interrupt controller; the watchdog -//! timer interrupt must be enabled via WatchdogEnable(). It is the interrupt -//! handler's responsibility to clear the interrupt source via -//! WatchdogIntClear(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note This function will only register the standard watchdog interrupt -//! handler. To register the NMI watchdog handler, use IntRegister() -//! to register the handler for the \b FAULT_NMI interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntRegister(unsigned long ulBase, void (*pfnHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Register the interrupt handler and - // Enable the watchdog timer interrupt. - // - IntRegister(INT_WDT, pfnHandler); - IntEnable(INT_WDT); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function does the actual unregistering of the interrupt handler. This -//! function will clear the handler to be called when a watchdog timer -//! interrupt occurs. This will also mask off the interrupt in the interrupt -//! controller so that the interrupt handler no longer is called. -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \note This function will only unregister the standard watchdog interrupt -//! handler. To unregister the NMI watchdog handler, use IntUnregister() -//! to unregister the handler for the \b FAULT_NMI interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntUnregister(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Disable the interrupt - IntDisable(INT_WDT); - - // - // Unregister the interrupt handler. - // - IntUnregister(INT_WDT); -} - -//***************************************************************************** -// -//! Gets the current watchdog timer interrupt status. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! \param bMasked is \b false if the raw interrupt status is required and -//! \b true if the masked interrupt status is required. -//! -//! This returns the interrupt status for the watchdog timer module. Either -//! the raw interrupt status or the status of interrupt that is allowed to -//! reflect to the processor can be returned. -//! -//! \return Returns the current interrupt status, where a 1 indicates that the -//! watchdog interrupt is active, and a 0 indicates that it is not active. -// -//***************************************************************************** -unsigned long -WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Return either the interrupt status or the raw interrupt status as - // requested. - // - if(bMasked) - { - return(HWREG(ulBase + WDT_O_MIS)); - } - else - { - return(HWREG(ulBase + WDT_O_RIS)); - } -} - -//***************************************************************************** -// -//! Clears the watchdog timer interrupt. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! The watchdog timer interrupt source is cleared, so that it no longer -//! asserts. -//! -//! \note Because there is a write buffer in the Cortex-M3 processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogIntClear(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Clear the interrupt source. - // - HWREG(ulBase + WDT_O_ICR) = WDT_INT_TIMEOUT; -} - -//***************************************************************************** -// -//! Enables stalling of the watchdog timer during debug events. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function allows the watchdog timer to stop counting when the processor -//! is stopped by the debugger. By doing so, the watchdog is prevented from -//! expiring (typically almost immediately from a human time perspective) and -//! resetting the system (if reset is enabled). The watchdog will instead -//! expired after the appropriate number of processor cycles have been executed -//! while debugging (or at the appropriate time after the processor has been -//! restarted). -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogStallEnable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Enable timer stalling. - // - HWREG(ulBase + WDT_O_TEST) |= WDT_TEST_STALL; -} - -//***************************************************************************** -// -//! Disables stalling of the watchdog timer during debug events. -//! -//! \param ulBase is the base address of the watchdog timer module. -//! -//! This function disables the debug mode stall of the watchdog timer. By -//! doing so, the watchdog timer continues to count regardless of the processor -//! debug state. -//! -//! \return None. -// -//***************************************************************************** -void -WatchdogStallDisable(unsigned long ulBase) -{ - // - // Check the arguments. - // - ASSERT((ulBase == WDT_BASE)); - - // - // Disable timer stalling. - // - HWREG(ulBase + WDT_O_TEST) &= ~(WDT_TEST_STALL); -} - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/wdt.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/wdt.h deleted file mode 100644 index 7a14d3fc0a0..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/driverlib/wdt.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** -// -// wdt.h - Prototypes for the Watchdog Timer API -// -// - -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern tBoolean WatchdogRunning(unsigned long ulBase); -extern void WatchdogEnable(unsigned long ulBase); -extern void WatchdogLock(unsigned long ulBase); -extern void WatchdogUnlock(unsigned long ulBase); -extern tBoolean WatchdogLockState(unsigned long ulBase); -extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); -extern unsigned long WatchdogReloadGet(unsigned long ulBase); -extern unsigned long WatchdogValueGet(unsigned long ulBase); -extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); -extern void WatchdogIntUnregister(unsigned long ulBase); -extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); -extern void WatchdogIntClear(unsigned long ulBase); -extern void WatchdogStallEnable(unsigned long ulBase); -extern void WatchdogStallDisable(unsigned long ulBase); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __WATCHDOG_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/asmdefs.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/asmdefs.h deleted file mode 100644 index de722a7ff27..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/asmdefs.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -//***************************************************************************** -// -// asmdefs.h - Macros to allow assembly code be portable among toolchains. -// -//***************************************************************************** - -#ifndef __ASMDEFS_H__ -#define __ASMDEFS_H__ - -//***************************************************************************** -// -// The defines required for code_red. -// -//***************************************************************************** -#ifdef codered - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // codered - -//***************************************************************************** -// -// The defines required for EW-ARM. -// -//***************************************************************************** -#ifdef ewarm - -// -// Section headers. -// -#define __LIBRARY__ module -#define __TEXT__ rseg CODE:CODE(2) -#define __DATA__ rseg DATA:DATA(2) -#define __BSS__ rseg DATA:DATA(2) -#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) - -// -// Assembler nmenonics. -// -#define __ALIGN__ alignrom 2 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ thumb -#define __WORD__ dcd -#define __INLINE_DATA__ data - -#endif // ewarm - -//***************************************************************************** -// -// The defines required for GCC. -// -//***************************************************************************** -#if defined(gcc) - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // gcc - -//***************************************************************************** -// -// The defines required for RV-MDK. -// -//***************************************************************************** -#ifdef rvmdk - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - thumb - require8 - preserve8 - -// -// Section headers. -// -#define __LIBRARY__ ; -#define __TEXT__ area ||.text||, code, readonly, align=2 -#define __DATA__ area ||.data||, data, align=2 -#define __BSS__ area ||.bss||, noinit, align=2 -#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 - -// -// Assembler nmenonics. -// -#define __ALIGN__ align 4 -#define __END__ end -#define __EXPORT__ export -#define __IMPORT__ import -#define __LABEL__ -#define __STR__ dcb -#define __THUMB_LABEL__ -#define __WORD__ dcd -#define __INLINE_DATA__ - -#endif // rvmdk - -//***************************************************************************** -// -// The defines required for Sourcery G++. -// -//***************************************************************************** -#if defined(sourcerygxx) - -// -// The assembly code preamble required to put the assembler into the correct -// configuration. -// - .syntax unified - .thumb - -// -// Section headers. -// -#define __LIBRARY__ @ -#define __TEXT__ .text -#define __DATA__ .data -#define __BSS__ .bss -#define __TEXT_NOROOT__ .text - -// -// Assembler nmenonics. -// -#define __ALIGN__ .balign 4 -#define __END__ .end -#define __EXPORT__ .globl -#define __IMPORT__ .extern -#define __LABEL__ : -#define __STR__ .ascii -#define __THUMB_LABEL__ .thumb_func -#define __WORD__ .word -#define __INLINE_DATA__ - -#endif // sourcerygxx - -#endif // __ASMDEF_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_adc.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_adc.h deleted file mode 100644 index d518bc3222b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_adc.h +++ /dev/null @@ -1,886 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_ADC_H__ -#define __HW_ADC_H__ - -//***************************************************************************** -// -// The following are defines for the ADC register offsets. -// -//***************************************************************************** -#define ADC_O_ADC_CTRL 0x00000000 // ADC control register. -#define ADC_O_adc_ch0_gain 0x00000004 // Channel 0 gain setting -#define ADC_O_adc_ch1_gain 0x00000008 // Channel 1 gain setting -#define ADC_O_adc_ch2_gain 0x0000000C // Channel 2 gain setting -#define ADC_O_adc_ch3_gain 0x00000010 // Channel 3 gain setting -#define ADC_O_adc_ch4_gain 0x00000014 // Channel 4 gain setting -#define ADC_O_adc_ch5_gain 0x00000018 // Channel 5 gain setting -#define ADC_O_adc_ch6_gain 0x0000001C // Channel 6 gain setting -#define ADC_O_adc_ch7_gain 0x00000020 // Channel 7 gain setting -#define ADC_O_adc_ch0_irq_en 0x00000024 // Channel 0 interrupt enable - // register -#define ADC_O_adc_ch1_irq_en 0x00000028 // Channel 1 interrupt enable - // register -#define ADC_O_adc_ch2_irq_en 0x0000002C // Channel 2 interrupt enable - // register -#define ADC_O_adc_ch3_irq_en 0x00000030 // Channel 3 interrupt enable - // register -#define ADC_O_adc_ch4_irq_en 0x00000034 // Channel 4 interrupt enable - // register -#define ADC_O_adc_ch5_irq_en 0x00000038 // Channel 5 interrupt enable - // register -#define ADC_O_adc_ch6_irq_en 0x0000003C // Channel 6 interrupt enable - // register -#define ADC_O_adc_ch7_irq_en 0x00000040 // Channel 7 interrupt enable - // register -#define ADC_O_adc_ch0_irq_status \ - 0x00000044 // Channel 0 interrupt status - // register - -#define ADC_O_adc_ch1_irq_status \ - 0x00000048 // Channel 1 interrupt status - // register - -#define ADC_O_adc_ch2_irq_status \ - 0x0000004C - -#define ADC_O_adc_ch3_irq_status \ - 0x00000050 // Channel 3 interrupt status - // register - -#define ADC_O_adc_ch4_irq_status \ - 0x00000054 // Channel 4 interrupt status - // register - -#define ADC_O_adc_ch5_irq_status \ - 0x00000058 - -#define ADC_O_adc_ch6_irq_status \ - 0x0000005C // Channel 6 interrupt status - // register - -#define ADC_O_adc_ch7_irq_status \ - 0x00000060 // Channel 7 interrupt status - // register - -#define ADC_O_adc_dma_mode_en 0x00000064 // DMA mode enable register -#define ADC_O_adc_timer_configuration \ - 0x00000068 // ADC timer configuration register - -#define ADC_O_adc_timer_current_count \ - 0x00000070 // ADC timer current count register - -#define ADC_O_channel0FIFODATA 0x00000074 // CH0 FIFO DATA register -#define ADC_O_channel1FIFODATA 0x00000078 // CH1 FIFO DATA register -#define ADC_O_channel2FIFODATA 0x0000007C // CH2 FIFO DATA register -#define ADC_O_channel3FIFODATA 0x00000080 // CH3 FIFO DATA register -#define ADC_O_channel4FIFODATA 0x00000084 // CH4 FIFO DATA register -#define ADC_O_channel5FIFODATA 0x00000088 // CH5 FIFO DATA register -#define ADC_O_channel6FIFODATA 0x0000008C // CH6 FIFO DATA register -#define ADC_O_channel7FIFODATA 0x00000090 // CH7 FIFO DATA register -#define ADC_O_adc_ch0_fifo_lvl 0x00000094 // channel 0 FIFO Level register -#define ADC_O_adc_ch1_fifo_lvl 0x00000098 // Channel 1 interrupt status - // register -#define ADC_O_adc_ch2_fifo_lvl 0x0000009C -#define ADC_O_adc_ch3_fifo_lvl 0x000000A0 // Channel 3 interrupt status - // register -#define ADC_O_adc_ch4_fifo_lvl 0x000000A4 // Channel 4 interrupt status - // register -#define ADC_O_adc_ch5_fifo_lvl 0x000000A8 -#define ADC_O_adc_ch6_fifo_lvl 0x000000AC // Channel 6 interrupt status - // register -#define ADC_O_adc_ch7_fifo_lvl 0x000000B0 // Channel 7 interrupt status - // register - -#define ADC_O_ADC_CH_ENABLE 0x000000B8 - -//****************************************************************************** -// -// The following are defines for the bit fields in the ADC_O_ADC_CTRL register. -// -//****************************************************************************** -#define ADC_ADC_CTRL_adc_cap_scale \ - 0x00000020 // ADC CAP SCALE. - -#define ADC_ADC_CTRL_adc_buf_bypass \ - 0x00000010 // ADC ANA CIO buffer bypass. - // Signal is modelled in ANA TOP. - // When '1': ADC buffer is bypassed. - -#define ADC_ADC_CTRL_adc_buf_en 0x00000008 // ADC ANA buffer enable. When 1: - // ADC buffer is enabled. -#define ADC_ADC_CTRL_adc_core_en \ - 0x00000004 // ANA ADC core en. This signal act - // as glbal enable to ADC CIO. When - // 1: ADC core is enabled. - -#define ADC_ADC_CTRL_adc_soft_reset \ - 0x00000002 // ADC soft reset. When '1' : reset - // ADC internal logic. - -#define ADC_ADC_CTRL_adc_en 0x00000001 // ADC global enable. When set ADC - // module is enabled -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch0_gain register. -// -//****************************************************************************** -#define ADC_adc_ch0_gain_adc_channel0_gain_M \ - 0x00000003 // gain setting for ADC channel 0. - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch0_gain_adc_channel0_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch1_gain register. -// -//****************************************************************************** -#define ADC_adc_ch1_gain_adc_channel1_gain_M \ - 0x00000003 // gain setting for ADC channel 1. - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch1_gain_adc_channel1_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch2_gain register. -// -//****************************************************************************** -#define ADC_adc_ch2_gain_adc_channel2_gain_M \ - 0x00000003 // gain setting for ADC channel 2. - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch2_gain_adc_channel2_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch3_gain register. -// -//****************************************************************************** -#define ADC_adc_ch3_gain_adc_channel3_gain_M \ - 0x00000003 // gain setting for ADC channel 3. - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch3_gain_adc_channel3_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch4_gain register. -// -//****************************************************************************** -#define ADC_adc_ch4_gain_adc_channel4_gain_M \ - 0x00000003 // gain setting for ADC channel 4 - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch4_gain_adc_channel4_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch5_gain register. -// -//****************************************************************************** -#define ADC_adc_ch5_gain_adc_channel5_gain_M \ - 0x00000003 // gain setting for ADC channel 5. - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch5_gain_adc_channel5_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch6_gain register. -// -//****************************************************************************** -#define ADC_adc_ch6_gain_adc_channel6_gain_M \ - 0x00000003 // gain setting for ADC channel 6 - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch6_gain_adc_channel6_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch7_gain register. -// -//****************************************************************************** -#define ADC_adc_ch7_gain_adc_channel7_gain_M \ - 0x00000003 // gain setting for ADC channel 7. - // when "00": 1x when "01: 2x when - // "10":3x when "11" 4x - -#define ADC_adc_ch7_gain_adc_channel7_gain_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch0_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch1_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch2_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch3_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch4_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch5_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch6_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch7_irq_en register. -// -//****************************************************************************** -#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \ - 0x0000000F // interrupt enable register for - // per ADC channel bit 3: when '1' - // -> enable FIFO overflow interrupt - // bit 2: when '1' -> enable FIFO - // underflow interrupt bit 1: when - // "1' -> enable FIFO empty - // interrupt bit 0: when "1" -> - // enable FIFO full interrupt - -#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch0_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch1_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch2_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch3_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch4_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch5_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch6_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch7_irq_status register. -// -//****************************************************************************** -#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \ - 0x0000000F // interrupt status register for - // per ADC channel. Interrupt status - // can be cleared on write. bit 3: - // when value '1' is written -> - // would clear FIFO overflow - // interrupt status in the next - // cycle. if same interrupt is set - // in the same cycle then interurpt - // would be set and clear command - // will be ignored. bit 2: when - // value '1' is written -> would - // clear FIFO underflow interrupt - // status in the next cycle. bit 1: - // when value '1' is written -> - // would clear FIFO empty interrupt - // status in the next cycle. bit 0: - // when value '1' is written -> - // would clear FIFO full interrupt - // status in the next cycle. - -#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_dma_mode_en register. -// -//****************************************************************************** -#define ADC_adc_dma_mode_en_DMA_MODEenable_M \ - 0x000000FF // this register enable DMA mode. - // when '1' respective ADC channel - // is enabled for DMA. When '0' only - // interrupt mode is enabled. Bit 0: - // channel 0 DMA mode enable. Bit 1: - // channel 1 DMA mode enable. Bit 2: - // channel 2 DMA mode enable. Bit 3: - // channel 3 DMA mode enable. bit 4: - // channel 4 DMA mode enable. bit 5: - // channel 5 DMA mode enable. bit 6: - // channel 6 DMA mode enable. bit 7: - // channel 7 DMA mode enable. - -#define ADC_adc_dma_mode_en_DMA_MODEenable_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_timer_configuration register. -// -//****************************************************************************** -#define ADC_adc_timer_configuration_timeren \ - 0x02000000 // when '1' timer is enabled. - -#define ADC_adc_timer_configuration_timerreset \ - 0x01000000 // when '1' reset timer. - -#define ADC_adc_timer_configuration_timercount_M \ - 0x00FFFFFF // Timer count configuration. 17 - // bit counter is supported. Other - // MSB's are redundent. - -#define ADC_adc_timer_configuration_timercount_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_timer_current_count register. -// -//****************************************************************************** -#define ADC_adc_timer_current_count_timercurrentcount_M \ - 0x0001FFFF // Timer count configuration - -#define ADC_adc_timer_current_count_timercurrentcount_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel0FIFODATA register. -// -//****************************************************************************** -#define ADC_channel0FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel1FIFODATA register. -// -//****************************************************************************** -#define ADC_channel1FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel2FIFODATA register. -// -//****************************************************************************** -#define ADC_channel2FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel3FIFODATA register. -// -//****************************************************************************** -#define ADC_channel3FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel4FIFODATA register. -// -//****************************************************************************** -#define ADC_channel4FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel5FIFODATA register. -// -//****************************************************************************** -#define ADC_channel5FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel6FIFODATA register. -// -//****************************************************************************** -#define ADC_channel6FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_channel7FIFODATA register. -// -//****************************************************************************** -#define ADC_channel7FIFODATA_FIFO_RD_DATA_M \ - 0xFFFFFFFF // read to this register would - // return ADC data along with time - // stamp information in following - // format: bits [13:0] : ADC sample - // bits [31:14]: : time stamp per - // ADC sample - -#define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch0_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch1_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch2_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch3_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch4_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch5_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch6_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// ADC_O_adc_ch7_fifo_lvl register. -// -//****************************************************************************** -#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \ - 0x00000007 // This register shows current FIFO - // level. FIFO is 4 word wide. - // Possible supported levels are : - // 0x0 to 0x3 - -#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0 - - - -#endif // __HW_ADC_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_aes.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_aes.h deleted file mode 100644 index 574f7576f83..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_aes.h +++ /dev/null @@ -1,800 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_AES_H__ -#define __HW_AES_H__ - -//***************************************************************************** -// -// The following are defines for the AES_P register offsets. -// -//***************************************************************************** -#define AES_O_KEY2_6 0x00000000 // XTS second key / CBC-MAC third - // key -#define AES_O_KEY2_7 0x00000004 // XTS second key (MSW for 256-bit - // key) / CBC-MAC third key (MSW) -#define AES_O_KEY2_4 0x00000008 // XTS / CCM second key / CBC-MAC - // third key (LSW) -#define AES_O_KEY2_5 0x0000000C // XTS second key (MSW for 192-bit - // key) / CBC-MAC third key -#define AES_O_KEY2_2 0x00000010 // XTS / CCM / CBC-MAC second key / - // Hash Key input -#define AES_O_KEY2_3 0x00000014 // XTS second key (MSW for 128-bit - // key) + CCM/CBC-MAC second key - // (MSW) / Hash Key input (MSW) -#define AES_O_KEY2_0 0x00000018 // XTS / CCM / CBC-MAC second key - // (LSW) / Hash Key input (LSW) -#define AES_O_KEY2_1 0x0000001C // XTS / CCM / CBC-MAC second key / - // Hash Key input -#define AES_O_KEY1_6 0x00000020 // Key (LSW for 256-bit key) -#define AES_O_KEY1_7 0x00000024 // Key (MSW for 256-bit key) -#define AES_O_KEY1_4 0x00000028 // Key (LSW for 192-bit key) -#define AES_O_KEY1_5 0x0000002C // Key (MSW for 192-bit key) -#define AES_O_KEY1_2 0x00000030 // Key -#define AES_O_KEY1_3 0x00000034 // Key (MSW for 128-bit key) -#define AES_O_KEY1_0 0x00000038 // Key (LSW for 128-bit key) -#define AES_O_KEY1_1 0x0000003C // Key -#define AES_O_IV_IN_0 0x00000040 // Initialization Vector input - // (LSW) -#define AES_O_IV_IN_1 0x00000044 // Initialization vector input -#define AES_O_IV_IN_2 0x00000048 // Initialization vector input -#define AES_O_IV_IN_3 0x0000004C // Initialization Vector input - // (MSW) -#define AES_O_CTRL 0x00000050 // register determines the mode of - // operation of the AES Engine -#define AES_O_C_LENGTH_0 0x00000054 // Crypto data length registers - // (LSW and MSW) store the - // cryptographic data length in - // bytes for all modes. Once - // processing with this context is - // started@@ this length decrements - // to zero. Data lengths up to (2^61 - // – 1) bytes are allowed. For GCM@@ - // any value up to 2^36 - 32 bytes - // can be used. This is because a - // 32-bit counter mode is used; the - // maximum number of 128-bit blocks - // is 2^32 – 2@@ resulting in a - // maximum number of bytes of 2^36 - - // 32. A write to this register - // triggers the engine to start - // using this context. This is valid - // for all modes except GCM and CCM. - // Note that for the combined - // modes@@ this length does not - // include the authentication only - // data; the authentication length - // is specified in the - // AES_AUTH_LENGTH register below. - // All modes must have a length > 0. - // For the combined modes@@ it is - // allowed to have one of the - // lengths equal to zero. For the - // basic encryption modes - // (ECB/CBC/CTR/ICM/CFB128) it is - // allowed to program zero to the - // length field; in that case the - // length is assumed infinite. All - // data must be byte (8-bit) - // aligned; bit aligned data streams - // are not supported by the AES - // Engine. For a Host read - // operation@@ these registers - // return all-zeroes. -#define AES_O_C_LENGTH_1 0x00000058 // Crypto data length registers - // (LSW and MSW) store the - // cryptographic data length in - // bytes for all modes. Once - // processing with this context is - // started@@ this length decrements - // to zero. Data lengths up to (2^61 - // – 1) bytes are allowed. For GCM@@ - // any value up to 2^36 - 32 bytes - // can be used. This is because a - // 32-bit counter mode is used; the - // maximum number of 128-bit blocks - // is 2^32 – 2@@ resulting in a - // maximum number of bytes of 2^36 - - // 32. A write to this register - // triggers the engine to start - // using this context. This is valid - // for all modes except GCM and CCM. - // Note that for the combined - // modes@@ this length does not - // include the authentication only - // data; the authentication length - // is specified in the - // AES_AUTH_LENGTH register below. - // All modes must have a length > 0. - // For the combined modes@@ it is - // allowed to have one of the - // lengths equal to zero. For the - // basic encryption modes - // (ECB/CBC/CTR/ICM/CFB128) it is - // allowed to program zero to the - // length field; in that case the - // length is assumed infinite. All - // data must be byte (8-bit) - // aligned; bit aligned data streams - // are not supported by the AES - // Engine. For a Host read - // operation@@ these registers - // return all-zeroes. -#define AES_O_AUTH_LENGTH 0x0000005C // AAD data length. The - // authentication length register - // store the authentication data - // length in bytes for combined - // modes only (GCM or CCM) Supported - // AAD-lengths for CCM are from 0 to - // (2^16 - 2^8) bytes. For GCM any - // value up to (2^32 - 1) bytes can - // be used. Once processing with - // this context is started@@ this - // length decrements to zero. A - // write to this register triggers - // the engine to start using this - // context for GCM and CCM. For XTS - // this register is optionally used - // to load ‘j’. Loading of ‘j’ is - // only required if ‘j’ != 0. ‘j’ is - // a 28-bit value and must be - // written to bits [31-4] of this - // register. ‘j’ represents the - // sequential number of the 128-bit - // block inside the data unit. For - // the first block in a unit@@ this - // value is zero. It is not required - // to provide a ‘j’ for each new - // data block within a unit. Note - // that it is possible to start with - // a ‘j’ unequal to zero; refer to - // Table 4 for more details. For a - // Host read operation@@ these - // registers return all-zeroes. -#define AES_O_DATA_IN_0 0x00000060 // Data register to read and write - // plaintext/ciphertext (MSW) -#define AES_O_DATA_IN_1 0x00000064 // Data register to read and write - // plaintext/ciphertext -#define AES_O_DATA_IN_2 0x00000068 // Data register to read and write - // plaintext/ciphertext -#define AES_O_DATA_IN_3 0x0000006C // Data register to read and write - // plaintext/ciphertext (LSW) -#define AES_O_TAG_OUT_0 0x00000070 -#define AES_O_TAG_OUT_1 0x00000074 -#define AES_O_TAG_OUT_2 0x00000078 -#define AES_O_TAG_OUT_3 0x0000007C -#define AES_O_REVISION 0x00000080 // Register AES_REVISION -#define AES_O_SYSCONFIG 0x00000084 // Register AES_SYSCONFIG.This - // register configures the DMA - // signals and controls the IDLE and - // reset logic -#define AES_O_SYSSTATUS 0x00000088 -#define AES_O_IRQSTATUS 0x0000008C // This register indicates the - // interrupt status. If one of the - // interrupt bits is set the - // interrupt output will be asserted -#define AES_O_IRQENABLE 0x00000090 // This register contains an enable - // bit for each unique interrupt - // generated by the module. It - // matches the layout of - // AES_IRQSTATUS register. An - // interrupt is enabled when the bit - // in this register is set to ‘1’. - // An interrupt that is enabled is - // propagated to the SINTREQUEST_x - // output. All interrupts need to be - // enabled explicitly by writing - // this register. - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_6 register. -// -//****************************************************************************** -#define AES_KEY2_6_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_6_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_7 register. -// -//****************************************************************************** -#define AES_KEY2_7_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_7_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_4 register. -// -//****************************************************************************** -#define AES_KEY2_4_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_4_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_5 register. -// -//****************************************************************************** -#define AES_KEY2_5_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_5_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_2 register. -// -//****************************************************************************** -#define AES_KEY2_2_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_2_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_3 register. -// -//****************************************************************************** -#define AES_KEY2_3_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_3_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_0 register. -// -//****************************************************************************** -#define AES_KEY2_0_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_0_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY2_1 register. -// -//****************************************************************************** -#define AES_KEY2_1_KEY_M 0xFFFFFFFF // key data -#define AES_KEY2_1_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_6 register. -// -//****************************************************************************** -#define AES_KEY1_6_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_6_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_7 register. -// -//****************************************************************************** -#define AES_KEY1_7_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_7_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_4 register. -// -//****************************************************************************** -#define AES_KEY1_4_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_4_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_5 register. -// -//****************************************************************************** -#define AES_KEY1_5_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_5_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_2 register. -// -//****************************************************************************** -#define AES_KEY1_2_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_2_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_3 register. -// -//****************************************************************************** -#define AES_KEY1_3_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_3_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_0 register. -// -//****************************************************************************** -#define AES_KEY1_0_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_0_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_KEY1_1 register. -// -//****************************************************************************** -#define AES_KEY1_1_KEY_M 0xFFFFFFFF // key data -#define AES_KEY1_1_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_0 register. -// -//****************************************************************************** -#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // IV data -#define AES_IV_IN_0_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_1 register. -// -//****************************************************************************** -#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // IV data -#define AES_IV_IN_1_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_2 register. -// -//****************************************************************************** -#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // IV data -#define AES_IV_IN_2_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IV_IN_3 register. -// -//****************************************************************************** -#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // IV data -#define AES_IV_IN_3_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_CTRL register. -// -//****************************************************************************** -#define AES_CTRL_CONTEXT_READY \ - 0x80000000 // If ‘1’@@ this read-only status - // bit indicates that the context - // data registers can be overwritten - // and the host is permitted to - // write the next context. - -#define AES_CTRL_SVCTXTRDY \ - 0x40000000 // If ‘1’@@ this read-only status - // bit indicates that an AES - // authentication TAG and/or IV - // block(s) is/are available for the - // host to retrieve. This bit is - // only asserted if the - // ‘save_context’ bit is set to ‘1’. - // The bit is mutual exclusive with - // the ‘context_ready’ bit. - -#define AES_CTRL_SAVE_CONTEXT 0x20000000 // This bit is used to indicate - // that an authentication TAG or - // result IV needs to be stored as a - // result context. If this bit is - // set@@ context output DMA and/or - // interrupt will be asserted if the - // operation is finished and related - // signals are enabled. -#define AES_CTRL_CCM_M 0x01C00000 // Defines “M� that indicated the - // length of the authentication - // field for CCM operations; the - // authentication field length - // equals two times (the value of - // CCM-M plus one). Note that the - // AES Engine always returns a - // 128-bit authentication field@@ of - // which the M least significant - // bytes are valid. All values are - // supported. -#define AES_CTRL_CCM_S 22 -#define AES_CTRL_CCM_L_M 0x00380000 // Defines “L� that indicated the - // width of the length field for CCM - // operations; the length field in - // bytes equals the value of CMM-L - // plus one. Supported values for L - // are (programmed value): 2 (1)@@ 4 - // (3) and 8 (7). -#define AES_CTRL_CCM_L_S 19 -#define AES_CTRL_CCM 0x00040000 // AES-CCM is selected@@ this is a - // combined mode@@ using AES for - // both authentication and - // encryption. No additional mode - // selection is required. 0 Other - // mode selected 1 ccm mode selected -#define AES_CTRL_GCM_M 0x00030000 // AES-GCM mode is selected.this is - // a combined mode@@ using the - // Galois field multiplier GF(2^128) - // for authentication and AES-CTR - // mode for encryption@@ the bits - // specify the GCM mode. 0x0 No - // operation 0x1 GHASH with H loaded - // and Y0-encrypted forced to zero - // 0x2 GHASH with H loaded and - // Y0-encrypted calculated - // internally 0x3 Autonomous GHASH - // (both H and Y0-encrypted - // calculated internally) -#define AES_CTRL_GCM_S 16 -#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC is selected@@ the - // Direction bit must be set to ‘1’ - // for this mode. 0 Other mode - // selected 1 cbcmac mode selected -#define AES_CTRL_F9 0x00004000 // AES f9 mode is selected@@ the - // AES key size must be set to - // 128-bit for this mode. 0 Other - // mode selected 1 f9 selected -#define AES_CTRL_F8 0x00002000 // AES f8 mode is selected@@ the - // AES key size must be set to - // 128-bit for this mode. 0 Other - // mode selected 1 f8 selected -#define AES_CTRL_XTS_M 0x00001800 // AES-XTS operation is selected; - // the bits specify the XTS mode.01 - // = Previous/intermediate tweak - // value and ‘j’ loaded (value is - // loaded via IV@@ j is loaded via - // the AAD length register) 0x0 No - // operation 0x1 - // Previous/intermediate tweak value - // and ‘j’ loaded (value is loaded - // via IV@@ j is loaded via the AAD - // length register) 0x2 Key2@@ i and - // j loaded (i is loaded via IV@@ j - // is loaded via the AAD length - // register) 0x3 Key2 and i loaded@@ - // j=0 (i is loaded via IV) -#define AES_CTRL_XTS_S 11 -#define AES_CTRL_CFB 0x00000400 // full block AES cipher feedback - // mode (CFB128) is selected. 0 - // other mode selected 1 cfb - // selected -#define AES_CTRL_ICM 0x00000200 // AES integer counter mode (ICM) - // is selected@@ this is a counter - // mode with a 16-bit wide counter. - // 0 Other mode selected. 1 ICM mode - // selected -#define AES_CTRL_CTR_WIDTH_M 0x00000180 // Specifies the counter width for - // AES-CTR mode 0x0 Counter is 32 - // bits 0x1 Counter is 64 bits 0x2 - // Counter is 128 bits 0x3 Counter - // is 192 bits -#define AES_CTRL_CTR_WIDTH_S 7 -#define AES_CTRL_CTR 0x00000040 // Tthis bit must also be set for - // GCM and CCM@@ when - // encryption/decryption is - // required. 0 Other mode selected 1 - // Counter mode -#define AES_CTRL_MODE 0x00000020 // ecb/cbc mode 0 ecb mode 1 cbc - // mode -#define AES_CTRL_KEY_SIZE_M 0x00000018 // key size 0x0 reserved 0x1 Key is - // 128 bits. 0x2 Key is 192 bits 0x3 - // Key is 256 -#define AES_CTRL_KEY_SIZE_S 3 -#define AES_CTRL_DIRECTION 0x00000004 // If set to ‘1’ an encrypt - // operation is performed. If set to - // ‘0’ a decrypt operation is - // performed. Read 0 decryption is - // selected Read 1 Encryption is - // selected -#define AES_CTRL_INPUT_READY 0x00000002 // If ‘1’@@ this read-only status - // bit indicates that the 16-byte - // input buffer is empty@@ and the - // host is permitted to write the - // next block of data. -#define AES_CTRL_OUTPUT_READY 0x00000001 // If ‘1’@@ this read-only status - // bit indicates that an AES output - // block is available for the host - // to retrieve. -//****************************************************************************** -// -// The following are defines for the bit fields in the -// AES_O_C_LENGTH_0 register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the -// AES_O_C_LENGTH_1 register. -// -//****************************************************************************** -#define AES_C_LENGTH_1_LENGTH_M \ - 0x1FFFFFFF // Data length (MSW) length - // registers (LSW and MSW) store the - // cryptographic data length in - // bytes for all modes. Once - // processing with this context is - // started@@ this length decrements - // to zero. Data lengths up to (2^61 - // – 1) bytes are allowed. For GCM@@ - // any value up to 2^36 - 32 bytes - // can be used. This is because a - // 32-bit counter mode is used; the - // maximum number of 128-bit blocks - // is 2^32 – 2@@ resulting in a - // maximum number of bytes of 2^36 - - // 32. A write to this register - // triggers the engine to start - // using this context. This is valid - // for all modes except GCM and CCM. - // Note that for the combined - // modes@@ this length does not - // include the authentication only - // data; the authentication length - // is specified in the - // AES_AUTH_LENGTH register below. - // All modes must have a length > 0. - // For the combined modes@@ it is - // allowed to have one of the - // lengths equal to zero. For the - // basic encryption modes - // (ECB/CBC/CTR/ICM/CFB128) it is - // allowed to program zero to the - // length field; in that case the - // length is assumed infinite. All - // data must be byte (8-bit) - // aligned; bit aligned data streams - // are not supported by the AES - // Engine. For a Host read - // operation@@ these registers - // return all-zeroes. - -#define AES_C_LENGTH_1_LENGTH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// AES_O_AUTH_LENGTH register. -// -//****************************************************************************** -#define AES_AUTH_LENGTH_AUTH_M \ - 0xFFFFFFFF // data - -#define AES_AUTH_LENGTH_AUTH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_0 register. -// -//****************************************************************************** -#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt -#define AES_DATA_IN_0_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_1 register. -// -//****************************************************************************** -#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt -#define AES_DATA_IN_1_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_2 register. -// -//****************************************************************************** -#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt -#define AES_DATA_IN_2_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_DATA_IN_3 register. -// -//****************************************************************************** -#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt -#define AES_DATA_IN_3_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_0 register. -// -//****************************************************************************** -#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash result (MSW) -#define AES_TAG_OUT_0_HASH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_1 register. -// -//****************************************************************************** -#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash result (MSW) -#define AES_TAG_OUT_1_HASH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_2 register. -// -//****************************************************************************** -#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash result (MSW) -#define AES_TAG_OUT_2_HASH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_TAG_OUT_3 register. -// -//****************************************************************************** -#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash result (LSW) -#define AES_TAG_OUT_3_HASH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_REVISION register. -// -//****************************************************************************** -#define AES_REVISION_SCHEME_M 0xC0000000 -#define AES_REVISION_SCHEME_S 30 -#define AES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software - // compatible module family. If - // there is no level of software - // compatibility a new Func number - // (and hence REVISION) should be - // assigned. -#define AES_REVISION_FUNC_S 16 -#define AES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R)@@ maintained by - // IP design owner. RTL follows a - // numbering such as X.Y.R.Z which - // are explained in this table. R - // changes ONLY when: (1) PDS - // uploads occur which may have been - // due to spec changes (2) Bug fixes - // occur (3) Resets to '0' when X or - // Y changes. Design team has an - // internal 'Z' (customer invisible) - // number which increments on every - // drop that happens due to DV and - // RTL updates. Z resets to 0 when R - // increments. -#define AES_REVISION_R_RTL_S 11 -#define AES_REVISION_X_MAJOR_M \ - 0x00000700 // Major Revision (X)@@ maintained - // by IP specification owner. X - // changes ONLY when: (1) There is a - // major feature addition. An - // example would be adding Master - // Mode to Utopia Level2. The Func - // field (or Class/Type in old PID - // format) will remain the same. X - // does NOT change due to: (1) Bug - // fixes (2) Change in feature - // parameters. - -#define AES_REVISION_X_MAJOR_S 8 -#define AES_REVISION_CUSTOM_M 0x000000C0 -#define AES_REVISION_CUSTOM_S 6 -#define AES_REVISION_Y_MINOR_M \ - 0x0000003F // Minor Revision (Y)@@ maintained - // by IP specification owner. Y - // changes ONLY when: (1) Features - // are scaled (up or down). - // Flexibility exists in that this - // feature scalability may either be - // represented in the Y change or a - // specific register in the IP that - // indicates which features are - // exactly available. (2) When - // feature creeps from Is-Not list - // to Is list. But this may not be - // the case once it sees silicon; in - // which case X will change. Y does - // NOT change due to: (1) Bug fixes - // (2) Typos or clarifications (3) - // major functional/feature - // change/addition/deletion. Instead - // these changes may be reflected - // via R@@ S@@ X as applicable. Spec - // owner maintains a - // customer-invisible number 'S' - // which changes due to: (1) - // Typos/clarifications (2) Bug - // documentation. Note that this bug - // is not due to a spec change but - // due to implementation. - // Nevertheless@@ the spec tracks - // the IP bugs. An RTL release (say - // for silicon PG1.1) that occurs - // due to bug fix should document - // the corresponding spec number - // (X.Y.S) in its release notes. - -#define AES_REVISION_Y_MINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_SYSCONFIG register. -// -//****************************************************************************** -#define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \ - 0x00000200 // If set to '1' the two context - // out requests - // (dma_req_context_out_en@@ Bit [8] - // above@@ and context_out interrupt - // enable@@ Bit [3] of AES_IRQENABLE - // register) are mapped on the - // corresponding data output request - // bit. In this case@@ the original - // ‘context out’ bit values are - // ignored. - -#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ - 0x00000100 // If set to ‘1’@@ the DMA context - // output request is enabled (for - // context data out@@ e.g. TAG for - // authentication modes). 0 Dma - // disabled 1 Dma enabled - -#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ - 0x00000080 // If set to ‘1’@@ the DMA context - // request is enabled. 0 Dma - // disabled 1 Dma enabled - -#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ - 0x00000040 // If set to ‘1’@@ the DMA output - // request is enabled. 0 Dma - // disabled 1 Dma enabled - -#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ - 0x00000020 // If set to ‘1’@@ the DMA input - // request is enabled. 0 Dma - // disabled 1 Dma enabled - -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_SYSSTATUS register. -// -//****************************************************************************** -#define AES_SYSSTATUS_RESETDONE \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IRQSTATUS register. -// -//****************************************************************************** -#define AES_IRQSTATUS_CONTEXT_OUT \ - 0x00000008 // This bit indicates - // authentication tag (and IV) - // interrupt(s) is/are active and - // triggers the interrupt output. - -#define AES_IRQSTATUS_DATA_OUT \ - 0x00000004 // This bit indicates data output - // interrupt is active and triggers - // the interrupt output. - -#define AES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input - // interrupt is active and triggers - // the interrupt output. -#define AES_IRQSTATUS_CONTEX_IN \ - 0x00000001 // This bit indicates context - // interrupt is active and triggers - // the interrupt output. - -//****************************************************************************** -// -// The following are defines for the bit fields in the AES_O_IRQENABLE register. -// -//****************************************************************************** -#define AES_IRQENABLE_CONTEXT_OUT \ - 0x00000008 // This bit indicates - // authentication tag (and IV) - // interrupt(s) is/are active and - // triggers the interrupt output. - -#define AES_IRQENABLE_DATA_OUT \ - 0x00000004 // This bit indicates data output - // interrupt is active and triggers - // the interrupt output. - -#define AES_IRQENABLE_DATA_IN 0x00000002 // This bit indicates data input - // interrupt is active and triggers - // the interrupt output. -#define AES_IRQENABLE_CONTEX_IN \ - 0x00000001 // This bit indicates context - // interrupt is active and triggers - // the interrupt output. - - - - -#endif // __HW_AES_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_apps_config.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_apps_config.h deleted file mode 100644 index e5f26928ab5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_apps_config.h +++ /dev/null @@ -1,745 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#ifndef __HW_APPS_CONFIG_H__ -#define __HW_APPS_CONFIG_H__ - -//***************************************************************************** -// -// The following are defines for the APPS_CONFIG register offsets. -// -//***************************************************************************** -#define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \ - 0x00000000 // Patch trap address Register - // array - -#define APPS_CONFIG_O_PATCH_TRAP_EN_REG \ - 0x00000078 - -#define APPS_CONFIG_O_FAULT_STATUS_REG \ - 0x0000007C - -#define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \ - 0x00000080 - -#define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \ - 0x00000084 - -#define APPS_CONFIG_O_DMA_DONE_INT_MASK \ - 0x0000008C - -#define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \ - 0x00000090 - -#define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \ - 0x00000094 - -#define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \ - 0x00000098 - -#define APPS_CONFIG_O_DMA_DONE_INT_ACK \ - 0x0000009C - -#define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \ - 0x000000A0 - -#define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \ - 0x000000A4 - -#define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \ - 0x000000A8 - -#define APPS_CONFIG_O_RESERVD_REG_0 \ - 0x000000AC - -#define APPS_CONFIG_O_GPT_TRIG_SEL \ - 0x000000B0 - -#define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \ - 0x000000B4 - -#define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \ - 0x000000B8 - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \ - 0xFFFFFFFF // When PATCH_TRAP_EN[n] is set bus - // fault is generated for the - // address - // PATCH_TRAP_ADDR_REG[n][31:0] from - // Idcode bus. The exception routine - // should take care to jump to the - // location where the patch - // correspond to this address is - // kept. - -#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_PATCH_TRAP_EN_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \ - 0x3FFFFFFF // When PATCH_TRAP_EN[n] is set bus - // fault is generated for the - // address PATCH_TRAP_ADD[n][31:0] - // from Idcode bus. The exception - // routine should take care to jump - // to the location where the patch - // correspond to this address is - // kept. - -#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_FAULT_STATUS_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \ - 0x0000003E // This field shows because of - // which patch trap address the - // bus_fault is generated. If the - // PATCH_ERR bit is set, then it - // means the bus fault is generated - // because of - // PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX] - -#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1 -#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \ - 0x00000001 // This bit is set when there is a - // bus fault because of patched - // address access to the Apps boot - // rom. Write 0 to clear this - // register. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \ - 0x00000001 // This bit is set when there is a - // an error in memss write access. - // And the address causing this - // error is captured in - // MEMSS_ERR_ADDR_REG. To capture - // the next error address one have - // to clear this bit. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_MASK register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \ - 0x0000F000 // 1= disable corresponding - // interrupt;0 = interrupt enabled - // bit 14: ADC channel 7 interrupt - // enable/disable bit 13: ADC - // channel 5 interrupt - // enable/disable bit 12: ADC - // channel 3 interrupt - // enable/disable bit 11: ADC - // channel 1 interrupt - // enable/disable - -#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12 -#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \ - 0x00000800 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \ - 0x00000400 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \ - 0x00000200 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \ - 0x00000100 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \ - 0x00000080 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \ - 0x00000040 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \ - 0x00000020 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \ - 0x00000010 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \ - 0x00000008 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \ - 0x00000004 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \ - 0x00000002 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \ - 0x00000001 // 1= disable corresponding - // interrupt;0 = interrupt enabled - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \ - 0x0000F000 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect bit 14: ADC channel 7 DMA - // Done IRQ bit 13: ADC channel 5 - // DMA Done IRQ bit 12: ADC channel - // 3 DMA Done IRQ bit 11: ADC - // channel 1 DMA Done IRQ - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12 -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \ - 0x00000800 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \ - 0x00000400 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \ - 0x00000200 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \ - 0x00000100 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \ - 0x00000080 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \ - 0x00000040 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \ - 0x00000020 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \ - 0x00000010 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \ - 0x00000008 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \ - 0x00000004 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \ - 0x00000002 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \ - 0x00000001 // write 1 to set mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \ - 0x0000F000 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect bit 14: ADC channel 7 DMA - // Done IRQ mask bit 13: ADC channel - // 5 DMA Done IRQ mask bit 12: ADC - // channel 3 DMA Done IRQ mask bit - // 11: ADC channel 1 DMA Done IRQ - // mask - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12 -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \ - 0x00000800 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \ - 0x00000400 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \ - 0x00000200 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \ - 0x00000100 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \ - 0x00000080 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \ - 0x00000040 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \ - 0x00000020 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \ - 0x00000010 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \ - 0x00000008 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \ - 0x00000004 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \ - 0x00000002 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \ - 0x00000001 // write 1 to clear mask of the - // corresponding DMA DONE IRQ;0 = no - // effect - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \ - 0xFFFFFFFF // write 1 or 0 to clear all - // DMA_DONE interrupt; - -#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_ACK register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \ - 0x0000F000 // write 1 to clear corresponding - // interrupt; 0 = no effect; bit 14: - // ADC channel 7 DMA Done IRQ bit - // 13: ADC channel 5 DMA Done IRQ - // bit 12: ADC channel 3 DMA Done - // IRQ bit 11: ADC channel 1 DMA - // Done IRQ - -#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12 -#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \ - 0x00000800 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \ - 0x00000400 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \ - 0x00000200 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \ - 0x00000100 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \ - 0x00000080 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \ - 0x00000040 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \ - 0x00000020 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \ - 0x00000010 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \ - 0x00000008 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \ - 0x00000004 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \ - 0x00000002 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \ - 0x00000001 // write 1 to clear corresponding - // interrupt; 0 = no effect; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \ - 0x0000F000 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask bit 14: ADC - // channel 7 DMA Done IRQ bit 13: - // ADC channel 5 DMA Done IRQ bit - // 12: ADC channel 3 DMA Done IRQ - // bit 11: ADC channel 1 DMA Done - // IRQ - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12 -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \ - 0x00000800 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \ - 0x00000400 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \ - 0x00000200 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \ - 0x00000100 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \ - 0x00000080 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \ - 0x00000040 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \ - 0x00000020 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \ - 0x00000010 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \ - 0x00000008 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \ - 0x00000004 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \ - 0x00000002 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \ - 0x00000001 // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by DMA_DONE_INT mask - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register. -// -//****************************************************************************** -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \ - 0x0000F000 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive bit 14: ADC channel 7 - // DMA Done IRQ bit 13: ADC channel - // 5 DMA Done IRQ bit 12: ADC - // channel 3 DMA Done IRQ bit 11: - // ADC channel 1 DMA Done IRQ - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12 -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \ - 0x00000800 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \ - 0x00000400 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \ - 0x00000200 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \ - 0x00000100 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \ - 0x00000080 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \ - 0x00000040 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \ - 0x00000020 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \ - 0x00000010 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \ - 0x00000008 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \ - 0x00000004 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \ - 0x00000002 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \ - 0x00000001 // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_FAULT_STATUS_CLR_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \ - 0x00000001 // Write 1 to clear the LSB of - // FAULT_STATUS_REG - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_RESERVD_REG_0 register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_GPT_TRIG_SEL register. -// -//****************************************************************************** -#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \ - 0x000000FF // This bit is implemented for GPT - // trigger mode select. GPT IP - // support 2 modes: RTC mode and - // external trigger. When this bit - // is set to logic '1': enable - // external trigger mode for APPS - // GPT CP0 and CP1 pin. bit 0: when - // set '1' enable external GPT - // trigger 0 on GPIO0 CP0 pin else - // RTC mode is selected. bit 1: when - // set '1' enable external GPT - // trigger 1 on GPIO0 CP1 pin else - // RTC mode is selected. bit 2: when - // set '1' enable external GPT - // trigger 2 on GPIO1 CP0 pin else - // RTC mode is selected. bit 3: when - // set '1' enable external GPT - // trigger 3 on GPIO1 CP1 pin else - // RTC mode is selected. bit 4: when - // set '1' enable external GPT - // trigger 4 on GPIO2 CP0 pin else - // RTC mode is selected. bit 5: when - // set '1' enable external GPT - // trigger 5 on GPIO2 CP1 pin else - // RTC mode is selected. bit 6: when - // set '1' enable external GPT - // trigger 6 on GPIO3 CP0 pin else - // RTC mode is selected. bit 7: when - // set '1' enable external GPT - // trigger 7 on GPIO3 CP1 pin else - // RTC mode is selected. - -#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \ - 0x00000007 // Capture data from d2d_spare pads - -#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register. -// -//****************************************************************************** -#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \ - 0x00000007 // Send data to d2d_spare pads - - // eventually this will get - // registered in top die - -#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0 - - - -#endif // __HW_APPS_CONFIG_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_apps_rcm.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_apps_rcm.h deleted file mode 100644 index 997bccd8c2b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_apps_rcm.h +++ /dev/null @@ -1,1504 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_APPS_RCM_H__ -#define __HW_APPS_RCM_H__ - -//***************************************************************************** -// -// The following are defines for the APPS_RCM register offsets. -// -//***************************************************************************** -#define APPS_RCM_O_CAMERA_CLK_GEN \ - 0x00000000 - -#define APPS_RCM_O_CAMERA_CLK_GATING \ - 0x00000004 - -#define APPS_RCM_O_CAMERA_SOFT_RESET \ - 0x00000008 - -#define APPS_RCM_O_MCASP_CLK_GATING \ - 0x00000014 - -#define APPS_RCM_O_MCASP_SOFT_RESET \ - 0x00000018 - -#define APPS_RCM_O_MMCHS_CLK_GEN \ - 0x00000020 - -#define APPS_RCM_O_MMCHS_CLK_GATING \ - 0x00000024 - -#define APPS_RCM_O_MMCHS_SOFT_RESET \ - 0x00000028 - -#define APPS_RCM_O_MCSPI_A1_CLK_GEN \ - 0x0000002C - -#define APPS_RCM_O_MCSPI_A1_CLK_GATING \ - 0x00000030 - -#define APPS_RCM_O_MCSPI_A1_SOFT_RESET \ - 0x00000034 - -#define APPS_RCM_O_MCSPI_A2_CLK_GEN \ - 0x00000038 - -#define APPS_RCM_O_MCSPI_A2_CLK_GATING \ - 0x00000040 - -#define APPS_RCM_O_MCSPI_A2_SOFT_RESET \ - 0x00000044 - -#define APPS_RCM_O_UDMA_A_CLK_GATING \ - 0x00000048 - -#define APPS_RCM_O_UDMA_A_SOFT_RESET \ - 0x0000004C - -#define APPS_RCM_O_GPIO_A_CLK_GATING \ - 0x00000050 - -#define APPS_RCM_O_GPIO_A_SOFT_RESET \ - 0x00000054 - -#define APPS_RCM_O_GPIO_B_CLK_GATING \ - 0x00000058 - -#define APPS_RCM_O_GPIO_B_SOFT_RESET \ - 0x0000005C - -#define APPS_RCM_O_GPIO_C_CLK_GATING \ - 0x00000060 - -#define APPS_RCM_O_GPIO_C_SOFT_RESET \ - 0x00000064 - -#define APPS_RCM_O_GPIO_D_CLK_GATING \ - 0x00000068 - -#define APPS_RCM_O_GPIO_D_SOFT_RESET \ - 0x0000006C - -#define APPS_RCM_O_GPIO_E_CLK_GATING \ - 0x00000070 - -#define APPS_RCM_O_GPIO_E_SOFT_RESET \ - 0x00000074 - -#define APPS_RCM_O_WDOG_A_CLK_GATING \ - 0x00000078 - -#define APPS_RCM_O_WDOG_A_SOFT_RESET \ - 0x0000007C - -#define APPS_RCM_O_UART_A0_CLK_GATING \ - 0x00000080 - -#define APPS_RCM_O_UART_A0_SOFT_RESET \ - 0x00000084 - -#define APPS_RCM_O_UART_A1_CLK_GATING \ - 0x00000088 - -#define APPS_RCM_O_UART_A1_SOFT_RESET \ - 0x0000008C - -#define APPS_RCM_O_GPT_A0_CLK_GATING \ - 0x00000090 - -#define APPS_RCM_O_GPT_A0_SOFT_RESET \ - 0x00000094 - -#define APPS_RCM_O_GPT_A1_CLK_GATING \ - 0x00000098 - -#define APPS_RCM_O_GPT_A1_SOFT_RESET \ - 0x0000009C - -#define APPS_RCM_O_GPT_A2_CLK_GATING \ - 0x000000A0 - -#define APPS_RCM_O_GPT_A2_SOFT_RESET \ - 0x000000A4 - -#define APPS_RCM_O_GPT_A3_CLK_GATING \ - 0x000000A8 - -#define APPS_RCM_O_GPT_A3_SOFT_RESET \ - 0x000000AC - -#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 \ - 0x000000B0 - -#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 \ - 0x000000B4 - -#define APPS_RCM_O_CRYPTO_CLK_GATING \ - 0x000000B8 - -#define APPS_RCM_O_CRYPTO_SOFT_RESET \ - 0x000000BC - -#define APPS_RCM_O_MCSPI_S0_CLK_GATING \ - 0x000000C8 - -#define APPS_RCM_O_MCSPI_S0_SOFT_RESET \ - 0x000000CC - -#define APPS_RCM_O_MCSPI_S0_CLKDIV_CFG \ - 0x000000D0 - -#define APPS_RCM_O_I2C_CLK_GATING \ - 0x000000D8 - -#define APPS_RCM_O_I2C_SOFT_RESET \ - 0x000000DC - -#define APPS_RCM_O_APPS_LPDS_REQ \ - 0x000000E4 - -#define APPS_RCM_O_APPS_TURBO_REQ \ - 0x000000EC - -#define APPS_RCM_O_APPS_DSLP_WAKE_CONFIG \ - 0x00000108 - -#define APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG \ - 0x0000010C - -#define APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE \ - 0x00000110 - -#define APPS_RCM_O_APPS_SLP_WAKETIMER_CFG \ - 0x00000114 - -#define APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST \ - 0x00000118 - -#define APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS \ - 0x00000120 - -#define APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE \ - 0x00000124 - - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_CAMERA_CLK_GEN register. -// -//****************************************************************************** -#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_M \ - 0x00000700 // Configuration of OFF-TIME for - // dividing PLL clk (240 MHz) in - // generation of Camera func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_S 8 -#define APPS_RCM_CAMERA_CLK_GEN_NU1_M \ - 0x000000F8 - -#define APPS_RCM_CAMERA_CLK_GEN_NU1_S 3 -#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_M \ - 0x00000007 // Configuration of ON-TIME for - // dividing PLL clk (240 MHz) in - // generation of Camera func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_CAMERA_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_CAMERA_CLK_GATING_NU1_M \ - 0x00FE0000 - -#define APPS_RCM_CAMERA_CLK_GATING_NU1_S 17 -#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable camera clk during - // deep-sleep mode - -#define APPS_RCM_CAMERA_CLK_GATING_NU2_M \ - 0x0000FE00 - -#define APPS_RCM_CAMERA_CLK_GATING_NU2_S 9 -#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_SLP_CLK_ENABLE \ - 0x00000100 // 1- Enable camera clk during - // sleep mode ; 0- Disable camera - // clk during sleep mode - -#define APPS_RCM_CAMERA_CLK_GATING_NU3_M \ - 0x000000FE - -#define APPS_RCM_CAMERA_CLK_GATING_NU3_S 1 -#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_RUN_CLK_ENABLE \ - 0x00000001 // 1- Enable camera clk during run - // mode ; 0- Disable camera clk - // during run mode - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_CAMERA_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_ENABLED_STATUS \ - 0x00000002 // 1 - Camera clocks/resets are - // enabled ; 0 - Camera - // clocks/resets are disabled - -#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for Camera-core - // ; 0 - De-assert reset for - // Camera-core - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCASP_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_MCASP_CLK_GATING_NU1_M \ - 0x00FE0000 - -#define APPS_RCM_MCASP_CLK_GATING_NU1_S 17 -#define APPS_RCM_MCASP_CLK_GATING_MCASP_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable MCASP clk during - // deep-sleep mode - -#define APPS_RCM_MCASP_CLK_GATING_NU2_M \ - 0x0000FE00 - -#define APPS_RCM_MCASP_CLK_GATING_NU2_S 9 -#define APPS_RCM_MCASP_CLK_GATING_MCASP_SLP_CLK_ENABLE \ - 0x00000100 // 1- Enable MCASP clk during sleep - // mode ; 0- Disable MCASP clk - // during sleep mode - -#define APPS_RCM_MCASP_CLK_GATING_NU3_M \ - 0x000000FE - -#define APPS_RCM_MCASP_CLK_GATING_NU3_S 1 -#define APPS_RCM_MCASP_CLK_GATING_MCASP_RUN_CLK_ENABLE \ - 0x00000001 // 1- Enable MCASP clk during run - // mode ; 0- Disable MCASP clk - // during run mode - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCASP_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_MCASP_SOFT_RESET_MCASP_ENABLED_STATUS \ - 0x00000002 // 1 - MCASP Clocks/resets are - // enabled ; 0 - MCASP Clocks/resets - // are disabled - -#define APPS_RCM_MCASP_SOFT_RESET_MCASP_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for MCASP-core - // ; 0 - De-assert reset for - // MCASP-core - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MMCHS_CLK_GEN register. -// -//****************************************************************************** -#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_M \ - 0x00000700 // Configuration of OFF-TIME for - // dividing PLL clk (240 MHz) in - // generation of MMCHS func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_S 8 -#define APPS_RCM_MMCHS_CLK_GEN_NU1_M \ - 0x000000F8 - -#define APPS_RCM_MMCHS_CLK_GEN_NU1_S 3 -#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_M \ - 0x00000007 // Configuration of ON-TIME for - // dividing PLL clk (240 MHz) in - // generation of MMCHS func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MMCHS_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_MMCHS_CLK_GATING_NU1_M \ - 0x00FE0000 - -#define APPS_RCM_MMCHS_CLK_GATING_NU1_S 17 -#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable MMCHS clk during - // deep-sleep mode - -#define APPS_RCM_MMCHS_CLK_GATING_NU2_M \ - 0x0000FE00 - -#define APPS_RCM_MMCHS_CLK_GATING_NU2_S 9 -#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_SLP_CLK_ENABLE \ - 0x00000100 // 1- Enable MMCHS clk during sleep - // mode ; 0- Disable MMCHS clk - // during sleep mode - -#define APPS_RCM_MMCHS_CLK_GATING_NU3_M \ - 0x000000FE - -#define APPS_RCM_MMCHS_CLK_GATING_NU3_S 1 -#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_RUN_CLK_ENABLE \ - 0x00000001 // 1- Enable MMCHS clk during run - // mode ; 0- Disable MMCHS clk - // during run mode - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MMCHS_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_ENABLED_STATUS \ - 0x00000002 // 1 - MMCHS Clocks/resets are - // enabled ; 0 - MMCHS Clocks/resets - // are disabled - -#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for MMCHS-core - // ; 0 - De-assert reset for - // MMCHS-core - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_A1_CLK_GEN register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_BAUD_CLK_SEL \ - 0x00010000 // 0 - XTAL clk is used as baud clk - // for MCSPI_A1 ; 1 - PLL divclk is - // used as baud clk for MCSPI_A1. - -#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_M \ - 0x0000F800 - -#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_S 11 -#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_M \ - 0x00000700 // Configuration of OFF-TIME for - // dividing PLL clk (240 MHz) in - // generation of MCSPI_A1 func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_S 8 -#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_M \ - 0x000000F8 - -#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_S 3 -#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_M \ - 0x00000007 // Configuration of ON-TIME for - // dividing PLL clk (240 MHz) in - // generation of MCSPI_A1 func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_A1_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_M \ - 0x00FE0000 - -#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_S 17 -#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable MCSPI_A1 clk during - // deep-sleep mode - -#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_M \ - 0x0000FE00 - -#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_S 9 -#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_SLP_CLK_ENABLE \ - 0x00000100 // 1- Enable MCSPI_A1 clk during - // sleep mode ; 0- Disable MCSPI_A1 - // clk during sleep mode - -#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_M \ - 0x000000FE - -#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_S 1 -#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_RUN_CLK_ENABLE \ - 0x00000001 // 1- Enable MCSPI_A1 clk during - // run mode ; 0- Disable MCSPI_A1 - // clk during run mode - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_A1_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_ENABLED_STATUS \ - 0x00000002 // 1 - MCSPI_A1 Clocks/Resets are - // enabled ; 0 - MCSPI_A1 - // Clocks/Resets are disabled - -#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for - // MCSPI_A1-core ; 0 - De-assert - // reset for MCSPI_A1-core - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_A2_CLK_GEN register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_BAUD_CLK_SEL \ - 0x00010000 // 0 - XTAL clk is used as baud-clk - // for MCSPI_A2 ; 1 - PLL divclk is - // used as baud-clk for MCSPI_A2 - -#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_M \ - 0x0000F800 - -#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_S 11 -#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_M \ - 0x00000700 // Configuration of OFF-TIME for - // dividing PLL clk (240 MHz) in - // generation of MCSPI_A2 func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_S 8 -#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_M \ - 0x000000F8 - -#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_S 3 -#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_M \ - 0x00000007 // Configuration of OFF-TIME for - // dividing PLL clk (240 MHz) in - // generation of MCSPI_A2 func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_A2_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_M \ - 0x00FE0000 - -#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_S 17 -#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable MCSPI_A2 clk during - // deep-sleep mode - -#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_M \ - 0x0000FE00 - -#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_S 9 -#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_SLP_CLK_ENABLE \ - 0x00000100 // 1- Enable MCSPI_A2 clk during - // sleep mode ; 0- Disable MCSPI_A2 - // clk during sleep mode - -#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_M \ - 0x000000FE - -#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_S 1 -#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_RUN_CLK_ENABLE \ - 0x00000001 // 1- Enable MCSPI_A2 clk during - // run mode ; 0- Disable MCSPI_A2 - // clk during run mode - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_A2_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_ENABLED_STATUS \ - 0x00000002 // 1 - MCSPI_A2 Clocks/Resets are - // enabled ; 0 - MCSPI_A2 - // Clocks/Resets are disabled - -#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for - // MCSPI_A2-core ; 0 - De-assert - // reset for MCSPI_A2-core - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_UDMA_A_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable UDMA_A clk during - // deep-sleep mode 0 - Disable - // UDMA_A clk during deep-sleep mode - // ; - -#define APPS_RCM_UDMA_A_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_UDMA_A_CLK_GATING_NU1_S 9 -#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable UDMA_A clk during - // sleep mode 0 - Disable UDMA_A clk - // during sleep mode ; - -#define APPS_RCM_UDMA_A_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_UDMA_A_CLK_GATING_NU2_S 1 -#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable UDMA_A clk during run - // mode 0 - Disable UDMA_A clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_UDMA_A_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_ENABLED_STATUS \ - 0x00000002 // 1 - UDMA_A Clocks/Resets are - // enabled ; 0 - UDMA_A - // Clocks/Resets are disabled - -#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for DMA_A ; 0 - - // De-assert reset for DMA_A - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_A_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable GPIO_A clk during - // deep-sleep mode 0 - Disable - // GPIO_A clk during deep-sleep mode - // ; - -#define APPS_RCM_GPIO_A_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPIO_A_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable GPIO_A clk during - // sleep mode 0 - Disable GPIO_A clk - // during sleep mode ; - -#define APPS_RCM_GPIO_A_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPIO_A_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable GPIO_A clk during run - // mode 0 - Disable GPIO_A clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_A_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_ENABLED_STATUS \ - 0x00000002 // 1 - GPIO_A Clocks/Resets are - // enabled ; 0 - GPIO_A - // Clocks/Resets are disabled - -#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for GPIO_A ; 0 - // - De-assert reset for GPIO_A - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_B_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable GPIO_B clk during - // deep-sleep mode 0 - Disable - // GPIO_B clk during deep-sleep mode - // ; - -#define APPS_RCM_GPIO_B_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPIO_B_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable GPIO_B clk during - // sleep mode 0 - Disable GPIO_B clk - // during sleep mode ; - -#define APPS_RCM_GPIO_B_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPIO_B_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable GPIO_B clk during run - // mode 0 - Disable GPIO_B clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_B_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_ENABLED_STATUS \ - 0x00000002 // 1 - GPIO_B Clocks/Resets are - // enabled ; 0 - GPIO_B - // Clocks/Resets are disabled - -#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for GPIO_B ; 0 - // - De-assert reset for GPIO_B - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_C_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable GPIO_C clk during - // deep-sleep mode 0 - Disable - // GPIO_C clk during deep-sleep mode - // ; - -#define APPS_RCM_GPIO_C_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPIO_C_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable GPIO_C clk during - // sleep mode 0 - Disable GPIO_C clk - // during sleep mode ; - -#define APPS_RCM_GPIO_C_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPIO_C_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable GPIO_C clk during run - // mode 0 - Disable GPIO_C clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_C_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_ENABLED_STATUS \ - 0x00000002 // 1 - GPIO_C Clocks/Resets are - // enabled ; 0 - GPIO_C - // Clocks/Resets are disabled - -#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for GPIO_C ; 0 - // - De-assert reset for GPIO_C - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_D_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable GPIO_D clk during - // deep-sleep mode 0 - Disable - // GPIO_D clk during deep-sleep mode - // ; - -#define APPS_RCM_GPIO_D_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPIO_D_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable GPIO_D clk during - // sleep mode 0 - Disable GPIO_D clk - // during sleep mode ; - -#define APPS_RCM_GPIO_D_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPIO_D_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable GPIO_D clk during run - // mode 0 - Disable GPIO_D clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_D_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_ENABLED_STATUS \ - 0x00000002 // 1 - GPIO_D Clocks/Resets are - // enabled ; 0 - GPIO_D - // Clocks/Resets are disabled - -#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for GPIO_D ; 0 - // - De-assert reset for GPIO_D - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_E_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable GPIO_E clk during - // deep-sleep mode 0 - Disable - // GPIO_E clk during deep-sleep mode - // ; - -#define APPS_RCM_GPIO_E_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPIO_E_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable GPIO_E clk during - // sleep mode 0 - Disable GPIO_E clk - // during sleep mode ; - -#define APPS_RCM_GPIO_E_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPIO_E_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable GPIO_E clk during run - // mode 0 - Disable GPIO_E clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPIO_E_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_ENABLED_STATUS \ - 0x00000002 // 1 - GPIO_E Clocks/Resets are - // enabled ; 0 - GPIO_E - // Clocks/Resets are disabled - -#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for GPIO_E ; 0 - // - De-assert reset for GPIO_E - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_WDOG_A_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_M \ - 0x03000000 // "00" - Sysclk ; "01" - REF_CLK - // (38.4 MHz) ; "10/11" - Slow_clk - -#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_S 24 -#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable WDOG_A clk during - // deep-sleep mode 0 - Disable - // WDOG_A clk during deep-sleep mode - // ; - -#define APPS_RCM_WDOG_A_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_WDOG_A_CLK_GATING_NU1_S 9 -#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable WDOG_A clk during - // sleep mode 0 - Disable WDOG_A clk - // during sleep mode ; - -#define APPS_RCM_WDOG_A_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_WDOG_A_CLK_GATING_NU2_S 1 -#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable WDOG_A clk during run - // mode 0 - Disable WDOG_A clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_WDOG_A_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_ENABLED_STATUS \ - 0x00000002 // 1 - WDOG_A Clocks/Resets are - // enabled ; 0 - WDOG_A - // Clocks/Resets are disabled - -#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for WDOG_A ; 0 - // - De-assert reset for WDOG_A - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_UART_A0_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable UART_A0 clk during - // deep-sleep mode 0 - Disable - // UART_A0 clk during deep-sleep - // mode ; - -#define APPS_RCM_UART_A0_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_UART_A0_CLK_GATING_NU1_S 9 -#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable UART_A0 clk during - // sleep mode 0 - Disable UART_A0 - // clk during sleep mode ; - -#define APPS_RCM_UART_A0_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_UART_A0_CLK_GATING_NU2_S 1 -#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable UART_A0 clk during - // run mode 0 - Disable UART_A0 clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_UART_A0_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_ENABLED_STATUS \ - 0x00000002 // 1 - UART_A0 Clocks/Resets are - // enabled ; 0 - UART_A0 - // Clocks/Resets are disabled - -#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_SOFT_RESET \ - 0x00000001 // 1 - Assert reset for UART_A0 ; 0 - // - De-assert reset for UART_A0 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_UART_A1_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable UART_A1 clk during - // deep-sleep mode 0 - Disable - // UART_A1 clk during deep-sleep - // mode ; - -#define APPS_RCM_UART_A1_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_UART_A1_CLK_GATING_NU1_S 9 -#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable UART_A1 clk during - // sleep mode 0 - Disable UART_A1 - // clk during sleep mode ; - -#define APPS_RCM_UART_A1_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_UART_A1_CLK_GATING_NU2_S 1 -#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable UART_A1 clk during - // run mode 0 - Disable UART_A1 clk - // during run mode ; - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_UART_A1_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_ENABLED_STATUS \ - 0x00000002 // 1 - UART_A1 Clocks/Resets are - // enabled ; 0 - UART_A1 - // Clocks/Resets are disabled - -#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // UART_A1 ; 0 - De-assert the soft - // reset for UART_A1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A0_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable the GPT_A0 clock - // during deep-sleep ; 0 - Disable - // the GPT_A0 clock during - // deep-sleep - -#define APPS_RCM_GPT_A0_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPT_A0_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the GPT_A0 clock - // during sleep ; 0 - Disable the - // GPT_A0 clock during sleep - -#define APPS_RCM_GPT_A0_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPT_A0_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the GPT_A0 clock - // during run ; 0 - Disable the - // GPT_A0 clock during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A0_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_ENABLED_STATUS \ - 0x00000002 // 1 - GPT_A0 clocks/resets are - // enabled ; 0 - GPT_A0 - // clocks/resets are disabled - -#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // GPT_A0 ; 0 - De-assert the soft - // reset for GPT_A0 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A1_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable the GPT_A1 clock - // during deep-sleep ; 0 - Disable - // the GPT_A1 clock during - // deep-sleep - -#define APPS_RCM_GPT_A1_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPT_A1_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the GPT_A1 clock - // during sleep ; 0 - Disable the - // GPT_A1 clock during sleep - -#define APPS_RCM_GPT_A1_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPT_A1_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the GPT_A1 clock - // during run ; 0 - Disable the - // GPT_A1 clock during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A1_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_ENABLED_STATUS \ - 0x00000002 // 1 - GPT_A1 clocks/resets are - // enabled ; 0 - GPT_A1 - // clocks/resets are disabled - -#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // GPT_A1 ; 0 - De-assert the soft - // reset for GPT_A1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A2_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable the GPT_A2 clock - // during deep-sleep ; 0 - Disable - // the GPT_A2 clock during - // deep-sleep - -#define APPS_RCM_GPT_A2_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPT_A2_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the GPT_A2 clock - // during sleep ; 0 - Disable the - // GPT_A2 clock during sleep - -#define APPS_RCM_GPT_A2_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPT_A2_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the GPT_A2 clock - // during run ; 0 - Disable the - // GPT_A2 clock during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A2_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_ENABLED_STATUS \ - 0x00000002 // 1 - GPT_A2 clocks/resets are - // enabled ; 0 - GPT_A2 - // clocks/resets are disabled - -#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // GPT_A2 ; 0 - De-assert the soft - // reset for GPT_A2 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A3_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable the GPT_A3 clock - // during deep-sleep ; 0 - Disable - // the GPT_A3 clock during - // deep-sleep - -#define APPS_RCM_GPT_A3_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_GPT_A3_CLK_GATING_NU1_S 9 -#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the GPT_A3 clock - // during sleep ; 0 - Disable the - // GPT_A3 clock during sleep - -#define APPS_RCM_GPT_A3_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_GPT_A3_CLK_GATING_NU2_S 1 -#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the GPT_A3 clock - // during run ; 0 - Disable the - // GPT_A3 clock during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_GPT_A3_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_ENABLED_STATUS \ - 0x00000002 // 1 - GPT_A3 Clocks/resets are - // enabled ; 0 - GPT_A3 - // Clocks/resets are disabled - -#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // GPT_A3 ; 0 - De-assert the soft - // reset for GPT_A3 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 register. -// -//****************************************************************************** -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_M \ - 0x03FF0000 - -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_S 16 -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_M \ - 0x0000FFFF - -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 register. -// -//****************************************************************************** -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_SOFT_RESET \ - 0x00010000 // 1 - Assert the reset for MCASP - // Frac-clk div; 0 - Donot assert - // the reset for MCASP frac clk-div - -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_M \ - 0x000003FF - -#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_CRYPTO_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable the Crypto clock - // during deep-sleep - -#define APPS_RCM_CRYPTO_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_CRYPTO_CLK_GATING_NU1_S 9 -#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the Crypto clock - // during sleep ; 0 - Disable the - // Crypto clock during sleep - -#define APPS_RCM_CRYPTO_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_CRYPTO_CLK_GATING_NU2_S 1 -#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the Crypto clock - // during run ; 0 - Disable the - // Crypto clock during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_CRYPTO_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_ENABLED_STATUS \ - 0x00000002 // 1 - Crypto clocks/resets are - // enabled ; 0 - Crypto - // clocks/resets are disabled - -#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // Crypto ; 0 - De-assert the soft - // reset for Crypto - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_S0_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_DSLP_CLK_ENABLE \ - 0x00010000 // 0 - Disable the MCSPI_S0 clock - // during deep-sleep - -#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_S 9 -#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the MCSPI_S0 clock - // during sleep ; 0 - Disable the - // MCSPI_S0 clock during sleep - -#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_S 1 -#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the MCSPI_S0 clock - // during run ; 0 - Disable the - // MCSPI_S0 clock during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_S0_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_ENABLED_STATUS \ - 0x00000002 // 1 - MCSPI_S0 Clocks/Resets are - // enabled ; 0 - MCSPI_S0 - // Clocks/resets are disabled - -#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // MCSPI_S0 ; 0 - De-assert the soft - // reset for MCSPI_S0 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_MCSPI_S0_CLKDIV_CFG register. -// -//****************************************************************************** -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_BAUD_CLK_SEL \ - 0x00010000 // 0 - XTAL clk is used as baud-clk - // for MCSPI_S0 ; 1 - PLL divclk is - // used as buad-clk for MCSPI_S0 - -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_M \ - 0x0000F800 - -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_S 11 -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_M \ - 0x00000700 // Configuration of OFF-TIME for - // dividing PLL clk (240 MHz) in - // generation of MCSPI_S0 func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_S 8 -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_M \ - 0x000000F8 - -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_S 3 -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_M \ - 0x00000007 // Configuration of ON-TIME for - // dividing PLL clk (240 MHz) in - // generation of MCSPI_S0 func-clk : - // "000" - 1 "001" - 2 "010" - 3 - // "011" - 4 "100" - 5 "101" - 6 - // "110" - 7 "111" - 8 - -#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_I2C_CLK_GATING register. -// -//****************************************************************************** -#define APPS_RCM_I2C_CLK_GATING_I2C_DSLP_CLK_ENABLE \ - 0x00010000 // 1 - Enable the I2C Clock during - // deep-sleep 0 - Disable the I2C - // clock during deep-sleep - -#define APPS_RCM_I2C_CLK_GATING_NU1_M \ - 0x0000FE00 - -#define APPS_RCM_I2C_CLK_GATING_NU1_S 9 -#define APPS_RCM_I2C_CLK_GATING_I2C_SLP_CLK_ENABLE \ - 0x00000100 // 1 - Enable the I2C clock during - // sleep ; 0 - Disable the I2C clock - // during sleep - -#define APPS_RCM_I2C_CLK_GATING_NU2_M \ - 0x000000FE - -#define APPS_RCM_I2C_CLK_GATING_NU2_S 1 -#define APPS_RCM_I2C_CLK_GATING_I2C_RUN_CLK_ENABLE \ - 0x00000001 // 1 - Enable the I2C clock during - // run ; 0 - Disable the I2C clock - // during run - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_I2C_SOFT_RESET register. -// -//****************************************************************************** -#define APPS_RCM_I2C_SOFT_RESET_I2C_ENABLED_STATUS \ - 0x00000002 // 1 - I2C Clocks/Resets are - // enabled ; 0 - I2C clocks/resets - // are disabled - -#define APPS_RCM_I2C_SOFT_RESET_I2C_SOFT_RESET \ - 0x00000001 // 1 - Assert the soft reset for - // Shared-I2C ; 0 - De-assert the - // soft reset for Shared-I2C - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_LPDS_REQ register. -// -//****************************************************************************** -#define APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ \ - 0x00000001 // 1 - Request for LPDS - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_TURBO_REQ register. -// -//****************************************************************************** -#define APPS_RCM_APPS_TURBO_REQ_APPS_TURBO_REQ \ - 0x00000001 // 1 - Request for TURBO - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_DSLP_WAKE_CONFIG register. -// -//****************************************************************************** -#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_FROM_NWP_ENABLE \ - 0x00000002 // 1 - Enable the NWP to wake APPS - // from deep-sleep ; 0 - Disable NWP - // to wake APPS from deep-sleep - -#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_TIMER_ENABLE \ - 0x00000001 // 1 - Enable deep-sleep wake timer - // in APPS RCM for deep-sleep; 0 - - // Disable deep-sleep wake timer in - // APPS RCM - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG register. -// -//****************************************************************************** -#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_M \ - 0xFFFF0000 // Configuration (in slow_clks) - // which says when to request for - // OPP during deep-sleep exit - -#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_S 16 -#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_M \ - 0x0000FFFF // Configuration (in slow_clks) - // which says when to request for - // WAKE during deep-sleep exit - -#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE register. -// -//****************************************************************************** -#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_FROM_NWP_ENABLE \ - 0x00000002 // 1- Enable the sleep wakeup due - // to NWP request. 0- Disable the - // sleep wakeup due to NWP request - -#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_TIMER_ENABLE \ - 0x00000001 // 1- Enable the sleep wakeup due - // to sleep-timer; 0-Disable the - // sleep wakeup due to sleep-timer - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_SLP_WAKETIMER_CFG register. -// -//****************************************************************************** -#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_M \ - 0xFFFFFFFF // Configuration (number of - // sysclks-80MHz) for the Sleep - // wakeup timer - -#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST register. -// -//****************************************************************************** -#define APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST \ - 0x00000001 // When 1 => APPS generated a wake - // request to NWP (When NWP is in - // any of its low-power modes : - // SLP/DSLP/LPDS) - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS register. -// -//****************************************************************************** -#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_timer_wake \ - 0x00000008 // 1 - Indicates that deep-sleep - // timer expiry had caused the - // wakeup from deep-sleep - -#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_timer_wake \ - 0x00000004 // 1 - Indicates that sleep timer - // expiry had caused the wakeup from - // sleep - -#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_wake_from_nwp \ - 0x00000002 // 1 - Indicates that NWP had - // caused the wakeup from deep-sleep - -#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_wake_from_nwp \ - 0x00000001 // 1 - Indicates that NWP had - // caused the wakeup from Sleep - - - - -#endif // __HW_APPS_RCM_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_camera.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_camera.h deleted file mode 100644 index 11e4edb0e37..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_camera.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_CAMERA_H__ -#define __HW_CAMERA_H__ - -//***************************************************************************** -// -// The following are defines for the CAMERA register offsets. -// -//***************************************************************************** -#define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP - // revision code ( Parallel Mode) -#define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the - // various parameters of the OCP - // interface (CCP and Parallel Mode) -#define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status - // information about the module - // excluding the interrupt status - // information (CCP and Parallel - // Mode) -#define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups - // all the status of the module - // internal events that can generate - // an interrupt (CCP & Parallel - // Mode) -#define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register - // allows to enable/disable the - // module internal sources of - // interrupt on an event-by-event - // basis (CCP & Parallel Mode) -#define CAMERA_O_CC_CTRL 0x00000040 // This register controls the - // various parameters of the Camera - // Core block (CCP & Parallel Mode) -#define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA - // interface of the Camera Core - // block (CCP & Parallel Mode) -#define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value - // of the clock divisor used to - // generate the external clock - // (Parallel Mode) -#define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to - // the FIFO and read from the FIFO - // (CCP & Parallel Mode) -#define CAMERA_O_CC_TEST 0x00000050 // This register shows the status - // of some important variables of - // the camera core module (CCP & - // Parallel Mode) -#define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values - // of the generic parameters of the - // module - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_REVISION register. -// -//****************************************************************************** -#define CAMERA_CC_REVISION_REV_M \ - 0x000000FF // IP revision [7:4] Major revision - // [3:0] Minor revision Examples: - // 0x10 for 1.0 0x21 for 2.1 - -#define CAMERA_CC_REVISION_REV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_SYSCONFIG register. -// -//****************************************************************************** -#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \ - 0x00000018 // Slave interface power management - // req/ack control """00"" - // Force-idle. An idle request is - // acknoledged unconditionally" - // """01"" No-idle. An idle request - // is never acknowledged" """10"" - // reserved (Smart-idle not - // implemented)" - -#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3 -#define CAMERA_CC_SYSCONFIG_SOFT_RESET \ - 0x00000002 // Software reset. Set this bit to - // 1 to trigger a module reset. The - // bit is automatically reset by the - // hardware. During reset it always - // returns 0. 0 Normal mode 1 The - // module is reset - -#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \ - 0x00000001 // Internal OCP clock gating - // strategy 0 OCP clock is - // free-running 1 Automatic OCP - // clock gating strategy is applied - // based on the OCP interface - // activity - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_SYSSTATUS register. -// -//****************************************************************************** -#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \ - 0x00000001 // Internal Reset Monitoring 0 - // Internal module reset is on-going - // 1 Reset completed - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_IRQSTATUS register. -// -//****************************************************************************** -#define CAMERA_CC_IRQSTATUS_FS_IRQ \ - 0x00080000 // Frame Start has occurred 0 Event - // false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_LE_IRQ \ - 0x00040000 // Line End has occurred 0 Event - // false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_LS_IRQ \ - 0x00020000 // Line Start has occurred 0 Event - // false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_FE_IRQ \ - 0x00010000 // Frame End has occurred 0 Event - // false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \ - 0x00000800 // FSP code error 0 Event false "1 - // Event is true (""pending"")" 0 - // Event status bit unchanged 1 - // Event status bit is reset - -#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \ - 0x00000400 // Frame Height Error 0 Event false - // "1 Event is true (""pending"")" 0 - // Event status bit unchanged 1 - // Event status bit is reset - -#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \ - 0x00000200 // False Synchronization Code 0 - // Event false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \ - 0x00000100 // Shifted Synchronization Code 0 - // Event false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \ - 0x00000010 // FIFO is not empty 0 Event false - // "1 Event is true (""pending"")" 0 - // Event status bit unchanged 1 - // Event status bit is reset - -#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \ - 0x00000008 // FIFO is full 0 Event false "1 - // Event is true (""pending"")" 0 - // Event status bit unchanged 1 - // Event status bit is reset - -#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \ - 0x00000004 // FIFO threshold has been reached - // 0 Event false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \ - 0x00000002 // FIFO overflow has occurred 0 - // Event false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \ - 0x00000001 // FIFO underflow has occurred 0 - // Event false "1 Event is true - // (""pending"")" 0 Event status bit - // unchanged 1 Event status bit is - // reset - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_IRQENABLE register. -// -//****************************************************************************** -#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \ - 0x00080000 // Frame Start Interrupt Enable 0 - // Event is masked 1 Event generates - // an interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \ - 0x00040000 // Line End Interrupt Enable 0 - // Event is masked 1 Event generates - // an interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \ - 0x00020000 // Line Start Interrupt Enable 0 - // Event is masked 1 Event generates - // an interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \ - 0x00010000 // Frame End Interrupt Enable 0 - // Event is masked 1 Event generates - // an interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \ - 0x00000800 // FSP code Interrupt Enable 0 - // Event is masked 1 Event generates - // an interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \ - 0x00000400 // Frame Height Error Interrupt - // Enable 0 Event is masked 1 Event - // generates an interrupt when it - // occurs - -#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \ - 0x00000200 // False Synchronization Code - // Interrupt Enable 0 Event is - // masked 1 Event generates an - // interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \ - 0x00000100 // False Synchronization Code - // Interrupt Enable 0 Event is - // masked 1 Event generates an - // interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \ - 0x00000010 // FIFO Threshold Interrupt Enable - // 0 Event is masked 1 Event - // generates an interrupt when it - // occurs - -#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \ - 0x00000008 // FIFO Threshold Interrupt Enable - // 0 Event is masked 1 Event - // generates an interrupt when it - // occurs - -#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \ - 0x00000004 // FIFO Threshold Interrupt Enable - // 0 Event is masked 1 Event - // generates an interrupt when it - // occurs - -#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \ - 0x00000002 // FIFO Overflow Interrupt Enable 0 - // Event is masked 1 Event generates - // an interrupt when it occurs - -#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \ - 0x00000001 // FIFO Underflow Interrupt Enable - // 0 Event is masked 1 Event - // generates an interrupt when it - // occurs - -//****************************************************************************** -// -// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register. -// -//****************************************************************************** -#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \ - 0x00080000 // Synchronize all camera sensor - // inputs This must be set during - // the configuration phase before - // CC_EN set to '1'. This can be - // used in very high frequency to - // avoid dependancy to the IO - // timings. 0 No synchro (most of - // applications) 1 Synchro enabled - // (should never be required) - -#define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite - // states machines of the camera - // core module - by writing a 1 to - // this bit. must be applied when - // CC_EN = 0 Reads returns 0 -#define CAMERA_CC_CTRL_CC_FRAME_TRIG \ - 0x00020000 // Set the modality in which CC_EN - // works when a disabling of the - // sensor camera core is wanted "If - // CC_FRAME_TRIG = 1 by writing - // ""0"" to CC_EN" the module is - // disabled at the end of the frame - // "If CC_FRAME_TRIG = 0 by writing - // ""0"" to CC_EN" the module is - // disabled immediately - -#define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of - // the camera core module "By - // writing ""1"" to this field the - // module is enabled." "By writing - // ""0"" to this field the module is - // disabled at" the end of the frame - // if CC_FRAM_TRIG =1 and is - // disabled immediately if - // CC_FRAM_TRIG = 0 -#define CAMERA_CC_CTRL_NOBT_SYNCHRO \ - 0x00002000 // Enables to start at the - // beginning of the frame or not in - // NoBT 0 Acquisition starts when - // Vertical synchro is high 1 - // Acquisition starts when Vertical - // synchro goes from low to high - // (beginning of the frame) - - // Recommended. - -#define CAMERA_CC_CTRL_BT_CORRECT \ - 0x00001000 // Enables the correction within - // the sync codes in BT mode 0 - // correction is not enabled 1 - // correction is enabled - -#define CAMERA_CC_CTRL_PAR_ORDERCAM \ - 0x00000800 // Enables swap between image-data - // in parallel mode 0 swap is not - // enabled 1 swap is enabled - -#define CAMERA_CC_CTRL_PAR_CLK_POL \ - 0x00000400 // Inverts the clock coming from - // the sensor in parallel mode 0 - // clock not inverted - data sampled - // on rising edge 1 clock inverted - - // data sampled on falling edge - -#define CAMERA_CC_CTRL_NOBT_HS_POL \ - 0x00000200 // Sets the polarity of the - // synchronization signals in NOBT - // parallel mode 0 CAM_P_HS is - // active high 1 CAM_P_HS is active - // low - -#define CAMERA_CC_CTRL_NOBT_VS_POL \ - 0x00000100 // Sets the polarity of the - // synchronization signals in NOBT - // parallel mode 0 CAM_P_VS is - // active high 1 CAM_P_VS is active - // low - -#define CAMERA_CC_CTRL_PAR_MODE_M \ - 0x0000000E // Sets the Protocol Mode of the - // Camera Core module in parallel - // mode (when CCP_MODE = 0) """000"" - // Parallel NOBT 8-bit" """001"" - // Parallel NOBT 10-bit" """010"" - // Parallel NOBT 12-bit" """011"" - // reserved" """100"" Parallet BT - // 8-bit" """101"" Parallel BT - // 10-bit" """110"" reserved" - // """111"" FIFO test mode. Refer to - // Table 12 - FIFO Write and Read - // access" - -#define CAMERA_CC_CTRL_PAR_MODE_S 1 -#define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode - // 0 CCP mode disabled 1 CCP mode - // enabled -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_CTRL_DMA register. -// -//****************************************************************************** -#define CAMERA_CC_CTRL_DMA_DMA_EN \ - 0x00000100 // Sets the number of dma request - // lines 0 DMA interface disabled - // The DMA request line stays - // inactive 1 DMA interface enabled - // The DMA request line is - // operational - -#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \ - 0x0000007F // Sets the threshold of the FIFO - // the assertion of the dmarequest - // line takes place when the - // threshold is reached. - // """0000000"" threshold set to 1" - // """0000001"" threshold set to 2" - // … """1111111"" threshold set to - // 128" - -#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_CTRL_XCLK register. -// -//****************************************************************************** -#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \ - 0x0000001F // Sets the clock divisor value for - // CAM_XCLK generation. based on - // CAM_MCK (value of CAM_MCLK is - // 96MHz) """00000"" CAM_XCLK Stable - // Low Level" Divider not enabled - // """00001"" CAM_XCLK Stable High - // Level" Divider not enabled from 2 - // to 30 CAM_XCLK = CAM_MCLK / - // XCLK_DIV """11111"" Bypass - - // CAM_XCLK = CAM_MCLK" - -#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_FIFO_DATA register. -// -//****************************************************************************** -#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \ - 0xFFFFFFFF // Writes the 32-bit word into the - // FIFO Reads the 32-bit word from - // the FIFO - -#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the CAMERA_O_CC_TEST register. -// -//****************************************************************************** -#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \ - 0xFF000000 // FIFO READ Pointer This field - // shows the value of the FIFO read - // pointer Expected value ranges - // from 0 to 127 - -#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24 -#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \ - 0x00FF0000 // FIFO WRITE pointer This field - // shows the value of the FIFO write - // pointer Expected value ranges - // from 0 to 127 - -#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16 -#define CAMERA_CC_TEST_FIFO_LEVEL_M \ - 0x0000FF00 // FIFO level (how many 32-bit - // words the FIFO contains) This - // field shows the value of the FIFO - // level and can assume values from - // 0 to 128 - -#define CAMERA_CC_TEST_FIFO_LEVEL_S 8 -#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \ - 0x000000FF // FIFO level peak This field shows - // the max value of the FIFO level - // and can assume values from 0 to - // 128 - -#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// CAMERA_O_CC_GEN_PAR register. -// -//****************************************************************************** -#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \ - 0x00000007 // Camera Core FIFO DEPTH generic - // parameter - -#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0 - - - -#endif // __HW_CAMERA_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_common_reg.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_common_reg.h deleted file mode 100644 index f296e1c533b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_common_reg.h +++ /dev/null @@ -1,1115 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_COMMON_REG_H__ -#define __HW_COMMON_REG_H__ - -//***************************************************************************** -// -// The following are defines for the COMMON_REG register offsets. -// -//***************************************************************************** -#define COMMON_REG_O_I2C_Properties_Register \ - 0x00000000 - -#define COMMON_REG_O_SPI_Properties_Register \ - 0x00000004 - -#define COMMON_REG_O_APPS_sh_resource_Interrupt_enable \ - 0x0000000C - -#define COMMON_REG_O_APPS_sh_resource_Interrupt_status \ - 0x00000010 - -#define COMMON_REG_O_NWP_sh_resource_Interrupt_enable \ - 0x00000014 - -#define COMMON_REG_O_NWP_sh_resource_Interrupt_status \ - 0x00000018 - -#define COMMON_REG_O_Flash_ctrl_reg \ - 0x0000001C - -#define COMMON_REG_O_Bus_matrix_M0_segment_access_config \ - 0x00000024 - -#define COMMON_REG_O_Bus_matrix_M1_segment_access_config \ - 0x00000028 - -#define COMMON_REG_O_Bus_matrix_M2_segment_access_config \ - 0x0000002C - -#define COMMON_REG_O_Bus_matrix_M3_segment_access_config \ - 0x00000030 - -#define COMMON_REG_O_Bus_matrix_M4_segment_access_config \ - 0x00000034 - -#define COMMON_REG_O_Bus_matrix_M5_segment_access_config \ - 0x00000038 - -#define COMMON_REG_O_GPIO_properties_register \ - 0x0000003C - -#define COMMON_REG_O_APPS_NW_SEMAPHORE1 \ - 0x00000040 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE2 \ - 0x00000044 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE3 \ - 0x00000048 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE4 \ - 0x0000004C - -#define COMMON_REG_O_APPS_NW_SEMAPHORE5 \ - 0x00000050 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE6 \ - 0x00000054 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE7 \ - 0x00000058 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE8 \ - 0x0000005C - -#define COMMON_REG_O_APPS_NW_SEMAPHORE9 \ - 0x00000060 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE10 \ - 0x00000064 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE11 \ - 0x00000068 - -#define COMMON_REG_O_APPS_NW_SEMAPHORE12 \ - 0x0000006C - -#define COMMON_REG_O_APPS_SEMAPPHORE_PEND \ - 0x00000070 - -#define COMMON_REG_O_NW_SEMAPPHORE_PEND \ - 0x00000074 - -#define COMMON_REG_O_SEMAPHORE_STATUS \ - 0x00000078 - -#define COMMON_REG_O_IDMEM_TIM_Update \ - 0x0000007C - -#define COMMON_REG_O_FPGA_ROM_WR_EN \ - 0x00000080 - -#define COMMON_REG_O_NW_INT_MASK \ - 0x00000084 - -#define COMMON_REG_O_NW_INT_MASK_SET \ - 0x00000088 - -#define COMMON_REG_O_NW_INT_MASK_CLR \ - 0x0000008C - -#define COMMON_REG_O_NW_INT_STS_CLR \ - 0x00000090 - -#define COMMON_REG_O_NW_INT_ACK 0x00000094 -#define COMMON_REG_O_NW_INT_TRIG \ - 0x00000098 - -#define COMMON_REG_O_NW_INT_STS_MASKED \ - 0x0000009C - -#define COMMON_REG_O_NW_INT_STS_RAW \ - 0x000000A0 - -#define COMMON_REG_O_APPS_INT_MASK \ - 0x000000A4 - -#define COMMON_REG_O_APPS_INT_MASK_SET \ - 0x000000A8 - -#define COMMON_REG_O_APPS_INT_MASK_CLR \ - 0x000000AC - -#define COMMON_REG_O_APPS_INT_STS_CLR \ - 0x000000B0 - -#define COMMON_REG_O_APPS_INT_ACK \ - 0x000000B4 - -#define COMMON_REG_O_APPS_INT_TRIG \ - 0x000000B8 - -#define COMMON_REG_O_APPS_INT_STS_MASKED \ - 0x000000BC - -#define COMMON_REG_O_APPS_INT_STS_RAW \ - 0x000000C0 - -#define COMMON_REG_O_IDMEM_TIM_Updated \ - 0x000000C4 - -#define COMMON_REG_O_APPS_GPIO_TRIG_EN \ - 0x000000C8 - -#define COMMON_REG_O_EMU_DEBUG_REG \ - 0x000000CC - -#define COMMON_REG_O_SEMAPHORE_STATUS2 \ - 0x000000D0 - -#define COMMON_REG_O_SEMAPHORE_PREV_OWNER1 \ - 0x000000D4 - -#define COMMON_REG_O_SEMAPHORE_PREV_OWNER2 \ - 0x000000D8 - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_I2C_Properties_Register register. -// -//****************************************************************************** -#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M \ - 0x00000003 // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_SPI_Properties_Register register. -// -//****************************************************************************** -#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_M \ - 0x00000003 // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_S 0 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_sh_resource_Interrupt_enable register. -// -//****************************************************************************** -#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_M \ - 0x0000000F // Interrupt enable APPS bit 0 -> - // when '1' enable I2C interrupt bit - // 1 -> when '1' enable SPI - // interrupt bit 3 -> - // when '1' enable GPIO interrupt - -#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_sh_resource_Interrupt_status register. -// -//****************************************************************************** -#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_M \ - 0x0000000F // Interrupt enable APPS bit 0 -> - // when '1' enable I2C interrupt bit - // 1 -> when '1' enable SPI - // interrupt bit 3 -> - // when '1' enable GPIO interrupt - -#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NWP_sh_resource_Interrupt_enable register. -// -//****************************************************************************** -#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_M \ - 0x0000000F // Interrupt enable NWP bit 0 -> - // when '1' enable I2C interrupt bit - // 1 -> when '1' enable SPI - // interrupt bit 3 -> - // when '1' enable GPIO interrupt - -#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NWP_sh_resource_Interrupt_status register. -// -//****************************************************************************** -#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_M \ - 0x0000000F // Interrupt enable NWP bit 0 -> - // when '1' enable I2C interrupt bit - // 1 -> when '1' enable SPI - // interrupt bit 3 -> - // when '1' enable GPIO interrupt - -#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Flash_ctrl_reg register. -// -//****************************************************************************** -#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_M \ - 0x00000003 // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Bus_matrix_M0_segment_access_config register. -// -//****************************************************************************** -#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_M \ - 0x0003FFFF // Master 0 control word matrix to - // each segment. Tieoff. Bit value 1 - // indicates segment is accesable. - -#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Bus_matrix_M1_segment_access_config register. -// -//****************************************************************************** -#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_M \ - 0x0003FFFF // Master 1 control word matrix to - // each segment. Tieoff. Bit value 1 - // indicates segment is accesable. - -#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Bus_matrix_M2_segment_access_config register. -// -//****************************************************************************** -#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_M \ - 0x0003FFFF // Master 2 control word matrix to - // each segment. Tieoff. Bit value 1 - // indicates segment is accesable. - -#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Bus_matrix_M3_segment_access_config register. -// -//****************************************************************************** -#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_M \ - 0x0003FFFF // Master 3 control word matrix to - // each segment. Tieoff. Bit value 1 - // indicates segment is accesable. - -#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Bus_matrix_M4_segment_access_config register. -// -//****************************************************************************** -#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_M \ - 0x0003FFFF // Master 4 control word matrix to - // each segment. Tieoff. Bit value 1 - // indicates segment is accesable. - -#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_Bus_matrix_M5_segment_access_config register. -// -//****************************************************************************** -#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_M \ - 0x0003FFFF // Master 5 control word matrix to - // each segment. Tieoff. Bit value 1 - // indicates segment is accesable. - -#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_GPIO_properties_register register. -// -//****************************************************************************** -#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_M \ - 0x000003FF // Shared GPIO configuration - // register. Bit [1:0] to configure - // GPIO0 Bit [3:2] to configure - // GPIO1 Bit [5:4] to configure - // GPIO2 Bit [7:6] to configure - // GPIO3 Bit [9:8] to configure - // GPIO4 each GPIO can be - // individully selected. When “00� - // GPIO is free resource. When “01� - // GPIO is APPS resource. When “10� - // GPIO is NWP resource. Writing 11 - // doesnt have any affect, i.e. If - // one write only relevant gpio - // semaphore and other bits are 1s, - // it'll not disturb the other - // semaphore bits. For example : Say - // If NW wants to take control of - // gpio-1, one should write - // 10'b11_1111_1011 and if one wants - // to release it write - // 10'b11_1111_0011. - -#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE1 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE2 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE3 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE4 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE5 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE6 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE7 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE8 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE9 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE10 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE11 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_M \ - 0xFFFFFFFF // • Each semaphore register is of - // 2 bit. • When this register is - // set to 2’b01 – Apps have access - // and when set to 2’b10 – NW have - // access. • Ideally both the master - // can modify any of this 2 bit, but - // assumption apps will write only - // 2’b01 or 2’b00 to this register - // and nw will write only 2’b10 or - // 2’b00. • Implementation is when - // any of the bit of this register - // is set, only next write - // allowedvis 2’b00 – Again - // assumption is one master will not - // write 2’b00 if other is already - // holding the semaphore. - -#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_NW_SEMAPHORE12 register. -// -//****************************************************************************** -#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_M \ - 0xFFFFFFFF // APPS NW semaphore register - not - // reflected in status. - -#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_SEMAPPHORE_PEND register. -// -//****************************************************************************** -#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_M \ - 0xFFFFFFFF // APPS SEMAPOHORE STATUS - -#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_SEMAPPHORE_PEND register. -// -//****************************************************************************** -#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_M \ - 0xFFFFFFFF // NW SEMAPHORE STATUS - -#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_SEMAPHORE_STATUS register. -// -//****************************************************************************** -#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_M \ - 0xFFFFFFFF // SEMAPHORE STATUS 9:8 :semaphore - // status of flash_control 7:6 - // :semaphore status of - // gpio_properties 5:4 - // :semaphore status of - // spi_propertie 1:0 :semaphore - // status of i2c_propertie - -#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_IDMEM_TIM_Update register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_FPGA_ROM_WR_EN register. -// -//****************************************************************************** -#define COMMON_REG_FPGA_ROM_WR_EN_FPGA_ROM_WR_EN \ - 0x00000001 // when '1' enables Write into - // IDMEM CORE ROM, APPS ROM, NWP ROM - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_MASK register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_M \ - 0xFFFFFFFF // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_MASK_SET register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_M \ - 0xFFFFFFFF // write 1 to set corresponding bit - // in NW_INT_MASK;0 = no effect - -#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_MASK_CLR register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_M \ - 0xFFFFFFFF // write 1 to clear corresponding - // bit in NW_INT_MASK;0 = no effect - -#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_STS_CLR register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_M \ - 0xFFFFFFFF // write 1 to clear corresponding - // interrupt; 0 = no effect; - // interrupt is not lost if coincide - // with write operation - -#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_ACK register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_M \ - 0xFFFFFFFF // write 1 to clear corresponding - // interrupt;0 = no effect - -#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_TRIG register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_M \ - 0xFFFFFFFF // Writing a 1 to a bit in this - // register causes the the Host CPU - // if enabled (not masked). This - // register is self-clearing. - // Writing 0 has no effect - -#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_STS_MASKED register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_M \ - 0xFFFFFFFF // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by NW_INT mask - -#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_NW_INT_STS_RAW register. -// -//****************************************************************************** -#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_M \ - 0xFFFFFFFF // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_MASK register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_M \ - 0xFFFFFFFF // 1= disable corresponding - // interrupt;0 = interrupt enabled - -#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_MASK_SET register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_M \ - 0xFFFFFFFF // write 1 to set corresponding bit - // in APPS_INT_MASK;0 = no effect - -#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_MASK_CLR register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_M \ - 0xFFFFFFFF // write 1 to clear corresponding - // bit in APPS_INT_MASK;0 = no - // effect - -#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_STS_CLR register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_M \ - 0xFFFFFFFF // write 1 to clear corresponding - // interrupt; 0 = no effect; - // interrupt is not lost if coincide - // with write operation - -#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_ACK register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_M \ - 0xFFFFFFFF // write 1 to clear corresponding - // interrupt;0 = no effect - -#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_TRIG register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_M \ - 0xFFFFFFFF // Writing a 1 to a bit in this - // register causes the the Host CPU - // if enabled (not masked). This - // register is self-clearing. - // Writing 0 has no effect - -#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_STS_MASKED register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_M \ - 0xFFFFFFFF // 1= corresponding interrupt is - // active and not masked. read is - // non-destructive;0 = corresponding - // interrupt is inactive or masked - // by APPS_INT mask - -#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_INT_STS_RAW register. -// -//****************************************************************************** -#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_M \ - 0xFFFFFFFF // 1= corresponding interrupt is - // active. read is non-destructive;0 - // = corresponding interrupt is - // inactive - -#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_IDMEM_TIM_Updated register. -// -//****************************************************************************** -#define COMMON_REG_IDMEM_TIM_Updated_TIM_UPDATED \ - 0x00000001 // toggle in this signal - // indicatesIDMEM_TIM_UPDATE - // register mentioned above is - // updated. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_APPS_GPIO_TRIG_EN register. -// -//****************************************************************************** -#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_M \ - 0x0000001F // APPS GPIO Trigger EN control. - // Bit 0: when '1' enable GPIO 0 - // trigger. This bit enables trigger - // for all GPIO 0 pins (GPIO 0 to - // GPIO7). Bit 1: when '1' enable - // GPIO 1 trigger. This bit enables - // trigger for all GPIO 1 pins ( - // GPIO8 to GPIO15). Bit 2: when '1' - // enable GPIO 2 trigger. This bit - // enables trigger for all GPIO 2 - // pins (GPIO16 to GPIO23). Bit 3: - // when '1' enable GPIO 3 trigger. - // This bit enables trigger for all - // GPIO 3 pins (GPIO24 to GPIO31). - // Bit 4: when '1' enable GPIO 4 - // trigger. This bit enables trigger - // for all GPIO 4 pins.(GPIO32 to - // GPIO39) - -#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_EMU_DEBUG_REG register. -// -//****************************************************************************** -#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_M \ - 0xFFFFFFFF // 0 th bit used for stalling APPS - // DMA and 1st bit is used for - // stalling NWP DMA for debug - // purpose. Other bits are unused. - -#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_SEMAPHORE_STATUS2 register. -// -//****************************************************************************** -#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_M \ - 0x00FFFFFF // SEMAPHORE STATUS 23:22 - // :semaphore status of - // apps_nw_semaphore11 21:20 - // :semaphore status of - // apps_nw_semaphore11 19:18 - // :semaphore status of - // apps_nw_semaphore10 17:16 - // :semaphore status of - // apps_nw_semaphore9 15:14 - // :semaphore status of - // apps_nw_semaphore8 13:12 - // :semaphore status of - // apps_nw_semaphore7 11:10 - // :semaphore status of - // apps_nw_semaphore6 9:8 :semaphore - // status of apps_nw_semaphore5 7:6 - // :semaphore status of - // apps_nw_semaphore4 5:4 :semaphore - // status of apps_nw_semaphore3 3:2 - // :semaphore status of - // apps_nw_semaphore2 1:0 :semaphore - // status of apps_nw_semaphore1 - -#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_SEMAPHORE_PREV_OWNER1 register. -// -//****************************************************************************** -#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_M \ - 0x0003FFFF // 1:0 : prvious owner of - // i2c_properties_reg[1:0] 3:2 : - // prvious owner of - // spi_properties_reg[1:0] 5:4 : - // prvious owner of - // gpio_properties_reg[1:0] 9:8 : - // prvious owner of - // gpio_properties_reg[3:2] 11:10 : - // prvious owner of - // gpio_properties_reg[5:4] 13:12 : - // prvious owner of - // gpio_properties_reg[7:6] 15:14 : - // prvious owner of - // gpio_properties_reg[9:8] 17:16 : - // prvious owner of - // flash_control_reg[1:0] - -#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// COMMON_REG_O_SEMAPHORE_PREV_OWNER2 register. -// -//****************************************************************************** -#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_M \ - 0x00FFFFFF // 1:0 : previous owner of - // apps_nw_semaphore1_reg[1:0] 3:2 : - // previous owner of - // apps_nw_semaphore2_reg[1:0] 5:4 : - // previous owner of - // apps_nw_semaphore3_reg[1:0] 7:6 : - // previous owner of - // apps_nw_semaphore4_reg[1:0] 9:8 : - // previous owner of - // apps_nw_semaphore5_reg[1:0] 11:10 - // : previous owner of - // apps_nw_semaphore6_reg[1:0] 13:12 - // : previous owner of - // apps_nw_semaphore7_reg[1:0] 15:14 - // : previous owner of - // apps_nw_semaphore8_reg[1:0] 17:16 - // : previous owner of - // apps_nw_semaphore9_reg[1:0] 19:18 - // : previous owner of - // apps_nw_semaphore10_reg[1:0] - // 21:20 : previous owner of - // apps_nw_semaphore11_reg[1:0] - // 23:22 : previous owner of - // apps_nw_semaphore12_reg[1:0] - -#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_S 0 - - - -#endif // __HW_COMMON_REG_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_des.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_des.h deleted file mode 100644 index 7d8de2c32fc..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_des.h +++ /dev/null @@ -1,337 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_DES_H__ -#define __HW_DES_H__ - -//***************************************************************************** -// -// The following are defines for the DES_P register offsets. -// -//***************************************************************************** -#define DES_O_KEY3_L 0x00000000 // KEY3 (LSW) for 192-bit key -#define DES_O_KEY3_H 0x00000004 // KEY3 (MSW) for 192-bit key -#define DES_O_KEY2_L 0x00000008 // KEY2 (LSW) for 192-bit key -#define DES_O_KEY2_H 0x0000000C // KEY2 (MSW) for 192-bit key -#define DES_O_KEY1_L 0x00000010 // KEY1 (LSW) for 128-bit - // key/192-bit key -#define DES_O_KEY1_H 0x00000014 // KEY1 (LSW) for 128-bit - // key/192-bit key -#define DES_O_IV_L 0x00000018 // Initialization vector LSW -#define DES_O_IV_H 0x0000001C // Initialization vector MSW -#define DES_O_CTRL 0x00000020 -#define DES_O_LENGTH 0x00000024 // Indicates the cryptographic data - // length in bytes for all modes. - // Once processing is started with - // this context this length - // decrements to zero. Data lengths - // up to (2^32 – 1) bytes are - // allowed. A write to this register - // triggers the engine to start - // using this context. For a Host - // read operation these registers - // return all-zeroes. -#define DES_O_DATA_L 0x00000028 // Data register(LSW) to read/write - // encrypted/decrypted data. -#define DES_O_DATA_H 0x0000002C // Data register(MSW) to read/write - // encrypted/decrypted data. -#define DES_O_REVISION 0x00000030 -#define DES_O_SYSCONFIG 0x00000034 -#define DES_O_SYSSTATUS 0x00000038 -#define DES_O_IRQSTATUS 0x0000003C // This register indicates the - // interrupt status. If one of the - // interrupt bits is set the - // interrupt output will be asserted -#define DES_O_IRQENABLE 0x00000040 // This register contains an enable - // bit for each unique interrupt - // generated by the module. It - // matches the layout of - // DES_IRQSTATUS register. An - // interrupt is enabled when the bit - // in this register is set to 1 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY3_L register. -// -//****************************************************************************** -#define DES_KEY3_L_KEY3_L_M 0xFFFFFFFF // data for key3 -#define DES_KEY3_L_KEY3_L_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY3_H register. -// -//****************************************************************************** -#define DES_KEY3_H_KEY3_H_M 0xFFFFFFFF // data for key3 -#define DES_KEY3_H_KEY3_H_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY2_L register. -// -//****************************************************************************** -#define DES_KEY2_L_KEY2_L_M 0xFFFFFFFF // data for key2 -#define DES_KEY2_L_KEY2_L_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY2_H register. -// -//****************************************************************************** -#define DES_KEY2_H_KEY2_H_M 0xFFFFFFFF // data for key2 -#define DES_KEY2_H_KEY2_H_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY1_L register. -// -//****************************************************************************** -#define DES_KEY1_L_KEY1_L_M 0xFFFFFFFF // data for key1 -#define DES_KEY1_L_KEY1_L_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_KEY1_H register. -// -//****************************************************************************** -#define DES_KEY1_H_KEY1_H_M 0xFFFFFFFF // data for key1 -#define DES_KEY1_H_KEY1_H_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IV_L register. -// -//****************************************************************************** -#define DES_IV_L_IV_L_M 0xFFFFFFFF // initialization vector for CBC - // CFB modes -#define DES_IV_L_IV_L_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IV_H register. -// -//****************************************************************************** -#define DES_IV_H_IV_H_M 0xFFFFFFFF // initialization vector for CBC - // CFB modes -#define DES_IV_H_IV_H_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_CTRL register. -// -//****************************************************************************** -#define DES_CTRL_CONTEXT 0x80000000 // If ‘1’ this read-only status bit - // indicates that the context data - // registers can be overwritten and - // the host is permitted to write - // the next context. -#define DES_CTRL_MODE_M 0x00000030 // Select CBC ECB or CFB mode 0x0 - // ecb mode 0x1 cbc mode 0x2 cfb - // mode 0x3 reserved -#define DES_CTRL_MODE_S 4 -#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES - // encryption/decryption. 0 des mode - // 1 tdes mode -#define DES_CTRL_DIRECTION 0x00000004 // select encryption/decryption 0 - // decryption is selected 1 - // Encryption is selected -#define DES_CTRL_INPUT_READY 0x00000002 // When '1' ready to - // encrypt/decrypt data -#define DES_CTRL_OUTPUT_READY 0x00000001 // When '1' Data - // decrypted/encrypted ready -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_LENGTH register. -// -//****************************************************************************** -#define DES_LENGTH_LENGTH_M 0xFFFFFFFF -#define DES_LENGTH_LENGTH_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DATA_L register. -// -//****************************************************************************** -#define DES_DATA_L_DATA_L_M 0xFFFFFFFF // data for encryption/decryption -#define DES_DATA_L_DATA_L_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_DATA_H register. -// -//****************************************************************************** -#define DES_DATA_H_DATA_H_M 0xFFFFFFFF // data for encryption/decryption -#define DES_DATA_H_DATA_H_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_REVISION register. -// -//****************************************************************************** -#define DES_REVISION_SCHEME_M 0xC0000000 -#define DES_REVISION_SCHEME_S 30 -#define DES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software - // compatible module family. If - // there is no level of software - // compatibility a new Func number - // (and hence REVISION) should be - // assigned. -#define DES_REVISION_FUNC_S 16 -#define DES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP - // design owner. RTL follows a - // numbering such as X.Y.R.Z which - // are explained in this table. R - // changes ONLY when: (1) PDS - // uploads occur which may have been - // due to spec changes (2) Bug fixes - // occur (3) Resets to '0' when X or - // Y changes. Design team has an - // internal 'Z' (customer invisible) - // number which increments on every - // drop that happens due to DV and - // RTL updates. Z resets to 0 when R - // increments. -#define DES_REVISION_R_RTL_S 11 -#define DES_REVISION_X_MAJOR_M \ - 0x00000700 // Major Revision (X) maintained by - // IP specification owner. X changes - // ONLY when: (1) There is a major - // feature addition. An example - // would be adding Master Mode to - // Utopia Level2. The Func field (or - // Class/Type in old PID format) - // will remain the same. X does NOT - // change due to: (1) Bug fixes (2) - // Change in feature parameters. - -#define DES_REVISION_X_MAJOR_S 8 -#define DES_REVISION_CUSTOM_M 0x000000C0 -#define DES_REVISION_CUSTOM_S 6 -#define DES_REVISION_Y_MINOR_M \ - 0x0000003F // Minor Revision (Y) maintained by - // IP specification owner. Y changes - // ONLY when: (1) Features are - // scaled (up or down). Flexibility - // exists in that this feature - // scalability may either be - // represented in the Y change or a - // specific register in the IP that - // indicates which features are - // exactly available. (2) When - // feature creeps from Is-Not list - // to Is list. But this may not be - // the case once it sees silicon; in - // which case X will change. Y does - // NOT change due to: (1) Bug fixes - // (2) Typos or clarifications (3) - // major functional/feature - // change/addition/deletion. Instead - // these changes may be reflected - // via R S X as applicable. Spec - // owner maintains a - // customer-invisible number 'S' - // which changes due to: (1) - // Typos/clarifications (2) Bug - // documentation. Note that this bug - // is not due to a spec change but - // due to implementation. - // Nevertheless the spec tracks the - // IP bugs. An RTL release (say for - // silicon PG1.1) that occurs due to - // bug fix should document the - // corresponding spec number (X.Y.S) - // in its release notes. - -#define DES_REVISION_Y_MINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_SYSCONFIG register. -// -//****************************************************************************** -#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ - 0x00000080 // If set to ‘1’ the DMA context - // request is enabled. 0 Dma - // disabled 1 Dma enabled - -#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ - 0x00000040 // If set to ‘1’ the DMA output - // request is enabled. 0 Dma - // disabled 1 Dma enabled - -#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ - 0x00000020 // If set to ‘1’ the DMA input - // request is enabled. 0 Dma - // disabled 1 Dma enabled - -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_SYSSTATUS register. -// -//****************************************************************************** -#define DES_SYSSTATUS_RESETDONE \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IRQSTATUS register. -// -//****************************************************************************** -#define DES_IRQSTATUS_DATA_OUT \ - 0x00000004 // This bit indicates data output - // interrupt is active and triggers - // the interrupt output. - -#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input - // interrupt is active and triggers - // the interrupt output. -#define DES_IRQSTATUS_CONTEX_IN \ - 0x00000001 // This bit indicates context - // interrupt is active and triggers - // the interrupt output. - -//****************************************************************************** -// -// The following are defines for the bit fields in the DES_O_IRQENABLE register. -// -//****************************************************************************** -#define DES_IRQENABLE_M_DATA_OUT \ - 0x00000004 // If this bit is set to ‘1’ the - // secure data output interrupt is - // enabled. - -#define DES_IRQENABLE_M_DATA_IN \ - 0x00000002 // If this bit is set to ‘1’ the - // secure data input interrupt is - // enabled. - -#define DES_IRQENABLE_M_CONTEX_IN \ - 0x00000001 // If this bit is set to ‘1’ the - // secure context interrupt is - // enabled. - - - - -#endif // __HW_DES_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_dthe.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_dthe.h deleted file mode 100644 index fa5d39450aa..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_dthe.h +++ /dev/null @@ -1,390 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -//***************************************************************************** - -#ifndef __HW_DTHE_H__ -#define __HW_DTHE_H__ - -//***************************************************************************** -// -// The following are defines for the DTHE register offsets. -// -//***************************************************************************** -#define DTHE_O_SHA_IM 0x00000810 -#define DTHE_O_SHA_RIS 0x00000814 -#define DTHE_O_SHA_MIS 0x00000818 -#define DTHE_O_SHA_IC 0x0000081C -#define DTHE_O_AES_IM 0x00000820 -#define DTHE_O_AES_RIS 0x00000824 -#define DTHE_O_AES_MIS 0x00000828 -#define DTHE_O_AES_IC 0x0000082C -#define DTHE_O_DES_IM 0x00000830 -#define DTHE_O_DES_RIS 0x00000834 -#define DTHE_O_DES_MIS 0x00000838 -#define DTHE_O_DES_IC 0x0000083C -#define DTHE_O_EIP_CGCFG 0x00000A00 -#define DTHE_O_EIP_CGREQ 0x00000A04 -#define DTHE_O_CRC_CTRL 0x00000C00 -#define DTHE_O_CRC_SEED 0x00000C10 -#define DTHE_O_CRC_DIN 0x00000C14 -#define DTHE_O_CRC_RSLT_PP 0x00000C18 -#define DTHE_O_RAND_KEY0 0x00000F00 -#define DTHE_O_RAND_KEY1 0x00000F04 -#define DTHE_O_RAND_KEY2 0x00000F08 -#define DTHE_O_RAND_KEY3 0x00000F0C - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_SHAMD5_IMST register. -// -//****************************************************************************** -#define DTHE_SHAMD5_IMST_DIN 0x00000004 // Data in: this interrupt is - // raised when DMA writes last word - // of input data to internal FIFO of - // the engine -#define DTHE_SHAMD5_IMST_COUT 0x00000002 // Context out: this interrupt is - // raised when DMA complets the - // output context movement from - // internal register -#define DTHE_SHAMD5_IMST_CIN 0x00000001 // context in: this interrupt is - // raised when DMA complets Context - // write to internal register -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_SHAMD5_IRIS register. -// -//****************************************************************************** -#define DTHE_SHAMD5_IRIS_DIN 0x00000004 // input Data movement is done -#define DTHE_SHAMD5_IRIS_COUT 0x00000002 // Context output is done -#define DTHE_SHAMD5_IRIS_CIN 0x00000001 // context input is done -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_SHAMD5_IMIS register. -// -//****************************************************************************** -#define DTHE_SHAMD5_IMIS_DIN 0x00000004 // input Data movement is done -#define DTHE_SHAMD5_IMIS_COUT 0x00000002 // Context output is done -#define DTHE_SHAMD5_IMIS_CIN 0x00000001 // context input is done -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_SHAMD5_ICIS register. -// -//****************************************************************************** -#define DTHE_SHAMD5_ICIS_DIN 0x00000004 // Clear “input Data movement done� - // flag -#define DTHE_SHAMD5_ICIS_COUT 0x00000002 // Clear “Context output done� flag -#define DTHE_SHAMD5_ICIS_CIN 0x00000001 // Clear “context input done� flag -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_AES_IMST register. -// -//****************************************************************************** -#define DTHE_AES_IMST_DOUT 0x00000008 // Data out: this interrupt is - // raised when DMA finishes writing - // last word of the process result -#define DTHE_AES_IMST_DIN 0x00000004 // Data in: this interrupt is - // raised when DMA writes last word - // of input data to internal FIFO of - // the engine -#define DTHE_AES_IMST_COUT 0x00000002 // Context out: this interrupt is - // raised when DMA complets the - // output context movement from - // internal register -#define DTHE_AES_IMST_CIN 0x00000001 // context in: this interrupt is - // raised when DMA complets Context - // write to internal register -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_AES_IRIS register. -// -//****************************************************************************** -#define DTHE_AES_IRIS_DOUT 0x00000008 // Output Data movement is done -#define DTHE_AES_IRIS_DIN 0x00000004 // input Data movement is done -#define DTHE_AES_IRIS_COUT 0x00000002 // Context output is done -#define DTHE_AES_IRIS_CIN 0x00000001 // context input is done -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_AES_IMIS register. -// -//****************************************************************************** -#define DTHE_AES_IMIS_DOUT 0x00000008 // Output Data movement is done -#define DTHE_AES_IMIS_DIN 0x00000004 // input Data movement is done -#define DTHE_AES_IMIS_COUT 0x00000002 // Context output is done -#define DTHE_AES_IMIS_CIN 0x00000001 // context input is done -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_AES_ICIS register. -// -//****************************************************************************** -#define DTHE_AES_ICIS_DOUT 0x00000008 // Clear “output Data movement - // done� flag -#define DTHE_AES_ICIS_DIN 0x00000004 // Clear “input Data movement done� - // flag -#define DTHE_AES_ICIS_COUT 0x00000002 // Clear “Context output done� flag -#define DTHE_AES_ICIS_CIN 0x00000001 // Clear “context input done� flag -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_DES_IMST register. -// -//****************************************************************************** -#define DTHE_DES_IMST_DOUT 0x00000008 // Data out: this interrupt is - // raised when DMA finishes writing - // last word of the process result -#define DTHE_DES_IMST_DIN 0x00000004 // Data in: this interrupt is - // raised when DMA writes last word - // of input data to internal FIFO of - // the engine -#define DTHE_DES_IMST_CIN 0x00000001 // context in: this interrupt is - // raised when DMA complets Context - // write to internal register -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_DES_IRIS register. -// -//****************************************************************************** -#define DTHE_DES_IRIS_DOUT 0x00000008 // Output Data movement is done -#define DTHE_DES_IRIS_DIN 0x00000004 // input Data movement is done -#define DTHE_DES_IRIS_CIN 0x00000001 // context input is done -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_DES_IMIS register. -// -//****************************************************************************** -#define DTHE_DES_IMIS_DOUT 0x00000008 // Output Data movement is done -#define DTHE_DES_IMIS_DIN 0x00000004 // input Data movement is done -#define DTHE_DES_IMIS_CIN 0x00000001 // context input is done -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_DES_ICIS register. -// -//****************************************************************************** -#define DTHE_DES_ICIS_DOUT 0x00000008 // Clear “output Data movement - // done� flag -#define DTHE_DES_ICIS_DIN 0x00000004 // Clear “input Data movement done� - // flag -#define DTHE_DES_ICIS_CIN 0x00000001 // Clear "context input done� flag -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_EIP_CGCFG register. -// -//****************************************************************************** -#define DTHE_EIP_CGCFG_EIP29_CFG \ - 0x00000010 // Clock gating protocol setting - // for EIP29T. 0 – Follow direct - // protocol 1 – Follow idle_req/ack - // protocol. - -#define DTHE_EIP_CGCFG_EIP75_CFG \ - 0x00000008 // Clock gating protocol setting - // for EIP75T. 0 – Follow direct - // protocol 1 – Follow idle_req/ack - // protocol. - -#define DTHE_EIP_CGCFG_EIP16_CFG \ - 0x00000004 // Clock gating protocol setting - // for DES. 0 – Follow direct - // protocol 1 – Follow idle_req/ack - // protocol. - -#define DTHE_EIP_CGCFG_EIP36_CFG \ - 0x00000002 // Clock gating protocol setting - // for AES. 0 – Follow direct - // protocol 1 – Follow idle_req/ack - // protocol. - -#define DTHE_EIP_CGCFG_EIP57_CFG \ - 0x00000001 // Clock gating protocol setting - // for SHAMD5. 0 – Follow direct - // protocol 1 – Follow idle_req/ack - // protocol. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_EIP_CGREQ register. -// -//****************************************************************************** -#define DTHE_EIP_CGREQ_Key_M 0xF0000000 // When “0x5� write “1� to lower - // bits [4:0] will set the bit. - // Write “0� will be ignored When - // “0x2� write “1� to lower bit - // [4:0] will clear the bit. Write - // “0� will be ignored for other key - // value, regular read write - // operation -#define DTHE_EIP_CGREQ_Key_S 28 -#define DTHE_EIP_CGREQ_EIP29_REQ \ - 0x00000010 // 0 – request clock gating 1 – - // request to un-gate the clock. - -#define DTHE_EIP_CGREQ_EIP75_REQ \ - 0x00000008 // 0 – request clock gating 1 – - // request to un-gate the clock. - -#define DTHE_EIP_CGREQ_EIP16_REQ \ - 0x00000004 // 0 – request clock gating 1 – - // request to un-gate the clock. - -#define DTHE_EIP_CGREQ_EIP36_REQ \ - 0x00000002 // 0 – request clock gating 1 – - // request to un-gate the clock. - -#define DTHE_EIP_CGREQ_EIP57_REQ \ - 0x00000001 // 0 – request clock gating 1 – - // request to un-gate the clock. - -//****************************************************************************** -// -// The following are defines for the bit fields in the DTHE_O_CRC_CTRL register. -// -//****************************************************************************** -#define DTHE_CRC_CTRL_INIT_M 0x00006000 // Initialize the CRC 00 – use SEED - // register context as starting - // value 10 – all “zero� 11 – all - // “one� This is self clearing. With - // first write to data register this - // value clears to zero and remain - // zero for rest of the operation - // unless written again -#define DTHE_CRC_CTRL_INIT_S 13 -#define DTHE_CRC_CTRL_SIZE 0x00001000 // Input data size 0 – 32 bit 1 – 8 - // bit -#define DTHE_CRC_CTRL_OINV 0x00000200 // Inverse the bits of result - // before storing to CRC_RSLT_PP0 -#define DTHE_CRC_CTRL_OBR 0x00000100 // Bit reverse the output result - // byte before storing to - // CRC_RSLT_PP0. applicable for all - // bytes in word -#define DTHE_CRC_CTRL_IBR 0x00000080 // Bit reverse the input byte. For - // all bytes in word -#define DTHE_CRC_CTRL_ENDIAN_M \ - 0x00000030 // Endian control [0] – swap byte - // in half-word [1] – swap half word - -#define DTHE_CRC_CTRL_ENDIAN_S 4 -#define DTHE_CRC_CTRL_TYPE_M 0x0000000F // Type of operation 0000 – - // polynomial 0x8005 0001 – - // polynomial 0x1021 0010 – - // polynomial 0x4C11DB7 0011 – - // polynomial 0x1EDC6F41 1000 – TCP - // checksum TYPE in DTHE_S_CRC_CTRL - // & DTHE_S_CRC_CTRL should be - // exclusive -#define DTHE_CRC_CTRL_TYPE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DTHE_O_CRC_SEED register. -// -//****************************************************************************** -#define DTHE_CRC_SEED_SEED_M 0xFFFFFFFF // Starting seed of CRC and - // checksum operation. Please see - // CTRL register for more detail. - // This resister also holds the - // latest result of CRC or checksum - // operation -#define DTHE_CRC_SEED_SEED_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the DTHE_O_CRC_DIN register. -// -//****************************************************************************** -#define DTHE_CRC_DIN_DATA_IN_M \ - 0xFFFFFFFF // Input data for CRC or checksum - // operation - -#define DTHE_CRC_DIN_DATA_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_CRC_RSLT_PP register. -// -//****************************************************************************** -#define DTHE_CRC_RSLT_PP_RSLT_PP_M \ - 0xFFFFFFFF // Input data for CRC or checksum - // operation - -#define DTHE_CRC_RSLT_PP_RSLT_PP_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_RAND_KEY0 register. -// -//****************************************************************************** -#define DTHE_RAND_KEY0_KEY_M 0xFFFFFFFF // Device Specific Randon key - // [31:0] -#define DTHE_RAND_KEY0_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_RAND_KEY1 register. -// -//****************************************************************************** -#define DTHE_RAND_KEY1_KEY_M 0xFFFFFFFF // Device Specific Randon key - // [63:32] -#define DTHE_RAND_KEY1_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_RAND_KEY2 register. -// -//****************************************************************************** -#define DTHE_RAND_KEY2_KEY_M 0xFFFFFFFF // Device Specific Randon key - // [95:34] -#define DTHE_RAND_KEY2_KEY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// DTHE_O_RAND_KEY3 register. -// -//****************************************************************************** -#define DTHE_RAND_KEY3_KEY_M 0xFFFFFFFF // Device Specific Randon key - // [127:96] -#define DTHE_RAND_KEY3_KEY_S 0 - - - -#endif // __HW_DTHE_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_flash_ctrl.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_flash_ctrl.h deleted file mode 100644 index ba68c123949..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_flash_ctrl.h +++ /dev/null @@ -1,1860 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_FLASH_CTRL_H__ -#define __HW_FLASH_CTRL_H__ - -//***************************************************************************** -// -// The following are defines for the FLASH_CTRL register offsets. -// -//***************************************************************************** -#define FLASH_CTRL_O_FMA 0x00000000 // Flash Memory Address (FMA) - // offset 0x000 During a write - // operation this register contains - // a 4-byte-aligned address and - // specifies where the data is - // written. During erase operations - // this register contains a 1 - // KB-aligned CPU byte address and - // specifies which block is erased. - // Note that the alignment - // requirements must be met by - // software or the results of the - // operation are unpredictable. -#define FLASH_CTRL_O_FMD 0x00000004 // Flash Memory Data (FMD) offset - // 0x004 This register contains the - // data to be written during the - // programming cycle or read during - // the read cycle. Note that the - // contents of this register are - // undefined for a read access of an - // execute-only block. This register - // is not used during erase cycles. -#define FLASH_CTRL_O_FMC 0x00000008 // Flash Memory Control (FMC) - // offset 0x008 When this register - // is written the Flash memory - // controller initiates the - // appropriate access cycle for the - // location specified by the Flash - // Memory Address (FMA) register . - // If the access is a write access - // the data contained in the Flash - // Memory Data (FMD) register is - // written to the specified address. - // This register must be the final - // register written and initiates - // the memory operation. The four - // control bits in the lower byte of - // this register are used to - // initiate memory operations. -#define FLASH_CTRL_O_FCRIS 0x0000000C // Flash Controller Raw Interrupt - // Status (FCRIS) offset 0x00C This - // register indicates that the Flash - // memory controller has an - // interrupt condition. An interrupt - // is sent to the interrupt - // controller only if the - // corresponding FCIM register bit - // is set. -#define FLASH_CTRL_O_FCIM 0x00000010 // Flash Controller Interrupt Mask - // (FCIM) offset 0x010 This register - // controls whether the Flash memory - // controller generates interrupts - // to the controller. -#define FLASH_CTRL_O_FCMISC 0x00000014 // Flash Controller Masked - // Interrupt Status and Clear - // (FCMISC) offset 0x014 This - // register provides two functions. - // First it reports the cause of an - // interrupt by indicating which - // interrupt source or sources are - // signalling the interrupt. Second - // it serves as the method to clear - // the interrupt reporting. -#define FLASH_CTRL_O_FMC2 0x00000020 // Flash Memory Control 2 (FMC2) - // offset 0x020 When this register - // is written the Flash memory - // controller initiates the - // appropriate access cycle for the - // location specified by the Flash - // Memory Address (FMA) register . - // If the access is a write access - // the data contained in the Flash - // Write Buffer (FWB) registers is - // written. This register must be - // the final register written as it - // initiates the memory operation. -#define FLASH_CTRL_O_FWBVAL 0x00000030 // Flash Write Buffer Valid - // (FWBVAL) offset 0x030 This - // register provides a bitwise - // status of which FWBn registers - // have been written by the - // processor since the last write of - // the Flash memory write buffer. - // The entries with a 1 are written - // on the next write of the Flash - // memory write buffer. This - // register is cleared after the - // write operation by hardware. A - // protection violation on the write - // operation also clears this - // status. Software can program the - // same 32 words to various Flash - // memory locations by setting the - // FWB[n] bits after they are - // cleared by the write operation. - // The next write operation then - // uses the same data as the - // previous one. In addition if a - // FWBn register change should not - // be written to Flash memory - // software can clear the - // corresponding FWB[n] bit to - // preserve the existing data when - // the next write operation occurs. -#define FLASH_CTRL_O_FWB1 0x00000100 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB2 0x00000104 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB3 0x00000108 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB4 0x0000010C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB5 0x00000110 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB6 0x00000114 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB7 0x00000118 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB8 0x0000011C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB9 0x00000120 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB10 0x00000124 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB11 0x00000128 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB12 0x0000012C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB13 0x00000130 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB14 0x00000134 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB15 0x00000138 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB16 0x0000013C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB17 0x00000140 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB18 0x00000144 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB19 0x00000148 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB20 0x0000014C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB21 0x00000150 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB22 0x00000154 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB23 0x00000158 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB24 0x0000015C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB25 0x00000160 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB26 0x00000164 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB27 0x00000168 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB28 0x0000016C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB29 0x00000170 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB30 0x00000174 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB31 0x00000178 // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FWB32 0x0000017C // Flash Write Buffer n (FWBn) - // offset 0x100 - 0x17C These 32 - // registers hold the contents of - // the data to be written into the - // Flash memory on a buffered Flash - // memory write operation. The - // offset selects one of the 32-bit - // registers. Only FWBn registers - // that have been updated since the - // preceding buffered Flash memory - // write operation are written into - // the Flash memory so it is not - // necessary to write the entire - // bank of registers in order to - // write 1 or 2 words. The FWBn - // registers are written into the - // Flash memory with the FWB0 - // register corresponding to the - // address contained in FMA. FWB1 is - // written to the address FMA+0x4 - // etc. Note that only data bits - // that are 0 result in the Flash - // memory being modified. A data bit - // that is 1 leaves the content of - // the Flash memory bit at its - // previous value. -#define FLASH_CTRL_O_FSIZE 0x00000FC0 // Flash Size (FSIZE) offset 0xFC0 - // This register indicates the size - // of the on-chip Flash memory. - // Important: This register should - // be used to determine the size of - // the Flash memory that is - // implemented on this - // microcontroller. However to - // support legacy software the DC0 - // register is available. A read of - // the DC0 register correctly - // identifies legacy memory sizes. - // Software must use the FSIZE - // register for memory sizes that - // are not listed in the DC0 - // register description. -#define FLASH_CTRL_O_SSIZE 0x00000FC4 // SRAM Size (SSIZE) offset 0xFC4 - // This register indicates the size - // of the on-chip SRAM. Important: - // This register should be used to - // determine the size of the SRAM - // that is implemented on this - // microcontroller. However to - // support legacy software the DC0 - // register is available. A read of - // the DC0 register correctly - // identifies legacy memory sizes. - // Software must use the SSIZE - // register for memory sizes that - // are not listed in the DC0 - // register description. - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FMA register. -// -//****************************************************************************** -#define FLASH_CTRL_FMA_OFFSET_M 0x0003FFFF // Address Offset Address offset in - // Flash memory where operation is - // performed except for nonvolatile - // registers -#define FLASH_CTRL_FMA_OFFSET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FMD register. -// -//****************************************************************************** -#define FLASH_CTRL_FMD_DATA_M 0xFFFFFFFF // Data Value Data value for write - // operation. -#define FLASH_CTRL_FMD_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FMC register. -// -//****************************************************************************** -#define FLASH_CTRL_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This - // field contains a write key which - // is used to minimize the incidence - // of accidental Flash memory - // writes. The value 0xA442 must be - // written into this field for a - // Flash memory write to occur. - // Writes to the FMC register - // without this WRKEY value are - // ignored. A read of this field - // returns the value 0. -#define FLASH_CTRL_FMC_WRKEY_S 16 -#define FLASH_CTRL_FMC_COMT 0x00000008 // Commit Register Value This bit - // is used to commit writes to - // Flash-memory-resident registers - // and to monitor the progress of - // that process. Value Description 1 - // Set this bit to commit (write) - // the register value to a - // Flash-memory-resident register. - // When read a 1 indicates that the - // previous commit access is not - // complete. 0 A write of 0 has no - // effect on the state of this bit. - // When read a 0 indicates that the - // previous commit access is - // complete. -#define FLASH_CTRL_FMC_MERASE1 0x00000004 // Mass Erase Flash Memory This bit - // is used to mass erase the Flash - // main memory and to monitor the - // progress of that process. Value - // Description 1 Set this bit to - // erase the Flash main memory. When - // read a 1 indicates that the - // previous mass erase access is not - // complete. 0 A write of 0 has no - // effect on the state of this bit. - // When read a 0 indicates that the - // previous mass erase access is - // complete. -#define FLASH_CTRL_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory - // This bit is used to erase a page - // of Flash memory and to monitor - // the progress of that process. - // Value Description 1 Set this bit - // to erase the Flash memory page - // specified by the contents of the - // FMA register. When read a 1 - // indicates that the previous page - // erase access is not complete. 0 A - // write of 0 has no effect on the - // state of this bit. When read a 0 - // indicates that the previous page - // erase access is complete. -#define FLASH_CTRL_FMC_WRITE 0x00000001 // Write a Word into Flash Memory - // This bit is used to write a word - // into Flash memory and to monitor - // the progress of that process. - // Value Description 1 Set this bit - // to write the data stored in the - // FMD register into the Flash - // memory location specified by the - // contents of the FMA register. - // When read a 1 indicates that the - // write update access is not - // complete. 0 A write of 0 has no - // effect on the state of this bit. - // When read a 0 indicates that the - // previous write update access is - // complete. -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FCRIS register. -// -//****************************************************************************** -#define FLASH_CTRL_FCRIS_PROGRIS \ - 0x00002000 // Program Verify Error Raw - // Interrupt Status Value - // Description 1 An interrupt is - // pending because the verify of a - // PROGRAM operation failed. 0 An - // interrupt has not occurred. This - // bit is cleared by writing a 1 to - // the PROGMISC bit in the FCMISC - // register. - -#define FLASH_CTRL_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt - // Status Value Description 1 An - // interrupt is pending because the - // verify of an ERASE operation - // failed. 0 An interrupt has not - // occurred. This bit is cleared by - // writing a 1 to the ERMISC bit in - // the FCMISC register. -#define FLASH_CTRL_FCRIS_INVDRIS \ - 0x00000400 // Invalid Data Raw Interrupt - // Status Value Description 1 An - // interrupt is pending because a - // bit that was previously - // programmed as a 0 is now being - // requested to be programmed as a - // 1. 0 An interrupt has not - // occurred. This bit is cleared by - // writing a 1 to the INVMISC bit in - // the FCMISC register. - -#define FLASH_CTRL_FCRIS_VOLTRIS \ - 0x00000200 // Pump Voltage Raw Interrupt - // Status Value Description 1 An - // interrupt is pending because the - // regulated voltage of the pump - // went out of spec during the Flash - // operation and the operation was - // terminated. 0 An interrupt has - // not occurred. This bit is cleared - // by writing a 1 to the VOLTMISC - // bit in the FCMISC register. - -#define FLASH_CTRL_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status This - // bit provides status EEPROM - // operation. Value Description 1 An - // EEPROM interrupt has occurred. 0 - // An EEPROM interrupt has not - // occurred. This bit is cleared by - // writing a 1 to the EMISC bit in - // the FCMISC register. -#define FLASH_CTRL_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status - // This bit provides status on - // programming cycles which are - // write or erase actions generated - // through the FMC or FMC2 register - // bits (see page 537 and page 549). - // Value Description 1 The - // programming or erase cycle has - // completed. 0 The programming or - // erase cycle has not completed. - // This status is sent to the - // interrupt controller when the - // PMASK bit in the FCIM register is - // set. This bit is cleared by - // writing a 1 to the PMISC bit in - // the FCMISC register. -#define FLASH_CTRL_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status - // Value Description 1 A program or - // erase action was attempted on a - // block of Flash memory that - // contradicts the protection policy - // for that block as set in the - // FMPPEn registers. 0 No access has - // tried to improperly program or - // erase the Flash memory. This - // status is sent to the interrupt - // controller when the AMASK bit in - // the FCIM register is set. This - // bit is cleared by writing a 1 to - // the AMISC bit in the FCMISC - // register. -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FCIM register. -// -//****************************************************************************** -#define FLASH_CTRL_FCIM_ILLMASK 0x00004000 // Illegal Address Interrupt Mask - // Value Description 1 An interrupt - // is sent to the interrupt - // controller when the ILLARIS bit - // is set. 0 The ILLARIS interrupt - // is suppressed and not sent to the - // interrupt controller. -#define FLASH_CTRL_FCIM_PROGMASK \ - 0x00002000 // PROGVER Interrupt Mask Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the PROGRIS bit is set. 0 - // The PROGRIS interrupt is - // suppressed and not sent to the - // interrupt controller. - -#define FLASH_CTRL_FCIM_PREMASK 0x00001000 // PREVER Interrupt Mask Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the PRERIS bit is set. 0 The - // PRERIS interrupt is suppressed - // and not sent to the interrupt - // controller. -#define FLASH_CTRL_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the ERRIS bit is set. 0 The - // ERRIS interrupt is suppressed and - // not sent to the interrupt - // controller. -#define FLASH_CTRL_FCIM_INVDMASK \ - 0x00000400 // Invalid Data Interrupt Mask - // Value Description 1 An interrupt - // is sent to the interrupt - // controller when the INVDRIS bit - // is set. 0 The INVDRIS interrupt - // is suppressed and not sent to the - // interrupt controller. - -#define FLASH_CTRL_FCIM_VOLTMASK \ - 0x00000200 // VOLT Interrupt Mask Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the VOLTRIS bit is set. 0 - // The VOLTRIS interrupt is - // suppressed and not sent to the - // interrupt controller. - -#define FLASH_CTRL_FCIM_LOCKMASK \ - 0x00000100 // LOCK Interrupt Mask Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the LOCKRIS bit is set. 0 - // The LOCKRIS interrupt is - // suppressed and not sent to the - // interrupt controller. - -#define FLASH_CTRL_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the ERIS bit is set. 0 The - // ERIS interrupt is suppressed and - // not sent to the interrupt - // controller. -#define FLASH_CTRL_FCIM_PMASK 0x00000002 // Programming Interrupt Mask This - // bit controls the reporting of the - // programming raw interrupt status - // to the interrupt controller. - // Value Description 1 An interrupt - // is sent to the interrupt - // controller when the PRIS bit is - // set. 0 The PRIS interrupt is - // suppressed and not sent to the - // interrupt controller. -#define FLASH_CTRL_FCIM_AMASK 0x00000001 // Access Interrupt Mask This bit - // controls the reporting of the - // access raw interrupt status to - // the interrupt controller. Value - // Description 1 An interrupt is - // sent to the interrupt controller - // when the ARIS bit is set. 0 The - // ARIS interrupt is suppressed and - // not sent to the interrupt - // controller. -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FCMISC register. -// -//****************************************************************************** -#define FLASH_CTRL_FCMISC_ILLMISC \ - 0x00004000 // Illegal Address Masked Interrupt - // Status and Clear Value - // Description 1 When read a 1 - // indicates that an unmasked - // interrupt was signaled. Writing a - // 1 to this bit clears ILLAMISC and - // also the ILLARIS bit in the FCRIS - // register (see page 540). 0 When - // read a 0 indicates that an - // interrupt has not occurred. A - // write of 0 has no effect on the - // state of this bit. - -#define FLASH_CTRL_FCMISC_PROGMISC \ - 0x00002000 // PROGVER Masked Interrupt Status - // and Clear Value Description 1 - // When read a 1 indicates that an - // unmasked interrupt was signaled. - // Writing a 1 to this bit clears - // PROGMISC and also the PROGRIS bit - // in the FCRIS register (see page - // 540). 0 When read a 0 indicates - // that an interrupt has not - // occurred. A write of 0 has no - // effect on the state of this bit. - -#define FLASH_CTRL_FCMISC_PREMISC \ - 0x00001000 // PREVER Masked Interrupt Status - // and Clear Value Description 1 - // When read a 1 indicates that an - // unmasked interrupt was signaled. - // Writing a 1 to this bit clears - // PREMISC and also the PRERIS bit - // in the FCRIS register . 0 When - // read a 0 indicates that an - // interrupt has not occurred. A - // write of 0 has no effect on the - // state of this bit. - -#define FLASH_CTRL_FCMISC_ERMISC \ - 0x00000800 // ERVER Masked Interrupt Status - // and Clear Value Description 1 - // When read a 1 indicates that an - // unmasked interrupt was signaled. - // Writing a 1 to this bit clears - // ERMISC and also the ERRIS bit in - // the FCRIS register 0 When read a - // 0 indicates that an interrupt has - // not occurred. A write of 0 has no - // effect on the state of this bit. - -#define FLASH_CTRL_FCMISC_INVDMISC \ - 0x00000400 // Invalid Data Masked Interrupt - // Status and Clear Value - // Description 1 When read a 1 - // indicates that an unmasked - // interrupt was signaled. Writing a - // 1 to this bit clears INVDMISC and - // also the INVDRIS bit in the FCRIS - // register (see page 540). 0 When - // read a 0 indicates that an - // interrupt has not occurred. A - // write of 0 has no effect on the - // state of this bit. - -#define FLASH_CTRL_FCMISC_VOLTMISC \ - 0x00000200 // VOLT Masked Interrupt Status and - // Clear Value Description 1 When - // read a 1 indicates that an - // unmasked interrupt was signaled. - // Writing a 1 to this bit clears - // VOLTMISC and also the VOLTRIS bit - // in the FCRIS register (see page - // 540). 0 When read a 0 indicates - // that an interrupt has not - // occurred. A write of 0 has no - // effect on the state of this bit. - -#define FLASH_CTRL_FCMISC_LOCKMISC \ - 0x00000100 // LOCK Masked Interrupt Status and - // Clear Value Description 1 When - // read a 1 indicates that an - // unmasked interrupt was signaled. - // Writing a 1 to this bit clears - // LOCKMISC and also the LOCKRIS bit - // in the FCRIS register (see page - // 540). 0 When read a 0 indicates - // that an interrupt has not - // occurred. A write of 0 has no - // effect on the state of this bit. - -#define FLASH_CTRL_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status - // and Clear Value Description 1 - // When read a 1 indicates that an - // unmasked interrupt was signaled. - // Writing a 1 to this bit clears - // EMISC and also the ERIS bit in - // the FCRIS register 0 When read a - // 0 indicates that an interrupt has - // not occurred. A write of 0 has no - // effect on the state of this bit. -#define FLASH_CTRL_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt - // Status and Clear Value - // Description 1 When read a 1 - // indicates that an unmasked - // interrupt was signaled because a - // programming cycle completed. - // Writing a 1 to this bit clears - // PMISC and also the PRIS bit in - // the FCRIS register 0 When read a - // 0 indicates that a programming - // cycle complete interrupt has not - // occurred. A write of 0 has no - // effect on the state of this bit. -#define FLASH_CTRL_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status - // and Clear Value Description 1 - // When read a 1 indicates that an - // unmasked interrupt was signaled - // because a program or erase action - // was attempted on a block of Flash - // memory that contradicts the - // protection policy for that block - // as set in the FMPPEn registers. - // Writing a 1 to this bit clears - // AMISC and also the ARIS bit in - // the FCRIS register 0 When read a - // 0 indicates that no improper - // accesses have occurred. A write - // of 0 has no effect on the state - // of this bit. -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FMC2 register. -// -//****************************************************************************** -#define FLASH_CTRL_FMC2_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This - // field contains a write key which - // is used to minimize the incidence - // of accidental Flash memory - // writes. The value 0xA442 must be - // written into this field for a - // write to occur. Writes to the - // FMC2 register without this WRKEY - // value are ignored. A read of this - // field returns the value 0. -#define FLASH_CTRL_FMC2_WRKEY_S 16 -#define FLASH_CTRL_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write This - // bit is used to start a buffered - // write to Flash memory. Value - // Description 1 Set this bit to - // write the data stored in the FWBn - // registers to the location - // specified by the contents of the - // FMA register. When read a 1 - // indicates that the previous - // buffered Flash memory write - // access is not complete. 0 A write - // of 0 has no effect on the state - // of this bit. When read a 0 - // indicates that the previous - // buffered Flash memory write - // access is complete. -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWBVAL register. -// -//****************************************************************************** -#define FLASH_CTRL_FWBVAL_FWBN_M \ - 0xFFFFFFFF // Flash Memory Write Buffer Value - // Description 1 The corresponding - // FWBn register has been updated - // since the last buffer write - // operation and is ready to be - // written to Flash memory. 0 The - // corresponding FWBn register has - // no new data to be written. Bit 0 - // corresponds to FWB0 offset 0x100 - // and bit 31 corresponds to FWB31 - // offset 0x13C. - -#define FLASH_CTRL_FWBVAL_FWBN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB1 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB1_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB1_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB2 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB2_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB2_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB3 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB3_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB3_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB4 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB4_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB4_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB5 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB5_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB5_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB6 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB6_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB6_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB7 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB7_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB7_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB8 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB8_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB8_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the FLASH_CTRL_O_FWB9 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB9_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB9_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB10 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB10_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB10_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB11 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB11_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB11_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB12 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB12_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB12_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB13 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB13_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB13_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB14 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB14_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB14_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB15 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB15_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB15_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB16 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB16_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB16_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB17 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB17_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB17_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB18 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB18_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB18_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB19 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB19_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB19_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB20 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB20_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB20_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB21 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB21_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB21_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB22 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB22_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB22_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB23 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB23_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB23_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB24 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB24_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB24_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB25 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB25_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB25_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB26 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB26_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB26_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB27 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB27_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB27_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB28 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB28_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB28_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB29 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB29_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB29_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB30 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB30_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB30_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB31 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB31_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB31_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FWB32 register. -// -//****************************************************************************** -#define FLASH_CTRL_FWB32_DATA_M 0xFFFFFFFF // Data Data to be written into the - // Flash memory. -#define FLASH_CTRL_FWB32_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_FSIZE register. -// -//****************************************************************************** -#define FLASH_CTRL_FSIZE_SIZE_M 0x0000FFFF // Flash Size Indicates the size of - // the on-chip Flash memory. Value - // Description 0x0003 8 KB of Flash - // 0x0007 16 KB of Flash 0x000F 32 - // KB of Flash 0x001F 64 KB of Flash - // 0x002F 96 KB of Flash 0x003F 128 - // KB of Flash 0x005F 192 KB of - // Flash 0x007F 256 KB of Flash -#define FLASH_CTRL_FSIZE_SIZE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// FLASH_CTRL_O_SSIZE register. -// -//****************************************************************************** -#define FLASH_CTRL_SSIZE_SRAM_SIZE_M \ - 0x0000FFFF // SRAM Size Indicates the size of - // the on-chip SRAM. Value - // Description 0x0007 2 KB of SRAM - // 0x000F 4 KB of SRAM 0x0017 6 KB - // of SRAM 0x001F 8 KB of SRAM - // 0x002F 12 KB of SRAM 0x003F 16 KB - // of SRAM 0x004F 20 KB of SRAM - // 0x005F 24 KB of SRAM 0x007F 32 KB - // of SRAM - -#define FLASH_CTRL_SSIZE_SRAM_SIZE_S 0 -#define FLASH_CTRL_FMC_WRKEY 0xA4420000 // FLASH write key -#define FLASH_CTRL_FMC2_WRKEY 0xA4420000 // FLASH write key -#define FLASH_CTRL_O_FWBN FLASH_CTRL_O_FWB1 -#define FLASH_ERASE_SIZE 0x00000400 -#define FLASH_PROTECT_SIZE 0x00000800 -#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 - -#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read - // Enable 0 -#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read - // Enable 1 -#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read - // Enable 2 -#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read - // Enable 3 -#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read - // Enable 4 -#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read - // Enable 5 -#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read - // Enable 6 -#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read - // Enable 7 -#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read - // Enable 8 -#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read - // Enable 9 -#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read - // Enable 10 -#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read - // Enable 11 -#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read - // Enable 12 -#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read - // Enable 13 -#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read - // Enable 14 -#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read - // Enable 15 - -#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program - // Enable 0 -#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program - // Enable 1 -#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program - // Enable 2 -#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program - // Enable 3 -#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program - // Enable 4 -#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program - // Enable 5 -#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program - // Enable 6 -#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program - // Enable 7 -#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program - // Enable 8 -#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program - // Enable 9 -#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program - // Enable 10 -#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program - // Enable 11 -#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program - // Enable 12 -#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program - // Enable 13 -#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program - // Enable 14 -#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program - // Enable 15 - -#define FLASH_USECRL 0x400FE140 // USec Reload -#define FLASH_CTRL_ERASE_SIZE 0x00000400 - - -#endif // __HW_FLASH_CTRL_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_gpio.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_gpio.h deleted file mode 100644 index 118e24704d5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_gpio.h +++ /dev/null @@ -1,1347 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_GPIO_H__ -#define __HW_GPIO_H__ - -//***************************************************************************** -// -// The following are defines for the GPIO register offsets. -// -//***************************************************************************** -#define GPIO_O_GPIO_DATA 0x00000000 // 0x4000 5000 0x4000 6000 0x4000 - // 7000 0x4002 4000 GPIO Data - // (GPIODATA)@@ offset 0x000 The - // GPIODATA register is the data - // register. In software control - // mode@@ values written in the - // GPIODATA register are transferred - // onto the GPIO port pins if the - // respective pins have been - // configured as outputs through the - // GPIO Direction (GPIODIR) register - // (see page 653). In order to write - // to GPIODATA@@ the corresponding - // bits in the mask@@ resulting from - // the address bus bits [9:2]@@ must - // be set. Otherwise@@ the bit - // values remain unchanged by the - // write. Similarly@@ the values - // read from this register are - // determined for each bit by the - // mask bit derived from the address - // used to access the data - // register@@ bits [9:2]. Bits that - // are set in the address mask cause - // the corresponding bits in - // GPIODATA to be read@@ and bits - // that are clear in the address - // mask cause the corresponding bits - // in GPIODATA to be read as 0@@ - // regardless of their value. A read - // from GPIODATA returns the last - // bit value written if the - // respective pins are configured as - // outputs@@ or it returns the value - // on the corresponding input pin - // when these are configured as - // inputs. All bits are cleared by a - // reset. -#define GPIO_O_GPIO_DIR 0x00000400 // 0x4000 5400 0x4000 6400 0x4000 - // 7400 0x4002 4400 GPIO Direction - // (GPIODIR)@@ offset 0x400 The - // GPIODIR register is the data - // direction register. Setting a bit - // in the GPIODIR register - // configures the corresponding pin - // to be an output@@ while clearing - // a bit configures the - // corresponding pin to be an input. - // All bits are cleared by a reset@@ - // meaning all GPIO pins are inputs - // by default. -#define GPIO_O_GPIO_IS 0x00000404 // 0x4000 5404 0x4000 6404 0x4000 - // 7404 0x4002 4404 GPIO Interrupt - // Sense (GPIOIS)@@ offset 0x404 The - // GPIOIS register is the interrupt - // sense register. Setting a bit in - // the GPIOIS register configures - // the corresponding pin to detect - // levels@@ while clearing a bit - // configures the corresponding pin - // to detect edges. All bits are - // cleared by a reset. -#define GPIO_O_GPIO_IBE 0x00000408 // 0x4000 5408 0x4000 6408 0x4000 - // 7408 0x4002 4408 GPIO Interrupt - // Both Edges (GPIOIBE)@@ offset - // 0x408 The GPIOIBE register allows - // both edges to cause interrupts. - // When the corresponding bit in the - // GPIO Interrupt Sense (GPIOIS) - // register is set to detect edges@@ - // setting a bit in the GPIOIBE - // register configures the - // corresponding pin to detect both - // rising and falling edges@@ - // regardless of the corresponding - // bit in the GPIO Interrupt Event - // (GPIOIEV) register . Clearing a - // bit configures the pin to be - // controlled by the GPIOIEV - // register. All bits are cleared by - // a reset. -#define GPIO_O_GPIO_IEV 0x0000040C // 0x4000 540C 0x4000 640C 0x4000 - // 740C 0x4002 440C GPIO Interrupt - // Event (GPIOIEV)@@ offset 0x40C - // The GPIOIEV register is the - // interrupt event register. Setting - // a bit in the GPIOIEV register - // configures the corresponding pin - // to detect rising edges or high - // levels@@ depending on the - // corresponding bit value in the - // GPIO Interrupt Sense (GPIOIS) - // register . Clearing a bit - // configures the pin to detect - // falling edges or low levels@@ - // depending on the corresponding - // bit value in the GPIOIS register. - // All bits are cleared by a reset. -#define GPIO_O_GPIO_IM 0x00000410 // 0x4000 5410 0x4000 6410 0x4000 - // 7410 0x4002 4410 GPIO Interrupt - // Mask (GPIOIM)@@ offset 0x410 The - // GPIOIM register is the interrupt - // mask register. Setting a bit in - // the GPIOIM register allows - // interrupts that are generated by - // the corresponding pin to be sent - // to the interrupt controller on - // the combined interrupt signal. - // Clearing a bit prevents an - // interrupt on the corresponding - // pin from being sent to the - // interrupt controller. All bits - // are cleared by a reset. -#define GPIO_O_GPIO_RIS 0x00000414 // 0x4000 5414 0x4000 6414 0x4000 - // 7414 0x4002 4414 GPIO Raw - // Interrupt Status (GPIORIS)@@ - // offset 0x414 The GPIORIS register - // is the raw interrupt status - // register. A bit in this register - // is set when an interrupt - // condition occurs on the - // corresponding GPIO pin. If the - // corresponding bit in the GPIO - // Interrupt Mask (GPIOIM) register - // is set@@ the interrupt is sent to - // the interrupt controller. Bits - // read as zero indicate that - // corresponding input pins have not - // initiated an interrupt. A bit in - // this register can be cleared by - // writing a 1 to the corresponding - // bit in the GPIO Interrupt Clear - // (GPIOICR) register. -#define GPIO_O_GPIO_MIS 0x00000418 // 0x4000 5418 0x4000 6418 0x4000 - // 7418 0x4002 4418 GPIO Masked - // Interrupt Status (GPIOMIS)@@ - // offset 0x418 The GPIOMIS register - // is the masked interrupt status - // register. If a bit is set in this - // register@@ the corresponding - // interrupt has triggered an - // interrupt to the interrupt - // controller. If a bit is clear@@ - // either no interrupt has been - // generated@@ or the interrupt is - // masked. If no port pin@@ other - // than the one that is being used - // as an ADC trigger@@ is being used - // to generate interrupts@@ the - // appropriate Interrupt Set Enable - // (ENn) register can disable the - // interrupts for the port@@ and the - // ADC interrupt can be used to read - // back the converted data. - // Otherwise@@ the port interrupt - // handler must ignore and clear - // interrupts on the port pin and - // wait for the ADC interrupt@@ or - // the ADC interrupt must be - // disabled in the EN0 register and - // the port interrupt handler must - // poll the ADC registers until the - // conversion is completed. If no - // port pin@@ other than the one - // that is being used as an ADC - // trigger@@ is being used to - // generate interrupts@@ the - // appropriate Interrupt Set Enable - // (ENn) register can disable the - // interrupts for the port@@ and the - // ADC interrupt can be used to read - // back the converted data. - // Otherwise@@ the port interrupt - // handler must ignore and clear - // interrupts on the port pin and - // wait for the ADC interrupt@@ or - // the ADC interrupt must be - // disabled in the EN0 register and - // the port interrupt handler must - // poll the ADC registers until the - // conversion is completed. Note - // that if the Port B GPIOADCCTL - // register is cleared@@ PB4 can - // still be used as an external - // trigger for the ADC. This is a - // legacy mode which allows code - // written for previous Stellaris - // devices to operate on this - // microcontroller. GPIOMIS is the - // state of the interrupt after - // masking. -#define GPIO_O_GPIO_ICR 0x0000041C // 0x4000 541C 0x4000 641C 0x4000 - // 741C 0x4002 441C GPIO Interrupt - // Clear (GPIOICR)@@ offset 0x41C - // The GPIOICR register is the - // interrupt clear register. Writing - // a 1 to a bit in this register - // clears the corresponding - // interrupt bit in the GPIORIS and - // GPIOMIS registers. Writing a 0 - // has no effect. -#define GPIO_O_GPIO_AFSEL 0x00000420 // 0x4000 5420 0x4000 6420 0x4000 - // 7420 0x4002 4420 GPIO Alternate - // Function Select (GPIOAFSEL)@@ - // offset 0x420 The GPIOAFSEL - // register is the mode control - // select register. If a bit is - // clear@@ the pin is used as a GPIO - // and is controlled by the GPIO - // registers. Setting a bit in this - // register configures the - // corresponding GPIO line to be - // controlled by an associated - // peripheral. Several possible - // peripheral functions are - // multiplexed on each GPIO. The - // GPIO Port Control (GPIOPCTL) - // register is used to select one of - // the possible functions. -#define GPIO_O_GPIO_DR2R 0x00000500 // 0x4000 5500 0x4000 6500 0x4000 - // 7500 0x4002 4500 GPIO 2-mA Drive - // Select (GPIODR2R)@@ offset 0x500 - // The GPIODR2R register is the 2-mA - // drive control register. Each GPIO - // signal in the port can be - // individually configured without - // affecting the other pads. When - // setting the DRV2 bit for a GPIO - // signal@@ the corresponding DRV4 - // bit in the GPIODR4R register and - // DRV8 bit in the GPIODR8R register - // are automatically cleared by - // hardware. By default@@ all GPIO - // pins have 2-mA drive. -#define GPIO_O_GPIO_DR4R 0x00000504 // 0x4000 5504 0x4000 6504 0x4000 - // 7504 0x4002 4504 GPIO 4-mA Drive - // Select (GPIODR4R)@@ offset 0x504 - // The GPIODR4R register is the 4-mA - // drive control register. Each GPIO - // signal in the port can be - // individually configured without - // affecting the other pads. When - // setting the DRV4 bit for a GPIO - // signal@@ the corresponding DRV2 - // bit in the GPIODR2R register and - // DRV8 bit in the GPIODR8R register - // are automatically cleared by - // hardware. -#define GPIO_O_GPIO_DR8R 0x00000508 // 0x4000 5508 0x4000 6508 0x4000 - // 7508 0x4002 4508 GPIO 8-mA Drive - // Select (GPIODR8R)@@ offset 0x508 - // The GPIODR8R register is the 8-mA - // drive control register. Each GPIO - // signal in the port can be - // individually configured without - // affecting the other pads. When - // setting the DRV8 bit for a GPIO - // signal@@ the corresponding DRV2 - // bit in the GPIODR2R register and - // DRV4 bit in the GPIODR4R register - // are automatically cleared by - // hardware. The 8-mA setting is - // also used for high-current - // operation. Note: There is no - // configuration difference between - // 8-mA and high-current operation. - // The additional current capacity - // results from a shift in the - // VOH/VOL levels. -#define GPIO_O_GPIO_ODR 0x0000050C // 0x4000 550C 0x4000 650C 0x4000 - // 750C 0x4002 450C GPIO Open Drain - // Select (GPIOODR)@@ offset 0x50C - // The GPIOODR register is the open - // drain control register. Setting a - // bit in this register enables the - // open-drain configuration of the - // corresponding GPIO pad. When - // open-drain mode is enabled@@ the - // corresponding bit should also be - // set in the GPIO Digital Input - // Enable (GPIODEN) register . - // Corresponding bits in the drive - // strength and slew rate control - // registers (GPIODR2R@@ GPIODR4R@@ - // GPIODR8R@@ and GPIOSLR) can be - // set to achieve the desired rise - // and fall times. The GPIO acts as - // an open-drain input if the - // corresponding bit in the GPIODIR - // register is cleared. If open - // drain is selected while the GPIO - // is configured as an input@@ the - // GPIO will remain an input and the - // open-drain selection has no - // effect until the GPIO is changed - // to an output. When using the I2C - // module@@ in addition to - // configuring the pin to open - // drain@@ the GPIO Alternate - // Function Select (GPIOAFSEL) - // register bits for the I2C clock - // and data pins should be set -#define GPIO_O_GPIO_PUR 0x00000510 // 0x4000 5510 0x4000 6510 0x4000 - // 7510 0x4002 4510 GPIO Pull-Up - // Select (GPIOPUR)@@ offset 0x510 - // The GPIOPUR register is the - // pull-up control register. When a - // bit is set@@ a weak pull-up - // resistor on the corresponding - // GPIO signal is enabled. Setting a - // bit in GPIOPUR automatically - // clears the corresponding bit in - // the GPIO Pull-Down Select - // (GPIOPDR) register . Write access - // to this register is protected - // with the GPIOCR register. Bits in - // GPIOCR that are cleared prevent - // writes to the equivalent bit in - // this register. -#define GPIO_O_GPIO_PDR 0x00000514 // 0x4000 5514 0x4000 6514 0x4000 - // 7514 0x4002 4514 GPIO Pull-Down - // Select (GPIOPDR)@@ offset 0x514 - // The GPIOPDR register is the - // pull-down control register. When - // a bit is set@@ a weak pull-down - // resistor on the corresponding - // GPIO signal is enabled. Setting a - // bit in GPIOPDR automatically - // clears the corresponding bit in - // the GPIO Pull-Up Select (GPIOPUR) - // register -#define GPIO_O_GPIO_SLR 0x00000518 // 0x4000 5518 0x4000 6518 0x4000 - // 7518 0x4002 4518 The GPIOSLR - // register is the slew rate control - // register. Slew rate control is - // only available when using the - // 8-mA drive strength option via - // the GPIO 8-mA Drive Select - // (GPIODR8R) register -#define GPIO_O_GPIO_DEN 0x0000051C // 0x4000 551C 0x4000 651C 0x4000 - // 751C 0x4002 451C GPIO Digital - // Enable (GPIODEN)@@ offset 0x51C - // Note: Pins configured as digital - // inputs are Schmitt-triggered. The - // GPIODEN register is the digital - // enable register. By default@@ all - // GPIO signals except those listed - // below are configured out of reset - // to be undriven (tristate). Their - // digital function is disabled; - // they do not drive a logic value - // on the pin and they do not allow - // the pin voltage into the GPIO - // receiver. To use the pin as a - // digital input or output (either - // GPIO or alternate function)@@ the - // corresponding GPIODEN bit must be - // set. -#define GPIO_O_GPIO_LOCK 0x00000520 // 0x4000 5520 0x4000 6520 0x4000 - // 7520 0x4002 4520 GPIO Lock - // (GPIOLOCK)@@ offset 0x520 The - // GPIOLOCK register enables write - // access to the GPIOCR register . - // Writing 0x4C4F.434B to the - // GPIOLOCK register unlocks the - // GPIOCR register. Writing any - // other value to the GPIOLOCK - // register re-enables the locked - // state. Reading the GPIOLOCK - // register returns the lock status - // rather than the 32-bit value that - // was previously written. - // Therefore@@ when write accesses - // are disabled@@ or locked@@ - // reading the GPIOLOCK register - // returns 0x0000.0001. When write - // accesses are enabled@@ or - // unlocked@@ reading the GPIOLOCK - // register returns 0x0000.0000. -#define GPIO_O_GPIO_CR 0x00000524 // 0x4000 5524 0x4000 6524 0x4000 - // 7524 0x4002 4524 GPIO Commit - // (GPIOCR)@@ offset 0x524 The - // GPIOCR register is the commit - // register. The value of the GPIOCR - // register determines which bits of - // the GPIOAFSEL@@ GPIOPUR@@ - // GPIOPDR@@ and GPIODEN registers - // are committed when a write to - // these registers is performed. If - // a bit in the GPIOCR register is - // cleared@@ the data being written - // to the corresponding bit in the - // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ - // or GPIODEN registers cannot be - // committed and retains its - // previous value. If a bit in the - // GPIOCR register is set@@ the data - // being written to the - // corresponding bit of the - // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ - // or GPIODEN registers is committed - // to the register and reflects the - // new value. The contents of the - // GPIOCR register can only be - // modified if the status in the - // GPIOLOCK register is unlocked. - // Writes to the GPIOCR register are - // ignored if the status in the - // GPIOLOCK register is locked. -#define GPIO_O_GPIO_AMSEL 0x00000528 // 0x4000 5528 0x4000 6528 0x4000 - // 7528 0x4002 4528 The GPIOAMSEL - // register controls isolation - // circuits to the analog side of a - // unified I/O pad. Because the - // GPIOs may be driven by a 5-V - // source and affect analog - // operation@@ analog circuitry - // requires isolation from the pins - // when they are not used in their - // analog function. Each bit of this - // register controls the isolation - // circuitry for the corresponding - // GPIO signal. -#define GPIO_O_GPIO_PCTL 0x0000052C // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) 0x4000 552C - // 0x4000 652C 0x4000 752C 0x4002 - // 452C GPIO Port Control - // (GPIOPCTL)@@ offset 0x52C The - // GPIOPCTL register is used in - // conjunction with the GPIOAFSEL - // register and selects the specific - // peripheral signal for each GPIO - // pin when using the alternate - // function mode. Most bits in the - // GPIOAFSEL register are cleared on - // reset@@ therefore most GPIO pins - // are configured as GPIOs by - // default. When a bit is set in the - // GPIOAFSEL register@@ the - // corresponding GPIO signal is - // controlled by an associated - // peripheral. The GPIOPCTL register - // selects one out of a set of - // peripheral functions for each - // GPIO@@ providing additional - // flexibility in signal definition. -#define GPIO_O_GPIO_ADCCTL 0x00000530 // This register is not used in - // cc3xx. ADC trigger via GPIO is - // not supported. 0x4000 5530 0x4000 - // 6530 0x4000 7530 0x4002 4530 GPIO - // ADC Control (GPIOADCCTL)@@ offset - // 0x530 This register is used to - // configure a GPIO pin as a source - // for the ADC trigger. Note that if - // the Port B GPIOADCCTL register is - // cleared@@ PB4 can still be used - // as an external trigger for the - // ADC. This is a legacy mode which - // allows code written for previous - // Stellaris devices to operate on - // this microcontroller. -#define GPIO_O_GPIO_DMACTL 0x00000534 // 0x4000 5534 0x4000 6534 0x4000 - // 7534 0x4002 4534 GPIO DMA Control - // (GPIODMACTL)@@ offset 0x534 This - // register is used to configure a - // GPIO pin as a source for the ?DMA - // trigger. -#define GPIO_O_GPIO_SI 0x00000538 // 0x4000 5538 0x4000 6538 0x4000 - // 7538 0x4002 4538 GPIO Select - // Interrupt (GPIOSI)@@ offset 0x538 - // This register is used to enable - // individual interrupts for each - // pin. Note: This register is only - // available on Port P and Port Q. -#define GPIO_O_GPIO_PERIPHID4 0x00000FD0 // 0x4000 5FD0 0x4000 6FD0 0x4000 - // 7FD0 0x4002 4FD0 GPIO Peripheral - // Identification 4 - // (GPIOPeriphID4)@@ offset 0xFD0 - // The GPIOPeriphID4@@ - // GPIOPeriphID5@@ GPIOPeriphID6@@ - // and GPIOPeriphID7 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID5 0x00000FD4 // 0x4000 5FD4 0x4000 6FD4 0x4000 - // 7FD4 0x4002 4FD4 GPIO Peripheral - // Identification 5 - // (GPIOPeriphID5)@@ offset 0xFD4 - // The GPIOPeriphID4@@ - // GPIOPeriphID5@@ GPIOPeriphID6@@ - // and GPIOPeriphID7 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID6 0x00000FD8 // 0x4000 5FD8 0x4000 6FD8 0x4000 - // 7FD8 0x4002 4FD8 GPIO Peripheral - // Identification 6 - // (GPIOPeriphID6)@@ offset 0xFD8 - // The GPIOPeriphID4@@ - // GPIOPeriphID5@@ GPIOPeriphID6@@ - // and GPIOPeriphID7 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID7 0x00000FDC // 0x4000 5FDC 0x4000 6FDC 0x4000 - // 7FDC 0x4002 4FDC GPIO Peripheral - // Identification 7 - // (GPIOPeriphID7)@@ offset 0xFDC - // The GPIOPeriphID4@@ - // GPIOPeriphID5@@ GPIOPeriphID6@@ - // and GPIOPeriphID7 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID0 0x00000FE0 // 0x4000 5FE0 0x4000 6FE0 0x4000 - // 7FE0 0x4002 4FE0 GPIO Peripheral - // Identification 0 - // (GPIOPeriphID0)@@ offset 0xFE0 - // The GPIOPeriphID0@@ - // GPIOPeriphID1@@ GPIOPeriphID2@@ - // and GPIOPeriphID3 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID1 0x00000FE4 // 0x4000 5FE4 0x4000 6FE4 0x4000 - // 7FE4 0x4002 4FE4 GPIO Peripheral - // Identification 1 - // (GPIOPeriphID1)@@ offset 0xFE4 - // The GPIOPeriphID0@@ - // GPIOPeriphID1@@ GPIOPeriphID2@@ - // and GPIOPeriphID3 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID2 0x00000FE8 // 0x4000 5FE8 0x4000 6FE8 0x4000 - // 7FE8 0x4002 4FE8 GPIO Peripheral - // Identification 2 - // (GPIOPeriphID2)@@ offset 0xFE8 - // The GPIOPeriphID0@@ - // GPIOPeriphID1@@ GPIOPeriphID2@@ - // and GPIOPeriphID3 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PERIPHID3 0x00000FEC // 0x4000 5FEC 0x4000 6FEC 0x4000 - // 7FEC 0x4002 4FEC GPIO Peripheral - // Identification 3 - // (GPIOPeriphID3)@@ offset 0xFEC - // The GPIOPeriphID0@@ - // GPIOPeriphID1@@ GPIOPeriphID2@@ - // and GPIOPeriphID3 registers can - // conceptually be treated as one - // 32-bit register; each register - // contains eight bits of the 32-bit - // register@@ used by software to - // identify the peripheral. -#define GPIO_O_GPIO_PCELLID0 0x00000FF0 // 0x4000 5FF0 0x4000 6FF0 0x4000 - // 7FF0 0x4002 4FF0 GPIO PrimeCell - // Identification 0 (GPIOPCellID0)@@ - // offset 0xFF0 The GPIOPCellID0@@ - // GPIOPCellID1@@ GPIOPCellID2@@ and - // GPIOPCellID3 registers are four - // 8-bit wide registers@@ that can - // conceptually be treated as one - // 32-bit register. The register is - // used as a standard - // cross-peripheral identification - // system. -#define GPIO_O_GPIO_PCELLID1 0x00000FF4 // 0x4000 5FF4 0x4000 6FF4 0x4000 - // 7FF4 0x4002 4FF4 GPIO PrimeCell - // Identification 1 (GPIOPCellID1)@@ - // offset 0xFF4 The GPIOPCellID0@@ - // GPIOPCellID1@@ GPIOPCellID2@@ and - // GPIOPCellID3 registers are four - // 8-bit wide registers@@ that can - // conceptually be treated as one - // 32-bit register. The register is - // used as a standard - // cross-peripheral identification - // system. -#define GPIO_O_GPIO_PCELLID2 0x00000FF8 // 0x4000 5FF8 0x4000 6FF8 0x4000 - // 7FF8 0x4002 4FF8 GPIO PrimeCell - // Identification 2 (GPIOPCellID2)@@ - // offset 0xFF8 The GPIOPCellID0@@ - // GPIOPCellID1@@ GPIOPCellID2@@ and - // GPIOPCellID3 registers are four - // 8-bit wide registers@@ that can - // conceptually be treated as one - // 32-bit register. The register is - // used as a standard - // cross-peripheral identification - // system. -#define GPIO_O_GPIO_PCELLID3 0x00000FFC // 0x4000 5FFC 0x4000 6FFC 0x4000 - // 7FFC 0x4002 4FFC GPIO PrimeCell - // Identification 3 (GPIOPCellID3)@@ - // offset 0xFFC The GPIOPCellID0@@ - // GPIOPCellID1@@ GPIOPCellID2@@ and - // GPIOPCellID3 registers are four - // 8-bit wide registers@@ that can - // conceptually be treated as one - // 32-bit register. The register is - // used as a standard - // cross-peripheral identification - // system.0xb1 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_DATA register. -// -//****************************************************************************** -#define GPIO_GPIO_DATA_DATA_M 0x000000FF // GPIO Data This register is - // virtually mapped to 256 locations - // in the address space. To - // facilitate the reading and - // writing of data to these - // registers by independent - // drivers@@ the data read from and - // written to the registers are - // masked by the eight address lines - // [9:2]. Reads from this register - // return its current state. Writes - // to this register only affect bits - // that are not masked by ADDR[9:2] - // and are configured as outputs. -#define GPIO_GPIO_DATA_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_DIR register. -// -//****************************************************************************** -#define GPIO_GPIO_DIR_DIR_M 0x000000FF // GPIO Data Direction Value - // Description 0 Corresponding pin - // is an input. 1 Corresponding pins - // is an output. -#define GPIO_GPIO_DIR_DIR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_IS register. -// -//****************************************************************************** -#define GPIO_GPIO_IS_IS_M 0x000000FF // GPIO Interrupt Sense Value - // Description 0 The edge on the - // corresponding pin is detected - // (edge-sensitive). 1 The level on - // the corresponding pin is detected - // (level-sensitive). -#define GPIO_GPIO_IS_IS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_IBE register. -// -//****************************************************************************** -#define GPIO_GPIO_IBE_IBE_M 0x000000FF // GPIO Interrupt Both Edges Value - // Description 0 Interrupt - // generation is controlled by the - // GPIO Interrupt Event (GPIOIEV) - // register. 1 Both edges on the - // corresponding pin trigger an - // interrupt. -#define GPIO_GPIO_IBE_IBE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_IEV register. -// -//****************************************************************************** -#define GPIO_GPIO_IEV_IEV_M 0x000000FF // GPIO Interrupt Event Value - // Description 1 A falling edge or a - // Low level on the corresponding - // pin triggers an interrupt. 0 A - // rising edge or a High level on - // the corresponding pin triggers an - // interrupt. -#define GPIO_GPIO_IEV_IEV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_IM register. -// -//****************************************************************************** -#define GPIO_GPIO_IM_IME_M 0x000000FF // GPIO Interrupt Mask Enable Value - // Description 0 The interrupt from - // the corresponding pin is masked. - // 1 The interrupt from the - // corresponding pin is sent to the - // interrupt controller. -#define GPIO_GPIO_IM_IME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_RIS register. -// -//****************************************************************************** -#define GPIO_GPIO_RIS_RIS_M 0x000000FF // GPIO Interrupt Raw Status Value - // Description 1 An interrupt - // condition has occurred on the - // corresponding pin. 0 interrupt - // condition has not occurred on the - // corresponding pin. A bit is - // cleared by writing a 1 to the - // corresponding bit in the GPIOICR - // register. -#define GPIO_GPIO_RIS_RIS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_MIS register. -// -//****************************************************************************** -#define GPIO_GPIO_MIS_MIS_M 0x000000FF // GPIO Masked Interrupt Status - // Value Description 1 An interrupt - // condition on the corresponding - // pin has triggered an interrupt to - // the interrupt controller. 0 An - // interrupt condition on the - // corresponding pin is masked or - // has not occurred. A bit is - // cleared by writing a 1 to the - // corresponding bit in the GPIOICR - // register. -#define GPIO_GPIO_MIS_MIS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_ICR register. -// -//****************************************************************************** -#define GPIO_GPIO_ICR_IC_M 0x000000FF // GPIO Interrupt Clear Value - // Description 1 The corresponding - // interrupt is cleared. 0 The - // corresponding interrupt is - // unaffected. -#define GPIO_GPIO_ICR_IC_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_AFSEL register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_DR2R register. -// -//****************************************************************************** -#define GPIO_GPIO_DR2R_DRV2_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Output Pad - // 2-mA Drive Enable Value - // Description 1 The corresponding - // GPIO pin has 2-mA drive. The - // drive for the corresponding GPIO - // pin is controlled by the GPIODR4R - // or GPIODR8R register. 0 Setting a - // bit in either the GPIODR4 - // register or the GPIODR8 register - // clears the corresponding 2-mA - // enable bit. The change is - // effective on the second clock - // cycle after the write if - // accessing GPIO via the APB memory - // aperture. If using AHB access@@ - // the change is effective on the - // next clock cycle. -#define GPIO_GPIO_DR2R_DRV2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_DR4R register. -// -//****************************************************************************** -#define GPIO_GPIO_DR4R_DRV4_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Output Pad - // 4-mA Drive Enable Value - // Description 1 The corresponding - // GPIO pin has 4-mA drive. The - // drive for the corresponding GPIO - // pin is controlled by the GPIODR2R - // or GPIODR8R register. 0 Setting a - // bit in either the GPIODR2 - // register or the GPIODR8 register - // clears the corresponding 4-mA - // enable bit. The change is - // effective on the second clock - // cycle after the write if - // accessing GPIO via the APB memory - // aperture. If using AHB access@@ - // the change is effective on the - // next clock cycle. -#define GPIO_GPIO_DR4R_DRV4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_DR8R register. -// -//****************************************************************************** -#define GPIO_GPIO_DR8R_DRV8_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Output Pad - // 8-mA Drive Enable Value - // Description 1 The corresponding - // GPIO pin has 8-mA drive. The - // drive for the corresponding GPIO - // pin is controlled by the GPIODR2R - // or GPIODR4R register. 0 Setting a - // bit in either the GPIODR2 - // register or the GPIODR4 register - // clears the corresponding 8-mA - // enable bit. The change is - // effective on the second clock - // cycle after the write if - // accessing GPIO via the APB memory - // aperture. If using AHB access@@ - // the change is effective on the - // next clock cycle. -#define GPIO_GPIO_DR8R_DRV8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_ODR register. -// -//****************************************************************************** -#define GPIO_GPIO_ODR_ODE_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Output Pad - // Open Drain Enable Value - // Description 1 The corresponding - // pin is configured as open drain. - // 0 The corresponding pin is not - // configured as open drain. -#define GPIO_GPIO_ODR_ODE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_PUR register. -// -//****************************************************************************** -#define GPIO_GPIO_PUR_PUE_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Pad Weak - // Pull-Up Enable Value Description - // 1 The corresponding pin has a - // weak pull-up resistor. 0 The - // corresponding pin is not - // affected. Setting a bit in the - // GPIOPDR register clears the - // corresponding bit in the GPIOPUR - // register. The change is effective - // on the second clock cycle after - // the write if accessing GPIO via - // the APB memory aperture. If using - // AHB access@@ the change is - // effective on the next clock - // cycle. -#define GPIO_GPIO_PUR_PUE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_PDR register. -// -//****************************************************************************** -#define GPIO_GPIO_PDR_PDE_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Pad Weak - // Pull-Down Enable Value - // Description 1 The corresponding - // pin has a weak pull-down - // resistor. 0 The corresponding pin - // is not affected. Setting a bit in - // the GPIOPUR register clears the - // corresponding bit in the GPIOPDR - // register. The change is effective - // on the second clock cycle after - // the write if accessing GPIO via - // the APB memory aperture. If using - // AHB access@@ the change is - // effective on the next clock - // cycle. -#define GPIO_GPIO_PDR_PDE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_SLR register. -// -//****************************************************************************** -#define GPIO_GPIO_SLR_SRL_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Slew Rate - // Limit Enable (8-mA drive only) - // Value Description 1 Slew rate - // control is enabled for the - // corresponding pin. 0 Slew rate - // control is disabled for the - // corresponding pin. -#define GPIO_GPIO_SLR_SRL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_DEN register. -// -//****************************************************************************** -#define GPIO_GPIO_DEN_DEN_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Digital Enable - // Value Description 0 The digital - // functions for the corresponding - // pin are disabled. 1 The digital - // functions for the corresponding - // pin are enabled. -#define GPIO_GPIO_DEN_DEN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_LOCK register. -// -//****************************************************************************** -#define GPIO_GPIO_LOCK_LOCK_M 0xFFFFFFFF // This register is not used in - // cc3xx. GPIO Lock A write of the - // value 0x4C4F.434B unlocks the - // GPIO Commit (GPIOCR) register for - // write access.A write of any other - // value or a write to the GPIOCR - // register reapplies the lock@@ - // preventing any register updates. - // A read of this register returns - // the following values: Value - // Description 0x1 The GPIOCR - // register is locked and may not be - // modified. 0x0 The GPIOCR register - // is unlocked and may be modified. -#define GPIO_GPIO_LOCK_LOCK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_CR register. -// -//****************************************************************************** -#define GPIO_GPIO_CR_CR_M 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) GPIO Commit - // Value Description The - // corresponding GPIOAFSEL@@ - // GPIOPUR@@ GPIOPDR@@ or GPIODEN - // bits can be written. 1 The - // corresponding GPIOAFSEL@@ - // GPIOPUR@@ GPIOPDR@@ or GPIODEN - // bits cannot be written. 0 Note: - // The default register type for the - // GPIOCR register is RO for all - // GPIO pins with the exception of - // the NMI pin and the four JTAG/SWD - // pins (PD7@@ PF0@@ and PC[3:0]). - // These six pins are the only GPIOs - // that are protected by the GPIOCR - // register. Because of this@@ the - // register type for GPIO Port D7@@ - // GPIO Port F0@@ and GPIO Port - // C[3:0] is R/W. The default reset - // value for the GPIOCR register is - // 0x0000.00FF for all GPIO pins@@ - // with the exception of the NMI pin - // and the four JTAG/SWD pins (PD7@@ - // PF0@@ and PC[3:0]). To ensure - // that the JTAG port is not - // accidentally programmed as GPIO - // pins@@ the PC[3:0] pins default - // to non-committable. Similarly@@ - // to ensure that the NMI pin is not - // accidentally programmed as a GPIO - // pin@@ the PD7 and PF0 pins - // default to non-committable. - // Because of this@@ the default - // reset value of GPIOCR for GPIO - // Port C is 0x0000.00F0@@ for GPIO - // Port D is 0x0000.007F@@ and for - // GPIO Port F is 0x0000.00FE. -#define GPIO_GPIO_CR_CR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_AMSEL register. -// -//****************************************************************************** -#define GPIO_GPIO_AMSEL_GPIO_AMSEL_M \ - 0x000000FF // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) GPIO Analog - // Mode Select Value Description 1 - // The analog function of the pin is - // enabled@@ the isolation is - // disabled@@ and the pin is capable - // of analog functions. 0 The analog - // function of the pin is disabled@@ - // the isolation is enabled@@ and - // the pin is capable of digital - // functions as specified by the - // other GPIO configuration - // registers. Note: This register - // and bits are only valid for GPIO - // signals that share analog - // function through a unified I/O - // pad. The reset state of this - // register is 0 for all signals. - -#define GPIO_GPIO_AMSEL_GPIO_AMSEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_PCTL register. -// -//****************************************************************************** -#define GPIO_GPIO_PCTL_PMC7_M 0xF0000000 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 7 This field controls the - // configuration for GPIO pin 7. -#define GPIO_GPIO_PCTL_PMC7_S 28 -#define GPIO_GPIO_PCTL_PMC6_M 0x0F000000 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 6 This field controls the - // configuration for GPIO pin 6. -#define GPIO_GPIO_PCTL_PMC6_S 24 -#define GPIO_GPIO_PCTL_PMC5_M 0x00F00000 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 5 This field controls the - // configuration for GPIO pin 5. -#define GPIO_GPIO_PCTL_PMC5_S 20 -#define GPIO_GPIO_PCTL_PMC4_M 0x000F0000 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 4 This field controls the - // configuration for GPIO pin 4. -#define GPIO_GPIO_PCTL_PMC4_S 16 -#define GPIO_GPIO_PCTL_PMC3_M 0x0000F000 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 43 This field controls - // the configuration for GPIO pin 3. -#define GPIO_GPIO_PCTL_PMC3_S 12 -#define GPIO_GPIO_PCTL_PMC1_M 0x00000F00 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 1 This field controls the - // configuration for GPIO pin 1. -#define GPIO_GPIO_PCTL_PMC1_S 8 -#define GPIO_GPIO_PCTL_PMC2_M 0x000000F0 // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 2 This field controls the - // configuration for GPIO pin 2. -#define GPIO_GPIO_PCTL_PMC2_S 4 -#define GPIO_GPIO_PCTL_PMC0_M 0x0000000F // This register is not used in - // cc3xx. equivalant register exsist - // outside GPIO IP (refer - // PAD*_config register in the - // shared comn space) Port Mux - // Control 0 This field controls the - // configuration for GPIO pin 0. -#define GPIO_GPIO_PCTL_PMC0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_ADCCTL register. -// -//****************************************************************************** -#define GPIO_GPIO_ADCCTL_ADCEN_M \ - 0x000000FF // This register is not used in - // cc3xx. ADC trigger via GPIO is - // not supported. ADC Trigger Enable - // Value Description 1 The - // corresponding pin is used to - // trigger the ADC. 0 The - // corresponding pin is not used to - // trigger the ADC. - -#define GPIO_GPIO_ADCCTL_ADCEN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_DMACTL register. -// -//****************************************************************************** -#define GPIO_GPIO_DMACTL_DMAEN_M \ - 0x000000FF // This register is not used in the - // cc3xx. Alternate register to - // support this feature is coded in - // the APPS_NWP_CMN space. refer - // register as offset 0x400F70D8 - // ?DMA Trigger Enable Value - // Description 1 The corresponding - // pin is used to trigger the ?DMA. - // 0 The corresponding pin is not - // used to trigger the ?DMA. - -#define GPIO_GPIO_DMACTL_DMAEN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPIO_O_GPIO_SI register. -// -//****************************************************************************** -#define GPIO_GPIO_SI_SUM 0x00000001 // Summary Interrupt Value - // Description 1 Each pin has its - // own interrupt vector. 0 All port - // pin interrupts are OR'ed together - // to produce a summary interrupt. -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID4 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID4_PID4_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO Peripheral ID - // Register [7:0] - -#define GPIO_GPIO_PERIPHID4_PID4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID5 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID5_PID5_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO Peripheral ID - // Register [15:8] - -#define GPIO_GPIO_PERIPHID5_PID5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID6 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID6_PID6_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO Peripheral ID - // Register [23:16] - -#define GPIO_GPIO_PERIPHID6_PID6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID7 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID7_PID7_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO Peripheral ID - // Register [31:24] - -#define GPIO_GPIO_PERIPHID7_PID7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID0 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID0_PID0_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO Peripheral ID - // Register [7:0] Can be used by - // software to identify the presence - // of this peripheral. - -#define GPIO_GPIO_PERIPHID0_PID0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID1 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID1_PID1_M \ - 0x000000FF // GPIO Peripheral ID Register - // [15:8] Can be used by software to - // identify the presence of this - // peripheral. - -#define GPIO_GPIO_PERIPHID1_PID1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID2 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID2_PID2_M \ - 0x000000FF // This register is not used in - // CC3XX.v GPIO Peripheral ID - // Register [23:16] Can be used by - // software to identify the presence - // of this peripheral. - -#define GPIO_GPIO_PERIPHID2_PID2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PERIPHID3 register. -// -//****************************************************************************** -#define GPIO_GPIO_PERIPHID3_PID3_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO Peripheral ID - // Register [31:24] Can be used by - // software to identify the presence - // of this peripheral. - -#define GPIO_GPIO_PERIPHID3_PID3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PCELLID0 register. -// -//****************************************************************************** -#define GPIO_GPIO_PCELLID0_CID0_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO PrimeCell ID Register - // [7:0] Provides software a - // standard cross-peripheral - // identification system. - -#define GPIO_GPIO_PCELLID0_CID0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PCELLID1 register. -// -//****************************************************************************** -#define GPIO_GPIO_PCELLID1_CID1_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO PrimeCell ID Register - // [15:8] Provides software a - // standard cross-peripheral - // identification system. - -#define GPIO_GPIO_PCELLID1_CID1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PCELLID2 register. -// -//****************************************************************************** -#define GPIO_GPIO_PCELLID2_CID2_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO PrimeCell ID Register - // [23:16] Provides software a - // standard cross-peripheral - // identification system. - -#define GPIO_GPIO_PCELLID2_CID2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPIO_O_GPIO_PCELLID3 register. -// -//****************************************************************************** -#define GPIO_GPIO_PCELLID3_CID3_M \ - 0x000000FF // This register is not used in - // CC3XX. GPIO PrimeCell ID Register - // [31:24] Provides software a - // standard cross-peripheral - // identification system. - -#define GPIO_GPIO_PCELLID3_CID3_S 0 - - - -#endif // __HW_GPIO_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_gprcm.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_gprcm.h deleted file mode 100644 index 72b99d6d511..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_gprcm.h +++ /dev/null @@ -1,3320 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_GPRCM_H__ -#define __HW_GPRCM_H__ - -//***************************************************************************** -// -// The following are defines for the GPRCM register offsets. -// -//***************************************************************************** -#define GPRCM_O_APPS_SOFT_RESET 0x00000000 -#define GPRCM_O_APPS_LPDS_WAKEUP_CFG \ - 0x00000004 - -#define GPRCM_O_APPS_LPDS_WAKEUP_SRC \ - 0x00000008 - -#define GPRCM_O_APPS_RESET_CAUSE \ - 0x0000000C - -#define GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG \ - 0x00000010 - -#define GPRCM_O_APPS_SRAM_DSLP_CFG \ - 0x00000018 - -#define GPRCM_O_APPS_SRAM_LPDS_CFG \ - 0x0000001C - -#define GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG \ - 0x00000020 - -#define GPRCM_O_TOP_DIE_ENABLE 0x00000100 -#define GPRCM_O_TOP_DIE_ENABLE_PARAMETERS \ - 0x00000104 - -#define GPRCM_O_MCU_GLOBAL_SOFT_RESET \ - 0x00000108 - -#define GPRCM_O_ADC_CLK_CONFIG 0x0000010C -#define GPRCM_O_APPS_GPIO_WAKE_CONF \ - 0x00000110 - -#define GPRCM_O_EN_NWP_BOOT_WO_DEVINIT \ - 0x00000114 - -#define GPRCM_O_MEM_HCLK_DIV_CFG \ - 0x00000118 - -#define GPRCM_O_MEM_SYSCLK_DIV_CFG \ - 0x0000011C - -#define GPRCM_O_APLLMCS_LOCK_TIME_CONF \ - 0x00000120 - -#define GPRCM_O_NWP_SOFT_RESET 0x00000400 -#define GPRCM_O_NWP_LPDS_WAKEUP_CFG \ - 0x00000404 - -#define GPRCM_O_NWP_LPDS_WAKEUP_SRC \ - 0x00000408 - -#define GPRCM_O_NWP_RESET_CAUSE 0x0000040C -#define GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG \ - 0x00000410 - -#define GPRCM_O_NWP_SRAM_DSLP_CFG \ - 0x00000418 - -#define GPRCM_O_NWP_SRAM_LPDS_CFG \ - 0x0000041C - -#define GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG \ - 0x00000420 - -#define GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL \ - 0x00000424 - -#define GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ \ - 0x00000428 - -#define GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST \ - 0x0000042C - -#define GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST \ - 0x00000430 - -#define GPRCM_O_NWP_GPIO_WAKE_CONF \ - 0x00000434 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG12 \ - 0x00000438 - -#define GPRCM_O_GPRCM_DIEID_READ_REG5 \ - 0x00000448 - -#define GPRCM_O_GPRCM_DIEID_READ_REG6 \ - 0x0000044C - -#define GPRCM_O_REF_FSM_CFG0 0x00000800 -#define GPRCM_O_REF_FSM_CFG1 0x00000804 -#define GPRCM_O_APLLMCS_WLAN_CONFIG0_40 \ - 0x00000808 - -#define GPRCM_O_APLLMCS_WLAN_CONFIG1_40 \ - 0x0000080C - -#define GPRCM_O_APLLMCS_WLAN_CONFIG0_26 \ - 0x00000810 - -#define GPRCM_O_APLLMCS_WLAN_CONFIG1_26 \ - 0x00000814 - -#define GPRCM_O_APLLMCS_WLAN_OVERRIDES \ - 0x00000818 - -#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 \ - 0x0000081C - -#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 \ - 0x00000820 - -#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 \ - 0x00000824 - -#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 \ - 0x00000828 - -#define GPRCM_O_SPARE_RW0 0x0000082C -#define GPRCM_O_SPARE_RW1 0x00000830 -#define GPRCM_O_APLLMCS_MCU_OVERRIDES \ - 0x00000834 - -#define GPRCM_O_SYSCLK_SWITCH_STATUS \ - 0x00000838 - -#define GPRCM_O_REF_LDO_CONTROLS \ - 0x0000083C - -#define GPRCM_O_REF_RTRIM_CONTROL \ - 0x00000840 - -#define GPRCM_O_REF_SLICER_CONTROLS0 \ - 0x00000844 - -#define GPRCM_O_REF_SLICER_CONTROLS1 \ - 0x00000848 - -#define GPRCM_O_REF_ANA_BGAP_CONTROLS0 \ - 0x0000084C - -#define GPRCM_O_REF_ANA_BGAP_CONTROLS1 \ - 0x00000850 - -#define GPRCM_O_REF_ANA_SPARE_CONTROLS0 \ - 0x00000854 - -#define GPRCM_O_REF_ANA_SPARE_CONTROLS1 \ - 0x00000858 - -#define GPRCM_O_MEMSS_PSCON_OVERRIDES0 \ - 0x0000085C - -#define GPRCM_O_MEMSS_PSCON_OVERRIDES1 \ - 0x00000860 - -#define GPRCM_O_PLL_REF_LOCK_OVERRIDES \ - 0x00000864 - -#define GPRCM_O_MCU_PSCON_DEBUG 0x00000868 -#define GPRCM_O_MEMSS_PWR_PS 0x0000086C -#define GPRCM_O_REF_FSM_DEBUG 0x00000870 -#define GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE \ - 0x00000874 - -#define GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG \ - 0x00000878 - -#define GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES \ - 0x0000087C - -#define GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES \ - 0x00000880 - -#define GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES \ - 0x00000884 - -#define GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES \ - 0x00000888 - -#define GPRCM_O_MEM_REF_FSM_CFG2 \ - 0x0000088C - -#define GPRCM_O_TESTCTRL_POWER_CTRL \ - 0x00000C10 - -#define GPRCM_O_SSDIO_POWER_CTRL \ - 0x00000C14 - -#define GPRCM_O_MCSPI_N1_POWER_CTRL \ - 0x00000C18 - -#define GPRCM_O_WELP_POWER_CTRL 0x00000C1C -#define GPRCM_O_WL_SDIO_POWER_CTRL \ - 0x00000C20 - -#define GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG \ - 0x00000C24 - -#define GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG \ - 0x00000C28 - -#define GPRCM_O_APPS_SECURE_INIT_DONE \ - 0x00000C30 - -#define GPRCM_O_APPS_DEV_MODE_INIT_DONE \ - 0x00000C34 - -#define GPRCM_O_EN_APPS_REBOOT 0x00000C38 -#define GPRCM_O_MEM_APPS_PERIPH_PRESENT \ - 0x00000C3C - -#define GPRCM_O_MEM_NWP_PERIPH_PRESENT \ - 0x00000C40 - -#define GPRCM_O_MEM_SHARED_PERIPH_PRESENT \ - 0x00000C44 - -#define GPRCM_O_NWP_PWR_STATE 0x00000C48 -#define GPRCM_O_APPS_PWR_STATE 0x00000C4C -#define GPRCM_O_MCU_PWR_STATE 0x00000C50 -#define GPRCM_O_WTOP_PM_PS 0x00000C54 -#define GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG \ - 0x00000C58 - -#define GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG \ - 0x00000C5C - -#define GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG \ - 0x00000C60 - -#define GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG \ - 0x00000C64 - -#define GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG \ - 0x00000C68 - -#define GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG \ - 0x00000C6C - -#define GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG \ - 0x00000C70 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG0 \ - 0x00000C78 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG1 \ - 0x00000C7C - -#define GPRCM_O_GPRCM_EFUSE_READ_REG2 \ - 0x00000C80 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG3 \ - 0x00000C84 - -#define GPRCM_O_WTOP_MEM_RET_CFG \ - 0x00000C88 - -#define GPRCM_O_COEX_CLK_SWALLOW_CFG0 \ - 0x00000C8C - -#define GPRCM_O_COEX_CLK_SWALLOW_CFG1 \ - 0x00000C90 - -#define GPRCM_O_COEX_CLK_SWALLOW_CFG2 \ - 0x00000C94 - -#define GPRCM_O_COEX_CLK_SWALLOW_ENABLE \ - 0x00000C98 - -#define GPRCM_O_DCDC_CLK_GEN_CONFIG \ - 0x00000C9C - -#define GPRCM_O_GPRCM_EFUSE_READ_REG4 \ - 0x00000CA0 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG5 \ - 0x00000CA4 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG6 \ - 0x00000CA8 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG7 \ - 0x00000CAC - -#define GPRCM_O_GPRCM_EFUSE_READ_REG8 \ - 0x00000CB0 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG9 \ - 0x00000CB4 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG10 \ - 0x00000CB8 - -#define GPRCM_O_GPRCM_EFUSE_READ_REG11 \ - 0x00000CBC - -#define GPRCM_O_GPRCM_DIEID_READ_REG0 \ - 0x00000CC0 - -#define GPRCM_O_GPRCM_DIEID_READ_REG1 \ - 0x00000CC4 - -#define GPRCM_O_GPRCM_DIEID_READ_REG2 \ - 0x00000CC8 - -#define GPRCM_O_GPRCM_DIEID_READ_REG3 \ - 0x00000CCC - -#define GPRCM_O_GPRCM_DIEID_READ_REG4 \ - 0x00000CD0 - -#define GPRCM_O_APPS_SS_OVERRIDES \ - 0x00000CD4 - -#define GPRCM_O_NWP_SS_OVERRIDES \ - 0x00000CD8 - -#define GPRCM_O_SHARED_SS_OVERRIDES \ - 0x00000CDC - -#define GPRCM_O_IDMEM_CORE_RST_OVERRIDES \ - 0x00000CE0 - -#define GPRCM_O_TOP_DIE_FSM_OVERRIDES \ - 0x00000CE4 - -#define GPRCM_O_MCU_PSCON_OVERRIDES \ - 0x00000CE8 - -#define GPRCM_O_WTOP_PSCON_OVERRIDES \ - 0x00000CEC - -#define GPRCM_O_WELP_PSCON_OVERRIDES \ - 0x00000CF0 - -#define GPRCM_O_WL_SDIO_PSCON_OVERRIDES \ - 0x00000CF4 - -#define GPRCM_O_MCSPI_PSCON_OVERRIDES \ - 0x00000CF8 - -#define GPRCM_O_SSDIO_PSCON_OVERRIDES \ - 0x00000CFC - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_SOFT_RESET register. -// -//****************************************************************************** -#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET1 \ - 0x00000002 // Soft-reset1 for APPS : Cortex - // sysrstn is asserted and in - // addition to that the associated - // APPS Peripherals are also reset. - // This is an auto-clear bit. - -#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET0 \ - 0x00000001 // Soft-reset0 for APPS : Only - // sys-resetn for Cortex will be - // asserted. This is an auto-clear - // bit. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_LPDS_WAKEUP_CFG register. -// -//****************************************************************************** -#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_M \ - 0x000000FF // Mask for LPDS Wakeup interrupt : - // [7] - Host IRQ from NWP [6] - - // NWP_LPDS_Wake_irq (TRUE_LPDS) [5] - // - NWP Wake-request to APPS [4] - - // GPIO [3:1] - Reserved [0] - LPDS - // Wakeup-timer - -#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_LPDS_WAKEUP_SRC register. -// -//****************************************************************************** -#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_M \ - 0x000000FF // Indicates the cause for wakeup - // from LPDS : [7] - Host IRQ from - // NWP [6] - NWP_LPDS_Wake_irq - // (TRUE_LPDS) [5] - NWP - // Wake-request to APPS [4] - GPIO - // [3:1] - Reserved [0] - LPDS - // Wakeup-timer - -#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_RESET_CAUSE register. -// -//****************************************************************************** -#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_M \ - 0x000000FF // Indicates the reset cause for - // APPS : "0000" - Wake from HIB/OFF - // mode; "0001" - Wake from LPDS ; - // "0010" - Reserved ; "0011" - - // Soft-reset0 (Only APPS - // Cortex-sysrstn is asserted); - // "0100" - Soft-reset1 (APPS - // Cortex-sysrstn and APPS - // peripherals are reset); "0101" - - // WDOG0 (APPS Cortex-sysrstn and - // APPS peripherals are reset); - // "0110" - MCU Soft-reset (APPS + - // NWP Cortex-sysrstn + Peripherals - // are reset); "0111" - Secure Init - // done (Indication that reset has - // happened after DevInit); "1000" - - // Dev Mode Patch Init done (During - // development mode, patch - // downloading and Cortex - // re-vectoring is completed) - -#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG register. -// -//****************************************************************************** -#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_M \ - 0xFFFFFFFF // OPP Request Configuration - // (Number of slow-clk cycles) for - // LPDS Wake-timer : This - // configuration implies the RTC - // time-stamp, which must be few - // slow-clks prior to - // APPS_LPDS_WAKETIME_WAKE_CFG, such - // that by the time actual wakeup is - // given, OPP is already switched to - // ACTIVE (RUN). - -#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_SRAM_DSLP_CFG register. -// -//****************************************************************************** -#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_M \ - 0x000FFFFF // Configuration of APPS Memories - // during Deep-sleep : 0 - SRAMs are - // OFF ; 1 - SRAMs are Retained. - // APPS SRAM Cluster information : - // [0] - 1st column in MEMSS - // (Applicable only when owned by - // APPS); [1] - 2nd column in MEMSS - // (Applicable only when owned by - // APPS); [2] - 3rd column in MEMSS - // (Applicable only when owned by - // APPS) ; [3] - 4th column in MEMSS - // (Applicable only when owned by - // APPS) ; [16] - MCU-PD - Apps - // cluster 0 (TBD); [19:18] - - // Reserved. - -#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_SRAM_LPDS_CFG register. -// -//****************************************************************************** -#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_M \ - 0x000FFFFF // Configuration of APPS Memories - // during LPDS : 0 - SRAMs are OFF ; - // 1 - SRAMs are Retained. APPS SRAM - // Cluster information : [0] - 1st - // column in MEMSS (Applicable only - // when owned by APPS); [1] - 2nd - // column in MEMSS (Applicable only - // when owned by APPS); [2] - 3rd - // column in MEMSS (Applicable only - // when owned by APPS) ; [3] - 4th - // column in MEMSS (Applicable only - // when owned by APPS) ; [16] - - // MCU-PD - Apps cluster 0 (TBD); - // [19:18] - Reserved. - -#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG register. -// -//****************************************************************************** -#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_M \ - 0xFFFFFFFF // Configuration (in no of - // slow_clks) which says when the - // actual wakeup request for - // removing the PD-reset be given. - -#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_TOP_DIE_ENABLE register. -// -//****************************************************************************** -#define GPRCM_TOP_DIE_ENABLE_FLASH_BUSY \ - 0x00001000 - -#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_M \ - 0x00000F00 - -#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_S 8 -#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE_STATUS \ - 0x00000002 // 1 - Top-die is enabled ; - -#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE \ - 0x00000001 // 1 - Enable the top-die ; 0 - - // Disable the top-die - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_TOP_DIE_ENABLE_PARAMETERS register. -// -//****************************************************************************** -#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_M \ - 0xF0000000 // Configuration (in slow_clks) for - // number of clks between - // Flash-3p3-rstn to D2D POR Resetn. - -#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_S 28 -#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_M \ - 0x00FF0000 // Configuration (in slow_clks) for - // number of clks between Top-die - // Switch-Enable and Top-die Flash - // 3p3 Reset removal - -#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_S 16 -#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_M \ - 0x000000FF // Configuration (in slow_clks) for - // number of clks between D2D POR - // Reset removal and bottom die FMC - // reset removal - -#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCU_GLOBAL_SOFT_RESET register. -// -//****************************************************************************** -#define GPRCM_MCU_GLOBAL_SOFT_RESET_MCU_GLOBAL_SOFT_RESET \ - 0x00000001 // 1 - Assert the global reset for - // MCU (APPS + NWP) ; Asserts both - // Cortex sysrstn and its - // peripherals 0 - Deassert the - // global reset for MCU (APPS + NWP) - // ; Asserts both Cortex sysrstn and - // its peripherals Note : Reset for - // shared peripherals is not - // affected here. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_ADC_CLK_CONFIG register. -// -//****************************************************************************** -#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_M \ - 0x000007C0 // Configuration (in number of 38.4 - // MHz clks) for the OFF-Time in - // generation of ADC_CLK - -#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_S 6 -#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_M \ - 0x0000003E // Configuration (in number of 38.4 - // MHz clks) for the ON-Time in - // generation of ADC_CLK - -#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_S 1 -#define GPRCM_ADC_CLK_CONFIG_ADC_CLK_ENABLE \ - 0x00000001 // 1 - Enable the ADC_CLK ; 0 - - // Disable the ADC_CLK - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_GPIO_WAKE_CONF register. -// -//****************************************************************************** -#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_M \ - 0x00000003 // "00" - Wake on Level0 on - // selected GPIO pin (GPIO is - // selected inside the HIB3p3 - // module); "01" - Wakeup on - // fall-edge of GPIO pin. - -#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_EN_NWP_BOOT_WO_DEVINIT register. -// -//****************************************************************************** -#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_M \ - 0xFFFFFFFE - -#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_S 1 -#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_mem_en_nwp_boot_wo_devinit \ - 0x00000001 // 1 - Override the secure-mode - // done for booting up NWP (Wakeup - // NWP on its event independent of - // CM4 state) ; 0 - Donot override - // the secure-mode done for NWP boot - // (NWP must be enabled by CM4 only) - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_HCLK_DIV_CFG register. -// -//****************************************************************************** -#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_M \ - 0x00000007 // Division configuration for - // HCLKDIVOUT : "000" - Divide by 1 - // ; "001" - Divide by 2 ; "010" - - // Divide by 3 ; "011" - Divide by 4 - // ; "100" - Divide by 5 ; "101" - - // Divide by 6 ; "110" - Divide by 7 - // ; "111" - Divide by 8 - -#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_SYSCLK_DIV_CFG register. -// -//****************************************************************************** -#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_M \ - 0x00000038 - -#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_S 3 -#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_M \ - 0x00000007 - -#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_LOCK_TIME_CONF register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_M \ - 0x0000FF00 - -#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_S 8 -#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_M \ - 0x000000FF - -#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_SOFT_RESET register. -// -//****************************************************************************** -#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET1 \ - 0x00000002 // Soft-reset1 for NWP - Cortex - // sysrstn and NWP associated - // peripherals are - This is an - // auto-clr bit. - -#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET0 \ - 0x00000001 // Soft-reset0 for NWP - Only - // Cortex-sysrstn is asserted - This - // is an auto-clear bit. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_LPDS_WAKEUP_CFG register. -// -//****************************************************************************** -#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_M \ - 0x000000FF // Mask for LPDS Wakeup interrupt : - // 7 - WLAN Host Interrupt ; 6 - - // WLAN to NWP Wake request ; 5 - - // APPS to NWP Wake request; 4 - - // GPIO Wakeup ; 3 - Autonomous UART - // Wakeup ; 2 - SSDIO Wakeup ; 1 - - // Autonomous SPI Wakeup ; 0 - LPDS - // Wakeup-timer - -#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_LPDS_WAKEUP_SRC register. -// -//****************************************************************************** -#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_M \ - 0x000000FF // Indicates the cause for NWP - // LPDS-Wakeup : 7 - WLAN Host - // Interrupt ; 6 - WLAN to NWP Wake - // request ; 5 - APPS to NWP Wake - // request; 4 - GPIO Wakeup ; 3 - - // Autonomous UART Wakeup ; 2 - - // SSDIO Wakeup ; 1 - Autonomous SPI - // Wakeup ; 0 - LPDS Wakeup-timer - -#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_RESET_CAUSE register. -// -//****************************************************************************** -#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_M \ - 0x000000FF // Indicates the reset cause for - // NWP : "0000" - Wake from HIB/OFF - // mode; "0001" - Wake from LPDS ; - // "0010" - Reserved ; "0011" - - // Soft-reset0 (Only NWP - // Cortex-sysrstn is asserted); - // "0100" - Soft-reset1 (NWP - // Cortex-sysrstn and NWP - // peripherals are reset); "0101" - - // WDOG0 (NWP Cortex-sysrstn and NWP - // peripherals are reset); "0110" - - // MCU Soft-reset (APPS + NWP - // Cortex-sysrstn + Peripherals are - // reset); "0111" - SSDIO Function2 - // reset (Only Cortex-sysrstn is - // asserted) ; "1000" - Reset due to - // WDOG of APPS (NWP Cortex-sysrstn - // and NWP peripherals are reset); - -#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG register. -// -//****************************************************************************** -#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_M \ - 0xFFFFFFFF // OPP Request Configuration - // (Number of slow-clk cycles) for - // LPDS Wake-timer - -#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_SRAM_DSLP_CFG register. -// -//****************************************************************************** -#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_M \ - 0x000FFFFF // Configuration of NWP Memories - // during DSLP : 0 - SRAMs are OFF ; - // 1 - SRAMs are Retained. NWP SRAM - // Cluster information : [2] - 3rd - // column in MEMSS (Applicable only - // when owned by NWP) ; [3] - 4th - // column in MEMSS (Applicable only - // when owned by NWP) ; [4] - 5th - // column in MEMSS (Applicable only - // when owned by NWP) ; [5] - 6th - // column in MEMSS (Applicable only - // when owned by NWP) ; [6] - 7th - // column in MEMSS (Applicable only - // when owned by NWP) ; [7] - 8th - // column in MEMSS (Applicable only - // when owned by NWP) ; [8] - 9th - // column in MEMSS (Applicable only - // when owned by NWP) ; [9] - 10th - // column in MEMSS (Applicable only - // when owned by NWP) ; [10] - 11th - // column in MEMSS (Applicable only - // when owned by NWP) ; [11] - 12th - // column in MEMSS (Applicable only - // when owned by NWP) ; [12] - 13th - // column in MEMSS (Applicable only - // when owned by NWP) ; [13] - 14th - // column in MEMSS (Applicable only - // when owned by NWP) ; [14] - 15th - // column in MEMSS (Applicable only - // when owned by NWP) ; [19:18] - - // Reserved. - -#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_SRAM_LPDS_CFG register. -// -//****************************************************************************** -#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_M \ - 0x000FFFFF // Configuration of NWP Memories - // during LPDS : 0 - SRAMs are OFF ; - // 1 - SRAMs are Retained. NWP SRAM - // Cluster information : [2] - 3rd - // column in MEMSS (Applicable only - // when owned by NWP) ; [3] - 4th - // column in MEMSS (Applicable only - // when owned by NWP) ; [4] - 5th - // column in MEMSS (Applicable only - // when owned by NWP) ; [5] - 6th - // column in MEMSS (Applicable only - // when owned by NWP) ; [6] - 7th - // column in MEMSS (Applicable only - // when owned by NWP) ; [7] - 8th - // column in MEMSS (Applicable only - // when owned by NWP) ; [8] - 9th - // column in MEMSS (Applicable only - // when owned by NWP) ; [9] - 10th - // column in MEMSS (Applicable only - // when owned by NWP) ; [10] - 11th - // column in MEMSS (Applicable only - // when owned by NWP) ; [11] - 12th - // column in MEMSS (Applicable only - // when owned by NWP) ; [12] - 13th - // column in MEMSS (Applicable only - // when owned by NWP) ; [13] - 14th - // column in MEMSS (Applicable only - // when owned by NWP) ; [14] - 15th - // column in MEMSS (Applicable only - // when owned by NWP) ; [19:18] - - // Reserved. - -#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG register. -// -//****************************************************************************** -#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_M \ - 0xFFFFFFFF // Wake time configuration (no of - // slow clks) for NWP wake from - // LPDS. - -#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL register. -// -//****************************************************************************** -#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_M \ - 0xFFFE0000 - -#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_S 17 -#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_MEM_AUTONMS_SPI_MASTER_SEL \ - 0x00010000 // 0 - APPS is selected as host for - // Autonms SPI ; 1 - External host - // is selected as host for Autonms - // SPI - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ register. -// -//****************************************************************************** -#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_WAKEUP \ - 0x00010000 - -#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_ACK \ - 0x00000002 // When 1 => IDLE-mode is - // acknowledged by the SPI-IP. (This - // is for MCSPI_N1) - -#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_REQ \ - 0x00000001 // When 1 => Request for IDLE-mode - // for autonomous SPI. (This is for - // MCSPI_N1) - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST register. -// -//****************************************************************************** -#define GPRCM_WLAN_TO_NWP_WAKE_REQUEST_WLAN_TO_NWP_WAKE_REQUEST \ - 0x00000001 // 1 - Request for waking up NWP - // from any of its low-power modes - // (SLP/DSLP/LPDS) - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST register. -// -//****************************************************************************** -#define GPRCM_NWP_TO_WLAN_WAKE_REQUEST_NWP_TO_WLAN_WAKE_REQUEST \ - 0x00000001 // 1 - Request for wakinp up WLAN - // from its ELP Mode (This gets - // triggered to ELP-logic of WLAN) - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_GPIO_WAKE_CONF register. -// -//****************************************************************************** -#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_M \ - 0x00000003 // "00" - Wakeup on level0 of the - // selected GPIO (GPIO gets selected - // inside HIB3P3-module); "01" - - // Wakeup on fall-edge of selected - // GPIO. - -#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG12 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_M \ - 0x0000FFFF // This corrsponds to ROW_32 - // [31:16] of the FUSEFARM. SPARE - -#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG5 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_M \ - 0xFFFFFFFF // Corresponds to ROW10 of FUSEFARM - // : [5:0] - ADC OFFSET ; [13:6] - - // TEMP_SENSE ; [14:14] - DFT_GSG ; - // [15:15] - FMC_DISABLE ; [31:16] - - // WLAN_MAC ID - -#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG6 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_M \ - 0xFFFFFFFF // Corresponds to ROW11 of FUSEFARM - // : [31:0] : WLAN MAC ID - -#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_FSM_CFG0 register. -// -//****************************************************************************** -#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_M \ - 0x00FF0000 // ANA-BGAP Settling time (In - // number of slow_clks) - -#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_S 16 -#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_M \ - 0x0000FF00 // Slicer LDO settling time (In - // number of slow clks) - -#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_S 8 -#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_M \ - 0x000000FF // Dig-buffer settling time (In - // number of slow clks) - -#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_FSM_CFG1 register. -// -//****************************************************************************** -#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_M \ - 0xFF000000 // XTAL settling time (In number of - // slow clks) - -#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_S 24 -#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_M \ - 0x00FF0000 // LV Slicer settling time - -#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_S 16 -#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_M \ - 0x0000FF00 // HV Slicer Pull-down settling - // time - -#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_S 8 -#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_M \ - 0x000000FF // HV Slicer settling time - -#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_WLAN_CONFIG0_40 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_M \ - 0x00007F00 // Configuration for WLAN APLLMCS - - // N[6:0], if the XTAL frequency is - // 40 MHz (Selected by efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_S 8 -#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_M \ - 0x000000FF // Configuration for WLAN APLLMCS - - // M[7:0], if the XTAL frequency is - // 40 MHz (Selected by efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_WLAN_CONFIG1_40 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_HISPEED_40 \ - 0x00000010 // Configuration for WLAN APLLMCS - - // if the XTAL frequency if 40 MHz - // (Selected by Efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SEL96_40 \ - 0x00000008 // Configuration for WLAN APLLMCS - - // Sel96, if the XTAL frequency is - // 40 MHz (Selected by Efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_M \ - 0x00000007 // Configuration for WLAN APLLMCS - - // Selinpfreq, if the XTAL frequency - // is 40 MHz (Selected by Efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_WLAN_CONFIG0_26 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_M \ - 0x00007F00 // Configuration for WLAN APLLMCS - - // N[6:0], if the XTAL frequency is - // 26 MHz (Selected by efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_S 8 -#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_M \ - 0x000000FF // Configuration for WLAN APLLMCS - - // M[7:0], if the XTAL frequency is - // 26 MHz (Selected by efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_WLAN_CONFIG1_26 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_HISPEED_26 \ - 0x00000010 // Configuration for WLAN APLLMCS - - // if the XTAL frequency if 26 MHz - // (Selected by Efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SEL96_26 \ - 0x00000008 // Configuration for WLAN APLLMCS - - // Sel96, if the XTAL frequency is - // 26 MHz (Selected by Efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_M \ - 0x00000007 // Configuration for WLAN APLLMCS - - // Selinpfreq, if the XTAL frequency - // is 26 MHz (Selected by Efuse) - -#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_WLAN_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_CTRL \ - 0x00080000 - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_M \ - 0x00070000 - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_S 16 -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_M \ - 0x00000700 - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_S 8 -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE_CTRL \ - 0x00000020 // Override control for - // WLAN_APLLMCS_M[8]. When set to1, - // M[8] will be selected by bit [3]. - // (Else controlled from WTOP) - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE \ - 0x00000010 // Override for WLAN_APLLMCS_M[8]. - // Applicable only when bit [4] is - // set to 1. (Else controlled from - // WTOP) - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_CTRL \ - 0x00000004 // Override control for - // WLAN_APLLMCS_N[8:7]. When set - // to1, N[8:7] will be selected by - // bits [2:1]. (Else controlled from - // WTOP) - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_M \ - 0x00000003 // Override value for - // WLAN_APLLMCS_N[8:7] bits. - // Applicable only when bit [1] is - // set to 1. (Else controlled from - // WTOP) - -#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_M \ - 0x38000000 - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_S 27 -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_M \ - 0x07000000 - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_S 24 -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_M \ - 0x007F0000 // Configuration for MCU-APLLMCS : - // N during RUN mode. Selected if - // the XTAL frequency is 38.4 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_S 16 -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_M \ - 0x0000FF00 // Configuration for MCU-APLLMCS : - // M during RUN mode. Selected if - // the XTAL frequency is 38.4 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_S 8 -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_8_38P4 \ - 0x00000010 // Configuration for MCU-APLLMCS : - // M[8] during RUN mode. Selected if - // the XTAL frequency is 38.4 MHz - // (From Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_M \ - 0x00000003 // Configuration for MCU-APLLMCS : - // N[8:7] during RUN mode. Selected - // if the XTAL frequency is 38.4 MHz - // (From Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_HISPEED_38P4 \ - 0x00000010 // Configuration for MCU-APLLMCS : - // HISPEED during RUN mode. Selected - // if the XTAL frequency is 38.4 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SEL96_38P4 \ - 0x00000008 // Configuration for MCU-APLLMCS : - // SEL96 during RUN mode. Selected - // if the XTAL frequency is 38.4 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_M \ - 0x00000007 // Configuration for MCU-APLLMCS : - // SELINPFREQ during RUN mode. - // Selected if the XTAL frequency is - // 38.4 MHz (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_M \ - 0x007F0000 // Configuration for MCU-APLLMCS : - // N during RUN mode. Selected if - // the XTAL frequency is 26 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_S 16 -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_M \ - 0x0000FF00 // Configuration for MCU-APLLMCS : - // M during RUN mode. Selected if - // the XTAL frequency is 26 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_S 8 -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_8_26 \ - 0x00000010 // Configuration for MCU-APLLMCS : - // M[8] during RUN mode. Selected if - // the XTAL frequency is 26 MHz - // (From Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_M \ - 0x00000003 // Configuration for MCU-APLLMCS : - // N[8:7] during RUN mode. Selected - // if the XTAL frequency is 26 MHz - // (From Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_HISPEED_26 \ - 0x00000010 // Configuration for MCU-APLLMCS : - // HISPEED during RUN mode. Selected - // if the XTAL frequency is 26 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SEL96_26 \ - 0x00000008 // Configuration for MCU-APLLMCS : - // SEL96 during RUN mode. Selected - // if the XTAL frequency is 26 MHz - // (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_M \ - 0x00000007 // Configuration for MCU-APLLMCS : - // SELINPFREQ during RUN mode. - // Selected if the XTAL frequency is - // 26 MHz (from Efuse) - -#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the GPRCM_O_SPARE_RW0 register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the GPRCM_O_SPARE_RW1 register. -// -//****************************************************************************** -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APLLMCS_MCU_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_LOCK \ - 0x00000400 // 1 - APLLMCS_MCU is locked ; 0 - - // APLLMCS_MCU is not locked - -#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE \ - 0x00000200 // Override for APLLMCS_MCU Enable. - // Applicable if bit [8] is set - -#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE_CTRL \ - 0x00000100 // 1 - Enable for APLLMCS_MCU comes - // from bit [9]. 0 - Enable for - // APLLMCS_MCU comes from FSM. - -#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_M \ - 0x00000006 // Override for sysclk src - // (applicable only if bit [0] is - // set to 1. "00"- SLOW_CLK "01"- - // XTAL_CLK "10"- PLL_CLK - -#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_S 1 -#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_CTRL \ - 0x00000001 // 1 - Sysclk src is selected from - // bits [2:1] of this register. 0 - - // Sysclk src is selected from FSM - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_SYSCLK_SWITCH_STATUS register. -// -//****************************************************************************** -#define GPRCM_SYSCLK_SWITCH_STATUS_SYSCLK_SWITCH_STATUS \ - 0x00000001 // 1 - Sysclk switching is - // complete. 0 - Sysclk switching is - // in progress. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_LDO_CONTROLS register. -// -//****************************************************************************** -#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE_OVERRIDE_CTRL \ - 0x00010000 // 1 - Enable for REF_LDO comes - // from bit [0] of this register ; 0 - // - Enable for REF_LDO comes from - // the FSM. Note : Final REF_LDO_EN - // reaches on the port - // TOP_PM_REG2[0] of gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_M \ - 0x0000C000 // Spare bits for REF_CTRL_FSM. - // Reaches directly on port - // TOP_PM_REG2[15:14] of gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_S 14 -#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_M \ - 0x00003800 // REF TLOAD Enable. Reaches - // directly on port - // TOP_PM_REG2[13:11] of gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_S 11 -#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_M \ - 0x00000700 // REF_LDO Test-mux control. - // Reaches directly on port - // TOP_PM_REG2[10:8] of gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_S 8 -#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_M \ - 0x000000C0 // REF BW Control. Reaches directly - // on port TOP_PM_REG2[7:6] of - // gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_S 6 -#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_M \ - 0x0000003C // REF VTRIM Control. Reaches - // directly on port TOP_PM_REG2[5:2] - // of gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_S 2 -#define GPRCM_REF_LDO_CONTROLS_REF_LDO_BYPASS_ENABLE \ - 0x00000002 // REF LDO Bypass Enable. Reaches - // directly on port TOP_PM_REG2[1] - // of gprcm. - -#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE \ - 0x00000001 // Override for REF_LDO Enable. - // Applicable only if bit [16] of - // this register is set. Note : - // Final REF_LDO_EN reaches on the - // port TOP_PM_REG2[0] of gprcm. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_RTRIM_CONTROL register. -// -//****************************************************************************** -#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_M \ - 0x18000000 // This is [5:4] bits of - // TOP_PM_REG0 - -#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_S 27 -#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_M \ - 0x07FF0000 // This is [15:5] bits of - // TOP_CLKM_REG0 - -#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_S 16 -#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_OVERRIDE_CTRL \ - 0x00000100 // 1 - CLKM_RTRIM comes for - // bits[4:0] of this register. 0 - - // CLKM_RTRIM comes from Efuse - // (after efuse_done = 1). - -#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_M \ - 0x0000001F // CLKM_TRIM Override. Applicable - // when efuse_done = 0 or bit[8] is - // set to 1. - -#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_SLICER_CONTROLS0 register. -// -//****************************************************************************** -#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV_OVERRIDE_CTRL \ - 0x00200000 // 1 - EN_DIG_BUF_TOP comes from - // bit [14] of this register. 0 - - // EN_DIG_BUF_TOP comes from the - // FSM. Note : Final EN_DIG_BUF_WLAN - // reaches on TOP_CLKM_REG1_IN[14] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV_OVERRIDE_CTRL \ - 0x00100000 // 1 - EN_DIG_BUF_TOP comes from - // bit [15] of this register. 0 - - // EN_DIG_BUF_TOP comes from the - // FSM. Note : Final EN_DIG_BUF_TOP - // reaches on TOP_CLKM_REG1_IN[15] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL_OVERRIDE_CTRL \ - 0x00080000 // 1 - EN_XTAL comes from bit [3] - // of this register. 0 - EN_XTAL - // comes from FSM. Note : Final - // XTAL_EN reaches on - // TOP_CLKM_REG1_IN[3] of gprcm. - -#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_OVERRIDE_CTRL \ - 0x00040000 // 1 - Enable HV Slicer comes from - // bit [2] of this register. 0 - - // Enable HV Slicer comes from FSM. - // Note : Final HV_SLICER_EN reaches - // on port TOP_CLKM_REG1_IN[1] of - // gprcm. - -#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_LV_OVERRIDE_CTRL \ - 0x00020000 // 1 - Enable LV Slicer comes from - // bit[1] of this register. 0 - - // Enable LV Slicer comes from FSM. - // Note : final LV_SLICER_EN reaches - // on port TOP_CLKM_REG1_IN[2] of - // gprcm. - -#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_PDN_OVERRIDE_CTRL \ - 0x00010000 // 1 - Enable HV Pull-down comes - // from bit[0] of this register. 0 - - // Enable HV Pull-down comes from - // FSM. Note : Final HV_PULL_DOWN - // reaches on port - // TOP_CLKM_REG1_IN[0] of gprcm. - -#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV \ - 0x00008000 // Override for EN_DIG_BUF_TOP. - // Applicable if bit[20] is set to - // 1. Note : Final EN_DIG_BUF_TOP - // reaches on TOP_CLKM_REG1_IN[15] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV \ - 0x00004000 // Override for EN_DIG_BUF_WLAN. - // Applicable if bit[19] is set to - // 1. Note : Final EN_DIG_BUF_WLAN - // reaches on TOP_CLKM_REG1_IN[14] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_CLKOUT_FLIP_EN \ - 0x00002000 // CLKOUT Flip Enable. Reaches on - // bit[13] of TOP_CLKM_REG1_IN[13] - // port of gprcm. - -#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV2_WLAN_CLK \ - 0x00001000 // Enable divide2 in WLAN Clk-path. - // Reaches on TOP_CLKM_REG1_IN[12] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV3_WLAN_CLK \ - 0x00000800 // Enable divide3 in WLAN Clk-path. - // Reaches on TOP_CLKM_REG1_IN[11] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV4_WLAN_CLK \ - 0x00000400 // Enable divide4 in WLAN Clk-path. - // Reaches on TOP_CLKM_REG1_IN[10] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_M \ - 0x000003C0 // CM Test-mux select. Reaches on - // TOP_CLMM_REG1_IN[9:6] port of - // gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_S 6 -#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_M \ - 0x00000030 // Slicer spare0 control. Reaches - // on TOP_CLKM_REG1_IN[5:4] port of - // gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_S 4 -#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL \ - 0x00000008 // Enable XTAL override. Reaches on - // TOP_CLKM_REG1_IN[3] port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV \ - 0x00000004 // Enable HV Slicer override. - // Reaches on TOP_CLKM_REG1_IN[1] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_LV \ - 0x00000002 // Enable LV Slicer override. - // Reaches on TOP_CLKM_REG1_IN[2] - // port of gprcm - -#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV_PDN \ - 0x00000001 // Enable HV Pull-down override. - // Reaches on TOP_CLKM_REG1_IN[0] - // port of gprcm - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_SLICER_CONTROLS1 register. -// -//****************************************************************************** -#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_M \ - 0x0000FC00 // Slicer spare1. Reaches on port - // TOP_CLKM_REG2_IN[15:10] of gprcm. - -#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_S 10 -#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_M \ - 0x000003F0 // XOSC Trim. Reaches on port - // TOP_CLKM_REG2_IN[9:4] of gprcm - -#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_S 4 -#define GPRCM_REF_SLICER_CONTROLS1_SLICER_ITRIM_CHANGE_TOGGLE \ - 0x00000008 // Slicer ITRIM Toggle. Reaches on - // port TOP_CLKM_REG2_IN[3] of - // gprcm. - -#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_M \ - 0x00000007 // LV Slicer trim. Reaches on port - // TOP_CLKM_REG2_IN[2:0] of gprcm. - -#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_ANA_BGAP_CONTROLS0 register. -// -//****************************************************************************** -#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_M \ - 0xFF800000 - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_S 23 -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_mag_trim_override_ctrl \ - 0x00400000 // 1 - REF_MAG_TRIM comes from - // bit[4:0] of register - // REF_ANA_BGAP_CONTROLS1 [Addr : - // 0x0850]; 0 - REF_MAG_TRIM comes - // from efuse (After efc_done = 1). - // Note : Final REF_MAG_TRIM reaches - // on port TOP_PM_REG1[4:0] of gprcm - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_override_ctrl \ - 0x00200000 // 1 - REF_V2I_TRIM comes from - // bit[9:6] of this register ; 0 - - // REF_V2I_TRIM comes from efuse - // (After efc_done = 1). Note : - // Final REF_V2I_TRIM reaches on - // port TOP_PM_REG0[9:6] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_override_ctrl \ - 0x00100000 // 1 - REF_TEMP_TRIM comes from - // bit[15:10] of this register ; 0 - - // REF_TEMP_TRIM comes from efuse - // (After efc_done = 1). Note : - // Final REF_TEMP_TRIM reaches on - // port TOP_PM_REG0[15:10] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en_override_ctrl \ - 0x00080000 // 1 - REF_STARTUP_EN comes from - // bit [3] of this register ; 0 - - // REF_STARTUP_EN comes from FSM. - // Note : Final REF_STARTUP_EN - // reaches on port TOP_PM_REG0[3] of - // gprcm - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en_override_ctrl \ - 0x00040000 // 1 - REF_V2I_EN comes from bit - // [2] of this register ; 0 - - // REF_V2I_EN comes from FSM. Note : - // Final REF_V2I_EN reaches on port - // TOP_PM_REG0[2] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en_override_ctrl \ - 0x00020000 // 1 - REF_FC_EN comes from bit [1] - // of this register ; 0 - REF_FC_EN - // comes from FSM. Note : Final - // REF_FC_EN reaches on port - // TOP_PM_REG0[1] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en_override_ctrl \ - 0x00010000 // 1 - REF_BGAP_EN comes from bit - // [0] of this register ; 0 - - // REF_BGAP_EN comes from FSM. Note - // : Final REF_BGAP_EN reaches on - // port TOP_PM_REG0[0] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_M \ - 0x0000FC00 // REF_TEMP_TRIM override. - // Applicable when bit [20] of this - // register set to 1. (or efc_done = - // 0) Note : Final REF_TEMP_TRIM - // reaches on port - // TOP_PM_REG0[15:10] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_S 10 -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_M \ - 0x000003C0 // REF_V2I_TRIM Override. - // Applicable when bit [21] of this - // register set to 1 . (of efc_done - // = 0) Note : Final REF_V2I_TRIM - // reaches on port TOP_PM_REG0[9:6] - // of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_S 6 -#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_M \ - 0x00000030 - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_S 4 -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en \ - 0x00000008 // REF_STARTUP_EN override. - // Applicable when bit [19] of this - // register is set to 1. Note : - // Final REF_STARTUP_EN reaches on - // port TOP_PM_REG0[3] of gprcm - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en \ - 0x00000004 // REF_V2I_EN override. Applicable - // when bit [21] of this register is - // set to 1. Note : Final REF_V2I_EN - // reaches on port TOP_PM_REG0[2] of - // gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en \ - 0x00000002 // REF_FC_EN override. Applicable - // when bit [17] of this register is - // set to 1. Note : Final REF_FC_EN - // reaches on port TOP_PM_REG0[1] of - // gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en \ - 0x00000001 // REF_BGAP_EN override. Applicable - // when bit [16] of this register - // set to 1. Note : Final - // REF_BGAP_EN reaches on port - // TOP_PM_REG0[0] of gprcm. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_ANA_BGAP_CONTROLS1 register. -// -//****************************************************************************** -#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_M \ - 0xFFFF0000 - -#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_S 16 -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_M \ - 0x0000C000 // REF_BGAP_SPARE. Reaches on port - // TOP_PM_REG1[15:14] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_S 14 -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_M \ - 0x00003E00 // REF_BGAP_TMUX_CTRL. Reaches on - // port TOP_PM_REG1[13:9] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_S 9 -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_M \ - 0x000001E0 // REF_FILT_TRIM. Reaches on port - // TOP_PM_REG1[8:5] of gprcm. - -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_S 5 -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_M \ - 0x0000001F // REF_MAG_TRIM Override. - // Applicable when bit[22] of - // REF_ANA_BGAP_CONTROLS0 [0x084C] - // set to 1 (of efc_done = 0). Note - // : Final REF_MAG_TRIM reaches on - // port TOP_PM_REG1[4:0] of gprcm - -#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_ANA_SPARE_CONTROLS0 register. -// -//****************************************************************************** -#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_M \ - 0xFFFF0000 - -#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_S 16 -#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_M \ - 0x0000FFFF // Spare control. Reaches on - // TOP_PM_REG3 [15:0] of gprcm. - -#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_ANA_SPARE_CONTROLS1 register. -// -//****************************************************************************** -#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_M \ - 0xFFFF0000 // Spare control. Reaches on - // TOP_CLKM_REG3 [15:0] of gprcm. - -#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_S 16 -#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_M \ - 0x0000FFFF // Spare control. Reaches on - // TOP_CLKM_REG4 [15:0] of gprcm. - -#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEMSS_PSCON_OVERRIDES0 register. -// -//****************************************************************************** -#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_M \ - 0xFFFF0000 - -#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_S 16 -#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_M \ - 0x0000FFFF - -#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEMSS_PSCON_OVERRIDES1 register. -// -//****************************************************************************** -#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_M \ - 0xFFFFFFC0 - -#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_S 6 -#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override_ctrl \ - 0x00000020 - -#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override \ - 0x00000010 - -#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override_ctrl \ - 0x00000008 - -#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override \ - 0x00000004 - -#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_off_override_ctrl \ - 0x00000002 - -#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memms_pscon_mem_retain_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_PLL_REF_LOCK_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_M \ - 0xFFFFFFF8 - -#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_S 3 -#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_mcu_apllmcs_lock_override \ - 0x00000004 - -#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_wlan_apllmcs_lock_override \ - 0x00000002 - -#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_ref_clk_valid_override \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCU_PSCON_DEBUG register. -// -//****************************************************************************** -#define GPRCM_MCU_PSCON_DEBUG_reserved_M \ - 0xFFFFFFC0 - -#define GPRCM_MCU_PSCON_DEBUG_reserved_S 6 -#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_M \ - 0x00000038 // MCU_PSCON_RTC_ON = "0000"; - // MCU_PSCON_RTC_OFF = "0001"; - // MCU_PSCON_RTC_RET = "0010"; - // MCU_PSCON_RTC_OFF_TO_ON = "0011"; - // MCU_PSCON_RTC_RET_TO_ON = "0100"; - // MCU_PSCON_RTC_ON_TO_RET = "0101"; - // MCU_PSCON_RTC_ON_TO_OFF = "0110"; - // MCU_PSCON_RTC_RET_TO_ON_WAIT_OPP - // = "0111"; - // MCU_PSCON_RTC_OFF_TO_ON_WAIT_OPP - // = "1000"; - -#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_S 3 -#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_M \ - 0x00000007 - -#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEMSS_PWR_PS register. -// -//****************************************************************************** -#define GPRCM_MEMSS_PWR_PS_reserved_M \ - 0xFFFFFFF8 - -#define GPRCM_MEMSS_PWR_PS_reserved_S 3 -#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_M \ - 0x00000007 // MEMSS_PM_SLEEP = "000"; - // MEMSS_PM_WAIT_OPP = "010"; - // MEMSS_PM_ACTIVE = "011"; - // MEMSS_PM_SLEEP_TO_ACTIVE = "100"; - // MEMSS_PM_ACTIVE_TO_SLEEP = "101"; - -#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_REF_FSM_DEBUG register. -// -//****************************************************************************** -#define GPRCM_REF_FSM_DEBUG_reserved_M \ - 0xFFFFFFC0 - -#define GPRCM_REF_FSM_DEBUG_reserved_S 6 -#define GPRCM_REF_FSM_DEBUG_fref_mode_M \ - 0x00000030 // 01 - HV Mode ; 10 - LV Mode ; 11 - // - XTAL Mode - -#define GPRCM_REF_FSM_DEBUG_fref_mode_S 4 -#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_M \ - 0x0000000F // constant FREF_CLK_OFF = "00000"; - // constant FREF_EN_BGAP = "00001"; - // constant FREF_EN_LDO = "00010"; - // constant FREF_EN_SLI_HV = - // "00011"; constant - // FREF_EN_SLI_HV_PD = "00100"; - // constant FREF_EN_DIG_BUF = - // "00101"; constant FREF_EN_OSC = - // "00110"; constant FREF_EN_SLI_LV - // = "00111"; constant - // FREF_EN_CLK_REQ = "01000"; - // constant FREF_CLK_VALID = - // "01001"; constant FREF_MODE_DET0 - // = "01010"; constant - // FREF_MODE_DET1 = "01011"; - // constant FREF_MODE_DET2 = - // "10010"; constant FREF_MODE_DET3 - // = "10011"; constant FREF_VALID = - // "01100"; constant FREF_VALID0 = - // "01101"; constant FREF_VALID1 = - // "01110"; constant FREF_VALID2 = - // "01111"; constant - // FREF_WAIT_EXT_TCXO0 = "10000"; - // constant FREF_WAIT_EXT_TCXO1 = - // "10001"; - -#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE register. -// -//****************************************************************************** -#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_M \ - 0xFFFFFFE0 - -#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_S 5 -#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_ctrl \ - 0x00000010 // 1 - Override the sytem-opp - // request to ANATOP using bit0 of - // this register - -#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_M \ - 0x0000000F // "0001" - RUN ; "0010" - DSLP ; - // "0100" - LPDS ; Others - NA - -#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG register. -// -//****************************************************************************** -#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_M \ - 0xFFFFFFFE - -#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_S 1 -#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_mem_sleep_opp_enter_with_testpd_on \ - 0x00000001 // 1 - Enable sleep-opp (DSLP/LPDS) - // entry even if Test-Pd is kept ON - // ; 0 - Donot enable sleep-opp - // (DSLP/LPDS) entry with Test-Pd - // ON. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_M \ - 0xFFFFFFF8 - -#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_S 3 -#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override_ctrl \ - 0x00000004 // NA - -#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override \ - 0x00000002 // NA - -#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_sleep_with_clk_req_override \ - 0x00000001 // NA - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_mode_req_override_ctrl \ - 0x00000004 // 1 - Override the MCU-PD power - // modes using bits [1] & [0] ; - -#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_pwrdn_req_override \ - 0x00000002 // 1 - Request for power-down of - // MCU-PD ; - -#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_ret_req_override \ - 0x00000001 // 1 - Request for retention mode - // of MCU-PD. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override_ctrl \ - 0x00000002 // 1- Override the MCSPI - // (Autonomous SPI) memory state - // using bit [0] - -#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override \ - 0x00000001 // 1 - Request for power-down of - // Autonomous SPI 8k memory ; 0 - - // Donot request power-down of - // Autonomous SPI 8k Memory - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_wlan_apllmcs_lock \ - 0x00000100 - -#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override \ - 0x00000002 - -#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_REF_FSM_CFG2 register. -// -//****************************************************************************** -#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_M \ - 0x00380000 // Number of RTC clocks for keeping - // the FC_EN asserted high - -#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_S 19 -#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_M \ - 0x00070000 // Number of RTC clocks for keeping - // the STARTUP_EN asserted high - -#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_S 16 -#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_M \ - 0x0000FFFF // Number of RTC clocks for waiting - // for clock to settle. - -#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_TESTCTRL_POWER_CTRL register. -// -//****************************************************************************** -#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_M \ - 0x00000006 - -#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_S 1 -#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_ENABLE \ - 0x00000001 // 0 - Disable the TestCtrl-pd ; 1 - // - Enable the TestCtrl-pd. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_SSDIO_POWER_CTRL register. -// -//****************************************************************************** -#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_M \ - 0x00000006 // 1 - SSDIO-PD is ON ; 0 - - // SSDIO-PD is OFF - -#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_S 1 -#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_ENABLE \ - 0x00000001 // 0 - Disable the SSDIO-pd ; 1 - - // Enable the SSDIO-pd. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCSPI_N1_POWER_CTRL register. -// -//****************************************************************************** -#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_M \ - 0x00000006 // 1 - MCSPI_N1-PD is ON ; 0 - - // MCSPI_N1-PD if OFF - -#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_S 1 -#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_ENABLE \ - 0x00000001 // 0 - Disable the MCSPI_N1-pd ; 1 - // - Enable the MCSPI_N1-pd. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WELP_POWER_CTRL register. -// -//****************************************************************************** -#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_M \ - 0x00001C00 - -#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_S 10 -#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE \ - 0x00000200 - -#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE_CTRL \ - 0x00000100 - -#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_M \ - 0x00000006 - -#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_S 1 -#define GPRCM_WELP_POWER_CTRL_WELP_PD_ENABLE \ - 0x00000001 // 0 - Disable the WELP-pd ; 1 - - // Enable the WELP-pd. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WL_SDIO_POWER_CTRL register. -// -//****************************************************************************** -#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_M \ - 0x00000006 - -#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_S 1 -#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_ENABLE \ - 0x00000001 // 0 - Disable the WL_SDIO-pd ; 1 - - // Enable the WL_SDIO-pd. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG register. -// -//****************************************************************************** -#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_M \ - 0x00FFFFFF // SRAM (WTOP+DRP) state during - // Active-mode : 1 - SRAMs are ON ; - // 0 - SRAMs are OFF. Cluster - // information : [0] - 1st column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) [1] - 2nd column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) ; [2] - 3rd column - // of MEMSS (Applicable only when - // owned by WTOP/PHY) ; [3] - 4th - // column of MEMSS (Applicable only - // when owned by WTOP/PHY) ; [4] - - // 5th column of MEMSS (Applicable - // only when owned by WTOP/PHY) ; - // [5] - 6th column of MEMSS - // (Applicable only when owned by - // WTOP/PHY) ; [6] - 7th column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) ; [7] - 8th column - // of MEMSS (Applicable only when - // owned by WTOP/PHY) ; [8] - 9th - // column of MEMSS (Applicable only - // when owned by WTOP/PHY) ; [9] - - // 10th column of MEMSS (Applicable - // only when owned by WTOP/PHY) ; - // [10] - 11th column of MEMSS - // (Applicable only when owned by - // WTOP/PHY) ; [11] - 12th column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) ; [12] - 13th column - // of MEMSS (Applicable only when - // owned by WTOP/PHY) ; [13] - 14th - // column of MEMSS (Applicable only - // when owned by WTOP/PHY) ; [14] - - // 15th column of MEMSS (Applicable - // only when owned by WTOP/PHY) ; - // [15] - 16th column of MEMSS - // (Applicable only when owned by - // WTOP/PHY) ; [23:16] - Internal to - // WTOP Cluster - -#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG register. -// -//****************************************************************************** -#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_M \ - 0x00FFFFFF // SRAM (WTOP+DRP) state during - // Sleep-mode : 1 - SRAMs are RET ; - // 0 - SRAMs are OFF. Cluster - // information : [0] - 1st column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) [1] - 2nd column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) ; [2] - 3rd column - // of MEMSS (Applicable only when - // owned by WTOP/PHY) ; [3] - 4th - // column of MEMSS (Applicable only - // when owned by WTOP/PHY) ; [4] - - // 5th column of MEMSS (Applicable - // only when owned by WTOP/PHY) ; - // [5] - 6th column of MEMSS - // (Applicable only when owned by - // WTOP/PHY) ; [6] - 7th column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) ; [7] - 8th column - // of MEMSS (Applicable only when - // owned by WTOP/PHY) ; [8] - 9th - // column of MEMSS (Applicable only - // when owned by WTOP/PHY) ; [9] - - // 10th column of MEMSS (Applicable - // only when owned by WTOP/PHY) ; - // [10] - 11th column of MEMSS - // (Applicable only when owned by - // WTOP/PHY) ; [11] - 12th column of - // MEMSS (Applicable only when owned - // by WTOP/PHY) ; [12] - 13th column - // of MEMSS (Applicable only when - // owned by WTOP/PHY) ; [13] - 14th - // column of MEMSS (Applicable only - // when owned by WTOP/PHY) ; [14] - - // 15th column of MEMSS (Applicable - // only when owned by WTOP/PHY) ; - // [15] - 16th column of MEMSS - // (Applicable only when owned by - // WTOP/PHY) ; [23:16] - Internal to - // WTOP Cluster - -#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_SECURE_INIT_DONE register. -// -//****************************************************************************** -#define GPRCM_APPS_SECURE_INIT_DONE_SECURE_INIT_DONE_STATUS \ - 0x00000002 // 1-Secure mode init is done ; - // 0-Secure mode init is not done - -#define GPRCM_APPS_SECURE_INIT_DONE_APPS_SECURE_INIT_DONE \ - 0x00000001 // Must be programmed 1 in order to - // say that secure-mode device init - // is done - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_DEV_MODE_INIT_DONE register. -// -//****************************************************************************** -#define GPRCM_APPS_DEV_MODE_INIT_DONE_APPS_DEV_MODE_INIT_DONE \ - 0x00000001 // 1 - Patch download and other - // initializations are done (before - // removing APPS resetn) for - // development mode (#3) . 0 - - // Development mode (#3) init is not - // done yet - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_EN_APPS_REBOOT register. -// -//****************************************************************************** -#define GPRCM_EN_APPS_REBOOT_EN_APPS_REBOOT \ - 0x00000001 // 1 - When 1, disable the reboot - // of APPS after DevInit is - // completed. In this case, APPS - // will permanantly help in reset. 0 - // - When 0, enable the reboot of - // APPS after DevInit is completed. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_APPS_PERIPH_PRESENT register. -// -//****************************************************************************** -#define GPRCM_MEM_APPS_PERIPH_PRESENT_WLAN_GEM_PP \ - 0x00010000 // 1 - Enable ; 0 - Disable - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_AES_PP \ - 0x00008000 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_DES_PP \ - 0x00004000 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_SHA_PP \ - 0x00002000 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_CAMERA_PP \ - 0x00001000 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MMCHS_PP \ - 0x00000800 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCASP_PP \ - 0x00000400 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A1_PP \ - 0x00000200 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A2_PP \ - 0x00000100 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UDMA_PP \ - 0x00000080 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_WDOG_PP \ - 0x00000040 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A0_PP \ - 0x00000020 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A1_PP \ - 0x00000010 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A0_PP \ - 0x00000008 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A1_PP \ - 0x00000004 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A2_PP \ - 0x00000002 - -#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A3_PP \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_NWP_PERIPH_PRESENT register. -// -//****************************************************************************** -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_ASYNC_BRIDGE_PP \ - 0x00000200 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N2_PP \ - 0x00000100 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N0_PP \ - 0x00000080 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N1_PP \ - 0x00000040 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_WDOG_PP \ - 0x00000020 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UDMA_PP \ - 0x00000010 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N0_PP \ - 0x00000008 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N1_PP \ - 0x00000004 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_SSDIO_PP \ - 0x00000002 - -#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N1_PP \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MEM_SHARED_PERIPH_PRESENT register. -// -//****************************************************************************** - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_MCSPI_PP \ - 0x00000040 - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_I2C_PP \ - 0x00000020 - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_A_PP \ - 0x00000010 - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_B_PP \ - 0x00000008 - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_C_PP \ - 0x00000004 - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_D_PP \ - 0x00000002 - -#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_E_PP \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_PWR_STATE register. -// -//****************************************************************************** -#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_M \ - 0x00000F00 // "0000"- PORZ :- NWP is yet to be - // enabled by APPS during powerup - // (from HIB/OFF) ; "0011"- ACTIVE - // :- NWP is enabled, clocks and - // resets to NWP-SubSystem are - // enabled ; "0010"- LPDS :- NWP is - // in LPDS-mode ; Clocks and reset - // to NWP-SubSystem are gated ; - // "0101"- WAIT_FOR_OPP :- NWP is in - // transition from LPDS to ACTIVE, - // where it is waiting for OPP to be - // stable ; "1000"- - // WAKE_TIMER_OPP_REQ :- NWP is in - // transition from LPDS, where the - // wakeup cause is LPDS_Wake timer - // OTHERS : NA - -#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_S 8 -#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_M \ - 0x00000007 // "000" - NWP_RUN : NWP is in RUN - // state (default) - Applicable only - // when NWP_PWR_STATE_PS = ACTIVE ; - // "001" - NWP_SLP : NWP is in SLEEP - // state (default) - Applicable only - // when NWP_PWR_STATE_PS = ACTIVE ; - // "010" - NWP_DSLP : NWP is in - // Deep-Sleep state (default) - - // Applicable only when - // NWP_PWR_STATE_PS = ACTIVE ; "011" - // - WAIT_FOR_ACTIVE : NWP is in - // transition from Deep-sleep to - // Run, where it is waiting for OPP - // to be stable ; "100" - - // WAIT_FOR_DSLP_TIMER_WAKE_REQ : - // NWP is in transition from - // Deep-sleep to Run, where the - // wakeup cause is deep-sleep - // wake-timer - -#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_PWR_STATE register. -// -//****************************************************************************** -#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_M \ - 0x00000F00 // "0000"- PORZ :- APPS is waiting - // for PLL_clock during powerup - // (from HIB/OFF) ; "0011"- ACTIVE - // :- APPS is enabled, clocks and - // resets to APPS-SubSystem are - // enabled ; APPS might be either in - // Secure or Un-secure mode during - // this state. "1001" - - // SECURE_MODE_LPDS :- While in - // ACTIVE (Secure-mode), APPS had to - // program the DevInit_done bit at - // the end, after which it enters - // into this state, where the reset - // to APPS will be asserted. From - // this state APPS might either - // re-boot itself or enter into LPDS - // depending upon whether the device - // is 3200 or 3100. "0010"- LPDS :- - // APPS is in LPDS-mode ; Clocks and - // reset to APPS-SubSystem are gated - // ; "0101"- WAIT_FOR_OPP :- APPS is - // in transition from LPDS to - // ACTIVE, where it is waiting for - // OPP to be stable ; "1000" - - // WAKE_TIMER_OPP_REQ : APPS is in - // transition from LPDS, where the - // wakeup cause is LPDS_Wake timer ; - // "1010" - WAIT_FOR_PATCH_INIT : - // APPS enters into this state - // during development-mode #3 (SOP = - // 3), where it is waiting for patch - // download to complete and 0x4 hack - // is programmed. OTHERS : NA - -#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_S 8 -#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_M \ - 0x00000007 // "000" - APPS_RUN : APPS is in - // RUN state (default) - Applicable - // only when APPS_PWR_STATE_PS = - // ACTIVE ; "001" - APPS_SLP : APPS - // is in SLEEP state (default) - - // Applicable only when - // APPS_PWR_STATE_PS = ACTIVE ; - // "010" - APPS_DSLP : APPS is in - // Deep-Sleep state (default) - - // Applicable only when - // APPS_PWR_STATE_PS = ACTIVE ; - // "011" - WAIT_FOR_ACTIVE : APPS is - // in transition from Deep-sleep to - // Run, where it is waiting for OPP - // to be stable ; "100" - - // WAIT_FOR_DSLP_TIMER_WAKE_REQ : - // APPS is in transition from - // Deep-sleep to Run, where the - // wakeup cause is deep-sleep - // wake-timer - -#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCU_PWR_STATE register. -// -//****************************************************************************** -#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_M \ - 0x0000001F // TBD - -#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WTOP_PM_PS register. -// -//****************************************************************************** -#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_M \ - 0x00000007 // "011" - WTOP_PM_ACTIVE (Default) - // :- WTOP_Pd is in ACTIVE mode; - // "100" - WTOP_PM_ACTIVE_TO_SLEEP - // :- WTOP_Pd is in transition from - // ACTIVE to SLEEP ; "000" - - // WTOP_PM_SLEEP : WTOP-Pd is in - // Sleep-state ; "100" - - // WTOP_PM_SLEEP_TO_ACTIVE : WTOP_Pd - // is in transition from SLEEP to - // ACTIVE ; "000" - - // WTOP_PM_WAIT_FOR_OPP : Wait for - // OPP to be stable ; - -#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for WTOP PD - // Resetz. When set to 1, - // WTOP_Resetz will be controlled by - // bit [0] - -#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for WTOP PD Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for WELP PD - // Resetz. When set to 1, - // WELP_Resetz will be controlled by - // bit [0] - -#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for WELP PD Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for WL_SDIO - // Resetz. When set to 1, - // WL_SDIO_Resetz will be controlled - // by bit [0] - -#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for WL_SDIO Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for SSDIO - // Resetz. When set to 1, - // SSDIO_Resetz will be controlled - // by bit [0] - -#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for SSDIO Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for MCSPI_N1 - // Resetz. When set to 1, - // MCSPI_N1_Resetz will be - // controlled by bit [0] - -#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for MCSPI_N1 Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for TESTCTRL-PD - // Resetz. When set to 1, - // TESTCTRL_Resetz will be - // controlled by bit [0] - -#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for TESTCTRL Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG register. -// -//****************************************************************************** -#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE_CTRL \ - 0x00000100 // Override control for MCU-PD - // Resetz. When set to 1, MCU_Resetz - // will be controlled by bit [0] - -#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE \ - 0x00000001 // Override for MCU Resetz. - // Applicable only when bit[8] is - // set to 1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG0 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_M \ - 0xFFFFFFFF // This is ROW_14 [31:0] of - // FUSEFARM. [0:0] : XTAL_IS_26MHZ - // [5:1] : TOP_CLKM_RTRIM[4:0] - // [10:6] : ANA_BGAP_MAG_TRIM[4:0] - // [16:11] : ANA_BGAP_TEMP_TRIM[5:0] - // [20:17] : ANA_BGAP_V2I_TRIM[3:0] - // [25:22] : PROCESS INDICATOR - // [26:26] : Reserved [31:27] : - // FUSEROM Version - -#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG1 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_M \ - 0x0000FFFF // This is ROW_15[15:0] of FUSEFARM - // 1. NWP Peripheral Present bits - // [15:8] NWP_GPT_N0_PP [15:15] - // NWP_GPT_N1_PP [14:14] NWP_WDOG_PP - // [13:13] NWP_UDMA_PP [12:12] - // NWP_UART_N0_PP [11:11] - // NWP_UART_N1_PP [10:10] - // NWP_SSDIO_PP [9:9] - // NWP_MCSPI_N1_PP [8:8] 2. Shared - // Peripheral Present bits [7:0] - // SHARED SPI PP [6:6] - // SHARED I2C PP [5:5] SHARED - // GPIO-A PP [4:4] SHARED GPIO-B PP - // [3:3] SHARED GPIO-C PP [2:2] - // SHARED GPIO-D PP [1:1] SHARED - // GPIO-E PP [0:0] - -#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG2 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_M \ - 0xFFFFFFFF // This is ROW_16[15:0] & - // ROW_15[31:16] of FUSEFARM. - // [31:21] - Reserved [20:16] - - // CHIP_ID [15:15] - SSBD SOP - // Control [14:14] - SSBD TAP - // Control [13:2] - APPS Peripheral - // Present bits : APPS_CAMERA_PP - // [13:13] APPS_MMCHS_PP [12:12] - // APPS_MCASP_PP [11:11] - // APPS_MCSPI_A1_PP [10:10] - // APPS_MCSPI_A2_PP [9:9] - // APPS_UDMA_PP [8:8] APPS_WDOG_PP - // [7:7] APPS_UART_A0_PP [6:6] - // APPS_UART_A1_PP [5:5] - // APPS_GPT_A0_PP [4:4] - // APPS_GPT_A1_PP [3:3] - // APPS_GPT_A2_PP [2:2] - // APPS_GPT_A3_PP [1:1] [0:0] - NWP - // Peripheral present bits - // NWP_ACSPI_PP [0:0] - -#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG3 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_M \ - 0xFFFFFFFF // This is ROW_17[15:0] & - // ROW_16[31:16] of FUSEFARM : - // [31:16] - TEST_TAP_KEY(15:0) - // [15:0] - Reserved - -#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WTOP_MEM_RET_CFG register. -// -//****************************************************************************** -#define GPRCM_WTOP_MEM_RET_CFG_WTOP_MEM_RET_CFG \ - 0x00000001 // 1 - Soft-compile memories in - // WTOP can be turned-off during - // WTOP-sleep mode ; 0 - - // Soft-compile memories in WTOP - // must be kept on during WTOP-sleep - // mode. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_COEX_CLK_SWALLOW_CFG0 register. -// -//****************************************************************************** -#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_M \ - 0x007FFFFF // TBD - -#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_COEX_CLK_SWALLOW_CFG1 register. -// -//****************************************************************************** -#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_M \ - 0x000FFFFF // TBD - -#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_COEX_CLK_SWALLOW_CFG2 register. -// -//****************************************************************************** -#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_M \ - 0x00000018 - -#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_S 3 -#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_GAIN \ - 0x00000004 - -#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_ENABLE \ - 0x00000002 - -#define GPRCM_COEX_CLK_SWALLOW_CFG2_SWALLOW_ENABLE \ - 0x00000001 // TBD - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_COEX_CLK_SWALLOW_ENABLE register. -// -//****************************************************************************** -#define GPRCM_COEX_CLK_SWALLOW_ENABLE_COEX_CLK_SWALLOW_ENABLE \ - 0x00000001 // 1 - Enable switching of sysclk - // to Coex-clk path ; 0 - Disable - // switching of sysclk to Coex-clk - // path. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_DCDC_CLK_GEN_CONFIG register. -// -//****************************************************************************** -#define GPRCM_DCDC_CLK_GEN_CONFIG_DCDC_CLK_ENABLE \ - 0x00000001 // 1 - Enable the clock for DCDC - // (PWM-mode) ; 0 - Disable the - // clock for DCDC (PWM-mode) - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG4 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_M \ - 0x0000FFFF // This corresponds to - // ROW_17[31:16] of the FUSEFARM : - // [15:0] : TEST_TAP_KEY(31:16) - -#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG5 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_M \ - 0xFFFFFFFF // Corresponds to ROW_18 of - // FUSEFARM. [29:0] - - // MEMSS_COLUMN_SEL_LSW ; [30:30] - - // WLAN GEM DISABLE ; [31:31] - - // SERIAL WIRE JTAG SELECT - -#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG6 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_M \ - 0x0000FFFF // Corresponds to ROW_19[15:0] of - // FUSEFARM. [15:0] : - // MEMSS_COLUMN_SEL_MSW - -#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG7 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_M \ - 0xFFFFFFFF // Corresponds to ROW_20[15:0] & - // ROW_19[31:16] of FUSEFARM. - // FLASH_REGION0 - -#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG8 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_M \ - 0xFFFFFFFF // Corresponds to ROW_21[15:0] & - // ROW_20[31:16] of FUSEFARM. - // FLASH_REGION1 - -#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG9 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_M \ - 0xFFFFFFFF // Corresponds to ROW_22[15:0] & - // ROW_21[31:16] of FUSEFARM. - // FLASH_REGION2 - -#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG10 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_M \ - 0xFFFFFFFF // Corresponds to ROW_23[15:0] & - // ROW_22[31:16] of FUSEFARM. - // FLASH_REGION3 - -#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_EFUSE_READ_REG11 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_M \ - 0xFFFFFFFF // Corresponds to ROW_24[15:0] & - // ROW_23[31:16] of FUSEFARM. - // FLASH_DESCRIPTOR - -#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG0 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_M \ - 0xFFFFFFFF // Corresponds to bits [191:160] of - // the FUSEFARM. This is ROW_5 of - // FUSEFARM [191:160] : [31:0] : - // DIE_ID0 [31:0] : DEVX [11:0] DEVY - // [23:12] DEVWAF [29:24] DEV_SPARE - // [31:30] - -#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG1 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_M \ - 0xFFFFFFFF // Corresponds to bits [223:192] of - // the FUSEFARM. This is ROW_6 of - // FUSEFARM :- DEVLOT [23:0] DEVFAB - // [28:24] DEVFABBE [31:29] - -#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG2 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_M \ - 0xFFFFFFFF // Corresponds to bits [255:224] of - // the FUSEFARM. This is ROW_7 of - // FUSEFARM:- DEVDESREV[4:0] - // Memrepair[5:5] MakeDefined[16:6] - // CHECKSUM[30:17] Reserved : - // [31:31] - -#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG3 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_M \ - 0xFFFFFFFF // Corresponds to bits [287:256] of - // the FUSEFARM. This is ROW_8 of - // FUSEFARM :- DIEID0 - DEVREG - // [31:0] - -#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_GPRCM_DIEID_READ_REG4 register. -// -//****************************************************************************** -#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_M \ - 0xFFFFFFFF // Corresponds to bits [319:288] of - // the FUSEFARM. This is ROW_9 of - // FUSEFARM :- [7:0] - VBATMON ; - // [13:8] - BUFF_OFFSET ; [15:15] - - // DFT_GXG ; [14:14] - DFT_GLX ; - // [19:16] - PHY ROM Version ; - // [23:20] - MAC ROM Version ; - // [27:24] - NWP ROM Version ; - // [31:28] - APPS ROM Version - -#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_APPS_SS_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_APPS_SS_OVERRIDES_reserved_M \ - 0xFFFFFC00 - -#define GPRCM_APPS_SS_OVERRIDES_reserved_S 10 -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override \ - 0x00000200 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override_ctrl \ - 0x00000100 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override \ - 0x00000080 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override_ctrl \ - 0x00000040 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override \ - 0x00000020 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override \ - 0x00000010 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override \ - 0x00000008 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override_ctrl \ - 0x00000004 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override_ctrl \ - 0x00000002 - -#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_NWP_SS_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_NWP_SS_OVERRIDES_reserved_M \ - 0xFFFFFC00 - -#define GPRCM_NWP_SS_OVERRIDES_reserved_S 10 -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override \ - 0x00000200 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override_ctrl \ - 0x00000100 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override \ - 0x00000080 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override_ctrl \ - 0x00000040 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override \ - 0x00000020 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override \ - 0x00000010 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override \ - 0x00000008 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override_ctrl \ - 0x00000004 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override_ctrl \ - 0x00000002 - -#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_SHARED_SS_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_SHARED_SS_OVERRIDES_reserved_M \ - 0xFFFFFF00 - -#define GPRCM_SHARED_SS_OVERRIDES_reserved_S 8 -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override_ctrl \ - 0x00000080 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override \ - 0x00000040 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override_ctrl \ - 0x00000020 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override \ - 0x00000010 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override \ - 0x00000008 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override \ - 0x00000004 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override_ctrl \ - 0x00000002 - -#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_IDMEM_CORE_RST_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_M \ - 0xFFFFFF00 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_S 8 -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override \ - 0x00000080 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override \ - 0x00000040 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW1 \ - 0x00000020 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override \ - 0x00000010 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override_ctrl \ - 0x00000008 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override_ctrl \ - 0x00000004 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW0 \ - 0x00000002 - -#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_TOP_DIE_FSM_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_M \ - 0xFFFFF000 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_S 12 -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override_ctrl \ - 0x00000800 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override \ - 0x00000400 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override \ - 0x00000200 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override \ - 0x00000100 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override \ - 0x00000080 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override \ - 0x00000040 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override \ - 0x00000020 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override_ctrl \ - 0x00000010 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override_ctrl \ - 0x00000008 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override_ctrl \ - 0x00000004 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override_ctrl \ - 0x00000002 - -#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCU_PSCON_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_MCU_PSCON_OVERRIDES_reserved_M \ - 0xFFF00000 - -#define GPRCM_MCU_PSCON_OVERRIDES_reserved_S 20 -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_sleep_override_ctrl \ - 0x00080000 - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override_ctrl \ - 0x00040000 - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_ctrl \ - 0x00020000 - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_ctrl \ - 0x00010000 - -#define GPRCM_MCU_PSCON_OVERRIDES_NU1_M \ - 0x0000FC00 - -#define GPRCM_MCU_PSCON_OVERRIDES_NU1_S 10 -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_sleep_override \ - 0x00000200 - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override \ - 0x00000100 - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_M \ - 0x000000F0 - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_S 4 -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_M \ - 0x0000000F - -#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WTOP_PSCON_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_M \ - 0xFFC00000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_S 22 -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override_ctrl \ - 0x00200000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override_ctrl \ - 0x00100000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_ctrl \ - 0x00080000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_ctrl \ - 0x00040000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override \ - 0x00020000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override \ - 0x00010000 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_M \ - 0x0000FF00 - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_S 8 -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_M \ - 0x000000FF - -#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WELP_PSCON_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_WELP_PSCON_OVERRIDES_reserved_M \ - 0xFFFFFFFC - -#define GPRCM_WELP_PSCON_OVERRIDES_reserved_S 2 -#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override_ctrl \ - 0x00000002 - -#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_WL_SDIO_PSCON_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_M \ - 0xFFFFFFFC - -#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_S 2 -#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override_ctrl \ - 0x00000002 - -#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_MCSPI_PSCON_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_M \ - 0xFFFFFF00 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_S 8 -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override_ctrl \ - 0x00000080 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override_ctrl \ - 0x00000040 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override \ - 0x00000020 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override \ - 0x00000010 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override_ctrl \ - 0x00000008 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override \ - 0x00000004 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override_ctrl \ - 0x00000002 - -#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// GPRCM_O_SSDIO_PSCON_OVERRIDES register. -// -//****************************************************************************** -#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_M \ - 0xFFFFFFFC - -#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_S 2 -#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override_ctrl \ - 0x00000002 - -#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override \ - 0x00000001 - - - - -#endif // __HW_GPRCM_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_hib1p2.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_hib1p2.h deleted file mode 100644 index 06694512f46..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_hib1p2.h +++ /dev/null @@ -1,1748 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_HIB1P2_H__ -#define __HW_HIB1P2_H__ - -//***************************************************************************** -// -// The following are defines for the HIB1P2 register offsets. -// -//***************************************************************************** -#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 \ - 0x00000000 - -#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 \ - 0x00000004 - -#define HIB1P2_O_DIG_DCDC_PARAMETERS0 \ - 0x00000008 - -#define HIB1P2_O_DIG_DCDC_PARAMETERS1 \ - 0x0000000C - -#define HIB1P2_O_DIG_DCDC_PARAMETERS2 \ - 0x00000010 - -#define HIB1P2_O_DIG_DCDC_PARAMETERS3 \ - 0x00000014 - -#define HIB1P2_O_DIG_DCDC_PARAMETERS4 \ - 0x00000018 - -#define HIB1P2_O_DIG_DCDC_PARAMETERS5 \ - 0x0000001C - -#define HIB1P2_O_DIG_DCDC_PARAMETERS6 \ - 0x00000020 - -#define HIB1P2_O_ANA_DCDC_PARAMETERS0 \ - 0x00000024 - -#define HIB1P2_O_ANA_DCDC_PARAMETERS1 \ - 0x00000028 - -#define HIB1P2_O_ANA_DCDC_PARAMETERS16 \ - 0x00000064 - -#define HIB1P2_O_ANA_DCDC_PARAMETERS17 \ - 0x00000068 - -#define HIB1P2_O_ANA_DCDC_PARAMETERS18 \ - 0x0000006C - -#define HIB1P2_O_ANA_DCDC_PARAMETERS19 \ - 0x00000070 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS0 \ - 0x00000074 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS1 \ - 0x00000078 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS2 \ - 0x0000007C - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS3 \ - 0x00000080 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS4 \ - 0x00000084 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS5 \ - 0x00000088 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS6 \ - 0x0000008C - -#define HIB1P2_O_PMBIST_PARAMETERS0 \ - 0x00000094 - -#define HIB1P2_O_PMBIST_PARAMETERS1 \ - 0x00000098 - -#define HIB1P2_O_PMBIST_PARAMETERS2 \ - 0x0000009C - -#define HIB1P2_O_PMBIST_PARAMETERS3 \ - 0x000000A0 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS8 \ - 0x000000A4 - -#define HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE \ - 0x000000A8 - -#define HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE \ - 0x000000AC - -#define HIB1P2_O_DIG_DCDC_VTRIM_CFG \ - 0x000000B0 - -#define HIB1P2_O_DIG_DCDC_FSM_PARAMETERS \ - 0x000000B4 - -#define HIB1P2_O_ANA_DCDC_FSM_PARAMETERS \ - 0x000000B8 - -#define HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS \ - 0x000000BC - -#define HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG \ - 0x000000C0 - -#define HIB1P2_O_CM_OSC_16M_CONFIG \ - 0x000000C4 - -#define HIB1P2_O_SOP_SENSE_VALUE \ - 0x000000C8 - -#define HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 \ - 0x000000CC - -#define HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 \ - 0x000000D0 - -#define HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES \ - 0x000000D4 - -#define HIB1P2_O_HIB1P2_EFUSE_READ_REG0 \ - 0x000000D8 - -#define HIB1P2_O_HIB1P2_EFUSE_READ_REG1 \ - 0x000000DC - -#define HIB1P2_O_HIB1P2_POR_TEST_CTRL \ - 0x000000E0 - -#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 \ - 0x000000E4 - -#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 \ - 0x000000E8 - -#define HIB1P2_O_HIB_TIMER_SYNC_CFG2 \ - 0x000000EC - -#define HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL \ - 0x000000F0 - -#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW \ - 0x000000F4 - -#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW \ - 0x000000F8 - -#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW \ - 0x000000FC - -#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW \ - 0x00000100 - -#define HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR \ - 0x00000104 - -#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW \ - 0x00000108 - -#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW \ - 0x0000010C - -#define HIB1P2_O_CM_SPARE 0x00000110 -#define HIB1P2_O_PORPOL_SPARE 0x00000114 -#define HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG \ - 0x00000118 - -#define HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG \ - 0x0000011C - -#define HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG \ - 0x00000120 - -#define HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG \ - 0x00000124 - -#define HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE \ - 0x00000128 - -#define HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE \ - 0x0000012C - -#define HIB1P2_O_MEM_HIB_FSM_DEBUG \ - 0x00000130 - -#define HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL \ - 0x00000134 - -#define HIB1P2_O_MEM_SLDO_WEAK_PROCESS \ - 0x00000138 - -#define HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS \ - 0x0000013C - -#define HIB1P2_O_MEM_CM_TEST_MODE \ - 0x00000140 - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 register. -// -//****************************************************************************** -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_M \ - 0xC0000000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_S 30 -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_M \ - 0x30000000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_S 28 -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_prot_lowv \ - 0x08000000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_override \ - 0x04000000 // FSM Override value for SLDO_EN : - // Applicable only when bit [4] of - // this register is set to 1. - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_low_pwr_lowv \ - 0x02000000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_int_cap_sel_lowv \ - 0x01000000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_M \ - 0x00FC0000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_S 18 -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_M \ - 0x0003FF00 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_S 8 -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_override \ - 0x00000080 // FSM Override value for - // SKA_LDO_EN : Applicable only when - // bit [3] of this register is set - // to 1. - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_cap_ref_lowv \ - 0x00000040 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_resdiv_ref_lowv \ - 0x00000020 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_fsm_override_ctrl \ - 0x00000010 // When 1, bit[26] of this register - // will be used as SLDO_EN - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_fsm_override_ctrl \ - 0x00000008 // When 1, bit[26] of this register - // will be used as SKA_LDO_EN - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_M \ - 0x00000007 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 register. -// -//****************************************************************************** -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_M \ - 0xFFC00000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_S 22 -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_M \ - 0x003F0000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_S 16 -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_sldo_en_tload_lowv \ - 0x00008000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_tload_lowv \ - 0x00004000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_cap_sw_en_lowv \ - 0x00002000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_hib_lowv \ - 0x00001000 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_vref_buf_lowv \ - 0x00000800 - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_M \ - 0x000007FF - -#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS0 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_lowv_override \ - 0x80000000 // Override value for DCDC_DIG_EN : - // Applicable only when bit [31] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1. Else from FSM - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_delayed_en_lowv \ - 0x40000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p8v_lowv_override \ - 0x20000000 // Override value for - // DCDC_DIG_EN_SUBREG_1P8V : - // Applicable only when bit [30] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1. Else from FSM - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p2v_lowv_override \ - 0x10000000 // Override value for - // DCDC_DIG_EN_SUBREG_1P2V : - // Applicable only when bit [29] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1. Else from FSM - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_slp_mode_lowv_override \ - 0x08000000 // Override value for - // DCDC_DIG_SLP_EN : Applicable only - // when bit [28] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1. Else from FSM - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_ldo_mode_lowv \ - 0x04000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_nfet_rds_mode_lowv \ - 0x02000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_pfet_rds_mode_lowv \ - 0x01000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_ext_smps_override_mode_lowv \ - 0x00800000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_clk_in_lowv_enable \ - 0x00400000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_M \ - 0x003F0000 // Override value for - // DCDC_DIG_VTRIM : Applicable only - // when bit [27] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1. - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_S 16 -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_M \ - 0x0000C000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_S 14 -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_M \ - 0x00003000 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_S 12 -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_cl_non_ov_lowv \ - 0x00000800 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_M \ - 0x00000780 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_S 7 -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_M \ - 0x00000078 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_S 3 -#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_M \ - 0x00000007 - -#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS1 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_lowv_fsm_override_ctrl \ - 0x80000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p8v_fsm_override_ctrl \ - 0x40000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p2v_fsm_override_ctrl \ - 0x20000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_slp_mode_lowv_fsm_override_ctrl \ - 0x10000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_vtrim_fsm_override_ctrl \ - 0x08000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_cot_mode_en_lowv_fsm_override_ctrl \ - 0x04000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_ilim_trim_lowv_efc_override_ctrl \ - 0x02000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_M \ - 0x01FFFFFF - -#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS2 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_M \ - 0xF0000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_S 28 -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_M \ - 0x0F000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_S 24 -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_M \ - 0x00C00000 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_S 22 -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_M \ - 0x00300000 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_S 20 -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_M \ - 0x000F0000 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_S 16 -#define HIB1P2_DIG_DCDC_PARAMETERS2_NA5 \ - 0x00008000 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_M \ - 0x00007800 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_S 11 -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_en_shootthru_ctrl_lowv \ - 0x00000400 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_M \ - 0x000003FC - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_S 2 -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_swcap_res_hf_clk_lowv \ - 0x00000002 - -#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_cot_mode_en_lowv_override \ - 0x00000001 // Override value for - // DCDC_DIG_COT_EN : Applicable only - // when bit[26] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS3 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS3_NA6 \ - 0x80000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_M \ - 0x7F800000 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_S 23 -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_lowv \ - 0x00400000 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_hib_lowv \ - 0x00200000 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_M \ - 0x001FE000 // Override value for - // DCDC_DIG_ILIM_TRIM : Applicable - // only when bit [25] of - // DIG_DCDC_PARAMETERS1 [0x000C] is - // set to 1 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_S 13 -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_M \ - 0x00001800 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_S 11 -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_lowv \ - 0x00000400 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_hib_lowv \ - 0x00000200 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_M \ - 0x000001F0 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_S 4 -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_M \ - 0x0000000C - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_S 2 -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_uv_prot_lowv \ - 0x00000002 - -#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ov_prot_lowv \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS4 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_uv_prot_out_lowv \ - 0x80000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_ov_prot_out_lowv \ - 0x40000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS4_mem_dcdc_dig_en_tmux_lowv \ - 0x20000000 - -#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_M \ - 0x1FFFFFFF - -#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS5 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_PARAMETERS6 register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS0 register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_lowv_override \ - 0x80000000 // Override for ANA DCDC EN - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_delayed_en_lowv \ - 0x40000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p8v_lowv \ - 0x20000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p2v_lowv \ - 0x10000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pwm_mode_lowv_override \ - 0x08000000 // Override for ANA DCDC PWM - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_slp_mode_lowv_override \ - 0x04000000 // Override for ANA DCDC SLP - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_ldo_mode_lowv \ - 0x02000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pfet_rds_mode_lowv \ - 0x01000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_nfet_rds_mode_lowv \ - 0x00800000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_ext_smps_override_mode_lowv \ - 0x00400000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_clk_in_lowv_enable \ - 0x00200000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_M \ - 0x001E0000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_S 17 -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_M \ - 0x00018000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_S 15 -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_M \ - 0x00006000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_S 13 -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_cl_non_ov_lowv \ - 0x00001000 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_M \ - 0x00000F00 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_S 8 -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_M \ - 0x000000F0 - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_S 4 -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_M \ - 0x0000000F - -#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS1 register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_M \ - 0xF0000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_S 28 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_M \ - 0x0C000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_S 26 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_M \ - 0x03000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_S 24 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_M \ - 0x00F00000 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_S 20 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_M \ - 0x000F0000 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_S 16 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_rtrim_lowv \ - 0x00008000 // (Earlier SHOOTTHRU CTRL) - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_apwm_en_lowv \ - 0x00004000 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_M \ - 0x00003E00 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_S 9 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_anti_glitch_lowv \ - 0x00000100 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_hi_clamp_lowv \ - 0x00000080 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_M \ - 0x00000060 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_S 5 -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_lo_clamp_lowv \ - 0x00000010 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_M \ - 0x0000000C - -#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_S 2 -#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_M \ - 0x00000003 - -#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS16 register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_lowv \ - 0x00200000 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_hib_lowv \ - 0x00100000 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_M \ - 0x000FF000 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_S 12 -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_M \ - 0x00000C00 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_S 10 -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_lowv \ - 0x00000200 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_hib_lowv \ - 0x00000100 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_M \ - 0x000000F8 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_S 3 -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_M \ - 0x00000006 - -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_S 1 -#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ov_prot_lowv \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS17 register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS17_dcdc_ana_ov_prot_out_lowv \ - 0x80000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS17_mem_dcdc_ana_en_tmux_lowv \ - 0x40000000 - -#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_M \ - 0x3FFFFFFF - -#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS18 register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS19 register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS0 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_lowv \ - 0x80000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_delayed_en_lowv \ - 0x40000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_clk_in_lowv_enable \ - 0x20000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_M \ - 0x18000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_S 27 -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_mode_lowv \ - 0x04000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_boost_mode_lowv \ - 0x02000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_boost_mode_lowv \ - 0x01000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_bb_alt_cycles_lowv \ - 0x00800000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_cl_non_ov_lowv \ - 0x00400000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_M \ - 0x003C0000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_S 18 -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_drv_lowv \ - 0x00020000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pwm_mode_lowv \ - 0x00010000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pfm_comp_lowv \ - 0x00008000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_slp_mode_lowv \ - 0x00004000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n1fet_rds_mode_lowv \ - 0x00002000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n2fet_rds_mode_lowv \ - 0x00001000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p1fet_rds_mode_lowv \ - 0x00000800 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p2fet_rds_mode_lowv \ - 0x00000400 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_ext_smps_mode_override_lowv \ - 0x00000200 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_M \ - 0x000001E0 - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_S 5 -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_M \ - 0x0000001E - -#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_S 1 -#define HIB1P2_FLASH_DCDC_PARAMETERS0_NA18 \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS1 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_M \ - 0xF0000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_S 28 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_M \ - 0x0F000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_S 24 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_M \ - 0x00F00000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_S 20 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_M \ - 0x000F0000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_S 16 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_M \ - 0x0000F000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_S 12 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_M \ - 0x00000F00 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_S 8 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_M \ - 0x000000C0 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_S 6 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_M \ - 0x00000030 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_S 4 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_M \ - 0x0000000C - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_S 2 -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_M \ - 0x00000003 - -#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS2 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_M \ - 0xC0000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_S 30 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_M \ - 0x30000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_S 28 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_M \ - 0x0C000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_S 26 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_M \ - 0x03000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_S 24 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_shoot_thru_ctrl_lowv \ - 0x00800000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_lowv \ - 0x00400000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_hib_lowv \ - 0x00200000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_M \ - 0x001F0000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_S 16 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_M \ - 0x0000F000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_S 12 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_lowv \ - 0x00000800 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_hib_lowv \ - 0x00000400 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_M \ - 0x000003FC - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_S 2 -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_M \ - 0x00000003 - -#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS3 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_anti_glitch_lowv \ - 0x80000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_hi_clamp_lowv \ - 0x40000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_lo_clamp_lowv \ - 0x20000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_M \ - 0x1F000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_S 24 -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_M \ - 0x00E00000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_S 21 -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_M \ - 0x001C0000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_S 18 -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_M \ - 0x0003C000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_S 14 -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_M \ - 0x00003C00 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_S 10 -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_M \ - 0x00000300 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_S 8 -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_ov_prot_lowv \ - 0x00000080 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_uv_prot_lowv \ - 0x00000040 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_tmux_lowv \ - 0x00000020 - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_M \ - 0x0000001F - -#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS4 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS5 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS6 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_ov_prot_out_lowv \ - 0x80000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_uv_prot_out_lowv \ - 0x40000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_M \ - 0x3FFFFFFF - -#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_PMBIST_PARAMETERS0 register. -// -//****************************************************************************** -#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_en_lowv \ - 0x80000000 - -#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_M \ - 0x7FFFF800 - -#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_S 11 -#define HIB1P2_PMBIST_PARAMETERS0_NA21_M \ - 0x000007FF - -#define HIB1P2_PMBIST_PARAMETERS0_NA21_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_PMBIST_PARAMETERS1 register. -// -//****************************************************************************** -#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_M \ - 0xFFFF0000 - -#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_S 16 -#define HIB1P2_PMBIST_PARAMETERS1_mem_pmtest_en_lowv \ - 0x00008000 - -#define HIB1P2_PMBIST_PARAMETERS1_NA22_M \ - 0x00007FFF - -#define HIB1P2_PMBIST_PARAMETERS1_NA22_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_PMBIST_PARAMETERS2 register. -// -//****************************************************************************** -#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_M \ - 0xFFFFFFFF - -#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_PMBIST_PARAMETERS3 register. -// -//****************************************************************************** -#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_M \ - 0xFFFF0000 - -#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_S 16 -#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_M \ - 0x0000E000 - -#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_S 13 -#define HIB1P2_PMBIST_PARAMETERS3_mem_rnwell_calib_en_lowv \ - 0x00001000 - -#define HIB1P2_PMBIST_PARAMETERS3_NA23_M \ - 0x00000FFF - -#define HIB1P2_PMBIST_PARAMETERS3_NA23_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS8 register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_en_flash_sup_comp_lowv \ - 0x80000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_M \ - 0x7C000000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_S 26 -#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_M \ - 0x03E00000 - -#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_S 21 -#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_M \ - 0x001FFFFF - -#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_M \ - 0xFFFFFFC0 - -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_S 6 -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p2v_lowv_override_ctrl \ - 0x00000020 - -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p8v_lowv_override_ctrl \ - 0x00000010 - -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_ilim_trim_lowv_efc_override_ctrl \ - 0x00000008 - -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_slp_mode_lowv_fsm_override_ctrl \ - 0x00000004 - -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_pwm_mode_lowv_fsm_override_ctrl \ - 0x00000002 - -#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_lowv_fsm_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE register. -// -//****************************************************************************** -#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_M \ - 0xFFFFFFFC - -#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_S 2 -#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_en_lowv_override_ctrl \ - 0x00000002 - -#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_ilim_trim_lowv_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_VTRIM_CFG register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_M \ - 0xFF000000 - -#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_S 24 -#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_M \ - 0x00FC0000 - -#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_S 18 -#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_M \ - 0x0003F000 - -#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_S 12 -#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_M \ - 0x00000FC0 - -#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_S 6 -#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_M \ - 0x0000003F - -#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_DIG_DCDC_FSM_PARAMETERS register. -// -//****************************************************************************** -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_M \ - 0xFFFF8000 - -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_S 15 -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_M \ - 0x00007000 - -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_S 12 -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_M \ - 0x00000E00 - -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_S 9 -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_M \ - 0x000001C0 - -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_S 6 -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_M \ - 0x00000038 - -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_S 3 -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_M \ - 0x00000007 - -#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_ANA_DCDC_FSM_PARAMETERS register. -// -//****************************************************************************** -#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_M \ - 0xFFFFFFF8 - -#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_S 3 -#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_M \ - 0x00000007 - -#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS register. -// -//****************************************************************************** -#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_M \ - 0xFFFFFFC0 - -#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_S 6 -#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_M \ - 0x00000038 - -#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_S 3 -#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_M \ - 0x00000007 - -#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG register. -// -//****************************************************************************** -#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_M \ - 0xFFFFFFF8 - -#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_S 3 -#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_M \ - 0x00000007 - -#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_CM_OSC_16M_CONFIG register. -// -//****************************************************************************** -#define HIB1P2_CM_OSC_16M_CONFIG_reserved_M \ - 0xFFFC0000 - -#define HIB1P2_CM_OSC_16M_CONFIG_reserved_S 18 -#define HIB1P2_CM_OSC_16M_CONFIG_cm_clk_good_16m \ - 0x00020000 - -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_en_osc_16m \ - 0x00010000 - -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_M \ - 0x0000FC00 - -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_S 10 -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_M \ - 0x000003F0 - -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_S 4 -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_en_sli_16m \ - 0x00000008 - -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_M \ - 0x00000007 - -#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_SOP_SENSE_VALUE register. -// -//****************************************************************************** -#define HIB1P2_SOP_SENSE_VALUE_reserved_M \ - 0xFFFFFF00 - -#define HIB1P2_SOP_SENSE_VALUE_reserved_S 8 -#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_M \ - 0x000000FF - -#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 register. -// -//****************************************************************************** -#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_M \ - 0xFFFFFFFF - -#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 register. -// -//****************************************************************************** -#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_M \ - 0x0000FFFF - -#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES register. -// -//****************************************************************************** -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_M \ - 0xFF800000 - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_S 23 -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_ctrl \ - 0x00400000 - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_M \ - 0x003FC000 - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_S 14 -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_ctrl \ - 0x00002000 - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_M \ - 0x00001FC0 - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_S 6 -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_ctrl \ - 0x00000020 - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_M \ - 0x0000001F - -#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB1P2_EFUSE_READ_REG0 register. -// -//****************************************************************************** -#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_M \ - 0xFFFFFFFF // Corresponds to ROW_12 of - // FUSEFARM. [7:0] : - // DCDC_DIG_ILIM_TRIM_LOWV(7:0) - // [15:8] : - // DCDC_ANA_ILIM_TRIM_LOWV(7:0) - // [23:16] : - // DCDC_FLASH_ILIM_TRIM_LOWV(7:0) - // [24:24] : DTHE SHA DISABLE - // [25:25] : DTHE DES DISABLE - // [26:26] : DTHE AES DISABLE - // [31:27] : HD_BG_RTRIM (4:0) - -#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB1P2_EFUSE_READ_REG1 register. -// -//****************************************************************************** -#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_M \ - 0xFFFFFFFF // Corresponds to ROW_13 of the - // FUSEFARM. [7:0] : HD_BG_MAG_TRIM - // (7:0) [14:8] : HD_BG_TEMP_TRIM - // (6:0) [15:15] : GREYOUT ENABLE - // DUTY CYCLING [31:16] : - // Reserved/Checksum - -#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB1P2_POR_TEST_CTRL register. -// -//****************************************************************************** -#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_M \ - 0xFFFFFF00 - -#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_S 8 -#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_M \ - 0x000000FF - -#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_M \ - 0xFFFF0000 - -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_S 16 -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_M \ - 0x0000FF00 - -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_S 8 -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_M \ - 0x000000FE - -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_S 1 -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_start \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_M \ - 0xFFF00000 - -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_S 20 -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_M \ - 0x000FFFFF - -#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_CFG2 register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_M \ - 0xFFFFFE00 - -#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_S 9 -#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_hib_unload \ - 0x00000100 - -#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_M \ - 0x000000FC - -#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_S 2 -#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_tsf_adj \ - 0x00000002 - -#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_update_tsf \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_M \ - 0xFFFFFFFF - -#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_M \ - 0xFFFFFFFF - -#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_M \ - 0xFFFF0000 - -#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_S 16 -#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_M \ - 0x0000FFFF - -#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_M \ - 0xFFFFFFFF - -#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_M \ - 0xFFFF0000 - -#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_S 16 -#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_M \ - 0x0000FFFF - -#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_M \ - 0xFFFFF000 - -#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_S 12 -#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_M \ - 0x00000FFF - -#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_M \ - 0xFFFFFFFF - -#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW register. -// -//****************************************************************************** -#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_M \ - 0xFFFFFFFF - -#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the HIB1P2_O_CM_SPARE register. -// -//****************************************************************************** -#define HIB1P2_CM_SPARE_CM_SPARE_OUT_M \ - 0xFF000000 - -#define HIB1P2_CM_SPARE_CM_SPARE_OUT_S 24 -#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_M \ - 0x00FF0000 - -#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_S 16 -#define HIB1P2_CM_SPARE_MEM_CM_SPARE_M \ - 0x0000FFFF - -#define HIB1P2_CM_SPARE_MEM_CM_SPARE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_PORPOL_SPARE register. -// -//****************************************************************************** -#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_M \ - 0xFFFFFFFF - -#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG register. -// -//****************************************************************************** -#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_ENABLE \ - 0x00000100 - -#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_M \ - 0x000000F0 - -#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_S 4 -#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_M \ - 0x0000000F - -#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG register. -// -//****************************************************************************** -#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_ENABLE \ - 0x00000100 - -#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_M \ - 0x000000F0 - -#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 -#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_M \ - 0x0000000F - -#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG register. -// -//****************************************************************************** -#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_ENABLE \ - 0x00000100 - -#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_M \ - 0x000000F0 - -#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_S 4 -#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_M \ - 0x0000000F - -#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG register. -// -//****************************************************************************** -#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_ENABLE \ - 0x00000100 - -#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_M \ - 0x000000F0 - -#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 -#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_M \ - 0x0000000F - -#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE register. -// -//****************************************************************************** -#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE_CTRL \ - 0x00000002 - -#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE register. -// -//****************************************************************************** -#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE_CTRL \ - 0x00000002 - -#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_HIB_FSM_DEBUG register. -// -//****************************************************************************** -#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_M \ - 0x00000700 - -#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_S 8 -#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_M \ - 0x000000F0 - -#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_S 4 -#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_M \ - 0x0000000F - -#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL register. -// -//****************************************************************************** -#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_M \ - 0x000FFFFF - -#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_SLDO_WEAK_PROCESS register. -// -//****************************************************************************** -#define HIB1P2_MEM_SLDO_WEAK_PROCESS_MEM_SLDO_WEAK_PROCESS \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS register. -// -//****************************************************************************** -#define HIB1P2_MEM_PA_DCDC_OV_UV_STATUS_dcdc_pa_ov_prot_out_lowv \ - 0x00000002 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB1P2_O_MEM_CM_TEST_MODE register. -// -//****************************************************************************** -#define HIB1P2_MEM_CM_TEST_MODE_mem_cm_test_mode \ - 0x00000001 - - - - -#endif // __HW_HIB1P2_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_hib3p3.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_hib3p3.h deleted file mode 100644 index 93c385e761e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_hib3p3.h +++ /dev/null @@ -1,1136 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_HIB3P3_H__ -#define __HW_HIB3P3_H__ - -//***************************************************************************** -// -// The following are defines for the HIB3P3 register offsets. -// -//***************************************************************************** -#define HIB3P3_O_MEM_HIB_REQ 0x00000000 -#define HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE \ - 0x00000004 - -#define HIB3P3_O_MEM_HIB_RTC_TIMER_RESET \ - 0x00000008 - -#define HIB3P3_O_MEM_HIB_RTC_TIMER_READ \ - 0x0000000C - -#define HIB3P3_O_MEM_HIB_RTC_TIMER_LSW \ - 0x00000010 - -#define HIB3P3_O_MEM_HIB_RTC_TIMER_MSW \ - 0x00000014 - -#define HIB3P3_O_MEM_HIB_RTC_WAKE_EN \ - 0x00000018 - -#define HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF \ - 0x0000001C - -#define HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF \ - 0x00000020 - -#define HIB3P3_O_MEM_INT_OSC_CONF \ - 0x0000002C - -#define HIB3P3_O_MEM_XTAL_OSC_CONF \ - 0x00000034 - -#define HIB3P3_O_MEM_BGAP_PARAMETERS0 \ - 0x00000038 - -#define HIB3P3_O_MEM_BGAP_PARAMETERS1 \ - 0x0000003C - -#define HIB3P3_O_MEM_HIB_DETECTION_STATUS \ - 0x00000040 - -#define HIB3P3_O_MEM_HIB_MISC_CONTROLS \ - 0x00000044 - -#define HIB3P3_O_MEM_HIB_CONFIG 0x00000050 -#define HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE \ - 0x00000054 - -#define HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF \ - 0x00000058 - -#define HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF \ - 0x0000005C - -#define HIB3P3_O_MEM_HIB_UART_CONF \ - 0x00000400 - -#define HIB3P3_O_MEM_GPIO_WAKE_EN \ - 0x00000404 - -#define HIB3P3_O_MEM_GPIO_WAKE_CONF \ - 0x00000408 - -#define HIB3P3_O_MEM_PAD_OEN_RET33_CONF \ - 0x0000040C - -#define HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF \ - 0x00000410 - -#define HIB3P3_O_MEM_JTAG_CONF 0x00000414 -#define HIB3P3_O_MEM_HIB_REG0 0x00000418 -#define HIB3P3_O_MEM_HIB_REG1 0x0000041C -#define HIB3P3_O_MEM_HIB_REG2 0x00000420 -#define HIB3P3_O_MEM_HIB_REG3 0x00000424 -#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 \ - 0x0000045C - -#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 \ - 0x00000460 - -#define HIB3P3_O_MEM_HIB_MISC_CONFIG \ - 0x00000464 - -#define HIB3P3_O_MEM_HIB_WAKE_STATUS \ - 0x00000468 - -#define HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL \ - 0x0000046C - -#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 \ - 0x00000470 - -#define HIB3P3_O_HIBANA_SPARE_LOWV \ - 0x00000474 - -#define HIB3P3_O_HIB_TMUX_CTRL 0x00000478 -#define HIB3P3_O_HIB_1P2_1P8_LDO_TRIM \ - 0x0000047C - -#define HIB3P3_O_HIB_COMP_TRIM 0x00000480 -#define HIB3P3_O_HIB_EN_TS 0x00000484 -#define HIB3P3_O_HIB_1P8V_DET_EN \ - 0x00000488 - -#define HIB3P3_O_HIB_VBAT_MON_EN \ - 0x0000048C - -#define HIB3P3_O_HIB_NHIB_ENABLE \ - 0x00000490 - -#define HIB3P3_O_HIB_UART_RTS_SW_ENABLE \ - 0x00000494 - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_REQ register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_REQ_reserved_M \ - 0xFFFFFE00 - -#define HIB3P3_MEM_HIB_REQ_reserved_S 9 -#define HIB3P3_MEM_HIB_REQ_NU1_M \ - 0x000001FC - -#define HIB3P3_MEM_HIB_REQ_NU1_S 2 -#define HIB3P3_MEM_HIB_REQ_mem_hib_clk_disable \ - 0x00000002 // 1 - Specifies that the Hiberante - // mode is without clocks ; 0 - - // Specified that the Hibernate mode - // is with clocks This register will - // be reset during Hibernate - // -WO-Clks mode (but not during - // Hibernate-W-Clks mode). - -#define HIB3P3_MEM_HIB_REQ_mem_hib_req \ - 0x00000001 // 1 - Request for hibernate mode - // (This is an auto-clear bit) ; 0 - - // Donot request for hibernate mode - // This register will be reset - // during Hibernate -WO-Clks mode - // (but not during Hibernate-W-Clks - // mode). - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_S 1 -#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_mem_hib_rtc_timer_enable \ - 0x00000001 // 1 - Enable the RTC timer to - // start running ; 0 - Keep the RTC - // timer disabled This register will - // be reset during Hibernate - // -WO-Clks mode (but not during - // Hibernate-W-Clks mode). - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_TIMER_RESET register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_S 1 -#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_mem_hib_rtc_timer_reset \ - 0x00000001 // 1 - Reset the RTC timer ; 0 - - // Donot reset the RTC timer. This - // is an auto-clear bit. This - // register will be reset during - // Hibernate -WO-Clks mode (but not - // during Hibernate-W-Clks mode). - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_TIMER_READ register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_S 1 -#define HIB3P3_MEM_HIB_RTC_TIMER_READ_mem_hib_rtc_timer_read \ - 0x00000001 // 1 - Latch the running RTC timer - // into local registers. After - // programming this bit to 1, the - // F/w can read the latched RTC - // timer values from - // MEM_HIB_RTC_TIMER_LSW and - // MEM_HIB_RTC_TIMER_MSW. Before the - // F/w (APPS or NWP) wants to read - // the RTC-Timer, it has to program - // this bit to 1, then only read the - // MSW and LSW values. This is an - // auto-clear bit. This register - // will be reset during Hibernate - // -WO-Clks mode (but not during - // Hibernate-W-Clks mode). - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_TIMER_LSW register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_M \ - 0xFFFFFFFF // Lower 32b value of the latched - // RTC-Timer. - -#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_TIMER_MSW register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_M \ - 0xFFFF0000 - -#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_S 16 -#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_M \ - 0x0000FFFF // Upper 32b value of the latched - // RTC-Timer. - -#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_WAKE_EN register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_S 1 -#define HIB3P3_MEM_HIB_RTC_WAKE_EN_mem_hib_rtc_wake_en \ - 0x00000001 // 1 - Enable the RTC timer based - // wakeup during Hibernate mode ; 0 - // - Disable the RTC timer based - // wakeup during Hibernate mode This - // register will be reset during - // Hibernate-WO-Clks mode (but not - // during Hibernate-W-Clks mode). - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_M \ - 0xFFFFFFFF // Configuration for RTC-Timer - // Wakeup (Lower 32b word) - -#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_M \ - 0xFFFF0000 - -#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_S 16 -#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_M \ - 0x0000FFFF // Configuration for RTC-Timer - // Wakeup (Upper 16b word) - -#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_INT_OSC_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_INT_OSC_CONF_reserved_M \ - 0xFFFF0000 - -#define HIB3P3_MEM_INT_OSC_CONF_reserved_S 16 -#define HIB3P3_MEM_INT_OSC_CONF_cm_clk_good_32k_int \ - 0x00008000 // 1 - Internal 32kHz Oscillator is - // valid ; 0 - Internal 32k - // oscillator clk is not valid - -#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_M \ - 0x00007E00 - -#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_S 9 -#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k_override_ctrl \ - 0x00000100 // When 1, the INT_32K_OSC_EN comes - // from bit [0] of this register, - // else comes from the FSM. This - // register will be reset during - // Hibernate-WO-Clks mode (but not - // during Hibernate-W-Clks mode) - -#define HIB3P3_MEM_INT_OSC_CONF_NU1 \ - 0x00000080 - -#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_M \ - 0x0000007E - -#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_S 1 -#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k \ - 0x00000001 // Override value for INT_OSC_EN. - // Applicable only when bit [3] of - // this register is set to 1. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_XTAL_OSC_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_M \ - 0xFFF00000 - -#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_S 20 -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k_override_ctrl \ - 0x00080000 // When 1, the SLICER_EN comes from - // bit [10] of this register, else - // comes from the FSM. - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k_override_ctrl \ - 0x00040000 // When 1, the XTAL_EN comes from - // bit [0] of this register, else - // comes from the FSM. - -#define HIB3P3_MEM_XTAL_OSC_CONF_cm_clk_good_xtal \ - 0x00020000 // 1 - XTAL Clk is good ; 0 - XTAL - // Clk is yet to be valid. - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_M \ - 0x0001F800 - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_S 11 -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k \ - 0x00000400 // SLICER_EN Override value : - // Applicable only when bit [19] of - // this register is set to 1. - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_M \ - 0x00000380 - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_S 7 -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_M \ - 0x00000070 - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_S 4 -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_fref_32k_slicer \ - 0x00000008 - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_M \ - 0x00000006 - -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_S 1 -#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k \ - 0x00000001 // XTAL_EN Override value : - // Applicable only when bit [18] of - // this register is set to 1. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_BGAP_PARAMETERS0 register. -// -//****************************************************************************** -#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_M \ - 0xFFF80000 - -#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_S 19 -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_en_seq \ - 0x00040000 - -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_M \ - 0x0001C000 - -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_S 14 -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbat_ok_4bg \ - 0x00001000 - -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp \ - 0x00000800 - -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp_ref \ - 0x00000400 - -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_M \ - 0x000003FF - -#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_BGAP_PARAMETERS1 register. -// -//****************************************************************************** -#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_M \ - 0xE0000000 - -#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_S 29 -#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_M \ - 0x1F000000 - -#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_S 24 -#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_act_iref \ - 0x00000008 - -#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_v2i \ - 0x00000004 - -#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_cap_sw \ - 0x00000002 - -#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_DETECTION_STATUS register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_M \ - 0xFFFFFF80 - -#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_S 7 -#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_ana_status \ - 0x00000040 // 1 - 1.8 V supply forced mode. - -#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_flash_status \ - 0x00000004 // 1 - 3.3 V supply forced mode for - // Flash supply - -#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_ext_clk_det_out_status \ - 0x00000002 // 1 - Forced clock mode - -#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_xtal_det_out_status \ - 0x00000001 // 1 - XTAL clock mode - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_MISC_CONTROLS register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_M \ - 0xFFFFF800 - -#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_S 11 -#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp \ - 0x00000400 - -#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp_ref \ - 0x00000200 - -#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_M \ - 0x000001C0 - -#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_S 6 -#define HIB3P3_MEM_HIB_MISC_CONTROLS_NU1 \ - 0x00000020 - -#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_flash_det_en \ - 0x00000010 - -#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_tmux \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_CONFIG register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_M \ - 0xFF000000 - -#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_S 24 -#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED3 \ - 0x00080000 // 1 - Enable VDD_FLASH_INDP_PAD - // for digital path (SHARED4) ; 0 - - // Disable VDD_FLASH_INDP_PAD for - // digital path (SHARED4) ; Before - // programming this bit to 1, ensure - // that the device is in FORCED 3.3 - // supply Mode, which can be - // inferred from the register : - // MEM_HIB_DETECTION_STATUS : 0x0040 - -#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED2 \ - 0x00040000 // 1 - Enable the - // VDD_FB_GPIO_MUX_PAD for digital - // path (SHARED3) ; 0 - Disable the - // VDD_FB_GPIO_MUX_PAD for digital - // path (SHARED3) ; This pin can be - // used only in modes other than - // SOP("111") - -#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED1 \ - 0x00020000 // 1 - Enable the PM_TEST_PAD for - // digital GPIO path (SHARED2) ; 0 - - // Disable the PM_TEST_PAD for - // digital GPIO path (SHARED2) This - // pin can be used for digital only - // in modes other then SOP-111 - -#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED0 \ - 0x00010000 // 1 - Enable the XTAL_N pin - // digital GPIO path (SHARED1); 0 - - // Disable the XTAL_N pin digital - // GPIO path (SHARED1). Before - // programming this bit to 1, ensure - // that the device is in FORCED CLK - // Mode, which can inferred from the - // register : - // MEM_HIB_DETECTION_STATUS : - // 0x0040. - -#define HIB3P3_MEM_HIB_CONFIG_mem_hib_xtal_enable \ - 0x00000100 // 1 - Enable the XTAL Clock ; 0 - - // Donot enable the XTAL Clock. This - // bit has to be programmed to 1 (by - // APPS Devinit F/w), during exit - // from OFF or Hib_wo_clks modes, - // after checking if the slow_clk - // mode is XTAL_CLK mode. Once - // enabled the XTAL will be disabled - // only after entering HIB_WO_CLKS - // mode. This register will be reset - // during Hibernate -WO-Clks mode - // (but not during Hibernate-W-Clks - // mode). - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_IRQ_ENABLE_HIB_RTC_IRQ_ENABLE \ - 0x00000001 // 1 - Enable the HIB RTC - IRQ ; 0 - // - Disable the HIB RTC - IRQ - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_M \ - 0xFFFFFFFF // Configuration for LSW of the - // RTC-Timestamp at which interrupt - // need to be generated - -#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_M \ - 0x0000FFFF // Configuration for MSW of thr - // RTC-Timestamp at which the - // interrupt need to be generated - -#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_UART_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_UART_CONF_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_MEM_HIB_UART_CONF_reserved_S 1 -#define HIB3P3_MEM_HIB_UART_CONF_mem_hib_uart_wake_en \ - 0x00000001 // 1 - Enable the UART-Autonomous - // mode wakeup during Hibernate mode - // ; This is an auto-clear bit, once - // programmed to 1, it will latched - // into an internal register which - // remain asserted until the - // Hib-wakeup is initiated. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_GPIO_WAKE_EN register. -// -//****************************************************************************** -#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_M \ - 0xFFFFFF00 - -#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_S 8 -#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_M \ - 0x000000FF // 1 - Enable the GPIO-Autonomous - // mode wakeup during Hibernate mode - // ; This is an auto-clear bit, once - // programmed to 1, it will latched - // into an internal register which - // remain asserted until the - // Hib-wakeup is initiated. - -#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_GPIO_WAKE_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_M \ - 0xFFFF0000 - -#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_S 16 -#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_M \ - 0x0000FFFF // Configuration to say whether the - // GPIO wakeup has to happen on - // Level0 or falling-edge for the - // given group. “00� – Level0 “01� – - // Level1 “10�- Fall-edge “11�- - // Rise-edge [1:0] – Conf for GPIO0 - // [3:2] – Conf for GPIO1 [5:4] – - // Conf for GPIO2 [7:6] – Conf for - // GPIO3 [9:8] – Conf for GPIO4 - // [11:10] – Conf for GPIO5 [13:12] - // – Conf for GPIO6 - -#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_PAD_OEN_RET33_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_PAD_OEN_RET33_CONF_mem_pad_oen_ret33_override_ctrl \ - 0x00000004 // 1 - Override the OEN33 and RET33 - // controls of GPIOs during - // SOP-Bootdebug mode ; 0 - Donot - // override the OEN33 and RET33 - // controls of GPIOs during - // SOP-Bootdebug mode - -#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_OEN33_CONF \ - 0x00000002 - -#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_RET33_CONF \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_mem_uart_nrts_oen_ret33_override_ctrl \ - 0x00000004 // 1 - Override the OEN33 and RET33 - // controls of UART NRTS GPIO during - // SOP-Bootdebug mode ; 0 - Donot - // override the OEN33 and RET33 - // controls of UART NRTS GPIO during - // SOP-Bootdebug mode - -#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_OEN33_CONF \ - 0x00000002 - -#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_RET33_CONF \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_JTAG_CONF register. -// -//****************************************************************************** -#define HIB3P3_MEM_JTAG_CONF_mem_jtag1_oen_ret33_override_ctrl \ - 0x00000200 - -#define HIB3P3_MEM_JTAG_CONF_mem_jtag0_oen_ret33_override_ctrl \ - 0x00000100 - -#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_OEN33_CONF \ - 0x00000008 - -#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_RET33_CONF \ - 0x00000004 - -#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_OEN33_CONF \ - 0x00000002 - -#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_RET33_CONF \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_REG0 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_M \ - 0xFFFFFFFF - -#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_REG1 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_M \ - 0xFFFFFFFF - -#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_REG2 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_M \ - 0xFFFFFFFF - -#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_REG3 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_M \ - 0xFFFFFFFF - -#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_M \ - 0xFFFF0000 // Configuration for the number of - // slow-clks between de-assertion of - // EN_BG_3P3V to assertion of - // EN_BG_3P3V - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_S 16 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_NU1 \ - 0x00008000 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_M \ - 0x00006000 // Configuration for the number of - // slow-clks between assertion of - // EN_COMP_3P3V and assertion of - // EN_COMP_LATCH_3P3V - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_S 13 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_M \ - 0x00001800 // Configuration for the number of - // slow-clks between assertion of - // (EN_CAP_SW_3P3V,EN_COMP_REF) and - // assertion of (EN_COMP_3P3V) - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_S 11 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_M \ - 0x00000600 // Configuration for the number of - // slow-clks between assertion of - // (EN_BG_3P3V) and assertion of - // (EN_CAP_SW_3P3V, - // EN_COMP_REF_3P3V) - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_S 9 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_crude_ref_comp \ - 0x00000100 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_ref_override_ctrl \ - 0x00000080 // 1 - EN_VBOK4BG_REF comes from - // bit[10] of the register - // MEM_BGAP_PARAMETERS0 [0x0038]. 0 - // - EN_VBOK4BG_REF comes directly - // from the Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_comp_override_ctrl \ - 0x00000040 // 1 - EN_VBOK4BG comes from - // bit[11] of the register - // MEM_BGAP_PARAMETERS0 [0x0038]. 0 - // - EN_VBOK4BG comes directly from - // the Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_v2i_override_ctrl \ - 0x00000020 // 1 - EN_V2I comes from bit[2] of - // the register MEM_BGAP_PARAMETERS1 - // [0x003C]. 0 - EN_V2I comes - // directly from the Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_por_comp_ref_override_ctrl \ - 0x00000010 // 1 - EN_POR_COMP_REF comes from - // bit[9] of the register - // MEM_HIB_MISC_CONTROLS [0x0044]. 0 - // - EN_POR_COMP_REF comes directly - // from the Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_por_comp_override_ctrl \ - 0x00000008 // 1 - EN_POR_COMP comes from - // bit[10] of the register - // MEM_HIB_MISC_CONTROLS [0x044]. 0 - // - EN_POR_COMP comes directly from - // the Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_cap_sw_override_ctrl \ - 0x00000004 // 1 - EN_CAP_SW comes from bit[1] - // of the register - // MEM_BGAP_PARAMETERS1 [0x003C]. 0 - // - EN_CAP_SW comes directly from - // Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bg_override_ctrl \ - 0x00000002 // 1 - EN_BGAP comes from bit[0] of - // the register MEM_BGAP_PARAMETERS1 - // [0x003C]. 0 - EN_BGAP comes - // directly from Hib-Sequencer. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_act_iref_override_ctrl \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_M \ - 0xFFFF0000 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_S 16 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_M \ - 0x0000C000 // Configuration for number of - // slow-clks between de-assertion of - // EN_COMP_LATCH and assertion of - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_S 14 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_M \ - 0x00003000 // Configuration for number of - // slow-clks between assertion of - // EN_COMP_REF to assertion of - // EN_COMP during HIB-Exit - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_S 12 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_M \ - 0x00000C00 // TBD - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_S 10 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_M \ - 0x00000300 // Configuration in number of - // slow-clks between assertion of - // (EN_BGAP_3P3V, EN_CAP_SW_3P3V, - // EN_ACT_IREF_3P3V, EN_COMP_REF) to - // assertion of EN_COMP_3P3V - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_S 8 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_M \ - 0x000000C0 // Configuration in number of - // slow-clks between de-assertion of - // (EN_COMP_3P3V, EN_COMP_REF_3P3V, - // EN_ACT_IREF_3P3V, EN_CAP_SW_3P3V) - // to deassertion of EN_BGAP_3P3V. - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_S 6 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_M \ - 0x0000003F - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_MISC_CONFIG register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_MISC_CONFIG_mem_en_pll_untrim_current \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_WAKE_STATUS register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_M \ - 0x0000001E // "0100" - GPIO ; "0010" - RTC ; - // "0001" - UART Others - Reserved - -#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_S 1 -#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_status \ - 0x00000001 // 1 - Wake from Hibernate ; 0 - - // Wake from OFF - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_M \ - 0x00000007 - -#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 register. -// -//****************************************************************************** -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_M \ - 0xFFFFF800 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_S 11 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_M \ - 0x00000600 // Deassertion of EN_COMP_LATCH_3P3 - // to deassertion of (EN_COMP_3P3, - // EN_COMP_REF_3P3, EN_ACT_IREF_3P3, - // EN_CAP_SW_3P3) - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_S 9 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_M \ - 0x000001C0 // Assertion of EN_COMP_LATCH_3P3 - // to deassertion of - // EN_COMP_LATCH_3P3 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_S 6 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_M \ - 0x00000030 // Deassertion of (EN_CAP_SW_3P3, - // EN_COMP_REF_3P3, EN_COMP_3P3, - // EN_COMP_OUT_LATCH_3P3) to - // deassertion of EN_BGAP_3P3 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_S 4 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_M \ - 0x0000000C // Assertion of EN_COMP_3P3 to - // assertion of EN_COMPOUT_LATCH_3P3 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_S 2 -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_M \ - 0x00000003 // Assertion of EN_COMP_3P3 to - // assertion of EN_COMPOUT_LATCH_3P3 - -#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIBANA_SPARE_LOWV register. -// -//****************************************************************************** -#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_M \ - 0xFFC00000 - -#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_S 22 -#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_M \ - 0x0001FFFF - -#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_TMUX_CTRL register. -// -//****************************************************************************** -#define HIB3P3_HIB_TMUX_CTRL_reserved_M \ - 0xFFFFFC00 - -#define HIB3P3_HIB_TMUX_CTRL_reserved_S 10 -#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_M \ - 0x000003FF - -#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_1P2_1P8_LDO_TRIM register. -// -//****************************************************************************** -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_M \ - 0xFFFFF000 - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_S 12 -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override_ctrl \ - 0x00000800 - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override_ctrl \ - 0x00000400 - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override \ - 0x00000200 - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override \ - 0x00000100 - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_M \ - 0x000000F0 - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_S 4 -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_M \ - 0x0000000F - -#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_COMP_TRIM register. -// -//****************************************************************************** -#define HIB3P3_HIB_COMP_TRIM_reserved_M \ - 0xFFFFFFF8 - -#define HIB3P3_HIB_COMP_TRIM_reserved_S 3 -#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_M \ - 0x00000007 - -#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_EN_TS register. -// -//****************************************************************************** -#define HIB3P3_HIB_EN_TS_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_HIB_EN_TS_reserved_S 1 -#define HIB3P3_HIB_EN_TS_mem_hd_en_ts \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_1P8V_DET_EN register. -// -//****************************************************************************** -#define HIB3P3_HIB_1P8V_DET_EN_reserved_M \ - 0xFFFFFFFE - -#define HIB3P3_HIB_1P8V_DET_EN_reserved_S 1 -#define HIB3P3_HIB_1P8V_DET_EN_mem_hib_1p8v_det_en \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_VBAT_MON_EN register. -// -//****************************************************************************** -#define HIB3P3_HIB_VBAT_MON_EN_reserved_M \ - 0xFFFFFFFC - -#define HIB3P3_HIB_VBAT_MON_EN_reserved_S 2 -#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_del_en \ - 0x00000002 - -#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_en \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_NHIB_ENABLE register. -// -//****************************************************************************** -#define HIB3P3_HIB_NHIB_ENABLE_mem_hib_nhib_enable \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// HIB3P3_O_HIB_UART_RTS_SW_ENABLE register. -// -//****************************************************************************** -#define HIB3P3_HIB_UART_RTS_SW_ENABLE_mem_hib_uart_rts_sw_enable \ - 0x00000001 - - - - -#endif // __HW_HIB3P3_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_i2c.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_i2c.h deleted file mode 100644 index 5a8246a615f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_i2c.h +++ /dev/null @@ -1,501 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_I2C_H__ -#define __HW_I2C_H__ - -//***************************************************************************** -// -// The following are defines for the I2C register offsets. -// -//***************************************************************************** -#define I2C_O_MSA 0x00000000 -#define I2C_O_MCS 0x00000004 -#define I2C_O_MDR 0x00000008 -#define I2C_O_MTPR 0x0000000C -#define I2C_O_MIMR 0x00000010 -#define I2C_O_MRIS 0x00000014 -#define I2C_O_MMIS 0x00000018 -#define I2C_O_MICR 0x0000001C -#define I2C_O_MCR 0x00000020 -#define I2C_O_MCLKOCNT 0x00000024 -#define I2C_O_MBMON 0x0000002C -#define I2C_O_MBLEN 0x00000030 -#define I2C_O_MBCNT 0x00000034 -#define I2C_O_SOAR 0x00000800 -#define I2C_O_SCSR 0x00000804 -#define I2C_O_SDR 0x00000808 -#define I2C_O_SIMR 0x0000080C -#define I2C_O_SRIS 0x00000810 -#define I2C_O_SMIS 0x00000814 -#define I2C_O_SICR 0x00000818 -#define I2C_O_SOAR2 0x0000081C -#define I2C_O_SACKCTL 0x00000820 -#define I2C_O_FIFODATA 0x00000F00 -#define I2C_O_FIFOCTL 0x00000F04 -#define I2C_O_FIFOSTATUS 0x00000F08 -#define I2C_O_OBSMUXSEL0 0x00000F80 -#define I2C_O_OBSMUXSEL1 0x00000F84 -#define I2C_O_MUXROUTE 0x00000F88 -#define I2C_O_PV 0x00000FB0 -#define I2C_O_PP 0x00000FC0 -#define I2C_O_PC 0x00000FC4 -#define I2C_O_CC 0x00000FC8 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MSA register. -// -//****************************************************************************** -#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address -#define I2C_MSA_SA_S 1 -#define I2C_MSA_RS 0x00000001 // Receive not send -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCS register. -// -//****************************************************************************** -#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status -#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status -#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error -#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy -#define I2C_MCS_IDLE 0x00000020 // I2C Idle -#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost -#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable -#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address -#define I2C_MCS_ERROR 0x00000002 // Error -#define I2C_MCS_BUSY 0x00000001 // I2C Busy -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MDR register. -// -//****************************************************************************** -#define I2C_MDR_DATA_M 0x000000FF // Data Transferred -#define I2C_MDR_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MTPR register. -// -//****************************************************************************** -#define I2C_MTPR_HS 0x00000080 // High-Speed Enable -#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period -#define I2C_MTPR_TPR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MIMR register. -// -//****************************************************************************** -#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask -#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt - // Mask -#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt - // Mask -#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask -#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask -#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask -#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask -#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask -#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask -#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask -#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MRIS register. -// -//****************************************************************************** -#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt - // Status -#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw - // Interrupt Status -#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw - // Interrupt Status -#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt - // Status -#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt - // Status -#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt - // Status -#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt - // Status -#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt - // Status -#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt - // Status -#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status -#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt - // Status -#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MMIS register. -// -//****************************************************************************** -#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask -#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt - // Mask -#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask -#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask -#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask -#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask -#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask -#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status -#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status -#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt - // Status -#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MICR register. -// -//****************************************************************************** -#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt - // Clear -#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt - // Clear -#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt - // Clear -#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt - // Clear -#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear -#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear -#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear -#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt - // Clear -#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear -#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear -#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear -#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCR register. -// -//****************************************************************************** -#define I2C_MCR_MMD 0x00000040 // Multi-master Disable -#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable -#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable -#define I2C_MCR_LPBK 0x00000001 // I2C Loopback -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. -// -//****************************************************************************** -#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count -#define I2C_MCLKOCNT_CNTL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBMON register. -// -//****************************************************************************** -#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status -#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBLEN register. -// -//****************************************************************************** -#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length -#define I2C_MBLEN_CNTL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MBCNT register. -// -//****************************************************************************** -#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count -#define I2C_MBCNT_CNTL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR register. -// -//****************************************************************************** -#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address -#define I2C_SOAR_OAR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SCSR register. -// -//****************************************************************************** -#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status -#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status -#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write -#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status -#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched -#define I2C_SCSR_FBR 0x00000004 // First Byte Received -#define I2C_SCSR_TREQ 0x00000002 // Transmit Request -#define I2C_SCSR_DA 0x00000001 // Device Active -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SDR register. -// -//****************************************************************************** -#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer -#define I2C_SDR_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SIMR register. -// -//****************************************************************************** -#define I2C_SIMR_IM 0x00000100 // Interrupt Mask -#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt - // Mask -#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt - // Mask -#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask -#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask -#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask -#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask -#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SRIS register. -// -//****************************************************************************** -#define I2C_SRIS_RIS 0x00000100 // Raw Interrupt Status -#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw - // Interrupt Status -#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw - // Interrupt Status -#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt - // Status -#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt - // Status -#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status -#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt - // Status -#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt - // Status -#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SMIS register. -// -//****************************************************************************** -#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt - // Mask -#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt - // Mask -#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt - // Status -#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt - // Status -#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt - // Status -#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt - // Status -#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SICR register. -// -//****************************************************************************** -#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask -#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt - // Mask -#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask -#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask -#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear -#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear -#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear -#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear -#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SOAR2 register. -// -//****************************************************************************** -#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable -#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 -#define I2C_SOAR2_OAR2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_SACKCTL register. -// -//****************************************************************************** -#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value -#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFODATA register. -// -//****************************************************************************** -#define I2C_FIFODATA_DATA_M 0x000000FF // I2C FIFO Data Byte -#define I2C_FIFODATA_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFOCTL register. -// -//****************************************************************************** -#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment -#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush -#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable -#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger -#define I2C_FIFOCTL_RXTRIG_S 16 -#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment -#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush -#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable -#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger -#define I2C_FIFOCTL_TXTRIG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_FIFOSTATUS register. -// -//****************************************************************************** -#define I2C_FIFOSTATUS_RXABVTRIG \ - 0x00040000 // RX FIFO Above Trigger Level - -#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full -#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty -#define I2C_FIFOSTATUS_TXBLWTRIG \ - 0x00000004 // TX FIFO Below Trigger Level - -#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full -#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_OBSMUXSEL0 register. -// -//****************************************************************************** -#define I2C_OBSMUXSEL0_LN3_M 0x07000000 // Observation Mux Lane 3 -#define I2C_OBSMUXSEL0_LN3_S 24 -#define I2C_OBSMUXSEL0_LN2_M 0x00070000 // Observation Mux Lane 2 -#define I2C_OBSMUXSEL0_LN2_S 16 -#define I2C_OBSMUXSEL0_LN1_M 0x00000700 // Observation Mux Lane 1 -#define I2C_OBSMUXSEL0_LN1_S 8 -#define I2C_OBSMUXSEL0_LN0_M 0x00000007 // Observation Mux Lane 0 -#define I2C_OBSMUXSEL0_LN0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_OBSMUXSEL1 register. -// -//****************************************************************************** -#define I2C_OBSMUXSEL1_LN7_M 0x07000000 // Observation Mux Lane 7 -#define I2C_OBSMUXSEL1_LN7_S 24 -#define I2C_OBSMUXSEL1_LN6_M 0x00070000 // Observation Mux Lane 6 -#define I2C_OBSMUXSEL1_LN6_S 16 -#define I2C_OBSMUXSEL1_LN5_M 0x00000700 // Observation Mux Lane 5 -#define I2C_OBSMUXSEL1_LN5_S 8 -#define I2C_OBSMUXSEL1_LN4_M 0x00000007 // Observation Mux Lane 4 -#define I2C_OBSMUXSEL1_LN4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_MUXROUTE register. -// -//****************************************************************************** -#define I2C_MUXROUTE_LN7ROUTE_M \ - 0x70000000 // Lane 7 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN7ROUTE_S 28 -#define I2C_MUXROUTE_LN6ROUTE_M \ - 0x07000000 // Lane 6 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN6ROUTE_S 24 -#define I2C_MUXROUTE_LN5ROUTE_M \ - 0x00700000 // Lane 5 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN5ROUTE_S 20 -#define I2C_MUXROUTE_LN4ROUTE_M \ - 0x00070000 // Lane 4 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN4ROUTE_S 16 -#define I2C_MUXROUTE_LN3ROUTE_M \ - 0x00007000 // Lane 3 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN3ROUTE_S 12 -#define I2C_MUXROUTE_LN2ROUTE_M \ - 0x00000700 // Lane 2 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN2ROUTE_S 8 -#define I2C_MUXROUTE_LN1ROUTE_M \ - 0x00000070 // Lane 1 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN1ROUTE_S 4 -#define I2C_MUXROUTE_LN0ROUTE_M \ - 0x00000007 // Lane 0 output is routed to the - // lane pointed to by the offset in - // this bit field - -#define I2C_MUXROUTE_LN0ROUTE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PV register. -// -//****************************************************************************** -#define I2C_PV_MAJOR_M 0x0000FF00 // Major Revision -#define I2C_PV_MAJOR_S 8 -#define I2C_PV_MINOR_M 0x000000FF // Minor Revision -#define I2C_PV_MINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PP register. -// -//****************************************************************************** -#define I2C_PP_HS 0x00000001 // High-Speed Capable -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_PC register. -// -//****************************************************************************** -#define I2C_PC_HS 0x00000001 // High-Speed Capable -//****************************************************************************** -// -// The following are defines for the bit fields in the I2C_O_CC register. -// -//****************************************************************************** - - - -#endif // __HW_I2C_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_ints.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_ints.h deleted file mode 100644 index 59da049796a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_ints.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -//***************************************************************************** -// -// hw_ints.h - Macros that define the interrupt assignment on CC3200. -// -//***************************************************************************** - -#ifndef __HW_INTS_H__ -#define __HW_INTS_H__ - -//***************************************************************************** -// -// The following are defines for the fault assignments. -// -//***************************************************************************** -#define FAULT_NMI 2 // NMI fault -#define FAULT_HARD 3 // Hard fault -#define FAULT_MPU 4 // MPU fault -#define FAULT_BUS 5 // Bus fault -#define FAULT_USAGE 6 // Usage fault -#define FAULT_SVCALL 11 // SVCall -#define FAULT_DEBUG 12 // Debug monitor -#define FAULT_PENDSV 14 // PendSV -#define FAULT_SYSTICK 15 // System Tick - -//***************************************************************************** -// -// The following are defines for the interrupt assignments. -// -//***************************************************************************** -#define INT_GPIOA0 16 // GPIO Port S0 -#define INT_GPIOA1 17 // GPIO Port S1 -#define INT_GPIOA2 18 // GPIO Port S2 -#define INT_GPIOA3 19 // GPIO Port S3 -#define INT_UARTA0 21 // UART0 Rx and Tx -#define INT_UARTA1 22 // UART1 Rx and Tx -#define INT_I2CA0 24 // I2C controller -#define INT_ADCCH0 30 // ADC Sequence 0 -#define INT_ADCCH1 31 // ADC Sequence 1 -#define INT_ADCCH2 32 // ADC Sequence 2 -#define INT_ADCCH3 33 // ADC Sequence 3 -#define INT_WDT 34 // Watchdog Timer0 -#define INT_TIMERA0A 35 // Timer 0 subtimer A -#define INT_TIMERA0B 36 // Timer 0 subtimer B -#define INT_TIMERA1A 37 // Timer 1 subtimer A -#define INT_TIMERA1B 38 // Timer 1 subtimer B -#define INT_TIMERA2A 39 // Timer 2 subtimer A -#define INT_TIMERA2B 40 // Timer 2 subtimer B -#define INT_FLASH 45 // FLASH Control -#define INT_TIMERA3A 51 // Timer 3 subtimer A -#define INT_TIMERA3B 52 // Timer 3 subtimer B -#define INT_UDMA 62 // uDMA controller -#define INT_UDMAERR 63 // uDMA Error -#define INT_SHA 164 // SHA -#define INT_AES 167 // AES -#define INT_DES 169 // DES -#define INT_MMCHS 175 // SDIO -#define INT_I2S 177 // McAPS -#define INT_CAMERA 179 // Camera -#define INT_NWPIC 187 // Interprocessor communication -#define INT_PRCM 188 // Power, Reset and Clock Module -#define INT_SSPI 191 // Shared SPI -#define INT_GSPI 192 // Generic SPI -#define INT_LSPI 193 // Link SPI - -//***************************************************************************** -// -// The following are defines for the total number of interrupts. -// -//***************************************************************************** -#define NUM_INTERRUPTS 195 //The above number plus 2? - - -//***************************************************************************** -// -// The following are defines for the total number of priority levels. -// -//***************************************************************************** -#define NUM_PRIORITY 8 -#define NUM_PRIORITY_BITS 3 - - -#endif // __HW_INTS_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_mcasp.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_mcasp.h deleted file mode 100644 index ec6e483dc4c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_mcasp.h +++ /dev/null @@ -1,1704 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_MCASP_H__ -#define __HW_MCASP_H__ - -//***************************************************************************** -// -// The following are defines for the MCASP register offsets. -// -//***************************************************************************** -#define MCASP_O_PID 0x00000000 -#define MCASP_O_ESYSCONFIG 0x00000004 // Power Idle SYSCONFIG register. -#define MCASP_O_PFUNC 0x00000010 -#define MCASP_O_PDIR 0x00000014 -#define MCASP_O_PDOUT 0x00000018 -#define MCASP_O_PDSET 0x0000001C // The pin data set register - // (PDSET) is an alias of the pin - // data output register (PDOUT) for - // writes only. Writing a 1 to the - // PDSET bit sets the corresponding - // bit in PDOUT and if PFUNC = 1 - // (GPIO function) and PDIR = 1 - // (output) drives a logic high on - // the pin. -#define MCASP_O_PDIN 0x0000001C // The pin data input register - // (PDIN) holds the I/O pin state of - // each of the McASP pins. PDIN - // allows the actual value of the - // pin to be read regardless of the - // state of PFUNC and PDIR. -#define MCASP_O_PDCLR 0x00000020 // The pin data clear register - // (PDCLR) is an alias of the pin - // data output register (PDOUT) for - // writes only. Writing a 1 to the - // PDCLR bit clears the - // corresponding bit in PDOUT and if - // PFUNC = 1 (GPIO function) and - // PDIR = 1 (output) drives a logic - // low on the pin. -#define MCASP_O_TLGC 0x00000030 // for IODFT -#define MCASP_O_TLMR 0x00000034 // for IODFT -#define MCASP_O_TLEC 0x00000038 // for IODFT -#define MCASP_O_GBLCTL 0x00000044 -#define MCASP_O_AMUTE 0x00000048 -#define MCASP_O_LBCTL 0x0000004C -#define MCASP_O_TXDITCTL 0x00000050 -#define MCASP_O_GBLCTLR 0x00000060 -#define MCASP_O_RXMASK 0x00000064 -#define MCASP_O_RXFMT 0x00000068 -#define MCASP_O_RXFMCTL 0x0000006C -#define MCASP_O_ACLKRCTL 0x00000070 -#define MCASP_O_AHCLKRCTL 0x00000074 -#define MCASP_O_RXTDM 0x00000078 -#define MCASP_O_EVTCTLR 0x0000007C -#define MCASP_O_RXSTAT 0x00000080 -#define MCASP_O_RXTDMSLOT 0x00000084 -#define MCASP_O_RXCLKCHK 0x00000088 -#define MCASP_O_REVTCTL 0x0000008C -#define MCASP_O_GBLCTLX 0x000000A0 -#define MCASP_O_TXMASK 0x000000A4 -#define MCASP_O_TXFMT 0x000000A8 -#define MCASP_O_TXFMCTL 0x000000AC -#define MCASP_O_ACLKXCTL 0x000000B0 -#define MCASP_O_AHCLKXCTL 0x000000B4 -#define MCASP_O_TXTDM 0x000000B8 -#define MCASP_O_EVTCTLX 0x000000BC -#define MCASP_O_TXSTAT 0x000000C0 -#define MCASP_O_TXTDMSLOT 0x000000C4 -#define MCASP_O_TXCLKCHK 0x000000C8 -#define MCASP_O_XEVTCTL 0x000000CC -#define MCASP_O_CLKADJEN 0x000000D0 -#define MCASP_O_DITCSRA0 0x00000100 -#define MCASP_O_DITCSRA1 0x00000104 -#define MCASP_O_DITCSRA2 0x00000108 -#define MCASP_O_DITCSRA3 0x0000010C -#define MCASP_O_DITCSRA4 0x00000110 -#define MCASP_O_DITCSRA5 0x00000114 -#define MCASP_O_DITCSRB0 0x00000118 -#define MCASP_O_DITCSRB1 0x0000011C -#define MCASP_O_DITCSRB2 0x00000120 -#define MCASP_O_DITCSRB3 0x00000124 -#define MCASP_O_DITCSRB4 0x00000128 -#define MCASP_O_DITCSRB5 0x0000012C -#define MCASP_O_DITUDRA0 0x00000130 -#define MCASP_O_DITUDRA1 0x00000134 -#define MCASP_O_DITUDRA2 0x00000138 -#define MCASP_O_DITUDRA3 0x0000013C -#define MCASP_O_DITUDRA4 0x00000140 -#define MCASP_O_DITUDRA5 0x00000144 -#define MCASP_O_DITUDRB0 0x00000148 -#define MCASP_O_DITUDRB1 0x0000014C -#define MCASP_O_DITUDRB2 0x00000150 -#define MCASP_O_DITUDRB3 0x00000154 -#define MCASP_O_DITUDRB4 0x00000158 -#define MCASP_O_DITUDRB5 0x0000015C -#define MCASP_O_XRSRCTL0 0x00000180 -#define MCASP_O_XRSRCTL1 0x00000184 -#define MCASP_O_XRSRCTL2 0x00000188 -#define MCASP_O_XRSRCTL3 0x0000018C -#define MCASP_O_XRSRCTL4 0x00000190 -#define MCASP_O_XRSRCTL5 0x00000194 -#define MCASP_O_XRSRCTL6 0x00000198 -#define MCASP_O_XRSRCTL7 0x0000019C -#define MCASP_O_XRSRCTL8 0x000001A0 -#define MCASP_O_XRSRCTL9 0x000001A4 -#define MCASP_O_XRSRCTL10 0x000001A8 -#define MCASP_O_XRSRCTL11 0x000001AC -#define MCASP_O_XRSRCTL12 0x000001B0 -#define MCASP_O_XRSRCTL13 0x000001B4 -#define MCASP_O_XRSRCTL14 0x000001B8 -#define MCASP_O_XRSRCTL15 0x000001BC -#define MCASP_O_TXBUF0 0x00000200 -#define MCASP_O_TXBUF1 0x00000204 -#define MCASP_O_TXBUF2 0x00000208 -#define MCASP_O_TXBUF3 0x0000020C -#define MCASP_O_TXBUF4 0x00000210 -#define MCASP_O_TXBUF5 0x00000214 -#define MCASP_O_TXBUF6 0x00000218 -#define MCASP_O_TXBUF7 0x0000021C -#define MCASP_O_TXBUF8 0x00000220 -#define MCASP_O_TXBUF9 0x00000224 -#define MCASP_O_TXBUF10 0x00000228 -#define MCASP_O_TXBUF11 0x0000022C -#define MCASP_O_TXBUF12 0x00000230 -#define MCASP_O_TXBUF13 0x00000234 -#define MCASP_O_TXBUF14 0x00000238 -#define MCASP_O_TXBUF15 0x0000023C -#define MCASP_O_RXBUF0 0x00000280 -#define MCASP_O_RXBUF1 0x00000284 -#define MCASP_O_RXBUF2 0x00000288 -#define MCASP_O_RXBUF3 0x0000028C -#define MCASP_O_RXBUF4 0x00000290 -#define MCASP_O_RXBUF5 0x00000294 -#define MCASP_O_RXBUF6 0x00000298 -#define MCASP_O_RXBUF7 0x0000029C -#define MCASP_O_RXBUF8 0x000002A0 -#define MCASP_O_RXBUF9 0x000002A4 -#define MCASP_O_RXBUF10 0x000002A8 -#define MCASP_O_RXBUF11 0x000002AC -#define MCASP_O_RXBUF12 0x000002B0 -#define MCASP_O_RXBUF13 0x000002B4 -#define MCASP_O_RXBUF14 0x000002B8 -#define MCASP_O_RXBUF15 0x000002BC -#define MCASP_0_WFIFOCTL 0x00001000 -#define MCASP_0_WFIFOSTS 0x00001004 -#define MCASP_0_RFIFOCTL 0x00001008 -#define MCASP_0_RFIFOSTS 0x0000100C - - -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PID register. -// -//****************************************************************************** -#define MCASP_PID_SCHEME_M 0xC0000000 -#define MCASP_PID_SCHEME_S 30 -#define MCASP_PID_RESV_M 0x30000000 -#define MCASP_PID_RESV_S 28 -#define MCASP_PID_FUNCTION_M 0x0FFF0000 // McASP -#define MCASP_PID_FUNCTION_S 16 -#define MCASP_PID_RTL_M 0x0000F800 -#define MCASP_PID_RTL_S 11 -#define MCASP_PID_REVMAJOR_M 0x00000700 -#define MCASP_PID_REVMAJOR_S 8 -#define MCASP_PID_CUSTOM_M 0x000000C0 // non-custom -#define MCASP_PID_CUSTOM_S 6 -#define MCASP_PID_REVMINOR_M 0x0000003F -#define MCASP_PID_REVMINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// MCASP_O_ESYSCONFIG register. -// -//****************************************************************************** -#define MCASP_ESYSCONFIG_RSV_M 0xFFFFFFC0 // Reserved as per PDR 3.5 -#define MCASP_ESYSCONFIG_RSV_S 6 -#define MCASP_ESYSCONFIG_OTHER_M \ - 0x0000003C // Reserved for future expansion - -#define MCASP_ESYSCONFIG_OTHER_S 2 -#define MCASP_ESYSCONFIG_IDLE_MODE_M \ - 0x00000003 // Idle Mode - -#define MCASP_ESYSCONFIG_IDLE_MODE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PFUNC register. -// -//****************************************************************************** -#define MCASP_PFUNC_AFSR 0x80000000 // AFSR PFUNC 31 0 1 -#define MCASP_PFUNC_AHCLKR 0x40000000 // AHCLKR PFUNC 30 0 1 -#define MCASP_PFUNC_ACLKR 0x20000000 // ACLKR PFUNC 29 0 1 -#define MCASP_PFUNC_AFSX 0x10000000 // AFSX PFUNC 28 0 1 -#define MCASP_PFUNC_AHCLKX 0x08000000 // AHCLKX PFUNC 27 0 1 -#define MCASP_PFUNC_ACLKX 0x04000000 // ACLKX PFUNC 26 0 1 -#define MCASP_PFUNC_AMUTE 0x02000000 // AMUTE PFUNC 25 0 1 -#define MCASP_PFUNC_RESV1_M 0x01FF0000 // Reserved -#define MCASP_PFUNC_RESV1_S 16 -#define MCASP_PFUNC_AXR15 0x00008000 // AXR PFUNC BIT 15 0 1 -#define MCASP_PFUNC_AXR14 0x00004000 // AXR PFUNC BIT 14 0 1 -#define MCASP_PFUNC_AXR13 0x00002000 // AXR PFUNC BIT 13 0 1 -#define MCASP_PFUNC_AXR12 0x00001000 // AXR PFUNC BIT 12 0 1 -#define MCASP_PFUNC_AXR11 0x00000800 // AXR PFUNC BIT 11 0 1 -#define MCASP_PFUNC_AXR10 0x00000400 // AXR PFUNC BIT 10 0 1 -#define MCASP_PFUNC_AXR9 0x00000200 // AXR PFUNC BIT 9 0 1 -#define MCASP_PFUNC_AXR8 0x00000100 // AXR PFUNC BIT 8 0 1 -#define MCASP_PFUNC_AXR7 0x00000080 // AXR PFUNC BIT 7 0 1 -#define MCASP_PFUNC_AXR6 0x00000040 // AXR PFUNC BIT 6 0 1 -#define MCASP_PFUNC_AXR5 0x00000020 // AXR PFUNC BIT 5 0 1 -#define MCASP_PFUNC_AXR4 0x00000010 // AXR PFUNC BIT 4 0 1 -#define MCASP_PFUNC_AXR3 0x00000008 // AXR PFUNC BIT 3 0 1 -#define MCASP_PFUNC_AXR2 0x00000004 // AXR PFUNC BIT 2 0 1 -#define MCASP_PFUNC_AXR1 0x00000002 // AXR PFUNC BIT 1 0 1 -#define MCASP_PFUNC_AXR0 0x00000001 // AXR PFUNC BIT 0 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PDIR register. -// -//****************************************************************************** -#define MCASP_PDIR_AFSR 0x80000000 // AFSR PDIR 31 0 1 -#define MCASP_PDIR_AHCLKR 0x40000000 // AHCLKR PDIR 30 0 1 -#define MCASP_PDIR_ACLKR 0x20000000 // ACLKR PDIR 29 0 1 -#define MCASP_PDIR_AFSX 0x10000000 // AFSX PDIR 28 0 1 -#define MCASP_PDIR_AHCLKX 0x08000000 // AHCLKX PDIR 27 0 1 -#define MCASP_PDIR_ACLKX 0x04000000 // ACLKX PDIR 26 0 1 -#define MCASP_PDIR_AMUTE 0x02000000 // AMUTE PDIR 25 0 1 -#define MCASP_PDIR_RESV_M 0x01FF0000 // Reserved -#define MCASP_PDIR_RESV_S 16 -#define MCASP_PDIR_AXR15 0x00008000 // AXR PDIR BIT 15 0 1 -#define MCASP_PDIR_AXR14 0x00004000 // AXR PDIR BIT 14 0 1 -#define MCASP_PDIR_AXR13 0x00002000 // AXR PDIR BIT 13 0 1 -#define MCASP_PDIR_AXR12 0x00001000 // AXR PDIR BIT 12 0 1 -#define MCASP_PDIR_AXR11 0x00000800 // AXR PDIR BIT 11 0 1 -#define MCASP_PDIR_AXR10 0x00000400 // AXR PDIR BIT 10 0 1 -#define MCASP_PDIR_AXR9 0x00000200 // AXR PDIR BIT 9 0 1 -#define MCASP_PDIR_AXR8 0x00000100 // AXR PDIR BIT 8 0 1 -#define MCASP_PDIR_AXR7 0x00000080 // AXR PDIR BIT 7 0 1 -#define MCASP_PDIR_AXR6 0x00000040 // AXR PDIR BIT 6 0 1 -#define MCASP_PDIR_AXR5 0x00000020 // AXR PDIR BIT 5 0 1 -#define MCASP_PDIR_AXR4 0x00000010 // AXR PDIR BIT 4 0 1 -#define MCASP_PDIR_AXR3 0x00000008 // AXR PDIR BIT 3 0 1 -#define MCASP_PDIR_AXR2 0x00000004 // AXR PDIR BIT 2 0 1 -#define MCASP_PDIR_AXR1 0x00000002 // AXR PDIR BIT 1 0 1 -#define MCASP_PDIR_AXR0 0x00000001 // AXR PDIR BIT 0 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PDOUT register. -// -//****************************************************************************** -#define MCASP_PDOUT_AFSR 0x80000000 // AFSR PDOUT 31 0 1 -#define MCASP_PDOUT_AHCLKR 0x40000000 // AHCLKR PDOUT 30 0 1 -#define MCASP_PDOUT_ACLKR 0x20000000 // ACLKR PDOUT 29 0 1 -#define MCASP_PDOUT_AFSX 0x10000000 // AFSX PDOUT 28 0 1 -#define MCASP_PDOUT_AHCLKX 0x08000000 // AHCLKX PDOUT 27 0 1 -#define MCASP_PDOUT_ACLKX 0x04000000 // ACLKX PDOUT 26 0 1 -#define MCASP_PDOUT_AMUTE 0x02000000 // AMUTE PDOUT 25 0 1 -#define MCASP_PDOUT_RESV_M 0x01FF0000 // Reserved -#define MCASP_PDOUT_RESV_S 16 -#define MCASP_PDOUT_AXR15 0x00008000 // AXR PDOUT BIT 15 0 1 -#define MCASP_PDOUT_AXR14 0x00004000 // AXR PDOUT BIT 14 0 1 -#define MCASP_PDOUT_AXR13 0x00002000 // AXR PDOUT BIT 13 0 1 -#define MCASP_PDOUT_AXR12 0x00001000 // AXR PDOUT BIT 12 0 1 -#define MCASP_PDOUT_AXR11 0x00000800 // AXR PDOUT BIT 11 0 1 -#define MCASP_PDOUT_AXR10 0x00000400 // AXR PDOUT BIT 10 0 1 -#define MCASP_PDOUT_AXR9 0x00000200 // AXR PDOUT BIT 9 0 1 -#define MCASP_PDOUT_AXR8 0x00000100 // AXR PDOUT BIT 8 0 1 -#define MCASP_PDOUT_AXR7 0x00000080 // AXR PDOUT BIT 7 0 1 -#define MCASP_PDOUT_AXR6 0x00000040 // AXR PDOUT BIT 6 0 1 -#define MCASP_PDOUT_AXR5 0x00000020 // AXR PDOUT BIT 5 0 1 -#define MCASP_PDOUT_AXR4 0x00000010 // AXR PDOUT BIT 4 0 1 -#define MCASP_PDOUT_AXR3 0x00000008 // AXR PDOUT BIT 3 0 1 -#define MCASP_PDOUT_AXR2 0x00000004 // AXR PDOUT BIT 2 0 1 -#define MCASP_PDOUT_AXR1 0x00000002 // AXR PDOUT BIT 1 0 1 -#define MCASP_PDOUT_AXR0 0x00000001 // AXR PDOUT BIT 0 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PDSET register. -// -//****************************************************************************** -#define MCASP_PDSET_AFSR 0x80000000 -#define MCASP_PDSET_AHCLKR 0x40000000 -#define MCASP_PDSET_ACLKR 0x20000000 -#define MCASP_PDSET_AFSX 0x10000000 -#define MCASP_PDSET_AHCLKX 0x08000000 -#define MCASP_PDSET_ACLKX 0x04000000 -#define MCASP_PDSET_AMUTE 0x02000000 -#define MCASP_PDSET_RESV_M 0x01FF0000 // Reserved -#define MCASP_PDSET_RESV_S 16 -#define MCASP_PDSET_AXR15 0x00008000 -#define MCASP_PDSET_AXR14 0x00004000 -#define MCASP_PDSET_AXR13 0x00002000 -#define MCASP_PDSET_AXR12 0x00001000 -#define MCASP_PDSET_AXR11 0x00000800 -#define MCASP_PDSET_AXR10 0x00000400 -#define MCASP_PDSET_AXR9 0x00000200 -#define MCASP_PDSET_AXR8 0x00000100 -#define MCASP_PDSET_AXR7 0x00000080 -#define MCASP_PDSET_AXR6 0x00000040 -#define MCASP_PDSET_AXR5 0x00000020 -#define MCASP_PDSET_AXR4 0x00000010 -#define MCASP_PDSET_AXR3 0x00000008 -#define MCASP_PDSET_AXR2 0x00000004 -#define MCASP_PDSET_AXR1 0x00000002 -#define MCASP_PDSET_AXR0 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PDIN register. -// -//****************************************************************************** -#define MCASP_PDIN_AFSR 0x80000000 -#define MCASP_PDIN_AHCLKR 0x40000000 -#define MCASP_PDIN_ACLKR 0x20000000 -#define MCASP_PDIN_AFSX 0x10000000 -#define MCASP_PDIN_AHCLKX 0x08000000 -#define MCASP_PDIN_ACLKX 0x04000000 -#define MCASP_PDIN_AMUTE 0x02000000 -#define MCASP_PDIN_RESV_M 0x01FF0000 // Reserved -#define MCASP_PDIN_RESV_S 16 -#define MCASP_PDIN_AXR15 0x00008000 -#define MCASP_PDIN_AXR14 0x00004000 -#define MCASP_PDIN_AXR13 0x00002000 -#define MCASP_PDIN_AXR12 0x00001000 -#define MCASP_PDIN_AXR11 0x00000800 -#define MCASP_PDIN_AXR10 0x00000400 -#define MCASP_PDIN_AXR9 0x00000200 -#define MCASP_PDIN_AXR8 0x00000100 -#define MCASP_PDIN_AXR7 0x00000080 -#define MCASP_PDIN_AXR6 0x00000040 -#define MCASP_PDIN_AXR5 0x00000020 -#define MCASP_PDIN_AXR4 0x00000010 -#define MCASP_PDIN_AXR3 0x00000008 -#define MCASP_PDIN_AXR2 0x00000004 -#define MCASP_PDIN_AXR1 0x00000002 -#define MCASP_PDIN_AXR0 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_PDCLR register. -// -//****************************************************************************** -#define MCASP_PDCLR_AFSR 0x80000000 // AFSR PDCLR 31 0 1 -#define MCASP_PDCLR_AHCLKR 0x40000000 // AHCLKR PDCLR 30 0 1 -#define MCASP_PDCLR_ACLKR 0x20000000 // ACLKR PDCLR 29 0 1 -#define MCASP_PDCLR_AFSX 0x10000000 // AFSX PDCLR 28 0 1 -#define MCASP_PDCLR_AHCLKX 0x08000000 // AHCLKX PDCLR 27 0 1 -#define MCASP_PDCLR_ACLKX 0x04000000 // ACLKX PDCLR 26 0 1 -#define MCASP_PDCLR_AMUTE 0x02000000 // AMUTE PDCLR 25 0 1 -#define MCASP_PDCLR_RESV_M 0x01FF0000 // Reserved -#define MCASP_PDCLR_RESV_S 16 -#define MCASP_PDCLR_AXR15 0x00008000 // AXR PDCLR BIT 15 0 1 -#define MCASP_PDCLR_AXR14 0x00004000 // AXR PDCLR BIT 14 0 1 -#define MCASP_PDCLR_AXR13 0x00002000 // AXR PDCLR BIT 13 0 1 -#define MCASP_PDCLR_AXR12 0x00001000 // AXR PDCLR BIT 12 0 1 -#define MCASP_PDCLR_AXR11 0x00000800 // AXR PDCLR BIT 11 0 1 -#define MCASP_PDCLR_AXR10 0x00000400 // AXR PDCLR BIT 10 0 1 -#define MCASP_PDCLR_AXR9 0x00000200 // AXR PDCLR BIT 9 0 1 -#define MCASP_PDCLR_AXR8 0x00000100 // AXR PDCLR BIT 8 0 1 -#define MCASP_PDCLR_AXR7 0x00000080 // AXR PDCLR BIT 7 0 1 -#define MCASP_PDCLR_AXR6 0x00000040 // AXR PDCLR BIT 6 0 1 -#define MCASP_PDCLR_AXR5 0x00000020 // AXR PDCLR BIT 5 0 1 -#define MCASP_PDCLR_AXR4 0x00000010 // AXR PDCLR BIT 4 0 1 -#define MCASP_PDCLR_AXR3 0x00000008 // AXR PDCLR BIT 3 0 1 -#define MCASP_PDCLR_AXR2 0x00000004 // AXR PDCLR BIT 2 0 1 -#define MCASP_PDCLR_AXR1 0x00000002 // AXR PDCLR BIT 1 0 1 -#define MCASP_PDCLR_AXR0 0x00000001 // AXR PDCLR BIT 0 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TLGC register. -// -//****************************************************************************** -#define MCASP_TLGC_RESV_M 0xFFFF0000 // Reserved -#define MCASP_TLGC_RESV_S 16 -#define MCASP_TLGC_MT_M 0x0000C000 // MISR on/off trigger command 0x0 - // 0x1 0x2 0x3 -#define MCASP_TLGC_MT_S 14 -#define MCASP_TLGC_RESV1_M 0x00003E00 // Reserved -#define MCASP_TLGC_RESV1_S 9 -#define MCASP_TLGC_MMS 0x00000100 // Source of MISR input 0 1 -#define MCASP_TLGC_ESEL 0x00000080 // Output enable select 0 1 -#define MCASP_TLGC_TOEN 0x00000040 // Test output enable control. 0 1 -#define MCASP_TLGC_MC_M 0x00000030 // States of MISR 0x0 0x1 0x2 0x3 -#define MCASP_TLGC_MC_S 4 -#define MCASP_TLGC_PC_M 0x0000000E // Pattern code 0x0 0x1 0x2 0x3 0x4 - // 0x5 0x6 0x7 -#define MCASP_TLGC_PC_S 1 -#define MCASP_TLGC_TM 0x00000001 // Tie high; do not write to this - // bit 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TLMR register. -// -//****************************************************************************** -#define MCASP_TLMR_TLMR_M 0xFFFFFFFF // Contains test result signature. -#define MCASP_TLMR_TLMR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TLEC register. -// -//****************************************************************************** -#define MCASP_TLEC_TLEC_M 0xFFFFFFFF // Contains number of cycles during - // which MISR sig will be - // accumulated. -#define MCASP_TLEC_TLEC_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_GBLCTL register. -// -//****************************************************************************** -#define MCASP_GBLCTL_XFRST 0x00001000 // Frame sync generator reset 0 1 -#define MCASP_GBLCTL_XSMRST 0x00000800 // XMT state machine reset 0 1 -#define MCASP_GBLCTL_XSRCLR 0x00000400 // XMT serializer clear 0 1 -#define MCASP_GBLCTL_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 -#define MCASP_GBLCTL_XCLKRST 0x00000100 // XMT clock divder reset 0 1 -#define MCASP_GBLCTL_RFRST 0x00000010 // Frame sync generator reset 0 1 -#define MCASP_GBLCTL_RSMRST 0x00000008 // RCV state machine reset 0 1 -#define MCASP_GBLCTL_RSRCLR 0x00000004 // RCV serializer clear 0 1 -#define MCASP_GBLCTL_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 -#define MCASP_GBLCTL_RCLKRST 0x00000001 // RCV clock divder reset 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_AMUTE register. -// -//****************************************************************************** -#define MCASP_AMUTE_XDMAERR 0x00001000 // MUTETXDMAERR occur 0 1 -#define MCASP_AMUTE_RDMAERR 0x00000800 // MUTERXDMAERR occur 0 1 -#define MCASP_AMUTE_XCKFAIL 0x00000400 // XMT bad clock 0 1 -#define MCASP_AMUTE_RCKFAIL 0x00000200 // RCV bad clock 0 1 -#define MCASP_AMUTE_XSYNCERR 0x00000100 // XMT unexpected FS 0 1 -#define MCASP_AMUTE_RSYNCERR 0x00000080 // RCV unexpected FS 0 1 -#define MCASP_AMUTE_XUNDRN 0x00000040 // XMT underrun occurs 0 1 -#define MCASP_AMUTE_ROVRN 0x00000020 // RCV overun occurs 0 1 -#define MCASP_AMUTE_INSTAT 0x00000010 -#define MCASP_AMUTE_INEN 0x00000008 // drive AMUTE active on mute in - // active 0 1 -#define MCASP_AMUTE_INPOL 0x00000004 // Mute input polarity 0 1 -#define MCASP_AMUTE_MUTEN_M 0x00000003 // AMUTE pin enable 0x0 0x1 0x2 -#define MCASP_AMUTE_MUTEN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_LBCTL register. -// -//****************************************************************************** -#define MCASP_LBCTL_IOLBEN 0x00000010 // IO loopback enable 0 1 -#define MCASP_LBCTL_MODE_M 0x0000000C // Loop back clock source generator - // 0x0 0x1 0x2 0x3 -#define MCASP_LBCTL_MODE_S 2 -#define MCASP_LBCTL_ORD 0x00000002 // Loopback order 0 1 -#define MCASP_LBCTL_DLBEN 0x00000001 // Loop back mode 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXDITCTL register. -// -//****************************************************************************** -#define MCASP_TXDITCTL_VB 0x00000008 // Valib bit for odd TDM 0 1 -#define MCASP_TXDITCTL_VA 0x00000004 // Valib bit for even TDM 0 1 -#define MCASP_TXDITCTL_DITEN 0x00000001 // XMT DIT Mode Enable 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_GBLCTLR register. -// -//****************************************************************************** -#define MCASP_GBLCTLR_XFRST 0x00001000 -#define MCASP_GBLCTLR_XSMRST 0x00000800 -#define MCASP_GBLCTLR_XSRCLR 0x00000400 -#define MCASP_GBLCTLR_XHCLKRST 0x00000200 -#define MCASP_GBLCTLR_XCLKRST 0x00000100 -#define MCASP_GBLCTLR_RFRST 0x00000010 // Frame sync generator reset 0 1 -#define MCASP_GBLCTLR_RSMRST 0x00000008 // RCV state machine reset 0 1 -#define MCASP_GBLCTLR_RSRCLR 0x00000004 // RCV serializer clear 0 1 -#define MCASP_GBLCTLR_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 -#define MCASP_GBLCTLR_RCLKRST 0x00000001 // RCV clock divder reset 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXMASK register. -// -//****************************************************************************** -#define MCASP_RXMASK_RMASK31 0x80000000 // RMASK BIT 31 0 1 -#define MCASP_RXMASK_RMASK30 0x40000000 // RMASK BIT 30 0 1 -#define MCASP_RXMASK_RMASK29 0x20000000 // RMASK BIT 29 0 1 -#define MCASP_RXMASK_RMASK28 0x10000000 // RMASK BIT 28 0 1 -#define MCASP_RXMASK_RMASK27 0x08000000 // RMASK BIT 27 0 1 -#define MCASP_RXMASK_RMASK26 0x04000000 // RMASK BIT 26 0 1 -#define MCASP_RXMASK_RMASK25 0x02000000 // RMASK BIT 25 0 1 -#define MCASP_RXMASK_RMASK24 0x01000000 // RMASK BIT 24 0 1 -#define MCASP_RXMASK_RMASK23 0x00800000 // RMASK BIT 23 0 1 -#define MCASP_RXMASK_RMASK22 0x00400000 // RMASK BIT 22 0 1 -#define MCASP_RXMASK_RMASK21 0x00200000 // RMASK BIT 21 0 1 -#define MCASP_RXMASK_RMASK20 0x00100000 // RMASK BIT 20 0 1 -#define MCASP_RXMASK_RMASK19 0x00080000 // RMASK BIT 19 0 1 -#define MCASP_RXMASK_RMASK18 0x00040000 // RMASK BIT 18 0 1 -#define MCASP_RXMASK_RMASK17 0x00020000 // RMASK BIT 17 0 1 -#define MCASP_RXMASK_RMASK16 0x00010000 // RMASK BIT 16 0 1 -#define MCASP_RXMASK_RMASK15 0x00008000 // RMASK BIT 15 0 1 -#define MCASP_RXMASK_RMASK14 0x00004000 // RMASK BIT 14 0 1 -#define MCASP_RXMASK_RMASK13 0x00002000 // RMASK BIT 13 0 1 -#define MCASP_RXMASK_RMASK12 0x00001000 // RMASK BIT 12 0 1 -#define MCASP_RXMASK_RMASK11 0x00000800 // RMASK BIT 11 0 1 -#define MCASP_RXMASK_RMASK10 0x00000400 // RMASK BIT 10 0 1 -#define MCASP_RXMASK_RMASK9 0x00000200 // RMASK BIT 9 0 1 -#define MCASP_RXMASK_RMASK8 0x00000100 // RMASK BIT 8 0 1 -#define MCASP_RXMASK_RMASK7 0x00000080 // RMASK BIT 7 0 1 -#define MCASP_RXMASK_RMASK6 0x00000040 // RMASK BIT 6 0 1 -#define MCASP_RXMASK_RMASK5 0x00000020 // RMASK BIT 5 0 1 -#define MCASP_RXMASK_RMASK4 0x00000010 // RMASK BIT 4 0 1 -#define MCASP_RXMASK_RMASK3 0x00000008 // RMASK BIT 3 0 1 -#define MCASP_RXMASK_RMASK2 0x00000004 // RMASK BIT 2 0 1 -#define MCASP_RXMASK_RMASK1 0x00000002 // RMASK BIT 1 0 1 -#define MCASP_RXMASK_RMASK0 0x00000001 // RMASK BIT 0 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXFMT register. -// -//****************************************************************************** -#define MCASP_RXFMT_RDATDLY_M 0x00030000 // RCV Frame sync delay 0x0 0 Bit - // delay 0x1 1 Bit delay 0x2 2 Bit - // delay -#define MCASP_RXFMT_RDATDLY_S 16 -#define MCASP_RXFMT_RRVRS 0x00008000 // RCV serial stream bit order 0 1 -#define MCASP_RXFMT_RPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 -#define MCASP_RXFMT_RPAD_S 13 -#define MCASP_RXFMT_RPBIT_M 0x00001F00 // Pad bit position -#define MCASP_RXFMT_RPBIT_S 8 -#define MCASP_RXFMT_RSSZ_M 0x000000F0 // RCV slot Size 0x0 0x1 0x2 0x3 - // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB - // 0xC 0xD 0xE 0xF -#define MCASP_RXFMT_RSSZ_S 4 -#define MCASP_RXFMT_RBUSEL 0x00000008 // Write to RBUF using CPU/DMA 0 - // DMA port access 1 CPU port Access -#define MCASP_RXFMT_RROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 - // 0x3 0x4 0x5 0x6 0x7 -#define MCASP_RXFMT_RROT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXFMCTL register. -// -//****************************************************************************** -#define MCASP_RXFMCTL_RMOD_M 0x0000FF80 // RCV Frame sync mode -#define MCASP_RXFMCTL_RMOD_S 7 -#define MCASP_RXFMCTL_FRWID 0x00000010 // RCV Frame sync Duration 0 1 -#define MCASP_RXFMCTL_FSRM 0x00000002 // RCV frame sync External 0 1 -#define MCASP_RXFMCTL_FSRP 0x00000001 // RCV Frame sync Polarity 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_ACLKRCTL register. -// -//****************************************************************************** -#define MCASP_ACLKRCTL_BUSY 0x00100000 -#define MCASP_ACLKRCTL_DIVBUSY 0x00080000 -#define MCASP_ACLKRCTL_ADJBUSY 0x00040000 -#define MCASP_ACLKRCTL_CLKRADJ_M \ - 0x00030000 - -#define MCASP_ACLKRCTL_CLKRADJ_S 16 -#define MCASP_ACLKRCTL_CLKRP 0x00000080 // RCV Clock Polarity 0 1 -#define MCASP_ACLKRCTL_CLKRM 0x00000020 // RCV clock source 0 1 -#define MCASP_ACLKRCTL_CLKRDIV_M \ - 0x0000001F // RCV clock devide ratio - -#define MCASP_ACLKRCTL_CLKRDIV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_AHCLKRCTL register. -// -//****************************************************************************** -#define MCASP_AHCLKRCTL_BUSY 0x00100000 -#define MCASP_AHCLKRCTL_DIVBUSY 0x00080000 -#define MCASP_AHCLKRCTL_ADJBUSY 0x00040000 -#define MCASP_AHCLKRCTL_HCLKRADJ_M \ - 0x00030000 - -#define MCASP_AHCLKRCTL_HCLKRADJ_S 16 -#define MCASP_AHCLKRCTL_HCLKRM 0x00008000 // High Freq. RCV clock Source 0 1 -#define MCASP_AHCLKRCTL_HCLKRP 0x00004000 // High Freq. clock Polarity Before - // diviser 0 1 -#define MCASP_AHCLKRCTL_HCLKRDIV_M \ - 0x00000FFF // RCV clock Divide Ratio - -#define MCASP_AHCLKRCTL_HCLKRDIV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXTDM register. -// -//****************************************************************************** -#define MCASP_RXTDM_RTDMS31 0x80000000 // RCV mode during TDM time slot 31 - // 0 1 -#define MCASP_RXTDM_RTDMS30 0x40000000 // RCV mode during TDM time slot 30 - // 0 1 -#define MCASP_RXTDM_RTDMS29 0x20000000 // RCV mode during TDM time slot 29 - // 0 1 -#define MCASP_RXTDM_RTDMS28 0x10000000 // RCV mode during TDM time slot 28 - // 0 1 -#define MCASP_RXTDM_RTDMS27 0x08000000 // RCV mode during TDM time slot 27 - // 0 1 -#define MCASP_RXTDM_RTDMS26 0x04000000 // RCV mode during TDM time slot 26 - // 0 1 -#define MCASP_RXTDM_RTDMS25 0x02000000 // RCV mode during TDM time slot 25 - // 0 1 -#define MCASP_RXTDM_RTDMS24 0x01000000 // RCV mode during TDM time slot 24 - // 0 1 -#define MCASP_RXTDM_RTDMS23 0x00800000 // RCV mode during TDM time slot 23 - // 0 1 -#define MCASP_RXTDM_RTDMS22 0x00400000 // RCV mode during TDM time slot 22 - // 0 1 -#define MCASP_RXTDM_RTDMS21 0x00200000 // RCV mode during TDM time slot 21 - // 0 1 -#define MCASP_RXTDM_RTDMS20 0x00100000 // RCV mode during TDM time slot 20 - // 0 1 -#define MCASP_RXTDM_RTDMS19 0x00080000 // RCV mode during TDM time slot 19 - // 0 1 -#define MCASP_RXTDM_RTDMS18 0x00040000 // RCV mode during TDM time slot 18 - // 0 1 -#define MCASP_RXTDM_RTDMS17 0x00020000 // RCV mode during TDM time slot 17 - // 0 1 -#define MCASP_RXTDM_RTDMS16 0x00010000 // RCV mode during TDM time slot 16 - // 0 1 -#define MCASP_RXTDM_RTDMS15 0x00008000 // RCV mode during TDM time slot 15 - // 0 1 -#define MCASP_RXTDM_RTDMS14 0x00004000 // RCV mode during TDM time slot 14 - // 0 1 -#define MCASP_RXTDM_RTDMS13 0x00002000 // RCV mode during TDM time slot 13 - // 0 1 -#define MCASP_RXTDM_RTDMS12 0x00001000 // RCV mode during TDM time slot 12 - // 0 1 -#define MCASP_RXTDM_RTDMS11 0x00000800 // RCV mode during TDM time slot 11 - // 0 1 -#define MCASP_RXTDM_RTDMS10 0x00000400 // RCV mode during TDM time slot 10 - // 0 1 -#define MCASP_RXTDM_RTDMS9 0x00000200 // RCV mode during TDM time slot 9 - // 0 1 -#define MCASP_RXTDM_RTDMS8 0x00000100 // RCV mode during TDM time slot 8 - // 0 1 -#define MCASP_RXTDM_RTDMS7 0x00000080 // RCV mode during TDM time slot 7 - // 0 1 -#define MCASP_RXTDM_RTDMS6 0x00000040 // RCV mode during TDM time slot 6 - // 0 1 -#define MCASP_RXTDM_RTDMS5 0x00000020 // RCV mode during TDM time slot 5 - // 0 1 -#define MCASP_RXTDM_RTDMS4 0x00000010 // RCV mode during TDM time slot 4 - // 0 1 -#define MCASP_RXTDM_RTDMS3 0x00000008 // RCV mode during TDM time slot 3 - // 0 1 -#define MCASP_RXTDM_RTDMS2 0x00000004 // RCV mode during TDM time slot 2 - // 0 1 -#define MCASP_RXTDM_RTDMS1 0x00000002 // RCV mode during TDM time slot 1 - // 0 1 -#define MCASP_RXTDM_RTDMS0 0x00000001 // RCV mode during TDM time slot 0 - // 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_EVTCTLR register. -// -//****************************************************************************** -#define MCASP_EVTCTLR_RSTAFRM 0x00000080 // RCV Start of Frame Interrupt 0 1 -#define MCASP_EVTCTLR_RDATA 0x00000020 // RCV Data Interrupt 0 1 -#define MCASP_EVTCTLR_RLAST 0x00000010 // RCV Last Slot Interrupt 0 1 -#define MCASP_EVTCTLR_RDMAERR 0x00000008 // RCV DMA Bus Error 0 1 -#define MCASP_EVTCTLR_RCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 -#define MCASP_EVTCTLR_RSYNCERR 0x00000002 // RCV Unexpected FSR Interrupt 0 1 -#define MCASP_EVTCTLR_ROVRN 0x00000001 // RCV Underrun Flag 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXSTAT register. -// -//****************************************************************************** -#define MCASP_RXSTAT_RERR 0x00000100 // RCV Error 0 1 -#define MCASP_RXSTAT_RDMAERR 0x00000080 // RCV DMA bus error 0 1 -#define MCASP_RXSTAT_RSTAFRM 0x00000040 // Start of Frame-RCV 0 1 -#define MCASP_RXSTAT_RDATA 0x00000020 // Data Ready Flag 0 1 -#define MCASP_RXSTAT_RLAST 0x00000010 // Last Slot Interrupt Flag 0 1 -#define MCASP_RXSTAT_RTDMSLOT 0x00000008 // EvenOdd Slot 0 1 -#define MCASP_RXSTAT_RCKFAIL 0x00000004 // Bad Transmit Flag 0 1 -#define MCASP_RXSTAT_RSYNCERR 0x00000002 // Unexpected RCV Frame sync flag 0 - // 1 -#define MCASP_RXSTAT_ROVRN 0x00000001 // RCV Underrun Flag 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXTDMSLOT register. -// -//****************************************************************************** -#define MCASP_RXTDMSLOT_RSLOTCNT_M \ - 0x000003FF // Current RCV time slot count - -#define MCASP_RXTDMSLOT_RSLOTCNT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXCLKCHK register. -// -//****************************************************************************** -#define MCASP_RXCLKCHK_RCNT_M 0xFF000000 // RCV clock count value -#define MCASP_RXCLKCHK_RCNT_S 24 -#define MCASP_RXCLKCHK_RMAX_M 0x00FF0000 // RCV clock maximum boundary -#define MCASP_RXCLKCHK_RMAX_S 16 -#define MCASP_RXCLKCHK_RMIN_M 0x0000FF00 // RCV clock minimum boundary -#define MCASP_RXCLKCHK_RMIN_S 8 -#define MCASP_RXCLKCHK_RPS_M 0x0000000F // RCV clock check prescaler 0x0 - // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 -#define MCASP_RXCLKCHK_RPS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_REVTCTL register. -// -//****************************************************************************** -#define MCASP_REVTCTL_RDATDMA 0x00000001 // RCV data DMA request 0 Enable - // DMA Transfer 1 Disable DMA - // Transfer -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_GBLCTLX register. -// -//****************************************************************************** -#define MCASP_GBLCTLX_XFRST 0x00001000 // Frame sync generator reset 0 1 -#define MCASP_GBLCTLX_XSMRST 0x00000800 // XMT state machine reset 0 1 -#define MCASP_GBLCTLX_XSRCLR 0x00000400 // XMT serializer clear 0 1 -#define MCASP_GBLCTLX_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 -#define MCASP_GBLCTLX_XCLKRST 0x00000100 // XMT clock divder reset 0 1 -#define MCASP_GBLCTLX_RFRST 0x00000010 -#define MCASP_GBLCTLX_RSMRST 0x00000008 -#define MCASP_GBLCTLX_RSRCLKR 0x00000004 -#define MCASP_GBLCTLX_RHCLKRST 0x00000002 -#define MCASP_GBLCTLX_RCLKRST 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXMASK register. -// -//****************************************************************************** -#define MCASP_TXMASK_XMASK31 0x80000000 // XMASK BIT 31 0 1 -#define MCASP_TXMASK_XMASK30 0x40000000 // XMASK BIT 30 0 1 -#define MCASP_TXMASK_XMASK29 0x20000000 // XMASK BIT 29 0 1 -#define MCASP_TXMASK_XMASK28 0x10000000 // XMASK BIT 28 0 1 -#define MCASP_TXMASK_XMASK27 0x08000000 // XMASK BIT 27 0 1 -#define MCASP_TXMASK_XMASK26 0x04000000 // XMASK BIT 26 0 1 -#define MCASP_TXMASK_XMASK25 0x02000000 // XMASK BIT 25 0 1 -#define MCASP_TXMASK_XMASK24 0x01000000 // XMASK BIT 24 0 1 -#define MCASP_TXMASK_XMASK23 0x00800000 // XMASK BIT 23 0 1 -#define MCASP_TXMASK_XMASK22 0x00400000 // XMASK BIT 22 0 1 -#define MCASP_TXMASK_XMASK21 0x00200000 // XMASK BIT 21 0 1 -#define MCASP_TXMASK_XMASK20 0x00100000 // XMASK BIT 20 0 1 -#define MCASP_TXMASK_XMASK19 0x00080000 // XMASK BIT 19 0 1 -#define MCASP_TXMASK_XMASK18 0x00040000 // XMASK BIT 18 0 1 -#define MCASP_TXMASK_XMASK17 0x00020000 // XMASK BIT 17 0 1 -#define MCASP_TXMASK_XMASK16 0x00010000 // XMASK BIT 16 0 1 -#define MCASP_TXMASK_XMASK15 0x00008000 // XMASK BIT 15 0 1 -#define MCASP_TXMASK_XMASK14 0x00004000 // XMASK BIT 14 0 1 -#define MCASP_TXMASK_XMASK13 0x00002000 // XMASK BIT 13 0 1 -#define MCASP_TXMASK_XMASK12 0x00001000 // XMASK BIT 12 0 1 -#define MCASP_TXMASK_XMASK11 0x00000800 // XMASK BIT 11 0 1 -#define MCASP_TXMASK_XMASK10 0x00000400 // XMASK BIT 10 0 1 -#define MCASP_TXMASK_XMASK9 0x00000200 // XMASK BIT 9 0 1 -#define MCASP_TXMASK_XMASK8 0x00000100 // XMASK BIT 8 0 1 -#define MCASP_TXMASK_XMASK7 0x00000080 // XMASK BIT 7 0 1 -#define MCASP_TXMASK_XMASK6 0x00000040 // XMASK BIT 6 0 1 -#define MCASP_TXMASK_XMASK5 0x00000020 // XMASK BIT 5 0 1 -#define MCASP_TXMASK_XMASK4 0x00000010 // XMASK BIT 4 0 1 -#define MCASP_TXMASK_XMASK3 0x00000008 // XMASK BIT 3 0 1 -#define MCASP_TXMASK_XMASK2 0x00000004 // XMASK BIT 2 0 1 -#define MCASP_TXMASK_XMASK1 0x00000002 // XMASK BIT 1 0 1 -#define MCASP_TXMASK_XMASK0 0x00000001 // XMASK BIT 0 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXFMT register. -// -//****************************************************************************** -#define MCASP_TXFMT_XDATDLY_M 0x00030000 // XMT Frame sync delay 0x0 0 Bit - // delay 0x1 1 Bit delay 0x2 2 Bit - // delay -#define MCASP_TXFMT_XDATDLY_S 16 -#define MCASP_TXFMT_XRVRS 0x00008000 // XMT serial stream bit order 0 1 -#define MCASP_TXFMT_XPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 -#define MCASP_TXFMT_XPAD_S 13 -#define MCASP_TXFMT_XPBIT_M 0x00001F00 // Pad bit position -#define MCASP_TXFMT_XPBIT_S 8 -#define MCASP_TXFMT_XSSZ_M 0x000000F0 // XMT slot Size 0x0 0x1 0x2 0x3 - // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB - // 0xC 0xD 0xE 0xF -#define MCASP_TXFMT_XSSZ_S 4 -#define MCASP_TXFMT_XBUSEL 0x00000008 // Write to XBUF using CPU/DMA 0 - // DMA port access 1 CPU port Access -#define MCASP_TXFMT_XROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 - // 0x3 0x4 0x5 0x6 0x7 -#define MCASP_TXFMT_XROT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXFMCTL register. -// -//****************************************************************************** -#define MCASP_TXFMCTL_XMOD_M 0x0000FF80 // XMT Frame sync mode -#define MCASP_TXFMCTL_XMOD_S 7 -#define MCASP_TXFMCTL_FXWID 0x00000010 // XMT Frame sync Duration 0 1 -#define MCASP_TXFMCTL_FSXM 0x00000002 // XMT frame sync External 0 1 -#define MCASP_TXFMCTL_FSXP 0x00000001 // XMT Frame sync Polarity 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_ACLKXCTL register. -// -//****************************************************************************** -#define MCASP_ACLKXCTL_BUSY 0x00100000 -#define MCASP_ACLKXCTL_DIVBUSY 0x00080000 -#define MCASP_ACLKXCTL_ADJBUSY 0x00040000 -#define MCASP_ACLKXCTL_CLKXADJ_M \ - 0x00030000 - -#define MCASP_ACLKXCTL_CLKXADJ_S 16 -#define MCASP_ACLKXCTL_CLKXP 0x00000080 // XMT Clock Polarity 0 1 -#define MCASP_ACLKXCTL_ASYNC 0x00000040 // XMT/RCV operation sync /Async 0 - // 1 -#define MCASP_ACLKXCTL_CLKXM 0x00000020 // XMT clock source 0 1 -#define MCASP_ACLKXCTL_CLKXDIV_M \ - 0x0000001F // XMT clock devide ratio - -#define MCASP_ACLKXCTL_CLKXDIV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_AHCLKXCTL register. -// -//****************************************************************************** -#define MCASP_AHCLKXCTL_BUSY 0x00100000 -#define MCASP_AHCLKXCTL_DIVBUSY 0x00080000 -#define MCASP_AHCLKXCTL_ADJBUSY 0x00040000 -#define MCASP_AHCLKXCTL_HCLKXADJ_M \ - 0x00030000 - -#define MCASP_AHCLKXCTL_HCLKXADJ_S 16 -#define MCASP_AHCLKXCTL_HCLKXM 0x00008000 // High Freq. XMT clock Source 0 1 -#define MCASP_AHCLKXCTL_HCLKXP 0x00004000 // High Freq. clock Polarity Before - // diviser 0 1 -#define MCASP_AHCLKXCTL_HCLKXDIV_M \ - 0x00000FFF // XMT clock Divide Ratio - -#define MCASP_AHCLKXCTL_HCLKXDIV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXTDM register. -// -//****************************************************************************** -#define MCASP_TXTDM_XTDMS31 0x80000000 // XMT mode during TDM time slot 31 - // 0 1 -#define MCASP_TXTDM_XTDMS30 0x40000000 // XMT mode during TDM time slot 30 - // 0 1 -#define MCASP_TXTDM_XTDMS29 0x20000000 // XMT mode during TDM time slot 29 - // 0 1 -#define MCASP_TXTDM_XTDMS28 0x10000000 // XMT mode during TDM time slot 28 - // 0 1 -#define MCASP_TXTDM_XTDMS27 0x08000000 // XMT mode during TDM time slot 27 - // 0 1 -#define MCASP_TXTDM_XTDMS26 0x04000000 // XMT mode during TDM time slot 26 - // 0 1 -#define MCASP_TXTDM_XTDMS25 0x02000000 // XMT mode during TDM time slot 25 - // 0 1 -#define MCASP_TXTDM_XTDMS24 0x01000000 // XMT mode during TDM time slot 24 - // 0 1 -#define MCASP_TXTDM_XTDMS23 0x00800000 // XMT mode during TDM time slot 23 - // 0 1 -#define MCASP_TXTDM_XTDMS22 0x00400000 // XMT mode during TDM time slot 22 - // 0 1 -#define MCASP_TXTDM_XTDMS21 0x00200000 // XMT mode during TDM time slot 21 - // 0 1 -#define MCASP_TXTDM_XTDMS20 0x00100000 // XMT mode during TDM time slot 20 - // 0 1 -#define MCASP_TXTDM_XTDMS19 0x00080000 // XMT mode during TDM time slot 19 - // 0 1 -#define MCASP_TXTDM_XTDMS18 0x00040000 // XMT mode during TDM time slot 18 - // 0 1 -#define MCASP_TXTDM_XTDMS17 0x00020000 // XMT mode during TDM time slot 17 - // 0 1 -#define MCASP_TXTDM_XTDMS16 0x00010000 // XMT mode during TDM time slot 16 - // 0 1 -#define MCASP_TXTDM_XTDMS15 0x00008000 // XMT mode during TDM time slot 15 - // 0 1 -#define MCASP_TXTDM_XTDMS14 0x00004000 // XMT mode during TDM time slot 14 - // 0 1 -#define MCASP_TXTDM_XTDMS13 0x00002000 // XMT mode during TDM time slot 13 - // 0 1 -#define MCASP_TXTDM_XTDMS12 0x00001000 // XMT mode during TDM time slot 12 - // 0 1 -#define MCASP_TXTDM_XTDMS11 0x00000800 // XMT mode during TDM time slot 11 - // 0 1 -#define MCASP_TXTDM_XTDMS10 0x00000400 // XMT mode during TDM time slot 10 - // 0 1 -#define MCASP_TXTDM_XTDMS9 0x00000200 // XMT mode during TDM time slot 9 - // 0 1 -#define MCASP_TXTDM_XTDMS8 0x00000100 // XMT mode during TDM time slot 8 - // 0 1 -#define MCASP_TXTDM_XTDMS7 0x00000080 // XMT mode during TDM time slot 7 - // 0 1 -#define MCASP_TXTDM_XTDMS6 0x00000040 // XMT mode during TDM time slot 6 - // 0 1 -#define MCASP_TXTDM_XTDMS5 0x00000020 // XMT mode during TDM time slot 5 - // 0 1 -#define MCASP_TXTDM_XTDMS4 0x00000010 // XMT mode during TDM time slot 4 - // 0 1 -#define MCASP_TXTDM_XTDMS3 0x00000008 // XMT mode during TDM time slot 3 - // 0 1 -#define MCASP_TXTDM_XTDMS2 0x00000004 // XMT mode during TDM time slot 2 - // 0 1 -#define MCASP_TXTDM_XTDMS1 0x00000002 // XMT mode during TDM time slot 1 - // 0 1 -#define MCASP_TXTDM_XTDMS0 0x00000001 // XMT mode during TDM time slot 0 - // 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_EVTCTLX register. -// -//****************************************************************************** -#define MCASP_EVTCTLX_XSTAFRM 0x00000080 // XMT Start of Frame Interrupt 0 1 -#define MCASP_EVTCTLX_XDATA 0x00000020 // XMT Data Interrupt 0 1 -#define MCASP_EVTCTLX_XLAST 0x00000010 // XMT Last Slot Interrupt 0 1 -#define MCASP_EVTCTLX_XDMAERR 0x00000008 // XMT DMA Bus Error 0 1 -#define MCASP_EVTCTLX_XCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 -#define MCASP_EVTCTLX_XSYNCERR 0x00000002 // XMT Unexpected FSR Interrupt 0 1 -#define MCASP_EVTCTLX_XUNDRN 0x00000001 // XMT Underrun Interrupt 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXSTAT register. -// -//****************************************************************************** -#define MCASP_TXSTAT_XERR 0x00000100 // XMT Error 0 1 -#define MCASP_TXSTAT_XDMAERR 0x00000080 // XMT DMA bus error 0 1 -#define MCASP_TXSTAT_XSTAFRM 0x00000040 // Start of Frame-XMT 0 1 -#define MCASP_TXSTAT_XDATA 0x00000020 // Data Ready Flag 0 1 -#define MCASP_TXSTAT_XLAST 0x00000010 // Last Slot Interrupt Flag 0 1 -#define MCASP_TXSTAT_XTDMSLOT 0x00000008 // EvenOdd Slot 0 1 -#define MCASP_TXSTAT_XCKFAIL 0x00000004 // Bad Transmit Flag 0 1 -#define MCASP_TXSTAT_XSYNCERR 0x00000002 // Unexpected XMT Frame sync flag 0 - // 1 -#define MCASP_TXSTAT_XUNDRN 0x00000001 // XMT Underrun Flag 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXTDMSLOT register. -// -//****************************************************************************** -#define MCASP_TXTDMSLOT_XSLOTCNT_M \ - 0x000003FF // Current XMT time slot count - // during reset the value of this - // register is 0b0101111111 (0x17f) - // and after reset 0 - -#define MCASP_TXTDMSLOT_XSLOTCNT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXCLKCHK register. -// -//****************************************************************************** -#define MCASP_TXCLKCHK_XCNT_M 0xFF000000 // XMT clock count value -#define MCASP_TXCLKCHK_XCNT_S 24 -#define MCASP_TXCLKCHK_XMAX_M 0x00FF0000 // XMT clock maximum boundary -#define MCASP_TXCLKCHK_XMAX_S 16 -#define MCASP_TXCLKCHK_XMIN_M 0x0000FF00 // XMT clock minimum boundary -#define MCASP_TXCLKCHK_XMIN_S 8 -#define MCASP_TXCLKCHK_RESV 0x00000080 // Reserved -#define MCASP_TXCLKCHK_XPS_M 0x0000000F // XMT clock check prescaler 0x0 - // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 -#define MCASP_TXCLKCHK_XPS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XEVTCTL register. -// -//****************************************************************************** -#define MCASP_XEVTCTL_XDATDMA 0x00000001 // XMT data DMA request 0 Enable - // DMA Transfer 1 Disable DMA - // Transfer -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_CLKADJEN register. -// -//****************************************************************************** -#define MCASP_CLKADJEN_ENABLE 0x00000001 // One-shot clock adjust enable 0 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRA0 register. -// -//****************************************************************************** -#define MCASP_DITCSRA0_DITCSRA0_M \ - 0xFFFFFFFF // Left (Even TDM slot ) Channel - // status - -#define MCASP_DITCSRA0_DITCSRA0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRA1 register. -// -//****************************************************************************** -#define MCASP_DITCSRA1_DITCSRA1_M \ - 0xFFFFFFFF // Left (Even TDM slot ) Channel - // status - -#define MCASP_DITCSRA1_DITCSRA1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRA2 register. -// -//****************************************************************************** -#define MCASP_DITCSRA2_DITCSRA2_M \ - 0xFFFFFFFF // Left (Even TDM slot ) Channel - // status Register - -#define MCASP_DITCSRA2_DITCSRA2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRA3 register. -// -//****************************************************************************** -#define MCASP_DITCSRA3_DITCSRA3_M \ - 0xFFFFFFFF // Left (Even TDM slot ) Channel - // status Register - -#define MCASP_DITCSRA3_DITCSRA3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRA4 register. -// -//****************************************************************************** -#define MCASP_DITCSRA4_DITCSRA4_M \ - 0xFFFFFFFF // Left (Even TDM slot ) Channel - // status - -#define MCASP_DITCSRA4_DITCSRA4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRA5 register. -// -//****************************************************************************** -#define MCASP_DITCSRA5_DITCSRA5_M \ - 0xFFFFFFFF // Left (Even TDM slot ) Channel - // status - -#define MCASP_DITCSRA5_DITCSRA5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRB0 register. -// -//****************************************************************************** -#define MCASP_DITCSRB0_DITCSRB0_M \ - 0xFFFFFFFF // Right (odd TDM slot ) Channel - // status - -#define MCASP_DITCSRB0_DITCSRB0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRB1 register. -// -//****************************************************************************** -#define MCASP_DITCSRB1_DITCSRB1_M \ - 0xFFFFFFFF // Right (odd TDM slot ) Channel - // status - -#define MCASP_DITCSRB1_DITCSRB1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRB2 register. -// -//****************************************************************************** -#define MCASP_DITCSRB2_DITCSRB2_M \ - 0xFFFFFFFF // Right (odd TDM slot ) Channel - // status - -#define MCASP_DITCSRB2_DITCSRB2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRB3 register. -// -//****************************************************************************** -#define MCASP_DITCSRB3_DITCSRB3_M \ - 0xFFFFFFFF // Right (odd TDM slot ) Channel - // status - -#define MCASP_DITCSRB3_DITCSRB3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRB4 register. -// -//****************************************************************************** -#define MCASP_DITCSRB4_DITCSRB4_M \ - 0xFFFFFFFF // Right (odd TDM slot ) Channel - // status - -#define MCASP_DITCSRB4_DITCSRB4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITCSRB5 register. -// -//****************************************************************************** -#define MCASP_DITCSRB5_DITCSRB5_M \ - 0xFFFFFFFF // Right (odd TDM slot ) Channel - // status - -#define MCASP_DITCSRB5_DITCSRB5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRA0 register. -// -//****************************************************************************** -#define MCASP_DITUDRA0_DITUDRA0_M \ - 0xFFFFFFFF // Left (Even TDM slot ) User Data - -#define MCASP_DITUDRA0_DITUDRA0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRA1 register. -// -//****************************************************************************** -#define MCASP_DITUDRA1_DITUDRA1_M \ - 0xFFFFFFFF // Left (Even TDM slot ) User Data - -#define MCASP_DITUDRA1_DITUDRA1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRA2 register. -// -//****************************************************************************** -#define MCASP_DITUDRA2_DITUDRA2_M \ - 0xFFFFFFFF // Left (Even TDM slot ) User Data - -#define MCASP_DITUDRA2_DITUDRA2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRA3 register. -// -//****************************************************************************** -#define MCASP_DITUDRA3_DITUDRA3_M \ - 0xFFFFFFFF // Left (Even TDM slot ) User Data - -#define MCASP_DITUDRA3_DITUDRA3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRA4 register. -// -//****************************************************************************** -#define MCASP_DITUDRA4_DITUDRA4_M \ - 0xFFFFFFFF // Left (Even TDM slot ) User Data - -#define MCASP_DITUDRA4_DITUDRA4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRA5 register. -// -//****************************************************************************** -#define MCASP_DITUDRA5_DITUDRA5_M \ - 0xFFFFFFFF // Left (Even TDM slot ) User Data - -#define MCASP_DITUDRA5_DITUDRA5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRB0 register. -// -//****************************************************************************** -#define MCASP_DITUDRB0_DITUDRB0_M \ - 0xFFFFFFFF // Right (odd TDM slot ) User Data - -#define MCASP_DITUDRB0_DITUDRB0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRB1 register. -// -//****************************************************************************** -#define MCASP_DITUDRB1_DITUDRB1_M \ - 0xFFFFFFFF // Right (odd TDM slot ) User Data - -#define MCASP_DITUDRB1_DITUDRB1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRB2 register. -// -//****************************************************************************** -#define MCASP_DITUDRB2_DITUDRB2_M \ - 0xFFFFFFFF // Right (odd TDM slot ) User Data - -#define MCASP_DITUDRB2_DITUDRB2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRB3 register. -// -//****************************************************************************** -#define MCASP_DITUDRB3_DITUDRB3_M \ - 0xFFFFFFFF // Right (odd TDM slot ) User Data - -#define MCASP_DITUDRB3_DITUDRB3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRB4 register. -// -//****************************************************************************** -#define MCASP_DITUDRB4_DITUDRB4_M \ - 0xFFFFFFFF // Right (odd TDM slot ) User Data - -#define MCASP_DITUDRB4_DITUDRB4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_DITUDRB5 register. -// -//****************************************************************************** -#define MCASP_DITUDRB5_DITUDRB5_M \ - 0xFFFFFFFF // Right (odd TDM slot ) User Data - -#define MCASP_DITUDRB5_DITUDRB5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL0 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL0_RRDY 0x00000020 -#define MCASP_XRSRCTL0_XRDY 0x00000010 -#define MCASP_XRSRCTL0_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL0_DISMOD_S 2 -#define MCASP_XRSRCTL0_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL0_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL1 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL1_RRDY 0x00000020 -#define MCASP_XRSRCTL1_XRDY 0x00000010 -#define MCASP_XRSRCTL1_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL1_DISMOD_S 2 -#define MCASP_XRSRCTL1_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL1_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL2 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL2_RRDY 0x00000020 -#define MCASP_XRSRCTL2_XRDY 0x00000010 -#define MCASP_XRSRCTL2_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL2_DISMOD_S 2 -#define MCASP_XRSRCTL2_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL2_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL3 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL3_RRDY 0x00000020 -#define MCASP_XRSRCTL3_XRDY 0x00000010 -#define MCASP_XRSRCTL3_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL3_DISMOD_S 2 -#define MCASP_XRSRCTL3_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL3_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL4 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL4_RRDY 0x00000020 -#define MCASP_XRSRCTL4_XRDY 0x00000010 -#define MCASP_XRSRCTL4_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL4_DISMOD_S 2 -#define MCASP_XRSRCTL4_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL4_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL5 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL5_RRDY 0x00000020 -#define MCASP_XRSRCTL5_XRDY 0x00000010 -#define MCASP_XRSRCTL5_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL5_DISMOD_S 2 -#define MCASP_XRSRCTL5_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL5_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL6 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL6_RRDY 0x00000020 -#define MCASP_XRSRCTL6_XRDY 0x00000010 -#define MCASP_XRSRCTL6_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL6_DISMOD_S 2 -#define MCASP_XRSRCTL6_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL6_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL7 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL7_RRDY 0x00000020 -#define MCASP_XRSRCTL7_XRDY 0x00000010 -#define MCASP_XRSRCTL7_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL7_DISMOD_S 2 -#define MCASP_XRSRCTL7_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL7_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL8 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL8_RRDY 0x00000020 -#define MCASP_XRSRCTL8_XRDY 0x00000010 -#define MCASP_XRSRCTL8_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL8_DISMOD_S 2 -#define MCASP_XRSRCTL8_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL8_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL9 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL9_RRDY 0x00000020 -#define MCASP_XRSRCTL9_XRDY 0x00000010 -#define MCASP_XRSRCTL9_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high -#define MCASP_XRSRCTL9_DISMOD_S 2 -#define MCASP_XRSRCTL9_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL9_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL10 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL10_RRDY 0x00000020 -#define MCASP_XRSRCTL10_XRDY 0x00000010 -#define MCASP_XRSRCTL10_DISMOD_M \ - 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high - -#define MCASP_XRSRCTL10_DISMOD_S 2 -#define MCASP_XRSRCTL10_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL10_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL11 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL11_RRDY 0x00000020 -#define MCASP_XRSRCTL11_XRDY 0x00000010 -#define MCASP_XRSRCTL11_DISMOD_M \ - 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high - -#define MCASP_XRSRCTL11_DISMOD_S 2 -#define MCASP_XRSRCTL11_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL11_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL12 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL12_RRDY 0x00000020 -#define MCASP_XRSRCTL12_XRDY 0x00000010 -#define MCASP_XRSRCTL12_DISMOD_M \ - 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high - -#define MCASP_XRSRCTL12_DISMOD_S 2 -#define MCASP_XRSRCTL12_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL12_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL13 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL13_RRDY 0x00000020 -#define MCASP_XRSRCTL13_XRDY 0x00000010 -#define MCASP_XRSRCTL13_DISMOD_M \ - 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high - -#define MCASP_XRSRCTL13_DISMOD_S 2 -#define MCASP_XRSRCTL13_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL13_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL14 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL14_RRDY 0x00000020 -#define MCASP_XRSRCTL14_XRDY 0x00000010 -#define MCASP_XRSRCTL14_DISMOD_M \ - 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high - -#define MCASP_XRSRCTL14_DISMOD_S 2 -#define MCASP_XRSRCTL14_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL14_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_XRSRCTL15 register. -// -//****************************************************************************** -#define MCASP_XRSRCTL15_RRDY 0x00000020 -#define MCASP_XRSRCTL15_XRDY 0x00000010 -#define MCASP_XRSRCTL15_DISMOD_M \ - 0x0000000C // Serializer drive state 0x0 Tri - // state 0x1 Reserved 0x2 Drive pin - // low 0x3 Drive pin high - -#define MCASP_XRSRCTL15_DISMOD_S 2 -#define MCASP_XRSRCTL15_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive - // mode 0x1 Transmit mode 0x2 - // Receive mode -#define MCASP_XRSRCTL15_SRMOD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF0 register. -// -//****************************************************************************** -#define MCASP_TXBUF0_XBUF0_M 0xFFFFFFFF // Transmit Buffer 0 -#define MCASP_TXBUF0_XBUF0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF1 register. -// -//****************************************************************************** -#define MCASP_TXBUF1_XBUF1_M 0xFFFFFFFF // Transmit Buffer 1 -#define MCASP_TXBUF1_XBUF1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF2 register. -// -//****************************************************************************** -#define MCASP_TXBUF2_XBUF2_M 0xFFFFFFFF // Transmit Buffer 2 -#define MCASP_TXBUF2_XBUF2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF3 register. -// -//****************************************************************************** -#define MCASP_TXBUF3_XBUF3_M 0xFFFFFFFF // Transmit Buffer 3 -#define MCASP_TXBUF3_XBUF3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF4 register. -// -//****************************************************************************** -#define MCASP_TXBUF4_XBUF4_M 0xFFFFFFFF // Transmit Buffer 4 -#define MCASP_TXBUF4_XBUF4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF5 register. -// -//****************************************************************************** -#define MCASP_TXBUF5_XBUF5_M 0xFFFFFFFF // Transmit Buffer 5 -#define MCASP_TXBUF5_XBUF5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF6 register. -// -//****************************************************************************** -#define MCASP_TXBUF6_XBUF6_M 0xFFFFFFFF // Transmit Buffer 6 -#define MCASP_TXBUF6_XBUF6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF7 register. -// -//****************************************************************************** -#define MCASP_TXBUF7_XBUF7_M 0xFFFFFFFF // Transmit Buffer 7 -#define MCASP_TXBUF7_XBUF7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF8 register. -// -//****************************************************************************** -#define MCASP_TXBUF8_XBUF8_M 0xFFFFFFFF // Transmit Buffer 8 -#define MCASP_TXBUF8_XBUF8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF9 register. -// -//****************************************************************************** -#define MCASP_TXBUF9_XBUF9_M 0xFFFFFFFF // Transmit Buffer 9 -#define MCASP_TXBUF9_XBUF9_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF10 register. -// -//****************************************************************************** -#define MCASP_TXBUF10_XBUF10_M 0xFFFFFFFF // Transmit Buffer 10 -#define MCASP_TXBUF10_XBUF10_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF11 register. -// -//****************************************************************************** -#define MCASP_TXBUF11_XBUF11_M 0xFFFFFFFF // Transmit Buffer 11 -#define MCASP_TXBUF11_XBUF11_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF12 register. -// -//****************************************************************************** -#define MCASP_TXBUF12_XBUF12_M 0xFFFFFFFF // Transmit Buffer 12 -#define MCASP_TXBUF12_XBUF12_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF13 register. -// -//****************************************************************************** -#define MCASP_TXBUF13_XBUF13_M 0xFFFFFFFF // Transmit Buffer 13 -#define MCASP_TXBUF13_XBUF13_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF14 register. -// -//****************************************************************************** -#define MCASP_TXBUF14_XBUF14_M 0xFFFFFFFF // Transmit Buffer 14 -#define MCASP_TXBUF14_XBUF14_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_TXBUF15 register. -// -//****************************************************************************** -#define MCASP_TXBUF15_XBUF15_M 0xFFFFFFFF // Transmit Buffer 15 -#define MCASP_TXBUF15_XBUF15_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF0 register. -// -//****************************************************************************** -#define MCASP_RXBUF0_RBUF0_M 0xFFFFFFFF // Receive Buffer 0 -#define MCASP_RXBUF0_RBUF0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF1 register. -// -//****************************************************************************** -#define MCASP_RXBUF1_RBUF1_M 0xFFFFFFFF // Receive Buffer 1 -#define MCASP_RXBUF1_RBUF1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF2 register. -// -//****************************************************************************** -#define MCASP_RXBUF2_RBUF2_M 0xFFFFFFFF // Receive Buffer 2 -#define MCASP_RXBUF2_RBUF2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF3 register. -// -//****************************************************************************** -#define MCASP_RXBUF3_RBUF3_M 0xFFFFFFFF // Receive Buffer 3 -#define MCASP_RXBUF3_RBUF3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF4 register. -// -//****************************************************************************** -#define MCASP_RXBUF4_RBUF4_M 0xFFFFFFFF // Receive Buffer 4 -#define MCASP_RXBUF4_RBUF4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF5 register. -// -//****************************************************************************** -#define MCASP_RXBUF5_RBUF5_M 0xFFFFFFFF // Receive Buffer 5 -#define MCASP_RXBUF5_RBUF5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF6 register. -// -//****************************************************************************** -#define MCASP_RXBUF6_RBUF6_M 0xFFFFFFFF // Receive Buffer 6 -#define MCASP_RXBUF6_RBUF6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF7 register. -// -//****************************************************************************** -#define MCASP_RXBUF7_RBUF7_M 0xFFFFFFFF // Receive Buffer 7 -#define MCASP_RXBUF7_RBUF7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF8 register. -// -//****************************************************************************** -#define MCASP_RXBUF8_RBUF8_M 0xFFFFFFFF // Receive Buffer 8 -#define MCASP_RXBUF8_RBUF8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF9 register. -// -//****************************************************************************** -#define MCASP_RXBUF9_RBUF9_M 0xFFFFFFFF // Receive Buffer 9 -#define MCASP_RXBUF9_RBUF9_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF10 register. -// -//****************************************************************************** -#define MCASP_RXBUF10_RBUF10_M 0xFFFFFFFF // Receive Buffer 10 -#define MCASP_RXBUF10_RBUF10_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF11 register. -// -//****************************************************************************** -#define MCASP_RXBUF11_RBUF11_M 0xFFFFFFFF // Receive Buffer 11 -#define MCASP_RXBUF11_RBUF11_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF12 register. -// -//****************************************************************************** -#define MCASP_RXBUF12_RBUF12_M 0xFFFFFFFF // Receive Buffer 12 -#define MCASP_RXBUF12_RBUF12_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF13 register. -// -//****************************************************************************** -#define MCASP_RXBUF13_RBUF13_M 0xFFFFFFFF // Receive Buffer 13 -#define MCASP_RXBUF13_RBUF13_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF14 register. -// -//****************************************************************************** -#define MCASP_RXBUF14_RBUF14_M 0xFFFFFFFF // Receive Buffer 14 -#define MCASP_RXBUF14_RBUF14_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCASP_O_RXBUF15 register. -// -//****************************************************************************** -#define MCASP_RXBUF15_RBUF15_M 0xFFFFFFFF // Receive Buffer 15 -#define MCASP_RXBUF15_RBUF15_S 0 - - - -#endif // __HW_MCASP_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_mcspi.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_mcspi.h deleted file mode 100644 index aeddbc2e740..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_mcspi.h +++ /dev/null @@ -1,1743 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_MCSPI_H__ -#define __HW_MCSPI_H__ - -//***************************************************************************** -// -// The following are defines for the MCSPI register offsets. -// -//***************************************************************************** -#define MCSPI_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) - // Used by software to track - // features bugs and compatibility -#define MCSPI_O_HL_HWINFO 0x00000004 // Information about the IP - // module's hardware configuration - // i.e. typically the module's HDL - // generics (if any). Actual field - // format and encoding is up to the - // module's designer to decide. -#define MCSPI_O_HL_SYSCONFIG 0x00000010 // 0x4402 1010 0x4402 2010 Clock - // management configuration -#define MCSPI_O_REVISION 0x00000100 // 0x4402 1100 0x4402 2100 This - // register contains the hard coded - // RTL revision number. -#define MCSPI_O_SYSCONFIG 0x00000110 // 0x4402 1110 0x4402 2110 This - // register allows controlling - // various parameters of the OCP - // interface. -#define MCSPI_O_SYSSTATUS 0x00000114 // 0x4402 1114 0x4402 2114 This - // register provides status - // information about the module - // excluding the interrupt status - // information -#define MCSPI_O_IRQSTATUS 0x00000118 // 0x4402 1118 0x4402 2118 The - // interrupt status regroups all the - // status of the module internal - // events that can generate an - // interrupt -#define MCSPI_O_IRQENABLE 0x0000011C // 0x4402 111C 0x4402 211C This - // register allows to enable/disable - // the module internal sources of - // interrupt on an event-by-event - // basis. -#define MCSPI_O_WAKEUPENABLE 0x00000120 // 0x4402 1120 0x4402 2120 The - // wakeup enable register allows to - // enable/disable the module - // internal sources of wakeup on - // event-by-event basis. -#define MCSPI_O_SYST 0x00000124 // 0x4402 1124 0x4402 2124 This - // register is used to check the - // correctness of the system - // interconnect either internally to - // peripheral bus or externally to - // device IO pads when the module is - // configured in system test - // (SYSTEST) mode. -#define MCSPI_O_MODULCTRL 0x00000128 // 0x4402 1128 0x4402 2128 This - // register is dedicated to the - // configuration of the serial port - // interface. -#define MCSPI_O_CH0CONF 0x0000012C // 0x4402 112C 0x4402 212C This - // register is dedicated to the - // configuration of the channel 0 -#define MCSPI_O_CH0STAT 0x00000130 // 0x4402 1130 0x4402 2130 This - // register provides status - // information about transmitter and - // receiver registers of channel 0 -#define MCSPI_O_CH0CTRL 0x00000134 // 0x4402 1134 0x4402 2134 This - // register is dedicated to enable - // the channel 0 -#define MCSPI_O_TX0 0x00000138 // 0x4402 1138 0x4402 2138 This - // register contains a single SPI - // word to transmit on the serial - // link what ever SPI word length - // is. -#define MCSPI_O_RX0 0x0000013C // 0x4402 113C 0x4402 213C This - // register contains a single SPI - // word received through the serial - // link what ever SPI word length - // is. -#define MCSPI_O_CH1CONF 0x00000140 // 0x4402 1140 0x4402 2140 This - // register is dedicated to the - // configuration of the channel. -#define MCSPI_O_CH1STAT 0x00000144 // 0x4402 1144 0x4402 2144 This - // register provides status - // information about transmitter and - // receiver registers of channel 1 -#define MCSPI_O_CH1CTRL 0x00000148 // 0x4402 1148 0x4402 2148 This - // register is dedicated to enable - // the channel 1 -#define MCSPI_O_TX1 0x0000014C // 0x4402 114C 0x4402 214C This - // register contains a single SPI - // word to transmit on the serial - // link what ever SPI word length - // is. -#define MCSPI_O_RX1 0x00000150 // 0x4402 1150 0x4402 2150 This - // register contains a single SPI - // word received through the serial - // link what ever SPI word length - // is. -#define MCSPI_O_CH2CONF 0x00000154 // 0x4402 1154 0x4402 2154 This - // register is dedicated to the - // configuration of the channel 2 -#define MCSPI_O_CH2STAT 0x00000158 // 0x4402 1158 0x4402 2158 This - // register provides status - // information about transmitter and - // receiver registers of channel 2 -#define MCSPI_O_CH2CTRL 0x0000015C // 0x4402 115C 0x4402 215C This - // register is dedicated to enable - // the channel 2 -#define MCSPI_O_TX2 0x00000160 // 0x4402 1160 0x4402 2160 This - // register contains a single SPI - // word to transmit on the serial - // link what ever SPI word length - // is. -#define MCSPI_O_RX2 0x00000164 // 0x4402 1164 0x4402 2164 This - // register contains a single SPI - // word received through the serial - // link what ever SPI word length - // is. -#define MCSPI_O_CH3CONF 0x00000168 // 0x4402 1168 0x4402 2168 This - // register is dedicated to the - // configuration of the channel 3 -#define MCSPI_O_CH3STAT 0x0000016C // 0x4402 116C 0x4402 216C This - // register provides status - // information about transmitter and - // receiver registers of channel 3 -#define MCSPI_O_CH3CTRL 0x00000170 // 0x4402 1170 0x4402 2170 This - // register is dedicated to enable - // the channel 3 -#define MCSPI_O_TX3 0x00000174 // 0x4402 1174 0x4402 2174 This - // register contains a single SPI - // word to transmit on the serial - // link what ever SPI word length - // is. -#define MCSPI_O_RX3 0x00000178 // 0x4402 1178 0x4402 2178 This - // register contains a single SPI - // word received through the serial - // link what ever SPI word length - // is. -#define MCSPI_O_XFERLEVEL 0x0000017C // 0x4402 117C 0x4402 217C This - // register provides transfer levels - // needed while using FIFO buffer - // during transfer. -#define MCSPI_O_DAFTX 0x00000180 // 0x4402 1180 0x4402 2180 This - // register contains the SPI words - // to transmit on the serial link - // when FIFO used and DMA address is - // aligned on 256 bit.This register - // is an image of one of MCSPI_TX(i) - // register corresponding to the - // channel which have its FIFO - // enabled. -#define MCSPI_O_DAFRX 0x000001A0 // 0x4402 11A0 0x4402 21A0 This - // register contains the SPI words - // to received on the serial link - // when FIFO used and DMA address is - // aligned on 256 bit.This register - // is an image of one of MCSPI_RX(i) - // register corresponding to the - // channel which have its FIFO - // enabled. - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_HL_REV register. -// -//****************************************************************************** -#define MCSPI_HL_REV_SCHEME_M 0xC0000000 -#define MCSPI_HL_REV_SCHEME_S 30 -#define MCSPI_HL_REV_RSVD_M 0x30000000 // Reserved These bits are - // initialized to zero and writes to - // them are ignored. -#define MCSPI_HL_REV_RSVD_S 28 -#define MCSPI_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software - // compatible module family. If - // there is no level of software - // compatibility a new Func number - // (and hence REVISION) should be - // assigned. -#define MCSPI_HL_REV_FUNC_S 16 -#define MCSPI_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP - // design owner. RTL follows a - // numbering such as X.Y.R.Z which - // are explained in this table. R - // changes ONLY when: (1) PDS - // uploads occur which may have been - // due to spec changes (2) Bug fixes - // occur (3) Resets to '0' when X or - // Y changes. Design team has an - // internal 'Z' (customer invisible) - // number which increments on every - // drop that happens due to DV and - // RTL updates. Z resets to 0 when R - // increments. -#define MCSPI_HL_REV_R_RTL_S 11 -#define MCSPI_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by - // IP specification owner. X changes - // ONLY when: (1) There is a major - // feature addition. An example - // would be adding Master Mode to - // Utopia Level2. The Func field (or - // Class/Type in old PID format) - // will remain the same. X does NOT - // change due to: (1) Bug fixes (2) - // Change in feature parameters. -#define MCSPI_HL_REV_X_MAJOR_S 8 -#define MCSPI_HL_REV_CUSTOM_M 0x000000C0 -#define MCSPI_HL_REV_CUSTOM_S 6 -#define MCSPI_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by - // IP specification owner. Y changes - // ONLY when: (1) Features are - // scaled (up or down). Flexibility - // exists in that this feature - // scalability may either be - // represented in the Y change or a - // specific register in the IP that - // indicates which features are - // exactly available. (2) When - // feature creeps from Is-Not list - // to Is list. But this may not be - // the case once it sees silicon; in - // which case X will change. Y does - // NOT change due to: (1) Bug fixes - // (2) Typos or clarifications (3) - // major functional/feature - // change/addition/deletion. Instead - // these changes may be reflected - // via R S X as applicable. Spec - // owner maintains a - // customer-invisible number 'S' - // which changes due to: (1) - // Typos/clarifications (2) Bug - // documentation. Note that this bug - // is not due to a spec change but - // due to implementation. - // Nevertheless the spec tracks the - // IP bugs. An RTL release (say for - // silicon PG1.1) that occurs due to - // bug fix should document the - // corresponding spec number (X.Y.S) - // in its release notes. -#define MCSPI_HL_REV_Y_MINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_HL_HWINFO register. -// -//****************************************************************************** -#define MCSPI_HL_HWINFO_RETMODE 0x00000040 -#define MCSPI_HL_HWINFO_FFNBYTE_M \ - 0x0000003E - -#define MCSPI_HL_HWINFO_FFNBYTE_S 1 -#define MCSPI_HL_HWINFO_USEFIFO 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// MCSPI_O_HL_SYSCONFIG register. -// -//****************************************************************************** -#define MCSPI_HL_SYSCONFIG_IDLEMODE_M \ - 0x0000000C // Configuration of the local - // target state management mode. By - // definition target can handle - // read/write transaction as long as - // it is out of IDLE state. 0x0 - // Force-idle mode: local target's - // idle state follows (acknowledges) - // the system's idle requests - // unconditionally i.e. regardless - // of the IP module's internal - // requirements.Backup mode for - // debug only. 0x1 No-idle mode: - // local target never enters idle - // state.Backup mode for debug only. - // 0x2 Smart-idle mode: local - // target's idle state eventually - // follows (acknowledges) the - // system's idle requests depending - // on the IP module's internal - // requirements.IP module shall not - // generate (IRQ- or - // DMA-request-related) wakeup - // events. 0x3 "Smart-idle - // wakeup-capable mode: local - // target's idle state eventually - // follows (acknowledges) the - // system's idle requests depending - // on the IP module's internal - // requirements.IP module may - // generate (IRQ- or - // DMA-request-related) wakeup - // events when in idle state.Mode is - // only relevant if the appropriate - // IP module ""swakeup"" output(s) - // is (are) implemented." - -#define MCSPI_HL_SYSCONFIG_IDLEMODE_S 2 -#define MCSPI_HL_SYSCONFIG_FREEEMU \ - 0x00000002 // Sensitivity to emulation (debug) - // suspend input signal. 0 IP module - // is sensitive to emulation suspend - // 1 IP module is not sensitive to - // emulation suspend - -#define MCSPI_HL_SYSCONFIG_SOFTRESET \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_REVISION register. -// -//****************************************************************************** -#define MCSPI_REVISION_REV_M 0x000000FF // IP revision [7:4] Major revision - // [3:0] Minor revision Examples: - // 0x10 for 1.0 0x21 for 2.1 -#define MCSPI_REVISION_REV_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_SYSCONFIG register. -// -//****************************************************************************** -#define MCSPI_SYSCONFIG_CLOCKACTIVITY_M \ - 0x00000300 // Clocks activity during wake up - // mode period 0x0 OCP and - // Functional clocks may be switched - // off. 0x1 OCP clock is maintained. - // Functional clock may be - // switched-off. 0x2 Functional - // clock is maintained. OCP clock - // may be switched-off. 0x3 OCP and - // Functional clocks are maintained. - -#define MCSPI_SYSCONFIG_CLOCKACTIVITY_S 8 -#define MCSPI_SYSCONFIG_SIDLEMODE_M \ - 0x00000018 // Power management 0x0 If an idle - // request is detected the McSPI - // acknowledges it unconditionally - // and goes in Inactive mode. - // Interrupt DMA requests and wake - // up lines are unconditionally - // de-asserted and the module wakeup - // capability is deactivated even if - // the bit - // MCSPI_SYSCONFIG[EnaWakeUp] is - // set. 0x1 If an idle request is - // detected the request is ignored - // and the module does not switch to - // wake up mode and keeps on - // behaving normally. 0x2 If an idle - // request is detected the module - // will switch to idle mode based on - // its internal activity. The wake - // up capability cannot be used. 0x3 - // If an idle request is detected - // the module will switch to idle - // mode based on its internal - // activity and the wake up - // capability can be used if the bit - // MCSPI_SYSCONFIG[EnaWakeUp] is - // set. - -#define MCSPI_SYSCONFIG_SIDLEMODE_S 3 -#define MCSPI_SYSCONFIG_ENAWAKEUP \ - 0x00000004 // WakeUp feature control 0 WakeUp - // capability is disabled 1 WakeUp - // capability is enabled - -#define MCSPI_SYSCONFIG_SOFTRESET \ - 0x00000002 // Software reset. During reads it - // always returns 0. 0 (write) - // Normal mode 1 (write) Set this - // bit to 1 to trigger a module - // reset.The bit is automatically - // reset by the hardware. - -#define MCSPI_SYSCONFIG_AUTOIDLE \ - 0x00000001 // Internal OCP Clock gating - // strategy 0 OCP clock is - // free-running 1 Automatic OCP - // clock gating strategy is applied - // based on the OCP interface - // activity - -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_SYSSTATUS register. -// -//****************************************************************************** -#define MCSPI_SYSSTATUS_RESETDONE \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_IRQSTATUS register. -// -//****************************************************************************** -#define MCSPI_IRQSTATUS_EOW 0x00020000 -#define MCSPI_IRQSTATUS_WKS 0x00010000 -#define MCSPI_IRQSTATUS_RX3_FULL \ - 0x00004000 - -#define MCSPI_IRQSTATUS_TX3_UNDERFLOW \ - 0x00002000 - -#define MCSPI_IRQSTATUS_TX3_EMPTY \ - 0x00001000 - -#define MCSPI_IRQSTATUS_RX2_FULL \ - 0x00000400 - -#define MCSPI_IRQSTATUS_TX2_UNDERFLOW \ - 0x00000200 - -#define MCSPI_IRQSTATUS_TX2_EMPTY \ - 0x00000100 - -#define MCSPI_IRQSTATUS_RX1_FULL \ - 0x00000040 - -#define MCSPI_IRQSTATUS_TX1_UNDERFLOW \ - 0x00000020 - -#define MCSPI_IRQSTATUS_TX1_EMPTY \ - 0x00000010 - -#define MCSPI_IRQSTATUS_RX0_OVERFLOW \ - 0x00000008 - -#define MCSPI_IRQSTATUS_RX0_FULL \ - 0x00000004 - -#define MCSPI_IRQSTATUS_TX0_UNDERFLOW \ - 0x00000002 - -#define MCSPI_IRQSTATUS_TX0_EMPTY \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_IRQENABLE register. -// -//****************************************************************************** -#define MCSPI_IRQENABLE_EOW_ENABLE \ - 0x00020000 // End of Word count Interrupt - // Enable. 0 Interrupt disabled 1 - // Interrupt enabled - -#define MCSPI_IRQENABLE_WKE 0x00010000 // Wake Up event interrupt Enable - // in slave mode when an active - // control signal is detected on the - // SPIEN line programmed in the - // field MCSPI_CH0CONF[SPIENSLV] 0 - // Interrupt disabled 1 Interrupt - // enabled -#define MCSPI_IRQENABLE_RX3_FULL_ENABLE \ - 0x00004000 // Receiver register Full Interrupt - // Enable. Ch 3 0 Interrupt disabled - // 1 Interrupt enabled - -#define MCSPI_IRQENABLE_TX3_UNDERFLOW_ENABLE \ - 0x00002000 // Transmitter register Underflow - // Interrupt Enable. Ch 3 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_TX3_EMPTY_ENABLE \ - 0x00001000 // Transmitter register Empty - // Interrupt Enable. Ch3 0 Interrupt - // disabled 1 Interrupt enabled - -#define MCSPI_IRQENABLE_RX2_FULL_ENABLE \ - 0x00000400 // Receiver register Full Interrupt - // Enable. Ch 2 0 Interrupt disabled - // 1 Interrupt enabled - -#define MCSPI_IRQENABLE_TX2_UNDERFLOW_ENABLE \ - 0x00000200 // Transmitter register Underflow - // Interrupt Enable. Ch 2 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_TX2_EMPTY_ENABLE \ - 0x00000100 // Transmitter register Empty - // Interrupt Enable. Ch 2 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_RX1_FULL_ENABLE \ - 0x00000040 // Receiver register Full Interrupt - // Enable. Ch 1 0 Interrupt disabled - // 1 Interrupt enabled - -#define MCSPI_IRQENABLE_TX1_UNDERFLOW_ENABLE \ - 0x00000020 // Transmitter register Underflow - // Interrupt Enable. Ch 1 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_TX1_EMPTY_ENABLE \ - 0x00000010 // Transmitter register Empty - // Interrupt Enable. Ch 1 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_RX0_OVERFLOW_ENABLE \ - 0x00000008 // Receiver register Overflow - // Interrupt Enable. Ch 0 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_RX0_FULL_ENABLE \ - 0x00000004 // Receiver register Full Interrupt - // Enable. Ch 0 0 Interrupt disabled - // 1 Interrupt enabled - -#define MCSPI_IRQENABLE_TX0_UNDERFLOW_ENABLE \ - 0x00000002 // Transmitter register Underflow - // Interrupt Enable. Ch 0 0 - // Interrupt disabled 1 Interrupt - // enabled - -#define MCSPI_IRQENABLE_TX0_EMPTY_ENABLE \ - 0x00000001 // Transmitter register Empty - // Interrupt Enable. Ch 0 0 - // Interrupt disabled 1 Interrupt - // enabled - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// MCSPI_O_WAKEUPENABLE register. -// -//****************************************************************************** -#define MCSPI_WAKEUPENABLE_WKEN 0x00000001 // WakeUp functionality in slave - // mode when an active control - // signal is detected on the SPIEN - // line programmed in the field - // MCSPI_CH0CONF[SPIENSLV] 0 The - // event is not allowed to wakeup - // the system even if the global - // control bit - // MCSPI_SYSCONF[EnaWakeUp] is set. - // 1 The event is allowed to wakeup - // the system if the global control - // bit MCSPI_SYSCONF[EnaWakeUp] is - // set. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_SYST register. -// -//****************************************************************************** -#define MCSPI_SYST_SSB 0x00000800 // Set status bit 0 No action. - // Writing 0 does not clear already - // set status bits; This bit must be - // cleared prior attempting to clear - // a status bit of the - // register. 1 - // Force to 1 all status bits of - // MCSPI_IRQSTATUS register. Writing - // 1 into this bit sets to 1 all - // status bits contained in the - // register. -#define MCSPI_SYST_SPIENDIR 0x00000400 // Set the direction of the - // SPIEN[3:0] lines and SPICLK line - // 0 output (as in master mode) 1 - // input (as in slave mode) -#define MCSPI_SYST_SPIDATDIR1 0x00000200 // Set the direction of the - // SPIDAT[1] 0 output 1 input -#define MCSPI_SYST_SPIDATDIR0 0x00000100 // Set the direction of the - // SPIDAT[0] 0 output 1 input -#define MCSPI_SYST_WAKD 0x00000080 // SWAKEUP output (signal data - // value of internal signal to - // system). The signal is driven - // high or low according to the - // value written into this register - // bit. 0 The pin is driven low. 1 - // The pin is driven high. -#define MCSPI_SYST_SPICLK 0x00000040 // SPICLK line (signal data value) - // If MCSPI_SYST[SPIENDIR] = 1 - // (input mode direction) this bit - // returns the value on the CLKSPI - // line (high or low) and a write - // into this bit has no effect. If - // MCSPI_SYST[SPIENDIR] = 0 (output - // mode direction) the CLKSPI line - // is driven high or low according - // to the value written into this - // register. -#define MCSPI_SYST_SPIDAT_1 0x00000020 // SPIDAT[1] line (signal data - // value) If MCSPI_SYST[SPIDATDIR1] - // = 0 (output mode direction) the - // SPIDAT[1] line is driven high or - // low according to the value - // written into this register. If - // MCSPI_SYST[SPIDATDIR1] = 1 (input - // mode direction) this bit returns - // the value on the SPIDAT[1] line - // (high or low) and a write into - // this bit has no effect. -#define MCSPI_SYST_SPIDAT_0 0x00000010 // SPIDAT[0] line (signal data - // value) If MCSPI_SYST[SPIDATDIR0] - // = 0 (output mode direction) the - // SPIDAT[0] line is driven high or - // low according to the value - // written into this register. If - // MCSPI_SYST[SPIDATDIR0] = 1 (input - // mode direction) this bit returns - // the value on the SPIDAT[0] line - // (high or low) and a write into - // this bit has no effect. -#define MCSPI_SYST_SPIEN_3 0x00000008 // SPIEN[3] line (signal data - // value) If MCSPI_SYST[SPIENDIR] = - // 0 (output mode direction) the - // SPIENT[3] line is driven high or - // low according to the value - // written into this register. If - // MCSPI_SYST[SPIENDIR] = 1 (input - // mode direction) this bit returns - // the value on the SPIEN[3] line - // (high or low) and a write into - // this bit has no effect. -#define MCSPI_SYST_SPIEN_2 0x00000004 // SPIEN[2] line (signal data - // value) If MCSPI_SYST[SPIENDIR] = - // 0 (output mode direction) the - // SPIENT[2] line is driven high or - // low according to the value - // written into this register. If - // MCSPI_SYST[SPIENDIR] = 1 (input - // mode direction) this bit returns - // the value on the SPIEN[2] line - // (high or low) and a write into - // this bit has no effect. -#define MCSPI_SYST_SPIEN_1 0x00000002 // SPIEN[1] line (signal data - // value) If MCSPI_SYST[SPIENDIR] = - // 0 (output mode direction) the - // SPIENT[1] line is driven high or - // low according to the value - // written into this register. If - // MCSPI_SYST[SPIENDIR] = 1 (input - // mode direction) this bit returns - // the value on the SPIEN[1] line - // (high or low) and a write into - // this bit has no effect. -#define MCSPI_SYST_SPIEN_0 0x00000001 // SPIEN[0] line (signal data - // value) If MCSPI_SYST[SPIENDIR] = - // 0 (output mode direction) the - // SPIENT[0] line is driven high or - // low according to the value - // written into this register. If - // MCSPI_SYST[SPIENDIR] = 1 (input - // mode direction) this bit returns - // the value on the SPIEN[0] line - // (high or low) and a write into - // this bit has no effect. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_MODULCTRL register. -// -//****************************************************************************** -#define MCSPI_MODULCTRL_FDAA 0x00000100 // FIFO DMA Address 256-bit aligned - // This register is used when a FIFO - // is managed by the module and DMA - // connected to the controller - // provides only 256 bit aligned - // address. If this bit is set the - // enabled channel which uses the - // FIFO has its datas managed - // through MCSPI_DAFTX and - // MCSPI_DAFRX registers instead of - // MCSPI_TX(i) and MCSPI_RX(i) - // registers. 0 FIFO data managed by - // MCSPI_TX(i) and MCSPI_RX(i) - // registers. 1 FIFO data managed by - // MCSPI_DAFTX and MCSPI_DAFRX - // registers. -#define MCSPI_MODULCTRL_MOA 0x00000080 // Multiple word ocp access: This - // register can only be used when a - // channel is enabled using a FIFO. - // It allows the system to perform - // multiple SPI word access for a - // single 32-bit OCP word access. - // This is possible for WL < 16. 0 - // Multiple word access disabled 1 - // Multiple word access enabled with - // FIFO -#define MCSPI_MODULCTRL_INITDLY_M \ - 0x00000070 // Initial spi delay for first - // transfer: This register is an - // option only available in SINGLE - // master mode The controller waits - // for a delay to transmit the first - // spi word after channel enabled - // and corresponding TX register - // filled. This Delay is based on - // SPI output frequency clock No - // clock output provided to the - // boundary and chip select is not - // active in 4 pin mode within this - // period. 0x0 No delay for first - // spi transfer. 0x1 The controller - // wait 4 spi bus clock 0x2 The - // controller wait 8 spi bus clock - // 0x3 The controller wait 16 spi - // bus clock 0x4 The controller wait - // 32 spi bus clock - -#define MCSPI_MODULCTRL_INITDLY_S 4 -#define MCSPI_MODULCTRL_SYSTEM_TEST \ - 0x00000008 // Enables the system test mode 0 - // Functional mode 1 System test - // mode (SYSTEST) - -#define MCSPI_MODULCTRL_MS 0x00000004 // Master/ Slave 0 Master - The - // module generates the SPICLK and - // SPIEN[3:0] 1 Slave - The module - // receives the SPICLK and - // SPIEN[3:0] -#define MCSPI_MODULCTRL_PIN34 0x00000002 // Pin mode selection: This - // register is used to configure the - // SPI pin mode in master or slave - // mode. If asserted the controller - // only use SIMOSOMI and SPICLK - // clock pin for spi transfers. 0 - // SPIEN is used as a chip select. 1 - // SPIEN is not used.In this mode - // all related option to chip select - // have no meaning. -#define MCSPI_MODULCTRL_SINGLE 0x00000001 // Single channel / Multi Channel - // (master mode only) 0 More than - // one channel will be used in - // master mode. 1 Only one channel - // will be used in master mode. This - // bit must be set in Force SPIEN - // mode. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH0CONF register. -// -//****************************************************************************** -#define MCSPI_CH0CONF_CLKG 0x20000000 // Clock divider granularity This - // register defines the granularity - // of channel clock divider: power - // of two or one clock cycle - // granularity. When this bit is set - // the register MCSPI_CHCTRL[EXTCLK] - // must be configured to reach a - // maximum of 4096 clock divider - // ratio. Then The clock divider - // ratio is a concatenation of - // MCSPI_CHCONF[CLKD] and - // MCSPI_CHCTRL[EXTCLK] values 0 - // Clock granularity of power of two - // 1 One clock cycle ganularity -#define MCSPI_CH0CONF_FFER 0x10000000 // FIFO enabled for receive:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to receive data. 1 The - // buffer is used to receive data. -#define MCSPI_CH0CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to transmit data. 1 The - // buffer is used to transmit data. -#define MCSPI_CH0CONF_TCS0_M 0x06000000 // Chip Select Time Control This - // 2-bits field defines the number - // of interface clock cycles between - // CS toggling and first or last - // edge of SPI clock. 0x0 0.5 clock - // cycle 0x1 1.5 clock cycle 0x2 2.5 - // clock cycle 0x3 3.5 clock cycle -#define MCSPI_CH0CONF_TCS0_S 25 -#define MCSPI_CH0CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit - // polarity is held to 0 during SPI - // transfer. 1 Start bit polarity is - // held to 1 during SPI transfer. -#define MCSPI_CH0CONF_SBE 0x00800000 // Start bit enable for SPI - // transfer 0 Default SPI transfer - // length as specified by WL bit - // field 1 Start bit D/CX added - // before SPI transfer polarity is - // defined by MCSPI_CH0CONF[SBPOL] -#define MCSPI_CH0CONF_SPIENSLV_M \ - 0x00600000 // Channel 0 only and slave mode - // only: SPI slave select signal - // detection. Reserved bits for - // other cases. 0x0 Detection - // enabled only on SPIEN[0] 0x1 - // Detection enabled only on - // SPIEN[1] 0x2 Detection enabled - // only on SPIEN[2] 0x3 Detection - // enabled only on SPIEN[3] - -#define MCSPI_CH0CONF_SPIENSLV_S 21 -#define MCSPI_CH0CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep - // SPIEN active between SPI words. - // (single channel master mode only) - // 0 Writing 0 into this bit drives - // low the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it high when - // MCSPI_CHCONF(i)[EPOL]=1. 1 - // Writing 1 into this bit drives - // high the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it low when - // MCSPI_CHCONF(i)[EPOL]=1 -#define MCSPI_CH0CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is - // deactivated (recommended for - // single SPI word transfer) 1 Turbo - // is activated to maximize the - // throughput for multi SPI words - // transfer. -#define MCSPI_CH0CONF_IS 0x00040000 // Input Select 0 Data Line0 - // (SPIDAT[0]) selected for - // reception. 1 Data Line1 - // (SPIDAT[1]) selected for - // reception -#define MCSPI_CH0CONF_DPE1 0x00020000 // Transmission Enable for data - // line 1 (SPIDATAGZEN[1]) 0 Data - // Line1 (SPIDAT[1]) selected for - // transmission 1 No transmission on - // Data Line1 (SPIDAT[1]) -#define MCSPI_CH0CONF_DPE0 0x00010000 // Transmission Enable for data - // line 0 (SPIDATAGZEN[0]) 0 Data - // Line0 (SPIDAT[0]) selected for - // transmission 1 No transmission on - // Data Line0 (SPIDAT[0]) -#define MCSPI_CH0CONF_DMAR 0x00008000 // DMA Read request The DMA Read - // request line is asserted when the - // channel is enabled and a new data - // is available in the receive - // register of the channel. The DMA - // Read request line is deasserted - // on read completion of the receive - // register of the channel. 0 DMA - // Read Request disabled 1 DMA Read - // Request enabled -#define MCSPI_CH0CONF_DMAW 0x00004000 // DMA Write request. The DMA Write - // request line is asserted when The - // channel is enabled and the - // transmitter register of the - // channel is empty. The DMA Write - // request line is deasserted on - // load completion of the - // transmitter register of the - // channel. 0 DMA Write Request - // disabled 1 DMA Write Request - // enabled -#define MCSPI_CH0CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 - // Transmit and Receive mode 0x1 - // Receive only mode 0x2 Transmit - // only mode 0x3 Reserved -#define MCSPI_CH0CONF_TRM_S 12 -#define MCSPI_CH0CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved - // 0x01 Reserved 0x02 Reserved 0x03 - // The SPI word is 4-bits long 0x04 - // The SPI word is 5-bits long 0x05 - // The SPI word is 6-bits long 0x06 - // The SPI word is 7-bits long 0x07 - // The SPI word is 8-bits long 0x08 - // The SPI word is 9-bits long 0x09 - // The SPI word is 10-bits long 0x0A - // The SPI word is 11-bits long 0x0B - // The SPI word is 12-bits long 0x0C - // The SPI word is 13-bits long 0x0D - // The SPI word is 14-bits long 0x0E - // The SPI word is 15-bits long 0x0F - // The SPI word is 16-bits long 0x10 - // The SPI word is 17-bits long 0x11 - // The SPI word is 18-bits long 0x12 - // The SPI word is 19-bits long 0x13 - // The SPI word is 20-bits long 0x14 - // The SPI word is 21-bits long 0x15 - // The SPI word is 22-bits long 0x16 - // The SPI word is 23-bits long 0x17 - // The SPI word is 24-bits long 0x18 - // The SPI word is 25-bits long 0x19 - // The SPI word is 26-bits long 0x1A - // The SPI word is 27-bits long 0x1B - // The SPI word is 28-bits long 0x1C - // The SPI word is 29-bits long 0x1D - // The SPI word is 30-bits long 0x1E - // The SPI word is 31-bits long 0x1F - // The SPI word is 32-bits long -#define MCSPI_CH0CONF_WL_S 7 -#define MCSPI_CH0CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held - // high during the active state. 1 - // SPIEN is held low during the - // active state. -#define MCSPI_CH0CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. - // (only when the module is a Master - // SPI device). A programmable clock - // divider divides the SPI reference - // clock (CLKSPIREF) with a 4-bit - // value and results in a new clock - // SPICLK available to shift-in and - // shift-out data. By default the - // clock divider ratio has a power - // of two granularity when - // MCSPI_CHCONF[CLKG] is cleared - // Otherwise this register is the 4 - // LSB bit of a 12-bit register - // concatenated with clock divider - // extension MCSPI_CHCTRL[EXTCLK] - // register.The value description - // below defines the clock ratio - // when MCSPI_CHCONF[CLKG] is set to - // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 - // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 - // 512 0xA 1024 0xB 2048 0xC 4096 - // 0xD 8192 0xE 16384 0xF 32768 -#define MCSPI_CH0CONF_CLKD_S 2 -#define MCSPI_CH0CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held - // high during the active state 1 - // SPICLK is held low during the - // active state -#define MCSPI_CH0CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched - // on odd numbered edges of SPICLK. - // 1 Data are latched on even - // numbered edges of SPICLK. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH0STAT register. -// -//****************************************************************************** -#define MCSPI_CH0STAT_RXFFF 0x00000040 -#define MCSPI_CH0STAT_RXFFE 0x00000020 -#define MCSPI_CH0STAT_TXFFF 0x00000010 -#define MCSPI_CH0STAT_TXFFE 0x00000008 -#define MCSPI_CH0STAT_EOT 0x00000004 -#define MCSPI_CH0STAT_TXS 0x00000002 -#define MCSPI_CH0STAT_RXS 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH0CTRL register. -// -//****************************************************************************** -#define MCSPI_CH0CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This - // register is used to concatenate - // with MCSPI_CHCONF[CLKD] register - // for clock ratio only when - // granularity is one clock cycle - // (MCSPI_CHCONF[CLKG] set to 1). - // Then the max value reached is - // 4096 clock divider ratio. 0x00 - // Clock ratio is CLKD + 1 0x01 - // Clock ratio is CLKD + 1 + 16 0xFF - // Clock ratio is CLKD + 1 + 4080 -#define MCSPI_CH0CTRL_EXTCLK_S 8 -#define MCSPI_CH0CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" - // is not active" 1 "Channel ""i"" - // is active" -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_TX0 register. -// -//****************************************************************************** -#define MCSPI_TX0_TDATA_M 0xFFFFFFFF // Channel 0 Data to transmit -#define MCSPI_TX0_TDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_RX0 register. -// -//****************************************************************************** -#define MCSPI_RX0_RDATA_M 0xFFFFFFFF // Channel 0 Received Data -#define MCSPI_RX0_RDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH1CONF register. -// -//****************************************************************************** -#define MCSPI_CH1CONF_CLKG 0x20000000 // Clock divider granularity This - // register defines the granularity - // of channel clock divider: power - // of two or one clock cycle - // granularity. When this bit is set - // the register MCSPI_CHCTRL[EXTCLK] - // must be configured to reach a - // maximum of 4096 clock divider - // ratio. Then The clock divider - // ratio is a concatenation of - // MCSPI_CHCONF[CLKD] and - // MCSPI_CHCTRL[EXTCLK] values 0 - // Clock granularity of power of two - // 1 One clock cycle ganularity -#define MCSPI_CH1CONF_FFER 0x10000000 // FIFO enabled for receive:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to receive data. 1 The - // buffer is used to receive data. -#define MCSPI_CH1CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to transmit data. 1 The - // buffer is used to transmit data. -#define MCSPI_CH1CONF_TCS1_M 0x06000000 // Chip Select Time Control This - // 2-bits field defines the number - // of interface clock cycles between - // CS toggling and first or last - // edge of SPI clock. 0x0 0.5 clock - // cycle 0x1 1.5 clock cycle 0x2 2.5 - // clock cycle 0x3 3.5 clock cycle -#define MCSPI_CH1CONF_TCS1_S 25 -#define MCSPI_CH1CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit - // polarity is held to 0 during SPI - // transfer. 1 Start bit polarity is - // held to 1 during SPI transfer. -#define MCSPI_CH1CONF_SBE 0x00800000 // Start bit enable for SPI - // transfer 0 Default SPI transfer - // length as specified by WL bit - // field 1 Start bit D/CX added - // before SPI transfer polarity is - // defined by MCSPI_CH1CONF[SBPOL] -#define MCSPI_CH1CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep - // SPIEN active between SPI words. - // (single channel master mode only) - // 0 Writing 0 into this bit drives - // low the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it high when - // MCSPI_CHCONF(i)[EPOL]=1. 1 - // Writing 1 into this bit drives - // high the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it low when - // MCSPI_CHCONF(i)[EPOL]=1 -#define MCSPI_CH1CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is - // deactivated (recommended for - // single SPI word transfer) 1 Turbo - // is activated to maximize the - // throughput for multi SPI words - // transfer. -#define MCSPI_CH1CONF_IS 0x00040000 // Input Select 0 Data Line0 - // (SPIDAT[0]) selected for - // reception. 1 Data Line1 - // (SPIDAT[1]) selected for - // reception -#define MCSPI_CH1CONF_DPE1 0x00020000 // Transmission Enable for data - // line 1 (SPIDATAGZEN[1]) 0 Data - // Line1 (SPIDAT[1]) selected for - // transmission 1 No transmission on - // Data Line1 (SPIDAT[1]) -#define MCSPI_CH1CONF_DPE0 0x00010000 // Transmission Enable for data - // line 0 (SPIDATAGZEN[0]) 0 Data - // Line0 (SPIDAT[0]) selected for - // transmission 1 No transmission on - // Data Line0 (SPIDAT[0]) -#define MCSPI_CH1CONF_DMAR 0x00008000 // DMA Read request The DMA Read - // request line is asserted when the - // channel is enabled and a new data - // is available in the receive - // register of the channel. The DMA - // Read request line is deasserted - // on read completion of the receive - // register of the channel. 0 DMA - // Read Request disabled 1 DMA Read - // Request enabled -#define MCSPI_CH1CONF_DMAW 0x00004000 // DMA Write request. The DMA Write - // request line is asserted when The - // channel is enabled and the - // transmitter register of the - // channel is empty. The DMA Write - // request line is deasserted on - // load completion of the - // transmitter register of the - // channel. 0 DMA Write Request - // disabled 1 DMA Write Request - // enabled -#define MCSPI_CH1CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 - // Transmit and Receive mode 0x1 - // Receive only mode 0x2 Transmit - // only mode 0x3 Reserved -#define MCSPI_CH1CONF_TRM_S 12 -#define MCSPI_CH1CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved - // 0x01 Reserved 0x02 Reserved 0x03 - // The SPI word is 4-bits long 0x04 - // The SPI word is 5-bits long 0x05 - // The SPI word is 6-bits long 0x06 - // The SPI word is 7-bits long 0x07 - // The SPI word is 8-bits long 0x08 - // The SPI word is 9-bits long 0x09 - // The SPI word is 10-bits long 0x0A - // The SPI word is 11-bits long 0x0B - // The SPI word is 12-bits long 0x0C - // The SPI word is 13-bits long 0x0D - // The SPI word is 14-bits long 0x0E - // The SPI word is 15-bits long 0x0F - // The SPI word is 16-bits long 0x10 - // The SPI word is 17-bits long 0x11 - // The SPI word is 18-bits long 0x12 - // The SPI word is 19-bits long 0x13 - // The SPI word is 20-bits long 0x14 - // The SPI word is 21-bits long 0x15 - // The SPI word is 22-bits long 0x16 - // The SPI word is 23-bits long 0x17 - // The SPI word is 24-bits long 0x18 - // The SPI word is 25-bits long 0x19 - // The SPI word is 26-bits long 0x1A - // The SPI word is 27-bits long 0x1B - // The SPI word is 28-bits long 0x1C - // The SPI word is 29-bits long 0x1D - // The SPI word is 30-bits long 0x1E - // The SPI word is 31-bits long 0x1F - // The SPI word is 32-bits long -#define MCSPI_CH1CONF_WL_S 7 -#define MCSPI_CH1CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held - // high during the active state. 1 - // SPIEN is held low during the - // active state. -#define MCSPI_CH1CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. - // (only when the module is a Master - // SPI device). A programmable clock - // divider divides the SPI reference - // clock (CLKSPIREF) with a 4-bit - // value and results in a new clock - // SPICLK available to shift-in and - // shift-out data. By default the - // clock divider ratio has a power - // of two granularity when - // MCSPI_CHCONF[CLKG] is cleared - // Otherwise this register is the 4 - // LSB bit of a 12-bit register - // concatenated with clock divider - // extension MCSPI_CHCTRL[EXTCLK] - // register.The value description - // below defines the clock ratio - // when MCSPI_CHCONF[CLKG] is set to - // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 - // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 - // 512 0xA 1024 0xB 2048 0xC 4096 - // 0xD 8192 0xE 16384 0xF 32768 -#define MCSPI_CH1CONF_CLKD_S 2 -#define MCSPI_CH1CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held - // high during the active state 1 - // SPICLK is held low during the - // active state -#define MCSPI_CH1CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched - // on odd numbered edges of SPICLK. - // 1 Data are latched on even - // numbered edges of SPICLK. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH1STAT register. -// -//****************************************************************************** -#define MCSPI_CH1STAT_RXFFF 0x00000040 -#define MCSPI_CH1STAT_RXFFE 0x00000020 -#define MCSPI_CH1STAT_TXFFF 0x00000010 -#define MCSPI_CH1STAT_TXFFE 0x00000008 -#define MCSPI_CH1STAT_EOT 0x00000004 -#define MCSPI_CH1STAT_TXS 0x00000002 -#define MCSPI_CH1STAT_RXS 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH1CTRL register. -// -//****************************************************************************** -#define MCSPI_CH1CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This - // register is used to concatenate - // with MCSPI_CHCONF[CLKD] register - // for clock ratio only when - // granularity is one clock cycle - // (MCSPI_CHCONF[CLKG] set to 1). - // Then the max value reached is - // 4096 clock divider ratio. 0x00 - // Clock ratio is CLKD + 1 0x01 - // Clock ratio is CLKD + 1 + 16 0xFF - // Clock ratio is CLKD + 1 + 4080 -#define MCSPI_CH1CTRL_EXTCLK_S 8 -#define MCSPI_CH1CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" - // is not active" 1 "Channel ""i"" - // is active" -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_TX1 register. -// -//****************************************************************************** -#define MCSPI_TX1_TDATA_M 0xFFFFFFFF // Channel 1 Data to transmit -#define MCSPI_TX1_TDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_RX1 register. -// -//****************************************************************************** -#define MCSPI_RX1_RDATA_M 0xFFFFFFFF // Channel 1 Received Data -#define MCSPI_RX1_RDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH2CONF register. -// -//****************************************************************************** -#define MCSPI_CH2CONF_CLKG 0x20000000 // Clock divider granularity This - // register defines the granularity - // of channel clock divider: power - // of two or one clock cycle - // granularity. When this bit is set - // the register MCSPI_CHCTRL[EXTCLK] - // must be configured to reach a - // maximum of 4096 clock divider - // ratio. Then The clock divider - // ratio is a concatenation of - // MCSPI_CHCONF[CLKD] and - // MCSPI_CHCTRL[EXTCLK] values 0 - // Clock granularity of power of two - // 1 One clock cycle ganularity -#define MCSPI_CH2CONF_FFER 0x10000000 // FIFO enabled for receive:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to receive data. 1 The - // buffer is used to receive data. -#define MCSPI_CH2CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to transmit data. 1 The - // buffer is used to transmit data. -#define MCSPI_CH2CONF_TCS2_M 0x06000000 // Chip Select Time Control This - // 2-bits field defines the number - // of interface clock cycles between - // CS toggling and first or last - // edge of SPI clock. 0x0 0.5 clock - // cycle 0x1 1.5 clock cycle 0x2 2.5 - // clock cycle 0x3 3.5 clock cycle -#define MCSPI_CH2CONF_TCS2_S 25 -#define MCSPI_CH2CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit - // polarity is held to 0 during SPI - // transfer. 1 Start bit polarity is - // held to 1 during SPI transfer. -#define MCSPI_CH2CONF_SBE 0x00800000 // Start bit enable for SPI - // transfer 0 Default SPI transfer - // length as specified by WL bit - // field 1 Start bit D/CX added - // before SPI transfer polarity is - // defined by MCSPI_CH2CONF[SBPOL] -#define MCSPI_CH2CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep - // SPIEN active between SPI words. - // (single channel master mode only) - // 0 Writing 0 into this bit drives - // low the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it high when - // MCSPI_CHCONF(i)[EPOL]=1. 1 - // Writing 1 into this bit drives - // high the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it low when - // MCSPI_CHCONF(i)[EPOL]=1 -#define MCSPI_CH2CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is - // deactivated (recommended for - // single SPI word transfer) 1 Turbo - // is activated to maximize the - // throughput for multi SPI words - // transfer. -#define MCSPI_CH2CONF_IS 0x00040000 // Input Select 0 Data Line0 - // (SPIDAT[0]) selected for - // reception. 1 Data Line1 - // (SPIDAT[1]) selected for - // reception -#define MCSPI_CH2CONF_DPE1 0x00020000 // Transmission Enable for data - // line 1 (SPIDATAGZEN[1]) 0 Data - // Line1 (SPIDAT[1]) selected for - // transmission 1 No transmission on - // Data Line1 (SPIDAT[1]) -#define MCSPI_CH2CONF_DPE0 0x00010000 // Transmission Enable for data - // line 0 (SPIDATAGZEN[0]) 0 Data - // Line0 (SPIDAT[0]) selected for - // transmission 1 No transmission on - // Data Line0 (SPIDAT[0]) -#define MCSPI_CH2CONF_DMAR 0x00008000 // DMA Read request The DMA Read - // request line is asserted when the - // channel is enabled and a new data - // is available in the receive - // register of the channel. The DMA - // Read request line is deasserted - // on read completion of the receive - // register of the channel. 0 DMA - // Read Request disabled 1 DMA Read - // Request enabled -#define MCSPI_CH2CONF_DMAW 0x00004000 // DMA Write request. The DMA Write - // request line is asserted when The - // channel is enabled and the - // transmitter register of the - // channel is empty. The DMA Write - // request line is deasserted on - // load completion of the - // transmitter register of the - // channel. 0 DMA Write Request - // disabled 1 DMA Write Request - // enabled -#define MCSPI_CH2CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 - // Transmit and Receive mode 0x1 - // Receive only mode 0x2 Transmit - // only mode 0x3 Reserved -#define MCSPI_CH2CONF_TRM_S 12 -#define MCSPI_CH2CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved - // 0x01 Reserved 0x02 Reserved 0x03 - // The SPI word is 4-bits long 0x04 - // The SPI word is 5-bits long 0x05 - // The SPI word is 6-bits long 0x06 - // The SPI word is 7-bits long 0x07 - // The SPI word is 8-bits long 0x08 - // The SPI word is 9-bits long 0x09 - // The SPI word is 10-bits long 0x0A - // The SPI word is 11-bits long 0x0B - // The SPI word is 12-bits long 0x0C - // The SPI word is 13-bits long 0x0D - // The SPI word is 14-bits long 0x0E - // The SPI word is 15-bits long 0x0F - // The SPI word is 16-bits long 0x10 - // The SPI word is 17-bits long 0x11 - // The SPI word is 18-bits long 0x12 - // The SPI word is 19-bits long 0x13 - // The SPI word is 20-bits long 0x14 - // The SPI word is 21-bits long 0x15 - // The SPI word is 22-bits long 0x16 - // The SPI word is 23-bits long 0x17 - // The SPI word is 24-bits long 0x18 - // The SPI word is 25-bits long 0x19 - // The SPI word is 26-bits long 0x1A - // The SPI word is 27-bits long 0x1B - // The SPI word is 28-bits long 0x1C - // The SPI word is 29-bits long 0x1D - // The SPI word is 30-bits long 0x1E - // The SPI word is 31-bits long 0x1F - // The SPI word is 32-bits long -#define MCSPI_CH2CONF_WL_S 7 -#define MCSPI_CH2CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held - // high during the active state. 1 - // SPIEN is held low during the - // active state. -#define MCSPI_CH2CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. - // (only when the module is a Master - // SPI device). A programmable clock - // divider divides the SPI reference - // clock (CLKSPIREF) with a 4-bit - // value and results in a new clock - // SPICLK available to shift-in and - // shift-out data. By default the - // clock divider ratio has a power - // of two granularity when - // MCSPI_CHCONF[CLKG] is cleared - // Otherwise this register is the 4 - // LSB bit of a 12-bit register - // concatenated with clock divider - // extension MCSPI_CHCTRL[EXTCLK] - // register.The value description - // below defines the clock ratio - // when MCSPI_CHCONF[CLKG] is set to - // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 - // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 - // 512 0xA 1024 0xB 2048 0xC 4096 - // 0xD 8192 0xE 16384 0xF 32768 -#define MCSPI_CH2CONF_CLKD_S 2 -#define MCSPI_CH2CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held - // high during the active state 1 - // SPICLK is held low during the - // active state -#define MCSPI_CH2CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched - // on odd numbered edges of SPICLK. - // 1 Data are latched on even - // numbered edges of SPICLK. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH2STAT register. -// -//****************************************************************************** -#define MCSPI_CH2STAT_RXFFF 0x00000040 -#define MCSPI_CH2STAT_RXFFE 0x00000020 -#define MCSPI_CH2STAT_TXFFF 0x00000010 -#define MCSPI_CH2STAT_TXFFE 0x00000008 -#define MCSPI_CH2STAT_EOT 0x00000004 -#define MCSPI_CH2STAT_TXS 0x00000002 -#define MCSPI_CH2STAT_RXS 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH2CTRL register. -// -//****************************************************************************** -#define MCSPI_CH2CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This - // register is used to concatenate - // with MCSPI_CHCONF[CLKD] register - // for clock ratio only when - // granularity is one clock cycle - // (MCSPI_CHCONF[CLKG] set to 1). - // Then the max value reached is - // 4096 clock divider ratio. 0x00 - // Clock ratio is CLKD + 1 0x01 - // Clock ratio is CLKD + 1 + 16 0xFF - // Clock ratio is CLKD + 1 + 4080 -#define MCSPI_CH2CTRL_EXTCLK_S 8 -#define MCSPI_CH2CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" - // is not active" 1 "Channel ""i"" - // is active" -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_TX2 register. -// -//****************************************************************************** -#define MCSPI_TX2_TDATA_M 0xFFFFFFFF // Channel 2 Data to transmit -#define MCSPI_TX2_TDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_RX2 register. -// -//****************************************************************************** -#define MCSPI_RX2_RDATA_M 0xFFFFFFFF // Channel 2 Received Data -#define MCSPI_RX2_RDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH3CONF register. -// -//****************************************************************************** -#define MCSPI_CH3CONF_CLKG 0x20000000 // Clock divider granularity This - // register defines the granularity - // of channel clock divider: power - // of two or one clock cycle - // granularity. When this bit is set - // the register MCSPI_CHCTRL[EXTCLK] - // must be configured to reach a - // maximum of 4096 clock divider - // ratio. Then The clock divider - // ratio is a concatenation of - // MCSPI_CHCONF[CLKD] and - // MCSPI_CHCTRL[EXTCLK] values 0 - // Clock granularity of power of two - // 1 One clock cycle ganularity -#define MCSPI_CH3CONF_FFER 0x10000000 // FIFO enabled for receive:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to receive data. 1 The - // buffer is used to receive data. -#define MCSPI_CH3CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only - // one channel can have this bit - // field set. 0 The buffer is not - // used to transmit data. 1 The - // buffer is used to transmit data. -#define MCSPI_CH3CONF_TCS3_M 0x06000000 // Chip Select Time Control This - // 2-bits field defines the number - // of interface clock cycles between - // CS toggling and first or last - // edge of SPI clock. 0x0 0.5 clock - // cycle 0x1 1.5 clock cycle 0x2 2.5 - // clock cycle 0x3 3.5 clock cycle -#define MCSPI_CH3CONF_TCS3_S 25 -#define MCSPI_CH3CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit - // polarity is held to 0 during SPI - // transfer. 1 Start bit polarity is - // held to 1 during SPI transfer. -#define MCSPI_CH3CONF_SBE 0x00800000 // Start bit enable for SPI - // transfer 0 Default SPI transfer - // length as specified by WL bit - // field 1 Start bit D/CX added - // before SPI transfer polarity is - // defined by MCSPI_CH3CONF[SBPOL] -#define MCSPI_CH3CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep - // SPIEN active between SPI words. - // (single channel master mode only) - // 0 Writing 0 into this bit drives - // low the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it high when - // MCSPI_CHCONF(i)[EPOL]=1. 1 - // Writing 1 into this bit drives - // high the SPIEN line when - // MCSPI_CHCONF(i)[EPOL]=0 and - // drives it low when - // MCSPI_CHCONF(i)[EPOL]=1 -#define MCSPI_CH3CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is - // deactivated (recommended for - // single SPI word transfer) 1 Turbo - // is activated to maximize the - // throughput for multi SPI words - // transfer. -#define MCSPI_CH3CONF_IS 0x00040000 // Input Select 0 Data Line0 - // (SPIDAT[0]) selected for - // reception. 1 Data Line1 - // (SPIDAT[1]) selected for - // reception -#define MCSPI_CH3CONF_DPE1 0x00020000 // Transmission Enable for data - // line 1 (SPIDATAGZEN[1]) 0 Data - // Line1 (SPIDAT[1]) selected for - // transmission 1 No transmission on - // Data Line1 (SPIDAT[1]) -#define MCSPI_CH3CONF_DPE0 0x00010000 // Transmission Enable for data - // line 0 (SPIDATAGZEN[0]) 0 Data - // Line0 (SPIDAT[0]) selected for - // transmission 1 No transmission on - // Data Line0 (SPIDAT[0]) -#define MCSPI_CH3CONF_DMAR 0x00008000 // DMA Read request The DMA Read - // request line is asserted when the - // channel is enabled and a new data - // is available in the receive - // register of the channel. The DMA - // Read request line is deasserted - // on read completion of the receive - // register of the channel. 0 DMA - // Read Request disabled 1 DMA Read - // Request enabled -#define MCSPI_CH3CONF_DMAW 0x00004000 // DMA Write request. The DMA Write - // request line is asserted when The - // channel is enabled and the - // transmitter register of the - // channel is empty. The DMA Write - // request line is deasserted on - // load completion of the - // transmitter register of the - // channel. 0 DMA Write Request - // disabled 1 DMA Write Request - // enabled -#define MCSPI_CH3CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 - // Transmit and Receive mode 0x1 - // Receive only mode 0x2 Transmit - // only mode 0x3 Reserved -#define MCSPI_CH3CONF_TRM_S 12 -#define MCSPI_CH3CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved - // 0x01 Reserved 0x02 Reserved 0x03 - // The SPI word is 4-bits long 0x04 - // The SPI word is 5-bits long 0x05 - // The SPI word is 6-bits long 0x06 - // The SPI word is 7-bits long 0x07 - // The SPI word is 8-bits long 0x08 - // The SPI word is 9-bits long 0x09 - // The SPI word is 10-bits long 0x0A - // The SPI word is 11-bits long 0x0B - // The SPI word is 12-bits long 0x0C - // The SPI word is 13-bits long 0x0D - // The SPI word is 14-bits long 0x0E - // The SPI word is 15-bits long 0x0F - // The SPI word is 16-bits long 0x10 - // The SPI word is 17-bits long 0x11 - // The SPI word is 18-bits long 0x12 - // The SPI word is 19-bits long 0x13 - // The SPI word is 20-bits long 0x14 - // The SPI word is 21-bits long 0x15 - // The SPI word is 22-bits long 0x16 - // The SPI word is 23-bits long 0x17 - // The SPI word is 24-bits long 0x18 - // The SPI word is 25-bits long 0x19 - // The SPI word is 26-bits long 0x1A - // The SPI word is 27-bits long 0x1B - // The SPI word is 28-bits long 0x1C - // The SPI word is 29-bits long 0x1D - // The SPI word is 30-bits long 0x1E - // The SPI word is 31-bits long 0x1F - // The SPI word is 32-bits long -#define MCSPI_CH3CONF_WL_S 7 -#define MCSPI_CH3CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held - // high during the active state. 1 - // SPIEN is held low during the - // active state. -#define MCSPI_CH3CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. - // (only when the module is a Master - // SPI device). A programmable clock - // divider divides the SPI reference - // clock (CLKSPIREF) with a 4-bit - // value and results in a new clock - // SPICLK available to shift-in and - // shift-out data. By default the - // clock divider ratio has a power - // of two granularity when - // MCSPI_CHCONF[CLKG] is cleared - // Otherwise this register is the 4 - // LSB bit of a 12-bit register - // concatenated with clock divider - // extension MCSPI_CHCTRL[EXTCLK] - // register.The value description - // below defines the clock ratio - // when MCSPI_CHCONF[CLKG] is set to - // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 - // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 - // 512 0xA 1024 0xB 2048 0xC 4096 - // 0xD 8192 0xE 16384 0xF 32768 -#define MCSPI_CH3CONF_CLKD_S 2 -#define MCSPI_CH3CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held - // high during the active state 1 - // SPICLK is held low during the - // active state -#define MCSPI_CH3CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched - // on odd numbered edges of SPICLK. - // 1 Data are latched on even - // numbered edges of SPICLK. -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH3STAT register. -// -//****************************************************************************** -#define MCSPI_CH3STAT_RXFFF 0x00000040 -#define MCSPI_CH3STAT_RXFFE 0x00000020 -#define MCSPI_CH3STAT_TXFFF 0x00000010 -#define MCSPI_CH3STAT_TXFFE 0x00000008 -#define MCSPI_CH3STAT_EOT 0x00000004 -#define MCSPI_CH3STAT_TXS 0x00000002 -#define MCSPI_CH3STAT_RXS 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_CH3CTRL register. -// -//****************************************************************************** -#define MCSPI_CH3CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This - // register is used to concatenate - // with MCSPI_CHCONF[CLKD] register - // for clock ratio only when - // granularity is one clock cycle - // (MCSPI_CHCONF[CLKG] set to 1). - // Then the max value reached is - // 4096 clock divider ratio. 0x00 - // Clock ratio is CLKD + 1 0x01 - // Clock ratio is CLKD + 1 + 16 0xFF - // Clock ratio is CLKD + 1 + 4080 -#define MCSPI_CH3CTRL_EXTCLK_S 8 -#define MCSPI_CH3CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" - // is not active" 1 "Channel ""i"" - // is active" -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_TX3 register. -// -//****************************************************************************** -#define MCSPI_TX3_TDATA_M 0xFFFFFFFF // Channel 3 Data to transmit -#define MCSPI_TX3_TDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_RX3 register. -// -//****************************************************************************** -#define MCSPI_RX3_RDATA_M 0xFFFFFFFF // Channel 3 Received Data -#define MCSPI_RX3_RDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_XFERLEVEL register. -// -//****************************************************************************** -#define MCSPI_XFERLEVEL_WCNT_M 0xFFFF0000 // Spi word counterThis register - // holds the programmable value of - // number of SPI word to be - // transferred on channel which is - // using the FIFO buffer.When - // transfer had started a read back - // in this register returns the - // current SPI word transfer index. - // 0x0000 Counter not used 0x0001 - // one word 0xFFFE 65534 spi word - // 0xFFFF 65535 spi word -#define MCSPI_XFERLEVEL_WCNT_S 16 -#define MCSPI_XFERLEVEL_AFL_M 0x0000FF00 // Buffer Almost Full This register - // holds the programmable almost - // full level value used to - // determine almost full buffer - // condition. If the user wants an - // interrupt or a DMA read request - // to be issued during a receive - // operation when the data buffer - // holds at least n bytes then the - // buffer MCSPI_MODULCTRL[AFL] must - // be set with n-1.The size of this - // register is defined by the - // generic parameter FFNBYTE. 0x00 - // one byte 0x01 2 bytes 0xFE - // 255bytes 0xFF 256bytes -#define MCSPI_XFERLEVEL_AFL_S 8 -#define MCSPI_XFERLEVEL_AEL_M 0x000000FF // Buffer Almost EmptyThis register - // holds the programmable almost - // empty level value used to - // determine almost empty buffer - // condition. If the user wants an - // interrupt or a DMA write request - // to be issued during a transmit - // operation when the data buffer is - // able to receive n bytes then the - // buffer MCSPI_MODULCTRL[AEL] must - // be set with n-1. 0x00 one byte - // 0x01 2 bytes 0xFE 255 bytes 0xFF - // 256bytes -#define MCSPI_XFERLEVEL_AEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_DAFTX register. -// -//****************************************************************************** -#define MCSPI_DAFTX_DAFTDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA - // 256 bit aligned address. "This - // Register is only is used when - // MCSPI_MODULCTRL[FDAA] is set to - // ""1"" and only one of the - // MCSPI_CH(i)CONF[FFEW] of enabled - // channels is set. If these - // conditions are not respected any - // access to this register return a - // null value." -#define MCSPI_DAFTX_DAFTDATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MCSPI_O_DAFRX register. -// -//****************************************************************************** -#define MCSPI_DAFRX_DAFRDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA - // 256 bit aligned address. "This - // Register is only is used when - // MCSPI_MODULCTRL[FDAA] is set to - // ""1"" and only one of the - // MCSPI_CH(i)CONF[FFEW] of enabled - // channels is set. If these - // conditions are not respected any - // access to this register return a - // null value." -#define MCSPI_DAFRX_DAFRDATA_S 0 - - - -#endif // __HW_MCSPI_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_memmap.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_memmap.h deleted file mode 100644 index 0919ee8c1d2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_memmap.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_MEMMAP_H__ -#define __HW_MEMMAP_H__ - -//***************************************************************************** -// -// The following are defines for the base address of the memories and -// peripherals on the slave_1 interface. -// -//***************************************************************************** -#define FLASH_BASE 0x01000000 -#define SRAM_BASE 0x20000000 -#define WDT_BASE 0x40000000 -#define GPIOA0_BASE 0x40004000 -#define GPIOA1_BASE 0x40005000 -#define GPIOA2_BASE 0x40006000 -#define GPIOA3_BASE 0x40007000 -#define GPIOA4_BASE 0x40024000 -#define UARTA0_BASE 0x4000C000 -#define UARTA1_BASE 0x4000D000 -#define I2CA0_BASE 0x40020000 -#define TIMERA0_BASE 0x40030000 -#define TIMERA1_BASE 0x40031000 -#define TIMERA2_BASE 0x40032000 -#define TIMERA3_BASE 0x40033000 -#define STACKDIE_CTRL_BASE 0x400F5000 -#define COMMON_REG_BASE 0x400F7000 -#define FLASH_CONTROL_BASE 0x400FD000 -#define SYSTEM_CONTROL_BASE 0x400FE000 -#define UDMA_BASE 0x400FF000 -#define SDHOST_BASE 0x44010000 -#define CAMERA_BASE 0x44018000 -#define I2S_BASE 0x4401C000 -#define SSPI_BASE 0x44020000 -#define GSPI_BASE 0x44021000 -#define LSPI_BASE 0x44022000 -#define ARCM_BASE 0x44025000 -#define APPS_CONFIG_BASE 0x44026000 -#define GPRCM_BASE 0x4402D000 -#define OCP_SHARED_BASE 0x4402E000 -#define ADC_BASE 0x4402E800 -#define HIB1P2_BASE 0x4402F000 -#define HIB3P3_BASE 0x4402F800 -#define DTHE_BASE 0x44030000 -#define SHAMD5_BASE 0x44035000 -#define AES_BASE 0x44037000 -#define DES_BASE 0x44039000 - - -#endif // __HW_MEMMAP_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_mmchs.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_mmchs.h deleted file mode 100644 index 88b8e755853..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_mmchs.h +++ /dev/null @@ -1,1917 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_MMCHS_H__ -#define __HW_MMCHS_H__ - -//***************************************************************************** -// -// The following are defines for the MMCHS register offsets. -// -//***************************************************************************** -#define MMCHS_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) - // Used by software to track - // features bugs and compatibility -#define MMCHS_O_HL_HWINFO 0x00000004 // Information about the IP - // module's hardware configuration - // i.e. typically the module's HDL - // generics (if any). Actual field - // format and encoding is up to the - // module's designer to decide. -#define MMCHS_O_HL_SYSCONFIG 0x00000010 // Clock management configuration -#define MMCHS_O_SYSCONFIG 0x00000110 // System Configuration Register - // This register allows controlling - // various parameters of the OCP - // interface. -#define MMCHS_O_SYSSTATUS 0x00000114 // System Status Register This - // register provides status - // information about the module - // excluding the interrupt status - // information -#define MMCHS_O_CSRE 0x00000124 // Card status response error This - // register enables the host - // controller to detect card status - // errors of response type R1 R1b - // for all cards and of R5 R5b and - // R6 response for cards types SD or - // SDIO. When a bit MMCHS_CSRE[i] is - // set to 1 if the corresponding bit - // at the same position in the - // response MMCHS_RSP0[i] is set to - // 1 the host controller indicates a - // card error (MMCHS_STAT[CERR]) - // interrupt status to avoid the - // host driver reading the response - // register (MMCHS_RSP0). Note: No - // automatic card error detection - // for autoCMD12 is implemented; the - // host system has to check - // autoCMD12 response register - // (MMCHS_RESP76) for possible card - // errors. -#define MMCHS_O_SYSTEST 0x00000128 // System Test register This - // register is used to control the - // signals that connect to I/O pins - // when the module is configured in - // system test (SYSTEST) mode for - // boundary connectivity - // verification. Note: In SYSTEST - // mode a write into MMCHS_CMD - // register will not start a - // transfer. The buffer behaves as a - // stack accessible only by the - // local host (push and pop - // operations). In this mode the - // Transfer Block Size - // (MMCHS_BLK[BLEN]) and the Blocks - // count for current transfer - // (MMCHS_BLK[NBLK]) are needed to - // generate a Buffer write ready - // interrupt (MMCHS_STAT[BWR]) or a - // Buffer read ready interrupt - // (MMCHS_STAT[BRR]) and DMA - // requests if enabled. -#define MMCHS_O_CON 0x0000012C // Configuration register This - // register is used: - to select the - // functional mode or the SYSTEST - // mode for any card. - to send an - // initialization sequence to any - // card. - to enable the detection - // on DAT[1] of a card interrupt for - // SDIO cards only. and also to - // configure : - specific data and - // command transfers for MMC cards - // only. - the parameters related to - // the card detect and write protect - // input signals. -#define MMCHS_O_PWCNT 0x00000130 // Power counter register This - // register is used to program a mmc - // counter to delay command - // transfers after activating the - // PAD power this value depends on - // PAD characteristics and voltage. -#define MMCHS_O_BLK 0x00000204 // Transfer Length Configuration - // register MMCHS_BLK[BLEN] is the - // block size register. - // MMCHS_BLK[NBLK] is the block - // count register. This register - // shall be used for any card. -#define MMCHS_O_ARG 0x00000208 // Command argument Register This - // register contains command - // argument specified as bit 39-8 of - // Command-Format These registers - // must be initialized prior to - // sending the command itself to the - // card (write action into the - // register MMCHS_CMD register). - // Only exception is for a command - // index specifying stuff bits in - // arguments making a write - // unnecessary. -#define MMCHS_O_CMD 0x0000020C // Command and transfer mode - // register MMCHS_CMD[31:16] = the - // command register MMCHS_CMD[15:0] - // = the transfer mode. This - // register configures the data and - // command transfers. A write into - // the most significant byte send - // the command. A write into - // MMCHS_CMD[15:0] registers during - // data transfer has no effect. This - // register shall be used for any - // card. Note: In SYSTEST mode a - // write into MMCHS_CMD register - // will not start a transfer. -#define MMCHS_O_RSP10 0x00000210 // Command response[31:0] Register - // This 32-bit register holds bits - // positions [31:0] of command - // response type - // R1/R1b/R2/R3/R4/R5/R5b/R6 -#define MMCHS_O_RSP32 0x00000214 // Command response[63:32] Register - // This 32-bit register holds bits - // positions [63:32] of command - // response type R2 -#define MMCHS_O_RSP54 0x00000218 // Command response[95:64] Register - // This 32-bit register holds bits - // positions [95:64] of command - // response type R2 -#define MMCHS_O_RSP76 0x0000021C // Command response[127:96] - // Register This 32-bit register - // holds bits positions [127:96] of - // command response type R2 -#define MMCHS_O_DATA 0x00000220 // Data Register This register is - // the 32-bit entry point of the - // buffer for read or write data - // transfers. The buffer size is - // 32bits x256(1024 bytes). Bytes - // within a word are stored and read - // in little endian format. This - // buffer can be used as two 512 - // byte buffers to transfer data - // efficiently without reducing the - // throughput. Sequential and - // contiguous access is necessary to - // increment the pointer correctly. - // Random or skipped access is not - // allowed. In little endian if the - // local host accesses this register - // byte-wise or 16bit-wise the least - // significant byte (bits [7:0]) - // must always be written/read - // first. The update of the buffer - // address is done on the most - // significant byte write for full - // 32-bit DATA register or on the - // most significant byte of the last - // word of block transfer. Example - // 1: Byte or 16-bit access - // Mbyteen[3:0]=0001 (1-byte) => - // Mbyteen[3:0]=0010 (1-byte) => - // Mbyteen[3:0]=1100 (2-bytes) OK - // Mbyteen[3:0]=0001 (1-byte) => - // Mbyteen[3:0]=0010 (1-byte) => - // Mbyteen[3:0]=0100 (1-byte) OK - // Mbyteen[3:0]=0001 (1-byte) => - // Mbyteen[3:0]=0010 (1-byte) => - // Mbyteen[3:0]=1000 (1-byte) Bad -#define MMCHS_O_PSTATE 0x00000224 // Present state register The Host - // can get status of the Host - // Controller from this 32-bit read - // only register. -#define MMCHS_O_HCTL 0x00000228 // Control register This register - // defines the host controls to set - // power wakeup and transfer - // parameters. MMCHS_HCTL[31:24] = - // Wakeup control MMCHS_HCTL[23:16] - // = Block gap control - // MMCHS_HCTL[15:8] = Power control - // MMCHS_HCTL[7:0] = Host control -#define MMCHS_O_SYSCTL 0x0000022C // SD system control register This - // register defines the system - // controls to set software resets - // clock frequency management and - // data timeout. MMCHS_SYSCTL[31:24] - // = Software resets - // MMCHS_SYSCTL[23:16] = Timeout - // control MMCHS_SYSCTL[15:0] = - // Clock control -#define MMCHS_O_STAT 0x00000230 // Interrupt status register The - // interrupt status regroups all the - // status of the module internal - // events that can generate an - // interrupt. MMCHS_STAT[31:16] = - // Error Interrupt Status - // MMCHS_STAT[15:0] = Normal - // Interrupt Status -#define MMCHS_O_IE 0x00000234 // Interrupt SD enable register - // This register allows to - // enable/disable the module to set - // status bits on an event-by-event - // basis. MMCHS_IE[31:16] = Error - // Interrupt Status Enable - // MMCHS_IE[15:0] = Normal Interrupt - // Status Enable -#define MMCHS_O_ISE 0x00000238 // Interrupt signal enable register - // This register allows to - // enable/disable the module - // internal sources of status on an - // event-by-event basis. - // MMCHS_ISE[31:16] = Error - // Interrupt Signal Enable - // MMCHS_ISE[15:0] = Normal - // Interrupt Signal Enable -#define MMCHS_O_AC12 0x0000023C // Auto CMD12 Error Status Register - // The host driver may determine - // which of the errors cases related - // to Auto CMD12 has occurred by - // checking this MMCHS_AC12 register - // when an Auto CMD12 Error - // interrupt occurs. This register - // is valid only when Auto CMD12 is - // enabled (MMCHS_CMD[ACEN]) and - // Auto CMD12Error (MMCHS_STAT[ACE]) - // is set to 1. Note: These bits are - // automatically reset when starting - // a new adtc command with data. -#define MMCHS_O_CAPA 0x00000240 // Capabilities register This - // register lists the capabilities - // of the MMC/SD/SDIO host - // controller. -#define MMCHS_O_CUR_CAPA 0x00000248 // Maximum current capabilities - // Register This register indicates - // the maximum current capability - // for each voltage. The value is - // meaningful if the voltage support - // is set in the capabilities - // register (MMCHS_CAPA). - // Initialization of this register - // (via a write access to this - // register) depends on the system - // capabilities. The host driver - // shall not modify this register - // after the initilaization. This - // register is only reinitialized by - // a hard reset (via RESETN signal) -#define MMCHS_O_FE 0x00000250 // Force Event Register for Error - // Interrupt status The force Event - // Register is not a physically - // implemented register. Rather it - // is an address at which the Error - // Interrupt Status register can be - // written. The effect of a write to - // this address will be reflected in - // the Error Interrupt Status - // Register if corresponding bit of - // the Error Interrupt Status Enable - // Register is set. -#define MMCHS_O_ADMAES 0x00000254 // ADMA Error Status Register When - // ADMA Error Interrupt is occurred - // the ADMA Error States field in - // this register holds the ADMA - // state and the ADMA System Address - // Register holds the address around - // the error descriptor. For - // recovering the error the Host - // Driver requires the ADMA state to - // identify the error descriptor - // address as follows: ST_STOP: - // Previous location set in the ADMA - // System Address register is the - // error descriptor address ST_FDS: - // Current location set in the ADMA - // System Address register is the - // error descriptor address ST_CADR: - // This sate is never set because do - // not generate ADMA error in this - // state. ST_TFR: Previous location - // set in the ADMA System Address - // register is the error descriptor - // address In case of write - // operation the Host Driver should - // use ACMD22 to get the number of - // written block rather than using - // this information since unwritten - // data may exist in the Host - // Controller. The Host Controller - // generates the ADMA Error - // Interrupt when it detects invalid - // descriptor data (Valid=0) at the - // ST_FDS state. In this case ADMA - // Error State indicates that an - // error occurs at ST_FDS state. The - // Host Driver may find that the - // Valid bit is not set in the error - // descriptor. -#define MMCHS_O_ADMASAL 0x00000258 // ADMA System address Low bits -#define MMCHS_O_REV 0x000002FC // Versions Register This register - // contains the hard coded RTL - // vendor revision number the - // version number of SD - // specification compliancy and a - // slot status bit. MMCHS_REV[31:16] - // = Host controller version - // MMCHS_REV[15:0] = Slot Interrupt - // Status - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_HL_REV register. -// -//****************************************************************************** -#define MMCHS_HL_REV_SCHEME_M 0xC0000000 -#define MMCHS_HL_REV_SCHEME_S 30 -#define MMCHS_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software - // compatible module family. If - // there is no level of software - // compatibility a new Func number - // (and hence REVISION) should be - // assigned. -#define MMCHS_HL_REV_FUNC_S 16 -#define MMCHS_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP - // design owner. RTL follows a - // numbering such as X.Y.R.Z which - // are explained in this table. R - // changes ONLY when: (1) PDS - // uploads occur which may have been - // due to spec changes (2) Bug fixes - // occur (3) Resets to '0' when X or - // Y changes. Design team has an - // internal 'Z' (customer invisible) - // number which increments on every - // drop that happens due to DV and - // RTL updates. Z resets to 0 when R - // increments. -#define MMCHS_HL_REV_R_RTL_S 11 -#define MMCHS_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by - // IP specification owner. X changes - // ONLY when: (1) There is a major - // feature addition. An example - // would be adding Master Mode to - // Utopia Level2. The Func field (or - // Class/Type in old PID format) - // will remain the same. X does NOT - // change due to: (1) Bug fixes (2) - // Change in feature parameters. -#define MMCHS_HL_REV_X_MAJOR_S 8 -#define MMCHS_HL_REV_CUSTOM_M 0x000000C0 -#define MMCHS_HL_REV_CUSTOM_S 6 -#define MMCHS_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by - // IP specification owner. Y changes - // ONLY when: (1) Features are - // scaled (up or down). Flexibility - // exists in that this feature - // scalability may either be - // represented in the Y change or a - // specific register in the IP that - // indicates which features are - // exactly available. (2) When - // feature creeps from Is-Not list - // to Is list. But this may not be - // the case once it sees silicon; in - // which case X will change. Y does - // NOT change due to: (1) Bug fixes - // (2) Typos or clarifications (3) - // major functional/feature - // change/addition/deletion. Instead - // these changes may be reflected - // via R S X as applicable. Spec - // owner maintains a - // customer-invisible number 'S' - // which changes due to: (1) - // Typos/clarifications (2) Bug - // documentation. Note that this bug - // is not due to a spec change but - // due to implementation. - // Nevertheless the spec tracks the - // IP bugs. An RTL release (say for - // silicon PG1.1) that occurs due to - // bug fix should document the - // corresponding spec number (X.Y.S) - // in its release notes. -#define MMCHS_HL_REV_Y_MINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_HL_HWINFO register. -// -//****************************************************************************** -#define MMCHS_HL_HWINFO_RETMODE 0x00000040 -#define MMCHS_HL_HWINFO_MEM_SIZE_M \ - 0x0000003C - -#define MMCHS_HL_HWINFO_MEM_SIZE_S 2 -#define MMCHS_HL_HWINFO_MERGE_MEM \ - 0x00000002 - -#define MMCHS_HL_HWINFO_MADMA_EN \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// MMCHS_O_HL_SYSCONFIG register. -// -//****************************************************************************** -#define MMCHS_HL_SYSCONFIG_STANDBYMODE_M \ - 0x00000030 // Configuration of the local - // initiator state management mode. - // By definition initiator may - // generate read/write transaction - // as long as it is out of STANDBY - // state. 0x0 Force-standby mode: - // local initiator is - // unconditionally placed in standby - // state.Backup mode for debug only. - // 0x1 No-standby mode: local - // initiator is unconditionally - // placed out of standby - // state.Backup mode for debug only. - // 0x2 Smart-standby mode: local - // initiator standby status depends - // on local conditions i.e. the - // module's functional requirement - // from the initiator.IP module - // shall not generate - // (initiator-related) wakeup - // events. 0x3 "Smart-Standby - // wakeup-capable mode: local - // initiator standby status depends - // on local conditions i.e. the - // module's functional requirement - // from the initiator. IP module may - // generate (master-related) wakeup - // events when in standby state.Mode - // is only relevant if the - // appropriate IP module ""mwakeup"" - // output is implemented." - -#define MMCHS_HL_SYSCONFIG_STANDBYMODE_S 4 -#define MMCHS_HL_SYSCONFIG_IDLEMODE_M \ - 0x0000000C // Configuration of the local - // target state management mode. By - // definition target can handle - // read/write transaction as long as - // it is out of IDLE state. 0x0 - // Force-idle mode: local target's - // idle state follows (acknowledges) - // the system's idle requests - // unconditionally i.e. regardless - // of the IP module's internal - // requirements.Backup mode for - // debug only. 0x1 No-idle mode: - // local target never enters idle - // state.Backup mode for debug only. - // 0x2 Smart-idle mode: local - // target's idle state eventually - // follows (acknowledges) the - // system's idle requests depending - // on the IP module's internal - // requirements.IP module shall not - // generate (IRQ- or - // DMA-request-related) wakeup - // events. 0x3 "Smart-idle - // wakeup-capable mode: local - // target's idle state eventually - // follows (acknowledges) the - // system's idle requests depending - // on the IP module's internal - // requirements.IP module may - // generate (IRQ- or - // DMA-request-related) wakeup - // events when in idle state.Mode is - // only relevant if the appropriate - // IP module ""swakeup"" output(s) - // is (are) implemented." - -#define MMCHS_HL_SYSCONFIG_IDLEMODE_S 2 -#define MMCHS_HL_SYSCONFIG_FREEEMU \ - 0x00000002 // Sensitivity to emulation (debug) - // suspend input signal. - // Functionality NOT implemented in - // MMCHS. 0 IP module is sensitive - // to emulation suspend 1 IP module - // is not sensitive to emulation - // suspend - -#define MMCHS_HL_SYSCONFIG_SOFTRESET \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_SYSCONFIG register. -// -//****************************************************************************** -#define MMCHS_SYSCONFIG_STANDBYMODE_M \ - 0x00003000 // Master interface power - // Management standby/wait control. - // The bit field is only useful when - // generic parameter MADMA_EN - // (Master ADMA enable) is set as - // active otherwise it is a read - // only register read a '0'. 0x0 - // Force-standby. Mstandby is forced - // unconditionnaly. 0x1 No-standby. - // Mstandby is never asserted. 0x2 - // Smart-standby mode: local - // initiator standby status depends - // on local conditions i.e. the - // module's functional requirement - // from the initiator.IP module - // shall not generate - // (initiator-related) wakeup - // events. 0x3 Smart-Standby - // wakeup-capable mode: "local - // initiator standby status depends - // on local conditions i.e. the - // module's functional requirement - // from the initiator. IP module may - // generate (master-related) wakeup - // events when in standby state.Mode - // is only relevant if the - // appropriate IP module ""mwakeup"" - // output is implemented." - -#define MMCHS_SYSCONFIG_STANDBYMODE_S 12 -#define MMCHS_SYSCONFIG_CLOCKACTIVITY_M \ - 0x00000300 // Clocks activity during wake up - // mode period. Bit8: OCP interface - // clock Bit9: Functional clock 0x0 - // OCP and Functional clock may be - // switched off. 0x1 OCP clock is - // maintained. Functional clock may - // be switched-off. 0x2 Functional - // clock is maintained. OCP clock - // may be switched-off. 0x3 OCP and - // Functional clocks are maintained. - -#define MMCHS_SYSCONFIG_CLOCKACTIVITY_S 8 -#define MMCHS_SYSCONFIG_SIDLEMODE_M \ - 0x00000018 // Power management 0x0 If an idle - // request is detected the MMCHS - // acknowledges it unconditionally - // and goes in Inactive mode. - // Interrupt and DMA requests are - // unconditionally de-asserted. 0x1 - // If an idle request is detected - // the request is ignored and the - // module keeps on behaving - // normally. 0x2 Smart-idle mode: - // local target's idle state - // eventually follows (acknowledges) - // the system's idle requests - // depending on the IP module's - // internal requirements.IP module - // shall not generate (IRQ- or - // DMA-request-related) wakeup - // events. 0x3 Smart-idle - // wakeup-capable mode: "local - // target's idle state eventually - // follows (acknowledges) the - // system's idle requests depending - // on the IP module's internal - // requirements.IP module may - // generate (IRQ- or - // DMA-request-related) wakeup - // events when in idle state.Mode is - // only relevant if the appropriate - // IP module ""swakeup"" output(s) - // is (are) implemented." - -#define MMCHS_SYSCONFIG_SIDLEMODE_S 3 -#define MMCHS_SYSCONFIG_ENAWAKEUP \ - 0x00000004 // Wakeup feature control 0 Wakeup - // capability is disabled 1 Wakeup - // capability is enabled - -#define MMCHS_SYSCONFIG_SOFTRESET \ - 0x00000002 - -#define MMCHS_SYSCONFIG_AUTOIDLE \ - 0x00000001 // Internal Clock gating strategy 0 - // Clocks are free-running 1 - // Automatic clock gating strategy - // is applied based on the OCP and - // MMC interface activity - -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_SYSSTATUS register. -// -//****************************************************************************** -#define MMCHS_SYSSTATUS_RESETDONE \ - 0x00000001 - -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_CSRE register. -// -//****************************************************************************** -#define MMCHS_CSRE_CSRE_M 0xFFFFFFFF // Card status response error -#define MMCHS_CSRE_CSRE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_SYSTEST register. -// -//****************************************************************************** -#define MMCHS_SYSTEST_OBI 0x00010000 -#define MMCHS_SYSTEST_SDCD 0x00008000 -#define MMCHS_SYSTEST_SDWP 0x00004000 -#define MMCHS_SYSTEST_WAKD 0x00002000 -#define MMCHS_SYSTEST_SSB 0x00001000 -#define MMCHS_SYSTEST_D7D 0x00000800 -#define MMCHS_SYSTEST_D6D 0x00000400 -#define MMCHS_SYSTEST_D5D 0x00000200 -#define MMCHS_SYSTEST_D4D 0x00000100 -#define MMCHS_SYSTEST_D3D 0x00000080 -#define MMCHS_SYSTEST_D2D 0x00000040 -#define MMCHS_SYSTEST_D1D 0x00000020 -#define MMCHS_SYSTEST_D0D 0x00000010 -#define MMCHS_SYSTEST_DDIR 0x00000008 -#define MMCHS_SYSTEST_CDAT 0x00000004 -#define MMCHS_SYSTEST_CDIR 0x00000002 -#define MMCHS_SYSTEST_MCKD 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_CON register. -// -//****************************************************************************** -#define MMCHS_CON_SDMA_LNE 0x00200000 // Slave DMA Level/Edge Request: - // The waveform of the DMA request - // can be configured either edge - // sensitive with early de-assertion - // on first access to MMCHS_DATA - // register or late de-assertion - // request remains active until last - // allowed data written into - // MMCHS_DATA. 0 Slave DMA edge - // sensitive Early DMA de-assertion - // 1 Slave DMA level sensitive Late - // DMA de-assertion -#define MMCHS_CON_DMA_MNS 0x00100000 // DMA Master or Slave selection: - // When this bit is set and the - // controller is configured to use - // the DMA Ocp master interface is - // used to get datas from system - // using ADMA2 procedure (direct - // access to the memory).This option - // is only available if generic - // parameter MADMA_EN is asserted to - // '1'. 0 The controller is slave on - // data transfers with system. 1 The - // controller is master on data - // exchange with system controller - // must be configured as using DMA. -#define MMCHS_CON_DDR 0x00080000 // Dual Data Rate mode: When this - // register is set the controller - // uses both clock edge to emit or - // receive data. Odd bytes are - // transmitted on falling edges and - // even bytes are transmitted on - // rise edges. It only applies on - // Data bytes and CRC Start end bits - // and CRC status are kept full - // cycle. This bit field is only - // meaningful and active for even - // clock divider ratio of - // MMCHS_SYSCTL[CLKD] it is - // insensitive to MMCHS_HCTL[HSPE] - // setting. 0 Standard mode : data - // are transmitted on a single edge - // depending on MMCHS_HCTRL[HSPE]. 1 - // Data Bytes and CRC are - // transmitted on both edge. -#define MMCHS_CON_BOOT_CF0 0x00040000 -#define MMCHS_CON_BOOT_ACK 0x00020000 // Book acknowledge received: When - // this bit is set the controller - // should receive a boot status on - // DAT0 line after next command - // issued. If no status is received - // a data timeout will be generated. - // 0 No acknowledge to be received 1 - // A boot status will be received on - // DAT0 line after issuing a - // command. -#define MMCHS_CON_CLKEXTFREE 0x00010000 // External clock free running: - // This register is used to maintain - // card clock out of transfer - // transaction to enable slave - // module for example to generate a - // synchronous interrupt on DAT[1]. - // The Clock will be maintain only - // if MMCHS_SYSCTL[CEN] is set. 0 - // External card clock is cut off - // outside active transaction - // period. 1 External card clock is - // maintain even out of active - // transaction period only if - // MMCHS_SYSCTL[CEN] is set. -#define MMCHS_CON_PADEN 0x00008000 // Control Power for MMC Lines: - // This register is only useful when - // MMC PADs contain power saving - // mechanism to minimize its leakage - // power. It works as a GPIO that - // directly control the ACTIVE pin - // of PADs. Excepted for DAT[1] the - // signal is also combine outside - // the module with the dedicated - // power control MMCHS_CON[CTPL] - // bit. 0 ADPIDLE module pin is not - // forced it is automatically - // generated by the MMC fsms. 1 - // ADPIDLE module pin is forced to - // active state. -#define MMCHS_CON_OBIE 0x00004000 // Out-of-Band Interrupt Enable MMC - // cards only: This bit enables the - // detection of Out-of-Band - // Interrupt on MMCOBI input pin. - // The usage of the Out-of-Band - // signal (OBI) is optional and - // depends on the system - // integration. 0 Out-of-Band - // interrupt detection disabled 1 - // Out-of-Band interrupt detection - // enabled -#define MMCHS_CON_OBIP 0x00002000 // Out-of-Band Interrupt Polarity - // MMC cards only: This bit selects - // the active level of the - // out-of-band interrupt coming from - // MMC cards. The usage of the - // Out-of-Band signal (OBI) is - // optional and depends on the - // system integration. 0 active high - // level 1 active low level -#define MMCHS_CON_CEATA 0x00001000 // CE-ATA control mode MMC cards - // compliant with CE-ATA:By default - // this bit is set to 0. It is use - // to indicate that next commands - // are considered as specific CE-ATA - // commands that potentially use - // 'command completion' features. 0 - // Standard MMC/SD/SDIO mode. 1 - // CE-ATA mode next commands are - // considered as CE-ATA commands. -#define MMCHS_CON_CTPL 0x00000800 // Control Power for DAT[1] line - // MMC and SD cards: By default this - // bit is set to 0 and the host - // controller automatically disables - // all the input buffers outside of - // a transaction to minimize the - // leakage current. SDIO cards: When - // this bit is set to 1 the host - // controller automatically disables - // all the input buffers except the - // buffer of DAT[1] outside of a - // transaction in order to detect - // asynchronous card interrupt on - // DAT[1] line and minimize the - // leakage current of the buffers. 0 - // Disable all the input buffers - // outside of a transaction. 1 - // Disable all the input buffers - // except the buffer of DAT[1] - // outside of a transaction. -#define MMCHS_CON_DVAL_M 0x00000600 // Debounce filter value All cards - // This register is used to define a - // debounce period to filter the - // card detect input signal (SDCD). - // The usage of the card detect - // input signal (SDCD) is optional - // and depends on the system - // integration and the type of the - // connector housing that - // accommodates the card. 0x0 33 us - // debounce period 0x1 231 us - // debounce period 0x2 1 ms debounce - // period 0x3 84 ms debounce period -#define MMCHS_CON_DVAL_S 9 -#define MMCHS_CON_WPP 0x00000100 // Write protect polarity For SD - // and SDIO cards only This bit - // selects the active level of the - // write protect input signal - // (SDWP). The usage of the write - // protect input signal (SDWP) is - // optional and depends on the - // system integration and the type - // of the connector housing that - // accommodates the card. 0 active - // high level 1 active low level -#define MMCHS_CON_CDP 0x00000080 // Card detect polarity All cards - // This bit selects the active level - // of the card detect input signal - // (SDCD). The usage of the card - // detect input signal (SDCD) is - // optional and depends on the - // system integration and the type - // of the connector housing that - // accommodates the card. 0 active - // high level 1 active low level -#define MMCHS_CON_MIT 0x00000040 // MMC interrupt command Only for - // MMC cards. This bit must be set - // to 1 when the next write access - // to the command register - // (MMCHS_CMD) is for writing a MMC - // interrupt command (CMD40) - // requiring the command timeout - // detection to be disabled for the - // command response. 0 Command - // timeout enabled 1 Command timeout - // disabled -#define MMCHS_CON_DW8 0x00000020 // 8-bit mode MMC select For - // SD/SDIO cards this bit must be - // set to 0. For MMC card this bit - // must be set following a valid - // SWITCH command (CMD6) with the - // correct value and extend CSD - // index written in the argument. - // Prior to this command the MMC - // card configuration register (CSD - // and EXT_CSD) must be verified for - // compliancy with MMC standard - // specification 4.x (see section - // 3.6). 0 1-bit or 4-bit Data width - // (DAT[0] used MMC SD cards) 1 - // 8-bit Data width (DAT[7:0] used - // MMC cards) -#define MMCHS_CON_MODE 0x00000010 // Mode select All cards These bits - // select between Functional mode - // and SYSTEST mode. 0 Functional - // mode. Transfers to the - // MMC/SD/SDIO cards follow the card - // protocol. MMC clock is enabled. - // MMC/SD transfers are operated - // under the control of the CMD - // register. 1 SYSTEST mode The - // signal pins are configured as - // general-purpose input/output and - // the 1024-byte buffer is - // configured as a stack memory - // accessible only by the local host - // or system DMA. The pins retain - // their default type (input output - // or in-out). SYSTEST mode is - // operated under the control of the - // SYSTEST register. -#define MMCHS_CON_STR 0x00000008 // Stream command Only for MMC - // cards. This bit must be set to 1 - // only for the stream data - // transfers (read or write) of the - // adtc commands. Stream read is a - // class 1 command (CMD11: - // READ_DAT_UNTIL_STOP). Stream - // write is a class 3 command - // (CMD20: WRITE_DAT_UNTIL_STOP). 0 - // Block oriented data transfer 1 - // Stream oriented data transfer -#define MMCHS_CON_HR 0x00000004 // Broadcast host response Only for - // MMC cards. This register is used - // to force the host to generate a - // 48-bit response for bc command - // type. "It can be used to - // terminate the interrupt mode by - // generating a CMD40 response by - // the core (see section 4.3 - // ""Interrupt Mode"" in the MMC [1] - // specification). In order to have - // the host response to be generated - // in open drain mode the register - // MMCHS_CON[OD] must be set to 1." - // When MMCHS_CON[CEATA] is set to 1 - // and MMCHS_ARG set to 0x00000000 - // when writing 0x00000000 into - // MMCHS_CMD register the host - // controller performs a 'command - // completion signal disable' token - // i.e. CMD line held to '0' during - // 47 cycles followed by a 1. 0 The - // host does not generate a 48-bit - // response instead of a command. 1 - // The host generates a 48-bit - // response instead of a command or - // a command completion signal - // disable token. -#define MMCHS_CON_INIT 0x00000002 // Send initialization stream All - // cards. When this bit is set to 1 - // and the card is idle an - // initialization sequence is sent - // to the card. "An initialization - // sequence consists of setting the - // CMD line to 1 during 80 clock - // cycles. The initialisation - // sequence is mandatory - but it is - // not required to do it through - // this bit - this bit makes it - // easier. Clock divider - // (MMCHS_SYSCTL[CLKD]) should be - // set to ensure that 80 clock - // periods are greater than 1ms. - // (see section 9.3 ""Power-Up"" in - // the MMC card specification [1] or - // section 6.4 in the SD card - // specification [2])." Note: in - // this mode there is no command - // sent to the card and no response - // is expected 0 The host does not - // send an initialization sequence. - // 1 The host sends an - // initialization sequence. -#define MMCHS_CON_OD 0x00000001 // Card open drain mode. Only for - // MMC cards. This bit must be set - // to 1 for MMC card commands 1 2 3 - // and 40 and if the MMC card bus is - // operating in open-drain mode - // during the response phase to the - // command sent. Typically during - // card identification mode when the - // card is either in idle ready or - // ident state. It is also necessary - // to set this bit to 1 for a - // broadcast host response (see - // Broadcast host response register - // MMCHS_CON[HR]) 0 No Open Drain 1 - // Open Drain or Broadcast host - // response -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_PWCNT register. -// -//****************************************************************************** -#define MMCHS_PWCNT_PWRCNT_M 0x0000FFFF // Power counter register. This - // register is used to introduce a - // delay between the PAD ACTIVE pin - // assertion and the command issued. - // 0x0000 No additional delay added - // 0x0001 TCF delay (card clock - // period) 0x0002 TCF x 2 delay - // (card clock period) 0xFFFE TCF x - // 65534 delay (card clock period) - // 0xFFFF TCF x 65535 delay (card - // clock period) -#define MMCHS_PWCNT_PWRCNT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_BLK register. -// -//****************************************************************************** -#define MMCHS_BLK_NBLK_M 0xFFFF0000 // Blocks count for current - // transfer This register is enabled - // when Block count Enable - // (MMCHS_CMD[BCE]) is set to 1 and - // is valid only for multiple block - // transfers. Setting the block - // count to 0 results no data blocks - // being transferred. Note: The host - // controller decrements the block - // count after each block transfer - // and stops when the count reaches - // zero. This register can be - // accessed only if no transaction - // is executing (i.e after a - // transaction has stopped). Read - // operations during transfers may - // return an invalid value and write - // operation will be ignored. In - // suspend context the number of - // blocks yet to be transferred can - // be determined by reading this - // register. When restoring transfer - // context prior to issuing a Resume - // command The local host shall - // restore the previously saved - // block count. 0x0000 Stop count - // 0x0001 1 block 0x0002 2 blocks - // 0xFFFF 65535 blocks -#define MMCHS_BLK_NBLK_S 16 -#define MMCHS_BLK_BLEN_M 0x00000FFF // Transfer Block Size. This - // register specifies the block size - // for block data transfers. Read - // operations during transfers may - // return an invalid value and write - // operations are ignored. When a - // CMD12 command is issued to stop - // the transfer a read of the BLEN - // field after transfer completion - // (MMCHS_STAT[TC] set to 1) will - // not return the true byte number - // of data length while the stop - // occurs but the value written in - // this register before transfer is - // launched. 0x000 No data transfer - // 0x001 1 byte block length 0x002 2 - // bytes block length 0x003 3 bytes - // block length 0x1FF 511 bytes - // block length 0x200 512 bytes - // block length 0x7FF 2047 bytes - // block length 0x800 2048 bytes - // block length -#define MMCHS_BLK_BLEN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_ARG register. -// -//****************************************************************************** -#define MMCHS_ARG_ARG_M 0xFFFFFFFF // Command argument bits [31:0] -#define MMCHS_ARG_ARG_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_CMD register. -// -//****************************************************************************** -#define MMCHS_CMD_INDX_M 0x3F000000 // Command index Binary encoded - // value from 0 to 63 specifying the - // command number send to card 0x00 - // CMD0 or ACMD0 0x01 CMD1 or ACMD1 - // 0x02 CMD2 or ACMD2 0x03 CMD3 or - // ACMD3 0x04 CMD4 or ACMD4 0x05 - // CMD5 or ACMD5 0x06 CMD6 or ACMD6 - // 0x07 CMD7 or ACMD7 0x08 CMD8 or - // ACMD8 0x09 CMD9 or ACMD9 0x0A - // CMD10 or ACMD10 0x0B CMD11 or - // ACMD11 0x0C CMD12 or ACMD12 0x0D - // CMD13 or ACMD13 0x0E CMD14 or - // ACMD14 0x0F CMD15 or ACMD15 0x10 - // CMD16 or ACMD16 0x11 CMD17 or - // ACMD17 0x12 CMD18 or ACMD18 0x13 - // CMD19 or ACMD19 0x14 CMD20 or - // ACMD20 0x15 CMD21 or ACMD21 0x16 - // CMD22 or ACMD22 0x17 CMD23 or - // ACMD23 0x18 CMD24 or ACMD24 0x19 - // CMD25 or ACMD25 0x1A CMD26 or - // ACMD26 0x1B CMD27 or ACMD27 0x1C - // CMD28 or ACMD28 0x1D CMD29 or - // ACMD29 0x1E CMD30 or ACMD30 0x1F - // CMD31 or ACMD31 0x20 CMD32 or - // ACMD32 0x21 CMD33 or ACMD33 0x22 - // CMD34 or ACMD34 0x23 CMD35 or - // ACMD35 0x24 CMD36 or ACMD36 0x25 - // CMD37 or ACMD37 0x26 CMD38 or - // ACMD38 0x27 CMD39 or ACMD39 0x28 - // CMD40 or ACMD40 0x29 CMD41 or - // ACMD41 0x2A CMD42 or ACMD42 0x2B - // CMD43 or ACMD43 0x2C CMD44 or - // ACMD44 0x2D CMD45 or ACMD45 0x2E - // CMD46 or ACMD46 0x2F CMD47 or - // ACMD47 0x30 CMD48 or ACMD48 0x31 - // CMD49 or ACMD49 0x32 CMD50 or - // ACMD50 0x33 CMD51 or ACMD51 0x34 - // CMD52 or ACMD52 0x35 CMD53 or - // ACMD53 0x36 CMD54 or ACMD54 0x37 - // CMD55 or ACMD55 0x38 CMD56 or - // ACMD56 0x39 CMD57 or ACMD57 0x3A - // CMD58 or ACMD58 0x3B CMD59 or - // ACMD59 0x3C CMD60 or ACMD60 0x3D - // CMD61 or ACMD61 0x3E CMD62 or - // ACMD62 0x3F CMD63 or ACMD63 -#define MMCHS_CMD_INDX_S 24 -#define MMCHS_CMD_CMD_TYPE_M 0x00C00000 // Command type This register - // specifies three types of special - // command: Suspend Resume and - // Abort. These bits shall be set to - // 00b for all other commands. 0x0 - // Others Commands 0x1 "CMD52 for - // writing ""Bus Suspend"" in CCCR" - // 0x2 "CMD52 for writing ""Function - // Select"" in CCCR" 0x3 "Abort - // command CMD12 CMD52 for writing - // "" I/O Abort"" in CCCR" -#define MMCHS_CMD_CMD_TYPE_S 22 -#define MMCHS_CMD_DP 0x00200000 // Data present select This - // register indicates that data is - // present and DAT line shall be - // used. It must be set to 0 in the - // following conditions: - command - // using only CMD line - command - // with no data transfer but using - // busy signal on DAT[0] - Resume - // command 0 Command with no data - // transfer 1 Command with data - // transfer -#define MMCHS_CMD_CICE 0x00100000 // Command Index check enable This - // bit must be set to 1 to enable - // index check on command response - // to compare the index field in the - // response against the index of the - // command. If the index is not the - // same in the response as in the - // command it is reported as a - // command index error - // (MMCHS_STAT[CIE] set to1) Note: - // The register CICE cannot be - // configured for an Auto CMD12 then - // index check is automatically - // checked when this command is - // issued. 0 Index check disable 1 - // Index check enable -#define MMCHS_CMD_CCCE 0x00080000 // Command CRC check enable This - // bit must be set to 1 to enable - // CRC7 check on command response to - // protect the response against - // transmission errors on the bus. - // If an error is detected it is - // reported as a command CRC error - // (MMCHS_STAT[CCRC] set to 1). - // Note: The register CCCE cannot be - // configured for an Auto CMD12 and - // then CRC check is automatically - // checked when this command is - // issued. 0 CRC7 check disable 1 - // CRC7 check enable -#define MMCHS_CMD_RSP_TYPE_M 0x00030000 // Response type This bits defines - // the response type of the command - // 0x0 No response 0x1 Response - // Length 136 bits 0x2 Response - // Length 48 bits 0x3 Response - // Length 48 bits with busy after - // response -#define MMCHS_CMD_RSP_TYPE_S 16 -#define MMCHS_CMD_MSBS 0x00000020 // Multi/Single block select This - // bit must be set to 1 for data - // transfer in case of multi block - // command. For any others command - // this bit shall be set to 0. 0 - // Single block. If this bit is 0 it - // is not necessary to set the - // register MMCHS_BLK[NBLK]. 1 Multi - // block. When Block Count is - // disabled (MMCHS_CMD[BCE] is set - // to 0) in Multiple block transfers - // (MMCHS_CMD[MSBS] is set to 1) the - // module can perform infinite - // transfer. -#define MMCHS_CMD_DDIR 0x00000010 // Data transfer Direction Select - // This bit defines either data - // transfer will be a read or a - // write. 0 Data Write (host to - // card) 1 Data Read (card to host) -#define MMCHS_CMD_ACEN 0x00000004 // Auto CMD12 Enable SD card only. - // When this bit is set to 1 the - // host controller issues a CMD12 - // automatically after the transfer - // completion of the last block. The - // Host Driver shall not set this - // bit to issue commands that do not - // require CMD12 to stop data - // transfer. In particular secure - // commands do not require CMD12. 0 - // Auto CMD12 disable 1 Auto CMD12 - // enable or CCS detection enabled. -#define MMCHS_CMD_BCE 0x00000002 // Block Count Enable Multiple - // block transfers only. This bit is - // used to enable the block count - // register (MMCHS_BLK[NBLK]). When - // Block Count is disabled - // (MMCHS_CMD[BCE] is set to 0) in - // Multiple block transfers - // (MMCHS_CMD[MSBS] is set to 1) the - // module can perform infinite - // transfer. 0 Block count disabled - // for infinite transfer. 1 Block - // count enabled for multiple block - // transfer with known number of - // blocks -#define MMCHS_CMD_DE 0x00000001 // DMA Enable This bit is used to - // enable DMA mode for host data - // access. 0 DMA mode disable 1 DMA - // mode enable -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_RSP10 register. -// -//****************************************************************************** -#define MMCHS_RSP10_RSP1_M 0xFFFF0000 // Command Response [31:16] -#define MMCHS_RSP10_RSP1_S 16 -#define MMCHS_RSP10_RSP0_M 0x0000FFFF // Command Response [15:0] -#define MMCHS_RSP10_RSP0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_RSP32 register. -// -//****************************************************************************** -#define MMCHS_RSP32_RSP3_M 0xFFFF0000 // Command Response [63:48] -#define MMCHS_RSP32_RSP3_S 16 -#define MMCHS_RSP32_RSP2_M 0x0000FFFF // Command Response [47:32] -#define MMCHS_RSP32_RSP2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_RSP54 register. -// -//****************************************************************************** -#define MMCHS_RSP54_RSP5_M 0xFFFF0000 // Command Response [95:80] -#define MMCHS_RSP54_RSP5_S 16 -#define MMCHS_RSP54_RSP4_M 0x0000FFFF // Command Response [79:64] -#define MMCHS_RSP54_RSP4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_RSP76 register. -// -//****************************************************************************** -#define MMCHS_RSP76_RSP7_M 0xFFFF0000 // Command Response [127:112] -#define MMCHS_RSP76_RSP7_S 16 -#define MMCHS_RSP76_RSP6_M 0x0000FFFF // Command Response [111:96] -#define MMCHS_RSP76_RSP6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_DATA register. -// -//****************************************************************************** -#define MMCHS_DATA_DATA_M 0xFFFFFFFF // Data Register [31:0] In - // functional mode (MMCHS_CON[MODE] - // set to the default value 0) A - // read access to this register is - // allowed only when the buffer read - // enable status is set to 1 - // (MMCHS_PSTATE[BRE]) otherwise a - // bad access (MMCHS_STAT[BADA]) is - // signaled. A write access to this - // register is allowed only when the - // buffer write enable status is set - // to 1(MMCHS_STATE[BWE]) otherwise - // a bad access (MMCHS_STAT[BADA]) - // is signaled and the data is not - // written. -#define MMCHS_DATA_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_PSTATE register. -// -//****************************************************************************** -#define MMCHS_PSTATE_CLEV 0x01000000 -#define MMCHS_PSTATE_DLEV_M 0x00F00000 // DAT[3:0] line signal level - // DAT[3] => bit 23 DAT[2] => bit 22 - // DAT[1] => bit 21 DAT[0] => bit 20 - // This status is used to check DAT - // line level to recover from errors - // and for debugging. This is - // especially useful in detecting - // the busy signal level from - // DAT[0]. The value of these - // registers after reset depends on - // the DAT lines level at that time. -#define MMCHS_PSTATE_DLEV_S 20 -#define MMCHS_PSTATE_WP 0x00080000 -#define MMCHS_PSTATE_CDPL 0x00040000 -#define MMCHS_PSTATE_CSS 0x00020000 -#define MMCHS_PSTATE_CINS 0x00010000 -#define MMCHS_PSTATE_BRE 0x00000800 -#define MMCHS_PSTATE_BWE 0x00000400 -#define MMCHS_PSTATE_RTA 0x00000200 -#define MMCHS_PSTATE_WTA 0x00000100 -#define MMCHS_PSTATE_DLA 0x00000004 -#define MMCHS_PSTATE_DATI 0x00000002 -#define MMCHS_PSTATE_CMDI 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_HCTL register. -// -//****************************************************************************** -#define MMCHS_HCTL_OBWE 0x08000000 // Wakeup event enable for - // 'Out-of-Band' Interrupt. This bit - // enables wakeup events for - // 'Out-of-Band' assertion. Wakeup - // is generated if the wakeup - // feature is enabled - // (MMCHS_SYSCONFIG[ENAWAKEUP]). The - // write to this register is ignored - // when MMCHS_CON[OBIE] is not set. - // 0 Disable wakeup on 'Out-of-Band' - // Interrupt 1 Enable wakeup on - // 'Out-of-Band' Interrupt -#define MMCHS_HCTL_REM 0x04000000 // Wakeup event enable on SD card - // removal This bit enables wakeup - // events for card removal - // assertion. Wakeup is generated if - // the wakeup feature is enabled - // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 - // Disable wakeup on card removal 1 - // Enable wakeup on card removal -#define MMCHS_HCTL_INS 0x02000000 // Wakeup event enable on SD card - // insertion This bit enables wakeup - // events for card insertion - // assertion. Wakeup is generated if - // the wakeup feature is enabled - // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 - // Disable wakeup on card insertion - // 1 Enable wakeup on card insertion -#define MMCHS_HCTL_IWE 0x01000000 // Wakeup event enable on SD card - // interrupt This bit enables wakeup - // events for card interrupt - // assertion. Wakeup is generated if - // the wakeup feature is enabled - // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 - // Disable wakeup on card interrupt - // 1 Enable wakeup on card interrupt -#define MMCHS_HCTL_IBG 0x00080000 // Interrupt block at gap This bit - // is valid only in 4-bit mode of - // SDIO card to enable interrupt - // detection in the interrupt cycle - // at block gap for a multiple block - // transfer. For MMC cards and for - // SD card this bit should be set to - // 0. 0 Disable interrupt detection - // at the block gap in 4-bit mode 1 - // Enable interrupt detection at the - // block gap in 4-bit mode -#define MMCHS_HCTL_RWC 0x00040000 // Read wait control The read wait - // function is optional only for - // SDIO cards. If the card supports - // read wait this bit must be - // enabled then requesting a stop at - // block gap (MMCHS_HCTL[SBGR]) - // generates a read wait period - // after the current end of block. - // Be careful if read wait is not - // supported it may cause a conflict - // on DAT line. 0 Disable Read Wait - // Control. Suspend/Resume cannot be - // supported. 1 Enable Read Wait - // Control -#define MMCHS_HCTL_CR 0x00020000 // Continue request This bit is - // used to restart a transaction - // that was stopped by requesting a - // stop at block gap - // (MMCHS_HCTL[SBGR]). Set this bit - // to 1 restarts the transfer. The - // bit is automatically set to 0 by - // the host controller when transfer - // has restarted i.e DAT line is - // active (MMCHS_PSTATE[DLA]) or - // transferring data - // (MMCHS_PSTATE[WTA]). The Stop at - // block gap request must be - // disabled (MMCHS_HCTL[SBGR]=0) - // before setting this bit. 0 No - // affect 1 transfer restart -#define MMCHS_HCTL_SBGR 0x00010000 // Stop at block gap request This - // bit is used to stop executing a - // transaction at the next block - // gap. The transfer can restart - // with a continue request - // (MMHS_HCTL[CR]) or during a - // suspend/resume sequence. In case - // of read transfer the card must - // support read wait control. In - // case of write transfer the host - // driver shall set this bit after - // all block data written. Until the - // transfer completion - // (MMCHS_STAT[TC] set to 1) the - // host driver shall leave this bit - // set to 1. If this bit is set the - // local host shall not write to the - // data register (MMCHS_DATA). 0 - // Transfer mode 1 Stop at block gap -#define MMCHS_HCTL_SDVS_M 0x00000E00 // SD bus voltage select All cards. - // The host driver should set to - // these bits to select the voltage - // level for the card according to - // the voltage supported by the - // system (MMCHS_CAPA[VS18VS30VS33]) - // before starting a transfer. 0x5 - // 1.8V (Typical) 0x6 3.0V (Typical) - // 0x7 3.3V (Typical) -#define MMCHS_HCTL_SDVS_S 9 -#define MMCHS_HCTL_SDBP 0x00000100 // SD bus power Before setting this - // bit the host driver shall select - // the SD bus voltage - // (MMCHS_HCTL[SDVS]). If the host - // controller detects the No card - // state this bit is automatically - // set to 0. If the module is power - // off a write in the command - // register (MMCHS_CMD) will not - // start the transfer. A write to - // this bit has no effect if the - // selected SD bus voltage - // MMCHS_HCTL[SDVS] is not supported - // according to capability register - // (MMCHS_CAPA[VS*]). 0 Power off 1 - // Power on -#define MMCHS_HCTL_CDSS 0x00000080 // Card Detect Signal Selection - // This bit selects source for the - // card detection.When the source - // for the card detection is - // switched the interrupt should be - // disabled during the switching - // period by clearing the Interrupt - // Status/Signal Enable register in - // order to mask unexpected - // interrupt being caused by the - // glitch. The Interrupt - // Status/Signal Enable should be - // disabled during over the period - // of debouncing. 0 SDCD# is - // selected (for normal use) 1 The - // Card Detect Test Level is - // selected (for test purpose) -#define MMCHS_HCTL_CDTL 0x00000040 // Card Detect Test Level: This bit - // is enabled while the Card Detect - // Signal Selection is set to 1 and - // it indicates card inserted or - // not. 0 No Card 1 Card Inserted -#define MMCHS_HCTL_DMAS_M 0x00000018 // DMA Select Mode: One of - // supported DMA modes can be - // selected. The host driver shall - // check support of DMA modes by - // referring the Capabilities - // register. Use of selected DMA is - // determined by DMA Enable of the - // Transfer Mode register. This - // register is only meaningful when - // MADMA_EN is set to 1. When - // MADMA_EN is set to 0 the bit - // field is read only and returned - // value is 0. 0x0 Reserved 0x1 - // Reserved 0x2 32-bit Address ADMA2 - // is selected 0x3 Reserved -#define MMCHS_HCTL_DMAS_S 3 -#define MMCHS_HCTL_HSPE 0x00000004 // High Speed Enable: Before - // setting this bit the Host Driver - // shall check the High Speed - // Support in the Capabilities - // register. If this bit is set to 0 - // (default) the Host Controller - // outputs CMD line and DAT lines at - // the falling edge of the SD Clock. - // If this bit is set to 1 the Host - // Controller outputs CMD line and - // DAT lines at the rising edge of - // the SD Clock.This bit shall not - // be set when dual data rate mode - // is activated in MMCHS_CON[DDR]. 0 - // Normal speed mode 1 High speed - // mode -#define MMCHS_HCTL_DTW 0x00000002 // Data transfer width For MMC card - // this bit must be set following a - // valid SWITCH command (CMD6) with - // the correct value and extend CSD - // index written in the argument. - // Prior to this command the MMC - // card configuration register (CSD - // and EXT_CSD) must be verified for - // compliance with MMC standard - // specification 4.x (see section - // 3.6). This register has no effect - // when the MMC 8-bit mode is - // selected (register MMCHS_CON[DW8] - // set to1 ) For SD/SDIO cards this - // bit must be set following a valid - // SET_BUS_WIDTH command (ACMD6) - // with the value written in bit 1 - // of the argument. Prior to this - // command the SD card configuration - // register (SCR) must be verified - // for the supported bus width by - // the SD card. 0 1-bit Data width - // (DAT[0] used) 1 4-bit Data width - // (DAT[3:0] used) -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_SYSCTL register. -// -//****************************************************************************** -#define MMCHS_SYSCTL_SRD 0x04000000 // Software reset for DAT line This - // bit is set to 1 for reset and - // released to 0 when completed. DAT - // finite state machine in both - // clock domain are also reset. Here - // below are the registers cleared - // by MMCHS_SYSCTL[SRD]: #VALUE! - - // MMCHS_PSTATE: BRE BWE RTA WTA DLA - // and DATI - MMCHS_HCTL: SBGR and - // CR - MMCHS_STAT: BRR BWR BGE and - // TC OCP and MMC buffer data - // management is reinitialized. 0 - // Reset completed 1 Software reset - // for DAT line -#define MMCHS_SYSCTL_SRC 0x02000000 // Software reset for CMD line This - // bit is set to 1 for reset and - // released to 0 when completed. CMD - // finite state machine in both - // clock domain are also reset. Here - // below the registers cleared by - // MMCHS_SYSCTL[SRC]: - - // MMCHS_PSTATE: CMDI - MMCHS_STAT: - // CC OCP and MMC command status - // management is reinitialized. 0 - // Reset completed 1 Software reset - // for CMD line -#define MMCHS_SYSCTL_SRA 0x01000000 // Software reset for all This bit - // is set to 1 for reset and - // released to 0 when completed. - // This reset affects the entire - // host controller except for the - // card detection circuit and - // capabilities registers. 0 Reset - // completed 1 Software reset for - // all the design -#define MMCHS_SYSCTL_DTO_M 0x000F0000 // Data timeout counter value and - // busy timeout. This value - // determines the interval by which - // DAT lines timeouts are detected. - // The host driver needs to set this - // bitfield based on - the maximum - // read access time (NAC) (Refer to - // the SD Specification Part1 - // Physical Layer) - the data read - // access time values (TAAC and - // NSAC) in the card specific data - // register (CSD) of the card - the - // timeout clock base frequency - // (MMCHS_CAPA[TCF]). If the card - // does not respond within the - // specified number of cycles a data - // timeout error occurs - // (MMCHS_STA[DTO]). The - // MMCHS_SYSCTL[DTO] register is - // also used to check busy duration - // to generate busy timeout for - // commands with busy response or - // for busy programming during a - // write command. Timeout on CRC - // status is generated if no CRC - // token is present after a block - // write. 0x0 TCF x 2^13 0x1 TCF x - // 2^14 0xE TCF x 2^27 0xF Reserved -#define MMCHS_SYSCTL_DTO_S 16 -#define MMCHS_SYSCTL_CLKD_M 0x0000FFC0 // Clock frequency select These - // bits define the ratio between a - // reference clock frequency (system - // dependant) and the output clock - // frequency on the CLK pin of - // either the memory card (MMC SD or - // SDIO). 0x000 Clock Ref bypass - // 0x001 Clock Ref bypass 0x002 - // Clock Ref / 2 0x003 Clock Ref / 3 - // 0x3FF Clock Ref / 1023 -#define MMCHS_SYSCTL_CLKD_S 6 -#define MMCHS_SYSCTL_CEN 0x00000004 // Clock enable This bit controls - // if the clock is provided to the - // card or not. 0 The clock is not - // provided to the card . Clock - // frequency can be changed . 1 The - // clock is provided to the card and - // can be automatically gated when - // MMCHS_SYSCONFIG[AUTOIDLE] is set - // to 1 (default value) . The host - // driver shall wait to set this bit - // to 1 until the Internal clock is - // stable (MMCHS_SYSCTL[ICS]). -#define MMCHS_SYSCTL_ICS 0x00000002 -#define MMCHS_SYSCTL_ICE 0x00000001 // Internal clock enable This - // register controls the internal - // clock activity. In very low power - // state the internal clock is - // stopped. Note: The activity of - // the debounce clock (used for - // wakeup events) and the OCP clock - // (used for reads and writes to the - // module register map) are not - // affected by this register. 0 The - // internal clock is stopped (very - // low power state). 1 The internal - // clock oscillates and can be - // automatically gated when - // MMCHS_SYSCONFIG[AUTOIDLE] is set - // to 1 (default value) . -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_STAT register. -// -//****************************************************************************** -#define MMCHS_STAT_BADA 0x20000000 -#define MMCHS_STAT_CERR 0x10000000 -#define MMCHS_STAT_ADMAE 0x02000000 -#define MMCHS_STAT_ACE 0x01000000 -#define MMCHS_STAT_DEB 0x00400000 -#define MMCHS_STAT_DCRC 0x00200000 -#define MMCHS_STAT_DTO 0x00100000 -#define MMCHS_STAT_CIE 0x00080000 -#define MMCHS_STAT_CEB 0x00040000 -#define MMCHS_STAT_CCRC 0x00020000 -#define MMCHS_STAT_CTO 0x00010000 -#define MMCHS_STAT_ERRI 0x00008000 -#define MMCHS_STAT_BSR 0x00000400 -#define MMCHS_STAT_OBI 0x00000200 -#define MMCHS_STAT_CIRQ 0x00000100 -#define MMCHS_STAT_CREM 0x00000080 -#define MMCHS_STAT_CINS 0x00000040 -#define MMCHS_STAT_BRR 0x00000020 -#define MMCHS_STAT_BWR 0x00000010 -#define MMCHS_STAT_DMA 0x00000008 -#define MMCHS_STAT_BGE 0x00000004 -#define MMCHS_STAT_TC 0x00000002 -#define MMCHS_STAT_CC 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_IE register. -// -//****************************************************************************** -#define MMCHS_IE_BADA_ENABLE 0x20000000 // Bad access to data space - // Interrupt Enable 0 Masked 1 - // Enabled -#define MMCHS_IE_CERR_ENABLE 0x10000000 // Card error interrupt Enable 0 - // Masked 1 Enabled -#define MMCHS_IE_ADMAE_ENABLE 0x02000000 // ADMA error Interrupt Enable 0 - // Masked 1 Enabled -#define MMCHS_IE_ACE_ENABLE 0x01000000 // Auto CMD12 error Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_DEB_ENABLE 0x00400000 // Data end bit error Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_DCRC_ENABLE 0x00200000 // Data CRC error Interrupt Enable - // 0 Masked 1 Enabled -#define MMCHS_IE_DTO_ENABLE 0x00100000 // Data timeout error Interrupt - // Enable 0 The data timeout - // detection is deactivated. The - // host controller provides the - // clock to the card until the card - // sends the data or the transfer is - // aborted. 1 The data timeout - // detection is enabled. -#define MMCHS_IE_CIE_ENABLE 0x00080000 // Command index error Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_CEB_ENABLE 0x00040000 // Command end bit error Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_CCRC_ENABLE 0x00020000 // Command CRC error Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_CTO_ENABLE 0x00010000 // Command timeout error Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_NULL 0x00008000 // Fixed to 0 The host driver shall - // control error interrupts using - // the Error Interrupt Signal Enable - // register. Writes to this bit are - // ignored -#define MMCHS_IE_BSR_ENABLE 0x00000400 // Boot status interrupt Enable A - // write to this register when - // MMCHS_CON[BOOT_ACK] is set to 0x0 - // is ignored. 0 Masked 1 Enabled -#define MMCHS_IE_OBI_ENABLE 0x00000200 // Out-of-Band interrupt Enable A - // write to this register when - // MMCHS_CON[OBIE] is set to '0' is - // ignored. 0 Masked 1 Enabled -#define MMCHS_IE_CIRQ_ENABLE 0x00000100 // Card interrupt Enable A clear of - // this bit also clears the - // corresponding status bit. During - // 1-bit mode if the interrupt - // routine doesn't remove the source - // of a card interrupt in the SDIO - // card the status bit is reasserted - // when this bit is set to 1. 0 - // Masked 1 Enabled -#define MMCHS_IE_CREM_ENABLE 0x00000080 // Card removal Interrupt Enable 0 - // Masked 1 Enabled -#define MMCHS_IE_CINS_ENABLE 0x00000040 // Card insertion Interrupt Enable - // 0 Masked 1 Enabled -#define MMCHS_IE_BRR_ENABLE 0x00000020 // Buffer Read Ready Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_BWR_ENABLE 0x00000010 // Buffer Write Ready Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_DMA_ENABLE 0x00000008 // DMA interrupt Enable 0 Masked 1 - // Enabled -#define MMCHS_IE_BGE_ENABLE 0x00000004 // Block Gap Event Interrupt Enable - // 0 Masked 1 Enabled -#define MMCHS_IE_TC_ENABLE 0x00000002 // Transfer completed Interrupt - // Enable 0 Masked 1 Enabled -#define MMCHS_IE_CC_ENABLE 0x00000001 // Command completed Interrupt - // Enable 0 Masked 1 Enabled -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_ISE register. -// -//****************************************************************************** -#define MMCHS_ISE_BADA_SIGEN 0x20000000 // Bad access to data space signal - // status Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CERR_SIGEN 0x10000000 // Card error interrupt signal - // status Enable 0 Masked 1 Enabled -#define MMCHS_ISE_ADMAE_SIGEN 0x02000000 // ADMA error signal status Enable - // 0 Masked 1 Enabled -#define MMCHS_ISE_ACE_SIGEN 0x01000000 // Auto CMD12 error signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_DEB_SIGEN 0x00400000 // Data end bit error signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_DCRC_SIGEN 0x00200000 // Data CRC error signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_DTO_SIGEN 0x00100000 // Data timeout error signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CIE_SIGEN 0x00080000 // Command index error signal - // status Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CEB_SIGEN 0x00040000 // Command end bit error signal - // status Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CCRC_SIGEN 0x00020000 // Command CRC error signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CTO_SIGEN 0x00010000 // Command timeout error signal - // status Enable 0 Masked 1 Enabled -#define MMCHS_ISE_NULL 0x00008000 // Fixed to 0 The host driver shall - // control error interrupts using - // the Error Interrupt Signal Enable - // register. Writes to this bit are - // ignored -#define MMCHS_ISE_BSR_SIGEN 0x00000400 // Boot status signal status - // EnableA write to this register - // when MMCHS_CON[BOOT_ACK] is set - // to 0x0 is ignored. 0 Masked 1 - // Enabled -#define MMCHS_ISE_OBI_SIGEN 0x00000200 // Out-Of-Band Interrupt signal - // status Enable A write to this - // register when MMCHS_CON[OBIE] is - // set to '0' is ignored. 0 Masked 1 - // Enabled -#define MMCHS_ISE_CIRQ_SIGEN 0x00000100 // Card interrupt signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CREM_SIGEN 0x00000080 // Card removal signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CINS_SIGEN 0x00000040 // Card insertion signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_BRR_SIGEN 0x00000020 // Buffer Read Ready signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_BWR_SIGEN 0x00000010 // Buffer Write Ready signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_DMA_SIGEN 0x00000008 // DMA interrupt Signal status - // enable 0 Masked 1 Enabled -#define MMCHS_ISE_BGE_SIGEN 0x00000004 // Black Gap Event signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_TC_SIGEN 0x00000002 // Transfer completed signal status - // Enable 0 Masked 1 Enabled -#define MMCHS_ISE_CC_SIGEN 0x00000001 // Command completed signal status - // Enable 0 Masked 1 Enabled -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_AC12 register. -// -//****************************************************************************** -#define MMCHS_AC12_CNI 0x00000080 -#define MMCHS_AC12_ACIE 0x00000010 -#define MMCHS_AC12_ACEB 0x00000008 -#define MMCHS_AC12_ACCE 0x00000004 -#define MMCHS_AC12_ACTO 0x00000002 -#define MMCHS_AC12_ACNE 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_CAPA register. -// -//****************************************************************************** -#define MMCHS_CAPA_BIT64 0x10000000 -#define MMCHS_CAPA_VS18 0x04000000 -#define MMCHS_CAPA_VS30 0x02000000 -#define MMCHS_CAPA_VS33 0x01000000 -#define MMCHS_CAPA_SRS 0x00800000 -#define MMCHS_CAPA_DS 0x00400000 -#define MMCHS_CAPA_HSS 0x00200000 -#define MMCHS_CAPA_AD2S 0x00080000 -#define MMCHS_CAPA_MBL_M 0x00030000 -#define MMCHS_CAPA_MBL_S 16 -#define MMCHS_CAPA_BCF_M 0x00003F00 -#define MMCHS_CAPA_BCF_S 8 -#define MMCHS_CAPA_TCU 0x00000080 -#define MMCHS_CAPA_TCF_M 0x0000003F -#define MMCHS_CAPA_TCF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_CUR_CAPA register. -// -//****************************************************************************** -#define MMCHS_CUR_CAPA_CUR_1V8_M \ - 0x00FF0000 - -#define MMCHS_CUR_CAPA_CUR_1V8_S 16 -#define MMCHS_CUR_CAPA_CUR_3V0_M \ - 0x0000FF00 - -#define MMCHS_CUR_CAPA_CUR_3V0_S 8 -#define MMCHS_CUR_CAPA_CUR_3V3_M \ - 0x000000FF - -#define MMCHS_CUR_CAPA_CUR_3V3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_FE register. -// -//****************************************************************************** -#define MMCHS_FE_FE_BADA 0x20000000 -#define MMCHS_FE_FE_CERR 0x10000000 -#define MMCHS_FE_FE_ADMAE 0x02000000 -#define MMCHS_FE_FE_ACE 0x01000000 -#define MMCHS_FE_FE_DEB 0x00400000 -#define MMCHS_FE_FE_DCRC 0x00200000 -#define MMCHS_FE_FE_DTO 0x00100000 -#define MMCHS_FE_FE_CIE 0x00080000 -#define MMCHS_FE_FE_CEB 0x00040000 -#define MMCHS_FE_FE_CCRC 0x00020000 -#define MMCHS_FE_FE_CTO 0x00010000 -#define MMCHS_FE_FE_CNI 0x00000080 -#define MMCHS_FE_FE_ACIE 0x00000010 -#define MMCHS_FE_FE_ACEB 0x00000008 -#define MMCHS_FE_FE_ACCE 0x00000004 -#define MMCHS_FE_FE_ACTO 0x00000002 -#define MMCHS_FE_FE_ACNE 0x00000001 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_ADMAES register. -// -//****************************************************************************** -#define MMCHS_ADMAES_LME 0x00000004 // ADMA Length Mismatch Error: (1) - // While Block Count Enable being - // set the total data length - // specified by the Descriptor table - // is different from that specified - // by the Block Count and Block - // Length. (2) Total data length can - // not be divided by the block - // length. 0 No Error 1 Error -#define MMCHS_ADMAES_AES_M 0x00000003 // ADMA Error State his field - // indicates the state of ADMA when - // error is occurred during ADMA - // data transfer. "This field never - // indicates ""10"" because ADMA - // never stops in this state." 0x0 - // ST_STOP (Stop DMA)Contents of - // SYS_SDR register 0x1 ST_STOP - // (Stop DMA)Points the error - // descriptor 0x2 Never set this - // state(Not used) 0x3 ST_TFR - // (Transfer Data)Points the next of - // the error descriptor -#define MMCHS_ADMAES_AES_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_ADMASAL register. -// -//****************************************************************************** -#define MMCHS_ADMASAL_ADMA_A32B_M \ - 0xFFFFFFFF // ADMA System address 32 bits.This - // register holds byte address of - // executing command of the - // Descriptor table. 32-bit Address - // Descriptor uses lower 32-bit of - // this register. At the start of - // ADMA the Host Driver shall set - // start address of the Descriptor - // table. The ADMA increments this - // register address which points to - // next line when every fetching a - // Descriptor line. When the ADMA - // Error Interrupt is generated this - // register shall hold valid - // Descriptor address depending on - // the ADMA state. The Host Driver - // shall program Descriptor Table on - // 32-bit boundary and set 32-bit - // boundary address to this - // register. ADMA2 ignores lower - // 2-bit of this register and - // assumes it to be 00b. - -#define MMCHS_ADMASAL_ADMA_A32B_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the MMCHS_O_REV register. -// -//****************************************************************************** -#define MMCHS_REV_VREV_M 0xFF000000 // Vendor Version Number: IP - // revision [7:4] Major revision - // [3:0] Minor revision Examples: - // 0x10 for 1.0 0x21 for 2.1 -#define MMCHS_REV_VREV_S 24 -#define MMCHS_REV_SREV_M 0x00FF0000 -#define MMCHS_REV_SREV_S 16 -#define MMCHS_REV_SIS 0x00000001 // Slot Interrupt Status This - // status bit indicates the inverted - // state of interrupt signal for the - // module. By a power on reset or by - // setting a software reset for all - // (MMCHS_HCTL[SRA]) the interrupt - // signal shall be de-asserted and - // this status shall read 0. - - - -#endif // __HW_MMCHS_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_nvic.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_nvic.h deleted file mode 100644 index c8c0c88fa34..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_nvic.h +++ /dev/null @@ -1,1708 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -//***************************************************************************** -// -// hw_nvic.h - Macros used when accessing the NVIC hardware. -// -//***************************************************************************** - -#ifndef __HW_NVIC_H__ -#define __HW_NVIC_H__ - -//***************************************************************************** -// -// The following are defines for the NVIC register addresses. -// -//***************************************************************************** -#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg -#define NVIC_ACTLR 0xE000E008 // Auxiliary Control -#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status - // Register -#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register -#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register -#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg - -#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable -#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable -#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable -#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable -#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable -#define NVIC_EN5 0xE000E114 // Interrupt 160-191 Set Enable - -#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable -#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable - -#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable -#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable -#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable -#define NVIC_DIS5 0xE000E194 // Interrupt 160-191 Clear Enable - -#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending -#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending - -#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending -#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending -#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending -#define NVIC_PEND5 0xE000E214 // Interrupt 160-191 Set Pending - -#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending -#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending - -#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending -#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending -#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending -#define NVIC_UNPEND5 0xE000E294 // Interrupt 160-191 Clear Pending - -#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit -#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit - -#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit -#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit -#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit -#define NVIC_ACTIVE5 0xE000E314 // Interrupt 160-191 Active Bit - -#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority -#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority -#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority -#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority -#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority -#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority -#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority -#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority -#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority -#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority -#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority -#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority -#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority -#define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority - -#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority -#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority -#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority -#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority -#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority -#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority -#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority -#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority -#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority -#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority -#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority -#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority -#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority -#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority -#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority -#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority -#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority -#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority -#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority -#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority -#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority -#define NVIC_PRI35 0xE000E48C // Interrupt 140-143 Priority -#define NVIC_PRI36 0xE000E490 // Interrupt 144-147 Priority -#define NVIC_PRI37 0xE000E494 // Interrupt 148-151 Priority -#define NVIC_PRI38 0xE000E498 // Interrupt 152-155 Priority -#define NVIC_PRI39 0xE000E49C // Interrupt 156-159 Priority -#define NVIC_PRI40 0xE000E4A0 // Interrupt 160-163 Priority -#define NVIC_PRI41 0xE000E4A4 // Interrupt 164-167 Priority -#define NVIC_PRI42 0xE000E4A8 // Interrupt 168-171 Priority -#define NVIC_PRI43 0xE000E4AC // Interrupt 172-175 Priority -#define NVIC_PRI44 0xE000E4B0 // Interrupt 176-179 Priority -#define NVIC_PRI45 0xE000E4B4 // Interrupt 180-183 Priority -#define NVIC_PRI46 0xE000E4B8 // Interrupt 184-187 Priority -#define NVIC_PRI47 0xE000E4BC // Interrupt 188-191 Priority -#define NVIC_PRI48 0xE000E4C0 // Interrupt 192-195 Priority - - - -#define NVIC_CPUID 0xE000ED00 // CPU ID Base -#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State -#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset -#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset - // Control -#define NVIC_SYS_CTRL 0xE000ED10 // System Control -#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control -#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 -#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 -#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 -#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State -#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status -#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status -#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register -#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address -#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address -#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type -#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control -#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number -#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address -#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size -#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 -#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size - // Alias 1 -#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 -#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size - // Alias 2 -#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 -#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size - // Alias 3 -#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg -#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select -#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data -#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control -#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_TYPE register. -// -//***************************************************************************** -#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) -#define NVIC_INT_TYPE_LINES_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTLR register. -// -//***************************************************************************** -#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding -#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer -#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple - // Cycle Instructions - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CTRL register. -// -//***************************************************************************** -#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag -#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source -#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable -#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_RELOAD register. -// -//***************************************************************************** -#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value -#define NVIC_ST_RELOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CURRENT -// register. -// -//***************************************************************************** -#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value -#define NVIC_ST_CURRENT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ST_CAL register. -// -//***************************************************************************** -#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock -#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew -#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value -#define NVIC_ST_CAL_ONEMS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN0 register. -// -//***************************************************************************** -#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable -#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable -#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable -#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable -#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable -#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable -#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable -#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable -#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable -#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable -#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable -#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable -#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable -#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable -#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable -#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable -#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable -#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable -#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable -#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable -#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable -#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable -#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable -#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable -#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable -#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable -#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable -#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable -#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable -#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable -#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable -#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable -#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN1 register. -// -//***************************************************************************** -#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable - -#undef NVIC_EN1_INT_M -#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable - -#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable -#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable -#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable -#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable -#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable -#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable -#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable -#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable -#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable -#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable -#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable -#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable -#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable -#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable -#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable -#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable -#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable -#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable -#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable -#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable -#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable -#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable -#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN2 register. -// -//***************************************************************************** -#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN3 register. -// -//***************************************************************************** -#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_EN4 register. -// -//***************************************************************************** -#define NVIC_EN4_INT_M 0x0000000F // Interrupt Enable - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS0 register. -// -//***************************************************************************** -#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable -#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable -#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable -#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable -#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable -#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable -#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable -#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable -#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable -#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable -#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable -#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable -#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable -#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable -#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable -#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable -#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable -#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable -#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable -#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable -#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable -#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable -#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable -#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable -#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable -#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable -#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable -#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable -#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable -#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable -#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable -#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable -#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS1 register. -// -//***************************************************************************** -#define NVIC_DIS1_INT_M 0x00FFFFFF // Interrupt Disable - -#undef NVIC_DIS1_INT_M -#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable - -#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable -#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable -#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable -#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable -#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable -#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable -#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable -#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable -#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable -#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable -#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable -#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable -#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable -#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable -#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable -#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable -#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable -#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable -#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable -#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable -#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable -#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable -#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable -#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS2 register. -// -//***************************************************************************** -#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS3 register. -// -//***************************************************************************** -#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DIS4 register. -// -//***************************************************************************** -#define NVIC_DIS4_INT_M 0x0000000F // Interrupt Disable - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND0 register. -// -//***************************************************************************** -#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending -#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend -#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend -#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend -#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend -#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend -#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend -#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend -#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend -#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend -#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend -#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend -#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend -#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend -#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend -#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend -#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend -#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend -#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend -#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend -#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend -#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend -#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend -#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend -#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend -#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend -#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend -#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend -#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend -#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend -#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend -#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend -#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND1 register. -// -//***************************************************************************** -#define NVIC_PEND1_INT_M 0x00FFFFFF // Interrupt Set Pending - -#undef NVIC_PEND1_INT_M -#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending - -#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend -#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend -#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend -#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend -#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend -#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend -#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend -#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend -#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend -#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend -#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend -#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend -#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend -#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend -#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend -#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend -#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend -#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend -#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend -#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend -#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend -#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend -#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend -#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND2 register. -// -//***************************************************************************** -#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND3 register. -// -//***************************************************************************** -#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PEND4 register. -// -//***************************************************************************** -#define NVIC_PEND4_INT_M 0x0000000F // Interrupt Set Pending - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND0 register. -// -//***************************************************************************** -#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending -#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend -#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend -#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend -#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend -#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend -#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend -#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend -#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend -#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend -#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend -#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend -#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend -#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend -#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend -#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend -#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend -#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend -#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend -#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend -#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend -#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend -#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend -#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend -#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend -#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend -#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend -#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend -#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend -#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend -#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend -#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend -#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND1 register. -// -//***************************************************************************** -#define NVIC_UNPEND1_INT_M 0x00FFFFFF // Interrupt Clear Pending - -#undef NVIC_UNPEND1_INT_M -#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend -#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend -#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend -#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend -#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend -#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend -#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend -#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend -#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend -#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend -#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend -#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend -#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend -#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend -#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend -#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend -#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend -#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend -#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend -#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend -#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend -#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend -#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend -#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND2 register. -// -//***************************************************************************** -#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND3 register. -// -//***************************************************************************** -#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_UNPEND4 register. -// -//***************************************************************************** -#define NVIC_UNPEND4_INT_M 0x0000000F // Interrupt Clear Pending - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE0 register. -// -//***************************************************************************** -#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active -#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active -#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active -#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active -#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active -#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active -#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active -#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active -#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active -#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active -#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active -#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active -#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active -#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active -#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active -#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active -#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active -#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active -#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active -#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active -#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active -#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active -#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active -#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active -#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active -#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active -#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active -#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active -#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active -#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active -#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active -#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active -#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE1 register. -// -//***************************************************************************** -#define NVIC_ACTIVE1_INT_M 0x00FFFFFF // Interrupt Active - -#undef NVIC_ACTIVE1_INT_M -#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active - -#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active -#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active -#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active -#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active -#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active -#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active -#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active -#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active -#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active -#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active -#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active -#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active -#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active -#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active -#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active -#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active -#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active -#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active -#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active -#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active -#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active -#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active -#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active -#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE2 register. -// -//***************************************************************************** -#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE3 register. -// -//***************************************************************************** -#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_ACTIVE4 register. -// -//***************************************************************************** -#define NVIC_ACTIVE4_INT_M 0x0000000F // Interrupt Active - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI0 register. -// -//***************************************************************************** -#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask -#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask -#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask -#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask -#define NVIC_PRI0_INT3_S 29 -#define NVIC_PRI0_INT2_S 21 -#define NVIC_PRI0_INT1_S 13 -#define NVIC_PRI0_INT0_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI1 register. -// -//***************************************************************************** -#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask -#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask -#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask -#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask -#define NVIC_PRI1_INT7_S 29 -#define NVIC_PRI1_INT6_S 21 -#define NVIC_PRI1_INT5_S 13 -#define NVIC_PRI1_INT4_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI2 register. -// -//***************************************************************************** -#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask -#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask -#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask -#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask -#define NVIC_PRI2_INT11_S 29 -#define NVIC_PRI2_INT10_S 21 -#define NVIC_PRI2_INT9_S 13 -#define NVIC_PRI2_INT8_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI3 register. -// -//***************************************************************************** -#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask -#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask -#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask -#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask -#define NVIC_PRI3_INT15_S 29 -#define NVIC_PRI3_INT14_S 21 -#define NVIC_PRI3_INT13_S 13 -#define NVIC_PRI3_INT12_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI4 register. -// -//***************************************************************************** -#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask -#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask -#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask -#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask -#define NVIC_PRI4_INT19_S 29 -#define NVIC_PRI4_INT18_S 21 -#define NVIC_PRI4_INT17_S 13 -#define NVIC_PRI4_INT16_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI5 register. -// -//***************************************************************************** -#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask -#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask -#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask -#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask -#define NVIC_PRI5_INT23_S 29 -#define NVIC_PRI5_INT22_S 21 -#define NVIC_PRI5_INT21_S 13 -#define NVIC_PRI5_INT20_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI6 register. -// -//***************************************************************************** -#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask -#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask -#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask -#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask -#define NVIC_PRI6_INT27_S 29 -#define NVIC_PRI6_INT26_S 21 -#define NVIC_PRI6_INT25_S 13 -#define NVIC_PRI6_INT24_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI7 register. -// -//***************************************************************************** -#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask -#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask -#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask -#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask -#define NVIC_PRI7_INT31_S 29 -#define NVIC_PRI7_INT30_S 21 -#define NVIC_PRI7_INT29_S 13 -#define NVIC_PRI7_INT28_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI8 register. -// -//***************************************************************************** -#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask -#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask -#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask -#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask -#define NVIC_PRI8_INT35_S 29 -#define NVIC_PRI8_INT34_S 21 -#define NVIC_PRI8_INT33_S 13 -#define NVIC_PRI8_INT32_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI9 register. -// -//***************************************************************************** -#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask -#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask -#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask -#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask -#define NVIC_PRI9_INT39_S 29 -#define NVIC_PRI9_INT38_S 21 -#define NVIC_PRI9_INT37_S 13 -#define NVIC_PRI9_INT36_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI10 register. -// -//***************************************************************************** -#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask -#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask -#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask -#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask -#define NVIC_PRI10_INT43_S 29 -#define NVIC_PRI10_INT42_S 21 -#define NVIC_PRI10_INT41_S 13 -#define NVIC_PRI10_INT40_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI11 register. -// -//***************************************************************************** -#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask -#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask -#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask -#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask -#define NVIC_PRI11_INT47_S 29 -#define NVIC_PRI11_INT46_S 21 -#define NVIC_PRI11_INT45_S 13 -#define NVIC_PRI11_INT44_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI12 register. -// -//***************************************************************************** -#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask -#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask -#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask -#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask -#define NVIC_PRI12_INT51_S 29 -#define NVIC_PRI12_INT50_S 21 -#define NVIC_PRI12_INT49_S 13 -#define NVIC_PRI12_INT48_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI13 register. -// -//***************************************************************************** -#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask -#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask -#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask -#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask -#define NVIC_PRI13_INT55_S 29 -#define NVIC_PRI13_INT54_S 21 -#define NVIC_PRI13_INT53_S 13 -#define NVIC_PRI13_INT52_S 5 - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI14 register. -// -//***************************************************************************** -#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask -#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask -#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask -#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask -#define NVIC_PRI14_INTD_S 29 -#define NVIC_PRI14_INTC_S 21 -#define NVIC_PRI14_INTB_S 13 -#define NVIC_PRI14_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI15 register. -// -//***************************************************************************** -#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask -#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask -#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask -#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask -#define NVIC_PRI15_INTD_S 29 -#define NVIC_PRI15_INTC_S 21 -#define NVIC_PRI15_INTB_S 13 -#define NVIC_PRI15_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI16 register. -// -//***************************************************************************** -#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask -#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask -#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask -#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask -#define NVIC_PRI16_INTD_S 29 -#define NVIC_PRI16_INTC_S 21 -#define NVIC_PRI16_INTB_S 13 -#define NVIC_PRI16_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI17 register. -// -//***************************************************************************** -#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask -#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask -#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask -#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask -#define NVIC_PRI17_INTD_S 29 -#define NVIC_PRI17_INTC_S 21 -#define NVIC_PRI17_INTB_S 13 -#define NVIC_PRI17_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI18 register. -// -//***************************************************************************** -#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask -#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask -#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask -#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask -#define NVIC_PRI18_INTD_S 29 -#define NVIC_PRI18_INTC_S 21 -#define NVIC_PRI18_INTB_S 13 -#define NVIC_PRI18_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI19 register. -// -//***************************************************************************** -#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask -#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask -#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask -#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask -#define NVIC_PRI19_INTD_S 29 -#define NVIC_PRI19_INTC_S 21 -#define NVIC_PRI19_INTB_S 13 -#define NVIC_PRI19_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI20 register. -// -//***************************************************************************** -#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask -#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask -#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask -#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask -#define NVIC_PRI20_INTD_S 29 -#define NVIC_PRI20_INTC_S 21 -#define NVIC_PRI20_INTB_S 13 -#define NVIC_PRI20_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI21 register. -// -//***************************************************************************** -#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask -#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask -#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask -#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask -#define NVIC_PRI21_INTD_S 29 -#define NVIC_PRI21_INTC_S 21 -#define NVIC_PRI21_INTB_S 13 -#define NVIC_PRI21_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI22 register. -// -//***************************************************************************** -#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask -#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask -#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask -#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask -#define NVIC_PRI22_INTD_S 29 -#define NVIC_PRI22_INTC_S 21 -#define NVIC_PRI22_INTB_S 13 -#define NVIC_PRI22_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI23 register. -// -//***************************************************************************** -#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask -#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask -#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask -#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask -#define NVIC_PRI23_INTD_S 29 -#define NVIC_PRI23_INTC_S 21 -#define NVIC_PRI23_INTB_S 13 -#define NVIC_PRI23_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI24 register. -// -//***************************************************************************** -#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask -#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask -#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask -#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask -#define NVIC_PRI24_INTD_S 29 -#define NVIC_PRI24_INTC_S 21 -#define NVIC_PRI24_INTB_S 13 -#define NVIC_PRI24_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI25 register. -// -//***************************************************************************** -#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask -#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask -#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask -#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask -#define NVIC_PRI25_INTD_S 29 -#define NVIC_PRI25_INTC_S 21 -#define NVIC_PRI25_INTB_S 13 -#define NVIC_PRI25_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI26 register. -// -//***************************************************************************** -#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask -#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask -#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask -#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask -#define NVIC_PRI26_INTD_S 29 -#define NVIC_PRI26_INTC_S 21 -#define NVIC_PRI26_INTB_S 13 -#define NVIC_PRI26_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI27 register. -// -//***************************************************************************** -#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask -#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask -#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask -#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask -#define NVIC_PRI27_INTD_S 29 -#define NVIC_PRI27_INTC_S 21 -#define NVIC_PRI27_INTB_S 13 -#define NVIC_PRI27_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI28 register. -// -//***************************************************************************** -#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask -#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask -#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask -#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask -#define NVIC_PRI28_INTD_S 29 -#define NVIC_PRI28_INTC_S 21 -#define NVIC_PRI28_INTB_S 13 -#define NVIC_PRI28_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI29 register. -// -//***************************************************************************** -#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask -#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask -#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask -#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask -#define NVIC_PRI29_INTD_S 29 -#define NVIC_PRI29_INTC_S 21 -#define NVIC_PRI29_INTB_S 13 -#define NVIC_PRI29_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI30 register. -// -//***************************************************************************** -#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask -#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask -#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask -#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask -#define NVIC_PRI30_INTD_S 29 -#define NVIC_PRI30_INTC_S 21 -#define NVIC_PRI30_INTB_S 13 -#define NVIC_PRI30_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI31 register. -// -//***************************************************************************** -#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask -#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask -#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask -#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask -#define NVIC_PRI31_INTD_S 29 -#define NVIC_PRI31_INTC_S 21 -#define NVIC_PRI31_INTB_S 13 -#define NVIC_PRI31_INTA_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_PRI32 register. -// -//***************************************************************************** -#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask -#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask -#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask -#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask -#define NVIC_PRI32_INTD_S 29 -#define NVIC_PRI32_INTC_S 21 -#define NVIC_PRI32_INTB_S 13 -#define NVIC_PRI32_INTA_S 5 - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CPUID register. -// -//***************************************************************************** -#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code -#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM -#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number -#define NVIC_CPUID_CON_M 0x000F0000 // Constant -#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number -#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor - -#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor - -#define NVIC_CPUID_REV_M 0x0000000F // Revision Number - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_INT_CTRL register. -// -//***************************************************************************** -#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending -#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending -#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending -#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending -#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending -#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling -#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending -#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number - -#undef NVIC_INT_CTRL_VEC_PEN_M -#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number - -#define NVIC_INT_CTRL_VEC_PEN_NMI \ - 0x00002000 // NMI -#define NVIC_INT_CTRL_VEC_PEN_HARD \ - 0x00003000 // Hard fault -#define NVIC_INT_CTRL_VEC_PEN_MEM \ - 0x00004000 // Memory management fault -#define NVIC_INT_CTRL_VEC_PEN_BUS \ - 0x00005000 // Bus fault -#define NVIC_INT_CTRL_VEC_PEN_USG \ - 0x00006000 // Usage fault -#define NVIC_INT_CTRL_VEC_PEN_SVC \ - 0x0000B000 // SVCall -#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ - 0x0000E000 // PendSV -#define NVIC_INT_CTRL_VEC_PEN_TICK \ - 0x0000F000 // SysTick -#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base -#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number - -#undef NVIC_INT_CTRL_VEC_ACT_M -#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number - -#define NVIC_INT_CTRL_VEC_PEN_S 12 -#define NVIC_INT_CTRL_VEC_ACT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_VTABLE register. -// -//***************************************************************************** -#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base -#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset - -#undef NVIC_VTABLE_OFFSET_M -#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset - -#define NVIC_VTABLE_OFFSET_S 9 - -#undef NVIC_VTABLE_OFFSET_S -#define NVIC_VTABLE_OFFSET_S 10 - - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_APINT register. -// -//***************************************************************************** -#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key -#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key -#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request -#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault -#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_CTRL register. -// -//***************************************************************************** -#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending -#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable -#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_CFG_CTRL register. -// -//***************************************************************************** -#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception - // Entry -#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and - // Fault -#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 -#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access -#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger -#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority -#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority -#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority -#define NVIC_SYS_PRI1_USAGE_S 21 -#define NVIC_SYS_PRI1_BUS_S 13 -#define NVIC_SYS_PRI1_MEM_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority -#define NVIC_SYS_PRI2_SVC_S 29 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. -// -//***************************************************************************** -#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority -#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority -#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority -#define NVIC_SYS_PRI3_TICK_S 29 -#define NVIC_SYS_PRI3_PENDSV_S 21 -#define NVIC_SYS_PRI3_DEBUG_S 5 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL -// register. -// -//***************************************************************************** -#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable -#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable -#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable -#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending -#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending -#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending -#define NVIC_SYS_HND_CTRL_USAGEP \ - 0x00001000 // Usage Fault Pending -#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active -#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active -#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active -#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active -#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active -#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active -#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault -#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault -#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault -#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault -#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault -#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage - // Fault -#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid - -#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy - // State Preservation - -#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault -#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault -#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error -#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error -#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error -#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address - // Register Valid - -#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on - // Floating-Point Lazy State - // Preservation - -#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation -#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation -#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation -#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_HFAULT_STAT -// register. -// -//***************************************************************************** -#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event -#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault -#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DEBUG_STAT -// register. -// -//***************************************************************************** -#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted -#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch -#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match -#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction -#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MM_ADDR register. -// -//***************************************************************************** -#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_MM_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_FAULT_ADDR -// register. -// -//***************************************************************************** -#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address -#define NVIC_FAULT_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_TYPE register. -// -//***************************************************************************** -#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions -#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions -#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU -#define NVIC_MPU_TYPE_IREGION_S 16 -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_CTRL register. -// -//***************************************************************************** -#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region -#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults -#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_NUMBER -// register. -// -//***************************************************************************** -#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access -#define NVIC_MPU_NUMBER_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE register. -// -//***************************************************************************** -#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE_ADDR_S 5 -#define NVIC_MPU_BASE_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes -#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access -#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none -#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only -#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw -#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none -#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro -#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable -#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable -#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable -#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable -#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable -#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable -#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable -#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable -#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable -#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable -#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable -#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes -#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes -#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes -#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes -#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes -#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes -#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes -#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes -#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes -#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes -#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes -#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes -#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes -#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes -#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes -#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes -#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes -#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes -#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes -#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes -#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes -#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes -#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes -#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes -#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes -#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes -#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes -#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes -#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE1_ADDR_S 5 -#define NVIC_MPU_BASE1_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR1_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR1_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR1_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE2_ADDR_S 5 -#define NVIC_MPU_BASE2_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR2_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR2_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR2_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. -// -//***************************************************************************** -#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask -#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid -#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number -#define NVIC_MPU_BASE3_ADDR_S 5 -#define NVIC_MPU_BASE3_REGION_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. -// -//***************************************************************************** -#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable -#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege -#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask -#define NVIC_MPU_ATTR3_SHAREABLE \ - 0x00040000 // Shareable -#define NVIC_MPU_ATTR3_CACHEABLE \ - 0x00020000 // Cacheable -#define NVIC_MPU_ATTR3_BUFFRABLE \ - 0x00010000 // Bufferable -#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits -#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask -#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_CTRL register. -// -//***************************************************************************** -#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask -#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key -#define NVIC_DBG_CTRL_S_RESET_ST \ - 0x02000000 // Core has reset since last read -#define NVIC_DBG_CTRL_S_RETIRE_ST \ - 0x01000000 // Core has executed insruction - // since last read -#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up -#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping -#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt -#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available -#define NVIC_DBG_CTRL_C_SNAPSTALL \ - 0x00000020 // Breaks a stalled load/store -#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping -#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core -#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core -#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_XFER register. -// -//***************************************************************************** -#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read -#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register -#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 -#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 -#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 -#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 -#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 -#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 -#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 -#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 -#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 -#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 -#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 -#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 -#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 -#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 -#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 -#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 -#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register -#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP -#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP -#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP -#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_DATA register. -// -//***************************************************************************** -#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache -#define NVIC_DBG_DATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_DBG_INT register. -// -//***************************************************************************** -#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault -#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors -#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error -#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state -#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check -#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error -#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault -#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status -#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset -#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending -#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch - -//***************************************************************************** -// -// The following are defines for the bit fields in the NVIC_SW_TRIG register. -// -//***************************************************************************** -#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID - -#undef NVIC_SW_TRIG_INTID_M -#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID - -#define NVIC_SW_TRIG_INTID_S 0 - -#endif // __HW_NVIC_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_ocp_shared.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_ocp_shared.h deleted file mode 100644 index 670cad67103..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_ocp_shared.h +++ /dev/null @@ -1,3443 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_OCP_SHARED_H__ -#define __HW_OCP_SHARED_H__ - -//***************************************************************************** -// -// The following are defines for the OCP_SHARED register offsets. -// -//***************************************************************************** -#define OCP_SHARED_O_SEMAPHORE1 0x00000000 -#define OCP_SHARED_O_SEMAPHORE2 0x00000004 -#define OCP_SHARED_O_SEMAPHORE3 0x00000008 -#define OCP_SHARED_O_SEMAPHORE4 0x0000000C -#define OCP_SHARED_O_SEMAPHORE5 0x00000010 -#define OCP_SHARED_O_SEMAPHORE6 0x00000014 -#define OCP_SHARED_O_SEMAPHORE7 0x00000018 -#define OCP_SHARED_O_SEMAPHORE8 0x0000001C -#define OCP_SHARED_O_SEMAPHORE9 0x00000020 -#define OCP_SHARED_O_SEMAPHORE10 \ - 0x00000024 - -#define OCP_SHARED_O_SEMAPHORE11 \ - 0x00000028 - -#define OCP_SHARED_O_SEMAPHORE12 \ - 0x0000002C - -#define OCP_SHARED_O_IC_LOCKER_ID \ - 0x00000030 - -#define OCP_SHARED_O_MCU_SEMAPHORE_PEND \ - 0x00000034 - -#define OCP_SHARED_O_WL_SEMAPHORE_PEND \ - 0x00000038 - -#define OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY \ - 0x0000003C - -#define OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY \ - 0x00000040 - -#define OCP_SHARED_O_CC3XX_CONFIG_CTRL \ - 0x00000044 - -#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB \ - 0x00000048 - -#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB \ - 0x0000004C - -#define OCP_SHARED_O_WLAN_ELP_WAKE_EN \ - 0x00000050 - -#define OCP_SHARED_O_DEVINIT_ROM_START_ADDR \ - 0x00000054 - -#define OCP_SHARED_O_DEVINIT_ROM_END_ADDR \ - 0x00000058 - -#define OCP_SHARED_O_SSBD_SEED 0x0000005C -#define OCP_SHARED_O_SSBD_CHK 0x00000060 -#define OCP_SHARED_O_SSBD_POLY_SEL \ - 0x00000064 - -#define OCP_SHARED_O_SPARE_REG_0 \ - 0x00000068 - -#define OCP_SHARED_O_SPARE_REG_1 \ - 0x0000006C - -#define OCP_SHARED_O_SPARE_REG_2 \ - 0x00000070 - -#define OCP_SHARED_O_SPARE_REG_3 \ - 0x00000074 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_0 \ - 0x000000A0 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_1 \ - 0x000000A4 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_2 \ - 0x000000A8 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_3 \ - 0x000000AC - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_4 \ - 0x000000B0 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_5 \ - 0x000000B4 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_6 \ - 0x000000B8 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_7 \ - 0x000000BC - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_8 \ - 0x000000C0 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_9 \ - 0x000000C4 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_10 \ - 0x000000C8 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_11 \ - 0x000000CC - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_12 \ - 0x000000D0 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_13 \ - 0x000000D4 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_14 \ - 0x000000D8 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_15 \ - 0x000000DC - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_16 \ - 0x000000E0 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_17 \ - 0x000000E4 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_18 \ - 0x000000E8 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_19 \ - 0x000000EC - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_20 \ - 0x000000F0 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_21 \ - 0x000000F4 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_22 \ - 0x000000F8 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_23 \ - 0x000000FC - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_24 \ - 0x00000100 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_25 \ - 0x00000104 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_26 \ - 0x00000108 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_27 \ - 0x0000010C - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_28 \ - 0x00000110 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_29 \ - 0x00000114 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_30 \ - 0x00000118 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_31 \ - 0x0000011C - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_32 \ - 0x00000120 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_33 \ - 0x00000124 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_34 \ - 0x00000128 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_35 \ - 0x0000012C - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_36 \ - 0x00000130 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_37 \ - 0x00000134 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_38 \ - 0x00000138 - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_39 \ - 0x0000013C - -#define OCP_SHARED_O_GPIO_PAD_CONFIG_40 \ - 0x00000140 - -#define OCP_SHARED_O_GPIO_PAD_CMN_CONFIG \ - 0x00000144 // This register provide control to - // GPIO_CC3XXV1 IO PAD. Common - // control signals to all bottom Die - // IO's are controlled via this. - -#define OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG \ - 0x00000148 - -#define OCP_SHARED_O_D2D_TOSTACK_PAD_CONF \ - 0x0000014C - -#define OCP_SHARED_O_D2D_MISC_PAD_CONF \ - 0x00000150 - -#define OCP_SHARED_O_SOP_CONF_OVERRIDE \ - 0x00000154 - -#define OCP_SHARED_O_CC3XX_DEBUGSS_STATUS \ - 0x00000158 - -#define OCP_SHARED_O_CC3XX_DEBUGMUX_SEL \ - 0x0000015C - -#define OCP_SHARED_O_ALT_PC_VAL_NW \ - 0x00000160 - -#define OCP_SHARED_O_ALT_PC_VAL_APPS \ - 0x00000164 - -#define OCP_SHARED_O_SPARE_REG_4 \ - 0x00000168 - -#define OCP_SHARED_O_SPARE_REG_5 \ - 0x0000016C - -#define OCP_SHARED_O_SH_SPI_CS_MASK \ - 0x00000170 - -#define OCP_SHARED_O_CC3XX_DEVICE_TYPE \ - 0x00000174 - -#define OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE \ - 0x00000178 - -#define OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT \ - 0x0000017C - -#define OCP_SHARED_O_AUTONMS_SPICLK_SEL \ - 0x00000180 - -#define OCP_SHARED_O_CC3XX_DEV_PADCONF \ - 0x00000184 - -#define OCP_SHARED_O_SPARE_REG_8 \ - 0x00000188 - -#define OCP_SHARED_O_SPARE_REG_6 \ - 0x0000018C - -#define OCP_SHARED_O_SPARE_REG_7 \ - 0x00000190 - -#define OCP_SHARED_O_APPS_WLAN_ORBIT \ - 0x00000194 - -#define OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD \ - 0x00000198 - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE1 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE2 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE3 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE4 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE5 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE6 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE7 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE8 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE9 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE10 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE11 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORE12 register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_M \ - 0x00000003 // General Purpose Semaphore for SW - // Usage. If any of the 2 bits of a - // given register is set to 1, it - // means that the semaphore is - // locked by one of the masters. - // Each bit represents a master IP - // as follows: {WLAN,NWP}. The JTAG - // cannot capture the semaphore but - // it can release it. As a master IP - // reads the semaphore, it will be - // caputed and the masters - // correlating bit will be set to 1 - // (set upon read). As any IP writes - // to this address (independent of - // the written data) the semaphore - // will be set to 2'b00. - -#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_IC_LOCKER_ID register. -// -//****************************************************************************** -#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_M \ - 0x00000007 // This register is used for - // allowing only one master OCP to - // perform write transactions to the - // OCP slaves. Each bit represents - // an IP in the following format: { - // JTAG,WLAN, NWP mcu}. As any of - // the bits is set to one, the - // correlating IP is preventing the - // other IP's from performing write - // transactions to the slaves. As - // the Inter Connect is locked, the - // only the locking IP can write to - // the register and by that - // releasing the lock. 3'b000 => IC - // is not locked. 3'b001 => IC is - // locked by NWP mcu. 3'b010 => IC - // is locked by WLAN. 3'b100 => IC - // is locked by JTAG. - -#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_MCU_SEMAPHORE_PEND register. -// -//****************************************************************************** -#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_M \ - 0x0000FFFF // This register specifies the - // semaphore for which the NWP mcu - // is waiting to be released. It is - // set to the serial number of a - // given locked semaphore after it - // was read by the NWP mcu. Only - // [11:0] is used. - -#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_WL_SEMAPHORE_PEND register. -// -//****************************************************************************** -#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_M \ - 0x0000FFFF // This register specifies the - // semaphore for which the WLAN is - // waiting to be released. It is set - // to the serial number of a given - // locked semaphore after it was - // read by the WLAN. Only [11:0] is - // used. - -#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY register. -// -//****************************************************************************** -#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_M \ - 0x0000FFFF // This information serves the IPs - // for knowing in which platform are - // they integrated at: 0 = CC31XX. - -#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY register. -// -//****************************************************************************** -#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_M \ - 0x00000FFF // Captured/released semaphores - // status for the 12 semaphores. - // Each bit of the 12 bits - // represents a semaphore. 0 => - // Semaphore Free. 1 => Semaphore - // Captured. - -#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_CONFIG_CTRL register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_IC_TO_EN \ - 0x00000010 // This bit is used to enable - // timeout mechanism for top_ocp_ic - // (for debug puropse). When 1 value - // , in case any ocp slave doesn't - // give sresponse within 16 cylcles - // top_ic will give error response - // itself to avoid bus hange. - -#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_APPS \ - 0x00000008 // 1 bit should be accessible only - // in devinit. This will enable 0x4 - // hack for apps processor - -#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_NW \ - 0x00000004 // 1 bit, should be accessible only - // in devinit. This will enable 0x4 - // hack for nw processor - -#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_EXTEND_NW_ROM \ - 0x00000002 // When set NW can take over apps - // rom and flash via IDCODE bus. - // Apps will able to access this - // register only during devinit and - // reset value should be 0. - -#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_WLAN_HOST_INTF_SEL \ - 0x00000001 // When this bit is set to 0 WPSI - // host interface wil be selected, - // when this bit is set to 1 , WLAN - // host async bridge will be - // selected. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_M \ - 0x3FFFFFFF // This register provides memss RAM - // column configuration for column 0 - // to 9. 3 bits are allocated per - // column. This register is required - // to be configured before starting - // RAM access. Changing register - // setting while code is running - // will result into unpredictable - // memory behaviour. Register is - // supported to configured ones - // after core is booted up. 3 bit - // encoding per column is as - // follows: when 000 : WLAN, 001: - // NWP, 010: APPS, 011: PHY, 100: - // OCLA column 0 select: bit [2:0] - // :when 000 -> WLAN,001 -> NWP,010 - // -> APPS, 011 -> PHY, 100 -> OCLA - // column 1 select: bit [5:3] - // :column 2 select: bit [8 : 6]: - // column 3 select : bit [11: 9] - // column 4 select : bit [14:12] - // column 5 select : bit [17:15] - // column 6 select : bit [20:18] - // column 7 select : bit [23:21] - // column 8 select : bit [26:24] - // column 9 select : bit [29:27] - // column 10 select - -#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_M \ - 0x00000FFF // This register provides memss RAM - // column configuration for column - // 10 to 15. 3 bits are allocated - // per column. This register is - // required to be configured before - // starting RAM access. Changing - // register setting while code is - // running will result into - // unpredictable memory behaviour. - // Register is supported to - // configured ones after core is - // booted up. 3 bit encoding per - // column is as follows: when 000 : - // WLAN, 001: NWP, 010: APPS, 011: - // PHY, 100: OCLA column 11 select : - // bit [2:0] column 12 select : bit - // [5:3] column 13 select : bit [8 : - // 6] column 14 select : - -#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_WLAN_ELP_WAKE_EN register. -// -//****************************************************************************** -#define OCP_SHARED_WLAN_ELP_WAKE_EN_MEM_WLAN_ELP_WAKE_EN \ - 0x00000001 // when '1' : signal will enabled - // ELP power doamin when '0': ELP is - // not powered up. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_DEVINIT_ROM_START_ADDR register. -// -//****************************************************************************** -#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_M \ - 0xFFFFFFFF // 32 bit, Writable only during - // devinit, and whole 32 bit should - // be output of the config register - // module. This register is not used - // , similar register availble in - // GPRCM space. - -#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_DEVINIT_ROM_END_ADDR register. -// -//****************************************************************************** -#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_M \ - 0xFFFFFFFF // 32 bit, Writable only during - // devinit, and whole 32 bit should - // be output of the config register - // module. - -#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SSBD_SEED register. -// -//****************************************************************************** -#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_M \ - 0xFFFFFFFF // 32 bit, Writable only during - // devinit, and whole 32 bit should - // be output of the config register - // module. - -#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SSBD_CHK register. -// -//****************************************************************************** -#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_M \ - 0xFFFFFFFF // 32 bit, Writable only during - // devinit, and whole 32 bit should - // be output of the config register - // module. - -#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SSBD_POLY_SEL register. -// -//****************************************************************************** -#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_M \ - 0x00000003 // 2 bit, Writable only during - // devinit, and whole 2 bit should - // be output of the config register - // module. - -#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_0 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_M \ - 0xFFFFFFFF // Devinit code should look for - // whether corresponding fuse is - // blown and if blown write to the - // 11th bit of this register to - // disable flshtst interface - -#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_1 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_M \ - 0xFFFFFFFF // NWP Software register - -#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_2 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_M \ - 0xFFFFFFFF // NWP Software register - -#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_3 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_M \ - 0xFFFFFFFF // APPS Software register - -#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_0 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." "For example in - // case of I2C Value gets latched at - // rising edge of RET33.""" """ 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_1 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_2 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_3 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_4 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_5 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_6 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_7 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_8 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_9 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_10 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_11 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_12 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_13 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_14 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_15 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_16 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_17 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_18 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_19 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_20 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_21 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_22 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_23 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_24 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_25 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_26 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_27 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_28 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_29 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_30 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_31 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_32 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_M \ - 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." it can be used - // for I2C type of peripherals. 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_33 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_34 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_35 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_36 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_37 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_38 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_39 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_M \ - 0x0000003F // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 5 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. IODEN and I8MAEN - // is diesabled for all development - // IO's. These signals are tied to - // logic level '0'. common control - // is implemented for I2MAEN, - // I4MAEN, WKPU, WKPD control . - // refer dev_pad_cmn_config register - // bits. - -#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CONFIG_40 register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_M \ - 0x0007FFFF // GPIO 0 register: "Bit 0 - 3 is - // used for PAD IO mode selection. - // io_register={ "" 0 => - // """"CONFMODE[0]"""""" "" 1 => - // """"CONFMODE[1]"""""" "" 2 => - // """"CONFMODE[2]"""""" "" 3 => - // """"CONFMODE[3]"""" 4 => - // """"IODEN"""" --> When level ‘1’ - // this disables the PMOS xtors of - // the output stages making them - // open-drain type." "For example in - // case of I2C Value gets latched at - // rising edge of RET33.""" """ 5 => - // """"I2MAEN"""" --> Level ‘1’ - // enables the approx 2mA output - // stage""" """ 6 => """"I4MAEN"""" - // --> Level ‘1’ enables the approx - // 4mA output stage""" """ 7 => - // """"I8MAEN"""" --> Level ‘1’ - // enables the approx 8mA output - // stage. Note: any drive strength - // between 2mA and 14mA can be - // obtained with combination of 2mA - // 4mA and 8mA.""" """ 8 => - // """"IWKPUEN"""" --> 10uA pull up - // (weak strength)""" """ 9 => - // """"IWKPDEN"""" --> 10uA pull - // down (weak strength)""" """ 10 => - // """"IOE_N"""" --> output enable - // value. level ‘0’ enables the IDO - // to PAD path. Else PAD is - // tristated (except for the PU/PD - // which are independent)." "Value - // gets latched at rising edge of - // RET33""" """ 11 =>"""" - // IOE_N_OV"""" --> output enable - // overirde. when bit is set to - // logic '1' IOE_N (bit 4) value - // will control IO IOE_N signal else - // IOE_N is control via selected HW - // logic. strong PULL UP and PULL - // Down control is disabled for all - // IO's. both controls are tied to - // logic level '0'. - -#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_GPIO_PAD_CMN_CONFIG register. -// -//****************************************************************************** -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_A_EN \ - 0x00000080 // when '1' enable ISO A control to - // D2D Pads else ISO is disabled. - // For these PADS to be functional - // this signals should be set 0. - -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_Y_EN \ - 0x00000040 // when '1' enable ISO Y control to - // D2D Pads else ISO is disabled. - // For these PADS to be functional - // this signals should be set 0. - -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_JTAG_IDIEN \ - 0x00000020 // If level ‘1’ enables the PAD to - // ODI path for JTAG PADS [PAD 23, - // 24, 28, 29]. Else ODI is pulled - // ‘Low’ regardless of PAD level." - // "Value gets latched at rising - // edge of RET33.""" """ - -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_M \ - 0x00000018 // 00’: hysteriris = 10% of VDDS - // (difference between upper and - // lower threshold of the schmit - // trigger) ‘01’: hysteriris = 20% - // of VDDS (difference between upper - // and lower threshold of the schmit - // trigger) ‘10’: hysteriris = 30% - // of VDDS (difference between upper - // and lower threshold of the schmit - // trigger) ‘11’: hysteriris = 40% - // of VDDS (difference between upper - // and lower threshold of the schmit - // trigger)" """ - -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_S 3 -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTEN \ - 0x00000004 // If logic ‘0’ there is no - // hysteresis. Set to ‘1’ to enable - // hysteresis. Leave the choice to - // customers""" - -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IBIASEN \ - 0x00000002 // Normal functional operation set - // this to logic ‘1’ to increase the - // speed of the o/p buffer at the - // cost of 0.2uA static current - // consumption per IO. During IDDQ - // test and during Hibernate this - // would be forced to logic ‘0’. - // Value is not latched at rising - // edge of RET33."" - -#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IDIEN \ - 0x00000001 // If level ‘1’ enables the PAD to - // ODI path. Else ODI is pulled - // ‘Low’ regardless of PAD level." - // "Value gets latched at rising - // edge of RET33.""" """ - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG register. -// -//****************************************************************************** -#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_M \ - 0x0000003F // this register implements common - // IO control to all devement mode - // PADs; these PADs are DEV_PAD33 to - // DEV_PAD39. Bit [1:0] : Drive - // strength control. These 2 bits - // are connected to DEV PAD drive - // strength control. possible drive - // stregnths are 2MA, 4MA and 6 MA - // for the these IO's. bit 0: when - // set to logic value '1' enable 2MA - // drive strength for DEVPAD01 to 07 - // bit 1: when set to logic value - // '1' enable 4MA drive strength for - // DEVPAD01 to 07. bit[3:2] : WK - // PULL UP and PULL down control. - // These 2 bits provide IWKPUEN and - // IWKPDEN control for all DEV IO's. - // bit 2: when set to logic value - // '1' enable WKPU to DEVPAD01 to 07 - // bit 3: when set to logic value - // '1' enable WKPD to DEVPAD01 to - // 07. bit 4: WK PULL control for - // DEV_PKG_DETECT pin. when '1' - // pullup enabled else it is - // disable. bit 5: when set to logic - // value '1' enable 8MA drive - // strength for DEVPAD01 to 07. - -#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_D2D_TOSTACK_PAD_CONF register. -// -//****************************************************************************** -#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_M \ - 0x1FFFFFFF // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - // this register control OEN2X pin - // of D2D TOSTACK PAD: OEN1X and - // OEN2X decoding is as follows: - // "when ""00"" :" "when ""01"" : - // dirve strength is '1' and output - // buffer enabled." "when ""10"" : - // drive strength is 2 and output - // buffer is disabled." "when ""11"" - // : dirve strength is '3' and - // output buffer enabled." - -#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_D2D_MISC_PAD_CONF register. -// -//****************************************************************************** -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_POR_RESET_N \ - 0x00000200 // This register provide OEN2X - // control to D2D PADS OEN/OEN2X - // control. When 0 : Act as input - // buffer else output buffer with - // drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_RESET_N \ - 0x00000100 // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_HCLK \ - 0x00000080 // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TCK \ - 0x00000040 // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TMS \ - 0x00000020 // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TDI \ - 0x00000010 // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_PIOSC \ - 0x00000008 // OEN/OEN2X control. When 0 : Act - // as input buffer else output - // buffer with drive strength 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_M \ - 0x00000007 // D2D SPARE PAD OEN/OEN2X control. - // When 0: Act as input buffer else - // output buffer with drive strength - // 2. - -#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SOP_CONF_OVERRIDE register. -// -//****************************************************************************** -#define OCP_SHARED_SOP_CONF_OVERRIDE_MEM_SOP_CONF_OVERRIDE \ - 0x00000001 // when '1' : signal will ovberride - // SoP setting of JTAG PADS. when - // '0': SoP setting will control - // JTAG PADs [ TDI, TDO, TMS, TCK] - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_DEBUGSS_STATUS register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_MCU_JTAGNSW \ - 0x00000020 // This register contains debug - // subsystem status bits From APPS - // MCU status bit to indicates - // whether serial wire or 4 pins - // jtag select. - -#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_CJTAG_BYPASS_STATUS \ - 0x00000010 // cjtag bypass bit select - -#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SW_INTERFACE_SEL_STATUS \ - 0x00000008 // serial wire interface bit select - -#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_TAP_ENABLE_STATUS \ - 0x00000004 // apps tap enable status - -#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_TAPS_ENABLE_STATUS \ - 0x00000002 // tap enable status - -#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SSBD_UNLOCK \ - 0x00000001 // ssbd unlock status - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_DEBUGMUX_SEL register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_M \ - 0x0000FFFF // debug mux select register. Upper - // 8 bits are used for debug module - // selection. Lower 8 bit [7:0] used - // inside debug module for selecting - // module specific signals. - // Bits[15:8: when set x"00" : GPRCM - // debug bus. When "o1" : SDIO debug - // debug bus when x"02" : - // autonoumous SPI when x"03" : - // TOPIC when x"04": memss when - // x"25": mcu debug bus : APPS debug - // when x"45": mcu debug bus : NWP - // debug when x"65": mcu debug bus : - // AHB2VBUS debug when x"85": mcu - // debug bus : VBUS2HAB debug when - // x"95": mcu debug bus : RCM debug - // when x"A5": mcu debug bus : - // crypto debug when x"06": WLAN - // debug bus when x"07": debugss bus - // when x"08": ADC debug when x"09": - // SDIO PHY debug bus then "others" - // : no debug is selected - -#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_ALT_PC_VAL_NW register. -// -//****************************************************************************** -#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_M \ - 0xFFFFFFFF // 32 bit. Program counter value - // for 0x4 address when Alt_pc_en_nw - // is set. - -#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_ALT_PC_VAL_APPS register. -// -//****************************************************************************** -#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_M \ - 0xFFFFFFFF // 32 bit. Program counter value - // for 0x4 address when - // Alt_pc_en_apps is set - -#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_4 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_M \ - 0xFFFFFFFE // HW register - -#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_S 1 -#define OCP_SHARED_SPARE_REG_4_INVERT_D2D_INTERFACE \ - 0x00000001 // Data to the top die launched at - // negative edge instead of positive - // edge. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_5 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_M \ - 0xFFFFFFFF // HW register - -#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SH_SPI_CS_MASK register. -// -//****************************************************************************** -#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_M \ - 0x0000000F // ( chip select 0 is unmasked - // after reset. When ‘1’ : CS is - // unmasked or else masked. Valid - // configurations are 1000, 0100, - // 0010 or 0001. Any other setting - // can lead to unpredictable - // behavior. - -#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_DEVICE_TYPE register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_M \ - 0x00000060 // reserved bits tied off "00". - -#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_S 5 -#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_M \ - 0x0000001F // CC3XX Device type information. - -#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE register. -// -//****************************************************************************** -#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_M \ - 0x000000F0 // [4] 1: switch between - // WLAN_I2C_SCL and - // TOP_GPIO_PORT4_I2C closes 0: - // switch opens [5] 1: switch - // between WLAN_I2C_SCL and - // TOP_VSENSE_PORT closes 0: switch - // opens [6] 1: switch between - // WLAN_I2C_SCL and WLAN_ANA_TP4 - // closes 0: switch opens [7] - // Reserved - -#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_S 4 -#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_M \ - 0x0000000F // [0] 1: switch between - // WLAN_I2C_SDA and - // TOP_GPIO_PORT3_I2C closes 0: - // switch opens [1] 1: switch - // between WLAN_I2C_SDA and - // TOP_IFORCE_PORT closes 0: switch - // opens [2] 1: switch between - // WLAN_I2C_SDA and WLAN_ANA_TP3 - // closes 0: switch opens [3] - // Reserved - -#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_DEV_PACKAGE_DETECT_DEV_PKG_DETECT \ - 0x00000001 // when '0' indicates package type - // is development. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_AUTONMS_SPICLK_SEL register. -// -//****************************************************************************** -#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONOMOUS_BYPASS \ - 0x00000002 // This bit is used to bypass MCPSI - // autonomous mode .if this bit is 1 - // autonomous MCSPI logic will be - // bypassed and it will act as link - // SPI - -#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONMS_SPICLK_SEL \ - 0x00000001 // This bit is used in SPI - // Autonomous mode to switch clock - // from system clock to SPI clk that - // is coming from PAD. When value 1 - // PAD SPI clk is used as system - // clock in LPDS mode by SPI as well - // as autonomous wrapper logic. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_CC3XX_DEV_PADCONF register. -// -//****************************************************************************** -#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_M \ - 0x0000FFFF - -#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_IDMEM_TIM_UPDATE register. -// -//****************************************************************************** -#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_M \ - 0xFFFFFFFF - -#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_6 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_M \ - 0xFFFFFFFF // NWP Software register - -#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_SPARE_REG_7 register. -// -//****************************************************************************** -#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_M \ - 0xFFFFFFFF // NWP Software register - -#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_APPS_WLAN_ORBIT register. -// -//****************************************************************************** -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_M \ - 0xFFFFFC00 // Spare bit - -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_S 10 -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_status \ - 0x00000200 // A rising edge on this bit - // indicates that the test case - // passes. This bit would be brought - // out on the pin interface during - // ORBIT. - -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_exec \ - 0x00000100 // This register bit is writable by - // the FW and when set to 1 it - // indicates the start of a test - // execution. A failing edge on this - // bit indicates that the test - // execution is complete. This bit - // would be brought out on the pin - // interface during ORBIT. - -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_M \ - 0x000000FC // Implies the test case ID that - // needs to run. - -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_S 2 -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_halt_proc \ - 0x00000002 // This bit is used to trigger the - // execution of test cases within - // the (ROM based) IP. - -#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_mode \ - 0x00000001 // When this bit is 1 it implies - // ORBIT mode of operation and the - // (ROM based) IP start the - // execution from a test case - // perspective - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD register. -// -//****************************************************************************** -#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_M \ - 0xFFFFFFFF // scratch pad register. - -#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_S 0 - - - -#endif // __HW_OCP_SHARED_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_shamd5.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_shamd5.h deleted file mode 100644 index aaee0ef4bde..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_shamd5.h +++ /dev/null @@ -1,1240 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_SHAMD5_H__ -#define __HW_SHAMD5_H__ - -//***************************************************************************** -// -// The following are defines for the SHAMD5_P register offsets. -// -//***************************************************************************** -#define SHAMD5_O_ODIGEST_A 0x00000000 // WRITE: Outer Digest [127:96] for - // MD5 [159:128] for SHA-1 [255:224] - // for SHA-2 / HMAC Key [31:0] for - // HMAC key proc READ: Outer Digest - // [127:96] for MD5 [159:128] for - // SHA-1 [255:224] for SHA-2 -#define SHAMD5_O_ODIGEST_B 0x00000004 // WRITE: Outer Digest [95:64] for - // MD5 [127:96] for SHA-1 [223:192] - // for SHA-2 / HMAC Key [63:32] for - // HMAC key proc READ: Outer Digest - // [95:64] for MD5 [127:96] for - // SHA-1 [223:192] for SHA-2 -#define SHAMD5_O_ODIGEST_C 0x00000008 // WRITE: Outer Digest [63:32] for - // MD5 [95:64] for SHA-1 [191:160] - // for SHA-2 / HMAC Key [95:64] for - // HMAC key proc READ: Outer Digest - // [63:32] for MD5 [95:64] for SHA-1 - // [191:160] for SHA-2 -#define SHAMD5_O_ODIGEST_D 0x0000000C // WRITE: Outer Digest [31:0] for - // MD5 [63:31] for SHA-1 [159:128] - // for SHA-2 / HMAC Key [127:96] for - // HMAC key proc READ: Outer Digest - // [31:0] for MD5 [63:32] for SHA-1 - // [159:128] for SHA-2 -#define SHAMD5_O_ODIGEST_E 0x00000010 // WRITE: Outer Digest [31:0] for - // SHA-1 [127:96] for SHA-2 / HMAC - // Key [159:128] for HMAC key proc - // READ: Outer Digest [31:0] for - // SHA-1 [127:96] for SHA-2 -#define SHAMD5_O_ODIGEST_F 0x00000014 // WRITE: Outer Digest [95:64] for - // SHA-2 / HMAC Key [191:160] for - // HMAC key proc READ: Outer Digest - // [95:64] for SHA-2 -#define SHAMD5_O_ODIGEST_G 0x00000018 // WRITE: Outer Digest [63:32] for - // SHA-2 / HMAC Key [223:192] for - // HMAC key proc READ: Outer Digest - // [63:32] for SHA-2 -#define SHAMD5_O_ODIGEST_H 0x0000001C // WRITE: Outer Digest [31:0] for - // SHA-2 / HMAC Key [255:224] for - // HMAC key proc READ: Outer Digest - // [31:0] for SHA-2 -#define SHAMD5_O_IDIGEST_A 0x00000020 // WRITE: Inner / Initial Digest - // [127:96] for MD5 [159:128] for - // SHA-1 [255:224] for SHA-2 / HMAC - // Key [287:256] for HMAC key proc - // READ: Intermediate / Inner Digest - // [127:96] for MD5 [159:128] for - // SHA-1 [255:224] for SHA-2 / - // Result Digest/MAC [127:96] for - // MD5 [159:128] for SHA-1 [223:192] - // for SHA-2 224 [255:224] for SHA-2 - // 256 -#define SHAMD5_O_IDIGEST_B 0x00000024 // WRITE: Inner / Initial Digest - // [95:64] for MD5 [127:96] for - // SHA-1 [223:192] for SHA-2 / HMAC - // Key [319:288] for HMAC key proc - // READ: Intermediate / Inner Digest - // [95:64] for MD5 [127:96] for - // SHA-1 [223:192] for SHA-2 / - // Result Digest/MAC [95:64] for MD5 - // [127:96] for SHA-1 [191:160] for - // SHA-2 224 [223:192] for SHA-2 256 -#define SHAMD5_O_IDIGEST_C 0x00000028 // WRITE: Inner / Initial Digest - // [63:32] for MD5 [95:64] for SHA-1 - // [191:160] for SHA- 2 / HMAC Key - // [351:320] for HMAC key proc READ: - // Intermediate / Inner Digest - // [63:32] for MD5 [95:64] for SHA-1 - // [191:160] for SHA-2 / Result - // Digest/MAC [63:32] for MD5 - // [95:64] for SHA-1 [159:128] for - // SHA-2 224 [191:160] for SHA-2 256 -#define SHAMD5_O_IDIGEST_D 0x0000002C // WRITE: Inner / Initial Digest - // [31:0] for MD5 [63:32] for SHA-1 - // [159:128] for SHA-2 / HMAC Key - // [383:352] for HMAC key proc READ: - // Intermediate / Inner Digest - // [31:0] for MD5 [63:32] for SHA-1 - // [159:128] for SHA-2 / Result - // Digest/MAC [31:0] for MD5 [63:32] - // for SHA-1 [127:96] for SHA-2 224 - // [159:128] for SHA-2 256 -#define SHAMD5_O_IDIGEST_E 0x00000030 // WRITE: Inner / Initial Digest - // [31:0] for SHA-1 [127:96] for - // SHA-2 / HMAC Key [415:384] for - // HMAC key proc READ: Intermediate - // / Inner Digest [31:0] for SHA-1 - // [127:96] for SHA-2 / Result - // Digest/MAC [31:0] for SHA-1 - // [95:64] for SHA-2 224 [127:96] - // for SHA-2 256 -#define SHAMD5_O_IDIGEST_F 0x00000034 // WRITE: Inner / Initial Digest - // [95:64] for SHA-2 / HMAC Key - // [447:416] for HMAC key proc READ: - // Intermediate / Inner Digest - // [95:64] for SHA-2 / Result - // Digest/MAC [63:32] for SHA-2 224 - // [95:64] for SHA-2 256 -#define SHAMD5_O_IDIGEST_G 0x00000038 // WRITE: Inner / Initial Digest - // [63:32] for SHA-2 / HMAC Key - // [479:448] for HMAC key proc READ: - // Intermediate / Inner Digest - // [63:32] for SHA-2 / Result - // Digest/MAC [31:0] for SHA-2 224 - // [63:32] for SHA-2 256 -#define SHAMD5_O_IDIGEST_H 0x0000003C // WRITE: Inner / Initial Digest - // [31:0] for SHA-2 / HMAC Key - // [511:480] for HMAC key proc READ: - // Intermediate / Inner Digest - // [31:0] for SHA-2 / Result - // Digest/MAC [31:0] for SHA-2 256 -#define SHAMD5_O_DIGEST_COUNT 0x00000040 // WRITE: Initial Digest Count - // ([31:6] only [5:0] assumed 0) - // READ: Result / IntermediateDigest - // Count The initial digest byte - // count for hash/HMAC continue - // operations (HMAC Key Processing = - // 0 and Use Algorithm Constants = - // 0) on the Secure World must be - // written to this register prior to - // starting the operation by writing - // to S_HASH_MODE. When either HMAC - // Key Processing is 1 or Use - // Algorithm Constants is 1 this - // register does not need to be - // written it will be overwritten - // with 64 (1 hash block of key XOR - // ipad) or 0 respectively - // automatically. When starting a - // HMAC operation from pre-computes - // (HMAC Key Processing is 0) then - // the value 64 must be written here - // to compensate for the appended - // key XOR ipad block. Note that the - // value written should always be a - // 64 byte multiple the lower 6 bits - // written are ignored. The updated - // digest byte count (initial digest - // byte count + bytes processed) can - // be read from this register when - // the status register indicates - // that the operation is done or - // suspended due to a context switch - // request or when a Secure World - // context out DMA is requested. In - // Advanced DMA mode when not - // suspended with a partial result - // reading the SHAMD5_DIGEST_COUNT - // register triggers the Hash/HMAC - // Engine to start the next context - // input DMA. Therefore reading the - // SHAMD5_DIGEST_COUNT register - // should always be the last - // context-read action if not - // suspended with a partial result - // (i.e. PartHashReady interrupt not - // pending). -#define SHAMD5_O_MODE 0x00000044 // Register SHAMD5_MODE -#define SHAMD5_O_LENGTH 0x00000048 // WRITE: Block Length / Remaining - // Byte Count (bytes) READ: - // Remaining Byte Count. The value - // programmed MUST be a 64-byte - // multiple if Close Hash is set to - // 0. This register is also the - // trigger to start processing: once - // this register is written the core - // will commence requesting input - // data via DMA or IRQ (if - // programmed length > 0) and start - // processing. The remaining byte - // count for the active operation - // can be read from this register - // when the interrupt status - // register indicates that the - // operation is suspended due to a - // context switch request. -#define SHAMD5_O_DATA0_IN 0x00000080 // Data input message 0 -#define SHAMD5_O_DATA1_IN 0x00000084 // Data input message 1 -#define SHAMD5_O_DATA2_IN 0x00000088 // Data input message 2 -#define SHAMD5_O_DATA3_IN 0x0000008C // Data input message 3 -#define SHAMD5_O_DATA4_IN 0x00000090 // Data input message 4 -#define SHAMD5_O_DATA5_IN 0x00000094 // Data input message 5 -#define SHAMD5_O_DATA6_IN 0x00000098 // Data input message 6 -#define SHAMD5_O_DATA7_IN 0x0000009C // Data input message 7 -#define SHAMD5_O_DATA8_IN 0x000000A0 // Data input message 8 -#define SHAMD5_O_DATA9_IN 0x000000A4 // Data input message 9 -#define SHAMD5_O_DATA10_IN 0x000000A8 // Data input message 10 -#define SHAMD5_O_DATA11_IN 0x000000AC // Data input message 11 -#define SHAMD5_O_DATA12_IN 0x000000B0 // Data input message 12 -#define SHAMD5_O_DATA13_IN 0x000000B4 // Data input message 13 -#define SHAMD5_O_DATA14_IN 0x000000B8 // Data input message 14 -#define SHAMD5_O_DATA15_IN 0x000000BC // Data input message 15 -#define SHAMD5_O_REVISION 0x00000100 // Register SHAMD5_REV -#define SHAMD5_O_SYSCONFIG 0x00000110 // Register SHAMD5_SYSCONFIG -#define SHAMD5_O_SYSSTATUS 0x00000114 // Register SHAMD5_SYSSTATUS -#define SHAMD5_O_IRQSTATUS 0x00000118 // Register SHAMD5_IRQSTATUS -#define SHAMD5_O_IRQENABLE 0x0000011C // Register SHAMD5_IRQENABLE. The - // SHAMD5_IRQENABLE register contains - // an enable bit for each unique - // interrupt for the public side. An - // interrupt is enabled when both - // the global enable in - // SHAMD5_SYSCONFIG (PIT_en) and the - // bit in this register are both set - // to 1. An interrupt that is - // enabled is propagated to the - // SINTREQUEST_P output. Please note - // that the dedicated partial hash - // output (SINTREQUEST_PART_P) is - // not affected by this register it - // is only affected by the global - // enable SHAMD5_SYSCONFIG (PIT_en). -#define SHAMD5_O_HASH512_ODIGEST_A \ - 0x00000200 - -#define SHAMD5_O_HASH512_ODIGEST_B \ - 0x00000204 - -#define SHAMD5_O_HASH512_ODIGEST_C \ - 0x00000208 - -#define SHAMD5_O_HASH512_ODIGEST_D \ - 0x0000020C - -#define SHAMD5_O_HASH512_ODIGEST_E \ - 0x00000210 - -#define SHAMD5_O_HASH512_ODIGEST_F \ - 0x00000214 - -#define SHAMD5_O_HASH512_ODIGEST_G \ - 0x00000218 - -#define SHAMD5_O_HASH512_ODIGEST_H \ - 0x0000021C - -#define SHAMD5_O_HASH512_ODIGEST_I \ - 0x00000220 - -#define SHAMD5_O_HASH512_ODIGEST_J \ - 0x00000224 - -#define SHAMD5_O_HASH512_ODIGEST_K \ - 0x00000228 - -#define SHAMD5_O_HASH512_ODIGEST_L \ - 0x0000022C - -#define SHAMD5_O_HASH512_ODIGEST_M \ - 0x00000230 - -#define SHAMD5_O_HASH512_ODIGEST_N \ - 0x00000234 - -#define SHAMD5_O_HASH512_ODIGEST_O \ - 0x00000238 - -#define SHAMD5_O_HASH512_ODIGEST_P \ - 0x0000023C - -#define SHAMD5_O_HASH512_IDIGEST_A \ - 0x00000240 - -#define SHAMD5_O_HASH512_IDIGEST_B \ - 0x00000244 - -#define SHAMD5_O_HASH512_IDIGEST_C \ - 0x00000248 - -#define SHAMD5_O_HASH512_IDIGEST_D \ - 0x0000024C - -#define SHAMD5_O_HASH512_IDIGEST_E \ - 0x00000250 - -#define SHAMD5_O_HASH512_IDIGEST_F \ - 0x00000254 - -#define SHAMD5_O_HASH512_IDIGEST_G \ - 0x00000258 - -#define SHAMD5_O_HASH512_IDIGEST_H \ - 0x0000025C - -#define SHAMD5_O_HASH512_IDIGEST_I \ - 0x00000260 - -#define SHAMD5_O_HASH512_IDIGEST_J \ - 0x00000264 - -#define SHAMD5_O_HASH512_IDIGEST_K \ - 0x00000268 - -#define SHAMD5_O_HASH512_IDIGEST_L \ - 0x0000026C - -#define SHAMD5_O_HASH512_IDIGEST_M \ - 0x00000270 - -#define SHAMD5_O_HASH512_IDIGEST_N \ - 0x00000274 - -#define SHAMD5_O_HASH512_IDIGEST_O \ - 0x00000278 - -#define SHAMD5_O_HASH512_IDIGEST_P \ - 0x0000027C - -#define SHAMD5_O_HASH512_DIGEST_COUNT \ - 0x00000280 - -#define SHAMD5_O_HASH512_MODE 0x00000284 -#define SHAMD5_O_HASH512_LENGTH 0x00000288 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_A_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_B_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_C_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_D_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_E_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_F_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_G_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H register. -// -//****************************************************************************** -#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // data -#define SHAMD5_ODIGEST_H_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_A_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_B_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_C_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_D_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_E_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_F_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_G_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H register. -// -//****************************************************************************** -#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // data -#define SHAMD5_IDIGEST_H_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_DIGEST_COUNT register. -// -//****************************************************************************** -#define SHAMD5_DIGEST_COUNT_DATA_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DIGEST_COUNT_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_MODE register. -// -//****************************************************************************** -#define SHAMD5_MODE_HMAC_OUTER_HASH \ - 0x00000080 // The HMAC Outer Hash is performed - // on the hash digest when the inner - // hash hash finished (block length - // exhausted and final hash - // performed if close_hash is 1). - // This bit should normally be set - // together with close_hash to - // finish the inner hash first or - // Block Length should be zero (HMAC - // continue with the just outer hash - // to be done). Auto cleared - // internally when outer hash - // performed. 0 No operation 1 hmac - // processing - -#define SHAMD5_MODE_HMAC_KEY_PROC \ - 0x00000020 // Performs HMAC key processing on - // the 512 bit HMAC key loaded into - // the SHAMD5_IDIGEST_{A to H} and - // SHAMD5_ODIGEST_{A to H} register - // block. Once HMAC key processing - // is finished this bit is - // automatically cleared and the - // resulting Inner and Outer digest - // is available from - // SHAMD5_IDIGEST_{A to H} and - // SHAMD5_ODIGEST_{A to H} - // respectively after which regular - // hash processing (using - // SHAMD5_IDIGEST_{A to H} as initial - // digest) will commence until the - // Block Length is exhausted. 0 No - // operation. 1 Hmac processing. - -#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding the - // hash/HMAC will be 'closed' at the - // end of the block as per - // MD5/SHA-1/SHA-2 specification - // (i.e. appropriate padding is - // added) or no padding is done - // allowing the hash to be continued - // later. However if the hash/HMAC - // is not closed then the Block - // Length MUST be a multiple of 64 - // bytes to ensure correct - // operation. Auto cleared - // internally when hash closed. 0 No - // padding hash computation can be - // contimued. 1 Last packet will be - // padded. -#define SHAMD5_MODE_ALGO_CONSTANT \ - 0x00000008 // The initial digest register will - // be overwritten with the algorithm - // constants for the selected - // algorithm when hashing and the - // initial digest count register - // will be reset to 0. This will - // start a normal hash operation. - // When continuing an existing hash - // or when performing an HMAC - // operation this register must be - // set to 0 and the - // intermediate/inner digest or HMAC - // key and digest count need to be - // written to the context input - // registers prior to writing - // SHAMD5_MODE. Auto cleared - // internally after first block - // processed. 0 Use pre-calculated - // digest (from an other operation) - // 1 Use constants of the selected - // algo. - -#define SHAMD5_MODE_ALGO_M 0x00000006 // These bits select the hash - // algorithm to be used for - // processing: 0x0 md5_128 algorithm - // 0x1 sha1_160 algorithm 0x2 - // sha2_224 algorithm 0x3 sha2_256 - // algorithm -#define SHAMD5_MODE_ALGO_S 1 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_LENGTH register. -// -//****************************************************************************** -#define SHAMD5_LENGTH_DATA_M 0xFFFFFFFF // data -#define SHAMD5_LENGTH_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA0_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA0_IN_DATA0_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA0_IN_DATA0_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA1_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA1_IN_DATA1_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA1_IN_DATA1_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA2_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA2_IN_DATA2_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA2_IN_DATA2_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA3_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA3_IN_DATA3_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA3_IN_DATA3_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA4_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA4_IN_DATA4_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA4_IN_DATA4_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA5_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA5_IN_DATA5_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA5_IN_DATA5_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA6_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA6_IN_DATA6_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA6_IN_DATA6_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA7_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA7_IN_DATA7_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA7_IN_DATA7_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA8_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA8_IN_DATA8_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA8_IN_DATA8_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA9_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA9_IN_DATA9_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA9_IN_DATA9_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA10_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA10_IN_DATA10_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA10_IN_DATA10_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA11_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA11_IN_DATA11_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA11_IN_DATA11_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA12_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA12_IN_DATA12_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA12_IN_DATA12_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA13_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA13_IN_DATA13_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA13_IN_DATA13_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA14_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA14_IN_DATA14_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA14_IN_DATA14_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_DATA15_IN register. -// -//****************************************************************************** -#define SHAMD5_DATA15_IN_DATA15_IN_M \ - 0xFFFFFFFF // data - -#define SHAMD5_DATA15_IN_DATA15_IN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_REVISION register. -// -//****************************************************************************** -#define SHAMD5_REVISION_SCHEME_M 0xC0000000 -#define SHAMD5_REVISION_SCHEME_S 30 -#define SHAMD5_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software - // compatible module family. If - // there is no level of software - // compatibility a new Func number - // (and hence REVISION) should be - // assigned. -#define SHAMD5_REVISION_FUNC_S 16 -#define SHAMD5_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP - // design owner. RTL follows a - // numbering such as X.Y.R.Z which - // are explained in this table. R - // changes ONLY when: (1) PDS - // uploads occur which may have been - // due to spec changes (2) Bug fixes - // occur (3) Resets to '0' when X or - // Y changes. Design team has an - // internal 'Z' (customer invisible) - // number which increments on every - // drop that happens due to DV and - // RTL updates. Z resets to 0 when R - // increments. -#define SHAMD5_REVISION_R_RTL_S 11 -#define SHAMD5_REVISION_X_MAJOR_M \ - 0x00000700 // Major Revision (X) maintained by - // IP specification owner. X changes - // ONLY when: (1) There is a major - // feature addition. An example - // would be adding Master Mode to - // Utopia Level2. The Func field (or - // Class/Type in old PID format) - // will remain the same. X does NOT - // change due to: (1) Bug fixes (2) - // Change in feature parameters. - -#define SHAMD5_REVISION_X_MAJOR_S 8 -#define SHAMD5_REVISION_CUSTOM_M 0x000000C0 -#define SHAMD5_REVISION_CUSTOM_S 6 -#define SHAMD5_REVISION_Y_MINOR_M \ - 0x0000003F // Minor Revision (Y) maintained by - // IP specification owner. Y changes - // ONLY when: (1) Features are - // scaled (up or down). Flexibility - // exists in that this feature - // scalability may either be - // represented in the Y change or a - // specific register in the IP that - // indicates which features are - // exactly available. (2) When - // feature creeps from Is-Not list - // to Is list. But this may not be - // the case once it sees silicon; in - // which case X will change. Y does - // NOT change due to: (1) Bug fixes - // (2) Typos or clarifications (3) - // major functional/feature - // change/addition/deletion. Instead - // these changes may be reflected - // via R S X as applicable. Spec - // owner maintains a - // customer-invisible number 'S' - // which changes due to: (1) - // Typos/clarifications (2) Bug - // documentation. Note that this bug - // is not due to a spec change but - // due to implementation. - // Nevertheless the spec tracks the - // IP bugs. An RTL release (say for - // silicon PG1.1) that occurs due to - // bug fix should document the - // corresponding spec number (X.Y.S) - // in its release notes. - -#define SHAMD5_REVISION_Y_MINOR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG register. -// -//****************************************************************************** -#define SHAMD5_SYSCONFIG_PADVANCED \ - 0x00000080 // If set to 1 Advanced mode is - // enabled for the Secure World. If - // set to 0 Legacy mode is enabled - // for the Secure World. - -#define SHAMD5_SYSCONFIG_PCONT_SWT \ - 0x00000040 // Finish all pending data and - // context DMA input requests (but - // will not assert any new requests) - // finish processing all data in the - // module and provide a saved - // context (partial hash result - // updated digest count remaining - // length updated mode information - // where applicable) for the last - // operation that was interrupted so - // that it can be resumed later. - -#define SHAMD5_SYSCONFIG_PDMA_EN 0x00000008 -#define SHAMD5_SYSCONFIG_PIT_EN 0x00000004 -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS register. -// -//****************************************************************************** -#define SHAMD5_SYSSTATUS_RESETDONE \ - 0x00000001 // data - -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS register. -// -//****************************************************************************** -#define SHAMD5_IRQSTATUS_CONTEXT_READY \ - 0x00000008 // indicates that the secure side - // context input registers are - // available for a new context for - // the next packet to be processed. - -#define SHAMD5_IRQSTATUS_PARTHASH_READY \ - 0x00000004 // After a secure side context - // switch request this bit will read - // as 1 indicating that the saved - // context is available from the - // secure side context output - // registers. Note that if the - // context switch request coincides - // with a final hash (when hashing) - // or an outer hash (when doing - // HMAC) that PartHashReady will not - // become active but a regular - // Output Ready will occur instead - // (indicating that the result is - // final and therefore no - // continuation is required). - -#define SHAMD5_IRQSTATUS_INPUT_READY \ - 0x00000002 // indicates that the secure side - // data FIFO is ready to receive the - // next 64 byte data block. - -#define SHAMD5_IRQSTATUS_OUTPUT_READY \ - 0x00000001 // Indicates that a (partial) - // result or saved context is - // available from the secure side - // context output registers. - -//****************************************************************************** -// -// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE register. -// -//****************************************************************************** -#define SHAMD5_IRQENABLE_M_CONTEXT_READY \ - 0x00000008 // mask for context ready - -#define SHAMD5_IRQENABLE_M_PARTHASH_READY \ - 0x00000004 // mask for partial hash - -#define SHAMD5_IRQENABLE_M_INPUT_READY \ - 0x00000002 // mask for input_ready - -#define SHAMD5_IRQENABLE_M_OUTPUT_READY \ - 0x00000001 // mask for output_ready - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_A register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_A_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_A_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_B register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_B_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_B_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_C register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_C_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_C_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_D register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_D_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_D_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_E register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_E_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_E_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_F register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_F_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_F_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_G register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_G_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_G_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_H register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_H_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_H_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_I register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_I_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_I_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_J register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_J_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_J_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_K register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_K_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_K_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_L register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_L_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_L_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_M register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_M_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_M_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_N register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_N_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_N_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_O register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_O_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_O_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_ODIGEST_P register. -// -//****************************************************************************** -#define SHAMD5_HASH512_ODIGEST_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_ODIGEST_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_A register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_A_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_A_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_B register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_B_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_B_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_C register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_C_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_C_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_D register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_D_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_D_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_E register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_E_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_E_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_F register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_F_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_F_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_G register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_G_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_G_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_H register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_H_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_H_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_I register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_I_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_I_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_J register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_J_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_J_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_K register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_K_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_K_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_L register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_L_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_L_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_M register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_M_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_M_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_N register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_N_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_N_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_O register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_O_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_O_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_IDIGEST_P register. -// -//****************************************************************************** -#define SHAMD5_HASH512_IDIGEST_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_IDIGEST_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_DIGEST_COUNT register. -// -//****************************************************************************** -#define SHAMD5_HASH512_DIGEST_COUNT_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_DIGEST_COUNT_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_MODE register. -// -//****************************************************************************** -#define SHAMD5_HASH512_MODE_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_MODE_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// SHAMD5_O_HASH512_LENGTH register. -// -//****************************************************************************** -#define SHAMD5_HASH512_LENGTH_DATA_M \ - 0xFFFFFFFF - -#define SHAMD5_HASH512_LENGTH_DATA_S 0 - - - -#endif // __HW_SHAMD5_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h deleted file mode 100644 index d406163277c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_stack_die_ctrl.h +++ /dev/null @@ -1,762 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#ifndef __HW_STACK_DIE_CTRL_H__ -#define __HW_STACK_DIE_CTRL_H__ - -//***************************************************************************** -// -// The following are defines for the STACK_DIE_CTRL register offsets. -// -//***************************************************************************** -#define STACK_DIE_CTRL_O_STK_UP_RESET \ - 0x00000000 // Can be written only by Base - // Processor. Writing to this - // register will reset the stack - // processor reset will be - // de-asserted upon clearing this - // register. - -#define STACK_DIE_CTRL_O_SR_MASTER_PRIORITY \ - 0x00000004 // This register defines who among - // base processor and stack - // processor have highest priority - // for Sram Access. Can be written - // only by Base Processor. - -#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 \ - 0x00000008 // In Spinlock mode this Register - // defines who among base processor - // and stack processor have access - // to Sram Bank2 right now. In - // Handshake mode this Register - // defines who among base processor - // and stack processor have access - // to Sram Bank2 and Bank3 right - // now. Its Clear only register and - // is set by hardware. Lower bit can - // be cleared only by Base Processor - // and Upper bit Cleared only by the - // Stack processor. - -#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 \ - 0x0000000C // In Spinlock mode whenever Base - // processor wants the access to - // Sram Bank2 it should request for - // it by writing into this register. - // It'll get interrupt whenever it - // is granted. In Handshake mode - // this bit will be set by Stack - // processor. Its a set only bit and - // is cleared by HW when the request - // is granted. - -#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 \ - 0x00000010 // In Spinlock mode Whenever Stack - // processor wants the access to - // Sram Bank2 it should request for - // it by writing into this register. - // It'll get interrupt whenever it - // is granted. In Handshake mode - // this bit will be set by the Base - // processor. Its a set only bit and - // is cleared by HW when the request - // is granted. - -#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 \ - 0x00000014 // Register defines who among base - // processor and stack processor - // have access to Sram Bank3 right - // now. Its Clear only register and - // is set by hardware. Lower bit can - // be cleared only by Base Processor - // and Upper bit Cleared only by the - // Stack processor. - -#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 \ - 0x00000018 // In Spinlock mode whenever Base - // processor wants the access to - // Sram Bank3 it should request for - // it by writing into this register. - // It'll get interrupt whenever it - // is granted. In Handshake mode - // this bit will be set by Stack - // processor. Its a set only bit and - // is cleared by HW when the request - // is granted. - -#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 \ - 0x0000001C // In Spinlock mode Whenever Stack - // processor wants the access to - // Sram Bank3 it should request for - // it by writing into this register. - // It'll get interrupt whenever it - // is granted. In Handshake mode - // this bit will be set by the Base - // processor. Its a set only bit and - // is cleared by HW when the request - // is granted. - -#define STACK_DIE_CTRL_O_RDSM_CFG_CPU \ - 0x00000020 // Read State Machine timing - // configuration register. Generally - // Bit 4 and 3 will be identical. - // For stacked die always 43 are 0 - // and 6:5 == 1 for 120Mhz. - -#define STACK_DIE_CTRL_O_RDSM_CFG_EE \ - 0x00000024 // Read State Machine timing - // configuration register. Generally - // Bit 4 and 3 will be identical. - // For stacked die always 43 are 0 - // and 6:5 == 1 for 120Mhz. - -#define STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG \ - 0x00000028 // Reading this register Base - // procesor will able to know the - // reason for the interrupt. This is - // clear only register - set by HW - // upon an interrupt to Base - // processor and can be cleared only - // by BASE processor. - -#define STACK_DIE_CTRL_O_STK_UP_IRQ_LOG \ - 0x0000002C // Reading this register Stack - // procesor will able to know the - // reason for the interrupt. This is - // clear only register - set by HW - // upon an interrupt to Stack - // processor and can be cleared only - // by Stack processor. - -#define STACK_DIE_CTRL_O_STK_CLK_EN \ - 0x00000030 // Can be written only by base - // processor. Controls the enable - // pin of the cgcs for the clocks - // going to CM3 dft ctrl block and - // Sram. - -#define STACK_DIE_CTRL_O_SPIN_LOCK_MODE \ - 0x00000034 // Can be written only by the base - // processor. Decides the ram - // sharing mode :: handshake or - // Spinlock mode. - -#define STACK_DIE_CTRL_O_BUS_FAULT_ADDR \ - 0x00000038 // Stores the last bus fault - // address. - -#define STACK_DIE_CTRL_O_BUS_FAULT_CLR \ - 0x0000003C // write only registers on read - // returns 0.W Write 1 to clear the - // bust fault to store the new bus - // fault address - -#define STACK_DIE_CTRL_O_RESET_CAUSE \ - 0x00000040 // Reset cause value captured from - // the ICR_CLKRST block. - -#define STACK_DIE_CTRL_O_WDOG_TIMER_EVENT \ - 0x00000044 // Watchdog timer event value - // captured from the ICR_CLKRST - // block - -#define STACK_DIE_CTRL_O_DMA_REQ \ - 0x00000048 // To send Dma Request to bottom - // die. - -#define STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR \ - 0x0000004C // Address offset within SRAM to - // which CM3 should jump after - // reset. - -#define STACK_DIE_CTRL_O_SW_REG1 \ - 0x00000050 // These are sw registers for - // topdie processor and bottom die - // processor to communicate. Both - // can set and read these registers. - // In case of write clash bottom - // die's processor wins and top die - // processor access is ignored. - -#define STACK_DIE_CTRL_O_SW_REG2 \ - 0x00000054 // These are sw registers for - // topdie processor and bottom die - // processor to communicate. Both - // can set and read these registers. - // In case of write clash bottom - // die's processor wins and top die - // processor access is ignored. - -#define STACK_DIE_CTRL_O_FMC_SLEEP_CTL \ - 0x00000058 // By posting the request Flash can - // be put into low-power mode - // (Sleep) without powering down the - // Flash. Earlier (in Garnet) this - // was fully h/w controlled and the - // control for this was coming from - // SysCtl while entering into Cortex - // Deep-sleep mode. But for our - // device the D2D i/f doesnt support - // this. The Firmware has to program - // the register in the top-die for - // entering into this mode and wait - // for an interrupt. - -#define STACK_DIE_CTRL_O_MISC_CTL \ - 0x0000005C // Miscellanious control register. - -#define STACK_DIE_CTRL_O_SW_DFT_CTL \ - 0x000000FC // DFT control and status bits - -#define STACK_DIE_CTRL_O_PADN_CTL_0 \ - 0x00000100 // Mainly for For controlling the - // pads OEN pins. There are total 60 - // pads and hence 60 control registe - // i.e n value varies from 0 to 59. - // Here is the mapping for the - // pad_ctl register number and the - // functionality : 0 D2DPAD_DMAREQ1 - // 1 D2DPAD_DMAREQ0 2 - // D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4 - // D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6 - // D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8 - // D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS - // 10 D2DPAD_JTAG_TDI 11-27 - // D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE - // -1:0] 28-56 D2DPAD_TOSTACK - // [D2D_TOSTACK_SIZE -1:0] 57-59 - // D2DPAD_SPARE [D2D_SPARE_PAD_SIZE - // -1:0] 0:00 - - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_UP_RESET register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_UP_RESET_UP_RESET \ - 0x00000001 // 1 :Assert Reset 0 : Deassert the - // Reset - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_SR_MASTER_PRIORITY register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_M \ - 0x00000003 // 00 : Equal Priority 01 : Stack - // Processor have priority 10 : Base - // Processor have priority 11 : - // Unused - -#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_STK_UP_ACCSS \ - 0x00000002 // Stack Processor should clear it - // when it is done with the sram - // bank usage. Set by HW It is set - // when Stack Processor is granted - // the access to this bank - -#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_BASE_UP_ACCSS \ - 0x00000001 // Base Processor should clear it - // when it is done wth the sram - // usage. Set by HW It is set when - // Base Processor is granted the - // access to this bank - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK2_ACCSS_REQ \ - 0x00000001 // Base Processor will set when - // Sram access is needed in Spin - // Lock mode. In Handshake mode - // Stack Processor will set to - // inform Base Processor that it is - // done with the processing of data - // in SRAM and is now ready to use - // by the base processor. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK2_ACCSS_REQ \ - 0x00000001 // Stack Processor will set when - // Sram access is needed in Spin - // Lock mode. In Handshake mode Base - // Processor will set to inform - // Stack Processor to start - // processing the data in the Ram. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_STK_UP_ACCSS \ - 0x00000002 // Stack Processor should clear it - // when it is done with the sram - // bank usage. Set by HW It is set - // when Stack Processor is granted - // the access to this bank. - -#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_BASE_UP_ACCSS \ - 0x00000001 // Base Processor should clear it - // when it is done wth the sram - // usage. Set by HW it is set when - // Base Processor is granted the - // access to this bank. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK3_ACCSS_REQ \ - 0x00000001 // Base Processor will set when - // Sram access is needed in Spin - // Lock mode. Not used in handshake - // mode. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK3_ACCSS_REQ \ - 0x00000001 // Stack Processor will set when - // Sram access is needed in Spin - // Lock mode. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_RDSM_CFG_CPU register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_M \ - 0x000000C0 // Bank Clock Hi Time 00 : HCLK - // pulse 01 : 1 cycle of HCLK 10 : - // 1.5 cycles of HCLK 11 : 2 cycles - // of HCLK - -#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_S 6 -#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_SENSE \ - 0x00000020 // FLCLK 0 : indicates flash clock - // rise aligns on HCLK rise 1 : - // indicates flash clock rise aligns - // on HCLK fall - -#define STACK_DIE_CTRL_RDSM_CFG_CPU_PIPELINE_FLDATA \ - 0x00000010 // 0 : Always register flash rdata - // before sending to CPU 1 : Drive - // Flash rdata directly out on MISS - // (Both ICODE / DCODE) - -#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_M \ - 0x0000000F // Number of wait states inserted - -#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_RDSM_CFG_EE register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_M \ - 0x000000C0 // Bank Clock Hi Time 00 : HCLK - // pulse 01 : 1 cycle of HCLK 10 : - // 1.5 cycles of HCLK 11 : 2 cycles - // of HCLK - -#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_S 6 -#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_SENSE \ - 0x00000020 // FLCLK 0 : indicates flash clock - // rise aligns on HCLK rise 1 : - // indicates flash clock rise aligns - // on HCLK fall - -#define STACK_DIE_CTRL_RDSM_CFG_EE_PIPELINE_FLDATA \ - 0x00000010 // 0 : Always register flash rdata - // before sending to CPU 1 : Drive - // Flash rdata directly out on MISS - // (Both ICODE / DCODE) - -#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_M \ - 0x0000000F // Number of wait states inserted - -#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_REL \ - 0x00000010 // Set when Relinquish Interrupt - // sent to Base processor for Bank3. - -#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_RELEASE \ - 0x00000008 // Set when Relinquish Interrupt - // sent to Base processor for Bank2. - -#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_GRANT \ - 0x00000004 // Set when Bank3 is granted to - // Base processor. - -#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_GRANT \ - 0x00000002 // Set when Bank2 is granted to - // BAse processor. - -#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_INVAL_ACCSS \ - 0x00000001 // Set when there Base processor do - // an Invalid access to Sram. Ex : - // Accessing the bank which is not - // granted for BAse processor. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_UP_IRQ_LOG register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_REL \ - 0x00000008 // Set when Relinquish Interrupt - // sent to Stack processor for - // Bank3. - -#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_REL \ - 0x00000004 // Set when Relinquish Interrupt - // sent to Stack processor for - // Bank2. - -#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_GRANT \ - 0x00000002 // Set when Bank3 is granted to - // Stack processor. - -#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_GRANT \ - 0x00000001 // Set when Bank2 is granted to - // Stack processor. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_STK_CLK_EN register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_STK_CLK_EN_SR_CLK \ - 0x00000004 // Enable the clock going to sram. - -#define STACK_DIE_CTRL_STK_CLK_EN_DFT_CTRL_CLK \ - 0x00000002 // Enable the clock going to dft - // control block - -#define STACK_DIE_CTRL_STK_CLK_EN_STK_UP_CLK \ - 0x00000001 // Enable the clock going to Cm3 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_SPIN_LOCK_MODE register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_SPIN_LOCK_MODE_MODE \ - 0x00000001 // 0 : Handshake Mode 1 : Spinlock - // mode. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_BUS_FAULT_ADDR register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_M \ - 0xFFFFFFFF // Fault Address - -#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_BUS_FAULT_CLR register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_BUS_FAULT_CLR_CLEAR \ - 0x00000001 // When set it'll clear the bust - // fault address register to store - // the new bus fault address - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_RESET_CAUSE register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_M \ - 0xFFFFFFFF - -#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_WDOG_TIMER_EVENT register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_M \ - 0xFFFFFFFF - -#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_DMA_REQ register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_DMA_REQ_DMAREQ1 \ - 0x00000002 // Generate DMAREQ1 on setting this - // bit. - -#define STACK_DIE_CTRL_DMA_REQ_DMAREQ0 \ - 0x00000001 // Generate DMAREQ0 on setting this - // bit. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_M \ - 0xFFFFFFFF - -#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_SW_REG1 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_M \ - 0xFFFFFFFF - -#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_SW_REG2 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_M \ - 0xFFFFFFFF - -#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_FMC_SLEEP_CTL register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_ACK \ - 0x00000002 // captures the status of of - // fmc_lpm_ack - -#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_REQ \ - 0x00000001 // When set assert - // iflpe2fmc_lpm_req to FMC. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_MISC_CTL register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_MISC_CTL_WDOG_RESET \ - 0x00000080 // 1 : will reset the async wdog - // timer runing on piosc clock - -#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ2 \ - 0x00000020 // Setting this Will send to - // interttupt to CM3 - -#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ1 \ - 0x00000010 // Setting this Will send to - // interttupt to CM3 - -#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ0 \ - 0x00000008 // Setting this Will send to - // interttupt to CM3 - -#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK3 \ - 0x00000004 // While testing Flash Setting this - // bit will Control the - // CE/STR/AIN/CLKIN going to flash - // banks 12 and 3. 0 : Control - // signals coming from FMC for Bank - // 3 goes to Bank3 1 : Control - // signals coming from FMC for Bank - // 0 goes to Bank2 - -#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK2 \ - 0x00000002 // While testing Flash Setting this - // bit will Control the - // CE/STR/AIN/CLKIN going to flash - // banks 12 and 3. 0 : Control - // signals coming from FMC for Bank - // 2 goes to Bank2 1 : Control - // signals coming from FMC for Bank - // 0 goes to Bank2 - -#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK1 \ - 0x00000001 // While testing Flash Setting this - // bit will Control the - // CE/STR/AIN/CLKIN going to flash - // banks 12 and 3. 0 : Control - // signals coming from FMC for Bank - // 1 goes to Bank1 1 : Control - // signals coming from FMC for Bank - // 0 goes to Bank1 - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_SW_DFT_CTL register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_SW_DFT_CTL_FL_CTRL_OWNS \ - 0x20000000 // when set to '1' all flash - // control signals switch over to - // CM3 control when '0' it is under - // the D2D interface control - -#define STACK_DIE_CTRL_SW_DFT_CTL_SWIF_CPU_READ \ - 0x10000000 // 1 indicates in SWIF mode the - // control signals to flash are from - // FMC CPU read controls the clock - // and address. that is one can give - // address via FMC and read through - // IDMEM. - -#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_DONE \ - 0x00800000 // 'CPU Done' bit for PBIST. Write - // '1' to indicate test done. - -#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_FAIL \ - 0x00400000 // 'CPU Fail' bit for PBIST. Write - // '1' to indicate test failed. - -#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK4_OWNS \ - 0x00001000 // when set to '1' flash bank 4 - // (EEPROM) is owned by the CM3for - // reads over DCODE bus. When '0' - // access control given to D2D - // interface. - -#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK3_OWNS \ - 0x00000800 // when set to '1' flash bank 3 is - // owned by the CM3for reads over - // DCODE bus. When '0' access - // control given to D2D interface. - -#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK2_OWNS \ - 0x00000400 // when set to '1' flash bank 2 is - // owned by the CM3for reads over - // DCODE bus. When '0' access - // control given to D2D interface. - -#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK1_OWNS \ - 0x00000200 // when set to '1' flash bank 1 is - // owned by the CM3for reads over - // DCODE bus. When '0' access - // control given to D2D interface. - -#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK0_OWNS \ - 0x00000100 // when set to '1' flash bank 0 is - // owned by the CM3 for reads over - // DCODE bus. When '0' access - // control given to D2D interface. - -//****************************************************************************** -// -// The following are defines for the bit fields in the -// STACK_DIE_CTRL_O_PADN_CTL_0 register. -// -//****************************************************************************** -#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DOUT \ - 0x00000008 // This bit is valid for only the - // spare pads ie for n=57 to 59. - // value to drive at the output of - // the pad - -#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DIN \ - 0x00000004 // This bit is valid for only the - // spare pads ie for n=57 to 59. - // captures the 'Y' pin of the pad - // which is the data being driven - // into the die - -#define STACK_DIE_CTRL_PADN_CTL_0_OEN2X \ - 0x00000002 // OEN2X control when '1' enables - // the output with 1x. Total drive - // strength is decided bu oen1x - // setting + oen2x setting. - -#define STACK_DIE_CTRL_PADN_CTL_0_OEN1X \ - 0x00000001 // OEN1X control when '1' enables - // the output with 1x . Total drive - // strength is decided bu oen1x - // setting + oen2x setting. - - - - -#endif // __HW_STACK_DIE_CTRL_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_timer.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_timer.h deleted file mode 100644 index af36c3fff3f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_timer.h +++ /dev/null @@ -1,776 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -//***************************************************************************** -// -// hw_timer.h - Defines and macros used when accessing the timer. -// -//***************************************************************************** - -//##### INTERNAL BEGIN ##### -// -// This is an auto-generated file. Do not edit by hand. -// Created by version 6779 of DriverLib. -// -//##### INTERNAL END ##### - -#ifndef __HW_TIMER_H__ -#define __HW_TIMER_H__ - -//***************************************************************************** -// -// The following are defines for the Timer register offsets. -// -//***************************************************************************** -#define TIMER_O_CFG 0x00000000 // GPTM Configuration -#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode -#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode -#define TIMER_O_CTL 0x0000000C // GPTM Control -//##### GARNET BEGIN ##### -#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize -//##### GARNET END ##### -#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask -#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status -#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status -#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear -#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load -#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load -#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match -#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match -#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale -#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale -#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match -#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match -#define TIMER_O_TAR 0x00000048 // GPTM Timer A -#define TIMER_O_TBR 0x0000004C // GPTM Timer B -#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value -#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value -#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide -#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot -#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot -#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value -#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value -#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event -#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties - - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CFG register. -// -//***************************************************************************** -#define TIMER_CFG_M 0x00000007 // GPTM Configuration -#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration -#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC) - // counter configuration -#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The - // function is controlled by bits - // 1:0 of GPTMTAMR and GPTMTBMR - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy - // Operation -#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register - // Update -#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt - // Enable -#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write -//##### GARNET END ##### -#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode -#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger -#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt - // Enable -#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction -#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode - // Select -#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode -#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode -#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy - // Operation -#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register - // Update -#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt - // Enable -#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write -//##### GARNET END ##### -#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode -#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger -#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt - // Enable -#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction -#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode - // Select -#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode -#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode -#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode -#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode -#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_CTL register. -// -//***************************************************************************** -#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level -#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger - // Enable -#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode -#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge -#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges -#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable -#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable -#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level -#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger - // Enable -#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable -#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode -#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge -#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge -#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges -#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable -#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable -//##### GARNET BEGIN ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_SYNC register. -// -//***************************************************************************** -#define TIMER_SYNC_SYNC11_M 0x00C00000 // Synchronize GPTM Timer 11 -#define TIMER_SYNC_SYNC11_TA 0x00400000 // A timeout event for Timer A of - // GPTM11 is triggered -#define TIMER_SYNC_SYNC11_TB 0x00800000 // A timeout event for Timer B of - // GPTM11 is triggered -#define TIMER_SYNC_SYNC11_TATB 0x00C00000 // A timeout event for both Timer A - // and Timer B of GPTM11 is - // triggered -#define TIMER_SYNC_SYNC10_M 0x00300000 // Synchronize GPTM Timer 10 -#define TIMER_SYNC_SYNC10_TA 0x00100000 // A timeout event for Timer A of - // GPTM10 is triggered -#define TIMER_SYNC_SYNC10_TB 0x00200000 // A timeout event for Timer B of - // GPTM10 is triggered -#define TIMER_SYNC_SYNC10_TATB 0x00300000 // A timeout event for both Timer A - // and Timer B of GPTM10 is - // triggered -#define TIMER_SYNC_SYNC9_M 0x000C0000 // Synchronize GPTM Timer 9 -#define TIMER_SYNC_SYNC9_TA 0x00040000 // A timeout event for Timer A of - // GPTM9 is triggered -#define TIMER_SYNC_SYNC9_TB 0x00080000 // A timeout event for Timer B of - // GPTM9 is triggered -#define TIMER_SYNC_SYNC9_TATB 0x000C0000 // A timeout event for both Timer A - // and Timer B of GPTM9 is - // triggered -#define TIMER_SYNC_SYNC8_M 0x00030000 // Synchronize GPTM Timer 8 -#define TIMER_SYNC_SYNC8_TA 0x00010000 // A timeout event for Timer A of - // GPTM8 is triggered -#define TIMER_SYNC_SYNC8_TB 0x00020000 // A timeout event for Timer B of - // GPTM8 is triggered -#define TIMER_SYNC_SYNC8_TATB 0x00030000 // A timeout event for both Timer A - // and Timer B of GPTM8 is - // triggered -#define TIMER_SYNC_SYNC7_M 0x0000C000 // Synchronize GPTM Timer 7 -#define TIMER_SYNC_SYNC7_TA 0x00004000 // A timeout event for Timer A of - // GPTM7 is triggered -#define TIMER_SYNC_SYNC7_TB 0x00008000 // A timeout event for Timer B of - // GPTM7 is triggered -#define TIMER_SYNC_SYNC7_TATB 0x0000C000 // A timeout event for both Timer A - // and Timer B of GPTM7 is - // triggered -#define TIMER_SYNC_SYNC6_M 0x00003000 // Synchronize GPTM Timer 6 -#define TIMER_SYNC_SYNC6_TA 0x00001000 // A timeout event for Timer A of - // GPTM6 is triggered -#define TIMER_SYNC_SYNC6_TB 0x00002000 // A timeout event for Timer B of - // GPTM6 is triggered -#define TIMER_SYNC_SYNC6_TATB 0x00003000 // A timeout event for both Timer A - // and Timer B of GPTM6 is - // triggered -#define TIMER_SYNC_SYNC5_M 0x00000C00 // Synchronize GPTM Timer 5 -#define TIMER_SYNC_SYNC5_TA 0x00000400 // A timeout event for Timer A of - // GPTM5 is triggered -#define TIMER_SYNC_SYNC5_TB 0x00000800 // A timeout event for Timer B of - // GPTM5 is triggered -#define TIMER_SYNC_SYNC5_TATB 0x00000C00 // A timeout event for both Timer A - // and Timer B of GPTM5 is - // triggered -#define TIMER_SYNC_SYNC4_M 0x00000300 // Synchronize GPTM Timer 4 -#define TIMER_SYNC_SYNC4_TA 0x00000100 // A timeout event for Timer A of - // GPTM4 is triggered -#define TIMER_SYNC_SYNC4_TB 0x00000200 // A timeout event for Timer B of - // GPTM4 is triggered -#define TIMER_SYNC_SYNC4_TATB 0x00000300 // A timeout event for both Timer A - // and Timer B of GPTM4 is - // triggered -#define TIMER_SYNC_SYNC3_M 0x000000C0 // Synchronize GPTM Timer 3 -#define TIMER_SYNC_SYNC3_TA 0x00000040 // A timeout event for Timer A of - // GPTM3 is triggered -#define TIMER_SYNC_SYNC3_TB 0x00000080 // A timeout event for Timer B of - // GPTM3 is triggered -#define TIMER_SYNC_SYNC3_TATB 0x000000C0 // A timeout event for both Timer A - // and Timer B of GPTM3 is - // triggered -#define TIMER_SYNC_SYNC2_M 0x00000030 // Synchronize GPTM Timer 2 -#define TIMER_SYNC_SYNC2_TA 0x00000010 // A timeout event for Timer A of - // GPTM2 is triggered -#define TIMER_SYNC_SYNC2_TB 0x00000020 // A timeout event for Timer B of - // GPTM2 is triggered -#define TIMER_SYNC_SYNC2_TATB 0x00000030 // A timeout event for both Timer A - // and Timer B of GPTM2 is - // triggered -#define TIMER_SYNC_SYNC1_M 0x0000000C // Synchronize GPTM Timer 1 -#define TIMER_SYNC_SYNC1_TA 0x00000004 // A timeout event for Timer A of - // GPTM1 is triggered -#define TIMER_SYNC_SYNC1_TB 0x00000008 // A timeout event for Timer B of - // GPTM1 is triggered -#define TIMER_SYNC_SYNC1_TATB 0x0000000C // A timeout event for both Timer A - // and Timer B of GPTM1 is - // triggered -#define TIMER_SYNC_SYNC0_M 0x00000003 // Synchronize GPTM Timer 0 -#define TIMER_SYNC_SYNC0_TA 0x00000001 // A timeout event for Timer A of - // GPTM0 is triggered -#define TIMER_SYNC_SYNC0_TB 0x00000002 // A timeout event for Timer B of - // GPTM0 is triggered -#define TIMER_SYNC_SYNC0_TATB 0x00000003 // A timeout event for both Timer A - // and Timer B of GPTM0 is - // triggered -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_IMR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update - // Error Interrupt Mask -//##### GARNET END ##### -#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match - // Interrupt Mask -#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt - // Mask -#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt - // Mask -#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt - // Mask -#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match - // Interrupt Mask -#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask -#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt - // Mask -#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt - // Mask -#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt - // Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RIS register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update - // Error Raw Interrupt Status -//##### GARNET END ##### -#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw - // Interrupt -#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw - // Interrupt -#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw - // Interrupt -#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw - // Interrupt -#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw - // Interrupt -#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt -#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw - // Interrupt -#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw - // Interrupt -#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_MIS register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update - // Error Masked Interrupt Status -//##### GARNET END ##### -#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked - // Interrupt -#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked - // Interrupt -#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked - // Interrupt -#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked - // Interrupt -#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked - // Interrupt -#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt -#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked - // Interrupt -#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked - // Interrupt -#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_ICR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update - // Error Interrupt Clear -//##### GARNET END ##### -#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match - // Interrupt Clear -#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt - // Clear -#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt - // Clear -#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt - // Clear -#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match - // Interrupt Clear -#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear -#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt - // Clear -#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt - // Clear -#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw - // Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAILR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load - // Register -//##### GARNET END ##### -#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load - // Register High -#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load - // Register Low -#define TIMER_TAILR_TAILRH_S 16 -#define TIMER_TAILR_TAILRL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TAILR_S 0 -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBILR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load - // Register -//##### GARNET END ##### -#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load - // Register -#define TIMER_TBILR_TBILRL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TBILR_S 0 -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAMATCHR -// register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register -//##### GARNET END ##### -#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High -#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low -#define TIMER_TAMATCHR_TAMRH_S 16 -#define TIMER_TAMATCHR_TAMRL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TAMATCHR_TAMR_S 0 -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBMATCHR -// register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register -//##### GARNET END ##### -#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low -//##### GARNET BEGIN ##### -#define TIMER_TBMATCHR_TBMR_S 0 -//##### GARNET END ##### -#define TIMER_TBMATCHR_TBMRL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte -//##### GARNET END ##### -#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale -//##### GARNET BEGIN ##### -#define TIMER_TAPR_TAPSRH_S 8 -//##### GARNET END ##### -#define TIMER_TAPR_TAPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte -//##### GARNET END ##### -#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale -//##### GARNET BEGIN ##### -#define TIMER_TBPR_TBPSRH_S 8 -//##### GARNET END ##### -#define TIMER_TBPR_TBPSR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPMR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High - // Byte -//##### GARNET END ##### -#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match -//##### GARNET BEGIN ##### -#define TIMER_TAPMR_TAPSMRH_S 8 -//##### GARNET END ##### -#define TIMER_TAPMR_TAPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPMR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High - // Byte -//##### GARNET END ##### -#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match -//##### GARNET BEGIN ##### -#define TIMER_TBPMR_TBPSMRH_S 8 -//##### GARNET END ##### -#define TIMER_TBPMR_TBPSMR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register -//##### GARNET END ##### -#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High -#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low -#define TIMER_TAR_TARH_S 16 -#define TIMER_TAR_TARL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TAR_S 0 -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBR register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register -//##### GARNET END ##### -#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B -#define TIMER_TBR_TBRL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TBR_S 0 -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAV register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value -//##### GARNET END ##### -#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High -#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low -#define TIMER_TAV_TAVH_S 16 -#define TIMER_TAV_TAVL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TAV_S 0 -//##### GARNET END ##### - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBV register. -// -//***************************************************************************** -//##### GARNET BEGIN ##### -#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value -//##### GARNET END ##### -#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register -#define TIMER_TBV_TBVL_S 0 -//##### GARNET BEGIN ##### -#define TIMER_TBV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_RTCPD register. -// -//***************************************************************************** -#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value -#define TIMER_RTCPD_RTCPD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPS register. -// -//***************************************************************************** -#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot -#define TIMER_TAPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPS register. -// -//***************************************************************************** -#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value -#define TIMER_TBPS_PSS_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TAPV register. -// -//***************************************************************************** -#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value -#define TIMER_TAPV_PSV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_TBPV register. -// -//***************************************************************************** -#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value -#define TIMER_TBPV_PSV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the TIMER_O_PP register. -// -//***************************************************************************** -#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start -#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers -#define TIMER_PP_SIZE_M 0x0000000F // Count Size -#define TIMER_PP_SIZE__0 0x00000000 // Timer A and Timer B counters are - // 16 bits each with an 8-bit - // prescale counter -#define TIMER_PP_SIZE__1 0x00000001 // Timer A and Timer B counters are - // 32 bits each with an 16-bit - // prescale counter -//##### GARNET END ##### - -//***************************************************************************** -// -// The following definitions are deprecated. -// -//***************************************************************************** -#ifndef DEPRECATED - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_CFG -// register. -// -//***************************************************************************** -#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_CTL -// register. -// -//***************************************************************************** -#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask -#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_RIS -// register. -// -//***************************************************************************** -#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status -#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status -#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat -#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status -#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status -#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status -#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_TAILR -// register. -// -//***************************************************************************** -#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode -#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_TBILR -// register. -// -//***************************************************************************** -#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the -// TIMER_O_TAMATCHR register. -// -//***************************************************************************** -#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode -#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the -// TIMER_O_TBMATCHR register. -// -//***************************************************************************** -#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_TAR -// register. -// -//***************************************************************************** -#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode -#define TIMER_TAR_TARL 0x0000FFFF // TimerA value - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_O_TBR -// register. -// -//***************************************************************************** -#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value - -//***************************************************************************** -// -// The following are deprecated defines for the reset values of the timer -// registers. -// -//***************************************************************************** -#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV -#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV -#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV -#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV -#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV -#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV -#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV -#define TIMER_RV_CFG 0x00000000 // Configuration register RV -#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV -#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV -#define TIMER_RV_CTL 0x00000000 // Control register RV -#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV -#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV -#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV -#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV -#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV -#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV -#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_TnMR -// register. -// -//***************************************************************************** -#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select -#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time -#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask -#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot -#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic -#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_TnPR -// register. -// -//***************************************************************************** -#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value - -//***************************************************************************** -// -// The following are deprecated defines for the bit fields in the TIMER_TnPMR -// register. -// -//***************************************************************************** -#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value - -#endif - -#endif // __HW_TIMER_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_types.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_types.h deleted file mode 100644 index 30f4270dd9c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_types.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_TYPES_H__ -#define __HW_TYPES_H__ - -//***************************************************************************** -// -// Define a boolean type, and values for true and false. -// -//***************************************************************************** -typedef unsigned char tBoolean; - -#ifndef true -#define true 1 -#endif - -#ifndef false -#define false 0 -#endif - -//***************************************************************************** -// -// Macros for hardware access, both direct and via the bit-band region. -// -//***************************************************************************** -#define HWREG(x) \ - (*((volatile unsigned long *)(x))) -#define HWREGH(x) \ - (*((volatile unsigned short *)(x))) -#define HWREGB(x) \ - (*((volatile unsigned char *)(x))) -#define HWREGBITW(x, b) \ - HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITH(x, b) \ - HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) -#define HWREGBITB(x, b) \ - HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ - (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) - - -#endif // __HW_TYPES_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_uart.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_uart.h deleted file mode 100644 index 9c2604ccbea..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_uart.h +++ /dev/null @@ -1,415 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_UART_H__ -#define __HW_UART_H__ - -//***************************************************************************** -// -// The following are defines for the UART register offsets. -// -//***************************************************************************** -#define UART_O_DR 0x00000000 -#define UART_O_RSR 0x00000004 -#define UART_O_ECR 0x00000004 -#define UART_O_FR 0x00000018 -#define UART_O_ILPR 0x00000020 -#define UART_O_IBRD 0x00000024 -#define UART_O_FBRD 0x00000028 -#define UART_O_LCRH 0x0000002C -#define UART_O_CTL 0x00000030 -#define UART_O_IFLS 0x00000034 -#define UART_O_IM 0x00000038 -#define UART_O_RIS 0x0000003C -#define UART_O_MIS 0x00000040 -#define UART_O_ICR 0x00000044 -#define UART_O_DMACTL 0x00000048 -#define UART_O_LCTL 0x00000090 -#define UART_O_LSS 0x00000094 -#define UART_O_LTIM 0x00000098 -#define UART_O_9BITADDR 0x000000A4 -#define UART_O_9BITAMASK 0x000000A8 -#define UART_O_PP 0x00000FC0 -#define UART_O_CC 0x00000FC8 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DR register. -// -//****************************************************************************** -#define UART_DR_OE 0x00000800 // UART Overrun Error -#define UART_DR_BE 0x00000400 // UART Break Error -#define UART_DR_PE 0x00000200 // UART Parity Error -#define UART_DR_FE 0x00000100 // UART Framing Error -#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received -#define UART_DR_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RSR register. -// -//****************************************************************************** -#define UART_RSR_OE 0x00000008 // UART Overrun Error -#define UART_RSR_BE 0x00000004 // UART Break Error -#define UART_RSR_PE 0x00000002 // UART Parity Error -#define UART_RSR_FE 0x00000001 // UART Framing Error -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ECR register. -// -//****************************************************************************** -#define UART_ECR_DATA_M 0x000000FF // Error Clear -#define UART_ECR_DATA_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FR register. -// -//****************************************************************************** -#define UART_FR_RI 0x00000100 // Ring Indicator -#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty -#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full -#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full -#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty -#define UART_FR_BUSY 0x00000008 // UART Busy -#define UART_FR_DCD 0x00000004 // Data Carrier Detect -#define UART_FR_DSR 0x00000002 // Data Set Ready -#define UART_FR_CTS 0x00000001 // Clear To Send -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ILPR register. -// -//****************************************************************************** -#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor -#define UART_ILPR_ILPDVSR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IBRD register. -// -//****************************************************************************** -#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor -#define UART_IBRD_DIVINT_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_FBRD register. -// -//****************************************************************************** -#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor -#define UART_FBRD_DIVFRAC_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCRH register. -// -//****************************************************************************** -#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select -#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 0x00000000 : - // UART_LCRH_WLEN_5 : 5 bits - // (default) 0x00000020 : - // UART_LCRH_WLEN_6 : 6 bits - // 0x00000040 : UART_LCRH_WLEN_7 : 7 - // bits 0x00000060 : - // UART_LCRH_WLEN_8 : 8 bits -#define UART_LCRH_WLEN_S 5 -#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs -#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select -#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select -#define UART_LCRH_PEN 0x00000002 // UART Parity Enable -#define UART_LCRH_BRK 0x00000001 // UART Send Break -#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length -#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) -#define UART_LCRH_WLEN_6 0x00000020 // 6 bits -#define UART_LCRH_WLEN_7 0x00000040 // 7 bits -#define UART_LCRH_WLEN_8 0x00000060 // 8 bits -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CTL register. -// -//****************************************************************************** -#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send -#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send -#define UART_CTL_RI 0x00002000 // Ring Indicator -#define UART_CTL_DCD 0x00001000 // Data Carrier Detect -#define UART_CTL_RTS 0x00000800 // Request to Send -#define UART_CTL_DTR 0x00000400 // Data Terminal Ready -#define UART_CTL_RXE 0x00000200 // UART Receive Enable -#define UART_CTL_TXE 0x00000100 // UART Transmit Enable -#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable -#define UART_CTL_LIN 0x00000040 // LIN Mode Enable -#define UART_CTL_HSE 0x00000020 // High-Speed Enable -#define UART_CTL_EOT 0x00000010 // End of Transmission -#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support -#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode -#define UART_CTL_SIREN 0x00000002 // UART SIR Enable -#define UART_CTL_UARTEN 0x00000001 // UART Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IFLS register. -// -//****************************************************************************** -#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO - // Level Select -#define UART_IFLS_RX_S 3 -#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO - // Level Select -#define UART_IFLS_TX_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_IM register. -// -//****************************************************************************** -#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask -#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask -#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask -#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask -#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt - // Mask -#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask -#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt - // Mask -#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt - // Mask -#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask -#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask -#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt - // Mask -#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt - // Mask -#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask -#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask -#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem - // Interrupt Mask -#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Mask -#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem - // Interrupt Mask -#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem - // Interrupt Mask -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_RIS register. -// -//****************************************************************************** -#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt - // Status -#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status -#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt - // Status -#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt - // Status -#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw - // Interrupt Status -#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status -#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw - // Interrupt Status -#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt - // Status -#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt - // Status -#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt - // Status -#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt - // Status -#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw - // Interrupt Status -#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt - // Status -#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt - // Status -#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw - // Interrupt Status -#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem - // Raw Interrupt Status -#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw - // Interrupt Status -#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw - // Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_MIS register. -// -//****************************************************************************** -#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt - // Status -#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt - // Status -#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt - // Status -#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt - // Status -#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked - // Interrupt Status -#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt - // Status -#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked - // Interrupt Status -#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked - // Interrupt Status -#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked - // Interrupt Status -#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked - // Interrupt Status -#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked - // Interrupt Status -#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked - // Interrupt Status -#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt - // Status -#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt - // Status -#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked - // Interrupt Status -#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem - // Masked Interrupt Status -#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked - // Interrupt Status -#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked - // Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_ICR register. -// -//****************************************************************************** -#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear -#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear -#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear -#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear -#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt - // Clear -#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear -#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt - // Clear -#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear -#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear -#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear -#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear -#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear -#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear -#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear -#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem - // Interrupt Clear -#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem - // Interrupt Clear -#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem - // Interrupt Clear -#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem - // Interrupt Clear -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_DMACTL register. -// -//****************************************************************************** -#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error -#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable -#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LCTL register. -// -//****************************************************************************** -#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 0x00000000 : - // UART_LCTL_BLEN_13T : Sync break - // length is 13T bits (default) - // 0x00000010 : UART_LCTL_BLEN_14T : - // Sync break length is 14T bits - // 0x00000020 : UART_LCTL_BLEN_15T : - // Sync break length is 15T bits - // 0x00000030 : UART_LCTL_BLEN_16T : - // Sync break length is 16T bits -#define UART_LCTL_BLEN_S 4 -#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LSS register. -// -//****************************************************************************** -#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot -#define UART_LSS_TSS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_LTIM register. -// -//****************************************************************************** -#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value -#define UART_LTIM_TIMER_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// UART_O_9BITADDR register. -// -//****************************************************************************** -#define UART_9BITADDR_9BITEN \ - 0x00008000 // Enable 9-Bit Mode - -#define UART_9BITADDR_ADDR_M \ - 0x000000FF // Self Address for 9-Bit Mode - -#define UART_9BITADDR_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// UART_O_9BITAMASK register. -// -//****************************************************************************** -#define UART_9BITAMASK_RANGE_M \ - 0x0000FF00 // Self Address Range for 9-Bit - // Mode - -#define UART_9BITAMASK_RANGE_S 8 -#define UART_9BITAMASK_MASK_M \ - 0x000000FF // Self Address Mask for 9-Bit Mode - -#define UART_9BITAMASK_MASK_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_PP register. -// -//****************************************************************************** -#define UART_PP_MSE 0x00000008 // Modem Support Extended -#define UART_PP_MS 0x00000004 // Modem Support -#define UART_PP_NB 0x00000002 // 9-Bit Support -#define UART_PP_SC 0x00000001 // Smart Card Support -//****************************************************************************** -// -// The following are defines for the bit fields in the UART_O_CC register. -// -//****************************************************************************** -#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source - // 0x00000005 : UART_CC_CS_PIOSC : - // PIOSC 0x00000000 : - // UART_CC_CS_SYSCLK : The system - // clock (default) -#define UART_CC_CS_S 0 - - - -#endif // __HW_UART_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_udma.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_udma.h deleted file mode 100644 index 8f01306ccbd..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_udma.h +++ /dev/null @@ -1,334 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_UDMA_H__ -#define __HW_UDMA_H__ - -//***************************************************************************** -// -// The following are defines for the UDMA register offsets. -// -//***************************************************************************** -#define UDMA_O_STAT 0x00000000 -#define UDMA_O_CFG 0x00000004 -#define UDMA_O_CTLBASE 0x00000008 -#define UDMA_O_ALTBASE 0x0000000C -#define UDMA_O_WAITSTAT 0x00000010 -#define UDMA_O_SWREQ 0x00000014 -#define UDMA_O_USEBURSTSET 0x00000018 -#define UDMA_O_USEBURSTCLR 0x0000001C -#define UDMA_O_REQMASKSET 0x00000020 -#define UDMA_O_REQMASKCLR 0x00000024 -#define UDMA_O_ENASET 0x00000028 -#define UDMA_O_ENACLR 0x0000002C -#define UDMA_O_ALTSET 0x00000030 -#define UDMA_O_ALTCLR 0x00000034 -#define UDMA_O_PRIOSET 0x00000038 -#define UDMA_O_PRIOCLR 0x0000003C -#define UDMA_O_ERRCLR 0x0000004C -#define UDMA_O_CHASGN 0x00000500 -#define UDMA_O_CHIS 0x00000504 -#define UDMA_O_CHMAP0 0x00000510 -#define UDMA_O_CHMAP1 0x00000514 -#define UDMA_O_CHMAP2 0x00000518 -#define UDMA_O_CHMAP3 0x0000051C -#define UDMA_O_PV 0x00000FB0 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_STAT register. -// -//****************************************************************************** -#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 -#define UDMA_STAT_DMACHANS_S 16 -#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status - // 0x00000090 : UDMA_STAT_STATE_DONE - // : Done 0x00000000 : - // UDMA_STAT_STATE_IDLE : Idle - // 0x00000010 : - // UDMA_STAT_STATE_RD_CTRL : Reading - // channel controller data - // 0x00000030 : - // UDMA_STAT_STATE_RD_DSTENDP : - // Reading destination end pointer - // 0x00000040 : - // UDMA_STAT_STATE_RD_SRCDAT : - // Reading source data 0x00000020 : - // UDMA_STAT_STATE_RD_SRCENDP : - // Reading source end pointer - // 0x00000080 : - // UDMA_STAT_STATE_STALL : Stalled - // 0x000000A0 : - // UDMA_STAT_STATE_UNDEF : Undefined - // 0x00000060 : UDMA_STAT_STATE_WAIT - // : Waiting for uDMA request to - // clear 0x00000070 : - // UDMA_STAT_STATE_WR_CTRL : Writing - // channel controller data - // 0x00000050 : - // UDMA_STAT_STATE_WR_DSTDAT : - // Writing destination data -#define UDMA_STAT_STATE_S 4 -#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CFG register. -// -//****************************************************************************** -#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CTLBASE register. -// -//****************************************************************************** -#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address -#define UDMA_CTLBASE_ADDR_S 10 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_ALTBASE register. -// -//****************************************************************************** -#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address - // Pointer -#define UDMA_ALTBASE_ADDR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_WAITSTAT register. -// -//****************************************************************************** -#define UDMA_WAITSTAT_WAITREQ_M \ - 0xFFFFFFFF // Channel [n] Wait Status - -#define UDMA_WAITSTAT_WAITREQ_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_SWREQ register. -// -//****************************************************************************** -#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request -#define UDMA_SWREQ_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// UDMA_O_USEBURSTSET register. -// -//****************************************************************************** -#define UDMA_USEBURSTSET_SET_M \ - 0xFFFFFFFF // Channel [n] Useburst Set - -#define UDMA_USEBURSTSET_SET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the -// UDMA_O_USEBURSTCLR register. -// -//****************************************************************************** -#define UDMA_USEBURSTCLR_CLR_M \ - 0xFFFFFFFF // Channel [n] Useburst Clear - -#define UDMA_USEBURSTCLR_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_REQMASKSET register. -// -//****************************************************************************** -#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set -#define UDMA_REQMASKSET_SET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_REQMASKCLR register. -// -//****************************************************************************** -#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear -#define UDMA_REQMASKCLR_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_ENASET register. -// -//****************************************************************************** -#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set -#define UDMA_ENASET_CHENSET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_ENACLR register. -// -//****************************************************************************** -#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear -#define UDMA_ENACLR_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_ALTSET register. -// -//****************************************************************************** -#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set -#define UDMA_ALTSET_SET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_ALTCLR register. -// -//****************************************************************************** -#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear -#define UDMA_ALTCLR_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_PRIOSET register. -// -//****************************************************************************** -#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set -#define UDMA_PRIOSET_SET_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_PRIOCLR register. -// -//****************************************************************************** -#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear -#define UDMA_PRIOCLR_CLR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_ERRCLR register. -// -//****************************************************************************** -#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHASGN register. -// -//****************************************************************************** -#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select -#define UDMA_CHASGN_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHIS register. -// -//****************************************************************************** -#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status -#define UDMA_CHIS_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHMAP0 register. -// -//****************************************************************************** -#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select -#define UDMA_CHMAP0_CH7SEL_S 28 -#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select -#define UDMA_CHMAP0_CH6SEL_S 24 -#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select -#define UDMA_CHMAP0_CH5SEL_S 20 -#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select -#define UDMA_CHMAP0_CH4SEL_S 16 -#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select -#define UDMA_CHMAP0_CH3SEL_S 12 -#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select -#define UDMA_CHMAP0_CH2SEL_S 8 -#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select -#define UDMA_CHMAP0_CH1SEL_S 4 -#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select -#define UDMA_CHMAP0_CH0SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHMAP1 register. -// -//****************************************************************************** -#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select -#define UDMA_CHMAP1_CH15SEL_S 28 -#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select -#define UDMA_CHMAP1_CH14SEL_S 24 -#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select -#define UDMA_CHMAP1_CH13SEL_S 20 -#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select -#define UDMA_CHMAP1_CH12SEL_S 16 -#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select -#define UDMA_CHMAP1_CH11SEL_S 12 -#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select -#define UDMA_CHMAP1_CH10SEL_S 8 -#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select -#define UDMA_CHMAP1_CH9SEL_S 4 -#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select -#define UDMA_CHMAP1_CH8SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHMAP2 register. -// -//****************************************************************************** -#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select -#define UDMA_CHMAP2_CH23SEL_S 28 -#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select -#define UDMA_CHMAP2_CH22SEL_S 24 -#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select -#define UDMA_CHMAP2_CH21SEL_S 20 -#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select -#define UDMA_CHMAP2_CH20SEL_S 16 -#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select -#define UDMA_CHMAP2_CH19SEL_S 12 -#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select -#define UDMA_CHMAP2_CH18SEL_S 8 -#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select -#define UDMA_CHMAP2_CH17SEL_S 4 -#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select -#define UDMA_CHMAP2_CH16SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_CHMAP3 register. -// -//****************************************************************************** -#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select -#define UDMA_CHMAP3_CH31SEL_S 28 -#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select -#define UDMA_CHMAP3_CH30SEL_S 24 -#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select -#define UDMA_CHMAP3_CH29SEL_S 20 -#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select -#define UDMA_CHMAP3_CH28SEL_S 16 -#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select -#define UDMA_CHMAP3_CH27SEL_S 12 -#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select -#define UDMA_CHMAP3_CH26SEL_S 8 -#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select -#define UDMA_CHMAP3_CH25SEL_S 4 -#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select -#define UDMA_CHMAP3_CH24SEL_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the UDMA_O_PV register. -// -//****************************************************************************** -#define UDMA_PV_MAJOR_M 0x0000FF00 // Major Revision -#define UDMA_PV_MAJOR_S 8 -#define UDMA_PV_MINOR_M 0x000000FF // Minor Revision -#define UDMA_PV_MINOR_S 0 - - - -#endif // __HW_UDMA_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_wdt.h b/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_wdt.h deleted file mode 100644 index 75d5591afe3..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/cc32xx/inc/hw_wdt.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef __HW_WDT_H__ -#define __HW_WDT_H__ - -//***************************************************************************** -// -// The following are defines for the WDT register offsets. -// -//***************************************************************************** -#define WDT_O_LOAD 0x00000000 -#define WDT_O_VALUE 0x00000004 -#define WDT_O_CTL 0x00000008 -#define WDT_O_ICR 0x0000000C -#define WDT_O_RIS 0x00000010 -#define WDT_O_MIS 0x00000014 -#define WDT_O_TEST 0x00000418 -#define WDT_O_LOCK 0x00000C00 - - - -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOAD register. -// -//****************************************************************************** -#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value -#define WDT_LOAD_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_VALUE register. -// -//****************************************************************************** -#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value -#define WDT_VALUE_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_CTL register. -// -//****************************************************************************** -#define WDT_CTL_WRC 0x80000000 // Write Complete -#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type -#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable. This bit - // is not used in cc3xx, WDOG shall - // always generate RESET to system - // irrespective of this bit setting. -#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_ICR register. -// -//****************************************************************************** -#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear -#define WDT_ICR_S 0 -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_RIS register. -// -//****************************************************************************** -#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_MIS register. -// -//****************************************************************************** -#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_TEST register. -// -//****************************************************************************** -#define WDT_TEST_STALL_EN_M 0x00000C00 // Watchdog stall enable -#define WDT_TEST_STALL_EN_S 10 -#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable -//****************************************************************************** -// -// The following are defines for the bit fields in the WDT_O_LOCK register. -// -//****************************************************************************** -#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock -#define WDT_LOCK_S 0 -#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked -#define WDT_LOCK_LOCKED 0x00000001 // Locked -#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer - -//***************************************************************************** -// -// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and -// WDT_MIS registers. -// -//***************************************************************************** -#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired - - - - - -#endif // __HW_WDT_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/CMakeLists.txt b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/CMakeLists.txt deleted file mode 100644 index 8776c65c411..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -zephyr_include_directories( - . - ) - -zephyr_library() -zephyr_library_compile_definitions(${COMPILER}) -zephyr_library_sources( - # Need system_msp432p401r for SystemInit which is not in ROM - startup_system_files/system_msp432p401r.c - ) - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/adc14.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/adc14.c deleted file mode 100644 index 595b7d8979a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/adc14.c +++ /dev/null @@ -1,750 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/* Standard Includes */ -#include -#include - -/* DriverLib Includes */ -#include -#include -#include - -/* Statics */ -static volatile uint32_t* const _ctlRegs[32] = -{ &ADC14->MCTL[0], &ADC14->MCTL[1], &ADC14->MCTL[2], &ADC14->MCTL[3], - &ADC14->MCTL[4], &ADC14->MCTL[5], &ADC14->MCTL[6], &ADC14->MCTL[7], - &ADC14->MCTL[8], &ADC14->MCTL[9], &ADC14->MCTL[10], - &ADC14->MCTL[11], &ADC14->MCTL[12], &ADC14->MCTL[13], - &ADC14->MCTL[14], &ADC14->MCTL[15], &ADC14->MCTL[16], - &ADC14->MCTL[17], &ADC14->MCTL[18], &ADC14->MCTL[19], - &ADC14->MCTL[20], &ADC14->MCTL[21], &ADC14->MCTL[22], - &ADC14->MCTL[23], &ADC14->MCTL[24], &ADC14->MCTL[25], - &ADC14->MCTL[26], &ADC14->MCTL[27], &ADC14->MCTL[28], - &ADC14->MCTL[29], &ADC14->MCTL[30], &ADC14->MCTL[31] }; - -static uint_fast8_t _getIndexForMemRegister(uint32_t reg) -{ - switch (reg) - { - case ADC_MEM0: - return 0; - case ADC_MEM1: - return 1; - case ADC_MEM2: - return 2; - case ADC_MEM3: - return 3; - case ADC_MEM4: - return 4; - case ADC_MEM5: - return 5; - case ADC_MEM6: - return 6; - case ADC_MEM7: - return 7; - case ADC_MEM8: - return 8; - case ADC_MEM9: - return 9; - case ADC_MEM10: - return 10; - case ADC_MEM11: - return 11; - case ADC_MEM12: - return 12; - case ADC_MEM13: - return 13; - case ADC_MEM14: - return 14; - case ADC_MEM15: - return 15; - case ADC_MEM16: - return 16; - case ADC_MEM17: - return 17; - case ADC_MEM18: - return 18; - case ADC_MEM19: - return 19; - case ADC_MEM20: - return 20; - case ADC_MEM21: - return 21; - case ADC_MEM22: - return 22; - case ADC_MEM23: - return 23; - case ADC_MEM24: - return 24; - case ADC_MEM25: - return 25; - case ADC_MEM26: - return 26; - case ADC_MEM27: - return 27; - case ADC_MEM28: - return 28; - case ADC_MEM29: - return 29; - case ADC_MEM30: - return 30; - case ADC_MEM31: - return 31; - default: - ASSERT(false); - return ADC_INVALID_MEM; - - } -} - -//***************************************************************************** -// -//! -//! Returns a boolean value that tells if conversion is active/running or is -//! not acMSP432 ted. -//! -//! Originally a public function, but moved to static. External customers should -//! use the ADC14_isBusy function. -//! -//! \return true if conversion is active, false otherwise -// -//***************************************************************************** -static bool ADCIsConversionRunning(void) -{ - return BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_BUSY_OFS); -} - -void ADC14_enableModule(void) -{ - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS) = 1; -} - -bool ADC14_disableModule(void) -{ - if (ADCIsConversionRunning()) - return false; - - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS) = 0; - - return true; -} - -bool ADC14_enableSampleTimer(uint32_t multiSampleConvert) -{ - if (ADCIsConversionRunning()) - return false; - - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SHP_OFS) = 1; - - if (multiSampleConvert == ADC_MANUAL_ITERATION) - { - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_MSC_OFS) = 0; - } else - { - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_MSC_OFS) = 1; - } - - return true; -} - -bool ADC14_disableSampleTimer(void) -{ - if (ADCIsConversionRunning()) - return false; - - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SHP_OFS) = 0; - - return true; -} - -bool ADC14_initModule(uint32_t clockSource, uint32_t clockPredivider, - uint32_t clockDivider, uint32_t internalChannelMask) -{ - ASSERT( - clockSource == ADC_CLOCKSOURCE_ADCOSC - || clockSource == ADC_CLOCKSOURCE_SYSOSC - || clockSource == ADC_CLOCKSOURCE_ACLK - || clockSource == ADC_CLOCKSOURCE_MCLK - || clockSource == ADC_CLOCKSOURCE_SMCLK - || clockSource == ADC_CLOCKSOURCE_HSMCLK); - - ASSERT( - clockPredivider == ADC_PREDIVIDER_1 - || clockPredivider == ADC_PREDIVIDER_4 - || clockPredivider == ADC_PREDIVIDER_32 - || clockPredivider == ADC_PREDIVIDER_64); - - ASSERT( - clockDivider == ADC_DIVIDER_1 || clockDivider == ADC_DIVIDER_2 - || clockDivider == ADC_DIVIDER_3 - || clockDivider == ADC_DIVIDER_4 - || clockDivider == ADC_DIVIDER_5 - || clockDivider == ADC_DIVIDER_6 - || clockDivider == ADC_DIVIDER_7 - || clockDivider == ADC_DIVIDER_8); - - ASSERT( - !(internalChannelMask - & ~(ADC_MAPINTCH3 | ADC_MAPINTCH2 | ADC_MAPINTCH1 - | ADC_MAPINTCH0 | ADC_TEMPSENSEMAP | ADC_BATTMAP))); - - if (ADCIsConversionRunning()) - return false; - - ADC14->CTL0 = (ADC14->CTL0 - & ~(ADC14_CTL0_PDIV_MASK | ADC14_CTL0_DIV_MASK | ADC14_CTL0_SSEL_MASK)) - | clockDivider | clockPredivider | clockSource; - - ADC14->CTL1 = (ADC14->CTL1 - & ~(ADC_MAPINTCH3 | ADC_MAPINTCH2 | ADC_MAPINTCH1 | ADC_MAPINTCH0 - | ADC_TEMPSENSEMAP | ADC_BATTMAP)) | internalChannelMask; - - return true; -} - -void ADC14_setResolution(uint32_t resolution) -{ - ASSERT( - resolution == ADC_8BIT || resolution == ADC_10BIT - || resolution == ADC_12BIT || resolution == ADC_14BIT); - - ADC14->CTL1 = (ADC14->CTL1 & ~ADC14_CTL1_RES_MASK) | resolution; -} - -uint_fast32_t ADC14_getResolution(void) -{ - return ADC14->CTL1 & ADC14_CTL1_RES_MASK; -} - -bool ADC14_setSampleHoldTrigger(uint32_t source, bool invertSignal) -{ - - ASSERT( - source == ADC_TRIGGER_ADCSC || source == ADC_TRIGGER_SOURCE1 - || source == ADC_TRIGGER_SOURCE2 - || source == ADC_TRIGGER_SOURCE3 - || source == ADC_TRIGGER_SOURCE4 - || source == ADC_TRIGGER_SOURCE5 - || source == ADC_TRIGGER_SOURCE6 - || source == ADC_TRIGGER_SOURCE7); - - if (ADCIsConversionRunning()) - return false; - - if (invertSignal) - { - ADC14->CTL0 = (ADC14->CTL0 - & ~(ADC14_CTL0_ISSH | ADC14_CTL0_SHS_MASK)) | source - | ADC14_CTL0_ISSH; - } else - { - ADC14->CTL0 = (ADC14->CTL0 - & ~(ADC14_CTL0_ISSH | ADC14_CTL0_SHS_MASK)) | source; - } - - return true; -} - -bool ADC14_setSampleHoldTime(uint32_t firstPulseWidth, - uint32_t secondPulseWidth) -{ - ASSERT( - firstPulseWidth == ADC_PULSE_WIDTH_4 - || firstPulseWidth == ADC_PULSE_WIDTH_8 - || firstPulseWidth == ADC_PULSE_WIDTH_16 - || firstPulseWidth == ADC_PULSE_WIDTH_32 - || firstPulseWidth == ADC_PULSE_WIDTH_64 - || firstPulseWidth == ADC_PULSE_WIDTH_96 - || firstPulseWidth == ADC_PULSE_WIDTH_128 - || firstPulseWidth == ADC_PULSE_WIDTH_192); - - ASSERT( - secondPulseWidth == ADC_PULSE_WIDTH_4 - || secondPulseWidth == ADC_PULSE_WIDTH_8 - || secondPulseWidth == ADC_PULSE_WIDTH_16 - || secondPulseWidth == ADC_PULSE_WIDTH_32 - || secondPulseWidth == ADC_PULSE_WIDTH_64 - || secondPulseWidth == ADC_PULSE_WIDTH_96 - || secondPulseWidth == ADC_PULSE_WIDTH_128 - || secondPulseWidth == ADC_PULSE_WIDTH_192); - - if (ADCIsConversionRunning()) - return false; - - ADC14->CTL0 = (ADC14->CTL0 - & ~(ADC14_CTL0_SHT0_MASK | ADC14_CTL0_SHT1_MASK)) | secondPulseWidth - | (firstPulseWidth >> 4); - - return true; -} - -bool ADC14_configureMultiSequenceMode(uint32_t memoryStart, uint32_t memoryEnd, -bool repeatMode) -{ - uint32_t ii; - - ASSERT( - _getIndexForMemRegister(memoryStart) != ADC_INVALID_MEM - && _getIndexForMemRegister(memoryEnd) != ADC_INVALID_MEM); - - if (ADCIsConversionRunning()) - return false; - - /* Clearing out any lingering EOS */ - for (ii = 0; ii < 32; ii++) - { - BITBAND_PERI(*(_ctlRegs[ii]), ADC14_MCTLN_EOS_OFS) = 0; - } - - /* Setting Start/Stop locations */ - BITBAND_PERI( - (*(_ctlRegs[_getIndexForMemRegister(memoryEnd)])), - ADC14_MCTLN_EOS_OFS) = 1; - - ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_CSTARTADD_MASK)) - | (_getIndexForMemRegister(memoryStart) << 16); - - /* Setting multiple sample mode */ - if (!repeatMode) - { - ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK)) - | (ADC14_CTL0_CONSEQ_1); - } else - { - ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK)) - | (ADC14_CTL0_CONSEQ_3); - } - - return true; -} - -bool ADC14_configureSingleSampleMode(uint32_t memoryDestination, -bool repeatMode) -{ - ASSERT(_getIndexForMemRegister(memoryDestination) != 32); - - if (ADCIsConversionRunning()) - return false; - - /* Setting the destination register */ - ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_CSTARTADD_MASK)) - | (_getIndexForMemRegister(memoryDestination) << 16); - - /* Setting single sample mode */ - if (!repeatMode) - { - ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK)) - | (ADC14_CTL0_CONSEQ_0); - } else - { - ADC14->CTL0 = (ADC14->CTL0 & ~(ADC14_CTL0_CONSEQ_MASK)) - | (ADC14_CTL0_CONSEQ_2); - } - - return true; -} - -bool ADC14_enableConversion(void) -{ - if (ADCIsConversionRunning() || !BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS)) - return false; - - ADC14->CTL0 |= (ADC14_CTL0_ENC); - - return true; -} - -bool ADC14_toggleConversionTrigger(void) -{ - if (!BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ON_OFS)) - return false; - - if (BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS)) - { - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS) = 0; - } else - { - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_SC_OFS) = 1; - } - - return true; -} - -void ADC14_disableConversion(void) -{ - ADC14->CTL0 &= ~(ADC14_CTL0_SC | ADC14_CTL0_ENC); -} - -bool ADC14_isBusy(void) -{ - return BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_BUSY_OFS); -} - -bool ADC14_configureConversionMemory(uint32_t memorySelect, uint32_t refSelect, - uint32_t channelSelect, bool differntialMode) -{ - uint32_t currentReg, ii; - uint32_t *curReg; - - /* Initialization */ - ii = 1; - currentReg = 0x01; - - if (ADCIsConversionRunning()) - return false; - - while (memorySelect != 0) - { - if (!(memorySelect & ii)) - { - ii = ii << 1; - continue; - } - - currentReg = memorySelect & ii; - memorySelect &= ~ii; - ii = ii << 1; - - curReg = (uint32_t*) _ctlRegs[_getIndexForMemRegister(currentReg)]; - - if (differntialMode) - { - (*curReg) = ((*curReg) - & ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK - | ADC14_MCTLN_DIF)) - | (channelSelect | refSelect | ADC14_MCTLN_DIF); - } else - { - (*curReg) = ((*curReg) - & ~(ADC14_MCTLN_VRSEL_MASK | ADC14_MCTLN_INCH_MASK - | ADC14_MCTLN_DIF)) | (channelSelect | refSelect); - } - - } - - return true; -} - -bool ADC14_enableComparatorWindow(uint32_t memorySelect, uint32_t windowSelect) -{ - uint32_t currentReg, ii; - uint32_t *curRegPoint; - - /* Initialization */ - ii = 1; - currentReg = 0x01; - - if (ADCIsConversionRunning()) - return false; - - while (memorySelect != 0) - { - if (!(memorySelect & ii)) - { - ii = ii << 1; - continue; - } - - currentReg = memorySelect & ii; - memorySelect &= ~ii; - ii = ii << 1; - - curRegPoint = - (uint32_t*) _ctlRegs[_getIndexForMemRegister(currentReg)]; - - if (windowSelect == ADC_COMP_WINDOW0) - { - (*curRegPoint) = ((*curRegPoint) - & ~(ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH)) - | (ADC14_MCTLN_WINC); - } else if (windowSelect == ADC_COMP_WINDOW1) - { - (*curRegPoint) |= ADC14_MCTLN_WINC | ADC14_MCTLN_WINCTH; - } - - } - - return true; -} - -bool ADC14_disableComparatorWindow(uint32_t memorySelect) -{ - uint32_t currentReg, ii; - - /* Initialization */ - ii = 1; - currentReg = 0x01; - - if (ADCIsConversionRunning()) - return false; - - while (memorySelect != 0) - { - if (!(memorySelect & ii)) - { - ii = ii << 1; - continue; - } - - currentReg = memorySelect & ii; - memorySelect &= ~ii; - ii = ii << 1; - - (*(_ctlRegs[_getIndexForMemRegister(currentReg)])) &= - ~ADC14_MCTLN_WINC; - - } - - return true; -} - -bool ADC14_setComparatorWindowValue(uint32_t window, int16_t low, int16_t high) -{ - if (ADCIsConversionRunning()) - return false; - - if(BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS)) - { - low = ((low << 2) | (0x8000 & low)) & 0xFFFC; - high = ((high << 2) | (0x8000 & high)) & 0xFFFC; - } - - if (window == ADC_COMP_WINDOW0) - { - ADC14->HI0 = (high); - ADC14->LO0 = (low); - - } else if (window == ADC_COMP_WINDOW1) - { - ADC14->HI1 = (high); - ADC14->LO1 = (low); - - } else - { - ASSERT(false); - return false; - } - - return true; -} - -bool ADC14_setResultFormat(uint32_t resultFormat) -{ - if (ADCIsConversionRunning()) - return false; - - if (resultFormat == ADC_UNSIGNED_BINARY) - { - BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS) = 0; - } else if (resultFormat == ADC_SIGNED_BINARY) - { - BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_DF_OFS) = 1; - } else - { - ASSERT(false); - } - - return true; -} - -uint_fast16_t ADC14_getResult(uint32_t memorySelect) -{ - return *((uint16_t*) (_ctlRegs[_getIndexForMemRegister(memorySelect)] - + 0x20)); -} - -void ADC14_getMultiSequenceResult(uint16_t* res) -{ - uint32_t *startAddr, *curAddr; - uint32_t ii; - - startAddr = (uint32_t*) _ctlRegs[(ADC14->CTL1 & ADC14_CTL1_CSTARTADD_MASK) - >> 16]; - - curAddr = startAddr; - - for (ii = 0; ii < 32; ii++) - { - res[ii] = *((uint16_t*)(curAddr + 32)); - - if (BITBAND_PERI((*curAddr), ADC14_MCTLN_EOS_OFS)) - break; - - if (curAddr == _ctlRegs[31]) - curAddr = (uint32_t*) _ctlRegs[0]; - else - curAddr++; - } - -} - -void ADC14_getResultArray(uint32_t memoryStart, uint32_t memoryEnd, - uint16_t* res) -{ - uint32_t ii = 0; - uint32_t *firstPoint, *secondPoint; - - bool foundEnd = false; - - ASSERT( - _getIndexForMemRegister(memoryStart) != ADC_INVALID_MEM - && _getIndexForMemRegister(memoryEnd) != ADC_INVALID_MEM); - - firstPoint = (uint32_t*) _ctlRegs[_getIndexForMemRegister(memoryStart)]; - secondPoint = (uint32_t*) _ctlRegs[_getIndexForMemRegister(memoryEnd)]; - - while (!foundEnd) - { - if (firstPoint == secondPoint) - { - foundEnd = true; - } - - res[ii] = *(((uint16_t*) firstPoint) + 0x40); - - if (firstPoint == _ctlRegs[31]) - firstPoint = (uint32_t*) _ctlRegs[0]; - else - firstPoint += 0x04; - } -} - -bool ADC14_enableReferenceBurst(void) -{ - if (ADCIsConversionRunning()) - return false; - - BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_REFBURST_OFS) = 1; - - return true; -} - -bool ADC14_disableReferenceBurst(void) -{ - if (ADCIsConversionRunning()) - return false; - - BITBAND_PERI(ADC14->CTL1, ADC14_CTL1_REFBURST_OFS) = 0; - - return true; -} - -bool ADC14_setPowerMode(uint32_t adcPowerMode) -{ - if (ADCIsConversionRunning()) - return false; - - switch (adcPowerMode) - { - case ADC_UNRESTRICTED_POWER_MODE: - ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_PWRMD_MASK)) - | (ADC14_CTL1_PWRMD_0); - break; - case ADC_ULTRA_LOW_POWER_MODE: - ADC14->CTL1 = (ADC14->CTL1 & ~(ADC14_CTL1_PWRMD_MASK)) - | (ADC14_CTL1_PWRMD_2); - break; - default: - ASSERT(false); - return false; - } - - return true; -} - -void ADC14_enableInterrupt(uint_fast64_t mask) -{ - uint32_t stat = mask & 0xFFFFFFFF; - - ADC14->IER0 |= stat; - stat = (mask >> 32); - ADC14->IER1 |= (stat); -} - -void ADC14_disableInterrupt(uint_fast64_t mask) -{ - uint32_t stat = mask & 0xFFFFFFFF; - - ADC14->IER0 &= ~stat; - stat = (mask >> 32); - ADC14->IER1 &= ~(stat); -} - -uint_fast64_t ADC14_getInterruptStatus(void) -{ - uint_fast64_t status = ADC14->IFGR1; - return ((status << 32) | ADC14->IFGR0); -} - -uint_fast64_t ADC14_getEnabledInterruptStatus(void) -{ - uint_fast64_t stat = ADC14->IER1; - - return ADC14_getInterruptStatus() & ((stat << 32) | ADC14->IER0); - -} - -void ADC14_clearInterruptFlag(uint_fast64_t mask) -{ - uint32_t stat = mask & 0xFFFFFFFF; - - ADC14->CLRIFGR0 |= stat; - stat = (mask >> 32); - ADC14->CLRIFGR1 |= (stat); -} - -void ADC14_registerInterrupt(void (*intHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - Interrupt_registerInterrupt(INT_ADC14, intHandler); - - // - // Enable the ADC interrupt. - // - Interrupt_enableInterrupt(INT_ADC14); -} - -void ADC14_unregisterInterrupt(void) -{ - // - // Disable the interrupt. - // - Interrupt_disableInterrupt(INT_ADC14); - - // - // Unregister the interrupt handler. - // - Interrupt_unregisterInterrupt(INT_ADC14); -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/adc14.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/adc14.h deleted file mode 100644 index 5a00cee307c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/adc14.h +++ /dev/null @@ -1,1068 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef ADC14_H_ -#define ADC14_H_ - -//***************************************************************************** -// -//! -//! \addtogroup adc14_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include - -//***************************************************************************** -// -// Control specific variables -// -//***************************************************************************** - -//***************************************************************************** -// -//The following are values that can be passed to ADC14_initModule -// -//***************************************************************************** -#define ADC_CLOCKSOURCE_ADCOSC (ADC14_CTL0_SSEL_0) -#define ADC_CLOCKSOURCE_SYSOSC (ADC14_CTL0_SSEL_1) -#define ADC_CLOCKSOURCE_ACLK (ADC14_CTL0_SSEL_2) -#define ADC_CLOCKSOURCE_MCLK (ADC14_CTL0_SSEL_3) -#define ADC_CLOCKSOURCE_SMCLK (ADC14_CTL0_SSEL_4) -#define ADC_CLOCKSOURCE_HSMCLK (ADC14_CTL0_SSEL_5) - -#define ADC_PREDIVIDER_1 (ADC14_CTL0_PDIV_0) -#define ADC_PREDIVIDER_4 (ADC14_CTL0_PDIV_1) -#define ADC_PREDIVIDER_32 (ADC14_CTL0_PDIV_2) -#define ADC_PREDIVIDER_64 (ADC14_CTL0_PDIV_3) - -#define ADC_DIVIDER_1 (ADC14_CTL0_DIV_0) -#define ADC_DIVIDER_2 (ADC14_CTL0_DIV_1) -#define ADC_DIVIDER_3 (ADC14_CTL0_DIV_2) -#define ADC_DIVIDER_4 (ADC14_CTL0_DIV_3) -#define ADC_DIVIDER_5 (ADC14_CTL0_DIV_4) -#define ADC_DIVIDER_6 (ADC14_CTL0_DIV_5) -#define ADC_DIVIDER_7 (ADC14_CTL0_DIV_6) -#define ADC_DIVIDER_8 (ADC14_CTL0_DIV_7) - -#define ADC_MAPINTCH3 (ADC14_CTL1_CH3MAP) -#define ADC_MAPINTCH2 (ADC14_CTL1_CH2MAP) -#define ADC_MAPINTCH1 (ADC14_CTL1_CH1MAP) -#define ADC_MAPINTCH0 (ADC14_CTL1_CH0MAP) -#define ADC_TEMPSENSEMAP (ADC14_CTL1_TCMAP) -#define ADC_BATTMAP (ADC14_CTL1_BATMAP) -#define ADC_NOROUTE 0 - -#define ADC_8BIT ADC14_CTL1_RES_0 -#define ADC_10BIT ADC14_CTL1_RES_1 -#define ADC_12BIT ADC14_CTL1_RES_2 -#define ADC_14BIT ADC14_CTL1_RES_3 - -#define ADC_TRIGGER_ADCSC ADC14_CTL0_SHS_0 -#define ADC_TRIGGER_SOURCE1 ADC14_CTL0_SHS_1 -#define ADC_TRIGGER_SOURCE2 ADC14_CTL0_SHS_2 -#define ADC_TRIGGER_SOURCE3 ADC14_CTL0_SHS_3 -#define ADC_TRIGGER_SOURCE4 ADC14_CTL0_SHS_4 -#define ADC_TRIGGER_SOURCE5 ADC14_CTL0_SHS_5 -#define ADC_TRIGGER_SOURCE6 ADC14_CTL0_SHS_6 -#define ADC_TRIGGER_SOURCE7 ADC14_CTL0_SHS_7 - -#define ADC_PULSE_WIDTH_4 ADC14_CTL0_SHT1_0 -#define ADC_PULSE_WIDTH_8 ADC14_CTL0_SHT1_1 -#define ADC_PULSE_WIDTH_16 ADC14_CTL0_SHT1_2 -#define ADC_PULSE_WIDTH_32 ADC14_CTL0_SHT1_3 -#define ADC_PULSE_WIDTH_64 ADC14_CTL0_SHT1_4 -#define ADC_PULSE_WIDTH_96 ADC14_CTL0_SHT1_5 -#define ADC_PULSE_WIDTH_128 ADC14_CTL0_SHT1_6 -#define ADC_PULSE_WIDTH_192 ADC14_CTL0_SHT1_7 - -#define ADC_NONDIFFERENTIAL_INPUTS false -#define ADC_DIFFERENTIAL_INPUTS true - -#define ADC_MEM0 0x00000001 -#define ADC_MEM1 0x00000002 -#define ADC_MEM2 0x00000004 -#define ADC_MEM3 0x00000008 -#define ADC_MEM4 0x00000010 -#define ADC_MEM5 0x00000020 -#define ADC_MEM6 0x00000040 -#define ADC_MEM7 0x00000080 -#define ADC_MEM8 0x00000100 -#define ADC_MEM9 0x00000200 -#define ADC_MEM10 0x00000400 -#define ADC_MEM11 0x00000800 -#define ADC_MEM12 0x00001000 -#define ADC_MEM13 0x00002000 -#define ADC_MEM14 0x00004000 -#define ADC_MEM15 0x00008000 -#define ADC_MEM16 0x00010000 -#define ADC_MEM17 0x00020000 -#define ADC_MEM18 0x00040000 -#define ADC_MEM19 0x00080000 -#define ADC_MEM20 0x00100000 -#define ADC_MEM21 0x00200000 -#define ADC_MEM22 0x00400000 -#define ADC_MEM23 0x00800000 -#define ADC_MEM24 0x01000000 -#define ADC_MEM25 0x02000000 -#define ADC_MEM26 0x04000000 -#define ADC_MEM27 0x08000000 -#define ADC_MEM28 0x10000000 -#define ADC_MEM29 0x20000000 -#define ADC_MEM30 0x40000000 -#define ADC_MEM31 0x80000000 - -#define ADC_VREFPOS_AVCC_VREFNEG_VSS (ADC14_MCTLN_VRSEL_0) -#define ADC_VREFPOS_INTBUF_VREFNEG_VSS (ADC14_MCTLN_VRSEL_1) -#define ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG (ADC14_MCTLN_VRSEL_14) -#define ADC_VREFPOS_EXTBUF_VREFNEG_EXTNEG (ADC14_MCTLN_VRSEL_15) - -#define ADC_INPUT_A0 (ADC14_MCTLN_INCH_0) -#define ADC_INPUT_A1 (ADC14_MCTLN_INCH_1) -#define ADC_INPUT_A2 (ADC14_MCTLN_INCH_2) -#define ADC_INPUT_A3 (ADC14_MCTLN_INCH_3) -#define ADC_INPUT_A4 (ADC14_MCTLN_INCH_4) -#define ADC_INPUT_A5 (ADC14_MCTLN_INCH_5) -#define ADC_INPUT_A6 (ADC14_MCTLN_INCH_6) -#define ADC_INPUT_A7 (ADC14_MCTLN_INCH_7) -#define ADC_INPUT_A8 (ADC14_MCTLN_INCH_8) -#define ADC_INPUT_A9 (ADC14_MCTLN_INCH_9) -#define ADC_INPUT_A10 (ADC14_MCTLN_INCH_10) -#define ADC_INPUT_A11 (ADC14_MCTLN_INCH_11) -#define ADC_INPUT_A12 (ADC14_MCTLN_INCH_12) -#define ADC_INPUT_A13 (ADC14_MCTLN_INCH_13) -#define ADC_INPUT_A14 (ADC14_MCTLN_INCH_14) -#define ADC_INPUT_A15 (ADC14_MCTLN_INCH_15) -#define ADC_INPUT_A16 (ADC14_MCTLN_INCH_16) -#define ADC_INPUT_A17 (ADC14_MCTLN_INCH_17) -#define ADC_INPUT_A18 (ADC14_MCTLN_INCH_18) -#define ADC_INPUT_A19 (ADC14_MCTLN_INCH_19) -#define ADC_INPUT_A20 (ADC14_MCTLN_INCH_20) -#define ADC_INPUT_A21 (ADC14_MCTLN_INCH_21) -#define ADC_INPUT_A22 (ADC14_MCTLN_INCH_22) -#define ADC_INPUT_A23 (ADC14_MCTLN_INCH_23) -#define ADC_INPUT_A24 (ADC14_MCTLN_INCH_24) -#define ADC_INPUT_A25 (ADC14_MCTLN_INCH_25) -#define ADC_INPUT_A26 (ADC14_MCTLN_INCH_26) -#define ADC_INPUT_A27 (ADC14_MCTLN_INCH_27) -#define ADC_INPUT_A28 (ADC14_MCTLN_INCH_28) -#define ADC_INPUT_A29 (ADC14_MCTLN_INCH_29) -#define ADC_INPUT_A30 (ADC14_MCTLN_INCH_30) -#define ADC_INPUT_A31 (ADC14_MCTLN_INCH_31) - -#define ADC_COMP_WINDOW0 0x00 -#define ADC_COMP_WINDOW1 0x01 - -#define ADC_SIGNED_BINARY 0x00 -#define ADC_UNSIGNED_BINARY 0x01 - -#define ADC_MANUAL_ITERATION 0x00 -#define ADC_AUTOMATIC_ITERATION ADC14_CTL0_MSC - -#define ADC_UNRESTRICTED_POWER_MODE ADC14_CTL1_PWRMD_0 -#define ADC_ULTRA_LOW_POWER_MODE ADC14_CTL1_PWRMD_2 - - -#define ADC_INT0 ADC14_IER0_IE0 -#define ADC_INT1 ADC14_IER0_IE1 -#define ADC_INT2 ADC14_IER0_IE2 -#define ADC_INT3 ADC14_IER0_IE3 -#define ADC_INT4 ADC14_IER0_IE4 -#define ADC_INT5 ADC14_IER0_IE5 -#define ADC_INT6 ADC14_IER0_IE6 -#define ADC_INT7 ADC14_IER0_IE7 -#define ADC_INT8 ADC14_IER0_IE8 -#define ADC_INT9 ADC14_IER0_IE9 -#define ADC_INT10 ADC14_IER0_IE10 -#define ADC_INT11 ADC14_IER0_IE11 -#define ADC_INT12 ADC14_IER0_IE12 -#define ADC_INT13 ADC14_IER0_IE13 -#define ADC_INT14 ADC14_IER0_IE14 -#define ADC_INT15 ADC14_IER0_IE15 -#define ADC_INT16 ADC14_IER0_IE16 -#define ADC_INT17 ADC14_IER0_IE17 -#define ADC_INT18 ADC14_IER0_IE18 -#define ADC_INT19 ADC14_IER0_IE19 -#define ADC_INT20 ADC14_IER0_IE20 -#define ADC_INT21 ADC14_IER0_IE21 -#define ADC_INT22 ADC14_IER0_IE22 -#define ADC_INT23 ADC14_IER0_IE23 -#define ADC_INT24 ADC14_IER0_IE24 -#define ADC_INT25 ADC14_IER0_IE25 -#define ADC_INT26 ADC14_IER0_IE26 -#define ADC_INT27 ADC14_IER0_IE27 -#define ADC_INT28 ADC14_IER0_IE28 -#define ADC_INT29 ADC14_IER0_IE29 -#define ADC_INT30 ADC14_IER0_IE30 -#define ADC_INT31 ADC14_IER0_IE31 -#define ADC_IN_INT 0x0000000200000000 -#define ADC_LO_INT 0x0000000400000000 -#define ADC_HI_INT 0x0000000800000000 -#define ADC_OV_INT 0x0000001000000000 -#define ADC_TOV_INT 0x0000002000000000 -#define ADC_RDY_INT 0x0000004000000000 - -#define ADC_INVALID_MEM 32 - -//***************************************************************************** -// -//Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! -//! Enables the ADC block. -//! -//! This will enable operation of the ADC block. -//! -//! \return none. -// -//***************************************************************************** -extern void ADC14_enableModule(void); - -//***************************************************************************** -// -//! -//! Disables the ADC block. -//! -//! This will disable operation of the ADC block. -//! -//! \return false if user is trying to disable during active conversion -// -//***************************************************************************** -extern bool ADC14_disableModule(void); - -//***************************************************************************** -// -//! -//! Initializes the ADC module and sets up the clock system divider/pre-divider. -//! This initialization function will also configure the internal/external -//! signal mapping. -//! -//! \note A call to this function while active ADC conversion is happening -//! is an invalid case and will result in a false value being returned. -//! -//! \param clockSource The clock source to use for the ADC module. -//! - \b ADC_CLOCKSOURCE_ADCOSC [DEFAULT] -//! - \b ADC_CLOCKSOURCE_SYSOSC -//! - \b ADC_CLOCKSOURCE_ACLK -//! - \b ADC_CLOCKSOURCE_MCLK -//! - \b ADC_CLOCKSOURCE_SMCLK -//! - \b ADC_CLOCKSOURCE_HSMCLK -//! -//! \param clockPredivider Divides the given clock source before feeding it -//! into the main clock divider. -//! Valid values are: -//! - \b ADC_PREDIVIDER_1 [DEFAULT] -//! - \b ADC_PREDIVIDER_4 -//! - \b ADC_PREDIVIDER_32 -//! - \b ADC_PREDIVIDER_64 -//! -//! \param clockDivider Divides the pre-divided clock source -//! Valid values are -//! - \b ADC_DIVIDER_1 [Default value] -//! - \b ADC_DIVIDER_2 -//! - \b ADC_DIVIDER_3 -//! - \b ADC_DIVIDER_4 -//! - \b ADC_DIVIDER_5 -//! - \b ADC_DIVIDER_6 -//! - \b ADC_DIVIDER_7 -//! - \b ADC_DIVIDER_8 -//! -//! \param internalChannelMask -//! Configures the internal/external pin mappings -//! for the ADC modules. This setting determines if the given ADC channel or -//! component is mapped to an external pin (default), or routed to an internal -//! component. This parameter is a bit mask where a logical high value will -//! switch the component to the internal routing. For a list of internal -//! routings, please refer to the device specific data sheet. -//! Valid values are a logical OR of the following values: -//! - \b ADC_MAPINTCH3 -//! - \b ADC_MAPINTCH2 -//! - \b ADC_MAPINTCH1 -//! - \b ADC_MAPINTCH0 -//! - \b ADC_TEMPSENSEMAP -//! - \b ADC_BATTMAP -//! - \n ADC_NOROUTE -//! If internalChannelMask is not desired, pass ADC_NOROUTE in lieu of this -//! parameter. -//! -//! \return false if the initialization fails due to an in progress conversion -//! -//! -// -//***************************************************************************** -extern bool ADC14_initModule(uint32_t clockSource, uint32_t clockPredivider, - uint32_t clockDivider, uint32_t internalChannelMask); - -//***************************************************************************** -// -//! -//! Sets the resolution of the ADC module. The default resolution is 12-bit, -//! however for power consumption concerns this can be limited to a lower -//! resolution -//! -//! \param resolution Resolution of the ADC module -//! - \b ADC_8BIT (10 clock cycle conversion time) -//! - \b ADC_10BIT (12 clock cycle conversion time) -//! - \b ADC_12BIT (14 clock cycle conversion time) -//! - \b ADC_14BIT (16 clock cycle conversion time)[DEFAULT] -//! -//! \return none -// -//***************************************************************************** -extern void ADC14_setResolution(uint32_t resolution); - -//***************************************************************************** -// -//! -//! Gets the resolution of the ADC module. -//! -//! \return Resolution of the ADC module -//! - \b ADC_8BIT (10 clock cycle conversion time) -//! - \b ADC_10BIT (12 clock cycle conversion time) -//! - \b ADC_12BIT (14 clock cycle conversion time) -//! - \b ADC_14BIT (16 clock cycle conversion time) -// -//***************************************************************************** -extern uint_fast32_t ADC14_getResolution(void); - -//***************************************************************************** -// -//! -//! Sets the source for the trigger of the ADC module. By default, this value -//! is configured to a software source (the ADCSC bit), however depending on -//! the specific device the trigger can be set to different sources (for -//! example, a timer output). These sources vary from part to part and the -//! user should refer to the device specific datasheet. -//! -//! \param source Trigger source for sampling. Possible values include: -//! - \b ADC_TRIGGER_ADCSC [DEFAULT] -//! - \b ADC_TRIGGER_SOURCE1 -//! - \b ADC_TRIGGER_SOURCE2 -//! - \b ADC_TRIGGER_SOURCE3 -//! - \b ADC_TRIGGER_SOURCE4 -//! - \b ADC_TRIGGER_SOURCE5 -//! - \b ADC_TRIGGER_SOURCE6 -//! - \b ADC_TRIGGER_SOURCE7 -//! \param invertSignal When set to true, will invert the trigger signal to a -//! falling edge. When false, will use a rising edge. -//! -//! \return false if setting fails due to an in progress conversion -// -//***************************************************************************** -extern bool ADC14_setSampleHoldTrigger(uint32_t source, bool invertSignal); - -//***************************************************************************** -// -//! -//! Sets the sample/hold time for the specified memory register range. The -//! duration of time required for a sample differs depending on the user's -//! hardware configuration. -//! -//! There are two values in the ADCC module. The first value controls -//! ADC memory locations ADC_MEMORY_0 through ADC_MEMORY_7 and -//! ADC_MEMORY_24 through ADC_MEMORY_31, while the second value -//! controls memory locations ADC_MEMORY_8 through ADC_MEMORY_23. -//! -//! \param firstPulseWidth Pulse width of the first pulse in ADCCLK cycles -//! Possible values must be one of the following: -//! - \b ADC_PULSE_WIDTH_4 [DEFAULT] -//! - \b ADC_PULSE_WIDTH_8 -//! - \b ADC_PULSE_WIDTH_16 -//! - \b ADC_PULSE_WIDTH_32 -//! - \b ADC_PULSE_WIDTH_64 -//! - \b ADC_PULSE_WIDTH_96 -//! - \b ADC_PULSE_WIDTH_128 -//! - \b ADC_PULSE_WIDTH_192 -//! \param secondPulseWidth Pulse width of the second pulse in ADCCLK -//! cycles. Possible values must be one of the following: -//! - \b ADC_PULSE_WIDTH_4 [DEFAULT] -//! - \b ADC_PULSE_WIDTH_8 -//! - \b ADC_PULSE_WIDTH_16 -//! - \b ADC_PULSE_WIDTH_32 -//! - \b ADC_PULSE_WIDTH_64 -//! - \b ADC_PULSE_WIDTH_96 -//! - \b ADC_PULSE_WIDTH_128 -//! - \b ADC_PULSE_WIDTH_192 -//! -//! \return false if setting fails due to an in progress conversion -// -//***************************************************************************** -extern bool ADC14_setSampleHoldTime(uint32_t firstPulseWidth, - uint32_t secondPulseWidth); - -//***************************************************************************** -// -//! -//! Configures the ADC module to use a multiple memory sample scheme. This -//! means that multiple samples will consecutively take place and be stored in -//! multiple memory locations. The first sample/conversion will be placed in -//! memoryStart, while the last sample will be stored in memoryEnd. -//! Each memory location should be configured individually using the -//! ADC14_configureConversionMemory function. -//! -//! The ADC module can be started in "repeat" mode which will cause the -//! ADC module to resume sampling once the initial sample/conversion set is -//! executed. For multi-sample mode, this means that the sampling of the -//! entire memory provided. -//! -//! \param memoryStart Memory location to store first sample/conversion -//! value. Possible values include: -//! - \b ADC_MEM0 through \b ADC_MEM31 -//! \param memoryEnd Memory location to store last sample. -//! Possible values include: -//! - \b ADC_MEM0 through \b ADC_MEM31 -//! \param repeatMode Specifies whether or not to repeat the conversion/sample -//! cycle after the first round of sample/conversions. Valid values -//! are true or false. -//! -//! \return false if setting fails due to an in progress conversion -// -//***************************************************************************** -extern bool ADC14_configureMultiSequenceMode(uint32_t memoryStart, - uint32_t memoryEnd, bool repeatMode); - -//***************************************************************************** -// -//! -//! Configures the ADC module to use a a single ADC memory location for -//! sampling/conversion. This is used when only one channel might be needed for -//! conversion, or where using a multiple sampling scheme is not important. -//! -//! The ADC module can be started in "repeat" mode which will cause the -//! ADC module to resume sampling once the initial sample/conversion set is -//! executed. In single sample mode, this will cause the ADC module to -//! continuously sample into the memory destination provided. - -//! \param memoryDestination Memory location to store sample/conversion -//! value. Possible values include: -//! - \b ADC_MEM0 through \b ADC_MEM31 -//! -//! \param repeatMode Specifies whether or not to repeat the conversion/sample -//! cycle after the first round of sample/conversions -//! -//! \return false if setting fails due to an in progress conversion -// -//***************************************************************************** -extern bool ADC14_configureSingleSampleMode(uint32_t memoryDestination, - bool repeatMode); - -//***************************************************************************** -// -//! -//! Enables conversion of ADC data. Note that this only enables conversion. -//! To trigger the conversion, you will have to call the -//! ADC14_toggleConversionTrigger or use the source trigger configured in -//! ADC14_setSampleHoldTrigger. -//! -//! \return false if setting fails due to an in progress conversion -// -//***************************************************************************** -extern bool ADC14_enableConversion(void); - -//***************************************************************************** -// -//! -//! Halts conversion conversion of the ADC module. Note that the software bit -//! for triggering conversions will also be cleared with this function. -//! -//! If multi-sequence conversion mode was enabled, the position of the last -//! completed conversion can be retrieved using ADCLastConversionMemoryGet -//! -//! \return none -// -//***************************************************************************** -extern void ADC14_disableConversion(void); - -//***************************************************************************** -// -//! -//! Toggles the trigger for conversion of the ADC module by toggling the -//! trigger software bit. Note that this will cause the ADC to start -//! conversion regardless if the software bit was set as the trigger using -//! ADC14_setSampleHoldTrigger. -//! -//! \return false if setting fails due to an in progress conversion -// -//***************************************************************************** -extern bool ADC14_toggleConversionTrigger(void); - -//***************************************************************************** -// -//! -//! Returns a boolean value that tells if a conversion/sample is in progress -//! -//! \return true if conversion is active, false otherwise -// -//***************************************************************************** -extern bool ADC14_isBusy(void); - -//***************************************************************************** -// -//! -//! Configures an individual memory location for the ADC module. -//! -//! \param memorySelect is the individual ADC memory location to -//! configure. If multiple memory locations want to be configured with the -//! same configuration, this value can be logically ORed together with other -//! values. -//! - \b ADC_MEM0 through \b ADC_MEM31 -//! \param refSelect is the voltage reference to use for the selected -//! memory spot. Possible values include: -//! - \b ADC_VREFPOS_AVCC_VREFNEG_VSS [DEFAULT] -//! - \b ADC_VREFPOS_INTBUF_VREFNEG_VSS -//! - \b ADC_VREFPOS_EXTPOS_VREFNEG_EXTNEG -//! - \b ADC_VREFPOS_EXTBUF_VREFNEG_EXTNEG -//! \param channelSelect selects the channel to be used for ADC sampling. -//! Note if differential mode is enabled, the value sampled will be -//! equal to the difference between the corresponding even/odd memory -//! locations. Possible values are: -//! - \b ADC_INPUT_A0 through \b ADC_INPUT_A31 -//! -//! \param differntialMode selects if the channel selected by the -//! channelSelect will be configured in differential mode. If this -//! parameter is given as true, the configured channel will be paired -//! with its neighbor in differential mode. for example, if channel A0 or A1 -//! is selected, the channel configured will be the difference between A0 -//! and A1. If A2 or A3 are selected, the channel configured will be the -//! difference between A2 and A3 (and so on). Users can enter true or false, -//! or one of the following values: -//! - ADC_NONDIFFERENTIAL_INPUTS -//! - ADC_DIFFERENTIAL_INPUTS -//! -//! -//! \return false if setting fails due to an in progress conversion -//! -// -//***************************************************************************** -extern bool ADC14_configureConversionMemory(uint32_t memorySelect, - uint32_t refSelect, uint32_t channelSelect, bool differntialMode); - -//***************************************************************************** -// -//! -//! Enables the specified mask of memory channels to use the specified -//! comparator window. THe ADCC module has two different comparator windows -//! that can be set with this function. -//! -//! \param memorySelect is the mask of memory locations to enable the -//! comparator window for. This can be a bitwise OR of the following -//! values: -//! - \b ADC_MEM0 through \b ADC_MEM31 -//! \param windowSelect Memory location to store sample/conversion -//! value. Possible values include: -//! \b ADCOMP_WINDOW0 [DEFAULT] -//! \b ADCOMP_WINDOW1 -//! -//! \return false if setting fails due to an in progress conversion -// -//***************************************************************************** -extern bool ADC14_enableComparatorWindow(uint32_t memorySelect, - uint32_t windowSelect); - -//***************************************************************************** -// -//! -//! Disables the comparator window on the specified memory channels -//! -//! \param memorySelect is the mask of memory locations to disable the -//! comparator window for. This can be a bitwise OR of the following -//! values: -//! - \b ADC_MEM0 through \b ADC_MEM31 -//! -//! \return false if setting fails due to an in progress conversion -// -//***************************************************************************** -extern bool ADC14_disableComparatorWindow(uint32_t memorySelect); - -//***************************************************************************** -// -//! -//! Sets the lower and upper limits of the specified window comparator. Note -//! that this function will truncate values based of the resolution/data -//! format configured. If the ADC is operating in 10-bit mode, and a 12-bit -//! value is passed into this function the most significant 2 bits will be -//! truncated. -//! -//! The parameters provided to this function for the upper and lower threshold -//! depend on the current resolution for the ADC. For example, if configured -//! in 12-bit mode, a 12-bit resolution is the maximum that can be provided -//! for the window. If in 2's complement mode, Bit 15 is used as the MSB. -//! -//! \param window Memory location to store sample/conversion -//! value. Possible values include: -//! \b ADC_COMP_WINDOW0 [DEFAULT] -//! \b ADC_COMP_WINDOW1 -//! \param low is the lower limit of the window comparator -//! \param high is the upper limit of the window comparator -//! -//! \return false if setting fails due to an in progress conversion -//! -// -//***************************************************************************** -extern bool ADC14_setComparatorWindowValue(uint32_t window, int16_t low, - int16_t high); - -//***************************************************************************** -// -//! -//! Switches between a binary unsigned data format and a signed 2's complement -//! data format. -//! -//! \param resultFormat Format for result to conversion results. -//! Possible values include: -//! \b ADC_UNSIGNED_BINARY [DEFAULT] -//! \b ADC_SIGNED_BINARY -//! -//! \return false if setting fails due to an in progress conversion -//! -// -//***************************************************************************** -extern bool ADC14_setResultFormat(uint32_t resultFormat); - -//***************************************************************************** -// -//! -//! Returns the conversion result for the specified memory channel in the format -//! assigned by the ADC14_setResultFormat (unsigned binary by default) function. -//! -//! \param memorySelect is the memory location to get the conversion result. -//! Valid values are: -//! - \b ADC_MEM0 through \b ADC_MEM31 -//! \return conversion result of specified memory channel -//! -// -//***************************************************************************** -extern uint_fast16_t ADC14_getResult(uint32_t memorySelect); - -//***************************************************************************** -// -//! -//! Returns the conversion results of the currently configured multi-sequence -//! conversion. If a multi-sequence conversion has not happened, this value -//! is unreliable. Note that it is up to the user to verify the integrity of -//! and proper size of the array being passed. If there are 16 multi-sequence -//! results, and an array with only 4 elements allocated is passed, invalid -//! memory settings will occur -//! -//! \param res conversion result of the last multi-sequence sample -//! in an array of unsigned 16-bit integers -//! -//! \return None -//! -// -//***************************************************************************** -extern void ADC14_getMultiSequenceResult(uint16_t* res); - -//***************************************************************************** -// -//! -//! Returns the conversion results of the specified ADC memory locations. -//! Note that it is up to the user to verify the integrity of -//! and proper size of the array being passed. If there are 16 multi-sequence -//! results, and an array with only 4 elements allocated is passed, invalid -//! memory settings will occur. This function is inclusive. -//! -//! \param memoryStart is the memory location to get the conversion result. -//! Valid values are: -//! - \b ADC_MEM0 through \b ADC_MEM31 -//! -//! \param memoryEnd is the memory location to get the conversion result. -//! Valid values are: -//! - \b ADC_MEM0 through \b ADC_MEM31 -//! \param res conversion result of the last multi-sequence sample -//! in an array of unsigned 16-bit integers -//! -//! \return None -//! -// -//***************************************************************************** -extern void ADC14_getResultArray(uint32_t memoryStart, uint32_t memoryEnd, - uint16_t* res); - -//***************************************************************************** -// -//! -//! Enables the "on-demand" activity of the voltage reference register. If this -//! setting is enabled, the internal voltage reference buffer will only be -//! updated during a sample or conversion cycle. This is used to optimize -//! power consumption. -//! -//! \return false if setting fails due to an in progress conversion -//! -// -//***************************************************************************** -extern bool ADC14_enableReferenceBurst(void); - -//***************************************************************************** -// -//! -//! Disables the "on-demand" activity of the voltage reference register. -//! -//! \return false if setting fails due to an in progress conversion -//! -// -//***************************************************************************** -extern bool ADC14_disableReferenceBurst(void); - -//***************************************************************************** -// -//! -//! Sets the power mode of the ADC module. A more aggressive power mode will -//! restrict the number of samples per second for sampling while optimizing -//! power consumption. Ideally, if power consumption is a concern, this value -//! should be set to the most restrictive setting that satisfies your sampling -//! requirement. -//! -//! \param adcPowerMode is the power mode to set. Valid values are: -//! - \b ADC_UNRESTRICTED_POWER_MODE (no restriction) -//! - \b ADC_LOW_POWER_MODE (500ksps restriction) -//! - \b ADC_ULTRA_LOW_POWER_MODE (200ksps restriction) -//! - \b ADC_EXTREME_LOW_POWER_MODE (50ksps restriction) -//! -//! \return false if setting fails due to an in progress conversion -//! -// -//***************************************************************************** -extern bool ADC14_setPowerMode(uint32_t powerMode); - -//***************************************************************************** -// -//! -//! Enables SAMPCON to be sourced from the sampling timer and to configures -//! multi sample and conversion mode. -//! \param multiSampleConvert - Switches between manual and automatic -//! iteration when using the sample timer. Valid values are: -//! - \b ADC_MANUAL_ITERATION The user will have to manually set the SHI signal -//! ( usually by ADC14_toggleConversionTrigger ) at the end -//! of each sample/conversion cycle. -//! - \b ADC_AUTOMATIC_ITERATION After one sample/convert is finished, the ADC -//! module will automatically continue on to the next sample -//! -//! \return false if the initialization fails due to an in progress conversion -// -//***************************************************************************** -extern bool ADC14_enableSampleTimer(uint32_t multiSampleConvert); - -//***************************************************************************** -// -//! -//! Disables SAMPCON from being sourced from the sample timer. -//! -//! \return false if the initialization fails due to an in progress conversion -// -//***************************************************************************** -extern bool ADC14_disableSampleTimer(void); - -//***************************************************************************** -// -//! -//! Enables the indicated ADCC interrupt sources. The ADC_INT0 -//! through ADC_INT31 parameters correspond to a completion event of the -//! corresponding memory location. For example, when the ADC_MEM0 location -//! finishes a conversion cycle, the ADC_INT0 interrupt will be set. -//! -//! \param mask is the bit mask of interrupts to enable. -//! Valid values are a bitwise OR of the following values: -//! - \b ADC_INT0 through ADC_INT31 -//! - \b ADC_IN_INT - Interrupt enable for a conversion in the result -//! register is either greater than the ADCLO or -//! lower than the ADCHI threshold. -//! - \b ADC_LO_INT - Interrupt enable for the falling short of the -//! lower limit interrupt of the window comparator for -//! the result register. -//! - \b ADC_HI_INT - Interrupt enable for the exceeding the upper -//! limit of the window comparator for the result -//! register. -//! - \b ADC_OV_INT - Interrupt enable for a conversion that is about -//! to save to a memory buffer that has not been read -//! out yet. -//! - \b ADC_TOV_INT -Interrupt enable for a conversion that is about -//! to start before the previous conversion has been -//! completed. -//! - \b ADC_RDY_INT -Interrupt enable for the local buffered reference -//! ready signal. -//! -//! -//! \return NONE -// -//***************************************************************************** -extern void ADC14_enableInterrupt(uint_fast64_t mask); - -//***************************************************************************** -// -//! -//! Disables the indicated ADCC interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. The ADC_INT0 through ADC_INT31 -//! parameters correspond to a completion event of the corresponding memory -//! location. For example, when the ADC_MEM0 location finishes a conversion -//! cycle, the ADC_INT0 interrupt will be set. -//! -//! \param mask is the bit mask of interrupts to disable. -//! Valid values are a bitwise OR of the following values: -//! - \b ADC_INT0 through ADC_INT31 -//! - \b ADC_IN_INT - Interrupt enable for a conversion in the result -//! register is either greater than the ADCLO or -//! lower than the ADCHI threshold. -//! - \b ADC_LO_INT - Interrupt enable for the falling short of the -//! lower limit interrupt of the window comparator for -//! the result register. -//! - \b ADC_HI_INT - Interrupt enable for the exceeding the upper -//! limit of the window comparator for the result -//! register. -//! - \b ADC_OV_INT - Interrupt enable for a conversion that is about -//! to save to a memory buffer that has not been read -//! out yet. -//! - \b ADC_TOV_INT -Interrupt enable for a conversion that is about -//! to start before the previous conversion has been -//! completed. -//! - \b ADC_RDY_INT -Interrupt enable for the local buffered reference -//! ready signal. -//! -//! -//! \return NONE -// -//***************************************************************************** -extern void ADC14_disableInterrupt(uint_fast64_t mask); - -//***************************************************************************** -// -//! -//! Returns the status of a the ADC interrupt register. The ADC_INT0 -//! through ADC_INT31 parameters correspond to a completion event of the -//! corresponding memory location. For example, when the ADC_MEM0 location -//! finishes a conversion cycle, the ADC_INT0 interrupt will be set. -//! -//! \return The interrupt status. Value is a bitwise OR of the following values: -//! - \b ADC_INT0 through ADC_INT31 -//! - \b ADC_IN_INT - Interrupt enable for a conversion in the result -//! register is either greater than the ADCLO or -//! lower than the ADCHI threshold. -//! - \b ADC_LO_INT - Interrupt enable for the falling short of the -//! lower limit interrupt of the window comparator for -//! the result register. -//! - \b ADC_HI_INT - Interrupt enable for the exceeding the upper -//! limit of the window comparator for the result -//! register. -//! - \b ADC_OV_INT - Interrupt enable for a conversion that is about -//! to save to a memory buffer that has not been read -//! out yet. -//! - \b ADC_TOV_INT -Interrupt enable for a conversion that is about -//! to start before the previous conversion has been -//! completed. -//! - \b ADC_RDY_INT -Interrupt enable for the local buffered reference -//! ready signal. -//! -//! -// -//***************************************************************************** -extern uint_fast64_t ADC14_getInterruptStatus(void); - -//***************************************************************************** -// -//! -//! Returns the status of a the ADC interrupt register masked with the -//! enabled interrupts. This function is useful to call in ISRs to get a list -//! of pending interrupts that are actually enabled and could have caused the -//! ISR. The ADC_INT0 through ADC_INT31 parameters correspond to a -//! completion event of the corresponding memory location. For example, -//! when the ADC_MEM0 location finishes a conversion cycle, the ADC_INT0 -// !interrupt will be set. -//! -//! \return The interrupt status. Value is a bitwise OR of the following values: -//! - \b ADC_INT0 through ADC_INT31 -//! - \b ADC_IN_INT - Interrupt enable for a conversion in the result -//! register is either greater than the ADCLO or -//! lower than the ADCHI threshold. -//! - \b ADC_LO_INT - Interrupt enable for the falling short of the -//! lower limit interrupt of the window comparator for -//! the result register. -//! - \b ADC_HI_INT - Interrupt enable for the exceeding the upper -//! limit of the window comparator for the result -//! register. -//! - \b ADC_OV_INT - Interrupt enable for a conversion that is about -//! to save to a memory buffer that has not been read -//! out yet. -//! - \b ADC_TOV_INT -Interrupt enable for a conversion that is about -//! to start before the previous conversion has been -//! completed. -//! - \b ADC_RDY_INT -Interrupt enable for the local buffered reference -//! ready signal. -//! -//! -// -//***************************************************************************** -extern uint_fast64_t ADC14_getEnabledInterruptStatus(void); - -//***************************************************************************** -// -//! -//! Clears the indicated ADCC interrupt sources. -//! -//! \param mask is the bit mask of interrupts to clear. The ADC_INT0 -//! through ADC_INT31 parameters correspond to a completion event of the -//! corresponding memory location. For example, when the ADC_MEM0 location -//! finishes a conversion cycle, the ADC_INT0 interrupt will be set. -//! Valid values are a bitwise OR of the following values: -//! - \b ADC_INT0 through ADC_INT31 -//! - \b ADC_IN_INT - Interrupt enable for a conversion in the result -//! register is either greater than the ADCLO or -//! lower than the ADCHI threshold. -//! - \b ADC_LO_INT - Interrupt enable for the falling short of the -//! lower limit interrupt of the window comparator for -//! the result register. -//! - \b ADC_HI_INT - Interrupt enable for the exceeding the upper -//! limit of the window comparator for the result -//! register. -//! - \b ADC_OV_INT - Interrupt enable for a conversion that is about -//! to save to a memory buffer that has not been read -//! out yet. -//! - \b ADC_TOV_INT -Interrupt enable for a conversion that is about -//! to start before the previous conversion has been -//! completed. -//! - \b ADC_RDY_INT -Interrupt enable for the local buffered reference -//! ready signal. -//! -//! -//! \return NONE -// -//***************************************************************************** -extern void ADC14_clearInterruptFlag(uint_fast64_t mask); - -//***************************************************************************** -// -//! -//! Registers an interrupt handler for the ADC interrupt. -//! -//! \param intHandler is a pointer to the function to be called when the ADC -//! interrupt occurs. -//! -//! This function registers the handler to be called when an ADC -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific ADC14 interrupts must be enabled -//! via ADC14_enableInterrupt(). It is the interrupt handler's responsibility -//! to clear the interrupt source via ADC14_clearInterruptFlag(). -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void ADC14_registerInterrupt(void (*intHandler)(void)); - -//***************************************************************************** -// -//! -//! Unregisters the interrupt handler for the ADCC module. -//! -//! This function unregisters the handler to be called when an ADCC -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void ADC14_unregisterInterrupt(void); - -/* Defines for future devices that might have multiple instances */ -#define ADC14_enableModuleMultipleInstance(a) ADC14_enableModule() -#define ADC14_disableModuleMultipleInstance(a) ADC14_disableModule() -#define ADC14_initModuleMultipleInstance(a,b,c,d,e) ADC14_initModule(b,c,d,e) -#define ADC14_setResolutionMultipleInstance(a,b) ADC14_setResolution(b) -#define ADC14_getResolutionMultipleInstance(a) ADC14_getResolution() -#define ADC14_setSampleHoldTriggerMultipleInstance(a,b,c) ADC14_setSampleHoldTrigger(b,c) -#define ADC14_setSampleHoldTimeMultipleInstance(a,b,c) ADC14_setSampleHoldTime(b,c) -#define ADC14_configureMultiSequenceModeMultipleInstance(a,b,c,d) ADC14_configureMultiSequenceMode(b,c,d) -#define ADC14_configureSingleSampleModeMultipleInstance(a,b,c) ADC14_configureSingleSampleMode(b,c) -#define ADC14_enableConversionMultipleInstance(a,b) ADC14_enableConversion(b) -#define ADC14_disableConversionMultipleInstance(a) ADC14_disableConversion() -#define ADC14_toggleConversionTriggerMultipleInstance(a) ADC14_toggleConversionTrigger() -#define ADC14_isBusyMultipleInstance(a) ADC14_isBusy() -#define ADC14_configureConversionMemoryMultipleInstance(a,b,c,d,e) ADC14_configureConversionMemory(b,c,d,e) -#define ADC14_enableComparatorWindowMultipleInstance(a,b,c) ADC14_enableComparatorWindow(b,c) -#define ADC14_disableComparatorWindowMultipleInstance(a,b) ADC14_disableComparatorWindow(b) -#define ADC14_setComparatorWindowValueMultipleInstance(a,b,c,d) ADC14_setComparatorWindowValue(b,c,d) -#define ADC14_setResultFormatMultipleInstance(a,b) ADC14_setResultFormat(b) -#define ADC14_getResultMultipleInstance(a,b) ADC14_getResult(b) -#define ADC14_getMultiSequenceResultMultipleInstance(a,b) ADC14_getMultiSequenceResult(b) -#define ADC14_getResultArrayMultipleInstance(a,b,c,d) ADC14_getResultArray(b,c,d) -#define ADC14_enableReferenceBurstMultipleInstance(a) ADC14_enableReferenceBurst() -#define ADC14_disableReferenceBurstMultipleInstance(a) ADC14_disableReferenceBurst() -#define ADC14_setPowerModeMultipleInstance(a,b) ADC14_setPowerMode(b) -#define ADC14_enableSampleTimerMultipleInstance(a,b) ADC14_enableSampleTimer(b) -#define ADC14_disableSampleTimerMultipleInstance(a) ADC14_disableSampleTimer() -#define ADC14_enableInterruptMultipleInstance(a,b) ADC14_enableInterrupt(b) -#define ADC14_disableInterruptMultipleInstance(a,b) ADC14_disableInterrupt(b) -#define ADC14_getInterruptStatusMultipleInstance(a) ADC14_getInterruptStatus() -#define ADC14_getEnabledInterruptStatusMultipleInstance(a) ADC14_getEnabledInterruptStatus() -#define ADC14_clearInterruptFlagMultipleInstance(a,b) ADC14_clearInterruptFlag(b) -#define ADC14_registerInterruptMultipleInstance(a,b) ADC14_registerInterrupt(b) -#define ADC14_unregisterInterruptMultipleInstance(a) ADC14_unregisterInterrupt() - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* ADC14_H_ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/aes256.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/aes256.c deleted file mode 100644 index 19e932b763c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/aes256.c +++ /dev/null @@ -1,350 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include - -bool AES256_setCipherKey(uint32_t moduleInstance, const uint8_t * cipherKey, - uint_fast16_t keyLength) -{ - uint_fast8_t i; - uint16_t sCipherKey; - - AES256_CMSIS(moduleInstance)->CTL0 |= 0; - - switch (keyLength) - { - case AES256_KEYLENGTH_128BIT: - AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT; - break; - - case AES256_KEYLENGTH_192BIT: - AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT; - break; - - case AES256_KEYLENGTH_256BIT: - AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT; - break; - default: - return false; - } - - keyLength = keyLength / 8; - - for (i = 0; i < keyLength; i = i + 2) - { - sCipherKey = (uint16_t) (cipherKey[i]); - sCipherKey = sCipherKey | ((uint16_t) (cipherKey[i + 1]) << 8); - AES256_CMSIS(moduleInstance)->KEY = sCipherKey; - } - - // Wait until key is written - while (!BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS)) - ; - - return true; -} - -void AES256_encryptData(uint32_t moduleInstance, const uint8_t * data, - uint8_t * encryptedData) -{ - uint_fast8_t i; - uint16_t tempData = 0; - uint16_t tempVariable = 0; - - // Set module to encrypt mode - AES256_CMSIS(moduleInstance)->CTL0 &= ~AES256_CTL0_OP_MASK; - - // Write data to encrypt to module - for (i = 0; i < 16; i = i + 2) - { - tempVariable = (uint16_t) (data[i]); - tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8); - AES256_CMSIS(moduleInstance)->DIN = tempVariable; - } - - // Key that is already written shall be used - // Encryption is initialized by setting AES256_STAT_KEYWR to 1 - BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1; - - // Wait unit finished ~167 MCLK - while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS)) - ; - - // Write encrypted data back to variable - for (i = 0; i < 16; i = i + 2) - { - tempData = AES256_CMSIS(moduleInstance)->DOUT; - *(encryptedData + i) = (uint8_t) tempData; - *(encryptedData + i + 1) = (uint8_t) (tempData >> 8); - } -} - -void AES256_decryptData(uint32_t moduleInstance, const uint8_t * data, - uint8_t * decryptedData) -{ - uint_fast8_t i; - uint16_t tempData = 0; - uint16_t tempVariable = 0; - - // Set module to decrypt mode - AES256_CMSIS(moduleInstance)->CTL0 |= (AES256_CTL0_OP_3); - - // Write data to decrypt to module - for (i = 0; i < 16; i = i + 2) - { - tempVariable = (uint16_t) (data[i + 1] << 8); - tempVariable = tempVariable | ((uint16_t) (data[i])); - AES256_CMSIS(moduleInstance)->DIN = tempVariable; - } - - // Key that is already written shall be used - // Now decryption starts - BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1; - - // Wait unit finished ~167 MCLK - while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS)) - ; - - // Write encrypted data back to variable - for (i = 0; i < 16; i = i + 2) - { - tempData = AES256_CMSIS(moduleInstance)->DOUT; - *(decryptedData + i) = (uint8_t) tempData; - *(decryptedData + i + 1) = (uint8_t) (tempData >> 8); - } -} - -bool AES256_setDecipherKey(uint32_t moduleInstance, const uint8_t * cipherKey, - uint_fast16_t keyLength) -{ - uint8_t i; - uint16_t tempVariable = 0; - - // Set module to decrypt mode - AES256_CMSIS(moduleInstance)->CTL0 = - (AES256_CMSIS(moduleInstance)->CTL0 & ~AES256_CTL0_OP_MASK) | AES256_CTL0_OP1; - - switch (keyLength) - { - case AES256_KEYLENGTH_128BIT: - AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT; - break; - - case AES256_KEYLENGTH_192BIT: - AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT; - break; - - case AES256_KEYLENGTH_256BIT: - AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT; - break; - - default: - return false; - } - - keyLength = keyLength / 8; - - // Write cipher key to key register - for (i = 0; i < keyLength; i = i + 2) - { - tempVariable = (uint16_t) (cipherKey[i]); - tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8); - AES256_CMSIS(moduleInstance)->KEY = tempVariable; - } - - // Wait until key is processed ~52 MCLK - while (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS)) - ; - - return true; -} - -void AES256_clearInterruptFlag(uint32_t moduleInstance) -{ - BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIFG_OFS) = 0; -} - -uint32_t AES256_getInterruptFlagStatus(uint32_t moduleInstance) -{ - return BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_RDYIFG_OFS); -} - -void AES256_enableInterrupt(uint32_t moduleInstance) -{ - BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIE_OFS) = 1; -} - -void AES256_disableInterrupt(uint32_t moduleInstance) -{ - BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_RDYIE_OFS) = 0; -} - -void AES256_reset(uint32_t moduleInstance) -{ - BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0,AES256_CTL0_SWRST_OFS) = 1; -} - -void AES256_startEncryptData(uint32_t moduleInstance, const uint8_t * data) -{ - uint8_t i; - uint16_t tempVariable = 0; - - // Set module to encrypt mode - AES256_CMSIS(moduleInstance)->CTL0 &= ~AES256_CTL0_OP_MASK; - - // Write data to encrypt to module - for (i = 0; i < 16; i = i + 2) - { - tempVariable = (uint16_t) (data[i]); - tempVariable = tempVariable | ((uint16_t) (data[i + 1]) << 8); - AES256_CMSIS(moduleInstance)->DIN = tempVariable; - } - - // Key that is already written shall be used - // Encryption is initialized by setting AES256_STAT_KEYWR to 1 - BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1; -} - -void AES256_startDecryptData(uint32_t moduleInstance, const uint8_t * data) -{ - uint_fast8_t i; - uint16_t tempVariable = 0; - - // Set module to decrypt mode - AES256_CMSIS(moduleInstance)->CTL0 |= (AES256_CTL0_OP_3); - - // Write data to decrypt to module - for (i = 0; i < 16; i = i + 2) - { - tempVariable = (uint16_t) (data[i + 1] << 8); - tempVariable = tempVariable | ((uint16_t) (data[i])); - AES256_CMSIS(moduleInstance)->DIN = tempVariable; - } - - // Key that is already written shall be used - // Now decryption starts - BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_KEYWR_OFS) = 1; -} - -bool AES256_startSetDecipherKey(uint32_t moduleInstance, - const uint8_t * cipherKey, uint_fast16_t keyLength) -{ - uint_fast8_t i; - uint16_t tempVariable = 0; - - AES256_CMSIS(moduleInstance)->CTL0 = - (AES256_CMSIS(moduleInstance)->CTL0 & ~AES256_CTL0_OP_MASK) | AES256_CTL0_OP1; - - switch (keyLength) - { - case AES256_KEYLENGTH_128BIT: - AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__128BIT; - break; - - case AES256_KEYLENGTH_192BIT: - AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__192BIT; - break; - - case AES256_KEYLENGTH_256BIT: - AES256_CMSIS(moduleInstance)->CTL0 |= AES256_CTL0_KL__256BIT; - break; - - default: - return false; - } - - keyLength = keyLength / 8; - - // Write cipher key to key register - for (i = 0; i < keyLength; i = i + 2) - { - tempVariable = (uint16_t) (cipherKey[i]); - tempVariable = tempVariable | ((uint16_t) (cipherKey[i + 1]) << 8); - AES256_CMSIS(moduleInstance)->KEY = tempVariable; - } - - return true; -} - -bool AES256_getDataOut(uint32_t moduleInstance, uint8_t *outputData) -{ - uint8_t i; - uint16_t tempData = 0; - - // If module is busy, exit and return failure - if (BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS)) - return false; - - // Write encrypted data back to variable - for (i = 0; i < 16; i = i + 2) - { - tempData = AES256_CMSIS(moduleInstance)->DOUT; - *(outputData + i) = (uint8_t) tempData; - *(outputData + i + 1) = (uint8_t) (tempData >> 8); - } - - return true; -} - -bool AES256_isBusy(uint32_t moduleInstance) -{ - return BITBAND_PERI(AES256_CMSIS(moduleInstance)->STAT, AES256_STAT_BUSY_OFS); -} - -void AES256_clearErrorFlag(uint32_t moduleInstance) -{ - BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_ERRFG_OFS) = 0; -} - -uint32_t AES256_getErrorFlagStatus(uint32_t moduleInstance) -{ - return BITBAND_PERI(AES256_CMSIS(moduleInstance)->CTL0, AES256_CTL0_ERRFG_OFS); -} - -void AES256_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void)) -{ - Interrupt_registerInterrupt(INT_AES256, intHandler); - Interrupt_enableInterrupt(INT_AES256); -} - -void AES256_unregisterInterrupt(uint32_t moduleInstance) -{ - Interrupt_disableInterrupt(INT_AES256); - Interrupt_unregisterInterrupt(INT_AES256); -} - -uint32_t AES256_getInterruptStatus(uint32_t moduleInstance) -{ - return AES256_getInterruptFlagStatus(moduleInstance); -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/aes256.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/aes256.h deleted file mode 100644 index 5925b8c923f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/aes256.h +++ /dev/null @@ -1,446 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef AES256_H_ -#define AES256_H_ - -//***************************************************************************** -// -//! \addtogroup aes256_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include - -/* Module Defines and macro for easy access */ -#define AES256_CMSIS(x) ((AES256_Type *) x) - -//***************************************************************************** -// -// The following are deprecated values. Please refer to documentation for the -// correct values to use. -// -//***************************************************************************** -#define Key_128BIT 128 -#define Key_192BIT 192 -#define Key_256BIT 256 - -//***************************************************************************** -// -// The following are values that can be passed to the keyLength parameter for -// functions: AES256_setCipherKey(), AES256_setDecipherKey(), and -// AES256_startSetDecipherKey(). -// -//***************************************************************************** -#define AES256_KEYLENGTH_128BIT 128 -#define AES256_KEYLENGTH_192BIT 192 -#define AES256_KEYLENGTH_256BIT 256 - -//***************************************************************************** -// -// The following are values that can be passed toThe following are values that -// can be returned by the AES256_getErrorFlagStatus() function. -// -//***************************************************************************** -#define AES256_ERROR_OCCURRED AES256_CTL0_ERRFG -#define AES256_NO_ERROR 0x00 - -//***************************************************************************** -// -// The following are values that can be passed toThe following are values that -// can be returned by the AES256_isBusy() function. -// -//***************************************************************************** -#define AES256_BUSY AES256_STAT_BUSY -#define AES256_NOT_BUSY 0x00 - -//***************************************************************************** -// -// The following are values that can be passed toThe following are values that -// can be returned by the AES256_getInterruptFlagStatus() function. -// -//***************************************************************************** -#define AES256_READY_INTERRUPT 0x01 -#define AES256_NOTREADY_INTERRUPT 0x00 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief Loads a 128, 192 or 256 bit cipher key to AES256 module. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes -//! that contains a 128 bit cipher key. -//! \param keyLength is the length of the key. -//! Valid values are: -//! - \b AES256_KEYLENGTH_128BIT -//! - \b AES256_KEYLENGTH_192BIT -//! - \b AES256_KEYLENGTH_256BIT -//! -//! \return true if set correctly, false otherwise -// -//***************************************************************************** -extern bool AES256_setCipherKey(uint32_t moduleInstance, - const uint8_t *cipherKey, uint_fast16_t keyLength); - -//***************************************************************************** -// -//! \brief Encrypts a block of data using the AES256 module. -//! -//! The cipher key that is used for encryption should be loaded in advance by -//! using function AES256_setCipherKey() -//! -//! \param moduleInstance is the base address of the AES256 module. -//! \param data is a pointer to an uint8_t array with a length of 16 bytes that -//! contains data to be encrypted. -//! \param encryptedData is a pointer to an uint8_t array with a length of 16 -//! bytes in that the encrypted data will be written. -//! -//! \return None -// -//***************************************************************************** -extern void AES256_encryptData(uint32_t moduleInstance, const uint8_t *data, - uint8_t *encryptedData); - -//***************************************************************************** -// -//! \brief Decrypts a block of data using the AES256 module. -//! -//! This function requires a pregenerated decryption key. A key can be loaded -//! and pregenerated by using function AES256_setDecipherKey() or -//! AES256_startSetDecipherKey(). The decryption takes 167 MCLK. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! \param data is a pointer to an uint8_t array with a length of 16 bytes that -//! contains encrypted data to be decrypted. -//! \param decryptedData is a pointer to an uint8_t array with a length of 16 -//! bytes in that the decrypted data will be written. -//! -//! \return None -// -//***************************************************************************** -extern void AES256_decryptData(uint32_t moduleInstance, const uint8_t *data, - uint8_t *decryptedData); - -//***************************************************************************** -// -//! \brief Sets the decipher key. -//! -//! The API AES256_startSetDecipherKey or AES256_setDecipherKey must be invoked -//! before invoking AES256_startDecryptData. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes -//! that contains a 128 bit cipher key. -//! \param keyLength is the length of the key. -//! Valid values are: -//! - \b AES256_KEYLENGTH_128BIT -//! - \b AES256_KEYLENGTH_192BIT -//! - \b AES256_KEYLENGTH_256BIT -//! -//! \return true if set, false otherwise -// -//***************************************************************************** -extern bool AES256_setDecipherKey(uint32_t moduleInstance, - const uint8_t *cipherKey, uint_fast16_t keyLength); - -//***************************************************************************** -// -//! \brief Clears the AES256 ready interrupt flag. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! -//! Modified bits are \b AESRDYIFG of \b AESACTL0 register. -//! -//! \return None -// -//***************************************************************************** -extern void AES256_clearInterruptFlag(uint32_t moduleInstance); - -//***************************************************************************** -// -//! \brief Gets the AES256 ready interrupt flag status. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! -//! \return One of the following: -//! - \b AES256_READY_INTERRUPT -//! - \b AES256_NOTREADY_INTERRUPT -//! \n indicating the status of the AES256 ready status -// -//***************************************************************************** -extern uint32_t AES256_getInterruptFlagStatus(uint32_t moduleInstance); - -//***************************************************************************** -// -//! \brief Enables AES256 ready interrupt. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! -//! Modified bits are \b AESRDYIE of \b AESACTL0 register. -//! -//! \return None -// -//***************************************************************************** -extern void AES256_enableInterrupt(uint32_t moduleInstance); - -//***************************************************************************** -// -//! \brief Disables AES256 ready interrupt. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! -//! Modified bits are \b AESRDYIE of \b AESACTL0 register. -//! -//! \return None -// -//***************************************************************************** -extern void AES256_disableInterrupt(uint32_t moduleInstance); - -//***************************************************************************** -// -//! \brief Resets AES256 Module immediately. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! -//! Modified bits are \b AESSWRST of \b AESACTL0 register. -//! -//! \return None -// -//***************************************************************************** -extern void AES256_reset(uint32_t moduleInstance); - -//***************************************************************************** -// -//! \brief Starts an encryption process on the AES256 module. -//! -//! The cipher key that is used for decryption should be loaded in advance by -//! using function AES256_setCipherKey(). This is a non-blocking equivalent pf -//! AES256_encryptData(). It is recommended to use the interrupt functionality -//! to check for procedure completion then use the AES256_getDataOut() API to -//! retrieve the encrypted data. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! \param data is a pointer to an uint8_t array with a length of 16 bytes that -//! contains data to be encrypted. -//! -//! \return None -// -//***************************************************************************** -extern void AES256_startEncryptData(uint32_t moduleInstance, - const uint8_t *data); - -//***************************************************************************** -// -//! \brief Decypts a block of data using the AES256 module. -//! -//! This is the non-blocking equivalant of AES256_decryptData(). This function -//! requires a pregenerated decryption key. A key can be loaded and -//! pregenerated by using function AES256_setDecipherKey() or -//! AES256_startSetDecipherKey(). The decryption takes 167 MCLK. It is -//! recommended to use interrupt to check for procedure completion then use the -//! AES256_getDataOut() API to retrieve the decrypted data. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! \param data is a pointer to an uint8_t array with a length of 16 bytes that -//! contains encrypted data to be decrypted. -//! -//! \return None -// -//***************************************************************************** -extern void AES256_startDecryptData(uint32_t moduleInstance, - const uint8_t *data); - -//***************************************************************************** -// -//! \brief Sets the decipher key -//! -//! The API AES256_startSetDecipherKey() or AES256_setDecipherKey() must be -//! invoked before invoking AES256_startDecryptData. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! \param cipherKey is a pointer to an uint8_t array with a length of 16 bytes -//! that contains a 128 bit cipher key. -//! \param keyLength is the length of the key. -//! Valid values are: -//! - \b AES256_KEYLENGTH_128BIT -//! - \b AES256_KEYLENGTH_192BIT -//! - \b AES256_KEYLENGTH_256BIT -//! -//! \return true if set correctly, false otherwise -// -//***************************************************************************** -extern bool AES256_startSetDecipherKey(uint32_t moduleInstance, - const uint8_t *cipherKey, uint_fast16_t keyLength); - -//***************************************************************************** -// -//! \brief Reads back the output data from AES256 module. -//! -//! This function is meant to use after an encryption or decryption process -//! that was started and finished by initiating an interrupt by use of -//! AES256_startEncryptData or AES256_startDecryptData functions. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! \param outputData is a pointer to an uint8_t array with a length of 16 -//! bytes in that the data will be written. -//! -//! \return true if data is valid, otherwise false -// -//***************************************************************************** -extern bool AES256_getDataOut(uint32_t moduleInstance, - uint8_t *outputData); - -//***************************************************************************** -// -//! \brief Gets the AES256 module busy status. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! -//! \return true if busy, false otherwise -// -//***************************************************************************** -extern bool AES256_isBusy(uint32_t moduleInstance); - -//***************************************************************************** -// -//! \brief Clears the AES256 error flag. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! -//! Modified bits are \b AESERRFG of \b AESACTL0 register. -//! -//! \return None -// -//***************************************************************************** -extern void AES256_clearErrorFlag(uint32_t moduleInstance); - -//***************************************************************************** -// -//! \brief Gets the AES256 error flag status. -//! -//! \param moduleInstance is the base address of the AES256 module. -//! -//! \return One of the following: -//! - \b AES256_ERROR_OCCURRED -//! - \b AES256_NO_ERROR -//! \n indicating the error flag status -// -//***************************************************************************** -extern uint32_t AES256_getErrorFlagStatus(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Registers an interrupt handler for the AES interrupt. -//! -//! \param moduleInstance Instance of the AES256 module -//! -//! \param intHandler is a pointer to the function to be called when the -//! AES interrupt occurs. -//! -//! This function registers the handler to be called when a AES -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific AES interrupts must be enabled -//! via AES256_enableInterrupt(). It is the interrupt handler's responsibility -//! to clear the interrupt source via AES256_clearInterrupt(). -//! -//! \return None. -// -//***************************************************************************** -extern void AES256_registerInterrupt(uint32_t moduleInstance, - void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the AES interrupt -//! -//! \param moduleInstance Instance of the AES256 module -//! -//! This function unregisters the handler to be called when AES -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void AES256_unregisterInterrupt(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Returns the current interrupt flag for the peripheral. -//! -//! \param moduleInstance Instance of the AES256 module -//! -//! \return The currently triggered interrupt flag for the module. -// -//***************************************************************************** -extern uint32_t AES256_getInterruptStatus(uint32_t moduleInstance); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* AES256_H_ */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/comp_e.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/comp_e.c deleted file mode 100644 index c16220a1fa0..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/comp_e.c +++ /dev/null @@ -1,312 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include - -static uint16_t __getRegisterSettingForInput(uint32_t input) -{ - switch (input) - { - case COMP_E_INPUT0: - return COMP_E_CTL0_IPSEL_0; - case COMP_E_INPUT1: - return COMP_E_CTL0_IPSEL_1; - case COMP_E_INPUT2: - return COMP_E_CTL0_IPSEL_2; - case COMP_E_INPUT3: - return COMP_E_CTL0_IPSEL_3; - case COMP_E_INPUT4: - return COMP_E_CTL0_IPSEL_4; - case COMP_E_INPUT5: - return COMP_E_CTL0_IPSEL_5; - case COMP_E_INPUT6: - return COMP_E_CTL0_IPSEL_6; - case COMP_E_INPUT7: - return COMP_E_CTL0_IPSEL_7; - case COMP_E_INPUT8: - return COMP_E_CTL0_IPSEL_8; - case COMP_E_INPUT9: - return COMP_E_CTL0_IPSEL_9; - case COMP_E_INPUT10: - return COMP_E_CTL0_IPSEL_10; - case COMP_E_INPUT11: - return COMP_E_CTL0_IPSEL_11; - case COMP_E_INPUT12: - return COMP_E_CTL0_IPSEL_12; - case COMP_E_INPUT13: - return COMP_E_CTL0_IPSEL_13; - case COMP_E_INPUT14: - return COMP_E_CTL0_IPSEL_14; - case COMP_E_INPUT15: - return COMP_E_CTL0_IPSEL_15; - case COMP_E_VREF: - return COMP_E_VREF; - default: - ASSERT(false); - return 0x11; - } - -} - -bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config) -{ - uint_fast8_t positiveTerminalInput = __getRegisterSettingForInput( - config->positiveTerminalInput); - uint_fast8_t negativeTerminalInput = __getRegisterSettingForInput( - config->negativeTerminalInput); - bool retVal = true; - - ASSERT(positiveTerminalInput < 0x10); ASSERT(negativeTerminalInput < 0x10); - ASSERT(positiveTerminalInput != negativeTerminalInput); - ASSERT( - config->outputFilterEnableAndDelayLevel - <= COMP_E_FILTEROUTPUT_DLYLVL4); - - /* Reset COMPE Control 1 & Interrupt Registers for initialization */ - COMP_E_CMSIS(comparator)->CTL0 = 0; - COMP_E_CMSIS(comparator)->INT = 0; - - // Set the Positive Terminal - if (COMP_E_VREF != positiveTerminalInput) - { - // Enable Positive Terminal Input Mux and Set to the appropriate input - COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IPEN - + positiveTerminalInput; - - // Disable the input buffer - COMP_E_CMSIS(comparator)->CTL3 |= (1 << positiveTerminalInput); - } else - { - // Reset and Set COMPE Control 2 Register - BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2,COMP_E_CTL2_RSEL_OFS) = 0; - } - - // Set the Negative Terminal - if (COMP_E_VREF != negativeTerminalInput) - { - // Enable Negative Terminal Input Mux and Set to the appropriate input - COMP_E_CMSIS(comparator)->CTL0 |= COMP_E_CTL0_IMEN - + (negativeTerminalInput << 8); - - // Disable the input buffer - COMP_E_CMSIS(comparator)->CTL3 |= (1 << negativeTerminalInput); - } else - { - // Reset and Set COMPE Control 2 Register - BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_RSEL_OFS) = 1; - } - - // Reset and Set COMPE Control 1 Register - COMP_E_CMSIS(comparator)->CTL1 = config->powerMode - + config->outputFilterEnableAndDelayLevel - + config->invertedOutputPolarity; - - return retVal; -} - -void COMP_E_setReferenceVoltage(uint32_t comparator, - uint_fast16_t supplyVoltageReferenceBase, - uint_fast16_t lowerLimitSupplyVoltageFractionOf32, - uint_fast16_t upperLimitSupplyVoltageFractionOf32) -{ - ASSERT(supplyVoltageReferenceBase <= COMP_E_VREFBASE2_5V); - ASSERT(upperLimitSupplyVoltageFractionOf32 <= 32); - ASSERT(lowerLimitSupplyVoltageFractionOf32 <= 32); - ASSERT(upperLimitSupplyVoltageFractionOf32 - >= lowerLimitSupplyVoltageFractionOf32); - - BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_MRVS_OFS) = 0; - COMP_E_CMSIS(comparator)->CTL2 &= COMP_E_CTL2_RSEL; - - // Set Voltage Source(Vcc | Vref, resistor ladder or not) - if (COMP_E_REFERENCE_AMPLIFIER_DISABLED == supplyVoltageReferenceBase) - { - COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_1; - } else if (lowerLimitSupplyVoltageFractionOf32 == 32) - { - COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_3; - } else - { - COMP_E_CMSIS(comparator)->CTL2 |= COMP_E_CTL2_RS_2; - } - - // Set COMPE Control 2 Register - COMP_E_CMSIS(comparator)->CTL2 |= supplyVoltageReferenceBase - + ((upperLimitSupplyVoltageFractionOf32 - 1) << 8) - + (lowerLimitSupplyVoltageFractionOf32 - 1); -} - -void COMP_E_setReferenceAccuracy(uint32_t comparator, - uint_fast16_t referenceAccuracy) -{ - ASSERT( - (referenceAccuracy == COMP_E_ACCURACY_STATIC) - || (referenceAccuracy == COMP_E_ACCURACY_CLOCKED)); - - if (referenceAccuracy) - BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_REFACC_OFS) = 1; - else - BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL2, COMP_E_CTL2_REFACC_OFS) = 0; - -} - -void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode) -{ - COMP_E_CMSIS(comparator)->CTL1 = (COMP_E_CMSIS(comparator)->CTL1 - & ~(COMP_E_CTL1_PWRMD_MASK)) | powerMode; -} - -void COMP_E_enableModule(uint32_t comparator) -{ - BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_ON_OFS) = 1; -} - -void COMP_E_disableModule(uint32_t comparator) -{ - BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_ON_OFS) = 0; -} - -void COMP_E_shortInputs(uint32_t comparator) -{ - BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_SHORT_OFS) = 1; -} - -void COMP_E_unshortInputs(uint32_t comparator) -{ - BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_SHORT_OFS) = 0; -} - -void COMP_E_disableInputBuffer(uint32_t comparator, uint_fast16_t inputPort) -{ - ASSERT(inputPort <= COMP_E_INPUT15); - - COMP_E_CMSIS(comparator)->CTL3 |= (inputPort); -} - -void COMP_E_enableInputBuffer(uint32_t comparator, uint_fast16_t inputPort) -{ - ASSERT(inputPort <= COMP_E_INPUT15); - - COMP_E_CMSIS(comparator)->CTL3 &= ~(inputPort); -} - -void COMP_E_swapIO(uint32_t comparator) -{ - COMP_E_CMSIS(comparator)->CTL1 ^= COMP_E_CTL1_EX; // Toggle CEEX bit -} - -uint8_t COMP_E_outputValue(uint32_t comparator) -{ - return COMP_E_CMSIS(comparator)->CTL1 & COMP_E_CTL1_OUT; -} - -void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask) -{ - // Set the Interrupt enable bit - COMP_E_CMSIS(comparator)->INT |= mask; -} - -uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator) -{ - return COMP_E_getInterruptStatus(comparator) & - COMP_E_CMSIS(comparator)->INT; -} - -void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask) -{ - COMP_E_CMSIS(comparator)->INT &= ~(mask); -} - -void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask) -{ - COMP_E_CMSIS(comparator)->INT &= ~(mask); -} - -uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator) -{ - return (COMP_E_CMSIS(comparator)->INT & (COMP_E_OUTPUT_INTERRUPT_FLAG | - COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY | - COMP_E_INTERRUPT_FLAG_READY)); -} - -void COMP_E_setInterruptEdgeDirection(uint32_t comparator, - uint_fast8_t edgeDirection) -{ - ASSERT(edgeDirection <= COMP_E_RISINGEDGE); - - // Set the edge direction that will trigger an interrupt - if (COMP_E_RISINGEDGE == edgeDirection) - BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 1; - else if (COMP_E_FALLINGEDGE == edgeDirection) - BITBAND_PERI(COMP_E_CMSIS(comparator)->CTL1, COMP_E_CTL1_IES_OFS) = 0; -} - -void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator) -{ - COMP_E_CMSIS(comparator)->CTL1 ^= COMP_E_CTL1_IES; -} - -void COMP_E_registerInterrupt(uint32_t comparator, void (*intHandler)(void)) -{ - switch (comparator) - { - case COMP_E0_BASE: - Interrupt_registerInterrupt(INT_COMP_E0, intHandler); - Interrupt_enableInterrupt(INT_COMP_E0); - break; - case COMP_E1_BASE: - Interrupt_registerInterrupt(INT_COMP_E1, intHandler); - Interrupt_enableInterrupt(INT_COMP_E1); - break; - default: - ASSERT(false); - } -} - -void COMP_E_unregisterInterrupt(uint32_t comparator) -{ - switch (comparator) - { - case COMP_E0_BASE: - Interrupt_disableInterrupt(INT_COMP_E0); - Interrupt_unregisterInterrupt(INT_COMP_E0); - break; - case COMP_E1_BASE: - Interrupt_disableInterrupt(INT_COMP_E1); - Interrupt_unregisterInterrupt(INT_COMP_E1); - break; - default: - ASSERT(false); - } -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/comp_e.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/comp_e.h deleted file mode 100644 index 841e5d823dd..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/comp_e.h +++ /dev/null @@ -1,728 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef COMP_E_H_ -#define COMP_E_H_ - -//***************************************************************************** -// -//! \addtogroup comp_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include - -/* Module defines for Comp */ -#define COMP_E_CMSIS(x) ((COMP_E_Type *) x) - -#define COMP_E_FILTEROUTPUT_OFF 0x00 -#define COMP_E_FILTEROUTPUT_DLYLVL1 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_0) -#define COMP_E_FILTEROUTPUT_DLYLVL2 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_1) -#define COMP_E_FILTEROUTPUT_DLYLVL3 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_2) -#define COMP_E_FILTEROUTPUT_DLYLVL4 (COMP_E_CTL1_F + COMP_E_CTL1_FDLY_3) - -#define COMP_E_INPUT0 (0x01) -#define COMP_E_INPUT1 (0x02) -#define COMP_E_INPUT2 (0x04) -#define COMP_E_INPUT3 (0x08) -#define COMP_E_INPUT4 (0x10) -#define COMP_E_INPUT5 (0x20) -#define COMP_E_INPUT6 (0x40) -#define COMP_E_INPUT7 (0x80) -#define COMP_E_INPUT8 (0x100) -#define COMP_E_INPUT9 (0x200) -#define COMP_E_INPUT10 (0x400) -#define COMP_E_INPUT11 (0x800) -#define COMP_E_INPUT12 (0x1000) -#define COMP_E_INPUT13 (0x2000) -#define COMP_E_INPUT14 (0x4000) -#define COMP_E_INPUT15 (0x8000) -#define COMP_E_VREF (0x9F) - -#define COMP_E_NORMALOUTPUTPOLARITY (!(COMP_E_CTL1_OUTPOL)) -#define COMP_E_INVERTEDOUTPUTPOLARITY (COMP_E_CTL1_OUTPOL) - -#define COMP_E_REFERENCE_AMPLIFIER_DISABLED (COMP_E_CTL2_CEREFL_0) -#define COMP_E_VREFBASE1_2V (COMP_E_CTL2_CEREFL_1) -#define COMP_E_VREFBASE2_0V (COMP_E_CTL2_CEREFL_2) -#define COMP_E_VREFBASE2_5V (COMP_E_CTL2_CEREFL_3) - -#define COMP_E_ACCURACY_STATIC (!COMP_E_CTL2_REFACC) -#define COMP_E_ACCURACY_CLOCKED (COMP_E_CTL2_REFACC) - -#define COMP_E_HIGH_SPEED_MODE (COMP_E_CTL1_PWRMD_0) -#define COMP_E_NORMAL_MODE (COMP_E_CTL1_PWRMD_1) -#define COMP_E_ULTRA_LOW_POWER_MODE (COMP_E_CTL1_PWRMD_2) - -#define COMP_E_OUTPUT_INTERRUPT (COMP_E_INT_IE) -#define COMP_E_INVERTED_POLARITY_INTERRUPT (COMP_E_INT_IIE) -#define COMP_E_READY_INTERRUPT (COMP_E_INT_RDYIE) - -#define COMP_E_OUTPUT_INTERRUPT_FLAG (COMP_E_INT_IFG) -#define COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY (COMP_E_INT_IIFG) -#define COMP_E_INTERRUPT_FLAG_READY (COMP_E_INT_RDYIFG) - -#define COMP_E_FALLINGEDGE (!(COMP_E_CTL1_IES)) -#define COMP_E_RISINGEDGE (COMP_E_CTL1_IES) - -#define COMP_E_LOW (0x0) -#define COMP_E_HIGH (COMP_E_CTL1_OUT) - -//***************************************************************************** -// -//! ypedef COMP_E_Config -//! \brief Type definition for \link _COMP_E_Config \endlink structure -//! -//! \struct _COMP_E_Config -//! \brief Configuration structure for Comparator module. See -//! \link COMP_E_initModule \endlink for parameter documentation. -// -//***************************************************************************** -typedef struct _COMP_E_Config -{ - uint_fast16_t positiveTerminalInput; - uint_fast16_t negativeTerminalInput; - uint_fast8_t outputFilterEnableAndDelayLevel; - uint_fast8_t invertedOutputPolarity; - uint_fast16_t powerMode; -} COMP_E_Config; - -//***************************************************************************** -// -//! Initializes the Comparator Module. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! \param config Configuration structure for the Comparator module -//! -//!
-//! Configuration options for \link COMP_E_Config \endlink structure. -//!
-//! -//! \param positiveTerminalInput selects the input to the positive terminal. -//! Valid values are -//! - \b COMP_E_INPUT0 [Default] -//! - \b COMP_E_INPUT1 -//! - \b COMP_E_INPUT2 -//! - \b COMP_E_INPUT3 -//! - \b COMP_E_INPUT4 -//! - \b COMP_E_INPUT5 -//! - \b COMP_E_INPUT6 -//! - \b COMP_E_INPUT7 -//! - \b COMP_E_INPUT8 -//! - \b COMP_E_INPUT9 -//! - \b COMP_E_INPUT10 -//! - \b COMP_E_INPUT11 -//! - \b COMP_E_INPUT12 -//! - \b COMP_E_INPUT13 -//! - \b COMP_E_INPUT14 -//! - \b COMP_E_INPUT15 -//! - \b COMP_E_VREF -//! \n Modified bits are \b CEIPSEL and \b CEIPEN of \b CECTL0 register, -//! \b CERSEL of \b CECTL2 register, and CEPDx of \b CECTL3 register. -//! \param negativeTerminalInput selects the input to the negative terminal. -//! \n Valid values are: -//! - \b COMP_E_INPUT0 [Default] -//! - \b COMP_E_INPUT1 -//! - \b COMP_E_INPUT2 -//! - \b COMP_E_INPUT3 -//! - \b COMP_E_INPUT4 -//! - \b COMP_E_INPUT5 -//! - \b COMP_E_INPUT6 -//! - \b COMP_E_INPUT7 -//! - \b COMP_E_INPUT8 -//! - \b COMP_E_INPUT9 -//! - \b COMP_E_INPUT10 -//! - \b COMP_E_INPUT11 -//! - \b COMP_E_INPUT12 -//! - \b COMP_E_INPUT13 -//! - \b COMP_E_INPUT14 -//! - \b COMP_E_INPUT15 -//! - \b COMP_E_VREF -//! \n Modified bits are \b CEIMSEL and \b CEIMEN of \b CECTL0 register, -//! \b CERSEL of \b CECTL2 register, and CEPDx of \b CECTL3 register. -//! \param outputFilterEnableAndDelayLevel controls the output filter delay -//! state, which is either off or enabled with a specified delay level. -//! \n Valid values are -//! - \b COMP_E_FILTEROUTPUT_OFF [Default] -//! - \b COMP_E_FILTEROUTPUT_DLYLVL1 -//! - \b COMP_E_FILTEROUTPUT_DLYLVL2 -//! - \b COMP_E_FILTEROUTPUT_DLYLVL3 -//! - \b COMP_E_FILTEROUTPUT_DLYLVL4 -//! \n This parameter is device specific and delay levels should be found -//! in the device's datasheet. -//! \n Modified bits are \b CEF and \b CEFDLY of \b CECTL1 register. -//! \param invertedOutputPolarity controls if the output will be inverted or -//! not. Valid values are -//! - \b COMP_E_NORMALOUTPUTPOLARITY - indicates the output should be -//! normal. [Default] -//! - \b COMP_E_INVERTEDOUTPUTPOLARITY - the output should be inverted. -//! \n Modified bits are \b CEOUTPOL of \b CECTL1 register. -//! \param powerMode controls the power mode of the module -//! - \b COMP_E_HIGH_SPEED_MODE [default] -//! - \b COMP_E_NORMAL_MODE -//! - \b COMP_E_ULTRA_LOW_POWER_MODE -//! Upon successful initialization of the Comparator module, this function will -//! have reset all necessary register bits and set the given options in the -//! registers. To actually use the comparator module, the COMP_E_enableModule() -//! function must be explicitly called before use. -//! If a Reference Voltage is set to a terminal, the Voltage should be set -//! using the COMP_E_setReferenceVoltage() function. -//! -//! \return true or false of the initialization process. -// -//***************************************************************************** -extern bool COMP_E_initModule(uint32_t comparator, const COMP_E_Config *config); - -//***************************************************************************** -// -//! Generates a Reference Voltage to the terminal selected during -//! initialization. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! \param supplyVoltageReferenceBase decides the source and max amount of -//! Voltage that can be used as a reference. -//! Valid values are -//! - \b COMP_E_REFERENCE_AMPLIFIER_DISABLED -//! - \b COMP_E_VREFBASE1_2V -//! - \b COMP_E_VREFBASE2_0V -//! - \b COMP_E_VREFBASE2_5V -//! \param upperLimitSupplyVoltageFractionOf32 is the numerator of the -//! equation to generate the reference voltage for the upper limit -//! reference voltage. Valid values are between 1 and 32. -//! \param lowerLimitSupplyVoltageFractionOf32 is the numerator of the -//! equation to generate the reference voltage for the lower limit -//! reference voltage. Valid values are between 1 and 32. -//!
Modified bits are \b CEREF0 of \b CECTL2 register. -//! -//! Use this function to generate a voltage to serve as a reference to the -//! terminal selected at initialization. The voltage is determined by the -//! equation: Vbase * (Numerator / 32). If the upper and lower limit voltage -//! numerators are equal, then a static reference is defined, whereas they are -//! different then a hysteresis effect is generated. -//! -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_setReferenceVoltage(uint32_t comparator, - uint_fast16_t supplyVoltageReferenceBase, - uint_fast16_t lowerLimitSupplyVoltageFractionOf32, - uint_fast16_t upperLimitSupplyVoltageFractionOf32); - -//***************************************************************************** -// -//! Sets the reference accuracy -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! \param referenceAccuracy is the reference accuracy setting of the -//! comparator. Clocked is for low power/low accuracy. -//! Valid values are -//! - \b COMP_E_ACCURACY_STATIC -//! - \b COMP_E_ACCURACY_CLOCKED -//!
Modified bits are \b CEREFACC of \b CECTL2 register. -//! -//! The reference accuracy is set to the desired setting. Clocked is better for -//! low power operations but has a lower accuracy. -//! -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_setReferenceAccuracy(uint32_t comparator, - uint_fast16_t referenceAccuracy); - -//***************************************************************************** -// -//! Sets the power mode -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! \param powerMode decides the power mode -//! Valid values are -//! - \b COMP_E_HIGH_SPEED_MODE -//! - \b COMP_E_NORMAL_MODE -//! - \b COMP_E_ULTRA_LOW_POWER_MODE -//!
Modified bits are \b CEPWRMD of \b CECTL1 register. -//! -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_setPowerMode(uint32_t comparator, uint_fast16_t powerMode); - -//***************************************************************************** -// -//! Turns on the Comparator module. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! -//! This function sets the bit that enables the operation of the -//! Comparator module. -//! -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_enableModule(uint32_t comparator); - -//***************************************************************************** -// -//! Turns off the Comparator module. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! -//! This function clears the CEON bit disabling the operation of the Comparator -//! module, saving from excess power consumption. -//! -//! Modified bits are \b CEON of \b CECTL1 register. -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_disableModule(uint32_t comparator); - -//***************************************************************************** -// -//! Shorts the two input pins chosen during initialization. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! -//! This function sets the bit that shorts the devices attached to the input -//! pins chosen from the initialization of the comparator. -//! -//! Modified bits are \b CESHORT of \b CECTL1 register. -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_shortInputs(uint32_t comparator); - -//***************************************************************************** -// -//! Disables the short of the two input pins chosen during initialization. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! -//! This function clears the bit that shorts the devices attached to the input -//! pins chosen from the initialization of the comparator. -//! -//! Modified bits are \b CESHORT of \b CECTL1 register. -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_unshortInputs(uint32_t comparator); - -//***************************************************************************** -// -//! Disables the input buffer of the selected input port to effectively allow -//! for analog signals. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! \param inputPort is the port in which the input buffer will be disabled. -//! Valid values are a logical OR of the following: -//! - \b COMP_E_INPUT0 [Default] -//! - \b COMP_E_INPUT1 -//! - \b COMP_E_INPUT2 -//! - \b COMP_E_INPUT3 -//! - \b COMP_E_INPUT4 -//! - \b COMP_E_INPUT5 -//! - \b COMP_E_INPUT6 -//! - \b COMP_E_INPUT7 -//! - \b COMP_E_INPUT8 -//! - \b COMP_E_INPUT9 -//! - \b COMP_E_INPUT10 -//! - \b COMP_E_INPUT11 -//! - \b COMP_E_INPUT12 -//! - \b COMP_E_INPUT13 -//! - \b COMP_E_INPUT14 -//! - \b COMP_E_INPUT15 -//!
Modified bits are \b CEPDx of \b CECTL3 register. -//! -//! This function sets the bit to disable the buffer for the specified input -//! port to allow for analog signals from any of the comparator input pins. This -//! bit is automatically set when the input is initialized to be used with the -//! comparator module. This function should be used whenever an analog input is -//! connected to one of these pins to prevent parasitic voltage from causing -//! unexpected results. -//! -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_disableInputBuffer(uint32_t comparator, - uint_fast16_t inputPort); - -//***************************************************************************** -// -//! Enables the input buffer of the selected input port to allow for digital -//! signals. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! \param inputPort is the port in which the input buffer will be enabled. -//! Valid values are a logical OR of the following: -//! - \b COMP_E_INPUT0 [Default] -//! - \b COMP_E_INPUT1 -//! - \b COMP_E_INPUT2 -//! - \b COMP_E_INPUT3 -//! - \b COMP_E_INPUT4 -//! - \b COMP_E_INPUT5 -//! - \b COMP_E_INPUT6 -//! - \b COMP_E_INPUT7 -//! - \b COMP_E_INPUT8 -//! - \b COMP_E_INPUT9 -//! - \b COMP_E_INPUT10 -//! - \b COMP_E_INPUT11 -//! - \b COMP_E_INPUT12 -//! - \b COMP_E_INPUT13 -//! - \b COMP_E_INPUT14 -//! - \b COMP_E_INPUT15 -//!
Modified bits are \b CEPDx of \b CECTL3 register. -//! -//! This function clears the bit to enable the buffer for the specified input -//! port to allow for digital signals from any of the comparator input pins. -//! This should not be reset if there is an analog signal connected to the -//! specified input pin to prevent from unexpected results. -//! -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_enableInputBuffer(uint32_t comparator, - uint_fast16_t inputPort); - -//***************************************************************************** -// -//! Toggles the bit that swaps which terminals the inputs go to, while also -//! inverting the output of the comparator. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \ bCOMP_E0 -//! - \ bCOMP_E1 -//! -//! This function toggles the bit that controls which input goes to which -//! terminal. After initialization, this bit is set to 0, after toggling it once -//! the inputs are routed to the opposite terminal and the output is inverted. -//! -//! Modified bits are \b CEEX of \b CECTL1 register. -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_swapIO(uint32_t comparator); - -//***************************************************************************** -// -//! Returns the output value of the Comparator module. -//! -//! \param comparator is the instance of the Comparator module. Valid parameters -//! vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! -//! Returns the output value of the Comparator module. -//! -//! \return COMP_E_HIGH or COMP_E_LOW as the output value of the Comparator -//! module. -// -//***************************************************************************** -extern uint8_t COMP_E_outputValue(uint32_t comparator); - -//***************************************************************************** -// -//! Enables selected Comparator interrupt sources. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! \param mask is the bit mask of the interrupt sources to be enabled. -//! Mask value is the logical OR of any of the following -//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt -//! - \b COMP_E_INVERTED_POLARITY_INTERRUPT - Output interrupt inverted -//! polarity -//! - \b COMP_E_READY_INTERRUPT - Ready interrupt -//! -//! Enables the indicated Comparator interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. The default trigger for the non-inverted -//! interrupt is a rising edge of the output, this can be changed with the -//! interruptSetEdgeDirection() function. -//! -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_enableInterrupt(uint32_t comparator, uint_fast16_t mask); - -//***************************************************************************** -// -//! Disables selected Comparator interrupt sources. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! \param mask is the bit mask of the interrupt sources to be disabled. -//! Mask value is the logical OR of any of the following -//! - \b COMP_E_OUTPUT_INTERRUPT - Output interrupt -//! - \b COMP_E_INVERTED_POLARITY_INTERRUPT - Output interrupt inverted -//! polarity -//! - \b COMP_E_READY_INTERRUPT - Ready interrupt -//! -//! Disables the indicated Comparator interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. -//! -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_disableInterrupt(uint32_t comparator, uint_fast16_t mask); - -//***************************************************************************** -// -//! Clears Comparator interrupt flags. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! \param mask is a bit mask of the interrupt sources to be cleared. -//! Mask value is the logical OR of any of the following -//! - \b COMP_E_INTERRUPT_FLAG - Output interrupt flag -//! - \b COMP_E_INTERRUPT_FLAG_INVERTED_POLARITY - Output interrupt flag -//! inverted polarity -//! - \b COMP_E_INTERRUPT_FLAG_READY - Ready interrupt flag -//! -//! The Comparator interrupt source is cleared, so that it no longer asserts. -//! The highest interrupt flag is automatically cleared when an interrupt vector -//! generator is used. -//! -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_clearInterruptFlag(uint32_t comparator, uint_fast16_t mask); - -//***************************************************************************** -// -//! Gets the current Comparator interrupt status. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! -//! This returns the interrupt status for the Comparator module based on which -//! flag is passed. -//! -//! \return The current interrupt flag status for the corresponding mask. -// -//***************************************************************************** -extern uint_fast16_t COMP_E_getInterruptStatus(uint32_t comparator); - -//***************************************************************************** -// -//! Enables selected Comparator interrupt sources masked with the enabled -//! interrupts. This function is useful to call in ISRs to get a list -//! of pending interrupts that are actually enabled and could have caused the -//! ISR. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! -//! Enables the indicated Comparator interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. The default trigger for the non-inverted -//! interrupt is a rising edge of the output, this can be changed with the -//! COMP_E_setInterruptEdgeDirection() function. -//! -//! \return NONE -// -//***************************************************************************** -extern uint_fast16_t COMP_E_getEnabledInterruptStatus(uint32_t comparator); - -//***************************************************************************** -// -//! Explicitly sets the edge direction that would trigger an interrupt. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! \param edgeDirection determines which direction the edge would have to go -//! to generate an interrupt based on the non-inverted interrupt flag. -//! Valid values are -//! - \b COMP_E_FALLINGEDGE - sets the bit to generate an interrupt when -//! the output of the comparator falls from HIGH to LOW if the -//! normal interrupt bit is set(and LOW to HIGH if the inverted -//! interrupt enable bit is set). [Default] -//! - \b COMP_E_RISINGEDGE - sets the bit to generate an interrupt when the -//! output of the comparator rises from LOW to HIGH if the normal -//! interrupt bit is set(and HIGH to LOW if the inverted interrupt -//! enable bit is set). -//!
Modified bits are \b CEIES of \b CECTL1 register. -//! -//! This function will set which direction the output will have to go, whether -//! rising or falling, to generate an interrupt based on a non-inverted -//! interrupt. -//! -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_setInterruptEdgeDirection(uint32_t comparator, - uint_fast8_t edgeDirection); - -//***************************************************************************** -// -//! Toggles the edge direction that would trigger an interrupt. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! -//! This function will toggle which direction the output will have to go, -//! whether rising or falling, to generate an interrupt based on a non-inverted -//! interrupt. If the direction was rising, it is now falling, if it was -//! falling, it is now rising. -//! -//! Modified bits are \b CEIES of \b CECTL1 register. -//! -//! \return NONE -// -//***************************************************************************** -extern void COMP_E_toggleInterruptEdgeDirection(uint32_t comparator); - -//***************************************************************************** -// -//! Registers an interrupt handler for the Comparator E interrupt. -//! -//! \param intHandler is a pointer to the function to be called when the -//! Comparator interrupt occurs. -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! -//! This function registers the handler to be called when a Comparator -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific Comparator interrupts must be enabled -//! via COMP_E_enableInterrupt(). It is the interrupt handler's responsibility to -//! clear the interrupt source via COMP_E_clearInterruptFlag(). -//! -//! \return None. -// -//***************************************************************************** -extern void COMP_E_registerInterrupt(uint32_t comparator, - void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the Comparator E interrupt -//! -//! \param comparator is the instance of the Comparator module. Valid -//! parameters vary from part to part, but can include: -//! - \b COMP_E0_BASE -//! - \b COMP_E1_BASE -//! -//! This function unregisters the handler to be called when Comparator E -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void COMP_E_unregisterInterrupt(uint32_t comparator); - -/* Backwards Compatibility Layer */ -#define COMP_E_enable(a) COMP_E_enableModule(a) -#define COMP_E_disable(a) COMP_E_disableModule(a) -#define COMP_E_IOSwap(a) COMP_E_swapIO(a) -#define COMP_E_interruptToggleEdgeDirection(a) COMP_E_toggleInterruptEdgeDirection(a) -#define COMP_E_clearInterrupt(a,b) COMP_E_clearInterruptFlag(a,b) - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - - -#endif /* COMP_E_H_ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/cpu.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/cpu.c deleted file mode 100644 index aae04fd1aeb..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/cpu.c +++ /dev/null @@ -1,425 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include - -//***************************************************************************** -// -// Wrapper function for the CPSID instruction. Returns the state of PRIMASK -// on entry. -// -//***************************************************************************** -#if defined(__GNUC__) -uint32_t __attribute__((naked)) CPU_cpsid(void) -{ - uint32_t ret; - - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " bx lr\n" - : "=r" (ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ret); -} -#endif -#if defined(__ICCARM__) -uint32_t CPU_cpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(__CC_ARM) -__asm uint32_t CPU_cpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - mrs r0, PRIMASK; - cpsid i; - bx lr -} -#endif -#if defined(__TI_ARM__) -uint32_t CPU_cpsid(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsid i\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function returning the state of PRIMASK (indicating whether -// interrupts are enabled or disabled). -// -//***************************************************************************** -#if defined(__GNUC__) -uint32_t __attribute__((naked)) CPU_primask(void) -{ - uint32_t ret; - - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " bx lr\n" - : "=r" (ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ret); -} -#endif -#if defined(__ICCARM__) -uint32_t CPU_primask(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(__CC_ARM) -__asm uint32_t CPU_primask(void) -{ - // - // Read PRIMASK and disable interrupts. - // - mrs r0, PRIMASK; - bx lr -} -#endif -#if defined(__TI_ARM__) -uint32_t CPU_primask(void) -{ - // - // Read PRIMASK and disable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function for the CPSIE instruction. Returns the state of PRIMASK -// on entry. -// -//***************************************************************************** -#if defined(__GNUC__) -uint32_t __attribute__((naked)) CPU_cpsie(void) -{ - uint32_t ret; - - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " bx lr\n" - : "=r" (ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ret); -} -#endif -#if defined(__ICCARM__) -uint32_t CPU_cpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(__CC_ARM) -__asm uint32_t CPU_cpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - mrs r0, PRIMASK; - cpsie i; - bx lr -} -#endif -#if defined(__TI_ARM__) -uint32_t CPU_cpsie(void) -{ - // - // Read PRIMASK and enable interrupts. - // - __asm(" mrs r0, PRIMASK\n" - " cpsie i\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif - -//***************************************************************************** -// -// Wrapper function for the CPUWFI instruction. -// -//***************************************************************************** -#if defined(__GNUC__) -void __attribute__((naked)) CPU_wfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" wfi\n" - " bx lr\n"); -} -#endif -#if defined(__ICCARM__) -void CPU_wfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" wfi\n"); -} -#endif -#if defined(__CC_ARM) -__asm void CPU_wfi(void) -{ - // - // Wait for the next interrupt. - // - wfi; - bx lr -} -#endif -#if defined(__TI_ARM__) -void CPU_wfi(void) -{ - // - // Wait for the next interrupt. - // - __asm(" wfi\n"); -} -#endif - -//***************************************************************************** -// -// Wrapper function for writing the BASEPRI register. -// -//***************************************************************************** -#if defined(__GNUC__) -void __attribute__((naked)) CPU_basepriSet(uint32_t newBasepri) -{ - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n" - " bx lr\n"); -} -#endif -#if defined(__ICCARM__) -void CPU_basepriSet(uint32_t newBasepri) -{ - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n"); -} -#endif -#if defined(__CC_ARM) -__asm void CPU_basepriSet(uint32_t newBasepri) -{ - // - // Set the BASEPRI register - // - msr BASEPRI, r0; - bx lr -} -#endif -#if defined(__TI_ARM__) -void CPU_basepriSet(uint32_t newBasepri) -{ - // - // Set the BASEPRI register - // - __asm(" msr BASEPRI, r0\n"); -} -#endif - -//***************************************************************************** -// -// Wrapper function for reading the BASEPRI register. -// -//***************************************************************************** -#if defined(__GNUC__) -uint32_t __attribute__((naked)) CPU_basepriGet(void) -{ - uint32_t ret; - - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n" - " bx lr\n" - : "=r" (ret)); - - // - // The return is handled in the inline assembly, but the compiler will - // still complain if there is not an explicit return here (despite the fact - // that this does not result in any code being produced because of the - // naked attribute). - // - return(ret); -} -#endif -#if defined(__ICCARM__) -uint32_t CPU_basepriGet(void) -{ - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n"); - - // - // "Warning[Pe940]: missing return statement at end of non-void function" - // is suppressed here to avoid putting a "bx lr" in the inline assembly - // above and a superfluous return statement here. - // -#pragma diag_suppress=Pe940 -} -#pragma diag_default=Pe940 -#endif -#if defined(__CC_ARM) -__asm uint32_t CPU_basepriGet(void) -{ - // - // Read BASEPRI - // - mrs r0, BASEPRI; - bx lr -} -#endif -#if defined(__TI_ARM__) -uint32_t CPU_basepriGet(void) -{ - // - // Read BASEPRI - // - __asm(" mrs r0, BASEPRI\n" - " bx lr\n"); - - // - // The following keeps the compiler happy, because it wants to see a - // return value from this function. It will generate code to return - // a zero. However, the real return is the "bx lr" above, so the - // return(0) is never executed and the function returns with the value - // you expect in R0. - // - return(0); -} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/cpu.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/cpu.h deleted file mode 100644 index 802fd81c7e7..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/cpu.h +++ /dev/null @@ -1,71 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __CPU_H__ -#define __CPU_H__ - -#include - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Prototypes. -// -//***************************************************************************** -extern uint32_t CPU_cpsid(void); -extern uint32_t CPU_cpsie(void); -extern uint32_t CPU_primask(void); -extern void CPU_wfi(void); -extern uint32_t CPU_basepriGet(void); -extern void CPU_basepriSet(uint32_t newBasepri); - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __CPU_H__ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/crc32.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/crc32.c deleted file mode 100644 index 70dd8789f9e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/crc32.c +++ /dev/null @@ -1,142 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include - - -void CRC32_setSeed(uint32_t seed, uint_fast8_t crcType) -{ - ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType)); - - if (CRC16_MODE == crcType) - CRC32->INIRES16 = seed; - else - { - CRC32->INIRES32_HI = ((seed & 0xFFFF0000) >> 16); - CRC32->INIRES32_LO = (seed & 0xFFFF); - } -} - -void CRC32_set8BitData(uint8_t dataIn, uint_fast8_t crcType) -{ - ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType)); - - if (CRC16_MODE == crcType) - HWREG8(&(CRC32->DI16)) = dataIn; - else - HWREG8(&(CRC32->DI32)) = dataIn; -} - -void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType) -{ - ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType)); - - if (CRC16_MODE == crcType) - CRC32->DI16 = dataIn; - else - CRC32->DI32 = dataIn; -} - -void CRC32_set32BitData(uint32_t dataIn) -{ - //CRC32->DI32 = dataIn & 0xFFFF; - //CRC32->DI32 = (uint16_t) ((dataIn & 0xFFFF0000) >> 16); - - HWREG16(&(CRC32->DI32)) = dataIn & 0xFFFF; - HWREG16(&(CRC32->DI32)) = (uint16_t)( - (dataIn & 0xFFFF0000) >> 16); -} - -void CRC32_set8BitDataReversed(uint8_t dataIn, uint_fast8_t crcType) -{ - ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType)); - - if (CRC16_MODE == crcType) - HWREG8(&(CRC32->DIRB16)) = dataIn; - else - HWREG8(&(CRC32->DIRB32)) = dataIn; -} - -void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType) -{ - ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType)); - - if (CRC16_MODE == crcType) - CRC32->DIRB16 = dataIn; - else - CRC32->DIRB32 = dataIn; -} - -void CRC32_set32BitDataReversed(uint32_t dataIn) -{ - //CRC32->DIRB32 = dataIn & 0xFFFF; - //CRC32->DIRB32 = (uint16_t) ((dataIn & 0xFFFF0000) >> 16); - - HWREG16(&(CRC32->DIRB32)) = dataIn & 0xFFFF; - HWREG16(&(CRC32->DIRB32)) = (uint16_t)( - (dataIn & 0xFFFF0000) >> 16); - -} - -uint32_t CRC32_getResult(uint_fast8_t crcType) -{ - uint32_t result; - ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType)); - - if (CRC16_MODE == crcType) - return CRC32->INIRES16; - else - { - result = CRC32->INIRES32_HI; - result = (result << 16); - result |= CRC32->INIRES32_LO; - return (result); - } -} - -uint32_t CRC32_getResultReversed(uint_fast8_t crcType) -{ - uint32_t result; - ASSERT((CRC16_MODE == crcType) || (CRC32_MODE == crcType)); - - if (CRC16_MODE == crcType) - return CRC32->RESR16; - else - { - result = CRC32->RESR32_HI; - result = (result << 16); - result |= CRC32->RESR32_LO; - return (result); - } -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/crc32.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/crc32.h deleted file mode 100644 index 03f68e69c68..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/crc32.h +++ /dev/null @@ -1,230 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef _CRC_32_H - -//***************************************************************************** -// -//! \addtogroup crc32_api -//! @{ -// -//***************************************************************************** - -#include - -#define CRC16_MODE 0x00 -#define CRC32_MODE 0x01 - -//***************************************************************************** -// -//! Sets the seed for the CRC. -//! -//! \param seed is the seed for the CRC to start generating a signature from. -//! Modified bits are \b CRC16INIRESL0 of \b CRC16INIRESL0 register. -//! \b CRC32INIRESL0 of \b CRC32INIRESL0 register -//! \param crcType selects between CRC32 and CRC16 -//! Valid values are \b CRC16_MODE and \b CRC32_MODE -//! -//! This function sets the seed for the CRC to begin generating a signature with -//! the given seed and all passed data. Using this function resets the CRC32 -//! signature. -//! -//! \return NONE -// -//***************************************************************************** -extern void CRC32_setSeed(uint32_t seed, uint_fast8_t crcType); - -//***************************************************************************** -// -//! Sets the 8 Bit data to add into the CRC module to generate a new signature. -//! -//! \param dataIn is the data to be added, through the CRC module, to the -//! signature. -//! Modified bits are \b CRC16DIB0 of \b CRC16DIB0 register. -//! \b CRC32DIB0 of \b CRC32DIB0 register. -//! \param crcType selects between CRC32 and CRC16 -//! Valid values are \b CRC16_MODE and \b CRC32_MODE -//! -//! This function sets the given data into the CRC module to generate the new -//! signature from the current signature and new data. Bit 0 is -//! treated as LSB. -//! -//! \return NONE -// -//***************************************************************************** -extern void CRC32_set8BitData(uint8_t dataIn, uint_fast8_t crcType); - -//***************************************************************************** -// -//! Sets the 16 Bit data to add into the CRC module to generate a new signature. -//! -//! \param dataIn is the data to be added, through the CRC module, to the -//! signature. -//! Modified bits are \b CRC16DIW0 of \b CRC16DIW0 register. -//! \b CRC32DIW0 of \b CRC32DIW0 register. -//! \param crcType selects between CRC32 and CRC16 -//! Valid values are \b CRC16_MODE and \b CRC32_MODE -//! -//! This function sets the given data into the CRC module to generate the new -//! signature from the current signature and new data. Bit 0 is -//! treated as LSB -//! -//! \return NONE -// -//***************************************************************************** -extern void CRC32_set16BitData(uint16_t dataIn, uint_fast8_t crcType); - -//***************************************************************************** -// -//! Sets the 32 Bit data to add into the CRC module to generate a new signature. -//! Available only for CRC32_MODE and not for CRC16_MODE -//! \param dataIn is the data to be added, through the CRC module, to the -//! signature. -//! Modified bits are \b CRC32DIL0 of \b CRC32DIL0 register. -//! -//! This function sets the given data into the CRC module to generate the new -//! signature from the current signature and new data. Bit 0 is -//! treated as LSB -//! -//! \return NONE -// -//***************************************************************************** -extern void CRC32_set32BitData(uint32_t dataIn); - -//***************************************************************************** -// -//! Translates the data by reversing the bits in each 8 bit data and then sets -//! this data to add into the CRC module to generate a new signature. -//! -//! \param dataIn is the data to be added, through the CRC module, to the -//! signature. -//! Modified bits are \b CRC16DIRBB0 of \b CRC16DIRBB0 register. -//! \b CRC32DIRBB0 of \b CRC32DIRBB0 register. -//! \param crcType selects between CRC32 and CRC16 -//! Valid values are \b CRC16_MODE and \b CRC32_MODE -//! -//! This function first reverses the bits in each byte of the data and then -//! generates the new signature from the current signature and new translated -//! data. Bit 0 is treated as MSB. -//! -//! \return NONE -// -//***************************************************************************** -extern void CRC32_set8BitDataReversed(uint8_t dataIn, uint_fast8_t crcType); - -//***************************************************************************** -// -//! Translates the data by reversing the bits in each 16 bit data and then -//! sets this data to add into the CRC module to generate a new signature. -//! -//! \param dataIn is the data to be added, through the CRC module, to the -//! signature. -//! Modified bits are \b CRC16DIRBW0 of \b CRC16DIRBW0 register. -//! \b CRC32DIRBW0 of \b CRC32DIRBW0 register. -//! \param crcType selects between CRC32 and CRC16 -//! Valid values are \b CRC16_MODE and \b CRC32_MODE -//! -//! This function first reverses the bits in each byte of the data and then -//! generates the new signature from the current signature and new translated -//! data. Bit 0 is treated as MSB. -//! -//! \return NONE -// -//***************************************************************************** -extern void CRC32_set16BitDataReversed(uint16_t dataIn, uint_fast8_t crcType); - -//***************************************************************************** -// -//! Translates the data by reversing the bits in each 32 Bit Data and then -//! sets this data to add into the CRC module to generate a new signature. -//! Available only for CRC32 mode and not for CRC16 mode -//! \param dataIn is the data to be added, through the CRC module, to the -//! signature. -//! Modified bits are \b CRC32DIRBL0 of \b CRC32DIRBL0 register. -//! -//! This function first reverses the bits in each byte of the data and then -//! generates the new signature from the current signature and new translated -//! data. Bit 0 is treated as MSB. -//! -//! \return NONE -// -//***************************************************************************** -extern void CRC32_set32BitDataReversed(uint32_t dataIn); - -//***************************************************************************** -// -//! Returns the value of CRC Signature Result. -//! -//! \param crcType selects between CRC32 and CRC16 -//! Valid values are \b CRC16_MODE and \b CRC32_MODE -//! -//! This function returns the value of the signature result generated by the CRC. -//! Bit 0 is treated as LSB. -//! \return uint32_t Result -// -//***************************************************************************** -extern uint32_t CRC32_getResult(uint_fast8_t crcType); - -//***************************************************************************** -// -//! Returns the bit-wise reversed format of the 32 bit Signature Result. -//! -//! \param crcType selects between CRC32 and CRC16 -//! Valid values are \b CRC16_MODE and \b CRC32_MODE -//! -//! This function returns the bit-wise reversed format of the Signature Result. -//! Bit 0 is treated as MSB. -//! -//! \return uint32_t Result -// -//***************************************************************************** -extern uint32_t CRC32_getResultReversed(uint_fast8_t crcType); - -/* Defines for future devices that might have multiple instances */ -#define CRC32_setSeedMultipleInstance(a,b,c) CRC32_setSeed(b,c) -#define CRC32_set8BitDataMultipleInstance(a,b,c) CRC32_set8BitData(b,c) -#define CRC32_set16BitDataMultipleInstance(a,b,c) CRC32_set16BitData(b,c) -#define CRC32_set32BitDataMultipleInstance(a,b) CRC32_set32BitData(b) -#define CRC32_set8BitDataReversedMultipleInstance(a,b,c) CRC32_set8BitDataReversed(b,c) -#define CRC32_set16BitDataReversedMultipleInstance(a,b,c) CRC32_set16BitDataReversed(b,c) -#define CRC32_set32BitDataReversedMultipleInstance(a,b) CRC32_set32BitDataReversed(b) -#define CRC32_getResultMultipleInstance(a,b) CRC32_getResult() -#define CRC32_getResultReversedMultipleInstance(a,b) CRC32_getResultReversed(b) - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/cs.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/cs.c deleted file mode 100644 index 6c2a9ac7e35..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/cs.c +++ /dev/null @@ -1,995 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/* Standard Includes */ -#include - -/* DriverLib Includes */ -#include -#include -#include - -#ifdef __MCU_HAS_SYSCTL_A__ -#include -#else -#include -#endif - -/* Statics */ -static uint32_t hfxtFreq; -static uint32_t lfxtFreq; - -#ifdef DEBUG - -bool _CSIsClockDividerValid(uint8_t divider) -{ - return ((divider == CS_CLOCK_DIVIDER_1) || (divider == CS_CLOCK_DIVIDER_2) - || (divider == CS_CLOCK_DIVIDER_4) || (divider == CS_CLOCK_DIVIDER_8) - || (divider == CS_CLOCK_DIVIDER_16) || (divider == CS_CLOCK_DIVIDER_32) - || (divider == CS_CLOCK_DIVIDER_64) || (divider == CS_CLOCK_DIVIDER_128)); -} - -#endif - -static uint32_t _CSGetHFXTFrequency() -{ - if (hfxtFreq >= CS_1MHZ && hfxtFreq <= CS_4MHZ) - return CS_CTL2_HFXTFREQ_0; - else if (hfxtFreq > CS_4MHZ && hfxtFreq <= CS_8MHZ) - return CS_CTL2_HFXTFREQ_1; - else if (hfxtFreq > CS_8MHZ && hfxtFreq <= CS_16MHZ) - return CS_CTL2_HFXTFREQ_2; - else if (hfxtFreq > CS_16MHZ && hfxtFreq <= CS_24MHZ) - return CS_CTL2_HFXTFREQ_3; - else if (hfxtFreq > CS_24MHZ && hfxtFreq <= CS_32MHZ) - return CS_CTL2_HFXTFREQ_4; - else if (hfxtFreq > CS_32MHZ && hfxtFreq <= CS_40MHZ) - return CS_CTL2_HFXTFREQ_5; - else if (hfxtFreq > CS_40MHZ && hfxtFreq <= CS_48MHZ) - return CS_CTL2_HFXTFREQ_6; - else - { - ASSERT(false); - return 0; - } - -} - -static uint32_t _CSGetDividerValue(uint32_t wDivider) -{ - switch (wDivider) - { - case CS_CLOCK_DIVIDER_1: - return 1; - case CS_CLOCK_DIVIDER_2: - return 2; - case CS_CLOCK_DIVIDER_4: - return 4; - case CS_CLOCK_DIVIDER_8: - return 8; - case CS_CLOCK_DIVIDER_16: - return 16; - case CS_CLOCK_DIVIDER_32: - return 32; - case CS_CLOCK_DIVIDER_64: - return 64; - case CS_CLOCK_DIVIDER_128: - return 128; - default: - ASSERT(false); - return 1; - } -} - -static uint32_t _CSComputeCLKFrequency(uint32_t wClockSource, uint32_t wDivider) -{ - uint_fast8_t bDivider; - - bDivider = _CSGetDividerValue(wDivider); - - switch (wClockSource) - { - case CS_LFXTCLK_SELECT: - { - if (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - CS_clearInterruptFlag(CS_LFXT_FAULT); - - if (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - return (128000 / bDivider); - else - return (32768 / bDivider); - } - } - return lfxtFreq / bDivider; - } - case CS_HFXTCLK_SELECT: - { - if (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - CS_clearInterruptFlag(CS_HFXT_FAULT); - - if (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - return (128000 / bDivider); - else - return (32768 / bDivider); - } - } - return hfxtFreq / bDivider; - } - case CS_VLOCLK_SELECT: - return CS_VLOCLK_FREQUENCY / bDivider; - case CS_REFOCLK_SELECT: - { - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - return (128000 / bDivider); - else - return (32768 / bDivider); - } - case CS_DCOCLK_SELECT: - return (CS_getDCOFrequency() / bDivider); - case CS_MODOSC_SELECT: - return CS_MODCLK_FREQUENCY / bDivider; - default: - ASSERT(false); - return 0; - } -} - -//****************************************************************************** -// Internal function for getting DCO nominal frequency -//****************************************************************************** -static uint32_t _CSGetDOCFrequency(void) -{ - uint32_t dcoFreq; - - switch (CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - dcoFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - dcoFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - dcoFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - dcoFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - dcoFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - dcoFreq = 48000000; - break; - default: - dcoFreq = 0; - } - - return (dcoFreq); -} - -void CS_setExternalClockSourceFrequency(uint32_t lfxt_XT_CLK_frequency, - uint32_t hfxt_XT_CLK_frequency) -{ - hfxtFreq = hfxt_XT_CLK_frequency; - lfxtFreq = lfxt_XT_CLK_frequency; -} - -void CS_initClockSignal(uint32_t selectedClockSignal, uint32_t clockSource, - uint32_t clockSourceDivider) -{ - ASSERT(_CSIsClockDividerValid(clockSourceDivider)); - - /* Unlocking the CS Module */ - CS->KEY = CS_KEY; - - switch (selectedClockSignal) - { - case CS_ACLK: - { - /* Making sure that the clock signal for ACLK isn't set to anything - * invalid - */ - ASSERT( - (selectedClockSignal != CS_DCOCLK_SELECT) - && (selectedClockSignal != CS_MODOSC_SELECT) - && (selectedClockSignal != CS_HFXTCLK_SELECT)); - - /* Waiting for the clock source ready bit to be valid before - * changing */ - while (!BITBAND_PERI(CS->STAT, CS_STAT_ACLK_READY_OFS)) - ; - - /* Setting the divider and source */ - CS->CTL1 = ((clockSourceDivider >> CS_ACLK_DIV_BITPOS) - | (clockSource << CS_ACLK_SRC_BITPOS)) - | (CS->CTL1 & ~(CS_CTL1_SELA_MASK | CS_CTL1_DIVA_MASK)); - - /* Waiting for ACLK to be ready again */ - while (!BITBAND_PERI(CS->STAT, CS_STAT_ACLK_READY_OFS)) - ; - - break; - } - case CS_MCLK: - { - - /* Waiting for the clock source ready bit to be valid before - * changing */ - while (!BITBAND_PERI(CS->STAT, CS_STAT_MCLK_READY_OFS)) - ; - - CS->CTL1 = ((clockSourceDivider >> CS_MCLK_DIV_BITPOS) - | (clockSource << CS_MCLK_SRC_BITPOS)) - | (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)); - - /* Waiting for MCLK to be ready */ - while (!BITBAND_PERI(CS->STAT, CS_STAT_MCLK_READY_OFS)) - ; - - break; - } - case CS_SMCLK: - { - /* Waiting for the clock source ready bit to be valid before - * changing */ - while (!BITBAND_PERI(CS->STAT, CS_STAT_SMCLK_READY_OFS)) - ; - - CS->CTL1 = ((clockSourceDivider >> CS_SMCLK_DIV_BITPOS) - | (clockSource << CS_HSMCLK_SRC_BITPOS)) - | (CS->CTL1 & ~(CS_CTL1_DIVS_MASK | CS_CTL1_SELS_MASK)); - - /* Waiting for SMCLK to be ready */ - while (!BITBAND_PERI(CS->STAT, CS_STAT_SMCLK_READY_OFS)) - ; - - break; - } - case CS_HSMCLK: - { - /* Waiting for the clock source ready bit to be valid before - * changing */ - while (!BITBAND_PERI(CS->STAT, CS_STAT_HSMCLK_READY_OFS)) - ; - - CS->CTL1 = ((clockSourceDivider >> CS_HSMCLK_DIV_BITPOS) - | (clockSource << CS_HSMCLK_SRC_BITPOS)) - | (CS->CTL1 & ~(CS_CTL1_DIVHS_MASK | CS_CTL1_SELS_MASK)); - - /* Waiting for HSMCLK to be ready */ - while (!BITBAND_PERI(CS->STAT, CS_STAT_HSMCLK_READY_OFS)) - ; - - break; - } - case CS_BCLK: - { - - /* Waiting for the clock source ready bit to be valid before - * changing */ - while (!BITBAND_PERI(CS->STAT, CS_STAT_BCLK_READY_OFS)) - ; - - /* Setting the clock source and then returning - * (cannot divide CLK) - */ - if (clockSource == CS_LFXTCLK_SELECT) - BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS) = 0; - else if (clockSource == CS_REFOCLK_SELECT) - BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS) = 1; - else - ASSERT(false); - - /* Waiting for BCLK to be ready */ - while (!BITBAND_PERI(CS->STAT, CS_STAT_BCLK_READY_OFS)) - ; - - break; - } - default: - { - /* Should never get here */ - ASSERT(false); - } - } - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -bool CS_startHFXT(bool bypassMode) -{ - return CS_startHFXTWithTimeout(bypassMode, 0); -} - -bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout) -{ - uint32_t wHFFreqRange; - uint_fast8_t bNMIStatus; - bool boolTimeout; - - /* Unlocking the CS Module */ - CS->KEY = CS_KEY; - - /* Saving status and temporarily disabling NMIs for UCS faults */ -#ifdef __MCU_HAS_SYSCTL_A__ - bNMIStatus = SysCtl_A_getNMISourceStatus() & SYSCTL_A_CS_SRC; - SysCtl_A_disableNMISource(SYSCTL_A_CS_SRC); -#else - bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC; - SysCtl_disableNMISource(SYSCTL_CS_SRC); -#endif - - /* Determining which frequency range to use */ - wHFFreqRange = _CSGetHFXTFrequency(); - boolTimeout = (timeout == 0) ? false : true; - - /* Setting to maximum drive strength */ - BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 1; - CS->CTL2 = (CS->CTL2 & (~CS_CTL2_HFXTFREQ_MASK)) | (wHFFreqRange); - - if (bypassMode) - { - BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTBYPASS_OFS) = 1; - } else - { - BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTBYPASS_OFS) = 0; - } - - /* Starting and Waiting for frequency stabilization */ - BITBAND_PERI(CS->CTL2, CS_CTL2_HFXT_EN_OFS) = 1; - while (BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if (boolTimeout && ((--timeout) == 0)) - break; - - BITBAND_PERI(CS->CLRIFG,CS_CLRIFG_CLR_HFXTIFG_OFS) = 1; - } - - /* Setting the drive strength */ - if (!bypassMode) - { - if (wHFFreqRange != CS_CTL2_HFXTFREQ_0) - BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 1; - else - BITBAND_PERI(CS->CTL2, CS_CTL2_HFXTDRIVE_OFS) = 0; - } - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; - - /* Enabling the NMI state */ -#ifdef __MCU_HAS_SYSCTL_A__ - SysCtl_A_enableNMISource(bNMIStatus); -#else - SysCtl_enableNMISource(bNMIStatus); -#endif - - if (boolTimeout && timeout == 0) - return false; - - return true; -} - -bool CS_startLFXT(uint32_t xtDrive) -{ - return CS_startLFXTWithTimeout(xtDrive, 0); -} - -bool CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout) -{ - uint8_t bNMIStatus; - bool boolBypassMode, boolTimeout; - - ASSERT(lfxtFreq != 0) - ASSERT( - (xtDrive == CS_LFXT_DRIVE0) || (xtDrive == CS_LFXT_DRIVE1) - || (xtDrive == CS_LFXT_DRIVE2) - || (xtDrive == CS_LFXT_DRIVE3) - || (xtDrive == CS_LFXT_BYPASS)); - - /* Unlocking the CS Module */ - CS->KEY = CS_KEY; - - /* Saving status and temporarily disabling NMIs for UCS faults */ -#ifdef __MCU_HAS_SYSCTL_A__ - bNMIStatus = SysCtl_A_getNMISourceStatus() & SYSCTL_A_CS_SRC; - SysCtl_A_disableNMISource(SYSCTL_A_CS_SRC); -#else - bNMIStatus = SysCtl_getNMISourceStatus() & SYSCTL_CS_SRC; - SysCtl_disableNMISource(SYSCTL_CS_SRC); -#endif - boolBypassMode = (xtDrive == CS_LFXT_BYPASS) ? true : false; - boolTimeout = (timeout == 0) ? false : true; - - /* Setting to maximum drive strength */ - if (boolBypassMode) - { - BITBAND_PERI(CS->CTL2, CS_CTL2_LFXTBYPASS_OFS) = 1; - } else - { - CS->CTL2 |= (CS_LFXT_DRIVE3); - BITBAND_PERI(CS->CTL2, CS_CTL2_LFXTBYPASS_OFS) = 0; - } - - /* Waiting for frequency stabilization */ - BITBAND_PERI(CS->CTL2, CS_CTL2_LFXT_EN_OFS) = 1; - - while (BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if (boolTimeout && ((--timeout) == 0)) - break; - - BITBAND_PERI(CS->CLRIFG,CS_CLRIFG_CLR_LFXTIFG_OFS) = 1; - } - - /* Setting the drive strength */ - if (!boolBypassMode) - { - CS->CTL2 = ((CS->CTL2 & ~CS_LFXT_DRIVE3) | xtDrive); - } - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; - - /* Enabling the NMI state */ -#ifdef __MCU_HAS_SYSCTL_A__ - SysCtl_A_enableNMISource(bNMIStatus); -#else - SysCtl_enableNMISource(bNMIStatus); -#endif - - if (boolTimeout && timeout == 0) - return false; - - return true; -} - -void CS_enableClockRequest(uint32_t selectClock) -{ - ASSERT( - selectClock == CS_ACLK || selectClock == CS_HSMCLK - || selectClock == CS_SMCLK || selectClock == CS_MCLK); - - /* Unlocking the module */ - CS->KEY = CS_KEY; - - CS->CLKEN |= selectClock; - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -void CS_disableClockRequest(uint32_t selectClock) -{ - ASSERT( - selectClock == CS_ACLK || selectClock == CS_HSMCLK - || selectClock == CS_SMCLK || selectClock == CS_MCLK); - - /* Unlocking the module */ - CS->KEY = CS_KEY; - - CS->CLKEN &= ~selectClock; - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -void CS_setReferenceOscillatorFrequency(uint8_t referenceFrequency) -{ - ASSERT( - referenceFrequency == CS_REFO_32KHZ - || referenceFrequency == CS_REFO_128KHZ); - - /* Unlocking the module */ - CS->KEY = CS_KEY; - - BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS) = referenceFrequency; - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -void CS_enableDCOExternalResistor(void) -{ - /* Unlocking the module */ - CS->KEY = CS_KEY; - - BITBAND_PERI(CS->CTL0,CS_CTL0_DCORES_OFS) = 1; - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -void CS_setDCOExternalResistorCalibration(uint_fast8_t calData, - uint_fast8_t freqRange) -{ - uint_fast8_t rselVal; - - /* Unlocking the module */ - CS->KEY = CS_KEY; - - rselVal = (CS->CTL0 | CS_CTL0_DCORSEL_MASK) >> CS_CTL0_DCORSEL_OFS; - - CS->CTL0 &= ~CS_CTL0_DCORSEL_MASK; - - if ((freqRange == CS_OVER32MHZ)) - { - CS->DCOERCAL1 &= ~CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK; - CS->DCOERCAL1 |= (calData); - } else - { - CS->DCOERCAL0 &= ~CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK; - CS->DCOERCAL0 |= (calData) << CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS; - } - - CS->CTL0 |= (rselVal) << CS_CTL0_DCORSEL_OFS; - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; - -} - -void CS_disableDCOExternalResistor(void) -{ - /* Unlocking the module */ - CS->KEY = CS_KEY; - - BITBAND_PERI(CS->CTL0,CS_CTL0_DCORES_OFS) = 0; - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -void CS_setDCOCenteredFrequency(uint32_t dcoFreq) -{ - ASSERT( - dcoFreq == CS_DCO_FREQUENCY_1_5 || dcoFreq == CS_DCO_FREQUENCY_3 - || dcoFreq == CS_DCO_FREQUENCY_6 - || dcoFreq == CS_DCO_FREQUENCY_12 - || dcoFreq == CS_DCO_FREQUENCY_24 - || dcoFreq == CS_DCO_FREQUENCY_48); - - /* Unlocking the CS Module */ - CS->KEY = CS_KEY; - - /* Resetting Tuning Parameters and Setting the frequency */ - CS->CTL0 = ((CS->CTL0 & ~CS_CTL0_DCORSEL_MASK) | dcoFreq); - - /* Locking the CS Module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -void CS_tuneDCOFrequency(int16_t tuneParameter) -{ - CS->KEY = CS_KEY; - - uint16_t dcoTuneMask = 0x1FFF; - uint16_t dcoTuneSigned = 0x1000; - - dcoTuneMask = 0x3FF; - dcoTuneSigned = 0x200; - - if (tuneParameter < 0) - { - CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter & dcoTuneMask) - | dcoTuneSigned); - } else - { - CS->CTL0 = ((CS->CTL0 & ~dcoTuneMask) | (tuneParameter & dcoTuneMask)); - } - - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -uint32_t CS_getDCOFrequency(void) -{ - float dcoConst; - int32_t calVal; - uint32_t centeredFreq; - int16_t dcoTune; - uint_fast8_t tlvLength; - uint32_t retVal; - -#ifdef __MCU_HAS_SYSCTL_A__ - SysCtl_A_CSCalTLV_Info *csInfo; - - /* Parsing the TLV and getting the trim information */ - SysCtl_A_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**) &csInfo); -#else - SysCtl_CSCalTLV_Info *csInfo; - - /* Parsing the TLV and getting the trim information */ - SysCtl_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**) &csInfo); -#endif - - centeredFreq = _CSGetDOCFrequency(); - - if (tlvLength == 0) - { - return centeredFreq; - } - - dcoTune = CS->CTL0 & 0x3FF; - if (dcoTune & 0x200) - { - dcoTune = dcoTune | 0xFE00; - } - - if (dcoTune == 0) - return (uint32_t) centeredFreq; - - /* DCORSEL = 5 */ - if ((centeredFreq == 48000000)) - { - /* External Resistor */ - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL5); - calVal = csInfo->rDCOER_FCAL_RSEL5; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL5); - calVal = csInfo->rDCOIR_FCAL_RSEL5; - } - } - /* DCORSEL = 4 */ - else - { - /* External Resistor */ - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL04); - calVal = csInfo->rDCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL04); - calVal = csInfo->rDCOIR_FCAL_RSEL04; - } - } - retVal = (uint32_t) (centeredFreq) - / (1 - ((dcoConst * dcoTune) / ((1 + dcoConst * (768 - calVal))))); - - return retVal; -} - -void CS_setDCOFrequency(uint32_t dcoFrequency) -{ - int32_t nomFreq, calVal, dcoSigned; - int16_t dcoTune; - float dcoConst; - bool rsel5 = false; - dcoSigned = (int32_t) dcoFrequency; - uint_fast8_t tlvLength; - -#ifdef __MCU_HAS_SYSCTL_A__ - SysCtl_A_CSCalTLV_Info *csInfo; - - /* Parsing the TLV and getting the trim information */ - SysCtl_A_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**) &csInfo); -#else - SysCtl_CSCalTLV_Info *csInfo; - - /* Parsing the TLV and getting the trim information */ - SysCtl_getTLVInfo(TLV_TAG_CS, 0, &tlvLength, (uint32_t**) &csInfo); -#endif - - - if (dcoFrequency < 2000000) - { - nomFreq = CS_15MHZ; - CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_1_5); - } else if (dcoFrequency < 4000000) - { - nomFreq = CS_3MHZ; - CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_3); - } else if (dcoFrequency < 8000000) - { - nomFreq = CS_6MHZ; - CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_6); - } else if (dcoFrequency < 16000000) - { - nomFreq = CS_12MHZ; - CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_12); - } else if (dcoFrequency < 32000000) - { - nomFreq = CS_24MHZ; - CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_24); - } else if (dcoFrequency < 640000001) - { - nomFreq = CS_48MHZ; - CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48); - rsel5 = true; - } else - { - ASSERT(false); - return; - } - - if (dcoFrequency == nomFreq || tlvLength == 0) - { - CS_tuneDCOFrequency(0); - return; - } - - if (rsel5) - { - /* External Resistor*/ - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL5); - calVal = csInfo->rDCOER_FCAL_RSEL5; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL5); - calVal = csInfo->rDCOIR_FCAL_RSEL5; - } - } - /* DCORSEL = 4 */ - else - { - /* External Resistor */ - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &csInfo->rDCOER_CONSTK_RSEL04); - calVal = csInfo->rDCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &csInfo->rDCOIR_CONSTK_RSEL04); - calVal = csInfo->rDCOIR_FCAL_RSEL04; - } - } - - dcoTune = (int16_t) (((dcoSigned - nomFreq) - * (1.0f + dcoConst * (768.0f - calVal))) / (dcoSigned * dcoConst)); - - CS_tuneDCOFrequency(dcoTune); - -} - -uint32_t CS_getBCLK(void) -{ - if (BITBAND_PERI(CS->CTL1, CS_CTL1_SELB_OFS)) - return _CSComputeCLKFrequency(CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1); - else - return _CSComputeCLKFrequency(CS_LFXTCLK_SELECT, CS_CLOCK_DIVIDER_1); -} - -uint32_t CS_getHSMCLK(void) -{ - uint32_t wSource, wDivider; - - wSource = (CS->CTL1 & CS_CTL1_SELS_MASK) >> CS_HSMCLK_SRC_BITPOS; - wDivider = ((CS->CTL1 & CS_CTL1_DIVHS_MASK) << CS_HSMCLK_DIV_BITPOS); - - return _CSComputeCLKFrequency(wSource, wDivider); -} - -uint32_t CS_getACLK(void) -{ - uint32_t wSource, wDivider; - - wSource = (CS->CTL1 & CS_CTL1_SELA_MASK) >> CS_ACLK_SRC_BITPOS; - wDivider = ((CS->CTL1 & CS_CTL1_DIVA_MASK) << CS_ACLK_DIV_BITPOS); - - return _CSComputeCLKFrequency(wSource, wDivider); -} - -uint32_t CS_getSMCLK(void) -{ - uint32_t wDivider, wSource; - - wSource = (CS->CTL1 & CS_CTL1_SELS_MASK) >> CS_HSMCLK_SRC_BITPOS; - wDivider = ((CS->CTL1 & CS_CTL1_DIVS_MASK)); - - return _CSComputeCLKFrequency(wSource, wDivider); - -} - -uint32_t CS_getMCLK(void) -{ - uint32_t wSource, wDivider; - - wSource = (CS->CTL1 & CS_CTL1_SELM_MASK) << CS_MCLK_SRC_BITPOS; - wDivider = ((CS->CTL1 & CS_CTL1_DIVM_MASK) << CS_MCLK_DIV_BITPOS); - - return _CSComputeCLKFrequency(wSource, wDivider); -} - -void CS_enableFaultCounter(uint_fast8_t counterSelect) -{ - ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER || - counterSelect == CS_HFXT_FAULT_COUNTER); - - /* Unlocking the module */ - CS->KEY = CS_KEY; - - if (counterSelect == CS_HFXT_FAULT_COUNTER) - { - BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTHF_EN_OFS) = 1; - } else - { - BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTLF_EN_OFS) = 1; - } - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -void CS_disableFaultCounter(uint_fast8_t counterSelect) -{ - ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER || - counterSelect == CS_HFXT_FAULT_COUNTER); - - /* Unlocking the module */ - CS->KEY = CS_KEY; - - if (counterSelect == CS_HFXT_FAULT_COUNTER) - { - BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTHF_EN_OFS) = 0; - } else - { - BITBAND_PERI(CS->CTL3, CS_CTL3_FCNTLF_EN_OFS) = 0; - } - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -void CS_resetFaultCounter(uint_fast8_t counterSelect) -{ - ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER || - counterSelect == CS_HFXT_FAULT_COUNTER); - - /* Unlocking the module */ - CS->KEY = CS_KEY; - - if (counterSelect == CS_HFXT_FAULT_COUNTER) - { - BITBAND_PERI(CS->CTL3, CS_CTL3_RFCNTHF_OFS) = 1; - } else - { - BITBAND_PERI(CS->CTL3, CS_CTL3_RFCNTLF_OFS) = 1; - } - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -void CS_startFaultCounter(uint_fast8_t counterSelect, uint_fast8_t countValue) -{ - ASSERT(counterSelect == CS_HFXT_FAULT_COUNTER || - counterSelect == CS_HFXT_FAULT_COUNTER); - - ASSERT(countValue == CS_FAULT_COUNTER_4096_CYCLES || - countValue == CS_FAULT_COUNTER_8192_CYCLES || - countValue == CS_FAULT_COUNTER_16384_CYCLES || - countValue == CS_FAULT_COUNTER_32768_CYCLES); - - /* Unlocking the module */ - CS->KEY = CS_KEY; - - if (counterSelect == CS_HFXT_FAULT_COUNTER) - { - CS->CTL3 = ((CS->CTL3 & ~CS_CTL3_FCNTHF_MASK) | (countValue << 4)); - } else - { - CS->CTL3 = ((CS->CTL3 & ~CS_CTL3_FCNTLF_MASK) | (countValue)); - } - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -void CS_enableInterrupt(uint32_t flags) -{ - /* Unlocking the module */ - CS->KEY = CS_KEY; - - CS->IE |= flags; - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -void CS_disableInterrupt(uint32_t flags) -{ - /* Unlocking the module */ - CS->KEY = CS_KEY; - - CS->IE &= ~flags; - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -uint32_t CS_getInterruptStatus(void) -{ - return CS->IFG; -} - -uint32_t CS_getEnabledInterruptStatus(void) -{ - return CS_getInterruptStatus() & CS->IE; -} - -void CS_clearInterruptFlag(uint32_t flags) -{ - /* Unlocking the module */ - CS->KEY = CS_KEY; - - CS->CLRIFG |= flags; - - /* Locking the module */ - BITBAND_PERI(CS->KEY, CS_KEY_KEY_OFS) = 1; -} - -void CS_registerInterrupt(void (*intHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - Interrupt_registerInterrupt(INT_CS, intHandler); - - // - // Enable the system control interrupt. - // - Interrupt_enableInterrupt(INT_CS); -} - -void CS_unregisterInterrupt(void) -{ - // - // Disable the interrupt. - // - Interrupt_disableInterrupt(INT_CS); - - // - // Unregister the interrupt handler. - // - Interrupt_unregisterInterrupt(INT_CS); -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/cs.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/cs.h deleted file mode 100644 index 289d2a46c64..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/cs.h +++ /dev/null @@ -1,818 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __CS_H__ -#define __CS_H__ - -//***************************************************************************** -// -//! \addtogroup cs_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include - -//***************************************************************************** -// -// Control specific variables -// -//***************************************************************************** -#define CS_CLOCK_DIVIDER_1 CS_CTL1_DIVS_0 -#define CS_CLOCK_DIVIDER_2 CS_CTL1_DIVS_1 -#define CS_CLOCK_DIVIDER_4 CS_CTL1_DIVS_2 -#define CS_CLOCK_DIVIDER_8 CS_CTL1_DIVS_3 -#define CS_CLOCK_DIVIDER_16 CS_CTL1_DIVS_4 -#define CS_CLOCK_DIVIDER_32 CS_CTL1_DIVS_5 -#define CS_CLOCK_DIVIDER_64 CS_CTL1_DIVS_6 -#define CS_CLOCK_DIVIDER_128 CS_CTL1_DIVS_7 - -#define CS_LFXTCLK_SELECT CS_CTL1_SELM_0 -#define CS_HFXTCLK_SELECT CS_CTL1_SELM_5 -#define CS_VLOCLK_SELECT CS_CTL1_SELM_1 -#define CS_REFOCLK_SELECT CS_CTL1_SELM_2 -#define CS_DCOCLK_SELECT CS_CTL1_SELM_3 -#define CS_MODOSC_SELECT CS_CTL1_SELM_4 - -#define CS_KEY 0x695A - -/* Number of positions to shift for divider calculation */ -#define CS_ACLK_DIV_BITPOS 0x04 -#define CS_MCLK_DIV_BITPOS 0x0C -#define CS_SMCLK_DIV_BITPOS 0x00 -#define CS_HSMCLK_DIV_BITPOS 0x08 - -/* Number of positions to shift for source calculation */ -#define CS_ACLK_SRC_BITPOS 0x08 -#define CS_MCLK_SRC_BITPOS 0x00 -#define CS_SMCLK_SRC_BITPOS 0x04 -#define CS_HSMCLK_SRC_BITPOS 0x04 - -/* REFO Clock Values */ -#define CS_REFO_32KHZ 0x00 -#define CS_REFO_128KHZ 0x01 - -/* Frequency Values */ -#define CS_VLOCLK_FREQUENCY 10000 -#define CS_MODCLK_FREQUENCY 24000000 - -/* Interrupts */ -#define CS_LFXT_FAULT CS_IE_LFXTIE -#define CS_HFXT_FAULT CS_IE_HFXTIE -#define CS_DCO_OPEN_FAULT CS_IE_DCOR_OPNIE -#define CS_STARTCOUNT_LFXT_FAULT CS_IE_FCNTLFIE -#define CS_STARTCOUNT_HFXT_FAULT CS_IE_FCNTHFIE -#define CS_DCO_SHORT_FAULT CS_IFG_DCOR_SHTIFG - -#define CS_HFXT_DRIVE CS_CTL2_HFXTDRIVE -#define CS_HFXT_BYPASS CS_CTL2_HFXTBYPASS - -#define CS_LFXT_DRIVE0 CS_CTL2_LFXTDRIVE_0 -#define CS_LFXT_DRIVE1 CS_CTL2_LFXTDRIVE_1 -#define CS_LFXT_DRIVE2 CS_CTL2_LFXTDRIVE_2 -#define CS_LFXT_DRIVE3 CS_CTL2_LFXTDRIVE_3 -#define CS_LFXT_BYPASS CS_CTL2_LFXTBYPASS - -#define CS_ACLK CS_CLKEN_ACLK_EN -#define CS_MCLK CS_CLKEN_MCLK_EN -#define CS_SMCLK CS_CLKEN_SMCLK_EN -#define CS_HSMCLK CS_CLKEN_HSMCLK_EN -#define CS_BCLK CS_STAT_BCLK_READY - -#define CS_LFXTCLK 0x01 - -#define CS_1MHZ 1000000 -#define CS_15MHZ 1500000 -#define CS_3MHZ 3000000 -#define CS_4MHZ 4000000 -#define CS_6MHZ 6000000 -#define CS_8MHZ 8000000 -#define CS_12MHZ 12000000 -#define CS_16MHZ 16000000 -#define CS_24MHZ 24000000 -#define CS_32MHZ 32000000 -#define CS_40MHZ 40000000 -#define CS_48MHZ 48000000 - -#define CS_DCO_FREQUENCY_1_5 CS_CTL0_DCORSEL_0 -#define CS_DCO_FREQUENCY_3 CS_CTL0_DCORSEL_1 -#define CS_DCO_FREQUENCY_6 CS_CTL0_DCORSEL_2 -#define CS_DCO_FREQUENCY_12 CS_CTL0_DCORSEL_3 -#define CS_DCO_FREQUENCY_24 CS_CTL0_DCORSEL_4 -#define CS_DCO_FREQUENCY_48 CS_CTL0_DCORSEL_5 - -#define CS_HFXT_FAULT_COUNTER 0x01 -#define CS_LFXT_FAULT_COUNTER 0x02 - -#define CS_FAULT_COUNTER_4096_CYCLES CS_CTL3_FCNTLF_0 -#define CS_FAULT_COUNTER_8192_CYCLES CS_CTL3_FCNTLF_1 -#define CS_FAULT_COUNTER_16384_CYCLES CS_CTL3_FCNTLF_2 -#define CS_FAULT_COUNTER_32768_CYCLES CS_CTL3_FCNTLF_3 - -#define CS_OVER32MHZ 0x01 -#define CS_UNDER32MHZ 0x02 - -//****************************************************************************** -// -//! This function sets the external clock sources LFXT and HFXT crystal -//! oscillator frequency values. This function must be called if an external -//! crystal LFXT or HFXT is used and the user intends to call -//! CS_getSMCLK, CS_getMCLK, CS_getBCLK, CS_getHSMCLK, CS_getACLK and -//! any of the HFXT oscillator control functions -//! -//! \param lfxt_XT_CLK_frequency is the LFXT crystal frequencies in Hz -//! \param hfxt_XT_CLK_frequency is the HFXT crystal frequencies in Hz -//! -//! \return None -// -//****************************************************************************** -extern void CS_setExternalClockSourceFrequency(uint32_t lfxt_XT_CLK_frequency, - uint32_t hfxt_XT_CLK_frequency); - -//****************************************************************************** -// -//! This function initializes each of the clock signals. The user must ensure -//! that this function is called for each clock signal. If not, the default -//! state is assumed for the particular clock signal. Refer to DriverLib -//! documentation for CS module or Device Family User's Guide for details of -//! default clock signal states. -//! -//! Note that this function is blocking and will wait on the appropriate bit -//! to be set in the CSSTAT READY register to be set before setting the clock -//! source. -//! -//! Also note that when HSMCLK and SMCLK share the same clock signal. If you -//! change the clock signal for HSMCLK, the clock signal for SMCLK will change -//! also (and vice-versa). -//! -//! HFXTCLK is not available for BCLK or ACLK. -//! -//! \param selectedClockSignal Clock signal to initialize. -//! - \b CS_ACLK, -//! - \b CS_MCLK, -//! - \b CS_HSMCLK -//! - \b CS_SMCLK -//! - \b CS_BCLK [clockSourceDivider is ignored for this parameter] -//! \param clockSource Clock source for the selectedClockSignal signal. -//! - \b CS_LFXTCLK_SELECT, -//! - \b CS_HFXTCLK_SELECT, -//! - \b CS_VLOCLK_SELECT, [Not available for BCLK] -//! - \b CS_DCOCLK_SELECT, [Not available for ACLK, BCLK] -//! - \b CS_REFOCLK_SELECT, -//! - \b CS_MODOSC_SELECT [Not available for ACLK, BCLK] -//! \param clockSourceDivider - selected the clock divider to calculate -//! clock signal from clock source. This parameter is ignored when -//! setting BLCK. Valid values are: -//! - \b CS_CLOCK_DIVIDER_1, -//! - \b CS_CLOCK_DIVIDER_2, -//! - \b CS_CLOCK_DIVIDER_4, -//! - \b CS_CLOCK_DIVIDER_8, -//! - \b CS_CLOCK_DIVIDER_16, -//! - \b CS_CLOCK_DIVIDER_32, -//! - \b CS_CLOCK_DIVIDER_64, -//! - \b CS_CLOCK_DIVIDER_128 -//! -//! \return NONE -// -//****************************************************************************** -extern void CS_initClockSignal(uint32_t selectedClockSignal, - uint32_t clockSource, uint32_t clockSourceDivider); - -//****************************************************************************** -// -//! Initializes the HFXT crystal oscillator, which supports crystal frequencies -//! between 0 MHz and 48 MHz, depending on the selected drive strength. Loops -//! until all oscillator fault flags are cleared, with no timeout. See the -//! device-specific data sheet for appropriate drive settings. NOTE: User must -//! call CS_setExternalClockSourceFrequency to set frequency of external clocks -//! before calling this function. -//! -//! \param bypassMode When this variable is set, the oscillator will start -//! in bypass mode and the signal can be generated by a digital square wave. -//! -//! \return true if started correctly, false otherwise -// -//****************************************************************************** -extern bool CS_startHFXT(bool bypassMode); - -//****************************************************************************** -// -//! Initializes the HFXT crystal oscillator, which supports crystal frequencies -//! between 0 MHz and 48 MHz, depending on the selected drive strength. Loops -//! until all oscillator fault flags are cleared, with no timeout. See the -//! device-specific data sheet for appropriate drive settings. NOTE: User must -//! call CS_setExternalClockSourceFrequency to set frequency of external clocks -//! before calling this function. This function has a timeout associated with -//! stabilizing the oscillator. -//! -//! \param bypassMode When this variable is set, the oscillator will start -//! in bypass mode and the signal can be generated by a digital square wave. -//! -//! \param timeout is the count value that gets decremented every time the loop -//! that clears oscillator fault flags gets executed. -//! -//! \return true if started correctly, false otherwise -// -//****************************************************************************** -extern bool CS_startHFXTWithTimeout(bool bypassMode, uint32_t timeout); - -//****************************************************************************** -// -//! Initializes the LFXT crystal oscillator, which supports crystal frequencies -//! up to 50kHz, depending on the selected drive strength. Loops -//! until all oscillator fault flags are cleared, with no timeout. See the -//! device-specific data sheet for appropriate drive settings. NOTE: User must -//! call CS_setExternalClockSourceFrequency to set frequency of external clocks -//! before calling this function. -//! -//! \param xtDrive is the target drive strength for the LFXT crystal -//! oscillator. -//! Valid values are: -//! - \b CS_LFXT_DRIVE0, -//! - \b CS_LFXT_DRIVE1, -//! - \b CS_LFXT_DRIVE2, -//! - \b CS_LFXT_DRIVE3, [Default Value] -//! - \b CS_LFXT_BYPASS -//! -//! \note When CS_LFXT_BYPASS is passed as a parameter the oscillator will start -//! in bypass mode and the signal can be generated by a digital square wave. -//! -//! \return true if started correctly, false otherwise -// -//****************************************************************************** -extern bool CS_startLFXT(uint32_t xtDrive); - -//****************************************************************************** -// -//! Initializes the LFXT crystal oscillator, which supports crystal frequencies -//! up to 50kHz, depending on the selected drive strength. Loops -//! until all oscillator fault flags are cleared. See the -//! device-specific data sheet for appropriate drive settings. NOTE: User must -//! call CS_setExternalClockSourceFrequency to set frequency of external clocks -//! before calling this function. This function has a timeout associated with -//! stabilizing the oscillator. -//! -//! \param xtDrive is the target drive strength for the LFXT crystal -//! oscillator. -//! Valid values are: -//! - \b CS_LFXT_DRIVE0, -//! - \b CS_LFXT_DRIVE1, -//! - \b CS_LFXT_DRIVE2, -//! - \b CS_LFXT_DRIVE3, [Default Value] -//! - \b CS_LFXT_BYPASS -//! -//! \note When CS_LFXT_BYPASS is passed as a parameter the oscillator will -//! start in bypass mode and the signal can be generated by a digital square -//! wave. -//! -//! \param timeout is the count value that gets decremented every time the loop -//! that clears oscillator fault flags gets executed. -//! -//! \return true if started correctly, false otherwise -// -//****************************************************************************** -extern bool CS_startLFXTWithTimeout(uint32_t xtDrive, uint32_t timeout); - -//****************************************************************************** -// -//! Selects between the frequency of the internal REFO clock source -//! -//! \param referenceFrequency selects between the valid frequencies: -//! - \b CS_REFO_32KHZ, -//! - \b CS_REFO_128KHZ, -//! -//! \return NONE -// -//****************************************************************************** -extern void CS_setReferenceOscillatorFrequency(uint8_t referenceFrequency); - -//****************************************************************************** -// -//! Enables conditional module requests -//! -//! \param selectClock selects specific request enables. Valid values are -//! are a logical OR of the following values: -//! - \b CS_ACLK, -//! - \b CS_HSMCLK, -//! - \b CS_SMCLK, -//! - \b CS_MCLK -//! -//! \return NONE -// -//****************************************************************************** -extern void CS_enableClockRequest(uint32_t selectClock); - -//****************************************************************************** -// -//! Disables conditional module requests -//! -//! \param selectClock selects specific request disables. Valid values are -//! are a logical OR of the following values: -//! - \b CS_ACLK, -//! - \b CS_HSMCLK, -//! - \b CS_SMCLK, -//! - \b CS_MCLK -//! -//! \return NONE -// -//****************************************************************************** -extern void CS_disableClockRequest(uint32_t selectClock); - -//****************************************************************************** -// -//! Get the current ACLK frequency. -//! -//! If a oscillator fault is set, the frequency returned will be based on the -//! fail safe mechanism of CS module. The user of this API must ensure that -//! \link CS_setExternalClockSourceFrequency() \endlink API was invoked before -//! in case LFXT is being used. -//! -//! \return Current ACLK frequency in Hz -// -//****************************************************************************** -extern uint32_t CS_getACLK(void); - -//****************************************************************************** -// -//! Get the current SMCLK frequency. -//! -//! If a oscillator fault is set, the frequency returned will be based on the -//! fail safe mechanism of CS module. The user of this API must ensure that -//! CS_setExternalClockSourceFrequency API was invoked before in case LFXT or -//! HFXT is being used. -//! -//! \return Current SMCLK frequency in Hz -// -//****************************************************************************** -extern uint32_t CS_getSMCLK(void); - -//****************************************************************************** -// -//! Get the current MCLK frequency. -//! -//! If a oscillator fault is set, the frequency returned will be based on the -//! fail safe mechanism of CS module. The user of this API must ensure that -//! CS_setExternalClockSourceFrequency API was invoked before in case LFXT or -//! HFXT is being used. -//! -//! \return Current MCLK frequency in Hz -// -//****************************************************************************** -extern uint32_t CS_getMCLK(void); - -//****************************************************************************** -// -//! Get the current BCLK frequency. -//! -//! If a oscillator fault is set, the frequency returned will be based on the -//! fail safe mechanism of CS module. The user of this API must ensure that -//! \link CS_setExternalClockSourceFrequency \endlink API was invoked before in -//! case LFXT or HFXT is being used. -//! -//! \return Current BCLK frequency in Hz -// -//****************************************************************************** -extern uint32_t CS_getBCLK(void); - -//****************************************************************************** -// -//! Get the current HSMCLK frequency. -//! -//! If a oscillator fault is set, the frequency returned will be based on the -//! fail safe mechanism of CS module. The user of this API must ensure that -//! \link CS_setExternalClockSourceFrequency \endlink API was invoked before in -//! case LFXT or HFXT is being used. -//! -//! \return Current HSMCLK frequency in Hz -// -//****************************************************************************** -extern uint32_t CS_getHSMCLK(void); - -//****************************************************************************** -// -//! Sets the centered frequency of DCO operation. Each frequency represents -//! the centred frequency of a particular frequency range. Further tuning can -//! be achieved by using the CS_tuneDCOFrequency function. Note that setting -//! the nominal frequency will reset the tuning parameters. -//! -//! \param dcoFreq selects between the valid frequencies: -//! - \b CS_DCO_FREQUENCY_1_5, [1MHz to 2MHz] -//! - \b CS_DCO_FREQUENCY_3, [2MHz to 4MHz] -//! - \b CS_DCO_FREQUENCY_6, [4MHz to 8MHz] -//! - \b CS_DCO_FREQUENCY_12, [8MHz to 16MHz] -//! - \b CS_DCO_FREQUENCY_24, [16MHz to 32MHz] -//! - \b CS_DCO_FREQUENCY_48 [32MHz to 64MHz] -//! -//! \return NONE -// -//****************************************************************************** -extern void CS_setDCOCenteredFrequency(uint32_t dcoFreq); - -//****************************************************************************** -// -//! Automatically sets/tunes the DCO to the given frequency. Any valid value -//! up to max frequency in the spec can be given to this function and the API -//! will do its best to determine the correct tuning parameter. -//! -//! \note The frequency ranges that can be custom tuned on early release MSP432 -//! devices is limited. For further details on supported tunable frequencies, -//! please refer to the device errata sheet or data sheet. -//! -//! \param dcoFrequency Frequency in Hz that the user wants to set the DCO to. -//! -//! \note This function uses floating point math to calculate the DCO tuning -//! parameter. If efficiency is a concern, the user should use the -//! \link FPU_enableModule \endlink function (if available) to enable -//! the floating point co-processor. -//! -//! \return None -// -//****************************************************************************** -extern void CS_setDCOFrequency(uint32_t dcoFrequency); - -//****************************************************************************** -// -//! Tunes the DCO to a specific frequency. Tuning of the DCO is based off of the -//! following equation in the user's guide: -//! -//! See the user's guide for more detailed information about DCO tuning. -//! -//! \note This function is not currently available on pre-release MSP432 devices. -//! On early release versions of MSP432, the DCO calibration information has not been -//! populated making the DCO only able to operate at the pre-calibrated centered -//! frequencies accessible by the \link CS_setDCOCenteredFrequency \endlink -//! function. While this function will be added on the final devices being released, -//! for early silicon please default to the pre-calibrated DCO center frequencies. -//! -//! \param tuneParameter Tuning parameter in 2's Compliment representation. -//! Can be negative or positive. -//! -//! \return NONE -// -//****************************************************************************** -extern void CS_tuneDCOFrequency(int16_t tuneParameter); - -//****************************************************************************** -// -//! Enables the external resistor for DCO operation -//! -//! \return NONE -// -//****************************************************************************** -extern void CS_enableDCOExternalResistor(void); - -//****************************************************************************** -// -//! Disables the external resistor for DCO operation -//! -//! \return NONE -// -//****************************************************************************** -extern void CS_disableDCOExternalResistor(void); - -//****************************************************************************** -// -//! Sets the calibration value for the DCO when using the external resistor -//! mode. This value is used for tuning the DCO to custom frequencies. By -//! default, the value in the CS module is populated by the calibration -//! data of the suggested external resistor (see device datasheet). -//! -//! \param calData is the calibration data constant for the external resistor. -//! -//! \param freqRange is the range of the DCO to set the external calibration -//! for. Frequencies above 32MHZ have a different calibration value -//! than frequencies below 32MHZ. -//! -//! \return None -// -//****************************************************************************** -extern void CS_setDCOExternalResistorCalibration(uint_fast8_t uiCalData, - uint_fast8_t freqRange); - -//****************************************************************************** -// -//! Gets the current tuned DCO frequency. If no tuning has been done, this -//! returns the nominal DCO frequency of the current DCO range. Note that this -//! function will grab any constant/calibration data from the DDDS table -//! without any user interaction needed. -//! -//! \note This function uses floating point math to calculate the DCO tuning -//! parameter. If efficiency is a concern, the user should use the -//! \link FPU_enableModule \endlink function (if available) to enable -//! the floating point co-processor. -//! -//! \return Current DCO frequency in Hz -// -//****************************************************************************** -extern uint32_t CS_getDCOFrequency(void); - -//****************************************************************************** -// -//! Automatically sets/tunes the DCO to the given frequency. Any valid value -//! up to (and including) 64Mhz can be given to this function and the API -//! will do its best to determine the correct tuning parameter. -//! -//! -//! \note This function is not currently available on pre-release MSP432 devices. -//! On early release versions of MSP432, the DCO calibration information has not been -//! populated making the DCO only able to operate at the pre-calibrated centered -//! frequencies accessible by the \link CS_setDCOCenteredFrequency \endlink -//! function. While this function will be added on the final devices being released, -//! for early silicon please default to the pre-calibrated DCO center frequencies. -//! -//! \param dcoFrequency Frequency in Hz (1500000 - 64000000) that the user wants -//! to set the DCO to. -//! -//! \note This function uses floating point math to calculate the DCO tuning -//! parameter. If efficiency is a concern, the user should use the -//! \link FPU_enableModule \endlink function (if available) to enable -//! the floating point co-processor. -//! -//! \return None -// -//****************************************************************************** -extern void CS_setDCOFrequency(uint32_t dcoFrequency); - -//****************************************************************************** -// -//! Enables the fault counter for the CS module. This function can enable -//! either the HFXT fault counter or the LFXT fault counter. -//! -//! \param counterSelect selects the fault counter to enable -//! - \b CS_HFXT_FAULT_COUNTER -//! - \b CS_LFXT_FAULT_COUNTER -//! -//! \return NONE -// -//****************************************************************************** -extern void CS_enableFaultCounter(uint_fast8_t counterSelect); - -//****************************************************************************** -// -//! Disables the fault counter for the CS module. This function can disable -//! either the HFXT fault counter or the LFXT fault counter. -//! -//! \param counterSelect selects the fault counter to disable -//! - \b CS_HFXT_FAULT_COUNTER -//! - \b CS_LFXT_FAULT_COUNTER -//! -//! \return NONE -// -//****************************************************************************** -extern void CS_disableFaultCounter(uint_fast8_t counterSelect); - -//****************************************************************************** -// -//! Resets the fault counter for the CS module. This function can reset -//! either the HFXT fault counter or the LFXT fault counter. -//! -//! \param counterSelect selects the fault counter to reset -//! - \b CS_HFXT_FAULT_COUNTER -//! - \b CS_LFXT_FAULT_COUNTER -//! -//! \return NONE -// -//****************************************************************************** -extern void CS_resetFaultCounter(uint_fast8_t counterSelect); - -//****************************************************************************** -// -//! Sets the count for the start value of the fault counter. This function can -//! be used to set either the HFXT count or the LFXT count. -//! -//! \param counterSelect selects the fault counter to reset -//! - \b CS_HFXT_FAULT_COUNTER -//! - \b CS_LFXT_FAULT_COUNTER -//! \param countValue selects the cycles to set the fault counter to -//! - \b CS_FAULT_COUNTER_4096_CYCLES -//! - \b CS_FAULT_COUNTER_8192_CYCLES -//! - \b CS_FAULT_COUNTER_16384_CYCLES -//! - \b CS_FAULT_COUNTER_32768_CYCLES -//! -//! \return NONE -// -//****************************************************************************** -extern void CS_startFaultCounter(uint_fast8_t counterSelect, - uint_fast8_t countValue); - -//***************************************************************************** -// -//! Enables individual clock control interrupt sources. -//! -//! \param flags is a bit mask of the interrupt sources to be enabled. Must -//! be a logical OR of: -//! - \b CS_LFXT_FAULT, -//! - \b CS_HFXT_FAULT, -//! - \b CS_DCOMIN_FAULT, -//! - \b CS_DCOMAX_FAULT, -//! - \b CS_DCO_OPEN_FAULT, -//! - \b CS_STARTCOUNT_LFXT_FAULT, -//! - \b CS_STARTCOUNT_HFXT_FAULT, -//! -//! This function enables the indicated clock system interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -extern void CS_enableInterrupt(uint32_t flags); - -//***************************************************************************** -// -//! Disables individual clock system interrupt sources. -//! -//! \param flags is a bit mask of the interrupt sources to be disabled. Must -//! be a logical OR of: -//! - \b CS_LFXT_FAULT, -//! - \b CS_HFXT_FAULT, -//! - \b CS_DCOMIN_FAULT, -//! - \b CS_DCOMAX_FAULT, -//! - \b CS_DCO_OPEN_FAULT, -//! - \b CS_STARTCOUNT_LFXT_FAULT, -//! - \b CS_STARTCOUNT_HFXT_FAULT, -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -extern void CS_disableInterrupt(uint32_t flags); - -//***************************************************************************** -// -//! Gets the current interrupt status masked with the enabled interrupts. -//! This function is useful to call in ISRs to get a list of pending interrupts -//! that are actually enabled and could have caused the ISR. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! - \b CS_LFXT_FAULT, -//! - \b CS_HFXT_FAULT, -//! - \b CS_DCO_OPEN_FAULT, -//! - \b CS_DCO_SHORT_FAULT, -//! - \b CS_STARTCOUNT_LFXT_FAULT, -//! - \b CS_STARTCOUNT_HFXT_FAULT, -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -// -//***************************************************************************** -extern uint32_t CS_getEnabledInterruptStatus(void); - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \return The current interrupt status, enumerated as a bit field of: -//! - \b CS_LFXT_FAULT, -//! - \b CS_HFXT_FAULT, -//! - \b CS_DCO_OPEN_FAULT, -//! - \b CS_DCO_SHORT_FAULT, -//! - \b CS_STARTCOUNT_LFXT_FAULT, -//! - \b CS_STARTCOUNT_HFXT_FAULT, -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -// -//***************************************************************************** -extern uint32_t CS_getInterruptStatus(void); - -//***************************************************************************** -// -//! Clears clock system interrupt sources. -//! -//! \param flags is a bit mask of the interrupt sources to be cleared. Must -//! be a logical OR of: -//! - \b CS_LFXT_FAULT, -//! - \b CS_HFXT_FAULT, -//! - \b CS_DCO_OPEN_FAULT, -//! - \b CS_STARTCOUNT_LFXT_FAULT, -//! - \b CS_STARTCOUNT_HFXT_FAULT, -//! -//! The specified clock system interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep it from being called again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -extern void CS_clearInterruptFlag(uint32_t flags); - -//***************************************************************************** -// -//! Registers an interrupt handler for the clock system interrupt. -//! -//! \param intHandler is a pointer to the function to be called when the clock -//! system interrupt occurs. -//! -//! This function registers the handler to be called when a clock system -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific clock system interrupts must be enabled -//! via CS_enableInterrupt(). It is the interrupt handler's responsibility to -//! clear the interrupt source via CS_clearInterruptFlag(). -//! -//! Clock System can generate interrupts when -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void CS_registerInterrupt(void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the clock system. -//! -//! This function unregisters the handler to be called when a clock system -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void CS_unregisterInterrupt(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/debug.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/debug.h deleted file mode 100644 index 69e370c4ae1..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/debug.h +++ /dev/null @@ -1,71 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __DEBUG_H__ -#define __DEBUG_H__ - -//***************************************************************************** -// -// Prototype for the function that is called when an invalid argument is passed -// to an API. This is only used when doing a DEBUG build. -// -//***************************************************************************** -extern void __error__(char *pcFilename, unsigned long line); - -//***************************************************************************** -// -// The ASSERT macro, which does the actual assertion checking. Typically, this -// will be for procedure arguments. -// -//***************************************************************************** -#ifdef DEBUG -#define ASSERT(expr) { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } -#else -#define ASSERT(expr) -#endif - -#ifdef DEBUG -#define assert(expr) { \ - if(!(expr)) \ - { \ - __error__(__FILE__, __LINE__); \ - } \ - } -#else -#define assert(expr) -#endif - -#endif // __DEBUG_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/dma.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/dma.c deleted file mode 100644 index 716fa1e5a56..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/dma.c +++ /dev/null @@ -1,845 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include - -#include -#include -#include - -void DMA_enableModule(void) -{ - // - // Set the master enable bit in the config register. - // - DMA_Control->CFG = DMA_CFG_MASTEN; -} - -void DMA_disableModule(void) -{ - // - // Clear the master enable bit in the config register. - // - DMA_Control->CFG = 0; -} - -uint32_t DMA_getErrorStatus(void) -{ - // - // Return the DMA error status. - // - return DMA_Control->ERRCLR; -} - -void DMA_clearErrorStatus(void) -{ - // - // Clear the DMA error interrupt. - // - DMA_Control->ERRCLR = 1; -} - -void DMA_enableChannel(uint32_t channelNum) -{ - // - // Check the arguments. - // - ASSERT((channelNum & 0xffff) < 8); - - // - // Set the bit for this channel in the enable set register. - // - DMA_Control->ENASET = 1 << (channelNum & 0x0F); -} - -void DMA_disableChannel(uint32_t channelNum) -{ - // - // Check the arguments. - // - ASSERT((channelNum & 0xffff) < 8); - - // - // Set the bit for this channel in the enable clear register. - // - DMA_Control->ENACLR = 1 << (channelNum & 0x0F); -} - -bool DMA_isChannelEnabled(uint32_t channelNum) -{ - // - // Check the arguments. - // - ASSERT((channelNum & 0xffff) < 8); - - // - // AND the specified channel bit with the enable register and return the - // result. - // - return ((DMA_Control->ENASET & (1 << (channelNum & 0x0F))) ? true : false); -} - -void DMA_setControlBase(void *controlTable) -{ - // - // Check the arguments. - // - ASSERT(((uint32_t) controlTable & ~0x3FF) == (uint32_t) controlTable); - ASSERT((uint32_t) controlTable >= 0x20000000); - - // - // Program the base address into the register. - // - DMA_Control->CTLBASE = (uint32_t) controlTable; -} - -void* DMA_getControlBase(void) -{ - // - // Read the current value of the control base register and return it to - // the caller. - // - return ((void *) DMA_Control->CTLBASE); -} - -void* DMA_getControlAlternateBase(void) -{ - // - // Read the current value of the control base register and return it to - // the caller. - // - return ((void *) DMA_Control->ALTBASE); -} - -void DMA_requestChannel(uint32_t channelNum) -{ - // - // Check the arguments. - // - ASSERT((channelNum & 0xffff) < 8); - - // - // Set the bit for this channel in the software DMA request register. - // - DMA_Control->SWREQ = 1 << (channelNum & 0x0F); -} - -void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr) -{ - // - // Check the arguments. - // - ASSERT((channelNum & 0xffff) < 8); - ASSERT( - (attr - & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT - | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) - == 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the channelNum parameter, extract just the channel number - // from this parameter. - // - channelNum &= 0x0F; - - // - // Set the useburst bit for this channel if set in config. - // - if (attr & UDMA_ATTR_USEBURST) - { - DMA_Control->USEBURSTSET = 1 << channelNum; - } - - // - // Set the alternate control select bit for this channel, - // if set in config. - // - if (attr & UDMA_ATTR_ALTSELECT) - { - DMA_Control->ALTSET = 1 << channelNum; - } - - // - // Set the high priority bit for this channel, if set in config. - // - if (attr & UDMA_ATTR_HIGH_PRIORITY) - { - DMA_Control->PRIOSET = 1 << channelNum; - } - - // - // Set the request mask bit for this channel, if set in config. - // - if (attr & UDMA_ATTR_REQMASK) - { - DMA_Control->REQMASKSET = 1 << channelNum; - } -} - -void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr) -{ - // - // Check the arguments. - // - ASSERT((channelNum & 0xffff) < 8); - ASSERT( - (attr - & ~(UDMA_ATTR_USEBURST | UDMA_ATTR_ALTSELECT - | UDMA_ATTR_HIGH_PRIORITY | UDMA_ATTR_REQMASK)) - == 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the channelNum parameter, extract just the channel number - // from this parameter. - // - channelNum &= 0x0F; - - // - // Clear the useburst bit for this channel if set in config. - // - if (attr & UDMA_ATTR_USEBURST) - { - DMA_Control->USEBURSTCLR = 1 << channelNum; - } - - // - // Clear the alternate control select bit for this channel, if set in - // config. - // - if (attr & UDMA_ATTR_ALTSELECT) - { - DMA_Control->ALTCLR = 1 << channelNum; - } - - // - // Clear the high priority bit for this channel, if set in config. - // - if (attr & UDMA_ATTR_HIGH_PRIORITY) - { - DMA_Control->PRIOCLR = 1 << channelNum; - } - - // - // Clear the request mask bit for this channel, if set in config. - // - if (attr & UDMA_ATTR_REQMASK) - { - DMA_Control->REQMASKCLR = 1 << channelNum; - } -} - -uint32_t DMA_getChannelAttribute(uint32_t channelNum) -{ - uint32_t attr = 0; - - // - // Check the arguments. - // - ASSERT((channelNum & 0xffff) < 8); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the channelNum parameter, extract just the channel number - // from this parameter. - // - channelNum &= 0x0F; - - // - // Check to see if useburst bit is set for this channel. - // - if (DMA_Control->USEBURSTSET & (1 << channelNum)) - { - attr |= UDMA_ATTR_USEBURST; - } - - // - // Check to see if the alternate control bit is set for this channel. - // - if (DMA_Control->ALTSET & (1 << channelNum)) - { - attr |= UDMA_ATTR_ALTSELECT; - } - - // - // Check to see if the high priority bit is set for this channel. - // - if (DMA_Control->PRIOSET & (1 << channelNum)) - { - attr |= UDMA_ATTR_HIGH_PRIORITY; - } - - // - // Check to see if the request mask bit is set for this channel. - // - if (DMA_Control->REQMASKSET & (1 << channelNum)) - { - attr |= UDMA_ATTR_REQMASK; - } - - // - // Return the configuration flags. - // - return (attr); -} - -void DMA_setChannelControl(uint32_t channelStructIndex, uint32_t control) -{ - DMA_ControlTable *pCtl; - - // - // Check the arguments. - // - ASSERT((channelStructIndex & 0xffff) < 64); - ASSERT(DMA_Control->CTLBASE != 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the channelStructIndex parameter, extract just the channel - // index from this parameter. - // - channelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - pCtl = (DMA_ControlTable *) DMA_Control->CTLBASE; - - // - // Get the current control word value and mask off the fields to be - // changed, then OR in the new settings. - // - pCtl[channelStructIndex].control = ((pCtl[channelStructIndex].control - & ~(UDMA_CHCTL_DSTINC_M | UDMA_CHCTL_DSTSIZE_M | UDMA_CHCTL_SRCINC_M - | UDMA_CHCTL_SRCSIZE_M | UDMA_CHCTL_ARBSIZE_M - | UDMA_CHCTL_NXTUSEBURST)) | control); -} - -void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode, - void *srcAddr, void *dstAddr, uint32_t transferSize) -{ - DMA_ControlTable *controlTable; - uint32_t control; - uint32_t increment; - uint32_t bufferBytes; - - // - // Check the arguments. - // - ASSERT((channelStructIndex & 0xffff) < 64); - ASSERT(DMA->CTLBASE != 0); - ASSERT(mode <= UDMA_MODE_PER_SCATTER_GATHER); - ASSERT((transferSize != 0) && (transferSize <= 1024)); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the channelStructIndex parameter, extract just the channel - // index from this parameter. - // - channelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE; - - // - // Get the current control word value and mask off the mode and size - // fields. - // - control = (controlTable[channelStructIndex].control - & ~(UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); - - // - // Adjust the mode if the alt control structure is selected. - // - if (channelStructIndex & UDMA_ALT_SELECT) - { - if ((mode == UDMA_MODE_MEM_SCATTER_GATHER) - || (mode == UDMA_MODE_PER_SCATTER_GATHER)) - { - mode |= UDMA_MODE_ALT_SELECT; - } - } - - // - // Set the transfer size and mode in the control word (but don't write the - // control word yet as it could kick off a transfer). - // - control |= mode | ((transferSize - 1) << 4); - - // - // Get the address increment value for the source, from the control word. - // - increment = (control & UDMA_CHCTL_SRCINC_M); - - // - // Compute the ending source address of the transfer. If the source - // increment is set to none, then the ending address is the same as the - // beginning. - // - if (increment != UDMA_SRC_INC_NONE) - { - increment = increment >> 26; - bufferBytes = transferSize << increment; - srcAddr = (void *) ((uint32_t) srcAddr + bufferBytes - 1); - } - - // - // Load the source ending address into the control block. - // - controlTable[channelStructIndex].srcEndAddr = srcAddr; - - // - // Get the address increment value for the destination, from the control - // word. - // - increment = control & UDMA_CHCTL_DSTINC_M; - - // - // Compute the ending destination address of the transfer. If the - // destination increment is set to none, then the ending address is the - // same as the beginning. - // - if (increment != UDMA_DST_INC_NONE) - { - // - // There is a special case if this is setting up a scatter-gather - // transfer. The destination pointer must point to the end of - // the alternate structure for this channel instead of calculating - // the end of the buffer in the normal way. - // - if ((mode == UDMA_MODE_MEM_SCATTER_GATHER) - || (mode == UDMA_MODE_PER_SCATTER_GATHER)) - { - dstAddr = (void *) &controlTable[channelStructIndex - | UDMA_ALT_SELECT].spare; - } - // - // Not a scatter-gather transfer, calculate end pointer normally. - // - else - { - increment = increment >> 30; - bufferBytes = transferSize << increment; - dstAddr = (void *) ((uint32_t) dstAddr + bufferBytes - 1); - } - } - - // - // Load the destination ending address into the control block. - // - controlTable[channelStructIndex].dstEndAddr = dstAddr; - - // - // Write the new control word value. - // - controlTable[channelStructIndex].control = control; -} - -void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount, - void *taskList, uint32_t isPeriphSG) -{ - DMA_ControlTable *controlTable; - DMA_ControlTable *pTaskTable; - - // - // Check the parameters - // - ASSERT((channelNum & 0xffff) < 8); - ASSERT(DMA->CTLBASE != 0); - ASSERT(taskList != 0); - ASSERT(taskCount <= 1024); - ASSERT(taskCount != 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the channelNum parameter, extract just the channel number - // from this parameter. - // - channelNum &= 0x0F; - - // - // Get the base address of the control table. - // - controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE; - - // - // Get a handy pointer to the task list - // - pTaskTable = (DMA_ControlTable *) taskList; - - // - // Compute the ending address for the source pointer. This address is the - // last element of the last task in the task table - // - controlTable[channelNum].srcEndAddr = &pTaskTable[taskCount - 1].spare; - - // - // Compute the ending address for the destination pointer. This address - // is the end of the alternate structure for this channel. - // - controlTable[channelNum].dstEndAddr = &controlTable[channelNum - | UDMA_ALT_SELECT].spare; - - // - // Compute the control word. Most configurable items are fixed for - // scatter-gather. Item and increment sizes are all 32-bit and arb - // size must be 4. The count is the number of items in the task list - // times 4 (4 words per task). - // - controlTable[channelNum].control = (UDMA_CHCTL_DSTINC_32 - | UDMA_CHCTL_DSTSIZE_32 | UDMA_CHCTL_SRCINC_32 - | UDMA_CHCTL_SRCSIZE_32 | UDMA_CHCTL_ARBSIZE_4 - | (((taskCount * 4) - 1) << UDMA_CHCTL_XFERSIZE_S) - | (isPeriphSG ? - UDMA_CHCTL_XFERMODE_PER_SG : - UDMA_CHCTL_XFERMODE_MEM_SG)); - - // - // Scatter-gather operations can leave the alt bit set. So if doing - // back to back scatter-gather transfers, the second attempt may not - // work correctly because the alt bit is set. Therefore, clear the - // alt bit here to ensure that it is always cleared before a new SG - // transfer is started. - // - DMA_Control->ALTCLR = 1 << channelNum; -} - -uint32_t DMA_getChannelSize(uint32_t channelStructIndex) -{ - DMA_ControlTable *controlTable; - uint32_t control; - - // - // Check the arguments. - // - ASSERT((channelStructIndex & 0xffff) < 16); - ASSERT(DMA->CTLBASE != 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the channelStructIndex parameter, extract just the channel - // index from this parameter. - // - channelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE; - - // - // Get the current control word value and mask off all but the size field - // and the mode field. - // - control = (controlTable[channelStructIndex].control - & (UDMA_CHCTL_XFERSIZE_M | UDMA_CHCTL_XFERMODE_M)); - - // - // If the size field and mode field are 0 then the transfer is finished - // and there are no more items to transfer - // - if (control == 0) - { - return (0); - } - - // - // Otherwise, if either the size field or more field is non-zero, then - // not all the items have been transferred. - // - else - { - // - // Shift the size field and add one, then return to user. - // - return ((control >> 4) + 1); - } -} - -uint32_t DMA_getChannelMode(uint32_t channelStructIndex) -{ - DMA_ControlTable *controlTable; - uint32_t control; - - // - // Check the arguments. - // - ASSERT((channelStructIndex & 0xffff) < 64); - ASSERT(DMA->CTLBASE != 0); - - // - // In case a channel selector macro (like UDMA_CH0_USB0EP1RX) was - // passed as the channelStructIndex parameter, extract just the channel - // index from this parameter. - // - channelStructIndex &= 0x3f; - - // - // Get the base address of the control table. - // - controlTable = (DMA_ControlTable *) DMA_Control->CTLBASE; - - // - // Get the current control word value and mask off all but the mode field. - // - control = - (controlTable[channelStructIndex].control & UDMA_CHCTL_XFERMODE_M); - - // - // Check if scatter/gather mode, and if so, mask off the alt bit. - // - if (((control & ~UDMA_MODE_ALT_SELECT) == UDMA_MODE_MEM_SCATTER_GATHER) - || ((control & ~UDMA_MODE_ALT_SELECT) - == UDMA_MODE_PER_SCATTER_GATHER)) - { - control &= ~UDMA_MODE_ALT_SELECT; - } - - // - // Return the mode to the caller. - // - return (control); -} - -void DMA_assignChannel(uint32_t mapping) -{ - switch (mapping) - { - case DMA_CH0_RESERVED0: - case DMA_CH0_EUSCIA0TX: - case DMA_CH0_EUSCIB0TX0: - case DMA_CH0_EUSCIB3TX1: - case DMA_CH0_EUSCIB2TX2: - case DMA_CH0_EUSCIB1TX3: - case DMA_CH0_TIMERA0CCR0: - case DMA_CH0_AESTRIGGER0: - DMA_Channel->CH_SRCCFG[0] = (mapping >> 24) & 0x1F; - break; - case DMA_CH1_RESERVED0: - case DMA_CH1_EUSCIA0RX: - case DMA_CH1_EUSCIB0RX0: - case DMA_CH1_EUSCIB3RX1: - case DMA_CH1_EUSCIB2RX2: - case DMA_CH1_EUSCIB1RX3: - case DMA_CH1_TIMERA0CCR2: - case DMA_CH1_AESTRIGGER1: - DMA_Channel->CH_SRCCFG[1] = (mapping >> 24) & 0x1F; - break; - case DMA_CH2_RESERVED0: - case DMA_CH2_EUSCIA1TX: - case DMA_CH2_EUSCIB1TX0: - case DMA_CH2_EUSCIB0TX1: - case DMA_CH2_EUSCIB3TX2: - case DMA_CH2_EUSCIB2TX3: - case DMA_CH2_TIMERA1CCR0: - case DMA_CH2_AESTRIGGER2: - DMA_Channel->CH_SRCCFG[2] = (mapping >> 24) & 0x1F; - break; - case DMA_CH3_RESERVED0: - case DMA_CH3_EUSCIA1RX: - case DMA_CH3_EUSCIB1RX0: - case DMA_CH3_EUSCIB0RX1: - case DMA_CH3_EUSCIB3RX2: - case DMA_CH3_EUSCIB2RX3: - case DMA_CH3_TIMERA1CCR2: - case DMA_CH3_RESERVED1: - DMA_Channel->CH_SRCCFG[3] = (mapping >> 24) & 0x1F; - break; - case DMA_CH4_RESERVED0: - case DMA_CH4_EUSCIA2TX: - case DMA_CH4_EUSCIB2TX0: - case DMA_CH4_EUSCIB1TX1: - case DMA_CH4_EUSCIB0TX2: - case DMA_CH4_EUSCIB3TX3: - case DMA_CH4_TIMERA2CCR0: - case DMA_CH4_RESERVED1: - DMA_Channel->CH_SRCCFG[4] = (mapping >> 24) & 0x1F; - break; - case DMA_CH5_RESERVED0: - case DMA_CH5_EUSCIA2RX: - case DMA_CH5_EUSCIB2RX0: - case DMA_CH5_EUSCIB1RX1: - case DMA_CH5_EUSCIB0RX2: - case DMA_CH5_EUSCIB3RX3: - case DMA_CH5_TIMERA2CCR2: - case DMA_CH5_RESERVED1: - DMA_Channel->CH_SRCCFG[5] = (mapping >> 24) & 0x1F; - break; - case DMA_CH6_RESERVED0: - case DMA_CH6_EUSCIA3TX: - case DMA_CH6_EUSCIB3TX0: - case DMA_CH6_EUSCIB2TX1: - case DMA_CH6_EUSCIB1TX2: - case DMA_CH6_EUSCIB0TX3: - case DMA_CH6_TIMERA3CCR0: - case DMA_CH6_EXTERNALPIN: - DMA_Channel->CH_SRCCFG[6] = (mapping >> 24) & 0x1F; - break; - case DMA_CH7_RESERVED0: - case DMA_CH7_EUSCIA3RX: - case DMA_CH7_EUSCIB3RX0: - case DMA_CH7_EUSCIB2RX1: - case DMA_CH7_EUSCIB1RX2: - case DMA_CH7_EUSCIB0RX3: - case DMA_CH7_TIMERA3CCR2: - case DMA_CH7_ADC14: - DMA_Channel->CH_SRCCFG[7] = (mapping >> 24) & 0x1F; - break; - default: - ASSERT(false); - } - -} - -void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel) -{ - ASSERT( - interruptNumber == DMA_INT1 || interruptNumber == DMA_INT2 - || interruptNumber == DMA_INT3); - - if (interruptNumber == DMA_INT1) - { - DMA_Channel->INT1_SRCCFG = (DMA_Channel->INT1_SRCCFG - & ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel; - } else if (interruptNumber == DMA_INT2) - { - DMA_Channel->INT2_SRCCFG = (DMA_Channel->INT2_SRCCFG - & ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel; - } else if (interruptNumber == DMA_INT3) - { - DMA_Channel->INT3_SRCCFG = (DMA_Channel->INT3_SRCCFG - & ~DMA_INT1_SRCCFG_INT_SRC_MASK) | channel; - } - - /* Enabling the assigned interrupt */ - DMA_enableInterrupt(interruptNumber); -} - -void DMA_requestSoftwareTransfer(uint32_t channel) -{ - DMA_Channel->SW_CHTRIG |= (1 << channel); -} - -uint32_t DMA_getInterruptStatus(void) -{ - return DMA_Channel->INT0_SRCFLG; -} - -void DMA_clearInterruptFlag(uint32_t channel) -{ - DMA_Channel->INT0_CLRFLG |= (1 << channel); -} - -void DMA_enableInterrupt(uint32_t interruptNumber) -{ - ASSERT( - (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1) - || (interruptNumber == DMA_INT2) - || (interruptNumber == DMA_INT3)); - - if (interruptNumber == DMA_INT1) - { - DMA_Channel->INT1_SRCCFG |= DMA_INT1_SRCCFG_EN; - } else if (interruptNumber == DMA_INT2) - { - DMA_Channel->INT2_SRCCFG |= DMA_INT2_SRCCFG_EN; - } else if (interruptNumber == DMA_INT3) - { - DMA_Channel->INT3_SRCCFG |= DMA_INT3_SRCCFG_EN; - } - -} - -void DMA_disableInterrupt(uint32_t interruptNumber) -{ - ASSERT( - (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1) - || (interruptNumber == DMA_INT2) - || (interruptNumber == DMA_INT3)); - - if (interruptNumber == DMA_INT1) - { - DMA_Channel->INT1_SRCCFG &= ~DMA_INT1_SRCCFG_EN; - } else if (interruptNumber == DMA_INT2) - { - DMA_Channel->INT2_SRCCFG &= ~DMA_INT2_SRCCFG_EN; - } else if (interruptNumber == DMA_INT3) - { - DMA_Channel->INT3_SRCCFG &= ~DMA_INT3_SRCCFG_EN; - } -} - -void DMA_registerInterrupt(uint32_t interruptNumber, void (*intHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(intHandler); - ASSERT( - (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1) - || (interruptNumber == DMA_INT2) - || (interruptNumber == DMA_INT3) - || (interruptNumber == DMA_INTERR)); - - // - // Register the interrupt handler. - // - Interrupt_registerInterrupt(interruptNumber, intHandler); - - // - // Enable the memory management fault. - // - Interrupt_enableInterrupt(interruptNumber); - -} - -void DMA_unregisterInterrupt(uint32_t interruptNumber) -{ - ASSERT( - (interruptNumber == DMA_INT0) || (interruptNumber == DMA_INT1) - || (interruptNumber == DMA_INT2) - || (interruptNumber == DMA_INT3) - || (interruptNumber == DMA_INTERR)); - - // - // Disable the interrupt. - // - Interrupt_disableInterrupt(interruptNumber); - - // - // Unregister the interrupt handler. - // - Interrupt_unregisterInterrupt(interruptNumber); -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/dma.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/dma.h deleted file mode 100644 index c282cd47dff..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/dma.h +++ /dev/null @@ -1,1002 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __DMA_H__ -#define __DMA_H__ - -//***************************************************************************** -// -//! \addtogroup dma_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include - -//***************************************************************************** -// -// A structure that defines an entry in the channel control table. These -// fields are used by the DMA controller and normally it is not necessary for -// software to directly read or write fields in the table. -// -//***************************************************************************** -typedef struct _DMA_ControlTable -{ - // - // The ending source address of the data transfer. - // - volatile void *srcEndAddr; - - // - // The ending destination address of the data transfer. - // - volatile void *dstEndAddr; - - // - // The channel control mode. - // - volatile uint32_t control; - - // - // An unused location. - // - volatile uint32_t spare; -} DMA_ControlTable; - -//***************************************************************************** -// -//! A helper macro for building scatter-gather task table entries. -//! -//! This macro is intended to be used to help populate a table of DMA tasks -//! for a scatter-gather transfer. This macro will calculate the values for -//! the fields of a task structure entry based on the input parameters. -//! -//! There are specific requirements for the values of each parameter. No -//! checking is done so it is up to the caller to ensure that correct values -//! are used for the parameters. -//! -//! The \b transferCount parameter is the number of items that will be -//! transferred by this task. It must be in the range 1-1024. -//! -//! The \b itemSize parameter is the bit size of the transfer data. It must -//! be one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or \b UDMA_SIZE_32. -//! -//! The \e srcIncrement parameter is the increment size for the source data. -//! It must be one of \b UDMA_SRC_INC_8, \b UDMA_SRC_INC_16, -//! \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE. -//! -//! The \b srcAddr parameter is a void pointer to the beginning of the source -//! data. -//! -//! The \b dstIncrement parameter is the increment size for the destination -//! data. It must be one of \b UDMA_DST_INC_8, \b UDMA_DST_INC_16, -//! \b UDMA_DST_INC_32, or \b UDMA_DST_INC_NONE. -//! -//! The \b dstAddr parameter is a void pointer to the beginning of the -//! location where the data will be transferred. -//! -//! The \b arbSize parameter is the arbitration size for the transfer, and -//! must be one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, and so on -//! up to \b UDMA_ARB_1024. This is used to select the arbitration size in -//! powers of 2, from 1 to 1024. -//! -//! The \e mode parameter is the mode to use for this transfer task. It -//! must be one of \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, -//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. Note -//! that normally all tasks will be one of the scatter-gather modes while the -//! last task is a task list will be AUTO or BASIC. -//! -//! This macro is intended to be used to initialize individual entries of -//! a structure of DMA_ControlTable type, like this: -//! -//! \code{.c} -//! DMA_ControlTable MyTaskList[] = -//! { -//! DMA_TaskStructEntry(Task1Count, UDMA_SIZE_8, -//! UDMA_SRC_INC_8, MySourceBuf, -//! UDMA_DST_INC_8, MyDestBuf, -//! UDMA_ARB_8, UDMA_MODE_MEM_SCATTER_GATHER), -//! DMA_TaskStructEntry(Task2Count, ... ), -//! } -//! \endcode -//! -//! \param transferCount is the count of items to transfer for this task. -//! \param itemSize is the bit size of the items to transfer for this task. -//! \param srcIncrement is the bit size increment for source data. -//! \param srcAddr is the starting address of the data to transfer. -//! \param dstIncrement is the bit size increment for destination data. -//! \param dstAddr is the starting address of the destination data. -//! \param arbSize is the arbitration size to use for the transfer task. -//! \param mode is the transfer mode for this task. -//! -//! \return Nothing; this is not a function. -// -//***************************************************************************** -#define DMA_TaskStructEntry(transferCount, \ - itemSize, \ - srcIncrement, \ - srcAddr, \ - dstIncrement, \ - dstAddr, \ - arbSize, \ - mode) \ - { \ - (((srcIncrement) == UDMA_SRC_INC_NONE) ? (void *)(srcAddr) : \ - ((void *)(&((uint8_t *)(srcAddr))[((transferCount) << \ - ((srcIncrement) >> 26)) - 1]))), \ - (((dstIncrement) == UDMA_DST_INC_NONE) ? (void *)(dstAddr) : \ - ((void *)(&((uint8_t *)(dstAddr))[((transferCount) << \ - ((dstIncrement) >> 30)) - 1]))), \ - (srcIncrement) | (dstIncrement) | (itemSize) | (arbSize) | \ - (((transferCount) - 1) << 4) | \ - ((((mode) == UDMA_MODE_MEM_SCATTER_GATHER) || \ - ((mode) == UDMA_MODE_PER_SCATTER_GATHER)) ? \ - (mode) | UDMA_MODE_ALT_SELECT : (mode)), 0 \ - } - -//***************************************************************************** -// -// Flags that can be passed to DMA_enableChannelAttribute(), -// DMA_disableChannelAttribute(), and returned from DMA_getChannelAttribute(). -// -//***************************************************************************** -#define UDMA_ATTR_USEBURST 0x00000001 -#define UDMA_ATTR_ALTSELECT 0x00000002 -#define UDMA_ATTR_HIGH_PRIORITY 0x00000004 -#define UDMA_ATTR_REQMASK 0x00000008 -#define UDMA_ATTR_ALL 0x0000000F - -//***************************************************************************** -// -// DMA control modes that can be passed to DMAModeSet() and returned -// DMAModeGet(). -// -//***************************************************************************** -#define UDMA_MODE_STOP 0x00000000 -#define UDMA_MODE_BASIC 0x00000001 -#define UDMA_MODE_AUTO 0x00000002 -#define UDMA_MODE_PINGPONG 0x00000003 -#define UDMA_MODE_MEM_SCATTER_GATHER \ - 0x00000004 -#define UDMA_MODE_PER_SCATTER_GATHER \ - 0x00000006 -#define UDMA_MODE_ALT_SELECT 0x00000001 - -//***************************************************************************** -// -// Channel configuration values that can be passed to DMAControlSet(). -// -//***************************************************************************** -#define UDMA_DST_INC_8 0x00000000 -#define UDMA_DST_INC_16 0x40000000 -#define UDMA_DST_INC_32 0x80000000 -#define UDMA_DST_INC_NONE 0xc0000000 -#define UDMA_SRC_INC_8 0x00000000 -#define UDMA_SRC_INC_16 0x04000000 -#define UDMA_SRC_INC_32 0x08000000 -#define UDMA_SRC_INC_NONE 0x0c000000 -#define UDMA_SIZE_8 0x00000000 -#define UDMA_SIZE_16 0x11000000 -#define UDMA_SIZE_32 0x22000000 -#define UDMA_DST_PROT_PRIV 0x00200000 -#define UDMA_SRC_PROT_PRIV 0x00040000 -#define UDMA_ARB_1 0x00000000 -#define UDMA_ARB_2 0x00004000 -#define UDMA_ARB_4 0x00008000 -#define UDMA_ARB_8 0x0000c000 -#define UDMA_ARB_16 0x00010000 -#define UDMA_ARB_32 0x00014000 -#define UDMA_ARB_64 0x00018000 -#define UDMA_ARB_128 0x0001c000 -#define UDMA_ARB_256 0x00020000 -#define UDMA_ARB_512 0x00024000 -#define UDMA_ARB_1024 0x00028000 -#define UDMA_NEXT_USEBURST 0x00000008 - -//***************************************************************************** -// -// Flags to be OR'd with the channel ID to indicate if the primary or alternate -// control structure should be used. -// -//***************************************************************************** -#define UDMA_PRI_SELECT 0x00000000 -#define UDMA_ALT_SELECT 0x00000008 - -//***************************************************************************** -// -// Values that can be passed to DMA_assignChannel() to select peripheral -// mapping for each channel. The channels named RESERVED may be assigned -// to a peripheral in future parts. -// -//***************************************************************************** -// -// Channel 0 -// -#define DMA_CH0_RESERVED0 0x00000000 -#define DMA_CH0_EUSCIA0TX 0x01000000 -#define DMA_CH0_EUSCIB0TX0 0x02000000 -#define DMA_CH0_EUSCIB3TX1 0x03000000 -#define DMA_CH0_EUSCIB2TX2 0x04000000 -#define DMA_CH0_EUSCIB1TX3 0x05000000 -#define DMA_CH0_TIMERA0CCR0 0x06000000 -#define DMA_CH0_AESTRIGGER0 0x07000000 - -// -// Channel 1 -// -#define DMA_CH1_RESERVED0 0x00000001 -#define DMA_CH1_EUSCIA0RX 0x01000001 -#define DMA_CH1_EUSCIB0RX0 0x02000001 -#define DMA_CH1_EUSCIB3RX1 0x03000001 -#define DMA_CH1_EUSCIB2RX2 0x04000001 -#define DMA_CH1_EUSCIB1RX3 0x05000001 -#define DMA_CH1_TIMERA0CCR2 0x06000001 -#define DMA_CH1_AESTRIGGER1 0x07000001 - -// -// Channel 2 -// -#define DMA_CH2_RESERVED0 0x00000002 -#define DMA_CH2_EUSCIA1TX 0x01000002 -#define DMA_CH2_EUSCIB1TX0 0x02000002 -#define DMA_CH2_EUSCIB0TX1 0x03000002 -#define DMA_CH2_EUSCIB3TX2 0x04000002 -#define DMA_CH2_EUSCIB2TX3 0x05000002 -#define DMA_CH2_TIMERA1CCR0 0x06000002 -#define DMA_CH2_AESTRIGGER2 0x07000002 - -// -// Channel 3 -// -#define DMA_CH3_RESERVED0 0x00000003 -#define DMA_CH3_EUSCIA1RX 0x01000003 -#define DMA_CH3_EUSCIB1RX0 0x02000003 -#define DMA_CH3_EUSCIB0RX1 0x03000003 -#define DMA_CH3_EUSCIB3RX2 0x04000003 -#define DMA_CH3_EUSCIB2RX3 0x05000003 -#define DMA_CH3_TIMERA1CCR2 0x06000003 -#define DMA_CH3_RESERVED1 0x07000003 - -// -// Channel 4 -// -#define DMA_CH4_RESERVED0 0x00000004 -#define DMA_CH4_EUSCIA2TX 0x01000004 -#define DMA_CH4_EUSCIB2TX0 0x02000004 -#define DMA_CH4_EUSCIB1TX1 0x03000004 -#define DMA_CH4_EUSCIB0TX2 0x04000004 -#define DMA_CH4_EUSCIB3TX3 0x05000004 -#define DMA_CH4_TIMERA2CCR0 0x06000004 -#define DMA_CH4_RESERVED1 0x07000004 - -// -// Channel 5 -// -#define DMA_CH5_RESERVED0 0x00000005 -#define DMA_CH5_EUSCIA2RX 0x01000005 -#define DMA_CH5_EUSCIB2RX0 0x02000005 -#define DMA_CH5_EUSCIB1RX1 0x03000005 -#define DMA_CH5_EUSCIB0RX2 0x04000005 -#define DMA_CH5_EUSCIB3RX3 0x05000005 -#define DMA_CH5_TIMERA2CCR2 0x06000005 -#define DMA_CH5_RESERVED1 0x07000005 - -// -// Channel 6 -// -#define DMA_CH6_RESERVED0 0x00000006 -#define DMA_CH6_EUSCIA3TX 0x01000006 -#define DMA_CH6_EUSCIB3TX0 0x02000006 -#define DMA_CH6_EUSCIB2TX1 0x03000006 -#define DMA_CH6_EUSCIB1TX2 0x04000006 -#define DMA_CH6_EUSCIB0TX3 0x05000006 -#define DMA_CH6_TIMERA3CCR0 0x06000006 -#define DMA_CH6_EXTERNALPIN 0x07000006 - -// -// Channel 7 -// -#define DMA_CH7_RESERVED0 0x00000007 -#define DMA_CH7_EUSCIA3RX 0x01000007 -#define DMA_CH7_EUSCIB3RX0 0x02000007 -#define DMA_CH7_EUSCIB2RX1 0x03000007 -#define DMA_CH7_EUSCIB1RX2 0x04000007 -#define DMA_CH7_EUSCIB0RX3 0x05000007 -#define DMA_CH7_TIMERA3CCR2 0x06000007 -#define DMA_CH7_ADC14 0x07000007 - -// -// Different interrupt handlers to pass into DMA_registerInterrupt and -// DMA_unregisterInterrupt and other Int functions -// -#define DMA_INT0 INT_DMA_INT0 -#define DMA_INT1 INT_DMA_INT1 -#define DMA_INT2 INT_DMA_INT2 -#define DMA_INT3 INT_DMA_INT3 -#define DMA_INTERR INT_DMA_ERR - -#define DMA_CHANNEL_0 0 -#define DMA_CHANNEL_1 1 -#define DMA_CHANNEL_2 2 -#define DMA_CHANNEL_3 3 -#define DMA_CHANNEL_4 4 -#define DMA_CHANNEL_5 5 -#define DMA_CHANNEL_6 6 -#define DMA_CHANNEL_7 7 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! Enables the DMA controller for use. -//! -//! This function enables the DMA controller. The DMA controller must be -//! enabled before it can be configured and used. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_enableModule(void); - -//***************************************************************************** -// -//! Disables the DMA controller for use. -//! -//! This function disables the DMA controller. Once disabled, the DMA -//! controller cannot operate until re-enabled with DMA_enableModule(). -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_disableModule(void); - -//***************************************************************************** -// -//! Gets the DMA error status. -//! -//! This function returns the DMA error status. It should be called from -//! within the DMA error interrupt handler to determine if a DMA error -//! occurred. -//! -//! \return Returns non-zero if a DMA error is pending. -// -//***************************************************************************** -extern uint32_t DMA_getErrorStatus(void); - -//***************************************************************************** -// -//! Clears the DMA error interrupt. -//! -//! This function clears a pending DMA error interrupt. This function should -//! be called from within the DMA error interrupt handler to clear the -//! interrupt. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_clearErrorStatus(void); - -//***************************************************************************** -// -//! Enables a DMA channel for operation. -//! -//! \param channelNum is the channel number to enable. -//! -//! When a DMA transfer is completed, the channel is automatically disabled by -//! the DMA controller. Therefore, this function should be called prior to -//! starting up any new transfer. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_enableChannel(uint32_t channelNum); - -//***************************************************************************** -// -//! Disables a DMA channel for operation. -//! -//! \param channelNum is the channel number to disable. -//! -//! This function disables a specific DMA channel. Once disabled, a channel -//! cannot respond to DMA transfer requests until re-enabled via -//! DMA_enableChannel(). -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_disableChannel(uint32_t channelNum); - -//***************************************************************************** -// -//! Checks if a DMA channel is enabled for operation. -//! -//! \param channelNum is the channel number to check. -//! -//! This function checks to see if a specific DMA channel is enabled. This -//! function can be used to check the status of a transfer, as the channel is -//! automatically disabled at the end of a transfer. -//! -//! \return Returns \b true if the channel is enabled, \b false if disabled. -// -//***************************************************************************** -extern bool DMA_isChannelEnabled(uint32_t channelNum); - -//***************************************************************************** -// -//! Sets the base address for the channel control table. -//! -//! \param controlTable is a pointer to the 1024-byte-aligned base address -//! of the DMA channel control table. -//! -//! This function configures the base address of the channel control table. -//! This table resides in system memory and holds control information for each -//! DMA channel. The table must be aligned on a 1024-byte boundary. The base -//! address must be configured before any of the channel functions can be used. -//! -//! The size of the channel control table depends on the number of DMA -//! channels and the transfer modes that are used. Refer to the introductory -//! text and the microcontroller datasheet for more information about the -//! channel control table. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_setControlBase(void *controlTable); - -//***************************************************************************** -// -//! Gets the base address for the channel control table. -//! -//! This function gets the base address of the channel control table. This -//! table resides in system memory and holds control information for each DMA -//! channel. -//! -//! \return Returns a pointer to the base address of the channel control table. -// -//***************************************************************************** -extern void* DMA_getControlBase(void); - -//***************************************************************************** -// -//! Gets the base address for the channel control table alternate structures. -//! -//! This function gets the base address of the second half of the channel -//! control table that holds the alternate control structures for each channel. -//! -//! \return Returns a pointer to the base address of the second half of the -//! channel control table. -// -//***************************************************************************** -extern void* DMA_getControlAlternateBase(void); - -//***************************************************************************** -// -//! Requests a DMA channel to start a transfer. -//! -//! \param channelNum is the channel number on which to request a DMA -//! transfer. -//! -//! This function allows software to request a DMA channel to begin a -//! transfer. This function could be used for performing a memory-to-memory -//! transfer, or if for some reason a transfer needs to be initiated by -//! software instead of the peripheral associated with that channel. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_requestChannel(uint32_t channelNum); - -//***************************************************************************** -// -//! Enables attributes of a DMA channel. -//! -//! \param channelNum is the channel to configure. -//! \param attr is a combination of attributes for the channel. -//! -//! This function is used to enable attributes of a DMA channel. -//! -//! The \e attr parameter is the logical OR of any of the following: -//! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel (it is very unlikely that this flag should be used). -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_enableChannelAttribute(uint32_t channelNum, uint32_t attr); - -//***************************************************************************** -// -//! Disables attributes of a DMA channel. -//! -//! \param channelNum is the channel to configure. -//! \param attr is a combination of attributes for the channel. -//! -//! This function is used to disable attributes of a DMA channel. -//! -//! The \e attr parameter is the logical OR of any of the following: -//! -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel. -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_disableChannelAttribute(uint32_t channelNum, uint32_t attr); - -//***************************************************************************** -// -//! Gets the enabled attributes of a DMA channel. -//! -//! \param channelNum is the channel to configure. -//! -//! This function returns a combination of flags representing the attributes of -//! the DMA channel. -//! -//! \return Returns the logical OR of the attributes of the DMA channel, which -//! can be any of the following: -//! - \b UDMA_ATTR_USEBURST is used to restrict transfers to use only burst -//! mode. -//! - \b UDMA_ATTR_ALTSELECT is used to select the alternate control structure -//! for this channel. -//! - \b UDMA_ATTR_HIGH_PRIORITY is used to set this channel to high priority. -//! - \b UDMA_ATTR_REQMASK is used to mask the hardware request signal from the -//! peripheral for this channel. -// -//***************************************************************************** -extern uint32_t DMA_getChannelAttribute(uint32_t channelNum); - -//***************************************************************************** -// -//! Sets the control parameters for a DMA channel control structure. -//! -//! \param channelStructIndex is the logical OR of the DMA channel number -//! with \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! \param control is logical OR of several control values to set the control -//! parameters for the channel. -//! -//! This function is used to set control parameters for a DMA transfer. These -//! parameters are typically not changed often. -//! -//! The \e channelStructIndex parameter should be the logical OR of the -//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to -//! choose whether the primary or alternate data structure is used. -//! -//! The \e control parameter is the logical OR of five values: the data size, -//! the source address increment, the destination address increment, the -//! arbitration size, and the use burst flag. The choices available for each -//! of these values is described below. -//! -//! Choose the data size from one of \b UDMA_SIZE_8, \b UDMA_SIZE_16, or -//! \b UDMA_SIZE_32 to select a data size of 8, 16, or 32 bits. -//! -//! Choose the source address increment from one of \b UDMA_SRC_INC_8, -//! \b UDMA_SRC_INC_16, \b UDMA_SRC_INC_32, or \b UDMA_SRC_INC_NONE to select -//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or -//! to select non-incrementing. -//! -//! Choose the destination address increment from one of \b UDMA_DST_INC_8, -//! \b UDMA_DST_INC_16, \b UDMA_DST_INC_32, or \b UDMA_SRC_INC_8 to select -//! an address increment of 8-bit bytes, 16-bit half-words, 32-bit words, or -//! to select non-incrementing. -//! -//! The arbitration size determines how many items are transferred before -//! the DMA controller re-arbitrates for the bus. Choose the arbitration size -//! from one of \b UDMA_ARB_1, \b UDMA_ARB_2, \b UDMA_ARB_4, \b UDMA_ARB_8, -//! through \b UDMA_ARB_1024 to select the arbitration size from 1 to 1024 -//! items, in powers of 2. -//! -//! The value \b UDMA_NEXT_USEBURST is used to force the channel to only -//! respond to burst requests at the tail end of a scatter-gather transfer. -//! -//! \note The address increment cannot be smaller than the data size. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_setChannelControl(uint32_t channelStructIndex, - uint32_t control); - -//***************************************************************************** -// -//! Sets the transfer parameters for a DMA channel control structure. -//! -//! \param channelStructIndex is the logical OR of the DMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! \param mode is the type of DMA transfer. -//! \param srcAddr is the source address for the transfer. -//! \param dstAddr is the destination address for the transfer. -//! \param transferSize is the number of data items to transfer. -//! -//! This function is used to configure the parameters for a DMA transfer. -//! These parameters are typically changed often. The function -//! DMA_setChannelControl() MUST be called at least once for this channel prior -//! to calling this function. -//! -//! The \e channelStructIndex parameter should be the logical OR of the -//! channel number with one of \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT to -//! choose whether the primary or alternate data structure is used. -//! -//! The \e mode parameter should be one of the following values: -//! -//! - \b UDMA_MODE_STOP stops the DMA transfer. The controller sets the mode -//! to this value at the end of a transfer. -//! - \b UDMA_MODE_BASIC to perform a basic transfer based on request. -//! - \b UDMA_MODE_AUTO to perform a transfer that always completes once -//! started even if the request is removed. -//! - \b UDMA_MODE_PINGPONG to set up a transfer that switches between the -//! primary and alternate control structures for the channel. This mode -//! allows use of ping-pong buffering for DMA transfers. -//! - \b UDMA_MODE_MEM_SCATTER_GATHER to set up a memory scatter-gather -//! transfer. -//! - \b UDMA_MODE_PER_SCATTER_GATHER to set up a peripheral scatter-gather -//! transfer. -//! -//! The \e srcAddr and \e dstAddr parameters are pointers to the first -//! location of the data to be transferred. These addresses should be aligned -//! according to the item size. The compiler takes care of this alignment if -//! the pointers are pointing to storage of the appropriate data type. -//! -//! The \e transferSize parameter is the number of data items, not the number -//! of bytes. -//! -//! The two scatter-gather modes, memory and peripheral, are actually different -//! depending on whether the primary or alternate control structure is -//! selected. This function looks for the \b UDMA_PRI_SELECT and -//! \b UDMA_ALT_SELECT flag along with the channel number and sets the -//! scatter-gather mode as appropriate for the primary or alternate control -//! structure. -//! -//! The channel must also be enabled using DMA_enableChannel() after calling -//! this function. The transfer does not begin until the channel has been -//! configured and enabled. Note that the channel is automatically disabled -//! after the transfer is completed, meaning that DMA_enableChannel() must be -//! called again after setting up the next transfer. -//! -//! \note Great care must be taken to not modify a channel control structure -//! that is in use or else the results are unpredictable, including the -//! possibility of undesired data transfers to or from memory or peripherals. -//! For BASIC and AUTO modes, it is safe to make changes when the channel is -//! disabled, or the DMA_getChannelMode() returns \b UDMA_MODE_STOP. For -//! PINGPONG or one of the SCATTER_GATHER modes, it is safe to modify the -//! primary or alternate control structure only when the other is being used. -//! The DMA_getChannelMode() function returns \b UDMA_MODE_STOP when a -//! channel control structure is inactive and safe to modify. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_setChannelTransfer(uint32_t channelStructIndex, uint32_t mode, - void *srcAddr, void *dstAddr, uint32_t transferSize); - -//***************************************************************************** -// -//! Configures a DMA channel for scatter-gather mode. -//! -//! \param channelNum is the DMA channel number. -//! \param taskCount is the number of scatter-gather tasks to execute. -//! \param taskList is a pointer to the beginning of the scatter-gather -//! task list. -//! \param isPeriphSG is a flag to indicate it is a peripheral scatter-gather -//! transfer (else it is memory scatter-gather transfer) -//! -//! This function is used to configure a channel for scatter-gather mode. -//! The caller must have already set up a task list and must pass a pointer to -//! the start of the task list as the \e taskList parameter. The -//! \e taskCount parameter is the count of tasks in the task list, not the -//! size of the task list. The flag \e bIsPeriphSG should be used to indicate -//! if scatter-gather should be configured for peripheral or memory -//! operation. -//! -//! \sa DMA_TaskStructEntry -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_setChannelScatterGather(uint32_t channelNum, uint32_t taskCount, - void *taskList, uint32_t isPeriphSG); - -//***************************************************************************** -// -//! Gets the current transfer size for a DMA channel control structure. -//! -//! \param channelStructIndex is the logical OR of the DMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! -//! This function is used to get the DMA transfer size for a channel. The -//! transfer size is the number of items to transfer, where the size of an item -//! might be 8, 16, or 32 bits. If a partial transfer has already occurred, -//! then the number of remaining items is returned. If the transfer is -//! complete, then 0 is returned. -//! -//! \return Returns the number of items remaining to transfer. -// -//***************************************************************************** -extern uint32_t DMA_getChannelSize(uint32_t channelStructIndex); - -//***************************************************************************** -// -//! Gets the transfer mode for a DMA channel control structure. -//! -//! \param channelStructIndex is the logical OR of the DMA channel number -//! with either \b UDMA_PRI_SELECT or \b UDMA_ALT_SELECT. -//! -//! This function is used to get the transfer mode for the DMA channel and -//! to query the status of a transfer on a channel. When the transfer is -//! complete the mode is \b UDMA_MODE_STOP. -//! -//! \return Returns the transfer mode of the specified channel and control -//! structure, which is one of the following values: \b UDMA_MODE_STOP, -//! \b UDMA_MODE_BASIC, \b UDMA_MODE_AUTO, \b UDMA_MODE_PINGPONG, -//! \b UDMA_MODE_MEM_SCATTER_GATHER, or \b UDMA_MODE_PER_SCATTER_GATHER. -// -//***************************************************************************** -extern uint32_t DMA_getChannelMode(uint32_t channelStructIndex); - -//***************************************************************************** -// -//! Assigns a peripheral mapping for a DMA channel. -//! -//! \param mapping is a macro specifying the peripheral assignment for -//! a channel. -//! -//! This function assigns a peripheral mapping to a DMA channel. It is -//! used to select which peripheral is used for a DMA channel. The parameter -//! \e mapping should be one of the macros named \b UDMA_CHn_tttt from the -//! header file \e dma.h. For example, to assign DMA channel 0 to the -//! eUSCI AO RX channel, the parameter should be the macro -//! \b UDMA_CH1_EUSCIA0RX. -//! -//! Please consult the data sheet for a table showing all the -//! possible peripheral assignments for the DMA channels for a particular -//! device. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_assignChannel(uint32_t mapping); - -//***************************************************************************** -// -//! Initializes a software transfer of the corresponding DMA channel. This is -//! done if the user wants to force a DMA on the specified channel without the -//! hardware precondition. Specific channels can be configured using the -//! DMA_assignChannel function. -//! -//! \param channel is the channel to trigger the interrupt -//! -//! -//! \return None -// -//***************************************************************************** -extern void DMA_requestSoftwareTransfer(uint32_t channel); - -//***************************************************************************** -// -//! Assigns a specific DMA channel to the corresponding interrupt handler. For -//! MSP432 devices, there are three configurable interrupts, and one master -//! interrupt. This function will assign a specific DMA channel to the -//! provided configurable DMA interrupt. -//! -//! Note that once a channel is assigned to a configurable interrupt, it will be -//! masked in hardware from the master DMA interrupt (interruptNumber zero). This -//! function can also be used in conjunction with the DMAIntTrigger function -//! to provide the feature to software trigger specific channel interrupts. -//! -//! \param interruptNumber is the configurable interrupt to assign the given -//! channel. Valid values are: -//! - \b DMA_INT1 the first configurable DMA interrupt handler -//! - \b DMA_INT2 the second configurable DMA interrupt handler -//! - \b DMA_INT3 the third configurable DMA interrupt handler -//! -//! \param channel is the channel to assign the interrupt -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_assignInterrupt(uint32_t interruptNumber, uint32_t channel); - -//***************************************************************************** -// -//! Enables the specified interrupt for the DMA controller. Note for interrupts -//! one through three, specific channels have to be mapped to the interrupt -//! using the DMA_assignInterrupt function. -//! -//! \param interruptNumber identifies which DMA interrupt is to be enabled. -//! This interrupt should be one of the following: -//! -//! - \b DMA_INT0 the master DMA interrupt handler -//! - \b DMA_INT1 the first configurable DMA interrupt handler -//! - \b DMA_INT2 the second configurable DMA interrupt handler -//! - \b DMA_INT3 the third configurable DMA interrupt handler -//! - \b DMA_INTERR the third configurable DMA interrupt handler -//! -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_enableInterrupt(uint32_t interruptNumber); - -//***************************************************************************** -// -//! Disables the specified interrupt for the DMA controller. -//! -//! \param interruptNumber identifies which DMA interrupt is to be disabled. -//! This interrupt should be one of the following: -//! -//! - \b DMA_INT0 the master DMA interrupt handler -//! - \b DMA_INT1 the first configurable DMA interrupt handler -//! - \b DMA_INT2 the second configurable DMA interrupt handler -//! - \b DMA_INT3 the third configurable DMA interrupt handler -//! - \b DMA_INTERR the third configurable DMA interrupt handler -//! -//! Note for interrupts that are associated with a specific DMA channel -//! (DMA_INT1 - DMA_INT3), this function will also enable that specific -//! channel for interrupts. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_disableInterrupt(uint32_t interruptNumber); - -//***************************************************************************** -// -//! Gets the DMA controller channel interrupt status for interrupt zero. -//! -//! This function is used to get the interrupt status of the DMA controller. -//! The returned value is a 32-bit bit mask that indicates which channels are -//! requesting an interrupt. This function can be used from within an -//! interrupt handler to determine or confirm which DMA channel has requested -//! an interrupt. -//! -//! Note that this will only apply to interrupt zero for the DMA -//! controller as only one interrupt can be associated with interrupts one -//! through three. If an interrupt is assigned to an interrupt other -//! than interrupt zero, it will be masked by this function. -//! -//! \return Returns a 32-bit mask which indicates requesting DMA channels. -//! There is a bit for each channel and a 1 indicates that the channel -//! is requesting an interrupt. Multiple bits can be set. -// -//***************************************************************************** -extern uint32_t DMA_getInterruptStatus(void); - -//***************************************************************************** -// -//! Clears the DMA controller channel interrupt mask for interrupt zero. -//! -//! \param channel is the channel interrupt to clear. -//! -//! This function is used to clear the interrupt status of the DMA controller. -//! Note that only interrupts that weren't assigned to DMA interrupts one -//! through three using the DMA_assignInterrupt function will be affected by -//! thisfunctions. For other DMA interrupts, only one channel can be associated -//! and therefore clearing in unnecessary. -//! -//! \return None -// -//***************************************************************************** -extern void DMA_clearInterruptFlag(uint32_t intChannel); - -//***************************************************************************** -// -//! Registers an interrupt handler for the DMA controller. -//! -//! \param interruptNumber identifies which DMA interrupt is to be registered. -//! \param intHandler is a pointer to the function to be called when the -//! interrupt is called. -//! -//! This function registers and enables the handler to be called when the DMA -//! controller generates an interrupt. The \e interrupt parameter should be -//! one of the following: -//! -//! - \b DMA_INT0 the master DMA interrupt handler -//! - \b DMA_INT1 the first configurable DMA interrupt handler -//! - \b DMA_INT2 the second configurable DMA interrupt handler -//! - \b DMA_INT3 the third configurable DMA interrupt handler -//! - \b DMA_INTERR the third configurable DMA interrupt handler -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_registerInterrupt(uint32_t intChannel, - void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the DMA controller. -//! -//! \param interruptNumber identifies which DMA interrupt to unregister. -//! -//! This function disables and unregisters the handler to be called for the -//! specified DMA interrupt. The \e interrupt parameter should be one of -//! \b the parameters as documented for the function -//! DMA_registerInterrupt(). -//! -//! Note fore interrupts that are associated with a specific DMA channel -//! (DMA_INT1 - DMA_INT3), this function will also disable that specific -//! channel for interrupts. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void DMA_unregisterInterrupt(uint32_t intChannel); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif // __UDMA_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/driverlib.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/driverlib.h deleted file mode 100644 index 0f8df2e7942..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/driverlib.h +++ /dev/null @@ -1,96 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __DRIVERLIB__H_ -#define __DRIVERLIB__H_ - -/* Common Modules */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* Device specific modules */ -#if defined(__MCU_HAS_SYSCTL_A__) -#include -#endif - -#if defined(__MCU_HAS_SYSCTL__) -#include -#endif - -#if defined(__MCU_HAS_FLCTL_A__) -#include -#endif - -#if defined(__MCU_HAS_FLCTL__) -#include -#endif - -#if defined(__MCU_HAS_LCD_F__) -#include -#endif - -/* Offset Definitions */ -#define HWREG8(x) (*((volatile uint8_t *)(x))) -#define HWREG16(x) (*((volatile uint16_t *)(x))) -#define HWREG32(x) (*((volatile uint32_t *)(x))) -#define HWREG(x) (HWREG16(x)) -#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x))) -#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1))) -#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x))) -#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1))) - - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/eusci.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/eusci.h deleted file mode 100644 index 663e276074c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/eusci.h +++ /dev/null @@ -1,40 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef EUSCI_H_ -#define EUSCI_H_ - -#include - -#define EUSCI_A_CMSIS(x) ((EUSCI_A_Type *) x) -#define EUSCI_B_CMSIS(x) ((EUSCI_B_Type *) x) - -#endif /* EUSCI_H_ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/flash.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/flash.c deleted file mode 100644 index 18aa5120b94..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/flash.c +++ /dev/null @@ -1,1567 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/* Standard Includes */ -#include - -/* DriverLib Includes */ -#include -#include -#include -#include -#include - -/* Define to ensure that our current MSP432 has the FLCTL module. This - definition is included in the device specific header file */ -#ifdef __MCU_HAS_FLCTL__ - -static const uint32_t MAX_ERASE_NO_TLV = 50; -static const uint32_t MAX_PROGRAM_NO_TLV = 5; - -static volatile uint32_t* __getBurstProgramRegs[16] = -{ &FLCTL->PRGBRST_DATA0_0, &FLCTL->PRGBRST_DATA0_1, -&FLCTL->PRGBRST_DATA0_2, &FLCTL->PRGBRST_DATA0_3, -&FLCTL->PRGBRST_DATA1_0, &FLCTL->PRGBRST_DATA1_1, -&FLCTL->PRGBRST_DATA1_2, &FLCTL->PRGBRST_DATA1_3, -&FLCTL->PRGBRST_DATA2_0, &FLCTL->PRGBRST_DATA2_1, -&FLCTL->PRGBRST_DATA2_2, &FLCTL->PRGBRST_DATA2_3, -&FLCTL->PRGBRST_DATA3_0, &FLCTL->PRGBRST_DATA3_1, -&FLCTL->PRGBRST_DATA3_2, &FLCTL->PRGBRST_DATA3_3 }; - -static uint32_t getUserFlashSector(uint32_t addr) -{ - if (addr > 0x1ffff) - { - addr = addr - 0x20000; - } - - switch (addr) - { - case 0: - return FLASH_SECTOR0; - case 0x1000: - return FLASH_SECTOR1; - case 0x2000: - return FLASH_SECTOR2; - case 0x3000: - return FLASH_SECTOR3; - case 0x4000: - return FLASH_SECTOR4; - case 0x5000: - return FLASH_SECTOR5; - case 0x6000: - return FLASH_SECTOR6; - case 0x7000: - return FLASH_SECTOR7; - case 0x8000: - return FLASH_SECTOR8; - case 0x9000: - return FLASH_SECTOR9; - case 0xA000: - return FLASH_SECTOR10; - case 0xB000: - return FLASH_SECTOR11; - case 0xC000: - return FLASH_SECTOR12; - case 0xD000: - return FLASH_SECTOR13; - case 0xE000: - return FLASH_SECTOR14; - case 0xF000: - return FLASH_SECTOR15; - case 0x10000: - return FLASH_SECTOR16; - case 0x11000: - return FLASH_SECTOR17; - case 0x12000: - return FLASH_SECTOR18; - case 0x13000: - return FLASH_SECTOR19; - case 0x14000: - return FLASH_SECTOR20; - case 0x15000: - return FLASH_SECTOR21; - case 0x16000: - return FLASH_SECTOR22; - case 0x17000: - return FLASH_SECTOR23; - case 0x18000: - return FLASH_SECTOR24; - case 0x19000: - return FLASH_SECTOR25; - case 0x1A000: - return FLASH_SECTOR26; - case 0x1B000: - return FLASH_SECTOR27; - case 0x1C000: - return FLASH_SECTOR28; - case 0x1D000: - return FLASH_SECTOR29; - case 0x1E000: - return FLASH_SECTOR30; - case 0x1F000: - return FLASH_SECTOR31; - default: - ASSERT(false); - return 0; - } -} - -void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *bankNum, - uint32_t *sectorNum) -{ - uint32_t bankLimit; - - bankLimit = SysCtl_getFlashSize() / 2; - - if (addr > bankLimit) - { - *(bankNum) = FLASH_BANK1; - addr = (addr - bankLimit); - } else - { - *(bankNum) = FLASH_BANK0; - } - - *(sectorNum) = (addr) / 4096; -} - -static bool _FlashCtl_Program8(uint32_t src, uint32_t dest, uint32_t mTries) -{ - uint32_t ii; - uint8_t data; - - /* Enabling the correct verification settings */ - FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST); - FlashCtl_clearProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE); - - data = HWREG8(src); - - for (ii = 0; ii < mTries; ii++) - { - /* Clearing flags */ - FLCTL->CLRIFG |= (FLASH_PROGRAM_ERROR | FLASH_POSTVERIFY_FAILED - | FLASH_PREVERIFY_FAILED | FLASH_WRDPRGM_COMPLETE); - - HWREG8(dest) = data; - - while (!(FlashCtl_getInterruptStatus() & FLASH_WRDPRGM_COMPLETE)) - { - __no_operation(); - } - - /* Pre-Verify */ - if ((BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) - && BITBAND_PERI(FLCTL->IFG, FLCTL_IFG_AVPRE_OFS))) - { - data = __FlashCtl_remaskData8Pre(data, dest); - - if (data != 0xFF) - { - FlashCtl_clearProgramVerification(FLASH_REGPRE); - continue; - } - - } - - /* Post Verify */ - if ((BITBAND_PERI(FLCTL->IFG, FLCTL_IFG_AVPST_OFS))) - { - data = __FlashCtl_remaskData8Post(data, dest); - - /* Seeing if we actually need to do another pulse */ - if (data == 0xFF) - return true; - - FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST); - continue; - } - - /* If we got this far, return true */ - return true; - - } - - return false; - -} - -static bool _FlashCtl_Program32(uint32_t src, uint32_t dest, uint32_t mTries) -{ - uint32_t ii; - uint32_t data; - - /* Enabling the correct verification settings */ - FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST); - FlashCtl_clearProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE); - - data = HWREG32(src); - - for (ii = 0; ii < mTries; ii++) - { - /* Clearing flags */ - FLCTL->CLRIFG |= (FLASH_PROGRAM_ERROR | FLASH_POSTVERIFY_FAILED - | FLASH_PREVERIFY_FAILED | FLASH_WRDPRGM_COMPLETE); - - HWREG32(dest) = data; - - while (!(FlashCtl_getInterruptStatus() & FLASH_WRDPRGM_COMPLETE)) - { - __no_operation(); - } - - /* Pre-Verify */ - if ((BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) - && BITBAND_PERI(FLCTL->IFG, FLCTL_IFG_AVPRE_OFS))) - { - data = __FlashCtl_remaskData32Pre(data, dest); - - if (data != 0xFFFFFFFF) - { - - FlashCtl_clearProgramVerification(FLASH_REGPRE); - continue; - } - - } - - /* Post Verify */ - if ((BITBAND_PERI(FLCTL->IFG, FLCTL_IFG_AVPST_OFS))) - { - data = __FlashCtl_remaskData32Post(data, dest); - - /* Seeing if we actually need to do another pulse */ - if (data == 0xFFFFFFFF) - return true; - - FlashCtl_setProgramVerification(FLASH_REGPRE | FLASH_REGPOST); - continue; - } - - /* If we got this far, return true */ - return true; - - } - - return false; - -} - -static bool _FlashCtl_ProgramBurst(uint32_t src, uint32_t dest, uint32_t length, - uint32_t mTries) -{ - uint32_t bCalc, otpOffset, ii, jj; - bool res; - - /* Setting verification */ - FlashCtl_clearProgramVerification(FLASH_REGPRE | FLASH_REGPOST); - FlashCtl_setProgramVerification(FLASH_BURSTPOST | FLASH_BURSTPRE); - - /* Assume Failure */ - res = false; - - /* Waiting for idle status */ - while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK) - != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0) - { - BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1; - } - - /* Setting/clearing INFO flash flags as appropriate */ - if (dest > SysCtl_getFlashSize()) - { - FLCTL->PRGBRST_CTLSTAT = (FLCTL->PRGBRST_CTLSTAT - & ~FLCTL_PRGBRST_CTLSTAT_TYPE_MASK) | FLCTL_PRGBRST_CTLSTAT_TYPE_1; - otpOffset = __INFO_FLASH_TECH_START__; - } else - { - FLCTL->PRGBRST_CTLSTAT = (FLCTL->PRGBRST_CTLSTAT - & ~FLCTL_PRGBRST_CTLSTAT_TYPE_MASK) | FLCTL_PRGBRST_CTLSTAT_TYPE_0; - otpOffset = 0; - } - - bCalc = 0; - FLCTL->PRGBRST_STARTADDR = (dest - otpOffset); - - /* Initially populating the burst registers */ - while (bCalc < 16 && length != 0) - { - HWREG32(__getBurstProgramRegs[bCalc]) = HWREG32(src); - bCalc++; - length -= 4; - src += 4; - } - - for (ii = 0; ii < mTries; ii++) - { - /* Clearing Flags */ - FLCTL->CLRIFG |= (FLASH_BRSTPRGM_COMPLETE | FLASH_POSTVERIFY_FAILED - | FLASH_PREVERIFY_FAILED); - - /* Waiting for idle status */ - while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK) - != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0) - { - BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1; - } - - /* Start the burst program */ - FLCTL->PRGBRST_CTLSTAT = (FLCTL->PRGBRST_CTLSTAT - & ~(FLCTL_PRGBRST_CTLSTAT_LEN_MASK)) - | ((bCalc / 4) << FLASH_BURST_PRG_BIT) - | FLCTL_PRGBRST_CTLSTAT_START; - - /* Waiting for the burst to complete */ - while ((FLCTL->PRGBRST_CTLSTAT & - FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK) - != FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE) - { - __no_operation(); - } - - /* Checking for errors and clearing/masking */ - - /* Address Error */ - if (BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS)) - { - goto BurstCleanUp; - } - - /* Pre-Verify Error */ - if (BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) && BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS)) - { - __FlashCtl_remaskBurstDataPre(dest, bCalc * 4); - - for (jj = 0; jj < bCalc; jj++) - { - if (HWREG32(__getBurstProgramRegs[jj]) - != 0xFFFFFFFF) - { - FlashCtl_clearProgramVerification(FLASH_BURSTPRE); - break; - } - } - - if (jj != bCalc) - continue; - } - - /* Post-Verify Error */ - if (BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS)) - { - __FlashCtl_remaskBurstDataPost(dest, bCalc * 4); - - for (jj = 0; jj < bCalc; jj++) - { - if ((HWREG32(__getBurstProgramRegs[jj])) - != 0xFFFFFFFF) - { - FlashCtl_setProgramVerification( - FLASH_BURSTPOST | FLASH_BURSTPRE); - break; - } - } - - if (jj != bCalc) - continue; - - } - - /* If we got this far, the program happened */ - res = true; - goto BurstCleanUp; - } - - BurstCleanUp: - /* Waiting for idle status */ - while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK) - != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0) - { - BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1; - } - return res; -} - -void FlashCtl_enableReadBuffering(uint_fast8_t memoryBank, - uint_fast8_t accessMethod) -{ - if (memoryBank == FLASH_BANK0 && accessMethod == FLASH_DATA_READ) - BITBAND_PERI(FLCTL->BANK0_RDCTL, FLCTL_BANK0_RDCTL_BUFD_OFS) = 1; - else if (memoryBank == FLASH_BANK1 && accessMethod == FLASH_DATA_READ) - BITBAND_PERI(FLCTL->BANK1_RDCTL, FLCTL_BANK1_RDCTL_BUFD_OFS) = 1; - else if (memoryBank == FLASH_BANK0 - && accessMethod == FLASH_INSTRUCTION_FETCH) - BITBAND_PERI(FLCTL->BANK0_RDCTL, FLCTL_BANK0_RDCTL_BUFI_OFS) = 1; - else if (memoryBank == FLASH_BANK1 - && accessMethod == FLASH_INSTRUCTION_FETCH) - BITBAND_PERI(FLCTL->BANK1_RDCTL, FLCTL_BANK1_RDCTL_BUFI_OFS) = 1; - else - ASSERT(false); -} - -void FlashCtl_disableReadBuffering(uint_fast8_t memoryBank, - uint_fast8_t accessMethod) -{ - if (memoryBank == FLASH_BANK0 && accessMethod == FLASH_DATA_READ) - BITBAND_PERI(FLCTL->BANK0_RDCTL, FLCTL_BANK0_RDCTL_BUFD_OFS) = 0; - else if (memoryBank == FLASH_BANK1 && accessMethod == FLASH_DATA_READ) - BITBAND_PERI(FLCTL->BANK1_RDCTL, FLCTL_BANK1_RDCTL_BUFD_OFS) = 0; - else if (memoryBank == FLASH_BANK0 - && accessMethod == FLASH_INSTRUCTION_FETCH) - BITBAND_PERI(FLCTL->BANK0_RDCTL, FLCTL_BANK0_RDCTL_BUFI_OFS) = 0; - else if (memoryBank == FLASH_BANK1 - && accessMethod == FLASH_INSTRUCTION_FETCH) - BITBAND_PERI(FLCTL->BANK1_RDCTL, FLCTL_BANK1_RDCTL_BUFI_OFS) = 0; - else - ASSERT(false); -} - -bool FlashCtl_unprotectSector(uint_fast8_t memorySpace, uint32_t sectorMask) -{ - switch (memorySpace) - { - case FLASH_MAIN_MEMORY_SPACE_BANK0: - FLCTL->BANK0_MAIN_WEPROT &= ~sectorMask; - break; - case FLASH_MAIN_MEMORY_SPACE_BANK1: - FLCTL->BANK1_MAIN_WEPROT &= ~sectorMask; - break; - case FLASH_INFO_MEMORY_SPACE_BANK0: - ASSERT(sectorMask <= 0x04); - FLCTL->BANK0_INFO_WEPROT &= ~sectorMask; - break; - case FLASH_INFO_MEMORY_SPACE_BANK1: - ASSERT(sectorMask <= 0x04); - FLCTL->BANK1_INFO_WEPROT &= ~sectorMask; - break; - - default: - ASSERT(false); - - } - - return !FlashCtl_isSectorProtected(memorySpace, sectorMask); -} - -bool FlashCtl_protectSector(uint_fast8_t memorySpace, uint32_t sectorMask) -{ - switch (memorySpace) - { - case FLASH_MAIN_MEMORY_SPACE_BANK0: - FLCTL->BANK0_MAIN_WEPROT |= sectorMask; - break; - case FLASH_MAIN_MEMORY_SPACE_BANK1: - FLCTL->BANK1_MAIN_WEPROT |= sectorMask; - break; - case FLASH_INFO_MEMORY_SPACE_BANK0: - ASSERT(sectorMask <= 0x04); - FLCTL->BANK0_INFO_WEPROT |= sectorMask; - break; - case FLASH_INFO_MEMORY_SPACE_BANK1: - ASSERT(sectorMask <= 0x04); - FLCTL->BANK1_INFO_WEPROT |= sectorMask; - break; - - default: - ASSERT(false); - - } - - return FlashCtl_isSectorProtected(memorySpace, sectorMask); -} - -bool FlashCtl_isSectorProtected(uint_fast8_t memorySpace, uint32_t sector) -{ - switch (memorySpace) - { - case FLASH_MAIN_MEMORY_SPACE_BANK0: - return FLCTL->BANK0_MAIN_WEPROT & sector; - case FLASH_MAIN_MEMORY_SPACE_BANK1: - return FLCTL->BANK1_MAIN_WEPROT & sector; - case FLASH_INFO_MEMORY_SPACE_BANK0: - ASSERT(sector <= 0x04); - return FLCTL->BANK0_INFO_WEPROT & sector; - case FLASH_INFO_MEMORY_SPACE_BANK1: - ASSERT(sector <= 0x04); - return FLCTL->BANK1_INFO_WEPROT & sector; - default: - return false; - } -} - -bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length, - uint_fast8_t pattern) -{ - uint32_t memoryPattern, addr, otpOffset; - uint32_t b0WaitState, b1WaitState, intStatus; - uint32_t bankOneStart, startBank, endBank; - uint_fast8_t b0readMode, b1readMode; - uint_fast8_t memoryType; - bool res; - - ASSERT(pattern == FLASH_0_PATTERN || pattern == FLASH_1_PATTERN); - - /* Saving interrupt context and disabling interrupts for program - * operation - */ - intStatus = CPU_primask(); - Interrupt_disableMaster(); - - /* Casting and determining the memory that we need to use */ - addr = (uint32_t) verifyAddr; - memoryType = - (addr > SysCtl_getFlashSize()) ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE; - - /* Assuming Failure */ - res = false; - - /* Finding out which bank we are in */ - if(addr > SysCtl_getFlashSize()) - { - bankOneStart = __INFO_FLASH_TECH_MIDDLE__; - } - else - { - bankOneStart = SysCtl_getFlashSize() / 2; - } - startBank = addr < (bankOneStart) ? FLASH_BANK0 : FLASH_BANK1; - endBank = (addr + length) < (bankOneStart) ? FLASH_BANK0 : FLASH_BANK1; - - /* Saving context and changing read modes */ - b0WaitState = FlashCtl_getWaitState(startBank); - b0readMode = FlashCtl_getReadMode(startBank); - - /* Setting the wait state to account for the mode */ - FlashCtl_setWaitState(startBank, (2 * b0WaitState) + 1); - - if(startBank != endBank) - { - b1WaitState = FlashCtl_getWaitState(endBank); - b1readMode = FlashCtl_getReadMode(endBank); - FlashCtl_setWaitState(endBank, (2 * b1WaitState) + 1); - } - - /* Changing to the relevant VERIFY mode */ - if (pattern == FLASH_1_PATTERN) - { - FlashCtl_setReadMode(startBank, FLASH_ERASE_VERIFY_READ_MODE); - - if(startBank != endBank) - { - FlashCtl_setReadMode(endBank, FLASH_ERASE_VERIFY_READ_MODE); - } - - memoryPattern = 0xFFFFFFFF; - } else - { - FlashCtl_setReadMode(startBank, FLASH_PROGRAM_VERIFY_READ_MODE); - - if(startBank != endBank) - { - FlashCtl_setReadMode(endBank, FLASH_PROGRAM_VERIFY_READ_MODE); - } - - memoryPattern = 0; - } - - /* Taking care of byte accesses */ - while ((addr & 0x03) && (length > 0)) - { - if (HWREG8(addr++) != ((uint8_t) memoryPattern)) - goto FlashVerifyCleanup; - length--; - } - - /* Making sure we are aligned by 128-bit address */ - while (((addr & 0x0F)) && (length > 3)) - { - if (HWREG32(addr) != memoryPattern) - goto FlashVerifyCleanup; - - addr = addr + 4; - length = length - 4; - } - - /* Burst Verify */ - if (length > 63) - { - /* Setting/clearing INFO flash flags as appropriate */ - if (addr > SysCtl_getFlashSize()) - { - FLCTL->RDBRST_CTLSTAT = (FLCTL->RDBRST_CTLSTAT - & ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK) - | FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1; - otpOffset = __INFO_FLASH_TECH_START__; - } else - { - FLCTL->RDBRST_CTLSTAT = (FLCTL->RDBRST_CTLSTAT - & ~FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK) - | FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0; - otpOffset = 0; - } - - /* Clearing any lingering fault flags and preparing burst verify*/ - BITBAND_PERI(FLCTL->RDBRST_CTLSTAT, - FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) = 1; - FLCTL->RDBRST_FAILCNT = 0; - FLCTL->RDBRST_STARTADDR = addr - otpOffset; - FLCTL->RDBRST_LEN = (length & 0xFFFFFFF0); - addr += FLCTL->RDBRST_LEN; - length = length & 0xF; - - /* Starting Burst Verify */ - FLCTL->RDBRST_CTLSTAT = (FLCTL_RDBRST_CTLSTAT_STOP_FAIL | pattern - | memoryType | FLCTL_RDBRST_CTLSTAT_START); - - /* While the burst read hasn't finished */ - while ((FLCTL->RDBRST_CTLSTAT & FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK) - != FLCTL_RDBRST_CTLSTAT_BRST_STAT_3) - { - __no_operation(); - } - - /* Checking for a verification/access error/failure */ - if (BITBAND_PERI(FLCTL->RDBRST_CTLSTAT, - FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS) - || BITBAND_PERI(FLCTL->RDBRST_CTLSTAT, - FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS) - || FLCTL->RDBRST_FAILCNT) - { - goto FlashVerifyCleanup; - } - } - - /* Remaining Words */ - while (length > 3) - { - if (HWREG32(addr) != memoryPattern) - goto FlashVerifyCleanup; - - addr = addr + 4; - length = length - 4; - } - - /* Remaining Bytes */ - while (length > 0) - { - if (HWREG8(addr++) != ((uint8_t) memoryPattern)) - goto FlashVerifyCleanup; - length--; - } - - /* If we got this far, that means it no failure happened */ - res = true; - - FlashVerifyCleanup: - - /* Clearing the Read Burst flag and returning */ - BITBAND_PERI(FLCTL->RDBRST_CTLSTAT, - FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS) = 1; - - FlashCtl_setReadMode(startBank, b0readMode); - FlashCtl_setWaitState(startBank, b0WaitState); - - if(startBank != endBank) - { - FlashCtl_setReadMode(endBank, b1readMode); - FlashCtl_setWaitState(endBank, b1WaitState); - } - - if(intStatus == 0) - Interrupt_enableMaster(); - - return res; -} - -bool FlashCtl_setReadMode(uint32_t flashBank, uint32_t readMode) -{ - - if (FLCTL->POWER_STAT & FLCTL_POWER_STAT_RD_2T) - return false; - - if (flashBank == FLASH_BANK0) - { - FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL - & ~FLCTL_BANK0_RDCTL_RD_MODE_MASK) | readMode; - while ((FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK) - != (readMode<<16)) - ; - } else if (flashBank == FLASH_BANK1) - { - FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL - & ~FLCTL_BANK1_RDCTL_RD_MODE_MASK) | readMode; - while ((FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK) - != (readMode<<16)) - ; - } else - { - ASSERT(false); - return false; - } - - return true; -} - -uint32_t FlashCtl_getReadMode(uint32_t flashBank) -{ - if (flashBank == FLASH_BANK0) - { - return (FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK) >> 16; - } else if (flashBank == FLASH_BANK1) - { - return (FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK) >> 16; - } else - { - ASSERT(false); - return 0; - } -} - -void FlashCtl_initiateMassErase(void) -{ - /* Clearing old mass erase flags */ - BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1; - - /* Performing the mass erase */ - FLCTL->ERASE_CTLSTAT |= (FLCTL_ERASE_CTLSTAT_MODE - | FLCTL_ERASE_CTLSTAT_START); -} - -bool FlashCtl_performMassErase(void) -{ - uint32_t userFlash, ii, sector, intStatus; - bool res; - - /* Saving interrupt context and disabling interrupts for program - * operation - */ - intStatus = CPU_primask(); - Interrupt_disableMaster(); - - /* Assume Failure */ - res = false; - - /* Clearing old mass erase flags */ - BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1; - - /* Performing the mass erase */ - FLCTL->ERASE_CTLSTAT |= (FLCTL_ERASE_CTLSTAT_MODE - | FLCTL_ERASE_CTLSTAT_START); - - while ((FLCTL->ERASE_CTLSTAT & FLCTL_ERASE_CTLSTAT_STATUS_MASK) - == FLCTL_ERASE_CTLSTAT_STATUS_1 - || (FLCTL->ERASE_CTLSTAT & FLCTL_ERASE_CTLSTAT_STATUS_MASK) - == FLCTL_ERASE_CTLSTAT_STATUS_2) - { - __no_operation(); - } - - /* Return false if an address error */ - if (BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS)) - goto MassEraseCleanup; - - /* Changing to erase verify */ - userFlash = SysCtl_getFlashSize() / 2; - - for (ii = 0; ii < userFlash; ii += 4096) - { - sector = getUserFlashSector(ii); - - if (!((FLCTL->BANK0_MAIN_WEPROT) & sector)) - { - if (!FlashCtl_verifyMemory((void*) ii, 4096, FLASH_1_PATTERN)) - { - if (!FlashCtl_eraseSector(ii)) - goto MassEraseCleanup; - } - } - - if (!(FLCTL->BANK1_MAIN_WEPROT & sector)) - { - if (!FlashCtl_verifyMemory((void*) (ii + userFlash), 4096, - FLASH_1_PATTERN)) - { - if (!FlashCtl_eraseSector(ii + userFlash)) - goto MassEraseCleanup; - } - } - - if (sector < FLCTL_BANK0_MAIN_WEPROT_PROT2) - { - if (!(FLCTL->BANK0_INFO_WEPROT & sector)) - { - if (!FlashCtl_verifyMemory( - (void*) (ii + __INFO_FLASH_TECH_START__), 4096, - FLASH_1_PATTERN)) - { - if (!FlashCtl_eraseSector(ii + __INFO_FLASH_TECH_START__)) - goto MassEraseCleanup; - } - } - - if (!(FLCTL->BANK1_INFO_WEPROT & sector)) - { - if (!FlashCtl_verifyMemory((void*) (ii + (0x202000)), 4096, - FLASH_1_PATTERN)) - { - if (!FlashCtl_eraseSector(ii + (0x202000))) - goto MassEraseCleanup; - } - } - - } - } - - /* If we got this far, the mass erase happened */ - res = true; - - MassEraseCleanup: - BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1; - - if(intStatus == 0) - Interrupt_enableMaster(); - - return res; -} - -bool FlashCtl_eraseSector(uint32_t addr) -{ - uint_fast8_t memoryType, ii; - uint32_t otpOffset = 0; - uint32_t intStatus; - uint_fast8_t mTries, tlvLength; - SysCtl_FlashTLV_Info *flInfo; - bool res; - - /* Saving interrupt context and disabling interrupts for program - * operation - */ - intStatus = CPU_primask(); - Interrupt_disableMaster(); - - /* Assuming Failure */ - res = false; - - memoryType = - addr > SysCtl_getFlashSize() ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE; - - /* Parsing the TLV and getting the maximum erase pulses */ - SysCtl_getTLVInfo(TLV_TAG_FLASHCTL, 0, &tlvLength, (uint32_t**) &flInfo); - - if (tlvLength == 0 || flInfo->maxErasePulses == 0) - { - mTries = MAX_ERASE_NO_TLV; - } else - { - mTries = flInfo->maxErasePulses; - } - - /* We can only erase on 4KB boundaries */ - while (addr & 0xFFF) - { - addr--; - } - - /* Clearing the status */ - BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1; - - if (memoryType == FLASH_INFO_SPACE) - { - otpOffset = __INFO_FLASH_TECH_START__; - FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT - & ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_1; - - } else - { - otpOffset = 0; - FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT - & ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_0; - } - - /* Clearing old flags and setting up the erase */ - BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_MODE_OFS) = 0; - FLCTL->ERASE_SECTADDR = addr - otpOffset; - - for (ii = 0; ii < mTries; ii++) - { - /* Clearing the status */ - BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = - 1; - - /* Starting the erase */ - BITBAND_PERI(FLCTL->ERASE_CTLSTAT, - FLCTL_ERASE_CTLSTAT_START_OFS) = 1; - - while ((FLCTL->ERASE_CTLSTAT & FLCTL_ERASE_CTLSTAT_STATUS_MASK) - == FLCTL_ERASE_CTLSTAT_STATUS_1 - || (FLCTL->ERASE_CTLSTAT & FLCTL_ERASE_CTLSTAT_STATUS_MASK) - == FLCTL_ERASE_CTLSTAT_STATUS_2) - { - __no_operation(); - } - - /* Return false if an address error */ - if (BITBAND_PERI(FLCTL->ERASE_CTLSTAT, - FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS)) - { - goto SectorEraseCleanup; - } - /* Erase verifying */ - if (FlashCtl_verifyMemory((void*) addr, 4096, FLASH_1_PATTERN)) - { - res = true; - goto SectorEraseCleanup; - } - - } - -SectorEraseCleanup: - - BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1; - - if(intStatus == 0) - Interrupt_enableMaster(); - - return res; -} - -void FlashCtl_initiateSectorErase(uint32_t addr) -{ - uint_fast8_t memoryType; - uint32_t otpOffset = 0; - - memoryType = - addr > SysCtl_getFlashSize() ? FLASH_INFO_SPACE : FLASH_MAIN_SPACE; - - /* We can only erase on 4KB boundaries */ - while (addr & 0xFFF) - { - addr--; - } - - /* Clearing the status */ - BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS) = 1; - - if (memoryType == FLASH_INFO_SPACE) - { - otpOffset = __INFO_FLASH_TECH_START__; - FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT - & ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_1; - - } else - { - otpOffset = 0; - FLCTL->ERASE_CTLSTAT = (FLCTL->ERASE_CTLSTAT - & ~(FLCTL_ERASE_CTLSTAT_TYPE_MASK)) | FLCTL_ERASE_CTLSTAT_TYPE_0; - } - - /* Clearing old flags and setting up the erase */ - BITBAND_PERI(FLCTL->ERASE_CTLSTAT, FLCTL_ERASE_CTLSTAT_MODE_OFS) = 0; - FLCTL->ERASE_SECTADDR = addr - otpOffset; - - /* Starting the erase */ - BITBAND_PERI(FLCTL->ERASE_CTLSTAT, - FLCTL_ERASE_CTLSTAT_START_OFS) = 1; - -} - -bool FlashCtl_programMemory(void* src, void* dest, uint32_t length) -{ - uint32_t destAddr, srcAddr, burstLength, intStatus; - bool res; - uint_fast8_t mTries, tlvLength; - SysCtl_FlashTLV_Info *flInfo; - - /* Saving interrupt context and disabling interrupts for program - * operation - */ - intStatus = CPU_primask(); - Interrupt_disableMaster(); - - /* Parsing the TLV and getting the maximum erase pulses */ - SysCtl_getTLVInfo(TLV_TAG_FLASHCTL, 0, &tlvLength, (uint32_t**) &flInfo); - - if (tlvLength == 0 || flInfo->maxProgramPulses == 0) - { - mTries = MAX_PROGRAM_NO_TLV; - } else - { - mTries = flInfo->maxProgramPulses; - } - - /* Casting to integers */ - srcAddr = (uint32_t) src; - destAddr = (uint32_t) dest; - - /* Enabling word programming */ - FlashCtl_enableWordProgramming(FLASH_IMMEDIATE_WRITE_MODE); - - /* Assume failure */ - res = false; - - /* Taking care of byte accesses */ - while ((destAddr & 0x03) && length > 0) - { - if (!_FlashCtl_Program8(srcAddr, destAddr, mTries)) - { - goto FlashProgramCleanUp; - } else - { - srcAddr++; - destAddr++; - length--; - } - } - - /* Taking care of word accesses */ - while ((destAddr & 0x0F) && (length > 3)) - { - if (!_FlashCtl_Program32(srcAddr, destAddr, mTries)) - { - goto FlashProgramCleanUp; - } else - { - srcAddr += 4; - destAddr += 4; - length -= 4; - } - } - - /* Taking care of burst programs */ - while (length > 16) - { - burstLength = length > 63 ? 64 : length & 0xFFFFFFF0; - - if (!_FlashCtl_ProgramBurst(srcAddr, destAddr, burstLength, mTries)) - { - goto FlashProgramCleanUp; - } else - { - srcAddr += burstLength; - destAddr += burstLength; - length -= burstLength; - } - } - - /* Remaining word accesses */ - while (length > 3) - { - if (!_FlashCtl_Program32(srcAddr, destAddr, mTries)) - { - goto FlashProgramCleanUp; - } else - { - srcAddr+=4; - destAddr+=4; - length-=4; - } - } - - /* Remaining byte accesses */ - while (length > 0) - { - if (!_FlashCtl_Program8(srcAddr, destAddr, mTries)) - { - goto FlashProgramCleanUp; - } else - { - srcAddr++; - destAddr++; - length--; - } - } - - /* If we got this far that means that we succeeded */ - res = true; - - FlashProgramCleanUp: - - if(intStatus == 0) - Interrupt_enableMaster(); - - FlashCtl_disableWordProgramming(); - return res; - -} -void FlashCtl_setProgramVerification(uint32_t verificationSetting) -{ - if ((verificationSetting & FLASH_BURSTPOST)) - BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS) = 1; - - if ((verificationSetting & FLASH_BURSTPRE)) - BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) = 1; - - if ((verificationSetting & FLASH_REGPRE)) - BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) = 1; - - if ((verificationSetting & FLASH_REGPOST)) - BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PST_OFS) = 1; -} - -void FlashCtl_clearProgramVerification(uint32_t verificationSetting) -{ - if ((verificationSetting & FLASH_BURSTPOST)) - BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS) = 0; - - if ((verificationSetting & FLASH_BURSTPRE)) - BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS) = 0; - - if ((verificationSetting & FLASH_REGPRE)) - BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PRE_OFS) = 0; - - if ((verificationSetting & FLASH_REGPOST)) - BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_VER_PST_OFS) = 0; - -} - -void FlashCtl_enableWordProgramming(uint32_t mode) -{ - if (mode == FLASH_IMMEDIATE_WRITE_MODE) - { - BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 1; - BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_MODE_OFS) = 0; - - } else if (mode == FLASH_COLLATED_WRITE_MODE) - { - BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 1; - BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_MODE_OFS) = 1; - } -} - -void FlashCtl_disableWordProgramming(void) -{ - BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_ENABLE_OFS) = 0; -} - -uint32_t FlashCtl_isWordProgrammingEnabled(void) -{ - if (!BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_ENABLE_OFS)) - { - return 0; - } else if (BITBAND_PERI(FLCTL->PRG_CTLSTAT, FLCTL_PRG_CTLSTAT_MODE_OFS)) - return FLASH_COLLATED_WRITE_MODE; - else - return FLASH_IMMEDIATE_WRITE_MODE; -} - -void FlashCtl_setWaitState(uint32_t flashBank, uint32_t waitState) -{ - if (flashBank == FLASH_BANK0) - { - FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL - & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | (waitState << FLCTL_BANK0_RDCTL_WAIT_OFS); - } else if (flashBank == FLASH_BANK1) - { - FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL - & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | (waitState << FLCTL_BANK1_RDCTL_WAIT_OFS); - } else - { - ASSERT(false); - } -} - -uint32_t FlashCtl_getWaitState(uint32_t flashBank) -{ - if (flashBank == FLASH_BANK0) - { - return (FLCTL->BANK0_RDCTL & FLCTL_BANK0_RDCTL_WAIT_MASK) >> FLCTL_BANK0_RDCTL_WAIT_OFS; - } else if (flashBank == FLASH_BANK1) - { - return (FLCTL->BANK1_RDCTL & FLCTL_BANK1_RDCTL_WAIT_MASK) >> FLCTL_BANK1_RDCTL_WAIT_OFS; - } else - { - ASSERT(false); - return 0; - } -} - -void FlashCtl_enableInterrupt(uint32_t flags) -{ - FLCTL->IE |= flags; -} - -void FlashCtl_disableInterrupt(uint32_t flags) -{ - FLCTL->IE &= ~flags; -} - -uint32_t FlashCtl_getInterruptStatus(void) -{ - return FLCTL->IFG; -} - -uint32_t FlashCtl_getEnabledInterruptStatus(void) -{ - return FlashCtl_getInterruptStatus() & FLCTL->IE; -} - -void FlashCtl_clearInterruptFlag(uint32_t flags) -{ - FLCTL->CLRIFG |= flags; -} - -void FlashCtl_registerInterrupt(void (*intHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - Interrupt_registerInterrupt(INT_FLCTL, intHandler); - - // - // Enable the system control interrupt. - // - Interrupt_enableInterrupt(INT_FLCTL); -} - -void FlashCtl_unregisterInterrupt(void) -{ - // - // Disable the interrupt. - // - Interrupt_disableInterrupt(INT_FLCTL); - - // - // Unregister the interrupt handler. - // - Interrupt_unregisterInterrupt(INT_FLCTL); -} - -uint8_t __FlashCtl_remaskData8Post(uint8_t data, uint32_t addr) -{ - uint32_t readMode, waitState, bankProgram, bankOneStart; - - /* Changing the waitstate and read mode of whichever bank we are in */ - /* Finding out which bank we are in */ - if(addr > SysCtl_getFlashSize()) - { - bankOneStart = __INFO_FLASH_TECH_MIDDLE__; - } - else - { - bankOneStart = SysCtl_getFlashSize() / 2; - } - - bankProgram = - addr < (bankOneStart) ? FLASH_BANK0 : FLASH_BANK1; - - /* Saving the current wait states and read mode */ - waitState = FlashCtl_getWaitState(bankProgram); - readMode = FlashCtl_getReadMode(bankProgram); - - /* Setting the wait state to account for the mode */ - FlashCtl_setWaitState(bankProgram, (2 * waitState) + 1); - - /* Changing to PROGRAM VERIFY mode */ - FlashCtl_setReadMode(bankProgram, FLASH_PROGRAM_VERIFY_READ_MODE); - - data = ~(~(data) & HWREG8(addr)); - - /* Setting the wait state to account for the mode */ - FlashCtl_setReadMode(bankProgram, readMode); - FlashCtl_setWaitState(bankProgram, waitState); - - return data; -} - -uint8_t __FlashCtl_remaskData8Pre(uint8_t data, uint32_t addr) -{ - uint32_t readMode, waitState, bankProgram, bankOneStart; - - /* Changing the waitstate and read mode of whichever bank we are in */ - /* Finding out which bank we are in */ - if(addr > SysCtl_getFlashSize()) - { - bankOneStart = __INFO_FLASH_TECH_MIDDLE__; - } - else - { - bankOneStart = SysCtl_getFlashSize() / 2; - } - - bankProgram = - addr < (bankOneStart) ? FLASH_BANK0 : FLASH_BANK1; - - /* Saving the current wait states and read mode */ - waitState = FlashCtl_getWaitState(bankProgram); - readMode = FlashCtl_getReadMode(bankProgram); - - /* Setting the wait state to account for the mode */ - FlashCtl_setWaitState(bankProgram, (2 * waitState) + 1); - - /* Changing to PROGRAM VERIFY mode */ - FlashCtl_setReadMode(bankProgram, FLASH_PROGRAM_VERIFY_READ_MODE); - - data |= ~(HWREG8(addr) | data); - - /* Setting the wait state to account for the mode */ - FlashCtl_setReadMode(bankProgram, readMode); - FlashCtl_setWaitState(bankProgram, waitState); - - return data; -} - -uint32_t __FlashCtl_remaskData32Post(uint32_t data, uint32_t addr) -{ - uint32_t bankProgramStart, bankProgramEnd, bank1Start; - uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode; - - /* Changing the waitstate and read mode of whichever bank we are in */ - /* Finding out which bank we are in */ - if(addr > SysCtl_getFlashSize()) - { - bank1Start = __INFO_FLASH_TECH_MIDDLE__; - } - else - { - bank1Start = SysCtl_getFlashSize() / 2; - } - - bankProgramStart = addr < bank1Start ? FLASH_BANK0 : FLASH_BANK1; - bankProgramEnd = (addr + 4) < bank1Start ? FLASH_BANK0 : FLASH_BANK1; - - /* Saving the current wait states and read mode */ - b0WaitState = FlashCtl_getWaitState(bankProgramStart); - b0ReadMode = FlashCtl_getReadMode(bankProgramStart); - FlashCtl_setWaitState(bankProgramStart, (2 * b0WaitState) + 1); - FlashCtl_setReadMode(bankProgramStart, FLASH_PROGRAM_VERIFY_READ_MODE); - - if (bankProgramStart != bankProgramEnd) - { - b1WaitState = FlashCtl_getWaitState(bankProgramEnd); - b1ReadMode = FlashCtl_getReadMode(bankProgramEnd); - FlashCtl_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1); - FlashCtl_setReadMode(bankProgramEnd, FLASH_PROGRAM_VERIFY_READ_MODE); - } - - data = ~(~(data) & HWREG32(addr)); - - /* Setting the wait state to account for the mode */ - FlashCtl_setReadMode(bankProgramStart, b0ReadMode); - FlashCtl_setWaitState(bankProgramStart, b0WaitState); - - if (bankProgramStart != bankProgramEnd) - { - FlashCtl_setReadMode(bankProgramEnd, b1ReadMode); - FlashCtl_setWaitState(bankProgramEnd, b1WaitState); - } - - return data; -} - -uint32_t __FlashCtl_remaskData32Pre(uint32_t data, uint32_t addr) -{ - uint32_t bankProgramStart, bankProgramEnd, bank1Start; - uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode; - - /* Changing the waitstate and read mode of whichever bank we are in */ - /* Finding out which bank we are in */ - if(addr > SysCtl_getFlashSize()) - { - bank1Start = __INFO_FLASH_TECH_MIDDLE__; - } - else - { - bank1Start = SysCtl_getFlashSize() / 2; - } - - bankProgramStart = addr < bank1Start ? FLASH_BANK0 : FLASH_BANK1; - bankProgramEnd = (addr + 4) < bank1Start ? FLASH_BANK0 : FLASH_BANK1; - - /* Saving the current wait states and read mode */ - b0WaitState = FlashCtl_getWaitState(bankProgramStart); - b0ReadMode = FlashCtl_getReadMode(bankProgramStart); - FlashCtl_setWaitState(bankProgramStart, (2 * b0WaitState) + 1); - FlashCtl_setReadMode(bankProgramStart, FLASH_PROGRAM_VERIFY_READ_MODE); - - if (bankProgramStart != bankProgramEnd) - { - b1WaitState = FlashCtl_getWaitState(bankProgramEnd); - b1ReadMode = FlashCtl_getReadMode(bankProgramEnd); - FlashCtl_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1); - FlashCtl_setReadMode(bankProgramEnd, FLASH_PROGRAM_VERIFY_READ_MODE); - } - - data |= ~(HWREG32(addr) | data); - - /* Setting the wait state to account for the mode */ - FlashCtl_setReadMode(bankProgramStart, b0ReadMode); - FlashCtl_setWaitState(bankProgramStart, b0WaitState); - - if (bankProgramStart != bankProgramEnd) - { - FlashCtl_setReadMode(bankProgramEnd, b1ReadMode); - FlashCtl_setWaitState(bankProgramEnd, b1WaitState); - } - - return data; -} - -void __FlashCtl_remaskBurstDataPre(uint32_t addr, uint32_t size) -{ - - uint32_t bankProgramStart, bankProgramEnd, bank1Start, ii; - uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode; - - /* Waiting for idle status */ - while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK) - != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0) - { - BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1; - } - - /* Changing the waitstate and read mode of whichever bank we are in */ - /* Finding out which bank we are in */ - if(addr > SysCtl_getFlashSize()) - { - bank1Start = __INFO_FLASH_TECH_MIDDLE__; - } - else - { - bank1Start = SysCtl_getFlashSize() / 2; - } - - bankProgramStart = addr < bank1Start ? FLASH_BANK0 : FLASH_BANK1; - bankProgramEnd = (addr + size) < bank1Start ? FLASH_BANK0 : FLASH_BANK1; - - /* Saving the current wait states and read mode */ - b0WaitState = FlashCtl_getWaitState(bankProgramStart); - b0ReadMode = FlashCtl_getReadMode(bankProgramStart); - FlashCtl_setWaitState(bankProgramStart, (2 * b0WaitState) + 1); - FlashCtl_setReadMode(bankProgramStart, FLASH_PROGRAM_VERIFY_READ_MODE); - - if (bankProgramStart != bankProgramEnd) - { - b1WaitState = FlashCtl_getWaitState(bankProgramEnd); - b1ReadMode = FlashCtl_getReadMode(bankProgramEnd); - FlashCtl_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1); - FlashCtl_setReadMode(bankProgramEnd, FLASH_PROGRAM_VERIFY_READ_MODE); - } - - /* Going through each BURST program register and masking out for pre - * verifcation - */ - size = (size / 4); - for (ii = 0; ii < size; ii++) - { - HWREG32(__getBurstProgramRegs[ii]) |= - ~(HWREG32(__getBurstProgramRegs[ii]) - | HWREG32(addr)); - addr += 4; - } - - /* Setting the wait state to account for the mode */ - FlashCtl_setReadMode(bankProgramStart, b0ReadMode); - FlashCtl_setWaitState(bankProgramStart, b0WaitState); - - if (bankProgramStart != bankProgramEnd) - { - FlashCtl_setReadMode(bankProgramEnd, b1ReadMode); - FlashCtl_setWaitState(bankProgramEnd, b1WaitState); - } - -} -void __FlashCtl_remaskBurstDataPost(uint32_t addr, uint32_t size) -{ - uint32_t bankProgramStart, bankProgramEnd, bank1Start, ii; - uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode; - - /* Waiting for idle status */ - while ((FLCTL->PRGBRST_CTLSTAT & FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK) - != FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0) - { - BITBAND_PERI(FLCTL->PRGBRST_CTLSTAT, - FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1; - } - - /* Changing the waitstate and read mode of whichever bank we are in */ - /* Finding out which bank we are in */ - if(addr > SysCtl_getFlashSize()) - { - bank1Start = __INFO_FLASH_TECH_MIDDLE__; - } - else - { - bank1Start = SysCtl_getFlashSize() / 2; - } - - bankProgramStart = addr < bank1Start ? FLASH_BANK0 : FLASH_BANK1; - bankProgramEnd = (addr + size) < bank1Start ? FLASH_BANK0 : FLASH_BANK1; - - /* Saving the current wait states and read mode */ - b0WaitState = FlashCtl_getWaitState(bankProgramStart); - b0ReadMode = FlashCtl_getReadMode(bankProgramStart); - FlashCtl_setWaitState(bankProgramStart, (2 * b0WaitState) + 1); - FlashCtl_setReadMode(bankProgramStart, FLASH_PROGRAM_VERIFY_READ_MODE); - - if (bankProgramStart != bankProgramEnd) - { - b1WaitState = FlashCtl_getWaitState(bankProgramEnd); - b1ReadMode = FlashCtl_getReadMode(bankProgramEnd); - FlashCtl_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1); - FlashCtl_setReadMode(bankProgramEnd, FLASH_PROGRAM_VERIFY_READ_MODE); - } - - /* Going through each BURST program register and masking out for post - * verifcation if needed - */ - size = (size / 4); - for (ii = 0; ii < size; ii++) - { - HWREG32(__getBurstProgramRegs[ii]) = ~(~(HWREG32( - __getBurstProgramRegs[ii])) & HWREG32(addr)); - - addr += 4; - } - - /* Setting the wait state to account for the mode */ - FlashCtl_setReadMode(bankProgramStart, b0ReadMode); - FlashCtl_setWaitState(bankProgramStart, b0WaitState); - - if (bankProgramStart != bankProgramEnd) - { - FlashCtl_setReadMode(bankProgramEnd, b1ReadMode); - FlashCtl_setWaitState(bankProgramEnd, b1WaitState); - } -} - -#endif /* __MCU_HAS_FLCTL__ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/flash.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/flash.h deleted file mode 100644 index 49ec582d165..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/flash.h +++ /dev/null @@ -1,944 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __FLASH_H__ -#define __FLASH_H__ - -#include -#include - -/* Define to ensure that our current MSP432 has the FLCTL module. This - definition is included in the device specific header file */ -#ifdef __MCU_HAS_FLCTL__ - -//***************************************************************************** -// -//! \addtogroup flash_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Control specific variables -// -//***************************************************************************** -#define FLASH_BURST_PRG_BIT 0x03 - -/* Interrupts */ -#define FLASH_PROGRAM_ERROR FLCTL_IFG_PRG_ERR -#define FLASH_BENCHMARK_INT FLCTL_IFG_BMRK -#define FLASH_ERASE_COMPLETE FLCTL_IFG_ERASE -#define FLASH_BRSTPRGM_COMPLETE FLCTL_IFG_PRGB -#define FLASH_WRDPRGM_COMPLETE FLCTL_IFG_PRG -#define FLASH_POSTVERIFY_FAILED FLCTL_IFG_AVPST -#define FLASH_PREVERIFY_FAILED FLCTL_IFG_AVPRE -#define FLASH_BRSTRDCMP_COMPLETE FLCTL_IFG_RDBRST - -#define FLASH_NORMAL_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_0 -#define FLASH_MARGIN0_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_1 -#define FLASH_MARGIN1_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_2 -#define FLASH_PROGRAM_VERIFY_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_3 -#define FLASH_ERASE_VERIFY_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_4 -#define FLASH_LEAKAGE_VERIFY_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_5 -#define FLASH_MARGIN0B_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_9 -#define FLASH_MARGIN1B_READ_MODE FLCTL_BANK0_RDCTL_RD_MODE_10 - -#define FLASH_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 - -#define FLASH_BANK0 0x00 -#define FLASH_BANK1 0x01 -#define FLASH_DATA_READ 0x00 -#define FLASH_INSTRUCTION_FETCH 0x01 - -#define FLASH_MAIN_MEMORY_SPACE_BANK0 0x01 -#define FLASH_MAIN_MEMORY_SPACE_BANK1 0x02 -#define FLASH_INFO_MEMORY_SPACE_BANK0 0x03 -#define FLASH_INFO_MEMORY_SPACE_BANK1 0x04 - -#define FLASH_MAIN_SPACE FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 -#define FLASH_INFO_SPACE FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 -#define FLASH_1_PATTERN FLCTL_RDBRST_CTLSTAT_DATA_CMP -#define FLASH_0_PATTERN 0x00 - -#define FLASH_SECTOR0 FLCTL_BANK0_MAIN_WEPROT_PROT0 -#define FLASH_SECTOR1 FLCTL_BANK0_MAIN_WEPROT_PROT1 -#define FLASH_SECTOR2 FLCTL_BANK0_MAIN_WEPROT_PROT2 -#define FLASH_SECTOR3 FLCTL_BANK0_MAIN_WEPROT_PROT3 -#define FLASH_SECTOR4 FLCTL_BANK0_MAIN_WEPROT_PROT4 -#define FLASH_SECTOR5 FLCTL_BANK0_MAIN_WEPROT_PROT5 -#define FLASH_SECTOR6 FLCTL_BANK0_MAIN_WEPROT_PROT6 -#define FLASH_SECTOR7 FLCTL_BANK0_MAIN_WEPROT_PROT7 -#define FLASH_SECTOR8 FLCTL_BANK0_MAIN_WEPROT_PROT8 -#define FLASH_SECTOR9 FLCTL_BANK0_MAIN_WEPROT_PROT9 -#define FLASH_SECTOR10 FLCTL_BANK0_MAIN_WEPROT_PROT10 -#define FLASH_SECTOR11 FLCTL_BANK0_MAIN_WEPROT_PROT11 -#define FLASH_SECTOR12 FLCTL_BANK0_MAIN_WEPROT_PROT12 -#define FLASH_SECTOR13 FLCTL_BANK0_MAIN_WEPROT_PROT13 -#define FLASH_SECTOR14 FLCTL_BANK0_MAIN_WEPROT_PROT14 -#define FLASH_SECTOR15 FLCTL_BANK0_MAIN_WEPROT_PROT15 -#define FLASH_SECTOR16 FLCTL_BANK0_MAIN_WEPROT_PROT16 -#define FLASH_SECTOR17 FLCTL_BANK0_MAIN_WEPROT_PROT17 -#define FLASH_SECTOR18 FLCTL_BANK0_MAIN_WEPROT_PROT18 -#define FLASH_SECTOR19 FLCTL_BANK0_MAIN_WEPROT_PROT19 -#define FLASH_SECTOR20 FLCTL_BANK0_MAIN_WEPROT_PROT20 -#define FLASH_SECTOR21 FLCTL_BANK0_MAIN_WEPROT_PROT21 -#define FLASH_SECTOR22 FLCTL_BANK0_MAIN_WEPROT_PROT22 -#define FLASH_SECTOR23 FLCTL_BANK0_MAIN_WEPROT_PROT23 -#define FLASH_SECTOR24 FLCTL_BANK0_MAIN_WEPROT_PROT24 -#define FLASH_SECTOR25 FLCTL_BANK0_MAIN_WEPROT_PROT25 -#define FLASH_SECTOR26 FLCTL_BANK0_MAIN_WEPROT_PROT26 -#define FLASH_SECTOR27 FLCTL_BANK0_MAIN_WEPROT_PROT27 -#define FLASH_SECTOR28 FLCTL_BANK0_MAIN_WEPROT_PROT28 -#define FLASH_SECTOR29 FLCTL_BANK0_MAIN_WEPROT_PROT29 -#define FLASH_SECTOR30 FLCTL_BANK0_MAIN_WEPROT_PROT30 -#define FLASH_SECTOR31 FLCTL_BANK0_MAIN_WEPROT_PROT31 - -#define FLASH_NOVER 0 -#define FLASH_BURSTPOST FLCTL_PRGBRST_CTLSTAT_AUTO_PST -#define FLASH_BURSTPRE FLCTL_PRGBRST_CTLSTAT_AUTO_PRE -#define FLASH_REGPRE FLCTL_PRG_CTLSTAT_VER_PRE -#define FLASH_REGPOST FLCTL_PRG_CTLSTAT_VER_PST -#define FLASH_FULLVER (FLCTL_PRGBRST_CTLSTAT_AUTO_PST | \ - FLCTL_PRGBRST_CTLSTAT_AUTO_PRE | FLCTL_PRG_CTLSTAT_VER_PRE \ - | FLCTL_PRG_CTLSTAT_VER_PST) - -#define FLASH_COLLATED_WRITE_MODE 0x01 -#define FLASH_IMMEDIATE_WRITE_MODE 0x02 - -#define __INFO_FLASH_TECH_START__ 0x00200000 -#define __INFO_FLASH_TECH_MIDDLE__ 0x00202000 - - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! Calculates the flash bank and sector number given an address. Stores the -//! results into the two pointers given as parameters. The user must provide -//! a valid memory address (an address in SRAM for example will give an invalid -//! result). -//! -//! \param addr Address to calculate the bank/sector information for -//! -//! \param bankNum The bank number will be stored in here after the function -//! completes. -//! -//! \param sectorNum The sector number will be stored in here after the function -//! completes. -//! -//! \note For simplicity, this API only works with address in MAIN flash memory. -//! For calculating the sector/bank number of an address in info memory, -//! please refer to your device datasheet/ -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_getMemoryInfo(uint32_t addr, uint32_t *bankNum, - uint32_t *sectorNum); - -//***************************************************************************** -// -//! Enables read buffering on accesses to a specified bank of flash memory -//! -//! \param memoryBank is the value of the memory bank to enable read -//! buffering. Must be only one of the following values: -//! - \b FLASH_BANK0, -//! - \b FLASH_BANK1 -//! -//! \param accessMethod is the value of the access type to enable read -//! buffering. Must be only one of the following values: -//! - \b FLASH_DATA_READ, -//! - \b FLASH_INSTRUCTION_FETCH -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_enableReadBuffering(uint_fast8_t memoryBank, - uint_fast8_t accessMethod); - -//***************************************************************************** -// -//! Disables read buffering on accesses to a specified bank of flash memory -//! -//! \param memoryBank is the value of the memory bank to disable read -//! buffering. Must be only one of the following values: -//! - \b FLASH_BANK0, -//! - \b FLASH_BANK1 -//! -//! \param accessMethod is the value of the access type to disable read -//! buffering. Must ne only one of the following values: -//! - \b FLASH_DATA_READ, -//! - \b FLASH_INSTRUCTION_FETCH -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_disableReadBuffering(uint_fast8_t memoryBank, - uint_fast8_t accessMethod); - -//***************************************************************************** -// -//! Disables program protection on the given sector mask. This setting can be -//! applied on a sector-wise bases on a given memory space (INFO or MAIN). -//! -//! \param memorySpace is the value of the memory bank to disable program -//! protection. Must be only one of the following values: -//! - \b FLASH_MAIN_MEMORY_SPACE_BANK0, -//! - \b FLASH_MAIN_MEMORY_SPACE_BANK1, -//! - \b FLASH_INFO_MEMORY_SPACE_BANK0, -//! - \b FLASH_INFO_MEMORY_SPACE_BANK1 -//! -//! \param sectorMask is a bit mask of the sectors to disable program -//! protection. Must be a bitfield of the following values: -//! - \b FLASH_SECTOR0, -//! - \b FLASH_SECTOR1, -//! - \b FLASH_SECTOR2, -//! - \b FLASH_SECTOR3, -//! - \b FLASH_SECTOR4, -//! - \b FLASH_SECTOR5, -//! - \b FLASH_SECTOR6, -//! - \b FLASH_SECTOR7, -//! - \b FLASH_SECTOR8, -//! - \b FLASH_SECTOR9, -//! - \b FLASH_SECTOR10, -//! - \b FLASH_SECTOR11, -//! - \b FLASH_SECTOR12, -//! - \b FLASH_SECTOR13, -//! - \b FLASH_SECTOR14, -//! - \b FLASH_SECTOR15, -//! - \b FLASH_SECTOR16, -//! - \b FLASH_SECTOR17, -//! - \b FLASH_SECTOR18, -//! - \b FLASH_SECTOR19, -//! - \b FLASH_SECTOR20, -//! - \b FLASH_SECTOR21, -//! - \b FLASH_SECTOR22, -//! - \b FLASH_SECTOR23, -//! - \b FLASH_SECTOR24, -//! - \b FLASH_SECTOR25, -//! - \b FLASH_SECTOR26, -//! - \b FLASH_SECTOR27, -//! - \b FLASH_SECTOR28, -//! - \b FLASH_SECTOR29, -//! - \b FLASH_SECTOR30, -//! - \b FLASH_SECTOR31 -//! -//! \note Flash sector sizes are 4KB and the number of sectors may vary -//! depending on the specific device. Also, for INFO memory space, only sectors -//! \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist. -//! -//! \note Not all devices will contain a dedicated INFO memory. Please check the -//! device datasheet to see if your device has INFO memory available for use. -//! For devices without INFO memory, any operation related to the INFO memory -//! will be ignored by the hardware. -//! -//! \return true if sector protection disabled false otherwise. -// -//***************************************************************************** -extern bool FlashCtl_unprotectSector(uint_fast8_t memorySpace, - uint32_t sectorMask); - -//***************************************************************************** -// -//! Enables program protection on the given sector mask. This setting can be -//! applied on a sector-wise bases on a given memory space (INFO or MAIN). -//! -//! \param memorySpace is the value of the memory bank to enable program -//! protection. Must be only one of the following values: -//! - \b FLASH_MAIN_MEMORY_SPACE_BANK0, -//! - \b FLASH_MAIN_MEMORY_SPACE_BANK1, -//! - \b FLASH_INFO_MEMORY_SPACE_BANK0, -//! - \b FLASH_INFO_MEMORY_SPACE_BANK1 -//! -//! \param sectorMask is a bit mask of the sectors to enable program -//! protection. Must be a bitfield of the following values: -//! - \b FLASH_SECTOR0, -//! - \b FLASH_SECTOR1, -//! - \b FLASH_SECTOR2, -//! - \b FLASH_SECTOR3, -//! - \b FLASH_SECTOR4, -//! - \b FLASH_SECTOR5, -//! - \b FLASH_SECTOR6, -//! - \b FLASH_SECTOR7, -//! - \b FLASH_SECTOR8, -//! - \b FLASH_SECTOR9, -//! - \b FLASH_SECTOR10, -//! - \b FLASH_SECTOR11, -//! - \b FLASH_SECTOR12, -//! - \b FLASH_SECTOR13, -//! - \b FLASH_SECTOR14, -//! - \b FLASH_SECTOR15, -//! - \b FLASH_SECTOR16, -//! - \b FLASH_SECTOR17, -//! - \b FLASH_SECTOR18, -//! - \b FLASH_SECTOR19, -//! - \b FLASH_SECTOR20, -//! - \b FLASH_SECTOR21, -//! - \b FLASH_SECTOR22, -//! - \b FLASH_SECTOR23, -//! - \b FLASH_SECTOR24, -//! - \b FLASH_SECTOR25, -//! - \b FLASH_SECTOR26, -//! - \b FLASH_SECTOR27, -//! - \b FLASH_SECTOR28, -//! - \b FLASH_SECTOR29, -//! - \b FLASH_SECTOR30, -//! - \b FLASH_SECTOR31 -//! -//! \note Flash sector sizes are 4KB and the number of sectors may vary -//! depending on the specific device. Also, for INFO memory space, only sectors -//! \b FLASH_SECTOR0 and \b FLASH_SECTOR1 will exist. -//! -//! \note Not all devices will contain a dedicated INFO memory. Please check the -//! device datasheet to see if your device has INFO memory available for use. -//! For devices without INFO memory, any operation related to the INFO memory -//! will be ignored by the hardware. -//! -//! \return true if sector protection enabled false otherwise. -// -//***************************************************************************** -extern bool FlashCtl_protectSector(uint_fast8_t memorySpace, - uint32_t sectorMask); - -//***************************************************************************** -// -//! Returns the sector protection for given sector mask and memory space -//! -//! \param memorySpace is the value of the memory bank to check for program -//! protection. Must be only one of the following values: -//! - \b FLASH_MAIN_MEMORY_SPACE_BANK0, -//! - \b FLASH_MAIN_MEMORY_SPACE_BANK1, -//! - \b FLASH_INFO_MEMORY_SPACE_BANK0, -//! - \b FLASH_INFO_MEMORY_SPACE_BANK1 -//! -//! \param sector is the sector to check for program protection. -//! Must be one of the following values: -//! - \b FLASH_SECTOR0, -//! - \b FLASH_SECTOR1, -//! - \b FLASH_SECTOR2, -//! - \b FLASH_SECTOR3, -//! - \b FLASH_SECTOR4, -//! - \b FLASH_SECTOR5, -//! - \b FLASH_SECTOR6, -//! - \b FLASH_SECTOR7, -//! - \b FLASH_SECTOR8, -//! - \b FLASH_SECTOR9, -//! - \b FLASH_SECTOR10, -//! - \b FLASH_SECTOR11, -//! - \b FLASH_SECTOR12, -//! - \b FLASH_SECTOR13, -//! - \b FLASH_SECTOR14, -//! - \b FLASH_SECTOR15, -//! - \b FLASH_SECTOR16, -//! - \b FLASH_SECTOR17, -//! - \b FLASH_SECTOR18, -//! - \b FLASH_SECTOR19, -//! - \b FLASH_SECTOR20, -//! - \b FLASH_SECTOR21, -//! - \b FLASH_SECTOR22, -//! - \b FLASH_SECTOR23, -//! - \b FLASH_SECTOR24, -//! - \b FLASH_SECTOR25, -//! - \b FLASH_SECTOR26, -//! - \b FLASH_SECTOR27, -//! - \b FLASH_SECTOR28, -//! - \b FLASH_SECTOR29, -//! - \b FLASH_SECTOR30, -//! - \b FLASH_SECTOR31 -//! -//! Note that flash sector sizes are 4KB and the number of sectors may vary -//! depending on the specific device. Also, for INFO memory space, only sectors -//! FLASH_SECTOR0 and FLASH_SECTOR1 will exist. -//! -//! \note Not all devices will contain a dedicated INFO memory. Please check the -//! device datasheet to see if your device has INFO memory available for use. -//! For devices without INFO memory, any operation related to the INFO memory -//! will be ignored by the hardware. -//! -//! \return true if sector protection enabled false otherwise. -// -//***************************************************************************** -extern bool FlashCtl_isSectorProtected(uint_fast8_t memorySpace, - uint32_t sector); - -//***************************************************************************** -// -//! Verifies a given segment of memory based off either a high (1) or low (0) -//! state. -//! -//! \param verifyAddr Start address where verification will begin -//! -//! \param length Length in bytes to verify based off the pattern -//! -//! \param pattern The pattern which verification will check versus. This can -//! either be a low pattern (each register will be checked versus a pattern -//! of 32 zeros, or a high pattern (each register will be checked versus a -//! pattern of 32 ones). Valid values are: FLASH_0_PATTERN, FLASH_1_PATTERN -//! -//! \note There are no sector/boundary restrictions for this function, -//! however it is encouraged to proved a start address aligned on 32-bit -//! boundaries. Providing an unaligned address will result in unaligned data -//! accesses and detriment efficiency. -//! -//! \note This function is blocking and will not exit until operation has -//! either completed or failed due to an error. Furthermore, given the -//! complex verification requirements of the flash controller, master -//! interrupts are disabled throughout execution of this function. The original -//! interrupt context is saved at the start of execution and restored prior -//! to exit of the API. -//! -//! \note Due to the hardware limitations of the flash controller, this -//! function cannot verify a memory address in the same flash bank that it -//! is executing from. If using the ROM version of this API (by using the -//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides -//! in flash then special care needs to be taken to ensure no code execution -//! or reads happen in the flash bank being programmed while this API is -//! being executed. -//! -//! \return true if memory verification is successful, false otherwise. -// -//***************************************************************************** -extern bool FlashCtl_verifyMemory(void* verifyAddr, uint32_t length, - uint_fast8_t pattern); - -//***************************************************************************** -// -//! Performs a mass erase on all unprotected flash sectors. Protected sectors -//! are ignored. -//! -//! \note This function is blocking and will not exit until operation has -//! either completed or failed due to an error. Furthermore, given the -//! complex verification requirements of the flash controller, master -//! interrupts are disabled throughout execution of this function. The original -//! interrupt context is saved at the start of execution and restored prior -//! to exit of the API. -//! -//! \note Due to the hardware limitations of the flash controller, this -//! function cannot erase a memory address in the same flash bank that it -//! is executing from. If using the ROM version of this API (by using the -//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides -//! in flash then special care needs to be taken to ensure no code execution -//! or reads happen in the flash bank being programmed while this API is -//! being executed. -//! -//! \return true if mass erase completes successfully, false otherwise -// -//***************************************************************************** -extern bool FlashCtl_performMassErase(void); - -//***************************************************************************** -// -//! Initiates a mass erase and returns control back to the program. This is a -//! non-blocking function, however it is the user's responsibility to perform -//! the necessary verification requirements after the interrupt is set to -//! signify completion. -//! -//! \return None -// -//***************************************************************************** -extern void FlashCtl_initiateMassErase(void); - -//***************************************************************************** -// -//! Erases a sector of MAIN or INFO flash memory. -//! -//! \param addr The start of the sector to erase. Note that with flash, -//! the minimum allowed size that can be erased is a flash sector -//! (which is 4KB on the MSP432 family). If an address is provided to -//! this function which is not on a 4KB boundary, the entire sector -//! will still be erased. -//! -//! \note This function is blocking and will not exit until operation has -//! either completed or failed due to an error. Furthermore, given the -//! complex verification requirements of the flash controller, master -//! interrupts are disabled throughout execution of this function. The original -//! interrupt context is saved at the start of execution and restored prior -//! to exit of the API. -//! -//! \note Due to the hardware limitations of the flash controller, this -//! function cannot erase a memory addressin the same flash bank that it -//! is executing from. If using the ROM version of this API (by using the -//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides -//! in flash then special care needs to be taken to ensure no code execution -//! or reads happen in the flash bank being programmed while this API is -//! being executed. -//! -//! \return true if sector erase is successful, false otherwise. -// -//***************************************************************************** -extern bool FlashCtl_eraseSector(uint32_t addr); - -//***************************************************************************** -// -//! Program a portion of flash memory with the provided data -//! -//! \param src Pointer to the data source to program into flash -//! -//! \param dest Pointer to the destination in flash to program -//! -//! \param length Length in bytes to program -//! -//! \note There are no sector/boundary restrictions for this function, -//! however it is encouraged to proved a start address aligned on 32-bit -//! boundaries. Providing an unaligned address will result in unaligned data -//! accesses and detriment efficiency. -//! -//! \note This function is blocking and will not exit until operation has -//! either completed or failed due to an error. Furthermore, given the -//! complex verification requirements of the flash controller, master -//! interrupts are disabled throughout execution of this function. The original -//! interrupt context is saved at the start of execution and restored prior -//! to exit of the API. -//! -//! \note Due to the hardware limitations of the flash controller, this -//! function cannot program a memory addressin the same flash bank that it -//! is executing from. If using the ROM version of this API (by using the -//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides -//! in flash then special care needs to be taken to ensure no code execution -//! or reads happen in the flash bank being programmed while this API is -//! being executed. -//! -//! \return Whether or not the program succeeded -// -//***************************************************************************** -extern bool FlashCtl_programMemory(void* src, void* dest, uint32_t length); - -//***************************************************************************** -// -//! Setups pre/post verification of burst and regular flash programming -//! instructions. Note that this API is for advanced users that are programming -//! their own flash drivers. The program/erase APIs are not affected by this -//! setting and take care of the verification requirements. -//! -//! \param verificationSetting Verification setting to set. This value can -//! be a bitwise OR of the following values: -//! - \b FLASH_BURSTPOST, -//! - \b FLASH_BURSTPRE, -//! - \b FLASH_REGPRE, -//! - \b FLASH_REGPOST -//! - \b FLASH_NOVER No verification enabled -//! - \b FLASH_FULLVER Full verification enabled -//! -//! \return none -// -//***************************************************************************** -extern void FlashCtl_setProgramVerification(uint32_t verificationSetting); - -//***************************************************************************** -// -//! Clears pre/post verification of burst and regular flash programming -//! instructions. Note that this API is for advanced users that are programming -//! their own flash drivers. The program/erase APIs are not affected by this -//! setting and take care of the verification requirements. -//! -//! \param verificationSetting Verification setting to clear. This value can -//! be a bitwise OR of the following values: -//! - \b FLASH_BURSTPOST, -//! - \b FLASH_BURSTPRE, -//! - \b FLASH_REGPRE, -//! - \b FLASH_REGPOST -//! - \b FLASH_NOVER No verification enabled -//! - \b FLASH_FULLVER Full verification enabled -//! -//! \return none -// -//***************************************************************************** -extern void FlashCtl_clearProgramVerification(uint32_t verificationSetting); - -//***************************************************************************** -// -//! Enables word programming of flash memory. -//! -//! This function will enable word programming of the flash memory and set the -//! mode of behavior when the flash write occurs. -//! -//! \param mode The mode specifies the behavior of the flash controller when -//! programming words to flash. In \b FLASH_IMMEDIATE_WRITE_MODE, the -//! program operation happens immediately on the write to flash while -//! in \b FLASH_COLLATED_WRITE_MODE the write will be delayed until a full -//! 128-bits have been collated. Possible values include: -//! - \b FLASH_IMMEDIATE_WRITE_MODE -//! - \b FLASH_COLLATED_WRITE_MODE -//! -//! -//! Refer to the user's guide for further documentation. -//! -//! \return none -// -//***************************************************************************** -extern void FlashCtl_enableWordProgramming(uint32_t mode); - -//***************************************************************************** -// -//! Disables word programming of flash memory. -//! -//! Refer to FlashCtl_enableWordProgramming and the user's guide for description -//! on the difference between full word and immediate programming -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_disableWordProgramming(void); - -//***************************************************************************** -// -//! Returns if word programming mode is enabled (and if it is, the specific mode) -//! -//! Refer to FlashCtl_enableWordProgramming and the user's guide for description -//! on the difference between full word and immediate programming -//! -//! \return a zero value if word programming is disabled, -//! - \b FLASH_IMMEDIATE_WRITE_MODE -//! - \b FLASH_COLLATED_WRITE_MODE -//! -// -//***************************************************************************** -extern uint32_t FlashCtl_isWordProgrammingEnabled(void); - -//***************************************************************************** -// -//! Sets the flash read mode to be used by default flash read operations. -//! Note that the proper wait states must be set prior to entering this -//! function. -//! -//! \param flashBank Flash bank to set read mode for. Valid values are: -//! - \b FLASH_BANK0 -//! - \b FLASH_BANK1 -//! -//! \param readMode The read mode to set. Valid values are: -//! - \b FLASH_NORMAL_READ_MODE, -//! - \b FLASH_MARGIN0_READ_MODE, -//! - \b FLASH_MARGIN1_READ_MODE, -//! - \b FLASH_PROGRAM_VERIFY_READ_MODE, -//! - \b FLASH_ERASE_VERIFY_READ_MODE, -//! - \b FLASH_LEAKAGE_VERIFY_READ_MODE, -//! - \b FLASH_MARGIN0B_READ_MODE, -//! - \b FLASH_MARGIN1B_READ_MODE -//! -//! \return None. -// -//***************************************************************************** -extern bool FlashCtl_setReadMode(uint32_t flashBank, uint32_t readMode); - -//***************************************************************************** -// -//! Gets the flash read mode to be used by default flash read operations. -//! -//! \param flashBank Flash bank to set read mode for. Valid values are: -//! - \b FLASH_BANK0 -//! - \b FLASH_BANK1 -//! -//! \return Returns the read mode to set. Valid values are: -//! - \b FLASH_NORMAL_READ_MODE, -//! - \b FLASH_MARGIN0_READ_MODE, -//! - \b FLASH_MARGIN1_READ_MODE, -//! - \b FLASH_PROGRAM_VERIFY_READ_MODE, -//! - \b FLASH_ERASE_VERIFY_READ_MODE, -//! - \b FLASH_LEAKAGE_VERIFY_READ_MODE, -//! - \b FLASH_MARGIN0B_READ_MODE, -//! - \b FLASH_MARGIN1B_READ_MODE -//! -// -//***************************************************************************** -extern uint32_t FlashCtl_getReadMode(uint32_t flashBank); - -//***************************************************************************** -// -//! Changes the number of wait states that are used by the flash controller -//! for read operations. When changing frequency ranges of the clock, this -//! functions must be used in order to allow for readable flash memory. -//! -//! \param waitState The number of wait states to set. Note that only -//! bits 0-3 are used. -//! -//! \param flashBank Flash bank to set wait state for. Valid values are: -//! - \b FLASH_BANK0 -//! - \b FLASH_BANK1 -//! -// -//***************************************************************************** -extern void FlashCtl_setWaitState(uint32_t bank, uint32_t waitState); - -//***************************************************************************** -// -//! Returns the set number of flash wait states for the given flash bank. -//! -//! \param flashBank Flash bank to set wait state for. Valid values are: -//! - \b FLASH_BANK0 -//! - \b FLASH_BANK1 -//! -//! \return The wait state setting for the specified flash bank -// -//***************************************************************************** -extern uint32_t FlashCtl_getWaitState(uint32_t bank); - -//***************************************************************************** -// -//! Enables individual flash control interrupt sources. -//! -//! \param flags is a bit mask of the interrupt sources to be enabled. Must -//! be a logical OR of: -//! - \b FLASH_PROGRAM_ERROR, -//! - \b FLASH_BENCHMARK_INT, -//! - \b FLASH_ERASE_COMPLETE, -//! - \b FLASH_BRSTPRGM_COMPLETE, -//! - \b FLASH_WRDPRGM_COMPLETE, -//! - \b FLASH_POSTVERIFY_FAILED, -//! - \b FLASH_PREVERIFY_FAILED, -//! - \b FLASH_BRSTRDCMP_COMPLETE -//! -//! This function enables the indicated flash system interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_enableInterrupt(uint32_t flags); - -//***************************************************************************** -// -//! Disables individual flash system interrupt sources. -//! -//! \param flags is a bit mask of the interrupt sources to be disabled. Must -//! be a logical OR of: -//! - \b FLASH_PROGRAM_ERROR, -//! - \b FLASH_BENCHMARK_INT, -//! - \b FLASH_ERASE_COMPLETE, -//! - \b FLASH_BRSTPRGM_COMPLETE, -//! - \b FLASH_WRDPRGM_COMPLETE, -//! - \b FLASH_POSTVERIFY_FAILED, -//! - \b FLASH_PREVERIFY_FAILED, -//! - \b FLASH_BRSTRDCMP_COMPLETE -//! -//! This function disables the indicated flash system interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_disableInterrupt(uint32_t flags); - -//***************************************************************************** -// -//! Gets the current interrupt status masked with the enabled interrupts. -//! This function is useful to call in ISRs to get a list -//! of pending interrupts that are actually enabled and could have caused the -//! ISR. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! - \b FLASH_PROGRAM_ERROR, -//! - \b FLASH_BENCHMARK_INT, -//! - \b FLASH_ERASE_COMPLETE, -//! - \b FLASH_BRSTPRGM_COMPLETE, -//! - \b FLASH_WRDPRGM_COMPLETE, -//! - \b FLASH_POSTVERIFY_FAILED, -//! - \b FLASH_PREVERIFY_FAILED, -//! - \b FLASH_BRSTRDCMP_COMPLETE -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -// -//***************************************************************************** -extern uint32_t FlashCtl_getEnabledInterruptStatus(void); - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \return The current interrupt status, enumerated as a bit field of: -//! - \b FLASH_PROGRAM_ERROR, -//! - \b FLASH_BENCHMARK_INT, -//! - \b FLASH_ERASE_COMPLETE, -//! - \b FLASH_BRSTPRGM_COMPLETE, -//! - \b FLASH_WRDPRGM_COMPLETE, -//! - \b FLASH_POSTVERIFY_FAILED, -//! - \b FLASH_PREVERIFY_FAILED, -//! - \b FLASH_BRSTRDCMP_COMPLETE -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -// -//***************************************************************************** -extern uint32_t FlashCtl_getInterruptStatus(void); - -//***************************************************************************** -// -//! Clears flash system interrupt sources. -//! -//! \param flags is a bit mask of the interrupt sources to be cleared. Must -//! be a logical OR of: -//! - \b FLASH_PROGRAM_ERROR, -//! - \b FLASH_BENCHMARK_INT, -//! - \b FLASH_ERASE_COMPLETE, -//! - \b FLASH_BRSTPRGM_COMPLETE, -//! - \b FLASH_WRDPRGM_COMPLETE, -//! - \b FLASH_POSTVERIFY_FAILED, -//! - \b FLASH_PREVERIFY_FAILED, -//! - \b FLASH_BRSTRDCMP_COMPLETE -//! -//! The specified flash system interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep it from being called again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_clearInterruptFlag(uint32_t flags); - -//***************************************************************************** -// -//! Registers an interrupt handler for flash clock system interrupt. -//! -//! \param intHandler is a pointer to the function to be called when the clock -//! system interrupt occurs. -//! -//! This function registers the handler to be called when a clock system -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific flash controller interrupts must be enabled -//! via FlashCtl_enableInterrupt(). It is the interrupt handler's -//! responsibility to clear the interrupt source via -//! FlashCtl_clearInterruptFlag(). -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_registerInterrupt(void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the flash system. -//! -//! This function unregisters the handler to be called when a clock system -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_unregisterInterrupt(void); - - -//***************************************************************************** -// -//! Initiates a sector erase of MAIN or INFO flash memory. Note that this -//! function simply initaites the sector erase, but does no verification -//! which is required by the flash controller. The user must manually set -//! and enable interrupts on the flash controller to fire on erase completion -//! and then use the FlashCtl_verifyMemory function to verify that the sector -//! was actually erased -//! -//! \param addr The start of the sector to erase. Note that with flash, -//! the minimum allowed size that can be erased is a flash sector -//! (which is 4KB on the MSP432 family). If an address is provided to -//! this function which is not on a 4KB boundary, the entire sector -//! will still be erased. -//! -//! \return None -// -//***************************************************************************** -extern void FlashCtl_initiateSectorErase(uint32_t addr); - - -/* The following functions are advanced functions that are used by the flash - * driver to remask a failed bit in the event of a post or pre verification - * failure. They are meant to be advanced functions and should not be used - * by the majority of users (unless you are writing your own flash driver). - */ -extern uint8_t __FlashCtl_remaskData8Post(uint8_t data, uint32_t addr); -extern uint8_t __FlashCtl_remaskData8Pre(uint8_t data, uint32_t addr); -extern uint32_t __FlashCtl_remaskData32Post(uint32_t data, uint32_t addr); -extern uint32_t __FlashCtl_remaskData32Pre(uint32_t data, uint32_t addr); -extern void __FlashCtl_remaskBurstDataPost(uint32_t addr, uint32_t size); -extern void __FlashCtl_remaskBurstDataPre(uint32_t addr, uint32_t size); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* __MCU_HAS_FLCTL__ */ - -#endif // __FLASH_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/flash_a.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/flash_a.c deleted file mode 100644 index 6886b436102..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/flash_a.c +++ /dev/null @@ -1,1777 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/* Standard Includes */ -#include - -/* DriverLib Includes */ -#include -#include -#include -#include -#include -#include - -/* Define to ensure that our current MSP432 has the FLCTL_A module. This - definition is included in the device specific header file */ -#ifdef __MCU_HAS_FLCTL_A__ - -static const uint32_t MAX_ERASE_NO_TLV = 50; -static const uint32_t MAX_PROGRAM_NO_TLV = 5; - -static const uint32_t __getBurstProgramRegs[16] = -{ (uint32_t)&FLCTL_A->PRGBRST_DATA0_0, (uint32_t)&FLCTL_A->PRGBRST_DATA0_1, - (uint32_t) &FLCTL_A->PRGBRST_DATA0_2, (uint32_t)&FLCTL_A->PRGBRST_DATA0_3, - (uint32_t)&FLCTL_A->PRGBRST_DATA1_0,(uint32_t) &FLCTL_A->PRGBRST_DATA1_1, - (uint32_t)&FLCTL_A->PRGBRST_DATA1_2, (uint32_t)&FLCTL_A->PRGBRST_DATA1_3, - (uint32_t) &FLCTL_A->PRGBRST_DATA2_0, (uint32_t)&FLCTL_A->PRGBRST_DATA2_1, - (uint32_t)&FLCTL_A->PRGBRST_DATA2_2,(uint32_t) &FLCTL_A->PRGBRST_DATA2_3, - (uint32_t) &FLCTL_A->PRGBRST_DATA3_0,(uint32_t) &FLCTL_A->PRGBRST_DATA3_1, - (uint32_t) &FLCTL_A->PRGBRST_DATA3_2,(uint32_t) &FLCTL_A->PRGBRST_DATA3_3 }; - -static void __saveProtectionRegisters(__FlashCtl_ProtectionRegister *pReg) -{ - pReg->B0_INFO_R0 = FLCTL_A->BANK0_INFO_WEPROT; - pReg->B1_INFO_R0 = FLCTL_A->BANK1_INFO_WEPROT; - pReg->B0_MAIN_R0 = FLCTL_A->BANK0_MAIN_WEPROT0; - pReg->B0_MAIN_R1 = FLCTL_A->BANK0_MAIN_WEPROT1; - pReg->B0_MAIN_R2 = FLCTL_A->BANK0_MAIN_WEPROT2; - pReg->B0_MAIN_R3 = FLCTL_A->BANK0_MAIN_WEPROT3; - pReg->B0_MAIN_R4 = FLCTL_A->BANK0_MAIN_WEPROT4; - pReg->B0_MAIN_R5 = FLCTL_A->BANK0_MAIN_WEPROT5; - pReg->B0_MAIN_R6 = FLCTL_A->BANK0_MAIN_WEPROT6; - pReg->B0_MAIN_R7 = FLCTL_A->BANK0_MAIN_WEPROT7; - pReg->B1_MAIN_R0 = FLCTL_A->BANK1_MAIN_WEPROT0; - pReg->B1_MAIN_R1 = FLCTL_A->BANK1_MAIN_WEPROT1; - pReg->B1_MAIN_R2 = FLCTL_A->BANK1_MAIN_WEPROT2; - pReg->B1_MAIN_R3 = FLCTL_A->BANK1_MAIN_WEPROT3; - pReg->B1_MAIN_R4 = FLCTL_A->BANK1_MAIN_WEPROT4; - pReg->B1_MAIN_R5 = FLCTL_A->BANK1_MAIN_WEPROT5; - pReg->B1_MAIN_R6 = FLCTL_A->BANK1_MAIN_WEPROT6; - pReg->B1_MAIN_R7 = FLCTL_A->BANK1_MAIN_WEPROT7; -} - -static void __restoreProtectionRegisters(__FlashCtl_ProtectionRegister *pReg) -{ - FLCTL_A->BANK0_INFO_WEPROT = pReg->B0_INFO_R0; - FLCTL_A->BANK1_INFO_WEPROT = pReg->B1_INFO_R0; - FLCTL_A->BANK0_MAIN_WEPROT0 = pReg->B0_MAIN_R0; - FLCTL_A->BANK0_MAIN_WEPROT1 = pReg->B0_MAIN_R1; - FLCTL_A->BANK0_MAIN_WEPROT2 = pReg->B0_MAIN_R2; - FLCTL_A->BANK0_MAIN_WEPROT3 = pReg->B0_MAIN_R3; - FLCTL_A->BANK0_MAIN_WEPROT4 = pReg->B0_MAIN_R4; - FLCTL_A->BANK0_MAIN_WEPROT5 = pReg->B0_MAIN_R5; - FLCTL_A->BANK0_MAIN_WEPROT6 = pReg->B0_MAIN_R6; - FLCTL_A->BANK0_MAIN_WEPROT7 = pReg->B0_MAIN_R7; - FLCTL_A->BANK1_MAIN_WEPROT0 = pReg->B1_MAIN_R0; - FLCTL_A->BANK1_MAIN_WEPROT1 = pReg->B1_MAIN_R1; - FLCTL_A->BANK1_MAIN_WEPROT2 = pReg->B1_MAIN_R2; - FLCTL_A->BANK1_MAIN_WEPROT3 = pReg->B1_MAIN_R3; - FLCTL_A->BANK1_MAIN_WEPROT4 = pReg->B1_MAIN_R4; - FLCTL_A->BANK1_MAIN_WEPROT5 = pReg->B1_MAIN_R5; - FLCTL_A->BANK1_MAIN_WEPROT6 = pReg->B1_MAIN_R6; - FLCTL_A->BANK1_MAIN_WEPROT7 = pReg->B1_MAIN_R7; -} - -void FlashCtl_A_getMemoryInfo(uint32_t addr, uint32_t *bankNum, - uint32_t *sectorNum) -{ - uint32_t bankLimit; - - bankLimit = SysCtl_A_getFlashSize() / 2; - - if (addr > bankLimit) - { - *(bankNum) = FLASH_A_BANK1; - addr = (addr - bankLimit); - } else - { - *(bankNum) = FLASH_A_BANK0; - } - - *(sectorNum) = (addr) / FLASH_A_SECTOR_SIZE; -} - -static bool _FlashCtl_A_Program8(uint32_t src, uint32_t dest, uint32_t mTries) -{ - uint32_t ii; - uint8_t data; - - /* Enabling the correct verification settings */ - FlashCtl_A_setProgramVerification(FLASH_A_REGPRE | FLASH_A_REGPOST); - FlashCtl_A_clearProgramVerification(FLASH_A_BURSTPOST | FLASH_A_BURSTPRE); - - data = HWREG8(src); - - for (ii = 0; ii < mTries; ii++) - { - /* Clearing flags */ - FLCTL_A->CLRIFG |= (FLASH_A_PROGRAM_ERROR | FLASH_A_POSTVERIFY_FAILED - | FLASH_A_PREVERIFY_FAILED | FLASH_A_WRDPRGM_COMPLETE); - - HWREG8(dest) = data; - - while (!(FlashCtl_A_getInterruptStatus() & FLASH_A_WRDPRGM_COMPLETE)) - { - __no_operation(); - } - - /* Pre-Verify */ - if ((BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_VER_PRE_OFS) - && BITBAND_PERI(FLCTL_A->IFG, FLCTL_A_IFG_AVPRE_OFS))) - { - data = __FlashCtl_A_remaskData8Pre(data, dest); - - if (data != 0xFF) - { - FlashCtl_A_clearProgramVerification(FLASH_A_REGPRE); - continue; - } - - } - - /* Post Verify */ - if ((BITBAND_PERI(FLCTL_A->IFG, FLCTL_A_IFG_AVPST_OFS))) - { - data = __FlashCtl_A_remaskData8Post(data, dest); - - /* Seeing if we actually need to do another pulse */ - if (data == 0xFF) - return true; - - FlashCtl_A_setProgramVerification(FLASH_A_REGPRE | FLASH_A_REGPOST); - continue; - } - - /* If we got this far, return true */ - return true; - - } - - return false; - -} - -static bool _FlashCtl_A_Program32(uint32_t src, uint32_t dest, uint32_t mTries) -{ - uint32_t ii; - uint32_t data; - - /* Enabling the correct verification settings */ - FlashCtl_A_setProgramVerification(FLASH_A_REGPRE | FLASH_A_REGPOST); - FlashCtl_A_clearProgramVerification(FLASH_A_BURSTPOST | FLASH_A_BURSTPRE); - - data = HWREG32(src); - - for (ii = 0; ii < mTries; ii++) - { - /* Clearing flags */ - FLCTL_A->CLRIFG |= (FLASH_A_PROGRAM_ERROR | FLASH_A_POSTVERIFY_FAILED - | FLASH_A_PREVERIFY_FAILED | FLASH_A_WRDPRGM_COMPLETE); - - HWREG32(dest) = data; - - while (!(FlashCtl_A_getInterruptStatus() & FLASH_A_WRDPRGM_COMPLETE)) - { - __no_operation(); - } - - /* Pre-Verify */ - if ((BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_VER_PRE_OFS) - && BITBAND_PERI(FLCTL_A->IFG, FLCTL_A_IFG_AVPRE_OFS))) - { - data = __FlashCtl_A_remaskData32Pre(data, dest); - - if (data != 0xFFFFFFFF) - { - - FlashCtl_A_clearProgramVerification(FLASH_A_REGPRE); - continue; - } - - } - - /* Post Verify */ - if ((BITBAND_PERI(FLCTL_A->IFG, FLCTL_A_IFG_AVPST_OFS))) - { - data = __FlashCtl_A_remaskData32Post(data, dest); - - /* Seeing if we actually need to do another pulse */ - if (data == 0xFFFFFFFF) - return true; - - FlashCtl_A_setProgramVerification(FLASH_A_REGPRE | FLASH_A_REGPOST); - continue; - } - - /* If we got this far, return true */ - return true; - - } - - return false; - -} - -static bool _FlashCtl_A_ProgramBurst(uint32_t src, uint32_t dest, - uint32_t length, uint32_t mTries) -{ - uint32_t bCalc, otpOffset, ii, jj; - bool res; - - /* Setting verification */ - FlashCtl_A_clearProgramVerification(FLASH_A_REGPRE | FLASH_A_REGPOST); - FlashCtl_A_setProgramVerification(FLASH_A_BURSTPOST | FLASH_A_BURSTPRE); - - /* Assume Failure */ - res = false; - - /* Waiting for idle status */ - while ((FLCTL_A->PRGBRST_CTLSTAT & FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK) - != FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_0) - { - BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1; - } - - /* Setting/clearing INFO flash flags as appropriate */ - if (dest >= SysCtl_A_getFlashSize()) - { - FLCTL_A->PRGBRST_CTLSTAT = (FLCTL_A->PRGBRST_CTLSTAT - & ~FLCTL_A_PRGBRST_CTLSTAT_TYPE_MASK) - | FLCTL_A_PRGBRST_CTLSTAT_TYPE_1; - otpOffset = __INFO_FLASH_A_TECH_START__; - } else - { - FLCTL_A->PRGBRST_CTLSTAT = (FLCTL_A->PRGBRST_CTLSTAT - & ~FLCTL_A_PRGBRST_CTLSTAT_TYPE_MASK) - | FLCTL_A_PRGBRST_CTLSTAT_TYPE_0; - otpOffset = 0; - } - - bCalc = 0; - FLCTL_A->PRGBRST_STARTADDR = (dest - otpOffset); - - /* Initially populating the burst registers */ - while (bCalc < 16 && length != 0) - { - HWREG32(__getBurstProgramRegs[bCalc]) = HWREG32(src); - bCalc++; - length -= 4; - src += 4; - } - - for (ii = 0; ii < mTries; ii++) - { - /* Clearing Flags */ - FLCTL_A->CLRIFG |= (FLASH_A_BRSTPRGM_COMPLETE - | FLASH_A_POSTVERIFY_FAILED | FLASH_A_PREVERIFY_FAILED); - - /* Waiting for idle status */ - while ((FLCTL_A->PRGBRST_CTLSTAT - & FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK) - != FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_0) - { - BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1; - } - - /* Start the burst program */ - FLCTL_A->PRGBRST_CTLSTAT = (FLCTL_A->PRGBRST_CTLSTAT - & ~(FLCTL_A_PRGBRST_CTLSTAT_LEN_MASK)) - | ((bCalc / 4) << FLASH_A_BURST_PRG_BIT) - | FLCTL_A_PRGBRST_CTLSTAT_START; - - /* Waiting for the burst to complete */ - while ((FLCTL_A->PRGBRST_CTLSTAT - & FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK) - != FLASH_A_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE) - { - __no_operation(); - } - - /* Checking for errors and clearing/masking */ - - /* Address Error */ - if (BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR_OFS)) - { - goto BurstCleanUp; - } - - /* Pre-Verify Error */ - if (BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE_OFS) - && BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR_OFS)) - { - __FlashCtl_A_remaskBurstDataPre(dest, bCalc * 4); - - for (jj = 0; jj < bCalc; jj++) - { - if (HWREG32(__getBurstProgramRegs[jj]) != 0xFFFFFFFF) - { - FlashCtl_A_clearProgramVerification(FLASH_A_BURSTPRE); - break; - } - } - - if (jj != bCalc) - continue; - } - - /* Post-Verify Error */ - if (BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_PST_ERR_OFS)) - { - __FlashCtl_A_remaskBurstDataPost(dest, bCalc * 4); - - for (jj = 0; jj < bCalc; jj++) - { - if ((HWREG32(__getBurstProgramRegs[jj])) != 0xFFFFFFFF) - { - FlashCtl_A_setProgramVerification( - FLASH_A_BURSTPOST | FLASH_A_BURSTPRE); - break; - } - } - - if (jj != bCalc) - continue; - - } - - /* If we got this far, the program happened */ - res = true; - goto BurstCleanUp; - } - - BurstCleanUp: - /* Waiting for idle status */ - while ((FLCTL_A->PRGBRST_CTLSTAT & FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK) - != FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_0) - { - BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1; - } - return res; -} - -void FlashCtl_A_enableReadBuffering(uint_fast8_t memoryBank, - uint_fast8_t accessMethod) -{ - if (memoryBank == FLASH_A_BANK0 && accessMethod == FLASH_A_DATA_READ) - BITBAND_PERI(FLCTL_A->BANK0_RDCTL, FLCTL_A_BANK0_RDCTL_BUFD_OFS) = 1; - else if (memoryBank == FLASH_A_BANK1 && accessMethod == FLASH_A_DATA_READ) - BITBAND_PERI(FLCTL_A->BANK1_RDCTL, FLCTL_A_BANK1_RDCTL_BUFD_OFS) = 1; - else if (memoryBank == FLASH_A_BANK0 - && accessMethod == FLASH_A_INSTRUCTION_FETCH) - BITBAND_PERI(FLCTL_A->BANK0_RDCTL, FLCTL_A_BANK0_RDCTL_BUFI_OFS) = 1; - else if (memoryBank == FLASH_A_BANK1 - && accessMethod == FLASH_A_INSTRUCTION_FETCH) - BITBAND_PERI(FLCTL_A->BANK1_RDCTL, FLCTL_A_BANK1_RDCTL_BUFI_OFS) = 1; - else - ASSERT(false); -} - -void FlashCtl_A_disableReadBuffering(uint_fast8_t memoryBank, - uint_fast8_t accessMethod) -{ - if (memoryBank == FLASH_A_BANK0 && accessMethod == FLASH_A_DATA_READ) - BITBAND_PERI(FLCTL_A->BANK0_RDCTL, FLCTL_A_BANK0_RDCTL_BUFD_OFS) = 0; - else if (memoryBank == FLASH_A_BANK1 && accessMethod == FLASH_A_DATA_READ) - BITBAND_PERI(FLCTL_A->BANK1_RDCTL, FLCTL_A_BANK1_RDCTL_BUFD_OFS) = 0; - else if (memoryBank == FLASH_A_BANK0 - && accessMethod == FLASH_A_INSTRUCTION_FETCH) - BITBAND_PERI(FLCTL_A->BANK0_RDCTL, FLCTL_A_BANK0_RDCTL_BUFI_OFS) = 0; - else if (memoryBank == FLASH_A_BANK1 - && accessMethod == FLASH_A_INSTRUCTION_FETCH) - BITBAND_PERI(FLCTL_A->BANK1_RDCTL, FLCTL_A_BANK1_RDCTL_BUFI_OFS) = 0; - else - ASSERT(false); -} - -bool FlashCtl_A_isMemoryProtected(uint32_t addr) -{ - volatile uint32_t *configRegister; - uint32_t memoryBit, cutOffMemory; - - if (addr >= SysCtl_A_getFlashSize()) - { - cutOffMemory = (SysCtl_A_getInfoFlashSize() >> 1) + __INFO_FLASH_A_TECH_START__; - - if (addr < cutOffMemory) - { - memoryBit = (addr - __INFO_FLASH_A_TECH_START__) - / FLASH_A_SECTOR_SIZE; - configRegister = &FLCTL_A->BANK0_INFO_WEPROT - + ((memoryBit >> 5)); - memoryBit &= 0x1F; - } else - { - memoryBit = (addr - cutOffMemory) / FLASH_A_SECTOR_SIZE; - configRegister = &FLCTL_A->BANK1_INFO_WEPROT - + ((memoryBit >> 5)); - memoryBit &= 0x1F; - } - } else - { - cutOffMemory = SysCtl_A_getFlashSize() >> 1; - - if (addr < cutOffMemory) - { - memoryBit = addr / FLASH_A_SECTOR_SIZE; - configRegister = &FLCTL_A->BANK0_MAIN_WEPROT0 - + ((memoryBit >> 5)); - memoryBit &= 0x1F; - } else - { - memoryBit = (addr - cutOffMemory) / FLASH_A_SECTOR_SIZE; - configRegister = &FLCTL_A->BANK1_MAIN_WEPROT0 - + ((memoryBit >> 5)); - memoryBit &= 0x1F; - } - } - - return (*configRegister & (1 << memoryBit)); -} - -bool FlashCtl_A_isMemoryRangeProtected(uint32_t startAddr, uint32_t endAddr) -{ - uint32_t ii; - - if (startAddr > endAddr) - return false; - - startAddr = (startAddr & 0xFFFFF000); - endAddr = (endAddr & 0xFFFFF000); - - for (ii = startAddr; ii <= endAddr; ii+=FLASH_A_SECTOR_SIZE) - { - if (!FlashCtl_A_isMemoryProtected(ii)) - return false; - } - return true; -} - -bool FlashCtl_A_unprotectMemory(uint32_t startAddr, uint32_t endAddr) -{ - uint32_t startBankBit, endBankBit, cutOffMemory; - volatile uint32_t* baseStartConfig, *baseEndConfig; - - if (startAddr > endAddr) - return false; - - if (endAddr >= SysCtl_A_getFlashSize()) - { - cutOffMemory = (SysCtl_A_getInfoFlashSize() >> 1) - + __INFO_FLASH_A_TECH_START__; - - if (endAddr < cutOffMemory && startAddr < cutOffMemory) - { - startBankBit = (startAddr - __INFO_FLASH_A_TECH_START__) - / FLASH_A_SECTOR_SIZE; - endBankBit = (endAddr - __INFO_FLASH_A_TECH_START__) - / FLASH_A_SECTOR_SIZE; - FLCTL_A->BANK0_INFO_WEPROT &= ~(0xFFFFFFFF >> (31 - endBankBit)) - & (0xFFFFFFFF << startBankBit); - } else if (endAddr > cutOffMemory && startAddr > cutOffMemory) - { - startBankBit = (startAddr - cutOffMemory) / FLASH_A_SECTOR_SIZE; - endBankBit = (endAddr - cutOffMemory) / FLASH_A_SECTOR_SIZE; - FLCTL_A->BANK1_INFO_WEPROT &= ~((0xFFFFFFFF >> (31 - endBankBit)) - & (0xFFFFFFFF << startBankBit)); - } else - { - startBankBit = (startAddr - __INFO_FLASH_A_TECH_START__) - / FLASH_A_SECTOR_SIZE; - endBankBit = (endAddr - cutOffMemory)/FLASH_A_SECTOR_SIZE; - FLCTL_A->BANK0_INFO_WEPROT &= ~(0xFFFFFFFF << startBankBit) & 0xF; - FLCTL_A->BANK1_INFO_WEPROT &= ~(0xFFFFFFFF >> (31 - (endBankBit))) & 0xF; - } - - return true; - - } else - { - cutOffMemory = SysCtl_A_getFlashSize() >> 1; - - if (endAddr < cutOffMemory) - { - endBankBit = endAddr / FLASH_A_SECTOR_SIZE; - baseEndConfig = &FLCTL_A->BANK0_MAIN_WEPROT0 - + ((endBankBit >> 5)); - endBankBit &= 0x1F; - } else - { - endBankBit = (endAddr - cutOffMemory) / FLASH_A_SECTOR_SIZE; - baseEndConfig = &FLCTL_A->BANK1_MAIN_WEPROT0 - + (endBankBit >> 5); - endBankBit &= 0x1F; - } - - if (startAddr < cutOffMemory) - { - startBankBit = (startAddr / FLASH_A_SECTOR_SIZE); - baseStartConfig = &FLCTL_A->BANK0_MAIN_WEPROT0 - + (startBankBit >> 5); - startBankBit &= 0x1F; - } else - { - startBankBit = (startAddr - cutOffMemory) / FLASH_A_SECTOR_SIZE; - baseStartConfig = &FLCTL_A->BANK1_MAIN_WEPROT0 - + (startBankBit >> 5); - startBankBit &= 0x1F; - } - - if (baseStartConfig == baseEndConfig) - { - (*baseStartConfig) &= ~((0xFFFFFFFF >> (31 - endBankBit)) - & (0xFFFFFFFF << startBankBit)); - return true; - } - - *baseStartConfig &= ~(0xFFFFFFFF << startBankBit); - - if (baseStartConfig == &FLCTL_A->BANK0_MAIN_WEPROT7) - { - baseStartConfig = &FLCTL_A->BANK1_MAIN_WEPROT0; - } else - { - baseStartConfig++; - } - - while (baseStartConfig != baseEndConfig) - { - *baseStartConfig = 0; - - if (baseStartConfig == &FLCTL_A->BANK0_MAIN_WEPROT7) - { - baseStartConfig = &FLCTL_A->BANK1_MAIN_WEPROT0; - } else - { - baseStartConfig++; - } - } - - (*baseEndConfig) &= ~(0xFFFFFFFF >> (31 - (endBankBit))); - } - - return true; - -} - -bool FlashCtl_A_protectMemory(uint32_t startAddr, uint32_t endAddr) -{ - uint32_t startBankBit, endBankBit, cutOffMemory; - volatile uint32_t* baseStartConfig, *baseEndConfig; - - if (startAddr > endAddr) - return false; - - if (endAddr >= SysCtl_A_getFlashSize()) - { - cutOffMemory = (SysCtl_A_getInfoFlashSize() >> 1) - + __INFO_FLASH_A_TECH_START__; - - if (endAddr < cutOffMemory && startAddr < cutOffMemory) - { - startBankBit = (startAddr - __INFO_FLASH_A_TECH_START__) - / FLASH_A_SECTOR_SIZE; - endBankBit = (endAddr - __INFO_FLASH_A_TECH_START__) - / FLASH_A_SECTOR_SIZE; - FLCTL_A->BANK0_INFO_WEPROT |= (0xFFFFFFFF >> (31 - endBankBit)) - & (0xFFFFFFFF << startBankBit); - } else if (endAddr > cutOffMemory && startAddr > cutOffMemory) - { - startBankBit = (startAddr - cutOffMemory) / FLASH_A_SECTOR_SIZE; - endBankBit = (endAddr - cutOffMemory) / FLASH_A_SECTOR_SIZE; - FLCTL_A->BANK1_INFO_WEPROT |= (0xFFFFFFFF >> (31 - endBankBit)) - & (0xFFFFFFFF << startBankBit); - } else - { - startBankBit = (startAddr - __INFO_FLASH_A_TECH_START__) - / FLASH_A_SECTOR_SIZE; - endBankBit = (endAddr - cutOffMemory) / FLASH_A_SECTOR_SIZE; - FLCTL_A->BANK0_INFO_WEPROT |= (0xFFFFFFFF << startBankBit); - FLCTL_A->BANK1_INFO_WEPROT |= (0xFFFFFFFF >> (31 - (endBankBit))); - } - - return true; - - } else - { - cutOffMemory = SysCtl_A_getFlashSize() >> 1; - - if (endAddr < cutOffMemory) - { - endBankBit = endAddr / FLASH_A_SECTOR_SIZE; - baseEndConfig = &FLCTL_A->BANK0_MAIN_WEPROT0 - + ((endBankBit >> 5)); - endBankBit &= 0x1F; - } else - { - endBankBit = (endAddr - cutOffMemory) / FLASH_A_SECTOR_SIZE; - baseEndConfig = &FLCTL_A->BANK1_MAIN_WEPROT0 - + (endBankBit >> 5); - endBankBit &= 0x1F; - } - - if (startAddr < cutOffMemory) - { - startBankBit = (startAddr / FLASH_A_SECTOR_SIZE); - baseStartConfig = &FLCTL_A->BANK0_MAIN_WEPROT0 - + (startBankBit >> 5); - startBankBit &= 0x1F; - } else - { - startBankBit = (startAddr - cutOffMemory) / FLASH_A_SECTOR_SIZE; - baseStartConfig = &FLCTL_A->BANK1_MAIN_WEPROT0 - + (startBankBit >> 5); - startBankBit &= 0x1F; - } - - if (baseStartConfig == baseEndConfig) - { - (*baseStartConfig) |= (0xFFFFFFFF >> (31 - endBankBit)) - & (0xFFFFFFFF << startBankBit); - return true; - } - - *baseStartConfig |= (0xFFFFFFFF << startBankBit); - - if (baseStartConfig == &FLCTL_A->BANK0_MAIN_WEPROT7) - { - baseStartConfig = &FLCTL_A->BANK1_MAIN_WEPROT0; - } else - { - baseStartConfig++; - } - - while (baseStartConfig != baseEndConfig) - { - *baseStartConfig = 0xFFFFFFFF; - - if (baseStartConfig == &FLCTL_A->BANK0_MAIN_WEPROT7) - { - baseStartConfig = &FLCTL_A->BANK1_MAIN_WEPROT0; - } else - { - baseStartConfig++; - } - } - - (*baseEndConfig) |= (0xFFFFFFFF >> (31 - (endBankBit))); - } - - return true; - -} - -bool FlashCtl_A_verifyMemory(void* verifyAddr, uint32_t length, - uint_fast8_t pattern) -{ - uint32_t memoryPattern, addr, otpOffset; - uint32_t b0WaitState, b1WaitState, intStatus; - uint32_t bankOneStart, startBank, endBank; - uint_fast8_t b0readMode, b1readMode; - uint_fast8_t memoryType; - bool res; - - ASSERT(pattern == FLASH_A_0_PATTERN || pattern == FLASH_A_1_PATTERN); - - /* Saving interrupt context and disabling interrupts for program - * operation - */ - intStatus = CPU_primask(); - Interrupt_disableMaster(); - - /* Casting and determining the memory that we need to use */ - addr = (uint32_t) verifyAddr; - memoryType = (addr >= SysCtl_A_getFlashSize()) ? - FLASH_A_INFO_SPACE : - FLASH_A_MAIN_SPACE; - - /* Assuming Failure */ - res = false; - - /* Finding out which bank we are in */ - if (addr >= SysCtl_A_getFlashSize()) - { - bankOneStart = __INFO_FLASH_A_TECH_MIDDLE__; - } else - { - bankOneStart = SysCtl_A_getFlashSize() / 2; - } - startBank = addr < (bankOneStart) ? FLASH_A_BANK0 : FLASH_A_BANK1; - endBank = (addr + length) < (bankOneStart) ? FLASH_A_BANK0 : FLASH_A_BANK1; - - /* Saving context and changing read modes */ - b0WaitState = FlashCtl_A_getWaitState(startBank); - b0readMode = FlashCtl_A_getReadMode(startBank); - - /* Setting the wait state to account for the mode */ - FlashCtl_A_setWaitState(startBank, (2 * b0WaitState) + 1); - - if (startBank != endBank) - { - b1WaitState = FlashCtl_A_getWaitState(endBank); - b1readMode = FlashCtl_A_getReadMode(endBank); - FlashCtl_A_setWaitState(endBank, (2 * b1WaitState) + 1); - } - - /* Changing to the relevant VERIFY mode */ - if (pattern == FLASH_A_1_PATTERN) - { - FlashCtl_A_setReadMode(startBank, FLASH_A_ERASE_VERIFY_READ_MODE); - - if (startBank != endBank) - { - FlashCtl_A_setReadMode(endBank, FLASH_A_ERASE_VERIFY_READ_MODE); - } - - memoryPattern = 0xFFFFFFFF; - } else - { - FlashCtl_A_setReadMode(startBank, FLASH_A_PROGRAM_VERIFY_READ_MODE); - - if (startBank != endBank) - { - FlashCtl_A_setReadMode(endBank, FLASH_A_PROGRAM_VERIFY_READ_MODE); - } - - memoryPattern = 0; - } - - /* Taking care of byte accesses */ - while ((addr & 0x03) && (length > 0)) - { - if (HWREG8(addr++) != ((uint8_t) memoryPattern)) - goto FlashVerifyCleanup; - length--; - } - - /* Making sure we are aligned by 128-bit address */ - while (((addr & 0x0F)) && (length > 3)) - { - if (HWREG32(addr) != memoryPattern) - goto FlashVerifyCleanup; - - addr = addr + 4; - length = length - 4; - } - - /* Burst Verify */ - if (length > 63) - { - /* Setting/clearing INFO flash flags as appropriate */ - if (addr >= SysCtl_A_getFlashSize()) - { - FLCTL_A->RDBRST_CTLSTAT = (FLCTL_A->RDBRST_CTLSTAT - & ~FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_MASK) - | FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_1; - otpOffset = __INFO_FLASH_A_TECH_START__; - } else - { - FLCTL_A->RDBRST_CTLSTAT = (FLCTL_A->RDBRST_CTLSTAT - & ~FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_MASK) - | FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_0; - otpOffset = 0; - } - - /* Clearing any lingering fault flags and preparing burst verify*/ - BITBAND_PERI(FLCTL_A->RDBRST_CTLSTAT, - FLCTL_A_RDBRST_CTLSTAT_CLR_STAT_OFS) = 1; - FLCTL_A->RDBRST_FAILCNT = 0; - FLCTL_A->RDBRST_STARTADDR = addr - otpOffset; - FLCTL_A->RDBRST_LEN = (length & 0xFFFFFFF0); - addr += FLCTL_A->RDBRST_LEN; - length = length & 0xF; - - /* Starting Burst Verify */ - FLCTL_A->RDBRST_CTLSTAT = (FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL | pattern - | memoryType | FLCTL_A_RDBRST_CTLSTAT_START); - - /* While the burst read hasn't finished */ - while ((FLCTL_A->RDBRST_CTLSTAT & FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_MASK) - != FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_3) - { - __no_operation(); - } - - /* Checking for a verification/access error/failure */ - if (BITBAND_PERI(FLCTL_A->RDBRST_CTLSTAT, - FLCTL_A_RDBRST_CTLSTAT_CMP_ERR_OFS) - || BITBAND_PERI(FLCTL_A->RDBRST_CTLSTAT, - FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR_OFS) - || FLCTL_A->RDBRST_FAILCNT) - { - goto FlashVerifyCleanup; - } - } - - /* Remaining Words */ - while (length > 3) - { - if (HWREG32(addr) != memoryPattern) - goto FlashVerifyCleanup; - - addr = addr + 4; - length = length - 4; - } - - /* Remaining Bytes */ - while (length > 0) - { - if (HWREG8(addr++) != ((uint8_t) memoryPattern)) - goto FlashVerifyCleanup; - length--; - } - - /* If we got this far, that means it no failure happened */ - res = true; - - FlashVerifyCleanup: - - /* Clearing the Read Burst flag and returning */ - BITBAND_PERI(FLCTL_A->RDBRST_CTLSTAT, FLCTL_A_RDBRST_CTLSTAT_CLR_STAT_OFS) = - 1; - - FlashCtl_A_setReadMode(startBank, b0readMode); - FlashCtl_A_setWaitState(startBank, b0WaitState); - - if (startBank != endBank) - { - FlashCtl_A_setReadMode(endBank, b1readMode); - FlashCtl_A_setWaitState(endBank, b1WaitState); - } - - if (intStatus == 0) - Interrupt_enableMaster(); - - return res; -} - -bool FlashCtl_A_setReadMode(uint32_t flashBank, uint32_t readMode) -{ - - if (FLCTL_A->POWER_STAT & FLCTL_A_POWER_STAT_RD_2T) - return false; - - if (flashBank == FLASH_A_BANK0) - { - FLCTL_A->BANK0_RDCTL = (FLCTL_A->BANK0_RDCTL - & ~FLCTL_A_BANK0_RDCTL_RD_MODE_MASK) | readMode; - while ((FLCTL_A->BANK0_RDCTL & FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_MASK) - != (readMode<<16)) - ; - } else if (flashBank == FLASH_A_BANK1) - { - FLCTL_A->BANK1_RDCTL = (FLCTL_A->BANK1_RDCTL - & ~FLCTL_A_BANK1_RDCTL_RD_MODE_MASK) | readMode; - while ((FLCTL_A->BANK1_RDCTL & FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_MASK) - != (readMode<<16)) - ; - } else - { - ASSERT(false); - return false; - } - - return true; -} - -uint32_t FlashCtl_A_getReadMode(uint32_t flashBank) -{ - if (flashBank == FLASH_A_BANK0) - { - return (FLCTL_A->BANK0_RDCTL & FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_MASK) - >> 16; - } else if (flashBank == FLASH_A_BANK1) - { - return (FLCTL_A->BANK1_RDCTL & FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_MASK) - >> 16; - } else - { - ASSERT(false); - return 0; - } -} - -void FlashCtl_A_initiateMassErase(void) -{ - /* Clearing old mass erase flags */ - BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS) = - 1; - - /* Performing the mass erase */ - FLCTL_A->ERASE_CTLSTAT |= (FLCTL_A_ERASE_CTLSTAT_MODE - | FLCTL_A_ERASE_CTLSTAT_START); -} - -bool FlashCtl_A_performMassErase(void) -{ - uint32_t flashSize, ii, intStatus, jj; - uint32_t mTries, tlvLength; - SysCtl_A_FlashTLV_Info *flInfo; - __FlashCtl_ProtectionRegister protectRegs; - bool res, needAnotherPulse; - - /* Parsing the TLV and getting the maximum erase pulses */ - SysCtl_A_getTLVInfo(TLV_TAG_FLASHCTL, 0, &tlvLength, (uint32_t**) &flInfo); - - if (tlvLength == 0 || flInfo->maxErasePulses == 0) - { - mTries = MAX_ERASE_NO_TLV; - } else - { - mTries = flInfo->maxErasePulses; - } - - /* Saving interrupt context and disabling interrupts for program - * operation - */ - intStatus = CPU_primask(); - Interrupt_disableMaster(); - - /* Assume Failure */ - res = false; - - /* Saving off protection settings so we can restore them later */ - __saveProtectionRegisters(&protectRegs); - - for(jj=0;jjERASE_CTLSTAT, FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS) = - 1; - - /* Performing the mass erase */ - FLCTL_A->ERASE_CTLSTAT |= (FLCTL_A_ERASE_CTLSTAT_MODE - | FLCTL_A_ERASE_CTLSTAT_START); - - while ((FLCTL_A->ERASE_CTLSTAT & FLCTL_A_ERASE_CTLSTAT_STATUS_MASK) - == FLCTL_A_ERASE_CTLSTAT_STATUS_1 - || (FLCTL_A->ERASE_CTLSTAT & FLCTL_A_ERASE_CTLSTAT_STATUS_MASK) - == FLCTL_A_ERASE_CTLSTAT_STATUS_2) - { - __no_operation(); - } - - /* Return false if an address error */ - if (BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, - FLCTL_A_ERASE_CTLSTAT_ADDR_ERR_OFS)) - goto MassEraseCleanup; - - /* Verifying the user memory that might have been erased */ - flashSize = SysCtl_A_getFlashSize(); - - /* Clearing old flag */ - BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS) = - 1; - - for (ii = 0; ii < flashSize; ii += FLASH_A_SECTOR_SIZE) - { - if (!FlashCtl_A_isMemoryProtected(ii)) - { - if (!FlashCtl_A_verifyMemory((void*) ii, FLASH_A_SECTOR_SIZE, - FLASH_A_1_PATTERN)) - { - needAnotherPulse = true; - } - else - { - FlashCtl_A_protectMemory(ii,ii); - } - } - } - - /* Verifying the INFO memory that might be protected */ - flashSize = SysCtl_A_getInfoFlashSize() + __INFO_FLASH_A_TECH_START__; - - for (ii = __INFO_FLASH_A_TECH_START__; ii < flashSize; ii += - FLASH_A_SECTOR_SIZE) - { - if (!FlashCtl_A_isMemoryProtected(ii)) - { - if (!FlashCtl_A_verifyMemory((void*) ii, FLASH_A_SECTOR_SIZE, - FLASH_A_1_PATTERN)) - { - needAnotherPulse = true; - } - else - { - FlashCtl_A_protectMemory(ii,ii); - } - } - } - - if(!needAnotherPulse) - { - break; - } - } - - /* If we got this far and didn't do the max number of tries, - * the mass erase happened */ - if(jj != mTries) - { - res = true; - } - -MassEraseCleanup: - - BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, - FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS) = 1; - __restoreProtectionRegisters(&protectRegs); - - if (intStatus == 0) - Interrupt_enableMaster(); - - return res; -} - -bool FlashCtl_A_eraseSector(uint32_t addr) -{ - uint_fast8_t memoryType, ii; - uint32_t otpOffset = 0; - uint32_t intStatus; - uint_fast8_t mTries, tlvLength; - SysCtl_A_FlashTLV_Info *flInfo; - bool res; - - /* Saving interrupt context and disabling interrupts for program - * operation - */ - intStatus = CPU_primask(); - Interrupt_disableMaster(); - - /* Assuming Failure */ - res = false; - - memoryType = addr >= SysCtl_A_getFlashSize() ? FLASH_A_INFO_SPACE : - FLASH_A_MAIN_SPACE; - - /* Parsing the TLV and getting the maximum erase pulses */ - SysCtl_A_getTLVInfo(TLV_TAG_FLASHCTL, 0, &tlvLength, (uint32_t**) &flInfo); - - if (tlvLength == 0 || flInfo->maxErasePulses == 0) - { - mTries = MAX_ERASE_NO_TLV; - } else - { - mTries = flInfo->maxErasePulses; - } - - /* We can only erase on 4KB boundaries */ - while (addr & 0xFFF) - { - addr--; - } - - /* Clearing the status */ - BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS) = - 1; - - if (memoryType == FLASH_A_INFO_SPACE) - { - otpOffset = __INFO_FLASH_A_TECH_START__; - FLCTL_A->ERASE_CTLSTAT = (FLCTL_A->ERASE_CTLSTAT - & ~(FLCTL_A_ERASE_CTLSTAT_TYPE_MASK)) - | FLCTL_A_ERASE_CTLSTAT_TYPE_1; - - } else - { - otpOffset = 0; - FLCTL_A->ERASE_CTLSTAT = (FLCTL_A->ERASE_CTLSTAT - & ~(FLCTL_A_ERASE_CTLSTAT_TYPE_MASK)) - | FLCTL_A_ERASE_CTLSTAT_TYPE_0; - } - - /* Clearing old flags and setting up the erase */ - BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, FLCTL_A_ERASE_CTLSTAT_MODE_OFS) = 0; - FLCTL_A->ERASE_SECTADDR = addr - otpOffset; - - for (ii = 0; ii < mTries; ii++) - { - /* Clearing the status */ - BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS) = - 1; - - /* Starting the erase */ - BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, FLCTL_A_ERASE_CTLSTAT_START_OFS) = - 1; - - while ((FLCTL_A->ERASE_CTLSTAT & FLCTL_A_ERASE_CTLSTAT_STATUS_MASK) - == FLCTL_A_ERASE_CTLSTAT_STATUS_1 - || (FLCTL_A->ERASE_CTLSTAT & FLCTL_A_ERASE_CTLSTAT_STATUS_MASK) - == FLCTL_A_ERASE_CTLSTAT_STATUS_2) - { - __no_operation(); - } - - /* Return false if an address error */ - if (BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, - FLCTL_A_ERASE_CTLSTAT_ADDR_ERR_OFS)) - { - goto SectorEraseCleanup; - } - /* Erase verifying */ - if (FlashCtl_A_verifyMemory((void*) addr, FLASH_A_SECTOR_SIZE, - FLASH_A_1_PATTERN)) - { - res = true; - goto SectorEraseCleanup; - } - - } - - SectorEraseCleanup: - - BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS) = - 1; - - if (intStatus == 0) - Interrupt_enableMaster(); - - return res; -} - -void FlashCtl_A_initiateSectorErase(uint32_t addr) -{ - uint_fast8_t memoryType; - uint32_t otpOffset = 0; - - memoryType = addr >= SysCtl_A_getFlashSize() ? - FLASH_A_INFO_SPACE : - FLASH_A_MAIN_SPACE; - - /* We can only erase on 4KB boundaries */ - while (addr & 0xFFF) - { - addr--; - } - - /* Clearing the status */ - BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS) = - 1; - - if (memoryType == FLASH_A_INFO_SPACE) - { - otpOffset = __INFO_FLASH_A_TECH_START__; - FLCTL_A->ERASE_CTLSTAT = (FLCTL_A->ERASE_CTLSTAT - & ~(FLCTL_A_ERASE_CTLSTAT_TYPE_MASK)) - | FLCTL_A_ERASE_CTLSTAT_TYPE_1; - - } else - { - otpOffset = 0; - FLCTL_A->ERASE_CTLSTAT = (FLCTL_A->ERASE_CTLSTAT - & ~(FLCTL_A_ERASE_CTLSTAT_TYPE_MASK)) - | FLCTL_A_ERASE_CTLSTAT_TYPE_0; - } - - /* Clearing old flags and setting up the erase */ - BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, FLCTL_A_ERASE_CTLSTAT_MODE_OFS) = 0; - FLCTL_A->ERASE_SECTADDR = addr - otpOffset; - - /* Starting the erase */ - BITBAND_PERI(FLCTL_A->ERASE_CTLSTAT, FLCTL_A_ERASE_CTLSTAT_START_OFS) = 1; - -} - -bool FlashCtl_A_programMemory(void* src, void* dest, uint32_t length) -{ - uint32_t destAddr, srcAddr, burstLength, intStatus; - bool res; - uint_fast8_t mTries, tlvLength; - SysCtl_A_FlashTLV_Info *flInfo; - - /* Saving interrupt context and disabling interrupts for program - * operation - */ - intStatus = CPU_primask(); - Interrupt_disableMaster(); - - /* Parsing the TLV and getting the maximum erase pulses */ - SysCtl_A_getTLVInfo(TLV_TAG_FLASHCTL, 0, &tlvLength, (uint32_t**) &flInfo); - - if (tlvLength == 0 || flInfo->maxProgramPulses == 0) - { - mTries = MAX_PROGRAM_NO_TLV; - } else - { - mTries = flInfo->maxProgramPulses; - } - - /* Casting to integers */ - srcAddr = (uint32_t) src; - destAddr = (uint32_t) dest; - - /* Enabling word programming */ - FlashCtl_A_enableWordProgramming(FLASH_A_IMMEDIATE_WRITE_MODE); - - /* Assume failure */ - res = false; - - /* Taking care of byte accesses */ - while ((destAddr & 0x03) && length > 0) - { - if (!_FlashCtl_A_Program8(srcAddr, destAddr, mTries)) - { - goto FlashProgramCleanUp; - } else - { - srcAddr++; - destAddr++; - length--; - } - } - - /* Taking care of word accesses */ - while ((destAddr & 0x0F) && (length > 3)) - { - if (!_FlashCtl_A_Program32(srcAddr, destAddr, mTries)) - { - goto FlashProgramCleanUp; - } else - { - srcAddr += 4; - destAddr += 4; - length -= 4; - } - } - - /* Taking care of burst programs */ - while (length > 16) - { - burstLength = length > 63 ? 64 : length & 0xFFFFFFF0; - - if (!_FlashCtl_A_ProgramBurst(srcAddr, destAddr, burstLength, mTries)) - { - goto FlashProgramCleanUp; - } else - { - srcAddr += burstLength; - destAddr += burstLength; - length -= burstLength; - } - } - - /* Remaining word accesses */ - while (length > 3) - { - if (!_FlashCtl_A_Program32(srcAddr, destAddr, mTries)) - { - goto FlashProgramCleanUp; - } else - { - srcAddr += 4; - destAddr += 4; - length -= 4; - } - } - - /* Remaining byte accesses */ - while (length > 0) - { - if (!_FlashCtl_A_Program8(srcAddr, destAddr, mTries)) - { - goto FlashProgramCleanUp; - } else - { - srcAddr++; - destAddr++; - length--; - } - } - - /* If we got this far that means that we succeeded */ - res = true; - - FlashProgramCleanUp: - - if (intStatus == 0) - Interrupt_enableMaster(); - - FlashCtl_A_disableWordProgramming(); - return res; - -} -void FlashCtl_A_setProgramVerification(uint32_t verificationSetting) -{ - if ((verificationSetting & FLASH_A_BURSTPOST)) - BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST_OFS) = 1; - - if ((verificationSetting & FLASH_A_BURSTPRE)) - BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE_OFS) = 1; - - if ((verificationSetting & FLASH_A_REGPRE)) - BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_VER_PRE_OFS) = 1; - - if ((verificationSetting & FLASH_A_REGPOST)) - BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_VER_PST_OFS) = 1; -} - -void FlashCtl_A_clearProgramVerification(uint32_t verificationSetting) -{ - if ((verificationSetting & FLASH_A_BURSTPOST)) - BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST_OFS) = 0; - - if ((verificationSetting & FLASH_A_BURSTPRE)) - BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE_OFS) = 0; - - if ((verificationSetting & FLASH_A_REGPRE)) - BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_VER_PRE_OFS) = 0; - - if ((verificationSetting & FLASH_A_REGPOST)) - BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_VER_PST_OFS) = 0; - -} - -void FlashCtl_A_enableWordProgramming(uint32_t mode) -{ - if (mode == FLASH_A_IMMEDIATE_WRITE_MODE) - { - BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_ENABLE_OFS) = 1; - BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_MODE_OFS) = 0; - - } else if (mode == FLASH_A_COLLATED_WRITE_MODE) - { - BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_ENABLE_OFS) = 1; - BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_MODE_OFS) = 1; - } -} - -void FlashCtl_A_disableWordProgramming(void) -{ - BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_ENABLE_OFS) = 0; -} - -uint32_t FlashCtl_A_isWordProgrammingEnabled(void) -{ - if (!BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_ENABLE_OFS)) - { - return 0; - } else if (BITBAND_PERI(FLCTL_A->PRG_CTLSTAT, FLCTL_A_PRG_CTLSTAT_MODE_OFS)) - return FLASH_A_COLLATED_WRITE_MODE; - else - return FLASH_A_IMMEDIATE_WRITE_MODE; -} - -void FlashCtl_A_setWaitState(uint32_t flashBank, uint32_t waitState) -{ - if (flashBank == FLASH_A_BANK0) - { - FLCTL_A->BANK0_RDCTL = (FLCTL_A->BANK0_RDCTL - & ~FLCTL_A_BANK0_RDCTL_WAIT_MASK) - | (waitState << FLCTL_A_BANK0_RDCTL_WAIT_OFS); - } else if (flashBank == FLASH_A_BANK1) - { - FLCTL_A->BANK1_RDCTL = (FLCTL_A->BANK1_RDCTL - & ~FLCTL_A_BANK1_RDCTL_WAIT_MASK) - | (waitState << FLCTL_A_BANK1_RDCTL_WAIT_OFS); - } else - { - ASSERT(false); - } -} - -uint32_t FlashCtl_A_getWaitState(uint32_t flashBank) -{ - if (flashBank == FLASH_A_BANK0) - { - return (FLCTL_A->BANK0_RDCTL & FLCTL_A_BANK0_RDCTL_WAIT_MASK) - >> FLCTL_A_BANK0_RDCTL_WAIT_OFS; - } else if (flashBank == FLASH_A_BANK1) - { - return (FLCTL_A->BANK1_RDCTL & FLCTL_A_BANK1_RDCTL_WAIT_MASK) - >> FLCTL_A_BANK1_RDCTL_WAIT_OFS; - } else - { - ASSERT(false); - return 0; - } -} - -void FlashCtl_A_enableInterrupt(uint32_t flags) -{ - FLCTL_A->IE |= flags; -} - -void FlashCtl_A_disableInterrupt(uint32_t flags) -{ - FLCTL_A->IE &= ~flags; -} - -uint32_t FlashCtl_A_getInterruptStatus(void) -{ - return FLCTL_A->IFG; -} - -uint32_t FlashCtl_A_getEnabledInterruptStatus(void) -{ - return FlashCtl_A_getInterruptStatus() & FLCTL_A->IE; -} - -void FlashCtl_A_clearInterruptFlag(uint32_t flags) -{ - FLCTL_A->CLRIFG |= flags; -} - -void FlashCtl_A_registerInterrupt(void (*intHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - Interrupt_registerInterrupt(INT_FLCTL, intHandler); - - // - // Enable the system control interrupt. - // - Interrupt_enableInterrupt(INT_FLCTL); -} - -void FlashCtl_A_unregisterInterrupt(void) -{ - // - // Disable the interrupt. - // - Interrupt_disableInterrupt(INT_FLCTL); - - // - // Unregister the interrupt handler. - // - Interrupt_unregisterInterrupt(INT_FLCTL); -} - -uint8_t __FlashCtl_A_remaskData8Post(uint8_t data, uint32_t addr) -{ - uint32_t readMode, waitState, bankProgram, bankOneStart; - - /* Changing the waitstate and read mode of whichever bank we are in */ - /* Finding out which bank we are in */ - if (addr >= SysCtl_A_getFlashSize()) - { - bankOneStart = __INFO_FLASH_A_TECH_MIDDLE__; - } else - { - bankOneStart = SysCtl_A_getFlashSize() / 2; - } - - bankProgram = addr < (bankOneStart) ? FLASH_A_BANK0 : FLASH_A_BANK1; - - /* Saving the current wait states and read mode */ - waitState = FlashCtl_A_getWaitState(bankProgram); - readMode = FlashCtl_A_getReadMode(bankProgram); - - /* Setting the wait state to account for the mode */ - FlashCtl_A_setWaitState(bankProgram, (2 * waitState) + 1); - - /* Changing to PROGRAM VERIFY mode */ - FlashCtl_A_setReadMode(bankProgram, FLASH_A_PROGRAM_VERIFY_READ_MODE); - - data = ~(~(data) & HWREG8(addr)); - - /* Setting the wait state to account for the mode */ - FlashCtl_A_setReadMode(bankProgram, readMode); - FlashCtl_A_setWaitState(bankProgram, waitState); - - return data; -} - -uint8_t __FlashCtl_A_remaskData8Pre(uint8_t data, uint32_t addr) -{ - uint32_t readMode, waitState, bankProgram, bankOneStart; - - /* Changing the waitstate and read mode of whichever bank we are in */ - /* Finding out which bank we are in */ - if (addr >= SysCtl_A_getFlashSize()) - { - bankOneStart = __INFO_FLASH_A_TECH_MIDDLE__; - } else - { - bankOneStart = SysCtl_A_getFlashSize() / 2; - } - - bankProgram = addr < (bankOneStart) ? FLASH_A_BANK0 : FLASH_A_BANK1; - - /* Saving the current wait states and read mode */ - waitState = FlashCtl_A_getWaitState(bankProgram); - readMode = FlashCtl_A_getReadMode(bankProgram); - - /* Setting the wait state to account for the mode */ - FlashCtl_A_setWaitState(bankProgram, (2 * waitState) + 1); - - /* Changing to PROGRAM VERIFY mode */ - FlashCtl_A_setReadMode(bankProgram, FLASH_A_PROGRAM_VERIFY_READ_MODE); - - data |= ~(HWREG8(addr) | data); - - /* Setting the wait state to account for the mode */ - FlashCtl_A_setReadMode(bankProgram, readMode); - FlashCtl_A_setWaitState(bankProgram, waitState); - - return data; -} - -uint32_t __FlashCtl_A_remaskData32Post(uint32_t data, uint32_t addr) -{ - uint32_t bankProgramStart, bankProgramEnd, bank1Start; - uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode; - - /* Changing the waitstate and read mode of whichever bank we are in */ - /* Finding out which bank we are in */ - if (addr >= SysCtl_A_getFlashSize()) - { - bank1Start = __INFO_FLASH_A_TECH_MIDDLE__; - } else - { - bank1Start = SysCtl_A_getFlashSize() / 2; - } - - bankProgramStart = addr < bank1Start ? FLASH_A_BANK0 : FLASH_A_BANK1; - bankProgramEnd = (addr + 4) < bank1Start ? FLASH_A_BANK0 : FLASH_A_BANK1; - - /* Saving the current wait states and read mode */ - b0WaitState = FlashCtl_A_getWaitState(bankProgramStart); - b0ReadMode = FlashCtl_A_getReadMode(bankProgramStart); - FlashCtl_A_setWaitState(bankProgramStart, (2 * b0WaitState) + 1); - FlashCtl_A_setReadMode(bankProgramStart, FLASH_A_PROGRAM_VERIFY_READ_MODE); - - if (bankProgramStart != bankProgramEnd) - { - b1WaitState = FlashCtl_A_getWaitState(bankProgramEnd); - b1ReadMode = FlashCtl_A_getReadMode(bankProgramEnd); - FlashCtl_A_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1); - FlashCtl_A_setReadMode(bankProgramEnd, - FLASH_A_PROGRAM_VERIFY_READ_MODE); - } - - data = ~(~(data) & HWREG32(addr)); - - /* Setting the wait state to account for the mode */ - FlashCtl_A_setReadMode(bankProgramStart, b0ReadMode); - FlashCtl_A_setWaitState(bankProgramStart, b0WaitState); - - if (bankProgramStart != bankProgramEnd) - { - FlashCtl_A_setReadMode(bankProgramEnd, b1ReadMode); - FlashCtl_A_setWaitState(bankProgramEnd, b1WaitState); - } - - return data; -} - -uint32_t __FlashCtl_A_remaskData32Pre(uint32_t data, uint32_t addr) -{ - uint32_t bankProgramStart, bankProgramEnd, bank1Start; - uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode; - - /* Changing the waitstate and read mode of whichever bank we are in */ - /* Finding out which bank we are in */ - if (addr >= SysCtl_A_getFlashSize()) - { - bank1Start = __INFO_FLASH_A_TECH_MIDDLE__; - } else - { - bank1Start = SysCtl_A_getFlashSize() / 2; - } - - bankProgramStart = addr < bank1Start ? FLASH_A_BANK0 : FLASH_A_BANK1; - bankProgramEnd = (addr + 4) < bank1Start ? FLASH_A_BANK0 : FLASH_A_BANK1; - - /* Saving the current wait states and read mode */ - b0WaitState = FlashCtl_A_getWaitState(bankProgramStart); - b0ReadMode = FlashCtl_A_getReadMode(bankProgramStart); - FlashCtl_A_setWaitState(bankProgramStart, (2 * b0WaitState) + 1); - FlashCtl_A_setReadMode(bankProgramStart, FLASH_A_PROGRAM_VERIFY_READ_MODE); - - if (bankProgramStart != bankProgramEnd) - { - b1WaitState = FlashCtl_A_getWaitState(bankProgramEnd); - b1ReadMode = FlashCtl_A_getReadMode(bankProgramEnd); - FlashCtl_A_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1); - FlashCtl_A_setReadMode(bankProgramEnd, - FLASH_A_PROGRAM_VERIFY_READ_MODE); - } - - data |= ~(HWREG32(addr) | data); - - /* Setting the wait state to account for the mode */ - FlashCtl_A_setReadMode(bankProgramStart, b0ReadMode); - FlashCtl_A_setWaitState(bankProgramStart, b0WaitState); - - if (bankProgramStart != bankProgramEnd) - { - FlashCtl_A_setReadMode(bankProgramEnd, b1ReadMode); - FlashCtl_A_setWaitState(bankProgramEnd, b1WaitState); - } - - return data; -} - -void __FlashCtl_A_remaskBurstDataPre(uint32_t addr, uint32_t size) -{ - - uint32_t bankProgramStart, bankProgramEnd, bank1Start, ii; - uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode; - - /* Waiting for idle status */ - while ((FLCTL_A->PRGBRST_CTLSTAT & FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK) - != FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_0) - { - BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1; - } - - /* Changing the waitstate and read mode of whichever bank we are in */ - /* Finding out which bank we are in */ - if (addr >= SysCtl_A_getFlashSize()) - { - bank1Start = __INFO_FLASH_A_TECH_MIDDLE__; - } else - { - bank1Start = SysCtl_A_getFlashSize() / 2; - } - - bankProgramStart = addr < bank1Start ? FLASH_A_BANK0 : FLASH_A_BANK1; - bankProgramEnd = (addr + size) < bank1Start ? FLASH_A_BANK0 : FLASH_A_BANK1; - - /* Saving the current wait states and read mode */ - b0WaitState = FlashCtl_A_getWaitState(bankProgramStart); - b0ReadMode = FlashCtl_A_getReadMode(bankProgramStart); - FlashCtl_A_setWaitState(bankProgramStart, (2 * b0WaitState) + 1); - FlashCtl_A_setReadMode(bankProgramStart, FLASH_A_PROGRAM_VERIFY_READ_MODE); - - if (bankProgramStart != bankProgramEnd) - { - b1WaitState = FlashCtl_A_getWaitState(bankProgramEnd); - b1ReadMode = FlashCtl_A_getReadMode(bankProgramEnd); - FlashCtl_A_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1); - FlashCtl_A_setReadMode(bankProgramEnd, - FLASH_A_PROGRAM_VERIFY_READ_MODE); - } - - /* Going through each BURST program register and masking out for pre - * verifcation - */ - size = (size / 4); - for (ii = 0; ii < size; ii++) - { - HWREG32(__getBurstProgramRegs[ii]) |= - ~(HWREG32(__getBurstProgramRegs[ii]) | HWREG32(addr)); - addr += 4; - } - - /* Setting the wait state to account for the mode */ - FlashCtl_A_setReadMode(bankProgramStart, b0ReadMode); - FlashCtl_A_setWaitState(bankProgramStart, b0WaitState); - - if (bankProgramStart != bankProgramEnd) - { - FlashCtl_A_setReadMode(bankProgramEnd, b1ReadMode); - FlashCtl_A_setWaitState(bankProgramEnd, b1WaitState); - } - -} -void __FlashCtl_A_remaskBurstDataPost(uint32_t addr, uint32_t size) -{ - uint32_t bankProgramStart, bankProgramEnd, bank1Start, ii; - uint32_t b0WaitState, b0ReadMode, b1WaitState, b1ReadMode; - - /* Waiting for idle status */ - while ((FLCTL_A->PRGBRST_CTLSTAT & FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK) - != FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_0) - { - BITBAND_PERI(FLCTL_A->PRGBRST_CTLSTAT, - FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT_OFS) = 1; - } - - /* Changing the waitstate and read mode of whichever bank we are in */ - /* Finding out which bank we are in */ - if (addr >= SysCtl_A_getFlashSize()) - { - bank1Start = __INFO_FLASH_A_TECH_MIDDLE__; - } else - { - bank1Start = SysCtl_A_getFlashSize() / 2; - } - - bankProgramStart = addr < bank1Start ? FLASH_A_BANK0 : FLASH_A_BANK1; - bankProgramEnd = (addr + size) < bank1Start ? FLASH_A_BANK0 : FLASH_A_BANK1; - - /* Saving the current wait states and read mode */ - b0WaitState = FlashCtl_A_getWaitState(bankProgramStart); - b0ReadMode = FlashCtl_A_getReadMode(bankProgramStart); - FlashCtl_A_setWaitState(bankProgramStart, (2 * b0WaitState) + 1); - FlashCtl_A_setReadMode(bankProgramStart, FLASH_A_PROGRAM_VERIFY_READ_MODE); - - if (bankProgramStart != bankProgramEnd) - { - b1WaitState = FlashCtl_A_getWaitState(bankProgramEnd); - b1ReadMode = FlashCtl_A_getReadMode(bankProgramEnd); - FlashCtl_A_setWaitState(bankProgramEnd, (2 * b1WaitState) + 1); - FlashCtl_A_setReadMode(bankProgramEnd, - FLASH_A_PROGRAM_VERIFY_READ_MODE); - } - - /* Going through each BURST program register and masking out for post - * verifcation if needed - */ - size = (size / 4); - for (ii = 0; ii < size; ii++) - { - HWREG32(__getBurstProgramRegs[ii]) = ~(~(HWREG32( - __getBurstProgramRegs[ii])) & HWREG32(addr)); - - addr += 4; - } - - /* Setting the wait state to account for the mode */ - FlashCtl_A_setReadMode(bankProgramStart, b0ReadMode); - FlashCtl_A_setWaitState(bankProgramStart, b0WaitState); - - if (bankProgramStart != bankProgramEnd) - { - FlashCtl_A_setReadMode(bankProgramEnd, b1ReadMode); - FlashCtl_A_setWaitState(bankProgramEnd, b1WaitState); - } -} - -#endif /* __MCU_HAS_FLCTL_A__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/flash_a.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/flash_a.h deleted file mode 100644 index c14c92b404b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/flash_a.h +++ /dev/null @@ -1,851 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __FLASH_A_H__ -#define __FLASH_A_H__ - -#include -#include - -/* Define to ensure that our current MSP432 has the FLCTL_A module. This - definition is included in the device specific header file */ -#ifdef __MCU_HAS_FLCTL_A__ - -//***************************************************************************** -// -//! \addtogroup flash_a_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Control specific variables -// -//***************************************************************************** -#define FLASH_A_BURST_PRG_BIT 0x03 -#define FLASH_A_SECTOR_SIZE 4096 - -/* Interrupts */ -#define FLASH_A_PROGRAM_ERROR FLCTL_A_IFG_PRG_ERR -#define FLASH_A_BENCHMARK_INT FLCTL_A_IFG_BMRK -#define FLASH_A_ERASE_COMPLETE FLCTL_A_IFG_ERASE -#define FLASH_A_BRSTPRGM_COMPLETE FLCTL_A_IFG_PRGB -#define FLASH_A_WRDPRGM_COMPLETE FLCTL_A_IFG_PRG -#define FLASH_A_POSTVERIFY_FAILED FLCTL_A_IFG_AVPST -#define FLASH_A_PREVERIFY_FAILED FLCTL_A_IFG_AVPRE -#define FLASH_A_BRSTRDCMP_COMPLETE FLCTL_A_IFG_RDBRST - -#define FLASH_A_NORMAL_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_0 -#define FLASH_A_MARGIN0_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_1 -#define FLASH_A_MARGIN1_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_2 -#define FLASH_A_PROGRAM_VERIFY_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_3 -#define FLASH_A_ERASE_VERIFY_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_4 -#define FLASH_A_LEAKAGE_VERIFY_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_5 -#define FLASH_A_MARGIN0B_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_9 -#define FLASH_A_MARGIN1B_READ_MODE FLCTL_A_BANK0_RDCTL_RD_MODE_10 - -#define FLASH_A_PRGBRSTCTLSTAT_BURSTSTATUS_COMPLETE FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_7 - -#define FLASH_A_BANK0 0x00 -#define FLASH_A_BANK1 0x01 -#define FLASH_A_DATA_READ 0x00 -#define FLASH_A_INSTRUCTION_FETCH 0x01 - -#define FLASH_A_MAIN_MEMORY_SPACE_BANK0 0x01 -#define FLASH_A_MAIN_MEMORY_SPACE_BANK1 0x02 -#define FLASH_A_INFO_MEMORY_SPACE_BANK0 0x03 -#define FLASH_A_INFO_MEMORY_SPACE_BANK1 0x04 - -#define FLASH_A_MAIN_SPACE FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_0 -#define FLASH_A_INFO_SPACE FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_1 -#define FLASH_A_1_PATTERN FLCTL_A_RDBRST_CTLSTAT_DATA_CMP -#define FLASH_A_0_PATTERN 0x00 - -#define FLASH_A_SECTOR0 FLCTL_A_BANK0_MAIN_WEPROT_PROT0 -#define FLASH_A_SECTOR1 FLCTL_A_BANK0_MAIN_WEPROT_PROT1 -#define FLASH_A_SECTOR2 FLCTL_A_BANK0_MAIN_WEPROT_PROT2 -#define FLASH_A_SECTOR3 FLCTL_A_BANK0_MAIN_WEPROT_PROT3 -#define FLASH_A_SECTOR4 FLCTL_A_BANK0_MAIN_WEPROT_PROT4 -#define FLASH_A_SECTOR5 FLCTL_A_BANK0_MAIN_WEPROT_PROT5 -#define FLASH_A_SECTOR6 FLCTL_A_BANK0_MAIN_WEPROT_PROT6 -#define FLASH_A_SECTOR7 FLCTL_A_BANK0_MAIN_WEPROT_PROT7 -#define FLASH_A_SECTOR8 FLCTL_A_BANK0_MAIN_WEPROT_PROT8 -#define FLASH_A_SECTOR9 FLCTL_A_BANK0_MAIN_WEPROT_PROT9 -#define FLASH_A_SECTOR10 FLCTL_A_BANK0_MAIN_WEPROT_PROT10 -#define FLASH_A_SECTOR11 FLCTL_A_BANK0_MAIN_WEPROT_PROT11 -#define FLASH_A_SECTOR12 FLCTL_A_BANK0_MAIN_WEPROT_PROT12 -#define FLASH_A_SECTOR13 FLCTL_A_BANK0_MAIN_WEPROT_PROT13 -#define FLASH_A_SECTOR14 FLCTL_A_BANK0_MAIN_WEPROT_PROT14 -#define FLASH_A_SECTOR15 FLCTL_A_BANK0_MAIN_WEPROT_PROT15 -#define FLASH_A_SECTOR16 FLCTL_A_BANK0_MAIN_WEPROT_PROT16 -#define FLASH_A_SECTOR17 FLCTL_A_BANK0_MAIN_WEPROT_PROT17 -#define FLASH_A_SECTOR18 FLCTL_A_BANK0_MAIN_WEPROT_PROT18 -#define FLASH_A_SECTOR19 FLCTL_A_BANK0_MAIN_WEPROT_PROT19 -#define FLASH_A_SECTOR20 FLCTL_A_BANK0_MAIN_WEPROT_PROT20 -#define FLASH_A_SECTOR21 FLCTL_A_BANK0_MAIN_WEPROT_PROT21 -#define FLASH_A_SECTOR22 FLCTL_A_BANK0_MAIN_WEPROT_PROT22 -#define FLASH_A_SECTOR23 FLCTL_A_BANK0_MAIN_WEPROT_PROT23 -#define FLASH_A_SECTOR24 FLCTL_A_BANK0_MAIN_WEPROT_PROT24 -#define FLASH_A_SECTOR25 FLCTL_A_BANK0_MAIN_WEPROT_PROT25 -#define FLASH_A_SECTOR26 FLCTL_A_BANK0_MAIN_WEPROT_PROT26 -#define FLASH_A_SECTOR27 FLCTL_A_BANK0_MAIN_WEPROT_PROT27 -#define FLASH_A_SECTOR28 FLCTL_A_BANK0_MAIN_WEPROT_PROT28 -#define FLASH_A_SECTOR29 FLCTL_A_BANK0_MAIN_WEPROT_PROT29 -#define FLASH_A_SECTOR30 FLCTL_A_BANK0_MAIN_WEPROT_PROT30 -#define FLASH_A_SECTOR31 FLCTL_A_BANK0_MAIN_WEPROT_PROT31 - -#define FLASH_A_NOVER 0 -#define FLASH_A_BURSTPOST FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST -#define FLASH_A_BURSTPRE FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE -#define FLASH_A_REGPRE FLCTL_A_PRG_CTLSTAT_VER_PRE -#define FLASH_A_REGPOST FLCTL_A_PRG_CTLSTAT_VER_PST -#define FLASH_A_FULLVER (FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST | \ - FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE | FLCTL_A_PRG_CTLSTAT_VER_PRE \ - | FLCTL_A_PRG_CTLSTAT_VER_PST) - -#define FLASH_A_COLLATED_WRITE_MODE 0x01 -#define FLASH_A_IMMEDIATE_WRITE_MODE 0x02 - -/* Internal parameters/definitions */ -#define __INFO_FLASH_A_TECH_START__ 0x00200000 -#define __INFO_FLASH_A_TECH_MIDDLE__ 0x00204000 - -typedef struct __sFlashCtl_ProtectionRegister -{ - uint32_t B0_MAIN_R0; - uint32_t B0_MAIN_R1; - uint32_t B0_MAIN_R2; - uint32_t B0_MAIN_R3; - uint32_t B0_MAIN_R4; - uint32_t B0_MAIN_R5; - uint32_t B0_MAIN_R6; - uint32_t B0_MAIN_R7; - uint32_t B1_MAIN_R0; - uint32_t B1_MAIN_R1; - uint32_t B1_MAIN_R2; - uint32_t B1_MAIN_R3; - uint32_t B1_MAIN_R4; - uint32_t B1_MAIN_R5; - uint32_t B1_MAIN_R6; - uint32_t B1_MAIN_R7; - uint32_t B0_INFO_R0; - uint32_t B1_INFO_R0; -} __FlashCtl_ProtectionRegister; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! Calculates the flash bank and sector number given an address. Stores the -//! results into the two pointers given as parameters. The user must provide -//! a valid memory address (an address in SRAM for example will give an invalid -//! result). -//! -//! \param addr Address to calculate the bank/sector information for -//! -//! \param bankNum The bank number will be stored in here after the function -//! completes. -//! -//! \param sectorNum The sector number will be stored in here after the function -//! completes. -//! -//! \note For simplicity, this API only works with address in MAIN flash memory. -//! For calculating the sector/bank number of an address in info memory, -//! please refer to your device datasheet/ -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_A_getMemoryInfo(uint32_t addr, uint32_t *bankNum, - uint32_t *sectorNum); - -//***************************************************************************** -// -//! Enables read buffering on accesses to a specified bank of flash memory -//! -//! \param memoryBank is the value of the memory bank to enable read -//! buffering. Must be only one of the following values: -//! - \b FLASH_A_BANK0, -//! - \b FLASH_A_BANK1 -//! -//! \param accessMethod is the value of the access type to enable read -//! buffering. Must be only one of the following values: -//! - \b FLASH_A_DATA_READ, -//! - \b FLASH_A_INSTRUCTION_FETCH -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_A_enableReadBuffering(uint_fast8_t memoryBank, - uint_fast8_t accessMethod); - -//***************************************************************************** -// -//! Disables read buffering on accesses to a specified bank of flash memory -//! -//! \param memoryBank is the value of the memory bank to disable read -//! buffering. Must be only one of the following values: -//! - \b FLASH_A_BANK0, -//! - \b FLASH_A_BANK1 -//! -//! \param accessMethod is the value of the access type to disable read -//! buffering. Must ne only one of the following values: -//! - \b FLASH_A_DATA_READ, -//! - \b FLASH_A_INSTRUCTION_FETCH -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_A_disableReadBuffering(uint_fast8_t memoryBank, - uint_fast8_t accessMethod); - -//***************************************************************************** -// -//! Enables protection on the given flash memory range from writes. Note that -//! this function only works on flash memory and giving in an address to ROM -//! or SRAM will result in unreliable behavior. -//! -//! \param startAddr is the start address of the memory to protect -//! -//! \param endAddr is the end address of the memory to protect -//! -//! \note Flash memory is organized by protection by sector sizes. This means -//! that you will only be able to protect/unprotect memory based off -//! 4096 aligned boundaries. -//! -//! \return true if sector protection enabled false otherwise. -// -//***************************************************************************** -extern bool FlashCtl_A_protectMemory(uint32_t startAddr, uint32_t endAddr); - -//***************************************************************************** -// -//! Disables protection on the given flash memory range from writes. Note that -//! this function only works on flash memory and giving in an address to ROM -//! or SRAM will result in unreliable behavior. -//! -//! \param startAddr is the start address of the memory to unprotect -//! -//! \param endAddr is the end address of the memory to unprotect -//! -//! \note Flash memory is organized by protection by sector sizes. This means -//! that you will only be able to protect/unprotect memory based off -//! 4096 aligned boundaries. -//! -//! \return true if sector protection enabled false otherwise. -// -//***************************************************************************** -extern bool FlashCtl_A_unprotectMemory(uint32_t startAddr, uint32_t endAddr); - -//***************************************************************************** -// -//! Scans over the given memory range and returns false if any of the inclusive -//! memory addresses is protect from writes. -//! -//! \param startAddr is the start address to scan -//! -//! \param endAddr is the end address to scan -//! -//! \return true if sector protection enabled on any of the incluseive memory -//! addresses, false otherwise. -// -//***************************************************************************** -extern bool FlashCtl_A_isMemoryRangeProtected(uint32_t startAddr, - uint32_t endAddr); - -//***************************************************************************** -// -//! Scans over the given memory range and returns false if any of the inclusive -//! memory addresses is protect from writes. -//! -//! \param startAddr is the start address to scan -//! -//! \param endAddr is the end address to scan -//! -//! \return true if sector protection enabled on any of the incluseive memory -//! addresses, false otherwise. -// -//***************************************************************************** -extern bool FlashCtl_A_isMemoryProtected(uint32_t addr); - -//***************************************************************************** -// -//! Verifies a given segment of memory based off either a high (1) or low (0) -//! state. -//! -//! \param verifyAddr Start address where verification will begin -//! -//! \param length Length in bytes to verify based off the pattern -//! -//! \param pattern The pattern which verification will check versus. This can -//! either be a low pattern (each register will be checked versus a pattern -//! of 32 zeros, or a high pattern (each register will be checked versus a -//! pattern of 32 ones). Valid values are: FLASH_A_0_PATTERN, FLASH_A_1_PATTERN -//! -//! \note There are no sector/boundary restrictions for this function, -//! however it is encouraged to proved a start address aligned on 32-bit -//! boundaries. Providing an unaligned address will result in unaligned data -//! accesses and detriment efficiency. -//! -//! \note This function is blocking and will not exit until operation has -//! either completed or failed due to an error. Furthermore, given the -//! complex verification requirements of the flash controller, master -//! interrupts are disabled throughout execution of this function. The original -//! interrupt context is saved at the start of execution and restored prior -//! to exit of the API. -//! -//! \note Due to the hardware limitations of the flash controller, this -//! function cannot verify a memory adress in the same flash bank that it -//! is executing from. If using the ROM version of this API (by using the -//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides -//! in flash then special care needs to be taken to ensure no code execution -//! or reads happen in the flash bank being programmed while this API is -//! being executed. -//! -//! \return true if memory verification is successful, false otherwise. -// -//***************************************************************************** -extern bool FlashCtl_A_verifyMemory(void* verifyAddr, uint32_t length, - uint_fast8_t pattern); - -//***************************************************************************** -// -//! Performs a mass erase on all unprotected flash sectors. Protected sectors -//! are ignored. -//! -//! \note This function is blocking and will not exit until operation has -//! either completed or failed due to an error. Furthermore, given the -//! complex verification requirements of the flash controller, master -//! interrupts are disabled throughout execution of this function. The original -//! interrupt context is saved at the start of execution and restored prior -//! to exit of the API. -//! -//! \note Due to the hardware limitations of the flash controller, this -//! function cannot erase a memory adress in the same flash bank that it -//! is executing from. If using the ROM version of this API (by using the -//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides -//! in flash then special care needs to be taken to ensure no code execution -//! or reads happen in the flash bank being programmed while this API is -//! being executed. -//! -//! \return true if mass erase completes successfully, false otherwise -// -//***************************************************************************** -extern bool FlashCtl_A_performMassErase(void); - -//***************************************************************************** -// -//! Initiates a mass erase and returns control back to the program. This is a -//! non-blocking function, however it is the user's responsibility to perform -//! the necessary verification requirements after the interrupt is set to -//! signify completion. -//! -//! \return None -// -//***************************************************************************** -extern void FlashCtl_A_initiateMassErase(void); - -//***************************************************************************** -// -//! Erases a sector of MAIN or INFO flash memory. -//! -//! \param addr The start of the sector to erase. Note that with flash, -//! the minimum allowed size that can be erased is a flash sector -//! (which is 4KB on the MSP432 family). If an address is provided to -//! this function which is not on a 4KB boundary, the entire sector -//! will still be erased. -//! -//! \note This function is blocking and will not exit until operation has -//! either completed or failed due to an error. Furthermore, given the -//! complex verification requirements of the flash controller, master -//! interrupts are disabled throughout execution of this function. The original -//! interrupt context is saved at the start of execution and restored prior -//! to exit of the API. -//! -//! \note Due to the hardware limitations of the flash controller, this -//! function cannot erase a memory adress in the same flash bank that it -//! is executing from. If using the ROM version of this API (by using the -//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides -//! in flash then special care needs to be taken to ensure no code execution -//! or reads happen in the flash bank being programmed while this API is -//! being executed. -//! -//! \return true if sector erase is successful, false otherwise. -// -//***************************************************************************** -extern bool FlashCtl_A_eraseSector(uint32_t addr); - -//***************************************************************************** -// -//! Program a portion of flash memory with the provided data -//! -//! \param src Pointer to the data source to program into flash -//! -//! \param dest Pointer to the destination in flash to program -//! -//! \param length Length in bytes to program -//! -//! \note There are no sector/boundary restrictions for this function, -//! however it is encouraged to proved a start address aligned on 32-bit -//! boundaries. Providing an unaligned address will result in unaligned data -//! accesses and detriment efficiency. -//! -//! \note This function is blocking and will not exit until operation has -//! either completed or failed due to an error. Furthermore, given the -//! complex verification requirements of the flash controller, master -//! interrupts are disabled throughout execution of this function. The original -//! interrupt context is saved at the start of execution and restored prior -//! to exit of the API. -//! -//! \note Due to the hardware limitations of the flash controller, this -//! function cannot program a memory adress in the same flash bank that it -//! is executing from. If using the ROM version of this API (by using the -//! (ROM_ or MAP_ prefixes) this is a don't care, however if this API resides -//! in flash then special care needs to be taken to ensure no code execution -//! or reads happen in the flash bank being programmed while this API is -//! being executed. -//! -//! \return Whether or not the program succeeded -// -//***************************************************************************** -extern bool FlashCtl_A_programMemory(void* src, void* dest, - uint32_t length); - -//***************************************************************************** -// -//! Setups pre/post verification of burst and regular flash programming -//! instructions. Note that this API is for advanced users that are programming -//! their own flash drivers. The program/erase APIs are not affected by this -//! setting and take care of the verification requirements. -//! -//! \param verificationSetting Verification setting to set. This value can -//! be a bitwise OR of the following values: -//! - \b FLASH_A_BURSTPOST, -//! - \b FLASH_A_BURSTPRE, -//! - \b FLASH_A_REGPRE, -//! - \b FLASH_A_REGPOST -//! - \b FLASH_A_NOVER No verification enabled -//! - \b FLASH_A_FULLVER Full verification enabled -//! -//! \return none -// -//***************************************************************************** -extern void FlashCtl_A_setProgramVerification(uint32_t verificationSetting); - -//***************************************************************************** -// -//! Clears pre/post verification of burst and regular flash programming -//! instructions. Note that this API is for advanced users that are programming -//! their own flash drivers. The program/erase APIs are not affected by this -//! setting and take care of the verification requirements. -//! -//! \param verificationSetting Verification setting to clear. This value can -//! be a bitwise OR of the following values: -//! - \b FLASH_A_BURSTPOST, -//! - \b FLASH_A_BURSTPRE, -//! - \b FLASH_A_REGPRE, -//! - \b FLASH_A_REGPOST -//! - \b FLASH_A_NOVER No verification enabled -//! - \b FLASH_A_FULLVER Full verification enabled -//! -//! \return none -// -//***************************************************************************** -extern void FlashCtl_A_clearProgramVerification( - uint32_t verificationSetting); - -//***************************************************************************** -// -//! Enables word programming of flash memory. -//! -//! This function will enable word programming of the flash memory and set the -//! mode of behavior when the flash write occurs. -//! -//! \param mode The mode specifies the behavior of the flash controller when -//! programming words to flash. In \b FLASH_A_IMMEDIATE_WRITE_MODE, the -//! program operation happens immediately on the write to flash while -//! in \b FLASH_A_COLLATED_WRITE_MODE the write will be delayed until a full -//! 128-bits have been collated. Possible values include: -//! - \b FLASH_A_IMMEDIATE_WRITE_MODE -//! - \b FLASH_A_COLLATED_WRITE_MODE -//! -//! -//! Refer to the user's guide for further documentation. -//! -//! \return none -// -//***************************************************************************** -extern void FlashCtl_A_enableWordProgramming(uint32_t mode); - -//***************************************************************************** -// -//! Disables word programming of flash memory. -//! -//! Refer to FlashCtl_A_enableWordProgramming and the user's guide for description -//! on the difference between full word and immediate programming -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_A_disableWordProgramming(void); - -//***************************************************************************** -// -//! Returns if word programming mode is enabled (and if it is, the specific mode) -//! -//! Refer to FlashCtl_A_enableWordProgramming and the user's guide for description -//! on the difference between full word and immediate programming -//! -//! \return a zero value if word programming is disabled, -//! - \b FLASH_A_IMMEDIATE_WRITE_MODE -//! - \b FLASH_A_COLLATED_WRITE_MODE -//! -// -//***************************************************************************** -extern uint32_t FlashCtl_A_isWordProgrammingEnabled(void); - -//***************************************************************************** -// -//! Sets the flash read mode to be used by default flash read operations. -//! Note that the proper wait states must be set prior to entering this -//! function. -//! -//! \param flashBank Flash bank to set read mode for. Valid values are: -//! - \b FLASH_A_BANK0 -//! - \b FLASH_A_BANK1 -//! -//! \param readMode The read mode to set. Valid values are: -//! - \b FLASH_A_NORMAL_READ_MODE, -//! - \b FLASH_A_MARGIN0_READ_MODE, -//! - \b FLASH_A_MARGIN1_READ_MODE, -//! - \b FLASH_A_PROGRAM_VERIFY_READ_MODE, -//! - \b FLASH_A_ERASE_VERIFY_READ_MODE, -//! - \b FLASH_A_LEAKAGE_VERIFY_READ_MODE, -//! - \b FLASH_A_MARGIN0B_READ_MODE, -//! - \b FLASH_A_MARGIN1B_READ_MODE -//! -//! \return None. -// -//***************************************************************************** -extern bool FlashCtl_A_setReadMode(uint32_t flashBank, uint32_t readMode); - -//***************************************************************************** -// -//! Gets the flash read mode to be used by default flash read operations. -//! -//! \param flashBank Flash bank to set read mode for. Valid values are: -//! - \b FLASH_A_BANK0 -//! - \b FLASH_A_BANK1 -//! -//! \return Returns the read mode to set. Valid values are: -//! - \b FLASH_A_NORMAL_READ_MODE, -//! - \b FLASH_A_MARGIN0_READ_MODE, -//! - \b FLASH_A_MARGIN1_READ_MODE, -//! - \b FLASH_A_PROGRAM_VERIFY_READ_MODE, -//! - \b FLASH_A_ERASE_VERIFY_READ_MODE, -//! - \b FLASH_A_LEAKAGE_VERIFY_READ_MODE, -//! - \b FLASH_A_MARGIN0B_READ_MODE, -//! - \b FLASH_A_MARGIN1B_READ_MODE -//! -// -//***************************************************************************** -extern uint32_t FlashCtl_A_getReadMode(uint32_t flashBank); - -//***************************************************************************** -// -//! Changes the number of wait states that are used by the flash controller -//! for read operations. When changing frequency ranges of the clock, this -//! functions must be used in order to allow for readable flash memory. -//! -//! \param waitState The number of wait states to set. Note that only -//! bits 0-3 are used. -//! -//! \param flashBank Flash bank to set wait state for. Valid values are: -//! - \b FLASH_A_BANK0 -//! - \b FLASH_A_BANK1 -//! -// -//***************************************************************************** -extern void FlashCtl_A_setWaitState(uint32_t bank, uint32_t waitState); - -//***************************************************************************** -// -//! Returns the set number of flash wait states for the given flash bank. -//! -//! \param flashBank Flash bank to set wait state for. Valid values are: -//! - \b FLASH_A_BANK0 -//! - \b FLASH_A_BANK1 -//! -//! \return The wait state setting for the specified flash bank -// -//***************************************************************************** -extern uint32_t FlashCtl_A_getWaitState(uint32_t bank); - -//***************************************************************************** -// -//! Enables individual flash control interrupt sources. -//! -//! \param flags is a bit mask of the interrupt sources to be enabled. Must -//! be a logical OR of: -//! - \b FLASH_A_PROGRAM_ERROR, -//! - \b FLASH_A_BENCHMARK_INT, -//! - \b FLASH_A_ERASE_COMPLETE, -//! - \b FLASH_A_BRSTPRGM_COMPLETE, -//! - \b FLASH_A_WRDPRGM_COMPLETE, -//! - \b FLASH_A_POSTVERIFY_FAILED, -//! - \b FLASH_A_PREVERIFY_FAILED, -//! - \b FLASH_A_BRSTRDCMP_COMPLETE -//! -//! This function enables the indicated flash system interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_A_enableInterrupt(uint32_t flags); - -//***************************************************************************** -// -//! Disables individual flash system interrupt sources. -//! -//! \param flags is a bit mask of the interrupt sources to be disabled. Must -//! be a logical OR of: -//! - \b FLASH_A_PROGRAM_ERROR, -//! - \b FLASH_A_BENCHMARK_INT, -//! - \b FLASH_A_ERASE_COMPLETE, -//! - \b FLASH_A_BRSTPRGM_COMPLETE, -//! - \b FLASH_A_WRDPRGM_COMPLETE, -//! - \b FLASH_A_POSTVERIFY_FAILED, -//! - \b FLASH_A_PREVERIFY_FAILED, -//! - \b FLASH_A_BRSTRDCMP_COMPLETE -//! -//! This function disables the indicated flash system interrupt sources. -//! Only the sources that are enabled can be reflected to the processor -//! interrupt; disabled sources have no effect on the processor. -//! -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_A_disableInterrupt(uint32_t flags); - -//***************************************************************************** -// -//! Gets the current interrupt status masked with the enabled interrupts. -//! This function is useful to call in ISRs to get a list -//! of pending interrupts that are actually enabled and could have caused the -//! ISR. -//! -//! \return The current interrupt status, enumerated as a bit field of -//! - \b FLASH_A_PROGRAM_ERROR, -//! - \b FLASH_A_BENCHMARK_INT, -//! - \b FLASH_A_ERASE_COMPLETE, -//! - \b FLASH_A_BRSTPRGM_COMPLETE, -//! - \b FLASH_A_WRDPRGM_COMPLETE, -//! - \b FLASH_A_POSTVERIFY_FAILED, -//! - \b FLASH_A_PREVERIFY_FAILED, -//! - \b FLASH_A_BRSTRDCMP_COMPLETE -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -// -//***************************************************************************** -extern uint32_t FlashCtl_A_getEnabledInterruptStatus(void); - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \return The current interrupt status, enumerated as a bit field of: -//! - \b FLASH_A_PROGRAM_ERROR, -//! - \b FLASH_A_BENCHMARK_INT, -//! - \b FLASH_A_ERASE_COMPLETE, -//! - \b FLASH_A_BRSTPRGM_COMPLETE, -//! - \b FLASH_A_WRDPRGM_COMPLETE, -//! - \b FLASH_A_POSTVERIFY_FAILED, -//! - \b FLASH_A_PREVERIFY_FAILED, -//! - \b FLASH_A_BRSTRDCMP_COMPLETE -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -// -//***************************************************************************** -extern uint32_t FlashCtl_A_getInterruptStatus(void); - -//***************************************************************************** -// -//! Clears flash system interrupt sources. -//! -//! \param flags is a bit mask of the interrupt sources to be cleared. Must -//! be a logical OR of: -//! - \b FLASH_A_PROGRAM_ERROR, -//! - \b FLASH_A_BENCHMARK_INT, -//! - \b FLASH_A_ERASE_COMPLETE, -//! - \b FLASH_A_BRSTPRGM_COMPLETE, -//! - \b FLASH_A_WRDPRGM_COMPLETE, -//! - \b FLASH_A_POSTVERIFY_FAILED, -//! - \b FLASH_A_PREVERIFY_FAILED, -//! - \b FLASH_A_BRSTRDCMP_COMPLETE -//! -//! The specified flash system interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep it from being called again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_A_clearInterruptFlag(uint32_t flags); - -//***************************************************************************** -// -//! Registers an interrupt handler for flash clock system interrupt. -//! -//! \param intHandler is a pointer to the function to be called when the clock -//! system interrupt occurs. -//! -//! This function registers the handler to be called when a clock system -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific flash controller interrupts must be enabled -//! via FlashCtl_A_enableInterrupt(). It is the interrupt handler's -//! responsibility to clear the interrupt source via -//! FlashCtl_A_clearInterruptFlag(). -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_A_registerInterrupt(void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the flash system. -//! -//! This function unregisters the handler to be called when a clock system -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void FlashCtl_A_unregisterInterrupt(void); - -//***************************************************************************** -// -//! Initiates a sector erase of MAIN or INFO flash memory. Note that this -//! function simply initaites the sector erase, but does no verification -//! which is required by the flash controller. The user must manually set -//! and enable interrupts on the flash controller to fire on erase completion -//! and then use the FlashCtl_A_verifyMemory function to verify that the sector -//! was actually erased -//! -//! \param addr The start of the sector to erase. Note that with flash, -//! the minimum allowed size that can be erased is a flash sector -//! (which is 4KB on the MSP432 family). If an address is provided to -//! this function which is not on a 4KB boundary, the entire sector -//! will still be erased. -//! -//! \return None -// -//***************************************************************************** -extern void FlashCtl_A_initiateSectorErase(uint32_t addr); - -/* The following functions are advanced functions that are used by the flash - * driver to remask a failed bit in the event of a post or pre verification - * failure. They are meant to be advanced functions and should not be used - * by the majority of users (unless you are writing your own flash driver). - */ -extern uint8_t __FlashCtl_A_remaskData8Post(uint8_t data, uint32_t addr); -extern uint8_t __FlashCtl_A_remaskData8Pre(uint8_t data, uint32_t addr); -extern uint32_t __FlashCtl_A_remaskData32Post(uint32_t data, uint32_t addr); -extern uint32_t __FlashCtl_A_remaskData32Pre(uint32_t data, uint32_t addr); -extern void __FlashCtl_A_remaskBurstDataPost(uint32_t addr, uint32_t size); -extern void __FlashCtl_A_remaskBurstDataPre(uint32_t addr, uint32_t size); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* __MCU_HAS_FLCTL_A__ */ - -#endif // __FLASH_A_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/fpu.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/fpu.c deleted file mode 100644 index 05a7e787d4c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/fpu.c +++ /dev/null @@ -1,110 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include - -void FPU_enableModule(void) -{ - // - // Enable the coprocessors used by the floating-point unit. - // - SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP11_MASK | SCB_CPACR_CP10_MASK)) - | SCB_CPACR_CP11_MASK | SCB_CPACR_CP10_MASK); -} - -void FPU_disableModule(void) -{ - // - // Disable the coprocessors used by the floating-point unit. - // - SCB->CPACR = ((SCB->CPACR & ~(SCB_CPACR_CP10_MASK | SCB_CPACR_CP11_MASK))); -} - -void FPU_enableStacking(void) -{ - // - // Enable automatic state preservation for the floating-point unit, and - // disable lazy state preservation (meaning that the floating-point state - // is always stacked when floating-point instructions are used). - // - FPU->FPCCR = (FPU->FPCCR & ~FPU_FPCCR_LSPEN_Msk) | FPU_FPCCR_ASPEN_Msk; -} - -void FPU_enableLazyStacking(void) -{ - // - // Enable automatic and lazy state preservation for the floating-point - // unit. - // - FPU->FPCCR |= FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk; -} - -void FPU_disableStacking(void) -{ - // - // Disable automatic and lazy state preservation for the floating-point - // unit. - // - FPU->FPCCR &= ~(FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk); -} - -void FPU_setHalfPrecisionMode(uint32_t mode) -{ - // - // Set the half-precision floating-point format. - // - FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_AHP_Msk)) | mode; -} - -void FPU_setNaNMode(uint32_t mode) -{ - // - // Set the NaN mode. - // - FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_DN_Msk)) | mode; -} - -void FPU_setFlushToZeroMode(uint32_t mode) -{ - // - // Set the flush-to-zero mode. - // - FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_FZ_Msk)) | mode; -} - -void FPU_setRoundingMode(uint32_t mode) -{ - // - // Set the rounding mode. - // - FPU->FPDSCR = (FPU->FPDSCR & ~(FPU_FPDSCR_RMode_Msk)) | mode; -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/fpu.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/fpu.h deleted file mode 100644 index eab3db3a0d4..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/fpu.h +++ /dev/null @@ -1,280 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __FPU_H__ -#define __FPU_H__ - -//***************************************************************************** -// -//! -//! \addtogroup fpu_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -//***************************************************************************** -// -// Values that can be passed to FPUHalfPrecisionSet as the mode parameter. -// -//***************************************************************************** -#define FPU_HALF_IEEE 0x00000000 -#define FPU_HALF_ALTERNATE 0x04000000 - -//***************************************************************************** -// -// Values that can be passed to FPU_setNaNMode as the mode parameter. -// -//***************************************************************************** -#define FPU_NAN_PROPAGATE 0x00000000 -#define FPU_NAN_DEFAULT 0x02000000 - -//***************************************************************************** -// -// Values that can be passed to FPU_setFlushToZeroMode as the mode parameter. -// -//***************************************************************************** -#define FPU_FLUSH_TO_ZERO_DIS 0x00000000 -#define FPU_FLUSH_TO_ZERO_EN 0x01000000 - -//***************************************************************************** -// -// Values that can be passed to FPU_setRoundingMode as the mode parameter. -// -//***************************************************************************** -#define FPU_ROUND_NEAREST 0x00000000 -#define FPU_ROUND_POS_INF 0x00400000 -#define FPU_ROUND_NEG_INF 0x00800000 -#define FPU_ROUND_ZERO 0x00c00000 - -//***************************************************************************** -// -//! Enables the floating-point unit. -//! -//! This function enables the floating-point unit, allowing the floating-point -//! instructions to be executed. This function must be called prior to -//! performing any hardware floating-point operations; failure to do so results -//! in a NOCP usage fault. -//! -//! \return None. -// -//***************************************************************************** -extern void FPU_enableModule(void); - -//***************************************************************************** -// -//! Disables the floating-point unit. -//! -//! This function disables the floating-point unit, preventing floating-point -//! instructions from executing (generating a NOCP usage fault instead). -//! -//! \return None. -// -//***************************************************************************** -extern void FPU_disableModule(void); - -//***************************************************************************** -// -//! Enables the stacking of floating-point registers. -//! -//! This function enables the stacking of floating-point registers s0-s15 when -//! an interrupt is handled. When enabled, space is reserved on the stack for -//! the floating-point context and the floating-point state is saved into this -//! stack space. Upon return from the interrupt, the floating-point context is -//! restored. -//! -//! If the floating-point registers are not stacked, floating-point -//! instructions cannot be safely executed in an interrupt handler because the -//! values of s0-s15 are not likely to be preserved for the interrupted code. -//! On the other hand, stacking the floating-point registers increases the -//! stacking operation from 8 words to 26 words, also increasing the interrupt -//! response latency. -//! -//! \return None. -// -//***************************************************************************** -extern void FPU_enableStacking(void); - -//***************************************************************************** -// -//! Enables the lazy stacking of floating-point registers. -//! -//! This function enables the lazy stacking of floating-point registers s0-s15 -//! when an interrupt is handled. When lazy stacking is enabled, space is -//! reserved on the stack for the floating-point context, but the -//! floating-point state is not saved. If a floating-point instruction is -//! executed from within the interrupt context, the floating-point context is -//! first saved into the space reserved on the stack. On completion of the -//! interrupt handler, the floating-point context is only restored if it was -//! saved (as the result of executing a floating-point instruction). -//! -//! This method provides a compromise between fast interrupt response (because -//! the floating-point state is not saved on interrupt entry) and the ability -//! to use floating-point in interrupt handlers (because the floating-point -//! state is saved if floating-point instructions are used). -//! -//! \return None. -// -//***************************************************************************** -extern void FPU_enableLazyStacking(void); - -//***************************************************************************** -// -//! Disables the stacking of floating-point registers. -//! -//! This function disables the stacking of floating-point registers s0-s15 when -//! an interrupt is handled. When floating-point context stacking is disabled, -//! floating-point operations performed in an interrupt handler destroy the -//! floating-point context of the main thread of execution. -//! -//! \return None. -// -//***************************************************************************** -extern void FPU_disableStacking(void); - -//***************************************************************************** -// -//! Selects the format of half-precision floating-point values. -//! -//! \param mode is the format for half-precision floating-point value, which -//! is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE. -//! -//! This function selects between the IEEE half-precision floating-point -//! representation and the Cortex-M processor alternative representation. The -//! alternative representation has a larger range but does not have a way to -//! encode infinity (positive or negative) or NaN (quiet or signalling). The -//! default setting is the IEEE format. -//! -//! \note Unless this function is called prior to executing any floating-point -//! instructions, the default mode is used. -//! -//! \return None. -// -//***************************************************************************** -extern void FPU_setHalfPrecisionMode(uint32_t mode); - -//***************************************************************************** -// -//! Selects the NaN mode. -//! -//! \param mode is the mode for NaN results; which is -//! either \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT. -//! -//! This function selects the handling of NaN results during floating-point -//! computations. NaNs can either propagate (the default), or they can return -//! the default NaN. -//! -//! \note Unless this function is called prior to executing any floating-point -//! instructions, the default mode is used. -//! -//! \return None. -// -//***************************************************************************** -extern void FPU_setNaNMode(uint32_t mode); - -//***************************************************************************** -// -//! Selects the flush-to-zero mode. -//! -//! \param mode is the flush-to-zero mode; which is either -//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN. -//! -//! This function enables or disables the flush-to-zero mode of the -//! floating-point unit. When disabled (the default), the floating-point unit -//! is fully IEEE compliant. When enabled, values close to zero are treated as -//! zero, greatly improving the execution speed at the expense of some accuracy -//! (as well as IEEE compliance). -//! -//! \note Unless this function is called prior to executing any floating-point -//! instructions, the default mode is used. -//! -//! \return None. -// -//***************************************************************************** -extern void FPU_setFlushToZeroMode(uint32_t mode); - -//***************************************************************************** -// -//! Selects the rounding mode for floating-point results. -//! -//! \param mode is the rounding mode. -//! -//! This function selects the rounding mode for floating-point results. After -//! a floating-point operation, the result is rounded toward the specified -//! value. The default mode is \b FPU_ROUND_NEAREST. -//! -//! The following rounding modes are available (as specified by \e mode): -//! -//! - \b FPU_ROUND_NEAREST - round toward the nearest value -//! - \b FPU_ROUND_POS_INF - round toward positive infinity -//! - \b FPU_ROUND_NEG_INF - round toward negative infinity -//! - \b FPU_ROUND_ZERO - round toward zero -//! -//! \note Unless this function is called prior to executing any floating-point -//! instructions, the default mode is used. -//! -//! \return None. -// -//***************************************************************************** -extern void FPU_setRoundingMode(uint32_t mode); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - - -#endif // __FPU_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/gpio.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/gpio.c deleted file mode 100644 index a4f81fd8a24..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/gpio.c +++ /dev/null @@ -1,350 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/* Standard Includes */ -#include - -/* DriverLib Includes */ -#include -#include -#include - - -static const uint32_t GPIO_PORT_TO_INT[] = -{ 0x00, -INT_PORT1, -INT_PORT2, -INT_PORT3, -INT_PORT4, -INT_PORT5, -INT_PORT6 }; - -static const uint32_t GPIO_PORT_TO_BASE[] = -{ 0x00, - (uint32_t)P1, - (uint32_t)P1+1, - (uint32_t)P3, - (uint32_t)P3+1, - (uint32_t)P5, - (uint32_t)P5+1, - (uint32_t)P7, - (uint32_t)P7+1, - (uint32_t)P9, - (uint32_t)P9+1, - (uint32_t)PJ -}; - -void GPIO_setAsOutputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins) -{ - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins; - HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins; - HWREG16(baseAddress + OFS_LIB_PADIR) |= selectedPins; -} - - -void GPIO_setAsInputPin(uint_fast8_t selectedPort, uint_fast16_t selectedPins) -{ - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins; - HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins; - HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins; - HWREG16(baseAddress + OFS_LIB_PAREN) &= ~selectedPins; -} - - -void GPIO_setAsPeripheralModuleFunctionOutputPin(uint_fast8_t selectedPort, - uint_fast16_t selectedPins, uint_fast8_t mode) -{ - - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG16(baseAddress + OFS_LIB_PADIR) |= selectedPins; - switch (mode) - { - case GPIO_PRIMARY_MODULE_FUNCTION: - HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins; - HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins; - break; - case GPIO_SECONDARY_MODULE_FUNCTION: - HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins; - HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins; - break; - case GPIO_TERTIARY_MODULE_FUNCTION: - HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins; - HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins; - break; - } -} - - -void GPIO_setAsPeripheralModuleFunctionInputPin(uint_fast8_t selectedPort, - uint_fast16_t selectedPins, uint_fast8_t mode) -{ - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins; - switch (mode) - { - case GPIO_PRIMARY_MODULE_FUNCTION: - HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins; - HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins; - break; - case GPIO_SECONDARY_MODULE_FUNCTION: - HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins; - HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins; - break; - case GPIO_TERTIARY_MODULE_FUNCTION: - HWREG16(baseAddress + OFS_LIB_PASEL0) |= selectedPins; - HWREG16(baseAddress + OFS_LIB_PASEL1) |= selectedPins; - break; - } -} - - -void GPIO_setOutputHighOnPin(uint_fast8_t selectedPort, - uint_fast16_t selectedPins) -{ - - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG16(baseAddress + OFS_LIB_PAOUT) |= selectedPins; -} - - -void GPIO_setOutputLowOnPin(uint_fast8_t selectedPort, - uint_fast16_t selectedPins) -{ - - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG16(baseAddress + OFS_LIB_PAOUT) &= ~selectedPins; -} - - -void GPIO_toggleOutputOnPin(uint_fast8_t selectedPort, - uint_fast16_t selectedPins) -{ - - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG16(baseAddress + OFS_LIB_PAOUT) ^= selectedPins; -} - - -void GPIO_setAsInputPinWithPullDownResistor(uint_fast8_t selectedPort, - uint_fast16_t selectedPins) -{ - - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins; - HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins; - - HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins; - HWREG16(baseAddress + OFS_LIB_PAREN) |= selectedPins; - HWREG16(baseAddress + OFS_LIB_PAOUT) &= ~selectedPins; -} - - -void GPIO_setAsInputPinWithPullUpResistor(uint_fast8_t selectedPort, - uint_fast16_t selectedPins) -{ - - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG16(baseAddress + OFS_LIB_PASEL0) &= ~selectedPins; - HWREG16(baseAddress + OFS_LIB_PASEL1) &= ~selectedPins; - HWREG16(baseAddress + OFS_LIB_PADIR) &= ~selectedPins; - HWREG16(baseAddress + OFS_LIB_PAREN) |= selectedPins; - HWREG16(baseAddress + OFS_LIB_PAOUT) |= selectedPins; -} - - -uint8_t GPIO_getInputPinValue(uint_fast8_t selectedPort, - uint_fast16_t selectedPins) -{ - uint_fast16_t inputPinValue; - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - inputPinValue = HWREG16(baseAddress + OFS_LIB_PAIN) & (selectedPins); - - if (inputPinValue > 0) - return GPIO_INPUT_PIN_HIGH; - return GPIO_INPUT_PIN_LOW; -} - - -void GPIO_enableInterrupt(uint_fast8_t selectedPort, uint_fast16_t selectedPins) -{ - - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG16(baseAddress + OFS_LIB_PAIE) |= selectedPins; -} - - -void GPIO_disableInterrupt(uint_fast8_t selectedPort, - uint_fast16_t selectedPins) -{ - - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG16(baseAddress + OFS_LIB_PAIE) &= ~selectedPins; -} - - -uint_fast16_t GPIO_getInterruptStatus(uint_fast8_t selectedPort, - uint_fast16_t selectedPins) -{ - - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - return HWREG16(baseAddress + OFS_LIB_PAIFG) & selectedPins; -} - - -void GPIO_clearInterruptFlag(uint_fast8_t selectedPort, - uint_fast16_t selectedPins) -{ - - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - - HWREG16(baseAddress + OFS_LIB_PAIFG) &= ~selectedPins; -} - - -void GPIO_interruptEdgeSelect(uint_fast8_t selectedPort, - uint_fast16_t selectedPins, uint_fast8_t edgeSelect) -{ - - uint32_t baseAddress = GPIO_PORT_TO_BASE[selectedPort]; - - - if (GPIO_LOW_TO_HIGH_TRANSITION == edgeSelect) - HWREG16(baseAddress + OFS_LIB_PAIES) &= ~selectedPins; - else - HWREG16(baseAddress + OFS_LIB_PAIES) |= selectedPins; -} - -uint_fast16_t GPIO_getEnabledInterruptStatus(uint_fast8_t selectedPort) -{ - uint_fast16_t pendingInts; - uint32_t baseAddr; - - pendingInts = GPIO_getInterruptStatus(selectedPort, 0xFFFF); - baseAddr = GPIO_PORT_TO_BASE[selectedPort]; - - ASSERT(baseAddr != 0xFFFF); - - switch (selectedPort) - { - case GPIO_PORT_P1: - case GPIO_PORT_P3: - case GPIO_PORT_P5: - case GPIO_PORT_P7: - case GPIO_PORT_P9: - return (HWREG8(baseAddr + OFS_LIB_P1IE) & pendingInts); - case GPIO_PORT_P2: - case GPIO_PORT_P4: - case GPIO_PORT_P6: - case GPIO_PORT_P8: - case GPIO_PORT_P10: - return (HWREG8(baseAddr + OFS_LIB_P2IE) & pendingInts); - case GPIO_PORT_PJ: - return (HWREG16(baseAddr + OFS_LIB_PAIE) & pendingInts); - default: - return 0; - } -} - - -void GPIO_setDriveStrengthHigh(uint_fast8_t selectedPort, - uint_fast8_t selectedPins) -{ - uint32_t baseAddr; - - baseAddr = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG8(baseAddr + OFS_LIB_PADS) |= selectedPins; - -} - -void GPIO_setDriveStrengthLow(uint_fast8_t selectedPort, - uint_fast8_t selectedPins) -{ - uint32_t baseAddr; - - baseAddr = GPIO_PORT_TO_BASE[selectedPort]; - - HWREG8(baseAddr + OFS_LIB_PADS) &= ~selectedPins; - -} - -void GPIO_registerInterrupt(uint_fast8_t selectedPort, void (*intHandler)(void)) -{ - uint32_t wPortInt; - - wPortInt = GPIO_PORT_TO_INT[selectedPort]; - - // - // Register the interrupt handler, returning an error if an error occurs. - // - Interrupt_registerInterrupt(wPortInt, intHandler); - - // - // Enable the system control interrupt. - // - Interrupt_enableInterrupt(wPortInt); -} - - -void GPIO_unregisterInterrupt(uint_fast8_t selectedPort) -{ - uint32_t wPortInt; - - wPortInt = GPIO_PORT_TO_INT[selectedPort]; - - // - // Disable the interrupt. - // - Interrupt_disableInterrupt(wPortInt); - - // - // Unregister the interrupt handler. - // - Interrupt_unregisterInterrupt(wPortInt); -} - - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/gpio.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/gpio.h deleted file mode 100644 index 1013515761c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/gpio.h +++ /dev/null @@ -1,1033 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __GPIO_H__ -#define __GPIO_H__ - -//***************************************************************************** -// -//! \addtogroup gpio_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#define GPIO_PORT_P1 1 -#define GPIO_PORT_P2 2 -#define GPIO_PORT_P3 3 -#define GPIO_PORT_P4 4 -#define GPIO_PORT_P5 5 -#define GPIO_PORT_P6 6 -#define GPIO_PORT_P7 7 -#define GPIO_PORT_P8 8 -#define GPIO_PORT_P9 9 -#define GPIO_PORT_P10 10 -#define GPIO_PORT_PA 1 -#define GPIO_PORT_PB 3 -#define GPIO_PORT_PC 5 -#define GPIO_PORT_PD 7 -#define GPIO_PORT_PE 9 -#define GPIO_PORT_PJ 11 - - -#define GPIO_PIN0 (0x0001) -#define GPIO_PIN1 (0x0002) -#define GPIO_PIN2 (0x0004) -#define GPIO_PIN3 (0x0008) -#define GPIO_PIN4 (0x0010) -#define GPIO_PIN5 (0x0020) -#define GPIO_PIN6 (0x0040) -#define GPIO_PIN7 (0x0080) -#define GPIO_PIN8 (0x0100) -#define GPIO_PIN9 (0x0200) -#define GPIO_PIN10 (0x0400) -#define GPIO_PIN11 (0x0800) -#define GPIO_PIN12 (0x1000) -#define GPIO_PIN13 (0x2000) -#define GPIO_PIN14 (0x4000) -#define GPIO_PIN15 (0x8000) -#define PIN_ALL8 (0xFF) -#define PIN_ALL16 (0xFFFF) - -#define GPIO_PRIMARY_MODULE_FUNCTION (0x01) -#define GPIO_SECONDARY_MODULE_FUNCTION (0x02) -#define GPIO_TERTIARY_MODULE_FUNCTION (0x03) - -#define GPIO_HIGH_TO_LOW_TRANSITION (0x01) -#define GPIO_LOW_TO_HIGH_TRANSITION (0x00) - -#define GPIO_INPUT_PIN_HIGH (0x01) -#define GPIO_INPUT_PIN_LOW (0x00) - -/* DriverLib internal GPIO register offset for optimized performance */ -#define OFS_LIB_PAIN ((uint32_t)&P1->IN - (uint32_t)P1) -#define OFS_LIB_PAOUT ((uint32_t)&P1->OUT - (uint32_t)P1) -#define OFS_LIB_PADIR ((uint32_t)&P1->DIR - (uint32_t)P1) -#define OFS_LIB_PAREN ((uint32_t)&P1->REN - (uint32_t)P1) -#define OFS_LIB_PADS ((uint32_t)&P1->DS - (uint32_t)P1) -#define OFS_LIB_PASEL0 ((uint32_t)&P1->SEL0 - (uint32_t)P1) -#define OFS_LIB_PASEL1 ((uint32_t)&P1->SEL1 - (uint32_t)P1) -#define OFS_LIB_PAIE ((uint32_t)&P1->IE - (uint32_t)P1) -#define OFS_LIB_PAIES ((uint32_t)&P1->IES - (uint32_t)P1) -#define OFS_LIB_PAIFG ((uint32_t)&P1->IFG - (uint32_t)P1) -#define OFS_LIB_P1IE ((uint32_t)&P1->IE - (uint32_t)P1) -#define OFS_LIB_P2IE OFS_LIB_P1IE - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! \brief This function configures the selected Pin as output pin -//! -//! This function selected pins on a selected port as output pins. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_P3 -//! - \b GPIO_PORT_P4 -//! - \b GPIO_PORT_P5 -//! - \b GPIO_PORT_P6 -//! - \b GPIO_PORT_P7 -//! - \b GPIO_PORT_P8 -//! - \b GPIO_PORT_P9 -//! - \b GPIO_PORT_P10 -//! - \b GPIO_PORT_P11 -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! -//! Modified bits of \b PxDIR register and bits of \b PxSEL register. -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_setAsOutputPin(uint_fast8_t selectedPort, - uint_fast16_t selectedPins); - -//***************************************************************************** -// -//! \brief This function configures the selected Pin as input pin -//! -//! This function selected pins on a selected port as input pins. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_P3 -//! - \b GPIO_PORT_P4 -//! - \b GPIO_PORT_P5 -//! - \b GPIO_PORT_P6 -//! - \b GPIO_PORT_P7 -//! - \b GPIO_PORT_P8 -//! - \b GPIO_PORT_P9 -//! - \b GPIO_PORT_P10 -//! - \b GPIO_PORT_P11 -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! -//! Modified bits of \b PxDIR register, bits of \b PxREN register and bits of -//! \b PxSEL register. -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_setAsInputPin(uint_fast8_t selectedPort, - uint_fast16_t selectedPins); - -//***************************************************************************** -// -//! \brief This function configures the peripheral module function in the -//! output direction for the selected pin for either primary, secondary or -//! ternary module function modes -//! -//! This function configures the peripheral module function in the output -//! direction for the selected pin for either primary, secondary or ternary -//! module function modes. Accepted values for mode are -//! GPIO_PRIMARY_MODULE_FUNCTION, GPIO_SECONDARY_MODULE_FUNCTION, and -//! GPIO_TERTIARY_MODULE_FUNCTION -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_P3 -//! - \b GPIO_PORT_P4 -//! - \b GPIO_PORT_P5 -//! - \b GPIO_PORT_P6 -//! - \b GPIO_PORT_P7 -//! - \b GPIO_PORT_P8 -//! - \b GPIO_PORT_P9 -//! - \b GPIO_PORT_P10 -//! - \b GPIO_PORT_P11 -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! \param mode is the specified mode that the pin should be configured for the -//! module function. -//! Valid values are: -//! - \b GPIO_PRIMARY_MODULE_FUNCTION -//! - \b GPIO_SECONDARY_MODULE_FUNCTION -//! - \b GPIO_TERTIARY_MODULE_FUNCTION -//! -//! Modified bits of \b PxDIR register and bits of \b PxSEL register. -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_setAsPeripheralModuleFunctionOutputPin( - uint_fast8_t selectedPort, uint_fast16_t selectedPins, - uint_fast8_t mode); - -//***************************************************************************** -// -//! \brief This function configures the peripheral module function in the input -//! direction for the selected pin for either primary, secondary or ternary -//! module function modes. -//! -//! This function configures the peripheral module function in the input -//! direction for the selected pin for either primary, secondary or ternary -//! module function modes. Accepted values for mode are -//! GPIO_PRIMARY_MODULE_FUNCTION, GPIO_SECONDARY_MODULE_FUNCTION, and -//! GPIO_TERTIARY_MODULE_FUNCTION -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_P3 -//! - \b GPIO_PORT_P4 -//! - \b GPIO_PORT_P5 -//! - \b GPIO_PORT_P6 -//! - \b GPIO_PORT_P7 -//! - \b GPIO_PORT_P8 -//! - \b GPIO_PORT_P9 -//! - \b GPIO_PORT_P10 -//! - \b GPIO_PORT_P11 -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! \param mode is the specified mode that the pin should be configured for the -//! module function. -//! Valid values are: -//! - \b GPIO_PRIMARY_MODULE_FUNCTION -//! - \b GPIO_SECONDARY_MODULE_FUNCTION -//! - \b GPIO_TERTIARY_MODULE_FUNCTION -//! -//! Modified bits of \b PxDIR register and bits of \b PxSEL register. -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_setAsPeripheralModuleFunctionInputPin( - uint_fast8_t selectedPort, uint_fast16_t selectedPins, - uint_fast8_t mode); - -//***************************************************************************** -// -//! \brief This function sets output HIGH on the selected Pin -//! -//! This function sets output HIGH on the selected port's pin. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_P3 -//! - \b GPIO_PORT_P4 -//! - \b GPIO_PORT_P5 -//! - \b GPIO_PORT_P6 -//! - \b GPIO_PORT_P7 -//! - \b GPIO_PORT_P8 -//! - \b GPIO_PORT_P9 -//! - \b GPIO_PORT_P10 -//! - \b GPIO_PORT_P11 -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! -//! Modified bits of \b PxOUT register. -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_setOutputHighOnPin(uint_fast8_t selectedPort, - uint_fast16_t selectedPins); - -//***************************************************************************** -// -//! \brief This function sets output LOW on the selected Pin -//! -//! This function sets output LOW on the selected port's pin. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_P3 -//! - \b GPIO_PORT_P4 -//! - \b GPIO_PORT_P5 -//! - \b GPIO_PORT_P6 -//! - \b GPIO_PORT_P7 -//! - \b GPIO_PORT_P8 -//! - \b GPIO_PORT_P9 -//! - \b GPIO_PORT_P10 -//! - \b GPIO_PORT_P11 -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_setOutputLowOnPin(uint_fast8_t selectedPort, - uint_fast16_t selectedPins); - -//***************************************************************************** -// -//! \brief This function toggles the output on the selected Pin -//! -//! This function toggles the output on the selected port's pin. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_P3 -//! - \b GPIO_PORT_P4 -//! - \b GPIO_PORT_P5 -//! - \b GPIO_PORT_P6 -//! - \b GPIO_PORT_P7 -//! - \b GPIO_PORT_P8 -//! - \b GPIO_PORT_P9 -//! - \b GPIO_PORT_P10 -//! - \b GPIO_PORT_P11 -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! -//! Modified bits of \b PxOUT register. -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_toggleOutputOnPin(uint_fast8_t selectedPort, - uint_fast16_t selectedPins); - -//***************************************************************************** -// -//! \brief This function sets the selected Pin in input Mode with Pull Down -//! resistor -//! -//! This function sets the selected Pin in input Mode with Pull Down resistor. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_P3 -//! - \b GPIO_PORT_P4 -//! - \b GPIO_PORT_P5 -//! - \b GPIO_PORT_P6 -//! - \b GPIO_PORT_P7 -//! - \b GPIO_PORT_P8 -//! - \b GPIO_PORT_P9 -//! - \b GPIO_PORT_P10 -//! - \b GPIO_PORT_P11 -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! -//! Modified bits of \b PxDIR register, bits of \b PxOUT register and bits of -//! \b PxREN register. -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_setAsInputPinWithPullDownResistor(uint_fast8_t selectedPort, - uint_fast16_t selectedPins); - -//***************************************************************************** -// -//! \brief This function sets the selected Pin in input Mode with Pull Up -//! resistor -//! -//! This function sets the selected Pin in input Mode with Pull Up resistor. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_P3 -//! - \b GPIO_PORT_P4 -//! - \b GPIO_PORT_P5 -//! - \b GPIO_PORT_P6 -//! - \b GPIO_PORT_P7 -//! - \b GPIO_PORT_P8 -//! - \b GPIO_PORT_P9 -//! - \b GPIO_PORT_P10 -//! - \b GPIO_PORT_P11 -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! -//! Modified bits of \b PxDIR register, bits of \b PxOUT register and bits of -//! \b PxREN register. -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_setAsInputPinWithPullUpResistor(uint_fast8_t selectedPort, - uint_fast16_t selectedPins); - -//***************************************************************************** -// -//! \brief This function gets the input value on the selected pin -//! -//! This function gets the input value on the selected pin. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_P3 -//! - \b GPIO_PORT_P4 -//! - \b GPIO_PORT_P5 -//! - \b GPIO_PORT_P6 -//! - \b GPIO_PORT_P7 -//! - \b GPIO_PORT_P8 -//! - \b GPIO_PORT_P9 -//! - \b GPIO_PORT_P10 -//! - \b GPIO_PORT_P11 -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Valid values are: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! -//! \return One of the following: -//! - \b GPIO_INPUT_PIN_HIGH -//! - \b GPIO_INPUT_PIN_LOW -//! \n indicating the status of the pin -// -//***************************************************************************** -extern uint8_t GPIO_getInputPinValue(uint_fast8_t selectedPort, - uint_fast16_t selectedPins); - -//***************************************************************************** -// -//! \brief This function enables the port interrupt on the selected pin -//! -//! This function enables the port interrupt on the selected pin. Note that -//! only Port 1,2, A have this capability. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_PA -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! -//! Modified bits of \b PxIE register. -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_enableInterrupt(uint_fast8_t selectedPort, - uint_fast16_t selectedPins); - -//***************************************************************************** -// -//! \brief This function disables the port interrupt on the selected pin -//! -//! This function disables the port interrupt on the selected pin. Note that -//! only Port 1,2, A have this capability. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_PA -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! -//! Modified bits of \b PxIE register. -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_disableInterrupt(uint_fast8_t selectedPort, - uint_fast16_t selectedPins); - -//***************************************************************************** -// -//! \brief This function gets the interrupt status of the selected pin -//! -//! This function gets the interrupt status of the selected pin. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_PA -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! -//! \return Logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! \n indicating the interrupt status of the selected pins [Default: -//! 0] -// -//***************************************************************************** -extern uint_fast16_t GPIO_getInterruptStatus(uint_fast8_t selectedPort, - uint_fast16_t selectedPins); - -//***************************************************************************** -// -//! \brief This function clears the interrupt flag on the selected pin -//! -//! This function clears the interrupt flag on the selected pin. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_PA -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! -//! Modified bits of \b PxIFG register. -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_clearInterruptFlag(uint_fast8_t selectedPort, - uint_fast16_t selectedPins); - -//***************************************************************************** -// -//! \brief This function selects on what edge the port interrupt flag should be -//! set for a transition -//! -//! This function selects on what edge the port interrupt flag should be set -//! for a transition. Values for edgeSelect should be -//! GPIO_LOW_TO_HIGH_TRANSITION or GPIO_HIGH_TO_LOW_TRANSITION. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_P3 -//! - \b GPIO_PORT_P4 -//! - \b GPIO_PORT_P5 -//! - \b GPIO_PORT_P6 -//! - \b GPIO_PORT_P7 -//! - \b GPIO_PORT_P8 -//! - \b GPIO_PORT_P9 -//! - \b GPIO_PORT_P10 -//! - \b GPIO_PORT_P11 -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Mask value is the logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15 -//! \param edgeSelect specifies what transition sets the interrupt flag -//! Valid values are: -//! - \b GPIO_HIGH_TO_LOW_TRANSITION -//! - \b GPIO_LOW_TO_HIGH_TRANSITION -//! -//! Modified bits of \b PxIES register. -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_interruptEdgeSelect(uint_fast8_t selectedPort, - uint_fast16_t selectedPins, uint_fast8_t edgeSelect); - -//***************************************************************************** -// -//! \brief This function gets the interrupt status of the provided PIN and -//! masks it with the interrupts that are actually enabled. This is -//! useful for inside ISRs where the status of only the enabled -//! interrupts needs to be checked. -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1 -//! - \b GPIO_PORT_P2 -//! - \b GPIO_PORT_P3 -//! - \b GPIO_PORT_P4 -//! - \b GPIO_PORT_P5 -//! - \b GPIO_PORT_P6 -//! - \b GPIO_PORT_P7 -//! - \b GPIO_PORT_P8 -//! - \b GPIO_PORT_P9 -//! - \b GPIO_PORT_P10 -//! - \b GPIO_PORT_P11 -//! - \b GPIO_PORT_PJ -//! -//! \return Logical OR of any of the following: -//! - \b GPIO_PIN0 -//! - \b GPIO_PIN1 -//! - \b GPIO_PIN2 -//! - \b GPIO_PIN3 -//! - \b GPIO_PIN4 -//! - \b GPIO_PIN5 -//! - \b GPIO_PIN6 -//! - \b GPIO_PIN7 -//! - \b GPIO_PIN8 -//! - \b GPIO_PIN9 -//! - \b GPIO_PIN10 -//! - \b GPIO_PIN11 -//! - \b GPIO_PIN12 -//! - \b GPIO_PIN13 -//! - \b GPIO_PIN14 -//! - \b GPIO_PIN15, -//! - \b PIN_ALL8, -//! - \b PIN_ALL16 -//! \n indicating the interrupt status of the selected pins [Default: -//! 0] -// -//***************************************************************************** -extern uint_fast16_t GPIO_getEnabledInterruptStatus(uint_fast8_t selectedPort); - - -//***************************************************************************** -// -//! Registers an interrupt handler for the port interrupt. -//! -//! \param selectedPort is the port to register the interrupt handler -//! -//! \param intHandler is a pointer to the function to be called when the port -//! interrupt occurs. -//! -//! This function registers the handler to be called when a port -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific GPIO interrupts must be enabled -//! via GPIO_enableInterrupt(). It is the interrupt handler's responsibility to -//! clear the interrupt source via GPIO_clearInterruptFlag(). -//! -//! Clock System can generate interrupts when -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void GPIO_registerInterrupt(uint_fast8_t selectedPort, - void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the port. -//! -//! \param selectedPort is the port to unregister the interrupt handler -//! -//! This function unregisters the handler to be called when a port -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void GPIO_unregisterInterrupt(uint_fast8_t selectedPort); - -//***************************************************************************** -// -//! This function sets the drive strength to high for the selected port -//! -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1, -//! - \b GPIO_PORT_P2, -//! - \b GPIO_PORT_P3, -//! - \b GPIO_PORT_P4, -//! - \b GPIO_PORT_P5, -//! - \b GPIO_PORT_P6, -//! - \b GPIO_PORT_P7, -//! - \b GPIO_PORT_P8, -//! - \b GPIO_PORT_P9, -//! - \b GPIO_PORT_P10, -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Valid values are: -//! - \b GPIO_PIN0, -//! - \b GPIO_PIN1, -//! - \b GPIO_PIN2, -//! - \b GPIO_PIN3, -//! - \b GPIO_PIN4, -//! - \b GPIO_PIN5, -//! - \b GPIO_PIN6, -//! - \b GPIO_PIN7, -//! - \b GPIO_PIN8, -//! - \b PIN_ALL8, -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_setDriveStrengthHigh(uint_fast8_t selectedPort, - uint_fast8_t selectedPins); - -//***************************************************************************** -// -//! This function sets the drive strength to low for the selected port -//! -//! -//! \param selectedPort is the selected port. -//! Valid values are: -//! - \b GPIO_PORT_P1, -//! - \b GPIO_PORT_P2, -//! - \b GPIO_PORT_P3, -//! - \b GPIO_PORT_P4, -//! - \b GPIO_PORT_P5, -//! - \b GPIO_PORT_P6, -//! - \b GPIO_PORT_P7, -//! - \b GPIO_PORT_P8, -//! - \b GPIO_PORT_P9, -//! - \b GPIO_PORT_P10, -//! - \b GPIO_PORT_PJ -//! \param selectedPins is the specified pin in the selected port. -//! Valid values are: -//! - \b GPIO_PIN0, -//! - \b GPIO_PIN1, -//! - \b GPIO_PIN2, -//! - \b GPIO_PIN3, -//! - \b GPIO_PIN4, -//! - \b GPIO_PIN5, -//! - \b GPIO_PIN6, -//! - \b GPIO_PIN7, -//! - \b GPIO_PIN8, -//! - \b PIN_ALL8, -//! -//! \return None -// -//***************************************************************************** -extern void GPIO_setDriveStrengthLow(uint_fast8_t selectedPort, - uint_fast8_t selectedPins); - -/* Backwards Compatibility Layer */ -#define GPIO_selectInterruptEdge GPIO_interruptEdgeSelect -#define GPIO_clearInterrupt GPIO_clearInterruptFlag - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif // __GPIO_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/i2c.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/i2c.c deleted file mode 100644 index 80970903f2b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/i2c.c +++ /dev/null @@ -1,794 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include - -void I2C_initMaster(uint32_t moduleInstance, - const eUSCI_I2C_MasterConfig *config) -{ - uint_fast16_t preScalarValue; - - ASSERT( - (EUSCI_B_I2C_CLOCKSOURCE_ACLK == config->selectClockSource) - || (EUSCI_B_I2C_CLOCKSOURCE_SMCLK - == config->selectClockSource)); - - ASSERT( - (EUSCI_B_I2C_SET_DATA_RATE_400KBPS == config->dataRate) - || (EUSCI_B_I2C_SET_DATA_RATE_100KBPS == config->dataRate) - || (EUSCI_B_I2C_SET_DATA_RATE_1MBPS == config->dataRate)); - - ASSERT( - (EUSCI_B_I2C_NO_AUTO_STOP == config->autoSTOPGeneration) - || (EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG - == config->autoSTOPGeneration) - || (EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD - == config->autoSTOPGeneration)); - - /* Disable the USCI module and clears the other bits of control register */ - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) = - 1; - - /* Configure Automatic STOP condition generation */ - EUSCI_B_CMSIS(moduleInstance)->CTLW1 = (EUSCI_B_CMSIS(moduleInstance)->CTLW1 - & ~EUSCI_B_CTLW1_ASTP_MASK) | (config->autoSTOPGeneration); - - /* Byte Count Threshold */ - EUSCI_B_CMSIS(moduleInstance)->TBCNT = config->byteCounterThreshold; - - /* - * Configure as I2C master mode. - * UCMST = Master mode - * UCMODE_3 = I2C mode - * UCSYNC = Synchronous mode - */ - EUSCI_B_CMSIS(moduleInstance)->CTLW0 = (EUSCI_B_CMSIS(moduleInstance)->CTLW0 - & ~EUSCI_B_CTLW0_SSEL_MASK) - | (config->selectClockSource | EUSCI_B_CTLW0_MST - | EUSCI_B_CTLW0_MODE_3 | EUSCI_B_CTLW0_SYNC - | EUSCI_B_CTLW0_SWRST); - - /* - * Compute the clock divider that achieves the fastest speed less than or - * equal to the desired speed. The numerator is biased to favor a larger - * clock divider so that the resulting clock is always less than or equal - * to the desired clock, never greater. - */ - preScalarValue = (uint16_t) (config->i2cClk / config->dataRate); - - EUSCI_B_CMSIS(moduleInstance)->BRW = preScalarValue; -} - -void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress, - uint_fast8_t slaveAddressOffset, uint32_t slaveOwnAddressEnable) -{ - ASSERT( - (EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 == slaveAddressOffset) - || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 == slaveAddressOffset) - || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 == slaveAddressOffset) - || (EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 == slaveAddressOffset)); - - /* Disable the USCI module */ - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) = - 1; - - /* Clear USCI master mode */ - EUSCI_B_CMSIS(moduleInstance)->CTLW0 = (EUSCI_B_CMSIS(moduleInstance)->CTLW0 - & (~EUSCI_B_CTLW0_MST)) - | (EUSCI_B_CTLW0_MODE_3 + EUSCI_B_CTLW0_SYNC); - - /* Set up the slave address. */ - HWREG16( - (uint32_t) &EUSCI_B_CMSIS(moduleInstance)->I2COA0 - + slaveAddressOffset) = slaveAddress - + slaveOwnAddressEnable; -} - -void I2C_enableModule(uint32_t moduleInstance) -{ - /* Reset the UCSWRST bit to enable the USCI Module */ - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) = - 0; -} - -void I2C_disableModule(uint32_t moduleInstance) -{ - /* Set the UCSWRST bit to disable the USCI Module */ - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) = - 1; - ; -} - -void I2C_setSlaveAddress(uint32_t moduleInstance, uint_fast16_t slaveAddress) -{ - /* Set the address of the slave with which the master will communicate */ - EUSCI_B_CMSIS(moduleInstance)->I2CSA = (slaveAddress); -} - -void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode) -{ - ASSERT( - (EUSCI_B_I2C_TRANSMIT_MODE == mode) - || (EUSCI_B_I2C_RECEIVE_MODE == mode)); - - EUSCI_B_CMSIS(moduleInstance)->CTLW0 = (EUSCI_B_CMSIS(moduleInstance)->CTLW0 - & (~EUSCI_B_I2C_TRANSMIT_MODE)) | mode; - -} - -uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance) -{ - //Set USCI in Receive mode - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TR_OFS) = - 0; - - //Send start - EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= (EUSCI_B_CTLW0_TXSTT - + EUSCI_B_CTLW0_TXSTP); - - //Poll for receive interrupt flag. - while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_RXIFG_OFS)) - ; - - //Send single byte data. - return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK); -} - -void I2C_slavePutData(uint32_t moduleInstance, uint8_t transmitData) -{ - //Send single byte data. - EUSCI_B_CMSIS(moduleInstance)->TXBUF = transmitData; -} - -uint8_t I2C_slaveGetData(uint32_t moduleInstance) -{ - //Read a byte. - return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK); -} - -uint8_t I2C_isBusBusy(uint32_t moduleInstance) -{ - //Return the bus busy status. - return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->STATW, - EUSCI_B_STATW_BBUSY_OFS); -} - -void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData) -{ - //Store current TXIE status - uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0; - - //Disable transmit interrupt enable - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0; - - //Send start condition. - EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR - + EUSCI_B_CTLW0_TXSTT; - - //Poll for transmit interrupt flag and start condition flag. - while ((BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, - EUSCI_B_CTLW0_TXSTT_OFS) - || !BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_TXIFG0_OFS))); - - //Send single byte data. - EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData; - - //Poll for transmit interrupt flag. - while (!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG)) - ; - - //Send stop condition. - EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TXSTP; - - //Clear transmit interrupt flag before enabling interrupt again - EUSCI_B_CMSIS(moduleInstance)->IFG &= ~(EUSCI_B_IFG_TXIFG); - - //Reinstate transmit interrupt enable - EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus; -} - -bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance, - uint8_t txData, uint32_t timeout) -{ - uint_fast16_t txieStatus; - uint32_t timeout2 = timeout; - - ASSERT(timeout > 0); - - //Store current TXIE status - txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0; - - //Disable transmit interrupt enable - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0; - - //Send start condition. - EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR - + EUSCI_B_CTLW0_TXSTT; - - //Poll for transmit interrupt flag. - while ((!(EUSCI_B_CMSIS(moduleInstance)->IFG & EUSCI_B_IFG_TXIFG)) - && --timeout) - ; - - //Check if transfer timed out - if (timeout == 0) - return false; - - //Send single byte data. - EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData; - - //Poll for transmit interrupt flag. - while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_TXIFG0_OFS)) && --timeout2) - ; - - //Check if transfer timed out - if (timeout2 == 0) - return false; - - //Send stop condition. - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) = - 1; - - //Clear transmit interrupt flag before enabling interrupt again - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_TXIFG0_OFS) = - 0; - - //Reinstate transmit interrupt enable - EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus; - - return true; -} - -void I2C_masterSendMultiByteStart(uint32_t moduleInstance, uint8_t txData) -{ - //Store current transmit interrupt enable - uint16_t txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0; - - //Disable transmit interrupt enable - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0; - - //Send start condition. - EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR - + EUSCI_B_CTLW0_TXSTT; - - //Poll for transmit interrupt flag and start condition flag. - while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, - EUSCI_B_CTLW0_TXSTT_OFS) - || !BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_TXIFG0_OFS)); - - //Send single byte data. - EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData; - - //Reinstate transmit interrupt enable - EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus; -} - -bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance, - uint8_t txData, uint32_t timeout) -{ - uint_fast16_t txieStatus; - - ASSERT(timeout > 0); - - //Store current transmit interrupt enable - txieStatus = EUSCI_B_CMSIS(moduleInstance)->IE & EUSCI_B_IE_TXIE0; - - //Disable transmit interrupt enable - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS) = 0; - - //Send start condition. - EUSCI_B_CMSIS(moduleInstance)->CTLW0 |= EUSCI_B_CTLW0_TR - + EUSCI_B_CTLW0_TXSTT; - - //Poll for transmit interrupt flag and start condition flag. - while ((BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, - EUSCI_B_CTLW0_TXSTT_OFS) - || !BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_TXIFG0_OFS)) && --timeout); - - - //Check if transfer timed out - if (timeout == 0) - return false; - - //Send single byte data. - EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData; - - //Reinstate transmit interrupt enable - EUSCI_B_CMSIS(moduleInstance)->IE |= txieStatus; - - return true; -} - -void I2C_masterSendMultiByteNext(uint32_t moduleInstance, uint8_t txData) -{ - //If interrupts are not used, poll for flags - if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS)) - { - //Poll for transmit interrupt flag. - while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_TXIFG0_OFS)) - ; - } - - //Send single byte data. - EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData; -} - -bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance, - uint8_t txData, uint32_t timeout) -{ - ASSERT(timeout > 0); - - //If interrupts are not used, poll for flags - if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS)) - { - //Poll for transmit interrupt flag. - while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_TXIFG0_OFS)) && --timeout) - ; - - //Check if transfer timed out - if (timeout == 0) - return false; - } - - //Send single byte data. - EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData; - - return true; -} - -bool I2C_masterSendMultiByteFinish(uint32_t moduleInstance, uint8_t txData) -{ - //If interrupts are not used, poll for flags - if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS)) - { - //Poll for transmit interrupt flag. - while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_TXIFG0_OFS)) - ; - } - - //Send single byte data. - EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData; - - //Poll for transmit interrupt flag. - while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_TXIFG0_OFS) - && !BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_NACKIFG_OFS)) - ; - if(BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, EUSCI_B_IFG_NACKIFG_OFS)) - return false; - - //Send stop condition. - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) = - 1; - - return true; -} - -bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance, - uint8_t txData, uint32_t timeout) -{ - uint32_t timeout2 = timeout; - - ASSERT(timeout > 0); - - //If interrupts are not used, poll for flags - if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS)) - { - //Poll for transmit interrupt flag. - while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_TXIFG0_OFS)) && --timeout) - ; - - //Check if transfer timed out - if (timeout == 0) - return false; - } - - //Send single byte data. - EUSCI_B_CMSIS(moduleInstance)->TXBUF = txData; - - //Poll for transmit interrupt flag. - while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_TXIFG0_OFS)) && --timeout2 - && !BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_NACKIFG_OFS)) - ; - - //Check if transfer timed out - if (timeout2 == 0) - return false; - - //Send stop condition. - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) = - 1; - - return true; -} - -void I2C_masterSendMultiByteStop(uint32_t moduleInstance) -{ - //If interrupts are not used, poll for flags - if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS)) - { - //Poll for transmit interrupt flag. - while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_TXIFG0_OFS)) - ; - } - - //Send stop condition. - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) = - 1; -} - -bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance, - uint32_t timeout) -{ - ASSERT(timeout > 0); - - //If interrupts are not used, poll for flags - if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_TXIE0_OFS)) - { - //Poll for transmit interrupt flag. - while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_TXIFG0_OFS)) && --timeout) - ; - - //Check if transfer timed out - if (timeout == 0) - return false; - } - - //Send stop condition. - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) = - 1; - - return 0x01; -} - -void I2C_masterReceiveStart(uint32_t moduleInstance) -{ - //Set USCI in Receive mode - EUSCI_B_CMSIS(moduleInstance)->CTLW0 = (EUSCI_B_CMSIS(moduleInstance)->CTLW0 - & (~EUSCI_B_CTLW0_TR)) | EUSCI_B_CTLW0_TXSTT; -} - -uint8_t I2C_masterReceiveMultiByteNext(uint32_t moduleInstance) -{ - return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK); -} - -uint8_t I2C_masterReceiveMultiByteFinish(uint32_t moduleInstance) -{ - //Send stop condition. - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) = - 1; - - //Wait for Stop to finish - while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, - EUSCI_B_CTLW0_TXSTP_OFS)) - { - // Wait for RX buffer - while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_RXIFG_OFS)) - ; - } - - /* Capture data from receive buffer after setting stop bit due to - MSP430 I2C critical timing. */ - return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK); -} - -bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance, - uint8_t *txData, uint32_t timeout) -{ - uint32_t timeout2 = timeout; - - ASSERT(timeout > 0); - - //Send stop condition. - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) = - 1; - - //Wait for Stop to finish - while (BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, - EUSCI_B_CTLW0_TXSTP_OFS) && --timeout) - ; - - //Check if transfer timed out - if (timeout == 0) - return false; - - // Wait for RX buffer - while ((!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_RXIFG_OFS)) && --timeout2) - ; - - //Check if transfer timed out - if (timeout2 == 0) - return false; - - //Capture data from receive buffer after setting stop bit due to - //MSP430 I2C critical timing. - *txData = (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK); - - return true; -} - -void I2C_masterReceiveMultiByteStop(uint32_t moduleInstance) -{ - //Send stop condition. - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTP_OFS) = - 1; -} - -uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance) -{ - //Polling RXIFG0 if RXIE is not enabled - if (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IE, EUSCI_B_IE_RXIE0_OFS)) - { - while (!BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->IFG, - EUSCI_B_IFG_RXIFG0_OFS)) - ; - } - - //Read a byte. - return (EUSCI_B_CMSIS(moduleInstance)->RXBUF & EUSCI_B_RXBUF_RXBUF_MASK); -} - -uint32_t I2C_getReceiveBufferAddressForDMA(uint32_t moduleInstance) -{ - return (uint32_t) &EUSCI_B_CMSIS(moduleInstance)->RXBUF; -} - -uint32_t I2C_getTransmitBufferAddressForDMA(uint32_t moduleInstance) -{ - return (uint32_t) &EUSCI_B_CMSIS(moduleInstance)->TXBUF; -} - -uint8_t I2C_masterIsStopSent(uint32_t moduleInstance) -{ - return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, - EUSCI_B_CTLW0_TXSTP_OFS); -} - -bool I2C_masterIsStartSent(uint32_t moduleInstance) -{ - return BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, - EUSCI_B_CTLW0_TXSTT_OFS); -} - -void I2C_masterSendStart(uint32_t moduleInstance) -{ - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXSTT_OFS) = - 1; -} - -void I2C_enableMultiMasterMode(uint32_t moduleInstance) -{ - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) = - 1; - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_MM_OFS) = - 1; -} - -void I2C_disableMultiMasterMode(uint32_t moduleInstance) -{ - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_SWRST_OFS) = - 1; - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_MM_OFS) = - 0; -} - -void I2C_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask) -{ - ASSERT( - 0x00 - == (mask - & ~(EUSCI_B_I2C_STOP_INTERRUPT - + EUSCI_B_I2C_START_INTERRUPT - + EUSCI_B_I2C_NAK_INTERRUPT - + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - + EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - + EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - + EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - + EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - + EUSCI_B_I2C_RECEIVE_INTERRUPT0 - + EUSCI_B_I2C_RECEIVE_INTERRUPT1 - + EUSCI_B_I2C_RECEIVE_INTERRUPT2 - + EUSCI_B_I2C_RECEIVE_INTERRUPT3))); - - //Enable the interrupt masked bit - EUSCI_B_CMSIS(moduleInstance)->IE |= mask; -} - -void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask) -{ - ASSERT( - 0x00 - == (mask - & ~(EUSCI_B_I2C_STOP_INTERRUPT - + EUSCI_B_I2C_START_INTERRUPT - + EUSCI_B_I2C_NAK_INTERRUPT - + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - + EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - + EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - + EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - + EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - + EUSCI_B_I2C_RECEIVE_INTERRUPT0 - + EUSCI_B_I2C_RECEIVE_INTERRUPT1 - + EUSCI_B_I2C_RECEIVE_INTERRUPT2 - + EUSCI_B_I2C_RECEIVE_INTERRUPT3))); - - //Disable the interrupt masked bit - EUSCI_B_CMSIS(moduleInstance)->IE &= ~(mask); -} - -void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask) -{ - ASSERT( - 0x00 - == (mask - & ~(EUSCI_B_I2C_STOP_INTERRUPT - + EUSCI_B_I2C_START_INTERRUPT - + EUSCI_B_I2C_NAK_INTERRUPT - + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - + EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - + EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - + EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - + EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - + EUSCI_B_I2C_RECEIVE_INTERRUPT0 - + EUSCI_B_I2C_RECEIVE_INTERRUPT1 - + EUSCI_B_I2C_RECEIVE_INTERRUPT2 - + EUSCI_B_I2C_RECEIVE_INTERRUPT3))); - //Clear the I2C interrupt source. - EUSCI_B_CMSIS(moduleInstance)->IFG &= ~(mask); -} - -uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask) -{ - ASSERT( - 0x00 - == (mask - & ~(EUSCI_B_I2C_STOP_INTERRUPT - + EUSCI_B_I2C_START_INTERRUPT - + EUSCI_B_I2C_NAK_INTERRUPT - + EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - + EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - + EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - + EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - + EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - + EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - + EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - + EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - + EUSCI_B_I2C_RECEIVE_INTERRUPT0 - + EUSCI_B_I2C_RECEIVE_INTERRUPT1 - + EUSCI_B_I2C_RECEIVE_INTERRUPT2 - + EUSCI_B_I2C_RECEIVE_INTERRUPT3))); - //Return the interrupt status of the request masked bit. - return EUSCI_B_CMSIS(moduleInstance)->IFG & mask; -} - -uint_fast16_t I2C_getEnabledInterruptStatus(uint32_t moduleInstance) -{ - return I2C_getInterruptStatus(moduleInstance, - EUSCI_B_CMSIS(moduleInstance)->IE); -} - -uint_fast16_t I2C_getMode(uint32_t moduleInstance) -{ - //Read the I2C mode. - return (EUSCI_B_CMSIS(moduleInstance)->CTLW0 & EUSCI_B_CTLW0_TR); -} - -void I2C_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void)) -{ - switch (moduleInstance) - { - case EUSCI_B0_BASE: - Interrupt_registerInterrupt(INT_EUSCIB0, intHandler); - Interrupt_enableInterrupt(INT_EUSCIB0); - break; - case EUSCI_B1_BASE: - Interrupt_registerInterrupt(INT_EUSCIB1, intHandler); - Interrupt_enableInterrupt(INT_EUSCIB1); - break; -#ifdef EUSCI_B2_BASE - case EUSCI_B2_BASE: - Interrupt_registerInterrupt(INT_EUSCIB2, intHandler); - Interrupt_enableInterrupt(INT_EUSCIB2); - break; -#endif -#ifdef EUSCI_B3_BASE - case EUSCI_B3_BASE: - Interrupt_registerInterrupt(INT_EUSCIB3, intHandler); - Interrupt_enableInterrupt(INT_EUSCIB3); - break; -#endif - default: - ASSERT(false); - } -} - -void I2C_unregisterInterrupt(uint32_t moduleInstance) -{ - switch (moduleInstance) - { - case EUSCI_B0_BASE: - Interrupt_disableInterrupt(INT_EUSCIB0); - Interrupt_unregisterInterrupt(INT_EUSCIB0); - break; - case EUSCI_B1_BASE: - Interrupt_disableInterrupt(INT_EUSCIB1); - Interrupt_unregisterInterrupt(INT_EUSCIB1); - break; -#ifdef EUSCI_B2_BASE - case EUSCI_B2_BASE: - Interrupt_disableInterrupt(INT_EUSCIB2); - Interrupt_unregisterInterrupt(INT_EUSCIB2); - break; -#endif -#ifdef EUSCI_B3_BASE - case EUSCI_B3_BASE: - Interrupt_disableInterrupt(INT_EUSCIB3); - Interrupt_unregisterInterrupt(INT_EUSCIB3); - break; -#endif - default: - ASSERT(false); - } -} - -void I2C_slaveSendNAK(uint32_t moduleInstance) -{ - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_B_CTLW0_TXNACK_OFS) = - 1; -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/i2c.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/i2c.h deleted file mode 100644 index 44ffda72696..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/i2c.h +++ /dev/null @@ -1,1421 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef I2C_H_ -#define I2C_H_ - -//***************************************************************************** -// -//! \addtogroup i2c_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include -#include - -#define EUSCI_B_I2C_NO_AUTO_STOP EUSCI_B_CTLW1_ASTP_0 -#define EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG EUSCI_B_CTLW1_ASTP_1 -#define EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD \ - EUSCI_B_CTLW1_ASTP_2 - -#define EUSCI_B_I2C_SET_DATA_RATE_1MBPS 1000000 -#define EUSCI_B_I2C_SET_DATA_RATE_400KBPS 400000 -#define EUSCI_B_I2C_SET_DATA_RATE_100KBPS 100000 - -#define EUSCI_B_I2C_CLOCKSOURCE_ACLK EUSCI_B_CTLW0_SSEL__ACLK -#define EUSCI_B_I2C_CLOCKSOURCE_SMCLK EUSCI_B_CTLW0_SSEL__SMCLK - -#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET0 0x00 -#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET1 0x02 -#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET2 0x04 -#define EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 0x06 - -#define EUSCI_B_I2C_OWN_ADDRESS_DISABLE 0x00 -#define EUSCI_B_I2C_OWN_ADDRESS_ENABLE EUSCI_B_I2COA0_OAEN - -#define EUSCI_B_I2C_TRANSMIT_MODE EUSCI_B_CTLW0_TR -#define EUSCI_B_I2C_RECEIVE_MODE 0x00 - -#define EUSCI_B_I2C_NAK_INTERRUPT EUSCI_B_IE_NACKIE -#define EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT EUSCI_B_IE_ALIE -#define EUSCI_B_I2C_STOP_INTERRUPT EUSCI_B_IE_STPIE -#define EUSCI_B_I2C_START_INTERRUPT EUSCI_B_IE_STTIE -#define EUSCI_B_I2C_TRANSMIT_INTERRUPT0 EUSCI_B_IE_TXIE0 -#define EUSCI_B_I2C_TRANSMIT_INTERRUPT1 EUSCI_B_IE_TXIE1 -#define EUSCI_B_I2C_TRANSMIT_INTERRUPT2 EUSCI_B_IE_TXIE2 -#define EUSCI_B_I2C_TRANSMIT_INTERRUPT3 EUSCI_B_IE_TXIE3 -#define EUSCI_B_I2C_RECEIVE_INTERRUPT0 EUSCI_B_IE_RXIE0 -#define EUSCI_B_I2C_RECEIVE_INTERRUPT1 EUSCI_B_IE_RXIE1 -#define EUSCI_B_I2C_RECEIVE_INTERRUPT2 EUSCI_B_IE_RXIE2 -#define EUSCI_B_I2C_RECEIVE_INTERRUPT3 EUSCI_B_IE_RXIE3 -#define EUSCI_B_I2C_BIT9_POSITION_INTERRUPT EUSCI_B_IE_BIT9IE -#define EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT EUSCI_B_IE_CLTOIE -#define EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT EUSCI_B_IE_BCNTIE - -#define EUSCI_B_I2C_BUS_BUSY EUSCI_B_STATW_BBUSY -#define EUSCI_B_I2C_BUS_NOT_BUSY 0x00 - -#define EUSCI_B_I2C_STOP_SEND_COMPLETE 0x00 -#define EUSCI_B_I2C_SENDING_STOP EUSCI_B_CTLW0_TXSTP - -#define EUSCI_B_I2C_START_SEND_COMPLETE 0x00 -#define EUSCI_B_I2C_SENDING_START EUSCI_B_CTLW0_TXSTT - -//***************************************************************************** -// -//! ypedef eUSCI_I2C_MasterConfig -//! \brief Type definition for \link _eUSCI_I2C_MasterConfig \endlink structure -//! -//! \struct _eUSCI_I2C_MasterConfig -//! \brief Configuration structure for master mode in the \b I2C module. See -//! \link I2C_initMaster \endlink for parameter documentation. -// -//***************************************************************************** -typedef struct -{ - uint_fast8_t selectClockSource; - uint32_t i2cClk; - uint32_t dataRate; - uint_fast8_t byteCounterThreshold; - uint_fast8_t autoSTOPGeneration; -} eUSCI_I2C_MasterConfig; - - -//***************************************************************************** -// -//! Initializes the I2C Master block. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! \param config Configuration structure for I2C master mode -//! -//!
-//! Configuration options for \link eUSCI_I2C_MasterConfig \endlink structure. -//!
-//! -//! \param selectClockSource is the clock source. -//! Valid values are -//! - \b EUSCI_B_I2C_CLOCKSOURCE_ACLK -//! - \b EUSCI_B_I2C_CLOCKSOURCE_SMCLK -//! \param i2cClk is the rate of the clock supplied to the I2C module -//! (the frequency in Hz of the clock source specified in -//! selectClockSource). -//! \param dataRate set up for selecting data transfer rate. -//! Valid values are -//! - \b EUSCI_B_I2C_SET_DATA_RATE_1MBPS -//! - \b EUSCI_B_I2C_SET_DATA_RATE_400KBPS -//! - \b EUSCI_B_I2C_SET_DATA_RATE_100KBPS -//! \param byteCounterThreshold sets threshold for automatic STOP or UCSTPIFG -//! \param autoSTOPGeneration sets up the STOP condition generation. -//! Valid values are -//! - \b EUSCI_B_I2C_NO_AUTO_STOP -//! - \b EUSCI_B_I2C_SET_BYTECOUNT_THRESHOLD_FLAG -//! - \b EUSCI_B_I2C_SEND_STOP_AUTOMATICALLY_ON_BYTECOUNT_THRESHOLD -//! -//! This function initializes operation of the I2C Master block. Upon -//! successful initialization of the I2C block, this function will have set the -//! bus speed for the master; however I2C module is still disabled till -//! I2C_enableModule is invoked -//! -//! Modified bits are \b UCMST,UCMODE_3,\b UCSYNC of \b UCBxCTL0 register -//! \b UCSSELx, \b UCSWRST, of \b UCBxCTL1 register -//! \b UCBxBR0 and \b UCBxBR1 registers -//! \return None. -// -//***************************************************************************** -extern void I2C_initMaster(uint32_t moduleInstance, - const eUSCI_I2C_MasterConfig *config); - -//***************************************************************************** -// -//! Initializes the I2C Slave block. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param slaveAddress 7-bit or 10-bit slave address -//! \param slaveAddressOffset Own address Offset referred to- 'x' value of -//! UCBxI2COAx. Valid values are: -//! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET0, -//! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET1, -//! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET2, -//! - \b EUSCI_B_I2C_OWN_ADDRESS_OFFSET3 -//! \param slaveOwnAddressEnable selects if the specified address is enabled -//! or disabled. Valid values are: -//! - \b EUSCI_B_I2C_OWN_ADDRESS_DISABLE, -//! - \b EUSCI_B_I2C_OWN_ADDRESS_ENABLE -//! -//! This function initializes operation of the I2C as a Slave mode. Upon -//! successful initialization of the I2C blocks, this function will have set -//! the slave address but the I2C module is still disabled till -//! I2C_enableModule is invoked. -//! -//! The parameter slaveAddress is the value that will be compared against the -//! slave address sent by an I2C master. -//! -//! Modified bits are \b UCMODE_3, \b UCSYNC of \b UCBxCTL0 register -//! \b UCSWRST of \b UCBxCTL1 register -//! \b UCBxI2COA register -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_initSlave(uint32_t moduleInstance, uint_fast16_t slaveAddress, - uint_fast8_t slaveAddressOffset, uint32_t slaveOwnAddressEnable); - -//***************************************************************************** -// -//! Enables the I2C block. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! This will enable operation of the I2C block. -//! Modified bits are \b UCSWRST of \b UCBxCTL1 register. -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_enableModule(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Disables the I2C block. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! This will disable operation of the I2C block. -//! Modified bits are \b UCSWRST of \b UCBxCTL1 register. -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_disableModule(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Sets the address that the I2C Master will place on the bus. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param slaveAddress 7-bit or 10-bit slave address -//! -//! This function will set the address that the I2C Master will place on the -//! bus when initiating a transaction. -//! Modified register is \b UCBxI2CSA register -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_setSlaveAddress(uint32_t moduleInstance, - uint_fast16_t slaveAddress); - -//***************************************************************************** -// -//! Sets the mode of the I2C device -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param mode indicates whether module is in transmit/receive mode -//! - \b EUSCI_B_I2C_TRANSMIT_MODE -//! - \b EUSCI_B_I2C_RECEIVE_MODE [Default value] -//! -//! Modified bits are \b UCTR of \b UCBxCTL1 register -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_setMode(uint32_t moduleInstance, uint_fast8_t mode); - -//***************************************************************************** -// -//! \brief Gets the mode of the I2C device -//! -//! Current I2C transmit/receive mode. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! Modified bits are \b UCTR of \b UCBxCTL1 register. -//! -//! \return None -//! Return one of the following: -//! - \b EUSCI_B_I2C_TRANSMIT_MODE -//! - \b EUSCI_B_I2C_RECEIVE_MODE -//! \n indicating the current mode -// -//***************************************************************************** -extern uint_fast8_t I2C_getMode(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Transmits a byte from the I2C Module. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param transmitData data to be transmitted from the I2C module -//! -//! This function will place the supplied data into I2C transmit data register -//! to start transmission -//! Modified register is \b UCBxTXBUF register -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_slavePutData(uint32_t moduleInstance, uint8_t transmitData); - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Module. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! This function reads a byte of data from the I2C receive data Register. -//! -//! \return Returns the byte received from by the I2C module, cast as an -//! uint8_t. -//! Modified bit is \b UCBxRXBUF register -// -//***************************************************************************** -extern uint8_t I2C_slaveGetData(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Indicates whether or not the I2C bus is busy. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! This function returns an indication of whether or not the I2C bus is -//! busy.This function checks the status of the bus via UCBBUSY bit in -//! UCBxSTAT register. -//! -//! \return Returns EUSCI_B_I2C_BUS_BUSY if the I2C Master is busy; otherwise, -//! returns EUSCI_B_I2C_BUS_NOT_BUSY. -// -//***************************************************************************** -extern uint8_t I2C_isBusBusy(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Does single byte transmission from Master to Slave -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param txData is the data byte to be transmitted -//! -//! This function is used by the Master module to send a single byte. -//! This function -//! - Sends START -//! - Transmits the byte to the Slave -//! - Sends STOP -//! -//! Modified registers are \b UCBxIE, \b UCBxCTL1, \b UCBxIFG, \b UCBxTXBUF, -//! \b UCBxIE -//! -//! \return none -// -//***************************************************************************** -extern void I2C_masterSendSingleByte(uint32_t moduleInstance, uint8_t txData); - -//***************************************************************************** -// -//! Does single byte transmission from Master to Slave with timeout -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param txData is the data byte to be transmitted -//! \param timeout is the amount of time to wait until giving up -//! -//! This function is used by the Master module to send a single byte. -//! This function -//! - Sends START -//! - Transmits the byte to the Slave -//! - Sends STOP -//! -//! Modified registers are \b UCBxIE, \b UCBxCTL1, \b UCBxIFG, \b UCBxTXBUF, -//! \b UCBxIE -//! -//! \return 0x01 or 0x00URE of the transmission process. -// -//***************************************************************************** -extern bool I2C_masterSendSingleByteWithTimeout(uint32_t moduleInstance, - uint8_t txData, uint32_t timeout); - -//***************************************************************************** -// -//! Starts multi-byte transmission from Master to Slave -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param txData is the first data byte to be transmitted -//! -//! This function is used by the Master module to send a single byte. -//! This function -//! - Sends START -//! - Transmits the first data byte of a multi-byte transmission to the Slave -//! -//! Modified registers are \b UCBxIE, \b UCBxCTL1, \b UCBxIFG, \b UCBxTXBUF, -//! \b UCBxIE -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_masterSendMultiByteStart(uint32_t moduleInstance, - uint8_t txData); - -//***************************************************************************** -// -//! Starts multi-byte transmission from Master to Slave with timeout -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param txData is the first data byte to be transmitted -//! \param timeout is the amount of time to wait until giving up -//! -//! This function is used by the Master module to send a single byte. -//! This function -//! - Sends START -//! - Transmits the first data byte of a multi-byte transmission to the Slave -//! -//! Modified registers are \b UCBxIE, \b UCBxCTL1, \b UCBxIFG, \b UCBxTXBUF, -//! \b UCBxIE -//! -//! \return 0x01 or 0x00URE of the transmission process. -// -//***************************************************************************** -extern bool I2C_masterSendMultiByteStartWithTimeout(uint32_t moduleInstance, - uint8_t txData, uint32_t timeout); - -//***************************************************************************** -// -//! Continues multi-byte transmission from Master to Slave -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param txData is the next data byte to be transmitted -//! -//! This function is used by the Master module continue each byte of a -//! multi-byte trasmission. This function -//! - Transmits each data byte of a multi-byte transmission to the Slave -//! -//! Modified registers are \b UCBxTXBUF -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_masterSendMultiByteNext(uint32_t moduleInstance, - uint8_t txData); - -//***************************************************************************** -// -//! Continues multi-byte transmission from Master to Slave with timeout -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param txData is the next data byte to be transmitted -//! -//! \param timeout is the amount of time to wait until giving up -//! -//! This function is used by the Master module continue each byte of a -//! multi-byte transmission. This function -//! - Transmits each data byte of a multi-byte transmission to the Slave -//! -//! Modified registers are \b UCBxTXBUF -//! -//! \return 0x01 or 0x00URE of the transmission process. -// -//***************************************************************************** -extern bool I2C_masterSendMultiByteNextWithTimeout(uint32_t moduleInstance, - uint8_t txData, uint32_t timeout); - -//***************************************************************************** -// -//! Finishes multi-byte transmission from Master to Slave -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param txData is the last data byte to be transmitted in a multi-byte -//! transmsission -//! -//! This function is used by the Master module to send the last byte and STOP. -//! This function -//! - Transmits the last data byte of a multi-byte transmission to the Slave -//! - Sends STOP -//! -//! Modified registers are \b UCBxTXBUF and \b UCBxCTL1. -//! -//! \return false if NAK occurred, false otherwise -// -//***************************************************************************** -extern bool I2C_masterSendMultiByteFinish(uint32_t moduleInstance, - uint8_t txData); - -//***************************************************************************** -// -//! Finishes multi-byte transmission from Master to Slave with timeout -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param txData is the last data byte to be transmitted in a multi-byte -//! transmission -//! \param timeout is the amount of time to wait until giving up -//! -//! This function is used by the Master module to send the last byte and STOP. -//! This function -//! - Transmits the last data byte of a multi-byte transmission to the Slave -//! - Sends STOP -//! -//! Modified registers are \b UCBxTXBUF and \b UCBxCTL1. -//! -//! \return 0x01 or 0x00URE of the transmission process. -// -//***************************************************************************** -extern bool I2C_masterSendMultiByteFinishWithTimeout(uint32_t moduleInstance, - uint8_t txData, uint32_t timeout); - -//***************************************************************************** -// -//! Send STOP byte at the end of a multi-byte transmission from Master to Slave -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! This function is used by the Master module send STOP at the end of a -//! multi-byte transmission -//! -//! This function -//! - Send a STOP after current transmission is complete -//! -//! Modified bits are \b UCTXSTP bit of \b UCBxCTL1. -//! \return None. -// -//***************************************************************************** -extern void I2C_masterSendMultiByteStop(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Send STOP byte at the end of a multi-byte transmission from Master to Slave -//! with timeout -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param timeout is the amount of time to wait until giving up -//! -//! This function is used by the Master module send STOP at the end of a -//! multi-byte transmission -//! -//! This function -//! - Send a STOP after current transmission is complete -//! -//! Modified bits are \b UCTXSTP bit of \b UCBxCTL1. -//! \return 0x01 or 0x00URE of the transmission process. -// -//***************************************************************************** -extern bool I2C_masterSendMultiByteStopWithTimeout(uint32_t moduleInstance, - uint32_t timeout); - -//***************************************************************************** -// -//! Starts reception at the Master end -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! This function is used by the Master module initiate reception of a single -//! byte. This function -//! - Sends START -//! -//! Modified bits are \b UCTXSTT bit of \b UCBxCTL1. -//! \return None. -// -//***************************************************************************** -extern void I2C_masterReceiveStart(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Starts multi-byte reception at the Master end one byte at a time -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! This function is used by the Master module to receive each byte of a -//! multi-byte reception -//! This function reads currently received byte -//! -//! Modified register is \b UCBxRXBUF. -//! \return Received byte at Master end. -// -//***************************************************************************** -extern uint8_t I2C_masterReceiveMultiByteNext(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Finishes multi-byte reception at the Master end -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! This function is used by the Master module to initiate completion of a -//! multi-byte reception -//! This function -//! - Receives the current byte and initiates the STOP from Master to Slave -//! -//! Modified bits are \b UCTXSTP bit of \b UCBxCTL1. -//! -//! \return Received byte at Master end. -// -//***************************************************************************** -extern uint8_t I2C_masterReceiveMultiByteFinish(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Finishes multi-byte reception at the Master end with timeout -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param txData is a pointer to the location to store the received byte at -//! master end -//! \param timeout is the amount of time to wait until giving up -//! -//! This function is used by the Master module to initiate completion of a -//! multi-byte reception -//! This function -//! - Receives the current byte and initiates the STOP from Master to Slave -//! -//! Modified bits are \b UCTXSTP bit of \b UCBxCTL1. -//! -//! \return 0x01 or 0x00URE of the transmission process. -// -//***************************************************************************** -extern bool I2C_masterReceiveMultiByteFinishWithTimeout(uint32_t moduleInstance, - uint8_t *txData, uint32_t timeout); - -//***************************************************************************** -// -//! Sends the STOP at the end of a multi-byte reception at the Master end -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! This function is used by the Master module to initiate STOP -//! -//! Modified bits are UCTXSTP bit of UCBxCTL1. -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_masterReceiveMultiByteStop(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Does single byte reception from the slave -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! This function is used by the Master module to receive a single byte. -//! This function: -//! - Sends START and STOP -//! - Waits for data reception -//! - Receives one byte from the Slave -//! -//! Modified registers are \b UCBxIE, \b UCBxCTL1, \b UCBxIFG, \b UCBxTXBUF, -//! \b UCBxIE -//! -//! \return The byte that has been received from the slave -// -//***************************************************************************** -extern uint8_t I2C_masterReceiveSingleByte(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Receives a byte that has been sent to the I2C Master Module. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! This function reads a byte of data from the I2C receive data Register. -//! -//! \return Returns the byte received from by the I2C module, cast as an -//! uint8_t. -// -//***************************************************************************** -extern uint8_t I2C_masterReceiveSingle(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Returns the address of the RX Buffer of the I2C for the DMA module. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! Returns the address of the I2C RX Buffer. This can be used in conjunction -//! with the DMA to store the received data directly to memory. -//! -//! \return NONE -// -//***************************************************************************** -extern uint32_t I2C_getReceiveBufferAddressForDMA(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Returns the address of the TX Buffer of the I2C for the DMA module. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! Returns the address of the I2C TX Buffer. This can be used in conjunction -//! with the DMA to obtain transmitted data directly from memory. -//! -//! \return NONE -// -//***************************************************************************** -extern uint32_t I2C_getTransmitBufferAddressForDMA(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Indicates whether STOP got sent. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! This function returns an indication of whether or not STOP got sent -//! This function checks the status of the bus via UCTXSTP bit in -//! UCBxCTL1 register. -//! -//! \return Returns EUSCI_B_I2C_STOP_SEND_COMPLETE if the I2C Master -//! finished sending STOP; otherwise, returns EUSCI_B_I2C_SENDING_STOP. -// -//***************************************************************************** -extern uint8_t I2C_masterIsStopSent(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Indicates whether Start got sent. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! This function returns an indication of whether or not Start got sent -//! This function checks the status of the bus via UCTXSTT bit in -//! UCBxCTL1 register. -//! -//! \return Returns true if the START has been sent, false if it is sending -// -//***************************************************************************** -extern bool I2C_masterIsStartSent(uint32_t moduleInstance); - -//***************************************************************************** -// -//! This function is used by the Master module to initiate START -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! This function is used by the Master module to initiate STOP -//! -//! Modified bits are UCTXSTT bit of UCBxCTLW0. -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_masterSendStart(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Enables Multi Master Mode -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! At the end of this function, the I2C module is still disabled till -//! I2C_enableModule is invoked -//! -//! Modified bits are \b UCSWRST of \b OFS_UCBxCTLW0, \b UCMM bit of -//! \b UCBxCTLW0 -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_enableMultiMasterMode(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Disables Multi Master Mode -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! -//! At the end of this function, the I2C module is still disabled till -//! I2C_enableModule is invoked -//! -//! Modified bits are \b UCSWRST of \b OFS_UCBxCTLW0, \b UCMM bit of -//! \b UCBxCTLW0 -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_disableMultiMasterMode(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Enables individual I2C interrupt sources. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param mask is the bit mask of the interrupt sources to -//! be enabled. -//! -//! Enables the indicated I2C interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. -//! -//! The mask parameter is the logical OR of any of the following: -//! -//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt -//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 -//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt -//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost interrupt -//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt enable -//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout interrupt -//! enable -//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt enable -//! -//! Modified registers are UCBxIFG and OFS_UCBxIE. -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_enableInterrupt(uint32_t moduleInstance, uint_fast16_t mask); - -//***************************************************************************** -// -//! Disables individual I2C interrupt sources. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param mask is the bit mask of the interrupt sources to be -//! disabled. -//! -//! Disables the indicated I2C interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. -//! -//! The mask parameter is the logical OR of any of the following: -//! -//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt -//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 -//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt -//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost interrupt -//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt enable -//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout interrupt -//! enable -//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt enable -//! -//! Modified register is \b UCBxIE. -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_disableInterrupt(uint32_t moduleInstance, uint_fast16_t mask); - -//***************************************************************************** -// -//! Clears I2C interrupt sources. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param mask is a bit mask of the interrupt sources to be cleared. -//! -//! The I2C interrupt source is cleared, so that it no longer asserts. -//! The highest interrupt flag is automatically cleared when an interrupt vector -//! generator is used. -//! -//! The mask parameter has the same definition as the mask -//! parameter to I2C_enableInterrupt(). -//! -//! Modified register is \b UCBxIFG. -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_clearInterruptFlag(uint32_t moduleInstance, uint_fast16_t mask); - -//***************************************************************************** -// -//! Gets the current I2C interrupt status. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! \param mask is the masked interrupt flag status to be returned. -//! Mask value is the logical OR of any of the following: -//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt -//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost -//! interrupt -//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt -//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 -//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt -//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout -//! interrupt enable -//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt -//! enable -//! -//! \return the masked status of the interrupt flag -//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt -//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 -//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt -//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost interrupt -//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt enable -//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout interrupt -//! enable -//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt enable -// -//***************************************************************************** -extern uint_fast16_t I2C_getInterruptStatus(uint32_t moduleInstance, uint16_t mask); - -//***************************************************************************** -// -//! Gets the current I2C interrupt status masked with the enabled interrupts. -//! This function is useful to call in ISRs to get a list of pending interrupts -//! that are actually enabled and could have caused the ISR. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \return the masked status of the interrupt flag -//! - \b EUSCI_B_I2C_STOP_INTERRUPT - STOP condition interrupt -//! - \b EUSCI_B_I2C_START_INTERRUPT - START condition interrupt -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT0 - Transmit interrupt0 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT1 - Transmit interrupt1 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT2 - Transmit interrupt2 -//! - \b EUSCI_B_I2C_TRANSMIT_INTERRUPT3 - Transmit interrupt3 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT0 - Receive interrupt0 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT1 - Receive interrupt1 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT2 - Receive interrupt2 -//! - \b EUSCI_B_I2C_RECEIVE_INTERRUPT3 - Receive interrupt3 -//! - \b EUSCI_B_I2C_NAK_INTERRUPT - Not-acknowledge interrupt -//! - \b EUSCI_B_I2C_ARBITRATIONLOST_INTERRUPT - Arbitration lost interrupt -//! - \b EUSCI_B_I2C_BIT9_POSITION_INTERRUPT - Bit position 9 interrupt enable -//! - \b EUSCI_B_I2C_CLOCK_LOW_TIMEOUT_INTERRUPT - Clock low timeout interrupt -//! enable -//! - \b EUSCI_B_I2C_BYTE_COUNTER_INTERRUPT - Byte counter interrupt enable -// -//***************************************************************************** -extern uint_fast16_t I2C_getEnabledInterruptStatus(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Registers an interrupt handler for I2C interrupts. -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param intHandler is a pointer to the function to be called when the -//! timer capture compare interrupt occurs. -//! -//! This function registers the handler to be called when an I2C -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific I2C interrupts must be enabled -//! via I2C_enableInterrupt(). It is the interrupt handler's responsibility to -//! clear the interrupt source via I2C_clearInterruptFlag(). -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_registerInterrupt(uint32_t moduleInstance, - void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the timer -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! This function unregisters the handler to be called when timer -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_unregisterInterrupt(uint32_t moduleInstance); - - -//***************************************************************************** -// -//! This function is used by the slave to send a NAK out over the I2C line -//! -//! \param moduleInstance is the instance of the eUSCI B (I2C) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//!
It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \return None. -// -//***************************************************************************** -extern void I2C_slaveSendNAK(uint32_t moduleInstance); - -/* Backwards Compatibility Layer */ -#define EUSCI_B_I2C_slaveInit I2C_initSlave -#define EUSCI_B_I2C_enable I2C_enableModule -#define EUSCI_B_I2C_disable I2C_disableModule -#define EUSCI_B_I2C_setSlaveAddress I2C_setSlaveAddress -#define EUSCI_B_I2C_setMode I2C_setMode -#define EUSCI_B_I2C_getMode I2C_getMode -#define EUSCI_B_I2C_slaveDataPut I2C_slavePutData -#define EUSCI_B_I2C_slaveDataGet I2C_slaveGetData -#define EUSCI_B_I2C_isBusBusy I2C_isBusBusy -#define EUSCI_B_I2C_masterIsStopSent I2C_masterIsStopSent -#define EUSCI_B_I2C_masterIsStartSent I2C_masterIsStartSent -#define EUSCI_B_I2C_enableInterrupt I2C_enableInterrupt -#define EUSCI_B_I2C_disableInterrupt I2C_disableInterrupt -#define EUSCI_B_I2C_clearInterruptFlag I2C_clearInterruptFlag -#define EUSCI_B_I2C_getInterruptStatus I2C_getEnabledInterruptStatus -#define EUSCI_B_I2C_masterSendSingleByte I2C_masterSendSingleByte -#define EUSCI_B_I2C_masterReceiveSingleByte I2C_masterReceiveSingleByte -#define EUSCI_B_I2C_masterSendSingleByteWithTimeout I2C_masterSendSingleByteWithTimeout -#define EUSCI_B_I2C_masterMultiByteSendStart I2C_masterSendMultiByteStart -#define EUSCI_B_I2C_masterMultiByteSendStartWithTimeout I2C_masterSendMultiByteStartWithTimeout -#define EUSCI_B_I2C_masterMultiByteSendNext I2C_masterSendMultiByteNext -#define EUSCI_B_I2C_masterMultiByteSendNextWithTimeout I2C_masterSendMultiByteNextWithTimeout -#define EUSCI_B_I2C_masterMultiByteSendFinish I2C_masterSendMultiByteFinish -#define EUSCI_B_I2C_masterMultiByteSendFinishWithTimeout I2C_masterSendMultiByteFinishWithTimeout -#define EUSCI_B_I2C_masterSendStart I2C_masterSendStart -#define EUSCI_B_I2C_masterMultiByteSendStop I2C_masterSendMultiByteStop -#define EUSCI_B_I2C_masterMultiByteSendStopWithTimeout I2C_masterSendMultiByteStopWithTimeout -#define EUSCI_B_I2C_masterReceiveStart I2C_masterReceiveStart -#define EUSCI_B_I2C_masterMultiByteReceiveNext I2C_masterReceiveMultiByteNext -#define EUSCI_B_I2C_masterMultiByteReceiveFinish I2C_masterReceiveMultiByteFinish -#define EUSCI_B_I2C_masterMultiByteReceiveFinishWithTimeout I2C_masterReceiveMultiByteFinishWithTimeout -#define EUSCI_B_I2C_masterMultiByteReceiveStop I2C_masterReceiveMultiByteStop -#define EUSCI_B_I2C_enableMultiMasterMode I2C_enableMultiMasterMode -#define EUSCI_B_I2C_disableMultiMasterMode I2C_disableMultiMasterMode -#define EUSCI_B_I2C_masterSingleReceive I2C_masterReceiveSingle -#define EUSCI_B_I2C_getReceiveBufferAddressForDMA I2C_getReceiveBufferAddressForDMA -#define EUSCI_B_I2C_getTransmitBufferAddressForDMA I2C_getTransmitBufferAddressForDMA - - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* I2C_H_ */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/interrupt.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/interrupt.c deleted file mode 100644 index d6947bf44a8..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/interrupt.c +++ /dev/null @@ -1,533 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/* Standard Includes */ -#include - -/* DriverLib Includes */ -#include -#include -#include - - -//***************************************************************************** -// -// This is a mapping between priority grouping encodings and the number of -// preemption priority bits. -// -//***************************************************************************** -static const uint32_t g_pulPriority[] = -{ NVIC_APINT_PRIGROUP_0_8, NVIC_APINT_PRIGROUP_1_7, NVIC_APINT_PRIGROUP_2_6, -NVIC_APINT_PRIGROUP_3_5, NVIC_APINT_PRIGROUP_4_4, -NVIC_APINT_PRIGROUP_5_3, NVIC_APINT_PRIGROUP_6_2, -NVIC_APINT_PRIGROUP_7_1 }; - -//***************************************************************************** -// -// This is a mapping between interrupt number and the register that contains -// the priority encoding for that interrupt. -// -//***************************************************************************** -static const uint32_t g_pulRegs[] = -{ 0, NVIC_SYS_PRI1_R, NVIC_SYS_PRI2_R, NVIC_SYS_PRI3_R, NVIC_PRI0_R, -NVIC_PRI1_R, NVIC_PRI2_R, NVIC_PRI3_R, NVIC_PRI4_R, NVIC_PRI5_R, -NVIC_PRI6_R, NVIC_PRI7_R, NVIC_PRI8_R, NVIC_PRI9_R, NVIC_PRI10_R, -NVIC_PRI11_R, NVIC_PRI12_R, NVIC_PRI13_R, NVIC_PRI14_R, NVIC_PRI15_R }; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt enable for that -// interrupt. -// -//***************************************************************************** -static const uint32_t g_pulEnRegs[] = -{ NVIC_EN0_R, NVIC_EN1_R }; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt disable for that -// interrupt. -// -//***************************************************************************** -static const uint32_t g_pulDisRegs[] = -{ NVIC_DIS0_R, NVIC_DIS1_R }; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt pend for that interrupt. -// -//***************************************************************************** -static const uint32_t g_pulPendRegs[] = -{ NVIC_PEND0_R, NVIC_PEND1_R }; - -//***************************************************************************** -// -// This is a mapping between interrupt number (for the peripheral interrupts -// only) and the register that contains the interrupt unpend for that -// interrupt. -// -//***************************************************************************** -static const uint32_t g_pulUnpendRegs[] = -{ NVIC_UNPEND0_R, NVIC_UNPEND1_R }; - -//***************************************************************************** -// -//! \internal -//! The default interrupt handler. -//! -//! This is the default interrupt handler for all interrupts. It simply loops -//! forever so that the system state is preserved for observation by a -//! debugger. Since interrupts should be disabled before unregistering the -//! corresponding handler, this should never be called. -//! -//! \return None. -// -//***************************************************************************** -static void IntDefaultHandler(void) -{ - // - // Go into an infinite loop. - // - while (1) - { - } -} - -//***************************************************************************** -// -// The processor vector table. -// -// This contains a list of the handlers for the various interrupt sources in -// the system. The layout of this list is defined by the hardware; assertion -// of an interrupt causes the processor to start executing directly at the -// address given in the corresponding location in this list. -// -//***************************************************************************** -#if defined(__IAR_SYSTEMS_ICC__) -#pragma data_alignment=1024 -static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS+1])(void) @ "VTABLE"; -#elif defined(__TI_COMPILER_VERSION__) -#pragma DATA_ALIGN(g_pfnRAMVectors, 1024) -#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable") -void (*g_pfnRAMVectors[NUM_INTERRUPTS + 1])(void); -#else -static __attribute__((section("vtable"))) -void (*g_pfnRAMVectors[NUM_INTERRUPTS+1])(void) __attribute__((aligned(1024))); -#endif - -bool Interrupt_enableMaster(void) -{ - // - // Enable processor interrupts. - // - return (CPU_cpsie()); -} - -bool Interrupt_disableMaster(void) -{ - // - // Disable processor interrupts. - // - return (CPU_cpsid()); -} - -void Interrupt_registerInterrupt(uint32_t interruptNumber, - void (*intHandler)(void)) -{ - uint32_t ulIdx, ulValue; - - // - // Check the arguments. - // - ASSERT(interruptNumber < (NUM_INTERRUPTS+1)); - - // - // Make sure that the RAM vector table is correctly aligned. - // - ASSERT(((uint32_t) g_pfnRAMVectors & 0x000000ff) == 0); - - // - // See if the RAM vector table has been initialized. - // - if (SCB->VTOR != (uint32_t) g_pfnRAMVectors) - { - // - // Copy the vector table from the beginning of FLASH to the RAM vector - // table. - // - ulValue = SCB->VTOR; - for (ulIdx = 0; ulIdx < (NUM_INTERRUPTS + 1); ulIdx++) - { - g_pfnRAMVectors[ulIdx] = (void (*)(void)) HWREG32( - (ulIdx * 4) + ulValue); - } - - // - // Point the NVIC at the RAM vector table. - // - SCB->VTOR = (uint32_t) g_pfnRAMVectors; - } - - // - // Save the interrupt handler. - // - g_pfnRAMVectors[interruptNumber] = intHandler; -} - -void Interrupt_unregisterInterrupt(uint32_t interruptNumber) -{ - // - // Check the arguments. - // - ASSERT(interruptNumber < (NUM_INTERRUPTS+1)); - - // - // Reset the interrupt handler. - // - g_pfnRAMVectors[interruptNumber] = IntDefaultHandler; -} - -void Interrupt_setPriorityGrouping(uint32_t bits) -{ - // - // Check the arguments. - // - ASSERT(bits < NUM_PRIORITY); - - // - // Set the priority grouping. - // - SCB->AIRCR = SCB_AIRCR_VECTKEY_Msk | g_pulPriority[bits]; -} - -uint32_t Interrupt_getPriorityGrouping(void) -{ - uint32_t ulLoop, ulValue; - - // - // Read the priority grouping. - // - ulValue = SCB->AIRCR & NVIC_APINT_PRIGROUP_M; - - // - // Loop through the priority grouping values. - // - for (ulLoop = 0; ulLoop < NUM_PRIORITY; ulLoop++) - { - // - // Stop looping if this value matches. - // - if (ulValue == g_pulPriority[ulLoop]) - { - break; - } - } - - // - // Return the number of priority bits. - // - return (ulLoop); -} - -void Interrupt_setPriority(uint32_t interruptNumber, uint8_t priority) -{ - uint32_t ulTemp; - - // - // Check the arguments. - // - ASSERT((interruptNumber >= 4) && (interruptNumber < (NUM_INTERRUPTS+1))); - - // - // Set the interrupt priority. - // - ulTemp = HWREG32(g_pulRegs[interruptNumber >> 2]); - ulTemp &= ~(0xFF << (8 * (interruptNumber & 3))); - ulTemp |= priority << (8 * (interruptNumber & 3)); - HWREG32 (g_pulRegs[interruptNumber >> 2]) = ulTemp; -} - -uint8_t Interrupt_getPriority(uint32_t interruptNumber) -{ - // - // Check the arguments. - // - ASSERT((interruptNumber >= 4) && (interruptNumber < (NUM_INTERRUPTS+1))); - - // - // Return the interrupt priority. - // - return ((HWREG32(g_pulRegs[interruptNumber >> 2]) - >> (8 * (interruptNumber & 3))) & 0xFF); -} - -void Interrupt_enableInterrupt(uint32_t interruptNumber) -{ - // - // Check the arguments. - // - ASSERT(interruptNumber < (NUM_INTERRUPTS+1)); - - // - // Determine the interrupt to enable. - // - if (interruptNumber == FAULT_MPU) - { - // - // Enable the MemManage interrupt. - // - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; - } else if (interruptNumber == FAULT_BUS) - { - // - // Enable the bus fault interrupt. - // - SCB->SHCSR |= SCB_SHCSR_BUSFAULTENA_Msk; - } else if (interruptNumber == FAULT_USAGE) - { - // - // Enable the usage fault interrupt. - // - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk; - } else if (interruptNumber == FAULT_SYSTICK) - { - // - // Enable the System Tick interrupt. - // - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - } else if (interruptNumber >= 16) - { - // - // Enable the general interrupt. - // - HWREG32 (g_pulEnRegs[(interruptNumber - 16) / 32]) = 1 - << ((interruptNumber - 16) & 31); - } -} - -void Interrupt_disableInterrupt(uint32_t interruptNumber) -{ - // - // Check the arguments. - // - ASSERT(interruptNumber < (NUM_INTERRUPTS+1)); - - // - // Determine the interrupt to disable. - // - if (interruptNumber == FAULT_MPU) - { - // - // Disable the MemManage interrupt. - // - SCB->SHCSR &= ~(SCB_SHCSR_MEMFAULTENA_Msk); - } else if (interruptNumber == FAULT_BUS) - { - // - // Disable the bus fault interrupt. - // - SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTENA_Msk); - } else if (interruptNumber == FAULT_USAGE) - { - // - // Disable the usage fault interrupt. - // - SCB->SHCSR &= ~(SCB_SHCSR_USGFAULTENA_Msk); - } else if (interruptNumber == FAULT_SYSTICK) - { - // - // Disable the System Tick interrupt. - // - SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk); - } else if (interruptNumber >= 16) - { - // - // Disable the general interrupt. - // - HWREG32 (g_pulDisRegs[(interruptNumber - 16) / 32]) = 1 - << ((interruptNumber - 16) & 31); - } -} - -bool Interrupt_isEnabled(uint32_t interruptNumber) -{ - uint32_t ulRet; - - // - // Check the arguments. - // - ASSERT(interruptNumber < (NUM_INTERRUPTS+1)); - - // - // Initialize the return value. - // - ulRet = 0; - - // - // Determine the interrupt to disable. - // - if (interruptNumber == FAULT_MPU) - { - // - // Check the MemManage interrupt. - // - ulRet = SCB->SHCSR & SCB_SHCSR_MEMFAULTENA_Msk; - } else if (interruptNumber == FAULT_BUS) - { - // - // Check the bus fault interrupt. - // - ulRet = SCB->SHCSR & SCB_SHCSR_BUSFAULTENA_Msk; - } else if (interruptNumber == FAULT_USAGE) - { - // - // Check the usage fault interrupt. - // - ulRet = SCB->SHCSR & SCB_SHCSR_USGFAULTENA_Msk; - } else if (interruptNumber == FAULT_SYSTICK) - { - // - // Check the System Tick interrupt. - // - ulRet = SysTick->CTRL & SysTick_CTRL_ENABLE_Msk; - } else if (interruptNumber >= 16) - { - // - // Check the general interrupt. - // - ulRet = HWREG32(g_pulEnRegs[(interruptNumber - 16) / 32]) - & (1 << ((interruptNumber - 16) & 31)); - } - return (ulRet); -} - -void Interrupt_pendInterrupt(uint32_t interruptNumber) -{ - // - // Check the arguments. - // - ASSERT(interruptNumber < (NUM_INTERRUPTS+1)); - - // - // Determine the interrupt to pend. - // - if (interruptNumber == FAULT_NMI) - { - // - // Pend the NMI interrupt. - // - SCB->ICSR |= SCB_ICSR_NMIPENDSET_Msk; - } else if (interruptNumber == FAULT_PENDSV) - { - // - // Pend the PendSV interrupt. - // - SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk; - } else if (interruptNumber == FAULT_SYSTICK) - { - // - // Pend the SysTick interrupt. - // - SCB->ICSR |= SCB_ICSR_PENDSTSET_Msk; - } else if (interruptNumber >= 16) - { - // - // Pend the general interrupt. - // - HWREG32 (g_pulPendRegs[(interruptNumber - 16) / 32]) = 1 - << ((interruptNumber - 16) & 31); - } -} - -void Interrupt_unpendInterrupt(uint32_t interruptNumber) -{ - // - // Check the arguments. - // - ASSERT(interruptNumber < (NUM_INTERRUPTS+1)); - - // - // Determine the interrupt to unpend. - // - if (interruptNumber == FAULT_PENDSV) - { - // - // Unpend the PendSV interrupt. - // - SCB->ICSR |= SCB_ICSR_PENDSVCLR_Msk; - } else if (interruptNumber == FAULT_SYSTICK) - { - // - // Unpend the SysTick interrupt. - // - SCB->ICSR |= SCB_ICSR_PENDSTCLR_Msk; - } else if (interruptNumber >= 16) - { - // - // Unpend the general interrupt. - // - HWREG32 (g_pulUnpendRegs[(interruptNumber - 16) / 32]) = 1 - << ((interruptNumber - 16) & 31); - } -} - -void Interrupt_setPriorityMask(uint8_t priorityMask) -{ - CPU_basepriSet(priorityMask); -} - -uint8_t Interrupt_getPriorityMask(void) -{ - return (CPU_basepriGet()); -} - -void Interrupt_setVectorTableAddress(uint32_t addr) -{ - SCB->VTOR = addr; -} - -uint32_t Interrupt_getVectorTableAddress(void) -{ - return SCB->VTOR; -} - -void Interrupt_enableSleepOnIsrExit(void) -{ - SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; -} - -void Interrupt_disableSleepOnIsrExit(void) -{ - SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk; -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/interrupt.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/interrupt.h deleted file mode 100644 index 3a051d8eee2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/interrupt.h +++ /dev/null @@ -1,576 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -//***************************************************************************** -// -//! \addtogroup interrupt_api -//! @{ -// -//***************************************************************************** - - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include - -/****************************************************************************** -* NVIC interrupts * -******************************************************************************/ -/* System exceptions */ -#define FAULT_NMI ( 2) /* NMI fault */ -#define FAULT_HARD ( 3) /* Hard fault */ -#define FAULT_MPU ( 4) /* MPU fault */ -#define FAULT_BUS ( 5) /* Bus fault */ -#define FAULT_USAGE ( 6) /* Usage fault */ -#define FAULT_SVCALL (11) /* SVCall */ -#define FAULT_DEBUG (12) /* Debug monitor */ -#define FAULT_PENDSV (14) /* PendSV */ -#define FAULT_SYSTICK (15) /* System Tick */ - -/* External interrupts */ -#define INT_PSS (16) /* PSS IRQ */ -#define INT_CS (17) /* CS IRQ */ -#define INT_PCM (18) /* PCM IRQ */ -#define INT_WDT_A (19) /* WDT_A IRQ */ -#define INT_FPU (20) /* FPU IRQ */ -#define INT_FLCTL (21) /* FLCTL IRQ */ -#define INT_COMP_E0 (22) /* COMP_E0 IRQ */ -#define INT_COMP_E1 (23) /* COMP_E1 IRQ */ -#define INT_TA0_0 (24) /* TA0_0 IRQ */ -#define INT_TA0_N (25) /* TA0_N IRQ */ -#define INT_TA1_0 (26) /* TA1_0 IRQ */ -#define INT_TA1_N (27) /* TA1_N IRQ */ -#define INT_TA2_0 (28) /* TA2_0 IRQ */ -#define INT_TA2_N (29) /* TA2_N IRQ */ -#define INT_TA3_0 (30) /* TA3_0 IRQ */ -#define INT_TA3_N (31) /* TA3_N IRQ */ -#define INT_EUSCIA0 (32) /* EUSCIA0 IRQ */ -#define INT_EUSCIA1 (33) /* EUSCIA1 IRQ */ -#define INT_EUSCIA2 (34) /* EUSCIA2 IRQ */ -#define INT_EUSCIA3 (35) /* EUSCIA3 IRQ */ -#define INT_EUSCIB0 (36) /* EUSCIB0 IRQ */ -#define INT_EUSCIB1 (37) /* EUSCIB1 IRQ */ -#define INT_EUSCIB2 (38) /* EUSCIB2 IRQ */ -#define INT_EUSCIB3 (39) /* EUSCIB3 IRQ */ -#define INT_ADC14 (40) /* ADC14 IRQ */ -#define INT_T32_INT1 (41) /* T32_INT1 IRQ */ -#define INT_T32_INT2 (42) /* T32_INT2 IRQ */ -#define INT_T32_INTC (43) /* T32_INTC IRQ */ -#define INT_AES256 (44) /* AES256 IRQ */ -#define INT_RTC_C (45) /* RTC_C IRQ */ -#define INT_DMA_ERR (46) /* DMA_ERR IRQ */ -#define INT_DMA_INT3 (47) /* DMA_INT3 IRQ */ -#define INT_DMA_INT2 (48) /* DMA_INT2 IRQ */ -#define INT_DMA_INT1 (49) /* DMA_INT1 IRQ */ -#define INT_DMA_INT0 (50) /* DMA_INT0 IRQ */ -#define INT_PORT1 (51) /* PORT1 IRQ */ -#define INT_PORT2 (52) /* PORT2 IRQ */ -#define INT_PORT3 (53) /* PORT3 IRQ */ -#define INT_PORT4 (54) /* PORT4 IRQ */ -#define INT_PORT5 (55) /* PORT5 IRQ */ -#define INT_PORT6 (56) /* PORT6 IRQ */ -#define INT_LCD_F (57) /* PORT6 IRQ */ - -#define NUM_INTERRUPTS (57) -//***************************************************************************** -// -// Macro to generate an interrupt priority mask based on the number of bits -// of priority supported by the hardware. -// -//***************************************************************************** -#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) -#define NUM_PRIORITY 8 - -#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping -#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split -#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split -#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split -#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split -#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split -#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split -#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split -#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split -#define NVIC_SYS_PRI1_R 0xE000ED18 // System Handler Priority 1 -#define NVIC_SYS_PRI2_R 0xE000ED1C // System Handler Priority 2 -#define NVIC_SYS_PRI3_R 0xE000ED20 // System Handler Priority 3 -#define NVIC_PRI0_R 0xE000E400 // Interrupt 0-3 Priority -#define NVIC_PRI1_R 0xE000E404 // Interrupt 4-7 Priority -#define NVIC_PRI2_R 0xE000E408 // Interrupt 8-11 Priority -#define NVIC_PRI3_R 0xE000E40C // Interrupt 12-15 Priority -#define NVIC_PRI4_R 0xE000E410 // Interrupt 16-19 Priority -#define NVIC_PRI5_R 0xE000E414 // Interrupt 20-23 Priority -#define NVIC_PRI6_R 0xE000E418 // Interrupt 24-27 Priority -#define NVIC_PRI7_R 0xE000E41C // Interrupt 28-31 Priority -#define NVIC_PRI8_R 0xE000E420 // Interrupt 32-35 Priority -#define NVIC_PRI9_R 0xE000E424 // Interrupt 36-39 Priority -#define NVIC_PRI10_R 0xE000E428 // Interrupt 40-43 Priority -#define NVIC_PRI11_R 0xE000E42C // Interrupt 44-47 Priority -#define NVIC_PRI12_R 0xE000E430 // Interrupt 48-51 Priority -#define NVIC_PRI13_R 0xE000E434 // Interrupt 52-55 Priority -#define NVIC_PRI14_R 0xE000E438 // Interrupt 56-59 Priority -#define NVIC_PRI15_R 0xE000E43C // Interrupt 60-63 Priority -#define NVIC_EN0_R 0xE000E100 // Interrupt 0-31 Set Enable -#define NVIC_EN1_R 0xE000E104 // Interrupt 32-54 Set Enable -#define NVIC_DIS0_R 0xE000E180 // Interrupt 0-31 Clear Enable -#define NVIC_DIS1_R 0xE000E184 // Interrupt 32-54 Clear Enable -#define NVIC_PEND0_R 0xE000E200 // Interrupt 0-31 Set Pending -#define NVIC_PEND1_R 0xE000E204 // Interrupt 32-54 Set Pending -#define NVIC_UNPEND0_R 0xE000E280 // Interrupt 0-31 Clear Pending -#define NVIC_UNPEND1_R 0xE000E284 // Interrupt 32-54 Clear Pending -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! Enables the processor interrupt. -//! -//! This function allows the processor to respond to interrupts. This function -//! does not affect the set of interrupts enabled in the interrupt controller; -//! it just gates the single interrupt from the controller to the processor. -//! -//! \return Returns \b true if interrupts were disabled when the function was -//! called or \b false if they were initially enabled. -// -//***************************************************************************** -extern bool Interrupt_enableMaster(void); - -//***************************************************************************** -// -//! Disables the processor interrupt. -//! -//! This function prevents the processor from receiving interrupts. This -//! function does not affect the set of interrupts enabled in the interrupt -//! controller; it just gates the single interrupt from the controller to the -//! processor. -//! -//! \return Returns \b true if interrupts were already disabled when the -//! function was called or \b false if they were initially enabled. -// -//***************************************************************************** -extern bool Interrupt_disableMaster(void); - -//***************************************************************************** -// -//! Registers a function to be called when an interrupt occurs. -//! -//! \param interruptNumber specifies the interrupt in question. -//! \param intHandler is a pointer to the function to be called. -//! -//! \note The use of this function (directly or indirectly via a peripheral -//! driver interrupt register function) moves the interrupt vector table from -//! flash to SRAM. Therefore, care must be taken when linking the application -//! to ensure that the SRAM vector table is located at the beginning of SRAM; -//! otherwise the NVIC does not look in the correct portion of memory for the -//! vector table (it requires the vector table be on a 1 kB memory alignment). -//! Normally, the SRAM vector table is so placed via the use of linker scripts. -//! See the discussion of compile-time versus run-time interrupt handler -//! registration in the introduction to this chapter. -//! -//! \note This function is only used if the customer wants to specify the -//! interrupt handler at run time. In most cases, this is done through means -//! of the user setting the ISR function pointer in the startup file. Refer -//! Refer to the Module Operation section for more details. -//! -//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt -//! parameter -//! -//! \return None. -// -//***************************************************************************** -extern void Interrupt_registerInterrupt(uint32_t interruptNumber, - void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the function to be called when an interrupt occurs. -//! -//! \param interruptNumber specifies the interrupt in question. -//! -//! This function is used to indicate that no handler should be called when the -//! given interrupt is asserted to the processor. The interrupt source is -//! automatically disabled (via Interrupt_disableInterrupt()) if necessary. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt -//! parameter -//! -//! \return None. -// -//***************************************************************************** -extern void Interrupt_unregisterInterrupt(uint32_t interruptNumber); - -//***************************************************************************** -// -//! Sets the priority grouping of the interrupt controller. -//! -//! \param bits specifies the number of bits of preemptable priority. -//! -//! This function specifies the split between preemptable priority levels and -//! sub-priority levels in the interrupt priority specification. The range of -//! the grouping values are dependent upon the hardware implementation; on -//! the MSP432 family, three bits are available for hardware interrupt -//! prioritization and therefore priority grouping values of three through -//! seven have the same effect. -//! -//! \return None. -// -//***************************************************************************** -extern void Interrupt_setPriorityGrouping(uint32_t bits); - -//***************************************************************************** -// -//! Gets the priority grouping of the interrupt controller. -//! -//! This function returns the split between preemptable priority levels and -//! sub-priority levels in the interrupt priority specification. -//! -//! \return The number of bits of preemptable priority. -// -//***************************************************************************** -extern uint32_t Interrupt_getPriorityGrouping(void); - -//***************************************************************************** -// -//! Sets the priority of an interrupt. -//! -//! \param interruptNumber specifies the interrupt in question. -//! \param priority specifies the priority of the interrupt. -//! -//! This function is used to set the priority of an interrupt. When multiple -//! interrupts are asserted simultaneously, the ones with the highest priority -//! are processed before the lower priority interrupts. Smaller numbers -//! correspond to higher interrupt priorities; priority 0 is the highest -//! interrupt priority. -//! -//! The hardware priority mechanism only looks at the upper N bits of the -//! priority level (where N is 3 for the MSP432 family), so any -//! prioritization must be performed in those bits. The remaining bits can be -//! used to sub-prioritize the interrupt sources, and may be used by the -//! hardware priority mechanism on a future part. This arrangement allows -//! priorities to migrate to different NVIC implementations without changing -//! the gross prioritization of the interrupts. -//! -//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt -//! parameter -//! -//! \return None. -// -//***************************************************************************** -extern void Interrupt_setPriority(uint32_t interruptNumber, uint8_t priority); - -//***************************************************************************** -// -//! Gets the priority of an interrupt. -//! -//! \param interruptNumber specifies the interrupt in question. -//! -//! This function gets the priority of an interrupt. See -//! Interrupt_setPriority() for a definition of the priority value. -//! -//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt -//! parameter -//! -//! \return Returns the interrupt priority, or -1 if an invalid interrupt was -//! specified. -// -//***************************************************************************** -extern uint8_t Interrupt_getPriority(uint32_t interruptNumber); - -//***************************************************************************** -// -//! Enables an interrupt. -//! -//! \param interruptNumber specifies the interrupt to be enabled. -//! -//! The specified interrupt is enabled in the interrupt controller. Other -//! enables for the interrupt (such as at the peripheral level) are unaffected -//! by this function. -//! -//! Valid values will vary from part to part, so it is important to check the -//! device specific datasheet, however for MSP432 101 the following values can -//! be provided: -//! - \b FAULT_NMI -//! - \b FAULT_HARD -//! - \b FAULT_MPU -//! - \b FAULT_BUS -//! - \b FAULT_USAGE -//! - \b FAULT_SVCALL -//! - \b FAULT_DEBUG -//! - \b FAULT_PENDSV -//! - \b FAULT_SYSTICK -//! - \b INT_PSS -//! - \b INT_CS -//! - \b INT_PCM -//! - \b INT_WDT_A -//! - \b INT_FPU -//! - \b INT_FLCTL -//! - \b INT_COMP0 -//! - \b INT_COMP1 -//! - \b INT_TA0_0 -//! - \b INT_TA0_N -//! - \b INT_TA1_0 -//! - \b INT_TA1_N -//! - \b INT_TA2_0 -//! - \b INT_TA2_N -//! - \b INT_TA3_0 -//! - \b INT_TA3_N -//! - \b INT_EUSCIA0 -//! - \b INT_EUSCIA1 -//! - \b INT_EUSCIA2 -//! - \b INT_EUSCIA3 -//! - \b INT_EUSCIB0 -//! - \b INT_EUSCIB1 -//! - \b INT_EUSCIB2 -//! - \b INT_EUSCIB3 -//! - \b INT_ADC14 -//! - \b INT_T32_INT1 -//! - \b INT_T32_INT2 -//! - \b INT_T32_INTC -//! - \b INT_AES -//! - \b INT_RTCC -//! - \b INT_DMA_ERR -//! - \b INT_DMA_INT3 -//! - \b INT_DMA_INT2 -//! - \b INT_DMA_INT1 -//! - \b INT_DMA_INT0 -//! - \b INT_PORT1 -//! - \b INT_PORT2 -//! - \b INT_PORT3 -//! - \b INT_PORT4 -//! - \b INT_PORT5 -//! - \b INT_PORT6 -//! -//! \return None. -// -//***************************************************************************** -extern void Interrupt_enableInterrupt(uint32_t interruptNumber); - -//***************************************************************************** -// -//! Disables an interrupt. -//! -//! \param interruptNumber specifies the interrupt to be disabled. -//! -//! The specified interrupt is disabled in the interrupt controller. Other -//! enables for the interrupt (such as at the peripheral level) are unaffected -//! by this function. -//! -//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt -//! parameter -//! -//! \return None. -// -//***************************************************************************** -extern void Interrupt_disableInterrupt(uint32_t interruptNumber); - -//***************************************************************************** -// -//! Returns if a peripheral interrupt is enabled. -//! -//! \param interruptNumber specifies the interrupt to check. -//! -//! This function checks if the specified interrupt is enabled in the interrupt -//! controller. -//! -//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt -//! parameter -//! -//! \return A non-zero value if the interrupt is enabled. -// -//***************************************************************************** -extern bool Interrupt_isEnabled(uint32_t interruptNumber); - -//***************************************************************************** -// -//! Pends an interrupt. -//! -//! \param interruptNumber specifies the interrupt to be pended. -//! -//! The specified interrupt is pended in the interrupt controller. Pending an -//! interrupt causes the interrupt controller to execute the corresponding -//! interrupt handler at the next available time, based on the current -//! interrupt state priorities. For example, if called by a higher priority -//! interrupt handler, the specified interrupt handler is not called until -//! after the current interrupt handler has completed execution. The interrupt -//! must have been enabled for it to be called. -//! -//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt -//! parameter -//! -//! \return None. -// -//***************************************************************************** -extern void Interrupt_pendInterrupt(uint32_t interruptNumber); - -//***************************************************************************** -// -//! Un-pends an interrupt. -//! -//! \param interruptNumber specifies the interrupt to be un-pended. -//! -//! The specified interrupt is un-pended in the interrupt controller. This -//! will cause any previously generated interrupts that have not been handled -//! yet (due to higher priority interrupts or the interrupt no having been -//! enabled yet) to be discarded. -//! -//! See \link Interrupt_enableInterrupt \endlink for details about the interrupt -//! parameter -//! -//! \return None. -// -//***************************************************************************** -extern void Interrupt_unpendInterrupt(uint32_t interruptNumber); - -//***************************************************************************** -// -//! Sets the priority masking level -//! -//! \param priorityMask is the priority level that is masked. -//! -//! This function sets the interrupt priority masking level so that all -//! interrupts at the specified or lesser priority level are masked. Masking -//! interrupts can be used to globally disable a set of interrupts with -//! priority below a predetermined threshold. A value of 0 disables priority -//! masking. -//! -//! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 allows interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater are blocked. -//! -//! The hardware priority mechanism only looks at the upper N bits of the -//! priority level (where N is 3 for the MSP432 family), so any -//! prioritization must be performed in those bits. -//! -//! \return None. -// -//***************************************************************************** -extern void Interrupt_setPriorityMask(uint8_t priorityMask); - -//***************************************************************************** -// -//! Gets the priority masking level -//! -//! This function gets the current setting of the interrupt priority masking -//! level. The value returned is the priority level such that all interrupts -//! of that and lesser priority are masked. A value of 0 means that priority -//! masking is disabled. -//! -//! Smaller numbers correspond to higher interrupt priorities. So for example -//! a priority level mask of 4 allows interrupts of priority level 0-3, -//! and interrupts with a numerical priority of 4 and greater are blocked. -//! -//! The hardware priority mechanism only looks at the upper N bits of the -//! priority level (where N is 3 for the MSP432 family), so any -//! prioritization must be performed in those bits. -//! -//! \return Returns the value of the interrupt priority level mask. -// -//***************************************************************************** -extern uint8_t Interrupt_getPriorityMask(void); - -//***************************************************************************** -// -//! Sets the address of the vector table. This function is for advanced users -//! who might want to switch between multiple instances of vector tables -//! (perhaps between flash/ram). -//! -//! \param addr is the new address of the vector table. -//! -//! \return None. -// -//***************************************************************************** -extern void Interrupt_setVectorTableAddress(uint32_t addr); - -//***************************************************************************** -// -//! Returns the address of the interrupt vector table. -//! -//! \return Address of the vector table. -// -//***************************************************************************** -extern uint32_t Interrupt_getVectorTableAddress(void); - -//***************************************************************************** -// -//! Enables the processor to sleep when exiting an ISR. For low power operation, -//! this is ideal as power cycles are not wasted with the processing required -//! for waking up from an ISR and going back to sleep. -//! -//! \return None -// -//***************************************************************************** -extern void Interrupt_enableSleepOnIsrExit(void); - -//***************************************************************************** -// -//! Disables the processor to sleep when exiting an ISR. -//! -//! \return None -// -//***************************************************************************** -extern void Interrupt_disableSleepOnIsrExit(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif // __INTERRUPT_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/lcd_f.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/lcd_f.c deleted file mode 100644 index f20c7d15ade..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/lcd_f.c +++ /dev/null @@ -1,262 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include - -/* Define to ensure that our current MSP432 has the LCD_F module. This - definition is included in the device specific header file */ -#ifdef __MCU_HAS_LCD_F__ - -/* Configuration functions */ -void LCD_F_initModule(LCD_F_Config *initParams) -{ - BITBAND_PERI(LCD_F->CTL,LCD_F_CTL_ON_OFS) = 0; - - LCD_F->CTL = (LCD_F->CTL - & ~(LCD_F_CTL_MX_MASK | LCD_F_CTL_SSEL_MASK | LCD_F_CTL_LP - | LCD_F_CTL_ON | LCD_F_CTL_DIV_MASK | LCD_F_CTL_PRE_MASK - | LCD_F_CTL_SON)) - | (initParams->muxRate | initParams->clockSource - | initParams->waveforms | initParams->segments - | initParams->clockDivider | initParams->clockPrescaler); -} - -void LCD_F_turnOn(void) -{ - BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 1; -} - -void LCD_F_turnOff(void) -{ - BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0; -} - -/* Memory management functions */ -void LCD_F_clearAllMemory(void) -{ - BITBAND_PERI(LCD_F->BMCTL , LCD_F_BMCTL_CLRM_OFS) = 1; -} - -void LCD_F_clearAllBlinkingMemory(void) -{ - BITBAND_PERI(LCD_F->BMCTL , LCD_F_BMCTL_CLRBM_OFS) = 1; -} - -void LCD_F_selectDisplayMemory(uint_fast16_t displayMemory) -{ - BITBAND_PERI(LCD_F->BMCTL , LCD_F_BMCTL_DISP_OFS) = displayMemory; -} - -void LCD_F_setBlinkingControl(uint_fast16_t clockPrescalar, - uint_fast16_t divider, uint_fast16_t mode) -{ - LCD_F->BMCTL = (LCD_F->BMCTL - & ~(LCD_F_BMCTL_BLKPRE_MASK | LCD_F_BMCTL_BLKDIV_MASK - | LCD_F_BMCTL_BLKMOD_MASK)) | clockPrescalar | mode - | divider; -} - -void LCD_F_setAnimationControl(uint_fast16_t clockPrescalar, - uint_fast16_t divider, uint_fast16_t frames) -{ - LCD_F->ANMCTL = (LCD_F->ANMCTL - & ~(LCD_F_ANMCTL_ANMPRE_MASK | LCD_F_ANMCTL_ANMDIV_MASK - | LCD_F_ANMCTL_ANMSTP_MASK)) | clockPrescalar | divider - | frames; -} - -void LCD_F_enableAnimation(void) -{ - BITBAND_PERI(LCD_F->ANMCTL, LCD_F_ANMCTL_ANMEN_OFS) = 1; -} - -void LCD_F_disableAnimation(void) -{ - BITBAND_PERI(LCD_F->ANMCTL, LCD_F_ANMCTL_ANMEN_OFS) = 0; -} - -void LCD_F_clearAllAnimationMemory(void) -{ - BITBAND_PERI(LCD_F->ANMCTL, LCD_F_ANMCTL_ANMCLR_OFS) = 1; -} - -/* Pin Configuration Functions */ -void LCD_F_setPinAsLCDFunction(uint_fast8_t pin) -{ - uint32_t val = (pin & 0x1F); - - BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0; - - if((pin >> 5) == 0) - { - BITBAND_PERI(LCD_F->PCTL0, val) = 1; - } - else - { - BITBAND_PERI(LCD_F->PCTL1, val) = 1; - } -} - -void LCD_F_setPinAsPortFunction(uint_fast8_t pin) -{ - uint32_t val = (pin & 0x1F); - - BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0; - - if((pin >> 5) == 0) - { - BITBAND_PERI(LCD_F->PCTL0, val) = 0; - } - else - { - BITBAND_PERI(LCD_F->PCTL1, val) = 0; - } -} - -void LCD_F_setPinsAsLCDFunction(uint_fast8_t startPin, uint8_t endPin) -{ - uint32_t startIdx = startPin >> 5; - uint32_t endIdx = endPin >> 5; - uint32_t startPos = startPin & 0x1F; - uint32_t endPos = endPin & 0x1F; - - BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0; - - if (startIdx == endIdx) - { - if (startIdx == 0) - { - LCD_F->PCTL0 |= (0xFFFFFFFF >> (31 - endPos)) - & (0xFFFFFFFF << startPos); - } else - { - LCD_F->PCTL1 |= (0xFFFFFFFF >> (31 - endPos)) - & (0xFFFFFFFF << startPos); - } - } else - { - LCD_F->PCTL0 |= (0xFFFFFFFF << startPos); - LCD_F->PCTL1 |= (0xFFFFFFFF >> (31 - endPos)); - } -} - -void LCD_F_setPinAsCOM(uint8_t pin, uint_fast8_t com) -{ - uint32_t val = (pin & 0x1F); - - BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0; - - if((pin >> 5) == 0) - { - BITBAND_PERI(LCD_F->CSSEL0, val) = 1; - } - else - { - BITBAND_PERI(LCD_F->CSSEL1, val) = 1; - } - - // Setting the relevant COM pin - HWREG8(LCD_F_BASE + OFS_LCDM0W + pin) |= com; - HWREG8(LCD_F_BASE + OFS_LCDBM0W + pin) |= com; - -} - -void LCD_F_setPinAsSEG(uint_fast8_t pin) -{ - uint32_t val = (pin & 0x1F); - - BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0; - - if((pin >> 5) == 0) - { - BITBAND_PERI(LCD_F->CSSEL0, val) = 0; - } - else - { - BITBAND_PERI(LCD_F->CSSEL1, val) = 0; - } -} - -void LCD_F_selectBias(uint_fast16_t bias) -{ - BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0; - LCD_F->VCTL = (LCD_F->VCTL & ~LCD_F_VCTL_LCD2B) | bias; -} - -void LCD_F_setVLCDSource(uint_fast16_t v2v3v4Source, uint_fast16_t v5Source) -{ - BITBAND_PERI(LCD_F->CTL, LCD_F_CTL_ON_OFS) = 0; - LCD_F->VCTL = (LCD_F->VCTL - & ~(LCD_F_VCTL_REXT | LCD_F_VCTL_EXTBIAS - | LCD_F_VCTL_R03EXT)) | v2v3v4Source | v5Source; -} - -/* Interrupt Management */ -void LCD_F_clearInterrupt(uint32_t mask) -{ - LCD_F->CLRIFG |= mask; -} - -uint32_t LCD_F_getInterruptStatus(void) -{ - return LCD_F->IFG; -} - -uint32_t LCD_F_getEnabledInterruptStatus(void) -{ - return (LCD_F->IFG & LCD_F->IE); -} - -void LCD_F_enableInterrupt(uint32_t mask) -{ - LCD_F->IE |= mask; -} - -void LCD_F_disableInterrupt(uint32_t mask) -{ - LCD_F->IE &= ~mask; -} - -void LCD_F_registerInterrupt(void (*intHandler)(void)) -{ - Interrupt_registerInterrupt(INT_LCD_F, intHandler); - Interrupt_enableInterrupt(INT_LCD_F); -} - -void LCD_F_unregisterInterrupt(void) -{ - Interrupt_disableInterrupt(INT_LCD_F); - Interrupt_unregisterInterrupt(INT_LCD_F); -} - -#endif /* __MCU_HAS_LCD_F__ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/lcd_f.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/lcd_f.h deleted file mode 100644 index ea75c5fae15..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/lcd_f.h +++ /dev/null @@ -1,1203 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef LCD_F_H_ -#define LCD_F_H_ - -#include -#include -#include - -/* Define to ensure that our current MSP432 has the LCD_F module. This - definition is included in the device specific header file */ -#ifdef __MCU_HAS_LCD_F__ - -//***************************************************************************** -// -//! \addtogroup lcd_f_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -typedef struct LCD_F_initParam -{ - //! Selects the clock that will be used by the LCD_F_E. - //! \n Valid values are: - //! - \b LCD_F_CLOCKSOURCE_XTCLK [Default] - //! - \b LCD_F_CLOCKSOURCE_ACLK [Default] - //! - \b LCD_F_CLOCKSOURCE_VLOCLK - //! - \b LCD_F_CLOCKSOURCE_LFXT - uint32_t clockSource; - //! Selects the divider for LCD frequency. - //! \n Valid values are: - //! - \b LCD_F_CLOCKDIVIDER_1 [Default] - //! - \b LCD_F_CLOCKDIVIDER_2 - //! - \b LCD_F_CLOCKDIVIDER_3 - //! - \b LCD_F_CLOCKDIVIDER_4 - //! - \b LCD_F_CLOCKDIVIDER_5 - //! - \b LCD_F_CLOCKDIVIDER_6 - //! - \b LCD_F_CLOCKDIVIDER_7 - //! - \b LCD_F_CLOCKDIVIDER_8 - //! - \b LCD_F_CLOCKDIVIDER_9 - //! - \b LCD_F_CLOCKDIVIDER_10 - //! - \b LCD_F_CLOCKDIVIDER_11 - //! - \b LCD_F_CLOCKDIVIDER_12 - //! - \b LCD_F_CLOCKDIVIDER_13 - //! - \b LCD_F_CLOCKDIVIDER_14 - //! - \b LCD_F_CLOCKDIVIDER_15 - //! - \b LCD_F_CLOCKDIVIDER_16 - //! - \b LCD_F_CLOCKDIVIDER_17 - //! - \b LCD_F_CLOCKDIVIDER_18 - //! - \b LCD_F_CLOCKDIVIDER_19 - //! - \b LCD_F_CLOCKDIVIDER_20 - //! - \b LCD_F_CLOCKDIVIDER_21 - //! - \b LCD_F_CLOCKDIVIDER_22 - //! - \b LCD_F_CLOCKDIVIDER_23 - //! - \b LCD_F_CLOCKDIVIDER_24 - //! - \b LCD_F_CLOCKDIVIDER_25 - //! - \b LCD_F_CLOCKDIVIDER_26 - //! - \b LCD_F_CLOCKDIVIDER_27 - //! - \b LCD_F_CLOCKDIVIDER_28 - //! - \b LCD_F_CLOCKDIVIDER_29 - //! - \b LCD_F_CLOCKDIVIDER_30 - //! - \b LCD_F_CLOCKDIVIDER_31 - //! - \b LCD_F_CLOCKDIVIDER_32 - uint32_t clockDivider; - //! Selects the prescaler - //! \n Valid values are: - //! - \b LCD_F_CLOCKPRESCALER_1 [Default] - //! - \b LCD_F_CLOCKPRESCALER_2 - //! - \b LCD_F_CLOCKPRESCALER_4 - //! - \b LCD_F_CLOCKPRESCALER_8 - //! - \b LCD_F_CLOCKPRESCALER_16 - //! - \b LCD_F_CLOCKPRESCALER_32 - uint32_t clockPrescaler; - //! Selects LCD_F_E mux rate. - //! \n Valid values are: - //! - \b LCD_F_STATIC [Default] - //! - \b LCD_F_2_MUX - //! - \b LCD_F_3_MUX - //! - \b LCD_F_4_MUX - //! - \b LCD_F_5_MUX - //! - \b LCD_F_6_MUX - //! - \b LCD_F_7_MUX - //! - \b LCD_F_8_MUX - uint32_t muxRate; - //! Selects LCD waveform mode. - //! \n Valid values are: - //! - \b LCD_F_STANDARD_WAVEFORMS [Default] - //! - \b LCD_F_LOW_POWER_WAVEFORMS - uint32_t waveforms; - //! Sets LCD segment on/off. - //! \n Valid values are: - //! - \b LCD_F_SEGMENTS_DISABLED [Default] - //! - \b LCD_F_SEGMENTS_ENABLED - uint32_t segments; -} LCD_F_Config; - -//***************************************************************************** -// -// The following are values that can be passed to the initParams parameter for -// functions: LCD_F_initModule(). -// -//***************************************************************************** -#define LCD_F_CLOCKSOURCE_ACLK (LCD_F_CTL_SSEL_0) -#define LCD_F_CLOCKSOURCE_VLOCLK (LCD_F_CTL_SSEL_1) -#define LCD_F_CLOCKSOURCE_REFOCLK (LCD_F_CTL_SSEL_2) -#define LCD_F_CLOCKSOURCE_LFXT (LCD_F_CTL_SSEL_3) - - -//***************************************************************************** -// -// The following are values that can be passed to the initParams parameter for -// functions: LCD_F_initModule(). -// -//***************************************************************************** -#define LCD_F_CLOCKDIVIDER_1 0x0 -#define LCD_F_CLOCKDIVIDER_2 0x800 -#define LCD_F_CLOCKDIVIDER_3 0x1000 -#define LCD_F_CLOCKDIVIDER_4 0x1800 -#define LCD_F_CLOCKDIVIDER_5 0x2000 -#define LCD_F_CLOCKDIVIDER_6 0x2800 -#define LCD_F_CLOCKDIVIDER_7 0x3000 -#define LCD_F_CLOCKDIVIDER_8 0x3800 -#define LCD_F_CLOCKDIVIDER_9 0x4000 -#define LCD_F_CLOCKDIVIDER_10 0x4800 -#define LCD_F_CLOCKDIVIDER_11 0x5000 -#define LCD_F_CLOCKDIVIDER_12 0x5800 -#define LCD_F_CLOCKDIVIDER_13 0x6000 -#define LCD_F_CLOCKDIVIDER_14 0x6800 -#define LCD_F_CLOCKDIVIDER_15 0x7000 -#define LCD_F_CLOCKDIVIDER_16 0x7800 -#define LCD_F_CLOCKDIVIDER_17 0x8000 -#define LCD_F_CLOCKDIVIDER_18 0x8800 -#define LCD_F_CLOCKDIVIDER_19 0x9000 -#define LCD_F_CLOCKDIVIDER_20 0x9800 -#define LCD_F_CLOCKDIVIDER_21 0xa000 -#define LCD_F_CLOCKDIVIDER_22 0xa800 -#define LCD_F_CLOCKDIVIDER_23 0xb000 -#define LCD_F_CLOCKDIVIDER_24 0xb800 -#define LCD_F_CLOCKDIVIDER_25 0xc000 -#define LCD_F_CLOCKDIVIDER_26 0xc800 -#define LCD_F_CLOCKDIVIDER_27 0xd000 -#define LCD_F_CLOCKDIVIDER_28 0xd800 -#define LCD_F_CLOCKDIVIDER_29 0xe000 -#define LCD_F_CLOCKDIVIDER_30 0xe800 -#define LCD_F_CLOCKDIVIDER_31 0xf000 -#define LCD_F_CLOCKDIVIDER_32 0xf800 - -//***************************************************************************** -// -// The following are values that can be passed to the initParams parameter for -// functions: LCD_F_initModule(). -// -//***************************************************************************** -#define LCD_F_CLOCKPRESCALER_1 (LCD_F_CTL_PRE_0) -#define LCD_F_CLOCKPRESCALER_2 (LCD_F_CTL_PRE_1) -#define LCD_F_CLOCKPRESCALER_4 (LCD_F_CTL_PRE_2) -#define LCD_F_CLOCKPRESCALER_8 (LCD_F_CTL_PRE_3) -#define LCD_F_CLOCKPRESCALER_16 (LCD_F_CTL_PRE_4) -#define LCD_F_CLOCKPRESCALER_32 (LCD_F_CTL_PRE_5) - -//***************************************************************************** -// -// The following are values that can be passed to the initParams parameter for -// functions: LCD_F_initModule(). -// -//***************************************************************************** -#define LCD_F_STATIC (LCD_F_CTL_MX_0) -#define LCD_F_2_MUX (LCD_F_CTL_MX_1) -#define LCD_F_3_MUX (LCD_F_CTL_MX_2) -#define LCD_F_4_MUX (LCD_F_CTL_MX_3) -#define LCD_F_5_MUX (LCD_F_CTL_MX_4) -#define LCD_F_6_MUX (LCD_F_CTL_MX_5) -#define LCD_F_7_MUX (LCD_F_CTL_MX_6) -#define LCD_F_8_MUX (LCD_F_CTL_MX_7) - -//***************************************************************************** -// -// The following are values that can be passed to the v2v3v4Source parameter -// for functions: LCD_F_setVLCDSource(). -// -//***************************************************************************** -#define LCD_F_V2V3V4_GENERATED_INTERNALLY_NOT_SWITCHED_TO_PINS (0x0) -#define LCD_F_V2V3V4_GENERATED_INTERNALLY_SWITCHED_TO_PINS (LCD_F_VCTL_REXT) -#define LCD_F_V2V3V4_SOURCED_EXTERNALLY (LCD_F_VCTL_EXTBIAS) - -//***************************************************************************** -// -// The following are values that can be passed to the v5Source parameter for -// functions: LCD_F_setVLCDSource(). -// -//***************************************************************************** -#define LCD_F_V5_VSS (0x0) -#define LCD_F_V5_SOURCED_FROM_R03 (LCD_F_VCTL_R03EXT) - -//***************************************************************************** -// -// The following are values that can be passed to the initParams parameter for -// functions: LCD_F_initModule(). -// -//***************************************************************************** -#define LCD_F_STANDARD_WAVEFORMS (0x0) -#define LCD_F_LOW_POWER_WAVEFORMS (LCD_F_CTL_LP) - -//***************************************************************************** -// -// The following are values that can be passed to the initParams parameter for -// functions: LCD_F_initModule(). -// -//***************************************************************************** -#define LCD_F_SEGMENTS_DISABLED (0x0) -#define LCD_F_SEGMENTS_ENABLED (LCD_F_CTL_SON) - -//***************************************************************************** -// -// The following are values that can be passed to the mask parameter for -// functions: LCD_F_clearInterrupt(), LCD_F_getInterruptStatus(), -// LCD_F_enableInterrupt(), and LCD_F_disableInterrupt() as well as returned by -// the LCD_F_getInterruptStatus() function. -// -//***************************************************************************** -#define LCD_F_BLINKING_SEGMENTS_ON_INTERRUPT (LCD_F_IE_BLKONIE) -#define LCD_F_BLINKING_SEGMENTS_OFF_INTERRUPT (LCD_F_IE_BLKOFFIE) -#define LCD_F_FRAME_INTERRUPT (LCD_F_IE_FRMIE) -#define LCD_F_ANIMATION_LOOP_INTERRUPT (LCD_F_IE_ANMLOOPIE) -#define LCD_F_ANIMATION_STEP_INTERRUPT (LCD_F_IE_ANMSTPIE) - -//***************************************************************************** -// -// The following are values that can be passed to the displayMemory parameter -// for functions: LCD_F_selectDisplayMemory(). -// -//***************************************************************************** -#define LCD_F_DISPLAYSOURCE_MEMORY (0x0) -#define LCD_F_DISPLAYSOURCE_BLINKINGMEMORY (0x1) - -//***************************************************************************** -// -// The following are values that can be passed to the clockPrescalar parameter -// for functions: LCD_F_setBlinkingControl(). -// -//***************************************************************************** -#define LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_512 LCD_F_BMCTL_BLKPRE_0 -#define LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_1024 LCD_F_BMCTL_BLKPRE_1 -#define LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_2048 LCD_F_BMCTL_BLKPRE_2 -#define LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_4096 LCD_F_BMCTL_BLKPRE_3 -#define LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_8162 LCD_F_BMCTL_BLKPRE_4 -#define LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_16384 LCD_F_BMCTL_BLKPRE_5 -#define LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_32768 LCD_F_BMCTL_BLKPRE_6 -#define LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_65536 LCD_F_BMCTL_BLKPRE_7 - -//***************************************************************************** -// -// The following are values that can be passed to the clockPrescalar parameter -// for functions: LCD_F_setBlinkingControl(). -// -//***************************************************************************** -#define LCD_F_BLINK_FREQ_CLOCK_DIVIDER_1 LCD_F_BMCTL_BLKDIV_0 -#define LCD_F_BLINK_FREQ_CLOCK_DIVIDER_2 LCD_F_BMCTL_BLKDIV_1 -#define LCD_F_BLINK_FREQ_CLOCK_DIVIDER_3 LCD_F_BMCTL_BLKDIV_2 -#define LCD_F_BLINK_FREQ_CLOCK_DIVIDER_4 LCD_F_BMCTL_BLKDIV_3 -#define LCD_F_BLINK_FREQ_CLOCK_DIVIDER_5 LCD_F_BMCTL_BLKDIV_4 -#define LCD_F_BLINK_FREQ_CLOCK_DIVIDER_6 LCD_F_BMCTL_BLKDIV_5 -#define LCD_F_BLINK_FREQ_CLOCK_DIVIDER_7 LCD_F_BMCTL_BLKDIV_6 -#define LCD_F_BLINK_FREQ_CLOCK_DIVIDER_8 LCD_F_BMCTL_BLKDIV_7 - -//***************************************************************************** -// -// The following are values that can be passed to the mode parameter for -// functions: LCD_F_setBlinkingControl(). -// -//***************************************************************************** -#define LCD_F_BLINK_MODE_DISABLED (LCD_F_BMCTL_BLKMOD_0) -#define LCD_F_BLINK_MODE_INDIVIDUAL_SEGMENTS (LCD_F_BMCTL_BLKMOD_1) -#define LCD_F_BLINK_MODE_ALL_SEGMENTS (LCD_F_BMCTL_BLKMOD_2) -#define LCD_F_BLINK_MODE_SWITCHING_BETWEEN_DISPLAY_CONTENTS \ - (LCD_F_BMCTL_BLKMOD_3) - -//***************************************************************************** -// -// The following are values that can be passed to the clockPrescalar parameter -// for functions: LCD_F_setAnimationControl(). -// -//***************************************************************************** -#define LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_512 LCD_F_ANMCTL_ANMPRE_0 -#define LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_1024 LCD_F_ANMCTL_ANMPRE_1 -#define LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_2048 LCD_F_ANMCTL_ANMPRE_2 -#define LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_4096 LCD_F_ANMCTL_ANMPRE_3 -#define LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_8162 LCD_F_ANMCTL_ANMPRE_4 -#define LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_16384 LCD_F_ANMCTL_ANMPRE_5 -#define LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_32768 LCD_F_ANMCTL_ANMPRE_6 -#define LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_65536 LCD_F_ANMCTL_ANMPRE_7 - -//***************************************************************************** -// -// The following are values that can be passed to the clockPrescalar parameter -// for functions: LCD_F_setAnimationControl(). -// -//***************************************************************************** -#define LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_1 LCD_F_ANMCTL_ANMDIV_0 -#define LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_2 LCD_F_ANMCTL_ANMDIV_1 -#define LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_3 LCD_F_ANMCTL_ANMDIV_2 -#define LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_4 LCD_F_ANMCTL_ANMDIV_3 -#define LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_5 LCD_F_ANMCTL_ANMDIV_4 -#define LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_6 LCD_F_ANMCTL_ANMDIV_5 -#define LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_7 LCD_F_ANMCTL_ANMDIV_6 -#define LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_8 LCD_F_ANMCTL_ANMDIV_7 - -//***************************************************************************** -// -// The following are values that can be passed to the mode parameter for -// functions: LCD_F_setAnimationControl(). -// -//***************************************************************************** -#define LCD_F_ANIMATION_FRAMES_T0_TO_T7 LCD_F_ANMCTL_ANMSTP_7 -#define LCD_F_ANIMATION_FRAMES_T0_TO_T6 LCD_F_ANMCTL_ANMSTP_6 -#define LCD_F_ANIMATION_FRAMES_T0_TO_T5 LCD_F_ANMCTL_ANMSTP_5 -#define LCD_F_ANIMATION_FRAMES_T0_TO_T4 LCD_F_ANMCTL_ANMSTP_4 -#define LCD_F_ANIMATION_FRAMES_T0_TO_T3 LCD_F_ANMCTL_ANMSTP_3 -#define LCD_F_ANIMATION_FRAMES_T0_TO_T2 LCD_F_ANMCTL_ANMSTP_2 -#define LCD_F_ANIMATION_FRAMES_T0_TO_T1 LCD_F_ANMCTL_ANMSTP_1 -#define LCD_F_ANIMATION_FRAMES_T0 LCD_F_ANMCTL_ANMSTP_0 - -//***************************************************************************** -// -// The following are values that can be passed to the startPin parameter for -// functions: LCD_F_setPinsAsLCDFunction(); the endPin parameter for -// functions: LCD_F_setPinsAsLCDFunction(); the pin parameter for functions: -// LCD_F_setPinAsLCDFunction(), LCD_F_setPinAsPortFunction(), -// LCD_F_setPinAsCOM(), and LCD_F_setPinAsSEG(). -// -//***************************************************************************** -#define LCD_F_SEGMENT_LINE_0 (0) -#define LCD_F_SEGMENT_LINE_1 (1) -#define LCD_F_SEGMENT_LINE_2 (2) -#define LCD_F_SEGMENT_LINE_3 (3) -#define LCD_F_SEGMENT_LINE_4 (4) -#define LCD_F_SEGMENT_LINE_5 (5) -#define LCD_F_SEGMENT_LINE_6 (6) -#define LCD_F_SEGMENT_LINE_7 (7) -#define LCD_F_SEGMENT_LINE_8 (8) -#define LCD_F_SEGMENT_LINE_9 (9) -#define LCD_F_SEGMENT_LINE_10 (10) -#define LCD_F_SEGMENT_LINE_11 (11) -#define LCD_F_SEGMENT_LINE_12 (12) -#define LCD_F_SEGMENT_LINE_13 (13) -#define LCD_F_SEGMENT_LINE_14 (14) -#define LCD_F_SEGMENT_LINE_15 (15) -#define LCD_F_SEGMENT_LINE_16 (16) -#define LCD_F_SEGMENT_LINE_17 (17) -#define LCD_F_SEGMENT_LINE_18 (18) -#define LCD_F_SEGMENT_LINE_19 (19) -#define LCD_F_SEGMENT_LINE_20 (20) -#define LCD_F_SEGMENT_LINE_21 (21) -#define LCD_F_SEGMENT_LINE_22 (22) -#define LCD_F_SEGMENT_LINE_23 (23) -#define LCD_F_SEGMENT_LINE_24 (24) -#define LCD_F_SEGMENT_LINE_25 (25) -#define LCD_F_SEGMENT_LINE_26 (26) -#define LCD_F_SEGMENT_LINE_27 (27) -#define LCD_F_SEGMENT_LINE_28 (28) -#define LCD_F_SEGMENT_LINE_29 (29) -#define LCD_F_SEGMENT_LINE_30 (30) -#define LCD_F_SEGMENT_LINE_31 (31) -#define LCD_F_SEGMENT_LINE_32 (32) -#define LCD_F_SEGMENT_LINE_33 (33) -#define LCD_F_SEGMENT_LINE_34 (34) -#define LCD_F_SEGMENT_LINE_35 (35) -#define LCD_F_SEGMENT_LINE_36 (36) -#define LCD_F_SEGMENT_LINE_37 (37) -#define LCD_F_SEGMENT_LINE_38 (38) -#define LCD_F_SEGMENT_LINE_39 (39) -#define LCD_F_SEGMENT_LINE_40 (40) -#define LCD_F_SEGMENT_LINE_41 (41) -#define LCD_F_SEGMENT_LINE_42 (42) -#define LCD_F_SEGMENT_LINE_43 (43) -#define LCD_F_SEGMENT_LINE_44 (44) -#define LCD_F_SEGMENT_LINE_45 (45) -#define LCD_F_SEGMENT_LINE_46 (46) -#define LCD_F_SEGMENT_LINE_47 (47) - - -//***************************************************************************** -// -// The following are values that can be passed to the com parameter for -// functions: LCD_F_setPinAsCOM(). -// -//***************************************************************************** -#define LCD_F_MEMORY_COM0 (0x01) -#define LCD_F_MEMORY_COM1 (0x02) -#define LCD_F_MEMORY_COM2 (0x04) -#define LCD_F_MEMORY_COM3 (0x08) -#define LCD_F_MEMORY_COM4 (0x10) -#define LCD_F_MEMORY_COM5 (0x20) -#define LCD_F_MEMORY_COM6 (0x40) -#define LCD_F_MEMORY_COM7 (0x80) - -//***************************************************************************** -// -// The following are values that can be passed to the bias parameter for -// functions: LCD_F_selectBias(). -// -//***************************************************************************** -#define LCD_F_BIAS_1_3 (0x0) -#define LCD_F_BIAS_1_2 (LCD_F_VCTL_LCD2B) -#define LCD_F_BIAS_1_4 (LCD_F_VCTL_LCD2B) - -/* Internal Macros for indexing */ -#define OFS_LCDM0W 0x120 -#define OFS_LCDBM0W 0x160 - -//***************************************************************************** -// -//! \brief Initializes the LCD_F Module. -//! -//! This function initializes the LCD_F but without turning on. It bascially -//! setup the clock source, clock divider, mux rate, low-power waveform and -//! segments on/off. After calling this function, user can enable/disable -//! internal reference voltage or pin SEG/COM configurations. -//! -//! \param initParams is the pointer to LCD_F_Config structure. -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_initModule(LCD_F_Config *initParams); - -//***************************************************************************** -// -//! \brief Turns on the LCD_F module. -//! -//! This function turns the LCD_F on. -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_turnOn(void); - -//***************************************************************************** -// -//! \brief Turns the LCD_F off. -//! -//! This function turns the LCD_F off. -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_turnOff(void); - -/* Memory management functions */ - -//***************************************************************************** -// -//! \brief Clears all LCD_F memory registers. -//! -//! This function clears all LCD_F memory registers. -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_clearAllMemory(void); - -//***************************************************************************** -// -//! \brief Clears all LCD_F blinking memory registers. -//! -//! This function clears all LCD_F blinking memory registers. -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_clearAllBlinkingMemory(void); - -//***************************************************************************** -// -//! \brief Selects display memory. -//! -//! This function selects display memory either from memory or blinking memory. -//! Please note if the blinking mode is selected as -//! LCD_F_BLINKMODE_INDIVIDUALSEGMENTS or LCD_F_BLINKMODE_ALLSEGMENTS or mux -//! rate >=5, display memory can not be changed. If -//! LCD_F_BLINKMODE_SWITCHDISPLAYCONTENTS is selected, display memory bit -//! reflects current displayed memory. -//! -//! \param displayMemory is the desired displayed memory. -//! Valid values are: -//! - \b LCD_F_DISPLAYSOURCE_MEMORY [Default] -//! - \b LCD_F_DISPLAYSOURCE_BLINKINGMEMORY -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_selectDisplayMemory(uint_fast16_t displayMemory); - -//***************************************************************************** -// -//! \brief Sets the blinking control register. -//! -//! This function sets the blink control related parameter, including blink -//! clock frequency prescalar and blink mode. -//! -//! \param clockPrescalar is the clock pre-scalar for blinking frequency. -//! Valid values are: -//! - \b LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_512 [Default] -//! - \b LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_1024 -//! - \b LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_2048 -//! - \b LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_4096 -//! - \b LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_8162 -//! - \b LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_16384 -//! - \b LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_32768 -//! - \b LCD_F_BLINK_FREQ_CLOCK_PRESCALAR_65536 -//! \param clockDivider is the clock divider for blinking frequency. -//! Valid values are: -//! - \b LCD_F_BLINK_FREQ_CLOCK_DIVIDER_1 [Default] -//! - \b LCD_F_BLINK_FREQ_CLOCK_DIVIDER_2 -//! - \b LCD_F_BLINK_FREQ_CLOCK_DIVIDER_3 -//! - \b LCD_F_BLINK_FREQ_CLOCK_DIVIDER_4 -//! - \b LCD_F_BLINK_FREQ_CLOCK_DIVIDER_5 -//! - \b LCD_F_BLINK_FREQ_CLOCK_DIVIDER_6 -//! - \b LCD_F_BLINK_FREQ_CLOCK_DIVIDER_7 -//! - \b LCD_F_BLINK_FREQ_CLOCK_DIVIDER_8 -//! \param mode is the select for blinking mode. -//! Valid values are: -//! - \b LCD_F_BLINK_MODE_DISABLED [Default] -//! - \b LCD_F_BLINK_MODE_INDIVIDUAL_SEGMENTS -//! - \b LCD_F_BLINK_MODE_ALL_SEGMENTS -//! - \b LCD_F_BLINK_MODE_SWITCHING_BETWEEN_DISPLAY_CONTENTS -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_setBlinkingControl(uint_fast16_t clockPrescalar, - uint_fast16_t divider, uint_fast16_t mode); - -//***************************************************************************** -// -//! \brief Sets the animation control register. -//! -//! This function sets the animation control related parameter, including -//! animation clock frequency prescalar, divider, and frame settings -//! -//! \param clockPrescalar is the clock pre-scalar for animation frequency. -//! Valid values are: -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_512 [Default] -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_1024 -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_2048 -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_4096 -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_8162 -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_16384 -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_32768 -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_PRESCALAR_65536 -//! \param clockDivider is the clock divider for animation frequency. -//! Valid values are: -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_1 [Default] -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_2 -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_3 -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_4 -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_5 -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_6 -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_7 -//! - \b LCD_F_ANIMATION_FREQ_CLOCK_DIVIDER_8 -//! \param frames is number of animations frames to be repeated -//! Valid values are: -//! - \b LCD_F_ANIMATION_FRAMES_T0_TO_T7 -//! - \b LCD_F_ANIMATION_FRAMES_T0_TO_T6 -//! - \b LCD_F_ANIMATION_FRAMES_T0_TO_T5 -//! - \b LCD_F_ANIMATION_FRAMES_T0_TO_T4 -//! - \b LCD_F_ANIMATION_FRAMES_T0_TO_T3 -//! - \b LCD_F_ANIMATION_FRAMES_T0_TO_T2 -//! - \b LCD_F_ANIMATION_FRAMES_T0_TO_T1 -//! - \b LCD_F_ANIMATION_FRAMES_T0 -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_setAnimationControl(uint_fast16_t clockPrescalar, - uint_fast16_t divider, - uint_fast16_t frames); - -//***************************************************************************** -// -//! \brief Enables animation on the LCD_F controller -//! -//! This function turns on animation for the LCD_F controller. -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_enableAnimation(void); - - -//***************************************************************************** -// -//! \brief Enables animation on the LCD_F controller -//! -//! This function turns on animation for the LCD_F controller. -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_disableAnimation(void); - -//***************************************************************************** -// -//! \brief Clears all LCD_F animation memory registers. -//! -//! This function clears all LCD_F animation memory registers. -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_clearAllAnimationMemory(void); - -//***************************************************************************** -// -//! \brief Sets the LCD_F pins as LCD function pin. -//! -//! This function sets the LCD_F pins as LCD function pin. -//! -//! \param pin is the select pin set as LCD function. -//! Valid values are: -//! - \b LCD_F_SEGMENT_LINE_0 -//! - \b LCD_F_SEGMENT_LINE_1 -//! - \b LCD_F_SEGMENT_LINE_2 -//! - \b LCD_F_SEGMENT_LINE_3 -//! - \b LCD_F_SEGMENT_LINE_4 -//! - \b LCD_F_SEGMENT_LINE_5 -//! - \b LCD_F_SEGMENT_LINE_6 -//! - \b LCD_F_SEGMENT_LINE_7 -//! - \b LCD_F_SEGMENT_LINE_8 -//! - \b LCD_F_SEGMENT_LINE_9 -//! - \b LCD_F_SEGMENT_LINE_10 -//! - \b LCD_F_SEGMENT_LINE_11 -//! - \b LCD_F_SEGMENT_LINE_12 -//! - \b LCD_F_SEGMENT_LINE_13 -//! - \b LCD_F_SEGMENT_LINE_14 -//! - \b LCD_F_SEGMENT_LINE_15 -//! - \b LCD_F_SEGMENT_LINE_16 -//! - \b LCD_F_SEGMENT_LINE_17 -//! - \b LCD_F_SEGMENT_LINE_18 -//! - \b LCD_F_SEGMENT_LINE_19 -//! - \b LCD_F_SEGMENT_LINE_20 -//! - \b LCD_F_SEGMENT_LINE_21 -//! - \b LCD_F_SEGMENT_LINE_22 -//! - \b LCD_F_SEGMENT_LINE_23 -//! - \b LCD_F_SEGMENT_LINE_24 -//! - \b LCD_F_SEGMENT_LINE_25 -//! - \b LCD_F_SEGMENT_LINE_26 -//! - \b LCD_F_SEGMENT_LINE_27 -//! - \b LCD_F_SEGMENT_LINE_28 -//! - \b LCD_F_SEGMENT_LINE_29 -//! - \b LCD_F_SEGMENT_LINE_30 -//! - \b LCD_F_SEGMENT_LINE_31 -//! - \b LCD_F_SEGMENT_LINE_32 -//! - \b LCD_F_SEGMENT_LINE_33 -//! - \b LCD_F_SEGMENT_LINE_34 -//! - \b LCD_F_SEGMENT_LINE_35 -//! - \b LCD_F_SEGMENT_LINE_36 -//! - \b LCD_F_SEGMENT_LINE_37 -//! - \b LCD_F_SEGMENT_LINE_38 -//! - \b LCD_F_SEGMENT_LINE_39 -//! - \b LCD_F_SEGMENT_LINE_40 -//! - \b LCD_F_SEGMENT_LINE_41 -//! - \b LCD_F_SEGMENT_LINE_42 -//! - \b LCD_F_SEGMENT_LINE_43 -//! - \b LCD_F_SEGMENT_LINE_44 -//! - \b LCD_F_SEGMENT_LINE_45 -//! - \b LCD_F_SEGMENT_LINE_46 -//! - \b LCD_F_SEGMENT_LINE_47 -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_setPinAsLCDFunction(uint_fast8_t pin); - -//***************************************************************************** -// -//! \brief Sets the LCD_F pins as port function pin. -//! -//! \param baseAddress is the base address of the LCD_F module. -//! \param pin is the select pin set as Port function. -//! Valid values are: -//! - \b LCD_F_SEGMENT_LINE_0 -//! - \b LCD_F_SEGMENT_LINE_1 -//! - \b LCD_F_SEGMENT_LINE_2 -//! - \b LCD_F_SEGMENT_LINE_3 -//! - \b LCD_F_SEGMENT_LINE_4 -//! - \b LCD_F_SEGMENT_LINE_5 -//! - \b LCD_F_SEGMENT_LINE_6 -//! - \b LCD_F_SEGMENT_LINE_7 -//! - \b LCD_F_SEGMENT_LINE_8 -//! - \b LCD_F_SEGMENT_LINE_9 -//! - \b LCD_F_SEGMENT_LINE_10 -//! - \b LCD_F_SEGMENT_LINE_11 -//! - \b LCD_F_SEGMENT_LINE_12 -//! - \b LCD_F_SEGMENT_LINE_13 -//! - \b LCD_F_SEGMENT_LINE_14 -//! - \b LCD_F_SEGMENT_LINE_15 -//! - \b LCD_F_SEGMENT_LINE_16 -//! - \b LCD_F_SEGMENT_LINE_17 -//! - \b LCD_F_SEGMENT_LINE_18 -//! - \b LCD_F_SEGMENT_LINE_19 -//! - \b LCD_F_SEGMENT_LINE_20 -//! - \b LCD_F_SEGMENT_LINE_21 -//! - \b LCD_F_SEGMENT_LINE_22 -//! - \b LCD_F_SEGMENT_LINE_23 -//! - \b LCD_F_SEGMENT_LINE_24 -//! - \b LCD_F_SEGMENT_LINE_25 -//! - \b LCD_F_SEGMENT_LINE_26 -//! - \b LCD_F_SEGMENT_LINE_27 -//! - \b LCD_F_SEGMENT_LINE_28 -//! - \b LCD_F_SEGMENT_LINE_29 -//! - \b LCD_F_SEGMENT_LINE_30 -//! - \b LCD_F_SEGMENT_LINE_31 -//! - \b LCD_F_SEGMENT_LINE_32 -//! - \b LCD_F_SEGMENT_LINE_33 -//! - \b LCD_F_SEGMENT_LINE_34 -//! - \b LCD_F_SEGMENT_LINE_35 -//! - \b LCD_F_SEGMENT_LINE_36 -//! - \b LCD_F_SEGMENT_LINE_37 -//! - \b LCD_F_SEGMENT_LINE_38 -//! - \b LCD_F_SEGMENT_LINE_39 -//! - \b LCD_F_SEGMENT_LINE_40 -//! - \b LCD_F_SEGMENT_LINE_41 -//! - \b LCD_F_SEGMENT_LINE_42 -//! - \b LCD_F_SEGMENT_LINE_43 -//! - \b LCD_F_SEGMENT_LINE_44 -//! - \b LCD_F_SEGMENT_LINE_45 -//! - \b LCD_F_SEGMENT_LINE_46 -//! - \b LCD_F_SEGMENT_LINE_47 -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_setPinAsPortFunction(uint_fast8_t pin); - -//***************************************************************************** -// -//! \brief Sets the LCD_F pins as LCD function pin. -//! -//! This function sets the LCD_F pins as LCD function pin. Instead of passing -//! the all the possible pins, it just requires the start pin and the end pin. -//! -//! \param startPin is the starting pin to be configured as LCD function pin. -//! Valid values are: -//! - \b LCD_F_SEGMENT_LINE_0 -//! - \b LCD_F_SEGMENT_LINE_1 -//! - \b LCD_F_SEGMENT_LINE_2 -//! - \b LCD_F_SEGMENT_LINE_3 -//! - \b LCD_F_SEGMENT_LINE_4 -//! - \b LCD_F_SEGMENT_LINE_5 -//! - \b LCD_F_SEGMENT_LINE_6 -//! - \b LCD_F_SEGMENT_LINE_7 -//! - \b LCD_F_SEGMENT_LINE_8 -//! - \b LCD_F_SEGMENT_LINE_9 -//! - \b LCD_F_SEGMENT_LINE_10 -//! - \b LCD_F_SEGMENT_LINE_11 -//! - \b LCD_F_SEGMENT_LINE_12 -//! - \b LCD_F_SEGMENT_LINE_13 -//! - \b LCD_F_SEGMENT_LINE_14 -//! - \b LCD_F_SEGMENT_LINE_15 -//! - \b LCD_F_SEGMENT_LINE_16 -//! - \b LCD_F_SEGMENT_LINE_17 -//! - \b LCD_F_SEGMENT_LINE_18 -//! - \b LCD_F_SEGMENT_LINE_19 -//! - \b LCD_F_SEGMENT_LINE_20 -//! - \b LCD_F_SEGMENT_LINE_21 -//! - \b LCD_F_SEGMENT_LINE_22 -//! - \b LCD_F_SEGMENT_LINE_23 -//! - \b LCD_F_SEGMENT_LINE_24 -//! - \b LCD_F_SEGMENT_LINE_25 -//! - \b LCD_F_SEGMENT_LINE_26 -//! - \b LCD_F_SEGMENT_LINE_27 -//! - \b LCD_F_SEGMENT_LINE_28 -//! - \b LCD_F_SEGMENT_LINE_29 -//! - \b LCD_F_SEGMENT_LINE_30 -//! - \b LCD_F_SEGMENT_LINE_31 -//! - \b LCD_F_SEGMENT_LINE_32 -//! - \b LCD_F_SEGMENT_LINE_33 -//! - \b LCD_F_SEGMENT_LINE_34 -//! - \b LCD_F_SEGMENT_LINE_35 -//! - \b LCD_F_SEGMENT_LINE_36 -//! - \b LCD_F_SEGMENT_LINE_37 -//! - \b LCD_F_SEGMENT_LINE_38 -//! - \b LCD_F_SEGMENT_LINE_39 -//! - \b LCD_F_SEGMENT_LINE_40 -//! - \b LCD_F_SEGMENT_LINE_41 -//! - \b LCD_F_SEGMENT_LINE_42 -//! - \b LCD_F_SEGMENT_LINE_43 -//! - \b LCD_F_SEGMENT_LINE_44 -//! - \b LCD_F_SEGMENT_LINE_45 -//! - \b LCD_F_SEGMENT_LINE_46 -//! - \b LCD_F_SEGMENT_LINE_47 -//! \param endPin is the ending pin to be configured as LCD function pin. -//! Valid values are: -//! - \b LCD_F_SEGMENT_LINE_0 -//! - \b LCD_F_SEGMENT_LINE_1 -//! - \b LCD_F_SEGMENT_LINE_2 -//! - \b LCD_F_SEGMENT_LINE_3 -//! - \b LCD_F_SEGMENT_LINE_4 -//! - \b LCD_F_SEGMENT_LINE_5 -//! - \b LCD_F_SEGMENT_LINE_6 -//! - \b LCD_F_SEGMENT_LINE_7 -//! - \b LCD_F_SEGMENT_LINE_8 -//! - \b LCD_F_SEGMENT_LINE_9 -//! - \b LCD_F_SEGMENT_LINE_10 -//! - \b LCD_F_SEGMENT_LINE_11 -//! - \b LCD_F_SEGMENT_LINE_12 -//! - \b LCD_F_SEGMENT_LINE_13 -//! - \b LCD_F_SEGMENT_LINE_14 -//! - \b LCD_F_SEGMENT_LINE_15 -//! - \b LCD_F_SEGMENT_LINE_16 -//! - \b LCD_F_SEGMENT_LINE_17 -//! - \b LCD_F_SEGMENT_LINE_18 -//! - \b LCD_F_SEGMENT_LINE_19 -//! - \b LCD_F_SEGMENT_LINE_20 -//! - \b LCD_F_SEGMENT_LINE_21 -//! - \b LCD_F_SEGMENT_LINE_22 -//! - \b LCD_F_SEGMENT_LINE_23 -//! - \b LCD_F_SEGMENT_LINE_24 -//! - \b LCD_F_SEGMENT_LINE_25 -//! - \b LCD_F_SEGMENT_LINE_26 -//! - \b LCD_F_SEGMENT_LINE_27 -//! - \b LCD_F_SEGMENT_LINE_28 -//! - \b LCD_F_SEGMENT_LINE_29 -//! - \b LCD_F_SEGMENT_LINE_30 -//! - \b LCD_F_SEGMENT_LINE_31 -//! - \b LCD_F_SEGMENT_LINE_32 -//! - \b LCD_F_SEGMENT_LINE_33 -//! - \b LCD_F_SEGMENT_LINE_34 -//! - \b LCD_F_SEGMENT_LINE_35 -//! - \b LCD_F_SEGMENT_LINE_36 -//! - \b LCD_F_SEGMENT_LINE_37 -//! - \b LCD_F_SEGMENT_LINE_38 -//! - \b LCD_F_SEGMENT_LINE_39 -//! - \b LCD_F_SEGMENT_LINE_40 -//! - \b LCD_F_SEGMENT_LINE_41 -//! - \b LCD_F_SEGMENT_LINE_42 -//! - \b LCD_F_SEGMENT_LINE_43 -//! - \b LCD_F_SEGMENT_LINE_44 -//! - \b LCD_F_SEGMENT_LINE_45 -//! - \b LCD_F_SEGMENT_LINE_46 -//! - \b LCD_F_SEGMENT_LINE_47 -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_setPinsAsLCDFunction(uint_fast8_t startPin, uint8_t endPin); - -//***************************************************************************** -// -//! \brief Sets the LCD_F pin as a common line. -//! -//! This function sets the LCD_F pin as a common line and assigns the -//! corresponding memory pin to a specific COM line. -//! -//! \param pin is the selected pin to be configured as common line. -//! Valid values are: -//! - \b LCD_F_SEGMENT_LINE_0 -//! - \b LCD_F_SEGMENT_LINE_1 -//! - \b LCD_F_SEGMENT_LINE_2 -//! - \b LCD_F_SEGMENT_LINE_3 -//! - \b LCD_F_SEGMENT_LINE_4 -//! - \b LCD_F_SEGMENT_LINE_5 -//! - \b LCD_F_SEGMENT_LINE_6 -//! - \b LCD_F_SEGMENT_LINE_7 -//! - \b LCD_F_SEGMENT_LINE_8 -//! - \b LCD_F_SEGMENT_LINE_9 -//! - \b LCD_F_SEGMENT_LINE_10 -//! - \b LCD_F_SEGMENT_LINE_11 -//! - \b LCD_F_SEGMENT_LINE_12 -//! - \b LCD_F_SEGMENT_LINE_13 -//! - \b LCD_F_SEGMENT_LINE_14 -//! - \b LCD_F_SEGMENT_LINE_15 -//! - \b LCD_F_SEGMENT_LINE_16 -//! - \b LCD_F_SEGMENT_LINE_17 -//! - \b LCD_F_SEGMENT_LINE_18 -//! - \b LCD_F_SEGMENT_LINE_19 -//! - \b LCD_F_SEGMENT_LINE_20 -//! - \b LCD_F_SEGMENT_LINE_21 -//! - \b LCD_F_SEGMENT_LINE_22 -//! - \b LCD_F_SEGMENT_LINE_23 -//! - \b LCD_F_SEGMENT_LINE_24 -//! - \b LCD_F_SEGMENT_LINE_25 -//! - \b LCD_F_SEGMENT_LINE_26 -//! - \b LCD_F_SEGMENT_LINE_27 -//! - \b LCD_F_SEGMENT_LINE_28 -//! - \b LCD_F_SEGMENT_LINE_29 -//! - \b LCD_F_SEGMENT_LINE_30 -//! - \b LCD_F_SEGMENT_LINE_31 -//! - \b LCD_F_SEGMENT_LINE_32 -//! - \b LCD_F_SEGMENT_LINE_33 -//! - \b LCD_F_SEGMENT_LINE_34 -//! - \b LCD_F_SEGMENT_LINE_35 -//! - \b LCD_F_SEGMENT_LINE_36 -//! - \b LCD_F_SEGMENT_LINE_37 -//! - \b LCD_F_SEGMENT_LINE_38 -//! - \b LCD_F_SEGMENT_LINE_39 -//! - \b LCD_F_SEGMENT_LINE_40 -//! - \b LCD_F_SEGMENT_LINE_41 -//! - \b LCD_F_SEGMENT_LINE_42 -//! - \b LCD_F_SEGMENT_LINE_43 -//! - \b LCD_F_SEGMENT_LINE_44 -//! - \b LCD_F_SEGMENT_LINE_45 -//! - \b LCD_F_SEGMENT_LINE_46 -//! - \b LCD_F_SEGMENT_LINE_47 -//! \param com is the selected COM number for the common line. -//! Valid values are: -//! - \b LCD_F_MEMORY_COM0 -//! - \b LCD_F_MEMORY_COM1 -//! - \b LCD_F_MEMORY_COM2 -//! - \b LCD_F_MEMORY_COM3 -//! - \b LCD_F_MEMORY_COM4 - only for 5-Mux/6-Mux/7-Mux/8-Mux -//! - \b LCD_F_MEMORY_COM5 - only for 5-Mux/6-Mux/7-Mux/8-Mux -//! - \b LCD_F_MEMORY_COM6 - only for 5-Mux/6-Mux/7-Mux/8-Mux -//! - \b LCD_F_MEMORY_COM7 - only for 5-Mux/6-Mux/7-Mux/8-Mux -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_setPinAsCOM(uint8_t pin, uint_fast8_t com); - -//***************************************************************************** -// -//! \brief Sets the LCD_F pin as a segment line. -//! -//! This function sets the LCD_F pin as segment line. -//! -//! \param pin is the selected pin to be configed as segment line. -//! Valid values are: -//! - \b LCD_F_SEGMENT_LINE_0 -//! - \b LCD_F_SEGMENT_LINE_1 -//! - \b LCD_F_SEGMENT_LINE_2 -//! - \b LCD_F_SEGMENT_LINE_3 -//! - \b LCD_F_SEGMENT_LINE_4 -//! - \b LCD_F_SEGMENT_LINE_5 -//! - \b LCD_F_SEGMENT_LINE_6 -//! - \b LCD_F_SEGMENT_LINE_7 -//! - \b LCD_F_SEGMENT_LINE_8 -//! - \b LCD_F_SEGMENT_LINE_9 -//! - \b LCD_F_SEGMENT_LINE_10 -//! - \b LCD_F_SEGMENT_LINE_11 -//! - \b LCD_F_SEGMENT_LINE_12 -//! - \b LCD_F_SEGMENT_LINE_13 -//! - \b LCD_F_SEGMENT_LINE_14 -//! - \b LCD_F_SEGMENT_LINE_15 -//! - \b LCD_F_SEGMENT_LINE_16 -//! - \b LCD_F_SEGMENT_LINE_17 -//! - \b LCD_F_SEGMENT_LINE_18 -//! - \b LCD_F_SEGMENT_LINE_19 -//! - \b LCD_F_SEGMENT_LINE_20 -//! - \b LCD_F_SEGMENT_LINE_21 -//! - \b LCD_F_SEGMENT_LINE_22 -//! - \b LCD_F_SEGMENT_LINE_23 -//! - \b LCD_F_SEGMENT_LINE_24 -//! - \b LCD_F_SEGMENT_LINE_25 -//! - \b LCD_F_SEGMENT_LINE_26 -//! - \b LCD_F_SEGMENT_LINE_27 -//! - \b LCD_F_SEGMENT_LINE_28 -//! - \b LCD_F_SEGMENT_LINE_29 -//! - \b LCD_F_SEGMENT_LINE_30 -//! - \b LCD_F_SEGMENT_LINE_31 -//! - \b LCD_F_SEGMENT_LINE_32 -//! - \b LCD_F_SEGMENT_LINE_33 -//! - \b LCD_F_SEGMENT_LINE_34 -//! - \b LCD_F_SEGMENT_LINE_35 -//! - \b LCD_F_SEGMENT_LINE_36 -//! - \b LCD_F_SEGMENT_LINE_37 -//! - \b LCD_F_SEGMENT_LINE_38 -//! - \b LCD_F_SEGMENT_LINE_39 -//! - \b LCD_F_SEGMENT_LINE_40 -//! - \b LCD_F_SEGMENT_LINE_41 -//! - \b LCD_F_SEGMENT_LINE_42 -//! - \b LCD_F_SEGMENT_LINE_43 -//! - \b LCD_F_SEGMENT_LINE_44 -//! - \b LCD_F_SEGMENT_LINE_45 -//! - \b LCD_F_SEGMENT_LINE_46 -//! - \b LCD_F_SEGMENT_LINE_47 -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_setPinAsSEG(uint_fast8_t pin); - -//***************************************************************************** -// -//! \brief Selects the bias level. -//! -//! \param bias is the select for bias level. -//! Valid values are: -//! - \b LCD_F_BIAS_1_3 [Default] - 1/3 bias -//! - \b LCD_F_BIAS_1_4 - 1/4 bias -//! - \b LCD_F_BIAS_1_2 - 1/2 bias -//! -//! \note Quarter (1/4) BIAS mode is only available in 5-mux to 8-mux. In -//! 2-mux to 4-mux modes, this value will result in a third BIAS (1/3) -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_selectBias(uint_fast16_t bias); - -//***************************************************************************** -// -//! \brief Sets the voltage source for V2/V3/V4 and V5. -//! -//! \param v2v3v4Source is the V2/V3/V4 source select. -//! Valid values are: -//! - \b LCD_F_V2V3V4_GENERATED_INTERNALLY_NOT_SWITCHED_TO_PINS -//! [Default] -//! - \b LCD_F_V2V3V4_GENERATED_INTERNALLY_SWITCHED_TO_PINS -//! - \b LCD_F_V2V3V4_SOURCED_EXTERNALLY -//! \param v5Source is the V5 source select. -//! Valid values are: -//! - \b LCD_F_V5_VSS [Default] -//! - \b LCD_F_V5_SOURCED_FROM_R03 -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_setVLCDSource(uint_fast16_t v2v3v4Source, - uint_fast16_t v5Source); - -//***************************************************************************** -// -//! \brief Clears the LCD_F selected interrupt flags. -//! -//! This function clears the specified interrupt flags. -//! -//! \param mask is the masked interrupt flag to be cleared. -//! Mask value is the logical OR of any of the following: -//! - \b LCD_F_BLINKING_SEGMENTS_ON_INTERRUPT -//! - \b LCD_F_BLINKING_SEGMENTS_OFF_INTERRUPT -//! - \b LCD_F_FRAME_INTERRUPT -//! - \b LCD_F_ANIMATION_LOOP_INTERRUPT -//! - \b LCD_F_ANIMATION_STEP_INTERRUPT -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_clearInterrupt(uint32_t mask); - -//***************************************************************************** -// -//! \brief Returns the status of the selected interrupt flags. -//! -//! This function returns the status of the selected interrupt flags. -//! -//! \return The current interrupt flag status. Can be a logical OR of: -//! - \b LCD_F_BLINKING_SEGMENTS_ON_INTERRUPT -//! - \b LCD_F_BLINKING_SEGMENTS_OFF_INTERRUPT -//! - \b LCD_F_FRAME_INTERRUPT -//! - \b LCD_F_ANIMATION_LOOP_INTERRUPT -//! - \b LCD_F_ANIMATION_STEP_INTERRUPT -// -//***************************************************************************** -extern uint32_t LCD_F_getInterruptStatus(void); - -//***************************************************************************** -// -//! \brief Returns the status of the selected interrupt flags masked with the -//! currently enabled interrupts. -//! -//! \return The current interrupt flag status. Can be a logical OR of: -//! - \b LCD_F_BLINKING_SEGMENTS_ON_INTERRUPT -//! - \b LCD_F_BLINKING_SEGMENTS_OFF_INTERRUPT -//! - \b LCD_F_FRAME_INTERRUPT -//! - \b LCD_F_ANIMATION_LOOP_INTERRUPT -//! - \b LCD_F_ANIMATION_STEP_INTERRUPT -// -//***************************************************************************** -extern uint32_t LCD_F_getEnabledInterruptStatus(void); - -//***************************************************************************** -// -//! \brief Enables the LCD_F selected interrupts -//! -//! This function enables the specified interrupts -//! -//! \param mask is the variable containing interrupt flags to be enabled. -//! Mask value is the logical OR of any of the following: -//! - \b LCD_F_BLINKING_SEGMENTS_ON_INTERRUPT -//! - \b LCD_F_BLINKING_SEGMENTS_OFF_INTERRUPT -//! - \b LCD_F_FRAME_INTERRUPT -//! - \b LCD_F_ANIMATION_LOOP_INTERRUPT -//! - \b LCD_F_ANIMATION_STEP_INTERRUPT -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_enableInterrupt(uint32_t mask); - -//***************************************************************************** -// -//! \brief Disables the LCD_F selected interrupts. -//! -//! This function disables the specified interrupts. -//! -//! \param mask is the variable containing interrupt flags to be disabled -//! Mask value is the logical OR of any of the following: -//! - \b LCD_F_BLINKING_SEGMENTS_ON_INTERRUPT -//! - \b LCD_F_BLINKING_SEGMENTS_OFF_INTERRUPT -//! - \b LCD_F_FRAME_INTERRUPT -//! - \b LCD_F_ANIMATION_LOOP_INTERRUPT -//! - \b LCD_F_ANIMATION_STEP_INTERRUPT -//! -//! \return None -// -//***************************************************************************** -extern void LCD_F_disableInterrupt(uint32_t mask); - -//***************************************************************************** -// -//! Registers an interrupt handler for LCD_F interrupt. -//! -//! \param intHandler is a pointer to the function to be called when the -//! LCD_F interrupt occurs. -//! -//! This function registers the handler to be called when a LCD_F -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific LCD_F interrupts must be enabled -//! via LCD_F_enableInterrupt(). It is the interrupt handler's responsibility -//! to clear the interrupt source through LCD_F_clearInterruptFlag(). -//! -//! \return None. -// -//***************************************************************************** -extern void LCD_F_registerInterrupt(void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the LCD_F interrupt -//! -//! This function unregisters the handler to be called when LCD_F -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void LCD_F_unregisterInterrupt(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* __MCU_HAS_LCD_F__ */ - -#endif /* LCD_F_H_ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/mpu.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/mpu.c deleted file mode 100644 index 20f20eb0e18..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/mpu.c +++ /dev/null @@ -1,189 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include - -void MPU_enableModule(uint32_t mpuConfig) -{ - // - // Check the arguments. - // - ASSERT(!(mpuConfig & ~(MPU_CONFIG_PRIV_DEFAULT | MPU_CONFIG_HARDFLT_NMI))); - - // - // Set the MPU control bits according to the flags passed by the user, - // and also set the enable bit. - // - MPU->CTRL = mpuConfig | MPU_CTRL_ENABLE_Msk; -} - -void MPU_disableModule(void) -{ - // - // Turn off the MPU enable bit. - // - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - -} - -uint32_t MPU_getRegionCount(void) -{ - // - // Read the DREGION field of the MPU type register and mask off - // the bits of interest to get the count of regions. - // - return ((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> NVIC_MPU_TYPE_DREGION_S); -} - -void MPU_enableRegion(uint32_t region) -{ - // - // Check the arguments. - // - ASSERT(region < 8); - - // - // Select the region to modify. - // - MPU->RNR = region; - - // - // Modify the enable bit in the region attributes. - // - MPU->RASR |= MPU_RASR_ENABLE_Msk; -} - -void MPU_disableRegion(uint32_t region) -{ - // - // Check the arguments. - // - ASSERT(region < 8); - - // - // Select the region to modify. - // - MPU->RNR = region; - - // - // Modify the enable bit in the region attributes. - // - MPU->RASR &= ~MPU_RASR_ENABLE_Msk; -} - -void MPU_setRegion(uint32_t region, uint32_t addr, uint32_t flags) -{ - // - // Check the arguments. - // - ASSERT(region < 8); - - // - // Program the base address, use the region field to select the - // region at the same time. - // - MPU->RBAR = addr | region | MPU_RBAR_VALID_Msk; - - // - // Program the region attributes. Set the TEX field and the S, C, - // and B bits to fixed values that are suitable for all Stellaris - // memory. - // - MPU->RASR = (flags & ~(MPU_RASR_TEX_Msk | MPU_RASR_C_Msk)) | MPU_RASR_S_Msk - | MPU_RASR_B_Msk; -} - -void MPU_getRegion(uint32_t region, uint32_t *addr, uint32_t *pflags) -{ - // - // Check the arguments. - // - ASSERT(region < 8); - ASSERT(addr); - ASSERT(pflags); - - // - // Select the region to get. - // - MPU->RNR = region; - - // - // Read and store the base address for the region. - // - *addr = MPU->RBAR & MPU_RBAR_ADDR_Msk; - - // - // Read and store the region attributes. - // - *pflags = MPU->RASR; -} - -void MPU_registerInterrupt(void (*intHandler)(void)) -{ - // - // Check the arguments. - // - ASSERT(intHandler); - - // - // Register the interrupt handler. - // - Interrupt_registerInterrupt(FAULT_MPU, intHandler); - -} - -void MPU_unregisterInterrupt(void) -{ - // - // Unregister the interrupt handler. - // - Interrupt_unregisterInterrupt(FAULT_MPU); -} - -void MPU_enableInterrupt(void) -{ - - // - // Enable the memory management fault. - // - Interrupt_enableInterrupt(FAULT_MPU); - -} - -void MPU_disableInterrupt(void) -{ - // - // Disable the interrupt. - // - Interrupt_disableInterrupt(FAULT_MPU); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/mpu.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/mpu.h deleted file mode 100644 index 9380af85f61..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/mpu.h +++ /dev/null @@ -1,444 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __MPU_H__ -#define __MPU_H__ - -//***************************************************************************** -// -//! \addtogroup mpu_api -//! @{ -// -//***************************************************************************** - - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -//***************************************************************************** -// -// Flags that can be passed to MPU_enableModule. -// -//***************************************************************************** -#define MPU_CONFIG_PRIV_DEFAULT MPU_CTRL_PRIVDEFENA_Msk -#define MPU_CONFIG_HARDFLT_NMI MPU_CTRL_HFNMIENA_Msk -#define MPU_CONFIG_NONE 0 - -//***************************************************************************** -// -// Flags for the region size to be passed to MPU_setRegion. -// -//***************************************************************************** -#define MPU_RGN_SIZE_32B (4 << 1) -#define MPU_RGN_SIZE_64B (5 << 1) -#define MPU_RGN_SIZE_128B (6 << 1) -#define MPU_RGN_SIZE_256B (7 << 1) -#define MPU_RGN_SIZE_512B (8 << 1) - -#define MPU_RGN_SIZE_1K (9 << 1) -#define MPU_RGN_SIZE_2K (10 << 1) -#define MPU_RGN_SIZE_4K (11 << 1) -#define MPU_RGN_SIZE_8K (12 << 1) -#define MPU_RGN_SIZE_16K (13 << 1) -#define MPU_RGN_SIZE_32K (14 << 1) -#define MPU_RGN_SIZE_64K (15 << 1) -#define MPU_RGN_SIZE_128K (16 << 1) -#define MPU_RGN_SIZE_256K (17 << 1) -#define MPU_RGN_SIZE_512K (18 << 1) - -#define MPU_RGN_SIZE_1M (19 << 1) -#define MPU_RGN_SIZE_2M (20 << 1) -#define MPU_RGN_SIZE_4M (21 << 1) -#define MPU_RGN_SIZE_8M (22 << 1) -#define MPU_RGN_SIZE_16M (23 << 1) -#define MPU_RGN_SIZE_32M (24 << 1) -#define MPU_RGN_SIZE_64M (25 << 1) -#define MPU_RGN_SIZE_128M (26 << 1) -#define MPU_RGN_SIZE_256M (27 << 1) -#define MPU_RGN_SIZE_512M (28 << 1) - -#define MPU_RGN_SIZE_1G (29 << 1) -#define MPU_RGN_SIZE_2G (30 << 1) -#define MPU_RGN_SIZE_4G (31 << 1) - -//***************************************************************************** -// -// Flags for the permissions to be passed to MPU_setRegion. -// -//***************************************************************************** -#define MPU_RGN_PERM_EXEC 0x00000000 -#define MPU_RGN_PERM_NOEXEC 0x10000000 -#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000 -#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000 -#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000 -#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000 -#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000 -#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000 - -//***************************************************************************** -// -// Flags for the sub-region to be passed to MPU_setRegion. -// -//***************************************************************************** -#define MPU_SUB_RGN_DISABLE_0 0x00000100 -#define MPU_SUB_RGN_DISABLE_1 0x00000200 -#define MPU_SUB_RGN_DISABLE_2 0x00000400 -#define MPU_SUB_RGN_DISABLE_3 0x00000800 -#define MPU_SUB_RGN_DISABLE_4 0x00001000 -#define MPU_SUB_RGN_DISABLE_5 0x00002000 -#define MPU_SUB_RGN_DISABLE_6 0x00004000 -#define MPU_SUB_RGN_DISABLE_7 0x00008000 - -//***************************************************************************** -// -// Flags to enable or disable a region, to be passed to MPU_setRegion. -// -//***************************************************************************** -#define MPU_RGN_ENABLE 1 -#define MPU_RGN_DISABLE 0 - -#define NVIC_MPU_TYPE_DREGION_S 8 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! Enables and configures the MPU for use. -//! -//! \param mpuConfig is the logical OR of the possible configurations. -//! -//! This function enables the Cortex-M memory protection unit. It also -//! configures the default behavior when in privileged mode and while handling -//! a hard fault or NMI. Prior to enabling the MPU, at least one region must -//! be set by calling MPU_setRegion() or else by enabling the default region for -//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to -//! MPU_enableModule(). Once the MPU is enabled, a memory management fault is -//! generated for memory access violations. -//! -//! The \e mpuConfig parameter should be the logical OR of any of the -//! following: -//! -//! - \b MPU_CONFIG_PRIV_DEFAULT enables the default memory map when in -//! privileged mode and when no other regions are defined. If this option -//! is not enabled, then there must be at least one valid region already -//! defined when the MPU is enabled. -//! - \b MPU_CONFIG_HARDFLT_NMI enables the MPU while in a hard fault or NMI -//! exception handler. If this option is not enabled, then the MPU is -//! disabled while in one of these exception handlers and the default -//! memory map is applied. -//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case, -//! no default memory map is provided in privileged mode, and the MPU is -//! not enabled in the fault handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void MPU_enableModule(uint32_t mpuConfig); - -//***************************************************************************** -// -//! Disables the MPU for use. -//! -//! This function disables the Cortex-M memory protection unit. When the -//! MPU is disabled, the default memory map is used and memory management -//! faults are not generated. -//! -//! \return None. -// -//***************************************************************************** -extern void MPU_disableModule(void); - -//***************************************************************************** -// -//! Gets the count of regions supported by the MPU. -//! -//! This function is used to get the total number of regions that are supported -//! by the MPU, including regions that are already programmed. -//! -//! \return The number of memory protection regions that are available -//! for programming using MPU_setRegion(). -// -//***************************************************************************** -extern uint32_t MPU_getRegionCount(void); - -//***************************************************************************** -// -//! Enables a specific region. -//! -//! \param region is the region number to enable. Valid values are between -//! 0 and 7 inclusively. -//! -//! This function is used to enable a memory protection region. The region -//! should already be configured with the MPU_setRegion() function. Once -//! enabled, the memory protection rules of the region are applied and access -//! violations cause a memory management fault. -//! -//! \return None. -// -//***************************************************************************** -extern void MPU_enableRegion(uint32_t region); - -//***************************************************************************** -// -//! Disables a specific region. -//! -//! \param region is the region number to disable. Valid values are between -//! 0 and 7 inclusively. -//! -//! This function is used to disable a previously enabled memory protection -//! region. The region remains configured if it is not overwritten with -//! another call to MPU_setRegion(), and can be enabled again by calling -//! MPU_enableRegion(). -//! -//! \return None. -// -//***************************************************************************** -extern void MPU_disableRegion(uint32_t region); - -//***************************************************************************** -// -//! Sets up the access rules for a specific region. -//! -//! \param region is the region number to set up. -//! \param addr is the base address of the region. It must be aligned -//! according to the size of the region specified in flags. -//! \param flags is a set of flags to define the attributes of the region. -//! -//! This function sets up the protection rules for a region. The region has -//! a base address and a set of attributes including the size. The base -//! address parameter, \e addr, must be aligned according to the size, and -//! the size must be a power of 2. -//! -//! \param region is the region number to set. Valid values are between -//! 0 and 7 inclusively. -//! -//! The \e flags parameter is the logical OR of all of the attributes -//! of the region. It is a combination of choices for region size, -//! execute permission, read/write permissions, disabled sub-regions, -//! and a flag to determine if the region is enabled. -//! -//! The size flag determines the size of a region and must be one of the -//! following: -//! -//! - \b MPU_RGN_SIZE_32B -//! - \b MPU_RGN_SIZE_64B -//! - \b MPU_RGN_SIZE_128B -//! - \b MPU_RGN_SIZE_256B -//! - \b MPU_RGN_SIZE_512B -//! - \b MPU_RGN_SIZE_1K -//! - \b MPU_RGN_SIZE_2K -//! - \b MPU_RGN_SIZE_4K -//! - \b MPU_RGN_SIZE_8K -//! - \b MPU_RGN_SIZE_16K -//! - \b MPU_RGN_SIZE_32K -//! - \b MPU_RGN_SIZE_64K -//! - \b MPU_RGN_SIZE_128K -//! - \b MPU_RGN_SIZE_256K -//! - \b MPU_RGN_SIZE_512K -//! - \b MPU_RGN_SIZE_1M -//! - \b MPU_RGN_SIZE_2M -//! - \b MPU_RGN_SIZE_4M -//! - \b MPU_RGN_SIZE_8M -//! - \b MPU_RGN_SIZE_16M -//! - \b MPU_RGN_SIZE_32M -//! - \b MPU_RGN_SIZE_64M -//! - \b MPU_RGN_SIZE_128M -//! - \b MPU_RGN_SIZE_256M -//! - \b MPU_RGN_SIZE_512M -//! - \b MPU_RGN_SIZE_1G -//! - \b MPU_RGN_SIZE_2G -//! - \b MPU_RGN_SIZE_4G -//! -//! The execute permission flag must be one of the following: -//! -//! - \b MPU_RGN_PERM_EXEC enables the region for execution of code -//! - \b MPU_RGN_PERM_NOEXEC disables the region for execution of code -//! -//! The read/write access permissions are applied separately for the -//! privileged and user modes. The read/write access flags must be one -//! of the following: -//! -//! - \b MPU_RGN_PERM_PRV_NO_USR_NO - no access in privileged or user mode -//! - \b MPU_RGN_PERM_PRV_RW_USR_NO - privileged read/write, user no access -//! - \b MPU_RGN_PERM_PRV_RW_USR_RO - privileged read/write, user read-only -//! - \b MPU_RGN_PERM_PRV_RW_USR_RW - privileged read/write, user read/write -//! - \b MPU_RGN_PERM_PRV_RO_USR_NO - privileged read-only, user no access -//! - \b MPU_RGN_PERM_PRV_RO_USR_RO - privileged read-only, user read-only -//! -//! The region is automatically divided into 8 equally-sized sub-regions by -//! the MPU. Sub-regions can only be used in regions of size 256 bytes -//! or larger. Any of these 8 sub-regions can be disabled, allowing for -//! creation of ``holes'' in a region which can be left open, or overlaid -//! by another region with different attributes. Any of the 8 sub-regions -//! can be disabled with a logical OR of any of the following flags: -//! -//! - \b MPU_SUB_RGN_DISABLE_0 -//! - \b MPU_SUB_RGN_DISABLE_1 -//! - \b MPU_SUB_RGN_DISABLE_2 -//! - \b MPU_SUB_RGN_DISABLE_3 -//! - \b MPU_SUB_RGN_DISABLE_4 -//! - \b MPU_SUB_RGN_DISABLE_5 -//! - \b MPU_SUB_RGN_DISABLE_6 -//! - \b MPU_SUB_RGN_DISABLE_7 -//! -//! Finally, the region can be initially enabled or disabled with one of -//! the following flags: -//! -//! - \b MPU_RGN_ENABLE -//! - \b MPU_RGN_DISABLE -//! -//! As an example, to set a region with the following attributes: size of -//! 32 KB, execution enabled, read-only for both privileged and user, one -//! sub-region disabled, and initially enabled; the \e flags parameter would -//! have the following value: -//! -//! -//! (MPU_RGN_SIZE_32K | MPU_RGN_PERM_EXEC | MPU_RGN_PERM_PRV_RO_USR_RO | -//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE) -//! -//! -//! \note This function writes to multiple registers and is not protected -//! from interrupts. It is possible that an interrupt which accesses a -//! region may occur while that region is in the process of being changed. -//! The safest way to handle this is to disable a region before changing it. -//! Refer to the discussion of this in the API Detailed Description section. -//! -//! \return None. -// -//***************************************************************************** -extern void MPU_setRegion(uint32_t region, uint32_t addr, uint32_t flags); - -//***************************************************************************** -// -//! Gets the current settings for a specific region. -//! -//! \param region is the region number to get. Valid values are between -//! 0 and 7 inclusively. -//! \param addr points to storage for the base address of the region. -//! \param pflags points to the attribute flags for the region. -//! -//! This function retrieves the configuration of a specific region. The -//! meanings and format of the parameters is the same as that of the -//! MPU_setRegion() function. -//! -//! This function can be used to save the configuration of a region for later -//! use with the MPU_setRegion() function. The region's enable state is -//! preserved in the attributes that are saved. -//! -//! \return None. -// -//***************************************************************************** -extern void MPU_getRegion(uint32_t region, uint32_t *addr, uint32_t *pflags); - -//***************************************************************************** -// -//! Registers an interrupt handler for the memory management fault. -//! -//! \param intHandler is a pointer to the function to be called when the -//! memory management fault occurs. -//! -//! This function sets and enables the handler to be called when the MPU -//! generates a memory management fault due to a protection region access -//! violation. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void MPU_registerInterrupt(void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the memory management fault. -//! -//! This function disables and clears the handler to be called when a -//! memory management fault occurs. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void MPU_unregisterInterrupt(void); - -//***************************************************************************** -// -//! Enables the interrupt for the memory management fault. -//! -//! \return None. -// -//***************************************************************************** -extern void MPU_enableInterrupt(void); - -//***************************************************************************** -// -//! Disables the interrupt for the memory management fault. -//! -//! \return None. -// -//***************************************************************************** -extern void MPU_disableInterrupt(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif // __MPU_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pcm.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pcm.c deleted file mode 100644 index 972f7326452..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pcm.c +++ /dev/null @@ -1,604 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/* Standard Includes */ -#include - -/* DriverLib Includes */ -#include -#include -#include -#include -#include -#include - -static bool __PCM_setCoreVoltageLevelAdvanced(uint_fast8_t voltageLevel, - uint32_t timeOut, bool blocking) -{ - uint8_t powerMode, bCurrentVoltageLevel; - uint32_t regValue; - bool boolTimeout; - - ASSERT(voltageLevel == PCM_VCORE0 || voltageLevel == PCM_VCORE1); - - /* Getting current power mode and level */ - powerMode = PCM_getPowerMode(); - bCurrentVoltageLevel = PCM_getCoreVoltageLevel(); - - boolTimeout = timeOut > 0 ? true : false; - - /* If we are already at the power mode they requested, return */ - if (bCurrentVoltageLevel == voltageLevel) - return true; - - while (bCurrentVoltageLevel != voltageLevel) - { - regValue = PCM->CTL0; - - switch (PCM_getPowerState()) - { - case PCM_AM_LF_VCORE1: - case PCM_AM_DCDC_VCORE1: - case PCM_AM_LDO_VCORE0: - PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE1) - | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK))); - break; - case PCM_AM_LF_VCORE0: - case PCM_AM_DCDC_VCORE0: - case PCM_AM_LDO_VCORE1: - PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE0) - | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK))); - break; - default: - ASSERT(false); - } - - if(blocking) - { - while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) - { - if (boolTimeout && !(--timeOut)) - return false; - - } - } - else - { - return true; - } - - bCurrentVoltageLevel = PCM_getCoreVoltageLevel(); - } - - /* Changing the power mode if we are stuck in LDO mode */ - if (powerMode != PCM_getPowerMode()) - { - if (powerMode == PCM_DCDC_MODE) - return PCM_setPowerMode(PCM_DCDC_MODE); - else - return PCM_setPowerMode(PCM_LF_MODE); - } - - return true; - -} - - -bool PCM_setCoreVoltageLevel(uint_fast8_t voltageLevel) -{ - return __PCM_setCoreVoltageLevelAdvanced(voltageLevel, 0, true); -} - -bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel, - uint32_t timeOut) -{ - return __PCM_setCoreVoltageLevelAdvanced(voltageLevel, timeOut, true); -} - -bool PCM_setCoreVoltageLevelNonBlocking(uint_fast8_t voltageLevel) -{ - return __PCM_setCoreVoltageLevelAdvanced(voltageLevel, 0, false); -} - -uint8_t PCM_getPowerMode(void) -{ - uint8_t currentPowerState; - - currentPowerState = PCM_getPowerState(); - - switch (currentPowerState) - { - case PCM_AM_LDO_VCORE0: - case PCM_AM_LDO_VCORE1: - case PCM_LPM0_LDO_VCORE0: - case PCM_LPM0_LDO_VCORE1: - return PCM_LDO_MODE; - case PCM_AM_DCDC_VCORE0: - case PCM_AM_DCDC_VCORE1: - case PCM_LPM0_DCDC_VCORE0: - case PCM_LPM0_DCDC_VCORE1: - return PCM_DCDC_MODE; - case PCM_LPM0_LF_VCORE0: - case PCM_LPM0_LF_VCORE1: - case PCM_AM_LF_VCORE1: - case PCM_AM_LF_VCORE0: - return PCM_LF_MODE; - default: - ASSERT(false); - return false; - - } -} - -uint8_t PCM_getCoreVoltageLevel(void) -{ - uint8_t currentPowerState = PCM_getPowerState(); - - switch (currentPowerState) - { - case PCM_AM_LDO_VCORE0: - case PCM_AM_DCDC_VCORE0: - case PCM_AM_LF_VCORE0: - case PCM_LPM0_LDO_VCORE0: - case PCM_LPM0_DCDC_VCORE0: - case PCM_LPM0_LF_VCORE0: - return PCM_VCORE0; - case PCM_AM_LDO_VCORE1: - case PCM_AM_DCDC_VCORE1: - case PCM_AM_LF_VCORE1: - case PCM_LPM0_LDO_VCORE1: - case PCM_LPM0_DCDC_VCORE1: - case PCM_LPM0_LF_VCORE1: - return PCM_VCORE1; - case PCM_LPM3: - return PCM_VCORELPM3; - default: - ASSERT(false); - return false; - - } -} - -static bool __PCM_setPowerModeAdvanced(uint_fast8_t powerMode, uint32_t timeOut, -bool blocking) -{ - uint8_t bCurrentPowerMode, bCurrentPowerState; - uint32_t regValue; - bool boolTimeout; - - ASSERT( - powerMode == PCM_LDO_MODE || powerMode == PCM_DCDC_MODE - || powerMode == PCM_LF_MODE); - - /* Getting Current Power Mode */ - bCurrentPowerMode = PCM_getPowerMode(); - - /* If the power mode being set it the same as the current mode, return */ - if (powerMode == bCurrentPowerMode) - return true; - - bCurrentPowerState = PCM_getPowerState(); - - boolTimeout = timeOut > 0 ? true : false; - - /* Go through the while loop while we haven't achieved the power mode */ - while (bCurrentPowerMode != powerMode) - { - regValue = PCM->CTL0; - - switch (bCurrentPowerState) - { - case PCM_AM_DCDC_VCORE0: - case PCM_AM_LF_VCORE0: - PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE0 - | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK))); - break; - case PCM_AM_LF_VCORE1: - case PCM_AM_DCDC_VCORE1: - PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE1 - | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK))); - break; - case PCM_AM_LDO_VCORE1: - { - if (powerMode == PCM_DCDC_MODE) - { - PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE1 - | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK))); - } else if (powerMode == PCM_LF_MODE) - { - PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE1 - | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK))); - } else - ASSERT(false); - - break; - } - case PCM_AM_LDO_VCORE0: - { - if (powerMode == PCM_DCDC_MODE) - { - PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE0 - | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK))); - } else if (powerMode == PCM_LF_MODE) - { - PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE0 - | (regValue & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK))); - } else - ASSERT(false); - - break; - } - default: - ASSERT(false); - } - - if (blocking) - { - while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) - { - if (boolTimeout && !(--timeOut)) - return false; - - } - } else - return true; - - bCurrentPowerMode = PCM_getPowerMode(); - bCurrentPowerState = PCM_getPowerState(); - } - - return true; - -} - -bool PCM_setPowerMode(uint_fast8_t powerMode) -{ - return __PCM_setPowerModeAdvanced(powerMode, 0, true); -} - -bool PCM_setPowerModeNonBlocking(uint_fast8_t powerMode) -{ - return __PCM_setPowerModeAdvanced(powerMode, 0, false); -} - -bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, uint32_t timeOut) -{ - return __PCM_setPowerModeAdvanced(powerMode, timeOut, true); -} - -static bool __PCM_setPowerStateAdvanced(uint_fast8_t powerState, - uint32_t timeout, - bool blocking) -{ - uint8_t bCurrentPowerState; - bCurrentPowerState = PCM_getPowerState(); - - ASSERT( - powerState == PCM_AM_LDO_VCORE0 || powerState == PCM_AM_LDO_VCORE1 - || powerState == PCM_AM_DCDC_VCORE0 || powerState == PCM_AM_DCDC_VCORE1 - || powerState == PCM_AM_LF_VCORE0 || powerState == PCM_AM_LF_VCORE1 - || powerState == PCM_LPM0_LDO_VCORE0 || powerState == PCM_LPM0_LDO_VCORE1 - || powerState == PCM_LPM0_DCDC_VCORE0 || powerState == PCM_LPM0_DCDC_VCORE1 - || powerState == PCM_LPM3 || powerState == PCM_LPM35_VCORE0 - || powerState == PCM_LPM45 || powerState == PCM_LPM4); - - if (bCurrentPowerState == powerState) - return true; - - switch (powerState) - { - case PCM_AM_LDO_VCORE0: - return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking) - && __PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking)); - case PCM_AM_LDO_VCORE1: - return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking) - && __PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking)); - case PCM_AM_DCDC_VCORE0: - return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking) - && __PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout, blocking)); - case PCM_AM_DCDC_VCORE1: - return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking) - && __PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout, blocking)); - case PCM_AM_LF_VCORE0: - return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking) - && __PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking)); - case PCM_AM_LF_VCORE1: - return (__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking) - && __PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking)); - case PCM_LPM0_LDO_VCORE0: - if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking) - || !__PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking)) - break; - return PCM_gotoLPM0(); - case PCM_LPM0_LDO_VCORE1: - if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking) - || !__PCM_setPowerModeAdvanced(PCM_LDO_MODE, timeout, blocking)) - break; - return PCM_gotoLPM0(); - case PCM_LPM0_DCDC_VCORE0: - if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking) - || !__PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout, - blocking)) - break; - return PCM_gotoLPM0(); - case PCM_LPM0_DCDC_VCORE1: - if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking) - || !__PCM_setPowerModeAdvanced(PCM_DCDC_MODE, timeout, - blocking)) - break; - return PCM_gotoLPM0(); - case PCM_LPM0_LF_VCORE0: - if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE0, timeout, blocking) - || !__PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking)) - break; - return PCM_gotoLPM0(); - case PCM_LPM0_LF_VCORE1: - if (!__PCM_setCoreVoltageLevelAdvanced(PCM_VCORE1, timeout, blocking) - || !__PCM_setPowerModeAdvanced(PCM_LF_MODE, timeout, blocking)) - break; - return PCM_gotoLPM0(); - case PCM_LPM3: - return PCM_gotoLPM3(); - case PCM_LPM4: - return PCM_gotoLPM4(); - case PCM_LPM45: - return PCM_shutdownDevice(PCM_LPM45); - case PCM_LPM35_VCORE0: - return PCM_shutdownDevice(PCM_LPM35_VCORE0); - default: - ASSERT(false); - return false; - } - - return false; - -} - -bool PCM_setPowerState(uint_fast8_t powerState) -{ - return __PCM_setPowerStateAdvanced(powerState, 0, true); -} - -bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState, uint32_t timeout) -{ - return __PCM_setPowerStateAdvanced(powerState, timeout, true); -} - -bool PCM_setPowerStateNonBlocking(uint_fast8_t powerState) -{ - return __PCM_setPowerStateAdvanced(powerState, 0, false); -} - -bool PCM_shutdownDevice(uint32_t shutdownMode) -{ - uint32_t shutdownModeBits = (shutdownMode == PCM_LPM45) ? - PCM_CTL0_LPMR_12 : PCM_CTL0_LPMR_10; - - ASSERT( - shutdownMode == PCM_SHUTDOWN_PARTIAL - || shutdownMode == PCM_SHUTDOWN_COMPLETE); - - /* If a power transition is occuring, return false */ - if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) - return false; - - /* Initiating the shutdown */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - PCM->CTL0 = (PCM_KEY | shutdownModeBits - | (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK))); - - CPU_wfi(); - - return true; -} - -bool PCM_gotoLPM4(void) -{ - /* Disabling RTC_C and WDT_A */ - WDT_A_holdTimer(); - RTC_C_holdClock(); - - /* LPM4 is just LPM3 with WDT_A/RTC_C disabled... */ - return PCM_gotoLPM3(); -} - -bool PCM_gotoLPM4InterruptSafe(void) -{ - bool slHappenedCorrect; - - /* Disabling master interrupts. In Cortex M, if an interrupt is enabled but - master interrupts are disabled and a WFI happens the WFI will - immediately exit. */ - Interrupt_disableMaster(); - - slHappenedCorrect = PCM_gotoLPM4(); - - /* Enabling and Disabling Interrupts very quickly so that the - processor catches any pending interrupts */ - Interrupt_enableMaster(); - Interrupt_disableMaster(); - - return slHappenedCorrect; -} - -bool PCM_gotoLPM0(void) -{ - /* If we are in the middle of a state transition, return false */ - if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) - return false; - - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - - CPU_wfi(); - - return true; -} - -bool PCM_gotoLPM0InterruptSafe(void) -{ - bool slHappenedCorrect; - - /* Disabling master interrupts. In Cortex M, if an interrupt is enabled but - master interrupts are disabled and a WFI happens the WFI will - immediately exit. */ - Interrupt_disableMaster(); - - slHappenedCorrect = PCM_gotoLPM0(); - - /* Enabling and Disabling Interrupts very quickly so that the - processor catches any pending interrupts */ - Interrupt_enableMaster(); - Interrupt_disableMaster(); - - return slHappenedCorrect; -} - -bool PCM_gotoLPM3(void) -{ - uint_fast8_t bCurrentPowerState; - uint_fast8_t currentPowerMode; - - /* If we are in the middle of a state transition, return false */ - if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) - return false; - - /* If we are in the middle of a shutdown, return false */ - if ((PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_10 - || (PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_12) - return false; - - currentPowerMode = PCM_getPowerMode(); - bCurrentPowerState = PCM_getPowerState(); - - if (currentPowerMode == PCM_DCDC_MODE) - PCM_setPowerMode(PCM_LDO_MODE); - - /* Clearing the SDR */ - PCM->CTL0 = (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)) | PCM_KEY; - - /* Setting the sleep deep bit */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - CPU_wfi(); - - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - - return PCM_setPowerState(bCurrentPowerState); -} - -bool PCM_gotoLPM3InterruptSafe(void) -{ - bool lpmHappenedCorrect; - - /* Disabling master interrupts. In Cortex M, if an interrupt is enabled but - master interrupts are disabled and a WFI happens the WFI will - immediately exit. */ - Interrupt_disableMaster(); - - lpmHappenedCorrect = PCM_gotoLPM3(); - - /* Enabling and Disabling Interrupts very quickly so that the - processor catches any pending interrupts */ - Interrupt_enableMaster(); - Interrupt_disableMaster(); - - return lpmHappenedCorrect; -} - -uint8_t PCM_getPowerState(void) -{ - return (PCM->CTL0 & PCM_CTL0_CPM_MASK) >> PCM_CTL0_CPM_OFS; -} - -void PCM_enableRudeMode(void) -{ - - PCM->CTL1 = (PCM->CTL1 & ~(PCM_CTL0_KEY_MASK)) | PCM_KEY - | PCM_CTL1_FORCE_LPM_ENTRY; -} - -void PCM_disableRudeMode(void) -{ - PCM->CTL1 = (PCM->CTL1 & ~(PCM_CTL0_KEY_MASK | PCM_CTL1_FORCE_LPM_ENTRY)) - | PCM_KEY; -} - -void PCM_enableInterrupt(uint32_t flags) -{ - PCM->IE |= flags; -} - -void PCM_disableInterrupt(uint32_t flags) -{ - PCM->IE &= ~flags; -} - -uint32_t PCM_getInterruptStatus(void) -{ - return PCM->IFG; -} - -uint32_t PCM_getEnabledInterruptStatus(void) -{ - return PCM_getInterruptStatus() & PCM->IE; -} - -void PCM_clearInterruptFlag(uint32_t flags) -{ - PCM->CLRIFG |= flags; -} - -void PCM_registerInterrupt(void (*intHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - Interrupt_registerInterrupt(INT_PCM, intHandler); - - // - // Enable the system control interrupt. - // - Interrupt_enableInterrupt(INT_PCM); -} - -void PCM_unregisterInterrupt(void) -{ - // - // Disable the interrupt. - // - Interrupt_disableInterrupt(INT_PCM); - - // - // Unregister the interrupt handler. - // - Interrupt_unregisterInterrupt(INT_PCM); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pcm.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pcm.h deleted file mode 100644 index 60a3c8791ee..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pcm.h +++ /dev/null @@ -1,706 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __PCM_H__ -#define __PCM_H__ - -//***************************************************************************** -// -//! \addtogroup pcm_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include - -//***************************************************************************** -// -// Control specific variables -// -//***************************************************************************** -#define PCM_KEY 0x695A0000 - -/* Power Modes */ -#define PCM_AM_LDO_VCORE0 0x00 -#define PCM_AM_LDO_VCORE1 0x01 -#define PCM_AM_DCDC_VCORE0 0x04 -#define PCM_AM_DCDC_VCORE1 0x05 -#define PCM_AM_LF_VCORE0 0x08 -#define PCM_AM_LF_VCORE1 0x09 -#define PCM_LPM0_LDO_VCORE0 0x10 -#define PCM_LPM0_LDO_VCORE1 0x11 -#define PCM_LPM0_DCDC_VCORE0 0x14 -#define PCM_LPM0_DCDC_VCORE1 0x15 -#define PCM_LPM0_LF_VCORE0 0x18 -#define PCM_LPM0_LF_VCORE1 0x19 -#define PCM_LPM3 0x20 -#define PCM_LPM4 0x21 -#define PCM_LPM35_VCORE0 0xC0 -#define PCM_LPM45 0xA0 - -#define PCM_VCORE0 0x00 -#define PCM_VCORE1 0x01 -#define PCM_VCORELPM3 0x02 - -#define PCM_LDO_MODE 0x00 -#define PCM_DCDC_MODE 0x01 -#define PCM_LF_MODE 0x02 - -#define PCM_SHUTDOWN_PARTIAL PCM_LPM35_VCORE0 -#define PCM_SHUTDOWN_COMPLETE PCM_LPM45 - -#define PCM_DCDCERROR PCM_IE_DCDC_ERROR_IE -#define PCM_AM_INVALIDTRANSITION PCM_IE_AM_INVALID_TR_IE -#define PCM_SM_INVALIDCLOCK PCM_IE_LPM_INVALID_CLK_IE -#define PCM_SM_INVALIDTRANSITION PCM_IE_LPM_INVALID_TR_IE - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//****************************************************************************** -// -//! Sets the core voltage level (Vcore). The function will take care of all -//! power state transitions needed to shift between core voltage levels. -//! Because transitions between voltage levels may require changes power modes, -//! the power mode might temporarily be change. The power mode will be returned -//! to the original state (with the new voltage level) at the end of a -//! successful execution of this function. -//! -//! Refer to the device specific data sheet for specifics about core voltage -//! levels. -//! -//! \param voltageLevel The voltage level to be shifted to. -//! - \b PCM_VCORE0, -//! - \b PCM_VCORE1 -//! -//! \return true if voltage level set, false otherwise. -// -//****************************************************************************** -extern bool PCM_setCoreVoltageLevel(uint_fast8_t voltageLevel); - -//****************************************************************************** -// -//! Returns the current powers state of the system see the -//! PCM_setCoreVoltageLevel function for specific information about the modes. -//! -//! \return The current voltage of the system -//! -//! Possible return values include: -//! - \b PCM_VCORE0 -//! - \b PCM_VCORE1 -//! - \b PCM_VCORELPM3 -//! -// -//****************************************************************************** -extern uint8_t PCM_getCoreVoltageLevel(void); - -//****************************************************************************** -// -//! Sets the core voltage level (Vcore). This function will take care of all -//! power state transitions needed to shift between core voltage levels. -//! Because transitions between voltage levels may require changes power modes, -//! the power mode might temporarily be change. The power mode will be returned -//! to the original state (with the new voltage level) at the end of a -//! successful execution of this function. -//! -//! This function is similar to PCMSetCoreVoltageLevel, however a timeout -//! mechanism is used. -//! -//! Refer to the device specific data sheet for specifics about core voltage -//! levels. -//! -//! \param voltageLevel The voltage level to be shifted to. -//! - \b PCM_VCORE0, -//! - \b PCM_VCORE1 -//! -//! \param timeOut Number of loop iterations to timeout when checking for -//! power state transitions. This should be used for debugging initial -//! power/hardware configurations. After a stable hardware base is -//! established, the PCMSetCoreVoltageLevel function should be used -//! -//! \return true if voltage level set, false otherwise. -// -//****************************************************************************** -extern bool PCM_setCoreVoltageLevelWithTimeout(uint_fast8_t voltageLevel, - uint32_t timeOut); - -//****************************************************************************** -// -//! Sets the core voltage level (Vcore). This function is similar to -//! PCM_setCoreVoltageLevel, however there are no polling flags to ensure -//! a state has changed. Execution is returned back to the calling program -// and it is up to the user to ensure proper state transitions happen -//! correctly. For MSP432, changing into different power modes/states -//! require very specific logic. This function will initiate only one state -//! transition and then return. It is up to the user to keep calling this -//! function until the correct power state has been achieved. -//! -//! Refer to the device specific data sheet for specifics about core voltage -//! levels. -//! -//! \param voltageLevel The voltage level to be shifted to. -//! - \b PCM_VCORE0, -//! - \b PCM_VCORE1 -//! -//! \return true if voltage level set, false otherwise. -// -//****************************************************************************** -extern bool PCM_setCoreVoltageLevelNonBlocking(uint_fast8_t voltageLevel); - -//****************************************************************************** -// -//! Switches between power modes. This function will take care of all -//! power state transitions needed to shift between power modes. Note for -//! changing to DCDC mode, specific hardware considerations are required. -//! -//! Refer to the device specific data sheet for specifics about power modes. -//! -//! \param powerMode The voltage modes to be shifted to. Valid values are: -//! - \b PCM_LDO_MODE, -//! - \b PCM_DCDC_MODE, -//! - \b PCM_LF_MODE -//! -//! \return true if power mode is set, false otherwise. -// -//****************************************************************************** -extern bool PCM_setPowerMode(uint_fast8_t powerMode); - -//****************************************************************************** -// -//! Switches between power modes. This function will take care of all -//! power state transitions needed to shift between power modes. Note for -//! changing to DCDC mode, specific hardware considerations are required. -//! -//! This function is similar to PCMSetPowerMode, however a timeout -//! mechanism is used. -//! -//! Refer to the device specific data sheet for specifics about power modes. -//! -//! \param powerMode The voltage modes to be shifted to. Valid values are: -//! - \b PCM_LDO_MODE, -//! - \b PCM_DCDC_MODE, -//! - \b PCM_LF_MODE -//! -//! \param timeOut Number of loop iterations to timeout when checking for -//! power state transitions. This should be used for debugging initial -//! power/hardware configurations. After a stable hardware base is -//! established, the PCMSetPowerMode function should be used -//! -//! \return true if power mode is set, false otherwise. -// -//****************************************************************************** -extern bool PCM_setPowerModeWithTimeout(uint_fast8_t powerMode, - uint32_t timeOut); - -//****************************************************************************** -// -//! Sets the core voltage level (Vcore). This function is similar to -//! PCM_setPowerMode, however there are no polling flags to ensure -//! a state has changed. Execution is returned back to the calling program -// and it is up to the user to ensure proper state transitions happen -//! correctly. For MSP432, changing into different power modes/states -//! require very specific logic. This function will initiate only one state -//! transition and then return. It is up to the user to keep calling this -//! function until the correct power state has been achieved. -//! -//! Refer to the device specific data sheet for specifics about core voltage -//! levels. -//! -//! \param powerMode The voltage modes to be shifted to. Valid values are: -//! - \b PCM_LDO_MODE, -//! - \b PCM_DCDC_MODE, -//! - \b PCM_LF_MODE -//! -//! \return true if power mode change was initiated, false otherwise -// -//****************************************************************************** -extern bool PCM_setPowerModeNonBlocking(uint_fast8_t powerMode); - -//****************************************************************************** -// -//! Returns the current powers state of the system see the \b PCM_setPowerState -//! function for specific information about the modes. -//! -//! \return The current power mode of the system -//! -// -//****************************************************************************** -extern uint8_t PCM_getPowerMode(void); - -//****************************************************************************** -// -//! Switches between power states. This is a convenience function that combines -//! the functionality of PCM_setPowerMode and PCM_setCoreVoltageLevel as well as -//! the LPM0/LPM3 functions. -//! -//! Refer to the device specific data sheet for specifics about power states. -//! -//! \param powerState The voltage modes to be shifted to. Valid values are: -//! - \b PCM_AM_LDO_VCORE0, [Active Mode, LDO, VCORE0] -//! - \b PCM_AM_LDO_VCORE1, [Active Mode, LDO, VCORE1] -//! - \b PCM_AM_DCDC_VCORE0, [Active Mode, DCDC, VCORE0] -//! - \b PCM_AM_DCDC_VCORE1, [Active Mode, DCDC, VCORE1] -//! - \b PCM_AM_LF_VCORE0, [Active Mode, Low Frequency, VCORE0] -//! - \b PCM_AM_LF_VCORE1, [Active Mode, Low Frequency, VCORE1] -//! - \b PCM_LPM0_LDO_VCORE0, [LMP0, LDO, VCORE0] -//! - \b PCM_LPM0_LDO_VCORE1, [LMP0, LDO, VCORE1] -//! - \b PCM_LPM0_DCDC_VCORE0, [LMP0, DCDC, VCORE0] -//! - \b PCM_LPM0_DCDC_VCORE1, [LMP0, DCDC, VCORE1] -//! - \b PCM_LPM0_LF_VCORE0, [LMP0, Low Frequency, VCORE0] -//! - \b PCM_LPM0_LF_VCORE1, [LMP0, Low Frequency, VCORE1] -//! - \b PCM_LPM3, [LPM3] -//! - \b PCM_LPM35_VCORE0, [LPM3.5 VCORE 0] -//! - \b PCM_LPM4, [LPM4] -//! - \b PCM_LPM45, [LPM4.5] -//! -//! \return true if power state is set, false otherwise. -// -//****************************************************************************** -extern bool PCM_setPowerState(uint_fast8_t powerState); - -//****************************************************************************** -// -//! Switches between power states. This is a convenience function that combines -//! the functionality of PCM_setPowerMode and PCM_setCoreVoltageLevel as well as -//! the LPM modes. -//! -//! This function is similar to PCM_setPowerState, however a timeout -//! mechanism is used. -//! -//! Refer to the device specific data sheet for specifics about power states. -//! -//! \param powerState The voltage modes to be shifted to. Valid values are: -//! - \b PCM_AM_LDO_VCORE0, [Active Mode, LDO, VCORE0] -//! - \b PCM_AM_LDO_VCORE1, [Active Mode, LDO, VCORE1] -//! - \b PCM_AM_DCDC_VCORE0, [Active Mode, DCDC, VCORE0] -//! - \b PCM_AM_DCDC_VCORE1, [Active Mode, DCDC, VCORE1] -//! - \b PCM_AM_LF_VCORE0, [Active Mode, Low Frequency, VCORE0] -//! - \b PCM_AM_LF_VCORE1, [Active Mode, Low Frequency, VCORE1] -//! - \b PCM_LPM0_LDO_VCORE0, [LMP0, LDO, VCORE0] -//! - \b PCM_LPM0_LDO_VCORE1, [LMP0, LDO, VCORE1] -//! - \b PCM_LPM0_DCDC_VCORE0, [LMP0, DCDC, VCORE0] -//! - \b PCM_LPM0_DCDC_VCORE1, [LMP0, DCDC, VCORE1] -//! - \b PCM_LPM0_LF_VCORE0, [LMP0, Low Frequency, VCORE0] -//! - \b PCM_LPM0_LF_VCORE1, [LMP0, Low Frequency, VCORE1] -//! - \b PCM_LPM3, [LPM3] -//! - \b PCM_LPM35_VCORE0, [LPM3.5 VCORE 0] -//! - \b PCM_LPM4, [LPM4] -//! - \b PCM_LPM45, [LPM4.5] -//! -//! \param timeout Number of loop iterations to timeout when checking for -//! power state transitions. This should be used for debugging initial -//! power/hardware configurations. After a stable hardware base is -//! established, the PCMSetPowerMode function should be used -//! -//! \return true if power state is set, false otherwise. It is important to -//! note that if a timeout occurs, false will be returned, however the -//! power state at this point is not guaranteed to be the same as the -//! state prior to the function call -// -//****************************************************************************** -extern bool PCM_setPowerStateWithTimeout(uint_fast8_t powerState, - uint32_t timeout); - -//****************************************************************************** -// -//! Returns the current powers state of the system see the PCMChangePowerState -//! function for specific information about the states. -//! -//! Refer to \link PCM_setPowerState \endlink for possible return values. -//! -//! \return The current power state of the system -// -//****************************************************************************** -extern uint8_t PCM_getPowerState(void); - -//****************************************************************************** -// -//! Sets the power state of the part. This function is similar to -//! PCM_getPowerState, however there are no polling flags to ensure -//! a state has changed. Execution is returned back to the calling program -// and it is up to the user to ensure proper state transitions happen -//! correctly. For MSP432, changing into different power modes/states -//! require very specific logic. This function will initiate only one state -//! transition and then return. It is up to the user to keep calling this -//! function until the correct power state has been achieved. -//! -//! Refer to the device specific data sheet for specifics about core voltage -//! levels. -//! -//! \param powerState The voltage modes to be shifted to. Valid values are: -//! - \b PCM_AM_LDO_VCORE0, [Active Mode, LDO, VCORE0] -//! - \b PCM_AM_LDO_VCORE1, [Active Mode, LDO, VCORE1] -//! - \b PCM_AM_DCDC_VCORE0, [Active Mode, DCDC, VCORE0] -//! - \b PCM_AM_DCDC_VCORE1, [Active Mode, DCDC, VCORE1] -//! - \b PCM_AM_LF_VCORE0, [Active Mode, Low Frequency, VCORE0] -//! - \b PCM_AM_LF_VCORE1, [Active Mode, Low Frequency, VCORE1] -//! - \b PCM_LPM0_LDO_VCORE0, [LMP0, LDO, VCORE0] -//! - \b PCM_LPM0_LDO_VCORE1, [LMP0, LDO, VCORE1] -//! - \b PCM_LPM0_DCDC_VCORE0, [LMP0, DCDC, VCORE0] -//! - \b PCM_LPM0_DCDC_VCORE1, [LMP0, DCDC, VCORE1] -//! - \b PCM_LPM0_LF_VCORE0, [LMP0, Low Frequency, VCORE0] -//! - \b PCM_LPM0_LF_VCORE1, [LMP0, Low Frequency, VCORE1] -//! - \b PCM_LPM3, [LPM3] -//! - \b PCM_LPM35_VCORE0, [LPM3.5 VCORE 0] -//! - \b PCM_LPM45, [LPM4.5] -//! -//! \return true if power state change was initiated, false otherwise -// -//****************************************************************************** -extern bool PCM_setPowerStateNonBlocking(uint_fast8_t powerState); - -//****************************************************************************** -// -//! Transitions the device into LPM3.5/LPM4.5 mode. -//! -//! Refer to the device specific data sheet for specifics about shutdown modes. -//! -//! The following events will cause a wake up from LPM3.5 mode: -//! - Device reset -//! - External reset RST -//! - Enabled RTC, WDT, and wake-up I/O only interrupt events -//! -//! The following events will cause a wake up from the LPM4.5 mode: -//! - Device reset -//! - External reset RST -//! - Wake-up I/O only interrupt events -//! -//! \param shutdownMode Specific mode to go to. Valid values are: -//! - \b PCM_LPM35_VCORE0 -//! - \b PCM_LPM45 -//! -//! -//! \return false if LPM state cannot be entered, true otherwise. -// -//****************************************************************************** -extern bool PCM_shutdownDevice(uint32_t shutdownMode); - -//****************************************************************************** -// -//! Transitions the device into LPM0. -//! -//! Refer to the device specific data sheet for specifics about low power modes. -//! -//! \return false if LPM0 state cannot be entered, true otherwise. -// -//****************************************************************************** -extern bool PCM_gotoLPM0(void); - -//****************************************************************************** -// -//! Transitions the device into LPM3 -//! -//! Refer to the device specific data sheet for specifics about low power modes. -//! Note that since LPM3 cannot be entered from a DCDC power modes, the -//! power mode is first switched to LDO operation (if in DCDC mode), -//! LPM3 is entered, and the DCDC mode is restored on wake up. -//! -//! \return false if LPM3 state cannot be entered, true otherwise. -// -//****************************************************************************** -extern bool PCM_gotoLPM3(void); - -//****************************************************************************** -// -//! Transitions the device into LPM0 while maintaining a safe -//! interrupt handling mentality. This function is meant to be used in -//! situations where the user wants to go to LPM0, however does not want -//! to go to "miss" any interrupts due to the fact that going to LPM0 is not -//! an atomic operation. This function will modify the PRIMASK and on exit of -//! the program the master interrupts will be disabled. -//! -//! Refer to the device specific data sheet for specifics about low power modes. -//! -//! \return false if LPM0 state cannot be entered, true otherwise. -// -//****************************************************************************** -extern bool PCM_gotoLPM0InterruptSafe(void); - -//****************************************************************************** -// -//! Transitions the device into LPM3 while maintaining a safe -//! interrupt handling mentality. This function is meant to be used in -//! situations where the user wants to go to LPM3, however does not want -//! to go to "miss" any interrupts due to the fact that going to LPM3 is not -//! an atomic operation. This function will modify the PRIMASK and on exit of -//! the program the master interrupts will be disabled. -//! -//! Refer to the device specific data sheet for specifics about low power modes. -//! Note that since LPM3 cannot be entered from a DCDC power modes, the -//! power mode is first switched to LDO operation (if in DCDC mode), the LPM3 -//! is entered, and the DCDC mode is restored on wake up. -//! -//! \return false if LPM3 cannot be entered, true otherwise. -// -//****************************************************************************** -extern bool PCM_gotoLPM3InterruptSafe(void); - -//****************************************************************************** -// -//! Transitions the device into LPM4. LPM4 is the exact same with LPM3, just -//! with RTC_C and WDT_A disabled. When waking up, RTC_C and WDT_A will remain -//! disabled until reconfigured by the user. -//! -//! \return false if LPM4 state cannot be entered, true otherwise. -// -//****************************************************************************** -extern bool PCM_gotoLPM4(void); - -//****************************************************************************** -// -//! Transitions the device into LPM4 while maintaining a safe -//! interrupt handling mentality. This function is meant to be used in -//! situations where the user wants to go to LPM4, however does not want -//! to go to "miss" any interrupts due to the fact that going to LPM4 is not -//! an atomic operation. This function will modify the PRIMASK and on exit of -//! the program the master interrupts will be disabled. -//! -//! Refer to the device specific data sheet for specifics about low power modes. -//! Note that since LPM3 cannot be entered from a DCDC power modes, the -//! power mode is first switched to LDO operation (if in DCDC mode), -//! LPM4 is entered, and the DCDC mode is restored on wake up. -//! -//! \return false if LPM4 state cannot be entered, true otherwise. -// -//****************************************************************************** -extern bool PCM_gotoLPM4InterruptSafe(void); - -//****************************************************************************** -// -//! Enables "rude mode" entry into LPM3 and shutdown modes. With this mode -//! enabled, an entry into shutdown or LPM3 will occur even if there are -//! clock systems active. The system will forcibly turn off all clock/systems -//! when going into these modes. -//! -//! \return None -// -//****************************************************************************** -extern void PCM_enableRudeMode(void); - -//****************************************************************************** -// -//! Disables "rude mode" entry into LPM3 and shutdown modes. With this -//! mode disabled, an entry into shutdown or LPM3 will wait for any -//! active clock requests to free up before going into LPM3 or shutdown. -//! -//! \return None -// -//****************************************************************************** -extern void PCM_disableRudeMode(void); - -//***************************************************************************** -// -//! Enables individual power control interrupt sources. -//! -//! \param flags is a bit mask of the interrupt sources to be enabled. Must -//! be a logical OR of: -//! - \b PCM_DCDCERROR, -//! - \b PCM_AM_INVALIDTRANSITION, -//! - \b PCM_SM_INVALIDCLOCK, -//! - \b PCM_SM_INVALIDTRANSITION -//! -//! This function enables the indicated power control interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -extern void PCM_enableInterrupt(uint32_t flags); - -//***************************************************************************** -// -//! Disables individual power control interrupt sources. -//! -//! \param flags is a bit mask of the interrupt sources to be enabled. Must -//! be a logical OR of: -//! - \b PCM_DCDCERROR, -//! - \b PCM_AM_INVALIDTRANSITION, -//! - \b PCM_SM_INVALIDCLOCK, -//! - \b PCM_SM_INVALIDTRANSITION -//! -//! This function disables the indicated power control interrupt sources. Only -//! the sources that are enabled can be reflected to the processor interrupt; -//! disabled sources have no effect on the processor. -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -extern void PCM_disableInterrupt(uint32_t flags); - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \return The current interrupt status, enumerated as a bit field of: -//! - \b PCM_DCDCERROR, -//! - \b PCM_AM_INVALIDTRANSITION, -//! - \b PCM_SM_INVALIDCLOCK, -//! - \b PCM_SM_INVALIDTRANSITION -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -// -//***************************************************************************** -extern uint32_t PCM_getInterruptStatus(void); - -//***************************************************************************** -// -//! Gets the current interrupt status masked with the enabled interrupts. -//! This function is useful to call in ISRs to get a list of pending -//! interrupts that are actually enabled and could have caused -//! the ISR. -//! -//! \return The current interrupt status, enumerated as a bit field of: -//! - \b PCM_DCDCERROR, -//! - \b PCM_AM_INVALIDTRANSITION, -//! - \b PCM_SM_INVALIDCLOCK, -//! - \b PCM_SM_INVALIDTRANSITION -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -// -//***************************************************************************** -extern uint32_t PCM_getEnabledInterruptStatus(void); - -//***************************************************************************** -// -//! Clears power system interrupt sources. -//! -//! The specified power system interrupt sources are cleared, so that they no -//! longer assert. This function must be called in the interrupt handler to -//! keep it from being called again immediately upon exit. -//! -//! \note Because there is a write buffer in the Cortex-M processor, it may -//! take several clock cycles before the interrupt source is actually cleared. -//! Therefore, it is recommended that the interrupt source be cleared early in -//! the interrupt handler (as opposed to the very last action) to avoid -//! returning from the interrupt handler before the interrupt source is -//! actually cleared. Failure to do so may result in the interrupt handler -//! being immediately reentered (because the interrupt controller still sees -//! the interrupt source asserted). -//! -//! \param flags is a bit mask of the interrupt sources to be cleared. Must -//! be a logical OR of -//! - \b PCM_DCDCERROR, -//! - \b PCM_AM_INVALIDTRANSITION, -//! - \b PCM_SM_INVALIDCLOCK, -//! - \b PCM_SM_INVALIDTRANSITION -//! -//! \note The interrupt sources vary based on the part in use. -//! Please consult the data sheet for the part you are using to determine -//! which interrupt sources are available. -//! -//! \return None. -// -//***************************************************************************** -extern void PCM_clearInterruptFlag(uint32_t flags); - -//***************************************************************************** -// -//! Registers an interrupt handler for the power system interrupt. -//! -//! \param intHandler is a pointer to the function to be called when the power -//! system interrupt occurs. -//! -//! This function registers the handler to be called when a clock system -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific PCM interrupts must be enabled -//! via PCM_enableInterrupt(). It is the interrupt handler's responsibility to -//! clear the interrupt source via \link PCM_clearInterruptFlag \endlink . -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void PCM_registerInterrupt(void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the power system. -//! -//! This function unregisters the handler to be called when a power system -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void PCM_unregisterInterrupt(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif // __PCM_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pmap.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pmap.c deleted file mode 100644 index eecc8a1dace..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pmap.c +++ /dev/null @@ -1,61 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include - - -void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy, - uint8_t numberOfPorts, uint8_t portMapReconfigure) -{ - uint_fast16_t i; - - ASSERT( - (portMapReconfigure == PMAP_ENABLE_RECONFIGURATION) - || (portMapReconfigure == PMAP_DISABLE_RECONFIGURATION)); - - //Get write-access to port mapping registers: - PMAP->KEYID = PMAP_KEYID_VAL; - - //Enable/Disable reconfiguration during runtime - PMAP->CTL = (PMAP->CTL & ~PMAP_CTL_PRECFG) | portMapReconfigure; - - //Configure Port Mapping: - - for (i = 0; i < numberOfPorts * 8; i++) - { - HWREG8(PMAP_BASE + i + pxMAPy) = portMapping[i]; - } - - //Disable write-access to port mapping registers: - PMAP->KEYID = 0; -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pmap.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pmap.h deleted file mode 100644 index fd41beab306..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pmap.h +++ /dev/null @@ -1,124 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __PMAP_H__ -#define __PMAP_H__ - -//***************************************************************************** -// -//! \addtogroup pmap_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -//***************************************************************************** -// -//The following are values that can be passed to the PMAP_configurePorts() API -//as the portMapReconfigure parameter. -// -//***************************************************************************** -#define PMAP_ENABLE_RECONFIGURATION PMAP_CTL_PRECFG -#define PMAP_DISABLE_RECONFIGURATION 0x00 - -//***************************************************************************** -// -//The following are values that can be passed to the PMAP_configurePorts() API -//as the pxMAPy parameter. -// -//***************************************************************************** -#define PMAP_P1MAP ((uint32_t)P1MAP - PMAP_BASE) -#define PMAP_P2MAP ((uint32_t)P2MAP - PMAP_BASE) -#define PMAP_P3MAP ((uint32_t)P3MAP - PMAP_BASE) -#define PMAP_P4MAP ((uint32_t)P4MAP - PMAP_BASE) -#define PMAP_P5MAP ((uint32_t)P5MAP - PMAP_BASE) -#define PMAP_P6MAP ((uint32_t)P6MAP - PMAP_BASE) -#define PMAP_P7MAP ((uint32_t)P7MAP - PMAP_BASE) - - -//***************************************************************************** -// -//Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! This function configures the MSP432 Port Mapper -//! -//! \param portMapping is the pointer to init Data -//! \param pxMAPy is the Port Mapper to initialize -//! \param numberOfPorts is the number of Ports to initialize -//! \param portMapReconfigure is used to enable/disable reconfiguration -//! Valid values are -//! \b PMAP_ENABLE_RECONFIGURATION -//! \b PMAP_DISABLE_RECONFIGURATION [Default value] -//! Modified registers are \b PMAPKEYID, \b PMAPCTL -//! -//! \return None -// -//***************************************************************************** -extern void PMAP_configurePorts(const uint8_t *portMapping, uint8_t pxMAPy, - uint8_t numberOfPorts, uint8_t portMapReconfigure); - -/* Defines for future devices that might have multiple instances */ -#define PMAP_configurePortsMultipleInstance(a,b,c,d,e) PMAP_configurePorts(b,c,d,e) - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pss.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pss.c deleted file mode 100644 index 0c1e6768aef..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pss.c +++ /dev/null @@ -1,219 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/* Standard Includes */ -#include - -/* DriverLib Includes */ -#include -#include -#include -#include - -static void __PSSUnlock() -{ - PSS->KEY = PSS_KEY_VALUE; -} - -static void __PSSLock() -{ - PSS->KEY = 0; -} - - -void PSS_enableForcedDCDCOperation(void) -{ - __PSSUnlock(); - - BITBAND_PERI(PSS->CTL0, PSS_CTL0_DCDC_FORCE_OFS) = 1; - - __PSSLock(); -} - -void PSS_disableForcedDCDCOperation(void) -{ - __PSSUnlock(); - - BITBAND_PERI(PSS->CTL0, PSS_CTL0_DCDC_FORCE_OFS) = 0; - - __PSSLock(); - -} - -void PSS_enableHighSidePinToggle(bool activeLow) -{ - __PSSUnlock(); - - if (activeLow) - PSS->CTL0 |= (PSS_CTL0_SVMHOE | PSS_CTL0_SVMHOUTPOLAL); - else - { - BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVMHOUTPOLAL_OFS) = 0; - BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVMHOE_OFS) = 1; - } - - __PSSLock(); -} - -void PSS_disableHighSidePinToggle(void) -{ - __PSSUnlock(); - - BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVMHOE_OFS) = 0; - - __PSSLock(); -} - -void PSS_enableHighSide(void) -{ - __PSSUnlock(); - - BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHOFF_OFS) = 0; - - __PSSLock(); -} - -void PSS_disableHighSide(void) -{ - __PSSUnlock(); - - BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHOFF_OFS) = 1; - - __PSSLock(); -} - -void PSS_setHighSidePerformanceMode(uint_fast8_t powerMode) -{ - __PSSUnlock(); - - if (powerMode == PSS_FULL_PERFORMANCE_MODE) - BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHLP_OFS) = 0; - else - BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHLP_OFS) = 1; - - __PSSLock(); -} - -uint_fast8_t PSS_getHighSidePerformanceMode(void) -{ - if (BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHLP_OFS)) - return PSS_NORMAL_PERFORMANCE_MODE; - else - return PSS_FULL_PERFORMANCE_MODE; -} - -void PSS_enableHighSideMonitor(void) -{ - __PSSUnlock(); - - BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHS_OFS) = 1; - - __PSSLock(); -} - -void PSS_disableHighSideMonitor(void) -{ - __PSSUnlock(); - - BITBAND_PERI(PSS->CTL0, PSS_CTL0_SVSMHS_OFS) = 0; - - __PSSLock(); -} - -void PSS_setHighSideVoltageTrigger(uint_fast8_t triggerVoltage) -{ - __PSSUnlock(); - - ASSERT(!(triggerVoltage & 0xF8)) - - PSS->CTL0 &= ~PSS_CTL0_SVSMHTH_MASK; - PSS->CTL0 |= (triggerVoltage & 0x07) << PSS_CTL0_SVSMHTH_OFS; - - __PSSLock(); -} - -uint_fast8_t PSS_getHighSideVoltageTrigger(void) -{ - return (uint_fast8_t)((PSS->CTL0 & PSS_CTL0_SVSMHTH_MASK) - >> PSS_CTL0_SVSMHTH_OFS); -} - -void PSS_enableInterrupt(void) -{ - __PSSUnlock(); - BITBAND_PERI(PSS->IE,PSS_IE_SVSMHIE_OFS) = 1; - __PSSLock(); -} - -void PSS_disableInterrupt(void) -{ - __PSSUnlock(); - BITBAND_PERI(PSS->IE,PSS_IE_SVSMHIE_OFS) = 0; - __PSSLock(); -} - -uint32_t PSS_getInterruptStatus(void) -{ - return PSS->IFG; -} - -void PSS_clearInterruptFlag(void) -{ - __PSSUnlock(); - BITBAND_PERI(PSS->CLRIFG,PSS_CLRIFG_CLRSVSMHIFG_OFS) = 0; - __PSSLock(); -} - -void PSS_registerInterrupt(void (*intHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - Interrupt_registerInterrupt(INT_PSS, intHandler); - - // - // Enable the system control interrupt. - // - Interrupt_enableInterrupt(INT_PSS); -} - -void PSS_unregisterInterrupt(void) -{ - // - // Disable the interrupt. - // - Interrupt_disableInterrupt(INT_PSS); - - // - // Unregister the interrupt handler. - // - Interrupt_unregisterInterrupt(INT_PSS); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pss.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pss.h deleted file mode 100644 index 2edb80b9204..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/pss.h +++ /dev/null @@ -1,316 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __PSS_H__ -#define __PSS_H__ - -//***************************************************************************** -// -//! \addtogroup pss_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include - -//***************************************************************************** -// -// Control specific variables -// -//***************************************************************************** -#define PSS_KEY_VALUE PSS_KEY_KEY_VAL - -#define PSS_SVSMH PSS_IE_SVSMHIE - -#define PSS_FULL_PERFORMANCE_MODE 0x01 -#define PSS_NORMAL_PERFORMANCE_MODE 0x00 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! Enables output of the High Side interrupt flag on the device \b SVMHOUT pin -//! -//! \param activeLow True if the signal should be logic low when SVSMHIFG -//! is set. False if signal should be high when \b SVSMHIFG is set. -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_enableHighSidePinToggle(bool activeLow); - -//***************************************************************************** -// -//! Disables output of the High Side interrupt flag on the device \b SVMHOUT pin -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_disableHighSidePinToggle(void); - -//***************************************************************************** -// -//! Enables high side voltage supervisor/monitor. -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_enableHighSide(void); - -//***************************************************************************** -// -//! Disables high side voltage supervisor/monitor. -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_disableHighSide(void); - -//***************************************************************************** -// -//! Sets the performance mode of the high side regulator. Full performance -//! mode allows for the best response times while normal performance mode is -//! optimized for the lowest possible current consumption. -//! -//! \param powerMode is the performance mode to set. Valid values are one of -//! the following: -//! - \b PSS_FULL_PERFORMANCE_MODE, -//! - \b PSS_NORMAL_PERFORMANCE_MODE -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_setHighSidePerformanceMode(uint_fast8_t powerMode); - -//***************************************************************************** -// -//! Gets the performance mode of the high side voltage regulator. Refer to the -//! user's guide for specific information about information about the different -//! performance modes. -//! -//! \return Performance mode of the voltage regulator -// -//***************************************************************************** -extern uint_fast8_t PSS_getHighSidePerformanceMode(void); - -//***************************************************************************** -// -//! Sets the high side voltage supervisor to monitor mode -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_enableHighSideMonitor(void); - -//***************************************************************************** -// -//! Switches the high side of the power supply system to be a supervisor instead -//! of a monitor -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_disableHighSideMonitor(void); - -//***************************************************************************** -// -//! Sets the voltage level at which the high side of the device voltage -//! regulator triggers a reset. This value is represented as an unsigned eight -//! bit integer where only the lowest three bits are most significant. -//! -//! \param triggerVoltage Voltage level in which high side supervisor/monitor -//! triggers a reset. See the device specific data sheet for details -//! on these voltage levels. -//! -//! Typical values will vary from part to part (so it is very important to -//! check the SVSH section of the data sheet. For reference only, the typical -//! MSP432 101 values are listed below: -//! - 0 --> 1.57V -//! - 1 --> 1.62V -//! - 2 --> 1.83V -//! - 3 --> 2V -//! - 4 --> 2.25V -//! - 5 --> 2.4V -//! - 6 --> 2.6V -//! - 7 --> 2.8V -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_setHighSideVoltageTrigger(uint_fast8_t triggerVoltage); - -//***************************************************************************** -// -//! Returns the voltage level at which the high side of the device voltage -//! regulator triggers a reset. -//! -//! \return The voltage level that the high side voltage supervisor/monitor -//! triggers a reset. This value is represented as an unsigned eight -//! bit integer where only the lowest three bits are most significant. -//! See \link PSS_setHighSideVoltageTrigger \endlink for information regarding -//! the return value -// -//***************************************************************************** -extern uint_fast8_t PSS_getHighSideVoltageTrigger(void); - -//***************************************************************************** -// -//! Enables the power supply system interrupt source. -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_enableInterrupt(void); - -//***************************************************************************** -// -//! Disables the power supply system interrupt source. -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_disableInterrupt(void); - -//***************************************************************************** -// -//! Gets the current interrupt status. -//! -//! \return The current interrupt status ( \b PSS_SVSMH ) -//! -//***************************************************************************** -extern uint32_t PSS_getInterruptStatus(void); - -//***************************************************************************** -// -//! Clears power supply system interrupt source. -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_clearInterruptFlag(void); - - -//***************************************************************************** -// -//! Enables the "forced" mode of the DCDC regulator. In this mode, the fail -//! safe mechanism that disables the regulator to LDO mode when the supply -//! voltage falls below the minimum supply voltage required for DCDC operation -//! is turned off. -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_enableForcedDCDCOperation(void); - - -//***************************************************************************** -// -//! Disables the "forced" mode of the DCDC regulator. In this mode, the fail -//! safe mechanism that disables the regulator to LDO mode when the supply -//! voltage falls below the minimum supply voltage required for DCDC operation -//! is turned on. -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_disableForcedDCDCOperation(void); - -//***************************************************************************** -// -//! Registers an interrupt handler for the power supply system interrupt. -//! -//! \param intHandler is a pointer to the function to be called when the power -//! supply system interrupt occurs. -//! -//! This function registers the handler to be called when a power supply system -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific PSS interrupts must be enabled -//! via PSS_enableInterrupt(). It is the interrupt handler's responsibility to -//! clear the interrupt source via PSS_clearInterruptFlag(). -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_registerInterrupt(void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the power supply system -//! -//! This function unregisters the handler to be called when a power supply -//! system interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void PSS_unregisterInterrupt(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif // __PSS_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/ref_a.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/ref_a.c deleted file mode 100644 index 504e90c6a44..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/ref_a.c +++ /dev/null @@ -1,111 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include - -void REF_A_setReferenceVoltage(uint_fast8_t referenceVoltageSelect) -{ - ASSERT(referenceVoltageSelect <= REF_A_VREF2_5V); - - REF_A->CTL0 = (REF_A->CTL0 & ~REF_A_CTL0_VSEL_3) | referenceVoltageSelect; -} - -void REF_A_disableTempSensor(void) -{ - BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_TCOFF_OFS) = 1; -} - -void REF_A_enableTempSensor(void) -{ - BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_TCOFF_OFS) = 0; -} - -void REF_A_enableReferenceVoltageOutput(void) -{ - BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_OUT_OFS) = 1; -} - -void REF_A_disableReferenceVoltageOutput(void) -{ - BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_OUT_OFS) = 0; -} - -void REF_A_enableReferenceVoltage(void) -{ - BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_ON_OFS) = 1; -} - -void REF_A_disableReferenceVoltage(void) -{ - BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_ON_OFS) = 0; -} - -uint_fast8_t REF_A_getBandgapMode(void) -{ - return (REF_A->CTL0 & REF_A_CTL0_BGMODE); -} - -bool REF_A_isBandgapActive(void) -{ - return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_BGACT_OFS); -} - -bool REF_A_isRefGenBusy(void) -{ - return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENBUSY_OFS); -} - -bool REF_A_isRefGenActive(void) -{ - return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENACT_OFS); -} - -bool REF_A_getBufferedBandgapVoltageStatus(void) -{ - return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_BGRDY_OFS); -} - -bool REF_A_getVariableReferenceVoltageStatus(void) -{ - return BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENRDY_OFS); -} - -void REF_A_setReferenceVoltageOneTimeTrigger(void) -{ - BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_GENOT_OFS) = 1; -} - -void REF_A_setBufferedBandgapVoltageOneTimeTrigger(void) -{ - BITBAND_PERI(REF_A->CTL0,REF_A_CTL0_BGOT_OFS) = 1; -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/ref_a.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/ref_a.h deleted file mode 100644 index 78dc9cb0d86..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/ref_a.h +++ /dev/null @@ -1,341 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __REF_B_H__ -#define __REF_B_H__ - -//***************************************************************************** -// -//! \addtogroup ref_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -//The following are values that can be passed to Ref_setReferenceVoltage() -//in the referenceVoltageSelect parameter. -// -//***************************************************************************** -#define REF_A_VREF1_2V REF_A_CTL0_VSEL_0 -#define REF_A_VREF1_45V REF_A_CTL0_VSEL_1 -#define REF_A_VREF2_5V REF_A_CTL0_VSEL_3 - -//***************************************************************************** -// -//The following are values that are returned by Ref_getBandgapMode(). -// -//***************************************************************************** -#define REF_A_STATICMODE 0x0 -#define REF_A_SAMPLEMODE REF_A_CTL0_BGMODE - -//***************************************************************************** -// -//! Sets the reference voltage for the voltage generator. -//! -//! \param referenceVoltageSelect is the desired voltage to generate for a -//! reference voltage. -//! Valid values are: -//! - \b REF_A_VREF1_2V [Default] -//! - \b REF_A_VREF1_45V -//! - \b REF_A_VREF2_5V -//! Modified bits are \b REFVSEL of \b REFCTL0 register. -//! -//! This function sets the reference voltage generated by the voltage generator -//! to be used by other peripherals. This reference voltage will only be valid -//! while the REF module is in control. -//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns \b REF_BUSY, -//! this function will have no effect. -//! -//! \return none -// -//***************************************************************************** -extern void REF_A_setReferenceVoltage(uint_fast8_t referenceVoltageSelect); - -//***************************************************************************** -// -//! Disables the internal temperature sensor to save power consumption. -//! -//! This function is used to turn off the internal temperature sensor to save -//! on power consumption. The temperature sensor is enabled by default. Please -//! note, that giving ADC12 module control over the REF module, the state of the -//! temperature sensor is dependent on the controls of the ADC12 module. -//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns -//! \b REF_A_BUSY, this function will have no effect. -//! -//! Modified bits are \b REFTCOFF of \b REFCTL0 register. -//! \return none -// -//***************************************************************************** -extern void REF_A_disableTempSensor(void); - -//***************************************************************************** -// -//! Enables the internal temperature sensor. -//! -//! This function is used to turn on the internal temperature sensor to use by -//! other peripherals. The temperature sensor is enabled by default. -//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns -//! \b REF_A_BUSY, this function will have no effect. -//! -//! Modified bits are \b REFTCOFF of \b REFCTL0 register. -//! -//! \return none -// -//***************************************************************************** -extern void REF_A_enableTempSensor(void); - -//***************************************************************************** -// -//! Outputs the reference voltage to an output pin. -//! -//! This function is used to output the reference voltage being generated to an -//! output pin. Please note, the output pin is device specific. Please note, -//! that giving ADC12 module control over the REF module, the state of the -//! reference voltage as an output to a pin is dependent on the controls of the -//! ADC12 module. -//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns -//! \b REF_A_BUSY, this function will have no effect. -//! -//! Modified bits are \b REFOUT of \b REFCTL0 register. -//! \return none -// -//***************************************************************************** -extern void REF_A_enableReferenceVoltageOutput(void); - -//***************************************************************************** -// -//! Disables the reference voltage as an output to a pin. -//! -//! This function is used to disables the reference voltage being generated to -//! be given to an output pin. -//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns -//! \b REF_A_BUSY, this function will have no effect. -//! -//! Modified bits are \b REFOUT of \b REFCTL0 register. -//! \return none -// -//***************************************************************************** -extern void REF_A_disableReferenceVoltageOutput(void); - -//***************************************************************************** -// -//! Enables the reference voltage to be used by peripherals. -//! -//! This function is used to enable the generated reference voltage to be used -//! other peripherals or by an output pin, if enabled. Please note, that giving -//! ADC12 module control over the REF module, the state of the reference voltage -//! is dependent on the controls of the ADC12 module. -//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns -//! REF_A_BUSY, this function will have no effect. -//! -//! Modified bits are \b REFON of \b REFCTL0 register. -//! \return none -// -//***************************************************************************** -extern void REF_A_enableReferenceVoltage(void); - -//***************************************************************************** -// -//! Disables the reference voltage. -//! -//! This function is used to disable the generated reference voltage. -//! Please note, if the \link REF_A_isRefGenBusy() \endlink returns -//! \b REF_A_BUSY, this function will have no effect. -//! -//! Modified bits are \b REFON of \b REFCTL0 register. -//! \return none -// -//***************************************************************************** -extern void REF_A_disableReferenceVoltage(void); - -//***************************************************************************** -// -//! Returns the bandgap mode of the REF module. -//! -//! This function is used to return the bandgap mode of the REF module, -//! requested by the peripherals using the bandgap. If a peripheral requests -//! static mode, then the bandgap mode will be static for all modules, whereas -//! if all of the peripherals using the bandgap request sample mode, then that -//! will be the mode returned. Sample mode allows the bandgap to be active only -//! when necessary to save on power consumption, static mode requires the -//! bandgap to be active until no peripherals are using it anymore. -//! -//! \return The bandgap mode of the REF module: -//! - \b REF_A_STATICMODE if the bandgap is operating in static mode -//! - \b REF_A_SAMPLEMODE if the bandgap is operating in sample mode -// -//***************************************************************************** -extern uint_fast8_t REF_A_getBandgapMode(void); - -//***************************************************************************** -// -//! Returns the active status of the bandgap in the REF module. -//! -//! This function is used to return the active status of the bandgap in the REF -//! module. If the bandgap is in use by a peripheral, then the status will be -//! seen as active. -//! -//! \return true if the bandgap is being used, false otherwise -// -//***************************************************************************** -extern bool REF_A_isBandgapActive(void); - -//***************************************************************************** -// -//! Returns the busy status of the reference generator in the REF module. -//! -//! This function is used to return the busy status of the reference generator -//! in the REF module. If the ref. generator is in use by a peripheral, then the -//! status will be seen as busy. -//! -//! \return true if the reference generator is being used, false otherwise. -//***************************************************************************** -extern bool REF_A_isRefGenBusy(void); - -//***************************************************************************** -// -//! Returns the active status of the reference generator in the REF module. -//! -//! This function is used to return the active status of the reference generator -//! in the REF module. If the ref. generator is on and ready to use, then the -//! status will be seen as active. -//! -//! \return true if the reference generator is active, false otherwise. -// -//***************************************************************************** -extern bool REF_A_isRefGenActive(void); - -//***************************************************************************** -// -//! Returns the busy status of the reference generator in the REF module. -//! -//! This function is used to return the buys status of the buffered bandgap -//! voltage in the REF module. If the ref. generator is on and ready to use, -//! then the status will be seen as active. -//! -//! \return true if the buffered bandgap voltage is ready to be used, false -//! otherwise -// -//***************************************************************************** -extern bool REF_A_getBufferedBandgapVoltageStatus(void); - -//***************************************************************************** -// -//! Returns the busy status of the variable reference voltage in the REF module. -//! -//! This function is used to return the buys status of the variable reference -//! voltage in the REF module. If the ref. generator is on and ready to use, -//! then the status will be seen as active. -//! -//! \return true if the variable bandgap voltage is ready to be used, false -//! otherwise -// -//***************************************************************************** -extern bool REF_A_getVariableReferenceVoltageStatus(void); - -//***************************************************************************** -// -//! Enables the one-time trigger of the reference voltage. -//! -//! Triggers the one-time generation of the variable reference voltage. Once -//! the reference voltage request is set, this bit is cleared by hardware -//! -//! Modified bits are \b REFGENOT of \b REFCTL0 register. -//! -//! \return none -// -//***************************************************************************** -extern void REF_A_setReferenceVoltageOneTimeTrigger(void); - -//***************************************************************************** -// -//! Enables the one-time trigger of the buffered bandgap voltage. -//! -//! Triggers the one-time generation of the buffered bandgap voltage. Once -//! the buffered bandgap voltage request is set, this bit is cleared by hardware -//! -//! Modified bits are \b RefGOT of \b REFCTL0 register. -//! -//! \return none -// -//***************************************************************************** -extern void REF_A_setBufferedBandgapVoltageOneTimeTrigger(void); - -/* Defines for future devices that might have multiple instances */ -#define REF_A_setReferenceVoltageMultipleInstance(a,b) REF_A_setReferenceVoltage(b) -#define REF_A_disableTempSensorMultipleInstance(a) REF_A_disableTempSensor() -#define REF_A_enableTempSensorMultipleInstance(a) REF_A_enableTempSensor() -#define REF_A_enableReferenceVoltageOutputMultipleInstance(a) REF_A_enableReferenceVoltageOutput() -#define REF_A_disableReferenceVoltageOutputMultipleInstance(a) REF_A_disableReferenceVoltageOutput() -#define REF_A_enableReferenceVoltageMultipleInstance(a) REF_A_enableReferenceVoltage() -#define REF_A_disableReferenceVoltageMultipleInstance(a) REF_A_disableReferenceVoltage() -#define REF_A_getBandgapModeMultipleInstance(a) REF_A_getBandgapMode() -#define REF_A_isBandgapActiveMultipleInstance(a) REF_A_isBandgapActive() -#define REF_A_isRefGenBusyMultipleInstance(a) REF_A_isRefGenBusy() -#define REF_A_isRefGenActiveMultipleInstance(a) REF_A_isRefGenActive() -#define REF_A_getBufferedBandgapVoltageStatusMultipleInstance(a) REF_A_getBufferedBandgapVoltageStatus() -#define REF_A_getVariableReferenceVoltageStatusMultipleInstance(a) REF_A_getVariableReferenceVoltageStatus() -#define REF_A_setReferenceVoltageOneTimeTriggerMultipleInstance(a) REF_A_setReferenceVoltageOneTimeTrigger() -#define REF_A_setBufferedBandgapVoltageOneTimeTriggerMultipleInstance(a) REF_A_setBufferedBandgapVoltageOneTimeTrigger() - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif // __REF_A_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/reset.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/reset.c deleted file mode 100644 index 307b1374fd9..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/reset.c +++ /dev/null @@ -1,94 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include - -void ResetCtl_initiateSoftReset(void) -{ - RSTCTL->RESET_REQ |= (RESET_KEY | RESET_SOFT_RESET); -} - -void ResetCtl_initiateSoftResetWithSource(uint32_t source) -{ - RSTCTL->SOFTRESET_SET |= (source); -} - -uint32_t ResetCtl_getSoftResetSource(void) -{ - return RSTCTL->SOFTRESET_STAT; -} - -void ResetCtl_clearSoftResetSource(uint32_t mask) -{ - RSTCTL->SOFTRESET_CLR |= mask; -} - -void ResetCtl_initiateHardReset(void) -{ - RSTCTL->RESET_REQ |= (RESET_KEY | RESET_HARD_RESET); -} - -void ResetCtl_initiateHardResetWithSource(uint32_t source) -{ - RSTCTL->HARDRESET_SET |= (source); -} - -uint32_t ResetCtl_getHardResetSource(void) -{ - return RSTCTL->HARDRESET_STAT; -} - -void ResetCtl_clearHardResetSource(uint32_t mask) -{ - RSTCTL->HARDRESET_CLR |= mask; -} - -uint32_t ResetCtl_getPSSSource(void) -{ - return RSTCTL->PSSRESET_STAT; -} - -void ResetCtl_clearPSSFlags(void) -{ - RSTCTL->PSSRESET_CLR |= RSTCTL_PSSRESET_CLR_CLR; -} - -uint32_t ResetCtl_getPCMSource(void) -{ - return RSTCTL->PCMRESET_STAT; -} - -void ResetCtl_clearPCMFlags(void) -{ - RSTCTL->PCMRESET_CLR |= RSTCTL_PCMRESET_CLR_CLR; -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/reset.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/reset.h deleted file mode 100644 index c34af05ef58..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/reset.h +++ /dev/null @@ -1,338 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __RESET_H__ -#define __RESET_H__ - -//***************************************************************************** -// -//! \addtogroup reset_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -//***************************************************************************** -// -// Control specific variables -// -//***************************************************************************** -#define RESET_KEY 0x6900 -#define RESET_HARD_RESET RSTCTL_RESET_REQ_HARD_REQ -#define RESET_SOFT_RESET RSTCTL_RESET_REQ_SOFT_REQ - -#define RESET_SRC_0 RSTCTL_HARDRESET_CLR_SRC0 -#define RESET_SRC_1 RSTCTL_HARDRESET_CLR_SRC1 -#define RESET_SRC_2 RSTCTL_HARDRESET_CLR_SRC2 -#define RESET_SRC_3 RSTCTL_HARDRESET_CLR_SRC3 -#define RESET_SRC_4 RSTCTL_HARDRESET_CLR_SRC4 -#define RESET_SRC_5 RSTCTL_HARDRESET_CLR_SRC5 -#define RESET_SRC_6 RSTCTL_HARDRESET_CLR_SRC6 -#define RESET_SRC_7 RSTCTL_HARDRESET_CLR_SRC7 -#define RESET_SRC_8 RSTCTL_HARDRESET_CLR_SRC8 -#define RESET_SRC_9 RSTCTL_HARDRESET_CLR_SRC9 -#define RESET_SRC_10 RSTCTL_HARDRESET_CLR_SRC10 -#define RESET_SRC_11 RSTCTL_HARDRESET_CLR_SRC11 -#define RESET_SRC_12 RSTCTL_HARDRESET_CLR_SRC12 -#define RESET_SRC_13 RSTCTL_HARDRESET_CLR_SRC13 -#define RESET_SRC_14 RSTCTL_HARDRESET_CLR_SRC14 -#define RESET_SRC_15 RSTCTL_HARDRESET_CLR_SRC15 - -#define RESET_VCCDET RSTCTL_PSSRESET_STAT_VCCDET -#define RESET_SVSH_TRIP RSTCTL_PSSRESET_STAT_SVSMH -#define RESET_BGREF_BAD RSTCTL_PSSRESET_STAT_BGREF - -#define RESET_LPM35 RSTCTL_PCMRESET_STAT_LPM35 -#define RESET_LPM45 RSTCTL_PCMRESET_STAT_LPM45 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! Initiates a soft system reset. -//! -//! \return none -// -//***************************************************************************** -extern void ResetCtl_initiateSoftReset(void); - -//***************************************************************************** -// -//! Initiates a soft system reset with a particular source given. This source -//! is generic and can be assigned by the user. -//! -//! \param source Source of the reset. Valid values are: -//! - \b RESET_SRC_0, -//! - \b RESET_SRC_1, -//! - \b RESET_SRC_2, -//! - \b RESET_SRC_3, -//! - \b RESET_SRC_4, -//! - \b RESET_SRC_5, -//! - \b RESET_SRC_6, -//! - \b RESET_SRC_7, -//! - \b RESET_SRC_8, -//! - \b RESET_SRC_9, -//! - \b RESET_SRC_10, -//! - \b RESET_SRC_11, -//! - \b RESET_SRC_12, -//! - \b RESET_SRC_13, -//! - \b RESET_SRC_14, -//! - \b RESET_SRC_15 -//! -//! \return none -// -//***************************************************************************** -extern void ResetCtl_initiateSoftResetWithSource(uint32_t source); - -//***************************************************************************** -// -//! Retrieves previous soft reset sources -//! -//! \return the bitwise or of previous reset sources. These sources must be -//! cleared using the \link ResetCtl_clearSoftResetSource \endlink function to -//! be cleared. -//! Possible values include: -//! - \b RESET_SRC_0, -//! - \b RESET_SRC_1, -//! - \b RESET_SRC_2, -//! - \b RESET_SRC_3, -//! - \b RESET_SRC_4, -//! - \b RESET_SRC_5, -//! - \b RESET_SRC_6, -//! - \b RESET_SRC_7, -//! - \b RESET_SRC_8, -//! - \b RESET_SRC_9, -//! - \b RESET_SRC_10, -//! - \b RESET_SRC_11, -//! - \b RESET_SRC_12, -//! - \b RESET_SRC_13, -//! - \b RESET_SRC_14, -//! - \b RESET_SRC_15 -// -//***************************************************************************** -extern uint32_t ResetCtl_getSoftResetSource(void); - -//***************************************************************************** -// -//! Clears the reset sources associated with at soft reset -//! -//! \param mask - Bitwise OR of any of the following values: -//! - \b RESET_SRC_0, -//! - \b RESET_SRC_1, -//! - \b RESET_SRC_2, -//! - \b RESET_SRC_3, -//! - \b RESET_SRC_4, -//! - \b RESET_SRC_5, -//! - \b RESET_SRC_6, -//! - \b RESET_SRC_7, -//! - \b RESET_SRC_8, -//! - \b RESET_SRC_9, -//! - \b RESET_SRC_10, -//! - \b RESET_SRC_11, -//! - \b RESET_SRC_12, -//! - \b RESET_SRC_13, -//! - \b RESET_SRC_14, -//! - \b RESET_SRC_15 -//! -//! \return none -// -//***************************************************************************** -extern void ResetCtl_clearSoftResetSource(uint32_t mask); - -//***************************************************************************** -// -//! Initiates a hard system reset. -//! -//! \return none -// -//***************************************************************************** -extern void ResetCtl_initiateHardReset(void); - -//***************************************************************************** -// -//! Initiates a hard system reset with a particular source given. This source -//! is generic and can be assigned by the user. -//! -//! \param source - Valid values are one the following values: -//! - \b RESET_SRC_0, -//! - \b RESET_SRC_1, -//! - \b RESET_SRC_2, -//! - \b RESET_SRC_3, -//! - \b RESET_SRC_4, -//! - \b RESET_SRC_5, -//! - \b RESET_SRC_6, -//! - \b RESET_SRC_7, -//! - \b RESET_SRC_8, -//! - \b RESET_SRC_9, -//! - \b RESET_SRC_10, -//! - \b RESET_SRC_11, -//! - \b RESET_SRC_12, -//! - \b RESET_SRC_13, -//! - \b RESET_SRC_14, -//! - \b RESET_SRC_15 -//! \return none -// -//***************************************************************************** -extern void ResetCtl_initiateHardResetWithSource(uint32_t source); - -//***************************************************************************** -// -//! Retrieves previous hard reset sources -//! -//! \return the bitwise or of previous reset sources. These sources must be -//! cleared using the \link ResetCtl_clearHardResetSource \endlink function to -//! be cleared. -//! Possible values include: -//! - \b RESET_SRC_0, -//! - \b RESET_SRC_1, -//! - \b RESET_SRC_2, -//! - \b RESET_SRC_3, -//! - \b RESET_SRC_4, -//! - \b RESET_SRC_5, -//! - \b RESET_SRC_6, -//! - \b RESET_SRC_7, -//! - \b RESET_SRC_8, -//! - \b RESET_SRC_9, -//! - \b RESET_SRC_10, -//! - \b RESET_SRC_11, -//! - \b RESET_SRC_12, -//! - \b RESET_SRC_13, -//! - \b RESET_SRC_14, -//! - \b RESET_SRC_15 -// -//***************************************************************************** -extern uint32_t ResetCtl_getHardResetSource(void); - -//***************************************************************************** -// -//! Clears the reset sources associated with at hard reset -//! -//! \param mask - Bitwise OR of any of the following values: -//! - \b RESET_SRC_0, -//! - \b RESET_SRC_1, -//! - \b RESET_SRC_2, -//! - \b RESET_SRC_3, -//! - \b RESET_SRC_4, -//! - \b RESET_SRC_5, -//! - \b RESET_SRC_6, -//! - \b RESET_SRC_7, -//! - \b RESET_SRC_8, -//! - \b RESET_SRC_9, -//! - \b RESET_SRC_10, -//! - \b RESET_SRC_11, -//! - \b RESET_SRC_12, -//! - \b RESET_SRC_13, -//! - \b RESET_SRC_14, -//! - \b RESET_SRC_15 -//! -//! \return none -// -//***************************************************************************** -extern void ResetCtl_clearHardResetSource(uint32_t mask); - -//***************************************************************************** -// -//! Indicates the last cause of a power-on reset (POR) due to PSS operation. -//! Note that the bits returned from this function may be set in different -//! combinations. When a cold power up occurs, the value of all the values ORed -//! together could be returned as a cold power up causes these conditions. -//! -//! \return Bitwise OR of any of the following values: -//! - RESET_VCCDET, -//! - RESET_SVSH_TRIP, -//! - RESET_BGREF_BAD -// -//***************************************************************************** -extern uint32_t ResetCtl_getPSSSource(void); - -//***************************************************************************** -// -//! Clears the PSS reset source flags -//! -//! \return none -// -//***************************************************************************** -extern void ResetCtl_clearPSSFlags(void); - -//***************************************************************************** -// -//! Indicates the last cause of a power-on reset (POR) due to PCM operation. -//! -//! \return Bitwise OR of any of the following values: -//! - RESET_LPM35, -//! - RESET_LPM45 -// -//***************************************************************************** -extern uint32_t ResetCtl_getPCMSource(void); - -//***************************************************************************** -// -//! Clears the corresponding PCM reset source flags -//! -//! \return none -// -//***************************************************************************** -extern void ResetCtl_clearPCMFlags(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif // __RESET_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/rom.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/rom.h deleted file mode 100644 index 8debd57a341..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/rom.h +++ /dev/null @@ -1,2771 +0,0 @@ -//***************************************************************************** -// -// rom.h - Macros to facilitate calling functions in the ROM. -// -// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved. -// TI Information - Selective Disclosure -// -//***************************************************************************** -// - -#ifndef __ROM_H__ -#define __ROM_H__ - -//***************************************************************************** -// -// Pointers to the main API tables. -// -//***************************************************************************** -#define ROM_APITABLE ((unsigned long *)0x02000800) -#define ROM_VERSION (ROM_APITABLE[0]) -#define ROM_ADC14TABLE ((unsigned long *)(ROM_APITABLE[1])) -#define ROM_AES256TABLE ((unsigned long *)(ROM_APITABLE[2])) -#define ROM_COMPTABLE ((unsigned long *)(ROM_APITABLE[3])) -#define ROM_CRC32TABLE ((unsigned long *)(ROM_APITABLE[4])) -#define ROM_CSTABLE ((unsigned long *)(ROM_APITABLE[5])) -#define ROM_DMATABLE ((unsigned long *)(ROM_APITABLE[6])) -#define ROM_FLASHCTLTABLE ((unsigned long *)(ROM_APITABLE[7])) -#define ROM_FPUTABLE ((unsigned long *)(ROM_APITABLE[8])) -#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[9])) -#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[10])) -#define ROM_INTTABLE ((unsigned long *)(ROM_APITABLE[11])) -#define ROM_MPUTABLE ((unsigned long *)(ROM_APITABLE[12])) -#define ROM_PCMTABLE ((unsigned long *)(ROM_APITABLE[13])) -#define ROM_PMAPTABLE ((unsigned long *)(ROM_APITABLE[14])) -#define ROM_PSSTABLE ((unsigned long *)(ROM_APITABLE[15])) -#define ROM_REFTABLE ((unsigned long *)(ROM_APITABLE[16])) -#define ROM_RESETCTLTABLE ((unsigned long *)(ROM_APITABLE[17])) -#define ROM_RTCTABLE ((unsigned long *)(ROM_APITABLE[18])) -#define ROM_SPITABLE ((unsigned long *)(ROM_APITABLE[19])) -#define ROM_SYSCTLTABLE ((unsigned long *)(ROM_APITABLE[20])) -#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[21])) -#define ROM_TIMER_ATABLE ((unsigned long *)(ROM_APITABLE[22])) -#define ROM_TIMER32TABLE ((unsigned long *)(ROM_APITABLE[23])) -#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[24])) -#define ROM_WDTTABLE ((unsigned long *)(ROM_APITABLE[25])) -#define ROM_SYSCTLATABLE ((unsigned long *)(ROM_APITABLE[26])) -#define ROM_FLASHCTLATABLE ((unsigned long *)(ROM_APITABLE[27])) -#define ROM_LCDFTABLE ((unsigned long *)(ROM_APITABLE[28])) - -#if defined(__MSP432P401R__) || defined(__MSP432P401M__) -#define TARGET_IS_MSP432P4XX -#else -#define TARGET_IS_MSP432P4XX_NEXT -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the ADC14 API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_enableModule \ - ((void (*)(void))ROM_ADC14TABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_disableModule \ - ((bool (*)(void))ROM_ADC14TABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_initModule \ - ((bool (*)(uint32_t clockSource, \ - uint32_t clockPredivider, \ - uint32_t clockDivider, \ - uint32_t internalChannelMask))ROM_ADC14TABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_setResolution \ - ((void (*)(uint32_t resolution))ROM_ADC14TABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_getResolution \ - ((uint_fast32_t (*)(void))ROM_ADC14TABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_setSampleHoldTrigger \ - ((bool (*)(uint32_t source, \ - bool invertSignal))ROM_ADC14TABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_setSampleHoldTime \ - ((bool (*)(uint32_t firstPulseWidth, \ - uint32_t secondPulseWidth))ROM_ADC14TABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_configureMultiSequenceMode \ - ((bool (*)(uint32_t memoryStart, \ - uint32_t memoryEnd, \ - bool repeatMode))ROM_ADC14TABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_configureSingleSampleMode \ - ((bool (*)(uint32_t memoryDestination, \ - bool repeatMode))ROM_ADC14TABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_enableConversion \ - ((bool (*)(void))ROM_ADC14TABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_disableConversion \ - ((void (*)(void))ROM_ADC14TABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_isBusy \ - ((bool (*)(void))ROM_ADC14TABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_configureConversionMemory \ - ((bool (*)(uint32_t memorySelect, \ - uint32_t refSelect, \ - uint32_t channelSelect, \ - bool differntialMode))ROM_ADC14TABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_enableComparatorWindow \ - ((bool (*)(uint32_t memorySelect, \ - uint32_t windowSelect))ROM_ADC14TABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_disableComparatorWindow \ - ((bool (*)(uint32_t memorySelect))ROM_ADC14TABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_setComparatorWindowValue \ - ((bool (*)(uint32_t window, \ - int16_t low, \ - int16_t high))ROM_ADC14TABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_setResultFormat \ - ((bool (*)(uint32_t resultFormat))ROM_ADC14TABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_getResult \ - ((uint_fast16_t (*)(uint32_t memorySelect))ROM_ADC14TABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_getMultiSequenceResult \ - ((void (*)(uint16_t* res))ROM_ADC14TABLE[18]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_getResultArray \ - ((void (*)(uint32_t memoryStart, \ - uint32_t memoryEnd, \ - uint16_t* res))ROM_ADC14TABLE[19]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_enableReferenceBurst \ - ((bool (*)(void))ROM_ADC14TABLE[20]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_disableReferenceBurst \ - ((bool (*)(void))ROM_ADC14TABLE[21]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_setPowerMode \ - ((bool (*)(uint32_t powerMode))ROM_ADC14TABLE[22]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_enableInterrupt \ - ((void (*)(uint_fast64_t mask))ROM_ADC14TABLE[23]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_disableInterrupt \ - ((void (*)(uint_fast64_t mask))ROM_ADC14TABLE[24]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_getInterruptStatus \ - ((uint_fast64_t (*)(void))ROM_ADC14TABLE[25]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_getEnabledInterruptStatus \ - ((uint_fast64_t (*)(void))ROM_ADC14TABLE[26]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_clearInterruptFlag \ - ((void (*)(uint_fast64_t mask))ROM_ADC14TABLE[27]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_toggleConversionTrigger \ - ((bool (*)(void))ROM_ADC14TABLE[28]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_enableSampleTimer \ - ((bool (*)(uint32_t multiSampleConvert))ROM_ADC14TABLE[29]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ADC14_disableSampleTimer \ - ((bool (*)(void))ROM_ADC14TABLE[30]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the AES256 API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_setCipherKey \ - ((bool (*)(uint32_t moduleInstance, \ - const uint8_t *cipherKey, \ - uint_fast16_t keyLength))ROM_AES256TABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_encryptData \ - ((void (*)(uint32_t moduleInstance, \ - const uint8_t *data, \ - uint8_t *encryptedData))ROM_AES256TABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_decryptData \ - ((void (*)(uint32_t moduleInstance, \ - const uint8_t *data, \ - uint8_t *decryptedData))ROM_AES256TABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_setDecipherKey \ - ((bool (*)(uint32_t moduleInstance, \ - const uint8_t *cipherKey, \ - uint_fast16_t keyLength))ROM_AES256TABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_reset \ - ((void (*)(uint32_t moduleInstance))ROM_AES256TABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_startEncryptData \ - ((void (*)(uint32_t moduleInstance, \ - const uint8_t *data))ROM_AES256TABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_startDecryptData \ - ((void (*)(uint32_t moduleInstance, \ - const uint8_t *data))ROM_AES256TABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_startSetDecipherKey \ - ((bool (*)(uint32_t moduleInstance, \ - const uint8_t *cipherKey, \ - uint_fast16_t keyLength))ROM_AES256TABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_getDataOut \ - ((bool (*)(uint32_t moduleInstance, \ - uint8_t *outputData))ROM_AES256TABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_isBusy \ - ((bool (*)(uint32_t moduleInstance))ROM_AES256TABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_clearErrorFlag \ - ((void (*)(uint32_t moduleInstance))ROM_AES256TABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_getErrorFlagStatus \ - ((uint32_t (*)(uint32_t moduleInstance))ROM_AES256TABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_clearInterruptFlag \ - ((void (*)(uint32_t moduleInstance))ROM_AES256TABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_getInterruptStatus \ - ((uint32_t (*)(uint32_t moduleInstance))ROM_AES256TABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_enableInterrupt \ - ((void (*)(uint32_t moduleInstance))ROM_AES256TABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_disableInterrupt \ - ((void (*)(uint32_t moduleInstance))ROM_AES256TABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_AES256_getInterruptFlagStatus \ - ((uint32_t (*)(uint32_t moduleInstance))ROM_AES256TABLE[18]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Comp API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_initModule \ - ((bool (*)(uint32_t comparator, \ - const COMP_E_Config *config))ROM_COMPTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_setReferenceVoltage \ - ((void (*)(uint32_t comparator, \ - uint_fast16_t supplyVoltageReferenceBase, \ - uint_fast16_t lowerLimitSupplyVoltageFractionOf32, \ - uint_fast16_t upperLimitSupplyVoltageFractionOf32))ROM_COMPTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_setReferenceAccuracy \ - ((void (*)(uint32_t comparator, \ - uint_fast16_t referenceAccuracy))ROM_COMPTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_setPowerMode \ - ((void (*)(uint32_t comparator, \ - uint_fast16_t powerMode))ROM_COMPTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_enableModule \ - ((void (*)(uint32_t comparator))ROM_COMPTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_disableModule \ - ((void (*)(uint32_t comparator))ROM_COMPTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_shortInputs \ - ((void (*)(uint32_t comparator))ROM_COMPTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_unshortInputs \ - ((void (*)(uint32_t comparator))ROM_COMPTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_disableInputBuffer \ - ((void (*)(uint32_t comparator, \ - uint_fast16_t inputPort))ROM_COMPTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_enableInputBuffer \ - ((void (*)(uint32_t comparator, \ - uint_fast16_t inputPort))ROM_COMPTABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_swapIO \ - ((void (*)(uint32_t comparator))ROM_COMPTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_outputValue \ - ((uint8_t (*)(uint32_t comparator))ROM_COMPTABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_enableInterrupt \ - ((void (*)(uint32_t comparator, \ - uint_fast16_t mask))ROM_COMPTABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_disableInterrupt \ - ((void (*)(uint32_t comparator, \ - uint_fast16_t mask))ROM_COMPTABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_clearInterruptFlag \ - ((void (*)(uint32_t comparator, \ - uint_fast16_t mask))ROM_COMPTABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_getInterruptStatus \ - ((uint_fast16_t (*)(uint32_t comparator))ROM_COMPTABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_getEnabledInterruptStatus \ - ((uint_fast16_t (*)(uint32_t comparator))ROM_COMPTABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_setInterruptEdgeDirection \ - ((void (*)(uint32_t comparator, \ - uint_fast8_t edgeDirection))ROM_COMPTABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_COMP_E_toggleInterruptEdgeDirection \ - ((void (*)(uint32_t comparator))ROM_COMPTABLE[18]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the CRC32 API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CRC32_setSeed \ - ((void (*)(uint32_t seed, \ - uint_fast8_t crcType))ROM_CRC32TABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CRC32_set8BitData \ - ((void (*)(uint8_t dataIn, \ - uint_fast8_t crcType))ROM_CRC32TABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CRC32_set16BitData \ - ((void (*)(uint16_t dataIn, \ - uint_fast8_t crcType))ROM_CRC32TABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CRC32_set32BitData \ - ((void (*)(uint32_t dataIn))ROM_CRC32TABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CRC32_set8BitDataReversed \ - ((void (*)(uint8_t dataIn, \ - uint_fast8_t crcType))ROM_CRC32TABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CRC32_set16BitDataReversed \ - ((void (*)(uint16_t dataIn, \ - uint_fast8_t crcType))ROM_CRC32TABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CRC32_set32BitDataReversed \ - ((void (*)(uint32_t dataIn))ROM_CRC32TABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CRC32_getResult \ - ((uint32_t (*)(uint_fast8_t crcType))ROM_CRC32TABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CRC32_getResultReversed \ - ((uint32_t (*)(uint_fast8_t crcType))ROM_CRC32TABLE[8]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the CS API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_initClockSignal \ - ((void (*)(uint32_t selectedClockSignal, \ - uint32_t clockSource, \ - uint32_t clockSourceDivider))ROM_CSTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_setReferenceOscillatorFrequency \ - ((void (*)(uint8_t referenceFrequency))ROM_CSTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_enableClockRequest \ - ((void (*)(uint32_t selectClock))ROM_CSTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_disableClockRequest \ - ((void (*)(uint32_t selectClock))ROM_CSTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_setDCOCenteredFrequency \ - ((void (*)(uint32_t dcoFreq))ROM_CSTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_tuneDCOFrequency \ - ((void (*)(int16_t tuneParameter))ROM_CSTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_enableDCOExternalResistor \ - ((void (*)(void))ROM_CSTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_disableDCOExternalResistor \ - ((void (*)(void))ROM_CSTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_enableInterrupt \ - ((void (*)(uint32_t flags))ROM_CSTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_disableInterrupt \ - ((void (*)(uint32_t flags))ROM_CSTABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_getEnabledInterruptStatus \ - ((uint32_t (*)(void))ROM_CSTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_getInterruptStatus \ - ((uint32_t (*)(void))ROM_CSTABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_setDCOFrequency \ - ((void (*)(uint32_t dcoFrequency))ROM_CSTABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_getDCOFrequency \ - ((uint32_t (*)(void))ROM_CSTABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_enableFaultCounter \ - ((void (*)(uint_fast8_t counterSelect))ROM_CSTABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_disableFaultCounter \ - ((void (*)(uint_fast8_t counterSelect))ROM_CSTABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_resetFaultCounter \ - ((void (*)(uint_fast8_t counterSelect))ROM_CSTABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_startFaultCounter \ - ((void (*)(uint_fast8_t counterSelect, \ - uint_fast8_t countValue))ROM_CSTABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_clearInterruptFlag \ - ((void (*)(uint32_t flags))ROM_CSTABLE[20]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_CS_setDCOExternalResistorCalibration \ - ((void (*)(uint_fast8_t uiCalData, \ - uint_fast8_t freqRange))ROM_CSTABLE[31]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the DMA API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_enableModule \ - ((void (*)(void))ROM_DMATABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_disableModule \ - ((void (*)(void))ROM_DMATABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_getErrorStatus \ - ((uint32_t (*)(void))ROM_DMATABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_clearErrorStatus \ - ((void (*)(void))ROM_DMATABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_enableChannel \ - ((void (*)(uint32_t channelNum))ROM_DMATABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_disableChannel \ - ((void (*)(uint32_t channelNum))ROM_DMATABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_isChannelEnabled \ - ((bool (*)(uint32_t channelNum))ROM_DMATABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_setControlBase \ - ((void (*)(void *controlTable))ROM_DMATABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_getControlBase \ - ((void* (*)(void))ROM_DMATABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_getControlAlternateBase \ - ((void* (*)(void))ROM_DMATABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_requestChannel \ - ((void (*)(uint32_t channelNum))ROM_DMATABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_enableChannelAttribute \ - ((void (*)(uint32_t channelNum, \ - uint32_t attr))ROM_DMATABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_disableChannelAttribute \ - ((void (*)(uint32_t channelNum, \ - uint32_t attr))ROM_DMATABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_getChannelAttribute \ - ((uint32_t (*)(uint32_t channelNum))ROM_DMATABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_setChannelControl \ - ((void (*)(uint32_t channelStructIndex, \ - uint32_t control))ROM_DMATABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_setChannelTransfer \ - ((void (*)(uint32_t channelStructIndex, \ - uint32_t mode, \ - void *srcAddr, \ - void *dstAddr, \ - uint32_t transferSize))ROM_DMATABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_setChannelScatterGather \ - ((void (*)(uint32_t channelNum, \ - uint32_t taskCount, \ - void *taskList, \ - uint32_t isPeriphSG))ROM_DMATABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_getChannelSize \ - ((uint32_t (*)(uint32_t channelStructIndex))ROM_DMATABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_getChannelMode \ - ((uint32_t (*)(uint32_t channelStructIndex))ROM_DMATABLE[18]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_assignChannel \ - ((void (*)(uint32_t mapping))ROM_DMATABLE[19]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_requestSoftwareTransfer \ - ((void (*)(uint32_t channel))ROM_DMATABLE[20]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_assignInterrupt \ - ((void (*)(uint32_t interruptNumber, \ - uint32_t channel))ROM_DMATABLE[21]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_enableInterrupt \ - ((void (*)(uint32_t interruptNumber))ROM_DMATABLE[22]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_disableInterrupt \ - ((void (*)(uint32_t interruptNumber))ROM_DMATABLE[23]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_getInterruptStatus \ - ((uint32_t (*)(void))ROM_DMATABLE[24]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_DMA_clearInterruptFlag \ - ((void (*)(uint32_t intChannel))ROM_DMATABLE[25]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Flash API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_enableReadBuffering \ - ((void (*)(uint_fast8_t memoryBank, \ - uint_fast8_t accessMethod))ROM_FLASHCTLTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_disableReadBuffering \ - ((void (*)(uint_fast8_t memoryBank, \ - uint_fast8_t accessMethod))ROM_FLASHCTLTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_unprotectSector \ - ((bool (*)(uint_fast8_t memorySpace, \ - uint32_t sectorMask))ROM_FLASHCTLTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_protectSector \ - ((bool (*)(uint_fast8_t memorySpace, \ - uint32_t sectorMask))ROM_FLASHCTLTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_isSectorProtected \ - ((bool (*)(uint_fast8_t memorySpace, \ - uint32_t sector))ROM_FLASHCTLTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_verifyMemory \ - ((bool (*)(void* verifyAddr, \ - uint32_t length, \ - uint_fast8_t pattern))ROM_FLASHCTLTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_performMassErase \ - ((bool (*)(void))ROM_FLASHCTLTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_eraseSector \ - ((bool (*)(uint32_t addr))ROM_FLASHCTLTABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_programMemory \ - ((bool (*)(void* src, \ - void* dest, \ - uint32_t length))ROM_FLASHCTLTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_setProgramVerification \ - ((void (*)(uint32_t verificationSetting))ROM_FLASHCTLTABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_clearProgramVerification \ - ((void (*)(uint32_t verificationSetting))ROM_FLASHCTLTABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_enableWordProgramming \ - ((void (*)(uint32_t mode))ROM_FLASHCTLTABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_disableWordProgramming \ - ((void (*)(void))ROM_FLASHCTLTABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_isWordProgrammingEnabled \ - ((uint32_t (*)(void))ROM_FLASHCTLTABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_enableInterrupt \ - ((void (*)(uint32_t flags))ROM_FLASHCTLTABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_disableInterrupt \ - ((void (*)(uint32_t flags))ROM_FLASHCTLTABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_getEnabledInterruptStatus \ - ((uint32_t (*)(void))ROM_FLASHCTLTABLE[18]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_getInterruptStatus \ - ((uint32_t (*)(void))ROM_FLASHCTLTABLE[19]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_clearInterruptFlag \ - ((void (*)(uint32_t flags))ROM_FLASHCTLTABLE[20]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_setWaitState \ - ((void (*)(uint32_t bank, \ - uint32_t waitState))ROM_FLASHCTLTABLE[21]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_getWaitState \ - ((uint32_t (*)(uint32_t bank))ROM_FLASHCTLTABLE[22]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_setReadMode \ - ((bool (*)(uint32_t flashBank, \ - uint32_t readMode))ROM_FLASHCTLTABLE[23]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_getReadMode \ - ((uint32_t (*)(uint32_t flashBank))ROM_FLASHCTLTABLE[24]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM___FlashCtl_remaskData8Post \ - ((uint8_t (*)(uint8_t data, \ - uint32_t addr))ROM_FLASHCTLTABLE[27]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM___FlashCtl_remaskData8Pre \ - ((uint8_t (*)(uint8_t data, \ - uint32_t addr))ROM_FLASHCTLTABLE[28]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM___FlashCtl_remaskData32Pre \ - ((uint32_t (*)(uint32_t data, \ - uint32_t addr))ROM_FLASHCTLTABLE[29]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM___FlashCtl_remaskData32Post \ - ((uint32_t (*)(uint32_t data, \ - uint32_t addr))ROM_FLASHCTLTABLE[30]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM___FlashCtl_remaskBurstDataPre \ - ((void (*)(uint32_t addr, \ - uint32_t size))ROM_FLASHCTLTABLE[31]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM___FlashCtl_remaskBurstDataPost \ - ((void (*)(uint32_t addr, \ - uint32_t size))ROM_FLASHCTLTABLE[32]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_initiateSectorErase \ - ((void (*)(uint32_t addr))ROM_FLASHCTLTABLE[33]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_FlashCtl_initiateMassErase \ - ((void (*)(void))ROM_FLASHCTLTABLE[34]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the FPU API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FPU_enableModule \ - ((void (*)(void))ROM_FPUTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FPU_disableModule \ - ((void (*)(void))ROM_FPUTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FPU_enableStacking \ - ((void (*)(void))ROM_FPUTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FPU_enableLazyStacking \ - ((void (*)(void))ROM_FPUTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FPU_disableStacking \ - ((void (*)(void))ROM_FPUTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FPU_setHalfPrecisionMode \ - ((void (*)(uint32_t mode))ROM_FPUTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FPU_setNaNMode \ - ((void (*)(uint32_t mode))ROM_FPUTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FPU_setFlushToZeroMode \ - ((void (*)(uint32_t mode))ROM_FPUTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FPU_setRoundingMode \ - ((void (*)(uint32_t mode))ROM_FPUTABLE[8]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the GPIO API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_setAsOutputPin \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins))ROM_GPIOTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_setOutputHighOnPin \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins))ROM_GPIOTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_setOutputLowOnPin \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins))ROM_GPIOTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_toggleOutputOnPin \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins))ROM_GPIOTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_setAsInputPinWithPullDownResistor \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins))ROM_GPIOTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_setAsInputPinWithPullUpResistor \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins))ROM_GPIOTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_setAsPeripheralModuleFunctionOutputPin \ - ((void (*)( uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins, \ - uint_fast8_t mode))ROM_GPIOTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_setAsPeripheralModuleFunctionInputPin \ - ((void (*)( uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins, \ - uint_fast8_t mode))ROM_GPIOTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_getInputPinValue \ - ((uint8_t (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins))ROM_GPIOTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_interruptEdgeSelect \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins, \ - uint_fast8_t edgeSelect))ROM_GPIOTABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_enableInterrupt \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins))ROM_GPIOTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_disableInterrupt \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins))ROM_GPIOTABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_getInterruptStatus \ - ((uint_fast16_t (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins))ROM_GPIOTABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_clearInterruptFlag \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins))ROM_GPIOTABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_setAsInputPin \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast16_t selectedPins))ROM_GPIOTABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_getEnabledInterruptStatus \ - ((uint_fast16_t (*)(uint_fast8_t selectedPort))ROM_GPIOTABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_setDriveStrengthHigh \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast8_t selectedPins))ROM_GPIOTABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_GPIO_setDriveStrengthLow \ - ((void (*)(uint_fast8_t selectedPort, \ - uint_fast8_t selectedPins))ROM_GPIOTABLE[17]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the I2C API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_initMaster \ - ((void (*)(uint32_t moduleInstance, \ - const eUSCI_I2C_MasterConfig *config))ROM_I2CTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_initSlave \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast16_t slaveAddress, \ - uint_fast8_t slaveAddressOffset, \ - uint32_t slaveOwnAddressEnable))ROM_I2CTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_enableModule \ - ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_disableModule \ - ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_setSlaveAddress \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast16_t slaveAddress))ROM_I2CTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_setMode \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast8_t mode))ROM_I2CTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_slavePutData \ - ((void (*)(uint32_t moduleInstance, \ - uint8_t transmitData))ROM_I2CTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_slaveGetData \ - ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_isBusBusy \ - ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterSendSingleByte \ - ((void (*)(uint32_t moduleInstance, \ - uint8_t txData))ROM_I2CTABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterSendMultiByteNext \ - ((void (*)(uint32_t moduleInstance, \ - uint8_t txData))ROM_I2CTABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterSendMultiByteNextWithTimeout \ - ((bool (*)(uint32_t moduleInstance, \ - uint8_t txData, \ - uint32_t timeout))ROM_I2CTABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterSendMultiByteStop \ - ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterSendMultiByteStopWithTimeout \ - ((bool (*)(uint32_t moduleInstance, \ - uint32_t timeout))ROM_I2CTABLE[18]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterReceiveStart \ - ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[19]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterReceiveMultiByteNext \ - ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[20]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterReceiveMultiByteFinish \ - ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[21]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterReceiveMultiByteFinishWithTimeout \ - ((bool (*)(uint32_t moduleInstance, \ - uint8_t *txData, \ - uint32_t timeout))ROM_I2CTABLE[22]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterReceiveMultiByteStop \ - ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[23]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterReceiveSingleByte \ - ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[24]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterReceiveSingle \ - ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[25]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_getReceiveBufferAddressForDMA \ - ((uint32_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[26]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_getTransmitBufferAddressForDMA \ - ((uint32_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[27]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterIsStopSent \ - ((uint8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[28]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterIsStartSent \ - ((bool (*)(uint32_t moduleInstance))ROM_I2CTABLE[29]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_masterSendStart \ - ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[30]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_enableMultiMasterMode \ - ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[31]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_disableMultiMasterMode \ - ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[32]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_enableInterrupt \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast16_t mask))ROM_I2CTABLE[33]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_disableInterrupt \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast16_t mask))ROM_I2CTABLE[34]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_clearInterruptFlag \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast16_t mask))ROM_I2CTABLE[35]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_getInterruptStatus \ - ((uint_fast16_t (*)(uint32_t moduleInstance, \ - uint16_t mask))ROM_I2CTABLE[36]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_getEnabledInterruptStatus \ - ((uint_fast16_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[37]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_getMode \ - ((uint_fast8_t (*)(uint32_t moduleInstance))ROM_I2CTABLE[38]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_I2C_slaveSendNAK \ - ((void (*)(uint32_t moduleInstance))ROM_I2CTABLE[41]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Interrupt API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_enableMaster \ - ((bool (*)(void))ROM_INTTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_disableMaster \ - ((bool (*)(void))ROM_INTTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_setPriorityGrouping \ - ((void (*)(uint32_t bits))ROM_INTTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_getPriorityGrouping \ - ((uint32_t (*)(void))ROM_INTTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_setPriority \ - ((void (*)(uint32_t interruptNumber, \ - uint8_t priority))ROM_INTTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_getPriority \ - ((uint8_t (*)(uint32_t interruptNumber))ROM_INTTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_enableInterrupt \ - ((void (*)(uint32_t interruptNumber))ROM_INTTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_disableInterrupt \ - ((void (*)(uint32_t interruptNumber))ROM_INTTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_isEnabled \ - ((bool (*)(uint32_t interruptNumber))ROM_INTTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_pendInterrupt \ - ((void (*)(uint32_t interruptNumber))ROM_INTTABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_setPriorityMask \ - ((void (*)(uint8_t priorityMask))ROM_INTTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_getPriorityMask \ - ((uint8_t (*)(void))ROM_INTTABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_setVectorTableAddress \ - ((void (*)(uint32_t addr))ROM_INTTABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_getVectorTableAddress \ - ((uint32_t (*)(void))ROM_INTTABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_enableSleepOnIsrExit \ - ((void (*)(void))ROM_INTTABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_disableSleepOnIsrExit \ - ((void (*)(void))ROM_INTTABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Interrupt_unpendInterrupt \ - ((void (*)(uint32_t interruptNumber))ROM_INTTABLE[18]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the MPU API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_MPU_enableModule \ - ((void (*)(uint32_t mpuConfig))ROM_MPUTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_MPU_disableModule \ - ((void (*)(void))ROM_MPUTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_MPU_getRegionCount \ - ((uint32_t (*)(void))ROM_MPUTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_MPU_enableRegion \ - ((void (*)(uint32_t region))ROM_MPUTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_MPU_disableRegion \ - ((void (*)(uint32_t region))ROM_MPUTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_MPU_setRegion \ - ((void (*)(uint32_t region, \ - uint32_t addr, \ - uint32_t flags))ROM_MPUTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_MPU_getRegion \ - ((void (*)(uint32_t region, \ - uint32_t *addr, \ - uint32_t *pflags))ROM_MPUTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_MPU_enableInterrupt \ - ((void (*)(void))ROM_MPUTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_MPU_disableInterrupt \ - ((void (*)(void))ROM_MPUTABLE[8]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the PCM API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_setCoreVoltageLevel \ - ((bool (*)(uint_fast8_t voltageLevel))ROM_PCMTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_getCoreVoltageLevel \ - ((uint8_t (*)(void))ROM_PCMTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_setCoreVoltageLevelWithTimeout \ - ((bool (*)(uint_fast8_t voltageLevel, \ - uint32_t timeOut))ROM_PCMTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_setPowerMode \ - ((bool (*)(uint_fast8_t powerMode))ROM_PCMTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_setPowerModeWithTimeout \ - ((bool (*)(uint_fast8_t powerMode, \ - uint32_t timeOut))ROM_PCMTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_getPowerMode \ - ((uint8_t (*)(void))ROM_PCMTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_setPowerState \ - ((bool (*)(uint_fast8_t powerState))ROM_PCMTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_setPowerStateWithTimeout \ - ((bool (*)(uint_fast8_t powerState, \ - uint32_t timeout))ROM_PCMTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_getPowerState \ - ((uint8_t (*)(void))ROM_PCMTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PCM_shutdownDevice \ - ((bool (*)(uint32_t shutdownMode))ROM_PCMTABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PCM_gotoLPM0 \ - ((bool (*)(void))ROM_PCMTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_gotoLPM3 \ - ((bool (*)(void))ROM_PCMTABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PCM_enableInterrupt \ - ((void (*)(uint32_t flags))ROM_PCMTABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PCM_disableInterrupt \ - ((void (*)(uint32_t flags))ROM_PCMTABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PCM_getInterruptStatus \ - ((uint32_t (*)(void))ROM_PCMTABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PCM_getEnabledInterruptStatus \ - ((uint32_t (*)(void))ROM_PCMTABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PCM_clearInterruptFlag \ - ((void (*)(uint32_t flags))ROM_PCMTABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PCM_enableRudeMode \ - ((void (*)(void))ROM_PCMTABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PCM_disableRudeMode \ - ((void (*)(void))ROM_PCMTABLE[18]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PCM_gotoLPM0InterruptSafe \ - ((bool (*)(void))ROM_PCMTABLE[19]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_gotoLPM3InterruptSafe \ - ((bool (*)(void))ROM_PCMTABLE[20]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_setCoreVoltageLevelNonBlocking \ - ((bool (*)(uint_fast8_t voltageLevel))ROM_PCMTABLE[23]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_setPowerModeNonBlocking \ - ((bool (*)(uint_fast8_t powerMode))ROM_PCMTABLE[24]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_setPowerStateNonBlocking \ - ((bool (*)(uint_fast8_t powerState))ROM_PCMTABLE[25]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_gotoLPM4 \ - ((bool (*)(void))ROM_PCMTABLE[26]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_PCM_gotoLPM4InterruptSafe \ - ((bool (*)(void))ROM_PCMTABLE[27]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the PMAP API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PMAP_configurePorts \ - ((void (*)(const uint8_t *portMapping, \ - uint8_t pxMAPy, \ - uint8_t numberOfPorts, \ - uint8_t portMapReconfigure))ROM_PMAPTABLE[0]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the PSS API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_enableHighSidePinToggle \ - ((void (*)(bool activeLow))ROM_PSSTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_disableHighSidePinToggle \ - ((void (*)(void))ROM_PSSTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_enableHighSide \ - ((void (*)(void))ROM_PSSTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_disableHighSide \ - ((void (*)(void))ROM_PSSTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_setHighSidePerformanceMode \ - ((void (*)(uint_fast8_t powerMode))ROM_PSSTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_getHighSidePerformanceMode \ - ((uint_fast8_t (*)(void))ROM_PSSTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_enableHighSideMonitor \ - ((void (*)(void))ROM_PSSTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_disableHighSideMonitor \ - ((void (*)(void))ROM_PSSTABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_setHighSideVoltageTrigger \ - ((void (*)(uint_fast8_t triggerVoltage))ROM_PSSTABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_getHighSideVoltageTrigger \ - ((uint_fast8_t (*)(void))ROM_PSSTABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_enableInterrupt \ - ((void (*)(void))ROM_PSSTABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_disableInterrupt \ - ((void (*)(void))ROM_PSSTABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_getInterruptStatus \ - ((uint32_t (*)(void))ROM_PSSTABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_clearInterruptFlag \ - ((void (*)(void))ROM_PSSTABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_enableForcedDCDCOperation \ - ((void (*)(void))ROM_PSSTABLE[20]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_PSS_disableForcedDCDCOperation \ - ((void (*)(void))ROM_PSSTABLE[21]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Ref API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_setReferenceVoltage \ - ((void (*)(uint_fast8_t referenceVoltageSelect))ROM_REFTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_disableTempSensor \ - ((void (*)(void))ROM_REFTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_enableTempSensor \ - ((void (*)(void))ROM_REFTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_enableReferenceVoltageOutput \ - ((void (*)(void))ROM_REFTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_disableReferenceVoltageOutput \ - ((void (*)(void))ROM_REFTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_enableReferenceVoltage \ - ((void (*)(void))ROM_REFTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_disableReferenceVoltage \ - ((void (*)(void))ROM_REFTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_getBandgapMode \ - ((uint_fast8_t (*)(void))ROM_REFTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_isBandgapActive \ - ((bool (*)(void))ROM_REFTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_isRefGenBusy \ - ((bool (*)(void))ROM_REFTABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_isRefGenActive \ - ((bool (*)(void))ROM_REFTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_getBufferedBandgapVoltageStatus \ - ((bool (*)(void))ROM_REFTABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_getVariableReferenceVoltageStatus \ - ((bool (*)(void))ROM_REFTABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_setReferenceVoltageOneTimeTrigger \ - ((void (*)(void))ROM_REFTABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_REF_A_setBufferedBandgapVoltageOneTimeTrigger \ - ((void (*)(void))ROM_REFTABLE[14]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the ResetCtl API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ResetCtl_initiateSoftReset \ - ((void (*)(void))ROM_RESETCTLTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ResetCtl_initiateSoftResetWithSource \ - ((void (*)(uint32_t source))ROM_RESETCTLTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ResetCtl_getSoftResetSource \ - ((uint32_t (*)(void))ROM_RESETCTLTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ResetCtl_clearSoftResetSource \ - ((void (*)(uint32_t mask))ROM_RESETCTLTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ResetCtl_initiateHardReset \ - ((void (*)(void))ROM_RESETCTLTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ResetCtl_initiateHardResetWithSource \ - ((void (*)(uint32_t source))ROM_RESETCTLTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ResetCtl_getHardResetSource \ - ((uint32_t (*)(void))ROM_RESETCTLTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ResetCtl_clearHardResetSource \ - ((void (*)(uint32_t mask))ROM_RESETCTLTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ResetCtl_getPSSSource \ - ((uint32_t (*)(void))ROM_RESETCTLTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ResetCtl_clearPSSFlags \ - ((void (*)(void))ROM_RESETCTLTABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ResetCtl_getPCMSource \ - ((uint32_t (*)(void))ROM_RESETCTLTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_ResetCtl_clearPCMFlags \ - ((void (*)(void))ROM_RESETCTLTABLE[11]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the RTC API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_startClock \ - ((void (*)(void))ROM_RTCTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_holdClock \ - ((void (*)(void))ROM_RTCTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_setCalibrationFrequency \ - ((void (*)(uint_fast16_t frequencySelect))ROM_RTCTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_setCalibrationData \ - ((void (*)(uint_fast8_t offsetDirection, \ - uint_fast8_t offsetValue))ROM_RTCTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_setTemperatureCompensation \ - ((bool (*)(uint_fast16_t offsetDirection, \ - uint_fast8_t offsetValue))ROM_RTCTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_initCalendar \ - ((void (*)(const RTC_C_Calendar *calendarTime, \ - uint_fast16_t formatSelect))ROM_RTCTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_setCalendarAlarm \ - ((void (*)(uint_fast8_t minutesAlarm, \ - uint_fast8_t hoursAlarm, \ - uint_fast8_t dayOfWeekAlarm, \ - uint_fast8_t dayOfmonthAlarm))ROM_RTCTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_setCalendarEvent \ - ((void (*)(uint_fast16_t eventSelect))ROM_RTCTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_getPrescaleValue \ - ((uint_fast8_t (*)(uint_fast8_t prescaleSelect))ROM_RTCTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_setPrescaleValue \ - ((void (*)(uint_fast8_t prescaleSelect, \ - uint_fast8_t prescaleCounterValue))ROM_RTCTABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_convertBCDToBinary \ - ((uint16_t (*)(uint16_t valueToConvert))ROM_RTCTABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_convertBinaryToBCD \ - ((uint16_t (*)(uint16_t valueToConvert))ROM_RTCTABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_getInterruptStatus \ - ((uint_fast8_t (*)(void))ROM_RTCTABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_getEnabledInterruptStatus \ - ((uint_fast8_t (*)(void))ROM_RTCTABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_RTC_C_clearInterruptFlag \ - ((void (*)(uint_fast8_t interruptFlagMask))ROM_RTCTABLE[18]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SPI API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_selectFourPinFunctionality \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast8_t select4PinFunctionality))ROM_SPITABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_changeMasterClock \ - ((void (*)(uint32_t moduleInstance, \ - uint32_t clockSourceFrequency, \ - uint32_t desiredSpiClock))ROM_SPITABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_initSlave \ - ((bool (*)(uint32_t moduleInstance, \ - const eUSCI_SPI_SlaveConfig *config))ROM_SPITABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_changeClockPhasePolarity \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast16_t clockPhase, \ - uint_fast16_t clockPolarity))ROM_SPITABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_transmitData \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast8_t transmitData))ROM_SPITABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_receiveData \ - ((uint8_t (*)(uint32_t moduleInstance))ROM_SPITABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_enableModule \ - ((void (*)(uint32_t moduleInstance))ROM_SPITABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_disableModule \ - ((void (*)(uint32_t moduleInstance))ROM_SPITABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_getReceiveBufferAddressForDMA \ - ((uint32_t (*)(uint32_t moduleInstance))ROM_SPITABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_getTransmitBufferAddressForDMA \ - ((uint32_t (*)(uint32_t moduleInstance))ROM_SPITABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_isBusy \ - ((uint_fast8_t (*)(uint32_t moduleInstance))ROM_SPITABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_enableInterrupt \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast8_t mask))ROM_SPITABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_disableInterrupt \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast8_t mask))ROM_SPITABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_getInterruptStatus \ - ((uint_fast8_t (*)(uint32_t moduleInstance, \ - uint16_t mask))ROM_SPITABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_getEnabledInterruptStatus \ - ((uint_fast8_t (*)(uint32_t moduleInstance))ROM_SPITABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SPI_clearInterruptFlag \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast8_t mask))ROM_SPITABLE[16]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SysCtl API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_getSRAMSize \ - ((uint_least32_t (*)(void))ROM_SYSCTLTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_getFlashSize \ - ((uint_least32_t (*)(void))ROM_SYSCTLTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_rebootDevice \ - ((void (*)(void))ROM_SYSCTLTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_enableSRAMBank \ - ((void (*)(uint_fast8_t sramBank))ROM_SYSCTLTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_disableSRAMBank \ - ((void (*)(uint_fast8_t sramBank))ROM_SYSCTLTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_enableSRAMBankRetention \ - ((void (*)(uint_fast8_t sramBank))ROM_SYSCTLTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_disableSRAMBankRetention \ - ((void (*)(uint_fast8_t sramBank))ROM_SYSCTLTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_enablePeripheralAtCPUHalt \ - ((void (*)(uint_fast16_t devices))ROM_SYSCTLTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_disablePeripheralAtCPUHalt \ - ((void (*)(uint_fast16_t devices))ROM_SYSCTLTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_setWDTTimeoutResetType \ - ((void (*)(uint_fast8_t resetType))ROM_SYSCTLTABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_setWDTPasswordViolationResetType \ - ((void (*)(uint_fast8_t resetType))ROM_SYSCTLTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_disableNMISource \ - ((void (*)(uint_fast8_t flags))ROM_SYSCTLTABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_enableNMISource \ - ((void (*)(uint_fast8_t flags))ROM_SYSCTLTABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_getTempCalibrationConstant \ - ((uint_fast16_t (*)(uint32_t refVoltage, \ - uint32_t temperature))ROM_SYSCTLTABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_enableGlitchFilter \ - ((void (*)(void))ROM_SYSCTLTABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_disableGlitchFilter \ - ((void (*)(void))ROM_SYSCTLTABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX) -#define ROM_SysCtl_getTLVInfo \ - ((void (*)(uint_fast8_t tag, \ - uint_fast8_t instance, \ - uint_fast8_t *length, \ - uint32_t **data_address))ROM_SYSCTLTABLE[17]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SysTick API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysTick_enableModule \ - ((void (*)(void))ROM_SYSTICKTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysTick_disableModule \ - ((void (*)(void))ROM_SYSTICKTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysTick_enableInterrupt \ - ((void (*)(void))ROM_SYSTICKTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysTick_disableInterrupt \ - ((void (*)(void))ROM_SYSTICKTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysTick_setPeriod \ - ((void (*)(uint32_t period))ROM_SYSTICKTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysTick_getPeriod \ - ((uint32_t (*)(void))ROM_SYSTICKTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysTick_getValue \ - ((uint32_t (*)(void))ROM_SYSTICKTABLE[6]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Timer_A API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_startCounter \ - ((void (*)(uint32_t timer, \ - uint_fast16_t timerMode))ROM_TIMER_ATABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_configureContinuousMode \ - ((void (*)(uint32_t timer, \ - const Timer_A_ContinuousModeConfig *config))ROM_TIMER_ATABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_configureUpMode \ - ((void (*)(uint32_t timer, \ - const Timer_A_UpModeConfig *config))ROM_TIMER_ATABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_configureUpDownMode \ - ((void (*)(uint32_t timer, \ - const Timer_A_UpDownModeConfig *config))ROM_TIMER_ATABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_initCapture \ - ((void (*)(uint32_t timer, \ - const Timer_A_CaptureModeConfig *config))ROM_TIMER_ATABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_initCompare \ - ((void (*)(uint32_t timer, \ - const Timer_A_CompareModeConfig *config))ROM_TIMER_ATABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_clearTimer \ - ((void (*)(uint32_t timer))ROM_TIMER_ATABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_getSynchronizedCaptureCompareInput \ - ((uint_fast8_t (*)(uint32_t timer, \ - uint_fast16_t captureCompareRegister, \ - uint_fast16_t synchronizedSetting))ROM_TIMER_ATABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_getOutputForOutputModeOutBitValue \ - ((uint_fast8_t (*)(uint32_t timer, \ - uint_fast16_t captureCompareRegister))ROM_TIMER_ATABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_getCaptureCompareCount \ - ((uint_fast16_t (*)(uint32_t timer, \ - uint_fast16_t captureCompareRegister))ROM_TIMER_ATABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_setOutputForOutputModeOutBitValue \ - ((void (*)(uint32_t timer, \ - uint_fast16_t captureCompareRegister, \ - uint_fast8_t outputModeOutBitValue))ROM_TIMER_ATABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_generatePWM \ - ((void (*)(uint32_t timer, \ - const Timer_A_PWMConfig *config))ROM_TIMER_ATABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_stopTimer \ - ((void (*)(uint32_t timer))ROM_TIMER_ATABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_setCompareValue \ - ((void (*)(uint32_t timer, \ - uint_fast16_t compareRegister, \ - uint_fast16_t compareValue))ROM_TIMER_ATABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_clearInterruptFlag \ - ((void (*)(uint32_t timer))ROM_TIMER_ATABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_clearCaptureCompareInterrupt \ - ((void (*)(uint32_t timer, \ - uint_fast16_t captureCompareRegister))ROM_TIMER_ATABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_enableInterrupt \ - ((void (*)(uint32_t timer))ROM_TIMER_ATABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_disableInterrupt \ - ((void (*)(uint32_t timer))ROM_TIMER_ATABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_getInterruptStatus \ - ((uint32_t (*)(uint32_t timer))ROM_TIMER_ATABLE[18]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_getEnabledInterruptStatus \ - ((uint32_t (*)(uint32_t timer))ROM_TIMER_ATABLE[19]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_enableCaptureCompareInterrupt \ - ((void (*)(uint32_t timer, \ - uint_fast16_t captureCompareRegister))ROM_TIMER_ATABLE[20]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_disableCaptureCompareInterrupt \ - ((void (*)(uint32_t timer, \ - uint_fast16_t captureCompareRegister))ROM_TIMER_ATABLE[21]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_getCaptureCompareInterruptStatus \ - ((uint32_t (*)(uint32_t timer, \ - uint_fast16_t captureCompareRegister, \ - uint_fast16_t mask))ROM_TIMER_ATABLE[22]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_getCaptureCompareEnabledInterruptStatus \ - ((uint32_t (*)(uint32_t timer, \ - uint_fast16_t captureCompareRegister))ROM_TIMER_ATABLE[23]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer_A_getCounterValue \ - ((uint16_t (*)(uint32_t timer))ROM_TIMER_ATABLE[26]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Timer32 API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer32_initModule \ - ((void (*)(uint32_t timer, \ - uint32_t preScaler, \ - uint32_t resolution, \ - uint32_t mode))ROM_TIMER32TABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer32_setCount \ - ((void (*)(uint32_t timer, \ - uint32_t count))ROM_TIMER32TABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer32_setCountInBackground \ - ((void (*)(uint32_t timer, \ - uint32_t count))ROM_TIMER32TABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer32_getValue \ - ((uint32_t (*)(uint32_t timer))ROM_TIMER32TABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer32_startTimer \ - ((void (*)(uint32_t timer, \ - bool oneShot))ROM_TIMER32TABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer32_haltTimer \ - ((void (*)(uint32_t timer))ROM_TIMER32TABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer32_enableInterrupt \ - ((void (*)(uint32_t timer))ROM_TIMER32TABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer32_disableInterrupt \ - ((void (*)(uint32_t timer))ROM_TIMER32TABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer32_clearInterruptFlag \ - ((void (*)(uint32_t timer))ROM_TIMER32TABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_Timer32_getInterruptStatus \ - ((uint32_t (*)(uint32_t timer))ROM_TIMER32TABLE[9]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the UART API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_initModule \ - ((bool (*)(uint32_t moduleInstance, \ - const eUSCI_UART_Config *config))ROM_UARTTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_transmitData \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast8_t transmitData))ROM_UARTTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_enableModule \ - ((void (*)(uint32_t moduleInstance))ROM_UARTTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_disableModule \ - ((void (*)(uint32_t moduleInstance))ROM_UARTTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_queryStatusFlags \ - ((uint_fast8_t (*)(uint32_t moduleInstance, \ - uint_fast8_t mask))ROM_UARTTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_setDormant \ - ((void (*)(uint32_t moduleInstance))ROM_UARTTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_resetDormant \ - ((void (*)(uint32_t moduleInstance))ROM_UARTTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_transmitAddress \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast8_t transmitAddress))ROM_UARTTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_transmitBreak \ - ((void (*)(uint32_t moduleInstance))ROM_UARTTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_getReceiveBufferAddressForDMA \ - ((uint32_t (*)(uint32_t moduleInstance))ROM_UARTTABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_getTransmitBufferAddressForDMA \ - ((uint32_t (*)(uint32_t moduleInstance))ROM_UARTTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_selectDeglitchTime \ - ((void (*)(uint32_t moduleInstance, \ - uint32_t deglitchTime))ROM_UARTTABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_enableInterrupt \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast8_t mask))ROM_UARTTABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_disableInterrupt \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast8_t mask))ROM_UARTTABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_getInterruptStatus \ - ((uint_fast8_t (*)(uint32_t moduleInstance, \ - uint8_t mask))ROM_UARTTABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_clearInterruptFlag \ - ((void (*)(uint32_t moduleInstance, \ - uint_fast8_t mask))ROM_UARTTABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_receiveData \ - ((uint8_t (*)(uint32_t moduleInstance))ROM_UARTTABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_UART_getEnabledInterruptStatus \ - ((uint_fast8_t (*)(uint32_t moduleInstance))ROM_UARTTABLE[17]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the WDT API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_WDT_A_holdTimer \ - ((void (*)(void))ROM_WDTTABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_WDT_A_startTimer \ - ((void (*)(void))ROM_WDTTABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_WDT_A_clearTimer \ - ((void (*)(void))ROM_WDTTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_WDT_A_initWatchdogTimer \ - ((void (*)(uint_fast8_t clockSelect, \ - uint_fast8_t clockDivider))ROM_WDTTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_WDT_A_initIntervalTimer \ - ((void (*)(uint_fast8_t clockSelect, \ - uint_fast8_t clockDivider))ROM_WDTTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_WDT_A_setPasswordViolationReset \ - ((void (*)(uint_fast8_t resetType))ROM_WDTTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX) || \ - defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_WDT_A_setTimeoutReset \ - ((void (*)(uint_fast8_t resetType))ROM_WDTTABLE[8]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the SysCtl_A API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_getSRAMSize \ - ((uint_least32_t (*)(void))ROM_SYSCTLATABLE[0]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_getFlashSize \ - ((uint_least32_t (*)(void))ROM_SYSCTLATABLE[1]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_rebootDevice \ - ((void (*)(void))ROM_SYSCTLATABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_enableSRAM \ - ((bool (*)(uint32_t addr))ROM_SYSCTLATABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_disableSRAM \ - ((bool (*)(uint32_t addr))ROM_SYSCTLATABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_enableSRAMRetention \ - ((bool (*)(uint32_t startAddr, \ - uint32_t endAddr))ROM_SYSCTLATABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_disableSRAMRetention \ - ((bool (*)(uint32_t startAddr, \ - uint32_t endAddr))ROM_SYSCTLATABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_enablePeripheralAtCPUHalt \ - ((void (*)(uint_fast16_t devices))ROM_SYSCTLATABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_disablePeripheralAtCPUHalt \ - ((void (*)(uint_fast16_t devices))ROM_SYSCTLATABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_setWDTTimeoutResetType \ - ((void (*)(uint_fast8_t resetType))ROM_SYSCTLATABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_setWDTPasswordViolationResetType \ - ((void (*)(uint_fast8_t resetType))ROM_SYSCTLATABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_disableNMISource \ - ((void (*)(uint_fast8_t flags))ROM_SYSCTLATABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_enableNMISource \ - ((void (*)(uint_fast8_t flags))ROM_SYSCTLATABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_getTempCalibrationConstant \ - ((uint_fast16_t (*)(uint32_t refVoltage, \ - uint32_t temperature))ROM_SYSCTLATABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_enableGlitchFilter \ - ((void (*)(void))ROM_SYSCTLATABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_disableGlitchFilter \ - ((void (*)(void))ROM_SYSCTLATABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_getTLVInfo \ - ((void (*)(uint_fast8_t tag, \ - uint_fast8_t instance, \ - uint_fast8_t *length, \ - uint32_t **data_address))ROM_SYSCTLATABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_SysCtl_A_getInfoFlashSize \ - ((uint_least32_t (*)(void))ROM_SYSCTLATABLE[18]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the Flash_A API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_enableReadBuffering \ - ((void (*)(uint_fast8_t memoryBank, \ - uint_fast8_t accessMethod))ROM_FLASHCTLATABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_disableReadBuffering \ - ((void (*)(uint_fast8_t memoryBank, \ - uint_fast8_t accessMethod))ROM_FLASHCTLATABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_unprotectMemory \ - ((bool (*)(uint32_t startAddr, \ - uint32_t endAddr))ROM_FLASHCTLATABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_protectMemory \ - ((bool (*)(uint32_t startAddr, \ - uint32_t endAddr))ROM_FLASHCTLATABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_isMemoryRangeProtected \ - ((bool (*)(uint32_t startAddr, \ - uint32_t endAddr))ROM_FLASHCTLATABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_verifyMemory \ - ((bool (*)(void* verifyAddr, \ - uint32_t length, \ - uint_fast8_t pattern))ROM_FLASHCTLATABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_performMassErase \ - ((bool (*)(void))ROM_FLASHCTLATABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_eraseSector \ - ((bool (*)(uint32_t addr))ROM_FLASHCTLATABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_programMemory \ - ((bool (*)(void* src, \ - void* dest, \ - uint32_t length))ROM_FLASHCTLATABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_setProgramVerification \ - ((void (*)(uint32_t verificationSetting))ROM_FLASHCTLATABLE[11]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_clearProgramVerification \ - ((void (*)( uint32_t verificationSetting))ROM_FLASHCTLATABLE[12]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_enableWordProgramming \ - ((void (*)(uint32_t mode))ROM_FLASHCTLATABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_disableWordProgramming \ - ((void (*)(void))ROM_FLASHCTLATABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_isWordProgrammingEnabled \ - ((uint32_t (*)(void))ROM_FLASHCTLATABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_enableInterrupt \ - ((void (*)(uint32_t flags))ROM_FLASHCTLATABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_disableInterrupt \ - ((void (*)(uint32_t flags))ROM_FLASHCTLATABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_getEnabledInterruptStatus \ - ((uint32_t (*)(void))ROM_FLASHCTLATABLE[18]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_getInterruptStatus \ - ((uint32_t (*)(void))ROM_FLASHCTLATABLE[19]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_clearInterruptFlag \ - ((void (*)(uint32_t flags))ROM_FLASHCTLATABLE[20]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_setWaitState \ - ((void (*)(uint32_t bank, \ - uint32_t waitState))ROM_FLASHCTLATABLE[21]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_getWaitState \ - ((uint32_t (*)(uint32_t bank))ROM_FLASHCTLATABLE[22]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_setReadMode \ - ((bool (*)(uint32_t flashBank, \ - uint32_t readMode))ROM_FLASHCTLATABLE[23]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_getReadMode \ - ((uint32_t (*)(uint32_t flashBank))ROM_FLASHCTLATABLE[24]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM___FlashCtl_A_remaskData8Post \ - ((uint8_t (*)(uint8_t data, \ - uint32_t addr))ROM_FLASHCTLATABLE[27]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM___FlashCtl_A_remaskData8Pre \ - ((uint8_t (*)(uint8_t data, \ - uint32_t addr))ROM_FLASHCTLATABLE[28]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM___FlashCtl_A_remaskData32Pre \ - ((uint32_t (*)(uint32_t data, \ - uint32_t addr))ROM_FLASHCTLATABLE[29]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM___FlashCtl_A_remaskData32Post \ - ((uint32_t (*)(uint32_t data, \ - uint32_t addr))ROM_FLASHCTLATABLE[30]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM___FlashCtl_A_remaskBurstDataPre \ - ((void (*)(uint32_t addr, \ - uint32_t size))ROM_FLASHCTLATABLE[31]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM___FlashCtl_A_remaskBurstDataPost \ - ((void (*)(uint32_t addr, \ - uint32_t size))ROM_FLASHCTLATABLE[32]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_initiateSectorErase \ - ((void (*)(uint32_t addr))ROM_FLASHCTLATABLE[33]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_initiateMassErase \ - ((void (*)(void))ROM_FLASHCTLATABLE[34]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_FlashCtl_A_isMemoryProtected \ - ((bool (*)(uint32_t addr))ROM_FLASHCTLATABLE[35]) -#endif - -//***************************************************************************** -// -// Macros for calling ROM functions in the LCD_F API. -// -//***************************************************************************** -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_turnOff \ - ((void (*)(void))ROM_LCDFTABLE[2]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_clearAllMemory \ - ((void (*)(void))ROM_LCDFTABLE[3]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_clearAllBlinkingMemory \ - ((void (*)(void))ROM_LCDFTABLE[4]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_selectDisplayMemory \ - ((void (*)(uint_fast16_t displayMemory))ROM_LCDFTABLE[5]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_setBlinkingControl \ - ((void (*)(uint_fast16_t clockPrescalar, \ - uint_fast16_t divider, \ - uint_fast16_t mode))ROM_LCDFTABLE[6]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_setAnimationControl \ - ((void (*)(uint_fast16_t clockPrescalar, \ - uint_fast16_t divider, \ - uint_fast16_t frames))ROM_LCDFTABLE[7]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_clearAllAnimationMemory \ - ((void (*)(void))ROM_LCDFTABLE[8]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_setPinAsLCDFunction \ - ((void (*)(uint_fast8_t pin))ROM_LCDFTABLE[9]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_setPinAsPortFunction \ - ((void (*)(uint_fast8_t pin))ROM_LCDFTABLE[10]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_setPinAsSEG \ - ((void (*)(uint_fast8_t pin))ROM_LCDFTABLE[13]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_selectBias \ - ((void (*)(uint_fast16_t bias))ROM_LCDFTABLE[14]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_setVLCDSource \ - ((void (*)(uint_fast16_t v2v3v4Source, \ - uint_fast16_t v5Source))ROM_LCDFTABLE[15]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_clearInterrupt \ - ((void (*)(uint32_t mask))ROM_LCDFTABLE[16]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_getInterruptStatus \ - ((uint32_t (*)(void))ROM_LCDFTABLE[17]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_getEnabledInterruptStatus \ - ((uint32_t (*)(void))ROM_LCDFTABLE[18]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_enableInterrupt \ - ((void (*)(uint32_t mask))ROM_LCDFTABLE[19]) -#endif -#if defined(TARGET_IS_MSP432P4XX_NEXT) -#define ROM_LCD_F_disableInterrupt \ - ((void (*)(uint32_t mask))ROM_LCDFTABLE[20]) -#endif - -#endif // __ROM_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/rom_map.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/rom_map.h deleted file mode 100644 index c632befb348..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/rom_map.h +++ /dev/null @@ -1,4180 +0,0 @@ -//***************************************************************************** -// -// rom_map.h - Macros to facilitate calling functions in the ROM when they are -// available and in flash otherwise. -// -// Copyright (c) 2013 Texas Instruments Incorporated. All rights reserved. -// TI Information - Selective Disclosure -// -// -//***************************************************************************** - -#ifndef __ROM_MAP_H__ -#define __ROM_MAP_H__ - -//***************************************************************************** -// -// Macros for the ADC14 API. -// -//***************************************************************************** -#ifdef ROM_ADC14_enableModule -#define MAP_ADC14_enableModule \ - ROM_ADC14_enableModule -#else -#define MAP_ADC14_enableModule \ - ADC14_enableModule -#endif -#ifdef ROM_ADC14_disableModule -#define MAP_ADC14_disableModule \ - ROM_ADC14_disableModule -#else -#define MAP_ADC14_disableModule \ - ADC14_disableModule -#endif -#ifdef ROM_ADC14_initModule -#define MAP_ADC14_initModule \ - ROM_ADC14_initModule -#else -#define MAP_ADC14_initModule \ - ADC14_initModule -#endif -#ifdef ROM_ADC14_setResolution -#define MAP_ADC14_setResolution \ - ROM_ADC14_setResolution -#else -#define MAP_ADC14_setResolution \ - ADC14_setResolution -#endif -#ifdef ROM_ADC14_getResolution -#define MAP_ADC14_getResolution \ - ROM_ADC14_getResolution -#else -#define MAP_ADC14_getResolution \ - ADC14_getResolution -#endif -#ifdef ROM_ADC14_setSampleHoldTrigger -#define MAP_ADC14_setSampleHoldTrigger \ - ROM_ADC14_setSampleHoldTrigger -#else -#define MAP_ADC14_setSampleHoldTrigger \ - ADC14_setSampleHoldTrigger -#endif -#ifdef ROM_ADC14_setSampleHoldTime -#define MAP_ADC14_setSampleHoldTime \ - ROM_ADC14_setSampleHoldTime -#else -#define MAP_ADC14_setSampleHoldTime \ - ADC14_setSampleHoldTime -#endif -#ifdef ROM_ADC14_configureMultiSequenceMode -#define MAP_ADC14_configureMultiSequenceMode \ - ROM_ADC14_configureMultiSequenceMode -#else -#define MAP_ADC14_configureMultiSequenceMode \ - ADC14_configureMultiSequenceMode -#endif -#ifdef ROM_ADC14_configureSingleSampleMode -#define MAP_ADC14_configureSingleSampleMode \ - ROM_ADC14_configureSingleSampleMode -#else -#define MAP_ADC14_configureSingleSampleMode \ - ADC14_configureSingleSampleMode -#endif -#ifdef ROM_ADC14_enableConversion -#define MAP_ADC14_enableConversion \ - ROM_ADC14_enableConversion -#else -#define MAP_ADC14_enableConversion \ - ADC14_enableConversion -#endif -#ifdef ROM_ADC14_disableConversion -#define MAP_ADC14_disableConversion \ - ROM_ADC14_disableConversion -#else -#define MAP_ADC14_disableConversion \ - ADC14_disableConversion -#endif -#ifdef ROM_ADC14_isBusy -#define MAP_ADC14_isBusy \ - ROM_ADC14_isBusy -#else -#define MAP_ADC14_isBusy \ - ADC14_isBusy -#endif -#ifdef ROM_ADC14_configureConversionMemory -#define MAP_ADC14_configureConversionMemory \ - ROM_ADC14_configureConversionMemory -#else -#define MAP_ADC14_configureConversionMemory \ - ADC14_configureConversionMemory -#endif -#ifdef ROM_ADC14_enableComparatorWindow -#define MAP_ADC14_enableComparatorWindow \ - ROM_ADC14_enableComparatorWindow -#else -#define MAP_ADC14_enableComparatorWindow \ - ADC14_enableComparatorWindow -#endif -#ifdef ROM_ADC14_disableComparatorWindow -#define MAP_ADC14_disableComparatorWindow \ - ROM_ADC14_disableComparatorWindow -#else -#define MAP_ADC14_disableComparatorWindow \ - ADC14_disableComparatorWindow -#endif -#ifdef ROM_ADC14_setComparatorWindowValue -#define MAP_ADC14_setComparatorWindowValue \ - ROM_ADC14_setComparatorWindowValue -#else -#define MAP_ADC14_setComparatorWindowValue \ - ADC14_setComparatorWindowValue -#endif -#ifdef ROM_ADC14_setResultFormat -#define MAP_ADC14_setResultFormat \ - ROM_ADC14_setResultFormat -#else -#define MAP_ADC14_setResultFormat \ - ADC14_setResultFormat -#endif -#ifdef ROM_ADC14_getResult -#define MAP_ADC14_getResult \ - ROM_ADC14_getResult -#else -#define MAP_ADC14_getResult \ - ADC14_getResult -#endif -#ifdef ROM_ADC14_getMultiSequenceResult -#define MAP_ADC14_getMultiSequenceResult \ - ROM_ADC14_getMultiSequenceResult -#else -#define MAP_ADC14_getMultiSequenceResult \ - ADC14_getMultiSequenceResult -#endif -#ifdef ROM_ADC14_getResultArray -#define MAP_ADC14_getResultArray \ - ROM_ADC14_getResultArray -#else -#define MAP_ADC14_getResultArray \ - ADC14_getResultArray -#endif -#ifdef ROM_ADC14_enableReferenceBurst -#define MAP_ADC14_enableReferenceBurst \ - ROM_ADC14_enableReferenceBurst -#else -#define MAP_ADC14_enableReferenceBurst \ - ADC14_enableReferenceBurst -#endif -#ifdef ROM_ADC14_disableReferenceBurst -#define MAP_ADC14_disableReferenceBurst \ - ROM_ADC14_disableReferenceBurst -#else -#define MAP_ADC14_disableReferenceBurst \ - ADC14_disableReferenceBurst -#endif -#ifdef ROM_ADC14_setPowerMode -#define MAP_ADC14_setPowerMode \ - ROM_ADC14_setPowerMode -#else -#define MAP_ADC14_setPowerMode \ - ADC14_setPowerMode -#endif -#ifdef ROM_ADC14_enableInterrupt -#define MAP_ADC14_enableInterrupt \ - ROM_ADC14_enableInterrupt -#else -#define MAP_ADC14_enableInterrupt \ - ADC14_enableInterrupt -#endif -#ifdef ROM_ADC14_disableInterrupt -#define MAP_ADC14_disableInterrupt \ - ROM_ADC14_disableInterrupt -#else -#define MAP_ADC14_disableInterrupt \ - ADC14_disableInterrupt -#endif -#ifdef ROM_ADC14_getInterruptStatus -#define MAP_ADC14_getInterruptStatus \ - ROM_ADC14_getInterruptStatus -#else -#define MAP_ADC14_getInterruptStatus \ - ADC14_getInterruptStatus -#endif -#ifdef ROM_ADC14_getEnabledInterruptStatus -#define MAP_ADC14_getEnabledInterruptStatus \ - ROM_ADC14_getEnabledInterruptStatus -#else -#define MAP_ADC14_getEnabledInterruptStatus \ - ADC14_getEnabledInterruptStatus -#endif -#ifdef ROM_ADC14_clearInterruptFlag -#define MAP_ADC14_clearInterruptFlag \ - ROM_ADC14_clearInterruptFlag -#else -#define MAP_ADC14_clearInterruptFlag \ - ADC14_clearInterruptFlag -#endif -#ifdef ROM_ADC14_toggleConversionTrigger -#define MAP_ADC14_toggleConversionTrigger \ - ROM_ADC14_toggleConversionTrigger -#else -#define MAP_ADC14_toggleConversionTrigger \ - ADC14_toggleConversionTrigger -#endif -#ifdef ROM_ADC14_enableSampleTimer -#define MAP_ADC14_enableSampleTimer \ - ROM_ADC14_enableSampleTimer -#else -#define MAP_ADC14_enableSampleTimer \ - ADC14_enableSampleTimer -#endif -#ifdef ROM_ADC14_disableSampleTimer -#define MAP_ADC14_disableSampleTimer \ - ROM_ADC14_disableSampleTimer -#else -#define MAP_ADC14_disableSampleTimer \ - ADC14_disableSampleTimer -#endif -#ifdef ROM_ADC14_registerInterrupt -#define MAP_ADC14_registerInterrupt \ - ROM_ADC14_registerInterrupt -#else -#define MAP_ADC14_registerInterrupt \ - ADC14_registerInterrupt -#endif -#ifdef ROM_ADC14_unregisterInterrupt -#define MAP_ADC14_unregisterInterrupt \ - ROM_ADC14_unregisterInterrupt -#else -#define MAP_ADC14_unregisterInterrupt \ - ADC14_unregisterInterrupt -#endif - -//***************************************************************************** -// -// Macros for the AES256 API. -// -//***************************************************************************** -#ifdef ROM_AES256_setCipherKey -#define MAP_AES256_setCipherKey \ - ROM_AES256_setCipherKey -#else -#define MAP_AES256_setCipherKey \ - AES256_setCipherKey -#endif -#ifdef ROM_AES256_encryptData -#define MAP_AES256_encryptData \ - ROM_AES256_encryptData -#else -#define MAP_AES256_encryptData \ - AES256_encryptData -#endif -#ifdef ROM_AES256_decryptData -#define MAP_AES256_decryptData \ - ROM_AES256_decryptData -#else -#define MAP_AES256_decryptData \ - AES256_decryptData -#endif -#ifdef ROM_AES256_setDecipherKey -#define MAP_AES256_setDecipherKey \ - ROM_AES256_setDecipherKey -#else -#define MAP_AES256_setDecipherKey \ - AES256_setDecipherKey -#endif -#ifdef ROM_AES256_reset -#define MAP_AES256_reset \ - ROM_AES256_reset -#else -#define MAP_AES256_reset \ - AES256_reset -#endif -#ifdef ROM_AES256_startEncryptData -#define MAP_AES256_startEncryptData \ - ROM_AES256_startEncryptData -#else -#define MAP_AES256_startEncryptData \ - AES256_startEncryptData -#endif -#ifdef ROM_AES256_startDecryptData -#define MAP_AES256_startDecryptData \ - ROM_AES256_startDecryptData -#else -#define MAP_AES256_startDecryptData \ - AES256_startDecryptData -#endif -#ifdef ROM_AES256_startSetDecipherKey -#define MAP_AES256_startSetDecipherKey \ - ROM_AES256_startSetDecipherKey -#else -#define MAP_AES256_startSetDecipherKey \ - AES256_startSetDecipherKey -#endif -#ifdef ROM_AES256_getDataOut -#define MAP_AES256_getDataOut \ - ROM_AES256_getDataOut -#else -#define MAP_AES256_getDataOut \ - AES256_getDataOut -#endif -#ifdef ROM_AES256_isBusy -#define MAP_AES256_isBusy \ - ROM_AES256_isBusy -#else -#define MAP_AES256_isBusy \ - AES256_isBusy -#endif -#ifdef ROM_AES256_clearErrorFlag -#define MAP_AES256_clearErrorFlag \ - ROM_AES256_clearErrorFlag -#else -#define MAP_AES256_clearErrorFlag \ - AES256_clearErrorFlag -#endif -#ifdef ROM_AES256_getErrorFlagStatus -#define MAP_AES256_getErrorFlagStatus \ - ROM_AES256_getErrorFlagStatus -#else -#define MAP_AES256_getErrorFlagStatus \ - AES256_getErrorFlagStatus -#endif -#ifdef ROM_AES256_clearInterruptFlag -#define MAP_AES256_clearInterruptFlag \ - ROM_AES256_clearInterruptFlag -#else -#define MAP_AES256_clearInterruptFlag \ - AES256_clearInterruptFlag -#endif -#ifdef ROM_AES256_getInterruptStatus -#define MAP_AES256_getInterruptStatus \ - ROM_AES256_getInterruptStatus -#else -#define MAP_AES256_getInterruptStatus \ - AES256_getInterruptStatus -#endif -#ifdef ROM_AES256_enableInterrupt -#define MAP_AES256_enableInterrupt \ - ROM_AES256_enableInterrupt -#else -#define MAP_AES256_enableInterrupt \ - AES256_enableInterrupt -#endif -#ifdef ROM_AES256_disableInterrupt -#define MAP_AES256_disableInterrupt \ - ROM_AES256_disableInterrupt -#else -#define MAP_AES256_disableInterrupt \ - AES256_disableInterrupt -#endif -#ifdef ROM_AES256_registerInterrupt -#define MAP_AES256_registerInterrupt \ - ROM_AES256_registerInterrupt -#else -#define MAP_AES256_registerInterrupt \ - AES256_registerInterrupt -#endif -#ifdef ROM_AES256_unregisterInterrupt -#define MAP_AES256_unregisterInterrupt \ - ROM_AES256_unregisterInterrupt -#else -#define MAP_AES256_unregisterInterrupt \ - AES256_unregisterInterrupt -#endif -#ifdef ROM_AES256_getInterruptFlagStatus -#define MAP_AES256_getInterruptFlagStatus \ - ROM_AES256_getInterruptFlagStatus -#else -#define MAP_AES256_getInterruptFlagStatus \ - AES256_getInterruptFlagStatus -#endif - -//***************************************************************************** -// -// Macros for the Comp API. -// -//***************************************************************************** -#ifdef ROM_COMP_E_initModule -#define MAP_COMP_E_initModule \ - ROM_COMP_E_initModule -#else -#define MAP_COMP_E_initModule \ - COMP_E_initModule -#endif -#ifdef ROM_COMP_E_setReferenceVoltage -#define MAP_COMP_E_setReferenceVoltage \ - ROM_COMP_E_setReferenceVoltage -#else -#define MAP_COMP_E_setReferenceVoltage \ - COMP_E_setReferenceVoltage -#endif -#ifdef ROM_COMP_E_setReferenceAccuracy -#define MAP_COMP_E_setReferenceAccuracy \ - ROM_COMP_E_setReferenceAccuracy -#else -#define MAP_COMP_E_setReferenceAccuracy \ - COMP_E_setReferenceAccuracy -#endif -#ifdef ROM_COMP_E_setPowerMode -#define MAP_COMP_E_setPowerMode \ - ROM_COMP_E_setPowerMode -#else -#define MAP_COMP_E_setPowerMode \ - COMP_E_setPowerMode -#endif -#ifdef ROM_COMP_E_enableModule -#define MAP_COMP_E_enableModule \ - ROM_COMP_E_enableModule -#else -#define MAP_COMP_E_enableModule \ - COMP_E_enableModule -#endif -#ifdef ROM_COMP_E_disableModule -#define MAP_COMP_E_disableModule \ - ROM_COMP_E_disableModule -#else -#define MAP_COMP_E_disableModule \ - COMP_E_disableModule -#endif -#ifdef ROM_COMP_E_shortInputs -#define MAP_COMP_E_shortInputs \ - ROM_COMP_E_shortInputs -#else -#define MAP_COMP_E_shortInputs \ - COMP_E_shortInputs -#endif -#ifdef ROM_COMP_E_unshortInputs -#define MAP_COMP_E_unshortInputs \ - ROM_COMP_E_unshortInputs -#else -#define MAP_COMP_E_unshortInputs \ - COMP_E_unshortInputs -#endif -#ifdef ROM_COMP_E_disableInputBuffer -#define MAP_COMP_E_disableInputBuffer \ - ROM_COMP_E_disableInputBuffer -#else -#define MAP_COMP_E_disableInputBuffer \ - COMP_E_disableInputBuffer -#endif -#ifdef ROM_COMP_E_enableInputBuffer -#define MAP_COMP_E_enableInputBuffer \ - ROM_COMP_E_enableInputBuffer -#else -#define MAP_COMP_E_enableInputBuffer \ - COMP_E_enableInputBuffer -#endif -#ifdef ROM_COMP_E_swapIO -#define MAP_COMP_E_swapIO \ - ROM_COMP_E_swapIO -#else -#define MAP_COMP_E_swapIO \ - COMP_E_swapIO -#endif -#ifdef ROM_COMP_E_outputValue -#define MAP_COMP_E_outputValue \ - ROM_COMP_E_outputValue -#else -#define MAP_COMP_E_outputValue \ - COMP_E_outputValue -#endif -#ifdef ROM_COMP_E_enableInterrupt -#define MAP_COMP_E_enableInterrupt \ - ROM_COMP_E_enableInterrupt -#else -#define MAP_COMP_E_enableInterrupt \ - COMP_E_enableInterrupt -#endif -#ifdef ROM_COMP_E_disableInterrupt -#define MAP_COMP_E_disableInterrupt \ - ROM_COMP_E_disableInterrupt -#else -#define MAP_COMP_E_disableInterrupt \ - COMP_E_disableInterrupt -#endif -#ifdef ROM_COMP_E_clearInterruptFlag -#define MAP_COMP_E_clearInterruptFlag \ - ROM_COMP_E_clearInterruptFlag -#else -#define MAP_COMP_E_clearInterruptFlag \ - COMP_E_clearInterruptFlag -#endif -#ifdef ROM_COMP_E_getInterruptStatus -#define MAP_COMP_E_getInterruptStatus \ - ROM_COMP_E_getInterruptStatus -#else -#define MAP_COMP_E_getInterruptStatus \ - COMP_E_getInterruptStatus -#endif -#ifdef ROM_COMP_E_getEnabledInterruptStatus -#define MAP_COMP_E_getEnabledInterruptStatus \ - ROM_COMP_E_getEnabledInterruptStatus -#else -#define MAP_COMP_E_getEnabledInterruptStatus \ - COMP_E_getEnabledInterruptStatus -#endif -#ifdef ROM_COMP_E_setInterruptEdgeDirection -#define MAP_COMP_E_setInterruptEdgeDirection \ - ROM_COMP_E_setInterruptEdgeDirection -#else -#define MAP_COMP_E_setInterruptEdgeDirection \ - COMP_E_setInterruptEdgeDirection -#endif -#ifdef ROM_COMP_E_toggleInterruptEdgeDirection -#define MAP_COMP_E_toggleInterruptEdgeDirection \ - ROM_COMP_E_toggleInterruptEdgeDirection -#else -#define MAP_COMP_E_toggleInterruptEdgeDirection \ - COMP_E_toggleInterruptEdgeDirection -#endif -#ifdef ROM_COMP_E_registerInterrupt -#define MAP_COMP_E_registerInterrupt \ - ROM_COMP_E_registerInterrupt -#else -#define MAP_COMP_E_registerInterrupt \ - COMP_E_registerInterrupt -#endif -#ifdef ROM_COMP_E_unregisterInterrupt -#define MAP_COMP_E_unregisterInterrupt \ - ROM_COMP_E_unregisterInterrupt -#else -#define MAP_COMP_E_unregisterInterrupt \ - COMP_E_unregisterInterrupt -#endif - -//***************************************************************************** -// -// Macros for the CRC32 API. -// -//***************************************************************************** -#ifdef ROM_CRC32_setSeed -#define MAP_CRC32_setSeed \ - ROM_CRC32_setSeed -#else -#define MAP_CRC32_setSeed \ - CRC32_setSeed -#endif -#ifdef ROM_CRC32_set8BitData -#define MAP_CRC32_set8BitData \ - ROM_CRC32_set8BitData -#else -#define MAP_CRC32_set8BitData \ - CRC32_set8BitData -#endif -#ifdef ROM_CRC32_set16BitData -#define MAP_CRC32_set16BitData \ - ROM_CRC32_set16BitData -#else -#define MAP_CRC32_set16BitData \ - CRC32_set16BitData -#endif -#ifdef ROM_CRC32_set32BitData -#define MAP_CRC32_set32BitData \ - ROM_CRC32_set32BitData -#else -#define MAP_CRC32_set32BitData \ - CRC32_set32BitData -#endif -#ifdef ROM_CRC32_set8BitDataReversed -#define MAP_CRC32_set8BitDataReversed \ - ROM_CRC32_set8BitDataReversed -#else -#define MAP_CRC32_set8BitDataReversed \ - CRC32_set8BitDataReversed -#endif -#ifdef ROM_CRC32_set16BitDataReversed -#define MAP_CRC32_set16BitDataReversed \ - ROM_CRC32_set16BitDataReversed -#else -#define MAP_CRC32_set16BitDataReversed \ - CRC32_set16BitDataReversed -#endif -#ifdef ROM_CRC32_set32BitDataReversed -#define MAP_CRC32_set32BitDataReversed \ - ROM_CRC32_set32BitDataReversed -#else -#define MAP_CRC32_set32BitDataReversed \ - CRC32_set32BitDataReversed -#endif -#ifdef ROM_CRC32_getResult -#define MAP_CRC32_getResult \ - ROM_CRC32_getResult -#else -#define MAP_CRC32_getResult \ - CRC32_getResult -#endif -#ifdef ROM_CRC32_getResultReversed -#define MAP_CRC32_getResultReversed \ - ROM_CRC32_getResultReversed -#else -#define MAP_CRC32_getResultReversed \ - CRC32_getResultReversed -#endif - -//***************************************************************************** -// -// Macros for the CS API. -// -//***************************************************************************** -#ifdef ROM_CS_initClockSignal -#define MAP_CS_initClockSignal \ - ROM_CS_initClockSignal -#else -#define MAP_CS_initClockSignal \ - CS_initClockSignal -#endif -#ifdef ROM_CS_setReferenceOscillatorFrequency -#define MAP_CS_setReferenceOscillatorFrequency \ - ROM_CS_setReferenceOscillatorFrequency -#else -#define MAP_CS_setReferenceOscillatorFrequency \ - CS_setReferenceOscillatorFrequency -#endif -#ifdef ROM_CS_enableClockRequest -#define MAP_CS_enableClockRequest \ - ROM_CS_enableClockRequest -#else -#define MAP_CS_enableClockRequest \ - CS_enableClockRequest -#endif -#ifdef ROM_CS_disableClockRequest -#define MAP_CS_disableClockRequest \ - ROM_CS_disableClockRequest -#else -#define MAP_CS_disableClockRequest \ - CS_disableClockRequest -#endif -#ifdef ROM_CS_setDCOCenteredFrequency -#define MAP_CS_setDCOCenteredFrequency \ - ROM_CS_setDCOCenteredFrequency -#else -#define MAP_CS_setDCOCenteredFrequency \ - CS_setDCOCenteredFrequency -#endif -#ifdef ROM_CS_tuneDCOFrequency -#define MAP_CS_tuneDCOFrequency \ - ROM_CS_tuneDCOFrequency -#else -#define MAP_CS_tuneDCOFrequency \ - CS_tuneDCOFrequency -#endif -#ifdef ROM_CS_enableDCOExternalResistor -#define MAP_CS_enableDCOExternalResistor \ - ROM_CS_enableDCOExternalResistor -#else -#define MAP_CS_enableDCOExternalResistor \ - CS_enableDCOExternalResistor -#endif -#ifdef ROM_CS_disableDCOExternalResistor -#define MAP_CS_disableDCOExternalResistor \ - ROM_CS_disableDCOExternalResistor -#else -#define MAP_CS_disableDCOExternalResistor \ - CS_disableDCOExternalResistor -#endif -#ifdef ROM_CS_enableInterrupt -#define MAP_CS_enableInterrupt \ - ROM_CS_enableInterrupt -#else -#define MAP_CS_enableInterrupt \ - CS_enableInterrupt -#endif -#ifdef ROM_CS_disableInterrupt -#define MAP_CS_disableInterrupt \ - ROM_CS_disableInterrupt -#else -#define MAP_CS_disableInterrupt \ - CS_disableInterrupt -#endif -#ifdef ROM_CS_getEnabledInterruptStatus -#define MAP_CS_getEnabledInterruptStatus \ - ROM_CS_getEnabledInterruptStatus -#else -#define MAP_CS_getEnabledInterruptStatus \ - CS_getEnabledInterruptStatus -#endif -#ifdef ROM_CS_getInterruptStatus -#define MAP_CS_getInterruptStatus \ - ROM_CS_getInterruptStatus -#else -#define MAP_CS_getInterruptStatus \ - CS_getInterruptStatus -#endif -#ifdef ROM_CS_setDCOFrequency -#define MAP_CS_setDCOFrequency \ - ROM_CS_setDCOFrequency -#else -#define MAP_CS_setDCOFrequency \ - CS_setDCOFrequency -#endif -#ifdef ROM_CS_getDCOFrequency -#define MAP_CS_getDCOFrequency \ - ROM_CS_getDCOFrequency -#else -#define MAP_CS_getDCOFrequency \ - CS_getDCOFrequency -#endif -#ifdef ROM_CS_enableFaultCounter -#define MAP_CS_enableFaultCounter \ - ROM_CS_enableFaultCounter -#else -#define MAP_CS_enableFaultCounter \ - CS_enableFaultCounter -#endif -#ifdef ROM_CS_disableFaultCounter -#define MAP_CS_disableFaultCounter \ - ROM_CS_disableFaultCounter -#else -#define MAP_CS_disableFaultCounter \ - CS_disableFaultCounter -#endif -#ifdef ROM_CS_resetFaultCounter -#define MAP_CS_resetFaultCounter \ - ROM_CS_resetFaultCounter -#else -#define MAP_CS_resetFaultCounter \ - CS_resetFaultCounter -#endif -#ifdef ROM_CS_startFaultCounter -#define MAP_CS_startFaultCounter \ - ROM_CS_startFaultCounter -#else -#define MAP_CS_startFaultCounter \ - CS_startFaultCounter -#endif -#ifdef ROM_CS_registerInterrupt -#define MAP_CS_registerInterrupt \ - ROM_CS_registerInterrupt -#else -#define MAP_CS_registerInterrupt \ - CS_registerInterrupt -#endif -#ifdef ROM_CS_unregisterInterrupt -#define MAP_CS_unregisterInterrupt \ - ROM_CS_unregisterInterrupt -#else -#define MAP_CS_unregisterInterrupt \ - CS_unregisterInterrupt -#endif -#ifdef ROM_CS_clearInterruptFlag -#define MAP_CS_clearInterruptFlag \ - ROM_CS_clearInterruptFlag -#else -#define MAP_CS_clearInterruptFlag \ - CS_clearInterruptFlag -#endif -#ifdef ROM_CS_getACLK -#define MAP_CS_getACLK \ - ROM_CS_getACLK -#else -#define MAP_CS_getACLK \ - CS_getACLK -#endif -#ifdef ROM_CS_getSMCLK -#define MAP_CS_getSMCLK \ - ROM_CS_getSMCLK -#else -#define MAP_CS_getSMCLK \ - CS_getSMCLK -#endif -#ifdef ROM_CS_getMCLK -#define MAP_CS_getMCLK \ - ROM_CS_getMCLK -#else -#define MAP_CS_getMCLK \ - CS_getMCLK -#endif -#ifdef ROM_CS_getBCLK -#define MAP_CS_getBCLK \ - ROM_CS_getBCLK -#else -#define MAP_CS_getBCLK \ - CS_getBCLK -#endif -#ifdef ROM_CS_getHSMCLK -#define MAP_CS_getHSMCLK \ - ROM_CS_getHSMCLK -#else -#define MAP_CS_getHSMCLK \ - CS_getHSMCLK -#endif -#ifdef ROM_CS_startHFXT -#define MAP_CS_startHFXT \ - ROM_CS_startHFXT -#else -#define MAP_CS_startHFXT \ - CS_startHFXT -#endif -#ifdef ROM_CS_startHFXTWithTimeout -#define MAP_CS_startHFXTWithTimeout \ - ROM_CS_startHFXTWithTimeout -#else -#define MAP_CS_startHFXTWithTimeout \ - CS_startHFXTWithTimeout -#endif -#ifdef ROM_CS_startLFXT -#define MAP_CS_startLFXT \ - ROM_CS_startLFXT -#else -#define MAP_CS_startLFXT \ - CS_startLFXT -#endif -#ifdef ROM_CS_startLFXTWithTimeout -#define MAP_CS_startLFXTWithTimeout \ - ROM_CS_startLFXTWithTimeout -#else -#define MAP_CS_startLFXTWithTimeout \ - CS_startLFXTWithTimeout -#endif -#ifdef ROM_CS_setExternalClockSourceFrequency -#define MAP_CS_setExternalClockSourceFrequency \ - ROM_CS_setExternalClockSourceFrequency -#else -#define MAP_CS_setExternalClockSourceFrequency \ - CS_setExternalClockSourceFrequency -#endif -#ifdef ROM_CS_setDCOExternalResistorCalibration -#define MAP_CS_setDCOExternalResistorCalibration \ - ROM_CS_setDCOExternalResistorCalibration -#else -#define MAP_CS_setDCOExternalResistorCalibration \ - CS_setDCOExternalResistorCalibration -#endif - -//***************************************************************************** -// -// Macros for the DMA API. -// -//***************************************************************************** -#ifdef ROM_DMA_enableModule -#define MAP_DMA_enableModule \ - ROM_DMA_enableModule -#else -#define MAP_DMA_enableModule \ - DMA_enableModule -#endif -#ifdef ROM_DMA_disableModule -#define MAP_DMA_disableModule \ - ROM_DMA_disableModule -#else -#define MAP_DMA_disableModule \ - DMA_disableModule -#endif -#ifdef ROM_DMA_getErrorStatus -#define MAP_DMA_getErrorStatus \ - ROM_DMA_getErrorStatus -#else -#define MAP_DMA_getErrorStatus \ - DMA_getErrorStatus -#endif -#ifdef ROM_DMA_clearErrorStatus -#define MAP_DMA_clearErrorStatus \ - ROM_DMA_clearErrorStatus -#else -#define MAP_DMA_clearErrorStatus \ - DMA_clearErrorStatus -#endif -#ifdef ROM_DMA_enableChannel -#define MAP_DMA_enableChannel \ - ROM_DMA_enableChannel -#else -#define MAP_DMA_enableChannel \ - DMA_enableChannel -#endif -#ifdef ROM_DMA_disableChannel -#define MAP_DMA_disableChannel \ - ROM_DMA_disableChannel -#else -#define MAP_DMA_disableChannel \ - DMA_disableChannel -#endif -#ifdef ROM_DMA_isChannelEnabled -#define MAP_DMA_isChannelEnabled \ - ROM_DMA_isChannelEnabled -#else -#define MAP_DMA_isChannelEnabled \ - DMA_isChannelEnabled -#endif -#ifdef ROM_DMA_setControlBase -#define MAP_DMA_setControlBase \ - ROM_DMA_setControlBase -#else -#define MAP_DMA_setControlBase \ - DMA_setControlBase -#endif -#ifdef ROM_DMA_getControlBase -#define MAP_DMA_getControlBase \ - ROM_DMA_getControlBase -#else -#define MAP_DMA_getControlBase \ - DMA_getControlBase -#endif -#ifdef ROM_DMA_getControlAlternateBase -#define MAP_DMA_getControlAlternateBase \ - ROM_DMA_getControlAlternateBase -#else -#define MAP_DMA_getControlAlternateBase \ - DMA_getControlAlternateBase -#endif -#ifdef ROM_DMA_requestChannel -#define MAP_DMA_requestChannel \ - ROM_DMA_requestChannel -#else -#define MAP_DMA_requestChannel \ - DMA_requestChannel -#endif -#ifdef ROM_DMA_enableChannelAttribute -#define MAP_DMA_enableChannelAttribute \ - ROM_DMA_enableChannelAttribute -#else -#define MAP_DMA_enableChannelAttribute \ - DMA_enableChannelAttribute -#endif -#ifdef ROM_DMA_disableChannelAttribute -#define MAP_DMA_disableChannelAttribute \ - ROM_DMA_disableChannelAttribute -#else -#define MAP_DMA_disableChannelAttribute \ - DMA_disableChannelAttribute -#endif -#ifdef ROM_DMA_getChannelAttribute -#define MAP_DMA_getChannelAttribute \ - ROM_DMA_getChannelAttribute -#else -#define MAP_DMA_getChannelAttribute \ - DMA_getChannelAttribute -#endif -#ifdef ROM_DMA_setChannelControl -#define MAP_DMA_setChannelControl \ - ROM_DMA_setChannelControl -#else -#define MAP_DMA_setChannelControl \ - DMA_setChannelControl -#endif -#ifdef ROM_DMA_setChannelTransfer -#define MAP_DMA_setChannelTransfer \ - ROM_DMA_setChannelTransfer -#else -#define MAP_DMA_setChannelTransfer \ - DMA_setChannelTransfer -#endif -#ifdef ROM_DMA_setChannelScatterGather -#define MAP_DMA_setChannelScatterGather \ - ROM_DMA_setChannelScatterGather -#else -#define MAP_DMA_setChannelScatterGather \ - DMA_setChannelScatterGather -#endif -#ifdef ROM_DMA_getChannelSize -#define MAP_DMA_getChannelSize \ - ROM_DMA_getChannelSize -#else -#define MAP_DMA_getChannelSize \ - DMA_getChannelSize -#endif -#ifdef ROM_DMA_getChannelMode -#define MAP_DMA_getChannelMode \ - ROM_DMA_getChannelMode -#else -#define MAP_DMA_getChannelMode \ - DMA_getChannelMode -#endif -#ifdef ROM_DMA_assignChannel -#define MAP_DMA_assignChannel \ - ROM_DMA_assignChannel -#else -#define MAP_DMA_assignChannel \ - DMA_assignChannel -#endif -#ifdef ROM_DMA_requestSoftwareTransfer -#define MAP_DMA_requestSoftwareTransfer \ - ROM_DMA_requestSoftwareTransfer -#else -#define MAP_DMA_requestSoftwareTransfer \ - DMA_requestSoftwareTransfer -#endif -#ifdef ROM_DMA_assignInterrupt -#define MAP_DMA_assignInterrupt \ - ROM_DMA_assignInterrupt -#else -#define MAP_DMA_assignInterrupt \ - DMA_assignInterrupt -#endif -#ifdef ROM_DMA_enableInterrupt -#define MAP_DMA_enableInterrupt \ - ROM_DMA_enableInterrupt -#else -#define MAP_DMA_enableInterrupt \ - DMA_enableInterrupt -#endif -#ifdef ROM_DMA_disableInterrupt -#define MAP_DMA_disableInterrupt \ - ROM_DMA_disableInterrupt -#else -#define MAP_DMA_disableInterrupt \ - DMA_disableInterrupt -#endif -#ifdef ROM_DMA_getInterruptStatus -#define MAP_DMA_getInterruptStatus \ - ROM_DMA_getInterruptStatus -#else -#define MAP_DMA_getInterruptStatus \ - DMA_getInterruptStatus -#endif -#ifdef ROM_DMA_clearInterruptFlag -#define MAP_DMA_clearInterruptFlag \ - ROM_DMA_clearInterruptFlag -#else -#define MAP_DMA_clearInterruptFlag \ - DMA_clearInterruptFlag -#endif -#ifdef ROM_DMA_registerInterrupt -#define MAP_DMA_registerInterrupt \ - ROM_DMA_registerInterrupt -#else -#define MAP_DMA_registerInterrupt \ - DMA_registerInterrupt -#endif -#ifdef ROM_DMA_unregisterInterrupt -#define MAP_DMA_unregisterInterrupt \ - ROM_DMA_unregisterInterrupt -#else -#define MAP_DMA_unregisterInterrupt \ - DMA_unregisterInterrupt -#endif - -//***************************************************************************** -// -// Macros for the Flash API. -// -//***************************************************************************** -#ifdef ROM_FlashCtl_enableReadParityCheck -#define MAP_FlashCtl_enableReadParityCheck \ - ROM_FlashCtl_enableReadParityCheck -#else -#define MAP_FlashCtl_enableReadParityCheck \ - FlashCtl_enableReadParityCheck -#endif -#ifdef ROM_FlashCtl_disableReadParityCheck -#define MAP_FlashCtl_disableReadParityCheck \ - ROM_FlashCtl_disableReadParityCheck -#else -#define MAP_FlashCtl_disableReadParityCheck \ - FlashCtl_disableReadParityCheck -#endif -#ifdef ROM_FlashCtl_enableReadBuffering -#define MAP_FlashCtl_enableReadBuffering \ - ROM_FlashCtl_enableReadBuffering -#else -#define MAP_FlashCtl_enableReadBuffering \ - FlashCtl_enableReadBuffering -#endif -#ifdef ROM_FlashCtl_disableReadBuffering -#define MAP_FlashCtl_disableReadBuffering \ - ROM_FlashCtl_disableReadBuffering -#else -#define MAP_FlashCtl_disableReadBuffering \ - FlashCtl_disableReadBuffering -#endif -#ifdef ROM_FlashCtl_unprotectSector -#define MAP_FlashCtl_unprotectSector \ - ROM_FlashCtl_unprotectSector -#else -#define MAP_FlashCtl_unprotectSector \ - FlashCtl_unprotectSector -#endif -#ifdef ROM_FlashCtl_protectSector -#define MAP_FlashCtl_protectSector \ - ROM_FlashCtl_protectSector -#else -#define MAP_FlashCtl_protectSector \ - FlashCtl_protectSector -#endif -#ifdef ROM_FlashCtl_isSectorProtected -#define MAP_FlashCtl_isSectorProtected \ - ROM_FlashCtl_isSectorProtected -#else -#define MAP_FlashCtl_isSectorProtected \ - FlashCtl_isSectorProtected -#endif -#ifdef ROM_FlashCtl_verifyMemory -#define MAP_FlashCtl_verifyMemory \ - ROM_FlashCtl_verifyMemory -#else -#define MAP_FlashCtl_verifyMemory \ - FlashCtl_verifyMemory -#endif -#ifdef ROM_FlashCtl_performMassErase -#define MAP_FlashCtl_performMassErase \ - ROM_FlashCtl_performMassErase -#else -#define MAP_FlashCtl_performMassErase \ - FlashCtl_performMassErase -#endif -#ifdef ROM_FlashCtl_eraseSector -#define MAP_FlashCtl_eraseSector \ - ROM_FlashCtl_eraseSector -#else -#define MAP_FlashCtl_eraseSector \ - FlashCtl_eraseSector -#endif -#ifdef ROM_FlashCtl_programMemory -#define MAP_FlashCtl_programMemory \ - ROM_FlashCtl_programMemory -#else -#define MAP_FlashCtl_programMemory \ - FlashCtl_programMemory -#endif -#ifdef ROM_FlashCtl_setProgramVerification -#define MAP_FlashCtl_setProgramVerification \ - ROM_FlashCtl_setProgramVerification -#else -#define MAP_FlashCtl_setProgramVerification \ - FlashCtl_setProgramVerification -#endif -#ifdef ROM_FlashCtl_clearProgramVerification -#define MAP_FlashCtl_clearProgramVerification \ - ROM_FlashCtl_clearProgramVerification -#else -#define MAP_FlashCtl_clearProgramVerification \ - FlashCtl_clearProgramVerification -#endif -#ifdef ROM_FlashCtl_enableWordProgramming -#define MAP_FlashCtl_enableWordProgramming \ - ROM_FlashCtl_enableWordProgramming -#else -#define MAP_FlashCtl_enableWordProgramming \ - FlashCtl_enableWordProgramming -#endif -#ifdef ROM_FlashCtl_disableWordProgramming -#define MAP_FlashCtl_disableWordProgramming \ - ROM_FlashCtl_disableWordProgramming -#else -#define MAP_FlashCtl_disableWordProgramming \ - FlashCtl_disableWordProgramming -#endif -#ifdef ROM_FlashCtl_isWordProgrammingEnabled -#define MAP_FlashCtl_isWordProgrammingEnabled \ - ROM_FlashCtl_isWordProgrammingEnabled -#else -#define MAP_FlashCtl_isWordProgrammingEnabled \ - FlashCtl_isWordProgrammingEnabled -#endif -#ifdef ROM_FlashCtl_enableInterrupt -#define MAP_FlashCtl_enableInterrupt \ - ROM_FlashCtl_enableInterrupt -#else -#define MAP_FlashCtl_enableInterrupt \ - FlashCtl_enableInterrupt -#endif -#ifdef ROM_FlashCtl_disableInterrupt -#define MAP_FlashCtl_disableInterrupt \ - ROM_FlashCtl_disableInterrupt -#else -#define MAP_FlashCtl_disableInterrupt \ - FlashCtl_disableInterrupt -#endif -#ifdef ROM_FlashCtl_getEnabledInterruptStatus -#define MAP_FlashCtl_getEnabledInterruptStatus \ - ROM_FlashCtl_getEnabledInterruptStatus -#else -#define MAP_FlashCtl_getEnabledInterruptStatus \ - FlashCtl_getEnabledInterruptStatus -#endif -#ifdef ROM_FlashCtl_getInterruptStatus -#define MAP_FlashCtl_getInterruptStatus \ - ROM_FlashCtl_getInterruptStatus -#else -#define MAP_FlashCtl_getInterruptStatus \ - FlashCtl_getInterruptStatus -#endif -#ifdef ROM_FlashCtl_clearInterruptFlag -#define MAP_FlashCtl_clearInterruptFlag \ - ROM_FlashCtl_clearInterruptFlag -#else -#define MAP_FlashCtl_clearInterruptFlag \ - FlashCtl_clearInterruptFlag -#endif -#ifdef ROM_FlashCtl_setWaitState -#define MAP_FlashCtl_setWaitState \ - ROM_FlashCtl_setWaitState -#else -#define MAP_FlashCtl_setWaitState \ - FlashCtl_setWaitState -#endif -#ifdef ROM_FlashCtl_getWaitState -#define MAP_FlashCtl_getWaitState \ - ROM_FlashCtl_getWaitState -#else -#define MAP_FlashCtl_getWaitState \ - FlashCtl_getWaitState -#endif -#ifdef ROM_FlashCtl_setReadMode -#define MAP_FlashCtl_setReadMode \ - ROM_FlashCtl_setReadMode -#else -#define MAP_FlashCtl_setReadMode \ - FlashCtl_setReadMode -#endif -#ifdef ROM_FlashCtl_getReadMode -#define MAP_FlashCtl_getReadMode \ - ROM_FlashCtl_getReadMode -#else -#define MAP_FlashCtl_getReadMode \ - FlashCtl_getReadMode -#endif -#ifdef ROM_FlashCtl_registerInterrupt -#define MAP_FlashCtl_registerInterrupt \ - ROM_FlashCtl_registerInterrupt -#else -#define MAP_FlashCtl_registerInterrupt \ - FlashCtl_registerInterrupt -#endif -#ifdef ROM_FlashCtl_unregisterInterrupt -#define MAP_FlashCtl_unregisterInterrupt \ - ROM_FlashCtl_unregisterInterrupt -#else -#define MAP_FlashCtl_unregisterInterrupt \ - FlashCtl_unregisterInterrupt -#endif -#ifdef ROM___FlashCtl_remaskData8Post -#define MAP___FlashCtl_remaskData8Post \ - ROM___FlashCtl_remaskData8Post -#else -#define MAP___FlashCtl_remaskData8Post \ - __FlashCtl_remaskData8Post -#endif -#ifdef ROM___FlashCtl_remaskData8Pre -#define MAP___FlashCtl_remaskData8Pre \ - ROM___FlashCtl_remaskData8Pre -#else -#define MAP___FlashCtl_remaskData8Pre \ - __FlashCtl_remaskData8Pre -#endif -#ifdef ROM___FlashCtl_remaskData32Pre -#define MAP___FlashCtl_remaskData32Pre \ - ROM___FlashCtl_remaskData32Pre -#else -#define MAP___FlashCtl_remaskData32Pre \ - __FlashCtl_remaskData32Pre -#endif -#ifdef ROM___FlashCtl_remaskData32Post -#define MAP___FlashCtl_remaskData32Post \ - ROM___FlashCtl_remaskData32Post -#else -#define MAP___FlashCtl_remaskData32Post \ - __FlashCtl_remaskData32Post -#endif -#ifdef ROM___FlashCtl_remaskBurstDataPre -#define MAP___FlashCtl_remaskBurstDataPre \ - ROM___FlashCtl_remaskBurstDataPre -#else -#define MAP___FlashCtl_remaskBurstDataPre \ - __FlashCtl_remaskBurstDataPre -#endif -#ifdef ROM___FlashCtl_remaskBurstDataPost -#define MAP___FlashCtl_remaskBurstDataPost \ - ROM___FlashCtl_remaskBurstDataPost -#else -#define MAP___FlashCtl_remaskBurstDataPost \ - __FlashCtl_remaskBurstDataPost -#endif -#ifdef ROM_FlashCtl_initiateSectorErase -#define MAP_FlashCtl_initiateSectorErase \ - ROM_FlashCtl_initiateSectorErase -#else -#define MAP_FlashCtl_initiateSectorErase \ - FlashCtl_initiateSectorErase -#endif -#ifdef ROM_FlashCtl_initiateMassErase -#define MAP_FlashCtl_initiateMassErase \ - ROM_FlashCtl_initiateMassErase -#else -#define MAP_FlashCtl_initiateMassErase \ - FlashCtl_initiateMassErase -#endif -#ifdef ROM_FlashCtl_getMemoryInfo -#define MAP_FlashCtl_getMemoryInfo \ - ROM_FlashCtl_getMemoryInfo -#else -#define MAP_FlashCtl_getMemoryInfo \ - FlashCtl_getMemoryInfo -#endif - -//***************************************************************************** -// -// Macros for the FPU API. -// -//***************************************************************************** -#ifdef ROM_FPU_enableModule -#define MAP_FPU_enableModule \ - ROM_FPU_enableModule -#else -#define MAP_FPU_enableModule \ - FPU_enableModule -#endif -#ifdef ROM_FPU_disableModule -#define MAP_FPU_disableModule \ - ROM_FPU_disableModule -#else -#define MAP_FPU_disableModule \ - FPU_disableModule -#endif -#ifdef ROM_FPU_enableStacking -#define MAP_FPU_enableStacking \ - ROM_FPU_enableStacking -#else -#define MAP_FPU_enableStacking \ - FPU_enableStacking -#endif -#ifdef ROM_FPU_enableLazyStacking -#define MAP_FPU_enableLazyStacking \ - ROM_FPU_enableLazyStacking -#else -#define MAP_FPU_enableLazyStacking \ - FPU_enableLazyStacking -#endif -#ifdef ROM_FPU_disableStacking -#define MAP_FPU_disableStacking \ - ROM_FPU_disableStacking -#else -#define MAP_FPU_disableStacking \ - FPU_disableStacking -#endif -#ifdef ROM_FPU_setHalfPrecisionMode -#define MAP_FPU_setHalfPrecisionMode \ - ROM_FPU_setHalfPrecisionMode -#else -#define MAP_FPU_setHalfPrecisionMode \ - FPU_setHalfPrecisionMode -#endif -#ifdef ROM_FPU_setNaNMode -#define MAP_FPU_setNaNMode \ - ROM_FPU_setNaNMode -#else -#define MAP_FPU_setNaNMode \ - FPU_setNaNMode -#endif -#ifdef ROM_FPU_setFlushToZeroMode -#define MAP_FPU_setFlushToZeroMode \ - ROM_FPU_setFlushToZeroMode -#else -#define MAP_FPU_setFlushToZeroMode \ - FPU_setFlushToZeroMode -#endif -#ifdef ROM_FPU_setRoundingMode -#define MAP_FPU_setRoundingMode \ - ROM_FPU_setRoundingMode -#else -#define MAP_FPU_setRoundingMode \ - FPU_setRoundingMode -#endif - -//***************************************************************************** -// -// Macros for the GPIO API. -// -//***************************************************************************** -#ifdef ROM_GPIO_setAsOutputPin -#define MAP_GPIO_setAsOutputPin \ - ROM_GPIO_setAsOutputPin -#else -#define MAP_GPIO_setAsOutputPin \ - GPIO_setAsOutputPin -#endif -#ifdef ROM_GPIO_setOutputHighOnPin -#define MAP_GPIO_setOutputHighOnPin \ - ROM_GPIO_setOutputHighOnPin -#else -#define MAP_GPIO_setOutputHighOnPin \ - GPIO_setOutputHighOnPin -#endif -#ifdef ROM_GPIO_setOutputLowOnPin -#define MAP_GPIO_setOutputLowOnPin \ - ROM_GPIO_setOutputLowOnPin -#else -#define MAP_GPIO_setOutputLowOnPin \ - GPIO_setOutputLowOnPin -#endif -#ifdef ROM_GPIO_toggleOutputOnPin -#define MAP_GPIO_toggleOutputOnPin \ - ROM_GPIO_toggleOutputOnPin -#else -#define MAP_GPIO_toggleOutputOnPin \ - GPIO_toggleOutputOnPin -#endif -#ifdef ROM_GPIO_setAsInputPinWithPullDownResistor -#define MAP_GPIO_setAsInputPinWithPullDownResistor \ - ROM_GPIO_setAsInputPinWithPullDownResistor -#else -#define MAP_GPIO_setAsInputPinWithPullDownResistor \ - GPIO_setAsInputPinWithPullDownResistor -#endif -#ifdef ROM_GPIO_setAsInputPinWithPullUpResistor -#define MAP_GPIO_setAsInputPinWithPullUpResistor \ - ROM_GPIO_setAsInputPinWithPullUpResistor -#else -#define MAP_GPIO_setAsInputPinWithPullUpResistor \ - GPIO_setAsInputPinWithPullUpResistor -#endif -#ifdef ROM_GPIO_setAsPeripheralModuleFunctionOutputPin -#define MAP_GPIO_setAsPeripheralModuleFunctionOutputPin \ - ROM_GPIO_setAsPeripheralModuleFunctionOutputPin -#else -#define MAP_GPIO_setAsPeripheralModuleFunctionOutputPin \ - GPIO_setAsPeripheralModuleFunctionOutputPin -#endif -#ifdef ROM_GPIO_setAsPeripheralModuleFunctionInputPin -#define MAP_GPIO_setAsPeripheralModuleFunctionInputPin \ - ROM_GPIO_setAsPeripheralModuleFunctionInputPin -#else -#define MAP_GPIO_setAsPeripheralModuleFunctionInputPin \ - GPIO_setAsPeripheralModuleFunctionInputPin -#endif -#ifdef ROM_GPIO_getInputPinValue -#define MAP_GPIO_getInputPinValue \ - ROM_GPIO_getInputPinValue -#else -#define MAP_GPIO_getInputPinValue \ - GPIO_getInputPinValue -#endif -#ifdef ROM_GPIO_interruptEdgeSelect -#define MAP_GPIO_interruptEdgeSelect \ - ROM_GPIO_interruptEdgeSelect -#else -#define MAP_GPIO_interruptEdgeSelect \ - GPIO_interruptEdgeSelect -#endif -#ifdef ROM_GPIO_enableInterrupt -#define MAP_GPIO_enableInterrupt \ - ROM_GPIO_enableInterrupt -#else -#define MAP_GPIO_enableInterrupt \ - GPIO_enableInterrupt -#endif -#ifdef ROM_GPIO_disableInterrupt -#define MAP_GPIO_disableInterrupt \ - ROM_GPIO_disableInterrupt -#else -#define MAP_GPIO_disableInterrupt \ - GPIO_disableInterrupt -#endif -#ifdef ROM_GPIO_getInterruptStatus -#define MAP_GPIO_getInterruptStatus \ - ROM_GPIO_getInterruptStatus -#else -#define MAP_GPIO_getInterruptStatus \ - GPIO_getInterruptStatus -#endif -#ifdef ROM_GPIO_clearInterruptFlag -#define MAP_GPIO_clearInterruptFlag \ - ROM_GPIO_clearInterruptFlag -#else -#define MAP_GPIO_clearInterruptFlag \ - GPIO_clearInterruptFlag -#endif -#ifdef ROM_GPIO_setAsInputPin -#define MAP_GPIO_setAsInputPin \ - ROM_GPIO_setAsInputPin -#else -#define MAP_GPIO_setAsInputPin \ - GPIO_setAsInputPin -#endif -#ifdef ROM_GPIO_getEnabledInterruptStatus -#define MAP_GPIO_getEnabledInterruptStatus \ - ROM_GPIO_getEnabledInterruptStatus -#else -#define MAP_GPIO_getEnabledInterruptStatus \ - GPIO_getEnabledInterruptStatus -#endif -#ifdef ROM_GPIO_setDriveStrengthHigh -#define MAP_GPIO_setDriveStrengthHigh \ - ROM_GPIO_setDriveStrengthHigh -#else -#define MAP_GPIO_setDriveStrengthHigh \ - GPIO_setDriveStrengthHigh -#endif -#ifdef ROM_GPIO_setDriveStrengthLow -#define MAP_GPIO_setDriveStrengthLow \ - ROM_GPIO_setDriveStrengthLow -#else -#define MAP_GPIO_setDriveStrengthLow \ - GPIO_setDriveStrengthLow -#endif -#ifdef ROM_GPIO_registerInterrupt -#define MAP_GPIO_registerInterrupt \ - ROM_GPIO_registerInterrupt -#else -#define MAP_GPIO_registerInterrupt \ - GPIO_registerInterrupt -#endif -#ifdef ROM_GPIO_unregisterInterrupt -#define MAP_GPIO_unregisterInterrupt \ - ROM_GPIO_unregisterInterrupt -#else -#define MAP_GPIO_unregisterInterrupt \ - GPIO_unregisterInterrupt -#endif - -//***************************************************************************** -// -// Macros for the I2C API. -// -//***************************************************************************** -#ifdef ROM_I2C_initMaster -#define MAP_I2C_initMaster \ - ROM_I2C_initMaster -#else -#define MAP_I2C_initMaster \ - I2C_initMaster -#endif -#ifdef ROM_I2C_initSlave -#define MAP_I2C_initSlave \ - ROM_I2C_initSlave -#else -#define MAP_I2C_initSlave \ - I2C_initSlave -#endif -#ifdef ROM_I2C_enableModule -#define MAP_I2C_enableModule \ - ROM_I2C_enableModule -#else -#define MAP_I2C_enableModule \ - I2C_enableModule -#endif -#ifdef ROM_I2C_disableModule -#define MAP_I2C_disableModule \ - ROM_I2C_disableModule -#else -#define MAP_I2C_disableModule \ - I2C_disableModule -#endif -#ifdef ROM_I2C_setSlaveAddress -#define MAP_I2C_setSlaveAddress \ - ROM_I2C_setSlaveAddress -#else -#define MAP_I2C_setSlaveAddress \ - I2C_setSlaveAddress -#endif -#ifdef ROM_I2C_setMode -#define MAP_I2C_setMode \ - ROM_I2C_setMode -#else -#define MAP_I2C_setMode \ - I2C_setMode -#endif -#ifdef ROM_I2C_slavePutData -#define MAP_I2C_slavePutData \ - ROM_I2C_slavePutData -#else -#define MAP_I2C_slavePutData \ - I2C_slavePutData -#endif -#ifdef ROM_I2C_slaveGetData -#define MAP_I2C_slaveGetData \ - ROM_I2C_slaveGetData -#else -#define MAP_I2C_slaveGetData \ - I2C_slaveGetData -#endif -#ifdef ROM_I2C_isBusBusy -#define MAP_I2C_isBusBusy \ - ROM_I2C_isBusBusy -#else -#define MAP_I2C_isBusBusy \ - I2C_isBusBusy -#endif -#ifdef ROM_I2C_masterSendSingleByte -#define MAP_I2C_masterSendSingleByte \ - ROM_I2C_masterSendSingleByte -#else -#define MAP_I2C_masterSendSingleByte \ - I2C_masterSendSingleByte -#endif -#ifdef ROM_I2C_masterSendSingleByteWithTimeout -#define MAP_I2C_masterSendSingleByteWithTimeout \ - ROM_I2C_masterSendSingleByteWithTimeout -#else -#define MAP_I2C_masterSendSingleByteWithTimeout \ - I2C_masterSendSingleByteWithTimeout -#endif -#ifdef ROM_I2C_masterSendMultiByteStart -#define MAP_I2C_masterSendMultiByteStart \ - ROM_I2C_masterSendMultiByteStart -#else -#define MAP_I2C_masterSendMultiByteStart \ - I2C_masterSendMultiByteStart -#endif -#ifdef ROM_I2C_masterSendMultiByteStartWithTimeout -#define MAP_I2C_masterSendMultiByteStartWithTimeout \ - ROM_I2C_masterSendMultiByteStartWithTimeout -#else -#define MAP_I2C_masterSendMultiByteStartWithTimeout \ - I2C_masterSendMultiByteStartWithTimeout -#endif -#ifdef ROM_I2C_masterSendMultiByteNext -#define MAP_I2C_masterSendMultiByteNext \ - ROM_I2C_masterSendMultiByteNext -#else -#define MAP_I2C_masterSendMultiByteNext \ - I2C_masterSendMultiByteNext -#endif -#ifdef ROM_I2C_masterSendMultiByteNextWithTimeout -#define MAP_I2C_masterSendMultiByteNextWithTimeout \ - ROM_I2C_masterSendMultiByteNextWithTimeout -#else -#define MAP_I2C_masterSendMultiByteNextWithTimeout \ - I2C_masterSendMultiByteNextWithTimeout -#endif -#ifdef ROM_I2C_masterSendMultiByteFinish -#define MAP_I2C_masterSendMultiByteFinish \ - ROM_I2C_masterSendMultiByteFinish -#else -#define MAP_I2C_masterSendMultiByteFinish \ - I2C_masterSendMultiByteFinish -#endif -#ifdef ROM_I2C_masterSendMultiByteFinishWithTimeout -#define MAP_I2C_masterSendMultiByteFinishWithTimeout \ - ROM_I2C_masterSendMultiByteFinishWithTimeout -#else -#define MAP_I2C_masterSendMultiByteFinishWithTimeout \ - I2C_masterSendMultiByteFinishWithTimeout -#endif -#ifdef ROM_I2C_masterSendMultiByteStop -#define MAP_I2C_masterSendMultiByteStop \ - ROM_I2C_masterSendMultiByteStop -#else -#define MAP_I2C_masterSendMultiByteStop \ - I2C_masterSendMultiByteStop -#endif -#ifdef ROM_I2C_masterSendMultiByteStopWithTimeout -#define MAP_I2C_masterSendMultiByteStopWithTimeout \ - ROM_I2C_masterSendMultiByteStopWithTimeout -#else -#define MAP_I2C_masterSendMultiByteStopWithTimeout \ - I2C_masterSendMultiByteStopWithTimeout -#endif -#ifdef ROM_I2C_masterReceiveStart -#define MAP_I2C_masterReceiveStart \ - ROM_I2C_masterReceiveStart -#else -#define MAP_I2C_masterReceiveStart \ - I2C_masterReceiveStart -#endif -#ifdef ROM_I2C_masterReceiveMultiByteNext -#define MAP_I2C_masterReceiveMultiByteNext \ - ROM_I2C_masterReceiveMultiByteNext -#else -#define MAP_I2C_masterReceiveMultiByteNext \ - I2C_masterReceiveMultiByteNext -#endif -#ifdef ROM_I2C_masterReceiveMultiByteFinish -#define MAP_I2C_masterReceiveMultiByteFinish \ - ROM_I2C_masterReceiveMultiByteFinish -#else -#define MAP_I2C_masterReceiveMultiByteFinish \ - I2C_masterReceiveMultiByteFinish -#endif -#ifdef ROM_I2C_masterReceiveMultiByteFinishWithTimeout -#define MAP_I2C_masterReceiveMultiByteFinishWithTimeout \ - ROM_I2C_masterReceiveMultiByteFinishWithTimeout -#else -#define MAP_I2C_masterReceiveMultiByteFinishWithTimeout \ - I2C_masterReceiveMultiByteFinishWithTimeout -#endif -#ifdef ROM_I2C_masterReceiveMultiByteStop -#define MAP_I2C_masterReceiveMultiByteStop \ - ROM_I2C_masterReceiveMultiByteStop -#else -#define MAP_I2C_masterReceiveMultiByteStop \ - I2C_masterReceiveMultiByteStop -#endif -#ifdef ROM_I2C_masterReceiveSingleByte -#define MAP_I2C_masterReceiveSingleByte \ - ROM_I2C_masterReceiveSingleByte -#else -#define MAP_I2C_masterReceiveSingleByte \ - I2C_masterReceiveSingleByte -#endif -#ifdef ROM_I2C_masterReceiveSingle -#define MAP_I2C_masterReceiveSingle \ - ROM_I2C_masterReceiveSingle -#else -#define MAP_I2C_masterReceiveSingle \ - I2C_masterReceiveSingle -#endif -#ifdef ROM_I2C_getReceiveBufferAddressForDMA -#define MAP_I2C_getReceiveBufferAddressForDMA \ - ROM_I2C_getReceiveBufferAddressForDMA -#else -#define MAP_I2C_getReceiveBufferAddressForDMA \ - I2C_getReceiveBufferAddressForDMA -#endif -#ifdef ROM_I2C_getTransmitBufferAddressForDMA -#define MAP_I2C_getTransmitBufferAddressForDMA \ - ROM_I2C_getTransmitBufferAddressForDMA -#else -#define MAP_I2C_getTransmitBufferAddressForDMA \ - I2C_getTransmitBufferAddressForDMA -#endif -#ifdef ROM_I2C_masterIsStopSent -#define MAP_I2C_masterIsStopSent \ - ROM_I2C_masterIsStopSent -#else -#define MAP_I2C_masterIsStopSent \ - I2C_masterIsStopSent -#endif -#ifdef ROM_I2C_masterIsStartSent -#define MAP_I2C_masterIsStartSent \ - ROM_I2C_masterIsStartSent -#else -#define MAP_I2C_masterIsStartSent \ - I2C_masterIsStartSent -#endif -#ifdef ROM_I2C_masterSendStart -#define MAP_I2C_masterSendStart \ - ROM_I2C_masterSendStart -#else -#define MAP_I2C_masterSendStart \ - I2C_masterSendStart -#endif -#ifdef ROM_I2C_enableMultiMasterMode -#define MAP_I2C_enableMultiMasterMode \ - ROM_I2C_enableMultiMasterMode -#else -#define MAP_I2C_enableMultiMasterMode \ - I2C_enableMultiMasterMode -#endif -#ifdef ROM_I2C_disableMultiMasterMode -#define MAP_I2C_disableMultiMasterMode \ - ROM_I2C_disableMultiMasterMode -#else -#define MAP_I2C_disableMultiMasterMode \ - I2C_disableMultiMasterMode -#endif -#ifdef ROM_I2C_enableInterrupt -#define MAP_I2C_enableInterrupt \ - ROM_I2C_enableInterrupt -#else -#define MAP_I2C_enableInterrupt \ - I2C_enableInterrupt -#endif -#ifdef ROM_I2C_disableInterrupt -#define MAP_I2C_disableInterrupt \ - ROM_I2C_disableInterrupt -#else -#define MAP_I2C_disableInterrupt \ - I2C_disableInterrupt -#endif -#ifdef ROM_I2C_clearInterruptFlag -#define MAP_I2C_clearInterruptFlag \ - ROM_I2C_clearInterruptFlag -#else -#define MAP_I2C_clearInterruptFlag \ - I2C_clearInterruptFlag -#endif -#ifdef ROM_I2C_getInterruptStatus -#define MAP_I2C_getInterruptStatus \ - ROM_I2C_getInterruptStatus -#else -#define MAP_I2C_getInterruptStatus \ - I2C_getInterruptStatus -#endif -#ifdef ROM_I2C_getEnabledInterruptStatus -#define MAP_I2C_getEnabledInterruptStatus \ - ROM_I2C_getEnabledInterruptStatus -#else -#define MAP_I2C_getEnabledInterruptStatus \ - I2C_getEnabledInterruptStatus -#endif -#ifdef ROM_I2C_getMode -#define MAP_I2C_getMode \ - ROM_I2C_getMode -#else -#define MAP_I2C_getMode \ - I2C_getMode -#endif -#ifdef ROM_I2C_registerInterrupt -#define MAP_I2C_registerInterrupt \ - ROM_I2C_registerInterrupt -#else -#define MAP_I2C_registerInterrupt \ - I2C_registerInterrupt -#endif -#ifdef ROM_I2C_unregisterInterrupt -#define MAP_I2C_unregisterInterrupt \ - ROM_I2C_unregisterInterrupt -#else -#define MAP_I2C_unregisterInterrupt \ - I2C_unregisterInterrupt -#endif -#ifdef ROM_I2C_slaveSendNAK -#define MAP_I2C_slaveSendNAK \ - ROM_I2C_slaveSendNAK -#else -#define MAP_I2C_slaveSendNAK \ - I2C_slaveSendNAK -#endif - -//***************************************************************************** -// -// Macros for the Interrupt API. -// -//***************************************************************************** -#ifdef ROM_Interrupt_enableMaster -#define MAP_Interrupt_enableMaster \ - ROM_Interrupt_enableMaster -#else -#define MAP_Interrupt_enableMaster \ - Interrupt_enableMaster -#endif -#ifdef ROM_Interrupt_disableMaster -#define MAP_Interrupt_disableMaster \ - ROM_Interrupt_disableMaster -#else -#define MAP_Interrupt_disableMaster \ - Interrupt_disableMaster -#endif -#ifdef ROM_Interrupt_setPriorityGrouping -#define MAP_Interrupt_setPriorityGrouping \ - ROM_Interrupt_setPriorityGrouping -#else -#define MAP_Interrupt_setPriorityGrouping \ - Interrupt_setPriorityGrouping -#endif -#ifdef ROM_Interrupt_getPriorityGrouping -#define MAP_Interrupt_getPriorityGrouping \ - ROM_Interrupt_getPriorityGrouping -#else -#define MAP_Interrupt_getPriorityGrouping \ - Interrupt_getPriorityGrouping -#endif -#ifdef ROM_Interrupt_setPriority -#define MAP_Interrupt_setPriority \ - ROM_Interrupt_setPriority -#else -#define MAP_Interrupt_setPriority \ - Interrupt_setPriority -#endif -#ifdef ROM_Interrupt_getPriority -#define MAP_Interrupt_getPriority \ - ROM_Interrupt_getPriority -#else -#define MAP_Interrupt_getPriority \ - Interrupt_getPriority -#endif -#ifdef ROM_Interrupt_enableInterrupt -#define MAP_Interrupt_enableInterrupt \ - ROM_Interrupt_enableInterrupt -#else -#define MAP_Interrupt_enableInterrupt \ - Interrupt_enableInterrupt -#endif -#ifdef ROM_Interrupt_disableInterrupt -#define MAP_Interrupt_disableInterrupt \ - ROM_Interrupt_disableInterrupt -#else -#define MAP_Interrupt_disableInterrupt \ - Interrupt_disableInterrupt -#endif -#ifdef ROM_Interrupt_isEnabled -#define MAP_Interrupt_isEnabled \ - ROM_Interrupt_isEnabled -#else -#define MAP_Interrupt_isEnabled \ - Interrupt_isEnabled -#endif -#ifdef ROM_Interrupt_pendInterrupt -#define MAP_Interrupt_pendInterrupt \ - ROM_Interrupt_pendInterrupt -#else -#define MAP_Interrupt_pendInterrupt \ - Interrupt_pendInterrupt -#endif -#ifdef ROM_Interrupt_setPriorityMask -#define MAP_Interrupt_setPriorityMask \ - ROM_Interrupt_setPriorityMask -#else -#define MAP_Interrupt_setPriorityMask \ - Interrupt_setPriorityMask -#endif -#ifdef ROM_Interrupt_getPriorityMask -#define MAP_Interrupt_getPriorityMask \ - ROM_Interrupt_getPriorityMask -#else -#define MAP_Interrupt_getPriorityMask \ - Interrupt_getPriorityMask -#endif -#ifdef ROM_Interrupt_setVectorTableAddress -#define MAP_Interrupt_setVectorTableAddress \ - ROM_Interrupt_setVectorTableAddress -#else -#define MAP_Interrupt_setVectorTableAddress \ - Interrupt_setVectorTableAddress -#endif -#ifdef ROM_Interrupt_getVectorTableAddress -#define MAP_Interrupt_getVectorTableAddress \ - ROM_Interrupt_getVectorTableAddress -#else -#define MAP_Interrupt_getVectorTableAddress \ - Interrupt_getVectorTableAddress -#endif -#ifdef ROM_Interrupt_enableSleepOnIsrExit -#define MAP_Interrupt_enableSleepOnIsrExit \ - ROM_Interrupt_enableSleepOnIsrExit -#else -#define MAP_Interrupt_enableSleepOnIsrExit \ - Interrupt_enableSleepOnIsrExit -#endif -#ifdef ROM_Interrupt_disableSleepOnIsrExit -#define MAP_Interrupt_disableSleepOnIsrExit \ - ROM_Interrupt_disableSleepOnIsrExit -#else -#define MAP_Interrupt_disableSleepOnIsrExit \ - Interrupt_disableSleepOnIsrExit -#endif -#ifdef ROM_Interrupt_registerInterrupt -#define MAP_Interrupt_registerInterrupt \ - ROM_Interrupt_registerInterrupt -#else -#define MAP_Interrupt_registerInterrupt \ - Interrupt_registerInterrupt -#endif -#ifdef ROM_Interrupt_unregisterInterrupt -#define MAP_Interrupt_unregisterInterrupt \ - ROM_Interrupt_unregisterInterrupt -#else -#define MAP_Interrupt_unregisterInterrupt \ - Interrupt_unregisterInterrupt -#endif -#ifdef ROM_Interrupt_unpendInterrupt -#define MAP_Interrupt_unpendInterrupt \ - ROM_Interrupt_unpendInterrupt -#else -#define MAP_Interrupt_unpendInterrupt \ - Interrupt_unpendInterrupt -#endif - -//***************************************************************************** -// -// Macros for the MPU API. -// -//***************************************************************************** -#ifdef ROM_MPU_enableModule -#define MAP_MPU_enableModule \ - ROM_MPU_enableModule -#else -#define MAP_MPU_enableModule \ - MPU_enableModule -#endif -#ifdef ROM_MPU_disableModule -#define MAP_MPU_disableModule \ - ROM_MPU_disableModule -#else -#define MAP_MPU_disableModule \ - MPU_disableModule -#endif -#ifdef ROM_MPU_getRegionCount -#define MAP_MPU_getRegionCount \ - ROM_MPU_getRegionCount -#else -#define MAP_MPU_getRegionCount \ - MPU_getRegionCount -#endif -#ifdef ROM_MPU_enableRegion -#define MAP_MPU_enableRegion \ - ROM_MPU_enableRegion -#else -#define MAP_MPU_enableRegion \ - MPU_enableRegion -#endif -#ifdef ROM_MPU_disableRegion -#define MAP_MPU_disableRegion \ - ROM_MPU_disableRegion -#else -#define MAP_MPU_disableRegion \ - MPU_disableRegion -#endif -#ifdef ROM_MPU_setRegion -#define MAP_MPU_setRegion \ - ROM_MPU_setRegion -#else -#define MAP_MPU_setRegion \ - MPU_setRegion -#endif -#ifdef ROM_MPU_getRegion -#define MAP_MPU_getRegion \ - ROM_MPU_getRegion -#else -#define MAP_MPU_getRegion \ - MPU_getRegion -#endif -#ifdef ROM_MPU_enableInterrupt -#define MAP_MPU_enableInterrupt \ - ROM_MPU_enableInterrupt -#else -#define MAP_MPU_enableInterrupt \ - MPU_enableInterrupt -#endif -#ifdef ROM_MPU_disableInterrupt -#define MAP_MPU_disableInterrupt \ - ROM_MPU_disableInterrupt -#else -#define MAP_MPU_disableInterrupt \ - MPU_disableInterrupt -#endif -#ifdef ROM_MPU_registerInterrupt -#define MAP_MPU_registerInterrupt \ - ROM_MPU_registerInterrupt -#else -#define MAP_MPU_registerInterrupt \ - MPU_registerInterrupt -#endif -#ifdef ROM_MPU_unregisterInterrupt -#define MAP_MPU_unregisterInterrupt \ - ROM_MPU_unregisterInterrupt -#else -#define MAP_MPU_unregisterInterrupt \ - MPU_unregisterInterrupt -#endif - -//***************************************************************************** -// -// Macros for the PCM API. -// -//***************************************************************************** -#ifdef ROM_PCM_setCoreVoltageLevel -#define MAP_PCM_setCoreVoltageLevel \ - ROM_PCM_setCoreVoltageLevel -#else -#define MAP_PCM_setCoreVoltageLevel \ - PCM_setCoreVoltageLevel -#endif -#ifdef ROM_PCM_getCoreVoltageLevel -#define MAP_PCM_getCoreVoltageLevel \ - ROM_PCM_getCoreVoltageLevel -#else -#define MAP_PCM_getCoreVoltageLevel \ - PCM_getCoreVoltageLevel -#endif -#ifdef ROM_PCM_setCoreVoltageLevelWithTimeout -#define MAP_PCM_setCoreVoltageLevelWithTimeout \ - ROM_PCM_setCoreVoltageLevelWithTimeout -#else -#define MAP_PCM_setCoreVoltageLevelWithTimeout \ - PCM_setCoreVoltageLevelWithTimeout -#endif -#ifdef ROM_PCM_setPowerMode -#define MAP_PCM_setPowerMode \ - ROM_PCM_setPowerMode -#else -#define MAP_PCM_setPowerMode \ - PCM_setPowerMode -#endif -#ifdef ROM_PCM_setPowerModeWithTimeout -#define MAP_PCM_setPowerModeWithTimeout \ - ROM_PCM_setPowerModeWithTimeout -#else -#define MAP_PCM_setPowerModeWithTimeout \ - PCM_setPowerModeWithTimeout -#endif -#ifdef ROM_PCM_getPowerMode -#define MAP_PCM_getPowerMode \ - ROM_PCM_getPowerMode -#else -#define MAP_PCM_getPowerMode \ - PCM_getPowerMode -#endif -#ifdef ROM_PCM_setPowerState -#define MAP_PCM_setPowerState \ - ROM_PCM_setPowerState -#else -#define MAP_PCM_setPowerState \ - PCM_setPowerState -#endif -#ifdef ROM_PCM_setPowerStateWithTimeout -#define MAP_PCM_setPowerStateWithTimeout \ - ROM_PCM_setPowerStateWithTimeout -#else -#define MAP_PCM_setPowerStateWithTimeout \ - PCM_setPowerStateWithTimeout -#endif -#ifdef ROM_PCM_getPowerState -#define MAP_PCM_getPowerState \ - ROM_PCM_getPowerState -#else -#define MAP_PCM_getPowerState \ - PCM_getPowerState -#endif -#ifdef ROM_PCM_shutdownDevice -#define MAP_PCM_shutdownDevice \ - ROM_PCM_shutdownDevice -#else -#define MAP_PCM_shutdownDevice \ - PCM_shutdownDevice -#endif -#ifdef ROM_PCM_gotoLPM0 -#define MAP_PCM_gotoLPM0 \ - ROM_PCM_gotoLPM0 -#else -#define MAP_PCM_gotoLPM0 \ - PCM_gotoLPM0 -#endif -#ifdef ROM_PCM_gotoLPM3 -#define MAP_PCM_gotoLPM3 \ - ROM_PCM_gotoLPM3 -#else -#define MAP_PCM_gotoLPM3 \ - PCM_gotoLPM3 -#endif -#ifdef ROM_PCM_enableInterrupt -#define MAP_PCM_enableInterrupt \ - ROM_PCM_enableInterrupt -#else -#define MAP_PCM_enableInterrupt \ - PCM_enableInterrupt -#endif -#ifdef ROM_PCM_disableInterrupt -#define MAP_PCM_disableInterrupt \ - ROM_PCM_disableInterrupt -#else -#define MAP_PCM_disableInterrupt \ - PCM_disableInterrupt -#endif -#ifdef ROM_PCM_getInterruptStatus -#define MAP_PCM_getInterruptStatus \ - ROM_PCM_getInterruptStatus -#else -#define MAP_PCM_getInterruptStatus \ - PCM_getInterruptStatus -#endif -#ifdef ROM_PCM_getEnabledInterruptStatus -#define MAP_PCM_getEnabledInterruptStatus \ - ROM_PCM_getEnabledInterruptStatus -#else -#define MAP_PCM_getEnabledInterruptStatus \ - PCM_getEnabledInterruptStatus -#endif -#ifdef ROM_PCM_clearInterruptFlag -#define MAP_PCM_clearInterruptFlag \ - ROM_PCM_clearInterruptFlag -#else -#define MAP_PCM_clearInterruptFlag \ - PCM_clearInterruptFlag -#endif -#ifdef ROM_PCM_enableRudeMode -#define MAP_PCM_enableRudeMode \ - ROM_PCM_enableRudeMode -#else -#define MAP_PCM_enableRudeMode \ - PCM_enableRudeMode -#endif -#ifdef ROM_PCM_disableRudeMode -#define MAP_PCM_disableRudeMode \ - ROM_PCM_disableRudeMode -#else -#define MAP_PCM_disableRudeMode \ - PCM_disableRudeMode -#endif -#ifdef ROM_PCM_gotoLPM0InterruptSafe -#define MAP_PCM_gotoLPM0InterruptSafe \ - ROM_PCM_gotoLPM0InterruptSafe -#else -#define MAP_PCM_gotoLPM0InterruptSafe \ - PCM_gotoLPM0InterruptSafe -#endif -#ifdef ROM_PCM_gotoLPM3InterruptSafe -#define MAP_PCM_gotoLPM3InterruptSafe \ - ROM_PCM_gotoLPM3InterruptSafe -#else -#define MAP_PCM_gotoLPM3InterruptSafe \ - PCM_gotoLPM3InterruptSafe -#endif -#ifdef ROM_PCM_registerInterrupt -#define MAP_PCM_registerInterrupt \ - ROM_PCM_registerInterrupt -#else -#define MAP_PCM_registerInterrupt \ - PCM_registerInterrupt -#endif -#ifdef ROM_PCM_unregisterInterrupt -#define MAP_PCM_unregisterInterrupt \ - ROM_PCM_unregisterInterrupt -#else -#define MAP_PCM_unregisterInterrupt \ - PCM_unregisterInterrupt -#endif -#ifdef ROM_PCM_setCoreVoltageLevelNonBlocking -#define MAP_PCM_setCoreVoltageLevelNonBlocking \ - ROM_PCM_setCoreVoltageLevelNonBlocking -#else -#define MAP_PCM_setCoreVoltageLevelNonBlocking \ - PCM_setCoreVoltageLevelNonBlocking -#endif -#ifdef ROM_PCM_setPowerModeNonBlocking -#define MAP_PCM_setPowerModeNonBlocking \ - ROM_PCM_setPowerModeNonBlocking -#else -#define MAP_PCM_setPowerModeNonBlocking \ - PCM_setPowerModeNonBlocking -#endif -#ifdef ROM_PCM_setPowerStateNonBlocking -#define MAP_PCM_setPowerStateNonBlocking \ - ROM_PCM_setPowerStateNonBlocking -#else -#define MAP_PCM_setPowerStateNonBlocking \ - PCM_setPowerStateNonBlocking -#endif -#ifdef ROM_PCM_gotoLPM4 -#define MAP_PCM_gotoLPM4 \ - ROM_PCM_gotoLPM4 -#else -#define MAP_PCM_gotoLPM4 \ - PCM_gotoLPM4 -#endif -#ifdef ROM_PCM_gotoLPM4InterruptSafe -#define MAP_PCM_gotoLPM4InterruptSafe \ - ROM_PCM_gotoLPM4InterruptSafe -#else -#define MAP_PCM_gotoLPM4InterruptSafe \ - PCM_gotoLPM4InterruptSafe -#endif - -//***************************************************************************** -// -// Macros for the PMAP API. -// -//***************************************************************************** -#ifdef ROM_PMAP_configurePorts -#define MAP_PMAP_configurePorts \ - ROM_PMAP_configurePorts -#else -#define MAP_PMAP_configurePorts \ - PMAP_configurePorts -#endif - -//***************************************************************************** -// -// Macros for the PSS API. -// -//***************************************************************************** -#ifdef ROM_PSS_enableHighSidePinToggle -#define MAP_PSS_enableHighSidePinToggle \ - ROM_PSS_enableHighSidePinToggle -#else -#define MAP_PSS_enableHighSidePinToggle \ - PSS_enableHighSidePinToggle -#endif -#ifdef ROM_PSS_disableHighSidePinToggle -#define MAP_PSS_disableHighSidePinToggle \ - ROM_PSS_disableHighSidePinToggle -#else -#define MAP_PSS_disableHighSidePinToggle \ - PSS_disableHighSidePinToggle -#endif -#ifdef ROM_PSS_enableHighSide -#define MAP_PSS_enableHighSide \ - ROM_PSS_enableHighSide -#else -#define MAP_PSS_enableHighSide \ - PSS_enableHighSide -#endif -#ifdef ROM_PSS_disableHighSide -#define MAP_PSS_disableHighSide \ - ROM_PSS_disableHighSide -#else -#define MAP_PSS_disableHighSide \ - PSS_disableHighSide -#endif -#ifdef ROM_PSS_enableLowSide -#define MAP_PSS_enableLowSide \ - ROM_PSS_enableLowSide -#else -#define MAP_PSS_enableLowSide \ - PSS_enableLowSide -#endif -#ifdef ROM_PSS_disableLowSide -#define MAP_PSS_disableLowSide \ - ROM_PSS_disableLowSide -#else -#define MAP_PSS_disableLowSide \ - PSS_disableLowSide -#endif -#ifdef ROM_PSS_setHighSidePerformanceMode -#define MAP_PSS_setHighSidePerformanceMode \ - ROM_PSS_setHighSidePerformanceMode -#else -#define MAP_PSS_setHighSidePerformanceMode \ - PSS_setHighSidePerformanceMode -#endif -#ifdef ROM_PSS_getHighSidePerformanceMode -#define MAP_PSS_getHighSidePerformanceMode \ - ROM_PSS_getHighSidePerformanceMode -#else -#define MAP_PSS_getHighSidePerformanceMode \ - PSS_getHighSidePerformanceMode -#endif -#ifdef ROM_PSS_setLowSidePerformanceMode -#define MAP_PSS_setLowSidePerformanceMode \ - ROM_PSS_setLowSidePerformanceMode -#else -#define MAP_PSS_setLowSidePerformanceMode \ - PSS_setLowSidePerformanceMode -#endif -#ifdef ROM_PSS_getLowSidePerformanceMode -#define MAP_PSS_getLowSidePerformanceMode \ - ROM_PSS_getLowSidePerformanceMode -#else -#define MAP_PSS_getLowSidePerformanceMode \ - PSS_getLowSidePerformanceMode -#endif -#ifdef ROM_PSS_enableHighSideMonitor -#define MAP_PSS_enableHighSideMonitor \ - ROM_PSS_enableHighSideMonitor -#else -#define MAP_PSS_enableHighSideMonitor \ - PSS_enableHighSideMonitor -#endif -#ifdef ROM_PSS_disableHighSideMonitor -#define MAP_PSS_disableHighSideMonitor \ - ROM_PSS_disableHighSideMonitor -#else -#define MAP_PSS_disableHighSideMonitor \ - PSS_disableHighSideMonitor -#endif -#ifdef ROM_PSS_setHighSideVoltageTrigger -#define MAP_PSS_setHighSideVoltageTrigger \ - ROM_PSS_setHighSideVoltageTrigger -#else -#define MAP_PSS_setHighSideVoltageTrigger \ - PSS_setHighSideVoltageTrigger -#endif -#ifdef ROM_PSS_getHighSideVoltageTrigger -#define MAP_PSS_getHighSideVoltageTrigger \ - ROM_PSS_getHighSideVoltageTrigger -#else -#define MAP_PSS_getHighSideVoltageTrigger \ - PSS_getHighSideVoltageTrigger -#endif -#ifdef ROM_PSS_enableInterrupt -#define MAP_PSS_enableInterrupt \ - ROM_PSS_enableInterrupt -#else -#define MAP_PSS_enableInterrupt \ - PSS_enableInterrupt -#endif -#ifdef ROM_PSS_disableInterrupt -#define MAP_PSS_disableInterrupt \ - ROM_PSS_disableInterrupt -#else -#define MAP_PSS_disableInterrupt \ - PSS_disableInterrupt -#endif -#ifdef ROM_PSS_getInterruptStatus -#define MAP_PSS_getInterruptStatus \ - ROM_PSS_getInterruptStatus -#else -#define MAP_PSS_getInterruptStatus \ - PSS_getInterruptStatus -#endif -#ifdef ROM_PSS_clearInterruptFlag -#define MAP_PSS_clearInterruptFlag \ - ROM_PSS_clearInterruptFlag -#else -#define MAP_PSS_clearInterruptFlag \ - PSS_clearInterruptFlag -#endif -#ifdef ROM_PSS_registerInterrupt -#define MAP_PSS_registerInterrupt \ - ROM_PSS_registerInterrupt -#else -#define MAP_PSS_registerInterrupt \ - PSS_registerInterrupt -#endif -#ifdef ROM_PSS_unregisterInterrupt -#define MAP_PSS_unregisterInterrupt \ - ROM_PSS_unregisterInterrupt -#else -#define MAP_PSS_unregisterInterrupt \ - PSS_unregisterInterrupt -#endif -#ifdef ROM_PSS_enableForcedDCDCOperation -#define MAP_PSS_enableForcedDCDCOperation \ - ROM_PSS_enableForcedDCDCOperation -#else -#define MAP_PSS_enableForcedDCDCOperation \ - PSS_enableForcedDCDCOperation -#endif -#ifdef ROM_PSS_disableForcedDCDCOperation -#define MAP_PSS_disableForcedDCDCOperation \ - ROM_PSS_disableForcedDCDCOperation -#else -#define MAP_PSS_disableForcedDCDCOperation \ - PSS_disableForcedDCDCOperation -#endif - -//***************************************************************************** -// -// Macros for the Ref API. -// -//***************************************************************************** -#ifdef ROM_REF_A_setReferenceVoltage -#define MAP_REF_A_setReferenceVoltage \ - ROM_REF_A_setReferenceVoltage -#else -#define MAP_REF_A_setReferenceVoltage \ - REF_A_setReferenceVoltage -#endif -#ifdef ROM_REF_A_disableTempSensor -#define MAP_REF_A_disableTempSensor \ - ROM_REF_A_disableTempSensor -#else -#define MAP_REF_A_disableTempSensor \ - REF_A_disableTempSensor -#endif -#ifdef ROM_REF_A_enableTempSensor -#define MAP_REF_A_enableTempSensor \ - ROM_REF_A_enableTempSensor -#else -#define MAP_REF_A_enableTempSensor \ - REF_A_enableTempSensor -#endif -#ifdef ROM_REF_A_enableReferenceVoltageOutput -#define MAP_REF_A_enableReferenceVoltageOutput \ - ROM_REF_A_enableReferenceVoltageOutput -#else -#define MAP_REF_A_enableReferenceVoltageOutput \ - REF_A_enableReferenceVoltageOutput -#endif -#ifdef ROM_REF_A_disableReferenceVoltageOutput -#define MAP_REF_A_disableReferenceVoltageOutput \ - ROM_REF_A_disableReferenceVoltageOutput -#else -#define MAP_REF_A_disableReferenceVoltageOutput \ - REF_A_disableReferenceVoltageOutput -#endif -#ifdef ROM_REF_A_enableReferenceVoltage -#define MAP_REF_A_enableReferenceVoltage \ - ROM_REF_A_enableReferenceVoltage -#else -#define MAP_REF_A_enableReferenceVoltage \ - REF_A_enableReferenceVoltage -#endif -#ifdef ROM_REF_A_disableReferenceVoltage -#define MAP_REF_A_disableReferenceVoltage \ - ROM_REF_A_disableReferenceVoltage -#else -#define MAP_REF_A_disableReferenceVoltage \ - REF_A_disableReferenceVoltage -#endif -#ifdef ROM_REF_A_getBandgapMode -#define MAP_REF_A_getBandgapMode \ - ROM_REF_A_getBandgapMode -#else -#define MAP_REF_A_getBandgapMode \ - REF_A_getBandgapMode -#endif -#ifdef ROM_REF_A_isBandgapActive -#define MAP_REF_A_isBandgapActive \ - ROM_REF_A_isBandgapActive -#else -#define MAP_REF_A_isBandgapActive \ - REF_A_isBandgapActive -#endif -#ifdef ROM_REF_A_isRefGenBusy -#define MAP_REF_A_isRefGenBusy \ - ROM_REF_A_isRefGenBusy -#else -#define MAP_REF_A_isRefGenBusy \ - REF_A_isRefGenBusy -#endif -#ifdef ROM_REF_A_isRefGenActive -#define MAP_REF_A_isRefGenActive \ - ROM_REF_A_isRefGenActive -#else -#define MAP_REF_A_isRefGenActive \ - REF_A_isRefGenActive -#endif -#ifdef ROM_REF_A_getBufferedBandgapVoltageStatus -#define MAP_REF_A_getBufferedBandgapVoltageStatus \ - ROM_REF_A_getBufferedBandgapVoltageStatus -#else -#define MAP_REF_A_getBufferedBandgapVoltageStatus \ - REF_A_getBufferedBandgapVoltageStatus -#endif -#ifdef ROM_REF_A_getVariableReferenceVoltageStatus -#define MAP_REF_A_getVariableReferenceVoltageStatus \ - ROM_REF_A_getVariableReferenceVoltageStatus -#else -#define MAP_REF_A_getVariableReferenceVoltageStatus \ - REF_A_getVariableReferenceVoltageStatus -#endif -#ifdef ROM_REF_A_setReferenceVoltageOneTimeTrigger -#define MAP_REF_A_setReferenceVoltageOneTimeTrigger \ - ROM_REF_A_setReferenceVoltageOneTimeTrigger -#else -#define MAP_REF_A_setReferenceVoltageOneTimeTrigger \ - REF_A_setReferenceVoltageOneTimeTrigger -#endif -#ifdef ROM_REF_A_setBufferedBandgapVoltageOneTimeTrigger -#define MAP_REF_A_setBufferedBandgapVoltageOneTimeTrigger \ - ROM_REF_A_setBufferedBandgapVoltageOneTimeTrigger -#else -#define MAP_REF_A_setBufferedBandgapVoltageOneTimeTrigger \ - REF_A_setBufferedBandgapVoltageOneTimeTrigger -#endif - -//***************************************************************************** -// -// Macros for the ResetCtl API. -// -//***************************************************************************** -#ifdef ROM_ResetCtl_initiateSoftReset -#define MAP_ResetCtl_initiateSoftReset \ - ROM_ResetCtl_initiateSoftReset -#else -#define MAP_ResetCtl_initiateSoftReset \ - ResetCtl_initiateSoftReset -#endif -#ifdef ROM_ResetCtl_initiateSoftResetWithSource -#define MAP_ResetCtl_initiateSoftResetWithSource \ - ROM_ResetCtl_initiateSoftResetWithSource -#else -#define MAP_ResetCtl_initiateSoftResetWithSource \ - ResetCtl_initiateSoftResetWithSource -#endif -#ifdef ROM_ResetCtl_getSoftResetSource -#define MAP_ResetCtl_getSoftResetSource \ - ROM_ResetCtl_getSoftResetSource -#else -#define MAP_ResetCtl_getSoftResetSource \ - ResetCtl_getSoftResetSource -#endif -#ifdef ROM_ResetCtl_clearSoftResetSource -#define MAP_ResetCtl_clearSoftResetSource \ - ROM_ResetCtl_clearSoftResetSource -#else -#define MAP_ResetCtl_clearSoftResetSource \ - ResetCtl_clearSoftResetSource -#endif -#ifdef ROM_ResetCtl_initiateHardReset -#define MAP_ResetCtl_initiateHardReset \ - ROM_ResetCtl_initiateHardReset -#else -#define MAP_ResetCtl_initiateHardReset \ - ResetCtl_initiateHardReset -#endif -#ifdef ROM_ResetCtl_initiateHardResetWithSource -#define MAP_ResetCtl_initiateHardResetWithSource \ - ROM_ResetCtl_initiateHardResetWithSource -#else -#define MAP_ResetCtl_initiateHardResetWithSource \ - ResetCtl_initiateHardResetWithSource -#endif -#ifdef ROM_ResetCtl_getHardResetSource -#define MAP_ResetCtl_getHardResetSource \ - ROM_ResetCtl_getHardResetSource -#else -#define MAP_ResetCtl_getHardResetSource \ - ResetCtl_getHardResetSource -#endif -#ifdef ROM_ResetCtl_clearHardResetSource -#define MAP_ResetCtl_clearHardResetSource \ - ROM_ResetCtl_clearHardResetSource -#else -#define MAP_ResetCtl_clearHardResetSource \ - ResetCtl_clearHardResetSource -#endif -#ifdef ROM_ResetCtl_getPSSSource -#define MAP_ResetCtl_getPSSSource \ - ROM_ResetCtl_getPSSSource -#else -#define MAP_ResetCtl_getPSSSource \ - ResetCtl_getPSSSource -#endif -#ifdef ROM_ResetCtl_clearPSSFlags -#define MAP_ResetCtl_clearPSSFlags \ - ROM_ResetCtl_clearPSSFlags -#else -#define MAP_ResetCtl_clearPSSFlags \ - ResetCtl_clearPSSFlags -#endif -#ifdef ROM_ResetCtl_getPCMSource -#define MAP_ResetCtl_getPCMSource \ - ROM_ResetCtl_getPCMSource -#else -#define MAP_ResetCtl_getPCMSource \ - ResetCtl_getPCMSource -#endif -#ifdef ROM_ResetCtl_clearPCMFlags -#define MAP_ResetCtl_clearPCMFlags \ - ROM_ResetCtl_clearPCMFlags -#else -#define MAP_ResetCtl_clearPCMFlags \ - ResetCtl_clearPCMFlags -#endif - -//***************************************************************************** -// -// Macros for the RTC API. -// -//***************************************************************************** -#ifdef ROM_RTC_C_startClock -#define MAP_RTC_C_startClock \ - ROM_RTC_C_startClock -#else -#define MAP_RTC_C_startClock \ - RTC_C_startClock -#endif -#ifdef ROM_RTC_C_holdClock -#define MAP_RTC_C_holdClock \ - ROM_RTC_C_holdClock -#else -#define MAP_RTC_C_holdClock \ - RTC_C_holdClock -#endif -#ifdef ROM_RTC_C_setCalibrationFrequency -#define MAP_RTC_C_setCalibrationFrequency \ - ROM_RTC_C_setCalibrationFrequency -#else -#define MAP_RTC_C_setCalibrationFrequency \ - RTC_C_setCalibrationFrequency -#endif -#ifdef ROM_RTC_C_setCalibrationData -#define MAP_RTC_C_setCalibrationData \ - ROM_RTC_C_setCalibrationData -#else -#define MAP_RTC_C_setCalibrationData \ - RTC_C_setCalibrationData -#endif -#ifdef ROM_RTC_C_setTemperatureCompensation -#define MAP_RTC_C_setTemperatureCompensation \ - ROM_RTC_C_setTemperatureCompensation -#else -#define MAP_RTC_C_setTemperatureCompensation \ - RTC_C_setTemperatureCompensation -#endif -#ifdef ROM_RTC_C_initCalendar -#define MAP_RTC_C_initCalendar \ - ROM_RTC_C_initCalendar -#else -#define MAP_RTC_C_initCalendar \ - RTC_C_initCalendar -#endif -#ifdef ROM_RTC_C_getCalendarTime -#define MAP_RTC_C_getCalendarTime \ - ROM_RTC_C_getCalendarTime -#else -#define MAP_RTC_C_getCalendarTime \ - RTC_C_getCalendarTime -#endif -#ifdef ROM_RTC_C_setCalendarAlarm -#define MAP_RTC_C_setCalendarAlarm \ - ROM_RTC_C_setCalendarAlarm -#else -#define MAP_RTC_C_setCalendarAlarm \ - RTC_C_setCalendarAlarm -#endif -#ifdef ROM_RTC_C_setCalendarEvent -#define MAP_RTC_C_setCalendarEvent \ - ROM_RTC_C_setCalendarEvent -#else -#define MAP_RTC_C_setCalendarEvent \ - RTC_C_setCalendarEvent -#endif -#ifdef ROM_RTC_C_definePrescaleEvent -#define MAP_RTC_C_definePrescaleEvent \ - ROM_RTC_C_definePrescaleEvent -#else -#define MAP_RTC_C_definePrescaleEvent \ - RTC_C_definePrescaleEvent -#endif -#ifdef ROM_RTC_C_getPrescaleValue -#define MAP_RTC_C_getPrescaleValue \ - ROM_RTC_C_getPrescaleValue -#else -#define MAP_RTC_C_getPrescaleValue \ - RTC_C_getPrescaleValue -#endif -#ifdef ROM_RTC_C_setPrescaleValue -#define MAP_RTC_C_setPrescaleValue \ - ROM_RTC_C_setPrescaleValue -#else -#define MAP_RTC_C_setPrescaleValue \ - RTC_C_setPrescaleValue -#endif -#ifdef ROM_RTC_C_convertBCDToBinary -#define MAP_RTC_C_convertBCDToBinary \ - ROM_RTC_C_convertBCDToBinary -#else -#define MAP_RTC_C_convertBCDToBinary \ - RTC_C_convertBCDToBinary -#endif -#ifdef ROM_RTC_C_convertBinaryToBCD -#define MAP_RTC_C_convertBinaryToBCD \ - ROM_RTC_C_convertBinaryToBCD -#else -#define MAP_RTC_C_convertBinaryToBCD \ - RTC_C_convertBinaryToBCD -#endif -#ifdef ROM_RTC_C_enableInterrupt -#define MAP_RTC_C_enableInterrupt \ - ROM_RTC_C_enableInterrupt -#else -#define MAP_RTC_C_enableInterrupt \ - RTC_C_enableInterrupt -#endif -#ifdef ROM_RTC_C_disableInterrupt -#define MAP_RTC_C_disableInterrupt \ - ROM_RTC_C_disableInterrupt -#else -#define MAP_RTC_C_disableInterrupt \ - RTC_C_disableInterrupt -#endif -#ifdef ROM_RTC_C_getInterruptStatus -#define MAP_RTC_C_getInterruptStatus \ - ROM_RTC_C_getInterruptStatus -#else -#define MAP_RTC_C_getInterruptStatus \ - RTC_C_getInterruptStatus -#endif -#ifdef ROM_RTC_C_getEnabledInterruptStatus -#define MAP_RTC_C_getEnabledInterruptStatus \ - ROM_RTC_C_getEnabledInterruptStatus -#else -#define MAP_RTC_C_getEnabledInterruptStatus \ - RTC_C_getEnabledInterruptStatus -#endif -#ifdef ROM_RTC_C_clearInterruptFlag -#define MAP_RTC_C_clearInterruptFlag \ - ROM_RTC_C_clearInterruptFlag -#else -#define MAP_RTC_C_clearInterruptFlag \ - RTC_C_clearInterruptFlag -#endif -#ifdef ROM_RTC_C_registerInterrupt -#define MAP_RTC_C_registerInterrupt \ - ROM_RTC_C_registerInterrupt -#else -#define MAP_RTC_C_registerInterrupt \ - RTC_C_registerInterrupt -#endif -#ifdef ROM_RTC_C_unregisterInterrupt -#define MAP_RTC_C_unregisterInterrupt \ - ROM_RTC_C_unregisterInterrupt -#else -#define MAP_RTC_C_unregisterInterrupt \ - RTC_C_unregisterInterrupt -#endif - -//***************************************************************************** -// -// Macros for the SPI API. -// -//***************************************************************************** -#ifdef ROM_SPI_initMaster -#define MAP_SPI_initMaster \ - ROM_SPI_initMaster -#else -#define MAP_SPI_initMaster \ - SPI_initMaster -#endif -#ifdef ROM_SPI_selectFourPinFunctionality -#define MAP_SPI_selectFourPinFunctionality \ - ROM_SPI_selectFourPinFunctionality -#else -#define MAP_SPI_selectFourPinFunctionality \ - SPI_selectFourPinFunctionality -#endif -#ifdef ROM_SPI_changeMasterClock -#define MAP_SPI_changeMasterClock \ - ROM_SPI_changeMasterClock -#else -#define MAP_SPI_changeMasterClock \ - SPI_changeMasterClock -#endif -#ifdef ROM_SPI_initSlave -#define MAP_SPI_initSlave \ - ROM_SPI_initSlave -#else -#define MAP_SPI_initSlave \ - SPI_initSlave -#endif -#ifdef ROM_SPI_changeClockPhasePolarity -#define MAP_SPI_changeClockPhasePolarity \ - ROM_SPI_changeClockPhasePolarity -#else -#define MAP_SPI_changeClockPhasePolarity \ - SPI_changeClockPhasePolarity -#endif -#ifdef ROM_SPI_transmitData -#define MAP_SPI_transmitData \ - ROM_SPI_transmitData -#else -#define MAP_SPI_transmitData \ - SPI_transmitData -#endif -#ifdef ROM_SPI_receiveData -#define MAP_SPI_receiveData \ - ROM_SPI_receiveData -#else -#define MAP_SPI_receiveData \ - SPI_receiveData -#endif -#ifdef ROM_SPI_enableModule -#define MAP_SPI_enableModule \ - ROM_SPI_enableModule -#else -#define MAP_SPI_enableModule \ - SPI_enableModule -#endif -#ifdef ROM_SPI_disableModule -#define MAP_SPI_disableModule \ - ROM_SPI_disableModule -#else -#define MAP_SPI_disableModule \ - SPI_disableModule -#endif -#ifdef ROM_SPI_getReceiveBufferAddressForDMA -#define MAP_SPI_getReceiveBufferAddressForDMA \ - ROM_SPI_getReceiveBufferAddressForDMA -#else -#define MAP_SPI_getReceiveBufferAddressForDMA \ - SPI_getReceiveBufferAddressForDMA -#endif -#ifdef ROM_SPI_getTransmitBufferAddressForDMA -#define MAP_SPI_getTransmitBufferAddressForDMA \ - ROM_SPI_getTransmitBufferAddressForDMA -#else -#define MAP_SPI_getTransmitBufferAddressForDMA \ - SPI_getTransmitBufferAddressForDMA -#endif -#ifdef ROM_SPI_isBusy -#define MAP_SPI_isBusy \ - ROM_SPI_isBusy -#else -#define MAP_SPI_isBusy \ - SPI_isBusy -#endif -#ifdef ROM_SPI_enableInterrupt -#define MAP_SPI_enableInterrupt \ - ROM_SPI_enableInterrupt -#else -#define MAP_SPI_enableInterrupt \ - SPI_enableInterrupt -#endif -#ifdef ROM_SPI_disableInterrupt -#define MAP_SPI_disableInterrupt \ - ROM_SPI_disableInterrupt -#else -#define MAP_SPI_disableInterrupt \ - SPI_disableInterrupt -#endif -#ifdef ROM_SPI_getInterruptStatus -#define MAP_SPI_getInterruptStatus \ - ROM_SPI_getInterruptStatus -#else -#define MAP_SPI_getInterruptStatus \ - SPI_getInterruptStatus -#endif -#ifdef ROM_SPI_getEnabledInterruptStatus -#define MAP_SPI_getEnabledInterruptStatus \ - ROM_SPI_getEnabledInterruptStatus -#else -#define MAP_SPI_getEnabledInterruptStatus \ - SPI_getEnabledInterruptStatus -#endif -#ifdef ROM_SPI_clearInterruptFlag -#define MAP_SPI_clearInterruptFlag \ - ROM_SPI_clearInterruptFlag -#else -#define MAP_SPI_clearInterruptFlag \ - SPI_clearInterruptFlag -#endif -#ifdef ROM_SPI_registerInterrupt -#define MAP_SPI_registerInterrupt \ - ROM_SPI_registerInterrupt -#else -#define MAP_SPI_registerInterrupt \ - SPI_registerInterrupt -#endif -#ifdef ROM_SPI_unregisterInterrupt -#define MAP_SPI_unregisterInterrupt \ - ROM_SPI_unregisterInterrupt -#else -#define MAP_SPI_unregisterInterrupt \ - SPI_unregisterInterrupt -#endif - -//***************************************************************************** -// -// Macros for the SysCtl API. -// -//***************************************************************************** -#ifdef ROM_SysCtl_getSRAMSize -#define MAP_SysCtl_getSRAMSize \ - ROM_SysCtl_getSRAMSize -#else -#define MAP_SysCtl_getSRAMSize \ - SysCtl_getSRAMSize -#endif -#ifdef ROM_SysCtl_getFlashSize -#define MAP_SysCtl_getFlashSize \ - ROM_SysCtl_getFlashSize -#else -#define MAP_SysCtl_getFlashSize \ - SysCtl_getFlashSize -#endif -#ifdef ROM_SysCtl_rebootDevice -#define MAP_SysCtl_rebootDevice \ - ROM_SysCtl_rebootDevice -#else -#define MAP_SysCtl_rebootDevice \ - SysCtl_rebootDevice -#endif -#ifdef ROM_SysCtl_enableSRAMBank -#define MAP_SysCtl_enableSRAMBank \ - ROM_SysCtl_enableSRAMBank -#else -#define MAP_SysCtl_enableSRAMBank \ - SysCtl_enableSRAMBank -#endif -#ifdef ROM_SysCtl_disableSRAMBank -#define MAP_SysCtl_disableSRAMBank \ - ROM_SysCtl_disableSRAMBank -#else -#define MAP_SysCtl_disableSRAMBank \ - SysCtl_disableSRAMBank -#endif -#ifdef ROM_SysCtl_enableSRAMBankRetention -#define MAP_SysCtl_enableSRAMBankRetention \ - ROM_SysCtl_enableSRAMBankRetention -#else -#define MAP_SysCtl_enableSRAMBankRetention \ - SysCtl_enableSRAMBankRetention -#endif -#ifdef ROM_SysCtl_disableSRAMBankRetention -#define MAP_SysCtl_disableSRAMBankRetention \ - ROM_SysCtl_disableSRAMBankRetention -#else -#define MAP_SysCtl_disableSRAMBankRetention \ - SysCtl_disableSRAMBankRetention -#endif -#ifdef ROM_SysCtl_enablePeripheralAtCPUHalt -#define MAP_SysCtl_enablePeripheralAtCPUHalt \ - ROM_SysCtl_enablePeripheralAtCPUHalt -#else -#define MAP_SysCtl_enablePeripheralAtCPUHalt \ - SysCtl_enablePeripheralAtCPUHalt -#endif -#ifdef ROM_SysCtl_disablePeripheralAtCPUHalt -#define MAP_SysCtl_disablePeripheralAtCPUHalt \ - ROM_SysCtl_disablePeripheralAtCPUHalt -#else -#define MAP_SysCtl_disablePeripheralAtCPUHalt \ - SysCtl_disablePeripheralAtCPUHalt -#endif -#ifdef ROM_SysCtl_setWDTTimeoutResetType -#define MAP_SysCtl_setWDTTimeoutResetType \ - ROM_SysCtl_setWDTTimeoutResetType -#else -#define MAP_SysCtl_setWDTTimeoutResetType \ - SysCtl_setWDTTimeoutResetType -#endif -#ifdef ROM_SysCtl_setWDTPasswordViolationResetType -#define MAP_SysCtl_setWDTPasswordViolationResetType \ - ROM_SysCtl_setWDTPasswordViolationResetType -#else -#define MAP_SysCtl_setWDTPasswordViolationResetType \ - SysCtl_setWDTPasswordViolationResetType -#endif -#ifdef ROM_SysCtl_disableNMISource -#define MAP_SysCtl_disableNMISource \ - ROM_SysCtl_disableNMISource -#else -#define MAP_SysCtl_disableNMISource \ - SysCtl_disableNMISource -#endif -#ifdef ROM_SysCtl_enableNMISource -#define MAP_SysCtl_enableNMISource \ - ROM_SysCtl_enableNMISource -#else -#define MAP_SysCtl_enableNMISource \ - SysCtl_enableNMISource -#endif -#ifdef ROM_SysCtl_getNMISourceStatus -#define MAP_SysCtl_getNMISourceStatus \ - ROM_SysCtl_getNMISourceStatus -#else -#define MAP_SysCtl_getNMISourceStatus \ - SysCtl_getNMISourceStatus -#endif -#ifdef ROM_SysCtl_getTempCalibrationConstant -#define MAP_SysCtl_getTempCalibrationConstant \ - ROM_SysCtl_getTempCalibrationConstant -#else -#define MAP_SysCtl_getTempCalibrationConstant \ - SysCtl_getTempCalibrationConstant -#endif -#ifdef ROM_SysCtl_enableGlitchFilter -#define MAP_SysCtl_enableGlitchFilter \ - ROM_SysCtl_enableGlitchFilter -#else -#define MAP_SysCtl_enableGlitchFilter \ - SysCtl_enableGlitchFilter -#endif -#ifdef ROM_SysCtl_disableGlitchFilter -#define MAP_SysCtl_disableGlitchFilter \ - ROM_SysCtl_disableGlitchFilter -#else -#define MAP_SysCtl_disableGlitchFilter \ - SysCtl_disableGlitchFilter -#endif -#ifdef ROM_SysCtl_getTLVInfo -#define MAP_SysCtl_getTLVInfo \ - ROM_SysCtl_getTLVInfo -#else -#define MAP_SysCtl_getTLVInfo \ - SysCtl_getTLVInfo -#endif - -//***************************************************************************** -// -// Macros for the SysTick API. -// -//***************************************************************************** -#ifdef ROM_SysTick_enableModule -#define MAP_SysTick_enableModule \ - ROM_SysTick_enableModule -#else -#define MAP_SysTick_enableModule \ - SysTick_enableModule -#endif -#ifdef ROM_SysTick_disableModule -#define MAP_SysTick_disableModule \ - ROM_SysTick_disableModule -#else -#define MAP_SysTick_disableModule \ - SysTick_disableModule -#endif -#ifdef ROM_SysTick_enableInterrupt -#define MAP_SysTick_enableInterrupt \ - ROM_SysTick_enableInterrupt -#else -#define MAP_SysTick_enableInterrupt \ - SysTick_enableInterrupt -#endif -#ifdef ROM_SysTick_disableInterrupt -#define MAP_SysTick_disableInterrupt \ - ROM_SysTick_disableInterrupt -#else -#define MAP_SysTick_disableInterrupt \ - SysTick_disableInterrupt -#endif -#ifdef ROM_SysTick_setPeriod -#define MAP_SysTick_setPeriod \ - ROM_SysTick_setPeriod -#else -#define MAP_SysTick_setPeriod \ - SysTick_setPeriod -#endif -#ifdef ROM_SysTick_getPeriod -#define MAP_SysTick_getPeriod \ - ROM_SysTick_getPeriod -#else -#define MAP_SysTick_getPeriod \ - SysTick_getPeriod -#endif -#ifdef ROM_SysTick_getValue -#define MAP_SysTick_getValue \ - ROM_SysTick_getValue -#else -#define MAP_SysTick_getValue \ - SysTick_getValue -#endif -#ifdef ROM_SysTick_registerInterrupt -#define MAP_SysTick_registerInterrupt \ - ROM_SysTick_registerInterrupt -#else -#define MAP_SysTick_registerInterrupt \ - SysTick_registerInterrupt -#endif -#ifdef ROM_SysTick_unregisterInterrupt -#define MAP_SysTick_unregisterInterrupt \ - ROM_SysTick_unregisterInterrupt -#else -#define MAP_SysTick_unregisterInterrupt \ - SysTick_unregisterInterrupt -#endif - -//***************************************************************************** -// -// Macros for the Timer_A API. -// -//***************************************************************************** -#ifdef ROM_Timer_A_startCounter -#define MAP_Timer_A_startCounter \ - ROM_Timer_A_startCounter -#else -#define MAP_Timer_A_startCounter \ - Timer_A_startCounter -#endif -#ifdef ROM_Timer_A_configureContinuousMode -#define MAP_Timer_A_configureContinuousMode \ - ROM_Timer_A_configureContinuousMode -#else -#define MAP_Timer_A_configureContinuousMode \ - Timer_A_configureContinuousMode -#endif -#ifdef ROM_Timer_A_configureUpMode -#define MAP_Timer_A_configureUpMode \ - ROM_Timer_A_configureUpMode -#else -#define MAP_Timer_A_configureUpMode \ - Timer_A_configureUpMode -#endif -#ifdef ROM_Timer_A_configureUpDownMode -#define MAP_Timer_A_configureUpDownMode \ - ROM_Timer_A_configureUpDownMode -#else -#define MAP_Timer_A_configureUpDownMode \ - Timer_A_configureUpDownMode -#endif -#ifdef ROM_Timer_A_initCapture -#define MAP_Timer_A_initCapture \ - ROM_Timer_A_initCapture -#else -#define MAP_Timer_A_initCapture \ - Timer_A_initCapture -#endif -#ifdef ROM_Timer_A_initCompare -#define MAP_Timer_A_initCompare \ - ROM_Timer_A_initCompare -#else -#define MAP_Timer_A_initCompare \ - Timer_A_initCompare -#endif -#ifdef ROM_Timer_A_clearTimer -#define MAP_Timer_A_clearTimer \ - ROM_Timer_A_clearTimer -#else -#define MAP_Timer_A_clearTimer \ - Timer_A_clearTimer -#endif -#ifdef ROM_Timer_A_getSynchronizedCaptureCompareInput -#define MAP_Timer_A_getSynchronizedCaptureCompareInput \ - ROM_Timer_A_getSynchronizedCaptureCompareInput -#else -#define MAP_Timer_A_getSynchronizedCaptureCompareInput \ - Timer_A_getSynchronizedCaptureCompareInput -#endif -#ifdef ROM_Timer_A_getOutputForOutputModeOutBitValue -#define MAP_Timer_A_getOutputForOutputModeOutBitValue \ - ROM_Timer_A_getOutputForOutputModeOutBitValue -#else -#define MAP_Timer_A_getOutputForOutputModeOutBitValue \ - Timer_A_getOutputForOutputModeOutBitValue -#endif -#ifdef ROM_Timer_A_getCaptureCompareCount -#define MAP_Timer_A_getCaptureCompareCount \ - ROM_Timer_A_getCaptureCompareCount -#else -#define MAP_Timer_A_getCaptureCompareCount \ - Timer_A_getCaptureCompareCount -#endif -#ifdef ROM_Timer_A_setOutputForOutputModeOutBitValue -#define MAP_Timer_A_setOutputForOutputModeOutBitValue \ - ROM_Timer_A_setOutputForOutputModeOutBitValue -#else -#define MAP_Timer_A_setOutputForOutputModeOutBitValue \ - Timer_A_setOutputForOutputModeOutBitValue -#endif -#ifdef ROM_Timer_A_generatePWM -#define MAP_Timer_A_generatePWM \ - ROM_Timer_A_generatePWM -#else -#define MAP_Timer_A_generatePWM \ - Timer_A_generatePWM -#endif -#ifdef ROM_Timer_A_stopTimer -#define MAP_Timer_A_stopTimer \ - ROM_Timer_A_stopTimer -#else -#define MAP_Timer_A_stopTimer \ - Timer_A_stopTimer -#endif -#ifdef ROM_Timer_A_setCompareValue -#define MAP_Timer_A_setCompareValue \ - ROM_Timer_A_setCompareValue -#else -#define MAP_Timer_A_setCompareValue \ - Timer_A_setCompareValue -#endif -#ifdef ROM_Timer_A_clearInterruptFlag -#define MAP_Timer_A_clearInterruptFlag \ - ROM_Timer_A_clearInterruptFlag -#else -#define MAP_Timer_A_clearInterruptFlag \ - Timer_A_clearInterruptFlag -#endif -#ifdef ROM_Timer_A_clearCaptureCompareInterrupt -#define MAP_Timer_A_clearCaptureCompareInterrupt \ - ROM_Timer_A_clearCaptureCompareInterrupt -#else -#define MAP_Timer_A_clearCaptureCompareInterrupt \ - Timer_A_clearCaptureCompareInterrupt -#endif -#ifdef ROM_Timer_A_enableInterrupt -#define MAP_Timer_A_enableInterrupt \ - ROM_Timer_A_enableInterrupt -#else -#define MAP_Timer_A_enableInterrupt \ - Timer_A_enableInterrupt -#endif -#ifdef ROM_Timer_A_disableInterrupt -#define MAP_Timer_A_disableInterrupt \ - ROM_Timer_A_disableInterrupt -#else -#define MAP_Timer_A_disableInterrupt \ - Timer_A_disableInterrupt -#endif -#ifdef ROM_Timer_A_getInterruptStatus -#define MAP_Timer_A_getInterruptStatus \ - ROM_Timer_A_getInterruptStatus -#else -#define MAP_Timer_A_getInterruptStatus \ - Timer_A_getInterruptStatus -#endif -#ifdef ROM_Timer_A_getEnabledInterruptStatus -#define MAP_Timer_A_getEnabledInterruptStatus \ - ROM_Timer_A_getEnabledInterruptStatus -#else -#define MAP_Timer_A_getEnabledInterruptStatus \ - Timer_A_getEnabledInterruptStatus -#endif -#ifdef ROM_Timer_A_enableCaptureCompareInterrupt -#define MAP_Timer_A_enableCaptureCompareInterrupt \ - ROM_Timer_A_enableCaptureCompareInterrupt -#else -#define MAP_Timer_A_enableCaptureCompareInterrupt \ - Timer_A_enableCaptureCompareInterrupt -#endif -#ifdef ROM_Timer_A_disableCaptureCompareInterrupt -#define MAP_Timer_A_disableCaptureCompareInterrupt \ - ROM_Timer_A_disableCaptureCompareInterrupt -#else -#define MAP_Timer_A_disableCaptureCompareInterrupt \ - Timer_A_disableCaptureCompareInterrupt -#endif -#ifdef ROM_Timer_A_getCaptureCompareInterruptStatus -#define MAP_Timer_A_getCaptureCompareInterruptStatus \ - ROM_Timer_A_getCaptureCompareInterruptStatus -#else -#define MAP_Timer_A_getCaptureCompareInterruptStatus \ - Timer_A_getCaptureCompareInterruptStatus -#endif -#ifdef ROM_Timer_A_getCaptureCompareEnabledInterruptStatus -#define MAP_Timer_A_getCaptureCompareEnabledInterruptStatus \ - ROM_Timer_A_getCaptureCompareEnabledInterruptStatus -#else -#define MAP_Timer_A_getCaptureCompareEnabledInterruptStatus \ - Timer_A_getCaptureCompareEnabledInterruptStatus -#endif -#ifdef ROM_Timer_A_registerInterrupt -#define MAP_Timer_A_registerInterrupt \ - ROM_Timer_A_registerInterrupt -#else -#define MAP_Timer_A_registerInterrupt \ - Timer_A_registerInterrupt -#endif -#ifdef ROM_Timer_A_unregisterInterrupt -#define MAP_Timer_A_unregisterInterrupt \ - ROM_Timer_A_unregisterInterrupt -#else -#define MAP_Timer_A_unregisterInterrupt \ - Timer_A_unregisterInterrupt -#endif -#ifdef ROM_Timer_A_getCounterValue -#define MAP_Timer_A_getCounterValue \ - ROM_Timer_A_getCounterValue -#else -#define MAP_Timer_A_getCounterValue \ - Timer_A_getCounterValue -#endif - -//***************************************************************************** -// -// Macros for the Timer32 API. -// -//***************************************************************************** -#ifdef ROM_Timer32_initModule -#define MAP_Timer32_initModule \ - ROM_Timer32_initModule -#else -#define MAP_Timer32_initModule \ - Timer32_initModule -#endif -#ifdef ROM_Timer32_setCount -#define MAP_Timer32_setCount \ - ROM_Timer32_setCount -#else -#define MAP_Timer32_setCount \ - Timer32_setCount -#endif -#ifdef ROM_Timer32_setCountInBackground -#define MAP_Timer32_setCountInBackground \ - ROM_Timer32_setCountInBackground -#else -#define MAP_Timer32_setCountInBackground \ - Timer32_setCountInBackground -#endif -#ifdef ROM_Timer32_getValue -#define MAP_Timer32_getValue \ - ROM_Timer32_getValue -#else -#define MAP_Timer32_getValue \ - Timer32_getValue -#endif -#ifdef ROM_Timer32_startTimer -#define MAP_Timer32_startTimer \ - ROM_Timer32_startTimer -#else -#define MAP_Timer32_startTimer \ - Timer32_startTimer -#endif -#ifdef ROM_Timer32_haltTimer -#define MAP_Timer32_haltTimer \ - ROM_Timer32_haltTimer -#else -#define MAP_Timer32_haltTimer \ - Timer32_haltTimer -#endif -#ifdef ROM_Timer32_enableInterrupt -#define MAP_Timer32_enableInterrupt \ - ROM_Timer32_enableInterrupt -#else -#define MAP_Timer32_enableInterrupt \ - Timer32_enableInterrupt -#endif -#ifdef ROM_Timer32_disableInterrupt -#define MAP_Timer32_disableInterrupt \ - ROM_Timer32_disableInterrupt -#else -#define MAP_Timer32_disableInterrupt \ - Timer32_disableInterrupt -#endif -#ifdef ROM_Timer32_clearInterruptFlag -#define MAP_Timer32_clearInterruptFlag \ - ROM_Timer32_clearInterruptFlag -#else -#define MAP_Timer32_clearInterruptFlag \ - Timer32_clearInterruptFlag -#endif -#ifdef ROM_Timer32_getInterruptStatus -#define MAP_Timer32_getInterruptStatus \ - ROM_Timer32_getInterruptStatus -#else -#define MAP_Timer32_getInterruptStatus \ - Timer32_getInterruptStatus -#endif -#ifdef ROM_Timer32_registerInterrupt -#define MAP_Timer32_registerInterrupt \ - ROM_Timer32_registerInterrupt -#else -#define MAP_Timer32_registerInterrupt \ - Timer32_registerInterrupt -#endif -#ifdef ROM_Timer32_unregisterInterrupt -#define MAP_Timer32_unregisterInterrupt \ - ROM_Timer32_unregisterInterrupt -#else -#define MAP_Timer32_unregisterInterrupt \ - Timer32_unregisterInterrupt -#endif - -//***************************************************************************** -// -// Macros for the UART API. -// -//***************************************************************************** -#ifdef ROM_UART_initModule -#define MAP_UART_initModule \ - ROM_UART_initModule -#else -#define MAP_UART_initModule \ - UART_initModule -#endif -#ifdef ROM_UART_transmitData -#define MAP_UART_transmitData \ - ROM_UART_transmitData -#else -#define MAP_UART_transmitData \ - UART_transmitData -#endif -#ifdef ROM_UART_enableModule -#define MAP_UART_enableModule \ - ROM_UART_enableModule -#else -#define MAP_UART_enableModule \ - UART_enableModule -#endif -#ifdef ROM_UART_disableModule -#define MAP_UART_disableModule \ - ROM_UART_disableModule -#else -#define MAP_UART_disableModule \ - UART_disableModule -#endif -#ifdef ROM_UART_queryStatusFlags -#define MAP_UART_queryStatusFlags \ - ROM_UART_queryStatusFlags -#else -#define MAP_UART_queryStatusFlags \ - UART_queryStatusFlags -#endif -#ifdef ROM_UART_setDormant -#define MAP_UART_setDormant \ - ROM_UART_setDormant -#else -#define MAP_UART_setDormant \ - UART_setDormant -#endif -#ifdef ROM_UART_resetDormant -#define MAP_UART_resetDormant \ - ROM_UART_resetDormant -#else -#define MAP_UART_resetDormant \ - UART_resetDormant -#endif -#ifdef ROM_UART_transmitAddress -#define MAP_UART_transmitAddress \ - ROM_UART_transmitAddress -#else -#define MAP_UART_transmitAddress \ - UART_transmitAddress -#endif -#ifdef ROM_UART_transmitBreak -#define MAP_UART_transmitBreak \ - ROM_UART_transmitBreak -#else -#define MAP_UART_transmitBreak \ - UART_transmitBreak -#endif -#ifdef ROM_UART_getReceiveBufferAddressForDMA -#define MAP_UART_getReceiveBufferAddressForDMA \ - ROM_UART_getReceiveBufferAddressForDMA -#else -#define MAP_UART_getReceiveBufferAddressForDMA \ - UART_getReceiveBufferAddressForDMA -#endif -#ifdef ROM_UART_getTransmitBufferAddressForDMA -#define MAP_UART_getTransmitBufferAddressForDMA \ - ROM_UART_getTransmitBufferAddressForDMA -#else -#define MAP_UART_getTransmitBufferAddressForDMA \ - UART_getTransmitBufferAddressForDMA -#endif -#ifdef ROM_UART_selectDeglitchTime -#define MAP_UART_selectDeglitchTime \ - ROM_UART_selectDeglitchTime -#else -#define MAP_UART_selectDeglitchTime \ - UART_selectDeglitchTime -#endif -#ifdef ROM_UART_enableInterrupt -#define MAP_UART_enableInterrupt \ - ROM_UART_enableInterrupt -#else -#define MAP_UART_enableInterrupt \ - UART_enableInterrupt -#endif -#ifdef ROM_UART_disableInterrupt -#define MAP_UART_disableInterrupt \ - ROM_UART_disableInterrupt -#else -#define MAP_UART_disableInterrupt \ - UART_disableInterrupt -#endif -#ifdef ROM_UART_getInterruptStatus -#define MAP_UART_getInterruptStatus \ - ROM_UART_getInterruptStatus -#else -#define MAP_UART_getInterruptStatus \ - UART_getInterruptStatus -#endif -#ifdef ROM_UART_clearInterruptFlag -#define MAP_UART_clearInterruptFlag \ - ROM_UART_clearInterruptFlag -#else -#define MAP_UART_clearInterruptFlag \ - UART_clearInterruptFlag -#endif -#ifdef ROM_UART_receiveData -#define MAP_UART_receiveData \ - ROM_UART_receiveData -#else -#define MAP_UART_receiveData \ - UART_receiveData -#endif -#ifdef ROM_UART_getEnabledInterruptStatus -#define MAP_UART_getEnabledInterruptStatus \ - ROM_UART_getEnabledInterruptStatus -#else -#define MAP_UART_getEnabledInterruptStatus \ - UART_getEnabledInterruptStatus -#endif -#ifdef ROM_UART_registerInterrupt -#define MAP_UART_registerInterrupt \ - ROM_UART_registerInterrupt -#else -#define MAP_UART_registerInterrupt \ - UART_registerInterrupt -#endif -#ifdef ROM_UART_unregisterInterrupt -#define MAP_UART_unregisterInterrupt \ - ROM_UART_unregisterInterrupt -#else -#define MAP_UART_unregisterInterrupt \ - UART_unregisterInterrupt -#endif - -//***************************************************************************** -// -// Macros for the WDT API. -// -//***************************************************************************** -#ifdef ROM_WDT_A_holdTimer -#define MAP_WDT_A_holdTimer \ - ROM_WDT_A_holdTimer -#else -#define MAP_WDT_A_holdTimer \ - WDT_A_holdTimer -#endif -#ifdef ROM_WDT_A_startTimer -#define MAP_WDT_A_startTimer \ - ROM_WDT_A_startTimer -#else -#define MAP_WDT_A_startTimer \ - WDT_A_startTimer -#endif -#ifdef ROM_WDT_A_clearTimer -#define MAP_WDT_A_clearTimer \ - ROM_WDT_A_clearTimer -#else -#define MAP_WDT_A_clearTimer \ - WDT_A_clearTimer -#endif -#ifdef ROM_WDT_A_initWatchdogTimer -#define MAP_WDT_A_initWatchdogTimer \ - ROM_WDT_A_initWatchdogTimer -#else -#define MAP_WDT_A_initWatchdogTimer \ - WDT_A_initWatchdogTimer -#endif -#ifdef ROM_WDT_A_initIntervalTimer -#define MAP_WDT_A_initIntervalTimer \ - ROM_WDT_A_initIntervalTimer -#else -#define MAP_WDT_A_initIntervalTimer \ - WDT_A_initIntervalTimer -#endif -#ifdef ROM_WDT_A_registerInterrupt -#define MAP_WDT_A_registerInterrupt \ - ROM_WDT_A_registerInterrupt -#else -#define MAP_WDT_A_registerInterrupt \ - WDT_A_registerInterrupt -#endif -#ifdef ROM_WDT_A_unregisterInterrupt -#define MAP_WDT_A_unregisterInterrupt \ - ROM_WDT_A_unregisterInterrupt -#else -#define MAP_WDT_A_unregisterInterrupt \ - WDT_A_unregisterInterrupt -#endif -#ifdef ROM_WDT_A_setPasswordViolationReset -#define MAP_WDT_A_setPasswordViolationReset \ - ROM_WDT_A_setPasswordViolationReset -#else -#define MAP_WDT_A_setPasswordViolationReset \ - WDT_A_setPasswordViolationReset -#endif -#ifdef ROM_WDT_A_setTimeoutReset -#define MAP_WDT_A_setTimeoutReset \ - ROM_WDT_A_setTimeoutReset -#else -#define MAP_WDT_A_setTimeoutReset \ - WDT_A_setTimeoutReset -#endif - -//***************************************************************************** -// -// Macros for the SysCtl_A API. -// -//***************************************************************************** -#ifdef ROM_SysCtl_A_getSRAMSize -#define MAP_SysCtl_A_getSRAMSize \ - ROM_SysCtl_A_getSRAMSize -#else -#define MAP_SysCtl_A_getSRAMSize \ - SysCtl_A_getSRAMSize -#endif -#ifdef ROM_SysCtl_A_getFlashSize -#define MAP_SysCtl_A_getFlashSize \ - ROM_SysCtl_A_getFlashSize -#else -#define MAP_SysCtl_A_getFlashSize \ - SysCtl_A_getFlashSize -#endif -#ifdef ROM_SysCtl_A_rebootDevice -#define MAP_SysCtl_A_rebootDevice \ - ROM_SysCtl_A_rebootDevice -#else -#define MAP_SysCtl_A_rebootDevice \ - SysCtl_A_rebootDevice -#endif -#ifdef ROM_SysCtl_A_enableSRAM -#define MAP_SysCtl_A_enableSRAM \ - ROM_SysCtl_A_enableSRAM -#else -#define MAP_SysCtl_A_enableSRAM \ - SysCtl_A_enableSRAM -#endif -#ifdef ROM_SysCtl_A_disableSRAM -#define MAP_SysCtl_A_disableSRAM \ - ROM_SysCtl_A_disableSRAM -#else -#define MAP_SysCtl_A_disableSRAM \ - SysCtl_A_disableSRAM -#endif -#ifdef ROM_SysCtl_A_enableSRAMRetention -#define MAP_SysCtl_A_enableSRAMRetention \ - ROM_SysCtl_A_enableSRAMRetention -#else -#define MAP_SysCtl_A_enableSRAMRetention \ - SysCtl_A_enableSRAMRetention -#endif -#ifdef ROM_SysCtl_A_disableSRAMRetention -#define MAP_SysCtl_A_disableSRAMRetention \ - ROM_SysCtl_A_disableSRAMRetention -#else -#define MAP_SysCtl_A_disableSRAMRetention \ - SysCtl_A_disableSRAMRetention -#endif -#ifdef ROM_SysCtl_A_enablePeripheralAtCPUHalt -#define MAP_SysCtl_A_enablePeripheralAtCPUHalt \ - ROM_SysCtl_A_enablePeripheralAtCPUHalt -#else -#define MAP_SysCtl_A_enablePeripheralAtCPUHalt \ - SysCtl_A_enablePeripheralAtCPUHalt -#endif -#ifdef ROM_SysCtl_A_disablePeripheralAtCPUHalt -#define MAP_SysCtl_A_disablePeripheralAtCPUHalt \ - ROM_SysCtl_A_disablePeripheralAtCPUHalt -#else -#define MAP_SysCtl_A_disablePeripheralAtCPUHalt \ - SysCtl_A_disablePeripheralAtCPUHalt -#endif -#ifdef ROM_SysCtl_A_setWDTTimeoutResetType -#define MAP_SysCtl_A_setWDTTimeoutResetType \ - ROM_SysCtl_A_setWDTTimeoutResetType -#else -#define MAP_SysCtl_A_setWDTTimeoutResetType \ - SysCtl_A_setWDTTimeoutResetType -#endif -#ifdef ROM_SysCtl_A_setWDTPasswordViolationResetType -#define MAP_SysCtl_A_setWDTPasswordViolationResetType \ - ROM_SysCtl_A_setWDTPasswordViolationResetType -#else -#define MAP_SysCtl_A_setWDTPasswordViolationResetType \ - SysCtl_A_setWDTPasswordViolationResetType -#endif -#ifdef ROM_SysCtl_A_disableNMISource -#define MAP_SysCtl_A_disableNMISource \ - ROM_SysCtl_A_disableNMISource -#else -#define MAP_SysCtl_A_disableNMISource \ - SysCtl_A_disableNMISource -#endif -#ifdef ROM_SysCtl_A_enableNMISource -#define MAP_SysCtl_A_enableNMISource \ - ROM_SysCtl_A_enableNMISource -#else -#define MAP_SysCtl_A_enableNMISource \ - SysCtl_A_enableNMISource -#endif -#ifdef ROM_SysCtl_A_getNMISourceStatus -#define MAP_SysCtl_A_getNMISourceStatus \ - ROM_SysCtl_A_getNMISourceStatus -#else -#define MAP_SysCtl_A_getNMISourceStatus \ - SysCtl_A_getNMISourceStatus -#endif -#ifdef ROM_SysCtl_A_getTempCalibrationConstant -#define MAP_SysCtl_A_getTempCalibrationConstant \ - ROM_SysCtl_A_getTempCalibrationConstant -#else -#define MAP_SysCtl_A_getTempCalibrationConstant \ - SysCtl_A_getTempCalibrationConstant -#endif -#ifdef ROM_SysCtl_A_enableGlitchFilter -#define MAP_SysCtl_A_enableGlitchFilter \ - ROM_SysCtl_A_enableGlitchFilter -#else -#define MAP_SysCtl_A_enableGlitchFilter \ - SysCtl_A_enableGlitchFilter -#endif -#ifdef ROM_SysCtl_A_disableGlitchFilter -#define MAP_SysCtl_A_disableGlitchFilter \ - ROM_SysCtl_A_disableGlitchFilter -#else -#define MAP_SysCtl_A_disableGlitchFilter \ - SysCtl_A_disableGlitchFilter -#endif -#ifdef ROM_SysCtl_A_getTLVInfo -#define MAP_SysCtl_A_getTLVInfo \ - ROM_SysCtl_A_getTLVInfo -#else -#define MAP_SysCtl_A_getTLVInfo \ - SysCtl_A_getTLVInfo -#endif -#ifdef ROM_SysCtl_A_getInfoFlashSize -#define MAP_SysCtl_A_getInfoFlashSize \ - ROM_SysCtl_A_getInfoFlashSize -#else -#define MAP_SysCtl_A_getInfoFlashSize \ - SysCtl_A_getInfoFlashSize -#endif - -//***************************************************************************** -// -// Macros for the Flash_A API. -// -//***************************************************************************** -#ifdef ROM_FlashCtl_A_enableReadParityCheck -#define MAP_FlashCtl_A_enableReadParityCheck \ - ROM_FlashCtl_A_enableReadParityCheck -#else -#define MAP_FlashCtl_A_enableReadParityCheck \ - FlashCtl_A_enableReadParityCheck -#endif -#ifdef ROM_FlashCtl_A_disableReadParityCheck -#define MAP_FlashCtl_A_disableReadParityCheck \ - ROM_FlashCtl_A_disableReadParityCheck -#else -#define MAP_FlashCtl_A_disableReadParityCheck \ - FlashCtl_A_disableReadParityCheck -#endif -#ifdef ROM_FlashCtl_A_enableReadBuffering -#define MAP_FlashCtl_A_enableReadBuffering \ - ROM_FlashCtl_A_enableReadBuffering -#else -#define MAP_FlashCtl_A_enableReadBuffering \ - FlashCtl_A_enableReadBuffering -#endif -#ifdef ROM_FlashCtl_A_disableReadBuffering -#define MAP_FlashCtl_A_disableReadBuffering \ - ROM_FlashCtl_A_disableReadBuffering -#else -#define MAP_FlashCtl_A_disableReadBuffering \ - FlashCtl_A_disableReadBuffering -#endif -#ifdef ROM_FlashCtl_A_unprotectMemory -#define MAP_FlashCtl_A_unprotectMemory \ - ROM_FlashCtl_A_unprotectMemory -#else -#define MAP_FlashCtl_A_unprotectMemory \ - FlashCtl_A_unprotectMemory -#endif -#ifdef ROM_FlashCtl_A_protectMemory -#define MAP_FlashCtl_A_protectMemory \ - ROM_FlashCtl_A_protectMemory -#else -#define MAP_FlashCtl_A_protectMemory \ - FlashCtl_A_protectMemory -#endif -#ifdef ROM_FlashCtl_A_isMemoryRangeProtected -#define MAP_FlashCtl_A_isMemoryRangeProtected \ - ROM_FlashCtl_A_isMemoryRangeProtected -#else -#define MAP_FlashCtl_A_isMemoryRangeProtected \ - FlashCtl_A_isMemoryRangeProtected -#endif -#ifdef ROM_FlashCtl_A_verifyMemory -#define MAP_FlashCtl_A_verifyMemory \ - ROM_FlashCtl_A_verifyMemory -#else -#define MAP_FlashCtl_A_verifyMemory \ - FlashCtl_A_verifyMemory -#endif -#ifdef ROM_FlashCtl_A_performMassErase -#define MAP_FlashCtl_A_performMassErase \ - ROM_FlashCtl_A_performMassErase -#else -#define MAP_FlashCtl_A_performMassErase \ - FlashCtl_A_performMassErase -#endif -#ifdef ROM_FlashCtl_A_eraseSector -#define MAP_FlashCtl_A_eraseSector \ - ROM_FlashCtl_A_eraseSector -#else -#define MAP_FlashCtl_A_eraseSector \ - FlashCtl_A_eraseSector -#endif -#ifdef ROM_FlashCtl_A_programMemory -#define MAP_FlashCtl_A_programMemory \ - ROM_FlashCtl_A_programMemory -#else -#define MAP_FlashCtl_A_programMemory \ - FlashCtl_A_programMemory -#endif -#ifdef ROM_FlashCtl_A_setProgramVerification -#define MAP_FlashCtl_A_setProgramVerification \ - ROM_FlashCtl_A_setProgramVerification -#else -#define MAP_FlashCtl_A_setProgramVerification \ - FlashCtl_A_setProgramVerification -#endif -#ifdef ROM_FlashCtl_A_clearProgramVerification -#define MAP_FlashCtl_A_clearProgramVerification \ - ROM_FlashCtl_A_clearProgramVerification -#else -#define MAP_FlashCtl_A_clearProgramVerification \ - FlashCtl_A_clearProgramVerification -#endif -#ifdef ROM_FlashCtl_A_enableWordProgramming -#define MAP_FlashCtl_A_enableWordProgramming \ - ROM_FlashCtl_A_enableWordProgramming -#else -#define MAP_FlashCtl_A_enableWordProgramming \ - FlashCtl_A_enableWordProgramming -#endif -#ifdef ROM_FlashCtl_A_disableWordProgramming -#define MAP_FlashCtl_A_disableWordProgramming \ - ROM_FlashCtl_A_disableWordProgramming -#else -#define MAP_FlashCtl_A_disableWordProgramming \ - FlashCtl_A_disableWordProgramming -#endif -#ifdef ROM_FlashCtl_A_isWordProgrammingEnabled -#define MAP_FlashCtl_A_isWordProgrammingEnabled \ - ROM_FlashCtl_A_isWordProgrammingEnabled -#else -#define MAP_FlashCtl_A_isWordProgrammingEnabled \ - FlashCtl_A_isWordProgrammingEnabled -#endif -#ifdef ROM_FlashCtl_A_enableInterrupt -#define MAP_FlashCtl_A_enableInterrupt \ - ROM_FlashCtl_A_enableInterrupt -#else -#define MAP_FlashCtl_A_enableInterrupt \ - FlashCtl_A_enableInterrupt -#endif -#ifdef ROM_FlashCtl_A_disableInterrupt -#define MAP_FlashCtl_A_disableInterrupt \ - ROM_FlashCtl_A_disableInterrupt -#else -#define MAP_FlashCtl_A_disableInterrupt \ - FlashCtl_A_disableInterrupt -#endif -#ifdef ROM_FlashCtl_A_getEnabledInterruptStatus -#define MAP_FlashCtl_A_getEnabledInterruptStatus \ - ROM_FlashCtl_A_getEnabledInterruptStatus -#else -#define MAP_FlashCtl_A_getEnabledInterruptStatus \ - FlashCtl_A_getEnabledInterruptStatus -#endif -#ifdef ROM_FlashCtl_A_getInterruptStatus -#define MAP_FlashCtl_A_getInterruptStatus \ - ROM_FlashCtl_A_getInterruptStatus -#else -#define MAP_FlashCtl_A_getInterruptStatus \ - FlashCtl_A_getInterruptStatus -#endif -#ifdef ROM_FlashCtl_A_clearInterruptFlag -#define MAP_FlashCtl_A_clearInterruptFlag \ - ROM_FlashCtl_A_clearInterruptFlag -#else -#define MAP_FlashCtl_A_clearInterruptFlag \ - FlashCtl_A_clearInterruptFlag -#endif -#ifdef ROM_FlashCtl_A_setWaitState -#define MAP_FlashCtl_A_setWaitState \ - ROM_FlashCtl_A_setWaitState -#else -#define MAP_FlashCtl_A_setWaitState \ - FlashCtl_A_setWaitState -#endif -#ifdef ROM_FlashCtl_A_getWaitState -#define MAP_FlashCtl_A_getWaitState \ - ROM_FlashCtl_A_getWaitState -#else -#define MAP_FlashCtl_A_getWaitState \ - FlashCtl_A_getWaitState -#endif -#ifdef ROM_FlashCtl_A_setReadMode -#define MAP_FlashCtl_A_setReadMode \ - ROM_FlashCtl_A_setReadMode -#else -#define MAP_FlashCtl_A_setReadMode \ - FlashCtl_A_setReadMode -#endif -#ifdef ROM_FlashCtl_A_getReadMode -#define MAP_FlashCtl_A_getReadMode \ - ROM_FlashCtl_A_getReadMode -#else -#define MAP_FlashCtl_A_getReadMode \ - FlashCtl_A_getReadMode -#endif -#ifdef ROM_FlashCtl_A_registerInterrupt -#define MAP_FlashCtl_A_registerInterrupt \ - ROM_FlashCtl_A_registerInterrupt -#else -#define MAP_FlashCtl_A_registerInterrupt \ - FlashCtl_A_registerInterrupt -#endif -#ifdef ROM_FlashCtl_A_unregisterInterrupt -#define MAP_FlashCtl_A_unregisterInterrupt \ - ROM_FlashCtl_A_unregisterInterrupt -#else -#define MAP_FlashCtl_A_unregisterInterrupt \ - FlashCtl_A_unregisterInterrupt -#endif -#ifdef ROM___FlashCtl_A_remaskData8Post -#define MAP___FlashCtl_A_remaskData8Post \ - ROM___FlashCtl_A_remaskData8Post -#else -#define MAP___FlashCtl_A_remaskData8Post \ - __FlashCtl_A_remaskData8Post -#endif -#ifdef ROM___FlashCtl_A_remaskData8Pre -#define MAP___FlashCtl_A_remaskData8Pre \ - ROM___FlashCtl_A_remaskData8Pre -#else -#define MAP___FlashCtl_A_remaskData8Pre \ - __FlashCtl_A_remaskData8Pre -#endif -#ifdef ROM___FlashCtl_A_remaskData32Pre -#define MAP___FlashCtl_A_remaskData32Pre \ - ROM___FlashCtl_A_remaskData32Pre -#else -#define MAP___FlashCtl_A_remaskData32Pre \ - __FlashCtl_A_remaskData32Pre -#endif -#ifdef ROM___FlashCtl_A_remaskData32Post -#define MAP___FlashCtl_A_remaskData32Post \ - ROM___FlashCtl_A_remaskData32Post -#else -#define MAP___FlashCtl_A_remaskData32Post \ - __FlashCtl_A_remaskData32Post -#endif -#ifdef ROM___FlashCtl_A_remaskBurstDataPre -#define MAP___FlashCtl_A_remaskBurstDataPre \ - ROM___FlashCtl_A_remaskBurstDataPre -#else -#define MAP___FlashCtl_A_remaskBurstDataPre \ - __FlashCtl_A_remaskBurstDataPre -#endif -#ifdef ROM___FlashCtl_A_remaskBurstDataPost -#define MAP___FlashCtl_A_remaskBurstDataPost \ - ROM___FlashCtl_A_remaskBurstDataPost -#else -#define MAP___FlashCtl_A_remaskBurstDataPost \ - __FlashCtl_A_remaskBurstDataPost -#endif -#ifdef ROM_FlashCtl_A_initiateSectorErase -#define MAP_FlashCtl_A_initiateSectorErase \ - ROM_FlashCtl_A_initiateSectorErase -#else -#define MAP_FlashCtl_A_initiateSectorErase \ - FlashCtl_A_initiateSectorErase -#endif -#ifdef ROM_FlashCtl_A_initiateMassErase -#define MAP_FlashCtl_A_initiateMassErase \ - ROM_FlashCtl_A_initiateMassErase -#else -#define MAP_FlashCtl_A_initiateMassErase \ - FlashCtl_A_initiateMassErase -#endif -#ifdef ROM_FlashCtl_A_isMemoryProtected -#define MAP_FlashCtl_A_isMemoryProtected \ - ROM_FlashCtl_A_isMemoryProtected -#else -#define MAP_FlashCtl_A_isMemoryProtected \ - FlashCtl_A_isMemoryProtected -#endif -#ifdef ROM_FlashCtl_A_getMemoryInfo -#define MAP_FlashCtl_A_getMemoryInfo \ - ROM_FlashCtl_A_getMemoryInfo -#else -#define MAP_FlashCtl_A_getMemoryInfo \ - FlashCtl_A_getMemoryInfo -#endif - -//***************************************************************************** -// -// Macros for the LCD_F API. -// -//***************************************************************************** -#ifdef ROM_LCD_F_initModule -#define MAP_LCD_F_initModule \ - ROM_LCD_F_initModule -#else -#define MAP_LCD_F_initModule \ - LCD_F_initModule -#endif -#ifdef ROM_LCD_F_turnOn -#define MAP_LCD_F_turnOn \ - ROM_LCD_F_turnOn -#else -#define MAP_LCD_F_turnOn \ - LCD_F_turnOn -#endif -#ifdef ROM_LCD_F_turnOff -#define MAP_LCD_F_turnOff \ - ROM_LCD_F_turnOff -#else -#define MAP_LCD_F_turnOff \ - LCD_F_turnOff -#endif -#ifdef ROM_LCD_F_clearAllMemory -#define MAP_LCD_F_clearAllMemory \ - ROM_LCD_F_clearAllMemory -#else -#define MAP_LCD_F_clearAllMemory \ - LCD_F_clearAllMemory -#endif -#ifdef ROM_LCD_F_clearAllBlinkingMemory -#define MAP_LCD_F_clearAllBlinkingMemory \ - ROM_LCD_F_clearAllBlinkingMemory -#else -#define MAP_LCD_F_clearAllBlinkingMemory \ - LCD_F_clearAllBlinkingMemory -#endif -#ifdef ROM_LCD_F_selectDisplayMemory -#define MAP_LCD_F_selectDisplayMemory \ - ROM_LCD_F_selectDisplayMemory -#else -#define MAP_LCD_F_selectDisplayMemory \ - LCD_F_selectDisplayMemory -#endif -#ifdef ROM_LCD_F_setBlinkingControl -#define MAP_LCD_F_setBlinkingControl \ - ROM_LCD_F_setBlinkingControl -#else -#define MAP_LCD_F_setBlinkingControl \ - LCD_F_setBlinkingControl -#endif -#ifdef ROM_LCD_F_setAnimationControl -#define MAP_LCD_F_setAnimationControl \ - ROM_LCD_F_setAnimationControl -#else -#define MAP_LCD_F_setAnimationControl \ - LCD_F_setAnimationControl -#endif -#ifdef ROM_LCD_F_clearAllAnimationMemory -#define MAP_LCD_F_clearAllAnimationMemory \ - ROM_LCD_F_clearAllAnimationMemory -#else -#define MAP_LCD_F_clearAllAnimationMemory \ - LCD_F_clearAllAnimationMemory -#endif -#ifdef ROM_LCD_F_setPinAsLCDFunction -#define MAP_LCD_F_setPinAsLCDFunction \ - ROM_LCD_F_setPinAsLCDFunction -#else -#define MAP_LCD_F_setPinAsLCDFunction \ - LCD_F_setPinAsLCDFunction -#endif -#ifdef ROM_LCD_F_setPinAsPortFunction -#define MAP_LCD_F_setPinAsPortFunction \ - ROM_LCD_F_setPinAsPortFunction -#else -#define MAP_LCD_F_setPinAsPortFunction \ - LCD_F_setPinAsPortFunction -#endif -#ifdef ROM_LCD_F_setPinsAsLCDFunction -#define MAP_LCD_F_setPinsAsLCDFunction \ - ROM_LCD_F_setPinsAsLCDFunction -#else -#define MAP_LCD_F_setPinsAsLCDFunction \ - LCD_F_setPinsAsLCDFunction -#endif -#ifdef ROM_LCD_F_setPinAsCOM -#define MAP_LCD_F_setPinAsCOM \ - ROM_LCD_F_setPinAsCOM -#else -#define MAP_LCD_F_setPinAsCOM \ - LCD_F_setPinAsCOM -#endif -#ifdef ROM_LCD_F_setPinAsSEG -#define MAP_LCD_F_setPinAsSEG \ - ROM_LCD_F_setPinAsSEG -#else -#define MAP_LCD_F_setPinAsSEG \ - LCD_F_setPinAsSEG -#endif -#ifdef ROM_LCD_F_selectBias -#define MAP_LCD_F_selectBias \ - ROM_LCD_F_selectBias -#else -#define MAP_LCD_F_selectBias \ - LCD_F_selectBias -#endif -#ifdef ROM_LCD_F_setVLCDSource -#define MAP_LCD_F_setVLCDSource \ - ROM_LCD_F_setVLCDSource -#else -#define MAP_LCD_F_setVLCDSource \ - LCD_F_setVLCDSource -#endif -#ifdef ROM_LCD_F_clearInterrupt -#define MAP_LCD_F_clearInterrupt \ - ROM_LCD_F_clearInterrupt -#else -#define MAP_LCD_F_clearInterrupt \ - LCD_F_clearInterrupt -#endif -#ifdef ROM_LCD_F_getInterruptStatus -#define MAP_LCD_F_getInterruptStatus \ - ROM_LCD_F_getInterruptStatus -#else -#define MAP_LCD_F_getInterruptStatus \ - LCD_F_getInterruptStatus -#endif -#ifdef ROM_LCD_F_getEnabledInterruptStatus -#define MAP_LCD_F_getEnabledInterruptStatus \ - ROM_LCD_F_getEnabledInterruptStatus -#else -#define MAP_LCD_F_getEnabledInterruptStatus \ - LCD_F_getEnabledInterruptStatus -#endif -#ifdef ROM_LCD_F_enableInterrupt -#define MAP_LCD_F_enableInterrupt \ - ROM_LCD_F_enableInterrupt -#else -#define MAP_LCD_F_enableInterrupt \ - LCD_F_enableInterrupt -#endif -#ifdef ROM_LCD_F_disableInterrupt -#define MAP_LCD_F_disableInterrupt \ - ROM_LCD_F_disableInterrupt -#else -#define MAP_LCD_F_disableInterrupt \ - LCD_F_disableInterrupt -#endif -#ifdef ROM_LCD_F_registerInterrupt -#define MAP_LCD_F_registerInterrupt \ - ROM_LCD_F_registerInterrupt -#else -#define MAP_LCD_F_registerInterrupt \ - LCD_F_registerInterrupt -#endif -#ifdef ROM_LCD_F_unregisterInterrupt -#define MAP_LCD_F_unregisterInterrupt \ - ROM_LCD_F_unregisterInterrupt -#else -#define MAP_LCD_F_unregisterInterrupt \ - LCD_F_unregisterInterrupt -#endif - -#endif // __ROM_MAP_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/rtc_c.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/rtc_c.c deleted file mode 100644 index bb82223df5b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/rtc_c.c +++ /dev/null @@ -1,357 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include - - -void RTC_C_startClock(void) -{ - RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY; - BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 0; - BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0; -} - -void RTC_C_holdClock(void) -{ - RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY; - BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1; - BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0; -} - -void RTC_C_setCalibrationFrequency(uint_fast16_t frequencySelect) -{ - RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY; - RTC_C->CTL13 = (RTC_C->CTL13 & ~(RTC_C_CTL13_CALF_3)) | frequencySelect; - BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0; -} - -void RTC_C_setCalibrationData(uint_fast8_t offsetDirection, - uint_fast8_t offsetValue) -{ - RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY; - RTC_C->OCAL = offsetValue + offsetDirection; - BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0; -} - -bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection, - uint_fast8_t offsetValue) -{ - while (!BITBAND_PERI(RTC_C->TCMP, RTC_C_TCMP_TCRDY_OFS)) - ; - - RTC_C->TCMP = offsetValue + offsetDirection; - - if (BITBAND_PERI(RTC_C->TCMP, RTC_C_TCMP_TCOK_OFS)) - return true; - else - return false; -} - -void RTC_C_initCalendar(const RTC_C_Calendar *calendarTime, - uint_fast16_t formatSelect) -{ - RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY; - - BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1; - - if (formatSelect) - BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_BCD_OFS) = 1; - else - BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_BCD_OFS) = 0; - - RTC_C->TIM0 = (calendarTime->minutes << RTC_C_TIM0_MIN_OFS) - | calendarTime->seconds; - RTC_C->TIM1 = (calendarTime->dayOfWeek << RTC_C_TIM1_DOW_OFS) - | calendarTime->hours; - RTC_C->DATE = (calendarTime->month << RTC_C_DATE_MON_OFS) - | calendarTime->dayOfmonth; - RTC_C->YEAR = calendarTime->year; - - BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0; -} - - -RTC_C_Calendar RTC_C_getCalendarTime(void) -{ - RTC_C_Calendar tempCal; - - while (!(BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_RDY_OFS))) - ; - - tempCal.seconds = RTC_C->TIM0 - & (RTC_C_TIM0_SEC_LD_MASK | RTC_C_TIM0_SEC_HD_MASK); - tempCal.minutes = (RTC_C->TIM0 - & (RTC_C_TIM0_MIN_LD_MASK | RTC_C_TIM0_MIN_HD_MASK)) - >> RTC_C_TIM0_MIN_OFS; - tempCal.hours = RTC_C->TIM1 - & (RTC_C_TIM1_HOUR_LD_MASK | RTC_C_TIM1_HOUR_HD_MASK); - tempCal.dayOfWeek = (RTC_C->TIM1 - & (RTC_C_TIM1_DOW_MASK)) >> RTC_C_TIM1_DOW_OFS; - tempCal.dayOfmonth = RTC_C->DATE - & (RTC_C_DATE_DAY_LD_MASK | RTC_C_DATE_DAY_HD_MASK); - tempCal.month = (RTC_C->DATE & (RTC_C_DATE_MON_LD_MASK | RTC_C_DATE_MON_HD)) - >> RTC_C_DATE_MON_OFS; - tempCal.year = RTC_C->YEAR; - - return (tempCal); -} - - -void RTC_C_setCalendarAlarm(uint_fast8_t minutesAlarm, uint_fast8_t hoursAlarm, - uint_fast8_t dayOfWeekAlarm, uint_fast8_t dayOfmonthAlarm) -{ - //Each of these is XORed with 0x80 to turn on if an integer is passed, - //or turn OFF if RTC_ALARM_OFF (0x80) is passed. - RTC_C->AMINHR = ((hoursAlarm ^ 0x80) << 8 )| (minutesAlarm ^ 0x80); - RTC_C->ADOWDAY = ((dayOfmonthAlarm ^ 0x80) << 8 )| (dayOfWeekAlarm ^ 0x80); -} - -void RTC_C_setCalendarEvent(uint_fast16_t eventSelect) -{ - RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY; - RTC_C->CTL13 = (RTC_C->CTL13 & ~(RTC_C_CTL13_TEV_3)) | eventSelect; - BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0; -} - -void RTC_C_definePrescaleEvent(uint_fast8_t prescaleSelect, - uint_fast8_t prescaleEventDivider) -{ - if(prescaleSelect == RTC_C_PRESCALE_0) - { - HWREG8(&RTC_C->PS0CTL) &= ~(RTC_C_PS0CTL_RT0IP_7); - HWREG8(&RTC_C->PS0CTL) |= prescaleEventDivider; - } - else if(prescaleSelect == RTC_C_PRESCALE_1) - { - HWREG8(&RTC_C->PS1CTL) &= ~(RTC_C_PS0CTL_RT0IP_7); - HWREG8(&RTC_C->PS1CTL) |= prescaleEventDivider; - } -} - -uint_fast8_t RTC_C_getPrescaleValue(uint_fast8_t prescaleSelect) -{ - if (RTC_C_PRESCALE_0 == prescaleSelect) - { - return (RTC_C->PS & RTC_C_PS_RT0PS_MASK); - } else if (RTC_C_PRESCALE_1 == prescaleSelect) - { - return (RTC_C->PS & RTC_C_PS_RT1PS_MASK)>>RTC_C_PS_RT1PS_OFS; - } else - { - return (0); - } -} - -void RTC_C_setPrescaleValue(uint_fast8_t prescaleSelect, - uint_fast8_t prescaleCounterValue) -{ - RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY; - - if (RTC_C_PRESCALE_0 == prescaleSelect) - { - RTC_C->PS = (RTC_C->PS & ~RTC_C_PS_RT0PS_MASK) | prescaleCounterValue; - } else if (RTC_C_PRESCALE_1 == prescaleSelect) - { - RTC_C->PS = (RTC_C->PS & ~RTC_C_PS_RT1PS_MASK) - | (prescaleCounterValue << RTC_C_PS_RT1PS_OFS); - } - - BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0; -} - -uint16_t RTC_C_convertBCDToBinary(uint16_t valueToConvert) -{ - RTC_C->BCD2BIN = valueToConvert; - return (RTC_C->BCD2BIN); -} - -uint16_t RTC_C_convertBinaryToBCD(uint16_t valueToConvert) -{ - RTC_C->BIN2BCD = valueToConvert; - return (RTC_C->BIN2BCD); -} - -void RTC_C_enableInterrupt(uint8_t interruptMask) -{ - if (interruptMask - & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE - + RTC_C_CTL0_RDYIE)) - { - RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) - | (RTC_C_KEY - | (interruptMask - & (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE - + RTC_C_CTL0_AIE + RTC_C_CTL0_RDYIE))); - BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0; - } - - if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT) - { - BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIE_OFS) = 1; - } - - if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT) - { - BITBAND_PERI(RTC_C->PS1CTL,RTC_C_PS1CTL_RT1PSIE_OFS) = 1; - } -} - -void RTC_C_disableInterrupt(uint8_t interruptMask) -{ - uint16_t allIntMask = (RTC_C_CTL0_OFIE + RTC_C_CTL0_TEVIE + RTC_C_CTL0_AIE - + RTC_C_CTL0_RDYIE); - - if (interruptMask & allIntMask) - { - RTC_C->CTL0 = (RTC_C->CTL0 - & ~((interruptMask & allIntMask) | RTC_C_CTL0_KEY_MASK)) - | RTC_C_KEY; - - BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0; - } - - if (interruptMask & RTC_C_PRESCALE_TIMER0_INTERRUPT) - { - BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIE_OFS) = 0; - } - - if (interruptMask & RTC_C_PRESCALE_TIMER1_INTERRUPT) - { - BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIE_OFS) = 0; - } -} - -uint_fast8_t RTC_C_getInterruptStatus(void) -{ - uint_fast8_t tempInterruptFlagMask = 0x00; - uint_fast8_t interruptFlagMask = RTC_C_TIME_EVENT_INTERRUPT - | RTC_C_CLOCK_ALARM_INTERRUPT | RTC_C_CLOCK_READ_READY_INTERRUPT - | RTC_C_PRESCALE_TIMER0_INTERRUPT | RTC_C_PRESCALE_TIMER1_INTERRUPT - | RTC_C_OSCILLATOR_FAULT_INTERRUPT; - - tempInterruptFlagMask |= (RTC_C->CTL0 & (interruptFlagMask >> 4)); - - tempInterruptFlagMask = tempInterruptFlagMask << 4; - - if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT) - { - if (BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIFG_OFS)) - { - tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER0_INTERRUPT; - } - } - - if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT) - { - if (BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIFG_OFS)) - { - tempInterruptFlagMask |= RTC_C_PRESCALE_TIMER1_INTERRUPT; - } - } - - return (tempInterruptFlagMask); -} - -uint_fast8_t RTC_C_getEnabledInterruptStatus(void) -{ - - uint32_t intStatus = RTC_C_getInterruptStatus(); - - if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_OFIE_OFS)) - { - intStatus &= ~RTC_C_OSCILLATOR_FAULT_INTERRUPT; - } - - if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_TEVIE_OFS)) - { - intStatus &= ~RTC_C_TIME_EVENT_INTERRUPT; - } - - if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_AIE_OFS)) - { - intStatus &= ~RTC_C_CLOCK_ALARM_INTERRUPT; - } - - if (!BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_RDYIE_OFS)) - { - intStatus &= ~RTC_C_CLOCK_READ_READY_INTERRUPT; - } - - if (!BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIE_OFS)) - { - intStatus &= ~RTC_C_PRESCALE_TIMER0_INTERRUPT; - } - - if (!BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIE_OFS)) - { - intStatus &= ~RTC_C_PRESCALE_TIMER1_INTERRUPT; - } - - return intStatus; -} - -void RTC_C_clearInterruptFlag(uint_fast8_t interruptFlagMask) -{ - if (interruptFlagMask - & (RTC_C_TIME_EVENT_INTERRUPT + RTC_C_CLOCK_ALARM_INTERRUPT - + RTC_C_CLOCK_READ_READY_INTERRUPT - + RTC_C_OSCILLATOR_FAULT_INTERRUPT)) - { - RTC_C->CTL0 = RTC_C_KEY - | (RTC_C->CTL0 & ~((interruptFlagMask >> 4) | RTC_C_CTL0_KEY_MASK)); - BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0; - } - - if (interruptFlagMask & RTC_C_PRESCALE_TIMER0_INTERRUPT) - { - BITBAND_PERI(RTC_C->PS0CTL, RTC_C_PS0CTL_RT0PSIFG_OFS) = 0; - } - - if (interruptFlagMask & RTC_C_PRESCALE_TIMER1_INTERRUPT) - { - BITBAND_PERI(RTC_C->PS1CTL, RTC_C_PS1CTL_RT1PSIFG_OFS) = 0; - } -} - -void RTC_C_registerInterrupt(void (*intHandler)(void)) -{ - Interrupt_registerInterrupt(INT_RTC_C, intHandler); - Interrupt_enableInterrupt(INT_RTC_C); -} - -void RTC_C_unregisterInterrupt(void) -{ - Interrupt_disableInterrupt(INT_RTC_C); - Interrupt_unregisterInterrupt(INT_RTC_C); -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/rtc_c.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/rtc_c.h deleted file mode 100644 index cdb994d63b4..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/rtc_c.h +++ /dev/null @@ -1,657 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef RTC_C_H_ -#define RTC_C_H_ - -//***************************************************************************** -// -//! \addtogroup rtc_api -//! @{ -// -//***************************************************************************** - - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include - -//***************************************************************************** -// -//The following is a struct that can be passed to RTC_CalendarInit() in the -//CalendarTime parameter, as well as returned by RTC_getCalendarTime() -// -//***************************************************************************** -typedef struct _RTC_C_Calendar -{ - uint_fast8_t seconds; - uint_fast8_t minutes; - uint_fast8_t hours; - uint_fast8_t dayOfWeek; - uint_fast8_t dayOfmonth; - uint_fast8_t month; - uint_fast16_t year; -} RTC_C_Calendar; - -//***************************************************************************** -// -//The following are values that can be passed to RTC_setCalibrationData() -// -//***************************************************************************** -#define RTC_C_CALIBRATIONFREQ_OFF (RTC_C_CTL13_CALF_0) -#define RTC_C_CALIBRATIONFREQ_512HZ (RTC_C_CTL13_CALF_1) -#define RTC_C_CALIBRATIONFREQ_256HZ (RTC_C_CTL13_CALF_2) -#define RTC_C_CALIBRATIONFREQ_1HZ (RTC_C_CTL13_CALF_3) - -//***************************************************************************** -// -//The following are values that can be passed to RTC_setCalibrationData() -// -//***************************************************************************** -#define RTC_C_CALIBRATION_DOWN1PPM ( !(RTC_C_OCAL_OCALS) ) -#define RTC_C_CALIBRATION_UP1PPM (RTC_C_OCAL_OCALS) - -//***************************************************************************** -// -//The following are values that can be passed to -//RTC_setTemperatureCompensation() -// -//***************************************************************************** -#define RTC_C_COMPENSATION_DOWN1PPM ( !(RTC_C_TCMP_TCMPS) ) -#define RTC_C_COMPENSATION_UP1PPM (RTC_C_TCMP_TCMPS) - -//***************************************************************************** -// -//The following are values that can be passed to RTC_iniRTC_Calendar() -// -//***************************************************************************** -#define RTC_C_FORMAT_BINARY ( !(RTC_C_CTL13_BCD) ) -#define RTC_C_FORMAT_BCD (RTC_C_CTL13_BCD) - -//***************************************************************************** -// -//The following is a value that can be passed to RTC_seRTC_CalendarAlarm() -// -//***************************************************************************** -#define RTC_C_ALARMCONDITION_OFF (0x80) - -//***************************************************************************** -// -//The following are values that can be passed to RTC_seRTC_CalendarEvent() -//in the eventSelect parameter. -// -//***************************************************************************** -#define RTC_C_CALENDAREVENT_MINUTECHANGE (RTC_C_CTL13_TEV_0) -#define RTC_C_CALENDAREVENT_HOURCHANGE (RTC_C_CTL13_TEV_1) -#define RTC_C_CALENDAREVENT_NOON (RTC_C_CTL13_TEV_2) -#define RTC_C_CALENDAREVENT_MIDNIGHT (RTC_C_CTL13_TEV_3) - -//***************************************************************************** -// -//The following are values that can be passed to RTC_definePrescaleEvent() -// -//***************************************************************************** -#define RTC_C_PRESCALE_0 (0x0) -#define RTC_C_PRESCALE_1 (0x1) - -//***************************************************************************** -// -//The following are values that can be passed to RTC_definePrescaleEvent() -//in the prescaleEventDivider parameter. -// -//***************************************************************************** -#define RTC_C_PSEVENTDIVIDER_2 (RTC_C_PS0CTL_RT0IP_0) -#define RTC_C_PSEVENTDIVIDER_4 (RTC_C_PS0CTL_RT0IP_1) -#define RTC_C_PSEVENTDIVIDER_8 (RTC_C_PS0CTL_RT0IP_2) -#define RTC_C_PSEVENTDIVIDER_16 (RTC_C_PS0CTL_RT0IP_3) -#define RTC_C_PSEVENTDIVIDER_32 (RTC_C_PS0CTL_RT0IP_4) -#define RTC_C_PSEVENTDIVIDER_64 (RTC_C_PS0CTL_RT0IP_5) -#define RTC_C_PSEVENTDIVIDER_128 (RTC_C_PS0CTL_RT0IP_6) -#define RTC_C_PSEVENTDIVIDER_256 (RTC_C_PS0CTL_RT0IP_7) - -//***************************************************************************** -// -//The following are values that can be passed to the interrupt functions -// -//***************************************************************************** -#define RTC_C_OSCILLATOR_FAULT_INTERRUPT RTC_C_CTL0_OFIE -#define RTC_C_TIME_EVENT_INTERRUPT RTC_C_CTL0_TEVIE -#define RTC_C_CLOCK_ALARM_INTERRUPT RTC_C_CTL0_AIE -#define RTC_C_CLOCK_READ_READY_INTERRUPT RTC_C_CTL0_RDYIE -#define RTC_C_PRESCALE_TIMER0_INTERRUPT 0x02 -#define RTC_C_PRESCALE_TIMER1_INTERRUPT 0x01 - -//***************************************************************************** -// -//! Starts the RTC. -//! -//! This function clears the RTC main hold bit to allow the RTC to function. -//! -//! \return None -// -//***************************************************************************** -extern void RTC_C_startClock(void); - -//***************************************************************************** -// -//! Holds the RTC. -//! -//! This function sets the RTC main hold bit to disable RTC functionality. -//! -//! \return None -// -//***************************************************************************** -extern void RTC_C_holdClock(void); - -//***************************************************************************** -// -//! Allows and Sets the frequency output to RTCLK pin for calibration -//! measurement. -//! -//! \param frequencySelect is the frequency output to RTCLK. -//! Valid values are -//! - \b RTC_C_CALIBRATIONFREQ_OFF - turn off calibration -//! output [Default] -//! - \b RTC_C_CALIBRATIONFREQ_512HZ - output signal at 512Hz -//! for calibration -//! - \b RTC_C_CALIBRATIONFREQ_256HZ - output signal at 256Hz -//! for calibration -//! - \b RTC_C_CALIBRATIONFREQ_1HZ - output signal at 1Hz -//! for calibration -//! -//! This function sets a frequency to measure at the RTCLK output pin. After -//! testing the set frequency, the calibration could be set accordingly. -//! -//! \return None -// -//***************************************************************************** -extern void RTC_C_setCalibrationFrequency(uint_fast16_t frequencySelect); - -//***************************************************************************** -// -//! Sets the specified calibration for the RTC. -//! -//! \param offsetDirection is the direction that the calibration offset will -//! go. Valid values are -//! - \b RTC_C_CALIBRATION_DOWN1PPM - calibrate at steps of -1 -//! - \b RTC_C_CALIBRATION_UP1PPM - calibrat at steps of +1 -//! \param offsetValue is the value that the offset will be a factor of; a -//! valid value is any integer from 1-240. -//! -//! This function sets the calibration offset to make the RTC as accurate as -//! possible. The offsetDirection can be either +1-ppm or -1-ppm, and the -//! offsetValue should be from 1-240 and is multiplied by the direction setting -//! (i.e. +1-ppm * 8 (offsetValue) = +8-ppm). -//! -//! \return None -// -//***************************************************************************** -extern void RTC_C_setCalibrationData(uint_fast8_t offsetDirection, - uint_fast8_t offsetValue); - -//***************************************************************************** -// -//! Sets the specified temperature compensation for the RTC. -//! -//! \param offsetDirection is the direction that the calibration offset will -//! go. Valid values are -//! - \b RTC_C_COMPENSATION_DOWN1PPM - calibrate at steps of -1 -//! - \b RTC_C_COMPENSATION_UP1PPM - calibrate at steps of +1 -//! \param offsetValue is the value that the offset will be a factor of; a -//! value is any integer from 1-240. -//! -//! This function sets the calibration offset to make the RTC as accurate as -//! possible. The offsetDirection can be either +1-ppm or -1-ppm, and the -//! offsetValue should be from 1-240 and is multiplied by the direction setting -//! (i.e. +1-ppm * 8 (offsetValue) = +8-ppm). -//! -//! \return true if calibration was set, false if it could not be set -//! -// -//***************************************************************************** -extern bool RTC_C_setTemperatureCompensation(uint_fast16_t offsetDirection, - uint_fast8_t offsetValue); - -//***************************************************************************** -// -//! Initializes the settings to operate the RTC in Calendar mode. -//! -//! \param calendarTime is the structure containing the values for the Calendar -//! to be initialized to. -//! Valid values should be of type Calendar and should contain the -//! following members and corresponding values: -//! - \b seconds between 0-59 -//! - \b minutes between 0-59 -//! - \b hours between 0-23 -//! - \b dayOfWeek between 0-6 -//! - \b dayOfmonth between 1-31 -//! - \b month between 1-12 -//! - \b year between 0-4095 -//! \note Values beyond the ones specified may result in erratic behavior. -//! \param formatSelect is the format for the Calendar registers to use. -//! Valid values are -//! - \b RTC_C_FORMAT_BINARY [Default] -//! - \b RTC_C_FORMAT_BCD -//! -//! This function initializes the Calendar mode of the RTC module. -//! -//! \return None -// -//***************************************************************************** -extern void RTC_C_initCalendar(const RTC_C_Calendar *calendarTime, - uint_fast16_t formatSelect); - -//***************************************************************************** -// -//! Returns the Calendar Time stored in the Calendar registers of the RTC. -//! -//! -//! This function returns the current Calendar time in the form of a Calendar -//! structure. -//! -//! \return A Calendar structure containing the current time. -// -//***************************************************************************** -extern RTC_C_Calendar RTC_C_getCalendarTime(void); - -//***************************************************************************** -// -//! Sets and Enables the desired Calendar Alarm settings. -//! -//! \param minutesAlarm is the alarm condition for the minutes. -//! Valid values are -//! - An integer between 0-59, OR -//! - \b RTC_C_ALARMCONDITION_OFF [Default] -//! \param hoursAlarm is the alarm condition for the hours. -//! Valid values are -//! - An integer between 0-24, OR -//! - \b RTC_C_ALARMCONDITION_OFF [Default] -//! \param dayOfWeekAlarm is the alarm condition for the day of week. -//! Valid values are -//! - An integer between 0-6, OR -//! - \b RTC_C_ALARMCONDITION_OFF [Default] -//! \param dayOfmonthAlarm is the alarm condition for the day of the month. -//! Valid values are -//! - An integer between 0-31, OR -//! - \b RTC_C_ALARMCONDITION_OFF [Default] -//! -//! This function sets a Calendar interrupt condition to assert the RTCAIFG -//! interrupt flag. The condition is a logical and of all of the parameters. -//! For example if the minutes and hours alarm is set, then the interrupt will -//! only assert when the minutes AND the hours change to the specified setting. -//! Use the RTC_ALARM_OFF for any alarm settings that should not be apart of -//! the alarm condition. -//! -//! \return None -// -//***************************************************************************** -extern void RTC_C_setCalendarAlarm(uint_fast8_t minutesAlarm, - uint_fast8_t hoursAlarm, uint_fast8_t dayOfWeekAlarm, - uint_fast8_t dayOfmonthAlarm); - -//***************************************************************************** -// -//! Sets a single specified Calendar interrupt condition. -//! -//! \param eventSelect is the condition selected. -//! Valid values are -//! - \b RTC_C_CALENDAREVENT_MINUTECHANGE - assert interrupt on every -//! minute -//! - \b RTC_C_CALENDAREVENT_HOURCHANGE - assert interrupt on every hour -//! - \b RTC_C_CALENDAREVENT_NOON - assert interrupt when hour is 12 -//! - \b RTC_C_CALENDAREVENT_MIDNIGHT - assert interrupt when hour is 0 -//! -//! This function sets a specified event to assert the RTCTEVIFG interrupt. This -//! interrupt is independent from the Calendar alarm interrupt. -//! -//! \return None -// -//***************************************************************************** -extern void RTC_C_setCalendarEvent(uint_fast16_t eventSelect); - -//***************************************************************************** -// -//! Sets up an interrupt condition for the selected Prescaler. -//! -//! \param prescaleSelect is the prescaler to define an interrupt for. -//! Valid values are -//! - \b RTC_C_PRESCALE_0 -//! - \b RTC_C_PRESCALE_1 -//! \param prescaleEventDivider is a divider to specify when an interrupt can -//! occur based on the clock source of the selected prescaler. -//! (Does not affect timer of the selected prescaler). -//! Valid values are -//! - \b RTC_C_PSEVENTDIVIDER_2 [Default] -//! - \b RTC_C_PSEVENTDIVIDER_4 -//! - \b RTC_C_PSEVENTDIVIDER_8 -//! - \b RTC_C_PSEVENTDIVIDER_16 -//! - \b RTC_C_PSEVENTDIVIDER_32 -//! - \b RTC_C_PSEVENTDIVIDER_64 -//! - \b RTC_C_PSEVENTDIVIDER_128 -//! - \b RTC_C_PSEVENTDIVIDER_256 -//! -//! This function sets the condition for an interrupt to assert based on the -//! individual prescalers. -//! -//! \return None -// -//***************************************************************************** -extern void RTC_C_definePrescaleEvent(uint_fast8_t prescaleSelect, - uint_fast8_t prescaleEventDivider); - -//***************************************************************************** -// -//! Returns the selected Prescaler value. -//! -//! \param prescaleSelect is the prescaler to obtain the value of. -//! Valid values are -//! - \b RTC_C_PRESCALE_0 -//! - \b RTC_C_PRESCALE_1 -//! -//! This function returns the value of the selected prescale counter register. -//! The counter should be held before reading. If in counter mode, the -//! individual prescaler can be held, while in Calendar mode the whole RTC must -//! be held. -//! -//! \return The value of the specified Prescaler count register -// -//***************************************************************************** -extern uint_fast8_t RTC_C_getPrescaleValue(uint_fast8_t prescaleSelect); - -//***************************************************************************** -// -//! Sets the selected Prescaler value. -//! -//! \param prescaleSelect is the prescaler to set the value for. -//! Valid values are -//! - \b RTC_C_PRESCALE_0 -//! - \b RTC_C_PRESCALE_1 -//! \param prescaleCounterValue is the specified value to set the prescaler to; -//! a valid value is any integer from 0-255. -//! -//! This function sets the prescale counter value. Before setting the prescale -//! counter, it should be held. -//! -//! \return None -// -//***************************************************************************** -extern void RTC_C_setPrescaleValue(uint_fast8_t prescaleSelect, - uint_fast8_t prescaleCounterValue); - -//***************************************************************************** -// -//! Returns the given BCD value in Binary Format -//! -//! \param valueToConvert is the raw value in BCD format to convert to -//! Binary. -//! -//! This function converts BCD values to Binary format. -//! -//! \return The Binary version of the valueToConvert parameter. -// -//***************************************************************************** -extern uint16_t RTC_C_convertBCDToBinary(uint16_t valueToConvert); - -//***************************************************************************** -// -//! Returns the given Binary value in BCD Format -//! - -//! \param valueToConvert is the raw value in Binary format to convert to -//! BCD. -//! -//! This function converts Binary values to BCD format. -//! -//! \return The BCD version of the valueToConvert parameter. -// -//***************************************************************************** -extern uint16_t RTC_C_convertBinaryToBCD(uint16_t valueToConvert); - -//***************************************************************************** -// -//! Enables selected RTC interrupt sources. -//! -//! \param interruptMask is a bit mask of the interrupts to enable. -//! Mask Value is the logical OR of any of the following -//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in -//! counter mode or when Calendar event condition defined by -//! setCalendarEvent() is met. -//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in -//! Calendar mode is met. -//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar -//! registers are settled. -//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 -//! event condition is met. -//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 -//! event condition is met. -//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is -//! a problem with the 32kHz oscillator, while the RTC is running. -//! -//! This function enables the selected RTC interrupt source. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. -//! -//! \return None -// -//***************************************************************************** -extern void RTC_C_enableInterrupt(uint8_t interruptMask); - -//***************************************************************************** -// -//! Disables selected RTC interrupt sources. -//! -//! \param interruptMask is a bit mask of the interrupts to disable. -//! Mask Value is the logical OR of any of the following -//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in -//! counter mode or when Calendar event condition defined by -//! setCalendarEvent() is met. -//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in -//! Calendar mode is met. -//! - \b RTC_CLOCK_READ_READY_INTERRUPT - asserts when Calendar -//! registers are settled. -//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 -//! event condition is met. -//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 -//! event condition is met. -//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a -//! problem with the 32kHz oscillator, while the RTC is running. -//! -//! This function disables the selected RTC interrupt source. Only the sources -//! that are enabled can be reflected to the processor interrupt; disabled -//! sources have no effect on the processor. -//! -//! \return None -// -//***************************************************************************** -extern void RTC_C_disableInterrupt(uint8_t interruptMask); - -//***************************************************************************** -// -//! Returns the status of the interrupts flags. -//! -//! \return A bit mask of the selected interrupt flag's status. -//! Mask Value is the logical OR of any of the following -//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in -//! counter mode or when Calendar event condition defined by -//! setCalendarEvent() is met. -//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in -//! Calendar mode is met. -//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar -//! registers are settled. -//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 -//! event condition is met. -//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 -//! event condition is met. -//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a -//! problem with the 32kHz oscillator, while the RTC is running. -// -//***************************************************************************** -extern uint_fast8_t RTC_C_getInterruptStatus(void); - -//***************************************************************************** -// -//! Returns the status of the interrupts flags masked with the enabled -//! interrupts. This function is useful to call in ISRs to get a -//! list of pending interrupts that are actually enabled and could have caused -//! the ISR. -//! -//! \return A bit mask of the selected interrupt flag's status. -//! Mask Value is the logical OR of any of the following -//! - \b RTC_TIME_EVENT_INTERRUPT - asserts when counter overflows in -//! counter mode or when Calendar event condition defined by -//! setCalendarEvent() is met. -//! - \b RTC_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in -//! Calendar mode is met. -//! - \b RTC_CLOCK_READ_READY_INTERRUPT - asserts when Calendar -//! registers are settled. -//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 -//! event condition is met. -//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 -//! event condition is met. -//! - \b RTC_OSCILLATOR_FAULT_INTERRUPT - asserts if there is a problem -//! with the 32kHz oscillator, while the RTC is running. -// -//***************************************************************************** -extern uint_fast8_t RTC_C_getEnabledInterruptStatus(void); - -//***************************************************************************** -// -//! Clears selected RTC interrupt flags. -//! -//! \param interruptFlagMask is a bit mask of the interrupt flags to be -//! cleared. Mask Value is the logical OR of any of the following -//! - \b RTC_C_TIME_EVENT_INTERRUPT - asserts when counter overflows in -//! counter mode or when Calendar event condition defined by -//! setCalendarEvent() is met. -//! - \b RTC_C_CLOCK_ALARM_INTERRUPT - asserts when alarm condition in -//! Calendar mode is met. -//! - \b RTC_C_CLOCK_READ_READY_INTERRUPT - asserts when Calendar -//! registers are settled. -//! - \b RTC_C_PRESCALE_TIMER0_INTERRUPT - asserts when Prescaler 0 -//! event condition is met. -//! - \b RTC_C_PRESCALE_TIMER1_INTERRUPT - asserts when Prescaler 1 -//! event condition is met. -//! - \b RTC_C_OSCILLATOR_FAULT_INTERRUPT - asserts if there is -//! a problem with the 32kHz oscillator, while the RTC is running. -//! -//! This function clears the RTC interrupt flag is cleared, so that it no longer -//! asserts. -//! -//! \return None -// -//***************************************************************************** -extern void RTC_C_clearInterruptFlag(uint_fast8_t interruptFlagMask); - -//***************************************************************************** -// -//! Registers an interrupt handler for the RTC interrupt. -//! -//! \param intHandler is a pointer to the function to be called when the -//! RTC interrupt occurs. -//! -//! This function registers the handler to be called when a RTC -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific AES interrupts must be enabled -//! via RTC_enableInterrupt(). It is the interrupt handler's responsibility to -//! clear the interrupt source via RTC_clearInterruptFlag(). -//! -//! \return None. -// -//***************************************************************************** -extern void RTC_C_registerInterrupt(void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the RTC interrupt -//! -//! This function unregisters the handler to be called when RTC -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void RTC_C_unregisterInterrupt(void); - -/* Defines for future devices that might have multiple instances */ -#define RTC_C_startClockMultipleInstance(a) RTC_C_startClock() -#define RTC_C_holdClockMultipleInstance(a) RTC_C_holdClock() -#define RTC_C_setCalibrationFrequencyMultipleInstance(a,b) RTC_C_setCalibrationFrequency(b) -#define RTC_C_setCalibrationDataMultipleInstance(a,b,c) RTC_C_setCalibrationData(b,c) -#define RTC_C_setTemperatureCompensationMultipleInstance(a,b,c) RTC_C_setTemperatureCompensation(b,c) -#define RTC_C_initCalendarMultipleInstance(a,b,c) RTC_C_initCalendar(b,c) -#define RTC_C_getCalendarTimeMultipleInstance(a) RTC_C_getCalendarTime() -#define RTC_C_setCalendarAlarmMultipleInstance(a,b,c,d,e) RTC_C_setCalendarAlarm(b,c,d,e) -#define RTC_C_setCalendarEventMultipleInstance(a,b) RTC_C_setCalendarEvent(b) -#define RTC_C_definePrescaleEventMultipleInstance(a,b,c) RTC_C_definePrescaleEvent(b,c) -#define RTC_C_getPrescaleValueMultipleInstance(a,b) RTC_C_getPrescaleValue(b) -#define RTC_C_setPrescaleValueMultipleInstance(a,b,c) RTC_C_setPrescaleValue(b,c) -#define RTC_C_convertBCDToBinaryMultipleInstance(a,b) RTC_C_convertBCDToBinary(b) -#define RTC_C_convertBinaryToBCDMultipleInstance(a,b) RTC_C_convertBinaryToBCD(b) -#define RTC_C_enableInterruptMultipleInstance(a,b) RTC_C_enableInterrupt(b) -#define RTC_C_disableInterruptMultipleInstance(a,b) RTC_C_disableInterrupt(b) -#define RTC_C_getInterruptStatusMultipleInstance(a) RTC_C_getInterruptStatus() -#define RTC_C_getEnabledInterruptStatusMultipleInstance(a) RTC_C_getEnabledInterruptStatus() -#define RTC_C_clearInterruptFlagMultipleInstance(a,b) RTC_C_clearInterruptFlag(b) -#define RTC_C_registerInterruptMultipleInstance(a,b) RTC_C_registerInterrupt(b) -#define RTC_C_unregisterInterruptMultipleInstance(a) RTC_C_unregisterInterrupt() - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* RTC_H */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/spi.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/spi.c deleted file mode 100644 index 53d2381014d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/spi.c +++ /dev/null @@ -1,1359 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include -#include - -static bool is_A_Module(uint32_t module) -{ - if (module == EUSCI_A0_BASE || module == EUSCI_A1_BASE -#ifdef EUSCI_A2_BASE - || module == EUSCI_A2_BASE -#endif -#ifdef EUSCI_A3_BASE - || module == EUSCI_A3_BASE -#endif - ) - return true; - else - return false; -} - -bool SPI_initMaster(uint32_t moduleInstance, const eUSCI_SPI_MasterConfig *config) -{ - if (is_A_Module(moduleInstance)) - { - ASSERT( - (EUSCI_A_SPI_CLOCKSOURCE_ACLK == config->selectClockSource) - || (EUSCI_A_SPI_CLOCKSOURCE_SMCLK - == config->selectClockSource)); - - ASSERT( - (EUSCI_A_SPI_MSB_FIRST == config->msbFirst) - || (EUSCI_A_SPI_LSB_FIRST == config->msbFirst)); - - ASSERT( - (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT - == config->clockPhase) - || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT - == config->clockPhase)); - - ASSERT( - (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH - == config->clockPolarity) - || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW - == config->clockPolarity)); - - ASSERT( - (EUSCI_A_SPI_3PIN == config->spiMode) - || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH - == config->spiMode) - || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW - == config->spiMode)); - - //Disable the USCI Module - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; - - /* - * Configure as SPI master mode. - * Clock phase select, polarity, msb - * EUSCI_A_CTLW0_MST = Master mode - * EUSCI_A_CTLW0_SYNC = Synchronous mode - * UCMODE_0 = 3-pin SPI - */ - EUSCI_A_CMSIS(moduleInstance)->CTLW0 = - (EUSCI_A_CMSIS(moduleInstance)->CTLW0 - & ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST - + EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC)) - | (config->selectClockSource + config->msbFirst - + config->clockPhase + config->clockPolarity - + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode); - - EUSCI_A_CMSIS(moduleInstance)->BRW = - (uint16_t) (config->clockSourceFrequency - / config->desiredSpiClock); - - //No modulation - EUSCI_A_CMSIS(moduleInstance)->MCTLW = 0; - - return true; - } else - { - ASSERT( - (EUSCI_B_SPI_CLOCKSOURCE_ACLK == config->selectClockSource) - || (EUSCI_B_SPI_CLOCKSOURCE_SMCLK - == config->selectClockSource)); - - ASSERT( - (EUSCI_B_SPI_MSB_FIRST == config->msbFirst) - || (EUSCI_B_SPI_LSB_FIRST == config->msbFirst)); - - ASSERT( - (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT - == config->clockPhase) - || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT - == config->clockPhase)); - - ASSERT( - (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH - == config->clockPolarity) - || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW - == config->clockPolarity)); - - ASSERT( - (EUSCI_B_SPI_3PIN == config->spiMode) - || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH - == config->spiMode) - || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW - == config->spiMode)); - - //Disable the USCI Module - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; - - /* - * Configure as SPI master mode. - * Clock phase select, polarity, msb - * EUSCI_A_CTLW0_MST = Master mode - * EUSCI_A_CTLW0_SYNC = Synchronous mode - * UCMODE_0 = 3-pin SPI - */ - EUSCI_B_CMSIS(moduleInstance)->CTLW0 = - (EUSCI_B_CMSIS(moduleInstance)->CTLW0 - & ~(EUSCI_A_CTLW0_SSEL_MASK + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_MST - + EUSCI_A_CTLW0_MODE_3 + EUSCI_A_CTLW0_SYNC)) - | (config->selectClockSource + config->msbFirst - + config->clockPhase + config->clockPolarity - + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_SYNC + config->spiMode); - - EUSCI_B_CMSIS(moduleInstance)->BRW = - (uint16_t) (config->clockSourceFrequency - / config->desiredSpiClock); - - return true; - } - -} - -void SPI_selectFourPinFunctionality(uint32_t moduleInstance, - uint_fast8_t select4PinFunctionality) -{ - if (is_A_Module(moduleInstance)) - { - EUSCI_A_SPI_select4PinFunctionality(moduleInstance, - select4PinFunctionality); - } else - { - EUSCI_B_SPI_select4PinFunctionality(moduleInstance, - select4PinFunctionality); - } - -} - -void SPI_changeMasterClock(uint32_t moduleInstance, - uint32_t clockSourceFrequency, uint32_t desiredSpiClock) -{ - if (is_A_Module(moduleInstance)) - { - EUSCI_A_SPI_masterChangeClock(moduleInstance, clockSourceFrequency, - desiredSpiClock); - } else - { - EUSCI_B_SPI_masterChangeClock(moduleInstance, clockSourceFrequency, - desiredSpiClock); - } - -} - -bool SPI_initSlave(uint32_t moduleInstance, const eUSCI_SPI_SlaveConfig *config) -{ - if (is_A_Module(moduleInstance)) - { - ASSERT( - (EUSCI_A_SPI_MSB_FIRST == config->msbFirst) - || (EUSCI_A_SPI_LSB_FIRST == config->msbFirst)); - - ASSERT( - (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT - == config->clockPhase) - || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT - == config->clockPhase)); - - ASSERT( - (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH - == config->clockPolarity) - || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW - == config->clockPolarity)); - - ASSERT( - (EUSCI_A_SPI_3PIN == config->spiMode) - || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH - == config->spiMode) - || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW - == config->spiMode)); - - //Disable USCI Module - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; - - //Reset OFS_UCAxCTLW0 register - EUSCI_A_CMSIS(moduleInstance)->CTLW0 = - (EUSCI_A_CMSIS(moduleInstance)->CTLW0 - & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3)) - | (config->clockPhase + config->clockPolarity - + config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode); - - return true; - } else - { - ASSERT( - (EUSCI_B_SPI_MSB_FIRST == config->msbFirst) - || (EUSCI_B_SPI_LSB_FIRST == config->msbFirst)); - - ASSERT( - (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT - == config->clockPhase) - || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT - == config->clockPhase)); - - ASSERT( - (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH - == config->clockPolarity) - || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW - == config->clockPolarity)); - - ASSERT( - (EUSCI_B_SPI_3PIN == config->spiMode) - || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH - == config->spiMode) - || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW - == config->spiMode)); - - //Disable USCI Module - BITBAND_PERI(EUSCI_B_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; - - //Reset OFS_UCBxCTLW0 register - EUSCI_B_CMSIS(moduleInstance)->CTLW0 = - (EUSCI_B_CMSIS(moduleInstance)->CTLW0 - & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3)) - | (config->clockPhase + config->clockPolarity - + config->msbFirst + EUSCI_A_CTLW0_SYNC + config->spiMode); - - return true; - } - -} - -void SPI_changeClockPhasePolarity(uint32_t moduleInstance, - uint_fast16_t clockPhase, uint_fast16_t clockPolarity) -{ - if (is_A_Module(moduleInstance)) - { - EUSCI_A_SPI_changeClockPhasePolarity(moduleInstance, clockPhase, - clockPolarity); - } else - { - EUSCI_B_SPI_changeClockPhasePolarity(moduleInstance, clockPhase, - clockPolarity); - } - -} - -void SPI_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData) -{ - if (is_A_Module(moduleInstance)) - { - EUSCI_A_SPI_transmitData(moduleInstance, transmitData); - } else - { - EUSCI_B_SPI_transmitData(moduleInstance, transmitData); - } - -} - -uint8_t SPI_receiveData(uint32_t moduleInstance) -{ - if (is_A_Module(moduleInstance)) - { - return EUSCI_A_SPI_receiveData(moduleInstance); - } else - { - return EUSCI_B_SPI_receiveData(moduleInstance); - } - -} - -void SPI_enableModule(uint32_t moduleInstance) -{ - if (is_A_Module(moduleInstance)) - { - EUSCI_A_SPI_enable(moduleInstance); - } else - { - EUSCI_B_SPI_enable(moduleInstance); - } - -} - -void SPI_disableModule(uint32_t moduleInstance) -{ - if (is_A_Module(moduleInstance)) - { - EUSCI_A_SPI_disable(moduleInstance); - } else - { - EUSCI_B_SPI_disable(moduleInstance); - } - -} - -uint32_t SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance) -{ - if (is_A_Module(moduleInstance)) - { - return EUSCI_A_SPI_getReceiveBufferAddressForDMA(moduleInstance); - } else - { - return EUSCI_B_SPI_getReceiveBufferAddressForDMA(moduleInstance); - } - -} - -uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance) -{ - if (is_A_Module(moduleInstance)) - { - return EUSCI_A_SPI_getTransmitBufferAddressForDMA(moduleInstance); - } else - { - return EUSCI_B_SPI_getTransmitBufferAddressForDMA(moduleInstance); - } - -} - -uint_fast8_t SPI_isBusy(uint32_t moduleInstance) -{ - if (is_A_Module(moduleInstance)) - { - return EUSCI_A_SPI_isBusy(moduleInstance); - } else - { - return EUSCI_B_SPI_isBusy(moduleInstance); - } - -} - -void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask) -{ - if (is_A_Module(moduleInstance)) - { - EUSCI_A_SPI_enableInterrupt(moduleInstance, mask); - } else - { - EUSCI_B_SPI_enableInterrupt(moduleInstance, mask); - } - -} - -void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask) -{ - if (is_A_Module(moduleInstance)) - { - EUSCI_A_SPI_disableInterrupt(moduleInstance, mask); - } else - { - EUSCI_B_SPI_disableInterrupt(moduleInstance, mask); - } - -} - -uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance, uint16_t mask) -{ - if (is_A_Module(moduleInstance)) - { - return EUSCI_A_SPI_getInterruptStatus(moduleInstance, mask); - } else - { - return EUSCI_B_SPI_getInterruptStatus(moduleInstance, mask); - } - -} - -uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance) -{ - if (is_A_Module(moduleInstance)) - { - return SPI_getInterruptStatus(moduleInstance, - EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT) - & EUSCI_A_CMSIS(moduleInstance)->IE; - - } else - { - return SPI_getInterruptStatus(moduleInstance, - EUSCI_SPI_TRANSMIT_INTERRUPT | EUSCI_SPI_RECEIVE_INTERRUPT) - & EUSCI_B_CMSIS(moduleInstance)->IE; - - } -} - -void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask) -{ - if (is_A_Module(moduleInstance)) - { - EUSCI_A_SPI_clearInterruptFlag(moduleInstance, mask); - } else - { - EUSCI_B_SPI_clearInterruptFlag(moduleInstance, mask); - } - -} - -void SPI_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void)) -{ - switch (moduleInstance) - { - case EUSCI_A0_BASE: - Interrupt_registerInterrupt(INT_EUSCIA0, intHandler); - Interrupt_enableInterrupt(INT_EUSCIA0); - break; - case EUSCI_A1_BASE: - Interrupt_registerInterrupt(INT_EUSCIA1, intHandler); - Interrupt_enableInterrupt(INT_EUSCIA1); - break; -#ifdef EUSCI_A2_BASE - case EUSCI_A2_BASE: - Interrupt_registerInterrupt(INT_EUSCIA2, intHandler); - Interrupt_enableInterrupt(INT_EUSCIA2); - break; -#endif -#ifdef EUSCI_A3_BASE - case EUSCI_A3_BASE: - Interrupt_registerInterrupt(INT_EUSCIA3, intHandler); - Interrupt_enableInterrupt(INT_EUSCIA3); - break; -#endif - case EUSCI_B0_BASE: - Interrupt_registerInterrupt(INT_EUSCIB0, intHandler); - Interrupt_enableInterrupt(INT_EUSCIB0); - break; - case EUSCI_B1_BASE: - Interrupt_registerInterrupt(INT_EUSCIB1, intHandler); - Interrupt_enableInterrupt(INT_EUSCIB1); - break; -#ifdef EUSCI_B2_BASE - case EUSCI_B2_BASE: - Interrupt_registerInterrupt(INT_EUSCIB2, intHandler); - Interrupt_enableInterrupt(INT_EUSCIB2); - break; -#endif -#ifdef EUSCI_B3_BASE - case EUSCI_B3_BASE: - Interrupt_registerInterrupt(INT_EUSCIB3, intHandler); - Interrupt_enableInterrupt(INT_EUSCIB3); - break; -#endif - default: - ASSERT(false); - } -} - -void SPI_unregisterInterrupt(uint32_t moduleInstance) -{ - switch (moduleInstance) - { - case EUSCI_A0_BASE: - Interrupt_disableInterrupt(INT_EUSCIA0); - Interrupt_unregisterInterrupt(INT_EUSCIA0); - break; - case EUSCI_A1_BASE: - Interrupt_disableInterrupt(INT_EUSCIA1); - Interrupt_unregisterInterrupt(INT_EUSCIA1); - break; -#ifdef EUSCI_A2_BASE - case EUSCI_A2_BASE: - Interrupt_disableInterrupt(INT_EUSCIA2); - Interrupt_unregisterInterrupt(INT_EUSCIA2); - break; -#endif -#ifdef EUSCI_A3_BASE - case EUSCI_A3_BASE: - Interrupt_disableInterrupt(INT_EUSCIA3); - Interrupt_unregisterInterrupt(INT_EUSCIA3); - break; -#endif - case EUSCI_B0_BASE: - Interrupt_disableInterrupt(INT_EUSCIB0); - Interrupt_unregisterInterrupt(INT_EUSCIB0); - break; - case EUSCI_B1_BASE: - Interrupt_disableInterrupt(INT_EUSCIB1); - Interrupt_unregisterInterrupt(INT_EUSCIB1); - break; -#ifdef EUSCI_B2_BASE - case EUSCI_B2_BASE: - Interrupt_disableInterrupt(INT_EUSCIB2); - Interrupt_unregisterInterrupt(INT_EUSCIB2); - break; -#endif -#ifdef EUSCI_B3_BASE - case EUSCI_B3_BASE: - Interrupt_disableInterrupt(INT_EUSCIB3); - Interrupt_unregisterInterrupt(INT_EUSCIB3); - break; -#endif - default: - ASSERT(false); - } - -} - -/* Backwards Compatibility Layer */ - -//***************************************************************************** -// -//! \brief Selects 4Pin Functionality -//! -//! This function should be invoked only in 4-wire mode. Invoking this function -//! has no effect in 3-wire mode. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! \param select4PinFunctionality selects 4 pin functionality -//! Valid values are: -//! - \b EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS -//! - \b EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE -//! -//! Modified bits are \b UCSTEM of \b UCAxCTLW0 register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress, - uint8_t select4PinFunctionality) -{ - ASSERT( - (EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS - == select4PinFunctionality) - || (EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE - == select4PinFunctionality)); - - EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0 - & ~EUSCI_B_CTLW0_STEM) | select4PinFunctionality; -} - -//***************************************************************************** -// -//! \brief Initializes the SPI Master clock. At the end of this function call, -//! SPI module is left enabled. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! \param clockSourceFrequency is the frequency of the slected clock source -//! \param desiredSpiClock is the desired clock rate for SPI communication -//! -//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress, - uint32_t clockSourceFrequency, uint32_t desiredSpiClock) -{ - //Disable the USCI Module - BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; - - EUSCI_B_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency - / desiredSpiClock); - - //Reset the UCSWRST bit to enable the USCI Module - BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; -} - -//***************************************************************************** -// -//! \brief Initializes the SPI Slave block. -//! -//! Upon successful initialization of the SPI slave block, this function will -//! have initailized the slave block, but the SPI Slave block still remains -//! disabled and must be enabled with EUSCI_B_SPI_enable() -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI Slave module. -//! \param msbFirst controls the direction of the receive and transmit shift -//! register. -//! Valid values are: -//! - \b EUSCI_B_SPI_MSB_FIRST -//! - \b EUSCI_B_SPI_LSB_FIRST [Default] -//! \param clockPhase is clock phase select. -//! Valid values are: -//! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT -//! [Default] -//! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT -//! \param clockPolarity is clock polarity select -//! Valid values are: -//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH -//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] -//! \param spiMode is SPI mode select -//! Valid values are: -//! - \b EUSCI_B_SPI_3PIN -//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH -//! - \b EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW -//! -//! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b -//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register. -//! -//! \return true -// -//***************************************************************************** -bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst, - uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode) -{ - ASSERT( - (EUSCI_B_SPI_MSB_FIRST == msbFirst) - || (EUSCI_B_SPI_LSB_FIRST == msbFirst)); - - ASSERT( - (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT - == clockPhase) - || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT - == clockPhase)); - - ASSERT( - (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) - || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW - == clockPolarity)); - - ASSERT( - (EUSCI_B_SPI_3PIN == spiMode) - || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode) - || (EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode)); - - //Disable USCI Module - BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; - - //Reset OFS_UCBxCTLW0 register - EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0 - & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3)) - | (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode); - - return true; -} - -//***************************************************************************** -// -//! \brief Changes the SPI colock phase and polarity. At the end of this -//! function call, SPI module is left enabled. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! \param clockPhase is clock phase select. -//! Valid values are: -//! - \b EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT -//! [Default] -//! - \b EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT -//! \param clockPolarity is clock polarity select -//! Valid values are: -//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH -//! - \b EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] -//! -//! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0 -//! register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress, - uint16_t clockPhase, uint16_t clockPolarity) -{ - - ASSERT( - (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) - || (EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW - == clockPolarity)); - - ASSERT( - (EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT - == clockPhase) - || (EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT - == clockPhase)); - - //Disable the USCI Module - BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; - - EUSCI_B_CMSIS(baseAddress)->CTLW0 = (EUSCI_B_CMSIS(baseAddress)->CTLW0 - & ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity); - - //Reset the UCSWRST bit to enable the USCI Module - BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; -} - -//***************************************************************************** -// -//! \brief Transmits a byte from the SPI Module. -//! -//! This function will place the supplied data into SPI trasmit data register -//! to start transmission. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! \param transmitData data to be transmitted from the SPI module -//! -//! \return None -// -//***************************************************************************** -void EUSCI_B_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData) -{ - EUSCI_B_CMSIS(baseAddress)->TXBUF = transmitData; -} - -//***************************************************************************** -// -//! \brief Receives a byte that has been sent to the SPI Module. -//! -//! This function reads a byte of data from the SPI receive data Register. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! -//! \return Returns the byte received from by the SPI module, cast as an -//! uint8_t. -// -//***************************************************************************** -uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress) -{ - return EUSCI_B_CMSIS(baseAddress)->RXBUF; -} - -//***************************************************************************** -// -//! \brief Enables individual SPI interrupt sources. -//! -//! Enables the indicated SPI interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. Does not clear interrupt flags. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! \param mask is the bit mask of the interrupt sources to be enabled. -//! Mask value is the logical OR of any of the following: -//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT -//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT -//! -//! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask) -{ - ASSERT( - !(mask - & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT - | EUSCI_B_SPI_TRANSMIT_INTERRUPT))); - - EUSCI_B_CMSIS(baseAddress)->IE |= mask; -} - -//***************************************************************************** -// -//! \brief Disables individual SPI interrupt sources. -//! -//! Disables the indicated SPI interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! \param mask is the bit mask of the interrupt sources to be disabled. -//! Mask value is the logical OR of any of the following: -//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT -//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT -//! -//! Modified bits of \b UCAxIE register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask) -{ - ASSERT( - !(mask - & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT - | EUSCI_B_SPI_TRANSMIT_INTERRUPT))); - - EUSCI_B_CMSIS(baseAddress)->IE &= ~mask; -} - -//***************************************************************************** -// -//! \brief Gets the current SPI interrupt status. -//! -//! This returns the interrupt status for the SPI module based on which flag is -//! passed. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! \param mask is the masked interrupt flag status to be returned. -//! Mask value is the logical OR of any of the following: -//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT -//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT -//! -//! \return Logical OR of any of the following: -//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT -//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT -//! \n indicating the status of the masked interrupts -// -//***************************************************************************** -uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask) -{ - ASSERT( - !(mask - & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT - | EUSCI_B_SPI_TRANSMIT_INTERRUPT))); - - return EUSCI_B_CMSIS(baseAddress)->IFG & mask; -} - -//***************************************************************************** -// -//! \brief Clears the selected SPI interrupt status flag. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! \param mask is the masked interrupt flag to be cleared. -//! Mask value is the logical OR of any of the following: -//! - \b EUSCI_B_SPI_TRANSMIT_INTERRUPT -//! - \b EUSCI_B_SPI_RECEIVE_INTERRUPT -//! -//! Modified bits of \b UCAxIFG register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask) -{ - ASSERT( - !(mask - & ~(EUSCI_B_SPI_RECEIVE_INTERRUPT - | EUSCI_B_SPI_TRANSMIT_INTERRUPT))); - - EUSCI_B_CMSIS(baseAddress)->IFG &= ~mask; -} - -//***************************************************************************** -// -//! \brief Enables the SPI block. -//! -//! This will enable operation of the SPI block. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! -//! Modified bits are \b UCSWRST of \b UCBxCTLW0 register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_B_SPI_enable(uint32_t baseAddress) -{ - //Reset the UCSWRST bit to enable the USCI Module - BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; -} - -//***************************************************************************** -// -//! \brief Disables the SPI block. -//! -//! This will disable operation of the SPI block. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! -//! Modified bits are \b UCSWRST of \b UCBxCTLW0 register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_B_SPI_disable(uint32_t baseAddress) -{ - //Set the UCSWRST bit to disable the USCI Module - BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; -} - -//***************************************************************************** -// -//! \brief Returns the address of the RX Buffer of the SPI for the DMA module. -//! -//! Returns the address of the SPI RX Buffer. This can be used in conjunction -//! with the DMA to store the received data directly to memory. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! -//! \return the address of the RX Buffer -// -//***************************************************************************** -uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress) -{ - return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->RXBUF)); -} - -//***************************************************************************** -// -//! \brief Returns the address of the TX Buffer of the SPI for the DMA module. -//! -//! Returns the address of the SPI TX Buffer. This can be used in conjunction -//! with the DMA to obtain transmitted data directly from memory. -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! -//! \return the address of the TX Buffer -// -//***************************************************************************** -uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress) -{ - return ((uint32_t)(&EUSCI_B_CMSIS(baseAddress)->TXBUF)); -} - -//***************************************************************************** -// -//! \brief Indicates whether or not the SPI bus is busy. -//! -//! This function returns an indication of whether or not the SPI bus is -//! busy.This function checks the status of the bus via UCBBUSY bit -//! -//! \param baseAddress is the base address of the EUSCI_B_SPI module. -//! -//! \return true if busy, false otherwise -// -//***************************************************************************** -bool EUSCI_B_SPI_isBusy(uint32_t baseAddress) -{ - //Return the bus busy status. - return BITBAND_PERI(EUSCI_B_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS); -} - -//***************************************************************************** -// -//! \brief Selects 4Pin Functionality -//! -//! This function should be invoked only in 4-wire mode. Invoking this function -//! has no effect in 3-wire mode. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! \param select4PinFunctionality selects 4 pin functionality -//! Valid values are: -//! - \b EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS -//! - \b EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE -//! -//! Modified bits are \b UCSTEM of \b UCAxCTLW0 register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress, - uint8_t select4PinFunctionality) -{ - ASSERT( - (EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS - == select4PinFunctionality) - || (EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE - == select4PinFunctionality)); - - EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0 - & ~EUSCI_A_CTLW0_STEM) | select4PinFunctionality; -} - -//***************************************************************************** -// -//! \brief Initializes the SPI Master clock. At the end of this function call, -//! SPI module is left enabled. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! \param clockSourceFrequency is the frequency of the slected clock source -//! \param desiredSpiClock is the desired clock rate for SPI communication -//! -//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress, - uint32_t clockSourceFrequency, uint32_t desiredSpiClock) -{ - //Disable the USCI Module - BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; - - EUSCI_A_CMSIS(baseAddress)->BRW = (uint16_t) (clockSourceFrequency - / desiredSpiClock); - - //Reset the UCSWRST bit to enable the USCI Module - BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; -} - -//***************************************************************************** -// -//! \brief Initializes the SPI Slave block. -//! -//! Upon successful initialization of the SPI slave block, this function will -//! have initailized the slave block, but the SPI Slave block still remains -//! disabled and must be enabled with EUSCI_A_SPI_enable() -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI Slave module. -//! \param msbFirst controls the direction of the receive and transmit shift -//! register. -//! Valid values are: -//! - \b EUSCI_A_SPI_MSB_FIRST -//! - \b EUSCI_A_SPI_LSB_FIRST [Default] -//! \param clockPhase is clock phase select. -//! Valid values are: -//! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT -//! [Default] -//! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT -//! \param clockPolarity is clock polarity select -//! Valid values are: -//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH -//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] -//! \param spiMode is SPI mode select -//! Valid values are: -//! - \b EUSCI_A_SPI_3PIN -//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH -//! - \b EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW -//! -//! Modified bits are \b EUSCI_A_CTLW0_MSB, \b EUSCI_A_CTLW0_MST, \b EUSCI_A_CTLW0_SEVENBIT, \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH, \b -//! UCMODE and \b UCSWRST of \b UCAxCTLW0 register. -//! -//! \return true -// -//***************************************************************************** -bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst, - uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode) -{ - ASSERT( - (EUSCI_A_SPI_MSB_FIRST == msbFirst) - || (EUSCI_A_SPI_LSB_FIRST == msbFirst)); - - ASSERT( - (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT - == clockPhase) - || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT - == clockPhase)); - - ASSERT( - (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) - || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW - == clockPolarity)); - - ASSERT( - (EUSCI_A_SPI_3PIN == spiMode) - || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH == spiMode) - || (EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW == spiMode)); - - //Disable USCI Module - BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; - - //Reset OFS_UCAxCTLW0 register - EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0 - & ~(EUSCI_A_CTLW0_MSB + EUSCI_A_CTLW0_SEVENBIT + EUSCI_A_CTLW0_MST + EUSCI_A_CTLW0_CKPL + EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_MODE_3)) - | (clockPhase + clockPolarity + msbFirst + EUSCI_A_CTLW0_SYNC + spiMode); - - return true; -} - -//***************************************************************************** -// -//! \brief Changes the SPI colock phase and polarity. At the end of this -//! function call, SPI module is left enabled. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! \param clockPhase is clock phase select. -//! Valid values are: -//! - \b EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT -//! [Default] -//! - \b EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT -//! \param clockPolarity is clock polarity select -//! Valid values are: -//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH -//! - \b EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default] -//! -//! Modified bits are \b EUSCI_A_CTLW0_CKPL, \b EUSCI_A_CTLW0_CKPH and \b UCSWRST of \b UCAxCTLW0 -//! register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress, - uint16_t clockPhase, uint16_t clockPolarity) -{ - - ASSERT( - (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH == clockPolarity) - || (EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW - == clockPolarity)); - - ASSERT( - (EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT - == clockPhase) - || (EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT - == clockPhase)); - - //Disable the USCI Module - BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; - - EUSCI_A_CMSIS(baseAddress)->CTLW0 = (EUSCI_A_CMSIS(baseAddress)->CTLW0 - & ~(EUSCI_A_CTLW0_CKPH + EUSCI_A_CTLW0_CKPL)) | (clockPhase + clockPolarity); - - //Reset the UCSWRST bit to enable the USCI Module - BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; -} - -//***************************************************************************** -// -//! \brief Transmits a byte from the SPI Module. -//! -//! This function will place the supplied data into SPI trasmit data register -//! to start transmission. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! \param transmitData data to be transmitted from the SPI module -//! -//! \return None -// -//***************************************************************************** -void EUSCI_A_SPI_transmitData(uint32_t baseAddress, uint8_t transmitData) -{ - EUSCI_A_CMSIS(baseAddress)->TXBUF = transmitData; -} - -//***************************************************************************** -// -//! \brief Receives a byte that has been sent to the SPI Module. -//! -//! This function reads a byte of data from the SPI receive data Register. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! -//! \return Returns the byte received from by the SPI module, cast as an -//! uint8_t. -// -//***************************************************************************** -uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress) -{ - return EUSCI_A_CMSIS(baseAddress)->RXBUF; -} - -//***************************************************************************** -// -//! \brief Enables individual SPI interrupt sources. -//! -//! Enables the indicated SPI interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. Does not clear interrupt flags. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! \param mask is the bit mask of the interrupt sources to be enabled. -//! Mask value is the logical OR of any of the following: -//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT -//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT -//! -//! Modified bits of \b UCAxIFG register and bits of \b UCAxIE register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask) -{ - ASSERT( - !(mask - & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT - | EUSCI_A_SPI_TRANSMIT_INTERRUPT))); - - EUSCI_A_CMSIS(baseAddress)->IE |= mask; -} - -//***************************************************************************** -// -//! \brief Disables individual SPI interrupt sources. -//! -//! Disables the indicated SPI interrupt sources. Only the sources that are -//! enabled can be reflected to the processor interrupt; disabled sources have -//! no effect on the processor. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! \param mask is the bit mask of the interrupt sources to be disabled. -//! Mask value is the logical OR of any of the following: -//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT -//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT -//! -//! Modified bits of \b UCAxIE register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask) -{ - ASSERT( - !(mask - & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT - | EUSCI_A_SPI_TRANSMIT_INTERRUPT))); - - EUSCI_A_CMSIS(baseAddress)->IE &= ~mask; -} - -//***************************************************************************** -// -//! \brief Gets the current SPI interrupt status. -//! -//! This returns the interrupt status for the SPI module based on which flag is -//! passed. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! \param mask is the masked interrupt flag status to be returned. -//! Mask value is the logical OR of any of the following: -//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT -//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT -//! -//! \return Logical OR of any of the following: -//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT -//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT -//! \n indicating the status of the masked interrupts -// -//***************************************************************************** -uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress, uint8_t mask) -{ - ASSERT( - !(mask - & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT - | EUSCI_A_SPI_TRANSMIT_INTERRUPT))); - - return EUSCI_A_CMSIS(baseAddress)->IFG & mask; -} - -//***************************************************************************** -// -//! \brief Clears the selected SPI interrupt status flag. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! \param mask is the masked interrupt flag to be cleared. -//! Mask value is the logical OR of any of the following: -//! - \b EUSCI_A_SPI_TRANSMIT_INTERRUPT -//! - \b EUSCI_A_SPI_RECEIVE_INTERRUPT -//! -//! Modified bits of \b UCAxIFG register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask) -{ - ASSERT( - !(mask - & ~(EUSCI_A_SPI_RECEIVE_INTERRUPT - | EUSCI_A_SPI_TRANSMIT_INTERRUPT))); - - EUSCI_A_CMSIS(baseAddress)->IFG &= ~mask; -} - -//***************************************************************************** -// -//! \brief Enables the SPI block. -//! -//! This will enable operation of the SPI block. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! -//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_A_SPI_enable(uint32_t baseAddress) -{ - //Reset the UCSWRST bit to enable the USCI Module - BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; -} - -//***************************************************************************** -// -//! \brief Disables the SPI block. -//! -//! This will disable operation of the SPI block. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! -//! Modified bits are \b UCSWRST of \b UCAxCTLW0 register. -//! -//! \return None -// -//***************************************************************************** -void EUSCI_A_SPI_disable(uint32_t baseAddress) -{ - //Set the UCSWRST bit to disable the USCI Module - BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; -} - -//***************************************************************************** -// -//! \brief Returns the address of the RX Buffer of the SPI for the DMA module. -//! -//! Returns the address of the SPI RX Buffer. This can be used in conjunction -//! with the DMA to store the received data directly to memory. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! -//! \return the address of the RX Buffer -// -//***************************************************************************** -uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress) -{ - return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->RXBUF; -} - -//***************************************************************************** -// -//! \brief Returns the address of the TX Buffer of the SPI for the DMA module. -//! -//! Returns the address of the SPI TX Buffer. This can be used in conjunction -//! with the DMA to obtain transmitted data directly from memory. -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! -//! \return the address of the TX Buffer -// -//***************************************************************************** -uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA(uint32_t baseAddress) -{ - return (uint32_t)&EUSCI_A_CMSIS(baseAddress)->TXBUF; -} - -//***************************************************************************** -// -//! \brief Indicates whether or not the SPI bus is busy. -//! -//! This function returns an indication of whether or not the SPI bus is -//! busy.This function checks the status of the bus via UCBBUSY bit -//! -//! \param baseAddress is the base address of the EUSCI_A_SPI module. -//! -//! \return true if busy, false otherwise -//***************************************************************************** -bool EUSCI_A_SPI_isBusy(uint32_t baseAddress) -{ - //Return the bus busy status. - return BITBAND_PERI(EUSCI_A_CMSIS(baseAddress)->STATW, EUSCI_B_STATW_BBUSY_OFS); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/spi.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/spi.h deleted file mode 100644 index 46efe00d2f2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/spi.h +++ /dev/null @@ -1,817 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef SPI_H_ -#define SPI_H_ - -//***************************************************************************** -// -//! \addtogroup spi_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include -#include -#include - -/* Configuration Defines */ -#define EUSCI_SPI_CLOCKSOURCE_ACLK EUSCI_B_CTLW0_SSEL__ACLK -#define EUSCI_SPI_CLOCKSOURCE_SMCLK EUSCI_B_CTLW0_SSEL__SMCLK - -#define EUSCI_SPI_MSB_FIRST EUSCI_B_CTLW0_MSB -#define EUSCI_SPI_LSB_FIRST 0x00 - -#define EUSCI_SPI_BUSY EUSCI_A_STATW_BUSY -#define EUSCI_SPI_NOT_BUSY 0x00 - -#define EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 -#define EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT EUSCI_B_CTLW0_CKPH - -#define EUSCI_SPI_3PIN EUSCI_B_CTLW0_MODE_0 -#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH EUSCI_B_CTLW0_MODE_1 -#define EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW EUSCI_B_CTLW0_MODE_2 - -#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH EUSCI_B_CTLW0_CKPL -#define EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 - -#define EUSCI_SPI_TRANSMIT_INTERRUPT EUSCI_B_IE_TXIE_OFS -#define EUSCI_SPI_RECEIVE_INTERRUPT EUSCI_B_IE_RXIE_OFS - -#define EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE EUSCI_B_CTLW0_STEM -#define EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00 - -//***************************************************************************** -// -//! ypedef eUSCI_SPI_MasterConfig -//! \brief Type definition for \link _eUSCI_SPI_MasterConfig \endlink structure -//! -//! \struct _eUSCI_SPI_MasterConfig -//! \brief Configuration structure for master mode in the \b SPI module. See -//! \link SPI_initMaster \endlink for parameter documentation. -// -//***************************************************************************** -typedef struct _eUSCI_SPI_MasterConfig -{ - uint_fast8_t selectClockSource; - uint32_t clockSourceFrequency; - uint32_t desiredSpiClock; - uint_fast16_t msbFirst; - uint_fast16_t clockPhase; - uint_fast16_t clockPolarity; - uint_fast16_t spiMode; -} eUSCI_SPI_MasterConfig; - -//***************************************************************************** -// -//! ypedef eUSCI_SPI_SlaveConfig -//! \brief Type definition for \link _eUSCI_SPI_SlaveConfig \endlink structure -//! -//! \struct _eUSCI_SPI_SlaveConfig -//! \brief Configuration structure for slave mode in the \b SPI module. See -//! \link SPI_initSlave \endlink for parameter documentation. -// -//***************************************************************************** -typedef struct _eUSCI_SPI_SlaveConfig -{ - uint_fast16_t msbFirst; - uint_fast16_t clockPhase; - uint_fast16_t clockPolarity; - uint_fast16_t spiMode; -} eUSCI_SPI_SlaveConfig; - -//***************************************************************************** -// -//! Initializes the SPI Master block. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! \param config Configuration structure for SPI master mode -//! -//!
-//! Configuration options for \link eUSCI_SPI_MasterConfig \endlink structure. -//!
-//! -//! \param selectClockSource selects clock source. Valid values are -//! - \b EUSCI_SPI_CLOCKSOURCE_ACLK -//! - \b EUSCI_SPI_CLOCKSOURCE_SMCLK -//! \param clockSourceFrequency is the frequency of the selected clock source -//! \param desiredSpiClock is the desired clock rate for SPI communication -//! \param msbFirst controls the direction of the receive and transmit shift -//! register. Valid values are -//! - \b EUSCI_SPI_MSB_FIRST -//! - \b EUSCI_SPI_LSB_FIRST [Default Value] -//! \param clockPhase is clock phase select. -//! Valid values are -//! - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT -//! [Default Value] -//! - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT -//! \param clockPolarity is clock polarity select. -//! Valid values are -//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH -//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default Value] -//! \param spiMode is SPI mode select. -//! Valid values are -//! - \b EUSCI_SPI_3PIN [Default Value] -//! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH -//! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW -//! Upon successful initialization of the SPI master block, this function -//! will have set the bus speed for the master, but the SPI Master block -//! still remains disabled and must be enabled with SPI_enableModule() -//! -//! Modified bits are \b UCCKPH, \b UCCKPL, \b UC7BIT, \b UCMSB,\b UCSSELx, -//! \b UCSWRST bits of \b UCAxCTLW0 register -//! -//! \return true -// -//***************************************************************************** -extern bool SPI_initMaster(uint32_t moduleInstance, - const eUSCI_SPI_MasterConfig *config); - -//***************************************************************************** -// -//! Selects 4Pin Functionality -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! \param select4PinFunctionality selects Clock source. Valid values are -//! - \b EUSCI_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS -//! - \b EUSCI_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE -//! This function should be invoked only in 4-wire mode. Invoking this function -//! has no effect in 3-wire mode. -//! -//! Modified bits are \b UCSTEM bit of \b UCAxCTLW0 register -//! -//! \return true -// -//***************************************************************************** -extern void SPI_selectFourPinFunctionality(uint32_t moduleInstance, - uint_fast8_t select4PinFunctionality); - -//***************************************************************************** -// -//! Initializes the SPI Master clock.At the end of this function call, SPI -//! module is left enabled. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! \param clockSourceFrequency is the frequency of the selected clock source -//! \param desiredSpiClock is the desired clock rate for SPI communication. -//! -//! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register and -//! \b UCAxBRW register -//! -//! \return None -// -//***************************************************************************** -extern void SPI_changeMasterClock(uint32_t moduleInstance, - uint32_t clockSourceFrequency, uint32_t desiredSpiClock); - -//***************************************************************************** -// -//! Initializes the SPI Slave block. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! \param config Configuration structure for SPI slave mode -//! -//!
-//! Configuration options for \link eUSCI_SPI_SlaveConfig \endlink structure. -//!
-//! -//! \param msbFirst controls the direction of the receive and transmit shift -//! register. Valid values are -//! - \b EUSCI_SPI_MSB_FIRST -//! - \b EUSCI_SPI_LSB_FIRST [Default Value] -//! \param clockPhase is clock phase select. -//! Valid values are -//! - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT -//! [Default Value] -//! - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT -//! \param clockPolarity is clock polarity select. -//! Valid values are -//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH -//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default Value] -//! \param spiMode is SPI mode select. -//! Valid values are -//! - \b EUSCI_SPI_3PIN [Default Value] -//! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_HIGH -//! - \b EUSCI_SPI_4PIN_UCxSTE_ACTIVE_LOW -//! Upon successful initialization of the SPI slave block, this function -//! will have initialized the slave block, but the SPI Slave block -//! still remains disabled and must be enabled with SPI_enableModule() -//! -//! Modified bits are \b UCMSB, \b UC7BIT, \b UCMST, \b UCCKPL, \b UCCKPH, -//! \b UCMODE, \b UCSWRST bits of \b UCAxCTLW0 -//! -//! \return true -//***************************************************************************** -extern bool SPI_initSlave(uint32_t moduleInstance, - const eUSCI_SPI_SlaveConfig *config); - -//***************************************************************************** -// -//! Changes the SPI clock phase and polarity.At the end of this function call, -//! SPI module is left enabled. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! \param clockPhase is clock phase select. -//! Valid values are: -//! - \b EUSCI_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT -//! [Default Value] -//! - \b EUSCI_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT -//! \param clockPolarity is clock polarity select. -//! Valid values are: -//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_HIGH -//! - \b EUSCI_SPI_CLOCKPOLARITY_INACTIVITY_LOW [Default Value] -//! -//! Modified bits are \b UCSWRST, \b UCCKPH, \b UCCKPL, \b UCSWRST bits of -//! \b UCAxCTLW0 -//! -//! \return None -// -//***************************************************************************** -extern void SPI_changeClockPhasePolarity(uint32_t moduleInstance, - uint_fast16_t clockPhase, uint_fast16_t clockPolarity); - -//***************************************************************************** -// -//! Transmits a byte from the SPI Module. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! \param transmitData data to be transmitted from the SPI module -//! -//! This function will place the supplied data into SPI transmit data register -//! to start transmission -//! -//! Modified register is \b UCAxTXBUF -//! -//! \return None. -// -//***************************************************************************** -extern void SPI_transmitData(uint32_t moduleInstance, - uint_fast8_t transmitData); - -//***************************************************************************** -// -//! Receives a byte that has been sent to the SPI Module. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! -//! This function reads a byte of data from the SPI receive data Register. -//! -//! \return Returns the byte received from by the SPI module, cast as an -//! uint8_t. -// -//***************************************************************************** -extern uint8_t SPI_receiveData(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Enables the SPI block. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! -//! This will enable operation of the SPI block. -//! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register. -//! -//! \return None. -// -//***************************************************************************** -extern void SPI_enableModule(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Disables the SPI block. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! -//! This will disable operation of the SPI block. -//! -//! Modified bits are \b UCSWRST bit of \b UCAxCTLW0 register. -//! -//! \return None. -// -//***************************************************************************** -extern void SPI_disableModule(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Returns the address of the RX Buffer of the SPI for the DMA module. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! -//! Returns the address of the SPI RX Buffer. This can be used in conjunction -//! with the DMA to store the received data directly to memory. -//! -//! \return NONE -// -//***************************************************************************** -extern uint32_t SPI_getReceiveBufferAddressForDMA(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Returns the address of the TX Buffer of the SPI for the DMA module. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! -//! Returns the address of the SPI TX Buffer. This can be used in conjunction -//! with the DMA to obtain transmitted data directly from memory. -//! -//! \return NONE -// -//***************************************************************************** -extern uint32_t SPI_getTransmitBufferAddressForDMA(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Indicates whether or not the SPI bus is busy. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! -//! This function returns an indication of whether or not the SPI bus is -//! busy.This function checks the status of the bus via UCBBUSY bit -//! -//! \return EUSCI_SPI_BUSY if the SPI module transmitting or receiving -//! is busy; otherwise, returns EUSCI_SPI_NOT_BUSY. -// -//***************************************************************************** -extern uint_fast8_t SPI_isBusy(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Enables individual SPI interrupt sources. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! \param mask is the bit mask of the interrupt sources to be enabled. -//! -//! Enables the indicated SPI interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. -//! -//! The mask parameter is the logical OR of any of the following: -//! - \b EUSCI_SPI_RECEIVE_INTERRUPT Receive interrupt -//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT Transmit interrupt -//! -//! Modified registers are \b UCAxIFG and \b UCAxIE -//! -//! \return None. -// -//***************************************************************************** -extern void SPI_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask); - -//***************************************************************************** -// -//! Disables individual SPI interrupt sources. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! \param mask is the bit mask of the interrupt sources to be -//! disabled. -//! -//! Disables the indicated SPI interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. -//! -//! The mask parameter is the logical OR of any of the following: -//! - \b EUSCI_SPI_RECEIVE_INTERRUPT Receive interrupt -//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT Transmit interrupt -//! -//! Modified register is \b UCAxIE -//! -//! \return None. -// -//***************************************************************************** -extern void SPI_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask); - -//***************************************************************************** -// -//! Gets the current SPI interrupt status. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! \param mask Mask of interrupt to filter. This can include: -//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt -//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt -//! -//! Modified registers are \b UCAxIFG. -//! -//! \return The current interrupt status as the mask of the set flags -//! Mask parameter can be either any of the following selection: -//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt -//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt -// -//***************************************************************************** -extern uint_fast8_t SPI_getInterruptStatus(uint32_t moduleInstance, - uint16_t mask); - -//***************************************************************************** -// -//! Gets the current SPI interrupt status masked with the enabled interrupts. -//! This function is useful to call in ISRs to get a list of pending -//! interrupts that are actually enabled and could have caused -//! the ISR. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! Modified registers are \b UCAxIFG. -//! -//! \return The current interrupt status as the mask of the set flags -//! Mask parameter can be either any of the following selection: -//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt -//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt -// -//***************************************************************************** -extern uint_fast8_t SPI_getEnabledInterruptStatus(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Clears the selected SPI interrupt status flag. -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! \param mask is the masked interrupt flag to be cleared. -//! -//! The mask parameter is the logical OR of any of the following: -//! - \b EUSCI_SPI_RECEIVE_INTERRUPT -Receive interrupt -//! - \b EUSCI_SPI_TRANSMIT_INTERRUPT - Transmit interrupt -//! Modified registers are \b UCAxIFG. -//! -//! \return None -// -//***************************************************************************** -extern void SPI_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask); - -//***************************************************************************** -// -//! Registers an interrupt handler for the timer capture compare interrupt. -//! -//! \param moduleInstance is the instance of the eUSCI (SPI) module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! It is important to note that for eUSCI modules, only "B" modules such as -//! EUSCI_B0 can be used. "A" modules such as EUSCI_A0 do not support the -//! I2C mode. -//! -//! \param intHandler is a pointer to the function to be called when the -//! timer capture compare interrupt occurs. -//! -//! This function registers the handler to be called when a timer -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific SPI interrupts must be enabled -//! via SPI_enableInterrupt(). It is the interrupt handler's responsibility to -//! clear the interrupt source via SPI_clearInterruptFlag(). -//! -//! \return None. -// -//***************************************************************************** -extern void SPI_registerInterrupt(uint32_t moduleInstance, - void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the timer -//! -//! \param moduleInstance is the instance of the eUSCI A/B module. Valid -//! parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! - \b EUSCI_B0_BASE -//! - \b EUSCI_B1_BASE -//! - \b EUSCI_B2_BASE -//! - \b EUSCI_B3_BASE -//! -//! This function unregisters the handler to be called when timer -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void SPI_unregisterInterrupt(uint32_t moduleInstance); - -/* Backwards Compatibility Layer */ -#define EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 -#define EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT EUSCI_B_CTLW0_CKPH - -#define EUSCI_B_SPI_MSB_FIRST EUSCI_B_CTLW0_MSB -#define EUSCI_B_SPI_LSB_FIRST 0x00 - -#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_HIGH EUSCI_B_CTLW0_CKPL -#define EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 - -#define EUSCI_B_SPI_CLOCKSOURCE_ACLK EUSCI_B_CTLW0_SSEL__ACLK -#define EUSCI_B_SPI_CLOCKSOURCE_SMCLK EUSCI_B_CTLW0_SSEL__SMCLK - -#define EUSCI_B_SPI_3PIN EUSCI_B_CTLW0_MODE_0 -#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH EUSCI_B_CTLW0_MODE_1 -#define EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_LOW EUSCI_B_CTLW0_MODE_2 - -#define EUSCI_B_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00 -#define EUSCI_B_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE EUSCI_B_CTLW0_STEM - -#define EUSCI_B_SPI_TRANSMIT_INTERRUPT EUSCI_B_IE_TXIE0 -#define EUSCI_B_SPI_RECEIVE_INTERRUPT EUSCI_B_IE_RXIE0 - -#define EUSCI_B_SPI_BUSY EUSCI_B_STATW_BBUSY -#define EUSCI_B_SPI_NOT_BUSY 0x00 - -#define EUSCI_A_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT 0x00 -#define EUSCI_A_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT EUSCI_A_CTLW0_CKPH - -#define EUSCI_A_SPI_MSB_FIRST EUSCI_A_CTLW0_MSB -#define EUSCI_A_SPI_LSB_FIRST 0x00 - -#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_HIGH EUSCI_A_CTLW0_CKPL -#define EUSCI_A_SPI_CLOCKPOLARITY_INACTIVITY_LOW 0x00 - -#define EUSCI_A_SPI_CLOCKSOURCE_ACLK EUSCI_A_CTLW0_SSEL__ACLK -#define EUSCI_A_SPI_CLOCKSOURCE_SMCLK EUSCI_A_CTLW0_SSEL__SMCLK - -#define EUSCI_A_SPI_3PIN EUSCI_A_CTLW0_MODE_0 -#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_HIGH EUSCI_A_CTLW0_MODE_1 -#define EUSCI_A_SPI_4PIN_UCxSTE_ACTIVE_LOW EUSCI_A_CTLW0_MODE_2 - -#define EUSCI_A_SPI_PREVENT_CONFLICTS_WITH_OTHER_MASTERS 0x00 -#define EUSCI_A_SPI_ENABLE_SIGNAL_FOR_4WIRE_SLAVE EUSCI_A_CTLW0_STEM - -#define EUSCI_A_SPI_TRANSMIT_INTERRUPT EUSCI_A_IE_TXIE -#define EUSCI_A_SPI_RECEIVE_INTERRUPT EUSCI_A_IE_RXIE - -#define EUSCI_A_SPI_BUSY EUSCI_B_STATW_BBUSY -#define EUSCI_A_SPI_NOT_BUSY 0x00 - -extern void EUSCI_A_SPI_select4PinFunctionality(uint32_t baseAddress, - uint8_t select4PinFunctionality); -extern void EUSCI_A_SPI_masterChangeClock(uint32_t baseAddress, - uint32_t clockSourceFrequency, uint32_t desiredSpiClock); -extern bool EUSCI_A_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst, - uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode); -extern void EUSCI_A_SPI_changeClockPhasePolarity(uint32_t baseAddress, - uint16_t clockPhase, uint16_t clockPolarity); -extern void EUSCI_A_SPI_transmitData(uint32_t baseAddress, - uint8_t transmitData); -extern uint8_t EUSCI_A_SPI_receiveData(uint32_t baseAddress); -extern void EUSCI_A_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask); -extern void EUSCI_A_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask); -extern uint8_t EUSCI_A_SPI_getInterruptStatus(uint32_t baseAddress, - uint8_t mask); -extern void EUSCI_A_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask); -extern void EUSCI_A_SPI_enable(uint32_t baseAddress); -extern void EUSCI_A_SPI_disable(uint32_t baseAddress); -extern uint32_t EUSCI_A_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress); -extern uint32_t EUSCI_A_SPI_getTransmitBufferAddressForDMA( - uint32_t baseAddress); -extern bool EUSCI_A_SPI_isBusy(uint32_t baseAddress); -extern void EUSCI_B_SPI_select4PinFunctionality(uint32_t baseAddress, - uint8_t select4PinFunctionality); -extern void EUSCI_B_SPI_masterChangeClock(uint32_t baseAddress, - uint32_t clockSourceFrequency, uint32_t desiredSpiClock); -extern bool EUSCI_B_SPI_slaveInit(uint32_t baseAddress, uint16_t msbFirst, - uint16_t clockPhase, uint16_t clockPolarity, uint16_t spiMode); -extern void EUSCI_B_SPI_changeClockPhasePolarity(uint32_t baseAddress, - uint16_t clockPhase, uint16_t clockPolarity); -extern void EUSCI_B_SPI_transmitData(uint32_t baseAddress, - uint8_t transmitData); -extern uint8_t EUSCI_B_SPI_receiveData(uint32_t baseAddress); -extern void EUSCI_B_SPI_enableInterrupt(uint32_t baseAddress, uint8_t mask); -extern void EUSCI_B_SPI_disableInterrupt(uint32_t baseAddress, uint8_t mask); -extern uint8_t EUSCI_B_SPI_getInterruptStatus(uint32_t baseAddress, - uint8_t mask); -extern void EUSCI_B_SPI_clearInterruptFlag(uint32_t baseAddress, uint8_t mask); -extern void EUSCI_B_SPI_enable(uint32_t baseAddress); -extern void EUSCI_B_SPI_disable(uint32_t baseAddress); -extern uint32_t EUSCI_B_SPI_getReceiveBufferAddressForDMA(uint32_t baseAddress); -extern uint32_t EUSCI_B_SPI_getTransmitBufferAddressForDMA( - uint32_t baseAddress); -extern bool EUSCI_B_SPI_isBusy(uint32_t baseAddress); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* SPI_H_ */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/sysctl.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/sysctl.c deleted file mode 100644 index c609f355946..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/sysctl.c +++ /dev/null @@ -1,284 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/* Standard Includes */ -#include -#include - -/* DriverLib Includes */ -#include -#include - -/* Define to ensure that our current MSP432 has the SYSCTL module. This - definition is included in the device specific header file */ -#ifdef __MCU_HAS_SYSCTL__ - -#ifdef DEBUG - -static bool SysCtlSRAMBankValid(uint8_t sramBank) -{ - return( - sramBank == SYSCTL_SRAM_BANK7 || - sramBank == SYSCTL_SRAM_BANK6 || - sramBank == SYSCTL_SRAM_BANK5 || - sramBank == SYSCTL_SRAM_BANK4 || - sramBank == SYSCTL_SRAM_BANK3 || - sramBank == SYSCTL_SRAM_BANK2 || - sramBank == SYSCTL_SRAM_BANK1 - ); -} - -static bool SysCtlSRAMBankValidRet(uint8_t sramBank) -{ - sramBank &= ~(SYSCTL_SRAM_BANK7 & SYSCTL_SRAM_BANK6 & - SYSCTL_SRAM_BANK5 & SYSCTL_SRAM_BANK4 & - SYSCTL_SRAM_BANK3 & SYSCTL_SRAM_BANK2 & - SYSCTL_SRAM_BANK1); - - return (sramBank == 0); -} - -static bool SysCtlPeripheralIsValid (uint16_t hwPeripheral) -{ - hwPeripheral &= ~(SYSCTL_PERIPH_DMA & SYSCTL_PERIPH_WDT & - SYSCTL_PERIPH_ADC & SYSCTL_PERIPH_EUSCIB3 & - SYSCTL_PERIPH_EUSCIB2 & SYSCTL_PERIPH_EUSCIB1 & - SYSCTL_PERIPH_EUSCIB0 & SYSCTL_PERIPH_EUSCIA3 & - SYSCTL_PERIPH_EUSCIA2 & SYSCTL_PERIPH_EUSCIA1 & - SYSCTL_PERIPH_EUSCIA0 & SYSCTL_PERIPH_TIMER32_0_MODULE & - SYSCTL_PERIPH_TIMER16_3 & SYSCTL_PERIPH_TIMER16_2 & - SYSCTL_PERIPH_TIMER16_2 & SYSCTL_PERIPH_TIMER16_1 & - SYSCTL_PERIPH_TIMER16_0); - - return (hwPeripheral == 0); -} -#endif - -void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance, - uint_fast8_t *length, uint32_t **data_address) -{ - /* TLV Structure Start Address */ - uint32_t *TLV_address = (uint32_t *) TLV_START; - - while (((*TLV_address != tag)) // check for tag and instance - && (*TLV_address != TLV_TAGEND)) // do range check first - { - if (*TLV_address == tag) - { - if(instance == 0) - { - break; - } - - /* Repeat until requested instance is reached */ - instance--; - } - - TLV_address += (*(TLV_address + 1)) + 2; - } - - /* Check if Tag match happened... */ - if (*TLV_address == tag) - { - /* Return length = Address + 1 */ - *length = (*(TLV_address + 1))*4; - /* Return address of first data/value info = Address + 2 */ - *data_address = (uint32_t *) (TLV_address + 2); - } - // If there was no tag match and the end of TLV structure was reached.. - else - { - // Return 0 for TAG not found - *length = 0; - // Return 0 for TAG not found - *data_address = 0; - } -} - -uint_least32_t SysCtl_getSRAMSize(void) -{ - return SYSCTL->SRAM_SIZE; -} - -uint_least32_t SysCtl_getFlashSize(void) -{ - return SYSCTL->FLASH_SIZE; -} - -void SysCtl_disableNMISource(uint_fast8_t flags) -{ - SYSCTL->NMI_CTLSTAT &= ~(flags); -} - -void SysCtl_enableNMISource(uint_fast8_t flags) -{ - SYSCTL->NMI_CTLSTAT |= flags; -} - -uint_fast8_t SysCtl_getNMISourceStatus(void) -{ - return SYSCTL->NMI_CTLSTAT & (SYSCTL_NMI_CTLSTAT_CS_FLG | - SYSCTL_NMI_CTLSTAT_PSS_FLG | - SYSCTL_NMI_CTLSTAT_PCM_FLG | - SYSCTL_NMI_CTLSTAT_PIN_FLG); -} - -void SysCtl_enableSRAMBank(uint_fast8_t sramBank) -{ - ASSERT(SysCtlSRAMBankValid(sramBank)); - - /* Waiting for SRAM Ready Bit to be set */ - while (!(SYSCTL->SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY)) - ; - - SYSCTL->SRAM_BANKEN = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN); -} - -void SysCtl_disableSRAMBank(uint_fast8_t sramBank) -{ - ASSERT(SysCtlSRAMBankValid(sramBank)); - - /* Waiting for SRAM Ready Bit to be set */ - while (!(SYSCTL->SRAM_BANKEN & SYSCTL_SRAM_BANKEN_SRAM_RDY)) - ; - - switch (sramBank) - { - case SYSCTL_SRAM_BANK7: - sramBank = SYSCTL_SRAM_BANK6 + SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4 - + SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2 - + SYSCTL_SRAM_BANK1; - break; - case SYSCTL_SRAM_BANK6: - sramBank = SYSCTL_SRAM_BANK5 + SYSCTL_SRAM_BANK4 - + SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2 - + SYSCTL_SRAM_BANK1; - break; - case SYSCTL_SRAM_BANK5: - sramBank = SYSCTL_SRAM_BANK4 + SYSCTL_SRAM_BANK3 - + SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1; - break; - case SYSCTL_SRAM_BANK4: - sramBank = SYSCTL_SRAM_BANK3 + SYSCTL_SRAM_BANK2 - + SYSCTL_SRAM_BANK1; - break; - case SYSCTL_SRAM_BANK3: - sramBank = SYSCTL_SRAM_BANK2 + SYSCTL_SRAM_BANK1; - break; - case SYSCTL_SRAM_BANK2: - sramBank = SYSCTL_SRAM_BANK1; - break; - case SYSCTL_SRAM_BANK1: - sramBank = 0; - break; - default: - return; - } - - SYSCTL->SRAM_BANKEN = (sramBank | SYSCTL_SRAM_BANKEN_BNK0_EN); -} - -void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank) -{ - ASSERT(SysCtlSRAMBankValidRet(sramBank)); - - /* Waiting for SRAM Ready Bit to be set */ - while (!(SYSCTL->SRAM_BANKRET & SYSCTL_SRAM_BANKRET_SRAM_RDY)) - ; - - SYSCTL->SRAM_BANKRET |= sramBank; -} - -void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank) -{ - ASSERT(SysCtlSRAMBankValidRet(sramBank)); - - /* Waiting for SRAM Ready Bit to be set */ - while (!(SYSCTL->SRAM_BANKRET & SYSCTL_SRAM_BANKRET_SRAM_RDY)) - ; - - SYSCTL->SRAM_BANKRET &= ~sramBank; -} - -void SysCtl_rebootDevice(void) -{ - SYSCTL->REBOOT_CTL = (SYSCTL_REBOOT_CTL_REBOOT | SYSCTL_REBOOT_KEY); -} - -void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices) -{ - ASSERT(SysCtlPeripheralIsValid(devices)); - SYSCTL->PERIHALT_CTL &= ~devices; -} - -void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices) -{ - ASSERT(SysCtlPeripheralIsValid(devices)); - SYSCTL->PERIHALT_CTL |= devices; -} - -void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType) -{ - if (resetType) - SYSCTL->WDTRESET_CTL |= - SYSCTL_WDTRESET_CTL_TIMEOUT; - else - SYSCTL->WDTRESET_CTL &= ~SYSCTL_WDTRESET_CTL_TIMEOUT; -} - -void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType) -{ - ASSERT(resetType <= SYSCTL_HARD_RESET); - - if (resetType) - SYSCTL->WDTRESET_CTL |= - SYSCTL_WDTRESET_CTL_VIOLATION; - else - SYSCTL->WDTRESET_CTL &= ~SYSCTL_WDTRESET_CTL_VIOLATION; -} - -void SysCtl_enableGlitchFilter(void) -{ - SYSCTL->DIO_GLTFLT_CTL |= SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN; -} - -void SysCtl_disableGlitchFilter(void) -{ - SYSCTL->DIO_GLTFLT_CTL &= ~SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN; -} - -uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage, - uint32_t temperature) -{ - return HWREG16(TLV_BASE + refVoltage + temperature); -} - -#endif /* __MCU_HAS_SYSCTL__ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/sysctl.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/sysctl.h deleted file mode 100644 index 9f6c2964fb0..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/sysctl.h +++ /dev/null @@ -1,545 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __SYSCTL_H__ -#define __SYSCTL_H__ - -#include -#include - -/* Define to ensure that our current MSP432 has the SYSCTL module. This - definition is included in the device specific header file */ -#ifdef __MCU_HAS_SYSCTL__ - -//***************************************************************************** -// -//! \addtogroup sysctl_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Control specific variables -// -//***************************************************************************** -#define SYSCTL_SRAM_BANK7 SYSCTL_SRAM_BANKEN_BNK7_EN -#define SYSCTL_SRAM_BANK6 SYSCTL_SRAM_BANKEN_BNK6_EN -#define SYSCTL_SRAM_BANK5 SYSCTL_SRAM_BANKEN_BNK5_EN -#define SYSCTL_SRAM_BANK4 SYSCTL_SRAM_BANKEN_BNK4_EN -#define SYSCTL_SRAM_BANK3 SYSCTL_SRAM_BANKEN_BNK3_EN -#define SYSCTL_SRAM_BANK2 SYSCTL_SRAM_BANKEN_BNK2_EN -#define SYSCTL_SRAM_BANK1 SYSCTL_SRAM_BANKEN_BNK1_EN - -#define SYSCTL_HARD_RESET 1 -#define SYSCTL_SOFT_RESET 0 - -#define SYSCTL_PERIPH_DMA SYSCTL_PERIHALT_CTL_HALT_DMA -#define SYSCTL_PERIPH_WDT SYSCTL_PERIHALT_CTL_HALT_WDT -#define SYSCTL_PERIPH_ADC SYSCTL_PERIHALT_CTL_HALT_ADC -#define SYSCTL_PERIPH_EUSCIB3 SYSCTL_PERIHALT_CTL_HALT_EUB3 -#define SYSCTL_PERIPH_EUSCIB2 SYSCTL_PERIHALT_CTL_HALT_EUB2 -#define SYSCTL_PERIPH_EUSCIB1 SYSCTL_PERIHALT_CTL_HALT_EUB1 -#define SYSCTL_PERIPH_EUSCIB0 SYSCTL_PERIHALT_CTL_HALT_EUB0 -#define SYSCTL_PERIPH_EUSCIA3 SYSCTL_PERIHALT_CTL_HALT_EUA3 -#define SYSCTL_PERIPH_EUSCIA2 SYSCTL_PERIHALT_CTL_HALT_EUA2 -#define SYSCTL_PERIPH_EUSCIA1 SYSCTL_PERIHALT_CTL_HALT_EUA1 -#define SYSCTL_PERIPH_EUSCIA0 SYSCTL_PERIHALT_CTL_HALT_EUA0 -#define SYSCTL_PERIPH_TIMER32_0_MODULE SYSCTL_PERIHALT_CTL_HALT_T32_0 -#define SYSCTL_PERIPH_TIMER16_3 SYSCTL_PERIHALT_CTL_HALT_T16_3 -#define SYSCTL_PERIPH_TIMER16_2 SYSCTL_PERIHALT_CTL_HALT_T16_2 -#define SYSCTL_PERIPH_TIMER16_1 SYSCTL_PERIHALT_CTL_HALT_T16_1 -#define SYSCTL_PERIPH_TIMER16_0 SYSCTL_PERIHALT_CTL_HALT_T16_0 - -#define SYSCTL_NMIPIN_SRC SYSCTL_NMI_CTLSTAT_PIN_SRC -#define SYSCTL_PCM_SRC SYSCTL_NMI_CTLSTAT_PCM_SRC -#define SYSCTL_PSS_SRC SYSCTL_NMI_CTLSTAT_PSS_SRC -#define SYSCTL_CS_SRC SYSCTL_NMI_CTLSTAT_CS_SRC - -#define SYSCTL_REBOOT_KEY 0x6900 - -#define SYSCTL_1_2V_REF (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE -#define SYSCTL_1_45V_REF (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE -#define SYSCTL_2_5V_REF (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE - -#define SYSCTL_85_DEGREES_C 4 -#define SYSCTL_30_DEGREES_C 0 - - -#define TLV_START 0x00201004 -#define TLV_TAG_RESERVED1 1 -#define TLV_TAG_RESERVED2 2 -#define TLV_TAG_CS 3 -#define TLV_TAG_FLASHCTL 4 -#define TLV_TAG_ADC14 5 -#define TLV_TAG_RESERVED6 6 -#define TLV_TAG_RESERVED7 7 -#define TLV_TAG_REF 8 -#define TLV_TAG_RESERVED9 9 -#define TLV_TAG_RESERVED10 10 -#define TLV_TAG_DEVINFO 11 -#define TLV_TAG_DIEREC 12 -#define TLV_TAG_RANDNUM 13 -#define TLV_TAG_RESERVED14 14 -#define TLV_TAG_BSL 15 -#define TLV_TAGEND 0x0BD0E11D - -//***************************************************************************** -// -// Structures for TLV definitions -// -//***************************************************************************** -typedef struct -{ - uint32_t maxProgramPulses; - uint32_t maxErasePulses; -} SysCtl_FlashTLV_Info; - -typedef struct -{ - uint32_t rDCOIR_FCAL_RSEL04; - uint32_t rDCOIR_FCAL_RSEL5; - uint32_t rDCOIR_MAXPOSTUNE_RSEL04; - uint32_t rDCOIR_MAXNEGTUNE_RSEL04; - uint32_t rDCOIR_MAXPOSTUNE_RSEL5; - uint32_t rDCOIR_MAXNEGTUNE_RSEL5; - uint32_t rDCOIR_CONSTK_RSEL04; - uint32_t rDCOIR_CONSTK_RSEL5; - uint32_t rDCOER_FCAL_RSEL04; - uint32_t rDCOER_FCAL_RSEL5; - uint32_t rDCOER_MAXPOSTUNE_RSEL04; - uint32_t rDCOER_MAXNEGTUNE_RSEL04; - uint32_t rDCOER_MAXPOSTUNE_RSEL5; - uint32_t rDCOER_MAXNEGTUNE_RSEL5; - uint32_t rDCOER_CONSTK_RSEL04; - uint32_t rDCOER_CONSTK_RSEL5; - -} SysCtl_CSCalTLV_Info; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! Gets the size of the SRAM. -//! -//! \return The total number of bytes of SRAM. -// -//***************************************************************************** -extern uint_least32_t SysCtl_getSRAMSize(void); - -//***************************************************************************** -// -//! Gets the size of the flash. -//! -//! \return The total number of bytes of flash. -// -//***************************************************************************** -extern uint_least32_t SysCtl_getFlashSize(void); - -//***************************************************************************** -// -//! Reboots the device and causes the device to re-initialize itself. -//! -//! \return This function does not return. -// -//***************************************************************************** -extern void SysCtl_rebootDevice(void); - -//***************************************************************************** -// -//! The TLV structure uses a tag or base address to identify segments of the -//! table where information is stored. Some examples of TLV tags are Peripheral -//! Descriptor, Interrupts, Info Block and Die Record. This function retrieves -//! the value of a tag and the length of the tag. -//! -//! \param tag represents the tag for which the information needs to be -//! retrieved. -//! Valid values are: -//! - \b TLV_TAG_RESERVED1 -//! - \b TLV_TAG_RESERVED2 -//! - \b TLV_TAG_CS -//! - \b TLV_TAG_FLASHCTL -//! - \b TLV_TAG_ADC14 -//! - \b TLV_TAG_RESERVED6 -//! - \b TLV_TAG_RESERVED7 -//! - \b TLV_TAG_REF -//! - \b TLV_TAG_RESERVED9 -//! - \b TLV_TAG_RESERVED10 -//! - \b TLV_TAG_DEVINFO -//! - \b TLV_TAG_DIEREC -//! - \b TLV_TAG_RANDNUM -//! - \b TLV_TAG_RESERVED14 -//! \param instance In some cases a specific tag may have more than one -//! instance. For example there may be multiple instances of timer -//! calibration data present under a single Timer Cal tag. This variable -//! specifies the instance for which information is to be retrieved (0, -//! 1, etc.). When only one instance exists; 0 is passed. -//! \param length Acts as a return through indirect reference. The function -//! retrieves the value of the TLV tag length. This value is pointed to -//! by *length and can be used by the application level once the -//! function is called. If the specified tag is not found then the -//! pointer is null 0. -//! \param data_address acts as a return through indirect reference. Once the -//! function is called data_address points to the pointer that holds the -//! value retrieved from the specified TLV tag. If the specified tag is -//! not found then the pointer is null 0. -//! -//! \return None -// -//***************************************************************************** -extern void SysCtl_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance, - uint_fast8_t *length, uint32_t **data_address); - -//***************************************************************************** -// -//! Enables a set of banks in the SRAM. This can be used to optimize power -//! consumption when every SRAM bank isn't needed. It is important to note -//! that when a higher bank is enabled, all of the SRAM banks below that bank -//! are also enabled. For example, if the user enables SYSCTL_SRAM_BANK7, -//! the banks SYSCTL_SRAM_BANK1 through SYSCTL_SRAM_BANK7 will be enabled -//! (SRAM_BANK0 is reserved and always enabled). -//! -//! \param sramBank The SRAM bank tier to enable. -//! Must be only one of the following values: -//! - \b SYSCTL_SRAM_BANK1, -//! - \b SYSCTL_SRAM_BANK2, -//! - \b SYSCTL_SRAM_BANK3, -//! - \b SYSCTL_SRAM_BANK4, -//! - \b SYSCTL_SRAM_BANK5, -//! - \b SYSCTL_SRAM_BANK6, -//! - \b SYSCTL_SRAM_BANK7 -//! -//! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled. -//! -//! \return None. -// -//***************************************************************************** -extern void SysCtl_enableSRAMBank(uint_fast8_t sramBank); - -//***************************************************************************** -// -//! Disables a set of banks in the SRAM. This can be used to optimize power -//! consumption when every SRAM bank isn't needed. It is important to note -//! that when a higher bank is disabled, all of the SRAM banks above that bank -//! are also disabled. For example, if the user disables SYSCTL_SRAM_BANK5, -//! the banks SYSCTL_SRAM_BANK6 through SYSCTL_SRAM_BANK7 will be disabled. -//! -//! \param sramBank The SRAM bank tier to disable. -//! Must be only one of the following values: -//! - \b SYSCTL_SRAM_BANK1, -//! - \b SYSCTL_SRAM_BANK2, -//! - \b SYSCTL_SRAM_BANK3, -//! - \b SYSCTL_SRAM_BANK4, -//! - \b SYSCTL_SRAM_BANK5, -//! - \b SYSCTL_SRAM_BANK6, -//! - \b SYSCTL_SRAM_BANK7 -//! -//! \note \b SYSCTL_SRAM_BANK0 is reserved and always enabled. -//! -//! \return None. -// -//***************************************************************************** -extern void SysCtl_disableSRAMBank(uint_fast8_t sramBank); - -//***************************************************************************** -// -//! Enables retention of the specified SRAM bank register when the device goes -//! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM -//! banks specified with this function will be placed into retention mode. By -//! default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved) is -//! disabled. Retention of individual banks can be set without the restrictions -//! of the enable/disable functions. -//! -//! \param sramBank The SRAM banks to enable retention -//! Can be a bitwise OR of the following values: -//! - \b SYSCTL_SRAM_BANK1, -//! - \b SYSCTL_SRAM_BANK2, -//! - \b SYSCTL_SRAM_BANK3, -//! - \b SYSCTL_SRAM_BANK4, -//! - \b SYSCTL_SRAM_BANK5, -//! - \b SYSCTL_SRAM_BANK6, -//! - \b SYSCTL_SRAM_BANK7 -//! \note \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled. -//! -//! -//! \return None. -// -//***************************************************************************** -extern void SysCtl_enableSRAMBankRetention(uint_fast8_t sramBank); - -//***************************************************************************** -// -//! Disables retention of the specified SRAM bank register when the device goes -//! into LPM3 mode. When the system is placed in LPM3 mode, the SRAM -//! banks specified with this function will not be placed into retention mode. -//! By default, retention of every SRAM bank except SYSCTL_SRAM_BANK0 (reserved) -//! is disabled. Retention of individual banks can be set without the -//! restrictions of the enable/disable SRAM bank functions. -//! -//! \param sramBank The SRAM banks to disable retention -//! Can be a bitwise OR of the following values: -//! - \b SYSCTL_SRAM_BANK1, -//! - \b SYSCTL_SRAM_BANK2, -//! - \b SYSCTL_SRAM_BANK3, -//! - \b SYSCTL_SRAM_BANK4, -//! - \b SYSCTL_SRAM_BANK5, -//! - \b SYSCTL_SRAM_BANK6, -//! - \b SYSCTL_SRAM_BANK7 -//! \note \b SYSCTL_SRAM_BANK0 is reserved and retention is always enabled. -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_disableSRAMBankRetention(uint_fast8_t sramBank); - -//***************************************************************************** -// -//! Makes it so that the provided peripherals will either halt execution after -//! a CPU HALT. Parameters in this function can be combined to account for -//! multiple peripherals. By default, all peripherals keep running after a -//! CPU HALT. -//! -//! \param devices The peripherals to continue running after a CPU HALT -//! This can be a bitwise OR of the following values: -//! - \b SYSCTL_PERIPH_DMA, -//! - \b SYSCTL_PERIPH_WDT, -//! - \b SYSCTL_PERIPH_ADC, -//! - \b SYSCTL_PERIPH_EUSCIB3, -//! - \b SYSCTL_PERIPH_EUSCIB2, -//! - \b SYSCTL_PERIPH_EUSCIB1 -//! - \b SYSCTL_PERIPH_EUSCIB0, -//! - \b SYSCTL_PERIPH_EUSCIA3, -//! - \b SYSCTL_PERIPH_EUSCIA2 -//! - \b SYSCTL_PERIPH_EUSCIA1, -//! - \b SYSCTL_PERIPH_EUSCIA0, -//! - \b SYSCTL_PERIPH_TIMER32_0_MODULE, -//! - \b SYSCTL_PERIPH_TIMER16_3, -//! - \b SYSCTL_PERIPH_TIMER16_2, -//! - \b SYSCTL_PERIPH_TIMER16_1, -//! - \b SYSCTL_PERIPH_TIMER16_0 -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_enablePeripheralAtCPUHalt(uint_fast16_t devices); - -//***************************************************************************** -// -//! Makes it so that the provided peripherals will either halt execution after -//! a CPU HALT. Parameters in this function can be combined to account for -//! multiple peripherals. By default, all peripherals keep running after a -//! CPU HALT. -//! -//! \param devices The peripherals to disable after a CPU HALT -//! -//! The \e devices parameter can be a bitwise OR of the following values: -//! This can be a bitwise OR of the following values: -//! - \b SYSCTL_PERIPH_DMA, -//! - \b SYSCTL_PERIPH_WDT, -//! - \b SYSCTL_PERIPH_ADC, -//! - \b SYSCTL_PERIPH_EUSCIB3, -//! - \b SYSCTL_PERIPH_EUSCIB2, -//! - \b SYSCTL_PERIPH_EUSCIB1 -//! - \b SYSCTL_PERIPH_EUSCIB0, -//! - \b SYSCTL_PERIPH_EUSCIA3, -//! - \b SYSCTL_PERIPH_EUSCIA2 -//! - \b SYSCTL_PERIPH_EUSCIA1, -//! - \b SYSCTL_PERIPH_EUSCIA0, -//! - \b SYSCTL_PERIPH_TIMER32_0_MODULE, -//! - \b SYSCTL_PERIPH_TIMER16_3, -//! - \b SYSCTL_PERIPH_TIMER16_2, -//! - \b SYSCTL_PERIPH_TIMER16_1, -//! - \b SYSCTL_PERIPH_TIMER16_0 -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_disablePeripheralAtCPUHalt(uint_fast16_t devices); - -//***************************************************************************** -// -//! Sets the type of RESET that happens when a watchdog timeout occurs. -//! -//! \param resetType The type of reset to set -//! -//! The \e resetType parameter must be only one of the following values: -//! - \b SYSCTL_HARD_RESET, -//! - \b SYSCTL_SOFT_RESET -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_setWDTTimeoutResetType(uint_fast8_t resetType); - -//***************************************************************************** -// -//! Sets the type of RESET that happens when a watchdog password violation -//! occurs. -//! -//! \param resetType The type of reset to set -//! -//! The \e resetType parameter must be only one of the following values: -//! - \b SYSCTL_HARD_RESET, -//! - \b SYSCTL_SOFT_RESET -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_setWDTPasswordViolationResetType(uint_fast8_t resetType); - -//***************************************************************************** -// -//! Disables NMIs for the provided modules. When disabled, a NMI flag will not -//! occur when a fault condition comes from the corresponding modules. -//! -//! \param flags The NMI sources to disable -//! Can be a bitwise OR of the following parameters: -//! - \b SYSCTL_NMIPIN_SRC, -//! - \b SYSCTL_PCM_SRC, -//! - \b SYSCTL_PSS_SRC, -//! - \b SYSCTL_CS_SRC -//! -// -//***************************************************************************** -extern void SysCtl_disableNMISource(uint_fast8_t flags); - -//***************************************************************************** -// -//! Enables NMIs for the provided modules. When enabled, a NMI flag will -//! occur when a fault condition comes from the corresponding modules. -//! -//! \param flags The NMI sources to enable -//! Can be a bitwise OR of the following parameters: -//! - \b SYSCTL_NMIPIN_SRC, -//! - \b SYSCTL_PCM_SRC, -//! - \b SYSCTL_PSS_SRC, -//! - \b SYSCTL_CS_SRC -//! -// -//***************************************************************************** -extern void SysCtl_enableNMISource(uint_fast8_t flags); - -//***************************************************************************** -// -//! Returns the current sources of NMIs that are enabled -//! -//! \return Bitwise OR of NMI flags that are enabled -// -//***************************************************************************** -extern uint_fast8_t SysCtl_getNMISourceStatus(void); - -//***************************************************************************** -// -//! Enables glitch suppression on the reset pin of the device. Refer to the -//! device data sheet for specific information about glitch suppression -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_enableGlitchFilter(void); - -//***************************************************************************** -// -//! Disables glitch suppression on the reset pin of the device. Refer to the -//! device data sheet for specific information about glitch suppression -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_disableGlitchFilter(void); - -//***************************************************************************** -// -//! Retrieves the calibration constant of the temperature sensor to be used -//! in temperature calculation. -//! -//! \param refVoltage Reference voltage being used. -//! -//! The \e refVoltage parameter must be only one of the following values: -//! - \b SYSCTL_1_2V_REF -//! - \b SYSCTL_1_45V_REF -//! - \b SYSCTL_2_5V_REF -//! -//! \param temperature is the calibration temperature that the user wants to be -//! returned. -//! -//! The \e temperature parameter must be only one of the following values: -//! - \b SYSCTL_30_DEGREES_C -//! - \b SYSCTL_85_DEGREES_C -//! -//! \return None. -// -// -//***************************************************************************** -extern uint_fast16_t SysCtl_getTempCalibrationConstant(uint32_t refVoltage, - uint32_t temperature); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* __MCU_HAS_SYSCTL__ */ - -#endif // __SYSCTL_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/sysctl_a.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/sysctl_a.c deleted file mode 100644 index cc43cbdd480..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/sysctl_a.c +++ /dev/null @@ -1,413 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/* Standard Includes */ -#include -#include - -/* DriverLib Includes */ -#include -#include - -/* Define to ensure that our current MSP432 has the SYSCTL_A module. This - definition is included in the device specific header file */ -#ifdef __MCU_HAS_SYSCTL_A__ - -void SysCtl_A_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance, - uint_fast8_t *length, uint32_t **data_address) -{ - /* TLV Structure Start Address */ - uint32_t *TLV_address = (uint32_t *) TLV_START; - - if(*TLV_address == 0xFFFFFFFF) - { - *length = 0; - // Return 0 for TAG not found - *data_address = 0; - return; - } - - while (((*TLV_address != tag)) // check for tag and instance - && (*TLV_address != TLV_TAGEND)) // do range check first - { - if (*TLV_address == tag) - { - if (instance == 0) - { - break; - } - - /* Repeat until requested instance is reached */ - instance--; - } - - TLV_address += (*(TLV_address + 1)) + 2; - } - - /* Check if Tag match happened... */ - if (*TLV_address == tag) - { - /* Return length = Address + 1 */ - *length = (*(TLV_address + 1)) * 4; - /* Return address of first data/value info = Address + 2 */ - *data_address = (uint32_t *) (TLV_address + 2); - } - // If there was no tag match and the end of TLV structure was reached.. - else - { - // Return 0 for TAG not found - *length = 0; - // Return 0 for TAG not found - *data_address = 0; - } -} - -uint_least32_t SysCtl_A_getSRAMSize(void) -{ - return SYSCTL_A->SRAM_SIZE; -} - -uint_least32_t SysCtl_A_getFlashSize(void) -{ - return SYSCTL_A->MAINFLASH_SIZE; -} - -uint_least32_t SysCtl_A_getInfoFlashSize(void) -{ - return SYSCTL_A->INFOFLASH_SIZE; -} - -void SysCtl_A_disableNMISource(uint_fast8_t flags) -{ - SYSCTL_A->NMI_CTLSTAT &= ~(flags); -} - -void SysCtl_A_enableNMISource(uint_fast8_t flags) -{ - SYSCTL_A->NMI_CTLSTAT |= flags; -} - -uint_fast8_t SysCtl_A_getNMISourceStatus(void) -{ - return SYSCTL_A->NMI_CTLSTAT & (SYSCTL_A_NMI_CTLSTAT_CS_FLG | - SYSCTL_A_NMI_CTLSTAT_PSS_FLG | - SYSCTL_A_NMI_CTLSTAT_PCM_FLG | - SYSCTL_A_NMI_CTLSTAT_PIN_FLG); -} - -void SysCtl_A_rebootDevice(void) -{ - SYSCTL_A->REBOOT_CTL = (SYSCTL_A_REBOOT_CTL_REBOOT | SYSCTL_A_REBOOT_KEY); -} - -void SysCtl_A_enablePeripheralAtCPUHalt(uint_fast16_t devices) -{ - SYSCTL_A->PERIHALT_CTL &= ~devices; -} - -void SysCtl_A_disablePeripheralAtCPUHalt(uint_fast16_t devices) -{ - SYSCTL_A->PERIHALT_CTL |= devices; -} - -void SysCtl_A_setWDTTimeoutResetType(uint_fast8_t resetType) -{ - if (resetType) - SYSCTL_A->WDTRESET_CTL |= SYSCTL_A_WDTRESET_CTL_TIMEOUT; - else - SYSCTL_A->WDTRESET_CTL &= ~SYSCTL_A_WDTRESET_CTL_TIMEOUT; -} - -void SysCtl_A_setWDTPasswordViolationResetType(uint_fast8_t resetType) -{ - if (resetType) - SYSCTL_A->WDTRESET_CTL |= SYSCTL_A_WDTRESET_CTL_VIOLATION; - else - SYSCTL_A->WDTRESET_CTL &= ~SYSCTL_A_WDTRESET_CTL_VIOLATION; -} - -void SysCtl_A_enableGlitchFilter(void) -{ - SYSCTL_A->DIO_GLTFLT_CTL |= SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN; -} - -void SysCtl_A_disableGlitchFilter(void) -{ - SYSCTL_A->DIO_GLTFLT_CTL &= ~SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN; -} - -uint_fast16_t SysCtl_A_getTempCalibrationConstant(uint32_t refVoltage, - uint32_t temperature) -{ - return HWREG16(TLV_BASE + refVoltage + temperature); -} - -bool SysCtl_A_enableSRAM(uint32_t addr) -{ - uint32_t bankSize, bankBit; - - /* If SRAM is busy, return false */ - if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY)) - return false; - - /* Grabbing the bank size */ - bankSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBANKS; - bankBit = (addr - SRAM_BASE) / bankSize; - - if (bankBit < 32) - { - SYSCTL_A->SRAM_BANKEN_CTL0 |= (1 << bankBit); - } else if (bankBit < 64) - { - SYSCTL_A->SRAM_BANKEN_CTL1 |= (1 << (bankBit - 32)); - } else if (bankBit < 96) - { - SYSCTL_A->SRAM_BANKEN_CTL2 |= (1 << (bankBit - 64)); - } else - { - SYSCTL_A->SRAM_BANKEN_CTL3 |= (1 << (bankBit - 96)); - } - - - return true; -} - -bool SysCtl_A_disableSRAM(uint32_t addr) -{ - uint32_t bankSize, bankBit; - - /* If SRAM is busy, return false */ - if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY)) - return false; - - /* Grabbing the bank size */ - bankSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBANKS; - bankBit = (addr - SRAM_BASE) / bankSize; - - if (bankBit < 32) - { - SYSCTL_A->SRAM_BANKEN_CTL0 &= ~(0xFFFFFFFF << bankBit); - } else if (bankBit < 64) - { - SYSCTL_A->SRAM_BANKEN_CTL1 &= ~(0xFFFFFFFF << (bankBit - 32)); - } else if (bankBit < 96) - { - SYSCTL_A->SRAM_BANKEN_CTL2 &= ~(0xFFFFFFFF << (bankBit - 64)); - } else - { - SYSCTL_A->SRAM_BANKEN_CTL3 &= ~(0xFFFFFFFF << (bankBit - 96)); - } - - - return true; -} - -bool SysCtl_A_enableSRAMRetention(uint32_t startAddr, - uint32_t endAddr) -{ - uint32_t blockSize, blockBitStart, blockBitEnd; - - if (startAddr > endAddr) - return false; - - /* If SRAM is busy, return false */ - if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BLKRET_RDY)) - return false; - - /* Getting how big each bank is and how many blocks we have per bank */ - blockSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBLOCKS; - blockBitStart = (startAddr - SRAM_BASE) / blockSize; - blockBitEnd = (endAddr - SRAM_BASE) / blockSize; - - if (blockBitStart < 32) - { - if (blockBitEnd < 32) - { - SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF >> (31 - blockBitEnd)) - & (0xFFFFFFFF << blockBitStart); - return true; - } else if (blockBitEnd < 64) - { - SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart); - SYSCTL_A->SRAM_BLKRET_CTL1 |= (0xFFFFFFFF - >> (31 - (blockBitEnd - 32))); - } else if (blockBitEnd < 96) - { - SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart); - SYSCTL_A->SRAM_BLKRET_CTL1 = 0xFFFFFFFF; - SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF - >> (31 - (blockBitEnd - 64))); - } else - { - SYSCTL_A->SRAM_BLKRET_CTL0 |= (0xFFFFFFFF << blockBitStart); - SYSCTL_A->SRAM_BLKRET_CTL1 = 0xFFFFFFFF; - SYSCTL_A->SRAM_BLKRET_CTL2 = 0xFFFFFFFF; - SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF - >> (31 - (blockBitEnd - 96))); - } - } else if (blockBitStart < 64) - { - if (blockBitEnd < 64) - { - SYSCTL_A->SRAM_BLKRET_CTL1 |= ((0xFFFFFFFF - >> (31 - (blockBitEnd - 32))) - & (0xFFFFFFFF << (blockBitStart - 32))); - return true; - } - - SYSCTL_A->SRAM_BLKRET_CTL1 = (0xFFFFFFFF << (blockBitStart - 32)); - - if (blockBitEnd < 96) - { - SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF - >> (31 - (blockBitEnd - 64))); - } else - { - - SYSCTL_A->SRAM_BLKRET_CTL2 |= 0xFFFFFFFF; - SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF - >> (31 - (blockBitEnd - 96))); - } - } else if (blockBitStart < 96) - { - if (blockBitEnd < 96) - { - SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF - >> (31 - (blockBitEnd - 64))) - & (0xFFFFFFFF << (blockBitStart - 64)); - return true; - } else - { - SYSCTL_A->SRAM_BLKRET_CTL2 |= (0xFFFFFFFF << (blockBitStart - 64)); - SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF - >> (31 - (blockBitEnd - 96))); - } - } else - { - SYSCTL_A->SRAM_BLKRET_CTL3 |= (0xFFFFFFFF >> (31 - (blockBitEnd - 96))) - & (0xFFFFFFFF << (blockBitStart - 96)); - } - - return true; - -} - -bool SysCtl_A_disableSRAMRetention(uint32_t startAddr, - uint32_t endAddr) -{ - uint32_t blockSize, blockBitStart, blockBitEnd; - - if (startAddr > endAddr) - return false; - - /* If SRAM is busy, return false */ - if(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BLKRET_RDY)) - return false; - - - /* Getting how big each bank is and how many blocks we have per bank */ - blockSize = SysCtl_A_getSRAMSize() / SYSCTL_A->SRAM_NUMBLOCKS; - blockBitStart = (startAddr - SRAM_BASE) / blockSize; - blockBitEnd = (endAddr - SRAM_BASE) / blockSize; - - if (blockBitStart < 32) - { - if (blockBitEnd < 32) - { - SYSCTL_A->SRAM_BLKRET_CTL0 &= ~((0xFFFFFFFF >> (31 - blockBitEnd)) - & (0xFFFFFFFF << blockBitStart)); - return true; - } - - SYSCTL_A->SRAM_BLKRET_CTL0 &= ~((0xFFFFFFFF << blockBitStart)); - - if (blockBitEnd < 64) - { - SYSCTL_A->SRAM_BLKRET_CTL1 &= ~((0xFFFFFFFF - >> (31 - (blockBitEnd - 32)))); - } else if (blockBitEnd < 96) - { - SYSCTL_A->SRAM_BLKRET_CTL1 = 0; - SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF - >> (31 - (blockBitEnd - 64))); - } else - { - SYSCTL_A->SRAM_BLKRET_CTL1 = 0; - SYSCTL_A->SRAM_BLKRET_CTL2 = 0; - SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF - >> (31 - (blockBitEnd - 96))); - } - } else if (blockBitStart < 64) - { - if (blockBitEnd < 64) - { - SYSCTL_A->SRAM_BLKRET_CTL1 &= ~((0xFFFFFFFF - >> (31 - (blockBitEnd - 32))) - & (0xFFFFFFFF << (blockBitStart - 32))); - return true; - } - - SYSCTL_A->SRAM_BLKRET_CTL1 &= ~(0xFFFFFFFF << (blockBitStart - 32)); - - if (blockBitEnd < 96) - { - SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF - >> (31 - (blockBitEnd - 64))); - } else - { - - SYSCTL_A->SRAM_BLKRET_CTL2 = 0; - SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF - >> (31 - (blockBitEnd - 96))); - } - } else if (blockBitStart < 96) - { - if (blockBitEnd < 96) - { - SYSCTL_A->SRAM_BLKRET_CTL2 &= ~((0xFFFFFFFF - >> (31 - (blockBitEnd - 64))) - & (0xFFFFFFFF << (blockBitStart - 64))); - } else - { - SYSCTL_A->SRAM_BLKRET_CTL2 &= ~(0xFFFFFFFF << (blockBitStart - 64)); - SYSCTL_A->SRAM_BLKRET_CTL3 &= ~(0xFFFFFFFF - >> (31 - (blockBitEnd - 96))); - } - } else - { - SYSCTL_A->SRAM_BLKRET_CTL3 &= ~((0xFFFFFFFF >> (31 - (blockBitEnd - 96))) - & (0xFFFFFFFF << (blockBitStart - 96))); - } - - return true; -} - -#endif /* __MCU_HAS_SYSCTL_A__ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/sysctl_a.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/sysctl_a.h deleted file mode 100644 index 0a4cc7e57f6..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/sysctl_a.h +++ /dev/null @@ -1,560 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __SYSCTL_A_H__ -#define __SYSCTL_A_H__ - -#include -#include -#include - -/* Define to ensure that our current MSP432 has the SYSCTL_A module. This - definition is included in the device specific header file */ -#ifdef __MCU_HAS_SYSCTL_A__ - -//***************************************************************************** -// -//! \addtogroup sysctl_a_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// Control specific variables -// -//***************************************************************************** -#define SYSCTL_A_HARD_RESET 1 -#define SYSCTL_A_SOFT_RESET 0 - -#define SYSCTL_A_PERIPH_LCD SYSCTL_A_PERIHALT_CTL_HALT_LCD -#define SYSCTL_A_PERIPH_DMA SYSCTL_A_PERIHALT_CTL_HALT_DMA -#define SYSCTL_A_PERIPH_WDT SYSCTL_A_PERIHALT_CTL_HALT_WDT -#define SYSCTL_A_PERIPH_ADC SYSCTL_A_PERIHALT_CTL_HALT_ADC -#define SYSCTL_A_PERIPH_EUSCIB3 SYSCTL_A_PERIHALT_CTL_HALT_EUB3 -#define SYSCTL_A_PERIPH_EUSCIB2 SYSCTL_A_PERIHALT_CTL_HALT_EUB2 -#define SYSCTL_A_PERIPH_EUSCIB1 SYSCTL_A_PERIHALT_CTL_HALT_EUB1 -#define SYSCTL_A_PERIPH_EUSCIB0 SYSCTL_A_PERIHALT_CTL_HALT_EUB0 -#define SYSCTL_A_PERIPH_EUSCIA3 SYSCTL_A_PERIHALT_CTL_HALT_EUA3 -#define SYSCTL_A_PERIPH_EUSCIA2 SYSCTL_A_PERIHALT_CTL_HALT_EUA2 -#define SYSCTL_A_PERIPH_EUSCIA1 SYSCTL_A_PERIHALT_CTL_HALT_EUA1 -#define SYSCTL_A_PERIPH_EUSCIA0 SYSCTL_A_PERIHALT_CTL_HALT_EUA0 -#define SYSCTL_A_PERIPH_TIMER32_0_MODULE SYSCTL_A_PERIHALT_CTL_HALT_T32_0 -#define SYSCTL_A_PERIPH_TIMER16_3 SYSCTL_A_PERIHALT_CTL_HALT_T16_3 -#define SYSCTL_A_PERIPH_TIMER16_2 SYSCTL_A_PERIHALT_CTL_HALT_T16_2 -#define SYSCTL_A_PERIPH_TIMER16_1 SYSCTL_A_PERIHALT_CTL_HALT_T16_1 -#define SYSCTL_A_PERIPH_TIMER16_0 SYSCTL_A_PERIHALT_CTL_HALT_T16_0 - -#define SYSCTL_A_NMIPIN_SRC SYSCTL_A_NMI_CTLSTAT_PIN_SRC -#define SYSCTL_A_PCM_SRC SYSCTL_A_NMI_CTLSTAT_PCM_SRC -#define SYSCTL_A_PSS_SRC SYSCTL_A_NMI_CTLSTAT_PSS_SRC -#define SYSCTL_A_CS_SRC SYSCTL_A_NMI_CTLSTAT_CS_SRC - -#define SYSCTL_A_REBOOT_KEY 0x6900 - -#define SYSCTL_A_1_2V_REF (uint32_t)&TLV->ADC14_REF1P2V_TS30C - (uint32_t)TLV_BASE -#define SYSCTL_A_1_45V_REF (uint32_t)&TLV->ADC14_REF1P45V_TS30C - (uint32_t)TLV_BASE -#define SYSCTL_A_2_5V_REF (uint32_t)&TLV->ADC14_REF2P5V_TS30C - (uint32_t)TLV_BASE - -#define SYSCTL_A_85_DEGREES_C 4 -#define SYSCTL_A_30_DEGREES_C 0 - -#define SYSCTL_A_BANKMASK 0x80000000 -#define SRAMCTL_CTL0_BANK 0x10000000 -#define SRAMCTL_CTL1_BANK 0x20000000 -#define SRAMCTL_CTL2_BANK 0x30000000 -#define SRAMCTL_CTL3_BANK 0x40000000 - - -#define TLV_START 0x00201004 -#define TLV_TAG_RESERVED1 1 -#define TLV_TAG_RESERVED2 2 -#define TLV_TAG_CS 3 -#define TLV_TAG_FLASHCTL 4 -#define TLV_TAG_ADC14 5 -#define TLV_TAG_RESERVED6 6 -#define TLV_TAG_RESERVED7 7 -#define TLV_TAG_REF 8 -#define TLV_TAG_RESERVED9 9 -#define TLV_TAG_RESERVED10 10 -#define TLV_TAG_DEVINFO 11 -#define TLV_TAG_DIEREC 12 -#define TLV_TAG_RANDNUM 13 -#define TLV_TAG_RESERVED14 14 -#define TLV_TAG_BSL 15 -#define TLV_TAGEND 0x0BD0E11D - -//***************************************************************************** -// -// Structures for TLV definitions -// -//***************************************************************************** -typedef struct -{ - uint32_t maxProgramPulses; - uint32_t maxErasePulses; -} SysCtl_A_FlashTLV_Info; - -typedef struct -{ - uint32_t rDCOIR_FCAL_RSEL04; - uint32_t rDCOIR_FCAL_RSEL5; - uint32_t rDCOIR_MAXPOSTUNE_RSEL04; - uint32_t rDCOIR_MAXNEGTUNE_RSEL04; - uint32_t rDCOIR_MAXPOSTUNE_RSEL5; - uint32_t rDCOIR_MAXNEGTUNE_RSEL5; - uint32_t rDCOIR_CONSTK_RSEL04; - uint32_t rDCOIR_CONSTK_RSEL5; - uint32_t rDCOER_FCAL_RSEL04; - uint32_t rDCOER_FCAL_RSEL5; - uint32_t rDCOER_MAXPOSTUNE_RSEL04; - uint32_t rDCOER_MAXNEGTUNE_RSEL04; - uint32_t rDCOER_MAXPOSTUNE_RSEL5; - uint32_t rDCOER_MAXNEGTUNE_RSEL5; - uint32_t rDCOER_CONSTK_RSEL04; - uint32_t rDCOER_CONSTK_RSEL5; - -} SysCtl_A_CSCalTLV_Info; - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! Gets the size of the SRAM. -//! -//! \return The total number of bytes of SRAM. -// -//***************************************************************************** -extern uint_least32_t SysCtl_A_getSRAMSize(void); - -//***************************************************************************** -// -//! Gets the size of the flash. -//! -//! \return The total number of bytes of main flash memory. -//! -//! \note This returns the total amount of main memory flash. To find how much -//! INFO memory is available, use the \link SysCtl_A_getInfoFlashSize -//! \endlink function. -// -//***************************************************************************** -extern uint_least32_t SysCtl_A_getFlashSize(void); - -//***************************************************************************** -// -//! Gets the size of the flash. -//! -//! \return The total number of bytes of flash of INFO flash memory. -//! -//! \note This returns the total amount of INFO memory flash. To find how much -//! main memory is available, use the \link SysCtl_A_getFlashSize -//! \endlink function. -// -//***************************************************************************** -extern uint_least32_t SysCtl_A_getInfoFlashSize(void); - -//***************************************************************************** -// -//! Reboots the device and causes the device to re-initialize itself. -//! -//! \return This function does not return. -// -//***************************************************************************** -extern void SysCtl_A_rebootDevice(void); - -//***************************************************************************** -// -//! The TLV structure uses a tag or base address to identify segments of the -//! table where information is stored. Some examples of TLV tags are Peripheral -//! Descriptor, Interrupts, Info Block and Die Record. This function retrieves -//! the value of a tag and the length of the tag. -//! -//! \param tag represents the tag for which the information needs to be -//! retrieved. -//! Valid values are: -//! - \b TLV_TAG_RESERVED1 -//! - \b TLV_TAG_RESERVED2 -//! - \b TLV_TAG_CS -//! - \b TLV_TAG_FLASHCTL -//! - \b TLV_TAG_ADC14 -//! - \b TLV_TAG_RESERVED6 -//! - \b TLV_TAG_RESERVED7 -//! - \b TLV_TAG_REF -//! - \b TLV_TAG_RESERVED9 -//! - \b TLV_TAG_RESERVED10 -//! - \b TLV_TAG_DEVINFO -//! - \b TLV_TAG_DIEREC -//! - \b TLV_TAG_RANDNUM -//! - \b TLV_TAG_RESERVED14 -//! \param instance In some cases a specific tag may have more than one -//! instance. For example there may be multiple instances of timer -//! calibration data present under a single Timer Cal tag. This variable -//! specifies the instance for which information is to be retrieved (0, -//! 1, etc.). When only one instance exists; 0 is passed. -//! \param length Acts as a return through indirect reference. The function -//! retrieves the value of the TLV tag length. This value is pointed to -//! by *length and can be used by the application level once the -//! function is called. If the specified tag is not found then the -//! pointer is null 0. -//! \param data_address acts as a return through indirect reference. Once the -//! function is called data_address points to the pointer that holds the -//! value retrieved from the specified TLV tag. If the specified tag is -//! not found then the pointer is null 0. -//! -//! \return None -// -//***************************************************************************** -extern void SysCtl_A_getTLVInfo(uint_fast8_t tag, uint_fast8_t instance, - uint_fast8_t *length, uint32_t **data_address); - -//***************************************************************************** -// -//! Enables areas of SRAM memory. This can be used to optimize power -//! consumption when every SRAM bank isn't needed. -//! This function takes in a 32-bit address to the area in SRAM to to enable. -//! It will convert this address into the corresponding register settings and -//! set them in the register accordingly. Note that passing an address to an -//! area other than SRAM will result in unreliable behavior. Addresses should -//! be given with reference to the SRAM_DATA area of SRAM (usually starting at -//! 0x20000000). -//! -//! \param addr Break address of SRAM to enable. All SRAM below this address -//! will also be enabled. If an unaligned address is given the appropriate -//! aligned address will be calculated. -//! -//! \note The first bank of SRAM is reserved and always enabled. -//! -//! \return true if banks were set, false otherwise. If the BNKEN_RDY bit is -//! not set in the STAT register, this function will return false. -// -//***************************************************************************** -extern bool SysCtl_A_enableSRAM(uint32_t addr); - -//***************************************************************************** -// -//! Disables areas of SRAM memory. This can be used to optimize power -//! consumption when every SRAM bank isn't needed. It is important to note -//! that when a higher bank is disabled, all of the SRAM banks above that bank -//! are also disabled. For example, if the address of 0x2001FA0 is given, all -//! SRAM banks from 0x2001FA0 to the top of SRAM will be disabled. -//! This function takes in a 32-bit address to the area in SRAM to to disable. -//! It will convert this address into the corresponding register settings and -//! set them in the register accordingly. Note that passing an address to an -//! area other than SRAM will result in unreliable behavior. Addresses should -//! be given with reference to the SRAM_DATA area of SRAM (usually starting at -//! 0x20000000). -//! -//! \param addr Break address of SRAM to disable. All SRAM above this address -//! will also be disabled. If an unaligned address is given the appropriate -//! aligned address will be calculated. -//! -//! \note The first bank of SRAM is reserved and always enabled. -//! -//! \return true if banks were set, false otherwise. If the BNKEN_RDY bit is -//! not set in the STAT register, this function will return false. -// -//***************************************************************************** -extern bool SysCtl_A_disableSRAM(uint32_t addr); - -//***************************************************************************** -// -//! Enables retention of the specified SRAM block address range when the device -//! goes into LPM3 mode. When the system is placed in LPM3 mode, the SRAM -//! banks specified with this function will be placed into retention mode. -//! Retention of individual blocks can be set without the restrictions of the -//! enable/disable functions. Note that any memory range given outside of SRAM -//! will result in unreliable behavior. Also note that any unaligned addresses -//! will be truncated to the closest aligned address before the address given. -//! Addresses should be given with reference to the SRAM_DATA area of SRAM -//! (usually starting at 0x20000000). -//! -//! \param startAddr Start address to enable retention -//! -//! \param endtAddr End address to enable retention -//! -//! \note Block 0 is reserved and retention is always enabled. -//! -//! \return true if banks were set, false otherwise. If the BLKEN_RDY bit is -//! not set in the STAT register, this function will return false. -// -//***************************************************************************** -extern bool SysCtl_A_enableSRAMRetention(uint32_t startAddr, - uint32_t endAddr); - -//***************************************************************************** -// -//! Disables retention of the specified SRAM block address range when the device -//! goes into LPM3 mode. When the system is placed in LPM3 mode, the SRAM -//! banks specified with this function will be placed into retention mode. -//! Retention of individual blocks can be set without the restrictions of the -//! enable/disable functions. Note that any memory range given outside of SRAM -//! will result in unreliable behavior. Also note that any unaligned addresses -//! will be truncated to the closest aligned address before the address given. -//! Addresses should be given with reference to the SRAM_DATA area of SRAM -//! (usually starting at 0x20000000). -//! -//! \param startAddr Start address to disable retention -//! -//! \param endtAddr End address to disable retention -//! -//! \note Block 0 is reserved and retention is always enabled. -//! -//! \return true if banks were set, false otherwise. If the BLKEN_RDY bit is -//! not set in the STAT register, this function will return false. -// -//***************************************************************************** -extern bool SysCtl_A_disableSRAMRetention(uint32_t startAddr, - uint32_t endAddr); - -//***************************************************************************** -// -//! Makes it so that the provided peripherals will either halt execution after -//! a CPU HALT. Parameters in this function can be combined to account for -//! multiple peripherals. By default, all peripherals keep running after a -//! CPU HALT. -//! -//! \param devices The peripherals to continue running after a CPU HALT -//! This can be a bitwise OR of the following values: -//! - \b SYSCTL_A_PERIPH_LCD, -//! - \b SYSCTL_A_PERIPH_DMA, -//! - \b SYSCTL_A_PERIPH_WDT, -//! - \b SYSCTL_A_PERIPH_ADC, -//! - \b SYSCTL_A_PERIPH_EUSCIB3, -//! - \b SYSCTL_A_PERIPH_EUSCIB2, -//! - \b SYSCTL_A_PERIPH_EUSCIB1 -//! - \b SYSCTL_A_PERIPH_EUSCIB0, -//! - \b SYSCTL_A_PERIPH_EUSCIA3, -//! - \b SYSCTL_A_PERIPH_EUSCIA2 -//! - \b SYSCTL_A_PERIPH_EUSCIA1, -//! - \b SYSCTL_A_PERIPH_EUSCIA0, -//! - \b SYSCTL_A_PERIPH_TIMER32_0_MODULE, -//! - \b SYSCTL_A_PERIPH_TIMER16_3, -//! - \b SYSCTL_A_PERIPH_TIMER16_2, -//! - \b SYSCTL_A_PERIPH_TIMER16_1, -//! - \b SYSCTL_A_PERIPH_TIMER16_0 -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_A_enablePeripheralAtCPUHalt(uint_fast16_t devices); - -//***************************************************************************** -// -//! Makes it so that the provided peripherals will either halt execution after -//! a CPU HALT. Parameters in this function can be combined to account for -//! multiple peripherals. By default, all peripherals keep running after a -//! CPU HALT. -//! -//! \param devices The peripherals to disable after a CPU HALT -//! -//! The \e devices parameter can be a bitwise OR of the following values: -//! This can be a bitwise OR of the following values: -//! - \b SYSCTL_A_PERIPH_LCD, -//! - \b SYSCTL_A_PERIPH_DMA, -//! - \b SYSCTL_A_PERIPH_WDT, -//! - \b SYSCTL_A_PERIPH_ADC, -//! - \b SYSCTL_A_PERIPH_EUSCIB3, -//! - \b SYSCTL_A_PERIPH_EUSCIB2, -//! - \b SYSCTL_A_PERIPH_EUSCIB1 -//! - \b SYSCTL_A_PERIPH_EUSCIB0, -//! - \b SYSCTL_A_PERIPH_EUSCIA3, -//! - \b SYSCTL_A_PERIPH_EUSCIA2 -//! - \b SYSCTL_A_PERIPH_EUSCIA1, -//! - \b SYSCTL_A_PERIPH_EUSCIA0, -//! - \b SYSCTL_A_PERIPH_TIMER32_0_MODULE, -//! - \b SYSCTL_A_PERIPH_TIMER16_3, -//! - \b SYSCTL_A_PERIPH_TIMER16_2, -//! - \b SYSCTL_A_PERIPH_TIMER16_1, -//! - \b SYSCTL_A_PERIPH_TIMER16_0 -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_A_disablePeripheralAtCPUHalt(uint_fast16_t devices); - -//***************************************************************************** -// -//! Sets the type of RESET that happens when a watchdog timeout occurs. -//! -//! \param resetType The type of reset to set -//! -//! The \e resetType parameter must be only one of the following values: -//! - \b SYSCTL_A_HARD_RESET, -//! - \b SYSCTL_A_SOFT_RESET -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_A_setWDTTimeoutResetType(uint_fast8_t resetType); - -//***************************************************************************** -// -//! Sets the type of RESET that happens when a watchdog password violation -//! occurs. -//! -//! \param resetType The type of reset to set -//! -//! The \e resetType parameter must be only one of the following values: -//! - \b SYSCTL_A_HARD_RESET, -//! - \b SYSCTL_A_SOFT_RESET -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_A_setWDTPasswordViolationResetType(uint_fast8_t resetType); - -//***************************************************************************** -// -//! Disables NMIs for the provided modules. When disabled, a NMI flag will not -//! occur when a fault condition comes from the corresponding modules. -//! -//! \param flags The NMI sources to disable -//! Can be a bitwise OR of the following parameters: -//! - \b SYSCTL_A_NMIPIN_SRC, -//! - \b SYSCTL_A_PCM_SRC, -//! - \b SYSCTL_A_PSS_SRC, -//! - \b SYSCTL_A_CS_SRC -//! -// -//***************************************************************************** -extern void SysCtl_A_disableNMISource(uint_fast8_t flags); - -//***************************************************************************** -// -//! Enables NMIs for the provided modules. When enabled, a NMI flag will -//! occur when a fault condition comes from the corresponding modules. -//! -//! \param flags The NMI sources to enable -//! Can be a bitwise OR of the following parameters: -//! - \b SYSCTL_A_NMIPIN_SRC, -//! - \b SYSCTL_A_PCM_SRC, -//! - \b SYSCTL_A_PSS_SRC, -//! - \b SYSCTL_A_CS_SRC -//! -// -//***************************************************************************** -extern void SysCtl_A_enableNMISource(uint_fast8_t flags); - -//***************************************************************************** -// -//! Returns the current sources of NMIs that are enabled -//! -//! \return NMI source status -// -//***************************************************************************** -extern uint_fast8_t SysCtl_A_getNMISourceStatus(void); - -//***************************************************************************** -// -//! Enables glitch suppression on the reset pin of the device. Refer to the -//! device data sheet for specific information about glitch suppression -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_A_enableGlitchFilter(void); - -//***************************************************************************** -// -//! Disables glitch suppression on the reset pin of the device. Refer to the -//! device data sheet for specific information about glitch suppression -//! -//! \return None. -// -// -//***************************************************************************** -extern void SysCtl_A_disableGlitchFilter(void); - -//***************************************************************************** -// -//! Retrieves the calibration constant of the temperature sensor to be used -//! in temperature calculation. -//! -//! \param refVoltage Reference voltage being used. -//! -//! The \e refVoltage parameter must be only one of the following values: -//! - \b SYSCTL_A_1_2V_REF -//! - \b SYSCTL_A_1_45V_REF -//! - \b SYSCTL_A_2_5V_REF -//! -//! \param temperature is the calibration temperature that the user wants to be -//! returned. -//! -//! The \e temperature parameter must be only one of the following values: -//! - \b SYSCTL_A_30_DEGREES_C -//! - \b SYSCTL_A_85_DEGREES_C -//! -//! \return None. -// -// -//***************************************************************************** -extern uint_fast16_t SysCtl_A_getTempCalibrationConstant(uint32_t refVoltage, - uint32_t temperature); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* __MCU_HAS_SYSCTL_A__ */ - -#endif // __SYSCTL_A_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/systick.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/systick.c deleted file mode 100644 index b1d65344e62..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/systick.c +++ /dev/null @@ -1,113 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include - -void SysTick_enableModule(void) -{ - // - // Enable SysTick. - // - SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; -} - -void SysTick_disableModule(void) -{ - // - // Disable SysTick. - // - SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk); -} - -void SysTick_registerInterrupt(void (*intHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - Interrupt_registerInterrupt(FAULT_SYSTICK, intHandler); - -} - -void SysTick_unregisterInterrupt(void) -{ - - // - // Unregister the interrupt handler. - // - Interrupt_unregisterInterrupt(FAULT_SYSTICK); -} - -void SysTick_enableInterrupt(void) -{ - // - // Enable the SysTick interrupt. - // - SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; -} - -void SysTick_disableInterrupt(void) -{ - // - // Disable the SysTick interrupt. - // - SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk); -} - -void SysTick_setPeriod(uint32_t period) -{ - // - // Check the arguments. - // - ASSERT((period > 0) && (period <= 16777216)); - - // - // Set the period of the SysTick counter. - // - SysTick->LOAD = period - 1; -} - -uint32_t SysTick_getPeriod(void) -{ - // - // Return the period of the SysTick counter. - // - return (SysTick->LOAD + 1); -} - -uint32_t SysTick_getValue(void) -{ - // - // Return the current value of the SysTick counter. - // - return (SysTick->VAL); -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/systick.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/systick.h deleted file mode 100644 index 5f3f8cb1e5a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/systick.h +++ /dev/null @@ -1,214 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -//***************************************************************************** -// -//! \addtogroup systick_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif -#include - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! Enables the SysTick counter. -//! -//! This function starts the SysTick counter. If an interrupt handler has been -//! registered, it is called when the SysTick counter rolls over. -//! -//! \note Calling this function causes the SysTick counter to (re)commence -//! counting from its current value. The counter is not automatically reloaded -//! with the period as specified in a previous call to SysTick_setPeriod(). If -//! an immediate reload is required, the \b NVIC_ST_CURRENT register must be -//! written to force the reload. Any write to this register clears the SysTick -//! counter to 0 and causes a reload with the supplied period on the next -//! clock. -//! -//! \return None. -// -//***************************************************************************** -extern void SysTick_enableModule(void); - -//***************************************************************************** -// -//! Disables the SysTick counter. -//! -//! This function stops the SysTick counter. If an interrupt handler has been -//! registered, it is not called until SysTick is restarted. -//! -//! \return None. -// -//***************************************************************************** -extern void SysTick_disableModule(void); - -//***************************************************************************** -// -//! Registers an interrupt handler for the SysTick interrupt. -//! -//! \param intHandler is a pointer to the function to be called when the -//! SysTick interrupt occurs. -//! -//! This function registers the handler to be called when a SysTick interrupt -//! occurs. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void SysTick_registerInterrupt(void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the SysTick interrupt. -//! -//! This function unregisters the handler to be called when a SysTick interrupt -//! occurs. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void SysTick_unregisterInterrupt(void); - -//***************************************************************************** -// -//! Enables the SysTick interrupt. -//! -//! This function enables the SysTick interrupt, allowing it to be -//! reflected to the processor. -//! -//! \note The SysTick interrupt handler is not required to clear the SysTick -//! interrupt source because it is cleared automatically by the NVIC when the -//! interrupt handler is called. -//! -//! \return None. -// -//***************************************************************************** -extern void SysTick_enableInterrupt(void); - -//***************************************************************************** -// -//! Disables the SysTick interrupt. -//! -//! This function disables the SysTick interrupt, preventing it from being -//! reflected to the processor. -//! -//! \return None. -// -//***************************************************************************** -extern void SysTick_disableInterrupt(void); - -//***************************************************************************** -// -//! Sets the period of the SysTick counter. -//! -//! \param period is the number of clock ticks in each period of the SysTick -//! counter and must be between 1 and 16,777,216, inclusive. -//! -//! This function sets the rate at which the SysTick counter wraps, which -//! equates to the number of processor clocks between interrupts. -//! -//! \note Calling this function does not cause the SysTick counter to reload -//! immediately. If an immediate reload is required, the \b NVIC_ST_CURRENT -//! register must be written. Any write to this register clears the SysTick -//! counter to 0 and causes a reload with the \e period supplied here on -//! the next clock after SysTick is enabled. -//! -//! \return None. -// -//***************************************************************************** -extern void SysTick_setPeriod(uint32_t period); - -//***************************************************************************** -// -//! Gets the period of the SysTick counter. -//! -//! This function returns the rate at which the SysTick counter wraps, which -//! equates to the number of processor clocks between interrupts. -//! -//! \return Returns the period of the SysTick counter. -// -//***************************************************************************** -extern uint32_t SysTick_getPeriod(void); - -//***************************************************************************** -// -//! Gets the current value of the SysTick counter. -//! -//! This function returns the current value of the SysTick counter, which is -//! a value between the period - 1 and zero, inclusive. -//! -//! \return Returns the current value of the SysTick counter. -// -//***************************************************************************** -extern uint32_t SysTick_getValue(void); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif // __SYSTICK_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/timer32.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/timer32.c deleted file mode 100644 index 210868adf17..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/timer32.c +++ /dev/null @@ -1,146 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include - -void Timer32_initModule(uint32_t timer, uint32_t preScaler, uint32_t resolution, - uint32_t mode) -{ - /* Setting up one shot or continuous mode */ - if (mode == TIMER32_PERIODIC_MODE) - BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS) - = 1; - else if (mode == TIMER32_FREE_RUN_MODE) - BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_MODE_OFS) - = 0; - else - ASSERT(false); - - /* Setting the resolution of the timer */ - if (resolution == TIMER32_16BIT) - BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS) - = 0; - else if (resolution == TIMER32_32BIT) - BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS) - = 1; - else - ASSERT(false); - - /* Setting the PreScaler */ - ASSERT( - resolution == TIMER32_PRESCALER_1 - || resolution == TIMER32_PRESCALER_16 - || resolution == TIMER32_PRESCALER_256); - - TIMER32_CMSIS(timer)->CONTROL = TIMER32_CMSIS(timer)->CONTROL - & (~TIMER32_CONTROL_PRESCALE_MASK) | preScaler; - -} - -void Timer32_setCount(uint32_t timer, uint32_t count) -{ - if (!BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS) - && (count > UINT16_MAX)) - TIMER32_CMSIS(timer)->LOAD = UINT16_MAX; - else - TIMER32_CMSIS(timer)->LOAD = count; -} - -void Timer32_setCountInBackground(uint32_t timer, uint32_t count) -{ - if (!BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_SIZE_OFS) - && (count > UINT16_MAX)) - TIMER32_CMSIS(timer)->BGLOAD = UINT16_MAX; - else - TIMER32_CMSIS(timer)->BGLOAD = count; -} - -uint32_t Timer32_getValue(uint32_t timer) -{ - return TIMER32_CMSIS(timer)->VALUE; -} - -void Timer32_startTimer(uint32_t timer, bool oneShot) -{ - ASSERT(timer == TIMER32_0_BASE || timer == TIMER32_1_BASE); - - if (oneShot) - BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_ONESHOT_OFS) - = 1; - else - BITBAND_PERI(TIMER32_CMSIS(timer)->CONTROL, TIMER32_CONTROL_ONESHOT_OFS) - = 0; - - TIMER32_CMSIS(timer)->CONTROL |= TIMER32_CONTROL_ENABLE; -} - -void Timer32_haltTimer(uint32_t timer) -{ - ASSERT(timer == TIMER32_0_BASE || timer == TIMER32_1_BASE); - - TIMER32_CMSIS(timer)->CONTROL &= ~TIMER32_CONTROL_ENABLE; -} - -void Timer32_enableInterrupt(uint32_t timer) -{ - TIMER32_CMSIS(timer)->CONTROL |= TIMER32_CONTROL_IE; -} - -void Timer32_disableInterrupt(uint32_t timer) -{ - TIMER32_CMSIS(timer)->CONTROL &= ~TIMER32_CONTROL_IE; -} - -void Timer32_clearInterruptFlag(uint32_t timer) -{ - TIMER32_CMSIS(timer)->INTCLR |= 0x01; -} - -uint32_t Timer32_getInterruptStatus(uint32_t timer) -{ - return TIMER32_CMSIS(timer)->MIS; -} - -void Timer32_registerInterrupt(uint32_t timerInterrupt, - void (*intHandler)(void)) -{ - Interrupt_registerInterrupt(timerInterrupt, intHandler); - Interrupt_enableInterrupt(timerInterrupt); -} - -void Timer32_unregisterInterrupt(uint32_t timerInterrupt) -{ - Interrupt_disableInterrupt(timerInterrupt); - Interrupt_unregisterInterrupt(timerInterrupt); -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/timer32.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/timer32.h deleted file mode 100644 index 3b449cea42b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/timer32.h +++ /dev/null @@ -1,356 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef TIMER32_H_ -#define TIMER32_H_ - -//***************************************************************************** -// -//! \addtogroup timer32_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif -#include -#include -#include - -//***************************************************************************** -// -// Control specific variables -// -//***************************************************************************** -#define TIMER32_CMSIS(x) ((Timer32_Type *) x) - -#define TIMER_OFFSET 0x020 - -#define TIMER32_0_BASE (uint32_t)TIMER32_1 -#define TIMER32_1_BASE (uint32_t)TIMER32_2 - -#define TIMER32_0_INTERRUPT INT_T32_INT1 -#define TIMER32_1_INTERRUPT INT_T32_INT2 -#define TIMER32_COMBINED_INTERRUPT INT_T32_INTC - -#define TIMER32_16BIT 0x00 -#define TIMER32_32BIT 0x01 - -#define TIMER32_PRESCALER_1 0x00 -#define TIMER32_PRESCALER_16 0x04 -#define TIMER32_PRESCALER_256 0x08 - -#define TIMER32_FREE_RUN_MODE 0x00 -#define TIMER32_PERIODIC_MODE 0x01 - -//***************************************************************************** -// -// API Function prototypes -// -//***************************************************************************** - -//***************************************************************************** -// -//! Initializes the Timer32 module -//! -//! \param timer is the instance of the Timer32 module. -//! Valid parameters must be one of the following values: -//! - \b TIMER32_0_BASE -//! - \b TIMER32_1_BASE -//! -//! \param preScaler is the prescaler (or divider) to apply to the clock -//! source given to the Timer32 module. -//! Valid values are -//! - \b TIMER32_PRESCALER_1 [DEFAULT] -//! - \b TIMER32_PRESCALER_16 -//! - \b TIMER32_PRESCALER_256 -//! \param resolution is the bit resolution of the Timer32 module. -//! Valid values are -//! - \b TIMER32_16BIT [DEFAULT] -//! - \b TIMER32_32BIT -//! \param mode selects between free run and periodic mode. In free run -//! mode, the value of the timer is reset to UINT16_MAX (for 16-bit mode) or -//! UINT32_MAX (for 16-bit mode) when the timer reaches zero. In periodic mode, -//! the timer is reset to the value set by the Timer32_setCount function. -//! Valid values are -//! - \b TIMER32_FREE_RUN_MODE [DEFAULT] -//! - \b TIMER32_PERIODIC_MODE -//! -//! -//! \return None. -// -//***************************************************************************** -extern void Timer32_initModule(uint32_t timer, uint32_t preScaler, - uint32_t resolution, uint32_t mode); - -//***************************************************************************** -// -//! Sets the count of the timer and resets the current value to the value -//! passed. This value is set on the next rising edge of the clock provided to -//! the timer module -//! -//! \param timer is the instance of the Timer32 module. -//! Valid parameters must be one of the following values: -//! - \b TIMER32_0_BASE -//! - \b TIMER32_1_BASE -//! \param count Value of the timer to set. Note that -//! if the timer is in 16-bit mode and a value is passed in that exceeds -//! UINT16_MAX, the value will be truncated to UINT16_MAX. -//! -//! Also note that if the timer is operating in periodic mode, the value passed -//! into this function will represent the new period of the timer (the value -//! which is reloaded into the timer each time it reaches a zero value). -//! -//! \return None -// -//***************************************************************************** -extern void Timer32_setCount(uint32_t timer, uint32_t count); - -//***************************************************************************** -// -//! Sets the count of the timer without resetting the current value. When the -//! current value of the timer reaches zero, the value passed into this function -//! will be set as the new count value. -//! -//! \param timer is the instance of the Timer32 module. -//! Valid parameters must be one of the following values: -//! - \b TIMER32_0_BASE -//! - \b TIMER32_1_BASE -//! \param count Value of the timer to set in the background. Note that -//! if the timer is in 16-bit mode and a value is passed in that exceeds -//! UINT16_MAX, the value will be truncated to UINT16_MAX. -//! -//! Also note that if the timer is operating in periodic mode, the value passed -//! into this function will represent the new period of the timer (the value -//! which is reloaded into the timer each time it reaches a zero value). -//! -//! \return None -// -//***************************************************************************** -extern void Timer32_setCountInBackground(uint32_t timer, uint32_t count); - -//***************************************************************************** -// -//! Returns the current value of the timer. -//! -//! \param timer is the instance of the Timer32 module. -//! Valid parameters must be one of the following values: -//! - \b TIMER32_0_BASE -//! - \b TIMER32_1_BASE -//! -//! \return The current count of the timer. -// -//***************************************************************************** -extern uint32_t Timer32_getValue(uint32_t timer); - -//***************************************************************************** -// -//! Starts the timer. The Timer32_initModule function should be called (in -//! conjunction with Timer32_setCount if periodic mode is desired) prior to -// starting the timer. -//! -//! \param timer is the instance of the Timer32 module. -//! Valid parameters must be one of the following values: -//! - \b TIMER32_0_BASE -//! - \b TIMER32_1_BASE -//! -//! \param oneShot sets whether the Timer32 module operates in one shot -//! or continuous mode. In one shot mode, the timer will halt when a zero is -//! reached and stay halted until either: -//! - The user calls the Timer32PeriodSet function -//! - The Timer32_initModule is called to reinitialize the timer with one-shot -//! mode disabled. -//! -//! A true value will cause the timer to operate in one shot mode while a false -//! value will cause the timer to operate in continuous mode -//! -//! \return None -// -//***************************************************************************** -extern void Timer32_startTimer(uint32_t timer, bool oneShot); - -//***************************************************************************** -// -//! Halts the timer. Current count and setting values are preserved. -//! -//! \param timer is the instance of the Timer32 module. -//! Valid parameters must be one of the following values: -//! - \b TIMER32_0_BASE -//! - \b TIMER32_1_BASE -//! -//! \return None -// -//***************************************************************************** -extern void Timer32_haltTimer(uint32_t timer); - -//***************************************************************************** -// -//! Enables a Timer32 interrupt source. -//! -//! \param timer is the instance of the Timer32 module. -//! Valid parameters must be one of the following values: -//! - \b TIMER32_0_BASE -//! - \b TIMER32_1_BASE -//! -//! Enables the indicated Timer32 interrupt source. -//! -//! \return None. -// -//***************************************************************************** -extern void Timer32_enableInterrupt(uint32_t timer); - -//***************************************************************************** -// -//! Disables a Timer32 interrupt source. -//! -//! \param timer is the instance of the Timer32 module. -//! Valid parameters must be one of the following values: -//! - \b TIMER32_0_BASE -//! - \b TIMER32_1_BASE -//! -//! Disables the indicated Timer32 interrupt source. -//! -//! \return None. -// -//***************************************************************************** -extern void Timer32_disableInterrupt(uint32_t timer); - -//***************************************************************************** -// -//! Clears Timer32 interrupt source. -//! -//! \param timer is the instance of the Timer32 module. -//! Valid parameters must be one of the following values: -//! - \b TIMER32_0_BASE -//! - \b TIMER32_1_BASE -//! -//! The Timer32 interrupt source is cleared, so that it no longer asserts. -//! -//! \return None. -// -//***************************************************************************** -extern void Timer32_clearInterruptFlag(uint32_t timer); - -//***************************************************************************** -// -//! Gets the current Timer32 interrupt status. -//! -//! \param timer is the instance of the Timer32 module. -//! Valid parameters must be one of the following values: -//! - \b TIMER32_0_BASE -//! - \b TIMER32_1_BASE -//! -//! This returns the interrupt status for the Timer32 module. A positive value -//! will indicate that an interrupt is pending while a zero value will indicate -//! that no interrupt is pending. -//! -//! \return The current interrupt status -// -//***************************************************************************** -extern uint32_t Timer32_getInterruptStatus(uint32_t timer); - -//***************************************************************************** -// -//! Registers an interrupt handler for Timer32 interrupts. -//! -//! \param timerInterrupt is the specific interrupt to register. For the -//! Timer32 module, there are a total of three different interrupts: one -//! interrupt for each two Timer32 modules, and a "combined" interrupt which -//! is a logical OR of each individual Timer32 interrupt. -//! - \b TIMER32_0_INTERRUPT -//! - \b TIMER32_1_INTERRUPT -//! - \b TIMER32_COMBINED_INTERRUPT -//! -//! \param intHandler is a pointer to the function to be called when the -//! Timer32 interrupt occurs. -//! -//! This function registers the handler to be called when an Timer32 -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific Timer32 interrupts must be enabled -//! via Timer32_enableInterrupt(). It is the interrupt handler's -//! responsibility to clear the interrupt source -//! via Timer32_clearInterruptFlag(). -//! -//! \return None. -// -//***************************************************************************** -extern void Timer32_registerInterrupt(uint32_t timerInterrupt, - void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the Timer32 interrupt. -//! -//! \param timerInterrupt is the specific interrupt to register. For the -//! Timer32 module, there are a total of three different interrupts: one -//! interrupt for each two Timer32 modules, and a "combined" interrupt which -//! is a logical OR of each individual Timer32 interrupt. -//! - \b TIMER32_0_INTERRUPT -//! - \b TIMER32_1_INTERRUPT -//! - \b TIMER32_COMBINED_INTERRUPT -//! -//! This function unregisters the handler to be called when a Timer32 -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void Timer32_unregisterInterrupt(uint32_t timerInterrupt); - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* TIMER32_H_ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/timer_a.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/timer_a.c deleted file mode 100644 index 0288599b780..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/timer_a.c +++ /dev/null @@ -1,807 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include - -static void privateTimer_AProcessClockSourceDivider(uint32_t timer, - uint16_t clockSourceDivider) -{ - TIMER_A_CMSIS(timer)->CTL &= ~TIMER_A_CTL_ID__8; - TIMER_A_CMSIS(timer)->EX0 &= ~TIMER_A_EX0_IDEX_MASK; - - switch (clockSourceDivider) - { - case TIMER_A_CLOCKSOURCE_DIVIDER_1: - case TIMER_A_CLOCKSOURCE_DIVIDER_2: - TIMER_A_CMSIS(timer)->CTL |= ((clockSourceDivider - 1) << 6); - TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0; - break; - case TIMER_A_CLOCKSOURCE_DIVIDER_4: - TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__4; - TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0; - break; - case TIMER_A_CLOCKSOURCE_DIVIDER_8: - TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__8; - TIMER_A_CMSIS(timer)->EX0 = TIMER_A_EX0_TAIDEX_0; - break; - case TIMER_A_CLOCKSOURCE_DIVIDER_3: - case TIMER_A_CLOCKSOURCE_DIVIDER_5: - case TIMER_A_CLOCKSOURCE_DIVIDER_6: - case TIMER_A_CLOCKSOURCE_DIVIDER_7: - TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__1; - TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider - 1); - break; - - case TIMER_A_CLOCKSOURCE_DIVIDER_10: - case TIMER_A_CLOCKSOURCE_DIVIDER_12: - case TIMER_A_CLOCKSOURCE_DIVIDER_14: - case TIMER_A_CLOCKSOURCE_DIVIDER_16: - TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__2; - TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 2 - 1); - break; - - case TIMER_A_CLOCKSOURCE_DIVIDER_20: - case TIMER_A_CLOCKSOURCE_DIVIDER_24: - case TIMER_A_CLOCKSOURCE_DIVIDER_28: - case TIMER_A_CLOCKSOURCE_DIVIDER_32: - TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__4; - TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 4 - 1); - break; - case TIMER_A_CLOCKSOURCE_DIVIDER_40: - case TIMER_A_CLOCKSOURCE_DIVIDER_48: - case TIMER_A_CLOCKSOURCE_DIVIDER_56: - case TIMER_A_CLOCKSOURCE_DIVIDER_64: - TIMER_A_CMSIS(timer)->CTL |= TIMER_A_CTL_ID__8; - TIMER_A_CMSIS(timer)->EX0 = (clockSourceDivider / 8 - 1); - break; - } -} - -void Timer_A_startCounter(uint32_t timer, uint_fast16_t timerMode) -{ - ASSERT( - (TIMER_A_UPDOWN_MODE == timerMode) - || (TIMER_A_CONTINUOUS_MODE == timerMode) - || (TIMER_A_UP_MODE == timerMode)); - - TIMER_A_CMSIS(timer)->CTL |= timerMode; -} - -void Timer_A_configureContinuousMode(uint32_t timer, - const Timer_A_ContinuousModeConfig *config) -{ - ASSERT( - (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource) - || (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource) - || (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource) - || (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK - == config->clockSource)); - - ASSERT( - (TIMER_A_DO_CLEAR == config->timerClear) - || (TIMER_A_SKIP_CLEAR == config->timerClear)); - - ASSERT( - (TIMER_A_TAIE_INTERRUPT_ENABLE == config->timerInterruptEnable_TAIE) - || (TIMER_A_TAIE_INTERRUPT_DISABLE - == config->timerInterruptEnable_TAIE)); - - ASSERT( - (TIMER_A_CLOCKSOURCE_DIVIDER_1 == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_2 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_4 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_8 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_3 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_5 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_6 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_7 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_10 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_12 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_14 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_16 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_20 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_24 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_28 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_32 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_40 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_48 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_56 - == config->clockSourceDivider) - || (TIMER_A_CLOCKSOURCE_DIVIDER_64 - == config->clockSourceDivider)); - - privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider); - - TIMER_A_CMSIS(timer)->CTL = (TIMER_A_CMSIS(timer)->CTL - & ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK - + TIMER_A_UPDOWN_MODE + TIMER_A_DO_CLEAR - + TIMER_A_TAIE_INTERRUPT_ENABLE)) - | (config->clockSource + config->timerClear - + config->timerInterruptEnable_TAIE); -} - -void Timer_A_configureUpMode(uint32_t timer, const Timer_A_UpModeConfig *config) -{ - ASSERT( - (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource) - || (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource) - || (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource) - || (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK - == config->clockSource)); - - ASSERT( - (TIMER_A_DO_CLEAR == config->timerClear) - || (TIMER_A_SKIP_CLEAR == config->timerClear)); - - ASSERT( - (TIMER_A_DO_CLEAR == config->timerClear) - || (TIMER_A_SKIP_CLEAR == config->timerClear)); - - privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider); - - TIMER_A_CMSIS(timer)->CTL &= - ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE - + TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE); - - TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + config->timerClear - + config->timerInterruptEnable_TAIE); - - if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE - == config->captureCompareInterruptEnable_CCR0_CCIE) - BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 1; - else - BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 0; - - TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod; -} - -void Timer_A_configureUpDownMode(uint32_t timer, - const Timer_A_UpDownModeConfig *config) -{ - ASSERT( - (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource) - || (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource) - || (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource) - || (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK - == config->clockSource)); - - ASSERT( - (TIMER_A_DO_CLEAR == config->timerClear) - || (TIMER_A_SKIP_CLEAR == config->timerClear)); - - ASSERT( - (TIMER_A_DO_CLEAR == config->timerClear) - || (TIMER_A_SKIP_CLEAR == config->timerClear)); - - privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider); - - TIMER_A_CMSIS(timer)->CTL &= - ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE - + TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE); - - TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + TIMER_A_STOP_MODE - + config->timerClear + config->timerInterruptEnable_TAIE); - if (TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE - == config->captureCompareInterruptEnable_CCR0_CCIE) - BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 1; - else - BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[0],TIMER_A_CCTLN_CCIE_OFS) = 0; - - TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod; -} - -void Timer_A_initCapture(uint32_t timer, - const Timer_A_CaptureModeConfig *config) -{ - ASSERT( - (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->captureRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_1 - == config->captureRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_2 - == config->captureRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_3 - == config->captureRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_4 - == config->captureRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_5 - == config->captureRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_6 - == config->captureRegister)); - - ASSERT( - (TIMER_A_CAPTUREMODE_NO_CAPTURE == config->captureMode) - || (TIMER_A_CAPTUREMODE_RISING_EDGE == config->captureMode) - || (TIMER_A_CAPTUREMODE_FALLING_EDGE == config->captureMode) - || (TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE - == config->captureMode)); - - ASSERT( - (TIMER_A_CAPTURE_INPUTSELECT_CCIxA == config->captureInputSelect) - || (TIMER_A_CAPTURE_INPUTSELECT_CCIxB - == config->captureInputSelect) - || (TIMER_A_CAPTURE_INPUTSELECT_GND - == config->captureInputSelect) - || (TIMER_A_CAPTURE_INPUTSELECT_Vcc - == config->captureInputSelect)); - - ASSERT( - (TIMER_A_CAPTURE_ASYNCHRONOUS == config->synchronizeCaptureSource) - || (TIMER_A_CAPTURE_SYNCHRONOUS - == config->synchronizeCaptureSource)); - - ASSERT( - (TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE - == config->captureInterruptEnable) - || (TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE - == config->captureInterruptEnable)); - - ASSERT( - (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->captureOutputMode) - || (TIMER_A_OUTPUTMODE_SET == config->captureOutputMode) - || (TIMER_A_OUTPUTMODE_TOGGLE_RESET - == config->captureOutputMode) - || (TIMER_A_OUTPUTMODE_SET_RESET - == config->captureOutputMode) - || (TIMER_A_OUTPUTMODE_TOGGLE == config->captureOutputMode) - || (TIMER_A_OUTPUTMODE_RESET == config->captureOutputMode) - || (TIMER_A_OUTPUTMODE_TOGGLE_SET - == config->captureOutputMode) - || (TIMER_A_OUTPUTMODE_RESET_SET - == config->captureOutputMode)); - - if (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->captureRegister) - { - //CaptureCompare register 0 only supports certain modes - ASSERT( - (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->captureOutputMode) - || (TIMER_A_OUTPUTMODE_SET == config->captureOutputMode) - || (TIMER_A_OUTPUTMODE_TOGGLE - == config->captureOutputMode) - || (TIMER_A_OUTPUTMODE_RESET - == config->captureOutputMode)); - } - uint8_t idx = (config->captureRegister>>1)-1; - TIMER_A_CMSIS(timer)->CCTL[idx] = - (TIMER_A_CMSIS(timer)->CCTL[idx] - & ~(TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE - | TIMER_A_CAPTURE_INPUTSELECT_Vcc - | TIMER_A_CAPTURE_SYNCHRONOUS | TIMER_A_DO_CLEAR - | TIMER_A_TAIE_INTERRUPT_ENABLE | TIMER_A_CCTLN_CM_3)) - | (config->captureMode | config->captureInputSelect - | config->synchronizeCaptureSource - | config->captureInterruptEnable - | config->captureOutputMode | TIMER_A_CCTLN_CAP); - -} - -void Timer_A_initCompare(uint32_t timer, - const Timer_A_CompareModeConfig *config) -{ - ASSERT( - (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_1 - == config->compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_2 - == config->compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_3 - == config->compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_4 - == config->compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_5 - == config->compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_6 - == config->compareRegister)); - - ASSERT( - (TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE - == config->compareInterruptEnable) - || (TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE - == config->compareInterruptEnable)); - - ASSERT( - (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_TOGGLE_RESET - == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_SET_RESET - == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_TOGGLE == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_RESET == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_TOGGLE_SET - == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_RESET_SET - == config->compareOutputMode)); - - if (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister) - { - //CaptureCompare register 0 only supports certain modes - ASSERT( - (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_TOGGLE - == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_RESET - == config->compareOutputMode)); - } - - uint8_t idx = (config->compareRegister>>1)-1; - TIMER_A_CMSIS(timer)->CCTL[idx] = - (TIMER_A_CMSIS(timer)->CCTL[idx] - & ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE - | TIMER_A_OUTPUTMODE_RESET_SET | TIMER_A_CCTLN_CAP)) - | (config->compareInterruptEnable + config->compareOutputMode); - - TIMER_A_CMSIS(timer)->CCR[idx] = config->compareValue; - -} - -uint16_t Timer_A_getCounterValue(uint32_t timer) -{ - uint_fast16_t voteOne, voteTwo, res; - - voteTwo = TIMER_A_CMSIS(timer)->R; - - do - { - voteOne = voteTwo; - voteTwo = TIMER_A_CMSIS(timer)->R; - - if (voteTwo > voteOne) - res = voteTwo - voteOne; - else if (voteOne > voteTwo) - res = voteOne - voteTwo; - else - res = 0; - - } while (res > TIMER_A_THRESHOLD); - - return voteTwo; - -} - -void Timer_A_clearTimer(uint32_t timer) -{ - BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL , TIMER_A_CTL_CLR_OFS) = 1; -} - -uint_fast8_t Timer_A_getSynchronizedCaptureCompareInput(uint32_t timer, - uint_fast16_t captureCompareRegister, uint_fast16_t synchronizedSetting) -{ - ASSERT( - (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_1 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_2 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_3 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_4 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_5 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_6 - == captureCompareRegister)); - - ASSERT( - (TIMER_A_READ_CAPTURE_COMPARE_INPUT == synchronizedSetting) - || (TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT - == synchronizedSetting)); - - uint8_t idx = (captureCompareRegister>>1) - 1; - if (TIMER_A_CMSIS(timer)->CCTL[idx] & synchronizedSetting) - return TIMER_A_CAPTURECOMPARE_INPUT_HIGH; - else - return TIMER_A_CAPTURECOMPARE_INPUT_LOW; -} - -uint_fast8_t Timer_A_getOutputForOutputModeOutBitValue(uint32_t timer, - uint_fast16_t captureCompareRegister) -{ - ASSERT( - (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_1 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_2 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_3 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_4 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_5 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_6 - == captureCompareRegister)); - - uint8_t idx = (captureCompareRegister>>1) - 1; - if (BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_OUT_OFS)) - return TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH; - else - return TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW; -} - -uint_fast16_t Timer_A_getCaptureCompareCount(uint32_t timer, - uint_fast16_t captureCompareRegister) -{ - ASSERT( - (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_1 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_2 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_3 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_4 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_5 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_6 - == captureCompareRegister)); - - uint8_t idx = (captureCompareRegister>>1) - 1; - return (TIMER_A_CMSIS(timer)->CCR[idx]); -} - -void Timer_A_setOutputForOutputModeOutBitValue(uint32_t timer, - uint_fast16_t captureCompareRegister, - uint_fast8_t outputModeOutBitValue) -{ - uint8_t idx = (captureCompareRegister>>1) - 1; - TIMER_A_CMSIS(timer)->CCTL[idx] = - ((TIMER_A_CMSIS(timer)->CCTL[idx]) - & ~(TIMER_A_OUTPUTMODE_RESET_SET)) - | (outputModeOutBitValue); -} - -void Timer_A_generatePWM(uint32_t timer, const Timer_A_PWMConfig *config) -{ - ASSERT( - (TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK == config->clockSource) - || (TIMER_A_CLOCKSOURCE_ACLK == config->clockSource) - || (TIMER_A_CLOCKSOURCE_SMCLK == config->clockSource) - || (TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK - == config->clockSource)); - - ASSERT( - (TIMER_A_CAPTURECOMPARE_REGISTER_0 == config->compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_1 - == config->compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_2 - == config->compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_3 - == config->compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_4 - == config->compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_5 - == config->compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_6 - == config->compareRegister)); - - ASSERT( - (TIMER_A_OUTPUTMODE_OUTBITVALUE == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_SET == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_TOGGLE_RESET - == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_SET_RESET - == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_TOGGLE == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_RESET == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_TOGGLE_SET - == config->compareOutputMode) - || (TIMER_A_OUTPUTMODE_RESET_SET - == config->compareOutputMode)); - - privateTimer_AProcessClockSourceDivider(timer, config->clockSourceDivider); - - TIMER_A_CMSIS(timer)->CTL &= - ~(TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK + TIMER_A_UPDOWN_MODE - + TIMER_A_DO_CLEAR + TIMER_A_TAIE_INTERRUPT_ENABLE); - - TIMER_A_CMSIS(timer)->CTL |= (config->clockSource + TIMER_A_UP_MODE - + TIMER_A_DO_CLEAR); - - TIMER_A_CMSIS(timer)->CCR[0] = config->timerPeriod; - - TIMER_A_CMSIS(timer)->CCTL[0] &= ~(TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE - + TIMER_A_OUTPUTMODE_RESET_SET); - - uint8_t idx = (config->compareRegister>>1) - 1; - TIMER_A_CMSIS(timer)->CCTL[idx] |= config->compareOutputMode; - TIMER_A_CMSIS(timer)->CCR[idx] = config->dutyCycle; -} - -void Timer_A_stopTimer(uint32_t timer) -{ - TIMER_A_CMSIS(timer)->CTL &= ~TIMER_A_CTL_MC_3; -} - -void Timer_A_setCompareValue(uint32_t timer, uint_fast16_t compareRegister, - uint_fast16_t compareValue) -{ - ASSERT( - (TIMER_A_CAPTURECOMPARE_REGISTER_0 == compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_1 == compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_2 == compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_3 == compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_4 == compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_5 == compareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_6 == compareRegister)); - - uint8_t idx = (compareRegister>>1) - 1; - TIMER_A_CMSIS(timer)->CCR[idx] = compareValue; -} - -void Timer_A_clearInterruptFlag(uint32_t timer) -{ - BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IFG_OFS) = 0; -} - -void Timer_A_clearCaptureCompareInterrupt(uint32_t timer, - uint_fast16_t captureCompareRegister) -{ - ASSERT( - (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_1 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_2 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_3 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_4 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_5 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_6 - == captureCompareRegister)); - - uint8_t idx = (captureCompareRegister>>1) - 1; - BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIFG_OFS) = 0; -} - -void Timer_A_enableInterrupt(uint32_t timer) -{ - BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IE_OFS) = 1; -} - -void Timer_A_disableInterrupt(uint32_t timer) -{ - BITBAND_PERI(TIMER_A_CMSIS(timer)->CTL,TIMER_A_CTL_IE_OFS) = 0; -} - -uint32_t Timer_A_getInterruptStatus(uint32_t timer) -{ - return (TIMER_A_CMSIS(timer)->CTL) & TIMER_A_CTL_IFG; -} - -void Timer_A_enableCaptureCompareInterrupt(uint32_t timer, - uint_fast16_t captureCompareRegister) -{ - ASSERT( - (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_1 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_2 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_3 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_4 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_5 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_6 - == captureCompareRegister)); - - uint8_t idx = (captureCompareRegister>>1) - 1; - BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS) = 1; -} - -void Timer_A_disableCaptureCompareInterrupt(uint32_t timer, - uint_fast16_t captureCompareRegister) -{ - ASSERT( - (TIMER_A_CAPTURECOMPARE_REGISTER_0 == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_1 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_2 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_3 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_4 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_5 - == captureCompareRegister) - || (TIMER_A_CAPTURECOMPARE_REGISTER_6 - == captureCompareRegister)); - - uint8_t idx = (captureCompareRegister>>1) - 1; - BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS) = 0; - -} - -uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer, - uint_fast16_t captureCompareRegister, uint_fast16_t mask) -{ - uint8_t idx = (captureCompareRegister>>1) - 1; - return (TIMER_A_CMSIS(timer)->CCTL[idx]) & mask; -} - -uint32_t Timer_A_getEnabledInterruptStatus(uint32_t timer) -{ - if (TIMER_A_CMSIS(timer)->CTL & TIMER_A_CTL_IE) - { - return Timer_A_getInterruptStatus(timer); - } else - { - return 0; - } - -} - -uint32_t Timer_A_getCaptureCompareEnabledInterruptStatus(uint32_t timer, - uint_fast16_t captureCompareRegister) -{ - uint8_t idx = (captureCompareRegister>>1) - 1; - if (BITBAND_PERI(TIMER_A_CMSIS(timer)->CCTL[idx],TIMER_A_CCTLN_CCIE_OFS)) - return Timer_A_getCaptureCompareInterruptStatus(timer, - captureCompareRegister, - TIMER_A_CAPTURE_OVERFLOW | - TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG); - else - return 0; -} - -void Timer_A_registerInterrupt(uint32_t timer, uint_fast8_t interruptSelect, - void (*intHandler)(void)) -{ - if (interruptSelect == TIMER_A_CCR0_INTERRUPT) - { - switch (timer) - { - case TIMER_A0_BASE: - Interrupt_registerInterrupt(INT_TA0_0, intHandler); - Interrupt_enableInterrupt(INT_TA0_0); - break; - case TIMER_A1_BASE: - Interrupt_registerInterrupt(INT_TA1_0, intHandler); - Interrupt_enableInterrupt(INT_TA1_0); - break; - case TIMER_A2_BASE: - Interrupt_registerInterrupt(INT_TA2_0, intHandler); - Interrupt_enableInterrupt(INT_TA2_0); - break; - case TIMER_A3_BASE: - Interrupt_registerInterrupt(INT_TA3_0, intHandler); - Interrupt_enableInterrupt(INT_TA3_0); - break; - default: - ASSERT(false); - } - } else if (interruptSelect == TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT) - { - switch (timer) - { - case TIMER_A0_BASE: - Interrupt_registerInterrupt(INT_TA0_N, intHandler); - Interrupt_enableInterrupt(INT_TA0_N); - break; - case TIMER_A1_BASE: - Interrupt_registerInterrupt(INT_TA1_N, intHandler); - Interrupt_enableInterrupt(INT_TA1_N); - break; - case TIMER_A2_BASE: - Interrupt_registerInterrupt(INT_TA2_N, intHandler); - Interrupt_enableInterrupt(INT_TA2_N); - break; - case TIMER_A3_BASE: - Interrupt_registerInterrupt(INT_TA3_N, intHandler); - Interrupt_enableInterrupt(INT_TA3_N); - break; - default: - ASSERT(false); - } - } else - { - ASSERT(false); - } -} - -void Timer_A_unregisterInterrupt(uint32_t timer, uint_fast8_t interruptSelect) -{ - if (interruptSelect == TIMER_A_CCR0_INTERRUPT) - { - switch (timer) - { - case TIMER_A0_BASE: - Interrupt_disableInterrupt(INT_TA0_0); - Interrupt_unregisterInterrupt(INT_TA0_0); - break; - case TIMER_A1_BASE: - Interrupt_disableInterrupt(INT_TA1_0); - Interrupt_unregisterInterrupt(INT_TA1_0); - break; - case TIMER_A2_BASE: - Interrupt_disableInterrupt(INT_TA2_0); - Interrupt_unregisterInterrupt(INT_TA2_0); - break; - case TIMER_A3_BASE: - Interrupt_disableInterrupt(INT_TA3_0); - Interrupt_unregisterInterrupt(INT_TA3_0); - break; - default: - ASSERT(false); - } - } else if (interruptSelect == TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT) - { - switch (timer) - { - case TIMER_A0_BASE: - Interrupt_disableInterrupt(INT_TA0_N); - Interrupt_unregisterInterrupt(INT_TA0_N); - break; - case TIMER_A1_BASE: - Interrupt_disableInterrupt(INT_TA1_N); - Interrupt_unregisterInterrupt(INT_TA1_N); - break; - case TIMER_A2_BASE: - Interrupt_disableInterrupt(INT_TA2_N); - Interrupt_unregisterInterrupt(INT_TA2_N); - break; - case TIMER_A3_BASE: - Interrupt_disableInterrupt(INT_TA3_N); - Interrupt_unregisterInterrupt(INT_TA3_N); - break; - default: - ASSERT(false); - } - } else - { - ASSERT(false); - } -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/timer_a.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/timer_a.h deleted file mode 100644 index 4a3b735a4c3..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/timer_a.h +++ /dev/null @@ -1,1294 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef TIMERA_H_ -#define TIMERA_H_ - -//***************************************************************************** -// -//! \addtogroup timera_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif -#include -#include -#include - -//***************************************************************************** -// -// Timer_A Specific Parameters -// -//***************************************************************************** -#define TIMER_A_CMSIS(x) ((Timer_A_Type *) x) - -#define TIMER_A_CCR0_INTERRUPT 0x00 -#define TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT 0x01 - -//***************************************************************************** -// -//! ypedef Timer_A_ContinuousModeConfig -//! \brief Type definition for \link _Timer_A_ContinuousModeConfig \endlink -//! structure -//! -//! \struct _Timer_A_ContinuousModeConfig -//! \brief Configuration structure for continuous mode in the \b Timer_A module. -//! See \link Timer_A_configureContinuousMode \endlink for parameter -//! documentation. -// -//***************************************************************************** -typedef struct _Timer_A_ContinuousModeConfig -{ - uint_fast16_t clockSource; - uint_fast16_t clockSourceDivider; - uint_fast16_t timerInterruptEnable_TAIE; - uint_fast16_t timerClear; -} Timer_A_ContinuousModeConfig; - -//***************************************************************************** -// -//! ypedef Timer_A_UpModeConfig -//! \brief Type definition for \link _Timer_A_UpModeConfig \endlink -//! structure -//! -//! \struct _Timer_A_UpModeConfig -//! \brief Configuration structure for Up mode in the \b Timer_A module. See -//! \link Timer_A_configureUpMode \endlink for parameter -//! documentation. -// -//***************************************************************************** -typedef struct _Timer_A_UpModeConfig -{ - uint_fast16_t clockSource; - uint_fast16_t clockSourceDivider; - uint_fast16_t timerPeriod; - uint_fast16_t timerInterruptEnable_TAIE; - uint_fast16_t captureCompareInterruptEnable_CCR0_CCIE; - uint_fast16_t timerClear; -} Timer_A_UpModeConfig; - -//***************************************************************************** -// -//! ypedef Timer_A_UpDownModeConfig -//! \brief Type definition for \link _Timer_A_UpDownModeConfig \endlink -//! structure -//! -//! \struct _Timer_A_UpDownModeConfig -//! \brief Configuration structure for UpDown mode in the \b Timer_A module. See -//! \link Timer_A_configureUpDownMode \endlink for parameter -//! documentation. -// -//***************************************************************************** -typedef struct _Timer_A_UpDownModeConfig -{ - uint_fast16_t clockSource; - uint_fast16_t clockSourceDivider; - uint_fast16_t timerPeriod; - uint_fast16_t timerInterruptEnable_TAIE; - uint_fast16_t captureCompareInterruptEnable_CCR0_CCIE; - uint_fast16_t timerClear; -} Timer_A_UpDownModeConfig; - -//***************************************************************************** -// -//! ypedef Timer_A_CaptureModeConfig -//! \brief Type definition for \link _Timer_A_CaptureModeConfig \endlink -//! structure -//! -//! \struct _Timer_A_CaptureModeConfig -//! \brief Configuration structure for capture mode in the \b Timer_A module. -//! See \link Timer_A_initCapture \endlink for parameter -//! documentation. -// -//***************************************************************************** -typedef struct _Timer_A_CaptureModeConfig -{ - uint_fast16_t captureRegister; - uint_fast16_t captureMode; - uint_fast16_t captureInputSelect; - uint_fast16_t synchronizeCaptureSource; - uint_fast8_t captureInterruptEnable; - uint_fast16_t captureOutputMode; -} Timer_A_CaptureModeConfig; - -//***************************************************************************** -// -//! ypedef Timer_A_CompareModeConfig -//! \brief Type definition for \link _Timer_A_CompareModeConfig \endlink -//! structure -//! -//! \struct _Timer_A_CompareModeConfig -//! \brief Configuration structure for compare mode in the \b Timer_A module. -//! See \link Timer_A_initCompare \endlink for parameter -//! documentation. -// -//***************************************************************************** -typedef struct _Timer_A_CompareModeConfig -{ - uint_fast16_t compareRegister; - uint_fast16_t compareInterruptEnable; - uint_fast16_t compareOutputMode; - uint_fast16_t compareValue; -} Timer_A_CompareModeConfig; - -//***************************************************************************** -// -//! ypedef Timer_A_PWMConfig -//! \brief Type definition for \link _Timer_A_PWMConfig \endlink -//! structure -//! -//! \struct _Timer_A_PWMConfig -//! \brief Configuration structure for PWM mode in the \b Timer_A module. See -//! \link Timer_A_generatePWM \endlink for parameter -//! documentation. -// -//***************************************************************************** -typedef struct _Timer_A_PWMConfig -{ - uint_fast16_t clockSource; - uint_fast16_t clockSourceDivider; - uint_fast16_t timerPeriod; - uint_fast16_t compareRegister; - uint_fast16_t compareOutputMode; - uint_fast16_t dutyCycle; -} Timer_A_PWMConfig; - - -//***************************************************************************** -// -// The following is a parameter determines the maximum difference in counts of -// the TAxR register for a majority vote -// -//***************************************************************************** -#define TIMER_A_THRESHOLD 50 - -//***************************************************************************** -// -// The following are values that can be passed to the clockSourceDivider -// parameter -// -//***************************************************************************** -#define TIMER_A_CLOCKSOURCE_DIVIDER_1 0x01 -#define TIMER_A_CLOCKSOURCE_DIVIDER_2 0x02 -#define TIMER_A_CLOCKSOURCE_DIVIDER_4 0x04 -#define TIMER_A_CLOCKSOURCE_DIVIDER_8 0x08 -#define TIMER_A_CLOCKSOURCE_DIVIDER_3 0x03 -#define TIMER_A_CLOCKSOURCE_DIVIDER_5 0x05 -#define TIMER_A_CLOCKSOURCE_DIVIDER_6 0x06 -#define TIMER_A_CLOCKSOURCE_DIVIDER_7 0x07 -#define TIMER_A_CLOCKSOURCE_DIVIDER_10 0x0A -#define TIMER_A_CLOCKSOURCE_DIVIDER_12 0x0C -#define TIMER_A_CLOCKSOURCE_DIVIDER_14 0x0E -#define TIMER_A_CLOCKSOURCE_DIVIDER_16 0x10 -#define TIMER_A_CLOCKSOURCE_DIVIDER_20 0x14 -#define TIMER_A_CLOCKSOURCE_DIVIDER_24 0x18 -#define TIMER_A_CLOCKSOURCE_DIVIDER_28 0x1C -#define TIMER_A_CLOCKSOURCE_DIVIDER_32 0x20 -#define TIMER_A_CLOCKSOURCE_DIVIDER_40 0x28 -#define TIMER_A_CLOCKSOURCE_DIVIDER_48 0x30 -#define TIMER_A_CLOCKSOURCE_DIVIDER_56 0x38 -#define TIMER_A_CLOCKSOURCE_DIVIDER_64 0x40 - -//***************************************************************************** -// -// The following are values that can be passed to the timerMode parameter -// -//***************************************************************************** -#define TIMER_A_STOP_MODE TIMER_A_CTL_MC_0 -#define TIMER_A_UP_MODE TIMER_A_CTL_MC_1 -#define TIMER_A_CONTINUOUS_MODE TIMER_A_CTL_MC_2 -#define TIMER_A_UPDOWN_MODE TIMER_A_CTL_MC_3 - -//***************************************************************************** -// -// The following are values that can be passed to the timerClear parameter -// -//***************************************************************************** -#define TIMER_A_DO_CLEAR TIMER_A_CTL_CLR -#define TIMER_A_SKIP_CLEAR 0x00 - -//***************************************************************************** -// -// The following are values that can be passed to the clockSource parameter -// -//***************************************************************************** -#define TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK TIMER_A_CTL_SSEL__TACLK -#define TIMER_A_CLOCKSOURCE_ACLK TIMER_A_CTL_SSEL__ACLK -#define TIMER_A_CLOCKSOURCE_SMCLK TIMER_A_CTL_SSEL__SMCLK -#define TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK TIMER_A_CTL_SSEL__INCLK - -//***************************************************************************** -// -// The following are values that can be passed to the timerInterruptEnable_TAIE -// parameter -// -//***************************************************************************** -#define TIMER_A_TAIE_INTERRUPT_ENABLE TIMER_A_CTL_IE -#define TIMER_A_TAIE_INTERRUPT_DISABLE 0x00 - -//***************************************************************************** -// -// The following are values that can be passed to the -// captureCompareInterruptEnable_CCR0_CCIE parameter -// -//***************************************************************************** -#define TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE TIMER_A_CCTLN_CCIE -#define TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE 0x00 - -//***************************************************************************** -// -// The following are values that can be passed to the captureInterruptEnable -// parameter -// -//***************************************************************************** -#define TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE 0x00 -#define TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE TIMER_A_CCTLN_CCIE - -//***************************************************************************** -// -// The following are values that can be passed to the captureInputSelect -// parameter -// -//***************************************************************************** -#define TIMER_A_CAPTURE_INPUTSELECT_CCIxA TIMER_A_CCTLN_CCIS_0 -#define TIMER_A_CAPTURE_INPUTSELECT_CCIxB TIMER_A_CCTLN_CCIS_1 -#define TIMER_A_CAPTURE_INPUTSELECT_GND TIMER_A_CCTLN_CCIS_2 -#define TIMER_A_CAPTURE_INPUTSELECT_Vcc TIMER_A_CCTLN_CCIS_3 - -//***************************************************************************** -// -// The following are values that can be passed to the compareOutputMode -// parameter -// -//***************************************************************************** -#define TIMER_A_OUTPUTMODE_OUTBITVALUE TIMER_A_CCTLN_OUTMOD_0 -#define TIMER_A_OUTPUTMODE_SET TIMER_A_CCTLN_OUTMOD_1 -#define TIMER_A_OUTPUTMODE_TOGGLE_RESET TIMER_A_CCTLN_OUTMOD_2 -#define TIMER_A_OUTPUTMODE_SET_RESET TIMER_A_CCTLN_OUTMOD_3 -#define TIMER_A_OUTPUTMODE_TOGGLE TIMER_A_CCTLN_OUTMOD_4 -#define TIMER_A_OUTPUTMODE_RESET TIMER_A_CCTLN_OUTMOD_5 -#define TIMER_A_OUTPUTMODE_TOGGLE_SET TIMER_A_CCTLN_OUTMOD_6 -#define TIMER_A_OUTPUTMODE_RESET_SET TIMER_A_CCTLN_OUTMOD_7 - -//***************************************************************************** -// -// The following are values that can be passed to the compareRegister parameter -// -//***************************************************************************** -#define TIMER_A_CAPTURECOMPARE_REGISTER_0 0x02 -#define TIMER_A_CAPTURECOMPARE_REGISTER_1 0x04 -#define TIMER_A_CAPTURECOMPARE_REGISTER_2 0x06 -#define TIMER_A_CAPTURECOMPARE_REGISTER_3 0x08 -#define TIMER_A_CAPTURECOMPARE_REGISTER_4 0x0A -#define TIMER_A_CAPTURECOMPARE_REGISTER_5 0x0C -#define TIMER_A_CAPTURECOMPARE_REGISTER_6 0x0E - -//***************************************************************************** -// -// The following are values that can be passed to the captureMode parameter -// -//***************************************************************************** -#define TIMER_A_CAPTUREMODE_NO_CAPTURE TIMER_A_CCTLN_CM_0 -#define TIMER_A_CAPTUREMODE_RISING_EDGE TIMER_A_CCTLN_CM_1 -#define TIMER_A_CAPTUREMODE_FALLING_EDGE TIMER_A_CCTLN_CM_2 -#define TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE TIMER_A_CCTLN_CM_3 - -//***************************************************************************** -// -// The following are values that can be passed to the synchronizeCaptureSource -// parameter -// -//***************************************************************************** -#define TIMER_A_CAPTURE_ASYNCHRONOUS 0x00 -#define TIMER_A_CAPTURE_SYNCHRONOUS TIMER_A_CCTLN_SCS - -//***************************************************************************** -// -// The following are values that can be passed to the mask parameter -// -//***************************************************************************** -#define TIMER_A_CAPTURE_OVERFLOW TIMER_A_CCTLN_COV -#define TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG TIMER_A_CCTLN_CCIFG - -//***************************************************************************** -// -// The following are values that can be passed to the synchronized parameter -// -//***************************************************************************** -#define TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT TIMER_A_CCTLN_SCCI -#define TIMER_A_READ_CAPTURE_COMPARE_INPUT TIMER_A_CCTLN_CCI - - -#define TIMER_A_CAPTURECOMPARE_INPUT_HIGH 0x01 -#define TIMER_A_CAPTURECOMPARE_INPUT_LOW 0x00 - -//***************************************************************************** -// -// The following are values that can be passed to the outputModeOutBitValue -// parameter -// -//***************************************************************************** -#define TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH TIMER_A_CCTLN_OUT -#define TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW 0x00 - -//***************************************************************************** -// -// The following are values that can be passed toThe following are values that -// can be returned by the interrupt functions -// -//***************************************************************************** -#define TIMER_A_INTERRUPT_NOT_PENDING 0x00 -#define TIMER_A_INTERRUPT_PENDING 0x01 - - -/* Convenience function for setting the PWM Duty Cycle */ -#define Timer_A_setDutyCycle(timer,dutyCycle) \ - Timer_A_setCompareValue(timer,dutyCycle) - -//***************************************************************************** -// -//Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! Starts Timer_A counter -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param timerMode selects Clock source. Valid values are -//! - \b TIMER_A_CONTINUOUS_MODE [Default value] -//! - \b TIMER_A_UPDOWN_MODE -//! - \b TIMER_A_UP_MODE -//! -//! \note This function assumes that the timer has been previously configured -//! using Timer_A_configureContinuousMode, Timer_A_configureUpMode or -//! Timer_A_configureUpDownMode. -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_startCounter(uint32_t timer, uint_fast16_t timerMode); - -//***************************************************************************** -// -//! Configures Timer_A in continuous mode. -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param config Configuration structure for Timer_A continuous mode -//! -//!
-//! Configuration options for \link Timer_A_ContinuousModeConfig \endlink -//! structure. -//!
-//! -//! \param clockSource selects Clock source. Valid values are -//! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default value] -//! - \b TIMER_A_CLOCKSOURCE_ACLK -//! - \b TIMER_A_CLOCKSOURCE_SMCLK -//! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK -//! \param timerInterruptEnable_TAIE is the divider for Clock source. -//! Valid values are: -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default value] -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 -//! \param timerInterruptEnable_TAIE is to enable or disable Timer_A -//! interrupt. Valid values are -//! - \b TIMER_A_TAIE_INTERRUPT_ENABLE -//! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default value] -//! \param timerClear decides if Timer_A clock divider, count direction, -//! count need to be reset. Valid values are -//! - \b TIMER_A_DO_CLEAR -//! - \b TIMER_A_SKIP_CLEAR [Default value] -//! -//! \note This API does not start the timer. Timer needs to be started when -//! required using the Timer_A_startCounter API. -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_configureContinuousMode(uint32_t timer, - const Timer_A_ContinuousModeConfig *config); - -//***************************************************************************** -// -//! Configures Timer_A in up mode. -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param config Configuration structure for Timer_A Up mode -//! -//!
-//! Configuration options for \link Timer_A_UpModeConfig \endlink -//! structure. -//!
-//! \param clockSource selects Clock source. Valid values are -//! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default value] -//! - \b TIMER_A_CLOCKSOURCE_ACLK -//! - \b TIMER_A_CLOCKSOURCE_SMCLK -//! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK -//! \param clockSourceDivider is the divider for Clock source. Valid values -//! are: -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default value] -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 -//! \param timerPeriod is the specified Timer_A period. This is the value -//! that gets written into the CCR0. Limited to 16 bits[uint16_t] -//! \param timerInterruptEnable_TAIE is to enable or disable Timer_A -//! interrupt. Valid values are: -//! - \b TIMER_A_TAIE_INTERRUPT_ENABLE and -//! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default value] -//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable -//! Timer_A CCR0 captureComapre interrupt. Valid values are -//! - \b TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE and -//! - \b TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE [Default value] -//! \param timerClear decides if Timer_A clock divider, count direction, -//! count need to be reset. Valid values are -//! - \b TIMER_A_DO_CLEAR -//! - \b TIMER_A_SKIP_CLEAR [Default value] -//! -//!\note This API does not start the timer. Timer needs to be started when -//!required using the Timer_A_startCounter API. -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_configureUpMode(uint32_t timer, - const Timer_A_UpModeConfig *config); - -//***************************************************************************** -// -//! Configures Timer_A in up down mode. -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param config Configuration structure for Timer_A UpDown mode -//! -//!
-//! Configuration options for \link Timer_A_UpDownModeConfig \endlink -//! structure. -//!
-//! \param clockSource selects Clock source. Valid values are -//! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK [Default value] -//! - \b TIMER_A_CLOCKSOURCE_ACLK -//! - \b TIMER_A_CLOCKSOURCE_SMCLK -//! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK -//! \param clockSourceDivider is the divider for Clock source. Valid values -//! are: -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 [Default value] -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 -//! \param timerPeriod is the specified Timer_A period -//! \param timerInterruptEnable_TAIE is to enable or disable Timer_A -//! interrupt. -//! Valid values are -//! - \b TIMER_A_TAIE_INTERRUPT_ENABLE -//! - \b TIMER_A_TAIE_INTERRUPT_DISABLE [Default value] -//! \param captureCompareInterruptEnable_CCR0_CCIE is to enable or disable -//! Timer_A CCR0 captureComapre interrupt. Valid values are -//! - \b TIMER_A_CCIE_CCR0_INTERRUPT_ENABLE and -//! - \b TIMER_A_CCIE_CCR0_INTERRUPT_DISABLE [Default value] -//! \param timerClear decides if Timer_A clock divider, count direction, count -//! need to be reset. Valid values are -//! - \b TIMER_A_DO_CLEAR -//! - \b TIMER_A_SKIP_CLEAR [Default value] -//! -//!This API does not start the timer. Timer needs to be started when required -//!using the Timer_A_startCounter API. -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_configureUpDownMode(uint32_t timer, - const Timer_A_UpDownModeConfig *config); - -//***************************************************************************** -// -//! Initializes Capture Mode -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param config Configuration structure for Timer_A capture mode -//! -//!
-//! Configuration options for \link Timer_A_CaptureModeConfig \endlink -//! structure. -//!
-//! \param captureRegister selects the Capture register being used. Valid -//! values are -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 -//! \n Refer to datasheet to ensure the device has the capture compare -//! register being used -//! \param captureMode is the capture mode selected. Valid values are -//! - \b TIMER_A_CAPTUREMODE_NO_CAPTURE [Default value] -//! - \b TIMER_A_CAPTUREMODE_RISING_EDGE -//! - \b TIMER_A_CAPTUREMODE_FALLING_EDGE -//! - \b TIMER_A_CAPTUREMODE_RISING_AND_FALLING_EDGE -//! \param captureInputSelect decides the Input Select -//! - \b TIMER_A_CAPTURE_INPUTSELECT_CCIxA [Default value] -//! - \b TIMER_A_CAPTURE_INPUTSELECT_CCIxB -//! - \b TIMER_A_CAPTURE_INPUTSELECT_GND -//! - \b TIMER_A_CAPTURE_INPUTSELECT_Vcc -//! \param synchronizeCaptureSource decides if capture source should be -//! synchronized with timer clock -//! Valid values are -//! - \b TIMER_A_CAPTURE_ASYNCHRONOUS [Default value] -//! - \b TIMER_A_CAPTURE_SYNCHRONOUS -//! \param captureInterruptEnable is to enable or disable -//! timer captureComapre interrupt. Valid values are -//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE [Default value] -//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE -//! \param captureOutputMode specifies the ouput mode. Valid values are -//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default value], -//! - \b TIMER_A_OUTPUTMODE_SET, -//! - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET, -//! - \b TIMER_A_OUTPUTMODE_SET_RESET -//! - \b TIMER_A_OUTPUTMODE_TOGGLE, -//! - \b TIMER_A_OUTPUTMODE_RESET, -//! - \b TIMER_A_OUTPUTMODE_TOGGLE_SET, -//! - \b TIMER_A_OUTPUTMODE_RESET_SET -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_initCapture(uint32_t timer, - const Timer_A_CaptureModeConfig *config); - -//***************************************************************************** -// -//! Initializes Compare Mode -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param config Configuration structure for Timer_A compare mode -//! -//!
-//! Configuration options for \link Timer_A_CompareModeConfig \endlink -//! structure. -//!
-//! \param compareRegister selects the Capture register being used. Valid -//! values are -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 -//! \n Refer to datasheet to ensure the device has the capture compare -//! register being used -//! \param compareInterruptEnable is to enable or disable -//! timer captureComapre interrupt. Valid values are -//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_ENABLE and -//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_DISABLE [Default value] -//! \param compareOutputMode specifies the output mode. Valid values are -//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE [Default value], -//! - \b TIMER_A_OUTPUTMODE_SET, -//! - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET, -//! - \b TIMER_A_OUTPUTMODE_SET_RESET -//! - \b TIMER_A_OUTPUTMODE_TOGGLE, -//! - \b TIMER_A_OUTPUTMODE_RESET, -//! - \b TIMER_A_OUTPUTMODE_TOGGLE_SET, -//! - \b TIMER_A_OUTPUTMODE_RESET_SET -//! \param compareValue is the count to be compared with in compare mode -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_initCompare(uint32_t timer, - const Timer_A_CompareModeConfig *config); - -//***************************************************************************** -// -//! Reset/Clear the timer clock divider, count direction, count -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! -//! \returns None -// -//***************************************************************************** -extern void Timer_A_clearTimer(uint32_t timer); - -//***************************************************************************** -// -//! Get synchronized capture compare input -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param captureCompareRegister selects the Capture register being used. -//! Valid values are -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 -//! \n Refer to datasheet to ensure the device has the capture compare -//! register being used -//! \param synchronizedSetting is to select type of capture compare input. -//! Valid values are -//! - \b TIMER_A_READ_CAPTURE_COMPARE_INPUT -//! - \b TIMER_A_READ_SYNCHRONIZED_CAPTURECOMPAREINPUT -//! -//! \return \b TIMER_A_CAPTURECOMPARE_INPUT_HIGH or -//! - \b TIMER_A_CAPTURECOMPARE_INPUT_LOW -// -//***************************************************************************** -extern uint_fast8_t Timer_A_getSynchronizedCaptureCompareInput(uint32_t timer, - uint_fast16_t captureCompareRegister, - uint_fast16_t synchronizedSetting); - -//***************************************************************************** -// -//! Get ouput bit for output mode -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param captureCompareRegister selects the Capture register being used. -//! Valid values are -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 -//! \n Refer to datasheet to ensure the device has the capture compare -//! register being used -//! -//! \return \b TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH or -//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW -// -//***************************************************************************** -extern uint_fast8_t Timer_A_getOutputForOutputModeOutBitValue(uint32_t timer, - uint_fast16_t captureCompareRegister); - -//***************************************************************************** -// -//! Get current capture compare count -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param captureCompareRegister selects the Capture register being used. -//! Valid values are -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 -//! \n Refer to datasheet to ensure the device has the capture compare -//! register being used -//! -//! \return current count as uint16_t -// -//***************************************************************************** -extern uint_fast16_t Timer_A_getCaptureCompareCount(uint32_t timer, - uint_fast16_t captureCompareRegister); - -//***************************************************************************** -// -//! Set ouput bit for output mode -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param captureCompareRegister selects the Capture register being used. -//! are -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 -//! \n Refer to datasheet to ensure the device has the capture compare -//! register being used -//! \param outputModeOutBitValue the value to be set for out bit. -//! Valid values are: -//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_HIGH -//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE_LOW -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_setOutputForOutputModeOutBitValue(uint32_t timer, - uint_fast16_t captureCompareRegister, - uint_fast8_t outputModeOutBitValue); - -//***************************************************************************** -// -//! Generate a PWM with timer running in up mode -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param config Configuration structure for Timer_A PWM mode -//! -//!
-//! Configuration options for \link Timer_A_PWMConfig \endlink -//! structure. -//!
-//! \param clockSource selects Clock source. Valid values are -//! - \b TIMER_A_CLOCKSOURCE_EXTERNAL_TXCLK -//! - \b TIMER_A_CLOCKSOURCE_ACLK -//! - \b TIMER_A_CLOCKSOURCE_SMCLK -//! - \b TIMER_A_CLOCKSOURCE_INVERTED_EXTERNAL_TXCLK -//! \param clockSourceDivider is the divider for Clock source. Valid values -//! are -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_1 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_2 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_4 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_8 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_3 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_5 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_6 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_7 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_10 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_12 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_14 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_16 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_20 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_24 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_28 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_32 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_40 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_48 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_56 -//! - \b TIMER_A_CLOCKSOURCE_DIVIDER_64 -//! \param timerPeriod selects the desired timer period -//! \param compareRegister selects the compare register being used. -//! Valid values are -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 -//!
\n Refer to datasheet to ensure the device has the capture compare -//! register being used -//! \param compareOutputMode specifies the ouput mode. Valid values are: -//! - \b TIMER_A_OUTPUTMODE_OUTBITVALUE, -//! - \b TIMER_A_OUTPUTMODE_SET, -//! - \b TIMER_A_OUTPUTMODE_TOGGLE_RESET, -//! - \b TIMER_A_OUTPUTMODE_SET_RESET -//! - \b TIMER_A_OUTPUTMODE_TOGGLE, -//! - \b TIMER_A_OUTPUTMODE_RESET, -//! - \b TIMER_A_OUTPUTMODE_TOGGLE_SET, -//! - \b TIMER_A_OUTPUTMODE_RESET_SET -//! \param dutyCycle specifies the dutycycle for the generated waveform -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_generatePWM(uint32_t timer, - const Timer_A_PWMConfig *config); - -//***************************************************************************** -// -//! Stops the timer -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! -//! \returns None -// -//***************************************************************************** -extern void Timer_A_stopTimer(uint32_t timer); - -//***************************************************************************** -// -//! Sets the value of the capture-compare register -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param compareRegister selects the Capture register being used. Valid -//! values are -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 -//!
\n Refer to datasheet to ensure the device has the capture compare -//! register being used -//! \param compareValue is the count to be compared with in compare mode -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_setCompareValue(uint32_t timer, - uint_fast16_t compareRegister, uint_fast16_t compareValue); - -//***************************************************************************** -// -//! Returns the current value of the specified timer. Note that according to -//! the Timer A user guide, reading the value of the counter is unreliable -//! if the system clock is asynchronous from the timer clock. The API addresses -//! this concern by reading the timer count register twice and then determining -//! the integrity of the value. If the two values are within 10 timer counts -//! of each other, the value is deemed safe and returned. If not, the process -//! is repeated until a reliable timer value is determined. -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! -//! \returns The value of the specified timer -// -//***************************************************************************** -extern uint16_t Timer_A_getCounterValue(uint32_t timer); - -//***************************************************************************** -// -//! Clears the Timer TAIFG interrupt flag -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_clearInterruptFlag(uint32_t timer); - -//***************************************************************************** -// -//! Clears the capture-compare interrupt flag -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param captureCompareRegister selects the Capture-compare register being -//! used. Valid values are -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_0 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_1 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_2 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_3 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_4 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_5 -//! - \b TIMER_A_CAPTURECOMPARE_REGISTER_6 -//!
Refer to the datasheet to ensure the device has the capture compare -//! register being used -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_clearCaptureCompareInterrupt(uint32_t timer, - uint_fast16_t captureCompareRegister); - -//***************************************************************************** -// -//! Enable timer interrupt -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_enableInterrupt(uint32_t timer); - -//***************************************************************************** -// -//! Disable timer interrupt -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_disableInterrupt(uint32_t timer); - -//***************************************************************************** -// -//! Get timer interrupt status -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! -//! \return uint32_t. Return interrupt status. Valid values are -//! - \b TIMER_A_INTERRUPT_PENDING -//! - \b TIMER_A_INTERRUPT_NOT_PENDING -// -//***************************************************************************** -extern uint32_t Timer_A_getInterruptStatus(uint32_t timer); - -//***************************************************************************** -// -//! Get timer interrupt status masked with the enabled interrupts. -//! This function is useful to call in ISRs to get a list of pending -//! interrupts that are actually enabled and could have caused -//! the ISR. -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! -//! \return uint32_t. Return interrupt status. Valid values are -//! - \b TIMER_A_INTERRUPT_PENDING -//! - \b TIMER_A_INTERRUPT_NOT_PENDING -// -//***************************************************************************** -extern uint32_t Timer_A_getEnabledInterruptStatus(uint32_t timer); - -//***************************************************************************** -// -//! Enable capture compare interrupt -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param captureCompareRegister is the selected capture compare register -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_enableCaptureCompareInterrupt(uint32_t timer, - uint_fast16_t captureCompareRegister); - -//***************************************************************************** -// -//! Disable capture compare interrupt -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param captureCompareRegister is the selected capture compare register -//! -//! \return None -// -//***************************************************************************** -extern void Timer_A_disableCaptureCompareInterrupt(uint32_t timer, - uint_fast16_t captureCompareRegister); - -//***************************************************************************** -// -//! Return capture compare interrupt status -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param captureCompareRegister is the selected capture compare register -//! -//! \param mask is the mask for the interrupt status -//! Mask value is the logical OR of any of the following: -//! - \b TIMER_A_CAPTURE_OVERFLOW -//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG -//! -//! \returns uint32_t. The mask of the set flags. -//! Valid values is an OR of -//! - \b TIMER_A_CAPTURE_OVERFLOW, -//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG -// -//***************************************************************************** -extern uint32_t Timer_A_getCaptureCompareInterruptStatus(uint32_t timer, - uint_fast16_t captureCompareRegister, uint_fast16_t mask); - -//***************************************************************************** -// -//! Return capture compare interrupt status masked with the enabled interrupts. -//! This function is useful to call in ISRs to get a list of pending -//! interrupts that are actually enabled and could have caused -//! the ISR. -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! \param captureCompareRegister is the selected capture compare register -//! -//! \returns uint32_t. The mask of the set flags. -//! Valid values is an OR of -//! - \b TIMER_A_CAPTURE_OVERFLOW, -//! - \b TIMER_A_CAPTURECOMPARE_INTERRUPT_FLAG -// -//***************************************************************************** -extern uint32_t Timer_A_getCaptureCompareEnabledInterruptStatus(uint32_t timer, - uint_fast16_t captureCompareRegister); - -//***************************************************************************** -// -//! Registers an interrupt handler for the timer capture compare interrupt. -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! -//! \param interruptSelect Selects which timer interrupt handler to -//! register. For the timer module, there are two separate interrupt handlers -//! that can be registered: -//! - \b TIMER_A_CCR0_INTERRUPT Corresponds to the interrupt for CCR0 -//! - \b TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT Corresponds to the -//! interrupt for CCR1-6, as well as the overflow interrupt. -//! -//! \param intHandler is a pointer to the function to be called when the -//! timer capture compare interrupt occurs. -//! -//! This function registers the handler to be called when a timer -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific Timer_Ainterrupts must be enabled -//! via Timer_A_enableInterrupt(). It is the interrupt handler's -//! responsibility to clear the interrupt source -//! via Timer_A_clearCaptureCompareInterrupt(). -//! -//! \return None. -// -//***************************************************************************** -extern void Timer_A_registerInterrupt(uint32_t timer, - uint_fast8_t interruptSelect, void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the timer -//! -//! \param timer is the instance of the Timer_A module. Valid parameters -//! vary from part to part, but can include: -//! - \b TIMER_A0_BASE -//! - \b TIMER_A1_BASE -//! - \b TIMER_A2_BASE -//! - \b TIMER_A3_BASE -//! -//! \param interruptSelect Selects which timer interrupt handler to -//! register. For the timer module, there are two separate interrupt handlers -//! that can be registered: -//! - \b TIMER_A_CCR0_INTERRUPT Corresponds to the interrupt for CCR0 -//! - \b TIMER_A_CCRX_AND_OVERFLOW_INTERRUPT Corresponds to the -//! interrupt for CCR1-6, as well as the overflow interrupt. -//! -//! This function unregisters the handler to be called when timer -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void Timer_A_unregisterInterrupt(uint32_t timer, - uint_fast8_t interruptSelect); - -/* Backwards Compatibility Layer */ -#define Timer_A_clearTimerInterrupt Timer_A_clearInterruptFlag -#define Timer_A_clear Timer_A_clearTimer -#define Timer_A_initCaptureMode Timer_A_initCapture -#define Timer_A_initCompareMode Timer_A_initCompare -#define Timer_A_initContinuousMode Timer_A_configureContinuousMode -#define Timer_A_initUpDownMode Timer_A_configureUpDownMode -#define Timer_A_initUpMode Timer_A_configureUpMode -#define Timer_A_outputPWM Timer_A_generatePWM -#define Timer_A_stop Timer_A_stopTimer - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* TIMERA_H_ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/uart.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/uart.c deleted file mode 100644 index b6b12d25928..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/uart.c +++ /dev/null @@ -1,391 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#include -#include -#include -#include - -bool UART_initModule(uint32_t moduleInstance, const eUSCI_UART_Config *config) -{ - bool retVal = true; - - ASSERT( - (EUSCI_A_UART_MODE == config->uartMode) - || (EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE - == config->uartMode) - || (EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE - == config->uartMode) - || (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE - == config->uartMode)); - - ASSERT( - (EUSCI_A_UART_CLOCKSOURCE_ACLK == config->selectClockSource) - || (EUSCI_A_UART_CLOCKSOURCE_SMCLK - == config->selectClockSource)); - - ASSERT( - (EUSCI_A_UART_MSB_FIRST == config->msborLsbFirst) - || (EUSCI_A_UART_LSB_FIRST == config->msborLsbFirst)); - - ASSERT( - (EUSCI_A_UART_ONE_STOP_BIT == config->numberofStopBits) - || (EUSCI_A_UART_TWO_STOP_BITS == config->numberofStopBits)); - - ASSERT( - (EUSCI_A_UART_NO_PARITY == config->parity) - || (EUSCI_A_UART_ODD_PARITY == config->parity) - || (EUSCI_A_UART_EVEN_PARITY == config->parity)); - - /* Disable the USCI Module */ - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; - - /* Clock source select */ - EUSCI_A_CMSIS(moduleInstance)->CTLW0 = - (EUSCI_A_CMSIS(moduleInstance)->CTLW0 & ~EUSCI_A_CTLW0_SSEL_MASK) - | config->selectClockSource; - - /* MSB, LSB select */ - if (config->msborLsbFirst) - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 1; - else - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_MSB_OFS) = 0; - - /* UCSPB = 0(1 stop bit) OR 1(2 stop bits) */ - if (config->numberofStopBits) - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 1; - else - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SPB_OFS) = 0; - - /* Parity */ - switch (config->parity) - { - case EUSCI_A_UART_NO_PARITY: - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 0; - break; - case EUSCI_A_UART_ODD_PARITY: - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1; - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 0; - break; - case EUSCI_A_UART_EVEN_PARITY: - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PEN_OFS) = 1; - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_PAR_OFS) = 1; - break; - } - - /* BaudRate Control Register */ - EUSCI_A_CMSIS(moduleInstance)->BRW = config->clockPrescalar; - EUSCI_A_CMSIS(moduleInstance)->MCTLW = ((config->secondModReg << 8) - + (config->firstModReg << 4) + config->overSampling); - - /* Asynchronous mode & 8 bit character select & clear mode */ - EUSCI_A_CMSIS(moduleInstance)->CTLW0 = - (EUSCI_A_CMSIS(moduleInstance)->CTLW0 - & ~(EUSCI_A_CTLW0_SYNC | EUSCI_A_CTLW0_SEVENBIT | EUSCI_A_CTLW0_MODE_3 | EUSCI_A_CTLW0_RXEIE | EUSCI_A_CTLW0_BRKIE | EUSCI_A_CTLW0_DORM - | EUSCI_A_CTLW0_TXADDR | EUSCI_A_CTLW0_TXBRK)) | config->uartMode; - - return retVal; -} - -void UART_transmitData(uint32_t moduleInstance, uint_fast8_t transmitData) -{ - /* If interrupts are not used, poll for flags */ - if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_TXIE_OFS)) - while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS)) - ; - - EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitData; -} - -uint8_t UART_receiveData(uint32_t moduleInstance) -{ - /* If interrupts are not used, poll for flags */ - if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_RXIE_OFS)) - while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_RXIFG_OFS)) - ; - - return EUSCI_A_CMSIS(moduleInstance)->RXBUF; -} - -void UART_enableModule(uint32_t moduleInstance) -{ - /* Reset the UCSWRST bit to enable the USCI Module */ - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 0; -} - -void UART_disableModule(uint32_t moduleInstance) -{ - /* Set the UCSWRST bit to disable the USCI Module */ - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_SWRST_OFS) = 1; -} - -uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, uint_fast8_t mask) -{ - ASSERT( - 0x00 != mask - && (EUSCI_A_UART_LISTEN_ENABLE + EUSCI_A_UART_FRAMING_ERROR - + EUSCI_A_UART_OVERRUN_ERROR - + EUSCI_A_UART_PARITY_ERROR - + EUSCI_A_UART_BREAK_DETECT - + EUSCI_A_UART_RECEIVE_ERROR - + EUSCI_A_UART_ADDRESS_RECEIVED - + EUSCI_A_UART_IDLELINE + EUSCI_A_UART_BUSY)); - - return EUSCI_A_CMSIS(moduleInstance)->STATW & mask; -} - -void UART_setDormant(uint32_t moduleInstance) -{ - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 1; -} - -void UART_resetDormant(uint32_t moduleInstance) -{ - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_DORM_OFS) = 0; -} - -void UART_transmitAddress(uint32_t moduleInstance, uint_fast8_t transmitAddress) -{ - /* Set UCTXADDR bit */ - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXADDR_OFS) = 1; - - /* Place next byte to be sent into the transmit buffer */ - EUSCI_A_CMSIS(moduleInstance)->TXBUF = transmitAddress; -} - -void UART_transmitBreak(uint32_t moduleInstance) -{ - /* Set UCTXADDR bit */ - BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->CTLW0, EUSCI_A_CTLW0_TXBRK_OFS) = 1; - - /* If current mode is automatic baud-rate detection */ - if (EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE - == (EUSCI_A_CMSIS(moduleInstance)->CTLW0 - & EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE)) - EUSCI_A_CMSIS(moduleInstance)->TXBUF = - EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC; - else - EUSCI_A_CMSIS(moduleInstance)->TXBUF = DEFAULT_SYNC; - - /* If interrupts are not used, poll for flags */ - if (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IE, EUSCI_A_IE_TXIE_OFS)) - while (!BITBAND_PERI(EUSCI_A_CMSIS(moduleInstance)->IFG, EUSCI_A_IFG_TXIFG_OFS)) - ; -} - -uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance) -{ - return (uint32_t)&EUSCI_A_CMSIS(moduleInstance)->RXBUF; -} - -uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance) -{ - return (uint32_t)&EUSCI_B_CMSIS(moduleInstance)->TXBUF; -} - -void UART_selectDeglitchTime(uint32_t moduleInstance, uint32_t deglitchTime) -{ - ASSERT( - (EUSCI_A_UART_DEGLITCH_TIME_2ns == deglitchTime) - || (EUSCI_A_UART_DEGLITCH_TIME_50ns == deglitchTime) - || (EUSCI_A_UART_DEGLITCH_TIME_100ns == deglitchTime) - || (EUSCI_A_UART_DEGLITCH_TIME_200ns == deglitchTime)); - - EUSCI_A_CMSIS(moduleInstance)->CTLW1 = - (EUSCI_A_CMSIS(moduleInstance)->CTLW1 & ~(EUSCI_A_CTLW1_GLIT_MASK)) - | deglitchTime; - -} - -void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask) -{ - uint_fast8_t locMask; - - ASSERT( - !(mask - & ~(EUSCI_A_UART_RECEIVE_INTERRUPT - | EUSCI_A_UART_TRANSMIT_INTERRUPT - | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - | EUSCI_A_UART_BREAKCHAR_INTERRUPT - | EUSCI_A_UART_STARTBIT_INTERRUPT - | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT))); - - locMask = (mask - & (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT - | EUSCI_A_UART_STARTBIT_INTERRUPT - | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)); - - EUSCI_A_CMSIS(moduleInstance)->IE |= locMask; - - locMask = (mask - & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - | EUSCI_A_UART_BREAKCHAR_INTERRUPT)); - EUSCI_A_CMSIS(moduleInstance)->CTLW0 |= locMask; -} - -void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask) -{ - uint_fast8_t locMask; - - ASSERT( - !(mask - & ~(EUSCI_A_UART_RECEIVE_INTERRUPT - | EUSCI_A_UART_TRANSMIT_INTERRUPT - | EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - | EUSCI_A_UART_BREAKCHAR_INTERRUPT - | EUSCI_A_UART_STARTBIT_INTERRUPT - | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT))); - - locMask = (mask - & (EUSCI_A_UART_RECEIVE_INTERRUPT | EUSCI_A_UART_TRANSMIT_INTERRUPT - | EUSCI_A_UART_STARTBIT_INTERRUPT - | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT)); - EUSCI_A_CMSIS(moduleInstance)->IE &= ~locMask; - - locMask = (mask - & (EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - | EUSCI_A_UART_BREAKCHAR_INTERRUPT)); - EUSCI_A_CMSIS(moduleInstance)->CTLW0 &= ~locMask; -} - -uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, uint8_t mask) -{ - ASSERT( - !(mask - & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG - | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG - | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG - | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG))); - - return EUSCI_A_CMSIS(moduleInstance)->IFG & mask; -} - -uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance) -{ - uint_fast8_t intStatus = UART_getInterruptStatus(moduleInstance, - EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG); - uint_fast8_t intEnabled = EUSCI_A_CMSIS(moduleInstance)->IE; - - if (!(intEnabled & EUSCI_A_UART_RECEIVE_INTERRUPT)) - { - intStatus &= ~EUSCI_A_UART_RECEIVE_INTERRUPT; - } - - if (!(intEnabled & EUSCI_A_UART_TRANSMIT_INTERRUPT)) - { - intStatus &= ~EUSCI_A_UART_TRANSMIT_INTERRUPT; - } - - intEnabled = EUSCI_A_CMSIS(moduleInstance)->CTLW0; - - if (!(intEnabled & EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT)) - { - intStatus &= ~EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT; - } - - if (!(intEnabled & EUSCI_A_UART_BREAKCHAR_INTERRUPT)) - { - intStatus &= ~EUSCI_A_UART_BREAKCHAR_INTERRUPT; - } - - return intStatus; -} - -void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask) -{ - ASSERT( - !(mask - & ~(EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG - | EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG - | EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG - | EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG))); - - //Clear the UART interrupt source. - EUSCI_A_CMSIS(moduleInstance)->IFG &= ~(mask); -} - -void UART_registerInterrupt(uint32_t moduleInstance, void (*intHandler)(void)) -{ - switch (moduleInstance) - { - case EUSCI_A0_BASE: - Interrupt_registerInterrupt(INT_EUSCIA0, intHandler); - Interrupt_enableInterrupt(INT_EUSCIA0); - break; - case EUSCI_A1_BASE: - Interrupt_registerInterrupt(INT_EUSCIA1, intHandler); - Interrupt_enableInterrupt(INT_EUSCIA1); - break; -#ifdef EUSCI_A2_BASE - case EUSCI_A2_BASE: - Interrupt_registerInterrupt(INT_EUSCIA2, intHandler); - Interrupt_enableInterrupt(INT_EUSCIA2); - break; -#endif -#ifdef EUSCI_A3_BASE - case EUSCI_A3_BASE: - Interrupt_registerInterrupt(INT_EUSCIA3, intHandler); - Interrupt_enableInterrupt(INT_EUSCIA3); - break; -#endif - default: - ASSERT(false); - } -} - -void UART_unregisterInterrupt(uint32_t moduleInstance) -{ - switch (moduleInstance) - { - case EUSCI_A0_BASE: - Interrupt_disableInterrupt(INT_EUSCIA0); - Interrupt_unregisterInterrupt(INT_EUSCIA0); - break; - case EUSCI_A1_BASE: - Interrupt_disableInterrupt(INT_EUSCIA1); - Interrupt_unregisterInterrupt(INT_EUSCIA1); - break; -#ifdef EUSCI_A2_BASE - case EUSCI_A2_BASE: - Interrupt_disableInterrupt(INT_EUSCIA2); - Interrupt_unregisterInterrupt(INT_EUSCIA2); - break; -#endif -#ifdef EUSCI_A3_BASE - case EUSCI_A3_BASE: - Interrupt_disableInterrupt(INT_EUSCIA3); - Interrupt_unregisterInterrupt(INT_EUSCIA3); - break; -#endif - default: - ASSERT(false); - } -} diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/uart.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/uart.h deleted file mode 100644 index f106a473dc1..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/uart.h +++ /dev/null @@ -1,755 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef UART_H_ -#define UART_H_ - -//***************************************************************************** -// -//! \addtogroup uart_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#include -#include - -#define DEFAULT_SYNC 0x00 -#define EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC 0x55 - -#define EUSCI_A_UART_NO_PARITY 0x00 -#define EUSCI_A_UART_ODD_PARITY 0x01 -#define EUSCI_A_UART_EVEN_PARITY 0x02 - -#define EUSCI_A_UART_MSB_FIRST EUSCI_A_CTLW0_MSB -#define EUSCI_A_UART_LSB_FIRST 0x00 - -#define EUSCI_A_UART_MODE EUSCI_A_CTLW0_MODE_0 -#define EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE EUSCI_A_CTLW0_MODE_1 -#define EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE EUSCI_A_CTLW0_MODE_2 -#define EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE EUSCI_A_CTLW0_MODE_3 - -#define EUSCI_A_UART_CLOCKSOURCE_SMCLK EUSCI_A_CTLW0_SSEL__SMCLK -#define EUSCI_A_UART_CLOCKSOURCE_ACLK EUSCI_A_CTLW0_SSEL__ACLK - -#define EUSCI_A_UART_ONE_STOP_BIT 0x00 -#define EUSCI_A_UART_TWO_STOP_BITS EUSCI_A_CTLW0_SPB - -#define EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION 0x01 -#define EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION 0x00 - -#define EUSCI_A_UART_RECEIVE_INTERRUPT EUSCI_A_IE_RXIE -#define EUSCI_A_UART_TRANSMIT_INTERRUPT EUSCI_A_IE_TXIE -#define EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT EUSCI_A_CTLW0_RXEIE -#define EUSCI_A_UART_BREAKCHAR_INTERRUPT EUSCI_A_CTLW0_BRKIE -#define EUSCI_A_UART_STARTBIT_INTERRUPT EUSCI_A_IE_STTIE -#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT EUSCI_B_IE_STPIE - -#define EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG EUSCI_A_IFG_RXIFG -#define EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG EUSCI_A_IFG_TXIFG -#define EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG EUSCI_A_IFG_STTIFG -#define EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG EUSCI_A_IFG_TXCPTIFG - -#define EUSCI_A_UART_LISTEN_ENABLE EUSCI_A_STATW_LISTEN -#define EUSCI_A_UART_FRAMING_ERROR EUSCI_A_STATW_FE -#define EUSCI_A_UART_OVERRUN_ERROR EUSCI_A_STATW_OE -#define EUSCI_A_UART_PARITY_ERROR EUSCI_A_STATW_PE -#define EUSCI_A_UART_BREAK_DETECT EUSCI_A_STATW_BRK -#define EUSCI_A_UART_RECEIVE_ERROR EUSCI_A_STATW_RXERR -#define EUSCI_A_UART_ADDRESS_RECEIVED EUSCI_A_STATW_ADDR_IDLE -#define EUSCI_A_UART_IDLELINE EUSCI_A_STATW_ADDR_IDLE -#define EUSCI_A_UART_BUSY EUSCI_A_STATW_BUSY - -#define EUSCI_A_UART_DEGLITCH_TIME_2ns 0x00 -#define EUSCI_A_UART_DEGLITCH_TIME_50ns 0x0001 -#define EUSCI_A_UART_DEGLITCH_TIME_100ns 0x0002 -#define EUSCI_A_UART_DEGLITCH_TIME_200ns (0x0001 + 0x0002) - -//***************************************************************************** -// -//! ypedef eUSCI_eUSCI_UART_Config -//! \brief Type definition for \link _eUSCI_UART_Config \endlink -//! structure -//! -//! \struct _eUSCI_eUSCI_UART_Config -//! \brief Configuration structure for compare mode in the \b UART module. See -//! \link UART_initModule \endlink for parameter -//! documentation. -// -//***************************************************************************** -typedef struct _eUSCI_eUSCI_UART_Config -{ - uint_fast8_t selectClockSource; - uint_fast16_t clockPrescalar; - uint_fast8_t firstModReg; - uint_fast8_t secondModReg; - uint_fast8_t parity; - uint_fast16_t msborLsbFirst; - uint_fast16_t numberofStopBits; - uint_fast16_t uartMode; - uint_fast8_t overSampling; -} eUSCI_UART_Config; - -//***************************************************************************** -// -//! Initialization routine for the UART block. The values to be written -//! into the UCAxBRW and UCAxMCTLW registers should be pre-computed and passed -//! into the initialization function -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//! \param config Configuration structure for the UART module -//! -//!
-//! Configuration options for \link eUSCI_UART_Config \endlink -//! structure. -//!
-//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode. -//! \param selectClockSource selects Clock source. Valid values are -//! - \b EUSCI_A_UART_CLOCKSOURCE_SMCLK -//! - \b EUSCI_A_UART_CLOCKSOURCE_ACLK -//! \param clockPrescalar is the value to be written into UCBRx bits -//! \param firstModReg is First modulation stage register setting. This -//! value is a pre-calculated value which can be obtained from the Device -//! User Guide.This value is written into UCBRFx bits of UCAxMCTLW. -//! \param secondModReg is Second modulation stage register setting. -//! This value is a pre-calculated value which can be obtained from the -//! Device User Guide. This value is written into UCBRSx bits of -//! UCAxMCTLW. -//! \param parity is the desired parity. Valid values are -//! - \b EUSCI_A_UART_NO_PARITY [Default Value], -//! - \b EUSCI_A_UART_ODD_PARITY, -//! - \b EUSCI_A_UART_EVEN_PARITY -//! \param msborLsbFirst controls direction of receive and transmit shift -//! register. Valid values are -//! - \b EUSCI_A_UART_MSB_FIRST -//! - \b EUSCI_A_UART_LSB_FIRST [Default Value] -//! \param numberofStopBits indicates one/two STOP bits -//! Valid values are -//! - \b EUSCI_A_UART_ONE_STOP_BIT [Default Value] -//! - \b EUSCI_A_UART_TWO_STOP_BITS -//! \param uartMode selects the mode of operation -//! Valid values are -//! - \b EUSCI_A_UART_MODE [Default Value], -//! - \b EUSCI_A_UART_IDLE_LINE_MULTI_PROCESSOR_MODE, -//! - \b EUSCI_A_UART_ADDRESS_BIT_MULTI_PROCESSOR_MODE, -//! - \b EUSCI_A_UART_AUTOMATIC_BAUDRATE_DETECTION_MODE -//! \param overSampling indicates low frequency or oversampling baud -//! generation -//! Valid values are -//! - \b EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION -//! - \b EUSCI_A_UART_LOW_FREQUENCY_BAUDRATE_GENERATION -//! -//! Upon successful initialization of the UART block, this function -//! will have initialized the module, but the UART block still remains -//! disabled and must be enabled with UART_enableModule() -//! -//! Refer to -//! -//! this calculator for help on calculating values for the parameters. -//! -//! Modified bits are \b UCPEN, \b UCPAR, \b UCMSB, \b UC7BIT, \b UCSPB, -//! \b UCMODEx, \b UCSYNC bits of \b UCAxCTL0 and \b UCSSELx, -//! \b UCSWRST bits of \b UCAxCTL1 -//! -//! \return true or -//! false of the initialization process -// -//***************************************************************************** -extern bool UART_initModule(uint32_t moduleInstance, - const eUSCI_UART_Config *config); - -//***************************************************************************** -// -//! Transmits a byte from the UART Module. -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! \param transmitData data to be transmitted from the UART module -//! -//! This function will place the supplied data into UART transmit data register -//! to start transmission -//! -//! Modified register is \b UCAxTXBUF -//! \return None. -// -//***************************************************************************** -extern void UART_transmitData(uint32_t moduleInstance, - uint_fast8_t transmitData); - -//***************************************************************************** -// -//! Receives a byte that has been sent to the UART Module. -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! -//! This function reads a byte of data from the UART receive data Register. -//! -//! Modified register is \b UCAxRXBUF -//! -//! \return Returns the byte received from by the UART module, cast as an -//! uint8_t. -// -//***************************************************************************** -extern uint8_t UART_receiveData(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Enables the UART block. -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! -//! This will enable operation of the UART block. -//! -//! Modified register is \b UCAxCTL1 -//! -//! \return None. -// -//***************************************************************************** -extern void UART_enableModule(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Disables the UART block. -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! -//! This will disable operation of the UART block. -//! -//! Modified register is \b UCAxCTL1 -//! -//! \return None. -// -//***************************************************************************** -extern void UART_disableModule(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Gets the current UART status flags. -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! \param mask is the masked interrupt flag status to be returned. -//! -//! This returns the status for the UART module based on which -//! flag is passed. mask parameter can be either any of the following -//! selection. -//! - \b EUSCI_A_UART_LISTEN_ENABLE -//! - \b EUSCI_A_UART_FRAMING_ERROR -//! - \b EUSCI_A_UART_OVERRUN_ERROR -//! - \b EUSCI_A_UART_PARITY_ERROR -//! - \b eUARTBREAK_DETECT -//! - \b EUSCI_A_UART_RECEIVE_ERROR -//! - \b EUSCI_A_UART_ADDRESS_RECEIVED -//! - \b EUSCI_A_UART_IDLELINE -//! - \b EUSCI_A_UART_BUSY -//! -//! Modified register is \b UCAxSTAT -//! -//! \return the masked status flag -// -//***************************************************************************** -extern uint_fast8_t UART_queryStatusFlags(uint32_t moduleInstance, - uint_fast8_t mask); - -//***************************************************************************** -// -//! Sets the UART module in dormant mode -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! -//! Puts USCI in sleep mode -//! Only characters that are preceded by an idle-line or with address bit set -//! UCRXIFG. In UART mode with automatic baud-rate detection, only the -//! combination of a break and synch field sets UCRXIFG. -//! -//! Modified register is \b UCAxCTL1 -//! -//! \return None. -// -//***************************************************************************** -extern void UART_setDormant(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Re-enables UART module from dormant mode -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! -//! Not dormant. All received characters set UCRXIFG. -//! -//! Modified bits are \b UCDORM of \b UCAxCTL1 register. -//! -//! \return None. -// -//***************************************************************************** -extern void UART_resetDormant(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Transmits the next byte to be transmitted marked as address depending on -//! selected multiprocessor mode -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! \param transmitAddress is the next byte to be transmitted -//! -//! Modified register is \b UCAxCTL1, \b UCAxTXBUF -//! -//! \return None. -// -//***************************************************************************** -extern void UART_transmitAddress(uint32_t moduleInstance, - uint_fast8_t transmitAddress); - -//***************************************************************************** -// -//! Transmit break. Transmits a break with the next write to the transmit -//! buffer. In UART mode with automatic baud-rate detection, -//! EUSCI_A_UART_AUTOMATICBAUDRATE_SYNC(0x55) must be written into UCAxTXBUF to -//! generate the required break/synch fields. -//! Otherwise, DEFAULT_SYNC(0x00) must be written into the transmit buffer. -//! Also ensures module is ready for transmitting the next data -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! asEUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! -//! Modified register is \b UCAxCTL1, \b UCAxTXBUF -//! -//! \return None. -// -//***************************************************************************** -extern void UART_transmitBreak(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Returns the address of the RX Buffer of the UART for the DMA module. -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! -//! Returns the address of the UART RX Buffer. This can be used in conjunction -//! with the DMA to store the received data directly to memory. -//! -//! \return None -// -//***************************************************************************** -extern uint32_t UART_getReceiveBufferAddressForDMA(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Returns the address of the TX Buffer of the UART for the DMA module. -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! -//! Returns the address of the UART TX Buffer. This can be used in conjunction -//! with the DMA to obtain transmitted data directly from memory. -//! -//! \return None -// -//***************************************************************************** -extern uint32_t UART_getTransmitBufferAddressForDMA(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Sets the deglitch time -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! \param deglitchTime is the selected deglitch time -//! Valid values are -//! - \b EUSCI_A_UART_DEGLITCH_TIME_2ns -//! - \b EUSCI_A_UART_DEGLITCH_TIME_50ns -//! - \b EUSCI_A_UART_DEGLITCH_TIME_100ns -//! - \b EUSCI_A_UART_DEGLITCH_TIME_200ns -//! -//! -//! Returns the address of the UART TX Buffer. This can be used in conjunction -//! with the DMA to obtain transmitted data directly from memory. -//! -//! \return None -// -//***************************************************************************** -extern void UART_selectDeglitchTime(uint32_t moduleInstance, - uint32_t deglitchTime); - -//***************************************************************************** -// -//! Enables individual UART interrupt sources. -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! \param mask is the bit mask of the interrupt sources to be enabled. -//! -//! Enables the indicated UART interrupt sources. The interrupt flag is first -//! and then the corresponding interrupt is enabled. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. -//! -//! The mask parameter is the logical OR of any of the following: -//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT -Receive interrupt -//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt -//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive -//! erroneous-character interrupt enable -//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character interrupt -//! enable -//! -//! Modified register is \b UCAxIFG, \b UCAxIE and \b UCAxCTL1 -//! -//! \return None. -// -//***************************************************************************** -extern void UART_enableInterrupt(uint32_t moduleInstance, uint_fast8_t mask); - -//***************************************************************************** -// -//! Disables individual UART interrupt sources. -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! \param mask is the bit mask of the interrupt sources to be -//! disabled. -//! -//! Disables the indicated UART interrupt sources. Only the sources that -//! are enabled can be reflected to the processor interrupt; disabled sources -//! have no effect on the processor. -//! -//! The mask parameter is the logical OR of any of the following: -//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT -Receive interrupt -//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT - Transmit interrupt -//! - \b EUSCI_A_UART_RECEIVE_ERRONEOUSCHAR_INTERRUPT - Receive -//! erroneous-character interrupt enable -//! - \b EUSCI_A_UART_BREAKCHAR_INTERRUPT - Receive break character interrupt -//! enable -//! -//! Modified register is \b UCAxIFG, \b UCAxIE and \b UCAxCTL1 -//! \return None. -// -//***************************************************************************** -extern void UART_disableInterrupt(uint32_t moduleInstance, uint_fast8_t mask); - -//***************************************************************************** -// -//! Gets the current UART interrupt status. -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! \param mask is the masked interrupt flag status to be returned. -//! Mask value is the logical OR of any of the following: -//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG -//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG -//! - \b EUSCI_A_UART_STARTBIT_INTERRUPT_FLAG -//! - \b EUSCI_A_UART_TRANSMIT_COMPLETE_INTERRUPT_FLAG -//! -//! -//! \return The current interrupt status as an ORed bit mask: -//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG -Receive interrupt flag -//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag -// -//***************************************************************************** -extern uint_fast8_t UART_getInterruptStatus(uint32_t moduleInstance, - uint8_t mask); - -//***************************************************************************** -// -//! Gets the current UART interrupt status masked with the enabled interrupts. -//! This function is useful to call in ISRs to get a list of pending -//! interrupts that are actually enabled and could have caused -//! the ISR. - -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! -//! \return The current interrupt status as an ORed bit mask: -//! - \b EUSCI_A_UART_RECEIVE_INTERRUPT_FLAG -Receive interrupt flag -//! - \b EUSCI_A_UART_TRANSMIT_INTERRUPT_FLAG - Transmit interrupt flag -// -//***************************************************************************** -extern uint_fast8_t UART_getEnabledInterruptStatus(uint32_t moduleInstance); - -//***************************************************************************** -// -//! Clears UART interrupt sources. -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode -//! \param mask is a bit mask of the interrupt sources to be cleared. -//! -//! The UART interrupt source is cleared, so that it no longer asserts. -//! The highest interrupt flag is automatically cleared when an interrupt vector -//! generator is used. -//! -//! The mask parameter has the same definition as the mask parameter to -//! EUSCI_A_UART_enableInterrupt(). -//! -//! Modified register is \b UCAxIFG -//! -//! \return None. -// -//***************************************************************************** -extern void UART_clearInterruptFlag(uint32_t moduleInstance, uint_fast8_t mask); - -//***************************************************************************** -// -//! Registers an interrupt handler for UART interrupts. -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode. -//! -//! \param intHandler is a pointer to the function to be called when the -//! timer capture compare interrupt occurs. -//! -//! This function registers the handler to be called when an UART -//! interrupt occurs. This function enables the global interrupt in the -//! interrupt controller; specific UART interrupts must be enabled -//! via UART_enableInterrupt(). It is the interrupt handler's responsibility to -//! clear the interrupt source via UART_clearInterruptFlag(). -//! -//! \return None. -// -//***************************************************************************** -extern void UART_registerInterrupt(uint32_t moduleInstance, - void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the UART module -//! -//! \param moduleInstance is the instance of the eUSCI A (UART) module. -//! Valid parameters vary from part to part, but can include: -//! - \b EUSCI_A0_BASE -//! - \b EUSCI_A1_BASE -//! - \b EUSCI_A2_BASE -//! - \b EUSCI_A3_BASE -//!
It is important to note that for eUSCI modules, only "A" modules such -//! as EUSCI_A0 can be used. "B" modules such as EUSCI_B0 do not support the -//! UART mode. -//! -//! This function unregisters the handler to be called when timer -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void UART_unregisterInterrupt(uint32_t moduleInstance); - -/* Backwards Compatibility Layer */ -#define EUSCI_A_UART_transmitData UART_transmitData -#define EUSCI_A_UART_receiveData UART_receiveData -#define EUSCI_A_UART_enableInterrupt UART_enableInterrupt -#define EUSCI_A_UART_disableInterrupt UART_disableInterrupt -#define EUSCI_A_UART_getInterruptStatus UART_getInterruptStatus -#define EUSCI_A_UART_clearInterruptFlag UART_clearInterruptFlag -#define EUSCI_A_UART_enable UART_enableModule -#define EUSCI_A_UART_disable UART_disableModule -#define EUSCI_A_UART_queryStatusFlags UART_queryStatusFlags -#define EUSCI_A_UART_setDormant UART_setDormant -#define EUSCI_A_UART_resetDormant UART_resetDormant -#define EUSCI_A_UART_transmitAddress UART_transmitAddress -#define EUSCI_A_UART_transmitBreak UART_transmitBreak -#define EUSCI_A_UART_getReceiveBufferAddressForDMA UART_getReceiveBufferAddressForDMA -#define EUSCI_A_UART_getTransmitBufferAddressForDMA UART_getTransmitBufferAddressForDMA -#define EUSCI_A_UART_selectDeglitchTime UART_selectDeglitchTime - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif /* UART_H_ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/wdt_a.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/wdt_a.c deleted file mode 100644 index 8e96a72f5ce..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/wdt_a.c +++ /dev/null @@ -1,129 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -/* Standard Includes */ -#include - -/* DriverLib Includes */ -#include -#include -#include - -#ifdef __MCU_HAS_SYSCTL_A__ -#include -#else -#include -#endif - - -void WDT_A_holdTimer(void) -{ - //Set Hold bit - uint8_t newWDTStatus = (WDT_A->CTL | WDT_A_CTL_HOLD); - - WDT_A->CTL = WDT_A_CTL_PW + newWDTStatus; -} - -void WDT_A_startTimer(void) -{ - //Reset Hold bit - uint8_t newWDTStatus = (WDT_A->CTL & ~(WDT_A_CTL_HOLD)); - - WDT_A->CTL = WDT_A_CTL_PW + newWDTStatus; -} - -void WDT_A_clearTimer(void) -{ - //Set Counter Clear bit - uint8_t newWDTStatus = (WDT_A->CTL | WDT_A_CTL_CNTCL); - - WDT_A->CTL = WDT_A_CTL_PW + newWDTStatus; -} - -void WDT_A_initWatchdogTimer(uint_fast8_t clockSelect, - uint_fast8_t clockIterations) -{ - WDT_A->CTL = WDT_A_CTL_PW + WDT_A_CTL_CNTCL + WDT_A_CTL_HOLD + - clockSelect + clockIterations; -} - -void WDT_A_initIntervalTimer(uint_fast8_t clockSelect, - uint_fast8_t clockIterations) -{ - - WDT_A->CTL = WDT_A_CTL_PW + WDT_A_CTL_CNTCL + WDT_A_CTL_HOLD + WDT_A_CTL_TMSEL - + clockSelect + clockIterations; -} - -void WDT_A_setPasswordViolationReset(uint_fast8_t resetType) -{ -#ifdef __MCU_HAS_SYSCTL_A__ - SysCtl_A_setWDTPasswordViolationResetType(resetType); -#else - SysCtl_setWDTPasswordViolationResetType(resetType); -#endif -} - -void WDT_A_setTimeoutReset(uint_fast8_t resetType) -{ -#ifdef __MCU_HAS_SYSCTL_A__ - SysCtl_A_setWDTTimeoutResetType(resetType); -#else - SysCtl_setWDTTimeoutResetType(resetType); -#endif -} - -void WDT_A_registerInterrupt(void (*intHandler)(void)) -{ - // - // Register the interrupt handler, returning an error if an error occurs. - // - Interrupt_registerInterrupt(INT_WDT_A, intHandler); - - // - // Enable the system control interrupt. - // - Interrupt_enableInterrupt (INT_WDT_A); -} - -void WDT_A_unregisterInterrupt(void) -{ - // - // Disable the interrupt. - // - Interrupt_disableInterrupt (INT_WDT_A); - - // - // Unregister the interrupt handler. - // - Interrupt_unregisterInterrupt(INT_WDT_A); -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/wdt_a.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/wdt_a.h deleted file mode 100644 index e8c006fbae1..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/driverlib/wdt_a.h +++ /dev/null @@ -1,300 +0,0 @@ -/* --COPYRIGHT--,BSD - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * --/COPYRIGHT--*/ -#ifndef __WATCHDOG_H__ -#define __WATCHDOG_H__ - -//***************************************************************************** -// -//! \addtogroup wdt_api -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -/* Includes */ -#include -#include - -#ifdef __MCU_HAS_SYSCTL_A__ - -#define WDT_A_HARD_RESET SYSCTL_A_HARD_RESET -#define WDT_A_SOFT_RESET SYSCTL_A_SOFT_RESET - -#else - -#define WDT_A_HARD_RESET SYSCTL_HARD_RESET -#define WDT_A_SOFT_RESET SYSCTL_SOFT_RESET - -#endif - -//***************************************************************************** -// -// The following are values that can be passed to the clockSelect parameter for -// functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit(). -// -//***************************************************************************** -#define WDT_A_CLOCKSOURCE_SMCLK (WDT_A_CTL_SSEL_0) -#define WDT_A_CLOCKSOURCE_ACLK (WDT_A_CTL_SSEL_1) -#define WDT_A_CLOCKSOURCE_VLOCLK (WDT_A_CTL_SSEL_2) -#define WDT_A_CLOCKSOURCE_BCLK (WDT_A_CTL_SSEL_3) - -//***************************************************************************** -// -// The following are values that can be passed to the clockDivider parameter -// for functions: WDT_A_watchdogTimerInit(), and WDT_A_intervalTimerInit(). -// -//***************************************************************************** -#define WDT_A_CLOCKDIVIDER_2G (WDT_A_CTL_IS_0) -#define WDT_A_CLOCKDIVIDER_128M (WDT_A_CTL_IS_1) -#define WDT_A_CLOCKDIVIDER_8192K (WDT_A_CTL_IS_2) -#define WDT_A_CLOCKDIVIDER_512K (WDT_A_CTL_IS_3) -#define WDT_A_CLOCKDIVIDER_32K (WDT_A_CTL_IS_4) -#define WDT_A_CLOCKDIVIDER_8192 (WDT_A_CTL_IS_5) -#define WDT_A_CLOCKDIVIDER_512 (WDT_A_CTL_IS_6) -#define WDT_A_CLOCKDIVIDER_64 (WDT_A_CTL_IS_7) -#define WDT_A_CLOCKITERATIONS_2G WDT_A_CLOCKDIVIDER_2G -#define WDT_A_CLOCKITERATIONS_128M WDT_A_CLOCKDIVIDER_128M -#define WDT_A_CLOCKITERATIONS_8192K WDT_A_CLOCKDIVIDER_8192K -#define WDT_A_CLOCKITERATIONS_512K WDT_A_CLOCKDIVIDER_512K -#define WDT_A_CLOCKITERATIONS_32K WDT_A_CLOCKDIVIDER_32K -#define WDT_A_CLOCKITERATIONS_8192 WDT_A_CLOCKDIVIDER_8192 -#define WDT_A_CLOCKITERATIONS_512 WDT_A_CLOCKDIVIDER_512 -#define WDT_A_CLOCKITERATIONS_64 WDT_A_CLOCKDIVIDER_64 - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** - -//***************************************************************************** -// -//! Holds the Watchdog Timer. -//! -//! This function stops the watchdog timer from running. This way no interrupt -//! or PUC is asserted. -//! -//! \return None -// -//***************************************************************************** -extern void WDT_A_holdTimer(void); - -//***************************************************************************** -// -//! Starts the Watchdog Timer. -//! -//! This function starts the watchdog timer functionality to start counting. -//! -//! \return None -// -//***************************************************************************** -extern void WDT_A_startTimer(void); - -//***************************************************************************** -// -//! Clears the timer counter of the Watchdog Timer. -//! -//! This function clears the watchdog timer count to 0x0000h. This function -//! is used to "service the dog" when operating in watchdog mode. -//! -//! \return None -// -//***************************************************************************** -extern void WDT_A_clearTimer(void); - -//***************************************************************************** -// -//! Sets the clock source for the Watchdog Timer in watchdog mode. -//! -//! \param clockSelect is the clock source that the watchdog timer will use. -//! Valid values are -//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default] -//! - \b WDT_A_CLOCKSOURCE_ACLK -//! - \b WDT_A_CLOCKSOURCE_VLOCLK -//! - \b WDT_A_CLOCKSOURCE_BCLK -//! \param clockIterations is the number of clock iterations for a watchdog -//! timeout. -//! Valid values are -//! - \b WDT_A_CLOCKITERATIONS_2G [Default] -//! - \b WDT_A_CLOCKITERATIONS_128M -//! - \b WDT_A_CLOCKITERATIONS_8192K -//! - \b WDT_A_CLOCKITERATIONS_512K -//! - \b WDT_A_CLOCKITERATIONS_32K -//! - \b WDT_A_CLOCKITERATIONS_8192 -//! - \b WDT_A_CLOCKITERATIONS_512 -//! - \b WDT_A_CLOCKITERATIONS_64 -//! -//! This function sets the watchdog timer in watchdog mode, which will cause a -//! PUC when the timer overflows. When in the mode, a PUC can be avoided with a -//! call to WDT_A_resetTimer() before the timer runs out. -//! -//! \return None -// -//***************************************************************************** -extern void WDT_A_initWatchdogTimer(uint_fast8_t clockSelect, - uint_fast8_t clockDivider); - -//***************************************************************************** -// -//! Sets the clock source for the Watchdog Timer in timer interval mode. -//! -//! \param clockSelect is the clock source that the watchdog timer will use. -//! Valid values are -//! - \b WDT_A_CLOCKSOURCE_SMCLK [Default] -//! - \b WDT_A_CLOCKSOURCE_ACLK -//! - \b WDT_A_CLOCKSOURCE_VLOCLK -//! - \b WDT_A_CLOCKSOURCE_BCLK -//! \param clockIterations is the number of clock iterations for a watchdog -//! interval. -//! Valid values are -//! - \b WDT_A_CLOCKITERATIONS_2G [Default] -//! - \b WDT_A_CLOCKITERATIONS_128M -//! - \b WDT_A_CLOCKITERATIONS_8192K -//! - \b WDT_A_CLOCKITERATIONS_512K -//! - \b WDT_A_CLOCKITERATIONS_32K -//! - \b WDT_A_CLOCKITERATIONS_8192 -//! - \b WDT_A_CLOCKITERATIONS_512 -//! - \b WDT_A_CLOCKITERATIONS_64 -//! -//! This function sets the watchdog timer as timer interval mode, which will -//! assert an interrupt without causing a PUC. -//! -//! \return None -// -//***************************************************************************** -extern void WDT_A_initIntervalTimer(uint_fast8_t clockSelect, - uint_fast8_t clockDivider); - -//***************************************************************************** -// -//! Registers an interrupt handler for the watchdog interrupt. -//! -//! \param intHandler is a pointer to the function to be called when the -//! watchdog interrupt occurs. -//! -//! \return None. -// -//***************************************************************************** -extern void WDT_A_registerInterrupt(void (*intHandler)(void)); - -//***************************************************************************** -// -//! Unregisters the interrupt handler for the watchdog. -//! -//! This function unregisters the handler to be called when a watchdog -//! interrupt occurs. This function also masks off the interrupt in the -//! interrupt controller so that the interrupt handler no longer is called. -//! -//! \sa Interrupt_registerInterrupt() for important information about -//! registering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -extern void WDT_A_unregisterInterrupt(void); - -//***************************************************************************** -// -//! Sets the type of RESET that happens when a watchdog password violation -//! occurs. -//! -//! \param resetType The type of reset to set -//! -//! The \e resetType parameter must be only one of the following values: -//! - \b WDT_A_HARD_RESET -//! - \b WDT_A_SOFT_RESET -//! -//! \return None. -// -// -//***************************************************************************** -extern void WDT_A_setPasswordViolationReset(uint_fast8_t resetType); - -//***************************************************************************** -// -//! Sets the type of RESET that happens when a watchdog timeout occurs. -//! -//! \param resetType The type of reset to set -//! -//! The \e resetType parameter must be only one of the following values: -//! - \b WDT_A_HARD_RESET -//! - \b WDT_A_SOFT_RESET -//! -//! \return None. -// -// -//***************************************************************************** -extern void WDT_A_setTimeoutReset(uint_fast8_t resetType); - -/* Defines for future devices that might have multiple instances */ -#define WDT_A_holdTimerMultipleTimer(a) WDT_A_holdTimer() -#define WDT_A_startTimerMultipleTimer(a) WDT_A_startTimer() -#define WDT_A_resetTimerMultipleTimer(a) WDT_A_clearTimer() -#define WDT_A_initWatchdogTimerMultipleTimer(a,b,c) WDT_A_initWatchdogTimer(b,c) -#define WDT_A_initIntervalTimerMultipleTimer(a,b,c) WDT_A_initIntervalTimer(b,c) -#define WDT_A_registerInterruptMultipleTimer(a,b) WDT_A_registerInterrupt(b) -#define WDT_A_unregisterInterruptMultipleTimer(a) WDT_A_unregisterInterrupt() - -/* Backwards compatibility layer */ -#define WDT_A_hold WDT_A_holdTimerMultipleTimer -#define WDT_A_start WDT_A_startTimerMultipleTimer -#define WDT_A_resetTimer WDT_A_resetTimerMultipleTimer -#define WDT_A_watchdogTimerInit WDT_A_initWatchdogTimerMultipleTimer -#define WDT_A_intervalTimerInit WDT_A_initIntervalTimerMultipleTimer - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// -// Close the Doxygen group. -//! @} -// -//***************************************************************************** - -#endif // __WATCHDOG_H__ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp.h deleted file mode 100644 index 50cda78fc36..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp.h +++ /dev/null @@ -1,61 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432 Family Generic Include File -* -* File creation date: 08/03/17 -* -******************************************************************************/ -#ifndef __MSP432_H__ -#define __MSP432_H__ -/****************************************************************************** -* MSP432 devices * -******************************************************************************/ -#if defined (__MSP432P401R__) -#include "msp432p401r.h" -#elif defined (__MSP432P401M__) -#include "msp432p401m.h" -#elif defined (__MSP432P411V__) -#include "msp432p411v.h" -#elif defined (__MSP432P4111__) -#include "msp432p4111.h" -#elif defined (__MSP432P4XX__) -#include "msp432p4xx.h" -#elif defined (__MSP432P411Y__) -#include "msp432p411y.h" -/****************************************************************************** -* Failed to match a default include file * -******************************************************************************/ -#else -#error "Failed to match a default include file" -#endif -#endif /* __MSP432_H__ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432.h deleted file mode 100644 index 50cda78fc36..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432.h +++ /dev/null @@ -1,61 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432 Family Generic Include File -* -* File creation date: 08/03/17 -* -******************************************************************************/ -#ifndef __MSP432_H__ -#define __MSP432_H__ -/****************************************************************************** -* MSP432 devices * -******************************************************************************/ -#if defined (__MSP432P401R__) -#include "msp432p401r.h" -#elif defined (__MSP432P401M__) -#include "msp432p401m.h" -#elif defined (__MSP432P411V__) -#include "msp432p411v.h" -#elif defined (__MSP432P4111__) -#include "msp432p4111.h" -#elif defined (__MSP432P4XX__) -#include "msp432p4xx.h" -#elif defined (__MSP432P411Y__) -#include "msp432p411y.h" -/****************************************************************************** -* Failed to match a default include file * -******************************************************************************/ -#else -#error "Failed to match a default include file" -#endif -#endif /* __MSP432_H__ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p401m.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p401m.h deleted file mode 100644 index f18366fe0af..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p401m.h +++ /dev/null @@ -1,6941 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432P401M Register Definitions -* -* This file includes CMSIS compliant component and register definitions -* -* For legacy components the definitions that are compatible with MSP430 code, -* are included with msp432p401m_classic.h -* -* With CMSIS definitions, the register defines have been reformatted: -* ModuleName[ModuleInstance]->RegisterName -* -* Writing to CMSIS bit fields can be done through register level -* or via bitband area access: -* - ADC14->CTL0 |= ADC14_CTL0_ENC; -* - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1; -* -* File creation date: 2017-08-03 -* -******************************************************************************/ - -#ifndef __MSP432P401M_H__ -#define __MSP432P401M_H__ - -/* Use standard integer types with explicit width */ -#include - -#ifdef __cplusplus - extern "C" { -#endif - -#define __MSP432_HEADER_VERSION__ 3202 - -/* Remap MSP432 intrinsics to ARM equivalents */ -#include "msp_compatibility.h" - -/****************************************************************************** -* include MSP430 legacy definitions to make porting of code from MSP430 * -* code base easier * -* With fully CMSIS compliant code, NO_MSP_CLASSIC_DEFINES may be defined in * -* your project to omit including the classic defines * -******************************************************************************/ -#ifndef NO_MSP_CLASSIC_DEFINES -#include "msp432p401m_classic.h" -#endif - - -#ifndef __CMSIS_CONFIG__ -#define __CMSIS_CONFIG__ - -/** @addtogroup MSP432P401M_Definitions MSP432P401M Definitions - This file defines all structures and symbols for MSP432P401M: - - components and registers - - peripheral base address - - peripheral ID - - Peripheral definitions - @{ -*/ - -/****************************************************************************** -* Processor and Core Peripherals * -******************************************************************************/ -/** @addtogroup MSP432P401M_CMSIS Device CMSIS Definitions - Configuration of the Cortex-M4 Processor and Core Peripherals - @{ -*/ - -/****************************************************************************** -* CMSIS-compatible Interrupt Number Definition * -******************************************************************************/ -typedef enum IRQn -{ - /* Cortex-M4 Processor Exceptions Numbers */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - /* Peripheral Exceptions Numbers */ - PSS_IRQn = 0, /* 16 PSS Interrupt */ - CS_IRQn = 1, /* 17 CS Interrupt */ - PCM_IRQn = 2, /* 18 PCM Interrupt */ - WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */ - FPU_IRQn = 4, /* 20 FPU Interrupt */ - FLCTL_IRQn = 5, /* 21 Flash Controller Interrupt*/ - COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */ - COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */ - TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */ - TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */ - TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */ - TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */ - TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */ - TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */ - TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */ - TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */ - EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */ - EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */ - EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */ - EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */ - EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */ - EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */ - EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */ - EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */ - ADC14_IRQn = 24, /* 40 ADC14 Interrupt */ - T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */ - T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */ - T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */ - AES256_IRQn = 28, /* 44 AES256 Interrupt */ - RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */ - DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */ - DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */ - DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */ - DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */ - DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */ - PORT1_IRQn = 35, /* 51 Port1 Interrupt */ - PORT2_IRQn = 36, /* 52 Port2 Interrupt */ - PORT3_IRQn = 37, /* 53 Port3 Interrupt */ - PORT4_IRQn = 38, /* 54 Port4 Interrupt */ - PORT5_IRQn = 39, /* 55 Port5 Interrupt */ - PORT6_IRQn = 40 /* 56 Port6 Interrupt */ -} IRQn_Type; - -/****************************************************************************** -* Processor and Core Peripheral Section * -******************************************************************************/ -#define __CM4_REV 0x0001 /* Core revision r0p1 */ -#define __MPU_PRESENT 1 /* MPU present or not */ -#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /* FPU present or not */ - -/****************************************************************************** -* Available Peripherals * -******************************************************************************/ -#define __MCU_HAS_ADC14__ /*!< Module ADC14 is available */ -#define __MCU_HAS_AES256__ /*!< Module AES256 is available */ -#define __MCU_HAS_CAPTIO0__ /*!< Module CAPTIO0 is available */ -#define __MCU_HAS_CAPTIO1__ /*!< Module CAPTIO1 is available */ -#define __MCU_HAS_COMP_E0__ /*!< Module COMP_E0 is available */ -#define __MCU_HAS_COMP_E1__ /*!< Module COMP_E1 is available */ -#define __MCU_HAS_CRC32__ /*!< Module CRC32 is available */ -#define __MCU_HAS_CS__ /*!< Module CS is available */ -#define __MCU_HAS_DIO__ /*!< Module DIO is available */ -#define __MCU_HAS_DMA__ /*!< Module DMA is available */ -#define __MCU_HAS_EUSCI_A0__ /*!< Module EUSCI_A0 is available */ -#define __MCU_HAS_EUSCI_A1__ /*!< Module EUSCI_A1 is available */ -#define __MCU_HAS_EUSCI_A2__ /*!< Module EUSCI_A2 is available */ -#define __MCU_HAS_EUSCI_A3__ /*!< Module EUSCI_A3 is available */ -#define __MCU_HAS_EUSCI_B0__ /*!< Module EUSCI_B0 is available */ -#define __MCU_HAS_EUSCI_B1__ /*!< Module EUSCI_B1 is available */ -#define __MCU_HAS_EUSCI_B2__ /*!< Module EUSCI_B2 is available */ -#define __MCU_HAS_EUSCI_B3__ /*!< Module EUSCI_B3 is available */ -#define __MCU_HAS_FLCTL__ /*!< Module FLCTL is available */ -#define __MCU_HAS_FL_BOOTOVER_MAILBOX__ /*!< Module FL_BOOTOVER_MAILBOX is available */ -#define __MCU_HAS_PCM__ /*!< Module PCM is available */ -#define __MCU_HAS_PMAP__ /*!< Module PMAP is available */ -#define __MCU_HAS_PSS__ /*!< Module PSS is available */ -#define __MCU_HAS_REF_A__ /*!< Module REF_A is available */ -#define __MCU_HAS_RSTCTL__ /*!< Module RSTCTL is available */ -#define __MCU_HAS_RTC_C__ /*!< Module RTC_C is available */ -#define __MCU_HAS_SYSCTL__ /*!< Module SYSCTL is available */ -#define __MCU_HAS_TIMER32__ /*!< Module TIMER32 is available */ -#define __MCU_HAS_TIMER_A0__ /*!< Module TIMER_A0 is available */ -#define __MCU_HAS_TIMER_A1__ /*!< Module TIMER_A1 is available */ -#define __MCU_HAS_TIMER_A2__ /*!< Module TIMER_A2 is available */ -#define __MCU_HAS_TIMER_A3__ /*!< Module TIMER_A3 is available */ -#define __MCU_HAS_TLV__ /*!< Module TLV is available */ -#define __MCU_HAS_WDT_A__ /*!< Module WDT_A is available */ - -/* Definitions to show that specific ports are available */ - -#define __MSP432_HAS_PORTA_R__ -#define __MSP432_HAS_PORTB_R__ -#define __MSP432_HAS_PORTC_R__ -#define __MSP432_HAS_PORTD_R__ -#define __MSP432_HAS_PORTE_R__ -#define __MSP432_HAS_PORTJ_R__ - -#define __MSP432_HAS_PORT1_R__ -#define __MSP432_HAS_PORT2_R__ -#define __MSP432_HAS_PORT3_R__ -#define __MSP432_HAS_PORT4_R__ -#define __MSP432_HAS_PORT5_R__ -#define __MSP432_HAS_PORT6_R__ -#define __MSP432_HAS_PORT7_R__ -#define __MSP432_HAS_PORT8_R__ -#define __MSP432_HAS_PORT9_R__ -#define __MSP432_HAS_PORT10_R__ - - -/*@}*/ /* end of group MSP432P401M_CMSIS */ - -/* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */ -#ifdef __TI_ARM__ -/* disable the TI ULP advisor check for the core header file definitions */ -#pragma diag_push -#pragma CHECK_ULP("none") -#include "core_cm4.h" -#pragma diag_pop -#else -#include "core_cm4.h" -#endif - -/* System Header */ -#include "system_msp432p401m.h" - -/****************************************************************************** -* Definition of standard bits * -******************************************************************************/ -#define BIT0 (uint16_t)(0x0001) -#define BIT1 (uint16_t)(0x0002) -#define BIT2 (uint16_t)(0x0004) -#define BIT3 (uint16_t)(0x0008) -#define BIT4 (uint16_t)(0x0010) -#define BIT5 (uint16_t)(0x0020) -#define BIT6 (uint16_t)(0x0040) -#define BIT7 (uint16_t)(0x0080) -#define BIT8 (uint16_t)(0x0100) -#define BIT9 (uint16_t)(0x0200) -#define BITA (uint16_t)(0x0400) -#define BITB (uint16_t)(0x0800) -#define BITC (uint16_t)(0x1000) -#define BITD (uint16_t)(0x2000) -#define BITE (uint16_t)(0x4000) -#define BITF (uint16_t)(0x8000) - -/****************************************************************************** -* Device and peripheral memory map * -******************************************************************************/ -/** @addtogroup MSP432P401M_MemoryMap MSP432P401M Memory Mapping - @{ -*/ - -#define FLASH_BASE ((uint32_t)0x00000000) /*!< Main Flash memory start address */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM memory start address */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripherals start address */ -#define PERIPH_BASE2 ((uint32_t)0xE0000000) /*!< Peripherals start address */ - -#define ADC14_BASE (PERIPH_BASE +0x00012000) /*!< Base address of module ADC14 registers */ -#define AES256_BASE (PERIPH_BASE +0x00003C00) /*!< Base address of module AES256 registers */ -#define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /*!< Base address of module CAPTIO0 registers */ -#define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /*!< Base address of module CAPTIO1 registers */ -#define COMP_E0_BASE (PERIPH_BASE +0x00003400) /*!< Base address of module COMP_E0 registers */ -#define COMP_E1_BASE (PERIPH_BASE +0x00003800) /*!< Base address of module COMP_E1 registers */ -#define CRC32_BASE (PERIPH_BASE +0x00004000) /*!< Base address of module CRC32 registers */ -#define CS_BASE (PERIPH_BASE +0x00010400) /*!< Base address of module CS registers */ -#define DIO_BASE (PERIPH_BASE +0x00004C00) /*!< Base address of module DIO registers */ -#define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address of module DMA registers */ -#define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define FLCTL_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL registers */ -#define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000) /*!< Base address of module FL_BOOTOVER_MAILBOX registers */ -#define PCM_BASE (PERIPH_BASE +0x00010000) /*!< Base address of module PCM registers */ -#define PMAP_BASE (PERIPH_BASE +0x00005000) /*!< Base address of module PMAP registers */ -#define PSS_BASE (PERIPH_BASE +0x00010800) /*!< Base address of module PSS registers */ -#define REF_A_BASE (PERIPH_BASE +0x00003000) /*!< Base address of module REF_A registers */ -#define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /*!< Base address of module RSTCTL registers */ -#define RTC_C_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define SYSCTL_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL registers */ -#define TIMER32_BASE (PERIPH_BASE +0x0000C000) /*!< Base address of module TIMER32 registers */ -#define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /*!< Base address of module TIMER_A0 registers */ -#define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /*!< Base address of module TIMER_A1 registers */ -#define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /*!< Base address of module TIMER_A2 registers */ -#define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /*!< Base address of module TIMER_A3 registers */ -#define TLV_BASE ((uint32_t)0x00201000) /*!< Base address of module TLV registers */ -#define WDT_A_BASE (PERIPH_BASE +0x00004800) /*!< Base address of module WDT_A registers */ - - -/*@}*/ /* end of group MSP432P401M_MemoryMap */ - -/****************************************************************************** -* Definitions for bit band access * -******************************************************************************/ -#define BITBAND_SRAM_BASE ((uint32_t)(0x22000000)) -#define BITBAND_PERI_BASE ((uint32_t)(0x42000000)) - -/* SRAM allows 32 bit bit band access */ -#define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4))) -/* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */ -#define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4))) - -/****************************************************************************** -* Peripheral register definitions * -******************************************************************************/ -/** @addtogroup MSP432P401M_Peripherals MSP432P401M Peripherals - MSP432P401M Device Specific Peripheral registers structures - @{ -*/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - -/****************************************************************************** -* ADC14 Registers -******************************************************************************/ -/** @addtogroup ADC14 MSP432P401M (ADC14) - @{ -*/ -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t LO0; /*!< Window Comparator Low Threshold 0 Register */ - __IO uint32_t HI0; /*!< Window Comparator High Threshold 0 Register */ - __IO uint32_t LO1; /*!< Window Comparator Low Threshold 1 Register */ - __IO uint32_t HI1; /*!< Window Comparator High Threshold 1 Register */ - __IO uint32_t MCTL[32]; /*!< Conversion Memory Control Register */ - __IO uint32_t MEM[32]; /*!< Conversion Memory Register */ - uint32_t RESERVED0[9]; - __IO uint32_t IER0; /*!< Interrupt Enable 0 Register */ - __IO uint32_t IER1; /*!< Interrupt Enable 1 Register */ - __I uint32_t IFGR0; /*!< Interrupt Flag 0 Register */ - __I uint32_t IFGR1; /*!< Interrupt Flag 1 Register */ - __O uint32_t CLRIFGR0; /*!< Clear Interrupt Flag 0 Register */ - __IO uint32_t CLRIFGR1; /*!< Clear Interrupt Flag 1 Register */ - __IO uint32_t IV; /*!< Interrupt Vector Register */ -} ADC14_Type; - -/*@}*/ /* end of group ADC14 */ - - -/****************************************************************************** -* AES256 Registers -******************************************************************************/ -/** @addtogroup AES256 MSP432P401M (AES256) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< AES Accelerator Control Register 0 */ - __IO uint16_t CTL1; /*!< AES Accelerator Control Register 1 */ - __IO uint16_t STAT; /*!< AES Accelerator Status Register */ - __O uint16_t KEY; /*!< AES Accelerator Key Register */ - __O uint16_t DIN; /*!< AES Accelerator Data In Register */ - __O uint16_t DOUT; /*!< AES Accelerator Data Out Register */ - __O uint16_t XDIN; /*!< AES Accelerator XORed Data In Register */ - __O uint16_t XIN; /*!< AES Accelerator XORed Data In Register */ -} AES256_Type; - -/*@}*/ /* end of group AES256 */ - - -/****************************************************************************** -* CAPTIO Registers -******************************************************************************/ -/** @addtogroup CAPTIO MSP432P401M (CAPTIO) - @{ -*/ -typedef struct { - uint16_t RESERVED0[7]; - __IO uint16_t CTL; /*!< Capacitive Touch IO x Control Register */ -} CAPTIO_Type; - -/*@}*/ /* end of group CAPTIO */ - - -/****************************************************************************** -* COMP_E Registers -******************************************************************************/ -/** @addtogroup COMP_E MSP432P401M (COMP_E) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< Comparator Control Register 0 */ - __IO uint16_t CTL1; /*!< Comparator Control Register 1 */ - __IO uint16_t CTL2; /*!< Comparator Control Register 2 */ - __IO uint16_t CTL3; /*!< Comparator Control Register 3 */ - uint16_t RESERVED0[2]; - __IO uint16_t INT; /*!< Comparator Interrupt Control Register */ - __I uint16_t IV; /*!< Comparator Interrupt Vector Word Register */ -} COMP_E_Type; - -/*@}*/ /* end of group COMP_E */ - - -/****************************************************************************** -* CRC32 Registers -******************************************************************************/ -/** @addtogroup CRC32 MSP432P401M (CRC32) - @{ -*/ -typedef struct { - __IO uint16_t DI32; /*!< Data Input for CRC32 Signature Computation */ - uint16_t RESERVED0; - __IO uint16_t DIRB32; /*!< Data In Reverse for CRC32 Computation */ - uint16_t RESERVED1; - __IO uint16_t INIRES32_LO; /*!< CRC32 Initialization and Result, lower 16 bits */ - __IO uint16_t INIRES32_HI; /*!< CRC32 Initialization and Result, upper 16 bits */ - __IO uint16_t RESR32_LO; /*!< CRC32 Result Reverse, lower 16 bits */ - __IO uint16_t RESR32_HI; /*!< CRC32 Result Reverse, Upper 16 bits */ - __IO uint16_t DI16; /*!< Data Input for CRC16 computation */ - uint16_t RESERVED2; - __IO uint16_t DIRB16; /*!< CRC16 Data In Reverse */ - uint16_t RESERVED3; - __IO uint16_t INIRES16; /*!< CRC16 Initialization and Result register */ - uint16_t RESERVED4[2]; - __IO uint16_t RESR16; /*!< CRC16 Result Reverse */ -} CRC32_Type; - -/*@}*/ /* end of group CRC32 */ - - -/****************************************************************************** -* CS Registers -******************************************************************************/ -/** @addtogroup CS MSP432P401M (CS) - @{ -*/ -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t CTL2; /*!< Control 2 Register */ - __IO uint32_t CTL3; /*!< Control 3 Register */ - uint32_t RESERVED0[7]; - __IO uint32_t CLKEN; /*!< Clock Enable Register */ - __I uint32_t STAT; /*!< Status Register */ - uint32_t RESERVED1[2]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - uint32_t RESERVED2; - __I uint32_t IFG; /*!< Interrupt Flag Register */ - uint32_t RESERVED3; - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - uint32_t RESERVED4; - __O uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - uint32_t RESERVED5; - __IO uint32_t DCOERCAL0; /*!< DCO External Resistor Cailbration 0 Register */ - __IO uint32_t DCOERCAL1; /*!< DCO External Resistor Calibration 1 Register */ -} CS_Type; - -/*@}*/ /* end of group CS */ - - -/****************************************************************************** -* DIO Registers -******************************************************************************/ -/** @addtogroup DIO MSP432P401R (DIO) - @{ -*/ -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - __I uint16_t IV_L; /*!< Low Port Interrupt Vector Value */ - uint16_t RESERVED0[3]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; - union { - __IO uint16_t IES; /*!< Port Pair Interrupt Edge Select */ - struct { - __IO uint8_t IES_L; /*!< Low Port Interrupt Edge Select */ - __IO uint8_t IES_H; /*!< High Port Interrupt Edge Select */ - }; - }; - union { - __IO uint16_t IE; /*!< Port Pair Interrupt Enable */ - struct { - __IO uint8_t IE_L; /*!< Low Port Interrupt Enable */ - __IO uint8_t IE_H; /*!< High Port Interrupt Enable */ - }; - }; - union { - __IO uint16_t IFG; /*!< Port Pair Interrupt Flag */ - struct { - __IO uint8_t IFG_L; /*!< Low Port Interrupt Flag */ - __IO uint8_t IFG_H; /*!< High Port Interrupt Flag */ - }; - }; - __I uint16_t IV_H; /*!< High Port Interrupt Vector Value */ -} DIO_PORT_Interruptable_Type; - -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - uint16_t RESERVED0[4]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; -} DIO_PORT_Not_Interruptable_Type; - - -typedef struct { - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED0; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED1; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED2; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED3; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED4; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED5; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED6; - __I uint16_t IV; /*!< Port Interrupt Vector Value */ - uint8_t RESERVED7[6]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ -} DIO_PORT_Odd_Interruptable_Type; - -typedef struct { - uint8_t RESERVED0; - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED1; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED2; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED3; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED4; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED5; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED6; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED7[9]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ - __I uint16_t IV; /*!< Port Interrupt Vector Value */ -} DIO_PORT_Even_Interruptable_Type; - -/*@}*/ /* end of group MSP432P401R_DIO */ - - -/****************************************************************************** -* DMA Registers -******************************************************************************/ -/** @addtogroup DMA MSP432P401R (DMA) - @{ -*/ -typedef struct { - __I uint32_t DEVICE_CFG; /*!< Device Configuration Status */ - __IO uint32_t SW_CHTRIG; /*!< Software Channel Trigger Register */ - uint32_t RESERVED0[2]; - __IO uint32_t CH_SRCCFG[32]; /*!< Channel n Source Configuration Register */ - uint32_t RESERVED1[28]; - __IO uint32_t INT1_SRCCFG; /*!< Interrupt 1 Source Channel Configuration */ - __IO uint32_t INT2_SRCCFG; /*!< Interrupt 2 Source Channel Configuration Register */ - __IO uint32_t INT3_SRCCFG; /*!< Interrupt 3 Source Channel Configuration Register */ - uint32_t RESERVED2; - __I uint32_t INT0_SRCFLG; /*!< Interrupt 0 Source Channel Flag Register */ - __O uint32_t INT0_CLRFLG; /*!< Interrupt 0 Source Channel Clear Flag Register */ -} DMA_Channel_Type; - -typedef struct { - __I uint32_t STAT; /*!< Status Register */ - __O uint32_t CFG; /*!< Configuration Register */ - __IO uint32_t CTLBASE; /*!< Channel Control Data Base Pointer Register */ - __I uint32_t ALTBASE; /*!< Channel Alternate Control Data Base Pointer Register */ - __I uint32_t WAITSTAT; /*!< Channel Wait on Request Status Register */ - __O uint32_t SWREQ; /*!< Channel Software Request Register */ - __IO uint32_t USEBURSTSET; /*!< Channel Useburst Set Register */ - __O uint32_t USEBURSTCLR; /*!< Channel Useburst Clear Register */ - __IO uint32_t REQMASKSET; /*!< Channel Request Mask Set Register */ - __O uint32_t REQMASKCLR; /*!< Channel Request Mask Clear Register */ - __IO uint32_t ENASET; /*!< Channel Enable Set Register */ - __O uint32_t ENACLR; /*!< Channel Enable Clear Register */ - __IO uint32_t ALTSET; /*!< Channel Primary-Alternate Set Register */ - __O uint32_t ALTCLR; /*!< Channel Primary-Alternate Clear Register */ - __IO uint32_t PRIOSET; /*!< Channel Priority Set Register */ - __O uint32_t PRIOCLR; /*!< Channel Priority Clear Register */ - uint32_t RESERVED4[3]; - __IO uint32_t ERRCLR; /*!< Bus Error Clear Register */ -} DMA_Control_Type; - -/*@}*/ /* end of group DMA */ - - -/****************************************************************************** -* EUSCI_A Registers -******************************************************************************/ -/** @addtogroup EUSCI_A MSP432P401M (EUSCI_A) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Ax Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Ax Baud Rate Control Word Register */ - __IO uint16_t MCTLW; /*!< eUSCI_Ax Modulation Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Ax Status Register */ - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - __IO uint16_t ABCTL; /*!< eUSCI_Ax Auto Baud Rate Control Register */ - __IO uint16_t IRCTL; /*!< eUSCI_Ax IrDA Control Word Register */ - uint16_t RESERVED1[3]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_Type; - -/*@}*/ /* end of group EUSCI_A */ - -/** @addtogroup EUSCI_A_SPI MSP432P401M (EUSCI_A_SPI) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Ax Bit Rate Control Register 1 */ - uint16_t RESERVED1; - __IO uint16_t STATW; - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - uint16_t RESERVED2[5]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_SPI_Type; - -/*@}*/ /* end of group EUSCI_A_SPI */ - - -/****************************************************************************** -* EUSCI_B Registers -******************************************************************************/ -/** @addtogroup EUSCI_B MSP432P401M (EUSCI_B) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Bx Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Bx Baud Rate Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Bx Status Register */ - __IO uint16_t TBCNT; /*!< eUSCI_Bx Byte Counter Threshold Register */ - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED1[2]; - __IO uint16_t I2COA0; /*!< eUSCI_Bx I2C Own Address 0 Register */ - __IO uint16_t I2COA1; /*!< eUSCI_Bx I2C Own Address 1 Register */ - __IO uint16_t I2COA2; /*!< eUSCI_Bx I2C Own Address 2 Register */ - __IO uint16_t I2COA3; /*!< eUSCI_Bx I2C Own Address 3 Register */ - __I uint16_t ADDRX; /*!< eUSCI_Bx I2C Received Address Register */ - __IO uint16_t ADDMASK; /*!< eUSCI_Bx I2C Address Mask Register */ - __IO uint16_t I2CSA; /*!< eUSCI_Bx I2C Slave Address Register */ - uint16_t RESERVED2[4]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_Type; - -/*@}*/ /* end of group EUSCI_B */ - -/** @addtogroup EUSCI_B_SPI MSP432P401M (EUSCI_B_SPI) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Bx Bit Rate Control Register 1 */ - __IO uint16_t STATW; - uint16_t RESERVED1; - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED2[13]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_SPI_Type; - -/*@}*/ /* end of group EUSCI_B_SPI */ - - -/****************************************************************************** -* FLCTL Registers -******************************************************************************/ -/** @addtogroup FLCTL MSP432P401M (FLCTL) - @{ -*/ -typedef struct { - __I uint32_t POWER_STAT; /*!< Power Status Register */ - uint32_t RESERVED0[3]; - __IO uint32_t BANK0_RDCTL; /*!< Bank0 Read Control Register */ - __IO uint32_t BANK1_RDCTL; /*!< Bank1 Read Control Register */ - uint32_t RESERVED1[2]; - __IO uint32_t RDBRST_CTLSTAT; /*!< Read Burst/Compare Control and Status Register */ - __IO uint32_t RDBRST_STARTADDR; /*!< Read Burst/Compare Start Address Register */ - __IO uint32_t RDBRST_LEN; /*!< Read Burst/Compare Length Register */ - uint32_t RESERVED2[4]; - __IO uint32_t RDBRST_FAILADDR; /*!< Read Burst/Compare Fail Address Register */ - __IO uint32_t RDBRST_FAILCNT; /*!< Read Burst/Compare Fail Count Register */ - uint32_t RESERVED3[3]; - __IO uint32_t PRG_CTLSTAT; /*!< Program Control and Status Register */ - __IO uint32_t PRGBRST_CTLSTAT; /*!< Program Burst Control and Status Register */ - __IO uint32_t PRGBRST_STARTADDR; /*!< Program Burst Start Address Register */ - uint32_t RESERVED4; - __IO uint32_t PRGBRST_DATA0_0; /*!< Program Burst Data0 Register0 */ - __IO uint32_t PRGBRST_DATA0_1; /*!< Program Burst Data0 Register1 */ - __IO uint32_t PRGBRST_DATA0_2; /*!< Program Burst Data0 Register2 */ - __IO uint32_t PRGBRST_DATA0_3; /*!< Program Burst Data0 Register3 */ - __IO uint32_t PRGBRST_DATA1_0; /*!< Program Burst Data1 Register0 */ - __IO uint32_t PRGBRST_DATA1_1; /*!< Program Burst Data1 Register1 */ - __IO uint32_t PRGBRST_DATA1_2; /*!< Program Burst Data1 Register2 */ - __IO uint32_t PRGBRST_DATA1_3; /*!< Program Burst Data1 Register3 */ - __IO uint32_t PRGBRST_DATA2_0; /*!< Program Burst Data2 Register0 */ - __IO uint32_t PRGBRST_DATA2_1; /*!< Program Burst Data2 Register1 */ - __IO uint32_t PRGBRST_DATA2_2; /*!< Program Burst Data2 Register2 */ - __IO uint32_t PRGBRST_DATA2_3; /*!< Program Burst Data2 Register3 */ - __IO uint32_t PRGBRST_DATA3_0; /*!< Program Burst Data3 Register0 */ - __IO uint32_t PRGBRST_DATA3_1; /*!< Program Burst Data3 Register1 */ - __IO uint32_t PRGBRST_DATA3_2; /*!< Program Burst Data3 Register2 */ - __IO uint32_t PRGBRST_DATA3_3; /*!< Program Burst Data3 Register3 */ - __IO uint32_t ERASE_CTLSTAT; /*!< Erase Control and Status Register */ - __IO uint32_t ERASE_SECTADDR; /*!< Erase Sector Address Register */ - uint32_t RESERVED5[2]; - __IO uint32_t BANK0_INFO_WEPROT; /*!< Information Memory Bank0 Write/Erase Protection Register */ - __IO uint32_t BANK0_MAIN_WEPROT; /*!< Main Memory Bank0 Write/Erase Protection Register */ - uint32_t RESERVED6[2]; - __IO uint32_t BANK1_INFO_WEPROT; /*!< Information Memory Bank1 Write/Erase Protection Register */ - __IO uint32_t BANK1_MAIN_WEPROT; /*!< Main Memory Bank1 Write/Erase Protection Register */ - uint32_t RESERVED7[2]; - __IO uint32_t BMRK_CTLSTAT; /*!< Benchmark Control and Status Register */ - __IO uint32_t BMRK_IFETCH; /*!< Benchmark Instruction Fetch Count Register */ - __IO uint32_t BMRK_DREAD; /*!< Benchmark Data Read Count Register */ - __IO uint32_t BMRK_CMP; /*!< Benchmark Count Compare Register */ - uint32_t RESERVED8[4]; - __IO uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - __IO uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - __I uint32_t READ_TIMCTL; /*!< Read Timing Control Register */ - __I uint32_t READMARGIN_TIMCTL; /*!< Read Margin Timing Control Register */ - __I uint32_t PRGVER_TIMCTL; /*!< Program Verify Timing Control Register */ - __I uint32_t ERSVER_TIMCTL; /*!< Erase Verify Timing Control Register */ - __I uint32_t LKGVER_TIMCTL; /*!< Leakage Verify Timing Control Register */ - __I uint32_t PROGRAM_TIMCTL; /*!< Program Timing Control Register */ - __I uint32_t ERASE_TIMCTL; /*!< Erase Timing Control Register */ - __I uint32_t MASSERASE_TIMCTL; /*!< Mass Erase Timing Control Register */ - __I uint32_t BURSTPRG_TIMCTL; /*!< Burst Program Timing Control Register */ -} FLCTL_Type; - -/*@}*/ /* end of group FLCTL */ - - -/****************************************************************************** -* FL_BOOTOVER_MAILBOX Registers -******************************************************************************/ -/** @addtogroup SEC_ZONE_PARAMS MSP432P401M (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t SEC_ZONE_SECEN; /*!< IP Protection Secure Zone Enable. */ - __IO uint32_t SEC_ZONE_START_ADDR; /*!< Start address of IP protected secure zone. */ - __IO uint32_t SEC_ZONE_LENGTH; /*!< Length of IP protected secure zone in number of bytes. */ - __IO uint32_t SEC_ZONE_AESINIT_VECT[4]; /*!< IP protected secure zone 0 AES initialization vector */ - __IO uint32_t SEC_ZONE_SECKEYS[8]; /*!< AES-CBC security keys. */ - __IO uint32_t SEC_ZONE_UNENC_PWD[4]; /*!< Unencrypted password for authentication. */ - __IO uint32_t SEC_ZONE_ENCUPDATE_EN; /*!< IP Protected Secure Zone Encrypted In-field Update Enable */ - __IO uint32_t SEC_ZONE_DATA_EN; /*!< IP Protected Secure Zone Data Access Enable */ - __IO uint32_t SEC_ZONE_ACK; /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */ - uint32_t RESERVED0[2]; -} SEC_ZONE_PARAMS_Type; - -/*@}*/ /* end of group SEC_ZONE_PARAMS */ - -/** @addtogroup SEC_ZONE_UPDATE MSP432P401M (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t SEC_ZONE_PAYLOADADDR; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t SEC_ZONE_PAYLOADLEN; /*!< Length of the payload in bytes. */ - __IO uint32_t SEC_ZONE_UPDATE_ACK; /*!< Acknowledgment for the IP Protected Secure Zone Update Command */ - uint32_t RESERVED0; -} SEC_ZONE_UPDATE_Type; - -/*@}*/ /* end of group SEC_ZONE_UPDATE */ - -/** @addtogroup FL_BOOTOVER_MAILBOX MSP432P401M (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t MB_START; /*!< Flash MailBox start: 0x0115ACF6 */ - __IO uint32_t CMD; /*!< Command for Boot override operations. */ - uint32_t RESERVED0[2]; - __IO uint32_t JTAG_SWD_LOCK_SECEN; /*!< JTAG and SWD Lock Enable */ - __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4]; /*!< JTAG and SWD lock AES initialization vector for AES-CBC */ - __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8]; /*!< JTAG and SWD lock AES CBC security Keys 0-7. */ - __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4]; /*!< JTAG and SWD lock unencrypted password */ - __IO uint32_t JTAG_SWD_LOCK_ACK; /*!< Acknowledgment for JTAG and SWD Lock command */ - uint32_t RESERVED1[2]; - SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4]; - __IO uint32_t BSL_ENABLE; /*!< BSL Enable. */ - __IO uint32_t BSL_START_ADDRESS; /*!< Contains the pointer to the BSL function. */ - __IO uint32_t BSL_PARAMETERS; /*!< BSL hardware invoke conifguration field. */ - uint32_t RESERVED2[2]; - __IO uint32_t BSL_ACK; /*!< Acknowledgment for the BSL Configuration Command */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN; /*!< Length of the encrypted payload in bytes */ - __IO uint32_t JTAG_SWD_LOCK_DST_ADDR; /*!< Destination address where the final data needs to be stored into the device. */ - __IO uint32_t ENC_UPDATE_ACK; /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */ - uint32_t RESERVED3; - SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4]; - uint32_t RESERVED4; - __IO uint32_t FACTORY_RESET_ENABLE; /*!< Enable/Disable Factory Reset */ - __IO uint32_t FACTORY_RESET_PWDEN; /*!< Factory reset password enable */ - __IO uint32_t FACTORY_RESET_PWD[4]; /*!< 128-bit Password for factory reset to be saved into the device. */ - __IO uint32_t FACTORY_RESET_PARAMS_ACK; /*!< Acknowledgment for the Factory Reset Params Command */ - uint32_t RESERVED5; - __IO uint32_t FACTORY_RESET_PASSWORD[4]; /*!< 128-bit Password for factory reset. */ - __IO uint32_t FACTORY_RESET_ACK; /*!< Acknowledgment for the Factory Reset Command */ - uint32_t RESERVED6[2]; - __IO uint32_t MB_END; /*!< Mailbox end */ -} FL_BOOTOVER_MAILBOX_Type; - -/*@}*/ /* end of group FL_BOOTOVER_MAILBOX */ - - -/****************************************************************************** -* PCM Registers -******************************************************************************/ -/** @addtogroup PCM MSP432P401M (PCM) - @{ -*/ -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PCM_Type; - -/*@}*/ /* end of group PCM */ - - -/****************************************************************************** -* PMAP Registers -******************************************************************************/ -/** @addtogroup PMAP MSP432P401R (PMAP) - @{ -*/ -typedef struct { - __IO uint16_t KEYID; - __IO uint16_t CTL; -} PMAP_COMMON_Type; - -typedef struct { - union { - __IO uint16_t PMAP_REGISTER[4]; - struct { - __IO uint8_t PMAP_REGISTER0; - __IO uint8_t PMAP_REGISTER1; - __IO uint8_t PMAP_REGISTER2; - __IO uint8_t PMAP_REGISTER3; - __IO uint8_t PMAP_REGISTER4; - __IO uint8_t PMAP_REGISTER5; - __IO uint8_t PMAP_REGISTER6; - __IO uint8_t PMAP_REGISTER7; - }; - }; -} PMAP_REGISTER_Type; - -/*@}*/ /* end of group PMAP */ - - -/****************************************************************************** -* PSS Registers -******************************************************************************/ -/** @addtogroup PSS MSP432P401M (PSS) - @{ -*/ -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - uint32_t RESERVED0[11]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PSS_Type; - -/*@}*/ /* end of group PSS */ - - -/****************************************************************************** -* REF_A Registers -******************************************************************************/ -/** @addtogroup REF_A MSP432P401M (REF_A) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< REF Control Register 0 */ -} REF_A_Type; - -/*@}*/ /* end of group REF_A */ - - -/****************************************************************************** -* RSTCTL Registers -******************************************************************************/ -/** @addtogroup RSTCTL MSP432P401M (RSTCTL) - @{ -*/ -typedef struct { - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __I uint32_t HARDRESET_STAT; /*!< Hard Reset Status Register */ - __IO uint32_t HARDRESET_CLR; /*!< Hard Reset Status Clear Register */ - __IO uint32_t HARDRESET_SET; /*!< Hard Reset Status Set Register */ - __I uint32_t SOFTRESET_STAT; /*!< Soft Reset Status Register */ - __IO uint32_t SOFTRESET_CLR; /*!< Soft Reset Status Clear Register */ - __IO uint32_t SOFTRESET_SET; /*!< Soft Reset Status Set Register */ - uint32_t RESERVED0[57]; - __I uint32_t PSSRESET_STAT; /*!< PSS Reset Status Register */ - __IO uint32_t PSSRESET_CLR; /*!< PSS Reset Status Clear Register */ - __I uint32_t PCMRESET_STAT; /*!< PCM Reset Status Register */ - __IO uint32_t PCMRESET_CLR; /*!< PCM Reset Status Clear Register */ - __I uint32_t PINRESET_STAT; /*!< Pin Reset Status Register */ - __IO uint32_t PINRESET_CLR; /*!< Pin Reset Status Clear Register */ - __I uint32_t REBOOTRESET_STAT; /*!< Reboot Reset Status Register */ - __IO uint32_t REBOOTRESET_CLR; /*!< Reboot Reset Status Clear Register */ - __I uint32_t CSRESET_STAT; /*!< CS Reset Status Register */ - __IO uint32_t CSRESET_CLR; /*!< CS Reset Status Clear Register */ -} RSTCTL_Type; - -/*@}*/ /* end of group RSTCTL */ - - -/****************************************************************************** -* RTC_C Registers -******************************************************************************/ -/** @addtogroup RTC_C MSP432P401M (RTC_C) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< RTCCTL0 Register */ - __IO uint16_t CTL13; /*!< RTCCTL13 Register */ - __IO uint16_t OCAL; /*!< RTCOCAL Register */ - __IO uint16_t TCMP; /*!< RTCTCMP Register */ - __IO uint16_t PS0CTL; /*!< Real-Time Clock Prescale Timer 0 Control Register */ - __IO uint16_t PS1CTL; /*!< Real-Time Clock Prescale Timer 1 Control Register */ - __IO uint16_t PS; /*!< Real-Time Clock Prescale Timer Counter Register */ - __I uint16_t IV; /*!< Real-Time Clock Interrupt Vector Register */ - __IO uint16_t TIM0; /*!< RTCTIM0 Register Hexadecimal Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week */ - __IO uint16_t DATE; /*!< RTCDATE - Hexadecimal Format */ - __IO uint16_t YEAR; /*!< RTCYEAR Register Hexadecimal Format */ - __IO uint16_t AMINHR; /*!< RTCMINHR - Hexadecimal Format */ - __IO uint16_t ADOWDAY; /*!< RTCADOWDAY - Hexadecimal Format */ - __IO uint16_t BIN2BCD; /*!< Binary-to-BCD Conversion Register */ - __IO uint16_t BCD2BIN; /*!< BCD-to-Binary Conversion Register */ -} RTC_C_Type; - -/*@}*/ /* end of group RTC_C */ - -/** @addtogroup RTC_C_BCD MSP432P401M (RTC_C_BCD) - @{ -*/ -typedef struct { - uint16_t RESERVED0[8]; - __IO uint16_t TIM0; /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week - BCD Format */ - __IO uint16_t DATE; /*!< Real-Time Clock Date - BCD Format */ - __IO uint16_t YEAR; /*!< Real-Time Clock Year Register - BCD Format */ - __IO uint16_t AMINHR; /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */ - __IO uint16_t ADOWDAY; /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */ -} RTC_C_BCD_Type; - -/*@}*/ /* end of group RTC_C_BCD */ - - -/****************************************************************************** -* SYSCTL Registers -******************************************************************************/ -/** @addtogroup SYSCTL MSP432P401R (SYSCTL) - @{ -*/ -typedef struct { - __IO uint32_t REBOOT_CTL; /*!< Reboot Control Register */ - __IO uint32_t NMI_CTLSTAT; /*!< NMI Control and Status Register */ - __IO uint32_t WDTRESET_CTL; /*!< Watchdog Reset Control Register */ - __IO uint32_t PERIHALT_CTL; /*!< Peripheral Halt Control Register */ - __I uint32_t SRAM_SIZE; /*!< SRAM Size Register */ - __IO uint32_t SRAM_BANKEN; /*!< SRAM Bank Enable Register */ - __IO uint32_t SRAM_BANKRET; /*!< SRAM Bank Retention Control Register */ - uint32_t RESERVED0; - __I uint32_t FLASH_SIZE; /*!< Flash Size Register */ - uint32_t RESERVED1[3]; - __IO uint32_t DIO_GLTFLT_CTL; /*!< Digital I/O Glitch Filter Control Register */ - uint32_t RESERVED2[3]; - __IO uint32_t SECDATA_UNLOCK; /*!< IP Protected Secure Zone Data Access Unlock Register */ -} SYSCTL_Type; - -typedef struct { - __IO uint32_t MASTER_UNLOCK; /*!< Master Unlock Register */ - __IO uint32_t BOOTOVER_REQ[2]; /*!< Boot Override Request Register */ - __IO uint32_t BOOTOVER_ACK; /*!< Boot Override Acknowledge Register */ - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __IO uint32_t RESET_STATOVER; /*!< Reset Status and Override Register */ - uint32_t RESERVED7[2]; - __I uint32_t SYSTEM_STAT; /*!< System Status Register */ -} SYSCTL_Boot_Type; - -/*@}*/ /* end of group SYSCTL */ - - -/****************************************************************************** -* Timer32 Registers -******************************************************************************/ -/** @addtogroup Timer32 MSP432P401R (Timer32) - @{ -*/ -typedef struct { - __IO uint32_t LOAD; /*!< Timer Load Register */ - __I uint32_t VALUE; /*!< Timer Current Value Register */ - __IO uint32_t CONTROL; /*!< Timer Control Register */ - __O uint32_t INTCLR; /*!< Timer Interrupt Clear Register */ - __I uint32_t RIS; /*!< Timer Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< Timer Interrupt Status Register */ - __IO uint32_t BGLOAD; /*!< Timer Background Load Register */ -} Timer32_Type; - -/*@}*/ /* end of group Timer32 */ - - -/****************************************************************************** -* Timer_A Registers -******************************************************************************/ -/** @addtogroup Timer_A MSP432P401M (Timer_A) - @{ -*/ -typedef struct { - __IO uint16_t CTL; /*!< TimerAx Control Register */ - __IO uint16_t CCTL[5]; /*!< Timer_A Capture/Compare Control Register */ - uint16_t RESERVED0[2]; - __IO uint16_t R; /*!< TimerA register */ - __IO uint16_t CCR[5]; /*!< Timer_A Capture/Compare Register */ - uint16_t RESERVED1[2]; - __IO uint16_t EX0; /*!< TimerAx Expansion 0 Register */ - uint16_t RESERVED2[6]; - __I uint16_t IV; /*!< TimerAx Interrupt Vector Register */ -} Timer_A_Type; - -/*@}*/ /* end of group Timer_A */ - - -/****************************************************************************** -* TLV Registers -******************************************************************************/ -/** @addtogroup TLV MSP432P401M (TLV) - @{ -*/ -typedef struct { - __I uint32_t TLV_CHECKSUM; /*!< TLV Checksum */ - __I uint32_t DEVICE_INFO_TAG; /*!< Device Info Tag */ - __I uint32_t DEVICE_INFO_LEN; /*!< Device Info Length */ - __I uint32_t DEVICE_ID; /*!< Device ID */ - __I uint32_t HWREV; /*!< HW Revision */ - __I uint32_t BCREV; /*!< Boot Code Revision */ - __I uint32_t ROM_DRVLIB_REV; /*!< ROM Driver Library Revision */ - __I uint32_t DIE_REC_TAG; /*!< Die Record Tag */ - __I uint32_t DIE_REC_LEN; /*!< Die Record Length */ - __I uint32_t DIE_XPOS; /*!< Die X-Position */ - __I uint32_t DIE_YPOS; /*!< Die Y-Position */ - __I uint32_t WAFER_ID; /*!< Wafer ID */ - __I uint32_t LOT_ID; /*!< Lot ID */ - __I uint32_t RESERVED0; /*!< Reserved */ - __I uint32_t RESERVED1; /*!< Reserved */ - __I uint32_t RESERVED2; /*!< Reserved */ - __I uint32_t TEST_RESULTS; /*!< Test Results */ - __I uint32_t CS_CAL_TAG; /*!< Clock System Calibration Tag */ - __I uint32_t CS_CAL_LEN; /*!< Clock System Calibration Length */ - __I uint32_t DCOIR_FCAL_RSEL04; /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_FCAL_RSEL5; /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED3; /*!< Reserved */ - __I uint32_t RESERVED4; /*!< Reserved */ - __I uint32_t RESERVED5; /*!< Reserved */ - __I uint32_t RESERVED6; /*!< Reserved */ - __I uint32_t DCOIR_CONSTK_RSEL04; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_CONSTK_RSEL5; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t DCOER_FCAL_RSEL04; /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOER_FCAL_RSEL5; /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED7; /*!< Reserved */ - __I uint32_t RESERVED8; /*!< Reserved */ - __I uint32_t RESERVED9; /*!< Reserved */ - __I uint32_t RESERVED10; /*!< Reserved */ - __I uint32_t DCOER_CONSTK_RSEL04; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I uint32_t DCOER_CONSTK_RSEL5; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t ADC14_CAL_TAG; /*!< ADC14 Calibration Tag */ - __I uint32_t ADC14_CAL_LEN; /*!< ADC14 Calibration Length */ - __I uint32_t ADC_GAIN_FACTOR; /*!< ADC Gain Factor */ - __I uint32_t ADC_OFFSET; /*!< ADC Offset */ - __I uint32_t RESERVED11; /*!< Reserved */ - __I uint32_t RESERVED12; /*!< Reserved */ - __I uint32_t RESERVED13; /*!< Reserved */ - __I uint32_t RESERVED14; /*!< Reserved */ - __I uint32_t RESERVED15; /*!< Reserved */ - __I uint32_t RESERVED16; /*!< Reserved */ - __I uint32_t RESERVED17; /*!< Reserved */ - __I uint32_t RESERVED18; /*!< Reserved */ - __I uint32_t RESERVED19; /*!< Reserved */ - __I uint32_t RESERVED20; /*!< Reserved */ - __I uint32_t RESERVED21; /*!< Reserved */ - __I uint32_t RESERVED22; /*!< Reserved */ - __I uint32_t RESERVED23; /*!< Reserved */ - __I uint32_t RESERVED24; /*!< Reserved */ - __I uint32_t RESERVED25; /*!< Reserved */ - __I uint32_t RESERVED26; /*!< Reserved */ - __I uint32_t ADC14_REF1P2V_TS30C; /*!< ADC14 1.2V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P2V_TS85C; /*!< ADC14 1.2V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF1P45V_TS30C; /*!< ADC14 1.45V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P45V_TS85C; /*!< ADC14 1.45V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF2P5V_TS30C; /*!< ADC14 2.5V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF2P5V_TS85C; /*!< ADC14 2.5V Reference Temp. Sensor 85C */ - __I uint32_t REF_CAL_TAG; /*!< REF Calibration Tag */ - __I uint32_t REF_CAL_LEN; /*!< REF Calibration Length */ - __I uint32_t REF_1P2V; /*!< REF 1.2V Reference */ - __I uint32_t REF_1P45V; /*!< REF 1.45V Reference */ - __I uint32_t REF_2P5V; /*!< REF 2.5V Reference */ - __I uint32_t FLASH_INFO_TAG; /*!< Flash Info Tag */ - __I uint32_t FLASH_INFO_LEN; /*!< Flash Info Length */ - __I uint32_t FLASH_MAX_PROG_PULSES; /*!< Flash Maximum Programming Pulses */ - __I uint32_t FLASH_MAX_ERASE_PULSES; /*!< Flash Maximum Erase Pulses */ - __I uint32_t RANDOM_NUM_TAG; /*!< 128-bit Random Number Tag */ - __I uint32_t RANDOM_NUM_LEN; /*!< 128-bit Random Number Length */ - __I uint32_t RANDOM_NUM_1; /*!< 32-bit Random Number 1 */ - __I uint32_t RANDOM_NUM_2; /*!< 32-bit Random Number 2 */ - __I uint32_t RANDOM_NUM_3; /*!< 32-bit Random Number 3 */ - __I uint32_t RANDOM_NUM_4; /*!< 32-bit Random Number 4 */ - __I uint32_t BSL_CFG_TAG; /*!< BSL Configuration Tag */ - __I uint32_t BSL_CFG_LEN; /*!< BSL Configuration Length */ - __I uint32_t BSL_PERIPHIF_SEL; /*!< BSL Peripheral Interface Selection */ - __I uint32_t BSL_PORTIF_CFG_UART; /*!< BSL Port Interface Configuration for UART */ - __I uint32_t BSL_PORTIF_CFG_SPI; /*!< BSL Port Interface Configuration for SPI */ - __I uint32_t BSL_PORTIF_CFG_I2C; /*!< BSL Port Interface Configuration for I2C */ - __I uint32_t TLV_END; /*!< TLV End Word */ -} TLV_Type; - -/*@}*/ /* end of group TLV */ - - -/****************************************************************************** -* WDT_A Registers -******************************************************************************/ -/** @addtogroup WDT_A MSP432P401M (WDT_A) - @{ -*/ -typedef struct { - uint16_t RESERVED0[6]; - __IO uint16_t CTL; /*!< Watchdog Timer Control Register */ -} WDT_A_Type; - -/*@}*/ /* end of group WDT_A */ - - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/*@}*/ /* end of group MSP432P401M_Peripherals */ - -/****************************************************************************** -* Peripheral declaration * -******************************************************************************/ -/** @addtogroup MSP432P401M_PeripheralDecl MSP432P401M Peripheral Declaration - @{ -*/ - -#define ADC14 ((ADC14_Type *) ADC14_BASE) -#define AES256 ((AES256_Type *) AES256_BASE) -#define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE) -#define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE) -#define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE) -#define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE) -#define CRC32 ((CRC32_Type *) CRC32_BASE) -#define CS ((CS_Type *) CS_BASE) -#define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120)) -#define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define DMA_Channel ((DMA_Channel_Type *) DMA_BASE) -#define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000)) -#define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE) -#define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE) -#define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE) -#define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE) -#define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE) -#define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE) -#define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE) -#define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE) -#define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE) -#define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE) -#define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE) -#define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE) -#define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE) -#define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE) -#define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE) -#define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE) -#define FLCTL ((FLCTL_Type *) FLCTL_BASE) -#define FL_BOOTOVER_MAILBOX ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE) -#define PCM ((PCM_Type *) PCM_BASE) -#define PMAP ((PMAP_COMMON_Type*) PMAP_BASE) -#define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008)) -#define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010)) -#define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018)) -#define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020)) -#define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028)) -#define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030)) -#define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038)) -#define PSS ((PSS_Type *) PSS_BASE) -#define REF_A ((REF_A_Type *) REF_A_BASE) -#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) -#define RTC_C ((RTC_C_Type *) RTC_C_BASE) -#define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE) -#define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE) -#define SYSCTL_Boot ((SYSCTL_Boot_Type *) (SYSCTL_BASE + 0x1000)) -#define TIMER32_1 ((Timer32_Type *) TIMER32_BASE) -#define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020)) -#define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE) -#define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE) -#define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE) -#define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE) -#define TLV ((TLV_Type *) TLV_BASE) -#define WDT_A ((WDT_A_Type *) WDT_A_BASE) - - -/*@}*/ /* end of group MSP432P401M_PeripheralDecl */ - -/*@}*/ /* end of group MSP432P401M_Definitions */ - -#endif /* __CMSIS_CONFIG__ */ - -/****************************************************************************** -* Peripheral register control bits * -******************************************************************************/ - -/****************************************************************************** -* ADC14 Bits -******************************************************************************/ -/* ADC14_CTL0[SC] Bits */ -#define ADC14_CTL0_SC_OFS ( 0) /*!< ADC14SC Bit Offset */ -#define ADC14_CTL0_SC ((uint32_t)0x00000001) /*!< ADC14 start conversion */ -/* ADC14_CTL0[ENC] Bits */ -#define ADC14_CTL0_ENC_OFS ( 1) /*!< ADC14ENC Bit Offset */ -#define ADC14_CTL0_ENC ((uint32_t)0x00000002) /*!< ADC14 enable conversion */ -/* ADC14_CTL0[ON] Bits */ -#define ADC14_CTL0_ON_OFS ( 4) /*!< ADC14ON Bit Offset */ -#define ADC14_CTL0_ON ((uint32_t)0x00000010) /*!< ADC14 on */ -/* ADC14_CTL0[MSC] Bits */ -#define ADC14_CTL0_MSC_OFS ( 7) /*!< ADC14MSC Bit Offset */ -#define ADC14_CTL0_MSC ((uint32_t)0x00000080) /*!< ADC14 multiple sample and conversion */ -/* ADC14_CTL0[SHT0] Bits */ -#define ADC14_CTL0_SHT0_OFS ( 8) /*!< ADC14SHT0 Bit Offset */ -#define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /*!< ADC14SHT0 Bit Mask */ -#define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /*!< SHT0 Bit 0 */ -#define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /*!< SHT0 Bit 1 */ -#define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /*!< SHT0 Bit 2 */ -#define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /*!< SHT0 Bit 3 */ -#define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /*!< 192 */ -#define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /*!< 192 */ -/* ADC14_CTL0[SHT1] Bits */ -#define ADC14_CTL0_SHT1_OFS (12) /*!< ADC14SHT1 Bit Offset */ -#define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /*!< ADC14SHT1 Bit Mask */ -#define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /*!< SHT1 Bit 0 */ -#define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /*!< SHT1 Bit 1 */ -#define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /*!< SHT1 Bit 2 */ -#define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /*!< SHT1 Bit 3 */ -#define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /*!< 192 */ -#define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /*!< 192 */ -/* ADC14_CTL0[BUSY] Bits */ -#define ADC14_CTL0_BUSY_OFS (16) /*!< ADC14BUSY Bit Offset */ -#define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /*!< ADC14 busy */ -/* ADC14_CTL0[CONSEQ] Bits */ -#define ADC14_CTL0_CONSEQ_OFS (17) /*!< ADC14CONSEQ Bit Offset */ -#define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /*!< ADC14CONSEQ Bit Mask */ -#define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /*!< CONSEQ Bit 0 */ -#define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /*!< CONSEQ Bit 1 */ -#define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /*!< Single-channel, single-conversion */ -#define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /*!< Sequence-of-channels */ -#define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /*!< Repeat-single-channel */ -#define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /*!< Repeat-sequence-of-channels */ -/* ADC14_CTL0[SSEL] Bits */ -#define ADC14_CTL0_SSEL_OFS (19) /*!< ADC14SSEL Bit Offset */ -#define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /*!< ADC14SSEL Bit Mask */ -#define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /*!< SSEL Bit 0 */ -#define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /*!< SSEL Bit 1 */ -#define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /*!< SSEL Bit 2 */ -#define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /*!< HSMCLK */ -#define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /*!< HSMCLK */ -/* ADC14_CTL0[DIV] Bits */ -#define ADC14_CTL0_DIV_OFS (22) /*!< ADC14DIV Bit Offset */ -#define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /*!< ADC14DIV Bit Mask */ -#define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /*!< DIV Bit 0 */ -#define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /*!< DIV Bit 1 */ -#define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /*!< DIV Bit 2 */ -#define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /*!< /8 */ -#define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /*!< /8 */ -/* ADC14_CTL0[ISSH] Bits */ -#define ADC14_CTL0_ISSH_OFS (25) /*!< ADC14ISSH Bit Offset */ -#define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /*!< ADC14 invert signal sample-and-hold */ -/* ADC14_CTL0[SHP] Bits */ -#define ADC14_CTL0_SHP_OFS (26) /*!< ADC14SHP Bit Offset */ -#define ADC14_CTL0_SHP ((uint32_t)0x04000000) /*!< ADC14 sample-and-hold pulse-mode select */ -/* ADC14_CTL0[SHS] Bits */ -#define ADC14_CTL0_SHS_OFS (27) /*!< ADC14SHS Bit Offset */ -#define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /*!< ADC14SHS Bit Mask */ -#define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /*!< SHS Bit 0 */ -#define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /*!< SHS Bit 1 */ -#define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /*!< SHS Bit 2 */ -#define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /*!< ADC14SC bit */ -#define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /*!< See device-specific data sheet for source */ -/* ADC14_CTL0[PDIV] Bits */ -#define ADC14_CTL0_PDIV_OFS (30) /*!< ADC14PDIV Bit Offset */ -#define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /*!< ADC14PDIV Bit Mask */ -#define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /*!< PDIV Bit 0 */ -#define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /*!< PDIV Bit 1 */ -#define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -#define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -/* ADC14_CTL1[PWRMD] Bits */ -#define ADC14_CTL1_PWRMD_OFS ( 0) /*!< ADC14PWRMD Bit Offset */ -#define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /*!< ADC14PWRMD Bit Mask */ -#define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /*!< PWRMD Bit 0 */ -#define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /*!< PWRMD Bit 1 */ -#define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /*!< Regular power mode for use with any resolution setting. Sample rate can be */ - /* up to 1 Msps. */ -#define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample */ - /* rate must not exceed 200 ksps. */ -/* ADC14_CTL1[REFBURST] Bits */ -#define ADC14_CTL1_REFBURST_OFS ( 2) /*!< ADC14REFBURST Bit Offset */ -#define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /*!< ADC14 reference buffer burst */ -/* ADC14_CTL1[DF] Bits */ -#define ADC14_CTL1_DF_OFS ( 3) /*!< ADC14DF Bit Offset */ -#define ADC14_CTL1_DF ((uint32_t)0x00000008) /*!< ADC14 data read-back format */ -/* ADC14_CTL1[RES] Bits */ -#define ADC14_CTL1_RES_OFS ( 4) /*!< ADC14RES Bit Offset */ -#define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /*!< ADC14RES Bit Mask */ -#define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /*!< RES Bit 0 */ -#define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /*!< RES Bit 1 */ -#define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -#define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -/* ADC14_CTL1[CSTARTADD] Bits */ -#define ADC14_CTL1_CSTARTADD_OFS (16) /*!< ADC14CSTARTADD Bit Offset */ -#define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /*!< ADC14CSTARTADD Bit Mask */ -/* ADC14_CTL1[BATMAP] Bits */ -#define ADC14_CTL1_BATMAP_OFS (22) /*!< ADC14BATMAP Bit Offset */ -#define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /*!< Controls 1/2 AVCC ADC input channel selection */ -/* ADC14_CTL1[TCMAP] Bits */ -#define ADC14_CTL1_TCMAP_OFS (23) /*!< ADC14TCMAP Bit Offset */ -#define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /*!< Controls temperature sensor ADC input channel selection */ -/* ADC14_CTL1[CH0MAP] Bits */ -#define ADC14_CTL1_CH0MAP_OFS (24) /*!< ADC14CH0MAP Bit Offset */ -#define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */ -/* ADC14_CTL1[CH1MAP] Bits */ -#define ADC14_CTL1_CH1MAP_OFS (25) /*!< ADC14CH1MAP Bit Offset */ -#define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */ -/* ADC14_CTL1[CH2MAP] Bits */ -#define ADC14_CTL1_CH2MAP_OFS (26) /*!< ADC14CH2MAP Bit Offset */ -#define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */ -/* ADC14_CTL1[CH3MAP] Bits */ -#define ADC14_CTL1_CH3MAP_OFS (27) /*!< ADC14CH3MAP Bit Offset */ -#define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */ -/* ADC14_LO0[LO0] Bits */ -#define ADC14_LO0_LO0_OFS ( 0) /*!< ADC14LO0 Bit Offset */ -#define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO0 Bit Mask */ -/* ADC14_HI0[HI0] Bits */ -#define ADC14_HI0_HI0_OFS ( 0) /*!< ADC14HI0 Bit Offset */ -#define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI0 Bit Mask */ -/* ADC14_LO1[LO1] Bits */ -#define ADC14_LO1_LO1_OFS ( 0) /*!< ADC14LO1 Bit Offset */ -#define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO1 Bit Mask */ -/* ADC14_HI1[HI1] Bits */ -#define ADC14_HI1_HI1_OFS ( 0) /*!< ADC14HI1 Bit Offset */ -#define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI1 Bit Mask */ -/* ADC14_MCTLN[INCH] Bits */ -#define ADC14_MCTLN_INCH_OFS ( 0) /*!< ADC14INCH Bit Offset */ -#define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /*!< ADC14INCH Bit Mask */ -#define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /*!< INCH Bit 0 */ -#define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /*!< INCH Bit 1 */ -#define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /*!< INCH Bit 2 */ -#define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /*!< INCH Bit 3 */ -#define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /*!< INCH Bit 4 */ -#define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -#define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -/* ADC14_MCTLN[EOS] Bits */ -#define ADC14_MCTLN_EOS_OFS ( 7) /*!< ADC14EOS Bit Offset */ -#define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /*!< End of sequence */ -/* ADC14_MCTLN[VRSEL] Bits */ -#define ADC14_MCTLN_VRSEL_OFS ( 8) /*!< ADC14VRSEL Bit Offset */ -#define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /*!< ADC14VRSEL Bit Mask */ -#define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /*!< VRSEL Bit 0 */ -#define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /*!< VRSEL Bit 1 */ -#define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /*!< VRSEL Bit 2 */ -#define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /*!< VRSEL Bit 3 */ -#define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /*!< V(R+) = AVCC, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /*!< V(R+) = VREF buffered, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /*!< V(R+) = VeREF+, V(R-) = VeREF- */ -#define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */ -/* ADC14_MCTLN[DIF] Bits */ -#define ADC14_MCTLN_DIF_OFS (13) /*!< ADC14DIF Bit Offset */ -#define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /*!< Differential mode */ -/* ADC14_MCTLN[WINC] Bits */ -#define ADC14_MCTLN_WINC_OFS (14) /*!< ADC14WINC Bit Offset */ -#define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /*!< Comparator window enable */ -/* ADC14_MCTLN[WINCTH] Bits */ -#define ADC14_MCTLN_WINCTH_OFS (15) /*!< ADC14WINCTH Bit Offset */ -#define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /*!< Window comparator threshold register selection */ -/* ADC14_MEMN[CONVRES] Bits */ -#define ADC14_MEMN_CONVRES_OFS ( 0) /*!< Conversion_Results Bit Offset */ -#define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /*!< Conversion_Results Bit Mask */ -/* ADC14_IER0[IE0] Bits */ -#define ADC14_IER0_IE0_OFS ( 0) /*!< ADC14IE0 Bit Offset */ -#define ADC14_IER0_IE0 ((uint32_t)0x00000001) /*!< Interrupt enable */ -/* ADC14_IER0[IE1] Bits */ -#define ADC14_IER0_IE1_OFS ( 1) /*!< ADC14IE1 Bit Offset */ -#define ADC14_IER0_IE1 ((uint32_t)0x00000002) /*!< Interrupt enable */ -/* ADC14_IER0[IE2] Bits */ -#define ADC14_IER0_IE2_OFS ( 2) /*!< ADC14IE2 Bit Offset */ -#define ADC14_IER0_IE2 ((uint32_t)0x00000004) /*!< Interrupt enable */ -/* ADC14_IER0[IE3] Bits */ -#define ADC14_IER0_IE3_OFS ( 3) /*!< ADC14IE3 Bit Offset */ -#define ADC14_IER0_IE3 ((uint32_t)0x00000008) /*!< Interrupt enable */ -/* ADC14_IER0[IE4] Bits */ -#define ADC14_IER0_IE4_OFS ( 4) /*!< ADC14IE4 Bit Offset */ -#define ADC14_IER0_IE4 ((uint32_t)0x00000010) /*!< Interrupt enable */ -/* ADC14_IER0[IE5] Bits */ -#define ADC14_IER0_IE5_OFS ( 5) /*!< ADC14IE5 Bit Offset */ -#define ADC14_IER0_IE5 ((uint32_t)0x00000020) /*!< Interrupt enable */ -/* ADC14_IER0[IE6] Bits */ -#define ADC14_IER0_IE6_OFS ( 6) /*!< ADC14IE6 Bit Offset */ -#define ADC14_IER0_IE6 ((uint32_t)0x00000040) /*!< Interrupt enable */ -/* ADC14_IER0[IE7] Bits */ -#define ADC14_IER0_IE7_OFS ( 7) /*!< ADC14IE7 Bit Offset */ -#define ADC14_IER0_IE7 ((uint32_t)0x00000080) /*!< Interrupt enable */ -/* ADC14_IER0[IE8] Bits */ -#define ADC14_IER0_IE8_OFS ( 8) /*!< ADC14IE8 Bit Offset */ -#define ADC14_IER0_IE8 ((uint32_t)0x00000100) /*!< Interrupt enable */ -/* ADC14_IER0[IE9] Bits */ -#define ADC14_IER0_IE9_OFS ( 9) /*!< ADC14IE9 Bit Offset */ -#define ADC14_IER0_IE9 ((uint32_t)0x00000200) /*!< Interrupt enable */ -/* ADC14_IER0[IE10] Bits */ -#define ADC14_IER0_IE10_OFS (10) /*!< ADC14IE10 Bit Offset */ -#define ADC14_IER0_IE10 ((uint32_t)0x00000400) /*!< Interrupt enable */ -/* ADC14_IER0[IE11] Bits */ -#define ADC14_IER0_IE11_OFS (11) /*!< ADC14IE11 Bit Offset */ -#define ADC14_IER0_IE11 ((uint32_t)0x00000800) /*!< Interrupt enable */ -/* ADC14_IER0[IE12] Bits */ -#define ADC14_IER0_IE12_OFS (12) /*!< ADC14IE12 Bit Offset */ -#define ADC14_IER0_IE12 ((uint32_t)0x00001000) /*!< Interrupt enable */ -/* ADC14_IER0[IE13] Bits */ -#define ADC14_IER0_IE13_OFS (13) /*!< ADC14IE13 Bit Offset */ -#define ADC14_IER0_IE13 ((uint32_t)0x00002000) /*!< Interrupt enable */ -/* ADC14_IER0[IE14] Bits */ -#define ADC14_IER0_IE14_OFS (14) /*!< ADC14IE14 Bit Offset */ -#define ADC14_IER0_IE14 ((uint32_t)0x00004000) /*!< Interrupt enable */ -/* ADC14_IER0[IE15] Bits */ -#define ADC14_IER0_IE15_OFS (15) /*!< ADC14IE15 Bit Offset */ -#define ADC14_IER0_IE15 ((uint32_t)0x00008000) /*!< Interrupt enable */ -/* ADC14_IER0[IE16] Bits */ -#define ADC14_IER0_IE16_OFS (16) /*!< ADC14IE16 Bit Offset */ -#define ADC14_IER0_IE16 ((uint32_t)0x00010000) /*!< Interrupt enable */ -/* ADC14_IER0[IE17] Bits */ -#define ADC14_IER0_IE17_OFS (17) /*!< ADC14IE17 Bit Offset */ -#define ADC14_IER0_IE17 ((uint32_t)0x00020000) /*!< Interrupt enable */ -/* ADC14_IER0[IE19] Bits */ -#define ADC14_IER0_IE19_OFS (19) /*!< ADC14IE19 Bit Offset */ -#define ADC14_IER0_IE19 ((uint32_t)0x00080000) /*!< Interrupt enable */ -/* ADC14_IER0[IE18] Bits */ -#define ADC14_IER0_IE18_OFS (18) /*!< ADC14IE18 Bit Offset */ -#define ADC14_IER0_IE18 ((uint32_t)0x00040000) /*!< Interrupt enable */ -/* ADC14_IER0[IE20] Bits */ -#define ADC14_IER0_IE20_OFS (20) /*!< ADC14IE20 Bit Offset */ -#define ADC14_IER0_IE20 ((uint32_t)0x00100000) /*!< Interrupt enable */ -/* ADC14_IER0[IE21] Bits */ -#define ADC14_IER0_IE21_OFS (21) /*!< ADC14IE21 Bit Offset */ -#define ADC14_IER0_IE21 ((uint32_t)0x00200000) /*!< Interrupt enable */ -/* ADC14_IER0[IE22] Bits */ -#define ADC14_IER0_IE22_OFS (22) /*!< ADC14IE22 Bit Offset */ -#define ADC14_IER0_IE22 ((uint32_t)0x00400000) /*!< Interrupt enable */ -/* ADC14_IER0[IE23] Bits */ -#define ADC14_IER0_IE23_OFS (23) /*!< ADC14IE23 Bit Offset */ -#define ADC14_IER0_IE23 ((uint32_t)0x00800000) /*!< Interrupt enable */ -/* ADC14_IER0[IE24] Bits */ -#define ADC14_IER0_IE24_OFS (24) /*!< ADC14IE24 Bit Offset */ -#define ADC14_IER0_IE24 ((uint32_t)0x01000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE25] Bits */ -#define ADC14_IER0_IE25_OFS (25) /*!< ADC14IE25 Bit Offset */ -#define ADC14_IER0_IE25 ((uint32_t)0x02000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE26] Bits */ -#define ADC14_IER0_IE26_OFS (26) /*!< ADC14IE26 Bit Offset */ -#define ADC14_IER0_IE26 ((uint32_t)0x04000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE27] Bits */ -#define ADC14_IER0_IE27_OFS (27) /*!< ADC14IE27 Bit Offset */ -#define ADC14_IER0_IE27 ((uint32_t)0x08000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE28] Bits */ -#define ADC14_IER0_IE28_OFS (28) /*!< ADC14IE28 Bit Offset */ -#define ADC14_IER0_IE28 ((uint32_t)0x10000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE29] Bits */ -#define ADC14_IER0_IE29_OFS (29) /*!< ADC14IE29 Bit Offset */ -#define ADC14_IER0_IE29 ((uint32_t)0x20000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE30] Bits */ -#define ADC14_IER0_IE30_OFS (30) /*!< ADC14IE30 Bit Offset */ -#define ADC14_IER0_IE30 ((uint32_t)0x40000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE31] Bits */ -#define ADC14_IER0_IE31_OFS (31) /*!< ADC14IE31 Bit Offset */ -#define ADC14_IER0_IE31 ((uint32_t)0x80000000) /*!< Interrupt enable */ -/* ADC14_IER1[INIE] Bits */ -#define ADC14_IER1_INIE_OFS ( 1) /*!< ADC14INIE Bit Offset */ -#define ADC14_IER1_INIE ((uint32_t)0x00000002) /*!< Interrupt enable for ADC14MEMx within comparator window */ -/* ADC14_IER1[LOIE] Bits */ -#define ADC14_IER1_LOIE_OFS ( 2) /*!< ADC14LOIE Bit Offset */ -#define ADC14_IER1_LOIE ((uint32_t)0x00000004) /*!< Interrupt enable for ADC14MEMx below comparator window */ -/* ADC14_IER1[HIIE] Bits */ -#define ADC14_IER1_HIIE_OFS ( 3) /*!< ADC14HIIE Bit Offset */ -#define ADC14_IER1_HIIE ((uint32_t)0x00000008) /*!< Interrupt enable for ADC14MEMx above comparator window */ -/* ADC14_IER1[OVIE] Bits */ -#define ADC14_IER1_OVIE_OFS ( 4) /*!< ADC14OVIE Bit Offset */ -#define ADC14_IER1_OVIE ((uint32_t)0x00000010) /*!< ADC14MEMx overflow-interrupt enable */ -/* ADC14_IER1[TOVIE] Bits */ -#define ADC14_IER1_TOVIE_OFS ( 5) /*!< ADC14TOVIE Bit Offset */ -#define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /*!< ADC14 conversion-time-overflow interrupt enable */ -/* ADC14_IER1[RDYIE] Bits */ -#define ADC14_IER1_RDYIE_OFS ( 6) /*!< ADC14RDYIE Bit Offset */ -#define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt enable */ -/* ADC14_IFGR0[IFG0] Bits */ -#define ADC14_IFGR0_IFG0_OFS ( 0) /*!< ADC14IFG0 Bit Offset */ -#define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /*!< ADC14MEM0 interrupt flag */ -/* ADC14_IFGR0[IFG1] Bits */ -#define ADC14_IFGR0_IFG1_OFS ( 1) /*!< ADC14IFG1 Bit Offset */ -#define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /*!< ADC14MEM1 interrupt flag */ -/* ADC14_IFGR0[IFG2] Bits */ -#define ADC14_IFGR0_IFG2_OFS ( 2) /*!< ADC14IFG2 Bit Offset */ -#define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /*!< ADC14MEM2 interrupt flag */ -/* ADC14_IFGR0[IFG3] Bits */ -#define ADC14_IFGR0_IFG3_OFS ( 3) /*!< ADC14IFG3 Bit Offset */ -#define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /*!< ADC14MEM3 interrupt flag */ -/* ADC14_IFGR0[IFG4] Bits */ -#define ADC14_IFGR0_IFG4_OFS ( 4) /*!< ADC14IFG4 Bit Offset */ -#define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /*!< ADC14MEM4 interrupt flag */ -/* ADC14_IFGR0[IFG5] Bits */ -#define ADC14_IFGR0_IFG5_OFS ( 5) /*!< ADC14IFG5 Bit Offset */ -#define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /*!< ADC14MEM5 interrupt flag */ -/* ADC14_IFGR0[IFG6] Bits */ -#define ADC14_IFGR0_IFG6_OFS ( 6) /*!< ADC14IFG6 Bit Offset */ -#define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /*!< ADC14MEM6 interrupt flag */ -/* ADC14_IFGR0[IFG7] Bits */ -#define ADC14_IFGR0_IFG7_OFS ( 7) /*!< ADC14IFG7 Bit Offset */ -#define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /*!< ADC14MEM7 interrupt flag */ -/* ADC14_IFGR0[IFG8] Bits */ -#define ADC14_IFGR0_IFG8_OFS ( 8) /*!< ADC14IFG8 Bit Offset */ -#define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /*!< ADC14MEM8 interrupt flag */ -/* ADC14_IFGR0[IFG9] Bits */ -#define ADC14_IFGR0_IFG9_OFS ( 9) /*!< ADC14IFG9 Bit Offset */ -#define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /*!< ADC14MEM9 interrupt flag */ -/* ADC14_IFGR0[IFG10] Bits */ -#define ADC14_IFGR0_IFG10_OFS (10) /*!< ADC14IFG10 Bit Offset */ -#define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /*!< ADC14MEM10 interrupt flag */ -/* ADC14_IFGR0[IFG11] Bits */ -#define ADC14_IFGR0_IFG11_OFS (11) /*!< ADC14IFG11 Bit Offset */ -#define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /*!< ADC14MEM11 interrupt flag */ -/* ADC14_IFGR0[IFG12] Bits */ -#define ADC14_IFGR0_IFG12_OFS (12) /*!< ADC14IFG12 Bit Offset */ -#define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /*!< ADC14MEM12 interrupt flag */ -/* ADC14_IFGR0[IFG13] Bits */ -#define ADC14_IFGR0_IFG13_OFS (13) /*!< ADC14IFG13 Bit Offset */ -#define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /*!< ADC14MEM13 interrupt flag */ -/* ADC14_IFGR0[IFG14] Bits */ -#define ADC14_IFGR0_IFG14_OFS (14) /*!< ADC14IFG14 Bit Offset */ -#define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /*!< ADC14MEM14 interrupt flag */ -/* ADC14_IFGR0[IFG15] Bits */ -#define ADC14_IFGR0_IFG15_OFS (15) /*!< ADC14IFG15 Bit Offset */ -#define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /*!< ADC14MEM15 interrupt flag */ -/* ADC14_IFGR0[IFG16] Bits */ -#define ADC14_IFGR0_IFG16_OFS (16) /*!< ADC14IFG16 Bit Offset */ -#define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /*!< ADC14MEM16 interrupt flag */ -/* ADC14_IFGR0[IFG17] Bits */ -#define ADC14_IFGR0_IFG17_OFS (17) /*!< ADC14IFG17 Bit Offset */ -#define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /*!< ADC14MEM17 interrupt flag */ -/* ADC14_IFGR0[IFG18] Bits */ -#define ADC14_IFGR0_IFG18_OFS (18) /*!< ADC14IFG18 Bit Offset */ -#define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /*!< ADC14MEM18 interrupt flag */ -/* ADC14_IFGR0[IFG19] Bits */ -#define ADC14_IFGR0_IFG19_OFS (19) /*!< ADC14IFG19 Bit Offset */ -#define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /*!< ADC14MEM19 interrupt flag */ -/* ADC14_IFGR0[IFG20] Bits */ -#define ADC14_IFGR0_IFG20_OFS (20) /*!< ADC14IFG20 Bit Offset */ -#define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /*!< ADC14MEM20 interrupt flag */ -/* ADC14_IFGR0[IFG21] Bits */ -#define ADC14_IFGR0_IFG21_OFS (21) /*!< ADC14IFG21 Bit Offset */ -#define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /*!< ADC14MEM21 interrupt flag */ -/* ADC14_IFGR0[IFG22] Bits */ -#define ADC14_IFGR0_IFG22_OFS (22) /*!< ADC14IFG22 Bit Offset */ -#define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /*!< ADC14MEM22 interrupt flag */ -/* ADC14_IFGR0[IFG23] Bits */ -#define ADC14_IFGR0_IFG23_OFS (23) /*!< ADC14IFG23 Bit Offset */ -#define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /*!< ADC14MEM23 interrupt flag */ -/* ADC14_IFGR0[IFG24] Bits */ -#define ADC14_IFGR0_IFG24_OFS (24) /*!< ADC14IFG24 Bit Offset */ -#define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /*!< ADC14MEM24 interrupt flag */ -/* ADC14_IFGR0[IFG25] Bits */ -#define ADC14_IFGR0_IFG25_OFS (25) /*!< ADC14IFG25 Bit Offset */ -#define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /*!< ADC14MEM25 interrupt flag */ -/* ADC14_IFGR0[IFG26] Bits */ -#define ADC14_IFGR0_IFG26_OFS (26) /*!< ADC14IFG26 Bit Offset */ -#define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /*!< ADC14MEM26 interrupt flag */ -/* ADC14_IFGR0[IFG27] Bits */ -#define ADC14_IFGR0_IFG27_OFS (27) /*!< ADC14IFG27 Bit Offset */ -#define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /*!< ADC14MEM27 interrupt flag */ -/* ADC14_IFGR0[IFG28] Bits */ -#define ADC14_IFGR0_IFG28_OFS (28) /*!< ADC14IFG28 Bit Offset */ -#define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /*!< ADC14MEM28 interrupt flag */ -/* ADC14_IFGR0[IFG29] Bits */ -#define ADC14_IFGR0_IFG29_OFS (29) /*!< ADC14IFG29 Bit Offset */ -#define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /*!< ADC14MEM29 interrupt flag */ -/* ADC14_IFGR0[IFG30] Bits */ -#define ADC14_IFGR0_IFG30_OFS (30) /*!< ADC14IFG30 Bit Offset */ -#define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /*!< ADC14MEM30 interrupt flag */ -/* ADC14_IFGR0[IFG31] Bits */ -#define ADC14_IFGR0_IFG31_OFS (31) /*!< ADC14IFG31 Bit Offset */ -#define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /*!< ADC14MEM31 interrupt flag */ -/* ADC14_IFGR1[INIFG] Bits */ -#define ADC14_IFGR1_INIFG_OFS ( 1) /*!< ADC14INIFG Bit Offset */ -#define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /*!< Interrupt flag for ADC14MEMx within comparator window */ -/* ADC14_IFGR1[LOIFG] Bits */ -#define ADC14_IFGR1_LOIFG_OFS ( 2) /*!< ADC14LOIFG Bit Offset */ -#define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /*!< Interrupt flag for ADC14MEMx below comparator window */ -/* ADC14_IFGR1[HIIFG] Bits */ -#define ADC14_IFGR1_HIIFG_OFS ( 3) /*!< ADC14HIIFG Bit Offset */ -#define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /*!< Interrupt flag for ADC14MEMx above comparator window */ -/* ADC14_IFGR1[OVIFG] Bits */ -#define ADC14_IFGR1_OVIFG_OFS ( 4) /*!< ADC14OVIFG Bit Offset */ -#define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /*!< ADC14MEMx overflow interrupt flag */ -/* ADC14_IFGR1[TOVIFG] Bits */ -#define ADC14_IFGR1_TOVIFG_OFS ( 5) /*!< ADC14TOVIFG Bit Offset */ -#define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /*!< ADC14 conversion time overflow interrupt flag */ -/* ADC14_IFGR1[RDYIFG] Bits */ -#define ADC14_IFGR1_RDYIFG_OFS ( 6) /*!< ADC14RDYIFG Bit Offset */ -#define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt flag */ -/* ADC14_CLRIFGR0[CLRIFG0] Bits */ -#define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /*!< CLRADC14IFG0 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /*!< clear ADC14IFG0 */ -/* ADC14_CLRIFGR0[CLRIFG1] Bits */ -#define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /*!< CLRADC14IFG1 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /*!< clear ADC14IFG1 */ -/* ADC14_CLRIFGR0[CLRIFG2] Bits */ -#define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /*!< CLRADC14IFG2 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /*!< clear ADC14IFG2 */ -/* ADC14_CLRIFGR0[CLRIFG3] Bits */ -#define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /*!< CLRADC14IFG3 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /*!< clear ADC14IFG3 */ -/* ADC14_CLRIFGR0[CLRIFG4] Bits */ -#define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /*!< CLRADC14IFG4 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /*!< clear ADC14IFG4 */ -/* ADC14_CLRIFGR0[CLRIFG5] Bits */ -#define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /*!< CLRADC14IFG5 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /*!< clear ADC14IFG5 */ -/* ADC14_CLRIFGR0[CLRIFG6] Bits */ -#define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /*!< CLRADC14IFG6 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /*!< clear ADC14IFG6 */ -/* ADC14_CLRIFGR0[CLRIFG7] Bits */ -#define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /*!< CLRADC14IFG7 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /*!< clear ADC14IFG7 */ -/* ADC14_CLRIFGR0[CLRIFG8] Bits */ -#define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /*!< CLRADC14IFG8 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /*!< clear ADC14IFG8 */ -/* ADC14_CLRIFGR0[CLRIFG9] Bits */ -#define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /*!< CLRADC14IFG9 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /*!< clear ADC14IFG9 */ -/* ADC14_CLRIFGR0[CLRIFG10] Bits */ -#define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /*!< CLRADC14IFG10 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /*!< clear ADC14IFG10 */ -/* ADC14_CLRIFGR0[CLRIFG11] Bits */ -#define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /*!< CLRADC14IFG11 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /*!< clear ADC14IFG11 */ -/* ADC14_CLRIFGR0[CLRIFG12] Bits */ -#define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /*!< CLRADC14IFG12 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /*!< clear ADC14IFG12 */ -/* ADC14_CLRIFGR0[CLRIFG13] Bits */ -#define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /*!< CLRADC14IFG13 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /*!< clear ADC14IFG13 */ -/* ADC14_CLRIFGR0[CLRIFG14] Bits */ -#define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /*!< CLRADC14IFG14 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /*!< clear ADC14IFG14 */ -/* ADC14_CLRIFGR0[CLRIFG15] Bits */ -#define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /*!< CLRADC14IFG15 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /*!< clear ADC14IFG15 */ -/* ADC14_CLRIFGR0[CLRIFG16] Bits */ -#define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /*!< CLRADC14IFG16 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /*!< clear ADC14IFG16 */ -/* ADC14_CLRIFGR0[CLRIFG17] Bits */ -#define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /*!< CLRADC14IFG17 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /*!< clear ADC14IFG17 */ -/* ADC14_CLRIFGR0[CLRIFG18] Bits */ -#define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /*!< CLRADC14IFG18 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /*!< clear ADC14IFG18 */ -/* ADC14_CLRIFGR0[CLRIFG19] Bits */ -#define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /*!< CLRADC14IFG19 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /*!< clear ADC14IFG19 */ -/* ADC14_CLRIFGR0[CLRIFG20] Bits */ -#define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /*!< CLRADC14IFG20 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /*!< clear ADC14IFG20 */ -/* ADC14_CLRIFGR0[CLRIFG21] Bits */ -#define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /*!< CLRADC14IFG21 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /*!< clear ADC14IFG21 */ -/* ADC14_CLRIFGR0[CLRIFG22] Bits */ -#define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /*!< CLRADC14IFG22 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /*!< clear ADC14IFG22 */ -/* ADC14_CLRIFGR0[CLRIFG23] Bits */ -#define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /*!< CLRADC14IFG23 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /*!< clear ADC14IFG23 */ -/* ADC14_CLRIFGR0[CLRIFG24] Bits */ -#define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /*!< CLRADC14IFG24 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /*!< clear ADC14IFG24 */ -/* ADC14_CLRIFGR0[CLRIFG25] Bits */ -#define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /*!< CLRADC14IFG25 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /*!< clear ADC14IFG25 */ -/* ADC14_CLRIFGR0[CLRIFG26] Bits */ -#define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /*!< CLRADC14IFG26 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /*!< clear ADC14IFG26 */ -/* ADC14_CLRIFGR0[CLRIFG27] Bits */ -#define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /*!< CLRADC14IFG27 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /*!< clear ADC14IFG27 */ -/* ADC14_CLRIFGR0[CLRIFG28] Bits */ -#define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /*!< CLRADC14IFG28 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /*!< clear ADC14IFG28 */ -/* ADC14_CLRIFGR0[CLRIFG29] Bits */ -#define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /*!< CLRADC14IFG29 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /*!< clear ADC14IFG29 */ -/* ADC14_CLRIFGR0[CLRIFG30] Bits */ -#define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /*!< CLRADC14IFG30 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /*!< clear ADC14IFG30 */ -/* ADC14_CLRIFGR0[CLRIFG31] Bits */ -#define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /*!< CLRADC14IFG31 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /*!< clear ADC14IFG31 */ -/* ADC14_CLRIFGR1[CLRINIFG] Bits */ -#define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /*!< CLRADC14INIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /*!< clear ADC14INIFG */ -/* ADC14_CLRIFGR1[CLRLOIFG] Bits */ -#define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /*!< CLRADC14LOIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /*!< clear ADC14LOIFG */ -/* ADC14_CLRIFGR1[CLRHIIFG] Bits */ -#define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /*!< CLRADC14HIIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /*!< clear ADC14HIIFG */ -/* ADC14_CLRIFGR1[CLROVIFG] Bits */ -#define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /*!< CLRADC14OVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /*!< clear ADC14OVIFG */ -/* ADC14_CLRIFGR1[CLRTOVIFG] Bits */ -#define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /*!< CLRADC14TOVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /*!< clear ADC14TOVIFG */ -/* ADC14_CLRIFGR1[CLRRDYIFG] Bits */ -#define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /*!< CLRADC14RDYIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /*!< clear ADC14RDYIFG */ - -/****************************************************************************** -* AES256 Bits -******************************************************************************/ -/* AES256_CTL0[OP] Bits */ -#define AES256_CTL0_OP_OFS ( 0) /*!< AESOPx Bit Offset */ -#define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /*!< AESOPx Bit Mask */ -#define AES256_CTL0_OP0 ((uint16_t)0x0001) /*!< OP Bit 0 */ -#define AES256_CTL0_OP1 ((uint16_t)0x0002) /*!< OP Bit 1 */ -#define AES256_CTL0_OP_0 ((uint16_t)0x0000) /*!< Encryption */ -#define AES256_CTL0_OP_1 ((uint16_t)0x0001) /*!< Decryption. The provided key is the same key used for encryption */ -#define AES256_CTL0_OP_2 ((uint16_t)0x0002) /*!< Generate first round key required for decryption */ -#define AES256_CTL0_OP_3 ((uint16_t)0x0003) /*!< Decryption. The provided key is the first round key required for decryption */ -/* AES256_CTL0[KL] Bits */ -#define AES256_CTL0_KL_OFS ( 2) /*!< AESKLx Bit Offset */ -#define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /*!< AESKLx Bit Mask */ -#define AES256_CTL0_KL0 ((uint16_t)0x0004) /*!< KL Bit 0 */ -#define AES256_CTL0_KL1 ((uint16_t)0x0008) /*!< KL Bit 1 */ -#define AES256_CTL0_KL_0 ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL_1 ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL_2 ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -#define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -/* AES256_CTL0[CM] Bits */ -#define AES256_CTL0_CM_OFS ( 5) /*!< AESCMx Bit Offset */ -#define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /*!< AESCMx Bit Mask */ -#define AES256_CTL0_CM0 ((uint16_t)0x0020) /*!< CM Bit 0 */ -#define AES256_CTL0_CM1 ((uint16_t)0x0040) /*!< CM Bit 1 */ -#define AES256_CTL0_CM_0 ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM_1 ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM_2 ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM_3 ((uint16_t)0x0060) /*!< CFB */ -#define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /*!< CFB */ -/* AES256_CTL0[SWRST] Bits */ -#define AES256_CTL0_SWRST_OFS ( 7) /*!< AESSWRST Bit Offset */ -#define AES256_CTL0_SWRST ((uint16_t)0x0080) /*!< AES software reset */ -/* AES256_CTL0[RDYIFG] Bits */ -#define AES256_CTL0_RDYIFG_OFS ( 8) /*!< AESRDYIFG Bit Offset */ -#define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /*!< AES ready interrupt flag */ -/* AES256_CTL0[ERRFG] Bits */ -#define AES256_CTL0_ERRFG_OFS (11) /*!< AESERRFG Bit Offset */ -#define AES256_CTL0_ERRFG ((uint16_t)0x0800) /*!< AES error flag */ -/* AES256_CTL0[RDYIE] Bits */ -#define AES256_CTL0_RDYIE_OFS (12) /*!< AESRDYIE Bit Offset */ -#define AES256_CTL0_RDYIE ((uint16_t)0x1000) /*!< AES ready interrupt enable */ -/* AES256_CTL0[CMEN] Bits */ -#define AES256_CTL0_CMEN_OFS (15) /*!< AESCMEN Bit Offset */ -#define AES256_CTL0_CMEN ((uint16_t)0x8000) /*!< AES cipher mode enable */ -/* AES256_CTL1[BLKCNT] Bits */ -#define AES256_CTL1_BLKCNT_OFS ( 0) /*!< AESBLKCNTx Bit Offset */ -#define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /*!< AESBLKCNTx Bit Mask */ -#define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /*!< BLKCNT Bit 0 */ -#define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /*!< BLKCNT Bit 1 */ -#define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /*!< BLKCNT Bit 2 */ -#define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /*!< BLKCNT Bit 3 */ -#define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /*!< BLKCNT Bit 4 */ -#define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /*!< BLKCNT Bit 5 */ -#define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /*!< BLKCNT Bit 6 */ -#define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /*!< BLKCNT Bit 7 */ -/* AES256_STAT[BUSY] Bits */ -#define AES256_STAT_BUSY_OFS ( 0) /*!< AESBUSY Bit Offset */ -#define AES256_STAT_BUSY ((uint16_t)0x0001) /*!< AES accelerator module busy */ -/* AES256_STAT[KEYWR] Bits */ -#define AES256_STAT_KEYWR_OFS ( 1) /*!< AESKEYWR Bit Offset */ -#define AES256_STAT_KEYWR ((uint16_t)0x0002) /*!< All 16 bytes written to AESAKEY */ -/* AES256_STAT[DINWR] Bits */ -#define AES256_STAT_DINWR_OFS ( 2) /*!< AESDINWR Bit Offset */ -#define AES256_STAT_DINWR ((uint16_t)0x0004) /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ -/* AES256_STAT[DOUTRD] Bits */ -#define AES256_STAT_DOUTRD_OFS ( 3) /*!< AESDOUTRD Bit Offset */ -#define AES256_STAT_DOUTRD ((uint16_t)0x0008) /*!< All 16 bytes read from AESADOUT */ -/* AES256_STAT[KEYCNT] Bits */ -#define AES256_STAT_KEYCNT_OFS ( 4) /*!< AESKEYCNTx Bit Offset */ -#define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /*!< AESKEYCNTx Bit Mask */ -#define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /*!< KEYCNT Bit 0 */ -#define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /*!< KEYCNT Bit 1 */ -#define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /*!< KEYCNT Bit 2 */ -#define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /*!< KEYCNT Bit 3 */ -/* AES256_STAT[DINCNT] Bits */ -#define AES256_STAT_DINCNT_OFS ( 8) /*!< AESDINCNTx Bit Offset */ -#define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /*!< AESDINCNTx Bit Mask */ -#define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /*!< DINCNT Bit 0 */ -#define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /*!< DINCNT Bit 1 */ -#define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /*!< DINCNT Bit 2 */ -#define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /*!< DINCNT Bit 3 */ -/* AES256_STAT[DOUTCNT] Bits */ -#define AES256_STAT_DOUTCNT_OFS (12) /*!< AESDOUTCNTx Bit Offset */ -#define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /*!< AESDOUTCNTx Bit Mask */ -#define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /*!< DOUTCNT Bit 0 */ -#define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /*!< DOUTCNT Bit 1 */ -#define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /*!< DOUTCNT Bit 2 */ -#define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /*!< DOUTCNT Bit 3 */ -/* AES256_KEY[KEY0] Bits */ -#define AES256_KEY_KEY0_OFS ( 0) /*!< AESKEY0x Bit Offset */ -#define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /*!< AESKEY0x Bit Mask */ -#define AES256_KEY_KEY00 ((uint16_t)0x0001) /*!< KEY0 Bit 0 */ -#define AES256_KEY_KEY01 ((uint16_t)0x0002) /*!< KEY0 Bit 1 */ -#define AES256_KEY_KEY02 ((uint16_t)0x0004) /*!< KEY0 Bit 2 */ -#define AES256_KEY_KEY03 ((uint16_t)0x0008) /*!< KEY0 Bit 3 */ -#define AES256_KEY_KEY04 ((uint16_t)0x0010) /*!< KEY0 Bit 4 */ -#define AES256_KEY_KEY05 ((uint16_t)0x0020) /*!< KEY0 Bit 5 */ -#define AES256_KEY_KEY06 ((uint16_t)0x0040) /*!< KEY0 Bit 6 */ -#define AES256_KEY_KEY07 ((uint16_t)0x0080) /*!< KEY0 Bit 7 */ -/* AES256_KEY[KEY1] Bits */ -#define AES256_KEY_KEY1_OFS ( 8) /*!< AESKEY1x Bit Offset */ -#define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /*!< AESKEY1x Bit Mask */ -#define AES256_KEY_KEY10 ((uint16_t)0x0100) /*!< KEY1 Bit 0 */ -#define AES256_KEY_KEY11 ((uint16_t)0x0200) /*!< KEY1 Bit 1 */ -#define AES256_KEY_KEY12 ((uint16_t)0x0400) /*!< KEY1 Bit 2 */ -#define AES256_KEY_KEY13 ((uint16_t)0x0800) /*!< KEY1 Bit 3 */ -#define AES256_KEY_KEY14 ((uint16_t)0x1000) /*!< KEY1 Bit 4 */ -#define AES256_KEY_KEY15 ((uint16_t)0x2000) /*!< KEY1 Bit 5 */ -#define AES256_KEY_KEY16 ((uint16_t)0x4000) /*!< KEY1 Bit 6 */ -#define AES256_KEY_KEY17 ((uint16_t)0x8000) /*!< KEY1 Bit 7 */ -/* AES256_DIN[DIN0] Bits */ -#define AES256_DIN_DIN0_OFS ( 0) /*!< AESDIN0x Bit Offset */ -#define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /*!< AESDIN0x Bit Mask */ -#define AES256_DIN_DIN00 ((uint16_t)0x0001) /*!< DIN0 Bit 0 */ -#define AES256_DIN_DIN01 ((uint16_t)0x0002) /*!< DIN0 Bit 1 */ -#define AES256_DIN_DIN02 ((uint16_t)0x0004) /*!< DIN0 Bit 2 */ -#define AES256_DIN_DIN03 ((uint16_t)0x0008) /*!< DIN0 Bit 3 */ -#define AES256_DIN_DIN04 ((uint16_t)0x0010) /*!< DIN0 Bit 4 */ -#define AES256_DIN_DIN05 ((uint16_t)0x0020) /*!< DIN0 Bit 5 */ -#define AES256_DIN_DIN06 ((uint16_t)0x0040) /*!< DIN0 Bit 6 */ -#define AES256_DIN_DIN07 ((uint16_t)0x0080) /*!< DIN0 Bit 7 */ -/* AES256_DIN[DIN1] Bits */ -#define AES256_DIN_DIN1_OFS ( 8) /*!< AESDIN1x Bit Offset */ -#define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /*!< AESDIN1x Bit Mask */ -#define AES256_DIN_DIN10 ((uint16_t)0x0100) /*!< DIN1 Bit 0 */ -#define AES256_DIN_DIN11 ((uint16_t)0x0200) /*!< DIN1 Bit 1 */ -#define AES256_DIN_DIN12 ((uint16_t)0x0400) /*!< DIN1 Bit 2 */ -#define AES256_DIN_DIN13 ((uint16_t)0x0800) /*!< DIN1 Bit 3 */ -#define AES256_DIN_DIN14 ((uint16_t)0x1000) /*!< DIN1 Bit 4 */ -#define AES256_DIN_DIN15 ((uint16_t)0x2000) /*!< DIN1 Bit 5 */ -#define AES256_DIN_DIN16 ((uint16_t)0x4000) /*!< DIN1 Bit 6 */ -#define AES256_DIN_DIN17 ((uint16_t)0x8000) /*!< DIN1 Bit 7 */ -/* AES256_DOUT[DOUT0] Bits */ -#define AES256_DOUT_DOUT0_OFS ( 0) /*!< AESDOUT0x Bit Offset */ -#define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /*!< AESDOUT0x Bit Mask */ -#define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /*!< DOUT0 Bit 0 */ -#define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /*!< DOUT0 Bit 1 */ -#define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /*!< DOUT0 Bit 2 */ -#define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /*!< DOUT0 Bit 3 */ -#define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /*!< DOUT0 Bit 4 */ -#define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /*!< DOUT0 Bit 5 */ -#define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /*!< DOUT0 Bit 6 */ -#define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /*!< DOUT0 Bit 7 */ -/* AES256_DOUT[DOUT1] Bits */ -#define AES256_DOUT_DOUT1_OFS ( 8) /*!< AESDOUT1x Bit Offset */ -#define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /*!< AESDOUT1x Bit Mask */ -#define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /*!< DOUT1 Bit 0 */ -#define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /*!< DOUT1 Bit 1 */ -#define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /*!< DOUT1 Bit 2 */ -#define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /*!< DOUT1 Bit 3 */ -#define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /*!< DOUT1 Bit 4 */ -#define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /*!< DOUT1 Bit 5 */ -#define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /*!< DOUT1 Bit 6 */ -#define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /*!< DOUT1 Bit 7 */ -/* AES256_XDIN[XDIN0] Bits */ -#define AES256_XDIN_XDIN0_OFS ( 0) /*!< AESXDIN0x Bit Offset */ -#define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /*!< AESXDIN0x Bit Mask */ -#define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /*!< XDIN0 Bit 0 */ -#define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /*!< XDIN0 Bit 1 */ -#define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /*!< XDIN0 Bit 2 */ -#define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /*!< XDIN0 Bit 3 */ -#define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /*!< XDIN0 Bit 4 */ -#define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /*!< XDIN0 Bit 5 */ -#define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /*!< XDIN0 Bit 6 */ -#define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /*!< XDIN0 Bit 7 */ -/* AES256_XDIN[XDIN1] Bits */ -#define AES256_XDIN_XDIN1_OFS ( 8) /*!< AESXDIN1x Bit Offset */ -#define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /*!< AESXDIN1x Bit Mask */ -#define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /*!< XDIN1 Bit 0 */ -#define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /*!< XDIN1 Bit 1 */ -#define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /*!< XDIN1 Bit 2 */ -#define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /*!< XDIN1 Bit 3 */ -#define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /*!< XDIN1 Bit 4 */ -#define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /*!< XDIN1 Bit 5 */ -#define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /*!< XDIN1 Bit 6 */ -#define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /*!< XDIN1 Bit 7 */ -/* AES256_XIN[XIN0] Bits */ -#define AES256_XIN_XIN0_OFS ( 0) /*!< AESXIN0x Bit Offset */ -#define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /*!< AESXIN0x Bit Mask */ -#define AES256_XIN_XIN00 ((uint16_t)0x0001) /*!< XIN0 Bit 0 */ -#define AES256_XIN_XIN01 ((uint16_t)0x0002) /*!< XIN0 Bit 1 */ -#define AES256_XIN_XIN02 ((uint16_t)0x0004) /*!< XIN0 Bit 2 */ -#define AES256_XIN_XIN03 ((uint16_t)0x0008) /*!< XIN0 Bit 3 */ -#define AES256_XIN_XIN04 ((uint16_t)0x0010) /*!< XIN0 Bit 4 */ -#define AES256_XIN_XIN05 ((uint16_t)0x0020) /*!< XIN0 Bit 5 */ -#define AES256_XIN_XIN06 ((uint16_t)0x0040) /*!< XIN0 Bit 6 */ -#define AES256_XIN_XIN07 ((uint16_t)0x0080) /*!< XIN0 Bit 7 */ -/* AES256_XIN[XIN1] Bits */ -#define AES256_XIN_XIN1_OFS ( 8) /*!< AESXIN1x Bit Offset */ -#define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /*!< AESXIN1x Bit Mask */ -#define AES256_XIN_XIN10 ((uint16_t)0x0100) /*!< XIN1 Bit 0 */ -#define AES256_XIN_XIN11 ((uint16_t)0x0200) /*!< XIN1 Bit 1 */ -#define AES256_XIN_XIN12 ((uint16_t)0x0400) /*!< XIN1 Bit 2 */ -#define AES256_XIN_XIN13 ((uint16_t)0x0800) /*!< XIN1 Bit 3 */ -#define AES256_XIN_XIN14 ((uint16_t)0x1000) /*!< XIN1 Bit 4 */ -#define AES256_XIN_XIN15 ((uint16_t)0x2000) /*!< XIN1 Bit 5 */ -#define AES256_XIN_XIN16 ((uint16_t)0x4000) /*!< XIN1 Bit 6 */ -#define AES256_XIN_XIN17 ((uint16_t)0x8000) /*!< XIN1 Bit 7 */ - -/****************************************************************************** -* CAPTIO Bits -******************************************************************************/ -/* CAPTIO_CTL[PISEL] Bits */ -#define CAPTIO_CTL_PISEL_OFS ( 1) /*!< CAPTIOPISELx Bit Offset */ -#define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /*!< CAPTIOPISELx Bit Mask */ -#define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /*!< PISEL Bit 0 */ -#define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /*!< PISEL Bit 1 */ -#define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /*!< PISEL Bit 2 */ -#define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /*!< Px.0 */ -#define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /*!< Px.1 */ -#define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /*!< Px.2 */ -#define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /*!< Px.3 */ -#define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /*!< Px.4 */ -#define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /*!< Px.5 */ -#define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /*!< Px.6 */ -#define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /*!< Px.7 */ -/* CAPTIO_CTL[POSEL] Bits */ -#define CAPTIO_CTL_POSEL_OFS ( 4) /*!< CAPTIOPOSELx Bit Offset */ -#define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /*!< CAPTIOPOSELx Bit Mask */ -#define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /*!< POSEL Bit 0 */ -#define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /*!< POSEL Bit 1 */ -#define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /*!< POSEL Bit 2 */ -#define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /*!< POSEL Bit 3 */ -#define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /*!< Px = P15 */ -#define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /*!< Px = P15 */ -/* CAPTIO_CTL[EN] Bits */ -#define CAPTIO_CTL_EN_OFS ( 8) /*!< CAPTIOEN Bit Offset */ -#define CAPTIO_CTL_EN ((uint16_t)0x0100) /*!< Capacitive Touch IO enable */ -/* CAPTIO_CTL[STATE] Bits */ -#define CAPTIO_CTL_STATE_OFS ( 9) /*!< CAPTIOSTATE Bit Offset */ -#define CAPTIO_CTL_STATE ((uint16_t)0x0200) /*!< Capacitive Touch IO state */ - -/****************************************************************************** -* COMP_E Bits -******************************************************************************/ -/* COMP_E_CTL0[IPSEL] Bits */ -#define COMP_E_CTL0_IPSEL_OFS ( 0) /*!< CEIPSEL Bit Offset */ -#define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /*!< CEIPSEL Bit Mask */ -#define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /*!< IPSEL Bit 0 */ -#define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /*!< IPSEL Bit 1 */ -#define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /*!< IPSEL Bit 2 */ -#define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /*!< IPSEL Bit 3 */ -#define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /*!< Channel 15 selected */ -/* COMP_E_CTL0[IPEN] Bits */ -#define COMP_E_CTL0_IPEN_OFS ( 7) /*!< CEIPEN Bit Offset */ -#define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /*!< Channel input enable for the V+ terminal */ -/* COMP_E_CTL0[IMSEL] Bits */ -#define COMP_E_CTL0_IMSEL_OFS ( 8) /*!< CEIMSEL Bit Offset */ -#define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /*!< CEIMSEL Bit Mask */ -#define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /*!< IMSEL Bit 0 */ -#define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /*!< IMSEL Bit 1 */ -#define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /*!< IMSEL Bit 2 */ -#define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /*!< IMSEL Bit 3 */ -#define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /*!< Channel 15 selected */ -/* COMP_E_CTL0[IMEN] Bits */ -#define COMP_E_CTL0_IMEN_OFS (15) /*!< CEIMEN Bit Offset */ -#define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /*!< Channel input enable for the - terminal */ -/* COMP_E_CTL1[OUT] Bits */ -#define COMP_E_CTL1_OUT_OFS ( 0) /*!< CEOUT Bit Offset */ -#define COMP_E_CTL1_OUT ((uint16_t)0x0001) /*!< Comparator output value */ -/* COMP_E_CTL1[OUTPOL] Bits */ -#define COMP_E_CTL1_OUTPOL_OFS ( 1) /*!< CEOUTPOL Bit Offset */ -#define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /*!< Comparator output polarity */ -/* COMP_E_CTL1[F] Bits */ -#define COMP_E_CTL1_F_OFS ( 2) /*!< CEF Bit Offset */ -#define COMP_E_CTL1_F ((uint16_t)0x0004) /*!< Comparator output filter */ -/* COMP_E_CTL1[IES] Bits */ -#define COMP_E_CTL1_IES_OFS ( 3) /*!< CEIES Bit Offset */ -#define COMP_E_CTL1_IES ((uint16_t)0x0008) /*!< Interrupt edge select for CEIIFG and CEIFG */ -/* COMP_E_CTL1[SHORT] Bits */ -#define COMP_E_CTL1_SHORT_OFS ( 4) /*!< CESHORT Bit Offset */ -#define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /*!< Input short */ -/* COMP_E_CTL1[EX] Bits */ -#define COMP_E_CTL1_EX_OFS ( 5) /*!< CEEX Bit Offset */ -#define COMP_E_CTL1_EX ((uint16_t)0x0020) /*!< Exchange */ -/* COMP_E_CTL1[FDLY] Bits */ -#define COMP_E_CTL1_FDLY_OFS ( 6) /*!< CEFDLY Bit Offset */ -#define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /*!< CEFDLY Bit Mask */ -#define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /*!< FDLY Bit 0 */ -#define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /*!< FDLY Bit 1 */ -#define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /*!< Typical filter delay of TBD (450) ns */ -#define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /*!< Typical filter delay of TBD (900) ns */ -#define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /*!< Typical filter delay of TBD (1800) ns */ -#define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /*!< Typical filter delay of TBD (3600) ns */ -/* COMP_E_CTL1[PWRMD] Bits */ -#define COMP_E_CTL1_PWRMD_OFS ( 8) /*!< CEPWRMD Bit Offset */ -#define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /*!< CEPWRMD Bit Mask */ -#define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /*!< PWRMD Bit 0 */ -#define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /*!< PWRMD Bit 1 */ -#define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /*!< High-speed mode */ -#define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /*!< Normal mode */ -#define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /*!< Ultra-low power mode */ -/* COMP_E_CTL1[ON] Bits */ -#define COMP_E_CTL1_ON_OFS (10) /*!< CEON Bit Offset */ -#define COMP_E_CTL1_ON ((uint16_t)0x0400) /*!< Comparator On */ -/* COMP_E_CTL1[MRVL] Bits */ -#define COMP_E_CTL1_MRVL_OFS (11) /*!< CEMRVL Bit Offset */ -#define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /*!< This bit is valid of CEMRVS is set to 1 */ -/* COMP_E_CTL1[MRVS] Bits */ -#define COMP_E_CTL1_MRVS_OFS (12) /*!< CEMRVS Bit Offset */ -#define COMP_E_CTL1_MRVS ((uint16_t)0x1000) -/* COMP_E_CTL2[REF0] Bits */ -#define COMP_E_CTL2_REF0_OFS ( 0) /*!< CEREF0 Bit Offset */ -#define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /*!< CEREF0 Bit Mask */ -#define COMP_E_CTL2_REF00 ((uint16_t)0x0001) /*!< REF0 Bit 0 */ -#define COMP_E_CTL2_REF01 ((uint16_t)0x0002) /*!< REF0 Bit 1 */ -#define COMP_E_CTL2_REF02 ((uint16_t)0x0004) /*!< REF0 Bit 2 */ -#define COMP_E_CTL2_REF03 ((uint16_t)0x0008) /*!< REF0 Bit 3 */ -#define COMP_E_CTL2_REF04 ((uint16_t)0x0010) /*!< REF0 Bit 4 */ -#define COMP_E_CTL2_REF0_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ -#define COMP_E_CTL2_REF0_1 ((uint16_t)0x0001) /*!< Reference resistor tap for setting 1. */ -#define COMP_E_CTL2_REF0_2 ((uint16_t)0x0002) /*!< Reference resistor tap for setting 2. */ -#define COMP_E_CTL2_REF0_3 ((uint16_t)0x0003) /*!< Reference resistor tap for setting 3. */ -#define COMP_E_CTL2_REF0_4 ((uint16_t)0x0004) /*!< Reference resistor tap for setting 4. */ -#define COMP_E_CTL2_REF0_5 ((uint16_t)0x0005) /*!< Reference resistor tap for setting 5. */ -#define COMP_E_CTL2_REF0_6 ((uint16_t)0x0006) /*!< Reference resistor tap for setting 6. */ -#define COMP_E_CTL2_REF0_7 ((uint16_t)0x0007) /*!< Reference resistor tap for setting 7. */ -#define COMP_E_CTL2_REF0_8 ((uint16_t)0x0008) /*!< Reference resistor tap for setting 8. */ -#define COMP_E_CTL2_REF0_9 ((uint16_t)0x0009) /*!< Reference resistor tap for setting 9. */ -#define COMP_E_CTL2_REF0_10 ((uint16_t)0x000A) /*!< Reference resistor tap for setting 10. */ -#define COMP_E_CTL2_REF0_11 ((uint16_t)0x000B) /*!< Reference resistor tap for setting 11. */ -#define COMP_E_CTL2_REF0_12 ((uint16_t)0x000C) /*!< Reference resistor tap for setting 12. */ -#define COMP_E_CTL2_REF0_13 ((uint16_t)0x000D) /*!< Reference resistor tap for setting 13. */ -#define COMP_E_CTL2_REF0_14 ((uint16_t)0x000E) /*!< Reference resistor tap for setting 14. */ -#define COMP_E_CTL2_REF0_15 ((uint16_t)0x000F) /*!< Reference resistor tap for setting 15. */ -#define COMP_E_CTL2_REF0_16 ((uint16_t)0x0010) /*!< Reference resistor tap for setting 16. */ -#define COMP_E_CTL2_REF0_17 ((uint16_t)0x0011) /*!< Reference resistor tap for setting 17. */ -#define COMP_E_CTL2_REF0_18 ((uint16_t)0x0012) /*!< Reference resistor tap for setting 18. */ -#define COMP_E_CTL2_REF0_19 ((uint16_t)0x0013) /*!< Reference resistor tap for setting 19. */ -#define COMP_E_CTL2_REF0_20 ((uint16_t)0x0014) /*!< Reference resistor tap for setting 20. */ -#define COMP_E_CTL2_REF0_21 ((uint16_t)0x0015) /*!< Reference resistor tap for setting 21. */ -#define COMP_E_CTL2_REF0_22 ((uint16_t)0x0016) /*!< Reference resistor tap for setting 22. */ -#define COMP_E_CTL2_REF0_23 ((uint16_t)0x0017) /*!< Reference resistor tap for setting 23. */ -#define COMP_E_CTL2_REF0_24 ((uint16_t)0x0018) /*!< Reference resistor tap for setting 24. */ -#define COMP_E_CTL2_REF0_25 ((uint16_t)0x0019) /*!< Reference resistor tap for setting 25. */ -#define COMP_E_CTL2_REF0_26 ((uint16_t)0x001A) /*!< Reference resistor tap for setting 26. */ -#define COMP_E_CTL2_REF0_27 ((uint16_t)0x001B) /*!< Reference resistor tap for setting 27. */ -#define COMP_E_CTL2_REF0_28 ((uint16_t)0x001C) /*!< Reference resistor tap for setting 28. */ -#define COMP_E_CTL2_REF0_29 ((uint16_t)0x001D) /*!< Reference resistor tap for setting 29. */ -#define COMP_E_CTL2_REF0_30 ((uint16_t)0x001E) /*!< Reference resistor tap for setting 30. */ -#define COMP_E_CTL2_REF0_31 ((uint16_t)0x001F) /*!< Reference resistor tap for setting 31. */ -/* COMP_E_CTL2[RSEL] Bits */ -#define COMP_E_CTL2_RSEL_OFS ( 5) /*!< CERSEL Bit Offset */ -#define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /*!< Reference select */ -/* COMP_E_CTL2[RS] Bits */ -#define COMP_E_CTL2_RS_OFS ( 6) /*!< CERS Bit Offset */ -#define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /*!< CERS Bit Mask */ -#define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /*!< RS Bit 0 */ -#define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /*!< RS Bit 1 */ -#define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /*!< No current is drawn by the reference circuitry */ -#define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /*!< VCC applied to the resistor ladder */ -#define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /*!< Shared reference voltage applied to the resistor ladder */ -#define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ -/* COMP_E_CTL2[REF1] Bits */ -#define COMP_E_CTL2_REF1_OFS ( 8) /*!< CEREF1 Bit Offset */ -#define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /*!< CEREF1 Bit Mask */ -#define COMP_E_CTL2_REF10 ((uint16_t)0x0100) /*!< REF1 Bit 0 */ -#define COMP_E_CTL2_REF11 ((uint16_t)0x0200) /*!< REF1 Bit 1 */ -#define COMP_E_CTL2_REF12 ((uint16_t)0x0400) /*!< REF1 Bit 2 */ -#define COMP_E_CTL2_REF13 ((uint16_t)0x0800) /*!< REF1 Bit 3 */ -#define COMP_E_CTL2_REF14 ((uint16_t)0x1000) /*!< REF1 Bit 4 */ -#define COMP_E_CTL2_REF1_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ -#define COMP_E_CTL2_REF1_1 ((uint16_t)0x0100) /*!< Reference resistor tap for setting 1. */ -#define COMP_E_CTL2_REF1_2 ((uint16_t)0x0200) /*!< Reference resistor tap for setting 2. */ -#define COMP_E_CTL2_REF1_3 ((uint16_t)0x0300) /*!< Reference resistor tap for setting 3. */ -#define COMP_E_CTL2_REF1_4 ((uint16_t)0x0400) /*!< Reference resistor tap for setting 4. */ -#define COMP_E_CTL2_REF1_5 ((uint16_t)0x0500) /*!< Reference resistor tap for setting 5. */ -#define COMP_E_CTL2_REF1_6 ((uint16_t)0x0600) /*!< Reference resistor tap for setting 6. */ -#define COMP_E_CTL2_REF1_7 ((uint16_t)0x0700) /*!< Reference resistor tap for setting 7. */ -#define COMP_E_CTL2_REF1_8 ((uint16_t)0x0800) /*!< Reference resistor tap for setting 8. */ -#define COMP_E_CTL2_REF1_9 ((uint16_t)0x0900) /*!< Reference resistor tap for setting 9. */ -#define COMP_E_CTL2_REF1_10 ((uint16_t)0x0A00) /*!< Reference resistor tap for setting 10. */ -#define COMP_E_CTL2_REF1_11 ((uint16_t)0x0B00) /*!< Reference resistor tap for setting 11. */ -#define COMP_E_CTL2_REF1_12 ((uint16_t)0x0C00) /*!< Reference resistor tap for setting 12. */ -#define COMP_E_CTL2_REF1_13 ((uint16_t)0x0D00) /*!< Reference resistor tap for setting 13. */ -#define COMP_E_CTL2_REF1_14 ((uint16_t)0x0E00) /*!< Reference resistor tap for setting 14. */ -#define COMP_E_CTL2_REF1_15 ((uint16_t)0x0F00) /*!< Reference resistor tap for setting 15. */ -#define COMP_E_CTL2_REF1_16 ((uint16_t)0x1000) /*!< Reference resistor tap for setting 16. */ -#define COMP_E_CTL2_REF1_17 ((uint16_t)0x1100) /*!< Reference resistor tap for setting 17. */ -#define COMP_E_CTL2_REF1_18 ((uint16_t)0x1200) /*!< Reference resistor tap for setting 18. */ -#define COMP_E_CTL2_REF1_19 ((uint16_t)0x1300) /*!< Reference resistor tap for setting 19. */ -#define COMP_E_CTL2_REF1_20 ((uint16_t)0x1400) /*!< Reference resistor tap for setting 20. */ -#define COMP_E_CTL2_REF1_21 ((uint16_t)0x1500) /*!< Reference resistor tap for setting 21. */ -#define COMP_E_CTL2_REF1_22 ((uint16_t)0x1600) /*!< Reference resistor tap for setting 22. */ -#define COMP_E_CTL2_REF1_23 ((uint16_t)0x1700) /*!< Reference resistor tap for setting 23. */ -#define COMP_E_CTL2_REF1_24 ((uint16_t)0x1800) /*!< Reference resistor tap for setting 24. */ -#define COMP_E_CTL2_REF1_25 ((uint16_t)0x1900) /*!< Reference resistor tap for setting 25. */ -#define COMP_E_CTL2_REF1_26 ((uint16_t)0x1A00) /*!< Reference resistor tap for setting 26. */ -#define COMP_E_CTL2_REF1_27 ((uint16_t)0x1B00) /*!< Reference resistor tap for setting 27. */ -#define COMP_E_CTL2_REF1_28 ((uint16_t)0x1C00) /*!< Reference resistor tap for setting 28. */ -#define COMP_E_CTL2_REF1_29 ((uint16_t)0x1D00) /*!< Reference resistor tap for setting 29. */ -#define COMP_E_CTL2_REF1_30 ((uint16_t)0x1E00) /*!< Reference resistor tap for setting 30. */ -#define COMP_E_CTL2_REF1_31 ((uint16_t)0x1F00) /*!< Reference resistor tap for setting 31. */ -/* COMP_E_CTL2[REFL] Bits */ -#define COMP_E_CTL2_REFL_OFS (13) /*!< CEREFL Bit Offset */ -#define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /*!< CEREFL Bit Mask */ -#define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /*!< REFL Bit 0 */ -#define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /*!< REFL Bit 1 */ -#define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -/* COMP_E_CTL2[REFACC] Bits */ -#define COMP_E_CTL2_REFACC_OFS (15) /*!< CEREFACC Bit Offset */ -#define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /*!< Reference accuracy */ -/* COMP_E_CTL3[PD0] Bits */ -#define COMP_E_CTL3_PD0_OFS ( 0) /*!< CEPD0 Bit Offset */ -#define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /*!< Port disable */ -/* COMP_E_CTL3[PD1] Bits */ -#define COMP_E_CTL3_PD1_OFS ( 1) /*!< CEPD1 Bit Offset */ -#define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /*!< Port disable */ -/* COMP_E_CTL3[PD2] Bits */ -#define COMP_E_CTL3_PD2_OFS ( 2) /*!< CEPD2 Bit Offset */ -#define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /*!< Port disable */ -/* COMP_E_CTL3[PD3] Bits */ -#define COMP_E_CTL3_PD3_OFS ( 3) /*!< CEPD3 Bit Offset */ -#define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /*!< Port disable */ -/* COMP_E_CTL3[PD4] Bits */ -#define COMP_E_CTL3_PD4_OFS ( 4) /*!< CEPD4 Bit Offset */ -#define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /*!< Port disable */ -/* COMP_E_CTL3[PD5] Bits */ -#define COMP_E_CTL3_PD5_OFS ( 5) /*!< CEPD5 Bit Offset */ -#define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /*!< Port disable */ -/* COMP_E_CTL3[PD6] Bits */ -#define COMP_E_CTL3_PD6_OFS ( 6) /*!< CEPD6 Bit Offset */ -#define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /*!< Port disable */ -/* COMP_E_CTL3[PD7] Bits */ -#define COMP_E_CTL3_PD7_OFS ( 7) /*!< CEPD7 Bit Offset */ -#define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /*!< Port disable */ -/* COMP_E_CTL3[PD8] Bits */ -#define COMP_E_CTL3_PD8_OFS ( 8) /*!< CEPD8 Bit Offset */ -#define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /*!< Port disable */ -/* COMP_E_CTL3[PD9] Bits */ -#define COMP_E_CTL3_PD9_OFS ( 9) /*!< CEPD9 Bit Offset */ -#define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /*!< Port disable */ -/* COMP_E_CTL3[PD10] Bits */ -#define COMP_E_CTL3_PD10_OFS (10) /*!< CEPD10 Bit Offset */ -#define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /*!< Port disable */ -/* COMP_E_CTL3[PD11] Bits */ -#define COMP_E_CTL3_PD11_OFS (11) /*!< CEPD11 Bit Offset */ -#define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /*!< Port disable */ -/* COMP_E_CTL3[PD12] Bits */ -#define COMP_E_CTL3_PD12_OFS (12) /*!< CEPD12 Bit Offset */ -#define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /*!< Port disable */ -/* COMP_E_CTL3[PD13] Bits */ -#define COMP_E_CTL3_PD13_OFS (13) /*!< CEPD13 Bit Offset */ -#define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /*!< Port disable */ -/* COMP_E_CTL3[PD14] Bits */ -#define COMP_E_CTL3_PD14_OFS (14) /*!< CEPD14 Bit Offset */ -#define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /*!< Port disable */ -/* COMP_E_CTL3[PD15] Bits */ -#define COMP_E_CTL3_PD15_OFS (15) /*!< CEPD15 Bit Offset */ -#define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /*!< Port disable */ -/* COMP_E_INT[IFG] Bits */ -#define COMP_E_INT_IFG_OFS ( 0) /*!< CEIFG Bit Offset */ -#define COMP_E_INT_IFG ((uint16_t)0x0001) /*!< Comparator output interrupt flag */ -/* COMP_E_INT[IIFG] Bits */ -#define COMP_E_INT_IIFG_OFS ( 1) /*!< CEIIFG Bit Offset */ -#define COMP_E_INT_IIFG ((uint16_t)0x0002) /*!< Comparator output inverted interrupt flag */ -/* COMP_E_INT[RDYIFG] Bits */ -#define COMP_E_INT_RDYIFG_OFS ( 4) /*!< CERDYIFG Bit Offset */ -#define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /*!< Comparator ready interrupt flag */ -/* COMP_E_INT[IE] Bits */ -#define COMP_E_INT_IE_OFS ( 8) /*!< CEIE Bit Offset */ -#define COMP_E_INT_IE ((uint16_t)0x0100) /*!< Comparator output interrupt enable */ -/* COMP_E_INT[IIE] Bits */ -#define COMP_E_INT_IIE_OFS ( 9) /*!< CEIIE Bit Offset */ -#define COMP_E_INT_IIE ((uint16_t)0x0200) /*!< Comparator output interrupt enable inverted polarity */ -/* COMP_E_INT[RDYIE] Bits */ -#define COMP_E_INT_RDYIE_OFS (12) /*!< CERDYIE Bit Offset */ -#define COMP_E_INT_RDYIE ((uint16_t)0x1000) /*!< Comparator ready interrupt enable */ - -/****************************************************************************** -* COREDEBUG Bits -******************************************************************************/ - - -/****************************************************************************** -* CRC32 Bits -******************************************************************************/ - -/****************************************************************************** -* CS Bits -******************************************************************************/ -/* CS_KEY[KEY] Bits */ -#define CS_KEY_KEY_OFS ( 0) /*!< CSKEY Bit Offset */ -#define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< CSKEY Bit Mask */ -/* CS_CTL0[DCOTUNE] Bits */ -#define CS_CTL0_DCOTUNE_OFS ( 0) /*!< DCOTUNE Bit Offset */ -#define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /*!< DCOTUNE Bit Mask */ -/* CS_CTL0[DCORSEL] Bits */ -#define CS_CTL0_DCORSEL_OFS (16) /*!< DCORSEL Bit Offset */ -#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /*!< DCORSEL Bit Mask */ -#define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /*!< DCORSEL Bit 0 */ -#define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /*!< DCORSEL Bit 1 */ -#define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /*!< DCORSEL Bit 2 */ -#define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */ -#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */ -#define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */ -#define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */ -#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */ -#define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */ -/* CS_CTL0[DCORES] Bits */ -#define CS_CTL0_DCORES_OFS (22) /*!< DCORES Bit Offset */ -#define CS_CTL0_DCORES ((uint32_t)0x00400000) /*!< Enables the DCO external resistor mode */ -/* CS_CTL0[DCOEN] Bits */ -#define CS_CTL0_DCOEN_OFS (23) /*!< DCOEN Bit Offset */ -#define CS_CTL0_DCOEN ((uint32_t)0x00800000) /*!< Enables the DCO oscillator */ -/* CS_CTL1[SELM] Bits */ -#define CS_CTL1_SELM_OFS ( 0) /*!< SELM Bit Offset */ -#define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /*!< SELM Bit Mask */ -#define CS_CTL1_SELM0 ((uint32_t)0x00000001) /*!< SELM Bit 0 */ -#define CS_CTL1_SELM1 ((uint32_t)0x00000002) /*!< SELM Bit 1 */ -#define CS_CTL1_SELM2 ((uint32_t)0x00000004) /*!< SELM Bit 2 */ -#define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM_1 ((uint32_t)0x00000001) -#define CS_CTL1_SELM_2 ((uint32_t)0x00000002) -#define CS_CTL1_SELM_3 ((uint32_t)0x00000003) -#define CS_CTL1_SELM_4 ((uint32_t)0x00000004) -#define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001) -#define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002) -#define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003) -#define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004) -#define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -/* CS_CTL1[SELS] Bits */ -#define CS_CTL1_SELS_OFS ( 4) /*!< SELS Bit Offset */ -#define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /*!< SELS Bit Mask */ -#define CS_CTL1_SELS0 ((uint32_t)0x00000010) /*!< SELS Bit 0 */ -#define CS_CTL1_SELS1 ((uint32_t)0x00000020) /*!< SELS Bit 1 */ -#define CS_CTL1_SELS2 ((uint32_t)0x00000040) /*!< SELS Bit 2 */ -#define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS_1 ((uint32_t)0x00000010) -#define CS_CTL1_SELS_2 ((uint32_t)0x00000020) -#define CS_CTL1_SELS_3 ((uint32_t)0x00000030) -#define CS_CTL1_SELS_4 ((uint32_t)0x00000040) -#define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010) -#define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020) -#define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030) -#define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040) -#define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -/* CS_CTL1[SELA] Bits */ -#define CS_CTL1_SELA_OFS ( 8) /*!< SELA Bit Offset */ -#define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /*!< SELA Bit Mask */ -#define CS_CTL1_SELA0 ((uint32_t)0x00000100) /*!< SELA Bit 0 */ -#define CS_CTL1_SELA1 ((uint32_t)0x00000200) /*!< SELA Bit 1 */ -#define CS_CTL1_SELA2 ((uint32_t)0x00000400) /*!< SELA Bit 2 */ -#define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA_1 ((uint32_t)0x00000100) -#define CS_CTL1_SELA_2 ((uint32_t)0x00000200) -#define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100) -#define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200) -/* CS_CTL1[SELB] Bits */ -#define CS_CTL1_SELB_OFS (12) /*!< SELB Bit Offset */ -#define CS_CTL1_SELB ((uint32_t)0x00001000) /*!< Selects the BCLK source */ -/* CS_CTL1[DIVM] Bits */ -#define CS_CTL1_DIVM_OFS (16) /*!< DIVM Bit Offset */ -#define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /*!< DIVM Bit Mask */ -#define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /*!< DIVM Bit 0 */ -#define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /*!< DIVM Bit 1 */ -#define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /*!< DIVM Bit 2 */ -#define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -#define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -/* CS_CTL1[DIVHS] Bits */ -#define CS_CTL1_DIVHS_OFS (20) /*!< DIVHS Bit Offset */ -#define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /*!< DIVHS Bit Mask */ -#define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /*!< DIVHS Bit 0 */ -#define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /*!< DIVHS Bit 1 */ -#define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /*!< DIVHS Bit 2 */ -#define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -#define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -/* CS_CTL1[DIVA] Bits */ -#define CS_CTL1_DIVA_OFS (24) /*!< DIVA Bit Offset */ -#define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /*!< DIVA Bit Mask */ -#define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /*!< DIVA Bit 0 */ -#define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /*!< DIVA Bit 1 */ -#define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /*!< DIVA Bit 2 */ -#define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -#define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -/* CS_CTL1[DIVS] Bits */ -#define CS_CTL1_DIVS_OFS (28) /*!< DIVS Bit Offset */ -#define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /*!< DIVS Bit Mask */ -#define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /*!< DIVS Bit 0 */ -#define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /*!< DIVS Bit 1 */ -#define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /*!< DIVS Bit 2 */ -#define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -#define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -/* CS_CTL2[LFXTDRIVE] Bits */ -#define CS_CTL2_LFXTDRIVE_OFS ( 0) /*!< LFXTDRIVE Bit Offset */ -#define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /*!< LFXTDRIVE Bit Mask */ -#define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /*!< LFXTDRIVE Bit 0 */ -#define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /*!< LFXTDRIVE Bit 1 */ -#define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /*!< Lowest drive strength and current consumption LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */ -/* CS_CTL2[LFXT_EN] Bits */ -#define CS_CTL2_LFXT_EN_OFS ( 8) /*!< LFXT_EN Bit Offset */ -#define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /*!< Turns on the LFXT oscillator regardless if used as a clock resource */ -/* CS_CTL2[LFXTBYPASS] Bits */ -#define CS_CTL2_LFXTBYPASS_OFS ( 9) /*!< LFXTBYPASS Bit Offset */ -#define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /*!< LFXT bypass select */ -/* CS_CTL2[HFXTDRIVE] Bits */ -#define CS_CTL2_HFXTDRIVE_OFS (16) /*!< HFXTDRIVE Bit Offset */ -#define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /*!< HFXT oscillator drive selection */ -/* CS_CTL2[HFXTFREQ] Bits */ -#define CS_CTL2_HFXTFREQ_OFS (20) /*!< HFXTFREQ Bit Offset */ -#define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /*!< HFXTFREQ Bit Mask */ -#define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /*!< HFXTFREQ Bit 0 */ -#define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /*!< HFXTFREQ Bit 1 */ -#define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /*!< HFXTFREQ Bit 2 */ -#define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /*!< 1 MHz to 4 MHz */ -#define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /*!< >4 MHz to 8 MHz */ -#define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /*!< >8 MHz to 16 MHz */ -#define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /*!< >16 MHz to 24 MHz */ -#define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /*!< >24 MHz to 32 MHz */ -#define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /*!< >32 MHz to 40 MHz */ -#define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /*!< >40 MHz to 48 MHz */ -#define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /*!< Reserved for future use. */ -/* CS_CTL2[HFXT_EN] Bits */ -#define CS_CTL2_HFXT_EN_OFS (24) /*!< HFXT_EN Bit Offset */ -#define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /*!< Turns on the HFXT oscillator regardless if used as a clock resource */ -/* CS_CTL2[HFXTBYPASS] Bits */ -#define CS_CTL2_HFXTBYPASS_OFS (25) /*!< HFXTBYPASS Bit Offset */ -#define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /*!< HFXT bypass select */ -/* CS_CTL3[FCNTLF] Bits */ -#define CS_CTL3_FCNTLF_OFS ( 0) /*!< FCNTLF Bit Offset */ -#define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /*!< FCNTLF Bit Mask */ -#define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /*!< FCNTLF Bit 0 */ -#define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /*!< FCNTLF Bit 1 */ -#define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /*!< 32768 cycles */ -#define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /*!< 32768 cycles */ -/* CS_CTL3[RFCNTLF] Bits */ -#define CS_CTL3_RFCNTLF_OFS ( 2) /*!< RFCNTLF Bit Offset */ -#define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /*!< Reset start fault counter for LFXT */ -/* CS_CTL3[FCNTLF_EN] Bits */ -#define CS_CTL3_FCNTLF_EN_OFS ( 3) /*!< FCNTLF_EN Bit Offset */ -#define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /*!< Enable start fault counter for LFXT */ -/* CS_CTL3[FCNTHF] Bits */ -#define CS_CTL3_FCNTHF_OFS ( 4) /*!< FCNTHF Bit Offset */ -#define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /*!< FCNTHF Bit Mask */ -#define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /*!< FCNTHF Bit 0 */ -#define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /*!< FCNTHF Bit 1 */ -#define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /*!< 16384 cycles */ -#define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /*!< 16384 cycles */ -/* CS_CTL3[RFCNTHF] Bits */ -#define CS_CTL3_RFCNTHF_OFS ( 6) /*!< RFCNTHF Bit Offset */ -#define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /*!< Reset start fault counter for HFXT */ -/* CS_CTL3[FCNTHF_EN] Bits */ -#define CS_CTL3_FCNTHF_EN_OFS ( 7) /*!< FCNTHF_EN Bit Offset */ -#define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /*!< Enable start fault counter for HFXT */ -/* CS_CLKEN[ACLK_EN] Bits */ -#define CS_CLKEN_ACLK_EN_OFS ( 0) /*!< ACLK_EN Bit Offset */ -#define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /*!< ACLK system clock conditional request enable */ -/* CS_CLKEN[MCLK_EN] Bits */ -#define CS_CLKEN_MCLK_EN_OFS ( 1) /*!< MCLK_EN Bit Offset */ -#define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /*!< MCLK system clock conditional request enable */ -/* CS_CLKEN[HSMCLK_EN] Bits */ -#define CS_CLKEN_HSMCLK_EN_OFS ( 2) /*!< HSMCLK_EN Bit Offset */ -#define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /*!< HSMCLK system clock conditional request enable */ -/* CS_CLKEN[SMCLK_EN] Bits */ -#define CS_CLKEN_SMCLK_EN_OFS ( 3) /*!< SMCLK_EN Bit Offset */ -#define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /*!< SMCLK system clock conditional request enable */ -/* CS_CLKEN[VLO_EN] Bits */ -#define CS_CLKEN_VLO_EN_OFS ( 8) /*!< VLO_EN Bit Offset */ -#define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /*!< Turns on the VLO oscillator */ -/* CS_CLKEN[REFO_EN] Bits */ -#define CS_CLKEN_REFO_EN_OFS ( 9) /*!< REFO_EN Bit Offset */ -#define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /*!< Turns on the REFO oscillator */ -/* CS_CLKEN[MODOSC_EN] Bits */ -#define CS_CLKEN_MODOSC_EN_OFS (10) /*!< MODOSC_EN Bit Offset */ -#define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /*!< Turns on the MODOSC oscillator */ -/* CS_CLKEN[REFOFSEL] Bits */ -#define CS_CLKEN_REFOFSEL_OFS (15) /*!< REFOFSEL Bit Offset */ -#define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /*!< Selects REFO nominal frequency */ -/* CS_STAT[DCO_ON] Bits */ -#define CS_STAT_DCO_ON_OFS ( 0) /*!< DCO_ON Bit Offset */ -#define CS_STAT_DCO_ON ((uint32_t)0x00000001) /*!< DCO status */ -/* CS_STAT[DCOBIAS_ON] Bits */ -#define CS_STAT_DCOBIAS_ON_OFS ( 1) /*!< DCOBIAS_ON Bit Offset */ -#define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /*!< DCO bias status */ -/* CS_STAT[HFXT_ON] Bits */ -#define CS_STAT_HFXT_ON_OFS ( 2) /*!< HFXT_ON Bit Offset */ -#define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /*!< HFXT status */ -/* CS_STAT[MODOSC_ON] Bits */ -#define CS_STAT_MODOSC_ON_OFS ( 4) /*!< MODOSC_ON Bit Offset */ -#define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /*!< MODOSC status */ -/* CS_STAT[VLO_ON] Bits */ -#define CS_STAT_VLO_ON_OFS ( 5) /*!< VLO_ON Bit Offset */ -#define CS_STAT_VLO_ON ((uint32_t)0x00000020) /*!< VLO status */ -/* CS_STAT[LFXT_ON] Bits */ -#define CS_STAT_LFXT_ON_OFS ( 6) /*!< LFXT_ON Bit Offset */ -#define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /*!< LFXT status */ -/* CS_STAT[REFO_ON] Bits */ -#define CS_STAT_REFO_ON_OFS ( 7) /*!< REFO_ON Bit Offset */ -#define CS_STAT_REFO_ON ((uint32_t)0x00000080) /*!< REFO status */ -/* CS_STAT[ACLK_ON] Bits */ -#define CS_STAT_ACLK_ON_OFS (16) /*!< ACLK_ON Bit Offset */ -#define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /*!< ACLK system clock status */ -/* CS_STAT[MCLK_ON] Bits */ -#define CS_STAT_MCLK_ON_OFS (17) /*!< MCLK_ON Bit Offset */ -#define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /*!< MCLK system clock status */ -/* CS_STAT[HSMCLK_ON] Bits */ -#define CS_STAT_HSMCLK_ON_OFS (18) /*!< HSMCLK_ON Bit Offset */ -#define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /*!< HSMCLK system clock status */ -/* CS_STAT[SMCLK_ON] Bits */ -#define CS_STAT_SMCLK_ON_OFS (19) /*!< SMCLK_ON Bit Offset */ -#define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /*!< SMCLK system clock status */ -/* CS_STAT[MODCLK_ON] Bits */ -#define CS_STAT_MODCLK_ON_OFS (20) /*!< MODCLK_ON Bit Offset */ -#define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /*!< MODCLK system clock status */ -/* CS_STAT[VLOCLK_ON] Bits */ -#define CS_STAT_VLOCLK_ON_OFS (21) /*!< VLOCLK_ON Bit Offset */ -#define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /*!< VLOCLK system clock status */ -/* CS_STAT[LFXTCLK_ON] Bits */ -#define CS_STAT_LFXTCLK_ON_OFS (22) /*!< LFXTCLK_ON Bit Offset */ -#define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /*!< LFXTCLK system clock status */ -/* CS_STAT[REFOCLK_ON] Bits */ -#define CS_STAT_REFOCLK_ON_OFS (23) /*!< REFOCLK_ON Bit Offset */ -#define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /*!< REFOCLK system clock status */ -/* CS_STAT[ACLK_READY] Bits */ -#define CS_STAT_ACLK_READY_OFS (24) /*!< ACLK_READY Bit Offset */ -#define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /*!< ACLK Ready status */ -/* CS_STAT[MCLK_READY] Bits */ -#define CS_STAT_MCLK_READY_OFS (25) /*!< MCLK_READY Bit Offset */ -#define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /*!< MCLK Ready status */ -/* CS_STAT[HSMCLK_READY] Bits */ -#define CS_STAT_HSMCLK_READY_OFS (26) /*!< HSMCLK_READY Bit Offset */ -#define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /*!< HSMCLK Ready status */ -/* CS_STAT[SMCLK_READY] Bits */ -#define CS_STAT_SMCLK_READY_OFS (27) /*!< SMCLK_READY Bit Offset */ -#define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /*!< SMCLK Ready status */ -/* CS_STAT[BCLK_READY] Bits */ -#define CS_STAT_BCLK_READY_OFS (28) /*!< BCLK_READY Bit Offset */ -#define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /*!< BCLK Ready status */ -/* CS_IE[LFXTIE] Bits */ -#define CS_IE_LFXTIE_OFS ( 0) /*!< LFXTIE Bit Offset */ -#define CS_IE_LFXTIE ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag interrupt enable */ -/* CS_IE[HFXTIE] Bits */ -#define CS_IE_HFXTIE_OFS ( 1) /*!< HFXTIE Bit Offset */ -#define CS_IE_HFXTIE ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag interrupt enable */ -/* CS_IE[DCOR_OPNIE] Bits */ -#define CS_IE_DCOR_OPNIE_OFS ( 6) /*!< DCOR_OPNIE Bit Offset */ -#define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag interrupt enable. */ -/* CS_IE[FCNTLFIE] Bits */ -#define CS_IE_FCNTLFIE_OFS ( 8) /*!< FCNTLFIE Bit Offset */ -#define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /*!< Start fault counter interrupt enable LFXT */ -/* CS_IE[FCNTHFIE] Bits */ -#define CS_IE_FCNTHFIE_OFS ( 9) /*!< FCNTHFIE Bit Offset */ -#define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /*!< Start fault counter interrupt enable HFXT */ -/* CS_IFG[LFXTIFG] Bits */ -#define CS_IFG_LFXTIFG_OFS ( 0) /*!< LFXTIFG Bit Offset */ -#define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag */ -/* CS_IFG[HFXTIFG] Bits */ -#define CS_IFG_HFXTIFG_OFS ( 1) /*!< HFXTIFG Bit Offset */ -#define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag */ -/* CS_IFG[DCOR_SHTIFG] Bits */ -#define CS_IFG_DCOR_SHTIFG_OFS ( 5) /*!< DCOR_SHTIFG Bit Offset */ -#define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /*!< DCO external resistor short circuit fault flag. */ -/* CS_IFG[DCOR_OPNIFG] Bits */ -#define CS_IFG_DCOR_OPNIFG_OFS ( 6) /*!< DCOR_OPNIFG Bit Offset */ -#define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag. */ -/* CS_IFG[FCNTLFIFG] Bits */ -#define CS_IFG_FCNTLFIFG_OFS ( 8) /*!< FCNTLFIFG Bit Offset */ -#define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter interrupt flag LFXT */ -/* CS_IFG[FCNTHFIFG] Bits */ -#define CS_IFG_FCNTHFIFG_OFS ( 9) /*!< FCNTHFIFG Bit Offset */ -#define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter interrupt flag HFXT */ -/* CS_CLRIFG[CLR_LFXTIFG] Bits */ -#define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /*!< CLR_LFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /*!< Clear LFXT oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_HFXTIFG] Bits */ -#define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /*!< CLR_HFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /*!< Clear HFXT oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /*!< CLR_DCOR_OPNIFG Bit Offset */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Clear DCO external resistor open circuit fault interrupt flag. */ -/* CS_CLRIFG[CLR_FCNTLFIFG] Bits */ -#define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /*!< CLR_FCNTLFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter clear interrupt flag LFXT */ -/* CS_CLRIFG[CLR_FCNTHFIFG] Bits */ -#define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /*!< CLR_FCNTHFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter clear interrupt flag HFXT */ -/* CS_SETIFG[SET_LFXTIFG] Bits */ -#define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /*!< SET_LFXTIFG Bit Offset */ -#define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /*!< Set LFXT oscillator fault interrupt flag */ -/* CS_SETIFG[SET_HFXTIFG] Bits */ -#define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /*!< SET_HFXTIFG Bit Offset */ -#define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /*!< Set HFXT oscillator fault interrupt flag */ -/* CS_SETIFG[SET_DCOR_OPNIFG] Bits */ -#define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /*!< SET_DCOR_OPNIFG Bit Offset */ -#define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Set DCO external resistor open circuit fault interrupt flag. */ -/* CS_SETIFG[SET_FCNTHFIFG] Bits */ -#define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /*!< SET_FCNTHFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter set interrupt flag HFXT */ -/* CS_SETIFG[SET_FCNTLFIFG] Bits */ -#define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /*!< SET_FCNTLFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter set interrupt flag LFXT */ -/* CS_DCOERCAL0[DCO_TCCAL] Bits */ -#define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /*!< DCO_TCCAL Bit Offset */ -#define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /*!< DCO_TCCAL Bit Mask */ -/* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /*!< DCO_FCAL_RSEL04 Bit Offset */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /*!< DCO_FCAL_RSEL04 Bit Mask */ -/* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /*!< DCO_FCAL_RSEL5 Bit Offset */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /*!< DCO_FCAL_RSEL5 Bit Mask */ -/* Pre-defined bitfield values */ -#define CS_KEY_VAL ((uint32_t)0x0000695A) /*!< CS control key value */ - -/****************************************************************************** -* DIO Bits -******************************************************************************/ -/* DIO_IV[IV] Bits */ -#define DIO_PORT_IV_OFS ( 0) /*!< DIO Port IV Bit Offset */ -#define DIO_PORT_IV_MASK ((uint16_t)0x001F) /*!< DIO Port IV Bit Mask */ -#define DIO_PORT_IV0 ((uint16_t)0x0001) /*!< DIO Port IV Bit 0 */ -#define DIO_PORT_IV1 ((uint16_t)0x0002) /*!< DIO Port IV Bit 1 */ -#define DIO_PORT_IV2 ((uint16_t)0x0004) /*!< DIO Port IV Bit 2 */ -#define DIO_PORT_IV3 ((uint16_t)0x0008) /*!< DIO Port IV Bit 3 */ -#define DIO_PORT_IV4 ((uint16_t)0x0010) /*!< DIO Port IV Bit 4 */ -#define DIO_PORT_IV_0 ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV_2 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ - /* Priority: Highest */ -#define DIO_PORT_IV_4 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV_6 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV_8 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV_10 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV_12 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV_14 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV_16 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ - /* Priority: Lowest */ -#define DIO_PORT_IV__NONE ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ - /* Priority: Highest */ -#define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ - /* Priority: Lowest */ - - -/****************************************************************************** -* DMA Bits -******************************************************************************/ -/* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /*!< NUM_DMA_CHANNELS Bit Offset */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /*!< NUM_DMA_CHANNELS Bit Mask */ -/* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /*!< NUM_SRC_PER_CHANNEL Bit Offset */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /*!< NUM_SRC_PER_CHANNEL Bit Mask */ -/* DMA_SW_CHTRIG[CH0] Bits */ -#define DMA_SW_CHTRIG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /*!< Write 1, triggers DMA_CHANNEL0 */ -/* DMA_SW_CHTRIG[CH1] Bits */ -#define DMA_SW_CHTRIG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /*!< Write 1, triggers DMA_CHANNEL1 */ -/* DMA_SW_CHTRIG[CH2] Bits */ -#define DMA_SW_CHTRIG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /*!< Write 1, triggers DMA_CHANNEL2 */ -/* DMA_SW_CHTRIG[CH3] Bits */ -#define DMA_SW_CHTRIG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /*!< Write 1, triggers DMA_CHANNEL3 */ -/* DMA_SW_CHTRIG[CH4] Bits */ -#define DMA_SW_CHTRIG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /*!< Write 1, triggers DMA_CHANNEL4 */ -/* DMA_SW_CHTRIG[CH5] Bits */ -#define DMA_SW_CHTRIG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /*!< Write 1, triggers DMA_CHANNEL5 */ -/* DMA_SW_CHTRIG[CH6] Bits */ -#define DMA_SW_CHTRIG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /*!< Write 1, triggers DMA_CHANNEL6 */ -/* DMA_SW_CHTRIG[CH7] Bits */ -#define DMA_SW_CHTRIG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /*!< Write 1, triggers DMA_CHANNEL7 */ -/* DMA_SW_CHTRIG[CH8] Bits */ -#define DMA_SW_CHTRIG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /*!< Write 1, triggers DMA_CHANNEL8 */ -/* DMA_SW_CHTRIG[CH9] Bits */ -#define DMA_SW_CHTRIG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /*!< Write 1, triggers DMA_CHANNEL9 */ -/* DMA_SW_CHTRIG[CH10] Bits */ -#define DMA_SW_CHTRIG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /*!< Write 1, triggers DMA_CHANNEL10 */ -/* DMA_SW_CHTRIG[CH11] Bits */ -#define DMA_SW_CHTRIG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /*!< Write 1, triggers DMA_CHANNEL11 */ -/* DMA_SW_CHTRIG[CH12] Bits */ -#define DMA_SW_CHTRIG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /*!< Write 1, triggers DMA_CHANNEL12 */ -/* DMA_SW_CHTRIG[CH13] Bits */ -#define DMA_SW_CHTRIG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /*!< Write 1, triggers DMA_CHANNEL13 */ -/* DMA_SW_CHTRIG[CH14] Bits */ -#define DMA_SW_CHTRIG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /*!< Write 1, triggers DMA_CHANNEL14 */ -/* DMA_SW_CHTRIG[CH15] Bits */ -#define DMA_SW_CHTRIG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /*!< Write 1, triggers DMA_CHANNEL15 */ -/* DMA_SW_CHTRIG[CH16] Bits */ -#define DMA_SW_CHTRIG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /*!< Write 1, triggers DMA_CHANNEL16 */ -/* DMA_SW_CHTRIG[CH17] Bits */ -#define DMA_SW_CHTRIG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /*!< Write 1, triggers DMA_CHANNEL17 */ -/* DMA_SW_CHTRIG[CH18] Bits */ -#define DMA_SW_CHTRIG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /*!< Write 1, triggers DMA_CHANNEL18 */ -/* DMA_SW_CHTRIG[CH19] Bits */ -#define DMA_SW_CHTRIG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /*!< Write 1, triggers DMA_CHANNEL19 */ -/* DMA_SW_CHTRIG[CH20] Bits */ -#define DMA_SW_CHTRIG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /*!< Write 1, triggers DMA_CHANNEL20 */ -/* DMA_SW_CHTRIG[CH21] Bits */ -#define DMA_SW_CHTRIG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /*!< Write 1, triggers DMA_CHANNEL21 */ -/* DMA_SW_CHTRIG[CH22] Bits */ -#define DMA_SW_CHTRIG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /*!< Write 1, triggers DMA_CHANNEL22 */ -/* DMA_SW_CHTRIG[CH23] Bits */ -#define DMA_SW_CHTRIG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /*!< Write 1, triggers DMA_CHANNEL23 */ -/* DMA_SW_CHTRIG[CH24] Bits */ -#define DMA_SW_CHTRIG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /*!< Write 1, triggers DMA_CHANNEL24 */ -/* DMA_SW_CHTRIG[CH25] Bits */ -#define DMA_SW_CHTRIG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /*!< Write 1, triggers DMA_CHANNEL25 */ -/* DMA_SW_CHTRIG[CH26] Bits */ -#define DMA_SW_CHTRIG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /*!< Write 1, triggers DMA_CHANNEL26 */ -/* DMA_SW_CHTRIG[CH27] Bits */ -#define DMA_SW_CHTRIG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /*!< Write 1, triggers DMA_CHANNEL27 */ -/* DMA_SW_CHTRIG[CH28] Bits */ -#define DMA_SW_CHTRIG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /*!< Write 1, triggers DMA_CHANNEL28 */ -/* DMA_SW_CHTRIG[CH29] Bits */ -#define DMA_SW_CHTRIG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /*!< Write 1, triggers DMA_CHANNEL29 */ -/* DMA_SW_CHTRIG[CH30] Bits */ -#define DMA_SW_CHTRIG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /*!< Write 1, triggers DMA_CHANNEL30 */ -/* DMA_SW_CHTRIG[CH31] Bits */ -#define DMA_SW_CHTRIG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /*!< Write 1, triggers DMA_CHANNEL31 */ -/* DMA_CHN_SRCCFG[DMA_SRC] Bits */ -#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /*!< DMA_SRC Bit Offset */ -#define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /*!< DMA_SRC Bit Mask */ -/* DMA_INT1_SRCCFG[INT_SRC] Bits */ -#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT1_SRCCFG[EN] Bits */ -#define DMA_INT1_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT1 mapping */ -/* DMA_INT2_SRCCFG[INT_SRC] Bits */ -#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT2_SRCCFG[EN] Bits */ -#define DMA_INT2_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT2 mapping */ -/* DMA_INT3_SRCCFG[INT_SRC] Bits */ -#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT3_SRCCFG[EN] Bits */ -#define DMA_INT3_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT3 mapping */ -/* DMA_INT0_SRCFLG[CH0] Bits */ -#define DMA_INT0_SRCFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /*!< Channel 0 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH1] Bits */ -#define DMA_INT0_SRCFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /*!< Channel 1 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH2] Bits */ -#define DMA_INT0_SRCFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /*!< Channel 2 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH3] Bits */ -#define DMA_INT0_SRCFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /*!< Channel 3 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH4] Bits */ -#define DMA_INT0_SRCFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /*!< Channel 4 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH5] Bits */ -#define DMA_INT0_SRCFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /*!< Channel 5 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH6] Bits */ -#define DMA_INT0_SRCFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /*!< Channel 6 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH7] Bits */ -#define DMA_INT0_SRCFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /*!< Channel 7 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH8] Bits */ -#define DMA_INT0_SRCFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /*!< Channel 8 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH9] Bits */ -#define DMA_INT0_SRCFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /*!< Channel 9 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH10] Bits */ -#define DMA_INT0_SRCFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /*!< Channel 10 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH11] Bits */ -#define DMA_INT0_SRCFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /*!< Channel 11 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH12] Bits */ -#define DMA_INT0_SRCFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /*!< Channel 12 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH13] Bits */ -#define DMA_INT0_SRCFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /*!< Channel 13 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH14] Bits */ -#define DMA_INT0_SRCFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /*!< Channel 14 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH15] Bits */ -#define DMA_INT0_SRCFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /*!< Channel 15 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH16] Bits */ -#define DMA_INT0_SRCFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /*!< Channel 16 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH17] Bits */ -#define DMA_INT0_SRCFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /*!< Channel 17 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH18] Bits */ -#define DMA_INT0_SRCFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /*!< Channel 18 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH19] Bits */ -#define DMA_INT0_SRCFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /*!< Channel 19 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH20] Bits */ -#define DMA_INT0_SRCFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /*!< Channel 20 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH21] Bits */ -#define DMA_INT0_SRCFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /*!< Channel 21 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH22] Bits */ -#define DMA_INT0_SRCFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /*!< Channel 22 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH23] Bits */ -#define DMA_INT0_SRCFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /*!< Channel 23 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH24] Bits */ -#define DMA_INT0_SRCFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /*!< Channel 24 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH25] Bits */ -#define DMA_INT0_SRCFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /*!< Channel 25 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH26] Bits */ -#define DMA_INT0_SRCFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /*!< Channel 26 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH27] Bits */ -#define DMA_INT0_SRCFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /*!< Channel 27 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH28] Bits */ -#define DMA_INT0_SRCFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /*!< Channel 28 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH29] Bits */ -#define DMA_INT0_SRCFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /*!< Channel 29 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH30] Bits */ -#define DMA_INT0_SRCFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /*!< Channel 30 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH31] Bits */ -#define DMA_INT0_SRCFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /*!< Channel 31 was the source of DMA_INT0 */ -/* DMA_INT0_CLRFLG[CH0] Bits */ -#define DMA_INT0_CLRFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH1] Bits */ -#define DMA_INT0_CLRFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH2] Bits */ -#define DMA_INT0_CLRFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH3] Bits */ -#define DMA_INT0_CLRFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH4] Bits */ -#define DMA_INT0_CLRFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH5] Bits */ -#define DMA_INT0_CLRFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH6] Bits */ -#define DMA_INT0_CLRFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH7] Bits */ -#define DMA_INT0_CLRFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH8] Bits */ -#define DMA_INT0_CLRFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH9] Bits */ -#define DMA_INT0_CLRFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH10] Bits */ -#define DMA_INT0_CLRFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH11] Bits */ -#define DMA_INT0_CLRFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH12] Bits */ -#define DMA_INT0_CLRFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH13] Bits */ -#define DMA_INT0_CLRFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH14] Bits */ -#define DMA_INT0_CLRFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH15] Bits */ -#define DMA_INT0_CLRFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH16] Bits */ -#define DMA_INT0_CLRFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH17] Bits */ -#define DMA_INT0_CLRFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH18] Bits */ -#define DMA_INT0_CLRFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH19] Bits */ -#define DMA_INT0_CLRFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH20] Bits */ -#define DMA_INT0_CLRFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH21] Bits */ -#define DMA_INT0_CLRFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH22] Bits */ -#define DMA_INT0_CLRFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH23] Bits */ -#define DMA_INT0_CLRFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH24] Bits */ -#define DMA_INT0_CLRFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH25] Bits */ -#define DMA_INT0_CLRFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH26] Bits */ -#define DMA_INT0_CLRFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH27] Bits */ -#define DMA_INT0_CLRFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH28] Bits */ -#define DMA_INT0_CLRFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH29] Bits */ -#define DMA_INT0_CLRFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH30] Bits */ -#define DMA_INT0_CLRFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH31] Bits */ -#define DMA_INT0_CLRFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_STAT[MASTEN] Bits */ -#define DMA_STAT_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_STAT_MASTEN ((uint32_t)0x00000001) -/* DMA_STAT[STATE] Bits */ -#define DMA_STAT_STATE_OFS ( 4) /*!< STATE Bit Offset */ -#define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /*!< STATE Bit Mask */ -#define DMA_STAT_STATE0 ((uint32_t)0x00000010) /*!< STATE Bit 0 */ -#define DMA_STAT_STATE1 ((uint32_t)0x00000020) /*!< STATE Bit 1 */ -#define DMA_STAT_STATE2 ((uint32_t)0x00000040) /*!< STATE Bit 2 */ -#define DMA_STAT_STATE3 ((uint32_t)0x00000080) /*!< STATE Bit 3 */ -#define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /*!< idle */ -#define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /*!< reading channel controller data */ -#define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /*!< reading source data end pointer */ -#define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /*!< reading destination data end pointer */ -#define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /*!< reading source data */ -#define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /*!< writing destination data */ -#define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /*!< waiting for DMA request to clear */ -#define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /*!< writing channel controller data */ -#define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /*!< stalled */ -#define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /*!< done */ -#define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /*!< peripheral scatter-gather transition */ -#define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /*!< Reserved */ -#define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /*!< Reserved */ -#define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /*!< Reserved */ -#define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /*!< Reserved */ -#define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /*!< Reserved */ -/* DMA_STAT[DMACHANS] Bits */ -#define DMA_STAT_DMACHANS_OFS (16) /*!< DMACHANS Bit Offset */ -#define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /*!< DMACHANS Bit Mask */ -#define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /*!< DMACHANS Bit 0 */ -#define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /*!< DMACHANS Bit 1 */ -#define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /*!< DMACHANS Bit 2 */ -#define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /*!< DMACHANS Bit 3 */ -#define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /*!< DMACHANS Bit 4 */ -#define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /*!< Controller configured to use 1 DMA channel */ -#define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /*!< Controller configured to use 2 DMA channels */ -#define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /*!< Controller configured to use 31 DMA channels */ -#define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /*!< Controller configured to use 32 DMA channels */ -/* DMA_STAT[TESTSTAT] Bits */ -#define DMA_STAT_TESTSTAT_OFS (28) /*!< TESTSTAT Bit Offset */ -#define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /*!< TESTSTAT Bit Mask */ -#define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /*!< TESTSTAT Bit 0 */ -#define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /*!< TESTSTAT Bit 1 */ -#define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /*!< TESTSTAT Bit 2 */ -#define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /*!< TESTSTAT Bit 3 */ -#define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /*!< Controller does not include the integration test logic */ -#define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /*!< Controller includes the integration test logic */ -/* DMA_CFG[MASTEN] Bits */ -#define DMA_CFG_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_CFG_MASTEN ((uint32_t)0x00000001) -/* DMA_CFG[CHPROTCTRL] Bits */ -#define DMA_CFG_CHPROTCTRL_OFS ( 5) /*!< CHPROTCTRL Bit Offset */ -#define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /*!< CHPROTCTRL Bit Mask */ -/* DMA_CTLBASE[ADDR] Bits */ -#define DMA_CTLBASE_ADDR_OFS ( 5) /*!< ADDR Bit Offset */ -#define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /*!< ADDR Bit Mask */ -/* DMA_ERRCLR[ERRCLR] Bits */ -#define DMA_ERRCLR_ERRCLR_OFS ( 0) /*!< ERRCLR Bit Offset */ -#define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) -/* DMA channel definitions and memory structure alignment */ -#define __MCU_NUM_DMA_CHANNELS__ 8 -#define DMA_CHANNEL_CONTROL_STRUCT_SIZE 0x10 -#define DMA_CONTROL_MEMORY_ALIGNMENT (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE) - -/* UDMA_STAT Control Bits */ -#define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /*!< Available uDMA Channels Minus 1 */ -#define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /*!< Control State Machine Status */ -#define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /*!< Idle */ -#define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /*!< Reading channel controller data */ -#define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /*!< Reading source end pointer */ -#define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /*!< Reading destination end pointer */ -#define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /*!< Reading source data */ -#define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /*!< Writing destination data */ -#define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /*!< Waiting for uDMA request to clear */ -#define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /*!< Writing channel controller data */ -#define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /*!< Stalled */ -#define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /*!< Done */ -#define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /*!< Undefined */ -#define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /*!< Master Enable Status */ -#define UDMA_STAT_DMACHANS_S (16) - -/* UDMA_CFG Control Bits */ -#define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /*!< Controller Master Enable */ - -/* UDMA_CTLBASE Control Bits */ -#define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /*!< Channel Control Base Address */ -#define UDMA_CTLBASE_ADDR_S (10) - -/* UDMA_ALTBASE Control Bits */ -#define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Alternate Channel Address Pointer */ -#define UDMA_ALTBASE_ADDR_S ( 0) - -/* UDMA_WAITSTAT Control Bits */ -#define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Wait Status */ - -/* UDMA_SWREQ Control Bits */ -#define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Software Request */ - -/* UDMA_USEBURSTSET Control Bits */ -#define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Set */ - -/* UDMA_USEBURSTCLR Control Bits */ -#define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Clear */ - -/* UDMA_REQMASKSET Control Bits */ -#define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Set */ - -/* UDMA_REQMASKCLR Control Bits */ -#define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Clear */ - -/* UDMA_ENASET Control Bits */ -#define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Enable Set */ - -/* UDMA_ENACLR Control Bits */ -#define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Clear Channel [n] Enable Clear */ - -/* UDMA_ALTSET Control Bits */ -#define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Set */ - -/* UDMA_ALTCLR Control Bits */ -#define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Clear */ - -/* UDMA_PRIOSET Control Bits */ -#define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Set */ - -/* UDMA_PRIOCLR Control Bits */ -#define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Clear */ - -/* UDMA_ERRCLR Control Bits */ -#define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /*!< uDMA Bus Error Status */ - -/* UDMA_CHASGN Control Bits */ -#define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Assignment Select */ -#define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /*!< Use the primary channel assignment */ -#define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /*!< Use the secondary channel assignment */ - -/* Micro Direct Memory Access (uDMA) offsets */ -#define UDMA_O_SRCENDP ((uint32_t)0x00000000) /*!< DMA Channel Source Address End Pointer */ -#define UDMA_O_DSTENDP ((uint32_t)0x00000004) /*!< DMA Channel Destination Address End Pointer */ -#define UDMA_O_CHCTL ((uint32_t)0x00000008) /*!< DMA Channel Control Word */ - -/* UDMA_O_SRCENDP Control Bits */ -#define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Source Address End Pointer */ -#define UDMA_SRCENDP_ADDR_S ( 0) - -/* UDMA_O_DSTENDP Control Bits */ -#define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Destination Address End Pointer */ -#define UDMA_DSTENDP_ADDR_S ( 0) - -/* UDMA_O_CHCTL Control Bits */ -#define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /*!< Destination Address Increment */ -#define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /*!< Word */ -#define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /*!< No increment */ -#define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /*!< Destination Data Size */ -#define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /*!< Source Address Increment */ -#define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /*!< No increment */ -#define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /*!< Source Data Size */ -#define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /*!< Word */ -#define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /*!< Arbitration Size */ -#define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /*!< 1 Transfer */ -#define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /*!< 2 Transfers */ -#define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /*!< 4 Transfers */ -#define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /*!< 8 Transfers */ -#define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /*!< 16 Transfers */ -#define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /*!< 32 Transfers */ -#define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /*!< 64 Transfers */ -#define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /*!< 128 Transfers */ -#define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /*!< 256 Transfers */ -#define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /*!< 512 Transfers */ -#define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /*!< 1024 Transfers */ -#define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /*!< Transfer Size (minus 1) */ -#define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /*!< Next Useburst */ -#define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /*!< uDMA Transfer Mode */ -#define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /*!< Stop */ -#define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /*!< Basic */ -#define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /*!< Auto-Request */ -#define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /*!< Ping-Pong */ -#define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /*!< Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /*!< Alternate Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /*!< Peripheral Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /*!< Alternate Peripheral Scatter-Gather */ - -#define UDMA_CHCTL_XFERSIZE_S ( 4) - - -/****************************************************************************** -* DWT Bits -******************************************************************************/ - - -/****************************************************************************** -* EUSCI_A Bits -******************************************************************************/ -/* EUSCI_A_CTLW0[SWRST] Bits */ -#define EUSCI_A_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -/* EUSCI_A_CTLW0[TXBRK] Bits */ -#define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /*!< UCTXBRK Bit Offset */ -#define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /*!< Transmit break */ -/* EUSCI_A_CTLW0[TXADDR] Bits */ -#define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /*!< UCTXADDR Bit Offset */ -#define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /*!< Transmit address */ -/* EUSCI_A_CTLW0[DORM] Bits */ -#define EUSCI_A_CTLW0_DORM_OFS ( 3) /*!< UCDORM Bit Offset */ -#define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /*!< Dormant */ -/* EUSCI_A_CTLW0[BRKIE] Bits */ -#define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /*!< UCBRKIE Bit Offset */ -#define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /*!< Receive break character interrupt enable */ -/* EUSCI_A_CTLW0[RXEIE] Bits */ -#define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /*!< UCRXEIE Bit Offset */ -#define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /*!< Receive erroneous-character interrupt enable */ -/* EUSCI_A_CTLW0[SSEL] Bits */ -#define EUSCI_A_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -/* EUSCI_A_CTLW0[SYNC] Bits */ -#define EUSCI_A_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -/* EUSCI_A_CTLW0[MODE] Bits */ -#define EUSCI_A_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< UART mode */ -#define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< Idle-line multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< Address-bit multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< UART mode with automatic baud-rate detection */ -/* EUSCI_A_CTLW0[SPB] Bits */ -#define EUSCI_A_CTLW0_SPB_OFS (11) /*!< UCSPB Bit Offset */ -#define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /*!< Stop bit select */ -/* EUSCI_A_CTLW0[SEVENBIT] Bits */ -#define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -/* EUSCI_A_CTLW0[MSB] Bits */ -#define EUSCI_A_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -/* EUSCI_A_CTLW0[PAR] Bits */ -#define EUSCI_A_CTLW0_PAR_OFS (14) /*!< UCPAR Bit Offset */ -#define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /*!< Parity select */ -/* EUSCI_A_CTLW0[PEN] Bits */ -#define EUSCI_A_CTLW0_PEN_OFS (15) /*!< UCPEN Bit Offset */ -#define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /*!< Parity enable */ -/* EUSCI_A_CTLW0[STEM] Bits */ -#define EUSCI_A_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -/* EUSCI_A_CTLW0[MST] Bits */ -#define EUSCI_A_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -/* EUSCI_A_CTLW0[CKPL] Bits */ -#define EUSCI_A_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -/* EUSCI_A_CTLW0[CKPH] Bits */ -#define EUSCI_A_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -/* EUSCI_A_CTLW1[GLIT] Bits */ -#define EUSCI_A_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< Approximately 2 ns (equivalent of 1 delay element) */ -#define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< Approximately 50 ns */ -#define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< Approximately 100 ns */ -#define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< Approximately 200 ns */ -/* EUSCI_A_MCTLW[OS16] Bits */ -#define EUSCI_A_MCTLW_OS16_OFS ( 0) /*!< UCOS16 Bit Offset */ -#define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /*!< Oversampling mode enabled */ -/* EUSCI_A_MCTLW[BRF] Bits */ -#define EUSCI_A_MCTLW_BRF_OFS ( 4) /*!< UCBRF Bit Offset */ -#define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /*!< UCBRF Bit Mask */ -/* EUSCI_A_MCTLW[BRS] Bits */ -#define EUSCI_A_MCTLW_BRS_OFS ( 8) /*!< UCBRS Bit Offset */ -#define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /*!< UCBRS Bit Mask */ -/* EUSCI_A_STATW[BUSY] Bits */ -#define EUSCI_A_STATW_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -/* EUSCI_A_STATW[ADDR_IDLE] Bits */ -#define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /*!< UCADDR_UCIDLE Bit Offset */ -#define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /*!< Address received / Idle line detected */ -/* EUSCI_A_STATW[RXERR] Bits */ -#define EUSCI_A_STATW_RXERR_OFS ( 2) /*!< UCRXERR Bit Offset */ -#define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /*!< Receive error flag */ -/* EUSCI_A_STATW[BRK] Bits */ -#define EUSCI_A_STATW_BRK_OFS ( 3) /*!< UCBRK Bit Offset */ -#define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /*!< Break detect flag */ -/* EUSCI_A_STATW[PE] Bits */ -#define EUSCI_A_STATW_PE_OFS ( 4) /*!< UCPE Bit Offset */ -#define EUSCI_A_STATW_PE ((uint16_t)0x0010) -/* EUSCI_A_STATW[OE] Bits */ -#define EUSCI_A_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_A_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -/* EUSCI_A_STATW[FE] Bits */ -#define EUSCI_A_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_A_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -/* EUSCI_A_STATW[LISTEN] Bits */ -#define EUSCI_A_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -/* EUSCI_A_STATW[SPI_BUSY] Bits */ -#define EUSCI_A_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -/* EUSCI_A_RXBUF[RXBUF] Bits */ -#define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -/* EUSCI_A_TXBUF[TXBUF] Bits */ -#define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -/* EUSCI_A_ABCTL[ABDEN] Bits */ -#define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /*!< UCABDEN Bit Offset */ -#define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /*!< Automatic baud-rate detect enable */ -/* EUSCI_A_ABCTL[BTOE] Bits */ -#define EUSCI_A_ABCTL_BTOE_OFS ( 2) /*!< UCBTOE Bit Offset */ -#define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /*!< Break time out error */ -/* EUSCI_A_ABCTL[STOE] Bits */ -#define EUSCI_A_ABCTL_STOE_OFS ( 3) /*!< UCSTOE Bit Offset */ -#define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /*!< Synch field time out error */ -/* EUSCI_A_ABCTL[DELIM] Bits */ -#define EUSCI_A_ABCTL_DELIM_OFS ( 4) /*!< UCDELIM Bit Offset */ -#define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /*!< UCDELIM Bit Mask */ -#define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /*!< DELIM Bit 0 */ -#define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /*!< DELIM Bit 1 */ -#define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /*!< 1 bit time */ -#define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /*!< 2 bit times */ -#define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /*!< 3 bit times */ -#define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /*!< 4 bit times */ -/* EUSCI_A_IRCTL[IREN] Bits */ -#define EUSCI_A_IRCTL_IREN_OFS ( 0) /*!< UCIREN Bit Offset */ -#define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /*!< IrDA encoder/decoder enable */ -/* EUSCI_A_IRCTL[IRTXCLK] Bits */ -#define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /*!< UCIRTXCLK Bit Offset */ -#define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /*!< IrDA transmit pulse clock select */ -/* EUSCI_A_IRCTL[IRTXPL] Bits */ -#define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /*!< UCIRTXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /*!< UCIRTXPL Bit Mask */ -/* EUSCI_A_IRCTL[IRRXFE] Bits */ -#define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /*!< UCIRRXFE Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /*!< IrDA receive filter enabled */ -/* EUSCI_A_IRCTL[IRRXPL] Bits */ -#define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /*!< UCIRRXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /*!< IrDA receive input UCAxRXD polarity */ -/* EUSCI_A_IRCTL[IRRXFL] Bits */ -#define EUSCI_A_IRCTL_IRRXFL_OFS (10) /*!< UCIRRXFL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /*!< UCIRRXFL Bit Mask */ -/* EUSCI_A_IE[RXIE] Bits */ -#define EUSCI_A_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -/* EUSCI_A_IE[TXIE] Bits */ -#define EUSCI_A_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -/* EUSCI_A_IE[STTIE] Bits */ -#define EUSCI_A_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /*!< Start bit interrupt enable */ -/* EUSCI_A_IE[TXCPTIE] Bits */ -#define EUSCI_A_IE_TXCPTIE_OFS ( 3) /*!< UCTXCPTIE Bit Offset */ -#define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /*!< Transmit complete interrupt enable */ -/* EUSCI_A_IFG[RXIFG] Bits */ -#define EUSCI_A_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -/* EUSCI_A_IFG[TXIFG] Bits */ -#define EUSCI_A_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -/* EUSCI_A_IFG[STTIFG] Bits */ -#define EUSCI_A_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /*!< Start bit interrupt flag */ -/* EUSCI_A_IFG[TXCPTIFG] Bits */ -#define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /*!< UCTXCPTIFG Bit Offset */ -#define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /*!< Transmit ready interrupt enable */ -/* legacy definitions for backward compatibility to version 2100 */ -#define EUSCI_A__RXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_A__RXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_A__TXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_A__TXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ - - -/****************************************************************************** -* EUSCI_B Bits -******************************************************************************/ -/* EUSCI_B_CTLW0[SWRST] Bits */ -#define EUSCI_B_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -/* EUSCI_B_CTLW0[TXSTT] Bits */ -#define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /*!< UCTXSTT Bit Offset */ -#define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /*!< Transmit START condition in master mode */ -/* EUSCI_B_CTLW0[TXSTP] Bits */ -#define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /*!< UCTXSTP Bit Offset */ -#define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /*!< Transmit STOP condition in master mode */ -/* EUSCI_B_CTLW0[TXNACK] Bits */ -#define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /*!< UCTXNACK Bit Offset */ -#define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /*!< Transmit a NACK */ -/* EUSCI_B_CTLW0[TR] Bits */ -#define EUSCI_B_CTLW0_TR_OFS ( 4) /*!< UCTR Bit Offset */ -#define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /*!< Transmitter/receiver */ -/* EUSCI_B_CTLW0[TXACK] Bits */ -#define EUSCI_B_CTLW0_TXACK_OFS ( 5) /*!< UCTXACK Bit Offset */ -#define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /*!< Transmit ACK condition in slave mode */ -/* EUSCI_B_CTLW0[SSEL] Bits */ -#define EUSCI_B_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_B_CTLW0_UCSSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ -#define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -/* EUSCI_B_CTLW0[SYNC] Bits */ -#define EUSCI_B_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -/* EUSCI_B_CTLW0[MODE] Bits */ -#define EUSCI_B_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< 3-pin SPI */ -#define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< 4-pin SPI (master or slave enabled if STE = 1) */ -#define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< 4-pin SPI (master or slave enabled if STE = 0) */ -#define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< I2C mode */ -/* EUSCI_B_CTLW0[MST] Bits */ -#define EUSCI_B_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -/* EUSCI_B_CTLW0[MM] Bits */ -#define EUSCI_B_CTLW0_MM_OFS (13) /*!< UCMM Bit Offset */ -#define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /*!< Multi-master environment select */ -/* EUSCI_B_CTLW0[SLA10] Bits */ -#define EUSCI_B_CTLW0_SLA10_OFS (14) /*!< UCSLA10 Bit Offset */ -#define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /*!< Slave addressing mode select */ -/* EUSCI_B_CTLW0[A10] Bits */ -#define EUSCI_B_CTLW0_A10_OFS (15) /*!< UCA10 Bit Offset */ -#define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /*!< Own addressing mode select */ -/* EUSCI_B_CTLW0[STEM] Bits */ -#define EUSCI_B_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -/* EUSCI_B_CTLW0[SEVENBIT] Bits */ -#define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -/* EUSCI_B_CTLW0[MSB] Bits */ -#define EUSCI_B_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -/* EUSCI_B_CTLW0[CKPL] Bits */ -#define EUSCI_B_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -/* EUSCI_B_CTLW0[CKPH] Bits */ -#define EUSCI_B_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -/* EUSCI_B_CTLW1[GLIT] Bits */ -#define EUSCI_B_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< 50 ns */ -#define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< 25 ns */ -#define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< 12.5 ns */ -#define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< 6.25 ns */ -/* EUSCI_B_CTLW1[ASTP] Bits */ -#define EUSCI_B_CTLW1_ASTP_OFS ( 2) /*!< UCASTP Bit Offset */ -#define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /*!< UCASTP Bit Mask */ -#define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /*!< ASTP Bit 0 */ -#define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /*!< ASTP Bit 1 */ -#define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /*!< No automatic STOP generation. The STOP condition is generated after the user */ - /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ -#define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ - /* UCBxTBCNT */ -#define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /*!< A STOP condition is generated automatically after the byte counter value */ - /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ - /* threshold */ -/* EUSCI_B_CTLW1[SWACK] Bits */ -#define EUSCI_B_CTLW1_SWACK_OFS ( 4) /*!< UCSWACK Bit Offset */ -#define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /*!< SW or HW ACK control */ -/* EUSCI_B_CTLW1[STPNACK] Bits */ -#define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /*!< UCSTPNACK Bit Offset */ -#define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /*!< ACK all master bytes */ -/* EUSCI_B_CTLW1[CLTO] Bits */ -#define EUSCI_B_CTLW1_CLTO_OFS ( 6) /*!< UCCLTO Bit Offset */ -#define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /*!< UCCLTO Bit Mask */ -#define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /*!< CLTO Bit 0 */ -#define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /*!< CLTO Bit 1 */ -#define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /*!< Disable clock low timeout counter */ -#define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ -#define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ -#define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ -/* EUSCI_B_CTLW1[ETXINT] Bits */ -#define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /*!< UCETXINT Bit Offset */ -#define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /*!< Early UCTXIFG0 */ -/* EUSCI_B_STATW[BBUSY] Bits */ -#define EUSCI_B_STATW_BBUSY_OFS ( 4) /*!< UCBBUSY Bit Offset */ -#define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /*!< Bus busy */ -/* EUSCI_B_STATW[GC] Bits */ -#define EUSCI_B_STATW_GC_OFS ( 5) /*!< UCGC Bit Offset */ -#define EUSCI_B_STATW_GC ((uint16_t)0x0020) /*!< General call address received */ -/* EUSCI_B_STATW[SCLLOW] Bits */ -#define EUSCI_B_STATW_SCLLOW_OFS ( 6) /*!< UCSCLLOW Bit Offset */ -#define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /*!< SCL low */ -/* EUSCI_B_STATW[BCNT] Bits */ -#define EUSCI_B_STATW_BCNT_OFS ( 8) /*!< UCBCNT Bit Offset */ -#define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /*!< UCBCNT Bit Mask */ -/* EUSCI_B_STATW[SPI_BUSY] Bits */ -#define EUSCI_B_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_B_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_B busy */ -/* EUSCI_B_STATW[OE] Bits */ -#define EUSCI_B_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_B_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -/* EUSCI_B_STATW[FE] Bits */ -#define EUSCI_B_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_B_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -/* EUSCI_B_STATW[LISTEN] Bits */ -#define EUSCI_B_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -/* EUSCI_B_TBCNT[TBCNT] Bits */ -#define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /*!< UCTBCNT Bit Offset */ -#define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /*!< UCTBCNT Bit Mask */ -/* EUSCI_B_RXBUF[RXBUF] Bits */ -#define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -/* EUSCI_B_TXBUF[TXBUF] Bits */ -#define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -/* EUSCI_B_I2COA0[I2COA0] Bits */ -#define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /*!< I2COA0 Bit Offset */ -#define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /*!< I2COA0 Bit Mask */ -/* EUSCI_B_I2COA0[OAEN] Bits */ -#define EUSCI_B_I2COA0_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA0[GCEN] Bits */ -#define EUSCI_B_I2COA0_GCEN_OFS (15) /*!< UCGCEN Bit Offset */ -#define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /*!< General call response enable */ -/* EUSCI_B_I2COA1[I2COA1] Bits */ -#define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /*!< I2COA1 Bit Offset */ -#define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /*!< I2COA1 Bit Mask */ -/* EUSCI_B_I2COA1[OAEN] Bits */ -#define EUSCI_B_I2COA1_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA2[I2COA2] Bits */ -#define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /*!< I2COA2 Bit Offset */ -#define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /*!< I2COA2 Bit Mask */ -/* EUSCI_B_I2COA2[OAEN] Bits */ -#define EUSCI_B_I2COA2_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA3[I2COA3] Bits */ -#define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /*!< I2COA3 Bit Offset */ -#define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /*!< I2COA3 Bit Mask */ -/* EUSCI_B_I2COA3[OAEN] Bits */ -#define EUSCI_B_I2COA3_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_ADDRX[ADDRX] Bits */ -#define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /*!< ADDRX Bit Offset */ -#define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /*!< ADDRX Bit Mask */ -#define EUSCI_B_ADDRX_ADDRX0 ((uint16_t)0x0001) /*!< ADDRX Bit 0 */ -#define EUSCI_B_ADDRX_ADDRX1 ((uint16_t)0x0002) /*!< ADDRX Bit 1 */ -#define EUSCI_B_ADDRX_ADDRX2 ((uint16_t)0x0004) /*!< ADDRX Bit 2 */ -#define EUSCI_B_ADDRX_ADDRX3 ((uint16_t)0x0008) /*!< ADDRX Bit 3 */ -#define EUSCI_B_ADDRX_ADDRX4 ((uint16_t)0x0010) /*!< ADDRX Bit 4 */ -#define EUSCI_B_ADDRX_ADDRX5 ((uint16_t)0x0020) /*!< ADDRX Bit 5 */ -#define EUSCI_B_ADDRX_ADDRX6 ((uint16_t)0x0040) /*!< ADDRX Bit 6 */ -#define EUSCI_B_ADDRX_ADDRX7 ((uint16_t)0x0080) /*!< ADDRX Bit 7 */ -#define EUSCI_B_ADDRX_ADDRX8 ((uint16_t)0x0100) /*!< ADDRX Bit 8 */ -#define EUSCI_B_ADDRX_ADDRX9 ((uint16_t)0x0200) /*!< ADDRX Bit 9 */ -/* EUSCI_B_ADDMASK[ADDMASK] Bits */ -#define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /*!< ADDMASK Bit Offset */ -#define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /*!< ADDMASK Bit Mask */ -/* EUSCI_B_I2CSA[I2CSA] Bits */ -#define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /*!< I2CSA Bit Offset */ -#define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /*!< I2CSA Bit Mask */ -/* EUSCI_B_IE[RXIE0] Bits */ -#define EUSCI_B_IE_RXIE0_OFS ( 0) /*!< UCRXIE0 Bit Offset */ -#define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /*!< Receive interrupt enable 0 */ -/* EUSCI_B_IE[TXIE0] Bits */ -#define EUSCI_B_IE_TXIE0_OFS ( 1) /*!< UCTXIE0 Bit Offset */ -#define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /*!< Transmit interrupt enable 0 */ -/* EUSCI_B_IE[STTIE] Bits */ -#define EUSCI_B_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /*!< START condition interrupt enable */ -/* EUSCI_B_IE[STPIE] Bits */ -#define EUSCI_B_IE_STPIE_OFS ( 3) /*!< UCSTPIE Bit Offset */ -#define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /*!< STOP condition interrupt enable */ -/* EUSCI_B_IE[ALIE] Bits */ -#define EUSCI_B_IE_ALIE_OFS ( 4) /*!< UCALIE Bit Offset */ -#define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /*!< Arbitration lost interrupt enable */ -/* EUSCI_B_IE[NACKIE] Bits */ -#define EUSCI_B_IE_NACKIE_OFS ( 5) /*!< UCNACKIE Bit Offset */ -#define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /*!< Not-acknowledge interrupt enable */ -/* EUSCI_B_IE[BCNTIE] Bits */ -#define EUSCI_B_IE_BCNTIE_OFS ( 6) /*!< UCBCNTIE Bit Offset */ -#define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /*!< Byte counter interrupt enable */ -/* EUSCI_B_IE[CLTOIE] Bits */ -#define EUSCI_B_IE_CLTOIE_OFS ( 7) /*!< UCCLTOIE Bit Offset */ -#define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /*!< Clock low timeout interrupt enable */ -/* EUSCI_B_IE[RXIE1] Bits */ -#define EUSCI_B_IE_RXIE1_OFS ( 8) /*!< UCRXIE1 Bit Offset */ -#define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /*!< Receive interrupt enable 1 */ -/* EUSCI_B_IE[TXIE1] Bits */ -#define EUSCI_B_IE_TXIE1_OFS ( 9) /*!< UCTXIE1 Bit Offset */ -#define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /*!< Transmit interrupt enable 1 */ -/* EUSCI_B_IE[RXIE2] Bits */ -#define EUSCI_B_IE_RXIE2_OFS (10) /*!< UCRXIE2 Bit Offset */ -#define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /*!< Receive interrupt enable 2 */ -/* EUSCI_B_IE[TXIE2] Bits */ -#define EUSCI_B_IE_TXIE2_OFS (11) /*!< UCTXIE2 Bit Offset */ -#define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /*!< Transmit interrupt enable 2 */ -/* EUSCI_B_IE[RXIE3] Bits */ -#define EUSCI_B_IE_RXIE3_OFS (12) /*!< UCRXIE3 Bit Offset */ -#define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /*!< Receive interrupt enable 3 */ -/* EUSCI_B_IE[TXIE3] Bits */ -#define EUSCI_B_IE_TXIE3_OFS (13) /*!< UCTXIE3 Bit Offset */ -#define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /*!< Transmit interrupt enable 3 */ -/* EUSCI_B_IE[BIT9IE] Bits */ -#define EUSCI_B_IE_BIT9IE_OFS (14) /*!< UCBIT9IE Bit Offset */ -#define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /*!< Bit position 9 interrupt enable */ -/* EUSCI_B_IE[RXIE] Bits */ -#define EUSCI_B_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_B_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -/* EUSCI_B_IE[TXIE] Bits */ -#define EUSCI_B_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_B_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -/* EUSCI_B_IFG[RXIFG0] Bits */ -#define EUSCI_B_IFG_RXIFG0_OFS ( 0) /*!< UCRXIFG0 Bit Offset */ -#define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /*!< eUSCI_B receive interrupt flag 0 */ -/* EUSCI_B_IFG[TXIFG0] Bits */ -#define EUSCI_B_IFG_TXIFG0_OFS ( 1) /*!< UCTXIFG0 Bit Offset */ -#define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /*!< eUSCI_B transmit interrupt flag 0 */ -/* EUSCI_B_IFG[STTIFG] Bits */ -#define EUSCI_B_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /*!< START condition interrupt flag */ -/* EUSCI_B_IFG[STPIFG] Bits */ -#define EUSCI_B_IFG_STPIFG_OFS ( 3) /*!< UCSTPIFG Bit Offset */ -#define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /*!< STOP condition interrupt flag */ -/* EUSCI_B_IFG[ALIFG] Bits */ -#define EUSCI_B_IFG_ALIFG_OFS ( 4) /*!< UCALIFG Bit Offset */ -#define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /*!< Arbitration lost interrupt flag */ -/* EUSCI_B_IFG[NACKIFG] Bits */ -#define EUSCI_B_IFG_NACKIFG_OFS ( 5) /*!< UCNACKIFG Bit Offset */ -#define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /*!< Not-acknowledge received interrupt flag */ -/* EUSCI_B_IFG[BCNTIFG] Bits */ -#define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /*!< UCBCNTIFG Bit Offset */ -#define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /*!< Byte counter interrupt flag */ -/* EUSCI_B_IFG[CLTOIFG] Bits */ -#define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /*!< UCCLTOIFG Bit Offset */ -#define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /*!< Clock low timeout interrupt flag */ -/* EUSCI_B_IFG[RXIFG1] Bits */ -#define EUSCI_B_IFG_RXIFG1_OFS ( 8) /*!< UCRXIFG1 Bit Offset */ -#define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /*!< eUSCI_B receive interrupt flag 1 */ -/* EUSCI_B_IFG[TXIFG1] Bits */ -#define EUSCI_B_IFG_TXIFG1_OFS ( 9) /*!< UCTXIFG1 Bit Offset */ -#define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /*!< eUSCI_B transmit interrupt flag 1 */ -/* EUSCI_B_IFG[RXIFG2] Bits */ -#define EUSCI_B_IFG_RXIFG2_OFS (10) /*!< UCRXIFG2 Bit Offset */ -#define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /*!< eUSCI_B receive interrupt flag 2 */ -/* EUSCI_B_IFG[TXIFG2] Bits */ -#define EUSCI_B_IFG_TXIFG2_OFS (11) /*!< UCTXIFG2 Bit Offset */ -#define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /*!< eUSCI_B transmit interrupt flag 2 */ -/* EUSCI_B_IFG[RXIFG3] Bits */ -#define EUSCI_B_IFG_RXIFG3_OFS (12) /*!< UCRXIFG3 Bit Offset */ -#define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /*!< eUSCI_B receive interrupt flag 3 */ -/* EUSCI_B_IFG[TXIFG3] Bits */ -#define EUSCI_B_IFG_TXIFG3_OFS (13) /*!< UCTXIFG3 Bit Offset */ -#define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /*!< eUSCI_B transmit interrupt flag 3 */ -/* EUSCI_B_IFG[BIT9IFG] Bits */ -#define EUSCI_B_IFG_BIT9IFG_OFS (14) /*!< UCBIT9IFG Bit Offset */ -#define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /*!< Bit position 9 interrupt flag */ -/* EUSCI_B_IFG[RXIFG] Bits */ -#define EUSCI_B_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -/* EUSCI_B_IFG[TXIFG] Bits */ -#define EUSCI_B_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -/* legacy definitions for backward compatibility to version 2100 */ -#define EUSCI_B__RXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_B__RXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_B__TXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_B__TXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ - - -/****************************************************************************** -* FLCTL Bits -******************************************************************************/ -/* FLCTL_POWER_STAT[PSTAT] Bits */ -#define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /*!< PSTAT Bit Offset */ -#define FLCTL_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /*!< PSTAT Bit Mask */ -#define FLCTL_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /*!< PSTAT Bit 0 */ -#define FLCTL_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /*!< PSTAT Bit 1 */ -#define FLCTL_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /*!< PSTAT Bit 2 */ -#define FLCTL_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /*!< Flash IP in power-down mode */ -#define FLCTL_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /*!< Flash IP Vdd domain power-up in progress */ -#define FLCTL_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */ -#define FLCTL_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /*!< Flash IP SAFE_LV check in progress */ -#define FLCTL_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /*!< Flash IP Active */ -#define FLCTL_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */ -#define FLCTL_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /*!< Flash IP in Standby mode */ -#define FLCTL_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /*!< Flash IP in Current mirror boost state */ -/* FLCTL_POWER_STAT[LDOSTAT] Bits */ -#define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /*!< LDOSTAT Bit Offset */ -#define FLCTL_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /*!< PSS FLDO GOOD status */ -/* FLCTL_POWER_STAT[VREFSTAT] Bits */ -#define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /*!< VREFSTAT Bit Offset */ -#define FLCTL_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /*!< PSS VREF stable status */ -/* FLCTL_POWER_STAT[IREFSTAT] Bits */ -#define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /*!< IREFSTAT Bit Offset */ -#define FLCTL_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /*!< PSS IREF stable status */ -/* FLCTL_POWER_STAT[TRIMSTAT] Bits */ -#define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /*!< TRIMSTAT Bit Offset */ -#define FLCTL_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /*!< PSS trim done status */ -/* FLCTL_POWER_STAT[RD_2T] Bits */ -#define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /*!< RD_2T Bit Offset */ -#define FLCTL_POWER_STAT_RD_2T ((uint32_t)0x00000080) /*!< Indicates if Flash is being accessed in 2T mode */ -/* FLCTL_BANK0_RDCTL[RD_MODE] Bits */ -#define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -/* FLCTL_BANK0_RDCTL[BUFI] Bits */ -#define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -/* FLCTL_BANK0_RDCTL[BUFD] Bits */ -#define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -/* FLCTL_BANK0_RDCTL[WAIT] Bits */ -#define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -/* FLCTL_BANK0_RDCTL[RD_MODE_STATUS] Bits */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -/* FLCTL_BANK1_RDCTL[RD_MODE] Bits */ -#define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -/* FLCTL_BANK1_RDCTL[BUFI] Bits */ -#define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -/* FLCTL_BANK1_RDCTL[BUFD] Bits */ -#define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -/* FLCTL_BANK1_RDCTL[RD_MODE_STATUS] Bits */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -/* FLCTL_BANK1_RDCTL[WAIT] Bits */ -#define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -/* FLCTL_RDBRST_CTLSTAT[START] Bits */ -#define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of burst/compare operation */ -/* FLCTL_RDBRST_CTLSTAT[MEM_TYPE] Bits */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /*!< MEM_TYPE Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /*!< MEM_TYPE Bit Mask */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /*!< MEM_TYPE Bit 0 */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /*!< MEM_TYPE Bit 1 */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -/* FLCTL_RDBRST_CTLSTAT[STOP_FAIL] Bits */ -#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /*!< STOP_FAIL Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /*!< Terminate burst/compare operation */ -/* FLCTL_RDBRST_CTLSTAT[DATA_CMP] Bits */ -#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /*!< DATA_CMP Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /*!< Data pattern used for comparison against memory read data */ -/* FLCTL_RDBRST_CTLSTAT[TEST_EN] Bits */ -#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /*!< TEST_EN Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /*!< Enable comparison against test data compare registers */ -/* FLCTL_RDBRST_CTLSTAT[BRST_STAT] Bits */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /*!< BRST_STAT Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /*!< BRST_STAT Bit Mask */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /*!< BRST_STAT Bit 0 */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /*!< BRST_STAT Bit 1 */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /*!< Idle */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /*!< Burst/Compare START bit written, but operation pending */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /*!< Burst/Compare in progress */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /*!< Burst complete (status of completed burst remains in this state unless */ - /* explicitly cleared by SW) */ -/* FLCTL_RDBRST_CTLSTAT[CMP_ERR] Bits */ -#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /*!< CMP_ERR Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /*!< Burst/Compare Operation encountered atleast one data */ -/* FLCTL_RDBRST_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /*!< Burst/Compare Operation was terminated due to access to */ -/* FLCTL_RDBRST_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 19-16 of this register */ -/* FLCTL_RDBRST_STARTADDR[START_ADDRESS] Bits */ -#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< START_ADDRESS Bit Mask */ -/* FLCTL_RDBRST_LEN[BURST_LENGTH] Bits */ -#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /*!< BURST_LENGTH Bit Offset */ -#define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /*!< BURST_LENGTH Bit Mask */ -/* FLCTL_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */ -#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /*!< FAIL_ADDRESS Bit Offset */ -#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< FAIL_ADDRESS Bit Mask */ -/* FLCTL_RDBRST_FAILCNT[FAIL_COUNT] Bits */ -#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /*!< FAIL_COUNT Bit Offset */ -#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /*!< FAIL_COUNT Bit Mask */ -/* FLCTL_PRG_CTLSTAT[ENABLE] Bits */ -#define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /*!< ENABLE Bit Offset */ -#define FLCTL_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /*!< Master control for all word program operations */ -/* FLCTL_PRG_CTLSTAT[MODE] Bits */ -#define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Write mode */ -/* FLCTL_PRG_CTLSTAT[VER_PRE] Bits */ -#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /*!< VER_PRE Bit Offset */ -#define FLCTL_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /*!< Controls automatic pre program verify operations */ -/* FLCTL_PRG_CTLSTAT[VER_PST] Bits */ -#define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /*!< VER_PST Bit Offset */ -#define FLCTL_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /*!< Controls automatic post program verify operations */ -/* FLCTL_PRG_CTLSTAT[STATUS] Bits */ -#define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Single word program operation triggered, but pending */ -#define FLCTL_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Single word program in progress */ -#define FLCTL_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Reserved (Idle) */ -/* FLCTL_PRG_CTLSTAT[BNK_ACT] Bits */ -#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /*!< BNK_ACT Bit Offset */ -#define FLCTL_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /*!< Bank active */ -/* FLCTL_PRGBRST_CTLSTAT[START] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Trigger start of burst program operation */ -/* FLCTL_PRGBRST_CTLSTAT[TYPE] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /*!< TYPE Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /*!< TYPE Bit Mask */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /*!< TYPE Bit 0 */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /*!< TYPE Bit 1 */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -/* FLCTL_PRGBRST_CTLSTAT[LEN] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /*!< LEN Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /*!< LEN Bit Mask */ -#define FLCTL_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /*!< LEN Bit 0 */ -#define FLCTL_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /*!< LEN Bit 1 */ -#define FLCTL_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /*!< LEN Bit 2 */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /*!< No burst operation */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /*!< 1 word burst of 128 bits, starting with address in the */ - /* FLCTL_PRGBRST_STARTADDR Register */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -/* FLCTL_PRGBRST_CTLSTAT[AUTO_PRE] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /*!< AUTO_PRE Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /*!< Auto-Verify operation before the Burst Program */ -/* FLCTL_PRGBRST_CTLSTAT[AUTO_PST] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /*!< AUTO_PST Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /*!< Auto-Verify operation after the Burst Program */ -/* FLCTL_PRGBRST_CTLSTAT[BURST_STATUS] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /*!< BURST_STATUS Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /*!< BURST_STATUS Bit Mask */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /*!< BURST_STATUS Bit 0 */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /*!< BURST_STATUS Bit 1 */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /*!< BURST_STATUS Bit 2 */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (Burst not active) */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /*!< Burst program started but pending */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /*!< Burst active, with 1st 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /*!< Burst active, with 2nd 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /*!< Burst active, with 3rd 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /*!< Burst active, with 4th 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /*!< Reserved (Idle) */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /*!< Burst Complete (status of completed burst remains in this state unless */ - /* explicitly cleared by SW) */ -/* FLCTL_PRGBRST_CTLSTAT[PRE_ERR] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /*!< PRE_ERR Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /*!< Burst Operation encountered preprogram auto-verify errors */ -/* FLCTL_PRGBRST_CTLSTAT[PST_ERR] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /*!< PST_ERR Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /*!< Burst Operation encountered postprogram auto-verify errors */ -/* FLCTL_PRGBRST_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /*!< Burst Operation was terminated due to attempted program of reserved memory */ -/* FLCTL_PRGBRST_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 21-16 of this register */ -/* FLCTL_PRGBRST_STARTADDR[START_ADDRESS] Bits */ -#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< START_ADDRESS Bit Mask */ -/* FLCTL_ERASE_CTLSTAT[START] Bits */ -#define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of Erase operation */ -/* FLCTL_ERASE_CTLSTAT[MODE] Bits */ -#define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Erase mode selected by application */ -/* FLCTL_ERASE_CTLSTAT[TYPE] Bits */ -#define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /*!< TYPE Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /*!< TYPE Bit Mask */ -#define FLCTL_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /*!< TYPE Bit 0 */ -#define FLCTL_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /*!< TYPE Bit 1 */ -#define FLCTL_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /*!< Information Memory */ -#define FLCTL_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /*!< Reserved */ -#define FLCTL_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /*!< Engineering Memory */ -/* FLCTL_ERASE_CTLSTAT[STATUS] Bits */ -#define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Erase operation triggered to START but pending */ -#define FLCTL_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Erase operation in progress */ -#define FLCTL_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Erase operation completed (status of completed erase remains in this state */ - /* unless explicitly cleared by SW) */ -/* FLCTL_ERASE_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /*!< Erase Operation was terminated due to attempted erase of reserved memory */ - /* address */ -/* FLCTL_ERASE_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /*!< CLR_STAT Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /*!< Clear status bits 18-16 of this register */ -/* FLCTL_ERASE_SECTADDR[SECT_ADDRESS] Bits */ -#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /*!< SECT_ADDRESS Bit Offset */ -#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< SECT_ADDRESS Bit Mask */ -/* FLCTL_BANK0_INFO_WEPROT[PROT0] Bits */ -#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_BANK0_INFO_WEPROT[PROT1] Bits */ -#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT0] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT1] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT2] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT3] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT4] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT5] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT6] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT7] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT8] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT9] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT10] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT11] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT12] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT13] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT14] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT15] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT16] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT17] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT18] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT19] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT20] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT21] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT22] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT23] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT24] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT25] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT26] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT27] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT28] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT29] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT30] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT31] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -/* FLCTL_BANK1_INFO_WEPROT[PROT0] Bits */ -#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -/* FLCTL_BANK1_INFO_WEPROT[PROT1] Bits */ -#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT0] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT1] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT2] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT3] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT4] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT5] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT6] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT7] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT8] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT9] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT10] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT11] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT12] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT13] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT14] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT15] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT16] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT17] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT18] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT19] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT20] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT21] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT22] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT23] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT24] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT25] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT26] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT27] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT28] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT29] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT30] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT31] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase operations */ -/* FLCTL_BMRK_CTLSTAT[I_BMRK] Bits */ -#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /*!< I_BMRK Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001) -/* FLCTL_BMRK_CTLSTAT[D_BMRK] Bits */ -#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /*!< D_BMRK Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002) -/* FLCTL_BMRK_CTLSTAT[CMP_EN] Bits */ -#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /*!< CMP_EN Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004) -/* FLCTL_BMRK_CTLSTAT[CMP_SEL] Bits */ -#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /*!< CMP_SEL Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008) -/* FLCTL_IFG[RDBRST] Bits */ -#define FLCTL_IFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_IFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_IFG[AVPRE] Bits */ -#define FLCTL_IFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_IFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_IFG[AVPST] Bits */ -#define FLCTL_IFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_IFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_IFG[PRG] Bits */ -#define FLCTL_IFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_IFG_PRG ((uint32_t)0x00000008) -/* FLCTL_IFG[PRGB] Bits */ -#define FLCTL_IFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_IFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_IFG[ERASE] Bits */ -#define FLCTL_IFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_IFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_IFG[BMRK] Bits */ -#define FLCTL_IFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_IFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_IFG[PRG_ERR] Bits */ -#define FLCTL_IFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_IFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_IE[RDBRST] Bits */ -#define FLCTL_IE_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_IE_RDBRST ((uint32_t)0x00000001) -/* FLCTL_IE[AVPRE] Bits */ -#define FLCTL_IE_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_IE_AVPRE ((uint32_t)0x00000002) -/* FLCTL_IE[AVPST] Bits */ -#define FLCTL_IE_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_IE_AVPST ((uint32_t)0x00000004) -/* FLCTL_IE[PRG] Bits */ -#define FLCTL_IE_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_IE_PRG ((uint32_t)0x00000008) -/* FLCTL_IE[PRGB] Bits */ -#define FLCTL_IE_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_IE_PRGB ((uint32_t)0x00000010) -/* FLCTL_IE[ERASE] Bits */ -#define FLCTL_IE_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_IE_ERASE ((uint32_t)0x00000020) -/* FLCTL_IE[BMRK] Bits */ -#define FLCTL_IE_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_IE_BMRK ((uint32_t)0x00000100) -/* FLCTL_IE[PRG_ERR] Bits */ -#define FLCTL_IE_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_IE_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_CLRIFG[RDBRST] Bits */ -#define FLCTL_CLRIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_CLRIFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_CLRIFG[AVPRE] Bits */ -#define FLCTL_CLRIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_CLRIFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_CLRIFG[AVPST] Bits */ -#define FLCTL_CLRIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_CLRIFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_CLRIFG[PRG] Bits */ -#define FLCTL_CLRIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_CLRIFG_PRG ((uint32_t)0x00000008) -/* FLCTL_CLRIFG[PRGB] Bits */ -#define FLCTL_CLRIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_CLRIFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_CLRIFG[ERASE] Bits */ -#define FLCTL_CLRIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_CLRIFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_CLRIFG[BMRK] Bits */ -#define FLCTL_CLRIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_CLRIFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_CLRIFG[PRG_ERR] Bits */ -#define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_CLRIFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_SETIFG[RDBRST] Bits */ -#define FLCTL_SETIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_SETIFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_SETIFG[AVPRE] Bits */ -#define FLCTL_SETIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_SETIFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_SETIFG[AVPST] Bits */ -#define FLCTL_SETIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_SETIFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_SETIFG[PRG] Bits */ -#define FLCTL_SETIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_SETIFG_PRG ((uint32_t)0x00000008) -/* FLCTL_SETIFG[PRGB] Bits */ -#define FLCTL_SETIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_SETIFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_SETIFG[ERASE] Bits */ -#define FLCTL_SETIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_SETIFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_SETIFG[BMRK] Bits */ -#define FLCTL_SETIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_SETIFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_SETIFG[PRG_ERR] Bits */ -#define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_SETIFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_READ_TIMCTL[SETUP] Bits */ -#define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_READ_TIMCTL[IREF_BOOST1] Bits */ -#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /*!< IREF_BOOST1 Bit Offset */ -#define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /*!< IREF_BOOST1 Bit Mask */ -/* FLCTL_READ_TIMCTL[SETUP_LONG] Bits */ -#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /*!< SETUP_LONG Bit Offset */ -#define FLCTL_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /*!< SETUP_LONG Bit Mask */ -/* FLCTL_READMARGIN_TIMCTL[SETUP] Bits */ -#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_PRGVER_TIMCTL[SETUP] Bits */ -#define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_PRGVER_TIMCTL[ACTIVE] Bits */ -#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /*!< ACTIVE Bit Mask */ -/* FLCTL_PRGVER_TIMCTL[HOLD] Bits */ -#define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /*!< HOLD Bit Offset */ -#define FLCTL_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /*!< HOLD Bit Mask */ -/* FLCTL_ERSVER_TIMCTL[SETUP] Bits */ -#define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_LKGVER_TIMCTL[SETUP] Bits */ -#define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_PROGRAM_TIMCTL[SETUP] Bits */ -#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_PROGRAM_TIMCTL[ACTIVE] Bits */ -#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_PROGRAM_TIMCTL[HOLD] Bits */ -#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -/* FLCTL_ERASE_TIMCTL[SETUP] Bits */ -#define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_ERASE_TIMCTL[ACTIVE] Bits */ -#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_ERASE_TIMCTL[HOLD] Bits */ -#define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -/* FLCTL_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /*!< BOOST_ACTIVE Bit Offset */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /*!< BOOST_ACTIVE Bit Mask */ -/* FLCTL_MASSERASE_TIMCTL[BOOST_HOLD] Bits */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /*!< BOOST_HOLD Bit Offset */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /*!< BOOST_HOLD Bit Mask */ -/* FLCTL_BURSTPRG_TIMCTL[ACTIVE] Bits */ -#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ - -/****************************************************************************** -* FL_BOOTOVER_MAILBOX Bits -******************************************************************************/ - -/****************************************************************************** -* FPB Bits -******************************************************************************/ - - -/****************************************************************************** -* FPU Bits -******************************************************************************/ - - -/****************************************************************************** -* ITM Bits -******************************************************************************/ - - -/****************************************************************************** -* MPU Bits -******************************************************************************/ - -/* Pre-defined bitfield values */ - -/* MPU_RASR_SIZE Bitfield Bits */ -#define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /*!< 32B */ -#define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /*!< 64B */ -#define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /*!< 128B */ -#define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /*!< 256B */ -#define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /*!< 512B */ -#define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /*!< 1KB */ -#define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /*!< 2KB */ -#define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /*!< 4KB */ -#define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /*!< 8KB */ -#define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /*!< 16KB */ -#define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /*!< 32KB */ -#define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /*!< 64KB */ -#define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /*!< 128KB */ -#define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /*!< 256KB */ -#define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /*!< 512KB */ -#define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /*!< 1MB */ -#define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /*!< 2MB */ -#define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /*!< 4MB */ -#define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /*!< 8MB */ -#define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /*!< 16MB */ -#define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /*!< 32MB */ -#define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /*!< 64MB */ -#define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /*!< 128MB */ -#define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /*!< 256MB */ -#define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /*!< 512MB */ -#define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /*!< 1GB */ -#define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /*!< 2GB */ -#define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /*!< 4GB */ - -/* MPU_RASR_AP Bitfield Bits */ -#define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /*!< Privileged permissions: No access. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /*!< Privileged permissions: Read-write. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /*!< Privileged permissions: Read-write. User permissions: Read-only. */ -#define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /*!< Privileged permissions: Read-write. User permissions: Read-write. */ -#define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /*!< Privileged permissions: Read-only. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /*!< Privileged permissions: Read-only. User permissions: Read-only. */ - -/* MPU_RASR_XN Bitfield Bits */ -#define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /*!< Instruction access enabled */ -#define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /*!< Instruction access disabled */ - - -/****************************************************************************** -* NVIC Bits -******************************************************************************/ - -/* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */ -#define NVIC_IPR0_PRI_0_OFS ( 0) /*!< PRI_0 Offset */ -#define NVIC_IPR0_PRI_0_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */ -#define NVIC_IPR0_PRI_1_OFS ( 8) /*!< PRI_1 Offset */ -#define NVIC_IPR0_PRI_1_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */ -#define NVIC_IPR0_PRI_2_OFS (16) /*!< PRI_2 Offset */ -#define NVIC_IPR0_PRI_2_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */ -#define NVIC_IPR0_PRI_3_OFS (24) /*!< PRI_3 Offset */ -#define NVIC_IPR0_PRI_3_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */ -#define NVIC_IPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define NVIC_IPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */ -#define NVIC_IPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define NVIC_IPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */ -#define NVIC_IPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define NVIC_IPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */ -#define NVIC_IPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define NVIC_IPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */ -#define NVIC_IPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define NVIC_IPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */ -#define NVIC_IPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define NVIC_IPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */ -#define NVIC_IPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define NVIC_IPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */ -#define NVIC_IPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define NVIC_IPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */ -#define NVIC_IPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define NVIC_IPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */ -#define NVIC_IPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define NVIC_IPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */ -#define NVIC_IPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define NVIC_IPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */ -#define NVIC_IPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define NVIC_IPR3_PRI_15_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */ -#define NVIC_IPR4_PRI_16_OFS ( 0) /*!< PRI_16 Offset */ -#define NVIC_IPR4_PRI_16_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */ -#define NVIC_IPR4_PRI_17_OFS ( 8) /*!< PRI_17 Offset */ -#define NVIC_IPR4_PRI_17_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */ -#define NVIC_IPR4_PRI_18_OFS (16) /*!< PRI_18 Offset */ -#define NVIC_IPR4_PRI_18_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */ -#define NVIC_IPR4_PRI_19_OFS (24) /*!< PRI_19 Offset */ -#define NVIC_IPR4_PRI_19_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */ -#define NVIC_IPR5_PRI_20_OFS ( 0) /*!< PRI_20 Offset */ -#define NVIC_IPR5_PRI_20_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */ -#define NVIC_IPR5_PRI_21_OFS ( 8) /*!< PRI_21 Offset */ -#define NVIC_IPR5_PRI_21_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */ -#define NVIC_IPR5_PRI_22_OFS (16) /*!< PRI_22 Offset */ -#define NVIC_IPR5_PRI_22_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */ -#define NVIC_IPR5_PRI_23_OFS (24) /*!< PRI_23 Offset */ -#define NVIC_IPR5_PRI_23_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */ -#define NVIC_IPR6_PRI_24_OFS ( 0) /*!< PRI_24 Offset */ -#define NVIC_IPR6_PRI_24_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */ -#define NVIC_IPR6_PRI_25_OFS ( 8) /*!< PRI_25 Offset */ -#define NVIC_IPR6_PRI_25_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */ -#define NVIC_IPR6_PRI_26_OFS (16) /*!< PRI_26 Offset */ -#define NVIC_IPR6_PRI_26_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */ -#define NVIC_IPR6_PRI_27_OFS (24) /*!< PRI_27 Offset */ -#define NVIC_IPR6_PRI_27_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */ -#define NVIC_IPR7_PRI_28_OFS ( 0) /*!< PRI_28 Offset */ -#define NVIC_IPR7_PRI_28_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */ -#define NVIC_IPR7_PRI_29_OFS ( 8) /*!< PRI_29 Offset */ -#define NVIC_IPR7_PRI_29_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */ -#define NVIC_IPR7_PRI_30_OFS (16) /*!< PRI_30 Offset */ -#define NVIC_IPR7_PRI_30_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */ -#define NVIC_IPR7_PRI_31_OFS (24) /*!< PRI_31 Offset */ -#define NVIC_IPR7_PRI_31_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */ -#define NVIC_IPR8_PRI_32_OFS ( 0) /*!< PRI_32 Offset */ -#define NVIC_IPR8_PRI_32_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */ -#define NVIC_IPR8_PRI_33_OFS ( 8) /*!< PRI_33 Offset */ -#define NVIC_IPR8_PRI_33_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */ -#define NVIC_IPR8_PRI_34_OFS (16) /*!< PRI_34 Offset */ -#define NVIC_IPR8_PRI_34_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */ -#define NVIC_IPR8_PRI_35_OFS (24) /*!< PRI_35 Offset */ -#define NVIC_IPR8_PRI_35_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */ -#define NVIC_IPR9_PRI_36_OFS ( 0) /*!< PRI_36 Offset */ -#define NVIC_IPR9_PRI_36_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */ -#define NVIC_IPR9_PRI_37_OFS ( 8) /*!< PRI_37 Offset */ -#define NVIC_IPR9_PRI_37_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */ -#define NVIC_IPR9_PRI_38_OFS (16) /*!< PRI_38 Offset */ -#define NVIC_IPR9_PRI_38_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */ -#define NVIC_IPR9_PRI_39_OFS (24) /*!< PRI_39 Offset */ -#define NVIC_IPR9_PRI_39_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */ -#define NVIC_IPR10_PRI_40_OFS ( 0) /*!< PRI_40 Offset */ -#define NVIC_IPR10_PRI_40_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */ -#define NVIC_IPR10_PRI_41_OFS ( 8) /*!< PRI_41 Offset */ -#define NVIC_IPR10_PRI_41_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */ -#define NVIC_IPR10_PRI_42_OFS (16) /*!< PRI_42 Offset */ -#define NVIC_IPR10_PRI_42_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */ -#define NVIC_IPR10_PRI_43_OFS (24) /*!< PRI_43 Offset */ -#define NVIC_IPR10_PRI_43_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */ -#define NVIC_IPR11_PRI_44_OFS ( 0) /*!< PRI_44 Offset */ -#define NVIC_IPR11_PRI_44_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */ -#define NVIC_IPR11_PRI_45_OFS ( 8) /*!< PRI_45 Offset */ -#define NVIC_IPR11_PRI_45_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */ -#define NVIC_IPR11_PRI_46_OFS (16) /*!< PRI_46 Offset */ -#define NVIC_IPR11_PRI_46_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */ -#define NVIC_IPR11_PRI_47_OFS (24) /*!< PRI_47 Offset */ -#define NVIC_IPR11_PRI_47_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */ -#define NVIC_IPR12_PRI_48_OFS ( 0) /*!< PRI_48 Offset */ -#define NVIC_IPR12_PRI_48_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */ -#define NVIC_IPR12_PRI_49_OFS ( 8) /*!< PRI_49 Offset */ -#define NVIC_IPR12_PRI_49_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */ -#define NVIC_IPR12_PRI_50_OFS (16) /*!< PRI_50 Offset */ -#define NVIC_IPR12_PRI_50_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */ -#define NVIC_IPR12_PRI_51_OFS (24) /*!< PRI_51 Offset */ -#define NVIC_IPR12_PRI_51_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */ -#define NVIC_IPR13_PRI_52_OFS ( 0) /*!< PRI_52 Offset */ -#define NVIC_IPR13_PRI_52_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */ -#define NVIC_IPR13_PRI_53_OFS ( 8) /*!< PRI_53 Offset */ -#define NVIC_IPR13_PRI_53_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */ -#define NVIC_IPR13_PRI_54_OFS (16) /*!< PRI_54 Offset */ -#define NVIC_IPR13_PRI_54_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */ -#define NVIC_IPR13_PRI_55_OFS (24) /*!< PRI_55 Offset */ -#define NVIC_IPR13_PRI_55_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */ -#define NVIC_IPR14_PRI_56_OFS ( 0) /*!< PRI_56 Offset */ -#define NVIC_IPR14_PRI_56_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */ -#define NVIC_IPR14_PRI_57_OFS ( 8) /*!< PRI_57 Offset */ -#define NVIC_IPR14_PRI_57_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */ -#define NVIC_IPR14_PRI_58_OFS (16) /*!< PRI_58 Offset */ -#define NVIC_IPR14_PRI_58_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */ -#define NVIC_IPR14_PRI_59_OFS (24) /*!< PRI_59 Offset */ -#define NVIC_IPR14_PRI_59_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */ -#define NVIC_IPR15_PRI_60_OFS ( 0) /*!< PRI_60 Offset */ -#define NVIC_IPR15_PRI_60_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */ -#define NVIC_IPR15_PRI_61_OFS ( 8) /*!< PRI_61 Offset */ -#define NVIC_IPR15_PRI_61_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */ -#define NVIC_IPR15_PRI_62_OFS (16) /*!< PRI_62 Offset */ -#define NVIC_IPR15_PRI_62_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */ -#define NVIC_IPR15_PRI_63_OFS (24) /*!< PRI_63 Offset */ -#define NVIC_IPR15_PRI_63_M ((uint32_t)0xff000000) /* */ - - -/****************************************************************************** -* PCM Bits -******************************************************************************/ -/* PCM_CTL0[AMR] Bits */ -#define PCM_CTL0_AMR_OFS ( 0) /*!< AMR Bit Offset */ -#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /*!< AMR Bit Mask */ -#define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /*!< AMR Bit 0 */ -#define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /*!< AMR Bit 1 */ -#define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /*!< AMR Bit 2 */ -#define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /*!< AMR Bit 3 */ -#define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -/* PCM_CTL0[LPMR] Bits */ -#define PCM_CTL0_LPMR_OFS ( 4) /*!< LPMR Bit Offset */ -#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /*!< LPMR Bit Mask */ -#define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /*!< LPMR Bit 0 */ -#define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /*!< LPMR Bit 1 */ -#define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /*!< LPMR Bit 2 */ -#define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /*!< LPMR Bit 3 */ -#define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ - /* entered. */ -#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -#define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ - /* entered. */ -#define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -/* PCM_CTL0[CPM] Bits */ -#define PCM_CTL0_CPM_OFS ( 8) /*!< CPM Bit Offset */ -#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /*!< CPM Bit Mask */ -#define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /*!< CPM Bit 0 */ -#define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /*!< CPM Bit 1 */ -#define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /*!< CPM Bit 2 */ -#define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /*!< CPM Bit 3 */ -#define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /*!< CPM Bit 4 */ -#define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /*!< CPM Bit 5 */ -#define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /*!< LPM3 */ -#define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /*!< LPM3 */ -/* PCM_CTL0[KEY] Bits */ -#define PCM_CTL0_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -/* PCM_CTL1[LOCKLPM5] Bits */ -#define PCM_CTL1_LOCKLPM5_OFS ( 0) /*!< LOCKLPM5 Bit Offset */ -#define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /*!< Lock LPM5 */ -/* PCM_CTL1[LOCKBKUP] Bits */ -#define PCM_CTL1_LOCKBKUP_OFS ( 1) /*!< LOCKBKUP Bit Offset */ -#define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /*!< Lock Backup */ -/* PCM_CTL1[FORCE_LPM_ENTRY] Bits */ -#define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /*!< FORCE_LPM_ENTRY Bit Offset */ -#define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /*!< Force LPM entry */ -/* PCM_CTL1[PMR_BUSY] Bits */ -#define PCM_CTL1_PMR_BUSY_OFS ( 8) /*!< PMR_BUSY Bit Offset */ -#define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /*!< Power mode request busy flag */ -/* PCM_CTL1[KEY] Bits */ -#define PCM_CTL1_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -/* PCM_IE[LPM_INVALID_TR_IE] Bits */ -#define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /*!< LPM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /*!< LPM invalid transition interrupt enable */ -/* PCM_IE[LPM_INVALID_CLK_IE] Bits */ -#define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /*!< LPM_INVALID_CLK_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /*!< LPM invalid clock interrupt enable */ -/* PCM_IE[AM_INVALID_TR_IE] Bits */ -#define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /*!< AM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /*!< Active mode invalid transition interrupt enable */ -/* PCM_IE[DCDC_ERROR_IE] Bits */ -#define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /*!< DCDC_ERROR_IE Bit Offset */ -#define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /*!< DC-DC error interrupt enable */ -/* PCM_IFG[LPM_INVALID_TR_IFG] Bits */ -#define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /*!< LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< LPM invalid transition flag */ -/* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */ -#define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< LPM invalid clock flag */ -/* PCM_IFG[AM_INVALID_TR_IFG] Bits */ -#define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /*!< AM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Active mode invalid transition flag */ -/* PCM_IFG[DCDC_ERROR_IFG] Bits */ -#define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /*!< DCDC_ERROR_IFG Bit Offset */ -#define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< DC-DC error flag */ -/* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< Clear LPM invalid transition flag */ -/* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< Clear LPM invalid clock flag */ -/* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /*!< CLR_AM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Clear active mode invalid transition flag */ -/* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /*!< CLR_DCDC_ERROR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< Clear DC-DC error flag */ -/* Pre-defined bitfield values */ -#define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ -#define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ - - -/****************************************************************************** -* PMAP Bits -******************************************************************************/ -/* PMAP_CTL[LOCKED] Bits */ -#define PMAP_CTL_LOCKED_OFS ( 0) /*!< PMAPLOCKED Bit Offset */ -#define PMAP_CTL_LOCKED ((uint16_t)0x0001) /*!< Port mapping lock bit */ -/* PMAP_CTL[PRECFG] Bits */ -#define PMAP_CTL_PRECFG_OFS ( 1) /*!< PMAPRECFG Bit Offset */ -#define PMAP_CTL_PRECFG ((uint16_t)0x0002) /*!< Port mapping reconfiguration control bit */ -/* Pre-defined bitfield values */ -#define PMAP_NONE 0 -#define PMAP_UCA0CLK 1 -#define PMAP_UCA0RXD 2 -#define PMAP_UCA0SOMI 2 -#define PMAP_UCA0TXD 3 -#define PMAP_UCA0SIMO 3 -#define PMAP_UCB0CLK 4 -#define PMAP_UCB0SDA 5 -#define PMAP_UCB0SIMO 5 -#define PMAP_UCB0SCL 6 -#define PMAP_UCB0SOMI 6 -#define PMAP_UCA1STE 7 -#define PMAP_UCA1CLK 8 -#define PMAP_UCA1RXD 9 -#define PMAP_UCA1SOMI 9 -#define PMAP_UCA1TXD 10 -#define PMAP_UCA1SIMO 10 -#define PMAP_UCA2STE 11 -#define PMAP_UCA2CLK 12 -#define PMAP_UCA2RXD 13 -#define PMAP_UCA2SOMI 13 -#define PMAP_UCA2TXD 14 -#define PMAP_UCA2SIMO 14 -#define PMAP_UCB2STE 15 -#define PMAP_UCB2CLK 16 -#define PMAP_UCB2SDA 17 -#define PMAP_UCB2SIMO 17 -#define PMAP_UCB2SCL 18 -#define PMAP_UCB2SOMI 18 -#define PMAP_TA0CCR0A 19 -#define PMAP_TA0CCR1A 20 -#define PMAP_TA0CCR2A 21 -#define PMAP_TA0CCR3A 22 -#define PMAP_TA0CCR4A 23 -#define PMAP_TA1CCR1A 24 -#define PMAP_TA1CCR2A 25 -#define PMAP_TA1CCR3A 26 -#define PMAP_TA1CCR4A 27 -#define PMAP_TA0CLK 28 -#define PMAP_CE0OUT 28 -#define PMAP_TA1CLK 29 -#define PMAP_CE1OUT 29 -#define PMAP_DMAE0 30 -#define PMAP_SMCLK 30 -#define PMAP_ANALOG 31 - -#define PMAP_KEYID_VAL ((uint16_t)0x2D52) /*!< Port Mapping Key */ - - -/****************************************************************************** -* PSS Bits -******************************************************************************/ -/* PSS_KEY[KEY] Bits */ -#define PSS_KEY_KEY_OFS ( 0) /*!< PSSKEY Bit Offset */ -#define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< PSSKEY Bit Mask */ -/* PSS_CTL0[SVSMHOFF] Bits */ -#define PSS_CTL0_SVSMHOFF_OFS ( 0) /*!< SVSMHOFF Bit Offset */ -#define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /*!< SVSM high-side off */ -/* PSS_CTL0[SVSMHLP] Bits */ -#define PSS_CTL0_SVSMHLP_OFS ( 1) /*!< SVSMHLP Bit Offset */ -#define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /*!< SVSM high-side low power normal performance mode */ -/* PSS_CTL0[SVSMHS] Bits */ -#define PSS_CTL0_SVSMHS_OFS ( 2) /*!< SVSMHS Bit Offset */ -#define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /*!< Supply supervisor or monitor selection for the high-side */ -/* PSS_CTL0[SVSMHTH] Bits */ -#define PSS_CTL0_SVSMHTH_OFS ( 3) /*!< SVSMHTH Bit Offset */ -#define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /*!< SVSMHTH Bit Mask */ -/* PSS_CTL0[SVMHOE] Bits */ -#define PSS_CTL0_SVMHOE_OFS ( 6) /*!< SVMHOE Bit Offset */ -#define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /*!< SVSM high-side output enable */ -/* PSS_CTL0[SVMHOUTPOLAL] Bits */ -#define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /*!< SVMHOUTPOLAL Bit Offset */ -#define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /*!< SVMHOUT pin polarity active low */ -/* PSS_CTL0[DCDC_FORCE] Bits */ -#define PSS_CTL0_DCDC_FORCE_OFS (10) /*!< DCDC_FORCE Bit Offset */ -#define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /*!< Force DC-DC regulator operation */ -/* PSS_CTL0[VCORETRAN] Bits */ -#define PSS_CTL0_VCORETRAN_OFS (12) /*!< VCORETRAN Bit Offset */ -#define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /*!< VCORETRAN Bit Mask */ -#define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /*!< VCORETRAN Bit 0 */ -#define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /*!< VCORETRAN Bit 1 */ -#define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -/* PSS_IE[SVSMHIE] Bits */ -#define PSS_IE_SVSMHIE_OFS ( 1) /*!< SVSMHIE Bit Offset */ -#define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /*!< High-side SVSM interrupt enable */ -/* PSS_IFG[SVSMHIFG] Bits */ -#define PSS_IFG_SVSMHIFG_OFS ( 1) /*!< SVSMHIFG Bit Offset */ -#define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /*!< High-side SVSM interrupt flag */ -/* PSS_CLRIFG[CLRSVSMHIFG] Bits */ -#define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /*!< CLRSVSMHIFG Bit Offset */ -#define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /*!< SVSMH clear interrupt flag */ -/* Pre-defined bitfield values */ -#define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /*!< PSS control key value */ - - -/****************************************************************************** -* REF_A Bits -******************************************************************************/ -/* REF_A_CTL0[ON] Bits */ -#define REF_A_CTL0_ON_OFS ( 0) /*!< REFON Bit Offset */ -#define REF_A_CTL0_ON ((uint16_t)0x0001) /*!< Reference enable */ -/* REF_A_CTL0[OUT] Bits */ -#define REF_A_CTL0_OUT_OFS ( 1) /*!< REFOUT Bit Offset */ -#define REF_A_CTL0_OUT ((uint16_t)0x0002) /*!< Reference output buffer */ -/* REF_A_CTL0[TCOFF] Bits */ -#define REF_A_CTL0_TCOFF_OFS ( 3) /*!< REFTCOFF Bit Offset */ -#define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /*!< Temperature sensor disabled */ -/* REF_A_CTL0[VSEL] Bits */ -#define REF_A_CTL0_VSEL_OFS ( 4) /*!< REFVSEL Bit Offset */ -#define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /*!< REFVSEL Bit Mask */ -#define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /*!< VSEL Bit 0 */ -#define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /*!< VSEL Bit 1 */ -#define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /*!< 1.2 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /*!< 1.45 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /*!< 2.5 V available when reference requested or REFON = 1 */ -/* REF_A_CTL0[GENOT] Bits */ -#define REF_A_CTL0_GENOT_OFS ( 6) /*!< REFGENOT Bit Offset */ -#define REF_A_CTL0_GENOT ((uint16_t)0x0040) /*!< Reference generator one-time trigger */ -/* REF_A_CTL0[BGOT] Bits */ -#define REF_A_CTL0_BGOT_OFS ( 7) /*!< REFBGOT Bit Offset */ -#define REF_A_CTL0_BGOT ((uint16_t)0x0080) /*!< Bandgap and bandgap buffer one-time trigger */ -/* REF_A_CTL0[GENACT] Bits */ -#define REF_A_CTL0_GENACT_OFS ( 8) /*!< REFGENACT Bit Offset */ -#define REF_A_CTL0_GENACT ((uint16_t)0x0100) /*!< Reference generator active */ -/* REF_A_CTL0[BGACT] Bits */ -#define REF_A_CTL0_BGACT_OFS ( 9) /*!< REFBGACT Bit Offset */ -#define REF_A_CTL0_BGACT ((uint16_t)0x0200) /*!< Reference bandgap active */ -/* REF_A_CTL0[GENBUSY] Bits */ -#define REF_A_CTL0_GENBUSY_OFS (10) /*!< REFGENBUSY Bit Offset */ -#define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /*!< Reference generator busy */ -/* REF_A_CTL0[BGMODE] Bits */ -#define REF_A_CTL0_BGMODE_OFS (11) /*!< BGMODE Bit Offset */ -#define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /*!< Bandgap mode */ -/* REF_A_CTL0[GENRDY] Bits */ -#define REF_A_CTL0_GENRDY_OFS (12) /*!< REFGENRDY Bit Offset */ -#define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /*!< Variable reference voltage ready status */ -/* REF_A_CTL0[BGRDY] Bits */ -#define REF_A_CTL0_BGRDY_OFS (13) /*!< REFBGRDY Bit Offset */ -#define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /*!< Buffered bandgap voltage ready status */ - -/****************************************************************************** -* RSTCTL Bits -******************************************************************************/ -/* RSTCTL_RESET_REQ[SOFT_REQ] Bits */ -#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /*!< SOFT_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /*!< Soft Reset request */ -/* RSTCTL_RESET_REQ[HARD_REQ] Bits */ -#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /*!< HARD_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /*!< Hard Reset request */ -/* RSTCTL_RESET_REQ[RSTKEY] Bits */ -#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /*!< RSTKEY Bit Offset */ -#define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /*!< RSTKEY Bit Mask */ -/* RSTCTL_HARDRESET_STAT[SRC0] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< Indicates that SRC0 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC1] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< Indicates that SRC1 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC2] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< Indicates that SRC2 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC3] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< Indicates that SRC3 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC4] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< Indicates that SRC4 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC5] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< Indicates that SRC5 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC6] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< Indicates that SRC6 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC7] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< Indicates that SRC7 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC8] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< Indicates that SRC8 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC9] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< Indicates that SRC9 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC10] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< Indicates that SRC10 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC11] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< Indicates that SRC11 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC12] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< Indicates that SRC12 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC13] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< Indicates that SRC13 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC14] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< Indicates that SRC14 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC15] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< Indicates that SRC15 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_CLR[SRC0] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC1] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC2] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC3] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC4] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC5] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC6] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC7] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC8] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC9] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC10] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC11] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC12] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC13] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC14] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC15] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */ -/* RSTCTL_HARDRESET_SET[SRC0] Bits */ -#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC1] Bits */ -#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC2] Bits */ -#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC3] Bits */ -#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC4] Bits */ -#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC5] Bits */ -#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC6] Bits */ -#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC7] Bits */ -#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC8] Bits */ -#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC9] Bits */ -#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC10] Bits */ -#define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC11] Bits */ -#define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC12] Bits */ -#define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC13] Bits */ -#define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC14] Bits */ -#define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC15] Bits */ -#define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_SOFTRESET_STAT[SRC0] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< If 1, indicates that SRC0 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC1] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< If 1, indicates that SRC1 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC2] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< If 1, indicates that SRC2 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC3] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< If 1, indicates that SRC3 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC4] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< If 1, indicates that SRC4 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC5] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< If 1, indicates that SRC5 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC6] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< If 1, indicates that SRC6 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC7] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< If 1, indicates that SRC7 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC8] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< If 1, indicates that SRC8 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC9] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< If 1, indicates that SRC9 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC10] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< If 1, indicates that SRC10 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC11] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< If 1, indicates that SRC11 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC12] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< If 1, indicates that SRC12 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC13] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< If 1, indicates that SRC13 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC14] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< If 1, indicates that SRC14 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC15] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< If 1, indicates that SRC15 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_CLR[SRC0] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC1] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC2] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC3] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC4] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC5] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC6] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC7] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC8] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC9] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC10] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC11] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC12] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC13] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC14] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC15] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_SET[SRC0] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC1] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC2] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC3] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC4] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC5] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC6] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC7] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC8] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC9] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC10] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC11] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC12] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC13] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC14] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC15] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_PSSRESET_STAT[SVSMH] Bits */ -#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /*!< SVSMH Bit Offset */ -#define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */ -/* RSTCTL_PSSRESET_STAT[BGREF] Bits */ -#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /*!< BGREF Bit Offset */ -#define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */ -/* RSTCTL_PSSRESET_STAT[VCCDET] Bits */ -#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /*!< VCCDET Bit Offset */ -#define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */ -/* RSTCTL_PSSRESET_CLR[CLR] Bits */ -#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */ -/* RSTCTL_PCMRESET_STAT[LPM35] Bits */ -#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /*!< LPM35 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */ -/* RSTCTL_PCMRESET_STAT[LPM45] Bits */ -#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /*!< LPM45 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */ -/* RSTCTL_PCMRESET_CLR[CLR] Bits */ -#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */ -/* RSTCTL_PINRESET_STAT[RSTNMI] Bits */ -#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /*!< RSTNMI Bit Offset */ -#define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /*!< POR was caused by RSTn/NMI pin based reset event */ -/* RSTCTL_PINRESET_CLR[CLR] Bits */ -#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */ -/* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /*!< Indicates if Reboot reset was caused by the SYSCTL module. */ -/* RSTCTL_REBOOTRESET_CLR[CLR] Bits */ -#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */ -/* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /*!< DCOR_SHT Bit Offset */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /*!< Indicates if POR was caused by DCO short circuit fault in the external */ - /* resistor mode */ -/* RSTCTL_CSRESET_CLR[CLR] Bits */ -#define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as */ - /* DCOR_SHTIFG flag in CSIFG register of clock system */ -/* Pre-defined bitfield values */ -#define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bits 1-0 */ - - -/****************************************************************************** -* RTC_C Bits -******************************************************************************/ -/* RTC_C_CTL0[RDYIFG] Bits */ -#define RTC_C_CTL0_RDYIFG_OFS ( 0) /*!< RTCRDYIFG Bit Offset */ -#define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /*!< Real-time clock ready interrupt flag */ -/* RTC_C_CTL0[AIFG] Bits */ -#define RTC_C_CTL0_AIFG_OFS ( 1) /*!< RTCAIFG Bit Offset */ -#define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /*!< Real-time clock alarm interrupt flag */ -/* RTC_C_CTL0[TEVIFG] Bits */ -#define RTC_C_CTL0_TEVIFG_OFS ( 2) /*!< RTCTEVIFG Bit Offset */ -#define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /*!< Real-time clock time event interrupt flag */ -/* RTC_C_CTL0[OFIFG] Bits */ -#define RTC_C_CTL0_OFIFG_OFS ( 3) /*!< RTCOFIFG Bit Offset */ -#define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /*!< 32-kHz crystal oscillator fault interrupt flag */ -/* RTC_C_CTL0[RDYIE] Bits */ -#define RTC_C_CTL0_RDYIE_OFS ( 4) /*!< RTCRDYIE Bit Offset */ -#define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /*!< Real-time clock ready interrupt enable */ -/* RTC_C_CTL0[AIE] Bits */ -#define RTC_C_CTL0_AIE_OFS ( 5) /*!< RTCAIE Bit Offset */ -#define RTC_C_CTL0_AIE ((uint16_t)0x0020) /*!< Real-time clock alarm interrupt enable */ -/* RTC_C_CTL0[TEVIE] Bits */ -#define RTC_C_CTL0_TEVIE_OFS ( 6) /*!< RTCTEVIE Bit Offset */ -#define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /*!< Real-time clock time event interrupt enable */ -/* RTC_C_CTL0[OFIE] Bits */ -#define RTC_C_CTL0_OFIE_OFS ( 7) /*!< RTCOFIE Bit Offset */ -#define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /*!< 32-kHz crystal oscillator fault interrupt enable */ -/* RTC_C_CTL0[KEY] Bits */ -#define RTC_C_CTL0_KEY_OFS ( 8) /*!< RTCKEY Bit Offset */ -#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /*!< RTCKEY Bit Mask */ -/* RTC_C_CTL13[TEV] Bits */ -#define RTC_C_CTL13_TEV_OFS ( 0) /*!< RTCTEV Bit Offset */ -#define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /*!< RTCTEV Bit Mask */ -#define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /*!< TEV Bit 0 */ -#define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /*!< TEV Bit 1 */ -#define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /*!< Minute changed */ -#define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /*!< Hour changed */ -#define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /*!< Every day at midnight (00:00) */ -#define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /*!< Every day at noon (12:00) */ -/* RTC_C_CTL13[SSEL] Bits */ -#define RTC_C_CTL13_SSEL_OFS ( 2) /*!< RTCSSEL Bit Offset */ -#define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /*!< RTCSSEL Bit Mask */ -#define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /*!< SSEL Bit 0 */ -#define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /*!< SSEL Bit 1 */ -#define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /*!< BCLK */ -#define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /*!< BCLK */ -/* RTC_C_CTL13[RDY] Bits */ -#define RTC_C_CTL13_RDY_OFS ( 4) /*!< RTCRDY Bit Offset */ -#define RTC_C_CTL13_RDY ((uint16_t)0x0010) /*!< Real-time clock ready */ -/* RTC_C_CTL13[MODE] Bits */ -#define RTC_C_CTL13_MODE_OFS ( 5) /*!< RTCMODE Bit Offset */ -#define RTC_C_CTL13_MODE ((uint16_t)0x0020) -/* RTC_C_CTL13[HOLD] Bits */ -#define RTC_C_CTL13_HOLD_OFS ( 6) /*!< RTCHOLD Bit Offset */ -#define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /*!< Real-time clock hold */ -/* RTC_C_CTL13[BCD] Bits */ -#define RTC_C_CTL13_BCD_OFS ( 7) /*!< RTCBCD Bit Offset */ -#define RTC_C_CTL13_BCD ((uint16_t)0x0080) /*!< Real-time clock BCD select */ -/* RTC_C_CTL13[CALF] Bits */ -#define RTC_C_CTL13_CALF_OFS ( 8) /*!< RTCCALF Bit Offset */ -#define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /*!< RTCCALF Bit Mask */ -#define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /*!< CALF Bit 0 */ -#define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /*!< CALF Bit 1 */ -#define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /*!< 1 Hz */ -#define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /*!< 1 Hz */ -/* RTC_C_OCAL[OCAL] Bits */ -#define RTC_C_OCAL_OCAL_OFS ( 0) /*!< RTCOCAL Bit Offset */ -#define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /*!< RTCOCAL Bit Mask */ -/* RTC_C_OCAL[OCALS] Bits */ -#define RTC_C_OCAL_OCALS_OFS (15) /*!< RTCOCALS Bit Offset */ -#define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /*!< Real-time clock offset error calibration sign */ -/* RTC_C_TCMP[TCMPx] Bits */ -#define RTC_C_TCMP_TCMPX_OFS ( 0) /*!< RTCTCMP Bit Offset */ -#define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /*!< RTCTCMP Bit Mask */ -/* RTC_C_TCMP[TCOK] Bits */ -#define RTC_C_TCMP_TCOK_OFS (13) /*!< RTCTCOK Bit Offset */ -#define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /*!< Real-time clock temperature compensation write OK */ -/* RTC_C_TCMP[TCRDY] Bits */ -#define RTC_C_TCMP_TCRDY_OFS (14) /*!< RTCTCRDY Bit Offset */ -#define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /*!< Real-time clock temperature compensation ready */ -/* RTC_C_TCMP[TCMPS] Bits */ -#define RTC_C_TCMP_TCMPS_OFS (15) /*!< RTCTCMPS Bit Offset */ -#define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /*!< Real-time clock temperature compensation sign */ -/* RTC_C_PS0CTL[RT0PSIFG] Bits */ -#define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /*!< RT0PSIFG Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /*!< Prescale timer 0 interrupt flag */ -/* RTC_C_PS0CTL[RT0PSIE] Bits */ -#define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /*!< RT0PSIE Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /*!< Prescale timer 0 interrupt enable */ -/* RTC_C_PS0CTL[RT0IP] Bits */ -#define RTC_C_PS0CTL_RT0IP_OFS ( 2) /*!< RT0IP Bit Offset */ -#define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /*!< RT0IP Bit Mask */ -#define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /*!< RT0IP Bit 0 */ -#define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /*!< RT0IP Bit 1 */ -#define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /*!< RT0IP Bit 2 */ -#define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -/* RTC_C_PS1CTL[RT1PSIFG] Bits */ -#define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /*!< RT1PSIFG Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /*!< Prescale timer 1 interrupt flag */ -/* RTC_C_PS1CTL[RT1PSIE] Bits */ -#define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /*!< RT1PSIE Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /*!< Prescale timer 1 interrupt enable */ -/* RTC_C_PS1CTL[RT1IP] Bits */ -#define RTC_C_PS1CTL_RT1IP_OFS ( 2) /*!< RT1IP Bit Offset */ -#define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /*!< RT1IP Bit Mask */ -#define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /*!< RT1IP Bit 0 */ -#define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /*!< RT1IP Bit 1 */ -#define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /*!< RT1IP Bit 2 */ -#define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -/* RTC_C_PS[RT0PS] Bits */ -#define RTC_C_PS_RT0PS_OFS ( 0) /*!< RT0PS Bit Offset */ -#define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /*!< RT0PS Bit Mask */ -/* RTC_C_PS[RT1PS] Bits */ -#define RTC_C_PS_RT1PS_OFS ( 8) /*!< RT1PS Bit Offset */ -#define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /*!< RT1PS Bit Mask */ -/* RTC_C_TIM0[SEC] Bits */ -#define RTC_C_TIM0_SEC_OFS ( 0) /*!< Seconds Bit Offset */ -#define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /*!< Seconds Bit Mask */ -/* RTC_C_TIM0[MIN] Bits */ -#define RTC_C_TIM0_MIN_OFS ( 8) /*!< Minutes Bit Offset */ -#define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /*!< Minutes Bit Mask */ -/* RTC_C_TIM0[SEC_LD] Bits */ -#define RTC_C_TIM0_SEC_LD_OFS ( 0) /*!< SecondsLowDigit Bit Offset */ -#define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /*!< SecondsLowDigit Bit Mask */ -/* RTC_C_TIM0[SEC_HD] Bits */ -#define RTC_C_TIM0_SEC_HD_OFS ( 4) /*!< SecondsHighDigit Bit Offset */ -#define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /*!< SecondsHighDigit Bit Mask */ -/* RTC_C_TIM0[MIN_LD] Bits */ -#define RTC_C_TIM0_MIN_LD_OFS ( 8) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /*!< MinutesLowDigit Bit Mask */ -/* RTC_C_TIM0[MIN_HD] Bits */ -#define RTC_C_TIM0_MIN_HD_OFS (12) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /*!< MinutesHighDigit Bit Mask */ -/* RTC_C_TIM1[HOUR] Bits */ -#define RTC_C_TIM1_HOUR_OFS ( 0) /*!< Hours Bit Offset */ -#define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /*!< Hours Bit Mask */ -/* RTC_C_TIM1[DOW] Bits */ -#define RTC_C_TIM1_DOW_OFS ( 8) /*!< DayofWeek Bit Offset */ -#define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /*!< DayofWeek Bit Mask */ -/* RTC_C_TIM1[HOUR_LD] Bits */ -#define RTC_C_TIM1_HOUR_LD_OFS ( 0) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /*!< HoursLowDigit Bit Mask */ -/* RTC_C_TIM1[HOUR_HD] Bits */ -#define RTC_C_TIM1_HOUR_HD_OFS ( 4) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /*!< HoursHighDigit Bit Mask */ -/* RTC_C_DATE[DAY] Bits */ -#define RTC_C_DATE_DAY_OFS ( 0) /*!< Day Bit Offset */ -#define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /*!< Day Bit Mask */ -/* RTC_C_DATE[MON] Bits */ -#define RTC_C_DATE_MON_OFS ( 8) /*!< Month Bit Offset */ -#define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /*!< Month Bit Mask */ -/* RTC_C_DATE[DAY_LD] Bits */ -#define RTC_C_DATE_DAY_LD_OFS ( 0) /*!< DayLowDigit Bit Offset */ -#define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /*!< DayLowDigit Bit Mask */ -/* RTC_C_DATE[DAY_HD] Bits */ -#define RTC_C_DATE_DAY_HD_OFS ( 4) /*!< DayHighDigit Bit Offset */ -#define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /*!< DayHighDigit Bit Mask */ -/* RTC_C_DATE[MON_LD] Bits */ -#define RTC_C_DATE_MON_LD_OFS ( 8) /*!< MonthLowDigit Bit Offset */ -#define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /*!< MonthLowDigit Bit Mask */ -/* RTC_C_DATE[MON_HD] Bits */ -#define RTC_C_DATE_MON_HD_OFS (12) /*!< MonthHighDigit Bit Offset */ -#define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /*!< Month high digit (0 or 1) */ -/* RTC_C_YEAR[YEAR_LB] Bits */ -#define RTC_C_YEAR_YEAR_LB_OFS ( 0) /*!< YearLowByte Bit Offset */ -#define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /*!< YearLowByte Bit Mask */ -/* RTC_C_YEAR[YEAR_HB] Bits */ -#define RTC_C_YEAR_YEAR_HB_OFS ( 8) /*!< YearHighByte Bit Offset */ -#define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /*!< YearHighByte Bit Mask */ -/* RTC_C_YEAR[YEAR] Bits */ -#define RTC_C_YEAR_YEAR_OFS ( 0) /*!< Year Bit Offset */ -#define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /*!< Year Bit Mask */ -/* RTC_C_YEAR[DEC] Bits */ -#define RTC_C_YEAR_DEC_OFS ( 4) /*!< Decade Bit Offset */ -#define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /*!< Decade Bit Mask */ -/* RTC_C_YEAR[CENT_LD] Bits */ -#define RTC_C_YEAR_CENT_LD_OFS ( 8) /*!< CenturyLowDigit Bit Offset */ -#define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /*!< CenturyLowDigit Bit Mask */ -/* RTC_C_YEAR[CENT_HD] Bits */ -#define RTC_C_YEAR_CENT_HD_OFS (12) /*!< CenturyHighDigit Bit Offset */ -#define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /*!< CenturyHighDigit Bit Mask */ -/* RTC_C_AMINHR[MIN] Bits */ -#define RTC_C_AMINHR_MIN_OFS ( 0) /*!< Minutes Bit Offset */ -#define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /*!< Minutes Bit Mask */ -/* RTC_C_AMINHR[MINAE] Bits */ -#define RTC_C_AMINHR_MINAE_OFS ( 7) /*!< MINAE Bit Offset */ -#define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /*!< Alarm enable */ -/* RTC_C_AMINHR[HOUR] Bits */ -#define RTC_C_AMINHR_HOUR_OFS ( 8) /*!< Hours Bit Offset */ -#define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /*!< Hours Bit Mask */ -/* RTC_C_AMINHR[HOURAE] Bits */ -#define RTC_C_AMINHR_HOURAE_OFS (15) /*!< HOURAE Bit Offset */ -#define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /*!< Alarm enable */ -/* RTC_C_AMINHR[MIN_LD] Bits */ -#define RTC_C_AMINHR_MIN_LD_OFS ( 0) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /*!< MinutesLowDigit Bit Mask */ -/* RTC_C_AMINHR[MIN_HD] Bits */ -#define RTC_C_AMINHR_MIN_HD_OFS ( 4) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /*!< MinutesHighDigit Bit Mask */ -/* RTC_C_AMINHR[HOUR_LD] Bits */ -#define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /*!< HoursLowDigit Bit Mask */ -/* RTC_C_AMINHR[HOUR_HD] Bits */ -#define RTC_C_AMINHR_HOUR_HD_OFS (12) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /*!< HoursHighDigit Bit Mask */ -/* RTC_C_ADOWDAY[DOW] Bits */ -#define RTC_C_ADOWDAY_DOW_OFS ( 0) /*!< DayofWeek Bit Offset */ -#define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /*!< DayofWeek Bit Mask */ -/* RTC_C_ADOWDAY[DOWAE] Bits */ -#define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /*!< DOWAE Bit Offset */ -#define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /*!< Alarm enable */ -/* RTC_C_ADOWDAY[DAY] Bits */ -#define RTC_C_ADOWDAY_DAY_OFS ( 8) /*!< DayofMonth Bit Offset */ -#define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /*!< DayofMonth Bit Mask */ -/* RTC_C_ADOWDAY[DAYAE] Bits */ -#define RTC_C_ADOWDAY_DAYAE_OFS (15) /*!< DAYAE Bit Offset */ -#define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /*!< Alarm enable */ -/* RTC_C_ADOWDAY[DAY_LD] Bits */ -#define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /*!< DayLowDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /*!< DayLowDigit Bit Mask */ -/* RTC_C_ADOWDAY[DAY_HD] Bits */ -#define RTC_C_ADOWDAY_DAY_HD_OFS (12) /*!< DayHighDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /*!< DayHighDigit Bit Mask */ -/* Pre-defined bitfield values */ -#define RTC_C_KEY ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_H ((uint16_t)0x00A5) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_VAL ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ - - -/****************************************************************************** -* SCB Bits -******************************************************************************/ -/* SCB_PFR0[STATE0] Bits */ -#define SCB_PFR0_STATE0_OFS ( 0) /*!< STATE0 Bit Offset */ -#define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /*!< STATE0 Bit Mask */ -#define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /*!< STATE0 Bit 0 */ -#define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /*!< STATE0 Bit 1 */ -#define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /*!< STATE0 Bit 2 */ -#define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /*!< STATE0 Bit 3 */ -#define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /*!< no ARM encoding */ -#define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /*!< N/A */ -/* SCB_PFR0[STATE1] Bits */ -#define SCB_PFR0_STATE1_OFS ( 4) /*!< STATE1 Bit Offset */ -#define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /*!< STATE1 Bit Mask */ -#define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /*!< STATE1 Bit 0 */ -#define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /*!< STATE1 Bit 1 */ -#define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /*!< STATE1 Bit 2 */ -#define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /*!< STATE1 Bit 3 */ -#define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /*!< N/A */ -#define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /*!< N/A */ -#define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL */ - /* but no other 32-bit basic instructions (Note non-basic 32-bit instructions */ - /* can be added using the appropriate instruction attribute, but other 32-bit */ - /* basic instructions cannot.) */ -#define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /*!< Thumb-2 encoding with all Thumb-2 basic instructions */ -/* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /*!< two-stack support */ -/* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */ -/* SCB_MMFR0[PMSA_SUPPORT] Bits */ -#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /*!< PMSA_SUPPORT Bit Offset */ -#define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /*!< PMSA_SUPPORT Bit Mask */ -#define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /*!< PMSA_SUPPORT Bit 0 */ -#define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /*!< PMSA_SUPPORT Bit 1 */ -#define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /*!< PMSA_SUPPORT Bit 2 */ -#define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /*!< PMSA_SUPPORT Bit 3 */ -#define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /*!< IMPLEMENTATION DEFINED (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /*!< PMSA base (features as defined for ARMv6) (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /*!< PMSAv7 (base plus subregion support) */ -/* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /*!< CACHE_COHERENCE_SUPPORT Bit Offset */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /*!< CACHE_COHERENCE_SUPPORT Bit Mask */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /*!< CACHE_COHERENCE_SUPPORT Bit 0 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /*!< CACHE_COHERENCE_SUPPORT Bit 1 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /*!< CACHE_COHERENCE_SUPPORT Bit 2 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /*!< CACHE_COHERENCE_SUPPORT Bit 3 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /*!< no shared support */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /*!< partial-inner-shared coherency (coherency amongst some - but not all - of */ - /* the entities within an inner-coherent domain) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /*!< full-inner-shared coherency (coherency amongst all of the entities within an */ - /* inner-coherent domain) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /*!< full coherency (coherency amongst all of the entities) */ -/* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /*!< Outer non-sharable not supported */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /*!< Outer sharable supported */ -/* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /*!< Auxiliary control register */ -/* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /*!< wait for interrupt supported */ -/* SCB_ISAR0[BITCOUNT_INSTRS] Bits */ -#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /*!< BITCOUNT_INSTRS Bit Offset */ -#define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< BITCOUNT_INSTRS Bit Mask */ -#define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /*!< BITCOUNT_INSTRS Bit 0 */ -#define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /*!< BITCOUNT_INSTRS Bit 1 */ -#define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /*!< BITCOUNT_INSTRS Bit 2 */ -#define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /*!< BITCOUNT_INSTRS Bit 3 */ -#define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /*!< no bit-counting instructions present */ -#define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds CLZ */ -/* SCB_ISAR0[BITFIELD_INSTRS] Bits */ -#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /*!< BITFIELD_INSTRS Bit Offset */ -#define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /*!< BITFIELD_INSTRS Bit Mask */ -#define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /*!< BITFIELD_INSTRS Bit 0 */ -#define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /*!< BITFIELD_INSTRS Bit 1 */ -#define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /*!< BITFIELD_INSTRS Bit 2 */ -#define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /*!< BITFIELD_INSTRS Bit 3 */ -#define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /*!< no bitfield instructions present */ -#define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /*!< adds BFC, BFI, SBFX, UBFX */ -/* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /*!< CMPBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /*!< CMPBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /*!< CMPBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /*!< CMPBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /*!< CMPBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /*!< CMPBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no combined compare-and-branch instructions present */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /*!< adds CB{N}Z */ -/* SCB_ISAR0[COPROC_INSTRS] Bits */ -#define SCB_ISAR0_COPROC_INSTRS_OFS (16) /*!< COPROC_INSTRS Bit Offset */ -#define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /*!< COPROC_INSTRS Bit Mask */ -#define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /*!< COPROC_INSTRS Bit 0 */ -#define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /*!< COPROC_INSTRS Bit 1 */ -#define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /*!< COPROC_INSTRS Bit 2 */ -#define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /*!< COPROC_INSTRS Bit 3 */ -#define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /*!< no coprocessor support, other than for separately attributed architectures */ - /* such as CP15 or VFP */ -#define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /*!< adds generic CDP, LDC, MCR, MRC, STC */ -#define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */ -#define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /*!< adds generic MCRR, MRRC */ -#define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /*!< adds generic MCRR2, MRRC2 */ -/* SCB_ISAR0[DEBUG_INSTRS] Bits */ -#define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /*!< DEBUG_INSTRS Bit Offset */ -#define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /*!< DEBUG_INSTRS Bit Mask */ -#define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /*!< DEBUG_INSTRS Bit 0 */ -#define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /*!< DEBUG_INSTRS Bit 1 */ -#define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /*!< DEBUG_INSTRS Bit 2 */ -#define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /*!< DEBUG_INSTRS Bit 3 */ -#define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /*!< no debug instructions present */ -#define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /*!< adds BKPT */ -/* SCB_ISAR0[DIVIDE_INSTRS] Bits */ -#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /*!< DIVIDE_INSTRS Bit Offset */ -#define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /*!< DIVIDE_INSTRS Bit Mask */ -#define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /*!< DIVIDE_INSTRS Bit 0 */ -#define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /*!< DIVIDE_INSTRS Bit 1 */ -#define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /*!< DIVIDE_INSTRS Bit 2 */ -#define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /*!< DIVIDE_INSTRS Bit 3 */ -#define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /*!< no divide instructions present */ -#define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /*!< adds SDIV, UDIV (v1 quotient only result) */ -/* SCB_ISAR1[ETEND_INSRS] Bits */ -#define SCB_ISAR1_ETEND_INSRS_OFS (12) /*!< EXTEND_INSRS Bit Offset */ -#define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /*!< EXTEND_INSRS Bit Mask */ -#define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /*!< ETEND_INSRS Bit 0 */ -#define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /*!< ETEND_INSRS Bit 1 */ -#define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /*!< ETEND_INSRS Bit 2 */ -#define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /*!< ETEND_INSRS Bit 3 */ -#define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */ -#define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /*!< adds SXTB, SXTH, UXTB, UXTH */ -#define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /*!< N/A */ -/* SCB_ISAR1[IFTHEN_INSTRS] Bits */ -#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /*!< IFTHEN_INSTRS Bit Offset */ -#define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /*!< IFTHEN_INSTRS Bit Mask */ -#define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /*!< IFTHEN_INSTRS Bit 0 */ -#define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /*!< IFTHEN_INSTRS Bit 1 */ -#define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /*!< IFTHEN_INSTRS Bit 2 */ -#define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /*!< IFTHEN_INSTRS Bit 3 */ -#define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /*!< IT instructions not present */ -#define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /*!< adds IT instructions (and IT bits in PSRs) */ -/* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /*!< IMMEDIATE_INSTRS Bit Offset */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /*!< IMMEDIATE_INSTRS Bit Mask */ -#define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /*!< IMMEDIATE_INSTRS Bit 0 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /*!< IMMEDIATE_INSTRS Bit 1 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /*!< IMMEDIATE_INSTRS Bit 2 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /*!< IMMEDIATE_INSTRS Bit 3 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no special immediate-generating instructions present */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /*!< adds ADDW, MOVW, MOVT, SUBW */ -/* SCB_ISAR1[INTERWORK_INSTRS] Bits */ -#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /*!< INTERWORK_INSTRS Bit Offset */ -#define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /*!< INTERWORK_INSTRS Bit Mask */ -#define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /*!< INTERWORK_INSTRS Bit 0 */ -#define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /*!< INTERWORK_INSTRS Bit 1 */ -#define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /*!< INTERWORK_INSTRS Bit 2 */ -#define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /*!< INTERWORK_INSTRS Bit 3 */ -#define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /*!< no interworking instructions supported */ -#define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /*!< adds BX (and T bit in PSRs) */ -#define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /*!< adds BLX, and PC loads have BX-like behavior */ -#define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /*!< N/A */ -/* SCB_ISAR2[LOADSTORE_INSTRS] Bits */ -#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /*!< LOADSTORE_INSTRS Bit Offset */ -#define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< LOADSTORE_INSTRS Bit Mask */ -#define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /*!< LOADSTORE_INSTRS Bit 0 */ -#define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /*!< LOADSTORE_INSTRS Bit 1 */ -#define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /*!< LOADSTORE_INSTRS Bit 2 */ -#define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /*!< LOADSTORE_INSTRS Bit 3 */ -#define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /*!< no additional normal load/store instructions present */ -#define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRD/STRD */ -/* SCB_ISAR2[MEMHINT_INSTRS] Bits */ -#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /*!< MEMHINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< MEMHINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /*!< MEMHINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /*!< MEMHINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /*!< MEMHINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /*!< MEMHINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /*!< no memory hint instructions presen */ -#define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds PLD */ -#define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /*!< adds PLD (ie a repeat on value 1) */ -#define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /*!< adds PLI */ -/* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /*!< MULTIACCESSINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /*!< MULTIACCESSINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /*!< MULTIACCESSINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /*!< MULTIACCESSINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /*!< MULTIACCESSINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /*!< MULTIACCESSINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /*!< the (LDM/STM) instructions are non-interruptible */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /*!< the (LDM/STM) instructions are restartable */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /*!< the (LDM/STM) instructions are continuable */ -/* SCB_ISAR2[MULT_INSTRS] Bits */ -#define SCB_ISAR2_MULT_INSTRS_OFS (12) /*!< MULT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /*!< MULT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /*!< MULT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /*!< MULT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /*!< MULT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /*!< MULT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /*!< only MUL present */ -#define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /*!< adds MLA */ -#define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /*!< adds MLS */ -/* SCB_ISAR2[MULTS_INSTRS] Bits */ -#define SCB_ISAR2_MULTS_INSTRS_OFS (16) /*!< MULTS_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /*!< MULTS_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /*!< MULTS_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /*!< MULTS_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /*!< MULTS_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /*!< MULTS_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /*!< no signed multiply instructions present */ -#define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /*!< adds SMULL, SMLAL */ -#define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /*!< N/A */ -#define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /*!< N/A */ -/* SCB_ISAR2[MULTU_INSTRS] Bits */ -#define SCB_ISAR2_MULTU_INSTRS_OFS (20) /*!< MULTU_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /*!< MULTU_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /*!< MULTU_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /*!< MULTU_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /*!< MULTU_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /*!< MULTU_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /*!< no unsigned multiply instructions present */ -#define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /*!< adds UMULL, UMLAL */ -#define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /*!< N/A */ -/* SCB_ISAR2[REVERSAL_INSTRS] Bits */ -#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /*!< REVERSAL_INSTRS Bit Offset */ -#define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /*!< REVERSAL_INSTRS Bit Mask */ -#define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /*!< REVERSAL_INSTRS Bit 0 */ -#define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /*!< REVERSAL_INSTRS Bit 1 */ -#define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /*!< REVERSAL_INSTRS Bit 2 */ -#define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /*!< REVERSAL_INSTRS Bit 3 */ -#define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /*!< no reversal instructions present */ -#define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /*!< adds REV, REV16, REVSH */ -#define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /*!< adds RBIT */ -/* SCB_ISAR3[SATRUATE_INSTRS] Bits */ -#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /*!< SATRUATE_INSTRS Bit Offset */ -#define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< SATRUATE_INSTRS Bit Mask */ -#define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /*!< SATRUATE_INSTRS Bit 0 */ -#define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /*!< SATRUATE_INSTRS Bit 1 */ -#define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /*!< SATRUATE_INSTRS Bit 2 */ -#define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /*!< SATRUATE_INSTRS Bit 3 */ -#define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no non-SIMD saturate instructions present */ -#define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /*!< N/A */ -/* SCB_ISAR3[SIMD_INSTRS] Bits */ -#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /*!< SIMD_INSTRS Bit Offset */ -#define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /*!< SIMD_INSTRS Bit Mask */ -#define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /*!< SIMD_INSTRS Bit 0 */ -#define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /*!< SIMD_INSTRS Bit 1 */ -#define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /*!< SIMD_INSTRS Bit 2 */ -#define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /*!< SIMD_INSTRS Bit 3 */ -#define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /*!< no SIMD instructions present */ -#define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /*!< adds SSAT, USAT (and the Q flag in the PSRs) */ -#define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /*!< N/A */ -/* SCB_ISAR3[SVC_INSTRS] Bits */ -#define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /*!< SVC_INSTRS Bit Offset */ -#define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /*!< SVC_INSTRS Bit Mask */ -#define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /*!< SVC_INSTRS Bit 0 */ -#define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /*!< SVC_INSTRS Bit 1 */ -#define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /*!< SVC_INSTRS Bit 2 */ -#define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /*!< SVC_INSTRS Bit 3 */ -#define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /*!< no SVC (SWI) instructions present */ -#define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /*!< adds SVC (SWI) */ -/* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /*!< SYNCPRIM_INSTRS Bit Offset */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /*!< SYNCPRIM_INSTRS Bit Mask */ -#define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /*!< SYNCPRIM_INSTRS Bit 0 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /*!< SYNCPRIM_INSTRS Bit 1 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /*!< SYNCPRIM_INSTRS Bit 2 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /*!< SYNCPRIM_INSTRS Bit 3 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /*!< no synchronization primitives present */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /*!< adds LDREX, STREX */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */ -/* SCB_ISAR3[TABBRANCH_INSTRS] Bits */ -#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /*!< TABBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /*!< TABBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /*!< TABBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /*!< TABBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /*!< TABBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /*!< TABBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no table-branch instructions present */ -#define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /*!< adds TBB, TBH */ -/* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /*!< THUMBCOPY_INSTRS Bit Offset */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /*!< THUMBCOPY_INSTRS Bit Mask */ -#define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /*!< THUMBCOPY_INSTRS Bit 0 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /*!< THUMBCOPY_INSTRS Bit 1 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /*!< THUMBCOPY_INSTRS Bit 2 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /*!< THUMBCOPY_INSTRS Bit 3 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */ -/* SCB_ISAR3[TRUENOP_INSTRS] Bits */ -#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /*!< TRUENOP_INSTRS Bit Offset */ -#define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /*!< TRUENOP_INSTRS Bit Mask */ -#define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /*!< TRUENOP_INSTRS Bit 0 */ -#define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /*!< TRUENOP_INSTRS Bit 1 */ -#define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /*!< TRUENOP_INSTRS Bit 2 */ -#define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /*!< TRUENOP_INSTRS Bit 3 */ -#define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /*!< true NOP instructions not present - that is, NOP instructions with no */ - /* register dependencies */ -#define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */ -/* SCB_ISAR4[UNPRIV_INSTRS] Bits */ -#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /*!< UNPRIV_INSTRS Bit Offset */ -#define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /*!< UNPRIV_INSTRS Bit Mask */ -#define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /*!< UNPRIV_INSTRS Bit 0 */ -#define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /*!< UNPRIV_INSTRS Bit 1 */ -#define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /*!< UNPRIV_INSTRS Bit 2 */ -#define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /*!< UNPRIV_INSTRS Bit 3 */ -#define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /*!< no "T variant" instructions exist */ -#define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRBT, LDRT, STRBT, STRT */ -#define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */ -/* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /*!< WITHSHIFTS_INSTRS Bit Offset */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /*!< WITHSHIFTS_INSTRS Bit Mask */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /*!< WITHSHIFTS_INSTRS Bit 0 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /*!< WITHSHIFTS_INSTRS Bit 1 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /*!< WITHSHIFTS_INSTRS Bit 2 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /*!< WITHSHIFTS_INSTRS Bit 3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /*!< non-zero shifts only support MOV and shift instructions (see notes) */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /*!< shifts of loads/stores over the range LSL 0-3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /*!< adds other constant shift options. */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /*!< adds register-controlled shift options. */ -/* SCB_ISAR4[WRITEBACK_INSTRS] Bits */ -#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /*!< WRITEBACK_INSTRS Bit Offset */ -#define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /*!< WRITEBACK_INSTRS Bit Mask */ -#define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /*!< WRITEBACK_INSTRS Bit 0 */ -#define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /*!< WRITEBACK_INSTRS Bit 1 */ -#define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /*!< WRITEBACK_INSTRS Bit 2 */ -#define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /*!< WRITEBACK_INSTRS Bit 3 */ -#define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /*!< only non-writeback addressing modes present, except that */ - /* LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */ -#define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */ -/* SCB_ISAR4[BARRIER_INSTRS] Bits */ -#define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /*!< BARRIER_INSTRS Bit Offset */ -#define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /*!< BARRIER_INSTRS Bit Mask */ -#define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /*!< BARRIER_INSTRS Bit 0 */ -#define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /*!< BARRIER_INSTRS Bit 1 */ -#define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /*!< BARRIER_INSTRS Bit 2 */ -#define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /*!< BARRIER_INSTRS Bit 3 */ -#define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /*!< no barrier instructions supported */ -#define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /*!< adds DMB, DSB, ISB barrier instructions */ -/* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /*!< no additional support */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */ -/* SCB_ISAR4[PSR_M_INSTRS] Bits */ -#define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /*!< PSR_M_INSTRS Bit Offset */ -#define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /*!< PSR_M_INSTRS Bit Mask */ -#define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /*!< PSR_M_INSTRS Bit 0 */ -#define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /*!< PSR_M_INSTRS Bit 1 */ -#define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /*!< PSR_M_INSTRS Bit 2 */ -#define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /*!< PSR_M_INSTRS Bit 3 */ -#define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /*!< instructions not present */ -#define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */ -/* SCB_CPACR[CP11] Bits */ -#define SCB_CPACR_CP11_OFS (22) /*!< CP11 Bit Offset */ -#define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /*!< CP11 Bit Mask */ -/* SCB_CPACR[CP10] Bits */ -#define SCB_CPACR_CP10_OFS (20) /*!< CP10 Bit Offset */ -#define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /*!< CP10 Bit Mask */ -/* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */ -#define SCB_SHPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define SCB_SHPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */ -#define SCB_SHPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define SCB_SHPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */ -#define SCB_SHPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define SCB_SHPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */ -#define SCB_SHPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define SCB_SHPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */ -#define SCB_SHPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define SCB_SHPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */ -#define SCB_SHPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define SCB_SHPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */ -#define SCB_SHPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define SCB_SHPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */ -#define SCB_SHPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define SCB_SHPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */ -#define SCB_SHPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define SCB_SHPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */ -#define SCB_SHPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define SCB_SHPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */ -#define SCB_SHPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define SCB_SHPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */ -#define SCB_SHPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define SCB_SHPR3_PRI_15_M ((uint32_t)0xff000000) /* */ - -/* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */ -#define SCB_CFSR_IACCVIOL_OFS ( 0) /*!< IACCVIOL Offset */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /* */ -/* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */ -#define SCB_CFSR_DACCVIOL_OFS ( 1) /*!< DACCVIOL Offset */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /* */ -/* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */ -#define SCB_CFSR_MUNSTKERR_OFS ( 3) /*!< MUNSTKERR Offset */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /* */ -/* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */ -#define SCB_CFSR_MSTKERR_OFS ( 4) /*!< MSTKERR Offset */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /* */ -/* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */ -#define SCB_CFSR_MMARVALID_OFS ( 7) /*!< MMARVALID Offset */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /* */ -/* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */ -#define SCB_CFSR_IBUSERR_OFS ( 8) /*!< IBUSERR Offset */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /* */ -/* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */ -#define SCB_CFSR_PRECISERR_OFS ( 9) /*!< PRECISERR Offset */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /* */ -/* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */ -#define SCB_CFSR_IMPRECISERR_OFS (10) /*!< IMPRECISERR Offset */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /* */ -/* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */ -#define SCB_CFSR_UNSTKERR_OFS (11) /*!< UNSTKERR Offset */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /* */ -/* SCB_CFSR[SCB_CFSR_STKERR] Bits */ -#define SCB_CFSR_STKERR_OFS (12) /*!< STKERR Offset */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /* */ -/* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */ -#define SCB_CFSR_BFARVALID_OFS (15) /*!< BFARVALID Offset */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /* */ -/* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */ -#define SCB_CFSR_UNDEFINSTR_OFS (16) /*!< UNDEFINSTR Offset */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /* */ -/* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */ -#define SCB_CFSR_INVSTATE_OFS (17) /*!< INVSTATE Offset */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /* */ -/* SCB_CFSR[SCB_CFSR_INVPC] Bits */ -#define SCB_CFSR_INVPC_OFS (18) /*!< INVPC Offset */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /* */ -/* SCB_CFSR[SCB_CFSR_NOCP] Bits */ -#define SCB_CFSR_NOCP_OFS (19) /*!< NOCP Offset */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /* */ -/* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */ -#define SCB_CFSR_UNALIGNED_OFS (24) /*!< UNALIGNED Offset */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /* */ -/* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */ -#define SCB_CFSR_DIVBYZERO_OFS (25) /*!< DIVBYZERO Offset */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /* */ -/* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */ -#define SCB_CFSR_MLSPERR_OFS ( 5) /*!< MLSPERR Offset */ -#define SCB_CFSR_MLSPERR ((uint32_t)0x00000020) /* */ -/* SCB_CFSR[SCB_CFSR_LSPERR] Bits */ -#define SCB_CFSR_LSPERR_OFS (13) /*!< LSPERR Offset */ -#define SCB_CFSR_LSPERR ((uint32_t)0x00002000) /* */ - - -/****************************************************************************** -* SCNSCB Bits -******************************************************************************/ - - -/****************************************************************************** -* SYSCTL Bits -******************************************************************************/ -/* SYSCTL_REBOOT_CTL[REBOOT] Bits */ -#define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define SYSCTL_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /*!< Write 1 initiates a Reboot of the device */ -/* SYSCTL_REBOOT_CTL[WKEY] Bits */ -#define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -/* SYSCTL_NMI_CTLSTAT[CS_SRC] Bits */ -#define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /*!< CS_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /*!< CS interrupt as a source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PSS_SRC] Bits */ -#define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /*!< PSS_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /*!< PSS interrupt as a source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PCM_SRC] Bits */ -#define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /*!< PCM_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /*!< PCM interrupt as a source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PIN_SRC] Bits */ -#define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /*!< PIN_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008) -/* SYSCTL_NMI_CTLSTAT[CS_FLG] Bits */ -#define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /*!< CS_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /*!< CS interrupt was the source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PSS_FLG] Bits */ -#define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /*!< PSS_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /*!< PSS interrupt was the source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PCM_FLG] Bits */ -#define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /*!< PCM_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /*!< PCM interrupt was the source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PIN_FLG] Bits */ -#define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /*!< PIN_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /*!< RSTn/NMI pin was the source of NMI */ -/* SYSCTL_WDTRESET_CTL[TIMEOUT] Bits */ -#define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /*!< TIMEOUT Bit Offset */ -#define SYSCTL_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /*!< WDT timeout reset type */ -/* SYSCTL_WDTRESET_CTL[VIOLATION] Bits */ -#define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /*!< VIOLATION Bit Offset */ -#define SYSCTL_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /*!< WDT password violation reset type */ -/* SYSCTL_PERIHALT_CTL[HALT_T16_0] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /*!< HALT_T16_0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_T16_1] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /*!< HALT_T16_1 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_T16_2] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /*!< HALT_T16_2 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_T16_3] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /*!< HALT_T16_3 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_T32_0] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /*!< HALT_T32_0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUA0] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /*!< HALT_eUA0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUA1] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /*!< HALT_eUA1 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUA2] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /*!< HALT_eUA2 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUA3] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /*!< HALT_eUA3 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUB0] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /*!< HALT_eUB0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUB1] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB1_OFS (10) /*!< HALT_eUB1 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUB2] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB2_OFS (11) /*!< HALT_eUB2 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUB3] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB3_OFS (12) /*!< HALT_eUB3 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_ADC] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_ADC_OFS (13) /*!< HALT_ADC Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_WDT] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_WDT_OFS (14) /*!< HALT_WDT Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_DMA] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_DMA_OFS (15) /*!< HALT_DMA Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_SRAM_BANKEN[BNK0_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /*!< BNK0_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK0_EN ((uint32_t)0x00000001) /*!< SRAM Bank0 enable */ -/* SYSCTL_SRAM_BANKEN[BNK1_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /*!< BNK1_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK1_EN ((uint32_t)0x00000002) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK2_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /*!< BNK2_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK2_EN ((uint32_t)0x00000004) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK3_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /*!< BNK3_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK3_EN ((uint32_t)0x00000008) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK4_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /*!< BNK4_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK4_EN ((uint32_t)0x00000010) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK5_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /*!< BNK5_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK5_EN ((uint32_t)0x00000020) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK6_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /*!< BNK6_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK6_EN ((uint32_t)0x00000040) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK7_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /*!< BNK7_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK7_EN ((uint32_t)0x00000080) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[SRAM_RDY] Bits */ -#define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ -#define SYSCTL_SRAM_BANKEN_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ -/* SYSCTL_SRAM_BANKRET[BNK0_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /*!< BNK0_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK0_RET ((uint32_t)0x00000001) /*!< Bank0 retention */ -/* SYSCTL_SRAM_BANKRET[BNK1_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /*!< BNK1_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK1_RET ((uint32_t)0x00000002) /*!< Bank1 retention */ -/* SYSCTL_SRAM_BANKRET[BNK2_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /*!< BNK2_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK2_RET ((uint32_t)0x00000004) /*!< Bank2 retention */ -/* SYSCTL_SRAM_BANKRET[BNK3_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /*!< BNK3_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK3_RET ((uint32_t)0x00000008) /*!< Bank3 retention */ -/* SYSCTL_SRAM_BANKRET[BNK4_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /*!< BNK4_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK4_RET ((uint32_t)0x00000010) /*!< Bank4 retention */ -/* SYSCTL_SRAM_BANKRET[BNK5_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /*!< BNK5_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK5_RET ((uint32_t)0x00000020) /*!< Bank5 retention */ -/* SYSCTL_SRAM_BANKRET[BNK6_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /*!< BNK6_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK6_RET ((uint32_t)0x00000040) /*!< Bank6 retention */ -/* SYSCTL_SRAM_BANKRET[BNK7_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /*!< BNK7_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK7_RET ((uint32_t)0x00000080) /*!< Bank7 retention */ -/* SYSCTL_SRAM_BANKRET[SRAM_RDY] Bits */ -#define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ -#define SYSCTL_SRAM_BANKRET_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ -/* SYSCTL_DIO_GLTFLT_CTL[GLTCH_EN] Bits */ -#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /*!< GLTCH_EN Bit Offset */ -#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /*!< Glitch filter enable */ -/* SYSCTL_SECDATA_UNLOCK[UNLKEY] Bits */ -#define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -/* SYSCTL_MASTER_UNLOCK[UNLKEY] Bits */ -#define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -/* SYSCTL_RESET_REQ[POR] Bits */ -#define SYSCTL_RESET_REQ_POR_OFS ( 0) /*!< POR Bit Offset */ -#define SYSCTL_RESET_REQ_POR ((uint32_t)0x00000001) /*!< Generate POR */ -/* SYSCTL_RESET_REQ[REBOOT] Bits */ -#define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /*!< REBOOT Bit Offset */ -#define SYSCTL_RESET_REQ_REBOOT ((uint32_t)0x00000002) /*!< Generate Reboot_Reset */ -/* SYSCTL_RESET_REQ[WKEY] Bits */ -#define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -/* SYSCTL_RESET_STATOVER[SOFT] Bits */ -#define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /*!< SOFT Bit Offset */ -#define SYSCTL_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /*!< Indicates if SOFT Reset is active */ -/* SYSCTL_RESET_STATOVER[HARD] Bits */ -#define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /*!< HARD Bit Offset */ -#define SYSCTL_RESET_STATOVER_HARD ((uint32_t)0x00000002) /*!< Indicates if HARD Reset is active */ -/* SYSCTL_RESET_STATOVER[REBOOT] Bits */ -#define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /*!< REBOOT Bit Offset */ -#define SYSCTL_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /*!< Indicates if Reboot Reset is active */ -/* SYSCTL_RESET_STATOVER[SOFT_OVER] Bits */ -#define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /*!< SOFT_OVER Bit Offset */ -#define SYSCTL_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /*!< SOFT_Reset overwrite request */ -/* SYSCTL_RESET_STATOVER[HARD_OVER] Bits */ -#define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /*!< HARD_OVER Bit Offset */ -#define SYSCTL_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /*!< HARD_Reset overwrite request */ -/* SYSCTL_RESET_STATOVER[RBT_OVER] Bits */ -#define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /*!< RBT_OVER Bit Offset */ -#define SYSCTL_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /*!< Reboot Reset overwrite request */ -/* Pre-defined bitfield values */ -#define SYSCTL_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bit 0 */ - /* cleared */ - - -/****************************************************************************** -* SYSTICK Bits -******************************************************************************/ - -/****************************************************************************** -* Timer32 Bits -******************************************************************************/ -/* TIMER32_CONTROL[ONESHOT] Bits */ -#define TIMER32_CONTROL_ONESHOT_OFS ( 0) /*!< ONESHOT Bit Offset */ -#define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /*!< Selects one-shot or wrapping counter mode */ -/* TIMER32_CONTROL[SIZE] Bits */ -#define TIMER32_CONTROL_SIZE_OFS ( 1) /*!< SIZE Bit Offset */ -#define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /*!< Selects 16 or 32 bit counter operation */ -/* TIMER32_CONTROL[PRESCALE] Bits */ -#define TIMER32_CONTROL_PRESCALE_OFS ( 2) /*!< PRESCALE Bit Offset */ -#define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /*!< PRESCALE Bit Mask */ -#define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /*!< PRESCALE Bit 0 */ -#define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /*!< PRESCALE Bit 1 */ -#define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /*!< 0 stages of prescale, clock is divided by 1 */ -#define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /*!< 4 stages of prescale, clock is divided by 16 */ -#define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /*!< 8 stages of prescale, clock is divided by 256 */ -/* TIMER32_CONTROL[IE] Bits */ -#define TIMER32_CONTROL_IE_OFS ( 5) /*!< IE Bit Offset */ -#define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /*!< Interrupt enable bit */ -/* TIMER32_CONTROL[MODE] Bits */ -#define TIMER32_CONTROL_MODE_OFS ( 6) /*!< MODE Bit Offset */ -#define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /*!< Mode bit */ -/* TIMER32_CONTROL[ENABLE] Bits */ -#define TIMER32_CONTROL_ENABLE_OFS ( 7) /*!< ENABLE Bit Offset */ -#define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080) -/* TIMER32_RIS[RAW_IFG] Bits */ -#define TIMER32_RIS_RAW_IFG_OFS ( 0) /*!< RAW_IFG Bit Offset */ -#define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /*!< Raw interrupt status */ -/* TIMER32_MIS[IFG] Bits */ -#define TIMER32_MIS_IFG_OFS ( 0) /*!< IFG Bit Offset */ -#define TIMER32_MIS_IFG ((uint32_t)0x00000001) /*!< Enabled interrupt status */ - - - -/****************************************************************************** -* TIMER_A Bits -******************************************************************************/ -/* TIMER_A_CTL[IFG] Bits */ -#define TIMER_A_CTL_IFG_OFS ( 0) /*!< TAIFG Bit Offset */ -#define TIMER_A_CTL_IFG ((uint16_t)0x0001) /*!< TimerA interrupt flag */ -/* TIMER_A_CTL[IE] Bits */ -#define TIMER_A_CTL_IE_OFS ( 1) /*!< TAIE Bit Offset */ -#define TIMER_A_CTL_IE ((uint16_t)0x0002) /*!< TimerA interrupt enable */ -/* TIMER_A_CTL[CLR] Bits */ -#define TIMER_A_CTL_CLR_OFS ( 2) /*!< TACLR Bit Offset */ -#define TIMER_A_CTL_CLR ((uint16_t)0x0004) /*!< TimerA clear */ -/* TIMER_A_CTL[MC] Bits */ -#define TIMER_A_CTL_MC_OFS ( 4) /*!< MC Bit Offset */ -#define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /*!< MC Bit Mask */ -#define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /*!< MC Bit 0 */ -#define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /*!< MC Bit 1 */ -#define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -#define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -/* TIMER_A_CTL[ID] Bits */ -#define TIMER_A_CTL_ID_OFS ( 6) /*!< ID Bit Offset */ -#define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /*!< ID Bit Mask */ -#define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /*!< ID Bit 0 */ -#define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /*!< ID Bit 1 */ -#define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /*!< /8 */ -#define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /*!< /8 */ -/* TIMER_A_CTL[SSEL] Bits */ -#define TIMER_A_CTL_SSEL_OFS ( 8) /*!< TASSEL Bit Offset */ -#define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /*!< TASSEL Bit Mask */ -#define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /*!< SSEL Bit 0 */ -#define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /*!< SSEL Bit 1 */ -#define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /*!< INCLK */ -#define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /*!< INCLK */ -/* TIMER_A_CCTLN[CCIFG] Bits */ -#define TIMER_A_CCTLN_CCIFG_OFS ( 0) /*!< CCIFG Bit Offset */ -#define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /*!< Capture/compare interrupt flag */ -/* TIMER_A_CCTLN[COV] Bits */ -#define TIMER_A_CCTLN_COV_OFS ( 1) /*!< COV Bit Offset */ -#define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /*!< Capture overflow */ -/* TIMER_A_CCTLN[OUT] Bits */ -#define TIMER_A_CCTLN_OUT_OFS ( 2) /*!< OUT Bit Offset */ -#define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /*!< Output */ -/* TIMER_A_CCTLN[CCI] Bits */ -#define TIMER_A_CCTLN_CCI_OFS ( 3) /*!< CCI Bit Offset */ -#define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /*!< Capture/compare input */ -/* TIMER_A_CCTLN[CCIE] Bits */ -#define TIMER_A_CCTLN_CCIE_OFS ( 4) /*!< CCIE Bit Offset */ -#define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /*!< Capture/compare interrupt enable */ -/* TIMER_A_CCTLN[OUTMOD] Bits */ -#define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /*!< OUTMOD Bit Offset */ -#define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /*!< OUTMOD Bit Mask */ -#define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /*!< OUTMOD Bit 0 */ -#define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /*!< OUTMOD Bit 1 */ -#define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /*!< OUTMOD Bit 2 */ -#define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /*!< OUT bit value */ -#define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /*!< Set */ -#define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /*!< Toggle/reset */ -#define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /*!< Set/reset */ -#define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /*!< Toggle */ -#define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /*!< Reset */ -#define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /*!< Toggle/set */ -#define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /*!< Reset/set */ -/* TIMER_A_CCTLN[CAP] Bits */ -#define TIMER_A_CCTLN_CAP_OFS ( 8) /*!< CAP Bit Offset */ -#define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /*!< Capture mode */ -/* TIMER_A_CCTLN[SCCI] Bits */ -#define TIMER_A_CCTLN_SCCI_OFS (10) /*!< SCCI Bit Offset */ -#define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /*!< Synchronized capture/compare input */ -/* TIMER_A_CCTLN[SCS] Bits */ -#define TIMER_A_CCTLN_SCS_OFS (11) /*!< SCS Bit Offset */ -#define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /*!< Synchronize capture source */ -/* TIMER_A_CCTLN[CCIS] Bits */ -#define TIMER_A_CCTLN_CCIS_OFS (12) /*!< CCIS Bit Offset */ -#define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /*!< CCIS Bit Mask */ -#define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /*!< CCIS Bit 0 */ -#define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /*!< CCIS Bit 1 */ -#define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /*!< VCC */ -#define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /*!< VCC */ -/* TIMER_A_CCTLN[CM] Bits */ -#define TIMER_A_CCTLN_CM_OFS (14) /*!< CM Bit Offset */ -#define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /*!< CM Bit Mask */ -#define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /*!< CM Bit 0 */ -#define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /*!< CM Bit 1 */ -#define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -#define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -/* TIMER_A_EX0[IDEX] Bits */ -#define TIMER_A_EX0_IDEX_OFS ( 0) /*!< TAIDEX Bit Offset */ -#define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /*!< TAIDEX Bit Mask */ -#define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /*!< IDEX Bit 0 */ -#define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /*!< IDEX Bit 1 */ -#define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /*!< IDEX Bit 2 */ -#define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /*!< Divide by 8 */ -#define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /*!< Divide by 8 */ - -/****************************************************************************** -* TLV Bits -******************************************************************************/ -/****************************************************************************** -* TLV table start and TLV tags * -******************************************************************************/ -#define TLV_START_ADDR (TLV_BASE + 0x0004) /*!< Start Address of the TLV structure */ - -#define TLV_TAG_RESERVED1 1 -#define TLV_TAG_RESERVED2 2 -#define TLV_TAG_CS 3 -#define TLV_TAG_FLASHCTL 4 -#define TLV_TAG_ADC14 5 -#define TLV_TAG_RESERVED6 6 -#define TLV_TAG_RESERVED7 7 -#define TLV_TAG_REF 8 -#define TLV_TAG_RESERVED9 9 -#define TLV_TAG_RESERVED10 10 -#define TLV_TAG_DEVINFO 11 -#define TLV_TAG_DIEREC 12 -#define TLV_TAG_RANDNUM 13 -#define TLV_TAG_RESERVED14 14 -#define TLV_TAG_BSL 15 -#define TLV_TAG_END (0x0BD0E11D) - - -/****************************************************************************** -* TPIU Bits -******************************************************************************/ - - -/****************************************************************************** -* WDT_A Bits -******************************************************************************/ -/* WDT_A_CTL[IS] Bits */ -#define WDT_A_CTL_IS_OFS ( 0) /*!< WDTIS Bit Offset */ -#define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /*!< WDTIS Bit Mask */ -#define WDT_A_CTL_IS0 ((uint16_t)0x0001) /*!< IS Bit 0 */ -#define WDT_A_CTL_IS1 ((uint16_t)0x0002) /*!< IS Bit 1 */ -#define WDT_A_CTL_IS2 ((uint16_t)0x0004) /*!< IS Bit 2 */ -#define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ -#define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ -/* WDT_A_CTL[CNTCL] Bits */ -#define WDT_A_CTL_CNTCL_OFS ( 3) /*!< WDTCNTCL Bit Offset */ -#define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /*!< Watchdog timer counter clear */ -/* WDT_A_CTL[TMSEL] Bits */ -#define WDT_A_CTL_TMSEL_OFS ( 4) /*!< WDTTMSEL Bit Offset */ -#define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /*!< Watchdog timer mode select */ -/* WDT_A_CTL[SSEL] Bits */ -#define WDT_A_CTL_SSEL_OFS ( 5) /*!< WDTSSEL Bit Offset */ -#define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /*!< WDTSSEL Bit Mask */ -#define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /*!< SSEL Bit 0 */ -#define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /*!< SSEL Bit 1 */ -#define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /*!< BCLK */ -#define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /*!< BCLK */ -/* WDT_A_CTL[HOLD] Bits */ -#define WDT_A_CTL_HOLD_OFS ( 7) /*!< WDTHOLD Bit Offset */ -#define WDT_A_CTL_HOLD ((uint16_t)0x0080) /*!< Watchdog timer hold */ -/* WDT_A_CTL[PW] Bits */ -#define WDT_A_CTL_PW_OFS ( 8) /*!< WDTPW Bit Offset */ -#define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /*!< WDTPW Bit Mask */ -/* Pre-defined bitfield values */ -#define WDT_A_CTL_PW ((uint16_t)0x5A00) /*!< WDT Key Value for WDT write access */ - - -/****************************************************************************** -* BSL * -******************************************************************************/ -#define BSL_DEFAULT_PARAM ((uint32_t)0xFC48FFFF) /*!< I2C slave address = 0x48, Interface selection = Auto */ -#define BSL_API_TABLE_ADDR ((uint32_t)0x00202000) /*!< Address of BSL API table */ -#define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR)) - -#define BSL_AUTO_INTERFACE ((uint32_t)0x0000E0000) /*!< Auto detect interface */ -#define BSL_UART_INTERFACE ((uint32_t)0x0000C0000) /*!< UART interface */ -#define BSL_SPI_INTERFACE ((uint32_t)0x0000A0000) /*!< SPI interface */ -#define BSL_I2C_INTERFACE ((uint32_t)0x000080000) /*!< I2C interface */ - -#define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */ - - -/****************************************************************************** -* Mailbox struct legacy definition * -******************************************************************************/ -#define FLASH_MAILBOX_Type FL_BOOTOVER_MAILBOX_Type - -/****************************************************************************** -* Device Unlock Support * -******************************************************************************/ -/* unlock the device by: - * Load SYSCTL_SECDATA_UNLOCK register address into R0 - * Load SYSCTL_SECDATA_UNLOCK unlock key into R1 - * Write the unlock key to the SYSCTL_SECDATA_UNLOCK register - */ -#define UNLOCK_DEVICE\ - __asm(" MOVW.W R0, #0x3040");\ - __asm(" MOVT.W R0, #0xE004");\ - __asm(" MOVW.W R1, #0x695A");\ - __asm(" MOVT.W R1, #0x0000");\ - __asm(" STR R1, [R0]"); - -/****************************************************************************** -* -* The following are values that can be used to choose the command that will be -* run by the boot code. Perform a logical OR of these settings to create your -* general parameter command. -* -******************************************************************************/ -#define COMMAND_FACTORY_RESET ((uint32_t)0x00010000) -#define COMMAND_BSL_CONFIG ((uint32_t)0x00020000) -#define COMMAND_JTAG_SWD_LOCK_SECEN ((uint32_t)0x00080000) -#define COMMAND_SEC_ZONE0_EN ((uint32_t)0x00100000) -#define COMMAND_SEC_ZONE1_EN ((uint32_t)0x00200000) -#define COMMAND_SEC_ZONE2_EN ((uint32_t)0x00400000) -#define COMMAND_SEC_ZONE3_EN ((uint32_t)0x00800000) -#define COMMAND_SEC_ZONE0_UPDATE ((uint32_t)0x01000000) -#define COMMAND_SEC_ZONE1_UPDATE ((uint32_t)0x02000000) -#define COMMAND_SEC_ZONE2_UPDATE ((uint32_t)0x04000000) -#define COMMAND_SEC_ZONE3_UPDATE ((uint32_t)0x08000000) -#define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE ((uint32_t)0x10000000) -#define COMMAND_NONE ((uint32_t)0xFFFFFFFF) - -/****************************************************************************** -* -* The following are values that can be used to configure the BSL. Perform a -* logical OR of these settings to create your BSL parameter. -* -******************************************************************************/ -#define BSL_CONFIG_HW_INVOKE ((uint32_t)0x70000000) - -#define BSL_CONFIG_HW_INVOKE_PORT1 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PORT2 ((uint32_t)0x00000001) -#define BSL_CONFIG_HW_INVOKE_PORT3 ((uint32_t)0x00000002) - -#define BSL_CONFIG_HW_INVOKE_PIN0 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN1 ((uint32_t)0x00000010) -#define BSL_CONFIG_HW_INVOKE_PIN2 ((uint32_t)0x00000020) -#define BSL_CONFIG_HW_INVOKE_PIN3 ((uint32_t)0x00000030) -#define BSL_CONFIG_HW_INVOKE_PIN4 ((uint32_t)0x00000040) -#define BSL_CONFIG_HW_INVOKE_PIN5 ((uint32_t)0x00000050) -#define BSL_CONFIG_HW_INVOKE_PIN6 ((uint32_t)0x00000060) -#define BSL_CONFIG_HW_INVOKE_PIN7 ((uint32_t)0x00000070) - -#define BSL_CONFIG_HW_INVOKE_PIN_LOW ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN_HIGH ((uint32_t)0x00001000) - -#define BSL_CONFIG_INTERFACE_I2C ((uint32_t)0x00008000) -#define BSL_CONFIG_INTERFACE_SPI ((uint32_t)0x0000A000) -#define BSL_CONFIG_INTERFACE_UART ((uint32_t)0x0000C000) -#define BSL_CONFIG_INTERFACE_AUTO ((uint32_t)0x0000E000) - -#define BSL_CONFIG_I2C_ADD_OFFSET (16) - - -/****************************************************************************** -* ULP Advisor * -******************************************************************************/ -#ifdef __TI_ARM__ -#pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8}) -#pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8}) -#pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8}) -#pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8}) -#pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8}) -#pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8}) -#pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8}) -#pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8}) -#pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8}) -#pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8}) -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* __MSP432P401M_H__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p401m_classic.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p401m_classic.h deleted file mode 100644 index 4039f213f96..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p401m_classic.h +++ /dev/null @@ -1,3623 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432P401M Register Definitions -* -* This file includes MSP430 style component and register definitions -* for legacy components re-used in MSP432 -* -* File creation date: 2017-08-03 -* -******************************************************************************/ - -#ifndef __MSP432P401M_CLASSIC_H__ -#define __MSP432P401M_CLASSIC_H__ - -/* Use standard integer types with explicit width */ -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/****************************************************************************** -* Device memory map * -******************************************************************************/ -#define __MAIN_MEMORY_START__ (0x00000000) /*!< Main Flash memory start address */ -#define __MAIN_MEMORY_END__ (0x0001FFFF) /*!< Main Flash memory end address */ -#define __BSL_MEMORY_START__ (0x00202000) /*!< BSL memory start address */ -#define __BSL_MEMORY_END__ (0x00203FFF) /*!< BSL memory end address */ -#define __SRAM_START__ (0x20000000) /*!< SRAM memory start address */ -#define __SRAM_END__ (0x20007FFF) /*!< SRAM memory end address */ - -/****************************************************************************** -* MSP-format peripheral registers * -******************************************************************************/ - -/****************************************************************************** -* AES256 Registers -******************************************************************************/ -#define AESACTL0 (HWREG16(0x40003C00)) /*!< AES Accelerator Control Register 0 */ -#define AESACTL1 (HWREG16(0x40003C02)) /*!< AES Accelerator Control Register 1 */ -#define AESASTAT (HWREG16(0x40003C04)) /*!< AES Accelerator Status Register */ -#define AESAKEY (HWREG16(0x40003C06)) /*!< AES Accelerator Key Register */ -#define AESADIN (HWREG16(0x40003C08)) /*!< AES Accelerator Data In Register */ -#define AESADOUT (HWREG16(0x40003C0A)) /*!< AES Accelerator Data Out Register */ -#define AESAXDIN (HWREG16(0x40003C0C)) /*!< AES Accelerator XORed Data In Register */ -#define AESAXIN (HWREG16(0x40003C0E)) /*!< AES Accelerator XORed Data In Register */ - -/* Register offsets from AES256_BASE address */ -#define OFS_AESACTL0 (0x0000) /*!< AES Accelerator Control Register 0 */ -#define OFS_AESACTL1 (0x0002) /*!< AES Accelerator Control Register 1 */ -#define OFS_AESASTAT (0x0004) /*!< AES Accelerator Status Register */ -#define OFS_AESAKEY (0x0006) /*!< AES Accelerator Key Register */ -#define OFS_AESADIN (0x0008) /*!< AES Accelerator Data In Register */ -#define OFS_AESADOUT (0x000A) /*!< AES Accelerator Data Out Register */ -#define OFS_AESAXDIN (0x000C) /*!< AES Accelerator XORed Data In Register */ -#define OFS_AESAXIN (0x000E) /*!< AES Accelerator XORed Data In Register */ - - -/****************************************************************************** -* CAPTIO0 Registers -******************************************************************************/ -#define CAPTIO0CTL (HWREG16(0x4000540E)) /*!< Capacitive Touch IO x Control Register */ - -/* Register offsets from CAPTIO0_BASE address */ -#define OFS_CAPTIO0CTL (0x000E) /*!< Capacitive Touch IO x Control Register */ - -#define CAPTIO0CTL_L (HWREG8_L(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */ -#define CAPTIO0CTL_H (HWREG8_H(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */ - -/****************************************************************************** -* CAPTIO1 Registers -******************************************************************************/ -#define CAPTIO1CTL (HWREG16(0x4000580E)) /*!< Capacitive Touch IO x Control Register */ - -/* Register offsets from CAPTIO1_BASE address */ -#define OFS_CAPTIO1CTL (0x000E) /*!< Capacitive Touch IO x Control Register */ - -#define CAPTIO1CTL_L (HWREG8_L(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */ -#define CAPTIO1CTL_H (HWREG8_H(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */ - -/****************************************************************************** -* COMP_E0 Registers -******************************************************************************/ -#define CE0CTL0 (HWREG16(0x40003400)) /*!< Comparator Control Register 0 */ -#define CE0CTL1 (HWREG16(0x40003402)) /*!< Comparator Control Register 1 */ -#define CE0CTL2 (HWREG16(0x40003404)) /*!< Comparator Control Register 2 */ -#define CE0CTL3 (HWREG16(0x40003406)) /*!< Comparator Control Register 3 */ -#define CE0INT (HWREG16(0x4000340C)) /*!< Comparator Interrupt Control Register */ -#define CE0IV (HWREG16(0x4000340E)) /*!< Comparator Interrupt Vector Word Register */ - -/* Register offsets from COMP_E0_BASE address */ -#define OFS_CE0CTL0 (0x0000) /*!< Comparator Control Register 0 */ -#define OFS_CE0CTL1 (0x0002) /*!< Comparator Control Register 1 */ -#define OFS_CE0CTL2 (0x0004) /*!< Comparator Control Register 2 */ -#define OFS_CE0CTL3 (0x0006) /*!< Comparator Control Register 3 */ -#define OFS_CE0INT (0x000C) /*!< Comparator Interrupt Control Register */ -#define OFS_CE0IV (0x000E) /*!< Comparator Interrupt Vector Word Register */ - - -/****************************************************************************** -* COMP_E1 Registers -******************************************************************************/ -#define CE1CTL0 (HWREG16(0x40003800)) /*!< Comparator Control Register 0 */ -#define CE1CTL1 (HWREG16(0x40003802)) /*!< Comparator Control Register 1 */ -#define CE1CTL2 (HWREG16(0x40003804)) /*!< Comparator Control Register 2 */ -#define CE1CTL3 (HWREG16(0x40003806)) /*!< Comparator Control Register 3 */ -#define CE1INT (HWREG16(0x4000380C)) /*!< Comparator Interrupt Control Register */ -#define CE1IV (HWREG16(0x4000380E)) /*!< Comparator Interrupt Vector Word Register */ - -/* Register offsets from COMP_E1_BASE address */ -#define OFS_CE1CTL0 (0x0000) /*!< Comparator Control Register 0 */ -#define OFS_CE1CTL1 (0x0002) /*!< Comparator Control Register 1 */ -#define OFS_CE1CTL2 (0x0004) /*!< Comparator Control Register 2 */ -#define OFS_CE1CTL3 (0x0006) /*!< Comparator Control Register 3 */ -#define OFS_CE1INT (0x000C) /*!< Comparator Interrupt Control Register */ -#define OFS_CE1IV (0x000E) /*!< Comparator Interrupt Vector Word Register */ - - -/****************************************************************************** -* CRC32 Registers -******************************************************************************/ -#define CRC32DI (HWREG16(0x40004000)) /*!< Data Input for CRC32 Signature Computation */ -#define CRC32DIRB (HWREG16(0x40004004)) /*!< Data In Reverse for CRC32 Computation */ -#define CRC32INIRES_LO (HWREG16(0x40004008)) /*!< CRC32 Initialization and Result, lower 16 bits */ -#define CRC32INIRES_HI (HWREG16(0x4000400A)) /*!< CRC32 Initialization and Result, upper 16 bits */ -#define CRC32RESR_LO (HWREG16(0x4000400C)) /*!< CRC32 Result Reverse, lower 16 bits */ -#define CRC32RESR_HI (HWREG16(0x4000400E)) /*!< CRC32 Result Reverse, Upper 16 bits */ -#define CRC16DI (HWREG16(0x40004010)) /*!< Data Input for CRC16 computation */ -#define CRC16DIRB (HWREG16(0x40004014)) /*!< CRC16 Data In Reverse */ -#define CRC16INIRES (HWREG16(0x40004018)) /*!< CRC16 Initialization and Result register */ -#define CRC16RESR (HWREG16(0x4000401E)) /*!< CRC16 Result Reverse */ - -/* Register offsets from CRC32_BASE address */ -#define OFS_CRC32DI (0x0000) /*!< Data Input for CRC32 Signature Computation */ -#define OFS_CRC32DIRB (0x0004) /*!< Data In Reverse for CRC32 Computation */ -#define OFS_CRC32INIRES_LO (0x0008) /*!< CRC32 Initialization and Result, lower 16 bits */ -#define OFS_CRC32INIRES_HI (0x000A) /*!< CRC32 Initialization and Result, upper 16 bits */ -#define OFS_CRC32RESR_LO (0x000C) /*!< CRC32 Result Reverse, lower 16 bits */ -#define OFS_CRC32RESR_HI (0x000E) /*!< CRC32 Result Reverse, Upper 16 bits */ -#define OFS_CRC16DI (0x0010) /*!< Data Input for CRC16 computation */ -#define OFS_CRC16DIRB (0x0014) /*!< CRC16 Data In Reverse */ -#define OFS_CRC16INIRES (0x0018) /*!< CRC16 Initialization and Result register */ -#define OFS_CRC16RESR (0x001E) /*!< CRC16 Result Reverse */ - - -/****************************************************************************** -* DIO Registers -******************************************************************************/ -#define PAIN (HWREG16(0x40004C00)) /*!< Port A Input */ -#define PAOUT (HWREG16(0x40004C02)) /*!< Port A Output */ -#define PADIR (HWREG16(0x40004C04)) /*!< Port A Direction */ -#define PAREN (HWREG16(0x40004C06)) /*!< Port A Resistor Enable */ -#define PADS (HWREG16(0x40004C08)) /*!< Port A Drive Strength */ -#define PASEL0 (HWREG16(0x40004C0A)) /*!< Port A Select 0 */ -#define PASEL1 (HWREG16(0x40004C0C)) /*!< Port A Select 1 */ -#define P1IV (HWREG16(0x40004C0E)) /*!< Port 1 Interrupt Vector Register */ -#define PASELC (HWREG16(0x40004C16)) /*!< Port A Complement Select */ -#define PAIES (HWREG16(0x40004C18)) /*!< Port A Interrupt Edge Select */ -#define PAIE (HWREG16(0x40004C1A)) /*!< Port A Interrupt Enable */ -#define PAIFG (HWREG16(0x40004C1C)) /*!< Port A Interrupt Flag */ -#define P2IV (HWREG16(0x40004C1E)) /*!< Port 2 Interrupt Vector Register */ -#define PBIN (HWREG16(0x40004C20)) /*!< Port B Input */ -#define PBOUT (HWREG16(0x40004C22)) /*!< Port B Output */ -#define PBDIR (HWREG16(0x40004C24)) /*!< Port B Direction */ -#define PBREN (HWREG16(0x40004C26)) /*!< Port B Resistor Enable */ -#define PBDS (HWREG16(0x40004C28)) /*!< Port B Drive Strength */ -#define PBSEL0 (HWREG16(0x40004C2A)) /*!< Port B Select 0 */ -#define PBSEL1 (HWREG16(0x40004C2C)) /*!< Port B Select 1 */ -#define P3IV (HWREG16(0x40004C2E)) /*!< Port 3 Interrupt Vector Register */ -#define PBSELC (HWREG16(0x40004C36)) /*!< Port B Complement Select */ -#define PBIES (HWREG16(0x40004C38)) /*!< Port B Interrupt Edge Select */ -#define PBIE (HWREG16(0x40004C3A)) /*!< Port B Interrupt Enable */ -#define PBIFG (HWREG16(0x40004C3C)) /*!< Port B Interrupt Flag */ -#define P4IV (HWREG16(0x40004C3E)) /*!< Port 4 Interrupt Vector Register */ -#define PCIN (HWREG16(0x40004C40)) /*!< Port C Input */ -#define PCOUT (HWREG16(0x40004C42)) /*!< Port C Output */ -#define PCDIR (HWREG16(0x40004C44)) /*!< Port C Direction */ -#define PCREN (HWREG16(0x40004C46)) /*!< Port C Resistor Enable */ -#define PCDS (HWREG16(0x40004C48)) /*!< Port C Drive Strength */ -#define PCSEL0 (HWREG16(0x40004C4A)) /*!< Port C Select 0 */ -#define PCSEL1 (HWREG16(0x40004C4C)) /*!< Port C Select 1 */ -#define P5IV (HWREG16(0x40004C4E)) /*!< Port 5 Interrupt Vector Register */ -#define PCSELC (HWREG16(0x40004C56)) /*!< Port C Complement Select */ -#define PCIES (HWREG16(0x40004C58)) /*!< Port C Interrupt Edge Select */ -#define PCIE (HWREG16(0x40004C5A)) /*!< Port C Interrupt Enable */ -#define PCIFG (HWREG16(0x40004C5C)) /*!< Port C Interrupt Flag */ -#define P6IV (HWREG16(0x40004C5E)) /*!< Port 6 Interrupt Vector Register */ -#define PDIN (HWREG16(0x40004C60)) /*!< Port D Input */ -#define PDOUT (HWREG16(0x40004C62)) /*!< Port D Output */ -#define PDDIR (HWREG16(0x40004C64)) /*!< Port D Direction */ -#define PDREN (HWREG16(0x40004C66)) /*!< Port D Resistor Enable */ -#define PDDS (HWREG16(0x40004C68)) /*!< Port D Drive Strength */ -#define PDSEL0 (HWREG16(0x40004C6A)) /*!< Port D Select 0 */ -#define PDSEL1 (HWREG16(0x40004C6C)) /*!< Port D Select 1 */ -#define P7IV (HWREG16(0x40004C6E)) /*!< Port 7 Interrupt Vector Register */ -#define PDSELC (HWREG16(0x40004C76)) /*!< Port D Complement Select */ -#define PDIES (HWREG16(0x40004C78)) /*!< Port D Interrupt Edge Select */ -#define PDIE (HWREG16(0x40004C7A)) /*!< Port D Interrupt Enable */ -#define PDIFG (HWREG16(0x40004C7C)) /*!< Port D Interrupt Flag */ -#define P8IV (HWREG16(0x40004C7E)) /*!< Port 8 Interrupt Vector Register */ -#define PEIN (HWREG16(0x40004C80)) /*!< Port E Input */ -#define PEOUT (HWREG16(0x40004C82)) /*!< Port E Output */ -#define PEDIR (HWREG16(0x40004C84)) /*!< Port E Direction */ -#define PEREN (HWREG16(0x40004C86)) /*!< Port E Resistor Enable */ -#define PEDS (HWREG16(0x40004C88)) /*!< Port E Drive Strength */ -#define PESEL0 (HWREG16(0x40004C8A)) /*!< Port E Select 0 */ -#define PESEL1 (HWREG16(0x40004C8C)) /*!< Port E Select 1 */ -#define P9IV (HWREG16(0x40004C8E)) /*!< Port 9 Interrupt Vector Register */ -#define PESELC (HWREG16(0x40004C96)) /*!< Port E Complement Select */ -#define PEIES (HWREG16(0x40004C98)) /*!< Port E Interrupt Edge Select */ -#define PEIE (HWREG16(0x40004C9A)) /*!< Port E Interrupt Enable */ -#define PEIFG (HWREG16(0x40004C9C)) /*!< Port E Interrupt Flag */ -#define P10IV (HWREG16(0x40004C9E)) /*!< Port 10 Interrupt Vector Register */ -#define PJIN (HWREG16(0x40004D20)) /*!< Port J Input */ -#define PJOUT (HWREG16(0x40004D22)) /*!< Port J Output */ -#define PJDIR (HWREG16(0x40004D24)) /*!< Port J Direction */ -#define PJREN (HWREG16(0x40004D26)) /*!< Port J Resistor Enable */ -#define PJDS (HWREG16(0x40004D28)) /*!< Port J Drive Strength */ -#define PJSEL0 (HWREG16(0x40004D2A)) /*!< Port J Select 0 */ -#define PJSEL1 (HWREG16(0x40004D2C)) /*!< Port J Select 1 */ -#define PJSELC (HWREG16(0x40004D36)) /*!< Port J Complement Select */ -#define P1IN (HWREG8(0x40004C00)) /*!< Port 1 Input */ -#define P2IN (HWREG8(0x40004C01)) /*!< Port 2 Input */ -#define P2OUT (HWREG8(0x40004C03)) /*!< Port 2 Output */ -#define P1OUT (HWREG8(0x40004C02)) /*!< Port 1 Output */ -#define P1DIR (HWREG8(0x40004C04)) /*!< Port 1 Direction */ -#define P2DIR (HWREG8(0x40004C05)) /*!< Port 2 Direction */ -#define P1REN (HWREG8(0x40004C06)) /*!< Port 1 Resistor Enable */ -#define P2REN (HWREG8(0x40004C07)) /*!< Port 2 Resistor Enable */ -#define P1DS (HWREG8(0x40004C08)) /*!< Port 1 Drive Strength */ -#define P2DS (HWREG8(0x40004C09)) /*!< Port 2 Drive Strength */ -#define P1SEL0 (HWREG8(0x40004C0A)) /*!< Port 1 Select 0 */ -#define P2SEL0 (HWREG8(0x40004C0B)) /*!< Port 2 Select 0 */ -#define P1SEL1 (HWREG8(0x40004C0C)) /*!< Port 1 Select 1 */ -#define P2SEL1 (HWREG8(0x40004C0D)) /*!< Port 2 Select 1 */ -#define P1SELC (HWREG8(0x40004C16)) /*!< Port 1 Complement Select */ -#define P2SELC (HWREG8(0x40004C17)) /*!< Port 2 Complement Select */ -#define P1IES (HWREG8(0x40004C18)) /*!< Port 1 Interrupt Edge Select */ -#define P2IES (HWREG8(0x40004C19)) /*!< Port 2 Interrupt Edge Select */ -#define P1IE (HWREG8(0x40004C1A)) /*!< Port 1 Interrupt Enable */ -#define P2IE (HWREG8(0x40004C1B)) /*!< Port 2 Interrupt Enable */ -#define P1IFG (HWREG8(0x40004C1C)) /*!< Port 1 Interrupt Flag */ -#define P2IFG (HWREG8(0x40004C1D)) /*!< Port 2 Interrupt Flag */ -#define P3IN (HWREG8(0x40004C20)) /*!< Port 3 Input */ -#define P4IN (HWREG8(0x40004C21)) /*!< Port 4 Input */ -#define P3OUT (HWREG8(0x40004C22)) /*!< Port 3 Output */ -#define P4OUT (HWREG8(0x40004C23)) /*!< Port 4 Output */ -#define P3DIR (HWREG8(0x40004C24)) /*!< Port 3 Direction */ -#define P4DIR (HWREG8(0x40004C25)) /*!< Port 4 Direction */ -#define P3REN (HWREG8(0x40004C26)) /*!< Port 3 Resistor Enable */ -#define P4REN (HWREG8(0x40004C27)) /*!< Port 4 Resistor Enable */ -#define P3DS (HWREG8(0x40004C28)) /*!< Port 3 Drive Strength */ -#define P4DS (HWREG8(0x40004C29)) /*!< Port 4 Drive Strength */ -#define P4SEL0 (HWREG8(0x40004C2B)) /*!< Port 4 Select 0 */ -#define P3SEL0 (HWREG8(0x40004C2A)) /*!< Port 3 Select 0 */ -#define P3SEL1 (HWREG8(0x40004C2C)) /*!< Port 3 Select 1 */ -#define P4SEL1 (HWREG8(0x40004C2D)) /*!< Port 4 Select 1 */ -#define P3SELC (HWREG8(0x40004C36)) /*!< Port 3 Complement Select */ -#define P4SELC (HWREG8(0x40004C37)) /*!< Port 4 Complement Select */ -#define P3IES (HWREG8(0x40004C38)) /*!< Port 3 Interrupt Edge Select */ -#define P4IES (HWREG8(0x40004C39)) /*!< Port 4 Interrupt Edge Select */ -#define P3IE (HWREG8(0x40004C3A)) /*!< Port 3 Interrupt Enable */ -#define P4IE (HWREG8(0x40004C3B)) /*!< Port 4 Interrupt Enable */ -#define P3IFG (HWREG8(0x40004C3C)) /*!< Port 3 Interrupt Flag */ -#define P4IFG (HWREG8(0x40004C3D)) /*!< Port 4 Interrupt Flag */ -#define P5IN (HWREG8(0x40004C40)) /*!< Port 5 Input */ -#define P6IN (HWREG8(0x40004C41)) /*!< Port 6 Input */ -#define P5OUT (HWREG8(0x40004C42)) /*!< Port 5 Output */ -#define P6OUT (HWREG8(0x40004C43)) /*!< Port 6 Output */ -#define P5DIR (HWREG8(0x40004C44)) /*!< Port 5 Direction */ -#define P6DIR (HWREG8(0x40004C45)) /*!< Port 6 Direction */ -#define P5REN (HWREG8(0x40004C46)) /*!< Port 5 Resistor Enable */ -#define P6REN (HWREG8(0x40004C47)) /*!< Port 6 Resistor Enable */ -#define P5DS (HWREG8(0x40004C48)) /*!< Port 5 Drive Strength */ -#define P6DS (HWREG8(0x40004C49)) /*!< Port 6 Drive Strength */ -#define P5SEL0 (HWREG8(0x40004C4A)) /*!< Port 5 Select 0 */ -#define P6SEL0 (HWREG8(0x40004C4B)) /*!< Port 6 Select 0 */ -#define P5SEL1 (HWREG8(0x40004C4C)) /*!< Port 5 Select 1 */ -#define P6SEL1 (HWREG8(0x40004C4D)) /*!< Port 6 Select 1 */ -#define P5SELC (HWREG8(0x40004C56)) /*!< Port 5 Complement Select */ -#define P6SELC (HWREG8(0x40004C57)) /*!< Port 6 Complement Select */ -#define P5IES (HWREG8(0x40004C58)) /*!< Port 5 Interrupt Edge Select */ -#define P6IES (HWREG8(0x40004C59)) /*!< Port 6 Interrupt Edge Select */ -#define P5IE (HWREG8(0x40004C5A)) /*!< Port 5 Interrupt Enable */ -#define P6IE (HWREG8(0x40004C5B)) /*!< Port 6 Interrupt Enable */ -#define P5IFG (HWREG8(0x40004C5C)) /*!< Port 5 Interrupt Flag */ -#define P6IFG (HWREG8(0x40004C5D)) /*!< Port 6 Interrupt Flag */ -#define P7IN (HWREG8(0x40004C60)) /*!< Port 7 Input */ -#define P8IN (HWREG8(0x40004C61)) /*!< Port 8 Input */ -#define P7OUT (HWREG8(0x40004C62)) /*!< Port 7 Output */ -#define P8OUT (HWREG8(0x40004C63)) /*!< Port 8 Output */ -#define P7DIR (HWREG8(0x40004C64)) /*!< Port 7 Direction */ -#define P8DIR (HWREG8(0x40004C65)) /*!< Port 8 Direction */ -#define P7REN (HWREG8(0x40004C66)) /*!< Port 7 Resistor Enable */ -#define P8REN (HWREG8(0x40004C67)) /*!< Port 8 Resistor Enable */ -#define P7DS (HWREG8(0x40004C68)) /*!< Port 7 Drive Strength */ -#define P8DS (HWREG8(0x40004C69)) /*!< Port 8 Drive Strength */ -#define P7SEL0 (HWREG8(0x40004C6A)) /*!< Port 7 Select 0 */ -#define P8SEL0 (HWREG8(0x40004C6B)) /*!< Port 8 Select 0 */ -#define P7SEL1 (HWREG8(0x40004C6C)) /*!< Port 7 Select 1 */ -#define P8SEL1 (HWREG8(0x40004C6D)) /*!< Port 8 Select 1 */ -#define P7SELC (HWREG8(0x40004C76)) /*!< Port 7 Complement Select */ -#define P8SELC (HWREG8(0x40004C77)) /*!< Port 8 Complement Select */ -#define P7IES (HWREG8(0x40004C78)) /*!< Port 7 Interrupt Edge Select */ -#define P8IES (HWREG8(0x40004C79)) /*!< Port 8 Interrupt Edge Select */ -#define P7IE (HWREG8(0x40004C7A)) /*!< Port 7 Interrupt Enable */ -#define P8IE (HWREG8(0x40004C7B)) /*!< Port 8 Interrupt Enable */ -#define P7IFG (HWREG8(0x40004C7C)) /*!< Port 7 Interrupt Flag */ -#define P8IFG (HWREG8(0x40004C7D)) /*!< Port 8 Interrupt Flag */ -#define P9IN (HWREG8(0x40004C80)) /*!< Port 9 Input */ -#define P10IN (HWREG8(0x40004C81)) /*!< Port 10 Input */ -#define P9OUT (HWREG8(0x40004C82)) /*!< Port 9 Output */ -#define P10OUT (HWREG8(0x40004C83)) /*!< Port 10 Output */ -#define P9DIR (HWREG8(0x40004C84)) /*!< Port 9 Direction */ -#define P10DIR (HWREG8(0x40004C85)) /*!< Port 10 Direction */ -#define P9REN (HWREG8(0x40004C86)) /*!< Port 9 Resistor Enable */ -#define P10REN (HWREG8(0x40004C87)) /*!< Port 10 Resistor Enable */ -#define P9DS (HWREG8(0x40004C88)) /*!< Port 9 Drive Strength */ -#define P10DS (HWREG8(0x40004C89)) /*!< Port 10 Drive Strength */ -#define P9SEL0 (HWREG8(0x40004C8A)) /*!< Port 9 Select 0 */ -#define P10SEL0 (HWREG8(0x40004C8B)) /*!< Port 10 Select 0 */ -#define P9SEL1 (HWREG8(0x40004C8C)) /*!< Port 9 Select 1 */ -#define P10SEL1 (HWREG8(0x40004C8D)) /*!< Port 10 Select 1 */ -#define P9SELC (HWREG8(0x40004C96)) /*!< Port 9 Complement Select */ -#define P10SELC (HWREG8(0x40004C97)) /*!< Port 10 Complement Select */ -#define P9IES (HWREG8(0x40004C98)) /*!< Port 9 Interrupt Edge Select */ -#define P10IES (HWREG8(0x40004C99)) /*!< Port 10 Interrupt Edge Select */ -#define P9IE (HWREG8(0x40004C9A)) /*!< Port 9 Interrupt Enable */ -#define P10IE (HWREG8(0x40004C9B)) /*!< Port 10 Interrupt Enable */ -#define P9IFG (HWREG8(0x40004C9C)) /*!< Port 9 Interrupt Flag */ -#define P10IFG (HWREG8(0x40004C9D)) /*!< Port 10 Interrupt Flag */ - -/* Register offsets from DIO_BASE address */ -#define OFS_PAIN (0x0000) /*!< Port A Input */ -#define OFS_PAOUT (0x0002) /*!< Port A Output */ -#define OFS_PADIR (0x0004) /*!< Port A Direction */ -#define OFS_PAREN (0x0006) /*!< Port A Resistor Enable */ -#define OFS_PADS (0x0008) /*!< Port A Drive Strength */ -#define OFS_PASEL0 (0x000A) /*!< Port A Select 0 */ -#define OFS_PASEL1 (0x000C) /*!< Port A Select 1 */ -#define OFS_P1IV (0x000E) /*!< Port 1 Interrupt Vector Register */ -#define OFS_PASELC (0x0016) /*!< Port A Complement Select */ -#define OFS_PAIES (0x0018) /*!< Port A Interrupt Edge Select */ -#define OFS_PAIE (0x001A) /*!< Port A Interrupt Enable */ -#define OFS_PAIFG (0x001C) /*!< Port A Interrupt Flag */ -#define OFS_P2IV (0x001E) /*!< Port 2 Interrupt Vector Register */ -#define OFS_PBIN (0x0020) /*!< Port B Input */ -#define OFS_PBOUT (0x0022) /*!< Port B Output */ -#define OFS_PBDIR (0x0024) /*!< Port B Direction */ -#define OFS_PBREN (0x0026) /*!< Port B Resistor Enable */ -#define OFS_PBDS (0x0028) /*!< Port B Drive Strength */ -#define OFS_PBSEL0 (0x002A) /*!< Port B Select 0 */ -#define OFS_PBSEL1 (0x002C) /*!< Port B Select 1 */ -#define OFS_P3IV (0x002E) /*!< Port 3 Interrupt Vector Register */ -#define OFS_PBSELC (0x0036) /*!< Port B Complement Select */ -#define OFS_PBIES (0x0038) /*!< Port B Interrupt Edge Select */ -#define OFS_PBIE (0x003A) /*!< Port B Interrupt Enable */ -#define OFS_PBIFG (0x003C) /*!< Port B Interrupt Flag */ -#define OFS_P4IV (0x003E) /*!< Port 4 Interrupt Vector Register */ -#define OFS_PCIN (0x0040) /*!< Port C Input */ -#define OFS_PCOUT (0x0042) /*!< Port C Output */ -#define OFS_PCDIR (0x0044) /*!< Port C Direction */ -#define OFS_PCREN (0x0046) /*!< Port C Resistor Enable */ -#define OFS_PCDS (0x0048) /*!< Port C Drive Strength */ -#define OFS_PCSEL0 (0x004A) /*!< Port C Select 0 */ -#define OFS_PCSEL1 (0x004C) /*!< Port C Select 1 */ -#define OFS_P5IV (0x004E) /*!< Port 5 Interrupt Vector Register */ -#define OFS_PCSELC (0x0056) /*!< Port C Complement Select */ -#define OFS_PCIES (0x0058) /*!< Port C Interrupt Edge Select */ -#define OFS_PCIE (0x005A) /*!< Port C Interrupt Enable */ -#define OFS_PCIFG (0x005C) /*!< Port C Interrupt Flag */ -#define OFS_P6IV (0x005E) /*!< Port 6 Interrupt Vector Register */ -#define OFS_PDIN (0x0060) /*!< Port D Input */ -#define OFS_PDOUT (0x0062) /*!< Port D Output */ -#define OFS_PDDIR (0x0064) /*!< Port D Direction */ -#define OFS_PDREN (0x0066) /*!< Port D Resistor Enable */ -#define OFS_PDDS (0x0068) /*!< Port D Drive Strength */ -#define OFS_PDSEL0 (0x006A) /*!< Port D Select 0 */ -#define OFS_PDSEL1 (0x006C) /*!< Port D Select 1 */ -#define OFS_P7IV (0x006E) /*!< Port 7 Interrupt Vector Register */ -#define OFS_PDSELC (0x0076) /*!< Port D Complement Select */ -#define OFS_PDIES (0x0078) /*!< Port D Interrupt Edge Select */ -#define OFS_PDIE (0x007A) /*!< Port D Interrupt Enable */ -#define OFS_PDIFG (0x007C) /*!< Port D Interrupt Flag */ -#define OFS_P8IV (0x007E) /*!< Port 8 Interrupt Vector Register */ -#define OFS_PEIN (0x0080) /*!< Port E Input */ -#define OFS_PEOUT (0x0082) /*!< Port E Output */ -#define OFS_PEDIR (0x0084) /*!< Port E Direction */ -#define OFS_PEREN (0x0086) /*!< Port E Resistor Enable */ -#define OFS_PEDS (0x0088) /*!< Port E Drive Strength */ -#define OFS_PESEL0 (0x008A) /*!< Port E Select 0 */ -#define OFS_PESEL1 (0x008C) /*!< Port E Select 1 */ -#define OFS_P9IV (0x008E) /*!< Port 9 Interrupt Vector Register */ -#define OFS_PESELC (0x0096) /*!< Port E Complement Select */ -#define OFS_PEIES (0x0098) /*!< Port E Interrupt Edge Select */ -#define OFS_PEIE (0x009A) /*!< Port E Interrupt Enable */ -#define OFS_PEIFG (0x009C) /*!< Port E Interrupt Flag */ -#define OFS_P10IV (0x009E) /*!< Port 10 Interrupt Vector Register */ -#define OFS_PJIN (0x0120) /*!< Port J Input */ -#define OFS_PJOUT (0x0122) /*!< Port J Output */ -#define OFS_PJDIR (0x0124) /*!< Port J Direction */ -#define OFS_PJREN (0x0126) /*!< Port J Resistor Enable */ -#define OFS_PJDS (0x0128) /*!< Port J Drive Strength */ -#define OFS_PJSEL0 (0x012A) /*!< Port J Select 0 */ -#define OFS_PJSEL1 (0x012C) /*!< Port J Select 1 */ -#define OFS_PJSELC (0x0136) /*!< Port J Complement Select */ -#define OFS_P1IN (0x0000) /*!< Port 1 Input */ -#define OFS_P2IN (0x0001) /*!< Port 2 Input */ -#define OFS_P2OUT (0x0003) /*!< Port 2 Output */ -#define OFS_P1OUT (0x0002) /*!< Port 1 Output */ -#define OFS_P1DIR (0x0004) /*!< Port 1 Direction */ -#define OFS_P2DIR (0x0005) /*!< Port 2 Direction */ -#define OFS_P1REN (0x0006) /*!< Port 1 Resistor Enable */ -#define OFS_P2REN (0x0007) /*!< Port 2 Resistor Enable */ -#define OFS_P1DS (0x0008) /*!< Port 1 Drive Strength */ -#define OFS_P2DS (0x0009) /*!< Port 2 Drive Strength */ -#define OFS_P1SEL0 (0x000A) /*!< Port 1 Select 0 */ -#define OFS_P2SEL0 (0x000B) /*!< Port 2 Select 0 */ -#define OFS_P1SEL1 (0x000C) /*!< Port 1 Select 1 */ -#define OFS_P2SEL1 (0x000D) /*!< Port 2 Select 1 */ -#define OFS_P1SELC (0x0016) /*!< Port 1 Complement Select */ -#define OFS_P2SELC (0x0017) /*!< Port 2 Complement Select */ -#define OFS_P1IES (0x0018) /*!< Port 1 Interrupt Edge Select */ -#define OFS_P2IES (0x0019) /*!< Port 2 Interrupt Edge Select */ -#define OFS_P1IE (0x001A) /*!< Port 1 Interrupt Enable */ -#define OFS_P2IE (0x001B) /*!< Port 2 Interrupt Enable */ -#define OFS_P1IFG (0x001C) /*!< Port 1 Interrupt Flag */ -#define OFS_P2IFG (0x001D) /*!< Port 2 Interrupt Flag */ -#define OFS_P3IN (0x0020) /*!< Port 3 Input */ -#define OFS_P4IN (0x0021) /*!< Port 4 Input */ -#define OFS_P3OUT (0x0022) /*!< Port 3 Output */ -#define OFS_P4OUT (0x0023) /*!< Port 4 Output */ -#define OFS_P3DIR (0x0024) /*!< Port 3 Direction */ -#define OFS_P4DIR (0x0025) /*!< Port 4 Direction */ -#define OFS_P3REN (0x0026) /*!< Port 3 Resistor Enable */ -#define OFS_P4REN (0x0027) /*!< Port 4 Resistor Enable */ -#define OFS_P3DS (0x0028) /*!< Port 3 Drive Strength */ -#define OFS_P4DS (0x0029) /*!< Port 4 Drive Strength */ -#define OFS_P4SEL0 (0x002B) /*!< Port 4 Select 0 */ -#define OFS_P3SEL0 (0x002A) /*!< Port 3 Select 0 */ -#define OFS_P3SEL1 (0x002C) /*!< Port 3 Select 1 */ -#define OFS_P4SEL1 (0x002D) /*!< Port 4 Select 1 */ -#define OFS_P3SELC (0x0036) /*!< Port 3 Complement Select */ -#define OFS_P4SELC (0x0037) /*!< Port 4 Complement Select */ -#define OFS_P3IES (0x0038) /*!< Port 3 Interrupt Edge Select */ -#define OFS_P4IES (0x0039) /*!< Port 4 Interrupt Edge Select */ -#define OFS_P3IE (0x003A) /*!< Port 3 Interrupt Enable */ -#define OFS_P4IE (0x003B) /*!< Port 4 Interrupt Enable */ -#define OFS_P3IFG (0x003C) /*!< Port 3 Interrupt Flag */ -#define OFS_P4IFG (0x003D) /*!< Port 4 Interrupt Flag */ -#define OFS_P5IN (0x0040) /*!< Port 5 Input */ -#define OFS_P6IN (0x0041) /*!< Port 6 Input */ -#define OFS_P5OUT (0x0042) /*!< Port 5 Output */ -#define OFS_P6OUT (0x0043) /*!< Port 6 Output */ -#define OFS_P5DIR (0x0044) /*!< Port 5 Direction */ -#define OFS_P6DIR (0x0045) /*!< Port 6 Direction */ -#define OFS_P5REN (0x0046) /*!< Port 5 Resistor Enable */ -#define OFS_P6REN (0x0047) /*!< Port 6 Resistor Enable */ -#define OFS_P5DS (0x0048) /*!< Port 5 Drive Strength */ -#define OFS_P6DS (0x0049) /*!< Port 6 Drive Strength */ -#define OFS_P5SEL0 (0x004A) /*!< Port 5 Select 0 */ -#define OFS_P6SEL0 (0x004B) /*!< Port 6 Select 0 */ -#define OFS_P5SEL1 (0x004C) /*!< Port 5 Select 1 */ -#define OFS_P6SEL1 (0x004D) /*!< Port 6 Select 1 */ -#define OFS_P5SELC (0x0056) /*!< Port 5 Complement Select */ -#define OFS_P6SELC (0x0057) /*!< Port 6 Complement Select */ -#define OFS_P5IES (0x0058) /*!< Port 5 Interrupt Edge Select */ -#define OFS_P6IES (0x0059) /*!< Port 6 Interrupt Edge Select */ -#define OFS_P5IE (0x005A) /*!< Port 5 Interrupt Enable */ -#define OFS_P6IE (0x005B) /*!< Port 6 Interrupt Enable */ -#define OFS_P5IFG (0x005C) /*!< Port 5 Interrupt Flag */ -#define OFS_P6IFG (0x005D) /*!< Port 6 Interrupt Flag */ -#define OFS_P7IN (0x0060) /*!< Port 7 Input */ -#define OFS_P8IN (0x0061) /*!< Port 8 Input */ -#define OFS_P7OUT (0x0062) /*!< Port 7 Output */ -#define OFS_P8OUT (0x0063) /*!< Port 8 Output */ -#define OFS_P7DIR (0x0064) /*!< Port 7 Direction */ -#define OFS_P8DIR (0x0065) /*!< Port 8 Direction */ -#define OFS_P7REN (0x0066) /*!< Port 7 Resistor Enable */ -#define OFS_P8REN (0x0067) /*!< Port 8 Resistor Enable */ -#define OFS_P7DS (0x0068) /*!< Port 7 Drive Strength */ -#define OFS_P8DS (0x0069) /*!< Port 8 Drive Strength */ -#define OFS_P7SEL0 (0x006A) /*!< Port 7 Select 0 */ -#define OFS_P8SEL0 (0x006B) /*!< Port 8 Select 0 */ -#define OFS_P7SEL1 (0x006C) /*!< Port 7 Select 1 */ -#define OFS_P8SEL1 (0x006D) /*!< Port 8 Select 1 */ -#define OFS_P7SELC (0x0076) /*!< Port 7 Complement Select */ -#define OFS_P8SELC (0x0077) /*!< Port 8 Complement Select */ -#define OFS_P7IES (0x0078) /*!< Port 7 Interrupt Edge Select */ -#define OFS_P8IES (0x0079) /*!< Port 8 Interrupt Edge Select */ -#define OFS_P7IE (0x007A) /*!< Port 7 Interrupt Enable */ -#define OFS_P8IE (0x007B) /*!< Port 8 Interrupt Enable */ -#define OFS_P7IFG (0x007C) /*!< Port 7 Interrupt Flag */ -#define OFS_P8IFG (0x007D) /*!< Port 8 Interrupt Flag */ -#define OFS_P9IN (0x0080) /*!< Port 9 Input */ -#define OFS_P10IN (0x0081) /*!< Port 10 Input */ -#define OFS_P9OUT (0x0082) /*!< Port 9 Output */ -#define OFS_P10OUT (0x0083) /*!< Port 10 Output */ -#define OFS_P9DIR (0x0084) /*!< Port 9 Direction */ -#define OFS_P10DIR (0x0085) /*!< Port 10 Direction */ -#define OFS_P9REN (0x0086) /*!< Port 9 Resistor Enable */ -#define OFS_P10REN (0x0087) /*!< Port 10 Resistor Enable */ -#define OFS_P9DS (0x0088) /*!< Port 9 Drive Strength */ -#define OFS_P10DS (0x0089) /*!< Port 10 Drive Strength */ -#define OFS_P9SEL0 (0x008A) /*!< Port 9 Select 0 */ -#define OFS_P10SEL0 (0x008B) /*!< Port 10 Select 0 */ -#define OFS_P9SEL1 (0x008C) /*!< Port 9 Select 1 */ -#define OFS_P10SEL1 (0x008D) /*!< Port 10 Select 1 */ -#define OFS_P9SELC (0x0096) /*!< Port 9 Complement Select */ -#define OFS_P10SELC (0x0097) /*!< Port 10 Complement Select */ -#define OFS_P9IES (0x0098) /*!< Port 9 Interrupt Edge Select */ -#define OFS_P10IES (0x0099) /*!< Port 10 Interrupt Edge Select */ -#define OFS_P9IE (0x009A) /*!< Port 9 Interrupt Enable */ -#define OFS_P10IE (0x009B) /*!< Port 10 Interrupt Enable */ -#define OFS_P9IFG (0x009C) /*!< Port 9 Interrupt Flag */ -#define OFS_P10IFG (0x009D) /*!< Port 10 Interrupt Flag */ - - -/****************************************************************************** -* EUSCI_A0 Registers -******************************************************************************/ -#define UCA0CTLW0 (HWREG16(0x40001000)) /*!< eUSCI_Ax Control Word Register 0 */ -#define UCA0CTLW0_SPI (HWREG16(0x40001000)) -#define UCA0CTLW1 (HWREG16(0x40001002)) /*!< eUSCI_Ax Control Word Register 1 */ -#define UCA0BRW (HWREG16(0x40001006)) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define UCA0BRW_SPI (HWREG16(0x40001006)) -#define UCA0MCTLW (HWREG16(0x40001008)) /*!< eUSCI_Ax Modulation Control Word Register */ -#define UCA0STATW (HWREG16(0x4000100A)) /*!< eUSCI_Ax Status Register */ -#define UCA0STATW_SPI (HWREG16(0x4000100A)) -#define UCA0RXBUF (HWREG16(0x4000100C)) /*!< eUSCI_Ax Receive Buffer Register */ -#define UCA0RXBUF_SPI (HWREG16(0x4000100C)) -#define UCA0TXBUF (HWREG16(0x4000100E)) /*!< eUSCI_Ax Transmit Buffer Register */ -#define UCA0TXBUF_SPI (HWREG16(0x4000100E)) -#define UCA0ABCTL (HWREG16(0x40001010)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define UCA0IRCTL (HWREG16(0x40001012)) /*!< eUSCI_Ax IrDA Control Word Register */ -#define UCA0IE (HWREG16(0x4000101A)) /*!< eUSCI_Ax Interrupt Enable Register */ -#define UCA0IE_SPI (HWREG16(0x4000101A)) -#define UCA0IFG (HWREG16(0x4000101C)) /*!< eUSCI_Ax Interrupt Flag Register */ -#define UCA0IFG_SPI (HWREG16(0x4000101C)) -#define UCA0IV (HWREG16(0x4000101E)) /*!< eUSCI_Ax Interrupt Vector Register */ -#define UCA0IV_SPI (HWREG16(0x4000101E)) - -/* Register offsets from EUSCI_A0_BASE address */ -#define OFS_UCA0CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ -#define OFS_UCA0CTLW0_SPI (0x0000) -#define OFS_UCA0CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ -#define OFS_UCA0BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define OFS_UCA0BRW_SPI (0x0006) -#define OFS_UCA0MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ -#define OFS_UCA0STATW (0x000A) /*!< eUSCI_Ax Status Register */ -#define OFS_UCA0STATW_SPI (0x000A) -#define OFS_UCA0RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ -#define OFS_UCA0RXBUF_SPI (0x000C) -#define OFS_UCA0TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ -#define OFS_UCA0TXBUF_SPI (0x000E) -#define OFS_UCA0ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define OFS_UCA0IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ -#define OFS_UCA0IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ -#define OFS_UCA0IE_SPI (0x001A) -#define OFS_UCA0IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ -#define OFS_UCA0IFG_SPI (0x001C) -#define OFS_UCA0IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ -#define OFS_UCA0IV_SPI (0x001E) - -#define UCA0CTL0 (HWREG8_L(UCA0CTLW0)) /* eUSCI_Ax Control 0 */ -#define UCA0CTL1 (HWREG8_H(UCA0CTLW0)) /* eUSCI_Ax Control 1 */ -#define UCA0BR0 (HWREG8_L(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 0 */ -#define UCA0BR1 (HWREG8_H(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 1 */ -#define UCA0IRTCTL (HWREG8_L(UCA0IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ -#define UCA0IRRCTL (HWREG8_H(UCA0IRCTL)) /* eUSCI_Ax IrDA Receive Control */ - -/****************************************************************************** -* EUSCI_A1 Registers -******************************************************************************/ -#define UCA1CTLW0 (HWREG16(0x40001400)) /*!< eUSCI_Ax Control Word Register 0 */ -#define UCA1CTLW0_SPI (HWREG16(0x40001400)) -#define UCA1CTLW1 (HWREG16(0x40001402)) /*!< eUSCI_Ax Control Word Register 1 */ -#define UCA1BRW (HWREG16(0x40001406)) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define UCA1BRW_SPI (HWREG16(0x40001406)) -#define UCA1MCTLW (HWREG16(0x40001408)) /*!< eUSCI_Ax Modulation Control Word Register */ -#define UCA1STATW (HWREG16(0x4000140A)) /*!< eUSCI_Ax Status Register */ -#define UCA1STATW_SPI (HWREG16(0x4000140A)) -#define UCA1RXBUF (HWREG16(0x4000140C)) /*!< eUSCI_Ax Receive Buffer Register */ -#define UCA1RXBUF_SPI (HWREG16(0x4000140C)) -#define UCA1TXBUF (HWREG16(0x4000140E)) /*!< eUSCI_Ax Transmit Buffer Register */ -#define UCA1TXBUF_SPI (HWREG16(0x4000140E)) -#define UCA1ABCTL (HWREG16(0x40001410)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define UCA1IRCTL (HWREG16(0x40001412)) /*!< eUSCI_Ax IrDA Control Word Register */ -#define UCA1IE (HWREG16(0x4000141A)) /*!< eUSCI_Ax Interrupt Enable Register */ -#define UCA1IE_SPI (HWREG16(0x4000141A)) -#define UCA1IFG (HWREG16(0x4000141C)) /*!< eUSCI_Ax Interrupt Flag Register */ -#define UCA1IFG_SPI (HWREG16(0x4000141C)) -#define UCA1IV (HWREG16(0x4000141E)) /*!< eUSCI_Ax Interrupt Vector Register */ -#define UCA1IV_SPI (HWREG16(0x4000141E)) - -/* Register offsets from EUSCI_A1_BASE address */ -#define OFS_UCA1CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ -#define OFS_UCA1CTLW0_SPI (0x0000) -#define OFS_UCA1CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ -#define OFS_UCA1BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define OFS_UCA1BRW_SPI (0x0006) -#define OFS_UCA1MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ -#define OFS_UCA1STATW (0x000A) /*!< eUSCI_Ax Status Register */ -#define OFS_UCA1STATW_SPI (0x000A) -#define OFS_UCA1RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ -#define OFS_UCA1RXBUF_SPI (0x000C) -#define OFS_UCA1TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ -#define OFS_UCA1TXBUF_SPI (0x000E) -#define OFS_UCA1ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define OFS_UCA1IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ -#define OFS_UCA1IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ -#define OFS_UCA1IE_SPI (0x001A) -#define OFS_UCA1IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ -#define OFS_UCA1IFG_SPI (0x001C) -#define OFS_UCA1IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ -#define OFS_UCA1IV_SPI (0x001E) - -#define UCA1CTL0 (HWREG8_L(UCA1CTLW0)) /* eUSCI_Ax Control 0 */ -#define UCA1CTL1 (HWREG8_H(UCA1CTLW0)) /* eUSCI_Ax Control 1 */ -#define UCA1BR0 (HWREG8_L(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 0 */ -#define UCA1BR1 (HWREG8_H(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 1 */ -#define UCA1IRTCTL (HWREG8_L(UCA1IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ -#define UCA1IRRCTL (HWREG8_H(UCA1IRCTL)) /* eUSCI_Ax IrDA Receive Control */ - -/****************************************************************************** -* EUSCI_A2 Registers -******************************************************************************/ -#define UCA2CTLW0 (HWREG16(0x40001800)) /*!< eUSCI_Ax Control Word Register 0 */ -#define UCA2CTLW0_SPI (HWREG16(0x40001800)) -#define UCA2CTLW1 (HWREG16(0x40001802)) /*!< eUSCI_Ax Control Word Register 1 */ -#define UCA2BRW (HWREG16(0x40001806)) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define UCA2BRW_SPI (HWREG16(0x40001806)) -#define UCA2MCTLW (HWREG16(0x40001808)) /*!< eUSCI_Ax Modulation Control Word Register */ -#define UCA2STATW (HWREG16(0x4000180A)) /*!< eUSCI_Ax Status Register */ -#define UCA2STATW_SPI (HWREG16(0x4000180A)) -#define UCA2RXBUF (HWREG16(0x4000180C)) /*!< eUSCI_Ax Receive Buffer Register */ -#define UCA2RXBUF_SPI (HWREG16(0x4000180C)) -#define UCA2TXBUF (HWREG16(0x4000180E)) /*!< eUSCI_Ax Transmit Buffer Register */ -#define UCA2TXBUF_SPI (HWREG16(0x4000180E)) -#define UCA2ABCTL (HWREG16(0x40001810)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define UCA2IRCTL (HWREG16(0x40001812)) /*!< eUSCI_Ax IrDA Control Word Register */ -#define UCA2IE (HWREG16(0x4000181A)) /*!< eUSCI_Ax Interrupt Enable Register */ -#define UCA2IE_SPI (HWREG16(0x4000181A)) -#define UCA2IFG (HWREG16(0x4000181C)) /*!< eUSCI_Ax Interrupt Flag Register */ -#define UCA2IFG_SPI (HWREG16(0x4000181C)) -#define UCA2IV (HWREG16(0x4000181E)) /*!< eUSCI_Ax Interrupt Vector Register */ -#define UCA2IV_SPI (HWREG16(0x4000181E)) - -/* Register offsets from EUSCI_A2_BASE address */ -#define OFS_UCA2CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ -#define OFS_UCA2CTLW0_SPI (0x0000) -#define OFS_UCA2CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ -#define OFS_UCA2BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define OFS_UCA2BRW_SPI (0x0006) -#define OFS_UCA2MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ -#define OFS_UCA2STATW (0x000A) /*!< eUSCI_Ax Status Register */ -#define OFS_UCA2STATW_SPI (0x000A) -#define OFS_UCA2RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ -#define OFS_UCA2RXBUF_SPI (0x000C) -#define OFS_UCA2TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ -#define OFS_UCA2TXBUF_SPI (0x000E) -#define OFS_UCA2ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define OFS_UCA2IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ -#define OFS_UCA2IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ -#define OFS_UCA2IE_SPI (0x001A) -#define OFS_UCA2IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ -#define OFS_UCA2IFG_SPI (0x001C) -#define OFS_UCA2IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ -#define OFS_UCA2IV_SPI (0x001E) - -#define UCA2CTL0 (HWREG8_L(UCA2CTLW0)) /* eUSCI_Ax Control 0 */ -#define UCA2CTL1 (HWREG8_H(UCA2CTLW0)) /* eUSCI_Ax Control 1 */ -#define UCA2BR0 (HWREG8_L(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 0 */ -#define UCA2BR1 (HWREG8_H(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 1 */ -#define UCA2IRTCTL (HWREG8_L(UCA2IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ -#define UCA2IRRCTL (HWREG8_H(UCA2IRCTL)) /* eUSCI_Ax IrDA Receive Control */ - -/****************************************************************************** -* EUSCI_A3 Registers -******************************************************************************/ -#define UCA3CTLW0 (HWREG16(0x40001C00)) /*!< eUSCI_Ax Control Word Register 0 */ -#define UCA3CTLW0_SPI (HWREG16(0x40001C00)) -#define UCA3CTLW1 (HWREG16(0x40001C02)) /*!< eUSCI_Ax Control Word Register 1 */ -#define UCA3BRW (HWREG16(0x40001C06)) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define UCA3BRW_SPI (HWREG16(0x40001C06)) -#define UCA3MCTLW (HWREG16(0x40001C08)) /*!< eUSCI_Ax Modulation Control Word Register */ -#define UCA3STATW (HWREG16(0x40001C0A)) /*!< eUSCI_Ax Status Register */ -#define UCA3STATW_SPI (HWREG16(0x40001C0A)) -#define UCA3RXBUF (HWREG16(0x40001C0C)) /*!< eUSCI_Ax Receive Buffer Register */ -#define UCA3RXBUF_SPI (HWREG16(0x40001C0C)) -#define UCA3TXBUF (HWREG16(0x40001C0E)) /*!< eUSCI_Ax Transmit Buffer Register */ -#define UCA3TXBUF_SPI (HWREG16(0x40001C0E)) -#define UCA3ABCTL (HWREG16(0x40001C10)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define UCA3IRCTL (HWREG16(0x40001C12)) /*!< eUSCI_Ax IrDA Control Word Register */ -#define UCA3IE (HWREG16(0x40001C1A)) /*!< eUSCI_Ax Interrupt Enable Register */ -#define UCA3IE_SPI (HWREG16(0x40001C1A)) -#define UCA3IFG (HWREG16(0x40001C1C)) /*!< eUSCI_Ax Interrupt Flag Register */ -#define UCA3IFG_SPI (HWREG16(0x40001C1C)) -#define UCA3IV (HWREG16(0x40001C1E)) /*!< eUSCI_Ax Interrupt Vector Register */ -#define UCA3IV_SPI (HWREG16(0x40001C1E)) - -/* Register offsets from EUSCI_A3_BASE address */ -#define OFS_UCA3CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ -#define OFS_UCA3CTLW0_SPI (0x0000) -#define OFS_UCA3CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ -#define OFS_UCA3BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define OFS_UCA3BRW_SPI (0x0006) -#define OFS_UCA3MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ -#define OFS_UCA3STATW (0x000A) /*!< eUSCI_Ax Status Register */ -#define OFS_UCA3STATW_SPI (0x000A) -#define OFS_UCA3RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ -#define OFS_UCA3RXBUF_SPI (0x000C) -#define OFS_UCA3TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ -#define OFS_UCA3TXBUF_SPI (0x000E) -#define OFS_UCA3ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define OFS_UCA3IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ -#define OFS_UCA3IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ -#define OFS_UCA3IE_SPI (0x001A) -#define OFS_UCA3IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ -#define OFS_UCA3IFG_SPI (0x001C) -#define OFS_UCA3IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ -#define OFS_UCA3IV_SPI (0x001E) - -#define UCA3CTL0 (HWREG8_L(UCA3CTLW0)) /* eUSCI_Ax Control 0 */ -#define UCA3CTL1 (HWREG8_H(UCA3CTLW0)) /* eUSCI_Ax Control 1 */ -#define UCA3BR0 (HWREG8_L(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 0 */ -#define UCA3BR1 (HWREG8_H(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 1 */ -#define UCA3IRTCTL (HWREG8_L(UCA3IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ -#define UCA3IRRCTL (HWREG8_H(UCA3IRCTL)) /* eUSCI_Ax IrDA Receive Control */ - -/****************************************************************************** -* EUSCI_B0 Registers -******************************************************************************/ -#define UCB0CTLW0 (HWREG16(0x40002000)) /*!< eUSCI_Bx Control Word Register 0 */ -#define UCB0CTLW0_SPI (HWREG16(0x40002000)) -#define UCB0CTLW1 (HWREG16(0x40002002)) /*!< eUSCI_Bx Control Word Register 1 */ -#define UCB0BRW (HWREG16(0x40002006)) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define UCB0BRW_SPI (HWREG16(0x40002006)) -#define UCB0STATW (HWREG16(0x40002008)) /*!< eUSCI_Bx Status Register */ -#define UCB0STATW_SPI (HWREG16(0x40002008)) -#define UCB0TBCNT (HWREG16(0x4000200A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define UCB0RXBUF (HWREG16(0x4000200C)) /*!< eUSCI_Bx Receive Buffer Register */ -#define UCB0RXBUF_SPI (HWREG16(0x4000200C)) -#define UCB0TXBUF (HWREG16(0x4000200E)) /*!< eUSCI_Bx Transmit Buffer Register */ -#define UCB0TXBUF_SPI (HWREG16(0x4000200E)) -#define UCB0I2COA0 (HWREG16(0x40002014)) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define UCB0I2COA1 (HWREG16(0x40002016)) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define UCB0I2COA2 (HWREG16(0x40002018)) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define UCB0I2COA3 (HWREG16(0x4000201A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define UCB0ADDRX (HWREG16(0x4000201C)) /*!< eUSCI_Bx I2C Received Address Register */ -#define UCB0ADDMASK (HWREG16(0x4000201E)) /*!< eUSCI_Bx I2C Address Mask Register */ -#define UCB0I2CSA (HWREG16(0x40002020)) /*!< eUSCI_Bx I2C Slave Address Register */ -#define UCB0IE (HWREG16(0x4000202A)) /*!< eUSCI_Bx Interrupt Enable Register */ -#define UCB0IE_SPI (HWREG16(0x4000202A)) -#define UCB0IFG (HWREG16(0x4000202C)) /*!< eUSCI_Bx Interrupt Flag Register */ -#define UCB0IFG_SPI (HWREG16(0x4000202C)) -#define UCB0IV (HWREG16(0x4000202E)) /*!< eUSCI_Bx Interrupt Vector Register */ -#define UCB0IV_SPI (HWREG16(0x4000202E)) - -/* Register offsets from EUSCI_B0_BASE address */ -#define OFS_UCB0CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ -#define OFS_UCB0CTLW0_SPI (0x0000) -#define OFS_UCB0CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ -#define OFS_UCB0BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define OFS_UCB0BRW_SPI (0x0006) -#define OFS_UCB0STATW (0x0008) /*!< eUSCI_Bx Status Register */ -#define OFS_UCB0STATW_SPI (0x0008) -#define OFS_UCB0TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define OFS_UCB0RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ -#define OFS_UCB0RXBUF_SPI (0x000C) -#define OFS_UCB0TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ -#define OFS_UCB0TXBUF_SPI (0x000E) -#define OFS_UCB0I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define OFS_UCB0I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define OFS_UCB0I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define OFS_UCB0I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define OFS_UCB0ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ -#define OFS_UCB0ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ -#define OFS_UCB0I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ -#define OFS_UCB0IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ -#define OFS_UCB0IE_SPI (0x002A) -#define OFS_UCB0IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ -#define OFS_UCB0IFG_SPI (0x002C) -#define OFS_UCB0IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ -#define OFS_UCB0IV_SPI (0x002E) - -#define UCB0CTL0 (HWREG8_L(UCB0CTLW0)) /* eUSCI_Bx Control 1 */ -#define UCB0CTL1 (HWREG8_H(UCB0CTLW0)) /* eUSCI_Bx Control 0 */ -#define UCB0BR0 (HWREG8_L(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 0 */ -#define UCB0BR1 (HWREG8_H(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 1 */ -#define UCB0STAT (HWREG8_L(UCB0STATW)) /* eUSCI_Bx Status */ -#define UCB0BCNT (HWREG8_H(UCB0STATW)) /* eUSCI_Bx Byte Counter Register */ - -/****************************************************************************** -* EUSCI_B1 Registers -******************************************************************************/ -#define UCB1CTLW0 (HWREG16(0x40002400)) /*!< eUSCI_Bx Control Word Register 0 */ -#define UCB1CTLW0_SPI (HWREG16(0x40002400)) -#define UCB1CTLW1 (HWREG16(0x40002402)) /*!< eUSCI_Bx Control Word Register 1 */ -#define UCB1BRW (HWREG16(0x40002406)) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define UCB1BRW_SPI (HWREG16(0x40002406)) -#define UCB1STATW (HWREG16(0x40002408)) /*!< eUSCI_Bx Status Register */ -#define UCB1STATW_SPI (HWREG16(0x40002408)) -#define UCB1TBCNT (HWREG16(0x4000240A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define UCB1RXBUF (HWREG16(0x4000240C)) /*!< eUSCI_Bx Receive Buffer Register */ -#define UCB1RXBUF_SPI (HWREG16(0x4000240C)) -#define UCB1TXBUF (HWREG16(0x4000240E)) /*!< eUSCI_Bx Transmit Buffer Register */ -#define UCB1TXBUF_SPI (HWREG16(0x4000240E)) -#define UCB1I2COA0 (HWREG16(0x40002414)) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define UCB1I2COA1 (HWREG16(0x40002416)) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define UCB1I2COA2 (HWREG16(0x40002418)) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define UCB1I2COA3 (HWREG16(0x4000241A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define UCB1ADDRX (HWREG16(0x4000241C)) /*!< eUSCI_Bx I2C Received Address Register */ -#define UCB1ADDMASK (HWREG16(0x4000241E)) /*!< eUSCI_Bx I2C Address Mask Register */ -#define UCB1I2CSA (HWREG16(0x40002420)) /*!< eUSCI_Bx I2C Slave Address Register */ -#define UCB1IE (HWREG16(0x4000242A)) /*!< eUSCI_Bx Interrupt Enable Register */ -#define UCB1IE_SPI (HWREG16(0x4000242A)) -#define UCB1IFG (HWREG16(0x4000242C)) /*!< eUSCI_Bx Interrupt Flag Register */ -#define UCB1IFG_SPI (HWREG16(0x4000242C)) -#define UCB1IV (HWREG16(0x4000242E)) /*!< eUSCI_Bx Interrupt Vector Register */ -#define UCB1IV_SPI (HWREG16(0x4000242E)) - -/* Register offsets from EUSCI_B1_BASE address */ -#define OFS_UCB1CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ -#define OFS_UCB1CTLW0_SPI (0x0000) -#define OFS_UCB1CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ -#define OFS_UCB1BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define OFS_UCB1BRW_SPI (0x0006) -#define OFS_UCB1STATW (0x0008) /*!< eUSCI_Bx Status Register */ -#define OFS_UCB1STATW_SPI (0x0008) -#define OFS_UCB1TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define OFS_UCB1RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ -#define OFS_UCB1RXBUF_SPI (0x000C) -#define OFS_UCB1TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ -#define OFS_UCB1TXBUF_SPI (0x000E) -#define OFS_UCB1I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define OFS_UCB1I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define OFS_UCB1I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define OFS_UCB1I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define OFS_UCB1ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ -#define OFS_UCB1ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ -#define OFS_UCB1I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ -#define OFS_UCB1IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ -#define OFS_UCB1IE_SPI (0x002A) -#define OFS_UCB1IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ -#define OFS_UCB1IFG_SPI (0x002C) -#define OFS_UCB1IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ -#define OFS_UCB1IV_SPI (0x002E) - -#define UCB1CTL0 (HWREG8_L(UCB1CTLW0)) /* eUSCI_Bx Control 1 */ -#define UCB1CTL1 (HWREG8_H(UCB1CTLW0)) /* eUSCI_Bx Control 0 */ -#define UCB1BR0 (HWREG8_L(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 0 */ -#define UCB1BR1 (HWREG8_H(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 1 */ -#define UCB1STAT (HWREG8_L(UCB1STATW)) /* eUSCI_Bx Status */ -#define UCB1BCNT (HWREG8_H(UCB1STATW)) /* eUSCI_Bx Byte Counter Register */ - -/****************************************************************************** -* EUSCI_B2 Registers -******************************************************************************/ -#define UCB2CTLW0 (HWREG16(0x40002800)) /*!< eUSCI_Bx Control Word Register 0 */ -#define UCB2CTLW0_SPI (HWREG16(0x40002800)) -#define UCB2CTLW1 (HWREG16(0x40002802)) /*!< eUSCI_Bx Control Word Register 1 */ -#define UCB2BRW (HWREG16(0x40002806)) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define UCB2BRW_SPI (HWREG16(0x40002806)) -#define UCB2STATW (HWREG16(0x40002808)) /*!< eUSCI_Bx Status Register */ -#define UCB2STATW_SPI (HWREG16(0x40002808)) -#define UCB2TBCNT (HWREG16(0x4000280A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define UCB2RXBUF (HWREG16(0x4000280C)) /*!< eUSCI_Bx Receive Buffer Register */ -#define UCB2RXBUF_SPI (HWREG16(0x4000280C)) -#define UCB2TXBUF (HWREG16(0x4000280E)) /*!< eUSCI_Bx Transmit Buffer Register */ -#define UCB2TXBUF_SPI (HWREG16(0x4000280E)) -#define UCB2I2COA0 (HWREG16(0x40002814)) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define UCB2I2COA1 (HWREG16(0x40002816)) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define UCB2I2COA2 (HWREG16(0x40002818)) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define UCB2I2COA3 (HWREG16(0x4000281A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define UCB2ADDRX (HWREG16(0x4000281C)) /*!< eUSCI_Bx I2C Received Address Register */ -#define UCB2ADDMASK (HWREG16(0x4000281E)) /*!< eUSCI_Bx I2C Address Mask Register */ -#define UCB2I2CSA (HWREG16(0x40002820)) /*!< eUSCI_Bx I2C Slave Address Register */ -#define UCB2IE (HWREG16(0x4000282A)) /*!< eUSCI_Bx Interrupt Enable Register */ -#define UCB2IE_SPI (HWREG16(0x4000282A)) -#define UCB2IFG (HWREG16(0x4000282C)) /*!< eUSCI_Bx Interrupt Flag Register */ -#define UCB2IFG_SPI (HWREG16(0x4000282C)) -#define UCB2IV (HWREG16(0x4000282E)) /*!< eUSCI_Bx Interrupt Vector Register */ -#define UCB2IV_SPI (HWREG16(0x4000282E)) - -/* Register offsets from EUSCI_B2_BASE address */ -#define OFS_UCB2CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ -#define OFS_UCB2CTLW0_SPI (0x0000) -#define OFS_UCB2CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ -#define OFS_UCB2BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define OFS_UCB2BRW_SPI (0x0006) -#define OFS_UCB2STATW (0x0008) /*!< eUSCI_Bx Status Register */ -#define OFS_UCB2STATW_SPI (0x0008) -#define OFS_UCB2TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define OFS_UCB2RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ -#define OFS_UCB2RXBUF_SPI (0x000C) -#define OFS_UCB2TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ -#define OFS_UCB2TXBUF_SPI (0x000E) -#define OFS_UCB2I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define OFS_UCB2I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define OFS_UCB2I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define OFS_UCB2I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define OFS_UCB2ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ -#define OFS_UCB2ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ -#define OFS_UCB2I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ -#define OFS_UCB2IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ -#define OFS_UCB2IE_SPI (0x002A) -#define OFS_UCB2IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ -#define OFS_UCB2IFG_SPI (0x002C) -#define OFS_UCB2IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ -#define OFS_UCB2IV_SPI (0x002E) - -#define UCB2CTL0 (HWREG8_L(UCB2CTLW0)) /* eUSCI_Bx Control 1 */ -#define UCB2CTL1 (HWREG8_H(UCB2CTLW0)) /* eUSCI_Bx Control 0 */ -#define UCB2BR0 (HWREG8_L(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 0 */ -#define UCB2BR1 (HWREG8_H(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 1 */ -#define UCB2STAT (HWREG8_L(UCB2STATW)) /* eUSCI_Bx Status */ -#define UCB2BCNT (HWREG8_H(UCB2STATW)) /* eUSCI_Bx Byte Counter Register */ - -/****************************************************************************** -* EUSCI_B3 Registers -******************************************************************************/ -#define UCB3CTLW0 (HWREG16(0x40002C00)) /*!< eUSCI_Bx Control Word Register 0 */ -#define UCB3CTLW0_SPI (HWREG16(0x40002C00)) -#define UCB3CTLW1 (HWREG16(0x40002C02)) /*!< eUSCI_Bx Control Word Register 1 */ -#define UCB3BRW (HWREG16(0x40002C06)) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define UCB3BRW_SPI (HWREG16(0x40002C06)) -#define UCB3STATW (HWREG16(0x40002C08)) /*!< eUSCI_Bx Status Register */ -#define UCB3STATW_SPI (HWREG16(0x40002C08)) -#define UCB3TBCNT (HWREG16(0x40002C0A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define UCB3RXBUF (HWREG16(0x40002C0C)) /*!< eUSCI_Bx Receive Buffer Register */ -#define UCB3RXBUF_SPI (HWREG16(0x40002C0C)) -#define UCB3TXBUF (HWREG16(0x40002C0E)) /*!< eUSCI_Bx Transmit Buffer Register */ -#define UCB3TXBUF_SPI (HWREG16(0x40002C0E)) -#define UCB3I2COA0 (HWREG16(0x40002C14)) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define UCB3I2COA1 (HWREG16(0x40002C16)) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define UCB3I2COA2 (HWREG16(0x40002C18)) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define UCB3I2COA3 (HWREG16(0x40002C1A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define UCB3ADDRX (HWREG16(0x40002C1C)) /*!< eUSCI_Bx I2C Received Address Register */ -#define UCB3ADDMASK (HWREG16(0x40002C1E)) /*!< eUSCI_Bx I2C Address Mask Register */ -#define UCB3I2CSA (HWREG16(0x40002C20)) /*!< eUSCI_Bx I2C Slave Address Register */ -#define UCB3IE (HWREG16(0x40002C2A)) /*!< eUSCI_Bx Interrupt Enable Register */ -#define UCB3IE_SPI (HWREG16(0x40002C2A)) -#define UCB3IFG (HWREG16(0x40002C2C)) /*!< eUSCI_Bx Interrupt Flag Register */ -#define UCB3IFG_SPI (HWREG16(0x40002C2C)) -#define UCB3IV (HWREG16(0x40002C2E)) /*!< eUSCI_Bx Interrupt Vector Register */ -#define UCB3IV_SPI (HWREG16(0x40002C2E)) - -/* Register offsets from EUSCI_B3_BASE address */ -#define OFS_UCB3CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ -#define OFS_UCB3CTLW0_SPI (0x0000) -#define OFS_UCB3CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ -#define OFS_UCB3BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define OFS_UCB3BRW_SPI (0x0006) -#define OFS_UCB3STATW (0x0008) /*!< eUSCI_Bx Status Register */ -#define OFS_UCB3STATW_SPI (0x0008) -#define OFS_UCB3TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define OFS_UCB3RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ -#define OFS_UCB3RXBUF_SPI (0x000C) -#define OFS_UCB3TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ -#define OFS_UCB3TXBUF_SPI (0x000E) -#define OFS_UCB3I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define OFS_UCB3I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define OFS_UCB3I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define OFS_UCB3I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define OFS_UCB3ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ -#define OFS_UCB3ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ -#define OFS_UCB3I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ -#define OFS_UCB3IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ -#define OFS_UCB3IE_SPI (0x002A) -#define OFS_UCB3IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ -#define OFS_UCB3IFG_SPI (0x002C) -#define OFS_UCB3IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ -#define OFS_UCB3IV_SPI (0x002E) - -#define UCB3CTL0 (HWREG8_L(UCB3CTLW0)) /* eUSCI_Bx Control 1 */ -#define UCB3CTL1 (HWREG8_H(UCB3CTLW0)) /* eUSCI_Bx Control 0 */ -#define UCB3BR0 (HWREG8_L(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 0 */ -#define UCB3BR1 (HWREG8_H(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 1 */ -#define UCB3STAT (HWREG8_L(UCB3STATW)) /* eUSCI_Bx Status */ -#define UCB3BCNT (HWREG8_H(UCB3STATW)) /* eUSCI_Bx Byte Counter Register */ - -/****************************************************************************** -* PMAP Registers -******************************************************************************/ -#define PMAPKEYID (HWREG16(0x40005000)) /*!< Port Mapping Key Register */ -#define PMAPCTL (HWREG16(0x40005002)) /*!< Port Mapping Control Register */ -#define P1MAP01 (HWREG16(0x40005008)) /*!< Port mapping register, P1.0 and P1.1 */ -#define P1MAP23 (HWREG16(0x4000500A)) /*!< Port mapping register, P1.2 and P1.3 */ -#define P1MAP45 (HWREG16(0x4000500C)) /*!< Port mapping register, P1.4 and P1.5 */ -#define P1MAP67 (HWREG16(0x4000500E)) /*!< Port mapping register, P1.6 and P1.7 */ -#define P2MAP01 (HWREG16(0x40005010)) /*!< Port mapping register, P2.0 and P2.1 */ -#define P2MAP23 (HWREG16(0x40005012)) /*!< Port mapping register, P2.2 and P2.3 */ -#define P2MAP45 (HWREG16(0x40005014)) /*!< Port mapping register, P2.4 and P2.5 */ -#define P2MAP67 (HWREG16(0x40005016)) /*!< Port mapping register, P2.6 and P2.7 */ -#define P3MAP01 (HWREG16(0x40005018)) /*!< Port mapping register, P3.0 and P3.1 */ -#define P3MAP23 (HWREG16(0x4000501A)) /*!< Port mapping register, P3.2 and P3.3 */ -#define P3MAP45 (HWREG16(0x4000501C)) /*!< Port mapping register, P3.4 and P3.5 */ -#define P3MAP67 (HWREG16(0x4000501E)) /*!< Port mapping register, P3.6 and P3.7 */ -#define P4MAP01 (HWREG16(0x40005020)) /*!< Port mapping register, P4.0 and P4.1 */ -#define P4MAP23 (HWREG16(0x40005022)) /*!< Port mapping register, P4.2 and P4.3 */ -#define P4MAP45 (HWREG16(0x40005024)) /*!< Port mapping register, P4.4 and P4.5 */ -#define P4MAP67 (HWREG16(0x40005026)) /*!< Port mapping register, P4.6 and P4.7 */ -#define P5MAP01 (HWREG16(0x40005028)) /*!< Port mapping register, P5.0 and P5.1 */ -#define P5MAP23 (HWREG16(0x4000502A)) /*!< Port mapping register, P5.2 and P5.3 */ -#define P5MAP45 (HWREG16(0x4000502C)) /*!< Port mapping register, P5.4 and P5.5 */ -#define P5MAP67 (HWREG16(0x4000502E)) /*!< Port mapping register, P5.6 and P5.7 */ -#define P6MAP01 (HWREG16(0x40005030)) /*!< Port mapping register, P6.0 and P6.1 */ -#define P6MAP23 (HWREG16(0x40005032)) /*!< Port mapping register, P6.2 and P6.3 */ -#define P6MAP45 (HWREG16(0x40005034)) /*!< Port mapping register, P6.4 and P6.5 */ -#define P6MAP67 (HWREG16(0x40005036)) /*!< Port mapping register, P6.6 and P6.7 */ -#define P7MAP01 (HWREG16(0x40005038)) /*!< Port mapping register, P7.0 and P7.1 */ -#define P7MAP23 (HWREG16(0x4000503A)) /*!< Port mapping register, P7.2 and P7.3 */ -#define P7MAP45 (HWREG16(0x4000503C)) /*!< Port mapping register, P7.4 and P7.5 */ -#define P7MAP67 (HWREG16(0x4000503E)) /*!< Port mapping register, P7.6 and P7.7 */ - -/* Register offsets from PMAP_BASE address */ -#define OFS_PMAPKEYID (0x0000) /*!< Port Mapping Key Register */ -#define OFS_PMAPCTL (0x0002) /*!< Port Mapping Control Register */ -#define OFS_P1MAP01 (0x0008) /*!< Port mapping register, P1.0 and P1.1 */ -#define OFS_P1MAP23 (0x000A) /*!< Port mapping register, P1.2 and P1.3 */ -#define OFS_P1MAP45 (0x000C) /*!< Port mapping register, P1.4 and P1.5 */ -#define OFS_P1MAP67 (0x000E) /*!< Port mapping register, P1.6 and P1.7 */ -#define OFS_P2MAP01 (0x0010) /*!< Port mapping register, P2.0 and P2.1 */ -#define OFS_P2MAP23 (0x0012) /*!< Port mapping register, P2.2 and P2.3 */ -#define OFS_P2MAP45 (0x0014) /*!< Port mapping register, P2.4 and P2.5 */ -#define OFS_P2MAP67 (0x0016) /*!< Port mapping register, P2.6 and P2.7 */ -#define OFS_P3MAP01 (0x0018) /*!< Port mapping register, P3.0 and P3.1 */ -#define OFS_P3MAP23 (0x001A) /*!< Port mapping register, P3.2 and P3.3 */ -#define OFS_P3MAP45 (0x001C) /*!< Port mapping register, P3.4 and P3.5 */ -#define OFS_P3MAP67 (0x001E) /*!< Port mapping register, P3.6 and P3.7 */ -#define OFS_P4MAP01 (0x0020) /*!< Port mapping register, P4.0 and P4.1 */ -#define OFS_P4MAP23 (0x0022) /*!< Port mapping register, P4.2 and P4.3 */ -#define OFS_P4MAP45 (0x0024) /*!< Port mapping register, P4.4 and P4.5 */ -#define OFS_P4MAP67 (0x0026) /*!< Port mapping register, P4.6 and P4.7 */ -#define OFS_P5MAP01 (0x0028) /*!< Port mapping register, P5.0 and P5.1 */ -#define OFS_P5MAP23 (0x002A) /*!< Port mapping register, P5.2 and P5.3 */ -#define OFS_P5MAP45 (0x002C) /*!< Port mapping register, P5.4 and P5.5 */ -#define OFS_P5MAP67 (0x002E) /*!< Port mapping register, P5.6 and P5.7 */ -#define OFS_P6MAP01 (0x0030) /*!< Port mapping register, P6.0 and P6.1 */ -#define OFS_P6MAP23 (0x0032) /*!< Port mapping register, P6.2 and P6.3 */ -#define OFS_P6MAP45 (0x0034) /*!< Port mapping register, P6.4 and P6.5 */ -#define OFS_P6MAP67 (0x0036) /*!< Port mapping register, P6.6 and P6.7 */ -#define OFS_P7MAP01 (0x0038) /*!< Port mapping register, P7.0 and P7.1 */ -#define OFS_P7MAP23 (0x003A) /*!< Port mapping register, P7.2 and P7.3 */ -#define OFS_P7MAP45 (0x003C) /*!< Port mapping register, P7.4 and P7.5 */ -#define OFS_P7MAP67 (0x003E) /*!< Port mapping register, P7.6 and P7.7 */ - - -/****************************************************************************** -* REF_A Registers -******************************************************************************/ -#define REFCTL0 (HWREG16(0x40003000)) /*!< REF Control Register 0 */ - -/* Register offsets from REF_A_BASE address */ -#define OFS_REFCTL0 (0x0000) /*!< REF Control Register 0 */ - -#define REFCTL0_L (HWREG8_L(REFCTL0)) /* REF Control Register 0 */ -#define REFCTL0_H (HWREG8_H(REFCTL0)) /* REF Control Register 0 */ - -/****************************************************************************** -* RTC_C Registers -******************************************************************************/ -#define RTCCTL0 (HWREG16(0x40004400)) /*!< RTCCTL0 Register */ -#define RTCCTL13 (HWREG16(0x40004402)) /*!< RTCCTL13 Register */ -#define RTCOCAL (HWREG16(0x40004404)) /*!< RTCOCAL Register */ -#define RTCTCMP (HWREG16(0x40004406)) /*!< RTCTCMP Register */ -#define RTCPS0CTL (HWREG16(0x40004408)) /*!< Real-Time Clock Prescale Timer 0 Control Register */ -#define RTCPS1CTL (HWREG16(0x4000440A)) /*!< Real-Time Clock Prescale Timer 1 Control Register */ -#define RTCPS (HWREG16(0x4000440C)) /*!< Real-Time Clock Prescale Timer Counter Register */ -#define RTCIV (HWREG16(0x4000440E)) /*!< Real-Time Clock Interrupt Vector Register */ -#define RTCTIM0 (HWREG16(0x40004410)) /*!< RTCTIM0 Register Hexadecimal Format */ -#define RTCTIM0_BCD (HWREG16(0x40004410)) -#define RTCTIM1 (HWREG16(0x40004412)) /*!< Real-Time Clock Hour, Day of Week */ -#define RTCTIM1_BCD (HWREG16(0x40004412)) -#define RTCDATE (HWREG16(0x40004414)) /*!< RTCDATE - Hexadecimal Format */ -#define RTCDATE_BCD (HWREG16(0x40004414)) -#define RTCYEAR (HWREG16(0x40004416)) /*!< RTCYEAR Register Hexadecimal Format */ -#define RTCYEAR_BCD (HWREG16(0x40004416)) -#define RTCAMINHR (HWREG16(0x40004418)) /*!< RTCMINHR - Hexadecimal Format */ -#define RTCAMINHR_BCD (HWREG16(0x40004418)) -#define RTCADOWDAY (HWREG16(0x4000441A)) /*!< RTCADOWDAY - Hexadecimal Format */ -#define RTCADOWDAY_BCD (HWREG16(0x4000441A)) -#define RTCBIN2BCD (HWREG16(0x4000441C)) /*!< Binary-to-BCD Conversion Register */ -#define RTCBCD2BIN (HWREG16(0x4000441E)) /*!< BCD-to-Binary Conversion Register */ - -/* Register offsets from RTC_C_BASE address */ -#define OFS_RTCCTL0 (0x0000) /*!< RTCCTL0 Register */ -#define OFS_RTCCTL13 (0x0002) /*!< RTCCTL13 Register */ -#define OFS_RTCOCAL (0x0004) /*!< RTCOCAL Register */ -#define OFS_RTCTCMP (0x0006) /*!< RTCTCMP Register */ -#define OFS_RTCPS0CTL (0x0008) /*!< Real-Time Clock Prescale Timer 0 Control Register */ -#define OFS_RTCPS1CTL (0x000A) /*!< Real-Time Clock Prescale Timer 1 Control Register */ -#define OFS_RTCPS (0x000C) /*!< Real-Time Clock Prescale Timer Counter Register */ -#define OFS_RTCIV (0x000E) /*!< Real-Time Clock Interrupt Vector Register */ -#define OFS_RTCTIM0 (0x0010) /*!< RTCTIM0 Register Hexadecimal Format */ -#define OFS_RTCTIM0_BCD (0x0010) -#define OFS_RTCTIM1 (0x0012) /*!< Real-Time Clock Hour, Day of Week */ -#define OFS_RTCTIM1_BCD (0x0012) -#define OFS_RTCDATE (0x0014) /*!< RTCDATE - Hexadecimal Format */ -#define OFS_RTCDATE_BCD (0x0014) -#define OFS_RTCYEAR (0x0016) /*!< RTCYEAR Register Hexadecimal Format */ -#define OFS_RTCYEAR_BCD (0x0016) -#define OFS_RTCAMINHR (0x0018) /*!< RTCMINHR - Hexadecimal Format */ -#define OFS_RTCAMINHR_BCD (0x0018) -#define OFS_RTCADOWDAY (0x001A) /*!< RTCADOWDAY - Hexadecimal Format */ -#define OFS_RTCADOWDAY_BCD (0x001A) -#define OFS_RTCBIN2BCD (0x001C) /*!< Binary-to-BCD Conversion Register */ -#define OFS_RTCBCD2BIN (0x001E) /*!< BCD-to-Binary Conversion Register */ - -#define RTCCTL0_L (HWREG8_L(RTCCTL0)) /* RTCCTL0 Register */ -#define RTCCTL0_H (HWREG8_H(RTCCTL0)) /* RTCCTL0 Register */ -#define RTCCTL1 (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */ -#define RTCCTL13_L (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */ -#define RTCCTL3 (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */ -#define RTCCTL13_H (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */ -#define RTCOCAL_L (HWREG8_L(RTCOCAL)) /* RTCOCAL Register */ -#define RTCOCAL_H (HWREG8_H(RTCOCAL)) /* RTCOCAL Register */ -#define RTCTCMP_L (HWREG8_L(RTCTCMP)) /* RTCTCMP Register */ -#define RTCTCMP_H (HWREG8_H(RTCTCMP)) /* RTCTCMP Register */ -#define RTCPS0CTL_L (HWREG8_L(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */ -#define RTCPS0CTL_H (HWREG8_H(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */ -#define RTCPS1CTL_L (HWREG8_L(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */ -#define RTCPS1CTL_H (HWREG8_H(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */ -#define RTCPS0 (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ -#define RTCPS_L (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ -#define RTCPS1 (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ -#define RTCPS_H (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ -#define RTCSEC (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */ -#define RTCTIM0_L (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */ -#define RTCMIN (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */ -#define RTCTIM0_H (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */ -#define RTCHOUR (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */ -#define RTCTIM1_L (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */ -#define RTCDOW (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */ -#define RTCTIM1_H (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */ -#define RTCDAY (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */ -#define RTCDATE_L (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */ -#define RTCMON (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */ -#define RTCDATE_H (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */ -#define RTCAMIN (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */ -#define RTCAMINHR_L (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */ -#define RTCAHOUR (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */ -#define RTCAMINHR_H (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */ -#define RTCADOW (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */ -#define RTCADOWDAY_L (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */ -#define RTCADAY (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */ -#define RTCADOWDAY_H (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */ - -/****************************************************************************** -* TIMER_A0 Registers -******************************************************************************/ -#define TA0CTL (HWREG16(0x40000000)) /*!< TimerAx Control Register */ -#define TA0CCTL0 (HWREG16(0x40000002)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0CCTL1 (HWREG16(0x40000004)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0CCTL2 (HWREG16(0x40000006)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0CCTL3 (HWREG16(0x40000008)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0CCTL4 (HWREG16(0x4000000A)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0R (HWREG16(0x40000010)) /*!< TimerA register */ -#define TA0CCR0 (HWREG16(0x40000012)) /*!< Timer_A Capture/Compare Register */ -#define TA0CCR1 (HWREG16(0x40000014)) /*!< Timer_A Capture/Compare Register */ -#define TA0CCR2 (HWREG16(0x40000016)) /*!< Timer_A Capture/Compare Register */ -#define TA0CCR3 (HWREG16(0x40000018)) /*!< Timer_A Capture/Compare Register */ -#define TA0CCR4 (HWREG16(0x4000001A)) /*!< Timer_A Capture/Compare Register */ -#define TA0EX0 (HWREG16(0x40000020)) /*!< TimerAx Expansion 0 Register */ -#define TA0IV (HWREG16(0x4000002E)) /*!< TimerAx Interrupt Vector Register */ - -/* Register offsets from TIMER_A0_BASE address */ -#define OFS_TA0CTL (0x0000) /*!< TimerAx Control Register */ -#define OFS_TA0CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0R (0x0010) /*!< TimerA register */ -#define OFS_TA0CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ -#define OFS_TA0IV (0x002E) /*!< TimerAx Interrupt Vector Register */ - - -/****************************************************************************** -* TIMER_A1 Registers -******************************************************************************/ -#define TA1CTL (HWREG16(0x40000400)) /*!< TimerAx Control Register */ -#define TA1CCTL0 (HWREG16(0x40000402)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1CCTL1 (HWREG16(0x40000404)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1CCTL2 (HWREG16(0x40000406)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1CCTL3 (HWREG16(0x40000408)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1CCTL4 (HWREG16(0x4000040A)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1R (HWREG16(0x40000410)) /*!< TimerA register */ -#define TA1CCR0 (HWREG16(0x40000412)) /*!< Timer_A Capture/Compare Register */ -#define TA1CCR1 (HWREG16(0x40000414)) /*!< Timer_A Capture/Compare Register */ -#define TA1CCR2 (HWREG16(0x40000416)) /*!< Timer_A Capture/Compare Register */ -#define TA1CCR3 (HWREG16(0x40000418)) /*!< Timer_A Capture/Compare Register */ -#define TA1CCR4 (HWREG16(0x4000041A)) /*!< Timer_A Capture/Compare Register */ -#define TA1EX0 (HWREG16(0x40000420)) /*!< TimerAx Expansion 0 Register */ -#define TA1IV (HWREG16(0x4000042E)) /*!< TimerAx Interrupt Vector Register */ - -/* Register offsets from TIMER_A1_BASE address */ -#define OFS_TA1CTL (0x0000) /*!< TimerAx Control Register */ -#define OFS_TA1CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1R (0x0010) /*!< TimerA register */ -#define OFS_TA1CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ -#define OFS_TA1IV (0x002E) /*!< TimerAx Interrupt Vector Register */ - - -/****************************************************************************** -* TIMER_A2 Registers -******************************************************************************/ -#define TA2CTL (HWREG16(0x40000800)) /*!< TimerAx Control Register */ -#define TA2CCTL0 (HWREG16(0x40000802)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2CCTL1 (HWREG16(0x40000804)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2CCTL2 (HWREG16(0x40000806)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2CCTL3 (HWREG16(0x40000808)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2CCTL4 (HWREG16(0x4000080A)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2R (HWREG16(0x40000810)) /*!< TimerA register */ -#define TA2CCR0 (HWREG16(0x40000812)) /*!< Timer_A Capture/Compare Register */ -#define TA2CCR1 (HWREG16(0x40000814)) /*!< Timer_A Capture/Compare Register */ -#define TA2CCR2 (HWREG16(0x40000816)) /*!< Timer_A Capture/Compare Register */ -#define TA2CCR3 (HWREG16(0x40000818)) /*!< Timer_A Capture/Compare Register */ -#define TA2CCR4 (HWREG16(0x4000081A)) /*!< Timer_A Capture/Compare Register */ -#define TA2EX0 (HWREG16(0x40000820)) /*!< TimerAx Expansion 0 Register */ -#define TA2IV (HWREG16(0x4000082E)) /*!< TimerAx Interrupt Vector Register */ - -/* Register offsets from TIMER_A2_BASE address */ -#define OFS_TA2CTL (0x0000) /*!< TimerAx Control Register */ -#define OFS_TA2CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2R (0x0010) /*!< TimerA register */ -#define OFS_TA2CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ -#define OFS_TA2IV (0x002E) /*!< TimerAx Interrupt Vector Register */ - - -/****************************************************************************** -* TIMER_A3 Registers -******************************************************************************/ -#define TA3CTL (HWREG16(0x40000C00)) /*!< TimerAx Control Register */ -#define TA3CCTL0 (HWREG16(0x40000C02)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3CCTL1 (HWREG16(0x40000C04)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3CCTL2 (HWREG16(0x40000C06)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3CCTL3 (HWREG16(0x40000C08)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3CCTL4 (HWREG16(0x40000C0A)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3R (HWREG16(0x40000C10)) /*!< TimerA register */ -#define TA3CCR0 (HWREG16(0x40000C12)) /*!< Timer_A Capture/Compare Register */ -#define TA3CCR1 (HWREG16(0x40000C14)) /*!< Timer_A Capture/Compare Register */ -#define TA3CCR2 (HWREG16(0x40000C16)) /*!< Timer_A Capture/Compare Register */ -#define TA3CCR3 (HWREG16(0x40000C18)) /*!< Timer_A Capture/Compare Register */ -#define TA3CCR4 (HWREG16(0x40000C1A)) /*!< Timer_A Capture/Compare Register */ -#define TA3EX0 (HWREG16(0x40000C20)) /*!< TimerAx Expansion 0 Register */ -#define TA3IV (HWREG16(0x40000C2E)) /*!< TimerAx Interrupt Vector Register */ - -/* Register offsets from TIMER_A3_BASE address */ -#define OFS_TA3CTL (0x0000) /*!< TimerAx Control Register */ -#define OFS_TA3CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3R (0x0010) /*!< TimerA register */ -#define OFS_TA3CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ -#define OFS_TA3IV (0x002E) /*!< TimerAx Interrupt Vector Register */ - - -/****************************************************************************** -* WDT_A Registers -******************************************************************************/ -#define WDTCTL (HWREG16(0x4000480C)) /*!< Watchdog Timer Control Register */ - -/* Register offsets from WDT_A_BASE address */ -#define OFS_WDTCTL (0x000C) /*!< Watchdog Timer Control Register */ - - -/****************************************************************************** -* Peripheral register control bits (legacy section) * -******************************************************************************/ - -/****************************************************************************** -* AES256 Bits (legacy section) -******************************************************************************/ -/* AESACTL0[AESOP] Bits */ -#define AESOP_OFS AES256_CTL0_OP_OFS /*!< AESOP Offset */ -#define AESOP_M AES256_CTL0_OP_MASK /*!< AES operation */ -#define AESOP0 AES256_CTL0_OP0 /*!< AESOP Bit 0 */ -#define AESOP1 AES256_CTL0_OP1 /*!< AESOP Bit 1 */ -#define AESOP_0 AES256_CTL0_OP_0 /*!< Encryption */ -#define AESOP_1 AES256_CTL0_OP_1 /*!< Decryption. The provided key is the same key used for encryption */ -#define AESOP_2 AES256_CTL0_OP_2 /*!< Generate first round key required for decryption */ -#define AESOP_3 AES256_CTL0_OP_3 /*!< Decryption. The provided key is the first round key required for decryption */ -/* AESACTL0[AESKL] Bits */ -#define AESKL_OFS AES256_CTL0_KL_OFS /*!< AESKL Offset */ -#define AESKL_M AES256_CTL0_KL_MASK /*!< AES key length */ -#define AESKL0 AES256_CTL0_KL0 /*!< AESKL Bit 0 */ -#define AESKL1 AES256_CTL0_KL1 /*!< AESKL Bit 1 */ -#define AESKL_0 AES256_CTL0_KL_0 /*!< AES128. The key size is 128 bit */ -#define AESKL_1 AES256_CTL0_KL_1 /*!< AES192. The key size is 192 bit. */ -#define AESKL_2 AES256_CTL0_KL_2 /*!< AES256. The key size is 256 bit */ -#define AESKL__128BIT AES256_CTL0_KL__128BIT /*!< AES128. The key size is 128 bit */ -#define AESKL__192BIT AES256_CTL0_KL__192BIT /*!< AES192. The key size is 192 bit. */ -#define AESKL__256BIT AES256_CTL0_KL__256BIT /*!< AES256. The key size is 256 bit */ -/* AESACTL0[AESCM] Bits */ -#define AESCM_OFS AES256_CTL0_CM_OFS /*!< AESCM Offset */ -#define AESCM_M AES256_CTL0_CM_MASK /*!< AES cipher mode select */ -#define AESCM0 AES256_CTL0_CM0 /*!< AESCM Bit 0 */ -#define AESCM1 AES256_CTL0_CM1 /*!< AESCM Bit 1 */ -#define AESCM_0 AES256_CTL0_CM_0 /*!< ECB */ -#define AESCM_1 AES256_CTL0_CM_1 /*!< CBC */ -#define AESCM_2 AES256_CTL0_CM_2 /*!< OFB */ -#define AESCM_3 AES256_CTL0_CM_3 /*!< CFB */ -#define AESCM__ECB AES256_CTL0_CM__ECB /*!< ECB */ -#define AESCM__CBC AES256_CTL0_CM__CBC /*!< CBC */ -#define AESCM__OFB AES256_CTL0_CM__OFB /*!< OFB */ -#define AESCM__CFB AES256_CTL0_CM__CFB /*!< CFB */ -/* AESACTL0[AESSWRST] Bits */ -#define AESSWRST_OFS AES256_CTL0_SWRST_OFS /*!< AESSWRST Offset */ -#define AESSWRST AES256_CTL0_SWRST /*!< AES software reset */ -/* AESACTL0[AESRDYIFG] Bits */ -#define AESRDYIFG_OFS AES256_CTL0_RDYIFG_OFS /*!< AESRDYIFG Offset */ -#define AESRDYIFG AES256_CTL0_RDYIFG /*!< AES ready interrupt flag */ -/* AESACTL0[AESERRFG] Bits */ -#define AESERRFG_OFS AES256_CTL0_ERRFG_OFS /*!< AESERRFG Offset */ -#define AESERRFG AES256_CTL0_ERRFG /*!< AES error flag */ -/* AESACTL0[AESRDYIE] Bits */ -#define AESRDYIE_OFS AES256_CTL0_RDYIE_OFS /*!< AESRDYIE Offset */ -#define AESRDYIE AES256_CTL0_RDYIE /*!< AES ready interrupt enable */ -/* AESACTL0[AESCMEN] Bits */ -#define AESCMEN_OFS AES256_CTL0_CMEN_OFS /*!< AESCMEN Offset */ -#define AESCMEN AES256_CTL0_CMEN /*!< AES cipher mode enable */ -/* AESACTL1[AESBLKCNT] Bits */ -#define AESBLKCNT_OFS AES256_CTL1_BLKCNT_OFS /*!< AESBLKCNT Offset */ -#define AESBLKCNT_M AES256_CTL1_BLKCNT_MASK /*!< Cipher Block Counter */ -#define AESBLKCNT0 AES256_CTL1_BLKCNT0 /*!< AESBLKCNT Bit 0 */ -#define AESBLKCNT1 AES256_CTL1_BLKCNT1 /*!< AESBLKCNT Bit 1 */ -#define AESBLKCNT2 AES256_CTL1_BLKCNT2 /*!< AESBLKCNT Bit 2 */ -#define AESBLKCNT3 AES256_CTL1_BLKCNT3 /*!< AESBLKCNT Bit 3 */ -#define AESBLKCNT4 AES256_CTL1_BLKCNT4 /*!< AESBLKCNT Bit 4 */ -#define AESBLKCNT5 AES256_CTL1_BLKCNT5 /*!< AESBLKCNT Bit 5 */ -#define AESBLKCNT6 AES256_CTL1_BLKCNT6 /*!< AESBLKCNT Bit 6 */ -#define AESBLKCNT7 AES256_CTL1_BLKCNT7 /*!< AESBLKCNT Bit 7 */ -/* AESASTAT[AESBUSY] Bits */ -#define AESBUSY_OFS AES256_STAT_BUSY_OFS /*!< AESBUSY Offset */ -#define AESBUSY AES256_STAT_BUSY /*!< AES accelerator module busy */ -/* AESASTAT[AESKEYWR] Bits */ -#define AESKEYWR_OFS AES256_STAT_KEYWR_OFS /*!< AESKEYWR Offset */ -#define AESKEYWR AES256_STAT_KEYWR /*!< All 16 bytes written to AESAKEY */ -/* AESASTAT[AESDINWR] Bits */ -#define AESDINWR_OFS AES256_STAT_DINWR_OFS /*!< AESDINWR Offset */ -#define AESDINWR AES256_STAT_DINWR /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ -/* AESASTAT[AESDOUTRD] Bits */ -#define AESDOUTRD_OFS AES256_STAT_DOUTRD_OFS /*!< AESDOUTRD Offset */ -#define AESDOUTRD AES256_STAT_DOUTRD /*!< All 16 bytes read from AESADOUT */ -/* AESASTAT[AESKEYCNT] Bits */ -#define AESKEYCNT_OFS AES256_STAT_KEYCNT_OFS /*!< AESKEYCNT Offset */ -#define AESKEYCNT_M AES256_STAT_KEYCNT_MASK /*!< Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */ -#define AESKEYCNT0 AES256_STAT_KEYCNT0 /*!< AESKEYCNT Bit 0 */ -#define AESKEYCNT1 AES256_STAT_KEYCNT1 /*!< AESKEYCNT Bit 1 */ -#define AESKEYCNT2 AES256_STAT_KEYCNT2 /*!< AESKEYCNT Bit 2 */ -#define AESKEYCNT3 AES256_STAT_KEYCNT3 /*!< AESKEYCNT Bit 3 */ -/* AESASTAT[AESDINCNT] Bits */ -#define AESDINCNT_OFS AES256_STAT_DINCNT_OFS /*!< AESDINCNT Offset */ -#define AESDINCNT_M AES256_STAT_DINCNT_MASK /*!< Bytes written via AESADIN, AESAXDIN or AESAXIN */ -#define AESDINCNT0 AES256_STAT_DINCNT0 /*!< AESDINCNT Bit 0 */ -#define AESDINCNT1 AES256_STAT_DINCNT1 /*!< AESDINCNT Bit 1 */ -#define AESDINCNT2 AES256_STAT_DINCNT2 /*!< AESDINCNT Bit 2 */ -#define AESDINCNT3 AES256_STAT_DINCNT3 /*!< AESDINCNT Bit 3 */ -/* AESASTAT[AESDOUTCNT] Bits */ -#define AESDOUTCNT_OFS AES256_STAT_DOUTCNT_OFS /*!< AESDOUTCNT Offset */ -#define AESDOUTCNT_M AES256_STAT_DOUTCNT_MASK /*!< Bytes read via AESADOUT */ -#define AESDOUTCNT0 AES256_STAT_DOUTCNT0 /*!< AESDOUTCNT Bit 0 */ -#define AESDOUTCNT1 AES256_STAT_DOUTCNT1 /*!< AESDOUTCNT Bit 1 */ -#define AESDOUTCNT2 AES256_STAT_DOUTCNT2 /*!< AESDOUTCNT Bit 2 */ -#define AESDOUTCNT3 AES256_STAT_DOUTCNT3 /*!< AESDOUTCNT Bit 3 */ -/* AESAKEY[AESKEY0] Bits */ -#define AESKEY0_OFS AES256_KEY_KEY0_OFS /*!< AESKEY0 Offset */ -#define AESKEY0_M AES256_KEY_KEY0_MASK /*!< AES key byte n when AESAKEY is written as half-word */ -#define AESKEY00 AES256_KEY_KEY00 /*!< AESKEY0 Bit 0 */ -#define AESKEY01 AES256_KEY_KEY01 /*!< AESKEY0 Bit 1 */ -#define AESKEY02 AES256_KEY_KEY02 /*!< AESKEY0 Bit 2 */ -#define AESKEY03 AES256_KEY_KEY03 /*!< AESKEY0 Bit 3 */ -#define AESKEY04 AES256_KEY_KEY04 /*!< AESKEY0 Bit 4 */ -#define AESKEY05 AES256_KEY_KEY05 /*!< AESKEY0 Bit 5 */ -#define AESKEY06 AES256_KEY_KEY06 /*!< AESKEY0 Bit 6 */ -#define AESKEY07 AES256_KEY_KEY07 /*!< AESKEY0 Bit 7 */ -/* AESAKEY[AESKEY1] Bits */ -#define AESKEY1_OFS AES256_KEY_KEY1_OFS /*!< AESKEY1 Offset */ -#define AESKEY1_M AES256_KEY_KEY1_MASK /*!< AES key byte n+1 when AESAKEY is written as half-word */ -#define AESKEY10 AES256_KEY_KEY10 /*!< AESKEY1 Bit 0 */ -#define AESKEY11 AES256_KEY_KEY11 /*!< AESKEY1 Bit 1 */ -#define AESKEY12 AES256_KEY_KEY12 /*!< AESKEY1 Bit 2 */ -#define AESKEY13 AES256_KEY_KEY13 /*!< AESKEY1 Bit 3 */ -#define AESKEY14 AES256_KEY_KEY14 /*!< AESKEY1 Bit 4 */ -#define AESKEY15 AES256_KEY_KEY15 /*!< AESKEY1 Bit 5 */ -#define AESKEY16 AES256_KEY_KEY16 /*!< AESKEY1 Bit 6 */ -#define AESKEY17 AES256_KEY_KEY17 /*!< AESKEY1 Bit 7 */ -/* AESADIN[AESDIN0] Bits */ -#define AESDIN0_OFS AES256_DIN_DIN0_OFS /*!< AESDIN0 Offset */ -#define AESDIN0_M AES256_DIN_DIN0_MASK /*!< AES data in byte n when AESADIN is written as half-word */ -#define AESDIN00 AES256_DIN_DIN00 /*!< AESDIN0 Bit 0 */ -#define AESDIN01 AES256_DIN_DIN01 /*!< AESDIN0 Bit 1 */ -#define AESDIN02 AES256_DIN_DIN02 /*!< AESDIN0 Bit 2 */ -#define AESDIN03 AES256_DIN_DIN03 /*!< AESDIN0 Bit 3 */ -#define AESDIN04 AES256_DIN_DIN04 /*!< AESDIN0 Bit 4 */ -#define AESDIN05 AES256_DIN_DIN05 /*!< AESDIN0 Bit 5 */ -#define AESDIN06 AES256_DIN_DIN06 /*!< AESDIN0 Bit 6 */ -#define AESDIN07 AES256_DIN_DIN07 /*!< AESDIN0 Bit 7 */ -/* AESADIN[AESDIN1] Bits */ -#define AESDIN1_OFS AES256_DIN_DIN1_OFS /*!< AESDIN1 Offset */ -#define AESDIN1_M AES256_DIN_DIN1_MASK /*!< AES data in byte n+1 when AESADIN is written as half-word */ -#define AESDIN10 AES256_DIN_DIN10 /*!< AESDIN1 Bit 0 */ -#define AESDIN11 AES256_DIN_DIN11 /*!< AESDIN1 Bit 1 */ -#define AESDIN12 AES256_DIN_DIN12 /*!< AESDIN1 Bit 2 */ -#define AESDIN13 AES256_DIN_DIN13 /*!< AESDIN1 Bit 3 */ -#define AESDIN14 AES256_DIN_DIN14 /*!< AESDIN1 Bit 4 */ -#define AESDIN15 AES256_DIN_DIN15 /*!< AESDIN1 Bit 5 */ -#define AESDIN16 AES256_DIN_DIN16 /*!< AESDIN1 Bit 6 */ -#define AESDIN17 AES256_DIN_DIN17 /*!< AESDIN1 Bit 7 */ -/* AESADOUT[AESDOUT0] Bits */ -#define AESDOUT0_OFS AES256_DOUT_DOUT0_OFS /*!< AESDOUT0 Offset */ -#define AESDOUT0_M AES256_DOUT_DOUT0_MASK /*!< AES data out byte n when AESADOUT is read as half-word */ -#define AESDOUT00 AES256_DOUT_DOUT00 /*!< AESDOUT0 Bit 0 */ -#define AESDOUT01 AES256_DOUT_DOUT01 /*!< AESDOUT0 Bit 1 */ -#define AESDOUT02 AES256_DOUT_DOUT02 /*!< AESDOUT0 Bit 2 */ -#define AESDOUT03 AES256_DOUT_DOUT03 /*!< AESDOUT0 Bit 3 */ -#define AESDOUT04 AES256_DOUT_DOUT04 /*!< AESDOUT0 Bit 4 */ -#define AESDOUT05 AES256_DOUT_DOUT05 /*!< AESDOUT0 Bit 5 */ -#define AESDOUT06 AES256_DOUT_DOUT06 /*!< AESDOUT0 Bit 6 */ -#define AESDOUT07 AES256_DOUT_DOUT07 /*!< AESDOUT0 Bit 7 */ -/* AESADOUT[AESDOUT1] Bits */ -#define AESDOUT1_OFS AES256_DOUT_DOUT1_OFS /*!< AESDOUT1 Offset */ -#define AESDOUT1_M AES256_DOUT_DOUT1_MASK /*!< AES data out byte n+1 when AESADOUT is read as half-word */ -#define AESDOUT10 AES256_DOUT_DOUT10 /*!< AESDOUT1 Bit 0 */ -#define AESDOUT11 AES256_DOUT_DOUT11 /*!< AESDOUT1 Bit 1 */ -#define AESDOUT12 AES256_DOUT_DOUT12 /*!< AESDOUT1 Bit 2 */ -#define AESDOUT13 AES256_DOUT_DOUT13 /*!< AESDOUT1 Bit 3 */ -#define AESDOUT14 AES256_DOUT_DOUT14 /*!< AESDOUT1 Bit 4 */ -#define AESDOUT15 AES256_DOUT_DOUT15 /*!< AESDOUT1 Bit 5 */ -#define AESDOUT16 AES256_DOUT_DOUT16 /*!< AESDOUT1 Bit 6 */ -#define AESDOUT17 AES256_DOUT_DOUT17 /*!< AESDOUT1 Bit 7 */ -/* AESAXDIN[AESXDIN0] Bits */ -#define AESXDIN0_OFS AES256_XDIN_XDIN0_OFS /*!< AESXDIN0 Offset */ -#define AESXDIN0_M AES256_XDIN_XDIN0_MASK /*!< AES data in byte n when AESAXDIN is written as half-word */ -#define AESXDIN00 AES256_XDIN_XDIN00 /*!< AESXDIN0 Bit 0 */ -#define AESXDIN01 AES256_XDIN_XDIN01 /*!< AESXDIN0 Bit 1 */ -#define AESXDIN02 AES256_XDIN_XDIN02 /*!< AESXDIN0 Bit 2 */ -#define AESXDIN03 AES256_XDIN_XDIN03 /*!< AESXDIN0 Bit 3 */ -#define AESXDIN04 AES256_XDIN_XDIN04 /*!< AESXDIN0 Bit 4 */ -#define AESXDIN05 AES256_XDIN_XDIN05 /*!< AESXDIN0 Bit 5 */ -#define AESXDIN06 AES256_XDIN_XDIN06 /*!< AESXDIN0 Bit 6 */ -#define AESXDIN07 AES256_XDIN_XDIN07 /*!< AESXDIN0 Bit 7 */ -/* AESAXDIN[AESXDIN1] Bits */ -#define AESXDIN1_OFS AES256_XDIN_XDIN1_OFS /*!< AESXDIN1 Offset */ -#define AESXDIN1_M AES256_XDIN_XDIN1_MASK /*!< AES data in byte n+1 when AESAXDIN is written as half-word */ -#define AESXDIN10 AES256_XDIN_XDIN10 /*!< AESXDIN1 Bit 0 */ -#define AESXDIN11 AES256_XDIN_XDIN11 /*!< AESXDIN1 Bit 1 */ -#define AESXDIN12 AES256_XDIN_XDIN12 /*!< AESXDIN1 Bit 2 */ -#define AESXDIN13 AES256_XDIN_XDIN13 /*!< AESXDIN1 Bit 3 */ -#define AESXDIN14 AES256_XDIN_XDIN14 /*!< AESXDIN1 Bit 4 */ -#define AESXDIN15 AES256_XDIN_XDIN15 /*!< AESXDIN1 Bit 5 */ -#define AESXDIN16 AES256_XDIN_XDIN16 /*!< AESXDIN1 Bit 6 */ -#define AESXDIN17 AES256_XDIN_XDIN17 /*!< AESXDIN1 Bit 7 */ -/* AESAXIN[AESXIN0] Bits */ -#define AESXIN0_OFS AES256_XIN_XIN0_OFS /*!< AESXIN0 Offset */ -#define AESXIN0_M AES256_XIN_XIN0_MASK /*!< AES data in byte n when AESAXIN is written as half-word */ -#define AESXIN00 AES256_XIN_XIN00 /*!< AESXIN0 Bit 0 */ -#define AESXIN01 AES256_XIN_XIN01 /*!< AESXIN0 Bit 1 */ -#define AESXIN02 AES256_XIN_XIN02 /*!< AESXIN0 Bit 2 */ -#define AESXIN03 AES256_XIN_XIN03 /*!< AESXIN0 Bit 3 */ -#define AESXIN04 AES256_XIN_XIN04 /*!< AESXIN0 Bit 4 */ -#define AESXIN05 AES256_XIN_XIN05 /*!< AESXIN0 Bit 5 */ -#define AESXIN06 AES256_XIN_XIN06 /*!< AESXIN0 Bit 6 */ -#define AESXIN07 AES256_XIN_XIN07 /*!< AESXIN0 Bit 7 */ -/* AESAXIN[AESXIN1] Bits */ -#define AESXIN1_OFS AES256_XIN_XIN1_OFS /*!< AESXIN1 Offset */ -#define AESXIN1_M AES256_XIN_XIN1_MASK /*!< AES data in byte n+1 when AESAXIN is written as half-word */ -#define AESXIN10 AES256_XIN_XIN10 /*!< AESXIN1 Bit 0 */ -#define AESXIN11 AES256_XIN_XIN11 /*!< AESXIN1 Bit 1 */ -#define AESXIN12 AES256_XIN_XIN12 /*!< AESXIN1 Bit 2 */ -#define AESXIN13 AES256_XIN_XIN13 /*!< AESXIN1 Bit 3 */ -#define AESXIN14 AES256_XIN_XIN14 /*!< AESXIN1 Bit 4 */ -#define AESXIN15 AES256_XIN_XIN15 /*!< AESXIN1 Bit 5 */ -#define AESXIN16 AES256_XIN_XIN16 /*!< AESXIN1 Bit 6 */ -#define AESXIN17 AES256_XIN_XIN17 /*!< AESXIN1 Bit 7 */ - -/****************************************************************************** -* CAPTIO Bits (legacy section) -******************************************************************************/ -/* CAPTIO0CTL[CAPTIOPISEL] Bits */ -#define CAPTIOPISEL_OFS CAPTIO_CTL_PISEL_OFS /*!< CAPTIOPISEL Offset */ -#define CAPTIOPISEL_M CAPTIO_CTL_PISEL_MASK /*!< Capacitive Touch IO pin select */ -#define CAPTIOPISEL0 CAPTIO_CTL_PISEL0 /*!< CAPTIOPISEL Bit 0 */ -#define CAPTIOPISEL1 CAPTIO_CTL_PISEL1 /*!< CAPTIOPISEL Bit 1 */ -#define CAPTIOPISEL2 CAPTIO_CTL_PISEL2 /*!< CAPTIOPISEL Bit 2 */ -#define CAPTIOPISEL_0 CAPTIO_CTL_PISEL_0 /*!< Px.0 */ -#define CAPTIOPISEL_1 CAPTIO_CTL_PISEL_1 /*!< Px.1 */ -#define CAPTIOPISEL_2 CAPTIO_CTL_PISEL_2 /*!< Px.2 */ -#define CAPTIOPISEL_3 CAPTIO_CTL_PISEL_3 /*!< Px.3 */ -#define CAPTIOPISEL_4 CAPTIO_CTL_PISEL_4 /*!< Px.4 */ -#define CAPTIOPISEL_5 CAPTIO_CTL_PISEL_5 /*!< Px.5 */ -#define CAPTIOPISEL_6 CAPTIO_CTL_PISEL_6 /*!< Px.6 */ -#define CAPTIOPISEL_7 CAPTIO_CTL_PISEL_7 /*!< Px.7 */ -/* CAPTIO0CTL[CAPTIOPOSEL] Bits */ -#define CAPTIOPOSEL_OFS CAPTIO_CTL_POSEL_OFS /*!< CAPTIOPOSEL Offset */ -#define CAPTIOPOSEL_M CAPTIO_CTL_POSEL_MASK /*!< Capacitive Touch IO port select */ -#define CAPTIOPOSEL0 CAPTIO_CTL_POSEL0 /*!< CAPTIOPOSEL Bit 0 */ -#define CAPTIOPOSEL1 CAPTIO_CTL_POSEL1 /*!< CAPTIOPOSEL Bit 1 */ -#define CAPTIOPOSEL2 CAPTIO_CTL_POSEL2 /*!< CAPTIOPOSEL Bit 2 */ -#define CAPTIOPOSEL3 CAPTIO_CTL_POSEL3 /*!< CAPTIOPOSEL Bit 3 */ -#define CAPTIOPOSEL_0 CAPTIO_CTL_POSEL_0 /*!< Px = PJ */ -#define CAPTIOPOSEL_1 CAPTIO_CTL_POSEL_1 /*!< Px = P1 */ -#define CAPTIOPOSEL_2 CAPTIO_CTL_POSEL_2 /*!< Px = P2 */ -#define CAPTIOPOSEL_3 CAPTIO_CTL_POSEL_3 /*!< Px = P3 */ -#define CAPTIOPOSEL_4 CAPTIO_CTL_POSEL_4 /*!< Px = P4 */ -#define CAPTIOPOSEL_5 CAPTIO_CTL_POSEL_5 /*!< Px = P5 */ -#define CAPTIOPOSEL_6 CAPTIO_CTL_POSEL_6 /*!< Px = P6 */ -#define CAPTIOPOSEL_7 CAPTIO_CTL_POSEL_7 /*!< Px = P7 */ -#define CAPTIOPOSEL_8 CAPTIO_CTL_POSEL_8 /*!< Px = P8 */ -#define CAPTIOPOSEL_9 CAPTIO_CTL_POSEL_9 /*!< Px = P9 */ -#define CAPTIOPOSEL_10 CAPTIO_CTL_POSEL_10 /*!< Px = P10 */ -#define CAPTIOPOSEL_11 CAPTIO_CTL_POSEL_11 /*!< Px = P11 */ -#define CAPTIOPOSEL_12 CAPTIO_CTL_POSEL_12 /*!< Px = P12 */ -#define CAPTIOPOSEL_13 CAPTIO_CTL_POSEL_13 /*!< Px = P13 */ -#define CAPTIOPOSEL_14 CAPTIO_CTL_POSEL_14 /*!< Px = P14 */ -#define CAPTIOPOSEL_15 CAPTIO_CTL_POSEL_15 /*!< Px = P15 */ -#define CAPTIOPOSEL__PJ CAPTIO_CTL_POSEL__PJ /*!< Px = PJ */ -#define CAPTIOPOSEL__P1 CAPTIO_CTL_POSEL__P1 /*!< Px = P1 */ -#define CAPTIOPOSEL__P2 CAPTIO_CTL_POSEL__P2 /*!< Px = P2 */ -#define CAPTIOPOSEL__P3 CAPTIO_CTL_POSEL__P3 /*!< Px = P3 */ -#define CAPTIOPOSEL__P4 CAPTIO_CTL_POSEL__P4 /*!< Px = P4 */ -#define CAPTIOPOSEL__P5 CAPTIO_CTL_POSEL__P5 /*!< Px = P5 */ -#define CAPTIOPOSEL__P6 CAPTIO_CTL_POSEL__P6 /*!< Px = P6 */ -#define CAPTIOPOSEL__P7 CAPTIO_CTL_POSEL__P7 /*!< Px = P7 */ -#define CAPTIOPOSEL__P8 CAPTIO_CTL_POSEL__P8 /*!< Px = P8 */ -#define CAPTIOPOSEL__P9 CAPTIO_CTL_POSEL__P9 /*!< Px = P9 */ -#define CAPTIOPOSEL__P10 CAPTIO_CTL_POSEL__P10 /*!< Px = P10 */ -#define CAPTIOPOSEL__P11 CAPTIO_CTL_POSEL__P11 /*!< Px = P11 */ -#define CAPTIOPOSEL__P12 CAPTIO_CTL_POSEL__P12 /*!< Px = P12 */ -#define CAPTIOPOSEL__P13 CAPTIO_CTL_POSEL__P13 /*!< Px = P13 */ -#define CAPTIOPOSEL__P14 CAPTIO_CTL_POSEL__P14 /*!< Px = P14 */ -#define CAPTIOPOSEL__P15 CAPTIO_CTL_POSEL__P15 /*!< Px = P15 */ -/* CAPTIO0CTL[CAPTIOEN] Bits */ -#define CAPTIOEN_OFS CAPTIO_CTL_EN_OFS /*!< CAPTIOEN Offset */ -#define CAPTIOEN CAPTIO_CTL_EN /*!< Capacitive Touch IO enable */ -/* CAPTIO0CTL[CAPTIOSTATE] Bits */ -#define CAPTIOSTATE_OFS CAPTIO_CTL_STATE_OFS /*!< CAPTIOSTATE Offset */ -#define CAPTIOSTATE CAPTIO_CTL_STATE /*!< Capacitive Touch IO state */ - -/****************************************************************************** -* COMP_E Bits (legacy section) -******************************************************************************/ -/* CE0CTL0[CEIPSEL] Bits */ -#define CEIPSEL_OFS COMP_E_CTL0_IPSEL_OFS /*!< CEIPSEL Offset */ -#define CEIPSEL_M COMP_E_CTL0_IPSEL_MASK /*!< Channel input selected for the V+ terminal */ -#define CEIPSEL0 COMP_E_CTL0_IPSEL0 /*!< CEIPSEL Bit 0 */ -#define CEIPSEL1 COMP_E_CTL0_IPSEL1 /*!< CEIPSEL Bit 1 */ -#define CEIPSEL2 COMP_E_CTL0_IPSEL2 /*!< CEIPSEL Bit 2 */ -#define CEIPSEL3 COMP_E_CTL0_IPSEL3 /*!< CEIPSEL Bit 3 */ -#define CEIPSEL_0 COMP_E_CTL0_IPSEL_0 /*!< Channel 0 selected */ -#define CEIPSEL_1 COMP_E_CTL0_IPSEL_1 /*!< Channel 1 selected */ -#define CEIPSEL_2 COMP_E_CTL0_IPSEL_2 /*!< Channel 2 selected */ -#define CEIPSEL_3 COMP_E_CTL0_IPSEL_3 /*!< Channel 3 selected */ -#define CEIPSEL_4 COMP_E_CTL0_IPSEL_4 /*!< Channel 4 selected */ -#define CEIPSEL_5 COMP_E_CTL0_IPSEL_5 /*!< Channel 5 selected */ -#define CEIPSEL_6 COMP_E_CTL0_IPSEL_6 /*!< Channel 6 selected */ -#define CEIPSEL_7 COMP_E_CTL0_IPSEL_7 /*!< Channel 7 selected */ -#define CEIPSEL_8 COMP_E_CTL0_IPSEL_8 /*!< Channel 8 selected */ -#define CEIPSEL_9 COMP_E_CTL0_IPSEL_9 /*!< Channel 9 selected */ -#define CEIPSEL_10 COMP_E_CTL0_IPSEL_10 /*!< Channel 10 selected */ -#define CEIPSEL_11 COMP_E_CTL0_IPSEL_11 /*!< Channel 11 selected */ -#define CEIPSEL_12 COMP_E_CTL0_IPSEL_12 /*!< Channel 12 selected */ -#define CEIPSEL_13 COMP_E_CTL0_IPSEL_13 /*!< Channel 13 selected */ -#define CEIPSEL_14 COMP_E_CTL0_IPSEL_14 /*!< Channel 14 selected */ -#define CEIPSEL_15 COMP_E_CTL0_IPSEL_15 /*!< Channel 15 selected */ -/* CE0CTL0[CEIPEN] Bits */ -#define CEIPEN_OFS COMP_E_CTL0_IPEN_OFS /*!< CEIPEN Offset */ -#define CEIPEN COMP_E_CTL0_IPEN /*!< Channel input enable for the V+ terminal */ -/* CE0CTL0[CEIMSEL] Bits */ -#define CEIMSEL_OFS COMP_E_CTL0_IMSEL_OFS /*!< CEIMSEL Offset */ -#define CEIMSEL_M COMP_E_CTL0_IMSEL_MASK /*!< Channel input selected for the - terminal */ -#define CEIMSEL0 COMP_E_CTL0_IMSEL0 /*!< CEIMSEL Bit 0 */ -#define CEIMSEL1 COMP_E_CTL0_IMSEL1 /*!< CEIMSEL Bit 1 */ -#define CEIMSEL2 COMP_E_CTL0_IMSEL2 /*!< CEIMSEL Bit 2 */ -#define CEIMSEL3 COMP_E_CTL0_IMSEL3 /*!< CEIMSEL Bit 3 */ -#define CEIMSEL_0 COMP_E_CTL0_IMSEL_0 /*!< Channel 0 selected */ -#define CEIMSEL_1 COMP_E_CTL0_IMSEL_1 /*!< Channel 1 selected */ -#define CEIMSEL_2 COMP_E_CTL0_IMSEL_2 /*!< Channel 2 selected */ -#define CEIMSEL_3 COMP_E_CTL0_IMSEL_3 /*!< Channel 3 selected */ -#define CEIMSEL_4 COMP_E_CTL0_IMSEL_4 /*!< Channel 4 selected */ -#define CEIMSEL_5 COMP_E_CTL0_IMSEL_5 /*!< Channel 5 selected */ -#define CEIMSEL_6 COMP_E_CTL0_IMSEL_6 /*!< Channel 6 selected */ -#define CEIMSEL_7 COMP_E_CTL0_IMSEL_7 /*!< Channel 7 selected */ -#define CEIMSEL_8 COMP_E_CTL0_IMSEL_8 /*!< Channel 8 selected */ -#define CEIMSEL_9 COMP_E_CTL0_IMSEL_9 /*!< Channel 9 selected */ -#define CEIMSEL_10 COMP_E_CTL0_IMSEL_10 /*!< Channel 10 selected */ -#define CEIMSEL_11 COMP_E_CTL0_IMSEL_11 /*!< Channel 11 selected */ -#define CEIMSEL_12 COMP_E_CTL0_IMSEL_12 /*!< Channel 12 selected */ -#define CEIMSEL_13 COMP_E_CTL0_IMSEL_13 /*!< Channel 13 selected */ -#define CEIMSEL_14 COMP_E_CTL0_IMSEL_14 /*!< Channel 14 selected */ -#define CEIMSEL_15 COMP_E_CTL0_IMSEL_15 /*!< Channel 15 selected */ -/* CE0CTL0[CEIMEN] Bits */ -#define CEIMEN_OFS COMP_E_CTL0_IMEN_OFS /*!< CEIMEN Offset */ -#define CEIMEN COMP_E_CTL0_IMEN /*!< Channel input enable for the - terminal */ -/* CE0CTL1[CEOUT] Bits */ -#define CEOUT_OFS COMP_E_CTL1_OUT_OFS /*!< CEOUT Offset */ -#define CEOUT COMP_E_CTL1_OUT /*!< Comparator output value */ -/* CE0CTL1[CEOUTPOL] Bits */ -#define CEOUTPOL_OFS COMP_E_CTL1_OUTPOL_OFS /*!< CEOUTPOL Offset */ -#define CEOUTPOL COMP_E_CTL1_OUTPOL /*!< Comparator output polarity */ -/* CE0CTL1[CEF] Bits */ -#define CEF_OFS COMP_E_CTL1_F_OFS /*!< CEF Offset */ -#define CEF COMP_E_CTL1_F /*!< Comparator output filter */ -/* CE0CTL1[CEIES] Bits */ -#define CEIES_OFS COMP_E_CTL1_IES_OFS /*!< CEIES Offset */ -#define CEIES COMP_E_CTL1_IES /*!< Interrupt edge select for CEIIFG and CEIFG */ -/* CE0CTL1[CESHORT] Bits */ -#define CESHORT_OFS COMP_E_CTL1_SHORT_OFS /*!< CESHORT Offset */ -#define CESHORT COMP_E_CTL1_SHORT /*!< Input short */ -/* CE0CTL1[CEEX] Bits */ -#define CEEX_OFS COMP_E_CTL1_EX_OFS /*!< CEEX Offset */ -#define CEEX COMP_E_CTL1_EX /*!< Exchange */ -/* CE0CTL1[CEFDLY] Bits */ -#define CEFDLY_OFS COMP_E_CTL1_FDLY_OFS /*!< CEFDLY Offset */ -#define CEFDLY_M COMP_E_CTL1_FDLY_MASK /*!< Filter delay */ -#define CEFDLY0 COMP_E_CTL1_FDLY0 /*!< CEFDLY Bit 0 */ -#define CEFDLY1 COMP_E_CTL1_FDLY1 /*!< CEFDLY Bit 1 */ -#define CEFDLY_0 COMP_E_CTL1_FDLY_0 /*!< Typical filter delay of TBD (450) ns */ -#define CEFDLY_1 COMP_E_CTL1_FDLY_1 /*!< Typical filter delay of TBD (900) ns */ -#define CEFDLY_2 COMP_E_CTL1_FDLY_2 /*!< Typical filter delay of TBD (1800) ns */ -#define CEFDLY_3 COMP_E_CTL1_FDLY_3 /*!< Typical filter delay of TBD (3600) ns */ -/* CE0CTL1[CEPWRMD] Bits */ -#define CEPWRMD_OFS COMP_E_CTL1_PWRMD_OFS /*!< CEPWRMD Offset */ -#define CEPWRMD_M COMP_E_CTL1_PWRMD_MASK /*!< Power Mode */ -#define CEPWRMD0 COMP_E_CTL1_PWRMD0 /*!< CEPWRMD Bit 0 */ -#define CEPWRMD1 COMP_E_CTL1_PWRMD1 /*!< CEPWRMD Bit 1 */ -#define CEPWRMD_0 COMP_E_CTL1_PWRMD_0 /*!< High-speed mode */ -#define CEPWRMD_1 COMP_E_CTL1_PWRMD_1 /*!< Normal mode */ -#define CEPWRMD_2 COMP_E_CTL1_PWRMD_2 /*!< Ultra-low power mode */ -/* CE0CTL1[CEON] Bits */ -#define CEON_OFS COMP_E_CTL1_ON_OFS /*!< CEON Offset */ -#define CEON COMP_E_CTL1_ON /*!< Comparator On */ -/* CE0CTL1[CEMRVL] Bits */ -#define CEMRVL_OFS COMP_E_CTL1_MRVL_OFS /*!< CEMRVL Offset */ -#define CEMRVL COMP_E_CTL1_MRVL /*!< This bit is valid of CEMRVS is set to 1 */ -/* CE0CTL1[CEMRVS] Bits */ -#define CEMRVS_OFS COMP_E_CTL1_MRVS_OFS /*!< CEMRVS Offset */ -#define CEMRVS COMP_E_CTL1_MRVS -/* CE0CTL2[CEREF0] Bits */ -#define CEREF0_OFS COMP_E_CTL2_REF0_OFS /*!< CEREF0 Offset */ -#define CEREF0_M COMP_E_CTL2_REF0_MASK /*!< Reference resistor tap 0 */ -#define CEREF00 COMP_E_CTL2_REF00 /*!< CEREF0 Bit 0 */ -#define CEREF01 COMP_E_CTL2_REF01 /*!< CEREF0 Bit 1 */ -#define CEREF02 COMP_E_CTL2_REF02 /*!< CEREF0 Bit 2 */ -#define CEREF03 COMP_E_CTL2_REF03 /*!< CEREF0 Bit 3 */ -#define CEREF04 COMP_E_CTL2_REF04 /*!< CEREF0 Bit 4 */ -#define CEREF0_0 COMP_E_CTL2_REF0_0 /*!< Reference resistor tap for setting 0. */ -#define CEREF0_1 COMP_E_CTL2_REF0_1 /*!< Reference resistor tap for setting 1. */ -#define CEREF0_2 COMP_E_CTL2_REF0_2 /*!< Reference resistor tap for setting 2. */ -#define CEREF0_3 COMP_E_CTL2_REF0_3 /*!< Reference resistor tap for setting 3. */ -#define CEREF0_4 COMP_E_CTL2_REF0_4 /*!< Reference resistor tap for setting 4. */ -#define CEREF0_5 COMP_E_CTL2_REF0_5 /*!< Reference resistor tap for setting 5. */ -#define CEREF0_6 COMP_E_CTL2_REF0_6 /*!< Reference resistor tap for setting 6. */ -#define CEREF0_7 COMP_E_CTL2_REF0_7 /*!< Reference resistor tap for setting 7. */ -#define CEREF0_8 COMP_E_CTL2_REF0_8 /*!< Reference resistor tap for setting 8. */ -#define CEREF0_9 COMP_E_CTL2_REF0_9 /*!< Reference resistor tap for setting 9. */ -#define CEREF0_10 COMP_E_CTL2_REF0_10 /*!< Reference resistor tap for setting 10. */ -#define CEREF0_11 COMP_E_CTL2_REF0_11 /*!< Reference resistor tap for setting 11. */ -#define CEREF0_12 COMP_E_CTL2_REF0_12 /*!< Reference resistor tap for setting 12. */ -#define CEREF0_13 COMP_E_CTL2_REF0_13 /*!< Reference resistor tap for setting 13. */ -#define CEREF0_14 COMP_E_CTL2_REF0_14 /*!< Reference resistor tap for setting 14. */ -#define CEREF0_15 COMP_E_CTL2_REF0_15 /*!< Reference resistor tap for setting 15. */ -#define CEREF0_16 COMP_E_CTL2_REF0_16 /*!< Reference resistor tap for setting 16. */ -#define CEREF0_17 COMP_E_CTL2_REF0_17 /*!< Reference resistor tap for setting 17. */ -#define CEREF0_18 COMP_E_CTL2_REF0_18 /*!< Reference resistor tap for setting 18. */ -#define CEREF0_19 COMP_E_CTL2_REF0_19 /*!< Reference resistor tap for setting 19. */ -#define CEREF0_20 COMP_E_CTL2_REF0_20 /*!< Reference resistor tap for setting 20. */ -#define CEREF0_21 COMP_E_CTL2_REF0_21 /*!< Reference resistor tap for setting 21. */ -#define CEREF0_22 COMP_E_CTL2_REF0_22 /*!< Reference resistor tap for setting 22. */ -#define CEREF0_23 COMP_E_CTL2_REF0_23 /*!< Reference resistor tap for setting 23. */ -#define CEREF0_24 COMP_E_CTL2_REF0_24 /*!< Reference resistor tap for setting 24. */ -#define CEREF0_25 COMP_E_CTL2_REF0_25 /*!< Reference resistor tap for setting 25. */ -#define CEREF0_26 COMP_E_CTL2_REF0_26 /*!< Reference resistor tap for setting 26. */ -#define CEREF0_27 COMP_E_CTL2_REF0_27 /*!< Reference resistor tap for setting 27. */ -#define CEREF0_28 COMP_E_CTL2_REF0_28 /*!< Reference resistor tap for setting 28. */ -#define CEREF0_29 COMP_E_CTL2_REF0_29 /*!< Reference resistor tap for setting 29. */ -#define CEREF0_30 COMP_E_CTL2_REF0_30 /*!< Reference resistor tap for setting 30. */ -#define CEREF0_31 COMP_E_CTL2_REF0_31 /*!< Reference resistor tap for setting 31. */ -/* CE0CTL2[CERSEL] Bits */ -#define CERSEL_OFS COMP_E_CTL2_RSEL_OFS /*!< CERSEL Offset */ -#define CERSEL COMP_E_CTL2_RSEL /*!< Reference select */ -/* CE0CTL2[CERS] Bits */ -#define CERS_OFS COMP_E_CTL2_RS_OFS /*!< CERS Offset */ -#define CERS_M COMP_E_CTL2_RS_MASK /*!< Reference source */ -#define CERS0 COMP_E_CTL2_RS0 /*!< CERS Bit 0 */ -#define CERS1 COMP_E_CTL2_RS1 /*!< CERS Bit 1 */ -#define CERS_0 COMP_E_CTL2_RS_0 /*!< No current is drawn by the reference circuitry */ -#define CERS_1 COMP_E_CTL2_RS_1 /*!< VCC applied to the resistor ladder */ -#define CERS_2 COMP_E_CTL2_RS_2 /*!< Shared reference voltage applied to the resistor ladder */ -#define CERS_3 COMP_E_CTL2_RS_3 /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ -/* CE0CTL2[CEREF1] Bits */ -#define CEREF1_OFS COMP_E_CTL2_REF1_OFS /*!< CEREF1 Offset */ -#define CEREF1_M COMP_E_CTL2_REF1_MASK /*!< Reference resistor tap 1 */ -#define CEREF10 COMP_E_CTL2_REF10 /*!< CEREF1 Bit 0 */ -#define CEREF11 COMP_E_CTL2_REF11 /*!< CEREF1 Bit 1 */ -#define CEREF12 COMP_E_CTL2_REF12 /*!< CEREF1 Bit 2 */ -#define CEREF13 COMP_E_CTL2_REF13 /*!< CEREF1 Bit 3 */ -#define CEREF14 COMP_E_CTL2_REF14 /*!< CEREF1 Bit 4 */ -#define CEREF1_0 COMP_E_CTL2_REF1_0 /*!< Reference resistor tap for setting 0. */ -#define CEREF1_1 COMP_E_CTL2_REF1_1 /*!< Reference resistor tap for setting 1. */ -#define CEREF1_2 COMP_E_CTL2_REF1_2 /*!< Reference resistor tap for setting 2. */ -#define CEREF1_3 COMP_E_CTL2_REF1_3 /*!< Reference resistor tap for setting 3. */ -#define CEREF1_4 COMP_E_CTL2_REF1_4 /*!< Reference resistor tap for setting 4. */ -#define CEREF1_5 COMP_E_CTL2_REF1_5 /*!< Reference resistor tap for setting 5. */ -#define CEREF1_6 COMP_E_CTL2_REF1_6 /*!< Reference resistor tap for setting 6. */ -#define CEREF1_7 COMP_E_CTL2_REF1_7 /*!< Reference resistor tap for setting 7. */ -#define CEREF1_8 COMP_E_CTL2_REF1_8 /*!< Reference resistor tap for setting 8. */ -#define CEREF1_9 COMP_E_CTL2_REF1_9 /*!< Reference resistor tap for setting 9. */ -#define CEREF1_10 COMP_E_CTL2_REF1_10 /*!< Reference resistor tap for setting 10. */ -#define CEREF1_11 COMP_E_CTL2_REF1_11 /*!< Reference resistor tap for setting 11. */ -#define CEREF1_12 COMP_E_CTL2_REF1_12 /*!< Reference resistor tap for setting 12. */ -#define CEREF1_13 COMP_E_CTL2_REF1_13 /*!< Reference resistor tap for setting 13. */ -#define CEREF1_14 COMP_E_CTL2_REF1_14 /*!< Reference resistor tap for setting 14. */ -#define CEREF1_15 COMP_E_CTL2_REF1_15 /*!< Reference resistor tap for setting 15. */ -#define CEREF1_16 COMP_E_CTL2_REF1_16 /*!< Reference resistor tap for setting 16. */ -#define CEREF1_17 COMP_E_CTL2_REF1_17 /*!< Reference resistor tap for setting 17. */ -#define CEREF1_18 COMP_E_CTL2_REF1_18 /*!< Reference resistor tap for setting 18. */ -#define CEREF1_19 COMP_E_CTL2_REF1_19 /*!< Reference resistor tap for setting 19. */ -#define CEREF1_20 COMP_E_CTL2_REF1_20 /*!< Reference resistor tap for setting 20. */ -#define CEREF1_21 COMP_E_CTL2_REF1_21 /*!< Reference resistor tap for setting 21. */ -#define CEREF1_22 COMP_E_CTL2_REF1_22 /*!< Reference resistor tap for setting 22. */ -#define CEREF1_23 COMP_E_CTL2_REF1_23 /*!< Reference resistor tap for setting 23. */ -#define CEREF1_24 COMP_E_CTL2_REF1_24 /*!< Reference resistor tap for setting 24. */ -#define CEREF1_25 COMP_E_CTL2_REF1_25 /*!< Reference resistor tap for setting 25. */ -#define CEREF1_26 COMP_E_CTL2_REF1_26 /*!< Reference resistor tap for setting 26. */ -#define CEREF1_27 COMP_E_CTL2_REF1_27 /*!< Reference resistor tap for setting 27. */ -#define CEREF1_28 COMP_E_CTL2_REF1_28 /*!< Reference resistor tap for setting 28. */ -#define CEREF1_29 COMP_E_CTL2_REF1_29 /*!< Reference resistor tap for setting 29. */ -#define CEREF1_30 COMP_E_CTL2_REF1_30 /*!< Reference resistor tap for setting 30. */ -#define CEREF1_31 COMP_E_CTL2_REF1_31 /*!< Reference resistor tap for setting 31. */ -/* CE0CTL2[CEREFL] Bits */ -#define CEREFL_OFS COMP_E_CTL2_REFL_OFS /*!< CEREFL Offset */ -#define CEREFL_M COMP_E_CTL2_REFL_MASK /*!< Reference voltage level */ -#define CEREFL0 COMP_E_CTL2_REFL0 /*!< CEREFL Bit 0 */ -#define CEREFL1 COMP_E_CTL2_REFL1 /*!< CEREFL Bit 1 */ -#define CEREFL_0 COMP_E_CTL2_CEREFL_0 /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define CEREFL_1 COMP_E_CTL2_CEREFL_1 /*!< 1.2 V is selected as shared reference voltage input */ -#define CEREFL_2 COMP_E_CTL2_CEREFL_2 /*!< 2.0 V is selected as shared reference voltage input */ -#define CEREFL_3 COMP_E_CTL2_CEREFL_3 /*!< 2.5 V is selected as shared reference voltage input */ -#define CEREFL__OFF COMP_E_CTL2_REFL__OFF /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define CEREFL__1P2V COMP_E_CTL2_REFL__1P2V /*!< 1.2 V is selected as shared reference voltage input */ -#define CEREFL__2P0V COMP_E_CTL2_REFL__2P0V /*!< 2.0 V is selected as shared reference voltage input */ -#define CEREFL__2P5V COMP_E_CTL2_REFL__2P5V /*!< 2.5 V is selected as shared reference voltage input */ -/* CE0CTL2[CEREFACC] Bits */ -#define CEREFACC_OFS COMP_E_CTL2_REFACC_OFS /*!< CEREFACC Offset */ -#define CEREFACC COMP_E_CTL2_REFACC /*!< Reference accuracy */ -/* CE0CTL3[CEPD0] Bits */ -#define CEPD0_OFS COMP_E_CTL3_PD0_OFS /*!< CEPD0 Offset */ -#define CEPD0 COMP_E_CTL3_PD0 /*!< Port disable */ -/* CE0CTL3[CEPD1] Bits */ -#define CEPD1_OFS COMP_E_CTL3_PD1_OFS /*!< CEPD1 Offset */ -#define CEPD1 COMP_E_CTL3_PD1 /*!< Port disable */ -/* CE0CTL3[CEPD2] Bits */ -#define CEPD2_OFS COMP_E_CTL3_PD2_OFS /*!< CEPD2 Offset */ -#define CEPD2 COMP_E_CTL3_PD2 /*!< Port disable */ -/* CE0CTL3[CEPD3] Bits */ -#define CEPD3_OFS COMP_E_CTL3_PD3_OFS /*!< CEPD3 Offset */ -#define CEPD3 COMP_E_CTL3_PD3 /*!< Port disable */ -/* CE0CTL3[CEPD4] Bits */ -#define CEPD4_OFS COMP_E_CTL3_PD4_OFS /*!< CEPD4 Offset */ -#define CEPD4 COMP_E_CTL3_PD4 /*!< Port disable */ -/* CE0CTL3[CEPD5] Bits */ -#define CEPD5_OFS COMP_E_CTL3_PD5_OFS /*!< CEPD5 Offset */ -#define CEPD5 COMP_E_CTL3_PD5 /*!< Port disable */ -/* CE0CTL3[CEPD6] Bits */ -#define CEPD6_OFS COMP_E_CTL3_PD6_OFS /*!< CEPD6 Offset */ -#define CEPD6 COMP_E_CTL3_PD6 /*!< Port disable */ -/* CE0CTL3[CEPD7] Bits */ -#define CEPD7_OFS COMP_E_CTL3_PD7_OFS /*!< CEPD7 Offset */ -#define CEPD7 COMP_E_CTL3_PD7 /*!< Port disable */ -/* CE0CTL3[CEPD8] Bits */ -#define CEPD8_OFS COMP_E_CTL3_PD8_OFS /*!< CEPD8 Offset */ -#define CEPD8 COMP_E_CTL3_PD8 /*!< Port disable */ -/* CE0CTL3[CEPD9] Bits */ -#define CEPD9_OFS COMP_E_CTL3_PD9_OFS /*!< CEPD9 Offset */ -#define CEPD9 COMP_E_CTL3_PD9 /*!< Port disable */ -/* CE0CTL3[CEPD10] Bits */ -#define CEPD10_OFS COMP_E_CTL3_PD10_OFS /*!< CEPD10 Offset */ -#define CEPD10 COMP_E_CTL3_PD10 /*!< Port disable */ -/* CE0CTL3[CEPD11] Bits */ -#define CEPD11_OFS COMP_E_CTL3_PD11_OFS /*!< CEPD11 Offset */ -#define CEPD11 COMP_E_CTL3_PD11 /*!< Port disable */ -/* CE0CTL3[CEPD12] Bits */ -#define CEPD12_OFS COMP_E_CTL3_PD12_OFS /*!< CEPD12 Offset */ -#define CEPD12 COMP_E_CTL3_PD12 /*!< Port disable */ -/* CE0CTL3[CEPD13] Bits */ -#define CEPD13_OFS COMP_E_CTL3_PD13_OFS /*!< CEPD13 Offset */ -#define CEPD13 COMP_E_CTL3_PD13 /*!< Port disable */ -/* CE0CTL3[CEPD14] Bits */ -#define CEPD14_OFS COMP_E_CTL3_PD14_OFS /*!< CEPD14 Offset */ -#define CEPD14 COMP_E_CTL3_PD14 /*!< Port disable */ -/* CE0CTL3[CEPD15] Bits */ -#define CEPD15_OFS COMP_E_CTL3_PD15_OFS /*!< CEPD15 Offset */ -#define CEPD15 COMP_E_CTL3_PD15 /*!< Port disable */ -/* CE0INT[CEIFG] Bits */ -#define CEIFG_OFS COMP_E_INT_IFG_OFS /*!< CEIFG Offset */ -#define CEIFG COMP_E_INT_IFG /*!< Comparator output interrupt flag */ -/* CE0INT[CEIIFG] Bits */ -#define CEIIFG_OFS COMP_E_INT_IIFG_OFS /*!< CEIIFG Offset */ -#define CEIIFG COMP_E_INT_IIFG /*!< Comparator output inverted interrupt flag */ -/* CE0INT[CERDYIFG] Bits */ -#define CERDYIFG_OFS COMP_E_INT_RDYIFG_OFS /*!< CERDYIFG Offset */ -#define CERDYIFG COMP_E_INT_RDYIFG /*!< Comparator ready interrupt flag */ -/* CE0INT[CEIE] Bits */ -#define CEIE_OFS COMP_E_INT_IE_OFS /*!< CEIE Offset */ -#define CEIE COMP_E_INT_IE /*!< Comparator output interrupt enable */ -/* CE0INT[CEIIE] Bits */ -#define CEIIE_OFS COMP_E_INT_IIE_OFS /*!< CEIIE Offset */ -#define CEIIE COMP_E_INT_IIE /*!< Comparator output interrupt enable inverted polarity */ -/* CE0INT[CERDYIE] Bits */ -#define CERDYIE_OFS COMP_E_INT_RDYIE_OFS /*!< CERDYIE Offset */ -#define CERDYIE COMP_E_INT_RDYIE /*!< Comparator ready interrupt enable */ - -/****************************************************************************** -* CRC32 Bits (legacy section) -******************************************************************************/ -/* DIO_PAIN[P1IN] Bits */ -#define P1IN_OFS ( 0) /*!< P1IN Offset */ -#define P1IN_M (0x00ff) /*!< Port 1 Input */ -/* DIO_PAIN[P2IN] Bits */ -#define P2IN_OFS ( 8) /*!< P2IN Offset */ -#define P2IN_M (0xff00) /*!< Port 2 Input */ -/* DIO_PAOUT[P2OUT] Bits */ -#define P2OUT_OFS ( 8) /*!< P2OUT Offset */ -#define P2OUT_M (0xff00) /*!< Port 2 Output */ -/* DIO_PAOUT[P1OUT] Bits */ -#define P1OUT_OFS ( 0) /*!< P1OUT Offset */ -#define P1OUT_M (0x00ff) /*!< Port 1 Output */ -/* DIO_PADIR[P1DIR] Bits */ -#define P1DIR_OFS ( 0) /*!< P1DIR Offset */ -#define P1DIR_M (0x00ff) /*!< Port 1 Direction */ -/* DIO_PADIR[P2DIR] Bits */ -#define P2DIR_OFS ( 8) /*!< P2DIR Offset */ -#define P2DIR_M (0xff00) /*!< Port 2 Direction */ -/* DIO_PAREN[P1REN] Bits */ -#define P1REN_OFS ( 0) /*!< P1REN Offset */ -#define P1REN_M (0x00ff) /*!< Port 1 Resistor Enable */ -/* DIO_PAREN[P2REN] Bits */ -#define P2REN_OFS ( 8) /*!< P2REN Offset */ -#define P2REN_M (0xff00) /*!< Port 2 Resistor Enable */ -/* DIO_PADS[P1DS] Bits */ -#define P1DS_OFS ( 0) /*!< P1DS Offset */ -#define P1DS_M (0x00ff) /*!< Port 1 Drive Strength */ -/* DIO_PADS[P2DS] Bits */ -#define P2DS_OFS ( 8) /*!< P2DS Offset */ -#define P2DS_M (0xff00) /*!< Port 2 Drive Strength */ -/* DIO_PASEL0[P1SEL0] Bits */ -#define P1SEL0_OFS ( 0) /*!< P1SEL0 Offset */ -#define P1SEL0_M (0x00ff) /*!< Port 1 Select 0 */ -/* DIO_PASEL0[P2SEL0] Bits */ -#define P2SEL0_OFS ( 8) /*!< P2SEL0 Offset */ -#define P2SEL0_M (0xff00) /*!< Port 2 Select 0 */ -/* DIO_PASEL1[P1SEL1] Bits */ -#define P1SEL1_OFS ( 0) /*!< P1SEL1 Offset */ -#define P1SEL1_M (0x00ff) /*!< Port 1 Select 1 */ -/* DIO_PASEL1[P2SEL1] Bits */ -#define P2SEL1_OFS ( 8) /*!< P2SEL1 Offset */ -#define P2SEL1_M (0xff00) /*!< Port 2 Select 1 */ -/* DIO_P1IV[P1IV] Bits */ -#define P1IV_OFS ( 0) /*!< P1IV Offset */ -#define P1IV_M (0x001f) /*!< Port 1 interrupt vector value */ -#define P1IV0 (0x0001) /*!< Port 1 interrupt vector value */ -#define P1IV1 (0x0002) /*!< Port 1 interrupt vector value */ -#define P1IV2 (0x0004) /*!< Port 1 interrupt vector value */ -#define P1IV3 (0x0008) /*!< Port 1 interrupt vector value */ -#define P1IV4 (0x0010) /*!< Port 1 interrupt vector value */ -#define P1IV_0 (0x0000) /*!< No interrupt pending */ -#define P1IV_2 (0x0002) /*!< Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */ -#define P1IV_4 (0x0004) /*!< Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */ -#define P1IV_6 (0x0006) /*!< Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */ -#define P1IV_8 (0x0008) /*!< Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */ -#define P1IV_10 (0x000a) /*!< Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */ -#define P1IV_12 (0x000c) /*!< Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */ -#define P1IV_14 (0x000e) /*!< Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */ -#define P1IV_16 (0x0010) /*!< Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */ -#define P1IV__NONE (0x0000) /*!< No interrupt pending */ -#define P1IV__P1IFG0 (0x0002) /*!< Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */ -#define P1IV__P1IFG1 (0x0004) /*!< Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */ -#define P1IV__P1IFG2 (0x0006) /*!< Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */ -#define P1IV__P1IFG3 (0x0008) /*!< Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */ -#define P1IV__P1IFG4 (0x000a) /*!< Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */ -#define P1IV__P1IFG5 (0x000c) /*!< Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */ -#define P1IV__P1IFG6 (0x000e) /*!< Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */ -#define P1IV__P1IFG7 (0x0010) /*!< Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */ -/* DIO_PASELC[P1SELC] Bits */ -#define P1SELC_OFS ( 0) /*!< P1SELC Offset */ -#define P1SELC_M (0x00ff) /*!< Port 1 Complement Select */ -/* DIO_PASELC[P2SELC] Bits */ -#define P2SELC_OFS ( 8) /*!< P2SELC Offset */ -#define P2SELC_M (0xff00) /*!< Port 2 Complement Select */ -/* DIO_PAIES[P1IES] Bits */ -#define P1IES_OFS ( 0) /*!< P1IES Offset */ -#define P1IES_M (0x00ff) /*!< Port 1 Interrupt Edge Select */ -/* DIO_PAIES[P2IES] Bits */ -#define P2IES_OFS ( 8) /*!< P2IES Offset */ -#define P2IES_M (0xff00) /*!< Port 2 Interrupt Edge Select */ -/* DIO_PAIE[P1IE] Bits */ -#define P1IE_OFS ( 0) /*!< P1IE Offset */ -#define P1IE_M (0x00ff) /*!< Port 1 Interrupt Enable */ -/* DIO_PAIE[P2IE] Bits */ -#define P2IE_OFS ( 8) /*!< P2IE Offset */ -#define P2IE_M (0xff00) /*!< Port 2 Interrupt Enable */ -/* DIO_PAIFG[P1IFG] Bits */ -#define P1IFG_OFS ( 0) /*!< P1IFG Offset */ -#define P1IFG_M (0x00ff) /*!< Port 1 Interrupt Flag */ -/* DIO_PAIFG[P2IFG] Bits */ -#define P2IFG_OFS ( 8) /*!< P2IFG Offset */ -#define P2IFG_M (0xff00) /*!< Port 2 Interrupt Flag */ -/* DIO_P2IV[P2IV] Bits */ -#define P2IV_OFS ( 0) /*!< P2IV Offset */ -#define P2IV_M (0x001f) /*!< Port 2 interrupt vector value */ -#define P2IV0 (0x0001) /*!< Port 2 interrupt vector value */ -#define P2IV1 (0x0002) /*!< Port 2 interrupt vector value */ -#define P2IV2 (0x0004) /*!< Port 2 interrupt vector value */ -#define P2IV3 (0x0008) /*!< Port 2 interrupt vector value */ -#define P2IV4 (0x0010) /*!< Port 2 interrupt vector value */ -#define P2IV_0 (0x0000) /*!< No interrupt pending */ -#define P2IV_2 (0x0002) /*!< Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */ -#define P2IV_4 (0x0004) /*!< Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */ -#define P2IV_6 (0x0006) /*!< Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */ -#define P2IV_8 (0x0008) /*!< Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */ -#define P2IV_10 (0x000a) /*!< Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */ -#define P2IV_12 (0x000c) /*!< Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */ -#define P2IV_14 (0x000e) /*!< Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */ -#define P2IV_16 (0x0010) /*!< Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */ -#define P2IV__NONE (0x0000) /*!< No interrupt pending */ -#define P2IV__P2IFG0 (0x0002) /*!< Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */ -#define P2IV__P2IFG1 (0x0004) /*!< Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */ -#define P2IV__P2IFG2 (0x0006) /*!< Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */ -#define P2IV__P2IFG3 (0x0008) /*!< Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */ -#define P2IV__P2IFG4 (0x000a) /*!< Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */ -#define P2IV__P2IFG5 (0x000c) /*!< Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */ -#define P2IV__P2IFG6 (0x000e) /*!< Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */ -#define P2IV__P2IFG7 (0x0010) /*!< Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */ -/* DIO_PBIN[P3IN] Bits */ -#define P3IN_OFS ( 0) /*!< P3IN Offset */ -#define P3IN_M (0x00ff) /*!< Port 3 Input */ -/* DIO_PBIN[P4IN] Bits */ -#define P4IN_OFS ( 8) /*!< P4IN Offset */ -#define P4IN_M (0xff00) /*!< Port 4 Input */ -/* DIO_PBOUT[P3OUT] Bits */ -#define P3OUT_OFS ( 0) /*!< P3OUT Offset */ -#define P3OUT_M (0x00ff) /*!< Port 3 Output */ -/* DIO_PBOUT[P4OUT] Bits */ -#define P4OUT_OFS ( 8) /*!< P4OUT Offset */ -#define P4OUT_M (0xff00) /*!< Port 4 Output */ -/* DIO_PBDIR[P3DIR] Bits */ -#define P3DIR_OFS ( 0) /*!< P3DIR Offset */ -#define P3DIR_M (0x00ff) /*!< Port 3 Direction */ -/* DIO_PBDIR[P4DIR] Bits */ -#define P4DIR_OFS ( 8) /*!< P4DIR Offset */ -#define P4DIR_M (0xff00) /*!< Port 4 Direction */ -/* DIO_PBREN[P3REN] Bits */ -#define P3REN_OFS ( 0) /*!< P3REN Offset */ -#define P3REN_M (0x00ff) /*!< Port 3 Resistor Enable */ -/* DIO_PBREN[P4REN] Bits */ -#define P4REN_OFS ( 8) /*!< P4REN Offset */ -#define P4REN_M (0xff00) /*!< Port 4 Resistor Enable */ -/* DIO_PBDS[P3DS] Bits */ -#define P3DS_OFS ( 0) /*!< P3DS Offset */ -#define P3DS_M (0x00ff) /*!< Port 3 Drive Strength */ -/* DIO_PBDS[P4DS] Bits */ -#define P4DS_OFS ( 8) /*!< P4DS Offset */ -#define P4DS_M (0xff00) /*!< Port 4 Drive Strength */ -/* DIO_PBSEL0[P4SEL0] Bits */ -#define P4SEL0_OFS ( 8) /*!< P4SEL0 Offset */ -#define P4SEL0_M (0xff00) /*!< Port 4 Select 0 */ -/* DIO_PBSEL0[P3SEL0] Bits */ -#define P3SEL0_OFS ( 0) /*!< P3SEL0 Offset */ -#define P3SEL0_M (0x00ff) /*!< Port 3 Select 0 */ -/* DIO_PBSEL1[P3SEL1] Bits */ -#define P3SEL1_OFS ( 0) /*!< P3SEL1 Offset */ -#define P3SEL1_M (0x00ff) /*!< Port 3 Select 1 */ -/* DIO_PBSEL1[P4SEL1] Bits */ -#define P4SEL1_OFS ( 8) /*!< P4SEL1 Offset */ -#define P4SEL1_M (0xff00) /*!< Port 4 Select 1 */ -/* DIO_P3IV[P3IV] Bits */ -#define P3IV_OFS ( 0) /*!< P3IV Offset */ -#define P3IV_M (0x001f) /*!< Port 3 interrupt vector value */ -#define P3IV0 (0x0001) /*!< Port 3 interrupt vector value */ -#define P3IV1 (0x0002) /*!< Port 3 interrupt vector value */ -#define P3IV2 (0x0004) /*!< Port 3 interrupt vector value */ -#define P3IV3 (0x0008) /*!< Port 3 interrupt vector value */ -#define P3IV4 (0x0010) /*!< Port 3 interrupt vector value */ -#define P3IV_0 (0x0000) /*!< No interrupt pending */ -#define P3IV_2 (0x0002) /*!< Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */ -#define P3IV_4 (0x0004) /*!< Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */ -#define P3IV_6 (0x0006) /*!< Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */ -#define P3IV_8 (0x0008) /*!< Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */ -#define P3IV_10 (0x000a) /*!< Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */ -#define P3IV_12 (0x000c) /*!< Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */ -#define P3IV_14 (0x000e) /*!< Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */ -#define P3IV_16 (0x0010) /*!< Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */ -#define P3IV__NONE (0x0000) /*!< No interrupt pending */ -#define P3IV__P3IFG0 (0x0002) /*!< Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */ -#define P3IV__P3IFG1 (0x0004) /*!< Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */ -#define P3IV__P3IFG2 (0x0006) /*!< Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */ -#define P3IV__P3IFG3 (0x0008) /*!< Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */ -#define P3IV__P3IFG4 (0x000a) /*!< Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */ -#define P3IV__P3IFG5 (0x000c) /*!< Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */ -#define P3IV__P3IFG6 (0x000e) /*!< Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */ -#define P3IV__P3IFG7 (0x0010) /*!< Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */ -/* DIO_PBSELC[P3SELC] Bits */ -#define P3SELC_OFS ( 0) /*!< P3SELC Offset */ -#define P3SELC_M (0x00ff) /*!< Port 3 Complement Select */ -/* DIO_PBSELC[P4SELC] Bits */ -#define P4SELC_OFS ( 8) /*!< P4SELC Offset */ -#define P4SELC_M (0xff00) /*!< Port 4 Complement Select */ -/* DIO_PBIES[P3IES] Bits */ -#define P3IES_OFS ( 0) /*!< P3IES Offset */ -#define P3IES_M (0x00ff) /*!< Port 3 Interrupt Edge Select */ -/* DIO_PBIES[P4IES] Bits */ -#define P4IES_OFS ( 8) /*!< P4IES Offset */ -#define P4IES_M (0xff00) /*!< Port 4 Interrupt Edge Select */ -/* DIO_PBIE[P3IE] Bits */ -#define P3IE_OFS ( 0) /*!< P3IE Offset */ -#define P3IE_M (0x00ff) /*!< Port 3 Interrupt Enable */ -/* DIO_PBIE[P4IE] Bits */ -#define P4IE_OFS ( 8) /*!< P4IE Offset */ -#define P4IE_M (0xff00) /*!< Port 4 Interrupt Enable */ -/* DIO_PBIFG[P3IFG] Bits */ -#define P3IFG_OFS ( 0) /*!< P3IFG Offset */ -#define P3IFG_M (0x00ff) /*!< Port 3 Interrupt Flag */ -/* DIO_PBIFG[P4IFG] Bits */ -#define P4IFG_OFS ( 8) /*!< P4IFG Offset */ -#define P4IFG_M (0xff00) /*!< Port 4 Interrupt Flag */ -/* DIO_P4IV[P4IV] Bits */ -#define P4IV_OFS ( 0) /*!< P4IV Offset */ -#define P4IV_M (0x001f) /*!< Port 4 interrupt vector value */ -#define P4IV0 (0x0001) /*!< Port 4 interrupt vector value */ -#define P4IV1 (0x0002) /*!< Port 4 interrupt vector value */ -#define P4IV2 (0x0004) /*!< Port 4 interrupt vector value */ -#define P4IV3 (0x0008) /*!< Port 4 interrupt vector value */ -#define P4IV4 (0x0010) /*!< Port 4 interrupt vector value */ -#define P4IV_0 (0x0000) /*!< No interrupt pending */ -#define P4IV_2 (0x0002) /*!< Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */ -#define P4IV_4 (0x0004) /*!< Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */ -#define P4IV_6 (0x0006) /*!< Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */ -#define P4IV_8 (0x0008) /*!< Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */ -#define P4IV_10 (0x000a) /*!< Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */ -#define P4IV_12 (0x000c) /*!< Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */ -#define P4IV_14 (0x000e) /*!< Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */ -#define P4IV_16 (0x0010) /*!< Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */ -#define P4IV__NONE (0x0000) /*!< No interrupt pending */ -#define P4IV__P4IFG0 (0x0002) /*!< Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */ -#define P4IV__P4IFG1 (0x0004) /*!< Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */ -#define P4IV__P4IFG2 (0x0006) /*!< Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */ -#define P4IV__P4IFG3 (0x0008) /*!< Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */ -#define P4IV__P4IFG4 (0x000a) /*!< Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */ -#define P4IV__P4IFG5 (0x000c) /*!< Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */ -#define P4IV__P4IFG6 (0x000e) /*!< Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */ -#define P4IV__P4IFG7 (0x0010) /*!< Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */ -/* DIO_PCIN[P5IN] Bits */ -#define P5IN_OFS ( 0) /*!< P5IN Offset */ -#define P5IN_M (0x00ff) /*!< Port 5 Input */ -/* DIO_PCIN[P6IN] Bits */ -#define P6IN_OFS ( 8) /*!< P6IN Offset */ -#define P6IN_M (0xff00) /*!< Port 6 Input */ -/* DIO_PCOUT[P5OUT] Bits */ -#define P5OUT_OFS ( 0) /*!< P5OUT Offset */ -#define P5OUT_M (0x00ff) /*!< Port 5 Output */ -/* DIO_PCOUT[P6OUT] Bits */ -#define P6OUT_OFS ( 8) /*!< P6OUT Offset */ -#define P6OUT_M (0xff00) /*!< Port 6 Output */ -/* DIO_PCDIR[P5DIR] Bits */ -#define P5DIR_OFS ( 0) /*!< P5DIR Offset */ -#define P5DIR_M (0x00ff) /*!< Port 5 Direction */ -/* DIO_PCDIR[P6DIR] Bits */ -#define P6DIR_OFS ( 8) /*!< P6DIR Offset */ -#define P6DIR_M (0xff00) /*!< Port 6 Direction */ -/* DIO_PCREN[P5REN] Bits */ -#define P5REN_OFS ( 0) /*!< P5REN Offset */ -#define P5REN_M (0x00ff) /*!< Port 5 Resistor Enable */ -/* DIO_PCREN[P6REN] Bits */ -#define P6REN_OFS ( 8) /*!< P6REN Offset */ -#define P6REN_M (0xff00) /*!< Port 6 Resistor Enable */ -/* DIO_PCDS[P5DS] Bits */ -#define P5DS_OFS ( 0) /*!< P5DS Offset */ -#define P5DS_M (0x00ff) /*!< Port 5 Drive Strength */ -/* DIO_PCDS[P6DS] Bits */ -#define P6DS_OFS ( 8) /*!< P6DS Offset */ -#define P6DS_M (0xff00) /*!< Port 6 Drive Strength */ -/* DIO_PCSEL0[P5SEL0] Bits */ -#define P5SEL0_OFS ( 0) /*!< P5SEL0 Offset */ -#define P5SEL0_M (0x00ff) /*!< Port 5 Select 0 */ -/* DIO_PCSEL0[P6SEL0] Bits */ -#define P6SEL0_OFS ( 8) /*!< P6SEL0 Offset */ -#define P6SEL0_M (0xff00) /*!< Port 6 Select 0 */ -/* DIO_PCSEL1[P5SEL1] Bits */ -#define P5SEL1_OFS ( 0) /*!< P5SEL1 Offset */ -#define P5SEL1_M (0x00ff) /*!< Port 5 Select 1 */ -/* DIO_PCSEL1[P6SEL1] Bits */ -#define P6SEL1_OFS ( 8) /*!< P6SEL1 Offset */ -#define P6SEL1_M (0xff00) /*!< Port 6 Select 1 */ -/* DIO_P5IV[P5IV] Bits */ -#define P5IV_OFS ( 0) /*!< P5IV Offset */ -#define P5IV_M (0x001f) /*!< Port 5 interrupt vector value */ -#define P5IV0 (0x0001) /*!< Port 5 interrupt vector value */ -#define P5IV1 (0x0002) /*!< Port 5 interrupt vector value */ -#define P5IV2 (0x0004) /*!< Port 5 interrupt vector value */ -#define P5IV3 (0x0008) /*!< Port 5 interrupt vector value */ -#define P5IV4 (0x0010) /*!< Port 5 interrupt vector value */ -#define P5IV_0 (0x0000) /*!< No interrupt pending */ -#define P5IV_2 (0x0002) /*!< Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */ -#define P5IV_4 (0x0004) /*!< Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */ -#define P5IV_6 (0x0006) /*!< Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */ -#define P5IV_8 (0x0008) /*!< Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */ -#define P5IV_10 (0x000a) /*!< Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */ -#define P5IV_12 (0x000c) /*!< Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */ -#define P5IV_14 (0x000e) /*!< Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */ -#define P5IV_16 (0x0010) /*!< Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */ -#define P5IV__NONE (0x0000) /*!< No interrupt pending */ -#define P5IV__P5IFG0 (0x0002) /*!< Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */ -#define P5IV__P5IFG1 (0x0004) /*!< Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */ -#define P5IV__P5IFG2 (0x0006) /*!< Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */ -#define P5IV__P5IFG3 (0x0008) /*!< Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */ -#define P5IV__P5IFG4 (0x000a) /*!< Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */ -#define P5IV__P5IFG5 (0x000c) /*!< Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */ -#define P5IV__P5IFG6 (0x000e) /*!< Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */ -#define P5IV__P5IFG7 (0x0010) /*!< Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */ -/* DIO_PCSELC[P5SELC] Bits */ -#define P5SELC_OFS ( 0) /*!< P5SELC Offset */ -#define P5SELC_M (0x00ff) /*!< Port 5 Complement Select */ -/* DIO_PCSELC[P6SELC] Bits */ -#define P6SELC_OFS ( 8) /*!< P6SELC Offset */ -#define P6SELC_M (0xff00) /*!< Port 6 Complement Select */ -/* DIO_PCIES[P5IES] Bits */ -#define P5IES_OFS ( 0) /*!< P5IES Offset */ -#define P5IES_M (0x00ff) /*!< Port 5 Interrupt Edge Select */ -/* DIO_PCIES[P6IES] Bits */ -#define P6IES_OFS ( 8) /*!< P6IES Offset */ -#define P6IES_M (0xff00) /*!< Port 6 Interrupt Edge Select */ -/* DIO_PCIE[P5IE] Bits */ -#define P5IE_OFS ( 0) /*!< P5IE Offset */ -#define P5IE_M (0x00ff) /*!< Port 5 Interrupt Enable */ -/* DIO_PCIE[P6IE] Bits */ -#define P6IE_OFS ( 8) /*!< P6IE Offset */ -#define P6IE_M (0xff00) /*!< Port 6 Interrupt Enable */ -/* DIO_PCIFG[P5IFG] Bits */ -#define P5IFG_OFS ( 0) /*!< P5IFG Offset */ -#define P5IFG_M (0x00ff) /*!< Port 5 Interrupt Flag */ -/* DIO_PCIFG[P6IFG] Bits */ -#define P6IFG_OFS ( 8) /*!< P6IFG Offset */ -#define P6IFG_M (0xff00) /*!< Port 6 Interrupt Flag */ -/* DIO_P6IV[P6IV] Bits */ -#define P6IV_OFS ( 0) /*!< P6IV Offset */ -#define P6IV_M (0x001f) /*!< Port 6 interrupt vector value */ -#define P6IV0 (0x0001) /*!< Port 6 interrupt vector value */ -#define P6IV1 (0x0002) /*!< Port 6 interrupt vector value */ -#define P6IV2 (0x0004) /*!< Port 6 interrupt vector value */ -#define P6IV3 (0x0008) /*!< Port 6 interrupt vector value */ -#define P6IV4 (0x0010) /*!< Port 6 interrupt vector value */ -#define P6IV_0 (0x0000) /*!< No interrupt pending */ -#define P6IV_2 (0x0002) /*!< Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */ -#define P6IV_4 (0x0004) /*!< Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */ -#define P6IV_6 (0x0006) /*!< Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */ -#define P6IV_8 (0x0008) /*!< Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */ -#define P6IV_10 (0x000a) /*!< Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */ -#define P6IV_12 (0x000c) /*!< Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */ -#define P6IV_14 (0x000e) /*!< Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */ -#define P6IV_16 (0x0010) /*!< Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */ -#define P6IV__NONE (0x0000) /*!< No interrupt pending */ -#define P6IV__P6IFG0 (0x0002) /*!< Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */ -#define P6IV__P6IFG1 (0x0004) /*!< Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */ -#define P6IV__P6IFG2 (0x0006) /*!< Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */ -#define P6IV__P6IFG3 (0x0008) /*!< Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */ -#define P6IV__P6IFG4 (0x000a) /*!< Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */ -#define P6IV__P6IFG5 (0x000c) /*!< Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */ -#define P6IV__P6IFG6 (0x000e) /*!< Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */ -#define P6IV__P6IFG7 (0x0010) /*!< Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */ -/* DIO_PDIN[P7IN] Bits */ -#define P7IN_OFS ( 0) /*!< P7IN Offset */ -#define P7IN_M (0x00ff) /*!< Port 7 Input */ -/* DIO_PDIN[P8IN] Bits */ -#define P8IN_OFS ( 8) /*!< P8IN Offset */ -#define P8IN_M (0xff00) /*!< Port 8 Input */ -/* DIO_PDOUT[P7OUT] Bits */ -#define P7OUT_OFS ( 0) /*!< P7OUT Offset */ -#define P7OUT_M (0x00ff) /*!< Port 7 Output */ -/* DIO_PDOUT[P8OUT] Bits */ -#define P8OUT_OFS ( 8) /*!< P8OUT Offset */ -#define P8OUT_M (0xff00) /*!< Port 8 Output */ -/* DIO_PDDIR[P7DIR] Bits */ -#define P7DIR_OFS ( 0) /*!< P7DIR Offset */ -#define P7DIR_M (0x00ff) /*!< Port 7 Direction */ -/* DIO_PDDIR[P8DIR] Bits */ -#define P8DIR_OFS ( 8) /*!< P8DIR Offset */ -#define P8DIR_M (0xff00) /*!< Port 8 Direction */ -/* DIO_PDREN[P7REN] Bits */ -#define P7REN_OFS ( 0) /*!< P7REN Offset */ -#define P7REN_M (0x00ff) /*!< Port 7 Resistor Enable */ -/* DIO_PDREN[P8REN] Bits */ -#define P8REN_OFS ( 8) /*!< P8REN Offset */ -#define P8REN_M (0xff00) /*!< Port 8 Resistor Enable */ -/* DIO_PDDS[P7DS] Bits */ -#define P7DS_OFS ( 0) /*!< P7DS Offset */ -#define P7DS_M (0x00ff) /*!< Port 7 Drive Strength */ -/* DIO_PDDS[P8DS] Bits */ -#define P8DS_OFS ( 8) /*!< P8DS Offset */ -#define P8DS_M (0xff00) /*!< Port 8 Drive Strength */ -/* DIO_PDSEL0[P7SEL0] Bits */ -#define P7SEL0_OFS ( 0) /*!< P7SEL0 Offset */ -#define P7SEL0_M (0x00ff) /*!< Port 7 Select 0 */ -/* DIO_PDSEL0[P8SEL0] Bits */ -#define P8SEL0_OFS ( 8) /*!< P8SEL0 Offset */ -#define P8SEL0_M (0xff00) /*!< Port 8 Select 0 */ -/* DIO_PDSEL1[P7SEL1] Bits */ -#define P7SEL1_OFS ( 0) /*!< P7SEL1 Offset */ -#define P7SEL1_M (0x00ff) /*!< Port 7 Select 1 */ -/* DIO_PDSEL1[P8SEL1] Bits */ -#define P8SEL1_OFS ( 8) /*!< P8SEL1 Offset */ -#define P8SEL1_M (0xff00) /*!< Port 8 Select 1 */ -/* DIO_P7IV[P7IV] Bits */ -#define P7IV_OFS ( 0) /*!< P7IV Offset */ -#define P7IV_M (0x001f) /*!< Port 7 interrupt vector value */ -#define P7IV0 (0x0001) /*!< Port 7 interrupt vector value */ -#define P7IV1 (0x0002) /*!< Port 7 interrupt vector value */ -#define P7IV2 (0x0004) /*!< Port 7 interrupt vector value */ -#define P7IV3 (0x0008) /*!< Port 7 interrupt vector value */ -#define P7IV4 (0x0010) /*!< Port 7 interrupt vector value */ -#define P7IV_0 (0x0000) /*!< No interrupt pending */ -#define P7IV_2 (0x0002) /*!< Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */ -#define P7IV_4 (0x0004) /*!< Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */ -#define P7IV_6 (0x0006) /*!< Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */ -#define P7IV_8 (0x0008) /*!< Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */ -#define P7IV_10 (0x000a) /*!< Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */ -#define P7IV_12 (0x000c) /*!< Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */ -#define P7IV_14 (0x000e) /*!< Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */ -#define P7IV_16 (0x0010) /*!< Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */ -#define P7IV__NONE (0x0000) /*!< No interrupt pending */ -#define P7IV__P7IFG0 (0x0002) /*!< Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */ -#define P7IV__P7IFG1 (0x0004) /*!< Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */ -#define P7IV__P7IFG2 (0x0006) /*!< Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */ -#define P7IV__P7IFG3 (0x0008) /*!< Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */ -#define P7IV__P7IFG4 (0x000a) /*!< Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */ -#define P7IV__P7IFG5 (0x000c) /*!< Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */ -#define P7IV__P7IFG6 (0x000e) /*!< Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */ -#define P7IV__P7IFG7 (0x0010) /*!< Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */ -/* DIO_PDSELC[P7SELC] Bits */ -#define P7SELC_OFS ( 0) /*!< P7SELC Offset */ -#define P7SELC_M (0x00ff) /*!< Port 7 Complement Select */ -/* DIO_PDSELC[P8SELC] Bits */ -#define P8SELC_OFS ( 8) /*!< P8SELC Offset */ -#define P8SELC_M (0xff00) /*!< Port 8 Complement Select */ -/* DIO_PDIES[P7IES] Bits */ -#define P7IES_OFS ( 0) /*!< P7IES Offset */ -#define P7IES_M (0x00ff) /*!< Port 7 Interrupt Edge Select */ -/* DIO_PDIES[P8IES] Bits */ -#define P8IES_OFS ( 8) /*!< P8IES Offset */ -#define P8IES_M (0xff00) /*!< Port 8 Interrupt Edge Select */ -/* DIO_PDIE[P7IE] Bits */ -#define P7IE_OFS ( 0) /*!< P7IE Offset */ -#define P7IE_M (0x00ff) /*!< Port 7 Interrupt Enable */ -/* DIO_PDIE[P8IE] Bits */ -#define P8IE_OFS ( 8) /*!< P8IE Offset */ -#define P8IE_M (0xff00) /*!< Port 8 Interrupt Enable */ -/* DIO_PDIFG[P7IFG] Bits */ -#define P7IFG_OFS ( 0) /*!< P7IFG Offset */ -#define P7IFG_M (0x00ff) /*!< Port 7 Interrupt Flag */ -/* DIO_PDIFG[P8IFG] Bits */ -#define P8IFG_OFS ( 8) /*!< P8IFG Offset */ -#define P8IFG_M (0xff00) /*!< Port 8 Interrupt Flag */ -/* DIO_P8IV[P8IV] Bits */ -#define P8IV_OFS ( 0) /*!< P8IV Offset */ -#define P8IV_M (0x001f) /*!< Port 8 interrupt vector value */ -#define P8IV0 (0x0001) /*!< Port 8 interrupt vector value */ -#define P8IV1 (0x0002) /*!< Port 8 interrupt vector value */ -#define P8IV2 (0x0004) /*!< Port 8 interrupt vector value */ -#define P8IV3 (0x0008) /*!< Port 8 interrupt vector value */ -#define P8IV4 (0x0010) /*!< Port 8 interrupt vector value */ -#define P8IV_0 (0x0000) /*!< No interrupt pending */ -#define P8IV_2 (0x0002) /*!< Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */ -#define P8IV_4 (0x0004) /*!< Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */ -#define P8IV_6 (0x0006) /*!< Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */ -#define P8IV_8 (0x0008) /*!< Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */ -#define P8IV_10 (0x000a) /*!< Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */ -#define P8IV_12 (0x000c) /*!< Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */ -#define P8IV_14 (0x000e) /*!< Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */ -#define P8IV_16 (0x0010) /*!< Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */ -#define P8IV__NONE (0x0000) /*!< No interrupt pending */ -#define P8IV__P8IFG0 (0x0002) /*!< Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */ -#define P8IV__P8IFG1 (0x0004) /*!< Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */ -#define P8IV__P8IFG2 (0x0006) /*!< Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */ -#define P8IV__P8IFG3 (0x0008) /*!< Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */ -#define P8IV__P8IFG4 (0x000a) /*!< Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */ -#define P8IV__P8IFG5 (0x000c) /*!< Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */ -#define P8IV__P8IFG6 (0x000e) /*!< Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */ -#define P8IV__P8IFG7 (0x0010) /*!< Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */ -/* DIO_PEIN[P9IN] Bits */ -#define P9IN_OFS ( 0) /*!< P9IN Offset */ -#define P9IN_M (0x00ff) /*!< Port 9 Input */ -/* DIO_PEIN[P10IN] Bits */ -#define P10IN_OFS ( 8) /*!< P10IN Offset */ -#define P10IN_M (0xff00) /*!< Port 10 Input */ -/* DIO_PEOUT[P9OUT] Bits */ -#define P9OUT_OFS ( 0) /*!< P9OUT Offset */ -#define P9OUT_M (0x00ff) /*!< Port 9 Output */ -/* DIO_PEOUT[P10OUT] Bits */ -#define P10OUT_OFS ( 8) /*!< P10OUT Offset */ -#define P10OUT_M (0xff00) /*!< Port 10 Output */ -/* DIO_PEDIR[P9DIR] Bits */ -#define P9DIR_OFS ( 0) /*!< P9DIR Offset */ -#define P9DIR_M (0x00ff) /*!< Port 9 Direction */ -/* DIO_PEDIR[P10DIR] Bits */ -#define P10DIR_OFS ( 8) /*!< P10DIR Offset */ -#define P10DIR_M (0xff00) /*!< Port 10 Direction */ -/* DIO_PEREN[P9REN] Bits */ -#define P9REN_OFS ( 0) /*!< P9REN Offset */ -#define P9REN_M (0x00ff) /*!< Port 9 Resistor Enable */ -/* DIO_PEREN[P10REN] Bits */ -#define P10REN_OFS ( 8) /*!< P10REN Offset */ -#define P10REN_M (0xff00) /*!< Port 10 Resistor Enable */ -/* DIO_PEDS[P9DS] Bits */ -#define P9DS_OFS ( 0) /*!< P9DS Offset */ -#define P9DS_M (0x00ff) /*!< Port 9 Drive Strength */ -/* DIO_PEDS[P10DS] Bits */ -#define P10DS_OFS ( 8) /*!< P10DS Offset */ -#define P10DS_M (0xff00) /*!< Port 10 Drive Strength */ -/* DIO_PESEL0[P9SEL0] Bits */ -#define P9SEL0_OFS ( 0) /*!< P9SEL0 Offset */ -#define P9SEL0_M (0x00ff) /*!< Port 9 Select 0 */ -/* DIO_PESEL0[P10SEL0] Bits */ -#define P10SEL0_OFS ( 8) /*!< P10SEL0 Offset */ -#define P10SEL0_M (0xff00) /*!< Port 10 Select 0 */ -/* DIO_PESEL1[P9SEL1] Bits */ -#define P9SEL1_OFS ( 0) /*!< P9SEL1 Offset */ -#define P9SEL1_M (0x00ff) /*!< Port 9 Select 1 */ -/* DIO_PESEL1[P10SEL1] Bits */ -#define P10SEL1_OFS ( 8) /*!< P10SEL1 Offset */ -#define P10SEL1_M (0xff00) /*!< Port 10 Select 1 */ -/* DIO_P9IV[P9IV] Bits */ -#define P9IV_OFS ( 0) /*!< P9IV Offset */ -#define P9IV_M (0x001f) /*!< Port 9 interrupt vector value */ -#define P9IV0 (0x0001) /*!< Port 9 interrupt vector value */ -#define P9IV1 (0x0002) /*!< Port 9 interrupt vector value */ -#define P9IV2 (0x0004) /*!< Port 9 interrupt vector value */ -#define P9IV3 (0x0008) /*!< Port 9 interrupt vector value */ -#define P9IV4 (0x0010) /*!< Port 9 interrupt vector value */ -#define P9IV_0 (0x0000) /*!< No interrupt pending */ -#define P9IV_2 (0x0002) /*!< Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */ -#define P9IV_4 (0x0004) /*!< Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */ -#define P9IV_6 (0x0006) /*!< Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */ -#define P9IV_8 (0x0008) /*!< Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */ -#define P9IV_10 (0x000a) /*!< Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */ -#define P9IV_12 (0x000c) /*!< Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */ -#define P9IV_14 (0x000e) /*!< Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */ -#define P9IV_16 (0x0010) /*!< Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */ -#define P9IV__NONE (0x0000) /*!< No interrupt pending */ -#define P9IV__P9IFG0 (0x0002) /*!< Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */ -#define P9IV__P9IFG1 (0x0004) /*!< Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */ -#define P9IV__P9IFG2 (0x0006) /*!< Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */ -#define P9IV__P9IFG3 (0x0008) /*!< Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */ -#define P9IV__P9IFG4 (0x000a) /*!< Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */ -#define P9IV__P9IFG5 (0x000c) /*!< Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */ -#define P9IV__P9IFG6 (0x000e) /*!< Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */ -#define P9IV__P9IFG7 (0x0010) /*!< Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */ -/* DIO_PESELC[P9SELC] Bits */ -#define P9SELC_OFS ( 0) /*!< P9SELC Offset */ -#define P9SELC_M (0x00ff) /*!< Port 9 Complement Select */ -/* DIO_PESELC[P10SELC] Bits */ -#define P10SELC_OFS ( 8) /*!< P10SELC Offset */ -#define P10SELC_M (0xff00) /*!< Port 10 Complement Select */ -/* DIO_PEIES[P9IES] Bits */ -#define P9IES_OFS ( 0) /*!< P9IES Offset */ -#define P9IES_M (0x00ff) /*!< Port 9 Interrupt Edge Select */ -/* DIO_PEIES[P10IES] Bits */ -#define P10IES_OFS ( 8) /*!< P10IES Offset */ -#define P10IES_M (0xff00) /*!< Port 10 Interrupt Edge Select */ -/* DIO_PEIE[P9IE] Bits */ -#define P9IE_OFS ( 0) /*!< P9IE Offset */ -#define P9IE_M (0x00ff) /*!< Port 9 Interrupt Enable */ -/* DIO_PEIE[P10IE] Bits */ -#define P10IE_OFS ( 8) /*!< P10IE Offset */ -#define P10IE_M (0xff00) /*!< Port 10 Interrupt Enable */ -/* DIO_PEIFG[P9IFG] Bits */ -#define P9IFG_OFS ( 0) /*!< P9IFG Offset */ -#define P9IFG_M (0x00ff) /*!< Port 9 Interrupt Flag */ -/* DIO_PEIFG[P10IFG] Bits */ -#define P10IFG_OFS ( 8) /*!< P10IFG Offset */ -#define P10IFG_M (0xff00) /*!< Port 10 Interrupt Flag */ -/* DIO_P10IV[P10IV] Bits */ -#define P10IV_OFS ( 0) /*!< P10IV Offset */ -#define P10IV_M (0x001f) /*!< Port 10 interrupt vector value */ -#define P10IV0 (0x0001) /*!< Port 10 interrupt vector value */ -#define P10IV1 (0x0002) /*!< Port 10 interrupt vector value */ -#define P10IV2 (0x0004) /*!< Port 10 interrupt vector value */ -#define P10IV3 (0x0008) /*!< Port 10 interrupt vector value */ -#define P10IV4 (0x0010) /*!< Port 10 interrupt vector value */ -#define P10IV_0 (0x0000) /*!< No interrupt pending */ -#define P10IV_2 (0x0002) /*!< Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */ -#define P10IV_4 (0x0004) /*!< Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */ -#define P10IV_6 (0x0006) /*!< Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */ -#define P10IV_8 (0x0008) /*!< Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */ -#define P10IV_10 (0x000a) /*!< Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */ -#define P10IV_12 (0x000c) /*!< Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */ -#define P10IV_14 (0x000e) /*!< Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */ -#define P10IV_16 (0x0010) /*!< Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */ -#define P10IV__NONE (0x0000) /*!< No interrupt pending */ -#define P10IV__P10IFG0 (0x0002) /*!< Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */ -#define P10IV__P10IFG1 (0x0004) /*!< Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */ -#define P10IV__P10IFG2 (0x0006) /*!< Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */ -#define P10IV__P10IFG3 (0x0008) /*!< Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */ -#define P10IV__P10IFG4 (0x000a) /*!< Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */ -#define P10IV__P10IFG5 (0x000c) /*!< Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */ -#define P10IV__P10IFG6 (0x000e) /*!< Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */ -#define P10IV__P10IFG7 (0x0010) /*!< Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */ - - -/****************************************************************************** -* EUSCI_A Bits (legacy section) -******************************************************************************/ -/* UCA0CTLW0[UCSWRST] Bits */ -#define UCSWRST_OFS EUSCI_A_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ -#define UCSWRST EUSCI_A_CTLW0_SWRST /*!< Software reset enable */ -/* UCA0CTLW0[UCTXBRK] Bits */ -#define UCTXBRK_OFS EUSCI_A_CTLW0_TXBRK_OFS /*!< UCTXBRK Offset */ -#define UCTXBRK EUSCI_A_CTLW0_TXBRK /*!< Transmit break */ -/* UCA0CTLW0[UCTXADDR] Bits */ -#define UCTXADDR_OFS EUSCI_A_CTLW0_TXADDR_OFS /*!< UCTXADDR Offset */ -#define UCTXADDR EUSCI_A_CTLW0_TXADDR /*!< Transmit address */ -/* UCA0CTLW0[UCDORM] Bits */ -#define UCDORM_OFS EUSCI_A_CTLW0_DORM_OFS /*!< UCDORM Offset */ -#define UCDORM EUSCI_A_CTLW0_DORM /*!< Dormant */ -/* UCA0CTLW0[UCBRKIE] Bits */ -#define UCBRKIE_OFS EUSCI_A_CTLW0_BRKIE_OFS /*!< UCBRKIE Offset */ -#define UCBRKIE EUSCI_A_CTLW0_BRKIE /*!< Receive break character interrupt enable */ -/* UCA0CTLW0[UCRXEIE] Bits */ -#define UCRXEIE_OFS EUSCI_A_CTLW0_RXEIE_OFS /*!< UCRXEIE Offset */ -#define UCRXEIE EUSCI_A_CTLW0_RXEIE /*!< Receive erroneous-character interrupt enable */ -/* UCA0CTLW0[UCSSEL] Bits */ -#define UCSSEL_OFS EUSCI_A_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ -#define UCSSEL_M EUSCI_A_CTLW0_SSEL_MASK /*!< eUSCI_A clock source select */ -#define UCSSEL0 EUSCI_A_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ -#define UCSSEL1 EUSCI_A_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ -#define UCSSEL_0 EUSCI_A_CTLW0_UCSSEL_0 /*!< UCLK */ -#define UCSSEL_1 EUSCI_A_CTLW0_UCSSEL_1 /*!< ACLK */ -#define UCSSEL_2 EUSCI_A_CTLW0_UCSSEL_2 /*!< SMCLK */ -#define UCSSEL__UCLK EUSCI_A_CTLW0_SSEL__UCLK /*!< UCLK */ -#define UCSSEL__ACLK EUSCI_A_CTLW0_SSEL__ACLK /*!< ACLK */ -#define UCSSEL__SMCLK EUSCI_A_CTLW0_SSEL__SMCLK /*!< SMCLK */ -/* UCA0CTLW0[UCSYNC] Bits */ -#define UCSYNC_OFS EUSCI_A_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ -#define UCSYNC EUSCI_A_CTLW0_SYNC /*!< Synchronous mode enable */ -/* UCA0CTLW0[UCMODE] Bits */ -#define UCMODE_OFS EUSCI_A_CTLW0_MODE_OFS /*!< UCMODE Offset */ -#define UCMODE_M EUSCI_A_CTLW0_MODE_MASK /*!< eUSCI_A mode */ -#define UCMODE0 EUSCI_A_CTLW0_MODE0 /*!< UCMODE Bit 0 */ -#define UCMODE1 EUSCI_A_CTLW0_MODE1 /*!< UCMODE Bit 1 */ -#define UCMODE_0 EUSCI_A_CTLW0_MODE_0 /*!< UART mode */ -#define UCMODE_1 EUSCI_A_CTLW0_MODE_1 /*!< Idle-line multiprocessor mode */ -#define UCMODE_2 EUSCI_A_CTLW0_MODE_2 /*!< Address-bit multiprocessor mode */ -#define UCMODE_3 EUSCI_A_CTLW0_MODE_3 /*!< UART mode with automatic baud-rate detection */ -/* UCA0CTLW0[UCSPB] Bits */ -#define UCSPB_OFS EUSCI_A_CTLW0_SPB_OFS /*!< UCSPB Offset */ -#define UCSPB EUSCI_A_CTLW0_SPB /*!< Stop bit select */ -/* UCA0CTLW0[UC7BIT] Bits */ -#define UC7BIT_OFS EUSCI_A_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */ -#define UC7BIT EUSCI_A_CTLW0_SEVENBIT /*!< Character length */ -/* UCA0CTLW0[UCMSB] Bits */ -#define UCMSB_OFS EUSCI_A_CTLW0_MSB_OFS /*!< UCMSB Offset */ -#define UCMSB EUSCI_A_CTLW0_MSB /*!< MSB first select */ -/* UCA0CTLW0[UCPAR] Bits */ -#define UCPAR_OFS EUSCI_A_CTLW0_PAR_OFS /*!< UCPAR Offset */ -#define UCPAR EUSCI_A_CTLW0_PAR /*!< Parity select */ -/* UCA0CTLW0[UCPEN] Bits */ -#define UCPEN_OFS EUSCI_A_CTLW0_PEN_OFS /*!< UCPEN Offset */ -#define UCPEN EUSCI_A_CTLW0_PEN /*!< Parity enable */ -/* UCA0CTLW0_SPI[UCSWRST] Bits */ -//#define UCSWRST_OFS EUSCI_A_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ -//#define UCSWRST EUSCI_A_CTLW0_SWRST /*!< Software reset enable */ -/* UCA0CTLW0_SPI[UCSTEM] Bits */ -#define UCSTEM_OFS EUSCI_A_CTLW0_STEM_OFS /*!< UCSTEM Offset */ -#define UCSTEM EUSCI_A_CTLW0_STEM /*!< STE mode select in master mode. */ -/* UCA0CTLW0_SPI[UCSSEL] Bits */ -//#define UCSSEL_OFS EUSCI_A_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ -//#define UCSSEL_M EUSCI_A_CTLW0_SSEL_MASK /*!< eUSCI_A clock source select */ -//#define UCSSEL0 EUSCI_A_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ -//#define UCSSEL1 EUSCI_A_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ -//#define UCSSEL_0 EUSCI_A_CTLW0_UCSSEL_0 /*!< Reserved */ -//#define UCSSEL_1 EUSCI_A_CTLW0_UCSSEL_1 /*!< ACLK */ -//#define UCSSEL_2 EUSCI_A_CTLW0_UCSSEL_2 /*!< SMCLK */ -//#define UCSSEL__ACLK EUSCI_A_CTLW0_SSEL__ACLK /*!< ACLK */ -//#define UCSSEL__SMCLK EUSCI_A_CTLW0_SSEL__SMCLK /*!< SMCLK */ -/* UCA0CTLW0_SPI[UCSYNC] Bits */ -//#define UCSYNC_OFS EUSCI_A_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ -//#define UCSYNC EUSCI_A_CTLW0_SYNC /*!< Synchronous mode enable */ -/* UCA0CTLW0_SPI[UCMODE] Bits */ -//#define UCMODE_OFS EUSCI_A_CTLW0_MODE_OFS /*!< UCMODE Offset */ -//#define UCMODE_M EUSCI_A_CTLW0_MODE_MASK /*!< eUSCI mode */ -//#define UCMODE0 EUSCI_A_CTLW0_MODE0 /*!< UCMODE Bit 0 */ -//#define UCMODE1 EUSCI_A_CTLW0_MODE1 /*!< UCMODE Bit 1 */ -//#define UCMODE_0 EUSCI_A_CTLW0_MODE_0 /*!< 3-pin SPI */ -//#define UCMODE_1 EUSCI_A_CTLW0_MODE_1 /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */ -//#define UCMODE_2 EUSCI_A_CTLW0_MODE_2 /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */ -/* UCA0CTLW0_SPI[UCMST] Bits */ -#define UCMST_OFS EUSCI_A_CTLW0_MST_OFS /*!< UCMST Offset */ -#define UCMST EUSCI_A_CTLW0_MST /*!< Master mode select */ -/* UCA0CTLW0_SPI[UC7BIT] Bits */ -//#define UC7BIT_OFS EUSCI_A_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */ -//#define UC7BIT EUSCI_A_CTLW0_SEVENBIT /*!< Character length */ -/* UCA0CTLW0_SPI[UCMSB] Bits */ -//#define UCMSB_OFS EUSCI_A_CTLW0_MSB_OFS /*!< UCMSB Offset */ -//#define UCMSB EUSCI_A_CTLW0_MSB /*!< MSB first select */ -/* UCA0CTLW0_SPI[UCCKPL] Bits */ -#define UCCKPL_OFS EUSCI_A_CTLW0_CKPL_OFS /*!< UCCKPL Offset */ -#define UCCKPL EUSCI_A_CTLW0_CKPL /*!< Clock polarity select */ -/* UCA0CTLW0_SPI[UCCKPH] Bits */ -#define UCCKPH_OFS EUSCI_A_CTLW0_CKPH_OFS /*!< UCCKPH Offset */ -#define UCCKPH EUSCI_A_CTLW0_CKPH /*!< Clock phase select */ -/* UCA0CTLW1[UCGLIT] Bits */ -#define UCGLIT_OFS EUSCI_A_CTLW1_GLIT_OFS /*!< UCGLIT Offset */ -#define UCGLIT_M EUSCI_A_CTLW1_GLIT_MASK /*!< Deglitch time */ -#define UCGLIT0 EUSCI_A_CTLW1_GLIT0 /*!< UCGLIT Bit 0 */ -#define UCGLIT1 EUSCI_A_CTLW1_GLIT1 /*!< UCGLIT Bit 1 */ -#define UCGLIT_0 EUSCI_A_CTLW1_GLIT_0 /*!< Approximately 2 ns (equivalent of 1 delay element) */ -#define UCGLIT_1 EUSCI_A_CTLW1_GLIT_1 /*!< Approximately 50 ns */ -#define UCGLIT_2 EUSCI_A_CTLW1_GLIT_2 /*!< Approximately 100 ns */ -#define UCGLIT_3 EUSCI_A_CTLW1_GLIT_3 /*!< Approximately 200 ns */ -/* UCA0MCTLW[UCOS16] Bits */ -#define UCOS16_OFS EUSCI_A_MCTLW_OS16_OFS /*!< UCOS16 Offset */ -#define UCOS16 EUSCI_A_MCTLW_OS16 /*!< Oversampling mode enabled */ -/* UCA0MCTLW[UCBRF] Bits */ -#define UCBRF_OFS EUSCI_A_MCTLW_BRF_OFS /*!< UCBRF Offset */ -#define UCBRF_M EUSCI_A_MCTLW_BRF_MASK /*!< First modulation stage select */ -/* UCA0MCTLW[UCBRS] Bits */ -#define UCBRS_OFS EUSCI_A_MCTLW_BRS_OFS /*!< UCBRS Offset */ -#define UCBRS_M EUSCI_A_MCTLW_BRS_MASK /*!< Second modulation stage select */ -/* UCA0STATW[UCBUSY] Bits */ -#define UCBUSY_OFS EUSCI_A_STATW_BUSY_OFS /*!< UCBUSY Offset */ -#define UCBUSY EUSCI_A_STATW_BUSY /*!< eUSCI_A busy */ -/* UCA0STATW[UCADDR_UCIDLE] Bits */ -#define UCADDR_UCIDLE_OFS EUSCI_A_STATW_ADDR_IDLE_OFS /*!< UCADDR_UCIDLE Offset */ -#define UCADDR_UCIDLE EUSCI_A_STATW_ADDR_IDLE /*!< Address received / Idle line detected */ -/* UCA0STATW[UCRXERR] Bits */ -#define UCRXERR_OFS EUSCI_A_STATW_RXERR_OFS /*!< UCRXERR Offset */ -#define UCRXERR EUSCI_A_STATW_RXERR /*!< Receive error flag */ -/* UCA0STATW[UCBRK] Bits */ -#define UCBRK_OFS EUSCI_A_STATW_BRK_OFS /*!< UCBRK Offset */ -#define UCBRK EUSCI_A_STATW_BRK /*!< Break detect flag */ -/* UCA0STATW[UCPE] Bits */ -#define UCPE_OFS EUSCI_A_STATW_PE_OFS /*!< UCPE Offset */ -#define UCPE EUSCI_A_STATW_PE -/* UCA0STATW[UCOE] Bits */ -#define UCOE_OFS EUSCI_A_STATW_OE_OFS /*!< UCOE Offset */ -#define UCOE EUSCI_A_STATW_OE /*!< Overrun error flag */ -/* UCA0STATW[UCFE] Bits */ -#define UCFE_OFS EUSCI_A_STATW_FE_OFS /*!< UCFE Offset */ -#define UCFE EUSCI_A_STATW_FE /*!< Framing error flag */ -/* UCA0STATW[UCLISTEN] Bits */ -#define UCLISTEN_OFS EUSCI_A_STATW_LISTEN_OFS /*!< UCLISTEN Offset */ -#define UCLISTEN EUSCI_A_STATW_LISTEN /*!< Listen enable */ -/* UCA0STATW_SPI[UCBUSY] Bits */ -//#define UCBUSY_OFS EUSCI_A_STATW_SPI_BUSY_OFS /*!< UCBUSY Offset */ -//#define UCBUSY EUSCI_A_STATW_SPI_BUSY /*!< eUSCI_A busy */ -/* UCA0STATW_SPI[UCOE] Bits */ -//#define UCOE_OFS EUSCI_A_STATW_OE_OFS /*!< UCOE Offset */ -//#define UCOE EUSCI_A_STATW_OE /*!< Overrun error flag */ -/* UCA0STATW_SPI[UCFE] Bits */ -//#define UCFE_OFS EUSCI_A_STATW_FE_OFS /*!< UCFE Offset */ -//#define UCFE EUSCI_A_STATW_FE /*!< Framing error flag */ -/* UCA0STATW_SPI[UCLISTEN] Bits */ -//#define UCLISTEN_OFS EUSCI_A_STATW_LISTEN_OFS /*!< UCLISTEN Offset */ -//#define UCLISTEN EUSCI_A_STATW_LISTEN /*!< Listen enable */ -/* UCA0RXBUF[UCRXBUF] Bits */ -#define UCRXBUF_OFS EUSCI_A_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ -#define UCRXBUF_M EUSCI_A_RXBUF_RXBUF_MASK /*!< Receive data buffer */ -/* UCA0RXBUF_SPI[UCRXBUF] Bits */ -//#define UCRXBUF_OFS EUSCI_A_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ -//#define UCRXBUF_M EUSCI_A_RXBUF_RXBUF_MASK /*!< Receive data buffer */ -/* UCA0TXBUF[UCTXBUF] Bits */ -#define UCTXBUF_OFS EUSCI_A_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ -#define UCTXBUF_M EUSCI_A_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ -/* UCA0TXBUF_SPI[UCTXBUF] Bits */ -//#define UCTXBUF_OFS EUSCI_A_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ -//#define UCTXBUF_M EUSCI_A_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ -/* UCA0ABCTL[UCABDEN] Bits */ -#define UCABDEN_OFS EUSCI_A_ABCTL_ABDEN_OFS /*!< UCABDEN Offset */ -#define UCABDEN EUSCI_A_ABCTL_ABDEN /*!< Automatic baud-rate detect enable */ -/* UCA0ABCTL[UCBTOE] Bits */ -#define UCBTOE_OFS EUSCI_A_ABCTL_BTOE_OFS /*!< UCBTOE Offset */ -#define UCBTOE EUSCI_A_ABCTL_BTOE /*!< Break time out error */ -/* UCA0ABCTL[UCSTOE] Bits */ -#define UCSTOE_OFS EUSCI_A_ABCTL_STOE_OFS /*!< UCSTOE Offset */ -#define UCSTOE EUSCI_A_ABCTL_STOE /*!< Synch field time out error */ -/* UCA0ABCTL[UCDELIM] Bits */ -#define UCDELIM_OFS EUSCI_A_ABCTL_DELIM_OFS /*!< UCDELIM Offset */ -#define UCDELIM_M EUSCI_A_ABCTL_DELIM_MASK /*!< Break/synch delimiter length */ -#define UCDELIM0 EUSCI_A_ABCTL_DELIM0 /*!< UCDELIM Bit 0 */ -#define UCDELIM1 EUSCI_A_ABCTL_DELIM1 /*!< UCDELIM Bit 1 */ -#define UCDELIM_0 EUSCI_A_ABCTL_DELIM_0 /*!< 1 bit time */ -#define UCDELIM_1 EUSCI_A_ABCTL_DELIM_1 /*!< 2 bit times */ -#define UCDELIM_2 EUSCI_A_ABCTL_DELIM_2 /*!< 3 bit times */ -#define UCDELIM_3 EUSCI_A_ABCTL_DELIM_3 /*!< 4 bit times */ -/* UCA0IRCTL[UCIREN] Bits */ -#define UCIREN_OFS EUSCI_A_IRCTL_IREN_OFS /*!< UCIREN Offset */ -#define UCIREN EUSCI_A_IRCTL_IREN /*!< IrDA encoder/decoder enable */ -/* UCA0IRCTL[UCIRTXCLK] Bits */ -#define UCIRTXCLK_OFS EUSCI_A_IRCTL_IRTXCLK_OFS /*!< UCIRTXCLK Offset */ -#define UCIRTXCLK EUSCI_A_IRCTL_IRTXCLK /*!< IrDA transmit pulse clock select */ -/* UCA0IRCTL[UCIRTXPL] Bits */ -#define UCIRTXPL_OFS EUSCI_A_IRCTL_IRTXPL_OFS /*!< UCIRTXPL Offset */ -#define UCIRTXPL_M EUSCI_A_IRCTL_IRTXPL_MASK /*!< Transmit pulse length */ -/* UCA0IRCTL[UCIRRXFE] Bits */ -#define UCIRRXFE_OFS EUSCI_A_IRCTL_IRRXFE_OFS /*!< UCIRRXFE Offset */ -#define UCIRRXFE EUSCI_A_IRCTL_IRRXFE /*!< IrDA receive filter enabled */ -/* UCA0IRCTL[UCIRRXPL] Bits */ -#define UCIRRXPL_OFS EUSCI_A_IRCTL_IRRXPL_OFS /*!< UCIRRXPL Offset */ -#define UCIRRXPL EUSCI_A_IRCTL_IRRXPL /*!< IrDA receive input UCAxRXD polarity */ -/* UCA0IRCTL[UCIRRXFL] Bits */ -#define UCIRRXFL_OFS EUSCI_A_IRCTL_IRRXFL_OFS /*!< UCIRRXFL Offset */ -#define UCIRRXFL_M EUSCI_A_IRCTL_IRRXFL_MASK /*!< Receive filter length */ -/* UCA0IE[UCRXIE] Bits */ -#define UCRXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Offset */ -#define UCRXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -/* UCA0IE[UCTXIE] Bits */ -#define UCTXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Offset */ -#define UCTXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ -/* UCA0IE[UCSTTIE] Bits */ -#define UCSTTIE_OFS EUSCI_A_IE_STTIE_OFS /*!< UCSTTIE Offset */ -#define UCSTTIE EUSCI_A_IE_STTIE /*!< Start bit interrupt enable */ -/* UCA0IE[UCTXCPTIE] Bits */ -#define UCTXCPTIE_OFS EUSCI_A_IE_TXCPTIE_OFS /*!< UCTXCPTIE Offset */ -#define UCTXCPTIE EUSCI_A_IE_TXCPTIE /*!< Transmit complete interrupt enable */ -/* UCA0IE_SPI[UCRXIE] Bits */ -//#define UCRXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Offset */ -//#define UCRXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -/* UCA0IE_SPI[UCTXIE] Bits */ -//#define UCTXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Offset */ -//#define UCTXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ -/* UCA0IFG[UCRXIFG] Bits */ -#define UCRXIFG_OFS EUSCI_A_IFG_RXIFG_OFS /*!< UCRXIFG Offset */ -#define UCRXIFG EUSCI_A_IFG_RXIFG /*!< Receive interrupt flag */ -/* UCA0IFG[UCTXIFG] Bits */ -#define UCTXIFG_OFS EUSCI_A_IFG_TXIFG_OFS /*!< UCTXIFG Offset */ -#define UCTXIFG EUSCI_A_IFG_TXIFG /*!< Transmit interrupt flag */ -/* UCA0IFG[UCSTTIFG] Bits */ -#define UCSTTIFG_OFS EUSCI_A_IFG_STTIFG_OFS /*!< UCSTTIFG Offset */ -#define UCSTTIFG EUSCI_A_IFG_STTIFG /*!< Start bit interrupt flag */ -/* UCA0IFG[UCTXCPTIFG] Bits */ -#define UCTXCPTIFG_OFS EUSCI_A_IFG_TXCPTIFG_OFS /*!< UCTXCPTIFG Offset */ -#define UCTXCPTIFG EUSCI_A_IFG_TXCPTIFG /*!< Transmit ready interrupt enable */ -/* UCA0IFG_SPI[UCRXIFG] Bits */ -//#define UCRXIFG_OFS EUSCI_A_IFG_RXIFG_OFS /*!< UCRXIFG Offset */ -//#define UCRXIFG EUSCI_A_IFG_RXIFG /*!< Receive interrupt flag */ -/* UCA0IFG_SPI[UCTXIFG] Bits */ -//#define UCTXIFG_OFS EUSCI_A_IFG_TXIFG_OFS /*!< UCTXIFG Offset */ -//#define UCTXIFG EUSCI_A_IFG_TXIFG /*!< Transmit interrupt flag */ - -/****************************************************************************** -* EUSCI_B Bits (legacy section) -******************************************************************************/ -/* UCB0CTLW0[UCSWRST] Bits */ -//#define UCSWRST_OFS EUSCI_B_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ -//#define UCSWRST EUSCI_B_CTLW0_SWRST /*!< Software reset enable */ -/* UCB0CTLW0[UCTXSTT] Bits */ -#define UCTXSTT_OFS EUSCI_B_CTLW0_TXSTT_OFS /*!< UCTXSTT Offset */ -#define UCTXSTT EUSCI_B_CTLW0_TXSTT /*!< Transmit START condition in master mode */ -/* UCB0CTLW0[UCTXSTP] Bits */ -#define UCTXSTP_OFS EUSCI_B_CTLW0_TXSTP_OFS /*!< UCTXSTP Offset */ -#define UCTXSTP EUSCI_B_CTLW0_TXSTP /*!< Transmit STOP condition in master mode */ -/* UCB0CTLW0[UCTXNACK] Bits */ -#define UCTXNACK_OFS EUSCI_B_CTLW0_TXNACK_OFS /*!< UCTXNACK Offset */ -#define UCTXNACK EUSCI_B_CTLW0_TXNACK /*!< Transmit a NACK */ -/* UCB0CTLW0[UCTR] Bits */ -#define UCTR_OFS EUSCI_B_CTLW0_TR_OFS /*!< UCTR Offset */ -#define UCTR EUSCI_B_CTLW0_TR /*!< Transmitter/receiver */ -/* UCB0CTLW0[UCTXACK] Bits */ -#define UCTXACK_OFS EUSCI_B_CTLW0_TXACK_OFS /*!< UCTXACK Offset */ -#define UCTXACK EUSCI_B_CTLW0_TXACK /*!< Transmit ACK condition in slave mode */ -/* UCB0CTLW0[UCSSEL] Bits */ -//#define UCSSEL_OFS EUSCI_B_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ -//#define UCSSEL_M EUSCI_B_CTLW0_SSEL_MASK /*!< eUSCI_B clock source select */ -//#define UCSSEL0 EUSCI_B_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ -//#define UCSSEL1 EUSCI_B_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ -//#define UCSSEL_0 EUSCI_B_CTLW0_UCSSEL_0 /*!< UCLKI */ -//#define UCSSEL_1 EUSCI_B_CTLW0_UCSSEL_1 /*!< ACLK */ -//#define UCSSEL_2 EUSCI_B_CTLW0_UCSSEL_2 /*!< SMCLK */ -#define UCSSEL_3 EUSCI_B_CTLW0_UCSSEL_3 /*!< SMCLK */ -#define UCSSEL__UCLKI EUSCI_B_CTLW0_SSEL__UCLKI /*!< UCLKI */ -//#define UCSSEL__ACLK EUSCI_B_CTLW0_SSEL__ACLK /*!< ACLK */ -//#define UCSSEL__SMCLK EUSCI_B_CTLW0_SSEL__SMCLK /*!< SMCLK */ -/* UCB0CTLW0[UCSYNC] Bits */ -//#define UCSYNC_OFS EUSCI_B_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ -//#define UCSYNC EUSCI_B_CTLW0_SYNC /*!< Synchronous mode enable */ -/* UCB0CTLW0[UCMODE] Bits */ -//#define UCMODE_OFS EUSCI_B_CTLW0_MODE_OFS /*!< UCMODE Offset */ -//#define UCMODE_M EUSCI_B_CTLW0_MODE_MASK /*!< eUSCI_B mode */ -//#define UCMODE0 EUSCI_B_CTLW0_MODE0 /*!< UCMODE Bit 0 */ -//#define UCMODE1 EUSCI_B_CTLW0_MODE1 /*!< UCMODE Bit 1 */ -//#define UCMODE_0 EUSCI_B_CTLW0_MODE_0 /*!< 3-pin SPI */ -//#define UCMODE_1 EUSCI_B_CTLW0_MODE_1 /*!< 4-pin SPI (master or slave enabled if STE = 1) */ -//#define UCMODE_2 EUSCI_B_CTLW0_MODE_2 /*!< 4-pin SPI (master or slave enabled if STE = 0) */ -//#define UCMODE_3 EUSCI_B_CTLW0_MODE_3 /*!< I2C mode */ -/* UCB0CTLW0[UCMST] Bits */ -//#define UCMST_OFS EUSCI_B_CTLW0_MST_OFS /*!< UCMST Offset */ -//#define UCMST EUSCI_B_CTLW0_MST /*!< Master mode select */ -/* UCB0CTLW0[UCMM] Bits */ -#define UCMM_OFS EUSCI_B_CTLW0_MM_OFS /*!< UCMM Offset */ -#define UCMM EUSCI_B_CTLW0_MM /*!< Multi-master environment select */ -/* UCB0CTLW0[UCSLA10] Bits */ -#define UCSLA10_OFS EUSCI_B_CTLW0_SLA10_OFS /*!< UCSLA10 Offset */ -#define UCSLA10 EUSCI_B_CTLW0_SLA10 /*!< Slave addressing mode select */ -/* UCB0CTLW0[UCA10] Bits */ -#define UCA10_OFS EUSCI_B_CTLW0_A10_OFS /*!< UCA10 Offset */ -#define UCA10 EUSCI_B_CTLW0_A10 /*!< Own addressing mode select */ -/* UCB0CTLW0_SPI[UCSWRST] Bits */ -//#define UCSWRST_OFS EUSCI_B_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ -//#define UCSWRST EUSCI_B_CTLW0_SWRST /*!< Software reset enable */ -/* UCB0CTLW0_SPI[UCSTEM] Bits */ -//#define UCSTEM_OFS EUSCI_B_CTLW0_STEM_OFS /*!< UCSTEM Offset */ -//#define UCSTEM EUSCI_B_CTLW0_STEM /*!< STE mode select in master mode. */ -/* UCB0CTLW0_SPI[UCSSEL] Bits */ -//#define UCSSEL_OFS EUSCI_B_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ -//#define UCSSEL_M EUSCI_B_CTLW0_SSEL_MASK /*!< eUSCI_B clock source select */ -//#define UCSSEL0 EUSCI_B_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ -//#define UCSSEL1 EUSCI_B_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ -//#define UCSSEL_0 EUSCI_B_CTLW0_UCSSEL_0 /*!< Reserved */ -//#define UCSSEL_1 EUSCI_B_CTLW0_UCSSEL_1 /*!< ACLK */ -//#define UCSSEL_2 EUSCI_B_CTLW0_UCSSEL_2 /*!< SMCLK */ -//#define UCSSEL_3 EUSCI_B_CTLW0_UCSSEL_3 /*!< SMCLK */ -//#define UCSSEL__ACLK EUSCI_B_CTLW0_SSEL__ACLK /*!< ACLK */ -//#define UCSSEL__SMCLK EUSCI_B_CTLW0_SSEL__SMCLK /*!< SMCLK */ -/* UCB0CTLW0_SPI[UCSYNC] Bits */ -//#define UCSYNC_OFS EUSCI_B_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ -//#define UCSYNC EUSCI_B_CTLW0_SYNC /*!< Synchronous mode enable */ -/* UCB0CTLW0_SPI[UCMODE] Bits */ -//#define UCMODE_OFS EUSCI_B_CTLW0_MODE_OFS /*!< UCMODE Offset */ -//#define UCMODE_M EUSCI_B_CTLW0_MODE_MASK /*!< eUSCI mode */ -//#define UCMODE0 EUSCI_B_CTLW0_MODE0 /*!< UCMODE Bit 0 */ -//#define UCMODE1 EUSCI_B_CTLW0_MODE1 /*!< UCMODE Bit 1 */ -//#define UCMODE_0 EUSCI_B_CTLW0_MODE_0 /*!< 3-pin SPI */ -//#define UCMODE_1 EUSCI_B_CTLW0_MODE_1 /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */ -//#define UCMODE_2 EUSCI_B_CTLW0_MODE_2 /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */ -//#define UCMODE_3 EUSCI_B_CTLW0_MODE_3 /*!< I2C mode */ -/* UCB0CTLW0_SPI[UCMST] Bits */ -//#define UCMST_OFS EUSCI_B_CTLW0_MST_OFS /*!< UCMST Offset */ -//#define UCMST EUSCI_B_CTLW0_MST /*!< Master mode select */ -/* UCB0CTLW0_SPI[UC7BIT] Bits */ -//#define UC7BIT_OFS EUSCI_B_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */ -//#define UC7BIT EUSCI_B_CTLW0_SEVENBIT /*!< Character length */ -/* UCB0CTLW0_SPI[UCMSB] Bits */ -//#define UCMSB_OFS EUSCI_B_CTLW0_MSB_OFS /*!< UCMSB Offset */ -//#define UCMSB EUSCI_B_CTLW0_MSB /*!< MSB first select */ -/* UCB0CTLW0_SPI[UCCKPL] Bits */ -//#define UCCKPL_OFS EUSCI_B_CTLW0_CKPL_OFS /*!< UCCKPL Offset */ -//#define UCCKPL EUSCI_B_CTLW0_CKPL /*!< Clock polarity select */ -/* UCB0CTLW0_SPI[UCCKPH] Bits */ -//#define UCCKPH_OFS EUSCI_B_CTLW0_CKPH_OFS /*!< UCCKPH Offset */ -//#define UCCKPH EUSCI_B_CTLW0_CKPH /*!< Clock phase select */ -/* UCB0CTLW1[UCGLIT] Bits */ -//#define UCGLIT_OFS EUSCI_B_CTLW1_GLIT_OFS /*!< UCGLIT Offset */ -//#define UCGLIT_M EUSCI_B_CTLW1_GLIT_MASK /*!< Deglitch time */ -//#define UCGLIT0 EUSCI_B_CTLW1_GLIT0 /*!< UCGLIT Bit 0 */ -//#define UCGLIT1 EUSCI_B_CTLW1_GLIT1 /*!< UCGLIT Bit 1 */ -//#define UCGLIT_0 EUSCI_B_CTLW1_GLIT_0 /*!< 50 ns */ -//#define UCGLIT_1 EUSCI_B_CTLW1_GLIT_1 /*!< 25 ns */ -//#define UCGLIT_2 EUSCI_B_CTLW1_GLIT_2 /*!< 12.5 ns */ -//#define UCGLIT_3 EUSCI_B_CTLW1_GLIT_3 /*!< 6.25 ns */ -/* UCB0CTLW1[UCASTP] Bits */ -#define UCASTP_OFS EUSCI_B_CTLW1_ASTP_OFS /*!< UCASTP Offset */ -#define UCASTP_M EUSCI_B_CTLW1_ASTP_MASK /*!< Automatic STOP condition generation */ -#define UCASTP0 EUSCI_B_CTLW1_ASTP0 /*!< UCASTP Bit 0 */ -#define UCASTP1 EUSCI_B_CTLW1_ASTP1 /*!< UCASTP Bit 1 */ -#define UCASTP_0 EUSCI_B_CTLW1_ASTP_0 /*!< No automatic STOP generation. The STOP condition is generated after the user */ - /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ -#define UCASTP_1 EUSCI_B_CTLW1_ASTP_1 /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ - /* UCBxTBCNT */ -#define UCASTP_2 EUSCI_B_CTLW1_ASTP_2 /*!< A STOP condition is generated automatically after the byte counter value */ - /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ - /* threshold */ -/* UCB0CTLW1[UCSWACK] Bits */ -#define UCSWACK_OFS EUSCI_B_CTLW1_SWACK_OFS /*!< UCSWACK Offset */ -#define UCSWACK EUSCI_B_CTLW1_SWACK /*!< SW or HW ACK control */ -/* UCB0CTLW1[UCSTPNACK] Bits */ -#define UCSTPNACK_OFS EUSCI_B_CTLW1_STPNACK_OFS /*!< UCSTPNACK Offset */ -#define UCSTPNACK EUSCI_B_CTLW1_STPNACK /*!< ACK all master bytes */ -/* UCB0CTLW1[UCCLTO] Bits */ -#define UCCLTO_OFS EUSCI_B_CTLW1_CLTO_OFS /*!< UCCLTO Offset */ -#define UCCLTO_M EUSCI_B_CTLW1_CLTO_MASK /*!< Clock low timeout select */ -#define UCCLTO0 EUSCI_B_CTLW1_CLTO0 /*!< UCCLTO Bit 0 */ -#define UCCLTO1 EUSCI_B_CTLW1_CLTO1 /*!< UCCLTO Bit 1 */ -#define UCCLTO_0 EUSCI_B_CTLW1_CLTO_0 /*!< Disable clock low timeout counter */ -#define UCCLTO_1 EUSCI_B_CTLW1_CLTO_1 /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ -#define UCCLTO_2 EUSCI_B_CTLW1_CLTO_2 /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ -#define UCCLTO_3 EUSCI_B_CTLW1_CLTO_3 /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ -/* UCB0CTLW1[UCETXINT] Bits */ -#define UCETXINT_OFS EUSCI_B_CTLW1_ETXINT_OFS /*!< UCETXINT Offset */ -#define UCETXINT EUSCI_B_CTLW1_ETXINT /*!< Early UCTXIFG0 */ -/* UCB0STATW[UCBBUSY] Bits */ -#define UCBBUSY_OFS EUSCI_B_STATW_BBUSY_OFS /*!< UCBBUSY Offset */ -#define UCBBUSY EUSCI_B_STATW_BBUSY /*!< Bus busy */ -/* UCB0STATW[UCGC] Bits */ -#define UCGC_OFS EUSCI_B_STATW_GC_OFS /*!< UCGC Offset */ -#define UCGC EUSCI_B_STATW_GC /*!< General call address received */ -/* UCB0STATW[UCSCLLOW] Bits */ -#define UCSCLLOW_OFS EUSCI_B_STATW_SCLLOW_OFS /*!< UCSCLLOW Offset */ -#define UCSCLLOW EUSCI_B_STATW_SCLLOW /*!< SCL low */ -/* UCB0STATW[UCBCNT] Bits */ -#define UCBCNT_OFS EUSCI_B_STATW_BCNT_OFS /*!< UCBCNT Offset */ -#define UCBCNT_M EUSCI_B_STATW_BCNT_MASK /*!< Hardware byte counter value */ -/* UCB0STATW_SPI[UCBUSY] Bits */ -//#define UCBUSY_OFS EUSCI_B_STATW_SPI_BUSY_OFS /*!< UCBUSY Offset */ -//#define UCBUSY EUSCI_B_STATW_SPI_BUSY /*!< eUSCI_B busy */ -/* UCB0STATW_SPI[UCOE] Bits */ -//#define UCOE_OFS EUSCI_B_STATW_OE_OFS /*!< UCOE Offset */ -//#define UCOE EUSCI_B_STATW_OE /*!< Overrun error flag */ -/* UCB0STATW_SPI[UCFE] Bits */ -//#define UCFE_OFS EUSCI_B_STATW_FE_OFS /*!< UCFE Offset */ -//#define UCFE EUSCI_B_STATW_FE /*!< Framing error flag */ -/* UCB0STATW_SPI[UCLISTEN] Bits */ -//#define UCLISTEN_OFS EUSCI_B_STATW_LISTEN_OFS /*!< UCLISTEN Offset */ -//#define UCLISTEN EUSCI_B_STATW_LISTEN /*!< Listen enable */ -/* UCB0TBCNT[UCTBCNT] Bits */ -#define UCTBCNT_OFS EUSCI_B_TBCNT_TBCNT_OFS /*!< UCTBCNT Offset */ -#define UCTBCNT_M EUSCI_B_TBCNT_TBCNT_MASK /*!< Byte counter threshold value */ -/* UCB0RXBUF[UCRXBUF] Bits */ -//#define UCRXBUF_OFS EUSCI_B_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ -//#define UCRXBUF_M EUSCI_B_RXBUF_RXBUF_MASK /*!< Receive data buffer */ -/* UCB0RXBUF_SPI[UCRXBUF] Bits */ -//#define UCRXBUF_OFS EUSCI_B_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ -//#define UCRXBUF_M EUSCI_B_RXBUF_RXBUF_MASK /*!< Receive data buffer */ -/* UCB0TXBUF[UCTXBUF] Bits */ -//#define UCTXBUF_OFS EUSCI_B_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ -//#define UCTXBUF_M EUSCI_B_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ -/* UCB0TXBUF_SPI[UCTXBUF] Bits */ -//#define UCTXBUF_OFS EUSCI_B_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ -//#define UCTXBUF_M EUSCI_B_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ -/* UCB0I2COA0[I2COA0] Bits */ -#define I2COA0_OFS EUSCI_B_I2COA0_I2COA0_OFS /*!< I2COA0 Offset */ -#define I2COA0_M EUSCI_B_I2COA0_I2COA0_MASK /*!< I2C own address */ -/* UCB0I2COA0[UCOAEN] Bits */ -#define UCOAEN_OFS EUSCI_B_I2COA0_OAEN_OFS /*!< UCOAEN Offset */ -#define UCOAEN EUSCI_B_I2COA0_OAEN /*!< Own Address enable register */ -/* UCB0I2COA0[UCGCEN] Bits */ -#define UCGCEN_OFS EUSCI_B_I2COA0_GCEN_OFS /*!< UCGCEN Offset */ -#define UCGCEN EUSCI_B_I2COA0_GCEN /*!< General call response enable */ -/* UCB0I2COA1[I2COA1] Bits */ -#define I2COA1_OFS EUSCI_B_I2COA1_I2COA1_OFS /*!< I2COA1 Offset */ -#define I2COA1_M EUSCI_B_I2COA1_I2COA1_MASK /*!< I2C own address */ -/* UCB0I2COA1[UCOAEN] Bits */ -//#define UCOAEN_OFS EUSCI_B_I2COA1_OAEN_OFS /*!< UCOAEN Offset */ -//#define UCOAEN EUSCI_B_I2COA1_OAEN /*!< Own Address enable register */ -/* UCB0I2COA2[I2COA2] Bits */ -#define I2COA2_OFS EUSCI_B_I2COA2_I2COA2_OFS /*!< I2COA2 Offset */ -#define I2COA2_M EUSCI_B_I2COA2_I2COA2_MASK /*!< I2C own address */ -/* UCB0I2COA2[UCOAEN] Bits */ -//#define UCOAEN_OFS EUSCI_B_I2COA2_OAEN_OFS /*!< UCOAEN Offset */ -//#define UCOAEN EUSCI_B_I2COA2_OAEN /*!< Own Address enable register */ -/* UCB0I2COA3[I2COA3] Bits */ -#define I2COA3_OFS EUSCI_B_I2COA3_I2COA3_OFS /*!< I2COA3 Offset */ -#define I2COA3_M EUSCI_B_I2COA3_I2COA3_MASK /*!< I2C own address */ -/* UCB0I2COA3[UCOAEN] Bits */ -//#define UCOAEN_OFS EUSCI_B_I2COA3_OAEN_OFS /*!< UCOAEN Offset */ -//#define UCOAEN EUSCI_B_I2COA3_OAEN /*!< Own Address enable register */ -/* UCB0ADDRX[ADDRX] Bits */ -#define ADDRX_OFS EUSCI_B_ADDRX_ADDRX_OFS /*!< ADDRX Offset */ -#define ADDRX_M EUSCI_B_ADDRX_ADDRX_MASK /*!< Received Address Register */ -#define ADDRX0 EUSCI_B_ADDRX_ADDRX0 /*!< ADDRX Bit 0 */ -#define ADDRX1 EUSCI_B_ADDRX_ADDRX1 /*!< ADDRX Bit 1 */ -#define ADDRX2 EUSCI_B_ADDRX_ADDRX2 /*!< ADDRX Bit 2 */ -#define ADDRX3 EUSCI_B_ADDRX_ADDRX3 /*!< ADDRX Bit 3 */ -#define ADDRX4 EUSCI_B_ADDRX_ADDRX4 /*!< ADDRX Bit 4 */ -#define ADDRX5 EUSCI_B_ADDRX_ADDRX5 /*!< ADDRX Bit 5 */ -#define ADDRX6 EUSCI_B_ADDRX_ADDRX6 /*!< ADDRX Bit 6 */ -#define ADDRX7 EUSCI_B_ADDRX_ADDRX7 /*!< ADDRX Bit 7 */ -#define ADDRX8 EUSCI_B_ADDRX_ADDRX8 /*!< ADDRX Bit 8 */ -#define ADDRX9 EUSCI_B_ADDRX_ADDRX9 /*!< ADDRX Bit 9 */ -/* UCB0ADDMASK[ADDMASK] Bits */ -#define ADDMASK_OFS EUSCI_B_ADDMASK_ADDMASK_OFS /*!< ADDMASK Offset */ -#define ADDMASK_M EUSCI_B_ADDMASK_ADDMASK_MASK -/* UCB0I2CSA[I2CSA] Bits */ -#define I2CSA_OFS EUSCI_B_I2CSA_I2CSA_OFS /*!< I2CSA Offset */ -#define I2CSA_M EUSCI_B_I2CSA_I2CSA_MASK /*!< I2C slave address */ -/* UCB0IE[UCRXIE0] Bits */ -#define UCRXIE0_OFS EUSCI_B_IE_RXIE0_OFS /*!< UCRXIE0 Offset */ -#define UCRXIE0 EUSCI_B_IE_RXIE0 /*!< Receive interrupt enable 0 */ -/* UCB0IE[UCTXIE0] Bits */ -#define UCTXIE0_OFS EUSCI_B_IE_TXIE0_OFS /*!< UCTXIE0 Offset */ -#define UCTXIE0 EUSCI_B_IE_TXIE0 /*!< Transmit interrupt enable 0 */ -/* UCB0IE[UCSTTIE] Bits */ -//#define UCSTTIE_OFS EUSCI_B_IE_STTIE_OFS /*!< UCSTTIE Offset */ -//#define UCSTTIE EUSCI_B_IE_STTIE /*!< START condition interrupt enable */ -/* UCB0IE[UCSTPIE] Bits */ -#define UCSTPIE_OFS EUSCI_B_IE_STPIE_OFS /*!< UCSTPIE Offset */ -#define UCSTPIE EUSCI_B_IE_STPIE /*!< STOP condition interrupt enable */ -/* UCB0IE[UCALIE] Bits */ -#define UCALIE_OFS EUSCI_B_IE_ALIE_OFS /*!< UCALIE Offset */ -#define UCALIE EUSCI_B_IE_ALIE /*!< Arbitration lost interrupt enable */ -/* UCB0IE[UCNACKIE] Bits */ -#define UCNACKIE_OFS EUSCI_B_IE_NACKIE_OFS /*!< UCNACKIE Offset */ -#define UCNACKIE EUSCI_B_IE_NACKIE /*!< Not-acknowledge interrupt enable */ -/* UCB0IE[UCBCNTIE] Bits */ -#define UCBCNTIE_OFS EUSCI_B_IE_BCNTIE_OFS /*!< UCBCNTIE Offset */ -#define UCBCNTIE EUSCI_B_IE_BCNTIE /*!< Byte counter interrupt enable */ -/* UCB0IE[UCCLTOIE] Bits */ -#define UCCLTOIE_OFS EUSCI_B_IE_CLTOIE_OFS /*!< UCCLTOIE Offset */ -#define UCCLTOIE EUSCI_B_IE_CLTOIE /*!< Clock low timeout interrupt enable */ -/* UCB0IE[UCRXIE1] Bits */ -#define UCRXIE1_OFS EUSCI_B_IE_RXIE1_OFS /*!< UCRXIE1 Offset */ -#define UCRXIE1 EUSCI_B_IE_RXIE1 /*!< Receive interrupt enable 1 */ -/* UCB0IE[UCTXIE1] Bits */ -#define UCTXIE1_OFS EUSCI_B_IE_TXIE1_OFS /*!< UCTXIE1 Offset */ -#define UCTXIE1 EUSCI_B_IE_TXIE1 /*!< Transmit interrupt enable 1 */ -/* UCB0IE[UCRXIE2] Bits */ -#define UCRXIE2_OFS EUSCI_B_IE_RXIE2_OFS /*!< UCRXIE2 Offset */ -#define UCRXIE2 EUSCI_B_IE_RXIE2 /*!< Receive interrupt enable 2 */ -/* UCB0IE[UCTXIE2] Bits */ -#define UCTXIE2_OFS EUSCI_B_IE_TXIE2_OFS /*!< UCTXIE2 Offset */ -#define UCTXIE2 EUSCI_B_IE_TXIE2 /*!< Transmit interrupt enable 2 */ -/* UCB0IE[UCRXIE3] Bits */ -#define UCRXIE3_OFS EUSCI_B_IE_RXIE3_OFS /*!< UCRXIE3 Offset */ -#define UCRXIE3 EUSCI_B_IE_RXIE3 /*!< Receive interrupt enable 3 */ -/* UCB0IE[UCTXIE3] Bits */ -#define UCTXIE3_OFS EUSCI_B_IE_TXIE3_OFS /*!< UCTXIE3 Offset */ -#define UCTXIE3 EUSCI_B_IE_TXIE3 /*!< Transmit interrupt enable 3 */ -/* UCB0IE[UCBIT9IE] Bits */ -#define UCBIT9IE_OFS EUSCI_B_IE_BIT9IE_OFS /*!< UCBIT9IE Offset */ -#define UCBIT9IE EUSCI_B_IE_BIT9IE /*!< Bit position 9 interrupt enable */ -/* UCB0IE_SPI[UCRXIE] Bits */ -//#define UCRXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Offset */ -//#define UCRXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ -/* UCB0IE_SPI[UCTXIE] Bits */ -//#define UCTXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Offset */ -//#define UCTXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ -/* UCB0IFG[UCRXIFG0] Bits */ -#define UCRXIFG0_OFS EUSCI_B_IFG_RXIFG0_OFS /*!< UCRXIFG0 Offset */ -#define UCRXIFG0 EUSCI_B_IFG_RXIFG0 /*!< eUSCI_B receive interrupt flag 0 */ -/* UCB0IFG[UCTXIFG0] Bits */ -#define UCTXIFG0_OFS EUSCI_B_IFG_TXIFG0_OFS /*!< UCTXIFG0 Offset */ -#define UCTXIFG0 EUSCI_B_IFG_TXIFG0 /*!< eUSCI_B transmit interrupt flag 0 */ -/* UCB0IFG[UCSTTIFG] Bits */ -//#define UCSTTIFG_OFS EUSCI_B_IFG_STTIFG_OFS /*!< UCSTTIFG Offset */ -//#define UCSTTIFG EUSCI_B_IFG_STTIFG /*!< START condition interrupt flag */ -/* UCB0IFG[UCSTPIFG] Bits */ -#define UCSTPIFG_OFS EUSCI_B_IFG_STPIFG_OFS /*!< UCSTPIFG Offset */ -#define UCSTPIFG EUSCI_B_IFG_STPIFG /*!< STOP condition interrupt flag */ -/* UCB0IFG[UCALIFG] Bits */ -#define UCALIFG_OFS EUSCI_B_IFG_ALIFG_OFS /*!< UCALIFG Offset */ -#define UCALIFG EUSCI_B_IFG_ALIFG /*!< Arbitration lost interrupt flag */ -/* UCB0IFG[UCNACKIFG] Bits */ -#define UCNACKIFG_OFS EUSCI_B_IFG_NACKIFG_OFS /*!< UCNACKIFG Offset */ -#define UCNACKIFG EUSCI_B_IFG_NACKIFG /*!< Not-acknowledge received interrupt flag */ -/* UCB0IFG[UCBCNTIFG] Bits */ -#define UCBCNTIFG_OFS EUSCI_B_IFG_BCNTIFG_OFS /*!< UCBCNTIFG Offset */ -#define UCBCNTIFG EUSCI_B_IFG_BCNTIFG /*!< Byte counter interrupt flag */ -/* UCB0IFG[UCCLTOIFG] Bits */ -#define UCCLTOIFG_OFS EUSCI_B_IFG_CLTOIFG_OFS /*!< UCCLTOIFG Offset */ -#define UCCLTOIFG EUSCI_B_IFG_CLTOIFG /*!< Clock low timeout interrupt flag */ -/* UCB0IFG[UCRXIFG1] Bits */ -#define UCRXIFG1_OFS EUSCI_B_IFG_RXIFG1_OFS /*!< UCRXIFG1 Offset */ -#define UCRXIFG1 EUSCI_B_IFG_RXIFG1 /*!< eUSCI_B receive interrupt flag 1 */ -/* UCB0IFG[UCTXIFG1] Bits */ -#define UCTXIFG1_OFS EUSCI_B_IFG_TXIFG1_OFS /*!< UCTXIFG1 Offset */ -#define UCTXIFG1 EUSCI_B_IFG_TXIFG1 /*!< eUSCI_B transmit interrupt flag 1 */ -/* UCB0IFG[UCRXIFG2] Bits */ -#define UCRXIFG2_OFS EUSCI_B_IFG_RXIFG2_OFS /*!< UCRXIFG2 Offset */ -#define UCRXIFG2 EUSCI_B_IFG_RXIFG2 /*!< eUSCI_B receive interrupt flag 2 */ -/* UCB0IFG[UCTXIFG2] Bits */ -#define UCTXIFG2_OFS EUSCI_B_IFG_TXIFG2_OFS /*!< UCTXIFG2 Offset */ -#define UCTXIFG2 EUSCI_B_IFG_TXIFG2 /*!< eUSCI_B transmit interrupt flag 2 */ -/* UCB0IFG[UCRXIFG3] Bits */ -#define UCRXIFG3_OFS EUSCI_B_IFG_RXIFG3_OFS /*!< UCRXIFG3 Offset */ -#define UCRXIFG3 EUSCI_B_IFG_RXIFG3 /*!< eUSCI_B receive interrupt flag 3 */ -/* UCB0IFG[UCTXIFG3] Bits */ -#define UCTXIFG3_OFS EUSCI_B_IFG_TXIFG3_OFS /*!< UCTXIFG3 Offset */ -#define UCTXIFG3 EUSCI_B_IFG_TXIFG3 /*!< eUSCI_B transmit interrupt flag 3 */ -/* UCB0IFG[UCBIT9IFG] Bits */ -#define UCBIT9IFG_OFS EUSCI_B_IFG_BIT9IFG_OFS /*!< UCBIT9IFG Offset */ -#define UCBIT9IFG EUSCI_B_IFG_BIT9IFG /*!< Bit position 9 interrupt flag */ -/* UCB0IFG_SPI[UCRXIFG] Bits */ -//#define UCRXIFG_OFS EUSCI_B_IFG_RXIFG_OFS /*!< UCRXIFG Offset */ -//#define UCRXIFG EUSCI_B_IFG_RXIFG /*!< Receive interrupt flag */ -/* UCB0IFG_SPI[UCTXIFG] Bits */ -//#define UCTXIFG_OFS EUSCI_B_IFG_TXIFG_OFS /*!< UCTXIFG Offset */ -//#define UCTXIFG EUSCI_B_IFG_TXIFG /*!< Transmit interrupt flag */ - -/****************************************************************************** -* PMAP Bits (legacy section) -******************************************************************************/ -/* PMAPCTL[PMAPLOCKED] Bits */ -#define PMAPLOCKED_OFS PMAP_CTL_LOCKED_OFS /*!< PMAPLOCKED Offset */ -#define PMAPLOCKED PMAP_CTL_LOCKED /*!< Port mapping lock bit */ -/* PMAPCTL[PMAPRECFG] Bits */ -#define PMAPRECFG_OFS PMAP_CTL_PRECFG_OFS /*!< PMAPRECFG Offset */ -#define PMAPRECFG PMAP_CTL_PRECFG /*!< Port mapping reconfiguration control bit */ -/* Pre-defined bitfield values */ -/* PMAP_PMAPCTL[PMAPLOCKED] Bits */ -#define PMAPLOCKED_OFS PMAP_CTL_LOCKED_OFS /*!< PMAPLOCKED Offset */ -#define PMAPLOCKED PMAP_CTL_LOCKED /*!< Port mapping lock bit */ -/* PMAP_PMAPCTL[PMAPRECFG] Bits */ -#define PMAPRECFG_OFS PMAP_CTL_PRECFG_OFS /*!< PMAPRECFG Offset */ -#define PMAPRECFG PMAP_CTL_PRECFG /*!< Port mapping reconfiguration control bit */ - -#define PM_NONE PMAP_NONE -#define PM_UCA0CLK PMAP_UCA0CLK -#define PM_UCA0RXD PMAP_UCA0RXD -#define PM_UCA0SOMI PMAP_UCA0SOMI -#define PM_UCA0TXD PMAP_UCA0TXD -#define PM_UCA0SIMO PMAP_UCA0SIMO -#define PM_UCB0CLK PMAP_UCB0CLK -#define PM_UCB0SDA PMAP_UCB0SDA -#define PM_UCB0SIMO PMAP_UCB0SIMO -#define PM_UCB0SCL PMAP_UCB0SCL -#define PM_UCB0SOMI PMAP_UCB0SOMI -#define PM_UCA1STE PMAP_UCA1STE -#define PM_UCA1CLK PMAP_UCA1CLK -#define PM_UCA1RXD PMAP_UCA1RXD -#define PM_UCA1SOMI PMAP_UCA1SOMI -#define PM_UCA1TXD PMAP_UCA1TXD -#define PM_UCA1SIMO PMAP_UCA1SIMO -#define PM_UCA2STE PMAP_UCA2STE -#define PM_UCA2CLK PMAP_UCA2CLK -#define PM_UCA2RXD PMAP_UCA2RXD -#define PM_UCA2SOMI PMAP_UCA2SOMI -#define PM_UCA2TXD PMAP_UCA2TXD -#define PM_UCA2SIMO PMAP_UCA2SIMO -#define PM_UCB2STE PMAP_UCB2STE -#define PM_UCB2CLK PMAP_UCB2CLK -#define PM_UCB2SDA PMAP_UCB2SDA -#define PM_UCB2SIMO PMAP_UCB2SIMO -#define PM_UCB2SCL PMAP_UCB2SCL -#define PM_UCB2SOMI PMAP_UCB2SOMI -#define PM_TA0CCR0A PMAP_TA0CCR0A -#define PM_TA0CCR1A PMAP_TA0CCR1A -#define PM_TA0CCR2A PMAP_TA0CCR2A -#define PM_TA0CCR3A PMAP_TA0CCR3A -#define PM_TA0CCR4A PMAP_TA0CCR4A -#define PM_TA1CCR1A PMAP_TA1CCR1A -#define PM_TA1CCR2A PMAP_TA1CCR2A -#define PM_TA1CCR3A PMAP_TA1CCR3A -#define PM_TA1CCR4A PMAP_TA1CCR4A -#define PM_TA0CLK PMAP_TA0CLK -#define PM_CE0OUT PMAP_CE0OUT -#define PM_TA1CLK PMAP_TA1CLK -#define PM_CE1OUT PMAP_CE1OUT -#define PM_DMAE0 PMAP_DMAE0 -#define PM_SMCLK PMAP_SMCLK -#define PM_ANALOG PMAP_ANALOG - -#define PMAPKEY PMAP_KEYID_VAL /*!< Port Mapping Key */ -#define PMAPPWD PMAP_KEYID_VAL /*!< Legacy Definition: Mapping Key register */ -#define PMAPPW PMAP_KEYID_VAL /*!< Legacy Definition: Port Mapping Password */ - - -/****************************************************************************** -* REF_A Bits (legacy section) -******************************************************************************/ -/* REFCTL0[REFON] Bits */ -#define REFON_OFS REF_A_CTL0_ON_OFS /*!< REFON Offset */ -#define REFON REF_A_CTL0_ON /*!< Reference enable */ -/* REFCTL0[REFOUT] Bits */ -#define REFOUT_OFS REF_A_CTL0_OUT_OFS /*!< REFOUT Offset */ -#define REFOUT REF_A_CTL0_OUT /*!< Reference output buffer */ -/* REFCTL0[REFTCOFF] Bits */ -#define REFTCOFF_OFS REF_A_CTL0_TCOFF_OFS /*!< REFTCOFF Offset */ -#define REFTCOFF REF_A_CTL0_TCOFF /*!< Temperature sensor disabled */ -/* REFCTL0[REFVSEL] Bits */ -#define REFVSEL_OFS REF_A_CTL0_VSEL_OFS /*!< REFVSEL Offset */ -#define REFVSEL_M REF_A_CTL0_VSEL_MASK /*!< Reference voltage level select */ -#define REFVSEL0 REF_A_CTL0_VSEL0 /*!< REFVSEL Bit 0 */ -#define REFVSEL1 REF_A_CTL0_VSEL1 /*!< REFVSEL Bit 1 */ -#define REFVSEL_0 REF_A_CTL0_VSEL_0 /*!< 1.2 V available when reference requested or REFON = 1 */ -#define REFVSEL_1 REF_A_CTL0_VSEL_1 /*!< 1.45 V available when reference requested or REFON = 1 */ -#define REFVSEL_3 REF_A_CTL0_VSEL_3 /*!< 2.5 V available when reference requested or REFON = 1 */ -/* REFCTL0[REFGENOT] Bits */ -#define REFGENOT_OFS REF_A_CTL0_GENOT_OFS /*!< REFGENOT Offset */ -#define REFGENOT REF_A_CTL0_GENOT /*!< Reference generator one-time trigger */ -/* REFCTL0[REFBGOT] Bits */ -#define REFBGOT_OFS REF_A_CTL0_BGOT_OFS /*!< REFBGOT Offset */ -#define REFBGOT REF_A_CTL0_BGOT /*!< Bandgap and bandgap buffer one-time trigger */ -/* REFCTL0[REFGENACT] Bits */ -#define REFGENACT_OFS REF_A_CTL0_GENACT_OFS /*!< REFGENACT Offset */ -#define REFGENACT REF_A_CTL0_GENACT /*!< Reference generator active */ -/* REFCTL0[REFBGACT] Bits */ -#define REFBGACT_OFS REF_A_CTL0_BGACT_OFS /*!< REFBGACT Offset */ -#define REFBGACT REF_A_CTL0_BGACT /*!< Reference bandgap active */ -/* REFCTL0[REFGENBUSY] Bits */ -#define REFGENBUSY_OFS REF_A_CTL0_GENBUSY_OFS /*!< REFGENBUSY Offset */ -#define REFGENBUSY REF_A_CTL0_GENBUSY /*!< Reference generator busy */ -/* REFCTL0[BGMODE] Bits */ -#define BGMODE_OFS REF_A_CTL0_BGMODE_OFS /*!< BGMODE Offset */ -#define BGMODE REF_A_CTL0_BGMODE /*!< Bandgap mode */ -/* REFCTL0[REFGENRDY] Bits */ -#define REFGENRDY_OFS REF_A_CTL0_GENRDY_OFS /*!< REFGENRDY Offset */ -#define REFGENRDY REF_A_CTL0_GENRDY /*!< Variable reference voltage ready status */ -/* REFCTL0[REFBGRDY] Bits */ -#define REFBGRDY_OFS REF_A_CTL0_BGRDY_OFS /*!< REFBGRDY Offset */ -#define REFBGRDY REF_A_CTL0_BGRDY /*!< Buffered bandgap voltage ready status */ - -/****************************************************************************** -* RTC_C Bits (legacy section) -******************************************************************************/ -/* RTCCTL0[RTCRDYIFG] Bits */ -#define RTCRDYIFG_OFS RTC_C_CTL0_RDYIFG_OFS /*!< RTCRDYIFG Offset */ -#define RTCRDYIFG RTC_C_CTL0_RDYIFG /*!< Real-time clock ready interrupt flag */ -/* RTCCTL0[RTCAIFG] Bits */ -#define RTCAIFG_OFS RTC_C_CTL0_AIFG_OFS /*!< RTCAIFG Offset */ -#define RTCAIFG RTC_C_CTL0_AIFG /*!< Real-time clock alarm interrupt flag */ -/* RTCCTL0[RTCTEVIFG] Bits */ -#define RTCTEVIFG_OFS RTC_C_CTL0_TEVIFG_OFS /*!< RTCTEVIFG Offset */ -#define RTCTEVIFG RTC_C_CTL0_TEVIFG /*!< Real-time clock time event interrupt flag */ -/* RTCCTL0[RTCOFIFG] Bits */ -#define RTCOFIFG_OFS RTC_C_CTL0_OFIFG_OFS /*!< RTCOFIFG Offset */ -#define RTCOFIFG RTC_C_CTL0_OFIFG /*!< 32-kHz crystal oscillator fault interrupt flag */ -/* RTCCTL0[RTCRDYIE] Bits */ -#define RTCRDYIE_OFS RTC_C_CTL0_RDYIE_OFS /*!< RTCRDYIE Offset */ -#define RTCRDYIE RTC_C_CTL0_RDYIE /*!< Real-time clock ready interrupt enable */ -/* RTCCTL0[RTCAIE] Bits */ -#define RTCAIE_OFS RTC_C_CTL0_AIE_OFS /*!< RTCAIE Offset */ -#define RTCAIE RTC_C_CTL0_AIE /*!< Real-time clock alarm interrupt enable */ -/* RTCCTL0[RTCTEVIE] Bits */ -#define RTCTEVIE_OFS RTC_C_CTL0_TEVIE_OFS /*!< RTCTEVIE Offset */ -#define RTCTEVIE RTC_C_CTL0_TEVIE /*!< Real-time clock time event interrupt enable */ -/* RTCCTL0[RTCOFIE] Bits */ -#define RTCOFIE_OFS RTC_C_CTL0_OFIE_OFS /*!< RTCOFIE Offset */ -#define RTCOFIE RTC_C_CTL0_OFIE /*!< 32-kHz crystal oscillator fault interrupt enable */ -/* RTCCTL0[RTCKEY] Bits */ -#define RTCKEY_OFS RTC_C_CTL0_KEY_OFS /*!< RTCKEY Offset */ -#define RTCKEY_M RTC_C_CTL0_KEY_MASK /*!< Real-time clock key */ -/* RTCCTL13[RTCTEV] Bits */ -#define RTCTEV_OFS RTC_C_CTL13_TEV_OFS /*!< RTCTEV Offset */ -#define RTCTEV_M RTC_C_CTL13_TEV_MASK /*!< Real-time clock time event */ -#define RTCTEV0 RTC_C_CTL13_TEV0 /*!< RTCTEV Bit 0 */ -#define RTCTEV1 RTC_C_CTL13_TEV1 /*!< RTCTEV Bit 1 */ -#define RTCTEV_0 RTC_C_CTL13_TEV_0 /*!< Minute changed */ -#define RTCTEV_1 RTC_C_CTL13_TEV_1 /*!< Hour changed */ -#define RTCTEV_2 RTC_C_CTL13_TEV_2 /*!< Every day at midnight (00:00) */ -#define RTCTEV_3 RTC_C_CTL13_TEV_3 /*!< Every day at noon (12:00) */ -/* RTCCTL13[RTCSSEL] Bits */ -#define RTCSSEL_OFS RTC_C_CTL13_SSEL_OFS /*!< RTCSSEL Offset */ -#define RTCSSEL_M RTC_C_CTL13_SSEL_MASK /*!< Real-time clock source select */ -#define RTCSSEL0 RTC_C_CTL13_SSEL0 /*!< RTCSSEL Bit 0 */ -#define RTCSSEL1 RTC_C_CTL13_SSEL1 /*!< RTCSSEL Bit 1 */ -#define RTCSSEL_0 RTC_C_CTL13_SSEL_0 /*!< BCLK */ -#define RTCSSEL__BCLK RTC_C_CTL13_SSEL__BCLK /*!< BCLK */ -/* RTCCTL13[RTCRDY] Bits */ -#define RTCRDY_OFS RTC_C_CTL13_RDY_OFS /*!< RTCRDY Offset */ -#define RTCRDY RTC_C_CTL13_RDY /*!< Real-time clock ready */ -/* RTCCTL13[RTCMODE] Bits */ -#define RTCMODE_OFS RTC_C_CTL13_MODE_OFS /*!< RTCMODE Offset */ -#define RTCMODE RTC_C_CTL13_MODE -/* RTCCTL13[RTCHOLD] Bits */ -#define RTCHOLD_OFS RTC_C_CTL13_HOLD_OFS /*!< RTCHOLD Offset */ -#define RTCHOLD RTC_C_CTL13_HOLD /*!< Real-time clock hold */ -/* RTCCTL13[RTCBCD] Bits */ -#define RTCBCD_OFS RTC_C_CTL13_BCD_OFS /*!< RTCBCD Offset */ -#define RTCBCD RTC_C_CTL13_BCD /*!< Real-time clock BCD select */ -/* RTCCTL13[RTCCALF] Bits */ -#define RTCCALF_OFS RTC_C_CTL13_CALF_OFS /*!< RTCCALF Offset */ -#define RTCCALF_M RTC_C_CTL13_CALF_MASK /*!< Real-time clock calibration frequency */ -#define RTCCALF0 RTC_C_CTL13_CALF0 /*!< RTCCALF Bit 0 */ -#define RTCCALF1 RTC_C_CTL13_CALF1 /*!< RTCCALF Bit 1 */ -#define RTCCALF_0 RTC_C_CTL13_CALF_0 /*!< No frequency output to RTCCLK pin */ -#define RTCCALF_1 RTC_C_CTL13_CALF_1 /*!< 512 Hz */ -#define RTCCALF_2 RTC_C_CTL13_CALF_2 /*!< 256 Hz */ -#define RTCCALF_3 RTC_C_CTL13_CALF_3 /*!< 1 Hz */ -#define RTCCALF__NONE RTC_C_CTL13_CALF__NONE /*!< No frequency output to RTCCLK pin */ -#define RTCCALF__512 RTC_C_CTL13_CALF__512 /*!< 512 Hz */ -#define RTCCALF__256 RTC_C_CTL13_CALF__256 /*!< 256 Hz */ -#define RTCCALF__1 RTC_C_CTL13_CALF__1 /*!< 1 Hz */ -/* RTCOCAL[RTCOCAL] Bits */ -#define RTCOCAL_OFS RTC_C_OCAL_OCAL_OFS /*!< RTCOCAL Offset */ -#define RTCOCAL_M RTC_C_OCAL_OCAL_MASK /*!< Real-time clock offset error calibration */ -/* RTCOCAL[RTCOCALS] Bits */ -#define RTCOCALS_OFS RTC_C_OCAL_OCALS_OFS /*!< RTCOCALS Offset */ -#define RTCOCALS RTC_C_OCAL_OCALS /*!< Real-time clock offset error calibration sign */ -/* RTCTCMP[RTCTCMP] Bits */ -#define RTCTCMP_OFS RTC_C_TCMP_TCMPX_OFS /*!< RTCTCMP Offset */ -#define RTCTCMP_M RTC_C_TCMP_TCMPX_MASK /*!< Real-time clock temperature compensation */ -/* RTCTCMP[RTCTCOK] Bits */ -#define RTCTCOK_OFS RTC_C_TCMP_TCOK_OFS /*!< RTCTCOK Offset */ -#define RTCTCOK RTC_C_TCMP_TCOK /*!< Real-time clock temperature compensation write OK */ -/* RTCTCMP[RTCTCRDY] Bits */ -#define RTCTCRDY_OFS RTC_C_TCMP_TCRDY_OFS /*!< RTCTCRDY Offset */ -#define RTCTCRDY RTC_C_TCMP_TCRDY /*!< Real-time clock temperature compensation ready */ -/* RTCTCMP[RTCTCMPS] Bits */ -#define RTCTCMPS_OFS RTC_C_TCMP_TCMPS_OFS /*!< RTCTCMPS Offset */ -#define RTCTCMPS RTC_C_TCMP_TCMPS /*!< Real-time clock temperature compensation sign */ -/* RTCPS0CTL[RT0PSIFG] Bits */ -#define RT0PSIFG_OFS RTC_C_PS0CTL_RT0PSIFG_OFS /*!< RT0PSIFG Offset */ -#define RT0PSIFG RTC_C_PS0CTL_RT0PSIFG /*!< Prescale timer 0 interrupt flag */ -/* RTCPS0CTL[RT0PSIE] Bits */ -#define RT0PSIE_OFS RTC_C_PS0CTL_RT0PSIE_OFS /*!< RT0PSIE Offset */ -#define RT0PSIE RTC_C_PS0CTL_RT0PSIE /*!< Prescale timer 0 interrupt enable */ -/* RTCPS0CTL[RT0IP] Bits */ -#define RT0IP_OFS RTC_C_PS0CTL_RT0IP_OFS /*!< RT0IP Offset */ -#define RT0IP_M RTC_C_PS0CTL_RT0IP_MASK /*!< Prescale timer 0 interrupt interval */ -#define RT0IP0 RTC_C_PS0CTL_RT0IP0 /*!< RT0IP Bit 0 */ -#define RT0IP1 RTC_C_PS0CTL_RT0IP1 /*!< RT0IP Bit 1 */ -#define RT0IP2 RTC_C_PS0CTL_RT0IP2 /*!< RT0IP Bit 2 */ -#define RT0IP_0 RTC_C_PS0CTL_RT0IP_0 /*!< Divide by 2 */ -#define RT0IP_1 RTC_C_PS0CTL_RT0IP_1 /*!< Divide by 4 */ -#define RT0IP_2 RTC_C_PS0CTL_RT0IP_2 /*!< Divide by 8 */ -#define RT0IP_3 RTC_C_PS0CTL_RT0IP_3 /*!< Divide by 16 */ -#define RT0IP_4 RTC_C_PS0CTL_RT0IP_4 /*!< Divide by 32 */ -#define RT0IP_5 RTC_C_PS0CTL_RT0IP_5 /*!< Divide by 64 */ -#define RT0IP_6 RTC_C_PS0CTL_RT0IP_6 /*!< Divide by 128 */ -#define RT0IP_7 RTC_C_PS0CTL_RT0IP_7 /*!< Divide by 256 */ -#define RT0IP__2 RTC_C_PS0CTL_RT0IP__2 /*!< Divide by 2 */ -#define RT0IP__4 RTC_C_PS0CTL_RT0IP__4 /*!< Divide by 4 */ -#define RT0IP__8 RTC_C_PS0CTL_RT0IP__8 /*!< Divide by 8 */ -#define RT0IP__16 RTC_C_PS0CTL_RT0IP__16 /*!< Divide by 16 */ -#define RT0IP__32 RTC_C_PS0CTL_RT0IP__32 /*!< Divide by 32 */ -#define RT0IP__64 RTC_C_PS0CTL_RT0IP__64 /*!< Divide by 64 */ -#define RT0IP__128 RTC_C_PS0CTL_RT0IP__128 /*!< Divide by 128 */ -#define RT0IP__256 RTC_C_PS0CTL_RT0IP__256 /*!< Divide by 256 */ -/* RTCPS1CTL[RT1PSIFG] Bits */ -#define RT1PSIFG_OFS RTC_C_PS1CTL_RT1PSIFG_OFS /*!< RT1PSIFG Offset */ -#define RT1PSIFG RTC_C_PS1CTL_RT1PSIFG /*!< Prescale timer 1 interrupt flag */ -/* RTCPS1CTL[RT1PSIE] Bits */ -#define RT1PSIE_OFS RTC_C_PS1CTL_RT1PSIE_OFS /*!< RT1PSIE Offset */ -#define RT1PSIE RTC_C_PS1CTL_RT1PSIE /*!< Prescale timer 1 interrupt enable */ -/* RTCPS1CTL[RT1IP] Bits */ -#define RT1IP_OFS RTC_C_PS1CTL_RT1IP_OFS /*!< RT1IP Offset */ -#define RT1IP_M RTC_C_PS1CTL_RT1IP_MASK /*!< Prescale timer 1 interrupt interval */ -#define RT1IP0 RTC_C_PS1CTL_RT1IP0 /*!< RT1IP Bit 0 */ -#define RT1IP1 RTC_C_PS1CTL_RT1IP1 /*!< RT1IP Bit 1 */ -#define RT1IP2 RTC_C_PS1CTL_RT1IP2 /*!< RT1IP Bit 2 */ -#define RT1IP_0 RTC_C_PS1CTL_RT1IP_0 /*!< Divide by 2 */ -#define RT1IP_1 RTC_C_PS1CTL_RT1IP_1 /*!< Divide by 4 */ -#define RT1IP_2 RTC_C_PS1CTL_RT1IP_2 /*!< Divide by 8 */ -#define RT1IP_3 RTC_C_PS1CTL_RT1IP_3 /*!< Divide by 16 */ -#define RT1IP_4 RTC_C_PS1CTL_RT1IP_4 /*!< Divide by 32 */ -#define RT1IP_5 RTC_C_PS1CTL_RT1IP_5 /*!< Divide by 64 */ -#define RT1IP_6 RTC_C_PS1CTL_RT1IP_6 /*!< Divide by 128 */ -#define RT1IP_7 RTC_C_PS1CTL_RT1IP_7 /*!< Divide by 256 */ -#define RT1IP__2 RTC_C_PS1CTL_RT1IP__2 /*!< Divide by 2 */ -#define RT1IP__4 RTC_C_PS1CTL_RT1IP__4 /*!< Divide by 4 */ -#define RT1IP__8 RTC_C_PS1CTL_RT1IP__8 /*!< Divide by 8 */ -#define RT1IP__16 RTC_C_PS1CTL_RT1IP__16 /*!< Divide by 16 */ -#define RT1IP__32 RTC_C_PS1CTL_RT1IP__32 /*!< Divide by 32 */ -#define RT1IP__64 RTC_C_PS1CTL_RT1IP__64 /*!< Divide by 64 */ -#define RT1IP__128 RTC_C_PS1CTL_RT1IP__128 /*!< Divide by 128 */ -#define RT1IP__256 RTC_C_PS1CTL_RT1IP__256 /*!< Divide by 256 */ -/* RTCPS[RT0PS] Bits */ -#define RT0PS_OFS RTC_C_PS_RT0PS_OFS /*!< RT0PS Offset */ -#define RT0PS_M RTC_C_PS_RT0PS_MASK /*!< Prescale timer 0 counter value */ -/* RTCPS[RT1PS] Bits */ -#define RT1PS_OFS RTC_C_PS_RT1PS_OFS /*!< RT1PS Offset */ -#define RT1PS_M RTC_C_PS_RT1PS_MASK /*!< Prescale timer 1 counter value */ -/* RTCTIM0[SECONDS] Bits */ -#define SECONDS_OFS RTC_C_TIM0_SEC_OFS /*!< Seconds Offset */ -#define SECONDS_M RTC_C_TIM0_SEC_MASK /*!< Seconds (0 to 59) */ -/* RTCTIM0[MINUTES] Bits */ -#define MINUTES_OFS RTC_C_TIM0_MIN_OFS /*!< Minutes Offset */ -#define MINUTES_M RTC_C_TIM0_MIN_MASK /*!< Minutes (0 to 59) */ -/* RTCTIM0_BCD[SECONDSLOWDIGIT] Bits */ -#define SECONDSLOWDIGIT_OFS RTC_C_TIM0_SEC_LD_OFS /*!< SecondsLowDigit Offset */ -#define SECONDSLOWDIGIT_M RTC_C_TIM0_SEC_LD_MASK /*!< Seconds low digit (0 to 9) */ -/* RTCTIM0_BCD[SECONDSHIGHDIGIT] Bits */ -#define SECONDSHIGHDIGIT_OFS RTC_C_TIM0_SEC_HD_OFS /*!< SecondsHighDigit Offset */ -#define SECONDSHIGHDIGIT_M RTC_C_TIM0_SEC_HD_MASK /*!< Seconds high digit (0 to 5) */ -/* RTCTIM0_BCD[MINUTESLOWDIGIT] Bits */ -#define MINUTESLOWDIGIT_OFS RTC_C_TIM0_MIN_LD_OFS /*!< MinutesLowDigit Offset */ -#define MINUTESLOWDIGIT_M RTC_C_TIM0_MIN_LD_MASK /*!< Minutes low digit (0 to 9) */ -/* RTCTIM0_BCD[MINUTESHIGHDIGIT] Bits */ -#define MINUTESHIGHDIGIT_OFS RTC_C_TIM0_MIN_HD_OFS /*!< MinutesHighDigit Offset */ -#define MINUTESHIGHDIGIT_M RTC_C_TIM0_MIN_HD_MASK /*!< Minutes high digit (0 to 5) */ -/* RTCTIM1[HOURS] Bits */ -#define HOURS_OFS RTC_C_TIM1_HOUR_OFS /*!< Hours Offset */ -#define HOURS_M RTC_C_TIM1_HOUR_MASK /*!< Hours (0 to 23) */ -/* RTCTIM1[DAYOFWEEK] Bits */ -#define DAYOFWEEK_OFS RTC_C_TIM1_DOW_OFS /*!< DayofWeek Offset */ -#define DAYOFWEEK_M RTC_C_TIM1_DOW_MASK /*!< Day of week (0 to 6) */ -/* RTCTIM1_BCD[HOURSLOWDIGIT] Bits */ -#define HOURSLOWDIGIT_OFS RTC_C_TIM1_HOUR_LD_OFS /*!< HoursLowDigit Offset */ -#define HOURSLOWDIGIT_M RTC_C_TIM1_HOUR_LD_MASK /*!< Hours low digit (0 to 9) */ -/* RTCTIM1_BCD[HOURSHIGHDIGIT] Bits */ -#define HOURSHIGHDIGIT_OFS RTC_C_TIM1_HOUR_HD_OFS /*!< HoursHighDigit Offset */ -#define HOURSHIGHDIGIT_M RTC_C_TIM1_HOUR_HD_MASK /*!< Hours high digit (0 to 2) */ -/* RTCTIM1_BCD[DAYOFWEEK] Bits */ -//#define DAYOFWEEK_OFS RTC_C_TIM1_DOW_OFS /*!< DayofWeek Offset */ -//#define DAYOFWEEK_M RTC_C_TIM1_DOW_MASK /*!< Day of week (0 to 6) */ -/* RTCDATE[DAY] Bits */ -#define DAY_OFS RTC_C_DATE_DAY_OFS /*!< Day Offset */ -#define DAY_M RTC_C_DATE_DAY_MASK /*!< Day of month (1 to 28, 29, 30, 31) */ -/* RTCDATE[MONTH] Bits */ -#define MONTH_OFS RTC_C_DATE_MON_OFS /*!< Month Offset */ -#define MONTH_M RTC_C_DATE_MON_MASK /*!< Month (1 to 12) */ -/* RTCDATE_BCD[DAYLOWDIGIT] Bits */ -#define DAYLOWDIGIT_OFS RTC_C_DATE_DAY_LD_OFS /*!< DayLowDigit Offset */ -#define DAYLOWDIGIT_M RTC_C_DATE_DAY_LD_MASK /*!< Day of month low digit (0 to 9) */ -/* RTCDATE_BCD[DAYHIGHDIGIT] Bits */ -#define DAYHIGHDIGIT_OFS RTC_C_DATE_DAY_HD_OFS /*!< DayHighDigit Offset */ -#define DAYHIGHDIGIT_M RTC_C_DATE_DAY_HD_MASK /*!< Day of month high digit (0 to 3) */ -/* RTCDATE_BCD[MONTHLOWDIGIT] Bits */ -#define MONTHLOWDIGIT_OFS RTC_C_DATE_MON_LD_OFS /*!< MonthLowDigit Offset */ -#define MONTHLOWDIGIT_M RTC_C_DATE_MON_LD_MASK /*!< Month low digit (0 to 9) */ -/* RTCDATE_BCD[MONTHHIGHDIGIT] Bits */ -#define MONTHHIGHDIGIT_OFS RTC_C_DATE_MON_HD_OFS /*!< MonthHighDigit Offset */ -#define MONTHHIGHDIGIT RTC_C_DATE_MON_HD /*!< Month high digit (0 or 1) */ -/* RTCYEAR[YEARLOWBYTE] Bits */ -#define YEARLOWBYTE_OFS RTC_C_YEAR_YEAR_LB_OFS /*!< YearLowByte Offset */ -#define YEARLOWBYTE_M RTC_C_YEAR_YEAR_LB_MASK /*!< Year low byte. Valid values for Year are 0 to 4095. */ -/* RTCYEAR[YEARHIGHBYTE] Bits */ -#define YEARHIGHBYTE_OFS RTC_C_YEAR_YEAR_HB_OFS /*!< YearHighByte Offset */ -#define YEARHIGHBYTE_M RTC_C_YEAR_YEAR_HB_MASK /*!< Year high byte. Valid values for Year are 0 to 4095. */ -/* RTCYEAR_BCD[YEAR] Bits */ -#define YEAR_OFS RTC_C_YEAR_YEAR_OFS /*!< Year Offset */ -#define YEAR_M RTC_C_YEAR_YEAR_MASK /*!< Year lowest digit (0 to 9) */ -/* RTCYEAR_BCD[DECADE] Bits */ -#define DECADE_OFS RTC_C_YEAR_DEC_OFS /*!< Decade Offset */ -#define DECADE_M RTC_C_YEAR_DEC_MASK /*!< Decade (0 to 9) */ -/* RTCYEAR_BCD[CENTURYLOWDIGIT] Bits */ -#define CENTURYLOWDIGIT_OFS RTC_C_YEAR_CENT_LD_OFS /*!< CenturyLowDigit Offset */ -#define CENTURYLOWDIGIT_M RTC_C_YEAR_CENT_LD_MASK /*!< Century low digit (0 to 9) */ -/* RTCYEAR_BCD[CENTURYHIGHDIGIT] Bits */ -#define CENTURYHIGHDIGIT_OFS RTC_C_YEAR_CENT_HD_OFS /*!< CenturyHighDigit Offset */ -#define CENTURYHIGHDIGIT_M RTC_C_YEAR_CENT_HD_MASK /*!< Century high digit (0 to 4) */ -/* RTCAMINHR[MINUTES] Bits */ -//#define MINUTES_OFS RTC_C_AMINHR_MIN_OFS /*!< Minutes Offset */ -//#define MINUTES_M RTC_C_AMINHR_MIN_MASK /*!< Minutes (0 to 59) */ -/* RTCAMINHR[MINAE] Bits */ -#define MINAE_OFS RTC_C_AMINHR_MINAE_OFS /*!< MINAE Offset */ -#define MINAE RTC_C_AMINHR_MINAE /*!< Alarm enable */ -/* RTCAMINHR[HOURS] Bits */ -//#define HOURS_OFS RTC_C_AMINHR_HOUR_OFS /*!< Hours Offset */ -//#define HOURS_M RTC_C_AMINHR_HOUR_MASK /*!< Hours (0 to 23) */ -/* RTCAMINHR[HOURAE] Bits */ -#define HOURAE_OFS RTC_C_AMINHR_HOURAE_OFS /*!< HOURAE Offset */ -#define HOURAE RTC_C_AMINHR_HOURAE /*!< Alarm enable */ -/* RTCAMINHR_BCD[MINUTESLOWDIGIT] Bits */ -//#define MINUTESLOWDIGIT_OFS RTC_C_AMINHR_MIN_LD_OFS /*!< MinutesLowDigit Offset */ -//#define MINUTESLOWDIGIT_M RTC_C_AMINHR_MIN_LD_MASK /*!< Minutes low digit (0 to 9) */ -/* RTCAMINHR_BCD[MINUTESHIGHDIGIT] Bits */ -//#define MINUTESHIGHDIGIT_OFS RTC_C_AMINHR_MIN_HD_OFS /*!< MinutesHighDigit Offset */ -//#define MINUTESHIGHDIGIT_M RTC_C_AMINHR_MIN_HD_MASK /*!< Minutes high digit (0 to 5) */ -/* RTCAMINHR_BCD[MINAE] Bits */ -//#define MINAE_OFS RTC_C_AMINHR_MINAE_OFS /*!< MINAE Offset */ -//#define MINAE RTC_C_AMINHR_MINAE /*!< Alarm enable */ -/* RTCAMINHR_BCD[HOURSLOWDIGIT] Bits */ -//#define HOURSLOWDIGIT_OFS RTC_C_AMINHR_HOUR_LD_OFS /*!< HoursLowDigit Offset */ -//#define HOURSLOWDIGIT_M RTC_C_AMINHR_HOUR_LD_MASK /*!< Hours low digit (0 to 9) */ -/* RTCAMINHR_BCD[HOURSHIGHDIGIT] Bits */ -//#define HOURSHIGHDIGIT_OFS RTC_C_AMINHR_HOUR_HD_OFS /*!< HoursHighDigit Offset */ -//#define HOURSHIGHDIGIT_M RTC_C_AMINHR_HOUR_HD_MASK /*!< Hours high digit (0 to 2) */ -/* RTCAMINHR_BCD[HOURAE] Bits */ -//#define HOURAE_OFS RTC_C_AMINHR_HOURAE_OFS /*!< HOURAE Offset */ -//#define HOURAE RTC_C_AMINHR_HOURAE /*!< Alarm enable */ -/* RTCADOWDAY[DAYOFWEEK] Bits */ -//#define DAYOFWEEK_OFS RTC_C_ADOWDAY_DOW_OFS /*!< DayofWeek Offset */ -//#define DAYOFWEEK_M RTC_C_ADOWDAY_DOW_MASK /*!< Day of week (0 to 6) */ -/* RTCADOWDAY[DOWAE] Bits */ -#define DOWAE_OFS RTC_C_ADOWDAY_DOWAE_OFS /*!< DOWAE Offset */ -#define DOWAE RTC_C_ADOWDAY_DOWAE /*!< Alarm enable */ -/* RTCADOWDAY[DAYOFMONTH] Bits */ -#define DAYOFMONTH_OFS RTC_C_ADOWDAY_DAY_OFS /*!< DayofMonth Offset */ -#define DAYOFMONTH_M RTC_C_ADOWDAY_DAY_MASK /*!< Day of month (1 to 28, 29, 30, 31) */ -/* RTCADOWDAY[DAYAE] Bits */ -#define DAYAE_OFS RTC_C_ADOWDAY_DAYAE_OFS /*!< DAYAE Offset */ -#define DAYAE RTC_C_ADOWDAY_DAYAE /*!< Alarm enable */ -/* RTCADOWDAY_BCD[DAYOFWEEK] Bits */ -//#define DAYOFWEEK_OFS RTC_C_ADOWDAY_DOW_OFS /*!< DayofWeek Offset */ -//#define DAYOFWEEK_M RTC_C_ADOWDAY_DOW_MASK /*!< Day of week (0 to 6) */ -/* RTCADOWDAY_BCD[DOWAE] Bits */ -//#define DOWAE_OFS RTC_C_ADOWDAY_DOWAE_OFS /*!< DOWAE Offset */ -//#define DOWAE RTC_C_ADOWDAY_DOWAE /*!< Alarm enable */ -/* RTCADOWDAY_BCD[DAYLOWDIGIT] Bits */ -//#define DAYLOWDIGIT_OFS RTC_C_ADOWDAY_DAY_LD_OFS /*!< DayLowDigit Offset */ -//#define DAYLOWDIGIT_M RTC_C_ADOWDAY_DAY_LD_MASK /*!< Day of month low digit (0 to 9) */ -/* RTCADOWDAY_BCD[DAYHIGHDIGIT] Bits */ -//#define DAYHIGHDIGIT_OFS RTC_C_ADOWDAY_DAY_HD_OFS /*!< DayHighDigit Offset */ -//#define DAYHIGHDIGIT_M RTC_C_ADOWDAY_DAY_HD_MASK /*!< Day of month high digit (0 to 3) */ -/* RTCADOWDAY_BCD[DAYAE] Bits */ -//#define DAYAE_OFS RTC_C_ADOWDAY_DAYAE_OFS /*!< DAYAE Offset */ -//#define DAYAE RTC_C_ADOWDAY_DAYAE /*!< Alarm enable */ -/* Pre-defined bitfield values */ -#define RTCKEY RTC_C_KEY /*!< RTC_C Key Value for RTC_C write access */ -#define RTCKEY_H RTC_C_KEY_H /*!< RTC_C Key Value for RTC_C write access */ -#define RTCKEY_VAL RTC_C_KEY_VAL /*!< RTC_C Key Value for RTC_C write access */ - - -/****************************************************************************** -* TIMER_A Bits (legacy section) -******************************************************************************/ -/* TA0CTL[TAIFG] Bits */ -#define TAIFG_OFS TIMER_A_CTL_IFG_OFS /*!< TAIFG Offset */ -#define TAIFG TIMER_A_CTL_IFG /*!< TimerA interrupt flag */ -/* TA0CTL[TAIE] Bits */ -#define TAIE_OFS TIMER_A_CTL_IE_OFS /*!< TAIE Offset */ -#define TAIE TIMER_A_CTL_IE /*!< TimerA interrupt enable */ -/* TA0CTL[TACLR] Bits */ -#define TACLR_OFS TIMER_A_CTL_CLR_OFS /*!< TACLR Offset */ -#define TACLR TIMER_A_CTL_CLR /*!< TimerA clear */ -/* TA0CTL[MC] Bits */ -#define MC_OFS TIMER_A_CTL_MC_OFS /*!< MC Offset */ -#define MC_M TIMER_A_CTL_MC_MASK /*!< Mode control */ -#define MC0 TIMER_A_CTL_MC0 /*!< MC Bit 0 */ -#define MC1 TIMER_A_CTL_MC1 /*!< MC Bit 1 */ -#define MC_0 TIMER_A_CTL_MC_0 /*!< Stop mode: Timer is halted */ -#define MC_1 TIMER_A_CTL_MC_1 /*!< Up mode: Timer counts up to TAxCCR0 */ -#define MC_2 TIMER_A_CTL_MC_2 /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define MC_3 TIMER_A_CTL_MC_3 /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -#define MC__STOP TIMER_A_CTL_MC__STOP /*!< Stop mode: Timer is halted */ -#define MC__UP TIMER_A_CTL_MC__UP /*!< Up mode: Timer counts up to TAxCCR0 */ -#define MC__CONTINUOUS TIMER_A_CTL_MC__CONTINUOUS /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define MC__UPDOWN TIMER_A_CTL_MC__UPDOWN /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -/* TA0CTL[ID] Bits */ -#define ID_OFS TIMER_A_CTL_ID_OFS /*!< ID Offset */ -#define ID_M TIMER_A_CTL_ID_MASK /*!< Input divider */ -#define ID0 TIMER_A_CTL_ID0 /*!< ID Bit 0 */ -#define ID1 TIMER_A_CTL_ID1 /*!< ID Bit 1 */ -#define ID_0 TIMER_A_CTL_ID_0 /*!< /1 */ -#define ID_1 TIMER_A_CTL_ID_1 /*!< /2 */ -#define ID_2 TIMER_A_CTL_ID_2 /*!< /4 */ -#define ID_3 TIMER_A_CTL_ID_3 /*!< /8 */ -#define ID__1 TIMER_A_CTL_ID__1 /*!< /1 */ -#define ID__2 TIMER_A_CTL_ID__2 /*!< /2 */ -#define ID__4 TIMER_A_CTL_ID__4 /*!< /4 */ -#define ID__8 TIMER_A_CTL_ID__8 /*!< /8 */ -/* TA0CTL[TASSEL] Bits */ -#define TASSEL_OFS TIMER_A_CTL_SSEL_OFS /*!< TASSEL Offset */ -#define TASSEL_M TIMER_A_CTL_SSEL_MASK /*!< TimerA clock source select */ -#define TASSEL0 TIMER_A_CTL_SSEL0 /*!< TASSEL Bit 0 */ -#define TASSEL1 TIMER_A_CTL_SSEL1 /*!< TASSEL Bit 1 */ -#define TASSEL_0 TIMER_A_CTL_TASSEL_0 /*!< TAxCLK */ -#define TASSEL_1 TIMER_A_CTL_TASSEL_1 /*!< ACLK */ -#define TASSEL_2 TIMER_A_CTL_TASSEL_2 /*!< SMCLK */ -#define TASSEL_3 TIMER_A_CTL_TASSEL_3 /*!< INCLK */ -#define TASSEL__TACLK TIMER_A_CTL_SSEL__TACLK /*!< TAxCLK */ -#define TASSEL__ACLK TIMER_A_CTL_SSEL__ACLK /*!< ACLK */ -#define TASSEL__SMCLK TIMER_A_CTL_SSEL__SMCLK /*!< SMCLK */ -#define TASSEL__INCLK TIMER_A_CTL_SSEL__INCLK /*!< INCLK */ -/* TA0CCTLn[CCIFG] Bits */ -#define CCIFG_OFS TIMER_A_CCTLN_CCIFG_OFS /*!< CCIFG Offset */ -#define CCIFG TIMER_A_CCTLN_CCIFG /*!< Capture/compare interrupt flag */ -/* TA0CCTLn[COV] Bits */ -#define COV_OFS TIMER_A_CCTLN_COV_OFS /*!< COV Offset */ -#define COV TIMER_A_CCTLN_COV /*!< Capture overflow */ -/* TA0CCTLn[OUT] Bits */ -#define OUT_OFS TIMER_A_CCTLN_OUT_OFS /*!< OUT Offset */ -//#define OUT TIMER_A_CCTLN_OUT /*!< Output */ -/* TA0CCTLn[CCI] Bits */ -#define CCI_OFS TIMER_A_CCTLN_CCI_OFS /*!< CCI Offset */ -#define CCI TIMER_A_CCTLN_CCI /*!< Capture/compare input */ -/* TA0CCTLn[CCIE] Bits */ -#define CCIE_OFS TIMER_A_CCTLN_CCIE_OFS /*!< CCIE Offset */ -#define CCIE TIMER_A_CCTLN_CCIE /*!< Capture/compare interrupt enable */ -/* TA0CCTLn[OUTMOD] Bits */ -#define OUTMOD_OFS TIMER_A_CCTLN_OUTMOD_OFS /*!< OUTMOD Offset */ -#define OUTMOD_M TIMER_A_CCTLN_OUTMOD_MASK /*!< Output mode */ -#define OUTMOD0 TIMER_A_CCTLN_OUTMOD0 /*!< OUTMOD Bit 0 */ -#define OUTMOD1 TIMER_A_CCTLN_OUTMOD1 /*!< OUTMOD Bit 1 */ -#define OUTMOD2 TIMER_A_CCTLN_OUTMOD2 /*!< OUTMOD Bit 2 */ -#define OUTMOD_0 TIMER_A_CCTLN_OUTMOD_0 /*!< OUT bit value */ -#define OUTMOD_1 TIMER_A_CCTLN_OUTMOD_1 /*!< Set */ -#define OUTMOD_2 TIMER_A_CCTLN_OUTMOD_2 /*!< Toggle/reset */ -#define OUTMOD_3 TIMER_A_CCTLN_OUTMOD_3 /*!< Set/reset */ -#define OUTMOD_4 TIMER_A_CCTLN_OUTMOD_4 /*!< Toggle */ -#define OUTMOD_5 TIMER_A_CCTLN_OUTMOD_5 /*!< Reset */ -#define OUTMOD_6 TIMER_A_CCTLN_OUTMOD_6 /*!< Toggle/set */ -#define OUTMOD_7 TIMER_A_CCTLN_OUTMOD_7 /*!< Reset/set */ -/* TA0CCTLn[CAP] Bits */ -#define CAP_OFS TIMER_A_CCTLN_CAP_OFS /*!< CAP Offset */ -#define CAP TIMER_A_CCTLN_CAP /*!< Capture mode */ -/* TA0CCTLn[SCCI] Bits */ -#define SCCI_OFS TIMER_A_CCTLN_SCCI_OFS /*!< SCCI Offset */ -#define SCCI TIMER_A_CCTLN_SCCI /*!< Synchronized capture/compare input */ -/* TA0CCTLn[SCS] Bits */ -#define SCS_OFS TIMER_A_CCTLN_SCS_OFS /*!< SCS Offset */ -#define SCS TIMER_A_CCTLN_SCS /*!< Synchronize capture source */ -/* TA0CCTLn[CCIS] Bits */ -#define CCIS_OFS TIMER_A_CCTLN_CCIS_OFS /*!< CCIS Offset */ -#define CCIS_M TIMER_A_CCTLN_CCIS_MASK /*!< Capture/compare input select */ -#define CCIS0 TIMER_A_CCTLN_CCIS0 /*!< CCIS Bit 0 */ -#define CCIS1 TIMER_A_CCTLN_CCIS1 /*!< CCIS Bit 1 */ -#define CCIS_0 TIMER_A_CCTLN_CCIS_0 /*!< CCIxA */ -#define CCIS_1 TIMER_A_CCTLN_CCIS_1 /*!< CCIxB */ -#define CCIS_2 TIMER_A_CCTLN_CCIS_2 /*!< GND */ -#define CCIS_3 TIMER_A_CCTLN_CCIS_3 /*!< VCC */ -#define CCIS__CCIA TIMER_A_CCTLN_CCIS__CCIA /*!< CCIxA */ -#define CCIS__CCIB TIMER_A_CCTLN_CCIS__CCIB /*!< CCIxB */ -#define CCIS__GND TIMER_A_CCTLN_CCIS__GND /*!< GND */ -#define CCIS__VCC TIMER_A_CCTLN_CCIS__VCC /*!< VCC */ -/* TA0CCTLn[CM] Bits */ -#define CM_OFS TIMER_A_CCTLN_CM_OFS /*!< CM Offset */ -#define CM_M TIMER_A_CCTLN_CM_MASK /*!< Capture mode */ -#define CM0 TIMER_A_CCTLN_CM0 /*!< CM Bit 0 */ -#define CM1 TIMER_A_CCTLN_CM1 /*!< CM Bit 1 */ -#define CM_0 TIMER_A_CCTLN_CM_0 /*!< No capture */ -#define CM_1 TIMER_A_CCTLN_CM_1 /*!< Capture on rising edge */ -#define CM_2 TIMER_A_CCTLN_CM_2 /*!< Capture on falling edge */ -#define CM_3 TIMER_A_CCTLN_CM_3 /*!< Capture on both rising and falling edges */ -#define CM__NONE TIMER_A_CCTLN_CM__NONE /*!< No capture */ -#define CM__RISING TIMER_A_CCTLN_CM__RISING /*!< Capture on rising edge */ -#define CM__FALLING TIMER_A_CCTLN_CM__FALLING /*!< Capture on falling edge */ -#define CM__BOTH TIMER_A_CCTLN_CM__BOTH /*!< Capture on both rising and falling edges */ -/* TA0EX0[TAIDEX] Bits */ -#define TAIDEX_OFS TIMER_A_EX0_IDEX_OFS /*!< TAIDEX Offset */ -#define TAIDEX_M TIMER_A_EX0_IDEX_MASK /*!< Input divider expansion */ -#define TAIDEX0 TIMER_A_EX0_IDEX0 /*!< TAIDEX Bit 0 */ -#define TAIDEX1 TIMER_A_EX0_IDEX1 /*!< TAIDEX Bit 1 */ -#define TAIDEX2 TIMER_A_EX0_IDEX2 /*!< TAIDEX Bit 2 */ -#define TAIDEX_0 TIMER_A_EX0_TAIDEX_0 /*!< Divide by 1 */ -#define TAIDEX_1 TIMER_A_EX0_TAIDEX_1 /*!< Divide by 2 */ -#define TAIDEX_2 TIMER_A_EX0_TAIDEX_2 /*!< Divide by 3 */ -#define TAIDEX_3 TIMER_A_EX0_TAIDEX_3 /*!< Divide by 4 */ -#define TAIDEX_4 TIMER_A_EX0_TAIDEX_4 /*!< Divide by 5 */ -#define TAIDEX_5 TIMER_A_EX0_TAIDEX_5 /*!< Divide by 6 */ -#define TAIDEX_6 TIMER_A_EX0_TAIDEX_6 /*!< Divide by 7 */ -#define TAIDEX_7 TIMER_A_EX0_TAIDEX_7 /*!< Divide by 8 */ -#define TAIDEX__1 TIMER_A_EX0_IDEX__1 /*!< Divide by 1 */ -#define TAIDEX__2 TIMER_A_EX0_IDEX__2 /*!< Divide by 2 */ -#define TAIDEX__3 TIMER_A_EX0_IDEX__3 /*!< Divide by 3 */ -#define TAIDEX__4 TIMER_A_EX0_IDEX__4 /*!< Divide by 4 */ -#define TAIDEX__5 TIMER_A_EX0_IDEX__5 /*!< Divide by 5 */ -#define TAIDEX__6 TIMER_A_EX0_IDEX__6 /*!< Divide by 6 */ -#define TAIDEX__7 TIMER_A_EX0_IDEX__7 /*!< Divide by 7 */ -#define TAIDEX__8 TIMER_A_EX0_IDEX__8 /*!< Divide by 8 */ - -/****************************************************************************** -* WDT_A Bits (legacy section) -******************************************************************************/ -/* WDTCTL[WDTIS] Bits */ -#define WDTIS_OFS WDT_A_CTL_IS_OFS /*!< WDTIS Offset */ -#define WDTIS_M WDT_A_CTL_IS_MASK /*!< Watchdog timer interval select */ -#define WDTIS0 WDT_A_CTL_IS0 /*!< WDTIS Bit 0 */ -#define WDTIS1 WDT_A_CTL_IS1 /*!< WDTIS Bit 1 */ -#define WDTIS2 WDT_A_CTL_IS2 /*!< WDTIS Bit 2 */ -#define WDTIS_0 WDT_A_CTL_IS_0 /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ -#define WDTIS_1 WDT_A_CTL_IS_1 /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ -#define WDTIS_2 WDT_A_CTL_IS_2 /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ -#define WDTIS_3 WDT_A_CTL_IS_3 /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ -#define WDTIS_4 WDT_A_CTL_IS_4 /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ -#define WDTIS_5 WDT_A_CTL_IS_5 /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ -#define WDTIS_6 WDT_A_CTL_IS_6 /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ -#define WDTIS_7 WDT_A_CTL_IS_7 /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ -/* WDTCTL[WDTCNTCL] Bits */ -#define WDTCNTCL_OFS WDT_A_CTL_CNTCL_OFS /*!< WDTCNTCL Offset */ -#define WDTCNTCL WDT_A_CTL_CNTCL /*!< Watchdog timer counter clear */ -/* WDTCTL[WDTTMSEL] Bits */ -#define WDTTMSEL_OFS WDT_A_CTL_TMSEL_OFS /*!< WDTTMSEL Offset */ -#define WDTTMSEL WDT_A_CTL_TMSEL /*!< Watchdog timer mode select */ -/* WDTCTL[WDTSSEL] Bits */ -#define WDTSSEL_OFS WDT_A_CTL_SSEL_OFS /*!< WDTSSEL Offset */ -#define WDTSSEL_M WDT_A_CTL_SSEL_MASK /*!< Watchdog timer clock source select */ -#define WDTSSEL0 WDT_A_CTL_SSEL0 /*!< WDTSSEL Bit 0 */ -#define WDTSSEL1 WDT_A_CTL_SSEL1 /*!< WDTSSEL Bit 1 */ -#define WDTSSEL_0 WDT_A_CTL_SSEL_0 /*!< SMCLK */ -#define WDTSSEL_1 WDT_A_CTL_SSEL_1 /*!< ACLK */ -#define WDTSSEL_2 WDT_A_CTL_SSEL_2 /*!< VLOCLK */ -#define WDTSSEL_3 WDT_A_CTL_SSEL_3 /*!< BCLK */ -#define WDTSSEL__SMCLK WDT_A_CTL_SSEL__SMCLK /*!< SMCLK */ -#define WDTSSEL__ACLK WDT_A_CTL_SSEL__ACLK /*!< ACLK */ -#define WDTSSEL__VLOCLK WDT_A_CTL_SSEL__VLOCLK /*!< VLOCLK */ -#define WDTSSEL__BCLK WDT_A_CTL_SSEL__BCLK /*!< BCLK */ -/* WDTCTL[WDTHOLD] Bits */ -#define WDTHOLD_OFS WDT_A_CTL_HOLD_OFS /*!< WDTHOLD Offset */ -#define WDTHOLD WDT_A_CTL_HOLD /*!< Watchdog timer hold */ -/* WDTCTL[WDTPW] Bits */ -#define WDTPW_OFS WDT_A_CTL_PW_OFS /*!< WDTPW Offset */ -#define WDTPW_M WDT_A_CTL_PW_MASK /*!< Watchdog timer password */ -/* Pre-defined bitfield values */ -#define WDTPW WDT_A_CTL_PW /*!< WDT Key Value for WDT write access */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __MSP432P401M_CLASSIC_H__ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p401r.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p401r.h deleted file mode 100644 index afd11e46e07..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p401r.h +++ /dev/null @@ -1,6941 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432P401R Register Definitions -* -* This file includes CMSIS compliant component and register definitions -* -* For legacy components the definitions that are compatible with MSP430 code, -* are included with msp432p401r_classic.h -* -* With CMSIS definitions, the register defines have been reformatted: -* ModuleName[ModuleInstance]->RegisterName -* -* Writing to CMSIS bit fields can be done through register level -* or via bitband area access: -* - ADC14->CTL0 |= ADC14_CTL0_ENC; -* - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1; -* -* File creation date: 2017-08-03 -* -******************************************************************************/ - -#ifndef __MSP432P401R_H__ -#define __MSP432P401R_H__ - -/* Use standard integer types with explicit width */ -#include - -#ifdef __cplusplus - extern "C" { -#endif - -#define __MSP432_HEADER_VERSION__ 3202 - -/* Remap MSP432 intrinsics to ARM equivalents */ -#include "msp_compatibility.h" - -/****************************************************************************** -* include MSP430 legacy definitions to make porting of code from MSP430 * -* code base easier * -* With fully CMSIS compliant code, NO_MSP_CLASSIC_DEFINES may be defined in * -* your project to omit including the classic defines * -******************************************************************************/ -#ifndef NO_MSP_CLASSIC_DEFINES -#include "msp432p401r_classic.h" -#endif - - -#ifndef __CMSIS_CONFIG__ -#define __CMSIS_CONFIG__ - -/** @addtogroup MSP432P401R_Definitions MSP432P401R Definitions - This file defines all structures and symbols for MSP432P401R: - - components and registers - - peripheral base address - - peripheral ID - - Peripheral definitions - @{ -*/ - -/****************************************************************************** -* Processor and Core Peripherals * -******************************************************************************/ -/** @addtogroup MSP432P401R_CMSIS Device CMSIS Definitions - Configuration of the Cortex-M4 Processor and Core Peripherals - @{ -*/ - -/****************************************************************************** -* CMSIS-compatible Interrupt Number Definition * -******************************************************************************/ -typedef enum IRQn -{ - /* Cortex-M4 Processor Exceptions Numbers */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - /* Peripheral Exceptions Numbers */ - PSS_IRQn = 0, /* 16 PSS Interrupt */ - CS_IRQn = 1, /* 17 CS Interrupt */ - PCM_IRQn = 2, /* 18 PCM Interrupt */ - WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */ - FPU_IRQn = 4, /* 20 FPU Interrupt */ - FLCTL_IRQn = 5, /* 21 Flash Controller Interrupt*/ - COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */ - COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */ - TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */ - TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */ - TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */ - TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */ - TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */ - TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */ - TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */ - TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */ - EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */ - EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */ - EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */ - EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */ - EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */ - EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */ - EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */ - EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */ - ADC14_IRQn = 24, /* 40 ADC14 Interrupt */ - T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */ - T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */ - T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */ - AES256_IRQn = 28, /* 44 AES256 Interrupt */ - RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */ - DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */ - DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */ - DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */ - DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */ - DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */ - PORT1_IRQn = 35, /* 51 Port1 Interrupt */ - PORT2_IRQn = 36, /* 52 Port2 Interrupt */ - PORT3_IRQn = 37, /* 53 Port3 Interrupt */ - PORT4_IRQn = 38, /* 54 Port4 Interrupt */ - PORT5_IRQn = 39, /* 55 Port5 Interrupt */ - PORT6_IRQn = 40 /* 56 Port6 Interrupt */ -} IRQn_Type; - -/****************************************************************************** -* Processor and Core Peripheral Section * -******************************************************************************/ -#define __CM4_REV 0x0001 /* Core revision r0p1 */ -#define __MPU_PRESENT 1 /* MPU present or not */ -#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /* FPU present or not */ - -/****************************************************************************** -* Available Peripherals * -******************************************************************************/ -#define __MCU_HAS_ADC14__ /*!< Module ADC14 is available */ -#define __MCU_HAS_AES256__ /*!< Module AES256 is available */ -#define __MCU_HAS_CAPTIO0__ /*!< Module CAPTIO0 is available */ -#define __MCU_HAS_CAPTIO1__ /*!< Module CAPTIO1 is available */ -#define __MCU_HAS_COMP_E0__ /*!< Module COMP_E0 is available */ -#define __MCU_HAS_COMP_E1__ /*!< Module COMP_E1 is available */ -#define __MCU_HAS_CRC32__ /*!< Module CRC32 is available */ -#define __MCU_HAS_CS__ /*!< Module CS is available */ -#define __MCU_HAS_DIO__ /*!< Module DIO is available */ -#define __MCU_HAS_DMA__ /*!< Module DMA is available */ -#define __MCU_HAS_EUSCI_A0__ /*!< Module EUSCI_A0 is available */ -#define __MCU_HAS_EUSCI_A1__ /*!< Module EUSCI_A1 is available */ -#define __MCU_HAS_EUSCI_A2__ /*!< Module EUSCI_A2 is available */ -#define __MCU_HAS_EUSCI_A3__ /*!< Module EUSCI_A3 is available */ -#define __MCU_HAS_EUSCI_B0__ /*!< Module EUSCI_B0 is available */ -#define __MCU_HAS_EUSCI_B1__ /*!< Module EUSCI_B1 is available */ -#define __MCU_HAS_EUSCI_B2__ /*!< Module EUSCI_B2 is available */ -#define __MCU_HAS_EUSCI_B3__ /*!< Module EUSCI_B3 is available */ -#define __MCU_HAS_FLCTL__ /*!< Module FLCTL is available */ -#define __MCU_HAS_FL_BOOTOVER_MAILBOX__ /*!< Module FL_BOOTOVER_MAILBOX is available */ -#define __MCU_HAS_PCM__ /*!< Module PCM is available */ -#define __MCU_HAS_PMAP__ /*!< Module PMAP is available */ -#define __MCU_HAS_PSS__ /*!< Module PSS is available */ -#define __MCU_HAS_REF_A__ /*!< Module REF_A is available */ -#define __MCU_HAS_RSTCTL__ /*!< Module RSTCTL is available */ -#define __MCU_HAS_RTC_C__ /*!< Module RTC_C is available */ -#define __MCU_HAS_SYSCTL__ /*!< Module SYSCTL is available */ -#define __MCU_HAS_TIMER32__ /*!< Module TIMER32 is available */ -#define __MCU_HAS_TIMER_A0__ /*!< Module TIMER_A0 is available */ -#define __MCU_HAS_TIMER_A1__ /*!< Module TIMER_A1 is available */ -#define __MCU_HAS_TIMER_A2__ /*!< Module TIMER_A2 is available */ -#define __MCU_HAS_TIMER_A3__ /*!< Module TIMER_A3 is available */ -#define __MCU_HAS_TLV__ /*!< Module TLV is available */ -#define __MCU_HAS_WDT_A__ /*!< Module WDT_A is available */ - -/* Definitions to show that specific ports are available */ - -#define __MSP432_HAS_PORTA_R__ -#define __MSP432_HAS_PORTB_R__ -#define __MSP432_HAS_PORTC_R__ -#define __MSP432_HAS_PORTD_R__ -#define __MSP432_HAS_PORTE_R__ -#define __MSP432_HAS_PORTJ_R__ - -#define __MSP432_HAS_PORT1_R__ -#define __MSP432_HAS_PORT2_R__ -#define __MSP432_HAS_PORT3_R__ -#define __MSP432_HAS_PORT4_R__ -#define __MSP432_HAS_PORT5_R__ -#define __MSP432_HAS_PORT6_R__ -#define __MSP432_HAS_PORT7_R__ -#define __MSP432_HAS_PORT8_R__ -#define __MSP432_HAS_PORT9_R__ -#define __MSP432_HAS_PORT10_R__ - - -/*@}*/ /* end of group MSP432P401R_CMSIS */ - -/* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */ -#ifdef __TI_ARM__ -/* disable the TI ULP advisor check for the core header file definitions */ -#pragma diag_push -#pragma CHECK_ULP("none") -#include "core_cm4.h" -#pragma diag_pop -#else -#include "core_cm4.h" -#endif - -/* System Header */ -#include "system_msp432p401r.h" - -/****************************************************************************** -* Definition of standard bits * -******************************************************************************/ -#define BIT0 (uint16_t)(0x0001) -#define BIT1 (uint16_t)(0x0002) -#define BIT2 (uint16_t)(0x0004) -#define BIT3 (uint16_t)(0x0008) -#define BIT4 (uint16_t)(0x0010) -#define BIT5 (uint16_t)(0x0020) -#define BIT6 (uint16_t)(0x0040) -#define BIT7 (uint16_t)(0x0080) -#define BIT8 (uint16_t)(0x0100) -#define BIT9 (uint16_t)(0x0200) -#define BITA (uint16_t)(0x0400) -#define BITB (uint16_t)(0x0800) -#define BITC (uint16_t)(0x1000) -#define BITD (uint16_t)(0x2000) -#define BITE (uint16_t)(0x4000) -#define BITF (uint16_t)(0x8000) - -/****************************************************************************** -* Device and peripheral memory map * -******************************************************************************/ -/** @addtogroup MSP432P401R_MemoryMap MSP432P401R Memory Mapping - @{ -*/ - -#define FLASH_BASE ((uint32_t)0x00000000) /*!< Main Flash memory start address */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM memory start address */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripherals start address */ -#define PERIPH_BASE2 ((uint32_t)0xE0000000) /*!< Peripherals start address */ - -#define ADC14_BASE (PERIPH_BASE +0x00012000) /*!< Base address of module ADC14 registers */ -#define AES256_BASE (PERIPH_BASE +0x00003C00) /*!< Base address of module AES256 registers */ -#define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /*!< Base address of module CAPTIO0 registers */ -#define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /*!< Base address of module CAPTIO1 registers */ -#define COMP_E0_BASE (PERIPH_BASE +0x00003400) /*!< Base address of module COMP_E0 registers */ -#define COMP_E1_BASE (PERIPH_BASE +0x00003800) /*!< Base address of module COMP_E1 registers */ -#define CRC32_BASE (PERIPH_BASE +0x00004000) /*!< Base address of module CRC32 registers */ -#define CS_BASE (PERIPH_BASE +0x00010400) /*!< Base address of module CS registers */ -#define DIO_BASE (PERIPH_BASE +0x00004C00) /*!< Base address of module DIO registers */ -#define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address of module DMA registers */ -#define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define FLCTL_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL registers */ -#define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000) /*!< Base address of module FL_BOOTOVER_MAILBOX registers */ -#define PCM_BASE (PERIPH_BASE +0x00010000) /*!< Base address of module PCM registers */ -#define PMAP_BASE (PERIPH_BASE +0x00005000) /*!< Base address of module PMAP registers */ -#define PSS_BASE (PERIPH_BASE +0x00010800) /*!< Base address of module PSS registers */ -#define REF_A_BASE (PERIPH_BASE +0x00003000) /*!< Base address of module REF_A registers */ -#define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /*!< Base address of module RSTCTL registers */ -#define RTC_C_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define SYSCTL_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL registers */ -#define TIMER32_BASE (PERIPH_BASE +0x0000C000) /*!< Base address of module TIMER32 registers */ -#define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /*!< Base address of module TIMER_A0 registers */ -#define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /*!< Base address of module TIMER_A1 registers */ -#define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /*!< Base address of module TIMER_A2 registers */ -#define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /*!< Base address of module TIMER_A3 registers */ -#define TLV_BASE ((uint32_t)0x00201000) /*!< Base address of module TLV registers */ -#define WDT_A_BASE (PERIPH_BASE +0x00004800) /*!< Base address of module WDT_A registers */ - - -/*@}*/ /* end of group MSP432P401R_MemoryMap */ - -/****************************************************************************** -* Definitions for bit band access * -******************************************************************************/ -#define BITBAND_SRAM_BASE ((uint32_t)(0x22000000)) -#define BITBAND_PERI_BASE ((uint32_t)(0x42000000)) - -/* SRAM allows 32 bit bit band access */ -#define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4))) -/* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */ -#define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4))) - -/****************************************************************************** -* Peripheral register definitions * -******************************************************************************/ -/** @addtogroup MSP432P401R_Peripherals MSP432P401R Peripherals - MSP432P401R Device Specific Peripheral registers structures - @{ -*/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - -/****************************************************************************** -* ADC14 Registers -******************************************************************************/ -/** @addtogroup ADC14 MSP432P401R (ADC14) - @{ -*/ -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t LO0; /*!< Window Comparator Low Threshold 0 Register */ - __IO uint32_t HI0; /*!< Window Comparator High Threshold 0 Register */ - __IO uint32_t LO1; /*!< Window Comparator Low Threshold 1 Register */ - __IO uint32_t HI1; /*!< Window Comparator High Threshold 1 Register */ - __IO uint32_t MCTL[32]; /*!< Conversion Memory Control Register */ - __IO uint32_t MEM[32]; /*!< Conversion Memory Register */ - uint32_t RESERVED0[9]; - __IO uint32_t IER0; /*!< Interrupt Enable 0 Register */ - __IO uint32_t IER1; /*!< Interrupt Enable 1 Register */ - __I uint32_t IFGR0; /*!< Interrupt Flag 0 Register */ - __I uint32_t IFGR1; /*!< Interrupt Flag 1 Register */ - __O uint32_t CLRIFGR0; /*!< Clear Interrupt Flag 0 Register */ - __IO uint32_t CLRIFGR1; /*!< Clear Interrupt Flag 1 Register */ - __IO uint32_t IV; /*!< Interrupt Vector Register */ -} ADC14_Type; - -/*@}*/ /* end of group ADC14 */ - - -/****************************************************************************** -* AES256 Registers -******************************************************************************/ -/** @addtogroup AES256 MSP432P401R (AES256) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< AES Accelerator Control Register 0 */ - __IO uint16_t CTL1; /*!< AES Accelerator Control Register 1 */ - __IO uint16_t STAT; /*!< AES Accelerator Status Register */ - __O uint16_t KEY; /*!< AES Accelerator Key Register */ - __O uint16_t DIN; /*!< AES Accelerator Data In Register */ - __O uint16_t DOUT; /*!< AES Accelerator Data Out Register */ - __O uint16_t XDIN; /*!< AES Accelerator XORed Data In Register */ - __O uint16_t XIN; /*!< AES Accelerator XORed Data In Register */ -} AES256_Type; - -/*@}*/ /* end of group AES256 */ - - -/****************************************************************************** -* CAPTIO Registers -******************************************************************************/ -/** @addtogroup CAPTIO MSP432P401R (CAPTIO) - @{ -*/ -typedef struct { - uint16_t RESERVED0[7]; - __IO uint16_t CTL; /*!< Capacitive Touch IO x Control Register */ -} CAPTIO_Type; - -/*@}*/ /* end of group CAPTIO */ - - -/****************************************************************************** -* COMP_E Registers -******************************************************************************/ -/** @addtogroup COMP_E MSP432P401R (COMP_E) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< Comparator Control Register 0 */ - __IO uint16_t CTL1; /*!< Comparator Control Register 1 */ - __IO uint16_t CTL2; /*!< Comparator Control Register 2 */ - __IO uint16_t CTL3; /*!< Comparator Control Register 3 */ - uint16_t RESERVED0[2]; - __IO uint16_t INT; /*!< Comparator Interrupt Control Register */ - __I uint16_t IV; /*!< Comparator Interrupt Vector Word Register */ -} COMP_E_Type; - -/*@}*/ /* end of group COMP_E */ - - -/****************************************************************************** -* CRC32 Registers -******************************************************************************/ -/** @addtogroup CRC32 MSP432P401R (CRC32) - @{ -*/ -typedef struct { - __IO uint16_t DI32; /*!< Data Input for CRC32 Signature Computation */ - uint16_t RESERVED0; - __IO uint16_t DIRB32; /*!< Data In Reverse for CRC32 Computation */ - uint16_t RESERVED1; - __IO uint16_t INIRES32_LO; /*!< CRC32 Initialization and Result, lower 16 bits */ - __IO uint16_t INIRES32_HI; /*!< CRC32 Initialization and Result, upper 16 bits */ - __IO uint16_t RESR32_LO; /*!< CRC32 Result Reverse, lower 16 bits */ - __IO uint16_t RESR32_HI; /*!< CRC32 Result Reverse, Upper 16 bits */ - __IO uint16_t DI16; /*!< Data Input for CRC16 computation */ - uint16_t RESERVED2; - __IO uint16_t DIRB16; /*!< CRC16 Data In Reverse */ - uint16_t RESERVED3; - __IO uint16_t INIRES16; /*!< CRC16 Initialization and Result register */ - uint16_t RESERVED4[2]; - __IO uint16_t RESR16; /*!< CRC16 Result Reverse */ -} CRC32_Type; - -/*@}*/ /* end of group CRC32 */ - - -/****************************************************************************** -* CS Registers -******************************************************************************/ -/** @addtogroup CS MSP432P401R (CS) - @{ -*/ -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t CTL2; /*!< Control 2 Register */ - __IO uint32_t CTL3; /*!< Control 3 Register */ - uint32_t RESERVED0[7]; - __IO uint32_t CLKEN; /*!< Clock Enable Register */ - __I uint32_t STAT; /*!< Status Register */ - uint32_t RESERVED1[2]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - uint32_t RESERVED2; - __I uint32_t IFG; /*!< Interrupt Flag Register */ - uint32_t RESERVED3; - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - uint32_t RESERVED4; - __O uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - uint32_t RESERVED5; - __IO uint32_t DCOERCAL0; /*!< DCO External Resistor Cailbration 0 Register */ - __IO uint32_t DCOERCAL1; /*!< DCO External Resistor Calibration 1 Register */ -} CS_Type; - -/*@}*/ /* end of group CS */ - - -/****************************************************************************** -* DIO Registers -******************************************************************************/ -/** @addtogroup DIO MSP432P401R (DIO) - @{ -*/ -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - __I uint16_t IV_L; /*!< Low Port Interrupt Vector Value */ - uint16_t RESERVED0[3]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; - union { - __IO uint16_t IES; /*!< Port Pair Interrupt Edge Select */ - struct { - __IO uint8_t IES_L; /*!< Low Port Interrupt Edge Select */ - __IO uint8_t IES_H; /*!< High Port Interrupt Edge Select */ - }; - }; - union { - __IO uint16_t IE; /*!< Port Pair Interrupt Enable */ - struct { - __IO uint8_t IE_L; /*!< Low Port Interrupt Enable */ - __IO uint8_t IE_H; /*!< High Port Interrupt Enable */ - }; - }; - union { - __IO uint16_t IFG; /*!< Port Pair Interrupt Flag */ - struct { - __IO uint8_t IFG_L; /*!< Low Port Interrupt Flag */ - __IO uint8_t IFG_H; /*!< High Port Interrupt Flag */ - }; - }; - __I uint16_t IV_H; /*!< High Port Interrupt Vector Value */ -} DIO_PORT_Interruptable_Type; - -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - uint16_t RESERVED0[4]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; -} DIO_PORT_Not_Interruptable_Type; - - -typedef struct { - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED0; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED1; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED2; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED3; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED4; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED5; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED6; - __I uint16_t IV; /*!< Port Interrupt Vector Value */ - uint8_t RESERVED7[6]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ -} DIO_PORT_Odd_Interruptable_Type; - -typedef struct { - uint8_t RESERVED0; - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED1; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED2; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED3; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED4; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED5; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED6; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED7[9]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ - __I uint16_t IV; /*!< Port Interrupt Vector Value */ -} DIO_PORT_Even_Interruptable_Type; - -/*@}*/ /* end of group MSP432P401R_DIO */ - - -/****************************************************************************** -* DMA Registers -******************************************************************************/ -/** @addtogroup DMA MSP432P401R (DMA) - @{ -*/ -typedef struct { - __I uint32_t DEVICE_CFG; /*!< Device Configuration Status */ - __IO uint32_t SW_CHTRIG; /*!< Software Channel Trigger Register */ - uint32_t RESERVED0[2]; - __IO uint32_t CH_SRCCFG[32]; /*!< Channel n Source Configuration Register */ - uint32_t RESERVED1[28]; - __IO uint32_t INT1_SRCCFG; /*!< Interrupt 1 Source Channel Configuration */ - __IO uint32_t INT2_SRCCFG; /*!< Interrupt 2 Source Channel Configuration Register */ - __IO uint32_t INT3_SRCCFG; /*!< Interrupt 3 Source Channel Configuration Register */ - uint32_t RESERVED2; - __I uint32_t INT0_SRCFLG; /*!< Interrupt 0 Source Channel Flag Register */ - __O uint32_t INT0_CLRFLG; /*!< Interrupt 0 Source Channel Clear Flag Register */ -} DMA_Channel_Type; - -typedef struct { - __I uint32_t STAT; /*!< Status Register */ - __O uint32_t CFG; /*!< Configuration Register */ - __IO uint32_t CTLBASE; /*!< Channel Control Data Base Pointer Register */ - __I uint32_t ALTBASE; /*!< Channel Alternate Control Data Base Pointer Register */ - __I uint32_t WAITSTAT; /*!< Channel Wait on Request Status Register */ - __O uint32_t SWREQ; /*!< Channel Software Request Register */ - __IO uint32_t USEBURSTSET; /*!< Channel Useburst Set Register */ - __O uint32_t USEBURSTCLR; /*!< Channel Useburst Clear Register */ - __IO uint32_t REQMASKSET; /*!< Channel Request Mask Set Register */ - __O uint32_t REQMASKCLR; /*!< Channel Request Mask Clear Register */ - __IO uint32_t ENASET; /*!< Channel Enable Set Register */ - __O uint32_t ENACLR; /*!< Channel Enable Clear Register */ - __IO uint32_t ALTSET; /*!< Channel Primary-Alternate Set Register */ - __O uint32_t ALTCLR; /*!< Channel Primary-Alternate Clear Register */ - __IO uint32_t PRIOSET; /*!< Channel Priority Set Register */ - __O uint32_t PRIOCLR; /*!< Channel Priority Clear Register */ - uint32_t RESERVED4[3]; - __IO uint32_t ERRCLR; /*!< Bus Error Clear Register */ -} DMA_Control_Type; - -/*@}*/ /* end of group DMA */ - - -/****************************************************************************** -* EUSCI_A Registers -******************************************************************************/ -/** @addtogroup EUSCI_A MSP432P401R (EUSCI_A) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Ax Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Ax Baud Rate Control Word Register */ - __IO uint16_t MCTLW; /*!< eUSCI_Ax Modulation Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Ax Status Register */ - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - __IO uint16_t ABCTL; /*!< eUSCI_Ax Auto Baud Rate Control Register */ - __IO uint16_t IRCTL; /*!< eUSCI_Ax IrDA Control Word Register */ - uint16_t RESERVED1[3]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_Type; - -/*@}*/ /* end of group EUSCI_A */ - -/** @addtogroup EUSCI_A_SPI MSP432P401R (EUSCI_A_SPI) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Ax Bit Rate Control Register 1 */ - uint16_t RESERVED1; - __IO uint16_t STATW; - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - uint16_t RESERVED2[5]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_SPI_Type; - -/*@}*/ /* end of group EUSCI_A_SPI */ - - -/****************************************************************************** -* EUSCI_B Registers -******************************************************************************/ -/** @addtogroup EUSCI_B MSP432P401R (EUSCI_B) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Bx Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Bx Baud Rate Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Bx Status Register */ - __IO uint16_t TBCNT; /*!< eUSCI_Bx Byte Counter Threshold Register */ - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED1[2]; - __IO uint16_t I2COA0; /*!< eUSCI_Bx I2C Own Address 0 Register */ - __IO uint16_t I2COA1; /*!< eUSCI_Bx I2C Own Address 1 Register */ - __IO uint16_t I2COA2; /*!< eUSCI_Bx I2C Own Address 2 Register */ - __IO uint16_t I2COA3; /*!< eUSCI_Bx I2C Own Address 3 Register */ - __I uint16_t ADDRX; /*!< eUSCI_Bx I2C Received Address Register */ - __IO uint16_t ADDMASK; /*!< eUSCI_Bx I2C Address Mask Register */ - __IO uint16_t I2CSA; /*!< eUSCI_Bx I2C Slave Address Register */ - uint16_t RESERVED2[4]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_Type; - -/*@}*/ /* end of group EUSCI_B */ - -/** @addtogroup EUSCI_B_SPI MSP432P401R (EUSCI_B_SPI) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Bx Bit Rate Control Register 1 */ - __IO uint16_t STATW; - uint16_t RESERVED1; - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED2[13]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_SPI_Type; - -/*@}*/ /* end of group EUSCI_B_SPI */ - - -/****************************************************************************** -* FLCTL Registers -******************************************************************************/ -/** @addtogroup FLCTL MSP432P401R (FLCTL) - @{ -*/ -typedef struct { - __I uint32_t POWER_STAT; /*!< Power Status Register */ - uint32_t RESERVED0[3]; - __IO uint32_t BANK0_RDCTL; /*!< Bank0 Read Control Register */ - __IO uint32_t BANK1_RDCTL; /*!< Bank1 Read Control Register */ - uint32_t RESERVED1[2]; - __IO uint32_t RDBRST_CTLSTAT; /*!< Read Burst/Compare Control and Status Register */ - __IO uint32_t RDBRST_STARTADDR; /*!< Read Burst/Compare Start Address Register */ - __IO uint32_t RDBRST_LEN; /*!< Read Burst/Compare Length Register */ - uint32_t RESERVED2[4]; - __IO uint32_t RDBRST_FAILADDR; /*!< Read Burst/Compare Fail Address Register */ - __IO uint32_t RDBRST_FAILCNT; /*!< Read Burst/Compare Fail Count Register */ - uint32_t RESERVED3[3]; - __IO uint32_t PRG_CTLSTAT; /*!< Program Control and Status Register */ - __IO uint32_t PRGBRST_CTLSTAT; /*!< Program Burst Control and Status Register */ - __IO uint32_t PRGBRST_STARTADDR; /*!< Program Burst Start Address Register */ - uint32_t RESERVED4; - __IO uint32_t PRGBRST_DATA0_0; /*!< Program Burst Data0 Register0 */ - __IO uint32_t PRGBRST_DATA0_1; /*!< Program Burst Data0 Register1 */ - __IO uint32_t PRGBRST_DATA0_2; /*!< Program Burst Data0 Register2 */ - __IO uint32_t PRGBRST_DATA0_3; /*!< Program Burst Data0 Register3 */ - __IO uint32_t PRGBRST_DATA1_0; /*!< Program Burst Data1 Register0 */ - __IO uint32_t PRGBRST_DATA1_1; /*!< Program Burst Data1 Register1 */ - __IO uint32_t PRGBRST_DATA1_2; /*!< Program Burst Data1 Register2 */ - __IO uint32_t PRGBRST_DATA1_3; /*!< Program Burst Data1 Register3 */ - __IO uint32_t PRGBRST_DATA2_0; /*!< Program Burst Data2 Register0 */ - __IO uint32_t PRGBRST_DATA2_1; /*!< Program Burst Data2 Register1 */ - __IO uint32_t PRGBRST_DATA2_2; /*!< Program Burst Data2 Register2 */ - __IO uint32_t PRGBRST_DATA2_3; /*!< Program Burst Data2 Register3 */ - __IO uint32_t PRGBRST_DATA3_0; /*!< Program Burst Data3 Register0 */ - __IO uint32_t PRGBRST_DATA3_1; /*!< Program Burst Data3 Register1 */ - __IO uint32_t PRGBRST_DATA3_2; /*!< Program Burst Data3 Register2 */ - __IO uint32_t PRGBRST_DATA3_3; /*!< Program Burst Data3 Register3 */ - __IO uint32_t ERASE_CTLSTAT; /*!< Erase Control and Status Register */ - __IO uint32_t ERASE_SECTADDR; /*!< Erase Sector Address Register */ - uint32_t RESERVED5[2]; - __IO uint32_t BANK0_INFO_WEPROT; /*!< Information Memory Bank0 Write/Erase Protection Register */ - __IO uint32_t BANK0_MAIN_WEPROT; /*!< Main Memory Bank0 Write/Erase Protection Register */ - uint32_t RESERVED6[2]; - __IO uint32_t BANK1_INFO_WEPROT; /*!< Information Memory Bank1 Write/Erase Protection Register */ - __IO uint32_t BANK1_MAIN_WEPROT; /*!< Main Memory Bank1 Write/Erase Protection Register */ - uint32_t RESERVED7[2]; - __IO uint32_t BMRK_CTLSTAT; /*!< Benchmark Control and Status Register */ - __IO uint32_t BMRK_IFETCH; /*!< Benchmark Instruction Fetch Count Register */ - __IO uint32_t BMRK_DREAD; /*!< Benchmark Data Read Count Register */ - __IO uint32_t BMRK_CMP; /*!< Benchmark Count Compare Register */ - uint32_t RESERVED8[4]; - __IO uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - __IO uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - __I uint32_t READ_TIMCTL; /*!< Read Timing Control Register */ - __I uint32_t READMARGIN_TIMCTL; /*!< Read Margin Timing Control Register */ - __I uint32_t PRGVER_TIMCTL; /*!< Program Verify Timing Control Register */ - __I uint32_t ERSVER_TIMCTL; /*!< Erase Verify Timing Control Register */ - __I uint32_t LKGVER_TIMCTL; /*!< Leakage Verify Timing Control Register */ - __I uint32_t PROGRAM_TIMCTL; /*!< Program Timing Control Register */ - __I uint32_t ERASE_TIMCTL; /*!< Erase Timing Control Register */ - __I uint32_t MASSERASE_TIMCTL; /*!< Mass Erase Timing Control Register */ - __I uint32_t BURSTPRG_TIMCTL; /*!< Burst Program Timing Control Register */ -} FLCTL_Type; - -/*@}*/ /* end of group FLCTL */ - - -/****************************************************************************** -* FL_BOOTOVER_MAILBOX Registers -******************************************************************************/ -/** @addtogroup SEC_ZONE_PARAMS MSP432P401R (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t SEC_ZONE_SECEN; /*!< IP Protection Secure Zone Enable. */ - __IO uint32_t SEC_ZONE_START_ADDR; /*!< Start address of IP protected secure zone. */ - __IO uint32_t SEC_ZONE_LENGTH; /*!< Length of IP protected secure zone in number of bytes. */ - __IO uint32_t SEC_ZONE_AESINIT_VECT[4]; /*!< IP protected secure zone 0 AES initialization vector */ - __IO uint32_t SEC_ZONE_SECKEYS[8]; /*!< AES-CBC security keys. */ - __IO uint32_t SEC_ZONE_UNENC_PWD[4]; /*!< Unencrypted password for authentication. */ - __IO uint32_t SEC_ZONE_ENCUPDATE_EN; /*!< IP Protected Secure Zone Encrypted In-field Update Enable */ - __IO uint32_t SEC_ZONE_DATA_EN; /*!< IP Protected Secure Zone Data Access Enable */ - __IO uint32_t SEC_ZONE_ACK; /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */ - uint32_t RESERVED0[2]; -} SEC_ZONE_PARAMS_Type; - -/*@}*/ /* end of group SEC_ZONE_PARAMS */ - -/** @addtogroup SEC_ZONE_UPDATE MSP432P401R (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t SEC_ZONE_PAYLOADADDR; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t SEC_ZONE_PAYLOADLEN; /*!< Length of the payload in bytes. */ - __IO uint32_t SEC_ZONE_UPDATE_ACK; /*!< Acknowledgment for the IP Protected Secure Zone Update Command */ - uint32_t RESERVED0; -} SEC_ZONE_UPDATE_Type; - -/*@}*/ /* end of group SEC_ZONE_UPDATE */ - -/** @addtogroup FL_BOOTOVER_MAILBOX MSP432P401R (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t MB_START; /*!< Flash MailBox start: 0x0115ACF6 */ - __IO uint32_t CMD; /*!< Command for Boot override operations. */ - uint32_t RESERVED0[2]; - __IO uint32_t JTAG_SWD_LOCK_SECEN; /*!< JTAG and SWD Lock Enable */ - __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4]; /*!< JTAG and SWD lock AES initialization vector for AES-CBC */ - __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8]; /*!< JTAG and SWD lock AES CBC security Keys 0-7. */ - __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4]; /*!< JTAG and SWD lock unencrypted password */ - __IO uint32_t JTAG_SWD_LOCK_ACK; /*!< Acknowledgment for JTAG and SWD Lock command */ - uint32_t RESERVED1[2]; - SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4]; - __IO uint32_t BSL_ENABLE; /*!< BSL Enable. */ - __IO uint32_t BSL_START_ADDRESS; /*!< Contains the pointer to the BSL function. */ - __IO uint32_t BSL_PARAMETERS; /*!< BSL hardware invoke conifguration field. */ - uint32_t RESERVED2[2]; - __IO uint32_t BSL_ACK; /*!< Acknowledgment for the BSL Configuration Command */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN; /*!< Length of the encrypted payload in bytes */ - __IO uint32_t JTAG_SWD_LOCK_DST_ADDR; /*!< Destination address where the final data needs to be stored into the device. */ - __IO uint32_t ENC_UPDATE_ACK; /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */ - uint32_t RESERVED3; - SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4]; - uint32_t RESERVED4; - __IO uint32_t FACTORY_RESET_ENABLE; /*!< Enable/Disable Factory Reset */ - __IO uint32_t FACTORY_RESET_PWDEN; /*!< Factory reset password enable */ - __IO uint32_t FACTORY_RESET_PWD[4]; /*!< 128-bit Password for factory reset to be saved into the device. */ - __IO uint32_t FACTORY_RESET_PARAMS_ACK; /*!< Acknowledgment for the Factory Reset Params Command */ - uint32_t RESERVED5; - __IO uint32_t FACTORY_RESET_PASSWORD[4]; /*!< 128-bit Password for factory reset. */ - __IO uint32_t FACTORY_RESET_ACK; /*!< Acknowledgment for the Factory Reset Command */ - uint32_t RESERVED6[2]; - __IO uint32_t MB_END; /*!< Mailbox end */ -} FL_BOOTOVER_MAILBOX_Type; - -/*@}*/ /* end of group FL_BOOTOVER_MAILBOX */ - - -/****************************************************************************** -* PCM Registers -******************************************************************************/ -/** @addtogroup PCM MSP432P401R (PCM) - @{ -*/ -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PCM_Type; - -/*@}*/ /* end of group PCM */ - - -/****************************************************************************** -* PMAP Registers -******************************************************************************/ -/** @addtogroup PMAP MSP432P401R (PMAP) - @{ -*/ -typedef struct { - __IO uint16_t KEYID; - __IO uint16_t CTL; -} PMAP_COMMON_Type; - -typedef struct { - union { - __IO uint16_t PMAP_REGISTER[4]; - struct { - __IO uint8_t PMAP_REGISTER0; - __IO uint8_t PMAP_REGISTER1; - __IO uint8_t PMAP_REGISTER2; - __IO uint8_t PMAP_REGISTER3; - __IO uint8_t PMAP_REGISTER4; - __IO uint8_t PMAP_REGISTER5; - __IO uint8_t PMAP_REGISTER6; - __IO uint8_t PMAP_REGISTER7; - }; - }; -} PMAP_REGISTER_Type; - -/*@}*/ /* end of group PMAP */ - - -/****************************************************************************** -* PSS Registers -******************************************************************************/ -/** @addtogroup PSS MSP432P401R (PSS) - @{ -*/ -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - uint32_t RESERVED0[11]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PSS_Type; - -/*@}*/ /* end of group PSS */ - - -/****************************************************************************** -* REF_A Registers -******************************************************************************/ -/** @addtogroup REF_A MSP432P401R (REF_A) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< REF Control Register 0 */ -} REF_A_Type; - -/*@}*/ /* end of group REF_A */ - - -/****************************************************************************** -* RSTCTL Registers -******************************************************************************/ -/** @addtogroup RSTCTL MSP432P401R (RSTCTL) - @{ -*/ -typedef struct { - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __I uint32_t HARDRESET_STAT; /*!< Hard Reset Status Register */ - __IO uint32_t HARDRESET_CLR; /*!< Hard Reset Status Clear Register */ - __IO uint32_t HARDRESET_SET; /*!< Hard Reset Status Set Register */ - __I uint32_t SOFTRESET_STAT; /*!< Soft Reset Status Register */ - __IO uint32_t SOFTRESET_CLR; /*!< Soft Reset Status Clear Register */ - __IO uint32_t SOFTRESET_SET; /*!< Soft Reset Status Set Register */ - uint32_t RESERVED0[57]; - __I uint32_t PSSRESET_STAT; /*!< PSS Reset Status Register */ - __IO uint32_t PSSRESET_CLR; /*!< PSS Reset Status Clear Register */ - __I uint32_t PCMRESET_STAT; /*!< PCM Reset Status Register */ - __IO uint32_t PCMRESET_CLR; /*!< PCM Reset Status Clear Register */ - __I uint32_t PINRESET_STAT; /*!< Pin Reset Status Register */ - __IO uint32_t PINRESET_CLR; /*!< Pin Reset Status Clear Register */ - __I uint32_t REBOOTRESET_STAT; /*!< Reboot Reset Status Register */ - __IO uint32_t REBOOTRESET_CLR; /*!< Reboot Reset Status Clear Register */ - __I uint32_t CSRESET_STAT; /*!< CS Reset Status Register */ - __IO uint32_t CSRESET_CLR; /*!< CS Reset Status Clear Register */ -} RSTCTL_Type; - -/*@}*/ /* end of group RSTCTL */ - - -/****************************************************************************** -* RTC_C Registers -******************************************************************************/ -/** @addtogroup RTC_C MSP432P401R (RTC_C) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< RTCCTL0 Register */ - __IO uint16_t CTL13; /*!< RTCCTL13 Register */ - __IO uint16_t OCAL; /*!< RTCOCAL Register */ - __IO uint16_t TCMP; /*!< RTCTCMP Register */ - __IO uint16_t PS0CTL; /*!< Real-Time Clock Prescale Timer 0 Control Register */ - __IO uint16_t PS1CTL; /*!< Real-Time Clock Prescale Timer 1 Control Register */ - __IO uint16_t PS; /*!< Real-Time Clock Prescale Timer Counter Register */ - __I uint16_t IV; /*!< Real-Time Clock Interrupt Vector Register */ - __IO uint16_t TIM0; /*!< RTCTIM0 Register Hexadecimal Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week */ - __IO uint16_t DATE; /*!< RTCDATE - Hexadecimal Format */ - __IO uint16_t YEAR; /*!< RTCYEAR Register Hexadecimal Format */ - __IO uint16_t AMINHR; /*!< RTCMINHR - Hexadecimal Format */ - __IO uint16_t ADOWDAY; /*!< RTCADOWDAY - Hexadecimal Format */ - __IO uint16_t BIN2BCD; /*!< Binary-to-BCD Conversion Register */ - __IO uint16_t BCD2BIN; /*!< BCD-to-Binary Conversion Register */ -} RTC_C_Type; - -/*@}*/ /* end of group RTC_C */ - -/** @addtogroup RTC_C_BCD MSP432P401R (RTC_C_BCD) - @{ -*/ -typedef struct { - uint16_t RESERVED0[8]; - __IO uint16_t TIM0; /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week - BCD Format */ - __IO uint16_t DATE; /*!< Real-Time Clock Date - BCD Format */ - __IO uint16_t YEAR; /*!< Real-Time Clock Year Register - BCD Format */ - __IO uint16_t AMINHR; /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */ - __IO uint16_t ADOWDAY; /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */ -} RTC_C_BCD_Type; - -/*@}*/ /* end of group RTC_C_BCD */ - - -/****************************************************************************** -* SYSCTL Registers -******************************************************************************/ -/** @addtogroup SYSCTL MSP432P401R (SYSCTL) - @{ -*/ -typedef struct { - __IO uint32_t REBOOT_CTL; /*!< Reboot Control Register */ - __IO uint32_t NMI_CTLSTAT; /*!< NMI Control and Status Register */ - __IO uint32_t WDTRESET_CTL; /*!< Watchdog Reset Control Register */ - __IO uint32_t PERIHALT_CTL; /*!< Peripheral Halt Control Register */ - __I uint32_t SRAM_SIZE; /*!< SRAM Size Register */ - __IO uint32_t SRAM_BANKEN; /*!< SRAM Bank Enable Register */ - __IO uint32_t SRAM_BANKRET; /*!< SRAM Bank Retention Control Register */ - uint32_t RESERVED0; - __I uint32_t FLASH_SIZE; /*!< Flash Size Register */ - uint32_t RESERVED1[3]; - __IO uint32_t DIO_GLTFLT_CTL; /*!< Digital I/O Glitch Filter Control Register */ - uint32_t RESERVED2[3]; - __IO uint32_t SECDATA_UNLOCK; /*!< IP Protected Secure Zone Data Access Unlock Register */ -} SYSCTL_Type; - -typedef struct { - __IO uint32_t MASTER_UNLOCK; /*!< Master Unlock Register */ - __IO uint32_t BOOTOVER_REQ[2]; /*!< Boot Override Request Register */ - __IO uint32_t BOOTOVER_ACK; /*!< Boot Override Acknowledge Register */ - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __IO uint32_t RESET_STATOVER; /*!< Reset Status and Override Register */ - uint32_t RESERVED7[2]; - __I uint32_t SYSTEM_STAT; /*!< System Status Register */ -} SYSCTL_Boot_Type; - -/*@}*/ /* end of group SYSCTL */ - - -/****************************************************************************** -* Timer32 Registers -******************************************************************************/ -/** @addtogroup Timer32 MSP432P401R (Timer32) - @{ -*/ -typedef struct { - __IO uint32_t LOAD; /*!< Timer Load Register */ - __I uint32_t VALUE; /*!< Timer Current Value Register */ - __IO uint32_t CONTROL; /*!< Timer Control Register */ - __O uint32_t INTCLR; /*!< Timer Interrupt Clear Register */ - __I uint32_t RIS; /*!< Timer Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< Timer Interrupt Status Register */ - __IO uint32_t BGLOAD; /*!< Timer Background Load Register */ -} Timer32_Type; - -/*@}*/ /* end of group Timer32 */ - - -/****************************************************************************** -* Timer_A Registers -******************************************************************************/ -/** @addtogroup Timer_A MSP432P401R (Timer_A) - @{ -*/ -typedef struct { - __IO uint16_t CTL; /*!< TimerAx Control Register */ - __IO uint16_t CCTL[5]; /*!< Timer_A Capture/Compare Control Register */ - uint16_t RESERVED0[2]; - __IO uint16_t R; /*!< TimerA register */ - __IO uint16_t CCR[5]; /*!< Timer_A Capture/Compare Register */ - uint16_t RESERVED1[2]; - __IO uint16_t EX0; /*!< TimerAx Expansion 0 Register */ - uint16_t RESERVED2[6]; - __I uint16_t IV; /*!< TimerAx Interrupt Vector Register */ -} Timer_A_Type; - -/*@}*/ /* end of group Timer_A */ - - -/****************************************************************************** -* TLV Registers -******************************************************************************/ -/** @addtogroup TLV MSP432P401R (TLV) - @{ -*/ -typedef struct { - __I uint32_t TLV_CHECKSUM; /*!< TLV Checksum */ - __I uint32_t DEVICE_INFO_TAG; /*!< Device Info Tag */ - __I uint32_t DEVICE_INFO_LEN; /*!< Device Info Length */ - __I uint32_t DEVICE_ID; /*!< Device ID */ - __I uint32_t HWREV; /*!< HW Revision */ - __I uint32_t BCREV; /*!< Boot Code Revision */ - __I uint32_t ROM_DRVLIB_REV; /*!< ROM Driver Library Revision */ - __I uint32_t DIE_REC_TAG; /*!< Die Record Tag */ - __I uint32_t DIE_REC_LEN; /*!< Die Record Length */ - __I uint32_t DIE_XPOS; /*!< Die X-Position */ - __I uint32_t DIE_YPOS; /*!< Die Y-Position */ - __I uint32_t WAFER_ID; /*!< Wafer ID */ - __I uint32_t LOT_ID; /*!< Lot ID */ - __I uint32_t RESERVED0; /*!< Reserved */ - __I uint32_t RESERVED1; /*!< Reserved */ - __I uint32_t RESERVED2; /*!< Reserved */ - __I uint32_t TEST_RESULTS; /*!< Test Results */ - __I uint32_t CS_CAL_TAG; /*!< Clock System Calibration Tag */ - __I uint32_t CS_CAL_LEN; /*!< Clock System Calibration Length */ - __I uint32_t DCOIR_FCAL_RSEL04; /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_FCAL_RSEL5; /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED3; /*!< Reserved */ - __I uint32_t RESERVED4; /*!< Reserved */ - __I uint32_t RESERVED5; /*!< Reserved */ - __I uint32_t RESERVED6; /*!< Reserved */ - __I uint32_t DCOIR_CONSTK_RSEL04; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_CONSTK_RSEL5; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t DCOER_FCAL_RSEL04; /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOER_FCAL_RSEL5; /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED7; /*!< Reserved */ - __I uint32_t RESERVED8; /*!< Reserved */ - __I uint32_t RESERVED9; /*!< Reserved */ - __I uint32_t RESERVED10; /*!< Reserved */ - __I uint32_t DCOER_CONSTK_RSEL04; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I uint32_t DCOER_CONSTK_RSEL5; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t ADC14_CAL_TAG; /*!< ADC14 Calibration Tag */ - __I uint32_t ADC14_CAL_LEN; /*!< ADC14 Calibration Length */ - __I uint32_t ADC_GAIN_FACTOR; /*!< ADC Gain Factor */ - __I uint32_t ADC_OFFSET; /*!< ADC Offset */ - __I uint32_t RESERVED11; /*!< Reserved */ - __I uint32_t RESERVED12; /*!< Reserved */ - __I uint32_t RESERVED13; /*!< Reserved */ - __I uint32_t RESERVED14; /*!< Reserved */ - __I uint32_t RESERVED15; /*!< Reserved */ - __I uint32_t RESERVED16; /*!< Reserved */ - __I uint32_t RESERVED17; /*!< Reserved */ - __I uint32_t RESERVED18; /*!< Reserved */ - __I uint32_t RESERVED19; /*!< Reserved */ - __I uint32_t RESERVED20; /*!< Reserved */ - __I uint32_t RESERVED21; /*!< Reserved */ - __I uint32_t RESERVED22; /*!< Reserved */ - __I uint32_t RESERVED23; /*!< Reserved */ - __I uint32_t RESERVED24; /*!< Reserved */ - __I uint32_t RESERVED25; /*!< Reserved */ - __I uint32_t RESERVED26; /*!< Reserved */ - __I uint32_t ADC14_REF1P2V_TS30C; /*!< ADC14 1.2V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P2V_TS85C; /*!< ADC14 1.2V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF1P45V_TS30C; /*!< ADC14 1.45V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P45V_TS85C; /*!< ADC14 1.45V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF2P5V_TS30C; /*!< ADC14 2.5V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF2P5V_TS85C; /*!< ADC14 2.5V Reference Temp. Sensor 85C */ - __I uint32_t REF_CAL_TAG; /*!< REF Calibration Tag */ - __I uint32_t REF_CAL_LEN; /*!< REF Calibration Length */ - __I uint32_t REF_1P2V; /*!< REF 1.2V Reference */ - __I uint32_t REF_1P45V; /*!< REF 1.45V Reference */ - __I uint32_t REF_2P5V; /*!< REF 2.5V Reference */ - __I uint32_t FLASH_INFO_TAG; /*!< Flash Info Tag */ - __I uint32_t FLASH_INFO_LEN; /*!< Flash Info Length */ - __I uint32_t FLASH_MAX_PROG_PULSES; /*!< Flash Maximum Programming Pulses */ - __I uint32_t FLASH_MAX_ERASE_PULSES; /*!< Flash Maximum Erase Pulses */ - __I uint32_t RANDOM_NUM_TAG; /*!< 128-bit Random Number Tag */ - __I uint32_t RANDOM_NUM_LEN; /*!< 128-bit Random Number Length */ - __I uint32_t RANDOM_NUM_1; /*!< 32-bit Random Number 1 */ - __I uint32_t RANDOM_NUM_2; /*!< 32-bit Random Number 2 */ - __I uint32_t RANDOM_NUM_3; /*!< 32-bit Random Number 3 */ - __I uint32_t RANDOM_NUM_4; /*!< 32-bit Random Number 4 */ - __I uint32_t BSL_CFG_TAG; /*!< BSL Configuration Tag */ - __I uint32_t BSL_CFG_LEN; /*!< BSL Configuration Length */ - __I uint32_t BSL_PERIPHIF_SEL; /*!< BSL Peripheral Interface Selection */ - __I uint32_t BSL_PORTIF_CFG_UART; /*!< BSL Port Interface Configuration for UART */ - __I uint32_t BSL_PORTIF_CFG_SPI; /*!< BSL Port Interface Configuration for SPI */ - __I uint32_t BSL_PORTIF_CFG_I2C; /*!< BSL Port Interface Configuration for I2C */ - __I uint32_t TLV_END; /*!< TLV End Word */ -} TLV_Type; - -/*@}*/ /* end of group TLV */ - - -/****************************************************************************** -* WDT_A Registers -******************************************************************************/ -/** @addtogroup WDT_A MSP432P401R (WDT_A) - @{ -*/ -typedef struct { - uint16_t RESERVED0[6]; - __IO uint16_t CTL; /*!< Watchdog Timer Control Register */ -} WDT_A_Type; - -/*@}*/ /* end of group WDT_A */ - - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/*@}*/ /* end of group MSP432P401R_Peripherals */ - -/****************************************************************************** -* Peripheral declaration * -******************************************************************************/ -/** @addtogroup MSP432P401R_PeripheralDecl MSP432P401R Peripheral Declaration - @{ -*/ - -#define ADC14 ((ADC14_Type *) ADC14_BASE) -#define AES256 ((AES256_Type *) AES256_BASE) -#define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE) -#define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE) -#define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE) -#define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE) -#define CRC32 ((CRC32_Type *) CRC32_BASE) -#define CS ((CS_Type *) CS_BASE) -#define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120)) -#define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define DMA_Channel ((DMA_Channel_Type *) DMA_BASE) -#define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000)) -#define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE) -#define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE) -#define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE) -#define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE) -#define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE) -#define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE) -#define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE) -#define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE) -#define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE) -#define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE) -#define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE) -#define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE) -#define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE) -#define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE) -#define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE) -#define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE) -#define FLCTL ((FLCTL_Type *) FLCTL_BASE) -#define FL_BOOTOVER_MAILBOX ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE) -#define PCM ((PCM_Type *) PCM_BASE) -#define PMAP ((PMAP_COMMON_Type*) PMAP_BASE) -#define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008)) -#define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010)) -#define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018)) -#define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020)) -#define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028)) -#define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030)) -#define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038)) -#define PSS ((PSS_Type *) PSS_BASE) -#define REF_A ((REF_A_Type *) REF_A_BASE) -#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) -#define RTC_C ((RTC_C_Type *) RTC_C_BASE) -#define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE) -#define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE) -#define SYSCTL_Boot ((SYSCTL_Boot_Type *) (SYSCTL_BASE + 0x1000)) -#define TIMER32_1 ((Timer32_Type *) TIMER32_BASE) -#define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020)) -#define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE) -#define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE) -#define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE) -#define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE) -#define TLV ((TLV_Type *) TLV_BASE) -#define WDT_A ((WDT_A_Type *) WDT_A_BASE) - - -/*@}*/ /* end of group MSP432P401R_PeripheralDecl */ - -/*@}*/ /* end of group MSP432P401R_Definitions */ - -#endif /* __CMSIS_CONFIG__ */ - -/****************************************************************************** -* Peripheral register control bits * -******************************************************************************/ - -/****************************************************************************** -* ADC14 Bits -******************************************************************************/ -/* ADC14_CTL0[SC] Bits */ -#define ADC14_CTL0_SC_OFS ( 0) /*!< ADC14SC Bit Offset */ -#define ADC14_CTL0_SC ((uint32_t)0x00000001) /*!< ADC14 start conversion */ -/* ADC14_CTL0[ENC] Bits */ -#define ADC14_CTL0_ENC_OFS ( 1) /*!< ADC14ENC Bit Offset */ -#define ADC14_CTL0_ENC ((uint32_t)0x00000002) /*!< ADC14 enable conversion */ -/* ADC14_CTL0[ON] Bits */ -#define ADC14_CTL0_ON_OFS ( 4) /*!< ADC14ON Bit Offset */ -#define ADC14_CTL0_ON ((uint32_t)0x00000010) /*!< ADC14 on */ -/* ADC14_CTL0[MSC] Bits */ -#define ADC14_CTL0_MSC_OFS ( 7) /*!< ADC14MSC Bit Offset */ -#define ADC14_CTL0_MSC ((uint32_t)0x00000080) /*!< ADC14 multiple sample and conversion */ -/* ADC14_CTL0[SHT0] Bits */ -#define ADC14_CTL0_SHT0_OFS ( 8) /*!< ADC14SHT0 Bit Offset */ -#define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /*!< ADC14SHT0 Bit Mask */ -#define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /*!< SHT0 Bit 0 */ -#define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /*!< SHT0 Bit 1 */ -#define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /*!< SHT0 Bit 2 */ -#define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /*!< SHT0 Bit 3 */ -#define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /*!< 192 */ -#define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /*!< 192 */ -/* ADC14_CTL0[SHT1] Bits */ -#define ADC14_CTL0_SHT1_OFS (12) /*!< ADC14SHT1 Bit Offset */ -#define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /*!< ADC14SHT1 Bit Mask */ -#define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /*!< SHT1 Bit 0 */ -#define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /*!< SHT1 Bit 1 */ -#define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /*!< SHT1 Bit 2 */ -#define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /*!< SHT1 Bit 3 */ -#define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /*!< 192 */ -#define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /*!< 192 */ -/* ADC14_CTL0[BUSY] Bits */ -#define ADC14_CTL0_BUSY_OFS (16) /*!< ADC14BUSY Bit Offset */ -#define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /*!< ADC14 busy */ -/* ADC14_CTL0[CONSEQ] Bits */ -#define ADC14_CTL0_CONSEQ_OFS (17) /*!< ADC14CONSEQ Bit Offset */ -#define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /*!< ADC14CONSEQ Bit Mask */ -#define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /*!< CONSEQ Bit 0 */ -#define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /*!< CONSEQ Bit 1 */ -#define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /*!< Single-channel, single-conversion */ -#define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /*!< Sequence-of-channels */ -#define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /*!< Repeat-single-channel */ -#define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /*!< Repeat-sequence-of-channels */ -/* ADC14_CTL0[SSEL] Bits */ -#define ADC14_CTL0_SSEL_OFS (19) /*!< ADC14SSEL Bit Offset */ -#define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /*!< ADC14SSEL Bit Mask */ -#define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /*!< SSEL Bit 0 */ -#define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /*!< SSEL Bit 1 */ -#define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /*!< SSEL Bit 2 */ -#define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /*!< HSMCLK */ -#define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /*!< HSMCLK */ -/* ADC14_CTL0[DIV] Bits */ -#define ADC14_CTL0_DIV_OFS (22) /*!< ADC14DIV Bit Offset */ -#define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /*!< ADC14DIV Bit Mask */ -#define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /*!< DIV Bit 0 */ -#define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /*!< DIV Bit 1 */ -#define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /*!< DIV Bit 2 */ -#define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /*!< /8 */ -#define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /*!< /8 */ -/* ADC14_CTL0[ISSH] Bits */ -#define ADC14_CTL0_ISSH_OFS (25) /*!< ADC14ISSH Bit Offset */ -#define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /*!< ADC14 invert signal sample-and-hold */ -/* ADC14_CTL0[SHP] Bits */ -#define ADC14_CTL0_SHP_OFS (26) /*!< ADC14SHP Bit Offset */ -#define ADC14_CTL0_SHP ((uint32_t)0x04000000) /*!< ADC14 sample-and-hold pulse-mode select */ -/* ADC14_CTL0[SHS] Bits */ -#define ADC14_CTL0_SHS_OFS (27) /*!< ADC14SHS Bit Offset */ -#define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /*!< ADC14SHS Bit Mask */ -#define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /*!< SHS Bit 0 */ -#define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /*!< SHS Bit 1 */ -#define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /*!< SHS Bit 2 */ -#define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /*!< ADC14SC bit */ -#define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /*!< See device-specific data sheet for source */ -/* ADC14_CTL0[PDIV] Bits */ -#define ADC14_CTL0_PDIV_OFS (30) /*!< ADC14PDIV Bit Offset */ -#define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /*!< ADC14PDIV Bit Mask */ -#define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /*!< PDIV Bit 0 */ -#define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /*!< PDIV Bit 1 */ -#define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -#define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -/* ADC14_CTL1[PWRMD] Bits */ -#define ADC14_CTL1_PWRMD_OFS ( 0) /*!< ADC14PWRMD Bit Offset */ -#define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /*!< ADC14PWRMD Bit Mask */ -#define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /*!< PWRMD Bit 0 */ -#define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /*!< PWRMD Bit 1 */ -#define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /*!< Regular power mode for use with any resolution setting. Sample rate can be */ - /* up to 1 Msps. */ -#define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample */ - /* rate must not exceed 200 ksps. */ -/* ADC14_CTL1[REFBURST] Bits */ -#define ADC14_CTL1_REFBURST_OFS ( 2) /*!< ADC14REFBURST Bit Offset */ -#define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /*!< ADC14 reference buffer burst */ -/* ADC14_CTL1[DF] Bits */ -#define ADC14_CTL1_DF_OFS ( 3) /*!< ADC14DF Bit Offset */ -#define ADC14_CTL1_DF ((uint32_t)0x00000008) /*!< ADC14 data read-back format */ -/* ADC14_CTL1[RES] Bits */ -#define ADC14_CTL1_RES_OFS ( 4) /*!< ADC14RES Bit Offset */ -#define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /*!< ADC14RES Bit Mask */ -#define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /*!< RES Bit 0 */ -#define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /*!< RES Bit 1 */ -#define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -#define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -/* ADC14_CTL1[CSTARTADD] Bits */ -#define ADC14_CTL1_CSTARTADD_OFS (16) /*!< ADC14CSTARTADD Bit Offset */ -#define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /*!< ADC14CSTARTADD Bit Mask */ -/* ADC14_CTL1[BATMAP] Bits */ -#define ADC14_CTL1_BATMAP_OFS (22) /*!< ADC14BATMAP Bit Offset */ -#define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /*!< Controls 1/2 AVCC ADC input channel selection */ -/* ADC14_CTL1[TCMAP] Bits */ -#define ADC14_CTL1_TCMAP_OFS (23) /*!< ADC14TCMAP Bit Offset */ -#define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /*!< Controls temperature sensor ADC input channel selection */ -/* ADC14_CTL1[CH0MAP] Bits */ -#define ADC14_CTL1_CH0MAP_OFS (24) /*!< ADC14CH0MAP Bit Offset */ -#define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */ -/* ADC14_CTL1[CH1MAP] Bits */ -#define ADC14_CTL1_CH1MAP_OFS (25) /*!< ADC14CH1MAP Bit Offset */ -#define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */ -/* ADC14_CTL1[CH2MAP] Bits */ -#define ADC14_CTL1_CH2MAP_OFS (26) /*!< ADC14CH2MAP Bit Offset */ -#define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */ -/* ADC14_CTL1[CH3MAP] Bits */ -#define ADC14_CTL1_CH3MAP_OFS (27) /*!< ADC14CH3MAP Bit Offset */ -#define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */ -/* ADC14_LO0[LO0] Bits */ -#define ADC14_LO0_LO0_OFS ( 0) /*!< ADC14LO0 Bit Offset */ -#define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO0 Bit Mask */ -/* ADC14_HI0[HI0] Bits */ -#define ADC14_HI0_HI0_OFS ( 0) /*!< ADC14HI0 Bit Offset */ -#define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI0 Bit Mask */ -/* ADC14_LO1[LO1] Bits */ -#define ADC14_LO1_LO1_OFS ( 0) /*!< ADC14LO1 Bit Offset */ -#define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO1 Bit Mask */ -/* ADC14_HI1[HI1] Bits */ -#define ADC14_HI1_HI1_OFS ( 0) /*!< ADC14HI1 Bit Offset */ -#define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI1 Bit Mask */ -/* ADC14_MCTLN[INCH] Bits */ -#define ADC14_MCTLN_INCH_OFS ( 0) /*!< ADC14INCH Bit Offset */ -#define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /*!< ADC14INCH Bit Mask */ -#define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /*!< INCH Bit 0 */ -#define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /*!< INCH Bit 1 */ -#define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /*!< INCH Bit 2 */ -#define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /*!< INCH Bit 3 */ -#define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /*!< INCH Bit 4 */ -#define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -#define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -/* ADC14_MCTLN[EOS] Bits */ -#define ADC14_MCTLN_EOS_OFS ( 7) /*!< ADC14EOS Bit Offset */ -#define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /*!< End of sequence */ -/* ADC14_MCTLN[VRSEL] Bits */ -#define ADC14_MCTLN_VRSEL_OFS ( 8) /*!< ADC14VRSEL Bit Offset */ -#define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /*!< ADC14VRSEL Bit Mask */ -#define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /*!< VRSEL Bit 0 */ -#define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /*!< VRSEL Bit 1 */ -#define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /*!< VRSEL Bit 2 */ -#define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /*!< VRSEL Bit 3 */ -#define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /*!< V(R+) = AVCC, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /*!< V(R+) = VREF buffered, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /*!< V(R+) = VeREF+, V(R-) = VeREF- */ -#define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */ -/* ADC14_MCTLN[DIF] Bits */ -#define ADC14_MCTLN_DIF_OFS (13) /*!< ADC14DIF Bit Offset */ -#define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /*!< Differential mode */ -/* ADC14_MCTLN[WINC] Bits */ -#define ADC14_MCTLN_WINC_OFS (14) /*!< ADC14WINC Bit Offset */ -#define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /*!< Comparator window enable */ -/* ADC14_MCTLN[WINCTH] Bits */ -#define ADC14_MCTLN_WINCTH_OFS (15) /*!< ADC14WINCTH Bit Offset */ -#define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /*!< Window comparator threshold register selection */ -/* ADC14_MEMN[CONVRES] Bits */ -#define ADC14_MEMN_CONVRES_OFS ( 0) /*!< Conversion_Results Bit Offset */ -#define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /*!< Conversion_Results Bit Mask */ -/* ADC14_IER0[IE0] Bits */ -#define ADC14_IER0_IE0_OFS ( 0) /*!< ADC14IE0 Bit Offset */ -#define ADC14_IER0_IE0 ((uint32_t)0x00000001) /*!< Interrupt enable */ -/* ADC14_IER0[IE1] Bits */ -#define ADC14_IER0_IE1_OFS ( 1) /*!< ADC14IE1 Bit Offset */ -#define ADC14_IER0_IE1 ((uint32_t)0x00000002) /*!< Interrupt enable */ -/* ADC14_IER0[IE2] Bits */ -#define ADC14_IER0_IE2_OFS ( 2) /*!< ADC14IE2 Bit Offset */ -#define ADC14_IER0_IE2 ((uint32_t)0x00000004) /*!< Interrupt enable */ -/* ADC14_IER0[IE3] Bits */ -#define ADC14_IER0_IE3_OFS ( 3) /*!< ADC14IE3 Bit Offset */ -#define ADC14_IER0_IE3 ((uint32_t)0x00000008) /*!< Interrupt enable */ -/* ADC14_IER0[IE4] Bits */ -#define ADC14_IER0_IE4_OFS ( 4) /*!< ADC14IE4 Bit Offset */ -#define ADC14_IER0_IE4 ((uint32_t)0x00000010) /*!< Interrupt enable */ -/* ADC14_IER0[IE5] Bits */ -#define ADC14_IER0_IE5_OFS ( 5) /*!< ADC14IE5 Bit Offset */ -#define ADC14_IER0_IE5 ((uint32_t)0x00000020) /*!< Interrupt enable */ -/* ADC14_IER0[IE6] Bits */ -#define ADC14_IER0_IE6_OFS ( 6) /*!< ADC14IE6 Bit Offset */ -#define ADC14_IER0_IE6 ((uint32_t)0x00000040) /*!< Interrupt enable */ -/* ADC14_IER0[IE7] Bits */ -#define ADC14_IER0_IE7_OFS ( 7) /*!< ADC14IE7 Bit Offset */ -#define ADC14_IER0_IE7 ((uint32_t)0x00000080) /*!< Interrupt enable */ -/* ADC14_IER0[IE8] Bits */ -#define ADC14_IER0_IE8_OFS ( 8) /*!< ADC14IE8 Bit Offset */ -#define ADC14_IER0_IE8 ((uint32_t)0x00000100) /*!< Interrupt enable */ -/* ADC14_IER0[IE9] Bits */ -#define ADC14_IER0_IE9_OFS ( 9) /*!< ADC14IE9 Bit Offset */ -#define ADC14_IER0_IE9 ((uint32_t)0x00000200) /*!< Interrupt enable */ -/* ADC14_IER0[IE10] Bits */ -#define ADC14_IER0_IE10_OFS (10) /*!< ADC14IE10 Bit Offset */ -#define ADC14_IER0_IE10 ((uint32_t)0x00000400) /*!< Interrupt enable */ -/* ADC14_IER0[IE11] Bits */ -#define ADC14_IER0_IE11_OFS (11) /*!< ADC14IE11 Bit Offset */ -#define ADC14_IER0_IE11 ((uint32_t)0x00000800) /*!< Interrupt enable */ -/* ADC14_IER0[IE12] Bits */ -#define ADC14_IER0_IE12_OFS (12) /*!< ADC14IE12 Bit Offset */ -#define ADC14_IER0_IE12 ((uint32_t)0x00001000) /*!< Interrupt enable */ -/* ADC14_IER0[IE13] Bits */ -#define ADC14_IER0_IE13_OFS (13) /*!< ADC14IE13 Bit Offset */ -#define ADC14_IER0_IE13 ((uint32_t)0x00002000) /*!< Interrupt enable */ -/* ADC14_IER0[IE14] Bits */ -#define ADC14_IER0_IE14_OFS (14) /*!< ADC14IE14 Bit Offset */ -#define ADC14_IER0_IE14 ((uint32_t)0x00004000) /*!< Interrupt enable */ -/* ADC14_IER0[IE15] Bits */ -#define ADC14_IER0_IE15_OFS (15) /*!< ADC14IE15 Bit Offset */ -#define ADC14_IER0_IE15 ((uint32_t)0x00008000) /*!< Interrupt enable */ -/* ADC14_IER0[IE16] Bits */ -#define ADC14_IER0_IE16_OFS (16) /*!< ADC14IE16 Bit Offset */ -#define ADC14_IER0_IE16 ((uint32_t)0x00010000) /*!< Interrupt enable */ -/* ADC14_IER0[IE17] Bits */ -#define ADC14_IER0_IE17_OFS (17) /*!< ADC14IE17 Bit Offset */ -#define ADC14_IER0_IE17 ((uint32_t)0x00020000) /*!< Interrupt enable */ -/* ADC14_IER0[IE19] Bits */ -#define ADC14_IER0_IE19_OFS (19) /*!< ADC14IE19 Bit Offset */ -#define ADC14_IER0_IE19 ((uint32_t)0x00080000) /*!< Interrupt enable */ -/* ADC14_IER0[IE18] Bits */ -#define ADC14_IER0_IE18_OFS (18) /*!< ADC14IE18 Bit Offset */ -#define ADC14_IER0_IE18 ((uint32_t)0x00040000) /*!< Interrupt enable */ -/* ADC14_IER0[IE20] Bits */ -#define ADC14_IER0_IE20_OFS (20) /*!< ADC14IE20 Bit Offset */ -#define ADC14_IER0_IE20 ((uint32_t)0x00100000) /*!< Interrupt enable */ -/* ADC14_IER0[IE21] Bits */ -#define ADC14_IER0_IE21_OFS (21) /*!< ADC14IE21 Bit Offset */ -#define ADC14_IER0_IE21 ((uint32_t)0x00200000) /*!< Interrupt enable */ -/* ADC14_IER0[IE22] Bits */ -#define ADC14_IER0_IE22_OFS (22) /*!< ADC14IE22 Bit Offset */ -#define ADC14_IER0_IE22 ((uint32_t)0x00400000) /*!< Interrupt enable */ -/* ADC14_IER0[IE23] Bits */ -#define ADC14_IER0_IE23_OFS (23) /*!< ADC14IE23 Bit Offset */ -#define ADC14_IER0_IE23 ((uint32_t)0x00800000) /*!< Interrupt enable */ -/* ADC14_IER0[IE24] Bits */ -#define ADC14_IER0_IE24_OFS (24) /*!< ADC14IE24 Bit Offset */ -#define ADC14_IER0_IE24 ((uint32_t)0x01000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE25] Bits */ -#define ADC14_IER0_IE25_OFS (25) /*!< ADC14IE25 Bit Offset */ -#define ADC14_IER0_IE25 ((uint32_t)0x02000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE26] Bits */ -#define ADC14_IER0_IE26_OFS (26) /*!< ADC14IE26 Bit Offset */ -#define ADC14_IER0_IE26 ((uint32_t)0x04000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE27] Bits */ -#define ADC14_IER0_IE27_OFS (27) /*!< ADC14IE27 Bit Offset */ -#define ADC14_IER0_IE27 ((uint32_t)0x08000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE28] Bits */ -#define ADC14_IER0_IE28_OFS (28) /*!< ADC14IE28 Bit Offset */ -#define ADC14_IER0_IE28 ((uint32_t)0x10000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE29] Bits */ -#define ADC14_IER0_IE29_OFS (29) /*!< ADC14IE29 Bit Offset */ -#define ADC14_IER0_IE29 ((uint32_t)0x20000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE30] Bits */ -#define ADC14_IER0_IE30_OFS (30) /*!< ADC14IE30 Bit Offset */ -#define ADC14_IER0_IE30 ((uint32_t)0x40000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE31] Bits */ -#define ADC14_IER0_IE31_OFS (31) /*!< ADC14IE31 Bit Offset */ -#define ADC14_IER0_IE31 ((uint32_t)0x80000000) /*!< Interrupt enable */ -/* ADC14_IER1[INIE] Bits */ -#define ADC14_IER1_INIE_OFS ( 1) /*!< ADC14INIE Bit Offset */ -#define ADC14_IER1_INIE ((uint32_t)0x00000002) /*!< Interrupt enable for ADC14MEMx within comparator window */ -/* ADC14_IER1[LOIE] Bits */ -#define ADC14_IER1_LOIE_OFS ( 2) /*!< ADC14LOIE Bit Offset */ -#define ADC14_IER1_LOIE ((uint32_t)0x00000004) /*!< Interrupt enable for ADC14MEMx below comparator window */ -/* ADC14_IER1[HIIE] Bits */ -#define ADC14_IER1_HIIE_OFS ( 3) /*!< ADC14HIIE Bit Offset */ -#define ADC14_IER1_HIIE ((uint32_t)0x00000008) /*!< Interrupt enable for ADC14MEMx above comparator window */ -/* ADC14_IER1[OVIE] Bits */ -#define ADC14_IER1_OVIE_OFS ( 4) /*!< ADC14OVIE Bit Offset */ -#define ADC14_IER1_OVIE ((uint32_t)0x00000010) /*!< ADC14MEMx overflow-interrupt enable */ -/* ADC14_IER1[TOVIE] Bits */ -#define ADC14_IER1_TOVIE_OFS ( 5) /*!< ADC14TOVIE Bit Offset */ -#define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /*!< ADC14 conversion-time-overflow interrupt enable */ -/* ADC14_IER1[RDYIE] Bits */ -#define ADC14_IER1_RDYIE_OFS ( 6) /*!< ADC14RDYIE Bit Offset */ -#define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt enable */ -/* ADC14_IFGR0[IFG0] Bits */ -#define ADC14_IFGR0_IFG0_OFS ( 0) /*!< ADC14IFG0 Bit Offset */ -#define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /*!< ADC14MEM0 interrupt flag */ -/* ADC14_IFGR0[IFG1] Bits */ -#define ADC14_IFGR0_IFG1_OFS ( 1) /*!< ADC14IFG1 Bit Offset */ -#define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /*!< ADC14MEM1 interrupt flag */ -/* ADC14_IFGR0[IFG2] Bits */ -#define ADC14_IFGR0_IFG2_OFS ( 2) /*!< ADC14IFG2 Bit Offset */ -#define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /*!< ADC14MEM2 interrupt flag */ -/* ADC14_IFGR0[IFG3] Bits */ -#define ADC14_IFGR0_IFG3_OFS ( 3) /*!< ADC14IFG3 Bit Offset */ -#define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /*!< ADC14MEM3 interrupt flag */ -/* ADC14_IFGR0[IFG4] Bits */ -#define ADC14_IFGR0_IFG4_OFS ( 4) /*!< ADC14IFG4 Bit Offset */ -#define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /*!< ADC14MEM4 interrupt flag */ -/* ADC14_IFGR0[IFG5] Bits */ -#define ADC14_IFGR0_IFG5_OFS ( 5) /*!< ADC14IFG5 Bit Offset */ -#define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /*!< ADC14MEM5 interrupt flag */ -/* ADC14_IFGR0[IFG6] Bits */ -#define ADC14_IFGR0_IFG6_OFS ( 6) /*!< ADC14IFG6 Bit Offset */ -#define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /*!< ADC14MEM6 interrupt flag */ -/* ADC14_IFGR0[IFG7] Bits */ -#define ADC14_IFGR0_IFG7_OFS ( 7) /*!< ADC14IFG7 Bit Offset */ -#define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /*!< ADC14MEM7 interrupt flag */ -/* ADC14_IFGR0[IFG8] Bits */ -#define ADC14_IFGR0_IFG8_OFS ( 8) /*!< ADC14IFG8 Bit Offset */ -#define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /*!< ADC14MEM8 interrupt flag */ -/* ADC14_IFGR0[IFG9] Bits */ -#define ADC14_IFGR0_IFG9_OFS ( 9) /*!< ADC14IFG9 Bit Offset */ -#define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /*!< ADC14MEM9 interrupt flag */ -/* ADC14_IFGR0[IFG10] Bits */ -#define ADC14_IFGR0_IFG10_OFS (10) /*!< ADC14IFG10 Bit Offset */ -#define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /*!< ADC14MEM10 interrupt flag */ -/* ADC14_IFGR0[IFG11] Bits */ -#define ADC14_IFGR0_IFG11_OFS (11) /*!< ADC14IFG11 Bit Offset */ -#define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /*!< ADC14MEM11 interrupt flag */ -/* ADC14_IFGR0[IFG12] Bits */ -#define ADC14_IFGR0_IFG12_OFS (12) /*!< ADC14IFG12 Bit Offset */ -#define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /*!< ADC14MEM12 interrupt flag */ -/* ADC14_IFGR0[IFG13] Bits */ -#define ADC14_IFGR0_IFG13_OFS (13) /*!< ADC14IFG13 Bit Offset */ -#define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /*!< ADC14MEM13 interrupt flag */ -/* ADC14_IFGR0[IFG14] Bits */ -#define ADC14_IFGR0_IFG14_OFS (14) /*!< ADC14IFG14 Bit Offset */ -#define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /*!< ADC14MEM14 interrupt flag */ -/* ADC14_IFGR0[IFG15] Bits */ -#define ADC14_IFGR0_IFG15_OFS (15) /*!< ADC14IFG15 Bit Offset */ -#define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /*!< ADC14MEM15 interrupt flag */ -/* ADC14_IFGR0[IFG16] Bits */ -#define ADC14_IFGR0_IFG16_OFS (16) /*!< ADC14IFG16 Bit Offset */ -#define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /*!< ADC14MEM16 interrupt flag */ -/* ADC14_IFGR0[IFG17] Bits */ -#define ADC14_IFGR0_IFG17_OFS (17) /*!< ADC14IFG17 Bit Offset */ -#define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /*!< ADC14MEM17 interrupt flag */ -/* ADC14_IFGR0[IFG18] Bits */ -#define ADC14_IFGR0_IFG18_OFS (18) /*!< ADC14IFG18 Bit Offset */ -#define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /*!< ADC14MEM18 interrupt flag */ -/* ADC14_IFGR0[IFG19] Bits */ -#define ADC14_IFGR0_IFG19_OFS (19) /*!< ADC14IFG19 Bit Offset */ -#define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /*!< ADC14MEM19 interrupt flag */ -/* ADC14_IFGR0[IFG20] Bits */ -#define ADC14_IFGR0_IFG20_OFS (20) /*!< ADC14IFG20 Bit Offset */ -#define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /*!< ADC14MEM20 interrupt flag */ -/* ADC14_IFGR0[IFG21] Bits */ -#define ADC14_IFGR0_IFG21_OFS (21) /*!< ADC14IFG21 Bit Offset */ -#define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /*!< ADC14MEM21 interrupt flag */ -/* ADC14_IFGR0[IFG22] Bits */ -#define ADC14_IFGR0_IFG22_OFS (22) /*!< ADC14IFG22 Bit Offset */ -#define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /*!< ADC14MEM22 interrupt flag */ -/* ADC14_IFGR0[IFG23] Bits */ -#define ADC14_IFGR0_IFG23_OFS (23) /*!< ADC14IFG23 Bit Offset */ -#define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /*!< ADC14MEM23 interrupt flag */ -/* ADC14_IFGR0[IFG24] Bits */ -#define ADC14_IFGR0_IFG24_OFS (24) /*!< ADC14IFG24 Bit Offset */ -#define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /*!< ADC14MEM24 interrupt flag */ -/* ADC14_IFGR0[IFG25] Bits */ -#define ADC14_IFGR0_IFG25_OFS (25) /*!< ADC14IFG25 Bit Offset */ -#define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /*!< ADC14MEM25 interrupt flag */ -/* ADC14_IFGR0[IFG26] Bits */ -#define ADC14_IFGR0_IFG26_OFS (26) /*!< ADC14IFG26 Bit Offset */ -#define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /*!< ADC14MEM26 interrupt flag */ -/* ADC14_IFGR0[IFG27] Bits */ -#define ADC14_IFGR0_IFG27_OFS (27) /*!< ADC14IFG27 Bit Offset */ -#define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /*!< ADC14MEM27 interrupt flag */ -/* ADC14_IFGR0[IFG28] Bits */ -#define ADC14_IFGR0_IFG28_OFS (28) /*!< ADC14IFG28 Bit Offset */ -#define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /*!< ADC14MEM28 interrupt flag */ -/* ADC14_IFGR0[IFG29] Bits */ -#define ADC14_IFGR0_IFG29_OFS (29) /*!< ADC14IFG29 Bit Offset */ -#define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /*!< ADC14MEM29 interrupt flag */ -/* ADC14_IFGR0[IFG30] Bits */ -#define ADC14_IFGR0_IFG30_OFS (30) /*!< ADC14IFG30 Bit Offset */ -#define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /*!< ADC14MEM30 interrupt flag */ -/* ADC14_IFGR0[IFG31] Bits */ -#define ADC14_IFGR0_IFG31_OFS (31) /*!< ADC14IFG31 Bit Offset */ -#define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /*!< ADC14MEM31 interrupt flag */ -/* ADC14_IFGR1[INIFG] Bits */ -#define ADC14_IFGR1_INIFG_OFS ( 1) /*!< ADC14INIFG Bit Offset */ -#define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /*!< Interrupt flag for ADC14MEMx within comparator window */ -/* ADC14_IFGR1[LOIFG] Bits */ -#define ADC14_IFGR1_LOIFG_OFS ( 2) /*!< ADC14LOIFG Bit Offset */ -#define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /*!< Interrupt flag for ADC14MEMx below comparator window */ -/* ADC14_IFGR1[HIIFG] Bits */ -#define ADC14_IFGR1_HIIFG_OFS ( 3) /*!< ADC14HIIFG Bit Offset */ -#define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /*!< Interrupt flag for ADC14MEMx above comparator window */ -/* ADC14_IFGR1[OVIFG] Bits */ -#define ADC14_IFGR1_OVIFG_OFS ( 4) /*!< ADC14OVIFG Bit Offset */ -#define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /*!< ADC14MEMx overflow interrupt flag */ -/* ADC14_IFGR1[TOVIFG] Bits */ -#define ADC14_IFGR1_TOVIFG_OFS ( 5) /*!< ADC14TOVIFG Bit Offset */ -#define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /*!< ADC14 conversion time overflow interrupt flag */ -/* ADC14_IFGR1[RDYIFG] Bits */ -#define ADC14_IFGR1_RDYIFG_OFS ( 6) /*!< ADC14RDYIFG Bit Offset */ -#define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt flag */ -/* ADC14_CLRIFGR0[CLRIFG0] Bits */ -#define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /*!< CLRADC14IFG0 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /*!< clear ADC14IFG0 */ -/* ADC14_CLRIFGR0[CLRIFG1] Bits */ -#define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /*!< CLRADC14IFG1 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /*!< clear ADC14IFG1 */ -/* ADC14_CLRIFGR0[CLRIFG2] Bits */ -#define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /*!< CLRADC14IFG2 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /*!< clear ADC14IFG2 */ -/* ADC14_CLRIFGR0[CLRIFG3] Bits */ -#define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /*!< CLRADC14IFG3 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /*!< clear ADC14IFG3 */ -/* ADC14_CLRIFGR0[CLRIFG4] Bits */ -#define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /*!< CLRADC14IFG4 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /*!< clear ADC14IFG4 */ -/* ADC14_CLRIFGR0[CLRIFG5] Bits */ -#define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /*!< CLRADC14IFG5 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /*!< clear ADC14IFG5 */ -/* ADC14_CLRIFGR0[CLRIFG6] Bits */ -#define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /*!< CLRADC14IFG6 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /*!< clear ADC14IFG6 */ -/* ADC14_CLRIFGR0[CLRIFG7] Bits */ -#define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /*!< CLRADC14IFG7 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /*!< clear ADC14IFG7 */ -/* ADC14_CLRIFGR0[CLRIFG8] Bits */ -#define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /*!< CLRADC14IFG8 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /*!< clear ADC14IFG8 */ -/* ADC14_CLRIFGR0[CLRIFG9] Bits */ -#define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /*!< CLRADC14IFG9 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /*!< clear ADC14IFG9 */ -/* ADC14_CLRIFGR0[CLRIFG10] Bits */ -#define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /*!< CLRADC14IFG10 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /*!< clear ADC14IFG10 */ -/* ADC14_CLRIFGR0[CLRIFG11] Bits */ -#define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /*!< CLRADC14IFG11 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /*!< clear ADC14IFG11 */ -/* ADC14_CLRIFGR0[CLRIFG12] Bits */ -#define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /*!< CLRADC14IFG12 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /*!< clear ADC14IFG12 */ -/* ADC14_CLRIFGR0[CLRIFG13] Bits */ -#define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /*!< CLRADC14IFG13 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /*!< clear ADC14IFG13 */ -/* ADC14_CLRIFGR0[CLRIFG14] Bits */ -#define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /*!< CLRADC14IFG14 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /*!< clear ADC14IFG14 */ -/* ADC14_CLRIFGR0[CLRIFG15] Bits */ -#define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /*!< CLRADC14IFG15 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /*!< clear ADC14IFG15 */ -/* ADC14_CLRIFGR0[CLRIFG16] Bits */ -#define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /*!< CLRADC14IFG16 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /*!< clear ADC14IFG16 */ -/* ADC14_CLRIFGR0[CLRIFG17] Bits */ -#define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /*!< CLRADC14IFG17 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /*!< clear ADC14IFG17 */ -/* ADC14_CLRIFGR0[CLRIFG18] Bits */ -#define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /*!< CLRADC14IFG18 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /*!< clear ADC14IFG18 */ -/* ADC14_CLRIFGR0[CLRIFG19] Bits */ -#define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /*!< CLRADC14IFG19 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /*!< clear ADC14IFG19 */ -/* ADC14_CLRIFGR0[CLRIFG20] Bits */ -#define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /*!< CLRADC14IFG20 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /*!< clear ADC14IFG20 */ -/* ADC14_CLRIFGR0[CLRIFG21] Bits */ -#define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /*!< CLRADC14IFG21 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /*!< clear ADC14IFG21 */ -/* ADC14_CLRIFGR0[CLRIFG22] Bits */ -#define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /*!< CLRADC14IFG22 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /*!< clear ADC14IFG22 */ -/* ADC14_CLRIFGR0[CLRIFG23] Bits */ -#define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /*!< CLRADC14IFG23 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /*!< clear ADC14IFG23 */ -/* ADC14_CLRIFGR0[CLRIFG24] Bits */ -#define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /*!< CLRADC14IFG24 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /*!< clear ADC14IFG24 */ -/* ADC14_CLRIFGR0[CLRIFG25] Bits */ -#define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /*!< CLRADC14IFG25 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /*!< clear ADC14IFG25 */ -/* ADC14_CLRIFGR0[CLRIFG26] Bits */ -#define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /*!< CLRADC14IFG26 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /*!< clear ADC14IFG26 */ -/* ADC14_CLRIFGR0[CLRIFG27] Bits */ -#define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /*!< CLRADC14IFG27 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /*!< clear ADC14IFG27 */ -/* ADC14_CLRIFGR0[CLRIFG28] Bits */ -#define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /*!< CLRADC14IFG28 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /*!< clear ADC14IFG28 */ -/* ADC14_CLRIFGR0[CLRIFG29] Bits */ -#define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /*!< CLRADC14IFG29 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /*!< clear ADC14IFG29 */ -/* ADC14_CLRIFGR0[CLRIFG30] Bits */ -#define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /*!< CLRADC14IFG30 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /*!< clear ADC14IFG30 */ -/* ADC14_CLRIFGR0[CLRIFG31] Bits */ -#define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /*!< CLRADC14IFG31 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /*!< clear ADC14IFG31 */ -/* ADC14_CLRIFGR1[CLRINIFG] Bits */ -#define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /*!< CLRADC14INIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /*!< clear ADC14INIFG */ -/* ADC14_CLRIFGR1[CLRLOIFG] Bits */ -#define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /*!< CLRADC14LOIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /*!< clear ADC14LOIFG */ -/* ADC14_CLRIFGR1[CLRHIIFG] Bits */ -#define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /*!< CLRADC14HIIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /*!< clear ADC14HIIFG */ -/* ADC14_CLRIFGR1[CLROVIFG] Bits */ -#define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /*!< CLRADC14OVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /*!< clear ADC14OVIFG */ -/* ADC14_CLRIFGR1[CLRTOVIFG] Bits */ -#define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /*!< CLRADC14TOVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /*!< clear ADC14TOVIFG */ -/* ADC14_CLRIFGR1[CLRRDYIFG] Bits */ -#define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /*!< CLRADC14RDYIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /*!< clear ADC14RDYIFG */ - -/****************************************************************************** -* AES256 Bits -******************************************************************************/ -/* AES256_CTL0[OP] Bits */ -#define AES256_CTL0_OP_OFS ( 0) /*!< AESOPx Bit Offset */ -#define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /*!< AESOPx Bit Mask */ -#define AES256_CTL0_OP0 ((uint16_t)0x0001) /*!< OP Bit 0 */ -#define AES256_CTL0_OP1 ((uint16_t)0x0002) /*!< OP Bit 1 */ -#define AES256_CTL0_OP_0 ((uint16_t)0x0000) /*!< Encryption */ -#define AES256_CTL0_OP_1 ((uint16_t)0x0001) /*!< Decryption. The provided key is the same key used for encryption */ -#define AES256_CTL0_OP_2 ((uint16_t)0x0002) /*!< Generate first round key required for decryption */ -#define AES256_CTL0_OP_3 ((uint16_t)0x0003) /*!< Decryption. The provided key is the first round key required for decryption */ -/* AES256_CTL0[KL] Bits */ -#define AES256_CTL0_KL_OFS ( 2) /*!< AESKLx Bit Offset */ -#define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /*!< AESKLx Bit Mask */ -#define AES256_CTL0_KL0 ((uint16_t)0x0004) /*!< KL Bit 0 */ -#define AES256_CTL0_KL1 ((uint16_t)0x0008) /*!< KL Bit 1 */ -#define AES256_CTL0_KL_0 ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL_1 ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL_2 ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -#define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -/* AES256_CTL0[CM] Bits */ -#define AES256_CTL0_CM_OFS ( 5) /*!< AESCMx Bit Offset */ -#define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /*!< AESCMx Bit Mask */ -#define AES256_CTL0_CM0 ((uint16_t)0x0020) /*!< CM Bit 0 */ -#define AES256_CTL0_CM1 ((uint16_t)0x0040) /*!< CM Bit 1 */ -#define AES256_CTL0_CM_0 ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM_1 ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM_2 ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM_3 ((uint16_t)0x0060) /*!< CFB */ -#define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /*!< CFB */ -/* AES256_CTL0[SWRST] Bits */ -#define AES256_CTL0_SWRST_OFS ( 7) /*!< AESSWRST Bit Offset */ -#define AES256_CTL0_SWRST ((uint16_t)0x0080) /*!< AES software reset */ -/* AES256_CTL0[RDYIFG] Bits */ -#define AES256_CTL0_RDYIFG_OFS ( 8) /*!< AESRDYIFG Bit Offset */ -#define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /*!< AES ready interrupt flag */ -/* AES256_CTL0[ERRFG] Bits */ -#define AES256_CTL0_ERRFG_OFS (11) /*!< AESERRFG Bit Offset */ -#define AES256_CTL0_ERRFG ((uint16_t)0x0800) /*!< AES error flag */ -/* AES256_CTL0[RDYIE] Bits */ -#define AES256_CTL0_RDYIE_OFS (12) /*!< AESRDYIE Bit Offset */ -#define AES256_CTL0_RDYIE ((uint16_t)0x1000) /*!< AES ready interrupt enable */ -/* AES256_CTL0[CMEN] Bits */ -#define AES256_CTL0_CMEN_OFS (15) /*!< AESCMEN Bit Offset */ -#define AES256_CTL0_CMEN ((uint16_t)0x8000) /*!< AES cipher mode enable */ -/* AES256_CTL1[BLKCNT] Bits */ -#define AES256_CTL1_BLKCNT_OFS ( 0) /*!< AESBLKCNTx Bit Offset */ -#define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /*!< AESBLKCNTx Bit Mask */ -#define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /*!< BLKCNT Bit 0 */ -#define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /*!< BLKCNT Bit 1 */ -#define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /*!< BLKCNT Bit 2 */ -#define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /*!< BLKCNT Bit 3 */ -#define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /*!< BLKCNT Bit 4 */ -#define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /*!< BLKCNT Bit 5 */ -#define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /*!< BLKCNT Bit 6 */ -#define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /*!< BLKCNT Bit 7 */ -/* AES256_STAT[BUSY] Bits */ -#define AES256_STAT_BUSY_OFS ( 0) /*!< AESBUSY Bit Offset */ -#define AES256_STAT_BUSY ((uint16_t)0x0001) /*!< AES accelerator module busy */ -/* AES256_STAT[KEYWR] Bits */ -#define AES256_STAT_KEYWR_OFS ( 1) /*!< AESKEYWR Bit Offset */ -#define AES256_STAT_KEYWR ((uint16_t)0x0002) /*!< All 16 bytes written to AESAKEY */ -/* AES256_STAT[DINWR] Bits */ -#define AES256_STAT_DINWR_OFS ( 2) /*!< AESDINWR Bit Offset */ -#define AES256_STAT_DINWR ((uint16_t)0x0004) /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ -/* AES256_STAT[DOUTRD] Bits */ -#define AES256_STAT_DOUTRD_OFS ( 3) /*!< AESDOUTRD Bit Offset */ -#define AES256_STAT_DOUTRD ((uint16_t)0x0008) /*!< All 16 bytes read from AESADOUT */ -/* AES256_STAT[KEYCNT] Bits */ -#define AES256_STAT_KEYCNT_OFS ( 4) /*!< AESKEYCNTx Bit Offset */ -#define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /*!< AESKEYCNTx Bit Mask */ -#define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /*!< KEYCNT Bit 0 */ -#define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /*!< KEYCNT Bit 1 */ -#define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /*!< KEYCNT Bit 2 */ -#define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /*!< KEYCNT Bit 3 */ -/* AES256_STAT[DINCNT] Bits */ -#define AES256_STAT_DINCNT_OFS ( 8) /*!< AESDINCNTx Bit Offset */ -#define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /*!< AESDINCNTx Bit Mask */ -#define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /*!< DINCNT Bit 0 */ -#define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /*!< DINCNT Bit 1 */ -#define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /*!< DINCNT Bit 2 */ -#define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /*!< DINCNT Bit 3 */ -/* AES256_STAT[DOUTCNT] Bits */ -#define AES256_STAT_DOUTCNT_OFS (12) /*!< AESDOUTCNTx Bit Offset */ -#define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /*!< AESDOUTCNTx Bit Mask */ -#define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /*!< DOUTCNT Bit 0 */ -#define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /*!< DOUTCNT Bit 1 */ -#define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /*!< DOUTCNT Bit 2 */ -#define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /*!< DOUTCNT Bit 3 */ -/* AES256_KEY[KEY0] Bits */ -#define AES256_KEY_KEY0_OFS ( 0) /*!< AESKEY0x Bit Offset */ -#define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /*!< AESKEY0x Bit Mask */ -#define AES256_KEY_KEY00 ((uint16_t)0x0001) /*!< KEY0 Bit 0 */ -#define AES256_KEY_KEY01 ((uint16_t)0x0002) /*!< KEY0 Bit 1 */ -#define AES256_KEY_KEY02 ((uint16_t)0x0004) /*!< KEY0 Bit 2 */ -#define AES256_KEY_KEY03 ((uint16_t)0x0008) /*!< KEY0 Bit 3 */ -#define AES256_KEY_KEY04 ((uint16_t)0x0010) /*!< KEY0 Bit 4 */ -#define AES256_KEY_KEY05 ((uint16_t)0x0020) /*!< KEY0 Bit 5 */ -#define AES256_KEY_KEY06 ((uint16_t)0x0040) /*!< KEY0 Bit 6 */ -#define AES256_KEY_KEY07 ((uint16_t)0x0080) /*!< KEY0 Bit 7 */ -/* AES256_KEY[KEY1] Bits */ -#define AES256_KEY_KEY1_OFS ( 8) /*!< AESKEY1x Bit Offset */ -#define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /*!< AESKEY1x Bit Mask */ -#define AES256_KEY_KEY10 ((uint16_t)0x0100) /*!< KEY1 Bit 0 */ -#define AES256_KEY_KEY11 ((uint16_t)0x0200) /*!< KEY1 Bit 1 */ -#define AES256_KEY_KEY12 ((uint16_t)0x0400) /*!< KEY1 Bit 2 */ -#define AES256_KEY_KEY13 ((uint16_t)0x0800) /*!< KEY1 Bit 3 */ -#define AES256_KEY_KEY14 ((uint16_t)0x1000) /*!< KEY1 Bit 4 */ -#define AES256_KEY_KEY15 ((uint16_t)0x2000) /*!< KEY1 Bit 5 */ -#define AES256_KEY_KEY16 ((uint16_t)0x4000) /*!< KEY1 Bit 6 */ -#define AES256_KEY_KEY17 ((uint16_t)0x8000) /*!< KEY1 Bit 7 */ -/* AES256_DIN[DIN0] Bits */ -#define AES256_DIN_DIN0_OFS ( 0) /*!< AESDIN0x Bit Offset */ -#define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /*!< AESDIN0x Bit Mask */ -#define AES256_DIN_DIN00 ((uint16_t)0x0001) /*!< DIN0 Bit 0 */ -#define AES256_DIN_DIN01 ((uint16_t)0x0002) /*!< DIN0 Bit 1 */ -#define AES256_DIN_DIN02 ((uint16_t)0x0004) /*!< DIN0 Bit 2 */ -#define AES256_DIN_DIN03 ((uint16_t)0x0008) /*!< DIN0 Bit 3 */ -#define AES256_DIN_DIN04 ((uint16_t)0x0010) /*!< DIN0 Bit 4 */ -#define AES256_DIN_DIN05 ((uint16_t)0x0020) /*!< DIN0 Bit 5 */ -#define AES256_DIN_DIN06 ((uint16_t)0x0040) /*!< DIN0 Bit 6 */ -#define AES256_DIN_DIN07 ((uint16_t)0x0080) /*!< DIN0 Bit 7 */ -/* AES256_DIN[DIN1] Bits */ -#define AES256_DIN_DIN1_OFS ( 8) /*!< AESDIN1x Bit Offset */ -#define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /*!< AESDIN1x Bit Mask */ -#define AES256_DIN_DIN10 ((uint16_t)0x0100) /*!< DIN1 Bit 0 */ -#define AES256_DIN_DIN11 ((uint16_t)0x0200) /*!< DIN1 Bit 1 */ -#define AES256_DIN_DIN12 ((uint16_t)0x0400) /*!< DIN1 Bit 2 */ -#define AES256_DIN_DIN13 ((uint16_t)0x0800) /*!< DIN1 Bit 3 */ -#define AES256_DIN_DIN14 ((uint16_t)0x1000) /*!< DIN1 Bit 4 */ -#define AES256_DIN_DIN15 ((uint16_t)0x2000) /*!< DIN1 Bit 5 */ -#define AES256_DIN_DIN16 ((uint16_t)0x4000) /*!< DIN1 Bit 6 */ -#define AES256_DIN_DIN17 ((uint16_t)0x8000) /*!< DIN1 Bit 7 */ -/* AES256_DOUT[DOUT0] Bits */ -#define AES256_DOUT_DOUT0_OFS ( 0) /*!< AESDOUT0x Bit Offset */ -#define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /*!< AESDOUT0x Bit Mask */ -#define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /*!< DOUT0 Bit 0 */ -#define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /*!< DOUT0 Bit 1 */ -#define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /*!< DOUT0 Bit 2 */ -#define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /*!< DOUT0 Bit 3 */ -#define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /*!< DOUT0 Bit 4 */ -#define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /*!< DOUT0 Bit 5 */ -#define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /*!< DOUT0 Bit 6 */ -#define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /*!< DOUT0 Bit 7 */ -/* AES256_DOUT[DOUT1] Bits */ -#define AES256_DOUT_DOUT1_OFS ( 8) /*!< AESDOUT1x Bit Offset */ -#define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /*!< AESDOUT1x Bit Mask */ -#define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /*!< DOUT1 Bit 0 */ -#define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /*!< DOUT1 Bit 1 */ -#define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /*!< DOUT1 Bit 2 */ -#define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /*!< DOUT1 Bit 3 */ -#define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /*!< DOUT1 Bit 4 */ -#define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /*!< DOUT1 Bit 5 */ -#define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /*!< DOUT1 Bit 6 */ -#define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /*!< DOUT1 Bit 7 */ -/* AES256_XDIN[XDIN0] Bits */ -#define AES256_XDIN_XDIN0_OFS ( 0) /*!< AESXDIN0x Bit Offset */ -#define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /*!< AESXDIN0x Bit Mask */ -#define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /*!< XDIN0 Bit 0 */ -#define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /*!< XDIN0 Bit 1 */ -#define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /*!< XDIN0 Bit 2 */ -#define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /*!< XDIN0 Bit 3 */ -#define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /*!< XDIN0 Bit 4 */ -#define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /*!< XDIN0 Bit 5 */ -#define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /*!< XDIN0 Bit 6 */ -#define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /*!< XDIN0 Bit 7 */ -/* AES256_XDIN[XDIN1] Bits */ -#define AES256_XDIN_XDIN1_OFS ( 8) /*!< AESXDIN1x Bit Offset */ -#define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /*!< AESXDIN1x Bit Mask */ -#define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /*!< XDIN1 Bit 0 */ -#define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /*!< XDIN1 Bit 1 */ -#define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /*!< XDIN1 Bit 2 */ -#define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /*!< XDIN1 Bit 3 */ -#define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /*!< XDIN1 Bit 4 */ -#define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /*!< XDIN1 Bit 5 */ -#define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /*!< XDIN1 Bit 6 */ -#define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /*!< XDIN1 Bit 7 */ -/* AES256_XIN[XIN0] Bits */ -#define AES256_XIN_XIN0_OFS ( 0) /*!< AESXIN0x Bit Offset */ -#define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /*!< AESXIN0x Bit Mask */ -#define AES256_XIN_XIN00 ((uint16_t)0x0001) /*!< XIN0 Bit 0 */ -#define AES256_XIN_XIN01 ((uint16_t)0x0002) /*!< XIN0 Bit 1 */ -#define AES256_XIN_XIN02 ((uint16_t)0x0004) /*!< XIN0 Bit 2 */ -#define AES256_XIN_XIN03 ((uint16_t)0x0008) /*!< XIN0 Bit 3 */ -#define AES256_XIN_XIN04 ((uint16_t)0x0010) /*!< XIN0 Bit 4 */ -#define AES256_XIN_XIN05 ((uint16_t)0x0020) /*!< XIN0 Bit 5 */ -#define AES256_XIN_XIN06 ((uint16_t)0x0040) /*!< XIN0 Bit 6 */ -#define AES256_XIN_XIN07 ((uint16_t)0x0080) /*!< XIN0 Bit 7 */ -/* AES256_XIN[XIN1] Bits */ -#define AES256_XIN_XIN1_OFS ( 8) /*!< AESXIN1x Bit Offset */ -#define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /*!< AESXIN1x Bit Mask */ -#define AES256_XIN_XIN10 ((uint16_t)0x0100) /*!< XIN1 Bit 0 */ -#define AES256_XIN_XIN11 ((uint16_t)0x0200) /*!< XIN1 Bit 1 */ -#define AES256_XIN_XIN12 ((uint16_t)0x0400) /*!< XIN1 Bit 2 */ -#define AES256_XIN_XIN13 ((uint16_t)0x0800) /*!< XIN1 Bit 3 */ -#define AES256_XIN_XIN14 ((uint16_t)0x1000) /*!< XIN1 Bit 4 */ -#define AES256_XIN_XIN15 ((uint16_t)0x2000) /*!< XIN1 Bit 5 */ -#define AES256_XIN_XIN16 ((uint16_t)0x4000) /*!< XIN1 Bit 6 */ -#define AES256_XIN_XIN17 ((uint16_t)0x8000) /*!< XIN1 Bit 7 */ - -/****************************************************************************** -* CAPTIO Bits -******************************************************************************/ -/* CAPTIO_CTL[PISEL] Bits */ -#define CAPTIO_CTL_PISEL_OFS ( 1) /*!< CAPTIOPISELx Bit Offset */ -#define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /*!< CAPTIOPISELx Bit Mask */ -#define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /*!< PISEL Bit 0 */ -#define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /*!< PISEL Bit 1 */ -#define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /*!< PISEL Bit 2 */ -#define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /*!< Px.0 */ -#define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /*!< Px.1 */ -#define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /*!< Px.2 */ -#define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /*!< Px.3 */ -#define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /*!< Px.4 */ -#define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /*!< Px.5 */ -#define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /*!< Px.6 */ -#define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /*!< Px.7 */ -/* CAPTIO_CTL[POSEL] Bits */ -#define CAPTIO_CTL_POSEL_OFS ( 4) /*!< CAPTIOPOSELx Bit Offset */ -#define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /*!< CAPTIOPOSELx Bit Mask */ -#define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /*!< POSEL Bit 0 */ -#define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /*!< POSEL Bit 1 */ -#define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /*!< POSEL Bit 2 */ -#define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /*!< POSEL Bit 3 */ -#define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /*!< Px = P15 */ -#define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /*!< Px = P15 */ -/* CAPTIO_CTL[EN] Bits */ -#define CAPTIO_CTL_EN_OFS ( 8) /*!< CAPTIOEN Bit Offset */ -#define CAPTIO_CTL_EN ((uint16_t)0x0100) /*!< Capacitive Touch IO enable */ -/* CAPTIO_CTL[STATE] Bits */ -#define CAPTIO_CTL_STATE_OFS ( 9) /*!< CAPTIOSTATE Bit Offset */ -#define CAPTIO_CTL_STATE ((uint16_t)0x0200) /*!< Capacitive Touch IO state */ - -/****************************************************************************** -* COMP_E Bits -******************************************************************************/ -/* COMP_E_CTL0[IPSEL] Bits */ -#define COMP_E_CTL0_IPSEL_OFS ( 0) /*!< CEIPSEL Bit Offset */ -#define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /*!< CEIPSEL Bit Mask */ -#define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /*!< IPSEL Bit 0 */ -#define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /*!< IPSEL Bit 1 */ -#define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /*!< IPSEL Bit 2 */ -#define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /*!< IPSEL Bit 3 */ -#define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /*!< Channel 15 selected */ -/* COMP_E_CTL0[IPEN] Bits */ -#define COMP_E_CTL0_IPEN_OFS ( 7) /*!< CEIPEN Bit Offset */ -#define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /*!< Channel input enable for the V+ terminal */ -/* COMP_E_CTL0[IMSEL] Bits */ -#define COMP_E_CTL0_IMSEL_OFS ( 8) /*!< CEIMSEL Bit Offset */ -#define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /*!< CEIMSEL Bit Mask */ -#define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /*!< IMSEL Bit 0 */ -#define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /*!< IMSEL Bit 1 */ -#define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /*!< IMSEL Bit 2 */ -#define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /*!< IMSEL Bit 3 */ -#define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /*!< Channel 15 selected */ -/* COMP_E_CTL0[IMEN] Bits */ -#define COMP_E_CTL0_IMEN_OFS (15) /*!< CEIMEN Bit Offset */ -#define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /*!< Channel input enable for the - terminal */ -/* COMP_E_CTL1[OUT] Bits */ -#define COMP_E_CTL1_OUT_OFS ( 0) /*!< CEOUT Bit Offset */ -#define COMP_E_CTL1_OUT ((uint16_t)0x0001) /*!< Comparator output value */ -/* COMP_E_CTL1[OUTPOL] Bits */ -#define COMP_E_CTL1_OUTPOL_OFS ( 1) /*!< CEOUTPOL Bit Offset */ -#define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /*!< Comparator output polarity */ -/* COMP_E_CTL1[F] Bits */ -#define COMP_E_CTL1_F_OFS ( 2) /*!< CEF Bit Offset */ -#define COMP_E_CTL1_F ((uint16_t)0x0004) /*!< Comparator output filter */ -/* COMP_E_CTL1[IES] Bits */ -#define COMP_E_CTL1_IES_OFS ( 3) /*!< CEIES Bit Offset */ -#define COMP_E_CTL1_IES ((uint16_t)0x0008) /*!< Interrupt edge select for CEIIFG and CEIFG */ -/* COMP_E_CTL1[SHORT] Bits */ -#define COMP_E_CTL1_SHORT_OFS ( 4) /*!< CESHORT Bit Offset */ -#define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /*!< Input short */ -/* COMP_E_CTL1[EX] Bits */ -#define COMP_E_CTL1_EX_OFS ( 5) /*!< CEEX Bit Offset */ -#define COMP_E_CTL1_EX ((uint16_t)0x0020) /*!< Exchange */ -/* COMP_E_CTL1[FDLY] Bits */ -#define COMP_E_CTL1_FDLY_OFS ( 6) /*!< CEFDLY Bit Offset */ -#define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /*!< CEFDLY Bit Mask */ -#define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /*!< FDLY Bit 0 */ -#define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /*!< FDLY Bit 1 */ -#define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /*!< Typical filter delay of TBD (450) ns */ -#define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /*!< Typical filter delay of TBD (900) ns */ -#define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /*!< Typical filter delay of TBD (1800) ns */ -#define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /*!< Typical filter delay of TBD (3600) ns */ -/* COMP_E_CTL1[PWRMD] Bits */ -#define COMP_E_CTL1_PWRMD_OFS ( 8) /*!< CEPWRMD Bit Offset */ -#define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /*!< CEPWRMD Bit Mask */ -#define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /*!< PWRMD Bit 0 */ -#define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /*!< PWRMD Bit 1 */ -#define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /*!< High-speed mode */ -#define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /*!< Normal mode */ -#define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /*!< Ultra-low power mode */ -/* COMP_E_CTL1[ON] Bits */ -#define COMP_E_CTL1_ON_OFS (10) /*!< CEON Bit Offset */ -#define COMP_E_CTL1_ON ((uint16_t)0x0400) /*!< Comparator On */ -/* COMP_E_CTL1[MRVL] Bits */ -#define COMP_E_CTL1_MRVL_OFS (11) /*!< CEMRVL Bit Offset */ -#define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /*!< This bit is valid of CEMRVS is set to 1 */ -/* COMP_E_CTL1[MRVS] Bits */ -#define COMP_E_CTL1_MRVS_OFS (12) /*!< CEMRVS Bit Offset */ -#define COMP_E_CTL1_MRVS ((uint16_t)0x1000) -/* COMP_E_CTL2[REF0] Bits */ -#define COMP_E_CTL2_REF0_OFS ( 0) /*!< CEREF0 Bit Offset */ -#define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /*!< CEREF0 Bit Mask */ -#define COMP_E_CTL2_REF00 ((uint16_t)0x0001) /*!< REF0 Bit 0 */ -#define COMP_E_CTL2_REF01 ((uint16_t)0x0002) /*!< REF0 Bit 1 */ -#define COMP_E_CTL2_REF02 ((uint16_t)0x0004) /*!< REF0 Bit 2 */ -#define COMP_E_CTL2_REF03 ((uint16_t)0x0008) /*!< REF0 Bit 3 */ -#define COMP_E_CTL2_REF04 ((uint16_t)0x0010) /*!< REF0 Bit 4 */ -#define COMP_E_CTL2_REF0_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ -#define COMP_E_CTL2_REF0_1 ((uint16_t)0x0001) /*!< Reference resistor tap for setting 1. */ -#define COMP_E_CTL2_REF0_2 ((uint16_t)0x0002) /*!< Reference resistor tap for setting 2. */ -#define COMP_E_CTL2_REF0_3 ((uint16_t)0x0003) /*!< Reference resistor tap for setting 3. */ -#define COMP_E_CTL2_REF0_4 ((uint16_t)0x0004) /*!< Reference resistor tap for setting 4. */ -#define COMP_E_CTL2_REF0_5 ((uint16_t)0x0005) /*!< Reference resistor tap for setting 5. */ -#define COMP_E_CTL2_REF0_6 ((uint16_t)0x0006) /*!< Reference resistor tap for setting 6. */ -#define COMP_E_CTL2_REF0_7 ((uint16_t)0x0007) /*!< Reference resistor tap for setting 7. */ -#define COMP_E_CTL2_REF0_8 ((uint16_t)0x0008) /*!< Reference resistor tap for setting 8. */ -#define COMP_E_CTL2_REF0_9 ((uint16_t)0x0009) /*!< Reference resistor tap for setting 9. */ -#define COMP_E_CTL2_REF0_10 ((uint16_t)0x000A) /*!< Reference resistor tap for setting 10. */ -#define COMP_E_CTL2_REF0_11 ((uint16_t)0x000B) /*!< Reference resistor tap for setting 11. */ -#define COMP_E_CTL2_REF0_12 ((uint16_t)0x000C) /*!< Reference resistor tap for setting 12. */ -#define COMP_E_CTL2_REF0_13 ((uint16_t)0x000D) /*!< Reference resistor tap for setting 13. */ -#define COMP_E_CTL2_REF0_14 ((uint16_t)0x000E) /*!< Reference resistor tap for setting 14. */ -#define COMP_E_CTL2_REF0_15 ((uint16_t)0x000F) /*!< Reference resistor tap for setting 15. */ -#define COMP_E_CTL2_REF0_16 ((uint16_t)0x0010) /*!< Reference resistor tap for setting 16. */ -#define COMP_E_CTL2_REF0_17 ((uint16_t)0x0011) /*!< Reference resistor tap for setting 17. */ -#define COMP_E_CTL2_REF0_18 ((uint16_t)0x0012) /*!< Reference resistor tap for setting 18. */ -#define COMP_E_CTL2_REF0_19 ((uint16_t)0x0013) /*!< Reference resistor tap for setting 19. */ -#define COMP_E_CTL2_REF0_20 ((uint16_t)0x0014) /*!< Reference resistor tap for setting 20. */ -#define COMP_E_CTL2_REF0_21 ((uint16_t)0x0015) /*!< Reference resistor tap for setting 21. */ -#define COMP_E_CTL2_REF0_22 ((uint16_t)0x0016) /*!< Reference resistor tap for setting 22. */ -#define COMP_E_CTL2_REF0_23 ((uint16_t)0x0017) /*!< Reference resistor tap for setting 23. */ -#define COMP_E_CTL2_REF0_24 ((uint16_t)0x0018) /*!< Reference resistor tap for setting 24. */ -#define COMP_E_CTL2_REF0_25 ((uint16_t)0x0019) /*!< Reference resistor tap for setting 25. */ -#define COMP_E_CTL2_REF0_26 ((uint16_t)0x001A) /*!< Reference resistor tap for setting 26. */ -#define COMP_E_CTL2_REF0_27 ((uint16_t)0x001B) /*!< Reference resistor tap for setting 27. */ -#define COMP_E_CTL2_REF0_28 ((uint16_t)0x001C) /*!< Reference resistor tap for setting 28. */ -#define COMP_E_CTL2_REF0_29 ((uint16_t)0x001D) /*!< Reference resistor tap for setting 29. */ -#define COMP_E_CTL2_REF0_30 ((uint16_t)0x001E) /*!< Reference resistor tap for setting 30. */ -#define COMP_E_CTL2_REF0_31 ((uint16_t)0x001F) /*!< Reference resistor tap for setting 31. */ -/* COMP_E_CTL2[RSEL] Bits */ -#define COMP_E_CTL2_RSEL_OFS ( 5) /*!< CERSEL Bit Offset */ -#define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /*!< Reference select */ -/* COMP_E_CTL2[RS] Bits */ -#define COMP_E_CTL2_RS_OFS ( 6) /*!< CERS Bit Offset */ -#define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /*!< CERS Bit Mask */ -#define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /*!< RS Bit 0 */ -#define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /*!< RS Bit 1 */ -#define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /*!< No current is drawn by the reference circuitry */ -#define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /*!< VCC applied to the resistor ladder */ -#define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /*!< Shared reference voltage applied to the resistor ladder */ -#define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ -/* COMP_E_CTL2[REF1] Bits */ -#define COMP_E_CTL2_REF1_OFS ( 8) /*!< CEREF1 Bit Offset */ -#define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /*!< CEREF1 Bit Mask */ -#define COMP_E_CTL2_REF10 ((uint16_t)0x0100) /*!< REF1 Bit 0 */ -#define COMP_E_CTL2_REF11 ((uint16_t)0x0200) /*!< REF1 Bit 1 */ -#define COMP_E_CTL2_REF12 ((uint16_t)0x0400) /*!< REF1 Bit 2 */ -#define COMP_E_CTL2_REF13 ((uint16_t)0x0800) /*!< REF1 Bit 3 */ -#define COMP_E_CTL2_REF14 ((uint16_t)0x1000) /*!< REF1 Bit 4 */ -#define COMP_E_CTL2_REF1_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ -#define COMP_E_CTL2_REF1_1 ((uint16_t)0x0100) /*!< Reference resistor tap for setting 1. */ -#define COMP_E_CTL2_REF1_2 ((uint16_t)0x0200) /*!< Reference resistor tap for setting 2. */ -#define COMP_E_CTL2_REF1_3 ((uint16_t)0x0300) /*!< Reference resistor tap for setting 3. */ -#define COMP_E_CTL2_REF1_4 ((uint16_t)0x0400) /*!< Reference resistor tap for setting 4. */ -#define COMP_E_CTL2_REF1_5 ((uint16_t)0x0500) /*!< Reference resistor tap for setting 5. */ -#define COMP_E_CTL2_REF1_6 ((uint16_t)0x0600) /*!< Reference resistor tap for setting 6. */ -#define COMP_E_CTL2_REF1_7 ((uint16_t)0x0700) /*!< Reference resistor tap for setting 7. */ -#define COMP_E_CTL2_REF1_8 ((uint16_t)0x0800) /*!< Reference resistor tap for setting 8. */ -#define COMP_E_CTL2_REF1_9 ((uint16_t)0x0900) /*!< Reference resistor tap for setting 9. */ -#define COMP_E_CTL2_REF1_10 ((uint16_t)0x0A00) /*!< Reference resistor tap for setting 10. */ -#define COMP_E_CTL2_REF1_11 ((uint16_t)0x0B00) /*!< Reference resistor tap for setting 11. */ -#define COMP_E_CTL2_REF1_12 ((uint16_t)0x0C00) /*!< Reference resistor tap for setting 12. */ -#define COMP_E_CTL2_REF1_13 ((uint16_t)0x0D00) /*!< Reference resistor tap for setting 13. */ -#define COMP_E_CTL2_REF1_14 ((uint16_t)0x0E00) /*!< Reference resistor tap for setting 14. */ -#define COMP_E_CTL2_REF1_15 ((uint16_t)0x0F00) /*!< Reference resistor tap for setting 15. */ -#define COMP_E_CTL2_REF1_16 ((uint16_t)0x1000) /*!< Reference resistor tap for setting 16. */ -#define COMP_E_CTL2_REF1_17 ((uint16_t)0x1100) /*!< Reference resistor tap for setting 17. */ -#define COMP_E_CTL2_REF1_18 ((uint16_t)0x1200) /*!< Reference resistor tap for setting 18. */ -#define COMP_E_CTL2_REF1_19 ((uint16_t)0x1300) /*!< Reference resistor tap for setting 19. */ -#define COMP_E_CTL2_REF1_20 ((uint16_t)0x1400) /*!< Reference resistor tap for setting 20. */ -#define COMP_E_CTL2_REF1_21 ((uint16_t)0x1500) /*!< Reference resistor tap for setting 21. */ -#define COMP_E_CTL2_REF1_22 ((uint16_t)0x1600) /*!< Reference resistor tap for setting 22. */ -#define COMP_E_CTL2_REF1_23 ((uint16_t)0x1700) /*!< Reference resistor tap for setting 23. */ -#define COMP_E_CTL2_REF1_24 ((uint16_t)0x1800) /*!< Reference resistor tap for setting 24. */ -#define COMP_E_CTL2_REF1_25 ((uint16_t)0x1900) /*!< Reference resistor tap for setting 25. */ -#define COMP_E_CTL2_REF1_26 ((uint16_t)0x1A00) /*!< Reference resistor tap for setting 26. */ -#define COMP_E_CTL2_REF1_27 ((uint16_t)0x1B00) /*!< Reference resistor tap for setting 27. */ -#define COMP_E_CTL2_REF1_28 ((uint16_t)0x1C00) /*!< Reference resistor tap for setting 28. */ -#define COMP_E_CTL2_REF1_29 ((uint16_t)0x1D00) /*!< Reference resistor tap for setting 29. */ -#define COMP_E_CTL2_REF1_30 ((uint16_t)0x1E00) /*!< Reference resistor tap for setting 30. */ -#define COMP_E_CTL2_REF1_31 ((uint16_t)0x1F00) /*!< Reference resistor tap for setting 31. */ -/* COMP_E_CTL2[REFL] Bits */ -#define COMP_E_CTL2_REFL_OFS (13) /*!< CEREFL Bit Offset */ -#define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /*!< CEREFL Bit Mask */ -#define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /*!< REFL Bit 0 */ -#define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /*!< REFL Bit 1 */ -#define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -/* COMP_E_CTL2[REFACC] Bits */ -#define COMP_E_CTL2_REFACC_OFS (15) /*!< CEREFACC Bit Offset */ -#define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /*!< Reference accuracy */ -/* COMP_E_CTL3[PD0] Bits */ -#define COMP_E_CTL3_PD0_OFS ( 0) /*!< CEPD0 Bit Offset */ -#define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /*!< Port disable */ -/* COMP_E_CTL3[PD1] Bits */ -#define COMP_E_CTL3_PD1_OFS ( 1) /*!< CEPD1 Bit Offset */ -#define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /*!< Port disable */ -/* COMP_E_CTL3[PD2] Bits */ -#define COMP_E_CTL3_PD2_OFS ( 2) /*!< CEPD2 Bit Offset */ -#define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /*!< Port disable */ -/* COMP_E_CTL3[PD3] Bits */ -#define COMP_E_CTL3_PD3_OFS ( 3) /*!< CEPD3 Bit Offset */ -#define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /*!< Port disable */ -/* COMP_E_CTL3[PD4] Bits */ -#define COMP_E_CTL3_PD4_OFS ( 4) /*!< CEPD4 Bit Offset */ -#define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /*!< Port disable */ -/* COMP_E_CTL3[PD5] Bits */ -#define COMP_E_CTL3_PD5_OFS ( 5) /*!< CEPD5 Bit Offset */ -#define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /*!< Port disable */ -/* COMP_E_CTL3[PD6] Bits */ -#define COMP_E_CTL3_PD6_OFS ( 6) /*!< CEPD6 Bit Offset */ -#define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /*!< Port disable */ -/* COMP_E_CTL3[PD7] Bits */ -#define COMP_E_CTL3_PD7_OFS ( 7) /*!< CEPD7 Bit Offset */ -#define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /*!< Port disable */ -/* COMP_E_CTL3[PD8] Bits */ -#define COMP_E_CTL3_PD8_OFS ( 8) /*!< CEPD8 Bit Offset */ -#define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /*!< Port disable */ -/* COMP_E_CTL3[PD9] Bits */ -#define COMP_E_CTL3_PD9_OFS ( 9) /*!< CEPD9 Bit Offset */ -#define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /*!< Port disable */ -/* COMP_E_CTL3[PD10] Bits */ -#define COMP_E_CTL3_PD10_OFS (10) /*!< CEPD10 Bit Offset */ -#define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /*!< Port disable */ -/* COMP_E_CTL3[PD11] Bits */ -#define COMP_E_CTL3_PD11_OFS (11) /*!< CEPD11 Bit Offset */ -#define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /*!< Port disable */ -/* COMP_E_CTL3[PD12] Bits */ -#define COMP_E_CTL3_PD12_OFS (12) /*!< CEPD12 Bit Offset */ -#define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /*!< Port disable */ -/* COMP_E_CTL3[PD13] Bits */ -#define COMP_E_CTL3_PD13_OFS (13) /*!< CEPD13 Bit Offset */ -#define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /*!< Port disable */ -/* COMP_E_CTL3[PD14] Bits */ -#define COMP_E_CTL3_PD14_OFS (14) /*!< CEPD14 Bit Offset */ -#define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /*!< Port disable */ -/* COMP_E_CTL3[PD15] Bits */ -#define COMP_E_CTL3_PD15_OFS (15) /*!< CEPD15 Bit Offset */ -#define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /*!< Port disable */ -/* COMP_E_INT[IFG] Bits */ -#define COMP_E_INT_IFG_OFS ( 0) /*!< CEIFG Bit Offset */ -#define COMP_E_INT_IFG ((uint16_t)0x0001) /*!< Comparator output interrupt flag */ -/* COMP_E_INT[IIFG] Bits */ -#define COMP_E_INT_IIFG_OFS ( 1) /*!< CEIIFG Bit Offset */ -#define COMP_E_INT_IIFG ((uint16_t)0x0002) /*!< Comparator output inverted interrupt flag */ -/* COMP_E_INT[RDYIFG] Bits */ -#define COMP_E_INT_RDYIFG_OFS ( 4) /*!< CERDYIFG Bit Offset */ -#define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /*!< Comparator ready interrupt flag */ -/* COMP_E_INT[IE] Bits */ -#define COMP_E_INT_IE_OFS ( 8) /*!< CEIE Bit Offset */ -#define COMP_E_INT_IE ((uint16_t)0x0100) /*!< Comparator output interrupt enable */ -/* COMP_E_INT[IIE] Bits */ -#define COMP_E_INT_IIE_OFS ( 9) /*!< CEIIE Bit Offset */ -#define COMP_E_INT_IIE ((uint16_t)0x0200) /*!< Comparator output interrupt enable inverted polarity */ -/* COMP_E_INT[RDYIE] Bits */ -#define COMP_E_INT_RDYIE_OFS (12) /*!< CERDYIE Bit Offset */ -#define COMP_E_INT_RDYIE ((uint16_t)0x1000) /*!< Comparator ready interrupt enable */ - -/****************************************************************************** -* COREDEBUG Bits -******************************************************************************/ - - -/****************************************************************************** -* CRC32 Bits -******************************************************************************/ - -/****************************************************************************** -* CS Bits -******************************************************************************/ -/* CS_KEY[KEY] Bits */ -#define CS_KEY_KEY_OFS ( 0) /*!< CSKEY Bit Offset */ -#define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< CSKEY Bit Mask */ -/* CS_CTL0[DCOTUNE] Bits */ -#define CS_CTL0_DCOTUNE_OFS ( 0) /*!< DCOTUNE Bit Offset */ -#define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /*!< DCOTUNE Bit Mask */ -/* CS_CTL0[DCORSEL] Bits */ -#define CS_CTL0_DCORSEL_OFS (16) /*!< DCORSEL Bit Offset */ -#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /*!< DCORSEL Bit Mask */ -#define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /*!< DCORSEL Bit 0 */ -#define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /*!< DCORSEL Bit 1 */ -#define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /*!< DCORSEL Bit 2 */ -#define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */ -#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */ -#define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */ -#define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */ -#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */ -#define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */ -/* CS_CTL0[DCORES] Bits */ -#define CS_CTL0_DCORES_OFS (22) /*!< DCORES Bit Offset */ -#define CS_CTL0_DCORES ((uint32_t)0x00400000) /*!< Enables the DCO external resistor mode */ -/* CS_CTL0[DCOEN] Bits */ -#define CS_CTL0_DCOEN_OFS (23) /*!< DCOEN Bit Offset */ -#define CS_CTL0_DCOEN ((uint32_t)0x00800000) /*!< Enables the DCO oscillator */ -/* CS_CTL1[SELM] Bits */ -#define CS_CTL1_SELM_OFS ( 0) /*!< SELM Bit Offset */ -#define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /*!< SELM Bit Mask */ -#define CS_CTL1_SELM0 ((uint32_t)0x00000001) /*!< SELM Bit 0 */ -#define CS_CTL1_SELM1 ((uint32_t)0x00000002) /*!< SELM Bit 1 */ -#define CS_CTL1_SELM2 ((uint32_t)0x00000004) /*!< SELM Bit 2 */ -#define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM_1 ((uint32_t)0x00000001) -#define CS_CTL1_SELM_2 ((uint32_t)0x00000002) -#define CS_CTL1_SELM_3 ((uint32_t)0x00000003) -#define CS_CTL1_SELM_4 ((uint32_t)0x00000004) -#define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001) -#define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002) -#define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003) -#define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004) -#define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -/* CS_CTL1[SELS] Bits */ -#define CS_CTL1_SELS_OFS ( 4) /*!< SELS Bit Offset */ -#define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /*!< SELS Bit Mask */ -#define CS_CTL1_SELS0 ((uint32_t)0x00000010) /*!< SELS Bit 0 */ -#define CS_CTL1_SELS1 ((uint32_t)0x00000020) /*!< SELS Bit 1 */ -#define CS_CTL1_SELS2 ((uint32_t)0x00000040) /*!< SELS Bit 2 */ -#define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS_1 ((uint32_t)0x00000010) -#define CS_CTL1_SELS_2 ((uint32_t)0x00000020) -#define CS_CTL1_SELS_3 ((uint32_t)0x00000030) -#define CS_CTL1_SELS_4 ((uint32_t)0x00000040) -#define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010) -#define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020) -#define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030) -#define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040) -#define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -/* CS_CTL1[SELA] Bits */ -#define CS_CTL1_SELA_OFS ( 8) /*!< SELA Bit Offset */ -#define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /*!< SELA Bit Mask */ -#define CS_CTL1_SELA0 ((uint32_t)0x00000100) /*!< SELA Bit 0 */ -#define CS_CTL1_SELA1 ((uint32_t)0x00000200) /*!< SELA Bit 1 */ -#define CS_CTL1_SELA2 ((uint32_t)0x00000400) /*!< SELA Bit 2 */ -#define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA_1 ((uint32_t)0x00000100) -#define CS_CTL1_SELA_2 ((uint32_t)0x00000200) -#define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100) -#define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200) -/* CS_CTL1[SELB] Bits */ -#define CS_CTL1_SELB_OFS (12) /*!< SELB Bit Offset */ -#define CS_CTL1_SELB ((uint32_t)0x00001000) /*!< Selects the BCLK source */ -/* CS_CTL1[DIVM] Bits */ -#define CS_CTL1_DIVM_OFS (16) /*!< DIVM Bit Offset */ -#define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /*!< DIVM Bit Mask */ -#define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /*!< DIVM Bit 0 */ -#define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /*!< DIVM Bit 1 */ -#define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /*!< DIVM Bit 2 */ -#define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -#define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -/* CS_CTL1[DIVHS] Bits */ -#define CS_CTL1_DIVHS_OFS (20) /*!< DIVHS Bit Offset */ -#define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /*!< DIVHS Bit Mask */ -#define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /*!< DIVHS Bit 0 */ -#define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /*!< DIVHS Bit 1 */ -#define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /*!< DIVHS Bit 2 */ -#define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -#define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -/* CS_CTL1[DIVA] Bits */ -#define CS_CTL1_DIVA_OFS (24) /*!< DIVA Bit Offset */ -#define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /*!< DIVA Bit Mask */ -#define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /*!< DIVA Bit 0 */ -#define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /*!< DIVA Bit 1 */ -#define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /*!< DIVA Bit 2 */ -#define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -#define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -/* CS_CTL1[DIVS] Bits */ -#define CS_CTL1_DIVS_OFS (28) /*!< DIVS Bit Offset */ -#define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /*!< DIVS Bit Mask */ -#define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /*!< DIVS Bit 0 */ -#define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /*!< DIVS Bit 1 */ -#define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /*!< DIVS Bit 2 */ -#define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -#define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -/* CS_CTL2[LFXTDRIVE] Bits */ -#define CS_CTL2_LFXTDRIVE_OFS ( 0) /*!< LFXTDRIVE Bit Offset */ -#define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /*!< LFXTDRIVE Bit Mask */ -#define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /*!< LFXTDRIVE Bit 0 */ -#define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /*!< LFXTDRIVE Bit 1 */ -#define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /*!< Lowest drive strength and current consumption LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */ -/* CS_CTL2[LFXT_EN] Bits */ -#define CS_CTL2_LFXT_EN_OFS ( 8) /*!< LFXT_EN Bit Offset */ -#define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /*!< Turns on the LFXT oscillator regardless if used as a clock resource */ -/* CS_CTL2[LFXTBYPASS] Bits */ -#define CS_CTL2_LFXTBYPASS_OFS ( 9) /*!< LFXTBYPASS Bit Offset */ -#define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /*!< LFXT bypass select */ -/* CS_CTL2[HFXTDRIVE] Bits */ -#define CS_CTL2_HFXTDRIVE_OFS (16) /*!< HFXTDRIVE Bit Offset */ -#define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /*!< HFXT oscillator drive selection */ -/* CS_CTL2[HFXTFREQ] Bits */ -#define CS_CTL2_HFXTFREQ_OFS (20) /*!< HFXTFREQ Bit Offset */ -#define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /*!< HFXTFREQ Bit Mask */ -#define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /*!< HFXTFREQ Bit 0 */ -#define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /*!< HFXTFREQ Bit 1 */ -#define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /*!< HFXTFREQ Bit 2 */ -#define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /*!< 1 MHz to 4 MHz */ -#define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /*!< >4 MHz to 8 MHz */ -#define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /*!< >8 MHz to 16 MHz */ -#define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /*!< >16 MHz to 24 MHz */ -#define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /*!< >24 MHz to 32 MHz */ -#define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /*!< >32 MHz to 40 MHz */ -#define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /*!< >40 MHz to 48 MHz */ -#define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /*!< Reserved for future use. */ -/* CS_CTL2[HFXT_EN] Bits */ -#define CS_CTL2_HFXT_EN_OFS (24) /*!< HFXT_EN Bit Offset */ -#define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /*!< Turns on the HFXT oscillator regardless if used as a clock resource */ -/* CS_CTL2[HFXTBYPASS] Bits */ -#define CS_CTL2_HFXTBYPASS_OFS (25) /*!< HFXTBYPASS Bit Offset */ -#define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /*!< HFXT bypass select */ -/* CS_CTL3[FCNTLF] Bits */ -#define CS_CTL3_FCNTLF_OFS ( 0) /*!< FCNTLF Bit Offset */ -#define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /*!< FCNTLF Bit Mask */ -#define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /*!< FCNTLF Bit 0 */ -#define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /*!< FCNTLF Bit 1 */ -#define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /*!< 32768 cycles */ -#define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /*!< 32768 cycles */ -/* CS_CTL3[RFCNTLF] Bits */ -#define CS_CTL3_RFCNTLF_OFS ( 2) /*!< RFCNTLF Bit Offset */ -#define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /*!< Reset start fault counter for LFXT */ -/* CS_CTL3[FCNTLF_EN] Bits */ -#define CS_CTL3_FCNTLF_EN_OFS ( 3) /*!< FCNTLF_EN Bit Offset */ -#define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /*!< Enable start fault counter for LFXT */ -/* CS_CTL3[FCNTHF] Bits */ -#define CS_CTL3_FCNTHF_OFS ( 4) /*!< FCNTHF Bit Offset */ -#define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /*!< FCNTHF Bit Mask */ -#define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /*!< FCNTHF Bit 0 */ -#define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /*!< FCNTHF Bit 1 */ -#define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /*!< 16384 cycles */ -#define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /*!< 16384 cycles */ -/* CS_CTL3[RFCNTHF] Bits */ -#define CS_CTL3_RFCNTHF_OFS ( 6) /*!< RFCNTHF Bit Offset */ -#define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /*!< Reset start fault counter for HFXT */ -/* CS_CTL3[FCNTHF_EN] Bits */ -#define CS_CTL3_FCNTHF_EN_OFS ( 7) /*!< FCNTHF_EN Bit Offset */ -#define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /*!< Enable start fault counter for HFXT */ -/* CS_CLKEN[ACLK_EN] Bits */ -#define CS_CLKEN_ACLK_EN_OFS ( 0) /*!< ACLK_EN Bit Offset */ -#define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /*!< ACLK system clock conditional request enable */ -/* CS_CLKEN[MCLK_EN] Bits */ -#define CS_CLKEN_MCLK_EN_OFS ( 1) /*!< MCLK_EN Bit Offset */ -#define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /*!< MCLK system clock conditional request enable */ -/* CS_CLKEN[HSMCLK_EN] Bits */ -#define CS_CLKEN_HSMCLK_EN_OFS ( 2) /*!< HSMCLK_EN Bit Offset */ -#define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /*!< HSMCLK system clock conditional request enable */ -/* CS_CLKEN[SMCLK_EN] Bits */ -#define CS_CLKEN_SMCLK_EN_OFS ( 3) /*!< SMCLK_EN Bit Offset */ -#define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /*!< SMCLK system clock conditional request enable */ -/* CS_CLKEN[VLO_EN] Bits */ -#define CS_CLKEN_VLO_EN_OFS ( 8) /*!< VLO_EN Bit Offset */ -#define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /*!< Turns on the VLO oscillator */ -/* CS_CLKEN[REFO_EN] Bits */ -#define CS_CLKEN_REFO_EN_OFS ( 9) /*!< REFO_EN Bit Offset */ -#define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /*!< Turns on the REFO oscillator */ -/* CS_CLKEN[MODOSC_EN] Bits */ -#define CS_CLKEN_MODOSC_EN_OFS (10) /*!< MODOSC_EN Bit Offset */ -#define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /*!< Turns on the MODOSC oscillator */ -/* CS_CLKEN[REFOFSEL] Bits */ -#define CS_CLKEN_REFOFSEL_OFS (15) /*!< REFOFSEL Bit Offset */ -#define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /*!< Selects REFO nominal frequency */ -/* CS_STAT[DCO_ON] Bits */ -#define CS_STAT_DCO_ON_OFS ( 0) /*!< DCO_ON Bit Offset */ -#define CS_STAT_DCO_ON ((uint32_t)0x00000001) /*!< DCO status */ -/* CS_STAT[DCOBIAS_ON] Bits */ -#define CS_STAT_DCOBIAS_ON_OFS ( 1) /*!< DCOBIAS_ON Bit Offset */ -#define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /*!< DCO bias status */ -/* CS_STAT[HFXT_ON] Bits */ -#define CS_STAT_HFXT_ON_OFS ( 2) /*!< HFXT_ON Bit Offset */ -#define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /*!< HFXT status */ -/* CS_STAT[MODOSC_ON] Bits */ -#define CS_STAT_MODOSC_ON_OFS ( 4) /*!< MODOSC_ON Bit Offset */ -#define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /*!< MODOSC status */ -/* CS_STAT[VLO_ON] Bits */ -#define CS_STAT_VLO_ON_OFS ( 5) /*!< VLO_ON Bit Offset */ -#define CS_STAT_VLO_ON ((uint32_t)0x00000020) /*!< VLO status */ -/* CS_STAT[LFXT_ON] Bits */ -#define CS_STAT_LFXT_ON_OFS ( 6) /*!< LFXT_ON Bit Offset */ -#define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /*!< LFXT status */ -/* CS_STAT[REFO_ON] Bits */ -#define CS_STAT_REFO_ON_OFS ( 7) /*!< REFO_ON Bit Offset */ -#define CS_STAT_REFO_ON ((uint32_t)0x00000080) /*!< REFO status */ -/* CS_STAT[ACLK_ON] Bits */ -#define CS_STAT_ACLK_ON_OFS (16) /*!< ACLK_ON Bit Offset */ -#define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /*!< ACLK system clock status */ -/* CS_STAT[MCLK_ON] Bits */ -#define CS_STAT_MCLK_ON_OFS (17) /*!< MCLK_ON Bit Offset */ -#define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /*!< MCLK system clock status */ -/* CS_STAT[HSMCLK_ON] Bits */ -#define CS_STAT_HSMCLK_ON_OFS (18) /*!< HSMCLK_ON Bit Offset */ -#define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /*!< HSMCLK system clock status */ -/* CS_STAT[SMCLK_ON] Bits */ -#define CS_STAT_SMCLK_ON_OFS (19) /*!< SMCLK_ON Bit Offset */ -#define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /*!< SMCLK system clock status */ -/* CS_STAT[MODCLK_ON] Bits */ -#define CS_STAT_MODCLK_ON_OFS (20) /*!< MODCLK_ON Bit Offset */ -#define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /*!< MODCLK system clock status */ -/* CS_STAT[VLOCLK_ON] Bits */ -#define CS_STAT_VLOCLK_ON_OFS (21) /*!< VLOCLK_ON Bit Offset */ -#define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /*!< VLOCLK system clock status */ -/* CS_STAT[LFXTCLK_ON] Bits */ -#define CS_STAT_LFXTCLK_ON_OFS (22) /*!< LFXTCLK_ON Bit Offset */ -#define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /*!< LFXTCLK system clock status */ -/* CS_STAT[REFOCLK_ON] Bits */ -#define CS_STAT_REFOCLK_ON_OFS (23) /*!< REFOCLK_ON Bit Offset */ -#define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /*!< REFOCLK system clock status */ -/* CS_STAT[ACLK_READY] Bits */ -#define CS_STAT_ACLK_READY_OFS (24) /*!< ACLK_READY Bit Offset */ -#define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /*!< ACLK Ready status */ -/* CS_STAT[MCLK_READY] Bits */ -#define CS_STAT_MCLK_READY_OFS (25) /*!< MCLK_READY Bit Offset */ -#define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /*!< MCLK Ready status */ -/* CS_STAT[HSMCLK_READY] Bits */ -#define CS_STAT_HSMCLK_READY_OFS (26) /*!< HSMCLK_READY Bit Offset */ -#define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /*!< HSMCLK Ready status */ -/* CS_STAT[SMCLK_READY] Bits */ -#define CS_STAT_SMCLK_READY_OFS (27) /*!< SMCLK_READY Bit Offset */ -#define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /*!< SMCLK Ready status */ -/* CS_STAT[BCLK_READY] Bits */ -#define CS_STAT_BCLK_READY_OFS (28) /*!< BCLK_READY Bit Offset */ -#define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /*!< BCLK Ready status */ -/* CS_IE[LFXTIE] Bits */ -#define CS_IE_LFXTIE_OFS ( 0) /*!< LFXTIE Bit Offset */ -#define CS_IE_LFXTIE ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag interrupt enable */ -/* CS_IE[HFXTIE] Bits */ -#define CS_IE_HFXTIE_OFS ( 1) /*!< HFXTIE Bit Offset */ -#define CS_IE_HFXTIE ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag interrupt enable */ -/* CS_IE[DCOR_OPNIE] Bits */ -#define CS_IE_DCOR_OPNIE_OFS ( 6) /*!< DCOR_OPNIE Bit Offset */ -#define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag interrupt enable. */ -/* CS_IE[FCNTLFIE] Bits */ -#define CS_IE_FCNTLFIE_OFS ( 8) /*!< FCNTLFIE Bit Offset */ -#define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /*!< Start fault counter interrupt enable LFXT */ -/* CS_IE[FCNTHFIE] Bits */ -#define CS_IE_FCNTHFIE_OFS ( 9) /*!< FCNTHFIE Bit Offset */ -#define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /*!< Start fault counter interrupt enable HFXT */ -/* CS_IFG[LFXTIFG] Bits */ -#define CS_IFG_LFXTIFG_OFS ( 0) /*!< LFXTIFG Bit Offset */ -#define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag */ -/* CS_IFG[HFXTIFG] Bits */ -#define CS_IFG_HFXTIFG_OFS ( 1) /*!< HFXTIFG Bit Offset */ -#define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag */ -/* CS_IFG[DCOR_SHTIFG] Bits */ -#define CS_IFG_DCOR_SHTIFG_OFS ( 5) /*!< DCOR_SHTIFG Bit Offset */ -#define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /*!< DCO external resistor short circuit fault flag. */ -/* CS_IFG[DCOR_OPNIFG] Bits */ -#define CS_IFG_DCOR_OPNIFG_OFS ( 6) /*!< DCOR_OPNIFG Bit Offset */ -#define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag. */ -/* CS_IFG[FCNTLFIFG] Bits */ -#define CS_IFG_FCNTLFIFG_OFS ( 8) /*!< FCNTLFIFG Bit Offset */ -#define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter interrupt flag LFXT */ -/* CS_IFG[FCNTHFIFG] Bits */ -#define CS_IFG_FCNTHFIFG_OFS ( 9) /*!< FCNTHFIFG Bit Offset */ -#define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter interrupt flag HFXT */ -/* CS_CLRIFG[CLR_LFXTIFG] Bits */ -#define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /*!< CLR_LFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /*!< Clear LFXT oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_HFXTIFG] Bits */ -#define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /*!< CLR_HFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /*!< Clear HFXT oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /*!< CLR_DCOR_OPNIFG Bit Offset */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Clear DCO external resistor open circuit fault interrupt flag. */ -/* CS_CLRIFG[CLR_FCNTLFIFG] Bits */ -#define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /*!< CLR_FCNTLFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter clear interrupt flag LFXT */ -/* CS_CLRIFG[CLR_FCNTHFIFG] Bits */ -#define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /*!< CLR_FCNTHFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter clear interrupt flag HFXT */ -/* CS_SETIFG[SET_LFXTIFG] Bits */ -#define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /*!< SET_LFXTIFG Bit Offset */ -#define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /*!< Set LFXT oscillator fault interrupt flag */ -/* CS_SETIFG[SET_HFXTIFG] Bits */ -#define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /*!< SET_HFXTIFG Bit Offset */ -#define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /*!< Set HFXT oscillator fault interrupt flag */ -/* CS_SETIFG[SET_DCOR_OPNIFG] Bits */ -#define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /*!< SET_DCOR_OPNIFG Bit Offset */ -#define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Set DCO external resistor open circuit fault interrupt flag. */ -/* CS_SETIFG[SET_FCNTHFIFG] Bits */ -#define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /*!< SET_FCNTHFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter set interrupt flag HFXT */ -/* CS_SETIFG[SET_FCNTLFIFG] Bits */ -#define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /*!< SET_FCNTLFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter set interrupt flag LFXT */ -/* CS_DCOERCAL0[DCO_TCCAL] Bits */ -#define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /*!< DCO_TCCAL Bit Offset */ -#define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /*!< DCO_TCCAL Bit Mask */ -/* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /*!< DCO_FCAL_RSEL04 Bit Offset */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /*!< DCO_FCAL_RSEL04 Bit Mask */ -/* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /*!< DCO_FCAL_RSEL5 Bit Offset */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /*!< DCO_FCAL_RSEL5 Bit Mask */ -/* Pre-defined bitfield values */ -#define CS_KEY_VAL ((uint32_t)0x0000695A) /*!< CS control key value */ - -/****************************************************************************** -* DIO Bits -******************************************************************************/ -/* DIO_IV[IV] Bits */ -#define DIO_PORT_IV_OFS ( 0) /*!< DIO Port IV Bit Offset */ -#define DIO_PORT_IV_MASK ((uint16_t)0x001F) /*!< DIO Port IV Bit Mask */ -#define DIO_PORT_IV0 ((uint16_t)0x0001) /*!< DIO Port IV Bit 0 */ -#define DIO_PORT_IV1 ((uint16_t)0x0002) /*!< DIO Port IV Bit 1 */ -#define DIO_PORT_IV2 ((uint16_t)0x0004) /*!< DIO Port IV Bit 2 */ -#define DIO_PORT_IV3 ((uint16_t)0x0008) /*!< DIO Port IV Bit 3 */ -#define DIO_PORT_IV4 ((uint16_t)0x0010) /*!< DIO Port IV Bit 4 */ -#define DIO_PORT_IV_0 ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV_2 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ - /* Priority: Highest */ -#define DIO_PORT_IV_4 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV_6 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV_8 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV_10 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV_12 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV_14 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV_16 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ - /* Priority: Lowest */ -#define DIO_PORT_IV__NONE ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ - /* Priority: Highest */ -#define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ - /* Priority: Lowest */ - - -/****************************************************************************** -* DMA Bits -******************************************************************************/ -/* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /*!< NUM_DMA_CHANNELS Bit Offset */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /*!< NUM_DMA_CHANNELS Bit Mask */ -/* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /*!< NUM_SRC_PER_CHANNEL Bit Offset */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /*!< NUM_SRC_PER_CHANNEL Bit Mask */ -/* DMA_SW_CHTRIG[CH0] Bits */ -#define DMA_SW_CHTRIG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /*!< Write 1, triggers DMA_CHANNEL0 */ -/* DMA_SW_CHTRIG[CH1] Bits */ -#define DMA_SW_CHTRIG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /*!< Write 1, triggers DMA_CHANNEL1 */ -/* DMA_SW_CHTRIG[CH2] Bits */ -#define DMA_SW_CHTRIG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /*!< Write 1, triggers DMA_CHANNEL2 */ -/* DMA_SW_CHTRIG[CH3] Bits */ -#define DMA_SW_CHTRIG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /*!< Write 1, triggers DMA_CHANNEL3 */ -/* DMA_SW_CHTRIG[CH4] Bits */ -#define DMA_SW_CHTRIG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /*!< Write 1, triggers DMA_CHANNEL4 */ -/* DMA_SW_CHTRIG[CH5] Bits */ -#define DMA_SW_CHTRIG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /*!< Write 1, triggers DMA_CHANNEL5 */ -/* DMA_SW_CHTRIG[CH6] Bits */ -#define DMA_SW_CHTRIG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /*!< Write 1, triggers DMA_CHANNEL6 */ -/* DMA_SW_CHTRIG[CH7] Bits */ -#define DMA_SW_CHTRIG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /*!< Write 1, triggers DMA_CHANNEL7 */ -/* DMA_SW_CHTRIG[CH8] Bits */ -#define DMA_SW_CHTRIG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /*!< Write 1, triggers DMA_CHANNEL8 */ -/* DMA_SW_CHTRIG[CH9] Bits */ -#define DMA_SW_CHTRIG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /*!< Write 1, triggers DMA_CHANNEL9 */ -/* DMA_SW_CHTRIG[CH10] Bits */ -#define DMA_SW_CHTRIG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /*!< Write 1, triggers DMA_CHANNEL10 */ -/* DMA_SW_CHTRIG[CH11] Bits */ -#define DMA_SW_CHTRIG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /*!< Write 1, triggers DMA_CHANNEL11 */ -/* DMA_SW_CHTRIG[CH12] Bits */ -#define DMA_SW_CHTRIG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /*!< Write 1, triggers DMA_CHANNEL12 */ -/* DMA_SW_CHTRIG[CH13] Bits */ -#define DMA_SW_CHTRIG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /*!< Write 1, triggers DMA_CHANNEL13 */ -/* DMA_SW_CHTRIG[CH14] Bits */ -#define DMA_SW_CHTRIG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /*!< Write 1, triggers DMA_CHANNEL14 */ -/* DMA_SW_CHTRIG[CH15] Bits */ -#define DMA_SW_CHTRIG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /*!< Write 1, triggers DMA_CHANNEL15 */ -/* DMA_SW_CHTRIG[CH16] Bits */ -#define DMA_SW_CHTRIG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /*!< Write 1, triggers DMA_CHANNEL16 */ -/* DMA_SW_CHTRIG[CH17] Bits */ -#define DMA_SW_CHTRIG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /*!< Write 1, triggers DMA_CHANNEL17 */ -/* DMA_SW_CHTRIG[CH18] Bits */ -#define DMA_SW_CHTRIG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /*!< Write 1, triggers DMA_CHANNEL18 */ -/* DMA_SW_CHTRIG[CH19] Bits */ -#define DMA_SW_CHTRIG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /*!< Write 1, triggers DMA_CHANNEL19 */ -/* DMA_SW_CHTRIG[CH20] Bits */ -#define DMA_SW_CHTRIG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /*!< Write 1, triggers DMA_CHANNEL20 */ -/* DMA_SW_CHTRIG[CH21] Bits */ -#define DMA_SW_CHTRIG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /*!< Write 1, triggers DMA_CHANNEL21 */ -/* DMA_SW_CHTRIG[CH22] Bits */ -#define DMA_SW_CHTRIG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /*!< Write 1, triggers DMA_CHANNEL22 */ -/* DMA_SW_CHTRIG[CH23] Bits */ -#define DMA_SW_CHTRIG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /*!< Write 1, triggers DMA_CHANNEL23 */ -/* DMA_SW_CHTRIG[CH24] Bits */ -#define DMA_SW_CHTRIG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /*!< Write 1, triggers DMA_CHANNEL24 */ -/* DMA_SW_CHTRIG[CH25] Bits */ -#define DMA_SW_CHTRIG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /*!< Write 1, triggers DMA_CHANNEL25 */ -/* DMA_SW_CHTRIG[CH26] Bits */ -#define DMA_SW_CHTRIG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /*!< Write 1, triggers DMA_CHANNEL26 */ -/* DMA_SW_CHTRIG[CH27] Bits */ -#define DMA_SW_CHTRIG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /*!< Write 1, triggers DMA_CHANNEL27 */ -/* DMA_SW_CHTRIG[CH28] Bits */ -#define DMA_SW_CHTRIG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /*!< Write 1, triggers DMA_CHANNEL28 */ -/* DMA_SW_CHTRIG[CH29] Bits */ -#define DMA_SW_CHTRIG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /*!< Write 1, triggers DMA_CHANNEL29 */ -/* DMA_SW_CHTRIG[CH30] Bits */ -#define DMA_SW_CHTRIG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /*!< Write 1, triggers DMA_CHANNEL30 */ -/* DMA_SW_CHTRIG[CH31] Bits */ -#define DMA_SW_CHTRIG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /*!< Write 1, triggers DMA_CHANNEL31 */ -/* DMA_CHN_SRCCFG[DMA_SRC] Bits */ -#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /*!< DMA_SRC Bit Offset */ -#define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /*!< DMA_SRC Bit Mask */ -/* DMA_INT1_SRCCFG[INT_SRC] Bits */ -#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT1_SRCCFG[EN] Bits */ -#define DMA_INT1_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT1 mapping */ -/* DMA_INT2_SRCCFG[INT_SRC] Bits */ -#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT2_SRCCFG[EN] Bits */ -#define DMA_INT2_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT2 mapping */ -/* DMA_INT3_SRCCFG[INT_SRC] Bits */ -#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT3_SRCCFG[EN] Bits */ -#define DMA_INT3_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT3 mapping */ -/* DMA_INT0_SRCFLG[CH0] Bits */ -#define DMA_INT0_SRCFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /*!< Channel 0 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH1] Bits */ -#define DMA_INT0_SRCFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /*!< Channel 1 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH2] Bits */ -#define DMA_INT0_SRCFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /*!< Channel 2 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH3] Bits */ -#define DMA_INT0_SRCFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /*!< Channel 3 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH4] Bits */ -#define DMA_INT0_SRCFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /*!< Channel 4 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH5] Bits */ -#define DMA_INT0_SRCFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /*!< Channel 5 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH6] Bits */ -#define DMA_INT0_SRCFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /*!< Channel 6 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH7] Bits */ -#define DMA_INT0_SRCFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /*!< Channel 7 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH8] Bits */ -#define DMA_INT0_SRCFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /*!< Channel 8 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH9] Bits */ -#define DMA_INT0_SRCFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /*!< Channel 9 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH10] Bits */ -#define DMA_INT0_SRCFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /*!< Channel 10 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH11] Bits */ -#define DMA_INT0_SRCFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /*!< Channel 11 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH12] Bits */ -#define DMA_INT0_SRCFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /*!< Channel 12 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH13] Bits */ -#define DMA_INT0_SRCFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /*!< Channel 13 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH14] Bits */ -#define DMA_INT0_SRCFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /*!< Channel 14 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH15] Bits */ -#define DMA_INT0_SRCFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /*!< Channel 15 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH16] Bits */ -#define DMA_INT0_SRCFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /*!< Channel 16 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH17] Bits */ -#define DMA_INT0_SRCFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /*!< Channel 17 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH18] Bits */ -#define DMA_INT0_SRCFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /*!< Channel 18 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH19] Bits */ -#define DMA_INT0_SRCFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /*!< Channel 19 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH20] Bits */ -#define DMA_INT0_SRCFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /*!< Channel 20 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH21] Bits */ -#define DMA_INT0_SRCFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /*!< Channel 21 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH22] Bits */ -#define DMA_INT0_SRCFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /*!< Channel 22 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH23] Bits */ -#define DMA_INT0_SRCFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /*!< Channel 23 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH24] Bits */ -#define DMA_INT0_SRCFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /*!< Channel 24 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH25] Bits */ -#define DMA_INT0_SRCFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /*!< Channel 25 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH26] Bits */ -#define DMA_INT0_SRCFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /*!< Channel 26 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH27] Bits */ -#define DMA_INT0_SRCFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /*!< Channel 27 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH28] Bits */ -#define DMA_INT0_SRCFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /*!< Channel 28 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH29] Bits */ -#define DMA_INT0_SRCFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /*!< Channel 29 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH30] Bits */ -#define DMA_INT0_SRCFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /*!< Channel 30 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH31] Bits */ -#define DMA_INT0_SRCFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /*!< Channel 31 was the source of DMA_INT0 */ -/* DMA_INT0_CLRFLG[CH0] Bits */ -#define DMA_INT0_CLRFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH1] Bits */ -#define DMA_INT0_CLRFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH2] Bits */ -#define DMA_INT0_CLRFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH3] Bits */ -#define DMA_INT0_CLRFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH4] Bits */ -#define DMA_INT0_CLRFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH5] Bits */ -#define DMA_INT0_CLRFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH6] Bits */ -#define DMA_INT0_CLRFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH7] Bits */ -#define DMA_INT0_CLRFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH8] Bits */ -#define DMA_INT0_CLRFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH9] Bits */ -#define DMA_INT0_CLRFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH10] Bits */ -#define DMA_INT0_CLRFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH11] Bits */ -#define DMA_INT0_CLRFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH12] Bits */ -#define DMA_INT0_CLRFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH13] Bits */ -#define DMA_INT0_CLRFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH14] Bits */ -#define DMA_INT0_CLRFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH15] Bits */ -#define DMA_INT0_CLRFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH16] Bits */ -#define DMA_INT0_CLRFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH17] Bits */ -#define DMA_INT0_CLRFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH18] Bits */ -#define DMA_INT0_CLRFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH19] Bits */ -#define DMA_INT0_CLRFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH20] Bits */ -#define DMA_INT0_CLRFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH21] Bits */ -#define DMA_INT0_CLRFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH22] Bits */ -#define DMA_INT0_CLRFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH23] Bits */ -#define DMA_INT0_CLRFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH24] Bits */ -#define DMA_INT0_CLRFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH25] Bits */ -#define DMA_INT0_CLRFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH26] Bits */ -#define DMA_INT0_CLRFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH27] Bits */ -#define DMA_INT0_CLRFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH28] Bits */ -#define DMA_INT0_CLRFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH29] Bits */ -#define DMA_INT0_CLRFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH30] Bits */ -#define DMA_INT0_CLRFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH31] Bits */ -#define DMA_INT0_CLRFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_STAT[MASTEN] Bits */ -#define DMA_STAT_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_STAT_MASTEN ((uint32_t)0x00000001) -/* DMA_STAT[STATE] Bits */ -#define DMA_STAT_STATE_OFS ( 4) /*!< STATE Bit Offset */ -#define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /*!< STATE Bit Mask */ -#define DMA_STAT_STATE0 ((uint32_t)0x00000010) /*!< STATE Bit 0 */ -#define DMA_STAT_STATE1 ((uint32_t)0x00000020) /*!< STATE Bit 1 */ -#define DMA_STAT_STATE2 ((uint32_t)0x00000040) /*!< STATE Bit 2 */ -#define DMA_STAT_STATE3 ((uint32_t)0x00000080) /*!< STATE Bit 3 */ -#define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /*!< idle */ -#define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /*!< reading channel controller data */ -#define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /*!< reading source data end pointer */ -#define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /*!< reading destination data end pointer */ -#define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /*!< reading source data */ -#define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /*!< writing destination data */ -#define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /*!< waiting for DMA request to clear */ -#define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /*!< writing channel controller data */ -#define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /*!< stalled */ -#define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /*!< done */ -#define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /*!< peripheral scatter-gather transition */ -#define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /*!< Reserved */ -#define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /*!< Reserved */ -#define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /*!< Reserved */ -#define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /*!< Reserved */ -#define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /*!< Reserved */ -/* DMA_STAT[DMACHANS] Bits */ -#define DMA_STAT_DMACHANS_OFS (16) /*!< DMACHANS Bit Offset */ -#define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /*!< DMACHANS Bit Mask */ -#define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /*!< DMACHANS Bit 0 */ -#define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /*!< DMACHANS Bit 1 */ -#define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /*!< DMACHANS Bit 2 */ -#define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /*!< DMACHANS Bit 3 */ -#define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /*!< DMACHANS Bit 4 */ -#define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /*!< Controller configured to use 1 DMA channel */ -#define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /*!< Controller configured to use 2 DMA channels */ -#define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /*!< Controller configured to use 31 DMA channels */ -#define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /*!< Controller configured to use 32 DMA channels */ -/* DMA_STAT[TESTSTAT] Bits */ -#define DMA_STAT_TESTSTAT_OFS (28) /*!< TESTSTAT Bit Offset */ -#define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /*!< TESTSTAT Bit Mask */ -#define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /*!< TESTSTAT Bit 0 */ -#define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /*!< TESTSTAT Bit 1 */ -#define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /*!< TESTSTAT Bit 2 */ -#define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /*!< TESTSTAT Bit 3 */ -#define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /*!< Controller does not include the integration test logic */ -#define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /*!< Controller includes the integration test logic */ -/* DMA_CFG[MASTEN] Bits */ -#define DMA_CFG_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_CFG_MASTEN ((uint32_t)0x00000001) -/* DMA_CFG[CHPROTCTRL] Bits */ -#define DMA_CFG_CHPROTCTRL_OFS ( 5) /*!< CHPROTCTRL Bit Offset */ -#define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /*!< CHPROTCTRL Bit Mask */ -/* DMA_CTLBASE[ADDR] Bits */ -#define DMA_CTLBASE_ADDR_OFS ( 5) /*!< ADDR Bit Offset */ -#define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /*!< ADDR Bit Mask */ -/* DMA_ERRCLR[ERRCLR] Bits */ -#define DMA_ERRCLR_ERRCLR_OFS ( 0) /*!< ERRCLR Bit Offset */ -#define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) -/* DMA channel definitions and memory structure alignment */ -#define __MCU_NUM_DMA_CHANNELS__ 8 -#define DMA_CHANNEL_CONTROL_STRUCT_SIZE 0x10 -#define DMA_CONTROL_MEMORY_ALIGNMENT (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE) - -/* UDMA_STAT Control Bits */ -#define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /*!< Available uDMA Channels Minus 1 */ -#define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /*!< Control State Machine Status */ -#define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /*!< Idle */ -#define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /*!< Reading channel controller data */ -#define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /*!< Reading source end pointer */ -#define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /*!< Reading destination end pointer */ -#define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /*!< Reading source data */ -#define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /*!< Writing destination data */ -#define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /*!< Waiting for uDMA request to clear */ -#define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /*!< Writing channel controller data */ -#define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /*!< Stalled */ -#define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /*!< Done */ -#define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /*!< Undefined */ -#define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /*!< Master Enable Status */ -#define UDMA_STAT_DMACHANS_S (16) - -/* UDMA_CFG Control Bits */ -#define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /*!< Controller Master Enable */ - -/* UDMA_CTLBASE Control Bits */ -#define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /*!< Channel Control Base Address */ -#define UDMA_CTLBASE_ADDR_S (10) - -/* UDMA_ALTBASE Control Bits */ -#define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Alternate Channel Address Pointer */ -#define UDMA_ALTBASE_ADDR_S ( 0) - -/* UDMA_WAITSTAT Control Bits */ -#define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Wait Status */ - -/* UDMA_SWREQ Control Bits */ -#define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Software Request */ - -/* UDMA_USEBURSTSET Control Bits */ -#define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Set */ - -/* UDMA_USEBURSTCLR Control Bits */ -#define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Clear */ - -/* UDMA_REQMASKSET Control Bits */ -#define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Set */ - -/* UDMA_REQMASKCLR Control Bits */ -#define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Clear */ - -/* UDMA_ENASET Control Bits */ -#define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Enable Set */ - -/* UDMA_ENACLR Control Bits */ -#define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Clear Channel [n] Enable Clear */ - -/* UDMA_ALTSET Control Bits */ -#define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Set */ - -/* UDMA_ALTCLR Control Bits */ -#define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Clear */ - -/* UDMA_PRIOSET Control Bits */ -#define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Set */ - -/* UDMA_PRIOCLR Control Bits */ -#define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Clear */ - -/* UDMA_ERRCLR Control Bits */ -#define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /*!< uDMA Bus Error Status */ - -/* UDMA_CHASGN Control Bits */ -#define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Assignment Select */ -#define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /*!< Use the primary channel assignment */ -#define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /*!< Use the secondary channel assignment */ - -/* Micro Direct Memory Access (uDMA) offsets */ -#define UDMA_O_SRCENDP ((uint32_t)0x00000000) /*!< DMA Channel Source Address End Pointer */ -#define UDMA_O_DSTENDP ((uint32_t)0x00000004) /*!< DMA Channel Destination Address End Pointer */ -#define UDMA_O_CHCTL ((uint32_t)0x00000008) /*!< DMA Channel Control Word */ - -/* UDMA_O_SRCENDP Control Bits */ -#define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Source Address End Pointer */ -#define UDMA_SRCENDP_ADDR_S ( 0) - -/* UDMA_O_DSTENDP Control Bits */ -#define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Destination Address End Pointer */ -#define UDMA_DSTENDP_ADDR_S ( 0) - -/* UDMA_O_CHCTL Control Bits */ -#define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /*!< Destination Address Increment */ -#define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /*!< Word */ -#define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /*!< No increment */ -#define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /*!< Destination Data Size */ -#define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /*!< Source Address Increment */ -#define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /*!< No increment */ -#define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /*!< Source Data Size */ -#define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /*!< Word */ -#define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /*!< Arbitration Size */ -#define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /*!< 1 Transfer */ -#define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /*!< 2 Transfers */ -#define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /*!< 4 Transfers */ -#define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /*!< 8 Transfers */ -#define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /*!< 16 Transfers */ -#define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /*!< 32 Transfers */ -#define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /*!< 64 Transfers */ -#define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /*!< 128 Transfers */ -#define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /*!< 256 Transfers */ -#define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /*!< 512 Transfers */ -#define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /*!< 1024 Transfers */ -#define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /*!< Transfer Size (minus 1) */ -#define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /*!< Next Useburst */ -#define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /*!< uDMA Transfer Mode */ -#define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /*!< Stop */ -#define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /*!< Basic */ -#define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /*!< Auto-Request */ -#define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /*!< Ping-Pong */ -#define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /*!< Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /*!< Alternate Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /*!< Peripheral Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /*!< Alternate Peripheral Scatter-Gather */ - -#define UDMA_CHCTL_XFERSIZE_S ( 4) - - -/****************************************************************************** -* DWT Bits -******************************************************************************/ - - -/****************************************************************************** -* EUSCI_A Bits -******************************************************************************/ -/* EUSCI_A_CTLW0[SWRST] Bits */ -#define EUSCI_A_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -/* EUSCI_A_CTLW0[TXBRK] Bits */ -#define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /*!< UCTXBRK Bit Offset */ -#define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /*!< Transmit break */ -/* EUSCI_A_CTLW0[TXADDR] Bits */ -#define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /*!< UCTXADDR Bit Offset */ -#define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /*!< Transmit address */ -/* EUSCI_A_CTLW0[DORM] Bits */ -#define EUSCI_A_CTLW0_DORM_OFS ( 3) /*!< UCDORM Bit Offset */ -#define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /*!< Dormant */ -/* EUSCI_A_CTLW0[BRKIE] Bits */ -#define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /*!< UCBRKIE Bit Offset */ -#define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /*!< Receive break character interrupt enable */ -/* EUSCI_A_CTLW0[RXEIE] Bits */ -#define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /*!< UCRXEIE Bit Offset */ -#define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /*!< Receive erroneous-character interrupt enable */ -/* EUSCI_A_CTLW0[SSEL] Bits */ -#define EUSCI_A_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -/* EUSCI_A_CTLW0[SYNC] Bits */ -#define EUSCI_A_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -/* EUSCI_A_CTLW0[MODE] Bits */ -#define EUSCI_A_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< UART mode */ -#define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< Idle-line multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< Address-bit multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< UART mode with automatic baud-rate detection */ -/* EUSCI_A_CTLW0[SPB] Bits */ -#define EUSCI_A_CTLW0_SPB_OFS (11) /*!< UCSPB Bit Offset */ -#define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /*!< Stop bit select */ -/* EUSCI_A_CTLW0[SEVENBIT] Bits */ -#define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -/* EUSCI_A_CTLW0[MSB] Bits */ -#define EUSCI_A_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -/* EUSCI_A_CTLW0[PAR] Bits */ -#define EUSCI_A_CTLW0_PAR_OFS (14) /*!< UCPAR Bit Offset */ -#define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /*!< Parity select */ -/* EUSCI_A_CTLW0[PEN] Bits */ -#define EUSCI_A_CTLW0_PEN_OFS (15) /*!< UCPEN Bit Offset */ -#define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /*!< Parity enable */ -/* EUSCI_A_CTLW0[STEM] Bits */ -#define EUSCI_A_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -/* EUSCI_A_CTLW0[MST] Bits */ -#define EUSCI_A_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -/* EUSCI_A_CTLW0[CKPL] Bits */ -#define EUSCI_A_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -/* EUSCI_A_CTLW0[CKPH] Bits */ -#define EUSCI_A_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -/* EUSCI_A_CTLW1[GLIT] Bits */ -#define EUSCI_A_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< Approximately 2 ns (equivalent of 1 delay element) */ -#define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< Approximately 50 ns */ -#define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< Approximately 100 ns */ -#define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< Approximately 200 ns */ -/* EUSCI_A_MCTLW[OS16] Bits */ -#define EUSCI_A_MCTLW_OS16_OFS ( 0) /*!< UCOS16 Bit Offset */ -#define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /*!< Oversampling mode enabled */ -/* EUSCI_A_MCTLW[BRF] Bits */ -#define EUSCI_A_MCTLW_BRF_OFS ( 4) /*!< UCBRF Bit Offset */ -#define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /*!< UCBRF Bit Mask */ -/* EUSCI_A_MCTLW[BRS] Bits */ -#define EUSCI_A_MCTLW_BRS_OFS ( 8) /*!< UCBRS Bit Offset */ -#define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /*!< UCBRS Bit Mask */ -/* EUSCI_A_STATW[BUSY] Bits */ -#define EUSCI_A_STATW_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -/* EUSCI_A_STATW[ADDR_IDLE] Bits */ -#define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /*!< UCADDR_UCIDLE Bit Offset */ -#define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /*!< Address received / Idle line detected */ -/* EUSCI_A_STATW[RXERR] Bits */ -#define EUSCI_A_STATW_RXERR_OFS ( 2) /*!< UCRXERR Bit Offset */ -#define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /*!< Receive error flag */ -/* EUSCI_A_STATW[BRK] Bits */ -#define EUSCI_A_STATW_BRK_OFS ( 3) /*!< UCBRK Bit Offset */ -#define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /*!< Break detect flag */ -/* EUSCI_A_STATW[PE] Bits */ -#define EUSCI_A_STATW_PE_OFS ( 4) /*!< UCPE Bit Offset */ -#define EUSCI_A_STATW_PE ((uint16_t)0x0010) -/* EUSCI_A_STATW[OE] Bits */ -#define EUSCI_A_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_A_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -/* EUSCI_A_STATW[FE] Bits */ -#define EUSCI_A_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_A_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -/* EUSCI_A_STATW[LISTEN] Bits */ -#define EUSCI_A_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -/* EUSCI_A_STATW[SPI_BUSY] Bits */ -#define EUSCI_A_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -/* EUSCI_A_RXBUF[RXBUF] Bits */ -#define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -/* EUSCI_A_TXBUF[TXBUF] Bits */ -#define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -/* EUSCI_A_ABCTL[ABDEN] Bits */ -#define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /*!< UCABDEN Bit Offset */ -#define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /*!< Automatic baud-rate detect enable */ -/* EUSCI_A_ABCTL[BTOE] Bits */ -#define EUSCI_A_ABCTL_BTOE_OFS ( 2) /*!< UCBTOE Bit Offset */ -#define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /*!< Break time out error */ -/* EUSCI_A_ABCTL[STOE] Bits */ -#define EUSCI_A_ABCTL_STOE_OFS ( 3) /*!< UCSTOE Bit Offset */ -#define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /*!< Synch field time out error */ -/* EUSCI_A_ABCTL[DELIM] Bits */ -#define EUSCI_A_ABCTL_DELIM_OFS ( 4) /*!< UCDELIM Bit Offset */ -#define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /*!< UCDELIM Bit Mask */ -#define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /*!< DELIM Bit 0 */ -#define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /*!< DELIM Bit 1 */ -#define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /*!< 1 bit time */ -#define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /*!< 2 bit times */ -#define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /*!< 3 bit times */ -#define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /*!< 4 bit times */ -/* EUSCI_A_IRCTL[IREN] Bits */ -#define EUSCI_A_IRCTL_IREN_OFS ( 0) /*!< UCIREN Bit Offset */ -#define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /*!< IrDA encoder/decoder enable */ -/* EUSCI_A_IRCTL[IRTXCLK] Bits */ -#define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /*!< UCIRTXCLK Bit Offset */ -#define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /*!< IrDA transmit pulse clock select */ -/* EUSCI_A_IRCTL[IRTXPL] Bits */ -#define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /*!< UCIRTXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /*!< UCIRTXPL Bit Mask */ -/* EUSCI_A_IRCTL[IRRXFE] Bits */ -#define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /*!< UCIRRXFE Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /*!< IrDA receive filter enabled */ -/* EUSCI_A_IRCTL[IRRXPL] Bits */ -#define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /*!< UCIRRXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /*!< IrDA receive input UCAxRXD polarity */ -/* EUSCI_A_IRCTL[IRRXFL] Bits */ -#define EUSCI_A_IRCTL_IRRXFL_OFS (10) /*!< UCIRRXFL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /*!< UCIRRXFL Bit Mask */ -/* EUSCI_A_IE[RXIE] Bits */ -#define EUSCI_A_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -/* EUSCI_A_IE[TXIE] Bits */ -#define EUSCI_A_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -/* EUSCI_A_IE[STTIE] Bits */ -#define EUSCI_A_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /*!< Start bit interrupt enable */ -/* EUSCI_A_IE[TXCPTIE] Bits */ -#define EUSCI_A_IE_TXCPTIE_OFS ( 3) /*!< UCTXCPTIE Bit Offset */ -#define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /*!< Transmit complete interrupt enable */ -/* EUSCI_A_IFG[RXIFG] Bits */ -#define EUSCI_A_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -/* EUSCI_A_IFG[TXIFG] Bits */ -#define EUSCI_A_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -/* EUSCI_A_IFG[STTIFG] Bits */ -#define EUSCI_A_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /*!< Start bit interrupt flag */ -/* EUSCI_A_IFG[TXCPTIFG] Bits */ -#define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /*!< UCTXCPTIFG Bit Offset */ -#define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /*!< Transmit ready interrupt enable */ -/* legacy definitions for backward compatibility to version 2100 */ -#define EUSCI_A__RXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_A__RXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_A__TXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_A__TXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ - - -/****************************************************************************** -* EUSCI_B Bits -******************************************************************************/ -/* EUSCI_B_CTLW0[SWRST] Bits */ -#define EUSCI_B_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -/* EUSCI_B_CTLW0[TXSTT] Bits */ -#define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /*!< UCTXSTT Bit Offset */ -#define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /*!< Transmit START condition in master mode */ -/* EUSCI_B_CTLW0[TXSTP] Bits */ -#define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /*!< UCTXSTP Bit Offset */ -#define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /*!< Transmit STOP condition in master mode */ -/* EUSCI_B_CTLW0[TXNACK] Bits */ -#define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /*!< UCTXNACK Bit Offset */ -#define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /*!< Transmit a NACK */ -/* EUSCI_B_CTLW0[TR] Bits */ -#define EUSCI_B_CTLW0_TR_OFS ( 4) /*!< UCTR Bit Offset */ -#define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /*!< Transmitter/receiver */ -/* EUSCI_B_CTLW0[TXACK] Bits */ -#define EUSCI_B_CTLW0_TXACK_OFS ( 5) /*!< UCTXACK Bit Offset */ -#define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /*!< Transmit ACK condition in slave mode */ -/* EUSCI_B_CTLW0[SSEL] Bits */ -#define EUSCI_B_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_B_CTLW0_UCSSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ -#define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -/* EUSCI_B_CTLW0[SYNC] Bits */ -#define EUSCI_B_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -/* EUSCI_B_CTLW0[MODE] Bits */ -#define EUSCI_B_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< 3-pin SPI */ -#define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< 4-pin SPI (master or slave enabled if STE = 1) */ -#define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< 4-pin SPI (master or slave enabled if STE = 0) */ -#define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< I2C mode */ -/* EUSCI_B_CTLW0[MST] Bits */ -#define EUSCI_B_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -/* EUSCI_B_CTLW0[MM] Bits */ -#define EUSCI_B_CTLW0_MM_OFS (13) /*!< UCMM Bit Offset */ -#define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /*!< Multi-master environment select */ -/* EUSCI_B_CTLW0[SLA10] Bits */ -#define EUSCI_B_CTLW0_SLA10_OFS (14) /*!< UCSLA10 Bit Offset */ -#define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /*!< Slave addressing mode select */ -/* EUSCI_B_CTLW0[A10] Bits */ -#define EUSCI_B_CTLW0_A10_OFS (15) /*!< UCA10 Bit Offset */ -#define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /*!< Own addressing mode select */ -/* EUSCI_B_CTLW0[STEM] Bits */ -#define EUSCI_B_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -/* EUSCI_B_CTLW0[SEVENBIT] Bits */ -#define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -/* EUSCI_B_CTLW0[MSB] Bits */ -#define EUSCI_B_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -/* EUSCI_B_CTLW0[CKPL] Bits */ -#define EUSCI_B_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -/* EUSCI_B_CTLW0[CKPH] Bits */ -#define EUSCI_B_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -/* EUSCI_B_CTLW1[GLIT] Bits */ -#define EUSCI_B_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< 50 ns */ -#define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< 25 ns */ -#define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< 12.5 ns */ -#define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< 6.25 ns */ -/* EUSCI_B_CTLW1[ASTP] Bits */ -#define EUSCI_B_CTLW1_ASTP_OFS ( 2) /*!< UCASTP Bit Offset */ -#define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /*!< UCASTP Bit Mask */ -#define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /*!< ASTP Bit 0 */ -#define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /*!< ASTP Bit 1 */ -#define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /*!< No automatic STOP generation. The STOP condition is generated after the user */ - /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ -#define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ - /* UCBxTBCNT */ -#define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /*!< A STOP condition is generated automatically after the byte counter value */ - /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ - /* threshold */ -/* EUSCI_B_CTLW1[SWACK] Bits */ -#define EUSCI_B_CTLW1_SWACK_OFS ( 4) /*!< UCSWACK Bit Offset */ -#define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /*!< SW or HW ACK control */ -/* EUSCI_B_CTLW1[STPNACK] Bits */ -#define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /*!< UCSTPNACK Bit Offset */ -#define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /*!< ACK all master bytes */ -/* EUSCI_B_CTLW1[CLTO] Bits */ -#define EUSCI_B_CTLW1_CLTO_OFS ( 6) /*!< UCCLTO Bit Offset */ -#define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /*!< UCCLTO Bit Mask */ -#define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /*!< CLTO Bit 0 */ -#define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /*!< CLTO Bit 1 */ -#define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /*!< Disable clock low timeout counter */ -#define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ -#define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ -#define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ -/* EUSCI_B_CTLW1[ETXINT] Bits */ -#define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /*!< UCETXINT Bit Offset */ -#define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /*!< Early UCTXIFG0 */ -/* EUSCI_B_STATW[BBUSY] Bits */ -#define EUSCI_B_STATW_BBUSY_OFS ( 4) /*!< UCBBUSY Bit Offset */ -#define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /*!< Bus busy */ -/* EUSCI_B_STATW[GC] Bits */ -#define EUSCI_B_STATW_GC_OFS ( 5) /*!< UCGC Bit Offset */ -#define EUSCI_B_STATW_GC ((uint16_t)0x0020) /*!< General call address received */ -/* EUSCI_B_STATW[SCLLOW] Bits */ -#define EUSCI_B_STATW_SCLLOW_OFS ( 6) /*!< UCSCLLOW Bit Offset */ -#define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /*!< SCL low */ -/* EUSCI_B_STATW[BCNT] Bits */ -#define EUSCI_B_STATW_BCNT_OFS ( 8) /*!< UCBCNT Bit Offset */ -#define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /*!< UCBCNT Bit Mask */ -/* EUSCI_B_STATW[SPI_BUSY] Bits */ -#define EUSCI_B_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_B_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_B busy */ -/* EUSCI_B_STATW[OE] Bits */ -#define EUSCI_B_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_B_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -/* EUSCI_B_STATW[FE] Bits */ -#define EUSCI_B_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_B_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -/* EUSCI_B_STATW[LISTEN] Bits */ -#define EUSCI_B_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -/* EUSCI_B_TBCNT[TBCNT] Bits */ -#define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /*!< UCTBCNT Bit Offset */ -#define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /*!< UCTBCNT Bit Mask */ -/* EUSCI_B_RXBUF[RXBUF] Bits */ -#define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -/* EUSCI_B_TXBUF[TXBUF] Bits */ -#define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -/* EUSCI_B_I2COA0[I2COA0] Bits */ -#define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /*!< I2COA0 Bit Offset */ -#define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /*!< I2COA0 Bit Mask */ -/* EUSCI_B_I2COA0[OAEN] Bits */ -#define EUSCI_B_I2COA0_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA0[GCEN] Bits */ -#define EUSCI_B_I2COA0_GCEN_OFS (15) /*!< UCGCEN Bit Offset */ -#define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /*!< General call response enable */ -/* EUSCI_B_I2COA1[I2COA1] Bits */ -#define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /*!< I2COA1 Bit Offset */ -#define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /*!< I2COA1 Bit Mask */ -/* EUSCI_B_I2COA1[OAEN] Bits */ -#define EUSCI_B_I2COA1_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA2[I2COA2] Bits */ -#define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /*!< I2COA2 Bit Offset */ -#define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /*!< I2COA2 Bit Mask */ -/* EUSCI_B_I2COA2[OAEN] Bits */ -#define EUSCI_B_I2COA2_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA3[I2COA3] Bits */ -#define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /*!< I2COA3 Bit Offset */ -#define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /*!< I2COA3 Bit Mask */ -/* EUSCI_B_I2COA3[OAEN] Bits */ -#define EUSCI_B_I2COA3_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_ADDRX[ADDRX] Bits */ -#define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /*!< ADDRX Bit Offset */ -#define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /*!< ADDRX Bit Mask */ -#define EUSCI_B_ADDRX_ADDRX0 ((uint16_t)0x0001) /*!< ADDRX Bit 0 */ -#define EUSCI_B_ADDRX_ADDRX1 ((uint16_t)0x0002) /*!< ADDRX Bit 1 */ -#define EUSCI_B_ADDRX_ADDRX2 ((uint16_t)0x0004) /*!< ADDRX Bit 2 */ -#define EUSCI_B_ADDRX_ADDRX3 ((uint16_t)0x0008) /*!< ADDRX Bit 3 */ -#define EUSCI_B_ADDRX_ADDRX4 ((uint16_t)0x0010) /*!< ADDRX Bit 4 */ -#define EUSCI_B_ADDRX_ADDRX5 ((uint16_t)0x0020) /*!< ADDRX Bit 5 */ -#define EUSCI_B_ADDRX_ADDRX6 ((uint16_t)0x0040) /*!< ADDRX Bit 6 */ -#define EUSCI_B_ADDRX_ADDRX7 ((uint16_t)0x0080) /*!< ADDRX Bit 7 */ -#define EUSCI_B_ADDRX_ADDRX8 ((uint16_t)0x0100) /*!< ADDRX Bit 8 */ -#define EUSCI_B_ADDRX_ADDRX9 ((uint16_t)0x0200) /*!< ADDRX Bit 9 */ -/* EUSCI_B_ADDMASK[ADDMASK] Bits */ -#define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /*!< ADDMASK Bit Offset */ -#define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /*!< ADDMASK Bit Mask */ -/* EUSCI_B_I2CSA[I2CSA] Bits */ -#define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /*!< I2CSA Bit Offset */ -#define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /*!< I2CSA Bit Mask */ -/* EUSCI_B_IE[RXIE0] Bits */ -#define EUSCI_B_IE_RXIE0_OFS ( 0) /*!< UCRXIE0 Bit Offset */ -#define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /*!< Receive interrupt enable 0 */ -/* EUSCI_B_IE[TXIE0] Bits */ -#define EUSCI_B_IE_TXIE0_OFS ( 1) /*!< UCTXIE0 Bit Offset */ -#define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /*!< Transmit interrupt enable 0 */ -/* EUSCI_B_IE[STTIE] Bits */ -#define EUSCI_B_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /*!< START condition interrupt enable */ -/* EUSCI_B_IE[STPIE] Bits */ -#define EUSCI_B_IE_STPIE_OFS ( 3) /*!< UCSTPIE Bit Offset */ -#define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /*!< STOP condition interrupt enable */ -/* EUSCI_B_IE[ALIE] Bits */ -#define EUSCI_B_IE_ALIE_OFS ( 4) /*!< UCALIE Bit Offset */ -#define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /*!< Arbitration lost interrupt enable */ -/* EUSCI_B_IE[NACKIE] Bits */ -#define EUSCI_B_IE_NACKIE_OFS ( 5) /*!< UCNACKIE Bit Offset */ -#define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /*!< Not-acknowledge interrupt enable */ -/* EUSCI_B_IE[BCNTIE] Bits */ -#define EUSCI_B_IE_BCNTIE_OFS ( 6) /*!< UCBCNTIE Bit Offset */ -#define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /*!< Byte counter interrupt enable */ -/* EUSCI_B_IE[CLTOIE] Bits */ -#define EUSCI_B_IE_CLTOIE_OFS ( 7) /*!< UCCLTOIE Bit Offset */ -#define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /*!< Clock low timeout interrupt enable */ -/* EUSCI_B_IE[RXIE1] Bits */ -#define EUSCI_B_IE_RXIE1_OFS ( 8) /*!< UCRXIE1 Bit Offset */ -#define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /*!< Receive interrupt enable 1 */ -/* EUSCI_B_IE[TXIE1] Bits */ -#define EUSCI_B_IE_TXIE1_OFS ( 9) /*!< UCTXIE1 Bit Offset */ -#define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /*!< Transmit interrupt enable 1 */ -/* EUSCI_B_IE[RXIE2] Bits */ -#define EUSCI_B_IE_RXIE2_OFS (10) /*!< UCRXIE2 Bit Offset */ -#define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /*!< Receive interrupt enable 2 */ -/* EUSCI_B_IE[TXIE2] Bits */ -#define EUSCI_B_IE_TXIE2_OFS (11) /*!< UCTXIE2 Bit Offset */ -#define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /*!< Transmit interrupt enable 2 */ -/* EUSCI_B_IE[RXIE3] Bits */ -#define EUSCI_B_IE_RXIE3_OFS (12) /*!< UCRXIE3 Bit Offset */ -#define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /*!< Receive interrupt enable 3 */ -/* EUSCI_B_IE[TXIE3] Bits */ -#define EUSCI_B_IE_TXIE3_OFS (13) /*!< UCTXIE3 Bit Offset */ -#define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /*!< Transmit interrupt enable 3 */ -/* EUSCI_B_IE[BIT9IE] Bits */ -#define EUSCI_B_IE_BIT9IE_OFS (14) /*!< UCBIT9IE Bit Offset */ -#define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /*!< Bit position 9 interrupt enable */ -/* EUSCI_B_IE[RXIE] Bits */ -#define EUSCI_B_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_B_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -/* EUSCI_B_IE[TXIE] Bits */ -#define EUSCI_B_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_B_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -/* EUSCI_B_IFG[RXIFG0] Bits */ -#define EUSCI_B_IFG_RXIFG0_OFS ( 0) /*!< UCRXIFG0 Bit Offset */ -#define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /*!< eUSCI_B receive interrupt flag 0 */ -/* EUSCI_B_IFG[TXIFG0] Bits */ -#define EUSCI_B_IFG_TXIFG0_OFS ( 1) /*!< UCTXIFG0 Bit Offset */ -#define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /*!< eUSCI_B transmit interrupt flag 0 */ -/* EUSCI_B_IFG[STTIFG] Bits */ -#define EUSCI_B_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /*!< START condition interrupt flag */ -/* EUSCI_B_IFG[STPIFG] Bits */ -#define EUSCI_B_IFG_STPIFG_OFS ( 3) /*!< UCSTPIFG Bit Offset */ -#define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /*!< STOP condition interrupt flag */ -/* EUSCI_B_IFG[ALIFG] Bits */ -#define EUSCI_B_IFG_ALIFG_OFS ( 4) /*!< UCALIFG Bit Offset */ -#define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /*!< Arbitration lost interrupt flag */ -/* EUSCI_B_IFG[NACKIFG] Bits */ -#define EUSCI_B_IFG_NACKIFG_OFS ( 5) /*!< UCNACKIFG Bit Offset */ -#define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /*!< Not-acknowledge received interrupt flag */ -/* EUSCI_B_IFG[BCNTIFG] Bits */ -#define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /*!< UCBCNTIFG Bit Offset */ -#define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /*!< Byte counter interrupt flag */ -/* EUSCI_B_IFG[CLTOIFG] Bits */ -#define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /*!< UCCLTOIFG Bit Offset */ -#define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /*!< Clock low timeout interrupt flag */ -/* EUSCI_B_IFG[RXIFG1] Bits */ -#define EUSCI_B_IFG_RXIFG1_OFS ( 8) /*!< UCRXIFG1 Bit Offset */ -#define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /*!< eUSCI_B receive interrupt flag 1 */ -/* EUSCI_B_IFG[TXIFG1] Bits */ -#define EUSCI_B_IFG_TXIFG1_OFS ( 9) /*!< UCTXIFG1 Bit Offset */ -#define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /*!< eUSCI_B transmit interrupt flag 1 */ -/* EUSCI_B_IFG[RXIFG2] Bits */ -#define EUSCI_B_IFG_RXIFG2_OFS (10) /*!< UCRXIFG2 Bit Offset */ -#define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /*!< eUSCI_B receive interrupt flag 2 */ -/* EUSCI_B_IFG[TXIFG2] Bits */ -#define EUSCI_B_IFG_TXIFG2_OFS (11) /*!< UCTXIFG2 Bit Offset */ -#define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /*!< eUSCI_B transmit interrupt flag 2 */ -/* EUSCI_B_IFG[RXIFG3] Bits */ -#define EUSCI_B_IFG_RXIFG3_OFS (12) /*!< UCRXIFG3 Bit Offset */ -#define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /*!< eUSCI_B receive interrupt flag 3 */ -/* EUSCI_B_IFG[TXIFG3] Bits */ -#define EUSCI_B_IFG_TXIFG3_OFS (13) /*!< UCTXIFG3 Bit Offset */ -#define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /*!< eUSCI_B transmit interrupt flag 3 */ -/* EUSCI_B_IFG[BIT9IFG] Bits */ -#define EUSCI_B_IFG_BIT9IFG_OFS (14) /*!< UCBIT9IFG Bit Offset */ -#define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /*!< Bit position 9 interrupt flag */ -/* EUSCI_B_IFG[RXIFG] Bits */ -#define EUSCI_B_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -/* EUSCI_B_IFG[TXIFG] Bits */ -#define EUSCI_B_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -/* legacy definitions for backward compatibility to version 2100 */ -#define EUSCI_B__RXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_B__RXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_B__TXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_B__TXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ - - -/****************************************************************************** -* FLCTL Bits -******************************************************************************/ -/* FLCTL_POWER_STAT[PSTAT] Bits */ -#define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /*!< PSTAT Bit Offset */ -#define FLCTL_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /*!< PSTAT Bit Mask */ -#define FLCTL_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /*!< PSTAT Bit 0 */ -#define FLCTL_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /*!< PSTAT Bit 1 */ -#define FLCTL_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /*!< PSTAT Bit 2 */ -#define FLCTL_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /*!< Flash IP in power-down mode */ -#define FLCTL_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /*!< Flash IP Vdd domain power-up in progress */ -#define FLCTL_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */ -#define FLCTL_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /*!< Flash IP SAFE_LV check in progress */ -#define FLCTL_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /*!< Flash IP Active */ -#define FLCTL_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */ -#define FLCTL_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /*!< Flash IP in Standby mode */ -#define FLCTL_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /*!< Flash IP in Current mirror boost state */ -/* FLCTL_POWER_STAT[LDOSTAT] Bits */ -#define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /*!< LDOSTAT Bit Offset */ -#define FLCTL_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /*!< PSS FLDO GOOD status */ -/* FLCTL_POWER_STAT[VREFSTAT] Bits */ -#define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /*!< VREFSTAT Bit Offset */ -#define FLCTL_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /*!< PSS VREF stable status */ -/* FLCTL_POWER_STAT[IREFSTAT] Bits */ -#define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /*!< IREFSTAT Bit Offset */ -#define FLCTL_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /*!< PSS IREF stable status */ -/* FLCTL_POWER_STAT[TRIMSTAT] Bits */ -#define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /*!< TRIMSTAT Bit Offset */ -#define FLCTL_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /*!< PSS trim done status */ -/* FLCTL_POWER_STAT[RD_2T] Bits */ -#define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /*!< RD_2T Bit Offset */ -#define FLCTL_POWER_STAT_RD_2T ((uint32_t)0x00000080) /*!< Indicates if Flash is being accessed in 2T mode */ -/* FLCTL_BANK0_RDCTL[RD_MODE] Bits */ -#define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -/* FLCTL_BANK0_RDCTL[BUFI] Bits */ -#define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -/* FLCTL_BANK0_RDCTL[BUFD] Bits */ -#define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -/* FLCTL_BANK0_RDCTL[WAIT] Bits */ -#define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -/* FLCTL_BANK0_RDCTL[RD_MODE_STATUS] Bits */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -/* FLCTL_BANK1_RDCTL[RD_MODE] Bits */ -#define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -/* FLCTL_BANK1_RDCTL[BUFI] Bits */ -#define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -/* FLCTL_BANK1_RDCTL[BUFD] Bits */ -#define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -/* FLCTL_BANK1_RDCTL[RD_MODE_STATUS] Bits */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -/* FLCTL_BANK1_RDCTL[WAIT] Bits */ -#define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -/* FLCTL_RDBRST_CTLSTAT[START] Bits */ -#define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of burst/compare operation */ -/* FLCTL_RDBRST_CTLSTAT[MEM_TYPE] Bits */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /*!< MEM_TYPE Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /*!< MEM_TYPE Bit Mask */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /*!< MEM_TYPE Bit 0 */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /*!< MEM_TYPE Bit 1 */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -/* FLCTL_RDBRST_CTLSTAT[STOP_FAIL] Bits */ -#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /*!< STOP_FAIL Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /*!< Terminate burst/compare operation */ -/* FLCTL_RDBRST_CTLSTAT[DATA_CMP] Bits */ -#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /*!< DATA_CMP Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /*!< Data pattern used for comparison against memory read data */ -/* FLCTL_RDBRST_CTLSTAT[TEST_EN] Bits */ -#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /*!< TEST_EN Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /*!< Enable comparison against test data compare registers */ -/* FLCTL_RDBRST_CTLSTAT[BRST_STAT] Bits */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /*!< BRST_STAT Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /*!< BRST_STAT Bit Mask */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /*!< BRST_STAT Bit 0 */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /*!< BRST_STAT Bit 1 */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /*!< Idle */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /*!< Burst/Compare START bit written, but operation pending */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /*!< Burst/Compare in progress */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /*!< Burst complete (status of completed burst remains in this state unless */ - /* explicitly cleared by SW) */ -/* FLCTL_RDBRST_CTLSTAT[CMP_ERR] Bits */ -#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /*!< CMP_ERR Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /*!< Burst/Compare Operation encountered atleast one data */ -/* FLCTL_RDBRST_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /*!< Burst/Compare Operation was terminated due to access to */ -/* FLCTL_RDBRST_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 19-16 of this register */ -/* FLCTL_RDBRST_STARTADDR[START_ADDRESS] Bits */ -#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< START_ADDRESS Bit Mask */ -/* FLCTL_RDBRST_LEN[BURST_LENGTH] Bits */ -#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /*!< BURST_LENGTH Bit Offset */ -#define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /*!< BURST_LENGTH Bit Mask */ -/* FLCTL_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */ -#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /*!< FAIL_ADDRESS Bit Offset */ -#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< FAIL_ADDRESS Bit Mask */ -/* FLCTL_RDBRST_FAILCNT[FAIL_COUNT] Bits */ -#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /*!< FAIL_COUNT Bit Offset */ -#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /*!< FAIL_COUNT Bit Mask */ -/* FLCTL_PRG_CTLSTAT[ENABLE] Bits */ -#define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /*!< ENABLE Bit Offset */ -#define FLCTL_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /*!< Master control for all word program operations */ -/* FLCTL_PRG_CTLSTAT[MODE] Bits */ -#define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Write mode */ -/* FLCTL_PRG_CTLSTAT[VER_PRE] Bits */ -#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /*!< VER_PRE Bit Offset */ -#define FLCTL_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /*!< Controls automatic pre program verify operations */ -/* FLCTL_PRG_CTLSTAT[VER_PST] Bits */ -#define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /*!< VER_PST Bit Offset */ -#define FLCTL_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /*!< Controls automatic post program verify operations */ -/* FLCTL_PRG_CTLSTAT[STATUS] Bits */ -#define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Single word program operation triggered, but pending */ -#define FLCTL_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Single word program in progress */ -#define FLCTL_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Reserved (Idle) */ -/* FLCTL_PRG_CTLSTAT[BNK_ACT] Bits */ -#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /*!< BNK_ACT Bit Offset */ -#define FLCTL_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /*!< Bank active */ -/* FLCTL_PRGBRST_CTLSTAT[START] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Trigger start of burst program operation */ -/* FLCTL_PRGBRST_CTLSTAT[TYPE] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /*!< TYPE Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /*!< TYPE Bit Mask */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /*!< TYPE Bit 0 */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /*!< TYPE Bit 1 */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -/* FLCTL_PRGBRST_CTLSTAT[LEN] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /*!< LEN Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /*!< LEN Bit Mask */ -#define FLCTL_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /*!< LEN Bit 0 */ -#define FLCTL_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /*!< LEN Bit 1 */ -#define FLCTL_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /*!< LEN Bit 2 */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /*!< No burst operation */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /*!< 1 word burst of 128 bits, starting with address in the */ - /* FLCTL_PRGBRST_STARTADDR Register */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -/* FLCTL_PRGBRST_CTLSTAT[AUTO_PRE] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /*!< AUTO_PRE Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /*!< Auto-Verify operation before the Burst Program */ -/* FLCTL_PRGBRST_CTLSTAT[AUTO_PST] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /*!< AUTO_PST Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /*!< Auto-Verify operation after the Burst Program */ -/* FLCTL_PRGBRST_CTLSTAT[BURST_STATUS] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /*!< BURST_STATUS Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /*!< BURST_STATUS Bit Mask */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /*!< BURST_STATUS Bit 0 */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /*!< BURST_STATUS Bit 1 */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /*!< BURST_STATUS Bit 2 */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (Burst not active) */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /*!< Burst program started but pending */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /*!< Burst active, with 1st 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /*!< Burst active, with 2nd 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /*!< Burst active, with 3rd 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /*!< Burst active, with 4th 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /*!< Reserved (Idle) */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /*!< Burst Complete (status of completed burst remains in this state unless */ - /* explicitly cleared by SW) */ -/* FLCTL_PRGBRST_CTLSTAT[PRE_ERR] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /*!< PRE_ERR Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /*!< Burst Operation encountered preprogram auto-verify errors */ -/* FLCTL_PRGBRST_CTLSTAT[PST_ERR] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /*!< PST_ERR Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /*!< Burst Operation encountered postprogram auto-verify errors */ -/* FLCTL_PRGBRST_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /*!< Burst Operation was terminated due to attempted program of reserved memory */ -/* FLCTL_PRGBRST_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 21-16 of this register */ -/* FLCTL_PRGBRST_STARTADDR[START_ADDRESS] Bits */ -#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< START_ADDRESS Bit Mask */ -/* FLCTL_ERASE_CTLSTAT[START] Bits */ -#define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of Erase operation */ -/* FLCTL_ERASE_CTLSTAT[MODE] Bits */ -#define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Erase mode selected by application */ -/* FLCTL_ERASE_CTLSTAT[TYPE] Bits */ -#define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /*!< TYPE Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /*!< TYPE Bit Mask */ -#define FLCTL_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /*!< TYPE Bit 0 */ -#define FLCTL_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /*!< TYPE Bit 1 */ -#define FLCTL_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /*!< Information Memory */ -#define FLCTL_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /*!< Reserved */ -#define FLCTL_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /*!< Engineering Memory */ -/* FLCTL_ERASE_CTLSTAT[STATUS] Bits */ -#define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Erase operation triggered to START but pending */ -#define FLCTL_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Erase operation in progress */ -#define FLCTL_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Erase operation completed (status of completed erase remains in this state */ - /* unless explicitly cleared by SW) */ -/* FLCTL_ERASE_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /*!< Erase Operation was terminated due to attempted erase of reserved memory */ - /* address */ -/* FLCTL_ERASE_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /*!< CLR_STAT Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /*!< Clear status bits 18-16 of this register */ -/* FLCTL_ERASE_SECTADDR[SECT_ADDRESS] Bits */ -#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /*!< SECT_ADDRESS Bit Offset */ -#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< SECT_ADDRESS Bit Mask */ -/* FLCTL_BANK0_INFO_WEPROT[PROT0] Bits */ -#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_BANK0_INFO_WEPROT[PROT1] Bits */ -#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT0] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT1] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT2] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT3] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT4] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT5] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT6] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT7] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT8] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT9] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT10] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT11] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT12] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT13] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT14] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT15] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT16] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT17] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT18] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT19] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT20] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT21] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT22] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT23] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT24] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT25] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT26] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT27] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT28] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT29] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT30] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -/* FLCTL_BANK0_MAIN_WEPROT[PROT31] Bits */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -/* FLCTL_BANK1_INFO_WEPROT[PROT0] Bits */ -#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -/* FLCTL_BANK1_INFO_WEPROT[PROT1] Bits */ -#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT0] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT1] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT2] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT3] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT4] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT5] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT6] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT7] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT8] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT9] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT10] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT11] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT12] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT13] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT14] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT15] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT16] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT17] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT18] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT19] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT20] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT21] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT22] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT23] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT24] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT25] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT26] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT27] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT28] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT29] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT30] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase operations */ -/* FLCTL_BANK1_MAIN_WEPROT[PROT31] Bits */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase operations */ -/* FLCTL_BMRK_CTLSTAT[I_BMRK] Bits */ -#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /*!< I_BMRK Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001) -/* FLCTL_BMRK_CTLSTAT[D_BMRK] Bits */ -#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /*!< D_BMRK Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002) -/* FLCTL_BMRK_CTLSTAT[CMP_EN] Bits */ -#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /*!< CMP_EN Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004) -/* FLCTL_BMRK_CTLSTAT[CMP_SEL] Bits */ -#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /*!< CMP_SEL Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008) -/* FLCTL_IFG[RDBRST] Bits */ -#define FLCTL_IFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_IFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_IFG[AVPRE] Bits */ -#define FLCTL_IFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_IFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_IFG[AVPST] Bits */ -#define FLCTL_IFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_IFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_IFG[PRG] Bits */ -#define FLCTL_IFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_IFG_PRG ((uint32_t)0x00000008) -/* FLCTL_IFG[PRGB] Bits */ -#define FLCTL_IFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_IFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_IFG[ERASE] Bits */ -#define FLCTL_IFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_IFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_IFG[BMRK] Bits */ -#define FLCTL_IFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_IFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_IFG[PRG_ERR] Bits */ -#define FLCTL_IFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_IFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_IE[RDBRST] Bits */ -#define FLCTL_IE_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_IE_RDBRST ((uint32_t)0x00000001) -/* FLCTL_IE[AVPRE] Bits */ -#define FLCTL_IE_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_IE_AVPRE ((uint32_t)0x00000002) -/* FLCTL_IE[AVPST] Bits */ -#define FLCTL_IE_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_IE_AVPST ((uint32_t)0x00000004) -/* FLCTL_IE[PRG] Bits */ -#define FLCTL_IE_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_IE_PRG ((uint32_t)0x00000008) -/* FLCTL_IE[PRGB] Bits */ -#define FLCTL_IE_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_IE_PRGB ((uint32_t)0x00000010) -/* FLCTL_IE[ERASE] Bits */ -#define FLCTL_IE_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_IE_ERASE ((uint32_t)0x00000020) -/* FLCTL_IE[BMRK] Bits */ -#define FLCTL_IE_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_IE_BMRK ((uint32_t)0x00000100) -/* FLCTL_IE[PRG_ERR] Bits */ -#define FLCTL_IE_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_IE_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_CLRIFG[RDBRST] Bits */ -#define FLCTL_CLRIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_CLRIFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_CLRIFG[AVPRE] Bits */ -#define FLCTL_CLRIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_CLRIFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_CLRIFG[AVPST] Bits */ -#define FLCTL_CLRIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_CLRIFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_CLRIFG[PRG] Bits */ -#define FLCTL_CLRIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_CLRIFG_PRG ((uint32_t)0x00000008) -/* FLCTL_CLRIFG[PRGB] Bits */ -#define FLCTL_CLRIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_CLRIFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_CLRIFG[ERASE] Bits */ -#define FLCTL_CLRIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_CLRIFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_CLRIFG[BMRK] Bits */ -#define FLCTL_CLRIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_CLRIFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_CLRIFG[PRG_ERR] Bits */ -#define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_CLRIFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_SETIFG[RDBRST] Bits */ -#define FLCTL_SETIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_SETIFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_SETIFG[AVPRE] Bits */ -#define FLCTL_SETIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_SETIFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_SETIFG[AVPST] Bits */ -#define FLCTL_SETIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_SETIFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_SETIFG[PRG] Bits */ -#define FLCTL_SETIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_SETIFG_PRG ((uint32_t)0x00000008) -/* FLCTL_SETIFG[PRGB] Bits */ -#define FLCTL_SETIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_SETIFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_SETIFG[ERASE] Bits */ -#define FLCTL_SETIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_SETIFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_SETIFG[BMRK] Bits */ -#define FLCTL_SETIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_SETIFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_SETIFG[PRG_ERR] Bits */ -#define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_SETIFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_READ_TIMCTL[SETUP] Bits */ -#define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_READ_TIMCTL[IREF_BOOST1] Bits */ -#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /*!< IREF_BOOST1 Bit Offset */ -#define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /*!< IREF_BOOST1 Bit Mask */ -/* FLCTL_READ_TIMCTL[SETUP_LONG] Bits */ -#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /*!< SETUP_LONG Bit Offset */ -#define FLCTL_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /*!< SETUP_LONG Bit Mask */ -/* FLCTL_READMARGIN_TIMCTL[SETUP] Bits */ -#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_PRGVER_TIMCTL[SETUP] Bits */ -#define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_PRGVER_TIMCTL[ACTIVE] Bits */ -#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /*!< ACTIVE Bit Mask */ -/* FLCTL_PRGVER_TIMCTL[HOLD] Bits */ -#define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /*!< HOLD Bit Offset */ -#define FLCTL_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /*!< HOLD Bit Mask */ -/* FLCTL_ERSVER_TIMCTL[SETUP] Bits */ -#define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_LKGVER_TIMCTL[SETUP] Bits */ -#define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_PROGRAM_TIMCTL[SETUP] Bits */ -#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_PROGRAM_TIMCTL[ACTIVE] Bits */ -#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_PROGRAM_TIMCTL[HOLD] Bits */ -#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -/* FLCTL_ERASE_TIMCTL[SETUP] Bits */ -#define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_ERASE_TIMCTL[ACTIVE] Bits */ -#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_ERASE_TIMCTL[HOLD] Bits */ -#define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -/* FLCTL_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /*!< BOOST_ACTIVE Bit Offset */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /*!< BOOST_ACTIVE Bit Mask */ -/* FLCTL_MASSERASE_TIMCTL[BOOST_HOLD] Bits */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /*!< BOOST_HOLD Bit Offset */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /*!< BOOST_HOLD Bit Mask */ -/* FLCTL_BURSTPRG_TIMCTL[ACTIVE] Bits */ -#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ - -/****************************************************************************** -* FL_BOOTOVER_MAILBOX Bits -******************************************************************************/ - -/****************************************************************************** -* FPB Bits -******************************************************************************/ - - -/****************************************************************************** -* FPU Bits -******************************************************************************/ - - -/****************************************************************************** -* ITM Bits -******************************************************************************/ - - -/****************************************************************************** -* MPU Bits -******************************************************************************/ - -/* Pre-defined bitfield values */ - -/* MPU_RASR_SIZE Bitfield Bits */ -#define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /*!< 32B */ -#define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /*!< 64B */ -#define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /*!< 128B */ -#define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /*!< 256B */ -#define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /*!< 512B */ -#define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /*!< 1KB */ -#define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /*!< 2KB */ -#define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /*!< 4KB */ -#define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /*!< 8KB */ -#define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /*!< 16KB */ -#define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /*!< 32KB */ -#define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /*!< 64KB */ -#define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /*!< 128KB */ -#define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /*!< 256KB */ -#define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /*!< 512KB */ -#define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /*!< 1MB */ -#define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /*!< 2MB */ -#define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /*!< 4MB */ -#define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /*!< 8MB */ -#define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /*!< 16MB */ -#define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /*!< 32MB */ -#define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /*!< 64MB */ -#define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /*!< 128MB */ -#define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /*!< 256MB */ -#define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /*!< 512MB */ -#define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /*!< 1GB */ -#define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /*!< 2GB */ -#define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /*!< 4GB */ - -/* MPU_RASR_AP Bitfield Bits */ -#define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /*!< Privileged permissions: No access. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /*!< Privileged permissions: Read-write. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /*!< Privileged permissions: Read-write. User permissions: Read-only. */ -#define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /*!< Privileged permissions: Read-write. User permissions: Read-write. */ -#define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /*!< Privileged permissions: Read-only. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /*!< Privileged permissions: Read-only. User permissions: Read-only. */ - -/* MPU_RASR_XN Bitfield Bits */ -#define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /*!< Instruction access enabled */ -#define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /*!< Instruction access disabled */ - - -/****************************************************************************** -* NVIC Bits -******************************************************************************/ - -/* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */ -#define NVIC_IPR0_PRI_0_OFS ( 0) /*!< PRI_0 Offset */ -#define NVIC_IPR0_PRI_0_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */ -#define NVIC_IPR0_PRI_1_OFS ( 8) /*!< PRI_1 Offset */ -#define NVIC_IPR0_PRI_1_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */ -#define NVIC_IPR0_PRI_2_OFS (16) /*!< PRI_2 Offset */ -#define NVIC_IPR0_PRI_2_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */ -#define NVIC_IPR0_PRI_3_OFS (24) /*!< PRI_3 Offset */ -#define NVIC_IPR0_PRI_3_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */ -#define NVIC_IPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define NVIC_IPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */ -#define NVIC_IPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define NVIC_IPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */ -#define NVIC_IPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define NVIC_IPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */ -#define NVIC_IPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define NVIC_IPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */ -#define NVIC_IPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define NVIC_IPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */ -#define NVIC_IPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define NVIC_IPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */ -#define NVIC_IPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define NVIC_IPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */ -#define NVIC_IPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define NVIC_IPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */ -#define NVIC_IPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define NVIC_IPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */ -#define NVIC_IPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define NVIC_IPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */ -#define NVIC_IPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define NVIC_IPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */ -#define NVIC_IPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define NVIC_IPR3_PRI_15_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */ -#define NVIC_IPR4_PRI_16_OFS ( 0) /*!< PRI_16 Offset */ -#define NVIC_IPR4_PRI_16_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */ -#define NVIC_IPR4_PRI_17_OFS ( 8) /*!< PRI_17 Offset */ -#define NVIC_IPR4_PRI_17_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */ -#define NVIC_IPR4_PRI_18_OFS (16) /*!< PRI_18 Offset */ -#define NVIC_IPR4_PRI_18_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */ -#define NVIC_IPR4_PRI_19_OFS (24) /*!< PRI_19 Offset */ -#define NVIC_IPR4_PRI_19_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */ -#define NVIC_IPR5_PRI_20_OFS ( 0) /*!< PRI_20 Offset */ -#define NVIC_IPR5_PRI_20_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */ -#define NVIC_IPR5_PRI_21_OFS ( 8) /*!< PRI_21 Offset */ -#define NVIC_IPR5_PRI_21_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */ -#define NVIC_IPR5_PRI_22_OFS (16) /*!< PRI_22 Offset */ -#define NVIC_IPR5_PRI_22_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */ -#define NVIC_IPR5_PRI_23_OFS (24) /*!< PRI_23 Offset */ -#define NVIC_IPR5_PRI_23_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */ -#define NVIC_IPR6_PRI_24_OFS ( 0) /*!< PRI_24 Offset */ -#define NVIC_IPR6_PRI_24_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */ -#define NVIC_IPR6_PRI_25_OFS ( 8) /*!< PRI_25 Offset */ -#define NVIC_IPR6_PRI_25_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */ -#define NVIC_IPR6_PRI_26_OFS (16) /*!< PRI_26 Offset */ -#define NVIC_IPR6_PRI_26_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */ -#define NVIC_IPR6_PRI_27_OFS (24) /*!< PRI_27 Offset */ -#define NVIC_IPR6_PRI_27_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */ -#define NVIC_IPR7_PRI_28_OFS ( 0) /*!< PRI_28 Offset */ -#define NVIC_IPR7_PRI_28_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */ -#define NVIC_IPR7_PRI_29_OFS ( 8) /*!< PRI_29 Offset */ -#define NVIC_IPR7_PRI_29_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */ -#define NVIC_IPR7_PRI_30_OFS (16) /*!< PRI_30 Offset */ -#define NVIC_IPR7_PRI_30_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */ -#define NVIC_IPR7_PRI_31_OFS (24) /*!< PRI_31 Offset */ -#define NVIC_IPR7_PRI_31_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */ -#define NVIC_IPR8_PRI_32_OFS ( 0) /*!< PRI_32 Offset */ -#define NVIC_IPR8_PRI_32_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */ -#define NVIC_IPR8_PRI_33_OFS ( 8) /*!< PRI_33 Offset */ -#define NVIC_IPR8_PRI_33_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */ -#define NVIC_IPR8_PRI_34_OFS (16) /*!< PRI_34 Offset */ -#define NVIC_IPR8_PRI_34_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */ -#define NVIC_IPR8_PRI_35_OFS (24) /*!< PRI_35 Offset */ -#define NVIC_IPR8_PRI_35_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */ -#define NVIC_IPR9_PRI_36_OFS ( 0) /*!< PRI_36 Offset */ -#define NVIC_IPR9_PRI_36_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */ -#define NVIC_IPR9_PRI_37_OFS ( 8) /*!< PRI_37 Offset */ -#define NVIC_IPR9_PRI_37_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */ -#define NVIC_IPR9_PRI_38_OFS (16) /*!< PRI_38 Offset */ -#define NVIC_IPR9_PRI_38_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */ -#define NVIC_IPR9_PRI_39_OFS (24) /*!< PRI_39 Offset */ -#define NVIC_IPR9_PRI_39_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */ -#define NVIC_IPR10_PRI_40_OFS ( 0) /*!< PRI_40 Offset */ -#define NVIC_IPR10_PRI_40_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */ -#define NVIC_IPR10_PRI_41_OFS ( 8) /*!< PRI_41 Offset */ -#define NVIC_IPR10_PRI_41_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */ -#define NVIC_IPR10_PRI_42_OFS (16) /*!< PRI_42 Offset */ -#define NVIC_IPR10_PRI_42_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */ -#define NVIC_IPR10_PRI_43_OFS (24) /*!< PRI_43 Offset */ -#define NVIC_IPR10_PRI_43_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */ -#define NVIC_IPR11_PRI_44_OFS ( 0) /*!< PRI_44 Offset */ -#define NVIC_IPR11_PRI_44_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */ -#define NVIC_IPR11_PRI_45_OFS ( 8) /*!< PRI_45 Offset */ -#define NVIC_IPR11_PRI_45_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */ -#define NVIC_IPR11_PRI_46_OFS (16) /*!< PRI_46 Offset */ -#define NVIC_IPR11_PRI_46_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */ -#define NVIC_IPR11_PRI_47_OFS (24) /*!< PRI_47 Offset */ -#define NVIC_IPR11_PRI_47_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */ -#define NVIC_IPR12_PRI_48_OFS ( 0) /*!< PRI_48 Offset */ -#define NVIC_IPR12_PRI_48_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */ -#define NVIC_IPR12_PRI_49_OFS ( 8) /*!< PRI_49 Offset */ -#define NVIC_IPR12_PRI_49_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */ -#define NVIC_IPR12_PRI_50_OFS (16) /*!< PRI_50 Offset */ -#define NVIC_IPR12_PRI_50_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */ -#define NVIC_IPR12_PRI_51_OFS (24) /*!< PRI_51 Offset */ -#define NVIC_IPR12_PRI_51_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */ -#define NVIC_IPR13_PRI_52_OFS ( 0) /*!< PRI_52 Offset */ -#define NVIC_IPR13_PRI_52_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */ -#define NVIC_IPR13_PRI_53_OFS ( 8) /*!< PRI_53 Offset */ -#define NVIC_IPR13_PRI_53_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */ -#define NVIC_IPR13_PRI_54_OFS (16) /*!< PRI_54 Offset */ -#define NVIC_IPR13_PRI_54_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */ -#define NVIC_IPR13_PRI_55_OFS (24) /*!< PRI_55 Offset */ -#define NVIC_IPR13_PRI_55_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */ -#define NVIC_IPR14_PRI_56_OFS ( 0) /*!< PRI_56 Offset */ -#define NVIC_IPR14_PRI_56_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */ -#define NVIC_IPR14_PRI_57_OFS ( 8) /*!< PRI_57 Offset */ -#define NVIC_IPR14_PRI_57_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */ -#define NVIC_IPR14_PRI_58_OFS (16) /*!< PRI_58 Offset */ -#define NVIC_IPR14_PRI_58_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */ -#define NVIC_IPR14_PRI_59_OFS (24) /*!< PRI_59 Offset */ -#define NVIC_IPR14_PRI_59_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */ -#define NVIC_IPR15_PRI_60_OFS ( 0) /*!< PRI_60 Offset */ -#define NVIC_IPR15_PRI_60_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */ -#define NVIC_IPR15_PRI_61_OFS ( 8) /*!< PRI_61 Offset */ -#define NVIC_IPR15_PRI_61_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */ -#define NVIC_IPR15_PRI_62_OFS (16) /*!< PRI_62 Offset */ -#define NVIC_IPR15_PRI_62_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */ -#define NVIC_IPR15_PRI_63_OFS (24) /*!< PRI_63 Offset */ -#define NVIC_IPR15_PRI_63_M ((uint32_t)0xff000000) /* */ - - -/****************************************************************************** -* PCM Bits -******************************************************************************/ -/* PCM_CTL0[AMR] Bits */ -#define PCM_CTL0_AMR_OFS ( 0) /*!< AMR Bit Offset */ -#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /*!< AMR Bit Mask */ -#define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /*!< AMR Bit 0 */ -#define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /*!< AMR Bit 1 */ -#define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /*!< AMR Bit 2 */ -#define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /*!< AMR Bit 3 */ -#define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -/* PCM_CTL0[LPMR] Bits */ -#define PCM_CTL0_LPMR_OFS ( 4) /*!< LPMR Bit Offset */ -#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /*!< LPMR Bit Mask */ -#define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /*!< LPMR Bit 0 */ -#define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /*!< LPMR Bit 1 */ -#define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /*!< LPMR Bit 2 */ -#define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /*!< LPMR Bit 3 */ -#define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ - /* entered. */ -#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -#define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ - /* entered. */ -#define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -/* PCM_CTL0[CPM] Bits */ -#define PCM_CTL0_CPM_OFS ( 8) /*!< CPM Bit Offset */ -#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /*!< CPM Bit Mask */ -#define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /*!< CPM Bit 0 */ -#define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /*!< CPM Bit 1 */ -#define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /*!< CPM Bit 2 */ -#define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /*!< CPM Bit 3 */ -#define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /*!< CPM Bit 4 */ -#define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /*!< CPM Bit 5 */ -#define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /*!< LPM3 */ -#define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /*!< LPM3 */ -/* PCM_CTL0[KEY] Bits */ -#define PCM_CTL0_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -/* PCM_CTL1[LOCKLPM5] Bits */ -#define PCM_CTL1_LOCKLPM5_OFS ( 0) /*!< LOCKLPM5 Bit Offset */ -#define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /*!< Lock LPM5 */ -/* PCM_CTL1[LOCKBKUP] Bits */ -#define PCM_CTL1_LOCKBKUP_OFS ( 1) /*!< LOCKBKUP Bit Offset */ -#define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /*!< Lock Backup */ -/* PCM_CTL1[FORCE_LPM_ENTRY] Bits */ -#define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /*!< FORCE_LPM_ENTRY Bit Offset */ -#define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /*!< Force LPM entry */ -/* PCM_CTL1[PMR_BUSY] Bits */ -#define PCM_CTL1_PMR_BUSY_OFS ( 8) /*!< PMR_BUSY Bit Offset */ -#define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /*!< Power mode request busy flag */ -/* PCM_CTL1[KEY] Bits */ -#define PCM_CTL1_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -/* PCM_IE[LPM_INVALID_TR_IE] Bits */ -#define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /*!< LPM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /*!< LPM invalid transition interrupt enable */ -/* PCM_IE[LPM_INVALID_CLK_IE] Bits */ -#define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /*!< LPM_INVALID_CLK_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /*!< LPM invalid clock interrupt enable */ -/* PCM_IE[AM_INVALID_TR_IE] Bits */ -#define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /*!< AM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /*!< Active mode invalid transition interrupt enable */ -/* PCM_IE[DCDC_ERROR_IE] Bits */ -#define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /*!< DCDC_ERROR_IE Bit Offset */ -#define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /*!< DC-DC error interrupt enable */ -/* PCM_IFG[LPM_INVALID_TR_IFG] Bits */ -#define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /*!< LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< LPM invalid transition flag */ -/* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */ -#define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< LPM invalid clock flag */ -/* PCM_IFG[AM_INVALID_TR_IFG] Bits */ -#define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /*!< AM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Active mode invalid transition flag */ -/* PCM_IFG[DCDC_ERROR_IFG] Bits */ -#define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /*!< DCDC_ERROR_IFG Bit Offset */ -#define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< DC-DC error flag */ -/* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< Clear LPM invalid transition flag */ -/* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< Clear LPM invalid clock flag */ -/* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /*!< CLR_AM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Clear active mode invalid transition flag */ -/* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /*!< CLR_DCDC_ERROR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< Clear DC-DC error flag */ -/* Pre-defined bitfield values */ -#define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ -#define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ - - -/****************************************************************************** -* PMAP Bits -******************************************************************************/ -/* PMAP_CTL[LOCKED] Bits */ -#define PMAP_CTL_LOCKED_OFS ( 0) /*!< PMAPLOCKED Bit Offset */ -#define PMAP_CTL_LOCKED ((uint16_t)0x0001) /*!< Port mapping lock bit */ -/* PMAP_CTL[PRECFG] Bits */ -#define PMAP_CTL_PRECFG_OFS ( 1) /*!< PMAPRECFG Bit Offset */ -#define PMAP_CTL_PRECFG ((uint16_t)0x0002) /*!< Port mapping reconfiguration control bit */ -/* Pre-defined bitfield values */ -#define PMAP_NONE 0 -#define PMAP_UCA0CLK 1 -#define PMAP_UCA0RXD 2 -#define PMAP_UCA0SOMI 2 -#define PMAP_UCA0TXD 3 -#define PMAP_UCA0SIMO 3 -#define PMAP_UCB0CLK 4 -#define PMAP_UCB0SDA 5 -#define PMAP_UCB0SIMO 5 -#define PMAP_UCB0SCL 6 -#define PMAP_UCB0SOMI 6 -#define PMAP_UCA1STE 7 -#define PMAP_UCA1CLK 8 -#define PMAP_UCA1RXD 9 -#define PMAP_UCA1SOMI 9 -#define PMAP_UCA1TXD 10 -#define PMAP_UCA1SIMO 10 -#define PMAP_UCA2STE 11 -#define PMAP_UCA2CLK 12 -#define PMAP_UCA2RXD 13 -#define PMAP_UCA2SOMI 13 -#define PMAP_UCA2TXD 14 -#define PMAP_UCA2SIMO 14 -#define PMAP_UCB2STE 15 -#define PMAP_UCB2CLK 16 -#define PMAP_UCB2SDA 17 -#define PMAP_UCB2SIMO 17 -#define PMAP_UCB2SCL 18 -#define PMAP_UCB2SOMI 18 -#define PMAP_TA0CCR0A 19 -#define PMAP_TA0CCR1A 20 -#define PMAP_TA0CCR2A 21 -#define PMAP_TA0CCR3A 22 -#define PMAP_TA0CCR4A 23 -#define PMAP_TA1CCR1A 24 -#define PMAP_TA1CCR2A 25 -#define PMAP_TA1CCR3A 26 -#define PMAP_TA1CCR4A 27 -#define PMAP_TA0CLK 28 -#define PMAP_CE0OUT 28 -#define PMAP_TA1CLK 29 -#define PMAP_CE1OUT 29 -#define PMAP_DMAE0 30 -#define PMAP_SMCLK 30 -#define PMAP_ANALOG 31 - -#define PMAP_KEYID_VAL ((uint16_t)0x2D52) /*!< Port Mapping Key */ - - -/****************************************************************************** -* PSS Bits -******************************************************************************/ -/* PSS_KEY[KEY] Bits */ -#define PSS_KEY_KEY_OFS ( 0) /*!< PSSKEY Bit Offset */ -#define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< PSSKEY Bit Mask */ -/* PSS_CTL0[SVSMHOFF] Bits */ -#define PSS_CTL0_SVSMHOFF_OFS ( 0) /*!< SVSMHOFF Bit Offset */ -#define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /*!< SVSM high-side off */ -/* PSS_CTL0[SVSMHLP] Bits */ -#define PSS_CTL0_SVSMHLP_OFS ( 1) /*!< SVSMHLP Bit Offset */ -#define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /*!< SVSM high-side low power normal performance mode */ -/* PSS_CTL0[SVSMHS] Bits */ -#define PSS_CTL0_SVSMHS_OFS ( 2) /*!< SVSMHS Bit Offset */ -#define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /*!< Supply supervisor or monitor selection for the high-side */ -/* PSS_CTL0[SVSMHTH] Bits */ -#define PSS_CTL0_SVSMHTH_OFS ( 3) /*!< SVSMHTH Bit Offset */ -#define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /*!< SVSMHTH Bit Mask */ -/* PSS_CTL0[SVMHOE] Bits */ -#define PSS_CTL0_SVMHOE_OFS ( 6) /*!< SVMHOE Bit Offset */ -#define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /*!< SVSM high-side output enable */ -/* PSS_CTL0[SVMHOUTPOLAL] Bits */ -#define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /*!< SVMHOUTPOLAL Bit Offset */ -#define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /*!< SVMHOUT pin polarity active low */ -/* PSS_CTL0[DCDC_FORCE] Bits */ -#define PSS_CTL0_DCDC_FORCE_OFS (10) /*!< DCDC_FORCE Bit Offset */ -#define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /*!< Force DC-DC regulator operation */ -/* PSS_CTL0[VCORETRAN] Bits */ -#define PSS_CTL0_VCORETRAN_OFS (12) /*!< VCORETRAN Bit Offset */ -#define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /*!< VCORETRAN Bit Mask */ -#define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /*!< VCORETRAN Bit 0 */ -#define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /*!< VCORETRAN Bit 1 */ -#define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -/* PSS_IE[SVSMHIE] Bits */ -#define PSS_IE_SVSMHIE_OFS ( 1) /*!< SVSMHIE Bit Offset */ -#define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /*!< High-side SVSM interrupt enable */ -/* PSS_IFG[SVSMHIFG] Bits */ -#define PSS_IFG_SVSMHIFG_OFS ( 1) /*!< SVSMHIFG Bit Offset */ -#define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /*!< High-side SVSM interrupt flag */ -/* PSS_CLRIFG[CLRSVSMHIFG] Bits */ -#define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /*!< CLRSVSMHIFG Bit Offset */ -#define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /*!< SVSMH clear interrupt flag */ -/* Pre-defined bitfield values */ -#define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /*!< PSS control key value */ - - -/****************************************************************************** -* REF_A Bits -******************************************************************************/ -/* REF_A_CTL0[ON] Bits */ -#define REF_A_CTL0_ON_OFS ( 0) /*!< REFON Bit Offset */ -#define REF_A_CTL0_ON ((uint16_t)0x0001) /*!< Reference enable */ -/* REF_A_CTL0[OUT] Bits */ -#define REF_A_CTL0_OUT_OFS ( 1) /*!< REFOUT Bit Offset */ -#define REF_A_CTL0_OUT ((uint16_t)0x0002) /*!< Reference output buffer */ -/* REF_A_CTL0[TCOFF] Bits */ -#define REF_A_CTL0_TCOFF_OFS ( 3) /*!< REFTCOFF Bit Offset */ -#define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /*!< Temperature sensor disabled */ -/* REF_A_CTL0[VSEL] Bits */ -#define REF_A_CTL0_VSEL_OFS ( 4) /*!< REFVSEL Bit Offset */ -#define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /*!< REFVSEL Bit Mask */ -#define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /*!< VSEL Bit 0 */ -#define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /*!< VSEL Bit 1 */ -#define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /*!< 1.2 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /*!< 1.45 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /*!< 2.5 V available when reference requested or REFON = 1 */ -/* REF_A_CTL0[GENOT] Bits */ -#define REF_A_CTL0_GENOT_OFS ( 6) /*!< REFGENOT Bit Offset */ -#define REF_A_CTL0_GENOT ((uint16_t)0x0040) /*!< Reference generator one-time trigger */ -/* REF_A_CTL0[BGOT] Bits */ -#define REF_A_CTL0_BGOT_OFS ( 7) /*!< REFBGOT Bit Offset */ -#define REF_A_CTL0_BGOT ((uint16_t)0x0080) /*!< Bandgap and bandgap buffer one-time trigger */ -/* REF_A_CTL0[GENACT] Bits */ -#define REF_A_CTL0_GENACT_OFS ( 8) /*!< REFGENACT Bit Offset */ -#define REF_A_CTL0_GENACT ((uint16_t)0x0100) /*!< Reference generator active */ -/* REF_A_CTL0[BGACT] Bits */ -#define REF_A_CTL0_BGACT_OFS ( 9) /*!< REFBGACT Bit Offset */ -#define REF_A_CTL0_BGACT ((uint16_t)0x0200) /*!< Reference bandgap active */ -/* REF_A_CTL0[GENBUSY] Bits */ -#define REF_A_CTL0_GENBUSY_OFS (10) /*!< REFGENBUSY Bit Offset */ -#define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /*!< Reference generator busy */ -/* REF_A_CTL0[BGMODE] Bits */ -#define REF_A_CTL0_BGMODE_OFS (11) /*!< BGMODE Bit Offset */ -#define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /*!< Bandgap mode */ -/* REF_A_CTL0[GENRDY] Bits */ -#define REF_A_CTL0_GENRDY_OFS (12) /*!< REFGENRDY Bit Offset */ -#define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /*!< Variable reference voltage ready status */ -/* REF_A_CTL0[BGRDY] Bits */ -#define REF_A_CTL0_BGRDY_OFS (13) /*!< REFBGRDY Bit Offset */ -#define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /*!< Buffered bandgap voltage ready status */ - -/****************************************************************************** -* RSTCTL Bits -******************************************************************************/ -/* RSTCTL_RESET_REQ[SOFT_REQ] Bits */ -#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /*!< SOFT_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /*!< Soft Reset request */ -/* RSTCTL_RESET_REQ[HARD_REQ] Bits */ -#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /*!< HARD_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /*!< Hard Reset request */ -/* RSTCTL_RESET_REQ[RSTKEY] Bits */ -#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /*!< RSTKEY Bit Offset */ -#define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /*!< RSTKEY Bit Mask */ -/* RSTCTL_HARDRESET_STAT[SRC0] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< Indicates that SRC0 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC1] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< Indicates that SRC1 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC2] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< Indicates that SRC2 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC3] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< Indicates that SRC3 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC4] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< Indicates that SRC4 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC5] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< Indicates that SRC5 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC6] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< Indicates that SRC6 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC7] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< Indicates that SRC7 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC8] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< Indicates that SRC8 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC9] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< Indicates that SRC9 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC10] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< Indicates that SRC10 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC11] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< Indicates that SRC11 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC12] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< Indicates that SRC12 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC13] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< Indicates that SRC13 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC14] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< Indicates that SRC14 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC15] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< Indicates that SRC15 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_CLR[SRC0] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC1] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC2] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC3] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC4] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC5] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC6] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC7] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC8] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC9] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC10] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC11] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC12] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC13] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC14] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC15] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */ -/* RSTCTL_HARDRESET_SET[SRC0] Bits */ -#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC1] Bits */ -#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC2] Bits */ -#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC3] Bits */ -#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC4] Bits */ -#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC5] Bits */ -#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC6] Bits */ -#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC7] Bits */ -#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC8] Bits */ -#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC9] Bits */ -#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC10] Bits */ -#define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC11] Bits */ -#define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC12] Bits */ -#define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC13] Bits */ -#define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC14] Bits */ -#define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC15] Bits */ -#define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_SOFTRESET_STAT[SRC0] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< If 1, indicates that SRC0 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC1] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< If 1, indicates that SRC1 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC2] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< If 1, indicates that SRC2 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC3] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< If 1, indicates that SRC3 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC4] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< If 1, indicates that SRC4 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC5] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< If 1, indicates that SRC5 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC6] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< If 1, indicates that SRC6 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC7] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< If 1, indicates that SRC7 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC8] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< If 1, indicates that SRC8 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC9] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< If 1, indicates that SRC9 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC10] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< If 1, indicates that SRC10 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC11] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< If 1, indicates that SRC11 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC12] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< If 1, indicates that SRC12 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC13] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< If 1, indicates that SRC13 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC14] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< If 1, indicates that SRC14 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC15] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< If 1, indicates that SRC15 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_CLR[SRC0] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC1] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC2] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC3] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC4] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC5] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC6] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC7] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC8] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC9] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC10] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC11] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC12] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC13] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC14] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC15] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_SET[SRC0] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC1] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC2] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC3] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC4] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC5] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC6] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC7] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC8] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC9] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC10] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC11] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC12] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC13] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC14] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC15] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_PSSRESET_STAT[SVSMH] Bits */ -#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /*!< SVSMH Bit Offset */ -#define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */ -/* RSTCTL_PSSRESET_STAT[BGREF] Bits */ -#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /*!< BGREF Bit Offset */ -#define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */ -/* RSTCTL_PSSRESET_STAT[VCCDET] Bits */ -#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /*!< VCCDET Bit Offset */ -#define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */ -/* RSTCTL_PSSRESET_CLR[CLR] Bits */ -#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */ -/* RSTCTL_PCMRESET_STAT[LPM35] Bits */ -#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /*!< LPM35 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */ -/* RSTCTL_PCMRESET_STAT[LPM45] Bits */ -#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /*!< LPM45 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */ -/* RSTCTL_PCMRESET_CLR[CLR] Bits */ -#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */ -/* RSTCTL_PINRESET_STAT[RSTNMI] Bits */ -#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /*!< RSTNMI Bit Offset */ -#define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /*!< POR was caused by RSTn/NMI pin based reset event */ -/* RSTCTL_PINRESET_CLR[CLR] Bits */ -#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */ -/* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /*!< Indicates if Reboot reset was caused by the SYSCTL module. */ -/* RSTCTL_REBOOTRESET_CLR[CLR] Bits */ -#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */ -/* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /*!< DCOR_SHT Bit Offset */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /*!< Indicates if POR was caused by DCO short circuit fault in the external */ - /* resistor mode */ -/* RSTCTL_CSRESET_CLR[CLR] Bits */ -#define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as */ - /* DCOR_SHTIFG flag in CSIFG register of clock system */ -/* Pre-defined bitfield values */ -#define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bits 1-0 */ - - -/****************************************************************************** -* RTC_C Bits -******************************************************************************/ -/* RTC_C_CTL0[RDYIFG] Bits */ -#define RTC_C_CTL0_RDYIFG_OFS ( 0) /*!< RTCRDYIFG Bit Offset */ -#define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /*!< Real-time clock ready interrupt flag */ -/* RTC_C_CTL0[AIFG] Bits */ -#define RTC_C_CTL0_AIFG_OFS ( 1) /*!< RTCAIFG Bit Offset */ -#define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /*!< Real-time clock alarm interrupt flag */ -/* RTC_C_CTL0[TEVIFG] Bits */ -#define RTC_C_CTL0_TEVIFG_OFS ( 2) /*!< RTCTEVIFG Bit Offset */ -#define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /*!< Real-time clock time event interrupt flag */ -/* RTC_C_CTL0[OFIFG] Bits */ -#define RTC_C_CTL0_OFIFG_OFS ( 3) /*!< RTCOFIFG Bit Offset */ -#define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /*!< 32-kHz crystal oscillator fault interrupt flag */ -/* RTC_C_CTL0[RDYIE] Bits */ -#define RTC_C_CTL0_RDYIE_OFS ( 4) /*!< RTCRDYIE Bit Offset */ -#define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /*!< Real-time clock ready interrupt enable */ -/* RTC_C_CTL0[AIE] Bits */ -#define RTC_C_CTL0_AIE_OFS ( 5) /*!< RTCAIE Bit Offset */ -#define RTC_C_CTL0_AIE ((uint16_t)0x0020) /*!< Real-time clock alarm interrupt enable */ -/* RTC_C_CTL0[TEVIE] Bits */ -#define RTC_C_CTL0_TEVIE_OFS ( 6) /*!< RTCTEVIE Bit Offset */ -#define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /*!< Real-time clock time event interrupt enable */ -/* RTC_C_CTL0[OFIE] Bits */ -#define RTC_C_CTL0_OFIE_OFS ( 7) /*!< RTCOFIE Bit Offset */ -#define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /*!< 32-kHz crystal oscillator fault interrupt enable */ -/* RTC_C_CTL0[KEY] Bits */ -#define RTC_C_CTL0_KEY_OFS ( 8) /*!< RTCKEY Bit Offset */ -#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /*!< RTCKEY Bit Mask */ -/* RTC_C_CTL13[TEV] Bits */ -#define RTC_C_CTL13_TEV_OFS ( 0) /*!< RTCTEV Bit Offset */ -#define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /*!< RTCTEV Bit Mask */ -#define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /*!< TEV Bit 0 */ -#define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /*!< TEV Bit 1 */ -#define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /*!< Minute changed */ -#define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /*!< Hour changed */ -#define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /*!< Every day at midnight (00:00) */ -#define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /*!< Every day at noon (12:00) */ -/* RTC_C_CTL13[SSEL] Bits */ -#define RTC_C_CTL13_SSEL_OFS ( 2) /*!< RTCSSEL Bit Offset */ -#define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /*!< RTCSSEL Bit Mask */ -#define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /*!< SSEL Bit 0 */ -#define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /*!< SSEL Bit 1 */ -#define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /*!< BCLK */ -#define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /*!< BCLK */ -/* RTC_C_CTL13[RDY] Bits */ -#define RTC_C_CTL13_RDY_OFS ( 4) /*!< RTCRDY Bit Offset */ -#define RTC_C_CTL13_RDY ((uint16_t)0x0010) /*!< Real-time clock ready */ -/* RTC_C_CTL13[MODE] Bits */ -#define RTC_C_CTL13_MODE_OFS ( 5) /*!< RTCMODE Bit Offset */ -#define RTC_C_CTL13_MODE ((uint16_t)0x0020) -/* RTC_C_CTL13[HOLD] Bits */ -#define RTC_C_CTL13_HOLD_OFS ( 6) /*!< RTCHOLD Bit Offset */ -#define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /*!< Real-time clock hold */ -/* RTC_C_CTL13[BCD] Bits */ -#define RTC_C_CTL13_BCD_OFS ( 7) /*!< RTCBCD Bit Offset */ -#define RTC_C_CTL13_BCD ((uint16_t)0x0080) /*!< Real-time clock BCD select */ -/* RTC_C_CTL13[CALF] Bits */ -#define RTC_C_CTL13_CALF_OFS ( 8) /*!< RTCCALF Bit Offset */ -#define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /*!< RTCCALF Bit Mask */ -#define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /*!< CALF Bit 0 */ -#define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /*!< CALF Bit 1 */ -#define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /*!< 1 Hz */ -#define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /*!< 1 Hz */ -/* RTC_C_OCAL[OCAL] Bits */ -#define RTC_C_OCAL_OCAL_OFS ( 0) /*!< RTCOCAL Bit Offset */ -#define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /*!< RTCOCAL Bit Mask */ -/* RTC_C_OCAL[OCALS] Bits */ -#define RTC_C_OCAL_OCALS_OFS (15) /*!< RTCOCALS Bit Offset */ -#define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /*!< Real-time clock offset error calibration sign */ -/* RTC_C_TCMP[TCMPx] Bits */ -#define RTC_C_TCMP_TCMPX_OFS ( 0) /*!< RTCTCMP Bit Offset */ -#define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /*!< RTCTCMP Bit Mask */ -/* RTC_C_TCMP[TCOK] Bits */ -#define RTC_C_TCMP_TCOK_OFS (13) /*!< RTCTCOK Bit Offset */ -#define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /*!< Real-time clock temperature compensation write OK */ -/* RTC_C_TCMP[TCRDY] Bits */ -#define RTC_C_TCMP_TCRDY_OFS (14) /*!< RTCTCRDY Bit Offset */ -#define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /*!< Real-time clock temperature compensation ready */ -/* RTC_C_TCMP[TCMPS] Bits */ -#define RTC_C_TCMP_TCMPS_OFS (15) /*!< RTCTCMPS Bit Offset */ -#define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /*!< Real-time clock temperature compensation sign */ -/* RTC_C_PS0CTL[RT0PSIFG] Bits */ -#define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /*!< RT0PSIFG Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /*!< Prescale timer 0 interrupt flag */ -/* RTC_C_PS0CTL[RT0PSIE] Bits */ -#define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /*!< RT0PSIE Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /*!< Prescale timer 0 interrupt enable */ -/* RTC_C_PS0CTL[RT0IP] Bits */ -#define RTC_C_PS0CTL_RT0IP_OFS ( 2) /*!< RT0IP Bit Offset */ -#define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /*!< RT0IP Bit Mask */ -#define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /*!< RT0IP Bit 0 */ -#define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /*!< RT0IP Bit 1 */ -#define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /*!< RT0IP Bit 2 */ -#define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -/* RTC_C_PS1CTL[RT1PSIFG] Bits */ -#define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /*!< RT1PSIFG Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /*!< Prescale timer 1 interrupt flag */ -/* RTC_C_PS1CTL[RT1PSIE] Bits */ -#define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /*!< RT1PSIE Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /*!< Prescale timer 1 interrupt enable */ -/* RTC_C_PS1CTL[RT1IP] Bits */ -#define RTC_C_PS1CTL_RT1IP_OFS ( 2) /*!< RT1IP Bit Offset */ -#define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /*!< RT1IP Bit Mask */ -#define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /*!< RT1IP Bit 0 */ -#define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /*!< RT1IP Bit 1 */ -#define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /*!< RT1IP Bit 2 */ -#define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -/* RTC_C_PS[RT0PS] Bits */ -#define RTC_C_PS_RT0PS_OFS ( 0) /*!< RT0PS Bit Offset */ -#define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /*!< RT0PS Bit Mask */ -/* RTC_C_PS[RT1PS] Bits */ -#define RTC_C_PS_RT1PS_OFS ( 8) /*!< RT1PS Bit Offset */ -#define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /*!< RT1PS Bit Mask */ -/* RTC_C_TIM0[SEC] Bits */ -#define RTC_C_TIM0_SEC_OFS ( 0) /*!< Seconds Bit Offset */ -#define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /*!< Seconds Bit Mask */ -/* RTC_C_TIM0[MIN] Bits */ -#define RTC_C_TIM0_MIN_OFS ( 8) /*!< Minutes Bit Offset */ -#define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /*!< Minutes Bit Mask */ -/* RTC_C_TIM0[SEC_LD] Bits */ -#define RTC_C_TIM0_SEC_LD_OFS ( 0) /*!< SecondsLowDigit Bit Offset */ -#define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /*!< SecondsLowDigit Bit Mask */ -/* RTC_C_TIM0[SEC_HD] Bits */ -#define RTC_C_TIM0_SEC_HD_OFS ( 4) /*!< SecondsHighDigit Bit Offset */ -#define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /*!< SecondsHighDigit Bit Mask */ -/* RTC_C_TIM0[MIN_LD] Bits */ -#define RTC_C_TIM0_MIN_LD_OFS ( 8) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /*!< MinutesLowDigit Bit Mask */ -/* RTC_C_TIM0[MIN_HD] Bits */ -#define RTC_C_TIM0_MIN_HD_OFS (12) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /*!< MinutesHighDigit Bit Mask */ -/* RTC_C_TIM1[HOUR] Bits */ -#define RTC_C_TIM1_HOUR_OFS ( 0) /*!< Hours Bit Offset */ -#define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /*!< Hours Bit Mask */ -/* RTC_C_TIM1[DOW] Bits */ -#define RTC_C_TIM1_DOW_OFS ( 8) /*!< DayofWeek Bit Offset */ -#define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /*!< DayofWeek Bit Mask */ -/* RTC_C_TIM1[HOUR_LD] Bits */ -#define RTC_C_TIM1_HOUR_LD_OFS ( 0) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /*!< HoursLowDigit Bit Mask */ -/* RTC_C_TIM1[HOUR_HD] Bits */ -#define RTC_C_TIM1_HOUR_HD_OFS ( 4) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /*!< HoursHighDigit Bit Mask */ -/* RTC_C_DATE[DAY] Bits */ -#define RTC_C_DATE_DAY_OFS ( 0) /*!< Day Bit Offset */ -#define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /*!< Day Bit Mask */ -/* RTC_C_DATE[MON] Bits */ -#define RTC_C_DATE_MON_OFS ( 8) /*!< Month Bit Offset */ -#define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /*!< Month Bit Mask */ -/* RTC_C_DATE[DAY_LD] Bits */ -#define RTC_C_DATE_DAY_LD_OFS ( 0) /*!< DayLowDigit Bit Offset */ -#define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /*!< DayLowDigit Bit Mask */ -/* RTC_C_DATE[DAY_HD] Bits */ -#define RTC_C_DATE_DAY_HD_OFS ( 4) /*!< DayHighDigit Bit Offset */ -#define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /*!< DayHighDigit Bit Mask */ -/* RTC_C_DATE[MON_LD] Bits */ -#define RTC_C_DATE_MON_LD_OFS ( 8) /*!< MonthLowDigit Bit Offset */ -#define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /*!< MonthLowDigit Bit Mask */ -/* RTC_C_DATE[MON_HD] Bits */ -#define RTC_C_DATE_MON_HD_OFS (12) /*!< MonthHighDigit Bit Offset */ -#define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /*!< Month high digit (0 or 1) */ -/* RTC_C_YEAR[YEAR_LB] Bits */ -#define RTC_C_YEAR_YEAR_LB_OFS ( 0) /*!< YearLowByte Bit Offset */ -#define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /*!< YearLowByte Bit Mask */ -/* RTC_C_YEAR[YEAR_HB] Bits */ -#define RTC_C_YEAR_YEAR_HB_OFS ( 8) /*!< YearHighByte Bit Offset */ -#define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /*!< YearHighByte Bit Mask */ -/* RTC_C_YEAR[YEAR] Bits */ -#define RTC_C_YEAR_YEAR_OFS ( 0) /*!< Year Bit Offset */ -#define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /*!< Year Bit Mask */ -/* RTC_C_YEAR[DEC] Bits */ -#define RTC_C_YEAR_DEC_OFS ( 4) /*!< Decade Bit Offset */ -#define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /*!< Decade Bit Mask */ -/* RTC_C_YEAR[CENT_LD] Bits */ -#define RTC_C_YEAR_CENT_LD_OFS ( 8) /*!< CenturyLowDigit Bit Offset */ -#define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /*!< CenturyLowDigit Bit Mask */ -/* RTC_C_YEAR[CENT_HD] Bits */ -#define RTC_C_YEAR_CENT_HD_OFS (12) /*!< CenturyHighDigit Bit Offset */ -#define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /*!< CenturyHighDigit Bit Mask */ -/* RTC_C_AMINHR[MIN] Bits */ -#define RTC_C_AMINHR_MIN_OFS ( 0) /*!< Minutes Bit Offset */ -#define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /*!< Minutes Bit Mask */ -/* RTC_C_AMINHR[MINAE] Bits */ -#define RTC_C_AMINHR_MINAE_OFS ( 7) /*!< MINAE Bit Offset */ -#define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /*!< Alarm enable */ -/* RTC_C_AMINHR[HOUR] Bits */ -#define RTC_C_AMINHR_HOUR_OFS ( 8) /*!< Hours Bit Offset */ -#define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /*!< Hours Bit Mask */ -/* RTC_C_AMINHR[HOURAE] Bits */ -#define RTC_C_AMINHR_HOURAE_OFS (15) /*!< HOURAE Bit Offset */ -#define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /*!< Alarm enable */ -/* RTC_C_AMINHR[MIN_LD] Bits */ -#define RTC_C_AMINHR_MIN_LD_OFS ( 0) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /*!< MinutesLowDigit Bit Mask */ -/* RTC_C_AMINHR[MIN_HD] Bits */ -#define RTC_C_AMINHR_MIN_HD_OFS ( 4) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /*!< MinutesHighDigit Bit Mask */ -/* RTC_C_AMINHR[HOUR_LD] Bits */ -#define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /*!< HoursLowDigit Bit Mask */ -/* RTC_C_AMINHR[HOUR_HD] Bits */ -#define RTC_C_AMINHR_HOUR_HD_OFS (12) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /*!< HoursHighDigit Bit Mask */ -/* RTC_C_ADOWDAY[DOW] Bits */ -#define RTC_C_ADOWDAY_DOW_OFS ( 0) /*!< DayofWeek Bit Offset */ -#define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /*!< DayofWeek Bit Mask */ -/* RTC_C_ADOWDAY[DOWAE] Bits */ -#define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /*!< DOWAE Bit Offset */ -#define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /*!< Alarm enable */ -/* RTC_C_ADOWDAY[DAY] Bits */ -#define RTC_C_ADOWDAY_DAY_OFS ( 8) /*!< DayofMonth Bit Offset */ -#define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /*!< DayofMonth Bit Mask */ -/* RTC_C_ADOWDAY[DAYAE] Bits */ -#define RTC_C_ADOWDAY_DAYAE_OFS (15) /*!< DAYAE Bit Offset */ -#define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /*!< Alarm enable */ -/* RTC_C_ADOWDAY[DAY_LD] Bits */ -#define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /*!< DayLowDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /*!< DayLowDigit Bit Mask */ -/* RTC_C_ADOWDAY[DAY_HD] Bits */ -#define RTC_C_ADOWDAY_DAY_HD_OFS (12) /*!< DayHighDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /*!< DayHighDigit Bit Mask */ -/* Pre-defined bitfield values */ -#define RTC_C_KEY ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_H ((uint16_t)0x00A5) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_VAL ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ - - -/****************************************************************************** -* SCB Bits -******************************************************************************/ -/* SCB_PFR0[STATE0] Bits */ -#define SCB_PFR0_STATE0_OFS ( 0) /*!< STATE0 Bit Offset */ -#define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /*!< STATE0 Bit Mask */ -#define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /*!< STATE0 Bit 0 */ -#define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /*!< STATE0 Bit 1 */ -#define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /*!< STATE0 Bit 2 */ -#define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /*!< STATE0 Bit 3 */ -#define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /*!< no ARM encoding */ -#define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /*!< N/A */ -/* SCB_PFR0[STATE1] Bits */ -#define SCB_PFR0_STATE1_OFS ( 4) /*!< STATE1 Bit Offset */ -#define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /*!< STATE1 Bit Mask */ -#define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /*!< STATE1 Bit 0 */ -#define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /*!< STATE1 Bit 1 */ -#define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /*!< STATE1 Bit 2 */ -#define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /*!< STATE1 Bit 3 */ -#define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /*!< N/A */ -#define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /*!< N/A */ -#define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL */ - /* but no other 32-bit basic instructions (Note non-basic 32-bit instructions */ - /* can be added using the appropriate instruction attribute, but other 32-bit */ - /* basic instructions cannot.) */ -#define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /*!< Thumb-2 encoding with all Thumb-2 basic instructions */ -/* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /*!< two-stack support */ -/* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */ -/* SCB_MMFR0[PMSA_SUPPORT] Bits */ -#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /*!< PMSA_SUPPORT Bit Offset */ -#define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /*!< PMSA_SUPPORT Bit Mask */ -#define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /*!< PMSA_SUPPORT Bit 0 */ -#define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /*!< PMSA_SUPPORT Bit 1 */ -#define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /*!< PMSA_SUPPORT Bit 2 */ -#define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /*!< PMSA_SUPPORT Bit 3 */ -#define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /*!< IMPLEMENTATION DEFINED (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /*!< PMSA base (features as defined for ARMv6) (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /*!< PMSAv7 (base plus subregion support) */ -/* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /*!< CACHE_COHERENCE_SUPPORT Bit Offset */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /*!< CACHE_COHERENCE_SUPPORT Bit Mask */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /*!< CACHE_COHERENCE_SUPPORT Bit 0 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /*!< CACHE_COHERENCE_SUPPORT Bit 1 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /*!< CACHE_COHERENCE_SUPPORT Bit 2 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /*!< CACHE_COHERENCE_SUPPORT Bit 3 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /*!< no shared support */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /*!< partial-inner-shared coherency (coherency amongst some - but not all - of */ - /* the entities within an inner-coherent domain) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /*!< full-inner-shared coherency (coherency amongst all of the entities within an */ - /* inner-coherent domain) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /*!< full coherency (coherency amongst all of the entities) */ -/* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /*!< Outer non-sharable not supported */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /*!< Outer sharable supported */ -/* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /*!< Auxiliary control register */ -/* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /*!< wait for interrupt supported */ -/* SCB_ISAR0[BITCOUNT_INSTRS] Bits */ -#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /*!< BITCOUNT_INSTRS Bit Offset */ -#define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< BITCOUNT_INSTRS Bit Mask */ -#define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /*!< BITCOUNT_INSTRS Bit 0 */ -#define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /*!< BITCOUNT_INSTRS Bit 1 */ -#define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /*!< BITCOUNT_INSTRS Bit 2 */ -#define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /*!< BITCOUNT_INSTRS Bit 3 */ -#define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /*!< no bit-counting instructions present */ -#define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds CLZ */ -/* SCB_ISAR0[BITFIELD_INSTRS] Bits */ -#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /*!< BITFIELD_INSTRS Bit Offset */ -#define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /*!< BITFIELD_INSTRS Bit Mask */ -#define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /*!< BITFIELD_INSTRS Bit 0 */ -#define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /*!< BITFIELD_INSTRS Bit 1 */ -#define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /*!< BITFIELD_INSTRS Bit 2 */ -#define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /*!< BITFIELD_INSTRS Bit 3 */ -#define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /*!< no bitfield instructions present */ -#define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /*!< adds BFC, BFI, SBFX, UBFX */ -/* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /*!< CMPBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /*!< CMPBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /*!< CMPBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /*!< CMPBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /*!< CMPBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /*!< CMPBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no combined compare-and-branch instructions present */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /*!< adds CB{N}Z */ -/* SCB_ISAR0[COPROC_INSTRS] Bits */ -#define SCB_ISAR0_COPROC_INSTRS_OFS (16) /*!< COPROC_INSTRS Bit Offset */ -#define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /*!< COPROC_INSTRS Bit Mask */ -#define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /*!< COPROC_INSTRS Bit 0 */ -#define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /*!< COPROC_INSTRS Bit 1 */ -#define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /*!< COPROC_INSTRS Bit 2 */ -#define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /*!< COPROC_INSTRS Bit 3 */ -#define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /*!< no coprocessor support, other than for separately attributed architectures */ - /* such as CP15 or VFP */ -#define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /*!< adds generic CDP, LDC, MCR, MRC, STC */ -#define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */ -#define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /*!< adds generic MCRR, MRRC */ -#define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /*!< adds generic MCRR2, MRRC2 */ -/* SCB_ISAR0[DEBUG_INSTRS] Bits */ -#define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /*!< DEBUG_INSTRS Bit Offset */ -#define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /*!< DEBUG_INSTRS Bit Mask */ -#define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /*!< DEBUG_INSTRS Bit 0 */ -#define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /*!< DEBUG_INSTRS Bit 1 */ -#define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /*!< DEBUG_INSTRS Bit 2 */ -#define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /*!< DEBUG_INSTRS Bit 3 */ -#define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /*!< no debug instructions present */ -#define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /*!< adds BKPT */ -/* SCB_ISAR0[DIVIDE_INSTRS] Bits */ -#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /*!< DIVIDE_INSTRS Bit Offset */ -#define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /*!< DIVIDE_INSTRS Bit Mask */ -#define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /*!< DIVIDE_INSTRS Bit 0 */ -#define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /*!< DIVIDE_INSTRS Bit 1 */ -#define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /*!< DIVIDE_INSTRS Bit 2 */ -#define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /*!< DIVIDE_INSTRS Bit 3 */ -#define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /*!< no divide instructions present */ -#define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /*!< adds SDIV, UDIV (v1 quotient only result) */ -/* SCB_ISAR1[ETEND_INSRS] Bits */ -#define SCB_ISAR1_ETEND_INSRS_OFS (12) /*!< EXTEND_INSRS Bit Offset */ -#define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /*!< EXTEND_INSRS Bit Mask */ -#define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /*!< ETEND_INSRS Bit 0 */ -#define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /*!< ETEND_INSRS Bit 1 */ -#define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /*!< ETEND_INSRS Bit 2 */ -#define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /*!< ETEND_INSRS Bit 3 */ -#define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */ -#define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /*!< adds SXTB, SXTH, UXTB, UXTH */ -#define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /*!< N/A */ -/* SCB_ISAR1[IFTHEN_INSTRS] Bits */ -#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /*!< IFTHEN_INSTRS Bit Offset */ -#define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /*!< IFTHEN_INSTRS Bit Mask */ -#define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /*!< IFTHEN_INSTRS Bit 0 */ -#define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /*!< IFTHEN_INSTRS Bit 1 */ -#define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /*!< IFTHEN_INSTRS Bit 2 */ -#define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /*!< IFTHEN_INSTRS Bit 3 */ -#define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /*!< IT instructions not present */ -#define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /*!< adds IT instructions (and IT bits in PSRs) */ -/* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /*!< IMMEDIATE_INSTRS Bit Offset */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /*!< IMMEDIATE_INSTRS Bit Mask */ -#define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /*!< IMMEDIATE_INSTRS Bit 0 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /*!< IMMEDIATE_INSTRS Bit 1 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /*!< IMMEDIATE_INSTRS Bit 2 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /*!< IMMEDIATE_INSTRS Bit 3 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no special immediate-generating instructions present */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /*!< adds ADDW, MOVW, MOVT, SUBW */ -/* SCB_ISAR1[INTERWORK_INSTRS] Bits */ -#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /*!< INTERWORK_INSTRS Bit Offset */ -#define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /*!< INTERWORK_INSTRS Bit Mask */ -#define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /*!< INTERWORK_INSTRS Bit 0 */ -#define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /*!< INTERWORK_INSTRS Bit 1 */ -#define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /*!< INTERWORK_INSTRS Bit 2 */ -#define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /*!< INTERWORK_INSTRS Bit 3 */ -#define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /*!< no interworking instructions supported */ -#define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /*!< adds BX (and T bit in PSRs) */ -#define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /*!< adds BLX, and PC loads have BX-like behavior */ -#define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /*!< N/A */ -/* SCB_ISAR2[LOADSTORE_INSTRS] Bits */ -#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /*!< LOADSTORE_INSTRS Bit Offset */ -#define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< LOADSTORE_INSTRS Bit Mask */ -#define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /*!< LOADSTORE_INSTRS Bit 0 */ -#define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /*!< LOADSTORE_INSTRS Bit 1 */ -#define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /*!< LOADSTORE_INSTRS Bit 2 */ -#define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /*!< LOADSTORE_INSTRS Bit 3 */ -#define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /*!< no additional normal load/store instructions present */ -#define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRD/STRD */ -/* SCB_ISAR2[MEMHINT_INSTRS] Bits */ -#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /*!< MEMHINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< MEMHINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /*!< MEMHINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /*!< MEMHINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /*!< MEMHINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /*!< MEMHINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /*!< no memory hint instructions presen */ -#define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds PLD */ -#define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /*!< adds PLD (ie a repeat on value 1) */ -#define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /*!< adds PLI */ -/* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /*!< MULTIACCESSINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /*!< MULTIACCESSINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /*!< MULTIACCESSINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /*!< MULTIACCESSINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /*!< MULTIACCESSINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /*!< MULTIACCESSINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /*!< the (LDM/STM) instructions are non-interruptible */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /*!< the (LDM/STM) instructions are restartable */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /*!< the (LDM/STM) instructions are continuable */ -/* SCB_ISAR2[MULT_INSTRS] Bits */ -#define SCB_ISAR2_MULT_INSTRS_OFS (12) /*!< MULT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /*!< MULT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /*!< MULT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /*!< MULT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /*!< MULT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /*!< MULT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /*!< only MUL present */ -#define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /*!< adds MLA */ -#define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /*!< adds MLS */ -/* SCB_ISAR2[MULTS_INSTRS] Bits */ -#define SCB_ISAR2_MULTS_INSTRS_OFS (16) /*!< MULTS_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /*!< MULTS_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /*!< MULTS_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /*!< MULTS_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /*!< MULTS_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /*!< MULTS_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /*!< no signed multiply instructions present */ -#define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /*!< adds SMULL, SMLAL */ -#define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /*!< N/A */ -#define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /*!< N/A */ -/* SCB_ISAR2[MULTU_INSTRS] Bits */ -#define SCB_ISAR2_MULTU_INSTRS_OFS (20) /*!< MULTU_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /*!< MULTU_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /*!< MULTU_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /*!< MULTU_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /*!< MULTU_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /*!< MULTU_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /*!< no unsigned multiply instructions present */ -#define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /*!< adds UMULL, UMLAL */ -#define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /*!< N/A */ -/* SCB_ISAR2[REVERSAL_INSTRS] Bits */ -#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /*!< REVERSAL_INSTRS Bit Offset */ -#define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /*!< REVERSAL_INSTRS Bit Mask */ -#define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /*!< REVERSAL_INSTRS Bit 0 */ -#define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /*!< REVERSAL_INSTRS Bit 1 */ -#define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /*!< REVERSAL_INSTRS Bit 2 */ -#define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /*!< REVERSAL_INSTRS Bit 3 */ -#define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /*!< no reversal instructions present */ -#define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /*!< adds REV, REV16, REVSH */ -#define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /*!< adds RBIT */ -/* SCB_ISAR3[SATRUATE_INSTRS] Bits */ -#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /*!< SATRUATE_INSTRS Bit Offset */ -#define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< SATRUATE_INSTRS Bit Mask */ -#define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /*!< SATRUATE_INSTRS Bit 0 */ -#define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /*!< SATRUATE_INSTRS Bit 1 */ -#define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /*!< SATRUATE_INSTRS Bit 2 */ -#define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /*!< SATRUATE_INSTRS Bit 3 */ -#define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no non-SIMD saturate instructions present */ -#define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /*!< N/A */ -/* SCB_ISAR3[SIMD_INSTRS] Bits */ -#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /*!< SIMD_INSTRS Bit Offset */ -#define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /*!< SIMD_INSTRS Bit Mask */ -#define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /*!< SIMD_INSTRS Bit 0 */ -#define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /*!< SIMD_INSTRS Bit 1 */ -#define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /*!< SIMD_INSTRS Bit 2 */ -#define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /*!< SIMD_INSTRS Bit 3 */ -#define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /*!< no SIMD instructions present */ -#define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /*!< adds SSAT, USAT (and the Q flag in the PSRs) */ -#define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /*!< N/A */ -/* SCB_ISAR3[SVC_INSTRS] Bits */ -#define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /*!< SVC_INSTRS Bit Offset */ -#define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /*!< SVC_INSTRS Bit Mask */ -#define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /*!< SVC_INSTRS Bit 0 */ -#define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /*!< SVC_INSTRS Bit 1 */ -#define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /*!< SVC_INSTRS Bit 2 */ -#define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /*!< SVC_INSTRS Bit 3 */ -#define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /*!< no SVC (SWI) instructions present */ -#define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /*!< adds SVC (SWI) */ -/* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /*!< SYNCPRIM_INSTRS Bit Offset */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /*!< SYNCPRIM_INSTRS Bit Mask */ -#define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /*!< SYNCPRIM_INSTRS Bit 0 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /*!< SYNCPRIM_INSTRS Bit 1 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /*!< SYNCPRIM_INSTRS Bit 2 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /*!< SYNCPRIM_INSTRS Bit 3 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /*!< no synchronization primitives present */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /*!< adds LDREX, STREX */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */ -/* SCB_ISAR3[TABBRANCH_INSTRS] Bits */ -#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /*!< TABBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /*!< TABBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /*!< TABBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /*!< TABBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /*!< TABBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /*!< TABBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no table-branch instructions present */ -#define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /*!< adds TBB, TBH */ -/* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /*!< THUMBCOPY_INSTRS Bit Offset */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /*!< THUMBCOPY_INSTRS Bit Mask */ -#define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /*!< THUMBCOPY_INSTRS Bit 0 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /*!< THUMBCOPY_INSTRS Bit 1 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /*!< THUMBCOPY_INSTRS Bit 2 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /*!< THUMBCOPY_INSTRS Bit 3 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */ -/* SCB_ISAR3[TRUENOP_INSTRS] Bits */ -#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /*!< TRUENOP_INSTRS Bit Offset */ -#define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /*!< TRUENOP_INSTRS Bit Mask */ -#define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /*!< TRUENOP_INSTRS Bit 0 */ -#define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /*!< TRUENOP_INSTRS Bit 1 */ -#define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /*!< TRUENOP_INSTRS Bit 2 */ -#define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /*!< TRUENOP_INSTRS Bit 3 */ -#define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /*!< true NOP instructions not present - that is, NOP instructions with no */ - /* register dependencies */ -#define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */ -/* SCB_ISAR4[UNPRIV_INSTRS] Bits */ -#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /*!< UNPRIV_INSTRS Bit Offset */ -#define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /*!< UNPRIV_INSTRS Bit Mask */ -#define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /*!< UNPRIV_INSTRS Bit 0 */ -#define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /*!< UNPRIV_INSTRS Bit 1 */ -#define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /*!< UNPRIV_INSTRS Bit 2 */ -#define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /*!< UNPRIV_INSTRS Bit 3 */ -#define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /*!< no "T variant" instructions exist */ -#define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRBT, LDRT, STRBT, STRT */ -#define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */ -/* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /*!< WITHSHIFTS_INSTRS Bit Offset */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /*!< WITHSHIFTS_INSTRS Bit Mask */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /*!< WITHSHIFTS_INSTRS Bit 0 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /*!< WITHSHIFTS_INSTRS Bit 1 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /*!< WITHSHIFTS_INSTRS Bit 2 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /*!< WITHSHIFTS_INSTRS Bit 3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /*!< non-zero shifts only support MOV and shift instructions (see notes) */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /*!< shifts of loads/stores over the range LSL 0-3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /*!< adds other constant shift options. */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /*!< adds register-controlled shift options. */ -/* SCB_ISAR4[WRITEBACK_INSTRS] Bits */ -#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /*!< WRITEBACK_INSTRS Bit Offset */ -#define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /*!< WRITEBACK_INSTRS Bit Mask */ -#define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /*!< WRITEBACK_INSTRS Bit 0 */ -#define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /*!< WRITEBACK_INSTRS Bit 1 */ -#define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /*!< WRITEBACK_INSTRS Bit 2 */ -#define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /*!< WRITEBACK_INSTRS Bit 3 */ -#define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /*!< only non-writeback addressing modes present, except that */ - /* LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */ -#define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */ -/* SCB_ISAR4[BARRIER_INSTRS] Bits */ -#define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /*!< BARRIER_INSTRS Bit Offset */ -#define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /*!< BARRIER_INSTRS Bit Mask */ -#define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /*!< BARRIER_INSTRS Bit 0 */ -#define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /*!< BARRIER_INSTRS Bit 1 */ -#define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /*!< BARRIER_INSTRS Bit 2 */ -#define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /*!< BARRIER_INSTRS Bit 3 */ -#define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /*!< no barrier instructions supported */ -#define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /*!< adds DMB, DSB, ISB barrier instructions */ -/* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /*!< no additional support */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */ -/* SCB_ISAR4[PSR_M_INSTRS] Bits */ -#define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /*!< PSR_M_INSTRS Bit Offset */ -#define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /*!< PSR_M_INSTRS Bit Mask */ -#define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /*!< PSR_M_INSTRS Bit 0 */ -#define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /*!< PSR_M_INSTRS Bit 1 */ -#define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /*!< PSR_M_INSTRS Bit 2 */ -#define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /*!< PSR_M_INSTRS Bit 3 */ -#define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /*!< instructions not present */ -#define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */ -/* SCB_CPACR[CP11] Bits */ -#define SCB_CPACR_CP11_OFS (22) /*!< CP11 Bit Offset */ -#define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /*!< CP11 Bit Mask */ -/* SCB_CPACR[CP10] Bits */ -#define SCB_CPACR_CP10_OFS (20) /*!< CP10 Bit Offset */ -#define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /*!< CP10 Bit Mask */ -/* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */ -#define SCB_SHPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define SCB_SHPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */ -#define SCB_SHPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define SCB_SHPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */ -#define SCB_SHPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define SCB_SHPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */ -#define SCB_SHPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define SCB_SHPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */ -#define SCB_SHPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define SCB_SHPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */ -#define SCB_SHPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define SCB_SHPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */ -#define SCB_SHPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define SCB_SHPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */ -#define SCB_SHPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define SCB_SHPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */ -#define SCB_SHPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define SCB_SHPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */ -#define SCB_SHPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define SCB_SHPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */ -#define SCB_SHPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define SCB_SHPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */ -#define SCB_SHPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define SCB_SHPR3_PRI_15_M ((uint32_t)0xff000000) /* */ - -/* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */ -#define SCB_CFSR_IACCVIOL_OFS ( 0) /*!< IACCVIOL Offset */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /* */ -/* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */ -#define SCB_CFSR_DACCVIOL_OFS ( 1) /*!< DACCVIOL Offset */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /* */ -/* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */ -#define SCB_CFSR_MUNSTKERR_OFS ( 3) /*!< MUNSTKERR Offset */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /* */ -/* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */ -#define SCB_CFSR_MSTKERR_OFS ( 4) /*!< MSTKERR Offset */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /* */ -/* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */ -#define SCB_CFSR_MMARVALID_OFS ( 7) /*!< MMARVALID Offset */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /* */ -/* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */ -#define SCB_CFSR_IBUSERR_OFS ( 8) /*!< IBUSERR Offset */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /* */ -/* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */ -#define SCB_CFSR_PRECISERR_OFS ( 9) /*!< PRECISERR Offset */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /* */ -/* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */ -#define SCB_CFSR_IMPRECISERR_OFS (10) /*!< IMPRECISERR Offset */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /* */ -/* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */ -#define SCB_CFSR_UNSTKERR_OFS (11) /*!< UNSTKERR Offset */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /* */ -/* SCB_CFSR[SCB_CFSR_STKERR] Bits */ -#define SCB_CFSR_STKERR_OFS (12) /*!< STKERR Offset */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /* */ -/* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */ -#define SCB_CFSR_BFARVALID_OFS (15) /*!< BFARVALID Offset */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /* */ -/* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */ -#define SCB_CFSR_UNDEFINSTR_OFS (16) /*!< UNDEFINSTR Offset */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /* */ -/* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */ -#define SCB_CFSR_INVSTATE_OFS (17) /*!< INVSTATE Offset */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /* */ -/* SCB_CFSR[SCB_CFSR_INVPC] Bits */ -#define SCB_CFSR_INVPC_OFS (18) /*!< INVPC Offset */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /* */ -/* SCB_CFSR[SCB_CFSR_NOCP] Bits */ -#define SCB_CFSR_NOCP_OFS (19) /*!< NOCP Offset */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /* */ -/* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */ -#define SCB_CFSR_UNALIGNED_OFS (24) /*!< UNALIGNED Offset */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /* */ -/* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */ -#define SCB_CFSR_DIVBYZERO_OFS (25) /*!< DIVBYZERO Offset */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /* */ -/* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */ -#define SCB_CFSR_MLSPERR_OFS ( 5) /*!< MLSPERR Offset */ -#define SCB_CFSR_MLSPERR ((uint32_t)0x00000020) /* */ -/* SCB_CFSR[SCB_CFSR_LSPERR] Bits */ -#define SCB_CFSR_LSPERR_OFS (13) /*!< LSPERR Offset */ -#define SCB_CFSR_LSPERR ((uint32_t)0x00002000) /* */ - - -/****************************************************************************** -* SCNSCB Bits -******************************************************************************/ - - -/****************************************************************************** -* SYSCTL Bits -******************************************************************************/ -/* SYSCTL_REBOOT_CTL[REBOOT] Bits */ -#define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define SYSCTL_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /*!< Write 1 initiates a Reboot of the device */ -/* SYSCTL_REBOOT_CTL[WKEY] Bits */ -#define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -/* SYSCTL_NMI_CTLSTAT[CS_SRC] Bits */ -#define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /*!< CS_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /*!< CS interrupt as a source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PSS_SRC] Bits */ -#define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /*!< PSS_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /*!< PSS interrupt as a source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PCM_SRC] Bits */ -#define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /*!< PCM_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /*!< PCM interrupt as a source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PIN_SRC] Bits */ -#define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /*!< PIN_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008) -/* SYSCTL_NMI_CTLSTAT[CS_FLG] Bits */ -#define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /*!< CS_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /*!< CS interrupt was the source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PSS_FLG] Bits */ -#define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /*!< PSS_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /*!< PSS interrupt was the source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PCM_FLG] Bits */ -#define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /*!< PCM_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /*!< PCM interrupt was the source of NMI */ -/* SYSCTL_NMI_CTLSTAT[PIN_FLG] Bits */ -#define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /*!< PIN_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /*!< RSTn/NMI pin was the source of NMI */ -/* SYSCTL_WDTRESET_CTL[TIMEOUT] Bits */ -#define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /*!< TIMEOUT Bit Offset */ -#define SYSCTL_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /*!< WDT timeout reset type */ -/* SYSCTL_WDTRESET_CTL[VIOLATION] Bits */ -#define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /*!< VIOLATION Bit Offset */ -#define SYSCTL_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /*!< WDT password violation reset type */ -/* SYSCTL_PERIHALT_CTL[HALT_T16_0] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /*!< HALT_T16_0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_T16_1] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /*!< HALT_T16_1 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_T16_2] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /*!< HALT_T16_2 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_T16_3] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /*!< HALT_T16_3 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_T32_0] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /*!< HALT_T32_0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUA0] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /*!< HALT_eUA0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUA1] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /*!< HALT_eUA1 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUA2] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /*!< HALT_eUA2 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUA3] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /*!< HALT_eUA3 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUB0] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /*!< HALT_eUB0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUB1] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB1_OFS (10) /*!< HALT_eUB1 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUB2] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB2_OFS (11) /*!< HALT_eUB2 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_eUB3] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB3_OFS (12) /*!< HALT_eUB3 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_ADC] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_ADC_OFS (13) /*!< HALT_ADC Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_WDT] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_WDT_OFS (14) /*!< HALT_WDT Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_PERIHALT_CTL[HALT_DMA] Bits */ -#define SYSCTL_PERIHALT_CTL_HALT_DMA_OFS (15) /*!< HALT_DMA Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_SRAM_BANKEN[BNK0_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /*!< BNK0_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK0_EN ((uint32_t)0x00000001) /*!< SRAM Bank0 enable */ -/* SYSCTL_SRAM_BANKEN[BNK1_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /*!< BNK1_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK1_EN ((uint32_t)0x00000002) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK2_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /*!< BNK2_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK2_EN ((uint32_t)0x00000004) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK3_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /*!< BNK3_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK3_EN ((uint32_t)0x00000008) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK4_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /*!< BNK4_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK4_EN ((uint32_t)0x00000010) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK5_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /*!< BNK5_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK5_EN ((uint32_t)0x00000020) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK6_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /*!< BNK6_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK6_EN ((uint32_t)0x00000040) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[BNK7_EN] Bits */ -#define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /*!< BNK7_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK7_EN ((uint32_t)0x00000080) /*!< SRAM Bank1 enable */ -/* SYSCTL_SRAM_BANKEN[SRAM_RDY] Bits */ -#define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ -#define SYSCTL_SRAM_BANKEN_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ -/* SYSCTL_SRAM_BANKRET[BNK0_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /*!< BNK0_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK0_RET ((uint32_t)0x00000001) /*!< Bank0 retention */ -/* SYSCTL_SRAM_BANKRET[BNK1_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /*!< BNK1_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK1_RET ((uint32_t)0x00000002) /*!< Bank1 retention */ -/* SYSCTL_SRAM_BANKRET[BNK2_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /*!< BNK2_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK2_RET ((uint32_t)0x00000004) /*!< Bank2 retention */ -/* SYSCTL_SRAM_BANKRET[BNK3_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /*!< BNK3_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK3_RET ((uint32_t)0x00000008) /*!< Bank3 retention */ -/* SYSCTL_SRAM_BANKRET[BNK4_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /*!< BNK4_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK4_RET ((uint32_t)0x00000010) /*!< Bank4 retention */ -/* SYSCTL_SRAM_BANKRET[BNK5_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /*!< BNK5_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK5_RET ((uint32_t)0x00000020) /*!< Bank5 retention */ -/* SYSCTL_SRAM_BANKRET[BNK6_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /*!< BNK6_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK6_RET ((uint32_t)0x00000040) /*!< Bank6 retention */ -/* SYSCTL_SRAM_BANKRET[BNK7_RET] Bits */ -#define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /*!< BNK7_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK7_RET ((uint32_t)0x00000080) /*!< Bank7 retention */ -/* SYSCTL_SRAM_BANKRET[SRAM_RDY] Bits */ -#define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ -#define SYSCTL_SRAM_BANKRET_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ -/* SYSCTL_DIO_GLTFLT_CTL[GLTCH_EN] Bits */ -#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /*!< GLTCH_EN Bit Offset */ -#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /*!< Glitch filter enable */ -/* SYSCTL_SECDATA_UNLOCK[UNLKEY] Bits */ -#define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -/* SYSCTL_MASTER_UNLOCK[UNLKEY] Bits */ -#define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -/* SYSCTL_RESET_REQ[POR] Bits */ -#define SYSCTL_RESET_REQ_POR_OFS ( 0) /*!< POR Bit Offset */ -#define SYSCTL_RESET_REQ_POR ((uint32_t)0x00000001) /*!< Generate POR */ -/* SYSCTL_RESET_REQ[REBOOT] Bits */ -#define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /*!< REBOOT Bit Offset */ -#define SYSCTL_RESET_REQ_REBOOT ((uint32_t)0x00000002) /*!< Generate Reboot_Reset */ -/* SYSCTL_RESET_REQ[WKEY] Bits */ -#define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -/* SYSCTL_RESET_STATOVER[SOFT] Bits */ -#define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /*!< SOFT Bit Offset */ -#define SYSCTL_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /*!< Indicates if SOFT Reset is active */ -/* SYSCTL_RESET_STATOVER[HARD] Bits */ -#define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /*!< HARD Bit Offset */ -#define SYSCTL_RESET_STATOVER_HARD ((uint32_t)0x00000002) /*!< Indicates if HARD Reset is active */ -/* SYSCTL_RESET_STATOVER[REBOOT] Bits */ -#define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /*!< REBOOT Bit Offset */ -#define SYSCTL_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /*!< Indicates if Reboot Reset is active */ -/* SYSCTL_RESET_STATOVER[SOFT_OVER] Bits */ -#define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /*!< SOFT_OVER Bit Offset */ -#define SYSCTL_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /*!< SOFT_Reset overwrite request */ -/* SYSCTL_RESET_STATOVER[HARD_OVER] Bits */ -#define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /*!< HARD_OVER Bit Offset */ -#define SYSCTL_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /*!< HARD_Reset overwrite request */ -/* SYSCTL_RESET_STATOVER[RBT_OVER] Bits */ -#define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /*!< RBT_OVER Bit Offset */ -#define SYSCTL_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /*!< Reboot Reset overwrite request */ -/* Pre-defined bitfield values */ -#define SYSCTL_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bit 0 */ - /* cleared */ - - -/****************************************************************************** -* SYSTICK Bits -******************************************************************************/ - -/****************************************************************************** -* Timer32 Bits -******************************************************************************/ -/* TIMER32_CONTROL[ONESHOT] Bits */ -#define TIMER32_CONTROL_ONESHOT_OFS ( 0) /*!< ONESHOT Bit Offset */ -#define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /*!< Selects one-shot or wrapping counter mode */ -/* TIMER32_CONTROL[SIZE] Bits */ -#define TIMER32_CONTROL_SIZE_OFS ( 1) /*!< SIZE Bit Offset */ -#define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /*!< Selects 16 or 32 bit counter operation */ -/* TIMER32_CONTROL[PRESCALE] Bits */ -#define TIMER32_CONTROL_PRESCALE_OFS ( 2) /*!< PRESCALE Bit Offset */ -#define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /*!< PRESCALE Bit Mask */ -#define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /*!< PRESCALE Bit 0 */ -#define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /*!< PRESCALE Bit 1 */ -#define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /*!< 0 stages of prescale, clock is divided by 1 */ -#define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /*!< 4 stages of prescale, clock is divided by 16 */ -#define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /*!< 8 stages of prescale, clock is divided by 256 */ -/* TIMER32_CONTROL[IE] Bits */ -#define TIMER32_CONTROL_IE_OFS ( 5) /*!< IE Bit Offset */ -#define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /*!< Interrupt enable bit */ -/* TIMER32_CONTROL[MODE] Bits */ -#define TIMER32_CONTROL_MODE_OFS ( 6) /*!< MODE Bit Offset */ -#define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /*!< Mode bit */ -/* TIMER32_CONTROL[ENABLE] Bits */ -#define TIMER32_CONTROL_ENABLE_OFS ( 7) /*!< ENABLE Bit Offset */ -#define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080) -/* TIMER32_RIS[RAW_IFG] Bits */ -#define TIMER32_RIS_RAW_IFG_OFS ( 0) /*!< RAW_IFG Bit Offset */ -#define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /*!< Raw interrupt status */ -/* TIMER32_MIS[IFG] Bits */ -#define TIMER32_MIS_IFG_OFS ( 0) /*!< IFG Bit Offset */ -#define TIMER32_MIS_IFG ((uint32_t)0x00000001) /*!< Enabled interrupt status */ - - - -/****************************************************************************** -* TIMER_A Bits -******************************************************************************/ -/* TIMER_A_CTL[IFG] Bits */ -#define TIMER_A_CTL_IFG_OFS ( 0) /*!< TAIFG Bit Offset */ -#define TIMER_A_CTL_IFG ((uint16_t)0x0001) /*!< TimerA interrupt flag */ -/* TIMER_A_CTL[IE] Bits */ -#define TIMER_A_CTL_IE_OFS ( 1) /*!< TAIE Bit Offset */ -#define TIMER_A_CTL_IE ((uint16_t)0x0002) /*!< TimerA interrupt enable */ -/* TIMER_A_CTL[CLR] Bits */ -#define TIMER_A_CTL_CLR_OFS ( 2) /*!< TACLR Bit Offset */ -#define TIMER_A_CTL_CLR ((uint16_t)0x0004) /*!< TimerA clear */ -/* TIMER_A_CTL[MC] Bits */ -#define TIMER_A_CTL_MC_OFS ( 4) /*!< MC Bit Offset */ -#define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /*!< MC Bit Mask */ -#define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /*!< MC Bit 0 */ -#define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /*!< MC Bit 1 */ -#define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -#define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -/* TIMER_A_CTL[ID] Bits */ -#define TIMER_A_CTL_ID_OFS ( 6) /*!< ID Bit Offset */ -#define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /*!< ID Bit Mask */ -#define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /*!< ID Bit 0 */ -#define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /*!< ID Bit 1 */ -#define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /*!< /8 */ -#define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /*!< /8 */ -/* TIMER_A_CTL[SSEL] Bits */ -#define TIMER_A_CTL_SSEL_OFS ( 8) /*!< TASSEL Bit Offset */ -#define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /*!< TASSEL Bit Mask */ -#define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /*!< SSEL Bit 0 */ -#define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /*!< SSEL Bit 1 */ -#define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /*!< INCLK */ -#define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /*!< INCLK */ -/* TIMER_A_CCTLN[CCIFG] Bits */ -#define TIMER_A_CCTLN_CCIFG_OFS ( 0) /*!< CCIFG Bit Offset */ -#define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /*!< Capture/compare interrupt flag */ -/* TIMER_A_CCTLN[COV] Bits */ -#define TIMER_A_CCTLN_COV_OFS ( 1) /*!< COV Bit Offset */ -#define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /*!< Capture overflow */ -/* TIMER_A_CCTLN[OUT] Bits */ -#define TIMER_A_CCTLN_OUT_OFS ( 2) /*!< OUT Bit Offset */ -#define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /*!< Output */ -/* TIMER_A_CCTLN[CCI] Bits */ -#define TIMER_A_CCTLN_CCI_OFS ( 3) /*!< CCI Bit Offset */ -#define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /*!< Capture/compare input */ -/* TIMER_A_CCTLN[CCIE] Bits */ -#define TIMER_A_CCTLN_CCIE_OFS ( 4) /*!< CCIE Bit Offset */ -#define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /*!< Capture/compare interrupt enable */ -/* TIMER_A_CCTLN[OUTMOD] Bits */ -#define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /*!< OUTMOD Bit Offset */ -#define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /*!< OUTMOD Bit Mask */ -#define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /*!< OUTMOD Bit 0 */ -#define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /*!< OUTMOD Bit 1 */ -#define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /*!< OUTMOD Bit 2 */ -#define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /*!< OUT bit value */ -#define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /*!< Set */ -#define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /*!< Toggle/reset */ -#define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /*!< Set/reset */ -#define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /*!< Toggle */ -#define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /*!< Reset */ -#define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /*!< Toggle/set */ -#define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /*!< Reset/set */ -/* TIMER_A_CCTLN[CAP] Bits */ -#define TIMER_A_CCTLN_CAP_OFS ( 8) /*!< CAP Bit Offset */ -#define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /*!< Capture mode */ -/* TIMER_A_CCTLN[SCCI] Bits */ -#define TIMER_A_CCTLN_SCCI_OFS (10) /*!< SCCI Bit Offset */ -#define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /*!< Synchronized capture/compare input */ -/* TIMER_A_CCTLN[SCS] Bits */ -#define TIMER_A_CCTLN_SCS_OFS (11) /*!< SCS Bit Offset */ -#define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /*!< Synchronize capture source */ -/* TIMER_A_CCTLN[CCIS] Bits */ -#define TIMER_A_CCTLN_CCIS_OFS (12) /*!< CCIS Bit Offset */ -#define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /*!< CCIS Bit Mask */ -#define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /*!< CCIS Bit 0 */ -#define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /*!< CCIS Bit 1 */ -#define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /*!< VCC */ -#define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /*!< VCC */ -/* TIMER_A_CCTLN[CM] Bits */ -#define TIMER_A_CCTLN_CM_OFS (14) /*!< CM Bit Offset */ -#define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /*!< CM Bit Mask */ -#define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /*!< CM Bit 0 */ -#define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /*!< CM Bit 1 */ -#define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -#define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -/* TIMER_A_EX0[IDEX] Bits */ -#define TIMER_A_EX0_IDEX_OFS ( 0) /*!< TAIDEX Bit Offset */ -#define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /*!< TAIDEX Bit Mask */ -#define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /*!< IDEX Bit 0 */ -#define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /*!< IDEX Bit 1 */ -#define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /*!< IDEX Bit 2 */ -#define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /*!< Divide by 8 */ -#define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /*!< Divide by 8 */ - -/****************************************************************************** -* TLV Bits -******************************************************************************/ -/****************************************************************************** -* TLV table start and TLV tags * -******************************************************************************/ -#define TLV_START_ADDR (TLV_BASE + 0x0004) /*!< Start Address of the TLV structure */ - -#define TLV_TAG_RESERVED1 1 -#define TLV_TAG_RESERVED2 2 -#define TLV_TAG_CS 3 -#define TLV_TAG_FLASHCTL 4 -#define TLV_TAG_ADC14 5 -#define TLV_TAG_RESERVED6 6 -#define TLV_TAG_RESERVED7 7 -#define TLV_TAG_REF 8 -#define TLV_TAG_RESERVED9 9 -#define TLV_TAG_RESERVED10 10 -#define TLV_TAG_DEVINFO 11 -#define TLV_TAG_DIEREC 12 -#define TLV_TAG_RANDNUM 13 -#define TLV_TAG_RESERVED14 14 -#define TLV_TAG_BSL 15 -#define TLV_TAG_END (0x0BD0E11D) - - -/****************************************************************************** -* TPIU Bits -******************************************************************************/ - - -/****************************************************************************** -* WDT_A Bits -******************************************************************************/ -/* WDT_A_CTL[IS] Bits */ -#define WDT_A_CTL_IS_OFS ( 0) /*!< WDTIS Bit Offset */ -#define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /*!< WDTIS Bit Mask */ -#define WDT_A_CTL_IS0 ((uint16_t)0x0001) /*!< IS Bit 0 */ -#define WDT_A_CTL_IS1 ((uint16_t)0x0002) /*!< IS Bit 1 */ -#define WDT_A_CTL_IS2 ((uint16_t)0x0004) /*!< IS Bit 2 */ -#define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ -#define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ -/* WDT_A_CTL[CNTCL] Bits */ -#define WDT_A_CTL_CNTCL_OFS ( 3) /*!< WDTCNTCL Bit Offset */ -#define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /*!< Watchdog timer counter clear */ -/* WDT_A_CTL[TMSEL] Bits */ -#define WDT_A_CTL_TMSEL_OFS ( 4) /*!< WDTTMSEL Bit Offset */ -#define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /*!< Watchdog timer mode select */ -/* WDT_A_CTL[SSEL] Bits */ -#define WDT_A_CTL_SSEL_OFS ( 5) /*!< WDTSSEL Bit Offset */ -#define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /*!< WDTSSEL Bit Mask */ -#define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /*!< SSEL Bit 0 */ -#define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /*!< SSEL Bit 1 */ -#define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /*!< BCLK */ -#define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /*!< BCLK */ -/* WDT_A_CTL[HOLD] Bits */ -#define WDT_A_CTL_HOLD_OFS ( 7) /*!< WDTHOLD Bit Offset */ -#define WDT_A_CTL_HOLD ((uint16_t)0x0080) /*!< Watchdog timer hold */ -/* WDT_A_CTL[PW] Bits */ -#define WDT_A_CTL_PW_OFS ( 8) /*!< WDTPW Bit Offset */ -#define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /*!< WDTPW Bit Mask */ -/* Pre-defined bitfield values */ -#define WDT_A_CTL_PW ((uint16_t)0x5A00) /*!< WDT Key Value for WDT write access */ - - -/****************************************************************************** -* BSL * -******************************************************************************/ -#define BSL_DEFAULT_PARAM ((uint32_t)0xFC48FFFF) /*!< I2C slave address = 0x48, Interface selection = Auto */ -#define BSL_API_TABLE_ADDR ((uint32_t)0x00202000) /*!< Address of BSL API table */ -#define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR)) - -#define BSL_AUTO_INTERFACE ((uint32_t)0x0000E0000) /*!< Auto detect interface */ -#define BSL_UART_INTERFACE ((uint32_t)0x0000C0000) /*!< UART interface */ -#define BSL_SPI_INTERFACE ((uint32_t)0x0000A0000) /*!< SPI interface */ -#define BSL_I2C_INTERFACE ((uint32_t)0x000080000) /*!< I2C interface */ - -#define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */ - - -/****************************************************************************** -* Mailbox struct legacy definition * -******************************************************************************/ -#define FLASH_MAILBOX_Type FL_BOOTOVER_MAILBOX_Type - -/****************************************************************************** -* Device Unlock Support * -******************************************************************************/ -/* unlock the device by: - * Load SYSCTL_SECDATA_UNLOCK register address into R0 - * Load SYSCTL_SECDATA_UNLOCK unlock key into R1 - * Write the unlock key to the SYSCTL_SECDATA_UNLOCK register - */ -#define UNLOCK_DEVICE\ - __asm(" MOVW.W R0, #0x3040");\ - __asm(" MOVT.W R0, #0xE004");\ - __asm(" MOVW.W R1, #0x695A");\ - __asm(" MOVT.W R1, #0x0000");\ - __asm(" STR R1, [R0]"); - -/****************************************************************************** -* -* The following are values that can be used to choose the command that will be -* run by the boot code. Perform a logical OR of these settings to create your -* general parameter command. -* -******************************************************************************/ -#define COMMAND_FACTORY_RESET ((uint32_t)0x00010000) -#define COMMAND_BSL_CONFIG ((uint32_t)0x00020000) -#define COMMAND_JTAG_SWD_LOCK_SECEN ((uint32_t)0x00080000) -#define COMMAND_SEC_ZONE0_EN ((uint32_t)0x00100000) -#define COMMAND_SEC_ZONE1_EN ((uint32_t)0x00200000) -#define COMMAND_SEC_ZONE2_EN ((uint32_t)0x00400000) -#define COMMAND_SEC_ZONE3_EN ((uint32_t)0x00800000) -#define COMMAND_SEC_ZONE0_UPDATE ((uint32_t)0x01000000) -#define COMMAND_SEC_ZONE1_UPDATE ((uint32_t)0x02000000) -#define COMMAND_SEC_ZONE2_UPDATE ((uint32_t)0x04000000) -#define COMMAND_SEC_ZONE3_UPDATE ((uint32_t)0x08000000) -#define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE ((uint32_t)0x10000000) -#define COMMAND_NONE ((uint32_t)0xFFFFFFFF) - -/****************************************************************************** -* -* The following are values that can be used to configure the BSL. Perform a -* logical OR of these settings to create your BSL parameter. -* -******************************************************************************/ -#define BSL_CONFIG_HW_INVOKE ((uint32_t)0x70000000) - -#define BSL_CONFIG_HW_INVOKE_PORT1 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PORT2 ((uint32_t)0x00000001) -#define BSL_CONFIG_HW_INVOKE_PORT3 ((uint32_t)0x00000002) - -#define BSL_CONFIG_HW_INVOKE_PIN0 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN1 ((uint32_t)0x00000010) -#define BSL_CONFIG_HW_INVOKE_PIN2 ((uint32_t)0x00000020) -#define BSL_CONFIG_HW_INVOKE_PIN3 ((uint32_t)0x00000030) -#define BSL_CONFIG_HW_INVOKE_PIN4 ((uint32_t)0x00000040) -#define BSL_CONFIG_HW_INVOKE_PIN5 ((uint32_t)0x00000050) -#define BSL_CONFIG_HW_INVOKE_PIN6 ((uint32_t)0x00000060) -#define BSL_CONFIG_HW_INVOKE_PIN7 ((uint32_t)0x00000070) - -#define BSL_CONFIG_HW_INVOKE_PIN_LOW ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN_HIGH ((uint32_t)0x00001000) - -#define BSL_CONFIG_INTERFACE_I2C ((uint32_t)0x00008000) -#define BSL_CONFIG_INTERFACE_SPI ((uint32_t)0x0000A000) -#define BSL_CONFIG_INTERFACE_UART ((uint32_t)0x0000C000) -#define BSL_CONFIG_INTERFACE_AUTO ((uint32_t)0x0000E000) - -#define BSL_CONFIG_I2C_ADD_OFFSET (16) - - -/****************************************************************************** -* ULP Advisor * -******************************************************************************/ -#ifdef __TI_ARM__ -#pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8}) -#pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8}) -#pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8}) -#pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8}) -#pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8}) -#pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8}) -#pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8}) -#pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8}) -#pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8}) -#pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8}) -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* __MSP432P401R_H__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p401r_classic.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p401r_classic.h deleted file mode 100644 index 836d48b201b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p401r_classic.h +++ /dev/null @@ -1,3623 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432P401R Register Definitions -* -* This file includes MSP430 style component and register definitions -* for legacy components re-used in MSP432 -* -* File creation date: 2017-08-03 -* -******************************************************************************/ - -#ifndef __MSP432P401R_CLASSIC_H__ -#define __MSP432P401R_CLASSIC_H__ - -/* Use standard integer types with explicit width */ -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/****************************************************************************** -* Device memory map * -******************************************************************************/ -#define __MAIN_MEMORY_START__ (0x00000000) /*!< Main Flash memory start address */ -#define __MAIN_MEMORY_END__ (0x0003FFFF) /*!< Main Flash memory end address */ -#define __BSL_MEMORY_START__ (0x00202000) /*!< BSL memory start address */ -#define __BSL_MEMORY_END__ (0x00203FFF) /*!< BSL memory end address */ -#define __SRAM_START__ (0x20000000) /*!< SRAM memory start address */ -#define __SRAM_END__ (0x2000FFFF) /*!< SRAM memory end address */ - -/****************************************************************************** -* MSP-format peripheral registers * -******************************************************************************/ - -/****************************************************************************** -* AES256 Registers -******************************************************************************/ -#define AESACTL0 (HWREG16(0x40003C00)) /*!< AES Accelerator Control Register 0 */ -#define AESACTL1 (HWREG16(0x40003C02)) /*!< AES Accelerator Control Register 1 */ -#define AESASTAT (HWREG16(0x40003C04)) /*!< AES Accelerator Status Register */ -#define AESAKEY (HWREG16(0x40003C06)) /*!< AES Accelerator Key Register */ -#define AESADIN (HWREG16(0x40003C08)) /*!< AES Accelerator Data In Register */ -#define AESADOUT (HWREG16(0x40003C0A)) /*!< AES Accelerator Data Out Register */ -#define AESAXDIN (HWREG16(0x40003C0C)) /*!< AES Accelerator XORed Data In Register */ -#define AESAXIN (HWREG16(0x40003C0E)) /*!< AES Accelerator XORed Data In Register */ - -/* Register offsets from AES256_BASE address */ -#define OFS_AESACTL0 (0x0000) /*!< AES Accelerator Control Register 0 */ -#define OFS_AESACTL1 (0x0002) /*!< AES Accelerator Control Register 1 */ -#define OFS_AESASTAT (0x0004) /*!< AES Accelerator Status Register */ -#define OFS_AESAKEY (0x0006) /*!< AES Accelerator Key Register */ -#define OFS_AESADIN (0x0008) /*!< AES Accelerator Data In Register */ -#define OFS_AESADOUT (0x000A) /*!< AES Accelerator Data Out Register */ -#define OFS_AESAXDIN (0x000C) /*!< AES Accelerator XORed Data In Register */ -#define OFS_AESAXIN (0x000E) /*!< AES Accelerator XORed Data In Register */ - - -/****************************************************************************** -* CAPTIO0 Registers -******************************************************************************/ -#define CAPTIO0CTL (HWREG16(0x4000540E)) /*!< Capacitive Touch IO x Control Register */ - -/* Register offsets from CAPTIO0_BASE address */ -#define OFS_CAPTIO0CTL (0x000E) /*!< Capacitive Touch IO x Control Register */ - -#define CAPTIO0CTL_L (HWREG8_L(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */ -#define CAPTIO0CTL_H (HWREG8_H(CAPTIO0CTL))/* Capacitive Touch IO x Control Register */ - -/****************************************************************************** -* CAPTIO1 Registers -******************************************************************************/ -#define CAPTIO1CTL (HWREG16(0x4000580E)) /*!< Capacitive Touch IO x Control Register */ - -/* Register offsets from CAPTIO1_BASE address */ -#define OFS_CAPTIO1CTL (0x000E) /*!< Capacitive Touch IO x Control Register */ - -#define CAPTIO1CTL_L (HWREG8_L(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */ -#define CAPTIO1CTL_H (HWREG8_H(CAPTIO1CTL))/* Capacitive Touch IO x Control Register */ - -/****************************************************************************** -* COMP_E0 Registers -******************************************************************************/ -#define CE0CTL0 (HWREG16(0x40003400)) /*!< Comparator Control Register 0 */ -#define CE0CTL1 (HWREG16(0x40003402)) /*!< Comparator Control Register 1 */ -#define CE0CTL2 (HWREG16(0x40003404)) /*!< Comparator Control Register 2 */ -#define CE0CTL3 (HWREG16(0x40003406)) /*!< Comparator Control Register 3 */ -#define CE0INT (HWREG16(0x4000340C)) /*!< Comparator Interrupt Control Register */ -#define CE0IV (HWREG16(0x4000340E)) /*!< Comparator Interrupt Vector Word Register */ - -/* Register offsets from COMP_E0_BASE address */ -#define OFS_CE0CTL0 (0x0000) /*!< Comparator Control Register 0 */ -#define OFS_CE0CTL1 (0x0002) /*!< Comparator Control Register 1 */ -#define OFS_CE0CTL2 (0x0004) /*!< Comparator Control Register 2 */ -#define OFS_CE0CTL3 (0x0006) /*!< Comparator Control Register 3 */ -#define OFS_CE0INT (0x000C) /*!< Comparator Interrupt Control Register */ -#define OFS_CE0IV (0x000E) /*!< Comparator Interrupt Vector Word Register */ - - -/****************************************************************************** -* COMP_E1 Registers -******************************************************************************/ -#define CE1CTL0 (HWREG16(0x40003800)) /*!< Comparator Control Register 0 */ -#define CE1CTL1 (HWREG16(0x40003802)) /*!< Comparator Control Register 1 */ -#define CE1CTL2 (HWREG16(0x40003804)) /*!< Comparator Control Register 2 */ -#define CE1CTL3 (HWREG16(0x40003806)) /*!< Comparator Control Register 3 */ -#define CE1INT (HWREG16(0x4000380C)) /*!< Comparator Interrupt Control Register */ -#define CE1IV (HWREG16(0x4000380E)) /*!< Comparator Interrupt Vector Word Register */ - -/* Register offsets from COMP_E1_BASE address */ -#define OFS_CE1CTL0 (0x0000) /*!< Comparator Control Register 0 */ -#define OFS_CE1CTL1 (0x0002) /*!< Comparator Control Register 1 */ -#define OFS_CE1CTL2 (0x0004) /*!< Comparator Control Register 2 */ -#define OFS_CE1CTL3 (0x0006) /*!< Comparator Control Register 3 */ -#define OFS_CE1INT (0x000C) /*!< Comparator Interrupt Control Register */ -#define OFS_CE1IV (0x000E) /*!< Comparator Interrupt Vector Word Register */ - - -/****************************************************************************** -* CRC32 Registers -******************************************************************************/ -#define CRC32DI (HWREG16(0x40004000)) /*!< Data Input for CRC32 Signature Computation */ -#define CRC32DIRB (HWREG16(0x40004004)) /*!< Data In Reverse for CRC32 Computation */ -#define CRC32INIRES_LO (HWREG16(0x40004008)) /*!< CRC32 Initialization and Result, lower 16 bits */ -#define CRC32INIRES_HI (HWREG16(0x4000400A)) /*!< CRC32 Initialization and Result, upper 16 bits */ -#define CRC32RESR_LO (HWREG16(0x4000400C)) /*!< CRC32 Result Reverse, lower 16 bits */ -#define CRC32RESR_HI (HWREG16(0x4000400E)) /*!< CRC32 Result Reverse, Upper 16 bits */ -#define CRC16DI (HWREG16(0x40004010)) /*!< Data Input for CRC16 computation */ -#define CRC16DIRB (HWREG16(0x40004014)) /*!< CRC16 Data In Reverse */ -#define CRC16INIRES (HWREG16(0x40004018)) /*!< CRC16 Initialization and Result register */ -#define CRC16RESR (HWREG16(0x4000401E)) /*!< CRC16 Result Reverse */ - -/* Register offsets from CRC32_BASE address */ -#define OFS_CRC32DI (0x0000) /*!< Data Input for CRC32 Signature Computation */ -#define OFS_CRC32DIRB (0x0004) /*!< Data In Reverse for CRC32 Computation */ -#define OFS_CRC32INIRES_LO (0x0008) /*!< CRC32 Initialization and Result, lower 16 bits */ -#define OFS_CRC32INIRES_HI (0x000A) /*!< CRC32 Initialization and Result, upper 16 bits */ -#define OFS_CRC32RESR_LO (0x000C) /*!< CRC32 Result Reverse, lower 16 bits */ -#define OFS_CRC32RESR_HI (0x000E) /*!< CRC32 Result Reverse, Upper 16 bits */ -#define OFS_CRC16DI (0x0010) /*!< Data Input for CRC16 computation */ -#define OFS_CRC16DIRB (0x0014) /*!< CRC16 Data In Reverse */ -#define OFS_CRC16INIRES (0x0018) /*!< CRC16 Initialization and Result register */ -#define OFS_CRC16RESR (0x001E) /*!< CRC16 Result Reverse */ - - -/****************************************************************************** -* DIO Registers -******************************************************************************/ -#define PAIN (HWREG16(0x40004C00)) /*!< Port A Input */ -#define PAOUT (HWREG16(0x40004C02)) /*!< Port A Output */ -#define PADIR (HWREG16(0x40004C04)) /*!< Port A Direction */ -#define PAREN (HWREG16(0x40004C06)) /*!< Port A Resistor Enable */ -#define PADS (HWREG16(0x40004C08)) /*!< Port A Drive Strength */ -#define PASEL0 (HWREG16(0x40004C0A)) /*!< Port A Select 0 */ -#define PASEL1 (HWREG16(0x40004C0C)) /*!< Port A Select 1 */ -#define P1IV (HWREG16(0x40004C0E)) /*!< Port 1 Interrupt Vector Register */ -#define PASELC (HWREG16(0x40004C16)) /*!< Port A Complement Select */ -#define PAIES (HWREG16(0x40004C18)) /*!< Port A Interrupt Edge Select */ -#define PAIE (HWREG16(0x40004C1A)) /*!< Port A Interrupt Enable */ -#define PAIFG (HWREG16(0x40004C1C)) /*!< Port A Interrupt Flag */ -#define P2IV (HWREG16(0x40004C1E)) /*!< Port 2 Interrupt Vector Register */ -#define PBIN (HWREG16(0x40004C20)) /*!< Port B Input */ -#define PBOUT (HWREG16(0x40004C22)) /*!< Port B Output */ -#define PBDIR (HWREG16(0x40004C24)) /*!< Port B Direction */ -#define PBREN (HWREG16(0x40004C26)) /*!< Port B Resistor Enable */ -#define PBDS (HWREG16(0x40004C28)) /*!< Port B Drive Strength */ -#define PBSEL0 (HWREG16(0x40004C2A)) /*!< Port B Select 0 */ -#define PBSEL1 (HWREG16(0x40004C2C)) /*!< Port B Select 1 */ -#define P3IV (HWREG16(0x40004C2E)) /*!< Port 3 Interrupt Vector Register */ -#define PBSELC (HWREG16(0x40004C36)) /*!< Port B Complement Select */ -#define PBIES (HWREG16(0x40004C38)) /*!< Port B Interrupt Edge Select */ -#define PBIE (HWREG16(0x40004C3A)) /*!< Port B Interrupt Enable */ -#define PBIFG (HWREG16(0x40004C3C)) /*!< Port B Interrupt Flag */ -#define P4IV (HWREG16(0x40004C3E)) /*!< Port 4 Interrupt Vector Register */ -#define PCIN (HWREG16(0x40004C40)) /*!< Port C Input */ -#define PCOUT (HWREG16(0x40004C42)) /*!< Port C Output */ -#define PCDIR (HWREG16(0x40004C44)) /*!< Port C Direction */ -#define PCREN (HWREG16(0x40004C46)) /*!< Port C Resistor Enable */ -#define PCDS (HWREG16(0x40004C48)) /*!< Port C Drive Strength */ -#define PCSEL0 (HWREG16(0x40004C4A)) /*!< Port C Select 0 */ -#define PCSEL1 (HWREG16(0x40004C4C)) /*!< Port C Select 1 */ -#define P5IV (HWREG16(0x40004C4E)) /*!< Port 5 Interrupt Vector Register */ -#define PCSELC (HWREG16(0x40004C56)) /*!< Port C Complement Select */ -#define PCIES (HWREG16(0x40004C58)) /*!< Port C Interrupt Edge Select */ -#define PCIE (HWREG16(0x40004C5A)) /*!< Port C Interrupt Enable */ -#define PCIFG (HWREG16(0x40004C5C)) /*!< Port C Interrupt Flag */ -#define P6IV (HWREG16(0x40004C5E)) /*!< Port 6 Interrupt Vector Register */ -#define PDIN (HWREG16(0x40004C60)) /*!< Port D Input */ -#define PDOUT (HWREG16(0x40004C62)) /*!< Port D Output */ -#define PDDIR (HWREG16(0x40004C64)) /*!< Port D Direction */ -#define PDREN (HWREG16(0x40004C66)) /*!< Port D Resistor Enable */ -#define PDDS (HWREG16(0x40004C68)) /*!< Port D Drive Strength */ -#define PDSEL0 (HWREG16(0x40004C6A)) /*!< Port D Select 0 */ -#define PDSEL1 (HWREG16(0x40004C6C)) /*!< Port D Select 1 */ -#define P7IV (HWREG16(0x40004C6E)) /*!< Port 7 Interrupt Vector Register */ -#define PDSELC (HWREG16(0x40004C76)) /*!< Port D Complement Select */ -#define PDIES (HWREG16(0x40004C78)) /*!< Port D Interrupt Edge Select */ -#define PDIE (HWREG16(0x40004C7A)) /*!< Port D Interrupt Enable */ -#define PDIFG (HWREG16(0x40004C7C)) /*!< Port D Interrupt Flag */ -#define P8IV (HWREG16(0x40004C7E)) /*!< Port 8 Interrupt Vector Register */ -#define PEIN (HWREG16(0x40004C80)) /*!< Port E Input */ -#define PEOUT (HWREG16(0x40004C82)) /*!< Port E Output */ -#define PEDIR (HWREG16(0x40004C84)) /*!< Port E Direction */ -#define PEREN (HWREG16(0x40004C86)) /*!< Port E Resistor Enable */ -#define PEDS (HWREG16(0x40004C88)) /*!< Port E Drive Strength */ -#define PESEL0 (HWREG16(0x40004C8A)) /*!< Port E Select 0 */ -#define PESEL1 (HWREG16(0x40004C8C)) /*!< Port E Select 1 */ -#define P9IV (HWREG16(0x40004C8E)) /*!< Port 9 Interrupt Vector Register */ -#define PESELC (HWREG16(0x40004C96)) /*!< Port E Complement Select */ -#define PEIES (HWREG16(0x40004C98)) /*!< Port E Interrupt Edge Select */ -#define PEIE (HWREG16(0x40004C9A)) /*!< Port E Interrupt Enable */ -#define PEIFG (HWREG16(0x40004C9C)) /*!< Port E Interrupt Flag */ -#define P10IV (HWREG16(0x40004C9E)) /*!< Port 10 Interrupt Vector Register */ -#define PJIN (HWREG16(0x40004D20)) /*!< Port J Input */ -#define PJOUT (HWREG16(0x40004D22)) /*!< Port J Output */ -#define PJDIR (HWREG16(0x40004D24)) /*!< Port J Direction */ -#define PJREN (HWREG16(0x40004D26)) /*!< Port J Resistor Enable */ -#define PJDS (HWREG16(0x40004D28)) /*!< Port J Drive Strength */ -#define PJSEL0 (HWREG16(0x40004D2A)) /*!< Port J Select 0 */ -#define PJSEL1 (HWREG16(0x40004D2C)) /*!< Port J Select 1 */ -#define PJSELC (HWREG16(0x40004D36)) /*!< Port J Complement Select */ -#define P1IN (HWREG8(0x40004C00)) /*!< Port 1 Input */ -#define P2IN (HWREG8(0x40004C01)) /*!< Port 2 Input */ -#define P2OUT (HWREG8(0x40004C03)) /*!< Port 2 Output */ -#define P1OUT (HWREG8(0x40004C02)) /*!< Port 1 Output */ -#define P1DIR (HWREG8(0x40004C04)) /*!< Port 1 Direction */ -#define P2DIR (HWREG8(0x40004C05)) /*!< Port 2 Direction */ -#define P1REN (HWREG8(0x40004C06)) /*!< Port 1 Resistor Enable */ -#define P2REN (HWREG8(0x40004C07)) /*!< Port 2 Resistor Enable */ -#define P1DS (HWREG8(0x40004C08)) /*!< Port 1 Drive Strength */ -#define P2DS (HWREG8(0x40004C09)) /*!< Port 2 Drive Strength */ -#define P1SEL0 (HWREG8(0x40004C0A)) /*!< Port 1 Select 0 */ -#define P2SEL0 (HWREG8(0x40004C0B)) /*!< Port 2 Select 0 */ -#define P1SEL1 (HWREG8(0x40004C0C)) /*!< Port 1 Select 1 */ -#define P2SEL1 (HWREG8(0x40004C0D)) /*!< Port 2 Select 1 */ -#define P1SELC (HWREG8(0x40004C16)) /*!< Port 1 Complement Select */ -#define P2SELC (HWREG8(0x40004C17)) /*!< Port 2 Complement Select */ -#define P1IES (HWREG8(0x40004C18)) /*!< Port 1 Interrupt Edge Select */ -#define P2IES (HWREG8(0x40004C19)) /*!< Port 2 Interrupt Edge Select */ -#define P1IE (HWREG8(0x40004C1A)) /*!< Port 1 Interrupt Enable */ -#define P2IE (HWREG8(0x40004C1B)) /*!< Port 2 Interrupt Enable */ -#define P1IFG (HWREG8(0x40004C1C)) /*!< Port 1 Interrupt Flag */ -#define P2IFG (HWREG8(0x40004C1D)) /*!< Port 2 Interrupt Flag */ -#define P3IN (HWREG8(0x40004C20)) /*!< Port 3 Input */ -#define P4IN (HWREG8(0x40004C21)) /*!< Port 4 Input */ -#define P3OUT (HWREG8(0x40004C22)) /*!< Port 3 Output */ -#define P4OUT (HWREG8(0x40004C23)) /*!< Port 4 Output */ -#define P3DIR (HWREG8(0x40004C24)) /*!< Port 3 Direction */ -#define P4DIR (HWREG8(0x40004C25)) /*!< Port 4 Direction */ -#define P3REN (HWREG8(0x40004C26)) /*!< Port 3 Resistor Enable */ -#define P4REN (HWREG8(0x40004C27)) /*!< Port 4 Resistor Enable */ -#define P3DS (HWREG8(0x40004C28)) /*!< Port 3 Drive Strength */ -#define P4DS (HWREG8(0x40004C29)) /*!< Port 4 Drive Strength */ -#define P4SEL0 (HWREG8(0x40004C2B)) /*!< Port 4 Select 0 */ -#define P3SEL0 (HWREG8(0x40004C2A)) /*!< Port 3 Select 0 */ -#define P3SEL1 (HWREG8(0x40004C2C)) /*!< Port 3 Select 1 */ -#define P4SEL1 (HWREG8(0x40004C2D)) /*!< Port 4 Select 1 */ -#define P3SELC (HWREG8(0x40004C36)) /*!< Port 3 Complement Select */ -#define P4SELC (HWREG8(0x40004C37)) /*!< Port 4 Complement Select */ -#define P3IES (HWREG8(0x40004C38)) /*!< Port 3 Interrupt Edge Select */ -#define P4IES (HWREG8(0x40004C39)) /*!< Port 4 Interrupt Edge Select */ -#define P3IE (HWREG8(0x40004C3A)) /*!< Port 3 Interrupt Enable */ -#define P4IE (HWREG8(0x40004C3B)) /*!< Port 4 Interrupt Enable */ -#define P3IFG (HWREG8(0x40004C3C)) /*!< Port 3 Interrupt Flag */ -#define P4IFG (HWREG8(0x40004C3D)) /*!< Port 4 Interrupt Flag */ -#define P5IN (HWREG8(0x40004C40)) /*!< Port 5 Input */ -#define P6IN (HWREG8(0x40004C41)) /*!< Port 6 Input */ -#define P5OUT (HWREG8(0x40004C42)) /*!< Port 5 Output */ -#define P6OUT (HWREG8(0x40004C43)) /*!< Port 6 Output */ -#define P5DIR (HWREG8(0x40004C44)) /*!< Port 5 Direction */ -#define P6DIR (HWREG8(0x40004C45)) /*!< Port 6 Direction */ -#define P5REN (HWREG8(0x40004C46)) /*!< Port 5 Resistor Enable */ -#define P6REN (HWREG8(0x40004C47)) /*!< Port 6 Resistor Enable */ -#define P5DS (HWREG8(0x40004C48)) /*!< Port 5 Drive Strength */ -#define P6DS (HWREG8(0x40004C49)) /*!< Port 6 Drive Strength */ -#define P5SEL0 (HWREG8(0x40004C4A)) /*!< Port 5 Select 0 */ -#define P6SEL0 (HWREG8(0x40004C4B)) /*!< Port 6 Select 0 */ -#define P5SEL1 (HWREG8(0x40004C4C)) /*!< Port 5 Select 1 */ -#define P6SEL1 (HWREG8(0x40004C4D)) /*!< Port 6 Select 1 */ -#define P5SELC (HWREG8(0x40004C56)) /*!< Port 5 Complement Select */ -#define P6SELC (HWREG8(0x40004C57)) /*!< Port 6 Complement Select */ -#define P5IES (HWREG8(0x40004C58)) /*!< Port 5 Interrupt Edge Select */ -#define P6IES (HWREG8(0x40004C59)) /*!< Port 6 Interrupt Edge Select */ -#define P5IE (HWREG8(0x40004C5A)) /*!< Port 5 Interrupt Enable */ -#define P6IE (HWREG8(0x40004C5B)) /*!< Port 6 Interrupt Enable */ -#define P5IFG (HWREG8(0x40004C5C)) /*!< Port 5 Interrupt Flag */ -#define P6IFG (HWREG8(0x40004C5D)) /*!< Port 6 Interrupt Flag */ -#define P7IN (HWREG8(0x40004C60)) /*!< Port 7 Input */ -#define P8IN (HWREG8(0x40004C61)) /*!< Port 8 Input */ -#define P7OUT (HWREG8(0x40004C62)) /*!< Port 7 Output */ -#define P8OUT (HWREG8(0x40004C63)) /*!< Port 8 Output */ -#define P7DIR (HWREG8(0x40004C64)) /*!< Port 7 Direction */ -#define P8DIR (HWREG8(0x40004C65)) /*!< Port 8 Direction */ -#define P7REN (HWREG8(0x40004C66)) /*!< Port 7 Resistor Enable */ -#define P8REN (HWREG8(0x40004C67)) /*!< Port 8 Resistor Enable */ -#define P7DS (HWREG8(0x40004C68)) /*!< Port 7 Drive Strength */ -#define P8DS (HWREG8(0x40004C69)) /*!< Port 8 Drive Strength */ -#define P7SEL0 (HWREG8(0x40004C6A)) /*!< Port 7 Select 0 */ -#define P8SEL0 (HWREG8(0x40004C6B)) /*!< Port 8 Select 0 */ -#define P7SEL1 (HWREG8(0x40004C6C)) /*!< Port 7 Select 1 */ -#define P8SEL1 (HWREG8(0x40004C6D)) /*!< Port 8 Select 1 */ -#define P7SELC (HWREG8(0x40004C76)) /*!< Port 7 Complement Select */ -#define P8SELC (HWREG8(0x40004C77)) /*!< Port 8 Complement Select */ -#define P7IES (HWREG8(0x40004C78)) /*!< Port 7 Interrupt Edge Select */ -#define P8IES (HWREG8(0x40004C79)) /*!< Port 8 Interrupt Edge Select */ -#define P7IE (HWREG8(0x40004C7A)) /*!< Port 7 Interrupt Enable */ -#define P8IE (HWREG8(0x40004C7B)) /*!< Port 8 Interrupt Enable */ -#define P7IFG (HWREG8(0x40004C7C)) /*!< Port 7 Interrupt Flag */ -#define P8IFG (HWREG8(0x40004C7D)) /*!< Port 8 Interrupt Flag */ -#define P9IN (HWREG8(0x40004C80)) /*!< Port 9 Input */ -#define P10IN (HWREG8(0x40004C81)) /*!< Port 10 Input */ -#define P9OUT (HWREG8(0x40004C82)) /*!< Port 9 Output */ -#define P10OUT (HWREG8(0x40004C83)) /*!< Port 10 Output */ -#define P9DIR (HWREG8(0x40004C84)) /*!< Port 9 Direction */ -#define P10DIR (HWREG8(0x40004C85)) /*!< Port 10 Direction */ -#define P9REN (HWREG8(0x40004C86)) /*!< Port 9 Resistor Enable */ -#define P10REN (HWREG8(0x40004C87)) /*!< Port 10 Resistor Enable */ -#define P9DS (HWREG8(0x40004C88)) /*!< Port 9 Drive Strength */ -#define P10DS (HWREG8(0x40004C89)) /*!< Port 10 Drive Strength */ -#define P9SEL0 (HWREG8(0x40004C8A)) /*!< Port 9 Select 0 */ -#define P10SEL0 (HWREG8(0x40004C8B)) /*!< Port 10 Select 0 */ -#define P9SEL1 (HWREG8(0x40004C8C)) /*!< Port 9 Select 1 */ -#define P10SEL1 (HWREG8(0x40004C8D)) /*!< Port 10 Select 1 */ -#define P9SELC (HWREG8(0x40004C96)) /*!< Port 9 Complement Select */ -#define P10SELC (HWREG8(0x40004C97)) /*!< Port 10 Complement Select */ -#define P9IES (HWREG8(0x40004C98)) /*!< Port 9 Interrupt Edge Select */ -#define P10IES (HWREG8(0x40004C99)) /*!< Port 10 Interrupt Edge Select */ -#define P9IE (HWREG8(0x40004C9A)) /*!< Port 9 Interrupt Enable */ -#define P10IE (HWREG8(0x40004C9B)) /*!< Port 10 Interrupt Enable */ -#define P9IFG (HWREG8(0x40004C9C)) /*!< Port 9 Interrupt Flag */ -#define P10IFG (HWREG8(0x40004C9D)) /*!< Port 10 Interrupt Flag */ - -/* Register offsets from DIO_BASE address */ -#define OFS_PAIN (0x0000) /*!< Port A Input */ -#define OFS_PAOUT (0x0002) /*!< Port A Output */ -#define OFS_PADIR (0x0004) /*!< Port A Direction */ -#define OFS_PAREN (0x0006) /*!< Port A Resistor Enable */ -#define OFS_PADS (0x0008) /*!< Port A Drive Strength */ -#define OFS_PASEL0 (0x000A) /*!< Port A Select 0 */ -#define OFS_PASEL1 (0x000C) /*!< Port A Select 1 */ -#define OFS_P1IV (0x000E) /*!< Port 1 Interrupt Vector Register */ -#define OFS_PASELC (0x0016) /*!< Port A Complement Select */ -#define OFS_PAIES (0x0018) /*!< Port A Interrupt Edge Select */ -#define OFS_PAIE (0x001A) /*!< Port A Interrupt Enable */ -#define OFS_PAIFG (0x001C) /*!< Port A Interrupt Flag */ -#define OFS_P2IV (0x001E) /*!< Port 2 Interrupt Vector Register */ -#define OFS_PBIN (0x0020) /*!< Port B Input */ -#define OFS_PBOUT (0x0022) /*!< Port B Output */ -#define OFS_PBDIR (0x0024) /*!< Port B Direction */ -#define OFS_PBREN (0x0026) /*!< Port B Resistor Enable */ -#define OFS_PBDS (0x0028) /*!< Port B Drive Strength */ -#define OFS_PBSEL0 (0x002A) /*!< Port B Select 0 */ -#define OFS_PBSEL1 (0x002C) /*!< Port B Select 1 */ -#define OFS_P3IV (0x002E) /*!< Port 3 Interrupt Vector Register */ -#define OFS_PBSELC (0x0036) /*!< Port B Complement Select */ -#define OFS_PBIES (0x0038) /*!< Port B Interrupt Edge Select */ -#define OFS_PBIE (0x003A) /*!< Port B Interrupt Enable */ -#define OFS_PBIFG (0x003C) /*!< Port B Interrupt Flag */ -#define OFS_P4IV (0x003E) /*!< Port 4 Interrupt Vector Register */ -#define OFS_PCIN (0x0040) /*!< Port C Input */ -#define OFS_PCOUT (0x0042) /*!< Port C Output */ -#define OFS_PCDIR (0x0044) /*!< Port C Direction */ -#define OFS_PCREN (0x0046) /*!< Port C Resistor Enable */ -#define OFS_PCDS (0x0048) /*!< Port C Drive Strength */ -#define OFS_PCSEL0 (0x004A) /*!< Port C Select 0 */ -#define OFS_PCSEL1 (0x004C) /*!< Port C Select 1 */ -#define OFS_P5IV (0x004E) /*!< Port 5 Interrupt Vector Register */ -#define OFS_PCSELC (0x0056) /*!< Port C Complement Select */ -#define OFS_PCIES (0x0058) /*!< Port C Interrupt Edge Select */ -#define OFS_PCIE (0x005A) /*!< Port C Interrupt Enable */ -#define OFS_PCIFG (0x005C) /*!< Port C Interrupt Flag */ -#define OFS_P6IV (0x005E) /*!< Port 6 Interrupt Vector Register */ -#define OFS_PDIN (0x0060) /*!< Port D Input */ -#define OFS_PDOUT (0x0062) /*!< Port D Output */ -#define OFS_PDDIR (0x0064) /*!< Port D Direction */ -#define OFS_PDREN (0x0066) /*!< Port D Resistor Enable */ -#define OFS_PDDS (0x0068) /*!< Port D Drive Strength */ -#define OFS_PDSEL0 (0x006A) /*!< Port D Select 0 */ -#define OFS_PDSEL1 (0x006C) /*!< Port D Select 1 */ -#define OFS_P7IV (0x006E) /*!< Port 7 Interrupt Vector Register */ -#define OFS_PDSELC (0x0076) /*!< Port D Complement Select */ -#define OFS_PDIES (0x0078) /*!< Port D Interrupt Edge Select */ -#define OFS_PDIE (0x007A) /*!< Port D Interrupt Enable */ -#define OFS_PDIFG (0x007C) /*!< Port D Interrupt Flag */ -#define OFS_P8IV (0x007E) /*!< Port 8 Interrupt Vector Register */ -#define OFS_PEIN (0x0080) /*!< Port E Input */ -#define OFS_PEOUT (0x0082) /*!< Port E Output */ -#define OFS_PEDIR (0x0084) /*!< Port E Direction */ -#define OFS_PEREN (0x0086) /*!< Port E Resistor Enable */ -#define OFS_PEDS (0x0088) /*!< Port E Drive Strength */ -#define OFS_PESEL0 (0x008A) /*!< Port E Select 0 */ -#define OFS_PESEL1 (0x008C) /*!< Port E Select 1 */ -#define OFS_P9IV (0x008E) /*!< Port 9 Interrupt Vector Register */ -#define OFS_PESELC (0x0096) /*!< Port E Complement Select */ -#define OFS_PEIES (0x0098) /*!< Port E Interrupt Edge Select */ -#define OFS_PEIE (0x009A) /*!< Port E Interrupt Enable */ -#define OFS_PEIFG (0x009C) /*!< Port E Interrupt Flag */ -#define OFS_P10IV (0x009E) /*!< Port 10 Interrupt Vector Register */ -#define OFS_PJIN (0x0120) /*!< Port J Input */ -#define OFS_PJOUT (0x0122) /*!< Port J Output */ -#define OFS_PJDIR (0x0124) /*!< Port J Direction */ -#define OFS_PJREN (0x0126) /*!< Port J Resistor Enable */ -#define OFS_PJDS (0x0128) /*!< Port J Drive Strength */ -#define OFS_PJSEL0 (0x012A) /*!< Port J Select 0 */ -#define OFS_PJSEL1 (0x012C) /*!< Port J Select 1 */ -#define OFS_PJSELC (0x0136) /*!< Port J Complement Select */ -#define OFS_P1IN (0x0000) /*!< Port 1 Input */ -#define OFS_P2IN (0x0001) /*!< Port 2 Input */ -#define OFS_P2OUT (0x0003) /*!< Port 2 Output */ -#define OFS_P1OUT (0x0002) /*!< Port 1 Output */ -#define OFS_P1DIR (0x0004) /*!< Port 1 Direction */ -#define OFS_P2DIR (0x0005) /*!< Port 2 Direction */ -#define OFS_P1REN (0x0006) /*!< Port 1 Resistor Enable */ -#define OFS_P2REN (0x0007) /*!< Port 2 Resistor Enable */ -#define OFS_P1DS (0x0008) /*!< Port 1 Drive Strength */ -#define OFS_P2DS (0x0009) /*!< Port 2 Drive Strength */ -#define OFS_P1SEL0 (0x000A) /*!< Port 1 Select 0 */ -#define OFS_P2SEL0 (0x000B) /*!< Port 2 Select 0 */ -#define OFS_P1SEL1 (0x000C) /*!< Port 1 Select 1 */ -#define OFS_P2SEL1 (0x000D) /*!< Port 2 Select 1 */ -#define OFS_P1SELC (0x0016) /*!< Port 1 Complement Select */ -#define OFS_P2SELC (0x0017) /*!< Port 2 Complement Select */ -#define OFS_P1IES (0x0018) /*!< Port 1 Interrupt Edge Select */ -#define OFS_P2IES (0x0019) /*!< Port 2 Interrupt Edge Select */ -#define OFS_P1IE (0x001A) /*!< Port 1 Interrupt Enable */ -#define OFS_P2IE (0x001B) /*!< Port 2 Interrupt Enable */ -#define OFS_P1IFG (0x001C) /*!< Port 1 Interrupt Flag */ -#define OFS_P2IFG (0x001D) /*!< Port 2 Interrupt Flag */ -#define OFS_P3IN (0x0020) /*!< Port 3 Input */ -#define OFS_P4IN (0x0021) /*!< Port 4 Input */ -#define OFS_P3OUT (0x0022) /*!< Port 3 Output */ -#define OFS_P4OUT (0x0023) /*!< Port 4 Output */ -#define OFS_P3DIR (0x0024) /*!< Port 3 Direction */ -#define OFS_P4DIR (0x0025) /*!< Port 4 Direction */ -#define OFS_P3REN (0x0026) /*!< Port 3 Resistor Enable */ -#define OFS_P4REN (0x0027) /*!< Port 4 Resistor Enable */ -#define OFS_P3DS (0x0028) /*!< Port 3 Drive Strength */ -#define OFS_P4DS (0x0029) /*!< Port 4 Drive Strength */ -#define OFS_P4SEL0 (0x002B) /*!< Port 4 Select 0 */ -#define OFS_P3SEL0 (0x002A) /*!< Port 3 Select 0 */ -#define OFS_P3SEL1 (0x002C) /*!< Port 3 Select 1 */ -#define OFS_P4SEL1 (0x002D) /*!< Port 4 Select 1 */ -#define OFS_P3SELC (0x0036) /*!< Port 3 Complement Select */ -#define OFS_P4SELC (0x0037) /*!< Port 4 Complement Select */ -#define OFS_P3IES (0x0038) /*!< Port 3 Interrupt Edge Select */ -#define OFS_P4IES (0x0039) /*!< Port 4 Interrupt Edge Select */ -#define OFS_P3IE (0x003A) /*!< Port 3 Interrupt Enable */ -#define OFS_P4IE (0x003B) /*!< Port 4 Interrupt Enable */ -#define OFS_P3IFG (0x003C) /*!< Port 3 Interrupt Flag */ -#define OFS_P4IFG (0x003D) /*!< Port 4 Interrupt Flag */ -#define OFS_P5IN (0x0040) /*!< Port 5 Input */ -#define OFS_P6IN (0x0041) /*!< Port 6 Input */ -#define OFS_P5OUT (0x0042) /*!< Port 5 Output */ -#define OFS_P6OUT (0x0043) /*!< Port 6 Output */ -#define OFS_P5DIR (0x0044) /*!< Port 5 Direction */ -#define OFS_P6DIR (0x0045) /*!< Port 6 Direction */ -#define OFS_P5REN (0x0046) /*!< Port 5 Resistor Enable */ -#define OFS_P6REN (0x0047) /*!< Port 6 Resistor Enable */ -#define OFS_P5DS (0x0048) /*!< Port 5 Drive Strength */ -#define OFS_P6DS (0x0049) /*!< Port 6 Drive Strength */ -#define OFS_P5SEL0 (0x004A) /*!< Port 5 Select 0 */ -#define OFS_P6SEL0 (0x004B) /*!< Port 6 Select 0 */ -#define OFS_P5SEL1 (0x004C) /*!< Port 5 Select 1 */ -#define OFS_P6SEL1 (0x004D) /*!< Port 6 Select 1 */ -#define OFS_P5SELC (0x0056) /*!< Port 5 Complement Select */ -#define OFS_P6SELC (0x0057) /*!< Port 6 Complement Select */ -#define OFS_P5IES (0x0058) /*!< Port 5 Interrupt Edge Select */ -#define OFS_P6IES (0x0059) /*!< Port 6 Interrupt Edge Select */ -#define OFS_P5IE (0x005A) /*!< Port 5 Interrupt Enable */ -#define OFS_P6IE (0x005B) /*!< Port 6 Interrupt Enable */ -#define OFS_P5IFG (0x005C) /*!< Port 5 Interrupt Flag */ -#define OFS_P6IFG (0x005D) /*!< Port 6 Interrupt Flag */ -#define OFS_P7IN (0x0060) /*!< Port 7 Input */ -#define OFS_P8IN (0x0061) /*!< Port 8 Input */ -#define OFS_P7OUT (0x0062) /*!< Port 7 Output */ -#define OFS_P8OUT (0x0063) /*!< Port 8 Output */ -#define OFS_P7DIR (0x0064) /*!< Port 7 Direction */ -#define OFS_P8DIR (0x0065) /*!< Port 8 Direction */ -#define OFS_P7REN (0x0066) /*!< Port 7 Resistor Enable */ -#define OFS_P8REN (0x0067) /*!< Port 8 Resistor Enable */ -#define OFS_P7DS (0x0068) /*!< Port 7 Drive Strength */ -#define OFS_P8DS (0x0069) /*!< Port 8 Drive Strength */ -#define OFS_P7SEL0 (0x006A) /*!< Port 7 Select 0 */ -#define OFS_P8SEL0 (0x006B) /*!< Port 8 Select 0 */ -#define OFS_P7SEL1 (0x006C) /*!< Port 7 Select 1 */ -#define OFS_P8SEL1 (0x006D) /*!< Port 8 Select 1 */ -#define OFS_P7SELC (0x0076) /*!< Port 7 Complement Select */ -#define OFS_P8SELC (0x0077) /*!< Port 8 Complement Select */ -#define OFS_P7IES (0x0078) /*!< Port 7 Interrupt Edge Select */ -#define OFS_P8IES (0x0079) /*!< Port 8 Interrupt Edge Select */ -#define OFS_P7IE (0x007A) /*!< Port 7 Interrupt Enable */ -#define OFS_P8IE (0x007B) /*!< Port 8 Interrupt Enable */ -#define OFS_P7IFG (0x007C) /*!< Port 7 Interrupt Flag */ -#define OFS_P8IFG (0x007D) /*!< Port 8 Interrupt Flag */ -#define OFS_P9IN (0x0080) /*!< Port 9 Input */ -#define OFS_P10IN (0x0081) /*!< Port 10 Input */ -#define OFS_P9OUT (0x0082) /*!< Port 9 Output */ -#define OFS_P10OUT (0x0083) /*!< Port 10 Output */ -#define OFS_P9DIR (0x0084) /*!< Port 9 Direction */ -#define OFS_P10DIR (0x0085) /*!< Port 10 Direction */ -#define OFS_P9REN (0x0086) /*!< Port 9 Resistor Enable */ -#define OFS_P10REN (0x0087) /*!< Port 10 Resistor Enable */ -#define OFS_P9DS (0x0088) /*!< Port 9 Drive Strength */ -#define OFS_P10DS (0x0089) /*!< Port 10 Drive Strength */ -#define OFS_P9SEL0 (0x008A) /*!< Port 9 Select 0 */ -#define OFS_P10SEL0 (0x008B) /*!< Port 10 Select 0 */ -#define OFS_P9SEL1 (0x008C) /*!< Port 9 Select 1 */ -#define OFS_P10SEL1 (0x008D) /*!< Port 10 Select 1 */ -#define OFS_P9SELC (0x0096) /*!< Port 9 Complement Select */ -#define OFS_P10SELC (0x0097) /*!< Port 10 Complement Select */ -#define OFS_P9IES (0x0098) /*!< Port 9 Interrupt Edge Select */ -#define OFS_P10IES (0x0099) /*!< Port 10 Interrupt Edge Select */ -#define OFS_P9IE (0x009A) /*!< Port 9 Interrupt Enable */ -#define OFS_P10IE (0x009B) /*!< Port 10 Interrupt Enable */ -#define OFS_P9IFG (0x009C) /*!< Port 9 Interrupt Flag */ -#define OFS_P10IFG (0x009D) /*!< Port 10 Interrupt Flag */ - - -/****************************************************************************** -* EUSCI_A0 Registers -******************************************************************************/ -#define UCA0CTLW0 (HWREG16(0x40001000)) /*!< eUSCI_Ax Control Word Register 0 */ -#define UCA0CTLW0_SPI (HWREG16(0x40001000)) -#define UCA0CTLW1 (HWREG16(0x40001002)) /*!< eUSCI_Ax Control Word Register 1 */ -#define UCA0BRW (HWREG16(0x40001006)) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define UCA0BRW_SPI (HWREG16(0x40001006)) -#define UCA0MCTLW (HWREG16(0x40001008)) /*!< eUSCI_Ax Modulation Control Word Register */ -#define UCA0STATW (HWREG16(0x4000100A)) /*!< eUSCI_Ax Status Register */ -#define UCA0STATW_SPI (HWREG16(0x4000100A)) -#define UCA0RXBUF (HWREG16(0x4000100C)) /*!< eUSCI_Ax Receive Buffer Register */ -#define UCA0RXBUF_SPI (HWREG16(0x4000100C)) -#define UCA0TXBUF (HWREG16(0x4000100E)) /*!< eUSCI_Ax Transmit Buffer Register */ -#define UCA0TXBUF_SPI (HWREG16(0x4000100E)) -#define UCA0ABCTL (HWREG16(0x40001010)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define UCA0IRCTL (HWREG16(0x40001012)) /*!< eUSCI_Ax IrDA Control Word Register */ -#define UCA0IE (HWREG16(0x4000101A)) /*!< eUSCI_Ax Interrupt Enable Register */ -#define UCA0IE_SPI (HWREG16(0x4000101A)) -#define UCA0IFG (HWREG16(0x4000101C)) /*!< eUSCI_Ax Interrupt Flag Register */ -#define UCA0IFG_SPI (HWREG16(0x4000101C)) -#define UCA0IV (HWREG16(0x4000101E)) /*!< eUSCI_Ax Interrupt Vector Register */ -#define UCA0IV_SPI (HWREG16(0x4000101E)) - -/* Register offsets from EUSCI_A0_BASE address */ -#define OFS_UCA0CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ -#define OFS_UCA0CTLW0_SPI (0x0000) -#define OFS_UCA0CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ -#define OFS_UCA0BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define OFS_UCA0BRW_SPI (0x0006) -#define OFS_UCA0MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ -#define OFS_UCA0STATW (0x000A) /*!< eUSCI_Ax Status Register */ -#define OFS_UCA0STATW_SPI (0x000A) -#define OFS_UCA0RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ -#define OFS_UCA0RXBUF_SPI (0x000C) -#define OFS_UCA0TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ -#define OFS_UCA0TXBUF_SPI (0x000E) -#define OFS_UCA0ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define OFS_UCA0IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ -#define OFS_UCA0IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ -#define OFS_UCA0IE_SPI (0x001A) -#define OFS_UCA0IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ -#define OFS_UCA0IFG_SPI (0x001C) -#define OFS_UCA0IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ -#define OFS_UCA0IV_SPI (0x001E) - -#define UCA0CTL0 (HWREG8_L(UCA0CTLW0)) /* eUSCI_Ax Control 0 */ -#define UCA0CTL1 (HWREG8_H(UCA0CTLW0)) /* eUSCI_Ax Control 1 */ -#define UCA0BR0 (HWREG8_L(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 0 */ -#define UCA0BR1 (HWREG8_H(UCA0BRW)) /* eUSCI_Ax Baud Rate Control 1 */ -#define UCA0IRTCTL (HWREG8_L(UCA0IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ -#define UCA0IRRCTL (HWREG8_H(UCA0IRCTL)) /* eUSCI_Ax IrDA Receive Control */ - -/****************************************************************************** -* EUSCI_A1 Registers -******************************************************************************/ -#define UCA1CTLW0 (HWREG16(0x40001400)) /*!< eUSCI_Ax Control Word Register 0 */ -#define UCA1CTLW0_SPI (HWREG16(0x40001400)) -#define UCA1CTLW1 (HWREG16(0x40001402)) /*!< eUSCI_Ax Control Word Register 1 */ -#define UCA1BRW (HWREG16(0x40001406)) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define UCA1BRW_SPI (HWREG16(0x40001406)) -#define UCA1MCTLW (HWREG16(0x40001408)) /*!< eUSCI_Ax Modulation Control Word Register */ -#define UCA1STATW (HWREG16(0x4000140A)) /*!< eUSCI_Ax Status Register */ -#define UCA1STATW_SPI (HWREG16(0x4000140A)) -#define UCA1RXBUF (HWREG16(0x4000140C)) /*!< eUSCI_Ax Receive Buffer Register */ -#define UCA1RXBUF_SPI (HWREG16(0x4000140C)) -#define UCA1TXBUF (HWREG16(0x4000140E)) /*!< eUSCI_Ax Transmit Buffer Register */ -#define UCA1TXBUF_SPI (HWREG16(0x4000140E)) -#define UCA1ABCTL (HWREG16(0x40001410)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define UCA1IRCTL (HWREG16(0x40001412)) /*!< eUSCI_Ax IrDA Control Word Register */ -#define UCA1IE (HWREG16(0x4000141A)) /*!< eUSCI_Ax Interrupt Enable Register */ -#define UCA1IE_SPI (HWREG16(0x4000141A)) -#define UCA1IFG (HWREG16(0x4000141C)) /*!< eUSCI_Ax Interrupt Flag Register */ -#define UCA1IFG_SPI (HWREG16(0x4000141C)) -#define UCA1IV (HWREG16(0x4000141E)) /*!< eUSCI_Ax Interrupt Vector Register */ -#define UCA1IV_SPI (HWREG16(0x4000141E)) - -/* Register offsets from EUSCI_A1_BASE address */ -#define OFS_UCA1CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ -#define OFS_UCA1CTLW0_SPI (0x0000) -#define OFS_UCA1CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ -#define OFS_UCA1BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define OFS_UCA1BRW_SPI (0x0006) -#define OFS_UCA1MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ -#define OFS_UCA1STATW (0x000A) /*!< eUSCI_Ax Status Register */ -#define OFS_UCA1STATW_SPI (0x000A) -#define OFS_UCA1RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ -#define OFS_UCA1RXBUF_SPI (0x000C) -#define OFS_UCA1TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ -#define OFS_UCA1TXBUF_SPI (0x000E) -#define OFS_UCA1ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define OFS_UCA1IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ -#define OFS_UCA1IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ -#define OFS_UCA1IE_SPI (0x001A) -#define OFS_UCA1IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ -#define OFS_UCA1IFG_SPI (0x001C) -#define OFS_UCA1IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ -#define OFS_UCA1IV_SPI (0x001E) - -#define UCA1CTL0 (HWREG8_L(UCA1CTLW0)) /* eUSCI_Ax Control 0 */ -#define UCA1CTL1 (HWREG8_H(UCA1CTLW0)) /* eUSCI_Ax Control 1 */ -#define UCA1BR0 (HWREG8_L(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 0 */ -#define UCA1BR1 (HWREG8_H(UCA1BRW)) /* eUSCI_Ax Baud Rate Control 1 */ -#define UCA1IRTCTL (HWREG8_L(UCA1IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ -#define UCA1IRRCTL (HWREG8_H(UCA1IRCTL)) /* eUSCI_Ax IrDA Receive Control */ - -/****************************************************************************** -* EUSCI_A2 Registers -******************************************************************************/ -#define UCA2CTLW0 (HWREG16(0x40001800)) /*!< eUSCI_Ax Control Word Register 0 */ -#define UCA2CTLW0_SPI (HWREG16(0x40001800)) -#define UCA2CTLW1 (HWREG16(0x40001802)) /*!< eUSCI_Ax Control Word Register 1 */ -#define UCA2BRW (HWREG16(0x40001806)) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define UCA2BRW_SPI (HWREG16(0x40001806)) -#define UCA2MCTLW (HWREG16(0x40001808)) /*!< eUSCI_Ax Modulation Control Word Register */ -#define UCA2STATW (HWREG16(0x4000180A)) /*!< eUSCI_Ax Status Register */ -#define UCA2STATW_SPI (HWREG16(0x4000180A)) -#define UCA2RXBUF (HWREG16(0x4000180C)) /*!< eUSCI_Ax Receive Buffer Register */ -#define UCA2RXBUF_SPI (HWREG16(0x4000180C)) -#define UCA2TXBUF (HWREG16(0x4000180E)) /*!< eUSCI_Ax Transmit Buffer Register */ -#define UCA2TXBUF_SPI (HWREG16(0x4000180E)) -#define UCA2ABCTL (HWREG16(0x40001810)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define UCA2IRCTL (HWREG16(0x40001812)) /*!< eUSCI_Ax IrDA Control Word Register */ -#define UCA2IE (HWREG16(0x4000181A)) /*!< eUSCI_Ax Interrupt Enable Register */ -#define UCA2IE_SPI (HWREG16(0x4000181A)) -#define UCA2IFG (HWREG16(0x4000181C)) /*!< eUSCI_Ax Interrupt Flag Register */ -#define UCA2IFG_SPI (HWREG16(0x4000181C)) -#define UCA2IV (HWREG16(0x4000181E)) /*!< eUSCI_Ax Interrupt Vector Register */ -#define UCA2IV_SPI (HWREG16(0x4000181E)) - -/* Register offsets from EUSCI_A2_BASE address */ -#define OFS_UCA2CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ -#define OFS_UCA2CTLW0_SPI (0x0000) -#define OFS_UCA2CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ -#define OFS_UCA2BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define OFS_UCA2BRW_SPI (0x0006) -#define OFS_UCA2MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ -#define OFS_UCA2STATW (0x000A) /*!< eUSCI_Ax Status Register */ -#define OFS_UCA2STATW_SPI (0x000A) -#define OFS_UCA2RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ -#define OFS_UCA2RXBUF_SPI (0x000C) -#define OFS_UCA2TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ -#define OFS_UCA2TXBUF_SPI (0x000E) -#define OFS_UCA2ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define OFS_UCA2IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ -#define OFS_UCA2IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ -#define OFS_UCA2IE_SPI (0x001A) -#define OFS_UCA2IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ -#define OFS_UCA2IFG_SPI (0x001C) -#define OFS_UCA2IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ -#define OFS_UCA2IV_SPI (0x001E) - -#define UCA2CTL0 (HWREG8_L(UCA2CTLW0)) /* eUSCI_Ax Control 0 */ -#define UCA2CTL1 (HWREG8_H(UCA2CTLW0)) /* eUSCI_Ax Control 1 */ -#define UCA2BR0 (HWREG8_L(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 0 */ -#define UCA2BR1 (HWREG8_H(UCA2BRW)) /* eUSCI_Ax Baud Rate Control 1 */ -#define UCA2IRTCTL (HWREG8_L(UCA2IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ -#define UCA2IRRCTL (HWREG8_H(UCA2IRCTL)) /* eUSCI_Ax IrDA Receive Control */ - -/****************************************************************************** -* EUSCI_A3 Registers -******************************************************************************/ -#define UCA3CTLW0 (HWREG16(0x40001C00)) /*!< eUSCI_Ax Control Word Register 0 */ -#define UCA3CTLW0_SPI (HWREG16(0x40001C00)) -#define UCA3CTLW1 (HWREG16(0x40001C02)) /*!< eUSCI_Ax Control Word Register 1 */ -#define UCA3BRW (HWREG16(0x40001C06)) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define UCA3BRW_SPI (HWREG16(0x40001C06)) -#define UCA3MCTLW (HWREG16(0x40001C08)) /*!< eUSCI_Ax Modulation Control Word Register */ -#define UCA3STATW (HWREG16(0x40001C0A)) /*!< eUSCI_Ax Status Register */ -#define UCA3STATW_SPI (HWREG16(0x40001C0A)) -#define UCA3RXBUF (HWREG16(0x40001C0C)) /*!< eUSCI_Ax Receive Buffer Register */ -#define UCA3RXBUF_SPI (HWREG16(0x40001C0C)) -#define UCA3TXBUF (HWREG16(0x40001C0E)) /*!< eUSCI_Ax Transmit Buffer Register */ -#define UCA3TXBUF_SPI (HWREG16(0x40001C0E)) -#define UCA3ABCTL (HWREG16(0x40001C10)) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define UCA3IRCTL (HWREG16(0x40001C12)) /*!< eUSCI_Ax IrDA Control Word Register */ -#define UCA3IE (HWREG16(0x40001C1A)) /*!< eUSCI_Ax Interrupt Enable Register */ -#define UCA3IE_SPI (HWREG16(0x40001C1A)) -#define UCA3IFG (HWREG16(0x40001C1C)) /*!< eUSCI_Ax Interrupt Flag Register */ -#define UCA3IFG_SPI (HWREG16(0x40001C1C)) -#define UCA3IV (HWREG16(0x40001C1E)) /*!< eUSCI_Ax Interrupt Vector Register */ -#define UCA3IV_SPI (HWREG16(0x40001C1E)) - -/* Register offsets from EUSCI_A3_BASE address */ -#define OFS_UCA3CTLW0 (0x0000) /*!< eUSCI_Ax Control Word Register 0 */ -#define OFS_UCA3CTLW0_SPI (0x0000) -#define OFS_UCA3CTLW1 (0x0002) /*!< eUSCI_Ax Control Word Register 1 */ -#define OFS_UCA3BRW (0x0006) /*!< eUSCI_Ax Baud Rate Control Word Register */ -#define OFS_UCA3BRW_SPI (0x0006) -#define OFS_UCA3MCTLW (0x0008) /*!< eUSCI_Ax Modulation Control Word Register */ -#define OFS_UCA3STATW (0x000A) /*!< eUSCI_Ax Status Register */ -#define OFS_UCA3STATW_SPI (0x000A) -#define OFS_UCA3RXBUF (0x000C) /*!< eUSCI_Ax Receive Buffer Register */ -#define OFS_UCA3RXBUF_SPI (0x000C) -#define OFS_UCA3TXBUF (0x000E) /*!< eUSCI_Ax Transmit Buffer Register */ -#define OFS_UCA3TXBUF_SPI (0x000E) -#define OFS_UCA3ABCTL (0x0010) /*!< eUSCI_Ax Auto Baud Rate Control Register */ -#define OFS_UCA3IRCTL (0x0012) /*!< eUSCI_Ax IrDA Control Word Register */ -#define OFS_UCA3IE (0x001A) /*!< eUSCI_Ax Interrupt Enable Register */ -#define OFS_UCA3IE_SPI (0x001A) -#define OFS_UCA3IFG (0x001C) /*!< eUSCI_Ax Interrupt Flag Register */ -#define OFS_UCA3IFG_SPI (0x001C) -#define OFS_UCA3IV (0x001E) /*!< eUSCI_Ax Interrupt Vector Register */ -#define OFS_UCA3IV_SPI (0x001E) - -#define UCA3CTL0 (HWREG8_L(UCA3CTLW0)) /* eUSCI_Ax Control 0 */ -#define UCA3CTL1 (HWREG8_H(UCA3CTLW0)) /* eUSCI_Ax Control 1 */ -#define UCA3BR0 (HWREG8_L(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 0 */ -#define UCA3BR1 (HWREG8_H(UCA3BRW)) /* eUSCI_Ax Baud Rate Control 1 */ -#define UCA3IRTCTL (HWREG8_L(UCA3IRCTL)) /* eUSCI_Ax IrDA Transmit Control */ -#define UCA3IRRCTL (HWREG8_H(UCA3IRCTL)) /* eUSCI_Ax IrDA Receive Control */ - -/****************************************************************************** -* EUSCI_B0 Registers -******************************************************************************/ -#define UCB0CTLW0 (HWREG16(0x40002000)) /*!< eUSCI_Bx Control Word Register 0 */ -#define UCB0CTLW0_SPI (HWREG16(0x40002000)) -#define UCB0CTLW1 (HWREG16(0x40002002)) /*!< eUSCI_Bx Control Word Register 1 */ -#define UCB0BRW (HWREG16(0x40002006)) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define UCB0BRW_SPI (HWREG16(0x40002006)) -#define UCB0STATW (HWREG16(0x40002008)) /*!< eUSCI_Bx Status Register */ -#define UCB0STATW_SPI (HWREG16(0x40002008)) -#define UCB0TBCNT (HWREG16(0x4000200A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define UCB0RXBUF (HWREG16(0x4000200C)) /*!< eUSCI_Bx Receive Buffer Register */ -#define UCB0RXBUF_SPI (HWREG16(0x4000200C)) -#define UCB0TXBUF (HWREG16(0x4000200E)) /*!< eUSCI_Bx Transmit Buffer Register */ -#define UCB0TXBUF_SPI (HWREG16(0x4000200E)) -#define UCB0I2COA0 (HWREG16(0x40002014)) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define UCB0I2COA1 (HWREG16(0x40002016)) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define UCB0I2COA2 (HWREG16(0x40002018)) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define UCB0I2COA3 (HWREG16(0x4000201A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define UCB0ADDRX (HWREG16(0x4000201C)) /*!< eUSCI_Bx I2C Received Address Register */ -#define UCB0ADDMASK (HWREG16(0x4000201E)) /*!< eUSCI_Bx I2C Address Mask Register */ -#define UCB0I2CSA (HWREG16(0x40002020)) /*!< eUSCI_Bx I2C Slave Address Register */ -#define UCB0IE (HWREG16(0x4000202A)) /*!< eUSCI_Bx Interrupt Enable Register */ -#define UCB0IE_SPI (HWREG16(0x4000202A)) -#define UCB0IFG (HWREG16(0x4000202C)) /*!< eUSCI_Bx Interrupt Flag Register */ -#define UCB0IFG_SPI (HWREG16(0x4000202C)) -#define UCB0IV (HWREG16(0x4000202E)) /*!< eUSCI_Bx Interrupt Vector Register */ -#define UCB0IV_SPI (HWREG16(0x4000202E)) - -/* Register offsets from EUSCI_B0_BASE address */ -#define OFS_UCB0CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ -#define OFS_UCB0CTLW0_SPI (0x0000) -#define OFS_UCB0CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ -#define OFS_UCB0BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define OFS_UCB0BRW_SPI (0x0006) -#define OFS_UCB0STATW (0x0008) /*!< eUSCI_Bx Status Register */ -#define OFS_UCB0STATW_SPI (0x0008) -#define OFS_UCB0TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define OFS_UCB0RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ -#define OFS_UCB0RXBUF_SPI (0x000C) -#define OFS_UCB0TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ -#define OFS_UCB0TXBUF_SPI (0x000E) -#define OFS_UCB0I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define OFS_UCB0I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define OFS_UCB0I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define OFS_UCB0I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define OFS_UCB0ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ -#define OFS_UCB0ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ -#define OFS_UCB0I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ -#define OFS_UCB0IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ -#define OFS_UCB0IE_SPI (0x002A) -#define OFS_UCB0IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ -#define OFS_UCB0IFG_SPI (0x002C) -#define OFS_UCB0IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ -#define OFS_UCB0IV_SPI (0x002E) - -#define UCB0CTL0 (HWREG8_L(UCB0CTLW0)) /* eUSCI_Bx Control 1 */ -#define UCB0CTL1 (HWREG8_H(UCB0CTLW0)) /* eUSCI_Bx Control 0 */ -#define UCB0BR0 (HWREG8_L(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 0 */ -#define UCB0BR1 (HWREG8_H(UCB0BRW)) /* eUSCI_Bx Bit Rate Control 1 */ -#define UCB0STAT (HWREG8_L(UCB0STATW)) /* eUSCI_Bx Status */ -#define UCB0BCNT (HWREG8_H(UCB0STATW)) /* eUSCI_Bx Byte Counter Register */ - -/****************************************************************************** -* EUSCI_B1 Registers -******************************************************************************/ -#define UCB1CTLW0 (HWREG16(0x40002400)) /*!< eUSCI_Bx Control Word Register 0 */ -#define UCB1CTLW0_SPI (HWREG16(0x40002400)) -#define UCB1CTLW1 (HWREG16(0x40002402)) /*!< eUSCI_Bx Control Word Register 1 */ -#define UCB1BRW (HWREG16(0x40002406)) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define UCB1BRW_SPI (HWREG16(0x40002406)) -#define UCB1STATW (HWREG16(0x40002408)) /*!< eUSCI_Bx Status Register */ -#define UCB1STATW_SPI (HWREG16(0x40002408)) -#define UCB1TBCNT (HWREG16(0x4000240A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define UCB1RXBUF (HWREG16(0x4000240C)) /*!< eUSCI_Bx Receive Buffer Register */ -#define UCB1RXBUF_SPI (HWREG16(0x4000240C)) -#define UCB1TXBUF (HWREG16(0x4000240E)) /*!< eUSCI_Bx Transmit Buffer Register */ -#define UCB1TXBUF_SPI (HWREG16(0x4000240E)) -#define UCB1I2COA0 (HWREG16(0x40002414)) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define UCB1I2COA1 (HWREG16(0x40002416)) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define UCB1I2COA2 (HWREG16(0x40002418)) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define UCB1I2COA3 (HWREG16(0x4000241A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define UCB1ADDRX (HWREG16(0x4000241C)) /*!< eUSCI_Bx I2C Received Address Register */ -#define UCB1ADDMASK (HWREG16(0x4000241E)) /*!< eUSCI_Bx I2C Address Mask Register */ -#define UCB1I2CSA (HWREG16(0x40002420)) /*!< eUSCI_Bx I2C Slave Address Register */ -#define UCB1IE (HWREG16(0x4000242A)) /*!< eUSCI_Bx Interrupt Enable Register */ -#define UCB1IE_SPI (HWREG16(0x4000242A)) -#define UCB1IFG (HWREG16(0x4000242C)) /*!< eUSCI_Bx Interrupt Flag Register */ -#define UCB1IFG_SPI (HWREG16(0x4000242C)) -#define UCB1IV (HWREG16(0x4000242E)) /*!< eUSCI_Bx Interrupt Vector Register */ -#define UCB1IV_SPI (HWREG16(0x4000242E)) - -/* Register offsets from EUSCI_B1_BASE address */ -#define OFS_UCB1CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ -#define OFS_UCB1CTLW0_SPI (0x0000) -#define OFS_UCB1CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ -#define OFS_UCB1BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define OFS_UCB1BRW_SPI (0x0006) -#define OFS_UCB1STATW (0x0008) /*!< eUSCI_Bx Status Register */ -#define OFS_UCB1STATW_SPI (0x0008) -#define OFS_UCB1TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define OFS_UCB1RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ -#define OFS_UCB1RXBUF_SPI (0x000C) -#define OFS_UCB1TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ -#define OFS_UCB1TXBUF_SPI (0x000E) -#define OFS_UCB1I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define OFS_UCB1I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define OFS_UCB1I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define OFS_UCB1I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define OFS_UCB1ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ -#define OFS_UCB1ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ -#define OFS_UCB1I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ -#define OFS_UCB1IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ -#define OFS_UCB1IE_SPI (0x002A) -#define OFS_UCB1IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ -#define OFS_UCB1IFG_SPI (0x002C) -#define OFS_UCB1IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ -#define OFS_UCB1IV_SPI (0x002E) - -#define UCB1CTL0 (HWREG8_L(UCB1CTLW0)) /* eUSCI_Bx Control 1 */ -#define UCB1CTL1 (HWREG8_H(UCB1CTLW0)) /* eUSCI_Bx Control 0 */ -#define UCB1BR0 (HWREG8_L(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 0 */ -#define UCB1BR1 (HWREG8_H(UCB1BRW)) /* eUSCI_Bx Bit Rate Control 1 */ -#define UCB1STAT (HWREG8_L(UCB1STATW)) /* eUSCI_Bx Status */ -#define UCB1BCNT (HWREG8_H(UCB1STATW)) /* eUSCI_Bx Byte Counter Register */ - -/****************************************************************************** -* EUSCI_B2 Registers -******************************************************************************/ -#define UCB2CTLW0 (HWREG16(0x40002800)) /*!< eUSCI_Bx Control Word Register 0 */ -#define UCB2CTLW0_SPI (HWREG16(0x40002800)) -#define UCB2CTLW1 (HWREG16(0x40002802)) /*!< eUSCI_Bx Control Word Register 1 */ -#define UCB2BRW (HWREG16(0x40002806)) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define UCB2BRW_SPI (HWREG16(0x40002806)) -#define UCB2STATW (HWREG16(0x40002808)) /*!< eUSCI_Bx Status Register */ -#define UCB2STATW_SPI (HWREG16(0x40002808)) -#define UCB2TBCNT (HWREG16(0x4000280A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define UCB2RXBUF (HWREG16(0x4000280C)) /*!< eUSCI_Bx Receive Buffer Register */ -#define UCB2RXBUF_SPI (HWREG16(0x4000280C)) -#define UCB2TXBUF (HWREG16(0x4000280E)) /*!< eUSCI_Bx Transmit Buffer Register */ -#define UCB2TXBUF_SPI (HWREG16(0x4000280E)) -#define UCB2I2COA0 (HWREG16(0x40002814)) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define UCB2I2COA1 (HWREG16(0x40002816)) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define UCB2I2COA2 (HWREG16(0x40002818)) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define UCB2I2COA3 (HWREG16(0x4000281A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define UCB2ADDRX (HWREG16(0x4000281C)) /*!< eUSCI_Bx I2C Received Address Register */ -#define UCB2ADDMASK (HWREG16(0x4000281E)) /*!< eUSCI_Bx I2C Address Mask Register */ -#define UCB2I2CSA (HWREG16(0x40002820)) /*!< eUSCI_Bx I2C Slave Address Register */ -#define UCB2IE (HWREG16(0x4000282A)) /*!< eUSCI_Bx Interrupt Enable Register */ -#define UCB2IE_SPI (HWREG16(0x4000282A)) -#define UCB2IFG (HWREG16(0x4000282C)) /*!< eUSCI_Bx Interrupt Flag Register */ -#define UCB2IFG_SPI (HWREG16(0x4000282C)) -#define UCB2IV (HWREG16(0x4000282E)) /*!< eUSCI_Bx Interrupt Vector Register */ -#define UCB2IV_SPI (HWREG16(0x4000282E)) - -/* Register offsets from EUSCI_B2_BASE address */ -#define OFS_UCB2CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ -#define OFS_UCB2CTLW0_SPI (0x0000) -#define OFS_UCB2CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ -#define OFS_UCB2BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define OFS_UCB2BRW_SPI (0x0006) -#define OFS_UCB2STATW (0x0008) /*!< eUSCI_Bx Status Register */ -#define OFS_UCB2STATW_SPI (0x0008) -#define OFS_UCB2TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define OFS_UCB2RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ -#define OFS_UCB2RXBUF_SPI (0x000C) -#define OFS_UCB2TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ -#define OFS_UCB2TXBUF_SPI (0x000E) -#define OFS_UCB2I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define OFS_UCB2I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define OFS_UCB2I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define OFS_UCB2I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define OFS_UCB2ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ -#define OFS_UCB2ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ -#define OFS_UCB2I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ -#define OFS_UCB2IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ -#define OFS_UCB2IE_SPI (0x002A) -#define OFS_UCB2IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ -#define OFS_UCB2IFG_SPI (0x002C) -#define OFS_UCB2IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ -#define OFS_UCB2IV_SPI (0x002E) - -#define UCB2CTL0 (HWREG8_L(UCB2CTLW0)) /* eUSCI_Bx Control 1 */ -#define UCB2CTL1 (HWREG8_H(UCB2CTLW0)) /* eUSCI_Bx Control 0 */ -#define UCB2BR0 (HWREG8_L(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 0 */ -#define UCB2BR1 (HWREG8_H(UCB2BRW)) /* eUSCI_Bx Bit Rate Control 1 */ -#define UCB2STAT (HWREG8_L(UCB2STATW)) /* eUSCI_Bx Status */ -#define UCB2BCNT (HWREG8_H(UCB2STATW)) /* eUSCI_Bx Byte Counter Register */ - -/****************************************************************************** -* EUSCI_B3 Registers -******************************************************************************/ -#define UCB3CTLW0 (HWREG16(0x40002C00)) /*!< eUSCI_Bx Control Word Register 0 */ -#define UCB3CTLW0_SPI (HWREG16(0x40002C00)) -#define UCB3CTLW1 (HWREG16(0x40002C02)) /*!< eUSCI_Bx Control Word Register 1 */ -#define UCB3BRW (HWREG16(0x40002C06)) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define UCB3BRW_SPI (HWREG16(0x40002C06)) -#define UCB3STATW (HWREG16(0x40002C08)) /*!< eUSCI_Bx Status Register */ -#define UCB3STATW_SPI (HWREG16(0x40002C08)) -#define UCB3TBCNT (HWREG16(0x40002C0A)) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define UCB3RXBUF (HWREG16(0x40002C0C)) /*!< eUSCI_Bx Receive Buffer Register */ -#define UCB3RXBUF_SPI (HWREG16(0x40002C0C)) -#define UCB3TXBUF (HWREG16(0x40002C0E)) /*!< eUSCI_Bx Transmit Buffer Register */ -#define UCB3TXBUF_SPI (HWREG16(0x40002C0E)) -#define UCB3I2COA0 (HWREG16(0x40002C14)) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define UCB3I2COA1 (HWREG16(0x40002C16)) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define UCB3I2COA2 (HWREG16(0x40002C18)) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define UCB3I2COA3 (HWREG16(0x40002C1A)) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define UCB3ADDRX (HWREG16(0x40002C1C)) /*!< eUSCI_Bx I2C Received Address Register */ -#define UCB3ADDMASK (HWREG16(0x40002C1E)) /*!< eUSCI_Bx I2C Address Mask Register */ -#define UCB3I2CSA (HWREG16(0x40002C20)) /*!< eUSCI_Bx I2C Slave Address Register */ -#define UCB3IE (HWREG16(0x40002C2A)) /*!< eUSCI_Bx Interrupt Enable Register */ -#define UCB3IE_SPI (HWREG16(0x40002C2A)) -#define UCB3IFG (HWREG16(0x40002C2C)) /*!< eUSCI_Bx Interrupt Flag Register */ -#define UCB3IFG_SPI (HWREG16(0x40002C2C)) -#define UCB3IV (HWREG16(0x40002C2E)) /*!< eUSCI_Bx Interrupt Vector Register */ -#define UCB3IV_SPI (HWREG16(0x40002C2E)) - -/* Register offsets from EUSCI_B3_BASE address */ -#define OFS_UCB3CTLW0 (0x0000) /*!< eUSCI_Bx Control Word Register 0 */ -#define OFS_UCB3CTLW0_SPI (0x0000) -#define OFS_UCB3CTLW1 (0x0002) /*!< eUSCI_Bx Control Word Register 1 */ -#define OFS_UCB3BRW (0x0006) /*!< eUSCI_Bx Baud Rate Control Word Register */ -#define OFS_UCB3BRW_SPI (0x0006) -#define OFS_UCB3STATW (0x0008) /*!< eUSCI_Bx Status Register */ -#define OFS_UCB3STATW_SPI (0x0008) -#define OFS_UCB3TBCNT (0x000A) /*!< eUSCI_Bx Byte Counter Threshold Register */ -#define OFS_UCB3RXBUF (0x000C) /*!< eUSCI_Bx Receive Buffer Register */ -#define OFS_UCB3RXBUF_SPI (0x000C) -#define OFS_UCB3TXBUF (0x000E) /*!< eUSCI_Bx Transmit Buffer Register */ -#define OFS_UCB3TXBUF_SPI (0x000E) -#define OFS_UCB3I2COA0 (0x0014) /*!< eUSCI_Bx I2C Own Address 0 Register */ -#define OFS_UCB3I2COA1 (0x0016) /*!< eUSCI_Bx I2C Own Address 1 Register */ -#define OFS_UCB3I2COA2 (0x0018) /*!< eUSCI_Bx I2C Own Address 2 Register */ -#define OFS_UCB3I2COA3 (0x001A) /*!< eUSCI_Bx I2C Own Address 3 Register */ -#define OFS_UCB3ADDRX (0x001C) /*!< eUSCI_Bx I2C Received Address Register */ -#define OFS_UCB3ADDMASK (0x001E) /*!< eUSCI_Bx I2C Address Mask Register */ -#define OFS_UCB3I2CSA (0x0020) /*!< eUSCI_Bx I2C Slave Address Register */ -#define OFS_UCB3IE (0x002A) /*!< eUSCI_Bx Interrupt Enable Register */ -#define OFS_UCB3IE_SPI (0x002A) -#define OFS_UCB3IFG (0x002C) /*!< eUSCI_Bx Interrupt Flag Register */ -#define OFS_UCB3IFG_SPI (0x002C) -#define OFS_UCB3IV (0x002E) /*!< eUSCI_Bx Interrupt Vector Register */ -#define OFS_UCB3IV_SPI (0x002E) - -#define UCB3CTL0 (HWREG8_L(UCB3CTLW0)) /* eUSCI_Bx Control 1 */ -#define UCB3CTL1 (HWREG8_H(UCB3CTLW0)) /* eUSCI_Bx Control 0 */ -#define UCB3BR0 (HWREG8_L(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 0 */ -#define UCB3BR1 (HWREG8_H(UCB3BRW)) /* eUSCI_Bx Bit Rate Control 1 */ -#define UCB3STAT (HWREG8_L(UCB3STATW)) /* eUSCI_Bx Status */ -#define UCB3BCNT (HWREG8_H(UCB3STATW)) /* eUSCI_Bx Byte Counter Register */ - -/****************************************************************************** -* PMAP Registers -******************************************************************************/ -#define PMAPKEYID (HWREG16(0x40005000)) /*!< Port Mapping Key Register */ -#define PMAPCTL (HWREG16(0x40005002)) /*!< Port Mapping Control Register */ -#define P1MAP01 (HWREG16(0x40005008)) /*!< Port mapping register, P1.0 and P1.1 */ -#define P1MAP23 (HWREG16(0x4000500A)) /*!< Port mapping register, P1.2 and P1.3 */ -#define P1MAP45 (HWREG16(0x4000500C)) /*!< Port mapping register, P1.4 and P1.5 */ -#define P1MAP67 (HWREG16(0x4000500E)) /*!< Port mapping register, P1.6 and P1.7 */ -#define P2MAP01 (HWREG16(0x40005010)) /*!< Port mapping register, P2.0 and P2.1 */ -#define P2MAP23 (HWREG16(0x40005012)) /*!< Port mapping register, P2.2 and P2.3 */ -#define P2MAP45 (HWREG16(0x40005014)) /*!< Port mapping register, P2.4 and P2.5 */ -#define P2MAP67 (HWREG16(0x40005016)) /*!< Port mapping register, P2.6 and P2.7 */ -#define P3MAP01 (HWREG16(0x40005018)) /*!< Port mapping register, P3.0 and P3.1 */ -#define P3MAP23 (HWREG16(0x4000501A)) /*!< Port mapping register, P3.2 and P3.3 */ -#define P3MAP45 (HWREG16(0x4000501C)) /*!< Port mapping register, P3.4 and P3.5 */ -#define P3MAP67 (HWREG16(0x4000501E)) /*!< Port mapping register, P3.6 and P3.7 */ -#define P4MAP01 (HWREG16(0x40005020)) /*!< Port mapping register, P4.0 and P4.1 */ -#define P4MAP23 (HWREG16(0x40005022)) /*!< Port mapping register, P4.2 and P4.3 */ -#define P4MAP45 (HWREG16(0x40005024)) /*!< Port mapping register, P4.4 and P4.5 */ -#define P4MAP67 (HWREG16(0x40005026)) /*!< Port mapping register, P4.6 and P4.7 */ -#define P5MAP01 (HWREG16(0x40005028)) /*!< Port mapping register, P5.0 and P5.1 */ -#define P5MAP23 (HWREG16(0x4000502A)) /*!< Port mapping register, P5.2 and P5.3 */ -#define P5MAP45 (HWREG16(0x4000502C)) /*!< Port mapping register, P5.4 and P5.5 */ -#define P5MAP67 (HWREG16(0x4000502E)) /*!< Port mapping register, P5.6 and P5.7 */ -#define P6MAP01 (HWREG16(0x40005030)) /*!< Port mapping register, P6.0 and P6.1 */ -#define P6MAP23 (HWREG16(0x40005032)) /*!< Port mapping register, P6.2 and P6.3 */ -#define P6MAP45 (HWREG16(0x40005034)) /*!< Port mapping register, P6.4 and P6.5 */ -#define P6MAP67 (HWREG16(0x40005036)) /*!< Port mapping register, P6.6 and P6.7 */ -#define P7MAP01 (HWREG16(0x40005038)) /*!< Port mapping register, P7.0 and P7.1 */ -#define P7MAP23 (HWREG16(0x4000503A)) /*!< Port mapping register, P7.2 and P7.3 */ -#define P7MAP45 (HWREG16(0x4000503C)) /*!< Port mapping register, P7.4 and P7.5 */ -#define P7MAP67 (HWREG16(0x4000503E)) /*!< Port mapping register, P7.6 and P7.7 */ - -/* Register offsets from PMAP_BASE address */ -#define OFS_PMAPKEYID (0x0000) /*!< Port Mapping Key Register */ -#define OFS_PMAPCTL (0x0002) /*!< Port Mapping Control Register */ -#define OFS_P1MAP01 (0x0008) /*!< Port mapping register, P1.0 and P1.1 */ -#define OFS_P1MAP23 (0x000A) /*!< Port mapping register, P1.2 and P1.3 */ -#define OFS_P1MAP45 (0x000C) /*!< Port mapping register, P1.4 and P1.5 */ -#define OFS_P1MAP67 (0x000E) /*!< Port mapping register, P1.6 and P1.7 */ -#define OFS_P2MAP01 (0x0010) /*!< Port mapping register, P2.0 and P2.1 */ -#define OFS_P2MAP23 (0x0012) /*!< Port mapping register, P2.2 and P2.3 */ -#define OFS_P2MAP45 (0x0014) /*!< Port mapping register, P2.4 and P2.5 */ -#define OFS_P2MAP67 (0x0016) /*!< Port mapping register, P2.6 and P2.7 */ -#define OFS_P3MAP01 (0x0018) /*!< Port mapping register, P3.0 and P3.1 */ -#define OFS_P3MAP23 (0x001A) /*!< Port mapping register, P3.2 and P3.3 */ -#define OFS_P3MAP45 (0x001C) /*!< Port mapping register, P3.4 and P3.5 */ -#define OFS_P3MAP67 (0x001E) /*!< Port mapping register, P3.6 and P3.7 */ -#define OFS_P4MAP01 (0x0020) /*!< Port mapping register, P4.0 and P4.1 */ -#define OFS_P4MAP23 (0x0022) /*!< Port mapping register, P4.2 and P4.3 */ -#define OFS_P4MAP45 (0x0024) /*!< Port mapping register, P4.4 and P4.5 */ -#define OFS_P4MAP67 (0x0026) /*!< Port mapping register, P4.6 and P4.7 */ -#define OFS_P5MAP01 (0x0028) /*!< Port mapping register, P5.0 and P5.1 */ -#define OFS_P5MAP23 (0x002A) /*!< Port mapping register, P5.2 and P5.3 */ -#define OFS_P5MAP45 (0x002C) /*!< Port mapping register, P5.4 and P5.5 */ -#define OFS_P5MAP67 (0x002E) /*!< Port mapping register, P5.6 and P5.7 */ -#define OFS_P6MAP01 (0x0030) /*!< Port mapping register, P6.0 and P6.1 */ -#define OFS_P6MAP23 (0x0032) /*!< Port mapping register, P6.2 and P6.3 */ -#define OFS_P6MAP45 (0x0034) /*!< Port mapping register, P6.4 and P6.5 */ -#define OFS_P6MAP67 (0x0036) /*!< Port mapping register, P6.6 and P6.7 */ -#define OFS_P7MAP01 (0x0038) /*!< Port mapping register, P7.0 and P7.1 */ -#define OFS_P7MAP23 (0x003A) /*!< Port mapping register, P7.2 and P7.3 */ -#define OFS_P7MAP45 (0x003C) /*!< Port mapping register, P7.4 and P7.5 */ -#define OFS_P7MAP67 (0x003E) /*!< Port mapping register, P7.6 and P7.7 */ - - -/****************************************************************************** -* REF_A Registers -******************************************************************************/ -#define REFCTL0 (HWREG16(0x40003000)) /*!< REF Control Register 0 */ - -/* Register offsets from REF_A_BASE address */ -#define OFS_REFCTL0 (0x0000) /*!< REF Control Register 0 */ - -#define REFCTL0_L (HWREG8_L(REFCTL0)) /* REF Control Register 0 */ -#define REFCTL0_H (HWREG8_H(REFCTL0)) /* REF Control Register 0 */ - -/****************************************************************************** -* RTC_C Registers -******************************************************************************/ -#define RTCCTL0 (HWREG16(0x40004400)) /*!< RTCCTL0 Register */ -#define RTCCTL13 (HWREG16(0x40004402)) /*!< RTCCTL13 Register */ -#define RTCOCAL (HWREG16(0x40004404)) /*!< RTCOCAL Register */ -#define RTCTCMP (HWREG16(0x40004406)) /*!< RTCTCMP Register */ -#define RTCPS0CTL (HWREG16(0x40004408)) /*!< Real-Time Clock Prescale Timer 0 Control Register */ -#define RTCPS1CTL (HWREG16(0x4000440A)) /*!< Real-Time Clock Prescale Timer 1 Control Register */ -#define RTCPS (HWREG16(0x4000440C)) /*!< Real-Time Clock Prescale Timer Counter Register */ -#define RTCIV (HWREG16(0x4000440E)) /*!< Real-Time Clock Interrupt Vector Register */ -#define RTCTIM0 (HWREG16(0x40004410)) /*!< RTCTIM0 Register Hexadecimal Format */ -#define RTCTIM0_BCD (HWREG16(0x40004410)) -#define RTCTIM1 (HWREG16(0x40004412)) /*!< Real-Time Clock Hour, Day of Week */ -#define RTCTIM1_BCD (HWREG16(0x40004412)) -#define RTCDATE (HWREG16(0x40004414)) /*!< RTCDATE - Hexadecimal Format */ -#define RTCDATE_BCD (HWREG16(0x40004414)) -#define RTCYEAR (HWREG16(0x40004416)) /*!< RTCYEAR Register Hexadecimal Format */ -#define RTCYEAR_BCD (HWREG16(0x40004416)) -#define RTCAMINHR (HWREG16(0x40004418)) /*!< RTCMINHR - Hexadecimal Format */ -#define RTCAMINHR_BCD (HWREG16(0x40004418)) -#define RTCADOWDAY (HWREG16(0x4000441A)) /*!< RTCADOWDAY - Hexadecimal Format */ -#define RTCADOWDAY_BCD (HWREG16(0x4000441A)) -#define RTCBIN2BCD (HWREG16(0x4000441C)) /*!< Binary-to-BCD Conversion Register */ -#define RTCBCD2BIN (HWREG16(0x4000441E)) /*!< BCD-to-Binary Conversion Register */ - -/* Register offsets from RTC_C_BASE address */ -#define OFS_RTCCTL0 (0x0000) /*!< RTCCTL0 Register */ -#define OFS_RTCCTL13 (0x0002) /*!< RTCCTL13 Register */ -#define OFS_RTCOCAL (0x0004) /*!< RTCOCAL Register */ -#define OFS_RTCTCMP (0x0006) /*!< RTCTCMP Register */ -#define OFS_RTCPS0CTL (0x0008) /*!< Real-Time Clock Prescale Timer 0 Control Register */ -#define OFS_RTCPS1CTL (0x000A) /*!< Real-Time Clock Prescale Timer 1 Control Register */ -#define OFS_RTCPS (0x000C) /*!< Real-Time Clock Prescale Timer Counter Register */ -#define OFS_RTCIV (0x000E) /*!< Real-Time Clock Interrupt Vector Register */ -#define OFS_RTCTIM0 (0x0010) /*!< RTCTIM0 Register Hexadecimal Format */ -#define OFS_RTCTIM0_BCD (0x0010) -#define OFS_RTCTIM1 (0x0012) /*!< Real-Time Clock Hour, Day of Week */ -#define OFS_RTCTIM1_BCD (0x0012) -#define OFS_RTCDATE (0x0014) /*!< RTCDATE - Hexadecimal Format */ -#define OFS_RTCDATE_BCD (0x0014) -#define OFS_RTCYEAR (0x0016) /*!< RTCYEAR Register Hexadecimal Format */ -#define OFS_RTCYEAR_BCD (0x0016) -#define OFS_RTCAMINHR (0x0018) /*!< RTCMINHR - Hexadecimal Format */ -#define OFS_RTCAMINHR_BCD (0x0018) -#define OFS_RTCADOWDAY (0x001A) /*!< RTCADOWDAY - Hexadecimal Format */ -#define OFS_RTCADOWDAY_BCD (0x001A) -#define OFS_RTCBIN2BCD (0x001C) /*!< Binary-to-BCD Conversion Register */ -#define OFS_RTCBCD2BIN (0x001E) /*!< BCD-to-Binary Conversion Register */ - -#define RTCCTL0_L (HWREG8_L(RTCCTL0)) /* RTCCTL0 Register */ -#define RTCCTL0_H (HWREG8_H(RTCCTL0)) /* RTCCTL0 Register */ -#define RTCCTL1 (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */ -#define RTCCTL13_L (HWREG8_L(RTCCTL13)) /* RTCCTL13 Register */ -#define RTCCTL3 (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */ -#define RTCCTL13_H (HWREG8_H(RTCCTL13)) /* RTCCTL13 Register */ -#define RTCOCAL_L (HWREG8_L(RTCOCAL)) /* RTCOCAL Register */ -#define RTCOCAL_H (HWREG8_H(RTCOCAL)) /* RTCOCAL Register */ -#define RTCTCMP_L (HWREG8_L(RTCTCMP)) /* RTCTCMP Register */ -#define RTCTCMP_H (HWREG8_H(RTCTCMP)) /* RTCTCMP Register */ -#define RTCPS0CTL_L (HWREG8_L(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */ -#define RTCPS0CTL_H (HWREG8_H(RTCPS0CTL)) /* Real-Time Clock Prescale Timer 0 Control Register */ -#define RTCPS1CTL_L (HWREG8_L(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */ -#define RTCPS1CTL_H (HWREG8_H(RTCPS1CTL)) /* Real-Time Clock Prescale Timer 1 Control Register */ -#define RTCPS0 (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ -#define RTCPS_L (HWREG8_L(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ -#define RTCPS1 (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ -#define RTCPS_H (HWREG8_H(RTCPS)) /* Real-Time Clock Prescale Timer Counter Register */ -#define RTCSEC (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */ -#define RTCTIM0_L (HWREG8_L(RTCTIM0)) /* Real-Time Clock Seconds */ -#define RTCMIN (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */ -#define RTCTIM0_H (HWREG8_H(RTCTIM0)) /* Real-Time Clock Minutes */ -#define RTCHOUR (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */ -#define RTCTIM1_L (HWREG8_L(RTCTIM1)) /* Real-Time Clock Hour */ -#define RTCDOW (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */ -#define RTCTIM1_H (HWREG8_H(RTCTIM1)) /* Real-Time Clock Day of Week */ -#define RTCDAY (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */ -#define RTCDATE_L (HWREG8_L(RTCDATE)) /* Real-Time Clock Day of Month */ -#define RTCMON (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */ -#define RTCDATE_H (HWREG8_H(RTCDATE)) /* Real-Time Clock Month */ -#define RTCAMIN (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */ -#define RTCAMINHR_L (HWREG8_L(RTCAMINHR)) /* Real-Time Clock Minutes Alarm */ -#define RTCAHOUR (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */ -#define RTCAMINHR_H (HWREG8_H(RTCAMINHR)) /* Real-Time Clock Hours Alarm */ -#define RTCADOW (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */ -#define RTCADOWDAY_L (HWREG8_L(RTCADOWDAY))/* Real-Time Clock Day of Week Alarm */ -#define RTCADAY (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */ -#define RTCADOWDAY_H (HWREG8_H(RTCADOWDAY))/* Real-Time Clock Day of Month Alarm */ - -/****************************************************************************** -* TIMER_A0 Registers -******************************************************************************/ -#define TA0CTL (HWREG16(0x40000000)) /*!< TimerAx Control Register */ -#define TA0CCTL0 (HWREG16(0x40000002)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0CCTL1 (HWREG16(0x40000004)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0CCTL2 (HWREG16(0x40000006)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0CCTL3 (HWREG16(0x40000008)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0CCTL4 (HWREG16(0x4000000A)) /*!< Timer_A Capture/Compare Control Register */ -#define TA0R (HWREG16(0x40000010)) /*!< TimerA register */ -#define TA0CCR0 (HWREG16(0x40000012)) /*!< Timer_A Capture/Compare Register */ -#define TA0CCR1 (HWREG16(0x40000014)) /*!< Timer_A Capture/Compare Register */ -#define TA0CCR2 (HWREG16(0x40000016)) /*!< Timer_A Capture/Compare Register */ -#define TA0CCR3 (HWREG16(0x40000018)) /*!< Timer_A Capture/Compare Register */ -#define TA0CCR4 (HWREG16(0x4000001A)) /*!< Timer_A Capture/Compare Register */ -#define TA0EX0 (HWREG16(0x40000020)) /*!< TimerAx Expansion 0 Register */ -#define TA0IV (HWREG16(0x4000002E)) /*!< TimerAx Interrupt Vector Register */ - -/* Register offsets from TIMER_A0_BASE address */ -#define OFS_TA0CTL (0x0000) /*!< TimerAx Control Register */ -#define OFS_TA0CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA0R (0x0010) /*!< TimerA register */ -#define OFS_TA0CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA0EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ -#define OFS_TA0IV (0x002E) /*!< TimerAx Interrupt Vector Register */ - - -/****************************************************************************** -* TIMER_A1 Registers -******************************************************************************/ -#define TA1CTL (HWREG16(0x40000400)) /*!< TimerAx Control Register */ -#define TA1CCTL0 (HWREG16(0x40000402)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1CCTL1 (HWREG16(0x40000404)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1CCTL2 (HWREG16(0x40000406)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1CCTL3 (HWREG16(0x40000408)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1CCTL4 (HWREG16(0x4000040A)) /*!< Timer_A Capture/Compare Control Register */ -#define TA1R (HWREG16(0x40000410)) /*!< TimerA register */ -#define TA1CCR0 (HWREG16(0x40000412)) /*!< Timer_A Capture/Compare Register */ -#define TA1CCR1 (HWREG16(0x40000414)) /*!< Timer_A Capture/Compare Register */ -#define TA1CCR2 (HWREG16(0x40000416)) /*!< Timer_A Capture/Compare Register */ -#define TA1CCR3 (HWREG16(0x40000418)) /*!< Timer_A Capture/Compare Register */ -#define TA1CCR4 (HWREG16(0x4000041A)) /*!< Timer_A Capture/Compare Register */ -#define TA1EX0 (HWREG16(0x40000420)) /*!< TimerAx Expansion 0 Register */ -#define TA1IV (HWREG16(0x4000042E)) /*!< TimerAx Interrupt Vector Register */ - -/* Register offsets from TIMER_A1_BASE address */ -#define OFS_TA1CTL (0x0000) /*!< TimerAx Control Register */ -#define OFS_TA1CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA1R (0x0010) /*!< TimerA register */ -#define OFS_TA1CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA1EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ -#define OFS_TA1IV (0x002E) /*!< TimerAx Interrupt Vector Register */ - - -/****************************************************************************** -* TIMER_A2 Registers -******************************************************************************/ -#define TA2CTL (HWREG16(0x40000800)) /*!< TimerAx Control Register */ -#define TA2CCTL0 (HWREG16(0x40000802)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2CCTL1 (HWREG16(0x40000804)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2CCTL2 (HWREG16(0x40000806)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2CCTL3 (HWREG16(0x40000808)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2CCTL4 (HWREG16(0x4000080A)) /*!< Timer_A Capture/Compare Control Register */ -#define TA2R (HWREG16(0x40000810)) /*!< TimerA register */ -#define TA2CCR0 (HWREG16(0x40000812)) /*!< Timer_A Capture/Compare Register */ -#define TA2CCR1 (HWREG16(0x40000814)) /*!< Timer_A Capture/Compare Register */ -#define TA2CCR2 (HWREG16(0x40000816)) /*!< Timer_A Capture/Compare Register */ -#define TA2CCR3 (HWREG16(0x40000818)) /*!< Timer_A Capture/Compare Register */ -#define TA2CCR4 (HWREG16(0x4000081A)) /*!< Timer_A Capture/Compare Register */ -#define TA2EX0 (HWREG16(0x40000820)) /*!< TimerAx Expansion 0 Register */ -#define TA2IV (HWREG16(0x4000082E)) /*!< TimerAx Interrupt Vector Register */ - -/* Register offsets from TIMER_A2_BASE address */ -#define OFS_TA2CTL (0x0000) /*!< TimerAx Control Register */ -#define OFS_TA2CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA2R (0x0010) /*!< TimerA register */ -#define OFS_TA2CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA2EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ -#define OFS_TA2IV (0x002E) /*!< TimerAx Interrupt Vector Register */ - - -/****************************************************************************** -* TIMER_A3 Registers -******************************************************************************/ -#define TA3CTL (HWREG16(0x40000C00)) /*!< TimerAx Control Register */ -#define TA3CCTL0 (HWREG16(0x40000C02)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3CCTL1 (HWREG16(0x40000C04)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3CCTL2 (HWREG16(0x40000C06)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3CCTL3 (HWREG16(0x40000C08)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3CCTL4 (HWREG16(0x40000C0A)) /*!< Timer_A Capture/Compare Control Register */ -#define TA3R (HWREG16(0x40000C10)) /*!< TimerA register */ -#define TA3CCR0 (HWREG16(0x40000C12)) /*!< Timer_A Capture/Compare Register */ -#define TA3CCR1 (HWREG16(0x40000C14)) /*!< Timer_A Capture/Compare Register */ -#define TA3CCR2 (HWREG16(0x40000C16)) /*!< Timer_A Capture/Compare Register */ -#define TA3CCR3 (HWREG16(0x40000C18)) /*!< Timer_A Capture/Compare Register */ -#define TA3CCR4 (HWREG16(0x40000C1A)) /*!< Timer_A Capture/Compare Register */ -#define TA3EX0 (HWREG16(0x40000C20)) /*!< TimerAx Expansion 0 Register */ -#define TA3IV (HWREG16(0x40000C2E)) /*!< TimerAx Interrupt Vector Register */ - -/* Register offsets from TIMER_A3_BASE address */ -#define OFS_TA3CTL (0x0000) /*!< TimerAx Control Register */ -#define OFS_TA3CCTL0 (0x0002) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3CCTL1 (0x0004) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3CCTL2 (0x0006) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3CCTL3 (0x0008) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3CCTL4 (0x000A) /*!< Timer_A Capture/Compare Control Register */ -#define OFS_TA3R (0x0010) /*!< TimerA register */ -#define OFS_TA3CCR0 (0x0012) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3CCR1 (0x0014) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3CCR2 (0x0016) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3CCR3 (0x0018) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3CCR4 (0x001A) /*!< Timer_A Capture/Compare Register */ -#define OFS_TA3EX0 (0x0020) /*!< TimerAx Expansion 0 Register */ -#define OFS_TA3IV (0x002E) /*!< TimerAx Interrupt Vector Register */ - - -/****************************************************************************** -* WDT_A Registers -******************************************************************************/ -#define WDTCTL (HWREG16(0x4000480C)) /*!< Watchdog Timer Control Register */ - -/* Register offsets from WDT_A_BASE address */ -#define OFS_WDTCTL (0x000C) /*!< Watchdog Timer Control Register */ - - -/****************************************************************************** -* Peripheral register control bits (legacy section) * -******************************************************************************/ - -/****************************************************************************** -* AES256 Bits (legacy section) -******************************************************************************/ -/* AESACTL0[AESOP] Bits */ -#define AESOP_OFS AES256_CTL0_OP_OFS /*!< AESOP Offset */ -#define AESOP_M AES256_CTL0_OP_MASK /*!< AES operation */ -#define AESOP0 AES256_CTL0_OP0 /*!< AESOP Bit 0 */ -#define AESOP1 AES256_CTL0_OP1 /*!< AESOP Bit 1 */ -#define AESOP_0 AES256_CTL0_OP_0 /*!< Encryption */ -#define AESOP_1 AES256_CTL0_OP_1 /*!< Decryption. The provided key is the same key used for encryption */ -#define AESOP_2 AES256_CTL0_OP_2 /*!< Generate first round key required for decryption */ -#define AESOP_3 AES256_CTL0_OP_3 /*!< Decryption. The provided key is the first round key required for decryption */ -/* AESACTL0[AESKL] Bits */ -#define AESKL_OFS AES256_CTL0_KL_OFS /*!< AESKL Offset */ -#define AESKL_M AES256_CTL0_KL_MASK /*!< AES key length */ -#define AESKL0 AES256_CTL0_KL0 /*!< AESKL Bit 0 */ -#define AESKL1 AES256_CTL0_KL1 /*!< AESKL Bit 1 */ -#define AESKL_0 AES256_CTL0_KL_0 /*!< AES128. The key size is 128 bit */ -#define AESKL_1 AES256_CTL0_KL_1 /*!< AES192. The key size is 192 bit. */ -#define AESKL_2 AES256_CTL0_KL_2 /*!< AES256. The key size is 256 bit */ -#define AESKL__128BIT AES256_CTL0_KL__128BIT /*!< AES128. The key size is 128 bit */ -#define AESKL__192BIT AES256_CTL0_KL__192BIT /*!< AES192. The key size is 192 bit. */ -#define AESKL__256BIT AES256_CTL0_KL__256BIT /*!< AES256. The key size is 256 bit */ -/* AESACTL0[AESCM] Bits */ -#define AESCM_OFS AES256_CTL0_CM_OFS /*!< AESCM Offset */ -#define AESCM_M AES256_CTL0_CM_MASK /*!< AES cipher mode select */ -#define AESCM0 AES256_CTL0_CM0 /*!< AESCM Bit 0 */ -#define AESCM1 AES256_CTL0_CM1 /*!< AESCM Bit 1 */ -#define AESCM_0 AES256_CTL0_CM_0 /*!< ECB */ -#define AESCM_1 AES256_CTL0_CM_1 /*!< CBC */ -#define AESCM_2 AES256_CTL0_CM_2 /*!< OFB */ -#define AESCM_3 AES256_CTL0_CM_3 /*!< CFB */ -#define AESCM__ECB AES256_CTL0_CM__ECB /*!< ECB */ -#define AESCM__CBC AES256_CTL0_CM__CBC /*!< CBC */ -#define AESCM__OFB AES256_CTL0_CM__OFB /*!< OFB */ -#define AESCM__CFB AES256_CTL0_CM__CFB /*!< CFB */ -/* AESACTL0[AESSWRST] Bits */ -#define AESSWRST_OFS AES256_CTL0_SWRST_OFS /*!< AESSWRST Offset */ -#define AESSWRST AES256_CTL0_SWRST /*!< AES software reset */ -/* AESACTL0[AESRDYIFG] Bits */ -#define AESRDYIFG_OFS AES256_CTL0_RDYIFG_OFS /*!< AESRDYIFG Offset */ -#define AESRDYIFG AES256_CTL0_RDYIFG /*!< AES ready interrupt flag */ -/* AESACTL0[AESERRFG] Bits */ -#define AESERRFG_OFS AES256_CTL0_ERRFG_OFS /*!< AESERRFG Offset */ -#define AESERRFG AES256_CTL0_ERRFG /*!< AES error flag */ -/* AESACTL0[AESRDYIE] Bits */ -#define AESRDYIE_OFS AES256_CTL0_RDYIE_OFS /*!< AESRDYIE Offset */ -#define AESRDYIE AES256_CTL0_RDYIE /*!< AES ready interrupt enable */ -/* AESACTL0[AESCMEN] Bits */ -#define AESCMEN_OFS AES256_CTL0_CMEN_OFS /*!< AESCMEN Offset */ -#define AESCMEN AES256_CTL0_CMEN /*!< AES cipher mode enable */ -/* AESACTL1[AESBLKCNT] Bits */ -#define AESBLKCNT_OFS AES256_CTL1_BLKCNT_OFS /*!< AESBLKCNT Offset */ -#define AESBLKCNT_M AES256_CTL1_BLKCNT_MASK /*!< Cipher Block Counter */ -#define AESBLKCNT0 AES256_CTL1_BLKCNT0 /*!< AESBLKCNT Bit 0 */ -#define AESBLKCNT1 AES256_CTL1_BLKCNT1 /*!< AESBLKCNT Bit 1 */ -#define AESBLKCNT2 AES256_CTL1_BLKCNT2 /*!< AESBLKCNT Bit 2 */ -#define AESBLKCNT3 AES256_CTL1_BLKCNT3 /*!< AESBLKCNT Bit 3 */ -#define AESBLKCNT4 AES256_CTL1_BLKCNT4 /*!< AESBLKCNT Bit 4 */ -#define AESBLKCNT5 AES256_CTL1_BLKCNT5 /*!< AESBLKCNT Bit 5 */ -#define AESBLKCNT6 AES256_CTL1_BLKCNT6 /*!< AESBLKCNT Bit 6 */ -#define AESBLKCNT7 AES256_CTL1_BLKCNT7 /*!< AESBLKCNT Bit 7 */ -/* AESASTAT[AESBUSY] Bits */ -#define AESBUSY_OFS AES256_STAT_BUSY_OFS /*!< AESBUSY Offset */ -#define AESBUSY AES256_STAT_BUSY /*!< AES accelerator module busy */ -/* AESASTAT[AESKEYWR] Bits */ -#define AESKEYWR_OFS AES256_STAT_KEYWR_OFS /*!< AESKEYWR Offset */ -#define AESKEYWR AES256_STAT_KEYWR /*!< All 16 bytes written to AESAKEY */ -/* AESASTAT[AESDINWR] Bits */ -#define AESDINWR_OFS AES256_STAT_DINWR_OFS /*!< AESDINWR Offset */ -#define AESDINWR AES256_STAT_DINWR /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ -/* AESASTAT[AESDOUTRD] Bits */ -#define AESDOUTRD_OFS AES256_STAT_DOUTRD_OFS /*!< AESDOUTRD Offset */ -#define AESDOUTRD AES256_STAT_DOUTRD /*!< All 16 bytes read from AESADOUT */ -/* AESASTAT[AESKEYCNT] Bits */ -#define AESKEYCNT_OFS AES256_STAT_KEYCNT_OFS /*!< AESKEYCNT Offset */ -#define AESKEYCNT_M AES256_STAT_KEYCNT_MASK /*!< Bytes written via AESAKEY for AESKLx=00, half-words written via AESAKEY */ -#define AESKEYCNT0 AES256_STAT_KEYCNT0 /*!< AESKEYCNT Bit 0 */ -#define AESKEYCNT1 AES256_STAT_KEYCNT1 /*!< AESKEYCNT Bit 1 */ -#define AESKEYCNT2 AES256_STAT_KEYCNT2 /*!< AESKEYCNT Bit 2 */ -#define AESKEYCNT3 AES256_STAT_KEYCNT3 /*!< AESKEYCNT Bit 3 */ -/* AESASTAT[AESDINCNT] Bits */ -#define AESDINCNT_OFS AES256_STAT_DINCNT_OFS /*!< AESDINCNT Offset */ -#define AESDINCNT_M AES256_STAT_DINCNT_MASK /*!< Bytes written via AESADIN, AESAXDIN or AESAXIN */ -#define AESDINCNT0 AES256_STAT_DINCNT0 /*!< AESDINCNT Bit 0 */ -#define AESDINCNT1 AES256_STAT_DINCNT1 /*!< AESDINCNT Bit 1 */ -#define AESDINCNT2 AES256_STAT_DINCNT2 /*!< AESDINCNT Bit 2 */ -#define AESDINCNT3 AES256_STAT_DINCNT3 /*!< AESDINCNT Bit 3 */ -/* AESASTAT[AESDOUTCNT] Bits */ -#define AESDOUTCNT_OFS AES256_STAT_DOUTCNT_OFS /*!< AESDOUTCNT Offset */ -#define AESDOUTCNT_M AES256_STAT_DOUTCNT_MASK /*!< Bytes read via AESADOUT */ -#define AESDOUTCNT0 AES256_STAT_DOUTCNT0 /*!< AESDOUTCNT Bit 0 */ -#define AESDOUTCNT1 AES256_STAT_DOUTCNT1 /*!< AESDOUTCNT Bit 1 */ -#define AESDOUTCNT2 AES256_STAT_DOUTCNT2 /*!< AESDOUTCNT Bit 2 */ -#define AESDOUTCNT3 AES256_STAT_DOUTCNT3 /*!< AESDOUTCNT Bit 3 */ -/* AESAKEY[AESKEY0] Bits */ -#define AESKEY0_OFS AES256_KEY_KEY0_OFS /*!< AESKEY0 Offset */ -#define AESKEY0_M AES256_KEY_KEY0_MASK /*!< AES key byte n when AESAKEY is written as half-word */ -#define AESKEY00 AES256_KEY_KEY00 /*!< AESKEY0 Bit 0 */ -#define AESKEY01 AES256_KEY_KEY01 /*!< AESKEY0 Bit 1 */ -#define AESKEY02 AES256_KEY_KEY02 /*!< AESKEY0 Bit 2 */ -#define AESKEY03 AES256_KEY_KEY03 /*!< AESKEY0 Bit 3 */ -#define AESKEY04 AES256_KEY_KEY04 /*!< AESKEY0 Bit 4 */ -#define AESKEY05 AES256_KEY_KEY05 /*!< AESKEY0 Bit 5 */ -#define AESKEY06 AES256_KEY_KEY06 /*!< AESKEY0 Bit 6 */ -#define AESKEY07 AES256_KEY_KEY07 /*!< AESKEY0 Bit 7 */ -/* AESAKEY[AESKEY1] Bits */ -#define AESKEY1_OFS AES256_KEY_KEY1_OFS /*!< AESKEY1 Offset */ -#define AESKEY1_M AES256_KEY_KEY1_MASK /*!< AES key byte n+1 when AESAKEY is written as half-word */ -#define AESKEY10 AES256_KEY_KEY10 /*!< AESKEY1 Bit 0 */ -#define AESKEY11 AES256_KEY_KEY11 /*!< AESKEY1 Bit 1 */ -#define AESKEY12 AES256_KEY_KEY12 /*!< AESKEY1 Bit 2 */ -#define AESKEY13 AES256_KEY_KEY13 /*!< AESKEY1 Bit 3 */ -#define AESKEY14 AES256_KEY_KEY14 /*!< AESKEY1 Bit 4 */ -#define AESKEY15 AES256_KEY_KEY15 /*!< AESKEY1 Bit 5 */ -#define AESKEY16 AES256_KEY_KEY16 /*!< AESKEY1 Bit 6 */ -#define AESKEY17 AES256_KEY_KEY17 /*!< AESKEY1 Bit 7 */ -/* AESADIN[AESDIN0] Bits */ -#define AESDIN0_OFS AES256_DIN_DIN0_OFS /*!< AESDIN0 Offset */ -#define AESDIN0_M AES256_DIN_DIN0_MASK /*!< AES data in byte n when AESADIN is written as half-word */ -#define AESDIN00 AES256_DIN_DIN00 /*!< AESDIN0 Bit 0 */ -#define AESDIN01 AES256_DIN_DIN01 /*!< AESDIN0 Bit 1 */ -#define AESDIN02 AES256_DIN_DIN02 /*!< AESDIN0 Bit 2 */ -#define AESDIN03 AES256_DIN_DIN03 /*!< AESDIN0 Bit 3 */ -#define AESDIN04 AES256_DIN_DIN04 /*!< AESDIN0 Bit 4 */ -#define AESDIN05 AES256_DIN_DIN05 /*!< AESDIN0 Bit 5 */ -#define AESDIN06 AES256_DIN_DIN06 /*!< AESDIN0 Bit 6 */ -#define AESDIN07 AES256_DIN_DIN07 /*!< AESDIN0 Bit 7 */ -/* AESADIN[AESDIN1] Bits */ -#define AESDIN1_OFS AES256_DIN_DIN1_OFS /*!< AESDIN1 Offset */ -#define AESDIN1_M AES256_DIN_DIN1_MASK /*!< AES data in byte n+1 when AESADIN is written as half-word */ -#define AESDIN10 AES256_DIN_DIN10 /*!< AESDIN1 Bit 0 */ -#define AESDIN11 AES256_DIN_DIN11 /*!< AESDIN1 Bit 1 */ -#define AESDIN12 AES256_DIN_DIN12 /*!< AESDIN1 Bit 2 */ -#define AESDIN13 AES256_DIN_DIN13 /*!< AESDIN1 Bit 3 */ -#define AESDIN14 AES256_DIN_DIN14 /*!< AESDIN1 Bit 4 */ -#define AESDIN15 AES256_DIN_DIN15 /*!< AESDIN1 Bit 5 */ -#define AESDIN16 AES256_DIN_DIN16 /*!< AESDIN1 Bit 6 */ -#define AESDIN17 AES256_DIN_DIN17 /*!< AESDIN1 Bit 7 */ -/* AESADOUT[AESDOUT0] Bits */ -#define AESDOUT0_OFS AES256_DOUT_DOUT0_OFS /*!< AESDOUT0 Offset */ -#define AESDOUT0_M AES256_DOUT_DOUT0_MASK /*!< AES data out byte n when AESADOUT is read as half-word */ -#define AESDOUT00 AES256_DOUT_DOUT00 /*!< AESDOUT0 Bit 0 */ -#define AESDOUT01 AES256_DOUT_DOUT01 /*!< AESDOUT0 Bit 1 */ -#define AESDOUT02 AES256_DOUT_DOUT02 /*!< AESDOUT0 Bit 2 */ -#define AESDOUT03 AES256_DOUT_DOUT03 /*!< AESDOUT0 Bit 3 */ -#define AESDOUT04 AES256_DOUT_DOUT04 /*!< AESDOUT0 Bit 4 */ -#define AESDOUT05 AES256_DOUT_DOUT05 /*!< AESDOUT0 Bit 5 */ -#define AESDOUT06 AES256_DOUT_DOUT06 /*!< AESDOUT0 Bit 6 */ -#define AESDOUT07 AES256_DOUT_DOUT07 /*!< AESDOUT0 Bit 7 */ -/* AESADOUT[AESDOUT1] Bits */ -#define AESDOUT1_OFS AES256_DOUT_DOUT1_OFS /*!< AESDOUT1 Offset */ -#define AESDOUT1_M AES256_DOUT_DOUT1_MASK /*!< AES data out byte n+1 when AESADOUT is read as half-word */ -#define AESDOUT10 AES256_DOUT_DOUT10 /*!< AESDOUT1 Bit 0 */ -#define AESDOUT11 AES256_DOUT_DOUT11 /*!< AESDOUT1 Bit 1 */ -#define AESDOUT12 AES256_DOUT_DOUT12 /*!< AESDOUT1 Bit 2 */ -#define AESDOUT13 AES256_DOUT_DOUT13 /*!< AESDOUT1 Bit 3 */ -#define AESDOUT14 AES256_DOUT_DOUT14 /*!< AESDOUT1 Bit 4 */ -#define AESDOUT15 AES256_DOUT_DOUT15 /*!< AESDOUT1 Bit 5 */ -#define AESDOUT16 AES256_DOUT_DOUT16 /*!< AESDOUT1 Bit 6 */ -#define AESDOUT17 AES256_DOUT_DOUT17 /*!< AESDOUT1 Bit 7 */ -/* AESAXDIN[AESXDIN0] Bits */ -#define AESXDIN0_OFS AES256_XDIN_XDIN0_OFS /*!< AESXDIN0 Offset */ -#define AESXDIN0_M AES256_XDIN_XDIN0_MASK /*!< AES data in byte n when AESAXDIN is written as half-word */ -#define AESXDIN00 AES256_XDIN_XDIN00 /*!< AESXDIN0 Bit 0 */ -#define AESXDIN01 AES256_XDIN_XDIN01 /*!< AESXDIN0 Bit 1 */ -#define AESXDIN02 AES256_XDIN_XDIN02 /*!< AESXDIN0 Bit 2 */ -#define AESXDIN03 AES256_XDIN_XDIN03 /*!< AESXDIN0 Bit 3 */ -#define AESXDIN04 AES256_XDIN_XDIN04 /*!< AESXDIN0 Bit 4 */ -#define AESXDIN05 AES256_XDIN_XDIN05 /*!< AESXDIN0 Bit 5 */ -#define AESXDIN06 AES256_XDIN_XDIN06 /*!< AESXDIN0 Bit 6 */ -#define AESXDIN07 AES256_XDIN_XDIN07 /*!< AESXDIN0 Bit 7 */ -/* AESAXDIN[AESXDIN1] Bits */ -#define AESXDIN1_OFS AES256_XDIN_XDIN1_OFS /*!< AESXDIN1 Offset */ -#define AESXDIN1_M AES256_XDIN_XDIN1_MASK /*!< AES data in byte n+1 when AESAXDIN is written as half-word */ -#define AESXDIN10 AES256_XDIN_XDIN10 /*!< AESXDIN1 Bit 0 */ -#define AESXDIN11 AES256_XDIN_XDIN11 /*!< AESXDIN1 Bit 1 */ -#define AESXDIN12 AES256_XDIN_XDIN12 /*!< AESXDIN1 Bit 2 */ -#define AESXDIN13 AES256_XDIN_XDIN13 /*!< AESXDIN1 Bit 3 */ -#define AESXDIN14 AES256_XDIN_XDIN14 /*!< AESXDIN1 Bit 4 */ -#define AESXDIN15 AES256_XDIN_XDIN15 /*!< AESXDIN1 Bit 5 */ -#define AESXDIN16 AES256_XDIN_XDIN16 /*!< AESXDIN1 Bit 6 */ -#define AESXDIN17 AES256_XDIN_XDIN17 /*!< AESXDIN1 Bit 7 */ -/* AESAXIN[AESXIN0] Bits */ -#define AESXIN0_OFS AES256_XIN_XIN0_OFS /*!< AESXIN0 Offset */ -#define AESXIN0_M AES256_XIN_XIN0_MASK /*!< AES data in byte n when AESAXIN is written as half-word */ -#define AESXIN00 AES256_XIN_XIN00 /*!< AESXIN0 Bit 0 */ -#define AESXIN01 AES256_XIN_XIN01 /*!< AESXIN0 Bit 1 */ -#define AESXIN02 AES256_XIN_XIN02 /*!< AESXIN0 Bit 2 */ -#define AESXIN03 AES256_XIN_XIN03 /*!< AESXIN0 Bit 3 */ -#define AESXIN04 AES256_XIN_XIN04 /*!< AESXIN0 Bit 4 */ -#define AESXIN05 AES256_XIN_XIN05 /*!< AESXIN0 Bit 5 */ -#define AESXIN06 AES256_XIN_XIN06 /*!< AESXIN0 Bit 6 */ -#define AESXIN07 AES256_XIN_XIN07 /*!< AESXIN0 Bit 7 */ -/* AESAXIN[AESXIN1] Bits */ -#define AESXIN1_OFS AES256_XIN_XIN1_OFS /*!< AESXIN1 Offset */ -#define AESXIN1_M AES256_XIN_XIN1_MASK /*!< AES data in byte n+1 when AESAXIN is written as half-word */ -#define AESXIN10 AES256_XIN_XIN10 /*!< AESXIN1 Bit 0 */ -#define AESXIN11 AES256_XIN_XIN11 /*!< AESXIN1 Bit 1 */ -#define AESXIN12 AES256_XIN_XIN12 /*!< AESXIN1 Bit 2 */ -#define AESXIN13 AES256_XIN_XIN13 /*!< AESXIN1 Bit 3 */ -#define AESXIN14 AES256_XIN_XIN14 /*!< AESXIN1 Bit 4 */ -#define AESXIN15 AES256_XIN_XIN15 /*!< AESXIN1 Bit 5 */ -#define AESXIN16 AES256_XIN_XIN16 /*!< AESXIN1 Bit 6 */ -#define AESXIN17 AES256_XIN_XIN17 /*!< AESXIN1 Bit 7 */ - -/****************************************************************************** -* CAPTIO Bits (legacy section) -******************************************************************************/ -/* CAPTIO0CTL[CAPTIOPISEL] Bits */ -#define CAPTIOPISEL_OFS CAPTIO_CTL_PISEL_OFS /*!< CAPTIOPISEL Offset */ -#define CAPTIOPISEL_M CAPTIO_CTL_PISEL_MASK /*!< Capacitive Touch IO pin select */ -#define CAPTIOPISEL0 CAPTIO_CTL_PISEL0 /*!< CAPTIOPISEL Bit 0 */ -#define CAPTIOPISEL1 CAPTIO_CTL_PISEL1 /*!< CAPTIOPISEL Bit 1 */ -#define CAPTIOPISEL2 CAPTIO_CTL_PISEL2 /*!< CAPTIOPISEL Bit 2 */ -#define CAPTIOPISEL_0 CAPTIO_CTL_PISEL_0 /*!< Px.0 */ -#define CAPTIOPISEL_1 CAPTIO_CTL_PISEL_1 /*!< Px.1 */ -#define CAPTIOPISEL_2 CAPTIO_CTL_PISEL_2 /*!< Px.2 */ -#define CAPTIOPISEL_3 CAPTIO_CTL_PISEL_3 /*!< Px.3 */ -#define CAPTIOPISEL_4 CAPTIO_CTL_PISEL_4 /*!< Px.4 */ -#define CAPTIOPISEL_5 CAPTIO_CTL_PISEL_5 /*!< Px.5 */ -#define CAPTIOPISEL_6 CAPTIO_CTL_PISEL_6 /*!< Px.6 */ -#define CAPTIOPISEL_7 CAPTIO_CTL_PISEL_7 /*!< Px.7 */ -/* CAPTIO0CTL[CAPTIOPOSEL] Bits */ -#define CAPTIOPOSEL_OFS CAPTIO_CTL_POSEL_OFS /*!< CAPTIOPOSEL Offset */ -#define CAPTIOPOSEL_M CAPTIO_CTL_POSEL_MASK /*!< Capacitive Touch IO port select */ -#define CAPTIOPOSEL0 CAPTIO_CTL_POSEL0 /*!< CAPTIOPOSEL Bit 0 */ -#define CAPTIOPOSEL1 CAPTIO_CTL_POSEL1 /*!< CAPTIOPOSEL Bit 1 */ -#define CAPTIOPOSEL2 CAPTIO_CTL_POSEL2 /*!< CAPTIOPOSEL Bit 2 */ -#define CAPTIOPOSEL3 CAPTIO_CTL_POSEL3 /*!< CAPTIOPOSEL Bit 3 */ -#define CAPTIOPOSEL_0 CAPTIO_CTL_POSEL_0 /*!< Px = PJ */ -#define CAPTIOPOSEL_1 CAPTIO_CTL_POSEL_1 /*!< Px = P1 */ -#define CAPTIOPOSEL_2 CAPTIO_CTL_POSEL_2 /*!< Px = P2 */ -#define CAPTIOPOSEL_3 CAPTIO_CTL_POSEL_3 /*!< Px = P3 */ -#define CAPTIOPOSEL_4 CAPTIO_CTL_POSEL_4 /*!< Px = P4 */ -#define CAPTIOPOSEL_5 CAPTIO_CTL_POSEL_5 /*!< Px = P5 */ -#define CAPTIOPOSEL_6 CAPTIO_CTL_POSEL_6 /*!< Px = P6 */ -#define CAPTIOPOSEL_7 CAPTIO_CTL_POSEL_7 /*!< Px = P7 */ -#define CAPTIOPOSEL_8 CAPTIO_CTL_POSEL_8 /*!< Px = P8 */ -#define CAPTIOPOSEL_9 CAPTIO_CTL_POSEL_9 /*!< Px = P9 */ -#define CAPTIOPOSEL_10 CAPTIO_CTL_POSEL_10 /*!< Px = P10 */ -#define CAPTIOPOSEL_11 CAPTIO_CTL_POSEL_11 /*!< Px = P11 */ -#define CAPTIOPOSEL_12 CAPTIO_CTL_POSEL_12 /*!< Px = P12 */ -#define CAPTIOPOSEL_13 CAPTIO_CTL_POSEL_13 /*!< Px = P13 */ -#define CAPTIOPOSEL_14 CAPTIO_CTL_POSEL_14 /*!< Px = P14 */ -#define CAPTIOPOSEL_15 CAPTIO_CTL_POSEL_15 /*!< Px = P15 */ -#define CAPTIOPOSEL__PJ CAPTIO_CTL_POSEL__PJ /*!< Px = PJ */ -#define CAPTIOPOSEL__P1 CAPTIO_CTL_POSEL__P1 /*!< Px = P1 */ -#define CAPTIOPOSEL__P2 CAPTIO_CTL_POSEL__P2 /*!< Px = P2 */ -#define CAPTIOPOSEL__P3 CAPTIO_CTL_POSEL__P3 /*!< Px = P3 */ -#define CAPTIOPOSEL__P4 CAPTIO_CTL_POSEL__P4 /*!< Px = P4 */ -#define CAPTIOPOSEL__P5 CAPTIO_CTL_POSEL__P5 /*!< Px = P5 */ -#define CAPTIOPOSEL__P6 CAPTIO_CTL_POSEL__P6 /*!< Px = P6 */ -#define CAPTIOPOSEL__P7 CAPTIO_CTL_POSEL__P7 /*!< Px = P7 */ -#define CAPTIOPOSEL__P8 CAPTIO_CTL_POSEL__P8 /*!< Px = P8 */ -#define CAPTIOPOSEL__P9 CAPTIO_CTL_POSEL__P9 /*!< Px = P9 */ -#define CAPTIOPOSEL__P10 CAPTIO_CTL_POSEL__P10 /*!< Px = P10 */ -#define CAPTIOPOSEL__P11 CAPTIO_CTL_POSEL__P11 /*!< Px = P11 */ -#define CAPTIOPOSEL__P12 CAPTIO_CTL_POSEL__P12 /*!< Px = P12 */ -#define CAPTIOPOSEL__P13 CAPTIO_CTL_POSEL__P13 /*!< Px = P13 */ -#define CAPTIOPOSEL__P14 CAPTIO_CTL_POSEL__P14 /*!< Px = P14 */ -#define CAPTIOPOSEL__P15 CAPTIO_CTL_POSEL__P15 /*!< Px = P15 */ -/* CAPTIO0CTL[CAPTIOEN] Bits */ -#define CAPTIOEN_OFS CAPTIO_CTL_EN_OFS /*!< CAPTIOEN Offset */ -#define CAPTIOEN CAPTIO_CTL_EN /*!< Capacitive Touch IO enable */ -/* CAPTIO0CTL[CAPTIOSTATE] Bits */ -#define CAPTIOSTATE_OFS CAPTIO_CTL_STATE_OFS /*!< CAPTIOSTATE Offset */ -#define CAPTIOSTATE CAPTIO_CTL_STATE /*!< Capacitive Touch IO state */ - -/****************************************************************************** -* COMP_E Bits (legacy section) -******************************************************************************/ -/* CE0CTL0[CEIPSEL] Bits */ -#define CEIPSEL_OFS COMP_E_CTL0_IPSEL_OFS /*!< CEIPSEL Offset */ -#define CEIPSEL_M COMP_E_CTL0_IPSEL_MASK /*!< Channel input selected for the V+ terminal */ -#define CEIPSEL0 COMP_E_CTL0_IPSEL0 /*!< CEIPSEL Bit 0 */ -#define CEIPSEL1 COMP_E_CTL0_IPSEL1 /*!< CEIPSEL Bit 1 */ -#define CEIPSEL2 COMP_E_CTL0_IPSEL2 /*!< CEIPSEL Bit 2 */ -#define CEIPSEL3 COMP_E_CTL0_IPSEL3 /*!< CEIPSEL Bit 3 */ -#define CEIPSEL_0 COMP_E_CTL0_IPSEL_0 /*!< Channel 0 selected */ -#define CEIPSEL_1 COMP_E_CTL0_IPSEL_1 /*!< Channel 1 selected */ -#define CEIPSEL_2 COMP_E_CTL0_IPSEL_2 /*!< Channel 2 selected */ -#define CEIPSEL_3 COMP_E_CTL0_IPSEL_3 /*!< Channel 3 selected */ -#define CEIPSEL_4 COMP_E_CTL0_IPSEL_4 /*!< Channel 4 selected */ -#define CEIPSEL_5 COMP_E_CTL0_IPSEL_5 /*!< Channel 5 selected */ -#define CEIPSEL_6 COMP_E_CTL0_IPSEL_6 /*!< Channel 6 selected */ -#define CEIPSEL_7 COMP_E_CTL0_IPSEL_7 /*!< Channel 7 selected */ -#define CEIPSEL_8 COMP_E_CTL0_IPSEL_8 /*!< Channel 8 selected */ -#define CEIPSEL_9 COMP_E_CTL0_IPSEL_9 /*!< Channel 9 selected */ -#define CEIPSEL_10 COMP_E_CTL0_IPSEL_10 /*!< Channel 10 selected */ -#define CEIPSEL_11 COMP_E_CTL0_IPSEL_11 /*!< Channel 11 selected */ -#define CEIPSEL_12 COMP_E_CTL0_IPSEL_12 /*!< Channel 12 selected */ -#define CEIPSEL_13 COMP_E_CTL0_IPSEL_13 /*!< Channel 13 selected */ -#define CEIPSEL_14 COMP_E_CTL0_IPSEL_14 /*!< Channel 14 selected */ -#define CEIPSEL_15 COMP_E_CTL0_IPSEL_15 /*!< Channel 15 selected */ -/* CE0CTL0[CEIPEN] Bits */ -#define CEIPEN_OFS COMP_E_CTL0_IPEN_OFS /*!< CEIPEN Offset */ -#define CEIPEN COMP_E_CTL0_IPEN /*!< Channel input enable for the V+ terminal */ -/* CE0CTL0[CEIMSEL] Bits */ -#define CEIMSEL_OFS COMP_E_CTL0_IMSEL_OFS /*!< CEIMSEL Offset */ -#define CEIMSEL_M COMP_E_CTL0_IMSEL_MASK /*!< Channel input selected for the - terminal */ -#define CEIMSEL0 COMP_E_CTL0_IMSEL0 /*!< CEIMSEL Bit 0 */ -#define CEIMSEL1 COMP_E_CTL0_IMSEL1 /*!< CEIMSEL Bit 1 */ -#define CEIMSEL2 COMP_E_CTL0_IMSEL2 /*!< CEIMSEL Bit 2 */ -#define CEIMSEL3 COMP_E_CTL0_IMSEL3 /*!< CEIMSEL Bit 3 */ -#define CEIMSEL_0 COMP_E_CTL0_IMSEL_0 /*!< Channel 0 selected */ -#define CEIMSEL_1 COMP_E_CTL0_IMSEL_1 /*!< Channel 1 selected */ -#define CEIMSEL_2 COMP_E_CTL0_IMSEL_2 /*!< Channel 2 selected */ -#define CEIMSEL_3 COMP_E_CTL0_IMSEL_3 /*!< Channel 3 selected */ -#define CEIMSEL_4 COMP_E_CTL0_IMSEL_4 /*!< Channel 4 selected */ -#define CEIMSEL_5 COMP_E_CTL0_IMSEL_5 /*!< Channel 5 selected */ -#define CEIMSEL_6 COMP_E_CTL0_IMSEL_6 /*!< Channel 6 selected */ -#define CEIMSEL_7 COMP_E_CTL0_IMSEL_7 /*!< Channel 7 selected */ -#define CEIMSEL_8 COMP_E_CTL0_IMSEL_8 /*!< Channel 8 selected */ -#define CEIMSEL_9 COMP_E_CTL0_IMSEL_9 /*!< Channel 9 selected */ -#define CEIMSEL_10 COMP_E_CTL0_IMSEL_10 /*!< Channel 10 selected */ -#define CEIMSEL_11 COMP_E_CTL0_IMSEL_11 /*!< Channel 11 selected */ -#define CEIMSEL_12 COMP_E_CTL0_IMSEL_12 /*!< Channel 12 selected */ -#define CEIMSEL_13 COMP_E_CTL0_IMSEL_13 /*!< Channel 13 selected */ -#define CEIMSEL_14 COMP_E_CTL0_IMSEL_14 /*!< Channel 14 selected */ -#define CEIMSEL_15 COMP_E_CTL0_IMSEL_15 /*!< Channel 15 selected */ -/* CE0CTL0[CEIMEN] Bits */ -#define CEIMEN_OFS COMP_E_CTL0_IMEN_OFS /*!< CEIMEN Offset */ -#define CEIMEN COMP_E_CTL0_IMEN /*!< Channel input enable for the - terminal */ -/* CE0CTL1[CEOUT] Bits */ -#define CEOUT_OFS COMP_E_CTL1_OUT_OFS /*!< CEOUT Offset */ -#define CEOUT COMP_E_CTL1_OUT /*!< Comparator output value */ -/* CE0CTL1[CEOUTPOL] Bits */ -#define CEOUTPOL_OFS COMP_E_CTL1_OUTPOL_OFS /*!< CEOUTPOL Offset */ -#define CEOUTPOL COMP_E_CTL1_OUTPOL /*!< Comparator output polarity */ -/* CE0CTL1[CEF] Bits */ -#define CEF_OFS COMP_E_CTL1_F_OFS /*!< CEF Offset */ -#define CEF COMP_E_CTL1_F /*!< Comparator output filter */ -/* CE0CTL1[CEIES] Bits */ -#define CEIES_OFS COMP_E_CTL1_IES_OFS /*!< CEIES Offset */ -#define CEIES COMP_E_CTL1_IES /*!< Interrupt edge select for CEIIFG and CEIFG */ -/* CE0CTL1[CESHORT] Bits */ -#define CESHORT_OFS COMP_E_CTL1_SHORT_OFS /*!< CESHORT Offset */ -#define CESHORT COMP_E_CTL1_SHORT /*!< Input short */ -/* CE0CTL1[CEEX] Bits */ -#define CEEX_OFS COMP_E_CTL1_EX_OFS /*!< CEEX Offset */ -#define CEEX COMP_E_CTL1_EX /*!< Exchange */ -/* CE0CTL1[CEFDLY] Bits */ -#define CEFDLY_OFS COMP_E_CTL1_FDLY_OFS /*!< CEFDLY Offset */ -#define CEFDLY_M COMP_E_CTL1_FDLY_MASK /*!< Filter delay */ -#define CEFDLY0 COMP_E_CTL1_FDLY0 /*!< CEFDLY Bit 0 */ -#define CEFDLY1 COMP_E_CTL1_FDLY1 /*!< CEFDLY Bit 1 */ -#define CEFDLY_0 COMP_E_CTL1_FDLY_0 /*!< Typical filter delay of TBD (450) ns */ -#define CEFDLY_1 COMP_E_CTL1_FDLY_1 /*!< Typical filter delay of TBD (900) ns */ -#define CEFDLY_2 COMP_E_CTL1_FDLY_2 /*!< Typical filter delay of TBD (1800) ns */ -#define CEFDLY_3 COMP_E_CTL1_FDLY_3 /*!< Typical filter delay of TBD (3600) ns */ -/* CE0CTL1[CEPWRMD] Bits */ -#define CEPWRMD_OFS COMP_E_CTL1_PWRMD_OFS /*!< CEPWRMD Offset */ -#define CEPWRMD_M COMP_E_CTL1_PWRMD_MASK /*!< Power Mode */ -#define CEPWRMD0 COMP_E_CTL1_PWRMD0 /*!< CEPWRMD Bit 0 */ -#define CEPWRMD1 COMP_E_CTL1_PWRMD1 /*!< CEPWRMD Bit 1 */ -#define CEPWRMD_0 COMP_E_CTL1_PWRMD_0 /*!< High-speed mode */ -#define CEPWRMD_1 COMP_E_CTL1_PWRMD_1 /*!< Normal mode */ -#define CEPWRMD_2 COMP_E_CTL1_PWRMD_2 /*!< Ultra-low power mode */ -/* CE0CTL1[CEON] Bits */ -#define CEON_OFS COMP_E_CTL1_ON_OFS /*!< CEON Offset */ -#define CEON COMP_E_CTL1_ON /*!< Comparator On */ -/* CE0CTL1[CEMRVL] Bits */ -#define CEMRVL_OFS COMP_E_CTL1_MRVL_OFS /*!< CEMRVL Offset */ -#define CEMRVL COMP_E_CTL1_MRVL /*!< This bit is valid of CEMRVS is set to 1 */ -/* CE0CTL1[CEMRVS] Bits */ -#define CEMRVS_OFS COMP_E_CTL1_MRVS_OFS /*!< CEMRVS Offset */ -#define CEMRVS COMP_E_CTL1_MRVS -/* CE0CTL2[CEREF0] Bits */ -#define CEREF0_OFS COMP_E_CTL2_REF0_OFS /*!< CEREF0 Offset */ -#define CEREF0_M COMP_E_CTL2_REF0_MASK /*!< Reference resistor tap 0 */ -#define CEREF00 COMP_E_CTL2_REF00 /*!< CEREF0 Bit 0 */ -#define CEREF01 COMP_E_CTL2_REF01 /*!< CEREF0 Bit 1 */ -#define CEREF02 COMP_E_CTL2_REF02 /*!< CEREF0 Bit 2 */ -#define CEREF03 COMP_E_CTL2_REF03 /*!< CEREF0 Bit 3 */ -#define CEREF04 COMP_E_CTL2_REF04 /*!< CEREF0 Bit 4 */ -#define CEREF0_0 COMP_E_CTL2_REF0_0 /*!< Reference resistor tap for setting 0. */ -#define CEREF0_1 COMP_E_CTL2_REF0_1 /*!< Reference resistor tap for setting 1. */ -#define CEREF0_2 COMP_E_CTL2_REF0_2 /*!< Reference resistor tap for setting 2. */ -#define CEREF0_3 COMP_E_CTL2_REF0_3 /*!< Reference resistor tap for setting 3. */ -#define CEREF0_4 COMP_E_CTL2_REF0_4 /*!< Reference resistor tap for setting 4. */ -#define CEREF0_5 COMP_E_CTL2_REF0_5 /*!< Reference resistor tap for setting 5. */ -#define CEREF0_6 COMP_E_CTL2_REF0_6 /*!< Reference resistor tap for setting 6. */ -#define CEREF0_7 COMP_E_CTL2_REF0_7 /*!< Reference resistor tap for setting 7. */ -#define CEREF0_8 COMP_E_CTL2_REF0_8 /*!< Reference resistor tap for setting 8. */ -#define CEREF0_9 COMP_E_CTL2_REF0_9 /*!< Reference resistor tap for setting 9. */ -#define CEREF0_10 COMP_E_CTL2_REF0_10 /*!< Reference resistor tap for setting 10. */ -#define CEREF0_11 COMP_E_CTL2_REF0_11 /*!< Reference resistor tap for setting 11. */ -#define CEREF0_12 COMP_E_CTL2_REF0_12 /*!< Reference resistor tap for setting 12. */ -#define CEREF0_13 COMP_E_CTL2_REF0_13 /*!< Reference resistor tap for setting 13. */ -#define CEREF0_14 COMP_E_CTL2_REF0_14 /*!< Reference resistor tap for setting 14. */ -#define CEREF0_15 COMP_E_CTL2_REF0_15 /*!< Reference resistor tap for setting 15. */ -#define CEREF0_16 COMP_E_CTL2_REF0_16 /*!< Reference resistor tap for setting 16. */ -#define CEREF0_17 COMP_E_CTL2_REF0_17 /*!< Reference resistor tap for setting 17. */ -#define CEREF0_18 COMP_E_CTL2_REF0_18 /*!< Reference resistor tap for setting 18. */ -#define CEREF0_19 COMP_E_CTL2_REF0_19 /*!< Reference resistor tap for setting 19. */ -#define CEREF0_20 COMP_E_CTL2_REF0_20 /*!< Reference resistor tap for setting 20. */ -#define CEREF0_21 COMP_E_CTL2_REF0_21 /*!< Reference resistor tap for setting 21. */ -#define CEREF0_22 COMP_E_CTL2_REF0_22 /*!< Reference resistor tap for setting 22. */ -#define CEREF0_23 COMP_E_CTL2_REF0_23 /*!< Reference resistor tap for setting 23. */ -#define CEREF0_24 COMP_E_CTL2_REF0_24 /*!< Reference resistor tap for setting 24. */ -#define CEREF0_25 COMP_E_CTL2_REF0_25 /*!< Reference resistor tap for setting 25. */ -#define CEREF0_26 COMP_E_CTL2_REF0_26 /*!< Reference resistor tap for setting 26. */ -#define CEREF0_27 COMP_E_CTL2_REF0_27 /*!< Reference resistor tap for setting 27. */ -#define CEREF0_28 COMP_E_CTL2_REF0_28 /*!< Reference resistor tap for setting 28. */ -#define CEREF0_29 COMP_E_CTL2_REF0_29 /*!< Reference resistor tap for setting 29. */ -#define CEREF0_30 COMP_E_CTL2_REF0_30 /*!< Reference resistor tap for setting 30. */ -#define CEREF0_31 COMP_E_CTL2_REF0_31 /*!< Reference resistor tap for setting 31. */ -/* CE0CTL2[CERSEL] Bits */ -#define CERSEL_OFS COMP_E_CTL2_RSEL_OFS /*!< CERSEL Offset */ -#define CERSEL COMP_E_CTL2_RSEL /*!< Reference select */ -/* CE0CTL2[CERS] Bits */ -#define CERS_OFS COMP_E_CTL2_RS_OFS /*!< CERS Offset */ -#define CERS_M COMP_E_CTL2_RS_MASK /*!< Reference source */ -#define CERS0 COMP_E_CTL2_RS0 /*!< CERS Bit 0 */ -#define CERS1 COMP_E_CTL2_RS1 /*!< CERS Bit 1 */ -#define CERS_0 COMP_E_CTL2_RS_0 /*!< No current is drawn by the reference circuitry */ -#define CERS_1 COMP_E_CTL2_RS_1 /*!< VCC applied to the resistor ladder */ -#define CERS_2 COMP_E_CTL2_RS_2 /*!< Shared reference voltage applied to the resistor ladder */ -#define CERS_3 COMP_E_CTL2_RS_3 /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ -/* CE0CTL2[CEREF1] Bits */ -#define CEREF1_OFS COMP_E_CTL2_REF1_OFS /*!< CEREF1 Offset */ -#define CEREF1_M COMP_E_CTL2_REF1_MASK /*!< Reference resistor tap 1 */ -#define CEREF10 COMP_E_CTL2_REF10 /*!< CEREF1 Bit 0 */ -#define CEREF11 COMP_E_CTL2_REF11 /*!< CEREF1 Bit 1 */ -#define CEREF12 COMP_E_CTL2_REF12 /*!< CEREF1 Bit 2 */ -#define CEREF13 COMP_E_CTL2_REF13 /*!< CEREF1 Bit 3 */ -#define CEREF14 COMP_E_CTL2_REF14 /*!< CEREF1 Bit 4 */ -#define CEREF1_0 COMP_E_CTL2_REF1_0 /*!< Reference resistor tap for setting 0. */ -#define CEREF1_1 COMP_E_CTL2_REF1_1 /*!< Reference resistor tap for setting 1. */ -#define CEREF1_2 COMP_E_CTL2_REF1_2 /*!< Reference resistor tap for setting 2. */ -#define CEREF1_3 COMP_E_CTL2_REF1_3 /*!< Reference resistor tap for setting 3. */ -#define CEREF1_4 COMP_E_CTL2_REF1_4 /*!< Reference resistor tap for setting 4. */ -#define CEREF1_5 COMP_E_CTL2_REF1_5 /*!< Reference resistor tap for setting 5. */ -#define CEREF1_6 COMP_E_CTL2_REF1_6 /*!< Reference resistor tap for setting 6. */ -#define CEREF1_7 COMP_E_CTL2_REF1_7 /*!< Reference resistor tap for setting 7. */ -#define CEREF1_8 COMP_E_CTL2_REF1_8 /*!< Reference resistor tap for setting 8. */ -#define CEREF1_9 COMP_E_CTL2_REF1_9 /*!< Reference resistor tap for setting 9. */ -#define CEREF1_10 COMP_E_CTL2_REF1_10 /*!< Reference resistor tap for setting 10. */ -#define CEREF1_11 COMP_E_CTL2_REF1_11 /*!< Reference resistor tap for setting 11. */ -#define CEREF1_12 COMP_E_CTL2_REF1_12 /*!< Reference resistor tap for setting 12. */ -#define CEREF1_13 COMP_E_CTL2_REF1_13 /*!< Reference resistor tap for setting 13. */ -#define CEREF1_14 COMP_E_CTL2_REF1_14 /*!< Reference resistor tap for setting 14. */ -#define CEREF1_15 COMP_E_CTL2_REF1_15 /*!< Reference resistor tap for setting 15. */ -#define CEREF1_16 COMP_E_CTL2_REF1_16 /*!< Reference resistor tap for setting 16. */ -#define CEREF1_17 COMP_E_CTL2_REF1_17 /*!< Reference resistor tap for setting 17. */ -#define CEREF1_18 COMP_E_CTL2_REF1_18 /*!< Reference resistor tap for setting 18. */ -#define CEREF1_19 COMP_E_CTL2_REF1_19 /*!< Reference resistor tap for setting 19. */ -#define CEREF1_20 COMP_E_CTL2_REF1_20 /*!< Reference resistor tap for setting 20. */ -#define CEREF1_21 COMP_E_CTL2_REF1_21 /*!< Reference resistor tap for setting 21. */ -#define CEREF1_22 COMP_E_CTL2_REF1_22 /*!< Reference resistor tap for setting 22. */ -#define CEREF1_23 COMP_E_CTL2_REF1_23 /*!< Reference resistor tap for setting 23. */ -#define CEREF1_24 COMP_E_CTL2_REF1_24 /*!< Reference resistor tap for setting 24. */ -#define CEREF1_25 COMP_E_CTL2_REF1_25 /*!< Reference resistor tap for setting 25. */ -#define CEREF1_26 COMP_E_CTL2_REF1_26 /*!< Reference resistor tap for setting 26. */ -#define CEREF1_27 COMP_E_CTL2_REF1_27 /*!< Reference resistor tap for setting 27. */ -#define CEREF1_28 COMP_E_CTL2_REF1_28 /*!< Reference resistor tap for setting 28. */ -#define CEREF1_29 COMP_E_CTL2_REF1_29 /*!< Reference resistor tap for setting 29. */ -#define CEREF1_30 COMP_E_CTL2_REF1_30 /*!< Reference resistor tap for setting 30. */ -#define CEREF1_31 COMP_E_CTL2_REF1_31 /*!< Reference resistor tap for setting 31. */ -/* CE0CTL2[CEREFL] Bits */ -#define CEREFL_OFS COMP_E_CTL2_REFL_OFS /*!< CEREFL Offset */ -#define CEREFL_M COMP_E_CTL2_REFL_MASK /*!< Reference voltage level */ -#define CEREFL0 COMP_E_CTL2_REFL0 /*!< CEREFL Bit 0 */ -#define CEREFL1 COMP_E_CTL2_REFL1 /*!< CEREFL Bit 1 */ -#define CEREFL_0 COMP_E_CTL2_CEREFL_0 /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define CEREFL_1 COMP_E_CTL2_CEREFL_1 /*!< 1.2 V is selected as shared reference voltage input */ -#define CEREFL_2 COMP_E_CTL2_CEREFL_2 /*!< 2.0 V is selected as shared reference voltage input */ -#define CEREFL_3 COMP_E_CTL2_CEREFL_3 /*!< 2.5 V is selected as shared reference voltage input */ -#define CEREFL__OFF COMP_E_CTL2_REFL__OFF /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define CEREFL__1P2V COMP_E_CTL2_REFL__1P2V /*!< 1.2 V is selected as shared reference voltage input */ -#define CEREFL__2P0V COMP_E_CTL2_REFL__2P0V /*!< 2.0 V is selected as shared reference voltage input */ -#define CEREFL__2P5V COMP_E_CTL2_REFL__2P5V /*!< 2.5 V is selected as shared reference voltage input */ -/* CE0CTL2[CEREFACC] Bits */ -#define CEREFACC_OFS COMP_E_CTL2_REFACC_OFS /*!< CEREFACC Offset */ -#define CEREFACC COMP_E_CTL2_REFACC /*!< Reference accuracy */ -/* CE0CTL3[CEPD0] Bits */ -#define CEPD0_OFS COMP_E_CTL3_PD0_OFS /*!< CEPD0 Offset */ -#define CEPD0 COMP_E_CTL3_PD0 /*!< Port disable */ -/* CE0CTL3[CEPD1] Bits */ -#define CEPD1_OFS COMP_E_CTL3_PD1_OFS /*!< CEPD1 Offset */ -#define CEPD1 COMP_E_CTL3_PD1 /*!< Port disable */ -/* CE0CTL3[CEPD2] Bits */ -#define CEPD2_OFS COMP_E_CTL3_PD2_OFS /*!< CEPD2 Offset */ -#define CEPD2 COMP_E_CTL3_PD2 /*!< Port disable */ -/* CE0CTL3[CEPD3] Bits */ -#define CEPD3_OFS COMP_E_CTL3_PD3_OFS /*!< CEPD3 Offset */ -#define CEPD3 COMP_E_CTL3_PD3 /*!< Port disable */ -/* CE0CTL3[CEPD4] Bits */ -#define CEPD4_OFS COMP_E_CTL3_PD4_OFS /*!< CEPD4 Offset */ -#define CEPD4 COMP_E_CTL3_PD4 /*!< Port disable */ -/* CE0CTL3[CEPD5] Bits */ -#define CEPD5_OFS COMP_E_CTL3_PD5_OFS /*!< CEPD5 Offset */ -#define CEPD5 COMP_E_CTL3_PD5 /*!< Port disable */ -/* CE0CTL3[CEPD6] Bits */ -#define CEPD6_OFS COMP_E_CTL3_PD6_OFS /*!< CEPD6 Offset */ -#define CEPD6 COMP_E_CTL3_PD6 /*!< Port disable */ -/* CE0CTL3[CEPD7] Bits */ -#define CEPD7_OFS COMP_E_CTL3_PD7_OFS /*!< CEPD7 Offset */ -#define CEPD7 COMP_E_CTL3_PD7 /*!< Port disable */ -/* CE0CTL3[CEPD8] Bits */ -#define CEPD8_OFS COMP_E_CTL3_PD8_OFS /*!< CEPD8 Offset */ -#define CEPD8 COMP_E_CTL3_PD8 /*!< Port disable */ -/* CE0CTL3[CEPD9] Bits */ -#define CEPD9_OFS COMP_E_CTL3_PD9_OFS /*!< CEPD9 Offset */ -#define CEPD9 COMP_E_CTL3_PD9 /*!< Port disable */ -/* CE0CTL3[CEPD10] Bits */ -#define CEPD10_OFS COMP_E_CTL3_PD10_OFS /*!< CEPD10 Offset */ -#define CEPD10 COMP_E_CTL3_PD10 /*!< Port disable */ -/* CE0CTL3[CEPD11] Bits */ -#define CEPD11_OFS COMP_E_CTL3_PD11_OFS /*!< CEPD11 Offset */ -#define CEPD11 COMP_E_CTL3_PD11 /*!< Port disable */ -/* CE0CTL3[CEPD12] Bits */ -#define CEPD12_OFS COMP_E_CTL3_PD12_OFS /*!< CEPD12 Offset */ -#define CEPD12 COMP_E_CTL3_PD12 /*!< Port disable */ -/* CE0CTL3[CEPD13] Bits */ -#define CEPD13_OFS COMP_E_CTL3_PD13_OFS /*!< CEPD13 Offset */ -#define CEPD13 COMP_E_CTL3_PD13 /*!< Port disable */ -/* CE0CTL3[CEPD14] Bits */ -#define CEPD14_OFS COMP_E_CTL3_PD14_OFS /*!< CEPD14 Offset */ -#define CEPD14 COMP_E_CTL3_PD14 /*!< Port disable */ -/* CE0CTL3[CEPD15] Bits */ -#define CEPD15_OFS COMP_E_CTL3_PD15_OFS /*!< CEPD15 Offset */ -#define CEPD15 COMP_E_CTL3_PD15 /*!< Port disable */ -/* CE0INT[CEIFG] Bits */ -#define CEIFG_OFS COMP_E_INT_IFG_OFS /*!< CEIFG Offset */ -#define CEIFG COMP_E_INT_IFG /*!< Comparator output interrupt flag */ -/* CE0INT[CEIIFG] Bits */ -#define CEIIFG_OFS COMP_E_INT_IIFG_OFS /*!< CEIIFG Offset */ -#define CEIIFG COMP_E_INT_IIFG /*!< Comparator output inverted interrupt flag */ -/* CE0INT[CERDYIFG] Bits */ -#define CERDYIFG_OFS COMP_E_INT_RDYIFG_OFS /*!< CERDYIFG Offset */ -#define CERDYIFG COMP_E_INT_RDYIFG /*!< Comparator ready interrupt flag */ -/* CE0INT[CEIE] Bits */ -#define CEIE_OFS COMP_E_INT_IE_OFS /*!< CEIE Offset */ -#define CEIE COMP_E_INT_IE /*!< Comparator output interrupt enable */ -/* CE0INT[CEIIE] Bits */ -#define CEIIE_OFS COMP_E_INT_IIE_OFS /*!< CEIIE Offset */ -#define CEIIE COMP_E_INT_IIE /*!< Comparator output interrupt enable inverted polarity */ -/* CE0INT[CERDYIE] Bits */ -#define CERDYIE_OFS COMP_E_INT_RDYIE_OFS /*!< CERDYIE Offset */ -#define CERDYIE COMP_E_INT_RDYIE /*!< Comparator ready interrupt enable */ - -/****************************************************************************** -* CRC32 Bits (legacy section) -******************************************************************************/ -/* DIO_PAIN[P1IN] Bits */ -#define P1IN_OFS ( 0) /*!< P1IN Offset */ -#define P1IN_M (0x00ff) /*!< Port 1 Input */ -/* DIO_PAIN[P2IN] Bits */ -#define P2IN_OFS ( 8) /*!< P2IN Offset */ -#define P2IN_M (0xff00) /*!< Port 2 Input */ -/* DIO_PAOUT[P2OUT] Bits */ -#define P2OUT_OFS ( 8) /*!< P2OUT Offset */ -#define P2OUT_M (0xff00) /*!< Port 2 Output */ -/* DIO_PAOUT[P1OUT] Bits */ -#define P1OUT_OFS ( 0) /*!< P1OUT Offset */ -#define P1OUT_M (0x00ff) /*!< Port 1 Output */ -/* DIO_PADIR[P1DIR] Bits */ -#define P1DIR_OFS ( 0) /*!< P1DIR Offset */ -#define P1DIR_M (0x00ff) /*!< Port 1 Direction */ -/* DIO_PADIR[P2DIR] Bits */ -#define P2DIR_OFS ( 8) /*!< P2DIR Offset */ -#define P2DIR_M (0xff00) /*!< Port 2 Direction */ -/* DIO_PAREN[P1REN] Bits */ -#define P1REN_OFS ( 0) /*!< P1REN Offset */ -#define P1REN_M (0x00ff) /*!< Port 1 Resistor Enable */ -/* DIO_PAREN[P2REN] Bits */ -#define P2REN_OFS ( 8) /*!< P2REN Offset */ -#define P2REN_M (0xff00) /*!< Port 2 Resistor Enable */ -/* DIO_PADS[P1DS] Bits */ -#define P1DS_OFS ( 0) /*!< P1DS Offset */ -#define P1DS_M (0x00ff) /*!< Port 1 Drive Strength */ -/* DIO_PADS[P2DS] Bits */ -#define P2DS_OFS ( 8) /*!< P2DS Offset */ -#define P2DS_M (0xff00) /*!< Port 2 Drive Strength */ -/* DIO_PASEL0[P1SEL0] Bits */ -#define P1SEL0_OFS ( 0) /*!< P1SEL0 Offset */ -#define P1SEL0_M (0x00ff) /*!< Port 1 Select 0 */ -/* DIO_PASEL0[P2SEL0] Bits */ -#define P2SEL0_OFS ( 8) /*!< P2SEL0 Offset */ -#define P2SEL0_M (0xff00) /*!< Port 2 Select 0 */ -/* DIO_PASEL1[P1SEL1] Bits */ -#define P1SEL1_OFS ( 0) /*!< P1SEL1 Offset */ -#define P1SEL1_M (0x00ff) /*!< Port 1 Select 1 */ -/* DIO_PASEL1[P2SEL1] Bits */ -#define P2SEL1_OFS ( 8) /*!< P2SEL1 Offset */ -#define P2SEL1_M (0xff00) /*!< Port 2 Select 1 */ -/* DIO_P1IV[P1IV] Bits */ -#define P1IV_OFS ( 0) /*!< P1IV Offset */ -#define P1IV_M (0x001f) /*!< Port 1 interrupt vector value */ -#define P1IV0 (0x0001) /*!< Port 1 interrupt vector value */ -#define P1IV1 (0x0002) /*!< Port 1 interrupt vector value */ -#define P1IV2 (0x0004) /*!< Port 1 interrupt vector value */ -#define P1IV3 (0x0008) /*!< Port 1 interrupt vector value */ -#define P1IV4 (0x0010) /*!< Port 1 interrupt vector value */ -#define P1IV_0 (0x0000) /*!< No interrupt pending */ -#define P1IV_2 (0x0002) /*!< Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */ -#define P1IV_4 (0x0004) /*!< Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */ -#define P1IV_6 (0x0006) /*!< Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */ -#define P1IV_8 (0x0008) /*!< Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */ -#define P1IV_10 (0x000a) /*!< Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */ -#define P1IV_12 (0x000c) /*!< Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */ -#define P1IV_14 (0x000e) /*!< Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */ -#define P1IV_16 (0x0010) /*!< Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */ -#define P1IV__NONE (0x0000) /*!< No interrupt pending */ -#define P1IV__P1IFG0 (0x0002) /*!< Interrupt Source: Port 1.0 interrupt; Interrupt Flag: P1IFG0; Interrupt Priority: Highest */ -#define P1IV__P1IFG1 (0x0004) /*!< Interrupt Source: Port 1.1 interrupt; Interrupt Flag: P1IFG1 */ -#define P1IV__P1IFG2 (0x0006) /*!< Interrupt Source: Port 1.2 interrupt; Interrupt Flag: P1IFG2 */ -#define P1IV__P1IFG3 (0x0008) /*!< Interrupt Source: Port 1.3 interrupt; Interrupt Flag: P1IFG3 */ -#define P1IV__P1IFG4 (0x000a) /*!< Interrupt Source: Port 1.4 interrupt; Interrupt Flag: P1IFG4 */ -#define P1IV__P1IFG5 (0x000c) /*!< Interrupt Source: Port 1.5 interrupt; Interrupt Flag: P1IFG5 */ -#define P1IV__P1IFG6 (0x000e) /*!< Interrupt Source: Port 1.6 interrupt; Interrupt Flag: P1IFG6 */ -#define P1IV__P1IFG7 (0x0010) /*!< Interrupt Source: Port 1.7 interrupt; Interrupt Flag: P1IFG7; Interrupt Priority: Lowest */ -/* DIO_PASELC[P1SELC] Bits */ -#define P1SELC_OFS ( 0) /*!< P1SELC Offset */ -#define P1SELC_M (0x00ff) /*!< Port 1 Complement Select */ -/* DIO_PASELC[P2SELC] Bits */ -#define P2SELC_OFS ( 8) /*!< P2SELC Offset */ -#define P2SELC_M (0xff00) /*!< Port 2 Complement Select */ -/* DIO_PAIES[P1IES] Bits */ -#define P1IES_OFS ( 0) /*!< P1IES Offset */ -#define P1IES_M (0x00ff) /*!< Port 1 Interrupt Edge Select */ -/* DIO_PAIES[P2IES] Bits */ -#define P2IES_OFS ( 8) /*!< P2IES Offset */ -#define P2IES_M (0xff00) /*!< Port 2 Interrupt Edge Select */ -/* DIO_PAIE[P1IE] Bits */ -#define P1IE_OFS ( 0) /*!< P1IE Offset */ -#define P1IE_M (0x00ff) /*!< Port 1 Interrupt Enable */ -/* DIO_PAIE[P2IE] Bits */ -#define P2IE_OFS ( 8) /*!< P2IE Offset */ -#define P2IE_M (0xff00) /*!< Port 2 Interrupt Enable */ -/* DIO_PAIFG[P1IFG] Bits */ -#define P1IFG_OFS ( 0) /*!< P1IFG Offset */ -#define P1IFG_M (0x00ff) /*!< Port 1 Interrupt Flag */ -/* DIO_PAIFG[P2IFG] Bits */ -#define P2IFG_OFS ( 8) /*!< P2IFG Offset */ -#define P2IFG_M (0xff00) /*!< Port 2 Interrupt Flag */ -/* DIO_P2IV[P2IV] Bits */ -#define P2IV_OFS ( 0) /*!< P2IV Offset */ -#define P2IV_M (0x001f) /*!< Port 2 interrupt vector value */ -#define P2IV0 (0x0001) /*!< Port 2 interrupt vector value */ -#define P2IV1 (0x0002) /*!< Port 2 interrupt vector value */ -#define P2IV2 (0x0004) /*!< Port 2 interrupt vector value */ -#define P2IV3 (0x0008) /*!< Port 2 interrupt vector value */ -#define P2IV4 (0x0010) /*!< Port 2 interrupt vector value */ -#define P2IV_0 (0x0000) /*!< No interrupt pending */ -#define P2IV_2 (0x0002) /*!< Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */ -#define P2IV_4 (0x0004) /*!< Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */ -#define P2IV_6 (0x0006) /*!< Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */ -#define P2IV_8 (0x0008) /*!< Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */ -#define P2IV_10 (0x000a) /*!< Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */ -#define P2IV_12 (0x000c) /*!< Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */ -#define P2IV_14 (0x000e) /*!< Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */ -#define P2IV_16 (0x0010) /*!< Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */ -#define P2IV__NONE (0x0000) /*!< No interrupt pending */ -#define P2IV__P2IFG0 (0x0002) /*!< Interrupt Source: Port 2.0 interrupt; Interrupt Flag: P2IFG0; Interrupt Priority: Highest */ -#define P2IV__P2IFG1 (0x0004) /*!< Interrupt Source: Port 2.1 interrupt; Interrupt Flag: P2IFG1 */ -#define P2IV__P2IFG2 (0x0006) /*!< Interrupt Source: Port 2.2 interrupt; Interrupt Flag: P2IFG2 */ -#define P2IV__P2IFG3 (0x0008) /*!< Interrupt Source: Port 2.3 interrupt; Interrupt Flag: P2IFG3 */ -#define P2IV__P2IFG4 (0x000a) /*!< Interrupt Source: Port 2.4 interrupt; Interrupt Flag: P2IFG4 */ -#define P2IV__P2IFG5 (0x000c) /*!< Interrupt Source: Port 2.5 interrupt; Interrupt Flag: P2IFG5 */ -#define P2IV__P2IFG6 (0x000e) /*!< Interrupt Source: Port 2.6 interrupt; Interrupt Flag: P2IFG6 */ -#define P2IV__P2IFG7 (0x0010) /*!< Interrupt Source: Port 2.7 interrupt; Interrupt Flag: P2IFG7; Interrupt Priority: Lowest */ -/* DIO_PBIN[P3IN] Bits */ -#define P3IN_OFS ( 0) /*!< P3IN Offset */ -#define P3IN_M (0x00ff) /*!< Port 3 Input */ -/* DIO_PBIN[P4IN] Bits */ -#define P4IN_OFS ( 8) /*!< P4IN Offset */ -#define P4IN_M (0xff00) /*!< Port 4 Input */ -/* DIO_PBOUT[P3OUT] Bits */ -#define P3OUT_OFS ( 0) /*!< P3OUT Offset */ -#define P3OUT_M (0x00ff) /*!< Port 3 Output */ -/* DIO_PBOUT[P4OUT] Bits */ -#define P4OUT_OFS ( 8) /*!< P4OUT Offset */ -#define P4OUT_M (0xff00) /*!< Port 4 Output */ -/* DIO_PBDIR[P3DIR] Bits */ -#define P3DIR_OFS ( 0) /*!< P3DIR Offset */ -#define P3DIR_M (0x00ff) /*!< Port 3 Direction */ -/* DIO_PBDIR[P4DIR] Bits */ -#define P4DIR_OFS ( 8) /*!< P4DIR Offset */ -#define P4DIR_M (0xff00) /*!< Port 4 Direction */ -/* DIO_PBREN[P3REN] Bits */ -#define P3REN_OFS ( 0) /*!< P3REN Offset */ -#define P3REN_M (0x00ff) /*!< Port 3 Resistor Enable */ -/* DIO_PBREN[P4REN] Bits */ -#define P4REN_OFS ( 8) /*!< P4REN Offset */ -#define P4REN_M (0xff00) /*!< Port 4 Resistor Enable */ -/* DIO_PBDS[P3DS] Bits */ -#define P3DS_OFS ( 0) /*!< P3DS Offset */ -#define P3DS_M (0x00ff) /*!< Port 3 Drive Strength */ -/* DIO_PBDS[P4DS] Bits */ -#define P4DS_OFS ( 8) /*!< P4DS Offset */ -#define P4DS_M (0xff00) /*!< Port 4 Drive Strength */ -/* DIO_PBSEL0[P4SEL0] Bits */ -#define P4SEL0_OFS ( 8) /*!< P4SEL0 Offset */ -#define P4SEL0_M (0xff00) /*!< Port 4 Select 0 */ -/* DIO_PBSEL0[P3SEL0] Bits */ -#define P3SEL0_OFS ( 0) /*!< P3SEL0 Offset */ -#define P3SEL0_M (0x00ff) /*!< Port 3 Select 0 */ -/* DIO_PBSEL1[P3SEL1] Bits */ -#define P3SEL1_OFS ( 0) /*!< P3SEL1 Offset */ -#define P3SEL1_M (0x00ff) /*!< Port 3 Select 1 */ -/* DIO_PBSEL1[P4SEL1] Bits */ -#define P4SEL1_OFS ( 8) /*!< P4SEL1 Offset */ -#define P4SEL1_M (0xff00) /*!< Port 4 Select 1 */ -/* DIO_P3IV[P3IV] Bits */ -#define P3IV_OFS ( 0) /*!< P3IV Offset */ -#define P3IV_M (0x001f) /*!< Port 3 interrupt vector value */ -#define P3IV0 (0x0001) /*!< Port 3 interrupt vector value */ -#define P3IV1 (0x0002) /*!< Port 3 interrupt vector value */ -#define P3IV2 (0x0004) /*!< Port 3 interrupt vector value */ -#define P3IV3 (0x0008) /*!< Port 3 interrupt vector value */ -#define P3IV4 (0x0010) /*!< Port 3 interrupt vector value */ -#define P3IV_0 (0x0000) /*!< No interrupt pending */ -#define P3IV_2 (0x0002) /*!< Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */ -#define P3IV_4 (0x0004) /*!< Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */ -#define P3IV_6 (0x0006) /*!< Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */ -#define P3IV_8 (0x0008) /*!< Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */ -#define P3IV_10 (0x000a) /*!< Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */ -#define P3IV_12 (0x000c) /*!< Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */ -#define P3IV_14 (0x000e) /*!< Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */ -#define P3IV_16 (0x0010) /*!< Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */ -#define P3IV__NONE (0x0000) /*!< No interrupt pending */ -#define P3IV__P3IFG0 (0x0002) /*!< Interrupt Source: Port 3.0 interrupt; Interrupt Flag: P3IFG0; Interrupt Priority: Highest */ -#define P3IV__P3IFG1 (0x0004) /*!< Interrupt Source: Port 3.1 interrupt; Interrupt Flag: P3IFG1 */ -#define P3IV__P3IFG2 (0x0006) /*!< Interrupt Source: Port 3.2 interrupt; Interrupt Flag: P3IFG2 */ -#define P3IV__P3IFG3 (0x0008) /*!< Interrupt Source: Port 3.3 interrupt; Interrupt Flag: P3IFG3 */ -#define P3IV__P3IFG4 (0x000a) /*!< Interrupt Source: Port 3.4 interrupt; Interrupt Flag: P3IFG4 */ -#define P3IV__P3IFG5 (0x000c) /*!< Interrupt Source: Port 3.5 interrupt; Interrupt Flag: P3IFG5 */ -#define P3IV__P3IFG6 (0x000e) /*!< Interrupt Source: Port 3.6 interrupt; Interrupt Flag: P3IFG6 */ -#define P3IV__P3IFG7 (0x0010) /*!< Interrupt Source: Port 3.7 interrupt; Interrupt Flag: P3IFG7; Interrupt Priority: Lowest */ -/* DIO_PBSELC[P3SELC] Bits */ -#define P3SELC_OFS ( 0) /*!< P3SELC Offset */ -#define P3SELC_M (0x00ff) /*!< Port 3 Complement Select */ -/* DIO_PBSELC[P4SELC] Bits */ -#define P4SELC_OFS ( 8) /*!< P4SELC Offset */ -#define P4SELC_M (0xff00) /*!< Port 4 Complement Select */ -/* DIO_PBIES[P3IES] Bits */ -#define P3IES_OFS ( 0) /*!< P3IES Offset */ -#define P3IES_M (0x00ff) /*!< Port 3 Interrupt Edge Select */ -/* DIO_PBIES[P4IES] Bits */ -#define P4IES_OFS ( 8) /*!< P4IES Offset */ -#define P4IES_M (0xff00) /*!< Port 4 Interrupt Edge Select */ -/* DIO_PBIE[P3IE] Bits */ -#define P3IE_OFS ( 0) /*!< P3IE Offset */ -#define P3IE_M (0x00ff) /*!< Port 3 Interrupt Enable */ -/* DIO_PBIE[P4IE] Bits */ -#define P4IE_OFS ( 8) /*!< P4IE Offset */ -#define P4IE_M (0xff00) /*!< Port 4 Interrupt Enable */ -/* DIO_PBIFG[P3IFG] Bits */ -#define P3IFG_OFS ( 0) /*!< P3IFG Offset */ -#define P3IFG_M (0x00ff) /*!< Port 3 Interrupt Flag */ -/* DIO_PBIFG[P4IFG] Bits */ -#define P4IFG_OFS ( 8) /*!< P4IFG Offset */ -#define P4IFG_M (0xff00) /*!< Port 4 Interrupt Flag */ -/* DIO_P4IV[P4IV] Bits */ -#define P4IV_OFS ( 0) /*!< P4IV Offset */ -#define P4IV_M (0x001f) /*!< Port 4 interrupt vector value */ -#define P4IV0 (0x0001) /*!< Port 4 interrupt vector value */ -#define P4IV1 (0x0002) /*!< Port 4 interrupt vector value */ -#define P4IV2 (0x0004) /*!< Port 4 interrupt vector value */ -#define P4IV3 (0x0008) /*!< Port 4 interrupt vector value */ -#define P4IV4 (0x0010) /*!< Port 4 interrupt vector value */ -#define P4IV_0 (0x0000) /*!< No interrupt pending */ -#define P4IV_2 (0x0002) /*!< Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */ -#define P4IV_4 (0x0004) /*!< Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */ -#define P4IV_6 (0x0006) /*!< Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */ -#define P4IV_8 (0x0008) /*!< Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */ -#define P4IV_10 (0x000a) /*!< Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */ -#define P4IV_12 (0x000c) /*!< Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */ -#define P4IV_14 (0x000e) /*!< Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */ -#define P4IV_16 (0x0010) /*!< Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */ -#define P4IV__NONE (0x0000) /*!< No interrupt pending */ -#define P4IV__P4IFG0 (0x0002) /*!< Interrupt Source: Port 4.0 interrupt; Interrupt Flag: P4IFG0; Interrupt Priority: Highest */ -#define P4IV__P4IFG1 (0x0004) /*!< Interrupt Source: Port 4.1 interrupt; Interrupt Flag: P4IFG1 */ -#define P4IV__P4IFG2 (0x0006) /*!< Interrupt Source: Port 4.2 interrupt; Interrupt Flag: P4IFG2 */ -#define P4IV__P4IFG3 (0x0008) /*!< Interrupt Source: Port 4.3 interrupt; Interrupt Flag: P4IFG3 */ -#define P4IV__P4IFG4 (0x000a) /*!< Interrupt Source: Port 4.4 interrupt; Interrupt Flag: P4IFG4 */ -#define P4IV__P4IFG5 (0x000c) /*!< Interrupt Source: Port 4.5 interrupt; Interrupt Flag: P4IFG5 */ -#define P4IV__P4IFG6 (0x000e) /*!< Interrupt Source: Port 4.6 interrupt; Interrupt Flag: P4IFG6 */ -#define P4IV__P4IFG7 (0x0010) /*!< Interrupt Source: Port 4.7 interrupt; Interrupt Flag: P4IFG7; Interrupt Priority: Lowest */ -/* DIO_PCIN[P5IN] Bits */ -#define P5IN_OFS ( 0) /*!< P5IN Offset */ -#define P5IN_M (0x00ff) /*!< Port 5 Input */ -/* DIO_PCIN[P6IN] Bits */ -#define P6IN_OFS ( 8) /*!< P6IN Offset */ -#define P6IN_M (0xff00) /*!< Port 6 Input */ -/* DIO_PCOUT[P5OUT] Bits */ -#define P5OUT_OFS ( 0) /*!< P5OUT Offset */ -#define P5OUT_M (0x00ff) /*!< Port 5 Output */ -/* DIO_PCOUT[P6OUT] Bits */ -#define P6OUT_OFS ( 8) /*!< P6OUT Offset */ -#define P6OUT_M (0xff00) /*!< Port 6 Output */ -/* DIO_PCDIR[P5DIR] Bits */ -#define P5DIR_OFS ( 0) /*!< P5DIR Offset */ -#define P5DIR_M (0x00ff) /*!< Port 5 Direction */ -/* DIO_PCDIR[P6DIR] Bits */ -#define P6DIR_OFS ( 8) /*!< P6DIR Offset */ -#define P6DIR_M (0xff00) /*!< Port 6 Direction */ -/* DIO_PCREN[P5REN] Bits */ -#define P5REN_OFS ( 0) /*!< P5REN Offset */ -#define P5REN_M (0x00ff) /*!< Port 5 Resistor Enable */ -/* DIO_PCREN[P6REN] Bits */ -#define P6REN_OFS ( 8) /*!< P6REN Offset */ -#define P6REN_M (0xff00) /*!< Port 6 Resistor Enable */ -/* DIO_PCDS[P5DS] Bits */ -#define P5DS_OFS ( 0) /*!< P5DS Offset */ -#define P5DS_M (0x00ff) /*!< Port 5 Drive Strength */ -/* DIO_PCDS[P6DS] Bits */ -#define P6DS_OFS ( 8) /*!< P6DS Offset */ -#define P6DS_M (0xff00) /*!< Port 6 Drive Strength */ -/* DIO_PCSEL0[P5SEL0] Bits */ -#define P5SEL0_OFS ( 0) /*!< P5SEL0 Offset */ -#define P5SEL0_M (0x00ff) /*!< Port 5 Select 0 */ -/* DIO_PCSEL0[P6SEL0] Bits */ -#define P6SEL0_OFS ( 8) /*!< P6SEL0 Offset */ -#define P6SEL0_M (0xff00) /*!< Port 6 Select 0 */ -/* DIO_PCSEL1[P5SEL1] Bits */ -#define P5SEL1_OFS ( 0) /*!< P5SEL1 Offset */ -#define P5SEL1_M (0x00ff) /*!< Port 5 Select 1 */ -/* DIO_PCSEL1[P6SEL1] Bits */ -#define P6SEL1_OFS ( 8) /*!< P6SEL1 Offset */ -#define P6SEL1_M (0xff00) /*!< Port 6 Select 1 */ -/* DIO_P5IV[P5IV] Bits */ -#define P5IV_OFS ( 0) /*!< P5IV Offset */ -#define P5IV_M (0x001f) /*!< Port 5 interrupt vector value */ -#define P5IV0 (0x0001) /*!< Port 5 interrupt vector value */ -#define P5IV1 (0x0002) /*!< Port 5 interrupt vector value */ -#define P5IV2 (0x0004) /*!< Port 5 interrupt vector value */ -#define P5IV3 (0x0008) /*!< Port 5 interrupt vector value */ -#define P5IV4 (0x0010) /*!< Port 5 interrupt vector value */ -#define P5IV_0 (0x0000) /*!< No interrupt pending */ -#define P5IV_2 (0x0002) /*!< Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */ -#define P5IV_4 (0x0004) /*!< Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */ -#define P5IV_6 (0x0006) /*!< Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */ -#define P5IV_8 (0x0008) /*!< Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */ -#define P5IV_10 (0x000a) /*!< Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */ -#define P5IV_12 (0x000c) /*!< Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */ -#define P5IV_14 (0x000e) /*!< Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */ -#define P5IV_16 (0x0010) /*!< Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */ -#define P5IV__NONE (0x0000) /*!< No interrupt pending */ -#define P5IV__P5IFG0 (0x0002) /*!< Interrupt Source: Port 5.0 interrupt; Interrupt Flag: P5IFG0; Interrupt Priority: Highest */ -#define P5IV__P5IFG1 (0x0004) /*!< Interrupt Source: Port 5.1 interrupt; Interrupt Flag: P5IFG1 */ -#define P5IV__P5IFG2 (0x0006) /*!< Interrupt Source: Port 5.2 interrupt; Interrupt Flag: P5IFG2 */ -#define P5IV__P5IFG3 (0x0008) /*!< Interrupt Source: Port 5.3 interrupt; Interrupt Flag: P5IFG3 */ -#define P5IV__P5IFG4 (0x000a) /*!< Interrupt Source: Port 5.4 interrupt; Interrupt Flag: P5IFG4 */ -#define P5IV__P5IFG5 (0x000c) /*!< Interrupt Source: Port 5.5 interrupt; Interrupt Flag: P5IFG5 */ -#define P5IV__P5IFG6 (0x000e) /*!< Interrupt Source: Port 5.6 interrupt; Interrupt Flag: P5IFG6 */ -#define P5IV__P5IFG7 (0x0010) /*!< Interrupt Source: Port 5.7 interrupt; Interrupt Flag: P5IFG7; Interrupt Priority: Lowest */ -/* DIO_PCSELC[P5SELC] Bits */ -#define P5SELC_OFS ( 0) /*!< P5SELC Offset */ -#define P5SELC_M (0x00ff) /*!< Port 5 Complement Select */ -/* DIO_PCSELC[P6SELC] Bits */ -#define P6SELC_OFS ( 8) /*!< P6SELC Offset */ -#define P6SELC_M (0xff00) /*!< Port 6 Complement Select */ -/* DIO_PCIES[P5IES] Bits */ -#define P5IES_OFS ( 0) /*!< P5IES Offset */ -#define P5IES_M (0x00ff) /*!< Port 5 Interrupt Edge Select */ -/* DIO_PCIES[P6IES] Bits */ -#define P6IES_OFS ( 8) /*!< P6IES Offset */ -#define P6IES_M (0xff00) /*!< Port 6 Interrupt Edge Select */ -/* DIO_PCIE[P5IE] Bits */ -#define P5IE_OFS ( 0) /*!< P5IE Offset */ -#define P5IE_M (0x00ff) /*!< Port 5 Interrupt Enable */ -/* DIO_PCIE[P6IE] Bits */ -#define P6IE_OFS ( 8) /*!< P6IE Offset */ -#define P6IE_M (0xff00) /*!< Port 6 Interrupt Enable */ -/* DIO_PCIFG[P5IFG] Bits */ -#define P5IFG_OFS ( 0) /*!< P5IFG Offset */ -#define P5IFG_M (0x00ff) /*!< Port 5 Interrupt Flag */ -/* DIO_PCIFG[P6IFG] Bits */ -#define P6IFG_OFS ( 8) /*!< P6IFG Offset */ -#define P6IFG_M (0xff00) /*!< Port 6 Interrupt Flag */ -/* DIO_P6IV[P6IV] Bits */ -#define P6IV_OFS ( 0) /*!< P6IV Offset */ -#define P6IV_M (0x001f) /*!< Port 6 interrupt vector value */ -#define P6IV0 (0x0001) /*!< Port 6 interrupt vector value */ -#define P6IV1 (0x0002) /*!< Port 6 interrupt vector value */ -#define P6IV2 (0x0004) /*!< Port 6 interrupt vector value */ -#define P6IV3 (0x0008) /*!< Port 6 interrupt vector value */ -#define P6IV4 (0x0010) /*!< Port 6 interrupt vector value */ -#define P6IV_0 (0x0000) /*!< No interrupt pending */ -#define P6IV_2 (0x0002) /*!< Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */ -#define P6IV_4 (0x0004) /*!< Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */ -#define P6IV_6 (0x0006) /*!< Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */ -#define P6IV_8 (0x0008) /*!< Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */ -#define P6IV_10 (0x000a) /*!< Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */ -#define P6IV_12 (0x000c) /*!< Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */ -#define P6IV_14 (0x000e) /*!< Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */ -#define P6IV_16 (0x0010) /*!< Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */ -#define P6IV__NONE (0x0000) /*!< No interrupt pending */ -#define P6IV__P6IFG0 (0x0002) /*!< Interrupt Source: Port 6.0 interrupt; Interrupt Flag: P6IFG0; Interrupt Priority: Highest */ -#define P6IV__P6IFG1 (0x0004) /*!< Interrupt Source: Port 6.1 interrupt; Interrupt Flag: P6IFG1 */ -#define P6IV__P6IFG2 (0x0006) /*!< Interrupt Source: Port 6.2 interrupt; Interrupt Flag: P6IFG2 */ -#define P6IV__P6IFG3 (0x0008) /*!< Interrupt Source: Port 6.3 interrupt; Interrupt Flag: P6IFG3 */ -#define P6IV__P6IFG4 (0x000a) /*!< Interrupt Source: Port 6.4 interrupt; Interrupt Flag: P6IFG4 */ -#define P6IV__P6IFG5 (0x000c) /*!< Interrupt Source: Port 6.5 interrupt; Interrupt Flag: P6IFG5 */ -#define P6IV__P6IFG6 (0x000e) /*!< Interrupt Source: Port 6.6 interrupt; Interrupt Flag: P6IFG6 */ -#define P6IV__P6IFG7 (0x0010) /*!< Interrupt Source: Port 6.7 interrupt; Interrupt Flag: P6IFG7; Interrupt Priority: Lowest */ -/* DIO_PDIN[P7IN] Bits */ -#define P7IN_OFS ( 0) /*!< P7IN Offset */ -#define P7IN_M (0x00ff) /*!< Port 7 Input */ -/* DIO_PDIN[P8IN] Bits */ -#define P8IN_OFS ( 8) /*!< P8IN Offset */ -#define P8IN_M (0xff00) /*!< Port 8 Input */ -/* DIO_PDOUT[P7OUT] Bits */ -#define P7OUT_OFS ( 0) /*!< P7OUT Offset */ -#define P7OUT_M (0x00ff) /*!< Port 7 Output */ -/* DIO_PDOUT[P8OUT] Bits */ -#define P8OUT_OFS ( 8) /*!< P8OUT Offset */ -#define P8OUT_M (0xff00) /*!< Port 8 Output */ -/* DIO_PDDIR[P7DIR] Bits */ -#define P7DIR_OFS ( 0) /*!< P7DIR Offset */ -#define P7DIR_M (0x00ff) /*!< Port 7 Direction */ -/* DIO_PDDIR[P8DIR] Bits */ -#define P8DIR_OFS ( 8) /*!< P8DIR Offset */ -#define P8DIR_M (0xff00) /*!< Port 8 Direction */ -/* DIO_PDREN[P7REN] Bits */ -#define P7REN_OFS ( 0) /*!< P7REN Offset */ -#define P7REN_M (0x00ff) /*!< Port 7 Resistor Enable */ -/* DIO_PDREN[P8REN] Bits */ -#define P8REN_OFS ( 8) /*!< P8REN Offset */ -#define P8REN_M (0xff00) /*!< Port 8 Resistor Enable */ -/* DIO_PDDS[P7DS] Bits */ -#define P7DS_OFS ( 0) /*!< P7DS Offset */ -#define P7DS_M (0x00ff) /*!< Port 7 Drive Strength */ -/* DIO_PDDS[P8DS] Bits */ -#define P8DS_OFS ( 8) /*!< P8DS Offset */ -#define P8DS_M (0xff00) /*!< Port 8 Drive Strength */ -/* DIO_PDSEL0[P7SEL0] Bits */ -#define P7SEL0_OFS ( 0) /*!< P7SEL0 Offset */ -#define P7SEL0_M (0x00ff) /*!< Port 7 Select 0 */ -/* DIO_PDSEL0[P8SEL0] Bits */ -#define P8SEL0_OFS ( 8) /*!< P8SEL0 Offset */ -#define P8SEL0_M (0xff00) /*!< Port 8 Select 0 */ -/* DIO_PDSEL1[P7SEL1] Bits */ -#define P7SEL1_OFS ( 0) /*!< P7SEL1 Offset */ -#define P7SEL1_M (0x00ff) /*!< Port 7 Select 1 */ -/* DIO_PDSEL1[P8SEL1] Bits */ -#define P8SEL1_OFS ( 8) /*!< P8SEL1 Offset */ -#define P8SEL1_M (0xff00) /*!< Port 8 Select 1 */ -/* DIO_P7IV[P7IV] Bits */ -#define P7IV_OFS ( 0) /*!< P7IV Offset */ -#define P7IV_M (0x001f) /*!< Port 7 interrupt vector value */ -#define P7IV0 (0x0001) /*!< Port 7 interrupt vector value */ -#define P7IV1 (0x0002) /*!< Port 7 interrupt vector value */ -#define P7IV2 (0x0004) /*!< Port 7 interrupt vector value */ -#define P7IV3 (0x0008) /*!< Port 7 interrupt vector value */ -#define P7IV4 (0x0010) /*!< Port 7 interrupt vector value */ -#define P7IV_0 (0x0000) /*!< No interrupt pending */ -#define P7IV_2 (0x0002) /*!< Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */ -#define P7IV_4 (0x0004) /*!< Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */ -#define P7IV_6 (0x0006) /*!< Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */ -#define P7IV_8 (0x0008) /*!< Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */ -#define P7IV_10 (0x000a) /*!< Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */ -#define P7IV_12 (0x000c) /*!< Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */ -#define P7IV_14 (0x000e) /*!< Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */ -#define P7IV_16 (0x0010) /*!< Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */ -#define P7IV__NONE (0x0000) /*!< No interrupt pending */ -#define P7IV__P7IFG0 (0x0002) /*!< Interrupt Source: Port 7.0 interrupt; Interrupt Flag: P7IFG0; Interrupt Priority: Highest */ -#define P7IV__P7IFG1 (0x0004) /*!< Interrupt Source: Port 7.1 interrupt; Interrupt Flag: P7IFG1 */ -#define P7IV__P7IFG2 (0x0006) /*!< Interrupt Source: Port 7.2 interrupt; Interrupt Flag: P7IFG2 */ -#define P7IV__P7IFG3 (0x0008) /*!< Interrupt Source: Port 7.3 interrupt; Interrupt Flag: P7IFG3 */ -#define P7IV__P7IFG4 (0x000a) /*!< Interrupt Source: Port 7.4 interrupt; Interrupt Flag: P7IFG4 */ -#define P7IV__P7IFG5 (0x000c) /*!< Interrupt Source: Port 7.5 interrupt; Interrupt Flag: P7IFG5 */ -#define P7IV__P7IFG6 (0x000e) /*!< Interrupt Source: Port 7.6 interrupt; Interrupt Flag: P7IFG6 */ -#define P7IV__P7IFG7 (0x0010) /*!< Interrupt Source: Port 7.7 interrupt; Interrupt Flag: P7IFG7; Interrupt Priority: Lowest */ -/* DIO_PDSELC[P7SELC] Bits */ -#define P7SELC_OFS ( 0) /*!< P7SELC Offset */ -#define P7SELC_M (0x00ff) /*!< Port 7 Complement Select */ -/* DIO_PDSELC[P8SELC] Bits */ -#define P8SELC_OFS ( 8) /*!< P8SELC Offset */ -#define P8SELC_M (0xff00) /*!< Port 8 Complement Select */ -/* DIO_PDIES[P7IES] Bits */ -#define P7IES_OFS ( 0) /*!< P7IES Offset */ -#define P7IES_M (0x00ff) /*!< Port 7 Interrupt Edge Select */ -/* DIO_PDIES[P8IES] Bits */ -#define P8IES_OFS ( 8) /*!< P8IES Offset */ -#define P8IES_M (0xff00) /*!< Port 8 Interrupt Edge Select */ -/* DIO_PDIE[P7IE] Bits */ -#define P7IE_OFS ( 0) /*!< P7IE Offset */ -#define P7IE_M (0x00ff) /*!< Port 7 Interrupt Enable */ -/* DIO_PDIE[P8IE] Bits */ -#define P8IE_OFS ( 8) /*!< P8IE Offset */ -#define P8IE_M (0xff00) /*!< Port 8 Interrupt Enable */ -/* DIO_PDIFG[P7IFG] Bits */ -#define P7IFG_OFS ( 0) /*!< P7IFG Offset */ -#define P7IFG_M (0x00ff) /*!< Port 7 Interrupt Flag */ -/* DIO_PDIFG[P8IFG] Bits */ -#define P8IFG_OFS ( 8) /*!< P8IFG Offset */ -#define P8IFG_M (0xff00) /*!< Port 8 Interrupt Flag */ -/* DIO_P8IV[P8IV] Bits */ -#define P8IV_OFS ( 0) /*!< P8IV Offset */ -#define P8IV_M (0x001f) /*!< Port 8 interrupt vector value */ -#define P8IV0 (0x0001) /*!< Port 8 interrupt vector value */ -#define P8IV1 (0x0002) /*!< Port 8 interrupt vector value */ -#define P8IV2 (0x0004) /*!< Port 8 interrupt vector value */ -#define P8IV3 (0x0008) /*!< Port 8 interrupt vector value */ -#define P8IV4 (0x0010) /*!< Port 8 interrupt vector value */ -#define P8IV_0 (0x0000) /*!< No interrupt pending */ -#define P8IV_2 (0x0002) /*!< Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */ -#define P8IV_4 (0x0004) /*!< Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */ -#define P8IV_6 (0x0006) /*!< Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */ -#define P8IV_8 (0x0008) /*!< Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */ -#define P8IV_10 (0x000a) /*!< Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */ -#define P8IV_12 (0x000c) /*!< Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */ -#define P8IV_14 (0x000e) /*!< Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */ -#define P8IV_16 (0x0010) /*!< Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */ -#define P8IV__NONE (0x0000) /*!< No interrupt pending */ -#define P8IV__P8IFG0 (0x0002) /*!< Interrupt Source: Port 8.0 interrupt; Interrupt Flag: P8IFG0; Interrupt Priority: Highest */ -#define P8IV__P8IFG1 (0x0004) /*!< Interrupt Source: Port 8.1 interrupt; Interrupt Flag: P8IFG1 */ -#define P8IV__P8IFG2 (0x0006) /*!< Interrupt Source: Port 8.2 interrupt; Interrupt Flag: P8IFG2 */ -#define P8IV__P8IFG3 (0x0008) /*!< Interrupt Source: Port 8.3 interrupt; Interrupt Flag: P8IFG3 */ -#define P8IV__P8IFG4 (0x000a) /*!< Interrupt Source: Port 8.4 interrupt; Interrupt Flag: P8IFG4 */ -#define P8IV__P8IFG5 (0x000c) /*!< Interrupt Source: Port 8.5 interrupt; Interrupt Flag: P8IFG5 */ -#define P8IV__P8IFG6 (0x000e) /*!< Interrupt Source: Port 8.6 interrupt; Interrupt Flag: P8IFG6 */ -#define P8IV__P8IFG7 (0x0010) /*!< Interrupt Source: Port 8.7 interrupt; Interrupt Flag: P8IFG7; Interrupt Priority: Lowest */ -/* DIO_PEIN[P9IN] Bits */ -#define P9IN_OFS ( 0) /*!< P9IN Offset */ -#define P9IN_M (0x00ff) /*!< Port 9 Input */ -/* DIO_PEIN[P10IN] Bits */ -#define P10IN_OFS ( 8) /*!< P10IN Offset */ -#define P10IN_M (0xff00) /*!< Port 10 Input */ -/* DIO_PEOUT[P9OUT] Bits */ -#define P9OUT_OFS ( 0) /*!< P9OUT Offset */ -#define P9OUT_M (0x00ff) /*!< Port 9 Output */ -/* DIO_PEOUT[P10OUT] Bits */ -#define P10OUT_OFS ( 8) /*!< P10OUT Offset */ -#define P10OUT_M (0xff00) /*!< Port 10 Output */ -/* DIO_PEDIR[P9DIR] Bits */ -#define P9DIR_OFS ( 0) /*!< P9DIR Offset */ -#define P9DIR_M (0x00ff) /*!< Port 9 Direction */ -/* DIO_PEDIR[P10DIR] Bits */ -#define P10DIR_OFS ( 8) /*!< P10DIR Offset */ -#define P10DIR_M (0xff00) /*!< Port 10 Direction */ -/* DIO_PEREN[P9REN] Bits */ -#define P9REN_OFS ( 0) /*!< P9REN Offset */ -#define P9REN_M (0x00ff) /*!< Port 9 Resistor Enable */ -/* DIO_PEREN[P10REN] Bits */ -#define P10REN_OFS ( 8) /*!< P10REN Offset */ -#define P10REN_M (0xff00) /*!< Port 10 Resistor Enable */ -/* DIO_PEDS[P9DS] Bits */ -#define P9DS_OFS ( 0) /*!< P9DS Offset */ -#define P9DS_M (0x00ff) /*!< Port 9 Drive Strength */ -/* DIO_PEDS[P10DS] Bits */ -#define P10DS_OFS ( 8) /*!< P10DS Offset */ -#define P10DS_M (0xff00) /*!< Port 10 Drive Strength */ -/* DIO_PESEL0[P9SEL0] Bits */ -#define P9SEL0_OFS ( 0) /*!< P9SEL0 Offset */ -#define P9SEL0_M (0x00ff) /*!< Port 9 Select 0 */ -/* DIO_PESEL0[P10SEL0] Bits */ -#define P10SEL0_OFS ( 8) /*!< P10SEL0 Offset */ -#define P10SEL0_M (0xff00) /*!< Port 10 Select 0 */ -/* DIO_PESEL1[P9SEL1] Bits */ -#define P9SEL1_OFS ( 0) /*!< P9SEL1 Offset */ -#define P9SEL1_M (0x00ff) /*!< Port 9 Select 1 */ -/* DIO_PESEL1[P10SEL1] Bits */ -#define P10SEL1_OFS ( 8) /*!< P10SEL1 Offset */ -#define P10SEL1_M (0xff00) /*!< Port 10 Select 1 */ -/* DIO_P9IV[P9IV] Bits */ -#define P9IV_OFS ( 0) /*!< P9IV Offset */ -#define P9IV_M (0x001f) /*!< Port 9 interrupt vector value */ -#define P9IV0 (0x0001) /*!< Port 9 interrupt vector value */ -#define P9IV1 (0x0002) /*!< Port 9 interrupt vector value */ -#define P9IV2 (0x0004) /*!< Port 9 interrupt vector value */ -#define P9IV3 (0x0008) /*!< Port 9 interrupt vector value */ -#define P9IV4 (0x0010) /*!< Port 9 interrupt vector value */ -#define P9IV_0 (0x0000) /*!< No interrupt pending */ -#define P9IV_2 (0x0002) /*!< Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */ -#define P9IV_4 (0x0004) /*!< Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */ -#define P9IV_6 (0x0006) /*!< Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */ -#define P9IV_8 (0x0008) /*!< Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */ -#define P9IV_10 (0x000a) /*!< Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */ -#define P9IV_12 (0x000c) /*!< Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */ -#define P9IV_14 (0x000e) /*!< Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */ -#define P9IV_16 (0x0010) /*!< Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */ -#define P9IV__NONE (0x0000) /*!< No interrupt pending */ -#define P9IV__P9IFG0 (0x0002) /*!< Interrupt Source: Port 9.0 interrupt; Interrupt Flag: P9IFG0; Interrupt Priority: Highest */ -#define P9IV__P9IFG1 (0x0004) /*!< Interrupt Source: Port 9.1 interrupt; Interrupt Flag: P9IFG1 */ -#define P9IV__P9IFG2 (0x0006) /*!< Interrupt Source: Port 9.2 interrupt; Interrupt Flag: P9IFG2 */ -#define P9IV__P9IFG3 (0x0008) /*!< Interrupt Source: Port 9.3 interrupt; Interrupt Flag: P9IFG3 */ -#define P9IV__P9IFG4 (0x000a) /*!< Interrupt Source: Port 9.4 interrupt; Interrupt Flag: P9IFG4 */ -#define P9IV__P9IFG5 (0x000c) /*!< Interrupt Source: Port 9.5 interrupt; Interrupt Flag: P9IFG5 */ -#define P9IV__P9IFG6 (0x000e) /*!< Interrupt Source: Port 9.6 interrupt; Interrupt Flag: P9IFG6 */ -#define P9IV__P9IFG7 (0x0010) /*!< Interrupt Source: Port 9.7 interrupt; Interrupt Flag: P9IFG7; Interrupt Priority: Lowest */ -/* DIO_PESELC[P9SELC] Bits */ -#define P9SELC_OFS ( 0) /*!< P9SELC Offset */ -#define P9SELC_M (0x00ff) /*!< Port 9 Complement Select */ -/* DIO_PESELC[P10SELC] Bits */ -#define P10SELC_OFS ( 8) /*!< P10SELC Offset */ -#define P10SELC_M (0xff00) /*!< Port 10 Complement Select */ -/* DIO_PEIES[P9IES] Bits */ -#define P9IES_OFS ( 0) /*!< P9IES Offset */ -#define P9IES_M (0x00ff) /*!< Port 9 Interrupt Edge Select */ -/* DIO_PEIES[P10IES] Bits */ -#define P10IES_OFS ( 8) /*!< P10IES Offset */ -#define P10IES_M (0xff00) /*!< Port 10 Interrupt Edge Select */ -/* DIO_PEIE[P9IE] Bits */ -#define P9IE_OFS ( 0) /*!< P9IE Offset */ -#define P9IE_M (0x00ff) /*!< Port 9 Interrupt Enable */ -/* DIO_PEIE[P10IE] Bits */ -#define P10IE_OFS ( 8) /*!< P10IE Offset */ -#define P10IE_M (0xff00) /*!< Port 10 Interrupt Enable */ -/* DIO_PEIFG[P9IFG] Bits */ -#define P9IFG_OFS ( 0) /*!< P9IFG Offset */ -#define P9IFG_M (0x00ff) /*!< Port 9 Interrupt Flag */ -/* DIO_PEIFG[P10IFG] Bits */ -#define P10IFG_OFS ( 8) /*!< P10IFG Offset */ -#define P10IFG_M (0xff00) /*!< Port 10 Interrupt Flag */ -/* DIO_P10IV[P10IV] Bits */ -#define P10IV_OFS ( 0) /*!< P10IV Offset */ -#define P10IV_M (0x001f) /*!< Port 10 interrupt vector value */ -#define P10IV0 (0x0001) /*!< Port 10 interrupt vector value */ -#define P10IV1 (0x0002) /*!< Port 10 interrupt vector value */ -#define P10IV2 (0x0004) /*!< Port 10 interrupt vector value */ -#define P10IV3 (0x0008) /*!< Port 10 interrupt vector value */ -#define P10IV4 (0x0010) /*!< Port 10 interrupt vector value */ -#define P10IV_0 (0x0000) /*!< No interrupt pending */ -#define P10IV_2 (0x0002) /*!< Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */ -#define P10IV_4 (0x0004) /*!< Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */ -#define P10IV_6 (0x0006) /*!< Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */ -#define P10IV_8 (0x0008) /*!< Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */ -#define P10IV_10 (0x000a) /*!< Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */ -#define P10IV_12 (0x000c) /*!< Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */ -#define P10IV_14 (0x000e) /*!< Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */ -#define P10IV_16 (0x0010) /*!< Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */ -#define P10IV__NONE (0x0000) /*!< No interrupt pending */ -#define P10IV__P10IFG0 (0x0002) /*!< Interrupt Source: Port 10.0 interrupt; Interrupt Flag: P10IFG0; Interrupt Priority: Highest */ -#define P10IV__P10IFG1 (0x0004) /*!< Interrupt Source: Port 10.1 interrupt; Interrupt Flag: P10IFG1 */ -#define P10IV__P10IFG2 (0x0006) /*!< Interrupt Source: Port 10.2 interrupt; Interrupt Flag: P10IFG2 */ -#define P10IV__P10IFG3 (0x0008) /*!< Interrupt Source: Port 10.3 interrupt; Interrupt Flag: P10IFG3 */ -#define P10IV__P10IFG4 (0x000a) /*!< Interrupt Source: Port 10.4 interrupt; Interrupt Flag: P10IFG4 */ -#define P10IV__P10IFG5 (0x000c) /*!< Interrupt Source: Port 10.5 interrupt; Interrupt Flag: P10IFG5 */ -#define P10IV__P10IFG6 (0x000e) /*!< Interrupt Source: Port 10.6 interrupt; Interrupt Flag: P10IFG6 */ -#define P10IV__P10IFG7 (0x0010) /*!< Interrupt Source: Port 10.7 interrupt; Interrupt Flag: P10IFG7; Interrupt Priority: Lowest */ - - -/****************************************************************************** -* EUSCI_A Bits (legacy section) -******************************************************************************/ -/* UCA0CTLW0[UCSWRST] Bits */ -#define UCSWRST_OFS EUSCI_A_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ -#define UCSWRST EUSCI_A_CTLW0_SWRST /*!< Software reset enable */ -/* UCA0CTLW0[UCTXBRK] Bits */ -#define UCTXBRK_OFS EUSCI_A_CTLW0_TXBRK_OFS /*!< UCTXBRK Offset */ -#define UCTXBRK EUSCI_A_CTLW0_TXBRK /*!< Transmit break */ -/* UCA0CTLW0[UCTXADDR] Bits */ -#define UCTXADDR_OFS EUSCI_A_CTLW0_TXADDR_OFS /*!< UCTXADDR Offset */ -#define UCTXADDR EUSCI_A_CTLW0_TXADDR /*!< Transmit address */ -/* UCA0CTLW0[UCDORM] Bits */ -#define UCDORM_OFS EUSCI_A_CTLW0_DORM_OFS /*!< UCDORM Offset */ -#define UCDORM EUSCI_A_CTLW0_DORM /*!< Dormant */ -/* UCA0CTLW0[UCBRKIE] Bits */ -#define UCBRKIE_OFS EUSCI_A_CTLW0_BRKIE_OFS /*!< UCBRKIE Offset */ -#define UCBRKIE EUSCI_A_CTLW0_BRKIE /*!< Receive break character interrupt enable */ -/* UCA0CTLW0[UCRXEIE] Bits */ -#define UCRXEIE_OFS EUSCI_A_CTLW0_RXEIE_OFS /*!< UCRXEIE Offset */ -#define UCRXEIE EUSCI_A_CTLW0_RXEIE /*!< Receive erroneous-character interrupt enable */ -/* UCA0CTLW0[UCSSEL] Bits */ -#define UCSSEL_OFS EUSCI_A_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ -#define UCSSEL_M EUSCI_A_CTLW0_SSEL_MASK /*!< eUSCI_A clock source select */ -#define UCSSEL0 EUSCI_A_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ -#define UCSSEL1 EUSCI_A_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ -#define UCSSEL_0 EUSCI_A_CTLW0_UCSSEL_0 /*!< UCLK */ -#define UCSSEL_1 EUSCI_A_CTLW0_UCSSEL_1 /*!< ACLK */ -#define UCSSEL_2 EUSCI_A_CTLW0_UCSSEL_2 /*!< SMCLK */ -#define UCSSEL__UCLK EUSCI_A_CTLW0_SSEL__UCLK /*!< UCLK */ -#define UCSSEL__ACLK EUSCI_A_CTLW0_SSEL__ACLK /*!< ACLK */ -#define UCSSEL__SMCLK EUSCI_A_CTLW0_SSEL__SMCLK /*!< SMCLK */ -/* UCA0CTLW0[UCSYNC] Bits */ -#define UCSYNC_OFS EUSCI_A_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ -#define UCSYNC EUSCI_A_CTLW0_SYNC /*!< Synchronous mode enable */ -/* UCA0CTLW0[UCMODE] Bits */ -#define UCMODE_OFS EUSCI_A_CTLW0_MODE_OFS /*!< UCMODE Offset */ -#define UCMODE_M EUSCI_A_CTLW0_MODE_MASK /*!< eUSCI_A mode */ -#define UCMODE0 EUSCI_A_CTLW0_MODE0 /*!< UCMODE Bit 0 */ -#define UCMODE1 EUSCI_A_CTLW0_MODE1 /*!< UCMODE Bit 1 */ -#define UCMODE_0 EUSCI_A_CTLW0_MODE_0 /*!< UART mode */ -#define UCMODE_1 EUSCI_A_CTLW0_MODE_1 /*!< Idle-line multiprocessor mode */ -#define UCMODE_2 EUSCI_A_CTLW0_MODE_2 /*!< Address-bit multiprocessor mode */ -#define UCMODE_3 EUSCI_A_CTLW0_MODE_3 /*!< UART mode with automatic baud-rate detection */ -/* UCA0CTLW0[UCSPB] Bits */ -#define UCSPB_OFS EUSCI_A_CTLW0_SPB_OFS /*!< UCSPB Offset */ -#define UCSPB EUSCI_A_CTLW0_SPB /*!< Stop bit select */ -/* UCA0CTLW0[UC7BIT] Bits */ -#define UC7BIT_OFS EUSCI_A_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */ -#define UC7BIT EUSCI_A_CTLW0_SEVENBIT /*!< Character length */ -/* UCA0CTLW0[UCMSB] Bits */ -#define UCMSB_OFS EUSCI_A_CTLW0_MSB_OFS /*!< UCMSB Offset */ -#define UCMSB EUSCI_A_CTLW0_MSB /*!< MSB first select */ -/* UCA0CTLW0[UCPAR] Bits */ -#define UCPAR_OFS EUSCI_A_CTLW0_PAR_OFS /*!< UCPAR Offset */ -#define UCPAR EUSCI_A_CTLW0_PAR /*!< Parity select */ -/* UCA0CTLW0[UCPEN] Bits */ -#define UCPEN_OFS EUSCI_A_CTLW0_PEN_OFS /*!< UCPEN Offset */ -#define UCPEN EUSCI_A_CTLW0_PEN /*!< Parity enable */ -/* UCA0CTLW0_SPI[UCSWRST] Bits */ -//#define UCSWRST_OFS EUSCI_A_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ -//#define UCSWRST EUSCI_A_CTLW0_SWRST /*!< Software reset enable */ -/* UCA0CTLW0_SPI[UCSTEM] Bits */ -#define UCSTEM_OFS EUSCI_A_CTLW0_STEM_OFS /*!< UCSTEM Offset */ -#define UCSTEM EUSCI_A_CTLW0_STEM /*!< STE mode select in master mode. */ -/* UCA0CTLW0_SPI[UCSSEL] Bits */ -//#define UCSSEL_OFS EUSCI_A_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ -//#define UCSSEL_M EUSCI_A_CTLW0_SSEL_MASK /*!< eUSCI_A clock source select */ -//#define UCSSEL0 EUSCI_A_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ -//#define UCSSEL1 EUSCI_A_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ -//#define UCSSEL_0 EUSCI_A_CTLW0_UCSSEL_0 /*!< Reserved */ -//#define UCSSEL_1 EUSCI_A_CTLW0_UCSSEL_1 /*!< ACLK */ -//#define UCSSEL_2 EUSCI_A_CTLW0_UCSSEL_2 /*!< SMCLK */ -//#define UCSSEL__ACLK EUSCI_A_CTLW0_SSEL__ACLK /*!< ACLK */ -//#define UCSSEL__SMCLK EUSCI_A_CTLW0_SSEL__SMCLK /*!< SMCLK */ -/* UCA0CTLW0_SPI[UCSYNC] Bits */ -//#define UCSYNC_OFS EUSCI_A_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ -//#define UCSYNC EUSCI_A_CTLW0_SYNC /*!< Synchronous mode enable */ -/* UCA0CTLW0_SPI[UCMODE] Bits */ -//#define UCMODE_OFS EUSCI_A_CTLW0_MODE_OFS /*!< UCMODE Offset */ -//#define UCMODE_M EUSCI_A_CTLW0_MODE_MASK /*!< eUSCI mode */ -//#define UCMODE0 EUSCI_A_CTLW0_MODE0 /*!< UCMODE Bit 0 */ -//#define UCMODE1 EUSCI_A_CTLW0_MODE1 /*!< UCMODE Bit 1 */ -//#define UCMODE_0 EUSCI_A_CTLW0_MODE_0 /*!< 3-pin SPI */ -//#define UCMODE_1 EUSCI_A_CTLW0_MODE_1 /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */ -//#define UCMODE_2 EUSCI_A_CTLW0_MODE_2 /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */ -/* UCA0CTLW0_SPI[UCMST] Bits */ -#define UCMST_OFS EUSCI_A_CTLW0_MST_OFS /*!< UCMST Offset */ -#define UCMST EUSCI_A_CTLW0_MST /*!< Master mode select */ -/* UCA0CTLW0_SPI[UC7BIT] Bits */ -//#define UC7BIT_OFS EUSCI_A_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */ -//#define UC7BIT EUSCI_A_CTLW0_SEVENBIT /*!< Character length */ -/* UCA0CTLW0_SPI[UCMSB] Bits */ -//#define UCMSB_OFS EUSCI_A_CTLW0_MSB_OFS /*!< UCMSB Offset */ -//#define UCMSB EUSCI_A_CTLW0_MSB /*!< MSB first select */ -/* UCA0CTLW0_SPI[UCCKPL] Bits */ -#define UCCKPL_OFS EUSCI_A_CTLW0_CKPL_OFS /*!< UCCKPL Offset */ -#define UCCKPL EUSCI_A_CTLW0_CKPL /*!< Clock polarity select */ -/* UCA0CTLW0_SPI[UCCKPH] Bits */ -#define UCCKPH_OFS EUSCI_A_CTLW0_CKPH_OFS /*!< UCCKPH Offset */ -#define UCCKPH EUSCI_A_CTLW0_CKPH /*!< Clock phase select */ -/* UCA0CTLW1[UCGLIT] Bits */ -#define UCGLIT_OFS EUSCI_A_CTLW1_GLIT_OFS /*!< UCGLIT Offset */ -#define UCGLIT_M EUSCI_A_CTLW1_GLIT_MASK /*!< Deglitch time */ -#define UCGLIT0 EUSCI_A_CTLW1_GLIT0 /*!< UCGLIT Bit 0 */ -#define UCGLIT1 EUSCI_A_CTLW1_GLIT1 /*!< UCGLIT Bit 1 */ -#define UCGLIT_0 EUSCI_A_CTLW1_GLIT_0 /*!< Approximately 2 ns (equivalent of 1 delay element) */ -#define UCGLIT_1 EUSCI_A_CTLW1_GLIT_1 /*!< Approximately 50 ns */ -#define UCGLIT_2 EUSCI_A_CTLW1_GLIT_2 /*!< Approximately 100 ns */ -#define UCGLIT_3 EUSCI_A_CTLW1_GLIT_3 /*!< Approximately 200 ns */ -/* UCA0MCTLW[UCOS16] Bits */ -#define UCOS16_OFS EUSCI_A_MCTLW_OS16_OFS /*!< UCOS16 Offset */ -#define UCOS16 EUSCI_A_MCTLW_OS16 /*!< Oversampling mode enabled */ -/* UCA0MCTLW[UCBRF] Bits */ -#define UCBRF_OFS EUSCI_A_MCTLW_BRF_OFS /*!< UCBRF Offset */ -#define UCBRF_M EUSCI_A_MCTLW_BRF_MASK /*!< First modulation stage select */ -/* UCA0MCTLW[UCBRS] Bits */ -#define UCBRS_OFS EUSCI_A_MCTLW_BRS_OFS /*!< UCBRS Offset */ -#define UCBRS_M EUSCI_A_MCTLW_BRS_MASK /*!< Second modulation stage select */ -/* UCA0STATW[UCBUSY] Bits */ -#define UCBUSY_OFS EUSCI_A_STATW_BUSY_OFS /*!< UCBUSY Offset */ -#define UCBUSY EUSCI_A_STATW_BUSY /*!< eUSCI_A busy */ -/* UCA0STATW[UCADDR_UCIDLE] Bits */ -#define UCADDR_UCIDLE_OFS EUSCI_A_STATW_ADDR_IDLE_OFS /*!< UCADDR_UCIDLE Offset */ -#define UCADDR_UCIDLE EUSCI_A_STATW_ADDR_IDLE /*!< Address received / Idle line detected */ -/* UCA0STATW[UCRXERR] Bits */ -#define UCRXERR_OFS EUSCI_A_STATW_RXERR_OFS /*!< UCRXERR Offset */ -#define UCRXERR EUSCI_A_STATW_RXERR /*!< Receive error flag */ -/* UCA0STATW[UCBRK] Bits */ -#define UCBRK_OFS EUSCI_A_STATW_BRK_OFS /*!< UCBRK Offset */ -#define UCBRK EUSCI_A_STATW_BRK /*!< Break detect flag */ -/* UCA0STATW[UCPE] Bits */ -#define UCPE_OFS EUSCI_A_STATW_PE_OFS /*!< UCPE Offset */ -#define UCPE EUSCI_A_STATW_PE -/* UCA0STATW[UCOE] Bits */ -#define UCOE_OFS EUSCI_A_STATW_OE_OFS /*!< UCOE Offset */ -#define UCOE EUSCI_A_STATW_OE /*!< Overrun error flag */ -/* UCA0STATW[UCFE] Bits */ -#define UCFE_OFS EUSCI_A_STATW_FE_OFS /*!< UCFE Offset */ -#define UCFE EUSCI_A_STATW_FE /*!< Framing error flag */ -/* UCA0STATW[UCLISTEN] Bits */ -#define UCLISTEN_OFS EUSCI_A_STATW_LISTEN_OFS /*!< UCLISTEN Offset */ -#define UCLISTEN EUSCI_A_STATW_LISTEN /*!< Listen enable */ -/* UCA0STATW_SPI[UCBUSY] Bits */ -//#define UCBUSY_OFS EUSCI_A_STATW_SPI_BUSY_OFS /*!< UCBUSY Offset */ -//#define UCBUSY EUSCI_A_STATW_SPI_BUSY /*!< eUSCI_A busy */ -/* UCA0STATW_SPI[UCOE] Bits */ -//#define UCOE_OFS EUSCI_A_STATW_OE_OFS /*!< UCOE Offset */ -//#define UCOE EUSCI_A_STATW_OE /*!< Overrun error flag */ -/* UCA0STATW_SPI[UCFE] Bits */ -//#define UCFE_OFS EUSCI_A_STATW_FE_OFS /*!< UCFE Offset */ -//#define UCFE EUSCI_A_STATW_FE /*!< Framing error flag */ -/* UCA0STATW_SPI[UCLISTEN] Bits */ -//#define UCLISTEN_OFS EUSCI_A_STATW_LISTEN_OFS /*!< UCLISTEN Offset */ -//#define UCLISTEN EUSCI_A_STATW_LISTEN /*!< Listen enable */ -/* UCA0RXBUF[UCRXBUF] Bits */ -#define UCRXBUF_OFS EUSCI_A_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ -#define UCRXBUF_M EUSCI_A_RXBUF_RXBUF_MASK /*!< Receive data buffer */ -/* UCA0RXBUF_SPI[UCRXBUF] Bits */ -//#define UCRXBUF_OFS EUSCI_A_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ -//#define UCRXBUF_M EUSCI_A_RXBUF_RXBUF_MASK /*!< Receive data buffer */ -/* UCA0TXBUF[UCTXBUF] Bits */ -#define UCTXBUF_OFS EUSCI_A_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ -#define UCTXBUF_M EUSCI_A_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ -/* UCA0TXBUF_SPI[UCTXBUF] Bits */ -//#define UCTXBUF_OFS EUSCI_A_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ -//#define UCTXBUF_M EUSCI_A_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ -/* UCA0ABCTL[UCABDEN] Bits */ -#define UCABDEN_OFS EUSCI_A_ABCTL_ABDEN_OFS /*!< UCABDEN Offset */ -#define UCABDEN EUSCI_A_ABCTL_ABDEN /*!< Automatic baud-rate detect enable */ -/* UCA0ABCTL[UCBTOE] Bits */ -#define UCBTOE_OFS EUSCI_A_ABCTL_BTOE_OFS /*!< UCBTOE Offset */ -#define UCBTOE EUSCI_A_ABCTL_BTOE /*!< Break time out error */ -/* UCA0ABCTL[UCSTOE] Bits */ -#define UCSTOE_OFS EUSCI_A_ABCTL_STOE_OFS /*!< UCSTOE Offset */ -#define UCSTOE EUSCI_A_ABCTL_STOE /*!< Synch field time out error */ -/* UCA0ABCTL[UCDELIM] Bits */ -#define UCDELIM_OFS EUSCI_A_ABCTL_DELIM_OFS /*!< UCDELIM Offset */ -#define UCDELIM_M EUSCI_A_ABCTL_DELIM_MASK /*!< Break/synch delimiter length */ -#define UCDELIM0 EUSCI_A_ABCTL_DELIM0 /*!< UCDELIM Bit 0 */ -#define UCDELIM1 EUSCI_A_ABCTL_DELIM1 /*!< UCDELIM Bit 1 */ -#define UCDELIM_0 EUSCI_A_ABCTL_DELIM_0 /*!< 1 bit time */ -#define UCDELIM_1 EUSCI_A_ABCTL_DELIM_1 /*!< 2 bit times */ -#define UCDELIM_2 EUSCI_A_ABCTL_DELIM_2 /*!< 3 bit times */ -#define UCDELIM_3 EUSCI_A_ABCTL_DELIM_3 /*!< 4 bit times */ -/* UCA0IRCTL[UCIREN] Bits */ -#define UCIREN_OFS EUSCI_A_IRCTL_IREN_OFS /*!< UCIREN Offset */ -#define UCIREN EUSCI_A_IRCTL_IREN /*!< IrDA encoder/decoder enable */ -/* UCA0IRCTL[UCIRTXCLK] Bits */ -#define UCIRTXCLK_OFS EUSCI_A_IRCTL_IRTXCLK_OFS /*!< UCIRTXCLK Offset */ -#define UCIRTXCLK EUSCI_A_IRCTL_IRTXCLK /*!< IrDA transmit pulse clock select */ -/* UCA0IRCTL[UCIRTXPL] Bits */ -#define UCIRTXPL_OFS EUSCI_A_IRCTL_IRTXPL_OFS /*!< UCIRTXPL Offset */ -#define UCIRTXPL_M EUSCI_A_IRCTL_IRTXPL_MASK /*!< Transmit pulse length */ -/* UCA0IRCTL[UCIRRXFE] Bits */ -#define UCIRRXFE_OFS EUSCI_A_IRCTL_IRRXFE_OFS /*!< UCIRRXFE Offset */ -#define UCIRRXFE EUSCI_A_IRCTL_IRRXFE /*!< IrDA receive filter enabled */ -/* UCA0IRCTL[UCIRRXPL] Bits */ -#define UCIRRXPL_OFS EUSCI_A_IRCTL_IRRXPL_OFS /*!< UCIRRXPL Offset */ -#define UCIRRXPL EUSCI_A_IRCTL_IRRXPL /*!< IrDA receive input UCAxRXD polarity */ -/* UCA0IRCTL[UCIRRXFL] Bits */ -#define UCIRRXFL_OFS EUSCI_A_IRCTL_IRRXFL_OFS /*!< UCIRRXFL Offset */ -#define UCIRRXFL_M EUSCI_A_IRCTL_IRRXFL_MASK /*!< Receive filter length */ -/* UCA0IE[UCRXIE] Bits */ -#define UCRXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Offset */ -#define UCRXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -/* UCA0IE[UCTXIE] Bits */ -#define UCTXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Offset */ -#define UCTXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ -/* UCA0IE[UCSTTIE] Bits */ -#define UCSTTIE_OFS EUSCI_A_IE_STTIE_OFS /*!< UCSTTIE Offset */ -#define UCSTTIE EUSCI_A_IE_STTIE /*!< Start bit interrupt enable */ -/* UCA0IE[UCTXCPTIE] Bits */ -#define UCTXCPTIE_OFS EUSCI_A_IE_TXCPTIE_OFS /*!< UCTXCPTIE Offset */ -#define UCTXCPTIE EUSCI_A_IE_TXCPTIE /*!< Transmit complete interrupt enable */ -/* UCA0IE_SPI[UCRXIE] Bits */ -//#define UCRXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Offset */ -//#define UCRXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -/* UCA0IE_SPI[UCTXIE] Bits */ -//#define UCTXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Offset */ -//#define UCTXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ -/* UCA0IFG[UCRXIFG] Bits */ -#define UCRXIFG_OFS EUSCI_A_IFG_RXIFG_OFS /*!< UCRXIFG Offset */ -#define UCRXIFG EUSCI_A_IFG_RXIFG /*!< Receive interrupt flag */ -/* UCA0IFG[UCTXIFG] Bits */ -#define UCTXIFG_OFS EUSCI_A_IFG_TXIFG_OFS /*!< UCTXIFG Offset */ -#define UCTXIFG EUSCI_A_IFG_TXIFG /*!< Transmit interrupt flag */ -/* UCA0IFG[UCSTTIFG] Bits */ -#define UCSTTIFG_OFS EUSCI_A_IFG_STTIFG_OFS /*!< UCSTTIFG Offset */ -#define UCSTTIFG EUSCI_A_IFG_STTIFG /*!< Start bit interrupt flag */ -/* UCA0IFG[UCTXCPTIFG] Bits */ -#define UCTXCPTIFG_OFS EUSCI_A_IFG_TXCPTIFG_OFS /*!< UCTXCPTIFG Offset */ -#define UCTXCPTIFG EUSCI_A_IFG_TXCPTIFG /*!< Transmit ready interrupt enable */ -/* UCA0IFG_SPI[UCRXIFG] Bits */ -//#define UCRXIFG_OFS EUSCI_A_IFG_RXIFG_OFS /*!< UCRXIFG Offset */ -//#define UCRXIFG EUSCI_A_IFG_RXIFG /*!< Receive interrupt flag */ -/* UCA0IFG_SPI[UCTXIFG] Bits */ -//#define UCTXIFG_OFS EUSCI_A_IFG_TXIFG_OFS /*!< UCTXIFG Offset */ -//#define UCTXIFG EUSCI_A_IFG_TXIFG /*!< Transmit interrupt flag */ - -/****************************************************************************** -* EUSCI_B Bits (legacy section) -******************************************************************************/ -/* UCB0CTLW0[UCSWRST] Bits */ -//#define UCSWRST_OFS EUSCI_B_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ -//#define UCSWRST EUSCI_B_CTLW0_SWRST /*!< Software reset enable */ -/* UCB0CTLW0[UCTXSTT] Bits */ -#define UCTXSTT_OFS EUSCI_B_CTLW0_TXSTT_OFS /*!< UCTXSTT Offset */ -#define UCTXSTT EUSCI_B_CTLW0_TXSTT /*!< Transmit START condition in master mode */ -/* UCB0CTLW0[UCTXSTP] Bits */ -#define UCTXSTP_OFS EUSCI_B_CTLW0_TXSTP_OFS /*!< UCTXSTP Offset */ -#define UCTXSTP EUSCI_B_CTLW0_TXSTP /*!< Transmit STOP condition in master mode */ -/* UCB0CTLW0[UCTXNACK] Bits */ -#define UCTXNACK_OFS EUSCI_B_CTLW0_TXNACK_OFS /*!< UCTXNACK Offset */ -#define UCTXNACK EUSCI_B_CTLW0_TXNACK /*!< Transmit a NACK */ -/* UCB0CTLW0[UCTR] Bits */ -#define UCTR_OFS EUSCI_B_CTLW0_TR_OFS /*!< UCTR Offset */ -#define UCTR EUSCI_B_CTLW0_TR /*!< Transmitter/receiver */ -/* UCB0CTLW0[UCTXACK] Bits */ -#define UCTXACK_OFS EUSCI_B_CTLW0_TXACK_OFS /*!< UCTXACK Offset */ -#define UCTXACK EUSCI_B_CTLW0_TXACK /*!< Transmit ACK condition in slave mode */ -/* UCB0CTLW0[UCSSEL] Bits */ -//#define UCSSEL_OFS EUSCI_B_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ -//#define UCSSEL_M EUSCI_B_CTLW0_SSEL_MASK /*!< eUSCI_B clock source select */ -//#define UCSSEL0 EUSCI_B_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ -//#define UCSSEL1 EUSCI_B_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ -//#define UCSSEL_0 EUSCI_B_CTLW0_UCSSEL_0 /*!< UCLKI */ -//#define UCSSEL_1 EUSCI_B_CTLW0_UCSSEL_1 /*!< ACLK */ -//#define UCSSEL_2 EUSCI_B_CTLW0_UCSSEL_2 /*!< SMCLK */ -#define UCSSEL_3 EUSCI_B_CTLW0_UCSSEL_3 /*!< SMCLK */ -#define UCSSEL__UCLKI EUSCI_B_CTLW0_SSEL__UCLKI /*!< UCLKI */ -//#define UCSSEL__ACLK EUSCI_B_CTLW0_SSEL__ACLK /*!< ACLK */ -//#define UCSSEL__SMCLK EUSCI_B_CTLW0_SSEL__SMCLK /*!< SMCLK */ -/* UCB0CTLW0[UCSYNC] Bits */ -//#define UCSYNC_OFS EUSCI_B_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ -//#define UCSYNC EUSCI_B_CTLW0_SYNC /*!< Synchronous mode enable */ -/* UCB0CTLW0[UCMODE] Bits */ -//#define UCMODE_OFS EUSCI_B_CTLW0_MODE_OFS /*!< UCMODE Offset */ -//#define UCMODE_M EUSCI_B_CTLW0_MODE_MASK /*!< eUSCI_B mode */ -//#define UCMODE0 EUSCI_B_CTLW0_MODE0 /*!< UCMODE Bit 0 */ -//#define UCMODE1 EUSCI_B_CTLW0_MODE1 /*!< UCMODE Bit 1 */ -//#define UCMODE_0 EUSCI_B_CTLW0_MODE_0 /*!< 3-pin SPI */ -//#define UCMODE_1 EUSCI_B_CTLW0_MODE_1 /*!< 4-pin SPI (master or slave enabled if STE = 1) */ -//#define UCMODE_2 EUSCI_B_CTLW0_MODE_2 /*!< 4-pin SPI (master or slave enabled if STE = 0) */ -//#define UCMODE_3 EUSCI_B_CTLW0_MODE_3 /*!< I2C mode */ -/* UCB0CTLW0[UCMST] Bits */ -//#define UCMST_OFS EUSCI_B_CTLW0_MST_OFS /*!< UCMST Offset */ -//#define UCMST EUSCI_B_CTLW0_MST /*!< Master mode select */ -/* UCB0CTLW0[UCMM] Bits */ -#define UCMM_OFS EUSCI_B_CTLW0_MM_OFS /*!< UCMM Offset */ -#define UCMM EUSCI_B_CTLW0_MM /*!< Multi-master environment select */ -/* UCB0CTLW0[UCSLA10] Bits */ -#define UCSLA10_OFS EUSCI_B_CTLW0_SLA10_OFS /*!< UCSLA10 Offset */ -#define UCSLA10 EUSCI_B_CTLW0_SLA10 /*!< Slave addressing mode select */ -/* UCB0CTLW0[UCA10] Bits */ -#define UCA10_OFS EUSCI_B_CTLW0_A10_OFS /*!< UCA10 Offset */ -#define UCA10 EUSCI_B_CTLW0_A10 /*!< Own addressing mode select */ -/* UCB0CTLW0_SPI[UCSWRST] Bits */ -//#define UCSWRST_OFS EUSCI_B_CTLW0_SWRST_OFS /*!< UCSWRST Offset */ -//#define UCSWRST EUSCI_B_CTLW0_SWRST /*!< Software reset enable */ -/* UCB0CTLW0_SPI[UCSTEM] Bits */ -//#define UCSTEM_OFS EUSCI_B_CTLW0_STEM_OFS /*!< UCSTEM Offset */ -//#define UCSTEM EUSCI_B_CTLW0_STEM /*!< STE mode select in master mode. */ -/* UCB0CTLW0_SPI[UCSSEL] Bits */ -//#define UCSSEL_OFS EUSCI_B_CTLW0_SSEL_OFS /*!< UCSSEL Offset */ -//#define UCSSEL_M EUSCI_B_CTLW0_SSEL_MASK /*!< eUSCI_B clock source select */ -//#define UCSSEL0 EUSCI_B_CTLW0_SSEL0 /*!< UCSSEL Bit 0 */ -//#define UCSSEL1 EUSCI_B_CTLW0_SSEL1 /*!< UCSSEL Bit 1 */ -//#define UCSSEL_0 EUSCI_B_CTLW0_UCSSEL_0 /*!< Reserved */ -//#define UCSSEL_1 EUSCI_B_CTLW0_UCSSEL_1 /*!< ACLK */ -//#define UCSSEL_2 EUSCI_B_CTLW0_UCSSEL_2 /*!< SMCLK */ -//#define UCSSEL_3 EUSCI_B_CTLW0_UCSSEL_3 /*!< SMCLK */ -//#define UCSSEL__ACLK EUSCI_B_CTLW0_SSEL__ACLK /*!< ACLK */ -//#define UCSSEL__SMCLK EUSCI_B_CTLW0_SSEL__SMCLK /*!< SMCLK */ -/* UCB0CTLW0_SPI[UCSYNC] Bits */ -//#define UCSYNC_OFS EUSCI_B_CTLW0_SYNC_OFS /*!< UCSYNC Offset */ -//#define UCSYNC EUSCI_B_CTLW0_SYNC /*!< Synchronous mode enable */ -/* UCB0CTLW0_SPI[UCMODE] Bits */ -//#define UCMODE_OFS EUSCI_B_CTLW0_MODE_OFS /*!< UCMODE Offset */ -//#define UCMODE_M EUSCI_B_CTLW0_MODE_MASK /*!< eUSCI mode */ -//#define UCMODE0 EUSCI_B_CTLW0_MODE0 /*!< UCMODE Bit 0 */ -//#define UCMODE1 EUSCI_B_CTLW0_MODE1 /*!< UCMODE Bit 1 */ -//#define UCMODE_0 EUSCI_B_CTLW0_MODE_0 /*!< 3-pin SPI */ -//#define UCMODE_1 EUSCI_B_CTLW0_MODE_1 /*!< 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */ -//#define UCMODE_2 EUSCI_B_CTLW0_MODE_2 /*!< 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */ -//#define UCMODE_3 EUSCI_B_CTLW0_MODE_3 /*!< I2C mode */ -/* UCB0CTLW0_SPI[UCMST] Bits */ -//#define UCMST_OFS EUSCI_B_CTLW0_MST_OFS /*!< UCMST Offset */ -//#define UCMST EUSCI_B_CTLW0_MST /*!< Master mode select */ -/* UCB0CTLW0_SPI[UC7BIT] Bits */ -//#define UC7BIT_OFS EUSCI_B_CTLW0_SEVENBIT_OFS /*!< UC7BIT Offset */ -//#define UC7BIT EUSCI_B_CTLW0_SEVENBIT /*!< Character length */ -/* UCB0CTLW0_SPI[UCMSB] Bits */ -//#define UCMSB_OFS EUSCI_B_CTLW0_MSB_OFS /*!< UCMSB Offset */ -//#define UCMSB EUSCI_B_CTLW0_MSB /*!< MSB first select */ -/* UCB0CTLW0_SPI[UCCKPL] Bits */ -//#define UCCKPL_OFS EUSCI_B_CTLW0_CKPL_OFS /*!< UCCKPL Offset */ -//#define UCCKPL EUSCI_B_CTLW0_CKPL /*!< Clock polarity select */ -/* UCB0CTLW0_SPI[UCCKPH] Bits */ -//#define UCCKPH_OFS EUSCI_B_CTLW0_CKPH_OFS /*!< UCCKPH Offset */ -//#define UCCKPH EUSCI_B_CTLW0_CKPH /*!< Clock phase select */ -/* UCB0CTLW1[UCGLIT] Bits */ -//#define UCGLIT_OFS EUSCI_B_CTLW1_GLIT_OFS /*!< UCGLIT Offset */ -//#define UCGLIT_M EUSCI_B_CTLW1_GLIT_MASK /*!< Deglitch time */ -//#define UCGLIT0 EUSCI_B_CTLW1_GLIT0 /*!< UCGLIT Bit 0 */ -//#define UCGLIT1 EUSCI_B_CTLW1_GLIT1 /*!< UCGLIT Bit 1 */ -//#define UCGLIT_0 EUSCI_B_CTLW1_GLIT_0 /*!< 50 ns */ -//#define UCGLIT_1 EUSCI_B_CTLW1_GLIT_1 /*!< 25 ns */ -//#define UCGLIT_2 EUSCI_B_CTLW1_GLIT_2 /*!< 12.5 ns */ -//#define UCGLIT_3 EUSCI_B_CTLW1_GLIT_3 /*!< 6.25 ns */ -/* UCB0CTLW1[UCASTP] Bits */ -#define UCASTP_OFS EUSCI_B_CTLW1_ASTP_OFS /*!< UCASTP Offset */ -#define UCASTP_M EUSCI_B_CTLW1_ASTP_MASK /*!< Automatic STOP condition generation */ -#define UCASTP0 EUSCI_B_CTLW1_ASTP0 /*!< UCASTP Bit 0 */ -#define UCASTP1 EUSCI_B_CTLW1_ASTP1 /*!< UCASTP Bit 1 */ -#define UCASTP_0 EUSCI_B_CTLW1_ASTP_0 /*!< No automatic STOP generation. The STOP condition is generated after the user */ - /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ -#define UCASTP_1 EUSCI_B_CTLW1_ASTP_1 /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ - /* UCBxTBCNT */ -#define UCASTP_2 EUSCI_B_CTLW1_ASTP_2 /*!< A STOP condition is generated automatically after the byte counter value */ - /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ - /* threshold */ -/* UCB0CTLW1[UCSWACK] Bits */ -#define UCSWACK_OFS EUSCI_B_CTLW1_SWACK_OFS /*!< UCSWACK Offset */ -#define UCSWACK EUSCI_B_CTLW1_SWACK /*!< SW or HW ACK control */ -/* UCB0CTLW1[UCSTPNACK] Bits */ -#define UCSTPNACK_OFS EUSCI_B_CTLW1_STPNACK_OFS /*!< UCSTPNACK Offset */ -#define UCSTPNACK EUSCI_B_CTLW1_STPNACK /*!< ACK all master bytes */ -/* UCB0CTLW1[UCCLTO] Bits */ -#define UCCLTO_OFS EUSCI_B_CTLW1_CLTO_OFS /*!< UCCLTO Offset */ -#define UCCLTO_M EUSCI_B_CTLW1_CLTO_MASK /*!< Clock low timeout select */ -#define UCCLTO0 EUSCI_B_CTLW1_CLTO0 /*!< UCCLTO Bit 0 */ -#define UCCLTO1 EUSCI_B_CTLW1_CLTO1 /*!< UCCLTO Bit 1 */ -#define UCCLTO_0 EUSCI_B_CTLW1_CLTO_0 /*!< Disable clock low timeout counter */ -#define UCCLTO_1 EUSCI_B_CTLW1_CLTO_1 /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ -#define UCCLTO_2 EUSCI_B_CTLW1_CLTO_2 /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ -#define UCCLTO_3 EUSCI_B_CTLW1_CLTO_3 /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ -/* UCB0CTLW1[UCETXINT] Bits */ -#define UCETXINT_OFS EUSCI_B_CTLW1_ETXINT_OFS /*!< UCETXINT Offset */ -#define UCETXINT EUSCI_B_CTLW1_ETXINT /*!< Early UCTXIFG0 */ -/* UCB0STATW[UCBBUSY] Bits */ -#define UCBBUSY_OFS EUSCI_B_STATW_BBUSY_OFS /*!< UCBBUSY Offset */ -#define UCBBUSY EUSCI_B_STATW_BBUSY /*!< Bus busy */ -/* UCB0STATW[UCGC] Bits */ -#define UCGC_OFS EUSCI_B_STATW_GC_OFS /*!< UCGC Offset */ -#define UCGC EUSCI_B_STATW_GC /*!< General call address received */ -/* UCB0STATW[UCSCLLOW] Bits */ -#define UCSCLLOW_OFS EUSCI_B_STATW_SCLLOW_OFS /*!< UCSCLLOW Offset */ -#define UCSCLLOW EUSCI_B_STATW_SCLLOW /*!< SCL low */ -/* UCB0STATW[UCBCNT] Bits */ -#define UCBCNT_OFS EUSCI_B_STATW_BCNT_OFS /*!< UCBCNT Offset */ -#define UCBCNT_M EUSCI_B_STATW_BCNT_MASK /*!< Hardware byte counter value */ -/* UCB0STATW_SPI[UCBUSY] Bits */ -//#define UCBUSY_OFS EUSCI_B_STATW_SPI_BUSY_OFS /*!< UCBUSY Offset */ -//#define UCBUSY EUSCI_B_STATW_SPI_BUSY /*!< eUSCI_B busy */ -/* UCB0STATW_SPI[UCOE] Bits */ -//#define UCOE_OFS EUSCI_B_STATW_OE_OFS /*!< UCOE Offset */ -//#define UCOE EUSCI_B_STATW_OE /*!< Overrun error flag */ -/* UCB0STATW_SPI[UCFE] Bits */ -//#define UCFE_OFS EUSCI_B_STATW_FE_OFS /*!< UCFE Offset */ -//#define UCFE EUSCI_B_STATW_FE /*!< Framing error flag */ -/* UCB0STATW_SPI[UCLISTEN] Bits */ -//#define UCLISTEN_OFS EUSCI_B_STATW_LISTEN_OFS /*!< UCLISTEN Offset */ -//#define UCLISTEN EUSCI_B_STATW_LISTEN /*!< Listen enable */ -/* UCB0TBCNT[UCTBCNT] Bits */ -#define UCTBCNT_OFS EUSCI_B_TBCNT_TBCNT_OFS /*!< UCTBCNT Offset */ -#define UCTBCNT_M EUSCI_B_TBCNT_TBCNT_MASK /*!< Byte counter threshold value */ -/* UCB0RXBUF[UCRXBUF] Bits */ -//#define UCRXBUF_OFS EUSCI_B_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ -//#define UCRXBUF_M EUSCI_B_RXBUF_RXBUF_MASK /*!< Receive data buffer */ -/* UCB0RXBUF_SPI[UCRXBUF] Bits */ -//#define UCRXBUF_OFS EUSCI_B_RXBUF_RXBUF_OFS /*!< UCRXBUF Offset */ -//#define UCRXBUF_M EUSCI_B_RXBUF_RXBUF_MASK /*!< Receive data buffer */ -/* UCB0TXBUF[UCTXBUF] Bits */ -//#define UCTXBUF_OFS EUSCI_B_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ -//#define UCTXBUF_M EUSCI_B_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ -/* UCB0TXBUF_SPI[UCTXBUF] Bits */ -//#define UCTXBUF_OFS EUSCI_B_TXBUF_TXBUF_OFS /*!< UCTXBUF Offset */ -//#define UCTXBUF_M EUSCI_B_TXBUF_TXBUF_MASK /*!< Transmit data buffer */ -/* UCB0I2COA0[I2COA0] Bits */ -#define I2COA0_OFS EUSCI_B_I2COA0_I2COA0_OFS /*!< I2COA0 Offset */ -#define I2COA0_M EUSCI_B_I2COA0_I2COA0_MASK /*!< I2C own address */ -/* UCB0I2COA0[UCOAEN] Bits */ -#define UCOAEN_OFS EUSCI_B_I2COA0_OAEN_OFS /*!< UCOAEN Offset */ -#define UCOAEN EUSCI_B_I2COA0_OAEN /*!< Own Address enable register */ -/* UCB0I2COA0[UCGCEN] Bits */ -#define UCGCEN_OFS EUSCI_B_I2COA0_GCEN_OFS /*!< UCGCEN Offset */ -#define UCGCEN EUSCI_B_I2COA0_GCEN /*!< General call response enable */ -/* UCB0I2COA1[I2COA1] Bits */ -#define I2COA1_OFS EUSCI_B_I2COA1_I2COA1_OFS /*!< I2COA1 Offset */ -#define I2COA1_M EUSCI_B_I2COA1_I2COA1_MASK /*!< I2C own address */ -/* UCB0I2COA1[UCOAEN] Bits */ -//#define UCOAEN_OFS EUSCI_B_I2COA1_OAEN_OFS /*!< UCOAEN Offset */ -//#define UCOAEN EUSCI_B_I2COA1_OAEN /*!< Own Address enable register */ -/* UCB0I2COA2[I2COA2] Bits */ -#define I2COA2_OFS EUSCI_B_I2COA2_I2COA2_OFS /*!< I2COA2 Offset */ -#define I2COA2_M EUSCI_B_I2COA2_I2COA2_MASK /*!< I2C own address */ -/* UCB0I2COA2[UCOAEN] Bits */ -//#define UCOAEN_OFS EUSCI_B_I2COA2_OAEN_OFS /*!< UCOAEN Offset */ -//#define UCOAEN EUSCI_B_I2COA2_OAEN /*!< Own Address enable register */ -/* UCB0I2COA3[I2COA3] Bits */ -#define I2COA3_OFS EUSCI_B_I2COA3_I2COA3_OFS /*!< I2COA3 Offset */ -#define I2COA3_M EUSCI_B_I2COA3_I2COA3_MASK /*!< I2C own address */ -/* UCB0I2COA3[UCOAEN] Bits */ -//#define UCOAEN_OFS EUSCI_B_I2COA3_OAEN_OFS /*!< UCOAEN Offset */ -//#define UCOAEN EUSCI_B_I2COA3_OAEN /*!< Own Address enable register */ -/* UCB0ADDRX[ADDRX] Bits */ -#define ADDRX_OFS EUSCI_B_ADDRX_ADDRX_OFS /*!< ADDRX Offset */ -#define ADDRX_M EUSCI_B_ADDRX_ADDRX_MASK /*!< Received Address Register */ -#define ADDRX0 EUSCI_B_ADDRX_ADDRX0 /*!< ADDRX Bit 0 */ -#define ADDRX1 EUSCI_B_ADDRX_ADDRX1 /*!< ADDRX Bit 1 */ -#define ADDRX2 EUSCI_B_ADDRX_ADDRX2 /*!< ADDRX Bit 2 */ -#define ADDRX3 EUSCI_B_ADDRX_ADDRX3 /*!< ADDRX Bit 3 */ -#define ADDRX4 EUSCI_B_ADDRX_ADDRX4 /*!< ADDRX Bit 4 */ -#define ADDRX5 EUSCI_B_ADDRX_ADDRX5 /*!< ADDRX Bit 5 */ -#define ADDRX6 EUSCI_B_ADDRX_ADDRX6 /*!< ADDRX Bit 6 */ -#define ADDRX7 EUSCI_B_ADDRX_ADDRX7 /*!< ADDRX Bit 7 */ -#define ADDRX8 EUSCI_B_ADDRX_ADDRX8 /*!< ADDRX Bit 8 */ -#define ADDRX9 EUSCI_B_ADDRX_ADDRX9 /*!< ADDRX Bit 9 */ -/* UCB0ADDMASK[ADDMASK] Bits */ -#define ADDMASK_OFS EUSCI_B_ADDMASK_ADDMASK_OFS /*!< ADDMASK Offset */ -#define ADDMASK_M EUSCI_B_ADDMASK_ADDMASK_MASK -/* UCB0I2CSA[I2CSA] Bits */ -#define I2CSA_OFS EUSCI_B_I2CSA_I2CSA_OFS /*!< I2CSA Offset */ -#define I2CSA_M EUSCI_B_I2CSA_I2CSA_MASK /*!< I2C slave address */ -/* UCB0IE[UCRXIE0] Bits */ -#define UCRXIE0_OFS EUSCI_B_IE_RXIE0_OFS /*!< UCRXIE0 Offset */ -#define UCRXIE0 EUSCI_B_IE_RXIE0 /*!< Receive interrupt enable 0 */ -/* UCB0IE[UCTXIE0] Bits */ -#define UCTXIE0_OFS EUSCI_B_IE_TXIE0_OFS /*!< UCTXIE0 Offset */ -#define UCTXIE0 EUSCI_B_IE_TXIE0 /*!< Transmit interrupt enable 0 */ -/* UCB0IE[UCSTTIE] Bits */ -//#define UCSTTIE_OFS EUSCI_B_IE_STTIE_OFS /*!< UCSTTIE Offset */ -//#define UCSTTIE EUSCI_B_IE_STTIE /*!< START condition interrupt enable */ -/* UCB0IE[UCSTPIE] Bits */ -#define UCSTPIE_OFS EUSCI_B_IE_STPIE_OFS /*!< UCSTPIE Offset */ -#define UCSTPIE EUSCI_B_IE_STPIE /*!< STOP condition interrupt enable */ -/* UCB0IE[UCALIE] Bits */ -#define UCALIE_OFS EUSCI_B_IE_ALIE_OFS /*!< UCALIE Offset */ -#define UCALIE EUSCI_B_IE_ALIE /*!< Arbitration lost interrupt enable */ -/* UCB0IE[UCNACKIE] Bits */ -#define UCNACKIE_OFS EUSCI_B_IE_NACKIE_OFS /*!< UCNACKIE Offset */ -#define UCNACKIE EUSCI_B_IE_NACKIE /*!< Not-acknowledge interrupt enable */ -/* UCB0IE[UCBCNTIE] Bits */ -#define UCBCNTIE_OFS EUSCI_B_IE_BCNTIE_OFS /*!< UCBCNTIE Offset */ -#define UCBCNTIE EUSCI_B_IE_BCNTIE /*!< Byte counter interrupt enable */ -/* UCB0IE[UCCLTOIE] Bits */ -#define UCCLTOIE_OFS EUSCI_B_IE_CLTOIE_OFS /*!< UCCLTOIE Offset */ -#define UCCLTOIE EUSCI_B_IE_CLTOIE /*!< Clock low timeout interrupt enable */ -/* UCB0IE[UCRXIE1] Bits */ -#define UCRXIE1_OFS EUSCI_B_IE_RXIE1_OFS /*!< UCRXIE1 Offset */ -#define UCRXIE1 EUSCI_B_IE_RXIE1 /*!< Receive interrupt enable 1 */ -/* UCB0IE[UCTXIE1] Bits */ -#define UCTXIE1_OFS EUSCI_B_IE_TXIE1_OFS /*!< UCTXIE1 Offset */ -#define UCTXIE1 EUSCI_B_IE_TXIE1 /*!< Transmit interrupt enable 1 */ -/* UCB0IE[UCRXIE2] Bits */ -#define UCRXIE2_OFS EUSCI_B_IE_RXIE2_OFS /*!< UCRXIE2 Offset */ -#define UCRXIE2 EUSCI_B_IE_RXIE2 /*!< Receive interrupt enable 2 */ -/* UCB0IE[UCTXIE2] Bits */ -#define UCTXIE2_OFS EUSCI_B_IE_TXIE2_OFS /*!< UCTXIE2 Offset */ -#define UCTXIE2 EUSCI_B_IE_TXIE2 /*!< Transmit interrupt enable 2 */ -/* UCB0IE[UCRXIE3] Bits */ -#define UCRXIE3_OFS EUSCI_B_IE_RXIE3_OFS /*!< UCRXIE3 Offset */ -#define UCRXIE3 EUSCI_B_IE_RXIE3 /*!< Receive interrupt enable 3 */ -/* UCB0IE[UCTXIE3] Bits */ -#define UCTXIE3_OFS EUSCI_B_IE_TXIE3_OFS /*!< UCTXIE3 Offset */ -#define UCTXIE3 EUSCI_B_IE_TXIE3 /*!< Transmit interrupt enable 3 */ -/* UCB0IE[UCBIT9IE] Bits */ -#define UCBIT9IE_OFS EUSCI_B_IE_BIT9IE_OFS /*!< UCBIT9IE Offset */ -#define UCBIT9IE EUSCI_B_IE_BIT9IE /*!< Bit position 9 interrupt enable */ -/* UCB0IE_SPI[UCRXIE] Bits */ -//#define UCRXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Offset */ -//#define UCRXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ -/* UCB0IE_SPI[UCTXIE] Bits */ -//#define UCTXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Offset */ -//#define UCTXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ -/* UCB0IFG[UCRXIFG0] Bits */ -#define UCRXIFG0_OFS EUSCI_B_IFG_RXIFG0_OFS /*!< UCRXIFG0 Offset */ -#define UCRXIFG0 EUSCI_B_IFG_RXIFG0 /*!< eUSCI_B receive interrupt flag 0 */ -/* UCB0IFG[UCTXIFG0] Bits */ -#define UCTXIFG0_OFS EUSCI_B_IFG_TXIFG0_OFS /*!< UCTXIFG0 Offset */ -#define UCTXIFG0 EUSCI_B_IFG_TXIFG0 /*!< eUSCI_B transmit interrupt flag 0 */ -/* UCB0IFG[UCSTTIFG] Bits */ -//#define UCSTTIFG_OFS EUSCI_B_IFG_STTIFG_OFS /*!< UCSTTIFG Offset */ -//#define UCSTTIFG EUSCI_B_IFG_STTIFG /*!< START condition interrupt flag */ -/* UCB0IFG[UCSTPIFG] Bits */ -#define UCSTPIFG_OFS EUSCI_B_IFG_STPIFG_OFS /*!< UCSTPIFG Offset */ -#define UCSTPIFG EUSCI_B_IFG_STPIFG /*!< STOP condition interrupt flag */ -/* UCB0IFG[UCALIFG] Bits */ -#define UCALIFG_OFS EUSCI_B_IFG_ALIFG_OFS /*!< UCALIFG Offset */ -#define UCALIFG EUSCI_B_IFG_ALIFG /*!< Arbitration lost interrupt flag */ -/* UCB0IFG[UCNACKIFG] Bits */ -#define UCNACKIFG_OFS EUSCI_B_IFG_NACKIFG_OFS /*!< UCNACKIFG Offset */ -#define UCNACKIFG EUSCI_B_IFG_NACKIFG /*!< Not-acknowledge received interrupt flag */ -/* UCB0IFG[UCBCNTIFG] Bits */ -#define UCBCNTIFG_OFS EUSCI_B_IFG_BCNTIFG_OFS /*!< UCBCNTIFG Offset */ -#define UCBCNTIFG EUSCI_B_IFG_BCNTIFG /*!< Byte counter interrupt flag */ -/* UCB0IFG[UCCLTOIFG] Bits */ -#define UCCLTOIFG_OFS EUSCI_B_IFG_CLTOIFG_OFS /*!< UCCLTOIFG Offset */ -#define UCCLTOIFG EUSCI_B_IFG_CLTOIFG /*!< Clock low timeout interrupt flag */ -/* UCB0IFG[UCRXIFG1] Bits */ -#define UCRXIFG1_OFS EUSCI_B_IFG_RXIFG1_OFS /*!< UCRXIFG1 Offset */ -#define UCRXIFG1 EUSCI_B_IFG_RXIFG1 /*!< eUSCI_B receive interrupt flag 1 */ -/* UCB0IFG[UCTXIFG1] Bits */ -#define UCTXIFG1_OFS EUSCI_B_IFG_TXIFG1_OFS /*!< UCTXIFG1 Offset */ -#define UCTXIFG1 EUSCI_B_IFG_TXIFG1 /*!< eUSCI_B transmit interrupt flag 1 */ -/* UCB0IFG[UCRXIFG2] Bits */ -#define UCRXIFG2_OFS EUSCI_B_IFG_RXIFG2_OFS /*!< UCRXIFG2 Offset */ -#define UCRXIFG2 EUSCI_B_IFG_RXIFG2 /*!< eUSCI_B receive interrupt flag 2 */ -/* UCB0IFG[UCTXIFG2] Bits */ -#define UCTXIFG2_OFS EUSCI_B_IFG_TXIFG2_OFS /*!< UCTXIFG2 Offset */ -#define UCTXIFG2 EUSCI_B_IFG_TXIFG2 /*!< eUSCI_B transmit interrupt flag 2 */ -/* UCB0IFG[UCRXIFG3] Bits */ -#define UCRXIFG3_OFS EUSCI_B_IFG_RXIFG3_OFS /*!< UCRXIFG3 Offset */ -#define UCRXIFG3 EUSCI_B_IFG_RXIFG3 /*!< eUSCI_B receive interrupt flag 3 */ -/* UCB0IFG[UCTXIFG3] Bits */ -#define UCTXIFG3_OFS EUSCI_B_IFG_TXIFG3_OFS /*!< UCTXIFG3 Offset */ -#define UCTXIFG3 EUSCI_B_IFG_TXIFG3 /*!< eUSCI_B transmit interrupt flag 3 */ -/* UCB0IFG[UCBIT9IFG] Bits */ -#define UCBIT9IFG_OFS EUSCI_B_IFG_BIT9IFG_OFS /*!< UCBIT9IFG Offset */ -#define UCBIT9IFG EUSCI_B_IFG_BIT9IFG /*!< Bit position 9 interrupt flag */ -/* UCB0IFG_SPI[UCRXIFG] Bits */ -//#define UCRXIFG_OFS EUSCI_B_IFG_RXIFG_OFS /*!< UCRXIFG Offset */ -//#define UCRXIFG EUSCI_B_IFG_RXIFG /*!< Receive interrupt flag */ -/* UCB0IFG_SPI[UCTXIFG] Bits */ -//#define UCTXIFG_OFS EUSCI_B_IFG_TXIFG_OFS /*!< UCTXIFG Offset */ -//#define UCTXIFG EUSCI_B_IFG_TXIFG /*!< Transmit interrupt flag */ - -/****************************************************************************** -* PMAP Bits (legacy section) -******************************************************************************/ -/* PMAPCTL[PMAPLOCKED] Bits */ -#define PMAPLOCKED_OFS PMAP_CTL_LOCKED_OFS /*!< PMAPLOCKED Offset */ -#define PMAPLOCKED PMAP_CTL_LOCKED /*!< Port mapping lock bit */ -/* PMAPCTL[PMAPRECFG] Bits */ -#define PMAPRECFG_OFS PMAP_CTL_PRECFG_OFS /*!< PMAPRECFG Offset */ -#define PMAPRECFG PMAP_CTL_PRECFG /*!< Port mapping reconfiguration control bit */ -/* Pre-defined bitfield values */ -/* PMAP_PMAPCTL[PMAPLOCKED] Bits */ -#define PMAPLOCKED_OFS PMAP_CTL_LOCKED_OFS /*!< PMAPLOCKED Offset */ -#define PMAPLOCKED PMAP_CTL_LOCKED /*!< Port mapping lock bit */ -/* PMAP_PMAPCTL[PMAPRECFG] Bits */ -#define PMAPRECFG_OFS PMAP_CTL_PRECFG_OFS /*!< PMAPRECFG Offset */ -#define PMAPRECFG PMAP_CTL_PRECFG /*!< Port mapping reconfiguration control bit */ - -#define PM_NONE PMAP_NONE -#define PM_UCA0CLK PMAP_UCA0CLK -#define PM_UCA0RXD PMAP_UCA0RXD -#define PM_UCA0SOMI PMAP_UCA0SOMI -#define PM_UCA0TXD PMAP_UCA0TXD -#define PM_UCA0SIMO PMAP_UCA0SIMO -#define PM_UCB0CLK PMAP_UCB0CLK -#define PM_UCB0SDA PMAP_UCB0SDA -#define PM_UCB0SIMO PMAP_UCB0SIMO -#define PM_UCB0SCL PMAP_UCB0SCL -#define PM_UCB0SOMI PMAP_UCB0SOMI -#define PM_UCA1STE PMAP_UCA1STE -#define PM_UCA1CLK PMAP_UCA1CLK -#define PM_UCA1RXD PMAP_UCA1RXD -#define PM_UCA1SOMI PMAP_UCA1SOMI -#define PM_UCA1TXD PMAP_UCA1TXD -#define PM_UCA1SIMO PMAP_UCA1SIMO -#define PM_UCA2STE PMAP_UCA2STE -#define PM_UCA2CLK PMAP_UCA2CLK -#define PM_UCA2RXD PMAP_UCA2RXD -#define PM_UCA2SOMI PMAP_UCA2SOMI -#define PM_UCA2TXD PMAP_UCA2TXD -#define PM_UCA2SIMO PMAP_UCA2SIMO -#define PM_UCB2STE PMAP_UCB2STE -#define PM_UCB2CLK PMAP_UCB2CLK -#define PM_UCB2SDA PMAP_UCB2SDA -#define PM_UCB2SIMO PMAP_UCB2SIMO -#define PM_UCB2SCL PMAP_UCB2SCL -#define PM_UCB2SOMI PMAP_UCB2SOMI -#define PM_TA0CCR0A PMAP_TA0CCR0A -#define PM_TA0CCR1A PMAP_TA0CCR1A -#define PM_TA0CCR2A PMAP_TA0CCR2A -#define PM_TA0CCR3A PMAP_TA0CCR3A -#define PM_TA0CCR4A PMAP_TA0CCR4A -#define PM_TA1CCR1A PMAP_TA1CCR1A -#define PM_TA1CCR2A PMAP_TA1CCR2A -#define PM_TA1CCR3A PMAP_TA1CCR3A -#define PM_TA1CCR4A PMAP_TA1CCR4A -#define PM_TA0CLK PMAP_TA0CLK -#define PM_CE0OUT PMAP_CE0OUT -#define PM_TA1CLK PMAP_TA1CLK -#define PM_CE1OUT PMAP_CE1OUT -#define PM_DMAE0 PMAP_DMAE0 -#define PM_SMCLK PMAP_SMCLK -#define PM_ANALOG PMAP_ANALOG - -#define PMAPKEY PMAP_KEYID_VAL /*!< Port Mapping Key */ -#define PMAPPWD PMAP_KEYID_VAL /*!< Legacy Definition: Mapping Key register */ -#define PMAPPW PMAP_KEYID_VAL /*!< Legacy Definition: Port Mapping Password */ - - -/****************************************************************************** -* REF_A Bits (legacy section) -******************************************************************************/ -/* REFCTL0[REFON] Bits */ -#define REFON_OFS REF_A_CTL0_ON_OFS /*!< REFON Offset */ -#define REFON REF_A_CTL0_ON /*!< Reference enable */ -/* REFCTL0[REFOUT] Bits */ -#define REFOUT_OFS REF_A_CTL0_OUT_OFS /*!< REFOUT Offset */ -#define REFOUT REF_A_CTL0_OUT /*!< Reference output buffer */ -/* REFCTL0[REFTCOFF] Bits */ -#define REFTCOFF_OFS REF_A_CTL0_TCOFF_OFS /*!< REFTCOFF Offset */ -#define REFTCOFF REF_A_CTL0_TCOFF /*!< Temperature sensor disabled */ -/* REFCTL0[REFVSEL] Bits */ -#define REFVSEL_OFS REF_A_CTL0_VSEL_OFS /*!< REFVSEL Offset */ -#define REFVSEL_M REF_A_CTL0_VSEL_MASK /*!< Reference voltage level select */ -#define REFVSEL0 REF_A_CTL0_VSEL0 /*!< REFVSEL Bit 0 */ -#define REFVSEL1 REF_A_CTL0_VSEL1 /*!< REFVSEL Bit 1 */ -#define REFVSEL_0 REF_A_CTL0_VSEL_0 /*!< 1.2 V available when reference requested or REFON = 1 */ -#define REFVSEL_1 REF_A_CTL0_VSEL_1 /*!< 1.45 V available when reference requested or REFON = 1 */ -#define REFVSEL_3 REF_A_CTL0_VSEL_3 /*!< 2.5 V available when reference requested or REFON = 1 */ -/* REFCTL0[REFGENOT] Bits */ -#define REFGENOT_OFS REF_A_CTL0_GENOT_OFS /*!< REFGENOT Offset */ -#define REFGENOT REF_A_CTL0_GENOT /*!< Reference generator one-time trigger */ -/* REFCTL0[REFBGOT] Bits */ -#define REFBGOT_OFS REF_A_CTL0_BGOT_OFS /*!< REFBGOT Offset */ -#define REFBGOT REF_A_CTL0_BGOT /*!< Bandgap and bandgap buffer one-time trigger */ -/* REFCTL0[REFGENACT] Bits */ -#define REFGENACT_OFS REF_A_CTL0_GENACT_OFS /*!< REFGENACT Offset */ -#define REFGENACT REF_A_CTL0_GENACT /*!< Reference generator active */ -/* REFCTL0[REFBGACT] Bits */ -#define REFBGACT_OFS REF_A_CTL0_BGACT_OFS /*!< REFBGACT Offset */ -#define REFBGACT REF_A_CTL0_BGACT /*!< Reference bandgap active */ -/* REFCTL0[REFGENBUSY] Bits */ -#define REFGENBUSY_OFS REF_A_CTL0_GENBUSY_OFS /*!< REFGENBUSY Offset */ -#define REFGENBUSY REF_A_CTL0_GENBUSY /*!< Reference generator busy */ -/* REFCTL0[BGMODE] Bits */ -#define BGMODE_OFS REF_A_CTL0_BGMODE_OFS /*!< BGMODE Offset */ -#define BGMODE REF_A_CTL0_BGMODE /*!< Bandgap mode */ -/* REFCTL0[REFGENRDY] Bits */ -#define REFGENRDY_OFS REF_A_CTL0_GENRDY_OFS /*!< REFGENRDY Offset */ -#define REFGENRDY REF_A_CTL0_GENRDY /*!< Variable reference voltage ready status */ -/* REFCTL0[REFBGRDY] Bits */ -#define REFBGRDY_OFS REF_A_CTL0_BGRDY_OFS /*!< REFBGRDY Offset */ -#define REFBGRDY REF_A_CTL0_BGRDY /*!< Buffered bandgap voltage ready status */ - -/****************************************************************************** -* RTC_C Bits (legacy section) -******************************************************************************/ -/* RTCCTL0[RTCRDYIFG] Bits */ -#define RTCRDYIFG_OFS RTC_C_CTL0_RDYIFG_OFS /*!< RTCRDYIFG Offset */ -#define RTCRDYIFG RTC_C_CTL0_RDYIFG /*!< Real-time clock ready interrupt flag */ -/* RTCCTL0[RTCAIFG] Bits */ -#define RTCAIFG_OFS RTC_C_CTL0_AIFG_OFS /*!< RTCAIFG Offset */ -#define RTCAIFG RTC_C_CTL0_AIFG /*!< Real-time clock alarm interrupt flag */ -/* RTCCTL0[RTCTEVIFG] Bits */ -#define RTCTEVIFG_OFS RTC_C_CTL0_TEVIFG_OFS /*!< RTCTEVIFG Offset */ -#define RTCTEVIFG RTC_C_CTL0_TEVIFG /*!< Real-time clock time event interrupt flag */ -/* RTCCTL0[RTCOFIFG] Bits */ -#define RTCOFIFG_OFS RTC_C_CTL0_OFIFG_OFS /*!< RTCOFIFG Offset */ -#define RTCOFIFG RTC_C_CTL0_OFIFG /*!< 32-kHz crystal oscillator fault interrupt flag */ -/* RTCCTL0[RTCRDYIE] Bits */ -#define RTCRDYIE_OFS RTC_C_CTL0_RDYIE_OFS /*!< RTCRDYIE Offset */ -#define RTCRDYIE RTC_C_CTL0_RDYIE /*!< Real-time clock ready interrupt enable */ -/* RTCCTL0[RTCAIE] Bits */ -#define RTCAIE_OFS RTC_C_CTL0_AIE_OFS /*!< RTCAIE Offset */ -#define RTCAIE RTC_C_CTL0_AIE /*!< Real-time clock alarm interrupt enable */ -/* RTCCTL0[RTCTEVIE] Bits */ -#define RTCTEVIE_OFS RTC_C_CTL0_TEVIE_OFS /*!< RTCTEVIE Offset */ -#define RTCTEVIE RTC_C_CTL0_TEVIE /*!< Real-time clock time event interrupt enable */ -/* RTCCTL0[RTCOFIE] Bits */ -#define RTCOFIE_OFS RTC_C_CTL0_OFIE_OFS /*!< RTCOFIE Offset */ -#define RTCOFIE RTC_C_CTL0_OFIE /*!< 32-kHz crystal oscillator fault interrupt enable */ -/* RTCCTL0[RTCKEY] Bits */ -#define RTCKEY_OFS RTC_C_CTL0_KEY_OFS /*!< RTCKEY Offset */ -#define RTCKEY_M RTC_C_CTL0_KEY_MASK /*!< Real-time clock key */ -/* RTCCTL13[RTCTEV] Bits */ -#define RTCTEV_OFS RTC_C_CTL13_TEV_OFS /*!< RTCTEV Offset */ -#define RTCTEV_M RTC_C_CTL13_TEV_MASK /*!< Real-time clock time event */ -#define RTCTEV0 RTC_C_CTL13_TEV0 /*!< RTCTEV Bit 0 */ -#define RTCTEV1 RTC_C_CTL13_TEV1 /*!< RTCTEV Bit 1 */ -#define RTCTEV_0 RTC_C_CTL13_TEV_0 /*!< Minute changed */ -#define RTCTEV_1 RTC_C_CTL13_TEV_1 /*!< Hour changed */ -#define RTCTEV_2 RTC_C_CTL13_TEV_2 /*!< Every day at midnight (00:00) */ -#define RTCTEV_3 RTC_C_CTL13_TEV_3 /*!< Every day at noon (12:00) */ -/* RTCCTL13[RTCSSEL] Bits */ -#define RTCSSEL_OFS RTC_C_CTL13_SSEL_OFS /*!< RTCSSEL Offset */ -#define RTCSSEL_M RTC_C_CTL13_SSEL_MASK /*!< Real-time clock source select */ -#define RTCSSEL0 RTC_C_CTL13_SSEL0 /*!< RTCSSEL Bit 0 */ -#define RTCSSEL1 RTC_C_CTL13_SSEL1 /*!< RTCSSEL Bit 1 */ -#define RTCSSEL_0 RTC_C_CTL13_SSEL_0 /*!< BCLK */ -#define RTCSSEL__BCLK RTC_C_CTL13_SSEL__BCLK /*!< BCLK */ -/* RTCCTL13[RTCRDY] Bits */ -#define RTCRDY_OFS RTC_C_CTL13_RDY_OFS /*!< RTCRDY Offset */ -#define RTCRDY RTC_C_CTL13_RDY /*!< Real-time clock ready */ -/* RTCCTL13[RTCMODE] Bits */ -#define RTCMODE_OFS RTC_C_CTL13_MODE_OFS /*!< RTCMODE Offset */ -#define RTCMODE RTC_C_CTL13_MODE -/* RTCCTL13[RTCHOLD] Bits */ -#define RTCHOLD_OFS RTC_C_CTL13_HOLD_OFS /*!< RTCHOLD Offset */ -#define RTCHOLD RTC_C_CTL13_HOLD /*!< Real-time clock hold */ -/* RTCCTL13[RTCBCD] Bits */ -#define RTCBCD_OFS RTC_C_CTL13_BCD_OFS /*!< RTCBCD Offset */ -#define RTCBCD RTC_C_CTL13_BCD /*!< Real-time clock BCD select */ -/* RTCCTL13[RTCCALF] Bits */ -#define RTCCALF_OFS RTC_C_CTL13_CALF_OFS /*!< RTCCALF Offset */ -#define RTCCALF_M RTC_C_CTL13_CALF_MASK /*!< Real-time clock calibration frequency */ -#define RTCCALF0 RTC_C_CTL13_CALF0 /*!< RTCCALF Bit 0 */ -#define RTCCALF1 RTC_C_CTL13_CALF1 /*!< RTCCALF Bit 1 */ -#define RTCCALF_0 RTC_C_CTL13_CALF_0 /*!< No frequency output to RTCCLK pin */ -#define RTCCALF_1 RTC_C_CTL13_CALF_1 /*!< 512 Hz */ -#define RTCCALF_2 RTC_C_CTL13_CALF_2 /*!< 256 Hz */ -#define RTCCALF_3 RTC_C_CTL13_CALF_3 /*!< 1 Hz */ -#define RTCCALF__NONE RTC_C_CTL13_CALF__NONE /*!< No frequency output to RTCCLK pin */ -#define RTCCALF__512 RTC_C_CTL13_CALF__512 /*!< 512 Hz */ -#define RTCCALF__256 RTC_C_CTL13_CALF__256 /*!< 256 Hz */ -#define RTCCALF__1 RTC_C_CTL13_CALF__1 /*!< 1 Hz */ -/* RTCOCAL[RTCOCAL] Bits */ -#define RTCOCAL_OFS RTC_C_OCAL_OCAL_OFS /*!< RTCOCAL Offset */ -#define RTCOCAL_M RTC_C_OCAL_OCAL_MASK /*!< Real-time clock offset error calibration */ -/* RTCOCAL[RTCOCALS] Bits */ -#define RTCOCALS_OFS RTC_C_OCAL_OCALS_OFS /*!< RTCOCALS Offset */ -#define RTCOCALS RTC_C_OCAL_OCALS /*!< Real-time clock offset error calibration sign */ -/* RTCTCMP[RTCTCMP] Bits */ -#define RTCTCMP_OFS RTC_C_TCMP_TCMPX_OFS /*!< RTCTCMP Offset */ -#define RTCTCMP_M RTC_C_TCMP_TCMPX_MASK /*!< Real-time clock temperature compensation */ -/* RTCTCMP[RTCTCOK] Bits */ -#define RTCTCOK_OFS RTC_C_TCMP_TCOK_OFS /*!< RTCTCOK Offset */ -#define RTCTCOK RTC_C_TCMP_TCOK /*!< Real-time clock temperature compensation write OK */ -/* RTCTCMP[RTCTCRDY] Bits */ -#define RTCTCRDY_OFS RTC_C_TCMP_TCRDY_OFS /*!< RTCTCRDY Offset */ -#define RTCTCRDY RTC_C_TCMP_TCRDY /*!< Real-time clock temperature compensation ready */ -/* RTCTCMP[RTCTCMPS] Bits */ -#define RTCTCMPS_OFS RTC_C_TCMP_TCMPS_OFS /*!< RTCTCMPS Offset */ -#define RTCTCMPS RTC_C_TCMP_TCMPS /*!< Real-time clock temperature compensation sign */ -/* RTCPS0CTL[RT0PSIFG] Bits */ -#define RT0PSIFG_OFS RTC_C_PS0CTL_RT0PSIFG_OFS /*!< RT0PSIFG Offset */ -#define RT0PSIFG RTC_C_PS0CTL_RT0PSIFG /*!< Prescale timer 0 interrupt flag */ -/* RTCPS0CTL[RT0PSIE] Bits */ -#define RT0PSIE_OFS RTC_C_PS0CTL_RT0PSIE_OFS /*!< RT0PSIE Offset */ -#define RT0PSIE RTC_C_PS0CTL_RT0PSIE /*!< Prescale timer 0 interrupt enable */ -/* RTCPS0CTL[RT0IP] Bits */ -#define RT0IP_OFS RTC_C_PS0CTL_RT0IP_OFS /*!< RT0IP Offset */ -#define RT0IP_M RTC_C_PS0CTL_RT0IP_MASK /*!< Prescale timer 0 interrupt interval */ -#define RT0IP0 RTC_C_PS0CTL_RT0IP0 /*!< RT0IP Bit 0 */ -#define RT0IP1 RTC_C_PS0CTL_RT0IP1 /*!< RT0IP Bit 1 */ -#define RT0IP2 RTC_C_PS0CTL_RT0IP2 /*!< RT0IP Bit 2 */ -#define RT0IP_0 RTC_C_PS0CTL_RT0IP_0 /*!< Divide by 2 */ -#define RT0IP_1 RTC_C_PS0CTL_RT0IP_1 /*!< Divide by 4 */ -#define RT0IP_2 RTC_C_PS0CTL_RT0IP_2 /*!< Divide by 8 */ -#define RT0IP_3 RTC_C_PS0CTL_RT0IP_3 /*!< Divide by 16 */ -#define RT0IP_4 RTC_C_PS0CTL_RT0IP_4 /*!< Divide by 32 */ -#define RT0IP_5 RTC_C_PS0CTL_RT0IP_5 /*!< Divide by 64 */ -#define RT0IP_6 RTC_C_PS0CTL_RT0IP_6 /*!< Divide by 128 */ -#define RT0IP_7 RTC_C_PS0CTL_RT0IP_7 /*!< Divide by 256 */ -#define RT0IP__2 RTC_C_PS0CTL_RT0IP__2 /*!< Divide by 2 */ -#define RT0IP__4 RTC_C_PS0CTL_RT0IP__4 /*!< Divide by 4 */ -#define RT0IP__8 RTC_C_PS0CTL_RT0IP__8 /*!< Divide by 8 */ -#define RT0IP__16 RTC_C_PS0CTL_RT0IP__16 /*!< Divide by 16 */ -#define RT0IP__32 RTC_C_PS0CTL_RT0IP__32 /*!< Divide by 32 */ -#define RT0IP__64 RTC_C_PS0CTL_RT0IP__64 /*!< Divide by 64 */ -#define RT0IP__128 RTC_C_PS0CTL_RT0IP__128 /*!< Divide by 128 */ -#define RT0IP__256 RTC_C_PS0CTL_RT0IP__256 /*!< Divide by 256 */ -/* RTCPS1CTL[RT1PSIFG] Bits */ -#define RT1PSIFG_OFS RTC_C_PS1CTL_RT1PSIFG_OFS /*!< RT1PSIFG Offset */ -#define RT1PSIFG RTC_C_PS1CTL_RT1PSIFG /*!< Prescale timer 1 interrupt flag */ -/* RTCPS1CTL[RT1PSIE] Bits */ -#define RT1PSIE_OFS RTC_C_PS1CTL_RT1PSIE_OFS /*!< RT1PSIE Offset */ -#define RT1PSIE RTC_C_PS1CTL_RT1PSIE /*!< Prescale timer 1 interrupt enable */ -/* RTCPS1CTL[RT1IP] Bits */ -#define RT1IP_OFS RTC_C_PS1CTL_RT1IP_OFS /*!< RT1IP Offset */ -#define RT1IP_M RTC_C_PS1CTL_RT1IP_MASK /*!< Prescale timer 1 interrupt interval */ -#define RT1IP0 RTC_C_PS1CTL_RT1IP0 /*!< RT1IP Bit 0 */ -#define RT1IP1 RTC_C_PS1CTL_RT1IP1 /*!< RT1IP Bit 1 */ -#define RT1IP2 RTC_C_PS1CTL_RT1IP2 /*!< RT1IP Bit 2 */ -#define RT1IP_0 RTC_C_PS1CTL_RT1IP_0 /*!< Divide by 2 */ -#define RT1IP_1 RTC_C_PS1CTL_RT1IP_1 /*!< Divide by 4 */ -#define RT1IP_2 RTC_C_PS1CTL_RT1IP_2 /*!< Divide by 8 */ -#define RT1IP_3 RTC_C_PS1CTL_RT1IP_3 /*!< Divide by 16 */ -#define RT1IP_4 RTC_C_PS1CTL_RT1IP_4 /*!< Divide by 32 */ -#define RT1IP_5 RTC_C_PS1CTL_RT1IP_5 /*!< Divide by 64 */ -#define RT1IP_6 RTC_C_PS1CTL_RT1IP_6 /*!< Divide by 128 */ -#define RT1IP_7 RTC_C_PS1CTL_RT1IP_7 /*!< Divide by 256 */ -#define RT1IP__2 RTC_C_PS1CTL_RT1IP__2 /*!< Divide by 2 */ -#define RT1IP__4 RTC_C_PS1CTL_RT1IP__4 /*!< Divide by 4 */ -#define RT1IP__8 RTC_C_PS1CTL_RT1IP__8 /*!< Divide by 8 */ -#define RT1IP__16 RTC_C_PS1CTL_RT1IP__16 /*!< Divide by 16 */ -#define RT1IP__32 RTC_C_PS1CTL_RT1IP__32 /*!< Divide by 32 */ -#define RT1IP__64 RTC_C_PS1CTL_RT1IP__64 /*!< Divide by 64 */ -#define RT1IP__128 RTC_C_PS1CTL_RT1IP__128 /*!< Divide by 128 */ -#define RT1IP__256 RTC_C_PS1CTL_RT1IP__256 /*!< Divide by 256 */ -/* RTCPS[RT0PS] Bits */ -#define RT0PS_OFS RTC_C_PS_RT0PS_OFS /*!< RT0PS Offset */ -#define RT0PS_M RTC_C_PS_RT0PS_MASK /*!< Prescale timer 0 counter value */ -/* RTCPS[RT1PS] Bits */ -#define RT1PS_OFS RTC_C_PS_RT1PS_OFS /*!< RT1PS Offset */ -#define RT1PS_M RTC_C_PS_RT1PS_MASK /*!< Prescale timer 1 counter value */ -/* RTCTIM0[SECONDS] Bits */ -#define SECONDS_OFS RTC_C_TIM0_SEC_OFS /*!< Seconds Offset */ -#define SECONDS_M RTC_C_TIM0_SEC_MASK /*!< Seconds (0 to 59) */ -/* RTCTIM0[MINUTES] Bits */ -#define MINUTES_OFS RTC_C_TIM0_MIN_OFS /*!< Minutes Offset */ -#define MINUTES_M RTC_C_TIM0_MIN_MASK /*!< Minutes (0 to 59) */ -/* RTCTIM0_BCD[SECONDSLOWDIGIT] Bits */ -#define SECONDSLOWDIGIT_OFS RTC_C_TIM0_SEC_LD_OFS /*!< SecondsLowDigit Offset */ -#define SECONDSLOWDIGIT_M RTC_C_TIM0_SEC_LD_MASK /*!< Seconds low digit (0 to 9) */ -/* RTCTIM0_BCD[SECONDSHIGHDIGIT] Bits */ -#define SECONDSHIGHDIGIT_OFS RTC_C_TIM0_SEC_HD_OFS /*!< SecondsHighDigit Offset */ -#define SECONDSHIGHDIGIT_M RTC_C_TIM0_SEC_HD_MASK /*!< Seconds high digit (0 to 5) */ -/* RTCTIM0_BCD[MINUTESLOWDIGIT] Bits */ -#define MINUTESLOWDIGIT_OFS RTC_C_TIM0_MIN_LD_OFS /*!< MinutesLowDigit Offset */ -#define MINUTESLOWDIGIT_M RTC_C_TIM0_MIN_LD_MASK /*!< Minutes low digit (0 to 9) */ -/* RTCTIM0_BCD[MINUTESHIGHDIGIT] Bits */ -#define MINUTESHIGHDIGIT_OFS RTC_C_TIM0_MIN_HD_OFS /*!< MinutesHighDigit Offset */ -#define MINUTESHIGHDIGIT_M RTC_C_TIM0_MIN_HD_MASK /*!< Minutes high digit (0 to 5) */ -/* RTCTIM1[HOURS] Bits */ -#define HOURS_OFS RTC_C_TIM1_HOUR_OFS /*!< Hours Offset */ -#define HOURS_M RTC_C_TIM1_HOUR_MASK /*!< Hours (0 to 23) */ -/* RTCTIM1[DAYOFWEEK] Bits */ -#define DAYOFWEEK_OFS RTC_C_TIM1_DOW_OFS /*!< DayofWeek Offset */ -#define DAYOFWEEK_M RTC_C_TIM1_DOW_MASK /*!< Day of week (0 to 6) */ -/* RTCTIM1_BCD[HOURSLOWDIGIT] Bits */ -#define HOURSLOWDIGIT_OFS RTC_C_TIM1_HOUR_LD_OFS /*!< HoursLowDigit Offset */ -#define HOURSLOWDIGIT_M RTC_C_TIM1_HOUR_LD_MASK /*!< Hours low digit (0 to 9) */ -/* RTCTIM1_BCD[HOURSHIGHDIGIT] Bits */ -#define HOURSHIGHDIGIT_OFS RTC_C_TIM1_HOUR_HD_OFS /*!< HoursHighDigit Offset */ -#define HOURSHIGHDIGIT_M RTC_C_TIM1_HOUR_HD_MASK /*!< Hours high digit (0 to 2) */ -/* RTCTIM1_BCD[DAYOFWEEK] Bits */ -//#define DAYOFWEEK_OFS RTC_C_TIM1_DOW_OFS /*!< DayofWeek Offset */ -//#define DAYOFWEEK_M RTC_C_TIM1_DOW_MASK /*!< Day of week (0 to 6) */ -/* RTCDATE[DAY] Bits */ -#define DAY_OFS RTC_C_DATE_DAY_OFS /*!< Day Offset */ -#define DAY_M RTC_C_DATE_DAY_MASK /*!< Day of month (1 to 28, 29, 30, 31) */ -/* RTCDATE[MONTH] Bits */ -#define MONTH_OFS RTC_C_DATE_MON_OFS /*!< Month Offset */ -#define MONTH_M RTC_C_DATE_MON_MASK /*!< Month (1 to 12) */ -/* RTCDATE_BCD[DAYLOWDIGIT] Bits */ -#define DAYLOWDIGIT_OFS RTC_C_DATE_DAY_LD_OFS /*!< DayLowDigit Offset */ -#define DAYLOWDIGIT_M RTC_C_DATE_DAY_LD_MASK /*!< Day of month low digit (0 to 9) */ -/* RTCDATE_BCD[DAYHIGHDIGIT] Bits */ -#define DAYHIGHDIGIT_OFS RTC_C_DATE_DAY_HD_OFS /*!< DayHighDigit Offset */ -#define DAYHIGHDIGIT_M RTC_C_DATE_DAY_HD_MASK /*!< Day of month high digit (0 to 3) */ -/* RTCDATE_BCD[MONTHLOWDIGIT] Bits */ -#define MONTHLOWDIGIT_OFS RTC_C_DATE_MON_LD_OFS /*!< MonthLowDigit Offset */ -#define MONTHLOWDIGIT_M RTC_C_DATE_MON_LD_MASK /*!< Month low digit (0 to 9) */ -/* RTCDATE_BCD[MONTHHIGHDIGIT] Bits */ -#define MONTHHIGHDIGIT_OFS RTC_C_DATE_MON_HD_OFS /*!< MonthHighDigit Offset */ -#define MONTHHIGHDIGIT RTC_C_DATE_MON_HD /*!< Month high digit (0 or 1) */ -/* RTCYEAR[YEARLOWBYTE] Bits */ -#define YEARLOWBYTE_OFS RTC_C_YEAR_YEAR_LB_OFS /*!< YearLowByte Offset */ -#define YEARLOWBYTE_M RTC_C_YEAR_YEAR_LB_MASK /*!< Year low byte. Valid values for Year are 0 to 4095. */ -/* RTCYEAR[YEARHIGHBYTE] Bits */ -#define YEARHIGHBYTE_OFS RTC_C_YEAR_YEAR_HB_OFS /*!< YearHighByte Offset */ -#define YEARHIGHBYTE_M RTC_C_YEAR_YEAR_HB_MASK /*!< Year high byte. Valid values for Year are 0 to 4095. */ -/* RTCYEAR_BCD[YEAR] Bits */ -#define YEAR_OFS RTC_C_YEAR_YEAR_OFS /*!< Year Offset */ -#define YEAR_M RTC_C_YEAR_YEAR_MASK /*!< Year lowest digit (0 to 9) */ -/* RTCYEAR_BCD[DECADE] Bits */ -#define DECADE_OFS RTC_C_YEAR_DEC_OFS /*!< Decade Offset */ -#define DECADE_M RTC_C_YEAR_DEC_MASK /*!< Decade (0 to 9) */ -/* RTCYEAR_BCD[CENTURYLOWDIGIT] Bits */ -#define CENTURYLOWDIGIT_OFS RTC_C_YEAR_CENT_LD_OFS /*!< CenturyLowDigit Offset */ -#define CENTURYLOWDIGIT_M RTC_C_YEAR_CENT_LD_MASK /*!< Century low digit (0 to 9) */ -/* RTCYEAR_BCD[CENTURYHIGHDIGIT] Bits */ -#define CENTURYHIGHDIGIT_OFS RTC_C_YEAR_CENT_HD_OFS /*!< CenturyHighDigit Offset */ -#define CENTURYHIGHDIGIT_M RTC_C_YEAR_CENT_HD_MASK /*!< Century high digit (0 to 4) */ -/* RTCAMINHR[MINUTES] Bits */ -//#define MINUTES_OFS RTC_C_AMINHR_MIN_OFS /*!< Minutes Offset */ -//#define MINUTES_M RTC_C_AMINHR_MIN_MASK /*!< Minutes (0 to 59) */ -/* RTCAMINHR[MINAE] Bits */ -#define MINAE_OFS RTC_C_AMINHR_MINAE_OFS /*!< MINAE Offset */ -#define MINAE RTC_C_AMINHR_MINAE /*!< Alarm enable */ -/* RTCAMINHR[HOURS] Bits */ -//#define HOURS_OFS RTC_C_AMINHR_HOUR_OFS /*!< Hours Offset */ -//#define HOURS_M RTC_C_AMINHR_HOUR_MASK /*!< Hours (0 to 23) */ -/* RTCAMINHR[HOURAE] Bits */ -#define HOURAE_OFS RTC_C_AMINHR_HOURAE_OFS /*!< HOURAE Offset */ -#define HOURAE RTC_C_AMINHR_HOURAE /*!< Alarm enable */ -/* RTCAMINHR_BCD[MINUTESLOWDIGIT] Bits */ -//#define MINUTESLOWDIGIT_OFS RTC_C_AMINHR_MIN_LD_OFS /*!< MinutesLowDigit Offset */ -//#define MINUTESLOWDIGIT_M RTC_C_AMINHR_MIN_LD_MASK /*!< Minutes low digit (0 to 9) */ -/* RTCAMINHR_BCD[MINUTESHIGHDIGIT] Bits */ -//#define MINUTESHIGHDIGIT_OFS RTC_C_AMINHR_MIN_HD_OFS /*!< MinutesHighDigit Offset */ -//#define MINUTESHIGHDIGIT_M RTC_C_AMINHR_MIN_HD_MASK /*!< Minutes high digit (0 to 5) */ -/* RTCAMINHR_BCD[MINAE] Bits */ -//#define MINAE_OFS RTC_C_AMINHR_MINAE_OFS /*!< MINAE Offset */ -//#define MINAE RTC_C_AMINHR_MINAE /*!< Alarm enable */ -/* RTCAMINHR_BCD[HOURSLOWDIGIT] Bits */ -//#define HOURSLOWDIGIT_OFS RTC_C_AMINHR_HOUR_LD_OFS /*!< HoursLowDigit Offset */ -//#define HOURSLOWDIGIT_M RTC_C_AMINHR_HOUR_LD_MASK /*!< Hours low digit (0 to 9) */ -/* RTCAMINHR_BCD[HOURSHIGHDIGIT] Bits */ -//#define HOURSHIGHDIGIT_OFS RTC_C_AMINHR_HOUR_HD_OFS /*!< HoursHighDigit Offset */ -//#define HOURSHIGHDIGIT_M RTC_C_AMINHR_HOUR_HD_MASK /*!< Hours high digit (0 to 2) */ -/* RTCAMINHR_BCD[HOURAE] Bits */ -//#define HOURAE_OFS RTC_C_AMINHR_HOURAE_OFS /*!< HOURAE Offset */ -//#define HOURAE RTC_C_AMINHR_HOURAE /*!< Alarm enable */ -/* RTCADOWDAY[DAYOFWEEK] Bits */ -//#define DAYOFWEEK_OFS RTC_C_ADOWDAY_DOW_OFS /*!< DayofWeek Offset */ -//#define DAYOFWEEK_M RTC_C_ADOWDAY_DOW_MASK /*!< Day of week (0 to 6) */ -/* RTCADOWDAY[DOWAE] Bits */ -#define DOWAE_OFS RTC_C_ADOWDAY_DOWAE_OFS /*!< DOWAE Offset */ -#define DOWAE RTC_C_ADOWDAY_DOWAE /*!< Alarm enable */ -/* RTCADOWDAY[DAYOFMONTH] Bits */ -#define DAYOFMONTH_OFS RTC_C_ADOWDAY_DAY_OFS /*!< DayofMonth Offset */ -#define DAYOFMONTH_M RTC_C_ADOWDAY_DAY_MASK /*!< Day of month (1 to 28, 29, 30, 31) */ -/* RTCADOWDAY[DAYAE] Bits */ -#define DAYAE_OFS RTC_C_ADOWDAY_DAYAE_OFS /*!< DAYAE Offset */ -#define DAYAE RTC_C_ADOWDAY_DAYAE /*!< Alarm enable */ -/* RTCADOWDAY_BCD[DAYOFWEEK] Bits */ -//#define DAYOFWEEK_OFS RTC_C_ADOWDAY_DOW_OFS /*!< DayofWeek Offset */ -//#define DAYOFWEEK_M RTC_C_ADOWDAY_DOW_MASK /*!< Day of week (0 to 6) */ -/* RTCADOWDAY_BCD[DOWAE] Bits */ -//#define DOWAE_OFS RTC_C_ADOWDAY_DOWAE_OFS /*!< DOWAE Offset */ -//#define DOWAE RTC_C_ADOWDAY_DOWAE /*!< Alarm enable */ -/* RTCADOWDAY_BCD[DAYLOWDIGIT] Bits */ -//#define DAYLOWDIGIT_OFS RTC_C_ADOWDAY_DAY_LD_OFS /*!< DayLowDigit Offset */ -//#define DAYLOWDIGIT_M RTC_C_ADOWDAY_DAY_LD_MASK /*!< Day of month low digit (0 to 9) */ -/* RTCADOWDAY_BCD[DAYHIGHDIGIT] Bits */ -//#define DAYHIGHDIGIT_OFS RTC_C_ADOWDAY_DAY_HD_OFS /*!< DayHighDigit Offset */ -//#define DAYHIGHDIGIT_M RTC_C_ADOWDAY_DAY_HD_MASK /*!< Day of month high digit (0 to 3) */ -/* RTCADOWDAY_BCD[DAYAE] Bits */ -//#define DAYAE_OFS RTC_C_ADOWDAY_DAYAE_OFS /*!< DAYAE Offset */ -//#define DAYAE RTC_C_ADOWDAY_DAYAE /*!< Alarm enable */ -/* Pre-defined bitfield values */ -#define RTCKEY RTC_C_KEY /*!< RTC_C Key Value for RTC_C write access */ -#define RTCKEY_H RTC_C_KEY_H /*!< RTC_C Key Value for RTC_C write access */ -#define RTCKEY_VAL RTC_C_KEY_VAL /*!< RTC_C Key Value for RTC_C write access */ - - -/****************************************************************************** -* TIMER_A Bits (legacy section) -******************************************************************************/ -/* TA0CTL[TAIFG] Bits */ -#define TAIFG_OFS TIMER_A_CTL_IFG_OFS /*!< TAIFG Offset */ -#define TAIFG TIMER_A_CTL_IFG /*!< TimerA interrupt flag */ -/* TA0CTL[TAIE] Bits */ -#define TAIE_OFS TIMER_A_CTL_IE_OFS /*!< TAIE Offset */ -#define TAIE TIMER_A_CTL_IE /*!< TimerA interrupt enable */ -/* TA0CTL[TACLR] Bits */ -#define TACLR_OFS TIMER_A_CTL_CLR_OFS /*!< TACLR Offset */ -#define TACLR TIMER_A_CTL_CLR /*!< TimerA clear */ -/* TA0CTL[MC] Bits */ -#define MC_OFS TIMER_A_CTL_MC_OFS /*!< MC Offset */ -#define MC_M TIMER_A_CTL_MC_MASK /*!< Mode control */ -#define MC0 TIMER_A_CTL_MC0 /*!< MC Bit 0 */ -#define MC1 TIMER_A_CTL_MC1 /*!< MC Bit 1 */ -#define MC_0 TIMER_A_CTL_MC_0 /*!< Stop mode: Timer is halted */ -#define MC_1 TIMER_A_CTL_MC_1 /*!< Up mode: Timer counts up to TAxCCR0 */ -#define MC_2 TIMER_A_CTL_MC_2 /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define MC_3 TIMER_A_CTL_MC_3 /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -#define MC__STOP TIMER_A_CTL_MC__STOP /*!< Stop mode: Timer is halted */ -#define MC__UP TIMER_A_CTL_MC__UP /*!< Up mode: Timer counts up to TAxCCR0 */ -#define MC__CONTINUOUS TIMER_A_CTL_MC__CONTINUOUS /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define MC__UPDOWN TIMER_A_CTL_MC__UPDOWN /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -/* TA0CTL[ID] Bits */ -#define ID_OFS TIMER_A_CTL_ID_OFS /*!< ID Offset */ -#define ID_M TIMER_A_CTL_ID_MASK /*!< Input divider */ -#define ID0 TIMER_A_CTL_ID0 /*!< ID Bit 0 */ -#define ID1 TIMER_A_CTL_ID1 /*!< ID Bit 1 */ -#define ID_0 TIMER_A_CTL_ID_0 /*!< /1 */ -#define ID_1 TIMER_A_CTL_ID_1 /*!< /2 */ -#define ID_2 TIMER_A_CTL_ID_2 /*!< /4 */ -#define ID_3 TIMER_A_CTL_ID_3 /*!< /8 */ -#define ID__1 TIMER_A_CTL_ID__1 /*!< /1 */ -#define ID__2 TIMER_A_CTL_ID__2 /*!< /2 */ -#define ID__4 TIMER_A_CTL_ID__4 /*!< /4 */ -#define ID__8 TIMER_A_CTL_ID__8 /*!< /8 */ -/* TA0CTL[TASSEL] Bits */ -#define TASSEL_OFS TIMER_A_CTL_SSEL_OFS /*!< TASSEL Offset */ -#define TASSEL_M TIMER_A_CTL_SSEL_MASK /*!< TimerA clock source select */ -#define TASSEL0 TIMER_A_CTL_SSEL0 /*!< TASSEL Bit 0 */ -#define TASSEL1 TIMER_A_CTL_SSEL1 /*!< TASSEL Bit 1 */ -#define TASSEL_0 TIMER_A_CTL_TASSEL_0 /*!< TAxCLK */ -#define TASSEL_1 TIMER_A_CTL_TASSEL_1 /*!< ACLK */ -#define TASSEL_2 TIMER_A_CTL_TASSEL_2 /*!< SMCLK */ -#define TASSEL_3 TIMER_A_CTL_TASSEL_3 /*!< INCLK */ -#define TASSEL__TACLK TIMER_A_CTL_SSEL__TACLK /*!< TAxCLK */ -#define TASSEL__ACLK TIMER_A_CTL_SSEL__ACLK /*!< ACLK */ -#define TASSEL__SMCLK TIMER_A_CTL_SSEL__SMCLK /*!< SMCLK */ -#define TASSEL__INCLK TIMER_A_CTL_SSEL__INCLK /*!< INCLK */ -/* TA0CCTLn[CCIFG] Bits */ -#define CCIFG_OFS TIMER_A_CCTLN_CCIFG_OFS /*!< CCIFG Offset */ -#define CCIFG TIMER_A_CCTLN_CCIFG /*!< Capture/compare interrupt flag */ -/* TA0CCTLn[COV] Bits */ -#define COV_OFS TIMER_A_CCTLN_COV_OFS /*!< COV Offset */ -#define COV TIMER_A_CCTLN_COV /*!< Capture overflow */ -/* TA0CCTLn[OUT] Bits */ -#define OUT_OFS TIMER_A_CCTLN_OUT_OFS /*!< OUT Offset */ -//#define OUT TIMER_A_CCTLN_OUT /*!< Output */ -/* TA0CCTLn[CCI] Bits */ -#define CCI_OFS TIMER_A_CCTLN_CCI_OFS /*!< CCI Offset */ -#define CCI TIMER_A_CCTLN_CCI /*!< Capture/compare input */ -/* TA0CCTLn[CCIE] Bits */ -#define CCIE_OFS TIMER_A_CCTLN_CCIE_OFS /*!< CCIE Offset */ -#define CCIE TIMER_A_CCTLN_CCIE /*!< Capture/compare interrupt enable */ -/* TA0CCTLn[OUTMOD] Bits */ -#define OUTMOD_OFS TIMER_A_CCTLN_OUTMOD_OFS /*!< OUTMOD Offset */ -#define OUTMOD_M TIMER_A_CCTLN_OUTMOD_MASK /*!< Output mode */ -#define OUTMOD0 TIMER_A_CCTLN_OUTMOD0 /*!< OUTMOD Bit 0 */ -#define OUTMOD1 TIMER_A_CCTLN_OUTMOD1 /*!< OUTMOD Bit 1 */ -#define OUTMOD2 TIMER_A_CCTLN_OUTMOD2 /*!< OUTMOD Bit 2 */ -#define OUTMOD_0 TIMER_A_CCTLN_OUTMOD_0 /*!< OUT bit value */ -#define OUTMOD_1 TIMER_A_CCTLN_OUTMOD_1 /*!< Set */ -#define OUTMOD_2 TIMER_A_CCTLN_OUTMOD_2 /*!< Toggle/reset */ -#define OUTMOD_3 TIMER_A_CCTLN_OUTMOD_3 /*!< Set/reset */ -#define OUTMOD_4 TIMER_A_CCTLN_OUTMOD_4 /*!< Toggle */ -#define OUTMOD_5 TIMER_A_CCTLN_OUTMOD_5 /*!< Reset */ -#define OUTMOD_6 TIMER_A_CCTLN_OUTMOD_6 /*!< Toggle/set */ -#define OUTMOD_7 TIMER_A_CCTLN_OUTMOD_7 /*!< Reset/set */ -/* TA0CCTLn[CAP] Bits */ -#define CAP_OFS TIMER_A_CCTLN_CAP_OFS /*!< CAP Offset */ -#define CAP TIMER_A_CCTLN_CAP /*!< Capture mode */ -/* TA0CCTLn[SCCI] Bits */ -#define SCCI_OFS TIMER_A_CCTLN_SCCI_OFS /*!< SCCI Offset */ -#define SCCI TIMER_A_CCTLN_SCCI /*!< Synchronized capture/compare input */ -/* TA0CCTLn[SCS] Bits */ -#define SCS_OFS TIMER_A_CCTLN_SCS_OFS /*!< SCS Offset */ -#define SCS TIMER_A_CCTLN_SCS /*!< Synchronize capture source */ -/* TA0CCTLn[CCIS] Bits */ -#define CCIS_OFS TIMER_A_CCTLN_CCIS_OFS /*!< CCIS Offset */ -#define CCIS_M TIMER_A_CCTLN_CCIS_MASK /*!< Capture/compare input select */ -#define CCIS0 TIMER_A_CCTLN_CCIS0 /*!< CCIS Bit 0 */ -#define CCIS1 TIMER_A_CCTLN_CCIS1 /*!< CCIS Bit 1 */ -#define CCIS_0 TIMER_A_CCTLN_CCIS_0 /*!< CCIxA */ -#define CCIS_1 TIMER_A_CCTLN_CCIS_1 /*!< CCIxB */ -#define CCIS_2 TIMER_A_CCTLN_CCIS_2 /*!< GND */ -#define CCIS_3 TIMER_A_CCTLN_CCIS_3 /*!< VCC */ -#define CCIS__CCIA TIMER_A_CCTLN_CCIS__CCIA /*!< CCIxA */ -#define CCIS__CCIB TIMER_A_CCTLN_CCIS__CCIB /*!< CCIxB */ -#define CCIS__GND TIMER_A_CCTLN_CCIS__GND /*!< GND */ -#define CCIS__VCC TIMER_A_CCTLN_CCIS__VCC /*!< VCC */ -/* TA0CCTLn[CM] Bits */ -#define CM_OFS TIMER_A_CCTLN_CM_OFS /*!< CM Offset */ -#define CM_M TIMER_A_CCTLN_CM_MASK /*!< Capture mode */ -#define CM0 TIMER_A_CCTLN_CM0 /*!< CM Bit 0 */ -#define CM1 TIMER_A_CCTLN_CM1 /*!< CM Bit 1 */ -#define CM_0 TIMER_A_CCTLN_CM_0 /*!< No capture */ -#define CM_1 TIMER_A_CCTLN_CM_1 /*!< Capture on rising edge */ -#define CM_2 TIMER_A_CCTLN_CM_2 /*!< Capture on falling edge */ -#define CM_3 TIMER_A_CCTLN_CM_3 /*!< Capture on both rising and falling edges */ -#define CM__NONE TIMER_A_CCTLN_CM__NONE /*!< No capture */ -#define CM__RISING TIMER_A_CCTLN_CM__RISING /*!< Capture on rising edge */ -#define CM__FALLING TIMER_A_CCTLN_CM__FALLING /*!< Capture on falling edge */ -#define CM__BOTH TIMER_A_CCTLN_CM__BOTH /*!< Capture on both rising and falling edges */ -/* TA0EX0[TAIDEX] Bits */ -#define TAIDEX_OFS TIMER_A_EX0_IDEX_OFS /*!< TAIDEX Offset */ -#define TAIDEX_M TIMER_A_EX0_IDEX_MASK /*!< Input divider expansion */ -#define TAIDEX0 TIMER_A_EX0_IDEX0 /*!< TAIDEX Bit 0 */ -#define TAIDEX1 TIMER_A_EX0_IDEX1 /*!< TAIDEX Bit 1 */ -#define TAIDEX2 TIMER_A_EX0_IDEX2 /*!< TAIDEX Bit 2 */ -#define TAIDEX_0 TIMER_A_EX0_TAIDEX_0 /*!< Divide by 1 */ -#define TAIDEX_1 TIMER_A_EX0_TAIDEX_1 /*!< Divide by 2 */ -#define TAIDEX_2 TIMER_A_EX0_TAIDEX_2 /*!< Divide by 3 */ -#define TAIDEX_3 TIMER_A_EX0_TAIDEX_3 /*!< Divide by 4 */ -#define TAIDEX_4 TIMER_A_EX0_TAIDEX_4 /*!< Divide by 5 */ -#define TAIDEX_5 TIMER_A_EX0_TAIDEX_5 /*!< Divide by 6 */ -#define TAIDEX_6 TIMER_A_EX0_TAIDEX_6 /*!< Divide by 7 */ -#define TAIDEX_7 TIMER_A_EX0_TAIDEX_7 /*!< Divide by 8 */ -#define TAIDEX__1 TIMER_A_EX0_IDEX__1 /*!< Divide by 1 */ -#define TAIDEX__2 TIMER_A_EX0_IDEX__2 /*!< Divide by 2 */ -#define TAIDEX__3 TIMER_A_EX0_IDEX__3 /*!< Divide by 3 */ -#define TAIDEX__4 TIMER_A_EX0_IDEX__4 /*!< Divide by 4 */ -#define TAIDEX__5 TIMER_A_EX0_IDEX__5 /*!< Divide by 5 */ -#define TAIDEX__6 TIMER_A_EX0_IDEX__6 /*!< Divide by 6 */ -#define TAIDEX__7 TIMER_A_EX0_IDEX__7 /*!< Divide by 7 */ -#define TAIDEX__8 TIMER_A_EX0_IDEX__8 /*!< Divide by 8 */ - -/****************************************************************************** -* WDT_A Bits (legacy section) -******************************************************************************/ -/* WDTCTL[WDTIS] Bits */ -#define WDTIS_OFS WDT_A_CTL_IS_OFS /*!< WDTIS Offset */ -#define WDTIS_M WDT_A_CTL_IS_MASK /*!< Watchdog timer interval select */ -#define WDTIS0 WDT_A_CTL_IS0 /*!< WDTIS Bit 0 */ -#define WDTIS1 WDT_A_CTL_IS1 /*!< WDTIS Bit 1 */ -#define WDTIS2 WDT_A_CTL_IS2 /*!< WDTIS Bit 2 */ -#define WDTIS_0 WDT_A_CTL_IS_0 /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ -#define WDTIS_1 WDT_A_CTL_IS_1 /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ -#define WDTIS_2 WDT_A_CTL_IS_2 /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ -#define WDTIS_3 WDT_A_CTL_IS_3 /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ -#define WDTIS_4 WDT_A_CTL_IS_4 /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ -#define WDTIS_5 WDT_A_CTL_IS_5 /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ -#define WDTIS_6 WDT_A_CTL_IS_6 /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ -#define WDTIS_7 WDT_A_CTL_IS_7 /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ -/* WDTCTL[WDTCNTCL] Bits */ -#define WDTCNTCL_OFS WDT_A_CTL_CNTCL_OFS /*!< WDTCNTCL Offset */ -#define WDTCNTCL WDT_A_CTL_CNTCL /*!< Watchdog timer counter clear */ -/* WDTCTL[WDTTMSEL] Bits */ -#define WDTTMSEL_OFS WDT_A_CTL_TMSEL_OFS /*!< WDTTMSEL Offset */ -#define WDTTMSEL WDT_A_CTL_TMSEL /*!< Watchdog timer mode select */ -/* WDTCTL[WDTSSEL] Bits */ -#define WDTSSEL_OFS WDT_A_CTL_SSEL_OFS /*!< WDTSSEL Offset */ -#define WDTSSEL_M WDT_A_CTL_SSEL_MASK /*!< Watchdog timer clock source select */ -#define WDTSSEL0 WDT_A_CTL_SSEL0 /*!< WDTSSEL Bit 0 */ -#define WDTSSEL1 WDT_A_CTL_SSEL1 /*!< WDTSSEL Bit 1 */ -#define WDTSSEL_0 WDT_A_CTL_SSEL_0 /*!< SMCLK */ -#define WDTSSEL_1 WDT_A_CTL_SSEL_1 /*!< ACLK */ -#define WDTSSEL_2 WDT_A_CTL_SSEL_2 /*!< VLOCLK */ -#define WDTSSEL_3 WDT_A_CTL_SSEL_3 /*!< BCLK */ -#define WDTSSEL__SMCLK WDT_A_CTL_SSEL__SMCLK /*!< SMCLK */ -#define WDTSSEL__ACLK WDT_A_CTL_SSEL__ACLK /*!< ACLK */ -#define WDTSSEL__VLOCLK WDT_A_CTL_SSEL__VLOCLK /*!< VLOCLK */ -#define WDTSSEL__BCLK WDT_A_CTL_SSEL__BCLK /*!< BCLK */ -/* WDTCTL[WDTHOLD] Bits */ -#define WDTHOLD_OFS WDT_A_CTL_HOLD_OFS /*!< WDTHOLD Offset */ -#define WDTHOLD WDT_A_CTL_HOLD /*!< Watchdog timer hold */ -/* WDTCTL[WDTPW] Bits */ -#define WDTPW_OFS WDT_A_CTL_PW_OFS /*!< WDTPW Offset */ -#define WDTPW_M WDT_A_CTL_PW_MASK /*!< Watchdog timer password */ -/* Pre-defined bitfield values */ -#define WDTPW WDT_A_CTL_PW /*!< WDT Key Value for WDT write access */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __MSP432P401R_CLASSIC_H__ */ diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p4111.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p4111.h deleted file mode 100644 index b76d0a97276..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p4111.h +++ /dev/null @@ -1,9839 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432P4111 Register Definitions -* -* This file includes CMSIS compliant component and register definitions -* -* For legacy components the definitions that are compatible with MSP430 code, -* are included with msp432p4111_classic.h -* -* With CMSIS definitions, the register defines have been reformatted: -* ModuleName[ModuleInstance]->RegisterName -* -* Writing to CMSIS bit fields can be done through register level -* or via bitband area access: -* - ADC14->CTL0 |= ADC14_CTL0_ENC; -* - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1; -* -* File creation date: 2017-08-03 -* -******************************************************************************/ - -#ifndef __MSP432P4111_H__ -#define __MSP432P4111_H__ - -/* Use standard integer types with explicit width */ -#include - -#ifdef __cplusplus - extern "C" { -#endif - -#define __MSP432_HEADER_VERSION__ 3202 - -/* Remap MSP432 intrinsics to ARM equivalents */ -#include "msp_compatibility.h" - -#ifndef __CMSIS_CONFIG__ -#define __CMSIS_CONFIG__ - -/** @addtogroup MSP432P4111_Definitions MSP432P4111 Definitions - This file defines all structures and symbols for MSP432P4111: - - components and registers - - peripheral base address - - peripheral ID - - Peripheral definitions - @{ -*/ - -/****************************************************************************** -* Processor and Core Peripherals * -******************************************************************************/ -/** @addtogroup MSP432P4111_CMSIS Device CMSIS Definitions - Configuration of the Cortex-M4 Processor and Core Peripherals - @{ -*/ - -/****************************************************************************** -* CMSIS-compatible Interrupt Number Definition * -******************************************************************************/ -typedef enum IRQn -{ - /* Cortex-M4 Processor Exceptions Numbers */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - /* Peripheral Exceptions Numbers */ - PSS_IRQn = 0, /* 16 PSS Interrupt */ - CS_IRQn = 1, /* 17 CS Interrupt */ - PCM_IRQn = 2, /* 18 PCM Interrupt */ - WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */ - FPU_IRQn = 4, /* 20 FPU Interrupt */ - FLCTL_A_IRQn = 5, /* 21 Flash Controller Interrupt*/ - COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */ - COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */ - TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */ - TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */ - TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */ - TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */ - TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */ - TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */ - TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */ - TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */ - EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */ - EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */ - EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */ - EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */ - EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */ - EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */ - EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */ - EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */ - ADC14_IRQn = 24, /* 40 ADC14 Interrupt */ - T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */ - T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */ - T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */ - AES256_IRQn = 28, /* 44 AES256 Interrupt */ - RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */ - DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */ - DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */ - DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */ - DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */ - DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */ - PORT1_IRQn = 35, /* 51 Port1 Interrupt */ - PORT2_IRQn = 36, /* 52 Port2 Interrupt */ - PORT3_IRQn = 37, /* 53 Port3 Interrupt */ - PORT4_IRQn = 38, /* 54 Port4 Interrupt */ - PORT5_IRQn = 39, /* 55 Port5 Interrupt */ - PORT6_IRQn = 40, /* 56 Port6 Interrupt */ - LCD_F_IRQn = 41 /* 57 LCD_F Interrupt */ -} IRQn_Type; - -/****************************************************************************** -* Processor and Core Peripheral Section * -******************************************************************************/ -#define __CM4_REV 0x0001 /* Core revision r0p1 */ -#define __MPU_PRESENT 1 /* MPU present or not */ -#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /* FPU present or not */ - -/****************************************************************************** -* Available Peripherals * -******************************************************************************/ -#define __MCU_HAS_ADC14__ /*!< Module ADC14 is available */ -#define __MCU_HAS_AES256__ /*!< Module AES256 is available */ -#define __MCU_HAS_CAPTIO0__ /*!< Module CAPTIO0 is available */ -#define __MCU_HAS_CAPTIO1__ /*!< Module CAPTIO1 is available */ -#define __MCU_HAS_COMP_E0__ /*!< Module COMP_E0 is available */ -#define __MCU_HAS_COMP_E1__ /*!< Module COMP_E1 is available */ -#define __MCU_HAS_CRC32__ /*!< Module CRC32 is available */ -#define __MCU_HAS_CS__ /*!< Module CS is available */ -#define __MCU_HAS_DIO__ /*!< Module DIO is available */ -#define __MCU_HAS_DMA__ /*!< Module DMA is available */ -#define __MCU_HAS_EUSCI_A0__ /*!< Module EUSCI_A0 is available */ -#define __MCU_HAS_EUSCI_A1__ /*!< Module EUSCI_A1 is available */ -#define __MCU_HAS_EUSCI_A2__ /*!< Module EUSCI_A2 is available */ -#define __MCU_HAS_EUSCI_A3__ /*!< Module EUSCI_A3 is available */ -#define __MCU_HAS_EUSCI_B0__ /*!< Module EUSCI_B0 is available */ -#define __MCU_HAS_EUSCI_B1__ /*!< Module EUSCI_B1 is available */ -#define __MCU_HAS_EUSCI_B2__ /*!< Module EUSCI_B2 is available */ -#define __MCU_HAS_EUSCI_B3__ /*!< Module EUSCI_B3 is available */ -#define __MCU_HAS_FLCTL_A__ /*!< Module FLCTL_A is available */ -#define __MCU_HAS_FL_BOOTOVER_MAILBOX__ /*!< Module FL_BOOTOVER_MAILBOX is available */ -#define __MCU_HAS_LCD_F__ /*!< Module LCD_F is available */ -#define __MCU_HAS_PCM__ /*!< Module PCM is available */ -#define __MCU_HAS_PMAP__ /*!< Module PMAP is available */ -#define __MCU_HAS_PSS__ /*!< Module PSS is available */ -#define __MCU_HAS_REF_A__ /*!< Module REF_A is available */ -#define __MCU_HAS_RSTCTL__ /*!< Module RSTCTL is available */ -#define __MCU_HAS_RTC_C__ /*!< Module RTC_C is available */ -#define __MCU_HAS_SYSCTL_A__ /*!< Module SYSCTL_A is available */ -#define __MCU_HAS_TIMER32__ /*!< Module TIMER32 is available */ -#define __MCU_HAS_TIMER_A0__ /*!< Module TIMER_A0 is available */ -#define __MCU_HAS_TIMER_A1__ /*!< Module TIMER_A1 is available */ -#define __MCU_HAS_TIMER_A2__ /*!< Module TIMER_A2 is available */ -#define __MCU_HAS_TIMER_A3__ /*!< Module TIMER_A3 is available */ -#define __MCU_HAS_TLV__ /*!< Module TLV is available */ -#define __MCU_HAS_WDT_A__ /*!< Module WDT_A is available */ - -/* Definitions to show that specific ports are available */ - -#define __MSP432_HAS_PORTA_R__ -#define __MSP432_HAS_PORTB_R__ -#define __MSP432_HAS_PORTC_R__ -#define __MSP432_HAS_PORTD_R__ -#define __MSP432_HAS_PORTE_R__ -#define __MSP432_HAS_PORTJ_R__ - -#define __MSP432_HAS_PORT1_R__ -#define __MSP432_HAS_PORT2_R__ -#define __MSP432_HAS_PORT3_R__ -#define __MSP432_HAS_PORT4_R__ -#define __MSP432_HAS_PORT5_R__ -#define __MSP432_HAS_PORT6_R__ -#define __MSP432_HAS_PORT7_R__ -#define __MSP432_HAS_PORT8_R__ -#define __MSP432_HAS_PORT9_R__ -#define __MSP432_HAS_PORT10_R__ - - -/*@}*/ /* end of group MSP432P4111_CMSIS */ - -/* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */ -#ifdef __TI_ARM__ -/* disable the TI ULP advisor check for the core header file definitions */ -#pragma diag_push -#pragma CHECK_ULP("none") -#include "core_cm4.h" -#pragma diag_pop -#else -#include "core_cm4.h" -#endif - -/* System Header */ -#include "system_msp432p4111.h" - -/****************************************************************************** -* Definition of standard bits * -******************************************************************************/ -#define BIT0 (uint16_t)(0x0001) -#define BIT1 (uint16_t)(0x0002) -#define BIT2 (uint16_t)(0x0004) -#define BIT3 (uint16_t)(0x0008) -#define BIT4 (uint16_t)(0x0010) -#define BIT5 (uint16_t)(0x0020) -#define BIT6 (uint16_t)(0x0040) -#define BIT7 (uint16_t)(0x0080) -#define BIT8 (uint16_t)(0x0100) -#define BIT9 (uint16_t)(0x0200) -#define BITA (uint16_t)(0x0400) -#define BITB (uint16_t)(0x0800) -#define BITC (uint16_t)(0x1000) -#define BITD (uint16_t)(0x2000) -#define BITE (uint16_t)(0x4000) -#define BITF (uint16_t)(0x8000) - -/****************************************************************************** -* Device and peripheral memory map * -******************************************************************************/ -/** @addtogroup MSP432P4111_MemoryMap MSP432P4111 Memory Mapping - @{ -*/ - -#define FLASH_BASE ((uint32_t)0x00000000) /*!< Main Flash memory start address */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM memory start address */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripherals start address */ -#define PERIPH_BASE2 ((uint32_t)0xE0000000) /*!< Peripherals start address */ - -#define ADC14_BASE (PERIPH_BASE +0x00012000) /*!< Base address of module ADC14 registers */ -#define AES256_BASE (PERIPH_BASE +0x00003C00) /*!< Base address of module AES256 registers */ -#define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /*!< Base address of module CAPTIO0 registers */ -#define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /*!< Base address of module CAPTIO1 registers */ -#define COMP_E0_BASE (PERIPH_BASE +0x00003400) /*!< Base address of module COMP_E0 registers */ -#define COMP_E1_BASE (PERIPH_BASE +0x00003800) /*!< Base address of module COMP_E1 registers */ -#define CRC32_BASE (PERIPH_BASE +0x00004000) /*!< Base address of module CRC32 registers */ -#define CS_BASE (PERIPH_BASE +0x00010400) /*!< Base address of module CS registers */ -#define DIO_BASE (PERIPH_BASE +0x00004C00) /*!< Base address of module DIO registers */ -#define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address of module DMA registers */ -#define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define FLCTL_A_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL_A registers */ -#define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000) /*!< Base address of module FL_BOOTOVER_MAILBOX registers */ -#define LCD_F_BASE (PERIPH_BASE +0x00012400) /*!< Base address of module LCD_F registers */ -#define PCM_BASE (PERIPH_BASE +0x00010000) /*!< Base address of module PCM registers */ -#define PMAP_BASE (PERIPH_BASE +0x00005000) /*!< Base address of module PMAP registers */ -#define PSS_BASE (PERIPH_BASE +0x00010800) /*!< Base address of module PSS registers */ -#define REF_A_BASE (PERIPH_BASE +0x00003000) /*!< Base address of module REF_A registers */ -#define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /*!< Base address of module RSTCTL registers */ -#define RTC_C_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define SYSCTL_A_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL_A registers */ -#define TIMER32_BASE (PERIPH_BASE +0x0000C000) /*!< Base address of module TIMER32 registers */ -#define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /*!< Base address of module TIMER_A0 registers */ -#define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /*!< Base address of module TIMER_A1 registers */ -#define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /*!< Base address of module TIMER_A2 registers */ -#define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /*!< Base address of module TIMER_A3 registers */ -#define TLV_BASE ((uint32_t)0x00201000) /*!< Base address of module TLV registers */ -#define WDT_A_BASE (PERIPH_BASE +0x00004800) /*!< Base address of module WDT_A registers */ - - -/*@}*/ /* end of group MSP432P4111_MemoryMap */ - -/****************************************************************************** -* Definitions for bit band access * -******************************************************************************/ -#define BITBAND_SRAM_BASE ((uint32_t)(0x22000000)) -#define BITBAND_PERI_BASE ((uint32_t)(0x42000000)) - -/* SRAM allows 32 bit bit band access */ -#define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4))) -/* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */ -#define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4))) - -/****************************************************************************** -* Peripheral register definitions * -******************************************************************************/ -/** @addtogroup MSP432P4111_Peripherals MSP432P4111 Peripherals - MSP432P4111 Device Specific Peripheral registers structures - @{ -*/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - -/****************************************************************************** -* ADC14 Registers -******************************************************************************/ -/** @addtogroup ADC14 MSP432P4111 (ADC14) - @{ -*/ -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t LO0; /*!< Window Comparator Low Threshold 0 Register */ - __IO uint32_t HI0; /*!< Window Comparator High Threshold 0 Register */ - __IO uint32_t LO1; /*!< Window Comparator Low Threshold 1 Register */ - __IO uint32_t HI1; /*!< Window Comparator High Threshold 1 Register */ - __IO uint32_t MCTL[32]; /*!< Conversion Memory Control Register */ - __IO uint32_t MEM[32]; /*!< Conversion Memory Register */ - uint32_t RESERVED0[9]; - __IO uint32_t IER0; /*!< Interrupt Enable 0 Register */ - __IO uint32_t IER1; /*!< Interrupt Enable 1 Register */ - __I uint32_t IFGR0; /*!< Interrupt Flag 0 Register */ - __I uint32_t IFGR1; /*!< Interrupt Flag 1 Register */ - __O uint32_t CLRIFGR0; /*!< Clear Interrupt Flag 0 Register */ - __IO uint32_t CLRIFGR1; /*!< Clear Interrupt Flag 1 Register */ - __IO uint32_t IV; /*!< Interrupt Vector Register */ -} ADC14_Type; - -/*@}*/ /* end of group ADC14 */ - - -/****************************************************************************** -* AES256 Registers -******************************************************************************/ -/** @addtogroup AES256 MSP432P4111 (AES256) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< AES Accelerator Control Register 0 */ - __IO uint16_t CTL1; /*!< AES Accelerator Control Register 1 */ - __IO uint16_t STAT; /*!< AES Accelerator Status Register */ - __O uint16_t KEY; /*!< AES Accelerator Key Register */ - __O uint16_t DIN; /*!< AES Accelerator Data In Register */ - __O uint16_t DOUT; /*!< AES Accelerator Data Out Register */ - __O uint16_t XDIN; /*!< AES Accelerator XORed Data In Register */ - __O uint16_t XIN; /*!< AES Accelerator XORed Data In Register */ -} AES256_Type; - -/*@}*/ /* end of group AES256 */ - - -/****************************************************************************** -* CAPTIO Registers -******************************************************************************/ -/** @addtogroup CAPTIO MSP432P4111 (CAPTIO) - @{ -*/ -typedef struct { - uint16_t RESERVED0[7]; - __IO uint16_t CTL; /*!< Capacitive Touch IO x Control Register */ -} CAPTIO_Type; - -/*@}*/ /* end of group CAPTIO */ - - -/****************************************************************************** -* COMP_E Registers -******************************************************************************/ -/** @addtogroup COMP_E MSP432P4111 (COMP_E) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< Comparator Control Register 0 */ - __IO uint16_t CTL1; /*!< Comparator Control Register 1 */ - __IO uint16_t CTL2; /*!< Comparator Control Register 2 */ - __IO uint16_t CTL3; /*!< Comparator Control Register 3 */ - uint16_t RESERVED0[2]; - __IO uint16_t INT; /*!< Comparator Interrupt Control Register */ - __I uint16_t IV; /*!< Comparator Interrupt Vector Word Register */ -} COMP_E_Type; - -/*@}*/ /* end of group COMP_E */ - - -/****************************************************************************** -* CRC32 Registers -******************************************************************************/ -/** @addtogroup CRC32 MSP432P4111 (CRC32) - @{ -*/ -typedef struct { - __IO uint16_t DI32; /*!< Data Input for CRC32 Signature Computation */ - uint16_t RESERVED0; - __IO uint16_t DIRB32; /*!< Data In Reverse for CRC32 Computation */ - uint16_t RESERVED1; - __IO uint16_t INIRES32_LO; /*!< CRC32 Initialization and Result, lower 16 bits */ - __IO uint16_t INIRES32_HI; /*!< CRC32 Initialization and Result, upper 16 bits */ - __IO uint16_t RESR32_LO; /*!< CRC32 Result Reverse, lower 16 bits */ - __IO uint16_t RESR32_HI; /*!< CRC32 Result Reverse, Upper 16 bits */ - __IO uint16_t DI16; /*!< Data Input for CRC16 computation */ - uint16_t RESERVED2; - __IO uint16_t DIRB16; /*!< CRC16 Data In Reverse */ - uint16_t RESERVED3; - __IO uint16_t INIRES16; /*!< CRC16 Initialization and Result register */ - uint16_t RESERVED4[2]; - __IO uint16_t RESR16; /*!< CRC16 Result Reverse */ -} CRC32_Type; - -/*@}*/ /* end of group CRC32 */ - - -/****************************************************************************** -* CS Registers -******************************************************************************/ -/** @addtogroup CS MSP432P4111 (CS) - @{ -*/ -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t CTL2; /*!< Control 2 Register */ - __IO uint32_t CTL3; /*!< Control 3 Register */ - uint32_t RESERVED0[7]; - __IO uint32_t CLKEN; /*!< Clock Enable Register */ - __I uint32_t STAT; /*!< Status Register */ - uint32_t RESERVED1[2]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - uint32_t RESERVED2; - __I uint32_t IFG; /*!< Interrupt Flag Register */ - uint32_t RESERVED3; - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - uint32_t RESERVED4; - __O uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - uint32_t RESERVED5; - __IO uint32_t DCOERCAL0; /*!< DCO External Resistor Cailbration 0 Register */ - __IO uint32_t DCOERCAL1; /*!< DCO External Resistor Calibration 1 Register */ -} CS_Type; - -/*@}*/ /* end of group CS */ - - -/****************************************************************************** -* DIO Registers -******************************************************************************/ -/** @addtogroup DIO MSP432P4111 (DIO) - @{ -*/ -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - __I uint16_t IV_L; /*!< Low Port Interrupt Vector Value */ - uint16_t RESERVED0[3]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; - union { - __IO uint16_t IES; /*!< Port Pair Interrupt Edge Select */ - struct { - __IO uint8_t IES_L; /*!< Low Port Interrupt Edge Select */ - __IO uint8_t IES_H; /*!< High Port Interrupt Edge Select */ - }; - }; - union { - __IO uint16_t IE; /*!< Port Pair Interrupt Enable */ - struct { - __IO uint8_t IE_L; /*!< Low Port Interrupt Enable */ - __IO uint8_t IE_H; /*!< High Port Interrupt Enable */ - }; - }; - union { - __IO uint16_t IFG; /*!< Port Pair Interrupt Flag */ - struct { - __IO uint8_t IFG_L; /*!< Low Port Interrupt Flag */ - __IO uint8_t IFG_H; /*!< High Port Interrupt Flag */ - }; - }; - __I uint16_t IV_H; /*!< High Port Interrupt Vector Value */ -} DIO_PORT_Interruptable_Type; - -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - uint16_t RESERVED0[4]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; -} DIO_PORT_Not_Interruptable_Type; - - -typedef struct { - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED0; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED1; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED2; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED3; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED4; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED5; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED6; - __I uint16_t IV; /*!< Port Interrupt Vector Value */ - uint8_t RESERVED7[6]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ -} DIO_PORT_Odd_Interruptable_Type; - -typedef struct { - uint8_t RESERVED0; - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED1; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED2; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED3; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED4; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED5; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED6; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED7[9]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ - __I uint16_t IV; /*!< Port Interrupt Vector Value */ -} DIO_PORT_Even_Interruptable_Type; - -/*@}*/ /* end of group MSP432P4111_DIO */ - - -/****************************************************************************** -* DMA Registers -******************************************************************************/ -/** @addtogroup DMA MSP432P4111 (DMA) - @{ -*/ -typedef struct { - __I uint32_t DEVICE_CFG; /*!< Device Configuration Status */ - __IO uint32_t SW_CHTRIG; /*!< Software Channel Trigger Register */ - uint32_t RESERVED0[2]; - __IO uint32_t CH_SRCCFG[32]; /*!< Channel n Source Configuration Register */ - uint32_t RESERVED1[28]; - __IO uint32_t INT1_SRCCFG; /*!< Interrupt 1 Source Channel Configuration */ - __IO uint32_t INT2_SRCCFG; /*!< Interrupt 2 Source Channel Configuration Register */ - __IO uint32_t INT3_SRCCFG; /*!< Interrupt 3 Source Channel Configuration Register */ - uint32_t RESERVED2; - __I uint32_t INT0_SRCFLG; /*!< Interrupt 0 Source Channel Flag Register */ - __O uint32_t INT0_CLRFLG; /*!< Interrupt 0 Source Channel Clear Flag Register */ -} DMA_Channel_Type; - -typedef struct { - __I uint32_t STAT; /*!< Status Register */ - __O uint32_t CFG; /*!< Configuration Register */ - __IO uint32_t CTLBASE; /*!< Channel Control Data Base Pointer Register */ - __I uint32_t ALTBASE; /*!< Channel Alternate Control Data Base Pointer Register */ - __I uint32_t WAITSTAT; /*!< Channel Wait on Request Status Register */ - __O uint32_t SWREQ; /*!< Channel Software Request Register */ - __IO uint32_t USEBURSTSET; /*!< Channel Useburst Set Register */ - __O uint32_t USEBURSTCLR; /*!< Channel Useburst Clear Register */ - __IO uint32_t REQMASKSET; /*!< Channel Request Mask Set Register */ - __O uint32_t REQMASKCLR; /*!< Channel Request Mask Clear Register */ - __IO uint32_t ENASET; /*!< Channel Enable Set Register */ - __O uint32_t ENACLR; /*!< Channel Enable Clear Register */ - __IO uint32_t ALTSET; /*!< Channel Primary-Alternate Set Register */ - __O uint32_t ALTCLR; /*!< Channel Primary-Alternate Clear Register */ - __IO uint32_t PRIOSET; /*!< Channel Priority Set Register */ - __O uint32_t PRIOCLR; /*!< Channel Priority Clear Register */ - uint32_t RESERVED4[3]; - __IO uint32_t ERRCLR; /*!< Bus Error Clear Register */ -} DMA_Control_Type; - -/*@}*/ /* end of group DMA */ - - -/****************************************************************************** -* EUSCI_A Registers -******************************************************************************/ -/** @addtogroup EUSCI_A MSP432P4111 (EUSCI_A) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Ax Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Ax Baud Rate Control Word Register */ - __IO uint16_t MCTLW; /*!< eUSCI_Ax Modulation Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Ax Status Register */ - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - __IO uint16_t ABCTL; /*!< eUSCI_Ax Auto Baud Rate Control Register */ - __IO uint16_t IRCTL; /*!< eUSCI_Ax IrDA Control Word Register */ - uint16_t RESERVED1[3]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_Type; - -/*@}*/ /* end of group EUSCI_A */ - -/** @addtogroup EUSCI_A_SPI MSP432P4111 (EUSCI_A_SPI) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Ax Bit Rate Control Register 1 */ - uint16_t RESERVED1; - __IO uint16_t STATW; - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - uint16_t RESERVED2[5]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_SPI_Type; - -/*@}*/ /* end of group EUSCI_A_SPI */ - - -/****************************************************************************** -* EUSCI_B Registers -******************************************************************************/ -/** @addtogroup EUSCI_B MSP432P4111 (EUSCI_B) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Bx Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Bx Baud Rate Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Bx Status Register */ - __IO uint16_t TBCNT; /*!< eUSCI_Bx Byte Counter Threshold Register */ - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED1[2]; - __IO uint16_t I2COA0; /*!< eUSCI_Bx I2C Own Address 0 Register */ - __IO uint16_t I2COA1; /*!< eUSCI_Bx I2C Own Address 1 Register */ - __IO uint16_t I2COA2; /*!< eUSCI_Bx I2C Own Address 2 Register */ - __IO uint16_t I2COA3; /*!< eUSCI_Bx I2C Own Address 3 Register */ - __I uint16_t ADDRX; /*!< eUSCI_Bx I2C Received Address Register */ - __IO uint16_t ADDMASK; /*!< eUSCI_Bx I2C Address Mask Register */ - __IO uint16_t I2CSA; /*!< eUSCI_Bx I2C Slave Address Register */ - uint16_t RESERVED2[4]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_Type; - -/*@}*/ /* end of group EUSCI_B */ - -/** @addtogroup EUSCI_B_SPI MSP432P4111 (EUSCI_B_SPI) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Bx Bit Rate Control Register 1 */ - __IO uint16_t STATW; - uint16_t RESERVED1; - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED2[13]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_SPI_Type; - -/*@}*/ /* end of group EUSCI_B_SPI */ - - -/****************************************************************************** -* FLCTL_A Registers -******************************************************************************/ -/** @addtogroup FLCTL_A MSP432P4111 (FLCTL_A) - @{ -*/ -typedef struct { - __I uint32_t POWER_STAT; /*!< Power Status Register */ - uint32_t RESERVED0[3]; - __IO uint32_t BANK0_RDCTL; /*!< Bank0 Read Control Register */ - __IO uint32_t BANK1_RDCTL; /*!< Bank1 Read Control Register */ - uint32_t RESERVED1[2]; - __IO uint32_t RDBRST_CTLSTAT; /*!< Read Burst/Compare Control and Status Register */ - __IO uint32_t RDBRST_STARTADDR; /*!< Read Burst/Compare Start Address Register */ - __IO uint32_t RDBRST_LEN; /*!< Read Burst/Compare Length Register */ - uint32_t RESERVED2[4]; - __IO uint32_t RDBRST_FAILADDR; /*!< Read Burst/Compare Fail Address Register */ - __IO uint32_t RDBRST_FAILCNT; /*!< Read Burst/Compare Fail Count Register */ - uint32_t RESERVED3[3]; - __IO uint32_t PRG_CTLSTAT; /*!< Program Control and Status Register */ - __IO uint32_t PRGBRST_CTLSTAT; /*!< Program Burst Control and Status Register */ - __IO uint32_t PRGBRST_STARTADDR; /*!< Program Burst Start Address Register */ - uint32_t RESERVED4; - __IO uint32_t PRGBRST_DATA0_0; /*!< Program Burst Data0 Register0 */ - __IO uint32_t PRGBRST_DATA0_1; /*!< Program Burst Data0 Register1 */ - __IO uint32_t PRGBRST_DATA0_2; /*!< Program Burst Data0 Register2 */ - __IO uint32_t PRGBRST_DATA0_3; /*!< Program Burst Data0 Register3 */ - __IO uint32_t PRGBRST_DATA1_0; /*!< Program Burst Data1 Register0 */ - __IO uint32_t PRGBRST_DATA1_1; /*!< Program Burst Data1 Register1 */ - __IO uint32_t PRGBRST_DATA1_2; /*!< Program Burst Data1 Register2 */ - __IO uint32_t PRGBRST_DATA1_3; /*!< Program Burst Data1 Register3 */ - __IO uint32_t PRGBRST_DATA2_0; /*!< Program Burst Data2 Register0 */ - __IO uint32_t PRGBRST_DATA2_1; /*!< Program Burst Data2 Register1 */ - __IO uint32_t PRGBRST_DATA2_2; /*!< Program Burst Data2 Register2 */ - __IO uint32_t PRGBRST_DATA2_3; /*!< Program Burst Data2 Register3 */ - __IO uint32_t PRGBRST_DATA3_0; /*!< Program Burst Data3 Register0 */ - __IO uint32_t PRGBRST_DATA3_1; /*!< Program Burst Data3 Register1 */ - __IO uint32_t PRGBRST_DATA3_2; /*!< Program Burst Data3 Register2 */ - __IO uint32_t PRGBRST_DATA3_3; /*!< Program Burst Data3 Register3 */ - __IO uint32_t ERASE_CTLSTAT; /*!< Erase Control and Status Register */ - __IO uint32_t ERASE_SECTADDR; /*!< Erase Sector Address Register */ - uint32_t RESERVED5[2]; - __IO uint32_t BANK0_INFO_WEPROT; /*!< Information Memory Bank0 Write/Erase Protection Register */ - __IO uint32_t BANK0_MAIN_WEPROT; /*!< Main Memory Bank0 Write/Erase Protection Register */ - uint32_t RESERVED6[2]; - __IO uint32_t BANK1_INFO_WEPROT; /*!< Information Memory Bank1 Write/Erase Protection Register */ - __IO uint32_t BANK1_MAIN_WEPROT; /*!< Main Memory Bank1 Write/Erase Protection Register */ - uint32_t RESERVED7[2]; - __IO uint32_t BMRK_CTLSTAT; /*!< Benchmark Control and Status Register */ - __IO uint32_t BMRK_IFETCH; /*!< Benchmark Instruction Fetch Count Register */ - __IO uint32_t BMRK_DREAD; /*!< Benchmark Data Read Count Register */ - __IO uint32_t BMRK_CMP; /*!< Benchmark Count Compare Register */ - uint32_t RESERVED8[4]; - __IO uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - __IO uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - __I uint32_t READ_TIMCTL; /*!< Read Timing Control Register */ - __I uint32_t READMARGIN_TIMCTL; /*!< Read Margin Timing Control Register */ - __I uint32_t PRGVER_TIMCTL; /*!< Program Verify Timing Control Register */ - __I uint32_t ERSVER_TIMCTL; /*!< Erase Verify Timing Control Register */ - __I uint32_t LKGVER_TIMCTL; /*!< Leakage Verify Timing Control Register */ - __I uint32_t PROGRAM_TIMCTL; /*!< Program Timing Control Register */ - __I uint32_t ERASE_TIMCTL; /*!< Erase Timing Control Register */ - __I uint32_t MASSERASE_TIMCTL; /*!< Mass Erase Timing Control Register */ - __I uint32_t BURSTPRG_TIMCTL; /*!< Burst Program Timing Control Register */ - uint32_t RESERVED9[55]; - __IO uint32_t BANK0_MAIN_WEPROT0; /*!< Main Memory Bank0 Write/Erase Protection Register 0 */ - __IO uint32_t BANK0_MAIN_WEPROT1; /*!< Main Memory Bank0 Write/Erase Protection Register 1 */ - __IO uint32_t BANK0_MAIN_WEPROT2; /*!< Main Memory Bank0 Write/Erase Protection Register 2 */ - __IO uint32_t BANK0_MAIN_WEPROT3; /*!< Main Memory Bank0 Write/Erase Protection Register 3 */ - __IO uint32_t BANK0_MAIN_WEPROT4; /*!< Main Memory Bank0 Write/Erase Protection Register 4 */ - __IO uint32_t BANK0_MAIN_WEPROT5; /*!< Main Memory Bank0 Write/Erase Protection Register 5 */ - __IO uint32_t BANK0_MAIN_WEPROT6; /*!< Main Memory Bank0 Write/Erase Protection Register 6 */ - __IO uint32_t BANK0_MAIN_WEPROT7; /*!< Main Memory Bank0 Write/Erase Protection Register 7 */ - uint32_t RESERVED10[8]; - __IO uint32_t BANK1_MAIN_WEPROT0; /*!< Main Memory Bank1 Write/Erase Protection Register 0 */ - __IO uint32_t BANK1_MAIN_WEPROT1; /*!< Main Memory Bank1 Write/Erase Protection Register 1 */ - __IO uint32_t BANK1_MAIN_WEPROT2; /*!< Main Memory Bank1 Write/Erase Protection Register 2 */ - __IO uint32_t BANK1_MAIN_WEPROT3; /*!< Main Memory Bank1 Write/Erase Protection Register 3 */ - __IO uint32_t BANK1_MAIN_WEPROT4; /*!< Main Memory Bank1 Write/Erase Protection Register 4 */ - __IO uint32_t BANK1_MAIN_WEPROT5; /*!< Main Memory Bank1 Write/Erase Protection Register 5 */ - __IO uint32_t BANK1_MAIN_WEPROT6; /*!< Main Memory Bank1 Write/Erase Protection Register 6 */ - __IO uint32_t BANK1_MAIN_WEPROT7; /*!< Main Memory Bank1 Write/Erase Protection Register 7 */ -} FLCTL_A_Type; - -/*@}*/ /* end of group FLCTL_A */ - - -/****************************************************************************** -* FL_BOOTOVER_MAILBOX Registers -******************************************************************************/ -/** @addtogroup SEC_ZONE_PARAMS MSP432P4111 (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t SEC_ZONE_SECEN; /*!< IP Protection Secure Zone Enable. */ - __IO uint32_t SEC_ZONE_START_ADDR; /*!< Start address of IP protected secure zone. */ - __IO uint32_t SEC_ZONE_LENGTH; /*!< Length of IP protected secure zone in number of bytes. */ - __IO uint32_t SEC_ZONE_AESINIT_VECT[4]; /*!< IP protected secure zone 0 AES initialization vector */ - __IO uint32_t SEC_ZONE_SECKEYS[8]; /*!< AES-CBC security keys. */ - __IO uint32_t SEC_ZONE_UNENC_PWD[4]; /*!< Unencrypted password for authentication. */ - __IO uint32_t SEC_ZONE_ENCUPDATE_EN; /*!< IP Protected Secure Zone Encrypted In-field Update Enable */ - __IO uint32_t SEC_ZONE_DATA_EN; /*!< IP Protected Secure Zone Data Access Enable */ - __IO uint32_t SEC_ZONE_ACK; /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */ - uint32_t RESERVED0[2]; -} SEC_ZONE_PARAMS_Type; - -/*@}*/ /* end of group SEC_ZONE_PARAMS */ - -/** @addtogroup SEC_ZONE_UPDATE MSP432P4111 (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t SEC_ZONE_PAYLOADADDR; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t SEC_ZONE_PAYLOADLEN; /*!< Length of the payload in bytes. */ - __IO uint32_t SEC_ZONE_UPDATE_ACK; /*!< Acknowledgment for the IP Protected Secure Zone Update Command */ - uint32_t RESERVED0; -} SEC_ZONE_UPDATE_Type; - -/*@}*/ /* end of group SEC_ZONE_UPDATE */ - -/** @addtogroup FL_BOOTOVER_MAILBOX MSP432P4111 (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t MB_START; /*!< Flash MailBox start: 0x0115ACF6 */ - __IO uint32_t CMD; /*!< Command for Boot override operations. */ - uint32_t RESERVED0[2]; - __IO uint32_t JTAG_SWD_LOCK_SECEN; /*!< JTAG and SWD Lock Enable */ - __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4]; /*!< JTAG and SWD lock AES initialization vector for AES-CBC */ - __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8]; /*!< JTAG and SWD lock AES CBC security Keys 0-7. */ - __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4]; /*!< JTAG and SWD lock unencrypted password */ - __IO uint32_t JTAG_SWD_LOCK_ACK; /*!< Acknowledgment for JTAG and SWD Lock command */ - uint32_t RESERVED1[2]; - SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4]; - __IO uint32_t BSL_ENABLE; /*!< BSL Enable. */ - __IO uint32_t BSL_START_ADDRESS; /*!< Contains the pointer to the BSL function. */ - __IO uint32_t BSL_PARAMETERS; /*!< BSL hardware invoke conifguration field. */ - uint32_t RESERVED2[2]; - __IO uint32_t BSL_ACK; /*!< Acknowledgment for the BSL Configuration Command */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN; /*!< Length of the encrypted payload in bytes */ - __IO uint32_t JTAG_SWD_LOCK_DST_ADDR; /*!< Destination address where the final data needs to be stored into the device. */ - __IO uint32_t ENC_UPDATE_ACK; /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */ - uint32_t RESERVED3; - SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4]; - uint32_t RESERVED4; - __IO uint32_t FACTORY_RESET_ENABLE; /*!< Enable/Disable Factory Reset */ - __IO uint32_t FACTORY_RESET_PWDEN; /*!< Factory reset password enable */ - __IO uint32_t FACTORY_RESET_PWD[4]; /*!< 128-bit Password for factory reset to be saved into the device. */ - __IO uint32_t FACTORY_RESET_PARAMS_ACK; /*!< Acknowledgment for the Factory Reset Params Command */ - uint32_t RESERVED5; - __IO uint32_t FACTORY_RESET_PASSWORD[4]; /*!< 128-bit Password for factory reset. */ - __IO uint32_t FACTORY_RESET_ACK; /*!< Acknowledgment for the Factory Reset Command */ - uint32_t RESERVED6[2]; - __IO uint32_t MB_END; /*!< Mailbox end */ -} FL_BOOTOVER_MAILBOX_Type; - -/*@}*/ /* end of group FL_BOOTOVER_MAILBOX */ - - -/****************************************************************************** -* LCD_F Registers -******************************************************************************/ -/** @addtogroup LCD_F MSP432P4111 (LCD_F) - @{ -*/ -typedef struct { - __IO uint32_t CTL; /*!< LCD_F control */ - __IO uint32_t BMCTL; /*!< LCD_F blinking and memory control */ - __IO uint32_t VCTL; /*!< LCD_F voltage control */ - __IO uint32_t PCTL0; /*!< LCD_F port control 0 */ - __IO uint32_t PCTL1; /*!< LCD_F port control 1 */ - __IO uint32_t CSSEL0; /*!< LCD_F COM/SEG select register 0 */ - __IO uint32_t CSSEL1; /*!< LCD_F COM/SEG select register 1 */ - __IO uint32_t ANMCTL; /*!< LCD_F Animation Control Register */ - uint32_t RESERVED0[60]; - __IO uint32_t IE; /*!< LCD_F interrupt enable register */ - __I uint32_t IFG; /*!< LCD_F interrupt flag register */ - __O uint32_t SETIFG; /*!< LCD_F set interrupt flag register */ - __O uint32_t CLRIFG; /*!< LCD_F clear interrupt flag register */ - __IO uint8_t M[48]; /*!< LCD memory registers */ - uint8_t RESERVED1[16]; - __IO uint8_t BM[48]; /*!< LCD Blinking memory registers */ - uint8_t RESERVED2[16]; - __IO uint8_t ANM[8]; /*!< LCD Animation memory registers */ -} LCD_F_Type; - -/*@}*/ /* end of group LCD_F */ - - -/****************************************************************************** -* PCM Registers -******************************************************************************/ -/** @addtogroup PCM MSP432P4111 (PCM) - @{ -*/ -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PCM_Type; - -/*@}*/ /* end of group PCM */ - - -/****************************************************************************** -* PMAP Registers -******************************************************************************/ -/** @addtogroup PMAP MSP432P4111 (PMAP) - @{ -*/ -typedef struct { - __IO uint16_t KEYID; /*!< Port Mapping Key Register */ - __IO uint16_t CTL; /*!< Port Mapping Control Register */ -} PMAP_COMMON_Type; - -typedef struct { - union { - __IO uint16_t PMAP_REGISTER[4]; /*!< Port Mapping Registers */ - struct { - __IO uint8_t PMAP_REGISTER0; /*!< Port Mapping Register Bit 0 */ - __IO uint8_t PMAP_REGISTER1; /*!< Port Mapping Register Bit 1 */ - __IO uint8_t PMAP_REGISTER2; /*!< Port Mapping Register Bit 2 */ - __IO uint8_t PMAP_REGISTER3; /*!< Port Mapping Register Bit 3 */ - __IO uint8_t PMAP_REGISTER4; /*!< Port Mapping Register Bit 4 */ - __IO uint8_t PMAP_REGISTER5; /*!< Port Mapping Register Bit 5 */ - __IO uint8_t PMAP_REGISTER6; /*!< Port Mapping Register Bit 6 */ - __IO uint8_t PMAP_REGISTER7; /*!< Port Mapping Register Bit 7 */ - }; - }; -} PMAP_REGISTER_Type; - -/*@}*/ /* end of group PMAP */ - - -/****************************************************************************** -* PSS Registers -******************************************************************************/ -/** @addtogroup PSS MSP432P4111 (PSS) - @{ -*/ -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - uint32_t RESERVED0[11]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PSS_Type; - -/*@}*/ /* end of group PSS */ - - -/****************************************************************************** -* REF_A Registers -******************************************************************************/ -/** @addtogroup REF_A MSP432P4111 (REF_A) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< REF Control Register 0 */ -} REF_A_Type; - -/*@}*/ /* end of group REF_A */ - - -/****************************************************************************** -* RSTCTL Registers -******************************************************************************/ -/** @addtogroup RSTCTL MSP432P4111 (RSTCTL) - @{ -*/ -typedef struct { - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __I uint32_t HARDRESET_STAT; /*!< Hard Reset Status Register */ - __IO uint32_t HARDRESET_CLR; /*!< Hard Reset Status Clear Register */ - __IO uint32_t HARDRESET_SET; /*!< Hard Reset Status Set Register */ - __I uint32_t SOFTRESET_STAT; /*!< Soft Reset Status Register */ - __IO uint32_t SOFTRESET_CLR; /*!< Soft Reset Status Clear Register */ - __IO uint32_t SOFTRESET_SET; /*!< Soft Reset Status Set Register */ - uint32_t RESERVED0[57]; - __I uint32_t PSSRESET_STAT; /*!< PSS Reset Status Register */ - __IO uint32_t PSSRESET_CLR; /*!< PSS Reset Status Clear Register */ - __I uint32_t PCMRESET_STAT; /*!< PCM Reset Status Register */ - __IO uint32_t PCMRESET_CLR; /*!< PCM Reset Status Clear Register */ - __I uint32_t PINRESET_STAT; /*!< Pin Reset Status Register */ - __IO uint32_t PINRESET_CLR; /*!< Pin Reset Status Clear Register */ - __I uint32_t REBOOTRESET_STAT; /*!< Reboot Reset Status Register */ - __IO uint32_t REBOOTRESET_CLR; /*!< Reboot Reset Status Clear Register */ - __I uint32_t CSRESET_STAT; /*!< CS Reset Status Register */ - __IO uint32_t CSRESET_CLR; /*!< CS Reset Status Clear Register */ -} RSTCTL_Type; - -/*@}*/ /* end of group RSTCTL */ - - -/****************************************************************************** -* RTC_C Registers -******************************************************************************/ -/** @addtogroup RTC_C MSP432P4111 (RTC_C) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< RTCCTL0 Register */ - __IO uint16_t CTL13; /*!< RTCCTL13 Register */ - __IO uint16_t OCAL; /*!< RTCOCAL Register */ - __IO uint16_t TCMP; /*!< RTCTCMP Register */ - __IO uint16_t PS0CTL; /*!< Real-Time Clock Prescale Timer 0 Control Register */ - __IO uint16_t PS1CTL; /*!< Real-Time Clock Prescale Timer 1 Control Register */ - __IO uint16_t PS; /*!< Real-Time Clock Prescale Timer Counter Register */ - __I uint16_t IV; /*!< Real-Time Clock Interrupt Vector Register */ - __IO uint16_t TIM0; /*!< RTCTIM0 Register Hexadecimal Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week */ - __IO uint16_t DATE; /*!< RTCDATE - Hexadecimal Format */ - __IO uint16_t YEAR; /*!< RTCYEAR Register Hexadecimal Format */ - __IO uint16_t AMINHR; /*!< RTCMINHR - Hexadecimal Format */ - __IO uint16_t ADOWDAY; /*!< RTCADOWDAY - Hexadecimal Format */ - __IO uint16_t BIN2BCD; /*!< Binary-to-BCD Conversion Register */ - __IO uint16_t BCD2BIN; /*!< BCD-to-Binary Conversion Register */ -} RTC_C_Type; - -/*@}*/ /* end of group RTC_C */ - -/** @addtogroup RTC_C_BCD MSP432P4111 (RTC_C_BCD) - @{ -*/ -typedef struct { - uint16_t RESERVED0[8]; - __IO uint16_t TIM0; /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week - BCD Format */ - __IO uint16_t DATE; /*!< Real-Time Clock Date - BCD Format */ - __IO uint16_t YEAR; /*!< Real-Time Clock Year Register - BCD Format */ - __IO uint16_t AMINHR; /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */ - __IO uint16_t ADOWDAY; /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */ -} RTC_C_BCD_Type; - -/*@}*/ /* end of group RTC_C_BCD */ - - -/****************************************************************************** -* SYSCTL_A Registers -******************************************************************************/ -/** @addtogroup SYSCTL_A MSP432P4111 (SYSCTL_A) - @{ -*/ -typedef struct { - __IO uint32_t REBOOT_CTL; /*!< Reboot Control Register */ - __IO uint32_t NMI_CTLSTAT; /*!< NMI Control and Status Register */ - __IO uint32_t WDTRESET_CTL; /*!< Watchdog Reset Control Register */ - __IO uint32_t PERIHALT_CTL; /*!< Peripheral Halt Control Register */ - __I uint32_t SRAM_SIZE; /*!< SRAM Size Register */ - __I uint32_t SRAM_NUMBANKS; /*!< SRAM Number of Banks Register */ - __I uint32_t SRAM_NUMBLOCKS; /*!< SRAM Number of Blocks Register */ - uint32_t RESERVED0; - __I uint32_t MAINFLASH_SIZE; /*!< Flash Main Memory Size Register */ - __I uint32_t INFOFLASH_SIZE; /*!< Flash Information Memory Size Register */ - uint32_t RESERVED1[2]; - __IO uint32_t DIO_GLTFLT_CTL; /*!< Digital I/O Glitch Filter Control Register */ - uint32_t RESERVED2[3]; - __IO uint32_t SECDATA_UNLOCK; /*!< IP Protected Secure Zone Data Access Unlock Register */ - uint32_t RESERVED3[3]; - __IO uint32_t SRAM_BANKEN_CTL0; /*!< SRAM Bank Enable Control Register 0 */ - __IO uint32_t SRAM_BANKEN_CTL1; /*!< SRAM Bank Enable Control Register 1 */ - __IO uint32_t SRAM_BANKEN_CTL2; /*!< SRAM Bank Enable Control Register 2 */ - __IO uint32_t SRAM_BANKEN_CTL3; /*!< SRAM Bank Enable Control Register 3 */ - uint32_t RESERVED4[4]; - __IO uint32_t SRAM_BLKRET_CTL0; /*!< SRAM Block Retention Control Register 0 */ - __IO uint32_t SRAM_BLKRET_CTL1; /*!< SRAM Block Retention Control Register 1 */ - __IO uint32_t SRAM_BLKRET_CTL2; /*!< SRAM Block Retention Control Register 2 */ - __IO uint32_t SRAM_BLKRET_CTL3; /*!< SRAM Block Retention Control Register 3 */ - uint32_t RESERVED5[4]; - __I uint32_t SRAM_STAT; /*!< SRAM Status Register */ -} SYSCTL_A_Type; - -typedef struct { - __IO uint32_t MASTER_UNLOCK; /*!< Master Unlock Register */ - __IO uint32_t BOOTOVER_REQ[2]; /*!< Boot Override Request Register */ - __IO uint32_t BOOTOVER_ACK; /*!< Boot Override Acknowledge Register */ - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __IO uint32_t RESET_STATOVER; /*!< Reset Status and Override Register */ - uint32_t RESERVED10[2]; - __I uint32_t SYSTEM_STAT; /*!< System Status Register */ -} SYSCTL_A_Boot_Type; - -/*@}*/ /* end of group SYSCTL_A */ - - -/****************************************************************************** -* Timer32 Registers -******************************************************************************/ -/** @addtogroup Timer32 MSP432P4111 (Timer32) - @{ -*/ -typedef struct { - __IO uint32_t LOAD; /*!< Timer Load Register */ - __I uint32_t VALUE; /*!< Timer Current Value Register */ - __IO uint32_t CONTROL; /*!< Timer Timer Control Register */ - __O uint32_t INTCLR; /*!< Timer Interrupt Clear Register */ - __I uint32_t RIS; /*!< Timer Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< Timer Interrupt Status Register */ - __IO uint32_t BGLOAD; /*!< Timer Background Load Register */ -} Timer32_Type; - -/*@}*/ /* end of group Timer32 */ - - -/****************************************************************************** -* Timer_A Registers -******************************************************************************/ -/** @addtogroup Timer_A MSP432P4111 (Timer_A) - @{ -*/ -typedef struct { - __IO uint16_t CTL; /*!< TimerAx Control Register */ - __IO uint16_t CCTL[5]; /*!< Timer_A Capture/Compare Control Register */ - uint16_t RESERVED0[2]; - __IO uint16_t R; /*!< TimerA register */ - __IO uint16_t CCR[5]; /*!< Timer_A Capture/Compare Register */ - uint16_t RESERVED1[2]; - __IO uint16_t EX0; /*!< TimerAx Expansion 0 Register */ - uint16_t RESERVED2[6]; - __I uint16_t IV; /*!< TimerAx Interrupt Vector Register */ -} Timer_A_Type; - -/*@}*/ /* end of group Timer_A */ - - -/****************************************************************************** -* TLV Registers -******************************************************************************/ -/** @addtogroup TLV MSP432P4111 (TLV) - @{ -*/ -typedef struct { - __I uint32_t TLV_CHECKSUM; /*!< TLV Checksum */ - __I uint32_t DEVICE_INFO_TAG; /*!< Device Info Tag */ - __I uint32_t DEVICE_INFO_LEN; /*!< Device Info Length */ - __I uint32_t DEVICE_ID; /*!< Device ID */ - __I uint32_t HWREV; /*!< HW Revision */ - __I uint32_t BCREV; /*!< Boot Code Revision */ - __I uint32_t ROM_DRVLIB_REV; /*!< ROM Driver Library Revision */ - __I uint32_t DIE_REC_TAG; /*!< Die Record Tag */ - __I uint32_t DIE_REC_LEN; /*!< Die Record Length */ - __I uint32_t DIE_XPOS; /*!< Die X-Position */ - __I uint32_t DIE_YPOS; /*!< Die Y-Position */ - __I uint32_t WAFER_ID; /*!< Wafer ID */ - __I uint32_t LOT_ID; /*!< Lot ID */ - __I uint32_t RESERVED0; /*!< Reserved */ - __I uint32_t RESERVED1; /*!< Reserved */ - __I uint32_t RESERVED2; /*!< Reserved */ - __I uint32_t TEST_RESULTS; /*!< Test Results */ - __I uint32_t CS_CAL_TAG; /*!< Clock System Calibration Tag */ - __I uint32_t CS_CAL_LEN; /*!< Clock System Calibration Length */ - __I uint32_t DCOIR_FCAL_RSEL04; /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_FCAL_RSEL5; /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED3; /*!< Reserved */ - __I uint32_t RESERVED4; /*!< Reserved */ - __I uint32_t RESERVED5; /*!< Reserved */ - __I uint32_t RESERVED6; /*!< Reserved */ - __I uint32_t DCOIR_CONSTK_RSEL04; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_CONSTK_RSEL5; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t DCOER_FCAL_RSEL04; /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOER_FCAL_RSEL5; /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED7; /*!< Reserved */ - __I uint32_t RESERVED8; /*!< Reserved */ - __I uint32_t RESERVED9; /*!< Reserved */ - __I uint32_t RESERVED10; /*!< Reserved */ - __I uint32_t DCOER_CONSTK_RSEL04; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I uint32_t DCOER_CONSTK_RSEL5; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t ADC14_CAL_TAG; /*!< ADC14 Calibration Tag */ - __I uint32_t ADC14_CAL_LEN; /*!< ADC14 Calibration Length */ - __I uint32_t ADC_GAIN_FACTOR; /*!< ADC Gain Factor */ - __I uint32_t ADC_OFFSET; /*!< ADC Offset */ - __I uint32_t RESERVED11; /*!< Reserved */ - __I uint32_t RESERVED12; /*!< Reserved */ - __I uint32_t RESERVED13; /*!< Reserved */ - __I uint32_t RESERVED14; /*!< Reserved */ - __I uint32_t RESERVED15; /*!< Reserved */ - __I uint32_t RESERVED16; /*!< Reserved */ - __I uint32_t RESERVED17; /*!< Reserved */ - __I uint32_t RESERVED18; /*!< Reserved */ - __I uint32_t RESERVED19; /*!< Reserved */ - __I uint32_t RESERVED20; /*!< Reserved */ - __I uint32_t RESERVED21; /*!< Reserved */ - __I uint32_t RESERVED22; /*!< Reserved */ - __I uint32_t RESERVED23; /*!< Reserved */ - __I uint32_t RESERVED24; /*!< Reserved */ - __I uint32_t RESERVED25; /*!< Reserved */ - __I uint32_t RESERVED26; /*!< Reserved */ - __I uint32_t ADC14_REF1P2V_TS30C; /*!< ADC14 1.2V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P2V_TS85C; /*!< ADC14 1.2V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF1P45V_TS30C; /*!< ADC14 1.45V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P45V_TS85C; /*!< ADC14 1.45V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF2P5V_TS30C; /*!< ADC14 2.5V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF2P5V_TS85C; /*!< ADC14 2.5V Reference Temp. Sensor 85C */ - __I uint32_t REF_CAL_TAG; /*!< REF Calibration Tag */ - __I uint32_t REF_CAL_LEN; /*!< REF Calibration Length */ - __I uint32_t REF_1P2V; /*!< REF 1.2V Reference */ - __I uint32_t REF_1P45V; /*!< REF 1.45V Reference */ - __I uint32_t REF_2P5V; /*!< REF 2.5V Reference */ - __I uint32_t FLASH_INFO_TAG; /*!< Flash Info Tag */ - __I uint32_t FLASH_INFO_LEN; /*!< Flash Info Length */ - __I uint32_t FLASH_MAX_PROG_PULSES; /*!< Flash Maximum Programming Pulses */ - __I uint32_t FLASH_MAX_ERASE_PULSES; /*!< Flash Maximum Erase Pulses */ - __I uint32_t RANDOM_NUM_TAG; /*!< 128-bit Random Number Tag */ - __I uint32_t RANDOM_NUM_LEN; /*!< 128-bit Random Number Length */ - __I uint32_t RANDOM_NUM_1; /*!< 32-bit Random Number 1 */ - __I uint32_t RANDOM_NUM_2; /*!< 32-bit Random Number 2 */ - __I uint32_t RANDOM_NUM_3; /*!< 32-bit Random Number 3 */ - __I uint32_t RANDOM_NUM_4; /*!< 32-bit Random Number 4 */ - __I uint32_t BSL_CFG_TAG; /*!< BSL Configuration Tag */ - __I uint32_t BSL_CFG_LEN; /*!< BSL Configuration Length */ - __I uint32_t BSL_PERIPHIF_SEL; /*!< BSL Peripheral Interface Selection */ - __I uint32_t BSL_PORTIF_CFG_UART; /*!< BSL Port Interface Configuration for UART */ - __I uint32_t BSL_PORTIF_CFG_SPI; /*!< BSL Port Interface Configuration for SPI */ - __I uint32_t BSL_PORTIF_CFG_I2C; /*!< BSL Port Interface Configuration for I2C */ - __I uint32_t TLV_END; /*!< TLV End Word */ -} TLV_Type; - -/*@}*/ /* end of group TLV */ - - -/****************************************************************************** -* WDT_A Registers -******************************************************************************/ -/** @addtogroup WDT_A MSP432P4111 (WDT_A) - @{ -*/ -typedef struct { - uint16_t RESERVED0[6]; - __IO uint16_t CTL; /*!< Watchdog Timer Control Register */ -} WDT_A_Type; - -/*@}*/ /* end of group WDT_A */ - - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/*@}*/ /* end of group MSP432P4111_Peripherals */ - -/****************************************************************************** -* Peripheral declaration * -******************************************************************************/ -/** @addtogroup MSP432P4111_PeripheralDecl MSP432P4111 Peripheral Declaration - @{ -*/ - -#define ADC14 ((ADC14_Type *) ADC14_BASE) -#define AES256 ((AES256_Type *) AES256_BASE) -#define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE) -#define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE) -#define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE) -#define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE) -#define CRC32 ((CRC32_Type *) CRC32_BASE) -#define CS ((CS_Type *) CS_BASE) -#define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120)) -#define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define DMA_Channel ((DMA_Channel_Type *) DMA_BASE) -#define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000)) -#define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE) -#define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE) -#define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE) -#define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE) -#define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE) -#define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE) -#define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE) -#define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE) -#define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE) -#define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE) -#define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE) -#define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE) -#define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE) -#define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE) -#define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE) -#define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE) -#define FLCTL_A ((FLCTL_A_Type *) FLCTL_A_BASE) -#define FL_BOOTOVER_MAILBOX ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE) -#define LCD_F ((LCD_F_Type *) LCD_F_BASE) -#define PCM ((PCM_Type *) PCM_BASE) -#define PMAP ((PMAP_COMMON_Type*) PMAP_BASE) -#define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008)) -#define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010)) -#define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018)) -#define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020)) -#define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028)) -#define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030)) -#define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038)) -#define PSS ((PSS_Type *) PSS_BASE) -#define REF_A ((REF_A_Type *) REF_A_BASE) -#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) -#define RTC_C ((RTC_C_Type *) RTC_C_BASE) -#define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE) -#define SYSCTL_A ((SYSCTL_A_Type *) SYSCTL_A_BASE) -#define SYSCTL_A_Boot ((SYSCTL_A_Boot_Type *) (SYSCTL_A_BASE + 0x1000)) -#define TIMER32_1 ((Timer32_Type *) TIMER32_BASE) -#define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020)) -#define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE) -#define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE) -#define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE) -#define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE) -#define TLV ((TLV_Type *) TLV_BASE) -#define WDT_A ((WDT_A_Type *) WDT_A_BASE) - - -/*@}*/ /* end of group MSP432P4111_PeripheralDecl */ - -/*@}*/ /* end of group MSP432P4111_Definitions */ - -#endif /* __CMSIS_CONFIG__ */ - -/****************************************************************************** -* Peripheral register control bits * -******************************************************************************/ - -/****************************************************************************** -* ADC14 Bits -******************************************************************************/ -/* ADC14_CTL0[SC] Bits */ -#define ADC14_CTL0_SC_OFS ( 0) /*!< ADC14SC Bit Offset */ -#define ADC14_CTL0_SC ((uint32_t)0x00000001) /*!< ADC14 start conversion */ -/* ADC14_CTL0[ENC] Bits */ -#define ADC14_CTL0_ENC_OFS ( 1) /*!< ADC14ENC Bit Offset */ -#define ADC14_CTL0_ENC ((uint32_t)0x00000002) /*!< ADC14 enable conversion */ -/* ADC14_CTL0[ON] Bits */ -#define ADC14_CTL0_ON_OFS ( 4) /*!< ADC14ON Bit Offset */ -#define ADC14_CTL0_ON ((uint32_t)0x00000010) /*!< ADC14 on */ -/* ADC14_CTL0[MSC] Bits */ -#define ADC14_CTL0_MSC_OFS ( 7) /*!< ADC14MSC Bit Offset */ -#define ADC14_CTL0_MSC ((uint32_t)0x00000080) /*!< ADC14 multiple sample and conversion */ -/* ADC14_CTL0[SHT0] Bits */ -#define ADC14_CTL0_SHT0_OFS ( 8) /*!< ADC14SHT0 Bit Offset */ -#define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /*!< ADC14SHT0 Bit Mask */ -#define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /*!< SHT0 Bit 0 */ -#define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /*!< SHT0 Bit 1 */ -#define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /*!< SHT0 Bit 2 */ -#define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /*!< SHT0 Bit 3 */ -#define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /*!< 192 */ -#define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /*!< 192 */ -/* ADC14_CTL0[SHT1] Bits */ -#define ADC14_CTL0_SHT1_OFS (12) /*!< ADC14SHT1 Bit Offset */ -#define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /*!< ADC14SHT1 Bit Mask */ -#define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /*!< SHT1 Bit 0 */ -#define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /*!< SHT1 Bit 1 */ -#define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /*!< SHT1 Bit 2 */ -#define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /*!< SHT1 Bit 3 */ -#define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /*!< 192 */ -#define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /*!< 192 */ -/* ADC14_CTL0[BUSY] Bits */ -#define ADC14_CTL0_BUSY_OFS (16) /*!< ADC14BUSY Bit Offset */ -#define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /*!< ADC14 busy */ -/* ADC14_CTL0[CONSEQ] Bits */ -#define ADC14_CTL0_CONSEQ_OFS (17) /*!< ADC14CONSEQ Bit Offset */ -#define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /*!< ADC14CONSEQ Bit Mask */ -#define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /*!< CONSEQ Bit 0 */ -#define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /*!< CONSEQ Bit 1 */ -#define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /*!< Single-channel, single-conversion */ -#define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /*!< Sequence-of-channels */ -#define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /*!< Repeat-single-channel */ -#define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /*!< Repeat-sequence-of-channels */ -/* ADC14_CTL0[SSEL] Bits */ -#define ADC14_CTL0_SSEL_OFS (19) /*!< ADC14SSEL Bit Offset */ -#define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /*!< ADC14SSEL Bit Mask */ -#define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /*!< SSEL Bit 0 */ -#define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /*!< SSEL Bit 1 */ -#define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /*!< SSEL Bit 2 */ -#define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /*!< HSMCLK */ -#define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /*!< HSMCLK */ -/* ADC14_CTL0[DIV] Bits */ -#define ADC14_CTL0_DIV_OFS (22) /*!< ADC14DIV Bit Offset */ -#define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /*!< ADC14DIV Bit Mask */ -#define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /*!< DIV Bit 0 */ -#define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /*!< DIV Bit 1 */ -#define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /*!< DIV Bit 2 */ -#define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /*!< /8 */ -#define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /*!< /8 */ -/* ADC14_CTL0[ISSH] Bits */ -#define ADC14_CTL0_ISSH_OFS (25) /*!< ADC14ISSH Bit Offset */ -#define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /*!< ADC14 invert signal sample-and-hold */ -/* ADC14_CTL0[SHP] Bits */ -#define ADC14_CTL0_SHP_OFS (26) /*!< ADC14SHP Bit Offset */ -#define ADC14_CTL0_SHP ((uint32_t)0x04000000) /*!< ADC14 sample-and-hold pulse-mode select */ -/* ADC14_CTL0[SHS] Bits */ -#define ADC14_CTL0_SHS_OFS (27) /*!< ADC14SHS Bit Offset */ -#define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /*!< ADC14SHS Bit Mask */ -#define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /*!< SHS Bit 0 */ -#define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /*!< SHS Bit 1 */ -#define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /*!< SHS Bit 2 */ -#define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /*!< ADC14SC bit */ -#define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /*!< See device-specific data sheet for source */ -/* ADC14_CTL0[PDIV] Bits */ -#define ADC14_CTL0_PDIV_OFS (30) /*!< ADC14PDIV Bit Offset */ -#define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /*!< ADC14PDIV Bit Mask */ -#define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /*!< PDIV Bit 0 */ -#define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /*!< PDIV Bit 1 */ -#define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -#define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -/* ADC14_CTL1[PWRMD] Bits */ -#define ADC14_CTL1_PWRMD_OFS ( 0) /*!< ADC14PWRMD Bit Offset */ -#define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /*!< ADC14PWRMD Bit Mask */ -#define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /*!< PWRMD Bit 0 */ -#define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /*!< PWRMD Bit 1 */ -#define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /*!< Regular power mode for use with any resolution setting. Sample rate can be */ - /* up to 1 Msps. */ -#define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample */ - /* rate must not exceed 200 ksps. */ -/* ADC14_CTL1[REFBURST] Bits */ -#define ADC14_CTL1_REFBURST_OFS ( 2) /*!< ADC14REFBURST Bit Offset */ -#define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /*!< ADC14 reference buffer burst */ -/* ADC14_CTL1[DF] Bits */ -#define ADC14_CTL1_DF_OFS ( 3) /*!< ADC14DF Bit Offset */ -#define ADC14_CTL1_DF ((uint32_t)0x00000008) /*!< ADC14 data read-back format */ -/* ADC14_CTL1[RES] Bits */ -#define ADC14_CTL1_RES_OFS ( 4) /*!< ADC14RES Bit Offset */ -#define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /*!< ADC14RES Bit Mask */ -#define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /*!< RES Bit 0 */ -#define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /*!< RES Bit 1 */ -#define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -#define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -/* ADC14_CTL1[CSTARTADD] Bits */ -#define ADC14_CTL1_CSTARTADD_OFS (16) /*!< ADC14CSTARTADD Bit Offset */ -#define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /*!< ADC14CSTARTADD Bit Mask */ -/* ADC14_CTL1[BATMAP] Bits */ -#define ADC14_CTL1_BATMAP_OFS (22) /*!< ADC14BATMAP Bit Offset */ -#define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /*!< Controls 1/2 AVCC ADC input channel selection */ -/* ADC14_CTL1[TCMAP] Bits */ -#define ADC14_CTL1_TCMAP_OFS (23) /*!< ADC14TCMAP Bit Offset */ -#define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /*!< Controls temperature sensor ADC input channel selection */ -/* ADC14_CTL1[CH0MAP] Bits */ -#define ADC14_CTL1_CH0MAP_OFS (24) /*!< ADC14CH0MAP Bit Offset */ -#define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */ -/* ADC14_CTL1[CH1MAP] Bits */ -#define ADC14_CTL1_CH1MAP_OFS (25) /*!< ADC14CH1MAP Bit Offset */ -#define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */ -/* ADC14_CTL1[CH2MAP] Bits */ -#define ADC14_CTL1_CH2MAP_OFS (26) /*!< ADC14CH2MAP Bit Offset */ -#define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */ -/* ADC14_CTL1[CH3MAP] Bits */ -#define ADC14_CTL1_CH3MAP_OFS (27) /*!< ADC14CH3MAP Bit Offset */ -#define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */ -/* ADC14_LO0[LO0] Bits */ -#define ADC14_LO0_LO0_OFS ( 0) /*!< ADC14LO0 Bit Offset */ -#define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO0 Bit Mask */ -/* ADC14_HI0[HI0] Bits */ -#define ADC14_HI0_HI0_OFS ( 0) /*!< ADC14HI0 Bit Offset */ -#define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI0 Bit Mask */ -/* ADC14_LO1[LO1] Bits */ -#define ADC14_LO1_LO1_OFS ( 0) /*!< ADC14LO1 Bit Offset */ -#define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO1 Bit Mask */ -/* ADC14_HI1[HI1] Bits */ -#define ADC14_HI1_HI1_OFS ( 0) /*!< ADC14HI1 Bit Offset */ -#define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI1 Bit Mask */ -/* ADC14_MCTLN[INCH] Bits */ -#define ADC14_MCTLN_INCH_OFS ( 0) /*!< ADC14INCH Bit Offset */ -#define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /*!< ADC14INCH Bit Mask */ -#define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /*!< INCH Bit 0 */ -#define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /*!< INCH Bit 1 */ -#define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /*!< INCH Bit 2 */ -#define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /*!< INCH Bit 3 */ -#define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /*!< INCH Bit 4 */ -#define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -#define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -/* ADC14_MCTLN[EOS] Bits */ -#define ADC14_MCTLN_EOS_OFS ( 7) /*!< ADC14EOS Bit Offset */ -#define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /*!< End of sequence */ -/* ADC14_MCTLN[VRSEL] Bits */ -#define ADC14_MCTLN_VRSEL_OFS ( 8) /*!< ADC14VRSEL Bit Offset */ -#define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /*!< ADC14VRSEL Bit Mask */ -#define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /*!< VRSEL Bit 0 */ -#define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /*!< VRSEL Bit 1 */ -#define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /*!< VRSEL Bit 2 */ -#define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /*!< VRSEL Bit 3 */ -#define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /*!< V(R+) = AVCC, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /*!< V(R+) = VREF buffered, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /*!< V(R+) = VeREF+, V(R-) = VeREF- */ -#define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */ -/* ADC14_MCTLN[DIF] Bits */ -#define ADC14_MCTLN_DIF_OFS (13) /*!< ADC14DIF Bit Offset */ -#define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /*!< Differential mode */ -/* ADC14_MCTLN[WINC] Bits */ -#define ADC14_MCTLN_WINC_OFS (14) /*!< ADC14WINC Bit Offset */ -#define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /*!< Comparator window enable */ -/* ADC14_MCTLN[WINCTH] Bits */ -#define ADC14_MCTLN_WINCTH_OFS (15) /*!< ADC14WINCTH Bit Offset */ -#define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /*!< Window comparator threshold register selection */ -/* ADC14_MEMN[CONVRES] Bits */ -#define ADC14_MEMN_CONVRES_OFS ( 0) /*!< Conversion_Results Bit Offset */ -#define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /*!< Conversion_Results Bit Mask */ -/* ADC14_IER0[IE0] Bits */ -#define ADC14_IER0_IE0_OFS ( 0) /*!< ADC14IE0 Bit Offset */ -#define ADC14_IER0_IE0 ((uint32_t)0x00000001) /*!< Interrupt enable */ -/* ADC14_IER0[IE1] Bits */ -#define ADC14_IER0_IE1_OFS ( 1) /*!< ADC14IE1 Bit Offset */ -#define ADC14_IER0_IE1 ((uint32_t)0x00000002) /*!< Interrupt enable */ -/* ADC14_IER0[IE2] Bits */ -#define ADC14_IER0_IE2_OFS ( 2) /*!< ADC14IE2 Bit Offset */ -#define ADC14_IER0_IE2 ((uint32_t)0x00000004) /*!< Interrupt enable */ -/* ADC14_IER0[IE3] Bits */ -#define ADC14_IER0_IE3_OFS ( 3) /*!< ADC14IE3 Bit Offset */ -#define ADC14_IER0_IE3 ((uint32_t)0x00000008) /*!< Interrupt enable */ -/* ADC14_IER0[IE4] Bits */ -#define ADC14_IER0_IE4_OFS ( 4) /*!< ADC14IE4 Bit Offset */ -#define ADC14_IER0_IE4 ((uint32_t)0x00000010) /*!< Interrupt enable */ -/* ADC14_IER0[IE5] Bits */ -#define ADC14_IER0_IE5_OFS ( 5) /*!< ADC14IE5 Bit Offset */ -#define ADC14_IER0_IE5 ((uint32_t)0x00000020) /*!< Interrupt enable */ -/* ADC14_IER0[IE6] Bits */ -#define ADC14_IER0_IE6_OFS ( 6) /*!< ADC14IE6 Bit Offset */ -#define ADC14_IER0_IE6 ((uint32_t)0x00000040) /*!< Interrupt enable */ -/* ADC14_IER0[IE7] Bits */ -#define ADC14_IER0_IE7_OFS ( 7) /*!< ADC14IE7 Bit Offset */ -#define ADC14_IER0_IE7 ((uint32_t)0x00000080) /*!< Interrupt enable */ -/* ADC14_IER0[IE8] Bits */ -#define ADC14_IER0_IE8_OFS ( 8) /*!< ADC14IE8 Bit Offset */ -#define ADC14_IER0_IE8 ((uint32_t)0x00000100) /*!< Interrupt enable */ -/* ADC14_IER0[IE9] Bits */ -#define ADC14_IER0_IE9_OFS ( 9) /*!< ADC14IE9 Bit Offset */ -#define ADC14_IER0_IE9 ((uint32_t)0x00000200) /*!< Interrupt enable */ -/* ADC14_IER0[IE10] Bits */ -#define ADC14_IER0_IE10_OFS (10) /*!< ADC14IE10 Bit Offset */ -#define ADC14_IER0_IE10 ((uint32_t)0x00000400) /*!< Interrupt enable */ -/* ADC14_IER0[IE11] Bits */ -#define ADC14_IER0_IE11_OFS (11) /*!< ADC14IE11 Bit Offset */ -#define ADC14_IER0_IE11 ((uint32_t)0x00000800) /*!< Interrupt enable */ -/* ADC14_IER0[IE12] Bits */ -#define ADC14_IER0_IE12_OFS (12) /*!< ADC14IE12 Bit Offset */ -#define ADC14_IER0_IE12 ((uint32_t)0x00001000) /*!< Interrupt enable */ -/* ADC14_IER0[IE13] Bits */ -#define ADC14_IER0_IE13_OFS (13) /*!< ADC14IE13 Bit Offset */ -#define ADC14_IER0_IE13 ((uint32_t)0x00002000) /*!< Interrupt enable */ -/* ADC14_IER0[IE14] Bits */ -#define ADC14_IER0_IE14_OFS (14) /*!< ADC14IE14 Bit Offset */ -#define ADC14_IER0_IE14 ((uint32_t)0x00004000) /*!< Interrupt enable */ -/* ADC14_IER0[IE15] Bits */ -#define ADC14_IER0_IE15_OFS (15) /*!< ADC14IE15 Bit Offset */ -#define ADC14_IER0_IE15 ((uint32_t)0x00008000) /*!< Interrupt enable */ -/* ADC14_IER0[IE16] Bits */ -#define ADC14_IER0_IE16_OFS (16) /*!< ADC14IE16 Bit Offset */ -#define ADC14_IER0_IE16 ((uint32_t)0x00010000) /*!< Interrupt enable */ -/* ADC14_IER0[IE17] Bits */ -#define ADC14_IER0_IE17_OFS (17) /*!< ADC14IE17 Bit Offset */ -#define ADC14_IER0_IE17 ((uint32_t)0x00020000) /*!< Interrupt enable */ -/* ADC14_IER0[IE19] Bits */ -#define ADC14_IER0_IE19_OFS (19) /*!< ADC14IE19 Bit Offset */ -#define ADC14_IER0_IE19 ((uint32_t)0x00080000) /*!< Interrupt enable */ -/* ADC14_IER0[IE18] Bits */ -#define ADC14_IER0_IE18_OFS (18) /*!< ADC14IE18 Bit Offset */ -#define ADC14_IER0_IE18 ((uint32_t)0x00040000) /*!< Interrupt enable */ -/* ADC14_IER0[IE20] Bits */ -#define ADC14_IER0_IE20_OFS (20) /*!< ADC14IE20 Bit Offset */ -#define ADC14_IER0_IE20 ((uint32_t)0x00100000) /*!< Interrupt enable */ -/* ADC14_IER0[IE21] Bits */ -#define ADC14_IER0_IE21_OFS (21) /*!< ADC14IE21 Bit Offset */ -#define ADC14_IER0_IE21 ((uint32_t)0x00200000) /*!< Interrupt enable */ -/* ADC14_IER0[IE22] Bits */ -#define ADC14_IER0_IE22_OFS (22) /*!< ADC14IE22 Bit Offset */ -#define ADC14_IER0_IE22 ((uint32_t)0x00400000) /*!< Interrupt enable */ -/* ADC14_IER0[IE23] Bits */ -#define ADC14_IER0_IE23_OFS (23) /*!< ADC14IE23 Bit Offset */ -#define ADC14_IER0_IE23 ((uint32_t)0x00800000) /*!< Interrupt enable */ -/* ADC14_IER0[IE24] Bits */ -#define ADC14_IER0_IE24_OFS (24) /*!< ADC14IE24 Bit Offset */ -#define ADC14_IER0_IE24 ((uint32_t)0x01000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE25] Bits */ -#define ADC14_IER0_IE25_OFS (25) /*!< ADC14IE25 Bit Offset */ -#define ADC14_IER0_IE25 ((uint32_t)0x02000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE26] Bits */ -#define ADC14_IER0_IE26_OFS (26) /*!< ADC14IE26 Bit Offset */ -#define ADC14_IER0_IE26 ((uint32_t)0x04000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE27] Bits */ -#define ADC14_IER0_IE27_OFS (27) /*!< ADC14IE27 Bit Offset */ -#define ADC14_IER0_IE27 ((uint32_t)0x08000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE28] Bits */ -#define ADC14_IER0_IE28_OFS (28) /*!< ADC14IE28 Bit Offset */ -#define ADC14_IER0_IE28 ((uint32_t)0x10000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE29] Bits */ -#define ADC14_IER0_IE29_OFS (29) /*!< ADC14IE29 Bit Offset */ -#define ADC14_IER0_IE29 ((uint32_t)0x20000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE30] Bits */ -#define ADC14_IER0_IE30_OFS (30) /*!< ADC14IE30 Bit Offset */ -#define ADC14_IER0_IE30 ((uint32_t)0x40000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE31] Bits */ -#define ADC14_IER0_IE31_OFS (31) /*!< ADC14IE31 Bit Offset */ -#define ADC14_IER0_IE31 ((uint32_t)0x80000000) /*!< Interrupt enable */ -/* ADC14_IER1[INIE] Bits */ -#define ADC14_IER1_INIE_OFS ( 1) /*!< ADC14INIE Bit Offset */ -#define ADC14_IER1_INIE ((uint32_t)0x00000002) /*!< Interrupt enable for ADC14MEMx within comparator window */ -/* ADC14_IER1[LOIE] Bits */ -#define ADC14_IER1_LOIE_OFS ( 2) /*!< ADC14LOIE Bit Offset */ -#define ADC14_IER1_LOIE ((uint32_t)0x00000004) /*!< Interrupt enable for ADC14MEMx below comparator window */ -/* ADC14_IER1[HIIE] Bits */ -#define ADC14_IER1_HIIE_OFS ( 3) /*!< ADC14HIIE Bit Offset */ -#define ADC14_IER1_HIIE ((uint32_t)0x00000008) /*!< Interrupt enable for ADC14MEMx above comparator window */ -/* ADC14_IER1[OVIE] Bits */ -#define ADC14_IER1_OVIE_OFS ( 4) /*!< ADC14OVIE Bit Offset */ -#define ADC14_IER1_OVIE ((uint32_t)0x00000010) /*!< ADC14MEMx overflow-interrupt enable */ -/* ADC14_IER1[TOVIE] Bits */ -#define ADC14_IER1_TOVIE_OFS ( 5) /*!< ADC14TOVIE Bit Offset */ -#define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /*!< ADC14 conversion-time-overflow interrupt enable */ -/* ADC14_IER1[RDYIE] Bits */ -#define ADC14_IER1_RDYIE_OFS ( 6) /*!< ADC14RDYIE Bit Offset */ -#define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt enable */ -/* ADC14_IFGR0[IFG0] Bits */ -#define ADC14_IFGR0_IFG0_OFS ( 0) /*!< ADC14IFG0 Bit Offset */ -#define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /*!< ADC14MEM0 interrupt flag */ -/* ADC14_IFGR0[IFG1] Bits */ -#define ADC14_IFGR0_IFG1_OFS ( 1) /*!< ADC14IFG1 Bit Offset */ -#define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /*!< ADC14MEM1 interrupt flag */ -/* ADC14_IFGR0[IFG2] Bits */ -#define ADC14_IFGR0_IFG2_OFS ( 2) /*!< ADC14IFG2 Bit Offset */ -#define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /*!< ADC14MEM2 interrupt flag */ -/* ADC14_IFGR0[IFG3] Bits */ -#define ADC14_IFGR0_IFG3_OFS ( 3) /*!< ADC14IFG3 Bit Offset */ -#define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /*!< ADC14MEM3 interrupt flag */ -/* ADC14_IFGR0[IFG4] Bits */ -#define ADC14_IFGR0_IFG4_OFS ( 4) /*!< ADC14IFG4 Bit Offset */ -#define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /*!< ADC14MEM4 interrupt flag */ -/* ADC14_IFGR0[IFG5] Bits */ -#define ADC14_IFGR0_IFG5_OFS ( 5) /*!< ADC14IFG5 Bit Offset */ -#define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /*!< ADC14MEM5 interrupt flag */ -/* ADC14_IFGR0[IFG6] Bits */ -#define ADC14_IFGR0_IFG6_OFS ( 6) /*!< ADC14IFG6 Bit Offset */ -#define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /*!< ADC14MEM6 interrupt flag */ -/* ADC14_IFGR0[IFG7] Bits */ -#define ADC14_IFGR0_IFG7_OFS ( 7) /*!< ADC14IFG7 Bit Offset */ -#define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /*!< ADC14MEM7 interrupt flag */ -/* ADC14_IFGR0[IFG8] Bits */ -#define ADC14_IFGR0_IFG8_OFS ( 8) /*!< ADC14IFG8 Bit Offset */ -#define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /*!< ADC14MEM8 interrupt flag */ -/* ADC14_IFGR0[IFG9] Bits */ -#define ADC14_IFGR0_IFG9_OFS ( 9) /*!< ADC14IFG9 Bit Offset */ -#define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /*!< ADC14MEM9 interrupt flag */ -/* ADC14_IFGR0[IFG10] Bits */ -#define ADC14_IFGR0_IFG10_OFS (10) /*!< ADC14IFG10 Bit Offset */ -#define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /*!< ADC14MEM10 interrupt flag */ -/* ADC14_IFGR0[IFG11] Bits */ -#define ADC14_IFGR0_IFG11_OFS (11) /*!< ADC14IFG11 Bit Offset */ -#define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /*!< ADC14MEM11 interrupt flag */ -/* ADC14_IFGR0[IFG12] Bits */ -#define ADC14_IFGR0_IFG12_OFS (12) /*!< ADC14IFG12 Bit Offset */ -#define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /*!< ADC14MEM12 interrupt flag */ -/* ADC14_IFGR0[IFG13] Bits */ -#define ADC14_IFGR0_IFG13_OFS (13) /*!< ADC14IFG13 Bit Offset */ -#define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /*!< ADC14MEM13 interrupt flag */ -/* ADC14_IFGR0[IFG14] Bits */ -#define ADC14_IFGR0_IFG14_OFS (14) /*!< ADC14IFG14 Bit Offset */ -#define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /*!< ADC14MEM14 interrupt flag */ -/* ADC14_IFGR0[IFG15] Bits */ -#define ADC14_IFGR0_IFG15_OFS (15) /*!< ADC14IFG15 Bit Offset */ -#define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /*!< ADC14MEM15 interrupt flag */ -/* ADC14_IFGR0[IFG16] Bits */ -#define ADC14_IFGR0_IFG16_OFS (16) /*!< ADC14IFG16 Bit Offset */ -#define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /*!< ADC14MEM16 interrupt flag */ -/* ADC14_IFGR0[IFG17] Bits */ -#define ADC14_IFGR0_IFG17_OFS (17) /*!< ADC14IFG17 Bit Offset */ -#define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /*!< ADC14MEM17 interrupt flag */ -/* ADC14_IFGR0[IFG18] Bits */ -#define ADC14_IFGR0_IFG18_OFS (18) /*!< ADC14IFG18 Bit Offset */ -#define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /*!< ADC14MEM18 interrupt flag */ -/* ADC14_IFGR0[IFG19] Bits */ -#define ADC14_IFGR0_IFG19_OFS (19) /*!< ADC14IFG19 Bit Offset */ -#define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /*!< ADC14MEM19 interrupt flag */ -/* ADC14_IFGR0[IFG20] Bits */ -#define ADC14_IFGR0_IFG20_OFS (20) /*!< ADC14IFG20 Bit Offset */ -#define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /*!< ADC14MEM20 interrupt flag */ -/* ADC14_IFGR0[IFG21] Bits */ -#define ADC14_IFGR0_IFG21_OFS (21) /*!< ADC14IFG21 Bit Offset */ -#define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /*!< ADC14MEM21 interrupt flag */ -/* ADC14_IFGR0[IFG22] Bits */ -#define ADC14_IFGR0_IFG22_OFS (22) /*!< ADC14IFG22 Bit Offset */ -#define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /*!< ADC14MEM22 interrupt flag */ -/* ADC14_IFGR0[IFG23] Bits */ -#define ADC14_IFGR0_IFG23_OFS (23) /*!< ADC14IFG23 Bit Offset */ -#define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /*!< ADC14MEM23 interrupt flag */ -/* ADC14_IFGR0[IFG24] Bits */ -#define ADC14_IFGR0_IFG24_OFS (24) /*!< ADC14IFG24 Bit Offset */ -#define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /*!< ADC14MEM24 interrupt flag */ -/* ADC14_IFGR0[IFG25] Bits */ -#define ADC14_IFGR0_IFG25_OFS (25) /*!< ADC14IFG25 Bit Offset */ -#define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /*!< ADC14MEM25 interrupt flag */ -/* ADC14_IFGR0[IFG26] Bits */ -#define ADC14_IFGR0_IFG26_OFS (26) /*!< ADC14IFG26 Bit Offset */ -#define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /*!< ADC14MEM26 interrupt flag */ -/* ADC14_IFGR0[IFG27] Bits */ -#define ADC14_IFGR0_IFG27_OFS (27) /*!< ADC14IFG27 Bit Offset */ -#define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /*!< ADC14MEM27 interrupt flag */ -/* ADC14_IFGR0[IFG28] Bits */ -#define ADC14_IFGR0_IFG28_OFS (28) /*!< ADC14IFG28 Bit Offset */ -#define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /*!< ADC14MEM28 interrupt flag */ -/* ADC14_IFGR0[IFG29] Bits */ -#define ADC14_IFGR0_IFG29_OFS (29) /*!< ADC14IFG29 Bit Offset */ -#define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /*!< ADC14MEM29 interrupt flag */ -/* ADC14_IFGR0[IFG30] Bits */ -#define ADC14_IFGR0_IFG30_OFS (30) /*!< ADC14IFG30 Bit Offset */ -#define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /*!< ADC14MEM30 interrupt flag */ -/* ADC14_IFGR0[IFG31] Bits */ -#define ADC14_IFGR0_IFG31_OFS (31) /*!< ADC14IFG31 Bit Offset */ -#define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /*!< ADC14MEM31 interrupt flag */ -/* ADC14_IFGR1[INIFG] Bits */ -#define ADC14_IFGR1_INIFG_OFS ( 1) /*!< ADC14INIFG Bit Offset */ -#define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /*!< Interrupt flag for ADC14MEMx within comparator window */ -/* ADC14_IFGR1[LOIFG] Bits */ -#define ADC14_IFGR1_LOIFG_OFS ( 2) /*!< ADC14LOIFG Bit Offset */ -#define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /*!< Interrupt flag for ADC14MEMx below comparator window */ -/* ADC14_IFGR1[HIIFG] Bits */ -#define ADC14_IFGR1_HIIFG_OFS ( 3) /*!< ADC14HIIFG Bit Offset */ -#define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /*!< Interrupt flag for ADC14MEMx above comparator window */ -/* ADC14_IFGR1[OVIFG] Bits */ -#define ADC14_IFGR1_OVIFG_OFS ( 4) /*!< ADC14OVIFG Bit Offset */ -#define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /*!< ADC14MEMx overflow interrupt flag */ -/* ADC14_IFGR1[TOVIFG] Bits */ -#define ADC14_IFGR1_TOVIFG_OFS ( 5) /*!< ADC14TOVIFG Bit Offset */ -#define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /*!< ADC14 conversion time overflow interrupt flag */ -/* ADC14_IFGR1[RDYIFG] Bits */ -#define ADC14_IFGR1_RDYIFG_OFS ( 6) /*!< ADC14RDYIFG Bit Offset */ -#define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt flag */ -/* ADC14_CLRIFGR0[CLRIFG0] Bits */ -#define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /*!< CLRADC14IFG0 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /*!< clear ADC14IFG0 */ -/* ADC14_CLRIFGR0[CLRIFG1] Bits */ -#define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /*!< CLRADC14IFG1 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /*!< clear ADC14IFG1 */ -/* ADC14_CLRIFGR0[CLRIFG2] Bits */ -#define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /*!< CLRADC14IFG2 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /*!< clear ADC14IFG2 */ -/* ADC14_CLRIFGR0[CLRIFG3] Bits */ -#define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /*!< CLRADC14IFG3 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /*!< clear ADC14IFG3 */ -/* ADC14_CLRIFGR0[CLRIFG4] Bits */ -#define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /*!< CLRADC14IFG4 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /*!< clear ADC14IFG4 */ -/* ADC14_CLRIFGR0[CLRIFG5] Bits */ -#define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /*!< CLRADC14IFG5 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /*!< clear ADC14IFG5 */ -/* ADC14_CLRIFGR0[CLRIFG6] Bits */ -#define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /*!< CLRADC14IFG6 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /*!< clear ADC14IFG6 */ -/* ADC14_CLRIFGR0[CLRIFG7] Bits */ -#define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /*!< CLRADC14IFG7 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /*!< clear ADC14IFG7 */ -/* ADC14_CLRIFGR0[CLRIFG8] Bits */ -#define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /*!< CLRADC14IFG8 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /*!< clear ADC14IFG8 */ -/* ADC14_CLRIFGR0[CLRIFG9] Bits */ -#define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /*!< CLRADC14IFG9 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /*!< clear ADC14IFG9 */ -/* ADC14_CLRIFGR0[CLRIFG10] Bits */ -#define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /*!< CLRADC14IFG10 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /*!< clear ADC14IFG10 */ -/* ADC14_CLRIFGR0[CLRIFG11] Bits */ -#define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /*!< CLRADC14IFG11 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /*!< clear ADC14IFG11 */ -/* ADC14_CLRIFGR0[CLRIFG12] Bits */ -#define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /*!< CLRADC14IFG12 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /*!< clear ADC14IFG12 */ -/* ADC14_CLRIFGR0[CLRIFG13] Bits */ -#define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /*!< CLRADC14IFG13 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /*!< clear ADC14IFG13 */ -/* ADC14_CLRIFGR0[CLRIFG14] Bits */ -#define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /*!< CLRADC14IFG14 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /*!< clear ADC14IFG14 */ -/* ADC14_CLRIFGR0[CLRIFG15] Bits */ -#define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /*!< CLRADC14IFG15 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /*!< clear ADC14IFG15 */ -/* ADC14_CLRIFGR0[CLRIFG16] Bits */ -#define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /*!< CLRADC14IFG16 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /*!< clear ADC14IFG16 */ -/* ADC14_CLRIFGR0[CLRIFG17] Bits */ -#define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /*!< CLRADC14IFG17 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /*!< clear ADC14IFG17 */ -/* ADC14_CLRIFGR0[CLRIFG18] Bits */ -#define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /*!< CLRADC14IFG18 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /*!< clear ADC14IFG18 */ -/* ADC14_CLRIFGR0[CLRIFG19] Bits */ -#define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /*!< CLRADC14IFG19 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /*!< clear ADC14IFG19 */ -/* ADC14_CLRIFGR0[CLRIFG20] Bits */ -#define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /*!< CLRADC14IFG20 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /*!< clear ADC14IFG20 */ -/* ADC14_CLRIFGR0[CLRIFG21] Bits */ -#define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /*!< CLRADC14IFG21 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /*!< clear ADC14IFG21 */ -/* ADC14_CLRIFGR0[CLRIFG22] Bits */ -#define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /*!< CLRADC14IFG22 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /*!< clear ADC14IFG22 */ -/* ADC14_CLRIFGR0[CLRIFG23] Bits */ -#define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /*!< CLRADC14IFG23 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /*!< clear ADC14IFG23 */ -/* ADC14_CLRIFGR0[CLRIFG24] Bits */ -#define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /*!< CLRADC14IFG24 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /*!< clear ADC14IFG24 */ -/* ADC14_CLRIFGR0[CLRIFG25] Bits */ -#define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /*!< CLRADC14IFG25 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /*!< clear ADC14IFG25 */ -/* ADC14_CLRIFGR0[CLRIFG26] Bits */ -#define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /*!< CLRADC14IFG26 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /*!< clear ADC14IFG26 */ -/* ADC14_CLRIFGR0[CLRIFG27] Bits */ -#define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /*!< CLRADC14IFG27 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /*!< clear ADC14IFG27 */ -/* ADC14_CLRIFGR0[CLRIFG28] Bits */ -#define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /*!< CLRADC14IFG28 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /*!< clear ADC14IFG28 */ -/* ADC14_CLRIFGR0[CLRIFG29] Bits */ -#define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /*!< CLRADC14IFG29 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /*!< clear ADC14IFG29 */ -/* ADC14_CLRIFGR0[CLRIFG30] Bits */ -#define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /*!< CLRADC14IFG30 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /*!< clear ADC14IFG30 */ -/* ADC14_CLRIFGR0[CLRIFG31] Bits */ -#define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /*!< CLRADC14IFG31 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /*!< clear ADC14IFG31 */ -/* ADC14_CLRIFGR1[CLRINIFG] Bits */ -#define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /*!< CLRADC14INIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /*!< clear ADC14INIFG */ -/* ADC14_CLRIFGR1[CLRLOIFG] Bits */ -#define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /*!< CLRADC14LOIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /*!< clear ADC14LOIFG */ -/* ADC14_CLRIFGR1[CLRHIIFG] Bits */ -#define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /*!< CLRADC14HIIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /*!< clear ADC14HIIFG */ -/* ADC14_CLRIFGR1[CLROVIFG] Bits */ -#define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /*!< CLRADC14OVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /*!< clear ADC14OVIFG */ -/* ADC14_CLRIFGR1[CLRTOVIFG] Bits */ -#define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /*!< CLRADC14TOVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /*!< clear ADC14TOVIFG */ -/* ADC14_CLRIFGR1[CLRRDYIFG] Bits */ -#define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /*!< CLRADC14RDYIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /*!< clear ADC14RDYIFG */ - -/****************************************************************************** -* AES256 Bits -******************************************************************************/ -/* AES256_CTL0[OP] Bits */ -#define AES256_CTL0_OP_OFS ( 0) /*!< AESOPx Bit Offset */ -#define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /*!< AESOPx Bit Mask */ -#define AES256_CTL0_OP0 ((uint16_t)0x0001) /*!< OP Bit 0 */ -#define AES256_CTL0_OP1 ((uint16_t)0x0002) /*!< OP Bit 1 */ -#define AES256_CTL0_OP_0 ((uint16_t)0x0000) /*!< Encryption */ -#define AES256_CTL0_OP_1 ((uint16_t)0x0001) /*!< Decryption. The provided key is the same key used for encryption */ -#define AES256_CTL0_OP_2 ((uint16_t)0x0002) /*!< Generate first round key required for decryption */ -#define AES256_CTL0_OP_3 ((uint16_t)0x0003) /*!< Decryption. The provided key is the first round key required for decryption */ -/* AES256_CTL0[KL] Bits */ -#define AES256_CTL0_KL_OFS ( 2) /*!< AESKLx Bit Offset */ -#define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /*!< AESKLx Bit Mask */ -#define AES256_CTL0_KL0 ((uint16_t)0x0004) /*!< KL Bit 0 */ -#define AES256_CTL0_KL1 ((uint16_t)0x0008) /*!< KL Bit 1 */ -#define AES256_CTL0_KL_0 ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL_1 ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL_2 ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -#define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -/* AES256_CTL0[CM] Bits */ -#define AES256_CTL0_CM_OFS ( 5) /*!< AESCMx Bit Offset */ -#define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /*!< AESCMx Bit Mask */ -#define AES256_CTL0_CM0 ((uint16_t)0x0020) /*!< CM Bit 0 */ -#define AES256_CTL0_CM1 ((uint16_t)0x0040) /*!< CM Bit 1 */ -#define AES256_CTL0_CM_0 ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM_1 ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM_2 ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM_3 ((uint16_t)0x0060) /*!< CFB */ -#define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /*!< CFB */ -/* AES256_CTL0[SWRST] Bits */ -#define AES256_CTL0_SWRST_OFS ( 7) /*!< AESSWRST Bit Offset */ -#define AES256_CTL0_SWRST ((uint16_t)0x0080) /*!< AES software reset */ -/* AES256_CTL0[RDYIFG] Bits */ -#define AES256_CTL0_RDYIFG_OFS ( 8) /*!< AESRDYIFG Bit Offset */ -#define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /*!< AES ready interrupt flag */ -/* AES256_CTL0[ERRFG] Bits */ -#define AES256_CTL0_ERRFG_OFS (11) /*!< AESERRFG Bit Offset */ -#define AES256_CTL0_ERRFG ((uint16_t)0x0800) /*!< AES error flag */ -/* AES256_CTL0[RDYIE] Bits */ -#define AES256_CTL0_RDYIE_OFS (12) /*!< AESRDYIE Bit Offset */ -#define AES256_CTL0_RDYIE ((uint16_t)0x1000) /*!< AES ready interrupt enable */ -/* AES256_CTL0[CMEN] Bits */ -#define AES256_CTL0_CMEN_OFS (15) /*!< AESCMEN Bit Offset */ -#define AES256_CTL0_CMEN ((uint16_t)0x8000) /*!< AES cipher mode enable */ -/* AES256_CTL1[BLKCNT] Bits */ -#define AES256_CTL1_BLKCNT_OFS ( 0) /*!< AESBLKCNTx Bit Offset */ -#define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /*!< AESBLKCNTx Bit Mask */ -#define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /*!< BLKCNT Bit 0 */ -#define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /*!< BLKCNT Bit 1 */ -#define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /*!< BLKCNT Bit 2 */ -#define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /*!< BLKCNT Bit 3 */ -#define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /*!< BLKCNT Bit 4 */ -#define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /*!< BLKCNT Bit 5 */ -#define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /*!< BLKCNT Bit 6 */ -#define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /*!< BLKCNT Bit 7 */ -/* AES256_STAT[BUSY] Bits */ -#define AES256_STAT_BUSY_OFS ( 0) /*!< AESBUSY Bit Offset */ -#define AES256_STAT_BUSY ((uint16_t)0x0001) /*!< AES accelerator module busy */ -/* AES256_STAT[KEYWR] Bits */ -#define AES256_STAT_KEYWR_OFS ( 1) /*!< AESKEYWR Bit Offset */ -#define AES256_STAT_KEYWR ((uint16_t)0x0002) /*!< All 16 bytes written to AESAKEY */ -/* AES256_STAT[DINWR] Bits */ -#define AES256_STAT_DINWR_OFS ( 2) /*!< AESDINWR Bit Offset */ -#define AES256_STAT_DINWR ((uint16_t)0x0004) /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ -/* AES256_STAT[DOUTRD] Bits */ -#define AES256_STAT_DOUTRD_OFS ( 3) /*!< AESDOUTRD Bit Offset */ -#define AES256_STAT_DOUTRD ((uint16_t)0x0008) /*!< All 16 bytes read from AESADOUT */ -/* AES256_STAT[KEYCNT] Bits */ -#define AES256_STAT_KEYCNT_OFS ( 4) /*!< AESKEYCNTx Bit Offset */ -#define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /*!< AESKEYCNTx Bit Mask */ -#define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /*!< KEYCNT Bit 0 */ -#define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /*!< KEYCNT Bit 1 */ -#define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /*!< KEYCNT Bit 2 */ -#define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /*!< KEYCNT Bit 3 */ -/* AES256_STAT[DINCNT] Bits */ -#define AES256_STAT_DINCNT_OFS ( 8) /*!< AESDINCNTx Bit Offset */ -#define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /*!< AESDINCNTx Bit Mask */ -#define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /*!< DINCNT Bit 0 */ -#define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /*!< DINCNT Bit 1 */ -#define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /*!< DINCNT Bit 2 */ -#define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /*!< DINCNT Bit 3 */ -/* AES256_STAT[DOUTCNT] Bits */ -#define AES256_STAT_DOUTCNT_OFS (12) /*!< AESDOUTCNTx Bit Offset */ -#define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /*!< AESDOUTCNTx Bit Mask */ -#define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /*!< DOUTCNT Bit 0 */ -#define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /*!< DOUTCNT Bit 1 */ -#define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /*!< DOUTCNT Bit 2 */ -#define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /*!< DOUTCNT Bit 3 */ -/* AES256_KEY[KEY0] Bits */ -#define AES256_KEY_KEY0_OFS ( 0) /*!< AESKEY0x Bit Offset */ -#define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /*!< AESKEY0x Bit Mask */ -#define AES256_KEY_KEY00 ((uint16_t)0x0001) /*!< KEY0 Bit 0 */ -#define AES256_KEY_KEY01 ((uint16_t)0x0002) /*!< KEY0 Bit 1 */ -#define AES256_KEY_KEY02 ((uint16_t)0x0004) /*!< KEY0 Bit 2 */ -#define AES256_KEY_KEY03 ((uint16_t)0x0008) /*!< KEY0 Bit 3 */ -#define AES256_KEY_KEY04 ((uint16_t)0x0010) /*!< KEY0 Bit 4 */ -#define AES256_KEY_KEY05 ((uint16_t)0x0020) /*!< KEY0 Bit 5 */ -#define AES256_KEY_KEY06 ((uint16_t)0x0040) /*!< KEY0 Bit 6 */ -#define AES256_KEY_KEY07 ((uint16_t)0x0080) /*!< KEY0 Bit 7 */ -/* AES256_KEY[KEY1] Bits */ -#define AES256_KEY_KEY1_OFS ( 8) /*!< AESKEY1x Bit Offset */ -#define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /*!< AESKEY1x Bit Mask */ -#define AES256_KEY_KEY10 ((uint16_t)0x0100) /*!< KEY1 Bit 0 */ -#define AES256_KEY_KEY11 ((uint16_t)0x0200) /*!< KEY1 Bit 1 */ -#define AES256_KEY_KEY12 ((uint16_t)0x0400) /*!< KEY1 Bit 2 */ -#define AES256_KEY_KEY13 ((uint16_t)0x0800) /*!< KEY1 Bit 3 */ -#define AES256_KEY_KEY14 ((uint16_t)0x1000) /*!< KEY1 Bit 4 */ -#define AES256_KEY_KEY15 ((uint16_t)0x2000) /*!< KEY1 Bit 5 */ -#define AES256_KEY_KEY16 ((uint16_t)0x4000) /*!< KEY1 Bit 6 */ -#define AES256_KEY_KEY17 ((uint16_t)0x8000) /*!< KEY1 Bit 7 */ -/* AES256_DIN[DIN0] Bits */ -#define AES256_DIN_DIN0_OFS ( 0) /*!< AESDIN0x Bit Offset */ -#define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /*!< AESDIN0x Bit Mask */ -#define AES256_DIN_DIN00 ((uint16_t)0x0001) /*!< DIN0 Bit 0 */ -#define AES256_DIN_DIN01 ((uint16_t)0x0002) /*!< DIN0 Bit 1 */ -#define AES256_DIN_DIN02 ((uint16_t)0x0004) /*!< DIN0 Bit 2 */ -#define AES256_DIN_DIN03 ((uint16_t)0x0008) /*!< DIN0 Bit 3 */ -#define AES256_DIN_DIN04 ((uint16_t)0x0010) /*!< DIN0 Bit 4 */ -#define AES256_DIN_DIN05 ((uint16_t)0x0020) /*!< DIN0 Bit 5 */ -#define AES256_DIN_DIN06 ((uint16_t)0x0040) /*!< DIN0 Bit 6 */ -#define AES256_DIN_DIN07 ((uint16_t)0x0080) /*!< DIN0 Bit 7 */ -/* AES256_DIN[DIN1] Bits */ -#define AES256_DIN_DIN1_OFS ( 8) /*!< AESDIN1x Bit Offset */ -#define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /*!< AESDIN1x Bit Mask */ -#define AES256_DIN_DIN10 ((uint16_t)0x0100) /*!< DIN1 Bit 0 */ -#define AES256_DIN_DIN11 ((uint16_t)0x0200) /*!< DIN1 Bit 1 */ -#define AES256_DIN_DIN12 ((uint16_t)0x0400) /*!< DIN1 Bit 2 */ -#define AES256_DIN_DIN13 ((uint16_t)0x0800) /*!< DIN1 Bit 3 */ -#define AES256_DIN_DIN14 ((uint16_t)0x1000) /*!< DIN1 Bit 4 */ -#define AES256_DIN_DIN15 ((uint16_t)0x2000) /*!< DIN1 Bit 5 */ -#define AES256_DIN_DIN16 ((uint16_t)0x4000) /*!< DIN1 Bit 6 */ -#define AES256_DIN_DIN17 ((uint16_t)0x8000) /*!< DIN1 Bit 7 */ -/* AES256_DOUT[DOUT0] Bits */ -#define AES256_DOUT_DOUT0_OFS ( 0) /*!< AESDOUT0x Bit Offset */ -#define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /*!< AESDOUT0x Bit Mask */ -#define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /*!< DOUT0 Bit 0 */ -#define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /*!< DOUT0 Bit 1 */ -#define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /*!< DOUT0 Bit 2 */ -#define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /*!< DOUT0 Bit 3 */ -#define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /*!< DOUT0 Bit 4 */ -#define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /*!< DOUT0 Bit 5 */ -#define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /*!< DOUT0 Bit 6 */ -#define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /*!< DOUT0 Bit 7 */ -/* AES256_DOUT[DOUT1] Bits */ -#define AES256_DOUT_DOUT1_OFS ( 8) /*!< AESDOUT1x Bit Offset */ -#define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /*!< AESDOUT1x Bit Mask */ -#define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /*!< DOUT1 Bit 0 */ -#define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /*!< DOUT1 Bit 1 */ -#define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /*!< DOUT1 Bit 2 */ -#define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /*!< DOUT1 Bit 3 */ -#define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /*!< DOUT1 Bit 4 */ -#define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /*!< DOUT1 Bit 5 */ -#define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /*!< DOUT1 Bit 6 */ -#define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /*!< DOUT1 Bit 7 */ -/* AES256_XDIN[XDIN0] Bits */ -#define AES256_XDIN_XDIN0_OFS ( 0) /*!< AESXDIN0x Bit Offset */ -#define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /*!< AESXDIN0x Bit Mask */ -#define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /*!< XDIN0 Bit 0 */ -#define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /*!< XDIN0 Bit 1 */ -#define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /*!< XDIN0 Bit 2 */ -#define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /*!< XDIN0 Bit 3 */ -#define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /*!< XDIN0 Bit 4 */ -#define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /*!< XDIN0 Bit 5 */ -#define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /*!< XDIN0 Bit 6 */ -#define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /*!< XDIN0 Bit 7 */ -/* AES256_XDIN[XDIN1] Bits */ -#define AES256_XDIN_XDIN1_OFS ( 8) /*!< AESXDIN1x Bit Offset */ -#define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /*!< AESXDIN1x Bit Mask */ -#define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /*!< XDIN1 Bit 0 */ -#define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /*!< XDIN1 Bit 1 */ -#define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /*!< XDIN1 Bit 2 */ -#define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /*!< XDIN1 Bit 3 */ -#define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /*!< XDIN1 Bit 4 */ -#define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /*!< XDIN1 Bit 5 */ -#define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /*!< XDIN1 Bit 6 */ -#define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /*!< XDIN1 Bit 7 */ -/* AES256_XIN[XIN0] Bits */ -#define AES256_XIN_XIN0_OFS ( 0) /*!< AESXIN0x Bit Offset */ -#define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /*!< AESXIN0x Bit Mask */ -#define AES256_XIN_XIN00 ((uint16_t)0x0001) /*!< XIN0 Bit 0 */ -#define AES256_XIN_XIN01 ((uint16_t)0x0002) /*!< XIN0 Bit 1 */ -#define AES256_XIN_XIN02 ((uint16_t)0x0004) /*!< XIN0 Bit 2 */ -#define AES256_XIN_XIN03 ((uint16_t)0x0008) /*!< XIN0 Bit 3 */ -#define AES256_XIN_XIN04 ((uint16_t)0x0010) /*!< XIN0 Bit 4 */ -#define AES256_XIN_XIN05 ((uint16_t)0x0020) /*!< XIN0 Bit 5 */ -#define AES256_XIN_XIN06 ((uint16_t)0x0040) /*!< XIN0 Bit 6 */ -#define AES256_XIN_XIN07 ((uint16_t)0x0080) /*!< XIN0 Bit 7 */ -/* AES256_XIN[XIN1] Bits */ -#define AES256_XIN_XIN1_OFS ( 8) /*!< AESXIN1x Bit Offset */ -#define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /*!< AESXIN1x Bit Mask */ -#define AES256_XIN_XIN10 ((uint16_t)0x0100) /*!< XIN1 Bit 0 */ -#define AES256_XIN_XIN11 ((uint16_t)0x0200) /*!< XIN1 Bit 1 */ -#define AES256_XIN_XIN12 ((uint16_t)0x0400) /*!< XIN1 Bit 2 */ -#define AES256_XIN_XIN13 ((uint16_t)0x0800) /*!< XIN1 Bit 3 */ -#define AES256_XIN_XIN14 ((uint16_t)0x1000) /*!< XIN1 Bit 4 */ -#define AES256_XIN_XIN15 ((uint16_t)0x2000) /*!< XIN1 Bit 5 */ -#define AES256_XIN_XIN16 ((uint16_t)0x4000) /*!< XIN1 Bit 6 */ -#define AES256_XIN_XIN17 ((uint16_t)0x8000) /*!< XIN1 Bit 7 */ - -/****************************************************************************** -* CAPTIO Bits -******************************************************************************/ -/* CAPTIO_CTL[PISEL] Bits */ -#define CAPTIO_CTL_PISEL_OFS ( 1) /*!< CAPTIOPISELx Bit Offset */ -#define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /*!< CAPTIOPISELx Bit Mask */ -#define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /*!< PISEL Bit 0 */ -#define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /*!< PISEL Bit 1 */ -#define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /*!< PISEL Bit 2 */ -#define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /*!< Px.0 */ -#define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /*!< Px.1 */ -#define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /*!< Px.2 */ -#define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /*!< Px.3 */ -#define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /*!< Px.4 */ -#define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /*!< Px.5 */ -#define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /*!< Px.6 */ -#define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /*!< Px.7 */ -/* CAPTIO_CTL[POSEL] Bits */ -#define CAPTIO_CTL_POSEL_OFS ( 4) /*!< CAPTIOPOSELx Bit Offset */ -#define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /*!< CAPTIOPOSELx Bit Mask */ -#define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /*!< POSEL Bit 0 */ -#define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /*!< POSEL Bit 1 */ -#define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /*!< POSEL Bit 2 */ -#define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /*!< POSEL Bit 3 */ -#define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /*!< Px = P15 */ -#define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /*!< Px = P15 */ -/* CAPTIO_CTL[EN] Bits */ -#define CAPTIO_CTL_EN_OFS ( 8) /*!< CAPTIOEN Bit Offset */ -#define CAPTIO_CTL_EN ((uint16_t)0x0100) /*!< Capacitive Touch IO enable */ -/* CAPTIO_CTL[STATE] Bits */ -#define CAPTIO_CTL_STATE_OFS ( 9) /*!< CAPTIOSTATE Bit Offset */ -#define CAPTIO_CTL_STATE ((uint16_t)0x0200) /*!< Capacitive Touch IO state */ - -/****************************************************************************** -* COMP_E Bits -******************************************************************************/ -/* COMP_E_CTL0[IPSEL] Bits */ -#define COMP_E_CTL0_IPSEL_OFS ( 0) /*!< CEIPSEL Bit Offset */ -#define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /*!< CEIPSEL Bit Mask */ -#define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /*!< IPSEL Bit 0 */ -#define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /*!< IPSEL Bit 1 */ -#define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /*!< IPSEL Bit 2 */ -#define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /*!< IPSEL Bit 3 */ -#define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /*!< Channel 15 selected */ -/* COMP_E_CTL0[IPEN] Bits */ -#define COMP_E_CTL0_IPEN_OFS ( 7) /*!< CEIPEN Bit Offset */ -#define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /*!< Channel input enable for the V+ terminal */ -/* COMP_E_CTL0[IMSEL] Bits */ -#define COMP_E_CTL0_IMSEL_OFS ( 8) /*!< CEIMSEL Bit Offset */ -#define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /*!< CEIMSEL Bit Mask */ -#define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /*!< IMSEL Bit 0 */ -#define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /*!< IMSEL Bit 1 */ -#define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /*!< IMSEL Bit 2 */ -#define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /*!< IMSEL Bit 3 */ -#define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /*!< Channel 15 selected */ -/* COMP_E_CTL0[IMEN] Bits */ -#define COMP_E_CTL0_IMEN_OFS (15) /*!< CEIMEN Bit Offset */ -#define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /*!< Channel input enable for the - terminal */ -/* COMP_E_CTL1[OUT] Bits */ -#define COMP_E_CTL1_OUT_OFS ( 0) /*!< CEOUT Bit Offset */ -#define COMP_E_CTL1_OUT ((uint16_t)0x0001) /*!< Comparator output value */ -/* COMP_E_CTL1[OUTPOL] Bits */ -#define COMP_E_CTL1_OUTPOL_OFS ( 1) /*!< CEOUTPOL Bit Offset */ -#define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /*!< Comparator output polarity */ -/* COMP_E_CTL1[F] Bits */ -#define COMP_E_CTL1_F_OFS ( 2) /*!< CEF Bit Offset */ -#define COMP_E_CTL1_F ((uint16_t)0x0004) /*!< Comparator output filter */ -/* COMP_E_CTL1[IES] Bits */ -#define COMP_E_CTL1_IES_OFS ( 3) /*!< CEIES Bit Offset */ -#define COMP_E_CTL1_IES ((uint16_t)0x0008) /*!< Interrupt edge select for CEIIFG and CEIFG */ -/* COMP_E_CTL1[SHORT] Bits */ -#define COMP_E_CTL1_SHORT_OFS ( 4) /*!< CESHORT Bit Offset */ -#define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /*!< Input short */ -/* COMP_E_CTL1[EX] Bits */ -#define COMP_E_CTL1_EX_OFS ( 5) /*!< CEEX Bit Offset */ -#define COMP_E_CTL1_EX ((uint16_t)0x0020) /*!< Exchange */ -/* COMP_E_CTL1[FDLY] Bits */ -#define COMP_E_CTL1_FDLY_OFS ( 6) /*!< CEFDLY Bit Offset */ -#define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /*!< CEFDLY Bit Mask */ -#define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /*!< FDLY Bit 0 */ -#define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /*!< FDLY Bit 1 */ -#define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /*!< Typical filter delay of TBD (450) ns */ -#define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /*!< Typical filter delay of TBD (900) ns */ -#define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /*!< Typical filter delay of TBD (1800) ns */ -#define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /*!< Typical filter delay of TBD (3600) ns */ -/* COMP_E_CTL1[PWRMD] Bits */ -#define COMP_E_CTL1_PWRMD_OFS ( 8) /*!< CEPWRMD Bit Offset */ -#define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /*!< CEPWRMD Bit Mask */ -#define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /*!< PWRMD Bit 0 */ -#define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /*!< PWRMD Bit 1 */ -#define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /*!< High-speed mode */ -#define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /*!< Normal mode */ -#define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /*!< Ultra-low power mode */ -/* COMP_E_CTL1[ON] Bits */ -#define COMP_E_CTL1_ON_OFS (10) /*!< CEON Bit Offset */ -#define COMP_E_CTL1_ON ((uint16_t)0x0400) /*!< Comparator On */ -/* COMP_E_CTL1[MRVL] Bits */ -#define COMP_E_CTL1_MRVL_OFS (11) /*!< CEMRVL Bit Offset */ -#define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /*!< This bit is valid of CEMRVS is set to 1 */ -/* COMP_E_CTL1[MRVS] Bits */ -#define COMP_E_CTL1_MRVS_OFS (12) /*!< CEMRVS Bit Offset */ -#define COMP_E_CTL1_MRVS ((uint16_t)0x1000) -/* COMP_E_CTL2[REF0] Bits */ -#define COMP_E_CTL2_REF0_OFS ( 0) /*!< CEREF0 Bit Offset */ -#define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /*!< CEREF0 Bit Mask */ -/* COMP_E_CTL2[RSEL] Bits */ -#define COMP_E_CTL2_RSEL_OFS ( 5) /*!< CERSEL Bit Offset */ -#define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /*!< Reference select */ -/* COMP_E_CTL2[RS] Bits */ -#define COMP_E_CTL2_RS_OFS ( 6) /*!< CERS Bit Offset */ -#define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /*!< CERS Bit Mask */ -#define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /*!< RS Bit 0 */ -#define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /*!< RS Bit 1 */ -#define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /*!< No current is drawn by the reference circuitry */ -#define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /*!< VCC applied to the resistor ladder */ -#define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /*!< Shared reference voltage applied to the resistor ladder */ -#define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ -/* COMP_E_CTL2[REF1] Bits */ -#define COMP_E_CTL2_REF1_OFS ( 8) /*!< CEREF1 Bit Offset */ -#define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /*!< CEREF1 Bit Mask */ -/* COMP_E_CTL2[REFL] Bits */ -#define COMP_E_CTL2_REFL_OFS (13) /*!< CEREFL Bit Offset */ -#define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /*!< CEREFL Bit Mask */ -#define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /*!< REFL Bit 0 */ -#define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /*!< REFL Bit 1 */ -#define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -/* COMP_E_CTL2[REFACC] Bits */ -#define COMP_E_CTL2_REFACC_OFS (15) /*!< CEREFACC Bit Offset */ -#define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /*!< Reference accuracy */ -/* COMP_E_CTL3[PD0] Bits */ -#define COMP_E_CTL3_PD0_OFS ( 0) /*!< CEPD0 Bit Offset */ -#define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /*!< Port disable */ -/* COMP_E_CTL3[PD1] Bits */ -#define COMP_E_CTL3_PD1_OFS ( 1) /*!< CEPD1 Bit Offset */ -#define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /*!< Port disable */ -/* COMP_E_CTL3[PD2] Bits */ -#define COMP_E_CTL3_PD2_OFS ( 2) /*!< CEPD2 Bit Offset */ -#define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /*!< Port disable */ -/* COMP_E_CTL3[PD3] Bits */ -#define COMP_E_CTL3_PD3_OFS ( 3) /*!< CEPD3 Bit Offset */ -#define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /*!< Port disable */ -/* COMP_E_CTL3[PD4] Bits */ -#define COMP_E_CTL3_PD4_OFS ( 4) /*!< CEPD4 Bit Offset */ -#define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /*!< Port disable */ -/* COMP_E_CTL3[PD5] Bits */ -#define COMP_E_CTL3_PD5_OFS ( 5) /*!< CEPD5 Bit Offset */ -#define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /*!< Port disable */ -/* COMP_E_CTL3[PD6] Bits */ -#define COMP_E_CTL3_PD6_OFS ( 6) /*!< CEPD6 Bit Offset */ -#define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /*!< Port disable */ -/* COMP_E_CTL3[PD7] Bits */ -#define COMP_E_CTL3_PD7_OFS ( 7) /*!< CEPD7 Bit Offset */ -#define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /*!< Port disable */ -/* COMP_E_CTL3[PD8] Bits */ -#define COMP_E_CTL3_PD8_OFS ( 8) /*!< CEPD8 Bit Offset */ -#define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /*!< Port disable */ -/* COMP_E_CTL3[PD9] Bits */ -#define COMP_E_CTL3_PD9_OFS ( 9) /*!< CEPD9 Bit Offset */ -#define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /*!< Port disable */ -/* COMP_E_CTL3[PD10] Bits */ -#define COMP_E_CTL3_PD10_OFS (10) /*!< CEPD10 Bit Offset */ -#define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /*!< Port disable */ -/* COMP_E_CTL3[PD11] Bits */ -#define COMP_E_CTL3_PD11_OFS (11) /*!< CEPD11 Bit Offset */ -#define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /*!< Port disable */ -/* COMP_E_CTL3[PD12] Bits */ -#define COMP_E_CTL3_PD12_OFS (12) /*!< CEPD12 Bit Offset */ -#define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /*!< Port disable */ -/* COMP_E_CTL3[PD13] Bits */ -#define COMP_E_CTL3_PD13_OFS (13) /*!< CEPD13 Bit Offset */ -#define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /*!< Port disable */ -/* COMP_E_CTL3[PD14] Bits */ -#define COMP_E_CTL3_PD14_OFS (14) /*!< CEPD14 Bit Offset */ -#define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /*!< Port disable */ -/* COMP_E_CTL3[PD15] Bits */ -#define COMP_E_CTL3_PD15_OFS (15) /*!< CEPD15 Bit Offset */ -#define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /*!< Port disable */ -/* COMP_E_INT[IFG] Bits */ -#define COMP_E_INT_IFG_OFS ( 0) /*!< CEIFG Bit Offset */ -#define COMP_E_INT_IFG ((uint16_t)0x0001) /*!< Comparator output interrupt flag */ -/* COMP_E_INT[IIFG] Bits */ -#define COMP_E_INT_IIFG_OFS ( 1) /*!< CEIIFG Bit Offset */ -#define COMP_E_INT_IIFG ((uint16_t)0x0002) /*!< Comparator output inverted interrupt flag */ -/* COMP_E_INT[RDYIFG] Bits */ -#define COMP_E_INT_RDYIFG_OFS ( 4) /*!< CERDYIFG Bit Offset */ -#define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /*!< Comparator ready interrupt flag */ -/* COMP_E_INT[IE] Bits */ -#define COMP_E_INT_IE_OFS ( 8) /*!< CEIE Bit Offset */ -#define COMP_E_INT_IE ((uint16_t)0x0100) /*!< Comparator output interrupt enable */ -/* COMP_E_INT[IIE] Bits */ -#define COMP_E_INT_IIE_OFS ( 9) /*!< CEIIE Bit Offset */ -#define COMP_E_INT_IIE ((uint16_t)0x0200) /*!< Comparator output interrupt enable inverted polarity */ -/* COMP_E_INT[RDYIE] Bits */ -#define COMP_E_INT_RDYIE_OFS (12) /*!< CERDYIE Bit Offset */ -#define COMP_E_INT_RDYIE ((uint16_t)0x1000) /*!< Comparator ready interrupt enable */ - -/****************************************************************************** -* COREDEBUG Bits -******************************************************************************/ - - -/****************************************************************************** -* CRC32 Bits -******************************************************************************/ - -/****************************************************************************** -* CS Bits -******************************************************************************/ -/* CS_KEY[KEY] Bits */ -#define CS_KEY_KEY_OFS ( 0) /*!< CSKEY Bit Offset */ -#define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< CSKEY Bit Mask */ -/* CS_CTL0[DCOTUNE] Bits */ -#define CS_CTL0_DCOTUNE_OFS ( 0) /*!< DCOTUNE Bit Offset */ -#define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /*!< DCOTUNE Bit Mask */ -/* CS_CTL0[DCORSEL] Bits */ -#define CS_CTL0_DCORSEL_OFS (16) /*!< DCORSEL Bit Offset */ -#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /*!< DCORSEL Bit Mask */ -#define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /*!< DCORSEL Bit 0 */ -#define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /*!< DCORSEL Bit 1 */ -#define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /*!< DCORSEL Bit 2 */ -#define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */ -#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */ -#define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */ -#define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */ -#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */ -#define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */ -/* CS_CTL0[DCORES] Bits */ -#define CS_CTL0_DCORES_OFS (22) /*!< DCORES Bit Offset */ -#define CS_CTL0_DCORES ((uint32_t)0x00400000) /*!< Enables the DCO external resistor mode */ -/* CS_CTL0[DCOEN] Bits */ -#define CS_CTL0_DCOEN_OFS (23) /*!< DCOEN Bit Offset */ -#define CS_CTL0_DCOEN ((uint32_t)0x00800000) /*!< Enables the DCO oscillator */ -/* CS_CTL1[SELM] Bits */ -#define CS_CTL1_SELM_OFS ( 0) /*!< SELM Bit Offset */ -#define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /*!< SELM Bit Mask */ -#define CS_CTL1_SELM0 ((uint32_t)0x00000001) /*!< SELM Bit 0 */ -#define CS_CTL1_SELM1 ((uint32_t)0x00000002) /*!< SELM Bit 1 */ -#define CS_CTL1_SELM2 ((uint32_t)0x00000004) /*!< SELM Bit 2 */ -#define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM_1 ((uint32_t)0x00000001) -#define CS_CTL1_SELM_2 ((uint32_t)0x00000002) -#define CS_CTL1_SELM_3 ((uint32_t)0x00000003) -#define CS_CTL1_SELM_4 ((uint32_t)0x00000004) -#define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001) -#define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002) -#define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003) -#define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004) -#define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -/* CS_CTL1[SELS] Bits */ -#define CS_CTL1_SELS_OFS ( 4) /*!< SELS Bit Offset */ -#define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /*!< SELS Bit Mask */ -#define CS_CTL1_SELS0 ((uint32_t)0x00000010) /*!< SELS Bit 0 */ -#define CS_CTL1_SELS1 ((uint32_t)0x00000020) /*!< SELS Bit 1 */ -#define CS_CTL1_SELS2 ((uint32_t)0x00000040) /*!< SELS Bit 2 */ -#define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS_1 ((uint32_t)0x00000010) -#define CS_CTL1_SELS_2 ((uint32_t)0x00000020) -#define CS_CTL1_SELS_3 ((uint32_t)0x00000030) -#define CS_CTL1_SELS_4 ((uint32_t)0x00000040) -#define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010) -#define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020) -#define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030) -#define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040) -#define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -/* CS_CTL1[SELA] Bits */ -#define CS_CTL1_SELA_OFS ( 8) /*!< SELA Bit Offset */ -#define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /*!< SELA Bit Mask */ -#define CS_CTL1_SELA0 ((uint32_t)0x00000100) /*!< SELA Bit 0 */ -#define CS_CTL1_SELA1 ((uint32_t)0x00000200) /*!< SELA Bit 1 */ -#define CS_CTL1_SELA2 ((uint32_t)0x00000400) /*!< SELA Bit 2 */ -#define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA_1 ((uint32_t)0x00000100) -#define CS_CTL1_SELA_2 ((uint32_t)0x00000200) -#define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100) -#define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200) -/* CS_CTL1[SELB] Bits */ -#define CS_CTL1_SELB_OFS (12) /*!< SELB Bit Offset */ -#define CS_CTL1_SELB ((uint32_t)0x00001000) /*!< Selects the BCLK source */ -/* CS_CTL1[DIVM] Bits */ -#define CS_CTL1_DIVM_OFS (16) /*!< DIVM Bit Offset */ -#define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /*!< DIVM Bit Mask */ -#define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /*!< DIVM Bit 0 */ -#define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /*!< DIVM Bit 1 */ -#define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /*!< DIVM Bit 2 */ -#define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -#define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -/* CS_CTL1[DIVHS] Bits */ -#define CS_CTL1_DIVHS_OFS (20) /*!< DIVHS Bit Offset */ -#define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /*!< DIVHS Bit Mask */ -#define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /*!< DIVHS Bit 0 */ -#define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /*!< DIVHS Bit 1 */ -#define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /*!< DIVHS Bit 2 */ -#define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -#define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -/* CS_CTL1[DIVA] Bits */ -#define CS_CTL1_DIVA_OFS (24) /*!< DIVA Bit Offset */ -#define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /*!< DIVA Bit Mask */ -#define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /*!< DIVA Bit 0 */ -#define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /*!< DIVA Bit 1 */ -#define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /*!< DIVA Bit 2 */ -#define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -#define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -/* CS_CTL1[DIVS] Bits */ -#define CS_CTL1_DIVS_OFS (28) /*!< DIVS Bit Offset */ -#define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /*!< DIVS Bit Mask */ -#define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /*!< DIVS Bit 0 */ -#define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /*!< DIVS Bit 1 */ -#define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /*!< DIVS Bit 2 */ -#define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -#define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -/* CS_CTL2[LFXTDRIVE] Bits */ -#define CS_CTL2_LFXTDRIVE_OFS ( 0) /*!< LFXTDRIVE Bit Offset */ -#define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /*!< LFXTDRIVE Bit Mask */ -#define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /*!< LFXTDRIVE Bit 0 */ -#define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /*!< LFXTDRIVE Bit 1 */ -#define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /*!< Lowest drive strength and current consumption LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */ -/* CS_CTL2[LFXT_EN] Bits */ -#define CS_CTL2_LFXT_EN_OFS ( 8) /*!< LFXT_EN Bit Offset */ -#define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /*!< Turns on the LFXT oscillator regardless if used as a clock resource */ -/* CS_CTL2[LFXTBYPASS] Bits */ -#define CS_CTL2_LFXTBYPASS_OFS ( 9) /*!< LFXTBYPASS Bit Offset */ -#define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /*!< LFXT bypass select */ -/* CS_CTL2[HFXTDRIVE] Bits */ -#define CS_CTL2_HFXTDRIVE_OFS (16) /*!< HFXTDRIVE Bit Offset */ -#define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /*!< HFXT oscillator drive selection */ -/* CS_CTL2[HFXTFREQ] Bits */ -#define CS_CTL2_HFXTFREQ_OFS (20) /*!< HFXTFREQ Bit Offset */ -#define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /*!< HFXTFREQ Bit Mask */ -#define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /*!< HFXTFREQ Bit 0 */ -#define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /*!< HFXTFREQ Bit 1 */ -#define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /*!< HFXTFREQ Bit 2 */ -#define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /*!< 1 MHz to 4 MHz */ -#define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /*!< >4 MHz to 8 MHz */ -#define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /*!< >8 MHz to 16 MHz */ -#define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /*!< >16 MHz to 24 MHz */ -#define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /*!< >24 MHz to 32 MHz */ -#define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /*!< >32 MHz to 40 MHz */ -#define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /*!< >40 MHz to 48 MHz */ -#define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /*!< Reserved for future use. */ -/* CS_CTL2[HFXT_EN] Bits */ -#define CS_CTL2_HFXT_EN_OFS (24) /*!< HFXT_EN Bit Offset */ -#define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /*!< Turns on the HFXT oscillator regardless if used as a clock resource */ -/* CS_CTL2[HFXTBYPASS] Bits */ -#define CS_CTL2_HFXTBYPASS_OFS (25) /*!< HFXTBYPASS Bit Offset */ -#define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /*!< HFXT bypass select */ -/* CS_CTL3[FCNTLF] Bits */ -#define CS_CTL3_FCNTLF_OFS ( 0) /*!< FCNTLF Bit Offset */ -#define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /*!< FCNTLF Bit Mask */ -#define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /*!< FCNTLF Bit 0 */ -#define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /*!< FCNTLF Bit 1 */ -#define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /*!< 32768 cycles */ -#define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /*!< 32768 cycles */ -/* CS_CTL3[RFCNTLF] Bits */ -#define CS_CTL3_RFCNTLF_OFS ( 2) /*!< RFCNTLF Bit Offset */ -#define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /*!< Reset start fault counter for LFXT */ -/* CS_CTL3[FCNTLF_EN] Bits */ -#define CS_CTL3_FCNTLF_EN_OFS ( 3) /*!< FCNTLF_EN Bit Offset */ -#define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /*!< Enable start fault counter for LFXT */ -/* CS_CTL3[FCNTHF] Bits */ -#define CS_CTL3_FCNTHF_OFS ( 4) /*!< FCNTHF Bit Offset */ -#define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /*!< FCNTHF Bit Mask */ -#define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /*!< FCNTHF Bit 0 */ -#define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /*!< FCNTHF Bit 1 */ -#define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /*!< 16384 cycles */ -#define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /*!< 16384 cycles */ -/* CS_CTL3[RFCNTHF] Bits */ -#define CS_CTL3_RFCNTHF_OFS ( 6) /*!< RFCNTHF Bit Offset */ -#define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /*!< Reset start fault counter for HFXT */ -/* CS_CTL3[FCNTHF_EN] Bits */ -#define CS_CTL3_FCNTHF_EN_OFS ( 7) /*!< FCNTHF_EN Bit Offset */ -#define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /*!< Enable start fault counter for HFXT */ -/* CS_CLKEN[ACLK_EN] Bits */ -#define CS_CLKEN_ACLK_EN_OFS ( 0) /*!< ACLK_EN Bit Offset */ -#define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /*!< ACLK system clock conditional request enable */ -/* CS_CLKEN[MCLK_EN] Bits */ -#define CS_CLKEN_MCLK_EN_OFS ( 1) /*!< MCLK_EN Bit Offset */ -#define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /*!< MCLK system clock conditional request enable */ -/* CS_CLKEN[HSMCLK_EN] Bits */ -#define CS_CLKEN_HSMCLK_EN_OFS ( 2) /*!< HSMCLK_EN Bit Offset */ -#define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /*!< HSMCLK system clock conditional request enable */ -/* CS_CLKEN[SMCLK_EN] Bits */ -#define CS_CLKEN_SMCLK_EN_OFS ( 3) /*!< SMCLK_EN Bit Offset */ -#define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /*!< SMCLK system clock conditional request enable */ -/* CS_CLKEN[VLO_EN] Bits */ -#define CS_CLKEN_VLO_EN_OFS ( 8) /*!< VLO_EN Bit Offset */ -#define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /*!< Turns on the VLO oscillator */ -/* CS_CLKEN[REFO_EN] Bits */ -#define CS_CLKEN_REFO_EN_OFS ( 9) /*!< REFO_EN Bit Offset */ -#define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /*!< Turns on the REFO oscillator */ -/* CS_CLKEN[MODOSC_EN] Bits */ -#define CS_CLKEN_MODOSC_EN_OFS (10) /*!< MODOSC_EN Bit Offset */ -#define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /*!< Turns on the MODOSC oscillator */ -/* CS_CLKEN[REFOFSEL] Bits */ -#define CS_CLKEN_REFOFSEL_OFS (15) /*!< REFOFSEL Bit Offset */ -#define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /*!< Selects REFO nominal frequency */ -/* CS_STAT[DCO_ON] Bits */ -#define CS_STAT_DCO_ON_OFS ( 0) /*!< DCO_ON Bit Offset */ -#define CS_STAT_DCO_ON ((uint32_t)0x00000001) /*!< DCO status */ -/* CS_STAT[DCOBIAS_ON] Bits */ -#define CS_STAT_DCOBIAS_ON_OFS ( 1) /*!< DCOBIAS_ON Bit Offset */ -#define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /*!< DCO bias status */ -/* CS_STAT[HFXT_ON] Bits */ -#define CS_STAT_HFXT_ON_OFS ( 2) /*!< HFXT_ON Bit Offset */ -#define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /*!< HFXT status */ -/* CS_STAT[MODOSC_ON] Bits */ -#define CS_STAT_MODOSC_ON_OFS ( 4) /*!< MODOSC_ON Bit Offset */ -#define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /*!< MODOSC status */ -/* CS_STAT[VLO_ON] Bits */ -#define CS_STAT_VLO_ON_OFS ( 5) /*!< VLO_ON Bit Offset */ -#define CS_STAT_VLO_ON ((uint32_t)0x00000020) /*!< VLO status */ -/* CS_STAT[LFXT_ON] Bits */ -#define CS_STAT_LFXT_ON_OFS ( 6) /*!< LFXT_ON Bit Offset */ -#define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /*!< LFXT status */ -/* CS_STAT[REFO_ON] Bits */ -#define CS_STAT_REFO_ON_OFS ( 7) /*!< REFO_ON Bit Offset */ -#define CS_STAT_REFO_ON ((uint32_t)0x00000080) /*!< REFO status */ -/* CS_STAT[ACLK_ON] Bits */ -#define CS_STAT_ACLK_ON_OFS (16) /*!< ACLK_ON Bit Offset */ -#define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /*!< ACLK system clock status */ -/* CS_STAT[MCLK_ON] Bits */ -#define CS_STAT_MCLK_ON_OFS (17) /*!< MCLK_ON Bit Offset */ -#define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /*!< MCLK system clock status */ -/* CS_STAT[HSMCLK_ON] Bits */ -#define CS_STAT_HSMCLK_ON_OFS (18) /*!< HSMCLK_ON Bit Offset */ -#define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /*!< HSMCLK system clock status */ -/* CS_STAT[SMCLK_ON] Bits */ -#define CS_STAT_SMCLK_ON_OFS (19) /*!< SMCLK_ON Bit Offset */ -#define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /*!< SMCLK system clock status */ -/* CS_STAT[MODCLK_ON] Bits */ -#define CS_STAT_MODCLK_ON_OFS (20) /*!< MODCLK_ON Bit Offset */ -#define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /*!< MODCLK system clock status */ -/* CS_STAT[VLOCLK_ON] Bits */ -#define CS_STAT_VLOCLK_ON_OFS (21) /*!< VLOCLK_ON Bit Offset */ -#define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /*!< VLOCLK system clock status */ -/* CS_STAT[LFXTCLK_ON] Bits */ -#define CS_STAT_LFXTCLK_ON_OFS (22) /*!< LFXTCLK_ON Bit Offset */ -#define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /*!< LFXTCLK system clock status */ -/* CS_STAT[REFOCLK_ON] Bits */ -#define CS_STAT_REFOCLK_ON_OFS (23) /*!< REFOCLK_ON Bit Offset */ -#define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /*!< REFOCLK system clock status */ -/* CS_STAT[ACLK_READY] Bits */ -#define CS_STAT_ACLK_READY_OFS (24) /*!< ACLK_READY Bit Offset */ -#define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /*!< ACLK Ready status */ -/* CS_STAT[MCLK_READY] Bits */ -#define CS_STAT_MCLK_READY_OFS (25) /*!< MCLK_READY Bit Offset */ -#define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /*!< MCLK Ready status */ -/* CS_STAT[HSMCLK_READY] Bits */ -#define CS_STAT_HSMCLK_READY_OFS (26) /*!< HSMCLK_READY Bit Offset */ -#define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /*!< HSMCLK Ready status */ -/* CS_STAT[SMCLK_READY] Bits */ -#define CS_STAT_SMCLK_READY_OFS (27) /*!< SMCLK_READY Bit Offset */ -#define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /*!< SMCLK Ready status */ -/* CS_STAT[BCLK_READY] Bits */ -#define CS_STAT_BCLK_READY_OFS (28) /*!< BCLK_READY Bit Offset */ -#define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /*!< BCLK Ready status */ -/* CS_IE[LFXTIE] Bits */ -#define CS_IE_LFXTIE_OFS ( 0) /*!< LFXTIE Bit Offset */ -#define CS_IE_LFXTIE ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag interrupt enable */ -/* CS_IE[HFXTIE] Bits */ -#define CS_IE_HFXTIE_OFS ( 1) /*!< HFXTIE Bit Offset */ -#define CS_IE_HFXTIE ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag interrupt enable */ -/* CS_IE[DCOR_OPNIE] Bits */ -#define CS_IE_DCOR_OPNIE_OFS ( 6) /*!< DCOR_OPNIE Bit Offset */ -#define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag interrupt enable. */ -/* CS_IE[FCNTLFIE] Bits */ -#define CS_IE_FCNTLFIE_OFS ( 8) /*!< FCNTLFIE Bit Offset */ -#define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /*!< Start fault counter interrupt enable LFXT */ -/* CS_IE[FCNTHFIE] Bits */ -#define CS_IE_FCNTHFIE_OFS ( 9) /*!< FCNTHFIE Bit Offset */ -#define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /*!< Start fault counter interrupt enable HFXT */ -/* CS_IFG[LFXTIFG] Bits */ -#define CS_IFG_LFXTIFG_OFS ( 0) /*!< LFXTIFG Bit Offset */ -#define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag */ -/* CS_IFG[HFXTIFG] Bits */ -#define CS_IFG_HFXTIFG_OFS ( 1) /*!< HFXTIFG Bit Offset */ -#define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag */ -/* CS_IFG[DCOR_SHTIFG] Bits */ -#define CS_IFG_DCOR_SHTIFG_OFS ( 5) /*!< DCOR_SHTIFG Bit Offset */ -#define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /*!< DCO external resistor short circuit fault flag. */ -/* CS_IFG[DCOR_OPNIFG] Bits */ -#define CS_IFG_DCOR_OPNIFG_OFS ( 6) /*!< DCOR_OPNIFG Bit Offset */ -#define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag. */ -/* CS_IFG[FCNTLFIFG] Bits */ -#define CS_IFG_FCNTLFIFG_OFS ( 8) /*!< FCNTLFIFG Bit Offset */ -#define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter interrupt flag LFXT */ -/* CS_IFG[FCNTHFIFG] Bits */ -#define CS_IFG_FCNTHFIFG_OFS ( 9) /*!< FCNTHFIFG Bit Offset */ -#define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter interrupt flag HFXT */ -/* CS_CLRIFG[CLR_LFXTIFG] Bits */ -#define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /*!< CLR_LFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /*!< Clear LFXT oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_HFXTIFG] Bits */ -#define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /*!< CLR_HFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /*!< Clear HFXT oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /*!< CLR_DCOR_OPNIFG Bit Offset */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Clear DCO external resistor open circuit fault interrupt flag. */ -/* CS_CLRIFG[CLR_FCNTLFIFG] Bits */ -#define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /*!< CLR_FCNTLFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter clear interrupt flag LFXT */ -/* CS_CLRIFG[CLR_FCNTHFIFG] Bits */ -#define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /*!< CLR_FCNTHFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter clear interrupt flag HFXT */ -/* CS_SETIFG[SET_LFXTIFG] Bits */ -#define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /*!< SET_LFXTIFG Bit Offset */ -#define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /*!< Set LFXT oscillator fault interrupt flag */ -/* CS_SETIFG[SET_HFXTIFG] Bits */ -#define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /*!< SET_HFXTIFG Bit Offset */ -#define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /*!< Set HFXT oscillator fault interrupt flag */ -/* CS_SETIFG[SET_DCOR_OPNIFG] Bits */ -#define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /*!< SET_DCOR_OPNIFG Bit Offset */ -#define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Set DCO external resistor open circuit fault interrupt flag. */ -/* CS_SETIFG[SET_FCNTHFIFG] Bits */ -#define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /*!< SET_FCNTHFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter set interrupt flag HFXT */ -/* CS_SETIFG[SET_FCNTLFIFG] Bits */ -#define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /*!< SET_FCNTLFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter set interrupt flag LFXT */ -/* CS_DCOERCAL0[DCO_TCCAL] Bits */ -#define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /*!< DCO_TCCAL Bit Offset */ -#define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /*!< DCO_TCCAL Bit Mask */ -/* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /*!< DCO_FCAL_RSEL04 Bit Offset */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /*!< DCO_FCAL_RSEL04 Bit Mask */ -/* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /*!< DCO_FCAL_RSEL5 Bit Offset */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /*!< DCO_FCAL_RSEL5 Bit Mask */ -/* Pre-defined bitfield values */ -#define CS_KEY_VAL ((uint32_t)0x0000695A) /*!< CS control key value */ - -/****************************************************************************** -* DIO Bits -******************************************************************************/ -/* DIO_IV[IV] Bits */ -#define DIO_PORT_IV_OFS ( 0) /*!< DIO Port IV Bit Offset */ -#define DIO_PORT_IV_MASK ((uint16_t)0x001F) /*!< DIO Port IV Bit Mask */ -#define DIO_PORT_IV0 ((uint16_t)0x0001) /*!< DIO Port IV Bit 0 */ -#define DIO_PORT_IV1 ((uint16_t)0x0002) /*!< DIO Port IV Bit 1 */ -#define DIO_PORT_IV2 ((uint16_t)0x0004) /*!< DIO Port IV Bit 2 */ -#define DIO_PORT_IV3 ((uint16_t)0x0008) /*!< DIO Port IV Bit 3 */ -#define DIO_PORT_IV4 ((uint16_t)0x0010) /*!< DIO Port IV Bit 4 */ -#define DIO_PORT_IV_0 ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV_2 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ - /* Priority: Highest */ -#define DIO_PORT_IV_4 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV_6 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV_8 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV_10 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV_12 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV_14 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV_16 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ - /* Priority: Lowest */ -#define DIO_PORT_IV__NONE ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ - /* Priority: Highest */ -#define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ - /* Priority: Lowest */ - - -/****************************************************************************** -* DMA Bits -******************************************************************************/ -/* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /*!< NUM_DMA_CHANNELS Bit Offset */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /*!< NUM_DMA_CHANNELS Bit Mask */ -/* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /*!< NUM_SRC_PER_CHANNEL Bit Offset */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /*!< NUM_SRC_PER_CHANNEL Bit Mask */ -/* DMA_SW_CHTRIG[CH0] Bits */ -#define DMA_SW_CHTRIG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /*!< Write 1, triggers DMA_CHANNEL0 */ -/* DMA_SW_CHTRIG[CH1] Bits */ -#define DMA_SW_CHTRIG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /*!< Write 1, triggers DMA_CHANNEL1 */ -/* DMA_SW_CHTRIG[CH2] Bits */ -#define DMA_SW_CHTRIG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /*!< Write 1, triggers DMA_CHANNEL2 */ -/* DMA_SW_CHTRIG[CH3] Bits */ -#define DMA_SW_CHTRIG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /*!< Write 1, triggers DMA_CHANNEL3 */ -/* DMA_SW_CHTRIG[CH4] Bits */ -#define DMA_SW_CHTRIG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /*!< Write 1, triggers DMA_CHANNEL4 */ -/* DMA_SW_CHTRIG[CH5] Bits */ -#define DMA_SW_CHTRIG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /*!< Write 1, triggers DMA_CHANNEL5 */ -/* DMA_SW_CHTRIG[CH6] Bits */ -#define DMA_SW_CHTRIG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /*!< Write 1, triggers DMA_CHANNEL6 */ -/* DMA_SW_CHTRIG[CH7] Bits */ -#define DMA_SW_CHTRIG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /*!< Write 1, triggers DMA_CHANNEL7 */ -/* DMA_SW_CHTRIG[CH8] Bits */ -#define DMA_SW_CHTRIG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /*!< Write 1, triggers DMA_CHANNEL8 */ -/* DMA_SW_CHTRIG[CH9] Bits */ -#define DMA_SW_CHTRIG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /*!< Write 1, triggers DMA_CHANNEL9 */ -/* DMA_SW_CHTRIG[CH10] Bits */ -#define DMA_SW_CHTRIG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /*!< Write 1, triggers DMA_CHANNEL10 */ -/* DMA_SW_CHTRIG[CH11] Bits */ -#define DMA_SW_CHTRIG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /*!< Write 1, triggers DMA_CHANNEL11 */ -/* DMA_SW_CHTRIG[CH12] Bits */ -#define DMA_SW_CHTRIG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /*!< Write 1, triggers DMA_CHANNEL12 */ -/* DMA_SW_CHTRIG[CH13] Bits */ -#define DMA_SW_CHTRIG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /*!< Write 1, triggers DMA_CHANNEL13 */ -/* DMA_SW_CHTRIG[CH14] Bits */ -#define DMA_SW_CHTRIG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /*!< Write 1, triggers DMA_CHANNEL14 */ -/* DMA_SW_CHTRIG[CH15] Bits */ -#define DMA_SW_CHTRIG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /*!< Write 1, triggers DMA_CHANNEL15 */ -/* DMA_SW_CHTRIG[CH16] Bits */ -#define DMA_SW_CHTRIG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /*!< Write 1, triggers DMA_CHANNEL16 */ -/* DMA_SW_CHTRIG[CH17] Bits */ -#define DMA_SW_CHTRIG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /*!< Write 1, triggers DMA_CHANNEL17 */ -/* DMA_SW_CHTRIG[CH18] Bits */ -#define DMA_SW_CHTRIG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /*!< Write 1, triggers DMA_CHANNEL18 */ -/* DMA_SW_CHTRIG[CH19] Bits */ -#define DMA_SW_CHTRIG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /*!< Write 1, triggers DMA_CHANNEL19 */ -/* DMA_SW_CHTRIG[CH20] Bits */ -#define DMA_SW_CHTRIG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /*!< Write 1, triggers DMA_CHANNEL20 */ -/* DMA_SW_CHTRIG[CH21] Bits */ -#define DMA_SW_CHTRIG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /*!< Write 1, triggers DMA_CHANNEL21 */ -/* DMA_SW_CHTRIG[CH22] Bits */ -#define DMA_SW_CHTRIG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /*!< Write 1, triggers DMA_CHANNEL22 */ -/* DMA_SW_CHTRIG[CH23] Bits */ -#define DMA_SW_CHTRIG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /*!< Write 1, triggers DMA_CHANNEL23 */ -/* DMA_SW_CHTRIG[CH24] Bits */ -#define DMA_SW_CHTRIG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /*!< Write 1, triggers DMA_CHANNEL24 */ -/* DMA_SW_CHTRIG[CH25] Bits */ -#define DMA_SW_CHTRIG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /*!< Write 1, triggers DMA_CHANNEL25 */ -/* DMA_SW_CHTRIG[CH26] Bits */ -#define DMA_SW_CHTRIG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /*!< Write 1, triggers DMA_CHANNEL26 */ -/* DMA_SW_CHTRIG[CH27] Bits */ -#define DMA_SW_CHTRIG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /*!< Write 1, triggers DMA_CHANNEL27 */ -/* DMA_SW_CHTRIG[CH28] Bits */ -#define DMA_SW_CHTRIG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /*!< Write 1, triggers DMA_CHANNEL28 */ -/* DMA_SW_CHTRIG[CH29] Bits */ -#define DMA_SW_CHTRIG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /*!< Write 1, triggers DMA_CHANNEL29 */ -/* DMA_SW_CHTRIG[CH30] Bits */ -#define DMA_SW_CHTRIG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /*!< Write 1, triggers DMA_CHANNEL30 */ -/* DMA_SW_CHTRIG[CH31] Bits */ -#define DMA_SW_CHTRIG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /*!< Write 1, triggers DMA_CHANNEL31 */ -/* DMA_CHN_SRCCFG[DMA_SRC] Bits */ -#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /*!< DMA_SRC Bit Offset */ -#define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /*!< DMA_SRC Bit Mask */ -/* DMA_INT1_SRCCFG[INT_SRC] Bits */ -#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT1_SRCCFG[EN] Bits */ -#define DMA_INT1_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT1 mapping */ -/* DMA_INT2_SRCCFG[INT_SRC] Bits */ -#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT2_SRCCFG[EN] Bits */ -#define DMA_INT2_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT2 mapping */ -/* DMA_INT3_SRCCFG[INT_SRC] Bits */ -#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT3_SRCCFG[EN] Bits */ -#define DMA_INT3_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT3 mapping */ -/* DMA_INT0_SRCFLG[CH0] Bits */ -#define DMA_INT0_SRCFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /*!< Channel 0 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH1] Bits */ -#define DMA_INT0_SRCFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /*!< Channel 1 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH2] Bits */ -#define DMA_INT0_SRCFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /*!< Channel 2 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH3] Bits */ -#define DMA_INT0_SRCFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /*!< Channel 3 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH4] Bits */ -#define DMA_INT0_SRCFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /*!< Channel 4 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH5] Bits */ -#define DMA_INT0_SRCFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /*!< Channel 5 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH6] Bits */ -#define DMA_INT0_SRCFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /*!< Channel 6 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH7] Bits */ -#define DMA_INT0_SRCFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /*!< Channel 7 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH8] Bits */ -#define DMA_INT0_SRCFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /*!< Channel 8 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH9] Bits */ -#define DMA_INT0_SRCFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /*!< Channel 9 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH10] Bits */ -#define DMA_INT0_SRCFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /*!< Channel 10 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH11] Bits */ -#define DMA_INT0_SRCFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /*!< Channel 11 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH12] Bits */ -#define DMA_INT0_SRCFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /*!< Channel 12 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH13] Bits */ -#define DMA_INT0_SRCFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /*!< Channel 13 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH14] Bits */ -#define DMA_INT0_SRCFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /*!< Channel 14 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH15] Bits */ -#define DMA_INT0_SRCFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /*!< Channel 15 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH16] Bits */ -#define DMA_INT0_SRCFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /*!< Channel 16 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH17] Bits */ -#define DMA_INT0_SRCFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /*!< Channel 17 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH18] Bits */ -#define DMA_INT0_SRCFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /*!< Channel 18 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH19] Bits */ -#define DMA_INT0_SRCFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /*!< Channel 19 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH20] Bits */ -#define DMA_INT0_SRCFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /*!< Channel 20 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH21] Bits */ -#define DMA_INT0_SRCFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /*!< Channel 21 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH22] Bits */ -#define DMA_INT0_SRCFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /*!< Channel 22 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH23] Bits */ -#define DMA_INT0_SRCFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /*!< Channel 23 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH24] Bits */ -#define DMA_INT0_SRCFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /*!< Channel 24 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH25] Bits */ -#define DMA_INT0_SRCFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /*!< Channel 25 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH26] Bits */ -#define DMA_INT0_SRCFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /*!< Channel 26 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH27] Bits */ -#define DMA_INT0_SRCFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /*!< Channel 27 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH28] Bits */ -#define DMA_INT0_SRCFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /*!< Channel 28 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH29] Bits */ -#define DMA_INT0_SRCFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /*!< Channel 29 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH30] Bits */ -#define DMA_INT0_SRCFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /*!< Channel 30 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH31] Bits */ -#define DMA_INT0_SRCFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /*!< Channel 31 was the source of DMA_INT0 */ -/* DMA_INT0_CLRFLG[CH0] Bits */ -#define DMA_INT0_CLRFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH1] Bits */ -#define DMA_INT0_CLRFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH2] Bits */ -#define DMA_INT0_CLRFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH3] Bits */ -#define DMA_INT0_CLRFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH4] Bits */ -#define DMA_INT0_CLRFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH5] Bits */ -#define DMA_INT0_CLRFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH6] Bits */ -#define DMA_INT0_CLRFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH7] Bits */ -#define DMA_INT0_CLRFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH8] Bits */ -#define DMA_INT0_CLRFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH9] Bits */ -#define DMA_INT0_CLRFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH10] Bits */ -#define DMA_INT0_CLRFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH11] Bits */ -#define DMA_INT0_CLRFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH12] Bits */ -#define DMA_INT0_CLRFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH13] Bits */ -#define DMA_INT0_CLRFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH14] Bits */ -#define DMA_INT0_CLRFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH15] Bits */ -#define DMA_INT0_CLRFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH16] Bits */ -#define DMA_INT0_CLRFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH17] Bits */ -#define DMA_INT0_CLRFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH18] Bits */ -#define DMA_INT0_CLRFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH19] Bits */ -#define DMA_INT0_CLRFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH20] Bits */ -#define DMA_INT0_CLRFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH21] Bits */ -#define DMA_INT0_CLRFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH22] Bits */ -#define DMA_INT0_CLRFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH23] Bits */ -#define DMA_INT0_CLRFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH24] Bits */ -#define DMA_INT0_CLRFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH25] Bits */ -#define DMA_INT0_CLRFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH26] Bits */ -#define DMA_INT0_CLRFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH27] Bits */ -#define DMA_INT0_CLRFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH28] Bits */ -#define DMA_INT0_CLRFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH29] Bits */ -#define DMA_INT0_CLRFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH30] Bits */ -#define DMA_INT0_CLRFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH31] Bits */ -#define DMA_INT0_CLRFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_STAT[MASTEN] Bits */ -#define DMA_STAT_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_STAT_MASTEN ((uint32_t)0x00000001) -/* DMA_STAT[STATE] Bits */ -#define DMA_STAT_STATE_OFS ( 4) /*!< STATE Bit Offset */ -#define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /*!< STATE Bit Mask */ -#define DMA_STAT_STATE0 ((uint32_t)0x00000010) /*!< STATE Bit 0 */ -#define DMA_STAT_STATE1 ((uint32_t)0x00000020) /*!< STATE Bit 1 */ -#define DMA_STAT_STATE2 ((uint32_t)0x00000040) /*!< STATE Bit 2 */ -#define DMA_STAT_STATE3 ((uint32_t)0x00000080) /*!< STATE Bit 3 */ -#define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /*!< idle */ -#define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /*!< reading channel controller data */ -#define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /*!< reading source data end pointer */ -#define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /*!< reading destination data end pointer */ -#define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /*!< reading source data */ -#define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /*!< writing destination data */ -#define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /*!< waiting for DMA request to clear */ -#define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /*!< writing channel controller data */ -#define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /*!< stalled */ -#define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /*!< done */ -#define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /*!< peripheral scatter-gather transition */ -#define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /*!< Reserved */ -#define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /*!< Reserved */ -#define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /*!< Reserved */ -#define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /*!< Reserved */ -#define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /*!< Reserved */ -/* DMA_STAT[DMACHANS] Bits */ -#define DMA_STAT_DMACHANS_OFS (16) /*!< DMACHANS Bit Offset */ -#define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /*!< DMACHANS Bit Mask */ -#define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /*!< DMACHANS Bit 0 */ -#define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /*!< DMACHANS Bit 1 */ -#define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /*!< DMACHANS Bit 2 */ -#define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /*!< DMACHANS Bit 3 */ -#define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /*!< DMACHANS Bit 4 */ -#define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /*!< Controller configured to use 1 DMA channel */ -#define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /*!< Controller configured to use 2 DMA channels */ -#define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /*!< Controller configured to use 31 DMA channels */ -#define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /*!< Controller configured to use 32 DMA channels */ -/* DMA_STAT[TESTSTAT] Bits */ -#define DMA_STAT_TESTSTAT_OFS (28) /*!< TESTSTAT Bit Offset */ -#define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /*!< TESTSTAT Bit Mask */ -#define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /*!< TESTSTAT Bit 0 */ -#define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /*!< TESTSTAT Bit 1 */ -#define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /*!< TESTSTAT Bit 2 */ -#define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /*!< TESTSTAT Bit 3 */ -#define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /*!< Controller does not include the integration test logic */ -#define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /*!< Controller includes the integration test logic */ -/* DMA_CFG[MASTEN] Bits */ -#define DMA_CFG_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_CFG_MASTEN ((uint32_t)0x00000001) -/* DMA_CFG[CHPROTCTRL] Bits */ -#define DMA_CFG_CHPROTCTRL_OFS ( 5) /*!< CHPROTCTRL Bit Offset */ -#define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /*!< CHPROTCTRL Bit Mask */ -/* DMA_CTLBASE[ADDR] Bits */ -#define DMA_CTLBASE_ADDR_OFS ( 5) /*!< ADDR Bit Offset */ -#define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /*!< ADDR Bit Mask */ -/* DMA_ERRCLR[ERRCLR] Bits */ -#define DMA_ERRCLR_ERRCLR_OFS ( 0) /*!< ERRCLR Bit Offset */ -#define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) -/* DMA channel definitions and memory structure alignment */ -#define __MCU_NUM_DMA_CHANNELS__ 8 -#define DMA_CHANNEL_CONTROL_STRUCT_SIZE 0x10 -#define DMA_CONTROL_MEMORY_ALIGNMENT (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE) - -/* UDMA_STAT Control Bits */ -#define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /*!< Available uDMA Channels Minus 1 */ -#define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /*!< Control State Machine Status */ -#define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /*!< Idle */ -#define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /*!< Reading channel controller data */ -#define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /*!< Reading source end pointer */ -#define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /*!< Reading destination end pointer */ -#define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /*!< Reading source data */ -#define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /*!< Writing destination data */ -#define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /*!< Waiting for uDMA request to clear */ -#define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /*!< Writing channel controller data */ -#define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /*!< Stalled */ -#define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /*!< Done */ -#define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /*!< Undefined */ -#define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /*!< Master Enable Status */ -#define UDMA_STAT_DMACHANS_S (16) - -/* UDMA_CFG Control Bits */ -#define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /*!< Controller Master Enable */ - -/* UDMA_CTLBASE Control Bits */ -#define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /*!< Channel Control Base Address */ -#define UDMA_CTLBASE_ADDR_S (10) - -/* UDMA_ALTBASE Control Bits */ -#define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Alternate Channel Address Pointer */ -#define UDMA_ALTBASE_ADDR_S ( 0) - -/* UDMA_WAITSTAT Control Bits */ -#define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Wait Status */ - -/* UDMA_SWREQ Control Bits */ -#define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Software Request */ - -/* UDMA_USEBURSTSET Control Bits */ -#define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Set */ - -/* UDMA_USEBURSTCLR Control Bits */ -#define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Clear */ - -/* UDMA_REQMASKSET Control Bits */ -#define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Set */ - -/* UDMA_REQMASKCLR Control Bits */ -#define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Clear */ - -/* UDMA_ENASET Control Bits */ -#define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Enable Set */ - -/* UDMA_ENACLR Control Bits */ -#define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Clear Channel [n] Enable Clear */ - -/* UDMA_ALTSET Control Bits */ -#define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Set */ - -/* UDMA_ALTCLR Control Bits */ -#define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Clear */ - -/* UDMA_PRIOSET Control Bits */ -#define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Set */ - -/* UDMA_PRIOCLR Control Bits */ -#define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Clear */ - -/* UDMA_ERRCLR Control Bits */ -#define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /*!< uDMA Bus Error Status */ - -/* UDMA_CHASGN Control Bits */ -#define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Assignment Select */ -#define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /*!< Use the primary channel assignment */ -#define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /*!< Use the secondary channel assignment */ - -/* Micro Direct Memory Access (uDMA) offsets */ -#define UDMA_O_SRCENDP ((uint32_t)0x00000000) /*!< DMA Channel Source Address End Pointer */ -#define UDMA_O_DSTENDP ((uint32_t)0x00000004) /*!< DMA Channel Destination Address End Pointer */ -#define UDMA_O_CHCTL ((uint32_t)0x00000008) /*!< DMA Channel Control Word */ - -/* UDMA_O_SRCENDP Control Bits */ -#define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Source Address End Pointer */ -#define UDMA_SRCENDP_ADDR_S ( 0) - -/* UDMA_O_DSTENDP Control Bits */ -#define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Destination Address End Pointer */ -#define UDMA_DSTENDP_ADDR_S ( 0) - -/* UDMA_O_CHCTL Control Bits */ -#define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /*!< Destination Address Increment */ -#define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /*!< Word */ -#define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /*!< No increment */ -#define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /*!< Destination Data Size */ -#define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /*!< Source Address Increment */ -#define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /*!< No increment */ -#define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /*!< Source Data Size */ -#define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /*!< Word */ -#define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /*!< Arbitration Size */ -#define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /*!< 1 Transfer */ -#define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /*!< 2 Transfers */ -#define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /*!< 4 Transfers */ -#define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /*!< 8 Transfers */ -#define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /*!< 16 Transfers */ -#define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /*!< 32 Transfers */ -#define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /*!< 64 Transfers */ -#define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /*!< 128 Transfers */ -#define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /*!< 256 Transfers */ -#define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /*!< 512 Transfers */ -#define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /*!< 1024 Transfers */ -#define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /*!< Transfer Size (minus 1) */ -#define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /*!< Next Useburst */ -#define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /*!< uDMA Transfer Mode */ -#define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /*!< Stop */ -#define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /*!< Basic */ -#define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /*!< Auto-Request */ -#define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /*!< Ping-Pong */ -#define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /*!< Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /*!< Alternate Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /*!< Peripheral Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /*!< Alternate Peripheral Scatter-Gather */ - -#define UDMA_CHCTL_XFERSIZE_S ( 4) - - -/****************************************************************************** -* DWT Bits -******************************************************************************/ - - -/****************************************************************************** -* EUSCI_A Bits -******************************************************************************/ -/* EUSCI_A_CTLW0[SWRST] Bits */ -#define EUSCI_A_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -/* EUSCI_A_CTLW0[TXBRK] Bits */ -#define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /*!< UCTXBRK Bit Offset */ -#define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /*!< Transmit break */ -/* EUSCI_A_CTLW0[TXADDR] Bits */ -#define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /*!< UCTXADDR Bit Offset */ -#define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /*!< Transmit address */ -/* EUSCI_A_CTLW0[DORM] Bits */ -#define EUSCI_A_CTLW0_DORM_OFS ( 3) /*!< UCDORM Bit Offset */ -#define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /*!< Dormant */ -/* EUSCI_A_CTLW0[BRKIE] Bits */ -#define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /*!< UCBRKIE Bit Offset */ -#define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /*!< Receive break character interrupt enable */ -/* EUSCI_A_CTLW0[RXEIE] Bits */ -#define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /*!< UCRXEIE Bit Offset */ -#define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /*!< Receive erroneous-character interrupt enable */ -/* EUSCI_A_CTLW0[SSEL] Bits */ -#define EUSCI_A_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -/* EUSCI_A_CTLW0[SYNC] Bits */ -#define EUSCI_A_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -/* EUSCI_A_CTLW0[MODE] Bits */ -#define EUSCI_A_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< UART mode */ -#define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< Idle-line multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< Address-bit multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< UART mode with automatic baud-rate detection */ -/* EUSCI_A_CTLW0[SPB] Bits */ -#define EUSCI_A_CTLW0_SPB_OFS (11) /*!< UCSPB Bit Offset */ -#define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /*!< Stop bit select */ -/* EUSCI_A_CTLW0[SEVENBIT] Bits */ -#define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -/* EUSCI_A_CTLW0[MSB] Bits */ -#define EUSCI_A_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -/* EUSCI_A_CTLW0[PAR] Bits */ -#define EUSCI_A_CTLW0_PAR_OFS (14) /*!< UCPAR Bit Offset */ -#define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /*!< Parity select */ -/* EUSCI_A_CTLW0[PEN] Bits */ -#define EUSCI_A_CTLW0_PEN_OFS (15) /*!< UCPEN Bit Offset */ -#define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /*!< Parity enable */ -/* EUSCI_A_CTLW0[STEM] Bits */ -#define EUSCI_A_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -/* EUSCI_A_CTLW0[MST] Bits */ -#define EUSCI_A_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -/* EUSCI_A_CTLW0[CKPL] Bits */ -#define EUSCI_A_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -/* EUSCI_A_CTLW0[CKPH] Bits */ -#define EUSCI_A_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -/* EUSCI_A_CTLW1[GLIT] Bits */ -#define EUSCI_A_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< Approximately 2 ns (equivalent of 1 delay element) */ -#define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< Approximately 50 ns */ -#define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< Approximately 100 ns */ -#define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< Approximately 200 ns */ -/* EUSCI_A_MCTLW[OS16] Bits */ -#define EUSCI_A_MCTLW_OS16_OFS ( 0) /*!< UCOS16 Bit Offset */ -#define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /*!< Oversampling mode enabled */ -/* EUSCI_A_MCTLW[BRF] Bits */ -#define EUSCI_A_MCTLW_BRF_OFS ( 4) /*!< UCBRF Bit Offset */ -#define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /*!< UCBRF Bit Mask */ -/* EUSCI_A_MCTLW[BRS] Bits */ -#define EUSCI_A_MCTLW_BRS_OFS ( 8) /*!< UCBRS Bit Offset */ -#define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /*!< UCBRS Bit Mask */ -/* EUSCI_A_STATW[BUSY] Bits */ -#define EUSCI_A_STATW_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -/* EUSCI_A_STATW[ADDR_IDLE] Bits */ -#define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /*!< UCADDR_UCIDLE Bit Offset */ -#define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /*!< Address received / Idle line detected */ -/* EUSCI_A_STATW[RXERR] Bits */ -#define EUSCI_A_STATW_RXERR_OFS ( 2) /*!< UCRXERR Bit Offset */ -#define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /*!< Receive error flag */ -/* EUSCI_A_STATW[BRK] Bits */ -#define EUSCI_A_STATW_BRK_OFS ( 3) /*!< UCBRK Bit Offset */ -#define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /*!< Break detect flag */ -/* EUSCI_A_STATW[PE] Bits */ -#define EUSCI_A_STATW_PE_OFS ( 4) /*!< UCPE Bit Offset */ -#define EUSCI_A_STATW_PE ((uint16_t)0x0010) -/* EUSCI_A_STATW[OE] Bits */ -#define EUSCI_A_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_A_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -/* EUSCI_A_STATW[FE] Bits */ -#define EUSCI_A_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_A_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -/* EUSCI_A_STATW[LISTEN] Bits */ -#define EUSCI_A_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -/* EUSCI_A_STATW[SPI_BUSY] Bits */ -#define EUSCI_A_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -/* EUSCI_A_RXBUF[RXBUF] Bits */ -#define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -/* EUSCI_A_TXBUF[TXBUF] Bits */ -#define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -/* EUSCI_A_ABCTL[ABDEN] Bits */ -#define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /*!< UCABDEN Bit Offset */ -#define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /*!< Automatic baud-rate detect enable */ -/* EUSCI_A_ABCTL[BTOE] Bits */ -#define EUSCI_A_ABCTL_BTOE_OFS ( 2) /*!< UCBTOE Bit Offset */ -#define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /*!< Break time out error */ -/* EUSCI_A_ABCTL[STOE] Bits */ -#define EUSCI_A_ABCTL_STOE_OFS ( 3) /*!< UCSTOE Bit Offset */ -#define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /*!< Synch field time out error */ -/* EUSCI_A_ABCTL[DELIM] Bits */ -#define EUSCI_A_ABCTL_DELIM_OFS ( 4) /*!< UCDELIM Bit Offset */ -#define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /*!< UCDELIM Bit Mask */ -#define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /*!< DELIM Bit 0 */ -#define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /*!< DELIM Bit 1 */ -#define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /*!< 1 bit time */ -#define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /*!< 2 bit times */ -#define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /*!< 3 bit times */ -#define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /*!< 4 bit times */ -/* EUSCI_A_IRCTL[IREN] Bits */ -#define EUSCI_A_IRCTL_IREN_OFS ( 0) /*!< UCIREN Bit Offset */ -#define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /*!< IrDA encoder/decoder enable */ -/* EUSCI_A_IRCTL[IRTXCLK] Bits */ -#define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /*!< UCIRTXCLK Bit Offset */ -#define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /*!< IrDA transmit pulse clock select */ -/* EUSCI_A_IRCTL[IRTXPL] Bits */ -#define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /*!< UCIRTXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /*!< UCIRTXPL Bit Mask */ -/* EUSCI_A_IRCTL[IRRXFE] Bits */ -#define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /*!< UCIRRXFE Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /*!< IrDA receive filter enabled */ -/* EUSCI_A_IRCTL[IRRXPL] Bits */ -#define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /*!< UCIRRXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /*!< IrDA receive input UCAxRXD polarity */ -/* EUSCI_A_IRCTL[IRRXFL] Bits */ -#define EUSCI_A_IRCTL_IRRXFL_OFS (10) /*!< UCIRRXFL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /*!< UCIRRXFL Bit Mask */ -/* EUSCI_A_IE[RXIE] Bits */ -#define EUSCI_A_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -/* EUSCI_A_IE[TXIE] Bits */ -#define EUSCI_A_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -/* EUSCI_A_IE[STTIE] Bits */ -#define EUSCI_A_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /*!< Start bit interrupt enable */ -/* EUSCI_A_IE[TXCPTIE] Bits */ -#define EUSCI_A_IE_TXCPTIE_OFS ( 3) /*!< UCTXCPTIE Bit Offset */ -#define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /*!< Transmit complete interrupt enable */ -/* EUSCI_A_IFG[RXIFG] Bits */ -#define EUSCI_A_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -/* EUSCI_A_IFG[TXIFG] Bits */ -#define EUSCI_A_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -/* EUSCI_A_IFG[STTIFG] Bits */ -#define EUSCI_A_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /*!< Start bit interrupt flag */ -/* EUSCI_A_IFG[TXCPTIFG] Bits */ -#define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /*!< UCTXCPTIFG Bit Offset */ -#define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /*!< Transmit ready interrupt enable */ -/* legacy definitions for backward compatibility to version 2100 */ -#define EUSCI_A__RXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_A__RXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_A__TXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_A__TXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ - - -/****************************************************************************** -* EUSCI_B Bits -******************************************************************************/ -/* EUSCI_B_CTLW0[SWRST] Bits */ -#define EUSCI_B_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -/* EUSCI_B_CTLW0[TXSTT] Bits */ -#define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /*!< UCTXSTT Bit Offset */ -#define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /*!< Transmit START condition in master mode */ -/* EUSCI_B_CTLW0[TXSTP] Bits */ -#define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /*!< UCTXSTP Bit Offset */ -#define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /*!< Transmit STOP condition in master mode */ -/* EUSCI_B_CTLW0[TXNACK] Bits */ -#define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /*!< UCTXNACK Bit Offset */ -#define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /*!< Transmit a NACK */ -/* EUSCI_B_CTLW0[TR] Bits */ -#define EUSCI_B_CTLW0_TR_OFS ( 4) /*!< UCTR Bit Offset */ -#define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /*!< Transmitter/receiver */ -/* EUSCI_B_CTLW0[TXACK] Bits */ -#define EUSCI_B_CTLW0_TXACK_OFS ( 5) /*!< UCTXACK Bit Offset */ -#define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /*!< Transmit ACK condition in slave mode */ -/* EUSCI_B_CTLW0[SSEL] Bits */ -#define EUSCI_B_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_B_CTLW0_UCSSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ -#define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -/* EUSCI_B_CTLW0[SYNC] Bits */ -#define EUSCI_B_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -/* EUSCI_B_CTLW0[MODE] Bits */ -#define EUSCI_B_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< 3-pin SPI */ -#define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< 4-pin SPI (master or slave enabled if STE = 1) */ -#define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< 4-pin SPI (master or slave enabled if STE = 0) */ -#define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< I2C mode */ -/* EUSCI_B_CTLW0[MST] Bits */ -#define EUSCI_B_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -/* EUSCI_B_CTLW0[MM] Bits */ -#define EUSCI_B_CTLW0_MM_OFS (13) /*!< UCMM Bit Offset */ -#define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /*!< Multi-master environment select */ -/* EUSCI_B_CTLW0[SLA10] Bits */ -#define EUSCI_B_CTLW0_SLA10_OFS (14) /*!< UCSLA10 Bit Offset */ -#define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /*!< Slave addressing mode select */ -/* EUSCI_B_CTLW0[A10] Bits */ -#define EUSCI_B_CTLW0_A10_OFS (15) /*!< UCA10 Bit Offset */ -#define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /*!< Own addressing mode select */ -/* EUSCI_B_CTLW0[STEM] Bits */ -#define EUSCI_B_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -/* EUSCI_B_CTLW0[SEVENBIT] Bits */ -#define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -/* EUSCI_B_CTLW0[MSB] Bits */ -#define EUSCI_B_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -/* EUSCI_B_CTLW0[CKPL] Bits */ -#define EUSCI_B_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -/* EUSCI_B_CTLW0[CKPH] Bits */ -#define EUSCI_B_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -/* EUSCI_B_CTLW1[GLIT] Bits */ -#define EUSCI_B_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< 50 ns */ -#define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< 25 ns */ -#define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< 12.5 ns */ -#define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< 6.25 ns */ -/* EUSCI_B_CTLW1[ASTP] Bits */ -#define EUSCI_B_CTLW1_ASTP_OFS ( 2) /*!< UCASTP Bit Offset */ -#define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /*!< UCASTP Bit Mask */ -#define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /*!< ASTP Bit 0 */ -#define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /*!< ASTP Bit 1 */ -#define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /*!< No automatic STOP generation. The STOP condition is generated after the user */ - /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ -#define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ - /* UCBxTBCNT */ -#define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /*!< A STOP condition is generated automatically after the byte counter value */ - /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ - /* threshold */ -/* EUSCI_B_CTLW1[SWACK] Bits */ -#define EUSCI_B_CTLW1_SWACK_OFS ( 4) /*!< UCSWACK Bit Offset */ -#define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /*!< SW or HW ACK control */ -/* EUSCI_B_CTLW1[STPNACK] Bits */ -#define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /*!< UCSTPNACK Bit Offset */ -#define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /*!< ACK all master bytes */ -/* EUSCI_B_CTLW1[CLTO] Bits */ -#define EUSCI_B_CTLW1_CLTO_OFS ( 6) /*!< UCCLTO Bit Offset */ -#define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /*!< UCCLTO Bit Mask */ -#define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /*!< CLTO Bit 0 */ -#define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /*!< CLTO Bit 1 */ -#define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /*!< Disable clock low timeout counter */ -#define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ -#define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ -#define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ -/* EUSCI_B_CTLW1[ETXINT] Bits */ -#define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /*!< UCETXINT Bit Offset */ -#define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /*!< Early UCTXIFG0 */ -/* EUSCI_B_STATW[BBUSY] Bits */ -#define EUSCI_B_STATW_BBUSY_OFS ( 4) /*!< UCBBUSY Bit Offset */ -#define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /*!< Bus busy */ -/* EUSCI_B_STATW[GC] Bits */ -#define EUSCI_B_STATW_GC_OFS ( 5) /*!< UCGC Bit Offset */ -#define EUSCI_B_STATW_GC ((uint16_t)0x0020) /*!< General call address received */ -/* EUSCI_B_STATW[SCLLOW] Bits */ -#define EUSCI_B_STATW_SCLLOW_OFS ( 6) /*!< UCSCLLOW Bit Offset */ -#define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /*!< SCL low */ -/* EUSCI_B_STATW[BCNT] Bits */ -#define EUSCI_B_STATW_BCNT_OFS ( 8) /*!< UCBCNT Bit Offset */ -#define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /*!< UCBCNT Bit Mask */ -/* EUSCI_B_STATW[SPI_BUSY] Bits */ -#define EUSCI_B_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_B_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_B busy */ -/* EUSCI_B_STATW[OE] Bits */ -#define EUSCI_B_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_B_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -/* EUSCI_B_STATW[FE] Bits */ -#define EUSCI_B_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_B_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -/* EUSCI_B_STATW[LISTEN] Bits */ -#define EUSCI_B_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -/* EUSCI_B_TBCNT[TBCNT] Bits */ -#define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /*!< UCTBCNT Bit Offset */ -#define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /*!< UCTBCNT Bit Mask */ -/* EUSCI_B_RXBUF[RXBUF] Bits */ -#define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -/* EUSCI_B_TXBUF[TXBUF] Bits */ -#define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -/* EUSCI_B_I2COA0[I2COA0] Bits */ -#define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /*!< I2COA0 Bit Offset */ -#define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /*!< I2COA0 Bit Mask */ -/* EUSCI_B_I2COA0[OAEN] Bits */ -#define EUSCI_B_I2COA0_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA0[GCEN] Bits */ -#define EUSCI_B_I2COA0_GCEN_OFS (15) /*!< UCGCEN Bit Offset */ -#define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /*!< General call response enable */ -/* EUSCI_B_I2COA1[I2COA1] Bits */ -#define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /*!< I2COA1 Bit Offset */ -#define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /*!< I2COA1 Bit Mask */ -/* EUSCI_B_I2COA1[OAEN] Bits */ -#define EUSCI_B_I2COA1_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA2[I2COA2] Bits */ -#define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /*!< I2COA2 Bit Offset */ -#define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /*!< I2COA2 Bit Mask */ -/* EUSCI_B_I2COA2[OAEN] Bits */ -#define EUSCI_B_I2COA2_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA3[I2COA3] Bits */ -#define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /*!< I2COA3 Bit Offset */ -#define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /*!< I2COA3 Bit Mask */ -/* EUSCI_B_I2COA3[OAEN] Bits */ -#define EUSCI_B_I2COA3_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_ADDRX[ADDRX] Bits */ -#define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /*!< ADDRX Bit Offset */ -#define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /*!< ADDRX Bit Mask */ -#define EUSCI_B_ADDRX_ADDRX0 ((uint16_t)0x0001) /*!< ADDRX Bit 0 */ -#define EUSCI_B_ADDRX_ADDRX1 ((uint16_t)0x0002) /*!< ADDRX Bit 1 */ -#define EUSCI_B_ADDRX_ADDRX2 ((uint16_t)0x0004) /*!< ADDRX Bit 2 */ -#define EUSCI_B_ADDRX_ADDRX3 ((uint16_t)0x0008) /*!< ADDRX Bit 3 */ -#define EUSCI_B_ADDRX_ADDRX4 ((uint16_t)0x0010) /*!< ADDRX Bit 4 */ -#define EUSCI_B_ADDRX_ADDRX5 ((uint16_t)0x0020) /*!< ADDRX Bit 5 */ -#define EUSCI_B_ADDRX_ADDRX6 ((uint16_t)0x0040) /*!< ADDRX Bit 6 */ -#define EUSCI_B_ADDRX_ADDRX7 ((uint16_t)0x0080) /*!< ADDRX Bit 7 */ -#define EUSCI_B_ADDRX_ADDRX8 ((uint16_t)0x0100) /*!< ADDRX Bit 8 */ -#define EUSCI_B_ADDRX_ADDRX9 ((uint16_t)0x0200) /*!< ADDRX Bit 9 */ -/* EUSCI_B_ADDMASK[ADDMASK] Bits */ -#define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /*!< ADDMASK Bit Offset */ -#define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /*!< ADDMASK Bit Mask */ -/* EUSCI_B_I2CSA[I2CSA] Bits */ -#define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /*!< I2CSA Bit Offset */ -#define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /*!< I2CSA Bit Mask */ -/* EUSCI_B_IE[RXIE0] Bits */ -#define EUSCI_B_IE_RXIE0_OFS ( 0) /*!< UCRXIE0 Bit Offset */ -#define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /*!< Receive interrupt enable 0 */ -/* EUSCI_B_IE[TXIE0] Bits */ -#define EUSCI_B_IE_TXIE0_OFS ( 1) /*!< UCTXIE0 Bit Offset */ -#define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /*!< Transmit interrupt enable 0 */ -/* EUSCI_B_IE[STTIE] Bits */ -#define EUSCI_B_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /*!< START condition interrupt enable */ -/* EUSCI_B_IE[STPIE] Bits */ -#define EUSCI_B_IE_STPIE_OFS ( 3) /*!< UCSTPIE Bit Offset */ -#define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /*!< STOP condition interrupt enable */ -/* EUSCI_B_IE[ALIE] Bits */ -#define EUSCI_B_IE_ALIE_OFS ( 4) /*!< UCALIE Bit Offset */ -#define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /*!< Arbitration lost interrupt enable */ -/* EUSCI_B_IE[NACKIE] Bits */ -#define EUSCI_B_IE_NACKIE_OFS ( 5) /*!< UCNACKIE Bit Offset */ -#define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /*!< Not-acknowledge interrupt enable */ -/* EUSCI_B_IE[BCNTIE] Bits */ -#define EUSCI_B_IE_BCNTIE_OFS ( 6) /*!< UCBCNTIE Bit Offset */ -#define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /*!< Byte counter interrupt enable */ -/* EUSCI_B_IE[CLTOIE] Bits */ -#define EUSCI_B_IE_CLTOIE_OFS ( 7) /*!< UCCLTOIE Bit Offset */ -#define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /*!< Clock low timeout interrupt enable */ -/* EUSCI_B_IE[RXIE1] Bits */ -#define EUSCI_B_IE_RXIE1_OFS ( 8) /*!< UCRXIE1 Bit Offset */ -#define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /*!< Receive interrupt enable 1 */ -/* EUSCI_B_IE[TXIE1] Bits */ -#define EUSCI_B_IE_TXIE1_OFS ( 9) /*!< UCTXIE1 Bit Offset */ -#define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /*!< Transmit interrupt enable 1 */ -/* EUSCI_B_IE[RXIE2] Bits */ -#define EUSCI_B_IE_RXIE2_OFS (10) /*!< UCRXIE2 Bit Offset */ -#define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /*!< Receive interrupt enable 2 */ -/* EUSCI_B_IE[TXIE2] Bits */ -#define EUSCI_B_IE_TXIE2_OFS (11) /*!< UCTXIE2 Bit Offset */ -#define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /*!< Transmit interrupt enable 2 */ -/* EUSCI_B_IE[RXIE3] Bits */ -#define EUSCI_B_IE_RXIE3_OFS (12) /*!< UCRXIE3 Bit Offset */ -#define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /*!< Receive interrupt enable 3 */ -/* EUSCI_B_IE[TXIE3] Bits */ -#define EUSCI_B_IE_TXIE3_OFS (13) /*!< UCTXIE3 Bit Offset */ -#define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /*!< Transmit interrupt enable 3 */ -/* EUSCI_B_IE[BIT9IE] Bits */ -#define EUSCI_B_IE_BIT9IE_OFS (14) /*!< UCBIT9IE Bit Offset */ -#define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /*!< Bit position 9 interrupt enable */ -/* EUSCI_B_IE[RXIE] Bits */ -#define EUSCI_B_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_B_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -/* EUSCI_B_IE[TXIE] Bits */ -#define EUSCI_B_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_B_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -/* EUSCI_B_IFG[RXIFG0] Bits */ -#define EUSCI_B_IFG_RXIFG0_OFS ( 0) /*!< UCRXIFG0 Bit Offset */ -#define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /*!< eUSCI_B receive interrupt flag 0 */ -/* EUSCI_B_IFG[TXIFG0] Bits */ -#define EUSCI_B_IFG_TXIFG0_OFS ( 1) /*!< UCTXIFG0 Bit Offset */ -#define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /*!< eUSCI_B transmit interrupt flag 0 */ -/* EUSCI_B_IFG[STTIFG] Bits */ -#define EUSCI_B_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /*!< START condition interrupt flag */ -/* EUSCI_B_IFG[STPIFG] Bits */ -#define EUSCI_B_IFG_STPIFG_OFS ( 3) /*!< UCSTPIFG Bit Offset */ -#define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /*!< STOP condition interrupt flag */ -/* EUSCI_B_IFG[ALIFG] Bits */ -#define EUSCI_B_IFG_ALIFG_OFS ( 4) /*!< UCALIFG Bit Offset */ -#define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /*!< Arbitration lost interrupt flag */ -/* EUSCI_B_IFG[NACKIFG] Bits */ -#define EUSCI_B_IFG_NACKIFG_OFS ( 5) /*!< UCNACKIFG Bit Offset */ -#define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /*!< Not-acknowledge received interrupt flag */ -/* EUSCI_B_IFG[BCNTIFG] Bits */ -#define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /*!< UCBCNTIFG Bit Offset */ -#define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /*!< Byte counter interrupt flag */ -/* EUSCI_B_IFG[CLTOIFG] Bits */ -#define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /*!< UCCLTOIFG Bit Offset */ -#define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /*!< Clock low timeout interrupt flag */ -/* EUSCI_B_IFG[RXIFG1] Bits */ -#define EUSCI_B_IFG_RXIFG1_OFS ( 8) /*!< UCRXIFG1 Bit Offset */ -#define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /*!< eUSCI_B receive interrupt flag 1 */ -/* EUSCI_B_IFG[TXIFG1] Bits */ -#define EUSCI_B_IFG_TXIFG1_OFS ( 9) /*!< UCTXIFG1 Bit Offset */ -#define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /*!< eUSCI_B transmit interrupt flag 1 */ -/* EUSCI_B_IFG[RXIFG2] Bits */ -#define EUSCI_B_IFG_RXIFG2_OFS (10) /*!< UCRXIFG2 Bit Offset */ -#define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /*!< eUSCI_B receive interrupt flag 2 */ -/* EUSCI_B_IFG[TXIFG2] Bits */ -#define EUSCI_B_IFG_TXIFG2_OFS (11) /*!< UCTXIFG2 Bit Offset */ -#define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /*!< eUSCI_B transmit interrupt flag 2 */ -/* EUSCI_B_IFG[RXIFG3] Bits */ -#define EUSCI_B_IFG_RXIFG3_OFS (12) /*!< UCRXIFG3 Bit Offset */ -#define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /*!< eUSCI_B receive interrupt flag 3 */ -/* EUSCI_B_IFG[TXIFG3] Bits */ -#define EUSCI_B_IFG_TXIFG3_OFS (13) /*!< UCTXIFG3 Bit Offset */ -#define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /*!< eUSCI_B transmit interrupt flag 3 */ -/* EUSCI_B_IFG[BIT9IFG] Bits */ -#define EUSCI_B_IFG_BIT9IFG_OFS (14) /*!< UCBIT9IFG Bit Offset */ -#define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /*!< Bit position 9 interrupt flag */ -/* EUSCI_B_IFG[RXIFG] Bits */ -#define EUSCI_B_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -/* EUSCI_B_IFG[TXIFG] Bits */ -#define EUSCI_B_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -/* legacy definitions for backward compatibility to version 2100 */ -#define EUSCI_B__RXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_B__RXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_B__TXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_B__TXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ - - -/****************************************************************************** -* FLCTL_A Bits -******************************************************************************/ -/* FLCTL_A_POWER_STAT[PSTAT] Bits */ -#define FLCTL_A_POWER_STAT_PSTAT_OFS ( 0) /*!< PSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /*!< PSTAT Bit Mask */ -#define FLCTL_A_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /*!< PSTAT Bit 0 */ -#define FLCTL_A_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /*!< PSTAT Bit 1 */ -#define FLCTL_A_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /*!< PSTAT Bit 2 */ -#define FLCTL_A_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /*!< Flash IP in power-down mode */ -#define FLCTL_A_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /*!< Flash IP Vdd domain power-up in progress */ -#define FLCTL_A_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */ -#define FLCTL_A_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /*!< Flash IP SAFE_LV check in progress */ -#define FLCTL_A_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /*!< Flash IP Active */ -#define FLCTL_A_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */ -#define FLCTL_A_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /*!< Flash IP in Standby mode */ -#define FLCTL_A_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /*!< Flash IP in Current mirror boost state */ -/* FLCTL_A_POWER_STAT[LDOSTAT] Bits */ -#define FLCTL_A_POWER_STAT_LDOSTAT_OFS ( 3) /*!< LDOSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /*!< PSS FLDO GOOD status */ -/* FLCTL_A_POWER_STAT[VREFSTAT] Bits */ -#define FLCTL_A_POWER_STAT_VREFSTAT_OFS ( 4) /*!< VREFSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /*!< PSS VREF stable status */ -/* FLCTL_A_POWER_STAT[IREFSTAT] Bits */ -#define FLCTL_A_POWER_STAT_IREFSTAT_OFS ( 5) /*!< IREFSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /*!< PSS IREF stable status */ -/* FLCTL_A_POWER_STAT[TRIMSTAT] Bits */ -#define FLCTL_A_POWER_STAT_TRIMSTAT_OFS ( 6) /*!< TRIMSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /*!< PSS trim done status */ -/* FLCTL_A_POWER_STAT[RD_2T] Bits */ -#define FLCTL_A_POWER_STAT_RD_2T_OFS ( 7) /*!< RD_2T Bit Offset */ -#define FLCTL_A_POWER_STAT_RD_2T ((uint32_t)0x00000080) /*!< Indicates if Flash is being accessed in 2T mode */ -/* FLCTL_A_BANK0_RDCTL[RD_MODE] Bits */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -/* FLCTL_A_BANK0_RDCTL[BUFI] Bits */ -#define FLCTL_A_BANK0_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -/* FLCTL_A_BANK0_RDCTL[BUFD] Bits */ -#define FLCTL_A_BANK0_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -/* FLCTL_A_BANK0_RDCTL[WAIT] Bits */ -#define FLCTL_A_BANK0_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_A_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_A_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_A_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_A_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_A_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -/* FLCTL_A_BANK0_RDCTL[RD_MODE_STATUS] Bits */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -/* FLCTL_A_BANK1_RDCTL[RD_MODE] Bits */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -/* FLCTL_A_BANK1_RDCTL[BUFI] Bits */ -#define FLCTL_A_BANK1_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -/* FLCTL_A_BANK1_RDCTL[BUFD] Bits */ -#define FLCTL_A_BANK1_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -/* FLCTL_A_BANK1_RDCTL[RD_MODE_STATUS] Bits */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -/* FLCTL_A_BANK1_RDCTL[WAIT] Bits */ -#define FLCTL_A_BANK1_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_A_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_A_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_A_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_A_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_A_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -/* FLCTL_A_RDBRST_CTLSTAT[START] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of burst/compare operation */ -/* FLCTL_A_RDBRST_CTLSTAT[MEM_TYPE] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /*!< MEM_TYPE Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /*!< MEM_TYPE Bit Mask */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /*!< MEM_TYPE Bit 0 */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /*!< MEM_TYPE Bit 1 */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -/* FLCTL_A_RDBRST_CTLSTAT[STOP_FAIL] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /*!< STOP_FAIL Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /*!< Terminate burst/compare operation */ -/* FLCTL_A_RDBRST_CTLSTAT[DATA_CMP] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /*!< DATA_CMP Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /*!< Data pattern used for comparison against memory read data */ -/* FLCTL_A_RDBRST_CTLSTAT[TEST_EN] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /*!< TEST_EN Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /*!< Enable comparison against test data compare registers */ -/* FLCTL_A_RDBRST_CTLSTAT[BRST_STAT] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /*!< BRST_STAT Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /*!< BRST_STAT Bit Mask */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /*!< BRST_STAT Bit 0 */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /*!< BRST_STAT Bit 1 */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /*!< Idle */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /*!< Burst/Compare START bit written, but operation pending */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /*!< Burst/Compare in progress */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /*!< Burst complete (status of completed burst remains in this state unless */ - /* explicitly cleared by SW) */ -/* FLCTL_A_RDBRST_CTLSTAT[CMP_ERR] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /*!< CMP_ERR Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /*!< Burst/Compare Operation encountered atleast one data */ -/* FLCTL_A_RDBRST_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /*!< Burst/Compare Operation was terminated due to access to */ -/* FLCTL_A_RDBRST_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 19-16 of this register */ -/* FLCTL_A_RDBRST_STARTADDR[START_ADDRESS] Bits */ -#define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< START_ADDRESS Bit Mask */ -/* FLCTL_A_RDBRST_LEN[BURST_LENGTH] Bits */ -#define FLCTL_A_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /*!< BURST_LENGTH Bit Offset */ -#define FLCTL_A_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /*!< BURST_LENGTH Bit Mask */ -/* FLCTL_A_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */ -#define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /*!< FAIL_ADDRESS Bit Offset */ -#define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< FAIL_ADDRESS Bit Mask */ -/* FLCTL_A_RDBRST_FAILCNT[FAIL_COUNT] Bits */ -#define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /*!< FAIL_COUNT Bit Offset */ -#define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /*!< FAIL_COUNT Bit Mask */ -/* FLCTL_A_PRG_CTLSTAT[ENABLE] Bits */ -#define FLCTL_A_PRG_CTLSTAT_ENABLE_OFS ( 0) /*!< ENABLE Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /*!< Master control for all word program operations */ -/* FLCTL_A_PRG_CTLSTAT[MODE] Bits */ -#define FLCTL_A_PRG_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Write mode */ -/* FLCTL_A_PRG_CTLSTAT[VER_PRE] Bits */ -#define FLCTL_A_PRG_CTLSTAT_VER_PRE_OFS ( 2) /*!< VER_PRE Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /*!< Controls automatic pre program verify operations */ -/* FLCTL_A_PRG_CTLSTAT[VER_PST] Bits */ -#define FLCTL_A_PRG_CTLSTAT_VER_PST_OFS ( 3) /*!< VER_PST Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /*!< Controls automatic post program verify operations */ -/* FLCTL_A_PRG_CTLSTAT[STATUS] Bits */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_A_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_A_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Single word program operation triggered, but pending */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Single word program in progress */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Reserved (Idle) */ -/* FLCTL_A_PRG_CTLSTAT[BNK_ACT] Bits */ -#define FLCTL_A_PRG_CTLSTAT_BNK_ACT_OFS (18) /*!< BNK_ACT Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /*!< Bank active */ -/* FLCTL_A_PRGBRST_CTLSTAT[START] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Trigger start of burst program operation */ -/* FLCTL_A_PRGBRST_CTLSTAT[TYPE] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /*!< TYPE Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /*!< TYPE Bit Mask */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /*!< TYPE Bit 0 */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /*!< TYPE Bit 1 */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -/* FLCTL_A_PRGBRST_CTLSTAT[LEN] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_OFS ( 3) /*!< LEN Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /*!< LEN Bit Mask */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /*!< LEN Bit 0 */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /*!< LEN Bit 1 */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /*!< LEN Bit 2 */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /*!< No burst operation */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /*!< 1 word burst of 128 bits, starting with address in the */ - /* FLCTL_PRGBRST_STARTADDR Register */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -/* FLCTL_A_PRGBRST_CTLSTAT[AUTO_PRE] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /*!< AUTO_PRE Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /*!< Auto-Verify operation before the Burst Program */ -/* FLCTL_A_PRGBRST_CTLSTAT[AUTO_PST] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /*!< AUTO_PST Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /*!< Auto-Verify operation after the Burst Program */ -/* FLCTL_A_PRGBRST_CTLSTAT[BURST_STATUS] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /*!< BURST_STATUS Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /*!< BURST_STATUS Bit Mask */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /*!< BURST_STATUS Bit 0 */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /*!< BURST_STATUS Bit 1 */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /*!< BURST_STATUS Bit 2 */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (Burst not active) */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /*!< Burst program started but pending */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /*!< Burst active, with 1st 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /*!< Burst active, with 2nd 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /*!< Burst active, with 3rd 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /*!< Burst active, with 4th 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /*!< Reserved (Idle) */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /*!< Burst Complete (status of completed burst remains in this state unless */ - /* explicitly cleared by SW) */ -/* FLCTL_A_PRGBRST_CTLSTAT[PRE_ERR] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /*!< PRE_ERR Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /*!< Burst Operation encountered preprogram auto-verify errors */ -/* FLCTL_A_PRGBRST_CTLSTAT[PST_ERR] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /*!< PST_ERR Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /*!< Burst Operation encountered postprogram auto-verify errors */ -/* FLCTL_A_PRGBRST_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /*!< Burst Operation was terminated due to attempted program of reserved memory */ -/* FLCTL_A_PRGBRST_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 21-16 of this register */ -/* FLCTL_A_PRGBRST_STARTADDR[START_ADDRESS] Bits */ -#define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< START_ADDRESS Bit Mask */ -/* FLCTL_A_ERASE_CTLSTAT[START] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of Erase operation */ -/* FLCTL_A_ERASE_CTLSTAT[MODE] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Erase mode selected by application */ -/* FLCTL_A_ERASE_CTLSTAT[TYPE] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_OFS ( 2) /*!< TYPE Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /*!< TYPE Bit Mask */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /*!< TYPE Bit 0 */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /*!< TYPE Bit 1 */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /*!< Information Memory */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /*!< Reserved */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /*!< Engineering Memory */ -/* FLCTL_A_ERASE_CTLSTAT[STATUS] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Erase operation triggered to START but pending */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Erase operation in progress */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Erase operation completed (status of completed erase remains in this state */ - /* unless explicitly cleared by SW) */ -/* FLCTL_A_ERASE_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /*!< Erase Operation was terminated due to attempted erase of reserved memory */ - /* address */ -/* FLCTL_A_ERASE_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS (19) /*!< CLR_STAT Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /*!< Clear status bits 18-16 of this register */ -/* FLCTL_A_ERASE_SECTADDR[SECT_ADDRESS] Bits */ -#define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /*!< SECT_ADDRESS Bit Offset */ -#define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< SECT_ADDRESS Bit Mask */ -/* FLCTL_A_BANK0_INFO_WEPROT[PROT0] Bits */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_A_BANK0_INFO_WEPROT[PROT1] Bits */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_A_BANK0_INFO_WEPROT[PROT2] Bits */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK0_INFO_WEPROT[PROT3] Bits */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT0] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT1] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT2] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT3] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT4] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT5] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT6] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT7] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT8] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT9] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT10] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT11] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT12] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT13] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT14] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT15] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT16] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT17] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT18] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT19] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT20] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT21] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT22] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT23] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT24] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT25] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT26] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT27] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT28] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT29] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT30] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT31] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -/* FLCTL_A_BANK1_INFO_WEPROT[PROT0] Bits */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -/* FLCTL_A_BANK1_INFO_WEPROT[PROT1] Bits */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -/* FLCTL_A_BANK1_INFO_WEPROT[PROT2] Bits */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK1_INFO_WEPROT[PROT3] Bits */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT0] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT1] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT2] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT3] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT4] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT5] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT6] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT7] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT8] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT9] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT10] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT11] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT12] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT13] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT14] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT15] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT16] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT17] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT18] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT19] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT20] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT21] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT22] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT23] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT24] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT25] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT26] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT27] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT28] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT29] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT30] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT31] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase operations */ -/* FLCTL_A_BMRK_CTLSTAT[I_BMRK] Bits */ -#define FLCTL_A_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /*!< I_BMRK Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001) -/* FLCTL_A_BMRK_CTLSTAT[D_BMRK] Bits */ -#define FLCTL_A_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /*!< D_BMRK Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002) -/* FLCTL_A_BMRK_CTLSTAT[CMP_EN] Bits */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /*!< CMP_EN Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004) -/* FLCTL_A_BMRK_CTLSTAT[CMP_SEL] Bits */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /*!< CMP_SEL Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008) -/* FLCTL_A_IFG[RDBRST] Bits */ -#define FLCTL_A_IFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_IFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_A_IFG[AVPRE] Bits */ -#define FLCTL_A_IFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_IFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_A_IFG[AVPST] Bits */ -#define FLCTL_A_IFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_IFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_A_IFG[PRG] Bits */ -#define FLCTL_A_IFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_IFG_PRG ((uint32_t)0x00000008) -/* FLCTL_A_IFG[PRGB] Bits */ -#define FLCTL_A_IFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_IFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_A_IFG[ERASE] Bits */ -#define FLCTL_A_IFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_IFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_A_IFG[BMRK] Bits */ -#define FLCTL_A_IFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_IFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_A_IFG[PRG_ERR] Bits */ -#define FLCTL_A_IFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_IFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_A_IE[RDBRST] Bits */ -#define FLCTL_A_IE_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_IE_RDBRST ((uint32_t)0x00000001) -/* FLCTL_A_IE[AVPRE] Bits */ -#define FLCTL_A_IE_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_IE_AVPRE ((uint32_t)0x00000002) -/* FLCTL_A_IE[AVPST] Bits */ -#define FLCTL_A_IE_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_IE_AVPST ((uint32_t)0x00000004) -/* FLCTL_A_IE[PRG] Bits */ -#define FLCTL_A_IE_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_IE_PRG ((uint32_t)0x00000008) -/* FLCTL_A_IE[PRGB] Bits */ -#define FLCTL_A_IE_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_IE_PRGB ((uint32_t)0x00000010) -/* FLCTL_A_IE[ERASE] Bits */ -#define FLCTL_A_IE_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_IE_ERASE ((uint32_t)0x00000020) -/* FLCTL_A_IE[BMRK] Bits */ -#define FLCTL_A_IE_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_IE_BMRK ((uint32_t)0x00000100) -/* FLCTL_A_IE[PRG_ERR] Bits */ -#define FLCTL_A_IE_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_IE_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_A_CLRIFG[RDBRST] Bits */ -#define FLCTL_A_CLRIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_CLRIFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_A_CLRIFG[AVPRE] Bits */ -#define FLCTL_A_CLRIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_CLRIFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_A_CLRIFG[AVPST] Bits */ -#define FLCTL_A_CLRIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_CLRIFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_A_CLRIFG[PRG] Bits */ -#define FLCTL_A_CLRIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_CLRIFG_PRG ((uint32_t)0x00000008) -/* FLCTL_A_CLRIFG[PRGB] Bits */ -#define FLCTL_A_CLRIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_CLRIFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_A_CLRIFG[ERASE] Bits */ -#define FLCTL_A_CLRIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_CLRIFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_A_CLRIFG[BMRK] Bits */ -#define FLCTL_A_CLRIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_CLRIFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_A_CLRIFG[PRG_ERR] Bits */ -#define FLCTL_A_CLRIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_CLRIFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_A_SETIFG[RDBRST] Bits */ -#define FLCTL_A_SETIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_SETIFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_A_SETIFG[AVPRE] Bits */ -#define FLCTL_A_SETIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_SETIFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_A_SETIFG[AVPST] Bits */ -#define FLCTL_A_SETIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_SETIFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_A_SETIFG[PRG] Bits */ -#define FLCTL_A_SETIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_SETIFG_PRG ((uint32_t)0x00000008) -/* FLCTL_A_SETIFG[PRGB] Bits */ -#define FLCTL_A_SETIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_SETIFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_A_SETIFG[ERASE] Bits */ -#define FLCTL_A_SETIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_SETIFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_A_SETIFG[BMRK] Bits */ -#define FLCTL_A_SETIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_SETIFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_A_SETIFG[PRG_ERR] Bits */ -#define FLCTL_A_SETIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_SETIFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_A_READ_TIMCTL[SETUP] Bits */ -#define FLCTL_A_READ_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_READ_TIMCTL[IREF_BOOST1] Bits */ -#define FLCTL_A_READ_TIMCTL_IREF_BOOST1_OFS (12) /*!< IREF_BOOST1 Bit Offset */ -#define FLCTL_A_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /*!< IREF_BOOST1 Bit Mask */ -/* FLCTL_A_READ_TIMCTL[SETUP_LONG] Bits */ -#define FLCTL_A_READ_TIMCTL_SETUP_LONG_OFS (16) /*!< SETUP_LONG Bit Offset */ -#define FLCTL_A_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /*!< SETUP_LONG Bit Mask */ -/* FLCTL_A_READMARGIN_TIMCTL[SETUP] Bits */ -#define FLCTL_A_READMARGIN_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_PRGVER_TIMCTL[SETUP] Bits */ -#define FLCTL_A_PRGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_PRGVER_TIMCTL[ACTIVE] Bits */ -#define FLCTL_A_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /*!< ACTIVE Bit Mask */ -/* FLCTL_A_PRGVER_TIMCTL[HOLD] Bits */ -#define FLCTL_A_PRGVER_TIMCTL_HOLD_OFS (12) /*!< HOLD Bit Offset */ -#define FLCTL_A_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /*!< HOLD Bit Mask */ -/* FLCTL_A_ERSVER_TIMCTL[SETUP] Bits */ -#define FLCTL_A_ERSVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_LKGVER_TIMCTL[SETUP] Bits */ -#define FLCTL_A_LKGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_PROGRAM_TIMCTL[SETUP] Bits */ -#define FLCTL_A_PROGRAM_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_PROGRAM_TIMCTL[ACTIVE] Bits */ -#define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_A_PROGRAM_TIMCTL[HOLD] Bits */ -#define FLCTL_A_PROGRAM_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_A_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -/* FLCTL_A_ERASE_TIMCTL[SETUP] Bits */ -#define FLCTL_A_ERASE_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_ERASE_TIMCTL[ACTIVE] Bits */ -#define FLCTL_A_ERASE_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_A_ERASE_TIMCTL[HOLD] Bits */ -#define FLCTL_A_ERASE_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_A_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -/* FLCTL_A_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /*!< BOOST_ACTIVE Bit Offset */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /*!< BOOST_ACTIVE Bit Mask */ -/* FLCTL_A_MASSERASE_TIMCTL[BOOST_HOLD] Bits */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /*!< BOOST_HOLD Bit Offset */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /*!< BOOST_HOLD Bit Mask */ -/* FLCTL_A_BURSTPRG_TIMCTL[ACTIVE] Bits */ -#define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT0] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT1] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT2] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT3] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT4] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT5] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT6] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT7] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT8] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT9] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT10] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT11] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT12] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT13] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT14] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT15] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT16] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT17] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT18] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT19] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT20] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT21] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT22] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT23] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT24] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT25] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT26] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT27] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT28] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT29] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT30] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT31] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT32] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32_OFS ( 0) /*!< PROT32 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32 ((uint32_t)0x00000001) /*!< Protects Sector 32 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT33] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33_OFS ( 1) /*!< PROT33 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33 ((uint32_t)0x00000002) /*!< Protects Sector 33 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT34] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34_OFS ( 2) /*!< PROT34 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34 ((uint32_t)0x00000004) /*!< Protects Sector 34 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT35] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35_OFS ( 3) /*!< PROT35 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35 ((uint32_t)0x00000008) /*!< Protects Sector 35 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT36] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36_OFS ( 4) /*!< PROT36 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36 ((uint32_t)0x00000010) /*!< Protects Sector 36 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT37] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37_OFS ( 5) /*!< PROT37 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37 ((uint32_t)0x00000020) /*!< Protects Sector 37 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT38] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38_OFS ( 6) /*!< PROT38 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38 ((uint32_t)0x00000040) /*!< Protects Sector 38 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT39] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39_OFS ( 7) /*!< PROT39 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39 ((uint32_t)0x00000080) /*!< Protects Sector 39 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT40] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40_OFS ( 8) /*!< PROT40 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40 ((uint32_t)0x00000100) /*!< Protects Sector 40 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT41] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41_OFS ( 9) /*!< PROT41 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41 ((uint32_t)0x00000200) /*!< Protects Sector 41 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT42] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42_OFS (10) /*!< PROT42 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42 ((uint32_t)0x00000400) /*!< Protects Sector 42 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT43] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43_OFS (11) /*!< PROT43 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43 ((uint32_t)0x00000800) /*!< Protects Sector 43 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT44] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44_OFS (12) /*!< PROT44 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44 ((uint32_t)0x00001000) /*!< Protects Sector 44 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT45] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45_OFS (13) /*!< PROT45 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45 ((uint32_t)0x00002000) /*!< Protects Sector 45 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT46] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46_OFS (14) /*!< PROT46 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46 ((uint32_t)0x00004000) /*!< Protects Sector 46 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT47] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47_OFS (15) /*!< PROT47 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47 ((uint32_t)0x00008000) /*!< Protects Sector 47 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT48] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48_OFS (16) /*!< PROT48 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48 ((uint32_t)0x00010000) /*!< Protects Sector 48 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT49] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49_OFS (17) /*!< PROT49 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49 ((uint32_t)0x00020000) /*!< Protects Sector 49 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT50] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50_OFS (18) /*!< PROT50 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50 ((uint32_t)0x00040000) /*!< Protects Sector 50 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT51] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51_OFS (19) /*!< PROT51 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51 ((uint32_t)0x00080000) /*!< Protects Sector 51 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT52] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52_OFS (20) /*!< PROT52 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52 ((uint32_t)0x00100000) /*!< Protects Sector 52 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT53] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53_OFS (21) /*!< PROT53 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53 ((uint32_t)0x00200000) /*!< Protects Sector 53 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT54] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54_OFS (22) /*!< PROT54 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54 ((uint32_t)0x00400000) /*!< Protects Sector 54 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT55] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55_OFS (23) /*!< PROT55 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55 ((uint32_t)0x00800000) /*!< Protects Sector 55 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT56] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56_OFS (24) /*!< PROT56 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56 ((uint32_t)0x01000000) /*!< Protects Sector 56 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT57] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57_OFS (25) /*!< PROT57 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57 ((uint32_t)0x02000000) /*!< Protects Sector 57 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT58] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58_OFS (26) /*!< PROT58 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58 ((uint32_t)0x04000000) /*!< Protects Sector 58 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT59] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59_OFS (27) /*!< PROT59 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59 ((uint32_t)0x08000000) /*!< Protects Sector 59 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT60] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60_OFS (28) /*!< PROT60 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60 ((uint32_t)0x10000000) /*!< Protects Sector 60 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT61] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61_OFS (29) /*!< PROT61 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61 ((uint32_t)0x20000000) /*!< Protects Sector 61 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT62] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62_OFS (30) /*!< PROT62 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62 ((uint32_t)0x40000000) /*!< Protects Sector 62 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT63] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63_OFS (31) /*!< PROT63 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63 ((uint32_t)0x80000000) /*!< Protects Sector 63 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT64] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64_OFS ( 0) /*!< PROT64 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64 ((uint32_t)0x00000001) /*!< Protects Sector 64 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT65] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65_OFS ( 1) /*!< PROT65 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65 ((uint32_t)0x00000002) /*!< Protects Sector 65 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT66] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66_OFS ( 2) /*!< PROT66 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66 ((uint32_t)0x00000004) /*!< Protects Sector 66 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT67] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67_OFS ( 3) /*!< PROT67 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67 ((uint32_t)0x00000008) /*!< Protects Sector 67 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT68] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68_OFS ( 4) /*!< PROT68 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68 ((uint32_t)0x00000010) /*!< Protects Sector 68 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT69] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69_OFS ( 5) /*!< PROT69 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69 ((uint32_t)0x00000020) /*!< Protects Sector 69 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT70] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70_OFS ( 6) /*!< PROT70 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70 ((uint32_t)0x00000040) /*!< Protects Sector 70 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT71] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71_OFS ( 7) /*!< PROT71 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71 ((uint32_t)0x00000080) /*!< Protects Sector 71 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT72] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72_OFS ( 8) /*!< PROT72 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72 ((uint32_t)0x00000100) /*!< Protects Sector 72 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT73] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73_OFS ( 9) /*!< PROT73 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73 ((uint32_t)0x00000200) /*!< Protects Sector 73 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT74] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74_OFS (10) /*!< PROT74 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74 ((uint32_t)0x00000400) /*!< Protects Sector 74 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT75] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75_OFS (11) /*!< PROT75 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75 ((uint32_t)0x00000800) /*!< Protects Sector 75 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT76] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76_OFS (12) /*!< PROT76 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76 ((uint32_t)0x00001000) /*!< Protects Sector 76 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT77] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77_OFS (13) /*!< PROT77 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77 ((uint32_t)0x00002000) /*!< Protects Sector 77 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT78] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78_OFS (14) /*!< PROT78 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78 ((uint32_t)0x00004000) /*!< Protects Sector 78 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT79] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79_OFS (15) /*!< PROT79 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79 ((uint32_t)0x00008000) /*!< Protects Sector 79 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT80] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80_OFS (16) /*!< PROT80 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80 ((uint32_t)0x00010000) /*!< Protects Sector 80 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT81] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81_OFS (17) /*!< PROT81 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81 ((uint32_t)0x00020000) /*!< Protects Sector 81 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT82] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82_OFS (18) /*!< PROT82 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82 ((uint32_t)0x00040000) /*!< Protects Sector 82 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT83] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83_OFS (19) /*!< PROT83 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83 ((uint32_t)0x00080000) /*!< Protects Sector 83 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT84] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84_OFS (20) /*!< PROT84 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84 ((uint32_t)0x00100000) /*!< Protects Sector 84 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT85] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85_OFS (21) /*!< PROT85 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85 ((uint32_t)0x00200000) /*!< Protects Sector 85 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT86] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86_OFS (22) /*!< PROT86 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86 ((uint32_t)0x00400000) /*!< Protects Sector 86 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT87] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87_OFS (23) /*!< PROT87 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87 ((uint32_t)0x00800000) /*!< Protects Sector 87 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT88] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88_OFS (24) /*!< PROT88 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88 ((uint32_t)0x01000000) /*!< Protects Sector 88 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT89] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89_OFS (25) /*!< PROT89 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89 ((uint32_t)0x02000000) /*!< Protects Sector 89 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT90] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90_OFS (26) /*!< PROT90 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90 ((uint32_t)0x04000000) /*!< Protects Sector 90 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT91] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91_OFS (27) /*!< PROT91 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91 ((uint32_t)0x08000000) /*!< Protects Sector 91 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT92] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92_OFS (28) /*!< PROT92 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92 ((uint32_t)0x10000000) /*!< Protects Sector 92 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT93] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93_OFS (29) /*!< PROT93 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93 ((uint32_t)0x20000000) /*!< Protects Sector 93 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT94] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94_OFS (30) /*!< PROT94 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94 ((uint32_t)0x40000000) /*!< Protects Sector 94 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT95] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95_OFS (31) /*!< PROT95 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95 ((uint32_t)0x80000000) /*!< Protects Sector 95 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT96] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96_OFS ( 0) /*!< PROT96 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96 ((uint32_t)0x00000001) /*!< Protects Sector 96 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT97] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97_OFS ( 1) /*!< PROT97 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97 ((uint32_t)0x00000002) /*!< Protects Sector 97 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT98] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98_OFS ( 2) /*!< PROT98 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98 ((uint32_t)0x00000004) /*!< Protects Sector 98 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT99] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99_OFS ( 3) /*!< PROT99 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99 ((uint32_t)0x00000008) /*!< Protects Sector 99 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT100] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100_OFS ( 4) /*!< PROT100 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100 ((uint32_t)0x00000010) /*!< Protects Sector 100 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT101] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101_OFS ( 5) /*!< PROT101 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101 ((uint32_t)0x00000020) /*!< Protects Sector 101 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT102] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102_OFS ( 6) /*!< PROT102 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102 ((uint32_t)0x00000040) /*!< Protects Sector 102 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT103] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103_OFS ( 7) /*!< PROT103 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103 ((uint32_t)0x00000080) /*!< Protects Sector 103 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT104] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104_OFS ( 8) /*!< PROT104 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104 ((uint32_t)0x00000100) /*!< Protects Sector 104 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT105] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105_OFS ( 9) /*!< PROT105 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105 ((uint32_t)0x00000200) /*!< Protects Sector 105 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT106] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106_OFS (10) /*!< PROT106 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106 ((uint32_t)0x00000400) /*!< Protects Sector 106 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT107] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107_OFS (11) /*!< PROT107 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107 ((uint32_t)0x00000800) /*!< Protects Sector 107 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT108] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108_OFS (12) /*!< PROT108 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108 ((uint32_t)0x00001000) /*!< Protects Sector 108 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT109] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109_OFS (13) /*!< PROT109 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109 ((uint32_t)0x00002000) /*!< Protects Sector 109 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT110] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110_OFS (14) /*!< PROT110 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110 ((uint32_t)0x00004000) /*!< Protects Sector 110 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT111] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111_OFS (15) /*!< PROT111 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111 ((uint32_t)0x00008000) /*!< Protects Sector 111 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT112] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112_OFS (16) /*!< PROT112 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112 ((uint32_t)0x00010000) /*!< Protects Sector 112 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT113] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113_OFS (17) /*!< PROT113 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113 ((uint32_t)0x00020000) /*!< Protects Sector 113 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT114] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114_OFS (18) /*!< PROT114 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114 ((uint32_t)0x00040000) /*!< Protects Sector 114 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT115] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115_OFS (19) /*!< PROT115 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115 ((uint32_t)0x00080000) /*!< Protects Sector 115 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT116] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116_OFS (20) /*!< PROT116 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116 ((uint32_t)0x00100000) /*!< Protects Sector 116 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT117] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117_OFS (21) /*!< PROT117 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117 ((uint32_t)0x00200000) /*!< Protects Sector 117 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT118] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118_OFS (22) /*!< PROT118 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118 ((uint32_t)0x00400000) /*!< Protects Sector 118 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT119] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119_OFS (23) /*!< PROT119 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119 ((uint32_t)0x00800000) /*!< Protects Sector 119 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT120] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120_OFS (24) /*!< PROT120 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120 ((uint32_t)0x01000000) /*!< Protects Sector 120 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT121] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121_OFS (25) /*!< PROT121 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121 ((uint32_t)0x02000000) /*!< Protects Sector 121 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT122] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122_OFS (26) /*!< PROT122 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122 ((uint32_t)0x04000000) /*!< Protects Sector 122 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT123] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123_OFS (27) /*!< PROT123 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123 ((uint32_t)0x08000000) /*!< Protects Sector 123 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT124] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124_OFS (28) /*!< PROT124 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124 ((uint32_t)0x10000000) /*!< Protects Sector 124 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT125] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125_OFS (29) /*!< PROT125 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125 ((uint32_t)0x20000000) /*!< Protects Sector 125 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT126] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126_OFS (30) /*!< PROT126 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126 ((uint32_t)0x40000000) /*!< Protects Sector 126 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT127] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127_OFS (31) /*!< PROT127 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127 ((uint32_t)0x80000000) /*!< Protects Sector 127 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT128] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128_OFS ( 0) /*!< PROT128 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128 ((uint32_t)0x00000001) /*!< Protects Sector 128 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT129] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129_OFS ( 1) /*!< PROT129 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129 ((uint32_t)0x00000002) /*!< Protects Sector 129 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT130] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130_OFS ( 2) /*!< PROT130 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130 ((uint32_t)0x00000004) /*!< Protects Sector 130 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT131] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131_OFS ( 3) /*!< PROT131 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131 ((uint32_t)0x00000008) /*!< Protects Sector 131 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT132] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132_OFS ( 4) /*!< PROT132 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132 ((uint32_t)0x00000010) /*!< Protects Sector 132 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT133] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133_OFS ( 5) /*!< PROT133 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133 ((uint32_t)0x00000020) /*!< Protects Sector 133 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT134] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134_OFS ( 6) /*!< PROT134 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134 ((uint32_t)0x00000040) /*!< Protects Sector 134 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT135] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135_OFS ( 7) /*!< PROT135 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135 ((uint32_t)0x00000080) /*!< Protects Sector 135 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT136] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136_OFS ( 8) /*!< PROT136 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136 ((uint32_t)0x00000100) /*!< Protects Sector 136 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT137] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137_OFS ( 9) /*!< PROT137 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137 ((uint32_t)0x00000200) /*!< Protects Sector 137 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT138] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138_OFS (10) /*!< PROT138 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138 ((uint32_t)0x00000400) /*!< Protects Sector 138 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT139] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139_OFS (11) /*!< PROT139 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139 ((uint32_t)0x00000800) /*!< Protects Sector 139 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT140] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140_OFS (12) /*!< PROT140 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140 ((uint32_t)0x00001000) /*!< Protects Sector 140 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT141] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141_OFS (13) /*!< PROT141 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141 ((uint32_t)0x00002000) /*!< Protects Sector 141 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT142] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142_OFS (14) /*!< PROT142 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142 ((uint32_t)0x00004000) /*!< Protects Sector 142 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT143] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143_OFS (15) /*!< PROT143 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143 ((uint32_t)0x00008000) /*!< Protects Sector 143 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT144] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144_OFS (16) /*!< PROT144 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144 ((uint32_t)0x00010000) /*!< Protects Sector 144 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT145] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145_OFS (17) /*!< PROT145 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145 ((uint32_t)0x00020000) /*!< Protects Sector 145 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT146] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146_OFS (18) /*!< PROT146 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146 ((uint32_t)0x00040000) /*!< Protects Sector 146 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT147] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147_OFS (19) /*!< PROT147 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147 ((uint32_t)0x00080000) /*!< Protects Sector 147 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT148] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148_OFS (20) /*!< PROT148 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148 ((uint32_t)0x00100000) /*!< Protects Sector 148 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT149] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149_OFS (21) /*!< PROT149 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149 ((uint32_t)0x00200000) /*!< Protects Sector 149 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT150] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150_OFS (22) /*!< PROT150 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150 ((uint32_t)0x00400000) /*!< Protects Sector 150 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT151] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151_OFS (23) /*!< PROT151 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151 ((uint32_t)0x00800000) /*!< Protects Sector 151 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT152] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152_OFS (24) /*!< PROT152 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152 ((uint32_t)0x01000000) /*!< Protects Sector 152 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT153] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153_OFS (25) /*!< PROT153 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153 ((uint32_t)0x02000000) /*!< Protects Sector 153 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT154] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154_OFS (26) /*!< PROT154 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154 ((uint32_t)0x04000000) /*!< Protects Sector 154 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT155] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155_OFS (27) /*!< PROT155 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155 ((uint32_t)0x08000000) /*!< Protects Sector 155 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT156] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156_OFS (28) /*!< PROT156 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156 ((uint32_t)0x10000000) /*!< Protects Sector 156 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT157] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157_OFS (29) /*!< PROT157 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157 ((uint32_t)0x20000000) /*!< Protects Sector 157 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT158] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158_OFS (30) /*!< PROT158 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158 ((uint32_t)0x40000000) /*!< Protects Sector 158 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT159] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159_OFS (31) /*!< PROT159 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159 ((uint32_t)0x80000000) /*!< Protects Sector 159 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT160] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160_OFS ( 0) /*!< PROT160 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160 ((uint32_t)0x00000001) /*!< Protects Sector 160 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT161] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161_OFS ( 1) /*!< PROT161 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161 ((uint32_t)0x00000002) /*!< Protects Sector 161 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT162] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162_OFS ( 2) /*!< PROT162 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162 ((uint32_t)0x00000004) /*!< Protects Sector 162 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT163] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163_OFS ( 3) /*!< PROT163 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163 ((uint32_t)0x00000008) /*!< Protects Sector 163 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT164] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164_OFS ( 4) /*!< PROT164 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164 ((uint32_t)0x00000010) /*!< Protects Sector 164 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT165] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165_OFS ( 5) /*!< PROT165 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165 ((uint32_t)0x00000020) /*!< Protects Sector 165 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT166] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166_OFS ( 6) /*!< PROT166 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166 ((uint32_t)0x00000040) /*!< Protects Sector 166 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT167] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167_OFS ( 7) /*!< PROT167 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167 ((uint32_t)0x00000080) /*!< Protects Sector 167 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT168] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168_OFS ( 8) /*!< PROT168 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168 ((uint32_t)0x00000100) /*!< Protects Sector 168 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT169] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169_OFS ( 9) /*!< PROT169 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169 ((uint32_t)0x00000200) /*!< Protects Sector 169 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT170] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170_OFS (10) /*!< PROT170 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170 ((uint32_t)0x00000400) /*!< Protects Sector 170 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT171] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171_OFS (11) /*!< PROT171 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171 ((uint32_t)0x00000800) /*!< Protects Sector 171 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT172] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172_OFS (12) /*!< PROT172 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172 ((uint32_t)0x00001000) /*!< Protects Sector 172 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT173] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173_OFS (13) /*!< PROT173 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173 ((uint32_t)0x00002000) /*!< Protects Sector 173 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT174] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174_OFS (14) /*!< PROT174 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174 ((uint32_t)0x00004000) /*!< Protects Sector 174 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT175] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175_OFS (15) /*!< PROT175 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175 ((uint32_t)0x00008000) /*!< Protects Sector 175 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT176] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176_OFS (16) /*!< PROT176 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176 ((uint32_t)0x00010000) /*!< Protects Sector 176 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT177] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177_OFS (17) /*!< PROT177 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177 ((uint32_t)0x00020000) /*!< Protects Sector 177 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT178] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178_OFS (18) /*!< PROT178 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178 ((uint32_t)0x00040000) /*!< Protects Sector 178 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT179] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179_OFS (19) /*!< PROT179 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179 ((uint32_t)0x00080000) /*!< Protects Sector 179 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT180] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180_OFS (20) /*!< PROT180 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180 ((uint32_t)0x00100000) /*!< Protects Sector 180 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT181] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181_OFS (21) /*!< PROT181 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181 ((uint32_t)0x00200000) /*!< Protects Sector 181 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT182] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182_OFS (22) /*!< PROT182 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182 ((uint32_t)0x00400000) /*!< Protects Sector 182 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT183] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183_OFS (23) /*!< PROT183 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183 ((uint32_t)0x00800000) /*!< Protects Sector 183 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT184] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184_OFS (24) /*!< PROT184 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184 ((uint32_t)0x01000000) /*!< Protects Sector 184 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT185] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185_OFS (25) /*!< PROT185 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185 ((uint32_t)0x02000000) /*!< Protects Sector 185 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT186] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186_OFS (26) /*!< PROT186 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186 ((uint32_t)0x04000000) /*!< Protects Sector 186 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT187] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187_OFS (27) /*!< PROT187 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187 ((uint32_t)0x08000000) /*!< Protects Sector 187 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT188] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188_OFS (28) /*!< PROT188 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188 ((uint32_t)0x10000000) /*!< Protects Sector 188 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT189] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189_OFS (29) /*!< PROT189 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189 ((uint32_t)0x20000000) /*!< Protects Sector 189 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT190] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190_OFS (30) /*!< PROT190 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190 ((uint32_t)0x40000000) /*!< Protects Sector 190 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT191] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191_OFS (31) /*!< PROT191 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191 ((uint32_t)0x80000000) /*!< Protects Sector 191 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT192] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192_OFS ( 0) /*!< PROT192 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192 ((uint32_t)0x00000001) /*!< Protects Sector 192 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT193] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193_OFS ( 1) /*!< PROT193 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193 ((uint32_t)0x00000002) /*!< Protects Sector 193 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT194] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194_OFS ( 2) /*!< PROT194 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194 ((uint32_t)0x00000004) /*!< Protects Sector 194 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT195] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195_OFS ( 3) /*!< PROT195 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195 ((uint32_t)0x00000008) /*!< Protects Sector 195 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT196] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196_OFS ( 4) /*!< PROT196 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196 ((uint32_t)0x00000010) /*!< Protects Sector 196 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT197] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197_OFS ( 5) /*!< PROT197 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197 ((uint32_t)0x00000020) /*!< Protects Sector 197 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT198] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198_OFS ( 6) /*!< PROT198 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198 ((uint32_t)0x00000040) /*!< Protects Sector 198 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT199] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199_OFS ( 7) /*!< PROT199 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199 ((uint32_t)0x00000080) /*!< Protects Sector 199 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT200] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200_OFS ( 8) /*!< PROT200 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200 ((uint32_t)0x00000100) /*!< Protects Sector 200 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT201] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201_OFS ( 9) /*!< PROT201 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201 ((uint32_t)0x00000200) /*!< Protects Sector 201 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT202] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202_OFS (10) /*!< PROT202 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202 ((uint32_t)0x00000400) /*!< Protects Sector 202 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT203] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203_OFS (11) /*!< PROT203 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203 ((uint32_t)0x00000800) /*!< Protects Sector 203 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT204] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204_OFS (12) /*!< PROT204 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204 ((uint32_t)0x00001000) /*!< Protects Sector 204 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT205] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205_OFS (13) /*!< PROT205 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205 ((uint32_t)0x00002000) /*!< Protects Sector 205 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT206] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206_OFS (14) /*!< PROT206 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206 ((uint32_t)0x00004000) /*!< Protects Sector 206 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT207] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207_OFS (15) /*!< PROT207 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207 ((uint32_t)0x00008000) /*!< Protects Sector 207 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT208] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208_OFS (16) /*!< PROT208 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208 ((uint32_t)0x00010000) /*!< Protects Sector 208 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT209] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209_OFS (17) /*!< PROT209 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209 ((uint32_t)0x00020000) /*!< Protects Sector 209 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT210] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210_OFS (18) /*!< PROT210 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210 ((uint32_t)0x00040000) /*!< Protects Sector 210 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT211] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211_OFS (19) /*!< PROT211 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211 ((uint32_t)0x00080000) /*!< Protects Sector 211 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT212] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212_OFS (20) /*!< PROT212 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212 ((uint32_t)0x00100000) /*!< Protects Sector 212 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT213] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213_OFS (21) /*!< PROT213 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213 ((uint32_t)0x00200000) /*!< Protects Sector 213 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT214] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214_OFS (22) /*!< PROT214 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214 ((uint32_t)0x00400000) /*!< Protects Sector 214 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT215] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215_OFS (23) /*!< PROT215 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215 ((uint32_t)0x00800000) /*!< Protects Sector 215 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT216] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216_OFS (24) /*!< PROT216 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216 ((uint32_t)0x01000000) /*!< Protects Sector 216 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT217] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217_OFS (25) /*!< PROT217 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217 ((uint32_t)0x02000000) /*!< Protects Sector 217 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT218] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218_OFS (26) /*!< PROT218 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218 ((uint32_t)0x04000000) /*!< Protects Sector 218 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT219] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219_OFS (27) /*!< PROT219 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219 ((uint32_t)0x08000000) /*!< Protects Sector 219 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT220] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220_OFS (28) /*!< PROT220 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220 ((uint32_t)0x10000000) /*!< Protects Sector 220 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT221] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221_OFS (29) /*!< PROT221 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221 ((uint32_t)0x20000000) /*!< Protects Sector 221 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT222] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222_OFS (30) /*!< PROT222 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222 ((uint32_t)0x40000000) /*!< Protects Sector 222 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT223] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223_OFS (31) /*!< PROT223 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223 ((uint32_t)0x80000000) /*!< Protects Sector 223 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT224] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224_OFS ( 0) /*!< PROT224 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224 ((uint32_t)0x00000001) /*!< Protects Sector 224 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT225] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225_OFS ( 1) /*!< PROT225 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225 ((uint32_t)0x00000002) /*!< Protects Sector 225 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT226] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226_OFS ( 2) /*!< PROT226 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226 ((uint32_t)0x00000004) /*!< Protects Sector 226 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT227] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227_OFS ( 3) /*!< PROT227 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227 ((uint32_t)0x00000008) /*!< Protects Sector 227 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT228] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228_OFS ( 4) /*!< PROT228 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228 ((uint32_t)0x00000010) /*!< Protects Sector 228 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT229] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229_OFS ( 5) /*!< PROT229 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229 ((uint32_t)0x00000020) /*!< Protects Sector 229 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT230] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230_OFS ( 6) /*!< PROT230 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230 ((uint32_t)0x00000040) /*!< Protects Sector 230 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT231] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231_OFS ( 7) /*!< PROT231 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231 ((uint32_t)0x00000080) /*!< Protects Sector 231 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT232] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232_OFS ( 8) /*!< PROT232 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232 ((uint32_t)0x00000100) /*!< Protects Sector 232 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT233] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233_OFS ( 9) /*!< PROT233 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233 ((uint32_t)0x00000200) /*!< Protects Sector 233 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT234] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234_OFS (10) /*!< PROT234 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234 ((uint32_t)0x00000400) /*!< Protects Sector 234 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT235] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235_OFS (11) /*!< PROT235 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235 ((uint32_t)0x00000800) /*!< Protects Sector 235 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT236] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236_OFS (12) /*!< PROT236 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236 ((uint32_t)0x00001000) /*!< Protects Sector 236 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT237] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237_OFS (13) /*!< PROT237 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237 ((uint32_t)0x00002000) /*!< Protects Sector 237 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT238] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238_OFS (14) /*!< PROT238 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238 ((uint32_t)0x00004000) /*!< Protects Sector 238 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT239] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239_OFS (15) /*!< PROT239 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239 ((uint32_t)0x00008000) /*!< Protects Sector 239 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT240] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240_OFS (16) /*!< PROT240 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240 ((uint32_t)0x00010000) /*!< Protects Sector 240 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT241] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241_OFS (17) /*!< PROT241 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241 ((uint32_t)0x00020000) /*!< Protects Sector 241 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT242] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242_OFS (18) /*!< PROT242 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242 ((uint32_t)0x00040000) /*!< Protects Sector 242 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT243] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243_OFS (19) /*!< PROT243 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243 ((uint32_t)0x00080000) /*!< Protects Sector 243 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT244] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244_OFS (20) /*!< PROT244 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244 ((uint32_t)0x00100000) /*!< Protects Sector 244 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT245] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245_OFS (21) /*!< PROT245 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245 ((uint32_t)0x00200000) /*!< Protects Sector 245 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT246] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246_OFS (22) /*!< PROT246 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246 ((uint32_t)0x00400000) /*!< Protects Sector 246 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT247] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247_OFS (23) /*!< PROT247 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247 ((uint32_t)0x00800000) /*!< Protects Sector 247 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT248] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248_OFS (24) /*!< PROT248 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248 ((uint32_t)0x01000000) /*!< Protects Sector 248 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT249] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249_OFS (25) /*!< PROT249 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249 ((uint32_t)0x02000000) /*!< Protects Sector 249 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT250] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250_OFS (26) /*!< PROT250 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250 ((uint32_t)0x04000000) /*!< Protects Sector 250 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT251] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251_OFS (27) /*!< PROT251 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251 ((uint32_t)0x08000000) /*!< Protects Sector 251 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT252] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252_OFS (28) /*!< PROT252 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252 ((uint32_t)0x10000000) /*!< Protects Sector 252 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT253] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253_OFS (29) /*!< PROT253 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253 ((uint32_t)0x20000000) /*!< Protects Sector 253 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT254] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254_OFS (30) /*!< PROT254 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254 ((uint32_t)0x40000000) /*!< Protects Sector 254 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT255] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255_OFS (31) /*!< PROT255 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255 ((uint32_t)0x80000000) /*!< Protects Sector 255 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT0] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT1] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT2] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT3] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT4] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT5] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT6] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT7] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT8] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT9] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT10] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT11] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT12] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT13] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT14] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT15] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT16] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT17] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT18] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT19] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT20] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT21] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT22] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT23] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT24] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT25] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT26] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT27] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT28] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT29] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT30] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT31] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT32] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32_OFS ( 0) /*!< PROT32 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32 ((uint32_t)0x00000001) /*!< Protects Sector 32 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT33] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33_OFS ( 1) /*!< PROT33 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33 ((uint32_t)0x00000002) /*!< Protects Sector 33 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT34] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34_OFS ( 2) /*!< PROT34 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34 ((uint32_t)0x00000004) /*!< Protects Sector 34 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT35] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35_OFS ( 3) /*!< PROT35 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35 ((uint32_t)0x00000008) /*!< Protects Sector 35 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT36] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36_OFS ( 4) /*!< PROT36 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36 ((uint32_t)0x00000010) /*!< Protects Sector 36 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT37] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37_OFS ( 5) /*!< PROT37 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37 ((uint32_t)0x00000020) /*!< Protects Sector 37 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT38] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38_OFS ( 6) /*!< PROT38 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38 ((uint32_t)0x00000040) /*!< Protects Sector 38 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT39] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39_OFS ( 7) /*!< PROT39 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39 ((uint32_t)0x00000080) /*!< Protects Sector 39 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT40] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40_OFS ( 8) /*!< PROT40 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40 ((uint32_t)0x00000100) /*!< Protects Sector 40 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT41] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41_OFS ( 9) /*!< PROT41 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41 ((uint32_t)0x00000200) /*!< Protects Sector 41 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT42] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42_OFS (10) /*!< PROT42 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42 ((uint32_t)0x00000400) /*!< Protects Sector 42 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT43] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43_OFS (11) /*!< PROT43 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43 ((uint32_t)0x00000800) /*!< Protects Sector 43 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT44] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44_OFS (12) /*!< PROT44 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44 ((uint32_t)0x00001000) /*!< Protects Sector 44 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT45] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45_OFS (13) /*!< PROT45 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45 ((uint32_t)0x00002000) /*!< Protects Sector 45 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT46] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46_OFS (14) /*!< PROT46 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46 ((uint32_t)0x00004000) /*!< Protects Sector 46 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT47] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47_OFS (15) /*!< PROT47 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47 ((uint32_t)0x00008000) /*!< Protects Sector 47 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT48] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48_OFS (16) /*!< PROT48 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48 ((uint32_t)0x00010000) /*!< Protects Sector 48 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT49] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49_OFS (17) /*!< PROT49 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49 ((uint32_t)0x00020000) /*!< Protects Sector 49 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT50] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50_OFS (18) /*!< PROT50 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50 ((uint32_t)0x00040000) /*!< Protects Sector 50 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT51] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51_OFS (19) /*!< PROT51 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51 ((uint32_t)0x00080000) /*!< Protects Sector 51 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT52] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52_OFS (20) /*!< PROT52 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52 ((uint32_t)0x00100000) /*!< Protects Sector 52 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT53] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53_OFS (21) /*!< PROT53 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53 ((uint32_t)0x00200000) /*!< Protects Sector 53 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT54] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54_OFS (22) /*!< PROT54 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54 ((uint32_t)0x00400000) /*!< Protects Sector 54 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT55] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55_OFS (23) /*!< PROT55 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55 ((uint32_t)0x00800000) /*!< Protects Sector 55 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT56] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56_OFS (24) /*!< PROT56 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56 ((uint32_t)0x01000000) /*!< Protects Sector 56 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT57] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57_OFS (25) /*!< PROT57 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57 ((uint32_t)0x02000000) /*!< Protects Sector 57 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT58] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58_OFS (26) /*!< PROT58 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58 ((uint32_t)0x04000000) /*!< Protects Sector 58 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT59] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59_OFS (27) /*!< PROT59 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59 ((uint32_t)0x08000000) /*!< Protects Sector 59 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT60] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60_OFS (28) /*!< PROT60 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60 ((uint32_t)0x10000000) /*!< Protects Sector 60 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT61] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61_OFS (29) /*!< PROT61 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61 ((uint32_t)0x20000000) /*!< Protects Sector 61 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT62] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62_OFS (30) /*!< PROT62 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62 ((uint32_t)0x40000000) /*!< Protects Sector 62 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT63] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63_OFS (31) /*!< PROT63 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63 ((uint32_t)0x80000000) /*!< Protects Sector 63 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT64] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64_OFS ( 0) /*!< PROT64 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64 ((uint32_t)0x00000001) /*!< Protects Sector 64 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT65] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65_OFS ( 1) /*!< PROT65 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65 ((uint32_t)0x00000002) /*!< Protects Sector 65 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT66] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66_OFS ( 2) /*!< PROT66 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66 ((uint32_t)0x00000004) /*!< Protects Sector 66 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT67] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67_OFS ( 3) /*!< PROT67 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67 ((uint32_t)0x00000008) /*!< Protects Sector 67 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT68] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68_OFS ( 4) /*!< PROT68 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68 ((uint32_t)0x00000010) /*!< Protects Sector 68 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT69] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69_OFS ( 5) /*!< PROT69 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69 ((uint32_t)0x00000020) /*!< Protects Sector 69 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT70] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70_OFS ( 6) /*!< PROT70 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70 ((uint32_t)0x00000040) /*!< Protects Sector 70 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT71] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71_OFS ( 7) /*!< PROT71 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71 ((uint32_t)0x00000080) /*!< Protects Sector 71 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT72] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72_OFS ( 8) /*!< PROT72 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72 ((uint32_t)0x00000100) /*!< Protects Sector 72 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT73] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73_OFS ( 9) /*!< PROT73 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73 ((uint32_t)0x00000200) /*!< Protects Sector 73 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT74] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74_OFS (10) /*!< PROT74 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74 ((uint32_t)0x00000400) /*!< Protects Sector 74 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT75] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75_OFS (11) /*!< PROT75 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75 ((uint32_t)0x00000800) /*!< Protects Sector 75 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT76] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76_OFS (12) /*!< PROT76 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76 ((uint32_t)0x00001000) /*!< Protects Sector 76 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT77] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77_OFS (13) /*!< PROT77 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77 ((uint32_t)0x00002000) /*!< Protects Sector 77 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT78] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78_OFS (14) /*!< PROT78 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78 ((uint32_t)0x00004000) /*!< Protects Sector 78 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT79] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79_OFS (15) /*!< PROT79 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79 ((uint32_t)0x00008000) /*!< Protects Sector 79 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT80] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80_OFS (16) /*!< PROT80 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80 ((uint32_t)0x00010000) /*!< Protects Sector 80 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT81] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81_OFS (17) /*!< PROT81 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81 ((uint32_t)0x00020000) /*!< Protects Sector 81 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT82] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82_OFS (18) /*!< PROT82 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82 ((uint32_t)0x00040000) /*!< Protects Sector 82 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT83] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83_OFS (19) /*!< PROT83 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83 ((uint32_t)0x00080000) /*!< Protects Sector 83 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT84] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84_OFS (20) /*!< PROT84 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84 ((uint32_t)0x00100000) /*!< Protects Sector 84 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT85] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85_OFS (21) /*!< PROT85 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85 ((uint32_t)0x00200000) /*!< Protects Sector 85 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT86] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86_OFS (22) /*!< PROT86 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86 ((uint32_t)0x00400000) /*!< Protects Sector 86 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT87] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87_OFS (23) /*!< PROT87 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87 ((uint32_t)0x00800000) /*!< Protects Sector 87 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT88] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88_OFS (24) /*!< PROT88 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88 ((uint32_t)0x01000000) /*!< Protects Sector 88 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT89] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89_OFS (25) /*!< PROT89 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89 ((uint32_t)0x02000000) /*!< Protects Sector 89 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT90] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90_OFS (26) /*!< PROT90 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90 ((uint32_t)0x04000000) /*!< Protects Sector 90 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT91] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91_OFS (27) /*!< PROT91 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91 ((uint32_t)0x08000000) /*!< Protects Sector 91 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT92] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92_OFS (28) /*!< PROT92 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92 ((uint32_t)0x10000000) /*!< Protects Sector 92 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT93] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93_OFS (29) /*!< PROT93 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93 ((uint32_t)0x20000000) /*!< Protects Sector 93 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT94] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94_OFS (30) /*!< PROT94 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94 ((uint32_t)0x40000000) /*!< Protects Sector 94 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT95] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95_OFS (31) /*!< PROT95 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95 ((uint32_t)0x80000000) /*!< Protects Sector 95 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT96] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96_OFS ( 0) /*!< PROT96 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96 ((uint32_t)0x00000001) /*!< Protects Sector 96 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT97] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97_OFS ( 1) /*!< PROT97 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97 ((uint32_t)0x00000002) /*!< Protects Sector 97 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT98] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98_OFS ( 2) /*!< PROT98 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98 ((uint32_t)0x00000004) /*!< Protects Sector 98 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT99] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99_OFS ( 3) /*!< PROT99 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99 ((uint32_t)0x00000008) /*!< Protects Sector 99 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT100] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100_OFS ( 4) /*!< PROT100 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100 ((uint32_t)0x00000010) /*!< Protects Sector 100 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT101] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101_OFS ( 5) /*!< PROT101 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101 ((uint32_t)0x00000020) /*!< Protects Sector 101 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT102] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102_OFS ( 6) /*!< PROT102 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102 ((uint32_t)0x00000040) /*!< Protects Sector 102 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT103] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103_OFS ( 7) /*!< PROT103 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103 ((uint32_t)0x00000080) /*!< Protects Sector 103 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT104] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104_OFS ( 8) /*!< PROT104 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104 ((uint32_t)0x00000100) /*!< Protects Sector 104 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT105] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105_OFS ( 9) /*!< PROT105 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105 ((uint32_t)0x00000200) /*!< Protects Sector 105 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT106] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106_OFS (10) /*!< PROT106 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106 ((uint32_t)0x00000400) /*!< Protects Sector 106 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT107] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107_OFS (11) /*!< PROT107 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107 ((uint32_t)0x00000800) /*!< Protects Sector 107 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT108] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108_OFS (12) /*!< PROT108 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108 ((uint32_t)0x00001000) /*!< Protects Sector 108 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT109] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109_OFS (13) /*!< PROT109 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109 ((uint32_t)0x00002000) /*!< Protects Sector 109 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT110] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110_OFS (14) /*!< PROT110 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110 ((uint32_t)0x00004000) /*!< Protects Sector 110 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT111] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111_OFS (15) /*!< PROT111 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111 ((uint32_t)0x00008000) /*!< Protects Sector 111 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT112] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112_OFS (16) /*!< PROT112 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112 ((uint32_t)0x00010000) /*!< Protects Sector 112 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT113] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113_OFS (17) /*!< PROT113 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113 ((uint32_t)0x00020000) /*!< Protects Sector 113 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT114] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114_OFS (18) /*!< PROT114 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114 ((uint32_t)0x00040000) /*!< Protects Sector 114 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT115] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115_OFS (19) /*!< PROT115 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115 ((uint32_t)0x00080000) /*!< Protects Sector 115 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT116] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116_OFS (20) /*!< PROT116 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116 ((uint32_t)0x00100000) /*!< Protects Sector 116 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT117] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117_OFS (21) /*!< PROT117 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117 ((uint32_t)0x00200000) /*!< Protects Sector 117 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT118] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118_OFS (22) /*!< PROT118 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118 ((uint32_t)0x00400000) /*!< Protects Sector 118 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT119] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119_OFS (23) /*!< PROT119 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119 ((uint32_t)0x00800000) /*!< Protects Sector 119 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT120] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120_OFS (24) /*!< PROT120 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120 ((uint32_t)0x01000000) /*!< Protects Sector 120 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT121] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121_OFS (25) /*!< PROT121 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121 ((uint32_t)0x02000000) /*!< Protects Sector 121 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT122] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122_OFS (26) /*!< PROT122 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122 ((uint32_t)0x04000000) /*!< Protects Sector 122 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT123] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123_OFS (27) /*!< PROT123 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123 ((uint32_t)0x08000000) /*!< Protects Sector 123 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT124] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124_OFS (28) /*!< PROT124 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124 ((uint32_t)0x10000000) /*!< Protects Sector 124 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT125] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125_OFS (29) /*!< PROT125 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125 ((uint32_t)0x20000000) /*!< Protects Sector 125 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT126] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126_OFS (30) /*!< PROT126 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126 ((uint32_t)0x40000000) /*!< Protects Sector 126 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT127] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127_OFS (31) /*!< PROT127 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127 ((uint32_t)0x80000000) /*!< Protects Sector 127 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT128] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128_OFS ( 0) /*!< PROT128 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128 ((uint32_t)0x00000001) /*!< Protects Sector 128 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT129] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129_OFS ( 1) /*!< PROT129 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129 ((uint32_t)0x00000002) /*!< Protects Sector 129 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT130] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130_OFS ( 2) /*!< PROT130 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130 ((uint32_t)0x00000004) /*!< Protects Sector 130 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT131] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131_OFS ( 3) /*!< PROT131 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131 ((uint32_t)0x00000008) /*!< Protects Sector 131 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT132] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132_OFS ( 4) /*!< PROT132 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132 ((uint32_t)0x00000010) /*!< Protects Sector 132 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT133] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133_OFS ( 5) /*!< PROT133 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133 ((uint32_t)0x00000020) /*!< Protects Sector 133 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT134] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134_OFS ( 6) /*!< PROT134 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134 ((uint32_t)0x00000040) /*!< Protects Sector 134 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT135] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135_OFS ( 7) /*!< PROT135 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135 ((uint32_t)0x00000080) /*!< Protects Sector 135 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT136] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136_OFS ( 8) /*!< PROT136 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136 ((uint32_t)0x00000100) /*!< Protects Sector 136 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT137] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137_OFS ( 9) /*!< PROT137 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137 ((uint32_t)0x00000200) /*!< Protects Sector 137 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT138] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138_OFS (10) /*!< PROT138 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138 ((uint32_t)0x00000400) /*!< Protects Sector 138 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT139] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139_OFS (11) /*!< PROT139 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139 ((uint32_t)0x00000800) /*!< Protects Sector 139 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT140] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140_OFS (12) /*!< PROT140 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140 ((uint32_t)0x00001000) /*!< Protects Sector 140 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT141] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141_OFS (13) /*!< PROT141 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141 ((uint32_t)0x00002000) /*!< Protects Sector 141 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT142] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142_OFS (14) /*!< PROT142 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142 ((uint32_t)0x00004000) /*!< Protects Sector 142 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT143] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143_OFS (15) /*!< PROT143 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143 ((uint32_t)0x00008000) /*!< Protects Sector 143 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT144] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144_OFS (16) /*!< PROT144 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144 ((uint32_t)0x00010000) /*!< Protects Sector 144 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT145] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145_OFS (17) /*!< PROT145 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145 ((uint32_t)0x00020000) /*!< Protects Sector 145 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT146] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146_OFS (18) /*!< PROT146 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146 ((uint32_t)0x00040000) /*!< Protects Sector 146 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT147] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147_OFS (19) /*!< PROT147 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147 ((uint32_t)0x00080000) /*!< Protects Sector 147 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT148] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148_OFS (20) /*!< PROT148 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148 ((uint32_t)0x00100000) /*!< Protects Sector 148 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT149] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149_OFS (21) /*!< PROT149 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149 ((uint32_t)0x00200000) /*!< Protects Sector 149 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT150] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150_OFS (22) /*!< PROT150 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150 ((uint32_t)0x00400000) /*!< Protects Sector 150 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT151] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151_OFS (23) /*!< PROT151 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151 ((uint32_t)0x00800000) /*!< Protects Sector 151 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT152] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152_OFS (24) /*!< PROT152 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152 ((uint32_t)0x01000000) /*!< Protects Sector 152 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT153] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153_OFS (25) /*!< PROT153 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153 ((uint32_t)0x02000000) /*!< Protects Sector 153 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT154] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154_OFS (26) /*!< PROT154 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154 ((uint32_t)0x04000000) /*!< Protects Sector 154 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT155] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155_OFS (27) /*!< PROT155 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155 ((uint32_t)0x08000000) /*!< Protects Sector 155 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT156] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156_OFS (28) /*!< PROT156 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156 ((uint32_t)0x10000000) /*!< Protects Sector 156 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT157] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157_OFS (29) /*!< PROT157 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157 ((uint32_t)0x20000000) /*!< Protects Sector 157 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT158] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158_OFS (30) /*!< PROT158 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158 ((uint32_t)0x40000000) /*!< Protects Sector 158 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT159] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159_OFS (31) /*!< PROT159 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159 ((uint32_t)0x80000000) /*!< Protects Sector 159 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT160] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160_OFS ( 0) /*!< PROT160 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160 ((uint32_t)0x00000001) /*!< Protects Sector 160 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT161] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161_OFS ( 1) /*!< PROT161 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161 ((uint32_t)0x00000002) /*!< Protects Sector 161 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT162] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162_OFS ( 2) /*!< PROT162 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162 ((uint32_t)0x00000004) /*!< Protects Sector 162 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT163] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163_OFS ( 3) /*!< PROT163 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163 ((uint32_t)0x00000008) /*!< Protects Sector 163 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT164] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164_OFS ( 4) /*!< PROT164 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164 ((uint32_t)0x00000010) /*!< Protects Sector 164 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT165] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165_OFS ( 5) /*!< PROT165 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165 ((uint32_t)0x00000020) /*!< Protects Sector 165 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT166] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166_OFS ( 6) /*!< PROT166 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166 ((uint32_t)0x00000040) /*!< Protects Sector 166 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT167] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167_OFS ( 7) /*!< PROT167 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167 ((uint32_t)0x00000080) /*!< Protects Sector 167 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT168] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168_OFS ( 8) /*!< PROT168 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168 ((uint32_t)0x00000100) /*!< Protects Sector 168 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT169] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169_OFS ( 9) /*!< PROT169 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169 ((uint32_t)0x00000200) /*!< Protects Sector 169 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT170] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170_OFS (10) /*!< PROT170 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170 ((uint32_t)0x00000400) /*!< Protects Sector 170 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT171] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171_OFS (11) /*!< PROT171 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171 ((uint32_t)0x00000800) /*!< Protects Sector 171 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT172] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172_OFS (12) /*!< PROT172 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172 ((uint32_t)0x00001000) /*!< Protects Sector 172 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT173] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173_OFS (13) /*!< PROT173 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173 ((uint32_t)0x00002000) /*!< Protects Sector 173 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT174] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174_OFS (14) /*!< PROT174 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174 ((uint32_t)0x00004000) /*!< Protects Sector 174 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT175] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175_OFS (15) /*!< PROT175 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175 ((uint32_t)0x00008000) /*!< Protects Sector 175 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT176] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176_OFS (16) /*!< PROT176 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176 ((uint32_t)0x00010000) /*!< Protects Sector 176 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT177] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177_OFS (17) /*!< PROT177 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177 ((uint32_t)0x00020000) /*!< Protects Sector 177 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT178] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178_OFS (18) /*!< PROT178 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178 ((uint32_t)0x00040000) /*!< Protects Sector 178 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT179] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179_OFS (19) /*!< PROT179 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179 ((uint32_t)0x00080000) /*!< Protects Sector 179 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT180] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180_OFS (20) /*!< PROT180 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180 ((uint32_t)0x00100000) /*!< Protects Sector 180 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT181] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181_OFS (21) /*!< PROT181 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181 ((uint32_t)0x00200000) /*!< Protects Sector 181 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT182] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182_OFS (22) /*!< PROT182 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182 ((uint32_t)0x00400000) /*!< Protects Sector 182 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT183] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183_OFS (23) /*!< PROT183 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183 ((uint32_t)0x00800000) /*!< Protects Sector 183 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT184] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184_OFS (24) /*!< PROT184 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184 ((uint32_t)0x01000000) /*!< Protects Sector 184 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT185] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185_OFS (25) /*!< PROT185 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185 ((uint32_t)0x02000000) /*!< Protects Sector 185 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT186] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186_OFS (26) /*!< PROT186 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186 ((uint32_t)0x04000000) /*!< Protects Sector 186 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT187] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187_OFS (27) /*!< PROT187 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187 ((uint32_t)0x08000000) /*!< Protects Sector 187 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT188] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188_OFS (28) /*!< PROT188 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188 ((uint32_t)0x10000000) /*!< Protects Sector 188 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT189] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189_OFS (29) /*!< PROT189 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189 ((uint32_t)0x20000000) /*!< Protects Sector 189 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT190] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190_OFS (30) /*!< PROT190 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190 ((uint32_t)0x40000000) /*!< Protects Sector 190 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT191] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191_OFS (31) /*!< PROT191 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191 ((uint32_t)0x80000000) /*!< Protects Sector 191 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT192] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192_OFS ( 0) /*!< PROT192 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192 ((uint32_t)0x00000001) /*!< Protects Sector 192 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT193] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193_OFS ( 1) /*!< PROT193 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193 ((uint32_t)0x00000002) /*!< Protects Sector 193 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT194] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194_OFS ( 2) /*!< PROT194 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194 ((uint32_t)0x00000004) /*!< Protects Sector 194 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT195] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195_OFS ( 3) /*!< PROT195 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195 ((uint32_t)0x00000008) /*!< Protects Sector 195 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT196] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196_OFS ( 4) /*!< PROT196 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196 ((uint32_t)0x00000010) /*!< Protects Sector 196 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT197] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197_OFS ( 5) /*!< PROT197 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197 ((uint32_t)0x00000020) /*!< Protects Sector 197 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT198] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198_OFS ( 6) /*!< PROT198 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198 ((uint32_t)0x00000040) /*!< Protects Sector 198 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT199] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199_OFS ( 7) /*!< PROT199 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199 ((uint32_t)0x00000080) /*!< Protects Sector 199 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT200] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200_OFS ( 8) /*!< PROT200 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200 ((uint32_t)0x00000100) /*!< Protects Sector 200 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT201] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201_OFS ( 9) /*!< PROT201 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201 ((uint32_t)0x00000200) /*!< Protects Sector 201 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT202] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202_OFS (10) /*!< PROT202 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202 ((uint32_t)0x00000400) /*!< Protects Sector 202 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT203] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203_OFS (11) /*!< PROT203 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203 ((uint32_t)0x00000800) /*!< Protects Sector 203 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT204] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204_OFS (12) /*!< PROT204 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204 ((uint32_t)0x00001000) /*!< Protects Sector 204 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT205] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205_OFS (13) /*!< PROT205 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205 ((uint32_t)0x00002000) /*!< Protects Sector 205 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT206] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206_OFS (14) /*!< PROT206 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206 ((uint32_t)0x00004000) /*!< Protects Sector 206 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT207] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207_OFS (15) /*!< PROT207 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207 ((uint32_t)0x00008000) /*!< Protects Sector 207 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT208] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208_OFS (16) /*!< PROT208 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208 ((uint32_t)0x00010000) /*!< Protects Sector 208 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT209] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209_OFS (17) /*!< PROT209 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209 ((uint32_t)0x00020000) /*!< Protects Sector 209 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT210] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210_OFS (18) /*!< PROT210 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210 ((uint32_t)0x00040000) /*!< Protects Sector 210 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT211] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211_OFS (19) /*!< PROT211 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211 ((uint32_t)0x00080000) /*!< Protects Sector 211 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT212] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212_OFS (20) /*!< PROT212 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212 ((uint32_t)0x00100000) /*!< Protects Sector 212 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT213] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213_OFS (21) /*!< PROT213 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213 ((uint32_t)0x00200000) /*!< Protects Sector 213 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT214] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214_OFS (22) /*!< PROT214 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214 ((uint32_t)0x00400000) /*!< Protects Sector 214 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT215] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215_OFS (23) /*!< PROT215 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215 ((uint32_t)0x00800000) /*!< Protects Sector 215 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT216] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216_OFS (24) /*!< PROT216 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216 ((uint32_t)0x01000000) /*!< Protects Sector 216 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT217] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217_OFS (25) /*!< PROT217 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217 ((uint32_t)0x02000000) /*!< Protects Sector 217 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT218] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218_OFS (26) /*!< PROT218 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218 ((uint32_t)0x04000000) /*!< Protects Sector 218 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT219] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219_OFS (27) /*!< PROT219 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219 ((uint32_t)0x08000000) /*!< Protects Sector 219 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT220] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220_OFS (28) /*!< PROT220 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220 ((uint32_t)0x10000000) /*!< Protects Sector 220 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT221] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221_OFS (29) /*!< PROT221 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221 ((uint32_t)0x20000000) /*!< Protects Sector 221 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT222] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222_OFS (30) /*!< PROT222 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222 ((uint32_t)0x40000000) /*!< Protects Sector 222 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT223] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223_OFS (31) /*!< PROT223 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223 ((uint32_t)0x80000000) /*!< Protects Sector 223 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT224] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224_OFS ( 0) /*!< PROT224 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224 ((uint32_t)0x00000001) /*!< Protects Sector 224 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT225] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225_OFS ( 1) /*!< PROT225 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225 ((uint32_t)0x00000002) /*!< Protects Sector 225 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT226] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226_OFS ( 2) /*!< PROT226 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226 ((uint32_t)0x00000004) /*!< Protects Sector 226 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT227] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227_OFS ( 3) /*!< PROT227 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227 ((uint32_t)0x00000008) /*!< Protects Sector 227 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT228] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228_OFS ( 4) /*!< PROT228 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228 ((uint32_t)0x00000010) /*!< Protects Sector 228 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT229] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229_OFS ( 5) /*!< PROT229 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229 ((uint32_t)0x00000020) /*!< Protects Sector 229 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT230] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230_OFS ( 6) /*!< PROT230 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230 ((uint32_t)0x00000040) /*!< Protects Sector 230 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT231] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231_OFS ( 7) /*!< PROT231 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231 ((uint32_t)0x00000080) /*!< Protects Sector 231 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT232] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232_OFS ( 8) /*!< PROT232 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232 ((uint32_t)0x00000100) /*!< Protects Sector 232 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT233] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233_OFS ( 9) /*!< PROT233 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233 ((uint32_t)0x00000200) /*!< Protects Sector 233 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT234] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234_OFS (10) /*!< PROT234 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234 ((uint32_t)0x00000400) /*!< Protects Sector 234 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT235] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235_OFS (11) /*!< PROT235 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235 ((uint32_t)0x00000800) /*!< Protects Sector 235 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT236] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236_OFS (12) /*!< PROT236 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236 ((uint32_t)0x00001000) /*!< Protects Sector 236 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT237] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237_OFS (13) /*!< PROT237 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237 ((uint32_t)0x00002000) /*!< Protects Sector 237 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT238] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238_OFS (14) /*!< PROT238 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238 ((uint32_t)0x00004000) /*!< Protects Sector 238 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT239] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239_OFS (15) /*!< PROT239 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239 ((uint32_t)0x00008000) /*!< Protects Sector 239 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT240] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240_OFS (16) /*!< PROT240 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240 ((uint32_t)0x00010000) /*!< Protects Sector 240 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT241] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241_OFS (17) /*!< PROT241 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241 ((uint32_t)0x00020000) /*!< Protects Sector 241 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT242] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242_OFS (18) /*!< PROT242 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242 ((uint32_t)0x00040000) /*!< Protects Sector 242 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT243] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243_OFS (19) /*!< PROT243 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243 ((uint32_t)0x00080000) /*!< Protects Sector 243 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT244] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244_OFS (20) /*!< PROT244 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244 ((uint32_t)0x00100000) /*!< Protects Sector 244 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT245] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245_OFS (21) /*!< PROT245 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245 ((uint32_t)0x00200000) /*!< Protects Sector 245 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT246] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246_OFS (22) /*!< PROT246 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246 ((uint32_t)0x00400000) /*!< Protects Sector 246 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT247] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247_OFS (23) /*!< PROT247 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247 ((uint32_t)0x00800000) /*!< Protects Sector 247 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT248] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248_OFS (24) /*!< PROT248 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248 ((uint32_t)0x01000000) /*!< Protects Sector 248 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT249] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249_OFS (25) /*!< PROT249 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249 ((uint32_t)0x02000000) /*!< Protects Sector 249 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT250] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250_OFS (26) /*!< PROT250 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250 ((uint32_t)0x04000000) /*!< Protects Sector 250 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT251] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251_OFS (27) /*!< PROT251 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251 ((uint32_t)0x08000000) /*!< Protects Sector 251 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT252] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252_OFS (28) /*!< PROT252 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252 ((uint32_t)0x10000000) /*!< Protects Sector 252 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT253] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253_OFS (29) /*!< PROT253 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253 ((uint32_t)0x20000000) /*!< Protects Sector 253 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT254] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254_OFS (30) /*!< PROT254 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254 ((uint32_t)0x40000000) /*!< Protects Sector 254 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT255] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255_OFS (31) /*!< PROT255 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255 ((uint32_t)0x80000000) /*!< Protects Sector 255 from program or erase */ - -/****************************************************************************** -* FL_BOOTOVER_MAILBOX Bits -******************************************************************************/ - -/****************************************************************************** -* FPB Bits -******************************************************************************/ - - -/****************************************************************************** -* FPU Bits -******************************************************************************/ - - -/****************************************************************************** -* ITM Bits -******************************************************************************/ - - -/****************************************************************************** -* LCD_F Bits -******************************************************************************/ -/* LCD_F_CTL[ON] Bits */ -#define LCD_F_CTL_ON_OFS ( 0) /*!< LCDON Bit Offset */ -#define LCD_F_CTL_ON ((uint32_t)0x00000001) /*!< LCD on */ -/* LCD_F_CTL[LP] Bits */ -#define LCD_F_CTL_LP_OFS ( 1) /*!< LCDLP Bit Offset */ -#define LCD_F_CTL_LP ((uint32_t)0x00000002) /*!< LCD Low-power Waveform */ -/* LCD_F_CTL[SON] Bits */ -#define LCD_F_CTL_SON_OFS ( 2) /*!< LCDSON Bit Offset */ -#define LCD_F_CTL_SON ((uint32_t)0x00000004) /*!< LCD segments on */ -/* LCD_F_CTL[MX] Bits */ -#define LCD_F_CTL_MX_OFS ( 3) /*!< LCDMXx Bit Offset */ -#define LCD_F_CTL_MX_MASK ((uint32_t)0x00000038) /*!< LCDMXx Bit Mask */ -#define LCD_F_CTL_MX0 ((uint32_t)0x00000008) /*!< MX Bit 0 */ -#define LCD_F_CTL_MX1 ((uint32_t)0x00000010) /*!< MX Bit 1 */ -#define LCD_F_CTL_MX2 ((uint32_t)0x00000020) /*!< MX Bit 2 */ -#define LCD_F_CTL_MX_0 ((uint32_t)0x00000000) /*!< Static */ -#define LCD_F_CTL_MX_1 ((uint32_t)0x00000008) /*!< 2-mux */ -#define LCD_F_CTL_MX_2 ((uint32_t)0x00000010) /*!< 3-mux */ -#define LCD_F_CTL_MX_3 ((uint32_t)0x00000018) /*!< 4-mux */ -#define LCD_F_CTL_MX_4 ((uint32_t)0x00000020) /*!< 5-mux */ -#define LCD_F_CTL_MX_5 ((uint32_t)0x00000028) /*!< 6-mux */ -#define LCD_F_CTL_MX_6 ((uint32_t)0x00000030) /*!< 7-mux */ -#define LCD_F_CTL_MX_7 ((uint32_t)0x00000038) /*!< 8-mux */ -/* LCD_F_CTL[PRE] Bits */ -#define LCD_F_CTL_PRE_OFS ( 8) /*!< LCDPREx Bit Offset */ -#define LCD_F_CTL_PRE_MASK ((uint32_t)0x00000700) /*!< LCDPREx Bit Mask */ -#define LCD_F_CTL_PRE0 ((uint32_t)0x00000100) /*!< PRE Bit 0 */ -#define LCD_F_CTL_PRE1 ((uint32_t)0x00000200) /*!< PRE Bit 1 */ -#define LCD_F_CTL_PRE2 ((uint32_t)0x00000400) /*!< PRE Bit 2 */ -#define LCD_F_CTL_PRE_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_CTL_PRE_1 ((uint32_t)0x00000100) /*!< Divide by 2 */ -#define LCD_F_CTL_PRE_2 ((uint32_t)0x00000200) /*!< Divide by 4 */ -#define LCD_F_CTL_PRE_3 ((uint32_t)0x00000300) /*!< Divide by 8 */ -#define LCD_F_CTL_PRE_4 ((uint32_t)0x00000400) /*!< Divide by 16 */ -#define LCD_F_CTL_PRE_5 ((uint32_t)0x00000500) /*!< Divide by 32 */ -#define LCD_F_CTL_PRE_6 ((uint32_t)0x00000600) /*!< Reserved (defaults to divide by 32) */ -#define LCD_F_CTL_PRE_7 ((uint32_t)0x00000700) /*!< Reserved (defaults to divide by 32) */ -/* LCD_F_CTL[DIV] Bits */ -#define LCD_F_CTL_DIV_OFS (11) /*!< LCDDIVx Bit Offset */ -#define LCD_F_CTL_DIV_MASK ((uint32_t)0x0000F800) /*!< LCDDIVx Bit Mask */ -#define LCD_F_CTL_DIV0 ((uint32_t)0x00000800) /*!< DIV Bit 0 */ -#define LCD_F_CTL_DIV1 ((uint32_t)0x00001000) /*!< DIV Bit 1 */ -#define LCD_F_CTL_DIV2 ((uint32_t)0x00002000) /*!< DIV Bit 2 */ -#define LCD_F_CTL_DIV3 ((uint32_t)0x00004000) /*!< DIV Bit 3 */ -#define LCD_F_CTL_DIV4 ((uint32_t)0x00008000) /*!< DIV Bit 4 */ -#define LCD_F_CTL_DIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_CTL_DIV_1 ((uint32_t)0x00000800) /*!< Divide by 2 */ -#define LCD_F_CTL_DIV_2 ((uint32_t)0x00001000) /*!< Divide by 3 */ -#define LCD_F_CTL_DIV_3 ((uint32_t)0x00001800) /*!< Divide by 4 */ -#define LCD_F_CTL_DIV_4 ((uint32_t)0x00002000) /*!< Divide by 5 */ -#define LCD_F_CTL_DIV_5 ((uint32_t)0x00002800) /*!< Divide by 6 */ -#define LCD_F_CTL_DIV_6 ((uint32_t)0x00003000) /*!< Divide by 7 */ -#define LCD_F_CTL_DIV_7 ((uint32_t)0x00003800) /*!< Divide by 8 */ -#define LCD_F_CTL_DIV_8 ((uint32_t)0x00004000) /*!< Divide by 9 */ -#define LCD_F_CTL_DIV_9 ((uint32_t)0x00004800) /*!< Divide by 10 */ -#define LCD_F_CTL_DIV_10 ((uint32_t)0x00005000) /*!< Divide by 11 */ -#define LCD_F_CTL_DIV_11 ((uint32_t)0x00005800) /*!< Divide by 12 */ -#define LCD_F_CTL_DIV_12 ((uint32_t)0x00006000) /*!< Divide by 13 */ -#define LCD_F_CTL_DIV_13 ((uint32_t)0x00006800) /*!< Divide by 14 */ -#define LCD_F_CTL_DIV_14 ((uint32_t)0x00007000) /*!< Divide by 15 */ -#define LCD_F_CTL_DIV_15 ((uint32_t)0x00007800) /*!< Divide by 16 */ -#define LCD_F_CTL_DIV_16 ((uint32_t)0x00008000) /*!< Divide by 17 */ -#define LCD_F_CTL_DIV_17 ((uint32_t)0x00008800) /*!< Divide by 18 */ -#define LCD_F_CTL_DIV_18 ((uint32_t)0x00009000) /*!< Divide by 19 */ -#define LCD_F_CTL_DIV_19 ((uint32_t)0x00009800) /*!< Divide by 20 */ -#define LCD_F_CTL_DIV_20 ((uint32_t)0x0000A000) /*!< Divide by 21 */ -#define LCD_F_CTL_DIV_21 ((uint32_t)0x0000A800) /*!< Divide by 22 */ -#define LCD_F_CTL_DIV_22 ((uint32_t)0x0000B000) /*!< Divide by 23 */ -#define LCD_F_CTL_DIV_23 ((uint32_t)0x0000B800) /*!< Divide by 24 */ -#define LCD_F_CTL_DIV_24 ((uint32_t)0x0000C000) /*!< Divide by 25 */ -#define LCD_F_CTL_DIV_25 ((uint32_t)0x0000C800) /*!< Divide by 26 */ -#define LCD_F_CTL_DIV_26 ((uint32_t)0x0000D000) /*!< Divide by 27 */ -#define LCD_F_CTL_DIV_27 ((uint32_t)0x0000D800) /*!< Divide by 28 */ -#define LCD_F_CTL_DIV_28 ((uint32_t)0x0000E000) /*!< Divide by 29 */ -#define LCD_F_CTL_DIV_29 ((uint32_t)0x0000E800) /*!< Divide by 30 */ -#define LCD_F_CTL_DIV_30 ((uint32_t)0x0000F000) /*!< Divide by 31 */ -#define LCD_F_CTL_DIV_31 ((uint32_t)0x0000F800) /*!< Divide by 32 */ -/* LCD_F_CTL[SSEL] Bits */ -#define LCD_F_CTL_SSEL_OFS (16) /*!< LCDSSEL Bit Offset */ -#define LCD_F_CTL_SSEL_MASK ((uint32_t)0x00030000) /*!< LCDSSEL Bit Mask */ -#define LCD_F_CTL_SSEL0 ((uint32_t)0x00010000) /*!< SSEL Bit 0 */ -#define LCD_F_CTL_SSEL1 ((uint32_t)0x00020000) /*!< SSEL Bit 1 */ -#define LCD_F_CTL_SSEL_0 ((uint32_t)0x00000000) /*!< ACLK */ -#define LCD_F_CTL_SSEL_1 ((uint32_t)0x00010000) /*!< VLOCLK */ -#define LCD_F_CTL_SSEL_2 ((uint32_t)0x00020000) /*!< REFOCLK */ -#define LCD_F_CTL_SSEL_3 ((uint32_t)0x00030000) /*!< LFXTCLK */ -/* LCD_F_BMCTL[BLKMOD] Bits */ -#define LCD_F_BMCTL_BLKMOD_OFS ( 0) /*!< LCDBLKMODx Bit Offset */ -#define LCD_F_BMCTL_BLKMOD_MASK ((uint32_t)0x00000003) /*!< LCDBLKMODx Bit Mask */ -#define LCD_F_BMCTL_BLKMOD0 ((uint32_t)0x00000001) /*!< BLKMOD Bit 0 */ -#define LCD_F_BMCTL_BLKMOD1 ((uint32_t)0x00000002) /*!< BLKMOD Bit 1 */ -#define LCD_F_BMCTL_BLKMOD_0 ((uint32_t)0x00000000) /*!< Blinking disabled */ -#define LCD_F_BMCTL_BLKMOD_1 ((uint32_t)0x00000001) /*!< Blinking of individual segments as enabled in blinking memory register */ - /* LCDBMx. */ -#define LCD_F_BMCTL_BLKMOD_2 ((uint32_t)0x00000002) /*!< Blinking of all segments */ -#define LCD_F_BMCTL_BLKMOD_3 ((uint32_t)0x00000003) /*!< Switching between display contents as stored in LCDMx and LCDBMx memory */ - /* registers. */ -/* LCD_F_BMCTL[BLKPRE] Bits */ -#define LCD_F_BMCTL_BLKPRE_OFS ( 2) /*!< LCDBLKPREx Bit Offset */ -#define LCD_F_BMCTL_BLKPRE_MASK ((uint32_t)0x0000001C) /*!< LCDBLKPREx Bit Mask */ -#define LCD_F_BMCTL_BLKPRE0 ((uint32_t)0x00000004) /*!< BLKPRE Bit 0 */ -#define LCD_F_BMCTL_BLKPRE1 ((uint32_t)0x00000008) /*!< BLKPRE Bit 1 */ -#define LCD_F_BMCTL_BLKPRE2 ((uint32_t)0x00000010) /*!< BLKPRE Bit 2 */ -#define LCD_F_BMCTL_BLKPRE_0 ((uint32_t)0x00000000) /*!< Divide by 512 */ -#define LCD_F_BMCTL_BLKPRE_1 ((uint32_t)0x00000004) /*!< Divide by 1024 */ -#define LCD_F_BMCTL_BLKPRE_2 ((uint32_t)0x00000008) /*!< Divide by 2048 */ -#define LCD_F_BMCTL_BLKPRE_3 ((uint32_t)0x0000000C) /*!< Divide by 4096 */ -#define LCD_F_BMCTL_BLKPRE_4 ((uint32_t)0x00000010) /*!< Divide by 8162 */ -#define LCD_F_BMCTL_BLKPRE_5 ((uint32_t)0x00000014) /*!< Divide by 16384 */ -#define LCD_F_BMCTL_BLKPRE_6 ((uint32_t)0x00000018) /*!< Divide by 32768 */ -#define LCD_F_BMCTL_BLKPRE_7 ((uint32_t)0x0000001C) /*!< Divide by 65536 */ -/* LCD_F_BMCTL[BLKDIV] Bits */ -#define LCD_F_BMCTL_BLKDIV_OFS ( 5) /*!< LCDBLKDIVx Bit Offset */ -#define LCD_F_BMCTL_BLKDIV_MASK ((uint32_t)0x000000E0) /*!< LCDBLKDIVx Bit Mask */ -#define LCD_F_BMCTL_BLKDIV0 ((uint32_t)0x00000020) /*!< BLKDIV Bit 0 */ -#define LCD_F_BMCTL_BLKDIV1 ((uint32_t)0x00000040) /*!< BLKDIV Bit 1 */ -#define LCD_F_BMCTL_BLKDIV2 ((uint32_t)0x00000080) /*!< BLKDIV Bit 2 */ -#define LCD_F_BMCTL_BLKDIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_BMCTL_BLKDIV_1 ((uint32_t)0x00000020) /*!< Divide by 2 */ -#define LCD_F_BMCTL_BLKDIV_2 ((uint32_t)0x00000040) /*!< Divide by 3 */ -#define LCD_F_BMCTL_BLKDIV_3 ((uint32_t)0x00000060) /*!< Divide by 4 */ -#define LCD_F_BMCTL_BLKDIV_4 ((uint32_t)0x00000080) /*!< Divide by 5 */ -#define LCD_F_BMCTL_BLKDIV_5 ((uint32_t)0x000000A0) /*!< Divide by 6 */ -#define LCD_F_BMCTL_BLKDIV_6 ((uint32_t)0x000000C0) /*!< Divide by 7 */ -#define LCD_F_BMCTL_BLKDIV_7 ((uint32_t)0x000000E0) /*!< Divide by 8 */ -/* LCD_F_BMCTL[DISP] Bits */ -#define LCD_F_BMCTL_DISP_OFS (16) /*!< LCDDISP Bit Offset */ -#define LCD_F_BMCTL_DISP ((uint32_t)0x00010000) /*!< Select LCD memory registers for display */ -/* LCD_F_BMCTL[CLRM] Bits */ -#define LCD_F_BMCTL_CLRM_OFS (17) /*!< LCDCLRM Bit Offset */ -#define LCD_F_BMCTL_CLRM ((uint32_t)0x00020000) /*!< Clear LCD memory */ -/* LCD_F_BMCTL[CLRBM] Bits */ -#define LCD_F_BMCTL_CLRBM_OFS (18) /*!< LCDCLRBM Bit Offset */ -#define LCD_F_BMCTL_CLRBM ((uint32_t)0x00040000) /*!< Clear LCD blinking memory */ -/* LCD_F_VCTL[LCD2B] Bits */ -#define LCD_F_VCTL_LCD2B_OFS ( 0) /*!< LCD2B Bit Offset */ -#define LCD_F_VCTL_LCD2B ((uint32_t)0x00000001) /*!< Bias select. */ -/* LCD_F_VCTL[EXTBIAS] Bits */ -#define LCD_F_VCTL_EXTBIAS_OFS ( 5) /*!< LCDEXTBIAS Bit Offset */ -#define LCD_F_VCTL_EXTBIAS ((uint32_t)0x00000020) /*!< V2 to V4 voltage select */ -/* LCD_F_VCTL[R03EXT] Bits */ -#define LCD_F_VCTL_R03EXT_OFS ( 6) /*!< R03EXT Bit Offset */ -#define LCD_F_VCTL_R03EXT ((uint32_t)0x00000040) /*!< V5 voltage select */ -/* LCD_F_VCTL[REXT] Bits */ -#define LCD_F_VCTL_REXT_OFS ( 7) /*!< LCDREXT Bit Offset */ -#define LCD_F_VCTL_REXT ((uint32_t)0x00000080) /*!< V2 to V4 voltage on external Rx3 pins */ -/* LCD_F_PCTL0[S0] Bits */ -#define LCD_F_PCTL0_S0_OFS ( 0) /*!< LCDS0 Bit Offset */ -#define LCD_F_PCTL0_S0 ((uint32_t)0x00000001) /*!< LCD pin 0 enable */ -/* LCD_F_PCTL0[S1] Bits */ -#define LCD_F_PCTL0_S1_OFS ( 1) /*!< LCDS1 Bit Offset */ -#define LCD_F_PCTL0_S1 ((uint32_t)0x00000002) /*!< LCD pin 1 enable */ -/* LCD_F_PCTL0[S2] Bits */ -#define LCD_F_PCTL0_S2_OFS ( 2) /*!< LCDS2 Bit Offset */ -#define LCD_F_PCTL0_S2 ((uint32_t)0x00000004) /*!< LCD pin 2 enable */ -/* LCD_F_PCTL0[S3] Bits */ -#define LCD_F_PCTL0_S3_OFS ( 3) /*!< LCDS3 Bit Offset */ -#define LCD_F_PCTL0_S3 ((uint32_t)0x00000008) /*!< LCD pin 3 enable */ -/* LCD_F_PCTL0[S4] Bits */ -#define LCD_F_PCTL0_S4_OFS ( 4) /*!< LCDS4 Bit Offset */ -#define LCD_F_PCTL0_S4 ((uint32_t)0x00000010) /*!< LCD pin 4 enable */ -/* LCD_F_PCTL0[S5] Bits */ -#define LCD_F_PCTL0_S5_OFS ( 5) /*!< LCDS5 Bit Offset */ -#define LCD_F_PCTL0_S5 ((uint32_t)0x00000020) /*!< LCD pin 5 enable */ -/* LCD_F_PCTL0[S6] Bits */ -#define LCD_F_PCTL0_S6_OFS ( 6) /*!< LCDS6 Bit Offset */ -#define LCD_F_PCTL0_S6 ((uint32_t)0x00000040) /*!< LCD pin 6 enable */ -/* LCD_F_PCTL0[S7] Bits */ -#define LCD_F_PCTL0_S7_OFS ( 7) /*!< LCDS7 Bit Offset */ -#define LCD_F_PCTL0_S7 ((uint32_t)0x00000080) /*!< LCD pin 7 enable */ -/* LCD_F_PCTL0[S8] Bits */ -#define LCD_F_PCTL0_S8_OFS ( 8) /*!< LCDS8 Bit Offset */ -#define LCD_F_PCTL0_S8 ((uint32_t)0x00000100) /*!< LCD pin 8 enable */ -/* LCD_F_PCTL0[S9] Bits */ -#define LCD_F_PCTL0_S9_OFS ( 9) /*!< LCDS9 Bit Offset */ -#define LCD_F_PCTL0_S9 ((uint32_t)0x00000200) /*!< LCD pin 9 enable */ -/* LCD_F_PCTL0[S10] Bits */ -#define LCD_F_PCTL0_S10_OFS (10) /*!< LCDS10 Bit Offset */ -#define LCD_F_PCTL0_S10 ((uint32_t)0x00000400) /*!< LCD pin 10 enable */ -/* LCD_F_PCTL0[S11] Bits */ -#define LCD_F_PCTL0_S11_OFS (11) /*!< LCDS11 Bit Offset */ -#define LCD_F_PCTL0_S11 ((uint32_t)0x00000800) /*!< LCD pin 11 enable */ -/* LCD_F_PCTL0[S12] Bits */ -#define LCD_F_PCTL0_S12_OFS (12) /*!< LCDS12 Bit Offset */ -#define LCD_F_PCTL0_S12 ((uint32_t)0x00001000) /*!< LCD pin 12 enable */ -/* LCD_F_PCTL0[S13] Bits */ -#define LCD_F_PCTL0_S13_OFS (13) /*!< LCDS13 Bit Offset */ -#define LCD_F_PCTL0_S13 ((uint32_t)0x00002000) /*!< LCD pin 13 enable */ -/* LCD_F_PCTL0[S14] Bits */ -#define LCD_F_PCTL0_S14_OFS (14) /*!< LCDS14 Bit Offset */ -#define LCD_F_PCTL0_S14 ((uint32_t)0x00004000) /*!< LCD pin 14 enable */ -/* LCD_F_PCTL0[S15] Bits */ -#define LCD_F_PCTL0_S15_OFS (15) /*!< LCDS15 Bit Offset */ -#define LCD_F_PCTL0_S15 ((uint32_t)0x00008000) /*!< LCD pin 15 enable */ -/* LCD_F_PCTL0[S16] Bits */ -#define LCD_F_PCTL0_S16_OFS (16) /*!< LCDS16 Bit Offset */ -#define LCD_F_PCTL0_S16 ((uint32_t)0x00010000) /*!< LCD pin 16 enable */ -/* LCD_F_PCTL0[S17] Bits */ -#define LCD_F_PCTL0_S17_OFS (17) /*!< LCDS17 Bit Offset */ -#define LCD_F_PCTL0_S17 ((uint32_t)0x00020000) /*!< LCD pin 17 enable */ -/* LCD_F_PCTL0[S18] Bits */ -#define LCD_F_PCTL0_S18_OFS (18) /*!< LCDS18 Bit Offset */ -#define LCD_F_PCTL0_S18 ((uint32_t)0x00040000) /*!< LCD pin 18 enable */ -/* LCD_F_PCTL0[S19] Bits */ -#define LCD_F_PCTL0_S19_OFS (19) /*!< LCDS19 Bit Offset */ -#define LCD_F_PCTL0_S19 ((uint32_t)0x00080000) /*!< LCD pin 19 enable */ -/* LCD_F_PCTL0[S20] Bits */ -#define LCD_F_PCTL0_S20_OFS (20) /*!< LCDS20 Bit Offset */ -#define LCD_F_PCTL0_S20 ((uint32_t)0x00100000) /*!< LCD pin 20 enable */ -/* LCD_F_PCTL0[S21] Bits */ -#define LCD_F_PCTL0_S21_OFS (21) /*!< LCDS21 Bit Offset */ -#define LCD_F_PCTL0_S21 ((uint32_t)0x00200000) /*!< LCD pin 21 enable */ -/* LCD_F_PCTL0[S22] Bits */ -#define LCD_F_PCTL0_S22_OFS (22) /*!< LCDS22 Bit Offset */ -#define LCD_F_PCTL0_S22 ((uint32_t)0x00400000) /*!< LCD pin 22 enable */ -/* LCD_F_PCTL0[S23] Bits */ -#define LCD_F_PCTL0_S23_OFS (23) /*!< LCDS23 Bit Offset */ -#define LCD_F_PCTL0_S23 ((uint32_t)0x00800000) /*!< LCD pin 23 enable */ -/* LCD_F_PCTL0[S24] Bits */ -#define LCD_F_PCTL0_S24_OFS (24) /*!< LCDS24 Bit Offset */ -#define LCD_F_PCTL0_S24 ((uint32_t)0x01000000) /*!< LCD pin 24 enable */ -/* LCD_F_PCTL0[S25] Bits */ -#define LCD_F_PCTL0_S25_OFS (25) /*!< LCDS25 Bit Offset */ -#define LCD_F_PCTL0_S25 ((uint32_t)0x02000000) /*!< LCD pin 25 enable */ -/* LCD_F_PCTL0[S26] Bits */ -#define LCD_F_PCTL0_S26_OFS (26) /*!< LCDS26 Bit Offset */ -#define LCD_F_PCTL0_S26 ((uint32_t)0x04000000) /*!< LCD pin 26 enable */ -/* LCD_F_PCTL0[S27] Bits */ -#define LCD_F_PCTL0_S27_OFS (27) /*!< LCDS27 Bit Offset */ -#define LCD_F_PCTL0_S27 ((uint32_t)0x08000000) /*!< LCD pin 27 enable */ -/* LCD_F_PCTL0[S28] Bits */ -#define LCD_F_PCTL0_S28_OFS (28) /*!< LCDS28 Bit Offset */ -#define LCD_F_PCTL0_S28 ((uint32_t)0x10000000) /*!< LCD pin 28 enable */ -/* LCD_F_PCTL0[S29] Bits */ -#define LCD_F_PCTL0_S29_OFS (29) /*!< LCDS29 Bit Offset */ -#define LCD_F_PCTL0_S29 ((uint32_t)0x20000000) /*!< LCD pin 29 enable */ -/* LCD_F_PCTL0[S30] Bits */ -#define LCD_F_PCTL0_S30_OFS (30) /*!< LCDS30 Bit Offset */ -#define LCD_F_PCTL0_S30 ((uint32_t)0x40000000) /*!< LCD pin 30 enable */ -/* LCD_F_PCTL0[S31] Bits */ -#define LCD_F_PCTL0_S31_OFS (31) /*!< LCDS31 Bit Offset */ -#define LCD_F_PCTL0_S31 ((uint32_t)0x80000000) /*!< LCD pin 31 enable */ -/* LCD_F_PCTL1[S32] Bits */ -#define LCD_F_PCTL1_S32_OFS ( 0) /*!< LCDS32 Bit Offset */ -#define LCD_F_PCTL1_S32 ((uint32_t)0x00000001) /*!< LCD pin 32 enable */ -/* LCD_F_PCTL1[S33] Bits */ -#define LCD_F_PCTL1_S33_OFS ( 1) /*!< LCDS33 Bit Offset */ -#define LCD_F_PCTL1_S33 ((uint32_t)0x00000002) /*!< LCD pin 33 enable */ -/* LCD_F_PCTL1[S34] Bits */ -#define LCD_F_PCTL1_S34_OFS ( 2) /*!< LCDS34 Bit Offset */ -#define LCD_F_PCTL1_S34 ((uint32_t)0x00000004) /*!< LCD pin 34 enable */ -/* LCD_F_PCTL1[S35] Bits */ -#define LCD_F_PCTL1_S35_OFS ( 3) /*!< LCDS35 Bit Offset */ -#define LCD_F_PCTL1_S35 ((uint32_t)0x00000008) /*!< LCD pin 35 enable */ -/* LCD_F_PCTL1[S36] Bits */ -#define LCD_F_PCTL1_S36_OFS ( 4) /*!< LCDS36 Bit Offset */ -#define LCD_F_PCTL1_S36 ((uint32_t)0x00000010) /*!< LCD pin 36 enable */ -/* LCD_F_PCTL1[S37] Bits */ -#define LCD_F_PCTL1_S37_OFS ( 5) /*!< LCDS37 Bit Offset */ -#define LCD_F_PCTL1_S37 ((uint32_t)0x00000020) /*!< LCD pin 37 enable */ -/* LCD_F_PCTL1[S38] Bits */ -#define LCD_F_PCTL1_S38_OFS ( 6) /*!< LCDS38 Bit Offset */ -#define LCD_F_PCTL1_S38 ((uint32_t)0x00000040) /*!< LCD pin 38 enable */ -/* LCD_F_PCTL1[S39] Bits */ -#define LCD_F_PCTL1_S39_OFS ( 7) /*!< LCDS39 Bit Offset */ -#define LCD_F_PCTL1_S39 ((uint32_t)0x00000080) /*!< LCD pin 39 enable */ -/* LCD_F_PCTL1[S40] Bits */ -#define LCD_F_PCTL1_S40_OFS ( 8) /*!< LCDS40 Bit Offset */ -#define LCD_F_PCTL1_S40 ((uint32_t)0x00000100) /*!< LCD pin 40 enable */ -/* LCD_F_PCTL1[S41] Bits */ -#define LCD_F_PCTL1_S41_OFS ( 9) /*!< LCDS41 Bit Offset */ -#define LCD_F_PCTL1_S41 ((uint32_t)0x00000200) /*!< LCD pin 41 enable */ -/* LCD_F_PCTL1[S42] Bits */ -#define LCD_F_PCTL1_S42_OFS (10) /*!< LCDS42 Bit Offset */ -#define LCD_F_PCTL1_S42 ((uint32_t)0x00000400) /*!< LCD pin 42 enable */ -/* LCD_F_PCTL1[S43] Bits */ -#define LCD_F_PCTL1_S43_OFS (11) /*!< LCDS43 Bit Offset */ -#define LCD_F_PCTL1_S43 ((uint32_t)0x00000800) /*!< LCD pin 43 enable */ -/* LCD_F_PCTL1[S44] Bits */ -#define LCD_F_PCTL1_S44_OFS (12) /*!< LCDS44 Bit Offset */ -#define LCD_F_PCTL1_S44 ((uint32_t)0x00001000) /*!< LCD pin 44 enable */ -/* LCD_F_PCTL1[S45] Bits */ -#define LCD_F_PCTL1_S45_OFS (13) /*!< LCDS45 Bit Offset */ -#define LCD_F_PCTL1_S45 ((uint32_t)0x00002000) /*!< LCD pin 45 enable */ -/* LCD_F_PCTL1[S46] Bits */ -#define LCD_F_PCTL1_S46_OFS (14) /*!< LCDS46 Bit Offset */ -#define LCD_F_PCTL1_S46 ((uint32_t)0x00004000) /*!< LCD pin 46 enable */ -/* LCD_F_PCTL1[S47] Bits */ -#define LCD_F_PCTL1_S47_OFS (15) /*!< LCDS47 Bit Offset */ -#define LCD_F_PCTL1_S47 ((uint32_t)0x00008000) /*!< LCD pin 47 enable */ -/* LCD_F_PCTL1[S48] Bits */ -#define LCD_F_PCTL1_S48_OFS (16) /*!< LCDS48 Bit Offset */ -#define LCD_F_PCTL1_S48 ((uint32_t)0x00010000) /*!< LCD pin 48 enable */ -/* LCD_F_PCTL1[S49] Bits */ -#define LCD_F_PCTL1_S49_OFS (17) /*!< LCDS49 Bit Offset */ -#define LCD_F_PCTL1_S49 ((uint32_t)0x00020000) /*!< LCD pin 49 enable */ -/* LCD_F_PCTL1[S50] Bits */ -#define LCD_F_PCTL1_S50_OFS (18) /*!< LCDS50 Bit Offset */ -#define LCD_F_PCTL1_S50 ((uint32_t)0x00040000) /*!< LCD pin 50 enable */ -/* LCD_F_PCTL1[S51] Bits */ -#define LCD_F_PCTL1_S51_OFS (19) /*!< LCDS51 Bit Offset */ -#define LCD_F_PCTL1_S51 ((uint32_t)0x00080000) /*!< LCD pin 51 enable */ -/* LCD_F_PCTL1[S52] Bits */ -#define LCD_F_PCTL1_S52_OFS (20) /*!< LCDS52 Bit Offset */ -#define LCD_F_PCTL1_S52 ((uint32_t)0x00100000) /*!< LCD pin 52 enable */ -/* LCD_F_PCTL1[S53] Bits */ -#define LCD_F_PCTL1_S53_OFS (21) /*!< LCDS53 Bit Offset */ -#define LCD_F_PCTL1_S53 ((uint32_t)0x00200000) /*!< LCD pin 53 enable */ -/* LCD_F_PCTL1[S54] Bits */ -#define LCD_F_PCTL1_S54_OFS (22) /*!< LCDS54 Bit Offset */ -#define LCD_F_PCTL1_S54 ((uint32_t)0x00400000) /*!< LCD pin 54 enable */ -/* LCD_F_PCTL1[S55] Bits */ -#define LCD_F_PCTL1_S55_OFS (23) /*!< LCDS55 Bit Offset */ -#define LCD_F_PCTL1_S55 ((uint32_t)0x00800000) /*!< LCD pin 55 enable */ -/* LCD_F_PCTL1[S56] Bits */ -#define LCD_F_PCTL1_S56_OFS (24) /*!< LCDS56 Bit Offset */ -#define LCD_F_PCTL1_S56 ((uint32_t)0x01000000) /*!< LCD pin 56 enable */ -/* LCD_F_PCTL1[S57] Bits */ -#define LCD_F_PCTL1_S57_OFS (25) /*!< LCDS57 Bit Offset */ -#define LCD_F_PCTL1_S57 ((uint32_t)0x02000000) /*!< LCD pin 57 enable */ -/* LCD_F_PCTL1[S58] Bits */ -#define LCD_F_PCTL1_S58_OFS (26) /*!< LCDS58 Bit Offset */ -#define LCD_F_PCTL1_S58 ((uint32_t)0x04000000) /*!< LCD pin 58 enable */ -/* LCD_F_PCTL1[S59] Bits */ -#define LCD_F_PCTL1_S59_OFS (27) /*!< LCDS59 Bit Offset */ -#define LCD_F_PCTL1_S59 ((uint32_t)0x08000000) /*!< LCD pin 59 enable */ -/* LCD_F_PCTL1[S60] Bits */ -#define LCD_F_PCTL1_S60_OFS (28) /*!< LCDS60 Bit Offset */ -#define LCD_F_PCTL1_S60 ((uint32_t)0x10000000) /*!< LCD pin 60 enable */ -/* LCD_F_PCTL1[S61] Bits */ -#define LCD_F_PCTL1_S61_OFS (29) /*!< LCDS61 Bit Offset */ -#define LCD_F_PCTL1_S61 ((uint32_t)0x20000000) /*!< LCD pin 61 enable */ -/* LCD_F_PCTL1[S62] Bits */ -#define LCD_F_PCTL1_S62_OFS (30) /*!< LCDS62 Bit Offset */ -#define LCD_F_PCTL1_S62 ((uint32_t)0x40000000) /*!< LCD pin 62 enable */ -/* LCD_F_PCTL1[S63] Bits */ -#define LCD_F_PCTL1_S63_OFS (31) /*!< LCDS63 Bit Offset */ -#define LCD_F_PCTL1_S63 ((uint32_t)0x80000000) /*!< LCD pin 63 enable */ -/* LCD_F_CSSEL0[CSS0] Bits */ -#define LCD_F_CSSEL0_CSS0_OFS ( 0) /*!< LCDCSS0 Bit Offset */ -#define LCD_F_CSSEL0_CSS0 ((uint32_t)0x00000001) /*!< L0 Com Seg select */ -/* LCD_F_CSSEL0[CSS1] Bits */ -#define LCD_F_CSSEL0_CSS1_OFS ( 1) /*!< LCDCSS1 Bit Offset */ -#define LCD_F_CSSEL0_CSS1 ((uint32_t)0x00000002) /*!< L1 Com Seg select */ -/* LCD_F_CSSEL0[CSS2] Bits */ -#define LCD_F_CSSEL0_CSS2_OFS ( 2) /*!< LCDCSS2 Bit Offset */ -#define LCD_F_CSSEL0_CSS2 ((uint32_t)0x00000004) /*!< L2 Com Seg select */ -/* LCD_F_CSSEL0[CSS3] Bits */ -#define LCD_F_CSSEL0_CSS3_OFS ( 3) /*!< LCDCSS3 Bit Offset */ -#define LCD_F_CSSEL0_CSS3 ((uint32_t)0x00000008) /*!< L3 Com Seg select */ -/* LCD_F_CSSEL0[CSS4] Bits */ -#define LCD_F_CSSEL0_CSS4_OFS ( 4) /*!< LCDCSS4 Bit Offset */ -#define LCD_F_CSSEL0_CSS4 ((uint32_t)0x00000010) /*!< L4 Com Seg select */ -/* LCD_F_CSSEL0[CSS5] Bits */ -#define LCD_F_CSSEL0_CSS5_OFS ( 5) /*!< LCDCSS5 Bit Offset */ -#define LCD_F_CSSEL0_CSS5 ((uint32_t)0x00000020) /*!< L5 Com Seg select */ -/* LCD_F_CSSEL0[CSS6] Bits */ -#define LCD_F_CSSEL0_CSS6_OFS ( 6) /*!< LCDCSS6 Bit Offset */ -#define LCD_F_CSSEL0_CSS6 ((uint32_t)0x00000040) /*!< L6 Com Seg select */ -/* LCD_F_CSSEL0[CSS7] Bits */ -#define LCD_F_CSSEL0_CSS7_OFS ( 7) /*!< LCDCSS7 Bit Offset */ -#define LCD_F_CSSEL0_CSS7 ((uint32_t)0x00000080) /*!< L7 Com Seg select */ -/* LCD_F_CSSEL0[CSS8] Bits */ -#define LCD_F_CSSEL0_CSS8_OFS ( 8) /*!< LCDCSS8 Bit Offset */ -#define LCD_F_CSSEL0_CSS8 ((uint32_t)0x00000100) /*!< L8 Com Seg select */ -/* LCD_F_CSSEL0[CSS9] Bits */ -#define LCD_F_CSSEL0_CSS9_OFS ( 9) /*!< LCDCSS9 Bit Offset */ -#define LCD_F_CSSEL0_CSS9 ((uint32_t)0x00000200) /*!< L9 Com Seg select */ -/* LCD_F_CSSEL0[CSS10] Bits */ -#define LCD_F_CSSEL0_CSS10_OFS (10) /*!< LCDCSS10 Bit Offset */ -#define LCD_F_CSSEL0_CSS10 ((uint32_t)0x00000400) /*!< L10 Com Seg select */ -/* LCD_F_CSSEL0[CSS11] Bits */ -#define LCD_F_CSSEL0_CSS11_OFS (11) /*!< LCDCSS11 Bit Offset */ -#define LCD_F_CSSEL0_CSS11 ((uint32_t)0x00000800) /*!< L11 Com Seg select */ -/* LCD_F_CSSEL0[CSS12] Bits */ -#define LCD_F_CSSEL0_CSS12_OFS (12) /*!< LCDCSS12 Bit Offset */ -#define LCD_F_CSSEL0_CSS12 ((uint32_t)0x00001000) /*!< L12 Com Seg select */ -/* LCD_F_CSSEL0[CSS13] Bits */ -#define LCD_F_CSSEL0_CSS13_OFS (13) /*!< LCDCSS13 Bit Offset */ -#define LCD_F_CSSEL0_CSS13 ((uint32_t)0x00002000) /*!< L13 Com Seg select */ -/* LCD_F_CSSEL0[CSS14] Bits */ -#define LCD_F_CSSEL0_CSS14_OFS (14) /*!< LCDCSS14 Bit Offset */ -#define LCD_F_CSSEL0_CSS14 ((uint32_t)0x00004000) /*!< L14 Com Seg select */ -/* LCD_F_CSSEL0[CSS15] Bits */ -#define LCD_F_CSSEL0_CSS15_OFS (15) /*!< LCDCSS15 Bit Offset */ -#define LCD_F_CSSEL0_CSS15 ((uint32_t)0x00008000) /*!< L15 Com Seg select */ -/* LCD_F_CSSEL0[CSS16] Bits */ -#define LCD_F_CSSEL0_CSS16_OFS (16) /*!< LCDCSS16 Bit Offset */ -#define LCD_F_CSSEL0_CSS16 ((uint32_t)0x00010000) /*!< L16 Com Seg select */ -/* LCD_F_CSSEL0[CSS17] Bits */ -#define LCD_F_CSSEL0_CSS17_OFS (17) /*!< LCDCSS17 Bit Offset */ -#define LCD_F_CSSEL0_CSS17 ((uint32_t)0x00020000) /*!< L17 Com Seg select */ -/* LCD_F_CSSEL0[CSS18] Bits */ -#define LCD_F_CSSEL0_CSS18_OFS (18) /*!< LCDCSS18 Bit Offset */ -#define LCD_F_CSSEL0_CSS18 ((uint32_t)0x00040000) /*!< L18 Com Seg select */ -/* LCD_F_CSSEL0[CSS19] Bits */ -#define LCD_F_CSSEL0_CSS19_OFS (19) /*!< LCDCSS19 Bit Offset */ -#define LCD_F_CSSEL0_CSS19 ((uint32_t)0x00080000) /*!< L19 Com Seg select */ -/* LCD_F_CSSEL0[CSS20] Bits */ -#define LCD_F_CSSEL0_CSS20_OFS (20) /*!< LCDCSS20 Bit Offset */ -#define LCD_F_CSSEL0_CSS20 ((uint32_t)0x00100000) /*!< L20 Com Seg select */ -/* LCD_F_CSSEL0[CSS21] Bits */ -#define LCD_F_CSSEL0_CSS21_OFS (21) /*!< LCDCSS21 Bit Offset */ -#define LCD_F_CSSEL0_CSS21 ((uint32_t)0x00200000) /*!< L21 Com Seg select */ -/* LCD_F_CSSEL0[CSS22] Bits */ -#define LCD_F_CSSEL0_CSS22_OFS (22) /*!< LCDCSS22 Bit Offset */ -#define LCD_F_CSSEL0_CSS22 ((uint32_t)0x00400000) /*!< L22 Com Seg select */ -/* LCD_F_CSSEL0[CSS23] Bits */ -#define LCD_F_CSSEL0_CSS23_OFS (23) /*!< LCDCSS23 Bit Offset */ -#define LCD_F_CSSEL0_CSS23 ((uint32_t)0x00800000) /*!< L23 Com Seg select */ -/* LCD_F_CSSEL0[CSS24] Bits */ -#define LCD_F_CSSEL0_CSS24_OFS (24) /*!< LCDCSS24 Bit Offset */ -#define LCD_F_CSSEL0_CSS24 ((uint32_t)0x01000000) /*!< L24 Com Seg select */ -/* LCD_F_CSSEL0[CSS25] Bits */ -#define LCD_F_CSSEL0_CSS25_OFS (25) /*!< LCDCSS25 Bit Offset */ -#define LCD_F_CSSEL0_CSS25 ((uint32_t)0x02000000) /*!< L25 Com Seg select */ -/* LCD_F_CSSEL0[CSS26] Bits */ -#define LCD_F_CSSEL0_CSS26_OFS (26) /*!< LCDCSS26 Bit Offset */ -#define LCD_F_CSSEL0_CSS26 ((uint32_t)0x04000000) /*!< L26 Com Seg select */ -/* LCD_F_CSSEL0[CSS27] Bits */ -#define LCD_F_CSSEL0_CSS27_OFS (27) /*!< LCDCSS27 Bit Offset */ -#define LCD_F_CSSEL0_CSS27 ((uint32_t)0x08000000) /*!< L27 Com Seg select */ -/* LCD_F_CSSEL0[CSS28] Bits */ -#define LCD_F_CSSEL0_CSS28_OFS (28) /*!< LCDCSS28 Bit Offset */ -#define LCD_F_CSSEL0_CSS28 ((uint32_t)0x10000000) /*!< L28 Com Seg select */ -/* LCD_F_CSSEL0[CSS29] Bits */ -#define LCD_F_CSSEL0_CSS29_OFS (29) /*!< LCDCSS29 Bit Offset */ -#define LCD_F_CSSEL0_CSS29 ((uint32_t)0x20000000) /*!< L29 Com Seg select */ -/* LCD_F_CSSEL0[CSS30] Bits */ -#define LCD_F_CSSEL0_CSS30_OFS (30) /*!< LCDCSS30 Bit Offset */ -#define LCD_F_CSSEL0_CSS30 ((uint32_t)0x40000000) /*!< L30 Com Seg select */ -/* LCD_F_CSSEL0[CSS31] Bits */ -#define LCD_F_CSSEL0_CSS31_OFS (31) /*!< LCDCSS31 Bit Offset */ -#define LCD_F_CSSEL0_CSS31 ((uint32_t)0x80000000) /*!< L31 Com Seg select */ -/* LCD_F_CSSEL1[CSS32] Bits */ -#define LCD_F_CSSEL1_CSS32_OFS ( 0) /*!< LCDCSS32 Bit Offset */ -#define LCD_F_CSSEL1_CSS32 ((uint32_t)0x00000001) /*!< L32 Com Seg select */ -/* LCD_F_CSSEL1[CSS33] Bits */ -#define LCD_F_CSSEL1_CSS33_OFS ( 1) /*!< LCDCSS33 Bit Offset */ -#define LCD_F_CSSEL1_CSS33 ((uint32_t)0x00000002) /*!< L33 Com Seg select */ -/* LCD_F_CSSEL1[CSS34] Bits */ -#define LCD_F_CSSEL1_CSS34_OFS ( 2) /*!< LCDCSS34 Bit Offset */ -#define LCD_F_CSSEL1_CSS34 ((uint32_t)0x00000004) /*!< L34 Com Seg select */ -/* LCD_F_CSSEL1[CSS35] Bits */ -#define LCD_F_CSSEL1_CSS35_OFS ( 3) /*!< LCDCSS35 Bit Offset */ -#define LCD_F_CSSEL1_CSS35 ((uint32_t)0x00000008) /*!< L35 Com Seg select */ -/* LCD_F_CSSEL1[CSS36] Bits */ -#define LCD_F_CSSEL1_CSS36_OFS ( 4) /*!< LCDCSS36 Bit Offset */ -#define LCD_F_CSSEL1_CSS36 ((uint32_t)0x00000010) /*!< L36 Com Seg select */ -/* LCD_F_CSSEL1[CSS37] Bits */ -#define LCD_F_CSSEL1_CSS37_OFS ( 5) /*!< LCDCSS37 Bit Offset */ -#define LCD_F_CSSEL1_CSS37 ((uint32_t)0x00000020) /*!< L37 Com Seg select */ -/* LCD_F_CSSEL1[CSS38] Bits */ -#define LCD_F_CSSEL1_CSS38_OFS ( 6) /*!< LCDCSS38 Bit Offset */ -#define LCD_F_CSSEL1_CSS38 ((uint32_t)0x00000040) /*!< L38 Com Seg select */ -/* LCD_F_CSSEL1[CSS39] Bits */ -#define LCD_F_CSSEL1_CSS39_OFS ( 7) /*!< LCDCSS39 Bit Offset */ -#define LCD_F_CSSEL1_CSS39 ((uint32_t)0x00000080) /*!< L39 Com Seg select */ -/* LCD_F_CSSEL1[CSS40] Bits */ -#define LCD_F_CSSEL1_CSS40_OFS ( 8) /*!< LCDCSS40 Bit Offset */ -#define LCD_F_CSSEL1_CSS40 ((uint32_t)0x00000100) /*!< L40 Com Seg select */ -/* LCD_F_CSSEL1[CSS41] Bits */ -#define LCD_F_CSSEL1_CSS41_OFS ( 9) /*!< LCDCSS41 Bit Offset */ -#define LCD_F_CSSEL1_CSS41 ((uint32_t)0x00000200) /*!< L41 Com Seg select */ -/* LCD_F_CSSEL1[CSS42] Bits */ -#define LCD_F_CSSEL1_CSS42_OFS (10) /*!< LCDCSS42 Bit Offset */ -#define LCD_F_CSSEL1_CSS42 ((uint32_t)0x00000400) /*!< L42 Com Seg select */ -/* LCD_F_CSSEL1[CSS43] Bits */ -#define LCD_F_CSSEL1_CSS43_OFS (11) /*!< LCDCSS43 Bit Offset */ -#define LCD_F_CSSEL1_CSS43 ((uint32_t)0x00000800) /*!< L43 Com Seg select */ -/* LCD_F_CSSEL1[CSS44] Bits */ -#define LCD_F_CSSEL1_CSS44_OFS (12) /*!< LCDCSS44 Bit Offset */ -#define LCD_F_CSSEL1_CSS44 ((uint32_t)0x00001000) /*!< L44 Com Seg select */ -/* LCD_F_CSSEL1[CSS45] Bits */ -#define LCD_F_CSSEL1_CSS45_OFS (13) /*!< LCDCSS45 Bit Offset */ -#define LCD_F_CSSEL1_CSS45 ((uint32_t)0x00002000) /*!< L45 Com Seg select */ -/* LCD_F_CSSEL1[CSS46] Bits */ -#define LCD_F_CSSEL1_CSS46_OFS (14) /*!< LCDCSS46 Bit Offset */ -#define LCD_F_CSSEL1_CSS46 ((uint32_t)0x00004000) /*!< L46 Com Seg select */ -/* LCD_F_CSSEL1[CSS47] Bits */ -#define LCD_F_CSSEL1_CSS47_OFS (15) /*!< LCDCSS47 Bit Offset */ -#define LCD_F_CSSEL1_CSS47 ((uint32_t)0x00008000) /*!< L47 Com Seg select */ -/* LCD_F_CSSEL1[CSS48] Bits */ -#define LCD_F_CSSEL1_CSS48_OFS (16) /*!< LCDCSS48 Bit Offset */ -#define LCD_F_CSSEL1_CSS48 ((uint32_t)0x00010000) /*!< L48 Com Seg select */ -/* LCD_F_CSSEL1[CSS49] Bits */ -#define LCD_F_CSSEL1_CSS49_OFS (17) /*!< LCDCSS49 Bit Offset */ -#define LCD_F_CSSEL1_CSS49 ((uint32_t)0x00020000) /*!< L49 Com Seg select */ -/* LCD_F_CSSEL1[CSS50] Bits */ -#define LCD_F_CSSEL1_CSS50_OFS (18) /*!< LCDCSS50 Bit Offset */ -#define LCD_F_CSSEL1_CSS50 ((uint32_t)0x00040000) /*!< L50 Com Seg select */ -/* LCD_F_CSSEL1[CSS51] Bits */ -#define LCD_F_CSSEL1_CSS51_OFS (19) /*!< LCDCSS51 Bit Offset */ -#define LCD_F_CSSEL1_CSS51 ((uint32_t)0x00080000) /*!< L51 Com Seg select */ -/* LCD_F_CSSEL1[CSS52] Bits */ -#define LCD_F_CSSEL1_CSS52_OFS (20) /*!< LCDCSS52 Bit Offset */ -#define LCD_F_CSSEL1_CSS52 ((uint32_t)0x00100000) /*!< L52 Com Seg select */ -/* LCD_F_CSSEL1[CSS53] Bits */ -#define LCD_F_CSSEL1_CSS53_OFS (21) /*!< LCDCSS53 Bit Offset */ -#define LCD_F_CSSEL1_CSS53 ((uint32_t)0x00200000) /*!< L53 Com Seg select */ -/* LCD_F_CSSEL1[CSS54] Bits */ -#define LCD_F_CSSEL1_CSS54_OFS (22) /*!< LCDCSS54 Bit Offset */ -#define LCD_F_CSSEL1_CSS54 ((uint32_t)0x00400000) /*!< L54 Com Seg select */ -/* LCD_F_CSSEL1[CSS55] Bits */ -#define LCD_F_CSSEL1_CSS55_OFS (23) /*!< LCDCSS55 Bit Offset */ -#define LCD_F_CSSEL1_CSS55 ((uint32_t)0x00800000) /*!< L55 Com Seg select */ -/* LCD_F_CSSEL1[CSS56] Bits */ -#define LCD_F_CSSEL1_CSS56_OFS (24) /*!< LCDCSS56 Bit Offset */ -#define LCD_F_CSSEL1_CSS56 ((uint32_t)0x01000000) /*!< L56 Com Seg select */ -/* LCD_F_CSSEL1[CSS57] Bits */ -#define LCD_F_CSSEL1_CSS57_OFS (25) /*!< LCDCSS57 Bit Offset */ -#define LCD_F_CSSEL1_CSS57 ((uint32_t)0x02000000) /*!< L57 Com Seg select */ -/* LCD_F_CSSEL1[CSS58] Bits */ -#define LCD_F_CSSEL1_CSS58_OFS (26) /*!< LCDCSS58 Bit Offset */ -#define LCD_F_CSSEL1_CSS58 ((uint32_t)0x04000000) /*!< L58 Com Seg select */ -/* LCD_F_CSSEL1[CSS59] Bits */ -#define LCD_F_CSSEL1_CSS59_OFS (27) /*!< LCDCSS59 Bit Offset */ -#define LCD_F_CSSEL1_CSS59 ((uint32_t)0x08000000) /*!< L59 Com Seg select */ -/* LCD_F_CSSEL1[CSS60] Bits */ -#define LCD_F_CSSEL1_CSS60_OFS (28) /*!< LCDCSS60 Bit Offset */ -#define LCD_F_CSSEL1_CSS60 ((uint32_t)0x10000000) /*!< L60 Com Seg select */ -/* LCD_F_CSSEL1[CSS61] Bits */ -#define LCD_F_CSSEL1_CSS61_OFS (29) /*!< LCDCSS61 Bit Offset */ -#define LCD_F_CSSEL1_CSS61 ((uint32_t)0x20000000) /*!< L61 Com Seg select */ -/* LCD_F_CSSEL1[CSS62] Bits */ -#define LCD_F_CSSEL1_CSS62_OFS (30) /*!< LCDCSS62 Bit Offset */ -#define LCD_F_CSSEL1_CSS62 ((uint32_t)0x40000000) /*!< L62 Com Seg select */ -/* LCD_F_CSSEL1[CSS63] Bits */ -#define LCD_F_CSSEL1_CSS63_OFS (31) /*!< LCDCSS63 Bit Offset */ -#define LCD_F_CSSEL1_CSS63 ((uint32_t)0x80000000) /*!< L63 Com Seg select */ -/* LCD_F_ANMCTL[ANMEN] Bits */ -#define LCD_F_ANMCTL_ANMEN_OFS ( 0) /*!< LCDANMEN Bit Offset */ -#define LCD_F_ANMCTL_ANMEN ((uint32_t)0x00000001) /*!< Enable Animation */ -/* LCD_F_ANMCTL[ANMSTP] Bits */ -#define LCD_F_ANMCTL_ANMSTP_OFS ( 1) /*!< LCDANMSTP Bit Offset */ -#define LCD_F_ANMCTL_ANMSTP_MASK ((uint32_t)0x0000000E) /*!< LCDANMSTP Bit Mask */ -#define LCD_F_ANMCTL_ANMSTP0 ((uint32_t)0x00000002) /*!< ANMSTP Bit 0 */ -#define LCD_F_ANMCTL_ANMSTP1 ((uint32_t)0x00000004) /*!< ANMSTP Bit 1 */ -#define LCD_F_ANMCTL_ANMSTP2 ((uint32_t)0x00000008) /*!< ANMSTP Bit 2 */ -#define LCD_F_ANMCTL_ANMSTP_0 ((uint32_t)0x00000000) /*!< T0 */ -#define LCD_F_ANMCTL_ANMSTP_1 ((uint32_t)0x00000002) /*!< T0 to T1 */ -#define LCD_F_ANMCTL_ANMSTP_2 ((uint32_t)0x00000004) /*!< T0 to T2 */ -#define LCD_F_ANMCTL_ANMSTP_3 ((uint32_t)0x00000006) /*!< T0 to T3 */ -#define LCD_F_ANMCTL_ANMSTP_4 ((uint32_t)0x00000008) /*!< T0 to T4 */ -#define LCD_F_ANMCTL_ANMSTP_5 ((uint32_t)0x0000000A) /*!< T0 to T5 */ -#define LCD_F_ANMCTL_ANMSTP_6 ((uint32_t)0x0000000C) /*!< T0 to T6 */ -#define LCD_F_ANMCTL_ANMSTP_7 ((uint32_t)0x0000000E) /*!< T0 to T7 */ -/* LCD_F_ANMCTL[ANMCLR] Bits */ -#define LCD_F_ANMCTL_ANMCLR_OFS ( 7) /*!< LCDANMCLR Bit Offset */ -#define LCD_F_ANMCTL_ANMCLR ((uint32_t)0x00000080) /*!< Clear Animation Memory */ -/* LCD_F_ANMCTL[ANMPRE] Bits */ -#define LCD_F_ANMCTL_ANMPRE_OFS (16) /*!< LCDANMPREx Bit Offset */ -#define LCD_F_ANMCTL_ANMPRE_MASK ((uint32_t)0x00070000) /*!< LCDANMPREx Bit Mask */ -#define LCD_F_ANMCTL_ANMPRE0 ((uint32_t)0x00010000) /*!< ANMPRE Bit 0 */ -#define LCD_F_ANMCTL_ANMPRE1 ((uint32_t)0x00020000) /*!< ANMPRE Bit 1 */ -#define LCD_F_ANMCTL_ANMPRE2 ((uint32_t)0x00040000) /*!< ANMPRE Bit 2 */ -#define LCD_F_ANMCTL_ANMPRE_0 ((uint32_t)0x00000000) /*!< Divide by 512 */ -#define LCD_F_ANMCTL_ANMPRE_1 ((uint32_t)0x00010000) /*!< Divide by 1024 */ -#define LCD_F_ANMCTL_ANMPRE_2 ((uint32_t)0x00020000) /*!< Divide by 2048 */ -#define LCD_F_ANMCTL_ANMPRE_3 ((uint32_t)0x00030000) /*!< Divide by 4096 */ -#define LCD_F_ANMCTL_ANMPRE_4 ((uint32_t)0x00040000) /*!< Divide by 8162 */ -#define LCD_F_ANMCTL_ANMPRE_5 ((uint32_t)0x00050000) /*!< Divide by 16384 */ -#define LCD_F_ANMCTL_ANMPRE_6 ((uint32_t)0x00060000) /*!< Divide by 32768 */ -#define LCD_F_ANMCTL_ANMPRE_7 ((uint32_t)0x00070000) /*!< Divide by 65536 */ -/* LCD_F_ANMCTL[ANMDIV] Bits */ -#define LCD_F_ANMCTL_ANMDIV_OFS (19) /*!< LCDANMDIVx Bit Offset */ -#define LCD_F_ANMCTL_ANMDIV_MASK ((uint32_t)0x00380000) /*!< LCDANMDIVx Bit Mask */ -#define LCD_F_ANMCTL_ANMDIV0 ((uint32_t)0x00080000) /*!< ANMDIV Bit 0 */ -#define LCD_F_ANMCTL_ANMDIV1 ((uint32_t)0x00100000) /*!< ANMDIV Bit 1 */ -#define LCD_F_ANMCTL_ANMDIV2 ((uint32_t)0x00200000) /*!< ANMDIV Bit 2 */ -#define LCD_F_ANMCTL_ANMDIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_ANMCTL_ANMDIV_1 ((uint32_t)0x00080000) /*!< Divide by 2 */ -#define LCD_F_ANMCTL_ANMDIV_2 ((uint32_t)0x00100000) /*!< Divide by 3 */ -#define LCD_F_ANMCTL_ANMDIV_3 ((uint32_t)0x00180000) /*!< Divide by 4 */ -#define LCD_F_ANMCTL_ANMDIV_4 ((uint32_t)0x00200000) /*!< Divide by 5 */ -#define LCD_F_ANMCTL_ANMDIV_5 ((uint32_t)0x00280000) /*!< Divide by 6 */ -#define LCD_F_ANMCTL_ANMDIV_6 ((uint32_t)0x00300000) /*!< Divide by 7 */ -#define LCD_F_ANMCTL_ANMDIV_7 ((uint32_t)0x00380000) /*!< Divide by 8 */ -/* LCD_F_IE[BLKOFFIE] Bits */ -#define LCD_F_IE_BLKOFFIE_OFS ( 1) /*!< LCDBLKOFFIE Bit Offset */ -#define LCD_F_IE_BLKOFFIE ((uint32_t)0x00000002) /*!< LCD Blink, segments off interrupt enable */ -/* LCD_F_IE[BLKONIE] Bits */ -#define LCD_F_IE_BLKONIE_OFS ( 2) /*!< LCDBLKONIE Bit Offset */ -#define LCD_F_IE_BLKONIE ((uint32_t)0x00000004) /*!< LCD Blink, segments on interrupt enable */ -/* LCD_F_IE[FRMIE] Bits */ -#define LCD_F_IE_FRMIE_OFS ( 3) /*!< LCDFRMIE Bit Offset */ -#define LCD_F_IE_FRMIE ((uint32_t)0x00000008) /*!< LCD Frame interrupt enable */ -/* LCD_F_IE[ANMSTPIE] Bits */ -#define LCD_F_IE_ANMSTPIE_OFS ( 8) /*!< LCDANMSTPIE Bit Offset */ -#define LCD_F_IE_ANMSTPIE ((uint32_t)0x00000100) /*!< LCD Animation step interrupt enable */ -/* LCD_F_IE[ANMLOOPIE] Bits */ -#define LCD_F_IE_ANMLOOPIE_OFS ( 9) /*!< LCDANMLOOPIE Bit Offset */ -#define LCD_F_IE_ANMLOOPIE ((uint32_t)0x00000200) /*!< LCD Animation loop interrupt enable */ -/* LCD_F_IFG[BLKOFFIFG] Bits */ -#define LCD_F_IFG_BLKOFFIFG_OFS ( 1) /*!< LCDBLKOFFIFG Bit Offset */ -#define LCD_F_IFG_BLKOFFIFG ((uint32_t)0x00000002) /*!< LCD Blink, segments off interrupt flag */ -/* LCD_F_IFG[BLKONIFG] Bits */ -#define LCD_F_IFG_BLKONIFG_OFS ( 2) /*!< LCDBLKONIFG Bit Offset */ -#define LCD_F_IFG_BLKONIFG ((uint32_t)0x00000004) /*!< LCD Blink, segments on interrupt flag */ -/* LCD_F_IFG[FRMIFG] Bits */ -#define LCD_F_IFG_FRMIFG_OFS ( 3) /*!< LCDFRMIFG Bit Offset */ -#define LCD_F_IFG_FRMIFG ((uint32_t)0x00000008) /*!< LCD Frame interrupt flag */ -/* LCD_F_IFG[ANMSTPIFG] Bits */ -#define LCD_F_IFG_ANMSTPIFG_OFS ( 8) /*!< LCDANMSTPIFG Bit Offset */ -#define LCD_F_IFG_ANMSTPIFG ((uint32_t)0x00000100) /*!< LCD Animation step interrupt flag */ -/* LCD_F_IFG[ANMLOOPIFG] Bits */ -#define LCD_F_IFG_ANMLOOPIFG_OFS ( 9) /*!< LCDANMLOOPIFG Bit Offset */ -#define LCD_F_IFG_ANMLOOPIFG ((uint32_t)0x00000200) /*!< LCD Animation loop interrupt flag */ -/* LCD_F_SETIFG[SETLCDBLKOFFIFG] Bits */ -#define LCD_F_SETIFG_SETLCDBLKOFFIFG_OFS ( 1) /*!< SETLCDBLKOFFIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDBLKOFFIFG ((uint32_t)0x00000002) /*!< Sets LCDBLKOFFIFG */ -/* LCD_F_SETIFG[SETLCDBLKONIFG] Bits */ -#define LCD_F_SETIFG_SETLCDBLKONIFG_OFS ( 2) /*!< SETLCDBLKONIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDBLKONIFG ((uint32_t)0x00000004) /*!< Sets LCDBLKONIFG */ -/* LCD_F_SETIFG[SETLCDFRMIFG] Bits */ -#define LCD_F_SETIFG_SETLCDFRMIFG_OFS ( 3) /*!< SETLCDFRMIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDFRMIFG ((uint32_t)0x00000008) /*!< Sets LCDFRMIFG */ -/* LCD_F_SETIFG[SETLCDANMSTPIFG] Bits */ -#define LCD_F_SETIFG_SETLCDANMSTPIFG_OFS ( 8) /*!< SETLCDANMSTPIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDANMSTPIFG ((uint32_t)0x00000100) /*!< Sets LCDANMSTPIFG */ -/* LCD_F_SETIFG[SETLCDANMLOOPIFG] Bits */ -#define LCD_F_SETIFG_SETLCDANMLOOPIFG_OFS ( 9) /*!< SETLCDANMLOOPIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDANMLOOPIFG ((uint32_t)0x00000200) /*!< Sets LCDANMLOOPIFG */ -/* LCD_F_CLRIFG[CLRLCDBLKOFFIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDBLKOFFIFG_OFS ( 1) /*!< CLRLCDBLKOFFIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDBLKOFFIFG ((uint32_t)0x00000002) /*!< Clears LCDBLKOFFIFG */ -/* LCD_F_CLRIFG[CLRLCDBLKONIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDBLKONIFG_OFS ( 2) /*!< CLRLCDBLKONIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDBLKONIFG ((uint32_t)0x00000004) /*!< Clears LCDBLKONIFG */ -/* LCD_F_CLRIFG[CLRLCDFRMIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDFRMIFG_OFS ( 3) /*!< CLRLCDFRMIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDFRMIFG ((uint32_t)0x00000008) /*!< Clears LCDFRMIFG */ -/* LCD_F_CLRIFG[CLRLCDANMSTPIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDANMSTPIFG_OFS ( 8) /*!< CLRLCDANMSTPIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDANMSTPIFG ((uint32_t)0x00000100) /*!< Clears LCDANMSTPIFG */ -/* LCD_F_CLRIFG[CLRLCDANMLOOPIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDANMLOOPIFG_OFS ( 9) /*!< CLRLCDANMLOOPIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDANMLOOPIFG ((uint32_t)0x00000200) /*!< Clears LCDANMLOOPIFG */ - -/****************************************************************************** -* MPU Bits -******************************************************************************/ - -/* Pre-defined bitfield values */ - -/* MPU_RASR_SIZE Bitfield Bits */ -#define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /*!< 32B */ -#define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /*!< 64B */ -#define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /*!< 128B */ -#define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /*!< 256B */ -#define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /*!< 512B */ -#define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /*!< 1KB */ -#define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /*!< 2KB */ -#define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /*!< 4KB */ -#define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /*!< 8KB */ -#define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /*!< 16KB */ -#define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /*!< 32KB */ -#define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /*!< 64KB */ -#define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /*!< 128KB */ -#define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /*!< 256KB */ -#define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /*!< 512KB */ -#define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /*!< 1MB */ -#define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /*!< 2MB */ -#define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /*!< 4MB */ -#define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /*!< 8MB */ -#define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /*!< 16MB */ -#define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /*!< 32MB */ -#define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /*!< 64MB */ -#define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /*!< 128MB */ -#define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /*!< 256MB */ -#define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /*!< 512MB */ -#define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /*!< 1GB */ -#define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /*!< 2GB */ -#define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /*!< 4GB */ - -/* MPU_RASR_AP Bitfield Bits */ -#define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /*!< Privileged permissions: No access. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /*!< Privileged permissions: Read-write. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /*!< Privileged permissions: Read-write. User permissions: Read-only. */ -#define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /*!< Privileged permissions: Read-write. User permissions: Read-write. */ -#define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /*!< Privileged permissions: Read-only. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /*!< Privileged permissions: Read-only. User permissions: Read-only. */ - -/* MPU_RASR_XN Bitfield Bits */ -#define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /*!< Instruction access enabled */ -#define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /*!< Instruction access disabled */ - - -/****************************************************************************** -* NVIC Bits -******************************************************************************/ - -/* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */ -#define NVIC_IPR0_PRI_0_OFS ( 0) /*!< PRI_0 Offset */ -#define NVIC_IPR0_PRI_0_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */ -#define NVIC_IPR0_PRI_1_OFS ( 8) /*!< PRI_1 Offset */ -#define NVIC_IPR0_PRI_1_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */ -#define NVIC_IPR0_PRI_2_OFS (16) /*!< PRI_2 Offset */ -#define NVIC_IPR0_PRI_2_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */ -#define NVIC_IPR0_PRI_3_OFS (24) /*!< PRI_3 Offset */ -#define NVIC_IPR0_PRI_3_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */ -#define NVIC_IPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define NVIC_IPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */ -#define NVIC_IPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define NVIC_IPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */ -#define NVIC_IPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define NVIC_IPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */ -#define NVIC_IPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define NVIC_IPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */ -#define NVIC_IPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define NVIC_IPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */ -#define NVIC_IPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define NVIC_IPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */ -#define NVIC_IPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define NVIC_IPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */ -#define NVIC_IPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define NVIC_IPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */ -#define NVIC_IPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define NVIC_IPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */ -#define NVIC_IPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define NVIC_IPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */ -#define NVIC_IPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define NVIC_IPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */ -#define NVIC_IPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define NVIC_IPR3_PRI_15_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */ -#define NVIC_IPR4_PRI_16_OFS ( 0) /*!< PRI_16 Offset */ -#define NVIC_IPR4_PRI_16_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */ -#define NVIC_IPR4_PRI_17_OFS ( 8) /*!< PRI_17 Offset */ -#define NVIC_IPR4_PRI_17_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */ -#define NVIC_IPR4_PRI_18_OFS (16) /*!< PRI_18 Offset */ -#define NVIC_IPR4_PRI_18_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */ -#define NVIC_IPR4_PRI_19_OFS (24) /*!< PRI_19 Offset */ -#define NVIC_IPR4_PRI_19_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */ -#define NVIC_IPR5_PRI_20_OFS ( 0) /*!< PRI_20 Offset */ -#define NVIC_IPR5_PRI_20_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */ -#define NVIC_IPR5_PRI_21_OFS ( 8) /*!< PRI_21 Offset */ -#define NVIC_IPR5_PRI_21_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */ -#define NVIC_IPR5_PRI_22_OFS (16) /*!< PRI_22 Offset */ -#define NVIC_IPR5_PRI_22_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */ -#define NVIC_IPR5_PRI_23_OFS (24) /*!< PRI_23 Offset */ -#define NVIC_IPR5_PRI_23_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */ -#define NVIC_IPR6_PRI_24_OFS ( 0) /*!< PRI_24 Offset */ -#define NVIC_IPR6_PRI_24_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */ -#define NVIC_IPR6_PRI_25_OFS ( 8) /*!< PRI_25 Offset */ -#define NVIC_IPR6_PRI_25_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */ -#define NVIC_IPR6_PRI_26_OFS (16) /*!< PRI_26 Offset */ -#define NVIC_IPR6_PRI_26_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */ -#define NVIC_IPR6_PRI_27_OFS (24) /*!< PRI_27 Offset */ -#define NVIC_IPR6_PRI_27_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */ -#define NVIC_IPR7_PRI_28_OFS ( 0) /*!< PRI_28 Offset */ -#define NVIC_IPR7_PRI_28_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */ -#define NVIC_IPR7_PRI_29_OFS ( 8) /*!< PRI_29 Offset */ -#define NVIC_IPR7_PRI_29_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */ -#define NVIC_IPR7_PRI_30_OFS (16) /*!< PRI_30 Offset */ -#define NVIC_IPR7_PRI_30_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */ -#define NVIC_IPR7_PRI_31_OFS (24) /*!< PRI_31 Offset */ -#define NVIC_IPR7_PRI_31_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */ -#define NVIC_IPR8_PRI_32_OFS ( 0) /*!< PRI_32 Offset */ -#define NVIC_IPR8_PRI_32_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */ -#define NVIC_IPR8_PRI_33_OFS ( 8) /*!< PRI_33 Offset */ -#define NVIC_IPR8_PRI_33_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */ -#define NVIC_IPR8_PRI_34_OFS (16) /*!< PRI_34 Offset */ -#define NVIC_IPR8_PRI_34_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */ -#define NVIC_IPR8_PRI_35_OFS (24) /*!< PRI_35 Offset */ -#define NVIC_IPR8_PRI_35_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */ -#define NVIC_IPR9_PRI_36_OFS ( 0) /*!< PRI_36 Offset */ -#define NVIC_IPR9_PRI_36_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */ -#define NVIC_IPR9_PRI_37_OFS ( 8) /*!< PRI_37 Offset */ -#define NVIC_IPR9_PRI_37_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */ -#define NVIC_IPR9_PRI_38_OFS (16) /*!< PRI_38 Offset */ -#define NVIC_IPR9_PRI_38_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */ -#define NVIC_IPR9_PRI_39_OFS (24) /*!< PRI_39 Offset */ -#define NVIC_IPR9_PRI_39_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */ -#define NVIC_IPR10_PRI_40_OFS ( 0) /*!< PRI_40 Offset */ -#define NVIC_IPR10_PRI_40_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */ -#define NVIC_IPR10_PRI_41_OFS ( 8) /*!< PRI_41 Offset */ -#define NVIC_IPR10_PRI_41_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */ -#define NVIC_IPR10_PRI_42_OFS (16) /*!< PRI_42 Offset */ -#define NVIC_IPR10_PRI_42_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */ -#define NVIC_IPR10_PRI_43_OFS (24) /*!< PRI_43 Offset */ -#define NVIC_IPR10_PRI_43_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */ -#define NVIC_IPR11_PRI_44_OFS ( 0) /*!< PRI_44 Offset */ -#define NVIC_IPR11_PRI_44_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */ -#define NVIC_IPR11_PRI_45_OFS ( 8) /*!< PRI_45 Offset */ -#define NVIC_IPR11_PRI_45_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */ -#define NVIC_IPR11_PRI_46_OFS (16) /*!< PRI_46 Offset */ -#define NVIC_IPR11_PRI_46_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */ -#define NVIC_IPR11_PRI_47_OFS (24) /*!< PRI_47 Offset */ -#define NVIC_IPR11_PRI_47_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */ -#define NVIC_IPR12_PRI_48_OFS ( 0) /*!< PRI_48 Offset */ -#define NVIC_IPR12_PRI_48_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */ -#define NVIC_IPR12_PRI_49_OFS ( 8) /*!< PRI_49 Offset */ -#define NVIC_IPR12_PRI_49_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */ -#define NVIC_IPR12_PRI_50_OFS (16) /*!< PRI_50 Offset */ -#define NVIC_IPR12_PRI_50_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */ -#define NVIC_IPR12_PRI_51_OFS (24) /*!< PRI_51 Offset */ -#define NVIC_IPR12_PRI_51_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */ -#define NVIC_IPR13_PRI_52_OFS ( 0) /*!< PRI_52 Offset */ -#define NVIC_IPR13_PRI_52_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */ -#define NVIC_IPR13_PRI_53_OFS ( 8) /*!< PRI_53 Offset */ -#define NVIC_IPR13_PRI_53_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */ -#define NVIC_IPR13_PRI_54_OFS (16) /*!< PRI_54 Offset */ -#define NVIC_IPR13_PRI_54_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */ -#define NVIC_IPR13_PRI_55_OFS (24) /*!< PRI_55 Offset */ -#define NVIC_IPR13_PRI_55_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */ -#define NVIC_IPR14_PRI_56_OFS ( 0) /*!< PRI_56 Offset */ -#define NVIC_IPR14_PRI_56_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */ -#define NVIC_IPR14_PRI_57_OFS ( 8) /*!< PRI_57 Offset */ -#define NVIC_IPR14_PRI_57_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */ -#define NVIC_IPR14_PRI_58_OFS (16) /*!< PRI_58 Offset */ -#define NVIC_IPR14_PRI_58_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */ -#define NVIC_IPR14_PRI_59_OFS (24) /*!< PRI_59 Offset */ -#define NVIC_IPR14_PRI_59_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */ -#define NVIC_IPR15_PRI_60_OFS ( 0) /*!< PRI_60 Offset */ -#define NVIC_IPR15_PRI_60_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */ -#define NVIC_IPR15_PRI_61_OFS ( 8) /*!< PRI_61 Offset */ -#define NVIC_IPR15_PRI_61_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */ -#define NVIC_IPR15_PRI_62_OFS (16) /*!< PRI_62 Offset */ -#define NVIC_IPR15_PRI_62_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */ -#define NVIC_IPR15_PRI_63_OFS (24) /*!< PRI_63 Offset */ -#define NVIC_IPR15_PRI_63_M ((uint32_t)0xff000000) /* */ - - -/****************************************************************************** -* PCM Bits -******************************************************************************/ -/* PCM_CTL0[AMR] Bits */ -#define PCM_CTL0_AMR_OFS ( 0) /*!< AMR Bit Offset */ -#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /*!< AMR Bit Mask */ -#define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /*!< AMR Bit 0 */ -#define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /*!< AMR Bit 1 */ -#define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /*!< AMR Bit 2 */ -#define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /*!< AMR Bit 3 */ -#define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -/* PCM_CTL0[LPMR] Bits */ -#define PCM_CTL0_LPMR_OFS ( 4) /*!< LPMR Bit Offset */ -#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /*!< LPMR Bit Mask */ -#define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /*!< LPMR Bit 0 */ -#define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /*!< LPMR Bit 1 */ -#define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /*!< LPMR Bit 2 */ -#define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /*!< LPMR Bit 3 */ -#define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ - /* entered. */ -#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -#define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ - /* entered. */ -#define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -/* PCM_CTL0[CPM] Bits */ -#define PCM_CTL0_CPM_OFS ( 8) /*!< CPM Bit Offset */ -#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /*!< CPM Bit Mask */ -#define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /*!< CPM Bit 0 */ -#define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /*!< CPM Bit 1 */ -#define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /*!< CPM Bit 2 */ -#define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /*!< CPM Bit 3 */ -#define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /*!< CPM Bit 4 */ -#define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /*!< CPM Bit 5 */ -#define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /*!< LPM3 */ -#define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /*!< LPM3 */ -/* PCM_CTL0[KEY] Bits */ -#define PCM_CTL0_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -/* PCM_CTL1[LOCKLPM5] Bits */ -#define PCM_CTL1_LOCKLPM5_OFS ( 0) /*!< LOCKLPM5 Bit Offset */ -#define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /*!< Lock LPM5 */ -/* PCM_CTL1[LOCKBKUP] Bits */ -#define PCM_CTL1_LOCKBKUP_OFS ( 1) /*!< LOCKBKUP Bit Offset */ -#define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /*!< Lock Backup */ -/* PCM_CTL1[FORCE_LPM_ENTRY] Bits */ -#define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /*!< FORCE_LPM_ENTRY Bit Offset */ -#define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /*!< Force LPM entry */ -/* PCM_CTL1[PMR_BUSY] Bits */ -#define PCM_CTL1_PMR_BUSY_OFS ( 8) /*!< PMR_BUSY Bit Offset */ -#define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /*!< Power mode request busy flag */ -/* PCM_CTL1[KEY] Bits */ -#define PCM_CTL1_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -/* PCM_IE[LPM_INVALID_TR_IE] Bits */ -#define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /*!< LPM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /*!< LPM invalid transition interrupt enable */ -/* PCM_IE[LPM_INVALID_CLK_IE] Bits */ -#define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /*!< LPM_INVALID_CLK_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /*!< LPM invalid clock interrupt enable */ -/* PCM_IE[AM_INVALID_TR_IE] Bits */ -#define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /*!< AM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /*!< Active mode invalid transition interrupt enable */ -/* PCM_IE[DCDC_ERROR_IE] Bits */ -#define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /*!< DCDC_ERROR_IE Bit Offset */ -#define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /*!< DC-DC error interrupt enable */ -/* PCM_IFG[LPM_INVALID_TR_IFG] Bits */ -#define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /*!< LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< LPM invalid transition flag */ -/* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */ -#define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< LPM invalid clock flag */ -/* PCM_IFG[AM_INVALID_TR_IFG] Bits */ -#define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /*!< AM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Active mode invalid transition flag */ -/* PCM_IFG[DCDC_ERROR_IFG] Bits */ -#define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /*!< DCDC_ERROR_IFG Bit Offset */ -#define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< DC-DC error flag */ -/* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< Clear LPM invalid transition flag */ -/* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< Clear LPM invalid clock flag */ -/* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /*!< CLR_AM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Clear active mode invalid transition flag */ -/* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /*!< CLR_DCDC_ERROR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< Clear DC-DC error flag */ -/* Pre-defined bitfield values */ -#define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ -#define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ - - -/****************************************************************************** -* PMAP Bits -******************************************************************************/ -/* PMAP_CTL[LOCKED] Bits */ -#define PMAP_CTL_LOCKED_OFS ( 0) /*!< PMAPLOCKED Bit Offset */ -#define PMAP_CTL_LOCKED ((uint16_t)0x0001) /*!< Port mapping lock bit */ -/* PMAP_CTL[PRECFG] Bits */ -#define PMAP_CTL_PRECFG_OFS ( 1) /*!< PMAPRECFG Bit Offset */ -#define PMAP_CTL_PRECFG ((uint16_t)0x0002) /*!< Port mapping reconfiguration control bit */ -/* Pre-defined bitfield values */ -#define PMAP_NONE 0 -#define PMAP_UCA0CLK 1 -#define PMAP_UCA0RXD 2 -#define PMAP_UCA0SOMI 2 -#define PMAP_UCA0TXD 3 -#define PMAP_UCA0SIMO 3 -#define PMAP_UCB0CLK 4 -#define PMAP_UCB0SDA 5 -#define PMAP_UCB0SIMO 5 -#define PMAP_UCB0SCL 6 -#define PMAP_UCB0SOMI 6 -#define PMAP_UCA1STE 7 -#define PMAP_UCA1CLK 8 -#define PMAP_UCA1RXD 9 -#define PMAP_UCA1SOMI 9 -#define PMAP_UCA1TXD 10 -#define PMAP_UCA1SIMO 10 -#define PMAP_UCA2STE 11 -#define PMAP_UCA2CLK 12 -#define PMAP_UCA2RXD 13 -#define PMAP_UCA2SOMI 13 -#define PMAP_UCA2TXD 14 -#define PMAP_UCA2SIMO 14 -#define PMAP_UCB2STE 15 -#define PMAP_UCB2CLK 16 -#define PMAP_UCB2SDA 17 -#define PMAP_UCB2SIMO 17 -#define PMAP_UCB2SCL 18 -#define PMAP_UCB2SOMI 18 -#define PMAP_TA0CCR0A 19 -#define PMAP_TA0CCR1A 20 -#define PMAP_TA0CCR2A 21 -#define PMAP_TA0CCR3A 22 -#define PMAP_TA0CCR4A 23 -#define PMAP_TA1CCR1A 24 -#define PMAP_TA1CCR2A 25 -#define PMAP_TA1CCR3A 26 -#define PMAP_TA1CCR4A 27 -#define PMAP_TA0CLK 28 -#define PMAP_CE0OUT 28 -#define PMAP_TA1CLK 29 -#define PMAP_CE1OUT 29 -#define PMAP_DMAE0 30 -#define PMAP_SMCLK 30 -#define PMAP_ANALOG 31 - -#define PMAP_KEYID_VAL ((uint16_t)0x2D52) /*!< Port Mapping Key */ - - -/****************************************************************************** -* PSS Bits -******************************************************************************/ -/* PSS_KEY[KEY] Bits */ -#define PSS_KEY_KEY_OFS ( 0) /*!< PSSKEY Bit Offset */ -#define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< PSSKEY Bit Mask */ -/* PSS_CTL0[SVSMHOFF] Bits */ -#define PSS_CTL0_SVSMHOFF_OFS ( 0) /*!< SVSMHOFF Bit Offset */ -#define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /*!< SVSM high-side off */ -/* PSS_CTL0[SVSMHLP] Bits */ -#define PSS_CTL0_SVSMHLP_OFS ( 1) /*!< SVSMHLP Bit Offset */ -#define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /*!< SVSM high-side low power normal performance mode */ -/* PSS_CTL0[SVSMHS] Bits */ -#define PSS_CTL0_SVSMHS_OFS ( 2) /*!< SVSMHS Bit Offset */ -#define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /*!< Supply supervisor or monitor selection for the high-side */ -/* PSS_CTL0[SVSMHTH] Bits */ -#define PSS_CTL0_SVSMHTH_OFS ( 3) /*!< SVSMHTH Bit Offset */ -#define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /*!< SVSMHTH Bit Mask */ -/* PSS_CTL0[SVMHOE] Bits */ -#define PSS_CTL0_SVMHOE_OFS ( 6) /*!< SVMHOE Bit Offset */ -#define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /*!< SVSM high-side output enable */ -/* PSS_CTL0[SVMHOUTPOLAL] Bits */ -#define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /*!< SVMHOUTPOLAL Bit Offset */ -#define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /*!< SVMHOUT pin polarity active low */ -/* PSS_CTL0[DCDC_FORCE] Bits */ -#define PSS_CTL0_DCDC_FORCE_OFS (10) /*!< DCDC_FORCE Bit Offset */ -#define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /*!< Force DC-DC regulator operation */ -/* PSS_CTL0[VCORETRAN] Bits */ -#define PSS_CTL0_VCORETRAN_OFS (12) /*!< VCORETRAN Bit Offset */ -#define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /*!< VCORETRAN Bit Mask */ -#define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /*!< VCORETRAN Bit 0 */ -#define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /*!< VCORETRAN Bit 1 */ -#define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -/* PSS_IE[SVSMHIE] Bits */ -#define PSS_IE_SVSMHIE_OFS ( 1) /*!< SVSMHIE Bit Offset */ -#define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /*!< High-side SVSM interrupt enable */ -/* PSS_IFG[SVSMHIFG] Bits */ -#define PSS_IFG_SVSMHIFG_OFS ( 1) /*!< SVSMHIFG Bit Offset */ -#define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /*!< High-side SVSM interrupt flag */ -/* PSS_CLRIFG[CLRSVSMHIFG] Bits */ -#define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /*!< CLRSVSMHIFG Bit Offset */ -#define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /*!< SVSMH clear interrupt flag */ -/* Pre-defined bitfield values */ -#define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /*!< PSS control key value */ - - -/****************************************************************************** -* REF_A Bits -******************************************************************************/ -/* REF_A_CTL0[ON] Bits */ -#define REF_A_CTL0_ON_OFS ( 0) /*!< REFON Bit Offset */ -#define REF_A_CTL0_ON ((uint16_t)0x0001) /*!< Reference enable */ -/* REF_A_CTL0[OUT] Bits */ -#define REF_A_CTL0_OUT_OFS ( 1) /*!< REFOUT Bit Offset */ -#define REF_A_CTL0_OUT ((uint16_t)0x0002) /*!< Reference output buffer */ -/* REF_A_CTL0[TCOFF] Bits */ -#define REF_A_CTL0_TCOFF_OFS ( 3) /*!< REFTCOFF Bit Offset */ -#define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /*!< Temperature sensor disabled */ -/* REF_A_CTL0[VSEL] Bits */ -#define REF_A_CTL0_VSEL_OFS ( 4) /*!< REFVSEL Bit Offset */ -#define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /*!< REFVSEL Bit Mask */ -#define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /*!< VSEL Bit 0 */ -#define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /*!< VSEL Bit 1 */ -#define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /*!< 1.2 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /*!< 1.45 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /*!< 2.5 V available when reference requested or REFON = 1 */ -/* REF_A_CTL0[GENOT] Bits */ -#define REF_A_CTL0_GENOT_OFS ( 6) /*!< REFGENOT Bit Offset */ -#define REF_A_CTL0_GENOT ((uint16_t)0x0040) /*!< Reference generator one-time trigger */ -/* REF_A_CTL0[BGOT] Bits */ -#define REF_A_CTL0_BGOT_OFS ( 7) /*!< REFBGOT Bit Offset */ -#define REF_A_CTL0_BGOT ((uint16_t)0x0080) /*!< Bandgap and bandgap buffer one-time trigger */ -/* REF_A_CTL0[GENACT] Bits */ -#define REF_A_CTL0_GENACT_OFS ( 8) /*!< REFGENACT Bit Offset */ -#define REF_A_CTL0_GENACT ((uint16_t)0x0100) /*!< Reference generator active */ -/* REF_A_CTL0[BGACT] Bits */ -#define REF_A_CTL0_BGACT_OFS ( 9) /*!< REFBGACT Bit Offset */ -#define REF_A_CTL0_BGACT ((uint16_t)0x0200) /*!< Reference bandgap active */ -/* REF_A_CTL0[GENBUSY] Bits */ -#define REF_A_CTL0_GENBUSY_OFS (10) /*!< REFGENBUSY Bit Offset */ -#define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /*!< Reference generator busy */ -/* REF_A_CTL0[BGMODE] Bits */ -#define REF_A_CTL0_BGMODE_OFS (11) /*!< BGMODE Bit Offset */ -#define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /*!< Bandgap mode */ -/* REF_A_CTL0[GENRDY] Bits */ -#define REF_A_CTL0_GENRDY_OFS (12) /*!< REFGENRDY Bit Offset */ -#define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /*!< Variable reference voltage ready status */ -/* REF_A_CTL0[BGRDY] Bits */ -#define REF_A_CTL0_BGRDY_OFS (13) /*!< REFBGRDY Bit Offset */ -#define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /*!< Buffered bandgap voltage ready status */ - -/****************************************************************************** -* RSTCTL Bits -******************************************************************************/ -/* RSTCTL_RESET_REQ[SOFT_REQ] Bits */ -#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /*!< SOFT_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /*!< Soft Reset request */ -/* RSTCTL_RESET_REQ[HARD_REQ] Bits */ -#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /*!< HARD_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /*!< Hard Reset request */ -/* RSTCTL_RESET_REQ[RSTKEY] Bits */ -#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /*!< RSTKEY Bit Offset */ -#define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /*!< RSTKEY Bit Mask */ -/* RSTCTL_HARDRESET_STAT[SRC0] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< Indicates that SRC0 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC1] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< Indicates that SRC1 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC2] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< Indicates that SRC2 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC3] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< Indicates that SRC3 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC4] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< Indicates that SRC4 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC5] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< Indicates that SRC5 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC6] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< Indicates that SRC6 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC7] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< Indicates that SRC7 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC8] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< Indicates that SRC8 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC9] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< Indicates that SRC9 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC10] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< Indicates that SRC10 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC11] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< Indicates that SRC11 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC12] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< Indicates that SRC12 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC13] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< Indicates that SRC13 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC14] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< Indicates that SRC14 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC15] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< Indicates that SRC15 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_CLR[SRC0] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC1] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC2] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC3] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC4] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC5] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC6] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC7] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC8] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC9] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC10] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC11] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC12] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC13] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC14] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC15] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */ -/* RSTCTL_HARDRESET_SET[SRC0] Bits */ -#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC1] Bits */ -#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC2] Bits */ -#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC3] Bits */ -#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC4] Bits */ -#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC5] Bits */ -#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC6] Bits */ -#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC7] Bits */ -#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC8] Bits */ -#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC9] Bits */ -#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC10] Bits */ -#define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC11] Bits */ -#define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC12] Bits */ -#define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC13] Bits */ -#define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC14] Bits */ -#define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC15] Bits */ -#define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_SOFTRESET_STAT[SRC0] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< If 1, indicates that SRC0 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC1] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< If 1, indicates that SRC1 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC2] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< If 1, indicates that SRC2 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC3] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< If 1, indicates that SRC3 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC4] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< If 1, indicates that SRC4 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC5] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< If 1, indicates that SRC5 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC6] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< If 1, indicates that SRC6 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC7] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< If 1, indicates that SRC7 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC8] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< If 1, indicates that SRC8 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC9] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< If 1, indicates that SRC9 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC10] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< If 1, indicates that SRC10 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC11] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< If 1, indicates that SRC11 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC12] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< If 1, indicates that SRC12 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC13] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< If 1, indicates that SRC13 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC14] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< If 1, indicates that SRC14 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC15] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< If 1, indicates that SRC15 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_CLR[SRC0] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC1] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC2] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC3] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC4] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC5] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC6] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC7] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC8] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC9] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC10] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC11] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC12] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC13] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC14] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC15] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_SET[SRC0] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC1] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC2] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC3] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC4] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC5] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC6] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC7] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC8] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC9] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC10] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC11] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC12] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC13] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC14] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC15] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_PSSRESET_STAT[SVSMH] Bits */ -#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /*!< SVSMH Bit Offset */ -#define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */ -/* RSTCTL_PSSRESET_STAT[BGREF] Bits */ -#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /*!< BGREF Bit Offset */ -#define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */ -/* RSTCTL_PSSRESET_STAT[VCCDET] Bits */ -#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /*!< VCCDET Bit Offset */ -#define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */ -/* RSTCTL_PSSRESET_CLR[CLR] Bits */ -#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */ -/* RSTCTL_PCMRESET_STAT[LPM35] Bits */ -#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /*!< LPM35 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */ -/* RSTCTL_PCMRESET_STAT[LPM45] Bits */ -#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /*!< LPM45 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */ -/* RSTCTL_PCMRESET_CLR[CLR] Bits */ -#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */ -/* RSTCTL_PINRESET_STAT[RSTNMI] Bits */ -#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /*!< RSTNMI Bit Offset */ -#define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /*!< POR was caused by RSTn/NMI pin based reset event */ -/* RSTCTL_PINRESET_CLR[CLR] Bits */ -#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */ -/* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /*!< Indicates if Reboot reset was caused by the SYSCTL module. */ -/* RSTCTL_REBOOTRESET_CLR[CLR] Bits */ -#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */ -/* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /*!< DCOR_SHT Bit Offset */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /*!< Indicates if POR was caused by DCO short circuit fault in the external */ - /* resistor mode */ -/* RSTCTL_CSRESET_CLR[CLR] Bits */ -#define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as */ - /* DCOR_SHTIFG flag in CSIFG register of clock system */ -/* Pre-defined bitfield values */ -#define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bits 1-0 */ - - -/****************************************************************************** -* RTC_C Bits -******************************************************************************/ -/* RTC_C_CTL0[RDYIFG] Bits */ -#define RTC_C_CTL0_RDYIFG_OFS ( 0) /*!< RTCRDYIFG Bit Offset */ -#define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /*!< Real-time clock ready interrupt flag */ -/* RTC_C_CTL0[AIFG] Bits */ -#define RTC_C_CTL0_AIFG_OFS ( 1) /*!< RTCAIFG Bit Offset */ -#define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /*!< Real-time clock alarm interrupt flag */ -/* RTC_C_CTL0[TEVIFG] Bits */ -#define RTC_C_CTL0_TEVIFG_OFS ( 2) /*!< RTCTEVIFG Bit Offset */ -#define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /*!< Real-time clock time event interrupt flag */ -/* RTC_C_CTL0[OFIFG] Bits */ -#define RTC_C_CTL0_OFIFG_OFS ( 3) /*!< RTCOFIFG Bit Offset */ -#define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /*!< 32-kHz crystal oscillator fault interrupt flag */ -/* RTC_C_CTL0[RDYIE] Bits */ -#define RTC_C_CTL0_RDYIE_OFS ( 4) /*!< RTCRDYIE Bit Offset */ -#define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /*!< Real-time clock ready interrupt enable */ -/* RTC_C_CTL0[AIE] Bits */ -#define RTC_C_CTL0_AIE_OFS ( 5) /*!< RTCAIE Bit Offset */ -#define RTC_C_CTL0_AIE ((uint16_t)0x0020) /*!< Real-time clock alarm interrupt enable */ -/* RTC_C_CTL0[TEVIE] Bits */ -#define RTC_C_CTL0_TEVIE_OFS ( 6) /*!< RTCTEVIE Bit Offset */ -#define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /*!< Real-time clock time event interrupt enable */ -/* RTC_C_CTL0[OFIE] Bits */ -#define RTC_C_CTL0_OFIE_OFS ( 7) /*!< RTCOFIE Bit Offset */ -#define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /*!< 32-kHz crystal oscillator fault interrupt enable */ -/* RTC_C_CTL0[KEY] Bits */ -#define RTC_C_CTL0_KEY_OFS ( 8) /*!< RTCKEY Bit Offset */ -#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /*!< RTCKEY Bit Mask */ -/* RTC_C_CTL13[TEV] Bits */ -#define RTC_C_CTL13_TEV_OFS ( 0) /*!< RTCTEV Bit Offset */ -#define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /*!< RTCTEV Bit Mask */ -#define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /*!< TEV Bit 0 */ -#define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /*!< TEV Bit 1 */ -#define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /*!< Minute changed */ -#define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /*!< Hour changed */ -#define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /*!< Every day at midnight (00:00) */ -#define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /*!< Every day at noon (12:00) */ -/* RTC_C_CTL13[SSEL] Bits */ -#define RTC_C_CTL13_SSEL_OFS ( 2) /*!< RTCSSEL Bit Offset */ -#define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /*!< RTCSSEL Bit Mask */ -#define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /*!< SSEL Bit 0 */ -#define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /*!< SSEL Bit 1 */ -#define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /*!< BCLK */ -#define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /*!< BCLK */ -/* RTC_C_CTL13[RDY] Bits */ -#define RTC_C_CTL13_RDY_OFS ( 4) /*!< RTCRDY Bit Offset */ -#define RTC_C_CTL13_RDY ((uint16_t)0x0010) /*!< Real-time clock ready */ -/* RTC_C_CTL13[MODE] Bits */ -#define RTC_C_CTL13_MODE_OFS ( 5) /*!< RTCMODE Bit Offset */ -#define RTC_C_CTL13_MODE ((uint16_t)0x0020) -/* RTC_C_CTL13[HOLD] Bits */ -#define RTC_C_CTL13_HOLD_OFS ( 6) /*!< RTCHOLD Bit Offset */ -#define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /*!< Real-time clock hold */ -/* RTC_C_CTL13[BCD] Bits */ -#define RTC_C_CTL13_BCD_OFS ( 7) /*!< RTCBCD Bit Offset */ -#define RTC_C_CTL13_BCD ((uint16_t)0x0080) /*!< Real-time clock BCD select */ -/* RTC_C_CTL13[CALF] Bits */ -#define RTC_C_CTL13_CALF_OFS ( 8) /*!< RTCCALF Bit Offset */ -#define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /*!< RTCCALF Bit Mask */ -#define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /*!< CALF Bit 0 */ -#define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /*!< CALF Bit 1 */ -#define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /*!< 1 Hz */ -#define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /*!< 1 Hz */ -/* RTC_C_OCAL[OCAL] Bits */ -#define RTC_C_OCAL_OCAL_OFS ( 0) /*!< RTCOCAL Bit Offset */ -#define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /*!< RTCOCAL Bit Mask */ -/* RTC_C_OCAL[OCALS] Bits */ -#define RTC_C_OCAL_OCALS_OFS (15) /*!< RTCOCALS Bit Offset */ -#define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /*!< Real-time clock offset error calibration sign */ -/* RTC_C_TCMP[TCMPx] Bits */ -#define RTC_C_TCMP_TCMPX_OFS ( 0) /*!< RTCTCMP Bit Offset */ -#define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /*!< RTCTCMP Bit Mask */ -/* RTC_C_TCMP[TCOK] Bits */ -#define RTC_C_TCMP_TCOK_OFS (13) /*!< RTCTCOK Bit Offset */ -#define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /*!< Real-time clock temperature compensation write OK */ -/* RTC_C_TCMP[TCRDY] Bits */ -#define RTC_C_TCMP_TCRDY_OFS (14) /*!< RTCTCRDY Bit Offset */ -#define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /*!< Real-time clock temperature compensation ready */ -/* RTC_C_TCMP[TCMPS] Bits */ -#define RTC_C_TCMP_TCMPS_OFS (15) /*!< RTCTCMPS Bit Offset */ -#define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /*!< Real-time clock temperature compensation sign */ -/* RTC_C_PS0CTL[RT0PSIFG] Bits */ -#define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /*!< RT0PSIFG Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /*!< Prescale timer 0 interrupt flag */ -/* RTC_C_PS0CTL[RT0PSIE] Bits */ -#define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /*!< RT0PSIE Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /*!< Prescale timer 0 interrupt enable */ -/* RTC_C_PS0CTL[RT0IP] Bits */ -#define RTC_C_PS0CTL_RT0IP_OFS ( 2) /*!< RT0IP Bit Offset */ -#define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /*!< RT0IP Bit Mask */ -#define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /*!< RT0IP Bit 0 */ -#define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /*!< RT0IP Bit 1 */ -#define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /*!< RT0IP Bit 2 */ -#define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -/* RTC_C_PS1CTL[RT1PSIFG] Bits */ -#define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /*!< RT1PSIFG Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /*!< Prescale timer 1 interrupt flag */ -/* RTC_C_PS1CTL[RT1PSIE] Bits */ -#define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /*!< RT1PSIE Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /*!< Prescale timer 1 interrupt enable */ -/* RTC_C_PS1CTL[RT1IP] Bits */ -#define RTC_C_PS1CTL_RT1IP_OFS ( 2) /*!< RT1IP Bit Offset */ -#define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /*!< RT1IP Bit Mask */ -#define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /*!< RT1IP Bit 0 */ -#define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /*!< RT1IP Bit 1 */ -#define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /*!< RT1IP Bit 2 */ -#define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -/* RTC_C_PS[RT0PS] Bits */ -#define RTC_C_PS_RT0PS_OFS ( 0) /*!< RT0PS Bit Offset */ -#define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /*!< RT0PS Bit Mask */ -/* RTC_C_PS[RT1PS] Bits */ -#define RTC_C_PS_RT1PS_OFS ( 8) /*!< RT1PS Bit Offset */ -#define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /*!< RT1PS Bit Mask */ -/* RTC_C_TIM0[SEC] Bits */ -#define RTC_C_TIM0_SEC_OFS ( 0) /*!< Seconds Bit Offset */ -#define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /*!< Seconds Bit Mask */ -/* RTC_C_TIM0[MIN] Bits */ -#define RTC_C_TIM0_MIN_OFS ( 8) /*!< Minutes Bit Offset */ -#define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /*!< Minutes Bit Mask */ -/* RTC_C_TIM0[SEC_LD] Bits */ -#define RTC_C_TIM0_SEC_LD_OFS ( 0) /*!< SecondsLowDigit Bit Offset */ -#define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /*!< SecondsLowDigit Bit Mask */ -/* RTC_C_TIM0[SEC_HD] Bits */ -#define RTC_C_TIM0_SEC_HD_OFS ( 4) /*!< SecondsHighDigit Bit Offset */ -#define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /*!< SecondsHighDigit Bit Mask */ -/* RTC_C_TIM0[MIN_LD] Bits */ -#define RTC_C_TIM0_MIN_LD_OFS ( 8) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /*!< MinutesLowDigit Bit Mask */ -/* RTC_C_TIM0[MIN_HD] Bits */ -#define RTC_C_TIM0_MIN_HD_OFS (12) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /*!< MinutesHighDigit Bit Mask */ -/* RTC_C_TIM1[HOUR] Bits */ -#define RTC_C_TIM1_HOUR_OFS ( 0) /*!< Hours Bit Offset */ -#define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /*!< Hours Bit Mask */ -/* RTC_C_TIM1[DOW] Bits */ -#define RTC_C_TIM1_DOW_OFS ( 8) /*!< DayofWeek Bit Offset */ -#define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /*!< DayofWeek Bit Mask */ -/* RTC_C_TIM1[HOUR_LD] Bits */ -#define RTC_C_TIM1_HOUR_LD_OFS ( 0) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /*!< HoursLowDigit Bit Mask */ -/* RTC_C_TIM1[HOUR_HD] Bits */ -#define RTC_C_TIM1_HOUR_HD_OFS ( 4) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /*!< HoursHighDigit Bit Mask */ -/* RTC_C_DATE[DAY] Bits */ -#define RTC_C_DATE_DAY_OFS ( 0) /*!< Day Bit Offset */ -#define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /*!< Day Bit Mask */ -/* RTC_C_DATE[MON] Bits */ -#define RTC_C_DATE_MON_OFS ( 8) /*!< Month Bit Offset */ -#define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /*!< Month Bit Mask */ -/* RTC_C_DATE[DAY_LD] Bits */ -#define RTC_C_DATE_DAY_LD_OFS ( 0) /*!< DayLowDigit Bit Offset */ -#define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /*!< DayLowDigit Bit Mask */ -/* RTC_C_DATE[DAY_HD] Bits */ -#define RTC_C_DATE_DAY_HD_OFS ( 4) /*!< DayHighDigit Bit Offset */ -#define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /*!< DayHighDigit Bit Mask */ -/* RTC_C_DATE[MON_LD] Bits */ -#define RTC_C_DATE_MON_LD_OFS ( 8) /*!< MonthLowDigit Bit Offset */ -#define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /*!< MonthLowDigit Bit Mask */ -/* RTC_C_DATE[MON_HD] Bits */ -#define RTC_C_DATE_MON_HD_OFS (12) /*!< MonthHighDigit Bit Offset */ -#define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /*!< Month high digit (0 or 1) */ -/* RTC_C_YEAR[YEAR_LB] Bits */ -#define RTC_C_YEAR_YEAR_LB_OFS ( 0) /*!< YearLowByte Bit Offset */ -#define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /*!< YearLowByte Bit Mask */ -/* RTC_C_YEAR[YEAR_HB] Bits */ -#define RTC_C_YEAR_YEAR_HB_OFS ( 8) /*!< YearHighByte Bit Offset */ -#define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /*!< YearHighByte Bit Mask */ -/* RTC_C_YEAR[YEAR] Bits */ -#define RTC_C_YEAR_YEAR_OFS ( 0) /*!< Year Bit Offset */ -#define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /*!< Year Bit Mask */ -/* RTC_C_YEAR[DEC] Bits */ -#define RTC_C_YEAR_DEC_OFS ( 4) /*!< Decade Bit Offset */ -#define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /*!< Decade Bit Mask */ -/* RTC_C_YEAR[CENT_LD] Bits */ -#define RTC_C_YEAR_CENT_LD_OFS ( 8) /*!< CenturyLowDigit Bit Offset */ -#define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /*!< CenturyLowDigit Bit Mask */ -/* RTC_C_YEAR[CENT_HD] Bits */ -#define RTC_C_YEAR_CENT_HD_OFS (12) /*!< CenturyHighDigit Bit Offset */ -#define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /*!< CenturyHighDigit Bit Mask */ -/* RTC_C_AMINHR[MIN] Bits */ -#define RTC_C_AMINHR_MIN_OFS ( 0) /*!< Minutes Bit Offset */ -#define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /*!< Minutes Bit Mask */ -/* RTC_C_AMINHR[MINAE] Bits */ -#define RTC_C_AMINHR_MINAE_OFS ( 7) /*!< MINAE Bit Offset */ -#define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /*!< Alarm enable */ -/* RTC_C_AMINHR[HOUR] Bits */ -#define RTC_C_AMINHR_HOUR_OFS ( 8) /*!< Hours Bit Offset */ -#define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /*!< Hours Bit Mask */ -/* RTC_C_AMINHR[HOURAE] Bits */ -#define RTC_C_AMINHR_HOURAE_OFS (15) /*!< HOURAE Bit Offset */ -#define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /*!< Alarm enable */ -/* RTC_C_AMINHR[MIN_LD] Bits */ -#define RTC_C_AMINHR_MIN_LD_OFS ( 0) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /*!< MinutesLowDigit Bit Mask */ -/* RTC_C_AMINHR[MIN_HD] Bits */ -#define RTC_C_AMINHR_MIN_HD_OFS ( 4) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /*!< MinutesHighDigit Bit Mask */ -/* RTC_C_AMINHR[HOUR_LD] Bits */ -#define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /*!< HoursLowDigit Bit Mask */ -/* RTC_C_AMINHR[HOUR_HD] Bits */ -#define RTC_C_AMINHR_HOUR_HD_OFS (12) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /*!< HoursHighDigit Bit Mask */ -/* RTC_C_ADOWDAY[DOW] Bits */ -#define RTC_C_ADOWDAY_DOW_OFS ( 0) /*!< DayofWeek Bit Offset */ -#define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /*!< DayofWeek Bit Mask */ -/* RTC_C_ADOWDAY[DOWAE] Bits */ -#define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /*!< DOWAE Bit Offset */ -#define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /*!< Alarm enable */ -/* RTC_C_ADOWDAY[DAY] Bits */ -#define RTC_C_ADOWDAY_DAY_OFS ( 8) /*!< DayofMonth Bit Offset */ -#define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /*!< DayofMonth Bit Mask */ -/* RTC_C_ADOWDAY[DAYAE] Bits */ -#define RTC_C_ADOWDAY_DAYAE_OFS (15) /*!< DAYAE Bit Offset */ -#define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /*!< Alarm enable */ -/* RTC_C_ADOWDAY[DAY_LD] Bits */ -#define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /*!< DayLowDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /*!< DayLowDigit Bit Mask */ -/* RTC_C_ADOWDAY[DAY_HD] Bits */ -#define RTC_C_ADOWDAY_DAY_HD_OFS (12) /*!< DayHighDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /*!< DayHighDigit Bit Mask */ -/* Pre-defined bitfield values */ -#define RTC_C_KEY ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_H ((uint16_t)0x00A5) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_VAL ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ - - -/****************************************************************************** -* SCB Bits -******************************************************************************/ -/* SCB_PFR0[STATE0] Bits */ -#define SCB_PFR0_STATE0_OFS ( 0) /*!< STATE0 Bit Offset */ -#define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /*!< STATE0 Bit Mask */ -#define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /*!< STATE0 Bit 0 */ -#define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /*!< STATE0 Bit 1 */ -#define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /*!< STATE0 Bit 2 */ -#define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /*!< STATE0 Bit 3 */ -#define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /*!< no ARM encoding */ -#define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /*!< N/A */ -/* SCB_PFR0[STATE1] Bits */ -#define SCB_PFR0_STATE1_OFS ( 4) /*!< STATE1 Bit Offset */ -#define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /*!< STATE1 Bit Mask */ -#define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /*!< STATE1 Bit 0 */ -#define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /*!< STATE1 Bit 1 */ -#define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /*!< STATE1 Bit 2 */ -#define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /*!< STATE1 Bit 3 */ -#define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /*!< N/A */ -#define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /*!< N/A */ -#define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL */ - /* but no other 32-bit basic instructions (Note non-basic 32-bit instructions */ - /* can be added using the appropriate instruction attribute, but other 32-bit */ - /* basic instructions cannot.) */ -#define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /*!< Thumb-2 encoding with all Thumb-2 basic instructions */ -/* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /*!< two-stack support */ -/* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */ -/* SCB_MMFR0[PMSA_SUPPORT] Bits */ -#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /*!< PMSA_SUPPORT Bit Offset */ -#define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /*!< PMSA_SUPPORT Bit Mask */ -#define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /*!< PMSA_SUPPORT Bit 0 */ -#define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /*!< PMSA_SUPPORT Bit 1 */ -#define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /*!< PMSA_SUPPORT Bit 2 */ -#define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /*!< PMSA_SUPPORT Bit 3 */ -#define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /*!< IMPLEMENTATION DEFINED (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /*!< PMSA base (features as defined for ARMv6) (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /*!< PMSAv7 (base plus subregion support) */ -/* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /*!< CACHE_COHERENCE_SUPPORT Bit Offset */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /*!< CACHE_COHERENCE_SUPPORT Bit Mask */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /*!< CACHE_COHERENCE_SUPPORT Bit 0 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /*!< CACHE_COHERENCE_SUPPORT Bit 1 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /*!< CACHE_COHERENCE_SUPPORT Bit 2 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /*!< CACHE_COHERENCE_SUPPORT Bit 3 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /*!< no shared support */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /*!< partial-inner-shared coherency (coherency amongst some - but not all - of */ - /* the entities within an inner-coherent domain) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /*!< full-inner-shared coherency (coherency amongst all of the entities within an */ - /* inner-coherent domain) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /*!< full coherency (coherency amongst all of the entities) */ -/* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /*!< Outer non-sharable not supported */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /*!< Outer sharable supported */ -/* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /*!< Auxiliary control register */ -/* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /*!< wait for interrupt supported */ -/* SCB_ISAR0[BITCOUNT_INSTRS] Bits */ -#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /*!< BITCOUNT_INSTRS Bit Offset */ -#define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< BITCOUNT_INSTRS Bit Mask */ -#define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /*!< BITCOUNT_INSTRS Bit 0 */ -#define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /*!< BITCOUNT_INSTRS Bit 1 */ -#define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /*!< BITCOUNT_INSTRS Bit 2 */ -#define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /*!< BITCOUNT_INSTRS Bit 3 */ -#define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /*!< no bit-counting instructions present */ -#define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds CLZ */ -/* SCB_ISAR0[BITFIELD_INSTRS] Bits */ -#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /*!< BITFIELD_INSTRS Bit Offset */ -#define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /*!< BITFIELD_INSTRS Bit Mask */ -#define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /*!< BITFIELD_INSTRS Bit 0 */ -#define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /*!< BITFIELD_INSTRS Bit 1 */ -#define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /*!< BITFIELD_INSTRS Bit 2 */ -#define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /*!< BITFIELD_INSTRS Bit 3 */ -#define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /*!< no bitfield instructions present */ -#define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /*!< adds BFC, BFI, SBFX, UBFX */ -/* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /*!< CMPBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /*!< CMPBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /*!< CMPBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /*!< CMPBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /*!< CMPBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /*!< CMPBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no combined compare-and-branch instructions present */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /*!< adds CB{N}Z */ -/* SCB_ISAR0[COPROC_INSTRS] Bits */ -#define SCB_ISAR0_COPROC_INSTRS_OFS (16) /*!< COPROC_INSTRS Bit Offset */ -#define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /*!< COPROC_INSTRS Bit Mask */ -#define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /*!< COPROC_INSTRS Bit 0 */ -#define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /*!< COPROC_INSTRS Bit 1 */ -#define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /*!< COPROC_INSTRS Bit 2 */ -#define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /*!< COPROC_INSTRS Bit 3 */ -#define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /*!< no coprocessor support, other than for separately attributed architectures */ - /* such as CP15 or VFP */ -#define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /*!< adds generic CDP, LDC, MCR, MRC, STC */ -#define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */ -#define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /*!< adds generic MCRR, MRRC */ -#define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /*!< adds generic MCRR2, MRRC2 */ -/* SCB_ISAR0[DEBUG_INSTRS] Bits */ -#define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /*!< DEBUG_INSTRS Bit Offset */ -#define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /*!< DEBUG_INSTRS Bit Mask */ -#define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /*!< DEBUG_INSTRS Bit 0 */ -#define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /*!< DEBUG_INSTRS Bit 1 */ -#define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /*!< DEBUG_INSTRS Bit 2 */ -#define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /*!< DEBUG_INSTRS Bit 3 */ -#define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /*!< no debug instructions present */ -#define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /*!< adds BKPT */ -/* SCB_ISAR0[DIVIDE_INSTRS] Bits */ -#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /*!< DIVIDE_INSTRS Bit Offset */ -#define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /*!< DIVIDE_INSTRS Bit Mask */ -#define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /*!< DIVIDE_INSTRS Bit 0 */ -#define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /*!< DIVIDE_INSTRS Bit 1 */ -#define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /*!< DIVIDE_INSTRS Bit 2 */ -#define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /*!< DIVIDE_INSTRS Bit 3 */ -#define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /*!< no divide instructions present */ -#define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /*!< adds SDIV, UDIV (v1 quotient only result) */ -/* SCB_ISAR1[ETEND_INSRS] Bits */ -#define SCB_ISAR1_ETEND_INSRS_OFS (12) /*!< EXTEND_INSRS Bit Offset */ -#define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /*!< EXTEND_INSRS Bit Mask */ -#define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /*!< ETEND_INSRS Bit 0 */ -#define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /*!< ETEND_INSRS Bit 1 */ -#define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /*!< ETEND_INSRS Bit 2 */ -#define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /*!< ETEND_INSRS Bit 3 */ -#define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */ -#define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /*!< adds SXTB, SXTH, UXTB, UXTH */ -#define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /*!< N/A */ -/* SCB_ISAR1[IFTHEN_INSTRS] Bits */ -#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /*!< IFTHEN_INSTRS Bit Offset */ -#define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /*!< IFTHEN_INSTRS Bit Mask */ -#define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /*!< IFTHEN_INSTRS Bit 0 */ -#define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /*!< IFTHEN_INSTRS Bit 1 */ -#define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /*!< IFTHEN_INSTRS Bit 2 */ -#define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /*!< IFTHEN_INSTRS Bit 3 */ -#define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /*!< IT instructions not present */ -#define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /*!< adds IT instructions (and IT bits in PSRs) */ -/* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /*!< IMMEDIATE_INSTRS Bit Offset */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /*!< IMMEDIATE_INSTRS Bit Mask */ -#define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /*!< IMMEDIATE_INSTRS Bit 0 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /*!< IMMEDIATE_INSTRS Bit 1 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /*!< IMMEDIATE_INSTRS Bit 2 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /*!< IMMEDIATE_INSTRS Bit 3 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no special immediate-generating instructions present */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /*!< adds ADDW, MOVW, MOVT, SUBW */ -/* SCB_ISAR1[INTERWORK_INSTRS] Bits */ -#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /*!< INTERWORK_INSTRS Bit Offset */ -#define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /*!< INTERWORK_INSTRS Bit Mask */ -#define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /*!< INTERWORK_INSTRS Bit 0 */ -#define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /*!< INTERWORK_INSTRS Bit 1 */ -#define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /*!< INTERWORK_INSTRS Bit 2 */ -#define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /*!< INTERWORK_INSTRS Bit 3 */ -#define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /*!< no interworking instructions supported */ -#define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /*!< adds BX (and T bit in PSRs) */ -#define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /*!< adds BLX, and PC loads have BX-like behavior */ -#define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /*!< N/A */ -/* SCB_ISAR2[LOADSTORE_INSTRS] Bits */ -#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /*!< LOADSTORE_INSTRS Bit Offset */ -#define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< LOADSTORE_INSTRS Bit Mask */ -#define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /*!< LOADSTORE_INSTRS Bit 0 */ -#define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /*!< LOADSTORE_INSTRS Bit 1 */ -#define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /*!< LOADSTORE_INSTRS Bit 2 */ -#define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /*!< LOADSTORE_INSTRS Bit 3 */ -#define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /*!< no additional normal load/store instructions present */ -#define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRD/STRD */ -/* SCB_ISAR2[MEMHINT_INSTRS] Bits */ -#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /*!< MEMHINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< MEMHINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /*!< MEMHINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /*!< MEMHINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /*!< MEMHINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /*!< MEMHINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /*!< no memory hint instructions presen */ -#define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds PLD */ -#define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /*!< adds PLD (ie a repeat on value 1) */ -#define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /*!< adds PLI */ -/* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /*!< MULTIACCESSINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /*!< MULTIACCESSINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /*!< MULTIACCESSINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /*!< MULTIACCESSINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /*!< MULTIACCESSINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /*!< MULTIACCESSINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /*!< the (LDM/STM) instructions are non-interruptible */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /*!< the (LDM/STM) instructions are restartable */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /*!< the (LDM/STM) instructions are continuable */ -/* SCB_ISAR2[MULT_INSTRS] Bits */ -#define SCB_ISAR2_MULT_INSTRS_OFS (12) /*!< MULT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /*!< MULT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /*!< MULT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /*!< MULT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /*!< MULT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /*!< MULT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /*!< only MUL present */ -#define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /*!< adds MLA */ -#define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /*!< adds MLS */ -/* SCB_ISAR2[MULTS_INSTRS] Bits */ -#define SCB_ISAR2_MULTS_INSTRS_OFS (16) /*!< MULTS_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /*!< MULTS_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /*!< MULTS_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /*!< MULTS_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /*!< MULTS_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /*!< MULTS_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /*!< no signed multiply instructions present */ -#define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /*!< adds SMULL, SMLAL */ -#define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /*!< N/A */ -#define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /*!< N/A */ -/* SCB_ISAR2[MULTU_INSTRS] Bits */ -#define SCB_ISAR2_MULTU_INSTRS_OFS (20) /*!< MULTU_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /*!< MULTU_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /*!< MULTU_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /*!< MULTU_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /*!< MULTU_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /*!< MULTU_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /*!< no unsigned multiply instructions present */ -#define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /*!< adds UMULL, UMLAL */ -#define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /*!< N/A */ -/* SCB_ISAR2[REVERSAL_INSTRS] Bits */ -#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /*!< REVERSAL_INSTRS Bit Offset */ -#define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /*!< REVERSAL_INSTRS Bit Mask */ -#define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /*!< REVERSAL_INSTRS Bit 0 */ -#define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /*!< REVERSAL_INSTRS Bit 1 */ -#define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /*!< REVERSAL_INSTRS Bit 2 */ -#define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /*!< REVERSAL_INSTRS Bit 3 */ -#define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /*!< no reversal instructions present */ -#define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /*!< adds REV, REV16, REVSH */ -#define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /*!< adds RBIT */ -/* SCB_ISAR3[SATRUATE_INSTRS] Bits */ -#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /*!< SATRUATE_INSTRS Bit Offset */ -#define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< SATRUATE_INSTRS Bit Mask */ -#define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /*!< SATRUATE_INSTRS Bit 0 */ -#define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /*!< SATRUATE_INSTRS Bit 1 */ -#define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /*!< SATRUATE_INSTRS Bit 2 */ -#define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /*!< SATRUATE_INSTRS Bit 3 */ -#define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no non-SIMD saturate instructions present */ -#define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /*!< N/A */ -/* SCB_ISAR3[SIMD_INSTRS] Bits */ -#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /*!< SIMD_INSTRS Bit Offset */ -#define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /*!< SIMD_INSTRS Bit Mask */ -#define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /*!< SIMD_INSTRS Bit 0 */ -#define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /*!< SIMD_INSTRS Bit 1 */ -#define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /*!< SIMD_INSTRS Bit 2 */ -#define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /*!< SIMD_INSTRS Bit 3 */ -#define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /*!< no SIMD instructions present */ -#define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /*!< adds SSAT, USAT (and the Q flag in the PSRs) */ -#define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /*!< N/A */ -/* SCB_ISAR3[SVC_INSTRS] Bits */ -#define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /*!< SVC_INSTRS Bit Offset */ -#define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /*!< SVC_INSTRS Bit Mask */ -#define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /*!< SVC_INSTRS Bit 0 */ -#define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /*!< SVC_INSTRS Bit 1 */ -#define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /*!< SVC_INSTRS Bit 2 */ -#define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /*!< SVC_INSTRS Bit 3 */ -#define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /*!< no SVC (SWI) instructions present */ -#define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /*!< adds SVC (SWI) */ -/* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /*!< SYNCPRIM_INSTRS Bit Offset */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /*!< SYNCPRIM_INSTRS Bit Mask */ -#define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /*!< SYNCPRIM_INSTRS Bit 0 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /*!< SYNCPRIM_INSTRS Bit 1 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /*!< SYNCPRIM_INSTRS Bit 2 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /*!< SYNCPRIM_INSTRS Bit 3 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /*!< no synchronization primitives present */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /*!< adds LDREX, STREX */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */ -/* SCB_ISAR3[TABBRANCH_INSTRS] Bits */ -#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /*!< TABBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /*!< TABBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /*!< TABBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /*!< TABBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /*!< TABBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /*!< TABBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no table-branch instructions present */ -#define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /*!< adds TBB, TBH */ -/* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /*!< THUMBCOPY_INSTRS Bit Offset */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /*!< THUMBCOPY_INSTRS Bit Mask */ -#define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /*!< THUMBCOPY_INSTRS Bit 0 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /*!< THUMBCOPY_INSTRS Bit 1 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /*!< THUMBCOPY_INSTRS Bit 2 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /*!< THUMBCOPY_INSTRS Bit 3 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */ -/* SCB_ISAR3[TRUENOP_INSTRS] Bits */ -#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /*!< TRUENOP_INSTRS Bit Offset */ -#define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /*!< TRUENOP_INSTRS Bit Mask */ -#define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /*!< TRUENOP_INSTRS Bit 0 */ -#define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /*!< TRUENOP_INSTRS Bit 1 */ -#define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /*!< TRUENOP_INSTRS Bit 2 */ -#define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /*!< TRUENOP_INSTRS Bit 3 */ -#define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /*!< true NOP instructions not present - that is, NOP instructions with no */ - /* register dependencies */ -#define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */ -/* SCB_ISAR4[UNPRIV_INSTRS] Bits */ -#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /*!< UNPRIV_INSTRS Bit Offset */ -#define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /*!< UNPRIV_INSTRS Bit Mask */ -#define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /*!< UNPRIV_INSTRS Bit 0 */ -#define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /*!< UNPRIV_INSTRS Bit 1 */ -#define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /*!< UNPRIV_INSTRS Bit 2 */ -#define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /*!< UNPRIV_INSTRS Bit 3 */ -#define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /*!< no "T variant" instructions exist */ -#define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRBT, LDRT, STRBT, STRT */ -#define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */ -/* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /*!< WITHSHIFTS_INSTRS Bit Offset */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /*!< WITHSHIFTS_INSTRS Bit Mask */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /*!< WITHSHIFTS_INSTRS Bit 0 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /*!< WITHSHIFTS_INSTRS Bit 1 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /*!< WITHSHIFTS_INSTRS Bit 2 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /*!< WITHSHIFTS_INSTRS Bit 3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /*!< non-zero shifts only support MOV and shift instructions (see notes) */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /*!< shifts of loads/stores over the range LSL 0-3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /*!< adds other constant shift options. */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /*!< adds register-controlled shift options. */ -/* SCB_ISAR4[WRITEBACK_INSTRS] Bits */ -#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /*!< WRITEBACK_INSTRS Bit Offset */ -#define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /*!< WRITEBACK_INSTRS Bit Mask */ -#define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /*!< WRITEBACK_INSTRS Bit 0 */ -#define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /*!< WRITEBACK_INSTRS Bit 1 */ -#define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /*!< WRITEBACK_INSTRS Bit 2 */ -#define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /*!< WRITEBACK_INSTRS Bit 3 */ -#define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /*!< only non-writeback addressing modes present, except that */ - /* LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */ -#define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */ -/* SCB_ISAR4[BARRIER_INSTRS] Bits */ -#define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /*!< BARRIER_INSTRS Bit Offset */ -#define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /*!< BARRIER_INSTRS Bit Mask */ -#define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /*!< BARRIER_INSTRS Bit 0 */ -#define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /*!< BARRIER_INSTRS Bit 1 */ -#define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /*!< BARRIER_INSTRS Bit 2 */ -#define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /*!< BARRIER_INSTRS Bit 3 */ -#define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /*!< no barrier instructions supported */ -#define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /*!< adds DMB, DSB, ISB barrier instructions */ -/* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /*!< no additional support */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */ -/* SCB_ISAR4[PSR_M_INSTRS] Bits */ -#define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /*!< PSR_M_INSTRS Bit Offset */ -#define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /*!< PSR_M_INSTRS Bit Mask */ -#define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /*!< PSR_M_INSTRS Bit 0 */ -#define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /*!< PSR_M_INSTRS Bit 1 */ -#define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /*!< PSR_M_INSTRS Bit 2 */ -#define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /*!< PSR_M_INSTRS Bit 3 */ -#define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /*!< instructions not present */ -#define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */ -/* SCB_CPACR[CP11] Bits */ -#define SCB_CPACR_CP11_OFS (22) /*!< CP11 Bit Offset */ -#define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /*!< CP11 Bit Mask */ -/* SCB_CPACR[CP10] Bits */ -#define SCB_CPACR_CP10_OFS (20) /*!< CP10 Bit Offset */ -#define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /*!< CP10 Bit Mask */ -/* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */ -#define SCB_SHPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define SCB_SHPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */ -#define SCB_SHPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define SCB_SHPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */ -#define SCB_SHPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define SCB_SHPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */ -#define SCB_SHPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define SCB_SHPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */ -#define SCB_SHPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define SCB_SHPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */ -#define SCB_SHPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define SCB_SHPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */ -#define SCB_SHPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define SCB_SHPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */ -#define SCB_SHPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define SCB_SHPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */ -#define SCB_SHPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define SCB_SHPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */ -#define SCB_SHPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define SCB_SHPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */ -#define SCB_SHPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define SCB_SHPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */ -#define SCB_SHPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define SCB_SHPR3_PRI_15_M ((uint32_t)0xff000000) /* */ - -/* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */ -#define SCB_CFSR_IACCVIOL_OFS ( 0) /*!< IACCVIOL Offset */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /* */ -/* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */ -#define SCB_CFSR_DACCVIOL_OFS ( 1) /*!< DACCVIOL Offset */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /* */ -/* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */ -#define SCB_CFSR_MUNSTKERR_OFS ( 3) /*!< MUNSTKERR Offset */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /* */ -/* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */ -#define SCB_CFSR_MSTKERR_OFS ( 4) /*!< MSTKERR Offset */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /* */ -/* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */ -#define SCB_CFSR_MMARVALID_OFS ( 7) /*!< MMARVALID Offset */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /* */ -/* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */ -#define SCB_CFSR_IBUSERR_OFS ( 8) /*!< IBUSERR Offset */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /* */ -/* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */ -#define SCB_CFSR_PRECISERR_OFS ( 9) /*!< PRECISERR Offset */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /* */ -/* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */ -#define SCB_CFSR_IMPRECISERR_OFS (10) /*!< IMPRECISERR Offset */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /* */ -/* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */ -#define SCB_CFSR_UNSTKERR_OFS (11) /*!< UNSTKERR Offset */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /* */ -/* SCB_CFSR[SCB_CFSR_STKERR] Bits */ -#define SCB_CFSR_STKERR_OFS (12) /*!< STKERR Offset */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /* */ -/* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */ -#define SCB_CFSR_BFARVALID_OFS (15) /*!< BFARVALID Offset */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /* */ -/* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */ -#define SCB_CFSR_UNDEFINSTR_OFS (16) /*!< UNDEFINSTR Offset */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /* */ -/* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */ -#define SCB_CFSR_INVSTATE_OFS (17) /*!< INVSTATE Offset */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /* */ -/* SCB_CFSR[SCB_CFSR_INVPC] Bits */ -#define SCB_CFSR_INVPC_OFS (18) /*!< INVPC Offset */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /* */ -/* SCB_CFSR[SCB_CFSR_NOCP] Bits */ -#define SCB_CFSR_NOCP_OFS (19) /*!< NOCP Offset */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /* */ -/* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */ -#define SCB_CFSR_UNALIGNED_OFS (24) /*!< UNALIGNED Offset */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /* */ -/* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */ -#define SCB_CFSR_DIVBYZERO_OFS (25) /*!< DIVBYZERO Offset */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /* */ -/* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */ -#define SCB_CFSR_MLSPERR_OFS ( 5) /*!< MLSPERR Offset */ -#define SCB_CFSR_MLSPERR ((uint32_t)0x00000020) /* */ -/* SCB_CFSR[SCB_CFSR_LSPERR] Bits */ -#define SCB_CFSR_LSPERR_OFS (13) /*!< LSPERR Offset */ -#define SCB_CFSR_LSPERR ((uint32_t)0x00002000) /* */ - - -/****************************************************************************** -* SCNSCB Bits -******************************************************************************/ - - -/****************************************************************************** -* SYSCTL_A Bits -******************************************************************************/ -/* SYSCTL_A_REBOOT_CTL[REBOOT] Bits */ -#define SYSCTL_A_REBOOT_CTL_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define SYSCTL_A_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /*!< Write 1 initiates a Reboot of the device */ -/* SYSCTL_A_REBOOT_CTL[WKEY] Bits */ -#define SYSCTL_A_REBOOT_CTL_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_A_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -/* SYSCTL_A_NMI_CTLSTAT[CS_SRC] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_CS_SRC_OFS ( 0) /*!< CS_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /*!< CS interrupt as a source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PSS_SRC] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /*!< PSS_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /*!< PSS interrupt as a source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PCM_SRC] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /*!< PCM_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /*!< PCM interrupt as a source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PIN_SRC] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /*!< PIN_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008) -/* SYSCTL_A_NMI_CTLSTAT[CS_FLG] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_CS_FLG_OFS (16) /*!< CS_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /*!< CS interrupt was the source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PSS_FLG] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_FLG_OFS (17) /*!< PSS_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /*!< PSS interrupt was the source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PCM_FLG] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_FLG_OFS (18) /*!< PCM_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /*!< PCM interrupt was the source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PIN_FLG] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_FLG_OFS (19) /*!< PIN_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /*!< RSTn/NMI pin was the source of NMI */ -/* SYSCTL_A_WDTRESET_CTL[TIMEOUT] Bits */ -#define SYSCTL_A_WDTRESET_CTL_TIMEOUT_OFS ( 0) /*!< TIMEOUT Bit Offset */ -#define SYSCTL_A_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /*!< WDT timeout reset type */ -/* SYSCTL_A_WDTRESET_CTL[VIOLATION] Bits */ -#define SYSCTL_A_WDTRESET_CTL_VIOLATION_OFS ( 1) /*!< VIOLATION Bit Offset */ -#define SYSCTL_A_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /*!< WDT password violation reset type */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T16_0] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /*!< HALT_T16_0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T16_1] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /*!< HALT_T16_1 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T16_2] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /*!< HALT_T16_2 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T16_3] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /*!< HALT_T16_3 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T32_0] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /*!< HALT_T32_0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUA0] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /*!< HALT_eUA0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUA1] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /*!< HALT_eUA1 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUA2] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /*!< HALT_eUA2 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUA3] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /*!< HALT_eUA3 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUB0] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /*!< HALT_eUB0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUB1] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB1_OFS (10) /*!< HALT_eUB1 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUB2] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB2_OFS (11) /*!< HALT_eUB2 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUB3] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB3_OFS (12) /*!< HALT_eUB3 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_ADC] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_ADC_OFS (13) /*!< HALT_ADC Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_WDT] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_WDT_OFS (14) /*!< HALT_WDT Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_DMA] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_DMA_OFS (15) /*!< HALT_DMA Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_LCD] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_LCD_OFS (16) /*!< HALT_LCD Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_LCD ((uint32_t)0x00010000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_DIO_GLTFLT_CTL[GLTCH_EN] Bits */ -#define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /*!< GLTCH_EN Bit Offset */ -#define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /*!< Glitch filter enable */ -/* SYSCTL_A_SECDATA_UNLOCK[UNLKEY] Bits */ -#define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK0_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN_OFS ( 0) /*!< BNK0_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank0 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK1_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN_OFS ( 1) /*!< BNK1_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank1 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK2_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN_OFS ( 2) /*!< BNK2_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank2 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK3_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN_OFS ( 3) /*!< BNK3_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank3 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK4_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN_OFS ( 4) /*!< BNK4_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank4 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK5_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN_OFS ( 5) /*!< BNK5_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank5 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK6_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN_OFS ( 6) /*!< BNK6_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank6 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK7_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN_OFS ( 7) /*!< BNK7_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank7 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK8_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN_OFS ( 8) /*!< BNK8_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank8 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK9_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN_OFS ( 9) /*!< BNK9_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank9 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK10_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN_OFS (10) /*!< BNK10_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank10 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK11_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN_OFS (11) /*!< BNK11_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank11 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK12_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN_OFS (12) /*!< BNK12_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank12 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK13_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN_OFS (13) /*!< BNK13_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank13 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK14_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN_OFS (14) /*!< BNK14_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank14 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK15_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN_OFS (15) /*!< BNK15_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank15 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK16_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN_OFS (16) /*!< BNK16_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank16 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK17_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN_OFS (17) /*!< BNK17_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank17 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK18_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN_OFS (18) /*!< BNK18_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank18 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK19_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN_OFS (19) /*!< BNK19_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank19 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK20_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN_OFS (20) /*!< BNK20_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank20 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK21_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN_OFS (21) /*!< BNK21_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank21 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK22_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN_OFS (22) /*!< BNK22_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank22 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK23_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN_OFS (23) /*!< BNK23_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank23 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK24_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN_OFS (24) /*!< BNK24_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank24 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK25_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN_OFS (25) /*!< BNK25_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank25 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK26_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN_OFS (26) /*!< BNK26_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank26 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK27_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN_OFS (27) /*!< BNK27_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank27 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK28_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN_OFS (28) /*!< BNK28_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank28 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK29_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN_OFS (29) /*!< BNK29_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank29 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK30_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN_OFS (30) /*!< BNK30_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank30 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK31_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN_OFS (31) /*!< BNK31_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank31 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK32_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN_OFS ( 0) /*!< BNK32_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank32 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK33_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN_OFS ( 1) /*!< BNK33_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank33 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK34_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN_OFS ( 2) /*!< BNK34_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank34 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK35_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN_OFS ( 3) /*!< BNK35_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank35 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK36_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN_OFS ( 4) /*!< BNK36_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank36 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK37_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN_OFS ( 5) /*!< BNK37_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank37 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK38_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN_OFS ( 6) /*!< BNK38_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank38 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK39_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN_OFS ( 7) /*!< BNK39_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank39 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK40_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN_OFS ( 8) /*!< BNK40_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank40 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK41_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN_OFS ( 9) /*!< BNK41_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank41 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK42_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN_OFS (10) /*!< BNK42_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank42 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK43_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN_OFS (11) /*!< BNK43_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank43 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK44_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN_OFS (12) /*!< BNK44_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank44 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK45_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN_OFS (13) /*!< BNK45_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank45 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK46_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN_OFS (14) /*!< BNK46_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank46 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK47_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN_OFS (15) /*!< BNK47_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank47 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK48_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN_OFS (16) /*!< BNK48_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank48 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK49_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN_OFS (17) /*!< BNK49_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank49 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK50_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN_OFS (18) /*!< BNK50_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank50 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK51_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN_OFS (19) /*!< BNK51_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank51 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK52_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN_OFS (20) /*!< BNK52_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank52 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK53_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN_OFS (21) /*!< BNK53_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank53 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK54_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN_OFS (22) /*!< BNK54_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank54 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK55_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN_OFS (23) /*!< BNK55_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank55 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK56_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN_OFS (24) /*!< BNK56_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank56 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK57_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN_OFS (25) /*!< BNK57_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank57 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK58_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN_OFS (26) /*!< BNK58_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank58 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK59_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN_OFS (27) /*!< BNK59_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank59 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK60_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN_OFS (28) /*!< BNK60_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank60 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK61_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN_OFS (29) /*!< BNK61_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank61 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK62_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN_OFS (30) /*!< BNK62_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank62 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK63_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN_OFS (31) /*!< BNK63_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank63 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK64_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN_OFS ( 0) /*!< BNK64_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank64 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK65_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN_OFS ( 1) /*!< BNK65_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank65 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK66_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN_OFS ( 2) /*!< BNK66_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank66 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK67_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN_OFS ( 3) /*!< BNK67_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank67 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK68_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN_OFS ( 4) /*!< BNK68_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank68 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK69_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN_OFS ( 5) /*!< BNK69_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank69 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK70_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN_OFS ( 6) /*!< BNK70_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank70 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK71_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN_OFS ( 7) /*!< BNK71_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank71 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK72_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN_OFS ( 8) /*!< BNK72_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank72 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK73_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN_OFS ( 9) /*!< BNK73_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank73 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK74_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN_OFS (10) /*!< BNK74_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank74 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK75_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN_OFS (11) /*!< BNK75_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank75 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK76_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN_OFS (12) /*!< BNK76_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank76 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK77_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN_OFS (13) /*!< BNK77_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank77 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK78_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN_OFS (14) /*!< BNK78_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank78 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK79_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN_OFS (15) /*!< BNK79_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank79 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK80_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN_OFS (16) /*!< BNK80_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank80 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK81_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN_OFS (17) /*!< BNK81_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank81 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK82_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN_OFS (18) /*!< BNK82_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank82 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK83_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN_OFS (19) /*!< BNK83_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank83 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK84_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN_OFS (20) /*!< BNK84_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank84 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK85_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN_OFS (21) /*!< BNK85_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank85 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK86_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN_OFS (22) /*!< BNK86_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank86 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK87_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN_OFS (23) /*!< BNK87_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank87 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK88_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN_OFS (24) /*!< BNK88_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank88 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK89_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN_OFS (25) /*!< BNK89_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank89 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK90_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN_OFS (26) /*!< BNK90_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank90 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK91_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN_OFS (27) /*!< BNK91_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank91 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK92_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN_OFS (28) /*!< BNK92_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank92 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK93_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN_OFS (29) /*!< BNK93_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank93 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK94_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN_OFS (30) /*!< BNK94_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank94 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK95_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN_OFS (31) /*!< BNK95_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank95 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK96_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN_OFS ( 0) /*!< BNK96_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank96 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK97_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN_OFS ( 1) /*!< BNK97_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank97 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK98_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN_OFS ( 2) /*!< BNK98_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank98 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK99_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN_OFS ( 3) /*!< BNK99_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank99 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK100_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN_OFS ( 4) /*!< BNK100_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank100 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK101_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN_OFS ( 5) /*!< BNK101_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank101 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK102_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN_OFS ( 6) /*!< BNK102_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank102 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK103_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN_OFS ( 7) /*!< BNK103_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank103 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK104_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN_OFS ( 8) /*!< BNK104_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank104 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK105_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN_OFS ( 9) /*!< BNK105_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank105 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK106_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN_OFS (10) /*!< BNK106_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank106 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK107_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN_OFS (11) /*!< BNK107_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank107 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK108_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN_OFS (12) /*!< BNK108_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank108 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK109_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN_OFS (13) /*!< BNK109_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank109 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK110_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN_OFS (14) /*!< BNK110_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank110 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK111_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN_OFS (15) /*!< BNK111_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank111 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK112_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN_OFS (16) /*!< BNK112_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank112 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK113_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN_OFS (17) /*!< BNK113_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank113 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK114_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN_OFS (18) /*!< BNK114_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank114 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK115_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN_OFS (19) /*!< BNK115_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank115 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK116_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN_OFS (20) /*!< BNK116_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank116 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK117_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN_OFS (21) /*!< BNK117_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank117 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK118_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN_OFS (22) /*!< BNK118_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank118 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK119_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN_OFS (23) /*!< BNK119_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank119 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK120_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN_OFS (24) /*!< BNK120_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank120 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK121_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN_OFS (25) /*!< BNK121_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank121 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK122_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN_OFS (26) /*!< BNK122_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank122 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK123_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN_OFS (27) /*!< BNK123_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank123 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK124_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN_OFS (28) /*!< BNK124_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank124 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK125_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN_OFS (29) /*!< BNK125_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank125 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK126_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN_OFS (30) /*!< BNK126_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank126 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK127_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN_OFS (31) /*!< BNK127_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank127 of the SRAM */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK0_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN_OFS ( 0) /*!< BLK0_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN ((uint32_t)0x00000001) /*!< Block0 is always retained in LPM3, LPM4 and LPM3.5 modes of operation */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK1_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN_OFS ( 1) /*!< BLK1_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN ((uint32_t)0x00000002) /*!< When 1, Block1 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK2_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN_OFS ( 2) /*!< BLK2_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN ((uint32_t)0x00000004) /*!< When 1, Block2 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK3_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN_OFS ( 3) /*!< BLK3_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN ((uint32_t)0x00000008) /*!< When 1, Block3 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK4_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN_OFS ( 4) /*!< BLK4_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN ((uint32_t)0x00000010) /*!< When 1, Block4 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK5_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN_OFS ( 5) /*!< BLK5_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN ((uint32_t)0x00000020) /*!< When 1, Block5 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK6_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN_OFS ( 6) /*!< BLK6_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN ((uint32_t)0x00000040) /*!< When 1, Block6 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK7_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN_OFS ( 7) /*!< BLK7_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN ((uint32_t)0x00000080) /*!< When 1, Block7 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK8_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN_OFS ( 8) /*!< BLK8_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN ((uint32_t)0x00000100) /*!< When 1, Block8 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK9_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN_OFS ( 9) /*!< BLK9_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN ((uint32_t)0x00000200) /*!< When 1, Block9 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK10_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN_OFS (10) /*!< BLK10_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN ((uint32_t)0x00000400) /*!< When 1, Block10 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK11_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN_OFS (11) /*!< BLK11_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN ((uint32_t)0x00000800) /*!< When 1, Block11 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK12_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN_OFS (12) /*!< BLK12_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN ((uint32_t)0x00001000) /*!< When 1, Block12 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK13_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN_OFS (13) /*!< BLK13_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN ((uint32_t)0x00002000) /*!< When 1, Block13 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK14_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN_OFS (14) /*!< BLK14_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN ((uint32_t)0x00004000) /*!< When 1, Block14 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK15_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN_OFS (15) /*!< BLK15_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN ((uint32_t)0x00008000) /*!< When 1, Block15 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK16_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN_OFS (16) /*!< BLK16_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN ((uint32_t)0x00010000) /*!< When 1, Block16 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK17_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN_OFS (17) /*!< BLK17_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN ((uint32_t)0x00020000) /*!< When 1, Block17 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK18_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN_OFS (18) /*!< BLK18_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN ((uint32_t)0x00040000) /*!< When 1, Block18 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK19_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN_OFS (19) /*!< BLK19_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN ((uint32_t)0x00080000) /*!< When 1, Block19 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK20_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN_OFS (20) /*!< BLK20_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN ((uint32_t)0x00100000) /*!< When 1, Block20 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK21_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN_OFS (21) /*!< BLK21_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN ((uint32_t)0x00200000) /*!< When 1, Block21 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK22_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN_OFS (22) /*!< BLK22_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN ((uint32_t)0x00400000) /*!< When 1, Block22 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK23_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN_OFS (23) /*!< BLK23_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN ((uint32_t)0x00800000) /*!< When 1, Block23 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK24_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN_OFS (24) /*!< BLK24_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN ((uint32_t)0x01000000) /*!< When 1, Block24 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK25_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN_OFS (25) /*!< BLK25_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN ((uint32_t)0x02000000) /*!< When 1, Block25 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK26_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN_OFS (26) /*!< BLK26_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN ((uint32_t)0x04000000) /*!< When 1, Block26 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK27_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN_OFS (27) /*!< BLK27_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN ((uint32_t)0x08000000) /*!< When 1, Block27 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK28_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN_OFS (28) /*!< BLK28_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN ((uint32_t)0x10000000) /*!< When 1, Block28 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK29_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN_OFS (29) /*!< BLK29_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN ((uint32_t)0x20000000) /*!< When 1, Block29 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK30_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN_OFS (30) /*!< BLK30_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN ((uint32_t)0x40000000) /*!< When 1, Block30 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK31_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN_OFS (31) /*!< BLK31_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN ((uint32_t)0x80000000) /*!< When 1, Block31 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK32_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN_OFS ( 0) /*!< BLK32_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN ((uint32_t)0x00000001) /*!< When 1, Block32 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK33_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN_OFS ( 1) /*!< BLK33_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN ((uint32_t)0x00000002) /*!< When 1, Block33 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK34_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN_OFS ( 2) /*!< BLK34_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN ((uint32_t)0x00000004) /*!< When 1, Block34 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK35_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN_OFS ( 3) /*!< BLK35_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN ((uint32_t)0x00000008) /*!< When 1, Block35 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK36_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN_OFS ( 4) /*!< BLK36_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN ((uint32_t)0x00000010) /*!< When 1, Block36 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK37_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN_OFS ( 5) /*!< BLK37_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN ((uint32_t)0x00000020) /*!< When 1, Block37 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK38_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN_OFS ( 6) /*!< BLK38_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN ((uint32_t)0x00000040) /*!< When 1, Block38 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK39_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN_OFS ( 7) /*!< BLK39_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN ((uint32_t)0x00000080) /*!< When 1, Block39 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK40_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN_OFS ( 8) /*!< BLK40_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN ((uint32_t)0x00000100) /*!< When 1, Block40 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK41_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN_OFS ( 9) /*!< BLK41_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN ((uint32_t)0x00000200) /*!< When 1, Block41 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK42_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN_OFS (10) /*!< BLK42_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN ((uint32_t)0x00000400) /*!< When 1, Block42 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK43_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN_OFS (11) /*!< BLK43_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN ((uint32_t)0x00000800) /*!< When 1, Block43 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK44_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN_OFS (12) /*!< BLK44_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN ((uint32_t)0x00001000) /*!< When 1, Block44 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK45_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN_OFS (13) /*!< BLK45_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN ((uint32_t)0x00002000) /*!< When 1, Block45 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK46_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN_OFS (14) /*!< BLK46_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN ((uint32_t)0x00004000) /*!< When 1, Block46 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK47_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN_OFS (15) /*!< BLK47_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN ((uint32_t)0x00008000) /*!< When 1, Block47 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK48_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN_OFS (16) /*!< BLK48_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN ((uint32_t)0x00010000) /*!< When 1, Block48 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK49_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN_OFS (17) /*!< BLK49_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN ((uint32_t)0x00020000) /*!< When 1, Block49 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK50_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN_OFS (18) /*!< BLK50_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN ((uint32_t)0x00040000) /*!< When 1, Block50 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK51_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN_OFS (19) /*!< BLK51_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN ((uint32_t)0x00080000) /*!< When 1, Block51 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK52_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN_OFS (20) /*!< BLK52_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN ((uint32_t)0x00100000) /*!< When 1, Block52 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK53_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN_OFS (21) /*!< BLK53_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN ((uint32_t)0x00200000) /*!< When 1, Block53 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK54_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN_OFS (22) /*!< BLK54_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN ((uint32_t)0x00400000) /*!< When 1, Block54 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK55_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN_OFS (23) /*!< BLK55_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN ((uint32_t)0x00800000) /*!< When 1, Block55 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK56_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN_OFS (24) /*!< BLK56_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN ((uint32_t)0x01000000) /*!< When 1, Block56 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK57_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN_OFS (25) /*!< BLK57_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN ((uint32_t)0x02000000) /*!< When 1, Block57 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK58_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN_OFS (26) /*!< BLK58_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN ((uint32_t)0x04000000) /*!< When 1, Block58 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK59_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN_OFS (27) /*!< BLK59_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN ((uint32_t)0x08000000) /*!< When 1, Block59 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK60_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN_OFS (28) /*!< BLK60_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN ((uint32_t)0x10000000) /*!< When 1, Block60 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK61_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN_OFS (29) /*!< BLK61_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN ((uint32_t)0x20000000) /*!< When 1, Block61 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK62_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN_OFS (30) /*!< BLK62_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN ((uint32_t)0x40000000) /*!< When 1, Block62 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK63_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN_OFS (31) /*!< BLK63_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN ((uint32_t)0x80000000) /*!< When 1, Block63 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK64_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN_OFS ( 0) /*!< BLK64_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN ((uint32_t)0x00000001) /*!< When 1, Block64 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK65_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN_OFS ( 1) /*!< BLK65_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN ((uint32_t)0x00000002) /*!< When 1, Block65 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK66_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN_OFS ( 2) /*!< BLK66_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN ((uint32_t)0x00000004) /*!< When 1, Block66 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK67_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN_OFS ( 3) /*!< BLK67_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN ((uint32_t)0x00000008) /*!< When 1, Block67 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK68_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN_OFS ( 4) /*!< BLK68_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN ((uint32_t)0x00000010) /*!< When 1, Block68 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK69_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN_OFS ( 5) /*!< BLK69_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN ((uint32_t)0x00000020) /*!< When 1, Block69 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK70_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN_OFS ( 6) /*!< BLK70_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN ((uint32_t)0x00000040) /*!< When 1, Block70 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK71_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN_OFS ( 7) /*!< BLK71_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN ((uint32_t)0x00000080) /*!< When 1, Block71 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK72_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN_OFS ( 8) /*!< BLK72_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN ((uint32_t)0x00000100) /*!< When 1, Block72 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK73_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN_OFS ( 9) /*!< BLK73_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN ((uint32_t)0x00000200) /*!< When 1, Block73 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK74_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN_OFS (10) /*!< BLK74_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN ((uint32_t)0x00000400) /*!< When 1, Block74 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK75_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN_OFS (11) /*!< BLK75_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN ((uint32_t)0x00000800) /*!< When 1, Block75 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK76_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN_OFS (12) /*!< BLK76_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN ((uint32_t)0x00001000) /*!< When 1, Block76 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK77_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN_OFS (13) /*!< BLK77_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN ((uint32_t)0x00002000) /*!< When 1, Block77 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK78_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN_OFS (14) /*!< BLK78_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN ((uint32_t)0x00004000) /*!< When 1, Block78 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK79_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN_OFS (15) /*!< BLK79_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN ((uint32_t)0x00008000) /*!< When 1, Block79 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK80_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN_OFS (16) /*!< BLK80_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN ((uint32_t)0x00010000) /*!< When 1, Block80 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK81_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN_OFS (17) /*!< BLK81_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN ((uint32_t)0x00020000) /*!< When 1, Block81 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK82_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN_OFS (18) /*!< BLK82_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN ((uint32_t)0x00040000) /*!< When 1, Block82 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK83_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN_OFS (19) /*!< BLK83_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN ((uint32_t)0x00080000) /*!< When 1, Block83 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK84_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN_OFS (20) /*!< BLK84_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN ((uint32_t)0x00100000) /*!< When 1, Block84 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK85_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN_OFS (21) /*!< BLK85_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN ((uint32_t)0x00200000) /*!< When 1, Block85 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK86_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN_OFS (22) /*!< BLK86_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN ((uint32_t)0x00400000) /*!< When 1, Block86 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK87_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN_OFS (23) /*!< BLK87_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN ((uint32_t)0x00800000) /*!< When 1, Block87 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK88_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN_OFS (24) /*!< BLK88_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN ((uint32_t)0x01000000) /*!< When 1, Block88 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK89_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN_OFS (25) /*!< BLK89_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN ((uint32_t)0x02000000) /*!< When 1, Block89 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK90_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN_OFS (26) /*!< BLK90_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN ((uint32_t)0x04000000) /*!< When 1, Block90 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK91_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN_OFS (27) /*!< BLK91_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN ((uint32_t)0x08000000) /*!< When 1, Block91 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK92_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN_OFS (28) /*!< BLK92_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN ((uint32_t)0x10000000) /*!< When 1, Block92 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK93_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN_OFS (29) /*!< BLK93_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN ((uint32_t)0x20000000) /*!< When 1, Block93 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK94_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN_OFS (30) /*!< BLK94_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN ((uint32_t)0x40000000) /*!< When 1, Block94 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK95_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN_OFS (31) /*!< BLK95_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN ((uint32_t)0x80000000) /*!< When 1, Block95 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK96_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN_OFS ( 0) /*!< BLK96_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN ((uint32_t)0x00000001) /*!< When 1, Block96 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK97_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN_OFS ( 1) /*!< BLK97_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN ((uint32_t)0x00000002) /*!< When 1, Block97 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK98_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN_OFS ( 2) /*!< BLK98_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN ((uint32_t)0x00000004) /*!< When 1, Block98 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK99_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN_OFS ( 3) /*!< BLK99_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN ((uint32_t)0x00000008) /*!< When 1, Block99 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK100_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN_OFS ( 4) /*!< BLK100_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN ((uint32_t)0x00000010) /*!< When 1, Block100 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK101_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN_OFS ( 5) /*!< BLK101_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN ((uint32_t)0x00000020) /*!< When 1, Block101 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK102_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN_OFS ( 6) /*!< BLK102_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN ((uint32_t)0x00000040) /*!< When 1, Block102 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK103_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN_OFS ( 7) /*!< BLK103_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN ((uint32_t)0x00000080) /*!< When 1, Block103 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK104_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN_OFS ( 8) /*!< BLK104_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN ((uint32_t)0x00000100) /*!< When 1, Block104 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK105_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN_OFS ( 9) /*!< BLK105_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN ((uint32_t)0x00000200) /*!< When 1, Block105 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK106_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN_OFS (10) /*!< BLK106_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN ((uint32_t)0x00000400) /*!< When 1, Block106 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK107_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN_OFS (11) /*!< BLK107_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN ((uint32_t)0x00000800) /*!< When 1, Block107 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK108_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN_OFS (12) /*!< BLK108_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN ((uint32_t)0x00001000) /*!< When 1, Block108 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK109_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN_OFS (13) /*!< BLK109_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN ((uint32_t)0x00002000) /*!< When 1, Block109 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK110_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN_OFS (14) /*!< BLK110_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN ((uint32_t)0x00004000) /*!< When 1, Block110 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK111_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN_OFS (15) /*!< BLK111_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN ((uint32_t)0x00008000) /*!< When 1, Block111 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK112_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN_OFS (16) /*!< BLK112_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN ((uint32_t)0x00010000) /*!< When 1, Block112 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK113_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN_OFS (17) /*!< BLK113_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN ((uint32_t)0x00020000) /*!< When 1, Block113 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK114_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN_OFS (18) /*!< BLK114_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN ((uint32_t)0x00040000) /*!< When 1, Block114 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK115_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN_OFS (19) /*!< BLK115_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN ((uint32_t)0x00080000) /*!< When 1, Block115 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK116_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN_OFS (20) /*!< BLK116_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN ((uint32_t)0x00100000) /*!< When 1, Block116 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK117_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN_OFS (21) /*!< BLK117_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN ((uint32_t)0x00200000) /*!< When 1, Block117 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK118_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN_OFS (22) /*!< BLK118_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN ((uint32_t)0x00400000) /*!< When 1, Block118 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK119_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN_OFS (23) /*!< BLK119_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN ((uint32_t)0x00800000) /*!< When 1, Block119 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK120_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN_OFS (24) /*!< BLK120_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN ((uint32_t)0x01000000) /*!< When 1, Block120 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK121_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN_OFS (25) /*!< BLK121_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN ((uint32_t)0x02000000) /*!< When 1, Block121 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK122_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN_OFS (26) /*!< BLK122_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN ((uint32_t)0x04000000) /*!< When 1, Block122 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK123_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN_OFS (27) /*!< BLK123_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN ((uint32_t)0x08000000) /*!< When 1, Block123 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK124_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN_OFS (28) /*!< BLK124_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN ((uint32_t)0x10000000) /*!< When 1, Block124 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK125_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN_OFS (29) /*!< BLK125_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN ((uint32_t)0x20000000) /*!< When 1, Block125 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK126_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN_OFS (30) /*!< BLK126_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN ((uint32_t)0x40000000) /*!< When 1, Block126 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK127_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN_OFS (31) /*!< BLK127_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN ((uint32_t)0x80000000) /*!< When 1, Block127 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_STAT[BNKEN_RDY] Bits */ -#define SYSCTL_A_SRAM_STAT_BNKEN_RDY_OFS ( 0) /*!< BNKEN_RDY Bit Offset */ -#define SYSCTL_A_SRAM_STAT_BNKEN_RDY ((uint32_t)0x00000001) /*!< When 1, indicates SRAM is ready for access and banks can be */ - /* enabled/disabled. */ -/* SYSCTL_A_SRAM_STAT[BLKRET_RDY] Bits */ -#define SYSCTL_A_SRAM_STAT_BLKRET_RDY_OFS ( 1) /*!< BLKRET_RDY Bit Offset */ -#define SYSCTL_A_SRAM_STAT_BLKRET_RDY ((uint32_t)0x00000002) /*!< When 1, indicates SRAM is ready for access and blocks can be */ - /* enabled/disabled for retention. */ -/* SYSCTL_A_MASTER_UNLOCK[UNLKEY] Bits */ -#define SYSCTL_A_MASTER_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_A_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -/* SYSCTL_A_RESET_REQ[POR] Bits */ -#define SYSCTL_A_RESET_REQ_POR_OFS ( 0) /*!< POR Bit Offset */ -#define SYSCTL_A_RESET_REQ_POR ((uint32_t)0x00000001) /*!< Generate POR */ -/* SYSCTL_A_RESET_REQ[REBOOT] Bits */ -#define SYSCTL_A_RESET_REQ_REBOOT_OFS ( 1) /*!< REBOOT Bit Offset */ -#define SYSCTL_A_RESET_REQ_REBOOT ((uint32_t)0x00000002) /*!< Generate Reboot_Reset */ -/* SYSCTL_A_RESET_REQ[WKEY] Bits */ -#define SYSCTL_A_RESET_REQ_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_A_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -/* SYSCTL_A_RESET_STATOVER[SOFT] Bits */ -#define SYSCTL_A_RESET_STATOVER_SOFT_OFS ( 0) /*!< SOFT Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /*!< Indicates if SOFT Reset is active */ -/* SYSCTL_A_RESET_STATOVER[HARD] Bits */ -#define SYSCTL_A_RESET_STATOVER_HARD_OFS ( 1) /*!< HARD Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_HARD ((uint32_t)0x00000002) /*!< Indicates if HARD Reset is active */ -/* SYSCTL_A_RESET_STATOVER[REBOOT] Bits */ -#define SYSCTL_A_RESET_STATOVER_REBOOT_OFS ( 2) /*!< REBOOT Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /*!< Indicates if Reboot Reset is active */ -/* SYSCTL_A_RESET_STATOVER[SOFT_OVER] Bits */ -#define SYSCTL_A_RESET_STATOVER_SOFT_OVER_OFS ( 8) /*!< SOFT_OVER Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /*!< SOFT_Reset overwrite request */ -/* SYSCTL_A_RESET_STATOVER[HARD_OVER] Bits */ -#define SYSCTL_A_RESET_STATOVER_HARD_OVER_OFS ( 9) /*!< HARD_OVER Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /*!< HARD_Reset overwrite request */ -/* SYSCTL_A_RESET_STATOVER[RBT_OVER] Bits */ -#define SYSCTL_A_RESET_STATOVER_RBT_OVER_OFS (10) /*!< RBT_OVER Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /*!< Reboot Reset overwrite request */ -/* Pre-defined bitfield values */ -#define SYSCTL_A_CSYS_MASTER_UNLOCK_UNLKEY_VAL ((uint32_t)0x0000695A) /*!< Unlock key value which when written, determines if accesses to other CPU_SYS register */ -#define SYSCTL_A_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ -#define SYSCTL_A_BOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ -#define SYSCTL_A_ETW_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ -#define SYSCTL_A_SECDATA_UNLOCK_KEY_VAL ((uint32_t)0x0000695A) /*!< Unlock Key value, which requests for secure data region to be unlocked for data access */ - - -/****************************************************************************** -* SYSTICK Bits -******************************************************************************/ - -/****************************************************************************** -* Timer32 Bits -******************************************************************************/ -/* TIMER32_CONTROL[ONESHOT] Bits */ -#define TIMER32_CONTROL_ONESHOT_OFS ( 0) /*!< ONESHOT Bit Offset */ -#define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /*!< Selects one-shot or wrapping counter mode */ -/* TIMER32_CONTROL[SIZE] Bits */ -#define TIMER32_CONTROL_SIZE_OFS ( 1) /*!< SIZE Bit Offset */ -#define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /*!< Selects 16 or 32 bit counter operation */ -/* TIMER32_CONTROL[PRESCALE] Bits */ -#define TIMER32_CONTROL_PRESCALE_OFS ( 2) /*!< PRESCALE Bit Offset */ -#define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /*!< PRESCALE Bit Mask */ -#define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /*!< PRESCALE Bit 0 */ -#define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /*!< PRESCALE Bit 1 */ -#define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /*!< 0 stages of prescale, clock is divided by 1 */ -#define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /*!< 4 stages of prescale, clock is divided by 16 */ -#define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /*!< 8 stages of prescale, clock is divided by 256 */ -/* TIMER32_CONTROL[IE] Bits */ -#define TIMER32_CONTROL_IE_OFS ( 5) /*!< IE Bit Offset */ -#define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /*!< Interrupt enable bit */ -/* TIMER32_CONTROL[MODE] Bits */ -#define TIMER32_CONTROL_MODE_OFS ( 6) /*!< MODE Bit Offset */ -#define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /*!< Mode bit */ -/* TIMER32_CONTROL[ENABLE] Bits */ -#define TIMER32_CONTROL_ENABLE_OFS ( 7) /*!< ENABLE Bit Offset */ -#define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080) -/* TIMER32_RIS[RAW_IFG] Bits */ -#define TIMER32_RIS_RAW_IFG_OFS ( 0) /*!< RAW_IFG Bit Offset */ -#define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /*!< Raw interrupt status */ -/* TIMER32_MIS[IFG] Bits */ -#define TIMER32_MIS_IFG_OFS ( 0) /*!< IFG Bit Offset */ -#define TIMER32_MIS_IFG ((uint32_t)0x00000001) /*!< Enabled interrupt status */ - - - -/****************************************************************************** -* TIMER_A Bits -******************************************************************************/ -/* TIMER_A_CTL[IFG] Bits */ -#define TIMER_A_CTL_IFG_OFS ( 0) /*!< TAIFG Bit Offset */ -#define TIMER_A_CTL_IFG ((uint16_t)0x0001) /*!< TimerA interrupt flag */ -/* TIMER_A_CTL[IE] Bits */ -#define TIMER_A_CTL_IE_OFS ( 1) /*!< TAIE Bit Offset */ -#define TIMER_A_CTL_IE ((uint16_t)0x0002) /*!< TimerA interrupt enable */ -/* TIMER_A_CTL[CLR] Bits */ -#define TIMER_A_CTL_CLR_OFS ( 2) /*!< TACLR Bit Offset */ -#define TIMER_A_CTL_CLR ((uint16_t)0x0004) /*!< TimerA clear */ -/* TIMER_A_CTL[MC] Bits */ -#define TIMER_A_CTL_MC_OFS ( 4) /*!< MC Bit Offset */ -#define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /*!< MC Bit Mask */ -#define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /*!< MC Bit 0 */ -#define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /*!< MC Bit 1 */ -#define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -#define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -/* TIMER_A_CTL[ID] Bits */ -#define TIMER_A_CTL_ID_OFS ( 6) /*!< ID Bit Offset */ -#define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /*!< ID Bit Mask */ -#define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /*!< ID Bit 0 */ -#define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /*!< ID Bit 1 */ -#define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /*!< /8 */ -#define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /*!< /8 */ -/* TIMER_A_CTL[SSEL] Bits */ -#define TIMER_A_CTL_SSEL_OFS ( 8) /*!< TASSEL Bit Offset */ -#define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /*!< TASSEL Bit Mask */ -#define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /*!< SSEL Bit 0 */ -#define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /*!< SSEL Bit 1 */ -#define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /*!< INCLK */ -#define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /*!< INCLK */ -/* TIMER_A_CCTLN[CCIFG] Bits */ -#define TIMER_A_CCTLN_CCIFG_OFS ( 0) /*!< CCIFG Bit Offset */ -#define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /*!< Capture/compare interrupt flag */ -/* TIMER_A_CCTLN[COV] Bits */ -#define TIMER_A_CCTLN_COV_OFS ( 1) /*!< COV Bit Offset */ -#define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /*!< Capture overflow */ -/* TIMER_A_CCTLN[OUT] Bits */ -#define TIMER_A_CCTLN_OUT_OFS ( 2) /*!< OUT Bit Offset */ -#define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /*!< Output */ -/* TIMER_A_CCTLN[CCI] Bits */ -#define TIMER_A_CCTLN_CCI_OFS ( 3) /*!< CCI Bit Offset */ -#define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /*!< Capture/compare input */ -/* TIMER_A_CCTLN[CCIE] Bits */ -#define TIMER_A_CCTLN_CCIE_OFS ( 4) /*!< CCIE Bit Offset */ -#define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /*!< Capture/compare interrupt enable */ -/* TIMER_A_CCTLN[OUTMOD] Bits */ -#define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /*!< OUTMOD Bit Offset */ -#define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /*!< OUTMOD Bit Mask */ -#define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /*!< OUTMOD Bit 0 */ -#define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /*!< OUTMOD Bit 1 */ -#define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /*!< OUTMOD Bit 2 */ -#define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /*!< OUT bit value */ -#define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /*!< Set */ -#define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /*!< Toggle/reset */ -#define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /*!< Set/reset */ -#define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /*!< Toggle */ -#define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /*!< Reset */ -#define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /*!< Toggle/set */ -#define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /*!< Reset/set */ -/* TIMER_A_CCTLN[CAP] Bits */ -#define TIMER_A_CCTLN_CAP_OFS ( 8) /*!< CAP Bit Offset */ -#define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /*!< Capture mode */ -/* TIMER_A_CCTLN[SCCI] Bits */ -#define TIMER_A_CCTLN_SCCI_OFS (10) /*!< SCCI Bit Offset */ -#define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /*!< Synchronized capture/compare input */ -/* TIMER_A_CCTLN[SCS] Bits */ -#define TIMER_A_CCTLN_SCS_OFS (11) /*!< SCS Bit Offset */ -#define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /*!< Synchronize capture source */ -/* TIMER_A_CCTLN[CCIS] Bits */ -#define TIMER_A_CCTLN_CCIS_OFS (12) /*!< CCIS Bit Offset */ -#define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /*!< CCIS Bit Mask */ -#define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /*!< CCIS Bit 0 */ -#define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /*!< CCIS Bit 1 */ -#define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /*!< VCC */ -#define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /*!< VCC */ -/* TIMER_A_CCTLN[CM] Bits */ -#define TIMER_A_CCTLN_CM_OFS (14) /*!< CM Bit Offset */ -#define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /*!< CM Bit Mask */ -#define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /*!< CM Bit 0 */ -#define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /*!< CM Bit 1 */ -#define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -#define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -/* TIMER_A_EX0[IDEX] Bits */ -#define TIMER_A_EX0_IDEX_OFS ( 0) /*!< TAIDEX Bit Offset */ -#define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /*!< TAIDEX Bit Mask */ -#define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /*!< IDEX Bit 0 */ -#define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /*!< IDEX Bit 1 */ -#define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /*!< IDEX Bit 2 */ -#define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /*!< Divide by 8 */ -#define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /*!< Divide by 8 */ - -/****************************************************************************** -* TLV Bits -******************************************************************************/ -/****************************************************************************** -* TLV table start and TLV tags * -******************************************************************************/ -#define TLV_START_ADDR (TLV_BASE + 0x0004) /*!< Start Address of the TLV structure */ - -#define TLV_TAG_RESERVED1 1 -#define TLV_TAG_RESERVED2 2 -#define TLV_TAG_CS 3 -#define TLV_TAG_FLASHCTL 4 -#define TLV_TAG_ADC14 5 -#define TLV_TAG_RESERVED6 6 -#define TLV_TAG_RESERVED7 7 -#define TLV_TAG_REF 8 -#define TLV_TAG_RESERVED9 9 -#define TLV_TAG_RESERVED10 10 -#define TLV_TAG_DEVINFO 11 -#define TLV_TAG_DIEREC 12 -#define TLV_TAG_RANDNUM 13 -#define TLV_TAG_RESERVED14 14 -#define TLV_TAG_BSL 15 -#define TLV_TAG_END (0x0BD0E11D) - - -/****************************************************************************** -* TPIU Bits -******************************************************************************/ - - -/****************************************************************************** -* WDT_A Bits -******************************************************************************/ -/* WDT_A_CTL[IS] Bits */ -#define WDT_A_CTL_IS_OFS ( 0) /*!< WDTIS Bit Offset */ -#define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /*!< WDTIS Bit Mask */ -#define WDT_A_CTL_IS0 ((uint16_t)0x0001) /*!< IS Bit 0 */ -#define WDT_A_CTL_IS1 ((uint16_t)0x0002) /*!< IS Bit 1 */ -#define WDT_A_CTL_IS2 ((uint16_t)0x0004) /*!< IS Bit 2 */ -#define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ -#define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ -/* WDT_A_CTL[CNTCL] Bits */ -#define WDT_A_CTL_CNTCL_OFS ( 3) /*!< WDTCNTCL Bit Offset */ -#define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /*!< Watchdog timer counter clear */ -/* WDT_A_CTL[TMSEL] Bits */ -#define WDT_A_CTL_TMSEL_OFS ( 4) /*!< WDTTMSEL Bit Offset */ -#define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /*!< Watchdog timer mode select */ -/* WDT_A_CTL[SSEL] Bits */ -#define WDT_A_CTL_SSEL_OFS ( 5) /*!< WDTSSEL Bit Offset */ -#define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /*!< WDTSSEL Bit Mask */ -#define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /*!< SSEL Bit 0 */ -#define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /*!< SSEL Bit 1 */ -#define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /*!< BCLK */ -#define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /*!< BCLK */ -/* WDT_A_CTL[HOLD] Bits */ -#define WDT_A_CTL_HOLD_OFS ( 7) /*!< WDTHOLD Bit Offset */ -#define WDT_A_CTL_HOLD ((uint16_t)0x0080) /*!< Watchdog timer hold */ -/* WDT_A_CTL[PW] Bits */ -#define WDT_A_CTL_PW_OFS ( 8) /*!< WDTPW Bit Offset */ -#define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /*!< WDTPW Bit Mask */ -/* Pre-defined bitfield values */ -#define WDT_A_CTL_PW ((uint16_t)0x5A00) /*!< WDT Key Value for WDT write access */ - - -/****************************************************************************** -* BSL * -******************************************************************************/ -#define BSL_DEFAULT_PARAM ((uint32_t)0xFC48FFFF) /*!< I2C slave address = 0x48, Interface selection = Auto */ -#define BSL_API_TABLE_ADDR ((uint32_t)0x00202000) /*!< Address of BSL API table */ -#define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR)) - -#define BSL_AUTO_INTERFACE ((uint32_t)0x0000E0000) /*!< Auto detect interface */ -#define BSL_UART_INTERFACE ((uint32_t)0x0000C0000) /*!< UART interface */ -#define BSL_SPI_INTERFACE ((uint32_t)0x0000A0000) /*!< SPI interface */ -#define BSL_I2C_INTERFACE ((uint32_t)0x000080000) /*!< I2C interface */ - -#define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */ - - -/****************************************************************************** -* Mailbox struct legacy definition * -******************************************************************************/ -#define FLASH_MAILBOX_Type FL_BOOTOVER_MAILBOX_Type - -/****************************************************************************** -* Device Unlock Support * -******************************************************************************/ -/* unlock the device by: - * Load SYSCTL_SECDATA_UNLOCK register address into R0 - * Load SYSCTL_SECDATA_UNLOCK unlock key into R1 - * Write the unlock key to the SYSCTL_SECDATA_UNLOCK register - */ -#define UNLOCK_DEVICE\ - __asm(" MOVW.W R0, #0x3040");\ - __asm(" MOVT.W R0, #0xE004");\ - __asm(" MOVW.W R1, #0x695A");\ - __asm(" MOVT.W R1, #0x0000");\ - __asm(" STR R1, [R0]"); - -/****************************************************************************** -* -* The following are values that can be used to choose the command that will be -* run by the boot code. Perform a logical OR of these settings to create your -* general parameter command. -* -******************************************************************************/ -#define COMMAND_FACTORY_RESET ((uint32_t)0x00010000) -#define COMMAND_BSL_CONFIG ((uint32_t)0x00020000) -#define COMMAND_JTAG_SWD_LOCK_SECEN ((uint32_t)0x00080000) -#define COMMAND_SEC_ZONE0_EN ((uint32_t)0x00100000) -#define COMMAND_SEC_ZONE1_EN ((uint32_t)0x00200000) -#define COMMAND_SEC_ZONE2_EN ((uint32_t)0x00400000) -#define COMMAND_SEC_ZONE3_EN ((uint32_t)0x00800000) -#define COMMAND_SEC_ZONE0_UPDATE ((uint32_t)0x01000000) -#define COMMAND_SEC_ZONE1_UPDATE ((uint32_t)0x02000000) -#define COMMAND_SEC_ZONE2_UPDATE ((uint32_t)0x04000000) -#define COMMAND_SEC_ZONE3_UPDATE ((uint32_t)0x08000000) -#define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE ((uint32_t)0x10000000) -#define COMMAND_NONE ((uint32_t)0xFFFFFFFF) - -/****************************************************************************** -* -* The following are values that can be used to configure the BSL. Perform a -* logical OR of these settings to create your BSL parameter. -* -******************************************************************************/ -#define BSL_CONFIG_HW_INVOKE ((uint32_t)0x70000000) - -#define BSL_CONFIG_HW_INVOKE_PORT1 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PORT2 ((uint32_t)0x00000001) -#define BSL_CONFIG_HW_INVOKE_PORT3 ((uint32_t)0x00000002) - -#define BSL_CONFIG_HW_INVOKE_PIN0 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN1 ((uint32_t)0x00000010) -#define BSL_CONFIG_HW_INVOKE_PIN2 ((uint32_t)0x00000020) -#define BSL_CONFIG_HW_INVOKE_PIN3 ((uint32_t)0x00000030) -#define BSL_CONFIG_HW_INVOKE_PIN4 ((uint32_t)0x00000040) -#define BSL_CONFIG_HW_INVOKE_PIN5 ((uint32_t)0x00000050) -#define BSL_CONFIG_HW_INVOKE_PIN6 ((uint32_t)0x00000060) -#define BSL_CONFIG_HW_INVOKE_PIN7 ((uint32_t)0x00000070) - -#define BSL_CONFIG_HW_INVOKE_PIN_LOW ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN_HIGH ((uint32_t)0x00001000) - -#define BSL_CONFIG_INTERFACE_I2C ((uint32_t)0x00008000) -#define BSL_CONFIG_INTERFACE_SPI ((uint32_t)0x0000A000) -#define BSL_CONFIG_INTERFACE_UART ((uint32_t)0x0000C000) -#define BSL_CONFIG_INTERFACE_AUTO ((uint32_t)0x0000E000) - -#define BSL_CONFIG_I2C_ADD_OFFSET (16) - - -/****************************************************************************** -* ULP Advisor * -******************************************************************************/ -#ifdef __TI_ARM__ -#pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8}) -#pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8}) -#pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8}) -#pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8}) -#pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8}) -#pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8}) -#pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8}) -#pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8}) -#pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8}) -#pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8}) -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* __MSP432P4111_H__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p411v.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p411v.h deleted file mode 100644 index 6b8a510cf41..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p411v.h +++ /dev/null @@ -1,9839 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432P411V Register Definitions -* -* This file includes CMSIS compliant component and register definitions -* -* For legacy components the definitions that are compatible with MSP430 code, -* are included with msp432p411v_classic.h -* -* With CMSIS definitions, the register defines have been reformatted: -* ModuleName[ModuleInstance]->RegisterName -* -* Writing to CMSIS bit fields can be done through register level -* or via bitband area access: -* - ADC14->CTL0 |= ADC14_CTL0_ENC; -* - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1; -* -* File creation date: 2017-08-03 -* -******************************************************************************/ - -#ifndef __MSP432P411V_H__ -#define __MSP432P411V_H__ - -/* Use standard integer types with explicit width */ -#include - -#ifdef __cplusplus - extern "C" { -#endif - -#define __MSP432_HEADER_VERSION__ 3202 - -/* Remap MSP432 intrinsics to ARM equivalents */ -#include "msp_compatibility.h" - -#ifndef __CMSIS_CONFIG__ -#define __CMSIS_CONFIG__ - -/** @addtogroup MSP432P411V_Definitions MSP432P411V Definitions - This file defines all structures and symbols for MSP432P411V: - - components and registers - - peripheral base address - - peripheral ID - - Peripheral definitions - @{ -*/ - -/****************************************************************************** -* Processor and Core Peripherals * -******************************************************************************/ -/** @addtogroup MSP432P411V_CMSIS Device CMSIS Definitions - Configuration of the Cortex-M4 Processor and Core Peripherals - @{ -*/ - -/****************************************************************************** -* CMSIS-compatible Interrupt Number Definition * -******************************************************************************/ -typedef enum IRQn -{ - /* Cortex-M4 Processor Exceptions Numbers */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - /* Peripheral Exceptions Numbers */ - PSS_IRQn = 0, /* 16 PSS Interrupt */ - CS_IRQn = 1, /* 17 CS Interrupt */ - PCM_IRQn = 2, /* 18 PCM Interrupt */ - WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */ - FPU_IRQn = 4, /* 20 FPU Interrupt */ - FLCTL_A_IRQn = 5, /* 21 Flash Controller Interrupt*/ - COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */ - COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */ - TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */ - TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */ - TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */ - TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */ - TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */ - TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */ - TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */ - TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */ - EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */ - EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */ - EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */ - EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */ - EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */ - EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */ - EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */ - EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */ - ADC14_IRQn = 24, /* 40 ADC14 Interrupt */ - T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */ - T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */ - T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */ - AES256_IRQn = 28, /* 44 AES256 Interrupt */ - RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */ - DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */ - DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */ - DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */ - DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */ - DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */ - PORT1_IRQn = 35, /* 51 Port1 Interrupt */ - PORT2_IRQn = 36, /* 52 Port2 Interrupt */ - PORT3_IRQn = 37, /* 53 Port3 Interrupt */ - PORT4_IRQn = 38, /* 54 Port4 Interrupt */ - PORT5_IRQn = 39, /* 55 Port5 Interrupt */ - PORT6_IRQn = 40, /* 56 Port6 Interrupt */ - LCD_F_IRQn = 41 /* 57 LCD_F Interrupt */ -} IRQn_Type; - -/****************************************************************************** -* Processor and Core Peripheral Section * -******************************************************************************/ -#define __CM4_REV 0x0001 /* Core revision r0p1 */ -#define __MPU_PRESENT 1 /* MPU present or not */ -#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /* FPU present or not */ - -/****************************************************************************** -* Available Peripherals * -******************************************************************************/ -#define __MCU_HAS_ADC14__ /*!< Module ADC14 is available */ -#define __MCU_HAS_AES256__ /*!< Module AES256 is available */ -#define __MCU_HAS_CAPTIO0__ /*!< Module CAPTIO0 is available */ -#define __MCU_HAS_CAPTIO1__ /*!< Module CAPTIO1 is available */ -#define __MCU_HAS_COMP_E0__ /*!< Module COMP_E0 is available */ -#define __MCU_HAS_COMP_E1__ /*!< Module COMP_E1 is available */ -#define __MCU_HAS_CRC32__ /*!< Module CRC32 is available */ -#define __MCU_HAS_CS__ /*!< Module CS is available */ -#define __MCU_HAS_DIO__ /*!< Module DIO is available */ -#define __MCU_HAS_DMA__ /*!< Module DMA is available */ -#define __MCU_HAS_EUSCI_A0__ /*!< Module EUSCI_A0 is available */ -#define __MCU_HAS_EUSCI_A1__ /*!< Module EUSCI_A1 is available */ -#define __MCU_HAS_EUSCI_A2__ /*!< Module EUSCI_A2 is available */ -#define __MCU_HAS_EUSCI_A3__ /*!< Module EUSCI_A3 is available */ -#define __MCU_HAS_EUSCI_B0__ /*!< Module EUSCI_B0 is available */ -#define __MCU_HAS_EUSCI_B1__ /*!< Module EUSCI_B1 is available */ -#define __MCU_HAS_EUSCI_B2__ /*!< Module EUSCI_B2 is available */ -#define __MCU_HAS_EUSCI_B3__ /*!< Module EUSCI_B3 is available */ -#define __MCU_HAS_FLCTL_A__ /*!< Module FLCTL_A is available */ -#define __MCU_HAS_FL_BOOTOVER_MAILBOX__ /*!< Module FL_BOOTOVER_MAILBOX is available */ -#define __MCU_HAS_LCD_F__ /*!< Module LCD_F is available */ -#define __MCU_HAS_PCM__ /*!< Module PCM is available */ -#define __MCU_HAS_PMAP__ /*!< Module PMAP is available */ -#define __MCU_HAS_PSS__ /*!< Module PSS is available */ -#define __MCU_HAS_REF_A__ /*!< Module REF_A is available */ -#define __MCU_HAS_RSTCTL__ /*!< Module RSTCTL is available */ -#define __MCU_HAS_RTC_C__ /*!< Module RTC_C is available */ -#define __MCU_HAS_SYSCTL_A__ /*!< Module SYSCTL_A is available */ -#define __MCU_HAS_TIMER32__ /*!< Module TIMER32 is available */ -#define __MCU_HAS_TIMER_A0__ /*!< Module TIMER_A0 is available */ -#define __MCU_HAS_TIMER_A1__ /*!< Module TIMER_A1 is available */ -#define __MCU_HAS_TIMER_A2__ /*!< Module TIMER_A2 is available */ -#define __MCU_HAS_TIMER_A3__ /*!< Module TIMER_A3 is available */ -#define __MCU_HAS_TLV__ /*!< Module TLV is available */ -#define __MCU_HAS_WDT_A__ /*!< Module WDT_A is available */ - -/* Definitions to show that specific ports are available */ - -#define __MSP432_HAS_PORTA_R__ -#define __MSP432_HAS_PORTB_R__ -#define __MSP432_HAS_PORTC_R__ -#define __MSP432_HAS_PORTD_R__ -#define __MSP432_HAS_PORTE_R__ -#define __MSP432_HAS_PORTJ_R__ - -#define __MSP432_HAS_PORT1_R__ -#define __MSP432_HAS_PORT2_R__ -#define __MSP432_HAS_PORT3_R__ -#define __MSP432_HAS_PORT4_R__ -#define __MSP432_HAS_PORT5_R__ -#define __MSP432_HAS_PORT6_R__ -#define __MSP432_HAS_PORT7_R__ -#define __MSP432_HAS_PORT8_R__ -#define __MSP432_HAS_PORT9_R__ -#define __MSP432_HAS_PORT10_R__ - - -/*@}*/ /* end of group MSP432P411V_CMSIS */ - -/* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */ -#ifdef __TI_ARM__ -/* disable the TI ULP advisor check for the core header file definitions */ -#pragma diag_push -#pragma CHECK_ULP("none") -#include "core_cm4.h" -#pragma diag_pop -#else -#include "core_cm4.h" -#endif - -/* System Header */ -#include "system_msp432p411v.h" - -/****************************************************************************** -* Definition of standard bits * -******************************************************************************/ -#define BIT0 (uint16_t)(0x0001) -#define BIT1 (uint16_t)(0x0002) -#define BIT2 (uint16_t)(0x0004) -#define BIT3 (uint16_t)(0x0008) -#define BIT4 (uint16_t)(0x0010) -#define BIT5 (uint16_t)(0x0020) -#define BIT6 (uint16_t)(0x0040) -#define BIT7 (uint16_t)(0x0080) -#define BIT8 (uint16_t)(0x0100) -#define BIT9 (uint16_t)(0x0200) -#define BITA (uint16_t)(0x0400) -#define BITB (uint16_t)(0x0800) -#define BITC (uint16_t)(0x1000) -#define BITD (uint16_t)(0x2000) -#define BITE (uint16_t)(0x4000) -#define BITF (uint16_t)(0x8000) - -/****************************************************************************** -* Device and peripheral memory map * -******************************************************************************/ -/** @addtogroup MSP432P411V_MemoryMap MSP432P411V Memory Mapping - @{ -*/ - -#define FLASH_BASE ((uint32_t)0x00000000) /*!< Main Flash memory start address */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM memory start address */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripherals start address */ -#define PERIPH_BASE2 ((uint32_t)0xE0000000) /*!< Peripherals start address */ - -#define ADC14_BASE (PERIPH_BASE +0x00012000) /*!< Base address of module ADC14 registers */ -#define AES256_BASE (PERIPH_BASE +0x00003C00) /*!< Base address of module AES256 registers */ -#define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /*!< Base address of module CAPTIO0 registers */ -#define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /*!< Base address of module CAPTIO1 registers */ -#define COMP_E0_BASE (PERIPH_BASE +0x00003400) /*!< Base address of module COMP_E0 registers */ -#define COMP_E1_BASE (PERIPH_BASE +0x00003800) /*!< Base address of module COMP_E1 registers */ -#define CRC32_BASE (PERIPH_BASE +0x00004000) /*!< Base address of module CRC32 registers */ -#define CS_BASE (PERIPH_BASE +0x00010400) /*!< Base address of module CS registers */ -#define DIO_BASE (PERIPH_BASE +0x00004C00) /*!< Base address of module DIO registers */ -#define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address of module DMA registers */ -#define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define FLCTL_A_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL_A registers */ -#define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000) /*!< Base address of module FL_BOOTOVER_MAILBOX registers */ -#define LCD_F_BASE (PERIPH_BASE +0x00012400) /*!< Base address of module LCD_F registers */ -#define PCM_BASE (PERIPH_BASE +0x00010000) /*!< Base address of module PCM registers */ -#define PMAP_BASE (PERIPH_BASE +0x00005000) /*!< Base address of module PMAP registers */ -#define PSS_BASE (PERIPH_BASE +0x00010800) /*!< Base address of module PSS registers */ -#define REF_A_BASE (PERIPH_BASE +0x00003000) /*!< Base address of module REF_A registers */ -#define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /*!< Base address of module RSTCTL registers */ -#define RTC_C_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define SYSCTL_A_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL_A registers */ -#define TIMER32_BASE (PERIPH_BASE +0x0000C000) /*!< Base address of module TIMER32 registers */ -#define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /*!< Base address of module TIMER_A0 registers */ -#define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /*!< Base address of module TIMER_A1 registers */ -#define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /*!< Base address of module TIMER_A2 registers */ -#define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /*!< Base address of module TIMER_A3 registers */ -#define TLV_BASE ((uint32_t)0x00201000) /*!< Base address of module TLV registers */ -#define WDT_A_BASE (PERIPH_BASE +0x00004800) /*!< Base address of module WDT_A registers */ - - -/*@}*/ /* end of group MSP432P411V_MemoryMap */ - -/****************************************************************************** -* Definitions for bit band access * -******************************************************************************/ -#define BITBAND_SRAM_BASE ((uint32_t)(0x22000000)) -#define BITBAND_PERI_BASE ((uint32_t)(0x42000000)) - -/* SRAM allows 32 bit bit band access */ -#define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4))) -/* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */ -#define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4))) - -/****************************************************************************** -* Peripheral register definitions * -******************************************************************************/ -/** @addtogroup MSP432P411V_Peripherals MSP432P411V Peripherals - MSP432P411V Device Specific Peripheral registers structures - @{ -*/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - -/****************************************************************************** -* ADC14 Registers -******************************************************************************/ -/** @addtogroup ADC14 MSP432P411V (ADC14) - @{ -*/ -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t LO0; /*!< Window Comparator Low Threshold 0 Register */ - __IO uint32_t HI0; /*!< Window Comparator High Threshold 0 Register */ - __IO uint32_t LO1; /*!< Window Comparator Low Threshold 1 Register */ - __IO uint32_t HI1; /*!< Window Comparator High Threshold 1 Register */ - __IO uint32_t MCTL[32]; /*!< Conversion Memory Control Register */ - __IO uint32_t MEM[32]; /*!< Conversion Memory Register */ - uint32_t RESERVED0[9]; - __IO uint32_t IER0; /*!< Interrupt Enable 0 Register */ - __IO uint32_t IER1; /*!< Interrupt Enable 1 Register */ - __I uint32_t IFGR0; /*!< Interrupt Flag 0 Register */ - __I uint32_t IFGR1; /*!< Interrupt Flag 1 Register */ - __O uint32_t CLRIFGR0; /*!< Clear Interrupt Flag 0 Register */ - __IO uint32_t CLRIFGR1; /*!< Clear Interrupt Flag 1 Register */ - __IO uint32_t IV; /*!< Interrupt Vector Register */ -} ADC14_Type; - -/*@}*/ /* end of group ADC14 */ - - -/****************************************************************************** -* AES256 Registers -******************************************************************************/ -/** @addtogroup AES256 MSP432P411V (AES256) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< AES Accelerator Control Register 0 */ - __IO uint16_t CTL1; /*!< AES Accelerator Control Register 1 */ - __IO uint16_t STAT; /*!< AES Accelerator Status Register */ - __O uint16_t KEY; /*!< AES Accelerator Key Register */ - __O uint16_t DIN; /*!< AES Accelerator Data In Register */ - __O uint16_t DOUT; /*!< AES Accelerator Data Out Register */ - __O uint16_t XDIN; /*!< AES Accelerator XORed Data In Register */ - __O uint16_t XIN; /*!< AES Accelerator XORed Data In Register */ -} AES256_Type; - -/*@}*/ /* end of group AES256 */ - - -/****************************************************************************** -* CAPTIO Registers -******************************************************************************/ -/** @addtogroup CAPTIO MSP432P411V (CAPTIO) - @{ -*/ -typedef struct { - uint16_t RESERVED0[7]; - __IO uint16_t CTL; /*!< Capacitive Touch IO x Control Register */ -} CAPTIO_Type; - -/*@}*/ /* end of group CAPTIO */ - - -/****************************************************************************** -* COMP_E Registers -******************************************************************************/ -/** @addtogroup COMP_E MSP432P411V (COMP_E) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< Comparator Control Register 0 */ - __IO uint16_t CTL1; /*!< Comparator Control Register 1 */ - __IO uint16_t CTL2; /*!< Comparator Control Register 2 */ - __IO uint16_t CTL3; /*!< Comparator Control Register 3 */ - uint16_t RESERVED0[2]; - __IO uint16_t INT; /*!< Comparator Interrupt Control Register */ - __I uint16_t IV; /*!< Comparator Interrupt Vector Word Register */ -} COMP_E_Type; - -/*@}*/ /* end of group COMP_E */ - - -/****************************************************************************** -* CRC32 Registers -******************************************************************************/ -/** @addtogroup CRC32 MSP432P411V (CRC32) - @{ -*/ -typedef struct { - __IO uint16_t DI32; /*!< Data Input for CRC32 Signature Computation */ - uint16_t RESERVED0; - __IO uint16_t DIRB32; /*!< Data In Reverse for CRC32 Computation */ - uint16_t RESERVED1; - __IO uint16_t INIRES32_LO; /*!< CRC32 Initialization and Result, lower 16 bits */ - __IO uint16_t INIRES32_HI; /*!< CRC32 Initialization and Result, upper 16 bits */ - __IO uint16_t RESR32_LO; /*!< CRC32 Result Reverse, lower 16 bits */ - __IO uint16_t RESR32_HI; /*!< CRC32 Result Reverse, Upper 16 bits */ - __IO uint16_t DI16; /*!< Data Input for CRC16 computation */ - uint16_t RESERVED2; - __IO uint16_t DIRB16; /*!< CRC16 Data In Reverse */ - uint16_t RESERVED3; - __IO uint16_t INIRES16; /*!< CRC16 Initialization and Result register */ - uint16_t RESERVED4[2]; - __IO uint16_t RESR16; /*!< CRC16 Result Reverse */ -} CRC32_Type; - -/*@}*/ /* end of group CRC32 */ - - -/****************************************************************************** -* CS Registers -******************************************************************************/ -/** @addtogroup CS MSP432P411V (CS) - @{ -*/ -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t CTL2; /*!< Control 2 Register */ - __IO uint32_t CTL3; /*!< Control 3 Register */ - uint32_t RESERVED0[7]; - __IO uint32_t CLKEN; /*!< Clock Enable Register */ - __I uint32_t STAT; /*!< Status Register */ - uint32_t RESERVED1[2]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - uint32_t RESERVED2; - __I uint32_t IFG; /*!< Interrupt Flag Register */ - uint32_t RESERVED3; - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - uint32_t RESERVED4; - __O uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - uint32_t RESERVED5; - __IO uint32_t DCOERCAL0; /*!< DCO External Resistor Cailbration 0 Register */ - __IO uint32_t DCOERCAL1; /*!< DCO External Resistor Calibration 1 Register */ -} CS_Type; - -/*@}*/ /* end of group CS */ - - -/****************************************************************************** -* DIO Registers -******************************************************************************/ -/** @addtogroup DIO MSP432P4111 (DIO) - @{ -*/ -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - __I uint16_t IV_L; /*!< Low Port Interrupt Vector Value */ - uint16_t RESERVED0[3]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; - union { - __IO uint16_t IES; /*!< Port Pair Interrupt Edge Select */ - struct { - __IO uint8_t IES_L; /*!< Low Port Interrupt Edge Select */ - __IO uint8_t IES_H; /*!< High Port Interrupt Edge Select */ - }; - }; - union { - __IO uint16_t IE; /*!< Port Pair Interrupt Enable */ - struct { - __IO uint8_t IE_L; /*!< Low Port Interrupt Enable */ - __IO uint8_t IE_H; /*!< High Port Interrupt Enable */ - }; - }; - union { - __IO uint16_t IFG; /*!< Port Pair Interrupt Flag */ - struct { - __IO uint8_t IFG_L; /*!< Low Port Interrupt Flag */ - __IO uint8_t IFG_H; /*!< High Port Interrupt Flag */ - }; - }; - __I uint16_t IV_H; /*!< High Port Interrupt Vector Value */ -} DIO_PORT_Interruptable_Type; - -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - uint16_t RESERVED0[4]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; -} DIO_PORT_Not_Interruptable_Type; - - -typedef struct { - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED0; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED1; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED2; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED3; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED4; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED5; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED6; - __I uint16_t IV; /*!< Port Interrupt Vector Value */ - uint8_t RESERVED7[6]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ -} DIO_PORT_Odd_Interruptable_Type; - -typedef struct { - uint8_t RESERVED0; - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED1; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED2; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED3; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED4; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED5; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED6; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED7[9]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ - __I uint16_t IV; /*!< Port Interrupt Vector Value */ -} DIO_PORT_Even_Interruptable_Type; - -/*@}*/ /* end of group MSP432P4111_DIO */ - - -/****************************************************************************** -* DMA Registers -******************************************************************************/ -/** @addtogroup DMA MSP432P4111 (DMA) - @{ -*/ -typedef struct { - __I uint32_t DEVICE_CFG; /*!< Device Configuration Status */ - __IO uint32_t SW_CHTRIG; /*!< Software Channel Trigger Register */ - uint32_t RESERVED0[2]; - __IO uint32_t CH_SRCCFG[32]; /*!< Channel n Source Configuration Register */ - uint32_t RESERVED1[28]; - __IO uint32_t INT1_SRCCFG; /*!< Interrupt 1 Source Channel Configuration */ - __IO uint32_t INT2_SRCCFG; /*!< Interrupt 2 Source Channel Configuration Register */ - __IO uint32_t INT3_SRCCFG; /*!< Interrupt 3 Source Channel Configuration Register */ - uint32_t RESERVED2; - __I uint32_t INT0_SRCFLG; /*!< Interrupt 0 Source Channel Flag Register */ - __O uint32_t INT0_CLRFLG; /*!< Interrupt 0 Source Channel Clear Flag Register */ -} DMA_Channel_Type; - -typedef struct { - __I uint32_t STAT; /*!< Status Register */ - __O uint32_t CFG; /*!< Configuration Register */ - __IO uint32_t CTLBASE; /*!< Channel Control Data Base Pointer Register */ - __I uint32_t ALTBASE; /*!< Channel Alternate Control Data Base Pointer Register */ - __I uint32_t WAITSTAT; /*!< Channel Wait on Request Status Register */ - __O uint32_t SWREQ; /*!< Channel Software Request Register */ - __IO uint32_t USEBURSTSET; /*!< Channel Useburst Set Register */ - __O uint32_t USEBURSTCLR; /*!< Channel Useburst Clear Register */ - __IO uint32_t REQMASKSET; /*!< Channel Request Mask Set Register */ - __O uint32_t REQMASKCLR; /*!< Channel Request Mask Clear Register */ - __IO uint32_t ENASET; /*!< Channel Enable Set Register */ - __O uint32_t ENACLR; /*!< Channel Enable Clear Register */ - __IO uint32_t ALTSET; /*!< Channel Primary-Alternate Set Register */ - __O uint32_t ALTCLR; /*!< Channel Primary-Alternate Clear Register */ - __IO uint32_t PRIOSET; /*!< Channel Priority Set Register */ - __O uint32_t PRIOCLR; /*!< Channel Priority Clear Register */ - uint32_t RESERVED4[3]; - __IO uint32_t ERRCLR; /*!< Bus Error Clear Register */ -} DMA_Control_Type; - -/*@}*/ /* end of group DMA */ - - -/****************************************************************************** -* EUSCI_A Registers -******************************************************************************/ -/** @addtogroup EUSCI_A MSP432P411V (EUSCI_A) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Ax Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Ax Baud Rate Control Word Register */ - __IO uint16_t MCTLW; /*!< eUSCI_Ax Modulation Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Ax Status Register */ - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - __IO uint16_t ABCTL; /*!< eUSCI_Ax Auto Baud Rate Control Register */ - __IO uint16_t IRCTL; /*!< eUSCI_Ax IrDA Control Word Register */ - uint16_t RESERVED1[3]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_Type; - -/*@}*/ /* end of group EUSCI_A */ - -/** @addtogroup EUSCI_A_SPI MSP432P411V (EUSCI_A_SPI) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Ax Bit Rate Control Register 1 */ - uint16_t RESERVED1; - __IO uint16_t STATW; - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - uint16_t RESERVED2[5]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_SPI_Type; - -/*@}*/ /* end of group EUSCI_A_SPI */ - - -/****************************************************************************** -* EUSCI_B Registers -******************************************************************************/ -/** @addtogroup EUSCI_B MSP432P411V (EUSCI_B) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Bx Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Bx Baud Rate Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Bx Status Register */ - __IO uint16_t TBCNT; /*!< eUSCI_Bx Byte Counter Threshold Register */ - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED1[2]; - __IO uint16_t I2COA0; /*!< eUSCI_Bx I2C Own Address 0 Register */ - __IO uint16_t I2COA1; /*!< eUSCI_Bx I2C Own Address 1 Register */ - __IO uint16_t I2COA2; /*!< eUSCI_Bx I2C Own Address 2 Register */ - __IO uint16_t I2COA3; /*!< eUSCI_Bx I2C Own Address 3 Register */ - __I uint16_t ADDRX; /*!< eUSCI_Bx I2C Received Address Register */ - __IO uint16_t ADDMASK; /*!< eUSCI_Bx I2C Address Mask Register */ - __IO uint16_t I2CSA; /*!< eUSCI_Bx I2C Slave Address Register */ - uint16_t RESERVED2[4]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_Type; - -/*@}*/ /* end of group EUSCI_B */ - -/** @addtogroup EUSCI_B_SPI MSP432P411V (EUSCI_B_SPI) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Bx Bit Rate Control Register 1 */ - __IO uint16_t STATW; - uint16_t RESERVED1; - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED2[13]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_SPI_Type; - -/*@}*/ /* end of group EUSCI_B_SPI */ - - -/****************************************************************************** -* FLCTL_A Registers -******************************************************************************/ -/** @addtogroup FLCTL_A MSP432P411V (FLCTL_A) - @{ -*/ -typedef struct { - __I uint32_t POWER_STAT; /*!< Power Status Register */ - uint32_t RESERVED0[3]; - __IO uint32_t BANK0_RDCTL; /*!< Bank0 Read Control Register */ - __IO uint32_t BANK1_RDCTL; /*!< Bank1 Read Control Register */ - uint32_t RESERVED1[2]; - __IO uint32_t RDBRST_CTLSTAT; /*!< Read Burst/Compare Control and Status Register */ - __IO uint32_t RDBRST_STARTADDR; /*!< Read Burst/Compare Start Address Register */ - __IO uint32_t RDBRST_LEN; /*!< Read Burst/Compare Length Register */ - uint32_t RESERVED2[4]; - __IO uint32_t RDBRST_FAILADDR; /*!< Read Burst/Compare Fail Address Register */ - __IO uint32_t RDBRST_FAILCNT; /*!< Read Burst/Compare Fail Count Register */ - uint32_t RESERVED3[3]; - __IO uint32_t PRG_CTLSTAT; /*!< Program Control and Status Register */ - __IO uint32_t PRGBRST_CTLSTAT; /*!< Program Burst Control and Status Register */ - __IO uint32_t PRGBRST_STARTADDR; /*!< Program Burst Start Address Register */ - uint32_t RESERVED4; - __IO uint32_t PRGBRST_DATA0_0; /*!< Program Burst Data0 Register0 */ - __IO uint32_t PRGBRST_DATA0_1; /*!< Program Burst Data0 Register1 */ - __IO uint32_t PRGBRST_DATA0_2; /*!< Program Burst Data0 Register2 */ - __IO uint32_t PRGBRST_DATA0_3; /*!< Program Burst Data0 Register3 */ - __IO uint32_t PRGBRST_DATA1_0; /*!< Program Burst Data1 Register0 */ - __IO uint32_t PRGBRST_DATA1_1; /*!< Program Burst Data1 Register1 */ - __IO uint32_t PRGBRST_DATA1_2; /*!< Program Burst Data1 Register2 */ - __IO uint32_t PRGBRST_DATA1_3; /*!< Program Burst Data1 Register3 */ - __IO uint32_t PRGBRST_DATA2_0; /*!< Program Burst Data2 Register0 */ - __IO uint32_t PRGBRST_DATA2_1; /*!< Program Burst Data2 Register1 */ - __IO uint32_t PRGBRST_DATA2_2; /*!< Program Burst Data2 Register2 */ - __IO uint32_t PRGBRST_DATA2_3; /*!< Program Burst Data2 Register3 */ - __IO uint32_t PRGBRST_DATA3_0; /*!< Program Burst Data3 Register0 */ - __IO uint32_t PRGBRST_DATA3_1; /*!< Program Burst Data3 Register1 */ - __IO uint32_t PRGBRST_DATA3_2; /*!< Program Burst Data3 Register2 */ - __IO uint32_t PRGBRST_DATA3_3; /*!< Program Burst Data3 Register3 */ - __IO uint32_t ERASE_CTLSTAT; /*!< Erase Control and Status Register */ - __IO uint32_t ERASE_SECTADDR; /*!< Erase Sector Address Register */ - uint32_t RESERVED5[2]; - __IO uint32_t BANK0_INFO_WEPROT; /*!< Information Memory Bank0 Write/Erase Protection Register */ - __IO uint32_t BANK0_MAIN_WEPROT; /*!< Main Memory Bank0 Write/Erase Protection Register */ - uint32_t RESERVED6[2]; - __IO uint32_t BANK1_INFO_WEPROT; /*!< Information Memory Bank1 Write/Erase Protection Register */ - __IO uint32_t BANK1_MAIN_WEPROT; /*!< Main Memory Bank1 Write/Erase Protection Register */ - uint32_t RESERVED7[2]; - __IO uint32_t BMRK_CTLSTAT; /*!< Benchmark Control and Status Register */ - __IO uint32_t BMRK_IFETCH; /*!< Benchmark Instruction Fetch Count Register */ - __IO uint32_t BMRK_DREAD; /*!< Benchmark Data Read Count Register */ - __IO uint32_t BMRK_CMP; /*!< Benchmark Count Compare Register */ - uint32_t RESERVED8[4]; - __IO uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - __IO uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - __I uint32_t READ_TIMCTL; /*!< Read Timing Control Register */ - __I uint32_t READMARGIN_TIMCTL; /*!< Read Margin Timing Control Register */ - __I uint32_t PRGVER_TIMCTL; /*!< Program Verify Timing Control Register */ - __I uint32_t ERSVER_TIMCTL; /*!< Erase Verify Timing Control Register */ - __I uint32_t LKGVER_TIMCTL; /*!< Leakage Verify Timing Control Register */ - __I uint32_t PROGRAM_TIMCTL; /*!< Program Timing Control Register */ - __I uint32_t ERASE_TIMCTL; /*!< Erase Timing Control Register */ - __I uint32_t MASSERASE_TIMCTL; /*!< Mass Erase Timing Control Register */ - __I uint32_t BURSTPRG_TIMCTL; /*!< Burst Program Timing Control Register */ - uint32_t RESERVED9[55]; - __IO uint32_t BANK0_MAIN_WEPROT0; /*!< Main Memory Bank0 Write/Erase Protection Register 0 */ - __IO uint32_t BANK0_MAIN_WEPROT1; /*!< Main Memory Bank0 Write/Erase Protection Register 1 */ - __IO uint32_t BANK0_MAIN_WEPROT2; /*!< Main Memory Bank0 Write/Erase Protection Register 2 */ - __IO uint32_t BANK0_MAIN_WEPROT3; /*!< Main Memory Bank0 Write/Erase Protection Register 3 */ - __IO uint32_t BANK0_MAIN_WEPROT4; /*!< Main Memory Bank0 Write/Erase Protection Register 4 */ - __IO uint32_t BANK0_MAIN_WEPROT5; /*!< Main Memory Bank0 Write/Erase Protection Register 5 */ - __IO uint32_t BANK0_MAIN_WEPROT6; /*!< Main Memory Bank0 Write/Erase Protection Register 6 */ - __IO uint32_t BANK0_MAIN_WEPROT7; /*!< Main Memory Bank0 Write/Erase Protection Register 7 */ - uint32_t RESERVED10[8]; - __IO uint32_t BANK1_MAIN_WEPROT0; /*!< Main Memory Bank1 Write/Erase Protection Register 0 */ - __IO uint32_t BANK1_MAIN_WEPROT1; /*!< Main Memory Bank1 Write/Erase Protection Register 1 */ - __IO uint32_t BANK1_MAIN_WEPROT2; /*!< Main Memory Bank1 Write/Erase Protection Register 2 */ - __IO uint32_t BANK1_MAIN_WEPROT3; /*!< Main Memory Bank1 Write/Erase Protection Register 3 */ - __IO uint32_t BANK1_MAIN_WEPROT4; /*!< Main Memory Bank1 Write/Erase Protection Register 4 */ - __IO uint32_t BANK1_MAIN_WEPROT5; /*!< Main Memory Bank1 Write/Erase Protection Register 5 */ - __IO uint32_t BANK1_MAIN_WEPROT6; /*!< Main Memory Bank1 Write/Erase Protection Register 6 */ - __IO uint32_t BANK1_MAIN_WEPROT7; /*!< Main Memory Bank1 Write/Erase Protection Register 7 */ -} FLCTL_A_Type; - -/*@}*/ /* end of group FLCTL_A */ - - -/****************************************************************************** -* FL_BOOTOVER_MAILBOX Registers -******************************************************************************/ -/** @addtogroup SEC_ZONE_PARAMS MSP432P411V (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t SEC_ZONE_SECEN; /*!< IP Protection Secure Zone Enable. */ - __IO uint32_t SEC_ZONE_START_ADDR; /*!< Start address of IP protected secure zone. */ - __IO uint32_t SEC_ZONE_LENGTH; /*!< Length of IP protected secure zone in number of bytes. */ - __IO uint32_t SEC_ZONE_AESINIT_VECT[4]; /*!< IP protected secure zone 0 AES initialization vector */ - __IO uint32_t SEC_ZONE_SECKEYS[8]; /*!< AES-CBC security keys. */ - __IO uint32_t SEC_ZONE_UNENC_PWD[4]; /*!< Unencrypted password for authentication. */ - __IO uint32_t SEC_ZONE_ENCUPDATE_EN; /*!< IP Protected Secure Zone Encrypted In-field Update Enable */ - __IO uint32_t SEC_ZONE_DATA_EN; /*!< IP Protected Secure Zone Data Access Enable */ - __IO uint32_t SEC_ZONE_ACK; /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */ - uint32_t RESERVED0[2]; -} SEC_ZONE_PARAMS_Type; - -/*@}*/ /* end of group SEC_ZONE_PARAMS */ - -/** @addtogroup SEC_ZONE_UPDATE MSP432P411V (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t SEC_ZONE_PAYLOADADDR; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t SEC_ZONE_PAYLOADLEN; /*!< Length of the payload in bytes. */ - __IO uint32_t SEC_ZONE_UPDATE_ACK; /*!< Acknowledgment for the IP Protected Secure Zone Update Command */ - uint32_t RESERVED0; -} SEC_ZONE_UPDATE_Type; - -/*@}*/ /* end of group SEC_ZONE_UPDATE */ - -/** @addtogroup FL_BOOTOVER_MAILBOX MSP432P411V (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t MB_START; /*!< Flash MailBox start: 0x0115ACF6 */ - __IO uint32_t CMD; /*!< Command for Boot override operations. */ - uint32_t RESERVED0[2]; - __IO uint32_t JTAG_SWD_LOCK_SECEN; /*!< JTAG and SWD Lock Enable */ - __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4]; /*!< JTAG and SWD lock AES initialization vector for AES-CBC */ - __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8]; /*!< JTAG and SWD lock AES CBC security Keys 0-7. */ - __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4]; /*!< JTAG and SWD lock unencrypted password */ - __IO uint32_t JTAG_SWD_LOCK_ACK; /*!< Acknowledgment for JTAG and SWD Lock command */ - uint32_t RESERVED1[2]; - SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4]; - __IO uint32_t BSL_ENABLE; /*!< BSL Enable. */ - __IO uint32_t BSL_START_ADDRESS; /*!< Contains the pointer to the BSL function. */ - __IO uint32_t BSL_PARAMETERS; /*!< BSL hardware invoke conifguration field. */ - uint32_t RESERVED2[2]; - __IO uint32_t BSL_ACK; /*!< Acknowledgment for the BSL Configuration Command */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN; /*!< Length of the encrypted payload in bytes */ - __IO uint32_t JTAG_SWD_LOCK_DST_ADDR; /*!< Destination address where the final data needs to be stored into the device. */ - __IO uint32_t ENC_UPDATE_ACK; /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */ - uint32_t RESERVED3; - SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4]; - uint32_t RESERVED4; - __IO uint32_t FACTORY_RESET_ENABLE; /*!< Enable/Disable Factory Reset */ - __IO uint32_t FACTORY_RESET_PWDEN; /*!< Factory reset password enable */ - __IO uint32_t FACTORY_RESET_PWD[4]; /*!< 128-bit Password for factory reset to be saved into the device. */ - __IO uint32_t FACTORY_RESET_PARAMS_ACK; /*!< Acknowledgment for the Factory Reset Params Command */ - uint32_t RESERVED5; - __IO uint32_t FACTORY_RESET_PASSWORD[4]; /*!< 128-bit Password for factory reset. */ - __IO uint32_t FACTORY_RESET_ACK; /*!< Acknowledgment for the Factory Reset Command */ - uint32_t RESERVED6[2]; - __IO uint32_t MB_END; /*!< Mailbox end */ -} FL_BOOTOVER_MAILBOX_Type; - -/*@}*/ /* end of group FL_BOOTOVER_MAILBOX */ - - -/****************************************************************************** -* LCD_F Registers -******************************************************************************/ -/** @addtogroup LCD_F MSP432P411V (LCD_F) - @{ -*/ -typedef struct { - __IO uint32_t CTL; /*!< LCD_F control */ - __IO uint32_t BMCTL; /*!< LCD_F blinking and memory control */ - __IO uint32_t VCTL; /*!< LCD_F voltage control */ - __IO uint32_t PCTL0; /*!< LCD_F port control 0 */ - __IO uint32_t PCTL1; /*!< LCD_F port control 1 */ - __IO uint32_t CSSEL0; /*!< LCD_F COM/SEG select register 0 */ - __IO uint32_t CSSEL1; /*!< LCD_F COM/SEG select register 1 */ - __IO uint32_t ANMCTL; /*!< LCD_F Animation Control Register */ - uint32_t RESERVED0[60]; - __IO uint32_t IE; /*!< LCD_F interrupt enable register */ - __I uint32_t IFG; /*!< LCD_F interrupt flag register */ - __O uint32_t SETIFG; /*!< LCD_F set interrupt flag register */ - __O uint32_t CLRIFG; /*!< LCD_F clear interrupt flag register */ - __IO uint8_t M[48]; /*!< LCD memory registers */ - uint8_t RESERVED1[16]; - __IO uint8_t BM[48]; /*!< LCD Blinking memory registers */ - uint8_t RESERVED2[16]; - __IO uint8_t ANM[8]; /*!< LCD Animation memory registers */ -} LCD_F_Type; - -/*@}*/ /* end of group LCD_F */ - - -/****************************************************************************** -* PCM Registers -******************************************************************************/ -/** @addtogroup PCM MSP432P411V (PCM) - @{ -*/ -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PCM_Type; - -/*@}*/ /* end of group PCM */ - - -/****************************************************************************** -* PMAP Registers -******************************************************************************/ -/** @addtogroup PMAP MSP432P4111 (PMAP) - @{ -*/ -typedef struct { - __IO uint16_t KEYID; /*!< Port Mapping Key Register */ - __IO uint16_t CTL; /*!< Port Mapping Control Register */ -} PMAP_COMMON_Type; - -typedef struct { - union { - __IO uint16_t PMAP_REGISTER[4]; /*!< Port Mapping Registers */ - struct { - __IO uint8_t PMAP_REGISTER0; /*!< Port Mapping Register Bit 0 */ - __IO uint8_t PMAP_REGISTER1; /*!< Port Mapping Register Bit 1 */ - __IO uint8_t PMAP_REGISTER2; /*!< Port Mapping Register Bit 2 */ - __IO uint8_t PMAP_REGISTER3; /*!< Port Mapping Register Bit 3 */ - __IO uint8_t PMAP_REGISTER4; /*!< Port Mapping Register Bit 4 */ - __IO uint8_t PMAP_REGISTER5; /*!< Port Mapping Register Bit 5 */ - __IO uint8_t PMAP_REGISTER6; /*!< Port Mapping Register Bit 6 */ - __IO uint8_t PMAP_REGISTER7; /*!< Port Mapping Register Bit 7 */ - }; - }; -} PMAP_REGISTER_Type; - -/*@}*/ /* end of group PMAP */ - - -/****************************************************************************** -* PSS Registers -******************************************************************************/ -/** @addtogroup PSS MSP432P411V (PSS) - @{ -*/ -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - uint32_t RESERVED0[11]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PSS_Type; - -/*@}*/ /* end of group PSS */ - - -/****************************************************************************** -* REF_A Registers -******************************************************************************/ -/** @addtogroup REF_A MSP432P411V (REF_A) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< REF Control Register 0 */ -} REF_A_Type; - -/*@}*/ /* end of group REF_A */ - - -/****************************************************************************** -* RSTCTL Registers -******************************************************************************/ -/** @addtogroup RSTCTL MSP432P411V (RSTCTL) - @{ -*/ -typedef struct { - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __I uint32_t HARDRESET_STAT; /*!< Hard Reset Status Register */ - __IO uint32_t HARDRESET_CLR; /*!< Hard Reset Status Clear Register */ - __IO uint32_t HARDRESET_SET; /*!< Hard Reset Status Set Register */ - __I uint32_t SOFTRESET_STAT; /*!< Soft Reset Status Register */ - __IO uint32_t SOFTRESET_CLR; /*!< Soft Reset Status Clear Register */ - __IO uint32_t SOFTRESET_SET; /*!< Soft Reset Status Set Register */ - uint32_t RESERVED0[57]; - __I uint32_t PSSRESET_STAT; /*!< PSS Reset Status Register */ - __IO uint32_t PSSRESET_CLR; /*!< PSS Reset Status Clear Register */ - __I uint32_t PCMRESET_STAT; /*!< PCM Reset Status Register */ - __IO uint32_t PCMRESET_CLR; /*!< PCM Reset Status Clear Register */ - __I uint32_t PINRESET_STAT; /*!< Pin Reset Status Register */ - __IO uint32_t PINRESET_CLR; /*!< Pin Reset Status Clear Register */ - __I uint32_t REBOOTRESET_STAT; /*!< Reboot Reset Status Register */ - __IO uint32_t REBOOTRESET_CLR; /*!< Reboot Reset Status Clear Register */ - __I uint32_t CSRESET_STAT; /*!< CS Reset Status Register */ - __IO uint32_t CSRESET_CLR; /*!< CS Reset Status Clear Register */ -} RSTCTL_Type; - -/*@}*/ /* end of group RSTCTL */ - - -/****************************************************************************** -* RTC_C Registers -******************************************************************************/ -/** @addtogroup RTC_C MSP432P411V (RTC_C) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< RTCCTL0 Register */ - __IO uint16_t CTL13; /*!< RTCCTL13 Register */ - __IO uint16_t OCAL; /*!< RTCOCAL Register */ - __IO uint16_t TCMP; /*!< RTCTCMP Register */ - __IO uint16_t PS0CTL; /*!< Real-Time Clock Prescale Timer 0 Control Register */ - __IO uint16_t PS1CTL; /*!< Real-Time Clock Prescale Timer 1 Control Register */ - __IO uint16_t PS; /*!< Real-Time Clock Prescale Timer Counter Register */ - __I uint16_t IV; /*!< Real-Time Clock Interrupt Vector Register */ - __IO uint16_t TIM0; /*!< RTCTIM0 Register Hexadecimal Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week */ - __IO uint16_t DATE; /*!< RTCDATE - Hexadecimal Format */ - __IO uint16_t YEAR; /*!< RTCYEAR Register Hexadecimal Format */ - __IO uint16_t AMINHR; /*!< RTCMINHR - Hexadecimal Format */ - __IO uint16_t ADOWDAY; /*!< RTCADOWDAY - Hexadecimal Format */ - __IO uint16_t BIN2BCD; /*!< Binary-to-BCD Conversion Register */ - __IO uint16_t BCD2BIN; /*!< BCD-to-Binary Conversion Register */ -} RTC_C_Type; - -/*@}*/ /* end of group RTC_C */ - -/** @addtogroup RTC_C_BCD MSP432P411V (RTC_C_BCD) - @{ -*/ -typedef struct { - uint16_t RESERVED0[8]; - __IO uint16_t TIM0; /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week - BCD Format */ - __IO uint16_t DATE; /*!< Real-Time Clock Date - BCD Format */ - __IO uint16_t YEAR; /*!< Real-Time Clock Year Register - BCD Format */ - __IO uint16_t AMINHR; /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */ - __IO uint16_t ADOWDAY; /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */ -} RTC_C_BCD_Type; - -/*@}*/ /* end of group RTC_C_BCD */ - - -/****************************************************************************** -* SYSCTL_A Registers -******************************************************************************/ -/** @addtogroup SYSCTL_A MSP432P4111 (SYSCTL_A) - @{ -*/ -typedef struct { - __IO uint32_t REBOOT_CTL; /*!< Reboot Control Register */ - __IO uint32_t NMI_CTLSTAT; /*!< NMI Control and Status Register */ - __IO uint32_t WDTRESET_CTL; /*!< Watchdog Reset Control Register */ - __IO uint32_t PERIHALT_CTL; /*!< Peripheral Halt Control Register */ - __I uint32_t SRAM_SIZE; /*!< SRAM Size Register */ - __I uint32_t SRAM_NUMBANKS; /*!< SRAM Number of Banks Register */ - __I uint32_t SRAM_NUMBLOCKS; /*!< SRAM Number of Blocks Register */ - uint32_t RESERVED0; - __I uint32_t MAINFLASH_SIZE; /*!< Flash Main Memory Size Register */ - __I uint32_t INFOFLASH_SIZE; /*!< Flash Information Memory Size Register */ - uint32_t RESERVED1[2]; - __IO uint32_t DIO_GLTFLT_CTL; /*!< Digital I/O Glitch Filter Control Register */ - uint32_t RESERVED2[3]; - __IO uint32_t SECDATA_UNLOCK; /*!< IP Protected Secure Zone Data Access Unlock Register */ - uint32_t RESERVED3[3]; - __IO uint32_t SRAM_BANKEN_CTL0; /*!< SRAM Bank Enable Control Register 0 */ - __IO uint32_t SRAM_BANKEN_CTL1; /*!< SRAM Bank Enable Control Register 1 */ - __IO uint32_t SRAM_BANKEN_CTL2; /*!< SRAM Bank Enable Control Register 2 */ - __IO uint32_t SRAM_BANKEN_CTL3; /*!< SRAM Bank Enable Control Register 3 */ - uint32_t RESERVED4[4]; - __IO uint32_t SRAM_BLKRET_CTL0; /*!< SRAM Block Retention Control Register 0 */ - __IO uint32_t SRAM_BLKRET_CTL1; /*!< SRAM Block Retention Control Register 1 */ - __IO uint32_t SRAM_BLKRET_CTL2; /*!< SRAM Block Retention Control Register 2 */ - __IO uint32_t SRAM_BLKRET_CTL3; /*!< SRAM Block Retention Control Register 3 */ - uint32_t RESERVED5[4]; - __I uint32_t SRAM_STAT; /*!< SRAM Status Register */ -} SYSCTL_A_Type; - -typedef struct { - __IO uint32_t MASTER_UNLOCK; /*!< Master Unlock Register */ - __IO uint32_t BOOTOVER_REQ[2]; /*!< Boot Override Request Register */ - __IO uint32_t BOOTOVER_ACK; /*!< Boot Override Acknowledge Register */ - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __IO uint32_t RESET_STATOVER; /*!< Reset Status and Override Register */ - uint32_t RESERVED10[2]; - __I uint32_t SYSTEM_STAT; /*!< System Status Register */ -} SYSCTL_A_Boot_Type; - -/*@}*/ /* end of group SYSCTL_A */ - - -/****************************************************************************** -* Timer32 Registers -******************************************************************************/ -/** @addtogroup Timer32 MSP432P4111 (Timer32) - @{ -*/ -typedef struct { - __IO uint32_t LOAD; /*!< Timer Load Register */ - __I uint32_t VALUE; /*!< Timer Current Value Register */ - __IO uint32_t CONTROL; /*!< Timer Timer Control Register */ - __O uint32_t INTCLR; /*!< Timer Interrupt Clear Register */ - __I uint32_t RIS; /*!< Timer Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< Timer Interrupt Status Register */ - __IO uint32_t BGLOAD; /*!< Timer Background Load Register */ -} Timer32_Type; - -/*@}*/ /* end of group Timer32 */ - - -/****************************************************************************** -* Timer_A Registers -******************************************************************************/ -/** @addtogroup Timer_A MSP432P411V (Timer_A) - @{ -*/ -typedef struct { - __IO uint16_t CTL; /*!< TimerAx Control Register */ - __IO uint16_t CCTL[5]; /*!< Timer_A Capture/Compare Control Register */ - uint16_t RESERVED0[2]; - __IO uint16_t R; /*!< TimerA register */ - __IO uint16_t CCR[5]; /*!< Timer_A Capture/Compare Register */ - uint16_t RESERVED1[2]; - __IO uint16_t EX0; /*!< TimerAx Expansion 0 Register */ - uint16_t RESERVED2[6]; - __I uint16_t IV; /*!< TimerAx Interrupt Vector Register */ -} Timer_A_Type; - -/*@}*/ /* end of group Timer_A */ - - -/****************************************************************************** -* TLV Registers -******************************************************************************/ -/** @addtogroup TLV MSP432P411V (TLV) - @{ -*/ -typedef struct { - __I uint32_t TLV_CHECKSUM; /*!< TLV Checksum */ - __I uint32_t DEVICE_INFO_TAG; /*!< Device Info Tag */ - __I uint32_t DEVICE_INFO_LEN; /*!< Device Info Length */ - __I uint32_t DEVICE_ID; /*!< Device ID */ - __I uint32_t HWREV; /*!< HW Revision */ - __I uint32_t BCREV; /*!< Boot Code Revision */ - __I uint32_t ROM_DRVLIB_REV; /*!< ROM Driver Library Revision */ - __I uint32_t DIE_REC_TAG; /*!< Die Record Tag */ - __I uint32_t DIE_REC_LEN; /*!< Die Record Length */ - __I uint32_t DIE_XPOS; /*!< Die X-Position */ - __I uint32_t DIE_YPOS; /*!< Die Y-Position */ - __I uint32_t WAFER_ID; /*!< Wafer ID */ - __I uint32_t LOT_ID; /*!< Lot ID */ - __I uint32_t RESERVED0; /*!< Reserved */ - __I uint32_t RESERVED1; /*!< Reserved */ - __I uint32_t RESERVED2; /*!< Reserved */ - __I uint32_t TEST_RESULTS; /*!< Test Results */ - __I uint32_t CS_CAL_TAG; /*!< Clock System Calibration Tag */ - __I uint32_t CS_CAL_LEN; /*!< Clock System Calibration Length */ - __I uint32_t DCOIR_FCAL_RSEL04; /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_FCAL_RSEL5; /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED3; /*!< Reserved */ - __I uint32_t RESERVED4; /*!< Reserved */ - __I uint32_t RESERVED5; /*!< Reserved */ - __I uint32_t RESERVED6; /*!< Reserved */ - __I uint32_t DCOIR_CONSTK_RSEL04; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_CONSTK_RSEL5; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t DCOER_FCAL_RSEL04; /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOER_FCAL_RSEL5; /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED7; /*!< Reserved */ - __I uint32_t RESERVED8; /*!< Reserved */ - __I uint32_t RESERVED9; /*!< Reserved */ - __I uint32_t RESERVED10; /*!< Reserved */ - __I uint32_t DCOER_CONSTK_RSEL04; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I uint32_t DCOER_CONSTK_RSEL5; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t ADC14_CAL_TAG; /*!< ADC14 Calibration Tag */ - __I uint32_t ADC14_CAL_LEN; /*!< ADC14 Calibration Length */ - __I uint32_t ADC_GAIN_FACTOR; /*!< ADC Gain Factor */ - __I uint32_t ADC_OFFSET; /*!< ADC Offset */ - __I uint32_t RESERVED11; /*!< Reserved */ - __I uint32_t RESERVED12; /*!< Reserved */ - __I uint32_t RESERVED13; /*!< Reserved */ - __I uint32_t RESERVED14; /*!< Reserved */ - __I uint32_t RESERVED15; /*!< Reserved */ - __I uint32_t RESERVED16; /*!< Reserved */ - __I uint32_t RESERVED17; /*!< Reserved */ - __I uint32_t RESERVED18; /*!< Reserved */ - __I uint32_t RESERVED19; /*!< Reserved */ - __I uint32_t RESERVED20; /*!< Reserved */ - __I uint32_t RESERVED21; /*!< Reserved */ - __I uint32_t RESERVED22; /*!< Reserved */ - __I uint32_t RESERVED23; /*!< Reserved */ - __I uint32_t RESERVED24; /*!< Reserved */ - __I uint32_t RESERVED25; /*!< Reserved */ - __I uint32_t RESERVED26; /*!< Reserved */ - __I uint32_t ADC14_REF1P2V_TS30C; /*!< ADC14 1.2V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P2V_TS85C; /*!< ADC14 1.2V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF1P45V_TS30C; /*!< ADC14 1.45V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P45V_TS85C; /*!< ADC14 1.45V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF2P5V_TS30C; /*!< ADC14 2.5V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF2P5V_TS85C; /*!< ADC14 2.5V Reference Temp. Sensor 85C */ - __I uint32_t REF_CAL_TAG; /*!< REF Calibration Tag */ - __I uint32_t REF_CAL_LEN; /*!< REF Calibration Length */ - __I uint32_t REF_1P2V; /*!< REF 1.2V Reference */ - __I uint32_t REF_1P45V; /*!< REF 1.45V Reference */ - __I uint32_t REF_2P5V; /*!< REF 2.5V Reference */ - __I uint32_t FLASH_INFO_TAG; /*!< Flash Info Tag */ - __I uint32_t FLASH_INFO_LEN; /*!< Flash Info Length */ - __I uint32_t FLASH_MAX_PROG_PULSES; /*!< Flash Maximum Programming Pulses */ - __I uint32_t FLASH_MAX_ERASE_PULSES; /*!< Flash Maximum Erase Pulses */ - __I uint32_t RANDOM_NUM_TAG; /*!< 128-bit Random Number Tag */ - __I uint32_t RANDOM_NUM_LEN; /*!< 128-bit Random Number Length */ - __I uint32_t RANDOM_NUM_1; /*!< 32-bit Random Number 1 */ - __I uint32_t RANDOM_NUM_2; /*!< 32-bit Random Number 2 */ - __I uint32_t RANDOM_NUM_3; /*!< 32-bit Random Number 3 */ - __I uint32_t RANDOM_NUM_4; /*!< 32-bit Random Number 4 */ - __I uint32_t BSL_CFG_TAG; /*!< BSL Configuration Tag */ - __I uint32_t BSL_CFG_LEN; /*!< BSL Configuration Length */ - __I uint32_t BSL_PERIPHIF_SEL; /*!< BSL Peripheral Interface Selection */ - __I uint32_t BSL_PORTIF_CFG_UART; /*!< BSL Port Interface Configuration for UART */ - __I uint32_t BSL_PORTIF_CFG_SPI; /*!< BSL Port Interface Configuration for SPI */ - __I uint32_t BSL_PORTIF_CFG_I2C; /*!< BSL Port Interface Configuration for I2C */ - __I uint32_t TLV_END; /*!< TLV End Word */ -} TLV_Type; - -/*@}*/ /* end of group TLV */ - - -/****************************************************************************** -* WDT_A Registers -******************************************************************************/ -/** @addtogroup WDT_A MSP432P411V (WDT_A) - @{ -*/ -typedef struct { - uint16_t RESERVED0[6]; - __IO uint16_t CTL; /*!< Watchdog Timer Control Register */ -} WDT_A_Type; - -/*@}*/ /* end of group WDT_A */ - - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/*@}*/ /* end of group MSP432P411V_Peripherals */ - -/****************************************************************************** -* Peripheral declaration * -******************************************************************************/ -/** @addtogroup MSP432P411V_PeripheralDecl MSP432P411V Peripheral Declaration - @{ -*/ - -#define ADC14 ((ADC14_Type *) ADC14_BASE) -#define AES256 ((AES256_Type *) AES256_BASE) -#define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE) -#define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE) -#define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE) -#define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE) -#define CRC32 ((CRC32_Type *) CRC32_BASE) -#define CS ((CS_Type *) CS_BASE) -#define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120)) -#define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define DMA_Channel ((DMA_Channel_Type *) DMA_BASE) -#define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000)) -#define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE) -#define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE) -#define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE) -#define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE) -#define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE) -#define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE) -#define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE) -#define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE) -#define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE) -#define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE) -#define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE) -#define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE) -#define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE) -#define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE) -#define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE) -#define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE) -#define FLCTL_A ((FLCTL_A_Type *) FLCTL_A_BASE) -#define FL_BOOTOVER_MAILBOX ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE) -#define LCD_F ((LCD_F_Type *) LCD_F_BASE) -#define PCM ((PCM_Type *) PCM_BASE) -#define PMAP ((PMAP_COMMON_Type*) PMAP_BASE) -#define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008)) -#define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010)) -#define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018)) -#define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020)) -#define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028)) -#define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030)) -#define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038)) -#define PSS ((PSS_Type *) PSS_BASE) -#define REF_A ((REF_A_Type *) REF_A_BASE) -#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) -#define RTC_C ((RTC_C_Type *) RTC_C_BASE) -#define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE) -#define SYSCTL_A ((SYSCTL_A_Type *) SYSCTL_A_BASE) -#define SYSCTL_A_Boot ((SYSCTL_A_Boot_Type *) (SYSCTL_A_BASE + 0x1000)) -#define TIMER32_1 ((Timer32_Type *) TIMER32_BASE) -#define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020)) -#define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE) -#define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE) -#define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE) -#define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE) -#define TLV ((TLV_Type *) TLV_BASE) -#define WDT_A ((WDT_A_Type *) WDT_A_BASE) - - -/*@}*/ /* end of group MSP432P411V_PeripheralDecl */ - -/*@}*/ /* end of group MSP432P411V_Definitions */ - -#endif /* __CMSIS_CONFIG__ */ - -/****************************************************************************** -* Peripheral register control bits * -******************************************************************************/ - -/****************************************************************************** -* ADC14 Bits -******************************************************************************/ -/* ADC14_CTL0[SC] Bits */ -#define ADC14_CTL0_SC_OFS ( 0) /*!< ADC14SC Bit Offset */ -#define ADC14_CTL0_SC ((uint32_t)0x00000001) /*!< ADC14 start conversion */ -/* ADC14_CTL0[ENC] Bits */ -#define ADC14_CTL0_ENC_OFS ( 1) /*!< ADC14ENC Bit Offset */ -#define ADC14_CTL0_ENC ((uint32_t)0x00000002) /*!< ADC14 enable conversion */ -/* ADC14_CTL0[ON] Bits */ -#define ADC14_CTL0_ON_OFS ( 4) /*!< ADC14ON Bit Offset */ -#define ADC14_CTL0_ON ((uint32_t)0x00000010) /*!< ADC14 on */ -/* ADC14_CTL0[MSC] Bits */ -#define ADC14_CTL0_MSC_OFS ( 7) /*!< ADC14MSC Bit Offset */ -#define ADC14_CTL0_MSC ((uint32_t)0x00000080) /*!< ADC14 multiple sample and conversion */ -/* ADC14_CTL0[SHT0] Bits */ -#define ADC14_CTL0_SHT0_OFS ( 8) /*!< ADC14SHT0 Bit Offset */ -#define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /*!< ADC14SHT0 Bit Mask */ -#define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /*!< SHT0 Bit 0 */ -#define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /*!< SHT0 Bit 1 */ -#define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /*!< SHT0 Bit 2 */ -#define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /*!< SHT0 Bit 3 */ -#define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /*!< 192 */ -#define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /*!< 192 */ -/* ADC14_CTL0[SHT1] Bits */ -#define ADC14_CTL0_SHT1_OFS (12) /*!< ADC14SHT1 Bit Offset */ -#define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /*!< ADC14SHT1 Bit Mask */ -#define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /*!< SHT1 Bit 0 */ -#define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /*!< SHT1 Bit 1 */ -#define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /*!< SHT1 Bit 2 */ -#define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /*!< SHT1 Bit 3 */ -#define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /*!< 192 */ -#define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /*!< 192 */ -/* ADC14_CTL0[BUSY] Bits */ -#define ADC14_CTL0_BUSY_OFS (16) /*!< ADC14BUSY Bit Offset */ -#define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /*!< ADC14 busy */ -/* ADC14_CTL0[CONSEQ] Bits */ -#define ADC14_CTL0_CONSEQ_OFS (17) /*!< ADC14CONSEQ Bit Offset */ -#define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /*!< ADC14CONSEQ Bit Mask */ -#define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /*!< CONSEQ Bit 0 */ -#define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /*!< CONSEQ Bit 1 */ -#define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /*!< Single-channel, single-conversion */ -#define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /*!< Sequence-of-channels */ -#define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /*!< Repeat-single-channel */ -#define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /*!< Repeat-sequence-of-channels */ -/* ADC14_CTL0[SSEL] Bits */ -#define ADC14_CTL0_SSEL_OFS (19) /*!< ADC14SSEL Bit Offset */ -#define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /*!< ADC14SSEL Bit Mask */ -#define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /*!< SSEL Bit 0 */ -#define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /*!< SSEL Bit 1 */ -#define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /*!< SSEL Bit 2 */ -#define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /*!< HSMCLK */ -#define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /*!< HSMCLK */ -/* ADC14_CTL0[DIV] Bits */ -#define ADC14_CTL0_DIV_OFS (22) /*!< ADC14DIV Bit Offset */ -#define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /*!< ADC14DIV Bit Mask */ -#define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /*!< DIV Bit 0 */ -#define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /*!< DIV Bit 1 */ -#define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /*!< DIV Bit 2 */ -#define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /*!< /8 */ -#define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /*!< /8 */ -/* ADC14_CTL0[ISSH] Bits */ -#define ADC14_CTL0_ISSH_OFS (25) /*!< ADC14ISSH Bit Offset */ -#define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /*!< ADC14 invert signal sample-and-hold */ -/* ADC14_CTL0[SHP] Bits */ -#define ADC14_CTL0_SHP_OFS (26) /*!< ADC14SHP Bit Offset */ -#define ADC14_CTL0_SHP ((uint32_t)0x04000000) /*!< ADC14 sample-and-hold pulse-mode select */ -/* ADC14_CTL0[SHS] Bits */ -#define ADC14_CTL0_SHS_OFS (27) /*!< ADC14SHS Bit Offset */ -#define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /*!< ADC14SHS Bit Mask */ -#define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /*!< SHS Bit 0 */ -#define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /*!< SHS Bit 1 */ -#define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /*!< SHS Bit 2 */ -#define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /*!< ADC14SC bit */ -#define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /*!< See device-specific data sheet for source */ -/* ADC14_CTL0[PDIV] Bits */ -#define ADC14_CTL0_PDIV_OFS (30) /*!< ADC14PDIV Bit Offset */ -#define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /*!< ADC14PDIV Bit Mask */ -#define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /*!< PDIV Bit 0 */ -#define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /*!< PDIV Bit 1 */ -#define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -#define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -/* ADC14_CTL1[PWRMD] Bits */ -#define ADC14_CTL1_PWRMD_OFS ( 0) /*!< ADC14PWRMD Bit Offset */ -#define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /*!< ADC14PWRMD Bit Mask */ -#define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /*!< PWRMD Bit 0 */ -#define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /*!< PWRMD Bit 1 */ -#define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /*!< Regular power mode for use with any resolution setting. Sample rate can be */ - /* up to 1 Msps. */ -#define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample */ - /* rate must not exceed 200 ksps. */ -/* ADC14_CTL1[REFBURST] Bits */ -#define ADC14_CTL1_REFBURST_OFS ( 2) /*!< ADC14REFBURST Bit Offset */ -#define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /*!< ADC14 reference buffer burst */ -/* ADC14_CTL1[DF] Bits */ -#define ADC14_CTL1_DF_OFS ( 3) /*!< ADC14DF Bit Offset */ -#define ADC14_CTL1_DF ((uint32_t)0x00000008) /*!< ADC14 data read-back format */ -/* ADC14_CTL1[RES] Bits */ -#define ADC14_CTL1_RES_OFS ( 4) /*!< ADC14RES Bit Offset */ -#define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /*!< ADC14RES Bit Mask */ -#define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /*!< RES Bit 0 */ -#define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /*!< RES Bit 1 */ -#define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -#define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -/* ADC14_CTL1[CSTARTADD] Bits */ -#define ADC14_CTL1_CSTARTADD_OFS (16) /*!< ADC14CSTARTADD Bit Offset */ -#define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /*!< ADC14CSTARTADD Bit Mask */ -/* ADC14_CTL1[BATMAP] Bits */ -#define ADC14_CTL1_BATMAP_OFS (22) /*!< ADC14BATMAP Bit Offset */ -#define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /*!< Controls 1/2 AVCC ADC input channel selection */ -/* ADC14_CTL1[TCMAP] Bits */ -#define ADC14_CTL1_TCMAP_OFS (23) /*!< ADC14TCMAP Bit Offset */ -#define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /*!< Controls temperature sensor ADC input channel selection */ -/* ADC14_CTL1[CH0MAP] Bits */ -#define ADC14_CTL1_CH0MAP_OFS (24) /*!< ADC14CH0MAP Bit Offset */ -#define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */ -/* ADC14_CTL1[CH1MAP] Bits */ -#define ADC14_CTL1_CH1MAP_OFS (25) /*!< ADC14CH1MAP Bit Offset */ -#define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */ -/* ADC14_CTL1[CH2MAP] Bits */ -#define ADC14_CTL1_CH2MAP_OFS (26) /*!< ADC14CH2MAP Bit Offset */ -#define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */ -/* ADC14_CTL1[CH3MAP] Bits */ -#define ADC14_CTL1_CH3MAP_OFS (27) /*!< ADC14CH3MAP Bit Offset */ -#define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */ -/* ADC14_LO0[LO0] Bits */ -#define ADC14_LO0_LO0_OFS ( 0) /*!< ADC14LO0 Bit Offset */ -#define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO0 Bit Mask */ -/* ADC14_HI0[HI0] Bits */ -#define ADC14_HI0_HI0_OFS ( 0) /*!< ADC14HI0 Bit Offset */ -#define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI0 Bit Mask */ -/* ADC14_LO1[LO1] Bits */ -#define ADC14_LO1_LO1_OFS ( 0) /*!< ADC14LO1 Bit Offset */ -#define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO1 Bit Mask */ -/* ADC14_HI1[HI1] Bits */ -#define ADC14_HI1_HI1_OFS ( 0) /*!< ADC14HI1 Bit Offset */ -#define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI1 Bit Mask */ -/* ADC14_MCTLN[INCH] Bits */ -#define ADC14_MCTLN_INCH_OFS ( 0) /*!< ADC14INCH Bit Offset */ -#define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /*!< ADC14INCH Bit Mask */ -#define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /*!< INCH Bit 0 */ -#define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /*!< INCH Bit 1 */ -#define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /*!< INCH Bit 2 */ -#define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /*!< INCH Bit 3 */ -#define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /*!< INCH Bit 4 */ -#define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -#define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -/* ADC14_MCTLN[EOS] Bits */ -#define ADC14_MCTLN_EOS_OFS ( 7) /*!< ADC14EOS Bit Offset */ -#define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /*!< End of sequence */ -/* ADC14_MCTLN[VRSEL] Bits */ -#define ADC14_MCTLN_VRSEL_OFS ( 8) /*!< ADC14VRSEL Bit Offset */ -#define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /*!< ADC14VRSEL Bit Mask */ -#define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /*!< VRSEL Bit 0 */ -#define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /*!< VRSEL Bit 1 */ -#define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /*!< VRSEL Bit 2 */ -#define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /*!< VRSEL Bit 3 */ -#define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /*!< V(R+) = AVCC, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /*!< V(R+) = VREF buffered, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /*!< V(R+) = VeREF+, V(R-) = VeREF- */ -#define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */ -/* ADC14_MCTLN[DIF] Bits */ -#define ADC14_MCTLN_DIF_OFS (13) /*!< ADC14DIF Bit Offset */ -#define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /*!< Differential mode */ -/* ADC14_MCTLN[WINC] Bits */ -#define ADC14_MCTLN_WINC_OFS (14) /*!< ADC14WINC Bit Offset */ -#define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /*!< Comparator window enable */ -/* ADC14_MCTLN[WINCTH] Bits */ -#define ADC14_MCTLN_WINCTH_OFS (15) /*!< ADC14WINCTH Bit Offset */ -#define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /*!< Window comparator threshold register selection */ -/* ADC14_MEMN[CONVRES] Bits */ -#define ADC14_MEMN_CONVRES_OFS ( 0) /*!< Conversion_Results Bit Offset */ -#define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /*!< Conversion_Results Bit Mask */ -/* ADC14_IER0[IE0] Bits */ -#define ADC14_IER0_IE0_OFS ( 0) /*!< ADC14IE0 Bit Offset */ -#define ADC14_IER0_IE0 ((uint32_t)0x00000001) /*!< Interrupt enable */ -/* ADC14_IER0[IE1] Bits */ -#define ADC14_IER0_IE1_OFS ( 1) /*!< ADC14IE1 Bit Offset */ -#define ADC14_IER0_IE1 ((uint32_t)0x00000002) /*!< Interrupt enable */ -/* ADC14_IER0[IE2] Bits */ -#define ADC14_IER0_IE2_OFS ( 2) /*!< ADC14IE2 Bit Offset */ -#define ADC14_IER0_IE2 ((uint32_t)0x00000004) /*!< Interrupt enable */ -/* ADC14_IER0[IE3] Bits */ -#define ADC14_IER0_IE3_OFS ( 3) /*!< ADC14IE3 Bit Offset */ -#define ADC14_IER0_IE3 ((uint32_t)0x00000008) /*!< Interrupt enable */ -/* ADC14_IER0[IE4] Bits */ -#define ADC14_IER0_IE4_OFS ( 4) /*!< ADC14IE4 Bit Offset */ -#define ADC14_IER0_IE4 ((uint32_t)0x00000010) /*!< Interrupt enable */ -/* ADC14_IER0[IE5] Bits */ -#define ADC14_IER0_IE5_OFS ( 5) /*!< ADC14IE5 Bit Offset */ -#define ADC14_IER0_IE5 ((uint32_t)0x00000020) /*!< Interrupt enable */ -/* ADC14_IER0[IE6] Bits */ -#define ADC14_IER0_IE6_OFS ( 6) /*!< ADC14IE6 Bit Offset */ -#define ADC14_IER0_IE6 ((uint32_t)0x00000040) /*!< Interrupt enable */ -/* ADC14_IER0[IE7] Bits */ -#define ADC14_IER0_IE7_OFS ( 7) /*!< ADC14IE7 Bit Offset */ -#define ADC14_IER0_IE7 ((uint32_t)0x00000080) /*!< Interrupt enable */ -/* ADC14_IER0[IE8] Bits */ -#define ADC14_IER0_IE8_OFS ( 8) /*!< ADC14IE8 Bit Offset */ -#define ADC14_IER0_IE8 ((uint32_t)0x00000100) /*!< Interrupt enable */ -/* ADC14_IER0[IE9] Bits */ -#define ADC14_IER0_IE9_OFS ( 9) /*!< ADC14IE9 Bit Offset */ -#define ADC14_IER0_IE9 ((uint32_t)0x00000200) /*!< Interrupt enable */ -/* ADC14_IER0[IE10] Bits */ -#define ADC14_IER0_IE10_OFS (10) /*!< ADC14IE10 Bit Offset */ -#define ADC14_IER0_IE10 ((uint32_t)0x00000400) /*!< Interrupt enable */ -/* ADC14_IER0[IE11] Bits */ -#define ADC14_IER0_IE11_OFS (11) /*!< ADC14IE11 Bit Offset */ -#define ADC14_IER0_IE11 ((uint32_t)0x00000800) /*!< Interrupt enable */ -/* ADC14_IER0[IE12] Bits */ -#define ADC14_IER0_IE12_OFS (12) /*!< ADC14IE12 Bit Offset */ -#define ADC14_IER0_IE12 ((uint32_t)0x00001000) /*!< Interrupt enable */ -/* ADC14_IER0[IE13] Bits */ -#define ADC14_IER0_IE13_OFS (13) /*!< ADC14IE13 Bit Offset */ -#define ADC14_IER0_IE13 ((uint32_t)0x00002000) /*!< Interrupt enable */ -/* ADC14_IER0[IE14] Bits */ -#define ADC14_IER0_IE14_OFS (14) /*!< ADC14IE14 Bit Offset */ -#define ADC14_IER0_IE14 ((uint32_t)0x00004000) /*!< Interrupt enable */ -/* ADC14_IER0[IE15] Bits */ -#define ADC14_IER0_IE15_OFS (15) /*!< ADC14IE15 Bit Offset */ -#define ADC14_IER0_IE15 ((uint32_t)0x00008000) /*!< Interrupt enable */ -/* ADC14_IER0[IE16] Bits */ -#define ADC14_IER0_IE16_OFS (16) /*!< ADC14IE16 Bit Offset */ -#define ADC14_IER0_IE16 ((uint32_t)0x00010000) /*!< Interrupt enable */ -/* ADC14_IER0[IE17] Bits */ -#define ADC14_IER0_IE17_OFS (17) /*!< ADC14IE17 Bit Offset */ -#define ADC14_IER0_IE17 ((uint32_t)0x00020000) /*!< Interrupt enable */ -/* ADC14_IER0[IE19] Bits */ -#define ADC14_IER0_IE19_OFS (19) /*!< ADC14IE19 Bit Offset */ -#define ADC14_IER0_IE19 ((uint32_t)0x00080000) /*!< Interrupt enable */ -/* ADC14_IER0[IE18] Bits */ -#define ADC14_IER0_IE18_OFS (18) /*!< ADC14IE18 Bit Offset */ -#define ADC14_IER0_IE18 ((uint32_t)0x00040000) /*!< Interrupt enable */ -/* ADC14_IER0[IE20] Bits */ -#define ADC14_IER0_IE20_OFS (20) /*!< ADC14IE20 Bit Offset */ -#define ADC14_IER0_IE20 ((uint32_t)0x00100000) /*!< Interrupt enable */ -/* ADC14_IER0[IE21] Bits */ -#define ADC14_IER0_IE21_OFS (21) /*!< ADC14IE21 Bit Offset */ -#define ADC14_IER0_IE21 ((uint32_t)0x00200000) /*!< Interrupt enable */ -/* ADC14_IER0[IE22] Bits */ -#define ADC14_IER0_IE22_OFS (22) /*!< ADC14IE22 Bit Offset */ -#define ADC14_IER0_IE22 ((uint32_t)0x00400000) /*!< Interrupt enable */ -/* ADC14_IER0[IE23] Bits */ -#define ADC14_IER0_IE23_OFS (23) /*!< ADC14IE23 Bit Offset */ -#define ADC14_IER0_IE23 ((uint32_t)0x00800000) /*!< Interrupt enable */ -/* ADC14_IER0[IE24] Bits */ -#define ADC14_IER0_IE24_OFS (24) /*!< ADC14IE24 Bit Offset */ -#define ADC14_IER0_IE24 ((uint32_t)0x01000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE25] Bits */ -#define ADC14_IER0_IE25_OFS (25) /*!< ADC14IE25 Bit Offset */ -#define ADC14_IER0_IE25 ((uint32_t)0x02000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE26] Bits */ -#define ADC14_IER0_IE26_OFS (26) /*!< ADC14IE26 Bit Offset */ -#define ADC14_IER0_IE26 ((uint32_t)0x04000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE27] Bits */ -#define ADC14_IER0_IE27_OFS (27) /*!< ADC14IE27 Bit Offset */ -#define ADC14_IER0_IE27 ((uint32_t)0x08000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE28] Bits */ -#define ADC14_IER0_IE28_OFS (28) /*!< ADC14IE28 Bit Offset */ -#define ADC14_IER0_IE28 ((uint32_t)0x10000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE29] Bits */ -#define ADC14_IER0_IE29_OFS (29) /*!< ADC14IE29 Bit Offset */ -#define ADC14_IER0_IE29 ((uint32_t)0x20000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE30] Bits */ -#define ADC14_IER0_IE30_OFS (30) /*!< ADC14IE30 Bit Offset */ -#define ADC14_IER0_IE30 ((uint32_t)0x40000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE31] Bits */ -#define ADC14_IER0_IE31_OFS (31) /*!< ADC14IE31 Bit Offset */ -#define ADC14_IER0_IE31 ((uint32_t)0x80000000) /*!< Interrupt enable */ -/* ADC14_IER1[INIE] Bits */ -#define ADC14_IER1_INIE_OFS ( 1) /*!< ADC14INIE Bit Offset */ -#define ADC14_IER1_INIE ((uint32_t)0x00000002) /*!< Interrupt enable for ADC14MEMx within comparator window */ -/* ADC14_IER1[LOIE] Bits */ -#define ADC14_IER1_LOIE_OFS ( 2) /*!< ADC14LOIE Bit Offset */ -#define ADC14_IER1_LOIE ((uint32_t)0x00000004) /*!< Interrupt enable for ADC14MEMx below comparator window */ -/* ADC14_IER1[HIIE] Bits */ -#define ADC14_IER1_HIIE_OFS ( 3) /*!< ADC14HIIE Bit Offset */ -#define ADC14_IER1_HIIE ((uint32_t)0x00000008) /*!< Interrupt enable for ADC14MEMx above comparator window */ -/* ADC14_IER1[OVIE] Bits */ -#define ADC14_IER1_OVIE_OFS ( 4) /*!< ADC14OVIE Bit Offset */ -#define ADC14_IER1_OVIE ((uint32_t)0x00000010) /*!< ADC14MEMx overflow-interrupt enable */ -/* ADC14_IER1[TOVIE] Bits */ -#define ADC14_IER1_TOVIE_OFS ( 5) /*!< ADC14TOVIE Bit Offset */ -#define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /*!< ADC14 conversion-time-overflow interrupt enable */ -/* ADC14_IER1[RDYIE] Bits */ -#define ADC14_IER1_RDYIE_OFS ( 6) /*!< ADC14RDYIE Bit Offset */ -#define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt enable */ -/* ADC14_IFGR0[IFG0] Bits */ -#define ADC14_IFGR0_IFG0_OFS ( 0) /*!< ADC14IFG0 Bit Offset */ -#define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /*!< ADC14MEM0 interrupt flag */ -/* ADC14_IFGR0[IFG1] Bits */ -#define ADC14_IFGR0_IFG1_OFS ( 1) /*!< ADC14IFG1 Bit Offset */ -#define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /*!< ADC14MEM1 interrupt flag */ -/* ADC14_IFGR0[IFG2] Bits */ -#define ADC14_IFGR0_IFG2_OFS ( 2) /*!< ADC14IFG2 Bit Offset */ -#define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /*!< ADC14MEM2 interrupt flag */ -/* ADC14_IFGR0[IFG3] Bits */ -#define ADC14_IFGR0_IFG3_OFS ( 3) /*!< ADC14IFG3 Bit Offset */ -#define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /*!< ADC14MEM3 interrupt flag */ -/* ADC14_IFGR0[IFG4] Bits */ -#define ADC14_IFGR0_IFG4_OFS ( 4) /*!< ADC14IFG4 Bit Offset */ -#define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /*!< ADC14MEM4 interrupt flag */ -/* ADC14_IFGR0[IFG5] Bits */ -#define ADC14_IFGR0_IFG5_OFS ( 5) /*!< ADC14IFG5 Bit Offset */ -#define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /*!< ADC14MEM5 interrupt flag */ -/* ADC14_IFGR0[IFG6] Bits */ -#define ADC14_IFGR0_IFG6_OFS ( 6) /*!< ADC14IFG6 Bit Offset */ -#define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /*!< ADC14MEM6 interrupt flag */ -/* ADC14_IFGR0[IFG7] Bits */ -#define ADC14_IFGR0_IFG7_OFS ( 7) /*!< ADC14IFG7 Bit Offset */ -#define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /*!< ADC14MEM7 interrupt flag */ -/* ADC14_IFGR0[IFG8] Bits */ -#define ADC14_IFGR0_IFG8_OFS ( 8) /*!< ADC14IFG8 Bit Offset */ -#define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /*!< ADC14MEM8 interrupt flag */ -/* ADC14_IFGR0[IFG9] Bits */ -#define ADC14_IFGR0_IFG9_OFS ( 9) /*!< ADC14IFG9 Bit Offset */ -#define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /*!< ADC14MEM9 interrupt flag */ -/* ADC14_IFGR0[IFG10] Bits */ -#define ADC14_IFGR0_IFG10_OFS (10) /*!< ADC14IFG10 Bit Offset */ -#define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /*!< ADC14MEM10 interrupt flag */ -/* ADC14_IFGR0[IFG11] Bits */ -#define ADC14_IFGR0_IFG11_OFS (11) /*!< ADC14IFG11 Bit Offset */ -#define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /*!< ADC14MEM11 interrupt flag */ -/* ADC14_IFGR0[IFG12] Bits */ -#define ADC14_IFGR0_IFG12_OFS (12) /*!< ADC14IFG12 Bit Offset */ -#define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /*!< ADC14MEM12 interrupt flag */ -/* ADC14_IFGR0[IFG13] Bits */ -#define ADC14_IFGR0_IFG13_OFS (13) /*!< ADC14IFG13 Bit Offset */ -#define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /*!< ADC14MEM13 interrupt flag */ -/* ADC14_IFGR0[IFG14] Bits */ -#define ADC14_IFGR0_IFG14_OFS (14) /*!< ADC14IFG14 Bit Offset */ -#define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /*!< ADC14MEM14 interrupt flag */ -/* ADC14_IFGR0[IFG15] Bits */ -#define ADC14_IFGR0_IFG15_OFS (15) /*!< ADC14IFG15 Bit Offset */ -#define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /*!< ADC14MEM15 interrupt flag */ -/* ADC14_IFGR0[IFG16] Bits */ -#define ADC14_IFGR0_IFG16_OFS (16) /*!< ADC14IFG16 Bit Offset */ -#define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /*!< ADC14MEM16 interrupt flag */ -/* ADC14_IFGR0[IFG17] Bits */ -#define ADC14_IFGR0_IFG17_OFS (17) /*!< ADC14IFG17 Bit Offset */ -#define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /*!< ADC14MEM17 interrupt flag */ -/* ADC14_IFGR0[IFG18] Bits */ -#define ADC14_IFGR0_IFG18_OFS (18) /*!< ADC14IFG18 Bit Offset */ -#define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /*!< ADC14MEM18 interrupt flag */ -/* ADC14_IFGR0[IFG19] Bits */ -#define ADC14_IFGR0_IFG19_OFS (19) /*!< ADC14IFG19 Bit Offset */ -#define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /*!< ADC14MEM19 interrupt flag */ -/* ADC14_IFGR0[IFG20] Bits */ -#define ADC14_IFGR0_IFG20_OFS (20) /*!< ADC14IFG20 Bit Offset */ -#define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /*!< ADC14MEM20 interrupt flag */ -/* ADC14_IFGR0[IFG21] Bits */ -#define ADC14_IFGR0_IFG21_OFS (21) /*!< ADC14IFG21 Bit Offset */ -#define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /*!< ADC14MEM21 interrupt flag */ -/* ADC14_IFGR0[IFG22] Bits */ -#define ADC14_IFGR0_IFG22_OFS (22) /*!< ADC14IFG22 Bit Offset */ -#define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /*!< ADC14MEM22 interrupt flag */ -/* ADC14_IFGR0[IFG23] Bits */ -#define ADC14_IFGR0_IFG23_OFS (23) /*!< ADC14IFG23 Bit Offset */ -#define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /*!< ADC14MEM23 interrupt flag */ -/* ADC14_IFGR0[IFG24] Bits */ -#define ADC14_IFGR0_IFG24_OFS (24) /*!< ADC14IFG24 Bit Offset */ -#define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /*!< ADC14MEM24 interrupt flag */ -/* ADC14_IFGR0[IFG25] Bits */ -#define ADC14_IFGR0_IFG25_OFS (25) /*!< ADC14IFG25 Bit Offset */ -#define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /*!< ADC14MEM25 interrupt flag */ -/* ADC14_IFGR0[IFG26] Bits */ -#define ADC14_IFGR0_IFG26_OFS (26) /*!< ADC14IFG26 Bit Offset */ -#define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /*!< ADC14MEM26 interrupt flag */ -/* ADC14_IFGR0[IFG27] Bits */ -#define ADC14_IFGR0_IFG27_OFS (27) /*!< ADC14IFG27 Bit Offset */ -#define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /*!< ADC14MEM27 interrupt flag */ -/* ADC14_IFGR0[IFG28] Bits */ -#define ADC14_IFGR0_IFG28_OFS (28) /*!< ADC14IFG28 Bit Offset */ -#define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /*!< ADC14MEM28 interrupt flag */ -/* ADC14_IFGR0[IFG29] Bits */ -#define ADC14_IFGR0_IFG29_OFS (29) /*!< ADC14IFG29 Bit Offset */ -#define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /*!< ADC14MEM29 interrupt flag */ -/* ADC14_IFGR0[IFG30] Bits */ -#define ADC14_IFGR0_IFG30_OFS (30) /*!< ADC14IFG30 Bit Offset */ -#define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /*!< ADC14MEM30 interrupt flag */ -/* ADC14_IFGR0[IFG31] Bits */ -#define ADC14_IFGR0_IFG31_OFS (31) /*!< ADC14IFG31 Bit Offset */ -#define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /*!< ADC14MEM31 interrupt flag */ -/* ADC14_IFGR1[INIFG] Bits */ -#define ADC14_IFGR1_INIFG_OFS ( 1) /*!< ADC14INIFG Bit Offset */ -#define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /*!< Interrupt flag for ADC14MEMx within comparator window */ -/* ADC14_IFGR1[LOIFG] Bits */ -#define ADC14_IFGR1_LOIFG_OFS ( 2) /*!< ADC14LOIFG Bit Offset */ -#define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /*!< Interrupt flag for ADC14MEMx below comparator window */ -/* ADC14_IFGR1[HIIFG] Bits */ -#define ADC14_IFGR1_HIIFG_OFS ( 3) /*!< ADC14HIIFG Bit Offset */ -#define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /*!< Interrupt flag for ADC14MEMx above comparator window */ -/* ADC14_IFGR1[OVIFG] Bits */ -#define ADC14_IFGR1_OVIFG_OFS ( 4) /*!< ADC14OVIFG Bit Offset */ -#define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /*!< ADC14MEMx overflow interrupt flag */ -/* ADC14_IFGR1[TOVIFG] Bits */ -#define ADC14_IFGR1_TOVIFG_OFS ( 5) /*!< ADC14TOVIFG Bit Offset */ -#define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /*!< ADC14 conversion time overflow interrupt flag */ -/* ADC14_IFGR1[RDYIFG] Bits */ -#define ADC14_IFGR1_RDYIFG_OFS ( 6) /*!< ADC14RDYIFG Bit Offset */ -#define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt flag */ -/* ADC14_CLRIFGR0[CLRIFG0] Bits */ -#define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /*!< CLRADC14IFG0 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /*!< clear ADC14IFG0 */ -/* ADC14_CLRIFGR0[CLRIFG1] Bits */ -#define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /*!< CLRADC14IFG1 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /*!< clear ADC14IFG1 */ -/* ADC14_CLRIFGR0[CLRIFG2] Bits */ -#define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /*!< CLRADC14IFG2 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /*!< clear ADC14IFG2 */ -/* ADC14_CLRIFGR0[CLRIFG3] Bits */ -#define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /*!< CLRADC14IFG3 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /*!< clear ADC14IFG3 */ -/* ADC14_CLRIFGR0[CLRIFG4] Bits */ -#define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /*!< CLRADC14IFG4 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /*!< clear ADC14IFG4 */ -/* ADC14_CLRIFGR0[CLRIFG5] Bits */ -#define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /*!< CLRADC14IFG5 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /*!< clear ADC14IFG5 */ -/* ADC14_CLRIFGR0[CLRIFG6] Bits */ -#define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /*!< CLRADC14IFG6 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /*!< clear ADC14IFG6 */ -/* ADC14_CLRIFGR0[CLRIFG7] Bits */ -#define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /*!< CLRADC14IFG7 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /*!< clear ADC14IFG7 */ -/* ADC14_CLRIFGR0[CLRIFG8] Bits */ -#define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /*!< CLRADC14IFG8 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /*!< clear ADC14IFG8 */ -/* ADC14_CLRIFGR0[CLRIFG9] Bits */ -#define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /*!< CLRADC14IFG9 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /*!< clear ADC14IFG9 */ -/* ADC14_CLRIFGR0[CLRIFG10] Bits */ -#define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /*!< CLRADC14IFG10 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /*!< clear ADC14IFG10 */ -/* ADC14_CLRIFGR0[CLRIFG11] Bits */ -#define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /*!< CLRADC14IFG11 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /*!< clear ADC14IFG11 */ -/* ADC14_CLRIFGR0[CLRIFG12] Bits */ -#define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /*!< CLRADC14IFG12 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /*!< clear ADC14IFG12 */ -/* ADC14_CLRIFGR0[CLRIFG13] Bits */ -#define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /*!< CLRADC14IFG13 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /*!< clear ADC14IFG13 */ -/* ADC14_CLRIFGR0[CLRIFG14] Bits */ -#define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /*!< CLRADC14IFG14 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /*!< clear ADC14IFG14 */ -/* ADC14_CLRIFGR0[CLRIFG15] Bits */ -#define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /*!< CLRADC14IFG15 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /*!< clear ADC14IFG15 */ -/* ADC14_CLRIFGR0[CLRIFG16] Bits */ -#define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /*!< CLRADC14IFG16 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /*!< clear ADC14IFG16 */ -/* ADC14_CLRIFGR0[CLRIFG17] Bits */ -#define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /*!< CLRADC14IFG17 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /*!< clear ADC14IFG17 */ -/* ADC14_CLRIFGR0[CLRIFG18] Bits */ -#define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /*!< CLRADC14IFG18 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /*!< clear ADC14IFG18 */ -/* ADC14_CLRIFGR0[CLRIFG19] Bits */ -#define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /*!< CLRADC14IFG19 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /*!< clear ADC14IFG19 */ -/* ADC14_CLRIFGR0[CLRIFG20] Bits */ -#define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /*!< CLRADC14IFG20 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /*!< clear ADC14IFG20 */ -/* ADC14_CLRIFGR0[CLRIFG21] Bits */ -#define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /*!< CLRADC14IFG21 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /*!< clear ADC14IFG21 */ -/* ADC14_CLRIFGR0[CLRIFG22] Bits */ -#define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /*!< CLRADC14IFG22 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /*!< clear ADC14IFG22 */ -/* ADC14_CLRIFGR0[CLRIFG23] Bits */ -#define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /*!< CLRADC14IFG23 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /*!< clear ADC14IFG23 */ -/* ADC14_CLRIFGR0[CLRIFG24] Bits */ -#define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /*!< CLRADC14IFG24 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /*!< clear ADC14IFG24 */ -/* ADC14_CLRIFGR0[CLRIFG25] Bits */ -#define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /*!< CLRADC14IFG25 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /*!< clear ADC14IFG25 */ -/* ADC14_CLRIFGR0[CLRIFG26] Bits */ -#define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /*!< CLRADC14IFG26 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /*!< clear ADC14IFG26 */ -/* ADC14_CLRIFGR0[CLRIFG27] Bits */ -#define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /*!< CLRADC14IFG27 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /*!< clear ADC14IFG27 */ -/* ADC14_CLRIFGR0[CLRIFG28] Bits */ -#define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /*!< CLRADC14IFG28 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /*!< clear ADC14IFG28 */ -/* ADC14_CLRIFGR0[CLRIFG29] Bits */ -#define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /*!< CLRADC14IFG29 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /*!< clear ADC14IFG29 */ -/* ADC14_CLRIFGR0[CLRIFG30] Bits */ -#define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /*!< CLRADC14IFG30 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /*!< clear ADC14IFG30 */ -/* ADC14_CLRIFGR0[CLRIFG31] Bits */ -#define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /*!< CLRADC14IFG31 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /*!< clear ADC14IFG31 */ -/* ADC14_CLRIFGR1[CLRINIFG] Bits */ -#define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /*!< CLRADC14INIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /*!< clear ADC14INIFG */ -/* ADC14_CLRIFGR1[CLRLOIFG] Bits */ -#define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /*!< CLRADC14LOIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /*!< clear ADC14LOIFG */ -/* ADC14_CLRIFGR1[CLRHIIFG] Bits */ -#define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /*!< CLRADC14HIIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /*!< clear ADC14HIIFG */ -/* ADC14_CLRIFGR1[CLROVIFG] Bits */ -#define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /*!< CLRADC14OVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /*!< clear ADC14OVIFG */ -/* ADC14_CLRIFGR1[CLRTOVIFG] Bits */ -#define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /*!< CLRADC14TOVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /*!< clear ADC14TOVIFG */ -/* ADC14_CLRIFGR1[CLRRDYIFG] Bits */ -#define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /*!< CLRADC14RDYIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /*!< clear ADC14RDYIFG */ - -/****************************************************************************** -* AES256 Bits -******************************************************************************/ -/* AES256_CTL0[OP] Bits */ -#define AES256_CTL0_OP_OFS ( 0) /*!< AESOPx Bit Offset */ -#define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /*!< AESOPx Bit Mask */ -#define AES256_CTL0_OP0 ((uint16_t)0x0001) /*!< OP Bit 0 */ -#define AES256_CTL0_OP1 ((uint16_t)0x0002) /*!< OP Bit 1 */ -#define AES256_CTL0_OP_0 ((uint16_t)0x0000) /*!< Encryption */ -#define AES256_CTL0_OP_1 ((uint16_t)0x0001) /*!< Decryption. The provided key is the same key used for encryption */ -#define AES256_CTL0_OP_2 ((uint16_t)0x0002) /*!< Generate first round key required for decryption */ -#define AES256_CTL0_OP_3 ((uint16_t)0x0003) /*!< Decryption. The provided key is the first round key required for decryption */ -/* AES256_CTL0[KL] Bits */ -#define AES256_CTL0_KL_OFS ( 2) /*!< AESKLx Bit Offset */ -#define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /*!< AESKLx Bit Mask */ -#define AES256_CTL0_KL0 ((uint16_t)0x0004) /*!< KL Bit 0 */ -#define AES256_CTL0_KL1 ((uint16_t)0x0008) /*!< KL Bit 1 */ -#define AES256_CTL0_KL_0 ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL_1 ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL_2 ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -#define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -/* AES256_CTL0[CM] Bits */ -#define AES256_CTL0_CM_OFS ( 5) /*!< AESCMx Bit Offset */ -#define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /*!< AESCMx Bit Mask */ -#define AES256_CTL0_CM0 ((uint16_t)0x0020) /*!< CM Bit 0 */ -#define AES256_CTL0_CM1 ((uint16_t)0x0040) /*!< CM Bit 1 */ -#define AES256_CTL0_CM_0 ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM_1 ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM_2 ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM_3 ((uint16_t)0x0060) /*!< CFB */ -#define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /*!< CFB */ -/* AES256_CTL0[SWRST] Bits */ -#define AES256_CTL0_SWRST_OFS ( 7) /*!< AESSWRST Bit Offset */ -#define AES256_CTL0_SWRST ((uint16_t)0x0080) /*!< AES software reset */ -/* AES256_CTL0[RDYIFG] Bits */ -#define AES256_CTL0_RDYIFG_OFS ( 8) /*!< AESRDYIFG Bit Offset */ -#define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /*!< AES ready interrupt flag */ -/* AES256_CTL0[ERRFG] Bits */ -#define AES256_CTL0_ERRFG_OFS (11) /*!< AESERRFG Bit Offset */ -#define AES256_CTL0_ERRFG ((uint16_t)0x0800) /*!< AES error flag */ -/* AES256_CTL0[RDYIE] Bits */ -#define AES256_CTL0_RDYIE_OFS (12) /*!< AESRDYIE Bit Offset */ -#define AES256_CTL0_RDYIE ((uint16_t)0x1000) /*!< AES ready interrupt enable */ -/* AES256_CTL0[CMEN] Bits */ -#define AES256_CTL0_CMEN_OFS (15) /*!< AESCMEN Bit Offset */ -#define AES256_CTL0_CMEN ((uint16_t)0x8000) /*!< AES cipher mode enable */ -/* AES256_CTL1[BLKCNT] Bits */ -#define AES256_CTL1_BLKCNT_OFS ( 0) /*!< AESBLKCNTx Bit Offset */ -#define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /*!< AESBLKCNTx Bit Mask */ -#define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /*!< BLKCNT Bit 0 */ -#define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /*!< BLKCNT Bit 1 */ -#define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /*!< BLKCNT Bit 2 */ -#define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /*!< BLKCNT Bit 3 */ -#define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /*!< BLKCNT Bit 4 */ -#define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /*!< BLKCNT Bit 5 */ -#define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /*!< BLKCNT Bit 6 */ -#define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /*!< BLKCNT Bit 7 */ -/* AES256_STAT[BUSY] Bits */ -#define AES256_STAT_BUSY_OFS ( 0) /*!< AESBUSY Bit Offset */ -#define AES256_STAT_BUSY ((uint16_t)0x0001) /*!< AES accelerator module busy */ -/* AES256_STAT[KEYWR] Bits */ -#define AES256_STAT_KEYWR_OFS ( 1) /*!< AESKEYWR Bit Offset */ -#define AES256_STAT_KEYWR ((uint16_t)0x0002) /*!< All 16 bytes written to AESAKEY */ -/* AES256_STAT[DINWR] Bits */ -#define AES256_STAT_DINWR_OFS ( 2) /*!< AESDINWR Bit Offset */ -#define AES256_STAT_DINWR ((uint16_t)0x0004) /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ -/* AES256_STAT[DOUTRD] Bits */ -#define AES256_STAT_DOUTRD_OFS ( 3) /*!< AESDOUTRD Bit Offset */ -#define AES256_STAT_DOUTRD ((uint16_t)0x0008) /*!< All 16 bytes read from AESADOUT */ -/* AES256_STAT[KEYCNT] Bits */ -#define AES256_STAT_KEYCNT_OFS ( 4) /*!< AESKEYCNTx Bit Offset */ -#define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /*!< AESKEYCNTx Bit Mask */ -#define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /*!< KEYCNT Bit 0 */ -#define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /*!< KEYCNT Bit 1 */ -#define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /*!< KEYCNT Bit 2 */ -#define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /*!< KEYCNT Bit 3 */ -/* AES256_STAT[DINCNT] Bits */ -#define AES256_STAT_DINCNT_OFS ( 8) /*!< AESDINCNTx Bit Offset */ -#define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /*!< AESDINCNTx Bit Mask */ -#define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /*!< DINCNT Bit 0 */ -#define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /*!< DINCNT Bit 1 */ -#define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /*!< DINCNT Bit 2 */ -#define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /*!< DINCNT Bit 3 */ -/* AES256_STAT[DOUTCNT] Bits */ -#define AES256_STAT_DOUTCNT_OFS (12) /*!< AESDOUTCNTx Bit Offset */ -#define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /*!< AESDOUTCNTx Bit Mask */ -#define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /*!< DOUTCNT Bit 0 */ -#define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /*!< DOUTCNT Bit 1 */ -#define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /*!< DOUTCNT Bit 2 */ -#define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /*!< DOUTCNT Bit 3 */ -/* AES256_KEY[KEY0] Bits */ -#define AES256_KEY_KEY0_OFS ( 0) /*!< AESKEY0x Bit Offset */ -#define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /*!< AESKEY0x Bit Mask */ -#define AES256_KEY_KEY00 ((uint16_t)0x0001) /*!< KEY0 Bit 0 */ -#define AES256_KEY_KEY01 ((uint16_t)0x0002) /*!< KEY0 Bit 1 */ -#define AES256_KEY_KEY02 ((uint16_t)0x0004) /*!< KEY0 Bit 2 */ -#define AES256_KEY_KEY03 ((uint16_t)0x0008) /*!< KEY0 Bit 3 */ -#define AES256_KEY_KEY04 ((uint16_t)0x0010) /*!< KEY0 Bit 4 */ -#define AES256_KEY_KEY05 ((uint16_t)0x0020) /*!< KEY0 Bit 5 */ -#define AES256_KEY_KEY06 ((uint16_t)0x0040) /*!< KEY0 Bit 6 */ -#define AES256_KEY_KEY07 ((uint16_t)0x0080) /*!< KEY0 Bit 7 */ -/* AES256_KEY[KEY1] Bits */ -#define AES256_KEY_KEY1_OFS ( 8) /*!< AESKEY1x Bit Offset */ -#define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /*!< AESKEY1x Bit Mask */ -#define AES256_KEY_KEY10 ((uint16_t)0x0100) /*!< KEY1 Bit 0 */ -#define AES256_KEY_KEY11 ((uint16_t)0x0200) /*!< KEY1 Bit 1 */ -#define AES256_KEY_KEY12 ((uint16_t)0x0400) /*!< KEY1 Bit 2 */ -#define AES256_KEY_KEY13 ((uint16_t)0x0800) /*!< KEY1 Bit 3 */ -#define AES256_KEY_KEY14 ((uint16_t)0x1000) /*!< KEY1 Bit 4 */ -#define AES256_KEY_KEY15 ((uint16_t)0x2000) /*!< KEY1 Bit 5 */ -#define AES256_KEY_KEY16 ((uint16_t)0x4000) /*!< KEY1 Bit 6 */ -#define AES256_KEY_KEY17 ((uint16_t)0x8000) /*!< KEY1 Bit 7 */ -/* AES256_DIN[DIN0] Bits */ -#define AES256_DIN_DIN0_OFS ( 0) /*!< AESDIN0x Bit Offset */ -#define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /*!< AESDIN0x Bit Mask */ -#define AES256_DIN_DIN00 ((uint16_t)0x0001) /*!< DIN0 Bit 0 */ -#define AES256_DIN_DIN01 ((uint16_t)0x0002) /*!< DIN0 Bit 1 */ -#define AES256_DIN_DIN02 ((uint16_t)0x0004) /*!< DIN0 Bit 2 */ -#define AES256_DIN_DIN03 ((uint16_t)0x0008) /*!< DIN0 Bit 3 */ -#define AES256_DIN_DIN04 ((uint16_t)0x0010) /*!< DIN0 Bit 4 */ -#define AES256_DIN_DIN05 ((uint16_t)0x0020) /*!< DIN0 Bit 5 */ -#define AES256_DIN_DIN06 ((uint16_t)0x0040) /*!< DIN0 Bit 6 */ -#define AES256_DIN_DIN07 ((uint16_t)0x0080) /*!< DIN0 Bit 7 */ -/* AES256_DIN[DIN1] Bits */ -#define AES256_DIN_DIN1_OFS ( 8) /*!< AESDIN1x Bit Offset */ -#define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /*!< AESDIN1x Bit Mask */ -#define AES256_DIN_DIN10 ((uint16_t)0x0100) /*!< DIN1 Bit 0 */ -#define AES256_DIN_DIN11 ((uint16_t)0x0200) /*!< DIN1 Bit 1 */ -#define AES256_DIN_DIN12 ((uint16_t)0x0400) /*!< DIN1 Bit 2 */ -#define AES256_DIN_DIN13 ((uint16_t)0x0800) /*!< DIN1 Bit 3 */ -#define AES256_DIN_DIN14 ((uint16_t)0x1000) /*!< DIN1 Bit 4 */ -#define AES256_DIN_DIN15 ((uint16_t)0x2000) /*!< DIN1 Bit 5 */ -#define AES256_DIN_DIN16 ((uint16_t)0x4000) /*!< DIN1 Bit 6 */ -#define AES256_DIN_DIN17 ((uint16_t)0x8000) /*!< DIN1 Bit 7 */ -/* AES256_DOUT[DOUT0] Bits */ -#define AES256_DOUT_DOUT0_OFS ( 0) /*!< AESDOUT0x Bit Offset */ -#define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /*!< AESDOUT0x Bit Mask */ -#define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /*!< DOUT0 Bit 0 */ -#define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /*!< DOUT0 Bit 1 */ -#define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /*!< DOUT0 Bit 2 */ -#define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /*!< DOUT0 Bit 3 */ -#define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /*!< DOUT0 Bit 4 */ -#define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /*!< DOUT0 Bit 5 */ -#define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /*!< DOUT0 Bit 6 */ -#define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /*!< DOUT0 Bit 7 */ -/* AES256_DOUT[DOUT1] Bits */ -#define AES256_DOUT_DOUT1_OFS ( 8) /*!< AESDOUT1x Bit Offset */ -#define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /*!< AESDOUT1x Bit Mask */ -#define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /*!< DOUT1 Bit 0 */ -#define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /*!< DOUT1 Bit 1 */ -#define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /*!< DOUT1 Bit 2 */ -#define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /*!< DOUT1 Bit 3 */ -#define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /*!< DOUT1 Bit 4 */ -#define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /*!< DOUT1 Bit 5 */ -#define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /*!< DOUT1 Bit 6 */ -#define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /*!< DOUT1 Bit 7 */ -/* AES256_XDIN[XDIN0] Bits */ -#define AES256_XDIN_XDIN0_OFS ( 0) /*!< AESXDIN0x Bit Offset */ -#define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /*!< AESXDIN0x Bit Mask */ -#define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /*!< XDIN0 Bit 0 */ -#define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /*!< XDIN0 Bit 1 */ -#define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /*!< XDIN0 Bit 2 */ -#define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /*!< XDIN0 Bit 3 */ -#define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /*!< XDIN0 Bit 4 */ -#define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /*!< XDIN0 Bit 5 */ -#define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /*!< XDIN0 Bit 6 */ -#define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /*!< XDIN0 Bit 7 */ -/* AES256_XDIN[XDIN1] Bits */ -#define AES256_XDIN_XDIN1_OFS ( 8) /*!< AESXDIN1x Bit Offset */ -#define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /*!< AESXDIN1x Bit Mask */ -#define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /*!< XDIN1 Bit 0 */ -#define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /*!< XDIN1 Bit 1 */ -#define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /*!< XDIN1 Bit 2 */ -#define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /*!< XDIN1 Bit 3 */ -#define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /*!< XDIN1 Bit 4 */ -#define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /*!< XDIN1 Bit 5 */ -#define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /*!< XDIN1 Bit 6 */ -#define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /*!< XDIN1 Bit 7 */ -/* AES256_XIN[XIN0] Bits */ -#define AES256_XIN_XIN0_OFS ( 0) /*!< AESXIN0x Bit Offset */ -#define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /*!< AESXIN0x Bit Mask */ -#define AES256_XIN_XIN00 ((uint16_t)0x0001) /*!< XIN0 Bit 0 */ -#define AES256_XIN_XIN01 ((uint16_t)0x0002) /*!< XIN0 Bit 1 */ -#define AES256_XIN_XIN02 ((uint16_t)0x0004) /*!< XIN0 Bit 2 */ -#define AES256_XIN_XIN03 ((uint16_t)0x0008) /*!< XIN0 Bit 3 */ -#define AES256_XIN_XIN04 ((uint16_t)0x0010) /*!< XIN0 Bit 4 */ -#define AES256_XIN_XIN05 ((uint16_t)0x0020) /*!< XIN0 Bit 5 */ -#define AES256_XIN_XIN06 ((uint16_t)0x0040) /*!< XIN0 Bit 6 */ -#define AES256_XIN_XIN07 ((uint16_t)0x0080) /*!< XIN0 Bit 7 */ -/* AES256_XIN[XIN1] Bits */ -#define AES256_XIN_XIN1_OFS ( 8) /*!< AESXIN1x Bit Offset */ -#define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /*!< AESXIN1x Bit Mask */ -#define AES256_XIN_XIN10 ((uint16_t)0x0100) /*!< XIN1 Bit 0 */ -#define AES256_XIN_XIN11 ((uint16_t)0x0200) /*!< XIN1 Bit 1 */ -#define AES256_XIN_XIN12 ((uint16_t)0x0400) /*!< XIN1 Bit 2 */ -#define AES256_XIN_XIN13 ((uint16_t)0x0800) /*!< XIN1 Bit 3 */ -#define AES256_XIN_XIN14 ((uint16_t)0x1000) /*!< XIN1 Bit 4 */ -#define AES256_XIN_XIN15 ((uint16_t)0x2000) /*!< XIN1 Bit 5 */ -#define AES256_XIN_XIN16 ((uint16_t)0x4000) /*!< XIN1 Bit 6 */ -#define AES256_XIN_XIN17 ((uint16_t)0x8000) /*!< XIN1 Bit 7 */ - -/****************************************************************************** -* CAPTIO Bits -******************************************************************************/ -/* CAPTIO_CTL[PISEL] Bits */ -#define CAPTIO_CTL_PISEL_OFS ( 1) /*!< CAPTIOPISELx Bit Offset */ -#define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /*!< CAPTIOPISELx Bit Mask */ -#define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /*!< PISEL Bit 0 */ -#define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /*!< PISEL Bit 1 */ -#define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /*!< PISEL Bit 2 */ -#define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /*!< Px.0 */ -#define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /*!< Px.1 */ -#define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /*!< Px.2 */ -#define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /*!< Px.3 */ -#define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /*!< Px.4 */ -#define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /*!< Px.5 */ -#define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /*!< Px.6 */ -#define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /*!< Px.7 */ -/* CAPTIO_CTL[POSEL] Bits */ -#define CAPTIO_CTL_POSEL_OFS ( 4) /*!< CAPTIOPOSELx Bit Offset */ -#define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /*!< CAPTIOPOSELx Bit Mask */ -#define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /*!< POSEL Bit 0 */ -#define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /*!< POSEL Bit 1 */ -#define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /*!< POSEL Bit 2 */ -#define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /*!< POSEL Bit 3 */ -#define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /*!< Px = P15 */ -#define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /*!< Px = P15 */ -/* CAPTIO_CTL[EN] Bits */ -#define CAPTIO_CTL_EN_OFS ( 8) /*!< CAPTIOEN Bit Offset */ -#define CAPTIO_CTL_EN ((uint16_t)0x0100) /*!< Capacitive Touch IO enable */ -/* CAPTIO_CTL[STATE] Bits */ -#define CAPTIO_CTL_STATE_OFS ( 9) /*!< CAPTIOSTATE Bit Offset */ -#define CAPTIO_CTL_STATE ((uint16_t)0x0200) /*!< Capacitive Touch IO state */ - -/****************************************************************************** -* COMP_E Bits -******************************************************************************/ -/* COMP_E_CTL0[IPSEL] Bits */ -#define COMP_E_CTL0_IPSEL_OFS ( 0) /*!< CEIPSEL Bit Offset */ -#define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /*!< CEIPSEL Bit Mask */ -#define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /*!< IPSEL Bit 0 */ -#define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /*!< IPSEL Bit 1 */ -#define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /*!< IPSEL Bit 2 */ -#define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /*!< IPSEL Bit 3 */ -#define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /*!< Channel 15 selected */ -/* COMP_E_CTL0[IPEN] Bits */ -#define COMP_E_CTL0_IPEN_OFS ( 7) /*!< CEIPEN Bit Offset */ -#define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /*!< Channel input enable for the V+ terminal */ -/* COMP_E_CTL0[IMSEL] Bits */ -#define COMP_E_CTL0_IMSEL_OFS ( 8) /*!< CEIMSEL Bit Offset */ -#define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /*!< CEIMSEL Bit Mask */ -#define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /*!< IMSEL Bit 0 */ -#define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /*!< IMSEL Bit 1 */ -#define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /*!< IMSEL Bit 2 */ -#define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /*!< IMSEL Bit 3 */ -#define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /*!< Channel 15 selected */ -/* COMP_E_CTL0[IMEN] Bits */ -#define COMP_E_CTL0_IMEN_OFS (15) /*!< CEIMEN Bit Offset */ -#define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /*!< Channel input enable for the - terminal */ -/* COMP_E_CTL1[OUT] Bits */ -#define COMP_E_CTL1_OUT_OFS ( 0) /*!< CEOUT Bit Offset */ -#define COMP_E_CTL1_OUT ((uint16_t)0x0001) /*!< Comparator output value */ -/* COMP_E_CTL1[OUTPOL] Bits */ -#define COMP_E_CTL1_OUTPOL_OFS ( 1) /*!< CEOUTPOL Bit Offset */ -#define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /*!< Comparator output polarity */ -/* COMP_E_CTL1[F] Bits */ -#define COMP_E_CTL1_F_OFS ( 2) /*!< CEF Bit Offset */ -#define COMP_E_CTL1_F ((uint16_t)0x0004) /*!< Comparator output filter */ -/* COMP_E_CTL1[IES] Bits */ -#define COMP_E_CTL1_IES_OFS ( 3) /*!< CEIES Bit Offset */ -#define COMP_E_CTL1_IES ((uint16_t)0x0008) /*!< Interrupt edge select for CEIIFG and CEIFG */ -/* COMP_E_CTL1[SHORT] Bits */ -#define COMP_E_CTL1_SHORT_OFS ( 4) /*!< CESHORT Bit Offset */ -#define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /*!< Input short */ -/* COMP_E_CTL1[EX] Bits */ -#define COMP_E_CTL1_EX_OFS ( 5) /*!< CEEX Bit Offset */ -#define COMP_E_CTL1_EX ((uint16_t)0x0020) /*!< Exchange */ -/* COMP_E_CTL1[FDLY] Bits */ -#define COMP_E_CTL1_FDLY_OFS ( 6) /*!< CEFDLY Bit Offset */ -#define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /*!< CEFDLY Bit Mask */ -#define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /*!< FDLY Bit 0 */ -#define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /*!< FDLY Bit 1 */ -#define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /*!< Typical filter delay of TBD (450) ns */ -#define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /*!< Typical filter delay of TBD (900) ns */ -#define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /*!< Typical filter delay of TBD (1800) ns */ -#define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /*!< Typical filter delay of TBD (3600) ns */ -/* COMP_E_CTL1[PWRMD] Bits */ -#define COMP_E_CTL1_PWRMD_OFS ( 8) /*!< CEPWRMD Bit Offset */ -#define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /*!< CEPWRMD Bit Mask */ -#define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /*!< PWRMD Bit 0 */ -#define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /*!< PWRMD Bit 1 */ -#define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /*!< High-speed mode */ -#define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /*!< Normal mode */ -#define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /*!< Ultra-low power mode */ -/* COMP_E_CTL1[ON] Bits */ -#define COMP_E_CTL1_ON_OFS (10) /*!< CEON Bit Offset */ -#define COMP_E_CTL1_ON ((uint16_t)0x0400) /*!< Comparator On */ -/* COMP_E_CTL1[MRVL] Bits */ -#define COMP_E_CTL1_MRVL_OFS (11) /*!< CEMRVL Bit Offset */ -#define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /*!< This bit is valid of CEMRVS is set to 1 */ -/* COMP_E_CTL1[MRVS] Bits */ -#define COMP_E_CTL1_MRVS_OFS (12) /*!< CEMRVS Bit Offset */ -#define COMP_E_CTL1_MRVS ((uint16_t)0x1000) -/* COMP_E_CTL2[REF0] Bits */ -#define COMP_E_CTL2_REF0_OFS ( 0) /*!< CEREF0 Bit Offset */ -#define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /*!< CEREF0 Bit Mask */ -/* COMP_E_CTL2[RSEL] Bits */ -#define COMP_E_CTL2_RSEL_OFS ( 5) /*!< CERSEL Bit Offset */ -#define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /*!< Reference select */ -/* COMP_E_CTL2[RS] Bits */ -#define COMP_E_CTL2_RS_OFS ( 6) /*!< CERS Bit Offset */ -#define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /*!< CERS Bit Mask */ -#define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /*!< RS Bit 0 */ -#define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /*!< RS Bit 1 */ -#define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /*!< No current is drawn by the reference circuitry */ -#define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /*!< VCC applied to the resistor ladder */ -#define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /*!< Shared reference voltage applied to the resistor ladder */ -#define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ -/* COMP_E_CTL2[REF1] Bits */ -#define COMP_E_CTL2_REF1_OFS ( 8) /*!< CEREF1 Bit Offset */ -#define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /*!< CEREF1 Bit Mask */ -/* COMP_E_CTL2[REFL] Bits */ -#define COMP_E_CTL2_REFL_OFS (13) /*!< CEREFL Bit Offset */ -#define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /*!< CEREFL Bit Mask */ -#define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /*!< REFL Bit 0 */ -#define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /*!< REFL Bit 1 */ -#define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -/* COMP_E_CTL2[REFACC] Bits */ -#define COMP_E_CTL2_REFACC_OFS (15) /*!< CEREFACC Bit Offset */ -#define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /*!< Reference accuracy */ -/* COMP_E_CTL3[PD0] Bits */ -#define COMP_E_CTL3_PD0_OFS ( 0) /*!< CEPD0 Bit Offset */ -#define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /*!< Port disable */ -/* COMP_E_CTL3[PD1] Bits */ -#define COMP_E_CTL3_PD1_OFS ( 1) /*!< CEPD1 Bit Offset */ -#define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /*!< Port disable */ -/* COMP_E_CTL3[PD2] Bits */ -#define COMP_E_CTL3_PD2_OFS ( 2) /*!< CEPD2 Bit Offset */ -#define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /*!< Port disable */ -/* COMP_E_CTL3[PD3] Bits */ -#define COMP_E_CTL3_PD3_OFS ( 3) /*!< CEPD3 Bit Offset */ -#define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /*!< Port disable */ -/* COMP_E_CTL3[PD4] Bits */ -#define COMP_E_CTL3_PD4_OFS ( 4) /*!< CEPD4 Bit Offset */ -#define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /*!< Port disable */ -/* COMP_E_CTL3[PD5] Bits */ -#define COMP_E_CTL3_PD5_OFS ( 5) /*!< CEPD5 Bit Offset */ -#define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /*!< Port disable */ -/* COMP_E_CTL3[PD6] Bits */ -#define COMP_E_CTL3_PD6_OFS ( 6) /*!< CEPD6 Bit Offset */ -#define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /*!< Port disable */ -/* COMP_E_CTL3[PD7] Bits */ -#define COMP_E_CTL3_PD7_OFS ( 7) /*!< CEPD7 Bit Offset */ -#define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /*!< Port disable */ -/* COMP_E_CTL3[PD8] Bits */ -#define COMP_E_CTL3_PD8_OFS ( 8) /*!< CEPD8 Bit Offset */ -#define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /*!< Port disable */ -/* COMP_E_CTL3[PD9] Bits */ -#define COMP_E_CTL3_PD9_OFS ( 9) /*!< CEPD9 Bit Offset */ -#define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /*!< Port disable */ -/* COMP_E_CTL3[PD10] Bits */ -#define COMP_E_CTL3_PD10_OFS (10) /*!< CEPD10 Bit Offset */ -#define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /*!< Port disable */ -/* COMP_E_CTL3[PD11] Bits */ -#define COMP_E_CTL3_PD11_OFS (11) /*!< CEPD11 Bit Offset */ -#define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /*!< Port disable */ -/* COMP_E_CTL3[PD12] Bits */ -#define COMP_E_CTL3_PD12_OFS (12) /*!< CEPD12 Bit Offset */ -#define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /*!< Port disable */ -/* COMP_E_CTL3[PD13] Bits */ -#define COMP_E_CTL3_PD13_OFS (13) /*!< CEPD13 Bit Offset */ -#define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /*!< Port disable */ -/* COMP_E_CTL3[PD14] Bits */ -#define COMP_E_CTL3_PD14_OFS (14) /*!< CEPD14 Bit Offset */ -#define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /*!< Port disable */ -/* COMP_E_CTL3[PD15] Bits */ -#define COMP_E_CTL3_PD15_OFS (15) /*!< CEPD15 Bit Offset */ -#define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /*!< Port disable */ -/* COMP_E_INT[IFG] Bits */ -#define COMP_E_INT_IFG_OFS ( 0) /*!< CEIFG Bit Offset */ -#define COMP_E_INT_IFG ((uint16_t)0x0001) /*!< Comparator output interrupt flag */ -/* COMP_E_INT[IIFG] Bits */ -#define COMP_E_INT_IIFG_OFS ( 1) /*!< CEIIFG Bit Offset */ -#define COMP_E_INT_IIFG ((uint16_t)0x0002) /*!< Comparator output inverted interrupt flag */ -/* COMP_E_INT[RDYIFG] Bits */ -#define COMP_E_INT_RDYIFG_OFS ( 4) /*!< CERDYIFG Bit Offset */ -#define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /*!< Comparator ready interrupt flag */ -/* COMP_E_INT[IE] Bits */ -#define COMP_E_INT_IE_OFS ( 8) /*!< CEIE Bit Offset */ -#define COMP_E_INT_IE ((uint16_t)0x0100) /*!< Comparator output interrupt enable */ -/* COMP_E_INT[IIE] Bits */ -#define COMP_E_INT_IIE_OFS ( 9) /*!< CEIIE Bit Offset */ -#define COMP_E_INT_IIE ((uint16_t)0x0200) /*!< Comparator output interrupt enable inverted polarity */ -/* COMP_E_INT[RDYIE] Bits */ -#define COMP_E_INT_RDYIE_OFS (12) /*!< CERDYIE Bit Offset */ -#define COMP_E_INT_RDYIE ((uint16_t)0x1000) /*!< Comparator ready interrupt enable */ - -/****************************************************************************** -* COREDEBUG Bits -******************************************************************************/ - - -/****************************************************************************** -* CRC32 Bits -******************************************************************************/ - -/****************************************************************************** -* CS Bits -******************************************************************************/ -/* CS_KEY[KEY] Bits */ -#define CS_KEY_KEY_OFS ( 0) /*!< CSKEY Bit Offset */ -#define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< CSKEY Bit Mask */ -/* CS_CTL0[DCOTUNE] Bits */ -#define CS_CTL0_DCOTUNE_OFS ( 0) /*!< DCOTUNE Bit Offset */ -#define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /*!< DCOTUNE Bit Mask */ -/* CS_CTL0[DCORSEL] Bits */ -#define CS_CTL0_DCORSEL_OFS (16) /*!< DCORSEL Bit Offset */ -#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /*!< DCORSEL Bit Mask */ -#define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /*!< DCORSEL Bit 0 */ -#define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /*!< DCORSEL Bit 1 */ -#define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /*!< DCORSEL Bit 2 */ -#define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */ -#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */ -#define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */ -#define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */ -#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */ -#define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */ -/* CS_CTL0[DCORES] Bits */ -#define CS_CTL0_DCORES_OFS (22) /*!< DCORES Bit Offset */ -#define CS_CTL0_DCORES ((uint32_t)0x00400000) /*!< Enables the DCO external resistor mode */ -/* CS_CTL0[DCOEN] Bits */ -#define CS_CTL0_DCOEN_OFS (23) /*!< DCOEN Bit Offset */ -#define CS_CTL0_DCOEN ((uint32_t)0x00800000) /*!< Enables the DCO oscillator */ -/* CS_CTL1[SELM] Bits */ -#define CS_CTL1_SELM_OFS ( 0) /*!< SELM Bit Offset */ -#define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /*!< SELM Bit Mask */ -#define CS_CTL1_SELM0 ((uint32_t)0x00000001) /*!< SELM Bit 0 */ -#define CS_CTL1_SELM1 ((uint32_t)0x00000002) /*!< SELM Bit 1 */ -#define CS_CTL1_SELM2 ((uint32_t)0x00000004) /*!< SELM Bit 2 */ -#define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM_1 ((uint32_t)0x00000001) -#define CS_CTL1_SELM_2 ((uint32_t)0x00000002) -#define CS_CTL1_SELM_3 ((uint32_t)0x00000003) -#define CS_CTL1_SELM_4 ((uint32_t)0x00000004) -#define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001) -#define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002) -#define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003) -#define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004) -#define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -/* CS_CTL1[SELS] Bits */ -#define CS_CTL1_SELS_OFS ( 4) /*!< SELS Bit Offset */ -#define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /*!< SELS Bit Mask */ -#define CS_CTL1_SELS0 ((uint32_t)0x00000010) /*!< SELS Bit 0 */ -#define CS_CTL1_SELS1 ((uint32_t)0x00000020) /*!< SELS Bit 1 */ -#define CS_CTL1_SELS2 ((uint32_t)0x00000040) /*!< SELS Bit 2 */ -#define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS_1 ((uint32_t)0x00000010) -#define CS_CTL1_SELS_2 ((uint32_t)0x00000020) -#define CS_CTL1_SELS_3 ((uint32_t)0x00000030) -#define CS_CTL1_SELS_4 ((uint32_t)0x00000040) -#define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010) -#define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020) -#define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030) -#define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040) -#define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -/* CS_CTL1[SELA] Bits */ -#define CS_CTL1_SELA_OFS ( 8) /*!< SELA Bit Offset */ -#define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /*!< SELA Bit Mask */ -#define CS_CTL1_SELA0 ((uint32_t)0x00000100) /*!< SELA Bit 0 */ -#define CS_CTL1_SELA1 ((uint32_t)0x00000200) /*!< SELA Bit 1 */ -#define CS_CTL1_SELA2 ((uint32_t)0x00000400) /*!< SELA Bit 2 */ -#define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA_1 ((uint32_t)0x00000100) -#define CS_CTL1_SELA_2 ((uint32_t)0x00000200) -#define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100) -#define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200) -/* CS_CTL1[SELB] Bits */ -#define CS_CTL1_SELB_OFS (12) /*!< SELB Bit Offset */ -#define CS_CTL1_SELB ((uint32_t)0x00001000) /*!< Selects the BCLK source */ -/* CS_CTL1[DIVM] Bits */ -#define CS_CTL1_DIVM_OFS (16) /*!< DIVM Bit Offset */ -#define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /*!< DIVM Bit Mask */ -#define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /*!< DIVM Bit 0 */ -#define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /*!< DIVM Bit 1 */ -#define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /*!< DIVM Bit 2 */ -#define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -#define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -/* CS_CTL1[DIVHS] Bits */ -#define CS_CTL1_DIVHS_OFS (20) /*!< DIVHS Bit Offset */ -#define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /*!< DIVHS Bit Mask */ -#define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /*!< DIVHS Bit 0 */ -#define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /*!< DIVHS Bit 1 */ -#define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /*!< DIVHS Bit 2 */ -#define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -#define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -/* CS_CTL1[DIVA] Bits */ -#define CS_CTL1_DIVA_OFS (24) /*!< DIVA Bit Offset */ -#define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /*!< DIVA Bit Mask */ -#define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /*!< DIVA Bit 0 */ -#define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /*!< DIVA Bit 1 */ -#define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /*!< DIVA Bit 2 */ -#define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -#define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -/* CS_CTL1[DIVS] Bits */ -#define CS_CTL1_DIVS_OFS (28) /*!< DIVS Bit Offset */ -#define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /*!< DIVS Bit Mask */ -#define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /*!< DIVS Bit 0 */ -#define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /*!< DIVS Bit 1 */ -#define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /*!< DIVS Bit 2 */ -#define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -#define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -/* CS_CTL2[LFXTDRIVE] Bits */ -#define CS_CTL2_LFXTDRIVE_OFS ( 0) /*!< LFXTDRIVE Bit Offset */ -#define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /*!< LFXTDRIVE Bit Mask */ -#define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /*!< LFXTDRIVE Bit 0 */ -#define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /*!< LFXTDRIVE Bit 1 */ -#define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /*!< Lowest drive strength and current consumption LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */ -/* CS_CTL2[LFXT_EN] Bits */ -#define CS_CTL2_LFXT_EN_OFS ( 8) /*!< LFXT_EN Bit Offset */ -#define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /*!< Turns on the LFXT oscillator regardless if used as a clock resource */ -/* CS_CTL2[LFXTBYPASS] Bits */ -#define CS_CTL2_LFXTBYPASS_OFS ( 9) /*!< LFXTBYPASS Bit Offset */ -#define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /*!< LFXT bypass select */ -/* CS_CTL2[HFXTDRIVE] Bits */ -#define CS_CTL2_HFXTDRIVE_OFS (16) /*!< HFXTDRIVE Bit Offset */ -#define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /*!< HFXT oscillator drive selection */ -/* CS_CTL2[HFXTFREQ] Bits */ -#define CS_CTL2_HFXTFREQ_OFS (20) /*!< HFXTFREQ Bit Offset */ -#define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /*!< HFXTFREQ Bit Mask */ -#define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /*!< HFXTFREQ Bit 0 */ -#define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /*!< HFXTFREQ Bit 1 */ -#define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /*!< HFXTFREQ Bit 2 */ -#define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /*!< 1 MHz to 4 MHz */ -#define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /*!< >4 MHz to 8 MHz */ -#define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /*!< >8 MHz to 16 MHz */ -#define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /*!< >16 MHz to 24 MHz */ -#define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /*!< >24 MHz to 32 MHz */ -#define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /*!< >32 MHz to 40 MHz */ -#define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /*!< >40 MHz to 48 MHz */ -#define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /*!< Reserved for future use. */ -/* CS_CTL2[HFXT_EN] Bits */ -#define CS_CTL2_HFXT_EN_OFS (24) /*!< HFXT_EN Bit Offset */ -#define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /*!< Turns on the HFXT oscillator regardless if used as a clock resource */ -/* CS_CTL2[HFXTBYPASS] Bits */ -#define CS_CTL2_HFXTBYPASS_OFS (25) /*!< HFXTBYPASS Bit Offset */ -#define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /*!< HFXT bypass select */ -/* CS_CTL3[FCNTLF] Bits */ -#define CS_CTL3_FCNTLF_OFS ( 0) /*!< FCNTLF Bit Offset */ -#define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /*!< FCNTLF Bit Mask */ -#define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /*!< FCNTLF Bit 0 */ -#define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /*!< FCNTLF Bit 1 */ -#define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /*!< 32768 cycles */ -#define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /*!< 32768 cycles */ -/* CS_CTL3[RFCNTLF] Bits */ -#define CS_CTL3_RFCNTLF_OFS ( 2) /*!< RFCNTLF Bit Offset */ -#define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /*!< Reset start fault counter for LFXT */ -/* CS_CTL3[FCNTLF_EN] Bits */ -#define CS_CTL3_FCNTLF_EN_OFS ( 3) /*!< FCNTLF_EN Bit Offset */ -#define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /*!< Enable start fault counter for LFXT */ -/* CS_CTL3[FCNTHF] Bits */ -#define CS_CTL3_FCNTHF_OFS ( 4) /*!< FCNTHF Bit Offset */ -#define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /*!< FCNTHF Bit Mask */ -#define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /*!< FCNTHF Bit 0 */ -#define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /*!< FCNTHF Bit 1 */ -#define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /*!< 16384 cycles */ -#define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /*!< 16384 cycles */ -/* CS_CTL3[RFCNTHF] Bits */ -#define CS_CTL3_RFCNTHF_OFS ( 6) /*!< RFCNTHF Bit Offset */ -#define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /*!< Reset start fault counter for HFXT */ -/* CS_CTL3[FCNTHF_EN] Bits */ -#define CS_CTL3_FCNTHF_EN_OFS ( 7) /*!< FCNTHF_EN Bit Offset */ -#define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /*!< Enable start fault counter for HFXT */ -/* CS_CLKEN[ACLK_EN] Bits */ -#define CS_CLKEN_ACLK_EN_OFS ( 0) /*!< ACLK_EN Bit Offset */ -#define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /*!< ACLK system clock conditional request enable */ -/* CS_CLKEN[MCLK_EN] Bits */ -#define CS_CLKEN_MCLK_EN_OFS ( 1) /*!< MCLK_EN Bit Offset */ -#define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /*!< MCLK system clock conditional request enable */ -/* CS_CLKEN[HSMCLK_EN] Bits */ -#define CS_CLKEN_HSMCLK_EN_OFS ( 2) /*!< HSMCLK_EN Bit Offset */ -#define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /*!< HSMCLK system clock conditional request enable */ -/* CS_CLKEN[SMCLK_EN] Bits */ -#define CS_CLKEN_SMCLK_EN_OFS ( 3) /*!< SMCLK_EN Bit Offset */ -#define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /*!< SMCLK system clock conditional request enable */ -/* CS_CLKEN[VLO_EN] Bits */ -#define CS_CLKEN_VLO_EN_OFS ( 8) /*!< VLO_EN Bit Offset */ -#define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /*!< Turns on the VLO oscillator */ -/* CS_CLKEN[REFO_EN] Bits */ -#define CS_CLKEN_REFO_EN_OFS ( 9) /*!< REFO_EN Bit Offset */ -#define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /*!< Turns on the REFO oscillator */ -/* CS_CLKEN[MODOSC_EN] Bits */ -#define CS_CLKEN_MODOSC_EN_OFS (10) /*!< MODOSC_EN Bit Offset */ -#define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /*!< Turns on the MODOSC oscillator */ -/* CS_CLKEN[REFOFSEL] Bits */ -#define CS_CLKEN_REFOFSEL_OFS (15) /*!< REFOFSEL Bit Offset */ -#define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /*!< Selects REFO nominal frequency */ -/* CS_STAT[DCO_ON] Bits */ -#define CS_STAT_DCO_ON_OFS ( 0) /*!< DCO_ON Bit Offset */ -#define CS_STAT_DCO_ON ((uint32_t)0x00000001) /*!< DCO status */ -/* CS_STAT[DCOBIAS_ON] Bits */ -#define CS_STAT_DCOBIAS_ON_OFS ( 1) /*!< DCOBIAS_ON Bit Offset */ -#define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /*!< DCO bias status */ -/* CS_STAT[HFXT_ON] Bits */ -#define CS_STAT_HFXT_ON_OFS ( 2) /*!< HFXT_ON Bit Offset */ -#define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /*!< HFXT status */ -/* CS_STAT[MODOSC_ON] Bits */ -#define CS_STAT_MODOSC_ON_OFS ( 4) /*!< MODOSC_ON Bit Offset */ -#define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /*!< MODOSC status */ -/* CS_STAT[VLO_ON] Bits */ -#define CS_STAT_VLO_ON_OFS ( 5) /*!< VLO_ON Bit Offset */ -#define CS_STAT_VLO_ON ((uint32_t)0x00000020) /*!< VLO status */ -/* CS_STAT[LFXT_ON] Bits */ -#define CS_STAT_LFXT_ON_OFS ( 6) /*!< LFXT_ON Bit Offset */ -#define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /*!< LFXT status */ -/* CS_STAT[REFO_ON] Bits */ -#define CS_STAT_REFO_ON_OFS ( 7) /*!< REFO_ON Bit Offset */ -#define CS_STAT_REFO_ON ((uint32_t)0x00000080) /*!< REFO status */ -/* CS_STAT[ACLK_ON] Bits */ -#define CS_STAT_ACLK_ON_OFS (16) /*!< ACLK_ON Bit Offset */ -#define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /*!< ACLK system clock status */ -/* CS_STAT[MCLK_ON] Bits */ -#define CS_STAT_MCLK_ON_OFS (17) /*!< MCLK_ON Bit Offset */ -#define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /*!< MCLK system clock status */ -/* CS_STAT[HSMCLK_ON] Bits */ -#define CS_STAT_HSMCLK_ON_OFS (18) /*!< HSMCLK_ON Bit Offset */ -#define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /*!< HSMCLK system clock status */ -/* CS_STAT[SMCLK_ON] Bits */ -#define CS_STAT_SMCLK_ON_OFS (19) /*!< SMCLK_ON Bit Offset */ -#define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /*!< SMCLK system clock status */ -/* CS_STAT[MODCLK_ON] Bits */ -#define CS_STAT_MODCLK_ON_OFS (20) /*!< MODCLK_ON Bit Offset */ -#define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /*!< MODCLK system clock status */ -/* CS_STAT[VLOCLK_ON] Bits */ -#define CS_STAT_VLOCLK_ON_OFS (21) /*!< VLOCLK_ON Bit Offset */ -#define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /*!< VLOCLK system clock status */ -/* CS_STAT[LFXTCLK_ON] Bits */ -#define CS_STAT_LFXTCLK_ON_OFS (22) /*!< LFXTCLK_ON Bit Offset */ -#define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /*!< LFXTCLK system clock status */ -/* CS_STAT[REFOCLK_ON] Bits */ -#define CS_STAT_REFOCLK_ON_OFS (23) /*!< REFOCLK_ON Bit Offset */ -#define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /*!< REFOCLK system clock status */ -/* CS_STAT[ACLK_READY] Bits */ -#define CS_STAT_ACLK_READY_OFS (24) /*!< ACLK_READY Bit Offset */ -#define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /*!< ACLK Ready status */ -/* CS_STAT[MCLK_READY] Bits */ -#define CS_STAT_MCLK_READY_OFS (25) /*!< MCLK_READY Bit Offset */ -#define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /*!< MCLK Ready status */ -/* CS_STAT[HSMCLK_READY] Bits */ -#define CS_STAT_HSMCLK_READY_OFS (26) /*!< HSMCLK_READY Bit Offset */ -#define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /*!< HSMCLK Ready status */ -/* CS_STAT[SMCLK_READY] Bits */ -#define CS_STAT_SMCLK_READY_OFS (27) /*!< SMCLK_READY Bit Offset */ -#define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /*!< SMCLK Ready status */ -/* CS_STAT[BCLK_READY] Bits */ -#define CS_STAT_BCLK_READY_OFS (28) /*!< BCLK_READY Bit Offset */ -#define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /*!< BCLK Ready status */ -/* CS_IE[LFXTIE] Bits */ -#define CS_IE_LFXTIE_OFS ( 0) /*!< LFXTIE Bit Offset */ -#define CS_IE_LFXTIE ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag interrupt enable */ -/* CS_IE[HFXTIE] Bits */ -#define CS_IE_HFXTIE_OFS ( 1) /*!< HFXTIE Bit Offset */ -#define CS_IE_HFXTIE ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag interrupt enable */ -/* CS_IE[DCOR_OPNIE] Bits */ -#define CS_IE_DCOR_OPNIE_OFS ( 6) /*!< DCOR_OPNIE Bit Offset */ -#define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag interrupt enable. */ -/* CS_IE[FCNTLFIE] Bits */ -#define CS_IE_FCNTLFIE_OFS ( 8) /*!< FCNTLFIE Bit Offset */ -#define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /*!< Start fault counter interrupt enable LFXT */ -/* CS_IE[FCNTHFIE] Bits */ -#define CS_IE_FCNTHFIE_OFS ( 9) /*!< FCNTHFIE Bit Offset */ -#define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /*!< Start fault counter interrupt enable HFXT */ -/* CS_IFG[LFXTIFG] Bits */ -#define CS_IFG_LFXTIFG_OFS ( 0) /*!< LFXTIFG Bit Offset */ -#define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag */ -/* CS_IFG[HFXTIFG] Bits */ -#define CS_IFG_HFXTIFG_OFS ( 1) /*!< HFXTIFG Bit Offset */ -#define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag */ -/* CS_IFG[DCOR_SHTIFG] Bits */ -#define CS_IFG_DCOR_SHTIFG_OFS ( 5) /*!< DCOR_SHTIFG Bit Offset */ -#define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /*!< DCO external resistor short circuit fault flag. */ -/* CS_IFG[DCOR_OPNIFG] Bits */ -#define CS_IFG_DCOR_OPNIFG_OFS ( 6) /*!< DCOR_OPNIFG Bit Offset */ -#define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag. */ -/* CS_IFG[FCNTLFIFG] Bits */ -#define CS_IFG_FCNTLFIFG_OFS ( 8) /*!< FCNTLFIFG Bit Offset */ -#define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter interrupt flag LFXT */ -/* CS_IFG[FCNTHFIFG] Bits */ -#define CS_IFG_FCNTHFIFG_OFS ( 9) /*!< FCNTHFIFG Bit Offset */ -#define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter interrupt flag HFXT */ -/* CS_CLRIFG[CLR_LFXTIFG] Bits */ -#define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /*!< CLR_LFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /*!< Clear LFXT oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_HFXTIFG] Bits */ -#define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /*!< CLR_HFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /*!< Clear HFXT oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /*!< CLR_DCOR_OPNIFG Bit Offset */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Clear DCO external resistor open circuit fault interrupt flag. */ -/* CS_CLRIFG[CLR_FCNTLFIFG] Bits */ -#define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /*!< CLR_FCNTLFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter clear interrupt flag LFXT */ -/* CS_CLRIFG[CLR_FCNTHFIFG] Bits */ -#define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /*!< CLR_FCNTHFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter clear interrupt flag HFXT */ -/* CS_SETIFG[SET_LFXTIFG] Bits */ -#define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /*!< SET_LFXTIFG Bit Offset */ -#define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /*!< Set LFXT oscillator fault interrupt flag */ -/* CS_SETIFG[SET_HFXTIFG] Bits */ -#define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /*!< SET_HFXTIFG Bit Offset */ -#define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /*!< Set HFXT oscillator fault interrupt flag */ -/* CS_SETIFG[SET_DCOR_OPNIFG] Bits */ -#define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /*!< SET_DCOR_OPNIFG Bit Offset */ -#define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Set DCO external resistor open circuit fault interrupt flag. */ -/* CS_SETIFG[SET_FCNTHFIFG] Bits */ -#define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /*!< SET_FCNTHFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter set interrupt flag HFXT */ -/* CS_SETIFG[SET_FCNTLFIFG] Bits */ -#define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /*!< SET_FCNTLFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter set interrupt flag LFXT */ -/* CS_DCOERCAL0[DCO_TCCAL] Bits */ -#define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /*!< DCO_TCCAL Bit Offset */ -#define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /*!< DCO_TCCAL Bit Mask */ -/* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /*!< DCO_FCAL_RSEL04 Bit Offset */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /*!< DCO_FCAL_RSEL04 Bit Mask */ -/* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /*!< DCO_FCAL_RSEL5 Bit Offset */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /*!< DCO_FCAL_RSEL5 Bit Mask */ -/* Pre-defined bitfield values */ -#define CS_KEY_VAL ((uint32_t)0x0000695A) /*!< CS control key value */ - -/****************************************************************************** -* DIO Bits -******************************************************************************/ -/* DIO_IV[IV] Bits */ -#define DIO_PORT_IV_OFS ( 0) /*!< DIO Port IV Bit Offset */ -#define DIO_PORT_IV_MASK ((uint16_t)0x001F) /*!< DIO Port IV Bit Mask */ -#define DIO_PORT_IV0 ((uint16_t)0x0001) /*!< DIO Port IV Bit 0 */ -#define DIO_PORT_IV1 ((uint16_t)0x0002) /*!< DIO Port IV Bit 1 */ -#define DIO_PORT_IV2 ((uint16_t)0x0004) /*!< DIO Port IV Bit 2 */ -#define DIO_PORT_IV3 ((uint16_t)0x0008) /*!< DIO Port IV Bit 3 */ -#define DIO_PORT_IV4 ((uint16_t)0x0010) /*!< DIO Port IV Bit 4 */ -#define DIO_PORT_IV_0 ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV_2 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ - /* Priority: Highest */ -#define DIO_PORT_IV_4 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV_6 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV_8 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV_10 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV_12 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV_14 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV_16 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ - /* Priority: Lowest */ -#define DIO_PORT_IV__NONE ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ - /* Priority: Highest */ -#define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ - /* Priority: Lowest */ - - -/****************************************************************************** -* DMA Bits -******************************************************************************/ -/* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /*!< NUM_DMA_CHANNELS Bit Offset */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /*!< NUM_DMA_CHANNELS Bit Mask */ -/* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /*!< NUM_SRC_PER_CHANNEL Bit Offset */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /*!< NUM_SRC_PER_CHANNEL Bit Mask */ -/* DMA_SW_CHTRIG[CH0] Bits */ -#define DMA_SW_CHTRIG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /*!< Write 1, triggers DMA_CHANNEL0 */ -/* DMA_SW_CHTRIG[CH1] Bits */ -#define DMA_SW_CHTRIG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /*!< Write 1, triggers DMA_CHANNEL1 */ -/* DMA_SW_CHTRIG[CH2] Bits */ -#define DMA_SW_CHTRIG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /*!< Write 1, triggers DMA_CHANNEL2 */ -/* DMA_SW_CHTRIG[CH3] Bits */ -#define DMA_SW_CHTRIG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /*!< Write 1, triggers DMA_CHANNEL3 */ -/* DMA_SW_CHTRIG[CH4] Bits */ -#define DMA_SW_CHTRIG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /*!< Write 1, triggers DMA_CHANNEL4 */ -/* DMA_SW_CHTRIG[CH5] Bits */ -#define DMA_SW_CHTRIG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /*!< Write 1, triggers DMA_CHANNEL5 */ -/* DMA_SW_CHTRIG[CH6] Bits */ -#define DMA_SW_CHTRIG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /*!< Write 1, triggers DMA_CHANNEL6 */ -/* DMA_SW_CHTRIG[CH7] Bits */ -#define DMA_SW_CHTRIG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /*!< Write 1, triggers DMA_CHANNEL7 */ -/* DMA_SW_CHTRIG[CH8] Bits */ -#define DMA_SW_CHTRIG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /*!< Write 1, triggers DMA_CHANNEL8 */ -/* DMA_SW_CHTRIG[CH9] Bits */ -#define DMA_SW_CHTRIG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /*!< Write 1, triggers DMA_CHANNEL9 */ -/* DMA_SW_CHTRIG[CH10] Bits */ -#define DMA_SW_CHTRIG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /*!< Write 1, triggers DMA_CHANNEL10 */ -/* DMA_SW_CHTRIG[CH11] Bits */ -#define DMA_SW_CHTRIG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /*!< Write 1, triggers DMA_CHANNEL11 */ -/* DMA_SW_CHTRIG[CH12] Bits */ -#define DMA_SW_CHTRIG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /*!< Write 1, triggers DMA_CHANNEL12 */ -/* DMA_SW_CHTRIG[CH13] Bits */ -#define DMA_SW_CHTRIG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /*!< Write 1, triggers DMA_CHANNEL13 */ -/* DMA_SW_CHTRIG[CH14] Bits */ -#define DMA_SW_CHTRIG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /*!< Write 1, triggers DMA_CHANNEL14 */ -/* DMA_SW_CHTRIG[CH15] Bits */ -#define DMA_SW_CHTRIG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /*!< Write 1, triggers DMA_CHANNEL15 */ -/* DMA_SW_CHTRIG[CH16] Bits */ -#define DMA_SW_CHTRIG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /*!< Write 1, triggers DMA_CHANNEL16 */ -/* DMA_SW_CHTRIG[CH17] Bits */ -#define DMA_SW_CHTRIG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /*!< Write 1, triggers DMA_CHANNEL17 */ -/* DMA_SW_CHTRIG[CH18] Bits */ -#define DMA_SW_CHTRIG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /*!< Write 1, triggers DMA_CHANNEL18 */ -/* DMA_SW_CHTRIG[CH19] Bits */ -#define DMA_SW_CHTRIG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /*!< Write 1, triggers DMA_CHANNEL19 */ -/* DMA_SW_CHTRIG[CH20] Bits */ -#define DMA_SW_CHTRIG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /*!< Write 1, triggers DMA_CHANNEL20 */ -/* DMA_SW_CHTRIG[CH21] Bits */ -#define DMA_SW_CHTRIG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /*!< Write 1, triggers DMA_CHANNEL21 */ -/* DMA_SW_CHTRIG[CH22] Bits */ -#define DMA_SW_CHTRIG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /*!< Write 1, triggers DMA_CHANNEL22 */ -/* DMA_SW_CHTRIG[CH23] Bits */ -#define DMA_SW_CHTRIG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /*!< Write 1, triggers DMA_CHANNEL23 */ -/* DMA_SW_CHTRIG[CH24] Bits */ -#define DMA_SW_CHTRIG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /*!< Write 1, triggers DMA_CHANNEL24 */ -/* DMA_SW_CHTRIG[CH25] Bits */ -#define DMA_SW_CHTRIG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /*!< Write 1, triggers DMA_CHANNEL25 */ -/* DMA_SW_CHTRIG[CH26] Bits */ -#define DMA_SW_CHTRIG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /*!< Write 1, triggers DMA_CHANNEL26 */ -/* DMA_SW_CHTRIG[CH27] Bits */ -#define DMA_SW_CHTRIG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /*!< Write 1, triggers DMA_CHANNEL27 */ -/* DMA_SW_CHTRIG[CH28] Bits */ -#define DMA_SW_CHTRIG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /*!< Write 1, triggers DMA_CHANNEL28 */ -/* DMA_SW_CHTRIG[CH29] Bits */ -#define DMA_SW_CHTRIG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /*!< Write 1, triggers DMA_CHANNEL29 */ -/* DMA_SW_CHTRIG[CH30] Bits */ -#define DMA_SW_CHTRIG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /*!< Write 1, triggers DMA_CHANNEL30 */ -/* DMA_SW_CHTRIG[CH31] Bits */ -#define DMA_SW_CHTRIG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /*!< Write 1, triggers DMA_CHANNEL31 */ -/* DMA_CHN_SRCCFG[DMA_SRC] Bits */ -#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /*!< DMA_SRC Bit Offset */ -#define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /*!< DMA_SRC Bit Mask */ -/* DMA_INT1_SRCCFG[INT_SRC] Bits */ -#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT1_SRCCFG[EN] Bits */ -#define DMA_INT1_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT1 mapping */ -/* DMA_INT2_SRCCFG[INT_SRC] Bits */ -#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT2_SRCCFG[EN] Bits */ -#define DMA_INT2_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT2 mapping */ -/* DMA_INT3_SRCCFG[INT_SRC] Bits */ -#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT3_SRCCFG[EN] Bits */ -#define DMA_INT3_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT3 mapping */ -/* DMA_INT0_SRCFLG[CH0] Bits */ -#define DMA_INT0_SRCFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /*!< Channel 0 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH1] Bits */ -#define DMA_INT0_SRCFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /*!< Channel 1 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH2] Bits */ -#define DMA_INT0_SRCFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /*!< Channel 2 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH3] Bits */ -#define DMA_INT0_SRCFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /*!< Channel 3 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH4] Bits */ -#define DMA_INT0_SRCFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /*!< Channel 4 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH5] Bits */ -#define DMA_INT0_SRCFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /*!< Channel 5 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH6] Bits */ -#define DMA_INT0_SRCFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /*!< Channel 6 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH7] Bits */ -#define DMA_INT0_SRCFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /*!< Channel 7 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH8] Bits */ -#define DMA_INT0_SRCFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /*!< Channel 8 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH9] Bits */ -#define DMA_INT0_SRCFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /*!< Channel 9 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH10] Bits */ -#define DMA_INT0_SRCFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /*!< Channel 10 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH11] Bits */ -#define DMA_INT0_SRCFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /*!< Channel 11 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH12] Bits */ -#define DMA_INT0_SRCFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /*!< Channel 12 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH13] Bits */ -#define DMA_INT0_SRCFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /*!< Channel 13 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH14] Bits */ -#define DMA_INT0_SRCFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /*!< Channel 14 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH15] Bits */ -#define DMA_INT0_SRCFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /*!< Channel 15 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH16] Bits */ -#define DMA_INT0_SRCFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /*!< Channel 16 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH17] Bits */ -#define DMA_INT0_SRCFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /*!< Channel 17 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH18] Bits */ -#define DMA_INT0_SRCFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /*!< Channel 18 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH19] Bits */ -#define DMA_INT0_SRCFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /*!< Channel 19 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH20] Bits */ -#define DMA_INT0_SRCFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /*!< Channel 20 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH21] Bits */ -#define DMA_INT0_SRCFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /*!< Channel 21 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH22] Bits */ -#define DMA_INT0_SRCFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /*!< Channel 22 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH23] Bits */ -#define DMA_INT0_SRCFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /*!< Channel 23 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH24] Bits */ -#define DMA_INT0_SRCFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /*!< Channel 24 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH25] Bits */ -#define DMA_INT0_SRCFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /*!< Channel 25 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH26] Bits */ -#define DMA_INT0_SRCFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /*!< Channel 26 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH27] Bits */ -#define DMA_INT0_SRCFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /*!< Channel 27 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH28] Bits */ -#define DMA_INT0_SRCFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /*!< Channel 28 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH29] Bits */ -#define DMA_INT0_SRCFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /*!< Channel 29 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH30] Bits */ -#define DMA_INT0_SRCFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /*!< Channel 30 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH31] Bits */ -#define DMA_INT0_SRCFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /*!< Channel 31 was the source of DMA_INT0 */ -/* DMA_INT0_CLRFLG[CH0] Bits */ -#define DMA_INT0_CLRFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH1] Bits */ -#define DMA_INT0_CLRFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH2] Bits */ -#define DMA_INT0_CLRFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH3] Bits */ -#define DMA_INT0_CLRFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH4] Bits */ -#define DMA_INT0_CLRFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH5] Bits */ -#define DMA_INT0_CLRFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH6] Bits */ -#define DMA_INT0_CLRFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH7] Bits */ -#define DMA_INT0_CLRFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH8] Bits */ -#define DMA_INT0_CLRFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH9] Bits */ -#define DMA_INT0_CLRFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH10] Bits */ -#define DMA_INT0_CLRFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH11] Bits */ -#define DMA_INT0_CLRFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH12] Bits */ -#define DMA_INT0_CLRFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH13] Bits */ -#define DMA_INT0_CLRFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH14] Bits */ -#define DMA_INT0_CLRFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH15] Bits */ -#define DMA_INT0_CLRFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH16] Bits */ -#define DMA_INT0_CLRFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH17] Bits */ -#define DMA_INT0_CLRFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH18] Bits */ -#define DMA_INT0_CLRFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH19] Bits */ -#define DMA_INT0_CLRFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH20] Bits */ -#define DMA_INT0_CLRFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH21] Bits */ -#define DMA_INT0_CLRFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH22] Bits */ -#define DMA_INT0_CLRFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH23] Bits */ -#define DMA_INT0_CLRFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH24] Bits */ -#define DMA_INT0_CLRFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH25] Bits */ -#define DMA_INT0_CLRFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH26] Bits */ -#define DMA_INT0_CLRFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH27] Bits */ -#define DMA_INT0_CLRFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH28] Bits */ -#define DMA_INT0_CLRFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH29] Bits */ -#define DMA_INT0_CLRFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH30] Bits */ -#define DMA_INT0_CLRFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH31] Bits */ -#define DMA_INT0_CLRFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_STAT[MASTEN] Bits */ -#define DMA_STAT_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_STAT_MASTEN ((uint32_t)0x00000001) -/* DMA_STAT[STATE] Bits */ -#define DMA_STAT_STATE_OFS ( 4) /*!< STATE Bit Offset */ -#define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /*!< STATE Bit Mask */ -#define DMA_STAT_STATE0 ((uint32_t)0x00000010) /*!< STATE Bit 0 */ -#define DMA_STAT_STATE1 ((uint32_t)0x00000020) /*!< STATE Bit 1 */ -#define DMA_STAT_STATE2 ((uint32_t)0x00000040) /*!< STATE Bit 2 */ -#define DMA_STAT_STATE3 ((uint32_t)0x00000080) /*!< STATE Bit 3 */ -#define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /*!< idle */ -#define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /*!< reading channel controller data */ -#define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /*!< reading source data end pointer */ -#define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /*!< reading destination data end pointer */ -#define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /*!< reading source data */ -#define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /*!< writing destination data */ -#define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /*!< waiting for DMA request to clear */ -#define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /*!< writing channel controller data */ -#define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /*!< stalled */ -#define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /*!< done */ -#define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /*!< peripheral scatter-gather transition */ -#define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /*!< Reserved */ -#define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /*!< Reserved */ -#define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /*!< Reserved */ -#define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /*!< Reserved */ -#define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /*!< Reserved */ -/* DMA_STAT[DMACHANS] Bits */ -#define DMA_STAT_DMACHANS_OFS (16) /*!< DMACHANS Bit Offset */ -#define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /*!< DMACHANS Bit Mask */ -#define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /*!< DMACHANS Bit 0 */ -#define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /*!< DMACHANS Bit 1 */ -#define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /*!< DMACHANS Bit 2 */ -#define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /*!< DMACHANS Bit 3 */ -#define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /*!< DMACHANS Bit 4 */ -#define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /*!< Controller configured to use 1 DMA channel */ -#define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /*!< Controller configured to use 2 DMA channels */ -#define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /*!< Controller configured to use 31 DMA channels */ -#define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /*!< Controller configured to use 32 DMA channels */ -/* DMA_STAT[TESTSTAT] Bits */ -#define DMA_STAT_TESTSTAT_OFS (28) /*!< TESTSTAT Bit Offset */ -#define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /*!< TESTSTAT Bit Mask */ -#define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /*!< TESTSTAT Bit 0 */ -#define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /*!< TESTSTAT Bit 1 */ -#define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /*!< TESTSTAT Bit 2 */ -#define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /*!< TESTSTAT Bit 3 */ -#define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /*!< Controller does not include the integration test logic */ -#define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /*!< Controller includes the integration test logic */ -/* DMA_CFG[MASTEN] Bits */ -#define DMA_CFG_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_CFG_MASTEN ((uint32_t)0x00000001) -/* DMA_CFG[CHPROTCTRL] Bits */ -#define DMA_CFG_CHPROTCTRL_OFS ( 5) /*!< CHPROTCTRL Bit Offset */ -#define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /*!< CHPROTCTRL Bit Mask */ -/* DMA_CTLBASE[ADDR] Bits */ -#define DMA_CTLBASE_ADDR_OFS ( 5) /*!< ADDR Bit Offset */ -#define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /*!< ADDR Bit Mask */ -/* DMA_ERRCLR[ERRCLR] Bits */ -#define DMA_ERRCLR_ERRCLR_OFS ( 0) /*!< ERRCLR Bit Offset */ -#define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) -/* DMA channel definitions and memory structure alignment */ -#define __MCU_NUM_DMA_CHANNELS__ 8 -#define DMA_CHANNEL_CONTROL_STRUCT_SIZE 0x10 -#define DMA_CONTROL_MEMORY_ALIGNMENT (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE) - -/* UDMA_STAT Control Bits */ -#define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /*!< Available uDMA Channels Minus 1 */ -#define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /*!< Control State Machine Status */ -#define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /*!< Idle */ -#define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /*!< Reading channel controller data */ -#define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /*!< Reading source end pointer */ -#define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /*!< Reading destination end pointer */ -#define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /*!< Reading source data */ -#define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /*!< Writing destination data */ -#define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /*!< Waiting for uDMA request to clear */ -#define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /*!< Writing channel controller data */ -#define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /*!< Stalled */ -#define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /*!< Done */ -#define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /*!< Undefined */ -#define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /*!< Master Enable Status */ -#define UDMA_STAT_DMACHANS_S (16) - -/* UDMA_CFG Control Bits */ -#define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /*!< Controller Master Enable */ - -/* UDMA_CTLBASE Control Bits */ -#define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /*!< Channel Control Base Address */ -#define UDMA_CTLBASE_ADDR_S (10) - -/* UDMA_ALTBASE Control Bits */ -#define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Alternate Channel Address Pointer */ -#define UDMA_ALTBASE_ADDR_S ( 0) - -/* UDMA_WAITSTAT Control Bits */ -#define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Wait Status */ - -/* UDMA_SWREQ Control Bits */ -#define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Software Request */ - -/* UDMA_USEBURSTSET Control Bits */ -#define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Set */ - -/* UDMA_USEBURSTCLR Control Bits */ -#define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Clear */ - -/* UDMA_REQMASKSET Control Bits */ -#define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Set */ - -/* UDMA_REQMASKCLR Control Bits */ -#define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Clear */ - -/* UDMA_ENASET Control Bits */ -#define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Enable Set */ - -/* UDMA_ENACLR Control Bits */ -#define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Clear Channel [n] Enable Clear */ - -/* UDMA_ALTSET Control Bits */ -#define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Set */ - -/* UDMA_ALTCLR Control Bits */ -#define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Clear */ - -/* UDMA_PRIOSET Control Bits */ -#define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Set */ - -/* UDMA_PRIOCLR Control Bits */ -#define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Clear */ - -/* UDMA_ERRCLR Control Bits */ -#define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /*!< uDMA Bus Error Status */ - -/* UDMA_CHASGN Control Bits */ -#define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Assignment Select */ -#define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /*!< Use the primary channel assignment */ -#define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /*!< Use the secondary channel assignment */ - -/* Micro Direct Memory Access (uDMA) offsets */ -#define UDMA_O_SRCENDP ((uint32_t)0x00000000) /*!< DMA Channel Source Address End Pointer */ -#define UDMA_O_DSTENDP ((uint32_t)0x00000004) /*!< DMA Channel Destination Address End Pointer */ -#define UDMA_O_CHCTL ((uint32_t)0x00000008) /*!< DMA Channel Control Word */ - -/* UDMA_O_SRCENDP Control Bits */ -#define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Source Address End Pointer */ -#define UDMA_SRCENDP_ADDR_S ( 0) - -/* UDMA_O_DSTENDP Control Bits */ -#define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Destination Address End Pointer */ -#define UDMA_DSTENDP_ADDR_S ( 0) - -/* UDMA_O_CHCTL Control Bits */ -#define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /*!< Destination Address Increment */ -#define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /*!< Word */ -#define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /*!< No increment */ -#define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /*!< Destination Data Size */ -#define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /*!< Source Address Increment */ -#define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /*!< No increment */ -#define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /*!< Source Data Size */ -#define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /*!< Word */ -#define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /*!< Arbitration Size */ -#define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /*!< 1 Transfer */ -#define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /*!< 2 Transfers */ -#define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /*!< 4 Transfers */ -#define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /*!< 8 Transfers */ -#define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /*!< 16 Transfers */ -#define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /*!< 32 Transfers */ -#define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /*!< 64 Transfers */ -#define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /*!< 128 Transfers */ -#define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /*!< 256 Transfers */ -#define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /*!< 512 Transfers */ -#define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /*!< 1024 Transfers */ -#define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /*!< Transfer Size (minus 1) */ -#define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /*!< Next Useburst */ -#define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /*!< uDMA Transfer Mode */ -#define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /*!< Stop */ -#define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /*!< Basic */ -#define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /*!< Auto-Request */ -#define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /*!< Ping-Pong */ -#define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /*!< Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /*!< Alternate Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /*!< Peripheral Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /*!< Alternate Peripheral Scatter-Gather */ - -#define UDMA_CHCTL_XFERSIZE_S ( 4) - - -/****************************************************************************** -* DWT Bits -******************************************************************************/ - - -/****************************************************************************** -* EUSCI_A Bits -******************************************************************************/ -/* EUSCI_A_CTLW0[SWRST] Bits */ -#define EUSCI_A_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -/* EUSCI_A_CTLW0[TXBRK] Bits */ -#define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /*!< UCTXBRK Bit Offset */ -#define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /*!< Transmit break */ -/* EUSCI_A_CTLW0[TXADDR] Bits */ -#define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /*!< UCTXADDR Bit Offset */ -#define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /*!< Transmit address */ -/* EUSCI_A_CTLW0[DORM] Bits */ -#define EUSCI_A_CTLW0_DORM_OFS ( 3) /*!< UCDORM Bit Offset */ -#define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /*!< Dormant */ -/* EUSCI_A_CTLW0[BRKIE] Bits */ -#define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /*!< UCBRKIE Bit Offset */ -#define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /*!< Receive break character interrupt enable */ -/* EUSCI_A_CTLW0[RXEIE] Bits */ -#define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /*!< UCRXEIE Bit Offset */ -#define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /*!< Receive erroneous-character interrupt enable */ -/* EUSCI_A_CTLW0[SSEL] Bits */ -#define EUSCI_A_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -/* EUSCI_A_CTLW0[SYNC] Bits */ -#define EUSCI_A_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -/* EUSCI_A_CTLW0[MODE] Bits */ -#define EUSCI_A_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< UART mode */ -#define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< Idle-line multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< Address-bit multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< UART mode with automatic baud-rate detection */ -/* EUSCI_A_CTLW0[SPB] Bits */ -#define EUSCI_A_CTLW0_SPB_OFS (11) /*!< UCSPB Bit Offset */ -#define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /*!< Stop bit select */ -/* EUSCI_A_CTLW0[SEVENBIT] Bits */ -#define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -/* EUSCI_A_CTLW0[MSB] Bits */ -#define EUSCI_A_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -/* EUSCI_A_CTLW0[PAR] Bits */ -#define EUSCI_A_CTLW0_PAR_OFS (14) /*!< UCPAR Bit Offset */ -#define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /*!< Parity select */ -/* EUSCI_A_CTLW0[PEN] Bits */ -#define EUSCI_A_CTLW0_PEN_OFS (15) /*!< UCPEN Bit Offset */ -#define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /*!< Parity enable */ -/* EUSCI_A_CTLW0[STEM] Bits */ -#define EUSCI_A_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -/* EUSCI_A_CTLW0[MST] Bits */ -#define EUSCI_A_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -/* EUSCI_A_CTLW0[CKPL] Bits */ -#define EUSCI_A_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -/* EUSCI_A_CTLW0[CKPH] Bits */ -#define EUSCI_A_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -/* EUSCI_A_CTLW1[GLIT] Bits */ -#define EUSCI_A_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< Approximately 2 ns (equivalent of 1 delay element) */ -#define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< Approximately 50 ns */ -#define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< Approximately 100 ns */ -#define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< Approximately 200 ns */ -/* EUSCI_A_MCTLW[OS16] Bits */ -#define EUSCI_A_MCTLW_OS16_OFS ( 0) /*!< UCOS16 Bit Offset */ -#define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /*!< Oversampling mode enabled */ -/* EUSCI_A_MCTLW[BRF] Bits */ -#define EUSCI_A_MCTLW_BRF_OFS ( 4) /*!< UCBRF Bit Offset */ -#define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /*!< UCBRF Bit Mask */ -/* EUSCI_A_MCTLW[BRS] Bits */ -#define EUSCI_A_MCTLW_BRS_OFS ( 8) /*!< UCBRS Bit Offset */ -#define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /*!< UCBRS Bit Mask */ -/* EUSCI_A_STATW[BUSY] Bits */ -#define EUSCI_A_STATW_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -/* EUSCI_A_STATW[ADDR_IDLE] Bits */ -#define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /*!< UCADDR_UCIDLE Bit Offset */ -#define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /*!< Address received / Idle line detected */ -/* EUSCI_A_STATW[RXERR] Bits */ -#define EUSCI_A_STATW_RXERR_OFS ( 2) /*!< UCRXERR Bit Offset */ -#define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /*!< Receive error flag */ -/* EUSCI_A_STATW[BRK] Bits */ -#define EUSCI_A_STATW_BRK_OFS ( 3) /*!< UCBRK Bit Offset */ -#define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /*!< Break detect flag */ -/* EUSCI_A_STATW[PE] Bits */ -#define EUSCI_A_STATW_PE_OFS ( 4) /*!< UCPE Bit Offset */ -#define EUSCI_A_STATW_PE ((uint16_t)0x0010) -/* EUSCI_A_STATW[OE] Bits */ -#define EUSCI_A_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_A_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -/* EUSCI_A_STATW[FE] Bits */ -#define EUSCI_A_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_A_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -/* EUSCI_A_STATW[LISTEN] Bits */ -#define EUSCI_A_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -/* EUSCI_A_STATW[SPI_BUSY] Bits */ -#define EUSCI_A_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -/* EUSCI_A_RXBUF[RXBUF] Bits */ -#define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -/* EUSCI_A_TXBUF[TXBUF] Bits */ -#define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -/* EUSCI_A_ABCTL[ABDEN] Bits */ -#define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /*!< UCABDEN Bit Offset */ -#define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /*!< Automatic baud-rate detect enable */ -/* EUSCI_A_ABCTL[BTOE] Bits */ -#define EUSCI_A_ABCTL_BTOE_OFS ( 2) /*!< UCBTOE Bit Offset */ -#define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /*!< Break time out error */ -/* EUSCI_A_ABCTL[STOE] Bits */ -#define EUSCI_A_ABCTL_STOE_OFS ( 3) /*!< UCSTOE Bit Offset */ -#define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /*!< Synch field time out error */ -/* EUSCI_A_ABCTL[DELIM] Bits */ -#define EUSCI_A_ABCTL_DELIM_OFS ( 4) /*!< UCDELIM Bit Offset */ -#define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /*!< UCDELIM Bit Mask */ -#define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /*!< DELIM Bit 0 */ -#define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /*!< DELIM Bit 1 */ -#define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /*!< 1 bit time */ -#define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /*!< 2 bit times */ -#define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /*!< 3 bit times */ -#define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /*!< 4 bit times */ -/* EUSCI_A_IRCTL[IREN] Bits */ -#define EUSCI_A_IRCTL_IREN_OFS ( 0) /*!< UCIREN Bit Offset */ -#define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /*!< IrDA encoder/decoder enable */ -/* EUSCI_A_IRCTL[IRTXCLK] Bits */ -#define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /*!< UCIRTXCLK Bit Offset */ -#define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /*!< IrDA transmit pulse clock select */ -/* EUSCI_A_IRCTL[IRTXPL] Bits */ -#define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /*!< UCIRTXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /*!< UCIRTXPL Bit Mask */ -/* EUSCI_A_IRCTL[IRRXFE] Bits */ -#define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /*!< UCIRRXFE Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /*!< IrDA receive filter enabled */ -/* EUSCI_A_IRCTL[IRRXPL] Bits */ -#define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /*!< UCIRRXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /*!< IrDA receive input UCAxRXD polarity */ -/* EUSCI_A_IRCTL[IRRXFL] Bits */ -#define EUSCI_A_IRCTL_IRRXFL_OFS (10) /*!< UCIRRXFL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /*!< UCIRRXFL Bit Mask */ -/* EUSCI_A_IE[RXIE] Bits */ -#define EUSCI_A_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -/* EUSCI_A_IE[TXIE] Bits */ -#define EUSCI_A_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -/* EUSCI_A_IE[STTIE] Bits */ -#define EUSCI_A_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /*!< Start bit interrupt enable */ -/* EUSCI_A_IE[TXCPTIE] Bits */ -#define EUSCI_A_IE_TXCPTIE_OFS ( 3) /*!< UCTXCPTIE Bit Offset */ -#define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /*!< Transmit complete interrupt enable */ -/* EUSCI_A_IFG[RXIFG] Bits */ -#define EUSCI_A_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -/* EUSCI_A_IFG[TXIFG] Bits */ -#define EUSCI_A_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -/* EUSCI_A_IFG[STTIFG] Bits */ -#define EUSCI_A_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /*!< Start bit interrupt flag */ -/* EUSCI_A_IFG[TXCPTIFG] Bits */ -#define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /*!< UCTXCPTIFG Bit Offset */ -#define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /*!< Transmit ready interrupt enable */ -/* legacy definitions for backward compatibility to version 2100 */ -#define EUSCI_A__RXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_A__RXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_A__TXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_A__TXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ - - -/****************************************************************************** -* EUSCI_B Bits -******************************************************************************/ -/* EUSCI_B_CTLW0[SWRST] Bits */ -#define EUSCI_B_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -/* EUSCI_B_CTLW0[TXSTT] Bits */ -#define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /*!< UCTXSTT Bit Offset */ -#define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /*!< Transmit START condition in master mode */ -/* EUSCI_B_CTLW0[TXSTP] Bits */ -#define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /*!< UCTXSTP Bit Offset */ -#define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /*!< Transmit STOP condition in master mode */ -/* EUSCI_B_CTLW0[TXNACK] Bits */ -#define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /*!< UCTXNACK Bit Offset */ -#define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /*!< Transmit a NACK */ -/* EUSCI_B_CTLW0[TR] Bits */ -#define EUSCI_B_CTLW0_TR_OFS ( 4) /*!< UCTR Bit Offset */ -#define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /*!< Transmitter/receiver */ -/* EUSCI_B_CTLW0[TXACK] Bits */ -#define EUSCI_B_CTLW0_TXACK_OFS ( 5) /*!< UCTXACK Bit Offset */ -#define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /*!< Transmit ACK condition in slave mode */ -/* EUSCI_B_CTLW0[SSEL] Bits */ -#define EUSCI_B_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_B_CTLW0_UCSSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ -#define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -/* EUSCI_B_CTLW0[SYNC] Bits */ -#define EUSCI_B_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -/* EUSCI_B_CTLW0[MODE] Bits */ -#define EUSCI_B_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< 3-pin SPI */ -#define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< 4-pin SPI (master or slave enabled if STE = 1) */ -#define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< 4-pin SPI (master or slave enabled if STE = 0) */ -#define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< I2C mode */ -/* EUSCI_B_CTLW0[MST] Bits */ -#define EUSCI_B_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -/* EUSCI_B_CTLW0[MM] Bits */ -#define EUSCI_B_CTLW0_MM_OFS (13) /*!< UCMM Bit Offset */ -#define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /*!< Multi-master environment select */ -/* EUSCI_B_CTLW0[SLA10] Bits */ -#define EUSCI_B_CTLW0_SLA10_OFS (14) /*!< UCSLA10 Bit Offset */ -#define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /*!< Slave addressing mode select */ -/* EUSCI_B_CTLW0[A10] Bits */ -#define EUSCI_B_CTLW0_A10_OFS (15) /*!< UCA10 Bit Offset */ -#define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /*!< Own addressing mode select */ -/* EUSCI_B_CTLW0[STEM] Bits */ -#define EUSCI_B_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -/* EUSCI_B_CTLW0[SEVENBIT] Bits */ -#define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -/* EUSCI_B_CTLW0[MSB] Bits */ -#define EUSCI_B_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -/* EUSCI_B_CTLW0[CKPL] Bits */ -#define EUSCI_B_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -/* EUSCI_B_CTLW0[CKPH] Bits */ -#define EUSCI_B_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -/* EUSCI_B_CTLW1[GLIT] Bits */ -#define EUSCI_B_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< 50 ns */ -#define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< 25 ns */ -#define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< 12.5 ns */ -#define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< 6.25 ns */ -/* EUSCI_B_CTLW1[ASTP] Bits */ -#define EUSCI_B_CTLW1_ASTP_OFS ( 2) /*!< UCASTP Bit Offset */ -#define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /*!< UCASTP Bit Mask */ -#define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /*!< ASTP Bit 0 */ -#define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /*!< ASTP Bit 1 */ -#define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /*!< No automatic STOP generation. The STOP condition is generated after the user */ - /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ -#define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ - /* UCBxTBCNT */ -#define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /*!< A STOP condition is generated automatically after the byte counter value */ - /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ - /* threshold */ -/* EUSCI_B_CTLW1[SWACK] Bits */ -#define EUSCI_B_CTLW1_SWACK_OFS ( 4) /*!< UCSWACK Bit Offset */ -#define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /*!< SW or HW ACK control */ -/* EUSCI_B_CTLW1[STPNACK] Bits */ -#define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /*!< UCSTPNACK Bit Offset */ -#define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /*!< ACK all master bytes */ -/* EUSCI_B_CTLW1[CLTO] Bits */ -#define EUSCI_B_CTLW1_CLTO_OFS ( 6) /*!< UCCLTO Bit Offset */ -#define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /*!< UCCLTO Bit Mask */ -#define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /*!< CLTO Bit 0 */ -#define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /*!< CLTO Bit 1 */ -#define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /*!< Disable clock low timeout counter */ -#define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ -#define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ -#define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ -/* EUSCI_B_CTLW1[ETXINT] Bits */ -#define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /*!< UCETXINT Bit Offset */ -#define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /*!< Early UCTXIFG0 */ -/* EUSCI_B_STATW[BBUSY] Bits */ -#define EUSCI_B_STATW_BBUSY_OFS ( 4) /*!< UCBBUSY Bit Offset */ -#define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /*!< Bus busy */ -/* EUSCI_B_STATW[GC] Bits */ -#define EUSCI_B_STATW_GC_OFS ( 5) /*!< UCGC Bit Offset */ -#define EUSCI_B_STATW_GC ((uint16_t)0x0020) /*!< General call address received */ -/* EUSCI_B_STATW[SCLLOW] Bits */ -#define EUSCI_B_STATW_SCLLOW_OFS ( 6) /*!< UCSCLLOW Bit Offset */ -#define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /*!< SCL low */ -/* EUSCI_B_STATW[BCNT] Bits */ -#define EUSCI_B_STATW_BCNT_OFS ( 8) /*!< UCBCNT Bit Offset */ -#define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /*!< UCBCNT Bit Mask */ -/* EUSCI_B_STATW[SPI_BUSY] Bits */ -#define EUSCI_B_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_B_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_B busy */ -/* EUSCI_B_STATW[OE] Bits */ -#define EUSCI_B_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_B_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -/* EUSCI_B_STATW[FE] Bits */ -#define EUSCI_B_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_B_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -/* EUSCI_B_STATW[LISTEN] Bits */ -#define EUSCI_B_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -/* EUSCI_B_TBCNT[TBCNT] Bits */ -#define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /*!< UCTBCNT Bit Offset */ -#define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /*!< UCTBCNT Bit Mask */ -/* EUSCI_B_RXBUF[RXBUF] Bits */ -#define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -/* EUSCI_B_TXBUF[TXBUF] Bits */ -#define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -/* EUSCI_B_I2COA0[I2COA0] Bits */ -#define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /*!< I2COA0 Bit Offset */ -#define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /*!< I2COA0 Bit Mask */ -/* EUSCI_B_I2COA0[OAEN] Bits */ -#define EUSCI_B_I2COA0_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA0[GCEN] Bits */ -#define EUSCI_B_I2COA0_GCEN_OFS (15) /*!< UCGCEN Bit Offset */ -#define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /*!< General call response enable */ -/* EUSCI_B_I2COA1[I2COA1] Bits */ -#define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /*!< I2COA1 Bit Offset */ -#define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /*!< I2COA1 Bit Mask */ -/* EUSCI_B_I2COA1[OAEN] Bits */ -#define EUSCI_B_I2COA1_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA2[I2COA2] Bits */ -#define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /*!< I2COA2 Bit Offset */ -#define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /*!< I2COA2 Bit Mask */ -/* EUSCI_B_I2COA2[OAEN] Bits */ -#define EUSCI_B_I2COA2_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA3[I2COA3] Bits */ -#define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /*!< I2COA3 Bit Offset */ -#define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /*!< I2COA3 Bit Mask */ -/* EUSCI_B_I2COA3[OAEN] Bits */ -#define EUSCI_B_I2COA3_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_ADDRX[ADDRX] Bits */ -#define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /*!< ADDRX Bit Offset */ -#define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /*!< ADDRX Bit Mask */ -#define EUSCI_B_ADDRX_ADDRX0 ((uint16_t)0x0001) /*!< ADDRX Bit 0 */ -#define EUSCI_B_ADDRX_ADDRX1 ((uint16_t)0x0002) /*!< ADDRX Bit 1 */ -#define EUSCI_B_ADDRX_ADDRX2 ((uint16_t)0x0004) /*!< ADDRX Bit 2 */ -#define EUSCI_B_ADDRX_ADDRX3 ((uint16_t)0x0008) /*!< ADDRX Bit 3 */ -#define EUSCI_B_ADDRX_ADDRX4 ((uint16_t)0x0010) /*!< ADDRX Bit 4 */ -#define EUSCI_B_ADDRX_ADDRX5 ((uint16_t)0x0020) /*!< ADDRX Bit 5 */ -#define EUSCI_B_ADDRX_ADDRX6 ((uint16_t)0x0040) /*!< ADDRX Bit 6 */ -#define EUSCI_B_ADDRX_ADDRX7 ((uint16_t)0x0080) /*!< ADDRX Bit 7 */ -#define EUSCI_B_ADDRX_ADDRX8 ((uint16_t)0x0100) /*!< ADDRX Bit 8 */ -#define EUSCI_B_ADDRX_ADDRX9 ((uint16_t)0x0200) /*!< ADDRX Bit 9 */ -/* EUSCI_B_ADDMASK[ADDMASK] Bits */ -#define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /*!< ADDMASK Bit Offset */ -#define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /*!< ADDMASK Bit Mask */ -/* EUSCI_B_I2CSA[I2CSA] Bits */ -#define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /*!< I2CSA Bit Offset */ -#define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /*!< I2CSA Bit Mask */ -/* EUSCI_B_IE[RXIE0] Bits */ -#define EUSCI_B_IE_RXIE0_OFS ( 0) /*!< UCRXIE0 Bit Offset */ -#define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /*!< Receive interrupt enable 0 */ -/* EUSCI_B_IE[TXIE0] Bits */ -#define EUSCI_B_IE_TXIE0_OFS ( 1) /*!< UCTXIE0 Bit Offset */ -#define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /*!< Transmit interrupt enable 0 */ -/* EUSCI_B_IE[STTIE] Bits */ -#define EUSCI_B_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /*!< START condition interrupt enable */ -/* EUSCI_B_IE[STPIE] Bits */ -#define EUSCI_B_IE_STPIE_OFS ( 3) /*!< UCSTPIE Bit Offset */ -#define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /*!< STOP condition interrupt enable */ -/* EUSCI_B_IE[ALIE] Bits */ -#define EUSCI_B_IE_ALIE_OFS ( 4) /*!< UCALIE Bit Offset */ -#define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /*!< Arbitration lost interrupt enable */ -/* EUSCI_B_IE[NACKIE] Bits */ -#define EUSCI_B_IE_NACKIE_OFS ( 5) /*!< UCNACKIE Bit Offset */ -#define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /*!< Not-acknowledge interrupt enable */ -/* EUSCI_B_IE[BCNTIE] Bits */ -#define EUSCI_B_IE_BCNTIE_OFS ( 6) /*!< UCBCNTIE Bit Offset */ -#define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /*!< Byte counter interrupt enable */ -/* EUSCI_B_IE[CLTOIE] Bits */ -#define EUSCI_B_IE_CLTOIE_OFS ( 7) /*!< UCCLTOIE Bit Offset */ -#define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /*!< Clock low timeout interrupt enable */ -/* EUSCI_B_IE[RXIE1] Bits */ -#define EUSCI_B_IE_RXIE1_OFS ( 8) /*!< UCRXIE1 Bit Offset */ -#define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /*!< Receive interrupt enable 1 */ -/* EUSCI_B_IE[TXIE1] Bits */ -#define EUSCI_B_IE_TXIE1_OFS ( 9) /*!< UCTXIE1 Bit Offset */ -#define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /*!< Transmit interrupt enable 1 */ -/* EUSCI_B_IE[RXIE2] Bits */ -#define EUSCI_B_IE_RXIE2_OFS (10) /*!< UCRXIE2 Bit Offset */ -#define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /*!< Receive interrupt enable 2 */ -/* EUSCI_B_IE[TXIE2] Bits */ -#define EUSCI_B_IE_TXIE2_OFS (11) /*!< UCTXIE2 Bit Offset */ -#define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /*!< Transmit interrupt enable 2 */ -/* EUSCI_B_IE[RXIE3] Bits */ -#define EUSCI_B_IE_RXIE3_OFS (12) /*!< UCRXIE3 Bit Offset */ -#define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /*!< Receive interrupt enable 3 */ -/* EUSCI_B_IE[TXIE3] Bits */ -#define EUSCI_B_IE_TXIE3_OFS (13) /*!< UCTXIE3 Bit Offset */ -#define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /*!< Transmit interrupt enable 3 */ -/* EUSCI_B_IE[BIT9IE] Bits */ -#define EUSCI_B_IE_BIT9IE_OFS (14) /*!< UCBIT9IE Bit Offset */ -#define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /*!< Bit position 9 interrupt enable */ -/* EUSCI_B_IE[RXIE] Bits */ -#define EUSCI_B_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_B_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -/* EUSCI_B_IE[TXIE] Bits */ -#define EUSCI_B_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_B_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -/* EUSCI_B_IFG[RXIFG0] Bits */ -#define EUSCI_B_IFG_RXIFG0_OFS ( 0) /*!< UCRXIFG0 Bit Offset */ -#define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /*!< eUSCI_B receive interrupt flag 0 */ -/* EUSCI_B_IFG[TXIFG0] Bits */ -#define EUSCI_B_IFG_TXIFG0_OFS ( 1) /*!< UCTXIFG0 Bit Offset */ -#define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /*!< eUSCI_B transmit interrupt flag 0 */ -/* EUSCI_B_IFG[STTIFG] Bits */ -#define EUSCI_B_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /*!< START condition interrupt flag */ -/* EUSCI_B_IFG[STPIFG] Bits */ -#define EUSCI_B_IFG_STPIFG_OFS ( 3) /*!< UCSTPIFG Bit Offset */ -#define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /*!< STOP condition interrupt flag */ -/* EUSCI_B_IFG[ALIFG] Bits */ -#define EUSCI_B_IFG_ALIFG_OFS ( 4) /*!< UCALIFG Bit Offset */ -#define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /*!< Arbitration lost interrupt flag */ -/* EUSCI_B_IFG[NACKIFG] Bits */ -#define EUSCI_B_IFG_NACKIFG_OFS ( 5) /*!< UCNACKIFG Bit Offset */ -#define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /*!< Not-acknowledge received interrupt flag */ -/* EUSCI_B_IFG[BCNTIFG] Bits */ -#define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /*!< UCBCNTIFG Bit Offset */ -#define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /*!< Byte counter interrupt flag */ -/* EUSCI_B_IFG[CLTOIFG] Bits */ -#define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /*!< UCCLTOIFG Bit Offset */ -#define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /*!< Clock low timeout interrupt flag */ -/* EUSCI_B_IFG[RXIFG1] Bits */ -#define EUSCI_B_IFG_RXIFG1_OFS ( 8) /*!< UCRXIFG1 Bit Offset */ -#define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /*!< eUSCI_B receive interrupt flag 1 */ -/* EUSCI_B_IFG[TXIFG1] Bits */ -#define EUSCI_B_IFG_TXIFG1_OFS ( 9) /*!< UCTXIFG1 Bit Offset */ -#define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /*!< eUSCI_B transmit interrupt flag 1 */ -/* EUSCI_B_IFG[RXIFG2] Bits */ -#define EUSCI_B_IFG_RXIFG2_OFS (10) /*!< UCRXIFG2 Bit Offset */ -#define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /*!< eUSCI_B receive interrupt flag 2 */ -/* EUSCI_B_IFG[TXIFG2] Bits */ -#define EUSCI_B_IFG_TXIFG2_OFS (11) /*!< UCTXIFG2 Bit Offset */ -#define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /*!< eUSCI_B transmit interrupt flag 2 */ -/* EUSCI_B_IFG[RXIFG3] Bits */ -#define EUSCI_B_IFG_RXIFG3_OFS (12) /*!< UCRXIFG3 Bit Offset */ -#define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /*!< eUSCI_B receive interrupt flag 3 */ -/* EUSCI_B_IFG[TXIFG3] Bits */ -#define EUSCI_B_IFG_TXIFG3_OFS (13) /*!< UCTXIFG3 Bit Offset */ -#define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /*!< eUSCI_B transmit interrupt flag 3 */ -/* EUSCI_B_IFG[BIT9IFG] Bits */ -#define EUSCI_B_IFG_BIT9IFG_OFS (14) /*!< UCBIT9IFG Bit Offset */ -#define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /*!< Bit position 9 interrupt flag */ -/* EUSCI_B_IFG[RXIFG] Bits */ -#define EUSCI_B_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -/* EUSCI_B_IFG[TXIFG] Bits */ -#define EUSCI_B_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -/* legacy definitions for backward compatibility to version 2100 */ -#define EUSCI_B__RXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_B__RXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_B__TXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_B__TXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ - - -/****************************************************************************** -* FLCTL_A Bits -******************************************************************************/ -/* FLCTL_A_POWER_STAT[PSTAT] Bits */ -#define FLCTL_A_POWER_STAT_PSTAT_OFS ( 0) /*!< PSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /*!< PSTAT Bit Mask */ -#define FLCTL_A_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /*!< PSTAT Bit 0 */ -#define FLCTL_A_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /*!< PSTAT Bit 1 */ -#define FLCTL_A_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /*!< PSTAT Bit 2 */ -#define FLCTL_A_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /*!< Flash IP in power-down mode */ -#define FLCTL_A_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /*!< Flash IP Vdd domain power-up in progress */ -#define FLCTL_A_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */ -#define FLCTL_A_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /*!< Flash IP SAFE_LV check in progress */ -#define FLCTL_A_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /*!< Flash IP Active */ -#define FLCTL_A_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */ -#define FLCTL_A_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /*!< Flash IP in Standby mode */ -#define FLCTL_A_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /*!< Flash IP in Current mirror boost state */ -/* FLCTL_A_POWER_STAT[LDOSTAT] Bits */ -#define FLCTL_A_POWER_STAT_LDOSTAT_OFS ( 3) /*!< LDOSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /*!< PSS FLDO GOOD status */ -/* FLCTL_A_POWER_STAT[VREFSTAT] Bits */ -#define FLCTL_A_POWER_STAT_VREFSTAT_OFS ( 4) /*!< VREFSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /*!< PSS VREF stable status */ -/* FLCTL_A_POWER_STAT[IREFSTAT] Bits */ -#define FLCTL_A_POWER_STAT_IREFSTAT_OFS ( 5) /*!< IREFSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /*!< PSS IREF stable status */ -/* FLCTL_A_POWER_STAT[TRIMSTAT] Bits */ -#define FLCTL_A_POWER_STAT_TRIMSTAT_OFS ( 6) /*!< TRIMSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /*!< PSS trim done status */ -/* FLCTL_A_POWER_STAT[RD_2T] Bits */ -#define FLCTL_A_POWER_STAT_RD_2T_OFS ( 7) /*!< RD_2T Bit Offset */ -#define FLCTL_A_POWER_STAT_RD_2T ((uint32_t)0x00000080) /*!< Indicates if Flash is being accessed in 2T mode */ -/* FLCTL_A_BANK0_RDCTL[RD_MODE] Bits */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -/* FLCTL_A_BANK0_RDCTL[BUFI] Bits */ -#define FLCTL_A_BANK0_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -/* FLCTL_A_BANK0_RDCTL[BUFD] Bits */ -#define FLCTL_A_BANK0_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -/* FLCTL_A_BANK0_RDCTL[WAIT] Bits */ -#define FLCTL_A_BANK0_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_A_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_A_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_A_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_A_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_A_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -/* FLCTL_A_BANK0_RDCTL[RD_MODE_STATUS] Bits */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -/* FLCTL_A_BANK1_RDCTL[RD_MODE] Bits */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -/* FLCTL_A_BANK1_RDCTL[BUFI] Bits */ -#define FLCTL_A_BANK1_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -/* FLCTL_A_BANK1_RDCTL[BUFD] Bits */ -#define FLCTL_A_BANK1_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -/* FLCTL_A_BANK1_RDCTL[RD_MODE_STATUS] Bits */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -/* FLCTL_A_BANK1_RDCTL[WAIT] Bits */ -#define FLCTL_A_BANK1_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_A_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_A_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_A_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_A_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_A_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -/* FLCTL_A_RDBRST_CTLSTAT[START] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of burst/compare operation */ -/* FLCTL_A_RDBRST_CTLSTAT[MEM_TYPE] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /*!< MEM_TYPE Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /*!< MEM_TYPE Bit Mask */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /*!< MEM_TYPE Bit 0 */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /*!< MEM_TYPE Bit 1 */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -/* FLCTL_A_RDBRST_CTLSTAT[STOP_FAIL] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /*!< STOP_FAIL Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /*!< Terminate burst/compare operation */ -/* FLCTL_A_RDBRST_CTLSTAT[DATA_CMP] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /*!< DATA_CMP Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /*!< Data pattern used for comparison against memory read data */ -/* FLCTL_A_RDBRST_CTLSTAT[TEST_EN] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /*!< TEST_EN Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /*!< Enable comparison against test data compare registers */ -/* FLCTL_A_RDBRST_CTLSTAT[BRST_STAT] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /*!< BRST_STAT Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /*!< BRST_STAT Bit Mask */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /*!< BRST_STAT Bit 0 */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /*!< BRST_STAT Bit 1 */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /*!< Idle */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /*!< Burst/Compare START bit written, but operation pending */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /*!< Burst/Compare in progress */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /*!< Burst complete (status of completed burst remains in this state unless */ - /* explicitly cleared by SW) */ -/* FLCTL_A_RDBRST_CTLSTAT[CMP_ERR] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /*!< CMP_ERR Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /*!< Burst/Compare Operation encountered atleast one data */ -/* FLCTL_A_RDBRST_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /*!< Burst/Compare Operation was terminated due to access to */ -/* FLCTL_A_RDBRST_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 19-16 of this register */ -/* FLCTL_A_RDBRST_STARTADDR[START_ADDRESS] Bits */ -#define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< START_ADDRESS Bit Mask */ -/* FLCTL_A_RDBRST_LEN[BURST_LENGTH] Bits */ -#define FLCTL_A_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /*!< BURST_LENGTH Bit Offset */ -#define FLCTL_A_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /*!< BURST_LENGTH Bit Mask */ -/* FLCTL_A_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */ -#define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /*!< FAIL_ADDRESS Bit Offset */ -#define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< FAIL_ADDRESS Bit Mask */ -/* FLCTL_A_RDBRST_FAILCNT[FAIL_COUNT] Bits */ -#define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /*!< FAIL_COUNT Bit Offset */ -#define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /*!< FAIL_COUNT Bit Mask */ -/* FLCTL_A_PRG_CTLSTAT[ENABLE] Bits */ -#define FLCTL_A_PRG_CTLSTAT_ENABLE_OFS ( 0) /*!< ENABLE Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /*!< Master control for all word program operations */ -/* FLCTL_A_PRG_CTLSTAT[MODE] Bits */ -#define FLCTL_A_PRG_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Write mode */ -/* FLCTL_A_PRG_CTLSTAT[VER_PRE] Bits */ -#define FLCTL_A_PRG_CTLSTAT_VER_PRE_OFS ( 2) /*!< VER_PRE Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /*!< Controls automatic pre program verify operations */ -/* FLCTL_A_PRG_CTLSTAT[VER_PST] Bits */ -#define FLCTL_A_PRG_CTLSTAT_VER_PST_OFS ( 3) /*!< VER_PST Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /*!< Controls automatic post program verify operations */ -/* FLCTL_A_PRG_CTLSTAT[STATUS] Bits */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_A_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_A_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Single word program operation triggered, but pending */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Single word program in progress */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Reserved (Idle) */ -/* FLCTL_A_PRG_CTLSTAT[BNK_ACT] Bits */ -#define FLCTL_A_PRG_CTLSTAT_BNK_ACT_OFS (18) /*!< BNK_ACT Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /*!< Bank active */ -/* FLCTL_A_PRGBRST_CTLSTAT[START] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Trigger start of burst program operation */ -/* FLCTL_A_PRGBRST_CTLSTAT[TYPE] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /*!< TYPE Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /*!< TYPE Bit Mask */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /*!< TYPE Bit 0 */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /*!< TYPE Bit 1 */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -/* FLCTL_A_PRGBRST_CTLSTAT[LEN] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_OFS ( 3) /*!< LEN Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /*!< LEN Bit Mask */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /*!< LEN Bit 0 */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /*!< LEN Bit 1 */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /*!< LEN Bit 2 */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /*!< No burst operation */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /*!< 1 word burst of 128 bits, starting with address in the */ - /* FLCTL_PRGBRST_STARTADDR Register */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -/* FLCTL_A_PRGBRST_CTLSTAT[AUTO_PRE] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /*!< AUTO_PRE Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /*!< Auto-Verify operation before the Burst Program */ -/* FLCTL_A_PRGBRST_CTLSTAT[AUTO_PST] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /*!< AUTO_PST Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /*!< Auto-Verify operation after the Burst Program */ -/* FLCTL_A_PRGBRST_CTLSTAT[BURST_STATUS] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /*!< BURST_STATUS Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /*!< BURST_STATUS Bit Mask */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /*!< BURST_STATUS Bit 0 */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /*!< BURST_STATUS Bit 1 */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /*!< BURST_STATUS Bit 2 */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (Burst not active) */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /*!< Burst program started but pending */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /*!< Burst active, with 1st 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /*!< Burst active, with 2nd 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /*!< Burst active, with 3rd 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /*!< Burst active, with 4th 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /*!< Reserved (Idle) */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /*!< Burst Complete (status of completed burst remains in this state unless */ - /* explicitly cleared by SW) */ -/* FLCTL_A_PRGBRST_CTLSTAT[PRE_ERR] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /*!< PRE_ERR Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /*!< Burst Operation encountered preprogram auto-verify errors */ -/* FLCTL_A_PRGBRST_CTLSTAT[PST_ERR] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /*!< PST_ERR Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /*!< Burst Operation encountered postprogram auto-verify errors */ -/* FLCTL_A_PRGBRST_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /*!< Burst Operation was terminated due to attempted program of reserved memory */ -/* FLCTL_A_PRGBRST_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 21-16 of this register */ -/* FLCTL_A_PRGBRST_STARTADDR[START_ADDRESS] Bits */ -#define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< START_ADDRESS Bit Mask */ -/* FLCTL_A_ERASE_CTLSTAT[START] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of Erase operation */ -/* FLCTL_A_ERASE_CTLSTAT[MODE] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Erase mode selected by application */ -/* FLCTL_A_ERASE_CTLSTAT[TYPE] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_OFS ( 2) /*!< TYPE Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /*!< TYPE Bit Mask */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /*!< TYPE Bit 0 */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /*!< TYPE Bit 1 */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /*!< Information Memory */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /*!< Reserved */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /*!< Engineering Memory */ -/* FLCTL_A_ERASE_CTLSTAT[STATUS] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Erase operation triggered to START but pending */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Erase operation in progress */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Erase operation completed (status of completed erase remains in this state */ - /* unless explicitly cleared by SW) */ -/* FLCTL_A_ERASE_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /*!< Erase Operation was terminated due to attempted erase of reserved memory */ - /* address */ -/* FLCTL_A_ERASE_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS (19) /*!< CLR_STAT Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /*!< Clear status bits 18-16 of this register */ -/* FLCTL_A_ERASE_SECTADDR[SECT_ADDRESS] Bits */ -#define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /*!< SECT_ADDRESS Bit Offset */ -#define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< SECT_ADDRESS Bit Mask */ -/* FLCTL_A_BANK0_INFO_WEPROT[PROT0] Bits */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_A_BANK0_INFO_WEPROT[PROT1] Bits */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_A_BANK0_INFO_WEPROT[PROT2] Bits */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK0_INFO_WEPROT[PROT3] Bits */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT0] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT1] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT2] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT3] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT4] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT5] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT6] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT7] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT8] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT9] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT10] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT11] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT12] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT13] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT14] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT15] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT16] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT17] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT18] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT19] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT20] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT21] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT22] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT23] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT24] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT25] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT26] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT27] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT28] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT29] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT30] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT31] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -/* FLCTL_A_BANK1_INFO_WEPROT[PROT0] Bits */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -/* FLCTL_A_BANK1_INFO_WEPROT[PROT1] Bits */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -/* FLCTL_A_BANK1_INFO_WEPROT[PROT2] Bits */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK1_INFO_WEPROT[PROT3] Bits */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT0] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT1] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT2] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT3] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT4] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT5] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT6] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT7] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT8] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT9] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT10] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT11] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT12] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT13] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT14] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT15] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT16] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT17] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT18] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT19] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT20] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT21] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT22] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT23] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT24] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT25] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT26] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT27] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT28] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT29] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT30] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT31] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase operations */ -/* FLCTL_A_BMRK_CTLSTAT[I_BMRK] Bits */ -#define FLCTL_A_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /*!< I_BMRK Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001) -/* FLCTL_A_BMRK_CTLSTAT[D_BMRK] Bits */ -#define FLCTL_A_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /*!< D_BMRK Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002) -/* FLCTL_A_BMRK_CTLSTAT[CMP_EN] Bits */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /*!< CMP_EN Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004) -/* FLCTL_A_BMRK_CTLSTAT[CMP_SEL] Bits */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /*!< CMP_SEL Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008) -/* FLCTL_A_IFG[RDBRST] Bits */ -#define FLCTL_A_IFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_IFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_A_IFG[AVPRE] Bits */ -#define FLCTL_A_IFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_IFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_A_IFG[AVPST] Bits */ -#define FLCTL_A_IFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_IFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_A_IFG[PRG] Bits */ -#define FLCTL_A_IFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_IFG_PRG ((uint32_t)0x00000008) -/* FLCTL_A_IFG[PRGB] Bits */ -#define FLCTL_A_IFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_IFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_A_IFG[ERASE] Bits */ -#define FLCTL_A_IFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_IFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_A_IFG[BMRK] Bits */ -#define FLCTL_A_IFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_IFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_A_IFG[PRG_ERR] Bits */ -#define FLCTL_A_IFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_IFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_A_IE[RDBRST] Bits */ -#define FLCTL_A_IE_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_IE_RDBRST ((uint32_t)0x00000001) -/* FLCTL_A_IE[AVPRE] Bits */ -#define FLCTL_A_IE_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_IE_AVPRE ((uint32_t)0x00000002) -/* FLCTL_A_IE[AVPST] Bits */ -#define FLCTL_A_IE_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_IE_AVPST ((uint32_t)0x00000004) -/* FLCTL_A_IE[PRG] Bits */ -#define FLCTL_A_IE_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_IE_PRG ((uint32_t)0x00000008) -/* FLCTL_A_IE[PRGB] Bits */ -#define FLCTL_A_IE_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_IE_PRGB ((uint32_t)0x00000010) -/* FLCTL_A_IE[ERASE] Bits */ -#define FLCTL_A_IE_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_IE_ERASE ((uint32_t)0x00000020) -/* FLCTL_A_IE[BMRK] Bits */ -#define FLCTL_A_IE_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_IE_BMRK ((uint32_t)0x00000100) -/* FLCTL_A_IE[PRG_ERR] Bits */ -#define FLCTL_A_IE_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_IE_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_A_CLRIFG[RDBRST] Bits */ -#define FLCTL_A_CLRIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_CLRIFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_A_CLRIFG[AVPRE] Bits */ -#define FLCTL_A_CLRIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_CLRIFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_A_CLRIFG[AVPST] Bits */ -#define FLCTL_A_CLRIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_CLRIFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_A_CLRIFG[PRG] Bits */ -#define FLCTL_A_CLRIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_CLRIFG_PRG ((uint32_t)0x00000008) -/* FLCTL_A_CLRIFG[PRGB] Bits */ -#define FLCTL_A_CLRIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_CLRIFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_A_CLRIFG[ERASE] Bits */ -#define FLCTL_A_CLRIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_CLRIFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_A_CLRIFG[BMRK] Bits */ -#define FLCTL_A_CLRIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_CLRIFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_A_CLRIFG[PRG_ERR] Bits */ -#define FLCTL_A_CLRIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_CLRIFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_A_SETIFG[RDBRST] Bits */ -#define FLCTL_A_SETIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_SETIFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_A_SETIFG[AVPRE] Bits */ -#define FLCTL_A_SETIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_SETIFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_A_SETIFG[AVPST] Bits */ -#define FLCTL_A_SETIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_SETIFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_A_SETIFG[PRG] Bits */ -#define FLCTL_A_SETIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_SETIFG_PRG ((uint32_t)0x00000008) -/* FLCTL_A_SETIFG[PRGB] Bits */ -#define FLCTL_A_SETIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_SETIFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_A_SETIFG[ERASE] Bits */ -#define FLCTL_A_SETIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_SETIFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_A_SETIFG[BMRK] Bits */ -#define FLCTL_A_SETIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_SETIFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_A_SETIFG[PRG_ERR] Bits */ -#define FLCTL_A_SETIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_SETIFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_A_READ_TIMCTL[SETUP] Bits */ -#define FLCTL_A_READ_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_READ_TIMCTL[IREF_BOOST1] Bits */ -#define FLCTL_A_READ_TIMCTL_IREF_BOOST1_OFS (12) /*!< IREF_BOOST1 Bit Offset */ -#define FLCTL_A_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /*!< IREF_BOOST1 Bit Mask */ -/* FLCTL_A_READ_TIMCTL[SETUP_LONG] Bits */ -#define FLCTL_A_READ_TIMCTL_SETUP_LONG_OFS (16) /*!< SETUP_LONG Bit Offset */ -#define FLCTL_A_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /*!< SETUP_LONG Bit Mask */ -/* FLCTL_A_READMARGIN_TIMCTL[SETUP] Bits */ -#define FLCTL_A_READMARGIN_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_PRGVER_TIMCTL[SETUP] Bits */ -#define FLCTL_A_PRGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_PRGVER_TIMCTL[ACTIVE] Bits */ -#define FLCTL_A_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /*!< ACTIVE Bit Mask */ -/* FLCTL_A_PRGVER_TIMCTL[HOLD] Bits */ -#define FLCTL_A_PRGVER_TIMCTL_HOLD_OFS (12) /*!< HOLD Bit Offset */ -#define FLCTL_A_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /*!< HOLD Bit Mask */ -/* FLCTL_A_ERSVER_TIMCTL[SETUP] Bits */ -#define FLCTL_A_ERSVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_LKGVER_TIMCTL[SETUP] Bits */ -#define FLCTL_A_LKGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_PROGRAM_TIMCTL[SETUP] Bits */ -#define FLCTL_A_PROGRAM_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_PROGRAM_TIMCTL[ACTIVE] Bits */ -#define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_A_PROGRAM_TIMCTL[HOLD] Bits */ -#define FLCTL_A_PROGRAM_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_A_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -/* FLCTL_A_ERASE_TIMCTL[SETUP] Bits */ -#define FLCTL_A_ERASE_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_ERASE_TIMCTL[ACTIVE] Bits */ -#define FLCTL_A_ERASE_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_A_ERASE_TIMCTL[HOLD] Bits */ -#define FLCTL_A_ERASE_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_A_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -/* FLCTL_A_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /*!< BOOST_ACTIVE Bit Offset */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /*!< BOOST_ACTIVE Bit Mask */ -/* FLCTL_A_MASSERASE_TIMCTL[BOOST_HOLD] Bits */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /*!< BOOST_HOLD Bit Offset */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /*!< BOOST_HOLD Bit Mask */ -/* FLCTL_A_BURSTPRG_TIMCTL[ACTIVE] Bits */ -#define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT0] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT1] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT2] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT3] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT4] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT5] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT6] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT7] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT8] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT9] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT10] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT11] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT12] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT13] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT14] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT15] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT16] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT17] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT18] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT19] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT20] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT21] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT22] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT23] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT24] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT25] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT26] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT27] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT28] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT29] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT30] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT31] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT32] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32_OFS ( 0) /*!< PROT32 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32 ((uint32_t)0x00000001) /*!< Protects Sector 32 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT33] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33_OFS ( 1) /*!< PROT33 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33 ((uint32_t)0x00000002) /*!< Protects Sector 33 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT34] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34_OFS ( 2) /*!< PROT34 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34 ((uint32_t)0x00000004) /*!< Protects Sector 34 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT35] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35_OFS ( 3) /*!< PROT35 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35 ((uint32_t)0x00000008) /*!< Protects Sector 35 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT36] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36_OFS ( 4) /*!< PROT36 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36 ((uint32_t)0x00000010) /*!< Protects Sector 36 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT37] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37_OFS ( 5) /*!< PROT37 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37 ((uint32_t)0x00000020) /*!< Protects Sector 37 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT38] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38_OFS ( 6) /*!< PROT38 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38 ((uint32_t)0x00000040) /*!< Protects Sector 38 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT39] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39_OFS ( 7) /*!< PROT39 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39 ((uint32_t)0x00000080) /*!< Protects Sector 39 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT40] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40_OFS ( 8) /*!< PROT40 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40 ((uint32_t)0x00000100) /*!< Protects Sector 40 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT41] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41_OFS ( 9) /*!< PROT41 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41 ((uint32_t)0x00000200) /*!< Protects Sector 41 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT42] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42_OFS (10) /*!< PROT42 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42 ((uint32_t)0x00000400) /*!< Protects Sector 42 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT43] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43_OFS (11) /*!< PROT43 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43 ((uint32_t)0x00000800) /*!< Protects Sector 43 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT44] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44_OFS (12) /*!< PROT44 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44 ((uint32_t)0x00001000) /*!< Protects Sector 44 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT45] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45_OFS (13) /*!< PROT45 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45 ((uint32_t)0x00002000) /*!< Protects Sector 45 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT46] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46_OFS (14) /*!< PROT46 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46 ((uint32_t)0x00004000) /*!< Protects Sector 46 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT47] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47_OFS (15) /*!< PROT47 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47 ((uint32_t)0x00008000) /*!< Protects Sector 47 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT48] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48_OFS (16) /*!< PROT48 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48 ((uint32_t)0x00010000) /*!< Protects Sector 48 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT49] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49_OFS (17) /*!< PROT49 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49 ((uint32_t)0x00020000) /*!< Protects Sector 49 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT50] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50_OFS (18) /*!< PROT50 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50 ((uint32_t)0x00040000) /*!< Protects Sector 50 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT51] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51_OFS (19) /*!< PROT51 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51 ((uint32_t)0x00080000) /*!< Protects Sector 51 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT52] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52_OFS (20) /*!< PROT52 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52 ((uint32_t)0x00100000) /*!< Protects Sector 52 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT53] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53_OFS (21) /*!< PROT53 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53 ((uint32_t)0x00200000) /*!< Protects Sector 53 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT54] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54_OFS (22) /*!< PROT54 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54 ((uint32_t)0x00400000) /*!< Protects Sector 54 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT55] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55_OFS (23) /*!< PROT55 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55 ((uint32_t)0x00800000) /*!< Protects Sector 55 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT56] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56_OFS (24) /*!< PROT56 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56 ((uint32_t)0x01000000) /*!< Protects Sector 56 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT57] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57_OFS (25) /*!< PROT57 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57 ((uint32_t)0x02000000) /*!< Protects Sector 57 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT58] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58_OFS (26) /*!< PROT58 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58 ((uint32_t)0x04000000) /*!< Protects Sector 58 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT59] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59_OFS (27) /*!< PROT59 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59 ((uint32_t)0x08000000) /*!< Protects Sector 59 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT60] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60_OFS (28) /*!< PROT60 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60 ((uint32_t)0x10000000) /*!< Protects Sector 60 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT61] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61_OFS (29) /*!< PROT61 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61 ((uint32_t)0x20000000) /*!< Protects Sector 61 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT62] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62_OFS (30) /*!< PROT62 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62 ((uint32_t)0x40000000) /*!< Protects Sector 62 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT63] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63_OFS (31) /*!< PROT63 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63 ((uint32_t)0x80000000) /*!< Protects Sector 63 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT64] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64_OFS ( 0) /*!< PROT64 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64 ((uint32_t)0x00000001) /*!< Protects Sector 64 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT65] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65_OFS ( 1) /*!< PROT65 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65 ((uint32_t)0x00000002) /*!< Protects Sector 65 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT66] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66_OFS ( 2) /*!< PROT66 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66 ((uint32_t)0x00000004) /*!< Protects Sector 66 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT67] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67_OFS ( 3) /*!< PROT67 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67 ((uint32_t)0x00000008) /*!< Protects Sector 67 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT68] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68_OFS ( 4) /*!< PROT68 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68 ((uint32_t)0x00000010) /*!< Protects Sector 68 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT69] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69_OFS ( 5) /*!< PROT69 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69 ((uint32_t)0x00000020) /*!< Protects Sector 69 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT70] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70_OFS ( 6) /*!< PROT70 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70 ((uint32_t)0x00000040) /*!< Protects Sector 70 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT71] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71_OFS ( 7) /*!< PROT71 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71 ((uint32_t)0x00000080) /*!< Protects Sector 71 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT72] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72_OFS ( 8) /*!< PROT72 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72 ((uint32_t)0x00000100) /*!< Protects Sector 72 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT73] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73_OFS ( 9) /*!< PROT73 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73 ((uint32_t)0x00000200) /*!< Protects Sector 73 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT74] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74_OFS (10) /*!< PROT74 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74 ((uint32_t)0x00000400) /*!< Protects Sector 74 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT75] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75_OFS (11) /*!< PROT75 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75 ((uint32_t)0x00000800) /*!< Protects Sector 75 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT76] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76_OFS (12) /*!< PROT76 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76 ((uint32_t)0x00001000) /*!< Protects Sector 76 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT77] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77_OFS (13) /*!< PROT77 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77 ((uint32_t)0x00002000) /*!< Protects Sector 77 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT78] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78_OFS (14) /*!< PROT78 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78 ((uint32_t)0x00004000) /*!< Protects Sector 78 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT79] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79_OFS (15) /*!< PROT79 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79 ((uint32_t)0x00008000) /*!< Protects Sector 79 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT80] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80_OFS (16) /*!< PROT80 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80 ((uint32_t)0x00010000) /*!< Protects Sector 80 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT81] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81_OFS (17) /*!< PROT81 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81 ((uint32_t)0x00020000) /*!< Protects Sector 81 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT82] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82_OFS (18) /*!< PROT82 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82 ((uint32_t)0x00040000) /*!< Protects Sector 82 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT83] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83_OFS (19) /*!< PROT83 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83 ((uint32_t)0x00080000) /*!< Protects Sector 83 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT84] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84_OFS (20) /*!< PROT84 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84 ((uint32_t)0x00100000) /*!< Protects Sector 84 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT85] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85_OFS (21) /*!< PROT85 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85 ((uint32_t)0x00200000) /*!< Protects Sector 85 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT86] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86_OFS (22) /*!< PROT86 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86 ((uint32_t)0x00400000) /*!< Protects Sector 86 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT87] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87_OFS (23) /*!< PROT87 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87 ((uint32_t)0x00800000) /*!< Protects Sector 87 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT88] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88_OFS (24) /*!< PROT88 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88 ((uint32_t)0x01000000) /*!< Protects Sector 88 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT89] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89_OFS (25) /*!< PROT89 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89 ((uint32_t)0x02000000) /*!< Protects Sector 89 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT90] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90_OFS (26) /*!< PROT90 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90 ((uint32_t)0x04000000) /*!< Protects Sector 90 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT91] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91_OFS (27) /*!< PROT91 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91 ((uint32_t)0x08000000) /*!< Protects Sector 91 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT92] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92_OFS (28) /*!< PROT92 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92 ((uint32_t)0x10000000) /*!< Protects Sector 92 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT93] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93_OFS (29) /*!< PROT93 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93 ((uint32_t)0x20000000) /*!< Protects Sector 93 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT94] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94_OFS (30) /*!< PROT94 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94 ((uint32_t)0x40000000) /*!< Protects Sector 94 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT95] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95_OFS (31) /*!< PROT95 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95 ((uint32_t)0x80000000) /*!< Protects Sector 95 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT96] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96_OFS ( 0) /*!< PROT96 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96 ((uint32_t)0x00000001) /*!< Protects Sector 96 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT97] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97_OFS ( 1) /*!< PROT97 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97 ((uint32_t)0x00000002) /*!< Protects Sector 97 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT98] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98_OFS ( 2) /*!< PROT98 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98 ((uint32_t)0x00000004) /*!< Protects Sector 98 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT99] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99_OFS ( 3) /*!< PROT99 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99 ((uint32_t)0x00000008) /*!< Protects Sector 99 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT100] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100_OFS ( 4) /*!< PROT100 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100 ((uint32_t)0x00000010) /*!< Protects Sector 100 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT101] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101_OFS ( 5) /*!< PROT101 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101 ((uint32_t)0x00000020) /*!< Protects Sector 101 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT102] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102_OFS ( 6) /*!< PROT102 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102 ((uint32_t)0x00000040) /*!< Protects Sector 102 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT103] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103_OFS ( 7) /*!< PROT103 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103 ((uint32_t)0x00000080) /*!< Protects Sector 103 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT104] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104_OFS ( 8) /*!< PROT104 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104 ((uint32_t)0x00000100) /*!< Protects Sector 104 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT105] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105_OFS ( 9) /*!< PROT105 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105 ((uint32_t)0x00000200) /*!< Protects Sector 105 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT106] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106_OFS (10) /*!< PROT106 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106 ((uint32_t)0x00000400) /*!< Protects Sector 106 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT107] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107_OFS (11) /*!< PROT107 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107 ((uint32_t)0x00000800) /*!< Protects Sector 107 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT108] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108_OFS (12) /*!< PROT108 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108 ((uint32_t)0x00001000) /*!< Protects Sector 108 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT109] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109_OFS (13) /*!< PROT109 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109 ((uint32_t)0x00002000) /*!< Protects Sector 109 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT110] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110_OFS (14) /*!< PROT110 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110 ((uint32_t)0x00004000) /*!< Protects Sector 110 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT111] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111_OFS (15) /*!< PROT111 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111 ((uint32_t)0x00008000) /*!< Protects Sector 111 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT112] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112_OFS (16) /*!< PROT112 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112 ((uint32_t)0x00010000) /*!< Protects Sector 112 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT113] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113_OFS (17) /*!< PROT113 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113 ((uint32_t)0x00020000) /*!< Protects Sector 113 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT114] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114_OFS (18) /*!< PROT114 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114 ((uint32_t)0x00040000) /*!< Protects Sector 114 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT115] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115_OFS (19) /*!< PROT115 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115 ((uint32_t)0x00080000) /*!< Protects Sector 115 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT116] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116_OFS (20) /*!< PROT116 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116 ((uint32_t)0x00100000) /*!< Protects Sector 116 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT117] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117_OFS (21) /*!< PROT117 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117 ((uint32_t)0x00200000) /*!< Protects Sector 117 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT118] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118_OFS (22) /*!< PROT118 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118 ((uint32_t)0x00400000) /*!< Protects Sector 118 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT119] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119_OFS (23) /*!< PROT119 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119 ((uint32_t)0x00800000) /*!< Protects Sector 119 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT120] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120_OFS (24) /*!< PROT120 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120 ((uint32_t)0x01000000) /*!< Protects Sector 120 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT121] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121_OFS (25) /*!< PROT121 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121 ((uint32_t)0x02000000) /*!< Protects Sector 121 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT122] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122_OFS (26) /*!< PROT122 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122 ((uint32_t)0x04000000) /*!< Protects Sector 122 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT123] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123_OFS (27) /*!< PROT123 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123 ((uint32_t)0x08000000) /*!< Protects Sector 123 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT124] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124_OFS (28) /*!< PROT124 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124 ((uint32_t)0x10000000) /*!< Protects Sector 124 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT125] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125_OFS (29) /*!< PROT125 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125 ((uint32_t)0x20000000) /*!< Protects Sector 125 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT126] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126_OFS (30) /*!< PROT126 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126 ((uint32_t)0x40000000) /*!< Protects Sector 126 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT127] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127_OFS (31) /*!< PROT127 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127 ((uint32_t)0x80000000) /*!< Protects Sector 127 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT128] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128_OFS ( 0) /*!< PROT128 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128 ((uint32_t)0x00000001) /*!< Protects Sector 128 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT129] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129_OFS ( 1) /*!< PROT129 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129 ((uint32_t)0x00000002) /*!< Protects Sector 129 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT130] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130_OFS ( 2) /*!< PROT130 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130 ((uint32_t)0x00000004) /*!< Protects Sector 130 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT131] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131_OFS ( 3) /*!< PROT131 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131 ((uint32_t)0x00000008) /*!< Protects Sector 131 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT132] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132_OFS ( 4) /*!< PROT132 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132 ((uint32_t)0x00000010) /*!< Protects Sector 132 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT133] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133_OFS ( 5) /*!< PROT133 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133 ((uint32_t)0x00000020) /*!< Protects Sector 133 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT134] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134_OFS ( 6) /*!< PROT134 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134 ((uint32_t)0x00000040) /*!< Protects Sector 134 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT135] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135_OFS ( 7) /*!< PROT135 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135 ((uint32_t)0x00000080) /*!< Protects Sector 135 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT136] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136_OFS ( 8) /*!< PROT136 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136 ((uint32_t)0x00000100) /*!< Protects Sector 136 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT137] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137_OFS ( 9) /*!< PROT137 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137 ((uint32_t)0x00000200) /*!< Protects Sector 137 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT138] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138_OFS (10) /*!< PROT138 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138 ((uint32_t)0x00000400) /*!< Protects Sector 138 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT139] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139_OFS (11) /*!< PROT139 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139 ((uint32_t)0x00000800) /*!< Protects Sector 139 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT140] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140_OFS (12) /*!< PROT140 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140 ((uint32_t)0x00001000) /*!< Protects Sector 140 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT141] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141_OFS (13) /*!< PROT141 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141 ((uint32_t)0x00002000) /*!< Protects Sector 141 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT142] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142_OFS (14) /*!< PROT142 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142 ((uint32_t)0x00004000) /*!< Protects Sector 142 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT143] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143_OFS (15) /*!< PROT143 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143 ((uint32_t)0x00008000) /*!< Protects Sector 143 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT144] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144_OFS (16) /*!< PROT144 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144 ((uint32_t)0x00010000) /*!< Protects Sector 144 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT145] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145_OFS (17) /*!< PROT145 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145 ((uint32_t)0x00020000) /*!< Protects Sector 145 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT146] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146_OFS (18) /*!< PROT146 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146 ((uint32_t)0x00040000) /*!< Protects Sector 146 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT147] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147_OFS (19) /*!< PROT147 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147 ((uint32_t)0x00080000) /*!< Protects Sector 147 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT148] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148_OFS (20) /*!< PROT148 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148 ((uint32_t)0x00100000) /*!< Protects Sector 148 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT149] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149_OFS (21) /*!< PROT149 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149 ((uint32_t)0x00200000) /*!< Protects Sector 149 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT150] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150_OFS (22) /*!< PROT150 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150 ((uint32_t)0x00400000) /*!< Protects Sector 150 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT151] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151_OFS (23) /*!< PROT151 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151 ((uint32_t)0x00800000) /*!< Protects Sector 151 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT152] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152_OFS (24) /*!< PROT152 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152 ((uint32_t)0x01000000) /*!< Protects Sector 152 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT153] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153_OFS (25) /*!< PROT153 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153 ((uint32_t)0x02000000) /*!< Protects Sector 153 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT154] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154_OFS (26) /*!< PROT154 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154 ((uint32_t)0x04000000) /*!< Protects Sector 154 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT155] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155_OFS (27) /*!< PROT155 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155 ((uint32_t)0x08000000) /*!< Protects Sector 155 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT156] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156_OFS (28) /*!< PROT156 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156 ((uint32_t)0x10000000) /*!< Protects Sector 156 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT157] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157_OFS (29) /*!< PROT157 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157 ((uint32_t)0x20000000) /*!< Protects Sector 157 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT158] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158_OFS (30) /*!< PROT158 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158 ((uint32_t)0x40000000) /*!< Protects Sector 158 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT159] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159_OFS (31) /*!< PROT159 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159 ((uint32_t)0x80000000) /*!< Protects Sector 159 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT160] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160_OFS ( 0) /*!< PROT160 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160 ((uint32_t)0x00000001) /*!< Protects Sector 160 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT161] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161_OFS ( 1) /*!< PROT161 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161 ((uint32_t)0x00000002) /*!< Protects Sector 161 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT162] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162_OFS ( 2) /*!< PROT162 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162 ((uint32_t)0x00000004) /*!< Protects Sector 162 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT163] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163_OFS ( 3) /*!< PROT163 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163 ((uint32_t)0x00000008) /*!< Protects Sector 163 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT164] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164_OFS ( 4) /*!< PROT164 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164 ((uint32_t)0x00000010) /*!< Protects Sector 164 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT165] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165_OFS ( 5) /*!< PROT165 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165 ((uint32_t)0x00000020) /*!< Protects Sector 165 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT166] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166_OFS ( 6) /*!< PROT166 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166 ((uint32_t)0x00000040) /*!< Protects Sector 166 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT167] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167_OFS ( 7) /*!< PROT167 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167 ((uint32_t)0x00000080) /*!< Protects Sector 167 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT168] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168_OFS ( 8) /*!< PROT168 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168 ((uint32_t)0x00000100) /*!< Protects Sector 168 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT169] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169_OFS ( 9) /*!< PROT169 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169 ((uint32_t)0x00000200) /*!< Protects Sector 169 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT170] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170_OFS (10) /*!< PROT170 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170 ((uint32_t)0x00000400) /*!< Protects Sector 170 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT171] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171_OFS (11) /*!< PROT171 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171 ((uint32_t)0x00000800) /*!< Protects Sector 171 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT172] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172_OFS (12) /*!< PROT172 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172 ((uint32_t)0x00001000) /*!< Protects Sector 172 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT173] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173_OFS (13) /*!< PROT173 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173 ((uint32_t)0x00002000) /*!< Protects Sector 173 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT174] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174_OFS (14) /*!< PROT174 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174 ((uint32_t)0x00004000) /*!< Protects Sector 174 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT175] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175_OFS (15) /*!< PROT175 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175 ((uint32_t)0x00008000) /*!< Protects Sector 175 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT176] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176_OFS (16) /*!< PROT176 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176 ((uint32_t)0x00010000) /*!< Protects Sector 176 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT177] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177_OFS (17) /*!< PROT177 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177 ((uint32_t)0x00020000) /*!< Protects Sector 177 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT178] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178_OFS (18) /*!< PROT178 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178 ((uint32_t)0x00040000) /*!< Protects Sector 178 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT179] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179_OFS (19) /*!< PROT179 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179 ((uint32_t)0x00080000) /*!< Protects Sector 179 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT180] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180_OFS (20) /*!< PROT180 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180 ((uint32_t)0x00100000) /*!< Protects Sector 180 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT181] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181_OFS (21) /*!< PROT181 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181 ((uint32_t)0x00200000) /*!< Protects Sector 181 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT182] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182_OFS (22) /*!< PROT182 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182 ((uint32_t)0x00400000) /*!< Protects Sector 182 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT183] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183_OFS (23) /*!< PROT183 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183 ((uint32_t)0x00800000) /*!< Protects Sector 183 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT184] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184_OFS (24) /*!< PROT184 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184 ((uint32_t)0x01000000) /*!< Protects Sector 184 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT185] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185_OFS (25) /*!< PROT185 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185 ((uint32_t)0x02000000) /*!< Protects Sector 185 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT186] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186_OFS (26) /*!< PROT186 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186 ((uint32_t)0x04000000) /*!< Protects Sector 186 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT187] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187_OFS (27) /*!< PROT187 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187 ((uint32_t)0x08000000) /*!< Protects Sector 187 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT188] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188_OFS (28) /*!< PROT188 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188 ((uint32_t)0x10000000) /*!< Protects Sector 188 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT189] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189_OFS (29) /*!< PROT189 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189 ((uint32_t)0x20000000) /*!< Protects Sector 189 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT190] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190_OFS (30) /*!< PROT190 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190 ((uint32_t)0x40000000) /*!< Protects Sector 190 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT191] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191_OFS (31) /*!< PROT191 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191 ((uint32_t)0x80000000) /*!< Protects Sector 191 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT192] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192_OFS ( 0) /*!< PROT192 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192 ((uint32_t)0x00000001) /*!< Protects Sector 192 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT193] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193_OFS ( 1) /*!< PROT193 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193 ((uint32_t)0x00000002) /*!< Protects Sector 193 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT194] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194_OFS ( 2) /*!< PROT194 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194 ((uint32_t)0x00000004) /*!< Protects Sector 194 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT195] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195_OFS ( 3) /*!< PROT195 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195 ((uint32_t)0x00000008) /*!< Protects Sector 195 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT196] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196_OFS ( 4) /*!< PROT196 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196 ((uint32_t)0x00000010) /*!< Protects Sector 196 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT197] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197_OFS ( 5) /*!< PROT197 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197 ((uint32_t)0x00000020) /*!< Protects Sector 197 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT198] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198_OFS ( 6) /*!< PROT198 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198 ((uint32_t)0x00000040) /*!< Protects Sector 198 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT199] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199_OFS ( 7) /*!< PROT199 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199 ((uint32_t)0x00000080) /*!< Protects Sector 199 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT200] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200_OFS ( 8) /*!< PROT200 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200 ((uint32_t)0x00000100) /*!< Protects Sector 200 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT201] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201_OFS ( 9) /*!< PROT201 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201 ((uint32_t)0x00000200) /*!< Protects Sector 201 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT202] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202_OFS (10) /*!< PROT202 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202 ((uint32_t)0x00000400) /*!< Protects Sector 202 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT203] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203_OFS (11) /*!< PROT203 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203 ((uint32_t)0x00000800) /*!< Protects Sector 203 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT204] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204_OFS (12) /*!< PROT204 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204 ((uint32_t)0x00001000) /*!< Protects Sector 204 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT205] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205_OFS (13) /*!< PROT205 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205 ((uint32_t)0x00002000) /*!< Protects Sector 205 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT206] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206_OFS (14) /*!< PROT206 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206 ((uint32_t)0x00004000) /*!< Protects Sector 206 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT207] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207_OFS (15) /*!< PROT207 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207 ((uint32_t)0x00008000) /*!< Protects Sector 207 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT208] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208_OFS (16) /*!< PROT208 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208 ((uint32_t)0x00010000) /*!< Protects Sector 208 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT209] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209_OFS (17) /*!< PROT209 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209 ((uint32_t)0x00020000) /*!< Protects Sector 209 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT210] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210_OFS (18) /*!< PROT210 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210 ((uint32_t)0x00040000) /*!< Protects Sector 210 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT211] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211_OFS (19) /*!< PROT211 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211 ((uint32_t)0x00080000) /*!< Protects Sector 211 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT212] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212_OFS (20) /*!< PROT212 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212 ((uint32_t)0x00100000) /*!< Protects Sector 212 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT213] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213_OFS (21) /*!< PROT213 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213 ((uint32_t)0x00200000) /*!< Protects Sector 213 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT214] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214_OFS (22) /*!< PROT214 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214 ((uint32_t)0x00400000) /*!< Protects Sector 214 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT215] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215_OFS (23) /*!< PROT215 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215 ((uint32_t)0x00800000) /*!< Protects Sector 215 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT216] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216_OFS (24) /*!< PROT216 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216 ((uint32_t)0x01000000) /*!< Protects Sector 216 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT217] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217_OFS (25) /*!< PROT217 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217 ((uint32_t)0x02000000) /*!< Protects Sector 217 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT218] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218_OFS (26) /*!< PROT218 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218 ((uint32_t)0x04000000) /*!< Protects Sector 218 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT219] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219_OFS (27) /*!< PROT219 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219 ((uint32_t)0x08000000) /*!< Protects Sector 219 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT220] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220_OFS (28) /*!< PROT220 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220 ((uint32_t)0x10000000) /*!< Protects Sector 220 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT221] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221_OFS (29) /*!< PROT221 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221 ((uint32_t)0x20000000) /*!< Protects Sector 221 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT222] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222_OFS (30) /*!< PROT222 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222 ((uint32_t)0x40000000) /*!< Protects Sector 222 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT223] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223_OFS (31) /*!< PROT223 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223 ((uint32_t)0x80000000) /*!< Protects Sector 223 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT224] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224_OFS ( 0) /*!< PROT224 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224 ((uint32_t)0x00000001) /*!< Protects Sector 224 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT225] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225_OFS ( 1) /*!< PROT225 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225 ((uint32_t)0x00000002) /*!< Protects Sector 225 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT226] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226_OFS ( 2) /*!< PROT226 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226 ((uint32_t)0x00000004) /*!< Protects Sector 226 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT227] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227_OFS ( 3) /*!< PROT227 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227 ((uint32_t)0x00000008) /*!< Protects Sector 227 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT228] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228_OFS ( 4) /*!< PROT228 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228 ((uint32_t)0x00000010) /*!< Protects Sector 228 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT229] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229_OFS ( 5) /*!< PROT229 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229 ((uint32_t)0x00000020) /*!< Protects Sector 229 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT230] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230_OFS ( 6) /*!< PROT230 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230 ((uint32_t)0x00000040) /*!< Protects Sector 230 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT231] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231_OFS ( 7) /*!< PROT231 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231 ((uint32_t)0x00000080) /*!< Protects Sector 231 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT232] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232_OFS ( 8) /*!< PROT232 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232 ((uint32_t)0x00000100) /*!< Protects Sector 232 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT233] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233_OFS ( 9) /*!< PROT233 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233 ((uint32_t)0x00000200) /*!< Protects Sector 233 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT234] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234_OFS (10) /*!< PROT234 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234 ((uint32_t)0x00000400) /*!< Protects Sector 234 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT235] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235_OFS (11) /*!< PROT235 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235 ((uint32_t)0x00000800) /*!< Protects Sector 235 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT236] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236_OFS (12) /*!< PROT236 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236 ((uint32_t)0x00001000) /*!< Protects Sector 236 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT237] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237_OFS (13) /*!< PROT237 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237 ((uint32_t)0x00002000) /*!< Protects Sector 237 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT238] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238_OFS (14) /*!< PROT238 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238 ((uint32_t)0x00004000) /*!< Protects Sector 238 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT239] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239_OFS (15) /*!< PROT239 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239 ((uint32_t)0x00008000) /*!< Protects Sector 239 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT240] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240_OFS (16) /*!< PROT240 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240 ((uint32_t)0x00010000) /*!< Protects Sector 240 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT241] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241_OFS (17) /*!< PROT241 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241 ((uint32_t)0x00020000) /*!< Protects Sector 241 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT242] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242_OFS (18) /*!< PROT242 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242 ((uint32_t)0x00040000) /*!< Protects Sector 242 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT243] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243_OFS (19) /*!< PROT243 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243 ((uint32_t)0x00080000) /*!< Protects Sector 243 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT244] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244_OFS (20) /*!< PROT244 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244 ((uint32_t)0x00100000) /*!< Protects Sector 244 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT245] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245_OFS (21) /*!< PROT245 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245 ((uint32_t)0x00200000) /*!< Protects Sector 245 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT246] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246_OFS (22) /*!< PROT246 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246 ((uint32_t)0x00400000) /*!< Protects Sector 246 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT247] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247_OFS (23) /*!< PROT247 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247 ((uint32_t)0x00800000) /*!< Protects Sector 247 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT248] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248_OFS (24) /*!< PROT248 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248 ((uint32_t)0x01000000) /*!< Protects Sector 248 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT249] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249_OFS (25) /*!< PROT249 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249 ((uint32_t)0x02000000) /*!< Protects Sector 249 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT250] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250_OFS (26) /*!< PROT250 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250 ((uint32_t)0x04000000) /*!< Protects Sector 250 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT251] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251_OFS (27) /*!< PROT251 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251 ((uint32_t)0x08000000) /*!< Protects Sector 251 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT252] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252_OFS (28) /*!< PROT252 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252 ((uint32_t)0x10000000) /*!< Protects Sector 252 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT253] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253_OFS (29) /*!< PROT253 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253 ((uint32_t)0x20000000) /*!< Protects Sector 253 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT254] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254_OFS (30) /*!< PROT254 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254 ((uint32_t)0x40000000) /*!< Protects Sector 254 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT255] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255_OFS (31) /*!< PROT255 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255 ((uint32_t)0x80000000) /*!< Protects Sector 255 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT0] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT1] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT2] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT3] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT4] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT5] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT6] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT7] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT8] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT9] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT10] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT11] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT12] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT13] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT14] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT15] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT16] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT17] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT18] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT19] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT20] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT21] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT22] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT23] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT24] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT25] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT26] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT27] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT28] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT29] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT30] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT31] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT32] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32_OFS ( 0) /*!< PROT32 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32 ((uint32_t)0x00000001) /*!< Protects Sector 32 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT33] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33_OFS ( 1) /*!< PROT33 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33 ((uint32_t)0x00000002) /*!< Protects Sector 33 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT34] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34_OFS ( 2) /*!< PROT34 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34 ((uint32_t)0x00000004) /*!< Protects Sector 34 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT35] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35_OFS ( 3) /*!< PROT35 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35 ((uint32_t)0x00000008) /*!< Protects Sector 35 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT36] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36_OFS ( 4) /*!< PROT36 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36 ((uint32_t)0x00000010) /*!< Protects Sector 36 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT37] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37_OFS ( 5) /*!< PROT37 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37 ((uint32_t)0x00000020) /*!< Protects Sector 37 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT38] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38_OFS ( 6) /*!< PROT38 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38 ((uint32_t)0x00000040) /*!< Protects Sector 38 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT39] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39_OFS ( 7) /*!< PROT39 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39 ((uint32_t)0x00000080) /*!< Protects Sector 39 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT40] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40_OFS ( 8) /*!< PROT40 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40 ((uint32_t)0x00000100) /*!< Protects Sector 40 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT41] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41_OFS ( 9) /*!< PROT41 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41 ((uint32_t)0x00000200) /*!< Protects Sector 41 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT42] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42_OFS (10) /*!< PROT42 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42 ((uint32_t)0x00000400) /*!< Protects Sector 42 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT43] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43_OFS (11) /*!< PROT43 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43 ((uint32_t)0x00000800) /*!< Protects Sector 43 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT44] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44_OFS (12) /*!< PROT44 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44 ((uint32_t)0x00001000) /*!< Protects Sector 44 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT45] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45_OFS (13) /*!< PROT45 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45 ((uint32_t)0x00002000) /*!< Protects Sector 45 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT46] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46_OFS (14) /*!< PROT46 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46 ((uint32_t)0x00004000) /*!< Protects Sector 46 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT47] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47_OFS (15) /*!< PROT47 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47 ((uint32_t)0x00008000) /*!< Protects Sector 47 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT48] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48_OFS (16) /*!< PROT48 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48 ((uint32_t)0x00010000) /*!< Protects Sector 48 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT49] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49_OFS (17) /*!< PROT49 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49 ((uint32_t)0x00020000) /*!< Protects Sector 49 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT50] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50_OFS (18) /*!< PROT50 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50 ((uint32_t)0x00040000) /*!< Protects Sector 50 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT51] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51_OFS (19) /*!< PROT51 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51 ((uint32_t)0x00080000) /*!< Protects Sector 51 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT52] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52_OFS (20) /*!< PROT52 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52 ((uint32_t)0x00100000) /*!< Protects Sector 52 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT53] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53_OFS (21) /*!< PROT53 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53 ((uint32_t)0x00200000) /*!< Protects Sector 53 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT54] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54_OFS (22) /*!< PROT54 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54 ((uint32_t)0x00400000) /*!< Protects Sector 54 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT55] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55_OFS (23) /*!< PROT55 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55 ((uint32_t)0x00800000) /*!< Protects Sector 55 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT56] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56_OFS (24) /*!< PROT56 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56 ((uint32_t)0x01000000) /*!< Protects Sector 56 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT57] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57_OFS (25) /*!< PROT57 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57 ((uint32_t)0x02000000) /*!< Protects Sector 57 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT58] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58_OFS (26) /*!< PROT58 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58 ((uint32_t)0x04000000) /*!< Protects Sector 58 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT59] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59_OFS (27) /*!< PROT59 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59 ((uint32_t)0x08000000) /*!< Protects Sector 59 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT60] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60_OFS (28) /*!< PROT60 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60 ((uint32_t)0x10000000) /*!< Protects Sector 60 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT61] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61_OFS (29) /*!< PROT61 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61 ((uint32_t)0x20000000) /*!< Protects Sector 61 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT62] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62_OFS (30) /*!< PROT62 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62 ((uint32_t)0x40000000) /*!< Protects Sector 62 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT63] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63_OFS (31) /*!< PROT63 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63 ((uint32_t)0x80000000) /*!< Protects Sector 63 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT64] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64_OFS ( 0) /*!< PROT64 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64 ((uint32_t)0x00000001) /*!< Protects Sector 64 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT65] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65_OFS ( 1) /*!< PROT65 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65 ((uint32_t)0x00000002) /*!< Protects Sector 65 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT66] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66_OFS ( 2) /*!< PROT66 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66 ((uint32_t)0x00000004) /*!< Protects Sector 66 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT67] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67_OFS ( 3) /*!< PROT67 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67 ((uint32_t)0x00000008) /*!< Protects Sector 67 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT68] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68_OFS ( 4) /*!< PROT68 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68 ((uint32_t)0x00000010) /*!< Protects Sector 68 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT69] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69_OFS ( 5) /*!< PROT69 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69 ((uint32_t)0x00000020) /*!< Protects Sector 69 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT70] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70_OFS ( 6) /*!< PROT70 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70 ((uint32_t)0x00000040) /*!< Protects Sector 70 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT71] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71_OFS ( 7) /*!< PROT71 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71 ((uint32_t)0x00000080) /*!< Protects Sector 71 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT72] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72_OFS ( 8) /*!< PROT72 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72 ((uint32_t)0x00000100) /*!< Protects Sector 72 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT73] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73_OFS ( 9) /*!< PROT73 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73 ((uint32_t)0x00000200) /*!< Protects Sector 73 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT74] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74_OFS (10) /*!< PROT74 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74 ((uint32_t)0x00000400) /*!< Protects Sector 74 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT75] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75_OFS (11) /*!< PROT75 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75 ((uint32_t)0x00000800) /*!< Protects Sector 75 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT76] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76_OFS (12) /*!< PROT76 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76 ((uint32_t)0x00001000) /*!< Protects Sector 76 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT77] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77_OFS (13) /*!< PROT77 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77 ((uint32_t)0x00002000) /*!< Protects Sector 77 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT78] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78_OFS (14) /*!< PROT78 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78 ((uint32_t)0x00004000) /*!< Protects Sector 78 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT79] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79_OFS (15) /*!< PROT79 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79 ((uint32_t)0x00008000) /*!< Protects Sector 79 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT80] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80_OFS (16) /*!< PROT80 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80 ((uint32_t)0x00010000) /*!< Protects Sector 80 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT81] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81_OFS (17) /*!< PROT81 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81 ((uint32_t)0x00020000) /*!< Protects Sector 81 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT82] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82_OFS (18) /*!< PROT82 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82 ((uint32_t)0x00040000) /*!< Protects Sector 82 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT83] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83_OFS (19) /*!< PROT83 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83 ((uint32_t)0x00080000) /*!< Protects Sector 83 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT84] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84_OFS (20) /*!< PROT84 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84 ((uint32_t)0x00100000) /*!< Protects Sector 84 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT85] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85_OFS (21) /*!< PROT85 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85 ((uint32_t)0x00200000) /*!< Protects Sector 85 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT86] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86_OFS (22) /*!< PROT86 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86 ((uint32_t)0x00400000) /*!< Protects Sector 86 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT87] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87_OFS (23) /*!< PROT87 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87 ((uint32_t)0x00800000) /*!< Protects Sector 87 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT88] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88_OFS (24) /*!< PROT88 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88 ((uint32_t)0x01000000) /*!< Protects Sector 88 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT89] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89_OFS (25) /*!< PROT89 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89 ((uint32_t)0x02000000) /*!< Protects Sector 89 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT90] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90_OFS (26) /*!< PROT90 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90 ((uint32_t)0x04000000) /*!< Protects Sector 90 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT91] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91_OFS (27) /*!< PROT91 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91 ((uint32_t)0x08000000) /*!< Protects Sector 91 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT92] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92_OFS (28) /*!< PROT92 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92 ((uint32_t)0x10000000) /*!< Protects Sector 92 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT93] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93_OFS (29) /*!< PROT93 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93 ((uint32_t)0x20000000) /*!< Protects Sector 93 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT94] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94_OFS (30) /*!< PROT94 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94 ((uint32_t)0x40000000) /*!< Protects Sector 94 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT95] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95_OFS (31) /*!< PROT95 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95 ((uint32_t)0x80000000) /*!< Protects Sector 95 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT96] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96_OFS ( 0) /*!< PROT96 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96 ((uint32_t)0x00000001) /*!< Protects Sector 96 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT97] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97_OFS ( 1) /*!< PROT97 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97 ((uint32_t)0x00000002) /*!< Protects Sector 97 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT98] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98_OFS ( 2) /*!< PROT98 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98 ((uint32_t)0x00000004) /*!< Protects Sector 98 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT99] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99_OFS ( 3) /*!< PROT99 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99 ((uint32_t)0x00000008) /*!< Protects Sector 99 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT100] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100_OFS ( 4) /*!< PROT100 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100 ((uint32_t)0x00000010) /*!< Protects Sector 100 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT101] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101_OFS ( 5) /*!< PROT101 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101 ((uint32_t)0x00000020) /*!< Protects Sector 101 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT102] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102_OFS ( 6) /*!< PROT102 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102 ((uint32_t)0x00000040) /*!< Protects Sector 102 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT103] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103_OFS ( 7) /*!< PROT103 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103 ((uint32_t)0x00000080) /*!< Protects Sector 103 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT104] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104_OFS ( 8) /*!< PROT104 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104 ((uint32_t)0x00000100) /*!< Protects Sector 104 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT105] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105_OFS ( 9) /*!< PROT105 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105 ((uint32_t)0x00000200) /*!< Protects Sector 105 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT106] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106_OFS (10) /*!< PROT106 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106 ((uint32_t)0x00000400) /*!< Protects Sector 106 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT107] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107_OFS (11) /*!< PROT107 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107 ((uint32_t)0x00000800) /*!< Protects Sector 107 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT108] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108_OFS (12) /*!< PROT108 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108 ((uint32_t)0x00001000) /*!< Protects Sector 108 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT109] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109_OFS (13) /*!< PROT109 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109 ((uint32_t)0x00002000) /*!< Protects Sector 109 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT110] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110_OFS (14) /*!< PROT110 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110 ((uint32_t)0x00004000) /*!< Protects Sector 110 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT111] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111_OFS (15) /*!< PROT111 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111 ((uint32_t)0x00008000) /*!< Protects Sector 111 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT112] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112_OFS (16) /*!< PROT112 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112 ((uint32_t)0x00010000) /*!< Protects Sector 112 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT113] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113_OFS (17) /*!< PROT113 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113 ((uint32_t)0x00020000) /*!< Protects Sector 113 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT114] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114_OFS (18) /*!< PROT114 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114 ((uint32_t)0x00040000) /*!< Protects Sector 114 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT115] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115_OFS (19) /*!< PROT115 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115 ((uint32_t)0x00080000) /*!< Protects Sector 115 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT116] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116_OFS (20) /*!< PROT116 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116 ((uint32_t)0x00100000) /*!< Protects Sector 116 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT117] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117_OFS (21) /*!< PROT117 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117 ((uint32_t)0x00200000) /*!< Protects Sector 117 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT118] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118_OFS (22) /*!< PROT118 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118 ((uint32_t)0x00400000) /*!< Protects Sector 118 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT119] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119_OFS (23) /*!< PROT119 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119 ((uint32_t)0x00800000) /*!< Protects Sector 119 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT120] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120_OFS (24) /*!< PROT120 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120 ((uint32_t)0x01000000) /*!< Protects Sector 120 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT121] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121_OFS (25) /*!< PROT121 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121 ((uint32_t)0x02000000) /*!< Protects Sector 121 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT122] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122_OFS (26) /*!< PROT122 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122 ((uint32_t)0x04000000) /*!< Protects Sector 122 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT123] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123_OFS (27) /*!< PROT123 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123 ((uint32_t)0x08000000) /*!< Protects Sector 123 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT124] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124_OFS (28) /*!< PROT124 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124 ((uint32_t)0x10000000) /*!< Protects Sector 124 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT125] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125_OFS (29) /*!< PROT125 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125 ((uint32_t)0x20000000) /*!< Protects Sector 125 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT126] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126_OFS (30) /*!< PROT126 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126 ((uint32_t)0x40000000) /*!< Protects Sector 126 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT127] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127_OFS (31) /*!< PROT127 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127 ((uint32_t)0x80000000) /*!< Protects Sector 127 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT128] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128_OFS ( 0) /*!< PROT128 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128 ((uint32_t)0x00000001) /*!< Protects Sector 128 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT129] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129_OFS ( 1) /*!< PROT129 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129 ((uint32_t)0x00000002) /*!< Protects Sector 129 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT130] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130_OFS ( 2) /*!< PROT130 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130 ((uint32_t)0x00000004) /*!< Protects Sector 130 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT131] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131_OFS ( 3) /*!< PROT131 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131 ((uint32_t)0x00000008) /*!< Protects Sector 131 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT132] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132_OFS ( 4) /*!< PROT132 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132 ((uint32_t)0x00000010) /*!< Protects Sector 132 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT133] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133_OFS ( 5) /*!< PROT133 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133 ((uint32_t)0x00000020) /*!< Protects Sector 133 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT134] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134_OFS ( 6) /*!< PROT134 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134 ((uint32_t)0x00000040) /*!< Protects Sector 134 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT135] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135_OFS ( 7) /*!< PROT135 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135 ((uint32_t)0x00000080) /*!< Protects Sector 135 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT136] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136_OFS ( 8) /*!< PROT136 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136 ((uint32_t)0x00000100) /*!< Protects Sector 136 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT137] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137_OFS ( 9) /*!< PROT137 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137 ((uint32_t)0x00000200) /*!< Protects Sector 137 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT138] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138_OFS (10) /*!< PROT138 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138 ((uint32_t)0x00000400) /*!< Protects Sector 138 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT139] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139_OFS (11) /*!< PROT139 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139 ((uint32_t)0x00000800) /*!< Protects Sector 139 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT140] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140_OFS (12) /*!< PROT140 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140 ((uint32_t)0x00001000) /*!< Protects Sector 140 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT141] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141_OFS (13) /*!< PROT141 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141 ((uint32_t)0x00002000) /*!< Protects Sector 141 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT142] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142_OFS (14) /*!< PROT142 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142 ((uint32_t)0x00004000) /*!< Protects Sector 142 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT143] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143_OFS (15) /*!< PROT143 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143 ((uint32_t)0x00008000) /*!< Protects Sector 143 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT144] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144_OFS (16) /*!< PROT144 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144 ((uint32_t)0x00010000) /*!< Protects Sector 144 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT145] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145_OFS (17) /*!< PROT145 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145 ((uint32_t)0x00020000) /*!< Protects Sector 145 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT146] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146_OFS (18) /*!< PROT146 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146 ((uint32_t)0x00040000) /*!< Protects Sector 146 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT147] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147_OFS (19) /*!< PROT147 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147 ((uint32_t)0x00080000) /*!< Protects Sector 147 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT148] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148_OFS (20) /*!< PROT148 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148 ((uint32_t)0x00100000) /*!< Protects Sector 148 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT149] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149_OFS (21) /*!< PROT149 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149 ((uint32_t)0x00200000) /*!< Protects Sector 149 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT150] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150_OFS (22) /*!< PROT150 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150 ((uint32_t)0x00400000) /*!< Protects Sector 150 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT151] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151_OFS (23) /*!< PROT151 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151 ((uint32_t)0x00800000) /*!< Protects Sector 151 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT152] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152_OFS (24) /*!< PROT152 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152 ((uint32_t)0x01000000) /*!< Protects Sector 152 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT153] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153_OFS (25) /*!< PROT153 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153 ((uint32_t)0x02000000) /*!< Protects Sector 153 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT154] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154_OFS (26) /*!< PROT154 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154 ((uint32_t)0x04000000) /*!< Protects Sector 154 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT155] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155_OFS (27) /*!< PROT155 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155 ((uint32_t)0x08000000) /*!< Protects Sector 155 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT156] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156_OFS (28) /*!< PROT156 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156 ((uint32_t)0x10000000) /*!< Protects Sector 156 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT157] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157_OFS (29) /*!< PROT157 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157 ((uint32_t)0x20000000) /*!< Protects Sector 157 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT158] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158_OFS (30) /*!< PROT158 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158 ((uint32_t)0x40000000) /*!< Protects Sector 158 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT159] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159_OFS (31) /*!< PROT159 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159 ((uint32_t)0x80000000) /*!< Protects Sector 159 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT160] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160_OFS ( 0) /*!< PROT160 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160 ((uint32_t)0x00000001) /*!< Protects Sector 160 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT161] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161_OFS ( 1) /*!< PROT161 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161 ((uint32_t)0x00000002) /*!< Protects Sector 161 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT162] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162_OFS ( 2) /*!< PROT162 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162 ((uint32_t)0x00000004) /*!< Protects Sector 162 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT163] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163_OFS ( 3) /*!< PROT163 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163 ((uint32_t)0x00000008) /*!< Protects Sector 163 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT164] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164_OFS ( 4) /*!< PROT164 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164 ((uint32_t)0x00000010) /*!< Protects Sector 164 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT165] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165_OFS ( 5) /*!< PROT165 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165 ((uint32_t)0x00000020) /*!< Protects Sector 165 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT166] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166_OFS ( 6) /*!< PROT166 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166 ((uint32_t)0x00000040) /*!< Protects Sector 166 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT167] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167_OFS ( 7) /*!< PROT167 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167 ((uint32_t)0x00000080) /*!< Protects Sector 167 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT168] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168_OFS ( 8) /*!< PROT168 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168 ((uint32_t)0x00000100) /*!< Protects Sector 168 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT169] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169_OFS ( 9) /*!< PROT169 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169 ((uint32_t)0x00000200) /*!< Protects Sector 169 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT170] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170_OFS (10) /*!< PROT170 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170 ((uint32_t)0x00000400) /*!< Protects Sector 170 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT171] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171_OFS (11) /*!< PROT171 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171 ((uint32_t)0x00000800) /*!< Protects Sector 171 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT172] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172_OFS (12) /*!< PROT172 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172 ((uint32_t)0x00001000) /*!< Protects Sector 172 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT173] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173_OFS (13) /*!< PROT173 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173 ((uint32_t)0x00002000) /*!< Protects Sector 173 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT174] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174_OFS (14) /*!< PROT174 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174 ((uint32_t)0x00004000) /*!< Protects Sector 174 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT175] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175_OFS (15) /*!< PROT175 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175 ((uint32_t)0x00008000) /*!< Protects Sector 175 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT176] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176_OFS (16) /*!< PROT176 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176 ((uint32_t)0x00010000) /*!< Protects Sector 176 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT177] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177_OFS (17) /*!< PROT177 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177 ((uint32_t)0x00020000) /*!< Protects Sector 177 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT178] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178_OFS (18) /*!< PROT178 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178 ((uint32_t)0x00040000) /*!< Protects Sector 178 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT179] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179_OFS (19) /*!< PROT179 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179 ((uint32_t)0x00080000) /*!< Protects Sector 179 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT180] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180_OFS (20) /*!< PROT180 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180 ((uint32_t)0x00100000) /*!< Protects Sector 180 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT181] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181_OFS (21) /*!< PROT181 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181 ((uint32_t)0x00200000) /*!< Protects Sector 181 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT182] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182_OFS (22) /*!< PROT182 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182 ((uint32_t)0x00400000) /*!< Protects Sector 182 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT183] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183_OFS (23) /*!< PROT183 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183 ((uint32_t)0x00800000) /*!< Protects Sector 183 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT184] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184_OFS (24) /*!< PROT184 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184 ((uint32_t)0x01000000) /*!< Protects Sector 184 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT185] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185_OFS (25) /*!< PROT185 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185 ((uint32_t)0x02000000) /*!< Protects Sector 185 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT186] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186_OFS (26) /*!< PROT186 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186 ((uint32_t)0x04000000) /*!< Protects Sector 186 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT187] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187_OFS (27) /*!< PROT187 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187 ((uint32_t)0x08000000) /*!< Protects Sector 187 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT188] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188_OFS (28) /*!< PROT188 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188 ((uint32_t)0x10000000) /*!< Protects Sector 188 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT189] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189_OFS (29) /*!< PROT189 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189 ((uint32_t)0x20000000) /*!< Protects Sector 189 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT190] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190_OFS (30) /*!< PROT190 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190 ((uint32_t)0x40000000) /*!< Protects Sector 190 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT191] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191_OFS (31) /*!< PROT191 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191 ((uint32_t)0x80000000) /*!< Protects Sector 191 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT192] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192_OFS ( 0) /*!< PROT192 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192 ((uint32_t)0x00000001) /*!< Protects Sector 192 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT193] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193_OFS ( 1) /*!< PROT193 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193 ((uint32_t)0x00000002) /*!< Protects Sector 193 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT194] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194_OFS ( 2) /*!< PROT194 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194 ((uint32_t)0x00000004) /*!< Protects Sector 194 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT195] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195_OFS ( 3) /*!< PROT195 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195 ((uint32_t)0x00000008) /*!< Protects Sector 195 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT196] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196_OFS ( 4) /*!< PROT196 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196 ((uint32_t)0x00000010) /*!< Protects Sector 196 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT197] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197_OFS ( 5) /*!< PROT197 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197 ((uint32_t)0x00000020) /*!< Protects Sector 197 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT198] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198_OFS ( 6) /*!< PROT198 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198 ((uint32_t)0x00000040) /*!< Protects Sector 198 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT199] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199_OFS ( 7) /*!< PROT199 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199 ((uint32_t)0x00000080) /*!< Protects Sector 199 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT200] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200_OFS ( 8) /*!< PROT200 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200 ((uint32_t)0x00000100) /*!< Protects Sector 200 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT201] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201_OFS ( 9) /*!< PROT201 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201 ((uint32_t)0x00000200) /*!< Protects Sector 201 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT202] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202_OFS (10) /*!< PROT202 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202 ((uint32_t)0x00000400) /*!< Protects Sector 202 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT203] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203_OFS (11) /*!< PROT203 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203 ((uint32_t)0x00000800) /*!< Protects Sector 203 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT204] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204_OFS (12) /*!< PROT204 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204 ((uint32_t)0x00001000) /*!< Protects Sector 204 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT205] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205_OFS (13) /*!< PROT205 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205 ((uint32_t)0x00002000) /*!< Protects Sector 205 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT206] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206_OFS (14) /*!< PROT206 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206 ((uint32_t)0x00004000) /*!< Protects Sector 206 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT207] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207_OFS (15) /*!< PROT207 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207 ((uint32_t)0x00008000) /*!< Protects Sector 207 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT208] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208_OFS (16) /*!< PROT208 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208 ((uint32_t)0x00010000) /*!< Protects Sector 208 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT209] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209_OFS (17) /*!< PROT209 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209 ((uint32_t)0x00020000) /*!< Protects Sector 209 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT210] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210_OFS (18) /*!< PROT210 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210 ((uint32_t)0x00040000) /*!< Protects Sector 210 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT211] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211_OFS (19) /*!< PROT211 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211 ((uint32_t)0x00080000) /*!< Protects Sector 211 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT212] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212_OFS (20) /*!< PROT212 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212 ((uint32_t)0x00100000) /*!< Protects Sector 212 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT213] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213_OFS (21) /*!< PROT213 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213 ((uint32_t)0x00200000) /*!< Protects Sector 213 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT214] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214_OFS (22) /*!< PROT214 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214 ((uint32_t)0x00400000) /*!< Protects Sector 214 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT215] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215_OFS (23) /*!< PROT215 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215 ((uint32_t)0x00800000) /*!< Protects Sector 215 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT216] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216_OFS (24) /*!< PROT216 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216 ((uint32_t)0x01000000) /*!< Protects Sector 216 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT217] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217_OFS (25) /*!< PROT217 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217 ((uint32_t)0x02000000) /*!< Protects Sector 217 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT218] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218_OFS (26) /*!< PROT218 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218 ((uint32_t)0x04000000) /*!< Protects Sector 218 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT219] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219_OFS (27) /*!< PROT219 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219 ((uint32_t)0x08000000) /*!< Protects Sector 219 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT220] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220_OFS (28) /*!< PROT220 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220 ((uint32_t)0x10000000) /*!< Protects Sector 220 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT221] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221_OFS (29) /*!< PROT221 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221 ((uint32_t)0x20000000) /*!< Protects Sector 221 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT222] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222_OFS (30) /*!< PROT222 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222 ((uint32_t)0x40000000) /*!< Protects Sector 222 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT223] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223_OFS (31) /*!< PROT223 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223 ((uint32_t)0x80000000) /*!< Protects Sector 223 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT224] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224_OFS ( 0) /*!< PROT224 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224 ((uint32_t)0x00000001) /*!< Protects Sector 224 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT225] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225_OFS ( 1) /*!< PROT225 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225 ((uint32_t)0x00000002) /*!< Protects Sector 225 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT226] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226_OFS ( 2) /*!< PROT226 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226 ((uint32_t)0x00000004) /*!< Protects Sector 226 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT227] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227_OFS ( 3) /*!< PROT227 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227 ((uint32_t)0x00000008) /*!< Protects Sector 227 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT228] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228_OFS ( 4) /*!< PROT228 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228 ((uint32_t)0x00000010) /*!< Protects Sector 228 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT229] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229_OFS ( 5) /*!< PROT229 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229 ((uint32_t)0x00000020) /*!< Protects Sector 229 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT230] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230_OFS ( 6) /*!< PROT230 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230 ((uint32_t)0x00000040) /*!< Protects Sector 230 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT231] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231_OFS ( 7) /*!< PROT231 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231 ((uint32_t)0x00000080) /*!< Protects Sector 231 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT232] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232_OFS ( 8) /*!< PROT232 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232 ((uint32_t)0x00000100) /*!< Protects Sector 232 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT233] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233_OFS ( 9) /*!< PROT233 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233 ((uint32_t)0x00000200) /*!< Protects Sector 233 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT234] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234_OFS (10) /*!< PROT234 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234 ((uint32_t)0x00000400) /*!< Protects Sector 234 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT235] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235_OFS (11) /*!< PROT235 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235 ((uint32_t)0x00000800) /*!< Protects Sector 235 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT236] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236_OFS (12) /*!< PROT236 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236 ((uint32_t)0x00001000) /*!< Protects Sector 236 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT237] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237_OFS (13) /*!< PROT237 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237 ((uint32_t)0x00002000) /*!< Protects Sector 237 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT238] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238_OFS (14) /*!< PROT238 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238 ((uint32_t)0x00004000) /*!< Protects Sector 238 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT239] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239_OFS (15) /*!< PROT239 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239 ((uint32_t)0x00008000) /*!< Protects Sector 239 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT240] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240_OFS (16) /*!< PROT240 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240 ((uint32_t)0x00010000) /*!< Protects Sector 240 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT241] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241_OFS (17) /*!< PROT241 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241 ((uint32_t)0x00020000) /*!< Protects Sector 241 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT242] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242_OFS (18) /*!< PROT242 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242 ((uint32_t)0x00040000) /*!< Protects Sector 242 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT243] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243_OFS (19) /*!< PROT243 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243 ((uint32_t)0x00080000) /*!< Protects Sector 243 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT244] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244_OFS (20) /*!< PROT244 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244 ((uint32_t)0x00100000) /*!< Protects Sector 244 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT245] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245_OFS (21) /*!< PROT245 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245 ((uint32_t)0x00200000) /*!< Protects Sector 245 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT246] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246_OFS (22) /*!< PROT246 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246 ((uint32_t)0x00400000) /*!< Protects Sector 246 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT247] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247_OFS (23) /*!< PROT247 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247 ((uint32_t)0x00800000) /*!< Protects Sector 247 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT248] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248_OFS (24) /*!< PROT248 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248 ((uint32_t)0x01000000) /*!< Protects Sector 248 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT249] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249_OFS (25) /*!< PROT249 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249 ((uint32_t)0x02000000) /*!< Protects Sector 249 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT250] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250_OFS (26) /*!< PROT250 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250 ((uint32_t)0x04000000) /*!< Protects Sector 250 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT251] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251_OFS (27) /*!< PROT251 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251 ((uint32_t)0x08000000) /*!< Protects Sector 251 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT252] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252_OFS (28) /*!< PROT252 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252 ((uint32_t)0x10000000) /*!< Protects Sector 252 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT253] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253_OFS (29) /*!< PROT253 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253 ((uint32_t)0x20000000) /*!< Protects Sector 253 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT254] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254_OFS (30) /*!< PROT254 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254 ((uint32_t)0x40000000) /*!< Protects Sector 254 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT255] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255_OFS (31) /*!< PROT255 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255 ((uint32_t)0x80000000) /*!< Protects Sector 255 from program or erase */ - -/****************************************************************************** -* FL_BOOTOVER_MAILBOX Bits -******************************************************************************/ - -/****************************************************************************** -* FPB Bits -******************************************************************************/ - - -/****************************************************************************** -* FPU Bits -******************************************************************************/ - - -/****************************************************************************** -* ITM Bits -******************************************************************************/ - - -/****************************************************************************** -* LCD_F Bits -******************************************************************************/ -/* LCD_F_CTL[ON] Bits */ -#define LCD_F_CTL_ON_OFS ( 0) /*!< LCDON Bit Offset */ -#define LCD_F_CTL_ON ((uint32_t)0x00000001) /*!< LCD on */ -/* LCD_F_CTL[LP] Bits */ -#define LCD_F_CTL_LP_OFS ( 1) /*!< LCDLP Bit Offset */ -#define LCD_F_CTL_LP ((uint32_t)0x00000002) /*!< LCD Low-power Waveform */ -/* LCD_F_CTL[SON] Bits */ -#define LCD_F_CTL_SON_OFS ( 2) /*!< LCDSON Bit Offset */ -#define LCD_F_CTL_SON ((uint32_t)0x00000004) /*!< LCD segments on */ -/* LCD_F_CTL[MX] Bits */ -#define LCD_F_CTL_MX_OFS ( 3) /*!< LCDMXx Bit Offset */ -#define LCD_F_CTL_MX_MASK ((uint32_t)0x00000038) /*!< LCDMXx Bit Mask */ -#define LCD_F_CTL_MX0 ((uint32_t)0x00000008) /*!< MX Bit 0 */ -#define LCD_F_CTL_MX1 ((uint32_t)0x00000010) /*!< MX Bit 1 */ -#define LCD_F_CTL_MX2 ((uint32_t)0x00000020) /*!< MX Bit 2 */ -#define LCD_F_CTL_MX_0 ((uint32_t)0x00000000) /*!< Static */ -#define LCD_F_CTL_MX_1 ((uint32_t)0x00000008) /*!< 2-mux */ -#define LCD_F_CTL_MX_2 ((uint32_t)0x00000010) /*!< 3-mux */ -#define LCD_F_CTL_MX_3 ((uint32_t)0x00000018) /*!< 4-mux */ -#define LCD_F_CTL_MX_4 ((uint32_t)0x00000020) /*!< 5-mux */ -#define LCD_F_CTL_MX_5 ((uint32_t)0x00000028) /*!< 6-mux */ -#define LCD_F_CTL_MX_6 ((uint32_t)0x00000030) /*!< 7-mux */ -#define LCD_F_CTL_MX_7 ((uint32_t)0x00000038) /*!< 8-mux */ -/* LCD_F_CTL[PRE] Bits */ -#define LCD_F_CTL_PRE_OFS ( 8) /*!< LCDPREx Bit Offset */ -#define LCD_F_CTL_PRE_MASK ((uint32_t)0x00000700) /*!< LCDPREx Bit Mask */ -#define LCD_F_CTL_PRE0 ((uint32_t)0x00000100) /*!< PRE Bit 0 */ -#define LCD_F_CTL_PRE1 ((uint32_t)0x00000200) /*!< PRE Bit 1 */ -#define LCD_F_CTL_PRE2 ((uint32_t)0x00000400) /*!< PRE Bit 2 */ -#define LCD_F_CTL_PRE_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_CTL_PRE_1 ((uint32_t)0x00000100) /*!< Divide by 2 */ -#define LCD_F_CTL_PRE_2 ((uint32_t)0x00000200) /*!< Divide by 4 */ -#define LCD_F_CTL_PRE_3 ((uint32_t)0x00000300) /*!< Divide by 8 */ -#define LCD_F_CTL_PRE_4 ((uint32_t)0x00000400) /*!< Divide by 16 */ -#define LCD_F_CTL_PRE_5 ((uint32_t)0x00000500) /*!< Divide by 32 */ -#define LCD_F_CTL_PRE_6 ((uint32_t)0x00000600) /*!< Reserved (defaults to divide by 32) */ -#define LCD_F_CTL_PRE_7 ((uint32_t)0x00000700) /*!< Reserved (defaults to divide by 32) */ -/* LCD_F_CTL[DIV] Bits */ -#define LCD_F_CTL_DIV_OFS (11) /*!< LCDDIVx Bit Offset */ -#define LCD_F_CTL_DIV_MASK ((uint32_t)0x0000F800) /*!< LCDDIVx Bit Mask */ -#define LCD_F_CTL_DIV0 ((uint32_t)0x00000800) /*!< DIV Bit 0 */ -#define LCD_F_CTL_DIV1 ((uint32_t)0x00001000) /*!< DIV Bit 1 */ -#define LCD_F_CTL_DIV2 ((uint32_t)0x00002000) /*!< DIV Bit 2 */ -#define LCD_F_CTL_DIV3 ((uint32_t)0x00004000) /*!< DIV Bit 3 */ -#define LCD_F_CTL_DIV4 ((uint32_t)0x00008000) /*!< DIV Bit 4 */ -#define LCD_F_CTL_DIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_CTL_DIV_1 ((uint32_t)0x00000800) /*!< Divide by 2 */ -#define LCD_F_CTL_DIV_2 ((uint32_t)0x00001000) /*!< Divide by 3 */ -#define LCD_F_CTL_DIV_3 ((uint32_t)0x00001800) /*!< Divide by 4 */ -#define LCD_F_CTL_DIV_4 ((uint32_t)0x00002000) /*!< Divide by 5 */ -#define LCD_F_CTL_DIV_5 ((uint32_t)0x00002800) /*!< Divide by 6 */ -#define LCD_F_CTL_DIV_6 ((uint32_t)0x00003000) /*!< Divide by 7 */ -#define LCD_F_CTL_DIV_7 ((uint32_t)0x00003800) /*!< Divide by 8 */ -#define LCD_F_CTL_DIV_8 ((uint32_t)0x00004000) /*!< Divide by 9 */ -#define LCD_F_CTL_DIV_9 ((uint32_t)0x00004800) /*!< Divide by 10 */ -#define LCD_F_CTL_DIV_10 ((uint32_t)0x00005000) /*!< Divide by 11 */ -#define LCD_F_CTL_DIV_11 ((uint32_t)0x00005800) /*!< Divide by 12 */ -#define LCD_F_CTL_DIV_12 ((uint32_t)0x00006000) /*!< Divide by 13 */ -#define LCD_F_CTL_DIV_13 ((uint32_t)0x00006800) /*!< Divide by 14 */ -#define LCD_F_CTL_DIV_14 ((uint32_t)0x00007000) /*!< Divide by 15 */ -#define LCD_F_CTL_DIV_15 ((uint32_t)0x00007800) /*!< Divide by 16 */ -#define LCD_F_CTL_DIV_16 ((uint32_t)0x00008000) /*!< Divide by 17 */ -#define LCD_F_CTL_DIV_17 ((uint32_t)0x00008800) /*!< Divide by 18 */ -#define LCD_F_CTL_DIV_18 ((uint32_t)0x00009000) /*!< Divide by 19 */ -#define LCD_F_CTL_DIV_19 ((uint32_t)0x00009800) /*!< Divide by 20 */ -#define LCD_F_CTL_DIV_20 ((uint32_t)0x0000A000) /*!< Divide by 21 */ -#define LCD_F_CTL_DIV_21 ((uint32_t)0x0000A800) /*!< Divide by 22 */ -#define LCD_F_CTL_DIV_22 ((uint32_t)0x0000B000) /*!< Divide by 23 */ -#define LCD_F_CTL_DIV_23 ((uint32_t)0x0000B800) /*!< Divide by 24 */ -#define LCD_F_CTL_DIV_24 ((uint32_t)0x0000C000) /*!< Divide by 25 */ -#define LCD_F_CTL_DIV_25 ((uint32_t)0x0000C800) /*!< Divide by 26 */ -#define LCD_F_CTL_DIV_26 ((uint32_t)0x0000D000) /*!< Divide by 27 */ -#define LCD_F_CTL_DIV_27 ((uint32_t)0x0000D800) /*!< Divide by 28 */ -#define LCD_F_CTL_DIV_28 ((uint32_t)0x0000E000) /*!< Divide by 29 */ -#define LCD_F_CTL_DIV_29 ((uint32_t)0x0000E800) /*!< Divide by 30 */ -#define LCD_F_CTL_DIV_30 ((uint32_t)0x0000F000) /*!< Divide by 31 */ -#define LCD_F_CTL_DIV_31 ((uint32_t)0x0000F800) /*!< Divide by 32 */ -/* LCD_F_CTL[SSEL] Bits */ -#define LCD_F_CTL_SSEL_OFS (16) /*!< LCDSSEL Bit Offset */ -#define LCD_F_CTL_SSEL_MASK ((uint32_t)0x00030000) /*!< LCDSSEL Bit Mask */ -#define LCD_F_CTL_SSEL0 ((uint32_t)0x00010000) /*!< SSEL Bit 0 */ -#define LCD_F_CTL_SSEL1 ((uint32_t)0x00020000) /*!< SSEL Bit 1 */ -#define LCD_F_CTL_SSEL_0 ((uint32_t)0x00000000) /*!< ACLK */ -#define LCD_F_CTL_SSEL_1 ((uint32_t)0x00010000) /*!< VLOCLK */ -#define LCD_F_CTL_SSEL_2 ((uint32_t)0x00020000) /*!< REFOCLK */ -#define LCD_F_CTL_SSEL_3 ((uint32_t)0x00030000) /*!< LFXTCLK */ -/* LCD_F_BMCTL[BLKMOD] Bits */ -#define LCD_F_BMCTL_BLKMOD_OFS ( 0) /*!< LCDBLKMODx Bit Offset */ -#define LCD_F_BMCTL_BLKMOD_MASK ((uint32_t)0x00000003) /*!< LCDBLKMODx Bit Mask */ -#define LCD_F_BMCTL_BLKMOD0 ((uint32_t)0x00000001) /*!< BLKMOD Bit 0 */ -#define LCD_F_BMCTL_BLKMOD1 ((uint32_t)0x00000002) /*!< BLKMOD Bit 1 */ -#define LCD_F_BMCTL_BLKMOD_0 ((uint32_t)0x00000000) /*!< Blinking disabled */ -#define LCD_F_BMCTL_BLKMOD_1 ((uint32_t)0x00000001) /*!< Blinking of individual segments as enabled in blinking memory register */ - /* LCDBMx. */ -#define LCD_F_BMCTL_BLKMOD_2 ((uint32_t)0x00000002) /*!< Blinking of all segments */ -#define LCD_F_BMCTL_BLKMOD_3 ((uint32_t)0x00000003) /*!< Switching between display contents as stored in LCDMx and LCDBMx memory */ - /* registers. */ -/* LCD_F_BMCTL[BLKPRE] Bits */ -#define LCD_F_BMCTL_BLKPRE_OFS ( 2) /*!< LCDBLKPREx Bit Offset */ -#define LCD_F_BMCTL_BLKPRE_MASK ((uint32_t)0x0000001C) /*!< LCDBLKPREx Bit Mask */ -#define LCD_F_BMCTL_BLKPRE0 ((uint32_t)0x00000004) /*!< BLKPRE Bit 0 */ -#define LCD_F_BMCTL_BLKPRE1 ((uint32_t)0x00000008) /*!< BLKPRE Bit 1 */ -#define LCD_F_BMCTL_BLKPRE2 ((uint32_t)0x00000010) /*!< BLKPRE Bit 2 */ -#define LCD_F_BMCTL_BLKPRE_0 ((uint32_t)0x00000000) /*!< Divide by 512 */ -#define LCD_F_BMCTL_BLKPRE_1 ((uint32_t)0x00000004) /*!< Divide by 1024 */ -#define LCD_F_BMCTL_BLKPRE_2 ((uint32_t)0x00000008) /*!< Divide by 2048 */ -#define LCD_F_BMCTL_BLKPRE_3 ((uint32_t)0x0000000C) /*!< Divide by 4096 */ -#define LCD_F_BMCTL_BLKPRE_4 ((uint32_t)0x00000010) /*!< Divide by 8162 */ -#define LCD_F_BMCTL_BLKPRE_5 ((uint32_t)0x00000014) /*!< Divide by 16384 */ -#define LCD_F_BMCTL_BLKPRE_6 ((uint32_t)0x00000018) /*!< Divide by 32768 */ -#define LCD_F_BMCTL_BLKPRE_7 ((uint32_t)0x0000001C) /*!< Divide by 65536 */ -/* LCD_F_BMCTL[BLKDIV] Bits */ -#define LCD_F_BMCTL_BLKDIV_OFS ( 5) /*!< LCDBLKDIVx Bit Offset */ -#define LCD_F_BMCTL_BLKDIV_MASK ((uint32_t)0x000000E0) /*!< LCDBLKDIVx Bit Mask */ -#define LCD_F_BMCTL_BLKDIV0 ((uint32_t)0x00000020) /*!< BLKDIV Bit 0 */ -#define LCD_F_BMCTL_BLKDIV1 ((uint32_t)0x00000040) /*!< BLKDIV Bit 1 */ -#define LCD_F_BMCTL_BLKDIV2 ((uint32_t)0x00000080) /*!< BLKDIV Bit 2 */ -#define LCD_F_BMCTL_BLKDIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_BMCTL_BLKDIV_1 ((uint32_t)0x00000020) /*!< Divide by 2 */ -#define LCD_F_BMCTL_BLKDIV_2 ((uint32_t)0x00000040) /*!< Divide by 3 */ -#define LCD_F_BMCTL_BLKDIV_3 ((uint32_t)0x00000060) /*!< Divide by 4 */ -#define LCD_F_BMCTL_BLKDIV_4 ((uint32_t)0x00000080) /*!< Divide by 5 */ -#define LCD_F_BMCTL_BLKDIV_5 ((uint32_t)0x000000A0) /*!< Divide by 6 */ -#define LCD_F_BMCTL_BLKDIV_6 ((uint32_t)0x000000C0) /*!< Divide by 7 */ -#define LCD_F_BMCTL_BLKDIV_7 ((uint32_t)0x000000E0) /*!< Divide by 8 */ -/* LCD_F_BMCTL[DISP] Bits */ -#define LCD_F_BMCTL_DISP_OFS (16) /*!< LCDDISP Bit Offset */ -#define LCD_F_BMCTL_DISP ((uint32_t)0x00010000) /*!< Select LCD memory registers for display */ -/* LCD_F_BMCTL[CLRM] Bits */ -#define LCD_F_BMCTL_CLRM_OFS (17) /*!< LCDCLRM Bit Offset */ -#define LCD_F_BMCTL_CLRM ((uint32_t)0x00020000) /*!< Clear LCD memory */ -/* LCD_F_BMCTL[CLRBM] Bits */ -#define LCD_F_BMCTL_CLRBM_OFS (18) /*!< LCDCLRBM Bit Offset */ -#define LCD_F_BMCTL_CLRBM ((uint32_t)0x00040000) /*!< Clear LCD blinking memory */ -/* LCD_F_VCTL[LCD2B] Bits */ -#define LCD_F_VCTL_LCD2B_OFS ( 0) /*!< LCD2B Bit Offset */ -#define LCD_F_VCTL_LCD2B ((uint32_t)0x00000001) /*!< Bias select. */ -/* LCD_F_VCTL[EXTBIAS] Bits */ -#define LCD_F_VCTL_EXTBIAS_OFS ( 5) /*!< LCDEXTBIAS Bit Offset */ -#define LCD_F_VCTL_EXTBIAS ((uint32_t)0x00000020) /*!< V2 to V4 voltage select */ -/* LCD_F_VCTL[R03EXT] Bits */ -#define LCD_F_VCTL_R03EXT_OFS ( 6) /*!< R03EXT Bit Offset */ -#define LCD_F_VCTL_R03EXT ((uint32_t)0x00000040) /*!< V5 voltage select */ -/* LCD_F_VCTL[REXT] Bits */ -#define LCD_F_VCTL_REXT_OFS ( 7) /*!< LCDREXT Bit Offset */ -#define LCD_F_VCTL_REXT ((uint32_t)0x00000080) /*!< V2 to V4 voltage on external Rx3 pins */ -/* LCD_F_PCTL0[S0] Bits */ -#define LCD_F_PCTL0_S0_OFS ( 0) /*!< LCDS0 Bit Offset */ -#define LCD_F_PCTL0_S0 ((uint32_t)0x00000001) /*!< LCD pin 0 enable */ -/* LCD_F_PCTL0[S1] Bits */ -#define LCD_F_PCTL0_S1_OFS ( 1) /*!< LCDS1 Bit Offset */ -#define LCD_F_PCTL0_S1 ((uint32_t)0x00000002) /*!< LCD pin 1 enable */ -/* LCD_F_PCTL0[S2] Bits */ -#define LCD_F_PCTL0_S2_OFS ( 2) /*!< LCDS2 Bit Offset */ -#define LCD_F_PCTL0_S2 ((uint32_t)0x00000004) /*!< LCD pin 2 enable */ -/* LCD_F_PCTL0[S3] Bits */ -#define LCD_F_PCTL0_S3_OFS ( 3) /*!< LCDS3 Bit Offset */ -#define LCD_F_PCTL0_S3 ((uint32_t)0x00000008) /*!< LCD pin 3 enable */ -/* LCD_F_PCTL0[S4] Bits */ -#define LCD_F_PCTL0_S4_OFS ( 4) /*!< LCDS4 Bit Offset */ -#define LCD_F_PCTL0_S4 ((uint32_t)0x00000010) /*!< LCD pin 4 enable */ -/* LCD_F_PCTL0[S5] Bits */ -#define LCD_F_PCTL0_S5_OFS ( 5) /*!< LCDS5 Bit Offset */ -#define LCD_F_PCTL0_S5 ((uint32_t)0x00000020) /*!< LCD pin 5 enable */ -/* LCD_F_PCTL0[S6] Bits */ -#define LCD_F_PCTL0_S6_OFS ( 6) /*!< LCDS6 Bit Offset */ -#define LCD_F_PCTL0_S6 ((uint32_t)0x00000040) /*!< LCD pin 6 enable */ -/* LCD_F_PCTL0[S7] Bits */ -#define LCD_F_PCTL0_S7_OFS ( 7) /*!< LCDS7 Bit Offset */ -#define LCD_F_PCTL0_S7 ((uint32_t)0x00000080) /*!< LCD pin 7 enable */ -/* LCD_F_PCTL0[S8] Bits */ -#define LCD_F_PCTL0_S8_OFS ( 8) /*!< LCDS8 Bit Offset */ -#define LCD_F_PCTL0_S8 ((uint32_t)0x00000100) /*!< LCD pin 8 enable */ -/* LCD_F_PCTL0[S9] Bits */ -#define LCD_F_PCTL0_S9_OFS ( 9) /*!< LCDS9 Bit Offset */ -#define LCD_F_PCTL0_S9 ((uint32_t)0x00000200) /*!< LCD pin 9 enable */ -/* LCD_F_PCTL0[S10] Bits */ -#define LCD_F_PCTL0_S10_OFS (10) /*!< LCDS10 Bit Offset */ -#define LCD_F_PCTL0_S10 ((uint32_t)0x00000400) /*!< LCD pin 10 enable */ -/* LCD_F_PCTL0[S11] Bits */ -#define LCD_F_PCTL0_S11_OFS (11) /*!< LCDS11 Bit Offset */ -#define LCD_F_PCTL0_S11 ((uint32_t)0x00000800) /*!< LCD pin 11 enable */ -/* LCD_F_PCTL0[S12] Bits */ -#define LCD_F_PCTL0_S12_OFS (12) /*!< LCDS12 Bit Offset */ -#define LCD_F_PCTL0_S12 ((uint32_t)0x00001000) /*!< LCD pin 12 enable */ -/* LCD_F_PCTL0[S13] Bits */ -#define LCD_F_PCTL0_S13_OFS (13) /*!< LCDS13 Bit Offset */ -#define LCD_F_PCTL0_S13 ((uint32_t)0x00002000) /*!< LCD pin 13 enable */ -/* LCD_F_PCTL0[S14] Bits */ -#define LCD_F_PCTL0_S14_OFS (14) /*!< LCDS14 Bit Offset */ -#define LCD_F_PCTL0_S14 ((uint32_t)0x00004000) /*!< LCD pin 14 enable */ -/* LCD_F_PCTL0[S15] Bits */ -#define LCD_F_PCTL0_S15_OFS (15) /*!< LCDS15 Bit Offset */ -#define LCD_F_PCTL0_S15 ((uint32_t)0x00008000) /*!< LCD pin 15 enable */ -/* LCD_F_PCTL0[S16] Bits */ -#define LCD_F_PCTL0_S16_OFS (16) /*!< LCDS16 Bit Offset */ -#define LCD_F_PCTL0_S16 ((uint32_t)0x00010000) /*!< LCD pin 16 enable */ -/* LCD_F_PCTL0[S17] Bits */ -#define LCD_F_PCTL0_S17_OFS (17) /*!< LCDS17 Bit Offset */ -#define LCD_F_PCTL0_S17 ((uint32_t)0x00020000) /*!< LCD pin 17 enable */ -/* LCD_F_PCTL0[S18] Bits */ -#define LCD_F_PCTL0_S18_OFS (18) /*!< LCDS18 Bit Offset */ -#define LCD_F_PCTL0_S18 ((uint32_t)0x00040000) /*!< LCD pin 18 enable */ -/* LCD_F_PCTL0[S19] Bits */ -#define LCD_F_PCTL0_S19_OFS (19) /*!< LCDS19 Bit Offset */ -#define LCD_F_PCTL0_S19 ((uint32_t)0x00080000) /*!< LCD pin 19 enable */ -/* LCD_F_PCTL0[S20] Bits */ -#define LCD_F_PCTL0_S20_OFS (20) /*!< LCDS20 Bit Offset */ -#define LCD_F_PCTL0_S20 ((uint32_t)0x00100000) /*!< LCD pin 20 enable */ -/* LCD_F_PCTL0[S21] Bits */ -#define LCD_F_PCTL0_S21_OFS (21) /*!< LCDS21 Bit Offset */ -#define LCD_F_PCTL0_S21 ((uint32_t)0x00200000) /*!< LCD pin 21 enable */ -/* LCD_F_PCTL0[S22] Bits */ -#define LCD_F_PCTL0_S22_OFS (22) /*!< LCDS22 Bit Offset */ -#define LCD_F_PCTL0_S22 ((uint32_t)0x00400000) /*!< LCD pin 22 enable */ -/* LCD_F_PCTL0[S23] Bits */ -#define LCD_F_PCTL0_S23_OFS (23) /*!< LCDS23 Bit Offset */ -#define LCD_F_PCTL0_S23 ((uint32_t)0x00800000) /*!< LCD pin 23 enable */ -/* LCD_F_PCTL0[S24] Bits */ -#define LCD_F_PCTL0_S24_OFS (24) /*!< LCDS24 Bit Offset */ -#define LCD_F_PCTL0_S24 ((uint32_t)0x01000000) /*!< LCD pin 24 enable */ -/* LCD_F_PCTL0[S25] Bits */ -#define LCD_F_PCTL0_S25_OFS (25) /*!< LCDS25 Bit Offset */ -#define LCD_F_PCTL0_S25 ((uint32_t)0x02000000) /*!< LCD pin 25 enable */ -/* LCD_F_PCTL0[S26] Bits */ -#define LCD_F_PCTL0_S26_OFS (26) /*!< LCDS26 Bit Offset */ -#define LCD_F_PCTL0_S26 ((uint32_t)0x04000000) /*!< LCD pin 26 enable */ -/* LCD_F_PCTL0[S27] Bits */ -#define LCD_F_PCTL0_S27_OFS (27) /*!< LCDS27 Bit Offset */ -#define LCD_F_PCTL0_S27 ((uint32_t)0x08000000) /*!< LCD pin 27 enable */ -/* LCD_F_PCTL0[S28] Bits */ -#define LCD_F_PCTL0_S28_OFS (28) /*!< LCDS28 Bit Offset */ -#define LCD_F_PCTL0_S28 ((uint32_t)0x10000000) /*!< LCD pin 28 enable */ -/* LCD_F_PCTL0[S29] Bits */ -#define LCD_F_PCTL0_S29_OFS (29) /*!< LCDS29 Bit Offset */ -#define LCD_F_PCTL0_S29 ((uint32_t)0x20000000) /*!< LCD pin 29 enable */ -/* LCD_F_PCTL0[S30] Bits */ -#define LCD_F_PCTL0_S30_OFS (30) /*!< LCDS30 Bit Offset */ -#define LCD_F_PCTL0_S30 ((uint32_t)0x40000000) /*!< LCD pin 30 enable */ -/* LCD_F_PCTL0[S31] Bits */ -#define LCD_F_PCTL0_S31_OFS (31) /*!< LCDS31 Bit Offset */ -#define LCD_F_PCTL0_S31 ((uint32_t)0x80000000) /*!< LCD pin 31 enable */ -/* LCD_F_PCTL1[S32] Bits */ -#define LCD_F_PCTL1_S32_OFS ( 0) /*!< LCDS32 Bit Offset */ -#define LCD_F_PCTL1_S32 ((uint32_t)0x00000001) /*!< LCD pin 32 enable */ -/* LCD_F_PCTL1[S33] Bits */ -#define LCD_F_PCTL1_S33_OFS ( 1) /*!< LCDS33 Bit Offset */ -#define LCD_F_PCTL1_S33 ((uint32_t)0x00000002) /*!< LCD pin 33 enable */ -/* LCD_F_PCTL1[S34] Bits */ -#define LCD_F_PCTL1_S34_OFS ( 2) /*!< LCDS34 Bit Offset */ -#define LCD_F_PCTL1_S34 ((uint32_t)0x00000004) /*!< LCD pin 34 enable */ -/* LCD_F_PCTL1[S35] Bits */ -#define LCD_F_PCTL1_S35_OFS ( 3) /*!< LCDS35 Bit Offset */ -#define LCD_F_PCTL1_S35 ((uint32_t)0x00000008) /*!< LCD pin 35 enable */ -/* LCD_F_PCTL1[S36] Bits */ -#define LCD_F_PCTL1_S36_OFS ( 4) /*!< LCDS36 Bit Offset */ -#define LCD_F_PCTL1_S36 ((uint32_t)0x00000010) /*!< LCD pin 36 enable */ -/* LCD_F_PCTL1[S37] Bits */ -#define LCD_F_PCTL1_S37_OFS ( 5) /*!< LCDS37 Bit Offset */ -#define LCD_F_PCTL1_S37 ((uint32_t)0x00000020) /*!< LCD pin 37 enable */ -/* LCD_F_PCTL1[S38] Bits */ -#define LCD_F_PCTL1_S38_OFS ( 6) /*!< LCDS38 Bit Offset */ -#define LCD_F_PCTL1_S38 ((uint32_t)0x00000040) /*!< LCD pin 38 enable */ -/* LCD_F_PCTL1[S39] Bits */ -#define LCD_F_PCTL1_S39_OFS ( 7) /*!< LCDS39 Bit Offset */ -#define LCD_F_PCTL1_S39 ((uint32_t)0x00000080) /*!< LCD pin 39 enable */ -/* LCD_F_PCTL1[S40] Bits */ -#define LCD_F_PCTL1_S40_OFS ( 8) /*!< LCDS40 Bit Offset */ -#define LCD_F_PCTL1_S40 ((uint32_t)0x00000100) /*!< LCD pin 40 enable */ -/* LCD_F_PCTL1[S41] Bits */ -#define LCD_F_PCTL1_S41_OFS ( 9) /*!< LCDS41 Bit Offset */ -#define LCD_F_PCTL1_S41 ((uint32_t)0x00000200) /*!< LCD pin 41 enable */ -/* LCD_F_PCTL1[S42] Bits */ -#define LCD_F_PCTL1_S42_OFS (10) /*!< LCDS42 Bit Offset */ -#define LCD_F_PCTL1_S42 ((uint32_t)0x00000400) /*!< LCD pin 42 enable */ -/* LCD_F_PCTL1[S43] Bits */ -#define LCD_F_PCTL1_S43_OFS (11) /*!< LCDS43 Bit Offset */ -#define LCD_F_PCTL1_S43 ((uint32_t)0x00000800) /*!< LCD pin 43 enable */ -/* LCD_F_PCTL1[S44] Bits */ -#define LCD_F_PCTL1_S44_OFS (12) /*!< LCDS44 Bit Offset */ -#define LCD_F_PCTL1_S44 ((uint32_t)0x00001000) /*!< LCD pin 44 enable */ -/* LCD_F_PCTL1[S45] Bits */ -#define LCD_F_PCTL1_S45_OFS (13) /*!< LCDS45 Bit Offset */ -#define LCD_F_PCTL1_S45 ((uint32_t)0x00002000) /*!< LCD pin 45 enable */ -/* LCD_F_PCTL1[S46] Bits */ -#define LCD_F_PCTL1_S46_OFS (14) /*!< LCDS46 Bit Offset */ -#define LCD_F_PCTL1_S46 ((uint32_t)0x00004000) /*!< LCD pin 46 enable */ -/* LCD_F_PCTL1[S47] Bits */ -#define LCD_F_PCTL1_S47_OFS (15) /*!< LCDS47 Bit Offset */ -#define LCD_F_PCTL1_S47 ((uint32_t)0x00008000) /*!< LCD pin 47 enable */ -/* LCD_F_PCTL1[S48] Bits */ -#define LCD_F_PCTL1_S48_OFS (16) /*!< LCDS48 Bit Offset */ -#define LCD_F_PCTL1_S48 ((uint32_t)0x00010000) /*!< LCD pin 48 enable */ -/* LCD_F_PCTL1[S49] Bits */ -#define LCD_F_PCTL1_S49_OFS (17) /*!< LCDS49 Bit Offset */ -#define LCD_F_PCTL1_S49 ((uint32_t)0x00020000) /*!< LCD pin 49 enable */ -/* LCD_F_PCTL1[S50] Bits */ -#define LCD_F_PCTL1_S50_OFS (18) /*!< LCDS50 Bit Offset */ -#define LCD_F_PCTL1_S50 ((uint32_t)0x00040000) /*!< LCD pin 50 enable */ -/* LCD_F_PCTL1[S51] Bits */ -#define LCD_F_PCTL1_S51_OFS (19) /*!< LCDS51 Bit Offset */ -#define LCD_F_PCTL1_S51 ((uint32_t)0x00080000) /*!< LCD pin 51 enable */ -/* LCD_F_PCTL1[S52] Bits */ -#define LCD_F_PCTL1_S52_OFS (20) /*!< LCDS52 Bit Offset */ -#define LCD_F_PCTL1_S52 ((uint32_t)0x00100000) /*!< LCD pin 52 enable */ -/* LCD_F_PCTL1[S53] Bits */ -#define LCD_F_PCTL1_S53_OFS (21) /*!< LCDS53 Bit Offset */ -#define LCD_F_PCTL1_S53 ((uint32_t)0x00200000) /*!< LCD pin 53 enable */ -/* LCD_F_PCTL1[S54] Bits */ -#define LCD_F_PCTL1_S54_OFS (22) /*!< LCDS54 Bit Offset */ -#define LCD_F_PCTL1_S54 ((uint32_t)0x00400000) /*!< LCD pin 54 enable */ -/* LCD_F_PCTL1[S55] Bits */ -#define LCD_F_PCTL1_S55_OFS (23) /*!< LCDS55 Bit Offset */ -#define LCD_F_PCTL1_S55 ((uint32_t)0x00800000) /*!< LCD pin 55 enable */ -/* LCD_F_PCTL1[S56] Bits */ -#define LCD_F_PCTL1_S56_OFS (24) /*!< LCDS56 Bit Offset */ -#define LCD_F_PCTL1_S56 ((uint32_t)0x01000000) /*!< LCD pin 56 enable */ -/* LCD_F_PCTL1[S57] Bits */ -#define LCD_F_PCTL1_S57_OFS (25) /*!< LCDS57 Bit Offset */ -#define LCD_F_PCTL1_S57 ((uint32_t)0x02000000) /*!< LCD pin 57 enable */ -/* LCD_F_PCTL1[S58] Bits */ -#define LCD_F_PCTL1_S58_OFS (26) /*!< LCDS58 Bit Offset */ -#define LCD_F_PCTL1_S58 ((uint32_t)0x04000000) /*!< LCD pin 58 enable */ -/* LCD_F_PCTL1[S59] Bits */ -#define LCD_F_PCTL1_S59_OFS (27) /*!< LCDS59 Bit Offset */ -#define LCD_F_PCTL1_S59 ((uint32_t)0x08000000) /*!< LCD pin 59 enable */ -/* LCD_F_PCTL1[S60] Bits */ -#define LCD_F_PCTL1_S60_OFS (28) /*!< LCDS60 Bit Offset */ -#define LCD_F_PCTL1_S60 ((uint32_t)0x10000000) /*!< LCD pin 60 enable */ -/* LCD_F_PCTL1[S61] Bits */ -#define LCD_F_PCTL1_S61_OFS (29) /*!< LCDS61 Bit Offset */ -#define LCD_F_PCTL1_S61 ((uint32_t)0x20000000) /*!< LCD pin 61 enable */ -/* LCD_F_PCTL1[S62] Bits */ -#define LCD_F_PCTL1_S62_OFS (30) /*!< LCDS62 Bit Offset */ -#define LCD_F_PCTL1_S62 ((uint32_t)0x40000000) /*!< LCD pin 62 enable */ -/* LCD_F_PCTL1[S63] Bits */ -#define LCD_F_PCTL1_S63_OFS (31) /*!< LCDS63 Bit Offset */ -#define LCD_F_PCTL1_S63 ((uint32_t)0x80000000) /*!< LCD pin 63 enable */ -/* LCD_F_CSSEL0[CSS0] Bits */ -#define LCD_F_CSSEL0_CSS0_OFS ( 0) /*!< LCDCSS0 Bit Offset */ -#define LCD_F_CSSEL0_CSS0 ((uint32_t)0x00000001) /*!< L0 Com Seg select */ -/* LCD_F_CSSEL0[CSS1] Bits */ -#define LCD_F_CSSEL0_CSS1_OFS ( 1) /*!< LCDCSS1 Bit Offset */ -#define LCD_F_CSSEL0_CSS1 ((uint32_t)0x00000002) /*!< L1 Com Seg select */ -/* LCD_F_CSSEL0[CSS2] Bits */ -#define LCD_F_CSSEL0_CSS2_OFS ( 2) /*!< LCDCSS2 Bit Offset */ -#define LCD_F_CSSEL0_CSS2 ((uint32_t)0x00000004) /*!< L2 Com Seg select */ -/* LCD_F_CSSEL0[CSS3] Bits */ -#define LCD_F_CSSEL0_CSS3_OFS ( 3) /*!< LCDCSS3 Bit Offset */ -#define LCD_F_CSSEL0_CSS3 ((uint32_t)0x00000008) /*!< L3 Com Seg select */ -/* LCD_F_CSSEL0[CSS4] Bits */ -#define LCD_F_CSSEL0_CSS4_OFS ( 4) /*!< LCDCSS4 Bit Offset */ -#define LCD_F_CSSEL0_CSS4 ((uint32_t)0x00000010) /*!< L4 Com Seg select */ -/* LCD_F_CSSEL0[CSS5] Bits */ -#define LCD_F_CSSEL0_CSS5_OFS ( 5) /*!< LCDCSS5 Bit Offset */ -#define LCD_F_CSSEL0_CSS5 ((uint32_t)0x00000020) /*!< L5 Com Seg select */ -/* LCD_F_CSSEL0[CSS6] Bits */ -#define LCD_F_CSSEL0_CSS6_OFS ( 6) /*!< LCDCSS6 Bit Offset */ -#define LCD_F_CSSEL0_CSS6 ((uint32_t)0x00000040) /*!< L6 Com Seg select */ -/* LCD_F_CSSEL0[CSS7] Bits */ -#define LCD_F_CSSEL0_CSS7_OFS ( 7) /*!< LCDCSS7 Bit Offset */ -#define LCD_F_CSSEL0_CSS7 ((uint32_t)0x00000080) /*!< L7 Com Seg select */ -/* LCD_F_CSSEL0[CSS8] Bits */ -#define LCD_F_CSSEL0_CSS8_OFS ( 8) /*!< LCDCSS8 Bit Offset */ -#define LCD_F_CSSEL0_CSS8 ((uint32_t)0x00000100) /*!< L8 Com Seg select */ -/* LCD_F_CSSEL0[CSS9] Bits */ -#define LCD_F_CSSEL0_CSS9_OFS ( 9) /*!< LCDCSS9 Bit Offset */ -#define LCD_F_CSSEL0_CSS9 ((uint32_t)0x00000200) /*!< L9 Com Seg select */ -/* LCD_F_CSSEL0[CSS10] Bits */ -#define LCD_F_CSSEL0_CSS10_OFS (10) /*!< LCDCSS10 Bit Offset */ -#define LCD_F_CSSEL0_CSS10 ((uint32_t)0x00000400) /*!< L10 Com Seg select */ -/* LCD_F_CSSEL0[CSS11] Bits */ -#define LCD_F_CSSEL0_CSS11_OFS (11) /*!< LCDCSS11 Bit Offset */ -#define LCD_F_CSSEL0_CSS11 ((uint32_t)0x00000800) /*!< L11 Com Seg select */ -/* LCD_F_CSSEL0[CSS12] Bits */ -#define LCD_F_CSSEL0_CSS12_OFS (12) /*!< LCDCSS12 Bit Offset */ -#define LCD_F_CSSEL0_CSS12 ((uint32_t)0x00001000) /*!< L12 Com Seg select */ -/* LCD_F_CSSEL0[CSS13] Bits */ -#define LCD_F_CSSEL0_CSS13_OFS (13) /*!< LCDCSS13 Bit Offset */ -#define LCD_F_CSSEL0_CSS13 ((uint32_t)0x00002000) /*!< L13 Com Seg select */ -/* LCD_F_CSSEL0[CSS14] Bits */ -#define LCD_F_CSSEL0_CSS14_OFS (14) /*!< LCDCSS14 Bit Offset */ -#define LCD_F_CSSEL0_CSS14 ((uint32_t)0x00004000) /*!< L14 Com Seg select */ -/* LCD_F_CSSEL0[CSS15] Bits */ -#define LCD_F_CSSEL0_CSS15_OFS (15) /*!< LCDCSS15 Bit Offset */ -#define LCD_F_CSSEL0_CSS15 ((uint32_t)0x00008000) /*!< L15 Com Seg select */ -/* LCD_F_CSSEL0[CSS16] Bits */ -#define LCD_F_CSSEL0_CSS16_OFS (16) /*!< LCDCSS16 Bit Offset */ -#define LCD_F_CSSEL0_CSS16 ((uint32_t)0x00010000) /*!< L16 Com Seg select */ -/* LCD_F_CSSEL0[CSS17] Bits */ -#define LCD_F_CSSEL0_CSS17_OFS (17) /*!< LCDCSS17 Bit Offset */ -#define LCD_F_CSSEL0_CSS17 ((uint32_t)0x00020000) /*!< L17 Com Seg select */ -/* LCD_F_CSSEL0[CSS18] Bits */ -#define LCD_F_CSSEL0_CSS18_OFS (18) /*!< LCDCSS18 Bit Offset */ -#define LCD_F_CSSEL0_CSS18 ((uint32_t)0x00040000) /*!< L18 Com Seg select */ -/* LCD_F_CSSEL0[CSS19] Bits */ -#define LCD_F_CSSEL0_CSS19_OFS (19) /*!< LCDCSS19 Bit Offset */ -#define LCD_F_CSSEL0_CSS19 ((uint32_t)0x00080000) /*!< L19 Com Seg select */ -/* LCD_F_CSSEL0[CSS20] Bits */ -#define LCD_F_CSSEL0_CSS20_OFS (20) /*!< LCDCSS20 Bit Offset */ -#define LCD_F_CSSEL0_CSS20 ((uint32_t)0x00100000) /*!< L20 Com Seg select */ -/* LCD_F_CSSEL0[CSS21] Bits */ -#define LCD_F_CSSEL0_CSS21_OFS (21) /*!< LCDCSS21 Bit Offset */ -#define LCD_F_CSSEL0_CSS21 ((uint32_t)0x00200000) /*!< L21 Com Seg select */ -/* LCD_F_CSSEL0[CSS22] Bits */ -#define LCD_F_CSSEL0_CSS22_OFS (22) /*!< LCDCSS22 Bit Offset */ -#define LCD_F_CSSEL0_CSS22 ((uint32_t)0x00400000) /*!< L22 Com Seg select */ -/* LCD_F_CSSEL0[CSS23] Bits */ -#define LCD_F_CSSEL0_CSS23_OFS (23) /*!< LCDCSS23 Bit Offset */ -#define LCD_F_CSSEL0_CSS23 ((uint32_t)0x00800000) /*!< L23 Com Seg select */ -/* LCD_F_CSSEL0[CSS24] Bits */ -#define LCD_F_CSSEL0_CSS24_OFS (24) /*!< LCDCSS24 Bit Offset */ -#define LCD_F_CSSEL0_CSS24 ((uint32_t)0x01000000) /*!< L24 Com Seg select */ -/* LCD_F_CSSEL0[CSS25] Bits */ -#define LCD_F_CSSEL0_CSS25_OFS (25) /*!< LCDCSS25 Bit Offset */ -#define LCD_F_CSSEL0_CSS25 ((uint32_t)0x02000000) /*!< L25 Com Seg select */ -/* LCD_F_CSSEL0[CSS26] Bits */ -#define LCD_F_CSSEL0_CSS26_OFS (26) /*!< LCDCSS26 Bit Offset */ -#define LCD_F_CSSEL0_CSS26 ((uint32_t)0x04000000) /*!< L26 Com Seg select */ -/* LCD_F_CSSEL0[CSS27] Bits */ -#define LCD_F_CSSEL0_CSS27_OFS (27) /*!< LCDCSS27 Bit Offset */ -#define LCD_F_CSSEL0_CSS27 ((uint32_t)0x08000000) /*!< L27 Com Seg select */ -/* LCD_F_CSSEL0[CSS28] Bits */ -#define LCD_F_CSSEL0_CSS28_OFS (28) /*!< LCDCSS28 Bit Offset */ -#define LCD_F_CSSEL0_CSS28 ((uint32_t)0x10000000) /*!< L28 Com Seg select */ -/* LCD_F_CSSEL0[CSS29] Bits */ -#define LCD_F_CSSEL0_CSS29_OFS (29) /*!< LCDCSS29 Bit Offset */ -#define LCD_F_CSSEL0_CSS29 ((uint32_t)0x20000000) /*!< L29 Com Seg select */ -/* LCD_F_CSSEL0[CSS30] Bits */ -#define LCD_F_CSSEL0_CSS30_OFS (30) /*!< LCDCSS30 Bit Offset */ -#define LCD_F_CSSEL0_CSS30 ((uint32_t)0x40000000) /*!< L30 Com Seg select */ -/* LCD_F_CSSEL0[CSS31] Bits */ -#define LCD_F_CSSEL0_CSS31_OFS (31) /*!< LCDCSS31 Bit Offset */ -#define LCD_F_CSSEL0_CSS31 ((uint32_t)0x80000000) /*!< L31 Com Seg select */ -/* LCD_F_CSSEL1[CSS32] Bits */ -#define LCD_F_CSSEL1_CSS32_OFS ( 0) /*!< LCDCSS32 Bit Offset */ -#define LCD_F_CSSEL1_CSS32 ((uint32_t)0x00000001) /*!< L32 Com Seg select */ -/* LCD_F_CSSEL1[CSS33] Bits */ -#define LCD_F_CSSEL1_CSS33_OFS ( 1) /*!< LCDCSS33 Bit Offset */ -#define LCD_F_CSSEL1_CSS33 ((uint32_t)0x00000002) /*!< L33 Com Seg select */ -/* LCD_F_CSSEL1[CSS34] Bits */ -#define LCD_F_CSSEL1_CSS34_OFS ( 2) /*!< LCDCSS34 Bit Offset */ -#define LCD_F_CSSEL1_CSS34 ((uint32_t)0x00000004) /*!< L34 Com Seg select */ -/* LCD_F_CSSEL1[CSS35] Bits */ -#define LCD_F_CSSEL1_CSS35_OFS ( 3) /*!< LCDCSS35 Bit Offset */ -#define LCD_F_CSSEL1_CSS35 ((uint32_t)0x00000008) /*!< L35 Com Seg select */ -/* LCD_F_CSSEL1[CSS36] Bits */ -#define LCD_F_CSSEL1_CSS36_OFS ( 4) /*!< LCDCSS36 Bit Offset */ -#define LCD_F_CSSEL1_CSS36 ((uint32_t)0x00000010) /*!< L36 Com Seg select */ -/* LCD_F_CSSEL1[CSS37] Bits */ -#define LCD_F_CSSEL1_CSS37_OFS ( 5) /*!< LCDCSS37 Bit Offset */ -#define LCD_F_CSSEL1_CSS37 ((uint32_t)0x00000020) /*!< L37 Com Seg select */ -/* LCD_F_CSSEL1[CSS38] Bits */ -#define LCD_F_CSSEL1_CSS38_OFS ( 6) /*!< LCDCSS38 Bit Offset */ -#define LCD_F_CSSEL1_CSS38 ((uint32_t)0x00000040) /*!< L38 Com Seg select */ -/* LCD_F_CSSEL1[CSS39] Bits */ -#define LCD_F_CSSEL1_CSS39_OFS ( 7) /*!< LCDCSS39 Bit Offset */ -#define LCD_F_CSSEL1_CSS39 ((uint32_t)0x00000080) /*!< L39 Com Seg select */ -/* LCD_F_CSSEL1[CSS40] Bits */ -#define LCD_F_CSSEL1_CSS40_OFS ( 8) /*!< LCDCSS40 Bit Offset */ -#define LCD_F_CSSEL1_CSS40 ((uint32_t)0x00000100) /*!< L40 Com Seg select */ -/* LCD_F_CSSEL1[CSS41] Bits */ -#define LCD_F_CSSEL1_CSS41_OFS ( 9) /*!< LCDCSS41 Bit Offset */ -#define LCD_F_CSSEL1_CSS41 ((uint32_t)0x00000200) /*!< L41 Com Seg select */ -/* LCD_F_CSSEL1[CSS42] Bits */ -#define LCD_F_CSSEL1_CSS42_OFS (10) /*!< LCDCSS42 Bit Offset */ -#define LCD_F_CSSEL1_CSS42 ((uint32_t)0x00000400) /*!< L42 Com Seg select */ -/* LCD_F_CSSEL1[CSS43] Bits */ -#define LCD_F_CSSEL1_CSS43_OFS (11) /*!< LCDCSS43 Bit Offset */ -#define LCD_F_CSSEL1_CSS43 ((uint32_t)0x00000800) /*!< L43 Com Seg select */ -/* LCD_F_CSSEL1[CSS44] Bits */ -#define LCD_F_CSSEL1_CSS44_OFS (12) /*!< LCDCSS44 Bit Offset */ -#define LCD_F_CSSEL1_CSS44 ((uint32_t)0x00001000) /*!< L44 Com Seg select */ -/* LCD_F_CSSEL1[CSS45] Bits */ -#define LCD_F_CSSEL1_CSS45_OFS (13) /*!< LCDCSS45 Bit Offset */ -#define LCD_F_CSSEL1_CSS45 ((uint32_t)0x00002000) /*!< L45 Com Seg select */ -/* LCD_F_CSSEL1[CSS46] Bits */ -#define LCD_F_CSSEL1_CSS46_OFS (14) /*!< LCDCSS46 Bit Offset */ -#define LCD_F_CSSEL1_CSS46 ((uint32_t)0x00004000) /*!< L46 Com Seg select */ -/* LCD_F_CSSEL1[CSS47] Bits */ -#define LCD_F_CSSEL1_CSS47_OFS (15) /*!< LCDCSS47 Bit Offset */ -#define LCD_F_CSSEL1_CSS47 ((uint32_t)0x00008000) /*!< L47 Com Seg select */ -/* LCD_F_CSSEL1[CSS48] Bits */ -#define LCD_F_CSSEL1_CSS48_OFS (16) /*!< LCDCSS48 Bit Offset */ -#define LCD_F_CSSEL1_CSS48 ((uint32_t)0x00010000) /*!< L48 Com Seg select */ -/* LCD_F_CSSEL1[CSS49] Bits */ -#define LCD_F_CSSEL1_CSS49_OFS (17) /*!< LCDCSS49 Bit Offset */ -#define LCD_F_CSSEL1_CSS49 ((uint32_t)0x00020000) /*!< L49 Com Seg select */ -/* LCD_F_CSSEL1[CSS50] Bits */ -#define LCD_F_CSSEL1_CSS50_OFS (18) /*!< LCDCSS50 Bit Offset */ -#define LCD_F_CSSEL1_CSS50 ((uint32_t)0x00040000) /*!< L50 Com Seg select */ -/* LCD_F_CSSEL1[CSS51] Bits */ -#define LCD_F_CSSEL1_CSS51_OFS (19) /*!< LCDCSS51 Bit Offset */ -#define LCD_F_CSSEL1_CSS51 ((uint32_t)0x00080000) /*!< L51 Com Seg select */ -/* LCD_F_CSSEL1[CSS52] Bits */ -#define LCD_F_CSSEL1_CSS52_OFS (20) /*!< LCDCSS52 Bit Offset */ -#define LCD_F_CSSEL1_CSS52 ((uint32_t)0x00100000) /*!< L52 Com Seg select */ -/* LCD_F_CSSEL1[CSS53] Bits */ -#define LCD_F_CSSEL1_CSS53_OFS (21) /*!< LCDCSS53 Bit Offset */ -#define LCD_F_CSSEL1_CSS53 ((uint32_t)0x00200000) /*!< L53 Com Seg select */ -/* LCD_F_CSSEL1[CSS54] Bits */ -#define LCD_F_CSSEL1_CSS54_OFS (22) /*!< LCDCSS54 Bit Offset */ -#define LCD_F_CSSEL1_CSS54 ((uint32_t)0x00400000) /*!< L54 Com Seg select */ -/* LCD_F_CSSEL1[CSS55] Bits */ -#define LCD_F_CSSEL1_CSS55_OFS (23) /*!< LCDCSS55 Bit Offset */ -#define LCD_F_CSSEL1_CSS55 ((uint32_t)0x00800000) /*!< L55 Com Seg select */ -/* LCD_F_CSSEL1[CSS56] Bits */ -#define LCD_F_CSSEL1_CSS56_OFS (24) /*!< LCDCSS56 Bit Offset */ -#define LCD_F_CSSEL1_CSS56 ((uint32_t)0x01000000) /*!< L56 Com Seg select */ -/* LCD_F_CSSEL1[CSS57] Bits */ -#define LCD_F_CSSEL1_CSS57_OFS (25) /*!< LCDCSS57 Bit Offset */ -#define LCD_F_CSSEL1_CSS57 ((uint32_t)0x02000000) /*!< L57 Com Seg select */ -/* LCD_F_CSSEL1[CSS58] Bits */ -#define LCD_F_CSSEL1_CSS58_OFS (26) /*!< LCDCSS58 Bit Offset */ -#define LCD_F_CSSEL1_CSS58 ((uint32_t)0x04000000) /*!< L58 Com Seg select */ -/* LCD_F_CSSEL1[CSS59] Bits */ -#define LCD_F_CSSEL1_CSS59_OFS (27) /*!< LCDCSS59 Bit Offset */ -#define LCD_F_CSSEL1_CSS59 ((uint32_t)0x08000000) /*!< L59 Com Seg select */ -/* LCD_F_CSSEL1[CSS60] Bits */ -#define LCD_F_CSSEL1_CSS60_OFS (28) /*!< LCDCSS60 Bit Offset */ -#define LCD_F_CSSEL1_CSS60 ((uint32_t)0x10000000) /*!< L60 Com Seg select */ -/* LCD_F_CSSEL1[CSS61] Bits */ -#define LCD_F_CSSEL1_CSS61_OFS (29) /*!< LCDCSS61 Bit Offset */ -#define LCD_F_CSSEL1_CSS61 ((uint32_t)0x20000000) /*!< L61 Com Seg select */ -/* LCD_F_CSSEL1[CSS62] Bits */ -#define LCD_F_CSSEL1_CSS62_OFS (30) /*!< LCDCSS62 Bit Offset */ -#define LCD_F_CSSEL1_CSS62 ((uint32_t)0x40000000) /*!< L62 Com Seg select */ -/* LCD_F_CSSEL1[CSS63] Bits */ -#define LCD_F_CSSEL1_CSS63_OFS (31) /*!< LCDCSS63 Bit Offset */ -#define LCD_F_CSSEL1_CSS63 ((uint32_t)0x80000000) /*!< L63 Com Seg select */ -/* LCD_F_ANMCTL[ANMEN] Bits */ -#define LCD_F_ANMCTL_ANMEN_OFS ( 0) /*!< LCDANMEN Bit Offset */ -#define LCD_F_ANMCTL_ANMEN ((uint32_t)0x00000001) /*!< Enable Animation */ -/* LCD_F_ANMCTL[ANMSTP] Bits */ -#define LCD_F_ANMCTL_ANMSTP_OFS ( 1) /*!< LCDANMSTP Bit Offset */ -#define LCD_F_ANMCTL_ANMSTP_MASK ((uint32_t)0x0000000E) /*!< LCDANMSTP Bit Mask */ -#define LCD_F_ANMCTL_ANMSTP0 ((uint32_t)0x00000002) /*!< ANMSTP Bit 0 */ -#define LCD_F_ANMCTL_ANMSTP1 ((uint32_t)0x00000004) /*!< ANMSTP Bit 1 */ -#define LCD_F_ANMCTL_ANMSTP2 ((uint32_t)0x00000008) /*!< ANMSTP Bit 2 */ -#define LCD_F_ANMCTL_ANMSTP_0 ((uint32_t)0x00000000) /*!< T0 */ -#define LCD_F_ANMCTL_ANMSTP_1 ((uint32_t)0x00000002) /*!< T0 to T1 */ -#define LCD_F_ANMCTL_ANMSTP_2 ((uint32_t)0x00000004) /*!< T0 to T2 */ -#define LCD_F_ANMCTL_ANMSTP_3 ((uint32_t)0x00000006) /*!< T0 to T3 */ -#define LCD_F_ANMCTL_ANMSTP_4 ((uint32_t)0x00000008) /*!< T0 to T4 */ -#define LCD_F_ANMCTL_ANMSTP_5 ((uint32_t)0x0000000A) /*!< T0 to T5 */ -#define LCD_F_ANMCTL_ANMSTP_6 ((uint32_t)0x0000000C) /*!< T0 to T6 */ -#define LCD_F_ANMCTL_ANMSTP_7 ((uint32_t)0x0000000E) /*!< T0 to T7 */ -/* LCD_F_ANMCTL[ANMCLR] Bits */ -#define LCD_F_ANMCTL_ANMCLR_OFS ( 7) /*!< LCDANMCLR Bit Offset */ -#define LCD_F_ANMCTL_ANMCLR ((uint32_t)0x00000080) /*!< Clear Animation Memory */ -/* LCD_F_ANMCTL[ANMPRE] Bits */ -#define LCD_F_ANMCTL_ANMPRE_OFS (16) /*!< LCDANMPREx Bit Offset */ -#define LCD_F_ANMCTL_ANMPRE_MASK ((uint32_t)0x00070000) /*!< LCDANMPREx Bit Mask */ -#define LCD_F_ANMCTL_ANMPRE0 ((uint32_t)0x00010000) /*!< ANMPRE Bit 0 */ -#define LCD_F_ANMCTL_ANMPRE1 ((uint32_t)0x00020000) /*!< ANMPRE Bit 1 */ -#define LCD_F_ANMCTL_ANMPRE2 ((uint32_t)0x00040000) /*!< ANMPRE Bit 2 */ -#define LCD_F_ANMCTL_ANMPRE_0 ((uint32_t)0x00000000) /*!< Divide by 512 */ -#define LCD_F_ANMCTL_ANMPRE_1 ((uint32_t)0x00010000) /*!< Divide by 1024 */ -#define LCD_F_ANMCTL_ANMPRE_2 ((uint32_t)0x00020000) /*!< Divide by 2048 */ -#define LCD_F_ANMCTL_ANMPRE_3 ((uint32_t)0x00030000) /*!< Divide by 4096 */ -#define LCD_F_ANMCTL_ANMPRE_4 ((uint32_t)0x00040000) /*!< Divide by 8162 */ -#define LCD_F_ANMCTL_ANMPRE_5 ((uint32_t)0x00050000) /*!< Divide by 16384 */ -#define LCD_F_ANMCTL_ANMPRE_6 ((uint32_t)0x00060000) /*!< Divide by 32768 */ -#define LCD_F_ANMCTL_ANMPRE_7 ((uint32_t)0x00070000) /*!< Divide by 65536 */ -/* LCD_F_ANMCTL[ANMDIV] Bits */ -#define LCD_F_ANMCTL_ANMDIV_OFS (19) /*!< LCDANMDIVx Bit Offset */ -#define LCD_F_ANMCTL_ANMDIV_MASK ((uint32_t)0x00380000) /*!< LCDANMDIVx Bit Mask */ -#define LCD_F_ANMCTL_ANMDIV0 ((uint32_t)0x00080000) /*!< ANMDIV Bit 0 */ -#define LCD_F_ANMCTL_ANMDIV1 ((uint32_t)0x00100000) /*!< ANMDIV Bit 1 */ -#define LCD_F_ANMCTL_ANMDIV2 ((uint32_t)0x00200000) /*!< ANMDIV Bit 2 */ -#define LCD_F_ANMCTL_ANMDIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_ANMCTL_ANMDIV_1 ((uint32_t)0x00080000) /*!< Divide by 2 */ -#define LCD_F_ANMCTL_ANMDIV_2 ((uint32_t)0x00100000) /*!< Divide by 3 */ -#define LCD_F_ANMCTL_ANMDIV_3 ((uint32_t)0x00180000) /*!< Divide by 4 */ -#define LCD_F_ANMCTL_ANMDIV_4 ((uint32_t)0x00200000) /*!< Divide by 5 */ -#define LCD_F_ANMCTL_ANMDIV_5 ((uint32_t)0x00280000) /*!< Divide by 6 */ -#define LCD_F_ANMCTL_ANMDIV_6 ((uint32_t)0x00300000) /*!< Divide by 7 */ -#define LCD_F_ANMCTL_ANMDIV_7 ((uint32_t)0x00380000) /*!< Divide by 8 */ -/* LCD_F_IE[BLKOFFIE] Bits */ -#define LCD_F_IE_BLKOFFIE_OFS ( 1) /*!< LCDBLKOFFIE Bit Offset */ -#define LCD_F_IE_BLKOFFIE ((uint32_t)0x00000002) /*!< LCD Blink, segments off interrupt enable */ -/* LCD_F_IE[BLKONIE] Bits */ -#define LCD_F_IE_BLKONIE_OFS ( 2) /*!< LCDBLKONIE Bit Offset */ -#define LCD_F_IE_BLKONIE ((uint32_t)0x00000004) /*!< LCD Blink, segments on interrupt enable */ -/* LCD_F_IE[FRMIE] Bits */ -#define LCD_F_IE_FRMIE_OFS ( 3) /*!< LCDFRMIE Bit Offset */ -#define LCD_F_IE_FRMIE ((uint32_t)0x00000008) /*!< LCD Frame interrupt enable */ -/* LCD_F_IE[ANMSTPIE] Bits */ -#define LCD_F_IE_ANMSTPIE_OFS ( 8) /*!< LCDANMSTPIE Bit Offset */ -#define LCD_F_IE_ANMSTPIE ((uint32_t)0x00000100) /*!< LCD Animation step interrupt enable */ -/* LCD_F_IE[ANMLOOPIE] Bits */ -#define LCD_F_IE_ANMLOOPIE_OFS ( 9) /*!< LCDANMLOOPIE Bit Offset */ -#define LCD_F_IE_ANMLOOPIE ((uint32_t)0x00000200) /*!< LCD Animation loop interrupt enable */ -/* LCD_F_IFG[BLKOFFIFG] Bits */ -#define LCD_F_IFG_BLKOFFIFG_OFS ( 1) /*!< LCDBLKOFFIFG Bit Offset */ -#define LCD_F_IFG_BLKOFFIFG ((uint32_t)0x00000002) /*!< LCD Blink, segments off interrupt flag */ -/* LCD_F_IFG[BLKONIFG] Bits */ -#define LCD_F_IFG_BLKONIFG_OFS ( 2) /*!< LCDBLKONIFG Bit Offset */ -#define LCD_F_IFG_BLKONIFG ((uint32_t)0x00000004) /*!< LCD Blink, segments on interrupt flag */ -/* LCD_F_IFG[FRMIFG] Bits */ -#define LCD_F_IFG_FRMIFG_OFS ( 3) /*!< LCDFRMIFG Bit Offset */ -#define LCD_F_IFG_FRMIFG ((uint32_t)0x00000008) /*!< LCD Frame interrupt flag */ -/* LCD_F_IFG[ANMSTPIFG] Bits */ -#define LCD_F_IFG_ANMSTPIFG_OFS ( 8) /*!< LCDANMSTPIFG Bit Offset */ -#define LCD_F_IFG_ANMSTPIFG ((uint32_t)0x00000100) /*!< LCD Animation step interrupt flag */ -/* LCD_F_IFG[ANMLOOPIFG] Bits */ -#define LCD_F_IFG_ANMLOOPIFG_OFS ( 9) /*!< LCDANMLOOPIFG Bit Offset */ -#define LCD_F_IFG_ANMLOOPIFG ((uint32_t)0x00000200) /*!< LCD Animation loop interrupt flag */ -/* LCD_F_SETIFG[SETLCDBLKOFFIFG] Bits */ -#define LCD_F_SETIFG_SETLCDBLKOFFIFG_OFS ( 1) /*!< SETLCDBLKOFFIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDBLKOFFIFG ((uint32_t)0x00000002) /*!< Sets LCDBLKOFFIFG */ -/* LCD_F_SETIFG[SETLCDBLKONIFG] Bits */ -#define LCD_F_SETIFG_SETLCDBLKONIFG_OFS ( 2) /*!< SETLCDBLKONIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDBLKONIFG ((uint32_t)0x00000004) /*!< Sets LCDBLKONIFG */ -/* LCD_F_SETIFG[SETLCDFRMIFG] Bits */ -#define LCD_F_SETIFG_SETLCDFRMIFG_OFS ( 3) /*!< SETLCDFRMIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDFRMIFG ((uint32_t)0x00000008) /*!< Sets LCDFRMIFG */ -/* LCD_F_SETIFG[SETLCDANMSTPIFG] Bits */ -#define LCD_F_SETIFG_SETLCDANMSTPIFG_OFS ( 8) /*!< SETLCDANMSTPIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDANMSTPIFG ((uint32_t)0x00000100) /*!< Sets LCDANMSTPIFG */ -/* LCD_F_SETIFG[SETLCDANMLOOPIFG] Bits */ -#define LCD_F_SETIFG_SETLCDANMLOOPIFG_OFS ( 9) /*!< SETLCDANMLOOPIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDANMLOOPIFG ((uint32_t)0x00000200) /*!< Sets LCDANMLOOPIFG */ -/* LCD_F_CLRIFG[CLRLCDBLKOFFIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDBLKOFFIFG_OFS ( 1) /*!< CLRLCDBLKOFFIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDBLKOFFIFG ((uint32_t)0x00000002) /*!< Clears LCDBLKOFFIFG */ -/* LCD_F_CLRIFG[CLRLCDBLKONIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDBLKONIFG_OFS ( 2) /*!< CLRLCDBLKONIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDBLKONIFG ((uint32_t)0x00000004) /*!< Clears LCDBLKONIFG */ -/* LCD_F_CLRIFG[CLRLCDFRMIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDFRMIFG_OFS ( 3) /*!< CLRLCDFRMIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDFRMIFG ((uint32_t)0x00000008) /*!< Clears LCDFRMIFG */ -/* LCD_F_CLRIFG[CLRLCDANMSTPIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDANMSTPIFG_OFS ( 8) /*!< CLRLCDANMSTPIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDANMSTPIFG ((uint32_t)0x00000100) /*!< Clears LCDANMSTPIFG */ -/* LCD_F_CLRIFG[CLRLCDANMLOOPIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDANMLOOPIFG_OFS ( 9) /*!< CLRLCDANMLOOPIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDANMLOOPIFG ((uint32_t)0x00000200) /*!< Clears LCDANMLOOPIFG */ - -/****************************************************************************** -* MPU Bits -******************************************************************************/ - -/* Pre-defined bitfield values */ - -/* MPU_RASR_SIZE Bitfield Bits */ -#define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /*!< 32B */ -#define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /*!< 64B */ -#define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /*!< 128B */ -#define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /*!< 256B */ -#define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /*!< 512B */ -#define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /*!< 1KB */ -#define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /*!< 2KB */ -#define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /*!< 4KB */ -#define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /*!< 8KB */ -#define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /*!< 16KB */ -#define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /*!< 32KB */ -#define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /*!< 64KB */ -#define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /*!< 128KB */ -#define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /*!< 256KB */ -#define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /*!< 512KB */ -#define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /*!< 1MB */ -#define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /*!< 2MB */ -#define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /*!< 4MB */ -#define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /*!< 8MB */ -#define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /*!< 16MB */ -#define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /*!< 32MB */ -#define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /*!< 64MB */ -#define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /*!< 128MB */ -#define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /*!< 256MB */ -#define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /*!< 512MB */ -#define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /*!< 1GB */ -#define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /*!< 2GB */ -#define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /*!< 4GB */ - -/* MPU_RASR_AP Bitfield Bits */ -#define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /*!< Privileged permissions: No access. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /*!< Privileged permissions: Read-write. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /*!< Privileged permissions: Read-write. User permissions: Read-only. */ -#define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /*!< Privileged permissions: Read-write. User permissions: Read-write. */ -#define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /*!< Privileged permissions: Read-only. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /*!< Privileged permissions: Read-only. User permissions: Read-only. */ - -/* MPU_RASR_XN Bitfield Bits */ -#define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /*!< Instruction access enabled */ -#define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /*!< Instruction access disabled */ - - -/****************************************************************************** -* NVIC Bits -******************************************************************************/ - -/* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */ -#define NVIC_IPR0_PRI_0_OFS ( 0) /*!< PRI_0 Offset */ -#define NVIC_IPR0_PRI_0_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */ -#define NVIC_IPR0_PRI_1_OFS ( 8) /*!< PRI_1 Offset */ -#define NVIC_IPR0_PRI_1_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */ -#define NVIC_IPR0_PRI_2_OFS (16) /*!< PRI_2 Offset */ -#define NVIC_IPR0_PRI_2_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */ -#define NVIC_IPR0_PRI_3_OFS (24) /*!< PRI_3 Offset */ -#define NVIC_IPR0_PRI_3_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */ -#define NVIC_IPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define NVIC_IPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */ -#define NVIC_IPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define NVIC_IPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */ -#define NVIC_IPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define NVIC_IPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */ -#define NVIC_IPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define NVIC_IPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */ -#define NVIC_IPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define NVIC_IPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */ -#define NVIC_IPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define NVIC_IPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */ -#define NVIC_IPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define NVIC_IPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */ -#define NVIC_IPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define NVIC_IPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */ -#define NVIC_IPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define NVIC_IPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */ -#define NVIC_IPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define NVIC_IPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */ -#define NVIC_IPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define NVIC_IPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */ -#define NVIC_IPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define NVIC_IPR3_PRI_15_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */ -#define NVIC_IPR4_PRI_16_OFS ( 0) /*!< PRI_16 Offset */ -#define NVIC_IPR4_PRI_16_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */ -#define NVIC_IPR4_PRI_17_OFS ( 8) /*!< PRI_17 Offset */ -#define NVIC_IPR4_PRI_17_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */ -#define NVIC_IPR4_PRI_18_OFS (16) /*!< PRI_18 Offset */ -#define NVIC_IPR4_PRI_18_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */ -#define NVIC_IPR4_PRI_19_OFS (24) /*!< PRI_19 Offset */ -#define NVIC_IPR4_PRI_19_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */ -#define NVIC_IPR5_PRI_20_OFS ( 0) /*!< PRI_20 Offset */ -#define NVIC_IPR5_PRI_20_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */ -#define NVIC_IPR5_PRI_21_OFS ( 8) /*!< PRI_21 Offset */ -#define NVIC_IPR5_PRI_21_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */ -#define NVIC_IPR5_PRI_22_OFS (16) /*!< PRI_22 Offset */ -#define NVIC_IPR5_PRI_22_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */ -#define NVIC_IPR5_PRI_23_OFS (24) /*!< PRI_23 Offset */ -#define NVIC_IPR5_PRI_23_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */ -#define NVIC_IPR6_PRI_24_OFS ( 0) /*!< PRI_24 Offset */ -#define NVIC_IPR6_PRI_24_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */ -#define NVIC_IPR6_PRI_25_OFS ( 8) /*!< PRI_25 Offset */ -#define NVIC_IPR6_PRI_25_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */ -#define NVIC_IPR6_PRI_26_OFS (16) /*!< PRI_26 Offset */ -#define NVIC_IPR6_PRI_26_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */ -#define NVIC_IPR6_PRI_27_OFS (24) /*!< PRI_27 Offset */ -#define NVIC_IPR6_PRI_27_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */ -#define NVIC_IPR7_PRI_28_OFS ( 0) /*!< PRI_28 Offset */ -#define NVIC_IPR7_PRI_28_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */ -#define NVIC_IPR7_PRI_29_OFS ( 8) /*!< PRI_29 Offset */ -#define NVIC_IPR7_PRI_29_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */ -#define NVIC_IPR7_PRI_30_OFS (16) /*!< PRI_30 Offset */ -#define NVIC_IPR7_PRI_30_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */ -#define NVIC_IPR7_PRI_31_OFS (24) /*!< PRI_31 Offset */ -#define NVIC_IPR7_PRI_31_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */ -#define NVIC_IPR8_PRI_32_OFS ( 0) /*!< PRI_32 Offset */ -#define NVIC_IPR8_PRI_32_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */ -#define NVIC_IPR8_PRI_33_OFS ( 8) /*!< PRI_33 Offset */ -#define NVIC_IPR8_PRI_33_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */ -#define NVIC_IPR8_PRI_34_OFS (16) /*!< PRI_34 Offset */ -#define NVIC_IPR8_PRI_34_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */ -#define NVIC_IPR8_PRI_35_OFS (24) /*!< PRI_35 Offset */ -#define NVIC_IPR8_PRI_35_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */ -#define NVIC_IPR9_PRI_36_OFS ( 0) /*!< PRI_36 Offset */ -#define NVIC_IPR9_PRI_36_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */ -#define NVIC_IPR9_PRI_37_OFS ( 8) /*!< PRI_37 Offset */ -#define NVIC_IPR9_PRI_37_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */ -#define NVIC_IPR9_PRI_38_OFS (16) /*!< PRI_38 Offset */ -#define NVIC_IPR9_PRI_38_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */ -#define NVIC_IPR9_PRI_39_OFS (24) /*!< PRI_39 Offset */ -#define NVIC_IPR9_PRI_39_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */ -#define NVIC_IPR10_PRI_40_OFS ( 0) /*!< PRI_40 Offset */ -#define NVIC_IPR10_PRI_40_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */ -#define NVIC_IPR10_PRI_41_OFS ( 8) /*!< PRI_41 Offset */ -#define NVIC_IPR10_PRI_41_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */ -#define NVIC_IPR10_PRI_42_OFS (16) /*!< PRI_42 Offset */ -#define NVIC_IPR10_PRI_42_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */ -#define NVIC_IPR10_PRI_43_OFS (24) /*!< PRI_43 Offset */ -#define NVIC_IPR10_PRI_43_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */ -#define NVIC_IPR11_PRI_44_OFS ( 0) /*!< PRI_44 Offset */ -#define NVIC_IPR11_PRI_44_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */ -#define NVIC_IPR11_PRI_45_OFS ( 8) /*!< PRI_45 Offset */ -#define NVIC_IPR11_PRI_45_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */ -#define NVIC_IPR11_PRI_46_OFS (16) /*!< PRI_46 Offset */ -#define NVIC_IPR11_PRI_46_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */ -#define NVIC_IPR11_PRI_47_OFS (24) /*!< PRI_47 Offset */ -#define NVIC_IPR11_PRI_47_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */ -#define NVIC_IPR12_PRI_48_OFS ( 0) /*!< PRI_48 Offset */ -#define NVIC_IPR12_PRI_48_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */ -#define NVIC_IPR12_PRI_49_OFS ( 8) /*!< PRI_49 Offset */ -#define NVIC_IPR12_PRI_49_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */ -#define NVIC_IPR12_PRI_50_OFS (16) /*!< PRI_50 Offset */ -#define NVIC_IPR12_PRI_50_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */ -#define NVIC_IPR12_PRI_51_OFS (24) /*!< PRI_51 Offset */ -#define NVIC_IPR12_PRI_51_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */ -#define NVIC_IPR13_PRI_52_OFS ( 0) /*!< PRI_52 Offset */ -#define NVIC_IPR13_PRI_52_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */ -#define NVIC_IPR13_PRI_53_OFS ( 8) /*!< PRI_53 Offset */ -#define NVIC_IPR13_PRI_53_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */ -#define NVIC_IPR13_PRI_54_OFS (16) /*!< PRI_54 Offset */ -#define NVIC_IPR13_PRI_54_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */ -#define NVIC_IPR13_PRI_55_OFS (24) /*!< PRI_55 Offset */ -#define NVIC_IPR13_PRI_55_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */ -#define NVIC_IPR14_PRI_56_OFS ( 0) /*!< PRI_56 Offset */ -#define NVIC_IPR14_PRI_56_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */ -#define NVIC_IPR14_PRI_57_OFS ( 8) /*!< PRI_57 Offset */ -#define NVIC_IPR14_PRI_57_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */ -#define NVIC_IPR14_PRI_58_OFS (16) /*!< PRI_58 Offset */ -#define NVIC_IPR14_PRI_58_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */ -#define NVIC_IPR14_PRI_59_OFS (24) /*!< PRI_59 Offset */ -#define NVIC_IPR14_PRI_59_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */ -#define NVIC_IPR15_PRI_60_OFS ( 0) /*!< PRI_60 Offset */ -#define NVIC_IPR15_PRI_60_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */ -#define NVIC_IPR15_PRI_61_OFS ( 8) /*!< PRI_61 Offset */ -#define NVIC_IPR15_PRI_61_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */ -#define NVIC_IPR15_PRI_62_OFS (16) /*!< PRI_62 Offset */ -#define NVIC_IPR15_PRI_62_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */ -#define NVIC_IPR15_PRI_63_OFS (24) /*!< PRI_63 Offset */ -#define NVIC_IPR15_PRI_63_M ((uint32_t)0xff000000) /* */ - - -/****************************************************************************** -* PCM Bits -******************************************************************************/ -/* PCM_CTL0[AMR] Bits */ -#define PCM_CTL0_AMR_OFS ( 0) /*!< AMR Bit Offset */ -#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /*!< AMR Bit Mask */ -#define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /*!< AMR Bit 0 */ -#define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /*!< AMR Bit 1 */ -#define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /*!< AMR Bit 2 */ -#define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /*!< AMR Bit 3 */ -#define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -/* PCM_CTL0[LPMR] Bits */ -#define PCM_CTL0_LPMR_OFS ( 4) /*!< LPMR Bit Offset */ -#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /*!< LPMR Bit Mask */ -#define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /*!< LPMR Bit 0 */ -#define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /*!< LPMR Bit 1 */ -#define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /*!< LPMR Bit 2 */ -#define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /*!< LPMR Bit 3 */ -#define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ - /* entered. */ -#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -#define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ - /* entered. */ -#define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -/* PCM_CTL0[CPM] Bits */ -#define PCM_CTL0_CPM_OFS ( 8) /*!< CPM Bit Offset */ -#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /*!< CPM Bit Mask */ -#define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /*!< CPM Bit 0 */ -#define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /*!< CPM Bit 1 */ -#define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /*!< CPM Bit 2 */ -#define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /*!< CPM Bit 3 */ -#define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /*!< CPM Bit 4 */ -#define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /*!< CPM Bit 5 */ -#define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /*!< LPM3 */ -#define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /*!< LPM3 */ -/* PCM_CTL0[KEY] Bits */ -#define PCM_CTL0_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -/* PCM_CTL1[LOCKLPM5] Bits */ -#define PCM_CTL1_LOCKLPM5_OFS ( 0) /*!< LOCKLPM5 Bit Offset */ -#define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /*!< Lock LPM5 */ -/* PCM_CTL1[LOCKBKUP] Bits */ -#define PCM_CTL1_LOCKBKUP_OFS ( 1) /*!< LOCKBKUP Bit Offset */ -#define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /*!< Lock Backup */ -/* PCM_CTL1[FORCE_LPM_ENTRY] Bits */ -#define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /*!< FORCE_LPM_ENTRY Bit Offset */ -#define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /*!< Force LPM entry */ -/* PCM_CTL1[PMR_BUSY] Bits */ -#define PCM_CTL1_PMR_BUSY_OFS ( 8) /*!< PMR_BUSY Bit Offset */ -#define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /*!< Power mode request busy flag */ -/* PCM_CTL1[KEY] Bits */ -#define PCM_CTL1_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -/* PCM_IE[LPM_INVALID_TR_IE] Bits */ -#define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /*!< LPM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /*!< LPM invalid transition interrupt enable */ -/* PCM_IE[LPM_INVALID_CLK_IE] Bits */ -#define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /*!< LPM_INVALID_CLK_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /*!< LPM invalid clock interrupt enable */ -/* PCM_IE[AM_INVALID_TR_IE] Bits */ -#define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /*!< AM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /*!< Active mode invalid transition interrupt enable */ -/* PCM_IE[DCDC_ERROR_IE] Bits */ -#define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /*!< DCDC_ERROR_IE Bit Offset */ -#define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /*!< DC-DC error interrupt enable */ -/* PCM_IFG[LPM_INVALID_TR_IFG] Bits */ -#define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /*!< LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< LPM invalid transition flag */ -/* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */ -#define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< LPM invalid clock flag */ -/* PCM_IFG[AM_INVALID_TR_IFG] Bits */ -#define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /*!< AM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Active mode invalid transition flag */ -/* PCM_IFG[DCDC_ERROR_IFG] Bits */ -#define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /*!< DCDC_ERROR_IFG Bit Offset */ -#define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< DC-DC error flag */ -/* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< Clear LPM invalid transition flag */ -/* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< Clear LPM invalid clock flag */ -/* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /*!< CLR_AM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Clear active mode invalid transition flag */ -/* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /*!< CLR_DCDC_ERROR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< Clear DC-DC error flag */ -/* Pre-defined bitfield values */ -#define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ -#define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ - - -/****************************************************************************** -* PMAP Bits -******************************************************************************/ -/* PMAP_CTL[LOCKED] Bits */ -#define PMAP_CTL_LOCKED_OFS ( 0) /*!< PMAPLOCKED Bit Offset */ -#define PMAP_CTL_LOCKED ((uint16_t)0x0001) /*!< Port mapping lock bit */ -/* PMAP_CTL[PRECFG] Bits */ -#define PMAP_CTL_PRECFG_OFS ( 1) /*!< PMAPRECFG Bit Offset */ -#define PMAP_CTL_PRECFG ((uint16_t)0x0002) /*!< Port mapping reconfiguration control bit */ -/* Pre-defined bitfield values */ -#define PMAP_NONE 0 -#define PMAP_UCA0CLK 1 -#define PMAP_UCA0RXD 2 -#define PMAP_UCA0SOMI 2 -#define PMAP_UCA0TXD 3 -#define PMAP_UCA0SIMO 3 -#define PMAP_UCB0CLK 4 -#define PMAP_UCB0SDA 5 -#define PMAP_UCB0SIMO 5 -#define PMAP_UCB0SCL 6 -#define PMAP_UCB0SOMI 6 -#define PMAP_UCA1STE 7 -#define PMAP_UCA1CLK 8 -#define PMAP_UCA1RXD 9 -#define PMAP_UCA1SOMI 9 -#define PMAP_UCA1TXD 10 -#define PMAP_UCA1SIMO 10 -#define PMAP_UCA2STE 11 -#define PMAP_UCA2CLK 12 -#define PMAP_UCA2RXD 13 -#define PMAP_UCA2SOMI 13 -#define PMAP_UCA2TXD 14 -#define PMAP_UCA2SIMO 14 -#define PMAP_UCB2STE 15 -#define PMAP_UCB2CLK 16 -#define PMAP_UCB2SDA 17 -#define PMAP_UCB2SIMO 17 -#define PMAP_UCB2SCL 18 -#define PMAP_UCB2SOMI 18 -#define PMAP_TA0CCR0A 19 -#define PMAP_TA0CCR1A 20 -#define PMAP_TA0CCR2A 21 -#define PMAP_TA0CCR3A 22 -#define PMAP_TA0CCR4A 23 -#define PMAP_TA1CCR1A 24 -#define PMAP_TA1CCR2A 25 -#define PMAP_TA1CCR3A 26 -#define PMAP_TA1CCR4A 27 -#define PMAP_TA0CLK 28 -#define PMAP_CE0OUT 28 -#define PMAP_TA1CLK 29 -#define PMAP_CE1OUT 29 -#define PMAP_DMAE0 30 -#define PMAP_SMCLK 30 -#define PMAP_ANALOG 31 - -#define PMAP_KEYID_VAL ((uint16_t)0x2D52) /*!< Port Mapping Key */ - - -/****************************************************************************** -* PSS Bits -******************************************************************************/ -/* PSS_KEY[KEY] Bits */ -#define PSS_KEY_KEY_OFS ( 0) /*!< PSSKEY Bit Offset */ -#define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< PSSKEY Bit Mask */ -/* PSS_CTL0[SVSMHOFF] Bits */ -#define PSS_CTL0_SVSMHOFF_OFS ( 0) /*!< SVSMHOFF Bit Offset */ -#define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /*!< SVSM high-side off */ -/* PSS_CTL0[SVSMHLP] Bits */ -#define PSS_CTL0_SVSMHLP_OFS ( 1) /*!< SVSMHLP Bit Offset */ -#define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /*!< SVSM high-side low power normal performance mode */ -/* PSS_CTL0[SVSMHS] Bits */ -#define PSS_CTL0_SVSMHS_OFS ( 2) /*!< SVSMHS Bit Offset */ -#define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /*!< Supply supervisor or monitor selection for the high-side */ -/* PSS_CTL0[SVSMHTH] Bits */ -#define PSS_CTL0_SVSMHTH_OFS ( 3) /*!< SVSMHTH Bit Offset */ -#define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /*!< SVSMHTH Bit Mask */ -/* PSS_CTL0[SVMHOE] Bits */ -#define PSS_CTL0_SVMHOE_OFS ( 6) /*!< SVMHOE Bit Offset */ -#define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /*!< SVSM high-side output enable */ -/* PSS_CTL0[SVMHOUTPOLAL] Bits */ -#define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /*!< SVMHOUTPOLAL Bit Offset */ -#define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /*!< SVMHOUT pin polarity active low */ -/* PSS_CTL0[DCDC_FORCE] Bits */ -#define PSS_CTL0_DCDC_FORCE_OFS (10) /*!< DCDC_FORCE Bit Offset */ -#define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /*!< Force DC-DC regulator operation */ -/* PSS_CTL0[VCORETRAN] Bits */ -#define PSS_CTL0_VCORETRAN_OFS (12) /*!< VCORETRAN Bit Offset */ -#define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /*!< VCORETRAN Bit Mask */ -#define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /*!< VCORETRAN Bit 0 */ -#define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /*!< VCORETRAN Bit 1 */ -#define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -/* PSS_IE[SVSMHIE] Bits */ -#define PSS_IE_SVSMHIE_OFS ( 1) /*!< SVSMHIE Bit Offset */ -#define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /*!< High-side SVSM interrupt enable */ -/* PSS_IFG[SVSMHIFG] Bits */ -#define PSS_IFG_SVSMHIFG_OFS ( 1) /*!< SVSMHIFG Bit Offset */ -#define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /*!< High-side SVSM interrupt flag */ -/* PSS_CLRIFG[CLRSVSMHIFG] Bits */ -#define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /*!< CLRSVSMHIFG Bit Offset */ -#define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /*!< SVSMH clear interrupt flag */ -/* Pre-defined bitfield values */ -#define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /*!< PSS control key value */ - - -/****************************************************************************** -* REF_A Bits -******************************************************************************/ -/* REF_A_CTL0[ON] Bits */ -#define REF_A_CTL0_ON_OFS ( 0) /*!< REFON Bit Offset */ -#define REF_A_CTL0_ON ((uint16_t)0x0001) /*!< Reference enable */ -/* REF_A_CTL0[OUT] Bits */ -#define REF_A_CTL0_OUT_OFS ( 1) /*!< REFOUT Bit Offset */ -#define REF_A_CTL0_OUT ((uint16_t)0x0002) /*!< Reference output buffer */ -/* REF_A_CTL0[TCOFF] Bits */ -#define REF_A_CTL0_TCOFF_OFS ( 3) /*!< REFTCOFF Bit Offset */ -#define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /*!< Temperature sensor disabled */ -/* REF_A_CTL0[VSEL] Bits */ -#define REF_A_CTL0_VSEL_OFS ( 4) /*!< REFVSEL Bit Offset */ -#define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /*!< REFVSEL Bit Mask */ -#define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /*!< VSEL Bit 0 */ -#define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /*!< VSEL Bit 1 */ -#define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /*!< 1.2 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /*!< 1.45 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /*!< 2.5 V available when reference requested or REFON = 1 */ -/* REF_A_CTL0[GENOT] Bits */ -#define REF_A_CTL0_GENOT_OFS ( 6) /*!< REFGENOT Bit Offset */ -#define REF_A_CTL0_GENOT ((uint16_t)0x0040) /*!< Reference generator one-time trigger */ -/* REF_A_CTL0[BGOT] Bits */ -#define REF_A_CTL0_BGOT_OFS ( 7) /*!< REFBGOT Bit Offset */ -#define REF_A_CTL0_BGOT ((uint16_t)0x0080) /*!< Bandgap and bandgap buffer one-time trigger */ -/* REF_A_CTL0[GENACT] Bits */ -#define REF_A_CTL0_GENACT_OFS ( 8) /*!< REFGENACT Bit Offset */ -#define REF_A_CTL0_GENACT ((uint16_t)0x0100) /*!< Reference generator active */ -/* REF_A_CTL0[BGACT] Bits */ -#define REF_A_CTL0_BGACT_OFS ( 9) /*!< REFBGACT Bit Offset */ -#define REF_A_CTL0_BGACT ((uint16_t)0x0200) /*!< Reference bandgap active */ -/* REF_A_CTL0[GENBUSY] Bits */ -#define REF_A_CTL0_GENBUSY_OFS (10) /*!< REFGENBUSY Bit Offset */ -#define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /*!< Reference generator busy */ -/* REF_A_CTL0[BGMODE] Bits */ -#define REF_A_CTL0_BGMODE_OFS (11) /*!< BGMODE Bit Offset */ -#define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /*!< Bandgap mode */ -/* REF_A_CTL0[GENRDY] Bits */ -#define REF_A_CTL0_GENRDY_OFS (12) /*!< REFGENRDY Bit Offset */ -#define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /*!< Variable reference voltage ready status */ -/* REF_A_CTL0[BGRDY] Bits */ -#define REF_A_CTL0_BGRDY_OFS (13) /*!< REFBGRDY Bit Offset */ -#define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /*!< Buffered bandgap voltage ready status */ - -/****************************************************************************** -* RSTCTL Bits -******************************************************************************/ -/* RSTCTL_RESET_REQ[SOFT_REQ] Bits */ -#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /*!< SOFT_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /*!< Soft Reset request */ -/* RSTCTL_RESET_REQ[HARD_REQ] Bits */ -#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /*!< HARD_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /*!< Hard Reset request */ -/* RSTCTL_RESET_REQ[RSTKEY] Bits */ -#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /*!< RSTKEY Bit Offset */ -#define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /*!< RSTKEY Bit Mask */ -/* RSTCTL_HARDRESET_STAT[SRC0] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< Indicates that SRC0 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC1] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< Indicates that SRC1 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC2] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< Indicates that SRC2 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC3] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< Indicates that SRC3 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC4] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< Indicates that SRC4 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC5] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< Indicates that SRC5 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC6] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< Indicates that SRC6 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC7] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< Indicates that SRC7 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC8] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< Indicates that SRC8 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC9] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< Indicates that SRC9 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC10] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< Indicates that SRC10 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC11] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< Indicates that SRC11 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC12] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< Indicates that SRC12 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC13] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< Indicates that SRC13 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC14] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< Indicates that SRC14 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC15] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< Indicates that SRC15 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_CLR[SRC0] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC1] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC2] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC3] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC4] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC5] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC6] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC7] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC8] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC9] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC10] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC11] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC12] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC13] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC14] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC15] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */ -/* RSTCTL_HARDRESET_SET[SRC0] Bits */ -#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC1] Bits */ -#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC2] Bits */ -#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC3] Bits */ -#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC4] Bits */ -#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC5] Bits */ -#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC6] Bits */ -#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC7] Bits */ -#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC8] Bits */ -#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC9] Bits */ -#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC10] Bits */ -#define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC11] Bits */ -#define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC12] Bits */ -#define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC13] Bits */ -#define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC14] Bits */ -#define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC15] Bits */ -#define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_SOFTRESET_STAT[SRC0] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< If 1, indicates that SRC0 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC1] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< If 1, indicates that SRC1 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC2] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< If 1, indicates that SRC2 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC3] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< If 1, indicates that SRC3 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC4] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< If 1, indicates that SRC4 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC5] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< If 1, indicates that SRC5 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC6] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< If 1, indicates that SRC6 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC7] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< If 1, indicates that SRC7 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC8] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< If 1, indicates that SRC8 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC9] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< If 1, indicates that SRC9 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC10] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< If 1, indicates that SRC10 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC11] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< If 1, indicates that SRC11 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC12] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< If 1, indicates that SRC12 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC13] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< If 1, indicates that SRC13 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC14] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< If 1, indicates that SRC14 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC15] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< If 1, indicates that SRC15 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_CLR[SRC0] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC1] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC2] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC3] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC4] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC5] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC6] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC7] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC8] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC9] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC10] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC11] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC12] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC13] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC14] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC15] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_SET[SRC0] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC1] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC2] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC3] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC4] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC5] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC6] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC7] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC8] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC9] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC10] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC11] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC12] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC13] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC14] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC15] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_PSSRESET_STAT[SVSMH] Bits */ -#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /*!< SVSMH Bit Offset */ -#define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */ -/* RSTCTL_PSSRESET_STAT[BGREF] Bits */ -#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /*!< BGREF Bit Offset */ -#define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */ -/* RSTCTL_PSSRESET_STAT[VCCDET] Bits */ -#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /*!< VCCDET Bit Offset */ -#define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */ -/* RSTCTL_PSSRESET_CLR[CLR] Bits */ -#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */ -/* RSTCTL_PCMRESET_STAT[LPM35] Bits */ -#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /*!< LPM35 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */ -/* RSTCTL_PCMRESET_STAT[LPM45] Bits */ -#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /*!< LPM45 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */ -/* RSTCTL_PCMRESET_CLR[CLR] Bits */ -#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */ -/* RSTCTL_PINRESET_STAT[RSTNMI] Bits */ -#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /*!< RSTNMI Bit Offset */ -#define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /*!< POR was caused by RSTn/NMI pin based reset event */ -/* RSTCTL_PINRESET_CLR[CLR] Bits */ -#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */ -/* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /*!< Indicates if Reboot reset was caused by the SYSCTL module. */ -/* RSTCTL_REBOOTRESET_CLR[CLR] Bits */ -#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */ -/* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /*!< DCOR_SHT Bit Offset */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /*!< Indicates if POR was caused by DCO short circuit fault in the external */ - /* resistor mode */ -/* RSTCTL_CSRESET_CLR[CLR] Bits */ -#define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as */ - /* DCOR_SHTIFG flag in CSIFG register of clock system */ -/* Pre-defined bitfield values */ -#define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bits 1-0 */ - - -/****************************************************************************** -* RTC_C Bits -******************************************************************************/ -/* RTC_C_CTL0[RDYIFG] Bits */ -#define RTC_C_CTL0_RDYIFG_OFS ( 0) /*!< RTCRDYIFG Bit Offset */ -#define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /*!< Real-time clock ready interrupt flag */ -/* RTC_C_CTL0[AIFG] Bits */ -#define RTC_C_CTL0_AIFG_OFS ( 1) /*!< RTCAIFG Bit Offset */ -#define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /*!< Real-time clock alarm interrupt flag */ -/* RTC_C_CTL0[TEVIFG] Bits */ -#define RTC_C_CTL0_TEVIFG_OFS ( 2) /*!< RTCTEVIFG Bit Offset */ -#define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /*!< Real-time clock time event interrupt flag */ -/* RTC_C_CTL0[OFIFG] Bits */ -#define RTC_C_CTL0_OFIFG_OFS ( 3) /*!< RTCOFIFG Bit Offset */ -#define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /*!< 32-kHz crystal oscillator fault interrupt flag */ -/* RTC_C_CTL0[RDYIE] Bits */ -#define RTC_C_CTL0_RDYIE_OFS ( 4) /*!< RTCRDYIE Bit Offset */ -#define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /*!< Real-time clock ready interrupt enable */ -/* RTC_C_CTL0[AIE] Bits */ -#define RTC_C_CTL0_AIE_OFS ( 5) /*!< RTCAIE Bit Offset */ -#define RTC_C_CTL0_AIE ((uint16_t)0x0020) /*!< Real-time clock alarm interrupt enable */ -/* RTC_C_CTL0[TEVIE] Bits */ -#define RTC_C_CTL0_TEVIE_OFS ( 6) /*!< RTCTEVIE Bit Offset */ -#define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /*!< Real-time clock time event interrupt enable */ -/* RTC_C_CTL0[OFIE] Bits */ -#define RTC_C_CTL0_OFIE_OFS ( 7) /*!< RTCOFIE Bit Offset */ -#define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /*!< 32-kHz crystal oscillator fault interrupt enable */ -/* RTC_C_CTL0[KEY] Bits */ -#define RTC_C_CTL0_KEY_OFS ( 8) /*!< RTCKEY Bit Offset */ -#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /*!< RTCKEY Bit Mask */ -/* RTC_C_CTL13[TEV] Bits */ -#define RTC_C_CTL13_TEV_OFS ( 0) /*!< RTCTEV Bit Offset */ -#define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /*!< RTCTEV Bit Mask */ -#define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /*!< TEV Bit 0 */ -#define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /*!< TEV Bit 1 */ -#define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /*!< Minute changed */ -#define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /*!< Hour changed */ -#define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /*!< Every day at midnight (00:00) */ -#define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /*!< Every day at noon (12:00) */ -/* RTC_C_CTL13[SSEL] Bits */ -#define RTC_C_CTL13_SSEL_OFS ( 2) /*!< RTCSSEL Bit Offset */ -#define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /*!< RTCSSEL Bit Mask */ -#define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /*!< SSEL Bit 0 */ -#define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /*!< SSEL Bit 1 */ -#define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /*!< BCLK */ -#define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /*!< BCLK */ -/* RTC_C_CTL13[RDY] Bits */ -#define RTC_C_CTL13_RDY_OFS ( 4) /*!< RTCRDY Bit Offset */ -#define RTC_C_CTL13_RDY ((uint16_t)0x0010) /*!< Real-time clock ready */ -/* RTC_C_CTL13[MODE] Bits */ -#define RTC_C_CTL13_MODE_OFS ( 5) /*!< RTCMODE Bit Offset */ -#define RTC_C_CTL13_MODE ((uint16_t)0x0020) -/* RTC_C_CTL13[HOLD] Bits */ -#define RTC_C_CTL13_HOLD_OFS ( 6) /*!< RTCHOLD Bit Offset */ -#define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /*!< Real-time clock hold */ -/* RTC_C_CTL13[BCD] Bits */ -#define RTC_C_CTL13_BCD_OFS ( 7) /*!< RTCBCD Bit Offset */ -#define RTC_C_CTL13_BCD ((uint16_t)0x0080) /*!< Real-time clock BCD select */ -/* RTC_C_CTL13[CALF] Bits */ -#define RTC_C_CTL13_CALF_OFS ( 8) /*!< RTCCALF Bit Offset */ -#define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /*!< RTCCALF Bit Mask */ -#define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /*!< CALF Bit 0 */ -#define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /*!< CALF Bit 1 */ -#define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /*!< 1 Hz */ -#define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /*!< 1 Hz */ -/* RTC_C_OCAL[OCAL] Bits */ -#define RTC_C_OCAL_OCAL_OFS ( 0) /*!< RTCOCAL Bit Offset */ -#define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /*!< RTCOCAL Bit Mask */ -/* RTC_C_OCAL[OCALS] Bits */ -#define RTC_C_OCAL_OCALS_OFS (15) /*!< RTCOCALS Bit Offset */ -#define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /*!< Real-time clock offset error calibration sign */ -/* RTC_C_TCMP[TCMPx] Bits */ -#define RTC_C_TCMP_TCMPX_OFS ( 0) /*!< RTCTCMP Bit Offset */ -#define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /*!< RTCTCMP Bit Mask */ -/* RTC_C_TCMP[TCOK] Bits */ -#define RTC_C_TCMP_TCOK_OFS (13) /*!< RTCTCOK Bit Offset */ -#define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /*!< Real-time clock temperature compensation write OK */ -/* RTC_C_TCMP[TCRDY] Bits */ -#define RTC_C_TCMP_TCRDY_OFS (14) /*!< RTCTCRDY Bit Offset */ -#define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /*!< Real-time clock temperature compensation ready */ -/* RTC_C_TCMP[TCMPS] Bits */ -#define RTC_C_TCMP_TCMPS_OFS (15) /*!< RTCTCMPS Bit Offset */ -#define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /*!< Real-time clock temperature compensation sign */ -/* RTC_C_PS0CTL[RT0PSIFG] Bits */ -#define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /*!< RT0PSIFG Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /*!< Prescale timer 0 interrupt flag */ -/* RTC_C_PS0CTL[RT0PSIE] Bits */ -#define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /*!< RT0PSIE Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /*!< Prescale timer 0 interrupt enable */ -/* RTC_C_PS0CTL[RT0IP] Bits */ -#define RTC_C_PS0CTL_RT0IP_OFS ( 2) /*!< RT0IP Bit Offset */ -#define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /*!< RT0IP Bit Mask */ -#define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /*!< RT0IP Bit 0 */ -#define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /*!< RT0IP Bit 1 */ -#define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /*!< RT0IP Bit 2 */ -#define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -/* RTC_C_PS1CTL[RT1PSIFG] Bits */ -#define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /*!< RT1PSIFG Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /*!< Prescale timer 1 interrupt flag */ -/* RTC_C_PS1CTL[RT1PSIE] Bits */ -#define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /*!< RT1PSIE Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /*!< Prescale timer 1 interrupt enable */ -/* RTC_C_PS1CTL[RT1IP] Bits */ -#define RTC_C_PS1CTL_RT1IP_OFS ( 2) /*!< RT1IP Bit Offset */ -#define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /*!< RT1IP Bit Mask */ -#define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /*!< RT1IP Bit 0 */ -#define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /*!< RT1IP Bit 1 */ -#define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /*!< RT1IP Bit 2 */ -#define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -/* RTC_C_PS[RT0PS] Bits */ -#define RTC_C_PS_RT0PS_OFS ( 0) /*!< RT0PS Bit Offset */ -#define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /*!< RT0PS Bit Mask */ -/* RTC_C_PS[RT1PS] Bits */ -#define RTC_C_PS_RT1PS_OFS ( 8) /*!< RT1PS Bit Offset */ -#define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /*!< RT1PS Bit Mask */ -/* RTC_C_TIM0[SEC] Bits */ -#define RTC_C_TIM0_SEC_OFS ( 0) /*!< Seconds Bit Offset */ -#define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /*!< Seconds Bit Mask */ -/* RTC_C_TIM0[MIN] Bits */ -#define RTC_C_TIM0_MIN_OFS ( 8) /*!< Minutes Bit Offset */ -#define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /*!< Minutes Bit Mask */ -/* RTC_C_TIM0[SEC_LD] Bits */ -#define RTC_C_TIM0_SEC_LD_OFS ( 0) /*!< SecondsLowDigit Bit Offset */ -#define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /*!< SecondsLowDigit Bit Mask */ -/* RTC_C_TIM0[SEC_HD] Bits */ -#define RTC_C_TIM0_SEC_HD_OFS ( 4) /*!< SecondsHighDigit Bit Offset */ -#define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /*!< SecondsHighDigit Bit Mask */ -/* RTC_C_TIM0[MIN_LD] Bits */ -#define RTC_C_TIM0_MIN_LD_OFS ( 8) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /*!< MinutesLowDigit Bit Mask */ -/* RTC_C_TIM0[MIN_HD] Bits */ -#define RTC_C_TIM0_MIN_HD_OFS (12) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /*!< MinutesHighDigit Bit Mask */ -/* RTC_C_TIM1[HOUR] Bits */ -#define RTC_C_TIM1_HOUR_OFS ( 0) /*!< Hours Bit Offset */ -#define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /*!< Hours Bit Mask */ -/* RTC_C_TIM1[DOW] Bits */ -#define RTC_C_TIM1_DOW_OFS ( 8) /*!< DayofWeek Bit Offset */ -#define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /*!< DayofWeek Bit Mask */ -/* RTC_C_TIM1[HOUR_LD] Bits */ -#define RTC_C_TIM1_HOUR_LD_OFS ( 0) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /*!< HoursLowDigit Bit Mask */ -/* RTC_C_TIM1[HOUR_HD] Bits */ -#define RTC_C_TIM1_HOUR_HD_OFS ( 4) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /*!< HoursHighDigit Bit Mask */ -/* RTC_C_DATE[DAY] Bits */ -#define RTC_C_DATE_DAY_OFS ( 0) /*!< Day Bit Offset */ -#define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /*!< Day Bit Mask */ -/* RTC_C_DATE[MON] Bits */ -#define RTC_C_DATE_MON_OFS ( 8) /*!< Month Bit Offset */ -#define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /*!< Month Bit Mask */ -/* RTC_C_DATE[DAY_LD] Bits */ -#define RTC_C_DATE_DAY_LD_OFS ( 0) /*!< DayLowDigit Bit Offset */ -#define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /*!< DayLowDigit Bit Mask */ -/* RTC_C_DATE[DAY_HD] Bits */ -#define RTC_C_DATE_DAY_HD_OFS ( 4) /*!< DayHighDigit Bit Offset */ -#define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /*!< DayHighDigit Bit Mask */ -/* RTC_C_DATE[MON_LD] Bits */ -#define RTC_C_DATE_MON_LD_OFS ( 8) /*!< MonthLowDigit Bit Offset */ -#define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /*!< MonthLowDigit Bit Mask */ -/* RTC_C_DATE[MON_HD] Bits */ -#define RTC_C_DATE_MON_HD_OFS (12) /*!< MonthHighDigit Bit Offset */ -#define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /*!< Month high digit (0 or 1) */ -/* RTC_C_YEAR[YEAR_LB] Bits */ -#define RTC_C_YEAR_YEAR_LB_OFS ( 0) /*!< YearLowByte Bit Offset */ -#define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /*!< YearLowByte Bit Mask */ -/* RTC_C_YEAR[YEAR_HB] Bits */ -#define RTC_C_YEAR_YEAR_HB_OFS ( 8) /*!< YearHighByte Bit Offset */ -#define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /*!< YearHighByte Bit Mask */ -/* RTC_C_YEAR[YEAR] Bits */ -#define RTC_C_YEAR_YEAR_OFS ( 0) /*!< Year Bit Offset */ -#define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /*!< Year Bit Mask */ -/* RTC_C_YEAR[DEC] Bits */ -#define RTC_C_YEAR_DEC_OFS ( 4) /*!< Decade Bit Offset */ -#define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /*!< Decade Bit Mask */ -/* RTC_C_YEAR[CENT_LD] Bits */ -#define RTC_C_YEAR_CENT_LD_OFS ( 8) /*!< CenturyLowDigit Bit Offset */ -#define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /*!< CenturyLowDigit Bit Mask */ -/* RTC_C_YEAR[CENT_HD] Bits */ -#define RTC_C_YEAR_CENT_HD_OFS (12) /*!< CenturyHighDigit Bit Offset */ -#define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /*!< CenturyHighDigit Bit Mask */ -/* RTC_C_AMINHR[MIN] Bits */ -#define RTC_C_AMINHR_MIN_OFS ( 0) /*!< Minutes Bit Offset */ -#define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /*!< Minutes Bit Mask */ -/* RTC_C_AMINHR[MINAE] Bits */ -#define RTC_C_AMINHR_MINAE_OFS ( 7) /*!< MINAE Bit Offset */ -#define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /*!< Alarm enable */ -/* RTC_C_AMINHR[HOUR] Bits */ -#define RTC_C_AMINHR_HOUR_OFS ( 8) /*!< Hours Bit Offset */ -#define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /*!< Hours Bit Mask */ -/* RTC_C_AMINHR[HOURAE] Bits */ -#define RTC_C_AMINHR_HOURAE_OFS (15) /*!< HOURAE Bit Offset */ -#define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /*!< Alarm enable */ -/* RTC_C_AMINHR[MIN_LD] Bits */ -#define RTC_C_AMINHR_MIN_LD_OFS ( 0) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /*!< MinutesLowDigit Bit Mask */ -/* RTC_C_AMINHR[MIN_HD] Bits */ -#define RTC_C_AMINHR_MIN_HD_OFS ( 4) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /*!< MinutesHighDigit Bit Mask */ -/* RTC_C_AMINHR[HOUR_LD] Bits */ -#define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /*!< HoursLowDigit Bit Mask */ -/* RTC_C_AMINHR[HOUR_HD] Bits */ -#define RTC_C_AMINHR_HOUR_HD_OFS (12) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /*!< HoursHighDigit Bit Mask */ -/* RTC_C_ADOWDAY[DOW] Bits */ -#define RTC_C_ADOWDAY_DOW_OFS ( 0) /*!< DayofWeek Bit Offset */ -#define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /*!< DayofWeek Bit Mask */ -/* RTC_C_ADOWDAY[DOWAE] Bits */ -#define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /*!< DOWAE Bit Offset */ -#define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /*!< Alarm enable */ -/* RTC_C_ADOWDAY[DAY] Bits */ -#define RTC_C_ADOWDAY_DAY_OFS ( 8) /*!< DayofMonth Bit Offset */ -#define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /*!< DayofMonth Bit Mask */ -/* RTC_C_ADOWDAY[DAYAE] Bits */ -#define RTC_C_ADOWDAY_DAYAE_OFS (15) /*!< DAYAE Bit Offset */ -#define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /*!< Alarm enable */ -/* RTC_C_ADOWDAY[DAY_LD] Bits */ -#define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /*!< DayLowDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /*!< DayLowDigit Bit Mask */ -/* RTC_C_ADOWDAY[DAY_HD] Bits */ -#define RTC_C_ADOWDAY_DAY_HD_OFS (12) /*!< DayHighDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /*!< DayHighDigit Bit Mask */ -/* Pre-defined bitfield values */ -#define RTC_C_KEY ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_H ((uint16_t)0x00A5) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_VAL ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ - - -/****************************************************************************** -* SCB Bits -******************************************************************************/ -/* SCB_PFR0[STATE0] Bits */ -#define SCB_PFR0_STATE0_OFS ( 0) /*!< STATE0 Bit Offset */ -#define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /*!< STATE0 Bit Mask */ -#define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /*!< STATE0 Bit 0 */ -#define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /*!< STATE0 Bit 1 */ -#define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /*!< STATE0 Bit 2 */ -#define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /*!< STATE0 Bit 3 */ -#define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /*!< no ARM encoding */ -#define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /*!< N/A */ -/* SCB_PFR0[STATE1] Bits */ -#define SCB_PFR0_STATE1_OFS ( 4) /*!< STATE1 Bit Offset */ -#define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /*!< STATE1 Bit Mask */ -#define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /*!< STATE1 Bit 0 */ -#define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /*!< STATE1 Bit 1 */ -#define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /*!< STATE1 Bit 2 */ -#define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /*!< STATE1 Bit 3 */ -#define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /*!< N/A */ -#define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /*!< N/A */ -#define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL */ - /* but no other 32-bit basic instructions (Note non-basic 32-bit instructions */ - /* can be added using the appropriate instruction attribute, but other 32-bit */ - /* basic instructions cannot.) */ -#define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /*!< Thumb-2 encoding with all Thumb-2 basic instructions */ -/* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /*!< two-stack support */ -/* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */ -/* SCB_MMFR0[PMSA_SUPPORT] Bits */ -#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /*!< PMSA_SUPPORT Bit Offset */ -#define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /*!< PMSA_SUPPORT Bit Mask */ -#define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /*!< PMSA_SUPPORT Bit 0 */ -#define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /*!< PMSA_SUPPORT Bit 1 */ -#define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /*!< PMSA_SUPPORT Bit 2 */ -#define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /*!< PMSA_SUPPORT Bit 3 */ -#define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /*!< IMPLEMENTATION DEFINED (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /*!< PMSA base (features as defined for ARMv6) (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /*!< PMSAv7 (base plus subregion support) */ -/* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /*!< CACHE_COHERENCE_SUPPORT Bit Offset */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /*!< CACHE_COHERENCE_SUPPORT Bit Mask */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /*!< CACHE_COHERENCE_SUPPORT Bit 0 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /*!< CACHE_COHERENCE_SUPPORT Bit 1 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /*!< CACHE_COHERENCE_SUPPORT Bit 2 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /*!< CACHE_COHERENCE_SUPPORT Bit 3 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /*!< no shared support */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /*!< partial-inner-shared coherency (coherency amongst some - but not all - of */ - /* the entities within an inner-coherent domain) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /*!< full-inner-shared coherency (coherency amongst all of the entities within an */ - /* inner-coherent domain) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /*!< full coherency (coherency amongst all of the entities) */ -/* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /*!< Outer non-sharable not supported */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /*!< Outer sharable supported */ -/* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /*!< Auxiliary control register */ -/* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /*!< wait for interrupt supported */ -/* SCB_ISAR0[BITCOUNT_INSTRS] Bits */ -#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /*!< BITCOUNT_INSTRS Bit Offset */ -#define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< BITCOUNT_INSTRS Bit Mask */ -#define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /*!< BITCOUNT_INSTRS Bit 0 */ -#define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /*!< BITCOUNT_INSTRS Bit 1 */ -#define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /*!< BITCOUNT_INSTRS Bit 2 */ -#define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /*!< BITCOUNT_INSTRS Bit 3 */ -#define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /*!< no bit-counting instructions present */ -#define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds CLZ */ -/* SCB_ISAR0[BITFIELD_INSTRS] Bits */ -#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /*!< BITFIELD_INSTRS Bit Offset */ -#define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /*!< BITFIELD_INSTRS Bit Mask */ -#define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /*!< BITFIELD_INSTRS Bit 0 */ -#define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /*!< BITFIELD_INSTRS Bit 1 */ -#define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /*!< BITFIELD_INSTRS Bit 2 */ -#define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /*!< BITFIELD_INSTRS Bit 3 */ -#define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /*!< no bitfield instructions present */ -#define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /*!< adds BFC, BFI, SBFX, UBFX */ -/* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /*!< CMPBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /*!< CMPBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /*!< CMPBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /*!< CMPBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /*!< CMPBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /*!< CMPBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no combined compare-and-branch instructions present */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /*!< adds CB{N}Z */ -/* SCB_ISAR0[COPROC_INSTRS] Bits */ -#define SCB_ISAR0_COPROC_INSTRS_OFS (16) /*!< COPROC_INSTRS Bit Offset */ -#define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /*!< COPROC_INSTRS Bit Mask */ -#define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /*!< COPROC_INSTRS Bit 0 */ -#define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /*!< COPROC_INSTRS Bit 1 */ -#define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /*!< COPROC_INSTRS Bit 2 */ -#define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /*!< COPROC_INSTRS Bit 3 */ -#define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /*!< no coprocessor support, other than for separately attributed architectures */ - /* such as CP15 or VFP */ -#define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /*!< adds generic CDP, LDC, MCR, MRC, STC */ -#define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */ -#define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /*!< adds generic MCRR, MRRC */ -#define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /*!< adds generic MCRR2, MRRC2 */ -/* SCB_ISAR0[DEBUG_INSTRS] Bits */ -#define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /*!< DEBUG_INSTRS Bit Offset */ -#define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /*!< DEBUG_INSTRS Bit Mask */ -#define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /*!< DEBUG_INSTRS Bit 0 */ -#define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /*!< DEBUG_INSTRS Bit 1 */ -#define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /*!< DEBUG_INSTRS Bit 2 */ -#define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /*!< DEBUG_INSTRS Bit 3 */ -#define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /*!< no debug instructions present */ -#define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /*!< adds BKPT */ -/* SCB_ISAR0[DIVIDE_INSTRS] Bits */ -#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /*!< DIVIDE_INSTRS Bit Offset */ -#define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /*!< DIVIDE_INSTRS Bit Mask */ -#define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /*!< DIVIDE_INSTRS Bit 0 */ -#define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /*!< DIVIDE_INSTRS Bit 1 */ -#define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /*!< DIVIDE_INSTRS Bit 2 */ -#define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /*!< DIVIDE_INSTRS Bit 3 */ -#define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /*!< no divide instructions present */ -#define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /*!< adds SDIV, UDIV (v1 quotient only result) */ -/* SCB_ISAR1[ETEND_INSRS] Bits */ -#define SCB_ISAR1_ETEND_INSRS_OFS (12) /*!< EXTEND_INSRS Bit Offset */ -#define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /*!< EXTEND_INSRS Bit Mask */ -#define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /*!< ETEND_INSRS Bit 0 */ -#define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /*!< ETEND_INSRS Bit 1 */ -#define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /*!< ETEND_INSRS Bit 2 */ -#define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /*!< ETEND_INSRS Bit 3 */ -#define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */ -#define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /*!< adds SXTB, SXTH, UXTB, UXTH */ -#define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /*!< N/A */ -/* SCB_ISAR1[IFTHEN_INSTRS] Bits */ -#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /*!< IFTHEN_INSTRS Bit Offset */ -#define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /*!< IFTHEN_INSTRS Bit Mask */ -#define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /*!< IFTHEN_INSTRS Bit 0 */ -#define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /*!< IFTHEN_INSTRS Bit 1 */ -#define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /*!< IFTHEN_INSTRS Bit 2 */ -#define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /*!< IFTHEN_INSTRS Bit 3 */ -#define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /*!< IT instructions not present */ -#define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /*!< adds IT instructions (and IT bits in PSRs) */ -/* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /*!< IMMEDIATE_INSTRS Bit Offset */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /*!< IMMEDIATE_INSTRS Bit Mask */ -#define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /*!< IMMEDIATE_INSTRS Bit 0 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /*!< IMMEDIATE_INSTRS Bit 1 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /*!< IMMEDIATE_INSTRS Bit 2 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /*!< IMMEDIATE_INSTRS Bit 3 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no special immediate-generating instructions present */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /*!< adds ADDW, MOVW, MOVT, SUBW */ -/* SCB_ISAR1[INTERWORK_INSTRS] Bits */ -#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /*!< INTERWORK_INSTRS Bit Offset */ -#define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /*!< INTERWORK_INSTRS Bit Mask */ -#define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /*!< INTERWORK_INSTRS Bit 0 */ -#define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /*!< INTERWORK_INSTRS Bit 1 */ -#define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /*!< INTERWORK_INSTRS Bit 2 */ -#define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /*!< INTERWORK_INSTRS Bit 3 */ -#define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /*!< no interworking instructions supported */ -#define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /*!< adds BX (and T bit in PSRs) */ -#define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /*!< adds BLX, and PC loads have BX-like behavior */ -#define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /*!< N/A */ -/* SCB_ISAR2[LOADSTORE_INSTRS] Bits */ -#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /*!< LOADSTORE_INSTRS Bit Offset */ -#define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< LOADSTORE_INSTRS Bit Mask */ -#define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /*!< LOADSTORE_INSTRS Bit 0 */ -#define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /*!< LOADSTORE_INSTRS Bit 1 */ -#define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /*!< LOADSTORE_INSTRS Bit 2 */ -#define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /*!< LOADSTORE_INSTRS Bit 3 */ -#define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /*!< no additional normal load/store instructions present */ -#define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRD/STRD */ -/* SCB_ISAR2[MEMHINT_INSTRS] Bits */ -#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /*!< MEMHINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< MEMHINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /*!< MEMHINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /*!< MEMHINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /*!< MEMHINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /*!< MEMHINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /*!< no memory hint instructions presen */ -#define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds PLD */ -#define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /*!< adds PLD (ie a repeat on value 1) */ -#define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /*!< adds PLI */ -/* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /*!< MULTIACCESSINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /*!< MULTIACCESSINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /*!< MULTIACCESSINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /*!< MULTIACCESSINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /*!< MULTIACCESSINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /*!< MULTIACCESSINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /*!< the (LDM/STM) instructions are non-interruptible */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /*!< the (LDM/STM) instructions are restartable */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /*!< the (LDM/STM) instructions are continuable */ -/* SCB_ISAR2[MULT_INSTRS] Bits */ -#define SCB_ISAR2_MULT_INSTRS_OFS (12) /*!< MULT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /*!< MULT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /*!< MULT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /*!< MULT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /*!< MULT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /*!< MULT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /*!< only MUL present */ -#define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /*!< adds MLA */ -#define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /*!< adds MLS */ -/* SCB_ISAR2[MULTS_INSTRS] Bits */ -#define SCB_ISAR2_MULTS_INSTRS_OFS (16) /*!< MULTS_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /*!< MULTS_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /*!< MULTS_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /*!< MULTS_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /*!< MULTS_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /*!< MULTS_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /*!< no signed multiply instructions present */ -#define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /*!< adds SMULL, SMLAL */ -#define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /*!< N/A */ -#define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /*!< N/A */ -/* SCB_ISAR2[MULTU_INSTRS] Bits */ -#define SCB_ISAR2_MULTU_INSTRS_OFS (20) /*!< MULTU_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /*!< MULTU_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /*!< MULTU_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /*!< MULTU_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /*!< MULTU_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /*!< MULTU_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /*!< no unsigned multiply instructions present */ -#define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /*!< adds UMULL, UMLAL */ -#define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /*!< N/A */ -/* SCB_ISAR2[REVERSAL_INSTRS] Bits */ -#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /*!< REVERSAL_INSTRS Bit Offset */ -#define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /*!< REVERSAL_INSTRS Bit Mask */ -#define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /*!< REVERSAL_INSTRS Bit 0 */ -#define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /*!< REVERSAL_INSTRS Bit 1 */ -#define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /*!< REVERSAL_INSTRS Bit 2 */ -#define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /*!< REVERSAL_INSTRS Bit 3 */ -#define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /*!< no reversal instructions present */ -#define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /*!< adds REV, REV16, REVSH */ -#define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /*!< adds RBIT */ -/* SCB_ISAR3[SATRUATE_INSTRS] Bits */ -#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /*!< SATRUATE_INSTRS Bit Offset */ -#define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< SATRUATE_INSTRS Bit Mask */ -#define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /*!< SATRUATE_INSTRS Bit 0 */ -#define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /*!< SATRUATE_INSTRS Bit 1 */ -#define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /*!< SATRUATE_INSTRS Bit 2 */ -#define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /*!< SATRUATE_INSTRS Bit 3 */ -#define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no non-SIMD saturate instructions present */ -#define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /*!< N/A */ -/* SCB_ISAR3[SIMD_INSTRS] Bits */ -#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /*!< SIMD_INSTRS Bit Offset */ -#define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /*!< SIMD_INSTRS Bit Mask */ -#define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /*!< SIMD_INSTRS Bit 0 */ -#define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /*!< SIMD_INSTRS Bit 1 */ -#define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /*!< SIMD_INSTRS Bit 2 */ -#define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /*!< SIMD_INSTRS Bit 3 */ -#define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /*!< no SIMD instructions present */ -#define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /*!< adds SSAT, USAT (and the Q flag in the PSRs) */ -#define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /*!< N/A */ -/* SCB_ISAR3[SVC_INSTRS] Bits */ -#define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /*!< SVC_INSTRS Bit Offset */ -#define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /*!< SVC_INSTRS Bit Mask */ -#define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /*!< SVC_INSTRS Bit 0 */ -#define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /*!< SVC_INSTRS Bit 1 */ -#define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /*!< SVC_INSTRS Bit 2 */ -#define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /*!< SVC_INSTRS Bit 3 */ -#define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /*!< no SVC (SWI) instructions present */ -#define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /*!< adds SVC (SWI) */ -/* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /*!< SYNCPRIM_INSTRS Bit Offset */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /*!< SYNCPRIM_INSTRS Bit Mask */ -#define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /*!< SYNCPRIM_INSTRS Bit 0 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /*!< SYNCPRIM_INSTRS Bit 1 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /*!< SYNCPRIM_INSTRS Bit 2 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /*!< SYNCPRIM_INSTRS Bit 3 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /*!< no synchronization primitives present */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /*!< adds LDREX, STREX */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */ -/* SCB_ISAR3[TABBRANCH_INSTRS] Bits */ -#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /*!< TABBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /*!< TABBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /*!< TABBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /*!< TABBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /*!< TABBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /*!< TABBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no table-branch instructions present */ -#define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /*!< adds TBB, TBH */ -/* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /*!< THUMBCOPY_INSTRS Bit Offset */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /*!< THUMBCOPY_INSTRS Bit Mask */ -#define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /*!< THUMBCOPY_INSTRS Bit 0 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /*!< THUMBCOPY_INSTRS Bit 1 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /*!< THUMBCOPY_INSTRS Bit 2 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /*!< THUMBCOPY_INSTRS Bit 3 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */ -/* SCB_ISAR3[TRUENOP_INSTRS] Bits */ -#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /*!< TRUENOP_INSTRS Bit Offset */ -#define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /*!< TRUENOP_INSTRS Bit Mask */ -#define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /*!< TRUENOP_INSTRS Bit 0 */ -#define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /*!< TRUENOP_INSTRS Bit 1 */ -#define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /*!< TRUENOP_INSTRS Bit 2 */ -#define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /*!< TRUENOP_INSTRS Bit 3 */ -#define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /*!< true NOP instructions not present - that is, NOP instructions with no */ - /* register dependencies */ -#define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */ -/* SCB_ISAR4[UNPRIV_INSTRS] Bits */ -#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /*!< UNPRIV_INSTRS Bit Offset */ -#define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /*!< UNPRIV_INSTRS Bit Mask */ -#define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /*!< UNPRIV_INSTRS Bit 0 */ -#define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /*!< UNPRIV_INSTRS Bit 1 */ -#define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /*!< UNPRIV_INSTRS Bit 2 */ -#define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /*!< UNPRIV_INSTRS Bit 3 */ -#define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /*!< no "T variant" instructions exist */ -#define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRBT, LDRT, STRBT, STRT */ -#define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */ -/* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /*!< WITHSHIFTS_INSTRS Bit Offset */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /*!< WITHSHIFTS_INSTRS Bit Mask */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /*!< WITHSHIFTS_INSTRS Bit 0 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /*!< WITHSHIFTS_INSTRS Bit 1 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /*!< WITHSHIFTS_INSTRS Bit 2 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /*!< WITHSHIFTS_INSTRS Bit 3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /*!< non-zero shifts only support MOV and shift instructions (see notes) */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /*!< shifts of loads/stores over the range LSL 0-3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /*!< adds other constant shift options. */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /*!< adds register-controlled shift options. */ -/* SCB_ISAR4[WRITEBACK_INSTRS] Bits */ -#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /*!< WRITEBACK_INSTRS Bit Offset */ -#define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /*!< WRITEBACK_INSTRS Bit Mask */ -#define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /*!< WRITEBACK_INSTRS Bit 0 */ -#define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /*!< WRITEBACK_INSTRS Bit 1 */ -#define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /*!< WRITEBACK_INSTRS Bit 2 */ -#define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /*!< WRITEBACK_INSTRS Bit 3 */ -#define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /*!< only non-writeback addressing modes present, except that */ - /* LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */ -#define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */ -/* SCB_ISAR4[BARRIER_INSTRS] Bits */ -#define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /*!< BARRIER_INSTRS Bit Offset */ -#define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /*!< BARRIER_INSTRS Bit Mask */ -#define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /*!< BARRIER_INSTRS Bit 0 */ -#define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /*!< BARRIER_INSTRS Bit 1 */ -#define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /*!< BARRIER_INSTRS Bit 2 */ -#define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /*!< BARRIER_INSTRS Bit 3 */ -#define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /*!< no barrier instructions supported */ -#define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /*!< adds DMB, DSB, ISB barrier instructions */ -/* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /*!< no additional support */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */ -/* SCB_ISAR4[PSR_M_INSTRS] Bits */ -#define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /*!< PSR_M_INSTRS Bit Offset */ -#define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /*!< PSR_M_INSTRS Bit Mask */ -#define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /*!< PSR_M_INSTRS Bit 0 */ -#define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /*!< PSR_M_INSTRS Bit 1 */ -#define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /*!< PSR_M_INSTRS Bit 2 */ -#define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /*!< PSR_M_INSTRS Bit 3 */ -#define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /*!< instructions not present */ -#define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */ -/* SCB_CPACR[CP11] Bits */ -#define SCB_CPACR_CP11_OFS (22) /*!< CP11 Bit Offset */ -#define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /*!< CP11 Bit Mask */ -/* SCB_CPACR[CP10] Bits */ -#define SCB_CPACR_CP10_OFS (20) /*!< CP10 Bit Offset */ -#define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /*!< CP10 Bit Mask */ -/* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */ -#define SCB_SHPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define SCB_SHPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */ -#define SCB_SHPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define SCB_SHPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */ -#define SCB_SHPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define SCB_SHPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */ -#define SCB_SHPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define SCB_SHPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */ -#define SCB_SHPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define SCB_SHPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */ -#define SCB_SHPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define SCB_SHPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */ -#define SCB_SHPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define SCB_SHPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */ -#define SCB_SHPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define SCB_SHPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */ -#define SCB_SHPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define SCB_SHPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */ -#define SCB_SHPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define SCB_SHPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */ -#define SCB_SHPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define SCB_SHPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */ -#define SCB_SHPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define SCB_SHPR3_PRI_15_M ((uint32_t)0xff000000) /* */ - -/* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */ -#define SCB_CFSR_IACCVIOL_OFS ( 0) /*!< IACCVIOL Offset */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /* */ -/* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */ -#define SCB_CFSR_DACCVIOL_OFS ( 1) /*!< DACCVIOL Offset */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /* */ -/* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */ -#define SCB_CFSR_MUNSTKERR_OFS ( 3) /*!< MUNSTKERR Offset */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /* */ -/* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */ -#define SCB_CFSR_MSTKERR_OFS ( 4) /*!< MSTKERR Offset */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /* */ -/* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */ -#define SCB_CFSR_MMARVALID_OFS ( 7) /*!< MMARVALID Offset */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /* */ -/* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */ -#define SCB_CFSR_IBUSERR_OFS ( 8) /*!< IBUSERR Offset */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /* */ -/* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */ -#define SCB_CFSR_PRECISERR_OFS ( 9) /*!< PRECISERR Offset */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /* */ -/* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */ -#define SCB_CFSR_IMPRECISERR_OFS (10) /*!< IMPRECISERR Offset */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /* */ -/* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */ -#define SCB_CFSR_UNSTKERR_OFS (11) /*!< UNSTKERR Offset */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /* */ -/* SCB_CFSR[SCB_CFSR_STKERR] Bits */ -#define SCB_CFSR_STKERR_OFS (12) /*!< STKERR Offset */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /* */ -/* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */ -#define SCB_CFSR_BFARVALID_OFS (15) /*!< BFARVALID Offset */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /* */ -/* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */ -#define SCB_CFSR_UNDEFINSTR_OFS (16) /*!< UNDEFINSTR Offset */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /* */ -/* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */ -#define SCB_CFSR_INVSTATE_OFS (17) /*!< INVSTATE Offset */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /* */ -/* SCB_CFSR[SCB_CFSR_INVPC] Bits */ -#define SCB_CFSR_INVPC_OFS (18) /*!< INVPC Offset */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /* */ -/* SCB_CFSR[SCB_CFSR_NOCP] Bits */ -#define SCB_CFSR_NOCP_OFS (19) /*!< NOCP Offset */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /* */ -/* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */ -#define SCB_CFSR_UNALIGNED_OFS (24) /*!< UNALIGNED Offset */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /* */ -/* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */ -#define SCB_CFSR_DIVBYZERO_OFS (25) /*!< DIVBYZERO Offset */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /* */ -/* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */ -#define SCB_CFSR_MLSPERR_OFS ( 5) /*!< MLSPERR Offset */ -#define SCB_CFSR_MLSPERR ((uint32_t)0x00000020) /* */ -/* SCB_CFSR[SCB_CFSR_LSPERR] Bits */ -#define SCB_CFSR_LSPERR_OFS (13) /*!< LSPERR Offset */ -#define SCB_CFSR_LSPERR ((uint32_t)0x00002000) /* */ - - -/****************************************************************************** -* SCNSCB Bits -******************************************************************************/ - - -/****************************************************************************** -* SYSCTL_A Bits -******************************************************************************/ -/* SYSCTL_A_REBOOT_CTL[REBOOT] Bits */ -#define SYSCTL_A_REBOOT_CTL_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define SYSCTL_A_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /*!< Write 1 initiates a Reboot of the device */ -/* SYSCTL_A_REBOOT_CTL[WKEY] Bits */ -#define SYSCTL_A_REBOOT_CTL_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_A_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -/* SYSCTL_A_NMI_CTLSTAT[CS_SRC] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_CS_SRC_OFS ( 0) /*!< CS_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /*!< CS interrupt as a source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PSS_SRC] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /*!< PSS_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /*!< PSS interrupt as a source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PCM_SRC] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /*!< PCM_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /*!< PCM interrupt as a source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PIN_SRC] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /*!< PIN_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008) -/* SYSCTL_A_NMI_CTLSTAT[CS_FLG] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_CS_FLG_OFS (16) /*!< CS_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /*!< CS interrupt was the source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PSS_FLG] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_FLG_OFS (17) /*!< PSS_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /*!< PSS interrupt was the source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PCM_FLG] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_FLG_OFS (18) /*!< PCM_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /*!< PCM interrupt was the source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PIN_FLG] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_FLG_OFS (19) /*!< PIN_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /*!< RSTn/NMI pin was the source of NMI */ -/* SYSCTL_A_WDTRESET_CTL[TIMEOUT] Bits */ -#define SYSCTL_A_WDTRESET_CTL_TIMEOUT_OFS ( 0) /*!< TIMEOUT Bit Offset */ -#define SYSCTL_A_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /*!< WDT timeout reset type */ -/* SYSCTL_A_WDTRESET_CTL[VIOLATION] Bits */ -#define SYSCTL_A_WDTRESET_CTL_VIOLATION_OFS ( 1) /*!< VIOLATION Bit Offset */ -#define SYSCTL_A_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /*!< WDT password violation reset type */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T16_0] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /*!< HALT_T16_0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T16_1] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /*!< HALT_T16_1 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T16_2] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /*!< HALT_T16_2 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T16_3] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /*!< HALT_T16_3 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T32_0] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /*!< HALT_T32_0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUA0] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /*!< HALT_eUA0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUA1] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /*!< HALT_eUA1 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUA2] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /*!< HALT_eUA2 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUA3] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /*!< HALT_eUA3 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUB0] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /*!< HALT_eUB0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUB1] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB1_OFS (10) /*!< HALT_eUB1 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUB2] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB2_OFS (11) /*!< HALT_eUB2 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUB3] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB3_OFS (12) /*!< HALT_eUB3 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_ADC] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_ADC_OFS (13) /*!< HALT_ADC Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_WDT] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_WDT_OFS (14) /*!< HALT_WDT Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_DMA] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_DMA_OFS (15) /*!< HALT_DMA Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_LCD] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_LCD_OFS (16) /*!< HALT_LCD Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_LCD ((uint32_t)0x00010000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_DIO_GLTFLT_CTL[GLTCH_EN] Bits */ -#define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /*!< GLTCH_EN Bit Offset */ -#define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /*!< Glitch filter enable */ -/* SYSCTL_A_SECDATA_UNLOCK[UNLKEY] Bits */ -#define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK0_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN_OFS ( 0) /*!< BNK0_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank0 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK1_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN_OFS ( 1) /*!< BNK1_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank1 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK2_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN_OFS ( 2) /*!< BNK2_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank2 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK3_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN_OFS ( 3) /*!< BNK3_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank3 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK4_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN_OFS ( 4) /*!< BNK4_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank4 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK5_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN_OFS ( 5) /*!< BNK5_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank5 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK6_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN_OFS ( 6) /*!< BNK6_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank6 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK7_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN_OFS ( 7) /*!< BNK7_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank7 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK8_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN_OFS ( 8) /*!< BNK8_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank8 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK9_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN_OFS ( 9) /*!< BNK9_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank9 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK10_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN_OFS (10) /*!< BNK10_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank10 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK11_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN_OFS (11) /*!< BNK11_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank11 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK12_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN_OFS (12) /*!< BNK12_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank12 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK13_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN_OFS (13) /*!< BNK13_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank13 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK14_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN_OFS (14) /*!< BNK14_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank14 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK15_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN_OFS (15) /*!< BNK15_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank15 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK16_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN_OFS (16) /*!< BNK16_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank16 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK17_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN_OFS (17) /*!< BNK17_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank17 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK18_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN_OFS (18) /*!< BNK18_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank18 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK19_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN_OFS (19) /*!< BNK19_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank19 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK20_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN_OFS (20) /*!< BNK20_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank20 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK21_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN_OFS (21) /*!< BNK21_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank21 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK22_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN_OFS (22) /*!< BNK22_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank22 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK23_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN_OFS (23) /*!< BNK23_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank23 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK24_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN_OFS (24) /*!< BNK24_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank24 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK25_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN_OFS (25) /*!< BNK25_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank25 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK26_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN_OFS (26) /*!< BNK26_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank26 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK27_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN_OFS (27) /*!< BNK27_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank27 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK28_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN_OFS (28) /*!< BNK28_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank28 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK29_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN_OFS (29) /*!< BNK29_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank29 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK30_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN_OFS (30) /*!< BNK30_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank30 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK31_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN_OFS (31) /*!< BNK31_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank31 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK32_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN_OFS ( 0) /*!< BNK32_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank32 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK33_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN_OFS ( 1) /*!< BNK33_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank33 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK34_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN_OFS ( 2) /*!< BNK34_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank34 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK35_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN_OFS ( 3) /*!< BNK35_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank35 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK36_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN_OFS ( 4) /*!< BNK36_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank36 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK37_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN_OFS ( 5) /*!< BNK37_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank37 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK38_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN_OFS ( 6) /*!< BNK38_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank38 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK39_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN_OFS ( 7) /*!< BNK39_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank39 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK40_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN_OFS ( 8) /*!< BNK40_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank40 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK41_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN_OFS ( 9) /*!< BNK41_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank41 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK42_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN_OFS (10) /*!< BNK42_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank42 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK43_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN_OFS (11) /*!< BNK43_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank43 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK44_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN_OFS (12) /*!< BNK44_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank44 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK45_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN_OFS (13) /*!< BNK45_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank45 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK46_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN_OFS (14) /*!< BNK46_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank46 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK47_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN_OFS (15) /*!< BNK47_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank47 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK48_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN_OFS (16) /*!< BNK48_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank48 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK49_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN_OFS (17) /*!< BNK49_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank49 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK50_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN_OFS (18) /*!< BNK50_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank50 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK51_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN_OFS (19) /*!< BNK51_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank51 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK52_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN_OFS (20) /*!< BNK52_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank52 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK53_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN_OFS (21) /*!< BNK53_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank53 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK54_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN_OFS (22) /*!< BNK54_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank54 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK55_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN_OFS (23) /*!< BNK55_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank55 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK56_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN_OFS (24) /*!< BNK56_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank56 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK57_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN_OFS (25) /*!< BNK57_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank57 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK58_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN_OFS (26) /*!< BNK58_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank58 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK59_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN_OFS (27) /*!< BNK59_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank59 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK60_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN_OFS (28) /*!< BNK60_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank60 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK61_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN_OFS (29) /*!< BNK61_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank61 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK62_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN_OFS (30) /*!< BNK62_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank62 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK63_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN_OFS (31) /*!< BNK63_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank63 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK64_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN_OFS ( 0) /*!< BNK64_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank64 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK65_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN_OFS ( 1) /*!< BNK65_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank65 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK66_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN_OFS ( 2) /*!< BNK66_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank66 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK67_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN_OFS ( 3) /*!< BNK67_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank67 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK68_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN_OFS ( 4) /*!< BNK68_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank68 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK69_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN_OFS ( 5) /*!< BNK69_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank69 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK70_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN_OFS ( 6) /*!< BNK70_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank70 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK71_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN_OFS ( 7) /*!< BNK71_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank71 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK72_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN_OFS ( 8) /*!< BNK72_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank72 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK73_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN_OFS ( 9) /*!< BNK73_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank73 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK74_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN_OFS (10) /*!< BNK74_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank74 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK75_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN_OFS (11) /*!< BNK75_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank75 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK76_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN_OFS (12) /*!< BNK76_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank76 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK77_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN_OFS (13) /*!< BNK77_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank77 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK78_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN_OFS (14) /*!< BNK78_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank78 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK79_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN_OFS (15) /*!< BNK79_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank79 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK80_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN_OFS (16) /*!< BNK80_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank80 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK81_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN_OFS (17) /*!< BNK81_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank81 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK82_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN_OFS (18) /*!< BNK82_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank82 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK83_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN_OFS (19) /*!< BNK83_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank83 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK84_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN_OFS (20) /*!< BNK84_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank84 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK85_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN_OFS (21) /*!< BNK85_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank85 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK86_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN_OFS (22) /*!< BNK86_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank86 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK87_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN_OFS (23) /*!< BNK87_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank87 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK88_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN_OFS (24) /*!< BNK88_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank88 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK89_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN_OFS (25) /*!< BNK89_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank89 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK90_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN_OFS (26) /*!< BNK90_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank90 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK91_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN_OFS (27) /*!< BNK91_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank91 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK92_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN_OFS (28) /*!< BNK92_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank92 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK93_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN_OFS (29) /*!< BNK93_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank93 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK94_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN_OFS (30) /*!< BNK94_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank94 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK95_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN_OFS (31) /*!< BNK95_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank95 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK96_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN_OFS ( 0) /*!< BNK96_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank96 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK97_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN_OFS ( 1) /*!< BNK97_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank97 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK98_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN_OFS ( 2) /*!< BNK98_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank98 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK99_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN_OFS ( 3) /*!< BNK99_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank99 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK100_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN_OFS ( 4) /*!< BNK100_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank100 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK101_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN_OFS ( 5) /*!< BNK101_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank101 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK102_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN_OFS ( 6) /*!< BNK102_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank102 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK103_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN_OFS ( 7) /*!< BNK103_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank103 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK104_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN_OFS ( 8) /*!< BNK104_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank104 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK105_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN_OFS ( 9) /*!< BNK105_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank105 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK106_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN_OFS (10) /*!< BNK106_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank106 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK107_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN_OFS (11) /*!< BNK107_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank107 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK108_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN_OFS (12) /*!< BNK108_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank108 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK109_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN_OFS (13) /*!< BNK109_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank109 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK110_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN_OFS (14) /*!< BNK110_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank110 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK111_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN_OFS (15) /*!< BNK111_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank111 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK112_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN_OFS (16) /*!< BNK112_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank112 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK113_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN_OFS (17) /*!< BNK113_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank113 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK114_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN_OFS (18) /*!< BNK114_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank114 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK115_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN_OFS (19) /*!< BNK115_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank115 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK116_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN_OFS (20) /*!< BNK116_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank116 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK117_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN_OFS (21) /*!< BNK117_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank117 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK118_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN_OFS (22) /*!< BNK118_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank118 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK119_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN_OFS (23) /*!< BNK119_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank119 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK120_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN_OFS (24) /*!< BNK120_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank120 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK121_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN_OFS (25) /*!< BNK121_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank121 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK122_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN_OFS (26) /*!< BNK122_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank122 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK123_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN_OFS (27) /*!< BNK123_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank123 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK124_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN_OFS (28) /*!< BNK124_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank124 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK125_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN_OFS (29) /*!< BNK125_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank125 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK126_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN_OFS (30) /*!< BNK126_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank126 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK127_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN_OFS (31) /*!< BNK127_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank127 of the SRAM */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK0_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN_OFS ( 0) /*!< BLK0_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN ((uint32_t)0x00000001) /*!< Block0 is always retained in LPM3, LPM4 and LPM3.5 modes of operation */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK1_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN_OFS ( 1) /*!< BLK1_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN ((uint32_t)0x00000002) /*!< When 1, Block1 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK2_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN_OFS ( 2) /*!< BLK2_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN ((uint32_t)0x00000004) /*!< When 1, Block2 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK3_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN_OFS ( 3) /*!< BLK3_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN ((uint32_t)0x00000008) /*!< When 1, Block3 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK4_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN_OFS ( 4) /*!< BLK4_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN ((uint32_t)0x00000010) /*!< When 1, Block4 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK5_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN_OFS ( 5) /*!< BLK5_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN ((uint32_t)0x00000020) /*!< When 1, Block5 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK6_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN_OFS ( 6) /*!< BLK6_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN ((uint32_t)0x00000040) /*!< When 1, Block6 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK7_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN_OFS ( 7) /*!< BLK7_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN ((uint32_t)0x00000080) /*!< When 1, Block7 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK8_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN_OFS ( 8) /*!< BLK8_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN ((uint32_t)0x00000100) /*!< When 1, Block8 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK9_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN_OFS ( 9) /*!< BLK9_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN ((uint32_t)0x00000200) /*!< When 1, Block9 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK10_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN_OFS (10) /*!< BLK10_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN ((uint32_t)0x00000400) /*!< When 1, Block10 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK11_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN_OFS (11) /*!< BLK11_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN ((uint32_t)0x00000800) /*!< When 1, Block11 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK12_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN_OFS (12) /*!< BLK12_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN ((uint32_t)0x00001000) /*!< When 1, Block12 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK13_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN_OFS (13) /*!< BLK13_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN ((uint32_t)0x00002000) /*!< When 1, Block13 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK14_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN_OFS (14) /*!< BLK14_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN ((uint32_t)0x00004000) /*!< When 1, Block14 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK15_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN_OFS (15) /*!< BLK15_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN ((uint32_t)0x00008000) /*!< When 1, Block15 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK16_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN_OFS (16) /*!< BLK16_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN ((uint32_t)0x00010000) /*!< When 1, Block16 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK17_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN_OFS (17) /*!< BLK17_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN ((uint32_t)0x00020000) /*!< When 1, Block17 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK18_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN_OFS (18) /*!< BLK18_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN ((uint32_t)0x00040000) /*!< When 1, Block18 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK19_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN_OFS (19) /*!< BLK19_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN ((uint32_t)0x00080000) /*!< When 1, Block19 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK20_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN_OFS (20) /*!< BLK20_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN ((uint32_t)0x00100000) /*!< When 1, Block20 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK21_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN_OFS (21) /*!< BLK21_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN ((uint32_t)0x00200000) /*!< When 1, Block21 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK22_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN_OFS (22) /*!< BLK22_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN ((uint32_t)0x00400000) /*!< When 1, Block22 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK23_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN_OFS (23) /*!< BLK23_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN ((uint32_t)0x00800000) /*!< When 1, Block23 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK24_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN_OFS (24) /*!< BLK24_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN ((uint32_t)0x01000000) /*!< When 1, Block24 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK25_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN_OFS (25) /*!< BLK25_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN ((uint32_t)0x02000000) /*!< When 1, Block25 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK26_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN_OFS (26) /*!< BLK26_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN ((uint32_t)0x04000000) /*!< When 1, Block26 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK27_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN_OFS (27) /*!< BLK27_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN ((uint32_t)0x08000000) /*!< When 1, Block27 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK28_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN_OFS (28) /*!< BLK28_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN ((uint32_t)0x10000000) /*!< When 1, Block28 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK29_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN_OFS (29) /*!< BLK29_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN ((uint32_t)0x20000000) /*!< When 1, Block29 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK30_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN_OFS (30) /*!< BLK30_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN ((uint32_t)0x40000000) /*!< When 1, Block30 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK31_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN_OFS (31) /*!< BLK31_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN ((uint32_t)0x80000000) /*!< When 1, Block31 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK32_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN_OFS ( 0) /*!< BLK32_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN ((uint32_t)0x00000001) /*!< When 1, Block32 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK33_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN_OFS ( 1) /*!< BLK33_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN ((uint32_t)0x00000002) /*!< When 1, Block33 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK34_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN_OFS ( 2) /*!< BLK34_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN ((uint32_t)0x00000004) /*!< When 1, Block34 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK35_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN_OFS ( 3) /*!< BLK35_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN ((uint32_t)0x00000008) /*!< When 1, Block35 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK36_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN_OFS ( 4) /*!< BLK36_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN ((uint32_t)0x00000010) /*!< When 1, Block36 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK37_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN_OFS ( 5) /*!< BLK37_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN ((uint32_t)0x00000020) /*!< When 1, Block37 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK38_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN_OFS ( 6) /*!< BLK38_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN ((uint32_t)0x00000040) /*!< When 1, Block38 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK39_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN_OFS ( 7) /*!< BLK39_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN ((uint32_t)0x00000080) /*!< When 1, Block39 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK40_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN_OFS ( 8) /*!< BLK40_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN ((uint32_t)0x00000100) /*!< When 1, Block40 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK41_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN_OFS ( 9) /*!< BLK41_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN ((uint32_t)0x00000200) /*!< When 1, Block41 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK42_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN_OFS (10) /*!< BLK42_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN ((uint32_t)0x00000400) /*!< When 1, Block42 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK43_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN_OFS (11) /*!< BLK43_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN ((uint32_t)0x00000800) /*!< When 1, Block43 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK44_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN_OFS (12) /*!< BLK44_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN ((uint32_t)0x00001000) /*!< When 1, Block44 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK45_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN_OFS (13) /*!< BLK45_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN ((uint32_t)0x00002000) /*!< When 1, Block45 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK46_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN_OFS (14) /*!< BLK46_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN ((uint32_t)0x00004000) /*!< When 1, Block46 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK47_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN_OFS (15) /*!< BLK47_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN ((uint32_t)0x00008000) /*!< When 1, Block47 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK48_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN_OFS (16) /*!< BLK48_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN ((uint32_t)0x00010000) /*!< When 1, Block48 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK49_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN_OFS (17) /*!< BLK49_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN ((uint32_t)0x00020000) /*!< When 1, Block49 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK50_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN_OFS (18) /*!< BLK50_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN ((uint32_t)0x00040000) /*!< When 1, Block50 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK51_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN_OFS (19) /*!< BLK51_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN ((uint32_t)0x00080000) /*!< When 1, Block51 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK52_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN_OFS (20) /*!< BLK52_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN ((uint32_t)0x00100000) /*!< When 1, Block52 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK53_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN_OFS (21) /*!< BLK53_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN ((uint32_t)0x00200000) /*!< When 1, Block53 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK54_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN_OFS (22) /*!< BLK54_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN ((uint32_t)0x00400000) /*!< When 1, Block54 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK55_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN_OFS (23) /*!< BLK55_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN ((uint32_t)0x00800000) /*!< When 1, Block55 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK56_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN_OFS (24) /*!< BLK56_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN ((uint32_t)0x01000000) /*!< When 1, Block56 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK57_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN_OFS (25) /*!< BLK57_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN ((uint32_t)0x02000000) /*!< When 1, Block57 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK58_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN_OFS (26) /*!< BLK58_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN ((uint32_t)0x04000000) /*!< When 1, Block58 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK59_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN_OFS (27) /*!< BLK59_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN ((uint32_t)0x08000000) /*!< When 1, Block59 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK60_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN_OFS (28) /*!< BLK60_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN ((uint32_t)0x10000000) /*!< When 1, Block60 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK61_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN_OFS (29) /*!< BLK61_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN ((uint32_t)0x20000000) /*!< When 1, Block61 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK62_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN_OFS (30) /*!< BLK62_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN ((uint32_t)0x40000000) /*!< When 1, Block62 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK63_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN_OFS (31) /*!< BLK63_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN ((uint32_t)0x80000000) /*!< When 1, Block63 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK64_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN_OFS ( 0) /*!< BLK64_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN ((uint32_t)0x00000001) /*!< When 1, Block64 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK65_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN_OFS ( 1) /*!< BLK65_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN ((uint32_t)0x00000002) /*!< When 1, Block65 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK66_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN_OFS ( 2) /*!< BLK66_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN ((uint32_t)0x00000004) /*!< When 1, Block66 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK67_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN_OFS ( 3) /*!< BLK67_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN ((uint32_t)0x00000008) /*!< When 1, Block67 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK68_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN_OFS ( 4) /*!< BLK68_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN ((uint32_t)0x00000010) /*!< When 1, Block68 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK69_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN_OFS ( 5) /*!< BLK69_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN ((uint32_t)0x00000020) /*!< When 1, Block69 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK70_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN_OFS ( 6) /*!< BLK70_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN ((uint32_t)0x00000040) /*!< When 1, Block70 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK71_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN_OFS ( 7) /*!< BLK71_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN ((uint32_t)0x00000080) /*!< When 1, Block71 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK72_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN_OFS ( 8) /*!< BLK72_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN ((uint32_t)0x00000100) /*!< When 1, Block72 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK73_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN_OFS ( 9) /*!< BLK73_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN ((uint32_t)0x00000200) /*!< When 1, Block73 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK74_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN_OFS (10) /*!< BLK74_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN ((uint32_t)0x00000400) /*!< When 1, Block74 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK75_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN_OFS (11) /*!< BLK75_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN ((uint32_t)0x00000800) /*!< When 1, Block75 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK76_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN_OFS (12) /*!< BLK76_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN ((uint32_t)0x00001000) /*!< When 1, Block76 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK77_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN_OFS (13) /*!< BLK77_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN ((uint32_t)0x00002000) /*!< When 1, Block77 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK78_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN_OFS (14) /*!< BLK78_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN ((uint32_t)0x00004000) /*!< When 1, Block78 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK79_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN_OFS (15) /*!< BLK79_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN ((uint32_t)0x00008000) /*!< When 1, Block79 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK80_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN_OFS (16) /*!< BLK80_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN ((uint32_t)0x00010000) /*!< When 1, Block80 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK81_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN_OFS (17) /*!< BLK81_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN ((uint32_t)0x00020000) /*!< When 1, Block81 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK82_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN_OFS (18) /*!< BLK82_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN ((uint32_t)0x00040000) /*!< When 1, Block82 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK83_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN_OFS (19) /*!< BLK83_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN ((uint32_t)0x00080000) /*!< When 1, Block83 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK84_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN_OFS (20) /*!< BLK84_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN ((uint32_t)0x00100000) /*!< When 1, Block84 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK85_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN_OFS (21) /*!< BLK85_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN ((uint32_t)0x00200000) /*!< When 1, Block85 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK86_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN_OFS (22) /*!< BLK86_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN ((uint32_t)0x00400000) /*!< When 1, Block86 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK87_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN_OFS (23) /*!< BLK87_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN ((uint32_t)0x00800000) /*!< When 1, Block87 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK88_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN_OFS (24) /*!< BLK88_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN ((uint32_t)0x01000000) /*!< When 1, Block88 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK89_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN_OFS (25) /*!< BLK89_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN ((uint32_t)0x02000000) /*!< When 1, Block89 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK90_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN_OFS (26) /*!< BLK90_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN ((uint32_t)0x04000000) /*!< When 1, Block90 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK91_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN_OFS (27) /*!< BLK91_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN ((uint32_t)0x08000000) /*!< When 1, Block91 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK92_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN_OFS (28) /*!< BLK92_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN ((uint32_t)0x10000000) /*!< When 1, Block92 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK93_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN_OFS (29) /*!< BLK93_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN ((uint32_t)0x20000000) /*!< When 1, Block93 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK94_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN_OFS (30) /*!< BLK94_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN ((uint32_t)0x40000000) /*!< When 1, Block94 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK95_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN_OFS (31) /*!< BLK95_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN ((uint32_t)0x80000000) /*!< When 1, Block95 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK96_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN_OFS ( 0) /*!< BLK96_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN ((uint32_t)0x00000001) /*!< When 1, Block96 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK97_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN_OFS ( 1) /*!< BLK97_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN ((uint32_t)0x00000002) /*!< When 1, Block97 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK98_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN_OFS ( 2) /*!< BLK98_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN ((uint32_t)0x00000004) /*!< When 1, Block98 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK99_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN_OFS ( 3) /*!< BLK99_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN ((uint32_t)0x00000008) /*!< When 1, Block99 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK100_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN_OFS ( 4) /*!< BLK100_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN ((uint32_t)0x00000010) /*!< When 1, Block100 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK101_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN_OFS ( 5) /*!< BLK101_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN ((uint32_t)0x00000020) /*!< When 1, Block101 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK102_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN_OFS ( 6) /*!< BLK102_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN ((uint32_t)0x00000040) /*!< When 1, Block102 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK103_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN_OFS ( 7) /*!< BLK103_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN ((uint32_t)0x00000080) /*!< When 1, Block103 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK104_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN_OFS ( 8) /*!< BLK104_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN ((uint32_t)0x00000100) /*!< When 1, Block104 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK105_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN_OFS ( 9) /*!< BLK105_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN ((uint32_t)0x00000200) /*!< When 1, Block105 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK106_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN_OFS (10) /*!< BLK106_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN ((uint32_t)0x00000400) /*!< When 1, Block106 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK107_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN_OFS (11) /*!< BLK107_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN ((uint32_t)0x00000800) /*!< When 1, Block107 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK108_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN_OFS (12) /*!< BLK108_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN ((uint32_t)0x00001000) /*!< When 1, Block108 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK109_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN_OFS (13) /*!< BLK109_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN ((uint32_t)0x00002000) /*!< When 1, Block109 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK110_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN_OFS (14) /*!< BLK110_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN ((uint32_t)0x00004000) /*!< When 1, Block110 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK111_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN_OFS (15) /*!< BLK111_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN ((uint32_t)0x00008000) /*!< When 1, Block111 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK112_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN_OFS (16) /*!< BLK112_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN ((uint32_t)0x00010000) /*!< When 1, Block112 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK113_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN_OFS (17) /*!< BLK113_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN ((uint32_t)0x00020000) /*!< When 1, Block113 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK114_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN_OFS (18) /*!< BLK114_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN ((uint32_t)0x00040000) /*!< When 1, Block114 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK115_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN_OFS (19) /*!< BLK115_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN ((uint32_t)0x00080000) /*!< When 1, Block115 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK116_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN_OFS (20) /*!< BLK116_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN ((uint32_t)0x00100000) /*!< When 1, Block116 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK117_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN_OFS (21) /*!< BLK117_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN ((uint32_t)0x00200000) /*!< When 1, Block117 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK118_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN_OFS (22) /*!< BLK118_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN ((uint32_t)0x00400000) /*!< When 1, Block118 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK119_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN_OFS (23) /*!< BLK119_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN ((uint32_t)0x00800000) /*!< When 1, Block119 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK120_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN_OFS (24) /*!< BLK120_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN ((uint32_t)0x01000000) /*!< When 1, Block120 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK121_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN_OFS (25) /*!< BLK121_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN ((uint32_t)0x02000000) /*!< When 1, Block121 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK122_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN_OFS (26) /*!< BLK122_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN ((uint32_t)0x04000000) /*!< When 1, Block122 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK123_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN_OFS (27) /*!< BLK123_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN ((uint32_t)0x08000000) /*!< When 1, Block123 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK124_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN_OFS (28) /*!< BLK124_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN ((uint32_t)0x10000000) /*!< When 1, Block124 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK125_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN_OFS (29) /*!< BLK125_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN ((uint32_t)0x20000000) /*!< When 1, Block125 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK126_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN_OFS (30) /*!< BLK126_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN ((uint32_t)0x40000000) /*!< When 1, Block126 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK127_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN_OFS (31) /*!< BLK127_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN ((uint32_t)0x80000000) /*!< When 1, Block127 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_STAT[BNKEN_RDY] Bits */ -#define SYSCTL_A_SRAM_STAT_BNKEN_RDY_OFS ( 0) /*!< BNKEN_RDY Bit Offset */ -#define SYSCTL_A_SRAM_STAT_BNKEN_RDY ((uint32_t)0x00000001) /*!< When 1, indicates SRAM is ready for access and banks can be */ - /* enabled/disabled. */ -/* SYSCTL_A_SRAM_STAT[BLKRET_RDY] Bits */ -#define SYSCTL_A_SRAM_STAT_BLKRET_RDY_OFS ( 1) /*!< BLKRET_RDY Bit Offset */ -#define SYSCTL_A_SRAM_STAT_BLKRET_RDY ((uint32_t)0x00000002) /*!< When 1, indicates SRAM is ready for access and blocks can be */ - /* enabled/disabled for retention. */ -/* SYSCTL_A_MASTER_UNLOCK[UNLKEY] Bits */ -#define SYSCTL_A_MASTER_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_A_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -/* SYSCTL_A_RESET_REQ[POR] Bits */ -#define SYSCTL_A_RESET_REQ_POR_OFS ( 0) /*!< POR Bit Offset */ -#define SYSCTL_A_RESET_REQ_POR ((uint32_t)0x00000001) /*!< Generate POR */ -/* SYSCTL_A_RESET_REQ[REBOOT] Bits */ -#define SYSCTL_A_RESET_REQ_REBOOT_OFS ( 1) /*!< REBOOT Bit Offset */ -#define SYSCTL_A_RESET_REQ_REBOOT ((uint32_t)0x00000002) /*!< Generate Reboot_Reset */ -/* SYSCTL_A_RESET_REQ[WKEY] Bits */ -#define SYSCTL_A_RESET_REQ_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_A_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -/* SYSCTL_A_RESET_STATOVER[SOFT] Bits */ -#define SYSCTL_A_RESET_STATOVER_SOFT_OFS ( 0) /*!< SOFT Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /*!< Indicates if SOFT Reset is active */ -/* SYSCTL_A_RESET_STATOVER[HARD] Bits */ -#define SYSCTL_A_RESET_STATOVER_HARD_OFS ( 1) /*!< HARD Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_HARD ((uint32_t)0x00000002) /*!< Indicates if HARD Reset is active */ -/* SYSCTL_A_RESET_STATOVER[REBOOT] Bits */ -#define SYSCTL_A_RESET_STATOVER_REBOOT_OFS ( 2) /*!< REBOOT Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /*!< Indicates if Reboot Reset is active */ -/* SYSCTL_A_RESET_STATOVER[SOFT_OVER] Bits */ -#define SYSCTL_A_RESET_STATOVER_SOFT_OVER_OFS ( 8) /*!< SOFT_OVER Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /*!< SOFT_Reset overwrite request */ -/* SYSCTL_A_RESET_STATOVER[HARD_OVER] Bits */ -#define SYSCTL_A_RESET_STATOVER_HARD_OVER_OFS ( 9) /*!< HARD_OVER Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /*!< HARD_Reset overwrite request */ -/* SYSCTL_A_RESET_STATOVER[RBT_OVER] Bits */ -#define SYSCTL_A_RESET_STATOVER_RBT_OVER_OFS (10) /*!< RBT_OVER Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /*!< Reboot Reset overwrite request */ -/* Pre-defined bitfield values */ -#define SYSCTL_A_CSYS_MASTER_UNLOCK_UNLKEY_VAL ((uint32_t)0x0000695A) /*!< Unlock key value which when written, determines if accesses to other CPU_SYS register */ -#define SYSCTL_A_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ -#define SYSCTL_A_BOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ -#define SYSCTL_A_ETW_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ -#define SYSCTL_A_SECDATA_UNLOCK_KEY_VAL ((uint32_t)0x0000695A) /*!< Unlock Key value, which requests for secure data region to be unlocked for data access */ - - -/****************************************************************************** -* SYSTICK Bits -******************************************************************************/ - -/****************************************************************************** -* Timer32 Bits -******************************************************************************/ -/* TIMER32_CONTROL[ONESHOT] Bits */ -#define TIMER32_CONTROL_ONESHOT_OFS ( 0) /*!< ONESHOT Bit Offset */ -#define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /*!< Selects one-shot or wrapping counter mode */ -/* TIMER32_CONTROL[SIZE] Bits */ -#define TIMER32_CONTROL_SIZE_OFS ( 1) /*!< SIZE Bit Offset */ -#define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /*!< Selects 16 or 32 bit counter operation */ -/* TIMER32_CONTROL[PRESCALE] Bits */ -#define TIMER32_CONTROL_PRESCALE_OFS ( 2) /*!< PRESCALE Bit Offset */ -#define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /*!< PRESCALE Bit Mask */ -#define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /*!< PRESCALE Bit 0 */ -#define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /*!< PRESCALE Bit 1 */ -#define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /*!< 0 stages of prescale, clock is divided by 1 */ -#define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /*!< 4 stages of prescale, clock is divided by 16 */ -#define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /*!< 8 stages of prescale, clock is divided by 256 */ -/* TIMER32_CONTROL[IE] Bits */ -#define TIMER32_CONTROL_IE_OFS ( 5) /*!< IE Bit Offset */ -#define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /*!< Interrupt enable bit */ -/* TIMER32_CONTROL[MODE] Bits */ -#define TIMER32_CONTROL_MODE_OFS ( 6) /*!< MODE Bit Offset */ -#define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /*!< Mode bit */ -/* TIMER32_CONTROL[ENABLE] Bits */ -#define TIMER32_CONTROL_ENABLE_OFS ( 7) /*!< ENABLE Bit Offset */ -#define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080) -/* TIMER32_RIS[RAW_IFG] Bits */ -#define TIMER32_RIS_RAW_IFG_OFS ( 0) /*!< RAW_IFG Bit Offset */ -#define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /*!< Raw interrupt status */ -/* TIMER32_MIS[IFG] Bits */ -#define TIMER32_MIS_IFG_OFS ( 0) /*!< IFG Bit Offset */ -#define TIMER32_MIS_IFG ((uint32_t)0x00000001) /*!< Enabled interrupt status */ - - - -/****************************************************************************** -* TIMER_A Bits -******************************************************************************/ -/* TIMER_A_CTL[IFG] Bits */ -#define TIMER_A_CTL_IFG_OFS ( 0) /*!< TAIFG Bit Offset */ -#define TIMER_A_CTL_IFG ((uint16_t)0x0001) /*!< TimerA interrupt flag */ -/* TIMER_A_CTL[IE] Bits */ -#define TIMER_A_CTL_IE_OFS ( 1) /*!< TAIE Bit Offset */ -#define TIMER_A_CTL_IE ((uint16_t)0x0002) /*!< TimerA interrupt enable */ -/* TIMER_A_CTL[CLR] Bits */ -#define TIMER_A_CTL_CLR_OFS ( 2) /*!< TACLR Bit Offset */ -#define TIMER_A_CTL_CLR ((uint16_t)0x0004) /*!< TimerA clear */ -/* TIMER_A_CTL[MC] Bits */ -#define TIMER_A_CTL_MC_OFS ( 4) /*!< MC Bit Offset */ -#define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /*!< MC Bit Mask */ -#define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /*!< MC Bit 0 */ -#define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /*!< MC Bit 1 */ -#define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -#define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -/* TIMER_A_CTL[ID] Bits */ -#define TIMER_A_CTL_ID_OFS ( 6) /*!< ID Bit Offset */ -#define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /*!< ID Bit Mask */ -#define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /*!< ID Bit 0 */ -#define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /*!< ID Bit 1 */ -#define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /*!< /8 */ -#define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /*!< /8 */ -/* TIMER_A_CTL[SSEL] Bits */ -#define TIMER_A_CTL_SSEL_OFS ( 8) /*!< TASSEL Bit Offset */ -#define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /*!< TASSEL Bit Mask */ -#define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /*!< SSEL Bit 0 */ -#define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /*!< SSEL Bit 1 */ -#define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /*!< INCLK */ -#define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /*!< INCLK */ -/* TIMER_A_CCTLN[CCIFG] Bits */ -#define TIMER_A_CCTLN_CCIFG_OFS ( 0) /*!< CCIFG Bit Offset */ -#define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /*!< Capture/compare interrupt flag */ -/* TIMER_A_CCTLN[COV] Bits */ -#define TIMER_A_CCTLN_COV_OFS ( 1) /*!< COV Bit Offset */ -#define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /*!< Capture overflow */ -/* TIMER_A_CCTLN[OUT] Bits */ -#define TIMER_A_CCTLN_OUT_OFS ( 2) /*!< OUT Bit Offset */ -#define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /*!< Output */ -/* TIMER_A_CCTLN[CCI] Bits */ -#define TIMER_A_CCTLN_CCI_OFS ( 3) /*!< CCI Bit Offset */ -#define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /*!< Capture/compare input */ -/* TIMER_A_CCTLN[CCIE] Bits */ -#define TIMER_A_CCTLN_CCIE_OFS ( 4) /*!< CCIE Bit Offset */ -#define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /*!< Capture/compare interrupt enable */ -/* TIMER_A_CCTLN[OUTMOD] Bits */ -#define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /*!< OUTMOD Bit Offset */ -#define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /*!< OUTMOD Bit Mask */ -#define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /*!< OUTMOD Bit 0 */ -#define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /*!< OUTMOD Bit 1 */ -#define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /*!< OUTMOD Bit 2 */ -#define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /*!< OUT bit value */ -#define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /*!< Set */ -#define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /*!< Toggle/reset */ -#define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /*!< Set/reset */ -#define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /*!< Toggle */ -#define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /*!< Reset */ -#define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /*!< Toggle/set */ -#define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /*!< Reset/set */ -/* TIMER_A_CCTLN[CAP] Bits */ -#define TIMER_A_CCTLN_CAP_OFS ( 8) /*!< CAP Bit Offset */ -#define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /*!< Capture mode */ -/* TIMER_A_CCTLN[SCCI] Bits */ -#define TIMER_A_CCTLN_SCCI_OFS (10) /*!< SCCI Bit Offset */ -#define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /*!< Synchronized capture/compare input */ -/* TIMER_A_CCTLN[SCS] Bits */ -#define TIMER_A_CCTLN_SCS_OFS (11) /*!< SCS Bit Offset */ -#define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /*!< Synchronize capture source */ -/* TIMER_A_CCTLN[CCIS] Bits */ -#define TIMER_A_CCTLN_CCIS_OFS (12) /*!< CCIS Bit Offset */ -#define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /*!< CCIS Bit Mask */ -#define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /*!< CCIS Bit 0 */ -#define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /*!< CCIS Bit 1 */ -#define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /*!< VCC */ -#define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /*!< VCC */ -/* TIMER_A_CCTLN[CM] Bits */ -#define TIMER_A_CCTLN_CM_OFS (14) /*!< CM Bit Offset */ -#define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /*!< CM Bit Mask */ -#define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /*!< CM Bit 0 */ -#define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /*!< CM Bit 1 */ -#define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -#define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -/* TIMER_A_EX0[IDEX] Bits */ -#define TIMER_A_EX0_IDEX_OFS ( 0) /*!< TAIDEX Bit Offset */ -#define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /*!< TAIDEX Bit Mask */ -#define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /*!< IDEX Bit 0 */ -#define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /*!< IDEX Bit 1 */ -#define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /*!< IDEX Bit 2 */ -#define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /*!< Divide by 8 */ -#define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /*!< Divide by 8 */ - -/****************************************************************************** -* TLV Bits -******************************************************************************/ -/****************************************************************************** -* TLV table start and TLV tags * -******************************************************************************/ -#define TLV_START_ADDR (TLV_BASE + 0x0004) /*!< Start Address of the TLV structure */ - -#define TLV_TAG_RESERVED1 1 -#define TLV_TAG_RESERVED2 2 -#define TLV_TAG_CS 3 -#define TLV_TAG_FLASHCTL 4 -#define TLV_TAG_ADC14 5 -#define TLV_TAG_RESERVED6 6 -#define TLV_TAG_RESERVED7 7 -#define TLV_TAG_REF 8 -#define TLV_TAG_RESERVED9 9 -#define TLV_TAG_RESERVED10 10 -#define TLV_TAG_DEVINFO 11 -#define TLV_TAG_DIEREC 12 -#define TLV_TAG_RANDNUM 13 -#define TLV_TAG_RESERVED14 14 -#define TLV_TAG_BSL 15 -#define TLV_TAG_END (0x0BD0E11D) - - -/****************************************************************************** -* TPIU Bits -******************************************************************************/ - - -/****************************************************************************** -* WDT_A Bits -******************************************************************************/ -/* WDT_A_CTL[IS] Bits */ -#define WDT_A_CTL_IS_OFS ( 0) /*!< WDTIS Bit Offset */ -#define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /*!< WDTIS Bit Mask */ -#define WDT_A_CTL_IS0 ((uint16_t)0x0001) /*!< IS Bit 0 */ -#define WDT_A_CTL_IS1 ((uint16_t)0x0002) /*!< IS Bit 1 */ -#define WDT_A_CTL_IS2 ((uint16_t)0x0004) /*!< IS Bit 2 */ -#define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ -#define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ -/* WDT_A_CTL[CNTCL] Bits */ -#define WDT_A_CTL_CNTCL_OFS ( 3) /*!< WDTCNTCL Bit Offset */ -#define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /*!< Watchdog timer counter clear */ -/* WDT_A_CTL[TMSEL] Bits */ -#define WDT_A_CTL_TMSEL_OFS ( 4) /*!< WDTTMSEL Bit Offset */ -#define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /*!< Watchdog timer mode select */ -/* WDT_A_CTL[SSEL] Bits */ -#define WDT_A_CTL_SSEL_OFS ( 5) /*!< WDTSSEL Bit Offset */ -#define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /*!< WDTSSEL Bit Mask */ -#define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /*!< SSEL Bit 0 */ -#define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /*!< SSEL Bit 1 */ -#define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /*!< BCLK */ -#define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /*!< BCLK */ -/* WDT_A_CTL[HOLD] Bits */ -#define WDT_A_CTL_HOLD_OFS ( 7) /*!< WDTHOLD Bit Offset */ -#define WDT_A_CTL_HOLD ((uint16_t)0x0080) /*!< Watchdog timer hold */ -/* WDT_A_CTL[PW] Bits */ -#define WDT_A_CTL_PW_OFS ( 8) /*!< WDTPW Bit Offset */ -#define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /*!< WDTPW Bit Mask */ -/* Pre-defined bitfield values */ -#define WDT_A_CTL_PW ((uint16_t)0x5A00) /*!< WDT Key Value for WDT write access */ - - -/****************************************************************************** -* BSL * -******************************************************************************/ -#define BSL_DEFAULT_PARAM ((uint32_t)0xFC48FFFF) /*!< I2C slave address = 0x48, Interface selection = Auto */ -#define BSL_API_TABLE_ADDR ((uint32_t)0x00202000) /*!< Address of BSL API table */ -#define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR)) - -#define BSL_AUTO_INTERFACE ((uint32_t)0x0000E0000) /*!< Auto detect interface */ -#define BSL_UART_INTERFACE ((uint32_t)0x0000C0000) /*!< UART interface */ -#define BSL_SPI_INTERFACE ((uint32_t)0x0000A0000) /*!< SPI interface */ -#define BSL_I2C_INTERFACE ((uint32_t)0x000080000) /*!< I2C interface */ - -#define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */ - - -/****************************************************************************** -* Mailbox struct legacy definition * -******************************************************************************/ -#define FLASH_MAILBOX_Type FL_BOOTOVER_MAILBOX_Type - -/****************************************************************************** -* Device Unlock Support * -******************************************************************************/ -/* unlock the device by: - * Load SYSCTL_SECDATA_UNLOCK register address into R0 - * Load SYSCTL_SECDATA_UNLOCK unlock key into R1 - * Write the unlock key to the SYSCTL_SECDATA_UNLOCK register - */ -#define UNLOCK_DEVICE\ - __asm(" MOVW.W R0, #0x3040");\ - __asm(" MOVT.W R0, #0xE004");\ - __asm(" MOVW.W R1, #0x695A");\ - __asm(" MOVT.W R1, #0x0000");\ - __asm(" STR R1, [R0]"); - -/****************************************************************************** -* -* The following are values that can be used to choose the command that will be -* run by the boot code. Perform a logical OR of these settings to create your -* general parameter command. -* -******************************************************************************/ -#define COMMAND_FACTORY_RESET ((uint32_t)0x00010000) -#define COMMAND_BSL_CONFIG ((uint32_t)0x00020000) -#define COMMAND_JTAG_SWD_LOCK_SECEN ((uint32_t)0x00080000) -#define COMMAND_SEC_ZONE0_EN ((uint32_t)0x00100000) -#define COMMAND_SEC_ZONE1_EN ((uint32_t)0x00200000) -#define COMMAND_SEC_ZONE2_EN ((uint32_t)0x00400000) -#define COMMAND_SEC_ZONE3_EN ((uint32_t)0x00800000) -#define COMMAND_SEC_ZONE0_UPDATE ((uint32_t)0x01000000) -#define COMMAND_SEC_ZONE1_UPDATE ((uint32_t)0x02000000) -#define COMMAND_SEC_ZONE2_UPDATE ((uint32_t)0x04000000) -#define COMMAND_SEC_ZONE3_UPDATE ((uint32_t)0x08000000) -#define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE ((uint32_t)0x10000000) -#define COMMAND_NONE ((uint32_t)0xFFFFFFFF) - -/****************************************************************************** -* -* The following are values that can be used to configure the BSL. Perform a -* logical OR of these settings to create your BSL parameter. -* -******************************************************************************/ -#define BSL_CONFIG_HW_INVOKE ((uint32_t)0x70000000) - -#define BSL_CONFIG_HW_INVOKE_PORT1 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PORT2 ((uint32_t)0x00000001) -#define BSL_CONFIG_HW_INVOKE_PORT3 ((uint32_t)0x00000002) - -#define BSL_CONFIG_HW_INVOKE_PIN0 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN1 ((uint32_t)0x00000010) -#define BSL_CONFIG_HW_INVOKE_PIN2 ((uint32_t)0x00000020) -#define BSL_CONFIG_HW_INVOKE_PIN3 ((uint32_t)0x00000030) -#define BSL_CONFIG_HW_INVOKE_PIN4 ((uint32_t)0x00000040) -#define BSL_CONFIG_HW_INVOKE_PIN5 ((uint32_t)0x00000050) -#define BSL_CONFIG_HW_INVOKE_PIN6 ((uint32_t)0x00000060) -#define BSL_CONFIG_HW_INVOKE_PIN7 ((uint32_t)0x00000070) - -#define BSL_CONFIG_HW_INVOKE_PIN_LOW ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN_HIGH ((uint32_t)0x00001000) - -#define BSL_CONFIG_INTERFACE_I2C ((uint32_t)0x00008000) -#define BSL_CONFIG_INTERFACE_SPI ((uint32_t)0x0000A000) -#define BSL_CONFIG_INTERFACE_UART ((uint32_t)0x0000C000) -#define BSL_CONFIG_INTERFACE_AUTO ((uint32_t)0x0000E000) - -#define BSL_CONFIG_I2C_ADD_OFFSET (16) - - -/****************************************************************************** -* ULP Advisor * -******************************************************************************/ -#ifdef __TI_ARM__ -#pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8}) -#pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8}) -#pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8}) -#pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8}) -#pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8}) -#pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8}) -#pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8}) -#pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8}) -#pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8}) -#pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8}) -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* __MSP432P411V_H__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p411y.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p411y.h deleted file mode 100644 index 04578469f65..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p411y.h +++ /dev/null @@ -1,9839 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432P411Y Register Definitions -* -* This file includes CMSIS compliant component and register definitions -* -* For legacy components the definitions that are compatible with MSP430 code, -* are included with msp432p411y_classic.h -* -* With CMSIS definitions, the register defines have been reformatted: -* ModuleName[ModuleInstance]->RegisterName -* -* Writing to CMSIS bit fields can be done through register level -* or via bitband area access: -* - ADC14->CTL0 |= ADC14_CTL0_ENC; -* - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1; -* -* File creation date: 2017-08-03 -* -******************************************************************************/ - -#ifndef __MSP432P411Y_H__ -#define __MSP432P411Y_H__ - -/* Use standard integer types with explicit width */ -#include - -#ifdef __cplusplus - extern "C" { -#endif - -#define __MSP432_HEADER_VERSION__ 3202 - -/* Remap MSP432 intrinsics to ARM equivalents */ -#include "msp_compatibility.h" - -#ifndef __CMSIS_CONFIG__ -#define __CMSIS_CONFIG__ - -/** @addtogroup MSP432P411Y_Definitions MSP432P411Y Definitions - This file defines all structures and symbols for MSP432P411Y: - - components and registers - - peripheral base address - - peripheral ID - - Peripheral definitions - @{ -*/ - -/****************************************************************************** -* Processor and Core Peripherals * -******************************************************************************/ -/** @addtogroup MSP432P411Y_CMSIS Device CMSIS Definitions - Configuration of the Cortex-M4 Processor and Core Peripherals - @{ -*/ - -/****************************************************************************** -* CMSIS-compatible Interrupt Number Definition * -******************************************************************************/ -typedef enum IRQn -{ - /* Cortex-M4 Processor Exceptions Numbers */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - /* Peripheral Exceptions Numbers */ - PSS_IRQn = 0, /* 16 PSS Interrupt */ - CS_IRQn = 1, /* 17 CS Interrupt */ - PCM_IRQn = 2, /* 18 PCM Interrupt */ - WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */ - FPU_IRQn = 4, /* 20 FPU Interrupt */ - FLCTL_A_IRQn = 5, /* 21 Flash Controller Interrupt*/ - COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */ - COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */ - TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */ - TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */ - TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */ - TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */ - TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */ - TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */ - TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */ - TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */ - EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */ - EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */ - EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */ - EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */ - EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */ - EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */ - EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */ - EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */ - ADC14_IRQn = 24, /* 40 ADC14 Interrupt */ - T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */ - T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */ - T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */ - AES256_IRQn = 28, /* 44 AES256 Interrupt */ - RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */ - DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */ - DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */ - DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */ - DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */ - DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */ - PORT1_IRQn = 35, /* 51 Port1 Interrupt */ - PORT2_IRQn = 36, /* 52 Port2 Interrupt */ - PORT3_IRQn = 37, /* 53 Port3 Interrupt */ - PORT4_IRQn = 38, /* 54 Port4 Interrupt */ - PORT5_IRQn = 39, /* 55 Port5 Interrupt */ - PORT6_IRQn = 40, /* 56 Port6 Interrupt */ - LCD_F_IRQn = 41 /* 57 LCD_F Interrupt */ -} IRQn_Type; - -/****************************************************************************** -* Processor and Core Peripheral Section * -******************************************************************************/ -#define __CM4_REV 0x0001 /* Core revision r0p1 */ -#define __MPU_PRESENT 1 /* MPU present or not */ -#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /* FPU present or not */ - -/****************************************************************************** -* Available Peripherals * -******************************************************************************/ -#define __MCU_HAS_ADC14__ /*!< Module ADC14 is available */ -#define __MCU_HAS_AES256__ /*!< Module AES256 is available */ -#define __MCU_HAS_CAPTIO0__ /*!< Module CAPTIO0 is available */ -#define __MCU_HAS_CAPTIO1__ /*!< Module CAPTIO1 is available */ -#define __MCU_HAS_COMP_E0__ /*!< Module COMP_E0 is available */ -#define __MCU_HAS_COMP_E1__ /*!< Module COMP_E1 is available */ -#define __MCU_HAS_CRC32__ /*!< Module CRC32 is available */ -#define __MCU_HAS_CS__ /*!< Module CS is available */ -#define __MCU_HAS_DIO__ /*!< Module DIO is available */ -#define __MCU_HAS_DMA__ /*!< Module DMA is available */ -#define __MCU_HAS_EUSCI_A0__ /*!< Module EUSCI_A0 is available */ -#define __MCU_HAS_EUSCI_A1__ /*!< Module EUSCI_A1 is available */ -#define __MCU_HAS_EUSCI_A2__ /*!< Module EUSCI_A2 is available */ -#define __MCU_HAS_EUSCI_A3__ /*!< Module EUSCI_A3 is available */ -#define __MCU_HAS_EUSCI_B0__ /*!< Module EUSCI_B0 is available */ -#define __MCU_HAS_EUSCI_B1__ /*!< Module EUSCI_B1 is available */ -#define __MCU_HAS_EUSCI_B2__ /*!< Module EUSCI_B2 is available */ -#define __MCU_HAS_EUSCI_B3__ /*!< Module EUSCI_B3 is available */ -#define __MCU_HAS_FLCTL_A__ /*!< Module FLCTL_A is available */ -#define __MCU_HAS_FL_BOOTOVER_MAILBOX__ /*!< Module FL_BOOTOVER_MAILBOX is available */ -#define __MCU_HAS_LCD_F__ /*!< Module LCD_F is available */ -#define __MCU_HAS_PCM__ /*!< Module PCM is available */ -#define __MCU_HAS_PMAP__ /*!< Module PMAP is available */ -#define __MCU_HAS_PSS__ /*!< Module PSS is available */ -#define __MCU_HAS_REF_A__ /*!< Module REF_A is available */ -#define __MCU_HAS_RSTCTL__ /*!< Module RSTCTL is available */ -#define __MCU_HAS_RTC_C__ /*!< Module RTC_C is available */ -#define __MCU_HAS_SYSCTL_A__ /*!< Module SYSCTL_A is available */ -#define __MCU_HAS_TIMER32__ /*!< Module TIMER32 is available */ -#define __MCU_HAS_TIMER_A0__ /*!< Module TIMER_A0 is available */ -#define __MCU_HAS_TIMER_A1__ /*!< Module TIMER_A1 is available */ -#define __MCU_HAS_TIMER_A2__ /*!< Module TIMER_A2 is available */ -#define __MCU_HAS_TIMER_A3__ /*!< Module TIMER_A3 is available */ -#define __MCU_HAS_TLV__ /*!< Module TLV is available */ -#define __MCU_HAS_WDT_A__ /*!< Module WDT_A is available */ - -/* Definitions to show that specific ports are available */ - -#define __MSP432_HAS_PORTA_R__ -#define __MSP432_HAS_PORTB_R__ -#define __MSP432_HAS_PORTC_R__ -#define __MSP432_HAS_PORTD_R__ -#define __MSP432_HAS_PORTE_R__ -#define __MSP432_HAS_PORTJ_R__ - -#define __MSP432_HAS_PORT1_R__ -#define __MSP432_HAS_PORT2_R__ -#define __MSP432_HAS_PORT3_R__ -#define __MSP432_HAS_PORT4_R__ -#define __MSP432_HAS_PORT5_R__ -#define __MSP432_HAS_PORT6_R__ -#define __MSP432_HAS_PORT7_R__ -#define __MSP432_HAS_PORT8_R__ -#define __MSP432_HAS_PORT9_R__ -#define __MSP432_HAS_PORT10_R__ - - -/*@}*/ /* end of group MSP432P411Y_CMSIS */ - -/* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */ -#ifdef __TI_ARM__ -/* disable the TI ULP advisor check for the core header file definitions */ -#pragma diag_push -#pragma CHECK_ULP("none") -#include "core_cm4.h" -#pragma diag_pop -#else -#include "core_cm4.h" -#endif - -/* System Header */ -#include "system_msp432p411y.h" - -/****************************************************************************** -* Definition of standard bits * -******************************************************************************/ -#define BIT0 (uint16_t)(0x0001) -#define BIT1 (uint16_t)(0x0002) -#define BIT2 (uint16_t)(0x0004) -#define BIT3 (uint16_t)(0x0008) -#define BIT4 (uint16_t)(0x0010) -#define BIT5 (uint16_t)(0x0020) -#define BIT6 (uint16_t)(0x0040) -#define BIT7 (uint16_t)(0x0080) -#define BIT8 (uint16_t)(0x0100) -#define BIT9 (uint16_t)(0x0200) -#define BITA (uint16_t)(0x0400) -#define BITB (uint16_t)(0x0800) -#define BITC (uint16_t)(0x1000) -#define BITD (uint16_t)(0x2000) -#define BITE (uint16_t)(0x4000) -#define BITF (uint16_t)(0x8000) - -/****************************************************************************** -* Device and peripheral memory map * -******************************************************************************/ -/** @addtogroup MSP432P411Y_MemoryMap MSP432P411Y Memory Mapping - @{ -*/ - -#define FLASH_BASE ((uint32_t)0x00000000) /*!< Main Flash memory start address */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM memory start address */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripherals start address */ -#define PERIPH_BASE2 ((uint32_t)0xE0000000) /*!< Peripherals start address */ - -#define ADC14_BASE (PERIPH_BASE +0x00012000) /*!< Base address of module ADC14 registers */ -#define AES256_BASE (PERIPH_BASE +0x00003C00) /*!< Base address of module AES256 registers */ -#define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /*!< Base address of module CAPTIO0 registers */ -#define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /*!< Base address of module CAPTIO1 registers */ -#define COMP_E0_BASE (PERIPH_BASE +0x00003400) /*!< Base address of module COMP_E0 registers */ -#define COMP_E1_BASE (PERIPH_BASE +0x00003800) /*!< Base address of module COMP_E1 registers */ -#define CRC32_BASE (PERIPH_BASE +0x00004000) /*!< Base address of module CRC32 registers */ -#define CS_BASE (PERIPH_BASE +0x00010400) /*!< Base address of module CS registers */ -#define DIO_BASE (PERIPH_BASE +0x00004C00) /*!< Base address of module DIO registers */ -#define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address of module DMA registers */ -#define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define FLCTL_A_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL_A registers */ -#define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000) /*!< Base address of module FL_BOOTOVER_MAILBOX registers */ -#define LCD_F_BASE (PERIPH_BASE +0x00012400) /*!< Base address of module LCD_F registers */ -#define PCM_BASE (PERIPH_BASE +0x00010000) /*!< Base address of module PCM registers */ -#define PMAP_BASE (PERIPH_BASE +0x00005000) /*!< Base address of module PMAP registers */ -#define PSS_BASE (PERIPH_BASE +0x00010800) /*!< Base address of module PSS registers */ -#define REF_A_BASE (PERIPH_BASE +0x00003000) /*!< Base address of module REF_A registers */ -#define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /*!< Base address of module RSTCTL registers */ -#define RTC_C_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define SYSCTL_A_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL_A registers */ -#define TIMER32_BASE (PERIPH_BASE +0x0000C000) /*!< Base address of module TIMER32 registers */ -#define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /*!< Base address of module TIMER_A0 registers */ -#define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /*!< Base address of module TIMER_A1 registers */ -#define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /*!< Base address of module TIMER_A2 registers */ -#define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /*!< Base address of module TIMER_A3 registers */ -#define TLV_BASE ((uint32_t)0x00201000) /*!< Base address of module TLV registers */ -#define WDT_A_BASE (PERIPH_BASE +0x00004800) /*!< Base address of module WDT_A registers */ - - -/*@}*/ /* end of group MSP432P411Y_MemoryMap */ - -/****************************************************************************** -* Definitions for bit band access * -******************************************************************************/ -#define BITBAND_SRAM_BASE ((uint32_t)(0x22000000)) -#define BITBAND_PERI_BASE ((uint32_t)(0x42000000)) - -/* SRAM allows 32 bit bit band access */ -#define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4))) -/* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */ -#define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4))) - -/****************************************************************************** -* Peripheral register definitions * -******************************************************************************/ -/** @addtogroup MSP432P411Y_Peripherals MSP432P411Y Peripherals - MSP432P411Y Device Specific Peripheral registers structures - @{ -*/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - -/****************************************************************************** -* ADC14 Registers -******************************************************************************/ -/** @addtogroup ADC14 MSP432P411Y (ADC14) - @{ -*/ -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t LO0; /*!< Window Comparator Low Threshold 0 Register */ - __IO uint32_t HI0; /*!< Window Comparator High Threshold 0 Register */ - __IO uint32_t LO1; /*!< Window Comparator Low Threshold 1 Register */ - __IO uint32_t HI1; /*!< Window Comparator High Threshold 1 Register */ - __IO uint32_t MCTL[32]; /*!< Conversion Memory Control Register */ - __IO uint32_t MEM[32]; /*!< Conversion Memory Register */ - uint32_t RESERVED0[9]; - __IO uint32_t IER0; /*!< Interrupt Enable 0 Register */ - __IO uint32_t IER1; /*!< Interrupt Enable 1 Register */ - __I uint32_t IFGR0; /*!< Interrupt Flag 0 Register */ - __I uint32_t IFGR1; /*!< Interrupt Flag 1 Register */ - __O uint32_t CLRIFGR0; /*!< Clear Interrupt Flag 0 Register */ - __IO uint32_t CLRIFGR1; /*!< Clear Interrupt Flag 1 Register */ - __IO uint32_t IV; /*!< Interrupt Vector Register */ -} ADC14_Type; - -/*@}*/ /* end of group ADC14 */ - - -/****************************************************************************** -* AES256 Registers -******************************************************************************/ -/** @addtogroup AES256 MSP432P411Y (AES256) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< AES Accelerator Control Register 0 */ - __IO uint16_t CTL1; /*!< AES Accelerator Control Register 1 */ - __IO uint16_t STAT; /*!< AES Accelerator Status Register */ - __O uint16_t KEY; /*!< AES Accelerator Key Register */ - __O uint16_t DIN; /*!< AES Accelerator Data In Register */ - __O uint16_t DOUT; /*!< AES Accelerator Data Out Register */ - __O uint16_t XDIN; /*!< AES Accelerator XORed Data In Register */ - __O uint16_t XIN; /*!< AES Accelerator XORed Data In Register */ -} AES256_Type; - -/*@}*/ /* end of group AES256 */ - - -/****************************************************************************** -* CAPTIO Registers -******************************************************************************/ -/** @addtogroup CAPTIO MSP432P411Y (CAPTIO) - @{ -*/ -typedef struct { - uint16_t RESERVED0[7]; - __IO uint16_t CTL; /*!< Capacitive Touch IO x Control Register */ -} CAPTIO_Type; - -/*@}*/ /* end of group CAPTIO */ - - -/****************************************************************************** -* COMP_E Registers -******************************************************************************/ -/** @addtogroup COMP_E MSP432P411Y (COMP_E) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< Comparator Control Register 0 */ - __IO uint16_t CTL1; /*!< Comparator Control Register 1 */ - __IO uint16_t CTL2; /*!< Comparator Control Register 2 */ - __IO uint16_t CTL3; /*!< Comparator Control Register 3 */ - uint16_t RESERVED0[2]; - __IO uint16_t INT; /*!< Comparator Interrupt Control Register */ - __I uint16_t IV; /*!< Comparator Interrupt Vector Word Register */ -} COMP_E_Type; - -/*@}*/ /* end of group COMP_E */ - - -/****************************************************************************** -* CRC32 Registers -******************************************************************************/ -/** @addtogroup CRC32 MSP432P411Y (CRC32) - @{ -*/ -typedef struct { - __IO uint16_t DI32; /*!< Data Input for CRC32 Signature Computation */ - uint16_t RESERVED0; - __IO uint16_t DIRB32; /*!< Data In Reverse for CRC32 Computation */ - uint16_t RESERVED1; - __IO uint16_t INIRES32_LO; /*!< CRC32 Initialization and Result, lower 16 bits */ - __IO uint16_t INIRES32_HI; /*!< CRC32 Initialization and Result, upper 16 bits */ - __IO uint16_t RESR32_LO; /*!< CRC32 Result Reverse, lower 16 bits */ - __IO uint16_t RESR32_HI; /*!< CRC32 Result Reverse, Upper 16 bits */ - __IO uint16_t DI16; /*!< Data Input for CRC16 computation */ - uint16_t RESERVED2; - __IO uint16_t DIRB16; /*!< CRC16 Data In Reverse */ - uint16_t RESERVED3; - __IO uint16_t INIRES16; /*!< CRC16 Initialization and Result register */ - uint16_t RESERVED4[2]; - __IO uint16_t RESR16; /*!< CRC16 Result Reverse */ -} CRC32_Type; - -/*@}*/ /* end of group CRC32 */ - - -/****************************************************************************** -* CS Registers -******************************************************************************/ -/** @addtogroup CS MSP432P411Y (CS) - @{ -*/ -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t CTL2; /*!< Control 2 Register */ - __IO uint32_t CTL3; /*!< Control 3 Register */ - uint32_t RESERVED0[7]; - __IO uint32_t CLKEN; /*!< Clock Enable Register */ - __I uint32_t STAT; /*!< Status Register */ - uint32_t RESERVED1[2]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - uint32_t RESERVED2; - __I uint32_t IFG; /*!< Interrupt Flag Register */ - uint32_t RESERVED3; - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - uint32_t RESERVED4; - __O uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - uint32_t RESERVED5; - __IO uint32_t DCOERCAL0; /*!< DCO External Resistor Cailbration 0 Register */ - __IO uint32_t DCOERCAL1; /*!< DCO External Resistor Calibration 1 Register */ -} CS_Type; - -/*@}*/ /* end of group CS */ - - -/****************************************************************************** -* DIO Registers -******************************************************************************/ -/** @addtogroup DIO MSP432P4111 (DIO) - @{ -*/ -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - __I uint16_t IV_L; /*!< Low Port Interrupt Vector Value */ - uint16_t RESERVED0[3]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; - union { - __IO uint16_t IES; /*!< Port Pair Interrupt Edge Select */ - struct { - __IO uint8_t IES_L; /*!< Low Port Interrupt Edge Select */ - __IO uint8_t IES_H; /*!< High Port Interrupt Edge Select */ - }; - }; - union { - __IO uint16_t IE; /*!< Port Pair Interrupt Enable */ - struct { - __IO uint8_t IE_L; /*!< Low Port Interrupt Enable */ - __IO uint8_t IE_H; /*!< High Port Interrupt Enable */ - }; - }; - union { - __IO uint16_t IFG; /*!< Port Pair Interrupt Flag */ - struct { - __IO uint8_t IFG_L; /*!< Low Port Interrupt Flag */ - __IO uint8_t IFG_H; /*!< High Port Interrupt Flag */ - }; - }; - __I uint16_t IV_H; /*!< High Port Interrupt Vector Value */ -} DIO_PORT_Interruptable_Type; - -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - uint16_t RESERVED0[4]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; -} DIO_PORT_Not_Interruptable_Type; - - -typedef struct { - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED0; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED1; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED2; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED3; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED4; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED5; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED6; - __I uint16_t IV; /*!< Port Interrupt Vector Value */ - uint8_t RESERVED7[6]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ -} DIO_PORT_Odd_Interruptable_Type; - -typedef struct { - uint8_t RESERVED0; - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED1; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED2; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED3; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED4; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED5; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED6; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED7[9]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ - __I uint16_t IV; /*!< Port Interrupt Vector Value */ -} DIO_PORT_Even_Interruptable_Type; - -/*@}*/ /* end of group MSP432P4111_DIO */ - - -/****************************************************************************** -* DMA Registers -******************************************************************************/ -/** @addtogroup DMA MSP432P4111 (DMA) - @{ -*/ -typedef struct { - __I uint32_t DEVICE_CFG; /*!< Device Configuration Status */ - __IO uint32_t SW_CHTRIG; /*!< Software Channel Trigger Register */ - uint32_t RESERVED0[2]; - __IO uint32_t CH_SRCCFG[32]; /*!< Channel n Source Configuration Register */ - uint32_t RESERVED1[28]; - __IO uint32_t INT1_SRCCFG; /*!< Interrupt 1 Source Channel Configuration */ - __IO uint32_t INT2_SRCCFG; /*!< Interrupt 2 Source Channel Configuration Register */ - __IO uint32_t INT3_SRCCFG; /*!< Interrupt 3 Source Channel Configuration Register */ - uint32_t RESERVED2; - __I uint32_t INT0_SRCFLG; /*!< Interrupt 0 Source Channel Flag Register */ - __O uint32_t INT0_CLRFLG; /*!< Interrupt 0 Source Channel Clear Flag Register */ -} DMA_Channel_Type; - -typedef struct { - __I uint32_t STAT; /*!< Status Register */ - __O uint32_t CFG; /*!< Configuration Register */ - __IO uint32_t CTLBASE; /*!< Channel Control Data Base Pointer Register */ - __I uint32_t ALTBASE; /*!< Channel Alternate Control Data Base Pointer Register */ - __I uint32_t WAITSTAT; /*!< Channel Wait on Request Status Register */ - __O uint32_t SWREQ; /*!< Channel Software Request Register */ - __IO uint32_t USEBURSTSET; /*!< Channel Useburst Set Register */ - __O uint32_t USEBURSTCLR; /*!< Channel Useburst Clear Register */ - __IO uint32_t REQMASKSET; /*!< Channel Request Mask Set Register */ - __O uint32_t REQMASKCLR; /*!< Channel Request Mask Clear Register */ - __IO uint32_t ENASET; /*!< Channel Enable Set Register */ - __O uint32_t ENACLR; /*!< Channel Enable Clear Register */ - __IO uint32_t ALTSET; /*!< Channel Primary-Alternate Set Register */ - __O uint32_t ALTCLR; /*!< Channel Primary-Alternate Clear Register */ - __IO uint32_t PRIOSET; /*!< Channel Priority Set Register */ - __O uint32_t PRIOCLR; /*!< Channel Priority Clear Register */ - uint32_t RESERVED4[3]; - __IO uint32_t ERRCLR; /*!< Bus Error Clear Register */ -} DMA_Control_Type; - -/*@}*/ /* end of group DMA */ - - -/****************************************************************************** -* EUSCI_A Registers -******************************************************************************/ -/** @addtogroup EUSCI_A MSP432P411Y (EUSCI_A) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Ax Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Ax Baud Rate Control Word Register */ - __IO uint16_t MCTLW; /*!< eUSCI_Ax Modulation Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Ax Status Register */ - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - __IO uint16_t ABCTL; /*!< eUSCI_Ax Auto Baud Rate Control Register */ - __IO uint16_t IRCTL; /*!< eUSCI_Ax IrDA Control Word Register */ - uint16_t RESERVED1[3]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_Type; - -/*@}*/ /* end of group EUSCI_A */ - -/** @addtogroup EUSCI_A_SPI MSP432P411Y (EUSCI_A_SPI) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Ax Bit Rate Control Register 1 */ - uint16_t RESERVED1; - __IO uint16_t STATW; - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - uint16_t RESERVED2[5]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_SPI_Type; - -/*@}*/ /* end of group EUSCI_A_SPI */ - - -/****************************************************************************** -* EUSCI_B Registers -******************************************************************************/ -/** @addtogroup EUSCI_B MSP432P411Y (EUSCI_B) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Bx Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Bx Baud Rate Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Bx Status Register */ - __IO uint16_t TBCNT; /*!< eUSCI_Bx Byte Counter Threshold Register */ - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED1[2]; - __IO uint16_t I2COA0; /*!< eUSCI_Bx I2C Own Address 0 Register */ - __IO uint16_t I2COA1; /*!< eUSCI_Bx I2C Own Address 1 Register */ - __IO uint16_t I2COA2; /*!< eUSCI_Bx I2C Own Address 2 Register */ - __IO uint16_t I2COA3; /*!< eUSCI_Bx I2C Own Address 3 Register */ - __I uint16_t ADDRX; /*!< eUSCI_Bx I2C Received Address Register */ - __IO uint16_t ADDMASK; /*!< eUSCI_Bx I2C Address Mask Register */ - __IO uint16_t I2CSA; /*!< eUSCI_Bx I2C Slave Address Register */ - uint16_t RESERVED2[4]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_Type; - -/*@}*/ /* end of group EUSCI_B */ - -/** @addtogroup EUSCI_B_SPI MSP432P411Y (EUSCI_B_SPI) - @{ -*/ -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Bx Bit Rate Control Register 1 */ - __IO uint16_t STATW; - uint16_t RESERVED1; - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED2[13]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_SPI_Type; - -/*@}*/ /* end of group EUSCI_B_SPI */ - - -/****************************************************************************** -* FLCTL_A Registers -******************************************************************************/ -/** @addtogroup FLCTL_A MSP432P411Y (FLCTL_A) - @{ -*/ -typedef struct { - __I uint32_t POWER_STAT; /*!< Power Status Register */ - uint32_t RESERVED0[3]; - __IO uint32_t BANK0_RDCTL; /*!< Bank0 Read Control Register */ - __IO uint32_t BANK1_RDCTL; /*!< Bank1 Read Control Register */ - uint32_t RESERVED1[2]; - __IO uint32_t RDBRST_CTLSTAT; /*!< Read Burst/Compare Control and Status Register */ - __IO uint32_t RDBRST_STARTADDR; /*!< Read Burst/Compare Start Address Register */ - __IO uint32_t RDBRST_LEN; /*!< Read Burst/Compare Length Register */ - uint32_t RESERVED2[4]; - __IO uint32_t RDBRST_FAILADDR; /*!< Read Burst/Compare Fail Address Register */ - __IO uint32_t RDBRST_FAILCNT; /*!< Read Burst/Compare Fail Count Register */ - uint32_t RESERVED3[3]; - __IO uint32_t PRG_CTLSTAT; /*!< Program Control and Status Register */ - __IO uint32_t PRGBRST_CTLSTAT; /*!< Program Burst Control and Status Register */ - __IO uint32_t PRGBRST_STARTADDR; /*!< Program Burst Start Address Register */ - uint32_t RESERVED4; - __IO uint32_t PRGBRST_DATA0_0; /*!< Program Burst Data0 Register0 */ - __IO uint32_t PRGBRST_DATA0_1; /*!< Program Burst Data0 Register1 */ - __IO uint32_t PRGBRST_DATA0_2; /*!< Program Burst Data0 Register2 */ - __IO uint32_t PRGBRST_DATA0_3; /*!< Program Burst Data0 Register3 */ - __IO uint32_t PRGBRST_DATA1_0; /*!< Program Burst Data1 Register0 */ - __IO uint32_t PRGBRST_DATA1_1; /*!< Program Burst Data1 Register1 */ - __IO uint32_t PRGBRST_DATA1_2; /*!< Program Burst Data1 Register2 */ - __IO uint32_t PRGBRST_DATA1_3; /*!< Program Burst Data1 Register3 */ - __IO uint32_t PRGBRST_DATA2_0; /*!< Program Burst Data2 Register0 */ - __IO uint32_t PRGBRST_DATA2_1; /*!< Program Burst Data2 Register1 */ - __IO uint32_t PRGBRST_DATA2_2; /*!< Program Burst Data2 Register2 */ - __IO uint32_t PRGBRST_DATA2_3; /*!< Program Burst Data2 Register3 */ - __IO uint32_t PRGBRST_DATA3_0; /*!< Program Burst Data3 Register0 */ - __IO uint32_t PRGBRST_DATA3_1; /*!< Program Burst Data3 Register1 */ - __IO uint32_t PRGBRST_DATA3_2; /*!< Program Burst Data3 Register2 */ - __IO uint32_t PRGBRST_DATA3_3; /*!< Program Burst Data3 Register3 */ - __IO uint32_t ERASE_CTLSTAT; /*!< Erase Control and Status Register */ - __IO uint32_t ERASE_SECTADDR; /*!< Erase Sector Address Register */ - uint32_t RESERVED5[2]; - __IO uint32_t BANK0_INFO_WEPROT; /*!< Information Memory Bank0 Write/Erase Protection Register */ - __IO uint32_t BANK0_MAIN_WEPROT; /*!< Main Memory Bank0 Write/Erase Protection Register */ - uint32_t RESERVED6[2]; - __IO uint32_t BANK1_INFO_WEPROT; /*!< Information Memory Bank1 Write/Erase Protection Register */ - __IO uint32_t BANK1_MAIN_WEPROT; /*!< Main Memory Bank1 Write/Erase Protection Register */ - uint32_t RESERVED7[2]; - __IO uint32_t BMRK_CTLSTAT; /*!< Benchmark Control and Status Register */ - __IO uint32_t BMRK_IFETCH; /*!< Benchmark Instruction Fetch Count Register */ - __IO uint32_t BMRK_DREAD; /*!< Benchmark Data Read Count Register */ - __IO uint32_t BMRK_CMP; /*!< Benchmark Count Compare Register */ - uint32_t RESERVED8[4]; - __IO uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - __IO uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - __I uint32_t READ_TIMCTL; /*!< Read Timing Control Register */ - __I uint32_t READMARGIN_TIMCTL; /*!< Read Margin Timing Control Register */ - __I uint32_t PRGVER_TIMCTL; /*!< Program Verify Timing Control Register */ - __I uint32_t ERSVER_TIMCTL; /*!< Erase Verify Timing Control Register */ - __I uint32_t LKGVER_TIMCTL; /*!< Leakage Verify Timing Control Register */ - __I uint32_t PROGRAM_TIMCTL; /*!< Program Timing Control Register */ - __I uint32_t ERASE_TIMCTL; /*!< Erase Timing Control Register */ - __I uint32_t MASSERASE_TIMCTL; /*!< Mass Erase Timing Control Register */ - __I uint32_t BURSTPRG_TIMCTL; /*!< Burst Program Timing Control Register */ - uint32_t RESERVED9[55]; - __IO uint32_t BANK0_MAIN_WEPROT0; /*!< Main Memory Bank0 Write/Erase Protection Register 0 */ - __IO uint32_t BANK0_MAIN_WEPROT1; /*!< Main Memory Bank0 Write/Erase Protection Register 1 */ - __IO uint32_t BANK0_MAIN_WEPROT2; /*!< Main Memory Bank0 Write/Erase Protection Register 2 */ - __IO uint32_t BANK0_MAIN_WEPROT3; /*!< Main Memory Bank0 Write/Erase Protection Register 3 */ - __IO uint32_t BANK0_MAIN_WEPROT4; /*!< Main Memory Bank0 Write/Erase Protection Register 4 */ - __IO uint32_t BANK0_MAIN_WEPROT5; /*!< Main Memory Bank0 Write/Erase Protection Register 5 */ - __IO uint32_t BANK0_MAIN_WEPROT6; /*!< Main Memory Bank0 Write/Erase Protection Register 6 */ - __IO uint32_t BANK0_MAIN_WEPROT7; /*!< Main Memory Bank0 Write/Erase Protection Register 7 */ - uint32_t RESERVED10[8]; - __IO uint32_t BANK1_MAIN_WEPROT0; /*!< Main Memory Bank1 Write/Erase Protection Register 0 */ - __IO uint32_t BANK1_MAIN_WEPROT1; /*!< Main Memory Bank1 Write/Erase Protection Register 1 */ - __IO uint32_t BANK1_MAIN_WEPROT2; /*!< Main Memory Bank1 Write/Erase Protection Register 2 */ - __IO uint32_t BANK1_MAIN_WEPROT3; /*!< Main Memory Bank1 Write/Erase Protection Register 3 */ - __IO uint32_t BANK1_MAIN_WEPROT4; /*!< Main Memory Bank1 Write/Erase Protection Register 4 */ - __IO uint32_t BANK1_MAIN_WEPROT5; /*!< Main Memory Bank1 Write/Erase Protection Register 5 */ - __IO uint32_t BANK1_MAIN_WEPROT6; /*!< Main Memory Bank1 Write/Erase Protection Register 6 */ - __IO uint32_t BANK1_MAIN_WEPROT7; /*!< Main Memory Bank1 Write/Erase Protection Register 7 */ -} FLCTL_A_Type; - -/*@}*/ /* end of group FLCTL_A */ - - -/****************************************************************************** -* FL_BOOTOVER_MAILBOX Registers -******************************************************************************/ -/** @addtogroup SEC_ZONE_PARAMS MSP432P411Y (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t SEC_ZONE_SECEN; /*!< IP Protection Secure Zone Enable. */ - __IO uint32_t SEC_ZONE_START_ADDR; /*!< Start address of IP protected secure zone. */ - __IO uint32_t SEC_ZONE_LENGTH; /*!< Length of IP protected secure zone in number of bytes. */ - __IO uint32_t SEC_ZONE_AESINIT_VECT[4]; /*!< IP protected secure zone 0 AES initialization vector */ - __IO uint32_t SEC_ZONE_SECKEYS[8]; /*!< AES-CBC security keys. */ - __IO uint32_t SEC_ZONE_UNENC_PWD[4]; /*!< Unencrypted password for authentication. */ - __IO uint32_t SEC_ZONE_ENCUPDATE_EN; /*!< IP Protected Secure Zone Encrypted In-field Update Enable */ - __IO uint32_t SEC_ZONE_DATA_EN; /*!< IP Protected Secure Zone Data Access Enable */ - __IO uint32_t SEC_ZONE_ACK; /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */ - uint32_t RESERVED0[2]; -} SEC_ZONE_PARAMS_Type; - -/*@}*/ /* end of group SEC_ZONE_PARAMS */ - -/** @addtogroup SEC_ZONE_UPDATE MSP432P411Y (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t SEC_ZONE_PAYLOADADDR; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t SEC_ZONE_PAYLOADLEN; /*!< Length of the payload in bytes. */ - __IO uint32_t SEC_ZONE_UPDATE_ACK; /*!< Acknowledgment for the IP Protected Secure Zone Update Command */ - uint32_t RESERVED0; -} SEC_ZONE_UPDATE_Type; - -/*@}*/ /* end of group SEC_ZONE_UPDATE */ - -/** @addtogroup FL_BOOTOVER_MAILBOX MSP432P411Y (FL_BOOTOVER_MAILBOX) - @{ -*/ -typedef struct { - __IO uint32_t MB_START; /*!< Flash MailBox start: 0x0115ACF6 */ - __IO uint32_t CMD; /*!< Command for Boot override operations. */ - uint32_t RESERVED0[2]; - __IO uint32_t JTAG_SWD_LOCK_SECEN; /*!< JTAG and SWD Lock Enable */ - __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4]; /*!< JTAG and SWD lock AES initialization vector for AES-CBC */ - __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8]; /*!< JTAG and SWD lock AES CBC security Keys 0-7. */ - __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4]; /*!< JTAG and SWD lock unencrypted password */ - __IO uint32_t JTAG_SWD_LOCK_ACK; /*!< Acknowledgment for JTAG and SWD Lock command */ - uint32_t RESERVED1[2]; - SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4]; - __IO uint32_t BSL_ENABLE; /*!< BSL Enable. */ - __IO uint32_t BSL_START_ADDRESS; /*!< Contains the pointer to the BSL function. */ - __IO uint32_t BSL_PARAMETERS; /*!< BSL hardware invoke conifguration field. */ - uint32_t RESERVED2[2]; - __IO uint32_t BSL_ACK; /*!< Acknowledgment for the BSL Configuration Command */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN; /*!< Length of the encrypted payload in bytes */ - __IO uint32_t JTAG_SWD_LOCK_DST_ADDR; /*!< Destination address where the final data needs to be stored into the device. */ - __IO uint32_t ENC_UPDATE_ACK; /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */ - uint32_t RESERVED3; - SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4]; - uint32_t RESERVED4; - __IO uint32_t FACTORY_RESET_ENABLE; /*!< Enable/Disable Factory Reset */ - __IO uint32_t FACTORY_RESET_PWDEN; /*!< Factory reset password enable */ - __IO uint32_t FACTORY_RESET_PWD[4]; /*!< 128-bit Password for factory reset to be saved into the device. */ - __IO uint32_t FACTORY_RESET_PARAMS_ACK; /*!< Acknowledgment for the Factory Reset Params Command */ - uint32_t RESERVED5; - __IO uint32_t FACTORY_RESET_PASSWORD[4]; /*!< 128-bit Password for factory reset. */ - __IO uint32_t FACTORY_RESET_ACK; /*!< Acknowledgment for the Factory Reset Command */ - uint32_t RESERVED6[2]; - __IO uint32_t MB_END; /*!< Mailbox end */ -} FL_BOOTOVER_MAILBOX_Type; - -/*@}*/ /* end of group FL_BOOTOVER_MAILBOX */ - - -/****************************************************************************** -* LCD_F Registers -******************************************************************************/ -/** @addtogroup LCD_F MSP432P411Y (LCD_F) - @{ -*/ -typedef struct { - __IO uint32_t CTL; /*!< LCD_F control */ - __IO uint32_t BMCTL; /*!< LCD_F blinking and memory control */ - __IO uint32_t VCTL; /*!< LCD_F voltage control */ - __IO uint32_t PCTL0; /*!< LCD_F port control 0 */ - __IO uint32_t PCTL1; /*!< LCD_F port control 1 */ - __IO uint32_t CSSEL0; /*!< LCD_F COM/SEG select register 0 */ - __IO uint32_t CSSEL1; /*!< LCD_F COM/SEG select register 1 */ - __IO uint32_t ANMCTL; /*!< LCD_F Animation Control Register */ - uint32_t RESERVED0[60]; - __IO uint32_t IE; /*!< LCD_F interrupt enable register */ - __I uint32_t IFG; /*!< LCD_F interrupt flag register */ - __O uint32_t SETIFG; /*!< LCD_F set interrupt flag register */ - __O uint32_t CLRIFG; /*!< LCD_F clear interrupt flag register */ - __IO uint8_t M[48]; /*!< LCD memory registers */ - uint8_t RESERVED1[16]; - __IO uint8_t BM[48]; /*!< LCD Blinking memory registers */ - uint8_t RESERVED2[16]; - __IO uint8_t ANM[8]; /*!< LCD Animation memory registers */ -} LCD_F_Type; - -/*@}*/ /* end of group LCD_F */ - - -/****************************************************************************** -* PCM Registers -******************************************************************************/ -/** @addtogroup PCM MSP432P411Y (PCM) - @{ -*/ -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PCM_Type; - -/*@}*/ /* end of group PCM */ - - -/****************************************************************************** -* PMAP Registers -******************************************************************************/ -/** @addtogroup PMAP MSP432P4111 (PMAP) - @{ -*/ -typedef struct { - __IO uint16_t KEYID; /*!< Port Mapping Key Register */ - __IO uint16_t CTL; /*!< Port Mapping Control Register */ -} PMAP_COMMON_Type; - -typedef struct { - union { - __IO uint16_t PMAP_REGISTER[4]; /*!< Port Mapping Registers */ - struct { - __IO uint8_t PMAP_REGISTER0; /*!< Port Mapping Register Bit 0 */ - __IO uint8_t PMAP_REGISTER1; /*!< Port Mapping Register Bit 1 */ - __IO uint8_t PMAP_REGISTER2; /*!< Port Mapping Register Bit 2 */ - __IO uint8_t PMAP_REGISTER3; /*!< Port Mapping Register Bit 3 */ - __IO uint8_t PMAP_REGISTER4; /*!< Port Mapping Register Bit 4 */ - __IO uint8_t PMAP_REGISTER5; /*!< Port Mapping Register Bit 5 */ - __IO uint8_t PMAP_REGISTER6; /*!< Port Mapping Register Bit 6 */ - __IO uint8_t PMAP_REGISTER7; /*!< Port Mapping Register Bit 7 */ - }; - }; -} PMAP_REGISTER_Type; - -/*@}*/ /* end of group PMAP */ - - -/****************************************************************************** -* PSS Registers -******************************************************************************/ -/** @addtogroup PSS MSP432P411Y (PSS) - @{ -*/ -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - uint32_t RESERVED0[11]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PSS_Type; - -/*@}*/ /* end of group PSS */ - - -/****************************************************************************** -* REF_A Registers -******************************************************************************/ -/** @addtogroup REF_A MSP432P411Y (REF_A) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< REF Control Register 0 */ -} REF_A_Type; - -/*@}*/ /* end of group REF_A */ - - -/****************************************************************************** -* RSTCTL Registers -******************************************************************************/ -/** @addtogroup RSTCTL MSP432P411Y (RSTCTL) - @{ -*/ -typedef struct { - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __I uint32_t HARDRESET_STAT; /*!< Hard Reset Status Register */ - __IO uint32_t HARDRESET_CLR; /*!< Hard Reset Status Clear Register */ - __IO uint32_t HARDRESET_SET; /*!< Hard Reset Status Set Register */ - __I uint32_t SOFTRESET_STAT; /*!< Soft Reset Status Register */ - __IO uint32_t SOFTRESET_CLR; /*!< Soft Reset Status Clear Register */ - __IO uint32_t SOFTRESET_SET; /*!< Soft Reset Status Set Register */ - uint32_t RESERVED0[57]; - __I uint32_t PSSRESET_STAT; /*!< PSS Reset Status Register */ - __IO uint32_t PSSRESET_CLR; /*!< PSS Reset Status Clear Register */ - __I uint32_t PCMRESET_STAT; /*!< PCM Reset Status Register */ - __IO uint32_t PCMRESET_CLR; /*!< PCM Reset Status Clear Register */ - __I uint32_t PINRESET_STAT; /*!< Pin Reset Status Register */ - __IO uint32_t PINRESET_CLR; /*!< Pin Reset Status Clear Register */ - __I uint32_t REBOOTRESET_STAT; /*!< Reboot Reset Status Register */ - __IO uint32_t REBOOTRESET_CLR; /*!< Reboot Reset Status Clear Register */ - __I uint32_t CSRESET_STAT; /*!< CS Reset Status Register */ - __IO uint32_t CSRESET_CLR; /*!< CS Reset Status Clear Register */ -} RSTCTL_Type; - -/*@}*/ /* end of group RSTCTL */ - - -/****************************************************************************** -* RTC_C Registers -******************************************************************************/ -/** @addtogroup RTC_C MSP432P411Y (RTC_C) - @{ -*/ -typedef struct { - __IO uint16_t CTL0; /*!< RTCCTL0 Register */ - __IO uint16_t CTL13; /*!< RTCCTL13 Register */ - __IO uint16_t OCAL; /*!< RTCOCAL Register */ - __IO uint16_t TCMP; /*!< RTCTCMP Register */ - __IO uint16_t PS0CTL; /*!< Real-Time Clock Prescale Timer 0 Control Register */ - __IO uint16_t PS1CTL; /*!< Real-Time Clock Prescale Timer 1 Control Register */ - __IO uint16_t PS; /*!< Real-Time Clock Prescale Timer Counter Register */ - __I uint16_t IV; /*!< Real-Time Clock Interrupt Vector Register */ - __IO uint16_t TIM0; /*!< RTCTIM0 Register Hexadecimal Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week */ - __IO uint16_t DATE; /*!< RTCDATE - Hexadecimal Format */ - __IO uint16_t YEAR; /*!< RTCYEAR Register Hexadecimal Format */ - __IO uint16_t AMINHR; /*!< RTCMINHR - Hexadecimal Format */ - __IO uint16_t ADOWDAY; /*!< RTCADOWDAY - Hexadecimal Format */ - __IO uint16_t BIN2BCD; /*!< Binary-to-BCD Conversion Register */ - __IO uint16_t BCD2BIN; /*!< BCD-to-Binary Conversion Register */ -} RTC_C_Type; - -/*@}*/ /* end of group RTC_C */ - -/** @addtogroup RTC_C_BCD MSP432P411Y (RTC_C_BCD) - @{ -*/ -typedef struct { - uint16_t RESERVED0[8]; - __IO uint16_t TIM0; /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week - BCD Format */ - __IO uint16_t DATE; /*!< Real-Time Clock Date - BCD Format */ - __IO uint16_t YEAR; /*!< Real-Time Clock Year Register - BCD Format */ - __IO uint16_t AMINHR; /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */ - __IO uint16_t ADOWDAY; /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */ -} RTC_C_BCD_Type; - -/*@}*/ /* end of group RTC_C_BCD */ - - -/****************************************************************************** -* SYSCTL_A Registers -******************************************************************************/ -/** @addtogroup SYSCTL_A MSP432P4111 (SYSCTL_A) - @{ -*/ -typedef struct { - __IO uint32_t REBOOT_CTL; /*!< Reboot Control Register */ - __IO uint32_t NMI_CTLSTAT; /*!< NMI Control and Status Register */ - __IO uint32_t WDTRESET_CTL; /*!< Watchdog Reset Control Register */ - __IO uint32_t PERIHALT_CTL; /*!< Peripheral Halt Control Register */ - __I uint32_t SRAM_SIZE; /*!< SRAM Size Register */ - __I uint32_t SRAM_NUMBANKS; /*!< SRAM Number of Banks Register */ - __I uint32_t SRAM_NUMBLOCKS; /*!< SRAM Number of Blocks Register */ - uint32_t RESERVED0; - __I uint32_t MAINFLASH_SIZE; /*!< Flash Main Memory Size Register */ - __I uint32_t INFOFLASH_SIZE; /*!< Flash Information Memory Size Register */ - uint32_t RESERVED1[2]; - __IO uint32_t DIO_GLTFLT_CTL; /*!< Digital I/O Glitch Filter Control Register */ - uint32_t RESERVED2[3]; - __IO uint32_t SECDATA_UNLOCK; /*!< IP Protected Secure Zone Data Access Unlock Register */ - uint32_t RESERVED3[3]; - __IO uint32_t SRAM_BANKEN_CTL0; /*!< SRAM Bank Enable Control Register 0 */ - __IO uint32_t SRAM_BANKEN_CTL1; /*!< SRAM Bank Enable Control Register 1 */ - __IO uint32_t SRAM_BANKEN_CTL2; /*!< SRAM Bank Enable Control Register 2 */ - __IO uint32_t SRAM_BANKEN_CTL3; /*!< SRAM Bank Enable Control Register 3 */ - uint32_t RESERVED4[4]; - __IO uint32_t SRAM_BLKRET_CTL0; /*!< SRAM Block Retention Control Register 0 */ - __IO uint32_t SRAM_BLKRET_CTL1; /*!< SRAM Block Retention Control Register 1 */ - __IO uint32_t SRAM_BLKRET_CTL2; /*!< SRAM Block Retention Control Register 2 */ - __IO uint32_t SRAM_BLKRET_CTL3; /*!< SRAM Block Retention Control Register 3 */ - uint32_t RESERVED5[4]; - __I uint32_t SRAM_STAT; /*!< SRAM Status Register */ -} SYSCTL_A_Type; - -typedef struct { - __IO uint32_t MASTER_UNLOCK; /*!< Master Unlock Register */ - __IO uint32_t BOOTOVER_REQ[2]; /*!< Boot Override Request Register */ - __IO uint32_t BOOTOVER_ACK; /*!< Boot Override Acknowledge Register */ - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __IO uint32_t RESET_STATOVER; /*!< Reset Status and Override Register */ - uint32_t RESERVED10[2]; - __I uint32_t SYSTEM_STAT; /*!< System Status Register */ -} SYSCTL_A_Boot_Type; - -/*@}*/ /* end of group SYSCTL_A */ - - -/****************************************************************************** -* Timer32 Registers -******************************************************************************/ -/** @addtogroup Timer32 MSP432P4111 (Timer32) - @{ -*/ -typedef struct { - __IO uint32_t LOAD; /*!< Timer Load Register */ - __I uint32_t VALUE; /*!< Timer Current Value Register */ - __IO uint32_t CONTROL; /*!< Timer Timer Control Register */ - __O uint32_t INTCLR; /*!< Timer Interrupt Clear Register */ - __I uint32_t RIS; /*!< Timer Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< Timer Interrupt Status Register */ - __IO uint32_t BGLOAD; /*!< Timer Background Load Register */ -} Timer32_Type; - -/*@}*/ /* end of group Timer32 */ - - -/****************************************************************************** -* Timer_A Registers -******************************************************************************/ -/** @addtogroup Timer_A MSP432P411Y (Timer_A) - @{ -*/ -typedef struct { - __IO uint16_t CTL; /*!< TimerAx Control Register */ - __IO uint16_t CCTL[5]; /*!< Timer_A Capture/Compare Control Register */ - uint16_t RESERVED0[2]; - __IO uint16_t R; /*!< TimerA register */ - __IO uint16_t CCR[5]; /*!< Timer_A Capture/Compare Register */ - uint16_t RESERVED1[2]; - __IO uint16_t EX0; /*!< TimerAx Expansion 0 Register */ - uint16_t RESERVED2[6]; - __I uint16_t IV; /*!< TimerAx Interrupt Vector Register */ -} Timer_A_Type; - -/*@}*/ /* end of group Timer_A */ - - -/****************************************************************************** -* TLV Registers -******************************************************************************/ -/** @addtogroup TLV MSP432P411Y (TLV) - @{ -*/ -typedef struct { - __I uint32_t TLV_CHECKSUM; /*!< TLV Checksum */ - __I uint32_t DEVICE_INFO_TAG; /*!< Device Info Tag */ - __I uint32_t DEVICE_INFO_LEN; /*!< Device Info Length */ - __I uint32_t DEVICE_ID; /*!< Device ID */ - __I uint32_t HWREV; /*!< HW Revision */ - __I uint32_t BCREV; /*!< Boot Code Revision */ - __I uint32_t ROM_DRVLIB_REV; /*!< ROM Driver Library Revision */ - __I uint32_t DIE_REC_TAG; /*!< Die Record Tag */ - __I uint32_t DIE_REC_LEN; /*!< Die Record Length */ - __I uint32_t DIE_XPOS; /*!< Die X-Position */ - __I uint32_t DIE_YPOS; /*!< Die Y-Position */ - __I uint32_t WAFER_ID; /*!< Wafer ID */ - __I uint32_t LOT_ID; /*!< Lot ID */ - __I uint32_t RESERVED0; /*!< Reserved */ - __I uint32_t RESERVED1; /*!< Reserved */ - __I uint32_t RESERVED2; /*!< Reserved */ - __I uint32_t TEST_RESULTS; /*!< Test Results */ - __I uint32_t CS_CAL_TAG; /*!< Clock System Calibration Tag */ - __I uint32_t CS_CAL_LEN; /*!< Clock System Calibration Length */ - __I uint32_t DCOIR_FCAL_RSEL04; /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_FCAL_RSEL5; /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED3; /*!< Reserved */ - __I uint32_t RESERVED4; /*!< Reserved */ - __I uint32_t RESERVED5; /*!< Reserved */ - __I uint32_t RESERVED6; /*!< Reserved */ - __I uint32_t DCOIR_CONSTK_RSEL04; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_CONSTK_RSEL5; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t DCOER_FCAL_RSEL04; /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOER_FCAL_RSEL5; /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED7; /*!< Reserved */ - __I uint32_t RESERVED8; /*!< Reserved */ - __I uint32_t RESERVED9; /*!< Reserved */ - __I uint32_t RESERVED10; /*!< Reserved */ - __I uint32_t DCOER_CONSTK_RSEL04; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I uint32_t DCOER_CONSTK_RSEL5; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t ADC14_CAL_TAG; /*!< ADC14 Calibration Tag */ - __I uint32_t ADC14_CAL_LEN; /*!< ADC14 Calibration Length */ - __I uint32_t ADC_GAIN_FACTOR; /*!< ADC Gain Factor */ - __I uint32_t ADC_OFFSET; /*!< ADC Offset */ - __I uint32_t RESERVED11; /*!< Reserved */ - __I uint32_t RESERVED12; /*!< Reserved */ - __I uint32_t RESERVED13; /*!< Reserved */ - __I uint32_t RESERVED14; /*!< Reserved */ - __I uint32_t RESERVED15; /*!< Reserved */ - __I uint32_t RESERVED16; /*!< Reserved */ - __I uint32_t RESERVED17; /*!< Reserved */ - __I uint32_t RESERVED18; /*!< Reserved */ - __I uint32_t RESERVED19; /*!< Reserved */ - __I uint32_t RESERVED20; /*!< Reserved */ - __I uint32_t RESERVED21; /*!< Reserved */ - __I uint32_t RESERVED22; /*!< Reserved */ - __I uint32_t RESERVED23; /*!< Reserved */ - __I uint32_t RESERVED24; /*!< Reserved */ - __I uint32_t RESERVED25; /*!< Reserved */ - __I uint32_t RESERVED26; /*!< Reserved */ - __I uint32_t ADC14_REF1P2V_TS30C; /*!< ADC14 1.2V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P2V_TS85C; /*!< ADC14 1.2V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF1P45V_TS30C; /*!< ADC14 1.45V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P45V_TS85C; /*!< ADC14 1.45V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF2P5V_TS30C; /*!< ADC14 2.5V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF2P5V_TS85C; /*!< ADC14 2.5V Reference Temp. Sensor 85C */ - __I uint32_t REF_CAL_TAG; /*!< REF Calibration Tag */ - __I uint32_t REF_CAL_LEN; /*!< REF Calibration Length */ - __I uint32_t REF_1P2V; /*!< REF 1.2V Reference */ - __I uint32_t REF_1P45V; /*!< REF 1.45V Reference */ - __I uint32_t REF_2P5V; /*!< REF 2.5V Reference */ - __I uint32_t FLASH_INFO_TAG; /*!< Flash Info Tag */ - __I uint32_t FLASH_INFO_LEN; /*!< Flash Info Length */ - __I uint32_t FLASH_MAX_PROG_PULSES; /*!< Flash Maximum Programming Pulses */ - __I uint32_t FLASH_MAX_ERASE_PULSES; /*!< Flash Maximum Erase Pulses */ - __I uint32_t RANDOM_NUM_TAG; /*!< 128-bit Random Number Tag */ - __I uint32_t RANDOM_NUM_LEN; /*!< 128-bit Random Number Length */ - __I uint32_t RANDOM_NUM_1; /*!< 32-bit Random Number 1 */ - __I uint32_t RANDOM_NUM_2; /*!< 32-bit Random Number 2 */ - __I uint32_t RANDOM_NUM_3; /*!< 32-bit Random Number 3 */ - __I uint32_t RANDOM_NUM_4; /*!< 32-bit Random Number 4 */ - __I uint32_t BSL_CFG_TAG; /*!< BSL Configuration Tag */ - __I uint32_t BSL_CFG_LEN; /*!< BSL Configuration Length */ - __I uint32_t BSL_PERIPHIF_SEL; /*!< BSL Peripheral Interface Selection */ - __I uint32_t BSL_PORTIF_CFG_UART; /*!< BSL Port Interface Configuration for UART */ - __I uint32_t BSL_PORTIF_CFG_SPI; /*!< BSL Port Interface Configuration for SPI */ - __I uint32_t BSL_PORTIF_CFG_I2C; /*!< BSL Port Interface Configuration for I2C */ - __I uint32_t TLV_END; /*!< TLV End Word */ -} TLV_Type; - -/*@}*/ /* end of group TLV */ - - -/****************************************************************************** -* WDT_A Registers -******************************************************************************/ -/** @addtogroup WDT_A MSP432P411Y (WDT_A) - @{ -*/ -typedef struct { - uint16_t RESERVED0[6]; - __IO uint16_t CTL; /*!< Watchdog Timer Control Register */ -} WDT_A_Type; - -/*@}*/ /* end of group WDT_A */ - - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/*@}*/ /* end of group MSP432P411Y_Peripherals */ - -/****************************************************************************** -* Peripheral declaration * -******************************************************************************/ -/** @addtogroup MSP432P411Y_PeripheralDecl MSP432P411Y Peripheral Declaration - @{ -*/ - -#define ADC14 ((ADC14_Type *) ADC14_BASE) -#define AES256 ((AES256_Type *) AES256_BASE) -#define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE) -#define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE) -#define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE) -#define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE) -#define CRC32 ((CRC32_Type *) CRC32_BASE) -#define CS ((CS_Type *) CS_BASE) -#define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120)) -#define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define DMA_Channel ((DMA_Channel_Type *) DMA_BASE) -#define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000)) -#define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE) -#define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE) -#define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE) -#define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE) -#define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE) -#define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE) -#define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE) -#define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE) -#define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE) -#define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE) -#define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE) -#define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE) -#define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE) -#define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE) -#define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE) -#define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE) -#define FLCTL_A ((FLCTL_A_Type *) FLCTL_A_BASE) -#define FL_BOOTOVER_MAILBOX ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE) -#define LCD_F ((LCD_F_Type *) LCD_F_BASE) -#define PCM ((PCM_Type *) PCM_BASE) -#define PMAP ((PMAP_COMMON_Type*) PMAP_BASE) -#define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008)) -#define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010)) -#define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018)) -#define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020)) -#define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028)) -#define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030)) -#define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038)) -#define PSS ((PSS_Type *) PSS_BASE) -#define REF_A ((REF_A_Type *) REF_A_BASE) -#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) -#define RTC_C ((RTC_C_Type *) RTC_C_BASE) -#define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE) -#define SYSCTL_A ((SYSCTL_A_Type *) SYSCTL_A_BASE) -#define SYSCTL_A_Boot ((SYSCTL_A_Boot_Type *) (SYSCTL_A_BASE + 0x1000)) -#define TIMER32_1 ((Timer32_Type *) TIMER32_BASE) -#define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020)) -#define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE) -#define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE) -#define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE) -#define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE) -#define TLV ((TLV_Type *) TLV_BASE) -#define WDT_A ((WDT_A_Type *) WDT_A_BASE) - - -/*@}*/ /* end of group MSP432P411Y_PeripheralDecl */ - -/*@}*/ /* end of group MSP432P411Y_Definitions */ - -#endif /* __CMSIS_CONFIG__ */ - -/****************************************************************************** -* Peripheral register control bits * -******************************************************************************/ - -/****************************************************************************** -* ADC14 Bits -******************************************************************************/ -/* ADC14_CTL0[SC] Bits */ -#define ADC14_CTL0_SC_OFS ( 0) /*!< ADC14SC Bit Offset */ -#define ADC14_CTL0_SC ((uint32_t)0x00000001) /*!< ADC14 start conversion */ -/* ADC14_CTL0[ENC] Bits */ -#define ADC14_CTL0_ENC_OFS ( 1) /*!< ADC14ENC Bit Offset */ -#define ADC14_CTL0_ENC ((uint32_t)0x00000002) /*!< ADC14 enable conversion */ -/* ADC14_CTL0[ON] Bits */ -#define ADC14_CTL0_ON_OFS ( 4) /*!< ADC14ON Bit Offset */ -#define ADC14_CTL0_ON ((uint32_t)0x00000010) /*!< ADC14 on */ -/* ADC14_CTL0[MSC] Bits */ -#define ADC14_CTL0_MSC_OFS ( 7) /*!< ADC14MSC Bit Offset */ -#define ADC14_CTL0_MSC ((uint32_t)0x00000080) /*!< ADC14 multiple sample and conversion */ -/* ADC14_CTL0[SHT0] Bits */ -#define ADC14_CTL0_SHT0_OFS ( 8) /*!< ADC14SHT0 Bit Offset */ -#define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /*!< ADC14SHT0 Bit Mask */ -#define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /*!< SHT0 Bit 0 */ -#define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /*!< SHT0 Bit 1 */ -#define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /*!< SHT0 Bit 2 */ -#define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /*!< SHT0 Bit 3 */ -#define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /*!< 192 */ -#define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /*!< 192 */ -/* ADC14_CTL0[SHT1] Bits */ -#define ADC14_CTL0_SHT1_OFS (12) /*!< ADC14SHT1 Bit Offset */ -#define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /*!< ADC14SHT1 Bit Mask */ -#define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /*!< SHT1 Bit 0 */ -#define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /*!< SHT1 Bit 1 */ -#define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /*!< SHT1 Bit 2 */ -#define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /*!< SHT1 Bit 3 */ -#define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /*!< 192 */ -#define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /*!< 192 */ -/* ADC14_CTL0[BUSY] Bits */ -#define ADC14_CTL0_BUSY_OFS (16) /*!< ADC14BUSY Bit Offset */ -#define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /*!< ADC14 busy */ -/* ADC14_CTL0[CONSEQ] Bits */ -#define ADC14_CTL0_CONSEQ_OFS (17) /*!< ADC14CONSEQ Bit Offset */ -#define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /*!< ADC14CONSEQ Bit Mask */ -#define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /*!< CONSEQ Bit 0 */ -#define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /*!< CONSEQ Bit 1 */ -#define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /*!< Single-channel, single-conversion */ -#define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /*!< Sequence-of-channels */ -#define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /*!< Repeat-single-channel */ -#define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /*!< Repeat-sequence-of-channels */ -/* ADC14_CTL0[SSEL] Bits */ -#define ADC14_CTL0_SSEL_OFS (19) /*!< ADC14SSEL Bit Offset */ -#define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /*!< ADC14SSEL Bit Mask */ -#define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /*!< SSEL Bit 0 */ -#define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /*!< SSEL Bit 1 */ -#define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /*!< SSEL Bit 2 */ -#define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /*!< HSMCLK */ -#define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /*!< HSMCLK */ -/* ADC14_CTL0[DIV] Bits */ -#define ADC14_CTL0_DIV_OFS (22) /*!< ADC14DIV Bit Offset */ -#define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /*!< ADC14DIV Bit Mask */ -#define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /*!< DIV Bit 0 */ -#define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /*!< DIV Bit 1 */ -#define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /*!< DIV Bit 2 */ -#define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /*!< /8 */ -#define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /*!< /8 */ -/* ADC14_CTL0[ISSH] Bits */ -#define ADC14_CTL0_ISSH_OFS (25) /*!< ADC14ISSH Bit Offset */ -#define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /*!< ADC14 invert signal sample-and-hold */ -/* ADC14_CTL0[SHP] Bits */ -#define ADC14_CTL0_SHP_OFS (26) /*!< ADC14SHP Bit Offset */ -#define ADC14_CTL0_SHP ((uint32_t)0x04000000) /*!< ADC14 sample-and-hold pulse-mode select */ -/* ADC14_CTL0[SHS] Bits */ -#define ADC14_CTL0_SHS_OFS (27) /*!< ADC14SHS Bit Offset */ -#define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /*!< ADC14SHS Bit Mask */ -#define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /*!< SHS Bit 0 */ -#define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /*!< SHS Bit 1 */ -#define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /*!< SHS Bit 2 */ -#define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /*!< ADC14SC bit */ -#define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /*!< See device-specific data sheet for source */ -/* ADC14_CTL0[PDIV] Bits */ -#define ADC14_CTL0_PDIV_OFS (30) /*!< ADC14PDIV Bit Offset */ -#define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /*!< ADC14PDIV Bit Mask */ -#define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /*!< PDIV Bit 0 */ -#define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /*!< PDIV Bit 1 */ -#define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -#define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -/* ADC14_CTL1[PWRMD] Bits */ -#define ADC14_CTL1_PWRMD_OFS ( 0) /*!< ADC14PWRMD Bit Offset */ -#define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /*!< ADC14PWRMD Bit Mask */ -#define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /*!< PWRMD Bit 0 */ -#define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /*!< PWRMD Bit 1 */ -#define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /*!< Regular power mode for use with any resolution setting. Sample rate can be */ - /* up to 1 Msps. */ -#define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample */ - /* rate must not exceed 200 ksps. */ -/* ADC14_CTL1[REFBURST] Bits */ -#define ADC14_CTL1_REFBURST_OFS ( 2) /*!< ADC14REFBURST Bit Offset */ -#define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /*!< ADC14 reference buffer burst */ -/* ADC14_CTL1[DF] Bits */ -#define ADC14_CTL1_DF_OFS ( 3) /*!< ADC14DF Bit Offset */ -#define ADC14_CTL1_DF ((uint32_t)0x00000008) /*!< ADC14 data read-back format */ -/* ADC14_CTL1[RES] Bits */ -#define ADC14_CTL1_RES_OFS ( 4) /*!< ADC14RES Bit Offset */ -#define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /*!< ADC14RES Bit Mask */ -#define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /*!< RES Bit 0 */ -#define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /*!< RES Bit 1 */ -#define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -#define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -/* ADC14_CTL1[CSTARTADD] Bits */ -#define ADC14_CTL1_CSTARTADD_OFS (16) /*!< ADC14CSTARTADD Bit Offset */ -#define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /*!< ADC14CSTARTADD Bit Mask */ -/* ADC14_CTL1[BATMAP] Bits */ -#define ADC14_CTL1_BATMAP_OFS (22) /*!< ADC14BATMAP Bit Offset */ -#define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /*!< Controls 1/2 AVCC ADC input channel selection */ -/* ADC14_CTL1[TCMAP] Bits */ -#define ADC14_CTL1_TCMAP_OFS (23) /*!< ADC14TCMAP Bit Offset */ -#define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /*!< Controls temperature sensor ADC input channel selection */ -/* ADC14_CTL1[CH0MAP] Bits */ -#define ADC14_CTL1_CH0MAP_OFS (24) /*!< ADC14CH0MAP Bit Offset */ -#define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */ -/* ADC14_CTL1[CH1MAP] Bits */ -#define ADC14_CTL1_CH1MAP_OFS (25) /*!< ADC14CH1MAP Bit Offset */ -#define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */ -/* ADC14_CTL1[CH2MAP] Bits */ -#define ADC14_CTL1_CH2MAP_OFS (26) /*!< ADC14CH2MAP Bit Offset */ -#define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */ -/* ADC14_CTL1[CH3MAP] Bits */ -#define ADC14_CTL1_CH3MAP_OFS (27) /*!< ADC14CH3MAP Bit Offset */ -#define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */ -/* ADC14_LO0[LO0] Bits */ -#define ADC14_LO0_LO0_OFS ( 0) /*!< ADC14LO0 Bit Offset */ -#define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO0 Bit Mask */ -/* ADC14_HI0[HI0] Bits */ -#define ADC14_HI0_HI0_OFS ( 0) /*!< ADC14HI0 Bit Offset */ -#define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI0 Bit Mask */ -/* ADC14_LO1[LO1] Bits */ -#define ADC14_LO1_LO1_OFS ( 0) /*!< ADC14LO1 Bit Offset */ -#define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO1 Bit Mask */ -/* ADC14_HI1[HI1] Bits */ -#define ADC14_HI1_HI1_OFS ( 0) /*!< ADC14HI1 Bit Offset */ -#define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI1 Bit Mask */ -/* ADC14_MCTLN[INCH] Bits */ -#define ADC14_MCTLN_INCH_OFS ( 0) /*!< ADC14INCH Bit Offset */ -#define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /*!< ADC14INCH Bit Mask */ -#define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /*!< INCH Bit 0 */ -#define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /*!< INCH Bit 1 */ -#define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /*!< INCH Bit 2 */ -#define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /*!< INCH Bit 3 */ -#define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /*!< INCH Bit 4 */ -#define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -#define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -/* ADC14_MCTLN[EOS] Bits */ -#define ADC14_MCTLN_EOS_OFS ( 7) /*!< ADC14EOS Bit Offset */ -#define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /*!< End of sequence */ -/* ADC14_MCTLN[VRSEL] Bits */ -#define ADC14_MCTLN_VRSEL_OFS ( 8) /*!< ADC14VRSEL Bit Offset */ -#define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /*!< ADC14VRSEL Bit Mask */ -#define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /*!< VRSEL Bit 0 */ -#define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /*!< VRSEL Bit 1 */ -#define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /*!< VRSEL Bit 2 */ -#define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /*!< VRSEL Bit 3 */ -#define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /*!< V(R+) = AVCC, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /*!< V(R+) = VREF buffered, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /*!< V(R+) = VeREF+, V(R-) = VeREF- */ -#define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */ -/* ADC14_MCTLN[DIF] Bits */ -#define ADC14_MCTLN_DIF_OFS (13) /*!< ADC14DIF Bit Offset */ -#define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /*!< Differential mode */ -/* ADC14_MCTLN[WINC] Bits */ -#define ADC14_MCTLN_WINC_OFS (14) /*!< ADC14WINC Bit Offset */ -#define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /*!< Comparator window enable */ -/* ADC14_MCTLN[WINCTH] Bits */ -#define ADC14_MCTLN_WINCTH_OFS (15) /*!< ADC14WINCTH Bit Offset */ -#define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /*!< Window comparator threshold register selection */ -/* ADC14_MEMN[CONVRES] Bits */ -#define ADC14_MEMN_CONVRES_OFS ( 0) /*!< Conversion_Results Bit Offset */ -#define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /*!< Conversion_Results Bit Mask */ -/* ADC14_IER0[IE0] Bits */ -#define ADC14_IER0_IE0_OFS ( 0) /*!< ADC14IE0 Bit Offset */ -#define ADC14_IER0_IE0 ((uint32_t)0x00000001) /*!< Interrupt enable */ -/* ADC14_IER0[IE1] Bits */ -#define ADC14_IER0_IE1_OFS ( 1) /*!< ADC14IE1 Bit Offset */ -#define ADC14_IER0_IE1 ((uint32_t)0x00000002) /*!< Interrupt enable */ -/* ADC14_IER0[IE2] Bits */ -#define ADC14_IER0_IE2_OFS ( 2) /*!< ADC14IE2 Bit Offset */ -#define ADC14_IER0_IE2 ((uint32_t)0x00000004) /*!< Interrupt enable */ -/* ADC14_IER0[IE3] Bits */ -#define ADC14_IER0_IE3_OFS ( 3) /*!< ADC14IE3 Bit Offset */ -#define ADC14_IER0_IE3 ((uint32_t)0x00000008) /*!< Interrupt enable */ -/* ADC14_IER0[IE4] Bits */ -#define ADC14_IER0_IE4_OFS ( 4) /*!< ADC14IE4 Bit Offset */ -#define ADC14_IER0_IE4 ((uint32_t)0x00000010) /*!< Interrupt enable */ -/* ADC14_IER0[IE5] Bits */ -#define ADC14_IER0_IE5_OFS ( 5) /*!< ADC14IE5 Bit Offset */ -#define ADC14_IER0_IE5 ((uint32_t)0x00000020) /*!< Interrupt enable */ -/* ADC14_IER0[IE6] Bits */ -#define ADC14_IER0_IE6_OFS ( 6) /*!< ADC14IE6 Bit Offset */ -#define ADC14_IER0_IE6 ((uint32_t)0x00000040) /*!< Interrupt enable */ -/* ADC14_IER0[IE7] Bits */ -#define ADC14_IER0_IE7_OFS ( 7) /*!< ADC14IE7 Bit Offset */ -#define ADC14_IER0_IE7 ((uint32_t)0x00000080) /*!< Interrupt enable */ -/* ADC14_IER0[IE8] Bits */ -#define ADC14_IER0_IE8_OFS ( 8) /*!< ADC14IE8 Bit Offset */ -#define ADC14_IER0_IE8 ((uint32_t)0x00000100) /*!< Interrupt enable */ -/* ADC14_IER0[IE9] Bits */ -#define ADC14_IER0_IE9_OFS ( 9) /*!< ADC14IE9 Bit Offset */ -#define ADC14_IER0_IE9 ((uint32_t)0x00000200) /*!< Interrupt enable */ -/* ADC14_IER0[IE10] Bits */ -#define ADC14_IER0_IE10_OFS (10) /*!< ADC14IE10 Bit Offset */ -#define ADC14_IER0_IE10 ((uint32_t)0x00000400) /*!< Interrupt enable */ -/* ADC14_IER0[IE11] Bits */ -#define ADC14_IER0_IE11_OFS (11) /*!< ADC14IE11 Bit Offset */ -#define ADC14_IER0_IE11 ((uint32_t)0x00000800) /*!< Interrupt enable */ -/* ADC14_IER0[IE12] Bits */ -#define ADC14_IER0_IE12_OFS (12) /*!< ADC14IE12 Bit Offset */ -#define ADC14_IER0_IE12 ((uint32_t)0x00001000) /*!< Interrupt enable */ -/* ADC14_IER0[IE13] Bits */ -#define ADC14_IER0_IE13_OFS (13) /*!< ADC14IE13 Bit Offset */ -#define ADC14_IER0_IE13 ((uint32_t)0x00002000) /*!< Interrupt enable */ -/* ADC14_IER0[IE14] Bits */ -#define ADC14_IER0_IE14_OFS (14) /*!< ADC14IE14 Bit Offset */ -#define ADC14_IER0_IE14 ((uint32_t)0x00004000) /*!< Interrupt enable */ -/* ADC14_IER0[IE15] Bits */ -#define ADC14_IER0_IE15_OFS (15) /*!< ADC14IE15 Bit Offset */ -#define ADC14_IER0_IE15 ((uint32_t)0x00008000) /*!< Interrupt enable */ -/* ADC14_IER0[IE16] Bits */ -#define ADC14_IER0_IE16_OFS (16) /*!< ADC14IE16 Bit Offset */ -#define ADC14_IER0_IE16 ((uint32_t)0x00010000) /*!< Interrupt enable */ -/* ADC14_IER0[IE17] Bits */ -#define ADC14_IER0_IE17_OFS (17) /*!< ADC14IE17 Bit Offset */ -#define ADC14_IER0_IE17 ((uint32_t)0x00020000) /*!< Interrupt enable */ -/* ADC14_IER0[IE19] Bits */ -#define ADC14_IER0_IE19_OFS (19) /*!< ADC14IE19 Bit Offset */ -#define ADC14_IER0_IE19 ((uint32_t)0x00080000) /*!< Interrupt enable */ -/* ADC14_IER0[IE18] Bits */ -#define ADC14_IER0_IE18_OFS (18) /*!< ADC14IE18 Bit Offset */ -#define ADC14_IER0_IE18 ((uint32_t)0x00040000) /*!< Interrupt enable */ -/* ADC14_IER0[IE20] Bits */ -#define ADC14_IER0_IE20_OFS (20) /*!< ADC14IE20 Bit Offset */ -#define ADC14_IER0_IE20 ((uint32_t)0x00100000) /*!< Interrupt enable */ -/* ADC14_IER0[IE21] Bits */ -#define ADC14_IER0_IE21_OFS (21) /*!< ADC14IE21 Bit Offset */ -#define ADC14_IER0_IE21 ((uint32_t)0x00200000) /*!< Interrupt enable */ -/* ADC14_IER0[IE22] Bits */ -#define ADC14_IER0_IE22_OFS (22) /*!< ADC14IE22 Bit Offset */ -#define ADC14_IER0_IE22 ((uint32_t)0x00400000) /*!< Interrupt enable */ -/* ADC14_IER0[IE23] Bits */ -#define ADC14_IER0_IE23_OFS (23) /*!< ADC14IE23 Bit Offset */ -#define ADC14_IER0_IE23 ((uint32_t)0x00800000) /*!< Interrupt enable */ -/* ADC14_IER0[IE24] Bits */ -#define ADC14_IER0_IE24_OFS (24) /*!< ADC14IE24 Bit Offset */ -#define ADC14_IER0_IE24 ((uint32_t)0x01000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE25] Bits */ -#define ADC14_IER0_IE25_OFS (25) /*!< ADC14IE25 Bit Offset */ -#define ADC14_IER0_IE25 ((uint32_t)0x02000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE26] Bits */ -#define ADC14_IER0_IE26_OFS (26) /*!< ADC14IE26 Bit Offset */ -#define ADC14_IER0_IE26 ((uint32_t)0x04000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE27] Bits */ -#define ADC14_IER0_IE27_OFS (27) /*!< ADC14IE27 Bit Offset */ -#define ADC14_IER0_IE27 ((uint32_t)0x08000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE28] Bits */ -#define ADC14_IER0_IE28_OFS (28) /*!< ADC14IE28 Bit Offset */ -#define ADC14_IER0_IE28 ((uint32_t)0x10000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE29] Bits */ -#define ADC14_IER0_IE29_OFS (29) /*!< ADC14IE29 Bit Offset */ -#define ADC14_IER0_IE29 ((uint32_t)0x20000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE30] Bits */ -#define ADC14_IER0_IE30_OFS (30) /*!< ADC14IE30 Bit Offset */ -#define ADC14_IER0_IE30 ((uint32_t)0x40000000) /*!< Interrupt enable */ -/* ADC14_IER0[IE31] Bits */ -#define ADC14_IER0_IE31_OFS (31) /*!< ADC14IE31 Bit Offset */ -#define ADC14_IER0_IE31 ((uint32_t)0x80000000) /*!< Interrupt enable */ -/* ADC14_IER1[INIE] Bits */ -#define ADC14_IER1_INIE_OFS ( 1) /*!< ADC14INIE Bit Offset */ -#define ADC14_IER1_INIE ((uint32_t)0x00000002) /*!< Interrupt enable for ADC14MEMx within comparator window */ -/* ADC14_IER1[LOIE] Bits */ -#define ADC14_IER1_LOIE_OFS ( 2) /*!< ADC14LOIE Bit Offset */ -#define ADC14_IER1_LOIE ((uint32_t)0x00000004) /*!< Interrupt enable for ADC14MEMx below comparator window */ -/* ADC14_IER1[HIIE] Bits */ -#define ADC14_IER1_HIIE_OFS ( 3) /*!< ADC14HIIE Bit Offset */ -#define ADC14_IER1_HIIE ((uint32_t)0x00000008) /*!< Interrupt enable for ADC14MEMx above comparator window */ -/* ADC14_IER1[OVIE] Bits */ -#define ADC14_IER1_OVIE_OFS ( 4) /*!< ADC14OVIE Bit Offset */ -#define ADC14_IER1_OVIE ((uint32_t)0x00000010) /*!< ADC14MEMx overflow-interrupt enable */ -/* ADC14_IER1[TOVIE] Bits */ -#define ADC14_IER1_TOVIE_OFS ( 5) /*!< ADC14TOVIE Bit Offset */ -#define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /*!< ADC14 conversion-time-overflow interrupt enable */ -/* ADC14_IER1[RDYIE] Bits */ -#define ADC14_IER1_RDYIE_OFS ( 6) /*!< ADC14RDYIE Bit Offset */ -#define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt enable */ -/* ADC14_IFGR0[IFG0] Bits */ -#define ADC14_IFGR0_IFG0_OFS ( 0) /*!< ADC14IFG0 Bit Offset */ -#define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /*!< ADC14MEM0 interrupt flag */ -/* ADC14_IFGR0[IFG1] Bits */ -#define ADC14_IFGR0_IFG1_OFS ( 1) /*!< ADC14IFG1 Bit Offset */ -#define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /*!< ADC14MEM1 interrupt flag */ -/* ADC14_IFGR0[IFG2] Bits */ -#define ADC14_IFGR0_IFG2_OFS ( 2) /*!< ADC14IFG2 Bit Offset */ -#define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /*!< ADC14MEM2 interrupt flag */ -/* ADC14_IFGR0[IFG3] Bits */ -#define ADC14_IFGR0_IFG3_OFS ( 3) /*!< ADC14IFG3 Bit Offset */ -#define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /*!< ADC14MEM3 interrupt flag */ -/* ADC14_IFGR0[IFG4] Bits */ -#define ADC14_IFGR0_IFG4_OFS ( 4) /*!< ADC14IFG4 Bit Offset */ -#define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /*!< ADC14MEM4 interrupt flag */ -/* ADC14_IFGR0[IFG5] Bits */ -#define ADC14_IFGR0_IFG5_OFS ( 5) /*!< ADC14IFG5 Bit Offset */ -#define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /*!< ADC14MEM5 interrupt flag */ -/* ADC14_IFGR0[IFG6] Bits */ -#define ADC14_IFGR0_IFG6_OFS ( 6) /*!< ADC14IFG6 Bit Offset */ -#define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /*!< ADC14MEM6 interrupt flag */ -/* ADC14_IFGR0[IFG7] Bits */ -#define ADC14_IFGR0_IFG7_OFS ( 7) /*!< ADC14IFG7 Bit Offset */ -#define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /*!< ADC14MEM7 interrupt flag */ -/* ADC14_IFGR0[IFG8] Bits */ -#define ADC14_IFGR0_IFG8_OFS ( 8) /*!< ADC14IFG8 Bit Offset */ -#define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /*!< ADC14MEM8 interrupt flag */ -/* ADC14_IFGR0[IFG9] Bits */ -#define ADC14_IFGR0_IFG9_OFS ( 9) /*!< ADC14IFG9 Bit Offset */ -#define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /*!< ADC14MEM9 interrupt flag */ -/* ADC14_IFGR0[IFG10] Bits */ -#define ADC14_IFGR0_IFG10_OFS (10) /*!< ADC14IFG10 Bit Offset */ -#define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /*!< ADC14MEM10 interrupt flag */ -/* ADC14_IFGR0[IFG11] Bits */ -#define ADC14_IFGR0_IFG11_OFS (11) /*!< ADC14IFG11 Bit Offset */ -#define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /*!< ADC14MEM11 interrupt flag */ -/* ADC14_IFGR0[IFG12] Bits */ -#define ADC14_IFGR0_IFG12_OFS (12) /*!< ADC14IFG12 Bit Offset */ -#define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /*!< ADC14MEM12 interrupt flag */ -/* ADC14_IFGR0[IFG13] Bits */ -#define ADC14_IFGR0_IFG13_OFS (13) /*!< ADC14IFG13 Bit Offset */ -#define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /*!< ADC14MEM13 interrupt flag */ -/* ADC14_IFGR0[IFG14] Bits */ -#define ADC14_IFGR0_IFG14_OFS (14) /*!< ADC14IFG14 Bit Offset */ -#define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /*!< ADC14MEM14 interrupt flag */ -/* ADC14_IFGR0[IFG15] Bits */ -#define ADC14_IFGR0_IFG15_OFS (15) /*!< ADC14IFG15 Bit Offset */ -#define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /*!< ADC14MEM15 interrupt flag */ -/* ADC14_IFGR0[IFG16] Bits */ -#define ADC14_IFGR0_IFG16_OFS (16) /*!< ADC14IFG16 Bit Offset */ -#define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /*!< ADC14MEM16 interrupt flag */ -/* ADC14_IFGR0[IFG17] Bits */ -#define ADC14_IFGR0_IFG17_OFS (17) /*!< ADC14IFG17 Bit Offset */ -#define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /*!< ADC14MEM17 interrupt flag */ -/* ADC14_IFGR0[IFG18] Bits */ -#define ADC14_IFGR0_IFG18_OFS (18) /*!< ADC14IFG18 Bit Offset */ -#define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /*!< ADC14MEM18 interrupt flag */ -/* ADC14_IFGR0[IFG19] Bits */ -#define ADC14_IFGR0_IFG19_OFS (19) /*!< ADC14IFG19 Bit Offset */ -#define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /*!< ADC14MEM19 interrupt flag */ -/* ADC14_IFGR0[IFG20] Bits */ -#define ADC14_IFGR0_IFG20_OFS (20) /*!< ADC14IFG20 Bit Offset */ -#define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /*!< ADC14MEM20 interrupt flag */ -/* ADC14_IFGR0[IFG21] Bits */ -#define ADC14_IFGR0_IFG21_OFS (21) /*!< ADC14IFG21 Bit Offset */ -#define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /*!< ADC14MEM21 interrupt flag */ -/* ADC14_IFGR0[IFG22] Bits */ -#define ADC14_IFGR0_IFG22_OFS (22) /*!< ADC14IFG22 Bit Offset */ -#define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /*!< ADC14MEM22 interrupt flag */ -/* ADC14_IFGR0[IFG23] Bits */ -#define ADC14_IFGR0_IFG23_OFS (23) /*!< ADC14IFG23 Bit Offset */ -#define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /*!< ADC14MEM23 interrupt flag */ -/* ADC14_IFGR0[IFG24] Bits */ -#define ADC14_IFGR0_IFG24_OFS (24) /*!< ADC14IFG24 Bit Offset */ -#define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /*!< ADC14MEM24 interrupt flag */ -/* ADC14_IFGR0[IFG25] Bits */ -#define ADC14_IFGR0_IFG25_OFS (25) /*!< ADC14IFG25 Bit Offset */ -#define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /*!< ADC14MEM25 interrupt flag */ -/* ADC14_IFGR0[IFG26] Bits */ -#define ADC14_IFGR0_IFG26_OFS (26) /*!< ADC14IFG26 Bit Offset */ -#define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /*!< ADC14MEM26 interrupt flag */ -/* ADC14_IFGR0[IFG27] Bits */ -#define ADC14_IFGR0_IFG27_OFS (27) /*!< ADC14IFG27 Bit Offset */ -#define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /*!< ADC14MEM27 interrupt flag */ -/* ADC14_IFGR0[IFG28] Bits */ -#define ADC14_IFGR0_IFG28_OFS (28) /*!< ADC14IFG28 Bit Offset */ -#define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /*!< ADC14MEM28 interrupt flag */ -/* ADC14_IFGR0[IFG29] Bits */ -#define ADC14_IFGR0_IFG29_OFS (29) /*!< ADC14IFG29 Bit Offset */ -#define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /*!< ADC14MEM29 interrupt flag */ -/* ADC14_IFGR0[IFG30] Bits */ -#define ADC14_IFGR0_IFG30_OFS (30) /*!< ADC14IFG30 Bit Offset */ -#define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /*!< ADC14MEM30 interrupt flag */ -/* ADC14_IFGR0[IFG31] Bits */ -#define ADC14_IFGR0_IFG31_OFS (31) /*!< ADC14IFG31 Bit Offset */ -#define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /*!< ADC14MEM31 interrupt flag */ -/* ADC14_IFGR1[INIFG] Bits */ -#define ADC14_IFGR1_INIFG_OFS ( 1) /*!< ADC14INIFG Bit Offset */ -#define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /*!< Interrupt flag for ADC14MEMx within comparator window */ -/* ADC14_IFGR1[LOIFG] Bits */ -#define ADC14_IFGR1_LOIFG_OFS ( 2) /*!< ADC14LOIFG Bit Offset */ -#define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /*!< Interrupt flag for ADC14MEMx below comparator window */ -/* ADC14_IFGR1[HIIFG] Bits */ -#define ADC14_IFGR1_HIIFG_OFS ( 3) /*!< ADC14HIIFG Bit Offset */ -#define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /*!< Interrupt flag for ADC14MEMx above comparator window */ -/* ADC14_IFGR1[OVIFG] Bits */ -#define ADC14_IFGR1_OVIFG_OFS ( 4) /*!< ADC14OVIFG Bit Offset */ -#define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /*!< ADC14MEMx overflow interrupt flag */ -/* ADC14_IFGR1[TOVIFG] Bits */ -#define ADC14_IFGR1_TOVIFG_OFS ( 5) /*!< ADC14TOVIFG Bit Offset */ -#define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /*!< ADC14 conversion time overflow interrupt flag */ -/* ADC14_IFGR1[RDYIFG] Bits */ -#define ADC14_IFGR1_RDYIFG_OFS ( 6) /*!< ADC14RDYIFG Bit Offset */ -#define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt flag */ -/* ADC14_CLRIFGR0[CLRIFG0] Bits */ -#define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /*!< CLRADC14IFG0 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /*!< clear ADC14IFG0 */ -/* ADC14_CLRIFGR0[CLRIFG1] Bits */ -#define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /*!< CLRADC14IFG1 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /*!< clear ADC14IFG1 */ -/* ADC14_CLRIFGR0[CLRIFG2] Bits */ -#define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /*!< CLRADC14IFG2 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /*!< clear ADC14IFG2 */ -/* ADC14_CLRIFGR0[CLRIFG3] Bits */ -#define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /*!< CLRADC14IFG3 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /*!< clear ADC14IFG3 */ -/* ADC14_CLRIFGR0[CLRIFG4] Bits */ -#define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /*!< CLRADC14IFG4 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /*!< clear ADC14IFG4 */ -/* ADC14_CLRIFGR0[CLRIFG5] Bits */ -#define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /*!< CLRADC14IFG5 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /*!< clear ADC14IFG5 */ -/* ADC14_CLRIFGR0[CLRIFG6] Bits */ -#define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /*!< CLRADC14IFG6 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /*!< clear ADC14IFG6 */ -/* ADC14_CLRIFGR0[CLRIFG7] Bits */ -#define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /*!< CLRADC14IFG7 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /*!< clear ADC14IFG7 */ -/* ADC14_CLRIFGR0[CLRIFG8] Bits */ -#define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /*!< CLRADC14IFG8 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /*!< clear ADC14IFG8 */ -/* ADC14_CLRIFGR0[CLRIFG9] Bits */ -#define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /*!< CLRADC14IFG9 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /*!< clear ADC14IFG9 */ -/* ADC14_CLRIFGR0[CLRIFG10] Bits */ -#define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /*!< CLRADC14IFG10 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /*!< clear ADC14IFG10 */ -/* ADC14_CLRIFGR0[CLRIFG11] Bits */ -#define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /*!< CLRADC14IFG11 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /*!< clear ADC14IFG11 */ -/* ADC14_CLRIFGR0[CLRIFG12] Bits */ -#define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /*!< CLRADC14IFG12 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /*!< clear ADC14IFG12 */ -/* ADC14_CLRIFGR0[CLRIFG13] Bits */ -#define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /*!< CLRADC14IFG13 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /*!< clear ADC14IFG13 */ -/* ADC14_CLRIFGR0[CLRIFG14] Bits */ -#define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /*!< CLRADC14IFG14 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /*!< clear ADC14IFG14 */ -/* ADC14_CLRIFGR0[CLRIFG15] Bits */ -#define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /*!< CLRADC14IFG15 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /*!< clear ADC14IFG15 */ -/* ADC14_CLRIFGR0[CLRIFG16] Bits */ -#define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /*!< CLRADC14IFG16 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /*!< clear ADC14IFG16 */ -/* ADC14_CLRIFGR0[CLRIFG17] Bits */ -#define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /*!< CLRADC14IFG17 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /*!< clear ADC14IFG17 */ -/* ADC14_CLRIFGR0[CLRIFG18] Bits */ -#define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /*!< CLRADC14IFG18 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /*!< clear ADC14IFG18 */ -/* ADC14_CLRIFGR0[CLRIFG19] Bits */ -#define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /*!< CLRADC14IFG19 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /*!< clear ADC14IFG19 */ -/* ADC14_CLRIFGR0[CLRIFG20] Bits */ -#define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /*!< CLRADC14IFG20 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /*!< clear ADC14IFG20 */ -/* ADC14_CLRIFGR0[CLRIFG21] Bits */ -#define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /*!< CLRADC14IFG21 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /*!< clear ADC14IFG21 */ -/* ADC14_CLRIFGR0[CLRIFG22] Bits */ -#define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /*!< CLRADC14IFG22 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /*!< clear ADC14IFG22 */ -/* ADC14_CLRIFGR0[CLRIFG23] Bits */ -#define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /*!< CLRADC14IFG23 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /*!< clear ADC14IFG23 */ -/* ADC14_CLRIFGR0[CLRIFG24] Bits */ -#define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /*!< CLRADC14IFG24 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /*!< clear ADC14IFG24 */ -/* ADC14_CLRIFGR0[CLRIFG25] Bits */ -#define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /*!< CLRADC14IFG25 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /*!< clear ADC14IFG25 */ -/* ADC14_CLRIFGR0[CLRIFG26] Bits */ -#define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /*!< CLRADC14IFG26 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /*!< clear ADC14IFG26 */ -/* ADC14_CLRIFGR0[CLRIFG27] Bits */ -#define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /*!< CLRADC14IFG27 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /*!< clear ADC14IFG27 */ -/* ADC14_CLRIFGR0[CLRIFG28] Bits */ -#define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /*!< CLRADC14IFG28 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /*!< clear ADC14IFG28 */ -/* ADC14_CLRIFGR0[CLRIFG29] Bits */ -#define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /*!< CLRADC14IFG29 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /*!< clear ADC14IFG29 */ -/* ADC14_CLRIFGR0[CLRIFG30] Bits */ -#define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /*!< CLRADC14IFG30 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /*!< clear ADC14IFG30 */ -/* ADC14_CLRIFGR0[CLRIFG31] Bits */ -#define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /*!< CLRADC14IFG31 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /*!< clear ADC14IFG31 */ -/* ADC14_CLRIFGR1[CLRINIFG] Bits */ -#define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /*!< CLRADC14INIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /*!< clear ADC14INIFG */ -/* ADC14_CLRIFGR1[CLRLOIFG] Bits */ -#define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /*!< CLRADC14LOIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /*!< clear ADC14LOIFG */ -/* ADC14_CLRIFGR1[CLRHIIFG] Bits */ -#define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /*!< CLRADC14HIIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /*!< clear ADC14HIIFG */ -/* ADC14_CLRIFGR1[CLROVIFG] Bits */ -#define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /*!< CLRADC14OVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /*!< clear ADC14OVIFG */ -/* ADC14_CLRIFGR1[CLRTOVIFG] Bits */ -#define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /*!< CLRADC14TOVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /*!< clear ADC14TOVIFG */ -/* ADC14_CLRIFGR1[CLRRDYIFG] Bits */ -#define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /*!< CLRADC14RDYIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /*!< clear ADC14RDYIFG */ - -/****************************************************************************** -* AES256 Bits -******************************************************************************/ -/* AES256_CTL0[OP] Bits */ -#define AES256_CTL0_OP_OFS ( 0) /*!< AESOPx Bit Offset */ -#define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /*!< AESOPx Bit Mask */ -#define AES256_CTL0_OP0 ((uint16_t)0x0001) /*!< OP Bit 0 */ -#define AES256_CTL0_OP1 ((uint16_t)0x0002) /*!< OP Bit 1 */ -#define AES256_CTL0_OP_0 ((uint16_t)0x0000) /*!< Encryption */ -#define AES256_CTL0_OP_1 ((uint16_t)0x0001) /*!< Decryption. The provided key is the same key used for encryption */ -#define AES256_CTL0_OP_2 ((uint16_t)0x0002) /*!< Generate first round key required for decryption */ -#define AES256_CTL0_OP_3 ((uint16_t)0x0003) /*!< Decryption. The provided key is the first round key required for decryption */ -/* AES256_CTL0[KL] Bits */ -#define AES256_CTL0_KL_OFS ( 2) /*!< AESKLx Bit Offset */ -#define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /*!< AESKLx Bit Mask */ -#define AES256_CTL0_KL0 ((uint16_t)0x0004) /*!< KL Bit 0 */ -#define AES256_CTL0_KL1 ((uint16_t)0x0008) /*!< KL Bit 1 */ -#define AES256_CTL0_KL_0 ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL_1 ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL_2 ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -#define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -/* AES256_CTL0[CM] Bits */ -#define AES256_CTL0_CM_OFS ( 5) /*!< AESCMx Bit Offset */ -#define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /*!< AESCMx Bit Mask */ -#define AES256_CTL0_CM0 ((uint16_t)0x0020) /*!< CM Bit 0 */ -#define AES256_CTL0_CM1 ((uint16_t)0x0040) /*!< CM Bit 1 */ -#define AES256_CTL0_CM_0 ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM_1 ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM_2 ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM_3 ((uint16_t)0x0060) /*!< CFB */ -#define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /*!< CFB */ -/* AES256_CTL0[SWRST] Bits */ -#define AES256_CTL0_SWRST_OFS ( 7) /*!< AESSWRST Bit Offset */ -#define AES256_CTL0_SWRST ((uint16_t)0x0080) /*!< AES software reset */ -/* AES256_CTL0[RDYIFG] Bits */ -#define AES256_CTL0_RDYIFG_OFS ( 8) /*!< AESRDYIFG Bit Offset */ -#define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /*!< AES ready interrupt flag */ -/* AES256_CTL0[ERRFG] Bits */ -#define AES256_CTL0_ERRFG_OFS (11) /*!< AESERRFG Bit Offset */ -#define AES256_CTL0_ERRFG ((uint16_t)0x0800) /*!< AES error flag */ -/* AES256_CTL0[RDYIE] Bits */ -#define AES256_CTL0_RDYIE_OFS (12) /*!< AESRDYIE Bit Offset */ -#define AES256_CTL0_RDYIE ((uint16_t)0x1000) /*!< AES ready interrupt enable */ -/* AES256_CTL0[CMEN] Bits */ -#define AES256_CTL0_CMEN_OFS (15) /*!< AESCMEN Bit Offset */ -#define AES256_CTL0_CMEN ((uint16_t)0x8000) /*!< AES cipher mode enable */ -/* AES256_CTL1[BLKCNT] Bits */ -#define AES256_CTL1_BLKCNT_OFS ( 0) /*!< AESBLKCNTx Bit Offset */ -#define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /*!< AESBLKCNTx Bit Mask */ -#define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /*!< BLKCNT Bit 0 */ -#define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /*!< BLKCNT Bit 1 */ -#define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /*!< BLKCNT Bit 2 */ -#define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /*!< BLKCNT Bit 3 */ -#define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /*!< BLKCNT Bit 4 */ -#define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /*!< BLKCNT Bit 5 */ -#define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /*!< BLKCNT Bit 6 */ -#define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /*!< BLKCNT Bit 7 */ -/* AES256_STAT[BUSY] Bits */ -#define AES256_STAT_BUSY_OFS ( 0) /*!< AESBUSY Bit Offset */ -#define AES256_STAT_BUSY ((uint16_t)0x0001) /*!< AES accelerator module busy */ -/* AES256_STAT[KEYWR] Bits */ -#define AES256_STAT_KEYWR_OFS ( 1) /*!< AESKEYWR Bit Offset */ -#define AES256_STAT_KEYWR ((uint16_t)0x0002) /*!< All 16 bytes written to AESAKEY */ -/* AES256_STAT[DINWR] Bits */ -#define AES256_STAT_DINWR_OFS ( 2) /*!< AESDINWR Bit Offset */ -#define AES256_STAT_DINWR ((uint16_t)0x0004) /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ -/* AES256_STAT[DOUTRD] Bits */ -#define AES256_STAT_DOUTRD_OFS ( 3) /*!< AESDOUTRD Bit Offset */ -#define AES256_STAT_DOUTRD ((uint16_t)0x0008) /*!< All 16 bytes read from AESADOUT */ -/* AES256_STAT[KEYCNT] Bits */ -#define AES256_STAT_KEYCNT_OFS ( 4) /*!< AESKEYCNTx Bit Offset */ -#define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /*!< AESKEYCNTx Bit Mask */ -#define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /*!< KEYCNT Bit 0 */ -#define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /*!< KEYCNT Bit 1 */ -#define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /*!< KEYCNT Bit 2 */ -#define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /*!< KEYCNT Bit 3 */ -/* AES256_STAT[DINCNT] Bits */ -#define AES256_STAT_DINCNT_OFS ( 8) /*!< AESDINCNTx Bit Offset */ -#define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /*!< AESDINCNTx Bit Mask */ -#define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /*!< DINCNT Bit 0 */ -#define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /*!< DINCNT Bit 1 */ -#define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /*!< DINCNT Bit 2 */ -#define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /*!< DINCNT Bit 3 */ -/* AES256_STAT[DOUTCNT] Bits */ -#define AES256_STAT_DOUTCNT_OFS (12) /*!< AESDOUTCNTx Bit Offset */ -#define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /*!< AESDOUTCNTx Bit Mask */ -#define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /*!< DOUTCNT Bit 0 */ -#define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /*!< DOUTCNT Bit 1 */ -#define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /*!< DOUTCNT Bit 2 */ -#define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /*!< DOUTCNT Bit 3 */ -/* AES256_KEY[KEY0] Bits */ -#define AES256_KEY_KEY0_OFS ( 0) /*!< AESKEY0x Bit Offset */ -#define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /*!< AESKEY0x Bit Mask */ -#define AES256_KEY_KEY00 ((uint16_t)0x0001) /*!< KEY0 Bit 0 */ -#define AES256_KEY_KEY01 ((uint16_t)0x0002) /*!< KEY0 Bit 1 */ -#define AES256_KEY_KEY02 ((uint16_t)0x0004) /*!< KEY0 Bit 2 */ -#define AES256_KEY_KEY03 ((uint16_t)0x0008) /*!< KEY0 Bit 3 */ -#define AES256_KEY_KEY04 ((uint16_t)0x0010) /*!< KEY0 Bit 4 */ -#define AES256_KEY_KEY05 ((uint16_t)0x0020) /*!< KEY0 Bit 5 */ -#define AES256_KEY_KEY06 ((uint16_t)0x0040) /*!< KEY0 Bit 6 */ -#define AES256_KEY_KEY07 ((uint16_t)0x0080) /*!< KEY0 Bit 7 */ -/* AES256_KEY[KEY1] Bits */ -#define AES256_KEY_KEY1_OFS ( 8) /*!< AESKEY1x Bit Offset */ -#define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /*!< AESKEY1x Bit Mask */ -#define AES256_KEY_KEY10 ((uint16_t)0x0100) /*!< KEY1 Bit 0 */ -#define AES256_KEY_KEY11 ((uint16_t)0x0200) /*!< KEY1 Bit 1 */ -#define AES256_KEY_KEY12 ((uint16_t)0x0400) /*!< KEY1 Bit 2 */ -#define AES256_KEY_KEY13 ((uint16_t)0x0800) /*!< KEY1 Bit 3 */ -#define AES256_KEY_KEY14 ((uint16_t)0x1000) /*!< KEY1 Bit 4 */ -#define AES256_KEY_KEY15 ((uint16_t)0x2000) /*!< KEY1 Bit 5 */ -#define AES256_KEY_KEY16 ((uint16_t)0x4000) /*!< KEY1 Bit 6 */ -#define AES256_KEY_KEY17 ((uint16_t)0x8000) /*!< KEY1 Bit 7 */ -/* AES256_DIN[DIN0] Bits */ -#define AES256_DIN_DIN0_OFS ( 0) /*!< AESDIN0x Bit Offset */ -#define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /*!< AESDIN0x Bit Mask */ -#define AES256_DIN_DIN00 ((uint16_t)0x0001) /*!< DIN0 Bit 0 */ -#define AES256_DIN_DIN01 ((uint16_t)0x0002) /*!< DIN0 Bit 1 */ -#define AES256_DIN_DIN02 ((uint16_t)0x0004) /*!< DIN0 Bit 2 */ -#define AES256_DIN_DIN03 ((uint16_t)0x0008) /*!< DIN0 Bit 3 */ -#define AES256_DIN_DIN04 ((uint16_t)0x0010) /*!< DIN0 Bit 4 */ -#define AES256_DIN_DIN05 ((uint16_t)0x0020) /*!< DIN0 Bit 5 */ -#define AES256_DIN_DIN06 ((uint16_t)0x0040) /*!< DIN0 Bit 6 */ -#define AES256_DIN_DIN07 ((uint16_t)0x0080) /*!< DIN0 Bit 7 */ -/* AES256_DIN[DIN1] Bits */ -#define AES256_DIN_DIN1_OFS ( 8) /*!< AESDIN1x Bit Offset */ -#define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /*!< AESDIN1x Bit Mask */ -#define AES256_DIN_DIN10 ((uint16_t)0x0100) /*!< DIN1 Bit 0 */ -#define AES256_DIN_DIN11 ((uint16_t)0x0200) /*!< DIN1 Bit 1 */ -#define AES256_DIN_DIN12 ((uint16_t)0x0400) /*!< DIN1 Bit 2 */ -#define AES256_DIN_DIN13 ((uint16_t)0x0800) /*!< DIN1 Bit 3 */ -#define AES256_DIN_DIN14 ((uint16_t)0x1000) /*!< DIN1 Bit 4 */ -#define AES256_DIN_DIN15 ((uint16_t)0x2000) /*!< DIN1 Bit 5 */ -#define AES256_DIN_DIN16 ((uint16_t)0x4000) /*!< DIN1 Bit 6 */ -#define AES256_DIN_DIN17 ((uint16_t)0x8000) /*!< DIN1 Bit 7 */ -/* AES256_DOUT[DOUT0] Bits */ -#define AES256_DOUT_DOUT0_OFS ( 0) /*!< AESDOUT0x Bit Offset */ -#define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /*!< AESDOUT0x Bit Mask */ -#define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /*!< DOUT0 Bit 0 */ -#define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /*!< DOUT0 Bit 1 */ -#define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /*!< DOUT0 Bit 2 */ -#define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /*!< DOUT0 Bit 3 */ -#define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /*!< DOUT0 Bit 4 */ -#define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /*!< DOUT0 Bit 5 */ -#define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /*!< DOUT0 Bit 6 */ -#define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /*!< DOUT0 Bit 7 */ -/* AES256_DOUT[DOUT1] Bits */ -#define AES256_DOUT_DOUT1_OFS ( 8) /*!< AESDOUT1x Bit Offset */ -#define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /*!< AESDOUT1x Bit Mask */ -#define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /*!< DOUT1 Bit 0 */ -#define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /*!< DOUT1 Bit 1 */ -#define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /*!< DOUT1 Bit 2 */ -#define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /*!< DOUT1 Bit 3 */ -#define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /*!< DOUT1 Bit 4 */ -#define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /*!< DOUT1 Bit 5 */ -#define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /*!< DOUT1 Bit 6 */ -#define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /*!< DOUT1 Bit 7 */ -/* AES256_XDIN[XDIN0] Bits */ -#define AES256_XDIN_XDIN0_OFS ( 0) /*!< AESXDIN0x Bit Offset */ -#define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /*!< AESXDIN0x Bit Mask */ -#define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /*!< XDIN0 Bit 0 */ -#define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /*!< XDIN0 Bit 1 */ -#define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /*!< XDIN0 Bit 2 */ -#define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /*!< XDIN0 Bit 3 */ -#define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /*!< XDIN0 Bit 4 */ -#define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /*!< XDIN0 Bit 5 */ -#define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /*!< XDIN0 Bit 6 */ -#define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /*!< XDIN0 Bit 7 */ -/* AES256_XDIN[XDIN1] Bits */ -#define AES256_XDIN_XDIN1_OFS ( 8) /*!< AESXDIN1x Bit Offset */ -#define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /*!< AESXDIN1x Bit Mask */ -#define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /*!< XDIN1 Bit 0 */ -#define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /*!< XDIN1 Bit 1 */ -#define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /*!< XDIN1 Bit 2 */ -#define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /*!< XDIN1 Bit 3 */ -#define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /*!< XDIN1 Bit 4 */ -#define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /*!< XDIN1 Bit 5 */ -#define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /*!< XDIN1 Bit 6 */ -#define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /*!< XDIN1 Bit 7 */ -/* AES256_XIN[XIN0] Bits */ -#define AES256_XIN_XIN0_OFS ( 0) /*!< AESXIN0x Bit Offset */ -#define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /*!< AESXIN0x Bit Mask */ -#define AES256_XIN_XIN00 ((uint16_t)0x0001) /*!< XIN0 Bit 0 */ -#define AES256_XIN_XIN01 ((uint16_t)0x0002) /*!< XIN0 Bit 1 */ -#define AES256_XIN_XIN02 ((uint16_t)0x0004) /*!< XIN0 Bit 2 */ -#define AES256_XIN_XIN03 ((uint16_t)0x0008) /*!< XIN0 Bit 3 */ -#define AES256_XIN_XIN04 ((uint16_t)0x0010) /*!< XIN0 Bit 4 */ -#define AES256_XIN_XIN05 ((uint16_t)0x0020) /*!< XIN0 Bit 5 */ -#define AES256_XIN_XIN06 ((uint16_t)0x0040) /*!< XIN0 Bit 6 */ -#define AES256_XIN_XIN07 ((uint16_t)0x0080) /*!< XIN0 Bit 7 */ -/* AES256_XIN[XIN1] Bits */ -#define AES256_XIN_XIN1_OFS ( 8) /*!< AESXIN1x Bit Offset */ -#define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /*!< AESXIN1x Bit Mask */ -#define AES256_XIN_XIN10 ((uint16_t)0x0100) /*!< XIN1 Bit 0 */ -#define AES256_XIN_XIN11 ((uint16_t)0x0200) /*!< XIN1 Bit 1 */ -#define AES256_XIN_XIN12 ((uint16_t)0x0400) /*!< XIN1 Bit 2 */ -#define AES256_XIN_XIN13 ((uint16_t)0x0800) /*!< XIN1 Bit 3 */ -#define AES256_XIN_XIN14 ((uint16_t)0x1000) /*!< XIN1 Bit 4 */ -#define AES256_XIN_XIN15 ((uint16_t)0x2000) /*!< XIN1 Bit 5 */ -#define AES256_XIN_XIN16 ((uint16_t)0x4000) /*!< XIN1 Bit 6 */ -#define AES256_XIN_XIN17 ((uint16_t)0x8000) /*!< XIN1 Bit 7 */ - -/****************************************************************************** -* CAPTIO Bits -******************************************************************************/ -/* CAPTIO_CTL[PISEL] Bits */ -#define CAPTIO_CTL_PISEL_OFS ( 1) /*!< CAPTIOPISELx Bit Offset */ -#define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /*!< CAPTIOPISELx Bit Mask */ -#define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /*!< PISEL Bit 0 */ -#define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /*!< PISEL Bit 1 */ -#define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /*!< PISEL Bit 2 */ -#define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /*!< Px.0 */ -#define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /*!< Px.1 */ -#define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /*!< Px.2 */ -#define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /*!< Px.3 */ -#define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /*!< Px.4 */ -#define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /*!< Px.5 */ -#define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /*!< Px.6 */ -#define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /*!< Px.7 */ -/* CAPTIO_CTL[POSEL] Bits */ -#define CAPTIO_CTL_POSEL_OFS ( 4) /*!< CAPTIOPOSELx Bit Offset */ -#define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /*!< CAPTIOPOSELx Bit Mask */ -#define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /*!< POSEL Bit 0 */ -#define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /*!< POSEL Bit 1 */ -#define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /*!< POSEL Bit 2 */ -#define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /*!< POSEL Bit 3 */ -#define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /*!< Px = P15 */ -#define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /*!< Px = P15 */ -/* CAPTIO_CTL[EN] Bits */ -#define CAPTIO_CTL_EN_OFS ( 8) /*!< CAPTIOEN Bit Offset */ -#define CAPTIO_CTL_EN ((uint16_t)0x0100) /*!< Capacitive Touch IO enable */ -/* CAPTIO_CTL[STATE] Bits */ -#define CAPTIO_CTL_STATE_OFS ( 9) /*!< CAPTIOSTATE Bit Offset */ -#define CAPTIO_CTL_STATE ((uint16_t)0x0200) /*!< Capacitive Touch IO state */ - -/****************************************************************************** -* COMP_E Bits -******************************************************************************/ -/* COMP_E_CTL0[IPSEL] Bits */ -#define COMP_E_CTL0_IPSEL_OFS ( 0) /*!< CEIPSEL Bit Offset */ -#define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /*!< CEIPSEL Bit Mask */ -#define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /*!< IPSEL Bit 0 */ -#define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /*!< IPSEL Bit 1 */ -#define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /*!< IPSEL Bit 2 */ -#define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /*!< IPSEL Bit 3 */ -#define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /*!< Channel 15 selected */ -/* COMP_E_CTL0[IPEN] Bits */ -#define COMP_E_CTL0_IPEN_OFS ( 7) /*!< CEIPEN Bit Offset */ -#define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /*!< Channel input enable for the V+ terminal */ -/* COMP_E_CTL0[IMSEL] Bits */ -#define COMP_E_CTL0_IMSEL_OFS ( 8) /*!< CEIMSEL Bit Offset */ -#define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /*!< CEIMSEL Bit Mask */ -#define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /*!< IMSEL Bit 0 */ -#define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /*!< IMSEL Bit 1 */ -#define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /*!< IMSEL Bit 2 */ -#define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /*!< IMSEL Bit 3 */ -#define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /*!< Channel 15 selected */ -/* COMP_E_CTL0[IMEN] Bits */ -#define COMP_E_CTL0_IMEN_OFS (15) /*!< CEIMEN Bit Offset */ -#define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /*!< Channel input enable for the - terminal */ -/* COMP_E_CTL1[OUT] Bits */ -#define COMP_E_CTL1_OUT_OFS ( 0) /*!< CEOUT Bit Offset */ -#define COMP_E_CTL1_OUT ((uint16_t)0x0001) /*!< Comparator output value */ -/* COMP_E_CTL1[OUTPOL] Bits */ -#define COMP_E_CTL1_OUTPOL_OFS ( 1) /*!< CEOUTPOL Bit Offset */ -#define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /*!< Comparator output polarity */ -/* COMP_E_CTL1[F] Bits */ -#define COMP_E_CTL1_F_OFS ( 2) /*!< CEF Bit Offset */ -#define COMP_E_CTL1_F ((uint16_t)0x0004) /*!< Comparator output filter */ -/* COMP_E_CTL1[IES] Bits */ -#define COMP_E_CTL1_IES_OFS ( 3) /*!< CEIES Bit Offset */ -#define COMP_E_CTL1_IES ((uint16_t)0x0008) /*!< Interrupt edge select for CEIIFG and CEIFG */ -/* COMP_E_CTL1[SHORT] Bits */ -#define COMP_E_CTL1_SHORT_OFS ( 4) /*!< CESHORT Bit Offset */ -#define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /*!< Input short */ -/* COMP_E_CTL1[EX] Bits */ -#define COMP_E_CTL1_EX_OFS ( 5) /*!< CEEX Bit Offset */ -#define COMP_E_CTL1_EX ((uint16_t)0x0020) /*!< Exchange */ -/* COMP_E_CTL1[FDLY] Bits */ -#define COMP_E_CTL1_FDLY_OFS ( 6) /*!< CEFDLY Bit Offset */ -#define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /*!< CEFDLY Bit Mask */ -#define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /*!< FDLY Bit 0 */ -#define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /*!< FDLY Bit 1 */ -#define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /*!< Typical filter delay of TBD (450) ns */ -#define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /*!< Typical filter delay of TBD (900) ns */ -#define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /*!< Typical filter delay of TBD (1800) ns */ -#define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /*!< Typical filter delay of TBD (3600) ns */ -/* COMP_E_CTL1[PWRMD] Bits */ -#define COMP_E_CTL1_PWRMD_OFS ( 8) /*!< CEPWRMD Bit Offset */ -#define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /*!< CEPWRMD Bit Mask */ -#define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /*!< PWRMD Bit 0 */ -#define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /*!< PWRMD Bit 1 */ -#define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /*!< High-speed mode */ -#define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /*!< Normal mode */ -#define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /*!< Ultra-low power mode */ -/* COMP_E_CTL1[ON] Bits */ -#define COMP_E_CTL1_ON_OFS (10) /*!< CEON Bit Offset */ -#define COMP_E_CTL1_ON ((uint16_t)0x0400) /*!< Comparator On */ -/* COMP_E_CTL1[MRVL] Bits */ -#define COMP_E_CTL1_MRVL_OFS (11) /*!< CEMRVL Bit Offset */ -#define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /*!< This bit is valid of CEMRVS is set to 1 */ -/* COMP_E_CTL1[MRVS] Bits */ -#define COMP_E_CTL1_MRVS_OFS (12) /*!< CEMRVS Bit Offset */ -#define COMP_E_CTL1_MRVS ((uint16_t)0x1000) -/* COMP_E_CTL2[REF0] Bits */ -#define COMP_E_CTL2_REF0_OFS ( 0) /*!< CEREF0 Bit Offset */ -#define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /*!< CEREF0 Bit Mask */ -/* COMP_E_CTL2[RSEL] Bits */ -#define COMP_E_CTL2_RSEL_OFS ( 5) /*!< CERSEL Bit Offset */ -#define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /*!< Reference select */ -/* COMP_E_CTL2[RS] Bits */ -#define COMP_E_CTL2_RS_OFS ( 6) /*!< CERS Bit Offset */ -#define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /*!< CERS Bit Mask */ -#define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /*!< RS Bit 0 */ -#define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /*!< RS Bit 1 */ -#define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /*!< No current is drawn by the reference circuitry */ -#define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /*!< VCC applied to the resistor ladder */ -#define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /*!< Shared reference voltage applied to the resistor ladder */ -#define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ -/* COMP_E_CTL2[REF1] Bits */ -#define COMP_E_CTL2_REF1_OFS ( 8) /*!< CEREF1 Bit Offset */ -#define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /*!< CEREF1 Bit Mask */ -/* COMP_E_CTL2[REFL] Bits */ -#define COMP_E_CTL2_REFL_OFS (13) /*!< CEREFL Bit Offset */ -#define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /*!< CEREFL Bit Mask */ -#define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /*!< REFL Bit 0 */ -#define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /*!< REFL Bit 1 */ -#define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -/* COMP_E_CTL2[REFACC] Bits */ -#define COMP_E_CTL2_REFACC_OFS (15) /*!< CEREFACC Bit Offset */ -#define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /*!< Reference accuracy */ -/* COMP_E_CTL3[PD0] Bits */ -#define COMP_E_CTL3_PD0_OFS ( 0) /*!< CEPD0 Bit Offset */ -#define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /*!< Port disable */ -/* COMP_E_CTL3[PD1] Bits */ -#define COMP_E_CTL3_PD1_OFS ( 1) /*!< CEPD1 Bit Offset */ -#define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /*!< Port disable */ -/* COMP_E_CTL3[PD2] Bits */ -#define COMP_E_CTL3_PD2_OFS ( 2) /*!< CEPD2 Bit Offset */ -#define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /*!< Port disable */ -/* COMP_E_CTL3[PD3] Bits */ -#define COMP_E_CTL3_PD3_OFS ( 3) /*!< CEPD3 Bit Offset */ -#define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /*!< Port disable */ -/* COMP_E_CTL3[PD4] Bits */ -#define COMP_E_CTL3_PD4_OFS ( 4) /*!< CEPD4 Bit Offset */ -#define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /*!< Port disable */ -/* COMP_E_CTL3[PD5] Bits */ -#define COMP_E_CTL3_PD5_OFS ( 5) /*!< CEPD5 Bit Offset */ -#define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /*!< Port disable */ -/* COMP_E_CTL3[PD6] Bits */ -#define COMP_E_CTL3_PD6_OFS ( 6) /*!< CEPD6 Bit Offset */ -#define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /*!< Port disable */ -/* COMP_E_CTL3[PD7] Bits */ -#define COMP_E_CTL3_PD7_OFS ( 7) /*!< CEPD7 Bit Offset */ -#define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /*!< Port disable */ -/* COMP_E_CTL3[PD8] Bits */ -#define COMP_E_CTL3_PD8_OFS ( 8) /*!< CEPD8 Bit Offset */ -#define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /*!< Port disable */ -/* COMP_E_CTL3[PD9] Bits */ -#define COMP_E_CTL3_PD9_OFS ( 9) /*!< CEPD9 Bit Offset */ -#define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /*!< Port disable */ -/* COMP_E_CTL3[PD10] Bits */ -#define COMP_E_CTL3_PD10_OFS (10) /*!< CEPD10 Bit Offset */ -#define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /*!< Port disable */ -/* COMP_E_CTL3[PD11] Bits */ -#define COMP_E_CTL3_PD11_OFS (11) /*!< CEPD11 Bit Offset */ -#define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /*!< Port disable */ -/* COMP_E_CTL3[PD12] Bits */ -#define COMP_E_CTL3_PD12_OFS (12) /*!< CEPD12 Bit Offset */ -#define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /*!< Port disable */ -/* COMP_E_CTL3[PD13] Bits */ -#define COMP_E_CTL3_PD13_OFS (13) /*!< CEPD13 Bit Offset */ -#define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /*!< Port disable */ -/* COMP_E_CTL3[PD14] Bits */ -#define COMP_E_CTL3_PD14_OFS (14) /*!< CEPD14 Bit Offset */ -#define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /*!< Port disable */ -/* COMP_E_CTL3[PD15] Bits */ -#define COMP_E_CTL3_PD15_OFS (15) /*!< CEPD15 Bit Offset */ -#define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /*!< Port disable */ -/* COMP_E_INT[IFG] Bits */ -#define COMP_E_INT_IFG_OFS ( 0) /*!< CEIFG Bit Offset */ -#define COMP_E_INT_IFG ((uint16_t)0x0001) /*!< Comparator output interrupt flag */ -/* COMP_E_INT[IIFG] Bits */ -#define COMP_E_INT_IIFG_OFS ( 1) /*!< CEIIFG Bit Offset */ -#define COMP_E_INT_IIFG ((uint16_t)0x0002) /*!< Comparator output inverted interrupt flag */ -/* COMP_E_INT[RDYIFG] Bits */ -#define COMP_E_INT_RDYIFG_OFS ( 4) /*!< CERDYIFG Bit Offset */ -#define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /*!< Comparator ready interrupt flag */ -/* COMP_E_INT[IE] Bits */ -#define COMP_E_INT_IE_OFS ( 8) /*!< CEIE Bit Offset */ -#define COMP_E_INT_IE ((uint16_t)0x0100) /*!< Comparator output interrupt enable */ -/* COMP_E_INT[IIE] Bits */ -#define COMP_E_INT_IIE_OFS ( 9) /*!< CEIIE Bit Offset */ -#define COMP_E_INT_IIE ((uint16_t)0x0200) /*!< Comparator output interrupt enable inverted polarity */ -/* COMP_E_INT[RDYIE] Bits */ -#define COMP_E_INT_RDYIE_OFS (12) /*!< CERDYIE Bit Offset */ -#define COMP_E_INT_RDYIE ((uint16_t)0x1000) /*!< Comparator ready interrupt enable */ - -/****************************************************************************** -* COREDEBUG Bits -******************************************************************************/ - - -/****************************************************************************** -* CRC32 Bits -******************************************************************************/ - -/****************************************************************************** -* CS Bits -******************************************************************************/ -/* CS_KEY[KEY] Bits */ -#define CS_KEY_KEY_OFS ( 0) /*!< CSKEY Bit Offset */ -#define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< CSKEY Bit Mask */ -/* CS_CTL0[DCOTUNE] Bits */ -#define CS_CTL0_DCOTUNE_OFS ( 0) /*!< DCOTUNE Bit Offset */ -#define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /*!< DCOTUNE Bit Mask */ -/* CS_CTL0[DCORSEL] Bits */ -#define CS_CTL0_DCORSEL_OFS (16) /*!< DCORSEL Bit Offset */ -#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /*!< DCORSEL Bit Mask */ -#define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /*!< DCORSEL Bit 0 */ -#define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /*!< DCORSEL Bit 1 */ -#define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /*!< DCORSEL Bit 2 */ -#define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */ -#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */ -#define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */ -#define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */ -#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */ -#define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */ -/* CS_CTL0[DCORES] Bits */ -#define CS_CTL0_DCORES_OFS (22) /*!< DCORES Bit Offset */ -#define CS_CTL0_DCORES ((uint32_t)0x00400000) /*!< Enables the DCO external resistor mode */ -/* CS_CTL0[DCOEN] Bits */ -#define CS_CTL0_DCOEN_OFS (23) /*!< DCOEN Bit Offset */ -#define CS_CTL0_DCOEN ((uint32_t)0x00800000) /*!< Enables the DCO oscillator */ -/* CS_CTL1[SELM] Bits */ -#define CS_CTL1_SELM_OFS ( 0) /*!< SELM Bit Offset */ -#define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /*!< SELM Bit Mask */ -#define CS_CTL1_SELM0 ((uint32_t)0x00000001) /*!< SELM Bit 0 */ -#define CS_CTL1_SELM1 ((uint32_t)0x00000002) /*!< SELM Bit 1 */ -#define CS_CTL1_SELM2 ((uint32_t)0x00000004) /*!< SELM Bit 2 */ -#define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM_1 ((uint32_t)0x00000001) -#define CS_CTL1_SELM_2 ((uint32_t)0x00000002) -#define CS_CTL1_SELM_3 ((uint32_t)0x00000003) -#define CS_CTL1_SELM_4 ((uint32_t)0x00000004) -#define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001) -#define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002) -#define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003) -#define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004) -#define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -/* CS_CTL1[SELS] Bits */ -#define CS_CTL1_SELS_OFS ( 4) /*!< SELS Bit Offset */ -#define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /*!< SELS Bit Mask */ -#define CS_CTL1_SELS0 ((uint32_t)0x00000010) /*!< SELS Bit 0 */ -#define CS_CTL1_SELS1 ((uint32_t)0x00000020) /*!< SELS Bit 1 */ -#define CS_CTL1_SELS2 ((uint32_t)0x00000040) /*!< SELS Bit 2 */ -#define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS_1 ((uint32_t)0x00000010) -#define CS_CTL1_SELS_2 ((uint32_t)0x00000020) -#define CS_CTL1_SELS_3 ((uint32_t)0x00000030) -#define CS_CTL1_SELS_4 ((uint32_t)0x00000040) -#define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010) -#define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020) -#define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030) -#define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040) -#define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -/* CS_CTL1[SELA] Bits */ -#define CS_CTL1_SELA_OFS ( 8) /*!< SELA Bit Offset */ -#define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /*!< SELA Bit Mask */ -#define CS_CTL1_SELA0 ((uint32_t)0x00000100) /*!< SELA Bit 0 */ -#define CS_CTL1_SELA1 ((uint32_t)0x00000200) /*!< SELA Bit 1 */ -#define CS_CTL1_SELA2 ((uint32_t)0x00000400) /*!< SELA Bit 2 */ -#define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA_1 ((uint32_t)0x00000100) -#define CS_CTL1_SELA_2 ((uint32_t)0x00000200) -#define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100) -#define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200) -/* CS_CTL1[SELB] Bits */ -#define CS_CTL1_SELB_OFS (12) /*!< SELB Bit Offset */ -#define CS_CTL1_SELB ((uint32_t)0x00001000) /*!< Selects the BCLK source */ -/* CS_CTL1[DIVM] Bits */ -#define CS_CTL1_DIVM_OFS (16) /*!< DIVM Bit Offset */ -#define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /*!< DIVM Bit Mask */ -#define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /*!< DIVM Bit 0 */ -#define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /*!< DIVM Bit 1 */ -#define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /*!< DIVM Bit 2 */ -#define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -#define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -/* CS_CTL1[DIVHS] Bits */ -#define CS_CTL1_DIVHS_OFS (20) /*!< DIVHS Bit Offset */ -#define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /*!< DIVHS Bit Mask */ -#define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /*!< DIVHS Bit 0 */ -#define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /*!< DIVHS Bit 1 */ -#define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /*!< DIVHS Bit 2 */ -#define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -#define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -/* CS_CTL1[DIVA] Bits */ -#define CS_CTL1_DIVA_OFS (24) /*!< DIVA Bit Offset */ -#define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /*!< DIVA Bit Mask */ -#define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /*!< DIVA Bit 0 */ -#define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /*!< DIVA Bit 1 */ -#define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /*!< DIVA Bit 2 */ -#define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -#define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -/* CS_CTL1[DIVS] Bits */ -#define CS_CTL1_DIVS_OFS (28) /*!< DIVS Bit Offset */ -#define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /*!< DIVS Bit Mask */ -#define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /*!< DIVS Bit 0 */ -#define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /*!< DIVS Bit 1 */ -#define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /*!< DIVS Bit 2 */ -#define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -#define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -/* CS_CTL2[LFXTDRIVE] Bits */ -#define CS_CTL2_LFXTDRIVE_OFS ( 0) /*!< LFXTDRIVE Bit Offset */ -#define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /*!< LFXTDRIVE Bit Mask */ -#define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /*!< LFXTDRIVE Bit 0 */ -#define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /*!< LFXTDRIVE Bit 1 */ -#define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /*!< Lowest drive strength and current consumption LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */ -/* CS_CTL2[LFXT_EN] Bits */ -#define CS_CTL2_LFXT_EN_OFS ( 8) /*!< LFXT_EN Bit Offset */ -#define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /*!< Turns on the LFXT oscillator regardless if used as a clock resource */ -/* CS_CTL2[LFXTBYPASS] Bits */ -#define CS_CTL2_LFXTBYPASS_OFS ( 9) /*!< LFXTBYPASS Bit Offset */ -#define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /*!< LFXT bypass select */ -/* CS_CTL2[HFXTDRIVE] Bits */ -#define CS_CTL2_HFXTDRIVE_OFS (16) /*!< HFXTDRIVE Bit Offset */ -#define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /*!< HFXT oscillator drive selection */ -/* CS_CTL2[HFXTFREQ] Bits */ -#define CS_CTL2_HFXTFREQ_OFS (20) /*!< HFXTFREQ Bit Offset */ -#define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /*!< HFXTFREQ Bit Mask */ -#define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /*!< HFXTFREQ Bit 0 */ -#define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /*!< HFXTFREQ Bit 1 */ -#define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /*!< HFXTFREQ Bit 2 */ -#define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /*!< 1 MHz to 4 MHz */ -#define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /*!< >4 MHz to 8 MHz */ -#define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /*!< >8 MHz to 16 MHz */ -#define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /*!< >16 MHz to 24 MHz */ -#define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /*!< >24 MHz to 32 MHz */ -#define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /*!< >32 MHz to 40 MHz */ -#define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /*!< >40 MHz to 48 MHz */ -#define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /*!< Reserved for future use. */ -/* CS_CTL2[HFXT_EN] Bits */ -#define CS_CTL2_HFXT_EN_OFS (24) /*!< HFXT_EN Bit Offset */ -#define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /*!< Turns on the HFXT oscillator regardless if used as a clock resource */ -/* CS_CTL2[HFXTBYPASS] Bits */ -#define CS_CTL2_HFXTBYPASS_OFS (25) /*!< HFXTBYPASS Bit Offset */ -#define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /*!< HFXT bypass select */ -/* CS_CTL3[FCNTLF] Bits */ -#define CS_CTL3_FCNTLF_OFS ( 0) /*!< FCNTLF Bit Offset */ -#define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /*!< FCNTLF Bit Mask */ -#define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /*!< FCNTLF Bit 0 */ -#define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /*!< FCNTLF Bit 1 */ -#define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /*!< 32768 cycles */ -#define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /*!< 32768 cycles */ -/* CS_CTL3[RFCNTLF] Bits */ -#define CS_CTL3_RFCNTLF_OFS ( 2) /*!< RFCNTLF Bit Offset */ -#define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /*!< Reset start fault counter for LFXT */ -/* CS_CTL3[FCNTLF_EN] Bits */ -#define CS_CTL3_FCNTLF_EN_OFS ( 3) /*!< FCNTLF_EN Bit Offset */ -#define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /*!< Enable start fault counter for LFXT */ -/* CS_CTL3[FCNTHF] Bits */ -#define CS_CTL3_FCNTHF_OFS ( 4) /*!< FCNTHF Bit Offset */ -#define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /*!< FCNTHF Bit Mask */ -#define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /*!< FCNTHF Bit 0 */ -#define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /*!< FCNTHF Bit 1 */ -#define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /*!< 16384 cycles */ -#define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /*!< 16384 cycles */ -/* CS_CTL3[RFCNTHF] Bits */ -#define CS_CTL3_RFCNTHF_OFS ( 6) /*!< RFCNTHF Bit Offset */ -#define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /*!< Reset start fault counter for HFXT */ -/* CS_CTL3[FCNTHF_EN] Bits */ -#define CS_CTL3_FCNTHF_EN_OFS ( 7) /*!< FCNTHF_EN Bit Offset */ -#define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /*!< Enable start fault counter for HFXT */ -/* CS_CLKEN[ACLK_EN] Bits */ -#define CS_CLKEN_ACLK_EN_OFS ( 0) /*!< ACLK_EN Bit Offset */ -#define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /*!< ACLK system clock conditional request enable */ -/* CS_CLKEN[MCLK_EN] Bits */ -#define CS_CLKEN_MCLK_EN_OFS ( 1) /*!< MCLK_EN Bit Offset */ -#define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /*!< MCLK system clock conditional request enable */ -/* CS_CLKEN[HSMCLK_EN] Bits */ -#define CS_CLKEN_HSMCLK_EN_OFS ( 2) /*!< HSMCLK_EN Bit Offset */ -#define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /*!< HSMCLK system clock conditional request enable */ -/* CS_CLKEN[SMCLK_EN] Bits */ -#define CS_CLKEN_SMCLK_EN_OFS ( 3) /*!< SMCLK_EN Bit Offset */ -#define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /*!< SMCLK system clock conditional request enable */ -/* CS_CLKEN[VLO_EN] Bits */ -#define CS_CLKEN_VLO_EN_OFS ( 8) /*!< VLO_EN Bit Offset */ -#define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /*!< Turns on the VLO oscillator */ -/* CS_CLKEN[REFO_EN] Bits */ -#define CS_CLKEN_REFO_EN_OFS ( 9) /*!< REFO_EN Bit Offset */ -#define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /*!< Turns on the REFO oscillator */ -/* CS_CLKEN[MODOSC_EN] Bits */ -#define CS_CLKEN_MODOSC_EN_OFS (10) /*!< MODOSC_EN Bit Offset */ -#define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /*!< Turns on the MODOSC oscillator */ -/* CS_CLKEN[REFOFSEL] Bits */ -#define CS_CLKEN_REFOFSEL_OFS (15) /*!< REFOFSEL Bit Offset */ -#define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /*!< Selects REFO nominal frequency */ -/* CS_STAT[DCO_ON] Bits */ -#define CS_STAT_DCO_ON_OFS ( 0) /*!< DCO_ON Bit Offset */ -#define CS_STAT_DCO_ON ((uint32_t)0x00000001) /*!< DCO status */ -/* CS_STAT[DCOBIAS_ON] Bits */ -#define CS_STAT_DCOBIAS_ON_OFS ( 1) /*!< DCOBIAS_ON Bit Offset */ -#define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /*!< DCO bias status */ -/* CS_STAT[HFXT_ON] Bits */ -#define CS_STAT_HFXT_ON_OFS ( 2) /*!< HFXT_ON Bit Offset */ -#define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /*!< HFXT status */ -/* CS_STAT[MODOSC_ON] Bits */ -#define CS_STAT_MODOSC_ON_OFS ( 4) /*!< MODOSC_ON Bit Offset */ -#define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /*!< MODOSC status */ -/* CS_STAT[VLO_ON] Bits */ -#define CS_STAT_VLO_ON_OFS ( 5) /*!< VLO_ON Bit Offset */ -#define CS_STAT_VLO_ON ((uint32_t)0x00000020) /*!< VLO status */ -/* CS_STAT[LFXT_ON] Bits */ -#define CS_STAT_LFXT_ON_OFS ( 6) /*!< LFXT_ON Bit Offset */ -#define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /*!< LFXT status */ -/* CS_STAT[REFO_ON] Bits */ -#define CS_STAT_REFO_ON_OFS ( 7) /*!< REFO_ON Bit Offset */ -#define CS_STAT_REFO_ON ((uint32_t)0x00000080) /*!< REFO status */ -/* CS_STAT[ACLK_ON] Bits */ -#define CS_STAT_ACLK_ON_OFS (16) /*!< ACLK_ON Bit Offset */ -#define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /*!< ACLK system clock status */ -/* CS_STAT[MCLK_ON] Bits */ -#define CS_STAT_MCLK_ON_OFS (17) /*!< MCLK_ON Bit Offset */ -#define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /*!< MCLK system clock status */ -/* CS_STAT[HSMCLK_ON] Bits */ -#define CS_STAT_HSMCLK_ON_OFS (18) /*!< HSMCLK_ON Bit Offset */ -#define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /*!< HSMCLK system clock status */ -/* CS_STAT[SMCLK_ON] Bits */ -#define CS_STAT_SMCLK_ON_OFS (19) /*!< SMCLK_ON Bit Offset */ -#define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /*!< SMCLK system clock status */ -/* CS_STAT[MODCLK_ON] Bits */ -#define CS_STAT_MODCLK_ON_OFS (20) /*!< MODCLK_ON Bit Offset */ -#define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /*!< MODCLK system clock status */ -/* CS_STAT[VLOCLK_ON] Bits */ -#define CS_STAT_VLOCLK_ON_OFS (21) /*!< VLOCLK_ON Bit Offset */ -#define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /*!< VLOCLK system clock status */ -/* CS_STAT[LFXTCLK_ON] Bits */ -#define CS_STAT_LFXTCLK_ON_OFS (22) /*!< LFXTCLK_ON Bit Offset */ -#define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /*!< LFXTCLK system clock status */ -/* CS_STAT[REFOCLK_ON] Bits */ -#define CS_STAT_REFOCLK_ON_OFS (23) /*!< REFOCLK_ON Bit Offset */ -#define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /*!< REFOCLK system clock status */ -/* CS_STAT[ACLK_READY] Bits */ -#define CS_STAT_ACLK_READY_OFS (24) /*!< ACLK_READY Bit Offset */ -#define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /*!< ACLK Ready status */ -/* CS_STAT[MCLK_READY] Bits */ -#define CS_STAT_MCLK_READY_OFS (25) /*!< MCLK_READY Bit Offset */ -#define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /*!< MCLK Ready status */ -/* CS_STAT[HSMCLK_READY] Bits */ -#define CS_STAT_HSMCLK_READY_OFS (26) /*!< HSMCLK_READY Bit Offset */ -#define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /*!< HSMCLK Ready status */ -/* CS_STAT[SMCLK_READY] Bits */ -#define CS_STAT_SMCLK_READY_OFS (27) /*!< SMCLK_READY Bit Offset */ -#define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /*!< SMCLK Ready status */ -/* CS_STAT[BCLK_READY] Bits */ -#define CS_STAT_BCLK_READY_OFS (28) /*!< BCLK_READY Bit Offset */ -#define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /*!< BCLK Ready status */ -/* CS_IE[LFXTIE] Bits */ -#define CS_IE_LFXTIE_OFS ( 0) /*!< LFXTIE Bit Offset */ -#define CS_IE_LFXTIE ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag interrupt enable */ -/* CS_IE[HFXTIE] Bits */ -#define CS_IE_HFXTIE_OFS ( 1) /*!< HFXTIE Bit Offset */ -#define CS_IE_HFXTIE ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag interrupt enable */ -/* CS_IE[DCOR_OPNIE] Bits */ -#define CS_IE_DCOR_OPNIE_OFS ( 6) /*!< DCOR_OPNIE Bit Offset */ -#define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag interrupt enable. */ -/* CS_IE[FCNTLFIE] Bits */ -#define CS_IE_FCNTLFIE_OFS ( 8) /*!< FCNTLFIE Bit Offset */ -#define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /*!< Start fault counter interrupt enable LFXT */ -/* CS_IE[FCNTHFIE] Bits */ -#define CS_IE_FCNTHFIE_OFS ( 9) /*!< FCNTHFIE Bit Offset */ -#define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /*!< Start fault counter interrupt enable HFXT */ -/* CS_IFG[LFXTIFG] Bits */ -#define CS_IFG_LFXTIFG_OFS ( 0) /*!< LFXTIFG Bit Offset */ -#define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag */ -/* CS_IFG[HFXTIFG] Bits */ -#define CS_IFG_HFXTIFG_OFS ( 1) /*!< HFXTIFG Bit Offset */ -#define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag */ -/* CS_IFG[DCOR_SHTIFG] Bits */ -#define CS_IFG_DCOR_SHTIFG_OFS ( 5) /*!< DCOR_SHTIFG Bit Offset */ -#define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /*!< DCO external resistor short circuit fault flag. */ -/* CS_IFG[DCOR_OPNIFG] Bits */ -#define CS_IFG_DCOR_OPNIFG_OFS ( 6) /*!< DCOR_OPNIFG Bit Offset */ -#define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag. */ -/* CS_IFG[FCNTLFIFG] Bits */ -#define CS_IFG_FCNTLFIFG_OFS ( 8) /*!< FCNTLFIFG Bit Offset */ -#define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter interrupt flag LFXT */ -/* CS_IFG[FCNTHFIFG] Bits */ -#define CS_IFG_FCNTHFIFG_OFS ( 9) /*!< FCNTHFIFG Bit Offset */ -#define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter interrupt flag HFXT */ -/* CS_CLRIFG[CLR_LFXTIFG] Bits */ -#define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /*!< CLR_LFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /*!< Clear LFXT oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_HFXTIFG] Bits */ -#define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /*!< CLR_HFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /*!< Clear HFXT oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /*!< CLR_DCOR_OPNIFG Bit Offset */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Clear DCO external resistor open circuit fault interrupt flag. */ -/* CS_CLRIFG[CLR_FCNTLFIFG] Bits */ -#define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /*!< CLR_FCNTLFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter clear interrupt flag LFXT */ -/* CS_CLRIFG[CLR_FCNTHFIFG] Bits */ -#define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /*!< CLR_FCNTHFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter clear interrupt flag HFXT */ -/* CS_SETIFG[SET_LFXTIFG] Bits */ -#define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /*!< SET_LFXTIFG Bit Offset */ -#define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /*!< Set LFXT oscillator fault interrupt flag */ -/* CS_SETIFG[SET_HFXTIFG] Bits */ -#define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /*!< SET_HFXTIFG Bit Offset */ -#define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /*!< Set HFXT oscillator fault interrupt flag */ -/* CS_SETIFG[SET_DCOR_OPNIFG] Bits */ -#define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /*!< SET_DCOR_OPNIFG Bit Offset */ -#define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Set DCO external resistor open circuit fault interrupt flag. */ -/* CS_SETIFG[SET_FCNTHFIFG] Bits */ -#define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /*!< SET_FCNTHFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter set interrupt flag HFXT */ -/* CS_SETIFG[SET_FCNTLFIFG] Bits */ -#define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /*!< SET_FCNTLFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter set interrupt flag LFXT */ -/* CS_DCOERCAL0[DCO_TCCAL] Bits */ -#define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /*!< DCO_TCCAL Bit Offset */ -#define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /*!< DCO_TCCAL Bit Mask */ -/* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /*!< DCO_FCAL_RSEL04 Bit Offset */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /*!< DCO_FCAL_RSEL04 Bit Mask */ -/* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /*!< DCO_FCAL_RSEL5 Bit Offset */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /*!< DCO_FCAL_RSEL5 Bit Mask */ -/* Pre-defined bitfield values */ -#define CS_KEY_VAL ((uint32_t)0x0000695A) /*!< CS control key value */ - -/****************************************************************************** -* DIO Bits -******************************************************************************/ -/* DIO_IV[IV] Bits */ -#define DIO_PORT_IV_OFS ( 0) /*!< DIO Port IV Bit Offset */ -#define DIO_PORT_IV_MASK ((uint16_t)0x001F) /*!< DIO Port IV Bit Mask */ -#define DIO_PORT_IV0 ((uint16_t)0x0001) /*!< DIO Port IV Bit 0 */ -#define DIO_PORT_IV1 ((uint16_t)0x0002) /*!< DIO Port IV Bit 1 */ -#define DIO_PORT_IV2 ((uint16_t)0x0004) /*!< DIO Port IV Bit 2 */ -#define DIO_PORT_IV3 ((uint16_t)0x0008) /*!< DIO Port IV Bit 3 */ -#define DIO_PORT_IV4 ((uint16_t)0x0010) /*!< DIO Port IV Bit 4 */ -#define DIO_PORT_IV_0 ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV_2 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ - /* Priority: Highest */ -#define DIO_PORT_IV_4 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV_6 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV_8 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV_10 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV_12 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV_14 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV_16 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ - /* Priority: Lowest */ -#define DIO_PORT_IV__NONE ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ - /* Priority: Highest */ -#define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ - /* Priority: Lowest */ - - -/****************************************************************************** -* DMA Bits -******************************************************************************/ -/* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /*!< NUM_DMA_CHANNELS Bit Offset */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /*!< NUM_DMA_CHANNELS Bit Mask */ -/* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /*!< NUM_SRC_PER_CHANNEL Bit Offset */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /*!< NUM_SRC_PER_CHANNEL Bit Mask */ -/* DMA_SW_CHTRIG[CH0] Bits */ -#define DMA_SW_CHTRIG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /*!< Write 1, triggers DMA_CHANNEL0 */ -/* DMA_SW_CHTRIG[CH1] Bits */ -#define DMA_SW_CHTRIG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /*!< Write 1, triggers DMA_CHANNEL1 */ -/* DMA_SW_CHTRIG[CH2] Bits */ -#define DMA_SW_CHTRIG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /*!< Write 1, triggers DMA_CHANNEL2 */ -/* DMA_SW_CHTRIG[CH3] Bits */ -#define DMA_SW_CHTRIG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /*!< Write 1, triggers DMA_CHANNEL3 */ -/* DMA_SW_CHTRIG[CH4] Bits */ -#define DMA_SW_CHTRIG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /*!< Write 1, triggers DMA_CHANNEL4 */ -/* DMA_SW_CHTRIG[CH5] Bits */ -#define DMA_SW_CHTRIG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /*!< Write 1, triggers DMA_CHANNEL5 */ -/* DMA_SW_CHTRIG[CH6] Bits */ -#define DMA_SW_CHTRIG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /*!< Write 1, triggers DMA_CHANNEL6 */ -/* DMA_SW_CHTRIG[CH7] Bits */ -#define DMA_SW_CHTRIG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /*!< Write 1, triggers DMA_CHANNEL7 */ -/* DMA_SW_CHTRIG[CH8] Bits */ -#define DMA_SW_CHTRIG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /*!< Write 1, triggers DMA_CHANNEL8 */ -/* DMA_SW_CHTRIG[CH9] Bits */ -#define DMA_SW_CHTRIG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /*!< Write 1, triggers DMA_CHANNEL9 */ -/* DMA_SW_CHTRIG[CH10] Bits */ -#define DMA_SW_CHTRIG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /*!< Write 1, triggers DMA_CHANNEL10 */ -/* DMA_SW_CHTRIG[CH11] Bits */ -#define DMA_SW_CHTRIG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /*!< Write 1, triggers DMA_CHANNEL11 */ -/* DMA_SW_CHTRIG[CH12] Bits */ -#define DMA_SW_CHTRIG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /*!< Write 1, triggers DMA_CHANNEL12 */ -/* DMA_SW_CHTRIG[CH13] Bits */ -#define DMA_SW_CHTRIG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /*!< Write 1, triggers DMA_CHANNEL13 */ -/* DMA_SW_CHTRIG[CH14] Bits */ -#define DMA_SW_CHTRIG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /*!< Write 1, triggers DMA_CHANNEL14 */ -/* DMA_SW_CHTRIG[CH15] Bits */ -#define DMA_SW_CHTRIG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /*!< Write 1, triggers DMA_CHANNEL15 */ -/* DMA_SW_CHTRIG[CH16] Bits */ -#define DMA_SW_CHTRIG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /*!< Write 1, triggers DMA_CHANNEL16 */ -/* DMA_SW_CHTRIG[CH17] Bits */ -#define DMA_SW_CHTRIG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /*!< Write 1, triggers DMA_CHANNEL17 */ -/* DMA_SW_CHTRIG[CH18] Bits */ -#define DMA_SW_CHTRIG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /*!< Write 1, triggers DMA_CHANNEL18 */ -/* DMA_SW_CHTRIG[CH19] Bits */ -#define DMA_SW_CHTRIG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /*!< Write 1, triggers DMA_CHANNEL19 */ -/* DMA_SW_CHTRIG[CH20] Bits */ -#define DMA_SW_CHTRIG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /*!< Write 1, triggers DMA_CHANNEL20 */ -/* DMA_SW_CHTRIG[CH21] Bits */ -#define DMA_SW_CHTRIG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /*!< Write 1, triggers DMA_CHANNEL21 */ -/* DMA_SW_CHTRIG[CH22] Bits */ -#define DMA_SW_CHTRIG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /*!< Write 1, triggers DMA_CHANNEL22 */ -/* DMA_SW_CHTRIG[CH23] Bits */ -#define DMA_SW_CHTRIG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /*!< Write 1, triggers DMA_CHANNEL23 */ -/* DMA_SW_CHTRIG[CH24] Bits */ -#define DMA_SW_CHTRIG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /*!< Write 1, triggers DMA_CHANNEL24 */ -/* DMA_SW_CHTRIG[CH25] Bits */ -#define DMA_SW_CHTRIG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /*!< Write 1, triggers DMA_CHANNEL25 */ -/* DMA_SW_CHTRIG[CH26] Bits */ -#define DMA_SW_CHTRIG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /*!< Write 1, triggers DMA_CHANNEL26 */ -/* DMA_SW_CHTRIG[CH27] Bits */ -#define DMA_SW_CHTRIG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /*!< Write 1, triggers DMA_CHANNEL27 */ -/* DMA_SW_CHTRIG[CH28] Bits */ -#define DMA_SW_CHTRIG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /*!< Write 1, triggers DMA_CHANNEL28 */ -/* DMA_SW_CHTRIG[CH29] Bits */ -#define DMA_SW_CHTRIG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /*!< Write 1, triggers DMA_CHANNEL29 */ -/* DMA_SW_CHTRIG[CH30] Bits */ -#define DMA_SW_CHTRIG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /*!< Write 1, triggers DMA_CHANNEL30 */ -/* DMA_SW_CHTRIG[CH31] Bits */ -#define DMA_SW_CHTRIG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /*!< Write 1, triggers DMA_CHANNEL31 */ -/* DMA_CHN_SRCCFG[DMA_SRC] Bits */ -#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /*!< DMA_SRC Bit Offset */ -#define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /*!< DMA_SRC Bit Mask */ -/* DMA_INT1_SRCCFG[INT_SRC] Bits */ -#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT1_SRCCFG[EN] Bits */ -#define DMA_INT1_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT1 mapping */ -/* DMA_INT2_SRCCFG[INT_SRC] Bits */ -#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT2_SRCCFG[EN] Bits */ -#define DMA_INT2_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT2 mapping */ -/* DMA_INT3_SRCCFG[INT_SRC] Bits */ -#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -/* DMA_INT3_SRCCFG[EN] Bits */ -#define DMA_INT3_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT3 mapping */ -/* DMA_INT0_SRCFLG[CH0] Bits */ -#define DMA_INT0_SRCFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /*!< Channel 0 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH1] Bits */ -#define DMA_INT0_SRCFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /*!< Channel 1 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH2] Bits */ -#define DMA_INT0_SRCFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /*!< Channel 2 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH3] Bits */ -#define DMA_INT0_SRCFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /*!< Channel 3 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH4] Bits */ -#define DMA_INT0_SRCFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /*!< Channel 4 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH5] Bits */ -#define DMA_INT0_SRCFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /*!< Channel 5 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH6] Bits */ -#define DMA_INT0_SRCFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /*!< Channel 6 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH7] Bits */ -#define DMA_INT0_SRCFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /*!< Channel 7 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH8] Bits */ -#define DMA_INT0_SRCFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /*!< Channel 8 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH9] Bits */ -#define DMA_INT0_SRCFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /*!< Channel 9 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH10] Bits */ -#define DMA_INT0_SRCFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /*!< Channel 10 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH11] Bits */ -#define DMA_INT0_SRCFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /*!< Channel 11 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH12] Bits */ -#define DMA_INT0_SRCFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /*!< Channel 12 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH13] Bits */ -#define DMA_INT0_SRCFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /*!< Channel 13 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH14] Bits */ -#define DMA_INT0_SRCFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /*!< Channel 14 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH15] Bits */ -#define DMA_INT0_SRCFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /*!< Channel 15 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH16] Bits */ -#define DMA_INT0_SRCFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /*!< Channel 16 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH17] Bits */ -#define DMA_INT0_SRCFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /*!< Channel 17 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH18] Bits */ -#define DMA_INT0_SRCFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /*!< Channel 18 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH19] Bits */ -#define DMA_INT0_SRCFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /*!< Channel 19 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH20] Bits */ -#define DMA_INT0_SRCFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /*!< Channel 20 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH21] Bits */ -#define DMA_INT0_SRCFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /*!< Channel 21 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH22] Bits */ -#define DMA_INT0_SRCFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /*!< Channel 22 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH23] Bits */ -#define DMA_INT0_SRCFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /*!< Channel 23 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH24] Bits */ -#define DMA_INT0_SRCFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /*!< Channel 24 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH25] Bits */ -#define DMA_INT0_SRCFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /*!< Channel 25 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH26] Bits */ -#define DMA_INT0_SRCFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /*!< Channel 26 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH27] Bits */ -#define DMA_INT0_SRCFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /*!< Channel 27 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH28] Bits */ -#define DMA_INT0_SRCFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /*!< Channel 28 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH29] Bits */ -#define DMA_INT0_SRCFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /*!< Channel 29 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH30] Bits */ -#define DMA_INT0_SRCFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /*!< Channel 30 was the source of DMA_INT0 */ -/* DMA_INT0_SRCFLG[CH31] Bits */ -#define DMA_INT0_SRCFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /*!< Channel 31 was the source of DMA_INT0 */ -/* DMA_INT0_CLRFLG[CH0] Bits */ -#define DMA_INT0_CLRFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH1] Bits */ -#define DMA_INT0_CLRFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH2] Bits */ -#define DMA_INT0_CLRFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH3] Bits */ -#define DMA_INT0_CLRFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH4] Bits */ -#define DMA_INT0_CLRFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH5] Bits */ -#define DMA_INT0_CLRFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH6] Bits */ -#define DMA_INT0_CLRFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH7] Bits */ -#define DMA_INT0_CLRFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH8] Bits */ -#define DMA_INT0_CLRFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH9] Bits */ -#define DMA_INT0_CLRFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH10] Bits */ -#define DMA_INT0_CLRFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH11] Bits */ -#define DMA_INT0_CLRFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH12] Bits */ -#define DMA_INT0_CLRFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH13] Bits */ -#define DMA_INT0_CLRFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH14] Bits */ -#define DMA_INT0_CLRFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH15] Bits */ -#define DMA_INT0_CLRFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH16] Bits */ -#define DMA_INT0_CLRFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH17] Bits */ -#define DMA_INT0_CLRFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH18] Bits */ -#define DMA_INT0_CLRFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH19] Bits */ -#define DMA_INT0_CLRFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH20] Bits */ -#define DMA_INT0_CLRFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH21] Bits */ -#define DMA_INT0_CLRFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH22] Bits */ -#define DMA_INT0_CLRFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH23] Bits */ -#define DMA_INT0_CLRFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH24] Bits */ -#define DMA_INT0_CLRFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH25] Bits */ -#define DMA_INT0_CLRFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH26] Bits */ -#define DMA_INT0_CLRFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH27] Bits */ -#define DMA_INT0_CLRFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH28] Bits */ -#define DMA_INT0_CLRFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH29] Bits */ -#define DMA_INT0_CLRFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH30] Bits */ -#define DMA_INT0_CLRFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_INT0_CLRFLG[CH31] Bits */ -#define DMA_INT0_CLRFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -/* DMA_STAT[MASTEN] Bits */ -#define DMA_STAT_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_STAT_MASTEN ((uint32_t)0x00000001) -/* DMA_STAT[STATE] Bits */ -#define DMA_STAT_STATE_OFS ( 4) /*!< STATE Bit Offset */ -#define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /*!< STATE Bit Mask */ -#define DMA_STAT_STATE0 ((uint32_t)0x00000010) /*!< STATE Bit 0 */ -#define DMA_STAT_STATE1 ((uint32_t)0x00000020) /*!< STATE Bit 1 */ -#define DMA_STAT_STATE2 ((uint32_t)0x00000040) /*!< STATE Bit 2 */ -#define DMA_STAT_STATE3 ((uint32_t)0x00000080) /*!< STATE Bit 3 */ -#define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /*!< idle */ -#define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /*!< reading channel controller data */ -#define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /*!< reading source data end pointer */ -#define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /*!< reading destination data end pointer */ -#define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /*!< reading source data */ -#define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /*!< writing destination data */ -#define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /*!< waiting for DMA request to clear */ -#define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /*!< writing channel controller data */ -#define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /*!< stalled */ -#define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /*!< done */ -#define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /*!< peripheral scatter-gather transition */ -#define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /*!< Reserved */ -#define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /*!< Reserved */ -#define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /*!< Reserved */ -#define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /*!< Reserved */ -#define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /*!< Reserved */ -/* DMA_STAT[DMACHANS] Bits */ -#define DMA_STAT_DMACHANS_OFS (16) /*!< DMACHANS Bit Offset */ -#define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /*!< DMACHANS Bit Mask */ -#define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /*!< DMACHANS Bit 0 */ -#define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /*!< DMACHANS Bit 1 */ -#define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /*!< DMACHANS Bit 2 */ -#define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /*!< DMACHANS Bit 3 */ -#define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /*!< DMACHANS Bit 4 */ -#define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /*!< Controller configured to use 1 DMA channel */ -#define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /*!< Controller configured to use 2 DMA channels */ -#define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /*!< Controller configured to use 31 DMA channels */ -#define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /*!< Controller configured to use 32 DMA channels */ -/* DMA_STAT[TESTSTAT] Bits */ -#define DMA_STAT_TESTSTAT_OFS (28) /*!< TESTSTAT Bit Offset */ -#define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /*!< TESTSTAT Bit Mask */ -#define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /*!< TESTSTAT Bit 0 */ -#define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /*!< TESTSTAT Bit 1 */ -#define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /*!< TESTSTAT Bit 2 */ -#define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /*!< TESTSTAT Bit 3 */ -#define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /*!< Controller does not include the integration test logic */ -#define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /*!< Controller includes the integration test logic */ -/* DMA_CFG[MASTEN] Bits */ -#define DMA_CFG_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_CFG_MASTEN ((uint32_t)0x00000001) -/* DMA_CFG[CHPROTCTRL] Bits */ -#define DMA_CFG_CHPROTCTRL_OFS ( 5) /*!< CHPROTCTRL Bit Offset */ -#define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /*!< CHPROTCTRL Bit Mask */ -/* DMA_CTLBASE[ADDR] Bits */ -#define DMA_CTLBASE_ADDR_OFS ( 5) /*!< ADDR Bit Offset */ -#define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /*!< ADDR Bit Mask */ -/* DMA_ERRCLR[ERRCLR] Bits */ -#define DMA_ERRCLR_ERRCLR_OFS ( 0) /*!< ERRCLR Bit Offset */ -#define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) -/* DMA channel definitions and memory structure alignment */ -#define __MCU_NUM_DMA_CHANNELS__ 8 -#define DMA_CHANNEL_CONTROL_STRUCT_SIZE 0x10 -#define DMA_CONTROL_MEMORY_ALIGNMENT (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE) - -/* UDMA_STAT Control Bits */ -#define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /*!< Available uDMA Channels Minus 1 */ -#define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /*!< Control State Machine Status */ -#define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /*!< Idle */ -#define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /*!< Reading channel controller data */ -#define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /*!< Reading source end pointer */ -#define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /*!< Reading destination end pointer */ -#define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /*!< Reading source data */ -#define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /*!< Writing destination data */ -#define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /*!< Waiting for uDMA request to clear */ -#define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /*!< Writing channel controller data */ -#define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /*!< Stalled */ -#define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /*!< Done */ -#define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /*!< Undefined */ -#define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /*!< Master Enable Status */ -#define UDMA_STAT_DMACHANS_S (16) - -/* UDMA_CFG Control Bits */ -#define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /*!< Controller Master Enable */ - -/* UDMA_CTLBASE Control Bits */ -#define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /*!< Channel Control Base Address */ -#define UDMA_CTLBASE_ADDR_S (10) - -/* UDMA_ALTBASE Control Bits */ -#define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Alternate Channel Address Pointer */ -#define UDMA_ALTBASE_ADDR_S ( 0) - -/* UDMA_WAITSTAT Control Bits */ -#define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Wait Status */ - -/* UDMA_SWREQ Control Bits */ -#define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Software Request */ - -/* UDMA_USEBURSTSET Control Bits */ -#define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Set */ - -/* UDMA_USEBURSTCLR Control Bits */ -#define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Clear */ - -/* UDMA_REQMASKSET Control Bits */ -#define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Set */ - -/* UDMA_REQMASKCLR Control Bits */ -#define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Clear */ - -/* UDMA_ENASET Control Bits */ -#define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Enable Set */ - -/* UDMA_ENACLR Control Bits */ -#define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Clear Channel [n] Enable Clear */ - -/* UDMA_ALTSET Control Bits */ -#define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Set */ - -/* UDMA_ALTCLR Control Bits */ -#define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Clear */ - -/* UDMA_PRIOSET Control Bits */ -#define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Set */ - -/* UDMA_PRIOCLR Control Bits */ -#define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Clear */ - -/* UDMA_ERRCLR Control Bits */ -#define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /*!< uDMA Bus Error Status */ - -/* UDMA_CHASGN Control Bits */ -#define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Assignment Select */ -#define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /*!< Use the primary channel assignment */ -#define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /*!< Use the secondary channel assignment */ - -/* Micro Direct Memory Access (uDMA) offsets */ -#define UDMA_O_SRCENDP ((uint32_t)0x00000000) /*!< DMA Channel Source Address End Pointer */ -#define UDMA_O_DSTENDP ((uint32_t)0x00000004) /*!< DMA Channel Destination Address End Pointer */ -#define UDMA_O_CHCTL ((uint32_t)0x00000008) /*!< DMA Channel Control Word */ - -/* UDMA_O_SRCENDP Control Bits */ -#define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Source Address End Pointer */ -#define UDMA_SRCENDP_ADDR_S ( 0) - -/* UDMA_O_DSTENDP Control Bits */ -#define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Destination Address End Pointer */ -#define UDMA_DSTENDP_ADDR_S ( 0) - -/* UDMA_O_CHCTL Control Bits */ -#define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /*!< Destination Address Increment */ -#define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /*!< Word */ -#define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /*!< No increment */ -#define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /*!< Destination Data Size */ -#define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /*!< Source Address Increment */ -#define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /*!< No increment */ -#define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /*!< Source Data Size */ -#define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /*!< Word */ -#define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /*!< Arbitration Size */ -#define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /*!< 1 Transfer */ -#define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /*!< 2 Transfers */ -#define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /*!< 4 Transfers */ -#define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /*!< 8 Transfers */ -#define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /*!< 16 Transfers */ -#define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /*!< 32 Transfers */ -#define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /*!< 64 Transfers */ -#define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /*!< 128 Transfers */ -#define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /*!< 256 Transfers */ -#define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /*!< 512 Transfers */ -#define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /*!< 1024 Transfers */ -#define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /*!< Transfer Size (minus 1) */ -#define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /*!< Next Useburst */ -#define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /*!< uDMA Transfer Mode */ -#define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /*!< Stop */ -#define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /*!< Basic */ -#define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /*!< Auto-Request */ -#define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /*!< Ping-Pong */ -#define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /*!< Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /*!< Alternate Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /*!< Peripheral Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /*!< Alternate Peripheral Scatter-Gather */ - -#define UDMA_CHCTL_XFERSIZE_S ( 4) - - -/****************************************************************************** -* DWT Bits -******************************************************************************/ - - -/****************************************************************************** -* EUSCI_A Bits -******************************************************************************/ -/* EUSCI_A_CTLW0[SWRST] Bits */ -#define EUSCI_A_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -/* EUSCI_A_CTLW0[TXBRK] Bits */ -#define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /*!< UCTXBRK Bit Offset */ -#define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /*!< Transmit break */ -/* EUSCI_A_CTLW0[TXADDR] Bits */ -#define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /*!< UCTXADDR Bit Offset */ -#define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /*!< Transmit address */ -/* EUSCI_A_CTLW0[DORM] Bits */ -#define EUSCI_A_CTLW0_DORM_OFS ( 3) /*!< UCDORM Bit Offset */ -#define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /*!< Dormant */ -/* EUSCI_A_CTLW0[BRKIE] Bits */ -#define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /*!< UCBRKIE Bit Offset */ -#define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /*!< Receive break character interrupt enable */ -/* EUSCI_A_CTLW0[RXEIE] Bits */ -#define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /*!< UCRXEIE Bit Offset */ -#define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /*!< Receive erroneous-character interrupt enable */ -/* EUSCI_A_CTLW0[SSEL] Bits */ -#define EUSCI_A_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -/* EUSCI_A_CTLW0[SYNC] Bits */ -#define EUSCI_A_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -/* EUSCI_A_CTLW0[MODE] Bits */ -#define EUSCI_A_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< UART mode */ -#define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< Idle-line multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< Address-bit multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< UART mode with automatic baud-rate detection */ -/* EUSCI_A_CTLW0[SPB] Bits */ -#define EUSCI_A_CTLW0_SPB_OFS (11) /*!< UCSPB Bit Offset */ -#define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /*!< Stop bit select */ -/* EUSCI_A_CTLW0[SEVENBIT] Bits */ -#define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -/* EUSCI_A_CTLW0[MSB] Bits */ -#define EUSCI_A_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -/* EUSCI_A_CTLW0[PAR] Bits */ -#define EUSCI_A_CTLW0_PAR_OFS (14) /*!< UCPAR Bit Offset */ -#define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /*!< Parity select */ -/* EUSCI_A_CTLW0[PEN] Bits */ -#define EUSCI_A_CTLW0_PEN_OFS (15) /*!< UCPEN Bit Offset */ -#define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /*!< Parity enable */ -/* EUSCI_A_CTLW0[STEM] Bits */ -#define EUSCI_A_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -/* EUSCI_A_CTLW0[MST] Bits */ -#define EUSCI_A_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -/* EUSCI_A_CTLW0[CKPL] Bits */ -#define EUSCI_A_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -/* EUSCI_A_CTLW0[CKPH] Bits */ -#define EUSCI_A_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -/* EUSCI_A_CTLW1[GLIT] Bits */ -#define EUSCI_A_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< Approximately 2 ns (equivalent of 1 delay element) */ -#define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< Approximately 50 ns */ -#define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< Approximately 100 ns */ -#define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< Approximately 200 ns */ -/* EUSCI_A_MCTLW[OS16] Bits */ -#define EUSCI_A_MCTLW_OS16_OFS ( 0) /*!< UCOS16 Bit Offset */ -#define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /*!< Oversampling mode enabled */ -/* EUSCI_A_MCTLW[BRF] Bits */ -#define EUSCI_A_MCTLW_BRF_OFS ( 4) /*!< UCBRF Bit Offset */ -#define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /*!< UCBRF Bit Mask */ -/* EUSCI_A_MCTLW[BRS] Bits */ -#define EUSCI_A_MCTLW_BRS_OFS ( 8) /*!< UCBRS Bit Offset */ -#define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /*!< UCBRS Bit Mask */ -/* EUSCI_A_STATW[BUSY] Bits */ -#define EUSCI_A_STATW_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -/* EUSCI_A_STATW[ADDR_IDLE] Bits */ -#define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /*!< UCADDR_UCIDLE Bit Offset */ -#define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /*!< Address received / Idle line detected */ -/* EUSCI_A_STATW[RXERR] Bits */ -#define EUSCI_A_STATW_RXERR_OFS ( 2) /*!< UCRXERR Bit Offset */ -#define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /*!< Receive error flag */ -/* EUSCI_A_STATW[BRK] Bits */ -#define EUSCI_A_STATW_BRK_OFS ( 3) /*!< UCBRK Bit Offset */ -#define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /*!< Break detect flag */ -/* EUSCI_A_STATW[PE] Bits */ -#define EUSCI_A_STATW_PE_OFS ( 4) /*!< UCPE Bit Offset */ -#define EUSCI_A_STATW_PE ((uint16_t)0x0010) -/* EUSCI_A_STATW[OE] Bits */ -#define EUSCI_A_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_A_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -/* EUSCI_A_STATW[FE] Bits */ -#define EUSCI_A_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_A_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -/* EUSCI_A_STATW[LISTEN] Bits */ -#define EUSCI_A_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -/* EUSCI_A_STATW[SPI_BUSY] Bits */ -#define EUSCI_A_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -/* EUSCI_A_RXBUF[RXBUF] Bits */ -#define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -/* EUSCI_A_TXBUF[TXBUF] Bits */ -#define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -/* EUSCI_A_ABCTL[ABDEN] Bits */ -#define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /*!< UCABDEN Bit Offset */ -#define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /*!< Automatic baud-rate detect enable */ -/* EUSCI_A_ABCTL[BTOE] Bits */ -#define EUSCI_A_ABCTL_BTOE_OFS ( 2) /*!< UCBTOE Bit Offset */ -#define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /*!< Break time out error */ -/* EUSCI_A_ABCTL[STOE] Bits */ -#define EUSCI_A_ABCTL_STOE_OFS ( 3) /*!< UCSTOE Bit Offset */ -#define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /*!< Synch field time out error */ -/* EUSCI_A_ABCTL[DELIM] Bits */ -#define EUSCI_A_ABCTL_DELIM_OFS ( 4) /*!< UCDELIM Bit Offset */ -#define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /*!< UCDELIM Bit Mask */ -#define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /*!< DELIM Bit 0 */ -#define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /*!< DELIM Bit 1 */ -#define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /*!< 1 bit time */ -#define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /*!< 2 bit times */ -#define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /*!< 3 bit times */ -#define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /*!< 4 bit times */ -/* EUSCI_A_IRCTL[IREN] Bits */ -#define EUSCI_A_IRCTL_IREN_OFS ( 0) /*!< UCIREN Bit Offset */ -#define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /*!< IrDA encoder/decoder enable */ -/* EUSCI_A_IRCTL[IRTXCLK] Bits */ -#define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /*!< UCIRTXCLK Bit Offset */ -#define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /*!< IrDA transmit pulse clock select */ -/* EUSCI_A_IRCTL[IRTXPL] Bits */ -#define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /*!< UCIRTXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /*!< UCIRTXPL Bit Mask */ -/* EUSCI_A_IRCTL[IRRXFE] Bits */ -#define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /*!< UCIRRXFE Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /*!< IrDA receive filter enabled */ -/* EUSCI_A_IRCTL[IRRXPL] Bits */ -#define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /*!< UCIRRXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /*!< IrDA receive input UCAxRXD polarity */ -/* EUSCI_A_IRCTL[IRRXFL] Bits */ -#define EUSCI_A_IRCTL_IRRXFL_OFS (10) /*!< UCIRRXFL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /*!< UCIRRXFL Bit Mask */ -/* EUSCI_A_IE[RXIE] Bits */ -#define EUSCI_A_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -/* EUSCI_A_IE[TXIE] Bits */ -#define EUSCI_A_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -/* EUSCI_A_IE[STTIE] Bits */ -#define EUSCI_A_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /*!< Start bit interrupt enable */ -/* EUSCI_A_IE[TXCPTIE] Bits */ -#define EUSCI_A_IE_TXCPTIE_OFS ( 3) /*!< UCTXCPTIE Bit Offset */ -#define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /*!< Transmit complete interrupt enable */ -/* EUSCI_A_IFG[RXIFG] Bits */ -#define EUSCI_A_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -/* EUSCI_A_IFG[TXIFG] Bits */ -#define EUSCI_A_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -/* EUSCI_A_IFG[STTIFG] Bits */ -#define EUSCI_A_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /*!< Start bit interrupt flag */ -/* EUSCI_A_IFG[TXCPTIFG] Bits */ -#define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /*!< UCTXCPTIFG Bit Offset */ -#define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /*!< Transmit ready interrupt enable */ -/* legacy definitions for backward compatibility to version 2100 */ -#define EUSCI_A__RXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_A__RXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_A__TXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_A__TXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ - - -/****************************************************************************** -* EUSCI_B Bits -******************************************************************************/ -/* EUSCI_B_CTLW0[SWRST] Bits */ -#define EUSCI_B_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -/* EUSCI_B_CTLW0[TXSTT] Bits */ -#define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /*!< UCTXSTT Bit Offset */ -#define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /*!< Transmit START condition in master mode */ -/* EUSCI_B_CTLW0[TXSTP] Bits */ -#define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /*!< UCTXSTP Bit Offset */ -#define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /*!< Transmit STOP condition in master mode */ -/* EUSCI_B_CTLW0[TXNACK] Bits */ -#define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /*!< UCTXNACK Bit Offset */ -#define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /*!< Transmit a NACK */ -/* EUSCI_B_CTLW0[TR] Bits */ -#define EUSCI_B_CTLW0_TR_OFS ( 4) /*!< UCTR Bit Offset */ -#define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /*!< Transmitter/receiver */ -/* EUSCI_B_CTLW0[TXACK] Bits */ -#define EUSCI_B_CTLW0_TXACK_OFS ( 5) /*!< UCTXACK Bit Offset */ -#define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /*!< Transmit ACK condition in slave mode */ -/* EUSCI_B_CTLW0[SSEL] Bits */ -#define EUSCI_B_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_B_CTLW0_UCSSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ -#define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -/* EUSCI_B_CTLW0[SYNC] Bits */ -#define EUSCI_B_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -/* EUSCI_B_CTLW0[MODE] Bits */ -#define EUSCI_B_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< 3-pin SPI */ -#define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< 4-pin SPI (master or slave enabled if STE = 1) */ -#define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< 4-pin SPI (master or slave enabled if STE = 0) */ -#define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< I2C mode */ -/* EUSCI_B_CTLW0[MST] Bits */ -#define EUSCI_B_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -/* EUSCI_B_CTLW0[MM] Bits */ -#define EUSCI_B_CTLW0_MM_OFS (13) /*!< UCMM Bit Offset */ -#define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /*!< Multi-master environment select */ -/* EUSCI_B_CTLW0[SLA10] Bits */ -#define EUSCI_B_CTLW0_SLA10_OFS (14) /*!< UCSLA10 Bit Offset */ -#define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /*!< Slave addressing mode select */ -/* EUSCI_B_CTLW0[A10] Bits */ -#define EUSCI_B_CTLW0_A10_OFS (15) /*!< UCA10 Bit Offset */ -#define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /*!< Own addressing mode select */ -/* EUSCI_B_CTLW0[STEM] Bits */ -#define EUSCI_B_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -/* EUSCI_B_CTLW0[SEVENBIT] Bits */ -#define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -/* EUSCI_B_CTLW0[MSB] Bits */ -#define EUSCI_B_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -/* EUSCI_B_CTLW0[CKPL] Bits */ -#define EUSCI_B_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -/* EUSCI_B_CTLW0[CKPH] Bits */ -#define EUSCI_B_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -/* EUSCI_B_CTLW1[GLIT] Bits */ -#define EUSCI_B_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< 50 ns */ -#define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< 25 ns */ -#define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< 12.5 ns */ -#define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< 6.25 ns */ -/* EUSCI_B_CTLW1[ASTP] Bits */ -#define EUSCI_B_CTLW1_ASTP_OFS ( 2) /*!< UCASTP Bit Offset */ -#define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /*!< UCASTP Bit Mask */ -#define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /*!< ASTP Bit 0 */ -#define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /*!< ASTP Bit 1 */ -#define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /*!< No automatic STOP generation. The STOP condition is generated after the user */ - /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ -#define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ - /* UCBxTBCNT */ -#define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /*!< A STOP condition is generated automatically after the byte counter value */ - /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ - /* threshold */ -/* EUSCI_B_CTLW1[SWACK] Bits */ -#define EUSCI_B_CTLW1_SWACK_OFS ( 4) /*!< UCSWACK Bit Offset */ -#define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /*!< SW or HW ACK control */ -/* EUSCI_B_CTLW1[STPNACK] Bits */ -#define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /*!< UCSTPNACK Bit Offset */ -#define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /*!< ACK all master bytes */ -/* EUSCI_B_CTLW1[CLTO] Bits */ -#define EUSCI_B_CTLW1_CLTO_OFS ( 6) /*!< UCCLTO Bit Offset */ -#define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /*!< UCCLTO Bit Mask */ -#define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /*!< CLTO Bit 0 */ -#define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /*!< CLTO Bit 1 */ -#define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /*!< Disable clock low timeout counter */ -#define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ -#define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ -#define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ -/* EUSCI_B_CTLW1[ETXINT] Bits */ -#define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /*!< UCETXINT Bit Offset */ -#define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /*!< Early UCTXIFG0 */ -/* EUSCI_B_STATW[BBUSY] Bits */ -#define EUSCI_B_STATW_BBUSY_OFS ( 4) /*!< UCBBUSY Bit Offset */ -#define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /*!< Bus busy */ -/* EUSCI_B_STATW[GC] Bits */ -#define EUSCI_B_STATW_GC_OFS ( 5) /*!< UCGC Bit Offset */ -#define EUSCI_B_STATW_GC ((uint16_t)0x0020) /*!< General call address received */ -/* EUSCI_B_STATW[SCLLOW] Bits */ -#define EUSCI_B_STATW_SCLLOW_OFS ( 6) /*!< UCSCLLOW Bit Offset */ -#define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /*!< SCL low */ -/* EUSCI_B_STATW[BCNT] Bits */ -#define EUSCI_B_STATW_BCNT_OFS ( 8) /*!< UCBCNT Bit Offset */ -#define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /*!< UCBCNT Bit Mask */ -/* EUSCI_B_STATW[SPI_BUSY] Bits */ -#define EUSCI_B_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_B_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_B busy */ -/* EUSCI_B_STATW[OE] Bits */ -#define EUSCI_B_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_B_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -/* EUSCI_B_STATW[FE] Bits */ -#define EUSCI_B_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_B_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -/* EUSCI_B_STATW[LISTEN] Bits */ -#define EUSCI_B_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -/* EUSCI_B_TBCNT[TBCNT] Bits */ -#define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /*!< UCTBCNT Bit Offset */ -#define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /*!< UCTBCNT Bit Mask */ -/* EUSCI_B_RXBUF[RXBUF] Bits */ -#define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -/* EUSCI_B_TXBUF[TXBUF] Bits */ -#define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -/* EUSCI_B_I2COA0[I2COA0] Bits */ -#define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /*!< I2COA0 Bit Offset */ -#define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /*!< I2COA0 Bit Mask */ -/* EUSCI_B_I2COA0[OAEN] Bits */ -#define EUSCI_B_I2COA0_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA0[GCEN] Bits */ -#define EUSCI_B_I2COA0_GCEN_OFS (15) /*!< UCGCEN Bit Offset */ -#define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /*!< General call response enable */ -/* EUSCI_B_I2COA1[I2COA1] Bits */ -#define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /*!< I2COA1 Bit Offset */ -#define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /*!< I2COA1 Bit Mask */ -/* EUSCI_B_I2COA1[OAEN] Bits */ -#define EUSCI_B_I2COA1_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA2[I2COA2] Bits */ -#define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /*!< I2COA2 Bit Offset */ -#define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /*!< I2COA2 Bit Mask */ -/* EUSCI_B_I2COA2[OAEN] Bits */ -#define EUSCI_B_I2COA2_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_I2COA3[I2COA3] Bits */ -#define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /*!< I2COA3 Bit Offset */ -#define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /*!< I2COA3 Bit Mask */ -/* EUSCI_B_I2COA3[OAEN] Bits */ -#define EUSCI_B_I2COA3_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -/* EUSCI_B_ADDRX[ADDRX] Bits */ -#define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /*!< ADDRX Bit Offset */ -#define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /*!< ADDRX Bit Mask */ -#define EUSCI_B_ADDRX_ADDRX0 ((uint16_t)0x0001) /*!< ADDRX Bit 0 */ -#define EUSCI_B_ADDRX_ADDRX1 ((uint16_t)0x0002) /*!< ADDRX Bit 1 */ -#define EUSCI_B_ADDRX_ADDRX2 ((uint16_t)0x0004) /*!< ADDRX Bit 2 */ -#define EUSCI_B_ADDRX_ADDRX3 ((uint16_t)0x0008) /*!< ADDRX Bit 3 */ -#define EUSCI_B_ADDRX_ADDRX4 ((uint16_t)0x0010) /*!< ADDRX Bit 4 */ -#define EUSCI_B_ADDRX_ADDRX5 ((uint16_t)0x0020) /*!< ADDRX Bit 5 */ -#define EUSCI_B_ADDRX_ADDRX6 ((uint16_t)0x0040) /*!< ADDRX Bit 6 */ -#define EUSCI_B_ADDRX_ADDRX7 ((uint16_t)0x0080) /*!< ADDRX Bit 7 */ -#define EUSCI_B_ADDRX_ADDRX8 ((uint16_t)0x0100) /*!< ADDRX Bit 8 */ -#define EUSCI_B_ADDRX_ADDRX9 ((uint16_t)0x0200) /*!< ADDRX Bit 9 */ -/* EUSCI_B_ADDMASK[ADDMASK] Bits */ -#define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /*!< ADDMASK Bit Offset */ -#define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /*!< ADDMASK Bit Mask */ -/* EUSCI_B_I2CSA[I2CSA] Bits */ -#define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /*!< I2CSA Bit Offset */ -#define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /*!< I2CSA Bit Mask */ -/* EUSCI_B_IE[RXIE0] Bits */ -#define EUSCI_B_IE_RXIE0_OFS ( 0) /*!< UCRXIE0 Bit Offset */ -#define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /*!< Receive interrupt enable 0 */ -/* EUSCI_B_IE[TXIE0] Bits */ -#define EUSCI_B_IE_TXIE0_OFS ( 1) /*!< UCTXIE0 Bit Offset */ -#define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /*!< Transmit interrupt enable 0 */ -/* EUSCI_B_IE[STTIE] Bits */ -#define EUSCI_B_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /*!< START condition interrupt enable */ -/* EUSCI_B_IE[STPIE] Bits */ -#define EUSCI_B_IE_STPIE_OFS ( 3) /*!< UCSTPIE Bit Offset */ -#define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /*!< STOP condition interrupt enable */ -/* EUSCI_B_IE[ALIE] Bits */ -#define EUSCI_B_IE_ALIE_OFS ( 4) /*!< UCALIE Bit Offset */ -#define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /*!< Arbitration lost interrupt enable */ -/* EUSCI_B_IE[NACKIE] Bits */ -#define EUSCI_B_IE_NACKIE_OFS ( 5) /*!< UCNACKIE Bit Offset */ -#define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /*!< Not-acknowledge interrupt enable */ -/* EUSCI_B_IE[BCNTIE] Bits */ -#define EUSCI_B_IE_BCNTIE_OFS ( 6) /*!< UCBCNTIE Bit Offset */ -#define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /*!< Byte counter interrupt enable */ -/* EUSCI_B_IE[CLTOIE] Bits */ -#define EUSCI_B_IE_CLTOIE_OFS ( 7) /*!< UCCLTOIE Bit Offset */ -#define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /*!< Clock low timeout interrupt enable */ -/* EUSCI_B_IE[RXIE1] Bits */ -#define EUSCI_B_IE_RXIE1_OFS ( 8) /*!< UCRXIE1 Bit Offset */ -#define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /*!< Receive interrupt enable 1 */ -/* EUSCI_B_IE[TXIE1] Bits */ -#define EUSCI_B_IE_TXIE1_OFS ( 9) /*!< UCTXIE1 Bit Offset */ -#define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /*!< Transmit interrupt enable 1 */ -/* EUSCI_B_IE[RXIE2] Bits */ -#define EUSCI_B_IE_RXIE2_OFS (10) /*!< UCRXIE2 Bit Offset */ -#define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /*!< Receive interrupt enable 2 */ -/* EUSCI_B_IE[TXIE2] Bits */ -#define EUSCI_B_IE_TXIE2_OFS (11) /*!< UCTXIE2 Bit Offset */ -#define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /*!< Transmit interrupt enable 2 */ -/* EUSCI_B_IE[RXIE3] Bits */ -#define EUSCI_B_IE_RXIE3_OFS (12) /*!< UCRXIE3 Bit Offset */ -#define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /*!< Receive interrupt enable 3 */ -/* EUSCI_B_IE[TXIE3] Bits */ -#define EUSCI_B_IE_TXIE3_OFS (13) /*!< UCTXIE3 Bit Offset */ -#define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /*!< Transmit interrupt enable 3 */ -/* EUSCI_B_IE[BIT9IE] Bits */ -#define EUSCI_B_IE_BIT9IE_OFS (14) /*!< UCBIT9IE Bit Offset */ -#define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /*!< Bit position 9 interrupt enable */ -/* EUSCI_B_IE[RXIE] Bits */ -#define EUSCI_B_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_B_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -/* EUSCI_B_IE[TXIE] Bits */ -#define EUSCI_B_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_B_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -/* EUSCI_B_IFG[RXIFG0] Bits */ -#define EUSCI_B_IFG_RXIFG0_OFS ( 0) /*!< UCRXIFG0 Bit Offset */ -#define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /*!< eUSCI_B receive interrupt flag 0 */ -/* EUSCI_B_IFG[TXIFG0] Bits */ -#define EUSCI_B_IFG_TXIFG0_OFS ( 1) /*!< UCTXIFG0 Bit Offset */ -#define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /*!< eUSCI_B transmit interrupt flag 0 */ -/* EUSCI_B_IFG[STTIFG] Bits */ -#define EUSCI_B_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /*!< START condition interrupt flag */ -/* EUSCI_B_IFG[STPIFG] Bits */ -#define EUSCI_B_IFG_STPIFG_OFS ( 3) /*!< UCSTPIFG Bit Offset */ -#define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /*!< STOP condition interrupt flag */ -/* EUSCI_B_IFG[ALIFG] Bits */ -#define EUSCI_B_IFG_ALIFG_OFS ( 4) /*!< UCALIFG Bit Offset */ -#define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /*!< Arbitration lost interrupt flag */ -/* EUSCI_B_IFG[NACKIFG] Bits */ -#define EUSCI_B_IFG_NACKIFG_OFS ( 5) /*!< UCNACKIFG Bit Offset */ -#define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /*!< Not-acknowledge received interrupt flag */ -/* EUSCI_B_IFG[BCNTIFG] Bits */ -#define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /*!< UCBCNTIFG Bit Offset */ -#define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /*!< Byte counter interrupt flag */ -/* EUSCI_B_IFG[CLTOIFG] Bits */ -#define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /*!< UCCLTOIFG Bit Offset */ -#define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /*!< Clock low timeout interrupt flag */ -/* EUSCI_B_IFG[RXIFG1] Bits */ -#define EUSCI_B_IFG_RXIFG1_OFS ( 8) /*!< UCRXIFG1 Bit Offset */ -#define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /*!< eUSCI_B receive interrupt flag 1 */ -/* EUSCI_B_IFG[TXIFG1] Bits */ -#define EUSCI_B_IFG_TXIFG1_OFS ( 9) /*!< UCTXIFG1 Bit Offset */ -#define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /*!< eUSCI_B transmit interrupt flag 1 */ -/* EUSCI_B_IFG[RXIFG2] Bits */ -#define EUSCI_B_IFG_RXIFG2_OFS (10) /*!< UCRXIFG2 Bit Offset */ -#define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /*!< eUSCI_B receive interrupt flag 2 */ -/* EUSCI_B_IFG[TXIFG2] Bits */ -#define EUSCI_B_IFG_TXIFG2_OFS (11) /*!< UCTXIFG2 Bit Offset */ -#define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /*!< eUSCI_B transmit interrupt flag 2 */ -/* EUSCI_B_IFG[RXIFG3] Bits */ -#define EUSCI_B_IFG_RXIFG3_OFS (12) /*!< UCRXIFG3 Bit Offset */ -#define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /*!< eUSCI_B receive interrupt flag 3 */ -/* EUSCI_B_IFG[TXIFG3] Bits */ -#define EUSCI_B_IFG_TXIFG3_OFS (13) /*!< UCTXIFG3 Bit Offset */ -#define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /*!< eUSCI_B transmit interrupt flag 3 */ -/* EUSCI_B_IFG[BIT9IFG] Bits */ -#define EUSCI_B_IFG_BIT9IFG_OFS (14) /*!< UCBIT9IFG Bit Offset */ -#define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /*!< Bit position 9 interrupt flag */ -/* EUSCI_B_IFG[RXIFG] Bits */ -#define EUSCI_B_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -/* EUSCI_B_IFG[TXIFG] Bits */ -#define EUSCI_B_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -/* legacy definitions for backward compatibility to version 2100 */ -#define EUSCI_B__RXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_B__RXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_B__TXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_B__TXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ - - -/****************************************************************************** -* FLCTL_A Bits -******************************************************************************/ -/* FLCTL_A_POWER_STAT[PSTAT] Bits */ -#define FLCTL_A_POWER_STAT_PSTAT_OFS ( 0) /*!< PSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /*!< PSTAT Bit Mask */ -#define FLCTL_A_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /*!< PSTAT Bit 0 */ -#define FLCTL_A_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /*!< PSTAT Bit 1 */ -#define FLCTL_A_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /*!< PSTAT Bit 2 */ -#define FLCTL_A_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /*!< Flash IP in power-down mode */ -#define FLCTL_A_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /*!< Flash IP Vdd domain power-up in progress */ -#define FLCTL_A_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */ -#define FLCTL_A_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /*!< Flash IP SAFE_LV check in progress */ -#define FLCTL_A_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /*!< Flash IP Active */ -#define FLCTL_A_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */ -#define FLCTL_A_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /*!< Flash IP in Standby mode */ -#define FLCTL_A_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /*!< Flash IP in Current mirror boost state */ -/* FLCTL_A_POWER_STAT[LDOSTAT] Bits */ -#define FLCTL_A_POWER_STAT_LDOSTAT_OFS ( 3) /*!< LDOSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /*!< PSS FLDO GOOD status */ -/* FLCTL_A_POWER_STAT[VREFSTAT] Bits */ -#define FLCTL_A_POWER_STAT_VREFSTAT_OFS ( 4) /*!< VREFSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /*!< PSS VREF stable status */ -/* FLCTL_A_POWER_STAT[IREFSTAT] Bits */ -#define FLCTL_A_POWER_STAT_IREFSTAT_OFS ( 5) /*!< IREFSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /*!< PSS IREF stable status */ -/* FLCTL_A_POWER_STAT[TRIMSTAT] Bits */ -#define FLCTL_A_POWER_STAT_TRIMSTAT_OFS ( 6) /*!< TRIMSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /*!< PSS trim done status */ -/* FLCTL_A_POWER_STAT[RD_2T] Bits */ -#define FLCTL_A_POWER_STAT_RD_2T_OFS ( 7) /*!< RD_2T Bit Offset */ -#define FLCTL_A_POWER_STAT_RD_2T ((uint32_t)0x00000080) /*!< Indicates if Flash is being accessed in 2T mode */ -/* FLCTL_A_BANK0_RDCTL[RD_MODE] Bits */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -/* FLCTL_A_BANK0_RDCTL[BUFI] Bits */ -#define FLCTL_A_BANK0_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -/* FLCTL_A_BANK0_RDCTL[BUFD] Bits */ -#define FLCTL_A_BANK0_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -/* FLCTL_A_BANK0_RDCTL[WAIT] Bits */ -#define FLCTL_A_BANK0_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_A_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_A_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_A_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_A_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_A_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -/* FLCTL_A_BANK0_RDCTL[RD_MODE_STATUS] Bits */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -/* FLCTL_A_BANK1_RDCTL[RD_MODE] Bits */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -/* FLCTL_A_BANK1_RDCTL[BUFI] Bits */ -#define FLCTL_A_BANK1_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -/* FLCTL_A_BANK1_RDCTL[BUFD] Bits */ -#define FLCTL_A_BANK1_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -/* FLCTL_A_BANK1_RDCTL[RD_MODE_STATUS] Bits */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -/* FLCTL_A_BANK1_RDCTL[WAIT] Bits */ -#define FLCTL_A_BANK1_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_A_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_A_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_A_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_A_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_A_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -/* FLCTL_A_RDBRST_CTLSTAT[START] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of burst/compare operation */ -/* FLCTL_A_RDBRST_CTLSTAT[MEM_TYPE] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /*!< MEM_TYPE Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /*!< MEM_TYPE Bit Mask */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /*!< MEM_TYPE Bit 0 */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /*!< MEM_TYPE Bit 1 */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -/* FLCTL_A_RDBRST_CTLSTAT[STOP_FAIL] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /*!< STOP_FAIL Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /*!< Terminate burst/compare operation */ -/* FLCTL_A_RDBRST_CTLSTAT[DATA_CMP] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /*!< DATA_CMP Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /*!< Data pattern used for comparison against memory read data */ -/* FLCTL_A_RDBRST_CTLSTAT[TEST_EN] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /*!< TEST_EN Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /*!< Enable comparison against test data compare registers */ -/* FLCTL_A_RDBRST_CTLSTAT[BRST_STAT] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /*!< BRST_STAT Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /*!< BRST_STAT Bit Mask */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /*!< BRST_STAT Bit 0 */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /*!< BRST_STAT Bit 1 */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /*!< Idle */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /*!< Burst/Compare START bit written, but operation pending */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /*!< Burst/Compare in progress */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /*!< Burst complete (status of completed burst remains in this state unless */ - /* explicitly cleared by SW) */ -/* FLCTL_A_RDBRST_CTLSTAT[CMP_ERR] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /*!< CMP_ERR Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /*!< Burst/Compare Operation encountered atleast one data */ -/* FLCTL_A_RDBRST_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /*!< Burst/Compare Operation was terminated due to access to */ -/* FLCTL_A_RDBRST_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 19-16 of this register */ -/* FLCTL_A_RDBRST_STARTADDR[START_ADDRESS] Bits */ -#define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< START_ADDRESS Bit Mask */ -/* FLCTL_A_RDBRST_LEN[BURST_LENGTH] Bits */ -#define FLCTL_A_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /*!< BURST_LENGTH Bit Offset */ -#define FLCTL_A_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /*!< BURST_LENGTH Bit Mask */ -/* FLCTL_A_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */ -#define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /*!< FAIL_ADDRESS Bit Offset */ -#define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< FAIL_ADDRESS Bit Mask */ -/* FLCTL_A_RDBRST_FAILCNT[FAIL_COUNT] Bits */ -#define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /*!< FAIL_COUNT Bit Offset */ -#define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /*!< FAIL_COUNT Bit Mask */ -/* FLCTL_A_PRG_CTLSTAT[ENABLE] Bits */ -#define FLCTL_A_PRG_CTLSTAT_ENABLE_OFS ( 0) /*!< ENABLE Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /*!< Master control for all word program operations */ -/* FLCTL_A_PRG_CTLSTAT[MODE] Bits */ -#define FLCTL_A_PRG_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Write mode */ -/* FLCTL_A_PRG_CTLSTAT[VER_PRE] Bits */ -#define FLCTL_A_PRG_CTLSTAT_VER_PRE_OFS ( 2) /*!< VER_PRE Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /*!< Controls automatic pre program verify operations */ -/* FLCTL_A_PRG_CTLSTAT[VER_PST] Bits */ -#define FLCTL_A_PRG_CTLSTAT_VER_PST_OFS ( 3) /*!< VER_PST Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /*!< Controls automatic post program verify operations */ -/* FLCTL_A_PRG_CTLSTAT[STATUS] Bits */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_A_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_A_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Single word program operation triggered, but pending */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Single word program in progress */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Reserved (Idle) */ -/* FLCTL_A_PRG_CTLSTAT[BNK_ACT] Bits */ -#define FLCTL_A_PRG_CTLSTAT_BNK_ACT_OFS (18) /*!< BNK_ACT Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /*!< Bank active */ -/* FLCTL_A_PRGBRST_CTLSTAT[START] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Trigger start of burst program operation */ -/* FLCTL_A_PRGBRST_CTLSTAT[TYPE] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /*!< TYPE Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /*!< TYPE Bit Mask */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /*!< TYPE Bit 0 */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /*!< TYPE Bit 1 */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -/* FLCTL_A_PRGBRST_CTLSTAT[LEN] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_OFS ( 3) /*!< LEN Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /*!< LEN Bit Mask */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /*!< LEN Bit 0 */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /*!< LEN Bit 1 */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /*!< LEN Bit 2 */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /*!< No burst operation */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /*!< 1 word burst of 128 bits, starting with address in the */ - /* FLCTL_PRGBRST_STARTADDR Register */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ - /* Register */ -/* FLCTL_A_PRGBRST_CTLSTAT[AUTO_PRE] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /*!< AUTO_PRE Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /*!< Auto-Verify operation before the Burst Program */ -/* FLCTL_A_PRGBRST_CTLSTAT[AUTO_PST] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /*!< AUTO_PST Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /*!< Auto-Verify operation after the Burst Program */ -/* FLCTL_A_PRGBRST_CTLSTAT[BURST_STATUS] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /*!< BURST_STATUS Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /*!< BURST_STATUS Bit Mask */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /*!< BURST_STATUS Bit 0 */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /*!< BURST_STATUS Bit 1 */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /*!< BURST_STATUS Bit 2 */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (Burst not active) */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /*!< Burst program started but pending */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /*!< Burst active, with 1st 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /*!< Burst active, with 2nd 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /*!< Burst active, with 3rd 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /*!< Burst active, with 4th 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /*!< Reserved (Idle) */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /*!< Burst Complete (status of completed burst remains in this state unless */ - /* explicitly cleared by SW) */ -/* FLCTL_A_PRGBRST_CTLSTAT[PRE_ERR] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /*!< PRE_ERR Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /*!< Burst Operation encountered preprogram auto-verify errors */ -/* FLCTL_A_PRGBRST_CTLSTAT[PST_ERR] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /*!< PST_ERR Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /*!< Burst Operation encountered postprogram auto-verify errors */ -/* FLCTL_A_PRGBRST_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /*!< Burst Operation was terminated due to attempted program of reserved memory */ -/* FLCTL_A_PRGBRST_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 21-16 of this register */ -/* FLCTL_A_PRGBRST_STARTADDR[START_ADDRESS] Bits */ -#define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< START_ADDRESS Bit Mask */ -/* FLCTL_A_ERASE_CTLSTAT[START] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of Erase operation */ -/* FLCTL_A_ERASE_CTLSTAT[MODE] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Erase mode selected by application */ -/* FLCTL_A_ERASE_CTLSTAT[TYPE] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_OFS ( 2) /*!< TYPE Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /*!< TYPE Bit Mask */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /*!< TYPE Bit 0 */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /*!< TYPE Bit 1 */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /*!< Information Memory */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /*!< Reserved */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /*!< Engineering Memory */ -/* FLCTL_A_ERASE_CTLSTAT[STATUS] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Erase operation triggered to START but pending */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Erase operation in progress */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Erase operation completed (status of completed erase remains in this state */ - /* unless explicitly cleared by SW) */ -/* FLCTL_A_ERASE_CTLSTAT[ADDR_ERR] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /*!< Erase Operation was terminated due to attempted erase of reserved memory */ - /* address */ -/* FLCTL_A_ERASE_CTLSTAT[CLR_STAT] Bits */ -#define FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS (19) /*!< CLR_STAT Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /*!< Clear status bits 18-16 of this register */ -/* FLCTL_A_ERASE_SECTADDR[SECT_ADDRESS] Bits */ -#define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /*!< SECT_ADDRESS Bit Offset */ -#define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< SECT_ADDRESS Bit Mask */ -/* FLCTL_A_BANK0_INFO_WEPROT[PROT0] Bits */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_A_BANK0_INFO_WEPROT[PROT1] Bits */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_A_BANK0_INFO_WEPROT[PROT2] Bits */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK0_INFO_WEPROT[PROT3] Bits */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT0] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT1] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT2] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT3] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT4] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT5] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT6] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT7] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT8] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT9] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT10] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT11] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT12] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT13] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT14] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT15] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT16] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT17] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT18] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT19] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT20] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT21] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT22] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT23] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT24] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT25] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT26] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT27] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT28] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT29] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT30] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT[PROT31] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -/* FLCTL_A_BANK1_INFO_WEPROT[PROT0] Bits */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -/* FLCTL_A_BANK1_INFO_WEPROT[PROT1] Bits */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -/* FLCTL_A_BANK1_INFO_WEPROT[PROT2] Bits */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK1_INFO_WEPROT[PROT3] Bits */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT0] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT1] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT2] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT3] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT4] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT5] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT6] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT7] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT8] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT9] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT10] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT11] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT12] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT13] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT14] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT15] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT16] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT17] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT18] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT19] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT20] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT21] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT22] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT23] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT24] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT25] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT26] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT27] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT28] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT29] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT30] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase operations */ -/* FLCTL_A_BANK1_MAIN_WEPROT[PROT31] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase operations */ -/* FLCTL_A_BMRK_CTLSTAT[I_BMRK] Bits */ -#define FLCTL_A_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /*!< I_BMRK Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001) -/* FLCTL_A_BMRK_CTLSTAT[D_BMRK] Bits */ -#define FLCTL_A_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /*!< D_BMRK Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002) -/* FLCTL_A_BMRK_CTLSTAT[CMP_EN] Bits */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /*!< CMP_EN Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004) -/* FLCTL_A_BMRK_CTLSTAT[CMP_SEL] Bits */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /*!< CMP_SEL Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008) -/* FLCTL_A_IFG[RDBRST] Bits */ -#define FLCTL_A_IFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_IFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_A_IFG[AVPRE] Bits */ -#define FLCTL_A_IFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_IFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_A_IFG[AVPST] Bits */ -#define FLCTL_A_IFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_IFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_A_IFG[PRG] Bits */ -#define FLCTL_A_IFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_IFG_PRG ((uint32_t)0x00000008) -/* FLCTL_A_IFG[PRGB] Bits */ -#define FLCTL_A_IFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_IFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_A_IFG[ERASE] Bits */ -#define FLCTL_A_IFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_IFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_A_IFG[BMRK] Bits */ -#define FLCTL_A_IFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_IFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_A_IFG[PRG_ERR] Bits */ -#define FLCTL_A_IFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_IFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_A_IE[RDBRST] Bits */ -#define FLCTL_A_IE_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_IE_RDBRST ((uint32_t)0x00000001) -/* FLCTL_A_IE[AVPRE] Bits */ -#define FLCTL_A_IE_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_IE_AVPRE ((uint32_t)0x00000002) -/* FLCTL_A_IE[AVPST] Bits */ -#define FLCTL_A_IE_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_IE_AVPST ((uint32_t)0x00000004) -/* FLCTL_A_IE[PRG] Bits */ -#define FLCTL_A_IE_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_IE_PRG ((uint32_t)0x00000008) -/* FLCTL_A_IE[PRGB] Bits */ -#define FLCTL_A_IE_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_IE_PRGB ((uint32_t)0x00000010) -/* FLCTL_A_IE[ERASE] Bits */ -#define FLCTL_A_IE_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_IE_ERASE ((uint32_t)0x00000020) -/* FLCTL_A_IE[BMRK] Bits */ -#define FLCTL_A_IE_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_IE_BMRK ((uint32_t)0x00000100) -/* FLCTL_A_IE[PRG_ERR] Bits */ -#define FLCTL_A_IE_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_IE_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_A_CLRIFG[RDBRST] Bits */ -#define FLCTL_A_CLRIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_CLRIFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_A_CLRIFG[AVPRE] Bits */ -#define FLCTL_A_CLRIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_CLRIFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_A_CLRIFG[AVPST] Bits */ -#define FLCTL_A_CLRIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_CLRIFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_A_CLRIFG[PRG] Bits */ -#define FLCTL_A_CLRIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_CLRIFG_PRG ((uint32_t)0x00000008) -/* FLCTL_A_CLRIFG[PRGB] Bits */ -#define FLCTL_A_CLRIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_CLRIFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_A_CLRIFG[ERASE] Bits */ -#define FLCTL_A_CLRIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_CLRIFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_A_CLRIFG[BMRK] Bits */ -#define FLCTL_A_CLRIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_CLRIFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_A_CLRIFG[PRG_ERR] Bits */ -#define FLCTL_A_CLRIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_CLRIFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_A_SETIFG[RDBRST] Bits */ -#define FLCTL_A_SETIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_SETIFG_RDBRST ((uint32_t)0x00000001) -/* FLCTL_A_SETIFG[AVPRE] Bits */ -#define FLCTL_A_SETIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_SETIFG_AVPRE ((uint32_t)0x00000002) -/* FLCTL_A_SETIFG[AVPST] Bits */ -#define FLCTL_A_SETIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_SETIFG_AVPST ((uint32_t)0x00000004) -/* FLCTL_A_SETIFG[PRG] Bits */ -#define FLCTL_A_SETIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_SETIFG_PRG ((uint32_t)0x00000008) -/* FLCTL_A_SETIFG[PRGB] Bits */ -#define FLCTL_A_SETIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_SETIFG_PRGB ((uint32_t)0x00000010) -/* FLCTL_A_SETIFG[ERASE] Bits */ -#define FLCTL_A_SETIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_SETIFG_ERASE ((uint32_t)0x00000020) -/* FLCTL_A_SETIFG[BMRK] Bits */ -#define FLCTL_A_SETIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_SETIFG_BMRK ((uint32_t)0x00000100) -/* FLCTL_A_SETIFG[PRG_ERR] Bits */ -#define FLCTL_A_SETIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_SETIFG_PRG_ERR ((uint32_t)0x00000200) -/* FLCTL_A_READ_TIMCTL[SETUP] Bits */ -#define FLCTL_A_READ_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_READ_TIMCTL[IREF_BOOST1] Bits */ -#define FLCTL_A_READ_TIMCTL_IREF_BOOST1_OFS (12) /*!< IREF_BOOST1 Bit Offset */ -#define FLCTL_A_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /*!< IREF_BOOST1 Bit Mask */ -/* FLCTL_A_READ_TIMCTL[SETUP_LONG] Bits */ -#define FLCTL_A_READ_TIMCTL_SETUP_LONG_OFS (16) /*!< SETUP_LONG Bit Offset */ -#define FLCTL_A_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /*!< SETUP_LONG Bit Mask */ -/* FLCTL_A_READMARGIN_TIMCTL[SETUP] Bits */ -#define FLCTL_A_READMARGIN_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_PRGVER_TIMCTL[SETUP] Bits */ -#define FLCTL_A_PRGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_PRGVER_TIMCTL[ACTIVE] Bits */ -#define FLCTL_A_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /*!< ACTIVE Bit Mask */ -/* FLCTL_A_PRGVER_TIMCTL[HOLD] Bits */ -#define FLCTL_A_PRGVER_TIMCTL_HOLD_OFS (12) /*!< HOLD Bit Offset */ -#define FLCTL_A_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /*!< HOLD Bit Mask */ -/* FLCTL_A_ERSVER_TIMCTL[SETUP] Bits */ -#define FLCTL_A_ERSVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_LKGVER_TIMCTL[SETUP] Bits */ -#define FLCTL_A_LKGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_PROGRAM_TIMCTL[SETUP] Bits */ -#define FLCTL_A_PROGRAM_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_PROGRAM_TIMCTL[ACTIVE] Bits */ -#define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_A_PROGRAM_TIMCTL[HOLD] Bits */ -#define FLCTL_A_PROGRAM_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_A_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -/* FLCTL_A_ERASE_TIMCTL[SETUP] Bits */ -#define FLCTL_A_ERASE_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -/* FLCTL_A_ERASE_TIMCTL[ACTIVE] Bits */ -#define FLCTL_A_ERASE_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_A_ERASE_TIMCTL[HOLD] Bits */ -#define FLCTL_A_ERASE_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_A_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -/* FLCTL_A_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /*!< BOOST_ACTIVE Bit Offset */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /*!< BOOST_ACTIVE Bit Mask */ -/* FLCTL_A_MASSERASE_TIMCTL[BOOST_HOLD] Bits */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /*!< BOOST_HOLD Bit Offset */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /*!< BOOST_HOLD Bit Mask */ -/* FLCTL_A_BURSTPRG_TIMCTL[ACTIVE] Bits */ -#define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT0] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT1] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT2] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT3] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT4] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT5] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT6] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT7] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT8] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT9] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT10] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT11] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT12] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT13] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT14] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT15] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT16] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT17] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT18] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT19] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT20] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT21] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT22] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT23] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT24] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT25] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT26] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT27] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT28] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT29] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT30] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT0[PROT31] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT32] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32_OFS ( 0) /*!< PROT32 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32 ((uint32_t)0x00000001) /*!< Protects Sector 32 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT33] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33_OFS ( 1) /*!< PROT33 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33 ((uint32_t)0x00000002) /*!< Protects Sector 33 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT34] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34_OFS ( 2) /*!< PROT34 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34 ((uint32_t)0x00000004) /*!< Protects Sector 34 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT35] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35_OFS ( 3) /*!< PROT35 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35 ((uint32_t)0x00000008) /*!< Protects Sector 35 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT36] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36_OFS ( 4) /*!< PROT36 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36 ((uint32_t)0x00000010) /*!< Protects Sector 36 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT37] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37_OFS ( 5) /*!< PROT37 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37 ((uint32_t)0x00000020) /*!< Protects Sector 37 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT38] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38_OFS ( 6) /*!< PROT38 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38 ((uint32_t)0x00000040) /*!< Protects Sector 38 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT39] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39_OFS ( 7) /*!< PROT39 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39 ((uint32_t)0x00000080) /*!< Protects Sector 39 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT40] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40_OFS ( 8) /*!< PROT40 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40 ((uint32_t)0x00000100) /*!< Protects Sector 40 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT41] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41_OFS ( 9) /*!< PROT41 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41 ((uint32_t)0x00000200) /*!< Protects Sector 41 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT42] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42_OFS (10) /*!< PROT42 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42 ((uint32_t)0x00000400) /*!< Protects Sector 42 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT43] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43_OFS (11) /*!< PROT43 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43 ((uint32_t)0x00000800) /*!< Protects Sector 43 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT44] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44_OFS (12) /*!< PROT44 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44 ((uint32_t)0x00001000) /*!< Protects Sector 44 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT45] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45_OFS (13) /*!< PROT45 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45 ((uint32_t)0x00002000) /*!< Protects Sector 45 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT46] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46_OFS (14) /*!< PROT46 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46 ((uint32_t)0x00004000) /*!< Protects Sector 46 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT47] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47_OFS (15) /*!< PROT47 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47 ((uint32_t)0x00008000) /*!< Protects Sector 47 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT48] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48_OFS (16) /*!< PROT48 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48 ((uint32_t)0x00010000) /*!< Protects Sector 48 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT49] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49_OFS (17) /*!< PROT49 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49 ((uint32_t)0x00020000) /*!< Protects Sector 49 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT50] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50_OFS (18) /*!< PROT50 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50 ((uint32_t)0x00040000) /*!< Protects Sector 50 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT51] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51_OFS (19) /*!< PROT51 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51 ((uint32_t)0x00080000) /*!< Protects Sector 51 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT52] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52_OFS (20) /*!< PROT52 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52 ((uint32_t)0x00100000) /*!< Protects Sector 52 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT53] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53_OFS (21) /*!< PROT53 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53 ((uint32_t)0x00200000) /*!< Protects Sector 53 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT54] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54_OFS (22) /*!< PROT54 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54 ((uint32_t)0x00400000) /*!< Protects Sector 54 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT55] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55_OFS (23) /*!< PROT55 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55 ((uint32_t)0x00800000) /*!< Protects Sector 55 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT56] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56_OFS (24) /*!< PROT56 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56 ((uint32_t)0x01000000) /*!< Protects Sector 56 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT57] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57_OFS (25) /*!< PROT57 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57 ((uint32_t)0x02000000) /*!< Protects Sector 57 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT58] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58_OFS (26) /*!< PROT58 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58 ((uint32_t)0x04000000) /*!< Protects Sector 58 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT59] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59_OFS (27) /*!< PROT59 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59 ((uint32_t)0x08000000) /*!< Protects Sector 59 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT60] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60_OFS (28) /*!< PROT60 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60 ((uint32_t)0x10000000) /*!< Protects Sector 60 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT61] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61_OFS (29) /*!< PROT61 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61 ((uint32_t)0x20000000) /*!< Protects Sector 61 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT62] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62_OFS (30) /*!< PROT62 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62 ((uint32_t)0x40000000) /*!< Protects Sector 62 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT1[PROT63] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63_OFS (31) /*!< PROT63 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63 ((uint32_t)0x80000000) /*!< Protects Sector 63 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT64] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64_OFS ( 0) /*!< PROT64 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64 ((uint32_t)0x00000001) /*!< Protects Sector 64 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT65] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65_OFS ( 1) /*!< PROT65 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65 ((uint32_t)0x00000002) /*!< Protects Sector 65 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT66] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66_OFS ( 2) /*!< PROT66 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66 ((uint32_t)0x00000004) /*!< Protects Sector 66 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT67] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67_OFS ( 3) /*!< PROT67 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67 ((uint32_t)0x00000008) /*!< Protects Sector 67 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT68] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68_OFS ( 4) /*!< PROT68 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68 ((uint32_t)0x00000010) /*!< Protects Sector 68 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT69] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69_OFS ( 5) /*!< PROT69 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69 ((uint32_t)0x00000020) /*!< Protects Sector 69 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT70] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70_OFS ( 6) /*!< PROT70 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70 ((uint32_t)0x00000040) /*!< Protects Sector 70 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT71] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71_OFS ( 7) /*!< PROT71 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71 ((uint32_t)0x00000080) /*!< Protects Sector 71 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT72] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72_OFS ( 8) /*!< PROT72 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72 ((uint32_t)0x00000100) /*!< Protects Sector 72 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT73] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73_OFS ( 9) /*!< PROT73 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73 ((uint32_t)0x00000200) /*!< Protects Sector 73 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT74] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74_OFS (10) /*!< PROT74 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74 ((uint32_t)0x00000400) /*!< Protects Sector 74 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT75] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75_OFS (11) /*!< PROT75 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75 ((uint32_t)0x00000800) /*!< Protects Sector 75 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT76] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76_OFS (12) /*!< PROT76 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76 ((uint32_t)0x00001000) /*!< Protects Sector 76 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT77] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77_OFS (13) /*!< PROT77 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77 ((uint32_t)0x00002000) /*!< Protects Sector 77 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT78] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78_OFS (14) /*!< PROT78 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78 ((uint32_t)0x00004000) /*!< Protects Sector 78 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT79] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79_OFS (15) /*!< PROT79 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79 ((uint32_t)0x00008000) /*!< Protects Sector 79 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT80] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80_OFS (16) /*!< PROT80 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80 ((uint32_t)0x00010000) /*!< Protects Sector 80 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT81] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81_OFS (17) /*!< PROT81 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81 ((uint32_t)0x00020000) /*!< Protects Sector 81 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT82] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82_OFS (18) /*!< PROT82 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82 ((uint32_t)0x00040000) /*!< Protects Sector 82 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT83] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83_OFS (19) /*!< PROT83 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83 ((uint32_t)0x00080000) /*!< Protects Sector 83 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT84] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84_OFS (20) /*!< PROT84 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84 ((uint32_t)0x00100000) /*!< Protects Sector 84 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT85] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85_OFS (21) /*!< PROT85 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85 ((uint32_t)0x00200000) /*!< Protects Sector 85 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT86] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86_OFS (22) /*!< PROT86 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86 ((uint32_t)0x00400000) /*!< Protects Sector 86 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT87] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87_OFS (23) /*!< PROT87 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87 ((uint32_t)0x00800000) /*!< Protects Sector 87 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT88] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88_OFS (24) /*!< PROT88 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88 ((uint32_t)0x01000000) /*!< Protects Sector 88 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT89] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89_OFS (25) /*!< PROT89 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89 ((uint32_t)0x02000000) /*!< Protects Sector 89 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT90] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90_OFS (26) /*!< PROT90 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90 ((uint32_t)0x04000000) /*!< Protects Sector 90 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT91] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91_OFS (27) /*!< PROT91 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91 ((uint32_t)0x08000000) /*!< Protects Sector 91 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT92] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92_OFS (28) /*!< PROT92 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92 ((uint32_t)0x10000000) /*!< Protects Sector 92 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT93] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93_OFS (29) /*!< PROT93 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93 ((uint32_t)0x20000000) /*!< Protects Sector 93 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT94] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94_OFS (30) /*!< PROT94 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94 ((uint32_t)0x40000000) /*!< Protects Sector 94 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT2[PROT95] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95_OFS (31) /*!< PROT95 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95 ((uint32_t)0x80000000) /*!< Protects Sector 95 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT96] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96_OFS ( 0) /*!< PROT96 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96 ((uint32_t)0x00000001) /*!< Protects Sector 96 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT97] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97_OFS ( 1) /*!< PROT97 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97 ((uint32_t)0x00000002) /*!< Protects Sector 97 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT98] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98_OFS ( 2) /*!< PROT98 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98 ((uint32_t)0x00000004) /*!< Protects Sector 98 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT99] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99_OFS ( 3) /*!< PROT99 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99 ((uint32_t)0x00000008) /*!< Protects Sector 99 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT100] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100_OFS ( 4) /*!< PROT100 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100 ((uint32_t)0x00000010) /*!< Protects Sector 100 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT101] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101_OFS ( 5) /*!< PROT101 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101 ((uint32_t)0x00000020) /*!< Protects Sector 101 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT102] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102_OFS ( 6) /*!< PROT102 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102 ((uint32_t)0x00000040) /*!< Protects Sector 102 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT103] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103_OFS ( 7) /*!< PROT103 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103 ((uint32_t)0x00000080) /*!< Protects Sector 103 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT104] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104_OFS ( 8) /*!< PROT104 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104 ((uint32_t)0x00000100) /*!< Protects Sector 104 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT105] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105_OFS ( 9) /*!< PROT105 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105 ((uint32_t)0x00000200) /*!< Protects Sector 105 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT106] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106_OFS (10) /*!< PROT106 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106 ((uint32_t)0x00000400) /*!< Protects Sector 106 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT107] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107_OFS (11) /*!< PROT107 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107 ((uint32_t)0x00000800) /*!< Protects Sector 107 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT108] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108_OFS (12) /*!< PROT108 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108 ((uint32_t)0x00001000) /*!< Protects Sector 108 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT109] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109_OFS (13) /*!< PROT109 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109 ((uint32_t)0x00002000) /*!< Protects Sector 109 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT110] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110_OFS (14) /*!< PROT110 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110 ((uint32_t)0x00004000) /*!< Protects Sector 110 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT111] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111_OFS (15) /*!< PROT111 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111 ((uint32_t)0x00008000) /*!< Protects Sector 111 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT112] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112_OFS (16) /*!< PROT112 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112 ((uint32_t)0x00010000) /*!< Protects Sector 112 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT113] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113_OFS (17) /*!< PROT113 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113 ((uint32_t)0x00020000) /*!< Protects Sector 113 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT114] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114_OFS (18) /*!< PROT114 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114 ((uint32_t)0x00040000) /*!< Protects Sector 114 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT115] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115_OFS (19) /*!< PROT115 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115 ((uint32_t)0x00080000) /*!< Protects Sector 115 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT116] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116_OFS (20) /*!< PROT116 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116 ((uint32_t)0x00100000) /*!< Protects Sector 116 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT117] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117_OFS (21) /*!< PROT117 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117 ((uint32_t)0x00200000) /*!< Protects Sector 117 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT118] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118_OFS (22) /*!< PROT118 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118 ((uint32_t)0x00400000) /*!< Protects Sector 118 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT119] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119_OFS (23) /*!< PROT119 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119 ((uint32_t)0x00800000) /*!< Protects Sector 119 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT120] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120_OFS (24) /*!< PROT120 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120 ((uint32_t)0x01000000) /*!< Protects Sector 120 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT121] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121_OFS (25) /*!< PROT121 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121 ((uint32_t)0x02000000) /*!< Protects Sector 121 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT122] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122_OFS (26) /*!< PROT122 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122 ((uint32_t)0x04000000) /*!< Protects Sector 122 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT123] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123_OFS (27) /*!< PROT123 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123 ((uint32_t)0x08000000) /*!< Protects Sector 123 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT124] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124_OFS (28) /*!< PROT124 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124 ((uint32_t)0x10000000) /*!< Protects Sector 124 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT125] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125_OFS (29) /*!< PROT125 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125 ((uint32_t)0x20000000) /*!< Protects Sector 125 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT126] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126_OFS (30) /*!< PROT126 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126 ((uint32_t)0x40000000) /*!< Protects Sector 126 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT3[PROT127] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127_OFS (31) /*!< PROT127 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127 ((uint32_t)0x80000000) /*!< Protects Sector 127 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT128] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128_OFS ( 0) /*!< PROT128 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128 ((uint32_t)0x00000001) /*!< Protects Sector 128 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT129] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129_OFS ( 1) /*!< PROT129 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129 ((uint32_t)0x00000002) /*!< Protects Sector 129 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT130] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130_OFS ( 2) /*!< PROT130 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130 ((uint32_t)0x00000004) /*!< Protects Sector 130 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT131] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131_OFS ( 3) /*!< PROT131 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131 ((uint32_t)0x00000008) /*!< Protects Sector 131 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT132] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132_OFS ( 4) /*!< PROT132 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132 ((uint32_t)0x00000010) /*!< Protects Sector 132 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT133] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133_OFS ( 5) /*!< PROT133 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133 ((uint32_t)0x00000020) /*!< Protects Sector 133 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT134] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134_OFS ( 6) /*!< PROT134 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134 ((uint32_t)0x00000040) /*!< Protects Sector 134 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT135] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135_OFS ( 7) /*!< PROT135 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135 ((uint32_t)0x00000080) /*!< Protects Sector 135 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT136] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136_OFS ( 8) /*!< PROT136 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136 ((uint32_t)0x00000100) /*!< Protects Sector 136 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT137] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137_OFS ( 9) /*!< PROT137 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137 ((uint32_t)0x00000200) /*!< Protects Sector 137 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT138] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138_OFS (10) /*!< PROT138 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138 ((uint32_t)0x00000400) /*!< Protects Sector 138 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT139] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139_OFS (11) /*!< PROT139 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139 ((uint32_t)0x00000800) /*!< Protects Sector 139 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT140] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140_OFS (12) /*!< PROT140 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140 ((uint32_t)0x00001000) /*!< Protects Sector 140 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT141] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141_OFS (13) /*!< PROT141 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141 ((uint32_t)0x00002000) /*!< Protects Sector 141 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT142] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142_OFS (14) /*!< PROT142 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142 ((uint32_t)0x00004000) /*!< Protects Sector 142 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT143] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143_OFS (15) /*!< PROT143 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143 ((uint32_t)0x00008000) /*!< Protects Sector 143 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT144] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144_OFS (16) /*!< PROT144 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144 ((uint32_t)0x00010000) /*!< Protects Sector 144 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT145] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145_OFS (17) /*!< PROT145 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145 ((uint32_t)0x00020000) /*!< Protects Sector 145 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT146] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146_OFS (18) /*!< PROT146 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146 ((uint32_t)0x00040000) /*!< Protects Sector 146 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT147] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147_OFS (19) /*!< PROT147 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147 ((uint32_t)0x00080000) /*!< Protects Sector 147 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT148] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148_OFS (20) /*!< PROT148 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148 ((uint32_t)0x00100000) /*!< Protects Sector 148 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT149] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149_OFS (21) /*!< PROT149 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149 ((uint32_t)0x00200000) /*!< Protects Sector 149 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT150] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150_OFS (22) /*!< PROT150 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150 ((uint32_t)0x00400000) /*!< Protects Sector 150 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT151] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151_OFS (23) /*!< PROT151 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151 ((uint32_t)0x00800000) /*!< Protects Sector 151 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT152] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152_OFS (24) /*!< PROT152 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152 ((uint32_t)0x01000000) /*!< Protects Sector 152 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT153] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153_OFS (25) /*!< PROT153 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153 ((uint32_t)0x02000000) /*!< Protects Sector 153 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT154] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154_OFS (26) /*!< PROT154 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154 ((uint32_t)0x04000000) /*!< Protects Sector 154 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT155] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155_OFS (27) /*!< PROT155 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155 ((uint32_t)0x08000000) /*!< Protects Sector 155 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT156] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156_OFS (28) /*!< PROT156 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156 ((uint32_t)0x10000000) /*!< Protects Sector 156 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT157] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157_OFS (29) /*!< PROT157 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157 ((uint32_t)0x20000000) /*!< Protects Sector 157 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT158] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158_OFS (30) /*!< PROT158 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158 ((uint32_t)0x40000000) /*!< Protects Sector 158 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT4[PROT159] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159_OFS (31) /*!< PROT159 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159 ((uint32_t)0x80000000) /*!< Protects Sector 159 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT160] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160_OFS ( 0) /*!< PROT160 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160 ((uint32_t)0x00000001) /*!< Protects Sector 160 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT161] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161_OFS ( 1) /*!< PROT161 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161 ((uint32_t)0x00000002) /*!< Protects Sector 161 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT162] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162_OFS ( 2) /*!< PROT162 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162 ((uint32_t)0x00000004) /*!< Protects Sector 162 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT163] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163_OFS ( 3) /*!< PROT163 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163 ((uint32_t)0x00000008) /*!< Protects Sector 163 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT164] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164_OFS ( 4) /*!< PROT164 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164 ((uint32_t)0x00000010) /*!< Protects Sector 164 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT165] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165_OFS ( 5) /*!< PROT165 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165 ((uint32_t)0x00000020) /*!< Protects Sector 165 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT166] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166_OFS ( 6) /*!< PROT166 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166 ((uint32_t)0x00000040) /*!< Protects Sector 166 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT167] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167_OFS ( 7) /*!< PROT167 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167 ((uint32_t)0x00000080) /*!< Protects Sector 167 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT168] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168_OFS ( 8) /*!< PROT168 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168 ((uint32_t)0x00000100) /*!< Protects Sector 168 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT169] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169_OFS ( 9) /*!< PROT169 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169 ((uint32_t)0x00000200) /*!< Protects Sector 169 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT170] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170_OFS (10) /*!< PROT170 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170 ((uint32_t)0x00000400) /*!< Protects Sector 170 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT171] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171_OFS (11) /*!< PROT171 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171 ((uint32_t)0x00000800) /*!< Protects Sector 171 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT172] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172_OFS (12) /*!< PROT172 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172 ((uint32_t)0x00001000) /*!< Protects Sector 172 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT173] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173_OFS (13) /*!< PROT173 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173 ((uint32_t)0x00002000) /*!< Protects Sector 173 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT174] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174_OFS (14) /*!< PROT174 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174 ((uint32_t)0x00004000) /*!< Protects Sector 174 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT175] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175_OFS (15) /*!< PROT175 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175 ((uint32_t)0x00008000) /*!< Protects Sector 175 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT176] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176_OFS (16) /*!< PROT176 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176 ((uint32_t)0x00010000) /*!< Protects Sector 176 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT177] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177_OFS (17) /*!< PROT177 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177 ((uint32_t)0x00020000) /*!< Protects Sector 177 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT178] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178_OFS (18) /*!< PROT178 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178 ((uint32_t)0x00040000) /*!< Protects Sector 178 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT179] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179_OFS (19) /*!< PROT179 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179 ((uint32_t)0x00080000) /*!< Protects Sector 179 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT180] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180_OFS (20) /*!< PROT180 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180 ((uint32_t)0x00100000) /*!< Protects Sector 180 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT181] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181_OFS (21) /*!< PROT181 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181 ((uint32_t)0x00200000) /*!< Protects Sector 181 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT182] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182_OFS (22) /*!< PROT182 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182 ((uint32_t)0x00400000) /*!< Protects Sector 182 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT183] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183_OFS (23) /*!< PROT183 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183 ((uint32_t)0x00800000) /*!< Protects Sector 183 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT184] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184_OFS (24) /*!< PROT184 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184 ((uint32_t)0x01000000) /*!< Protects Sector 184 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT185] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185_OFS (25) /*!< PROT185 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185 ((uint32_t)0x02000000) /*!< Protects Sector 185 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT186] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186_OFS (26) /*!< PROT186 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186 ((uint32_t)0x04000000) /*!< Protects Sector 186 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT187] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187_OFS (27) /*!< PROT187 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187 ((uint32_t)0x08000000) /*!< Protects Sector 187 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT188] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188_OFS (28) /*!< PROT188 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188 ((uint32_t)0x10000000) /*!< Protects Sector 188 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT189] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189_OFS (29) /*!< PROT189 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189 ((uint32_t)0x20000000) /*!< Protects Sector 189 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT190] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190_OFS (30) /*!< PROT190 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190 ((uint32_t)0x40000000) /*!< Protects Sector 190 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT5[PROT191] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191_OFS (31) /*!< PROT191 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191 ((uint32_t)0x80000000) /*!< Protects Sector 191 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT192] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192_OFS ( 0) /*!< PROT192 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192 ((uint32_t)0x00000001) /*!< Protects Sector 192 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT193] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193_OFS ( 1) /*!< PROT193 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193 ((uint32_t)0x00000002) /*!< Protects Sector 193 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT194] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194_OFS ( 2) /*!< PROT194 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194 ((uint32_t)0x00000004) /*!< Protects Sector 194 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT195] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195_OFS ( 3) /*!< PROT195 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195 ((uint32_t)0x00000008) /*!< Protects Sector 195 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT196] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196_OFS ( 4) /*!< PROT196 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196 ((uint32_t)0x00000010) /*!< Protects Sector 196 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT197] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197_OFS ( 5) /*!< PROT197 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197 ((uint32_t)0x00000020) /*!< Protects Sector 197 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT198] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198_OFS ( 6) /*!< PROT198 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198 ((uint32_t)0x00000040) /*!< Protects Sector 198 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT199] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199_OFS ( 7) /*!< PROT199 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199 ((uint32_t)0x00000080) /*!< Protects Sector 199 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT200] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200_OFS ( 8) /*!< PROT200 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200 ((uint32_t)0x00000100) /*!< Protects Sector 200 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT201] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201_OFS ( 9) /*!< PROT201 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201 ((uint32_t)0x00000200) /*!< Protects Sector 201 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT202] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202_OFS (10) /*!< PROT202 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202 ((uint32_t)0x00000400) /*!< Protects Sector 202 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT203] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203_OFS (11) /*!< PROT203 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203 ((uint32_t)0x00000800) /*!< Protects Sector 203 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT204] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204_OFS (12) /*!< PROT204 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204 ((uint32_t)0x00001000) /*!< Protects Sector 204 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT205] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205_OFS (13) /*!< PROT205 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205 ((uint32_t)0x00002000) /*!< Protects Sector 205 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT206] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206_OFS (14) /*!< PROT206 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206 ((uint32_t)0x00004000) /*!< Protects Sector 206 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT207] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207_OFS (15) /*!< PROT207 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207 ((uint32_t)0x00008000) /*!< Protects Sector 207 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT208] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208_OFS (16) /*!< PROT208 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208 ((uint32_t)0x00010000) /*!< Protects Sector 208 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT209] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209_OFS (17) /*!< PROT209 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209 ((uint32_t)0x00020000) /*!< Protects Sector 209 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT210] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210_OFS (18) /*!< PROT210 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210 ((uint32_t)0x00040000) /*!< Protects Sector 210 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT211] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211_OFS (19) /*!< PROT211 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211 ((uint32_t)0x00080000) /*!< Protects Sector 211 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT212] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212_OFS (20) /*!< PROT212 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212 ((uint32_t)0x00100000) /*!< Protects Sector 212 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT213] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213_OFS (21) /*!< PROT213 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213 ((uint32_t)0x00200000) /*!< Protects Sector 213 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT214] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214_OFS (22) /*!< PROT214 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214 ((uint32_t)0x00400000) /*!< Protects Sector 214 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT215] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215_OFS (23) /*!< PROT215 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215 ((uint32_t)0x00800000) /*!< Protects Sector 215 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT216] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216_OFS (24) /*!< PROT216 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216 ((uint32_t)0x01000000) /*!< Protects Sector 216 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT217] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217_OFS (25) /*!< PROT217 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217 ((uint32_t)0x02000000) /*!< Protects Sector 217 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT218] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218_OFS (26) /*!< PROT218 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218 ((uint32_t)0x04000000) /*!< Protects Sector 218 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT219] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219_OFS (27) /*!< PROT219 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219 ((uint32_t)0x08000000) /*!< Protects Sector 219 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT220] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220_OFS (28) /*!< PROT220 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220 ((uint32_t)0x10000000) /*!< Protects Sector 220 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT221] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221_OFS (29) /*!< PROT221 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221 ((uint32_t)0x20000000) /*!< Protects Sector 221 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT222] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222_OFS (30) /*!< PROT222 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222 ((uint32_t)0x40000000) /*!< Protects Sector 222 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT6[PROT223] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223_OFS (31) /*!< PROT223 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223 ((uint32_t)0x80000000) /*!< Protects Sector 223 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT224] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224_OFS ( 0) /*!< PROT224 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224 ((uint32_t)0x00000001) /*!< Protects Sector 224 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT225] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225_OFS ( 1) /*!< PROT225 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225 ((uint32_t)0x00000002) /*!< Protects Sector 225 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT226] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226_OFS ( 2) /*!< PROT226 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226 ((uint32_t)0x00000004) /*!< Protects Sector 226 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT227] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227_OFS ( 3) /*!< PROT227 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227 ((uint32_t)0x00000008) /*!< Protects Sector 227 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT228] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228_OFS ( 4) /*!< PROT228 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228 ((uint32_t)0x00000010) /*!< Protects Sector 228 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT229] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229_OFS ( 5) /*!< PROT229 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229 ((uint32_t)0x00000020) /*!< Protects Sector 229 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT230] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230_OFS ( 6) /*!< PROT230 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230 ((uint32_t)0x00000040) /*!< Protects Sector 230 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT231] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231_OFS ( 7) /*!< PROT231 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231 ((uint32_t)0x00000080) /*!< Protects Sector 231 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT232] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232_OFS ( 8) /*!< PROT232 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232 ((uint32_t)0x00000100) /*!< Protects Sector 232 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT233] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233_OFS ( 9) /*!< PROT233 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233 ((uint32_t)0x00000200) /*!< Protects Sector 233 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT234] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234_OFS (10) /*!< PROT234 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234 ((uint32_t)0x00000400) /*!< Protects Sector 234 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT235] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235_OFS (11) /*!< PROT235 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235 ((uint32_t)0x00000800) /*!< Protects Sector 235 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT236] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236_OFS (12) /*!< PROT236 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236 ((uint32_t)0x00001000) /*!< Protects Sector 236 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT237] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237_OFS (13) /*!< PROT237 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237 ((uint32_t)0x00002000) /*!< Protects Sector 237 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT238] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238_OFS (14) /*!< PROT238 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238 ((uint32_t)0x00004000) /*!< Protects Sector 238 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT239] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239_OFS (15) /*!< PROT239 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239 ((uint32_t)0x00008000) /*!< Protects Sector 239 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT240] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240_OFS (16) /*!< PROT240 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240 ((uint32_t)0x00010000) /*!< Protects Sector 240 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT241] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241_OFS (17) /*!< PROT241 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241 ((uint32_t)0x00020000) /*!< Protects Sector 241 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT242] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242_OFS (18) /*!< PROT242 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242 ((uint32_t)0x00040000) /*!< Protects Sector 242 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT243] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243_OFS (19) /*!< PROT243 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243 ((uint32_t)0x00080000) /*!< Protects Sector 243 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT244] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244_OFS (20) /*!< PROT244 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244 ((uint32_t)0x00100000) /*!< Protects Sector 244 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT245] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245_OFS (21) /*!< PROT245 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245 ((uint32_t)0x00200000) /*!< Protects Sector 245 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT246] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246_OFS (22) /*!< PROT246 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246 ((uint32_t)0x00400000) /*!< Protects Sector 246 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT247] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247_OFS (23) /*!< PROT247 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247 ((uint32_t)0x00800000) /*!< Protects Sector 247 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT248] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248_OFS (24) /*!< PROT248 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248 ((uint32_t)0x01000000) /*!< Protects Sector 248 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT249] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249_OFS (25) /*!< PROT249 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249 ((uint32_t)0x02000000) /*!< Protects Sector 249 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT250] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250_OFS (26) /*!< PROT250 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250 ((uint32_t)0x04000000) /*!< Protects Sector 250 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT251] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251_OFS (27) /*!< PROT251 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251 ((uint32_t)0x08000000) /*!< Protects Sector 251 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT252] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252_OFS (28) /*!< PROT252 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252 ((uint32_t)0x10000000) /*!< Protects Sector 252 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT253] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253_OFS (29) /*!< PROT253 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253 ((uint32_t)0x20000000) /*!< Protects Sector 253 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT254] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254_OFS (30) /*!< PROT254 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254 ((uint32_t)0x40000000) /*!< Protects Sector 254 from program or erase */ -/* FLCTL_A_BANK0_MAIN_WEPROT7[PROT255] Bits */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255_OFS (31) /*!< PROT255 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255 ((uint32_t)0x80000000) /*!< Protects Sector 255 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT0] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT1] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT2] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT3] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT4] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT5] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT6] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT7] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT8] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT9] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT10] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT11] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT12] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT13] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT14] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT15] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT16] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT17] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT18] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT19] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT20] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT21] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT22] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT23] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT24] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT25] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT26] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT27] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT28] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT29] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT30] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT0[PROT31] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT32] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32_OFS ( 0) /*!< PROT32 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32 ((uint32_t)0x00000001) /*!< Protects Sector 32 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT33] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33_OFS ( 1) /*!< PROT33 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33 ((uint32_t)0x00000002) /*!< Protects Sector 33 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT34] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34_OFS ( 2) /*!< PROT34 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34 ((uint32_t)0x00000004) /*!< Protects Sector 34 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT35] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35_OFS ( 3) /*!< PROT35 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35 ((uint32_t)0x00000008) /*!< Protects Sector 35 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT36] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36_OFS ( 4) /*!< PROT36 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36 ((uint32_t)0x00000010) /*!< Protects Sector 36 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT37] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37_OFS ( 5) /*!< PROT37 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37 ((uint32_t)0x00000020) /*!< Protects Sector 37 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT38] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38_OFS ( 6) /*!< PROT38 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38 ((uint32_t)0x00000040) /*!< Protects Sector 38 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT39] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39_OFS ( 7) /*!< PROT39 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39 ((uint32_t)0x00000080) /*!< Protects Sector 39 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT40] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40_OFS ( 8) /*!< PROT40 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40 ((uint32_t)0x00000100) /*!< Protects Sector 40 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT41] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41_OFS ( 9) /*!< PROT41 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41 ((uint32_t)0x00000200) /*!< Protects Sector 41 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT42] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42_OFS (10) /*!< PROT42 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42 ((uint32_t)0x00000400) /*!< Protects Sector 42 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT43] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43_OFS (11) /*!< PROT43 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43 ((uint32_t)0x00000800) /*!< Protects Sector 43 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT44] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44_OFS (12) /*!< PROT44 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44 ((uint32_t)0x00001000) /*!< Protects Sector 44 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT45] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45_OFS (13) /*!< PROT45 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45 ((uint32_t)0x00002000) /*!< Protects Sector 45 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT46] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46_OFS (14) /*!< PROT46 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46 ((uint32_t)0x00004000) /*!< Protects Sector 46 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT47] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47_OFS (15) /*!< PROT47 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47 ((uint32_t)0x00008000) /*!< Protects Sector 47 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT48] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48_OFS (16) /*!< PROT48 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48 ((uint32_t)0x00010000) /*!< Protects Sector 48 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT49] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49_OFS (17) /*!< PROT49 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49 ((uint32_t)0x00020000) /*!< Protects Sector 49 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT50] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50_OFS (18) /*!< PROT50 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50 ((uint32_t)0x00040000) /*!< Protects Sector 50 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT51] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51_OFS (19) /*!< PROT51 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51 ((uint32_t)0x00080000) /*!< Protects Sector 51 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT52] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52_OFS (20) /*!< PROT52 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52 ((uint32_t)0x00100000) /*!< Protects Sector 52 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT53] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53_OFS (21) /*!< PROT53 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53 ((uint32_t)0x00200000) /*!< Protects Sector 53 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT54] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54_OFS (22) /*!< PROT54 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54 ((uint32_t)0x00400000) /*!< Protects Sector 54 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT55] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55_OFS (23) /*!< PROT55 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55 ((uint32_t)0x00800000) /*!< Protects Sector 55 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT56] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56_OFS (24) /*!< PROT56 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56 ((uint32_t)0x01000000) /*!< Protects Sector 56 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT57] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57_OFS (25) /*!< PROT57 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57 ((uint32_t)0x02000000) /*!< Protects Sector 57 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT58] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58_OFS (26) /*!< PROT58 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58 ((uint32_t)0x04000000) /*!< Protects Sector 58 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT59] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59_OFS (27) /*!< PROT59 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59 ((uint32_t)0x08000000) /*!< Protects Sector 59 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT60] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60_OFS (28) /*!< PROT60 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60 ((uint32_t)0x10000000) /*!< Protects Sector 60 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT61] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61_OFS (29) /*!< PROT61 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61 ((uint32_t)0x20000000) /*!< Protects Sector 61 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT62] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62_OFS (30) /*!< PROT62 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62 ((uint32_t)0x40000000) /*!< Protects Sector 62 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT1[PROT63] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63_OFS (31) /*!< PROT63 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63 ((uint32_t)0x80000000) /*!< Protects Sector 63 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT64] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64_OFS ( 0) /*!< PROT64 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64 ((uint32_t)0x00000001) /*!< Protects Sector 64 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT65] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65_OFS ( 1) /*!< PROT65 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65 ((uint32_t)0x00000002) /*!< Protects Sector 65 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT66] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66_OFS ( 2) /*!< PROT66 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66 ((uint32_t)0x00000004) /*!< Protects Sector 66 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT67] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67_OFS ( 3) /*!< PROT67 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67 ((uint32_t)0x00000008) /*!< Protects Sector 67 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT68] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68_OFS ( 4) /*!< PROT68 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68 ((uint32_t)0x00000010) /*!< Protects Sector 68 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT69] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69_OFS ( 5) /*!< PROT69 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69 ((uint32_t)0x00000020) /*!< Protects Sector 69 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT70] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70_OFS ( 6) /*!< PROT70 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70 ((uint32_t)0x00000040) /*!< Protects Sector 70 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT71] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71_OFS ( 7) /*!< PROT71 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71 ((uint32_t)0x00000080) /*!< Protects Sector 71 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT72] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72_OFS ( 8) /*!< PROT72 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72 ((uint32_t)0x00000100) /*!< Protects Sector 72 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT73] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73_OFS ( 9) /*!< PROT73 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73 ((uint32_t)0x00000200) /*!< Protects Sector 73 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT74] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74_OFS (10) /*!< PROT74 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74 ((uint32_t)0x00000400) /*!< Protects Sector 74 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT75] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75_OFS (11) /*!< PROT75 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75 ((uint32_t)0x00000800) /*!< Protects Sector 75 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT76] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76_OFS (12) /*!< PROT76 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76 ((uint32_t)0x00001000) /*!< Protects Sector 76 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT77] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77_OFS (13) /*!< PROT77 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77 ((uint32_t)0x00002000) /*!< Protects Sector 77 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT78] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78_OFS (14) /*!< PROT78 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78 ((uint32_t)0x00004000) /*!< Protects Sector 78 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT79] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79_OFS (15) /*!< PROT79 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79 ((uint32_t)0x00008000) /*!< Protects Sector 79 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT80] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80_OFS (16) /*!< PROT80 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80 ((uint32_t)0x00010000) /*!< Protects Sector 80 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT81] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81_OFS (17) /*!< PROT81 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81 ((uint32_t)0x00020000) /*!< Protects Sector 81 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT82] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82_OFS (18) /*!< PROT82 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82 ((uint32_t)0x00040000) /*!< Protects Sector 82 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT83] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83_OFS (19) /*!< PROT83 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83 ((uint32_t)0x00080000) /*!< Protects Sector 83 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT84] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84_OFS (20) /*!< PROT84 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84 ((uint32_t)0x00100000) /*!< Protects Sector 84 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT85] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85_OFS (21) /*!< PROT85 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85 ((uint32_t)0x00200000) /*!< Protects Sector 85 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT86] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86_OFS (22) /*!< PROT86 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86 ((uint32_t)0x00400000) /*!< Protects Sector 86 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT87] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87_OFS (23) /*!< PROT87 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87 ((uint32_t)0x00800000) /*!< Protects Sector 87 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT88] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88_OFS (24) /*!< PROT88 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88 ((uint32_t)0x01000000) /*!< Protects Sector 88 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT89] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89_OFS (25) /*!< PROT89 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89 ((uint32_t)0x02000000) /*!< Protects Sector 89 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT90] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90_OFS (26) /*!< PROT90 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90 ((uint32_t)0x04000000) /*!< Protects Sector 90 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT91] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91_OFS (27) /*!< PROT91 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91 ((uint32_t)0x08000000) /*!< Protects Sector 91 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT92] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92_OFS (28) /*!< PROT92 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92 ((uint32_t)0x10000000) /*!< Protects Sector 92 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT93] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93_OFS (29) /*!< PROT93 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93 ((uint32_t)0x20000000) /*!< Protects Sector 93 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT94] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94_OFS (30) /*!< PROT94 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94 ((uint32_t)0x40000000) /*!< Protects Sector 94 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT2[PROT95] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95_OFS (31) /*!< PROT95 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95 ((uint32_t)0x80000000) /*!< Protects Sector 95 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT96] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96_OFS ( 0) /*!< PROT96 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96 ((uint32_t)0x00000001) /*!< Protects Sector 96 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT97] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97_OFS ( 1) /*!< PROT97 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97 ((uint32_t)0x00000002) /*!< Protects Sector 97 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT98] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98_OFS ( 2) /*!< PROT98 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98 ((uint32_t)0x00000004) /*!< Protects Sector 98 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT99] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99_OFS ( 3) /*!< PROT99 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99 ((uint32_t)0x00000008) /*!< Protects Sector 99 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT100] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100_OFS ( 4) /*!< PROT100 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100 ((uint32_t)0x00000010) /*!< Protects Sector 100 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT101] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101_OFS ( 5) /*!< PROT101 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101 ((uint32_t)0x00000020) /*!< Protects Sector 101 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT102] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102_OFS ( 6) /*!< PROT102 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102 ((uint32_t)0x00000040) /*!< Protects Sector 102 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT103] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103_OFS ( 7) /*!< PROT103 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103 ((uint32_t)0x00000080) /*!< Protects Sector 103 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT104] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104_OFS ( 8) /*!< PROT104 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104 ((uint32_t)0x00000100) /*!< Protects Sector 104 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT105] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105_OFS ( 9) /*!< PROT105 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105 ((uint32_t)0x00000200) /*!< Protects Sector 105 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT106] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106_OFS (10) /*!< PROT106 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106 ((uint32_t)0x00000400) /*!< Protects Sector 106 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT107] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107_OFS (11) /*!< PROT107 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107 ((uint32_t)0x00000800) /*!< Protects Sector 107 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT108] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108_OFS (12) /*!< PROT108 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108 ((uint32_t)0x00001000) /*!< Protects Sector 108 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT109] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109_OFS (13) /*!< PROT109 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109 ((uint32_t)0x00002000) /*!< Protects Sector 109 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT110] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110_OFS (14) /*!< PROT110 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110 ((uint32_t)0x00004000) /*!< Protects Sector 110 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT111] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111_OFS (15) /*!< PROT111 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111 ((uint32_t)0x00008000) /*!< Protects Sector 111 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT112] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112_OFS (16) /*!< PROT112 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112 ((uint32_t)0x00010000) /*!< Protects Sector 112 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT113] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113_OFS (17) /*!< PROT113 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113 ((uint32_t)0x00020000) /*!< Protects Sector 113 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT114] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114_OFS (18) /*!< PROT114 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114 ((uint32_t)0x00040000) /*!< Protects Sector 114 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT115] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115_OFS (19) /*!< PROT115 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115 ((uint32_t)0x00080000) /*!< Protects Sector 115 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT116] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116_OFS (20) /*!< PROT116 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116 ((uint32_t)0x00100000) /*!< Protects Sector 116 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT117] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117_OFS (21) /*!< PROT117 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117 ((uint32_t)0x00200000) /*!< Protects Sector 117 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT118] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118_OFS (22) /*!< PROT118 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118 ((uint32_t)0x00400000) /*!< Protects Sector 118 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT119] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119_OFS (23) /*!< PROT119 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119 ((uint32_t)0x00800000) /*!< Protects Sector 119 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT120] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120_OFS (24) /*!< PROT120 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120 ((uint32_t)0x01000000) /*!< Protects Sector 120 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT121] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121_OFS (25) /*!< PROT121 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121 ((uint32_t)0x02000000) /*!< Protects Sector 121 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT122] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122_OFS (26) /*!< PROT122 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122 ((uint32_t)0x04000000) /*!< Protects Sector 122 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT123] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123_OFS (27) /*!< PROT123 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123 ((uint32_t)0x08000000) /*!< Protects Sector 123 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT124] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124_OFS (28) /*!< PROT124 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124 ((uint32_t)0x10000000) /*!< Protects Sector 124 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT125] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125_OFS (29) /*!< PROT125 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125 ((uint32_t)0x20000000) /*!< Protects Sector 125 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT126] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126_OFS (30) /*!< PROT126 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126 ((uint32_t)0x40000000) /*!< Protects Sector 126 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT3[PROT127] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127_OFS (31) /*!< PROT127 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127 ((uint32_t)0x80000000) /*!< Protects Sector 127 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT128] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128_OFS ( 0) /*!< PROT128 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128 ((uint32_t)0x00000001) /*!< Protects Sector 128 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT129] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129_OFS ( 1) /*!< PROT129 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129 ((uint32_t)0x00000002) /*!< Protects Sector 129 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT130] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130_OFS ( 2) /*!< PROT130 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130 ((uint32_t)0x00000004) /*!< Protects Sector 130 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT131] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131_OFS ( 3) /*!< PROT131 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131 ((uint32_t)0x00000008) /*!< Protects Sector 131 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT132] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132_OFS ( 4) /*!< PROT132 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132 ((uint32_t)0x00000010) /*!< Protects Sector 132 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT133] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133_OFS ( 5) /*!< PROT133 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133 ((uint32_t)0x00000020) /*!< Protects Sector 133 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT134] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134_OFS ( 6) /*!< PROT134 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134 ((uint32_t)0x00000040) /*!< Protects Sector 134 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT135] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135_OFS ( 7) /*!< PROT135 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135 ((uint32_t)0x00000080) /*!< Protects Sector 135 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT136] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136_OFS ( 8) /*!< PROT136 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136 ((uint32_t)0x00000100) /*!< Protects Sector 136 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT137] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137_OFS ( 9) /*!< PROT137 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137 ((uint32_t)0x00000200) /*!< Protects Sector 137 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT138] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138_OFS (10) /*!< PROT138 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138 ((uint32_t)0x00000400) /*!< Protects Sector 138 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT139] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139_OFS (11) /*!< PROT139 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139 ((uint32_t)0x00000800) /*!< Protects Sector 139 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT140] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140_OFS (12) /*!< PROT140 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140 ((uint32_t)0x00001000) /*!< Protects Sector 140 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT141] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141_OFS (13) /*!< PROT141 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141 ((uint32_t)0x00002000) /*!< Protects Sector 141 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT142] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142_OFS (14) /*!< PROT142 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142 ((uint32_t)0x00004000) /*!< Protects Sector 142 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT143] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143_OFS (15) /*!< PROT143 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143 ((uint32_t)0x00008000) /*!< Protects Sector 143 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT144] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144_OFS (16) /*!< PROT144 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144 ((uint32_t)0x00010000) /*!< Protects Sector 144 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT145] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145_OFS (17) /*!< PROT145 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145 ((uint32_t)0x00020000) /*!< Protects Sector 145 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT146] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146_OFS (18) /*!< PROT146 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146 ((uint32_t)0x00040000) /*!< Protects Sector 146 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT147] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147_OFS (19) /*!< PROT147 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147 ((uint32_t)0x00080000) /*!< Protects Sector 147 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT148] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148_OFS (20) /*!< PROT148 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148 ((uint32_t)0x00100000) /*!< Protects Sector 148 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT149] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149_OFS (21) /*!< PROT149 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149 ((uint32_t)0x00200000) /*!< Protects Sector 149 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT150] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150_OFS (22) /*!< PROT150 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150 ((uint32_t)0x00400000) /*!< Protects Sector 150 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT151] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151_OFS (23) /*!< PROT151 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151 ((uint32_t)0x00800000) /*!< Protects Sector 151 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT152] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152_OFS (24) /*!< PROT152 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152 ((uint32_t)0x01000000) /*!< Protects Sector 152 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT153] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153_OFS (25) /*!< PROT153 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153 ((uint32_t)0x02000000) /*!< Protects Sector 153 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT154] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154_OFS (26) /*!< PROT154 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154 ((uint32_t)0x04000000) /*!< Protects Sector 154 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT155] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155_OFS (27) /*!< PROT155 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155 ((uint32_t)0x08000000) /*!< Protects Sector 155 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT156] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156_OFS (28) /*!< PROT156 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156 ((uint32_t)0x10000000) /*!< Protects Sector 156 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT157] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157_OFS (29) /*!< PROT157 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157 ((uint32_t)0x20000000) /*!< Protects Sector 157 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT158] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158_OFS (30) /*!< PROT158 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158 ((uint32_t)0x40000000) /*!< Protects Sector 158 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT4[PROT159] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159_OFS (31) /*!< PROT159 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159 ((uint32_t)0x80000000) /*!< Protects Sector 159 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT160] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160_OFS ( 0) /*!< PROT160 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160 ((uint32_t)0x00000001) /*!< Protects Sector 160 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT161] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161_OFS ( 1) /*!< PROT161 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161 ((uint32_t)0x00000002) /*!< Protects Sector 161 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT162] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162_OFS ( 2) /*!< PROT162 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162 ((uint32_t)0x00000004) /*!< Protects Sector 162 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT163] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163_OFS ( 3) /*!< PROT163 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163 ((uint32_t)0x00000008) /*!< Protects Sector 163 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT164] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164_OFS ( 4) /*!< PROT164 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164 ((uint32_t)0x00000010) /*!< Protects Sector 164 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT165] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165_OFS ( 5) /*!< PROT165 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165 ((uint32_t)0x00000020) /*!< Protects Sector 165 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT166] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166_OFS ( 6) /*!< PROT166 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166 ((uint32_t)0x00000040) /*!< Protects Sector 166 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT167] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167_OFS ( 7) /*!< PROT167 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167 ((uint32_t)0x00000080) /*!< Protects Sector 167 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT168] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168_OFS ( 8) /*!< PROT168 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168 ((uint32_t)0x00000100) /*!< Protects Sector 168 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT169] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169_OFS ( 9) /*!< PROT169 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169 ((uint32_t)0x00000200) /*!< Protects Sector 169 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT170] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170_OFS (10) /*!< PROT170 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170 ((uint32_t)0x00000400) /*!< Protects Sector 170 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT171] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171_OFS (11) /*!< PROT171 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171 ((uint32_t)0x00000800) /*!< Protects Sector 171 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT172] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172_OFS (12) /*!< PROT172 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172 ((uint32_t)0x00001000) /*!< Protects Sector 172 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT173] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173_OFS (13) /*!< PROT173 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173 ((uint32_t)0x00002000) /*!< Protects Sector 173 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT174] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174_OFS (14) /*!< PROT174 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174 ((uint32_t)0x00004000) /*!< Protects Sector 174 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT175] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175_OFS (15) /*!< PROT175 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175 ((uint32_t)0x00008000) /*!< Protects Sector 175 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT176] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176_OFS (16) /*!< PROT176 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176 ((uint32_t)0x00010000) /*!< Protects Sector 176 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT177] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177_OFS (17) /*!< PROT177 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177 ((uint32_t)0x00020000) /*!< Protects Sector 177 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT178] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178_OFS (18) /*!< PROT178 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178 ((uint32_t)0x00040000) /*!< Protects Sector 178 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT179] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179_OFS (19) /*!< PROT179 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179 ((uint32_t)0x00080000) /*!< Protects Sector 179 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT180] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180_OFS (20) /*!< PROT180 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180 ((uint32_t)0x00100000) /*!< Protects Sector 180 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT181] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181_OFS (21) /*!< PROT181 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181 ((uint32_t)0x00200000) /*!< Protects Sector 181 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT182] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182_OFS (22) /*!< PROT182 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182 ((uint32_t)0x00400000) /*!< Protects Sector 182 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT183] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183_OFS (23) /*!< PROT183 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183 ((uint32_t)0x00800000) /*!< Protects Sector 183 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT184] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184_OFS (24) /*!< PROT184 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184 ((uint32_t)0x01000000) /*!< Protects Sector 184 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT185] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185_OFS (25) /*!< PROT185 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185 ((uint32_t)0x02000000) /*!< Protects Sector 185 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT186] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186_OFS (26) /*!< PROT186 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186 ((uint32_t)0x04000000) /*!< Protects Sector 186 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT187] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187_OFS (27) /*!< PROT187 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187 ((uint32_t)0x08000000) /*!< Protects Sector 187 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT188] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188_OFS (28) /*!< PROT188 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188 ((uint32_t)0x10000000) /*!< Protects Sector 188 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT189] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189_OFS (29) /*!< PROT189 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189 ((uint32_t)0x20000000) /*!< Protects Sector 189 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT190] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190_OFS (30) /*!< PROT190 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190 ((uint32_t)0x40000000) /*!< Protects Sector 190 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT5[PROT191] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191_OFS (31) /*!< PROT191 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191 ((uint32_t)0x80000000) /*!< Protects Sector 191 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT192] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192_OFS ( 0) /*!< PROT192 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192 ((uint32_t)0x00000001) /*!< Protects Sector 192 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT193] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193_OFS ( 1) /*!< PROT193 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193 ((uint32_t)0x00000002) /*!< Protects Sector 193 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT194] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194_OFS ( 2) /*!< PROT194 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194 ((uint32_t)0x00000004) /*!< Protects Sector 194 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT195] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195_OFS ( 3) /*!< PROT195 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195 ((uint32_t)0x00000008) /*!< Protects Sector 195 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT196] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196_OFS ( 4) /*!< PROT196 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196 ((uint32_t)0x00000010) /*!< Protects Sector 196 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT197] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197_OFS ( 5) /*!< PROT197 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197 ((uint32_t)0x00000020) /*!< Protects Sector 197 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT198] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198_OFS ( 6) /*!< PROT198 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198 ((uint32_t)0x00000040) /*!< Protects Sector 198 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT199] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199_OFS ( 7) /*!< PROT199 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199 ((uint32_t)0x00000080) /*!< Protects Sector 199 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT200] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200_OFS ( 8) /*!< PROT200 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200 ((uint32_t)0x00000100) /*!< Protects Sector 200 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT201] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201_OFS ( 9) /*!< PROT201 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201 ((uint32_t)0x00000200) /*!< Protects Sector 201 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT202] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202_OFS (10) /*!< PROT202 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202 ((uint32_t)0x00000400) /*!< Protects Sector 202 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT203] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203_OFS (11) /*!< PROT203 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203 ((uint32_t)0x00000800) /*!< Protects Sector 203 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT204] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204_OFS (12) /*!< PROT204 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204 ((uint32_t)0x00001000) /*!< Protects Sector 204 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT205] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205_OFS (13) /*!< PROT205 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205 ((uint32_t)0x00002000) /*!< Protects Sector 205 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT206] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206_OFS (14) /*!< PROT206 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206 ((uint32_t)0x00004000) /*!< Protects Sector 206 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT207] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207_OFS (15) /*!< PROT207 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207 ((uint32_t)0x00008000) /*!< Protects Sector 207 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT208] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208_OFS (16) /*!< PROT208 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208 ((uint32_t)0x00010000) /*!< Protects Sector 208 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT209] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209_OFS (17) /*!< PROT209 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209 ((uint32_t)0x00020000) /*!< Protects Sector 209 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT210] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210_OFS (18) /*!< PROT210 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210 ((uint32_t)0x00040000) /*!< Protects Sector 210 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT211] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211_OFS (19) /*!< PROT211 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211 ((uint32_t)0x00080000) /*!< Protects Sector 211 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT212] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212_OFS (20) /*!< PROT212 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212 ((uint32_t)0x00100000) /*!< Protects Sector 212 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT213] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213_OFS (21) /*!< PROT213 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213 ((uint32_t)0x00200000) /*!< Protects Sector 213 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT214] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214_OFS (22) /*!< PROT214 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214 ((uint32_t)0x00400000) /*!< Protects Sector 214 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT215] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215_OFS (23) /*!< PROT215 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215 ((uint32_t)0x00800000) /*!< Protects Sector 215 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT216] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216_OFS (24) /*!< PROT216 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216 ((uint32_t)0x01000000) /*!< Protects Sector 216 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT217] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217_OFS (25) /*!< PROT217 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217 ((uint32_t)0x02000000) /*!< Protects Sector 217 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT218] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218_OFS (26) /*!< PROT218 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218 ((uint32_t)0x04000000) /*!< Protects Sector 218 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT219] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219_OFS (27) /*!< PROT219 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219 ((uint32_t)0x08000000) /*!< Protects Sector 219 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT220] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220_OFS (28) /*!< PROT220 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220 ((uint32_t)0x10000000) /*!< Protects Sector 220 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT221] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221_OFS (29) /*!< PROT221 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221 ((uint32_t)0x20000000) /*!< Protects Sector 221 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT222] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222_OFS (30) /*!< PROT222 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222 ((uint32_t)0x40000000) /*!< Protects Sector 222 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT6[PROT223] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223_OFS (31) /*!< PROT223 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223 ((uint32_t)0x80000000) /*!< Protects Sector 223 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT224] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224_OFS ( 0) /*!< PROT224 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224 ((uint32_t)0x00000001) /*!< Protects Sector 224 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT225] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225_OFS ( 1) /*!< PROT225 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225 ((uint32_t)0x00000002) /*!< Protects Sector 225 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT226] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226_OFS ( 2) /*!< PROT226 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226 ((uint32_t)0x00000004) /*!< Protects Sector 226 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT227] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227_OFS ( 3) /*!< PROT227 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227 ((uint32_t)0x00000008) /*!< Protects Sector 227 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT228] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228_OFS ( 4) /*!< PROT228 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228 ((uint32_t)0x00000010) /*!< Protects Sector 228 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT229] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229_OFS ( 5) /*!< PROT229 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229 ((uint32_t)0x00000020) /*!< Protects Sector 229 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT230] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230_OFS ( 6) /*!< PROT230 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230 ((uint32_t)0x00000040) /*!< Protects Sector 230 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT231] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231_OFS ( 7) /*!< PROT231 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231 ((uint32_t)0x00000080) /*!< Protects Sector 231 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT232] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232_OFS ( 8) /*!< PROT232 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232 ((uint32_t)0x00000100) /*!< Protects Sector 232 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT233] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233_OFS ( 9) /*!< PROT233 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233 ((uint32_t)0x00000200) /*!< Protects Sector 233 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT234] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234_OFS (10) /*!< PROT234 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234 ((uint32_t)0x00000400) /*!< Protects Sector 234 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT235] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235_OFS (11) /*!< PROT235 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235 ((uint32_t)0x00000800) /*!< Protects Sector 235 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT236] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236_OFS (12) /*!< PROT236 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236 ((uint32_t)0x00001000) /*!< Protects Sector 236 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT237] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237_OFS (13) /*!< PROT237 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237 ((uint32_t)0x00002000) /*!< Protects Sector 237 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT238] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238_OFS (14) /*!< PROT238 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238 ((uint32_t)0x00004000) /*!< Protects Sector 238 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT239] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239_OFS (15) /*!< PROT239 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239 ((uint32_t)0x00008000) /*!< Protects Sector 239 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT240] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240_OFS (16) /*!< PROT240 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240 ((uint32_t)0x00010000) /*!< Protects Sector 240 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT241] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241_OFS (17) /*!< PROT241 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241 ((uint32_t)0x00020000) /*!< Protects Sector 241 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT242] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242_OFS (18) /*!< PROT242 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242 ((uint32_t)0x00040000) /*!< Protects Sector 242 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT243] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243_OFS (19) /*!< PROT243 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243 ((uint32_t)0x00080000) /*!< Protects Sector 243 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT244] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244_OFS (20) /*!< PROT244 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244 ((uint32_t)0x00100000) /*!< Protects Sector 244 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT245] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245_OFS (21) /*!< PROT245 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245 ((uint32_t)0x00200000) /*!< Protects Sector 245 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT246] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246_OFS (22) /*!< PROT246 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246 ((uint32_t)0x00400000) /*!< Protects Sector 246 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT247] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247_OFS (23) /*!< PROT247 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247 ((uint32_t)0x00800000) /*!< Protects Sector 247 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT248] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248_OFS (24) /*!< PROT248 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248 ((uint32_t)0x01000000) /*!< Protects Sector 248 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT249] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249_OFS (25) /*!< PROT249 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249 ((uint32_t)0x02000000) /*!< Protects Sector 249 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT250] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250_OFS (26) /*!< PROT250 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250 ((uint32_t)0x04000000) /*!< Protects Sector 250 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT251] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251_OFS (27) /*!< PROT251 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251 ((uint32_t)0x08000000) /*!< Protects Sector 251 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT252] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252_OFS (28) /*!< PROT252 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252 ((uint32_t)0x10000000) /*!< Protects Sector 252 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT253] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253_OFS (29) /*!< PROT253 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253 ((uint32_t)0x20000000) /*!< Protects Sector 253 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT254] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254_OFS (30) /*!< PROT254 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254 ((uint32_t)0x40000000) /*!< Protects Sector 254 from program or erase */ -/* FLCTL_A_BANK1_MAIN_WEPROT7[PROT255] Bits */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255_OFS (31) /*!< PROT255 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255 ((uint32_t)0x80000000) /*!< Protects Sector 255 from program or erase */ - -/****************************************************************************** -* FL_BOOTOVER_MAILBOX Bits -******************************************************************************/ - -/****************************************************************************** -* FPB Bits -******************************************************************************/ - - -/****************************************************************************** -* FPU Bits -******************************************************************************/ - - -/****************************************************************************** -* ITM Bits -******************************************************************************/ - - -/****************************************************************************** -* LCD_F Bits -******************************************************************************/ -/* LCD_F_CTL[ON] Bits */ -#define LCD_F_CTL_ON_OFS ( 0) /*!< LCDON Bit Offset */ -#define LCD_F_CTL_ON ((uint32_t)0x00000001) /*!< LCD on */ -/* LCD_F_CTL[LP] Bits */ -#define LCD_F_CTL_LP_OFS ( 1) /*!< LCDLP Bit Offset */ -#define LCD_F_CTL_LP ((uint32_t)0x00000002) /*!< LCD Low-power Waveform */ -/* LCD_F_CTL[SON] Bits */ -#define LCD_F_CTL_SON_OFS ( 2) /*!< LCDSON Bit Offset */ -#define LCD_F_CTL_SON ((uint32_t)0x00000004) /*!< LCD segments on */ -/* LCD_F_CTL[MX] Bits */ -#define LCD_F_CTL_MX_OFS ( 3) /*!< LCDMXx Bit Offset */ -#define LCD_F_CTL_MX_MASK ((uint32_t)0x00000038) /*!< LCDMXx Bit Mask */ -#define LCD_F_CTL_MX0 ((uint32_t)0x00000008) /*!< MX Bit 0 */ -#define LCD_F_CTL_MX1 ((uint32_t)0x00000010) /*!< MX Bit 1 */ -#define LCD_F_CTL_MX2 ((uint32_t)0x00000020) /*!< MX Bit 2 */ -#define LCD_F_CTL_MX_0 ((uint32_t)0x00000000) /*!< Static */ -#define LCD_F_CTL_MX_1 ((uint32_t)0x00000008) /*!< 2-mux */ -#define LCD_F_CTL_MX_2 ((uint32_t)0x00000010) /*!< 3-mux */ -#define LCD_F_CTL_MX_3 ((uint32_t)0x00000018) /*!< 4-mux */ -#define LCD_F_CTL_MX_4 ((uint32_t)0x00000020) /*!< 5-mux */ -#define LCD_F_CTL_MX_5 ((uint32_t)0x00000028) /*!< 6-mux */ -#define LCD_F_CTL_MX_6 ((uint32_t)0x00000030) /*!< 7-mux */ -#define LCD_F_CTL_MX_7 ((uint32_t)0x00000038) /*!< 8-mux */ -/* LCD_F_CTL[PRE] Bits */ -#define LCD_F_CTL_PRE_OFS ( 8) /*!< LCDPREx Bit Offset */ -#define LCD_F_CTL_PRE_MASK ((uint32_t)0x00000700) /*!< LCDPREx Bit Mask */ -#define LCD_F_CTL_PRE0 ((uint32_t)0x00000100) /*!< PRE Bit 0 */ -#define LCD_F_CTL_PRE1 ((uint32_t)0x00000200) /*!< PRE Bit 1 */ -#define LCD_F_CTL_PRE2 ((uint32_t)0x00000400) /*!< PRE Bit 2 */ -#define LCD_F_CTL_PRE_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_CTL_PRE_1 ((uint32_t)0x00000100) /*!< Divide by 2 */ -#define LCD_F_CTL_PRE_2 ((uint32_t)0x00000200) /*!< Divide by 4 */ -#define LCD_F_CTL_PRE_3 ((uint32_t)0x00000300) /*!< Divide by 8 */ -#define LCD_F_CTL_PRE_4 ((uint32_t)0x00000400) /*!< Divide by 16 */ -#define LCD_F_CTL_PRE_5 ((uint32_t)0x00000500) /*!< Divide by 32 */ -#define LCD_F_CTL_PRE_6 ((uint32_t)0x00000600) /*!< Reserved (defaults to divide by 32) */ -#define LCD_F_CTL_PRE_7 ((uint32_t)0x00000700) /*!< Reserved (defaults to divide by 32) */ -/* LCD_F_CTL[DIV] Bits */ -#define LCD_F_CTL_DIV_OFS (11) /*!< LCDDIVx Bit Offset */ -#define LCD_F_CTL_DIV_MASK ((uint32_t)0x0000F800) /*!< LCDDIVx Bit Mask */ -#define LCD_F_CTL_DIV0 ((uint32_t)0x00000800) /*!< DIV Bit 0 */ -#define LCD_F_CTL_DIV1 ((uint32_t)0x00001000) /*!< DIV Bit 1 */ -#define LCD_F_CTL_DIV2 ((uint32_t)0x00002000) /*!< DIV Bit 2 */ -#define LCD_F_CTL_DIV3 ((uint32_t)0x00004000) /*!< DIV Bit 3 */ -#define LCD_F_CTL_DIV4 ((uint32_t)0x00008000) /*!< DIV Bit 4 */ -#define LCD_F_CTL_DIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_CTL_DIV_1 ((uint32_t)0x00000800) /*!< Divide by 2 */ -#define LCD_F_CTL_DIV_2 ((uint32_t)0x00001000) /*!< Divide by 3 */ -#define LCD_F_CTL_DIV_3 ((uint32_t)0x00001800) /*!< Divide by 4 */ -#define LCD_F_CTL_DIV_4 ((uint32_t)0x00002000) /*!< Divide by 5 */ -#define LCD_F_CTL_DIV_5 ((uint32_t)0x00002800) /*!< Divide by 6 */ -#define LCD_F_CTL_DIV_6 ((uint32_t)0x00003000) /*!< Divide by 7 */ -#define LCD_F_CTL_DIV_7 ((uint32_t)0x00003800) /*!< Divide by 8 */ -#define LCD_F_CTL_DIV_8 ((uint32_t)0x00004000) /*!< Divide by 9 */ -#define LCD_F_CTL_DIV_9 ((uint32_t)0x00004800) /*!< Divide by 10 */ -#define LCD_F_CTL_DIV_10 ((uint32_t)0x00005000) /*!< Divide by 11 */ -#define LCD_F_CTL_DIV_11 ((uint32_t)0x00005800) /*!< Divide by 12 */ -#define LCD_F_CTL_DIV_12 ((uint32_t)0x00006000) /*!< Divide by 13 */ -#define LCD_F_CTL_DIV_13 ((uint32_t)0x00006800) /*!< Divide by 14 */ -#define LCD_F_CTL_DIV_14 ((uint32_t)0x00007000) /*!< Divide by 15 */ -#define LCD_F_CTL_DIV_15 ((uint32_t)0x00007800) /*!< Divide by 16 */ -#define LCD_F_CTL_DIV_16 ((uint32_t)0x00008000) /*!< Divide by 17 */ -#define LCD_F_CTL_DIV_17 ((uint32_t)0x00008800) /*!< Divide by 18 */ -#define LCD_F_CTL_DIV_18 ((uint32_t)0x00009000) /*!< Divide by 19 */ -#define LCD_F_CTL_DIV_19 ((uint32_t)0x00009800) /*!< Divide by 20 */ -#define LCD_F_CTL_DIV_20 ((uint32_t)0x0000A000) /*!< Divide by 21 */ -#define LCD_F_CTL_DIV_21 ((uint32_t)0x0000A800) /*!< Divide by 22 */ -#define LCD_F_CTL_DIV_22 ((uint32_t)0x0000B000) /*!< Divide by 23 */ -#define LCD_F_CTL_DIV_23 ((uint32_t)0x0000B800) /*!< Divide by 24 */ -#define LCD_F_CTL_DIV_24 ((uint32_t)0x0000C000) /*!< Divide by 25 */ -#define LCD_F_CTL_DIV_25 ((uint32_t)0x0000C800) /*!< Divide by 26 */ -#define LCD_F_CTL_DIV_26 ((uint32_t)0x0000D000) /*!< Divide by 27 */ -#define LCD_F_CTL_DIV_27 ((uint32_t)0x0000D800) /*!< Divide by 28 */ -#define LCD_F_CTL_DIV_28 ((uint32_t)0x0000E000) /*!< Divide by 29 */ -#define LCD_F_CTL_DIV_29 ((uint32_t)0x0000E800) /*!< Divide by 30 */ -#define LCD_F_CTL_DIV_30 ((uint32_t)0x0000F000) /*!< Divide by 31 */ -#define LCD_F_CTL_DIV_31 ((uint32_t)0x0000F800) /*!< Divide by 32 */ -/* LCD_F_CTL[SSEL] Bits */ -#define LCD_F_CTL_SSEL_OFS (16) /*!< LCDSSEL Bit Offset */ -#define LCD_F_CTL_SSEL_MASK ((uint32_t)0x00030000) /*!< LCDSSEL Bit Mask */ -#define LCD_F_CTL_SSEL0 ((uint32_t)0x00010000) /*!< SSEL Bit 0 */ -#define LCD_F_CTL_SSEL1 ((uint32_t)0x00020000) /*!< SSEL Bit 1 */ -#define LCD_F_CTL_SSEL_0 ((uint32_t)0x00000000) /*!< ACLK */ -#define LCD_F_CTL_SSEL_1 ((uint32_t)0x00010000) /*!< VLOCLK */ -#define LCD_F_CTL_SSEL_2 ((uint32_t)0x00020000) /*!< REFOCLK */ -#define LCD_F_CTL_SSEL_3 ((uint32_t)0x00030000) /*!< LFXTCLK */ -/* LCD_F_BMCTL[BLKMOD] Bits */ -#define LCD_F_BMCTL_BLKMOD_OFS ( 0) /*!< LCDBLKMODx Bit Offset */ -#define LCD_F_BMCTL_BLKMOD_MASK ((uint32_t)0x00000003) /*!< LCDBLKMODx Bit Mask */ -#define LCD_F_BMCTL_BLKMOD0 ((uint32_t)0x00000001) /*!< BLKMOD Bit 0 */ -#define LCD_F_BMCTL_BLKMOD1 ((uint32_t)0x00000002) /*!< BLKMOD Bit 1 */ -#define LCD_F_BMCTL_BLKMOD_0 ((uint32_t)0x00000000) /*!< Blinking disabled */ -#define LCD_F_BMCTL_BLKMOD_1 ((uint32_t)0x00000001) /*!< Blinking of individual segments as enabled in blinking memory register */ - /* LCDBMx. */ -#define LCD_F_BMCTL_BLKMOD_2 ((uint32_t)0x00000002) /*!< Blinking of all segments */ -#define LCD_F_BMCTL_BLKMOD_3 ((uint32_t)0x00000003) /*!< Switching between display contents as stored in LCDMx and LCDBMx memory */ - /* registers. */ -/* LCD_F_BMCTL[BLKPRE] Bits */ -#define LCD_F_BMCTL_BLKPRE_OFS ( 2) /*!< LCDBLKPREx Bit Offset */ -#define LCD_F_BMCTL_BLKPRE_MASK ((uint32_t)0x0000001C) /*!< LCDBLKPREx Bit Mask */ -#define LCD_F_BMCTL_BLKPRE0 ((uint32_t)0x00000004) /*!< BLKPRE Bit 0 */ -#define LCD_F_BMCTL_BLKPRE1 ((uint32_t)0x00000008) /*!< BLKPRE Bit 1 */ -#define LCD_F_BMCTL_BLKPRE2 ((uint32_t)0x00000010) /*!< BLKPRE Bit 2 */ -#define LCD_F_BMCTL_BLKPRE_0 ((uint32_t)0x00000000) /*!< Divide by 512 */ -#define LCD_F_BMCTL_BLKPRE_1 ((uint32_t)0x00000004) /*!< Divide by 1024 */ -#define LCD_F_BMCTL_BLKPRE_2 ((uint32_t)0x00000008) /*!< Divide by 2048 */ -#define LCD_F_BMCTL_BLKPRE_3 ((uint32_t)0x0000000C) /*!< Divide by 4096 */ -#define LCD_F_BMCTL_BLKPRE_4 ((uint32_t)0x00000010) /*!< Divide by 8162 */ -#define LCD_F_BMCTL_BLKPRE_5 ((uint32_t)0x00000014) /*!< Divide by 16384 */ -#define LCD_F_BMCTL_BLKPRE_6 ((uint32_t)0x00000018) /*!< Divide by 32768 */ -#define LCD_F_BMCTL_BLKPRE_7 ((uint32_t)0x0000001C) /*!< Divide by 65536 */ -/* LCD_F_BMCTL[BLKDIV] Bits */ -#define LCD_F_BMCTL_BLKDIV_OFS ( 5) /*!< LCDBLKDIVx Bit Offset */ -#define LCD_F_BMCTL_BLKDIV_MASK ((uint32_t)0x000000E0) /*!< LCDBLKDIVx Bit Mask */ -#define LCD_F_BMCTL_BLKDIV0 ((uint32_t)0x00000020) /*!< BLKDIV Bit 0 */ -#define LCD_F_BMCTL_BLKDIV1 ((uint32_t)0x00000040) /*!< BLKDIV Bit 1 */ -#define LCD_F_BMCTL_BLKDIV2 ((uint32_t)0x00000080) /*!< BLKDIV Bit 2 */ -#define LCD_F_BMCTL_BLKDIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_BMCTL_BLKDIV_1 ((uint32_t)0x00000020) /*!< Divide by 2 */ -#define LCD_F_BMCTL_BLKDIV_2 ((uint32_t)0x00000040) /*!< Divide by 3 */ -#define LCD_F_BMCTL_BLKDIV_3 ((uint32_t)0x00000060) /*!< Divide by 4 */ -#define LCD_F_BMCTL_BLKDIV_4 ((uint32_t)0x00000080) /*!< Divide by 5 */ -#define LCD_F_BMCTL_BLKDIV_5 ((uint32_t)0x000000A0) /*!< Divide by 6 */ -#define LCD_F_BMCTL_BLKDIV_6 ((uint32_t)0x000000C0) /*!< Divide by 7 */ -#define LCD_F_BMCTL_BLKDIV_7 ((uint32_t)0x000000E0) /*!< Divide by 8 */ -/* LCD_F_BMCTL[DISP] Bits */ -#define LCD_F_BMCTL_DISP_OFS (16) /*!< LCDDISP Bit Offset */ -#define LCD_F_BMCTL_DISP ((uint32_t)0x00010000) /*!< Select LCD memory registers for display */ -/* LCD_F_BMCTL[CLRM] Bits */ -#define LCD_F_BMCTL_CLRM_OFS (17) /*!< LCDCLRM Bit Offset */ -#define LCD_F_BMCTL_CLRM ((uint32_t)0x00020000) /*!< Clear LCD memory */ -/* LCD_F_BMCTL[CLRBM] Bits */ -#define LCD_F_BMCTL_CLRBM_OFS (18) /*!< LCDCLRBM Bit Offset */ -#define LCD_F_BMCTL_CLRBM ((uint32_t)0x00040000) /*!< Clear LCD blinking memory */ -/* LCD_F_VCTL[LCD2B] Bits */ -#define LCD_F_VCTL_LCD2B_OFS ( 0) /*!< LCD2B Bit Offset */ -#define LCD_F_VCTL_LCD2B ((uint32_t)0x00000001) /*!< Bias select. */ -/* LCD_F_VCTL[EXTBIAS] Bits */ -#define LCD_F_VCTL_EXTBIAS_OFS ( 5) /*!< LCDEXTBIAS Bit Offset */ -#define LCD_F_VCTL_EXTBIAS ((uint32_t)0x00000020) /*!< V2 to V4 voltage select */ -/* LCD_F_VCTL[R03EXT] Bits */ -#define LCD_F_VCTL_R03EXT_OFS ( 6) /*!< R03EXT Bit Offset */ -#define LCD_F_VCTL_R03EXT ((uint32_t)0x00000040) /*!< V5 voltage select */ -/* LCD_F_VCTL[REXT] Bits */ -#define LCD_F_VCTL_REXT_OFS ( 7) /*!< LCDREXT Bit Offset */ -#define LCD_F_VCTL_REXT ((uint32_t)0x00000080) /*!< V2 to V4 voltage on external Rx3 pins */ -/* LCD_F_PCTL0[S0] Bits */ -#define LCD_F_PCTL0_S0_OFS ( 0) /*!< LCDS0 Bit Offset */ -#define LCD_F_PCTL0_S0 ((uint32_t)0x00000001) /*!< LCD pin 0 enable */ -/* LCD_F_PCTL0[S1] Bits */ -#define LCD_F_PCTL0_S1_OFS ( 1) /*!< LCDS1 Bit Offset */ -#define LCD_F_PCTL0_S1 ((uint32_t)0x00000002) /*!< LCD pin 1 enable */ -/* LCD_F_PCTL0[S2] Bits */ -#define LCD_F_PCTL0_S2_OFS ( 2) /*!< LCDS2 Bit Offset */ -#define LCD_F_PCTL0_S2 ((uint32_t)0x00000004) /*!< LCD pin 2 enable */ -/* LCD_F_PCTL0[S3] Bits */ -#define LCD_F_PCTL0_S3_OFS ( 3) /*!< LCDS3 Bit Offset */ -#define LCD_F_PCTL0_S3 ((uint32_t)0x00000008) /*!< LCD pin 3 enable */ -/* LCD_F_PCTL0[S4] Bits */ -#define LCD_F_PCTL0_S4_OFS ( 4) /*!< LCDS4 Bit Offset */ -#define LCD_F_PCTL0_S4 ((uint32_t)0x00000010) /*!< LCD pin 4 enable */ -/* LCD_F_PCTL0[S5] Bits */ -#define LCD_F_PCTL0_S5_OFS ( 5) /*!< LCDS5 Bit Offset */ -#define LCD_F_PCTL0_S5 ((uint32_t)0x00000020) /*!< LCD pin 5 enable */ -/* LCD_F_PCTL0[S6] Bits */ -#define LCD_F_PCTL0_S6_OFS ( 6) /*!< LCDS6 Bit Offset */ -#define LCD_F_PCTL0_S6 ((uint32_t)0x00000040) /*!< LCD pin 6 enable */ -/* LCD_F_PCTL0[S7] Bits */ -#define LCD_F_PCTL0_S7_OFS ( 7) /*!< LCDS7 Bit Offset */ -#define LCD_F_PCTL0_S7 ((uint32_t)0x00000080) /*!< LCD pin 7 enable */ -/* LCD_F_PCTL0[S8] Bits */ -#define LCD_F_PCTL0_S8_OFS ( 8) /*!< LCDS8 Bit Offset */ -#define LCD_F_PCTL0_S8 ((uint32_t)0x00000100) /*!< LCD pin 8 enable */ -/* LCD_F_PCTL0[S9] Bits */ -#define LCD_F_PCTL0_S9_OFS ( 9) /*!< LCDS9 Bit Offset */ -#define LCD_F_PCTL0_S9 ((uint32_t)0x00000200) /*!< LCD pin 9 enable */ -/* LCD_F_PCTL0[S10] Bits */ -#define LCD_F_PCTL0_S10_OFS (10) /*!< LCDS10 Bit Offset */ -#define LCD_F_PCTL0_S10 ((uint32_t)0x00000400) /*!< LCD pin 10 enable */ -/* LCD_F_PCTL0[S11] Bits */ -#define LCD_F_PCTL0_S11_OFS (11) /*!< LCDS11 Bit Offset */ -#define LCD_F_PCTL0_S11 ((uint32_t)0x00000800) /*!< LCD pin 11 enable */ -/* LCD_F_PCTL0[S12] Bits */ -#define LCD_F_PCTL0_S12_OFS (12) /*!< LCDS12 Bit Offset */ -#define LCD_F_PCTL0_S12 ((uint32_t)0x00001000) /*!< LCD pin 12 enable */ -/* LCD_F_PCTL0[S13] Bits */ -#define LCD_F_PCTL0_S13_OFS (13) /*!< LCDS13 Bit Offset */ -#define LCD_F_PCTL0_S13 ((uint32_t)0x00002000) /*!< LCD pin 13 enable */ -/* LCD_F_PCTL0[S14] Bits */ -#define LCD_F_PCTL0_S14_OFS (14) /*!< LCDS14 Bit Offset */ -#define LCD_F_PCTL0_S14 ((uint32_t)0x00004000) /*!< LCD pin 14 enable */ -/* LCD_F_PCTL0[S15] Bits */ -#define LCD_F_PCTL0_S15_OFS (15) /*!< LCDS15 Bit Offset */ -#define LCD_F_PCTL0_S15 ((uint32_t)0x00008000) /*!< LCD pin 15 enable */ -/* LCD_F_PCTL0[S16] Bits */ -#define LCD_F_PCTL0_S16_OFS (16) /*!< LCDS16 Bit Offset */ -#define LCD_F_PCTL0_S16 ((uint32_t)0x00010000) /*!< LCD pin 16 enable */ -/* LCD_F_PCTL0[S17] Bits */ -#define LCD_F_PCTL0_S17_OFS (17) /*!< LCDS17 Bit Offset */ -#define LCD_F_PCTL0_S17 ((uint32_t)0x00020000) /*!< LCD pin 17 enable */ -/* LCD_F_PCTL0[S18] Bits */ -#define LCD_F_PCTL0_S18_OFS (18) /*!< LCDS18 Bit Offset */ -#define LCD_F_PCTL0_S18 ((uint32_t)0x00040000) /*!< LCD pin 18 enable */ -/* LCD_F_PCTL0[S19] Bits */ -#define LCD_F_PCTL0_S19_OFS (19) /*!< LCDS19 Bit Offset */ -#define LCD_F_PCTL0_S19 ((uint32_t)0x00080000) /*!< LCD pin 19 enable */ -/* LCD_F_PCTL0[S20] Bits */ -#define LCD_F_PCTL0_S20_OFS (20) /*!< LCDS20 Bit Offset */ -#define LCD_F_PCTL0_S20 ((uint32_t)0x00100000) /*!< LCD pin 20 enable */ -/* LCD_F_PCTL0[S21] Bits */ -#define LCD_F_PCTL0_S21_OFS (21) /*!< LCDS21 Bit Offset */ -#define LCD_F_PCTL0_S21 ((uint32_t)0x00200000) /*!< LCD pin 21 enable */ -/* LCD_F_PCTL0[S22] Bits */ -#define LCD_F_PCTL0_S22_OFS (22) /*!< LCDS22 Bit Offset */ -#define LCD_F_PCTL0_S22 ((uint32_t)0x00400000) /*!< LCD pin 22 enable */ -/* LCD_F_PCTL0[S23] Bits */ -#define LCD_F_PCTL0_S23_OFS (23) /*!< LCDS23 Bit Offset */ -#define LCD_F_PCTL0_S23 ((uint32_t)0x00800000) /*!< LCD pin 23 enable */ -/* LCD_F_PCTL0[S24] Bits */ -#define LCD_F_PCTL0_S24_OFS (24) /*!< LCDS24 Bit Offset */ -#define LCD_F_PCTL0_S24 ((uint32_t)0x01000000) /*!< LCD pin 24 enable */ -/* LCD_F_PCTL0[S25] Bits */ -#define LCD_F_PCTL0_S25_OFS (25) /*!< LCDS25 Bit Offset */ -#define LCD_F_PCTL0_S25 ((uint32_t)0x02000000) /*!< LCD pin 25 enable */ -/* LCD_F_PCTL0[S26] Bits */ -#define LCD_F_PCTL0_S26_OFS (26) /*!< LCDS26 Bit Offset */ -#define LCD_F_PCTL0_S26 ((uint32_t)0x04000000) /*!< LCD pin 26 enable */ -/* LCD_F_PCTL0[S27] Bits */ -#define LCD_F_PCTL0_S27_OFS (27) /*!< LCDS27 Bit Offset */ -#define LCD_F_PCTL0_S27 ((uint32_t)0x08000000) /*!< LCD pin 27 enable */ -/* LCD_F_PCTL0[S28] Bits */ -#define LCD_F_PCTL0_S28_OFS (28) /*!< LCDS28 Bit Offset */ -#define LCD_F_PCTL0_S28 ((uint32_t)0x10000000) /*!< LCD pin 28 enable */ -/* LCD_F_PCTL0[S29] Bits */ -#define LCD_F_PCTL0_S29_OFS (29) /*!< LCDS29 Bit Offset */ -#define LCD_F_PCTL0_S29 ((uint32_t)0x20000000) /*!< LCD pin 29 enable */ -/* LCD_F_PCTL0[S30] Bits */ -#define LCD_F_PCTL0_S30_OFS (30) /*!< LCDS30 Bit Offset */ -#define LCD_F_PCTL0_S30 ((uint32_t)0x40000000) /*!< LCD pin 30 enable */ -/* LCD_F_PCTL0[S31] Bits */ -#define LCD_F_PCTL0_S31_OFS (31) /*!< LCDS31 Bit Offset */ -#define LCD_F_PCTL0_S31 ((uint32_t)0x80000000) /*!< LCD pin 31 enable */ -/* LCD_F_PCTL1[S32] Bits */ -#define LCD_F_PCTL1_S32_OFS ( 0) /*!< LCDS32 Bit Offset */ -#define LCD_F_PCTL1_S32 ((uint32_t)0x00000001) /*!< LCD pin 32 enable */ -/* LCD_F_PCTL1[S33] Bits */ -#define LCD_F_PCTL1_S33_OFS ( 1) /*!< LCDS33 Bit Offset */ -#define LCD_F_PCTL1_S33 ((uint32_t)0x00000002) /*!< LCD pin 33 enable */ -/* LCD_F_PCTL1[S34] Bits */ -#define LCD_F_PCTL1_S34_OFS ( 2) /*!< LCDS34 Bit Offset */ -#define LCD_F_PCTL1_S34 ((uint32_t)0x00000004) /*!< LCD pin 34 enable */ -/* LCD_F_PCTL1[S35] Bits */ -#define LCD_F_PCTL1_S35_OFS ( 3) /*!< LCDS35 Bit Offset */ -#define LCD_F_PCTL1_S35 ((uint32_t)0x00000008) /*!< LCD pin 35 enable */ -/* LCD_F_PCTL1[S36] Bits */ -#define LCD_F_PCTL1_S36_OFS ( 4) /*!< LCDS36 Bit Offset */ -#define LCD_F_PCTL1_S36 ((uint32_t)0x00000010) /*!< LCD pin 36 enable */ -/* LCD_F_PCTL1[S37] Bits */ -#define LCD_F_PCTL1_S37_OFS ( 5) /*!< LCDS37 Bit Offset */ -#define LCD_F_PCTL1_S37 ((uint32_t)0x00000020) /*!< LCD pin 37 enable */ -/* LCD_F_PCTL1[S38] Bits */ -#define LCD_F_PCTL1_S38_OFS ( 6) /*!< LCDS38 Bit Offset */ -#define LCD_F_PCTL1_S38 ((uint32_t)0x00000040) /*!< LCD pin 38 enable */ -/* LCD_F_PCTL1[S39] Bits */ -#define LCD_F_PCTL1_S39_OFS ( 7) /*!< LCDS39 Bit Offset */ -#define LCD_F_PCTL1_S39 ((uint32_t)0x00000080) /*!< LCD pin 39 enable */ -/* LCD_F_PCTL1[S40] Bits */ -#define LCD_F_PCTL1_S40_OFS ( 8) /*!< LCDS40 Bit Offset */ -#define LCD_F_PCTL1_S40 ((uint32_t)0x00000100) /*!< LCD pin 40 enable */ -/* LCD_F_PCTL1[S41] Bits */ -#define LCD_F_PCTL1_S41_OFS ( 9) /*!< LCDS41 Bit Offset */ -#define LCD_F_PCTL1_S41 ((uint32_t)0x00000200) /*!< LCD pin 41 enable */ -/* LCD_F_PCTL1[S42] Bits */ -#define LCD_F_PCTL1_S42_OFS (10) /*!< LCDS42 Bit Offset */ -#define LCD_F_PCTL1_S42 ((uint32_t)0x00000400) /*!< LCD pin 42 enable */ -/* LCD_F_PCTL1[S43] Bits */ -#define LCD_F_PCTL1_S43_OFS (11) /*!< LCDS43 Bit Offset */ -#define LCD_F_PCTL1_S43 ((uint32_t)0x00000800) /*!< LCD pin 43 enable */ -/* LCD_F_PCTL1[S44] Bits */ -#define LCD_F_PCTL1_S44_OFS (12) /*!< LCDS44 Bit Offset */ -#define LCD_F_PCTL1_S44 ((uint32_t)0x00001000) /*!< LCD pin 44 enable */ -/* LCD_F_PCTL1[S45] Bits */ -#define LCD_F_PCTL1_S45_OFS (13) /*!< LCDS45 Bit Offset */ -#define LCD_F_PCTL1_S45 ((uint32_t)0x00002000) /*!< LCD pin 45 enable */ -/* LCD_F_PCTL1[S46] Bits */ -#define LCD_F_PCTL1_S46_OFS (14) /*!< LCDS46 Bit Offset */ -#define LCD_F_PCTL1_S46 ((uint32_t)0x00004000) /*!< LCD pin 46 enable */ -/* LCD_F_PCTL1[S47] Bits */ -#define LCD_F_PCTL1_S47_OFS (15) /*!< LCDS47 Bit Offset */ -#define LCD_F_PCTL1_S47 ((uint32_t)0x00008000) /*!< LCD pin 47 enable */ -/* LCD_F_PCTL1[S48] Bits */ -#define LCD_F_PCTL1_S48_OFS (16) /*!< LCDS48 Bit Offset */ -#define LCD_F_PCTL1_S48 ((uint32_t)0x00010000) /*!< LCD pin 48 enable */ -/* LCD_F_PCTL1[S49] Bits */ -#define LCD_F_PCTL1_S49_OFS (17) /*!< LCDS49 Bit Offset */ -#define LCD_F_PCTL1_S49 ((uint32_t)0x00020000) /*!< LCD pin 49 enable */ -/* LCD_F_PCTL1[S50] Bits */ -#define LCD_F_PCTL1_S50_OFS (18) /*!< LCDS50 Bit Offset */ -#define LCD_F_PCTL1_S50 ((uint32_t)0x00040000) /*!< LCD pin 50 enable */ -/* LCD_F_PCTL1[S51] Bits */ -#define LCD_F_PCTL1_S51_OFS (19) /*!< LCDS51 Bit Offset */ -#define LCD_F_PCTL1_S51 ((uint32_t)0x00080000) /*!< LCD pin 51 enable */ -/* LCD_F_PCTL1[S52] Bits */ -#define LCD_F_PCTL1_S52_OFS (20) /*!< LCDS52 Bit Offset */ -#define LCD_F_PCTL1_S52 ((uint32_t)0x00100000) /*!< LCD pin 52 enable */ -/* LCD_F_PCTL1[S53] Bits */ -#define LCD_F_PCTL1_S53_OFS (21) /*!< LCDS53 Bit Offset */ -#define LCD_F_PCTL1_S53 ((uint32_t)0x00200000) /*!< LCD pin 53 enable */ -/* LCD_F_PCTL1[S54] Bits */ -#define LCD_F_PCTL1_S54_OFS (22) /*!< LCDS54 Bit Offset */ -#define LCD_F_PCTL1_S54 ((uint32_t)0x00400000) /*!< LCD pin 54 enable */ -/* LCD_F_PCTL1[S55] Bits */ -#define LCD_F_PCTL1_S55_OFS (23) /*!< LCDS55 Bit Offset */ -#define LCD_F_PCTL1_S55 ((uint32_t)0x00800000) /*!< LCD pin 55 enable */ -/* LCD_F_PCTL1[S56] Bits */ -#define LCD_F_PCTL1_S56_OFS (24) /*!< LCDS56 Bit Offset */ -#define LCD_F_PCTL1_S56 ((uint32_t)0x01000000) /*!< LCD pin 56 enable */ -/* LCD_F_PCTL1[S57] Bits */ -#define LCD_F_PCTL1_S57_OFS (25) /*!< LCDS57 Bit Offset */ -#define LCD_F_PCTL1_S57 ((uint32_t)0x02000000) /*!< LCD pin 57 enable */ -/* LCD_F_PCTL1[S58] Bits */ -#define LCD_F_PCTL1_S58_OFS (26) /*!< LCDS58 Bit Offset */ -#define LCD_F_PCTL1_S58 ((uint32_t)0x04000000) /*!< LCD pin 58 enable */ -/* LCD_F_PCTL1[S59] Bits */ -#define LCD_F_PCTL1_S59_OFS (27) /*!< LCDS59 Bit Offset */ -#define LCD_F_PCTL1_S59 ((uint32_t)0x08000000) /*!< LCD pin 59 enable */ -/* LCD_F_PCTL1[S60] Bits */ -#define LCD_F_PCTL1_S60_OFS (28) /*!< LCDS60 Bit Offset */ -#define LCD_F_PCTL1_S60 ((uint32_t)0x10000000) /*!< LCD pin 60 enable */ -/* LCD_F_PCTL1[S61] Bits */ -#define LCD_F_PCTL1_S61_OFS (29) /*!< LCDS61 Bit Offset */ -#define LCD_F_PCTL1_S61 ((uint32_t)0x20000000) /*!< LCD pin 61 enable */ -/* LCD_F_PCTL1[S62] Bits */ -#define LCD_F_PCTL1_S62_OFS (30) /*!< LCDS62 Bit Offset */ -#define LCD_F_PCTL1_S62 ((uint32_t)0x40000000) /*!< LCD pin 62 enable */ -/* LCD_F_PCTL1[S63] Bits */ -#define LCD_F_PCTL1_S63_OFS (31) /*!< LCDS63 Bit Offset */ -#define LCD_F_PCTL1_S63 ((uint32_t)0x80000000) /*!< LCD pin 63 enable */ -/* LCD_F_CSSEL0[CSS0] Bits */ -#define LCD_F_CSSEL0_CSS0_OFS ( 0) /*!< LCDCSS0 Bit Offset */ -#define LCD_F_CSSEL0_CSS0 ((uint32_t)0x00000001) /*!< L0 Com Seg select */ -/* LCD_F_CSSEL0[CSS1] Bits */ -#define LCD_F_CSSEL0_CSS1_OFS ( 1) /*!< LCDCSS1 Bit Offset */ -#define LCD_F_CSSEL0_CSS1 ((uint32_t)0x00000002) /*!< L1 Com Seg select */ -/* LCD_F_CSSEL0[CSS2] Bits */ -#define LCD_F_CSSEL0_CSS2_OFS ( 2) /*!< LCDCSS2 Bit Offset */ -#define LCD_F_CSSEL0_CSS2 ((uint32_t)0x00000004) /*!< L2 Com Seg select */ -/* LCD_F_CSSEL0[CSS3] Bits */ -#define LCD_F_CSSEL0_CSS3_OFS ( 3) /*!< LCDCSS3 Bit Offset */ -#define LCD_F_CSSEL0_CSS3 ((uint32_t)0x00000008) /*!< L3 Com Seg select */ -/* LCD_F_CSSEL0[CSS4] Bits */ -#define LCD_F_CSSEL0_CSS4_OFS ( 4) /*!< LCDCSS4 Bit Offset */ -#define LCD_F_CSSEL0_CSS4 ((uint32_t)0x00000010) /*!< L4 Com Seg select */ -/* LCD_F_CSSEL0[CSS5] Bits */ -#define LCD_F_CSSEL0_CSS5_OFS ( 5) /*!< LCDCSS5 Bit Offset */ -#define LCD_F_CSSEL0_CSS5 ((uint32_t)0x00000020) /*!< L5 Com Seg select */ -/* LCD_F_CSSEL0[CSS6] Bits */ -#define LCD_F_CSSEL0_CSS6_OFS ( 6) /*!< LCDCSS6 Bit Offset */ -#define LCD_F_CSSEL0_CSS6 ((uint32_t)0x00000040) /*!< L6 Com Seg select */ -/* LCD_F_CSSEL0[CSS7] Bits */ -#define LCD_F_CSSEL0_CSS7_OFS ( 7) /*!< LCDCSS7 Bit Offset */ -#define LCD_F_CSSEL0_CSS7 ((uint32_t)0x00000080) /*!< L7 Com Seg select */ -/* LCD_F_CSSEL0[CSS8] Bits */ -#define LCD_F_CSSEL0_CSS8_OFS ( 8) /*!< LCDCSS8 Bit Offset */ -#define LCD_F_CSSEL0_CSS8 ((uint32_t)0x00000100) /*!< L8 Com Seg select */ -/* LCD_F_CSSEL0[CSS9] Bits */ -#define LCD_F_CSSEL0_CSS9_OFS ( 9) /*!< LCDCSS9 Bit Offset */ -#define LCD_F_CSSEL0_CSS9 ((uint32_t)0x00000200) /*!< L9 Com Seg select */ -/* LCD_F_CSSEL0[CSS10] Bits */ -#define LCD_F_CSSEL0_CSS10_OFS (10) /*!< LCDCSS10 Bit Offset */ -#define LCD_F_CSSEL0_CSS10 ((uint32_t)0x00000400) /*!< L10 Com Seg select */ -/* LCD_F_CSSEL0[CSS11] Bits */ -#define LCD_F_CSSEL0_CSS11_OFS (11) /*!< LCDCSS11 Bit Offset */ -#define LCD_F_CSSEL0_CSS11 ((uint32_t)0x00000800) /*!< L11 Com Seg select */ -/* LCD_F_CSSEL0[CSS12] Bits */ -#define LCD_F_CSSEL0_CSS12_OFS (12) /*!< LCDCSS12 Bit Offset */ -#define LCD_F_CSSEL0_CSS12 ((uint32_t)0x00001000) /*!< L12 Com Seg select */ -/* LCD_F_CSSEL0[CSS13] Bits */ -#define LCD_F_CSSEL0_CSS13_OFS (13) /*!< LCDCSS13 Bit Offset */ -#define LCD_F_CSSEL0_CSS13 ((uint32_t)0x00002000) /*!< L13 Com Seg select */ -/* LCD_F_CSSEL0[CSS14] Bits */ -#define LCD_F_CSSEL0_CSS14_OFS (14) /*!< LCDCSS14 Bit Offset */ -#define LCD_F_CSSEL0_CSS14 ((uint32_t)0x00004000) /*!< L14 Com Seg select */ -/* LCD_F_CSSEL0[CSS15] Bits */ -#define LCD_F_CSSEL0_CSS15_OFS (15) /*!< LCDCSS15 Bit Offset */ -#define LCD_F_CSSEL0_CSS15 ((uint32_t)0x00008000) /*!< L15 Com Seg select */ -/* LCD_F_CSSEL0[CSS16] Bits */ -#define LCD_F_CSSEL0_CSS16_OFS (16) /*!< LCDCSS16 Bit Offset */ -#define LCD_F_CSSEL0_CSS16 ((uint32_t)0x00010000) /*!< L16 Com Seg select */ -/* LCD_F_CSSEL0[CSS17] Bits */ -#define LCD_F_CSSEL0_CSS17_OFS (17) /*!< LCDCSS17 Bit Offset */ -#define LCD_F_CSSEL0_CSS17 ((uint32_t)0x00020000) /*!< L17 Com Seg select */ -/* LCD_F_CSSEL0[CSS18] Bits */ -#define LCD_F_CSSEL0_CSS18_OFS (18) /*!< LCDCSS18 Bit Offset */ -#define LCD_F_CSSEL0_CSS18 ((uint32_t)0x00040000) /*!< L18 Com Seg select */ -/* LCD_F_CSSEL0[CSS19] Bits */ -#define LCD_F_CSSEL0_CSS19_OFS (19) /*!< LCDCSS19 Bit Offset */ -#define LCD_F_CSSEL0_CSS19 ((uint32_t)0x00080000) /*!< L19 Com Seg select */ -/* LCD_F_CSSEL0[CSS20] Bits */ -#define LCD_F_CSSEL0_CSS20_OFS (20) /*!< LCDCSS20 Bit Offset */ -#define LCD_F_CSSEL0_CSS20 ((uint32_t)0x00100000) /*!< L20 Com Seg select */ -/* LCD_F_CSSEL0[CSS21] Bits */ -#define LCD_F_CSSEL0_CSS21_OFS (21) /*!< LCDCSS21 Bit Offset */ -#define LCD_F_CSSEL0_CSS21 ((uint32_t)0x00200000) /*!< L21 Com Seg select */ -/* LCD_F_CSSEL0[CSS22] Bits */ -#define LCD_F_CSSEL0_CSS22_OFS (22) /*!< LCDCSS22 Bit Offset */ -#define LCD_F_CSSEL0_CSS22 ((uint32_t)0x00400000) /*!< L22 Com Seg select */ -/* LCD_F_CSSEL0[CSS23] Bits */ -#define LCD_F_CSSEL0_CSS23_OFS (23) /*!< LCDCSS23 Bit Offset */ -#define LCD_F_CSSEL0_CSS23 ((uint32_t)0x00800000) /*!< L23 Com Seg select */ -/* LCD_F_CSSEL0[CSS24] Bits */ -#define LCD_F_CSSEL0_CSS24_OFS (24) /*!< LCDCSS24 Bit Offset */ -#define LCD_F_CSSEL0_CSS24 ((uint32_t)0x01000000) /*!< L24 Com Seg select */ -/* LCD_F_CSSEL0[CSS25] Bits */ -#define LCD_F_CSSEL0_CSS25_OFS (25) /*!< LCDCSS25 Bit Offset */ -#define LCD_F_CSSEL0_CSS25 ((uint32_t)0x02000000) /*!< L25 Com Seg select */ -/* LCD_F_CSSEL0[CSS26] Bits */ -#define LCD_F_CSSEL0_CSS26_OFS (26) /*!< LCDCSS26 Bit Offset */ -#define LCD_F_CSSEL0_CSS26 ((uint32_t)0x04000000) /*!< L26 Com Seg select */ -/* LCD_F_CSSEL0[CSS27] Bits */ -#define LCD_F_CSSEL0_CSS27_OFS (27) /*!< LCDCSS27 Bit Offset */ -#define LCD_F_CSSEL0_CSS27 ((uint32_t)0x08000000) /*!< L27 Com Seg select */ -/* LCD_F_CSSEL0[CSS28] Bits */ -#define LCD_F_CSSEL0_CSS28_OFS (28) /*!< LCDCSS28 Bit Offset */ -#define LCD_F_CSSEL0_CSS28 ((uint32_t)0x10000000) /*!< L28 Com Seg select */ -/* LCD_F_CSSEL0[CSS29] Bits */ -#define LCD_F_CSSEL0_CSS29_OFS (29) /*!< LCDCSS29 Bit Offset */ -#define LCD_F_CSSEL0_CSS29 ((uint32_t)0x20000000) /*!< L29 Com Seg select */ -/* LCD_F_CSSEL0[CSS30] Bits */ -#define LCD_F_CSSEL0_CSS30_OFS (30) /*!< LCDCSS30 Bit Offset */ -#define LCD_F_CSSEL0_CSS30 ((uint32_t)0x40000000) /*!< L30 Com Seg select */ -/* LCD_F_CSSEL0[CSS31] Bits */ -#define LCD_F_CSSEL0_CSS31_OFS (31) /*!< LCDCSS31 Bit Offset */ -#define LCD_F_CSSEL0_CSS31 ((uint32_t)0x80000000) /*!< L31 Com Seg select */ -/* LCD_F_CSSEL1[CSS32] Bits */ -#define LCD_F_CSSEL1_CSS32_OFS ( 0) /*!< LCDCSS32 Bit Offset */ -#define LCD_F_CSSEL1_CSS32 ((uint32_t)0x00000001) /*!< L32 Com Seg select */ -/* LCD_F_CSSEL1[CSS33] Bits */ -#define LCD_F_CSSEL1_CSS33_OFS ( 1) /*!< LCDCSS33 Bit Offset */ -#define LCD_F_CSSEL1_CSS33 ((uint32_t)0x00000002) /*!< L33 Com Seg select */ -/* LCD_F_CSSEL1[CSS34] Bits */ -#define LCD_F_CSSEL1_CSS34_OFS ( 2) /*!< LCDCSS34 Bit Offset */ -#define LCD_F_CSSEL1_CSS34 ((uint32_t)0x00000004) /*!< L34 Com Seg select */ -/* LCD_F_CSSEL1[CSS35] Bits */ -#define LCD_F_CSSEL1_CSS35_OFS ( 3) /*!< LCDCSS35 Bit Offset */ -#define LCD_F_CSSEL1_CSS35 ((uint32_t)0x00000008) /*!< L35 Com Seg select */ -/* LCD_F_CSSEL1[CSS36] Bits */ -#define LCD_F_CSSEL1_CSS36_OFS ( 4) /*!< LCDCSS36 Bit Offset */ -#define LCD_F_CSSEL1_CSS36 ((uint32_t)0x00000010) /*!< L36 Com Seg select */ -/* LCD_F_CSSEL1[CSS37] Bits */ -#define LCD_F_CSSEL1_CSS37_OFS ( 5) /*!< LCDCSS37 Bit Offset */ -#define LCD_F_CSSEL1_CSS37 ((uint32_t)0x00000020) /*!< L37 Com Seg select */ -/* LCD_F_CSSEL1[CSS38] Bits */ -#define LCD_F_CSSEL1_CSS38_OFS ( 6) /*!< LCDCSS38 Bit Offset */ -#define LCD_F_CSSEL1_CSS38 ((uint32_t)0x00000040) /*!< L38 Com Seg select */ -/* LCD_F_CSSEL1[CSS39] Bits */ -#define LCD_F_CSSEL1_CSS39_OFS ( 7) /*!< LCDCSS39 Bit Offset */ -#define LCD_F_CSSEL1_CSS39 ((uint32_t)0x00000080) /*!< L39 Com Seg select */ -/* LCD_F_CSSEL1[CSS40] Bits */ -#define LCD_F_CSSEL1_CSS40_OFS ( 8) /*!< LCDCSS40 Bit Offset */ -#define LCD_F_CSSEL1_CSS40 ((uint32_t)0x00000100) /*!< L40 Com Seg select */ -/* LCD_F_CSSEL1[CSS41] Bits */ -#define LCD_F_CSSEL1_CSS41_OFS ( 9) /*!< LCDCSS41 Bit Offset */ -#define LCD_F_CSSEL1_CSS41 ((uint32_t)0x00000200) /*!< L41 Com Seg select */ -/* LCD_F_CSSEL1[CSS42] Bits */ -#define LCD_F_CSSEL1_CSS42_OFS (10) /*!< LCDCSS42 Bit Offset */ -#define LCD_F_CSSEL1_CSS42 ((uint32_t)0x00000400) /*!< L42 Com Seg select */ -/* LCD_F_CSSEL1[CSS43] Bits */ -#define LCD_F_CSSEL1_CSS43_OFS (11) /*!< LCDCSS43 Bit Offset */ -#define LCD_F_CSSEL1_CSS43 ((uint32_t)0x00000800) /*!< L43 Com Seg select */ -/* LCD_F_CSSEL1[CSS44] Bits */ -#define LCD_F_CSSEL1_CSS44_OFS (12) /*!< LCDCSS44 Bit Offset */ -#define LCD_F_CSSEL1_CSS44 ((uint32_t)0x00001000) /*!< L44 Com Seg select */ -/* LCD_F_CSSEL1[CSS45] Bits */ -#define LCD_F_CSSEL1_CSS45_OFS (13) /*!< LCDCSS45 Bit Offset */ -#define LCD_F_CSSEL1_CSS45 ((uint32_t)0x00002000) /*!< L45 Com Seg select */ -/* LCD_F_CSSEL1[CSS46] Bits */ -#define LCD_F_CSSEL1_CSS46_OFS (14) /*!< LCDCSS46 Bit Offset */ -#define LCD_F_CSSEL1_CSS46 ((uint32_t)0x00004000) /*!< L46 Com Seg select */ -/* LCD_F_CSSEL1[CSS47] Bits */ -#define LCD_F_CSSEL1_CSS47_OFS (15) /*!< LCDCSS47 Bit Offset */ -#define LCD_F_CSSEL1_CSS47 ((uint32_t)0x00008000) /*!< L47 Com Seg select */ -/* LCD_F_CSSEL1[CSS48] Bits */ -#define LCD_F_CSSEL1_CSS48_OFS (16) /*!< LCDCSS48 Bit Offset */ -#define LCD_F_CSSEL1_CSS48 ((uint32_t)0x00010000) /*!< L48 Com Seg select */ -/* LCD_F_CSSEL1[CSS49] Bits */ -#define LCD_F_CSSEL1_CSS49_OFS (17) /*!< LCDCSS49 Bit Offset */ -#define LCD_F_CSSEL1_CSS49 ((uint32_t)0x00020000) /*!< L49 Com Seg select */ -/* LCD_F_CSSEL1[CSS50] Bits */ -#define LCD_F_CSSEL1_CSS50_OFS (18) /*!< LCDCSS50 Bit Offset */ -#define LCD_F_CSSEL1_CSS50 ((uint32_t)0x00040000) /*!< L50 Com Seg select */ -/* LCD_F_CSSEL1[CSS51] Bits */ -#define LCD_F_CSSEL1_CSS51_OFS (19) /*!< LCDCSS51 Bit Offset */ -#define LCD_F_CSSEL1_CSS51 ((uint32_t)0x00080000) /*!< L51 Com Seg select */ -/* LCD_F_CSSEL1[CSS52] Bits */ -#define LCD_F_CSSEL1_CSS52_OFS (20) /*!< LCDCSS52 Bit Offset */ -#define LCD_F_CSSEL1_CSS52 ((uint32_t)0x00100000) /*!< L52 Com Seg select */ -/* LCD_F_CSSEL1[CSS53] Bits */ -#define LCD_F_CSSEL1_CSS53_OFS (21) /*!< LCDCSS53 Bit Offset */ -#define LCD_F_CSSEL1_CSS53 ((uint32_t)0x00200000) /*!< L53 Com Seg select */ -/* LCD_F_CSSEL1[CSS54] Bits */ -#define LCD_F_CSSEL1_CSS54_OFS (22) /*!< LCDCSS54 Bit Offset */ -#define LCD_F_CSSEL1_CSS54 ((uint32_t)0x00400000) /*!< L54 Com Seg select */ -/* LCD_F_CSSEL1[CSS55] Bits */ -#define LCD_F_CSSEL1_CSS55_OFS (23) /*!< LCDCSS55 Bit Offset */ -#define LCD_F_CSSEL1_CSS55 ((uint32_t)0x00800000) /*!< L55 Com Seg select */ -/* LCD_F_CSSEL1[CSS56] Bits */ -#define LCD_F_CSSEL1_CSS56_OFS (24) /*!< LCDCSS56 Bit Offset */ -#define LCD_F_CSSEL1_CSS56 ((uint32_t)0x01000000) /*!< L56 Com Seg select */ -/* LCD_F_CSSEL1[CSS57] Bits */ -#define LCD_F_CSSEL1_CSS57_OFS (25) /*!< LCDCSS57 Bit Offset */ -#define LCD_F_CSSEL1_CSS57 ((uint32_t)0x02000000) /*!< L57 Com Seg select */ -/* LCD_F_CSSEL1[CSS58] Bits */ -#define LCD_F_CSSEL1_CSS58_OFS (26) /*!< LCDCSS58 Bit Offset */ -#define LCD_F_CSSEL1_CSS58 ((uint32_t)0x04000000) /*!< L58 Com Seg select */ -/* LCD_F_CSSEL1[CSS59] Bits */ -#define LCD_F_CSSEL1_CSS59_OFS (27) /*!< LCDCSS59 Bit Offset */ -#define LCD_F_CSSEL1_CSS59 ((uint32_t)0x08000000) /*!< L59 Com Seg select */ -/* LCD_F_CSSEL1[CSS60] Bits */ -#define LCD_F_CSSEL1_CSS60_OFS (28) /*!< LCDCSS60 Bit Offset */ -#define LCD_F_CSSEL1_CSS60 ((uint32_t)0x10000000) /*!< L60 Com Seg select */ -/* LCD_F_CSSEL1[CSS61] Bits */ -#define LCD_F_CSSEL1_CSS61_OFS (29) /*!< LCDCSS61 Bit Offset */ -#define LCD_F_CSSEL1_CSS61 ((uint32_t)0x20000000) /*!< L61 Com Seg select */ -/* LCD_F_CSSEL1[CSS62] Bits */ -#define LCD_F_CSSEL1_CSS62_OFS (30) /*!< LCDCSS62 Bit Offset */ -#define LCD_F_CSSEL1_CSS62 ((uint32_t)0x40000000) /*!< L62 Com Seg select */ -/* LCD_F_CSSEL1[CSS63] Bits */ -#define LCD_F_CSSEL1_CSS63_OFS (31) /*!< LCDCSS63 Bit Offset */ -#define LCD_F_CSSEL1_CSS63 ((uint32_t)0x80000000) /*!< L63 Com Seg select */ -/* LCD_F_ANMCTL[ANMEN] Bits */ -#define LCD_F_ANMCTL_ANMEN_OFS ( 0) /*!< LCDANMEN Bit Offset */ -#define LCD_F_ANMCTL_ANMEN ((uint32_t)0x00000001) /*!< Enable Animation */ -/* LCD_F_ANMCTL[ANMSTP] Bits */ -#define LCD_F_ANMCTL_ANMSTP_OFS ( 1) /*!< LCDANMSTP Bit Offset */ -#define LCD_F_ANMCTL_ANMSTP_MASK ((uint32_t)0x0000000E) /*!< LCDANMSTP Bit Mask */ -#define LCD_F_ANMCTL_ANMSTP0 ((uint32_t)0x00000002) /*!< ANMSTP Bit 0 */ -#define LCD_F_ANMCTL_ANMSTP1 ((uint32_t)0x00000004) /*!< ANMSTP Bit 1 */ -#define LCD_F_ANMCTL_ANMSTP2 ((uint32_t)0x00000008) /*!< ANMSTP Bit 2 */ -#define LCD_F_ANMCTL_ANMSTP_0 ((uint32_t)0x00000000) /*!< T0 */ -#define LCD_F_ANMCTL_ANMSTP_1 ((uint32_t)0x00000002) /*!< T0 to T1 */ -#define LCD_F_ANMCTL_ANMSTP_2 ((uint32_t)0x00000004) /*!< T0 to T2 */ -#define LCD_F_ANMCTL_ANMSTP_3 ((uint32_t)0x00000006) /*!< T0 to T3 */ -#define LCD_F_ANMCTL_ANMSTP_4 ((uint32_t)0x00000008) /*!< T0 to T4 */ -#define LCD_F_ANMCTL_ANMSTP_5 ((uint32_t)0x0000000A) /*!< T0 to T5 */ -#define LCD_F_ANMCTL_ANMSTP_6 ((uint32_t)0x0000000C) /*!< T0 to T6 */ -#define LCD_F_ANMCTL_ANMSTP_7 ((uint32_t)0x0000000E) /*!< T0 to T7 */ -/* LCD_F_ANMCTL[ANMCLR] Bits */ -#define LCD_F_ANMCTL_ANMCLR_OFS ( 7) /*!< LCDANMCLR Bit Offset */ -#define LCD_F_ANMCTL_ANMCLR ((uint32_t)0x00000080) /*!< Clear Animation Memory */ -/* LCD_F_ANMCTL[ANMPRE] Bits */ -#define LCD_F_ANMCTL_ANMPRE_OFS (16) /*!< LCDANMPREx Bit Offset */ -#define LCD_F_ANMCTL_ANMPRE_MASK ((uint32_t)0x00070000) /*!< LCDANMPREx Bit Mask */ -#define LCD_F_ANMCTL_ANMPRE0 ((uint32_t)0x00010000) /*!< ANMPRE Bit 0 */ -#define LCD_F_ANMCTL_ANMPRE1 ((uint32_t)0x00020000) /*!< ANMPRE Bit 1 */ -#define LCD_F_ANMCTL_ANMPRE2 ((uint32_t)0x00040000) /*!< ANMPRE Bit 2 */ -#define LCD_F_ANMCTL_ANMPRE_0 ((uint32_t)0x00000000) /*!< Divide by 512 */ -#define LCD_F_ANMCTL_ANMPRE_1 ((uint32_t)0x00010000) /*!< Divide by 1024 */ -#define LCD_F_ANMCTL_ANMPRE_2 ((uint32_t)0x00020000) /*!< Divide by 2048 */ -#define LCD_F_ANMCTL_ANMPRE_3 ((uint32_t)0x00030000) /*!< Divide by 4096 */ -#define LCD_F_ANMCTL_ANMPRE_4 ((uint32_t)0x00040000) /*!< Divide by 8162 */ -#define LCD_F_ANMCTL_ANMPRE_5 ((uint32_t)0x00050000) /*!< Divide by 16384 */ -#define LCD_F_ANMCTL_ANMPRE_6 ((uint32_t)0x00060000) /*!< Divide by 32768 */ -#define LCD_F_ANMCTL_ANMPRE_7 ((uint32_t)0x00070000) /*!< Divide by 65536 */ -/* LCD_F_ANMCTL[ANMDIV] Bits */ -#define LCD_F_ANMCTL_ANMDIV_OFS (19) /*!< LCDANMDIVx Bit Offset */ -#define LCD_F_ANMCTL_ANMDIV_MASK ((uint32_t)0x00380000) /*!< LCDANMDIVx Bit Mask */ -#define LCD_F_ANMCTL_ANMDIV0 ((uint32_t)0x00080000) /*!< ANMDIV Bit 0 */ -#define LCD_F_ANMCTL_ANMDIV1 ((uint32_t)0x00100000) /*!< ANMDIV Bit 1 */ -#define LCD_F_ANMCTL_ANMDIV2 ((uint32_t)0x00200000) /*!< ANMDIV Bit 2 */ -#define LCD_F_ANMCTL_ANMDIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_ANMCTL_ANMDIV_1 ((uint32_t)0x00080000) /*!< Divide by 2 */ -#define LCD_F_ANMCTL_ANMDIV_2 ((uint32_t)0x00100000) /*!< Divide by 3 */ -#define LCD_F_ANMCTL_ANMDIV_3 ((uint32_t)0x00180000) /*!< Divide by 4 */ -#define LCD_F_ANMCTL_ANMDIV_4 ((uint32_t)0x00200000) /*!< Divide by 5 */ -#define LCD_F_ANMCTL_ANMDIV_5 ((uint32_t)0x00280000) /*!< Divide by 6 */ -#define LCD_F_ANMCTL_ANMDIV_6 ((uint32_t)0x00300000) /*!< Divide by 7 */ -#define LCD_F_ANMCTL_ANMDIV_7 ((uint32_t)0x00380000) /*!< Divide by 8 */ -/* LCD_F_IE[BLKOFFIE] Bits */ -#define LCD_F_IE_BLKOFFIE_OFS ( 1) /*!< LCDBLKOFFIE Bit Offset */ -#define LCD_F_IE_BLKOFFIE ((uint32_t)0x00000002) /*!< LCD Blink, segments off interrupt enable */ -/* LCD_F_IE[BLKONIE] Bits */ -#define LCD_F_IE_BLKONIE_OFS ( 2) /*!< LCDBLKONIE Bit Offset */ -#define LCD_F_IE_BLKONIE ((uint32_t)0x00000004) /*!< LCD Blink, segments on interrupt enable */ -/* LCD_F_IE[FRMIE] Bits */ -#define LCD_F_IE_FRMIE_OFS ( 3) /*!< LCDFRMIE Bit Offset */ -#define LCD_F_IE_FRMIE ((uint32_t)0x00000008) /*!< LCD Frame interrupt enable */ -/* LCD_F_IE[ANMSTPIE] Bits */ -#define LCD_F_IE_ANMSTPIE_OFS ( 8) /*!< LCDANMSTPIE Bit Offset */ -#define LCD_F_IE_ANMSTPIE ((uint32_t)0x00000100) /*!< LCD Animation step interrupt enable */ -/* LCD_F_IE[ANMLOOPIE] Bits */ -#define LCD_F_IE_ANMLOOPIE_OFS ( 9) /*!< LCDANMLOOPIE Bit Offset */ -#define LCD_F_IE_ANMLOOPIE ((uint32_t)0x00000200) /*!< LCD Animation loop interrupt enable */ -/* LCD_F_IFG[BLKOFFIFG] Bits */ -#define LCD_F_IFG_BLKOFFIFG_OFS ( 1) /*!< LCDBLKOFFIFG Bit Offset */ -#define LCD_F_IFG_BLKOFFIFG ((uint32_t)0x00000002) /*!< LCD Blink, segments off interrupt flag */ -/* LCD_F_IFG[BLKONIFG] Bits */ -#define LCD_F_IFG_BLKONIFG_OFS ( 2) /*!< LCDBLKONIFG Bit Offset */ -#define LCD_F_IFG_BLKONIFG ((uint32_t)0x00000004) /*!< LCD Blink, segments on interrupt flag */ -/* LCD_F_IFG[FRMIFG] Bits */ -#define LCD_F_IFG_FRMIFG_OFS ( 3) /*!< LCDFRMIFG Bit Offset */ -#define LCD_F_IFG_FRMIFG ((uint32_t)0x00000008) /*!< LCD Frame interrupt flag */ -/* LCD_F_IFG[ANMSTPIFG] Bits */ -#define LCD_F_IFG_ANMSTPIFG_OFS ( 8) /*!< LCDANMSTPIFG Bit Offset */ -#define LCD_F_IFG_ANMSTPIFG ((uint32_t)0x00000100) /*!< LCD Animation step interrupt flag */ -/* LCD_F_IFG[ANMLOOPIFG] Bits */ -#define LCD_F_IFG_ANMLOOPIFG_OFS ( 9) /*!< LCDANMLOOPIFG Bit Offset */ -#define LCD_F_IFG_ANMLOOPIFG ((uint32_t)0x00000200) /*!< LCD Animation loop interrupt flag */ -/* LCD_F_SETIFG[SETLCDBLKOFFIFG] Bits */ -#define LCD_F_SETIFG_SETLCDBLKOFFIFG_OFS ( 1) /*!< SETLCDBLKOFFIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDBLKOFFIFG ((uint32_t)0x00000002) /*!< Sets LCDBLKOFFIFG */ -/* LCD_F_SETIFG[SETLCDBLKONIFG] Bits */ -#define LCD_F_SETIFG_SETLCDBLKONIFG_OFS ( 2) /*!< SETLCDBLKONIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDBLKONIFG ((uint32_t)0x00000004) /*!< Sets LCDBLKONIFG */ -/* LCD_F_SETIFG[SETLCDFRMIFG] Bits */ -#define LCD_F_SETIFG_SETLCDFRMIFG_OFS ( 3) /*!< SETLCDFRMIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDFRMIFG ((uint32_t)0x00000008) /*!< Sets LCDFRMIFG */ -/* LCD_F_SETIFG[SETLCDANMSTPIFG] Bits */ -#define LCD_F_SETIFG_SETLCDANMSTPIFG_OFS ( 8) /*!< SETLCDANMSTPIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDANMSTPIFG ((uint32_t)0x00000100) /*!< Sets LCDANMSTPIFG */ -/* LCD_F_SETIFG[SETLCDANMLOOPIFG] Bits */ -#define LCD_F_SETIFG_SETLCDANMLOOPIFG_OFS ( 9) /*!< SETLCDANMLOOPIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDANMLOOPIFG ((uint32_t)0x00000200) /*!< Sets LCDANMLOOPIFG */ -/* LCD_F_CLRIFG[CLRLCDBLKOFFIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDBLKOFFIFG_OFS ( 1) /*!< CLRLCDBLKOFFIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDBLKOFFIFG ((uint32_t)0x00000002) /*!< Clears LCDBLKOFFIFG */ -/* LCD_F_CLRIFG[CLRLCDBLKONIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDBLKONIFG_OFS ( 2) /*!< CLRLCDBLKONIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDBLKONIFG ((uint32_t)0x00000004) /*!< Clears LCDBLKONIFG */ -/* LCD_F_CLRIFG[CLRLCDFRMIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDFRMIFG_OFS ( 3) /*!< CLRLCDFRMIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDFRMIFG ((uint32_t)0x00000008) /*!< Clears LCDFRMIFG */ -/* LCD_F_CLRIFG[CLRLCDANMSTPIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDANMSTPIFG_OFS ( 8) /*!< CLRLCDANMSTPIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDANMSTPIFG ((uint32_t)0x00000100) /*!< Clears LCDANMSTPIFG */ -/* LCD_F_CLRIFG[CLRLCDANMLOOPIFG] Bits */ -#define LCD_F_CLRIFG_CLRLCDANMLOOPIFG_OFS ( 9) /*!< CLRLCDANMLOOPIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDANMLOOPIFG ((uint32_t)0x00000200) /*!< Clears LCDANMLOOPIFG */ - -/****************************************************************************** -* MPU Bits -******************************************************************************/ - -/* Pre-defined bitfield values */ - -/* MPU_RASR_SIZE Bitfield Bits */ -#define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /*!< 32B */ -#define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /*!< 64B */ -#define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /*!< 128B */ -#define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /*!< 256B */ -#define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /*!< 512B */ -#define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /*!< 1KB */ -#define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /*!< 2KB */ -#define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /*!< 4KB */ -#define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /*!< 8KB */ -#define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /*!< 16KB */ -#define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /*!< 32KB */ -#define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /*!< 64KB */ -#define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /*!< 128KB */ -#define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /*!< 256KB */ -#define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /*!< 512KB */ -#define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /*!< 1MB */ -#define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /*!< 2MB */ -#define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /*!< 4MB */ -#define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /*!< 8MB */ -#define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /*!< 16MB */ -#define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /*!< 32MB */ -#define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /*!< 64MB */ -#define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /*!< 128MB */ -#define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /*!< 256MB */ -#define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /*!< 512MB */ -#define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /*!< 1GB */ -#define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /*!< 2GB */ -#define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /*!< 4GB */ - -/* MPU_RASR_AP Bitfield Bits */ -#define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /*!< Privileged permissions: No access. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /*!< Privileged permissions: Read-write. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /*!< Privileged permissions: Read-write. User permissions: Read-only. */ -#define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /*!< Privileged permissions: Read-write. User permissions: Read-write. */ -#define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /*!< Privileged permissions: Read-only. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /*!< Privileged permissions: Read-only. User permissions: Read-only. */ - -/* MPU_RASR_XN Bitfield Bits */ -#define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /*!< Instruction access enabled */ -#define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /*!< Instruction access disabled */ - - -/****************************************************************************** -* NVIC Bits -******************************************************************************/ - -/* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */ -#define NVIC_IPR0_PRI_0_OFS ( 0) /*!< PRI_0 Offset */ -#define NVIC_IPR0_PRI_0_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */ -#define NVIC_IPR0_PRI_1_OFS ( 8) /*!< PRI_1 Offset */ -#define NVIC_IPR0_PRI_1_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */ -#define NVIC_IPR0_PRI_2_OFS (16) /*!< PRI_2 Offset */ -#define NVIC_IPR0_PRI_2_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */ -#define NVIC_IPR0_PRI_3_OFS (24) /*!< PRI_3 Offset */ -#define NVIC_IPR0_PRI_3_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */ -#define NVIC_IPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define NVIC_IPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */ -#define NVIC_IPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define NVIC_IPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */ -#define NVIC_IPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define NVIC_IPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */ -#define NVIC_IPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define NVIC_IPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */ -#define NVIC_IPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define NVIC_IPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */ -#define NVIC_IPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define NVIC_IPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */ -#define NVIC_IPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define NVIC_IPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */ -#define NVIC_IPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define NVIC_IPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */ -#define NVIC_IPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define NVIC_IPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */ -#define NVIC_IPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define NVIC_IPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */ -#define NVIC_IPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define NVIC_IPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */ -#define NVIC_IPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define NVIC_IPR3_PRI_15_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */ -#define NVIC_IPR4_PRI_16_OFS ( 0) /*!< PRI_16 Offset */ -#define NVIC_IPR4_PRI_16_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */ -#define NVIC_IPR4_PRI_17_OFS ( 8) /*!< PRI_17 Offset */ -#define NVIC_IPR4_PRI_17_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */ -#define NVIC_IPR4_PRI_18_OFS (16) /*!< PRI_18 Offset */ -#define NVIC_IPR4_PRI_18_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */ -#define NVIC_IPR4_PRI_19_OFS (24) /*!< PRI_19 Offset */ -#define NVIC_IPR4_PRI_19_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */ -#define NVIC_IPR5_PRI_20_OFS ( 0) /*!< PRI_20 Offset */ -#define NVIC_IPR5_PRI_20_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */ -#define NVIC_IPR5_PRI_21_OFS ( 8) /*!< PRI_21 Offset */ -#define NVIC_IPR5_PRI_21_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */ -#define NVIC_IPR5_PRI_22_OFS (16) /*!< PRI_22 Offset */ -#define NVIC_IPR5_PRI_22_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */ -#define NVIC_IPR5_PRI_23_OFS (24) /*!< PRI_23 Offset */ -#define NVIC_IPR5_PRI_23_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */ -#define NVIC_IPR6_PRI_24_OFS ( 0) /*!< PRI_24 Offset */ -#define NVIC_IPR6_PRI_24_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */ -#define NVIC_IPR6_PRI_25_OFS ( 8) /*!< PRI_25 Offset */ -#define NVIC_IPR6_PRI_25_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */ -#define NVIC_IPR6_PRI_26_OFS (16) /*!< PRI_26 Offset */ -#define NVIC_IPR6_PRI_26_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */ -#define NVIC_IPR6_PRI_27_OFS (24) /*!< PRI_27 Offset */ -#define NVIC_IPR6_PRI_27_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */ -#define NVIC_IPR7_PRI_28_OFS ( 0) /*!< PRI_28 Offset */ -#define NVIC_IPR7_PRI_28_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */ -#define NVIC_IPR7_PRI_29_OFS ( 8) /*!< PRI_29 Offset */ -#define NVIC_IPR7_PRI_29_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */ -#define NVIC_IPR7_PRI_30_OFS (16) /*!< PRI_30 Offset */ -#define NVIC_IPR7_PRI_30_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */ -#define NVIC_IPR7_PRI_31_OFS (24) /*!< PRI_31 Offset */ -#define NVIC_IPR7_PRI_31_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */ -#define NVIC_IPR8_PRI_32_OFS ( 0) /*!< PRI_32 Offset */ -#define NVIC_IPR8_PRI_32_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */ -#define NVIC_IPR8_PRI_33_OFS ( 8) /*!< PRI_33 Offset */ -#define NVIC_IPR8_PRI_33_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */ -#define NVIC_IPR8_PRI_34_OFS (16) /*!< PRI_34 Offset */ -#define NVIC_IPR8_PRI_34_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */ -#define NVIC_IPR8_PRI_35_OFS (24) /*!< PRI_35 Offset */ -#define NVIC_IPR8_PRI_35_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */ -#define NVIC_IPR9_PRI_36_OFS ( 0) /*!< PRI_36 Offset */ -#define NVIC_IPR9_PRI_36_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */ -#define NVIC_IPR9_PRI_37_OFS ( 8) /*!< PRI_37 Offset */ -#define NVIC_IPR9_PRI_37_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */ -#define NVIC_IPR9_PRI_38_OFS (16) /*!< PRI_38 Offset */ -#define NVIC_IPR9_PRI_38_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */ -#define NVIC_IPR9_PRI_39_OFS (24) /*!< PRI_39 Offset */ -#define NVIC_IPR9_PRI_39_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */ -#define NVIC_IPR10_PRI_40_OFS ( 0) /*!< PRI_40 Offset */ -#define NVIC_IPR10_PRI_40_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */ -#define NVIC_IPR10_PRI_41_OFS ( 8) /*!< PRI_41 Offset */ -#define NVIC_IPR10_PRI_41_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */ -#define NVIC_IPR10_PRI_42_OFS (16) /*!< PRI_42 Offset */ -#define NVIC_IPR10_PRI_42_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */ -#define NVIC_IPR10_PRI_43_OFS (24) /*!< PRI_43 Offset */ -#define NVIC_IPR10_PRI_43_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */ -#define NVIC_IPR11_PRI_44_OFS ( 0) /*!< PRI_44 Offset */ -#define NVIC_IPR11_PRI_44_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */ -#define NVIC_IPR11_PRI_45_OFS ( 8) /*!< PRI_45 Offset */ -#define NVIC_IPR11_PRI_45_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */ -#define NVIC_IPR11_PRI_46_OFS (16) /*!< PRI_46 Offset */ -#define NVIC_IPR11_PRI_46_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */ -#define NVIC_IPR11_PRI_47_OFS (24) /*!< PRI_47 Offset */ -#define NVIC_IPR11_PRI_47_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */ -#define NVIC_IPR12_PRI_48_OFS ( 0) /*!< PRI_48 Offset */ -#define NVIC_IPR12_PRI_48_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */ -#define NVIC_IPR12_PRI_49_OFS ( 8) /*!< PRI_49 Offset */ -#define NVIC_IPR12_PRI_49_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */ -#define NVIC_IPR12_PRI_50_OFS (16) /*!< PRI_50 Offset */ -#define NVIC_IPR12_PRI_50_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */ -#define NVIC_IPR12_PRI_51_OFS (24) /*!< PRI_51 Offset */ -#define NVIC_IPR12_PRI_51_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */ -#define NVIC_IPR13_PRI_52_OFS ( 0) /*!< PRI_52 Offset */ -#define NVIC_IPR13_PRI_52_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */ -#define NVIC_IPR13_PRI_53_OFS ( 8) /*!< PRI_53 Offset */ -#define NVIC_IPR13_PRI_53_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */ -#define NVIC_IPR13_PRI_54_OFS (16) /*!< PRI_54 Offset */ -#define NVIC_IPR13_PRI_54_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */ -#define NVIC_IPR13_PRI_55_OFS (24) /*!< PRI_55 Offset */ -#define NVIC_IPR13_PRI_55_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */ -#define NVIC_IPR14_PRI_56_OFS ( 0) /*!< PRI_56 Offset */ -#define NVIC_IPR14_PRI_56_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */ -#define NVIC_IPR14_PRI_57_OFS ( 8) /*!< PRI_57 Offset */ -#define NVIC_IPR14_PRI_57_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */ -#define NVIC_IPR14_PRI_58_OFS (16) /*!< PRI_58 Offset */ -#define NVIC_IPR14_PRI_58_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */ -#define NVIC_IPR14_PRI_59_OFS (24) /*!< PRI_59 Offset */ -#define NVIC_IPR14_PRI_59_M ((uint32_t)0xff000000) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */ -#define NVIC_IPR15_PRI_60_OFS ( 0) /*!< PRI_60 Offset */ -#define NVIC_IPR15_PRI_60_M ((uint32_t)0x000000ff) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */ -#define NVIC_IPR15_PRI_61_OFS ( 8) /*!< PRI_61 Offset */ -#define NVIC_IPR15_PRI_61_M ((uint32_t)0x0000ff00) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */ -#define NVIC_IPR15_PRI_62_OFS (16) /*!< PRI_62 Offset */ -#define NVIC_IPR15_PRI_62_M ((uint32_t)0x00ff0000) /* */ -/* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */ -#define NVIC_IPR15_PRI_63_OFS (24) /*!< PRI_63 Offset */ -#define NVIC_IPR15_PRI_63_M ((uint32_t)0xff000000) /* */ - - -/****************************************************************************** -* PCM Bits -******************************************************************************/ -/* PCM_CTL0[AMR] Bits */ -#define PCM_CTL0_AMR_OFS ( 0) /*!< AMR Bit Offset */ -#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /*!< AMR Bit Mask */ -#define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /*!< AMR Bit 0 */ -#define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /*!< AMR Bit 1 */ -#define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /*!< AMR Bit 2 */ -#define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /*!< AMR Bit 3 */ -#define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -/* PCM_CTL0[LPMR] Bits */ -#define PCM_CTL0_LPMR_OFS ( 4) /*!< LPMR Bit Offset */ -#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /*!< LPMR Bit Mask */ -#define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /*!< LPMR Bit 0 */ -#define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /*!< LPMR Bit 1 */ -#define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /*!< LPMR Bit 2 */ -#define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /*!< LPMR Bit 3 */ -#define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ - /* entered. */ -#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -#define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ - /* entered. */ -#define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -/* PCM_CTL0[CPM] Bits */ -#define PCM_CTL0_CPM_OFS ( 8) /*!< CPM Bit Offset */ -#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /*!< CPM Bit Mask */ -#define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /*!< CPM Bit 0 */ -#define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /*!< CPM Bit 1 */ -#define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /*!< CPM Bit 2 */ -#define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /*!< CPM Bit 3 */ -#define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /*!< CPM Bit 4 */ -#define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /*!< CPM Bit 5 */ -#define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /*!< LPM3 */ -#define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /*!< LPM3 */ -/* PCM_CTL0[KEY] Bits */ -#define PCM_CTL0_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -/* PCM_CTL1[LOCKLPM5] Bits */ -#define PCM_CTL1_LOCKLPM5_OFS ( 0) /*!< LOCKLPM5 Bit Offset */ -#define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /*!< Lock LPM5 */ -/* PCM_CTL1[LOCKBKUP] Bits */ -#define PCM_CTL1_LOCKBKUP_OFS ( 1) /*!< LOCKBKUP Bit Offset */ -#define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /*!< Lock Backup */ -/* PCM_CTL1[FORCE_LPM_ENTRY] Bits */ -#define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /*!< FORCE_LPM_ENTRY Bit Offset */ -#define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /*!< Force LPM entry */ -/* PCM_CTL1[PMR_BUSY] Bits */ -#define PCM_CTL1_PMR_BUSY_OFS ( 8) /*!< PMR_BUSY Bit Offset */ -#define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /*!< Power mode request busy flag */ -/* PCM_CTL1[KEY] Bits */ -#define PCM_CTL1_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -/* PCM_IE[LPM_INVALID_TR_IE] Bits */ -#define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /*!< LPM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /*!< LPM invalid transition interrupt enable */ -/* PCM_IE[LPM_INVALID_CLK_IE] Bits */ -#define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /*!< LPM_INVALID_CLK_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /*!< LPM invalid clock interrupt enable */ -/* PCM_IE[AM_INVALID_TR_IE] Bits */ -#define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /*!< AM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /*!< Active mode invalid transition interrupt enable */ -/* PCM_IE[DCDC_ERROR_IE] Bits */ -#define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /*!< DCDC_ERROR_IE Bit Offset */ -#define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /*!< DC-DC error interrupt enable */ -/* PCM_IFG[LPM_INVALID_TR_IFG] Bits */ -#define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /*!< LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< LPM invalid transition flag */ -/* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */ -#define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< LPM invalid clock flag */ -/* PCM_IFG[AM_INVALID_TR_IFG] Bits */ -#define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /*!< AM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Active mode invalid transition flag */ -/* PCM_IFG[DCDC_ERROR_IFG] Bits */ -#define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /*!< DCDC_ERROR_IFG Bit Offset */ -#define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< DC-DC error flag */ -/* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< Clear LPM invalid transition flag */ -/* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< Clear LPM invalid clock flag */ -/* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /*!< CLR_AM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Clear active mode invalid transition flag */ -/* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /*!< CLR_DCDC_ERROR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< Clear DC-DC error flag */ -/* Pre-defined bitfield values */ -#define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ -#define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ - - -/****************************************************************************** -* PMAP Bits -******************************************************************************/ -/* PMAP_CTL[LOCKED] Bits */ -#define PMAP_CTL_LOCKED_OFS ( 0) /*!< PMAPLOCKED Bit Offset */ -#define PMAP_CTL_LOCKED ((uint16_t)0x0001) /*!< Port mapping lock bit */ -/* PMAP_CTL[PRECFG] Bits */ -#define PMAP_CTL_PRECFG_OFS ( 1) /*!< PMAPRECFG Bit Offset */ -#define PMAP_CTL_PRECFG ((uint16_t)0x0002) /*!< Port mapping reconfiguration control bit */ -/* Pre-defined bitfield values */ -#define PMAP_NONE 0 -#define PMAP_UCA0CLK 1 -#define PMAP_UCA0RXD 2 -#define PMAP_UCA0SOMI 2 -#define PMAP_UCA0TXD 3 -#define PMAP_UCA0SIMO 3 -#define PMAP_UCB0CLK 4 -#define PMAP_UCB0SDA 5 -#define PMAP_UCB0SIMO 5 -#define PMAP_UCB0SCL 6 -#define PMAP_UCB0SOMI 6 -#define PMAP_UCA1STE 7 -#define PMAP_UCA1CLK 8 -#define PMAP_UCA1RXD 9 -#define PMAP_UCA1SOMI 9 -#define PMAP_UCA1TXD 10 -#define PMAP_UCA1SIMO 10 -#define PMAP_UCA2STE 11 -#define PMAP_UCA2CLK 12 -#define PMAP_UCA2RXD 13 -#define PMAP_UCA2SOMI 13 -#define PMAP_UCA2TXD 14 -#define PMAP_UCA2SIMO 14 -#define PMAP_UCB2STE 15 -#define PMAP_UCB2CLK 16 -#define PMAP_UCB2SDA 17 -#define PMAP_UCB2SIMO 17 -#define PMAP_UCB2SCL 18 -#define PMAP_UCB2SOMI 18 -#define PMAP_TA0CCR0A 19 -#define PMAP_TA0CCR1A 20 -#define PMAP_TA0CCR2A 21 -#define PMAP_TA0CCR3A 22 -#define PMAP_TA0CCR4A 23 -#define PMAP_TA1CCR1A 24 -#define PMAP_TA1CCR2A 25 -#define PMAP_TA1CCR3A 26 -#define PMAP_TA1CCR4A 27 -#define PMAP_TA0CLK 28 -#define PMAP_CE0OUT 28 -#define PMAP_TA1CLK 29 -#define PMAP_CE1OUT 29 -#define PMAP_DMAE0 30 -#define PMAP_SMCLK 30 -#define PMAP_ANALOG 31 - -#define PMAP_KEYID_VAL ((uint16_t)0x2D52) /*!< Port Mapping Key */ - - -/****************************************************************************** -* PSS Bits -******************************************************************************/ -/* PSS_KEY[KEY] Bits */ -#define PSS_KEY_KEY_OFS ( 0) /*!< PSSKEY Bit Offset */ -#define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< PSSKEY Bit Mask */ -/* PSS_CTL0[SVSMHOFF] Bits */ -#define PSS_CTL0_SVSMHOFF_OFS ( 0) /*!< SVSMHOFF Bit Offset */ -#define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /*!< SVSM high-side off */ -/* PSS_CTL0[SVSMHLP] Bits */ -#define PSS_CTL0_SVSMHLP_OFS ( 1) /*!< SVSMHLP Bit Offset */ -#define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /*!< SVSM high-side low power normal performance mode */ -/* PSS_CTL0[SVSMHS] Bits */ -#define PSS_CTL0_SVSMHS_OFS ( 2) /*!< SVSMHS Bit Offset */ -#define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /*!< Supply supervisor or monitor selection for the high-side */ -/* PSS_CTL0[SVSMHTH] Bits */ -#define PSS_CTL0_SVSMHTH_OFS ( 3) /*!< SVSMHTH Bit Offset */ -#define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /*!< SVSMHTH Bit Mask */ -/* PSS_CTL0[SVMHOE] Bits */ -#define PSS_CTL0_SVMHOE_OFS ( 6) /*!< SVMHOE Bit Offset */ -#define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /*!< SVSM high-side output enable */ -/* PSS_CTL0[SVMHOUTPOLAL] Bits */ -#define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /*!< SVMHOUTPOLAL Bit Offset */ -#define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /*!< SVMHOUT pin polarity active low */ -/* PSS_CTL0[DCDC_FORCE] Bits */ -#define PSS_CTL0_DCDC_FORCE_OFS (10) /*!< DCDC_FORCE Bit Offset */ -#define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /*!< Force DC-DC regulator operation */ -/* PSS_CTL0[VCORETRAN] Bits */ -#define PSS_CTL0_VCORETRAN_OFS (12) /*!< VCORETRAN Bit Offset */ -#define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /*!< VCORETRAN Bit Mask */ -#define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /*!< VCORETRAN Bit 0 */ -#define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /*!< VCORETRAN Bit 1 */ -#define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -/* PSS_IE[SVSMHIE] Bits */ -#define PSS_IE_SVSMHIE_OFS ( 1) /*!< SVSMHIE Bit Offset */ -#define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /*!< High-side SVSM interrupt enable */ -/* PSS_IFG[SVSMHIFG] Bits */ -#define PSS_IFG_SVSMHIFG_OFS ( 1) /*!< SVSMHIFG Bit Offset */ -#define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /*!< High-side SVSM interrupt flag */ -/* PSS_CLRIFG[CLRSVSMHIFG] Bits */ -#define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /*!< CLRSVSMHIFG Bit Offset */ -#define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /*!< SVSMH clear interrupt flag */ -/* Pre-defined bitfield values */ -#define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /*!< PSS control key value */ - - -/****************************************************************************** -* REF_A Bits -******************************************************************************/ -/* REF_A_CTL0[ON] Bits */ -#define REF_A_CTL0_ON_OFS ( 0) /*!< REFON Bit Offset */ -#define REF_A_CTL0_ON ((uint16_t)0x0001) /*!< Reference enable */ -/* REF_A_CTL0[OUT] Bits */ -#define REF_A_CTL0_OUT_OFS ( 1) /*!< REFOUT Bit Offset */ -#define REF_A_CTL0_OUT ((uint16_t)0x0002) /*!< Reference output buffer */ -/* REF_A_CTL0[TCOFF] Bits */ -#define REF_A_CTL0_TCOFF_OFS ( 3) /*!< REFTCOFF Bit Offset */ -#define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /*!< Temperature sensor disabled */ -/* REF_A_CTL0[VSEL] Bits */ -#define REF_A_CTL0_VSEL_OFS ( 4) /*!< REFVSEL Bit Offset */ -#define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /*!< REFVSEL Bit Mask */ -#define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /*!< VSEL Bit 0 */ -#define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /*!< VSEL Bit 1 */ -#define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /*!< 1.2 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /*!< 1.45 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /*!< 2.5 V available when reference requested or REFON = 1 */ -/* REF_A_CTL0[GENOT] Bits */ -#define REF_A_CTL0_GENOT_OFS ( 6) /*!< REFGENOT Bit Offset */ -#define REF_A_CTL0_GENOT ((uint16_t)0x0040) /*!< Reference generator one-time trigger */ -/* REF_A_CTL0[BGOT] Bits */ -#define REF_A_CTL0_BGOT_OFS ( 7) /*!< REFBGOT Bit Offset */ -#define REF_A_CTL0_BGOT ((uint16_t)0x0080) /*!< Bandgap and bandgap buffer one-time trigger */ -/* REF_A_CTL0[GENACT] Bits */ -#define REF_A_CTL0_GENACT_OFS ( 8) /*!< REFGENACT Bit Offset */ -#define REF_A_CTL0_GENACT ((uint16_t)0x0100) /*!< Reference generator active */ -/* REF_A_CTL0[BGACT] Bits */ -#define REF_A_CTL0_BGACT_OFS ( 9) /*!< REFBGACT Bit Offset */ -#define REF_A_CTL0_BGACT ((uint16_t)0x0200) /*!< Reference bandgap active */ -/* REF_A_CTL0[GENBUSY] Bits */ -#define REF_A_CTL0_GENBUSY_OFS (10) /*!< REFGENBUSY Bit Offset */ -#define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /*!< Reference generator busy */ -/* REF_A_CTL0[BGMODE] Bits */ -#define REF_A_CTL0_BGMODE_OFS (11) /*!< BGMODE Bit Offset */ -#define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /*!< Bandgap mode */ -/* REF_A_CTL0[GENRDY] Bits */ -#define REF_A_CTL0_GENRDY_OFS (12) /*!< REFGENRDY Bit Offset */ -#define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /*!< Variable reference voltage ready status */ -/* REF_A_CTL0[BGRDY] Bits */ -#define REF_A_CTL0_BGRDY_OFS (13) /*!< REFBGRDY Bit Offset */ -#define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /*!< Buffered bandgap voltage ready status */ - -/****************************************************************************** -* RSTCTL Bits -******************************************************************************/ -/* RSTCTL_RESET_REQ[SOFT_REQ] Bits */ -#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /*!< SOFT_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /*!< Soft Reset request */ -/* RSTCTL_RESET_REQ[HARD_REQ] Bits */ -#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /*!< HARD_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /*!< Hard Reset request */ -/* RSTCTL_RESET_REQ[RSTKEY] Bits */ -#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /*!< RSTKEY Bit Offset */ -#define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /*!< RSTKEY Bit Mask */ -/* RSTCTL_HARDRESET_STAT[SRC0] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< Indicates that SRC0 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC1] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< Indicates that SRC1 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC2] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< Indicates that SRC2 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC3] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< Indicates that SRC3 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC4] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< Indicates that SRC4 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC5] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< Indicates that SRC5 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC6] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< Indicates that SRC6 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC7] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< Indicates that SRC7 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC8] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< Indicates that SRC8 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC9] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< Indicates that SRC9 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC10] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< Indicates that SRC10 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC11] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< Indicates that SRC11 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC12] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< Indicates that SRC12 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC13] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< Indicates that SRC13 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC14] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< Indicates that SRC14 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_STAT[SRC15] Bits */ -#define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< Indicates that SRC15 was the source of the Hard Reset */ -/* RSTCTL_HARDRESET_CLR[SRC0] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC1] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC2] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC3] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC4] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC5] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC6] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC7] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC8] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC9] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC10] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC11] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC12] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC13] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC14] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -/* RSTCTL_HARDRESET_CLR[SRC15] Bits */ -#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */ -/* RSTCTL_HARDRESET_SET[SRC0] Bits */ -#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC1] Bits */ -#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC2] Bits */ -#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC3] Bits */ -#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC4] Bits */ -#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC5] Bits */ -#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC6] Bits */ -#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC7] Bits */ -#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC8] Bits */ -#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC9] Bits */ -#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC10] Bits */ -#define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC11] Bits */ -#define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC12] Bits */ -#define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC13] Bits */ -#define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC14] Bits */ -#define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_HARDRESET_SET[SRC15] Bits */ -#define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ - /* initiates a Hard Reset) */ -/* RSTCTL_SOFTRESET_STAT[SRC0] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< If 1, indicates that SRC0 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC1] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< If 1, indicates that SRC1 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC2] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< If 1, indicates that SRC2 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC3] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< If 1, indicates that SRC3 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC4] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< If 1, indicates that SRC4 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC5] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< If 1, indicates that SRC5 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC6] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< If 1, indicates that SRC6 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC7] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< If 1, indicates that SRC7 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC8] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< If 1, indicates that SRC8 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC9] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< If 1, indicates that SRC9 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC10] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< If 1, indicates that SRC10 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC11] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< If 1, indicates that SRC11 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC12] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< If 1, indicates that SRC12 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC13] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< If 1, indicates that SRC13 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC14] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< If 1, indicates that SRC14 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_STAT[SRC15] Bits */ -#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< If 1, indicates that SRC15 was the source of the Soft Reset */ -/* RSTCTL_SOFTRESET_CLR[SRC0] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC1] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC2] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC3] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC4] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC5] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC6] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC7] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC8] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC9] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC10] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC11] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC12] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC13] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC14] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_CLR[SRC15] Bits */ -#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -/* RSTCTL_SOFTRESET_SET[SRC0] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC1] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC2] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC3] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC4] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC5] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC6] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC7] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC8] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC9] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC10] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC11] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC12] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC13] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC14] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_SOFTRESET_SET[SRC15] Bits */ -#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ - /* initiates a Soft Reset) */ -/* RSTCTL_PSSRESET_STAT[SVSMH] Bits */ -#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /*!< SVSMH Bit Offset */ -#define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */ -/* RSTCTL_PSSRESET_STAT[BGREF] Bits */ -#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /*!< BGREF Bit Offset */ -#define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */ -/* RSTCTL_PSSRESET_STAT[VCCDET] Bits */ -#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /*!< VCCDET Bit Offset */ -#define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */ -/* RSTCTL_PSSRESET_CLR[CLR] Bits */ -#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */ -/* RSTCTL_PCMRESET_STAT[LPM35] Bits */ -#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /*!< LPM35 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */ -/* RSTCTL_PCMRESET_STAT[LPM45] Bits */ -#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /*!< LPM45 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */ -/* RSTCTL_PCMRESET_CLR[CLR] Bits */ -#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */ -/* RSTCTL_PINRESET_STAT[RSTNMI] Bits */ -#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /*!< RSTNMI Bit Offset */ -#define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /*!< POR was caused by RSTn/NMI pin based reset event */ -/* RSTCTL_PINRESET_CLR[CLR] Bits */ -#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */ -/* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /*!< Indicates if Reboot reset was caused by the SYSCTL module. */ -/* RSTCTL_REBOOTRESET_CLR[CLR] Bits */ -#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */ -/* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /*!< DCOR_SHT Bit Offset */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /*!< Indicates if POR was caused by DCO short circuit fault in the external */ - /* resistor mode */ -/* RSTCTL_CSRESET_CLR[CLR] Bits */ -#define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as */ - /* DCOR_SHTIFG flag in CSIFG register of clock system */ -/* Pre-defined bitfield values */ -#define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bits 1-0 */ - - -/****************************************************************************** -* RTC_C Bits -******************************************************************************/ -/* RTC_C_CTL0[RDYIFG] Bits */ -#define RTC_C_CTL0_RDYIFG_OFS ( 0) /*!< RTCRDYIFG Bit Offset */ -#define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /*!< Real-time clock ready interrupt flag */ -/* RTC_C_CTL0[AIFG] Bits */ -#define RTC_C_CTL0_AIFG_OFS ( 1) /*!< RTCAIFG Bit Offset */ -#define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /*!< Real-time clock alarm interrupt flag */ -/* RTC_C_CTL0[TEVIFG] Bits */ -#define RTC_C_CTL0_TEVIFG_OFS ( 2) /*!< RTCTEVIFG Bit Offset */ -#define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /*!< Real-time clock time event interrupt flag */ -/* RTC_C_CTL0[OFIFG] Bits */ -#define RTC_C_CTL0_OFIFG_OFS ( 3) /*!< RTCOFIFG Bit Offset */ -#define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /*!< 32-kHz crystal oscillator fault interrupt flag */ -/* RTC_C_CTL0[RDYIE] Bits */ -#define RTC_C_CTL0_RDYIE_OFS ( 4) /*!< RTCRDYIE Bit Offset */ -#define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /*!< Real-time clock ready interrupt enable */ -/* RTC_C_CTL0[AIE] Bits */ -#define RTC_C_CTL0_AIE_OFS ( 5) /*!< RTCAIE Bit Offset */ -#define RTC_C_CTL0_AIE ((uint16_t)0x0020) /*!< Real-time clock alarm interrupt enable */ -/* RTC_C_CTL0[TEVIE] Bits */ -#define RTC_C_CTL0_TEVIE_OFS ( 6) /*!< RTCTEVIE Bit Offset */ -#define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /*!< Real-time clock time event interrupt enable */ -/* RTC_C_CTL0[OFIE] Bits */ -#define RTC_C_CTL0_OFIE_OFS ( 7) /*!< RTCOFIE Bit Offset */ -#define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /*!< 32-kHz crystal oscillator fault interrupt enable */ -/* RTC_C_CTL0[KEY] Bits */ -#define RTC_C_CTL0_KEY_OFS ( 8) /*!< RTCKEY Bit Offset */ -#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /*!< RTCKEY Bit Mask */ -/* RTC_C_CTL13[TEV] Bits */ -#define RTC_C_CTL13_TEV_OFS ( 0) /*!< RTCTEV Bit Offset */ -#define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /*!< RTCTEV Bit Mask */ -#define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /*!< TEV Bit 0 */ -#define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /*!< TEV Bit 1 */ -#define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /*!< Minute changed */ -#define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /*!< Hour changed */ -#define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /*!< Every day at midnight (00:00) */ -#define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /*!< Every day at noon (12:00) */ -/* RTC_C_CTL13[SSEL] Bits */ -#define RTC_C_CTL13_SSEL_OFS ( 2) /*!< RTCSSEL Bit Offset */ -#define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /*!< RTCSSEL Bit Mask */ -#define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /*!< SSEL Bit 0 */ -#define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /*!< SSEL Bit 1 */ -#define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /*!< BCLK */ -#define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /*!< BCLK */ -/* RTC_C_CTL13[RDY] Bits */ -#define RTC_C_CTL13_RDY_OFS ( 4) /*!< RTCRDY Bit Offset */ -#define RTC_C_CTL13_RDY ((uint16_t)0x0010) /*!< Real-time clock ready */ -/* RTC_C_CTL13[MODE] Bits */ -#define RTC_C_CTL13_MODE_OFS ( 5) /*!< RTCMODE Bit Offset */ -#define RTC_C_CTL13_MODE ((uint16_t)0x0020) -/* RTC_C_CTL13[HOLD] Bits */ -#define RTC_C_CTL13_HOLD_OFS ( 6) /*!< RTCHOLD Bit Offset */ -#define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /*!< Real-time clock hold */ -/* RTC_C_CTL13[BCD] Bits */ -#define RTC_C_CTL13_BCD_OFS ( 7) /*!< RTCBCD Bit Offset */ -#define RTC_C_CTL13_BCD ((uint16_t)0x0080) /*!< Real-time clock BCD select */ -/* RTC_C_CTL13[CALF] Bits */ -#define RTC_C_CTL13_CALF_OFS ( 8) /*!< RTCCALF Bit Offset */ -#define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /*!< RTCCALF Bit Mask */ -#define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /*!< CALF Bit 0 */ -#define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /*!< CALF Bit 1 */ -#define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /*!< 1 Hz */ -#define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /*!< 1 Hz */ -/* RTC_C_OCAL[OCAL] Bits */ -#define RTC_C_OCAL_OCAL_OFS ( 0) /*!< RTCOCAL Bit Offset */ -#define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /*!< RTCOCAL Bit Mask */ -/* RTC_C_OCAL[OCALS] Bits */ -#define RTC_C_OCAL_OCALS_OFS (15) /*!< RTCOCALS Bit Offset */ -#define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /*!< Real-time clock offset error calibration sign */ -/* RTC_C_TCMP[TCMPx] Bits */ -#define RTC_C_TCMP_TCMPX_OFS ( 0) /*!< RTCTCMP Bit Offset */ -#define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /*!< RTCTCMP Bit Mask */ -/* RTC_C_TCMP[TCOK] Bits */ -#define RTC_C_TCMP_TCOK_OFS (13) /*!< RTCTCOK Bit Offset */ -#define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /*!< Real-time clock temperature compensation write OK */ -/* RTC_C_TCMP[TCRDY] Bits */ -#define RTC_C_TCMP_TCRDY_OFS (14) /*!< RTCTCRDY Bit Offset */ -#define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /*!< Real-time clock temperature compensation ready */ -/* RTC_C_TCMP[TCMPS] Bits */ -#define RTC_C_TCMP_TCMPS_OFS (15) /*!< RTCTCMPS Bit Offset */ -#define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /*!< Real-time clock temperature compensation sign */ -/* RTC_C_PS0CTL[RT0PSIFG] Bits */ -#define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /*!< RT0PSIFG Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /*!< Prescale timer 0 interrupt flag */ -/* RTC_C_PS0CTL[RT0PSIE] Bits */ -#define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /*!< RT0PSIE Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /*!< Prescale timer 0 interrupt enable */ -/* RTC_C_PS0CTL[RT0IP] Bits */ -#define RTC_C_PS0CTL_RT0IP_OFS ( 2) /*!< RT0IP Bit Offset */ -#define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /*!< RT0IP Bit Mask */ -#define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /*!< RT0IP Bit 0 */ -#define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /*!< RT0IP Bit 1 */ -#define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /*!< RT0IP Bit 2 */ -#define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -/* RTC_C_PS1CTL[RT1PSIFG] Bits */ -#define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /*!< RT1PSIFG Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /*!< Prescale timer 1 interrupt flag */ -/* RTC_C_PS1CTL[RT1PSIE] Bits */ -#define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /*!< RT1PSIE Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /*!< Prescale timer 1 interrupt enable */ -/* RTC_C_PS1CTL[RT1IP] Bits */ -#define RTC_C_PS1CTL_RT1IP_OFS ( 2) /*!< RT1IP Bit Offset */ -#define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /*!< RT1IP Bit Mask */ -#define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /*!< RT1IP Bit 0 */ -#define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /*!< RT1IP Bit 1 */ -#define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /*!< RT1IP Bit 2 */ -#define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -/* RTC_C_PS[RT0PS] Bits */ -#define RTC_C_PS_RT0PS_OFS ( 0) /*!< RT0PS Bit Offset */ -#define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /*!< RT0PS Bit Mask */ -/* RTC_C_PS[RT1PS] Bits */ -#define RTC_C_PS_RT1PS_OFS ( 8) /*!< RT1PS Bit Offset */ -#define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /*!< RT1PS Bit Mask */ -/* RTC_C_TIM0[SEC] Bits */ -#define RTC_C_TIM0_SEC_OFS ( 0) /*!< Seconds Bit Offset */ -#define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /*!< Seconds Bit Mask */ -/* RTC_C_TIM0[MIN] Bits */ -#define RTC_C_TIM0_MIN_OFS ( 8) /*!< Minutes Bit Offset */ -#define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /*!< Minutes Bit Mask */ -/* RTC_C_TIM0[SEC_LD] Bits */ -#define RTC_C_TIM0_SEC_LD_OFS ( 0) /*!< SecondsLowDigit Bit Offset */ -#define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /*!< SecondsLowDigit Bit Mask */ -/* RTC_C_TIM0[SEC_HD] Bits */ -#define RTC_C_TIM0_SEC_HD_OFS ( 4) /*!< SecondsHighDigit Bit Offset */ -#define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /*!< SecondsHighDigit Bit Mask */ -/* RTC_C_TIM0[MIN_LD] Bits */ -#define RTC_C_TIM0_MIN_LD_OFS ( 8) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /*!< MinutesLowDigit Bit Mask */ -/* RTC_C_TIM0[MIN_HD] Bits */ -#define RTC_C_TIM0_MIN_HD_OFS (12) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /*!< MinutesHighDigit Bit Mask */ -/* RTC_C_TIM1[HOUR] Bits */ -#define RTC_C_TIM1_HOUR_OFS ( 0) /*!< Hours Bit Offset */ -#define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /*!< Hours Bit Mask */ -/* RTC_C_TIM1[DOW] Bits */ -#define RTC_C_TIM1_DOW_OFS ( 8) /*!< DayofWeek Bit Offset */ -#define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /*!< DayofWeek Bit Mask */ -/* RTC_C_TIM1[HOUR_LD] Bits */ -#define RTC_C_TIM1_HOUR_LD_OFS ( 0) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /*!< HoursLowDigit Bit Mask */ -/* RTC_C_TIM1[HOUR_HD] Bits */ -#define RTC_C_TIM1_HOUR_HD_OFS ( 4) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /*!< HoursHighDigit Bit Mask */ -/* RTC_C_DATE[DAY] Bits */ -#define RTC_C_DATE_DAY_OFS ( 0) /*!< Day Bit Offset */ -#define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /*!< Day Bit Mask */ -/* RTC_C_DATE[MON] Bits */ -#define RTC_C_DATE_MON_OFS ( 8) /*!< Month Bit Offset */ -#define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /*!< Month Bit Mask */ -/* RTC_C_DATE[DAY_LD] Bits */ -#define RTC_C_DATE_DAY_LD_OFS ( 0) /*!< DayLowDigit Bit Offset */ -#define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /*!< DayLowDigit Bit Mask */ -/* RTC_C_DATE[DAY_HD] Bits */ -#define RTC_C_DATE_DAY_HD_OFS ( 4) /*!< DayHighDigit Bit Offset */ -#define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /*!< DayHighDigit Bit Mask */ -/* RTC_C_DATE[MON_LD] Bits */ -#define RTC_C_DATE_MON_LD_OFS ( 8) /*!< MonthLowDigit Bit Offset */ -#define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /*!< MonthLowDigit Bit Mask */ -/* RTC_C_DATE[MON_HD] Bits */ -#define RTC_C_DATE_MON_HD_OFS (12) /*!< MonthHighDigit Bit Offset */ -#define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /*!< Month high digit (0 or 1) */ -/* RTC_C_YEAR[YEAR_LB] Bits */ -#define RTC_C_YEAR_YEAR_LB_OFS ( 0) /*!< YearLowByte Bit Offset */ -#define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /*!< YearLowByte Bit Mask */ -/* RTC_C_YEAR[YEAR_HB] Bits */ -#define RTC_C_YEAR_YEAR_HB_OFS ( 8) /*!< YearHighByte Bit Offset */ -#define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /*!< YearHighByte Bit Mask */ -/* RTC_C_YEAR[YEAR] Bits */ -#define RTC_C_YEAR_YEAR_OFS ( 0) /*!< Year Bit Offset */ -#define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /*!< Year Bit Mask */ -/* RTC_C_YEAR[DEC] Bits */ -#define RTC_C_YEAR_DEC_OFS ( 4) /*!< Decade Bit Offset */ -#define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /*!< Decade Bit Mask */ -/* RTC_C_YEAR[CENT_LD] Bits */ -#define RTC_C_YEAR_CENT_LD_OFS ( 8) /*!< CenturyLowDigit Bit Offset */ -#define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /*!< CenturyLowDigit Bit Mask */ -/* RTC_C_YEAR[CENT_HD] Bits */ -#define RTC_C_YEAR_CENT_HD_OFS (12) /*!< CenturyHighDigit Bit Offset */ -#define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /*!< CenturyHighDigit Bit Mask */ -/* RTC_C_AMINHR[MIN] Bits */ -#define RTC_C_AMINHR_MIN_OFS ( 0) /*!< Minutes Bit Offset */ -#define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /*!< Minutes Bit Mask */ -/* RTC_C_AMINHR[MINAE] Bits */ -#define RTC_C_AMINHR_MINAE_OFS ( 7) /*!< MINAE Bit Offset */ -#define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /*!< Alarm enable */ -/* RTC_C_AMINHR[HOUR] Bits */ -#define RTC_C_AMINHR_HOUR_OFS ( 8) /*!< Hours Bit Offset */ -#define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /*!< Hours Bit Mask */ -/* RTC_C_AMINHR[HOURAE] Bits */ -#define RTC_C_AMINHR_HOURAE_OFS (15) /*!< HOURAE Bit Offset */ -#define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /*!< Alarm enable */ -/* RTC_C_AMINHR[MIN_LD] Bits */ -#define RTC_C_AMINHR_MIN_LD_OFS ( 0) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /*!< MinutesLowDigit Bit Mask */ -/* RTC_C_AMINHR[MIN_HD] Bits */ -#define RTC_C_AMINHR_MIN_HD_OFS ( 4) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /*!< MinutesHighDigit Bit Mask */ -/* RTC_C_AMINHR[HOUR_LD] Bits */ -#define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /*!< HoursLowDigit Bit Mask */ -/* RTC_C_AMINHR[HOUR_HD] Bits */ -#define RTC_C_AMINHR_HOUR_HD_OFS (12) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /*!< HoursHighDigit Bit Mask */ -/* RTC_C_ADOWDAY[DOW] Bits */ -#define RTC_C_ADOWDAY_DOW_OFS ( 0) /*!< DayofWeek Bit Offset */ -#define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /*!< DayofWeek Bit Mask */ -/* RTC_C_ADOWDAY[DOWAE] Bits */ -#define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /*!< DOWAE Bit Offset */ -#define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /*!< Alarm enable */ -/* RTC_C_ADOWDAY[DAY] Bits */ -#define RTC_C_ADOWDAY_DAY_OFS ( 8) /*!< DayofMonth Bit Offset */ -#define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /*!< DayofMonth Bit Mask */ -/* RTC_C_ADOWDAY[DAYAE] Bits */ -#define RTC_C_ADOWDAY_DAYAE_OFS (15) /*!< DAYAE Bit Offset */ -#define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /*!< Alarm enable */ -/* RTC_C_ADOWDAY[DAY_LD] Bits */ -#define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /*!< DayLowDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /*!< DayLowDigit Bit Mask */ -/* RTC_C_ADOWDAY[DAY_HD] Bits */ -#define RTC_C_ADOWDAY_DAY_HD_OFS (12) /*!< DayHighDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /*!< DayHighDigit Bit Mask */ -/* Pre-defined bitfield values */ -#define RTC_C_KEY ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_H ((uint16_t)0x00A5) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_VAL ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ - - -/****************************************************************************** -* SCB Bits -******************************************************************************/ -/* SCB_PFR0[STATE0] Bits */ -#define SCB_PFR0_STATE0_OFS ( 0) /*!< STATE0 Bit Offset */ -#define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /*!< STATE0 Bit Mask */ -#define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /*!< STATE0 Bit 0 */ -#define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /*!< STATE0 Bit 1 */ -#define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /*!< STATE0 Bit 2 */ -#define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /*!< STATE0 Bit 3 */ -#define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /*!< no ARM encoding */ -#define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /*!< N/A */ -/* SCB_PFR0[STATE1] Bits */ -#define SCB_PFR0_STATE1_OFS ( 4) /*!< STATE1 Bit Offset */ -#define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /*!< STATE1 Bit Mask */ -#define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /*!< STATE1 Bit 0 */ -#define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /*!< STATE1 Bit 1 */ -#define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /*!< STATE1 Bit 2 */ -#define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /*!< STATE1 Bit 3 */ -#define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /*!< N/A */ -#define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /*!< N/A */ -#define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL */ - /* but no other 32-bit basic instructions (Note non-basic 32-bit instructions */ - /* can be added using the appropriate instruction attribute, but other 32-bit */ - /* basic instructions cannot.) */ -#define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /*!< Thumb-2 encoding with all Thumb-2 basic instructions */ -/* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /*!< two-stack support */ -/* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */ -/* SCB_MMFR0[PMSA_SUPPORT] Bits */ -#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /*!< PMSA_SUPPORT Bit Offset */ -#define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /*!< PMSA_SUPPORT Bit Mask */ -#define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /*!< PMSA_SUPPORT Bit 0 */ -#define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /*!< PMSA_SUPPORT Bit 1 */ -#define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /*!< PMSA_SUPPORT Bit 2 */ -#define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /*!< PMSA_SUPPORT Bit 3 */ -#define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /*!< IMPLEMENTATION DEFINED (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /*!< PMSA base (features as defined for ARMv6) (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /*!< PMSAv7 (base plus subregion support) */ -/* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /*!< CACHE_COHERENCE_SUPPORT Bit Offset */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /*!< CACHE_COHERENCE_SUPPORT Bit Mask */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /*!< CACHE_COHERENCE_SUPPORT Bit 0 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /*!< CACHE_COHERENCE_SUPPORT Bit 1 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /*!< CACHE_COHERENCE_SUPPORT Bit 2 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /*!< CACHE_COHERENCE_SUPPORT Bit 3 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /*!< no shared support */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /*!< partial-inner-shared coherency (coherency amongst some - but not all - of */ - /* the entities within an inner-coherent domain) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /*!< full-inner-shared coherency (coherency amongst all of the entities within an */ - /* inner-coherent domain) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /*!< full coherency (coherency amongst all of the entities) */ -/* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /*!< Outer non-sharable not supported */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /*!< Outer sharable supported */ -/* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /*!< Auxiliary control register */ -/* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /*!< wait for interrupt supported */ -/* SCB_ISAR0[BITCOUNT_INSTRS] Bits */ -#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /*!< BITCOUNT_INSTRS Bit Offset */ -#define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< BITCOUNT_INSTRS Bit Mask */ -#define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /*!< BITCOUNT_INSTRS Bit 0 */ -#define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /*!< BITCOUNT_INSTRS Bit 1 */ -#define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /*!< BITCOUNT_INSTRS Bit 2 */ -#define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /*!< BITCOUNT_INSTRS Bit 3 */ -#define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /*!< no bit-counting instructions present */ -#define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds CLZ */ -/* SCB_ISAR0[BITFIELD_INSTRS] Bits */ -#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /*!< BITFIELD_INSTRS Bit Offset */ -#define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /*!< BITFIELD_INSTRS Bit Mask */ -#define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /*!< BITFIELD_INSTRS Bit 0 */ -#define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /*!< BITFIELD_INSTRS Bit 1 */ -#define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /*!< BITFIELD_INSTRS Bit 2 */ -#define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /*!< BITFIELD_INSTRS Bit 3 */ -#define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /*!< no bitfield instructions present */ -#define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /*!< adds BFC, BFI, SBFX, UBFX */ -/* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /*!< CMPBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /*!< CMPBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /*!< CMPBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /*!< CMPBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /*!< CMPBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /*!< CMPBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no combined compare-and-branch instructions present */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /*!< adds CB{N}Z */ -/* SCB_ISAR0[COPROC_INSTRS] Bits */ -#define SCB_ISAR0_COPROC_INSTRS_OFS (16) /*!< COPROC_INSTRS Bit Offset */ -#define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /*!< COPROC_INSTRS Bit Mask */ -#define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /*!< COPROC_INSTRS Bit 0 */ -#define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /*!< COPROC_INSTRS Bit 1 */ -#define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /*!< COPROC_INSTRS Bit 2 */ -#define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /*!< COPROC_INSTRS Bit 3 */ -#define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /*!< no coprocessor support, other than for separately attributed architectures */ - /* such as CP15 or VFP */ -#define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /*!< adds generic CDP, LDC, MCR, MRC, STC */ -#define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */ -#define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /*!< adds generic MCRR, MRRC */ -#define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /*!< adds generic MCRR2, MRRC2 */ -/* SCB_ISAR0[DEBUG_INSTRS] Bits */ -#define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /*!< DEBUG_INSTRS Bit Offset */ -#define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /*!< DEBUG_INSTRS Bit Mask */ -#define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /*!< DEBUG_INSTRS Bit 0 */ -#define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /*!< DEBUG_INSTRS Bit 1 */ -#define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /*!< DEBUG_INSTRS Bit 2 */ -#define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /*!< DEBUG_INSTRS Bit 3 */ -#define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /*!< no debug instructions present */ -#define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /*!< adds BKPT */ -/* SCB_ISAR0[DIVIDE_INSTRS] Bits */ -#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /*!< DIVIDE_INSTRS Bit Offset */ -#define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /*!< DIVIDE_INSTRS Bit Mask */ -#define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /*!< DIVIDE_INSTRS Bit 0 */ -#define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /*!< DIVIDE_INSTRS Bit 1 */ -#define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /*!< DIVIDE_INSTRS Bit 2 */ -#define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /*!< DIVIDE_INSTRS Bit 3 */ -#define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /*!< no divide instructions present */ -#define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /*!< adds SDIV, UDIV (v1 quotient only result) */ -/* SCB_ISAR1[ETEND_INSRS] Bits */ -#define SCB_ISAR1_ETEND_INSRS_OFS (12) /*!< EXTEND_INSRS Bit Offset */ -#define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /*!< EXTEND_INSRS Bit Mask */ -#define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /*!< ETEND_INSRS Bit 0 */ -#define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /*!< ETEND_INSRS Bit 1 */ -#define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /*!< ETEND_INSRS Bit 2 */ -#define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /*!< ETEND_INSRS Bit 3 */ -#define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */ -#define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /*!< adds SXTB, SXTH, UXTB, UXTH */ -#define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /*!< N/A */ -/* SCB_ISAR1[IFTHEN_INSTRS] Bits */ -#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /*!< IFTHEN_INSTRS Bit Offset */ -#define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /*!< IFTHEN_INSTRS Bit Mask */ -#define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /*!< IFTHEN_INSTRS Bit 0 */ -#define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /*!< IFTHEN_INSTRS Bit 1 */ -#define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /*!< IFTHEN_INSTRS Bit 2 */ -#define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /*!< IFTHEN_INSTRS Bit 3 */ -#define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /*!< IT instructions not present */ -#define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /*!< adds IT instructions (and IT bits in PSRs) */ -/* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /*!< IMMEDIATE_INSTRS Bit Offset */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /*!< IMMEDIATE_INSTRS Bit Mask */ -#define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /*!< IMMEDIATE_INSTRS Bit 0 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /*!< IMMEDIATE_INSTRS Bit 1 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /*!< IMMEDIATE_INSTRS Bit 2 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /*!< IMMEDIATE_INSTRS Bit 3 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no special immediate-generating instructions present */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /*!< adds ADDW, MOVW, MOVT, SUBW */ -/* SCB_ISAR1[INTERWORK_INSTRS] Bits */ -#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /*!< INTERWORK_INSTRS Bit Offset */ -#define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /*!< INTERWORK_INSTRS Bit Mask */ -#define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /*!< INTERWORK_INSTRS Bit 0 */ -#define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /*!< INTERWORK_INSTRS Bit 1 */ -#define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /*!< INTERWORK_INSTRS Bit 2 */ -#define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /*!< INTERWORK_INSTRS Bit 3 */ -#define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /*!< no interworking instructions supported */ -#define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /*!< adds BX (and T bit in PSRs) */ -#define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /*!< adds BLX, and PC loads have BX-like behavior */ -#define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /*!< N/A */ -/* SCB_ISAR2[LOADSTORE_INSTRS] Bits */ -#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /*!< LOADSTORE_INSTRS Bit Offset */ -#define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< LOADSTORE_INSTRS Bit Mask */ -#define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /*!< LOADSTORE_INSTRS Bit 0 */ -#define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /*!< LOADSTORE_INSTRS Bit 1 */ -#define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /*!< LOADSTORE_INSTRS Bit 2 */ -#define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /*!< LOADSTORE_INSTRS Bit 3 */ -#define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /*!< no additional normal load/store instructions present */ -#define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRD/STRD */ -/* SCB_ISAR2[MEMHINT_INSTRS] Bits */ -#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /*!< MEMHINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< MEMHINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /*!< MEMHINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /*!< MEMHINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /*!< MEMHINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /*!< MEMHINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /*!< no memory hint instructions presen */ -#define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds PLD */ -#define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /*!< adds PLD (ie a repeat on value 1) */ -#define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /*!< adds PLI */ -/* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /*!< MULTIACCESSINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /*!< MULTIACCESSINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /*!< MULTIACCESSINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /*!< MULTIACCESSINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /*!< MULTIACCESSINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /*!< MULTIACCESSINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /*!< the (LDM/STM) instructions are non-interruptible */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /*!< the (LDM/STM) instructions are restartable */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /*!< the (LDM/STM) instructions are continuable */ -/* SCB_ISAR2[MULT_INSTRS] Bits */ -#define SCB_ISAR2_MULT_INSTRS_OFS (12) /*!< MULT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /*!< MULT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /*!< MULT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /*!< MULT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /*!< MULT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /*!< MULT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /*!< only MUL present */ -#define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /*!< adds MLA */ -#define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /*!< adds MLS */ -/* SCB_ISAR2[MULTS_INSTRS] Bits */ -#define SCB_ISAR2_MULTS_INSTRS_OFS (16) /*!< MULTS_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /*!< MULTS_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /*!< MULTS_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /*!< MULTS_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /*!< MULTS_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /*!< MULTS_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /*!< no signed multiply instructions present */ -#define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /*!< adds SMULL, SMLAL */ -#define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /*!< N/A */ -#define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /*!< N/A */ -/* SCB_ISAR2[MULTU_INSTRS] Bits */ -#define SCB_ISAR2_MULTU_INSTRS_OFS (20) /*!< MULTU_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /*!< MULTU_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /*!< MULTU_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /*!< MULTU_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /*!< MULTU_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /*!< MULTU_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /*!< no unsigned multiply instructions present */ -#define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /*!< adds UMULL, UMLAL */ -#define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /*!< N/A */ -/* SCB_ISAR2[REVERSAL_INSTRS] Bits */ -#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /*!< REVERSAL_INSTRS Bit Offset */ -#define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /*!< REVERSAL_INSTRS Bit Mask */ -#define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /*!< REVERSAL_INSTRS Bit 0 */ -#define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /*!< REVERSAL_INSTRS Bit 1 */ -#define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /*!< REVERSAL_INSTRS Bit 2 */ -#define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /*!< REVERSAL_INSTRS Bit 3 */ -#define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /*!< no reversal instructions present */ -#define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /*!< adds REV, REV16, REVSH */ -#define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /*!< adds RBIT */ -/* SCB_ISAR3[SATRUATE_INSTRS] Bits */ -#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /*!< SATRUATE_INSTRS Bit Offset */ -#define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< SATRUATE_INSTRS Bit Mask */ -#define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /*!< SATRUATE_INSTRS Bit 0 */ -#define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /*!< SATRUATE_INSTRS Bit 1 */ -#define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /*!< SATRUATE_INSTRS Bit 2 */ -#define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /*!< SATRUATE_INSTRS Bit 3 */ -#define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no non-SIMD saturate instructions present */ -#define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /*!< N/A */ -/* SCB_ISAR3[SIMD_INSTRS] Bits */ -#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /*!< SIMD_INSTRS Bit Offset */ -#define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /*!< SIMD_INSTRS Bit Mask */ -#define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /*!< SIMD_INSTRS Bit 0 */ -#define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /*!< SIMD_INSTRS Bit 1 */ -#define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /*!< SIMD_INSTRS Bit 2 */ -#define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /*!< SIMD_INSTRS Bit 3 */ -#define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /*!< no SIMD instructions present */ -#define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /*!< adds SSAT, USAT (and the Q flag in the PSRs) */ -#define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /*!< N/A */ -/* SCB_ISAR3[SVC_INSTRS] Bits */ -#define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /*!< SVC_INSTRS Bit Offset */ -#define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /*!< SVC_INSTRS Bit Mask */ -#define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /*!< SVC_INSTRS Bit 0 */ -#define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /*!< SVC_INSTRS Bit 1 */ -#define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /*!< SVC_INSTRS Bit 2 */ -#define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /*!< SVC_INSTRS Bit 3 */ -#define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /*!< no SVC (SWI) instructions present */ -#define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /*!< adds SVC (SWI) */ -/* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /*!< SYNCPRIM_INSTRS Bit Offset */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /*!< SYNCPRIM_INSTRS Bit Mask */ -#define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /*!< SYNCPRIM_INSTRS Bit 0 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /*!< SYNCPRIM_INSTRS Bit 1 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /*!< SYNCPRIM_INSTRS Bit 2 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /*!< SYNCPRIM_INSTRS Bit 3 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /*!< no synchronization primitives present */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /*!< adds LDREX, STREX */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */ -/* SCB_ISAR3[TABBRANCH_INSTRS] Bits */ -#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /*!< TABBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /*!< TABBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /*!< TABBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /*!< TABBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /*!< TABBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /*!< TABBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no table-branch instructions present */ -#define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /*!< adds TBB, TBH */ -/* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /*!< THUMBCOPY_INSTRS Bit Offset */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /*!< THUMBCOPY_INSTRS Bit Mask */ -#define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /*!< THUMBCOPY_INSTRS Bit 0 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /*!< THUMBCOPY_INSTRS Bit 1 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /*!< THUMBCOPY_INSTRS Bit 2 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /*!< THUMBCOPY_INSTRS Bit 3 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */ -/* SCB_ISAR3[TRUENOP_INSTRS] Bits */ -#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /*!< TRUENOP_INSTRS Bit Offset */ -#define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /*!< TRUENOP_INSTRS Bit Mask */ -#define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /*!< TRUENOP_INSTRS Bit 0 */ -#define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /*!< TRUENOP_INSTRS Bit 1 */ -#define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /*!< TRUENOP_INSTRS Bit 2 */ -#define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /*!< TRUENOP_INSTRS Bit 3 */ -#define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /*!< true NOP instructions not present - that is, NOP instructions with no */ - /* register dependencies */ -#define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */ -/* SCB_ISAR4[UNPRIV_INSTRS] Bits */ -#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /*!< UNPRIV_INSTRS Bit Offset */ -#define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /*!< UNPRIV_INSTRS Bit Mask */ -#define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /*!< UNPRIV_INSTRS Bit 0 */ -#define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /*!< UNPRIV_INSTRS Bit 1 */ -#define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /*!< UNPRIV_INSTRS Bit 2 */ -#define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /*!< UNPRIV_INSTRS Bit 3 */ -#define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /*!< no "T variant" instructions exist */ -#define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRBT, LDRT, STRBT, STRT */ -#define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */ -/* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /*!< WITHSHIFTS_INSTRS Bit Offset */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /*!< WITHSHIFTS_INSTRS Bit Mask */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /*!< WITHSHIFTS_INSTRS Bit 0 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /*!< WITHSHIFTS_INSTRS Bit 1 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /*!< WITHSHIFTS_INSTRS Bit 2 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /*!< WITHSHIFTS_INSTRS Bit 3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /*!< non-zero shifts only support MOV and shift instructions (see notes) */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /*!< shifts of loads/stores over the range LSL 0-3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /*!< adds other constant shift options. */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /*!< adds register-controlled shift options. */ -/* SCB_ISAR4[WRITEBACK_INSTRS] Bits */ -#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /*!< WRITEBACK_INSTRS Bit Offset */ -#define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /*!< WRITEBACK_INSTRS Bit Mask */ -#define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /*!< WRITEBACK_INSTRS Bit 0 */ -#define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /*!< WRITEBACK_INSTRS Bit 1 */ -#define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /*!< WRITEBACK_INSTRS Bit 2 */ -#define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /*!< WRITEBACK_INSTRS Bit 3 */ -#define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /*!< only non-writeback addressing modes present, except that */ - /* LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */ -#define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */ -/* SCB_ISAR4[BARRIER_INSTRS] Bits */ -#define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /*!< BARRIER_INSTRS Bit Offset */ -#define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /*!< BARRIER_INSTRS Bit Mask */ -#define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /*!< BARRIER_INSTRS Bit 0 */ -#define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /*!< BARRIER_INSTRS Bit 1 */ -#define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /*!< BARRIER_INSTRS Bit 2 */ -#define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /*!< BARRIER_INSTRS Bit 3 */ -#define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /*!< no barrier instructions supported */ -#define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /*!< adds DMB, DSB, ISB barrier instructions */ -/* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /*!< no additional support */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */ -/* SCB_ISAR4[PSR_M_INSTRS] Bits */ -#define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /*!< PSR_M_INSTRS Bit Offset */ -#define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /*!< PSR_M_INSTRS Bit Mask */ -#define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /*!< PSR_M_INSTRS Bit 0 */ -#define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /*!< PSR_M_INSTRS Bit 1 */ -#define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /*!< PSR_M_INSTRS Bit 2 */ -#define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /*!< PSR_M_INSTRS Bit 3 */ -#define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /*!< instructions not present */ -#define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */ -/* SCB_CPACR[CP11] Bits */ -#define SCB_CPACR_CP11_OFS (22) /*!< CP11 Bit Offset */ -#define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /*!< CP11 Bit Mask */ -/* SCB_CPACR[CP10] Bits */ -#define SCB_CPACR_CP10_OFS (20) /*!< CP10 Bit Offset */ -#define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /*!< CP10 Bit Mask */ -/* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */ -#define SCB_SHPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define SCB_SHPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */ -#define SCB_SHPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define SCB_SHPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */ -#define SCB_SHPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define SCB_SHPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */ -#define SCB_SHPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define SCB_SHPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */ -#define SCB_SHPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define SCB_SHPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */ -#define SCB_SHPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define SCB_SHPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */ -#define SCB_SHPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define SCB_SHPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */ -#define SCB_SHPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define SCB_SHPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */ -#define SCB_SHPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define SCB_SHPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */ -#define SCB_SHPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define SCB_SHPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */ -#define SCB_SHPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define SCB_SHPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -/* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */ -#define SCB_SHPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define SCB_SHPR3_PRI_15_M ((uint32_t)0xff000000) /* */ - -/* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */ -#define SCB_CFSR_IACCVIOL_OFS ( 0) /*!< IACCVIOL Offset */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /* */ -/* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */ -#define SCB_CFSR_DACCVIOL_OFS ( 1) /*!< DACCVIOL Offset */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /* */ -/* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */ -#define SCB_CFSR_MUNSTKERR_OFS ( 3) /*!< MUNSTKERR Offset */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /* */ -/* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */ -#define SCB_CFSR_MSTKERR_OFS ( 4) /*!< MSTKERR Offset */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /* */ -/* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */ -#define SCB_CFSR_MMARVALID_OFS ( 7) /*!< MMARVALID Offset */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /* */ -/* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */ -#define SCB_CFSR_IBUSERR_OFS ( 8) /*!< IBUSERR Offset */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /* */ -/* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */ -#define SCB_CFSR_PRECISERR_OFS ( 9) /*!< PRECISERR Offset */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /* */ -/* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */ -#define SCB_CFSR_IMPRECISERR_OFS (10) /*!< IMPRECISERR Offset */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /* */ -/* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */ -#define SCB_CFSR_UNSTKERR_OFS (11) /*!< UNSTKERR Offset */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /* */ -/* SCB_CFSR[SCB_CFSR_STKERR] Bits */ -#define SCB_CFSR_STKERR_OFS (12) /*!< STKERR Offset */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /* */ -/* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */ -#define SCB_CFSR_BFARVALID_OFS (15) /*!< BFARVALID Offset */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /* */ -/* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */ -#define SCB_CFSR_UNDEFINSTR_OFS (16) /*!< UNDEFINSTR Offset */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /* */ -/* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */ -#define SCB_CFSR_INVSTATE_OFS (17) /*!< INVSTATE Offset */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /* */ -/* SCB_CFSR[SCB_CFSR_INVPC] Bits */ -#define SCB_CFSR_INVPC_OFS (18) /*!< INVPC Offset */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /* */ -/* SCB_CFSR[SCB_CFSR_NOCP] Bits */ -#define SCB_CFSR_NOCP_OFS (19) /*!< NOCP Offset */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /* */ -/* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */ -#define SCB_CFSR_UNALIGNED_OFS (24) /*!< UNALIGNED Offset */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /* */ -/* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */ -#define SCB_CFSR_DIVBYZERO_OFS (25) /*!< DIVBYZERO Offset */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /* */ -/* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */ -#define SCB_CFSR_MLSPERR_OFS ( 5) /*!< MLSPERR Offset */ -#define SCB_CFSR_MLSPERR ((uint32_t)0x00000020) /* */ -/* SCB_CFSR[SCB_CFSR_LSPERR] Bits */ -#define SCB_CFSR_LSPERR_OFS (13) /*!< LSPERR Offset */ -#define SCB_CFSR_LSPERR ((uint32_t)0x00002000) /* */ - - -/****************************************************************************** -* SCNSCB Bits -******************************************************************************/ - - -/****************************************************************************** -* SYSCTL_A Bits -******************************************************************************/ -/* SYSCTL_A_REBOOT_CTL[REBOOT] Bits */ -#define SYSCTL_A_REBOOT_CTL_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define SYSCTL_A_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /*!< Write 1 initiates a Reboot of the device */ -/* SYSCTL_A_REBOOT_CTL[WKEY] Bits */ -#define SYSCTL_A_REBOOT_CTL_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_A_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -/* SYSCTL_A_NMI_CTLSTAT[CS_SRC] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_CS_SRC_OFS ( 0) /*!< CS_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /*!< CS interrupt as a source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PSS_SRC] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /*!< PSS_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /*!< PSS interrupt as a source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PCM_SRC] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /*!< PCM_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /*!< PCM interrupt as a source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PIN_SRC] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /*!< PIN_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008) -/* SYSCTL_A_NMI_CTLSTAT[CS_FLG] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_CS_FLG_OFS (16) /*!< CS_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /*!< CS interrupt was the source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PSS_FLG] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_FLG_OFS (17) /*!< PSS_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /*!< PSS interrupt was the source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PCM_FLG] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_FLG_OFS (18) /*!< PCM_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /*!< PCM interrupt was the source of NMI */ -/* SYSCTL_A_NMI_CTLSTAT[PIN_FLG] Bits */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_FLG_OFS (19) /*!< PIN_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /*!< RSTn/NMI pin was the source of NMI */ -/* SYSCTL_A_WDTRESET_CTL[TIMEOUT] Bits */ -#define SYSCTL_A_WDTRESET_CTL_TIMEOUT_OFS ( 0) /*!< TIMEOUT Bit Offset */ -#define SYSCTL_A_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /*!< WDT timeout reset type */ -/* SYSCTL_A_WDTRESET_CTL[VIOLATION] Bits */ -#define SYSCTL_A_WDTRESET_CTL_VIOLATION_OFS ( 1) /*!< VIOLATION Bit Offset */ -#define SYSCTL_A_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /*!< WDT password violation reset type */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T16_0] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /*!< HALT_T16_0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T16_1] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /*!< HALT_T16_1 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T16_2] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /*!< HALT_T16_2 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T16_3] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /*!< HALT_T16_3 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_T32_0] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /*!< HALT_T32_0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUA0] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /*!< HALT_eUA0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUA1] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /*!< HALT_eUA1 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUA2] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /*!< HALT_eUA2 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUA3] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /*!< HALT_eUA3 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUB0] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /*!< HALT_eUB0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUB1] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB1_OFS (10) /*!< HALT_eUB1 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUB2] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB2_OFS (11) /*!< HALT_eUB2 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_eUB3] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB3_OFS (12) /*!< HALT_eUB3 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_ADC] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_ADC_OFS (13) /*!< HALT_ADC Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_WDT] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_WDT_OFS (14) /*!< HALT_WDT Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_DMA] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_DMA_OFS (15) /*!< HALT_DMA Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_PERIHALT_CTL[HALT_LCD] Bits */ -#define SYSCTL_A_PERIHALT_CTL_HALT_LCD_OFS (16) /*!< HALT_LCD Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_LCD ((uint32_t)0x00010000) /*!< Freezes IP operation when CPU is halted */ -/* SYSCTL_A_DIO_GLTFLT_CTL[GLTCH_EN] Bits */ -#define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /*!< GLTCH_EN Bit Offset */ -#define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /*!< Glitch filter enable */ -/* SYSCTL_A_SECDATA_UNLOCK[UNLKEY] Bits */ -#define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK0_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN_OFS ( 0) /*!< BNK0_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank0 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK1_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN_OFS ( 1) /*!< BNK1_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank1 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK2_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN_OFS ( 2) /*!< BNK2_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank2 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK3_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN_OFS ( 3) /*!< BNK3_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank3 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK4_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN_OFS ( 4) /*!< BNK4_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank4 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK5_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN_OFS ( 5) /*!< BNK5_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank5 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK6_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN_OFS ( 6) /*!< BNK6_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank6 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK7_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN_OFS ( 7) /*!< BNK7_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank7 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK8_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN_OFS ( 8) /*!< BNK8_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank8 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK9_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN_OFS ( 9) /*!< BNK9_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank9 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK10_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN_OFS (10) /*!< BNK10_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank10 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK11_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN_OFS (11) /*!< BNK11_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank11 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK12_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN_OFS (12) /*!< BNK12_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank12 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK13_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN_OFS (13) /*!< BNK13_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank13 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK14_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN_OFS (14) /*!< BNK14_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank14 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK15_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN_OFS (15) /*!< BNK15_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank15 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK16_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN_OFS (16) /*!< BNK16_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank16 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK17_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN_OFS (17) /*!< BNK17_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank17 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK18_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN_OFS (18) /*!< BNK18_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank18 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK19_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN_OFS (19) /*!< BNK19_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank19 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK20_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN_OFS (20) /*!< BNK20_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank20 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK21_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN_OFS (21) /*!< BNK21_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank21 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK22_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN_OFS (22) /*!< BNK22_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank22 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK23_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN_OFS (23) /*!< BNK23_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank23 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK24_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN_OFS (24) /*!< BNK24_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank24 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK25_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN_OFS (25) /*!< BNK25_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank25 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK26_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN_OFS (26) /*!< BNK26_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank26 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK27_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN_OFS (27) /*!< BNK27_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank27 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK28_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN_OFS (28) /*!< BNK28_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank28 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK29_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN_OFS (29) /*!< BNK29_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank29 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK30_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN_OFS (30) /*!< BNK30_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank30 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL0[BNK31_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN_OFS (31) /*!< BNK31_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank31 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK32_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN_OFS ( 0) /*!< BNK32_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank32 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK33_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN_OFS ( 1) /*!< BNK33_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank33 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK34_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN_OFS ( 2) /*!< BNK34_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank34 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK35_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN_OFS ( 3) /*!< BNK35_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank35 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK36_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN_OFS ( 4) /*!< BNK36_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank36 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK37_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN_OFS ( 5) /*!< BNK37_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank37 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK38_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN_OFS ( 6) /*!< BNK38_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank38 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK39_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN_OFS ( 7) /*!< BNK39_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank39 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK40_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN_OFS ( 8) /*!< BNK40_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank40 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK41_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN_OFS ( 9) /*!< BNK41_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank41 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK42_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN_OFS (10) /*!< BNK42_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank42 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK43_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN_OFS (11) /*!< BNK43_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank43 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK44_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN_OFS (12) /*!< BNK44_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank44 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK45_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN_OFS (13) /*!< BNK45_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank45 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK46_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN_OFS (14) /*!< BNK46_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank46 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK47_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN_OFS (15) /*!< BNK47_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank47 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK48_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN_OFS (16) /*!< BNK48_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank48 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK49_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN_OFS (17) /*!< BNK49_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank49 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK50_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN_OFS (18) /*!< BNK50_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank50 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK51_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN_OFS (19) /*!< BNK51_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank51 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK52_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN_OFS (20) /*!< BNK52_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank52 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK53_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN_OFS (21) /*!< BNK53_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank53 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK54_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN_OFS (22) /*!< BNK54_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank54 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK55_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN_OFS (23) /*!< BNK55_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank55 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK56_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN_OFS (24) /*!< BNK56_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank56 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK57_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN_OFS (25) /*!< BNK57_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank57 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK58_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN_OFS (26) /*!< BNK58_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank58 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK59_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN_OFS (27) /*!< BNK59_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank59 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK60_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN_OFS (28) /*!< BNK60_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank60 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK61_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN_OFS (29) /*!< BNK61_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank61 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK62_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN_OFS (30) /*!< BNK62_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank62 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL1[BNK63_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN_OFS (31) /*!< BNK63_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank63 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK64_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN_OFS ( 0) /*!< BNK64_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank64 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK65_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN_OFS ( 1) /*!< BNK65_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank65 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK66_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN_OFS ( 2) /*!< BNK66_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank66 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK67_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN_OFS ( 3) /*!< BNK67_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank67 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK68_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN_OFS ( 4) /*!< BNK68_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank68 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK69_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN_OFS ( 5) /*!< BNK69_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank69 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK70_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN_OFS ( 6) /*!< BNK70_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank70 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK71_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN_OFS ( 7) /*!< BNK71_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank71 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK72_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN_OFS ( 8) /*!< BNK72_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank72 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK73_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN_OFS ( 9) /*!< BNK73_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank73 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK74_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN_OFS (10) /*!< BNK74_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank74 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK75_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN_OFS (11) /*!< BNK75_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank75 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK76_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN_OFS (12) /*!< BNK76_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank76 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK77_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN_OFS (13) /*!< BNK77_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank77 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK78_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN_OFS (14) /*!< BNK78_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank78 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK79_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN_OFS (15) /*!< BNK79_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank79 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK80_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN_OFS (16) /*!< BNK80_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank80 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK81_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN_OFS (17) /*!< BNK81_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank81 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK82_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN_OFS (18) /*!< BNK82_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank82 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK83_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN_OFS (19) /*!< BNK83_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank83 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK84_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN_OFS (20) /*!< BNK84_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank84 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK85_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN_OFS (21) /*!< BNK85_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank85 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK86_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN_OFS (22) /*!< BNK86_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank86 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK87_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN_OFS (23) /*!< BNK87_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank87 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK88_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN_OFS (24) /*!< BNK88_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank88 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK89_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN_OFS (25) /*!< BNK89_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank89 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK90_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN_OFS (26) /*!< BNK90_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank90 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK91_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN_OFS (27) /*!< BNK91_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank91 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK92_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN_OFS (28) /*!< BNK92_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank92 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK93_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN_OFS (29) /*!< BNK93_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank93 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK94_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN_OFS (30) /*!< BNK94_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank94 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL2[BNK95_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN_OFS (31) /*!< BNK95_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank95 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK96_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN_OFS ( 0) /*!< BNK96_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank96 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK97_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN_OFS ( 1) /*!< BNK97_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank97 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK98_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN_OFS ( 2) /*!< BNK98_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank98 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK99_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN_OFS ( 3) /*!< BNK99_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank99 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK100_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN_OFS ( 4) /*!< BNK100_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank100 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK101_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN_OFS ( 5) /*!< BNK101_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank101 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK102_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN_OFS ( 6) /*!< BNK102_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank102 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK103_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN_OFS ( 7) /*!< BNK103_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank103 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK104_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN_OFS ( 8) /*!< BNK104_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank104 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK105_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN_OFS ( 9) /*!< BNK105_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank105 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK106_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN_OFS (10) /*!< BNK106_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank106 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK107_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN_OFS (11) /*!< BNK107_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank107 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK108_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN_OFS (12) /*!< BNK108_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank108 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK109_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN_OFS (13) /*!< BNK109_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank109 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK110_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN_OFS (14) /*!< BNK110_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank110 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK111_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN_OFS (15) /*!< BNK111_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank111 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK112_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN_OFS (16) /*!< BNK112_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank112 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK113_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN_OFS (17) /*!< BNK113_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank113 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK114_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN_OFS (18) /*!< BNK114_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank114 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK115_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN_OFS (19) /*!< BNK115_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank115 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK116_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN_OFS (20) /*!< BNK116_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank116 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK117_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN_OFS (21) /*!< BNK117_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank117 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK118_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN_OFS (22) /*!< BNK118_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank118 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK119_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN_OFS (23) /*!< BNK119_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank119 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK120_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN_OFS (24) /*!< BNK120_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank120 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK121_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN_OFS (25) /*!< BNK121_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank121 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK122_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN_OFS (26) /*!< BNK122_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank122 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK123_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN_OFS (27) /*!< BNK123_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank123 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK124_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN_OFS (28) /*!< BNK124_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank124 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK125_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN_OFS (29) /*!< BNK125_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank125 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK126_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN_OFS (30) /*!< BNK126_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank126 of the SRAM */ -/* SYSCTL_A_SRAM_BANKEN_CTL3[BNK127_EN] Bits */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN_OFS (31) /*!< BNK127_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank127 of the SRAM */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK0_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN_OFS ( 0) /*!< BLK0_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN ((uint32_t)0x00000001) /*!< Block0 is always retained in LPM3, LPM4 and LPM3.5 modes of operation */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK1_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN_OFS ( 1) /*!< BLK1_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN ((uint32_t)0x00000002) /*!< When 1, Block1 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK2_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN_OFS ( 2) /*!< BLK2_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN ((uint32_t)0x00000004) /*!< When 1, Block2 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK3_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN_OFS ( 3) /*!< BLK3_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN ((uint32_t)0x00000008) /*!< When 1, Block3 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK4_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN_OFS ( 4) /*!< BLK4_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN ((uint32_t)0x00000010) /*!< When 1, Block4 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK5_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN_OFS ( 5) /*!< BLK5_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN ((uint32_t)0x00000020) /*!< When 1, Block5 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK6_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN_OFS ( 6) /*!< BLK6_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN ((uint32_t)0x00000040) /*!< When 1, Block6 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK7_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN_OFS ( 7) /*!< BLK7_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN ((uint32_t)0x00000080) /*!< When 1, Block7 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK8_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN_OFS ( 8) /*!< BLK8_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN ((uint32_t)0x00000100) /*!< When 1, Block8 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK9_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN_OFS ( 9) /*!< BLK9_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN ((uint32_t)0x00000200) /*!< When 1, Block9 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK10_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN_OFS (10) /*!< BLK10_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN ((uint32_t)0x00000400) /*!< When 1, Block10 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK11_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN_OFS (11) /*!< BLK11_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN ((uint32_t)0x00000800) /*!< When 1, Block11 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK12_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN_OFS (12) /*!< BLK12_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN ((uint32_t)0x00001000) /*!< When 1, Block12 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK13_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN_OFS (13) /*!< BLK13_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN ((uint32_t)0x00002000) /*!< When 1, Block13 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK14_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN_OFS (14) /*!< BLK14_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN ((uint32_t)0x00004000) /*!< When 1, Block14 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK15_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN_OFS (15) /*!< BLK15_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN ((uint32_t)0x00008000) /*!< When 1, Block15 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK16_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN_OFS (16) /*!< BLK16_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN ((uint32_t)0x00010000) /*!< When 1, Block16 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK17_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN_OFS (17) /*!< BLK17_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN ((uint32_t)0x00020000) /*!< When 1, Block17 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK18_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN_OFS (18) /*!< BLK18_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN ((uint32_t)0x00040000) /*!< When 1, Block18 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK19_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN_OFS (19) /*!< BLK19_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN ((uint32_t)0x00080000) /*!< When 1, Block19 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK20_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN_OFS (20) /*!< BLK20_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN ((uint32_t)0x00100000) /*!< When 1, Block20 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK21_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN_OFS (21) /*!< BLK21_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN ((uint32_t)0x00200000) /*!< When 1, Block21 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK22_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN_OFS (22) /*!< BLK22_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN ((uint32_t)0x00400000) /*!< When 1, Block22 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK23_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN_OFS (23) /*!< BLK23_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN ((uint32_t)0x00800000) /*!< When 1, Block23 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK24_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN_OFS (24) /*!< BLK24_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN ((uint32_t)0x01000000) /*!< When 1, Block24 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK25_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN_OFS (25) /*!< BLK25_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN ((uint32_t)0x02000000) /*!< When 1, Block25 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK26_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN_OFS (26) /*!< BLK26_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN ((uint32_t)0x04000000) /*!< When 1, Block26 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK27_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN_OFS (27) /*!< BLK27_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN ((uint32_t)0x08000000) /*!< When 1, Block27 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK28_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN_OFS (28) /*!< BLK28_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN ((uint32_t)0x10000000) /*!< When 1, Block28 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK29_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN_OFS (29) /*!< BLK29_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN ((uint32_t)0x20000000) /*!< When 1, Block29 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK30_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN_OFS (30) /*!< BLK30_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN ((uint32_t)0x40000000) /*!< When 1, Block30 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL0[BLK31_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN_OFS (31) /*!< BLK31_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN ((uint32_t)0x80000000) /*!< When 1, Block31 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK32_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN_OFS ( 0) /*!< BLK32_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN ((uint32_t)0x00000001) /*!< When 1, Block32 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK33_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN_OFS ( 1) /*!< BLK33_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN ((uint32_t)0x00000002) /*!< When 1, Block33 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK34_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN_OFS ( 2) /*!< BLK34_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN ((uint32_t)0x00000004) /*!< When 1, Block34 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK35_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN_OFS ( 3) /*!< BLK35_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN ((uint32_t)0x00000008) /*!< When 1, Block35 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK36_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN_OFS ( 4) /*!< BLK36_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN ((uint32_t)0x00000010) /*!< When 1, Block36 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK37_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN_OFS ( 5) /*!< BLK37_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN ((uint32_t)0x00000020) /*!< When 1, Block37 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK38_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN_OFS ( 6) /*!< BLK38_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN ((uint32_t)0x00000040) /*!< When 1, Block38 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK39_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN_OFS ( 7) /*!< BLK39_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN ((uint32_t)0x00000080) /*!< When 1, Block39 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK40_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN_OFS ( 8) /*!< BLK40_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN ((uint32_t)0x00000100) /*!< When 1, Block40 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK41_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN_OFS ( 9) /*!< BLK41_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN ((uint32_t)0x00000200) /*!< When 1, Block41 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK42_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN_OFS (10) /*!< BLK42_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN ((uint32_t)0x00000400) /*!< When 1, Block42 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK43_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN_OFS (11) /*!< BLK43_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN ((uint32_t)0x00000800) /*!< When 1, Block43 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK44_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN_OFS (12) /*!< BLK44_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN ((uint32_t)0x00001000) /*!< When 1, Block44 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK45_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN_OFS (13) /*!< BLK45_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN ((uint32_t)0x00002000) /*!< When 1, Block45 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK46_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN_OFS (14) /*!< BLK46_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN ((uint32_t)0x00004000) /*!< When 1, Block46 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK47_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN_OFS (15) /*!< BLK47_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN ((uint32_t)0x00008000) /*!< When 1, Block47 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK48_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN_OFS (16) /*!< BLK48_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN ((uint32_t)0x00010000) /*!< When 1, Block48 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK49_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN_OFS (17) /*!< BLK49_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN ((uint32_t)0x00020000) /*!< When 1, Block49 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK50_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN_OFS (18) /*!< BLK50_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN ((uint32_t)0x00040000) /*!< When 1, Block50 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK51_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN_OFS (19) /*!< BLK51_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN ((uint32_t)0x00080000) /*!< When 1, Block51 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK52_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN_OFS (20) /*!< BLK52_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN ((uint32_t)0x00100000) /*!< When 1, Block52 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK53_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN_OFS (21) /*!< BLK53_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN ((uint32_t)0x00200000) /*!< When 1, Block53 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK54_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN_OFS (22) /*!< BLK54_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN ((uint32_t)0x00400000) /*!< When 1, Block54 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK55_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN_OFS (23) /*!< BLK55_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN ((uint32_t)0x00800000) /*!< When 1, Block55 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK56_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN_OFS (24) /*!< BLK56_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN ((uint32_t)0x01000000) /*!< When 1, Block56 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK57_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN_OFS (25) /*!< BLK57_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN ((uint32_t)0x02000000) /*!< When 1, Block57 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK58_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN_OFS (26) /*!< BLK58_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN ((uint32_t)0x04000000) /*!< When 1, Block58 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK59_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN_OFS (27) /*!< BLK59_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN ((uint32_t)0x08000000) /*!< When 1, Block59 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK60_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN_OFS (28) /*!< BLK60_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN ((uint32_t)0x10000000) /*!< When 1, Block60 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK61_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN_OFS (29) /*!< BLK61_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN ((uint32_t)0x20000000) /*!< When 1, Block61 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK62_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN_OFS (30) /*!< BLK62_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN ((uint32_t)0x40000000) /*!< When 1, Block62 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL1[BLK63_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN_OFS (31) /*!< BLK63_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN ((uint32_t)0x80000000) /*!< When 1, Block63 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK64_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN_OFS ( 0) /*!< BLK64_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN ((uint32_t)0x00000001) /*!< When 1, Block64 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK65_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN_OFS ( 1) /*!< BLK65_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN ((uint32_t)0x00000002) /*!< When 1, Block65 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK66_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN_OFS ( 2) /*!< BLK66_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN ((uint32_t)0x00000004) /*!< When 1, Block66 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK67_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN_OFS ( 3) /*!< BLK67_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN ((uint32_t)0x00000008) /*!< When 1, Block67 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK68_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN_OFS ( 4) /*!< BLK68_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN ((uint32_t)0x00000010) /*!< When 1, Block68 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK69_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN_OFS ( 5) /*!< BLK69_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN ((uint32_t)0x00000020) /*!< When 1, Block69 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK70_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN_OFS ( 6) /*!< BLK70_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN ((uint32_t)0x00000040) /*!< When 1, Block70 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK71_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN_OFS ( 7) /*!< BLK71_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN ((uint32_t)0x00000080) /*!< When 1, Block71 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK72_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN_OFS ( 8) /*!< BLK72_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN ((uint32_t)0x00000100) /*!< When 1, Block72 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK73_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN_OFS ( 9) /*!< BLK73_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN ((uint32_t)0x00000200) /*!< When 1, Block73 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK74_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN_OFS (10) /*!< BLK74_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN ((uint32_t)0x00000400) /*!< When 1, Block74 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK75_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN_OFS (11) /*!< BLK75_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN ((uint32_t)0x00000800) /*!< When 1, Block75 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK76_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN_OFS (12) /*!< BLK76_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN ((uint32_t)0x00001000) /*!< When 1, Block76 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK77_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN_OFS (13) /*!< BLK77_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN ((uint32_t)0x00002000) /*!< When 1, Block77 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK78_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN_OFS (14) /*!< BLK78_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN ((uint32_t)0x00004000) /*!< When 1, Block78 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK79_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN_OFS (15) /*!< BLK79_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN ((uint32_t)0x00008000) /*!< When 1, Block79 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK80_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN_OFS (16) /*!< BLK80_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN ((uint32_t)0x00010000) /*!< When 1, Block80 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK81_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN_OFS (17) /*!< BLK81_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN ((uint32_t)0x00020000) /*!< When 1, Block81 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK82_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN_OFS (18) /*!< BLK82_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN ((uint32_t)0x00040000) /*!< When 1, Block82 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK83_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN_OFS (19) /*!< BLK83_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN ((uint32_t)0x00080000) /*!< When 1, Block83 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK84_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN_OFS (20) /*!< BLK84_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN ((uint32_t)0x00100000) /*!< When 1, Block84 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK85_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN_OFS (21) /*!< BLK85_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN ((uint32_t)0x00200000) /*!< When 1, Block85 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK86_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN_OFS (22) /*!< BLK86_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN ((uint32_t)0x00400000) /*!< When 1, Block86 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK87_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN_OFS (23) /*!< BLK87_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN ((uint32_t)0x00800000) /*!< When 1, Block87 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK88_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN_OFS (24) /*!< BLK88_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN ((uint32_t)0x01000000) /*!< When 1, Block88 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK89_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN_OFS (25) /*!< BLK89_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN ((uint32_t)0x02000000) /*!< When 1, Block89 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK90_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN_OFS (26) /*!< BLK90_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN ((uint32_t)0x04000000) /*!< When 1, Block90 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK91_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN_OFS (27) /*!< BLK91_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN ((uint32_t)0x08000000) /*!< When 1, Block91 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK92_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN_OFS (28) /*!< BLK92_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN ((uint32_t)0x10000000) /*!< When 1, Block92 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK93_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN_OFS (29) /*!< BLK93_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN ((uint32_t)0x20000000) /*!< When 1, Block93 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK94_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN_OFS (30) /*!< BLK94_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN ((uint32_t)0x40000000) /*!< When 1, Block94 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL2[BLK95_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN_OFS (31) /*!< BLK95_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN ((uint32_t)0x80000000) /*!< When 1, Block95 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK96_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN_OFS ( 0) /*!< BLK96_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN ((uint32_t)0x00000001) /*!< When 1, Block96 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK97_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN_OFS ( 1) /*!< BLK97_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN ((uint32_t)0x00000002) /*!< When 1, Block97 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK98_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN_OFS ( 2) /*!< BLK98_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN ((uint32_t)0x00000004) /*!< When 1, Block98 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK99_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN_OFS ( 3) /*!< BLK99_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN ((uint32_t)0x00000008) /*!< When 1, Block99 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK100_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN_OFS ( 4) /*!< BLK100_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN ((uint32_t)0x00000010) /*!< When 1, Block100 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK101_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN_OFS ( 5) /*!< BLK101_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN ((uint32_t)0x00000020) /*!< When 1, Block101 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK102_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN_OFS ( 6) /*!< BLK102_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN ((uint32_t)0x00000040) /*!< When 1, Block102 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK103_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN_OFS ( 7) /*!< BLK103_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN ((uint32_t)0x00000080) /*!< When 1, Block103 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK104_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN_OFS ( 8) /*!< BLK104_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN ((uint32_t)0x00000100) /*!< When 1, Block104 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK105_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN_OFS ( 9) /*!< BLK105_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN ((uint32_t)0x00000200) /*!< When 1, Block105 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK106_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN_OFS (10) /*!< BLK106_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN ((uint32_t)0x00000400) /*!< When 1, Block106 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK107_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN_OFS (11) /*!< BLK107_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN ((uint32_t)0x00000800) /*!< When 1, Block107 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK108_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN_OFS (12) /*!< BLK108_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN ((uint32_t)0x00001000) /*!< When 1, Block108 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK109_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN_OFS (13) /*!< BLK109_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN ((uint32_t)0x00002000) /*!< When 1, Block109 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK110_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN_OFS (14) /*!< BLK110_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN ((uint32_t)0x00004000) /*!< When 1, Block110 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK111_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN_OFS (15) /*!< BLK111_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN ((uint32_t)0x00008000) /*!< When 1, Block111 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK112_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN_OFS (16) /*!< BLK112_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN ((uint32_t)0x00010000) /*!< When 1, Block112 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK113_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN_OFS (17) /*!< BLK113_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN ((uint32_t)0x00020000) /*!< When 1, Block113 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK114_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN_OFS (18) /*!< BLK114_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN ((uint32_t)0x00040000) /*!< When 1, Block114 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK115_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN_OFS (19) /*!< BLK115_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN ((uint32_t)0x00080000) /*!< When 1, Block115 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK116_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN_OFS (20) /*!< BLK116_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN ((uint32_t)0x00100000) /*!< When 1, Block116 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK117_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN_OFS (21) /*!< BLK117_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN ((uint32_t)0x00200000) /*!< When 1, Block117 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK118_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN_OFS (22) /*!< BLK118_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN ((uint32_t)0x00400000) /*!< When 1, Block118 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK119_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN_OFS (23) /*!< BLK119_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN ((uint32_t)0x00800000) /*!< When 1, Block119 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK120_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN_OFS (24) /*!< BLK120_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN ((uint32_t)0x01000000) /*!< When 1, Block120 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK121_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN_OFS (25) /*!< BLK121_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN ((uint32_t)0x02000000) /*!< When 1, Block121 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK122_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN_OFS (26) /*!< BLK122_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN ((uint32_t)0x04000000) /*!< When 1, Block122 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK123_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN_OFS (27) /*!< BLK123_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN ((uint32_t)0x08000000) /*!< When 1, Block123 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK124_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN_OFS (28) /*!< BLK124_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN ((uint32_t)0x10000000) /*!< When 1, Block124 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK125_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN_OFS (29) /*!< BLK125_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN ((uint32_t)0x20000000) /*!< When 1, Block125 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK126_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN_OFS (30) /*!< BLK126_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN ((uint32_t)0x40000000) /*!< When 1, Block126 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_BLKRET_CTL3[BLK127_EN] Bits */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN_OFS (31) /*!< BLK127_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN ((uint32_t)0x80000000) /*!< When 1, Block127 of the SRAM is retained in LPM3 and LPM4 */ -/* SYSCTL_A_SRAM_STAT[BNKEN_RDY] Bits */ -#define SYSCTL_A_SRAM_STAT_BNKEN_RDY_OFS ( 0) /*!< BNKEN_RDY Bit Offset */ -#define SYSCTL_A_SRAM_STAT_BNKEN_RDY ((uint32_t)0x00000001) /*!< When 1, indicates SRAM is ready for access and banks can be */ - /* enabled/disabled. */ -/* SYSCTL_A_SRAM_STAT[BLKRET_RDY] Bits */ -#define SYSCTL_A_SRAM_STAT_BLKRET_RDY_OFS ( 1) /*!< BLKRET_RDY Bit Offset */ -#define SYSCTL_A_SRAM_STAT_BLKRET_RDY ((uint32_t)0x00000002) /*!< When 1, indicates SRAM is ready for access and blocks can be */ - /* enabled/disabled for retention. */ -/* SYSCTL_A_MASTER_UNLOCK[UNLKEY] Bits */ -#define SYSCTL_A_MASTER_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_A_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -/* SYSCTL_A_RESET_REQ[POR] Bits */ -#define SYSCTL_A_RESET_REQ_POR_OFS ( 0) /*!< POR Bit Offset */ -#define SYSCTL_A_RESET_REQ_POR ((uint32_t)0x00000001) /*!< Generate POR */ -/* SYSCTL_A_RESET_REQ[REBOOT] Bits */ -#define SYSCTL_A_RESET_REQ_REBOOT_OFS ( 1) /*!< REBOOT Bit Offset */ -#define SYSCTL_A_RESET_REQ_REBOOT ((uint32_t)0x00000002) /*!< Generate Reboot_Reset */ -/* SYSCTL_A_RESET_REQ[WKEY] Bits */ -#define SYSCTL_A_RESET_REQ_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_A_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -/* SYSCTL_A_RESET_STATOVER[SOFT] Bits */ -#define SYSCTL_A_RESET_STATOVER_SOFT_OFS ( 0) /*!< SOFT Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /*!< Indicates if SOFT Reset is active */ -/* SYSCTL_A_RESET_STATOVER[HARD] Bits */ -#define SYSCTL_A_RESET_STATOVER_HARD_OFS ( 1) /*!< HARD Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_HARD ((uint32_t)0x00000002) /*!< Indicates if HARD Reset is active */ -/* SYSCTL_A_RESET_STATOVER[REBOOT] Bits */ -#define SYSCTL_A_RESET_STATOVER_REBOOT_OFS ( 2) /*!< REBOOT Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /*!< Indicates if Reboot Reset is active */ -/* SYSCTL_A_RESET_STATOVER[SOFT_OVER] Bits */ -#define SYSCTL_A_RESET_STATOVER_SOFT_OVER_OFS ( 8) /*!< SOFT_OVER Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /*!< SOFT_Reset overwrite request */ -/* SYSCTL_A_RESET_STATOVER[HARD_OVER] Bits */ -#define SYSCTL_A_RESET_STATOVER_HARD_OVER_OFS ( 9) /*!< HARD_OVER Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /*!< HARD_Reset overwrite request */ -/* SYSCTL_A_RESET_STATOVER[RBT_OVER] Bits */ -#define SYSCTL_A_RESET_STATOVER_RBT_OVER_OFS (10) /*!< RBT_OVER Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /*!< Reboot Reset overwrite request */ -/* Pre-defined bitfield values */ -#define SYSCTL_A_CSYS_MASTER_UNLOCK_UNLKEY_VAL ((uint32_t)0x0000695A) /*!< Unlock key value which when written, determines if accesses to other CPU_SYS register */ -#define SYSCTL_A_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ -#define SYSCTL_A_BOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ -#define SYSCTL_A_ETW_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ -#define SYSCTL_A_SECDATA_UNLOCK_KEY_VAL ((uint32_t)0x0000695A) /*!< Unlock Key value, which requests for secure data region to be unlocked for data access */ - - -/****************************************************************************** -* SYSTICK Bits -******************************************************************************/ - -/****************************************************************************** -* Timer32 Bits -******************************************************************************/ -/* TIMER32_CONTROL[ONESHOT] Bits */ -#define TIMER32_CONTROL_ONESHOT_OFS ( 0) /*!< ONESHOT Bit Offset */ -#define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /*!< Selects one-shot or wrapping counter mode */ -/* TIMER32_CONTROL[SIZE] Bits */ -#define TIMER32_CONTROL_SIZE_OFS ( 1) /*!< SIZE Bit Offset */ -#define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /*!< Selects 16 or 32 bit counter operation */ -/* TIMER32_CONTROL[PRESCALE] Bits */ -#define TIMER32_CONTROL_PRESCALE_OFS ( 2) /*!< PRESCALE Bit Offset */ -#define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /*!< PRESCALE Bit Mask */ -#define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /*!< PRESCALE Bit 0 */ -#define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /*!< PRESCALE Bit 1 */ -#define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /*!< 0 stages of prescale, clock is divided by 1 */ -#define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /*!< 4 stages of prescale, clock is divided by 16 */ -#define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /*!< 8 stages of prescale, clock is divided by 256 */ -/* TIMER32_CONTROL[IE] Bits */ -#define TIMER32_CONTROL_IE_OFS ( 5) /*!< IE Bit Offset */ -#define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /*!< Interrupt enable bit */ -/* TIMER32_CONTROL[MODE] Bits */ -#define TIMER32_CONTROL_MODE_OFS ( 6) /*!< MODE Bit Offset */ -#define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /*!< Mode bit */ -/* TIMER32_CONTROL[ENABLE] Bits */ -#define TIMER32_CONTROL_ENABLE_OFS ( 7) /*!< ENABLE Bit Offset */ -#define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080) -/* TIMER32_RIS[RAW_IFG] Bits */ -#define TIMER32_RIS_RAW_IFG_OFS ( 0) /*!< RAW_IFG Bit Offset */ -#define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /*!< Raw interrupt status */ -/* TIMER32_MIS[IFG] Bits */ -#define TIMER32_MIS_IFG_OFS ( 0) /*!< IFG Bit Offset */ -#define TIMER32_MIS_IFG ((uint32_t)0x00000001) /*!< Enabled interrupt status */ - - - -/****************************************************************************** -* TIMER_A Bits -******************************************************************************/ -/* TIMER_A_CTL[IFG] Bits */ -#define TIMER_A_CTL_IFG_OFS ( 0) /*!< TAIFG Bit Offset */ -#define TIMER_A_CTL_IFG ((uint16_t)0x0001) /*!< TimerA interrupt flag */ -/* TIMER_A_CTL[IE] Bits */ -#define TIMER_A_CTL_IE_OFS ( 1) /*!< TAIE Bit Offset */ -#define TIMER_A_CTL_IE ((uint16_t)0x0002) /*!< TimerA interrupt enable */ -/* TIMER_A_CTL[CLR] Bits */ -#define TIMER_A_CTL_CLR_OFS ( 2) /*!< TACLR Bit Offset */ -#define TIMER_A_CTL_CLR ((uint16_t)0x0004) /*!< TimerA clear */ -/* TIMER_A_CTL[MC] Bits */ -#define TIMER_A_CTL_MC_OFS ( 4) /*!< MC Bit Offset */ -#define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /*!< MC Bit Mask */ -#define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /*!< MC Bit 0 */ -#define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /*!< MC Bit 1 */ -#define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -#define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -/* TIMER_A_CTL[ID] Bits */ -#define TIMER_A_CTL_ID_OFS ( 6) /*!< ID Bit Offset */ -#define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /*!< ID Bit Mask */ -#define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /*!< ID Bit 0 */ -#define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /*!< ID Bit 1 */ -#define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /*!< /8 */ -#define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /*!< /8 */ -/* TIMER_A_CTL[SSEL] Bits */ -#define TIMER_A_CTL_SSEL_OFS ( 8) /*!< TASSEL Bit Offset */ -#define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /*!< TASSEL Bit Mask */ -#define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /*!< SSEL Bit 0 */ -#define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /*!< SSEL Bit 1 */ -#define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /*!< INCLK */ -#define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /*!< INCLK */ -/* TIMER_A_CCTLN[CCIFG] Bits */ -#define TIMER_A_CCTLN_CCIFG_OFS ( 0) /*!< CCIFG Bit Offset */ -#define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /*!< Capture/compare interrupt flag */ -/* TIMER_A_CCTLN[COV] Bits */ -#define TIMER_A_CCTLN_COV_OFS ( 1) /*!< COV Bit Offset */ -#define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /*!< Capture overflow */ -/* TIMER_A_CCTLN[OUT] Bits */ -#define TIMER_A_CCTLN_OUT_OFS ( 2) /*!< OUT Bit Offset */ -#define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /*!< Output */ -/* TIMER_A_CCTLN[CCI] Bits */ -#define TIMER_A_CCTLN_CCI_OFS ( 3) /*!< CCI Bit Offset */ -#define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /*!< Capture/compare input */ -/* TIMER_A_CCTLN[CCIE] Bits */ -#define TIMER_A_CCTLN_CCIE_OFS ( 4) /*!< CCIE Bit Offset */ -#define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /*!< Capture/compare interrupt enable */ -/* TIMER_A_CCTLN[OUTMOD] Bits */ -#define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /*!< OUTMOD Bit Offset */ -#define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /*!< OUTMOD Bit Mask */ -#define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /*!< OUTMOD Bit 0 */ -#define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /*!< OUTMOD Bit 1 */ -#define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /*!< OUTMOD Bit 2 */ -#define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /*!< OUT bit value */ -#define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /*!< Set */ -#define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /*!< Toggle/reset */ -#define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /*!< Set/reset */ -#define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /*!< Toggle */ -#define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /*!< Reset */ -#define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /*!< Toggle/set */ -#define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /*!< Reset/set */ -/* TIMER_A_CCTLN[CAP] Bits */ -#define TIMER_A_CCTLN_CAP_OFS ( 8) /*!< CAP Bit Offset */ -#define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /*!< Capture mode */ -/* TIMER_A_CCTLN[SCCI] Bits */ -#define TIMER_A_CCTLN_SCCI_OFS (10) /*!< SCCI Bit Offset */ -#define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /*!< Synchronized capture/compare input */ -/* TIMER_A_CCTLN[SCS] Bits */ -#define TIMER_A_CCTLN_SCS_OFS (11) /*!< SCS Bit Offset */ -#define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /*!< Synchronize capture source */ -/* TIMER_A_CCTLN[CCIS] Bits */ -#define TIMER_A_CCTLN_CCIS_OFS (12) /*!< CCIS Bit Offset */ -#define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /*!< CCIS Bit Mask */ -#define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /*!< CCIS Bit 0 */ -#define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /*!< CCIS Bit 1 */ -#define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /*!< VCC */ -#define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /*!< VCC */ -/* TIMER_A_CCTLN[CM] Bits */ -#define TIMER_A_CCTLN_CM_OFS (14) /*!< CM Bit Offset */ -#define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /*!< CM Bit Mask */ -#define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /*!< CM Bit 0 */ -#define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /*!< CM Bit 1 */ -#define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -#define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -/* TIMER_A_EX0[IDEX] Bits */ -#define TIMER_A_EX0_IDEX_OFS ( 0) /*!< TAIDEX Bit Offset */ -#define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /*!< TAIDEX Bit Mask */ -#define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /*!< IDEX Bit 0 */ -#define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /*!< IDEX Bit 1 */ -#define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /*!< IDEX Bit 2 */ -#define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /*!< Divide by 8 */ -#define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /*!< Divide by 8 */ - -/****************************************************************************** -* TLV Bits -******************************************************************************/ -/****************************************************************************** -* TLV table start and TLV tags * -******************************************************************************/ -#define TLV_START_ADDR (TLV_BASE + 0x0004) /*!< Start Address of the TLV structure */ - -#define TLV_TAG_RESERVED1 1 -#define TLV_TAG_RESERVED2 2 -#define TLV_TAG_CS 3 -#define TLV_TAG_FLASHCTL 4 -#define TLV_TAG_ADC14 5 -#define TLV_TAG_RESERVED6 6 -#define TLV_TAG_RESERVED7 7 -#define TLV_TAG_REF 8 -#define TLV_TAG_RESERVED9 9 -#define TLV_TAG_RESERVED10 10 -#define TLV_TAG_DEVINFO 11 -#define TLV_TAG_DIEREC 12 -#define TLV_TAG_RANDNUM 13 -#define TLV_TAG_RESERVED14 14 -#define TLV_TAG_BSL 15 -#define TLV_TAG_END (0x0BD0E11D) - - -/****************************************************************************** -* TPIU Bits -******************************************************************************/ - - -/****************************************************************************** -* WDT_A Bits -******************************************************************************/ -/* WDT_A_CTL[IS] Bits */ -#define WDT_A_CTL_IS_OFS ( 0) /*!< WDTIS Bit Offset */ -#define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /*!< WDTIS Bit Mask */ -#define WDT_A_CTL_IS0 ((uint16_t)0x0001) /*!< IS Bit 0 */ -#define WDT_A_CTL_IS1 ((uint16_t)0x0002) /*!< IS Bit 1 */ -#define WDT_A_CTL_IS2 ((uint16_t)0x0004) /*!< IS Bit 2 */ -#define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ -#define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ -/* WDT_A_CTL[CNTCL] Bits */ -#define WDT_A_CTL_CNTCL_OFS ( 3) /*!< WDTCNTCL Bit Offset */ -#define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /*!< Watchdog timer counter clear */ -/* WDT_A_CTL[TMSEL] Bits */ -#define WDT_A_CTL_TMSEL_OFS ( 4) /*!< WDTTMSEL Bit Offset */ -#define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /*!< Watchdog timer mode select */ -/* WDT_A_CTL[SSEL] Bits */ -#define WDT_A_CTL_SSEL_OFS ( 5) /*!< WDTSSEL Bit Offset */ -#define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /*!< WDTSSEL Bit Mask */ -#define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /*!< SSEL Bit 0 */ -#define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /*!< SSEL Bit 1 */ -#define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /*!< BCLK */ -#define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /*!< BCLK */ -/* WDT_A_CTL[HOLD] Bits */ -#define WDT_A_CTL_HOLD_OFS ( 7) /*!< WDTHOLD Bit Offset */ -#define WDT_A_CTL_HOLD ((uint16_t)0x0080) /*!< Watchdog timer hold */ -/* WDT_A_CTL[PW] Bits */ -#define WDT_A_CTL_PW_OFS ( 8) /*!< WDTPW Bit Offset */ -#define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /*!< WDTPW Bit Mask */ -/* Pre-defined bitfield values */ -#define WDT_A_CTL_PW ((uint16_t)0x5A00) /*!< WDT Key Value for WDT write access */ - - -/****************************************************************************** -* BSL * -******************************************************************************/ -#define BSL_DEFAULT_PARAM ((uint32_t)0xFC48FFFF) /*!< I2C slave address = 0x48, Interface selection = Auto */ -#define BSL_API_TABLE_ADDR ((uint32_t)0x00202000) /*!< Address of BSL API table */ -#define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR)) - -#define BSL_AUTO_INTERFACE ((uint32_t)0x0000E0000) /*!< Auto detect interface */ -#define BSL_UART_INTERFACE ((uint32_t)0x0000C0000) /*!< UART interface */ -#define BSL_SPI_INTERFACE ((uint32_t)0x0000A0000) /*!< SPI interface */ -#define BSL_I2C_INTERFACE ((uint32_t)0x000080000) /*!< I2C interface */ - -#define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */ - - -/****************************************************************************** -* Mailbox struct legacy definition * -******************************************************************************/ -#define FLASH_MAILBOX_Type FL_BOOTOVER_MAILBOX_Type - -/****************************************************************************** -* Device Unlock Support * -******************************************************************************/ -/* unlock the device by: - * Load SYSCTL_SECDATA_UNLOCK register address into R0 - * Load SYSCTL_SECDATA_UNLOCK unlock key into R1 - * Write the unlock key to the SYSCTL_SECDATA_UNLOCK register - */ -#define UNLOCK_DEVICE\ - __asm(" MOVW.W R0, #0x3040");\ - __asm(" MOVT.W R0, #0xE004");\ - __asm(" MOVW.W R1, #0x695A");\ - __asm(" MOVT.W R1, #0x0000");\ - __asm(" STR R1, [R0]"); - -/****************************************************************************** -* -* The following are values that can be used to choose the command that will be -* run by the boot code. Perform a logical OR of these settings to create your -* general parameter command. -* -******************************************************************************/ -#define COMMAND_FACTORY_RESET ((uint32_t)0x00010000) -#define COMMAND_BSL_CONFIG ((uint32_t)0x00020000) -#define COMMAND_JTAG_SWD_LOCK_SECEN ((uint32_t)0x00080000) -#define COMMAND_SEC_ZONE0_EN ((uint32_t)0x00100000) -#define COMMAND_SEC_ZONE1_EN ((uint32_t)0x00200000) -#define COMMAND_SEC_ZONE2_EN ((uint32_t)0x00400000) -#define COMMAND_SEC_ZONE3_EN ((uint32_t)0x00800000) -#define COMMAND_SEC_ZONE0_UPDATE ((uint32_t)0x01000000) -#define COMMAND_SEC_ZONE1_UPDATE ((uint32_t)0x02000000) -#define COMMAND_SEC_ZONE2_UPDATE ((uint32_t)0x04000000) -#define COMMAND_SEC_ZONE3_UPDATE ((uint32_t)0x08000000) -#define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE ((uint32_t)0x10000000) -#define COMMAND_NONE ((uint32_t)0xFFFFFFFF) - -/****************************************************************************** -* -* The following are values that can be used to configure the BSL. Perform a -* logical OR of these settings to create your BSL parameter. -* -******************************************************************************/ -#define BSL_CONFIG_HW_INVOKE ((uint32_t)0x70000000) - -#define BSL_CONFIG_HW_INVOKE_PORT1 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PORT2 ((uint32_t)0x00000001) -#define BSL_CONFIG_HW_INVOKE_PORT3 ((uint32_t)0x00000002) - -#define BSL_CONFIG_HW_INVOKE_PIN0 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN1 ((uint32_t)0x00000010) -#define BSL_CONFIG_HW_INVOKE_PIN2 ((uint32_t)0x00000020) -#define BSL_CONFIG_HW_INVOKE_PIN3 ((uint32_t)0x00000030) -#define BSL_CONFIG_HW_INVOKE_PIN4 ((uint32_t)0x00000040) -#define BSL_CONFIG_HW_INVOKE_PIN5 ((uint32_t)0x00000050) -#define BSL_CONFIG_HW_INVOKE_PIN6 ((uint32_t)0x00000060) -#define BSL_CONFIG_HW_INVOKE_PIN7 ((uint32_t)0x00000070) - -#define BSL_CONFIG_HW_INVOKE_PIN_LOW ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN_HIGH ((uint32_t)0x00001000) - -#define BSL_CONFIG_INTERFACE_I2C ((uint32_t)0x00008000) -#define BSL_CONFIG_INTERFACE_SPI ((uint32_t)0x0000A000) -#define BSL_CONFIG_INTERFACE_UART ((uint32_t)0x0000C000) -#define BSL_CONFIG_INTERFACE_AUTO ((uint32_t)0x0000E000) - -#define BSL_CONFIG_I2C_ADD_OFFSET (16) - - -/****************************************************************************** -* ULP Advisor * -******************************************************************************/ -#ifdef __TI_ARM__ -#pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8}) -#pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8}) -#pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8}) -#pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8}) -#pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8}) -#pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8}) -#pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8}) -#pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8}) -#pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8}) -#pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8}) -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* __MSP432P411Y_H__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p4xx.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p4xx.h deleted file mode 100644 index e7ab903c0eb..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp432p4xx.h +++ /dev/null @@ -1,7988 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2012 - 17 Texas Instruments Incorporated - http://www.ti.com/ -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* -* Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the -* distribution. -* -* Neither the name of Texas Instruments Incorporated nor the names of -* its contributors may be used to endorse or promote products derived -* from this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* -* MSP432P4XX Register Definitions -* -* This file includes CMSIS compliant component and register definitions -* -* For legacy components the definitions that are compatible with MSP430 code, -* are included with msp432p4xx_classic.h -* -* With CMSIS definitions, the register defines have been reformatted: -* ModuleName[ModuleInstance]->RegisterName -* -* Writing to CMSIS bit fields can be done through register level -* or via bitband area access: -* - ADC14->CTL0 |= ADC14_CTL0_ENC; -* - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1; -* -* File creation date: 2017-08-03 -* -******************************************************************************/ - -#ifndef __MSP432P4XX_H__ -#define __MSP432P4XX_H__ - -/* Use standard integer types with explicit width */ -#include - -#ifdef __cplusplus - extern "C" { -#endif - -#define __MSP432_HEADER_VERSION__ 3.202 - -/* WARNING: The msp432p4xx.h file is indented to be used to rebuild TI Drivers for MSP432 MCUs. Do not use this file to build target code.*/ - -/* Remap MSP432 intrinsics to ARM equivalents */ -#include "msp_compatibility.h" - -#ifndef __CMSIS_CONFIG__ -#define __CMSIS_CONFIG__ - -/** @addtogroup MSP432P4XX_Definitions MSP432P4XX Definitions - This file defines all structures and symbols for MSP432P4XX: - - components and registers - - peripheral base address - - peripheral ID - - Peripheral definitions - @{ -*/ - -/****************************************************************************** -* Processor and Core Peripherals * -******************************************************************************/ -/** @addtogroup MSP432P4XX_CMSIS Device CMSIS Definitions - Configuration of the Cortex-M4 Processor and Core Peripherals - @{ -*/ - -/****************************************************************************** -* CMSIS-compatible Interrupt Number Definition * -******************************************************************************/ -typedef enum IRQn -{ - /* Cortex-M4 Processor Exceptions Numbers */ - NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ - BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /* 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /* 15 System Tick Interrupt */ - /* Peripheral Exceptions Numbers */ - PSS_IRQn = 0, /* 16 PSS Interrupt */ - CS_IRQn = 1, /* 17 CS Interrupt */ - PCM_IRQn = 2, /* 18 PCM Interrupt */ - WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */ - FPU_IRQn = 4, /* 20 FPU Interrupt */ - FLCTL_IRQn = 5, /* 21 Flash Controller Interrupt*/ - COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */ - COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */ - TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */ - TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */ - TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */ - TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */ - TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */ - TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */ - TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */ - TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */ - EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */ - EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */ - EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */ - EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */ - EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */ - EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */ - EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */ - EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */ - ADC14_IRQn = 24, /* 40 ADC14 Interrupt */ - T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */ - T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */ - T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */ - AES256_IRQn = 28, /* 44 AES256 Interrupt */ - RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */ - DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */ - DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */ - DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */ - DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */ - DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */ - PORT1_IRQn = 35, /* 51 Port1 Interrupt */ - PORT2_IRQn = 36, /* 52 Port2 Interrupt */ - PORT3_IRQn = 37, /* 53 Port3 Interrupt */ - PORT4_IRQn = 38, /* 54 Port4 Interrupt */ - PORT5_IRQn = 39, /* 55 Port5 Interrupt */ - FLCTL_A_IRQn = 5, /* 21 Flash Controller Interrupt*/ - PORT6_IRQn = 40, /* 56 Port6 Interrupt */ - LCD_F_IRQn = 41 /* 57 LCD_F Interrupt */ -} IRQn_Type; - -/****************************************************************************** -* Processor and Core Peripheral Section * -******************************************************************************/ -#define __CM4_REV 0x0001 /* Core revision r0p1 */ -#define __MPU_PRESENT 1 /* MPU present or not */ -#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /* FPU present or not */ - -/****************************************************************************** -* Available Peripherals * -******************************************************************************/ -#define __MCU_HAS_ADC14__ /*!< Module ADC14 is available */ -#define __MCU_HAS_AES256__ /*!< Module AES256 is available */ -#define __MCU_HAS_CAPTIO0__ /*!< Module CAPTIO0 is available */ -#define __MCU_HAS_CAPTIO1__ /*!< Module CAPTIO1 is available */ -#define __MCU_HAS_COMP_E0__ /*!< Module COMP_E0 is available */ -#define __MCU_HAS_COMP_E1__ /*!< Module COMP_E1 is available */ -#define __MCU_HAS_CRC32__ /*!< Module CRC32 is available */ -#define __MCU_HAS_CS__ /*!< Module CS is available */ -#define __MCU_HAS_DIO__ /*!< Module DIO is available */ -#define __MCU_HAS_DMA__ /*!< Module DMA is available */ -#define __MCU_HAS_EUSCI_A0__ /*!< Module EUSCI_A0 is available */ -#define __MCU_HAS_EUSCI_A1__ /*!< Module EUSCI_A1 is available */ -#define __MCU_HAS_EUSCI_A2__ /*!< Module EUSCI_A2 is available */ -#define __MCU_HAS_EUSCI_A3__ /*!< Module EUSCI_A3 is available */ -#define __MCU_HAS_EUSCI_B0__ /*!< Module EUSCI_B0 is available */ -#define __MCU_HAS_EUSCI_B1__ /*!< Module EUSCI_B1 is available */ -#define __MCU_HAS_EUSCI_B2__ /*!< Module EUSCI_B2 is available */ -#define __MCU_HAS_EUSCI_B3__ /*!< Module EUSCI_B3 is available */ -#define __MCU_HAS_FLCTL__ /*!< Module FLCTL is available */ -#define __MCU_HAS_FL_BOOTOVER_MAILBOX__ /*!< Module FL_BOOTOVER_MAILBOX is available */ -#define __MCU_HAS_PCM__ /*!< Module PCM is available */ -#define __MCU_HAS_PMAP__ /*!< Module PMAP is available */ -#define __MCU_HAS_PSS__ /*!< Module PSS is available */ -#define __MCU_HAS_REF_A__ /*!< Module REF_A is available */ -#define __MCU_HAS_RSTCTL__ /*!< Module RSTCTL is available */ -#define __MCU_HAS_RTC_C__ /*!< Module RTC_C is available */ -#define __MCU_HAS_SYSCTL__ /*!< Module SYSCTL is available */ -#define __MCU_HAS_TIMER32__ /*!< Module TIMER32 is available */ -#define __MCU_HAS_TIMER_A0__ /*!< Module TIMER_A0 is available */ -#define __MCU_HAS_TIMER_A1__ /*!< Module TIMER_A1 is available */ -#define __MCU_HAS_TIMER_A2__ /*!< Module TIMER_A2 is available */ -#define __MCU_HAS_TIMER_A3__ /*!< Module TIMER_A3 is available */ -#define __MCU_HAS_TLV__ /*!< Module TLV is available */ -#define __MCU_HAS_WDT_A__ /*!< Module WDT_A is available */ -#define __MCU_HAS_FLCTL_A__ /*!< Module FLCTL_A is available */ -#define __MCU_HAS_LCD_F__ /*!< Module LCD_F is available */ -#define __MCU_HAS_SYSCTL_A__ /*!< Module SYSCTL_A is available */ - -#define __MSP432_HAS_PORTA_R__ -#define __MSP432_HAS_PORTB_R__ -#define __MSP432_HAS_PORTC_R__ -#define __MSP432_HAS_PORTD_R__ -#define __MSP432_HAS_PORTE_R__ -#define __MSP432_HAS_PORTJ_R__ -#define __MSP432_HAS_PORT1_R__ -#define __MSP432_HAS_PORT2_R__ -#define __MSP432_HAS_PORT3_R__ -#define __MSP432_HAS_PORT4_R__ -#define __MSP432_HAS_PORT5_R__ -#define __MSP432_HAS_PORT6_R__ -#define __MSP432_HAS_PORT7_R__ -#define __MSP432_HAS_PORT8_R__ -#define __MSP432_HAS_PORT9_R__ -#define __MSP432_HAS_PORT10_R__ - - -/*@}*/ /* end of group MSP432P4XX_CMSIS */ - -/* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */ -#ifdef __TI_ARM__ -/* disable the TI ULP advisor check for the core header file definitions */ -#pragma diag_push -#pragma CHECK_ULP("none") -#include "core_cm4.h" -#pragma diag_pop -#else -#include "core_cm4.h" -#endif - -/* System Header */ -#include "system_msp432p401r.h" - -/****************************************************************************** -* Definition of standard bits * -******************************************************************************/ -#define BIT0 (uint16_t)(0x0001) -#define BIT1 (uint16_t)(0x0002) -#define BIT2 (uint16_t)(0x0004) -#define BIT3 (uint16_t)(0x0008) -#define BIT4 (uint16_t)(0x0010) -#define BIT5 (uint16_t)(0x0020) -#define BIT6 (uint16_t)(0x0040) -#define BIT7 (uint16_t)(0x0080) -#define BIT8 (uint16_t)(0x0100) -#define BIT9 (uint16_t)(0x0200) -#define BITA (uint16_t)(0x0400) -#define BITB (uint16_t)(0x0800) -#define BITC (uint16_t)(0x1000) -#define BITD (uint16_t)(0x2000) -#define BITE (uint16_t)(0x4000) -#define BITF (uint16_t)(0x8000) - -/****************************************************************************** -* Device and peripheral memory map * -******************************************************************************/ -/** @addtogroup MSP432P4XX_MemoryMap MSP432P4XX Memory Mapping - @{ -*/ - -#define FLASH_BASE ((uint32_t)0x00000000) /*!< Main Flash memory start address */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM memory start address */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripherals start address */ -#define PERIPH_BASE2 ((uint32_t)0xE0000000) /*!< Peripherals start address */ -#define ADC14_BASE (PERIPH_BASE +0x00012000) /*!< Base address of module ADC14 registers */ -#define AES256_BASE (PERIPH_BASE +0x00003C00) /*!< Base address of module AES256 registers */ -#define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /*!< Base address of module CAPTIO0 registers */ -#define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /*!< Base address of module CAPTIO1 registers */ -#define COMP_E0_BASE (PERIPH_BASE +0x00003400) /*!< Base address of module COMP_E0 registers */ -#define COMP_E1_BASE (PERIPH_BASE +0x00003800) /*!< Base address of module COMP_E1 registers */ -#define CRC32_BASE (PERIPH_BASE +0x00004000) /*!< Base address of module CRC32 registers */ -#define CS_BASE (PERIPH_BASE +0x00010400) /*!< Base address of module CS registers */ -#define DIO_BASE (PERIPH_BASE +0x00004C00) /*!< Base address of module DIO registers */ -#define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address of module DMA registers */ -#define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ -#define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ -#define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ -#define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ -#define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ -#define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ -#define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ -#define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ -#define FLCTL_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL registers */ -#define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000) /*!< Base address of module FL_BOOTOVER_MAILBOX registers */ -#define PCM_BASE (PERIPH_BASE +0x00010000) /*!< Base address of module PCM registers */ -#define PMAP_BASE (PERIPH_BASE +0x00005000) /*!< Base address of module PMAP registers */ -#define PSS_BASE (PERIPH_BASE +0x00010800) /*!< Base address of module PSS registers */ -#define REF_A_BASE (PERIPH_BASE +0x00003000) /*!< Base address of module REF_A registers */ -#define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /*!< Base address of module RSTCTL registers */ -#define RTC_C_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ -#define SYSCTL_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL registers */ -#define TIMER32_BASE (PERIPH_BASE +0x0000C000) /*!< Base address of module TIMER32 registers */ -#define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /*!< Base address of module TIMER_A0 registers */ -#define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /*!< Base address of module TIMER_A1 registers */ -#define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /*!< Base address of module TIMER_A2 registers */ -#define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /*!< Base address of module TIMER_A3 registers */ -#define TLV_BASE ((uint32_t)0x00201000) /*!< Base address of module TLV registers */ -#define WDT_A_BASE (PERIPH_BASE +0x00004800) /*!< Base address of module WDT_A registers */ -#define TLV_START_ADDR (TLV_BASE + 0x0004) /*!< Start Address of the TLV structure */ -#define FLCTL_A_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL_A registers */ -#define LCD_F_BASE (PERIPH_BASE +0x00012400) /*!< Base address of module LCD_F registers */ -#define SYSCTL_A_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL_A registers */ - - - -/*@}*/ /* end of group MSP432P4XX_MemoryMap */ - -/****************************************************************************** -* Definitions for bit band access * -******************************************************************************/ -#define BITBAND_SRAM_BASE ((uint32_t)(0x22000000)) -#define BITBAND_PERI_BASE ((uint32_t)(0x42000000)) - -/* SRAM allows 32 bit bit band access */ -#define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4))) -/* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */ -#define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4))) - -/****************************************************************************** -* Peripheral register definitions * -******************************************************************************/ -/** @addtogroup MSP432P4XX_Peripherals MSP432P4XX Peripherals - MSP432P4XX Device Specific Peripheral registers structures - @{ -*/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - - - -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t LO0; /*!< Window Comparator Low Threshold 0 Register */ - __IO uint32_t HI0; /*!< Window Comparator High Threshold 0 Register */ - __IO uint32_t LO1; /*!< Window Comparator Low Threshold 1 Register */ - __IO uint32_t HI1; /*!< Window Comparator High Threshold 1 Register */ - __IO uint32_t MCTL[32]; /*!< Conversion Memory Control Register */ - __IO uint32_t MEM[32]; /*!< Conversion Memory Register */ - uint32_t RESERVED0[9]; - __IO uint32_t IER0; /*!< Interrupt Enable 0 Register */ - __IO uint32_t IER1; /*!< Interrupt Enable 1 Register */ - __I uint32_t IFGR0; /*!< Interrupt Flag 0 Register */ - __I uint32_t IFGR1; /*!< Interrupt Flag 1 Register */ - __O uint32_t CLRIFGR0; /*!< Clear Interrupt Flag 0 Register */ - __IO uint32_t CLRIFGR1; /*!< Clear Interrupt Flag 1 Register */ - __IO uint32_t IV; /*!< Interrupt Vector Register */ -} ADC14_Type; - -typedef struct { - __IO uint16_t CTL0; /*!< AES Accelerator Control Register 0 */ - __IO uint16_t CTL1; /*!< AES Accelerator Control Register 1 */ - __IO uint16_t STAT; /*!< AES Accelerator Status Register */ - __O uint16_t KEY; /*!< AES Accelerator Key Register */ - __O uint16_t DIN; /*!< AES Accelerator Data In Register */ - __O uint16_t DOUT; /*!< AES Accelerator Data Out Register */ - __O uint16_t XDIN; /*!< AES Accelerator XORed Data In Register */ - __O uint16_t XIN; /*!< AES Accelerator XORed Data In Register */ -} AES256_Type; - -typedef struct { - uint16_t RESERVED0[7]; - __IO uint16_t CTL; /*!< Capacitive Touch IO x Control Register */ -} CAPTIO_Type; - -typedef struct { - __IO uint16_t CTL0; /*!< Comparator Control Register 0 */ - __IO uint16_t CTL1; /*!< Comparator Control Register 1 */ - __IO uint16_t CTL2; /*!< Comparator Control Register 2 */ - __IO uint16_t CTL3; /*!< Comparator Control Register 3 */ - uint16_t RESERVED0[2]; - __IO uint16_t INT; /*!< Comparator Interrupt Control Register */ - __I uint16_t IV; /*!< Comparator Interrupt Vector Word Register */ -} COMP_E_Type; - -typedef struct { - __IO uint16_t DI32; /*!< Data Input for CRC32 Signature Computation */ - uint16_t RESERVED0; - __IO uint16_t DIRB32; /*!< Data In Reverse for CRC32 Computation */ - uint16_t RESERVED1; - __IO uint16_t INIRES32_LO; /*!< CRC32 Initialization and Result, lower 16 bits */ - __IO uint16_t INIRES32_HI; /*!< CRC32 Initialization and Result, upper 16 bits */ - __IO uint16_t RESR32_LO; /*!< CRC32 Result Reverse, lower 16 bits */ - __IO uint16_t RESR32_HI; /*!< CRC32 Result Reverse, Upper 16 bits */ - __IO uint16_t DI16; /*!< Data Input for CRC16 computation */ - uint16_t RESERVED2; - __IO uint16_t DIRB16; /*!< CRC16 Data In Reverse */ - uint16_t RESERVED3; - __IO uint16_t INIRES16; /*!< CRC16 Initialization and Result register */ - uint16_t RESERVED4[2]; - __IO uint16_t RESR16; /*!< CRC16 Result Reverse */ -} CRC32_Type; - -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t CTL2; /*!< Control 2 Register */ - __IO uint32_t CTL3; /*!< Control 3 Register */ - uint32_t RESERVED0[7]; - __IO uint32_t CLKEN; /*!< Clock Enable Register */ - __I uint32_t STAT; /*!< Status Register */ - uint32_t RESERVED1[2]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - uint32_t RESERVED2; - __I uint32_t IFG; /*!< Interrupt Flag Register */ - uint32_t RESERVED3; - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - uint32_t RESERVED4; - __O uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - uint32_t RESERVED5; - __IO uint32_t DCOERCAL0; /*!< DCO External Resistor Cailbration 0 Register */ - __IO uint32_t DCOERCAL1; /*!< DCO External Resistor Calibration 1 Register */ -} CS_Type; - -typedef struct { - uint8_t RESERVED0; - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED1; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED2; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED3; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED4; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED5; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED6; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED7[9]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ - __I uint16_t IV; /*!< Port Interrupt Vector Value */ -} DIO_PORT_Even_Interruptable_Type; - -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - __I uint16_t IV_L; /*!< Low Port Interrupt Vector Value */ - uint16_t RESERVED0[3]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; - union { - __IO uint16_t IES; /*!< Port Pair Interrupt Edge Select */ - struct { - __IO uint8_t IES_L; /*!< Low Port Interrupt Edge Select */ - __IO uint8_t IES_H; /*!< High Port Interrupt Edge Select */ - }; - }; - union { - __IO uint16_t IE; /*!< Port Pair Interrupt Enable */ - struct { - __IO uint8_t IE_L; /*!< Low Port Interrupt Enable */ - __IO uint8_t IE_H; /*!< High Port Interrupt Enable */ - }; - }; - union { - __IO uint16_t IFG; /*!< Port Pair Interrupt Flag */ - struct { - __IO uint8_t IFG_L; /*!< Low Port Interrupt Flag */ - __IO uint8_t IFG_H; /*!< High Port Interrupt Flag */ - }; - }; - __I uint16_t IV_H; /*!< High Port Interrupt Vector Value */ -} DIO_PORT_Interruptable_Type; - -typedef struct { - union { - __I uint16_t IN; /*!< Port Pair Input */ - struct { - __I uint8_t IN_L; /*!< Low Port Input */ - __I uint8_t IN_H; /*!< High Port Input */ - }; - }; - union { - __IO uint16_t OUT; /*!< Port Pair Output */ - struct { - __IO uint8_t OUT_L; /*!< Low Port Output */ - __IO uint8_t OUT_H; /*!< High Port Output */ - }; - }; - union { - __IO uint16_t DIR; /*!< Port Pair Direction */ - struct { - __IO uint8_t DIR_L; /*!< Low Port Direction */ - __IO uint8_t DIR_H; /*!< High Port Direction */ - }; - }; - union { - __IO uint16_t REN; /*!< Port Pair Resistor Enable */ - struct { - __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ - __IO uint8_t REN_H; /*!< High Port Resistor Enable */ - }; - }; - union { - __IO uint16_t DS; /*!< Port Pair Drive Strength */ - struct { - __IO uint8_t DS_L; /*!< Low Port Drive Strength */ - __IO uint8_t DS_H; /*!< High Port Drive Strength */ - }; - }; - union { - __IO uint16_t SEL0; /*!< Port Pair Select 0 */ - struct { - __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ - __IO uint8_t SEL0_H; /*!< High Port Select 0 */ - }; - }; - union { - __IO uint16_t SEL1; /*!< Port Pair Select 1 */ - struct { - __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ - __IO uint8_t SEL1_H; /*!< High Port Select 1 */ - }; - }; - uint16_t RESERVED0[4]; - union { - __IO uint16_t SELC; /*!< Port Pair Complement Select */ - struct { - __IO uint8_t SELC_L; /*!< Low Port Complement Select */ - __IO uint8_t SELC_H; /*!< High Port Complement Select */ - }; - }; -} DIO_PORT_Not_Interruptable_Type; - -typedef struct { - __I uint8_t IN; /*!< Port Input */ - uint8_t RESERVED0; - __IO uint8_t OUT; /*!< Port Output */ - uint8_t RESERVED1; - __IO uint8_t DIR; /*!< Port Direction */ - uint8_t RESERVED2; - __IO uint8_t REN; /*!< Port Resistor Enable */ - uint8_t RESERVED3; - __IO uint8_t DS; /*!< Port Drive Strength */ - uint8_t RESERVED4; - __IO uint8_t SEL0; /*!< Port Select 0 */ - uint8_t RESERVED5; - __IO uint8_t SEL1; /*!< Port Select 1 */ - uint8_t RESERVED6; - __I uint16_t IV; /*!< Port Interrupt Vector Value */ - uint8_t RESERVED7[6]; - __IO uint8_t SELC; /*!< Port Complement Select */ - uint8_t RESERVED8; - __IO uint8_t IES; /*!< Port Interrupt Edge Select */ - uint8_t RESERVED9; - __IO uint8_t IE; /*!< Port Interrupt Enable */ - uint8_t RESERVED10; - __IO uint8_t IFG; /*!< Port Interrupt Flag */ -} DIO_PORT_Odd_Interruptable_Type; - -typedef struct { - __I uint32_t DEVICE_CFG; /*!< Device Configuration Status */ - __IO uint32_t SW_CHTRIG; /*!< Software Channel Trigger Register */ - uint32_t RESERVED0[2]; - __IO uint32_t CH_SRCCFG[32]; /*!< Channel n Source Configuration Register */ - uint32_t RESERVED1[28]; - __IO uint32_t INT1_SRCCFG; /*!< Interrupt 1 Source Channel Configuration */ - __IO uint32_t INT2_SRCCFG; /*!< Interrupt 2 Source Channel Configuration Register */ - __IO uint32_t INT3_SRCCFG; /*!< Interrupt 3 Source Channel Configuration Register */ - uint32_t RESERVED2; - __I uint32_t INT0_SRCFLG; /*!< Interrupt 0 Source Channel Flag Register */ - __O uint32_t INT0_CLRFLG; /*!< Interrupt 0 Source Channel Clear Flag Register */ -} DMA_Channel_Type; - -typedef struct { - __I uint32_t STAT; /*!< Status Register */ - __O uint32_t CFG; /*!< Configuration Register */ - __IO uint32_t CTLBASE; /*!< Channel Control Data Base Pointer Register */ - __I uint32_t ALTBASE; /*!< Channel Alternate Control Data Base Pointer Register */ - __I uint32_t WAITSTAT; /*!< Channel Wait on Request Status Register */ - __O uint32_t SWREQ; /*!< Channel Software Request Register */ - __IO uint32_t USEBURSTSET; /*!< Channel Useburst Set Register */ - __O uint32_t USEBURSTCLR; /*!< Channel Useburst Clear Register */ - __IO uint32_t REQMASKSET; /*!< Channel Request Mask Set Register */ - __O uint32_t REQMASKCLR; /*!< Channel Request Mask Clear Register */ - __IO uint32_t ENASET; /*!< Channel Enable Set Register */ - __O uint32_t ENACLR; /*!< Channel Enable Clear Register */ - __IO uint32_t ALTSET; /*!< Channel Primary-Alternate Set Register */ - __O uint32_t ALTCLR; /*!< Channel Primary-Alternate Clear Register */ - __IO uint32_t PRIOSET; /*!< Channel Priority Set Register */ - __O uint32_t PRIOCLR; /*!< Channel Priority Clear Register */ - uint32_t RESERVED4[3]; - __IO uint32_t ERRCLR; /*!< Bus Error Clear Register */ -} DMA_Control_Type; - -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Ax Bit Rate Control Register 1 */ - uint16_t RESERVED1; - __IO uint16_t STATW; - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - uint16_t RESERVED2[5]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_SPI_Type; - -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Ax Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Ax Baud Rate Control Word Register */ - __IO uint16_t MCTLW; /*!< eUSCI_Ax Modulation Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Ax Status Register */ - __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ - __IO uint16_t ABCTL; /*!< eUSCI_Ax Auto Baud Rate Control Register */ - __IO uint16_t IRCTL; /*!< eUSCI_Ax IrDA Control Word Register */ - uint16_t RESERVED1[3]; - __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ -} EUSCI_A_Type; - -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - uint16_t RESERVED0[2]; - __IO uint16_t BRW; /*!< eUSCI_Bx Bit Rate Control Register 1 */ - __IO uint16_t STATW; - uint16_t RESERVED1; - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED2[13]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_SPI_Type; - -typedef struct { - __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ - __IO uint16_t CTLW1; /*!< eUSCI_Bx Control Word Register 1 */ - uint16_t RESERVED0; - __IO uint16_t BRW; /*!< eUSCI_Bx Baud Rate Control Word Register */ - __IO uint16_t STATW; /*!< eUSCI_Bx Status Register */ - __IO uint16_t TBCNT; /*!< eUSCI_Bx Byte Counter Threshold Register */ - __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ - __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ - uint16_t RESERVED1[2]; - __IO uint16_t I2COA0; /*!< eUSCI_Bx I2C Own Address 0 Register */ - __IO uint16_t I2COA1; /*!< eUSCI_Bx I2C Own Address 1 Register */ - __IO uint16_t I2COA2; /*!< eUSCI_Bx I2C Own Address 2 Register */ - __IO uint16_t I2COA3; /*!< eUSCI_Bx I2C Own Address 3 Register */ - __I uint16_t ADDRX; /*!< eUSCI_Bx I2C Received Address Register */ - __IO uint16_t ADDMASK; /*!< eUSCI_Bx I2C Address Mask Register */ - __IO uint16_t I2CSA; /*!< eUSCI_Bx I2C Slave Address Register */ - uint16_t RESERVED2[4]; - __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ - __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ - __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ -} EUSCI_B_Type; - -typedef struct { - __I uint32_t POWER_STAT; /*!< Power Status Register */ - uint32_t RESERVED0[3]; - __IO uint32_t BANK0_RDCTL; /*!< Bank0 Read Control Register */ - __IO uint32_t BANK1_RDCTL; /*!< Bank1 Read Control Register */ - uint32_t RESERVED1[2]; - __IO uint32_t RDBRST_CTLSTAT; /*!< Read Burst/Compare Control and Status Register */ - __IO uint32_t RDBRST_STARTADDR; /*!< Read Burst/Compare Start Address Register */ - __IO uint32_t RDBRST_LEN; /*!< Read Burst/Compare Length Register */ - uint32_t RESERVED2[4]; - __IO uint32_t RDBRST_FAILADDR; /*!< Read Burst/Compare Fail Address Register */ - __IO uint32_t RDBRST_FAILCNT; /*!< Read Burst/Compare Fail Count Register */ - uint32_t RESERVED3[3]; - __IO uint32_t PRG_CTLSTAT; /*!< Program Control and Status Register */ - __IO uint32_t PRGBRST_CTLSTAT; /*!< Program Burst Control and Status Register */ - __IO uint32_t PRGBRST_STARTADDR; /*!< Program Burst Start Address Register */ - uint32_t RESERVED4; - __IO uint32_t PRGBRST_DATA0_0; /*!< Program Burst Data0 Register0 */ - __IO uint32_t PRGBRST_DATA0_1; /*!< Program Burst Data0 Register1 */ - __IO uint32_t PRGBRST_DATA0_2; /*!< Program Burst Data0 Register2 */ - __IO uint32_t PRGBRST_DATA0_3; /*!< Program Burst Data0 Register3 */ - __IO uint32_t PRGBRST_DATA1_0; /*!< Program Burst Data1 Register0 */ - __IO uint32_t PRGBRST_DATA1_1; /*!< Program Burst Data1 Register1 */ - __IO uint32_t PRGBRST_DATA1_2; /*!< Program Burst Data1 Register2 */ - __IO uint32_t PRGBRST_DATA1_3; /*!< Program Burst Data1 Register3 */ - __IO uint32_t PRGBRST_DATA2_0; /*!< Program Burst Data2 Register0 */ - __IO uint32_t PRGBRST_DATA2_1; /*!< Program Burst Data2 Register1 */ - __IO uint32_t PRGBRST_DATA2_2; /*!< Program Burst Data2 Register2 */ - __IO uint32_t PRGBRST_DATA2_3; /*!< Program Burst Data2 Register3 */ - __IO uint32_t PRGBRST_DATA3_0; /*!< Program Burst Data3 Register0 */ - __IO uint32_t PRGBRST_DATA3_1; /*!< Program Burst Data3 Register1 */ - __IO uint32_t PRGBRST_DATA3_2; /*!< Program Burst Data3 Register2 */ - __IO uint32_t PRGBRST_DATA3_3; /*!< Program Burst Data3 Register3 */ - __IO uint32_t ERASE_CTLSTAT; /*!< Erase Control and Status Register */ - __IO uint32_t ERASE_SECTADDR; /*!< Erase Sector Address Register */ - uint32_t RESERVED5[2]; - __IO uint32_t BANK0_INFO_WEPROT; /*!< Information Memory Bank0 Write/Erase Protection Register */ - __IO uint32_t BANK0_MAIN_WEPROT; /*!< Main Memory Bank0 Write/Erase Protection Register */ - uint32_t RESERVED6[2]; - __IO uint32_t BANK1_INFO_WEPROT; /*!< Information Memory Bank1 Write/Erase Protection Register */ - __IO uint32_t BANK1_MAIN_WEPROT; /*!< Main Memory Bank1 Write/Erase Protection Register */ - uint32_t RESERVED7[2]; - __IO uint32_t BMRK_CTLSTAT; /*!< Benchmark Control and Status Register */ - __IO uint32_t BMRK_IFETCH; /*!< Benchmark Instruction Fetch Count Register */ - __IO uint32_t BMRK_DREAD; /*!< Benchmark Data Read Count Register */ - __IO uint32_t BMRK_CMP; /*!< Benchmark Count Compare Register */ - uint32_t RESERVED8[4]; - __IO uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - __IO uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - __I uint32_t READ_TIMCTL; /*!< Read Timing Control Register */ - __I uint32_t READMARGIN_TIMCTL; /*!< Read Margin Timing Control Register */ - __I uint32_t PRGVER_TIMCTL; /*!< Program Verify Timing Control Register */ - __I uint32_t ERSVER_TIMCTL; /*!< Erase Verify Timing Control Register */ - __I uint32_t LKGVER_TIMCTL; /*!< Leakage Verify Timing Control Register */ - __I uint32_t PROGRAM_TIMCTL; /*!< Program Timing Control Register */ - __I uint32_t ERASE_TIMCTL; /*!< Erase Timing Control Register */ - __I uint32_t MASSERASE_TIMCTL; /*!< Mass Erase Timing Control Register */ - __I uint32_t BURSTPRG_TIMCTL; /*!< Burst Program Timing Control Register */ - uint32_t RESERVED9[55]; - __IO uint32_t BANK0_MAIN_WEPROT0; /*!< Main Memory Bank0 Write/Erase Protection Register 0 */ - __IO uint32_t BANK0_MAIN_WEPROT1; /*!< Main Memory Bank0 Write/Erase Protection Register 1 */ - __IO uint32_t BANK0_MAIN_WEPROT2; /*!< Main Memory Bank0 Write/Erase Protection Register 2 */ - __IO uint32_t BANK0_MAIN_WEPROT3; /*!< Main Memory Bank0 Write/Erase Protection Register 3 */ - __IO uint32_t BANK0_MAIN_WEPROT4; /*!< Main Memory Bank0 Write/Erase Protection Register 4 */ - __IO uint32_t BANK0_MAIN_WEPROT5; /*!< Main Memory Bank0 Write/Erase Protection Register 5 */ - __IO uint32_t BANK0_MAIN_WEPROT6; /*!< Main Memory Bank0 Write/Erase Protection Register 6 */ - __IO uint32_t BANK0_MAIN_WEPROT7; /*!< Main Memory Bank0 Write/Erase Protection Register 7 */ - uint32_t RESERVED10[8]; - __IO uint32_t BANK1_MAIN_WEPROT0; /*!< Main Memory Bank1 Write/Erase Protection Register 0 */ - __IO uint32_t BANK1_MAIN_WEPROT1; /*!< Main Memory Bank1 Write/Erase Protection Register 1 */ - __IO uint32_t BANK1_MAIN_WEPROT2; /*!< Main Memory Bank1 Write/Erase Protection Register 2 */ - __IO uint32_t BANK1_MAIN_WEPROT3; /*!< Main Memory Bank1 Write/Erase Protection Register 3 */ - __IO uint32_t BANK1_MAIN_WEPROT4; /*!< Main Memory Bank1 Write/Erase Protection Register 4 */ - __IO uint32_t BANK1_MAIN_WEPROT5; /*!< Main Memory Bank1 Write/Erase Protection Register 5 */ - __IO uint32_t BANK1_MAIN_WEPROT6; /*!< Main Memory Bank1 Write/Erase Protection Register 6 */ - __IO uint32_t BANK1_MAIN_WEPROT7; /*!< Main Memory Bank1 Write/Erase Protection Register 7 */ -} FLCTL_A_Type; - -typedef struct { - __I uint32_t POWER_STAT; /*!< Power Status Register */ - uint32_t RESERVED0[3]; - __IO uint32_t BANK0_RDCTL; /*!< Bank0 Read Control Register */ - __IO uint32_t BANK1_RDCTL; /*!< Bank1 Read Control Register */ - uint32_t RESERVED1[2]; - __IO uint32_t RDBRST_CTLSTAT; /*!< Read Burst/Compare Control and Status Register */ - __IO uint32_t RDBRST_STARTADDR; /*!< Read Burst/Compare Start Address Register */ - __IO uint32_t RDBRST_LEN; /*!< Read Burst/Compare Length Register */ - uint32_t RESERVED2[4]; - __IO uint32_t RDBRST_FAILADDR; /*!< Read Burst/Compare Fail Address Register */ - __IO uint32_t RDBRST_FAILCNT; /*!< Read Burst/Compare Fail Count Register */ - uint32_t RESERVED3[3]; - __IO uint32_t PRG_CTLSTAT; /*!< Program Control and Status Register */ - __IO uint32_t PRGBRST_CTLSTAT; /*!< Program Burst Control and Status Register */ - __IO uint32_t PRGBRST_STARTADDR; /*!< Program Burst Start Address Register */ - uint32_t RESERVED4; - __IO uint32_t PRGBRST_DATA0_0; /*!< Program Burst Data0 Register0 */ - __IO uint32_t PRGBRST_DATA0_1; /*!< Program Burst Data0 Register1 */ - __IO uint32_t PRGBRST_DATA0_2; /*!< Program Burst Data0 Register2 */ - __IO uint32_t PRGBRST_DATA0_3; /*!< Program Burst Data0 Register3 */ - __IO uint32_t PRGBRST_DATA1_0; /*!< Program Burst Data1 Register0 */ - __IO uint32_t PRGBRST_DATA1_1; /*!< Program Burst Data1 Register1 */ - __IO uint32_t PRGBRST_DATA1_2; /*!< Program Burst Data1 Register2 */ - __IO uint32_t PRGBRST_DATA1_3; /*!< Program Burst Data1 Register3 */ - __IO uint32_t PRGBRST_DATA2_0; /*!< Program Burst Data2 Register0 */ - __IO uint32_t PRGBRST_DATA2_1; /*!< Program Burst Data2 Register1 */ - __IO uint32_t PRGBRST_DATA2_2; /*!< Program Burst Data2 Register2 */ - __IO uint32_t PRGBRST_DATA2_3; /*!< Program Burst Data2 Register3 */ - __IO uint32_t PRGBRST_DATA3_0; /*!< Program Burst Data3 Register0 */ - __IO uint32_t PRGBRST_DATA3_1; /*!< Program Burst Data3 Register1 */ - __IO uint32_t PRGBRST_DATA3_2; /*!< Program Burst Data3 Register2 */ - __IO uint32_t PRGBRST_DATA3_3; /*!< Program Burst Data3 Register3 */ - __IO uint32_t ERASE_CTLSTAT; /*!< Erase Control and Status Register */ - __IO uint32_t ERASE_SECTADDR; /*!< Erase Sector Address Register */ - uint32_t RESERVED5[2]; - __IO uint32_t BANK0_INFO_WEPROT; /*!< Information Memory Bank0 Write/Erase Protection Register */ - __IO uint32_t BANK0_MAIN_WEPROT; /*!< Main Memory Bank0 Write/Erase Protection Register */ - uint32_t RESERVED6[2]; - __IO uint32_t BANK1_INFO_WEPROT; /*!< Information Memory Bank1 Write/Erase Protection Register */ - __IO uint32_t BANK1_MAIN_WEPROT; /*!< Main Memory Bank1 Write/Erase Protection Register */ - uint32_t RESERVED7[2]; - __IO uint32_t BMRK_CTLSTAT; /*!< Benchmark Control and Status Register */ - __IO uint32_t BMRK_IFETCH; /*!< Benchmark Instruction Fetch Count Register */ - __IO uint32_t BMRK_DREAD; /*!< Benchmark Data Read Count Register */ - __IO uint32_t BMRK_CMP; /*!< Benchmark Count Compare Register */ - uint32_t RESERVED8[4]; - __IO uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ - __IO uint32_t SETIFG; /*!< Set Interrupt Flag Register */ - __I uint32_t READ_TIMCTL; /*!< Read Timing Control Register */ - __I uint32_t READMARGIN_TIMCTL; /*!< Read Margin Timing Control Register */ - __I uint32_t PRGVER_TIMCTL; /*!< Program Verify Timing Control Register */ - __I uint32_t ERSVER_TIMCTL; /*!< Erase Verify Timing Control Register */ - __I uint32_t LKGVER_TIMCTL; /*!< Leakage Verify Timing Control Register */ - __I uint32_t PROGRAM_TIMCTL; /*!< Program Timing Control Register */ - __I uint32_t ERASE_TIMCTL; /*!< Erase Timing Control Register */ - __I uint32_t MASSERASE_TIMCTL; /*!< Mass Erase Timing Control Register */ - __I uint32_t BURSTPRG_TIMCTL; /*!< Burst Program Timing Control Register */ -} FLCTL_Type; - -typedef struct { - __IO uint32_t CTL; /*!< LCD_F control */ - __IO uint32_t BMCTL; /*!< LCD_F blinking and memory control */ - __IO uint32_t VCTL; /*!< LCD_F voltage control */ - __IO uint32_t PCTL0; /*!< LCD_F port control 0 */ - __IO uint32_t PCTL1; /*!< LCD_F port control 1 */ - __IO uint32_t CSSEL0; /*!< LCD_F COM/SEG select register 0 */ - __IO uint32_t CSSEL1; /*!< LCD_F COM/SEG select register 1 */ - __IO uint32_t ANMCTL; /*!< LCD_F Animation Control Register */ - uint32_t RESERVED0[60]; - __IO uint32_t IE; /*!< LCD_F interrupt enable register */ - __I uint32_t IFG; /*!< LCD_F interrupt flag register */ - __O uint32_t SETIFG; /*!< LCD_F set interrupt flag register */ - __O uint32_t CLRIFG; /*!< LCD_F clear interrupt flag register */ - __IO uint8_t M[48]; /*!< LCD memory registers */ - uint8_t RESERVED1[16]; - __IO uint8_t BM[48]; /*!< LCD Blinking memory registers */ - uint8_t RESERVED2[16]; - __IO uint8_t ANM[8]; /*!< LCD Animation memory registers */ -} LCD_F_Type; - -typedef struct { - __IO uint32_t CTL0; /*!< Control 0 Register */ - __IO uint32_t CTL1; /*!< Control 1 Register */ - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PCM_Type; - -typedef struct { - __IO uint16_t KEYID; - __IO uint16_t CTL; -} PMAP_COMMON_Type; - -typedef struct { - union { - __IO uint16_t PMAP_REGISTER[4]; - struct { - __IO uint8_t PMAP_REGISTER0; - __IO uint8_t PMAP_REGISTER1; - __IO uint8_t PMAP_REGISTER2; - __IO uint8_t PMAP_REGISTER3; - __IO uint8_t PMAP_REGISTER4; - __IO uint8_t PMAP_REGISTER5; - __IO uint8_t PMAP_REGISTER6; - __IO uint8_t PMAP_REGISTER7; - }; - }; -} PMAP_REGISTER_Type; - -typedef struct { - __IO uint32_t KEY; /*!< Key Register */ - __IO uint32_t CTL0; /*!< Control 0 Register */ - uint32_t RESERVED0[11]; - __IO uint32_t IE; /*!< Interrupt Enable Register */ - __I uint32_t IFG; /*!< Interrupt Flag Register */ - __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ -} PSS_Type; - -typedef struct { - __IO uint16_t CTL0; /*!< REF Control Register 0 */ -} REF_A_Type; - -typedef struct { - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __I uint32_t HARDRESET_STAT; /*!< Hard Reset Status Register */ - __IO uint32_t HARDRESET_CLR; /*!< Hard Reset Status Clear Register */ - __IO uint32_t HARDRESET_SET; /*!< Hard Reset Status Set Register */ - __I uint32_t SOFTRESET_STAT; /*!< Soft Reset Status Register */ - __IO uint32_t SOFTRESET_CLR; /*!< Soft Reset Status Clear Register */ - __IO uint32_t SOFTRESET_SET; /*!< Soft Reset Status Set Register */ - uint32_t RESERVED0[57]; - __I uint32_t PSSRESET_STAT; /*!< PSS Reset Status Register */ - __IO uint32_t PSSRESET_CLR; /*!< PSS Reset Status Clear Register */ - __I uint32_t PCMRESET_STAT; /*!< PCM Reset Status Register */ - __IO uint32_t PCMRESET_CLR; /*!< PCM Reset Status Clear Register */ - __I uint32_t PINRESET_STAT; /*!< Pin Reset Status Register */ - __IO uint32_t PINRESET_CLR; /*!< Pin Reset Status Clear Register */ - __I uint32_t REBOOTRESET_STAT; /*!< Reboot Reset Status Register */ - __IO uint32_t REBOOTRESET_CLR; /*!< Reboot Reset Status Clear Register */ - __I uint32_t CSRESET_STAT; /*!< CS Reset Status Register */ - __IO uint32_t CSRESET_CLR; /*!< CS Reset Status Clear Register */ -} RSTCTL_Type; - -typedef struct { - uint16_t RESERVED0[8]; - __IO uint16_t TIM0; /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week - BCD Format */ - __IO uint16_t DATE; /*!< Real-Time Clock Date - BCD Format */ - __IO uint16_t YEAR; /*!< Real-Time Clock Year Register - BCD Format */ - __IO uint16_t AMINHR; /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */ - __IO uint16_t ADOWDAY; /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */ -} RTC_C_BCD_Type; - -typedef struct { - __IO uint16_t CTL0; /*!< RTCCTL0 Register */ - __IO uint16_t CTL13; /*!< RTCCTL13 Register */ - __IO uint16_t OCAL; /*!< RTCOCAL Register */ - __IO uint16_t TCMP; /*!< RTCTCMP Register */ - __IO uint16_t PS0CTL; /*!< Real-Time Clock Prescale Timer 0 Control Register */ - __IO uint16_t PS1CTL; /*!< Real-Time Clock Prescale Timer 1 Control Register */ - __IO uint16_t PS; /*!< Real-Time Clock Prescale Timer Counter Register */ - __I uint16_t IV; /*!< Real-Time Clock Interrupt Vector Register */ - __IO uint16_t TIM0; /*!< RTCTIM0 Register Hexadecimal Format */ - __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week */ - __IO uint16_t DATE; /*!< RTCDATE - Hexadecimal Format */ - __IO uint16_t YEAR; /*!< RTCYEAR Register Hexadecimal Format */ - __IO uint16_t AMINHR; /*!< RTCMINHR - Hexadecimal Format */ - __IO uint16_t ADOWDAY; /*!< RTCADOWDAY - Hexadecimal Format */ - __IO uint16_t BIN2BCD; /*!< Binary-to-BCD Conversion Register */ - __IO uint16_t BCD2BIN; /*!< BCD-to-Binary Conversion Register */ -} RTC_C_Type; - -typedef struct { - __IO uint32_t SEC_ZONE_SECEN; /*!< IP Protection Secure Zone Enable. */ - __IO uint32_t SEC_ZONE_START_ADDR; /*!< Start address of IP protected secure zone. */ - __IO uint32_t SEC_ZONE_LENGTH; /*!< Length of IP protected secure zone in number of bytes. */ - __IO uint32_t SEC_ZONE_AESINIT_VECT[4]; /*!< IP protected secure zone 0 AES initialization vector */ - __IO uint32_t SEC_ZONE_SECKEYS[8]; /*!< AES-CBC security keys. */ - __IO uint32_t SEC_ZONE_UNENC_PWD[4]; /*!< Unencrypted password for authentication. */ - __IO uint32_t SEC_ZONE_ENCUPDATE_EN; /*!< IP Protected Secure Zone Encrypted In-field Update Enable */ - __IO uint32_t SEC_ZONE_DATA_EN; /*!< IP Protected Secure Zone Data Access Enable */ - __IO uint32_t SEC_ZONE_ACK; /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */ - uint32_t RESERVED0[2]; -} SEC_ZONE_PARAMS_Type; - -typedef struct { - __IO uint32_t SEC_ZONE_PAYLOADADDR; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t SEC_ZONE_PAYLOADLEN; /*!< Length of the payload in bytes. */ - __IO uint32_t SEC_ZONE_UPDATE_ACK; /*!< Acknowledgment for the IP Protected Secure Zone Update Command */ - uint32_t RESERVED0; -} SEC_ZONE_UPDATE_Type; - -typedef struct { - __IO uint32_t MASTER_UNLOCK; /*!< Master Unlock Register */ - __IO uint32_t BOOTOVER_REQ[2]; /*!< Boot Override Request Register */ - __IO uint32_t BOOTOVER_ACK; /*!< Boot Override Acknowledge Register */ - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __IO uint32_t RESET_STATOVER; /*!< Reset Status and Override Register */ - uint32_t RESERVED10[2]; - __I uint32_t SYSTEM_STAT; /*!< System Status Register */ -} SYSCTL_A_Boot_Type; - -typedef struct { - __IO uint32_t REBOOT_CTL; /*!< Reboot Control Register */ - __IO uint32_t NMI_CTLSTAT; /*!< NMI Control and Status Register */ - __IO uint32_t WDTRESET_CTL; /*!< Watchdog Reset Control Register */ - __IO uint32_t PERIHALT_CTL; /*!< Peripheral Halt Control Register */ - __I uint32_t SRAM_SIZE; /*!< SRAM Size Register */ - __I uint32_t SRAM_NUMBANKS; /*!< SRAM Number of Banks Register */ - __I uint32_t SRAM_NUMBLOCKS; /*!< SRAM Number of Blocks Register */ - uint32_t RESERVED0; - __I uint32_t MAINFLASH_SIZE; /*!< Flash Main Memory Size Register */ - __I uint32_t INFOFLASH_SIZE; /*!< Flash Information Memory Size Register */ - uint32_t RESERVED1[2]; - __IO uint32_t DIO_GLTFLT_CTL; /*!< Digital I/O Glitch Filter Control Register */ - uint32_t RESERVED2[3]; - __IO uint32_t SECDATA_UNLOCK; /*!< IP Protected Secure Zone Data Access Unlock Register */ - uint32_t RESERVED3[3]; - __IO uint32_t SRAM_BANKEN_CTL0; /*!< SRAM Bank Enable Control Register 0 */ - __IO uint32_t SRAM_BANKEN_CTL1; /*!< SRAM Bank Enable Control Register 1 */ - __IO uint32_t SRAM_BANKEN_CTL2; /*!< SRAM Bank Enable Control Register 2 */ - __IO uint32_t SRAM_BANKEN_CTL3; /*!< SRAM Bank Enable Control Register 3 */ - uint32_t RESERVED4[4]; - __IO uint32_t SRAM_BLKRET_CTL0; /*!< SRAM Block Retention Control Register 0 */ - __IO uint32_t SRAM_BLKRET_CTL1; /*!< SRAM Block Retention Control Register 1 */ - __IO uint32_t SRAM_BLKRET_CTL2; /*!< SRAM Block Retention Control Register 2 */ - __IO uint32_t SRAM_BLKRET_CTL3; /*!< SRAM Block Retention Control Register 3 */ - uint32_t RESERVED5[4]; - __I uint32_t SRAM_STAT; /*!< SRAM Status Register */ -} SYSCTL_A_Type; - -typedef struct { - __IO uint32_t MASTER_UNLOCK; /*!< Master Unlock Register */ - __IO uint32_t BOOTOVER_REQ[2]; /*!< Boot Override Request Register */ - __IO uint32_t BOOTOVER_ACK; /*!< Boot Override Acknowledge Register */ - __IO uint32_t RESET_REQ; /*!< Reset Request Register */ - __IO uint32_t RESET_STATOVER; /*!< Reset Status and Override Register */ - uint32_t RESERVED7[2]; - __I uint32_t SYSTEM_STAT; /*!< System Status Register */ -} SYSCTL_Boot_Type; - -typedef struct { - __IO uint32_t REBOOT_CTL; /*!< Reboot Control Register */ - __IO uint32_t NMI_CTLSTAT; /*!< NMI Control and Status Register */ - __IO uint32_t WDTRESET_CTL; /*!< Watchdog Reset Control Register */ - __IO uint32_t PERIHALT_CTL; /*!< Peripheral Halt Control Register */ - __I uint32_t SRAM_SIZE; /*!< SRAM Size Register */ - __IO uint32_t SRAM_BANKEN; /*!< SRAM Bank Enable Register */ - __IO uint32_t SRAM_BANKRET; /*!< SRAM Bank Retention Control Register */ - uint32_t RESERVED0; - __I uint32_t FLASH_SIZE; /*!< Flash Size Register */ - uint32_t RESERVED1[3]; - __IO uint32_t DIO_GLTFLT_CTL; /*!< Digital I/O Glitch Filter Control Register */ - uint32_t RESERVED2[3]; - __IO uint32_t SECDATA_UNLOCK; /*!< IP Protected Secure Zone Data Access Unlock Register */ -} SYSCTL_Type; - -typedef struct { - __I uint32_t TLV_CHECKSUM; /*!< TLV Checksum */ - __I uint32_t DEVICE_INFO_TAG; /*!< Device Info Tag */ - __I uint32_t DEVICE_INFO_LEN; /*!< Device Info Length */ - __I uint32_t DEVICE_ID; /*!< Device ID */ - __I uint32_t HWREV; /*!< HW Revision */ - __I uint32_t BCREV; /*!< Boot Code Revision */ - __I uint32_t ROM_DRVLIB_REV; /*!< ROM Driver Library Revision */ - __I uint32_t DIE_REC_TAG; /*!< Die Record Tag */ - __I uint32_t DIE_REC_LEN; /*!< Die Record Length */ - __I uint32_t DIE_XPOS; /*!< Die X-Position */ - __I uint32_t DIE_YPOS; /*!< Die Y-Position */ - __I uint32_t WAFER_ID; /*!< Wafer ID */ - __I uint32_t LOT_ID; /*!< Lot ID */ - __I uint32_t RESERVED0; /*!< Reserved */ - __I uint32_t RESERVED1; /*!< Reserved */ - __I uint32_t RESERVED2; /*!< Reserved */ - __I uint32_t TEST_RESULTS; /*!< Test Results */ - __I uint32_t CS_CAL_TAG; /*!< Clock System Calibration Tag */ - __I uint32_t CS_CAL_LEN; /*!< Clock System Calibration Length */ - __I uint32_t DCOIR_FCAL_RSEL04; /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_FCAL_RSEL5; /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED3; /*!< Reserved */ - __I uint32_t RESERVED4; /*!< Reserved */ - __I uint32_t RESERVED5; /*!< Reserved */ - __I uint32_t RESERVED6; /*!< Reserved */ - __I uint32_t DCOIR_CONSTK_RSEL04; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I uint32_t DCOIR_CONSTK_RSEL5; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t DCOER_FCAL_RSEL04; /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */ - __I uint32_t DCOER_FCAL_RSEL5; /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */ - __I uint32_t RESERVED7; /*!< Reserved */ - __I uint32_t RESERVED8; /*!< Reserved */ - __I uint32_t RESERVED9; /*!< Reserved */ - __I uint32_t RESERVED10; /*!< Reserved */ - __I uint32_t DCOER_CONSTK_RSEL04; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */ - __I uint32_t DCOER_CONSTK_RSEL5; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */ - __I uint32_t ADC14_CAL_TAG; /*!< ADC14 Calibration Tag */ - __I uint32_t ADC14_CAL_LEN; /*!< ADC14 Calibration Length */ - __I uint32_t ADC_GAIN_FACTOR; /*!< ADC Gain Factor */ - __I uint32_t ADC_OFFSET; /*!< ADC Offset */ - __I uint32_t RESERVED11; /*!< Reserved */ - __I uint32_t RESERVED12; /*!< Reserved */ - __I uint32_t RESERVED13; /*!< Reserved */ - __I uint32_t RESERVED14; /*!< Reserved */ - __I uint32_t RESERVED15; /*!< Reserved */ - __I uint32_t RESERVED16; /*!< Reserved */ - __I uint32_t RESERVED17; /*!< Reserved */ - __I uint32_t RESERVED18; /*!< Reserved */ - __I uint32_t RESERVED19; /*!< Reserved */ - __I uint32_t RESERVED20; /*!< Reserved */ - __I uint32_t RESERVED21; /*!< Reserved */ - __I uint32_t RESERVED22; /*!< Reserved */ - __I uint32_t RESERVED23; /*!< Reserved */ - __I uint32_t RESERVED24; /*!< Reserved */ - __I uint32_t RESERVED25; /*!< Reserved */ - __I uint32_t RESERVED26; /*!< Reserved */ - __I uint32_t ADC14_REF1P2V_TS30C; /*!< ADC14 1.2V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P2V_TS85C; /*!< ADC14 1.2V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF1P45V_TS30C; /*!< ADC14 1.45V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF1P45V_TS85C; /*!< ADC14 1.45V Reference Temp. Sensor 85C */ - __I uint32_t ADC14_REF2P5V_TS30C; /*!< ADC14 2.5V Reference Temp. Sensor 30C */ - __I uint32_t ADC14_REF2P5V_TS85C; /*!< ADC14 2.5V Reference Temp. Sensor 85C */ - __I uint32_t REF_CAL_TAG; /*!< REF Calibration Tag */ - __I uint32_t REF_CAL_LEN; /*!< REF Calibration Length */ - __I uint32_t REF_1P2V; /*!< REF 1.2V Reference */ - __I uint32_t REF_1P45V; /*!< REF 1.45V Reference */ - __I uint32_t REF_2P5V; /*!< REF 2.5V Reference */ - __I uint32_t FLASH_INFO_TAG; /*!< Flash Info Tag */ - __I uint32_t FLASH_INFO_LEN; /*!< Flash Info Length */ - __I uint32_t FLASH_MAX_PROG_PULSES; /*!< Flash Maximum Programming Pulses */ - __I uint32_t FLASH_MAX_ERASE_PULSES; /*!< Flash Maximum Erase Pulses */ - __I uint32_t RANDOM_NUM_TAG; /*!< 128-bit Random Number Tag */ - __I uint32_t RANDOM_NUM_LEN; /*!< 128-bit Random Number Length */ - __I uint32_t RANDOM_NUM_1; /*!< 32-bit Random Number 1 */ - __I uint32_t RANDOM_NUM_2; /*!< 32-bit Random Number 2 */ - __I uint32_t RANDOM_NUM_3; /*!< 32-bit Random Number 3 */ - __I uint32_t RANDOM_NUM_4; /*!< 32-bit Random Number 4 */ - __I uint32_t BSL_CFG_TAG; /*!< BSL Configuration Tag */ - __I uint32_t BSL_CFG_LEN; /*!< BSL Configuration Length */ - __I uint32_t BSL_PERIPHIF_SEL; /*!< BSL Peripheral Interface Selection */ - __I uint32_t BSL_PORTIF_CFG_UART; /*!< BSL Port Interface Configuration for UART */ - __I uint32_t BSL_PORTIF_CFG_SPI; /*!< BSL Port Interface Configuration for SPI */ - __I uint32_t BSL_PORTIF_CFG_I2C; /*!< BSL Port Interface Configuration for I2C */ - __I uint32_t TLV_END; /*!< TLV End Word */ -} TLV_Type; - -typedef struct { - __IO uint32_t LOAD; /*!< Timer Load Register */ - __I uint32_t VALUE; /*!< Timer Current Value Register */ - __IO uint32_t CONTROL; /*!< Timer Control Register */ - __O uint32_t INTCLR; /*!< Timer Interrupt Clear Register */ - __I uint32_t RIS; /*!< Timer Raw Interrupt Status Register */ - __I uint32_t MIS; /*!< Timer Interrupt Status Register */ - __IO uint32_t BGLOAD; /*!< Timer Background Load Register */ -} Timer32_Type; - -typedef struct { - __IO uint16_t CTL; /*!< TimerAx Control Register */ - __IO uint16_t CCTL[5]; /*!< Timer_A Capture/Compare Control Register */ - uint16_t RESERVED0[2]; - __IO uint16_t R; /*!< TimerA register */ - __IO uint16_t CCR[5]; /*!< Timer_A Capture/Compare Register */ - uint16_t RESERVED1[2]; - __IO uint16_t EX0; /*!< TimerAx Expansion 0 Register */ - uint16_t RESERVED2[6]; - __I uint16_t IV; /*!< TimerAx Interrupt Vector Register */ -} Timer_A_Type; - -typedef struct { - uint16_t RESERVED0[6]; - __IO uint16_t CTL; /*!< Watchdog Timer Control Register */ -} WDT_A_Type; - -typedef struct { - __IO uint32_t MB_START; /*!< Flash MailBox start: 0x0115ACF6 */ - __IO uint32_t CMD; /*!< Command for Boot override operations. */ - uint32_t RESERVED0[2]; - __IO uint32_t JTAG_SWD_LOCK_SECEN; /*!< JTAG and SWD Lock Enable */ - __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4]; /*!< JTAG and SWD lock AES initialization vector for AES-CBC */ - __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8]; /*!< JTAG and SWD lock AES CBC security Keys 0-7. */ - __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4]; /*!< JTAG and SWD lock unencrypted password */ - __IO uint32_t JTAG_SWD_LOCK_ACK; /*!< Acknowledgment for JTAG and SWD Lock command */ - uint32_t RESERVED1[2]; - SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4]; - __IO uint32_t BSL_ENABLE; /*!< BSL Enable. */ - __IO uint32_t BSL_START_ADDRESS; /*!< Contains the pointer to the BSL function. */ - __IO uint32_t BSL_PARAMETERS; /*!< BSL hardware invoke conifguration field. */ - uint32_t RESERVED2[2]; - __IO uint32_t BSL_ACK; /*!< Acknowledgment for the BSL Configuration Command */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD; /*!< Start address where the payload is loaded in the device. */ - __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN; /*!< Length of the encrypted payload in bytes */ - __IO uint32_t JTAG_SWD_LOCK_DST_ADDR; /*!< Destination address where the final data needs to be stored into the device. */ - __IO uint32_t ENC_UPDATE_ACK; /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */ - uint32_t RESERVED3; - SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4]; - uint32_t RESERVED4; - __IO uint32_t FACTORY_RESET_ENABLE; /*!< Enable/Disable Factory Reset */ - __IO uint32_t FACTORY_RESET_PWDEN; /*!< Factory reset password enable */ - __IO uint32_t FACTORY_RESET_PWD[4]; /*!< 128-bit Password for factory reset to be saved into the device. */ - __IO uint32_t FACTORY_RESET_PARAMS_ACK; /*!< Acknowledgment for the Factory Reset Params Command */ - uint32_t RESERVED5; - __IO uint32_t FACTORY_RESET_PASSWORD[4]; /*!< 128-bit Password for factory reset. */ - __IO uint32_t FACTORY_RESET_ACK; /*!< Acknowledgment for the Factory Reset Command */ - uint32_t RESERVED6[2]; - __IO uint32_t MB_END; /*!< Mailbox end */ -} FL_BOOTOVER_MAILBOX_Type; - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/*@}*/ /* end of group MSP432P4XX_Peripherals */ - -/****************************************************************************** -* Peripheral declaration * -******************************************************************************/ -/** @addtogroup MSP432P4XX_PeripheralDecl MSP432P4XX Peripheral Declaration - @{ -*/ - -#define ADC14 ((ADC14_Type *) ADC14_BASE) -#define AES256 ((AES256_Type *) AES256_BASE) -#define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE) -#define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE) -#define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE) -#define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE) -#define CRC32 ((CRC32_Type *) CRC32_BASE) -#define CS ((CS_Type *) CS_BASE) -#define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120)) -#define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000)) -#define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020)) -#define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040)) -#define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060)) -#define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080)) -#define DMA_Channel ((DMA_Channel_Type *) DMA_BASE) -#define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000)) -#define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE) -#define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE) -#define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE) -#define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE) -#define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE) -#define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE) -#define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE) -#define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE) -#define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE) -#define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE) -#define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE) -#define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE) -#define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE) -#define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE) -#define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE) -#define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE) -#define FLCTL ((FLCTL_Type *) FLCTL_BASE) -#define FL_BOOTOVER_MAILBOX ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE) -#define PCM ((PCM_Type *) PCM_BASE) -#define PMAP ((PMAP_COMMON_Type*) PMAP_BASE) -#define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008)) -#define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010)) -#define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018)) -#define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020)) -#define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028)) -#define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030)) -#define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038)) -#define PSS ((PSS_Type *) PSS_BASE) -#define REF_A ((REF_A_Type *) REF_A_BASE) -#define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) -#define RTC_C ((RTC_C_Type *) RTC_C_BASE) -#define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE) -#define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE) -#define SYSCTL_Boot ((SYSCTL_Boot_Type *) (SYSCTL_BASE + 0x1000)) -#define TIMER32_1 ((Timer32_Type *) TIMER32_BASE) -#define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020)) -#define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE) -#define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE) -#define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE) -#define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE) -#define TLV ((TLV_Type *) TLV_BASE) -#define WDT_A ((WDT_A_Type *) WDT_A_BASE) -#define FLCTL_A ((FLCTL_A_Type *) FLCTL_A_BASE) -#define LCD_F ((LCD_F_Type *) LCD_F_BASE) -#define SYSCTL_A ((SYSCTL_A_Type *) SYSCTL_A_BASE) -#define SYSCTL_A_Boot ((SYSCTL_A_Boot_Type *) (SYSCTL_A_BASE + 0x1000)) - - -/*@}*/ /* end of group MSP432P4XX_PeripheralDecl */ - -/*@}*/ /* end of group MSP432P4XX_Definitions */ - -#endif /* __CMSIS_CONFIG__ */ - -/****************************************************************************** -* Peripheral register control bits * -******************************************************************************/ -#define ADC14_CTL0_SC_OFS ( 0) /*!< ADC14SC Bit Offset */ -#define ADC14_CTL0_SC ((uint32_t)0x00000001) /*!< ADC14 start conversion */ -#define ADC14_CTL0_ENC_OFS ( 1) /*!< ADC14ENC Bit Offset */ -#define ADC14_CTL0_ENC ((uint32_t)0x00000002) /*!< ADC14 enable conversion */ -#define ADC14_CTL0_ON_OFS ( 4) /*!< ADC14ON Bit Offset */ -#define ADC14_CTL0_ON ((uint32_t)0x00000010) /*!< ADC14 on */ -#define ADC14_CTL0_MSC_OFS ( 7) /*!< ADC14MSC Bit Offset */ -#define ADC14_CTL0_MSC ((uint32_t)0x00000080) /*!< ADC14 multiple sample and conversion */ -#define ADC14_CTL0_SHT0_OFS ( 8) /*!< ADC14SHT0 Bit Offset */ -#define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /*!< ADC14SHT0 Bit Mask */ -#define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /*!< SHT0 Bit 0 */ -#define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /*!< SHT0 Bit 1 */ -#define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /*!< SHT0 Bit 2 */ -#define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /*!< SHT0 Bit 3 */ -#define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /*!< 192 */ -#define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /*!< 8 */ -#define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /*!< 16 */ -#define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /*!< 32 */ -#define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /*!< 64 */ -#define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /*!< 96 */ -#define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /*!< 128 */ -#define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /*!< 192 */ -#define ADC14_CTL0_SHT1_OFS (12) /*!< ADC14SHT1 Bit Offset */ -#define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /*!< ADC14SHT1 Bit Mask */ -#define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /*!< SHT1 Bit 0 */ -#define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /*!< SHT1 Bit 1 */ -#define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /*!< SHT1 Bit 2 */ -#define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /*!< SHT1 Bit 3 */ -#define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /*!< 192 */ -#define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /*!< 4 */ -#define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /*!< 8 */ -#define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /*!< 16 */ -#define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /*!< 32 */ -#define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /*!< 64 */ -#define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /*!< 96 */ -#define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /*!< 128 */ -#define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /*!< 192 */ -#define ADC14_CTL0_BUSY_OFS (16) /*!< ADC14BUSY Bit Offset */ -#define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /*!< ADC14 busy */ -#define ADC14_CTL0_CONSEQ_OFS (17) /*!< ADC14CONSEQ Bit Offset */ -#define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /*!< ADC14CONSEQ Bit Mask */ -#define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /*!< CONSEQ Bit 0 */ -#define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /*!< CONSEQ Bit 1 */ -#define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /*!< Single-channel, single-conversion */ -#define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /*!< Sequence-of-channels */ -#define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /*!< Repeat-single-channel */ -#define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /*!< Repeat-sequence-of-channels */ -#define ADC14_CTL0_SSEL_OFS (19) /*!< ADC14SSEL Bit Offset */ -#define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /*!< ADC14SSEL Bit Mask */ -#define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /*!< SSEL Bit 0 */ -#define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /*!< SSEL Bit 1 */ -#define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /*!< SSEL Bit 2 */ -#define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /*!< HSMCLK */ -#define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /*!< MODCLK */ -#define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /*!< SYSCLK */ -#define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /*!< ACLK */ -#define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /*!< MCLK */ -#define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /*!< SMCLK */ -#define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /*!< HSMCLK */ -#define ADC14_CTL0_DIV_OFS (22) /*!< ADC14DIV Bit Offset */ -#define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /*!< ADC14DIV Bit Mask */ -#define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /*!< DIV Bit 0 */ -#define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /*!< DIV Bit 1 */ -#define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /*!< DIV Bit 2 */ -#define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /*!< /8 */ -#define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /*!< /1 */ -#define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /*!< /2 */ -#define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /*!< /3 */ -#define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /*!< /4 */ -#define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /*!< /5 */ -#define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /*!< /6 */ -#define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /*!< /7 */ -#define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /*!< /8 */ -#define ADC14_CTL0_ISSH_OFS (25) /*!< ADC14ISSH Bit Offset */ -#define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /*!< ADC14 invert signal sample-and-hold */ -#define ADC14_CTL0_SHP_OFS (26) /*!< ADC14SHP Bit Offset */ -#define ADC14_CTL0_SHP ((uint32_t)0x04000000) /*!< ADC14 sample-and-hold pulse-mode select */ -#define ADC14_CTL0_SHS_OFS (27) /*!< ADC14SHS Bit Offset */ -#define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /*!< ADC14SHS Bit Mask */ -#define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /*!< SHS Bit 0 */ -#define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /*!< SHS Bit 1 */ -#define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /*!< SHS Bit 2 */ -#define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /*!< ADC14SC bit */ -#define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /*!< See device-specific data sheet for source */ -#define ADC14_CTL0_PDIV_OFS (30) /*!< ADC14PDIV Bit Offset */ -#define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /*!< ADC14PDIV Bit Mask */ -#define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /*!< PDIV Bit 0 */ -#define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /*!< PDIV Bit 1 */ -#define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -#define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /*!< Predivide by 1 */ -#define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /*!< Predivide by 4 */ -#define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /*!< Predivide by 32 */ -#define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ -#define ADC14_CTL1_PWRMD_OFS ( 0) /*!< ADC14PWRMD Bit Offset */ -#define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /*!< ADC14PWRMD Bit Mask */ -#define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /*!< PWRMD Bit 0 */ -#define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /*!< PWRMD Bit 1 */ -#define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /*!< Regular power mode for use with any resolution setting. Sample rate can be */ -#define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample */ -#define ADC14_CTL1_REFBURST_OFS ( 2) /*!< ADC14REFBURST Bit Offset */ -#define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /*!< ADC14 reference buffer burst */ -#define ADC14_CTL1_DF_OFS ( 3) /*!< ADC14DF Bit Offset */ -#define ADC14_CTL1_DF ((uint32_t)0x00000008) /*!< ADC14 data read-back format */ -#define ADC14_CTL1_RES_OFS ( 4) /*!< ADC14RES Bit Offset */ -#define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /*!< ADC14RES Bit Mask */ -#define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /*!< RES Bit 0 */ -#define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /*!< RES Bit 1 */ -#define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -#define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ -#define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ -#define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ -#define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ -#define ADC14_CTL1_CSTARTADD_OFS (16) /*!< ADC14CSTARTADD Bit Offset */ -#define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /*!< ADC14CSTARTADD Bit Mask */ -#define ADC14_CTL1_BATMAP_OFS (22) /*!< ADC14BATMAP Bit Offset */ -#define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /*!< Controls 1/2 AVCC ADC input channel selection */ -#define ADC14_CTL1_TCMAP_OFS (23) /*!< ADC14TCMAP Bit Offset */ -#define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /*!< Controls temperature sensor ADC input channel selection */ -#define ADC14_CTL1_CH0MAP_OFS (24) /*!< ADC14CH0MAP Bit Offset */ -#define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */ -#define ADC14_CTL1_CH1MAP_OFS (25) /*!< ADC14CH1MAP Bit Offset */ -#define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */ -#define ADC14_CTL1_CH2MAP_OFS (26) /*!< ADC14CH2MAP Bit Offset */ -#define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */ -#define ADC14_CTL1_CH3MAP_OFS (27) /*!< ADC14CH3MAP Bit Offset */ -#define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */ -#define ADC14_LO0_LO0_OFS ( 0) /*!< ADC14LO0 Bit Offset */ -#define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO0 Bit Mask */ -#define ADC14_HI0_HI0_OFS ( 0) /*!< ADC14HI0 Bit Offset */ -#define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI0 Bit Mask */ -#define ADC14_LO1_LO1_OFS ( 0) /*!< ADC14LO1 Bit Offset */ -#define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO1 Bit Mask */ -#define ADC14_HI1_HI1_OFS ( 0) /*!< ADC14HI1 Bit Offset */ -#define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI1 Bit Mask */ -#define ADC14_MCTLN_INCH_OFS ( 0) /*!< ADC14INCH Bit Offset */ -#define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /*!< ADC14INCH Bit Mask */ -#define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /*!< INCH Bit 0 */ -#define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /*!< INCH Bit 1 */ -#define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /*!< INCH Bit 2 */ -#define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /*!< INCH Bit 3 */ -#define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /*!< INCH Bit 4 */ -#define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ -#define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ -#define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ -#define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ -#define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ -#define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ -#define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ -#define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ -#define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ -#define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ -#define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ -#define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ -#define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ -#define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ -#define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ -#define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -#define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ -#define ADC14_MCTLN_EOS_OFS ( 7) /*!< ADC14EOS Bit Offset */ -#define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /*!< End of sequence */ -#define ADC14_MCTLN_VRSEL_OFS ( 8) /*!< ADC14VRSEL Bit Offset */ -#define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /*!< ADC14VRSEL Bit Mask */ -#define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /*!< VRSEL Bit 0 */ -#define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /*!< VRSEL Bit 1 */ -#define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /*!< VRSEL Bit 2 */ -#define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /*!< VRSEL Bit 3 */ -#define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /*!< V(R+) = AVCC, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /*!< V(R+) = VREF buffered, V(R-) = AVSS */ -#define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /*!< V(R+) = VeREF+, V(R-) = VeREF- */ -#define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */ -#define ADC14_MCTLN_DIF_OFS (13) /*!< ADC14DIF Bit Offset */ -#define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /*!< Differential mode */ -#define ADC14_MCTLN_WINC_OFS (14) /*!< ADC14WINC Bit Offset */ -#define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /*!< Comparator window enable */ -#define ADC14_MCTLN_WINCTH_OFS (15) /*!< ADC14WINCTH Bit Offset */ -#define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /*!< Window comparator threshold register selection */ -#define ADC14_MEMN_CONVRES_OFS ( 0) /*!< Conversion_Results Bit Offset */ -#define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /*!< Conversion_Results Bit Mask */ -#define ADC14_IER0_IE0_OFS ( 0) /*!< ADC14IE0 Bit Offset */ -#define ADC14_IER0_IE0 ((uint32_t)0x00000001) /*!< Interrupt enable */ -#define ADC14_IER0_IE1_OFS ( 1) /*!< ADC14IE1 Bit Offset */ -#define ADC14_IER0_IE1 ((uint32_t)0x00000002) /*!< Interrupt enable */ -#define ADC14_IER0_IE2_OFS ( 2) /*!< ADC14IE2 Bit Offset */ -#define ADC14_IER0_IE2 ((uint32_t)0x00000004) /*!< Interrupt enable */ -#define ADC14_IER0_IE3_OFS ( 3) /*!< ADC14IE3 Bit Offset */ -#define ADC14_IER0_IE3 ((uint32_t)0x00000008) /*!< Interrupt enable */ -#define ADC14_IER0_IE4_OFS ( 4) /*!< ADC14IE4 Bit Offset */ -#define ADC14_IER0_IE4 ((uint32_t)0x00000010) /*!< Interrupt enable */ -#define ADC14_IER0_IE5_OFS ( 5) /*!< ADC14IE5 Bit Offset */ -#define ADC14_IER0_IE5 ((uint32_t)0x00000020) /*!< Interrupt enable */ -#define ADC14_IER0_IE6_OFS ( 6) /*!< ADC14IE6 Bit Offset */ -#define ADC14_IER0_IE6 ((uint32_t)0x00000040) /*!< Interrupt enable */ -#define ADC14_IER0_IE7_OFS ( 7) /*!< ADC14IE7 Bit Offset */ -#define ADC14_IER0_IE7 ((uint32_t)0x00000080) /*!< Interrupt enable */ -#define ADC14_IER0_IE8_OFS ( 8) /*!< ADC14IE8 Bit Offset */ -#define ADC14_IER0_IE8 ((uint32_t)0x00000100) /*!< Interrupt enable */ -#define ADC14_IER0_IE9_OFS ( 9) /*!< ADC14IE9 Bit Offset */ -#define ADC14_IER0_IE9 ((uint32_t)0x00000200) /*!< Interrupt enable */ -#define ADC14_IER0_IE10_OFS (10) /*!< ADC14IE10 Bit Offset */ -#define ADC14_IER0_IE10 ((uint32_t)0x00000400) /*!< Interrupt enable */ -#define ADC14_IER0_IE11_OFS (11) /*!< ADC14IE11 Bit Offset */ -#define ADC14_IER0_IE11 ((uint32_t)0x00000800) /*!< Interrupt enable */ -#define ADC14_IER0_IE12_OFS (12) /*!< ADC14IE12 Bit Offset */ -#define ADC14_IER0_IE12 ((uint32_t)0x00001000) /*!< Interrupt enable */ -#define ADC14_IER0_IE13_OFS (13) /*!< ADC14IE13 Bit Offset */ -#define ADC14_IER0_IE13 ((uint32_t)0x00002000) /*!< Interrupt enable */ -#define ADC14_IER0_IE14_OFS (14) /*!< ADC14IE14 Bit Offset */ -#define ADC14_IER0_IE14 ((uint32_t)0x00004000) /*!< Interrupt enable */ -#define ADC14_IER0_IE15_OFS (15) /*!< ADC14IE15 Bit Offset */ -#define ADC14_IER0_IE15 ((uint32_t)0x00008000) /*!< Interrupt enable */ -#define ADC14_IER0_IE16_OFS (16) /*!< ADC14IE16 Bit Offset */ -#define ADC14_IER0_IE16 ((uint32_t)0x00010000) /*!< Interrupt enable */ -#define ADC14_IER0_IE17_OFS (17) /*!< ADC14IE17 Bit Offset */ -#define ADC14_IER0_IE17 ((uint32_t)0x00020000) /*!< Interrupt enable */ -#define ADC14_IER0_IE19_OFS (19) /*!< ADC14IE19 Bit Offset */ -#define ADC14_IER0_IE19 ((uint32_t)0x00080000) /*!< Interrupt enable */ -#define ADC14_IER0_IE18_OFS (18) /*!< ADC14IE18 Bit Offset */ -#define ADC14_IER0_IE18 ((uint32_t)0x00040000) /*!< Interrupt enable */ -#define ADC14_IER0_IE20_OFS (20) /*!< ADC14IE20 Bit Offset */ -#define ADC14_IER0_IE20 ((uint32_t)0x00100000) /*!< Interrupt enable */ -#define ADC14_IER0_IE21_OFS (21) /*!< ADC14IE21 Bit Offset */ -#define ADC14_IER0_IE21 ((uint32_t)0x00200000) /*!< Interrupt enable */ -#define ADC14_IER0_IE22_OFS (22) /*!< ADC14IE22 Bit Offset */ -#define ADC14_IER0_IE22 ((uint32_t)0x00400000) /*!< Interrupt enable */ -#define ADC14_IER0_IE23_OFS (23) /*!< ADC14IE23 Bit Offset */ -#define ADC14_IER0_IE23 ((uint32_t)0x00800000) /*!< Interrupt enable */ -#define ADC14_IER0_IE24_OFS (24) /*!< ADC14IE24 Bit Offset */ -#define ADC14_IER0_IE24 ((uint32_t)0x01000000) /*!< Interrupt enable */ -#define ADC14_IER0_IE25_OFS (25) /*!< ADC14IE25 Bit Offset */ -#define ADC14_IER0_IE25 ((uint32_t)0x02000000) /*!< Interrupt enable */ -#define ADC14_IER0_IE26_OFS (26) /*!< ADC14IE26 Bit Offset */ -#define ADC14_IER0_IE26 ((uint32_t)0x04000000) /*!< Interrupt enable */ -#define ADC14_IER0_IE27_OFS (27) /*!< ADC14IE27 Bit Offset */ -#define ADC14_IER0_IE27 ((uint32_t)0x08000000) /*!< Interrupt enable */ -#define ADC14_IER0_IE28_OFS (28) /*!< ADC14IE28 Bit Offset */ -#define ADC14_IER0_IE28 ((uint32_t)0x10000000) /*!< Interrupt enable */ -#define ADC14_IER0_IE29_OFS (29) /*!< ADC14IE29 Bit Offset */ -#define ADC14_IER0_IE29 ((uint32_t)0x20000000) /*!< Interrupt enable */ -#define ADC14_IER0_IE30_OFS (30) /*!< ADC14IE30 Bit Offset */ -#define ADC14_IER0_IE30 ((uint32_t)0x40000000) /*!< Interrupt enable */ -#define ADC14_IER0_IE31_OFS (31) /*!< ADC14IE31 Bit Offset */ -#define ADC14_IER0_IE31 ((uint32_t)0x80000000) /*!< Interrupt enable */ -#define ADC14_IER1_INIE_OFS ( 1) /*!< ADC14INIE Bit Offset */ -#define ADC14_IER1_INIE ((uint32_t)0x00000002) /*!< Interrupt enable for ADC14MEMx within comparator window */ -#define ADC14_IER1_LOIE_OFS ( 2) /*!< ADC14LOIE Bit Offset */ -#define ADC14_IER1_LOIE ((uint32_t)0x00000004) /*!< Interrupt enable for ADC14MEMx below comparator window */ -#define ADC14_IER1_HIIE_OFS ( 3) /*!< ADC14HIIE Bit Offset */ -#define ADC14_IER1_HIIE ((uint32_t)0x00000008) /*!< Interrupt enable for ADC14MEMx above comparator window */ -#define ADC14_IER1_OVIE_OFS ( 4) /*!< ADC14OVIE Bit Offset */ -#define ADC14_IER1_OVIE ((uint32_t)0x00000010) /*!< ADC14MEMx overflow-interrupt enable */ -#define ADC14_IER1_TOVIE_OFS ( 5) /*!< ADC14TOVIE Bit Offset */ -#define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /*!< ADC14 conversion-time-overflow interrupt enable */ -#define ADC14_IER1_RDYIE_OFS ( 6) /*!< ADC14RDYIE Bit Offset */ -#define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt enable */ -#define ADC14_IFGR0_IFG0_OFS ( 0) /*!< ADC14IFG0 Bit Offset */ -#define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /*!< ADC14MEM0 interrupt flag */ -#define ADC14_IFGR0_IFG1_OFS ( 1) /*!< ADC14IFG1 Bit Offset */ -#define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /*!< ADC14MEM1 interrupt flag */ -#define ADC14_IFGR0_IFG2_OFS ( 2) /*!< ADC14IFG2 Bit Offset */ -#define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /*!< ADC14MEM2 interrupt flag */ -#define ADC14_IFGR0_IFG3_OFS ( 3) /*!< ADC14IFG3 Bit Offset */ -#define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /*!< ADC14MEM3 interrupt flag */ -#define ADC14_IFGR0_IFG4_OFS ( 4) /*!< ADC14IFG4 Bit Offset */ -#define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /*!< ADC14MEM4 interrupt flag */ -#define ADC14_IFGR0_IFG5_OFS ( 5) /*!< ADC14IFG5 Bit Offset */ -#define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /*!< ADC14MEM5 interrupt flag */ -#define ADC14_IFGR0_IFG6_OFS ( 6) /*!< ADC14IFG6 Bit Offset */ -#define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /*!< ADC14MEM6 interrupt flag */ -#define ADC14_IFGR0_IFG7_OFS ( 7) /*!< ADC14IFG7 Bit Offset */ -#define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /*!< ADC14MEM7 interrupt flag */ -#define ADC14_IFGR0_IFG8_OFS ( 8) /*!< ADC14IFG8 Bit Offset */ -#define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /*!< ADC14MEM8 interrupt flag */ -#define ADC14_IFGR0_IFG9_OFS ( 9) /*!< ADC14IFG9 Bit Offset */ -#define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /*!< ADC14MEM9 interrupt flag */ -#define ADC14_IFGR0_IFG10_OFS (10) /*!< ADC14IFG10 Bit Offset */ -#define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /*!< ADC14MEM10 interrupt flag */ -#define ADC14_IFGR0_IFG11_OFS (11) /*!< ADC14IFG11 Bit Offset */ -#define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /*!< ADC14MEM11 interrupt flag */ -#define ADC14_IFGR0_IFG12_OFS (12) /*!< ADC14IFG12 Bit Offset */ -#define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /*!< ADC14MEM12 interrupt flag */ -#define ADC14_IFGR0_IFG13_OFS (13) /*!< ADC14IFG13 Bit Offset */ -#define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /*!< ADC14MEM13 interrupt flag */ -#define ADC14_IFGR0_IFG14_OFS (14) /*!< ADC14IFG14 Bit Offset */ -#define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /*!< ADC14MEM14 interrupt flag */ -#define ADC14_IFGR0_IFG15_OFS (15) /*!< ADC14IFG15 Bit Offset */ -#define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /*!< ADC14MEM15 interrupt flag */ -#define ADC14_IFGR0_IFG16_OFS (16) /*!< ADC14IFG16 Bit Offset */ -#define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /*!< ADC14MEM16 interrupt flag */ -#define ADC14_IFGR0_IFG17_OFS (17) /*!< ADC14IFG17 Bit Offset */ -#define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /*!< ADC14MEM17 interrupt flag */ -#define ADC14_IFGR0_IFG18_OFS (18) /*!< ADC14IFG18 Bit Offset */ -#define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /*!< ADC14MEM18 interrupt flag */ -#define ADC14_IFGR0_IFG19_OFS (19) /*!< ADC14IFG19 Bit Offset */ -#define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /*!< ADC14MEM19 interrupt flag */ -#define ADC14_IFGR0_IFG20_OFS (20) /*!< ADC14IFG20 Bit Offset */ -#define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /*!< ADC14MEM20 interrupt flag */ -#define ADC14_IFGR0_IFG21_OFS (21) /*!< ADC14IFG21 Bit Offset */ -#define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /*!< ADC14MEM21 interrupt flag */ -#define ADC14_IFGR0_IFG22_OFS (22) /*!< ADC14IFG22 Bit Offset */ -#define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /*!< ADC14MEM22 interrupt flag */ -#define ADC14_IFGR0_IFG23_OFS (23) /*!< ADC14IFG23 Bit Offset */ -#define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /*!< ADC14MEM23 interrupt flag */ -#define ADC14_IFGR0_IFG24_OFS (24) /*!< ADC14IFG24 Bit Offset */ -#define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /*!< ADC14MEM24 interrupt flag */ -#define ADC14_IFGR0_IFG25_OFS (25) /*!< ADC14IFG25 Bit Offset */ -#define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /*!< ADC14MEM25 interrupt flag */ -#define ADC14_IFGR0_IFG26_OFS (26) /*!< ADC14IFG26 Bit Offset */ -#define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /*!< ADC14MEM26 interrupt flag */ -#define ADC14_IFGR0_IFG27_OFS (27) /*!< ADC14IFG27 Bit Offset */ -#define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /*!< ADC14MEM27 interrupt flag */ -#define ADC14_IFGR0_IFG28_OFS (28) /*!< ADC14IFG28 Bit Offset */ -#define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /*!< ADC14MEM28 interrupt flag */ -#define ADC14_IFGR0_IFG29_OFS (29) /*!< ADC14IFG29 Bit Offset */ -#define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /*!< ADC14MEM29 interrupt flag */ -#define ADC14_IFGR0_IFG30_OFS (30) /*!< ADC14IFG30 Bit Offset */ -#define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /*!< ADC14MEM30 interrupt flag */ -#define ADC14_IFGR0_IFG31_OFS (31) /*!< ADC14IFG31 Bit Offset */ -#define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /*!< ADC14MEM31 interrupt flag */ -#define ADC14_IFGR1_INIFG_OFS ( 1) /*!< ADC14INIFG Bit Offset */ -#define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /*!< Interrupt flag for ADC14MEMx within comparator window */ -#define ADC14_IFGR1_LOIFG_OFS ( 2) /*!< ADC14LOIFG Bit Offset */ -#define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /*!< Interrupt flag for ADC14MEMx below comparator window */ -#define ADC14_IFGR1_HIIFG_OFS ( 3) /*!< ADC14HIIFG Bit Offset */ -#define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /*!< Interrupt flag for ADC14MEMx above comparator window */ -#define ADC14_IFGR1_OVIFG_OFS ( 4) /*!< ADC14OVIFG Bit Offset */ -#define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /*!< ADC14MEMx overflow interrupt flag */ -#define ADC14_IFGR1_TOVIFG_OFS ( 5) /*!< ADC14TOVIFG Bit Offset */ -#define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /*!< ADC14 conversion time overflow interrupt flag */ -#define ADC14_IFGR1_RDYIFG_OFS ( 6) /*!< ADC14RDYIFG Bit Offset */ -#define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt flag */ -#define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /*!< CLRADC14IFG0 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /*!< clear ADC14IFG0 */ -#define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /*!< CLRADC14IFG1 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /*!< clear ADC14IFG1 */ -#define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /*!< CLRADC14IFG2 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /*!< clear ADC14IFG2 */ -#define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /*!< CLRADC14IFG3 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /*!< clear ADC14IFG3 */ -#define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /*!< CLRADC14IFG4 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /*!< clear ADC14IFG4 */ -#define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /*!< CLRADC14IFG5 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /*!< clear ADC14IFG5 */ -#define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /*!< CLRADC14IFG6 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /*!< clear ADC14IFG6 */ -#define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /*!< CLRADC14IFG7 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /*!< clear ADC14IFG7 */ -#define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /*!< CLRADC14IFG8 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /*!< clear ADC14IFG8 */ -#define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /*!< CLRADC14IFG9 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /*!< clear ADC14IFG9 */ -#define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /*!< CLRADC14IFG10 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /*!< clear ADC14IFG10 */ -#define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /*!< CLRADC14IFG11 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /*!< clear ADC14IFG11 */ -#define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /*!< CLRADC14IFG12 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /*!< clear ADC14IFG12 */ -#define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /*!< CLRADC14IFG13 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /*!< clear ADC14IFG13 */ -#define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /*!< CLRADC14IFG14 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /*!< clear ADC14IFG14 */ -#define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /*!< CLRADC14IFG15 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /*!< clear ADC14IFG15 */ -#define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /*!< CLRADC14IFG16 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /*!< clear ADC14IFG16 */ -#define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /*!< CLRADC14IFG17 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /*!< clear ADC14IFG17 */ -#define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /*!< CLRADC14IFG18 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /*!< clear ADC14IFG18 */ -#define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /*!< CLRADC14IFG19 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /*!< clear ADC14IFG19 */ -#define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /*!< CLRADC14IFG20 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /*!< clear ADC14IFG20 */ -#define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /*!< CLRADC14IFG21 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /*!< clear ADC14IFG21 */ -#define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /*!< CLRADC14IFG22 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /*!< clear ADC14IFG22 */ -#define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /*!< CLRADC14IFG23 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /*!< clear ADC14IFG23 */ -#define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /*!< CLRADC14IFG24 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /*!< clear ADC14IFG24 */ -#define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /*!< CLRADC14IFG25 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /*!< clear ADC14IFG25 */ -#define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /*!< CLRADC14IFG26 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /*!< clear ADC14IFG26 */ -#define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /*!< CLRADC14IFG27 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /*!< clear ADC14IFG27 */ -#define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /*!< CLRADC14IFG28 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /*!< clear ADC14IFG28 */ -#define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /*!< CLRADC14IFG29 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /*!< clear ADC14IFG29 */ -#define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /*!< CLRADC14IFG30 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /*!< clear ADC14IFG30 */ -#define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /*!< CLRADC14IFG31 Bit Offset */ -#define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /*!< clear ADC14IFG31 */ -#define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /*!< CLRADC14INIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /*!< clear ADC14INIFG */ -#define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /*!< CLRADC14LOIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /*!< clear ADC14LOIFG */ -#define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /*!< CLRADC14HIIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /*!< clear ADC14HIIFG */ -#define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /*!< CLRADC14OVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /*!< clear ADC14OVIFG */ -#define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /*!< CLRADC14TOVIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /*!< clear ADC14TOVIFG */ -#define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /*!< CLRADC14RDYIFG Bit Offset */ -#define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /*!< clear ADC14RDYIFG */ -#define AES256_CTL0_OP_OFS ( 0) /*!< AESOPx Bit Offset */ -#define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /*!< AESOPx Bit Mask */ -#define AES256_CTL0_OP0 ((uint16_t)0x0001) /*!< OP Bit 0 */ -#define AES256_CTL0_OP1 ((uint16_t)0x0002) /*!< OP Bit 1 */ -#define AES256_CTL0_OP_0 ((uint16_t)0x0000) /*!< Encryption */ -#define AES256_CTL0_OP_1 ((uint16_t)0x0001) /*!< Decryption. The provided key is the same key used for encryption */ -#define AES256_CTL0_OP_2 ((uint16_t)0x0002) /*!< Generate first round key required for decryption */ -#define AES256_CTL0_OP_3 ((uint16_t)0x0003) /*!< Decryption. The provided key is the first round key required for decryption */ -#define AES256_CTL0_KL_OFS ( 2) /*!< AESKLx Bit Offset */ -#define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /*!< AESKLx Bit Mask */ -#define AES256_CTL0_KL0 ((uint16_t)0x0004) /*!< KL Bit 0 */ -#define AES256_CTL0_KL1 ((uint16_t)0x0008) /*!< KL Bit 1 */ -#define AES256_CTL0_KL_0 ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL_1 ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL_2 ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -#define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ -#define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ -#define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ -#define AES256_CTL0_CM_OFS ( 5) /*!< AESCMx Bit Offset */ -#define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /*!< AESCMx Bit Mask */ -#define AES256_CTL0_CM0 ((uint16_t)0x0020) /*!< CM Bit 0 */ -#define AES256_CTL0_CM1 ((uint16_t)0x0040) /*!< CM Bit 1 */ -#define AES256_CTL0_CM_0 ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM_1 ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM_2 ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM_3 ((uint16_t)0x0060) /*!< CFB */ -#define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /*!< ECB */ -#define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /*!< CBC */ -#define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /*!< OFB */ -#define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /*!< CFB */ -#define AES256_CTL0_SWRST_OFS ( 7) /*!< AESSWRST Bit Offset */ -#define AES256_CTL0_SWRST ((uint16_t)0x0080) /*!< AES software reset */ -#define AES256_CTL0_RDYIFG_OFS ( 8) /*!< AESRDYIFG Bit Offset */ -#define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /*!< AES ready interrupt flag */ -#define AES256_CTL0_ERRFG_OFS (11) /*!< AESERRFG Bit Offset */ -#define AES256_CTL0_ERRFG ((uint16_t)0x0800) /*!< AES error flag */ -#define AES256_CTL0_RDYIE_OFS (12) /*!< AESRDYIE Bit Offset */ -#define AES256_CTL0_RDYIE ((uint16_t)0x1000) /*!< AES ready interrupt enable */ -#define AES256_CTL0_CMEN_OFS (15) /*!< AESCMEN Bit Offset */ -#define AES256_CTL0_CMEN ((uint16_t)0x8000) /*!< AES cipher mode enable */ -#define AES256_CTL1_BLKCNT_OFS ( 0) /*!< AESBLKCNTx Bit Offset */ -#define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /*!< AESBLKCNTx Bit Mask */ -#define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /*!< BLKCNT Bit 0 */ -#define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /*!< BLKCNT Bit 1 */ -#define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /*!< BLKCNT Bit 2 */ -#define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /*!< BLKCNT Bit 3 */ -#define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /*!< BLKCNT Bit 4 */ -#define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /*!< BLKCNT Bit 5 */ -#define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /*!< BLKCNT Bit 6 */ -#define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /*!< BLKCNT Bit 7 */ -#define AES256_STAT_BUSY_OFS ( 0) /*!< AESBUSY Bit Offset */ -#define AES256_STAT_BUSY ((uint16_t)0x0001) /*!< AES accelerator module busy */ -#define AES256_STAT_KEYWR_OFS ( 1) /*!< AESKEYWR Bit Offset */ -#define AES256_STAT_KEYWR ((uint16_t)0x0002) /*!< All 16 bytes written to AESAKEY */ -#define AES256_STAT_DINWR_OFS ( 2) /*!< AESDINWR Bit Offset */ -#define AES256_STAT_DINWR ((uint16_t)0x0004) /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ -#define AES256_STAT_DOUTRD_OFS ( 3) /*!< AESDOUTRD Bit Offset */ -#define AES256_STAT_DOUTRD ((uint16_t)0x0008) /*!< All 16 bytes read from AESADOUT */ -#define AES256_STAT_KEYCNT_OFS ( 4) /*!< AESKEYCNTx Bit Offset */ -#define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /*!< AESKEYCNTx Bit Mask */ -#define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /*!< KEYCNT Bit 0 */ -#define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /*!< KEYCNT Bit 1 */ -#define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /*!< KEYCNT Bit 2 */ -#define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /*!< KEYCNT Bit 3 */ -#define AES256_STAT_DINCNT_OFS ( 8) /*!< AESDINCNTx Bit Offset */ -#define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /*!< AESDINCNTx Bit Mask */ -#define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /*!< DINCNT Bit 0 */ -#define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /*!< DINCNT Bit 1 */ -#define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /*!< DINCNT Bit 2 */ -#define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /*!< DINCNT Bit 3 */ -#define AES256_STAT_DOUTCNT_OFS (12) /*!< AESDOUTCNTx Bit Offset */ -#define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /*!< AESDOUTCNTx Bit Mask */ -#define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /*!< DOUTCNT Bit 0 */ -#define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /*!< DOUTCNT Bit 1 */ -#define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /*!< DOUTCNT Bit 2 */ -#define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /*!< DOUTCNT Bit 3 */ -#define AES256_KEY_KEY0_OFS ( 0) /*!< AESKEY0x Bit Offset */ -#define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /*!< AESKEY0x Bit Mask */ -#define AES256_KEY_KEY00 ((uint16_t)0x0001) /*!< KEY0 Bit 0 */ -#define AES256_KEY_KEY01 ((uint16_t)0x0002) /*!< KEY0 Bit 1 */ -#define AES256_KEY_KEY02 ((uint16_t)0x0004) /*!< KEY0 Bit 2 */ -#define AES256_KEY_KEY03 ((uint16_t)0x0008) /*!< KEY0 Bit 3 */ -#define AES256_KEY_KEY04 ((uint16_t)0x0010) /*!< KEY0 Bit 4 */ -#define AES256_KEY_KEY05 ((uint16_t)0x0020) /*!< KEY0 Bit 5 */ -#define AES256_KEY_KEY06 ((uint16_t)0x0040) /*!< KEY0 Bit 6 */ -#define AES256_KEY_KEY07 ((uint16_t)0x0080) /*!< KEY0 Bit 7 */ -#define AES256_KEY_KEY1_OFS ( 8) /*!< AESKEY1x Bit Offset */ -#define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /*!< AESKEY1x Bit Mask */ -#define AES256_KEY_KEY10 ((uint16_t)0x0100) /*!< KEY1 Bit 0 */ -#define AES256_KEY_KEY11 ((uint16_t)0x0200) /*!< KEY1 Bit 1 */ -#define AES256_KEY_KEY12 ((uint16_t)0x0400) /*!< KEY1 Bit 2 */ -#define AES256_KEY_KEY13 ((uint16_t)0x0800) /*!< KEY1 Bit 3 */ -#define AES256_KEY_KEY14 ((uint16_t)0x1000) /*!< KEY1 Bit 4 */ -#define AES256_KEY_KEY15 ((uint16_t)0x2000) /*!< KEY1 Bit 5 */ -#define AES256_KEY_KEY16 ((uint16_t)0x4000) /*!< KEY1 Bit 6 */ -#define AES256_KEY_KEY17 ((uint16_t)0x8000) /*!< KEY1 Bit 7 */ -#define AES256_DIN_DIN0_OFS ( 0) /*!< AESDIN0x Bit Offset */ -#define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /*!< AESDIN0x Bit Mask */ -#define AES256_DIN_DIN00 ((uint16_t)0x0001) /*!< DIN0 Bit 0 */ -#define AES256_DIN_DIN01 ((uint16_t)0x0002) /*!< DIN0 Bit 1 */ -#define AES256_DIN_DIN02 ((uint16_t)0x0004) /*!< DIN0 Bit 2 */ -#define AES256_DIN_DIN03 ((uint16_t)0x0008) /*!< DIN0 Bit 3 */ -#define AES256_DIN_DIN04 ((uint16_t)0x0010) /*!< DIN0 Bit 4 */ -#define AES256_DIN_DIN05 ((uint16_t)0x0020) /*!< DIN0 Bit 5 */ -#define AES256_DIN_DIN06 ((uint16_t)0x0040) /*!< DIN0 Bit 6 */ -#define AES256_DIN_DIN07 ((uint16_t)0x0080) /*!< DIN0 Bit 7 */ -#define AES256_DIN_DIN1_OFS ( 8) /*!< AESDIN1x Bit Offset */ -#define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /*!< AESDIN1x Bit Mask */ -#define AES256_DIN_DIN10 ((uint16_t)0x0100) /*!< DIN1 Bit 0 */ -#define AES256_DIN_DIN11 ((uint16_t)0x0200) /*!< DIN1 Bit 1 */ -#define AES256_DIN_DIN12 ((uint16_t)0x0400) /*!< DIN1 Bit 2 */ -#define AES256_DIN_DIN13 ((uint16_t)0x0800) /*!< DIN1 Bit 3 */ -#define AES256_DIN_DIN14 ((uint16_t)0x1000) /*!< DIN1 Bit 4 */ -#define AES256_DIN_DIN15 ((uint16_t)0x2000) /*!< DIN1 Bit 5 */ -#define AES256_DIN_DIN16 ((uint16_t)0x4000) /*!< DIN1 Bit 6 */ -#define AES256_DIN_DIN17 ((uint16_t)0x8000) /*!< DIN1 Bit 7 */ -#define AES256_DOUT_DOUT0_OFS ( 0) /*!< AESDOUT0x Bit Offset */ -#define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /*!< AESDOUT0x Bit Mask */ -#define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /*!< DOUT0 Bit 0 */ -#define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /*!< DOUT0 Bit 1 */ -#define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /*!< DOUT0 Bit 2 */ -#define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /*!< DOUT0 Bit 3 */ -#define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /*!< DOUT0 Bit 4 */ -#define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /*!< DOUT0 Bit 5 */ -#define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /*!< DOUT0 Bit 6 */ -#define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /*!< DOUT0 Bit 7 */ -#define AES256_DOUT_DOUT1_OFS ( 8) /*!< AESDOUT1x Bit Offset */ -#define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /*!< AESDOUT1x Bit Mask */ -#define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /*!< DOUT1 Bit 0 */ -#define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /*!< DOUT1 Bit 1 */ -#define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /*!< DOUT1 Bit 2 */ -#define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /*!< DOUT1 Bit 3 */ -#define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /*!< DOUT1 Bit 4 */ -#define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /*!< DOUT1 Bit 5 */ -#define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /*!< DOUT1 Bit 6 */ -#define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /*!< DOUT1 Bit 7 */ -#define AES256_XDIN_XDIN0_OFS ( 0) /*!< AESXDIN0x Bit Offset */ -#define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /*!< AESXDIN0x Bit Mask */ -#define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /*!< XDIN0 Bit 0 */ -#define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /*!< XDIN0 Bit 1 */ -#define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /*!< XDIN0 Bit 2 */ -#define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /*!< XDIN0 Bit 3 */ -#define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /*!< XDIN0 Bit 4 */ -#define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /*!< XDIN0 Bit 5 */ -#define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /*!< XDIN0 Bit 6 */ -#define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /*!< XDIN0 Bit 7 */ -#define AES256_XDIN_XDIN1_OFS ( 8) /*!< AESXDIN1x Bit Offset */ -#define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /*!< AESXDIN1x Bit Mask */ -#define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /*!< XDIN1 Bit 0 */ -#define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /*!< XDIN1 Bit 1 */ -#define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /*!< XDIN1 Bit 2 */ -#define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /*!< XDIN1 Bit 3 */ -#define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /*!< XDIN1 Bit 4 */ -#define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /*!< XDIN1 Bit 5 */ -#define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /*!< XDIN1 Bit 6 */ -#define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /*!< XDIN1 Bit 7 */ -#define AES256_XIN_XIN0_OFS ( 0) /*!< AESXIN0x Bit Offset */ -#define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /*!< AESXIN0x Bit Mask */ -#define AES256_XIN_XIN00 ((uint16_t)0x0001) /*!< XIN0 Bit 0 */ -#define AES256_XIN_XIN01 ((uint16_t)0x0002) /*!< XIN0 Bit 1 */ -#define AES256_XIN_XIN02 ((uint16_t)0x0004) /*!< XIN0 Bit 2 */ -#define AES256_XIN_XIN03 ((uint16_t)0x0008) /*!< XIN0 Bit 3 */ -#define AES256_XIN_XIN04 ((uint16_t)0x0010) /*!< XIN0 Bit 4 */ -#define AES256_XIN_XIN05 ((uint16_t)0x0020) /*!< XIN0 Bit 5 */ -#define AES256_XIN_XIN06 ((uint16_t)0x0040) /*!< XIN0 Bit 6 */ -#define AES256_XIN_XIN07 ((uint16_t)0x0080) /*!< XIN0 Bit 7 */ -#define AES256_XIN_XIN1_OFS ( 8) /*!< AESXIN1x Bit Offset */ -#define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /*!< AESXIN1x Bit Mask */ -#define AES256_XIN_XIN10 ((uint16_t)0x0100) /*!< XIN1 Bit 0 */ -#define AES256_XIN_XIN11 ((uint16_t)0x0200) /*!< XIN1 Bit 1 */ -#define AES256_XIN_XIN12 ((uint16_t)0x0400) /*!< XIN1 Bit 2 */ -#define AES256_XIN_XIN13 ((uint16_t)0x0800) /*!< XIN1 Bit 3 */ -#define AES256_XIN_XIN14 ((uint16_t)0x1000) /*!< XIN1 Bit 4 */ -#define AES256_XIN_XIN15 ((uint16_t)0x2000) /*!< XIN1 Bit 5 */ -#define AES256_XIN_XIN16 ((uint16_t)0x4000) /*!< XIN1 Bit 6 */ -#define AES256_XIN_XIN17 ((uint16_t)0x8000) /*!< XIN1 Bit 7 */ -#define CAPTIO_CTL_PISEL_OFS ( 1) /*!< CAPTIOPISELx Bit Offset */ -#define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /*!< CAPTIOPISELx Bit Mask */ -#define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /*!< PISEL Bit 0 */ -#define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /*!< PISEL Bit 1 */ -#define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /*!< PISEL Bit 2 */ -#define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /*!< Px.0 */ -#define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /*!< Px.1 */ -#define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /*!< Px.2 */ -#define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /*!< Px.3 */ -#define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /*!< Px.4 */ -#define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /*!< Px.5 */ -#define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /*!< Px.6 */ -#define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /*!< Px.7 */ -#define CAPTIO_CTL_POSEL_OFS ( 4) /*!< CAPTIOPOSELx Bit Offset */ -#define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /*!< CAPTIOPOSELx Bit Mask */ -#define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /*!< POSEL Bit 0 */ -#define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /*!< POSEL Bit 1 */ -#define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /*!< POSEL Bit 2 */ -#define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /*!< POSEL Bit 3 */ -#define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /*!< Px = P15 */ -#define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /*!< Px = PJ */ -#define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /*!< Px = P1 */ -#define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /*!< Px = P2 */ -#define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /*!< Px = P3 */ -#define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /*!< Px = P4 */ -#define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /*!< Px = P5 */ -#define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /*!< Px = P6 */ -#define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /*!< Px = P7 */ -#define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /*!< Px = P8 */ -#define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /*!< Px = P9 */ -#define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /*!< Px = P10 */ -#define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /*!< Px = P11 */ -#define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /*!< Px = P12 */ -#define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /*!< Px = P13 */ -#define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /*!< Px = P14 */ -#define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /*!< Px = P15 */ -#define CAPTIO_CTL_EN_OFS ( 8) /*!< CAPTIOEN Bit Offset */ -#define CAPTIO_CTL_EN ((uint16_t)0x0100) /*!< Capacitive Touch IO enable */ -#define CAPTIO_CTL_STATE_OFS ( 9) /*!< CAPTIOSTATE Bit Offset */ -#define CAPTIO_CTL_STATE ((uint16_t)0x0200) /*!< Capacitive Touch IO state */ -#define COMP_E_CTL0_IPSEL_OFS ( 0) /*!< CEIPSEL Bit Offset */ -#define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /*!< CEIPSEL Bit Mask */ -#define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /*!< IPSEL Bit 0 */ -#define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /*!< IPSEL Bit 1 */ -#define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /*!< IPSEL Bit 2 */ -#define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /*!< IPSEL Bit 3 */ -#define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /*!< Channel 15 selected */ -#define COMP_E_CTL0_IPEN_OFS ( 7) /*!< CEIPEN Bit Offset */ -#define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /*!< Channel input enable for the V+ terminal */ -#define COMP_E_CTL0_IMSEL_OFS ( 8) /*!< CEIMSEL Bit Offset */ -#define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /*!< CEIMSEL Bit Mask */ -#define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /*!< IMSEL Bit 0 */ -#define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /*!< IMSEL Bit 1 */ -#define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /*!< IMSEL Bit 2 */ -#define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /*!< IMSEL Bit 3 */ -#define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ -#define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /*!< Channel 1 selected */ -#define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /*!< Channel 2 selected */ -#define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /*!< Channel 3 selected */ -#define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /*!< Channel 4 selected */ -#define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /*!< Channel 5 selected */ -#define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /*!< Channel 6 selected */ -#define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /*!< Channel 7 selected */ -#define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /*!< Channel 8 selected */ -#define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /*!< Channel 9 selected */ -#define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /*!< Channel 10 selected */ -#define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /*!< Channel 11 selected */ -#define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /*!< Channel 12 selected */ -#define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /*!< Channel 13 selected */ -#define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /*!< Channel 14 selected */ -#define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /*!< Channel 15 selected */ -#define COMP_E_CTL0_IMEN_OFS (15) /*!< CEIMEN Bit Offset */ -#define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /*!< Channel input enable for the - terminal */ -#define COMP_E_CTL1_OUT_OFS ( 0) /*!< CEOUT Bit Offset */ -#define COMP_E_CTL1_OUT ((uint16_t)0x0001) /*!< Comparator output value */ -#define COMP_E_CTL1_OUTPOL_OFS ( 1) /*!< CEOUTPOL Bit Offset */ -#define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /*!< Comparator output polarity */ -#define COMP_E_CTL1_F_OFS ( 2) /*!< CEF Bit Offset */ -#define COMP_E_CTL1_F ((uint16_t)0x0004) /*!< Comparator output filter */ -#define COMP_E_CTL1_IES_OFS ( 3) /*!< CEIES Bit Offset */ -#define COMP_E_CTL1_IES ((uint16_t)0x0008) /*!< Interrupt edge select for CEIIFG and CEIFG */ -#define COMP_E_CTL1_SHORT_OFS ( 4) /*!< CESHORT Bit Offset */ -#define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /*!< Input short */ -#define COMP_E_CTL1_EX_OFS ( 5) /*!< CEEX Bit Offset */ -#define COMP_E_CTL1_EX ((uint16_t)0x0020) /*!< Exchange */ -#define COMP_E_CTL1_FDLY_OFS ( 6) /*!< CEFDLY Bit Offset */ -#define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /*!< CEFDLY Bit Mask */ -#define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /*!< FDLY Bit 0 */ -#define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /*!< FDLY Bit 1 */ -#define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /*!< Typical filter delay of TBD (450) ns */ -#define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /*!< Typical filter delay of TBD (900) ns */ -#define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /*!< Typical filter delay of TBD (1800) ns */ -#define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /*!< Typical filter delay of TBD (3600) ns */ -#define COMP_E_CTL1_PWRMD_OFS ( 8) /*!< CEPWRMD Bit Offset */ -#define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /*!< CEPWRMD Bit Mask */ -#define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /*!< PWRMD Bit 0 */ -#define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /*!< PWRMD Bit 1 */ -#define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /*!< High-speed mode */ -#define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /*!< Normal mode */ -#define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /*!< Ultra-low power mode */ -#define COMP_E_CTL1_ON_OFS (10) /*!< CEON Bit Offset */ -#define COMP_E_CTL1_ON ((uint16_t)0x0400) /*!< Comparator On */ -#define COMP_E_CTL1_MRVL_OFS (11) /*!< CEMRVL Bit Offset */ -#define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /*!< This bit is valid of CEMRVS is set to 1 */ -#define COMP_E_CTL1_MRVS_OFS (12) /*!< CEMRVS Bit Offset */ -#define COMP_E_CTL1_MRVS ((uint16_t)0x1000) -#define COMP_E_CTL2_REF0_OFS ( 0) /*!< CEREF0 Bit Offset */ -#define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /*!< CEREF0 Bit Mask */ -#define COMP_E_CTL2_REF00 ((uint16_t)0x0001) /*!< REF0 Bit 0 */ -#define COMP_E_CTL2_REF01 ((uint16_t)0x0002) /*!< REF0 Bit 1 */ -#define COMP_E_CTL2_REF02 ((uint16_t)0x0004) /*!< REF0 Bit 2 */ -#define COMP_E_CTL2_REF03 ((uint16_t)0x0008) /*!< REF0 Bit 3 */ -#define COMP_E_CTL2_REF04 ((uint16_t)0x0010) /*!< REF0 Bit 4 */ -#define COMP_E_CTL2_REF0_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ -#define COMP_E_CTL2_REF0_1 ((uint16_t)0x0001) /*!< Reference resistor tap for setting 1. */ -#define COMP_E_CTL2_REF0_2 ((uint16_t)0x0002) /*!< Reference resistor tap for setting 2. */ -#define COMP_E_CTL2_REF0_3 ((uint16_t)0x0003) /*!< Reference resistor tap for setting 3. */ -#define COMP_E_CTL2_REF0_4 ((uint16_t)0x0004) /*!< Reference resistor tap for setting 4. */ -#define COMP_E_CTL2_REF0_5 ((uint16_t)0x0005) /*!< Reference resistor tap for setting 5. */ -#define COMP_E_CTL2_REF0_6 ((uint16_t)0x0006) /*!< Reference resistor tap for setting 6. */ -#define COMP_E_CTL2_REF0_7 ((uint16_t)0x0007) /*!< Reference resistor tap for setting 7. */ -#define COMP_E_CTL2_REF0_8 ((uint16_t)0x0008) /*!< Reference resistor tap for setting 8. */ -#define COMP_E_CTL2_REF0_9 ((uint16_t)0x0009) /*!< Reference resistor tap for setting 9. */ -#define COMP_E_CTL2_REF0_10 ((uint16_t)0x000A) /*!< Reference resistor tap for setting 10. */ -#define COMP_E_CTL2_REF0_11 ((uint16_t)0x000B) /*!< Reference resistor tap for setting 11. */ -#define COMP_E_CTL2_REF0_12 ((uint16_t)0x000C) /*!< Reference resistor tap for setting 12. */ -#define COMP_E_CTL2_REF0_13 ((uint16_t)0x000D) /*!< Reference resistor tap for setting 13. */ -#define COMP_E_CTL2_REF0_14 ((uint16_t)0x000E) /*!< Reference resistor tap for setting 14. */ -#define COMP_E_CTL2_REF0_15 ((uint16_t)0x000F) /*!< Reference resistor tap for setting 15. */ -#define COMP_E_CTL2_REF0_16 ((uint16_t)0x0010) /*!< Reference resistor tap for setting 16. */ -#define COMP_E_CTL2_REF0_17 ((uint16_t)0x0011) /*!< Reference resistor tap for setting 17. */ -#define COMP_E_CTL2_REF0_18 ((uint16_t)0x0012) /*!< Reference resistor tap for setting 18. */ -#define COMP_E_CTL2_REF0_19 ((uint16_t)0x0013) /*!< Reference resistor tap for setting 19. */ -#define COMP_E_CTL2_REF0_20 ((uint16_t)0x0014) /*!< Reference resistor tap for setting 20. */ -#define COMP_E_CTL2_REF0_21 ((uint16_t)0x0015) /*!< Reference resistor tap for setting 21. */ -#define COMP_E_CTL2_REF0_22 ((uint16_t)0x0016) /*!< Reference resistor tap for setting 22. */ -#define COMP_E_CTL2_REF0_23 ((uint16_t)0x0017) /*!< Reference resistor tap for setting 23. */ -#define COMP_E_CTL2_REF0_24 ((uint16_t)0x0018) /*!< Reference resistor tap for setting 24. */ -#define COMP_E_CTL2_REF0_25 ((uint16_t)0x0019) /*!< Reference resistor tap for setting 25. */ -#define COMP_E_CTL2_REF0_26 ((uint16_t)0x001A) /*!< Reference resistor tap for setting 26. */ -#define COMP_E_CTL2_REF0_27 ((uint16_t)0x001B) /*!< Reference resistor tap for setting 27. */ -#define COMP_E_CTL2_REF0_28 ((uint16_t)0x001C) /*!< Reference resistor tap for setting 28. */ -#define COMP_E_CTL2_REF0_29 ((uint16_t)0x001D) /*!< Reference resistor tap for setting 29. */ -#define COMP_E_CTL2_REF0_30 ((uint16_t)0x001E) /*!< Reference resistor tap for setting 30. */ -#define COMP_E_CTL2_REF0_31 ((uint16_t)0x001F) /*!< Reference resistor tap for setting 31. */ -#define COMP_E_CTL2_RSEL_OFS ( 5) /*!< CERSEL Bit Offset */ -#define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /*!< Reference select */ -#define COMP_E_CTL2_RS_OFS ( 6) /*!< CERS Bit Offset */ -#define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /*!< CERS Bit Mask */ -#define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /*!< RS Bit 0 */ -#define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /*!< RS Bit 1 */ -#define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /*!< No current is drawn by the reference circuitry */ -#define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /*!< VCC applied to the resistor ladder */ -#define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /*!< Shared reference voltage applied to the resistor ladder */ -#define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ -#define COMP_E_CTL2_REF1_OFS ( 8) /*!< CEREF1 Bit Offset */ -#define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /*!< CEREF1 Bit Mask */ -#define COMP_E_CTL2_REF10 ((uint16_t)0x0100) /*!< REF1 Bit 0 */ -#define COMP_E_CTL2_REF11 ((uint16_t)0x0200) /*!< REF1 Bit 1 */ -#define COMP_E_CTL2_REF12 ((uint16_t)0x0400) /*!< REF1 Bit 2 */ -#define COMP_E_CTL2_REF13 ((uint16_t)0x0800) /*!< REF1 Bit 3 */ -#define COMP_E_CTL2_REF14 ((uint16_t)0x1000) /*!< REF1 Bit 4 */ -#define COMP_E_CTL2_REF1_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ -#define COMP_E_CTL2_REF1_1 ((uint16_t)0x0100) /*!< Reference resistor tap for setting 1. */ -#define COMP_E_CTL2_REF1_2 ((uint16_t)0x0200) /*!< Reference resistor tap for setting 2. */ -#define COMP_E_CTL2_REF1_3 ((uint16_t)0x0300) /*!< Reference resistor tap for setting 3. */ -#define COMP_E_CTL2_REF1_4 ((uint16_t)0x0400) /*!< Reference resistor tap for setting 4. */ -#define COMP_E_CTL2_REF1_5 ((uint16_t)0x0500) /*!< Reference resistor tap for setting 5. */ -#define COMP_E_CTL2_REF1_6 ((uint16_t)0x0600) /*!< Reference resistor tap for setting 6. */ -#define COMP_E_CTL2_REF1_7 ((uint16_t)0x0700) /*!< Reference resistor tap for setting 7. */ -#define COMP_E_CTL2_REF1_8 ((uint16_t)0x0800) /*!< Reference resistor tap for setting 8. */ -#define COMP_E_CTL2_REF1_9 ((uint16_t)0x0900) /*!< Reference resistor tap for setting 9. */ -#define COMP_E_CTL2_REF1_10 ((uint16_t)0x0A00) /*!< Reference resistor tap for setting 10. */ -#define COMP_E_CTL2_REF1_11 ((uint16_t)0x0B00) /*!< Reference resistor tap for setting 11. */ -#define COMP_E_CTL2_REF1_12 ((uint16_t)0x0C00) /*!< Reference resistor tap for setting 12. */ -#define COMP_E_CTL2_REF1_13 ((uint16_t)0x0D00) /*!< Reference resistor tap for setting 13. */ -#define COMP_E_CTL2_REF1_14 ((uint16_t)0x0E00) /*!< Reference resistor tap for setting 14. */ -#define COMP_E_CTL2_REF1_15 ((uint16_t)0x0F00) /*!< Reference resistor tap for setting 15. */ -#define COMP_E_CTL2_REF1_16 ((uint16_t)0x1000) /*!< Reference resistor tap for setting 16. */ -#define COMP_E_CTL2_REF1_17 ((uint16_t)0x1100) /*!< Reference resistor tap for setting 17. */ -#define COMP_E_CTL2_REF1_18 ((uint16_t)0x1200) /*!< Reference resistor tap for setting 18. */ -#define COMP_E_CTL2_REF1_19 ((uint16_t)0x1300) /*!< Reference resistor tap for setting 19. */ -#define COMP_E_CTL2_REF1_20 ((uint16_t)0x1400) /*!< Reference resistor tap for setting 20. */ -#define COMP_E_CTL2_REF1_21 ((uint16_t)0x1500) /*!< Reference resistor tap for setting 21. */ -#define COMP_E_CTL2_REF1_22 ((uint16_t)0x1600) /*!< Reference resistor tap for setting 22. */ -#define COMP_E_CTL2_REF1_23 ((uint16_t)0x1700) /*!< Reference resistor tap for setting 23. */ -#define COMP_E_CTL2_REF1_24 ((uint16_t)0x1800) /*!< Reference resistor tap for setting 24. */ -#define COMP_E_CTL2_REF1_25 ((uint16_t)0x1900) /*!< Reference resistor tap for setting 25. */ -#define COMP_E_CTL2_REF1_26 ((uint16_t)0x1A00) /*!< Reference resistor tap for setting 26. */ -#define COMP_E_CTL2_REF1_27 ((uint16_t)0x1B00) /*!< Reference resistor tap for setting 27. */ -#define COMP_E_CTL2_REF1_28 ((uint16_t)0x1C00) /*!< Reference resistor tap for setting 28. */ -#define COMP_E_CTL2_REF1_29 ((uint16_t)0x1D00) /*!< Reference resistor tap for setting 29. */ -#define COMP_E_CTL2_REF1_30 ((uint16_t)0x1E00) /*!< Reference resistor tap for setting 30. */ -#define COMP_E_CTL2_REF1_31 ((uint16_t)0x1F00) /*!< Reference resistor tap for setting 31. */ -#define COMP_E_CTL2_REFL_OFS (13) /*!< CEREFL Bit Offset */ -#define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /*!< CEREFL Bit Mask */ -#define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /*!< REFL Bit 0 */ -#define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /*!< REFL Bit 1 */ -#define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ -#define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ -#define COMP_E_CTL2_REFACC_OFS (15) /*!< CEREFACC Bit Offset */ -#define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /*!< Reference accuracy */ -#define COMP_E_CTL3_PD0_OFS ( 0) /*!< CEPD0 Bit Offset */ -#define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /*!< Port disable */ -#define COMP_E_CTL3_PD1_OFS ( 1) /*!< CEPD1 Bit Offset */ -#define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /*!< Port disable */ -#define COMP_E_CTL3_PD2_OFS ( 2) /*!< CEPD2 Bit Offset */ -#define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /*!< Port disable */ -#define COMP_E_CTL3_PD3_OFS ( 3) /*!< CEPD3 Bit Offset */ -#define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /*!< Port disable */ -#define COMP_E_CTL3_PD4_OFS ( 4) /*!< CEPD4 Bit Offset */ -#define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /*!< Port disable */ -#define COMP_E_CTL3_PD5_OFS ( 5) /*!< CEPD5 Bit Offset */ -#define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /*!< Port disable */ -#define COMP_E_CTL3_PD6_OFS ( 6) /*!< CEPD6 Bit Offset */ -#define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /*!< Port disable */ -#define COMP_E_CTL3_PD7_OFS ( 7) /*!< CEPD7 Bit Offset */ -#define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /*!< Port disable */ -#define COMP_E_CTL3_PD8_OFS ( 8) /*!< CEPD8 Bit Offset */ -#define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /*!< Port disable */ -#define COMP_E_CTL3_PD9_OFS ( 9) /*!< CEPD9 Bit Offset */ -#define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /*!< Port disable */ -#define COMP_E_CTL3_PD10_OFS (10) /*!< CEPD10 Bit Offset */ -#define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /*!< Port disable */ -#define COMP_E_CTL3_PD11_OFS (11) /*!< CEPD11 Bit Offset */ -#define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /*!< Port disable */ -#define COMP_E_CTL3_PD12_OFS (12) /*!< CEPD12 Bit Offset */ -#define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /*!< Port disable */ -#define COMP_E_CTL3_PD13_OFS (13) /*!< CEPD13 Bit Offset */ -#define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /*!< Port disable */ -#define COMP_E_CTL3_PD14_OFS (14) /*!< CEPD14 Bit Offset */ -#define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /*!< Port disable */ -#define COMP_E_CTL3_PD15_OFS (15) /*!< CEPD15 Bit Offset */ -#define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /*!< Port disable */ -#define COMP_E_INT_IFG_OFS ( 0) /*!< CEIFG Bit Offset */ -#define COMP_E_INT_IFG ((uint16_t)0x0001) /*!< Comparator output interrupt flag */ -#define COMP_E_INT_IIFG_OFS ( 1) /*!< CEIIFG Bit Offset */ -#define COMP_E_INT_IIFG ((uint16_t)0x0002) /*!< Comparator output inverted interrupt flag */ -#define COMP_E_INT_RDYIFG_OFS ( 4) /*!< CERDYIFG Bit Offset */ -#define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /*!< Comparator ready interrupt flag */ -#define COMP_E_INT_IE_OFS ( 8) /*!< CEIE Bit Offset */ -#define COMP_E_INT_IE ((uint16_t)0x0100) /*!< Comparator output interrupt enable */ -#define COMP_E_INT_IIE_OFS ( 9) /*!< CEIIE Bit Offset */ -#define COMP_E_INT_IIE ((uint16_t)0x0200) /*!< Comparator output interrupt enable inverted polarity */ -#define COMP_E_INT_RDYIE_OFS (12) /*!< CERDYIE Bit Offset */ -#define COMP_E_INT_RDYIE ((uint16_t)0x1000) /*!< Comparator ready interrupt enable */ -#define CS_KEY_KEY_OFS ( 0) /*!< CSKEY Bit Offset */ -#define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< CSKEY Bit Mask */ -#define CS_CTL0_DCOTUNE_OFS ( 0) /*!< DCOTUNE Bit Offset */ -#define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /*!< DCOTUNE Bit Mask */ -#define CS_CTL0_DCORSEL_OFS (16) /*!< DCORSEL Bit Offset */ -#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /*!< DCORSEL Bit Mask */ -#define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /*!< DCORSEL Bit 0 */ -#define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /*!< DCORSEL Bit 1 */ -#define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /*!< DCORSEL Bit 2 */ -#define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */ -#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */ -#define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */ -#define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */ -#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */ -#define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */ -#define CS_CTL0_DCORES_OFS (22) /*!< DCORES Bit Offset */ -#define CS_CTL0_DCORES ((uint32_t)0x00400000) /*!< Enables the DCO external resistor mode */ -#define CS_CTL0_DCOEN_OFS (23) /*!< DCOEN Bit Offset */ -#define CS_CTL0_DCOEN ((uint32_t)0x00800000) /*!< Enables the DCO oscillator */ -#define CS_CTL1_SELM_OFS ( 0) /*!< SELM Bit Offset */ -#define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /*!< SELM Bit Mask */ -#define CS_CTL1_SELM0 ((uint32_t)0x00000001) /*!< SELM Bit 0 */ -#define CS_CTL1_SELM1 ((uint32_t)0x00000002) /*!< SELM Bit 1 */ -#define CS_CTL1_SELM2 ((uint32_t)0x00000004) /*!< SELM Bit 2 */ -#define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM_1 ((uint32_t)0x00000001) -#define CS_CTL1_SELM_2 ((uint32_t)0x00000002) -#define CS_CTL1_SELM_3 ((uint32_t)0x00000003) -#define CS_CTL1_SELM_4 ((uint32_t)0x00000004) -#define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001) -#define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002) -#define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003) -#define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004) -#define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELS_OFS ( 4) /*!< SELS Bit Offset */ -#define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /*!< SELS Bit Mask */ -#define CS_CTL1_SELS0 ((uint32_t)0x00000010) /*!< SELS Bit 0 */ -#define CS_CTL1_SELS1 ((uint32_t)0x00000020) /*!< SELS Bit 1 */ -#define CS_CTL1_SELS2 ((uint32_t)0x00000040) /*!< SELS Bit 2 */ -#define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS_1 ((uint32_t)0x00000010) -#define CS_CTL1_SELS_2 ((uint32_t)0x00000020) -#define CS_CTL1_SELS_3 ((uint32_t)0x00000030) -#define CS_CTL1_SELS_4 ((uint32_t)0x00000040) -#define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010) -#define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020) -#define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030) -#define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040) -#define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ -#define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ -#define CS_CTL1_SELA_OFS ( 8) /*!< SELA Bit Offset */ -#define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /*!< SELA Bit Mask */ -#define CS_CTL1_SELA0 ((uint32_t)0x00000100) /*!< SELA Bit 0 */ -#define CS_CTL1_SELA1 ((uint32_t)0x00000200) /*!< SELA Bit 1 */ -#define CS_CTL1_SELA2 ((uint32_t)0x00000400) /*!< SELA Bit 2 */ -#define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA_1 ((uint32_t)0x00000100) -#define CS_CTL1_SELA_2 ((uint32_t)0x00000200) -#define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ -#define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100) -#define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200) -#define CS_CTL1_SELB_OFS (12) /*!< SELB Bit Offset */ -#define CS_CTL1_SELB ((uint32_t)0x00001000) /*!< Selects the BCLK source */ -#define CS_CTL1_DIVM_OFS (16) /*!< DIVM Bit Offset */ -#define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /*!< DIVM Bit Mask */ -#define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /*!< DIVM Bit 0 */ -#define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /*!< DIVM Bit 1 */ -#define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /*!< DIVM Bit 2 */ -#define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -#define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ -#define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ -#define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ -#define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ -#define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ -#define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ -#define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ -#define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ -#define CS_CTL1_DIVHS_OFS (20) /*!< DIVHS Bit Offset */ -#define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /*!< DIVHS Bit Mask */ -#define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /*!< DIVHS Bit 0 */ -#define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /*!< DIVHS Bit 1 */ -#define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /*!< DIVHS Bit 2 */ -#define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -#define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ -#define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ -#define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ -#define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ -#define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ -#define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ -#define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ -#define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ -#define CS_CTL1_DIVA_OFS (24) /*!< DIVA Bit Offset */ -#define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /*!< DIVA Bit Mask */ -#define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /*!< DIVA Bit 0 */ -#define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /*!< DIVA Bit 1 */ -#define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /*!< DIVA Bit 2 */ -#define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -#define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ -#define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ -#define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ -#define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ -#define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ -#define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ -#define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ -#define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ -#define CS_CTL1_DIVS_OFS (28) /*!< DIVS Bit Offset */ -#define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /*!< DIVS Bit Mask */ -#define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /*!< DIVS Bit 0 */ -#define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /*!< DIVS Bit 1 */ -#define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /*!< DIVS Bit 2 */ -#define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -#define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ -#define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ -#define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ -#define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ -#define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ -#define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ -#define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ -#define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ -#define CS_CTL2_LFXTDRIVE_OFS ( 0) /*!< LFXTDRIVE Bit Offset */ -#define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /*!< LFXTDRIVE Bit Mask */ -#define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /*!< LFXTDRIVE Bit 0 */ -#define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /*!< LFXTDRIVE Bit 1 */ -#define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /*!< Lowest drive strength and current consumption LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /*!< Increased drive strength LFXT oscillator. */ -#define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */ -#define CS_CTL2_LFXT_EN_OFS ( 8) /*!< LFXT_EN Bit Offset */ -#define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /*!< Turns on the LFXT oscillator regardless if used as a clock resource */ -#define CS_CTL2_LFXTBYPASS_OFS ( 9) /*!< LFXTBYPASS Bit Offset */ -#define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /*!< LFXT bypass select */ -#define CS_CTL2_HFXTDRIVE_OFS (16) /*!< HFXTDRIVE Bit Offset */ -#define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /*!< HFXT oscillator drive selection */ -#define CS_CTL2_HFXTFREQ_OFS (20) /*!< HFXTFREQ Bit Offset */ -#define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /*!< HFXTFREQ Bit Mask */ -#define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /*!< HFXTFREQ Bit 0 */ -#define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /*!< HFXTFREQ Bit 1 */ -#define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /*!< HFXTFREQ Bit 2 */ -#define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /*!< 1 MHz to 4 MHz */ -#define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /*!< >4 MHz to 8 MHz */ -#define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /*!< >8 MHz to 16 MHz */ -#define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /*!< >16 MHz to 24 MHz */ -#define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /*!< >24 MHz to 32 MHz */ -#define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /*!< >32 MHz to 40 MHz */ -#define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /*!< >40 MHz to 48 MHz */ -#define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /*!< Reserved for future use. */ -#define CS_CTL2_HFXT_EN_OFS (24) /*!< HFXT_EN Bit Offset */ -#define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /*!< Turns on the HFXT oscillator regardless if used as a clock resource */ -#define CS_CTL2_HFXTBYPASS_OFS (25) /*!< HFXTBYPASS Bit Offset */ -#define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /*!< HFXT bypass select */ -#define CS_CTL3_FCNTLF_OFS ( 0) /*!< FCNTLF Bit Offset */ -#define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /*!< FCNTLF Bit Mask */ -#define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /*!< FCNTLF Bit 0 */ -#define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /*!< FCNTLF Bit 1 */ -#define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /*!< 32768 cycles */ -#define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /*!< 4096 cycles */ -#define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /*!< 8192 cycles */ -#define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /*!< 16384 cycles */ -#define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /*!< 32768 cycles */ -#define CS_CTL3_RFCNTLF_OFS ( 2) /*!< RFCNTLF Bit Offset */ -#define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /*!< Reset start fault counter for LFXT */ -#define CS_CTL3_FCNTLF_EN_OFS ( 3) /*!< FCNTLF_EN Bit Offset */ -#define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /*!< Enable start fault counter for LFXT */ -#define CS_CTL3_FCNTHF_OFS ( 4) /*!< FCNTHF Bit Offset */ -#define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /*!< FCNTHF Bit Mask */ -#define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /*!< FCNTHF Bit 0 */ -#define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /*!< FCNTHF Bit 1 */ -#define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /*!< 16384 cycles */ -#define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /*!< 16384 cycles */ -#define CS_CTL3_RFCNTHF_OFS ( 6) /*!< RFCNTHF Bit Offset */ -#define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /*!< Reset start fault counter for HFXT */ -#define CS_CTL3_FCNTHF_EN_OFS ( 7) /*!< FCNTHF_EN Bit Offset */ -#define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /*!< Enable start fault counter for HFXT */ -#define CS_CLKEN_ACLK_EN_OFS ( 0) /*!< ACLK_EN Bit Offset */ -#define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /*!< ACLK system clock conditional request enable */ -#define CS_CLKEN_MCLK_EN_OFS ( 1) /*!< MCLK_EN Bit Offset */ -#define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /*!< MCLK system clock conditional request enable */ -#define CS_CLKEN_HSMCLK_EN_OFS ( 2) /*!< HSMCLK_EN Bit Offset */ -#define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /*!< HSMCLK system clock conditional request enable */ -#define CS_CLKEN_SMCLK_EN_OFS ( 3) /*!< SMCLK_EN Bit Offset */ -#define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /*!< SMCLK system clock conditional request enable */ -#define CS_CLKEN_VLO_EN_OFS ( 8) /*!< VLO_EN Bit Offset */ -#define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /*!< Turns on the VLO oscillator */ -#define CS_CLKEN_REFO_EN_OFS ( 9) /*!< REFO_EN Bit Offset */ -#define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /*!< Turns on the REFO oscillator */ -#define CS_CLKEN_MODOSC_EN_OFS (10) /*!< MODOSC_EN Bit Offset */ -#define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /*!< Turns on the MODOSC oscillator */ -#define CS_CLKEN_REFOFSEL_OFS (15) /*!< REFOFSEL Bit Offset */ -#define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /*!< Selects REFO nominal frequency */ -#define CS_STAT_DCO_ON_OFS ( 0) /*!< DCO_ON Bit Offset */ -#define CS_STAT_DCO_ON ((uint32_t)0x00000001) /*!< DCO status */ -#define CS_STAT_DCOBIAS_ON_OFS ( 1) /*!< DCOBIAS_ON Bit Offset */ -#define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /*!< DCO bias status */ -#define CS_STAT_HFXT_ON_OFS ( 2) /*!< HFXT_ON Bit Offset */ -#define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /*!< HFXT status */ -#define CS_STAT_MODOSC_ON_OFS ( 4) /*!< MODOSC_ON Bit Offset */ -#define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /*!< MODOSC status */ -#define CS_STAT_VLO_ON_OFS ( 5) /*!< VLO_ON Bit Offset */ -#define CS_STAT_VLO_ON ((uint32_t)0x00000020) /*!< VLO status */ -#define CS_STAT_LFXT_ON_OFS ( 6) /*!< LFXT_ON Bit Offset */ -#define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /*!< LFXT status */ -#define CS_STAT_REFO_ON_OFS ( 7) /*!< REFO_ON Bit Offset */ -#define CS_STAT_REFO_ON ((uint32_t)0x00000080) /*!< REFO status */ -#define CS_STAT_ACLK_ON_OFS (16) /*!< ACLK_ON Bit Offset */ -#define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /*!< ACLK system clock status */ -#define CS_STAT_MCLK_ON_OFS (17) /*!< MCLK_ON Bit Offset */ -#define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /*!< MCLK system clock status */ -#define CS_STAT_HSMCLK_ON_OFS (18) /*!< HSMCLK_ON Bit Offset */ -#define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /*!< HSMCLK system clock status */ -#define CS_STAT_SMCLK_ON_OFS (19) /*!< SMCLK_ON Bit Offset */ -#define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /*!< SMCLK system clock status */ -#define CS_STAT_MODCLK_ON_OFS (20) /*!< MODCLK_ON Bit Offset */ -#define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /*!< MODCLK system clock status */ -#define CS_STAT_VLOCLK_ON_OFS (21) /*!< VLOCLK_ON Bit Offset */ -#define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /*!< VLOCLK system clock status */ -#define CS_STAT_LFXTCLK_ON_OFS (22) /*!< LFXTCLK_ON Bit Offset */ -#define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /*!< LFXTCLK system clock status */ -#define CS_STAT_REFOCLK_ON_OFS (23) /*!< REFOCLK_ON Bit Offset */ -#define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /*!< REFOCLK system clock status */ -#define CS_STAT_ACLK_READY_OFS (24) /*!< ACLK_READY Bit Offset */ -#define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /*!< ACLK Ready status */ -#define CS_STAT_MCLK_READY_OFS (25) /*!< MCLK_READY Bit Offset */ -#define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /*!< MCLK Ready status */ -#define CS_STAT_HSMCLK_READY_OFS (26) /*!< HSMCLK_READY Bit Offset */ -#define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /*!< HSMCLK Ready status */ -#define CS_STAT_SMCLK_READY_OFS (27) /*!< SMCLK_READY Bit Offset */ -#define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /*!< SMCLK Ready status */ -#define CS_STAT_BCLK_READY_OFS (28) /*!< BCLK_READY Bit Offset */ -#define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /*!< BCLK Ready status */ -#define CS_IE_LFXTIE_OFS ( 0) /*!< LFXTIE Bit Offset */ -#define CS_IE_LFXTIE ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag interrupt enable */ -#define CS_IE_HFXTIE_OFS ( 1) /*!< HFXTIE Bit Offset */ -#define CS_IE_HFXTIE ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag interrupt enable */ -#define CS_IE_DCOR_OPNIE_OFS ( 6) /*!< DCOR_OPNIE Bit Offset */ -#define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag interrupt enable. */ -#define CS_IE_FCNTLFIE_OFS ( 8) /*!< FCNTLFIE Bit Offset */ -#define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /*!< Start fault counter interrupt enable LFXT */ -#define CS_IE_FCNTHFIE_OFS ( 9) /*!< FCNTHFIE Bit Offset */ -#define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /*!< Start fault counter interrupt enable HFXT */ -#define CS_IFG_LFXTIFG_OFS ( 0) /*!< LFXTIFG Bit Offset */ -#define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag */ -#define CS_IFG_HFXTIFG_OFS ( 1) /*!< HFXTIFG Bit Offset */ -#define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag */ -#define CS_IFG_DCOR_SHTIFG_OFS ( 5) /*!< DCOR_SHTIFG Bit Offset */ -#define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /*!< DCO external resistor short circuit fault flag. */ -#define CS_IFG_DCOR_OPNIFG_OFS ( 6) /*!< DCOR_OPNIFG Bit Offset */ -#define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag. */ -#define CS_IFG_FCNTLFIFG_OFS ( 8) /*!< FCNTLFIFG Bit Offset */ -#define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter interrupt flag LFXT */ -#define CS_IFG_FCNTHFIFG_OFS ( 9) /*!< FCNTHFIFG Bit Offset */ -#define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter interrupt flag HFXT */ -#define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /*!< CLR_LFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /*!< Clear LFXT oscillator fault interrupt flag */ -#define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /*!< CLR_HFXTIFG Bit Offset */ -#define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /*!< Clear HFXT oscillator fault interrupt flag */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /*!< CLR_DCOR_OPNIFG Bit Offset */ -#define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Clear DCO external resistor open circuit fault interrupt flag. */ -#define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /*!< CLR_FCNTLFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter clear interrupt flag LFXT */ -#define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /*!< CLR_FCNTHFIFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter clear interrupt flag HFXT */ -#define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /*!< SET_LFXTIFG Bit Offset */ -#define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /*!< Set LFXT oscillator fault interrupt flag */ -#define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /*!< SET_HFXTIFG Bit Offset */ -#define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /*!< Set HFXT oscillator fault interrupt flag */ -#define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /*!< SET_DCOR_OPNIFG Bit Offset */ -#define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Set DCO external resistor open circuit fault interrupt flag. */ -#define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /*!< SET_FCNTHFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter set interrupt flag HFXT */ -#define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /*!< SET_FCNTLFIFG Bit Offset */ -#define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter set interrupt flag LFXT */ -#define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /*!< DCO_TCCAL Bit Offset */ -#define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /*!< DCO_TCCAL Bit Mask */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /*!< DCO_FCAL_RSEL04 Bit Offset */ -#define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /*!< DCO_FCAL_RSEL04 Bit Mask */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /*!< DCO_FCAL_RSEL5 Bit Offset */ -#define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /*!< DCO_FCAL_RSEL5 Bit Mask */ -#define CS_KEY_VAL ((uint32_t)0x0000695A) /*!< CS control key value */ -#define DIO_PORT_IV_OFS ( 0) /*!< DIO Port IV Bit Offset */ -#define DIO_PORT_IV_MASK ((uint16_t)0x001F) /*!< DIO Port IV Bit Mask */ -#define DIO_PORT_IV0 ((uint16_t)0x0001) /*!< DIO Port IV Bit 0 */ -#define DIO_PORT_IV1 ((uint16_t)0x0002) /*!< DIO Port IV Bit 1 */ -#define DIO_PORT_IV2 ((uint16_t)0x0004) /*!< DIO Port IV Bit 2 */ -#define DIO_PORT_IV3 ((uint16_t)0x0008) /*!< DIO Port IV Bit 3 */ -#define DIO_PORT_IV4 ((uint16_t)0x0010) /*!< DIO Port IV Bit 4 */ -#define DIO_PORT_IV_0 ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV_2 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ -#define DIO_PORT_IV_4 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV_6 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV_8 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV_10 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV_12 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV_14 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV_16 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ -#define DIO_PORT_IV__NONE ((uint16_t)0x0000) /*!< No interrupt pending */ -#define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ -#define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ -#define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ -#define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ -#define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ -#define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ -#define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ -#define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /*!< NUM_DMA_CHANNELS Bit Offset */ -#define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /*!< NUM_DMA_CHANNELS Bit Mask */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /*!< NUM_SRC_PER_CHANNEL Bit Offset */ -#define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /*!< NUM_SRC_PER_CHANNEL Bit Mask */ -#define DMA_SW_CHTRIG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /*!< Write 1, triggers DMA_CHANNEL0 */ -#define DMA_SW_CHTRIG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /*!< Write 1, triggers DMA_CHANNEL1 */ -#define DMA_SW_CHTRIG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /*!< Write 1, triggers DMA_CHANNEL2 */ -#define DMA_SW_CHTRIG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /*!< Write 1, triggers DMA_CHANNEL3 */ -#define DMA_SW_CHTRIG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /*!< Write 1, triggers DMA_CHANNEL4 */ -#define DMA_SW_CHTRIG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /*!< Write 1, triggers DMA_CHANNEL5 */ -#define DMA_SW_CHTRIG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /*!< Write 1, triggers DMA_CHANNEL6 */ -#define DMA_SW_CHTRIG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /*!< Write 1, triggers DMA_CHANNEL7 */ -#define DMA_SW_CHTRIG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /*!< Write 1, triggers DMA_CHANNEL8 */ -#define DMA_SW_CHTRIG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /*!< Write 1, triggers DMA_CHANNEL9 */ -#define DMA_SW_CHTRIG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /*!< Write 1, triggers DMA_CHANNEL10 */ -#define DMA_SW_CHTRIG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /*!< Write 1, triggers DMA_CHANNEL11 */ -#define DMA_SW_CHTRIG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /*!< Write 1, triggers DMA_CHANNEL12 */ -#define DMA_SW_CHTRIG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /*!< Write 1, triggers DMA_CHANNEL13 */ -#define DMA_SW_CHTRIG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /*!< Write 1, triggers DMA_CHANNEL14 */ -#define DMA_SW_CHTRIG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /*!< Write 1, triggers DMA_CHANNEL15 */ -#define DMA_SW_CHTRIG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /*!< Write 1, triggers DMA_CHANNEL16 */ -#define DMA_SW_CHTRIG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /*!< Write 1, triggers DMA_CHANNEL17 */ -#define DMA_SW_CHTRIG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /*!< Write 1, triggers DMA_CHANNEL18 */ -#define DMA_SW_CHTRIG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /*!< Write 1, triggers DMA_CHANNEL19 */ -#define DMA_SW_CHTRIG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /*!< Write 1, triggers DMA_CHANNEL20 */ -#define DMA_SW_CHTRIG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /*!< Write 1, triggers DMA_CHANNEL21 */ -#define DMA_SW_CHTRIG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /*!< Write 1, triggers DMA_CHANNEL22 */ -#define DMA_SW_CHTRIG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /*!< Write 1, triggers DMA_CHANNEL23 */ -#define DMA_SW_CHTRIG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /*!< Write 1, triggers DMA_CHANNEL24 */ -#define DMA_SW_CHTRIG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /*!< Write 1, triggers DMA_CHANNEL25 */ -#define DMA_SW_CHTRIG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /*!< Write 1, triggers DMA_CHANNEL26 */ -#define DMA_SW_CHTRIG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /*!< Write 1, triggers DMA_CHANNEL27 */ -#define DMA_SW_CHTRIG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /*!< Write 1, triggers DMA_CHANNEL28 */ -#define DMA_SW_CHTRIG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /*!< Write 1, triggers DMA_CHANNEL29 */ -#define DMA_SW_CHTRIG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /*!< Write 1, triggers DMA_CHANNEL30 */ -#define DMA_SW_CHTRIG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /*!< Write 1, triggers DMA_CHANNEL31 */ -#define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /*!< DMA_SRC Bit Offset */ -#define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /*!< DMA_SRC Bit Mask */ -#define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -#define DMA_INT1_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT1 mapping */ -#define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -#define DMA_INT2_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT2 mapping */ -#define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ -#define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ -#define DMA_INT3_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ -#define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT3 mapping */ -#define DMA_INT0_SRCFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /*!< Channel 0 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /*!< Channel 1 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /*!< Channel 2 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /*!< Channel 3 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /*!< Channel 4 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /*!< Channel 5 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /*!< Channel 6 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /*!< Channel 7 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /*!< Channel 8 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /*!< Channel 9 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /*!< Channel 10 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /*!< Channel 11 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /*!< Channel 12 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /*!< Channel 13 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /*!< Channel 14 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /*!< Channel 15 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /*!< Channel 16 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /*!< Channel 17 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /*!< Channel 18 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /*!< Channel 19 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /*!< Channel 20 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /*!< Channel 21 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /*!< Channel 22 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /*!< Channel 23 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /*!< Channel 24 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /*!< Channel 25 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /*!< Channel 26 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /*!< Channel 27 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /*!< Channel 28 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /*!< Channel 29 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /*!< Channel 30 was the source of DMA_INT0 */ -#define DMA_INT0_SRCFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /*!< Channel 31 was the source of DMA_INT0 */ -#define DMA_INT0_CLRFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ -#define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ -#define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ -#define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ -#define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ -#define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ -#define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ -#define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ -#define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ -#define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ -#define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ -#define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ -#define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ -#define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ -#define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ -#define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ -#define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ -#define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ -#define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ -#define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ -#define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ -#define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ -#define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ -#define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ -#define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ -#define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ -#define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ -#define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ -#define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ -#define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ -#define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ -#define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_INT0_CLRFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ -#define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ -#define DMA_STAT_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_STAT_MASTEN ((uint32_t)0x00000001) -#define DMA_STAT_STATE_OFS ( 4) /*!< STATE Bit Offset */ -#define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /*!< STATE Bit Mask */ -#define DMA_STAT_STATE0 ((uint32_t)0x00000010) /*!< STATE Bit 0 */ -#define DMA_STAT_STATE1 ((uint32_t)0x00000020) /*!< STATE Bit 1 */ -#define DMA_STAT_STATE2 ((uint32_t)0x00000040) /*!< STATE Bit 2 */ -#define DMA_STAT_STATE3 ((uint32_t)0x00000080) /*!< STATE Bit 3 */ -#define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /*!< idle */ -#define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /*!< reading channel controller data */ -#define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /*!< reading source data end pointer */ -#define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /*!< reading destination data end pointer */ -#define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /*!< reading source data */ -#define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /*!< writing destination data */ -#define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /*!< waiting for DMA request to clear */ -#define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /*!< writing channel controller data */ -#define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /*!< stalled */ -#define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /*!< done */ -#define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /*!< peripheral scatter-gather transition */ -#define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /*!< Reserved */ -#define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /*!< Reserved */ -#define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /*!< Reserved */ -#define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /*!< Reserved */ -#define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /*!< Reserved */ -#define DMA_STAT_DMACHANS_OFS (16) /*!< DMACHANS Bit Offset */ -#define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /*!< DMACHANS Bit Mask */ -#define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /*!< DMACHANS Bit 0 */ -#define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /*!< DMACHANS Bit 1 */ -#define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /*!< DMACHANS Bit 2 */ -#define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /*!< DMACHANS Bit 3 */ -#define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /*!< DMACHANS Bit 4 */ -#define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /*!< Controller configured to use 1 DMA channel */ -#define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /*!< Controller configured to use 2 DMA channels */ -#define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /*!< Controller configured to use 31 DMA channels */ -#define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /*!< Controller configured to use 32 DMA channels */ -#define DMA_STAT_TESTSTAT_OFS (28) /*!< TESTSTAT Bit Offset */ -#define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /*!< TESTSTAT Bit Mask */ -#define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /*!< TESTSTAT Bit 0 */ -#define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /*!< TESTSTAT Bit 1 */ -#define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /*!< TESTSTAT Bit 2 */ -#define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /*!< TESTSTAT Bit 3 */ -#define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /*!< Controller does not include the integration test logic */ -#define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /*!< Controller includes the integration test logic */ -#define DMA_CFG_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ -#define DMA_CFG_MASTEN ((uint32_t)0x00000001) -#define DMA_CFG_CHPROTCTRL_OFS ( 5) /*!< CHPROTCTRL Bit Offset */ -#define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /*!< CHPROTCTRL Bit Mask */ -#define DMA_CTLBASE_ADDR_OFS ( 5) /*!< ADDR Bit Offset */ -#define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /*!< ADDR Bit Mask */ -#define DMA_ERRCLR_ERRCLR_OFS ( 0) /*!< ERRCLR Bit Offset */ -#define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) -#define __MCU_NUM_DMA_CHANNELS__ 8 -#define DMA_CHANNEL_CONTROL_STRUCT_SIZE 0x10 -#define DMA_CONTROL_MEMORY_ALIGNMENT (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE) -#define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /*!< Available uDMA Channels Minus 1 */ -#define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /*!< Control State Machine Status */ -#define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /*!< Idle */ -#define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /*!< Reading channel controller data */ -#define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /*!< Reading source end pointer */ -#define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /*!< Reading destination end pointer */ -#define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /*!< Reading source data */ -#define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /*!< Writing destination data */ -#define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /*!< Waiting for uDMA request to clear */ -#define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /*!< Writing channel controller data */ -#define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /*!< Stalled */ -#define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /*!< Done */ -#define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /*!< Undefined */ -#define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /*!< Master Enable Status */ -#define UDMA_STAT_DMACHANS_S (16) -#define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /*!< Controller Master Enable */ -#define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /*!< Channel Control Base Address */ -#define UDMA_CTLBASE_ADDR_S (10) -#define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Alternate Channel Address Pointer */ -#define UDMA_ALTBASE_ADDR_S ( 0) -#define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Wait Status */ -#define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Software Request */ -#define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Set */ -#define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Clear */ -#define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Set */ -#define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Clear */ -#define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Enable Set */ -#define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Clear Channel [n] Enable Clear */ -#define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Set */ -#define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Clear */ -#define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Set */ -#define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Clear */ -#define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /*!< uDMA Bus Error Status */ -#define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Assignment Select */ -#define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /*!< Use the primary channel assignment */ -#define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /*!< Use the secondary channel assignment */ -#define UDMA_O_SRCENDP ((uint32_t)0x00000000) /*!< DMA Channel Source Address End Pointer */ -#define UDMA_O_DSTENDP ((uint32_t)0x00000004) /*!< DMA Channel Destination Address End Pointer */ -#define UDMA_O_CHCTL ((uint32_t)0x00000008) /*!< DMA Channel Control Word */ -#define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Source Address End Pointer */ -#define UDMA_SRCENDP_ADDR_S ( 0) -#define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Destination Address End Pointer */ -#define UDMA_DSTENDP_ADDR_S ( 0) -#define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /*!< Destination Address Increment */ -#define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /*!< Word */ -#define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /*!< No increment */ -#define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /*!< Destination Data Size */ -#define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /*!< Half-word */ -#define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /*!< Source Address Increment */ -#define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /*!< Word */ -#define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /*!< No increment */ -#define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /*!< Source Data Size */ -#define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ -#define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /*!< Half-word */ -#define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /*!< Word */ -#define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /*!< Arbitration Size */ -#define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /*!< 1 Transfer */ -#define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /*!< 2 Transfers */ -#define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /*!< 4 Transfers */ -#define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /*!< 8 Transfers */ -#define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /*!< 16 Transfers */ -#define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /*!< 32 Transfers */ -#define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /*!< 64 Transfers */ -#define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /*!< 128 Transfers */ -#define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /*!< 256 Transfers */ -#define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /*!< 512 Transfers */ -#define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /*!< 1024 Transfers */ -#define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /*!< Transfer Size (minus 1) */ -#define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /*!< Next Useburst */ -#define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /*!< uDMA Transfer Mode */ -#define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /*!< Stop */ -#define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /*!< Basic */ -#define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /*!< Auto-Request */ -#define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /*!< Ping-Pong */ -#define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /*!< Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /*!< Alternate Memory Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /*!< Peripheral Scatter-Gather */ -#define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /*!< Alternate Peripheral Scatter-Gather */ -#define UDMA_CHCTL_XFERSIZE_S ( 4) -#define EUSCI_A_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -#define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /*!< UCTXBRK Bit Offset */ -#define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /*!< Transmit break */ -#define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /*!< UCTXADDR Bit Offset */ -#define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /*!< Transmit address */ -#define EUSCI_A_CTLW0_DORM_OFS ( 3) /*!< UCDORM Bit Offset */ -#define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /*!< Dormant */ -#define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /*!< UCBRKIE Bit Offset */ -#define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /*!< Receive break character interrupt enable */ -#define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /*!< UCRXEIE Bit Offset */ -#define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /*!< Receive erroneous-character interrupt enable */ -#define EUSCI_A_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /*!< UCLK */ -#define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_A_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -#define EUSCI_A_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< UART mode */ -#define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< Idle-line multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< Address-bit multiprocessor mode */ -#define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< UART mode with automatic baud-rate detection */ -#define EUSCI_A_CTLW0_SPB_OFS (11) /*!< UCSPB Bit Offset */ -#define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /*!< Stop bit select */ -#define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -#define EUSCI_A_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -#define EUSCI_A_CTLW0_PAR_OFS (14) /*!< UCPAR Bit Offset */ -#define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /*!< Parity select */ -#define EUSCI_A_CTLW0_PEN_OFS (15) /*!< UCPEN Bit Offset */ -#define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /*!< Parity enable */ -#define EUSCI_A_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -#define EUSCI_A_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -#define EUSCI_A_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -#define EUSCI_A_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -#define EUSCI_A_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< Approximately 2 ns (equivalent of 1 delay element) */ -#define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< Approximately 50 ns */ -#define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< Approximately 100 ns */ -#define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< Approximately 200 ns */ -#define EUSCI_A_MCTLW_OS16_OFS ( 0) /*!< UCOS16 Bit Offset */ -#define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /*!< Oversampling mode enabled */ -#define EUSCI_A_MCTLW_BRF_OFS ( 4) /*!< UCBRF Bit Offset */ -#define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /*!< UCBRF Bit Mask */ -#define EUSCI_A_MCTLW_BRS_OFS ( 8) /*!< UCBRS Bit Offset */ -#define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /*!< UCBRS Bit Mask */ -#define EUSCI_A_STATW_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -#define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /*!< UCADDR_UCIDLE Bit Offset */ -#define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /*!< Address received / Idle line detected */ -#define EUSCI_A_STATW_RXERR_OFS ( 2) /*!< UCRXERR Bit Offset */ -#define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /*!< Receive error flag */ -#define EUSCI_A_STATW_BRK_OFS ( 3) /*!< UCBRK Bit Offset */ -#define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /*!< Break detect flag */ -#define EUSCI_A_STATW_PE_OFS ( 4) /*!< UCPE Bit Offset */ -#define EUSCI_A_STATW_PE ((uint16_t)0x0010) -#define EUSCI_A_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_A_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -#define EUSCI_A_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_A_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -#define EUSCI_A_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -#define EUSCI_A_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_A_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ -#define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -#define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -#define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /*!< UCABDEN Bit Offset */ -#define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /*!< Automatic baud-rate detect enable */ -#define EUSCI_A_ABCTL_BTOE_OFS ( 2) /*!< UCBTOE Bit Offset */ -#define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /*!< Break time out error */ -#define EUSCI_A_ABCTL_STOE_OFS ( 3) /*!< UCSTOE Bit Offset */ -#define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /*!< Synch field time out error */ -#define EUSCI_A_ABCTL_DELIM_OFS ( 4) /*!< UCDELIM Bit Offset */ -#define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /*!< UCDELIM Bit Mask */ -#define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /*!< DELIM Bit 0 */ -#define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /*!< DELIM Bit 1 */ -#define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /*!< 1 bit time */ -#define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /*!< 2 bit times */ -#define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /*!< 3 bit times */ -#define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /*!< 4 bit times */ -#define EUSCI_A_IRCTL_IREN_OFS ( 0) /*!< UCIREN Bit Offset */ -#define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /*!< IrDA encoder/decoder enable */ -#define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /*!< UCIRTXCLK Bit Offset */ -#define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /*!< IrDA transmit pulse clock select */ -#define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /*!< UCIRTXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /*!< UCIRTXPL Bit Mask */ -#define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /*!< UCIRRXFE Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /*!< IrDA receive filter enabled */ -#define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /*!< UCIRRXPL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /*!< IrDA receive input UCAxRXD polarity */ -#define EUSCI_A_IRCTL_IRRXFL_OFS (10) /*!< UCIRRXFL Bit Offset */ -#define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /*!< UCIRRXFL Bit Mask */ -#define EUSCI_A_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -#define EUSCI_A_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -#define EUSCI_A_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /*!< Start bit interrupt enable */ -#define EUSCI_A_IE_TXCPTIE_OFS ( 3) /*!< UCTXCPTIE Bit Offset */ -#define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /*!< Transmit complete interrupt enable */ -#define EUSCI_A_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -#define EUSCI_A_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -#define EUSCI_A_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /*!< Start bit interrupt flag */ -#define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /*!< UCTXCPTIFG Bit Offset */ -#define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /*!< Transmit ready interrupt enable */ -#define EUSCI_A__RXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_A__RXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_A__TXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_A__TXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ -#define EUSCI_B_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ -#define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ -#define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /*!< UCTXSTT Bit Offset */ -#define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /*!< Transmit START condition in master mode */ -#define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /*!< UCTXSTP Bit Offset */ -#define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /*!< Transmit STOP condition in master mode */ -#define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /*!< UCTXNACK Bit Offset */ -#define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /*!< Transmit a NACK */ -#define EUSCI_B_CTLW0_TR_OFS ( 4) /*!< UCTR Bit Offset */ -#define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /*!< Transmitter/receiver */ -#define EUSCI_B_CTLW0_TXACK_OFS ( 5) /*!< UCTXACK Bit Offset */ -#define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /*!< Transmit ACK condition in slave mode */ -#define EUSCI_B_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ -#define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ -#define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ -#define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ -#define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_B_CTLW0_UCSSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ -#define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /*!< UCLKI */ -#define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ -#define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ -#define EUSCI_B_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ -#define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ -#define EUSCI_B_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ -#define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ -#define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ -#define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ -#define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< 3-pin SPI */ -#define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< 4-pin SPI (master or slave enabled if STE = 1) */ -#define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< 4-pin SPI (master or slave enabled if STE = 0) */ -#define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< I2C mode */ -#define EUSCI_B_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ -#define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ -#define EUSCI_B_CTLW0_MM_OFS (13) /*!< UCMM Bit Offset */ -#define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /*!< Multi-master environment select */ -#define EUSCI_B_CTLW0_SLA10_OFS (14) /*!< UCSLA10 Bit Offset */ -#define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /*!< Slave addressing mode select */ -#define EUSCI_B_CTLW0_A10_OFS (15) /*!< UCA10 Bit Offset */ -#define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /*!< Own addressing mode select */ -#define EUSCI_B_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ -#define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ -#define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ -#define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ -#define EUSCI_B_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ -#define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ -#define EUSCI_B_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ -#define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ -#define EUSCI_B_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ -#define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ -#define EUSCI_B_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ -#define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ -#define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ -#define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ -#define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< 50 ns */ -#define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< 25 ns */ -#define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< 12.5 ns */ -#define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< 6.25 ns */ -#define EUSCI_B_CTLW1_ASTP_OFS ( 2) /*!< UCASTP Bit Offset */ -#define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /*!< UCASTP Bit Mask */ -#define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /*!< ASTP Bit 0 */ -#define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /*!< ASTP Bit 1 */ -#define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /*!< No automatic STOP generation. The STOP condition is generated after the user */ -#define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ -#define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /*!< A STOP condition is generated automatically after the byte counter value */ -#define EUSCI_B_CTLW1_SWACK_OFS ( 4) /*!< UCSWACK Bit Offset */ -#define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /*!< SW or HW ACK control */ -#define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /*!< UCSTPNACK Bit Offset */ -#define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /*!< ACK all master bytes */ -#define EUSCI_B_CTLW1_CLTO_OFS ( 6) /*!< UCCLTO Bit Offset */ -#define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /*!< UCCLTO Bit Mask */ -#define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /*!< CLTO Bit 0 */ -#define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /*!< CLTO Bit 1 */ -#define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /*!< Disable clock low timeout counter */ -#define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ -#define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ -#define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ -#define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /*!< UCETXINT Bit Offset */ -#define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /*!< Early UCTXIFG0 */ -#define EUSCI_B_STATW_BBUSY_OFS ( 4) /*!< UCBBUSY Bit Offset */ -#define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /*!< Bus busy */ -#define EUSCI_B_STATW_GC_OFS ( 5) /*!< UCGC Bit Offset */ -#define EUSCI_B_STATW_GC ((uint16_t)0x0020) /*!< General call address received */ -#define EUSCI_B_STATW_SCLLOW_OFS ( 6) /*!< UCSCLLOW Bit Offset */ -#define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /*!< SCL low */ -#define EUSCI_B_STATW_BCNT_OFS ( 8) /*!< UCBCNT Bit Offset */ -#define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /*!< UCBCNT Bit Mask */ -#define EUSCI_B_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ -#define EUSCI_B_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_B busy */ -#define EUSCI_B_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ -#define EUSCI_B_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ -#define EUSCI_B_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ -#define EUSCI_B_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ -#define EUSCI_B_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ -#define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ -#define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /*!< UCTBCNT Bit Offset */ -#define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /*!< UCTBCNT Bit Mask */ -#define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ -#define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ -#define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ -#define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ -#define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /*!< I2COA0 Bit Offset */ -#define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /*!< I2COA0 Bit Mask */ -#define EUSCI_B_I2COA0_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -#define EUSCI_B_I2COA0_GCEN_OFS (15) /*!< UCGCEN Bit Offset */ -#define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /*!< General call response enable */ -#define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /*!< I2COA1 Bit Offset */ -#define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /*!< I2COA1 Bit Mask */ -#define EUSCI_B_I2COA1_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -#define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /*!< I2COA2 Bit Offset */ -#define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /*!< I2COA2 Bit Mask */ -#define EUSCI_B_I2COA2_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -#define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /*!< I2COA3 Bit Offset */ -#define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /*!< I2COA3 Bit Mask */ -#define EUSCI_B_I2COA3_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ -#define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ -#define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /*!< ADDRX Bit Offset */ -#define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /*!< ADDRX Bit Mask */ -#define EUSCI_B_ADDRX_ADDRX0 ((uint16_t)0x0001) /*!< ADDRX Bit 0 */ -#define EUSCI_B_ADDRX_ADDRX1 ((uint16_t)0x0002) /*!< ADDRX Bit 1 */ -#define EUSCI_B_ADDRX_ADDRX2 ((uint16_t)0x0004) /*!< ADDRX Bit 2 */ -#define EUSCI_B_ADDRX_ADDRX3 ((uint16_t)0x0008) /*!< ADDRX Bit 3 */ -#define EUSCI_B_ADDRX_ADDRX4 ((uint16_t)0x0010) /*!< ADDRX Bit 4 */ -#define EUSCI_B_ADDRX_ADDRX5 ((uint16_t)0x0020) /*!< ADDRX Bit 5 */ -#define EUSCI_B_ADDRX_ADDRX6 ((uint16_t)0x0040) /*!< ADDRX Bit 6 */ -#define EUSCI_B_ADDRX_ADDRX7 ((uint16_t)0x0080) /*!< ADDRX Bit 7 */ -#define EUSCI_B_ADDRX_ADDRX8 ((uint16_t)0x0100) /*!< ADDRX Bit 8 */ -#define EUSCI_B_ADDRX_ADDRX9 ((uint16_t)0x0200) /*!< ADDRX Bit 9 */ -#define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /*!< ADDMASK Bit Offset */ -#define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /*!< ADDMASK Bit Mask */ -#define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /*!< I2CSA Bit Offset */ -#define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /*!< I2CSA Bit Mask */ -#define EUSCI_B_IE_RXIE0_OFS ( 0) /*!< UCRXIE0 Bit Offset */ -#define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /*!< Receive interrupt enable 0 */ -#define EUSCI_B_IE_TXIE0_OFS ( 1) /*!< UCTXIE0 Bit Offset */ -#define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /*!< Transmit interrupt enable 0 */ -#define EUSCI_B_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ -#define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /*!< START condition interrupt enable */ -#define EUSCI_B_IE_STPIE_OFS ( 3) /*!< UCSTPIE Bit Offset */ -#define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /*!< STOP condition interrupt enable */ -#define EUSCI_B_IE_ALIE_OFS ( 4) /*!< UCALIE Bit Offset */ -#define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /*!< Arbitration lost interrupt enable */ -#define EUSCI_B_IE_NACKIE_OFS ( 5) /*!< UCNACKIE Bit Offset */ -#define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /*!< Not-acknowledge interrupt enable */ -#define EUSCI_B_IE_BCNTIE_OFS ( 6) /*!< UCBCNTIE Bit Offset */ -#define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /*!< Byte counter interrupt enable */ -#define EUSCI_B_IE_CLTOIE_OFS ( 7) /*!< UCCLTOIE Bit Offset */ -#define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /*!< Clock low timeout interrupt enable */ -#define EUSCI_B_IE_RXIE1_OFS ( 8) /*!< UCRXIE1 Bit Offset */ -#define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /*!< Receive interrupt enable 1 */ -#define EUSCI_B_IE_TXIE1_OFS ( 9) /*!< UCTXIE1 Bit Offset */ -#define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /*!< Transmit interrupt enable 1 */ -#define EUSCI_B_IE_RXIE2_OFS (10) /*!< UCRXIE2 Bit Offset */ -#define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /*!< Receive interrupt enable 2 */ -#define EUSCI_B_IE_TXIE2_OFS (11) /*!< UCTXIE2 Bit Offset */ -#define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /*!< Transmit interrupt enable 2 */ -#define EUSCI_B_IE_RXIE3_OFS (12) /*!< UCRXIE3 Bit Offset */ -#define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /*!< Receive interrupt enable 3 */ -#define EUSCI_B_IE_TXIE3_OFS (13) /*!< UCTXIE3 Bit Offset */ -#define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /*!< Transmit interrupt enable 3 */ -#define EUSCI_B_IE_BIT9IE_OFS (14) /*!< UCBIT9IE Bit Offset */ -#define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /*!< Bit position 9 interrupt enable */ -#define EUSCI_B_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ -#define EUSCI_B_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ -#define EUSCI_B_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ -#define EUSCI_B_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ -#define EUSCI_B_IFG_RXIFG0_OFS ( 0) /*!< UCRXIFG0 Bit Offset */ -#define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /*!< eUSCI_B receive interrupt flag 0 */ -#define EUSCI_B_IFG_TXIFG0_OFS ( 1) /*!< UCTXIFG0 Bit Offset */ -#define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /*!< eUSCI_B transmit interrupt flag 0 */ -#define EUSCI_B_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ -#define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /*!< START condition interrupt flag */ -#define EUSCI_B_IFG_STPIFG_OFS ( 3) /*!< UCSTPIFG Bit Offset */ -#define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /*!< STOP condition interrupt flag */ -#define EUSCI_B_IFG_ALIFG_OFS ( 4) /*!< UCALIFG Bit Offset */ -#define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /*!< Arbitration lost interrupt flag */ -#define EUSCI_B_IFG_NACKIFG_OFS ( 5) /*!< UCNACKIFG Bit Offset */ -#define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /*!< Not-acknowledge received interrupt flag */ -#define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /*!< UCBCNTIFG Bit Offset */ -#define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /*!< Byte counter interrupt flag */ -#define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /*!< UCCLTOIFG Bit Offset */ -#define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /*!< Clock low timeout interrupt flag */ -#define EUSCI_B_IFG_RXIFG1_OFS ( 8) /*!< UCRXIFG1 Bit Offset */ -#define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /*!< eUSCI_B receive interrupt flag 1 */ -#define EUSCI_B_IFG_TXIFG1_OFS ( 9) /*!< UCTXIFG1 Bit Offset */ -#define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /*!< eUSCI_B transmit interrupt flag 1 */ -#define EUSCI_B_IFG_RXIFG2_OFS (10) /*!< UCRXIFG2 Bit Offset */ -#define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /*!< eUSCI_B receive interrupt flag 2 */ -#define EUSCI_B_IFG_TXIFG2_OFS (11) /*!< UCTXIFG2 Bit Offset */ -#define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /*!< eUSCI_B transmit interrupt flag 2 */ -#define EUSCI_B_IFG_RXIFG3_OFS (12) /*!< UCRXIFG3 Bit Offset */ -#define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /*!< eUSCI_B receive interrupt flag 3 */ -#define EUSCI_B_IFG_TXIFG3_OFS (13) /*!< UCTXIFG3 Bit Offset */ -#define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /*!< eUSCI_B transmit interrupt flag 3 */ -#define EUSCI_B_IFG_BIT9IFG_OFS (14) /*!< UCBIT9IFG Bit Offset */ -#define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /*!< Bit position 9 interrupt flag */ -#define EUSCI_B_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ -#define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ -#define EUSCI_B_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ -#define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ -#define EUSCI_B__RXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ -#define EUSCI_B__RXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ -#define EUSCI_B__TXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ -#define EUSCI_B__TXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ -#define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /*!< PSTAT Bit Offset */ -#define FLCTL_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /*!< PSTAT Bit Mask */ -#define FLCTL_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /*!< PSTAT Bit 0 */ -#define FLCTL_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /*!< PSTAT Bit 1 */ -#define FLCTL_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /*!< PSTAT Bit 2 */ -#define FLCTL_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /*!< Flash IP in power-down mode */ -#define FLCTL_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /*!< Flash IP Vdd domain power-up in progress */ -#define FLCTL_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */ -#define FLCTL_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /*!< Flash IP SAFE_LV check in progress */ -#define FLCTL_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /*!< Flash IP Active */ -#define FLCTL_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */ -#define FLCTL_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /*!< Flash IP in Standby mode */ -#define FLCTL_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /*!< Flash IP in Current mirror boost state */ -#define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /*!< LDOSTAT Bit Offset */ -#define FLCTL_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /*!< PSS FLDO GOOD status */ -#define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /*!< VREFSTAT Bit Offset */ -#define FLCTL_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /*!< PSS VREF stable status */ -#define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /*!< IREFSTAT Bit Offset */ -#define FLCTL_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /*!< PSS IREF stable status */ -#define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /*!< TRIMSTAT Bit Offset */ -#define FLCTL_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /*!< PSS trim done status */ -#define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /*!< RD_2T Bit Offset */ -#define FLCTL_POWER_STAT_RD_2T ((uint32_t)0x00000080) /*!< Indicates if Flash is being accessed in 2T mode */ -#define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -#define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -#define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -#define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -#define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -#define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -#define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -#define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -#define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of burst/compare operation */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /*!< MEM_TYPE Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /*!< MEM_TYPE Bit Mask */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /*!< MEM_TYPE Bit 0 */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /*!< MEM_TYPE Bit 1 */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /*!< STOP_FAIL Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /*!< Terminate burst/compare operation */ -#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /*!< DATA_CMP Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /*!< Data pattern used for comparison against memory read data */ -#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /*!< TEST_EN Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /*!< Enable comparison against test data compare registers */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /*!< BRST_STAT Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /*!< BRST_STAT Bit Mask */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /*!< BRST_STAT Bit 0 */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /*!< BRST_STAT Bit 1 */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /*!< Idle */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /*!< Burst/Compare START bit written, but operation pending */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /*!< Burst/Compare in progress */ -#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /*!< Burst complete (status of completed burst remains in this state unless */ -#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /*!< CMP_ERR Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /*!< Burst/Compare Operation encountered atleast one data */ -#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /*!< Burst/Compare Operation was terminated due to access to */ -#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 19-16 of this register */ -#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< START_ADDRESS Bit Mask */ -#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /*!< BURST_LENGTH Bit Offset */ -#define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /*!< BURST_LENGTH Bit Mask */ -#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /*!< FAIL_ADDRESS Bit Offset */ -#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< FAIL_ADDRESS Bit Mask */ -#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /*!< FAIL_COUNT Bit Offset */ -#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /*!< FAIL_COUNT Bit Mask */ -#define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /*!< ENABLE Bit Offset */ -#define FLCTL_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /*!< Master control for all word program operations */ -#define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Write mode */ -#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /*!< VER_PRE Bit Offset */ -#define FLCTL_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /*!< Controls automatic pre program verify operations */ -#define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /*!< VER_PST Bit Offset */ -#define FLCTL_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /*!< Controls automatic post program verify operations */ -#define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Single word program operation triggered, but pending */ -#define FLCTL_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Single word program in progress */ -#define FLCTL_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Reserved (Idle) */ -#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /*!< BNK_ACT Bit Offset */ -#define FLCTL_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /*!< Bank active */ -#define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Trigger start of burst program operation */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /*!< TYPE Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /*!< TYPE Bit Mask */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /*!< TYPE Bit 0 */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /*!< TYPE Bit 1 */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /*!< LEN Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /*!< LEN Bit Mask */ -#define FLCTL_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /*!< LEN Bit 0 */ -#define FLCTL_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /*!< LEN Bit 1 */ -#define FLCTL_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /*!< LEN Bit 2 */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /*!< No burst operation */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /*!< 1 word burst of 128 bits, starting with address in the */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ -#define FLCTL_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /*!< AUTO_PRE Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /*!< Auto-Verify operation before the Burst Program */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /*!< AUTO_PST Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /*!< Auto-Verify operation after the Burst Program */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /*!< BURST_STATUS Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /*!< BURST_STATUS Bit Mask */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /*!< BURST_STATUS Bit 0 */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /*!< BURST_STATUS Bit 1 */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /*!< BURST_STATUS Bit 2 */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (Burst not active) */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /*!< Burst program started but pending */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /*!< Burst active, with 1st 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /*!< Burst active, with 2nd 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /*!< Burst active, with 3rd 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /*!< Burst active, with 4th 128 bit word being written into Flash */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /*!< Reserved (Idle) */ -#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /*!< Burst Complete (status of completed burst remains in this state unless */ -#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /*!< PRE_ERR Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /*!< Burst Operation encountered preprogram auto-verify errors */ -#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /*!< PST_ERR Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /*!< Burst Operation encountered postprogram auto-verify errors */ -#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /*!< Burst Operation was terminated due to attempted program of reserved memory */ -#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 21-16 of this register */ -#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< START_ADDRESS Bit Mask */ -#define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of Erase operation */ -#define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Erase mode selected by application */ -#define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /*!< TYPE Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /*!< TYPE Bit Mask */ -#define FLCTL_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /*!< TYPE Bit 0 */ -#define FLCTL_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /*!< TYPE Bit 1 */ -#define FLCTL_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /*!< Information Memory */ -#define FLCTL_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /*!< Reserved */ -#define FLCTL_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /*!< Engineering Memory */ -#define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Erase operation triggered to START but pending */ -#define FLCTL_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Erase operation in progress */ -#define FLCTL_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Erase operation completed (status of completed erase remains in this state */ -#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /*!< Erase Operation was terminated due to attempted erase of reserved memory */ -#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /*!< CLR_STAT Bit Offset */ -#define FLCTL_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /*!< Clear status bits 18-16 of this register */ -#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /*!< SECT_ADDRESS Bit Offset */ -#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< SECT_ADDRESS Bit Mask */ -#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase operations */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase operations */ -#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /*!< I_BMRK Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001) -#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /*!< D_BMRK Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002) -#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /*!< CMP_EN Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004) -#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /*!< CMP_SEL Bit Offset */ -#define FLCTL_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008) -#define FLCTL_IFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_IFG_RDBRST ((uint32_t)0x00000001) -#define FLCTL_IFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_IFG_AVPRE ((uint32_t)0x00000002) -#define FLCTL_IFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_IFG_AVPST ((uint32_t)0x00000004) -#define FLCTL_IFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_IFG_PRG ((uint32_t)0x00000008) -#define FLCTL_IFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_IFG_PRGB ((uint32_t)0x00000010) -#define FLCTL_IFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_IFG_ERASE ((uint32_t)0x00000020) -#define FLCTL_IFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_IFG_BMRK ((uint32_t)0x00000100) -#define FLCTL_IFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_IFG_PRG_ERR ((uint32_t)0x00000200) -#define FLCTL_IE_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_IE_RDBRST ((uint32_t)0x00000001) -#define FLCTL_IE_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_IE_AVPRE ((uint32_t)0x00000002) -#define FLCTL_IE_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_IE_AVPST ((uint32_t)0x00000004) -#define FLCTL_IE_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_IE_PRG ((uint32_t)0x00000008) -#define FLCTL_IE_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_IE_PRGB ((uint32_t)0x00000010) -#define FLCTL_IE_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_IE_ERASE ((uint32_t)0x00000020) -#define FLCTL_IE_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_IE_BMRK ((uint32_t)0x00000100) -#define FLCTL_IE_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_IE_PRG_ERR ((uint32_t)0x00000200) -#define FLCTL_CLRIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_CLRIFG_RDBRST ((uint32_t)0x00000001) -#define FLCTL_CLRIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_CLRIFG_AVPRE ((uint32_t)0x00000002) -#define FLCTL_CLRIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_CLRIFG_AVPST ((uint32_t)0x00000004) -#define FLCTL_CLRIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_CLRIFG_PRG ((uint32_t)0x00000008) -#define FLCTL_CLRIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_CLRIFG_PRGB ((uint32_t)0x00000010) -#define FLCTL_CLRIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_CLRIFG_ERASE ((uint32_t)0x00000020) -#define FLCTL_CLRIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_CLRIFG_BMRK ((uint32_t)0x00000100) -#define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_CLRIFG_PRG_ERR ((uint32_t)0x00000200) -#define FLCTL_SETIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_SETIFG_RDBRST ((uint32_t)0x00000001) -#define FLCTL_SETIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_SETIFG_AVPRE ((uint32_t)0x00000002) -#define FLCTL_SETIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_SETIFG_AVPST ((uint32_t)0x00000004) -#define FLCTL_SETIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_SETIFG_PRG ((uint32_t)0x00000008) -#define FLCTL_SETIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_SETIFG_PRGB ((uint32_t)0x00000010) -#define FLCTL_SETIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_SETIFG_ERASE ((uint32_t)0x00000020) -#define FLCTL_SETIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_SETIFG_BMRK ((uint32_t)0x00000100) -#define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_SETIFG_PRG_ERR ((uint32_t)0x00000200) -#define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /*!< IREF_BOOST1 Bit Offset */ -#define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /*!< IREF_BOOST1 Bit Mask */ -#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /*!< SETUP_LONG Bit Offset */ -#define FLCTL_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /*!< SETUP_LONG Bit Mask */ -#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /*!< ACTIVE Bit Mask */ -#define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /*!< HOLD Bit Offset */ -#define FLCTL_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /*!< HOLD Bit Mask */ -#define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -#define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -#define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /*!< BOOST_ACTIVE Bit Offset */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /*!< BOOST_ACTIVE Bit Mask */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /*!< BOOST_HOLD Bit Offset */ -#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /*!< BOOST_HOLD Bit Mask */ -#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -#define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /*!< 32B */ -#define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /*!< 64B */ -#define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /*!< 128B */ -#define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /*!< 256B */ -#define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /*!< 512B */ -#define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /*!< 1KB */ -#define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /*!< 2KB */ -#define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /*!< 4KB */ -#define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /*!< 8KB */ -#define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /*!< 16KB */ -#define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /*!< 32KB */ -#define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /*!< 64KB */ -#define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /*!< 128KB */ -#define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /*!< 256KB */ -#define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /*!< 512KB */ -#define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /*!< 1MB */ -#define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /*!< 2MB */ -#define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /*!< 4MB */ -#define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /*!< 8MB */ -#define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /*!< 16MB */ -#define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /*!< 32MB */ -#define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /*!< 64MB */ -#define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /*!< 128MB */ -#define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /*!< 256MB */ -#define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /*!< 512MB */ -#define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /*!< 1GB */ -#define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /*!< 2GB */ -#define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /*!< 4GB */ -#define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /*!< Privileged permissions: No access. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /*!< Privileged permissions: Read-write. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /*!< Privileged permissions: Read-write. User permissions: Read-only. */ -#define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /*!< Privileged permissions: Read-write. User permissions: Read-write. */ -#define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /*!< Privileged permissions: Read-only. User permissions: No access. */ -#define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /*!< Privileged permissions: Read-only. User permissions: Read-only. */ -#define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /*!< Instruction access enabled */ -#define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /*!< Instruction access disabled */ -#define NVIC_IPR0_PRI_0_OFS ( 0) /*!< PRI_0 Offset */ -#define NVIC_IPR0_PRI_0_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR0_PRI_1_OFS ( 8) /*!< PRI_1 Offset */ -#define NVIC_IPR0_PRI_1_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR0_PRI_2_OFS (16) /*!< PRI_2 Offset */ -#define NVIC_IPR0_PRI_2_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR0_PRI_3_OFS (24) /*!< PRI_3 Offset */ -#define NVIC_IPR0_PRI_3_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define NVIC_IPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define NVIC_IPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define NVIC_IPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define NVIC_IPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define NVIC_IPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define NVIC_IPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define NVIC_IPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define NVIC_IPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define NVIC_IPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define NVIC_IPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define NVIC_IPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define NVIC_IPR3_PRI_15_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR4_PRI_16_OFS ( 0) /*!< PRI_16 Offset */ -#define NVIC_IPR4_PRI_16_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR4_PRI_17_OFS ( 8) /*!< PRI_17 Offset */ -#define NVIC_IPR4_PRI_17_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR4_PRI_18_OFS (16) /*!< PRI_18 Offset */ -#define NVIC_IPR4_PRI_18_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR4_PRI_19_OFS (24) /*!< PRI_19 Offset */ -#define NVIC_IPR4_PRI_19_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR5_PRI_20_OFS ( 0) /*!< PRI_20 Offset */ -#define NVIC_IPR5_PRI_20_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR5_PRI_21_OFS ( 8) /*!< PRI_21 Offset */ -#define NVIC_IPR5_PRI_21_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR5_PRI_22_OFS (16) /*!< PRI_22 Offset */ -#define NVIC_IPR5_PRI_22_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR5_PRI_23_OFS (24) /*!< PRI_23 Offset */ -#define NVIC_IPR5_PRI_23_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR6_PRI_24_OFS ( 0) /*!< PRI_24 Offset */ -#define NVIC_IPR6_PRI_24_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR6_PRI_25_OFS ( 8) /*!< PRI_25 Offset */ -#define NVIC_IPR6_PRI_25_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR6_PRI_26_OFS (16) /*!< PRI_26 Offset */ -#define NVIC_IPR6_PRI_26_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR6_PRI_27_OFS (24) /*!< PRI_27 Offset */ -#define NVIC_IPR6_PRI_27_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR7_PRI_28_OFS ( 0) /*!< PRI_28 Offset */ -#define NVIC_IPR7_PRI_28_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR7_PRI_29_OFS ( 8) /*!< PRI_29 Offset */ -#define NVIC_IPR7_PRI_29_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR7_PRI_30_OFS (16) /*!< PRI_30 Offset */ -#define NVIC_IPR7_PRI_30_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR7_PRI_31_OFS (24) /*!< PRI_31 Offset */ -#define NVIC_IPR7_PRI_31_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR8_PRI_32_OFS ( 0) /*!< PRI_32 Offset */ -#define NVIC_IPR8_PRI_32_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR8_PRI_33_OFS ( 8) /*!< PRI_33 Offset */ -#define NVIC_IPR8_PRI_33_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR8_PRI_34_OFS (16) /*!< PRI_34 Offset */ -#define NVIC_IPR8_PRI_34_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR8_PRI_35_OFS (24) /*!< PRI_35 Offset */ -#define NVIC_IPR8_PRI_35_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR9_PRI_36_OFS ( 0) /*!< PRI_36 Offset */ -#define NVIC_IPR9_PRI_36_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR9_PRI_37_OFS ( 8) /*!< PRI_37 Offset */ -#define NVIC_IPR9_PRI_37_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR9_PRI_38_OFS (16) /*!< PRI_38 Offset */ -#define NVIC_IPR9_PRI_38_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR9_PRI_39_OFS (24) /*!< PRI_39 Offset */ -#define NVIC_IPR9_PRI_39_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR10_PRI_40_OFS ( 0) /*!< PRI_40 Offset */ -#define NVIC_IPR10_PRI_40_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR10_PRI_41_OFS ( 8) /*!< PRI_41 Offset */ -#define NVIC_IPR10_PRI_41_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR10_PRI_42_OFS (16) /*!< PRI_42 Offset */ -#define NVIC_IPR10_PRI_42_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR10_PRI_43_OFS (24) /*!< PRI_43 Offset */ -#define NVIC_IPR10_PRI_43_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR11_PRI_44_OFS ( 0) /*!< PRI_44 Offset */ -#define NVIC_IPR11_PRI_44_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR11_PRI_45_OFS ( 8) /*!< PRI_45 Offset */ -#define NVIC_IPR11_PRI_45_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR11_PRI_46_OFS (16) /*!< PRI_46 Offset */ -#define NVIC_IPR11_PRI_46_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR11_PRI_47_OFS (24) /*!< PRI_47 Offset */ -#define NVIC_IPR11_PRI_47_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR12_PRI_48_OFS ( 0) /*!< PRI_48 Offset */ -#define NVIC_IPR12_PRI_48_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR12_PRI_49_OFS ( 8) /*!< PRI_49 Offset */ -#define NVIC_IPR12_PRI_49_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR12_PRI_50_OFS (16) /*!< PRI_50 Offset */ -#define NVIC_IPR12_PRI_50_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR12_PRI_51_OFS (24) /*!< PRI_51 Offset */ -#define NVIC_IPR12_PRI_51_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR13_PRI_52_OFS ( 0) /*!< PRI_52 Offset */ -#define NVIC_IPR13_PRI_52_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR13_PRI_53_OFS ( 8) /*!< PRI_53 Offset */ -#define NVIC_IPR13_PRI_53_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR13_PRI_54_OFS (16) /*!< PRI_54 Offset */ -#define NVIC_IPR13_PRI_54_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR13_PRI_55_OFS (24) /*!< PRI_55 Offset */ -#define NVIC_IPR13_PRI_55_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR14_PRI_56_OFS ( 0) /*!< PRI_56 Offset */ -#define NVIC_IPR14_PRI_56_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR14_PRI_57_OFS ( 8) /*!< PRI_57 Offset */ -#define NVIC_IPR14_PRI_57_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR14_PRI_58_OFS (16) /*!< PRI_58 Offset */ -#define NVIC_IPR14_PRI_58_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR14_PRI_59_OFS (24) /*!< PRI_59 Offset */ -#define NVIC_IPR14_PRI_59_M ((uint32_t)0xff000000) /* */ -#define NVIC_IPR15_PRI_60_OFS ( 0) /*!< PRI_60 Offset */ -#define NVIC_IPR15_PRI_60_M ((uint32_t)0x000000ff) /* */ -#define NVIC_IPR15_PRI_61_OFS ( 8) /*!< PRI_61 Offset */ -#define NVIC_IPR15_PRI_61_M ((uint32_t)0x0000ff00) /* */ -#define NVIC_IPR15_PRI_62_OFS (16) /*!< PRI_62 Offset */ -#define NVIC_IPR15_PRI_62_M ((uint32_t)0x00ff0000) /* */ -#define NVIC_IPR15_PRI_63_OFS (24) /*!< PRI_63 Offset */ -#define NVIC_IPR15_PRI_63_M ((uint32_t)0xff000000) /* */ -#define PCM_CTL0_AMR_OFS ( 0) /*!< AMR Bit Offset */ -#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /*!< AMR Bit Mask */ -#define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /*!< AMR Bit 0 */ -#define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /*!< AMR Bit 1 */ -#define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /*!< AMR Bit 2 */ -#define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /*!< AMR Bit 3 */ -#define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_LPMR_OFS ( 4) /*!< LPMR Bit Offset */ -#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /*!< LPMR Bit Mask */ -#define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /*!< LPMR Bit 0 */ -#define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /*!< LPMR Bit 1 */ -#define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /*!< LPMR Bit 2 */ -#define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /*!< LPMR Bit 3 */ -#define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ -#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -#define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ -#define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ -#define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /*!< LPM4.5 */ -#define PCM_CTL0_CPM_OFS ( 8) /*!< CPM Bit Offset */ -#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /*!< CPM Bit Mask */ -#define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /*!< CPM Bit 0 */ -#define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /*!< CPM Bit 1 */ -#define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /*!< CPM Bit 2 */ -#define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /*!< CPM Bit 3 */ -#define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /*!< CPM Bit 4 */ -#define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /*!< CPM Bit 5 */ -#define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /*!< LPM3 */ -#define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ -#define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ -#define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ -#define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /*!< LPM3 */ -#define PCM_CTL0_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -#define PCM_CTL1_LOCKLPM5_OFS ( 0) /*!< LOCKLPM5 Bit Offset */ -#define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /*!< Lock LPM5 */ -#define PCM_CTL1_LOCKBKUP_OFS ( 1) /*!< LOCKBKUP Bit Offset */ -#define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /*!< Lock Backup */ -#define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /*!< FORCE_LPM_ENTRY Bit Offset */ -#define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /*!< Force LPM entry */ -#define PCM_CTL1_PMR_BUSY_OFS ( 8) /*!< PMR_BUSY Bit Offset */ -#define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /*!< Power mode request busy flag */ -#define PCM_CTL1_KEY_OFS (16) /*!< PCMKEY Bit Offset */ -#define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ -#define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /*!< LPM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /*!< LPM invalid transition interrupt enable */ -#define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /*!< LPM_INVALID_CLK_IE Bit Offset */ -#define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /*!< LPM invalid clock interrupt enable */ -#define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /*!< AM_INVALID_TR_IE Bit Offset */ -#define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /*!< Active mode invalid transition interrupt enable */ -#define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /*!< DCDC_ERROR_IE Bit Offset */ -#define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /*!< DC-DC error interrupt enable */ -#define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /*!< LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< LPM invalid transition flag */ -#define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< LPM invalid clock flag */ -#define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /*!< AM_INVALID_TR_IFG Bit Offset */ -#define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Active mode invalid transition flag */ -#define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /*!< DCDC_ERROR_IFG Bit Offset */ -#define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< DC-DC error flag */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< Clear LPM invalid transition flag */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< Clear LPM invalid clock flag */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /*!< CLR_AM_INVALID_TR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Clear active mode invalid transition flag */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /*!< CLR_DCDC_ERROR_IFG Bit Offset */ -#define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< Clear DC-DC error flag */ -#define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ -#define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ -#define PMAP_CTL_LOCKED_OFS ( 0) /*!< PMAPLOCKED Bit Offset */ -#define PMAP_CTL_LOCKED ((uint16_t)0x0001) /*!< Port mapping lock bit */ -#define PMAP_CTL_PRECFG_OFS ( 1) /*!< PMAPRECFG Bit Offset */ -#define PMAP_CTL_PRECFG ((uint16_t)0x0002) /*!< Port mapping reconfiguration control bit */ -#define PMAP_NONE 0 -#define PMAP_UCA0CLK 1 -#define PMAP_UCA0RXD 2 -#define PMAP_UCA0SOMI 2 -#define PMAP_UCA0TXD 3 -#define PMAP_UCA0SIMO 3 -#define PMAP_UCB0CLK 4 -#define PMAP_UCB0SDA 5 -#define PMAP_UCB0SIMO 5 -#define PMAP_UCB0SCL 6 -#define PMAP_UCB0SOMI 6 -#define PMAP_UCA1STE 7 -#define PMAP_UCA1CLK 8 -#define PMAP_UCA1RXD 9 -#define PMAP_UCA1SOMI 9 -#define PMAP_UCA1TXD 10 -#define PMAP_UCA1SIMO 10 -#define PMAP_UCA2STE 11 -#define PMAP_UCA2CLK 12 -#define PMAP_UCA2RXD 13 -#define PMAP_UCA2SOMI 13 -#define PMAP_UCA2TXD 14 -#define PMAP_UCA2SIMO 14 -#define PMAP_UCB2STE 15 -#define PMAP_UCB2CLK 16 -#define PMAP_UCB2SDA 17 -#define PMAP_UCB2SIMO 17 -#define PMAP_UCB2SCL 18 -#define PMAP_UCB2SOMI 18 -#define PMAP_TA0CCR0A 19 -#define PMAP_TA0CCR1A 20 -#define PMAP_TA0CCR2A 21 -#define PMAP_TA0CCR3A 22 -#define PMAP_TA0CCR4A 23 -#define PMAP_TA1CCR1A 24 -#define PMAP_TA1CCR2A 25 -#define PMAP_TA1CCR3A 26 -#define PMAP_TA1CCR4A 27 -#define PMAP_TA0CLK 28 -#define PMAP_CE0OUT 28 -#define PMAP_TA1CLK 29 -#define PMAP_CE1OUT 29 -#define PMAP_DMAE0 30 -#define PMAP_SMCLK 30 -#define PMAP_ANALOG 31 -#define PMAP_KEYID_VAL ((uint16_t)0x2D52) /*!< Port Mapping Key */ -#define PSS_KEY_KEY_OFS ( 0) /*!< PSSKEY Bit Offset */ -#define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< PSSKEY Bit Mask */ -#define PSS_CTL0_SVSMHOFF_OFS ( 0) /*!< SVSMHOFF Bit Offset */ -#define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /*!< SVSM high-side off */ -#define PSS_CTL0_SVSMHLP_OFS ( 1) /*!< SVSMHLP Bit Offset */ -#define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /*!< SVSM high-side low power normal performance mode */ -#define PSS_CTL0_SVSMHS_OFS ( 2) /*!< SVSMHS Bit Offset */ -#define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /*!< Supply supervisor or monitor selection for the high-side */ -#define PSS_CTL0_SVSMHTH_OFS ( 3) /*!< SVSMHTH Bit Offset */ -#define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /*!< SVSMHTH Bit Mask */ -#define PSS_CTL0_SVMHOE_OFS ( 6) /*!< SVMHOE Bit Offset */ -#define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /*!< SVSM high-side output enable */ -#define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /*!< SVMHOUTPOLAL Bit Offset */ -#define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /*!< SVMHOUT pin polarity active low */ -#define PSS_CTL0_DCDC_FORCE_OFS (10) /*!< DCDC_FORCE Bit Offset */ -#define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /*!< Force DC-DC regulator operation */ -#define PSS_CTL0_VCORETRAN_OFS (12) /*!< VCORETRAN Bit Offset */ -#define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /*!< VCORETRAN Bit Mask */ -#define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /*!< VCORETRAN Bit 0 */ -#define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /*!< VCORETRAN Bit 1 */ -#define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ -#define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ -#define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ -#define PSS_IE_SVSMHIE_OFS ( 1) /*!< SVSMHIE Bit Offset */ -#define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /*!< High-side SVSM interrupt enable */ -#define PSS_IFG_SVSMHIFG_OFS ( 1) /*!< SVSMHIFG Bit Offset */ -#define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /*!< High-side SVSM interrupt flag */ -#define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /*!< CLRSVSMHIFG Bit Offset */ -#define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /*!< SVSMH clear interrupt flag */ -#define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /*!< PSS control key value */ -#define REF_A_CTL0_ON_OFS ( 0) /*!< REFON Bit Offset */ -#define REF_A_CTL0_ON ((uint16_t)0x0001) /*!< Reference enable */ -#define REF_A_CTL0_OUT_OFS ( 1) /*!< REFOUT Bit Offset */ -#define REF_A_CTL0_OUT ((uint16_t)0x0002) /*!< Reference output buffer */ -#define REF_A_CTL0_TCOFF_OFS ( 3) /*!< REFTCOFF Bit Offset */ -#define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /*!< Temperature sensor disabled */ -#define REF_A_CTL0_VSEL_OFS ( 4) /*!< REFVSEL Bit Offset */ -#define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /*!< REFVSEL Bit Mask */ -#define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /*!< VSEL Bit 0 */ -#define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /*!< VSEL Bit 1 */ -#define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /*!< 1.2 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /*!< 1.45 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /*!< 2.5 V available when reference requested or REFON = 1 */ -#define REF_A_CTL0_GENOT_OFS ( 6) /*!< REFGENOT Bit Offset */ -#define REF_A_CTL0_GENOT ((uint16_t)0x0040) /*!< Reference generator one-time trigger */ -#define REF_A_CTL0_BGOT_OFS ( 7) /*!< REFBGOT Bit Offset */ -#define REF_A_CTL0_BGOT ((uint16_t)0x0080) /*!< Bandgap and bandgap buffer one-time trigger */ -#define REF_A_CTL0_GENACT_OFS ( 8) /*!< REFGENACT Bit Offset */ -#define REF_A_CTL0_GENACT ((uint16_t)0x0100) /*!< Reference generator active */ -#define REF_A_CTL0_BGACT_OFS ( 9) /*!< REFBGACT Bit Offset */ -#define REF_A_CTL0_BGACT ((uint16_t)0x0200) /*!< Reference bandgap active */ -#define REF_A_CTL0_GENBUSY_OFS (10) /*!< REFGENBUSY Bit Offset */ -#define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /*!< Reference generator busy */ -#define REF_A_CTL0_BGMODE_OFS (11) /*!< BGMODE Bit Offset */ -#define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /*!< Bandgap mode */ -#define REF_A_CTL0_GENRDY_OFS (12) /*!< REFGENRDY Bit Offset */ -#define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /*!< Variable reference voltage ready status */ -#define REF_A_CTL0_BGRDY_OFS (13) /*!< REFBGRDY Bit Offset */ -#define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /*!< Buffered bandgap voltage ready status */ -#define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /*!< SOFT_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /*!< Soft Reset request */ -#define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /*!< HARD_REQ Bit Offset */ -#define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /*!< Hard Reset request */ -#define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /*!< RSTKEY Bit Offset */ -#define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /*!< RSTKEY Bit Mask */ -#define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< Indicates that SRC0 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< Indicates that SRC1 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< Indicates that SRC2 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< Indicates that SRC3 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< Indicates that SRC4 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< Indicates that SRC5 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< Indicates that SRC6 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< Indicates that SRC7 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< Indicates that SRC8 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< Indicates that SRC9 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< Indicates that SRC10 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< Indicates that SRC11 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< Indicates that SRC12 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< Indicates that SRC13 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< Indicates that SRC14 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< Indicates that SRC15 was the source of the Hard Reset */ -#define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ -#define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */ -#define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ -#define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< If 1, indicates that SRC0 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< If 1, indicates that SRC1 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< If 1, indicates that SRC2 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< If 1, indicates that SRC3 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< If 1, indicates that SRC4 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< If 1, indicates that SRC5 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< If 1, indicates that SRC6 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< If 1, indicates that SRC7 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< If 1, indicates that SRC8 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< If 1, indicates that SRC9 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< If 1, indicates that SRC10 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< If 1, indicates that SRC11 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< If 1, indicates that SRC12 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< If 1, indicates that SRC13 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< If 1, indicates that SRC14 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< If 1, indicates that SRC15 was the source of the Soft Reset */ -#define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ -#define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ -#define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ -#define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /*!< SVSMH Bit Offset */ -#define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */ -#define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /*!< BGREF Bit Offset */ -#define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */ -#define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /*!< VCCDET Bit Offset */ -#define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */ -#define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */ -#define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /*!< LPM35 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */ -#define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /*!< LPM45 Bit Offset */ -#define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */ -#define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */ -#define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /*!< RSTNMI Bit Offset */ -#define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /*!< POR was caused by RSTn/NMI pin based reset event */ -#define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /*!< Indicates if Reboot reset was caused by the SYSCTL module. */ -#define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /*!< DCOR_SHT Bit Offset */ -#define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /*!< Indicates if POR was caused by DCO short circuit fault in the external */ -#define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ -#define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as */ -#define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bits 1-0 */ -#define RTC_C_CTL0_RDYIFG_OFS ( 0) /*!< RTCRDYIFG Bit Offset */ -#define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /*!< Real-time clock ready interrupt flag */ -#define RTC_C_CTL0_AIFG_OFS ( 1) /*!< RTCAIFG Bit Offset */ -#define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /*!< Real-time clock alarm interrupt flag */ -#define RTC_C_CTL0_TEVIFG_OFS ( 2) /*!< RTCTEVIFG Bit Offset */ -#define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /*!< Real-time clock time event interrupt flag */ -#define RTC_C_CTL0_OFIFG_OFS ( 3) /*!< RTCOFIFG Bit Offset */ -#define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /*!< 32-kHz crystal oscillator fault interrupt flag */ -#define RTC_C_CTL0_RDYIE_OFS ( 4) /*!< RTCRDYIE Bit Offset */ -#define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /*!< Real-time clock ready interrupt enable */ -#define RTC_C_CTL0_AIE_OFS ( 5) /*!< RTCAIE Bit Offset */ -#define RTC_C_CTL0_AIE ((uint16_t)0x0020) /*!< Real-time clock alarm interrupt enable */ -#define RTC_C_CTL0_TEVIE_OFS ( 6) /*!< RTCTEVIE Bit Offset */ -#define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /*!< Real-time clock time event interrupt enable */ -#define RTC_C_CTL0_OFIE_OFS ( 7) /*!< RTCOFIE Bit Offset */ -#define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /*!< 32-kHz crystal oscillator fault interrupt enable */ -#define RTC_C_CTL0_KEY_OFS ( 8) /*!< RTCKEY Bit Offset */ -#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /*!< RTCKEY Bit Mask */ -#define RTC_C_CTL13_TEV_OFS ( 0) /*!< RTCTEV Bit Offset */ -#define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /*!< RTCTEV Bit Mask */ -#define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /*!< TEV Bit 0 */ -#define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /*!< TEV Bit 1 */ -#define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /*!< Minute changed */ -#define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /*!< Hour changed */ -#define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /*!< Every day at midnight (00:00) */ -#define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /*!< Every day at noon (12:00) */ -#define RTC_C_CTL13_SSEL_OFS ( 2) /*!< RTCSSEL Bit Offset */ -#define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /*!< RTCSSEL Bit Mask */ -#define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /*!< SSEL Bit 0 */ -#define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /*!< SSEL Bit 1 */ -#define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /*!< BCLK */ -#define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /*!< BCLK */ -#define RTC_C_CTL13_RDY_OFS ( 4) /*!< RTCRDY Bit Offset */ -#define RTC_C_CTL13_RDY ((uint16_t)0x0010) /*!< Real-time clock ready */ -#define RTC_C_CTL13_MODE_OFS ( 5) /*!< RTCMODE Bit Offset */ -#define RTC_C_CTL13_MODE ((uint16_t)0x0020) -#define RTC_C_CTL13_HOLD_OFS ( 6) /*!< RTCHOLD Bit Offset */ -#define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /*!< Real-time clock hold */ -#define RTC_C_CTL13_BCD_OFS ( 7) /*!< RTCBCD Bit Offset */ -#define RTC_C_CTL13_BCD ((uint16_t)0x0080) /*!< Real-time clock BCD select */ -#define RTC_C_CTL13_CALF_OFS ( 8) /*!< RTCCALF Bit Offset */ -#define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /*!< RTCCALF Bit Mask */ -#define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /*!< CALF Bit 0 */ -#define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /*!< CALF Bit 1 */ -#define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /*!< 1 Hz */ -#define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ -#define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /*!< 512 Hz */ -#define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /*!< 256 Hz */ -#define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /*!< 1 Hz */ -#define RTC_C_OCAL_OCAL_OFS ( 0) /*!< RTCOCAL Bit Offset */ -#define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /*!< RTCOCAL Bit Mask */ -#define RTC_C_OCAL_OCALS_OFS (15) /*!< RTCOCALS Bit Offset */ -#define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /*!< Real-time clock offset error calibration sign */ -#define RTC_C_TCMP_TCMPX_OFS ( 0) /*!< RTCTCMP Bit Offset */ -#define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /*!< RTCTCMP Bit Mask */ -#define RTC_C_TCMP_TCOK_OFS (13) /*!< RTCTCOK Bit Offset */ -#define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /*!< Real-time clock temperature compensation write OK */ -#define RTC_C_TCMP_TCRDY_OFS (14) /*!< RTCTCRDY Bit Offset */ -#define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /*!< Real-time clock temperature compensation ready */ -#define RTC_C_TCMP_TCMPS_OFS (15) /*!< RTCTCMPS Bit Offset */ -#define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /*!< Real-time clock temperature compensation sign */ -#define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /*!< RT0PSIFG Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /*!< Prescale timer 0 interrupt flag */ -#define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /*!< RT0PSIE Bit Offset */ -#define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /*!< Prescale timer 0 interrupt enable */ -#define RTC_C_PS0CTL_RT0IP_OFS ( 2) /*!< RT0IP Bit Offset */ -#define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /*!< RT0IP Bit Mask */ -#define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /*!< RT0IP Bit 0 */ -#define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /*!< RT0IP Bit 1 */ -#define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /*!< RT0IP Bit 2 */ -#define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /*!< RT1PSIFG Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /*!< Prescale timer 1 interrupt flag */ -#define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /*!< RT1PSIE Bit Offset */ -#define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /*!< Prescale timer 1 interrupt enable */ -#define RTC_C_PS1CTL_RT1IP_OFS ( 2) /*!< RT1IP Bit Offset */ -#define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /*!< RT1IP Bit Mask */ -#define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /*!< RT1IP Bit 0 */ -#define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /*!< RT1IP Bit 1 */ -#define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /*!< RT1IP Bit 2 */ -#define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ -#define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ -#define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ -#define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ -#define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ -#define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ -#define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ -#define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ -#define RTC_C_PS_RT0PS_OFS ( 0) /*!< RT0PS Bit Offset */ -#define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /*!< RT0PS Bit Mask */ -#define RTC_C_PS_RT1PS_OFS ( 8) /*!< RT1PS Bit Offset */ -#define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /*!< RT1PS Bit Mask */ -#define RTC_C_TIM0_SEC_OFS ( 0) /*!< Seconds Bit Offset */ -#define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /*!< Seconds Bit Mask */ -#define RTC_C_TIM0_MIN_OFS ( 8) /*!< Minutes Bit Offset */ -#define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /*!< Minutes Bit Mask */ -#define RTC_C_TIM0_SEC_LD_OFS ( 0) /*!< SecondsLowDigit Bit Offset */ -#define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /*!< SecondsLowDigit Bit Mask */ -#define RTC_C_TIM0_SEC_HD_OFS ( 4) /*!< SecondsHighDigit Bit Offset */ -#define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /*!< SecondsHighDigit Bit Mask */ -#define RTC_C_TIM0_MIN_LD_OFS ( 8) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /*!< MinutesLowDigit Bit Mask */ -#define RTC_C_TIM0_MIN_HD_OFS (12) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /*!< MinutesHighDigit Bit Mask */ -#define RTC_C_TIM1_HOUR_OFS ( 0) /*!< Hours Bit Offset */ -#define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /*!< Hours Bit Mask */ -#define RTC_C_TIM1_DOW_OFS ( 8) /*!< DayofWeek Bit Offset */ -#define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /*!< DayofWeek Bit Mask */ -#define RTC_C_TIM1_HOUR_LD_OFS ( 0) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /*!< HoursLowDigit Bit Mask */ -#define RTC_C_TIM1_HOUR_HD_OFS ( 4) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /*!< HoursHighDigit Bit Mask */ -#define RTC_C_DATE_DAY_OFS ( 0) /*!< Day Bit Offset */ -#define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /*!< Day Bit Mask */ -#define RTC_C_DATE_MON_OFS ( 8) /*!< Month Bit Offset */ -#define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /*!< Month Bit Mask */ -#define RTC_C_DATE_DAY_LD_OFS ( 0) /*!< DayLowDigit Bit Offset */ -#define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /*!< DayLowDigit Bit Mask */ -#define RTC_C_DATE_DAY_HD_OFS ( 4) /*!< DayHighDigit Bit Offset */ -#define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /*!< DayHighDigit Bit Mask */ -#define RTC_C_DATE_MON_LD_OFS ( 8) /*!< MonthLowDigit Bit Offset */ -#define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /*!< MonthLowDigit Bit Mask */ -#define RTC_C_DATE_MON_HD_OFS (12) /*!< MonthHighDigit Bit Offset */ -#define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /*!< Month high digit (0 or 1) */ -#define RTC_C_YEAR_YEAR_LB_OFS ( 0) /*!< YearLowByte Bit Offset */ -#define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /*!< YearLowByte Bit Mask */ -#define RTC_C_YEAR_YEAR_HB_OFS ( 8) /*!< YearHighByte Bit Offset */ -#define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /*!< YearHighByte Bit Mask */ -#define RTC_C_YEAR_YEAR_OFS ( 0) /*!< Year Bit Offset */ -#define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /*!< Year Bit Mask */ -#define RTC_C_YEAR_DEC_OFS ( 4) /*!< Decade Bit Offset */ -#define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /*!< Decade Bit Mask */ -#define RTC_C_YEAR_CENT_LD_OFS ( 8) /*!< CenturyLowDigit Bit Offset */ -#define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /*!< CenturyLowDigit Bit Mask */ -#define RTC_C_YEAR_CENT_HD_OFS (12) /*!< CenturyHighDigit Bit Offset */ -#define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /*!< CenturyHighDigit Bit Mask */ -#define RTC_C_AMINHR_MIN_OFS ( 0) /*!< Minutes Bit Offset */ -#define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /*!< Minutes Bit Mask */ -#define RTC_C_AMINHR_MINAE_OFS ( 7) /*!< MINAE Bit Offset */ -#define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /*!< Alarm enable */ -#define RTC_C_AMINHR_HOUR_OFS ( 8) /*!< Hours Bit Offset */ -#define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /*!< Hours Bit Mask */ -#define RTC_C_AMINHR_HOURAE_OFS (15) /*!< HOURAE Bit Offset */ -#define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /*!< Alarm enable */ -#define RTC_C_AMINHR_MIN_LD_OFS ( 0) /*!< MinutesLowDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /*!< MinutesLowDigit Bit Mask */ -#define RTC_C_AMINHR_MIN_HD_OFS ( 4) /*!< MinutesHighDigit Bit Offset */ -#define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /*!< MinutesHighDigit Bit Mask */ -#define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /*!< HoursLowDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /*!< HoursLowDigit Bit Mask */ -#define RTC_C_AMINHR_HOUR_HD_OFS (12) /*!< HoursHighDigit Bit Offset */ -#define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /*!< HoursHighDigit Bit Mask */ -#define RTC_C_ADOWDAY_DOW_OFS ( 0) /*!< DayofWeek Bit Offset */ -#define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /*!< DayofWeek Bit Mask */ -#define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /*!< DOWAE Bit Offset */ -#define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /*!< Alarm enable */ -#define RTC_C_ADOWDAY_DAY_OFS ( 8) /*!< DayofMonth Bit Offset */ -#define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /*!< DayofMonth Bit Mask */ -#define RTC_C_ADOWDAY_DAYAE_OFS (15) /*!< DAYAE Bit Offset */ -#define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /*!< Alarm enable */ -#define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /*!< DayLowDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /*!< DayLowDigit Bit Mask */ -#define RTC_C_ADOWDAY_DAY_HD_OFS (12) /*!< DayHighDigit Bit Offset */ -#define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /*!< DayHighDigit Bit Mask */ -#define RTC_C_KEY ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_H ((uint16_t)0x00A5) /*!< RTC_C Key Value for RTC_C write access */ -#define RTC_C_KEY_VAL ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ -#define SCB_PFR0_STATE0_OFS ( 0) /*!< STATE0 Bit Offset */ -#define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /*!< STATE0 Bit Mask */ -#define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /*!< STATE0 Bit 0 */ -#define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /*!< STATE0 Bit 1 */ -#define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /*!< STATE0 Bit 2 */ -#define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /*!< STATE0 Bit 3 */ -#define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /*!< no ARM encoding */ -#define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /*!< N/A */ -#define SCB_PFR0_STATE1_OFS ( 4) /*!< STATE1 Bit Offset */ -#define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /*!< STATE1 Bit Mask */ -#define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /*!< STATE1 Bit 0 */ -#define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /*!< STATE1 Bit 1 */ -#define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /*!< STATE1 Bit 2 */ -#define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /*!< STATE1 Bit 3 */ -#define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /*!< N/A */ -#define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /*!< N/A */ -#define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL */ -#define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /*!< Thumb-2 encoding with all Thumb-2 basic instructions */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /*!< two-stack support */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */ -#define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /*!< PMSA_SUPPORT Bit Offset */ -#define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /*!< PMSA_SUPPORT Bit Mask */ -#define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /*!< PMSA_SUPPORT Bit 0 */ -#define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /*!< PMSA_SUPPORT Bit 1 */ -#define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /*!< PMSA_SUPPORT Bit 2 */ -#define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /*!< PMSA_SUPPORT Bit 3 */ -#define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /*!< IMPLEMENTATION DEFINED (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /*!< PMSA base (features as defined for ARMv6) (N/A) */ -#define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /*!< PMSAv7 (base plus subregion support) */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /*!< CACHE_COHERENCE_SUPPORT Bit Offset */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /*!< CACHE_COHERENCE_SUPPORT Bit Mask */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /*!< CACHE_COHERENCE_SUPPORT Bit 0 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /*!< CACHE_COHERENCE_SUPPORT Bit 1 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /*!< CACHE_COHERENCE_SUPPORT Bit 2 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /*!< CACHE_COHERENCE_SUPPORT Bit 3 */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /*!< no shared support */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /*!< partial-inner-shared coherency (coherency amongst some - but not all - of */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /*!< full-inner-shared coherency (coherency amongst all of the entities within an */ -#define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /*!< full coherency (coherency amongst all of the entities) */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /*!< Outer non-sharable not supported */ -#define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /*!< Outer sharable supported */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /*!< Auxiliary control register */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /*!< not supported */ -#define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /*!< wait for interrupt supported */ -#define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /*!< BITCOUNT_INSTRS Bit Offset */ -#define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< BITCOUNT_INSTRS Bit Mask */ -#define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /*!< BITCOUNT_INSTRS Bit 0 */ -#define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /*!< BITCOUNT_INSTRS Bit 1 */ -#define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /*!< BITCOUNT_INSTRS Bit 2 */ -#define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /*!< BITCOUNT_INSTRS Bit 3 */ -#define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /*!< no bit-counting instructions present */ -#define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds CLZ */ -#define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /*!< BITFIELD_INSTRS Bit Offset */ -#define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /*!< BITFIELD_INSTRS Bit Mask */ -#define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /*!< BITFIELD_INSTRS Bit 0 */ -#define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /*!< BITFIELD_INSTRS Bit 1 */ -#define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /*!< BITFIELD_INSTRS Bit 2 */ -#define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /*!< BITFIELD_INSTRS Bit 3 */ -#define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /*!< no bitfield instructions present */ -#define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /*!< adds BFC, BFI, SBFX, UBFX */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /*!< CMPBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /*!< CMPBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /*!< CMPBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /*!< CMPBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /*!< CMPBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /*!< CMPBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no combined compare-and-branch instructions present */ -#define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /*!< adds CB{N}Z */ -#define SCB_ISAR0_COPROC_INSTRS_OFS (16) /*!< COPROC_INSTRS Bit Offset */ -#define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /*!< COPROC_INSTRS Bit Mask */ -#define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /*!< COPROC_INSTRS Bit 0 */ -#define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /*!< COPROC_INSTRS Bit 1 */ -#define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /*!< COPROC_INSTRS Bit 2 */ -#define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /*!< COPROC_INSTRS Bit 3 */ -#define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /*!< no coprocessor support, other than for separately attributed architectures */ -#define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /*!< adds generic CDP, LDC, MCR, MRC, STC */ -#define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */ -#define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /*!< adds generic MCRR, MRRC */ -#define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /*!< adds generic MCRR2, MRRC2 */ -#define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /*!< DEBUG_INSTRS Bit Offset */ -#define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /*!< DEBUG_INSTRS Bit Mask */ -#define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /*!< DEBUG_INSTRS Bit 0 */ -#define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /*!< DEBUG_INSTRS Bit 1 */ -#define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /*!< DEBUG_INSTRS Bit 2 */ -#define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /*!< DEBUG_INSTRS Bit 3 */ -#define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /*!< no debug instructions present */ -#define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /*!< adds BKPT */ -#define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /*!< DIVIDE_INSTRS Bit Offset */ -#define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /*!< DIVIDE_INSTRS Bit Mask */ -#define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /*!< DIVIDE_INSTRS Bit 0 */ -#define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /*!< DIVIDE_INSTRS Bit 1 */ -#define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /*!< DIVIDE_INSTRS Bit 2 */ -#define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /*!< DIVIDE_INSTRS Bit 3 */ -#define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /*!< no divide instructions present */ -#define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /*!< adds SDIV, UDIV (v1 quotient only result) */ -#define SCB_ISAR1_ETEND_INSRS_OFS (12) /*!< EXTEND_INSRS Bit Offset */ -#define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /*!< EXTEND_INSRS Bit Mask */ -#define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /*!< ETEND_INSRS Bit 0 */ -#define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /*!< ETEND_INSRS Bit 1 */ -#define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /*!< ETEND_INSRS Bit 2 */ -#define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /*!< ETEND_INSRS Bit 3 */ -#define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */ -#define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /*!< adds SXTB, SXTH, UXTB, UXTH */ -#define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /*!< N/A */ -#define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /*!< IFTHEN_INSTRS Bit Offset */ -#define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /*!< IFTHEN_INSTRS Bit Mask */ -#define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /*!< IFTHEN_INSTRS Bit 0 */ -#define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /*!< IFTHEN_INSTRS Bit 1 */ -#define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /*!< IFTHEN_INSTRS Bit 2 */ -#define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /*!< IFTHEN_INSTRS Bit 3 */ -#define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /*!< IT instructions not present */ -#define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /*!< adds IT instructions (and IT bits in PSRs) */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /*!< IMMEDIATE_INSTRS Bit Offset */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /*!< IMMEDIATE_INSTRS Bit Mask */ -#define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /*!< IMMEDIATE_INSTRS Bit 0 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /*!< IMMEDIATE_INSTRS Bit 1 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /*!< IMMEDIATE_INSTRS Bit 2 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /*!< IMMEDIATE_INSTRS Bit 3 */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no special immediate-generating instructions present */ -#define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /*!< adds ADDW, MOVW, MOVT, SUBW */ -#define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /*!< INTERWORK_INSTRS Bit Offset */ -#define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /*!< INTERWORK_INSTRS Bit Mask */ -#define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /*!< INTERWORK_INSTRS Bit 0 */ -#define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /*!< INTERWORK_INSTRS Bit 1 */ -#define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /*!< INTERWORK_INSTRS Bit 2 */ -#define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /*!< INTERWORK_INSTRS Bit 3 */ -#define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /*!< no interworking instructions supported */ -#define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /*!< adds BX (and T bit in PSRs) */ -#define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /*!< adds BLX, and PC loads have BX-like behavior */ -#define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /*!< N/A */ -#define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /*!< LOADSTORE_INSTRS Bit Offset */ -#define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< LOADSTORE_INSTRS Bit Mask */ -#define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /*!< LOADSTORE_INSTRS Bit 0 */ -#define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /*!< LOADSTORE_INSTRS Bit 1 */ -#define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /*!< LOADSTORE_INSTRS Bit 2 */ -#define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /*!< LOADSTORE_INSTRS Bit 3 */ -#define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /*!< no additional normal load/store instructions present */ -#define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRD/STRD */ -#define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /*!< MEMHINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< MEMHINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /*!< MEMHINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /*!< MEMHINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /*!< MEMHINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /*!< MEMHINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /*!< no memory hint instructions presen */ -#define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds PLD */ -#define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /*!< adds PLD (ie a repeat on value 1) */ -#define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /*!< adds PLI */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /*!< MULTIACCESSINT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /*!< MULTIACCESSINT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /*!< MULTIACCESSINT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /*!< MULTIACCESSINT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /*!< MULTIACCESSINT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /*!< MULTIACCESSINT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /*!< the (LDM/STM) instructions are non-interruptible */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /*!< the (LDM/STM) instructions are restartable */ -#define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /*!< the (LDM/STM) instructions are continuable */ -#define SCB_ISAR2_MULT_INSTRS_OFS (12) /*!< MULT_INSTRS Bit Offset */ -#define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /*!< MULT_INSTRS Bit Mask */ -#define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /*!< MULT_INSTRS Bit 0 */ -#define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /*!< MULT_INSTRS Bit 1 */ -#define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /*!< MULT_INSTRS Bit 2 */ -#define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /*!< MULT_INSTRS Bit 3 */ -#define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /*!< only MUL present */ -#define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /*!< adds MLA */ -#define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /*!< adds MLS */ -#define SCB_ISAR2_MULTS_INSTRS_OFS (16) /*!< MULTS_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /*!< MULTS_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /*!< MULTS_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /*!< MULTS_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /*!< MULTS_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /*!< MULTS_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /*!< no signed multiply instructions present */ -#define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /*!< adds SMULL, SMLAL */ -#define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /*!< N/A */ -#define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /*!< N/A */ -#define SCB_ISAR2_MULTU_INSTRS_OFS (20) /*!< MULTU_INSTRS Bit Offset */ -#define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /*!< MULTU_INSTRS Bit Mask */ -#define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /*!< MULTU_INSTRS Bit 0 */ -#define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /*!< MULTU_INSTRS Bit 1 */ -#define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /*!< MULTU_INSTRS Bit 2 */ -#define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /*!< MULTU_INSTRS Bit 3 */ -#define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /*!< no unsigned multiply instructions present */ -#define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /*!< adds UMULL, UMLAL */ -#define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /*!< N/A */ -#define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /*!< REVERSAL_INSTRS Bit Offset */ -#define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /*!< REVERSAL_INSTRS Bit Mask */ -#define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /*!< REVERSAL_INSTRS Bit 0 */ -#define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /*!< REVERSAL_INSTRS Bit 1 */ -#define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /*!< REVERSAL_INSTRS Bit 2 */ -#define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /*!< REVERSAL_INSTRS Bit 3 */ -#define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /*!< no reversal instructions present */ -#define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /*!< adds REV, REV16, REVSH */ -#define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /*!< adds RBIT */ -#define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /*!< SATRUATE_INSTRS Bit Offset */ -#define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< SATRUATE_INSTRS Bit Mask */ -#define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /*!< SATRUATE_INSTRS Bit 0 */ -#define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /*!< SATRUATE_INSTRS Bit 1 */ -#define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /*!< SATRUATE_INSTRS Bit 2 */ -#define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /*!< SATRUATE_INSTRS Bit 3 */ -#define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no non-SIMD saturate instructions present */ -#define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /*!< N/A */ -#define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /*!< SIMD_INSTRS Bit Offset */ -#define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /*!< SIMD_INSTRS Bit Mask */ -#define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /*!< SIMD_INSTRS Bit 0 */ -#define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /*!< SIMD_INSTRS Bit 1 */ -#define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /*!< SIMD_INSTRS Bit 2 */ -#define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /*!< SIMD_INSTRS Bit 3 */ -#define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /*!< no SIMD instructions present */ -#define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /*!< adds SSAT, USAT (and the Q flag in the PSRs) */ -#define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /*!< N/A */ -#define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /*!< SVC_INSTRS Bit Offset */ -#define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /*!< SVC_INSTRS Bit Mask */ -#define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /*!< SVC_INSTRS Bit 0 */ -#define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /*!< SVC_INSTRS Bit 1 */ -#define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /*!< SVC_INSTRS Bit 2 */ -#define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /*!< SVC_INSTRS Bit 3 */ -#define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /*!< no SVC (SWI) instructions present */ -#define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /*!< adds SVC (SWI) */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /*!< SYNCPRIM_INSTRS Bit Offset */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /*!< SYNCPRIM_INSTRS Bit Mask */ -#define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /*!< SYNCPRIM_INSTRS Bit 0 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /*!< SYNCPRIM_INSTRS Bit 1 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /*!< SYNCPRIM_INSTRS Bit 2 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /*!< SYNCPRIM_INSTRS Bit 3 */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /*!< no synchronization primitives present */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /*!< adds LDREX, STREX */ -#define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */ -#define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /*!< TABBRANCH_INSTRS Bit Offset */ -#define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /*!< TABBRANCH_INSTRS Bit Mask */ -#define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /*!< TABBRANCH_INSTRS Bit 0 */ -#define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /*!< TABBRANCH_INSTRS Bit 1 */ -#define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /*!< TABBRANCH_INSTRS Bit 2 */ -#define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /*!< TABBRANCH_INSTRS Bit 3 */ -#define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no table-branch instructions present */ -#define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /*!< adds TBB, TBH */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /*!< THUMBCOPY_INSTRS Bit Offset */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /*!< THUMBCOPY_INSTRS Bit Mask */ -#define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /*!< THUMBCOPY_INSTRS Bit 0 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /*!< THUMBCOPY_INSTRS Bit 1 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /*!< THUMBCOPY_INSTRS Bit 2 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /*!< THUMBCOPY_INSTRS Bit 3 */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */ -#define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */ -#define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /*!< TRUENOP_INSTRS Bit Offset */ -#define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /*!< TRUENOP_INSTRS Bit Mask */ -#define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /*!< TRUENOP_INSTRS Bit 0 */ -#define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /*!< TRUENOP_INSTRS Bit 1 */ -#define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /*!< TRUENOP_INSTRS Bit 2 */ -#define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /*!< TRUENOP_INSTRS Bit 3 */ -#define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /*!< true NOP instructions not present - that is, NOP instructions with no */ -#define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */ -#define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /*!< UNPRIV_INSTRS Bit Offset */ -#define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /*!< UNPRIV_INSTRS Bit Mask */ -#define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /*!< UNPRIV_INSTRS Bit 0 */ -#define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /*!< UNPRIV_INSTRS Bit 1 */ -#define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /*!< UNPRIV_INSTRS Bit 2 */ -#define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /*!< UNPRIV_INSTRS Bit 3 */ -#define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /*!< no "T variant" instructions exist */ -#define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRBT, LDRT, STRBT, STRT */ -#define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /*!< WITHSHIFTS_INSTRS Bit Offset */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /*!< WITHSHIFTS_INSTRS Bit Mask */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /*!< WITHSHIFTS_INSTRS Bit 0 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /*!< WITHSHIFTS_INSTRS Bit 1 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /*!< WITHSHIFTS_INSTRS Bit 2 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /*!< WITHSHIFTS_INSTRS Bit 3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /*!< non-zero shifts only support MOV and shift instructions (see notes) */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /*!< shifts of loads/stores over the range LSL 0-3 */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /*!< adds other constant shift options. */ -#define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /*!< adds register-controlled shift options. */ -#define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /*!< WRITEBACK_INSTRS Bit Offset */ -#define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /*!< WRITEBACK_INSTRS Bit Mask */ -#define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /*!< WRITEBACK_INSTRS Bit 0 */ -#define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /*!< WRITEBACK_INSTRS Bit 1 */ -#define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /*!< WRITEBACK_INSTRS Bit 2 */ -#define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /*!< WRITEBACK_INSTRS Bit 3 */ -#define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /*!< only non-writeback addressing modes present, except that */ -#define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */ -#define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /*!< BARRIER_INSTRS Bit Offset */ -#define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /*!< BARRIER_INSTRS Bit Mask */ -#define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /*!< BARRIER_INSTRS Bit 0 */ -#define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /*!< BARRIER_INSTRS Bit 1 */ -#define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /*!< BARRIER_INSTRS Bit 2 */ -#define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /*!< BARRIER_INSTRS Bit 3 */ -#define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /*!< no barrier instructions supported */ -#define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /*!< adds DMB, DSB, ISB barrier instructions */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /*!< no additional support */ -#define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */ -#define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /*!< PSR_M_INSTRS Bit Offset */ -#define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /*!< PSR_M_INSTRS Bit Mask */ -#define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /*!< PSR_M_INSTRS Bit 0 */ -#define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /*!< PSR_M_INSTRS Bit 1 */ -#define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /*!< PSR_M_INSTRS Bit 2 */ -#define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /*!< PSR_M_INSTRS Bit 3 */ -#define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /*!< instructions not present */ -#define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */ -#define SCB_CPACR_CP11_OFS (22) /*!< CP11 Bit Offset */ -#define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /*!< CP11 Bit Mask */ -#define SCB_CPACR_CP10_OFS (20) /*!< CP10 Bit Offset */ -#define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /*!< CP10 Bit Mask */ -#define SCB_SHPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ -#define SCB_SHPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ -#define SCB_SHPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ -#define SCB_SHPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ -#define SCB_SHPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ -#define SCB_SHPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ -#define SCB_SHPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ -#define SCB_SHPR1_PRI_7_M ((uint32_t)0xff000000) /* */ -#define SCB_SHPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ -#define SCB_SHPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ -#define SCB_SHPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ -#define SCB_SHPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ -#define SCB_SHPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ -#define SCB_SHPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ -#define SCB_SHPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ -#define SCB_SHPR2_PRI_11_M ((uint32_t)0xff000000) /* */ -#define SCB_SHPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ -#define SCB_SHPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ -#define SCB_SHPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ -#define SCB_SHPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ -#define SCB_SHPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ -#define SCB_SHPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ -#define SCB_SHPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ -#define SCB_SHPR3_PRI_15_M ((uint32_t)0xff000000) /* */ -#define SCB_CFSR_IACCVIOL_OFS ( 0) /*!< IACCVIOL Offset */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /* */ -#define SCB_CFSR_DACCVIOL_OFS ( 1) /*!< DACCVIOL Offset */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /* */ -#define SCB_CFSR_MUNSTKERR_OFS ( 3) /*!< MUNSTKERR Offset */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /* */ -#define SCB_CFSR_MSTKERR_OFS ( 4) /*!< MSTKERR Offset */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /* */ -#define SCB_CFSR_MMARVALID_OFS ( 7) /*!< MMARVALID Offset */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /* */ -#define SCB_CFSR_IBUSERR_OFS ( 8) /*!< IBUSERR Offset */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /* */ -#define SCB_CFSR_PRECISERR_OFS ( 9) /*!< PRECISERR Offset */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /* */ -#define SCB_CFSR_IMPRECISERR_OFS (10) /*!< IMPRECISERR Offset */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /* */ -#define SCB_CFSR_UNSTKERR_OFS (11) /*!< UNSTKERR Offset */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /* */ -#define SCB_CFSR_STKERR_OFS (12) /*!< STKERR Offset */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /* */ -#define SCB_CFSR_BFARVALID_OFS (15) /*!< BFARVALID Offset */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /* */ -#define SCB_CFSR_UNDEFINSTR_OFS (16) /*!< UNDEFINSTR Offset */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /* */ -#define SCB_CFSR_INVSTATE_OFS (17) /*!< INVSTATE Offset */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /* */ -#define SCB_CFSR_INVPC_OFS (18) /*!< INVPC Offset */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /* */ -#define SCB_CFSR_NOCP_OFS (19) /*!< NOCP Offset */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /* */ -#define SCB_CFSR_UNALIGNED_OFS (24) /*!< UNALIGNED Offset */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /* */ -#define SCB_CFSR_DIVBYZERO_OFS (25) /*!< DIVBYZERO Offset */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /* */ -#define SCB_CFSR_MLSPERR_OFS ( 5) /*!< MLSPERR Offset */ -#define SCB_CFSR_MLSPERR ((uint32_t)0x00000020) /* */ -#define SCB_CFSR_LSPERR_OFS (13) /*!< LSPERR Offset */ -#define SCB_CFSR_LSPERR ((uint32_t)0x00002000) /* */ -#define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define SYSCTL_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /*!< Write 1 initiates a Reboot of the device */ -#define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -#define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /*!< CS_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /*!< CS interrupt as a source of NMI */ -#define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /*!< PSS_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /*!< PSS interrupt as a source of NMI */ -#define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /*!< PCM_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /*!< PCM interrupt as a source of NMI */ -#define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /*!< PIN_SRC Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008) -#define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /*!< CS_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /*!< CS interrupt was the source of NMI */ -#define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /*!< PSS_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /*!< PSS interrupt was the source of NMI */ -#define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /*!< PCM_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /*!< PCM interrupt was the source of NMI */ -#define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /*!< PIN_FLG Bit Offset */ -#define SYSCTL_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /*!< RSTn/NMI pin was the source of NMI */ -#define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /*!< TIMEOUT Bit Offset */ -#define SYSCTL_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /*!< WDT timeout reset type */ -#define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /*!< VIOLATION Bit Offset */ -#define SYSCTL_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /*!< WDT password violation reset type */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /*!< HALT_T16_0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /*!< HALT_T16_1 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /*!< HALT_T16_2 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /*!< HALT_T16_3 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /*!< HALT_T32_0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /*!< HALT_eUA0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /*!< HALT_eUA1 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /*!< HALT_eUA2 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /*!< HALT_eUA3 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /*!< HALT_eUB0 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB1_OFS (10) /*!< HALT_eUB1 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB2_OFS (11) /*!< HALT_eUB2 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB3_OFS (12) /*!< HALT_eUB3 Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_ADC_OFS (13) /*!< HALT_ADC Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_WDT_OFS (14) /*!< HALT_WDT Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_PERIHALT_CTL_HALT_DMA_OFS (15) /*!< HALT_DMA Bit Offset */ -#define SYSCTL_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /*!< BNK0_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK0_EN ((uint32_t)0x00000001) /*!< SRAM Bank0 enable */ -#define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /*!< BNK1_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK1_EN ((uint32_t)0x00000002) /*!< SRAM Bank1 enable */ -#define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /*!< BNK2_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK2_EN ((uint32_t)0x00000004) /*!< SRAM Bank1 enable */ -#define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /*!< BNK3_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK3_EN ((uint32_t)0x00000008) /*!< SRAM Bank1 enable */ -#define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /*!< BNK4_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK4_EN ((uint32_t)0x00000010) /*!< SRAM Bank1 enable */ -#define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /*!< BNK5_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK5_EN ((uint32_t)0x00000020) /*!< SRAM Bank1 enable */ -#define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /*!< BNK6_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK6_EN ((uint32_t)0x00000040) /*!< SRAM Bank1 enable */ -#define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /*!< BNK7_EN Bit Offset */ -#define SYSCTL_SRAM_BANKEN_BNK7_EN ((uint32_t)0x00000080) /*!< SRAM Bank1 enable */ -#define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ -#define SYSCTL_SRAM_BANKEN_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ -#define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /*!< BNK0_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK0_RET ((uint32_t)0x00000001) /*!< Bank0 retention */ -#define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /*!< BNK1_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK1_RET ((uint32_t)0x00000002) /*!< Bank1 retention */ -#define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /*!< BNK2_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK2_RET ((uint32_t)0x00000004) /*!< Bank2 retention */ -#define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /*!< BNK3_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK3_RET ((uint32_t)0x00000008) /*!< Bank3 retention */ -#define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /*!< BNK4_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK4_RET ((uint32_t)0x00000010) /*!< Bank4 retention */ -#define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /*!< BNK5_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK5_RET ((uint32_t)0x00000020) /*!< Bank5 retention */ -#define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /*!< BNK6_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK6_RET ((uint32_t)0x00000040) /*!< Bank6 retention */ -#define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /*!< BNK7_RET Bit Offset */ -#define SYSCTL_SRAM_BANKRET_BNK7_RET ((uint32_t)0x00000080) /*!< Bank7 retention */ -#define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ -#define SYSCTL_SRAM_BANKRET_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ -#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /*!< GLTCH_EN Bit Offset */ -#define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /*!< Glitch filter enable */ -#define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -#define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -#define SYSCTL_RESET_REQ_POR_OFS ( 0) /*!< POR Bit Offset */ -#define SYSCTL_RESET_REQ_POR ((uint32_t)0x00000001) /*!< Generate POR */ -#define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /*!< REBOOT Bit Offset */ -#define SYSCTL_RESET_REQ_REBOOT ((uint32_t)0x00000002) /*!< Generate Reboot_Reset */ -#define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -#define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /*!< SOFT Bit Offset */ -#define SYSCTL_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /*!< Indicates if SOFT Reset is active */ -#define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /*!< HARD Bit Offset */ -#define SYSCTL_RESET_STATOVER_HARD ((uint32_t)0x00000002) /*!< Indicates if HARD Reset is active */ -#define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /*!< REBOOT Bit Offset */ -#define SYSCTL_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /*!< Indicates if Reboot Reset is active */ -#define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /*!< SOFT_OVER Bit Offset */ -#define SYSCTL_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /*!< SOFT_Reset overwrite request */ -#define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /*!< HARD_OVER Bit Offset */ -#define SYSCTL_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /*!< HARD_Reset overwrite request */ -#define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /*!< RBT_OVER Bit Offset */ -#define SYSCTL_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /*!< Reboot Reset overwrite request */ -#define SYSCTL_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bit 0 */ -#define TIMER32_CONTROL_ONESHOT_OFS ( 0) /*!< ONESHOT Bit Offset */ -#define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /*!< Selects one-shot or wrapping counter mode */ -#define TIMER32_CONTROL_SIZE_OFS ( 1) /*!< SIZE Bit Offset */ -#define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /*!< Selects 16 or 32 bit counter operation */ -#define TIMER32_CONTROL_PRESCALE_OFS ( 2) /*!< PRESCALE Bit Offset */ -#define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /*!< PRESCALE Bit Mask */ -#define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /*!< PRESCALE Bit 0 */ -#define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /*!< PRESCALE Bit 1 */ -#define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /*!< 0 stages of prescale, clock is divided by 1 */ -#define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /*!< 4 stages of prescale, clock is divided by 16 */ -#define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /*!< 8 stages of prescale, clock is divided by 256 */ -#define TIMER32_CONTROL_IE_OFS ( 5) /*!< IE Bit Offset */ -#define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /*!< Interrupt enable bit */ -#define TIMER32_CONTROL_MODE_OFS ( 6) /*!< MODE Bit Offset */ -#define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /*!< Mode bit */ -#define TIMER32_CONTROL_ENABLE_OFS ( 7) /*!< ENABLE Bit Offset */ -#define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080) -#define TIMER32_RIS_RAW_IFG_OFS ( 0) /*!< RAW_IFG Bit Offset */ -#define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /*!< Raw interrupt status */ -#define TIMER32_MIS_IFG_OFS ( 0) /*!< IFG Bit Offset */ -#define TIMER32_MIS_IFG ((uint32_t)0x00000001) /*!< Enabled interrupt status */ -#define TIMER_A_CTL_IFG_OFS ( 0) /*!< TAIFG Bit Offset */ -#define TIMER_A_CTL_IFG ((uint16_t)0x0001) /*!< TimerA interrupt flag */ -#define TIMER_A_CTL_IE_OFS ( 1) /*!< TAIE Bit Offset */ -#define TIMER_A_CTL_IE ((uint16_t)0x0002) /*!< TimerA interrupt enable */ -#define TIMER_A_CTL_CLR_OFS ( 2) /*!< TACLR Bit Offset */ -#define TIMER_A_CTL_CLR ((uint16_t)0x0004) /*!< TimerA clear */ -#define TIMER_A_CTL_MC_OFS ( 4) /*!< MC Bit Offset */ -#define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /*!< MC Bit Mask */ -#define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /*!< MC Bit 0 */ -#define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /*!< MC Bit 1 */ -#define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -#define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ -#define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ -#define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ -#define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ -#define TIMER_A_CTL_ID_OFS ( 6) /*!< ID Bit Offset */ -#define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /*!< ID Bit Mask */ -#define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /*!< ID Bit 0 */ -#define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /*!< ID Bit 1 */ -#define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /*!< /8 */ -#define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /*!< /1 */ -#define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /*!< /2 */ -#define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /*!< /4 */ -#define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /*!< /8 */ -#define TIMER_A_CTL_SSEL_OFS ( 8) /*!< TASSEL Bit Offset */ -#define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /*!< TASSEL Bit Mask */ -#define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /*!< SSEL Bit 0 */ -#define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /*!< SSEL Bit 1 */ -#define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /*!< INCLK */ -#define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /*!< TAxCLK */ -#define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /*!< ACLK */ -#define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /*!< SMCLK */ -#define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /*!< INCLK */ -#define TIMER_A_CCTLN_CCIFG_OFS ( 0) /*!< CCIFG Bit Offset */ -#define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /*!< Capture/compare interrupt flag */ -#define TIMER_A_CCTLN_COV_OFS ( 1) /*!< COV Bit Offset */ -#define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /*!< Capture overflow */ -#define TIMER_A_CCTLN_OUT_OFS ( 2) /*!< OUT Bit Offset */ -#define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /*!< Output */ -#define TIMER_A_CCTLN_CCI_OFS ( 3) /*!< CCI Bit Offset */ -#define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /*!< Capture/compare input */ -#define TIMER_A_CCTLN_CCIE_OFS ( 4) /*!< CCIE Bit Offset */ -#define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /*!< Capture/compare interrupt enable */ -#define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /*!< OUTMOD Bit Offset */ -#define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /*!< OUTMOD Bit Mask */ -#define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /*!< OUTMOD Bit 0 */ -#define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /*!< OUTMOD Bit 1 */ -#define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /*!< OUTMOD Bit 2 */ -#define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /*!< OUT bit value */ -#define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /*!< Set */ -#define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /*!< Toggle/reset */ -#define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /*!< Set/reset */ -#define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /*!< Toggle */ -#define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /*!< Reset */ -#define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /*!< Toggle/set */ -#define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /*!< Reset/set */ -#define TIMER_A_CCTLN_CAP_OFS ( 8) /*!< CAP Bit Offset */ -#define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /*!< Capture mode */ -#define TIMER_A_CCTLN_SCCI_OFS (10) /*!< SCCI Bit Offset */ -#define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /*!< Synchronized capture/compare input */ -#define TIMER_A_CCTLN_SCS_OFS (11) /*!< SCS Bit Offset */ -#define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /*!< Synchronize capture source */ -#define TIMER_A_CCTLN_CCIS_OFS (12) /*!< CCIS Bit Offset */ -#define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /*!< CCIS Bit Mask */ -#define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /*!< CCIS Bit 0 */ -#define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /*!< CCIS Bit 1 */ -#define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /*!< VCC */ -#define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /*!< CCIxA */ -#define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /*!< CCIxB */ -#define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /*!< GND */ -#define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /*!< VCC */ -#define TIMER_A_CCTLN_CM_OFS (14) /*!< CM Bit Offset */ -#define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /*!< CM Bit Mask */ -#define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /*!< CM Bit 0 */ -#define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /*!< CM Bit 1 */ -#define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -#define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /*!< No capture */ -#define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /*!< Capture on rising edge */ -#define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /*!< Capture on falling edge */ -#define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ -#define TIMER_A_EX0_IDEX_OFS ( 0) /*!< TAIDEX Bit Offset */ -#define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /*!< TAIDEX Bit Mask */ -#define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /*!< IDEX Bit 0 */ -#define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /*!< IDEX Bit 1 */ -#define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /*!< IDEX Bit 2 */ -#define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /*!< Divide by 8 */ -#define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /*!< Divide by 1 */ -#define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /*!< Divide by 2 */ -#define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /*!< Divide by 3 */ -#define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /*!< Divide by 4 */ -#define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /*!< Divide by 5 */ -#define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /*!< Divide by 6 */ -#define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /*!< Divide by 7 */ -#define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /*!< Divide by 8 */ -#define TLV_TAG_RESERVED1 1 -#define TLV_TAG_RESERVED2 2 -#define TLV_TAG_CS 3 -#define TLV_TAG_FLASHCTL 4 -#define TLV_TAG_ADC14 5 -#define TLV_TAG_RESERVED6 6 -#define TLV_TAG_RESERVED7 7 -#define TLV_TAG_REF 8 -#define TLV_TAG_RESERVED9 9 -#define TLV_TAG_RESERVED10 10 -#define TLV_TAG_DEVINFO 11 -#define TLV_TAG_DIEREC 12 -#define TLV_TAG_RANDNUM 13 -#define TLV_TAG_RESERVED14 14 -#define TLV_TAG_BSL 15 -#define TLV_TAG_END (0x0BD0E11D) -#define WDT_A_CTL_IS_OFS ( 0) /*!< WDTIS Bit Offset */ -#define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /*!< WDTIS Bit Mask */ -#define WDT_A_CTL_IS0 ((uint16_t)0x0001) /*!< IS Bit 0 */ -#define WDT_A_CTL_IS1 ((uint16_t)0x0002) /*!< IS Bit 1 */ -#define WDT_A_CTL_IS2 ((uint16_t)0x0004) /*!< IS Bit 2 */ -#define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ -#define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ -#define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ -#define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ -#define WDT_A_CTL_CNTCL_OFS ( 3) /*!< WDTCNTCL Bit Offset */ -#define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /*!< Watchdog timer counter clear */ -#define WDT_A_CTL_TMSEL_OFS ( 4) /*!< WDTTMSEL Bit Offset */ -#define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /*!< Watchdog timer mode select */ -#define WDT_A_CTL_SSEL_OFS ( 5) /*!< WDTSSEL Bit Offset */ -#define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /*!< WDTSSEL Bit Mask */ -#define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /*!< SSEL Bit 0 */ -#define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /*!< SSEL Bit 1 */ -#define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /*!< BCLK */ -#define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /*!< SMCLK */ -#define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /*!< ACLK */ -#define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /*!< VLOCLK */ -#define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /*!< BCLK */ -#define WDT_A_CTL_HOLD_OFS ( 7) /*!< WDTHOLD Bit Offset */ -#define WDT_A_CTL_HOLD ((uint16_t)0x0080) /*!< Watchdog timer hold */ -#define WDT_A_CTL_PW_OFS ( 8) /*!< WDTPW Bit Offset */ -#define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /*!< WDTPW Bit Mask */ -#define WDT_A_CTL_PW ((uint16_t)0x5A00) /*!< WDT Key Value for WDT write access */ -#define FLCTL_A_POWER_STAT_PSTAT_OFS ( 0) /*!< PSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /*!< PSTAT Bit Mask */ -#define FLCTL_A_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /*!< PSTAT Bit 0 */ -#define FLCTL_A_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /*!< PSTAT Bit 1 */ -#define FLCTL_A_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /*!< PSTAT Bit 2 */ -#define FLCTL_A_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /*!< Flash IP in power-down mode */ -#define FLCTL_A_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /*!< Flash IP Vdd domain power-up in progress */ -#define FLCTL_A_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */ -#define FLCTL_A_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /*!< Flash IP SAFE_LV check in progress */ -#define FLCTL_A_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /*!< Flash IP Active */ -#define FLCTL_A_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */ -#define FLCTL_A_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /*!< Flash IP in Standby mode */ -#define FLCTL_A_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /*!< Flash IP in Current mirror boost state */ -#define FLCTL_A_POWER_STAT_LDOSTAT_OFS ( 3) /*!< LDOSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /*!< PSS FLDO GOOD status */ -#define FLCTL_A_POWER_STAT_VREFSTAT_OFS ( 4) /*!< VREFSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /*!< PSS VREF stable status */ -#define FLCTL_A_POWER_STAT_IREFSTAT_OFS ( 5) /*!< IREFSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /*!< PSS IREF stable status */ -#define FLCTL_A_POWER_STAT_TRIMSTAT_OFS ( 6) /*!< TRIMSTAT Bit Offset */ -#define FLCTL_A_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /*!< PSS trim done status */ -#define FLCTL_A_POWER_STAT_RD_2T_OFS ( 7) /*!< RD_2T Bit Offset */ -#define FLCTL_A_POWER_STAT_RD_2T ((uint32_t)0x00000080) /*!< Indicates if Flash is being accessed in 2T mode */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -#define FLCTL_A_BANK0_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -#define FLCTL_A_BANK0_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -#define FLCTL_A_BANK0_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_A_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_A_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_A_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_A_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_A_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_A_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ -#define FLCTL_A_BANK1_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ -#define FLCTL_A_BANK1_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ -#define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ -#define FLCTL_A_BANK1_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ -#define FLCTL_A_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ -#define FLCTL_A_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ -#define FLCTL_A_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ -#define FLCTL_A_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ -#define FLCTL_A_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ -#define FLCTL_A_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ -#define FLCTL_A_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ -#define FLCTL_A_RDBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of burst/compare operation */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /*!< MEM_TYPE Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /*!< MEM_TYPE Bit Mask */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /*!< MEM_TYPE Bit 0 */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /*!< MEM_TYPE Bit 1 */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -#define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /*!< STOP_FAIL Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /*!< Terminate burst/compare operation */ -#define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /*!< DATA_CMP Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /*!< Data pattern used for comparison against memory read data */ -#define FLCTL_A_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /*!< TEST_EN Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /*!< Enable comparison against test data compare registers */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /*!< BRST_STAT Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /*!< BRST_STAT Bit Mask */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /*!< BRST_STAT Bit 0 */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /*!< BRST_STAT Bit 1 */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /*!< Idle */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /*!< Burst/Compare START bit written, but operation pending */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /*!< Burst/Compare in progress */ -#define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /*!< Burst complete (status of completed burst remains in this state unless */ -#define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /*!< CMP_ERR Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /*!< Burst/Compare Operation encountered atleast one data */ -#define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /*!< Burst/Compare Operation was terminated due to access to */ -#define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 19-16 of this register */ -#define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< START_ADDRESS Bit Mask */ -#define FLCTL_A_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /*!< BURST_LENGTH Bit Offset */ -#define FLCTL_A_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /*!< BURST_LENGTH Bit Mask */ -#define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /*!< FAIL_ADDRESS Bit Offset */ -#define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< FAIL_ADDRESS Bit Mask */ -#define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /*!< FAIL_COUNT Bit Offset */ -#define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /*!< FAIL_COUNT Bit Mask */ -#define FLCTL_A_PRG_CTLSTAT_ENABLE_OFS ( 0) /*!< ENABLE Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /*!< Master control for all word program operations */ -#define FLCTL_A_PRG_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Write mode */ -#define FLCTL_A_PRG_CTLSTAT_VER_PRE_OFS ( 2) /*!< VER_PRE Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /*!< Controls automatic pre program verify operations */ -#define FLCTL_A_PRG_CTLSTAT_VER_PST_OFS ( 3) /*!< VER_PST Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /*!< Controls automatic post program verify operations */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_A_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_A_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Single word program operation triggered, but pending */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Single word program in progress */ -#define FLCTL_A_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Reserved (Idle) */ -#define FLCTL_A_PRG_CTLSTAT_BNK_ACT_OFS (18) /*!< BNK_ACT Bit Offset */ -#define FLCTL_A_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /*!< Bank active */ -#define FLCTL_A_PRGBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Trigger start of burst program operation */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /*!< TYPE Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /*!< TYPE Bit Mask */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /*!< TYPE Bit 0 */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /*!< TYPE Bit 1 */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ -#define FLCTL_A_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_OFS ( 3) /*!< LEN Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /*!< LEN Bit Mask */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /*!< LEN Bit 0 */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /*!< LEN Bit 1 */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /*!< LEN Bit 2 */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /*!< No burst operation */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /*!< 1 word burst of 128 bits, starting with address in the */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ -#define FLCTL_A_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /*!< AUTO_PRE Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /*!< Auto-Verify operation before the Burst Program */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /*!< AUTO_PST Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /*!< Auto-Verify operation after the Burst Program */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /*!< BURST_STATUS Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /*!< BURST_STATUS Bit Mask */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /*!< BURST_STATUS Bit 0 */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /*!< BURST_STATUS Bit 1 */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /*!< BURST_STATUS Bit 2 */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (Burst not active) */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /*!< Burst program started but pending */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /*!< Burst active, with 1st 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /*!< Burst active, with 2nd 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /*!< Burst active, with 3rd 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /*!< Burst active, with 4th 128 bit word being written into Flash */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /*!< Reserved (Idle) */ -#define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /*!< Burst Complete (status of completed burst remains in this state unless */ -#define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /*!< PRE_ERR Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /*!< Burst Operation encountered preprogram auto-verify errors */ -#define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /*!< PST_ERR Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /*!< Burst Operation encountered postprogram auto-verify errors */ -#define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /*!< Burst Operation was terminated due to attempted program of reserved memory */ -#define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ -#define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 21-16 of this register */ -#define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ -#define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< START_ADDRESS Bit Mask */ -#define FLCTL_A_ERASE_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of Erase operation */ -#define FLCTL_A_ERASE_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Erase mode selected by application */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_OFS ( 2) /*!< TYPE Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /*!< TYPE Bit Mask */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /*!< TYPE Bit 0 */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /*!< TYPE Bit 1 */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /*!< Information Memory */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /*!< Reserved */ -#define FLCTL_A_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /*!< Engineering Memory */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Erase operation triggered to START but pending */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Erase operation in progress */ -#define FLCTL_A_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Erase operation completed (status of completed erase remains in this state */ -#define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /*!< ADDR_ERR Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /*!< Erase Operation was terminated due to attempted erase of reserved memory */ -#define FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS (19) /*!< CLR_STAT Bit Offset */ -#define FLCTL_A_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /*!< Clear status bits 18-16 of this register */ -#define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /*!< SECT_ADDRESS Bit Offset */ -#define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< SECT_ADDRESS Bit Mask */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK0_INFO_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK1_INFO_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase operations */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase operations */ -#define FLCTL_A_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /*!< I_BMRK Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001) -#define FLCTL_A_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /*!< D_BMRK Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002) -#define FLCTL_A_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /*!< CMP_EN Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004) -#define FLCTL_A_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /*!< CMP_SEL Bit Offset */ -#define FLCTL_A_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008) -#define FLCTL_A_IFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_IFG_RDBRST ((uint32_t)0x00000001) -#define FLCTL_A_IFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_IFG_AVPRE ((uint32_t)0x00000002) -#define FLCTL_A_IFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_IFG_AVPST ((uint32_t)0x00000004) -#define FLCTL_A_IFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_IFG_PRG ((uint32_t)0x00000008) -#define FLCTL_A_IFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_IFG_PRGB ((uint32_t)0x00000010) -#define FLCTL_A_IFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_IFG_ERASE ((uint32_t)0x00000020) -#define FLCTL_A_IFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_IFG_BMRK ((uint32_t)0x00000100) -#define FLCTL_A_IFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_IFG_PRG_ERR ((uint32_t)0x00000200) -#define FLCTL_A_IE_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_IE_RDBRST ((uint32_t)0x00000001) -#define FLCTL_A_IE_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_IE_AVPRE ((uint32_t)0x00000002) -#define FLCTL_A_IE_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_IE_AVPST ((uint32_t)0x00000004) -#define FLCTL_A_IE_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_IE_PRG ((uint32_t)0x00000008) -#define FLCTL_A_IE_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_IE_PRGB ((uint32_t)0x00000010) -#define FLCTL_A_IE_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_IE_ERASE ((uint32_t)0x00000020) -#define FLCTL_A_IE_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_IE_BMRK ((uint32_t)0x00000100) -#define FLCTL_A_IE_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_IE_PRG_ERR ((uint32_t)0x00000200) -#define FLCTL_A_CLRIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_CLRIFG_RDBRST ((uint32_t)0x00000001) -#define FLCTL_A_CLRIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_CLRIFG_AVPRE ((uint32_t)0x00000002) -#define FLCTL_A_CLRIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_CLRIFG_AVPST ((uint32_t)0x00000004) -#define FLCTL_A_CLRIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_CLRIFG_PRG ((uint32_t)0x00000008) -#define FLCTL_A_CLRIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_CLRIFG_PRGB ((uint32_t)0x00000010) -#define FLCTL_A_CLRIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_CLRIFG_ERASE ((uint32_t)0x00000020) -#define FLCTL_A_CLRIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_CLRIFG_BMRK ((uint32_t)0x00000100) -#define FLCTL_A_CLRIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_CLRIFG_PRG_ERR ((uint32_t)0x00000200) -#define FLCTL_A_SETIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ -#define FLCTL_A_SETIFG_RDBRST ((uint32_t)0x00000001) -#define FLCTL_A_SETIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ -#define FLCTL_A_SETIFG_AVPRE ((uint32_t)0x00000002) -#define FLCTL_A_SETIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ -#define FLCTL_A_SETIFG_AVPST ((uint32_t)0x00000004) -#define FLCTL_A_SETIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ -#define FLCTL_A_SETIFG_PRG ((uint32_t)0x00000008) -#define FLCTL_A_SETIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ -#define FLCTL_A_SETIFG_PRGB ((uint32_t)0x00000010) -#define FLCTL_A_SETIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ -#define FLCTL_A_SETIFG_ERASE ((uint32_t)0x00000020) -#define FLCTL_A_SETIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ -#define FLCTL_A_SETIFG_BMRK ((uint32_t)0x00000100) -#define FLCTL_A_SETIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ -#define FLCTL_A_SETIFG_PRG_ERR ((uint32_t)0x00000200) -#define FLCTL_A_READ_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_A_READ_TIMCTL_IREF_BOOST1_OFS (12) /*!< IREF_BOOST1 Bit Offset */ -#define FLCTL_A_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /*!< IREF_BOOST1 Bit Mask */ -#define FLCTL_A_READ_TIMCTL_SETUP_LONG_OFS (16) /*!< SETUP_LONG Bit Offset */ -#define FLCTL_A_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /*!< SETUP_LONG Bit Mask */ -#define FLCTL_A_READMARGIN_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_A_PRGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_A_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /*!< ACTIVE Bit Mask */ -#define FLCTL_A_PRGVER_TIMCTL_HOLD_OFS (12) /*!< HOLD Bit Offset */ -#define FLCTL_A_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /*!< HOLD Bit Mask */ -#define FLCTL_A_ERSVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_A_LKGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_A_PROGRAM_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -#define FLCTL_A_PROGRAM_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_A_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -#define FLCTL_A_ERASE_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ -#define FLCTL_A_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ -#define FLCTL_A_ERASE_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -#define FLCTL_A_ERASE_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ -#define FLCTL_A_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /*!< BOOST_ACTIVE Bit Offset */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /*!< BOOST_ACTIVE Bit Mask */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /*!< BOOST_HOLD Bit Offset */ -#define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /*!< BOOST_HOLD Bit Mask */ -#define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ -#define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32_OFS ( 0) /*!< PROT32 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32 ((uint32_t)0x00000001) /*!< Protects Sector 32 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33_OFS ( 1) /*!< PROT33 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33 ((uint32_t)0x00000002) /*!< Protects Sector 33 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34_OFS ( 2) /*!< PROT34 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34 ((uint32_t)0x00000004) /*!< Protects Sector 34 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35_OFS ( 3) /*!< PROT35 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35 ((uint32_t)0x00000008) /*!< Protects Sector 35 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36_OFS ( 4) /*!< PROT36 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36 ((uint32_t)0x00000010) /*!< Protects Sector 36 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37_OFS ( 5) /*!< PROT37 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37 ((uint32_t)0x00000020) /*!< Protects Sector 37 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38_OFS ( 6) /*!< PROT38 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38 ((uint32_t)0x00000040) /*!< Protects Sector 38 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39_OFS ( 7) /*!< PROT39 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39 ((uint32_t)0x00000080) /*!< Protects Sector 39 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40_OFS ( 8) /*!< PROT40 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40 ((uint32_t)0x00000100) /*!< Protects Sector 40 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41_OFS ( 9) /*!< PROT41 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41 ((uint32_t)0x00000200) /*!< Protects Sector 41 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42_OFS (10) /*!< PROT42 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42 ((uint32_t)0x00000400) /*!< Protects Sector 42 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43_OFS (11) /*!< PROT43 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43 ((uint32_t)0x00000800) /*!< Protects Sector 43 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44_OFS (12) /*!< PROT44 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44 ((uint32_t)0x00001000) /*!< Protects Sector 44 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45_OFS (13) /*!< PROT45 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45 ((uint32_t)0x00002000) /*!< Protects Sector 45 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46_OFS (14) /*!< PROT46 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46 ((uint32_t)0x00004000) /*!< Protects Sector 46 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47_OFS (15) /*!< PROT47 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47 ((uint32_t)0x00008000) /*!< Protects Sector 47 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48_OFS (16) /*!< PROT48 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48 ((uint32_t)0x00010000) /*!< Protects Sector 48 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49_OFS (17) /*!< PROT49 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49 ((uint32_t)0x00020000) /*!< Protects Sector 49 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50_OFS (18) /*!< PROT50 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50 ((uint32_t)0x00040000) /*!< Protects Sector 50 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51_OFS (19) /*!< PROT51 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51 ((uint32_t)0x00080000) /*!< Protects Sector 51 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52_OFS (20) /*!< PROT52 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52 ((uint32_t)0x00100000) /*!< Protects Sector 52 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53_OFS (21) /*!< PROT53 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53 ((uint32_t)0x00200000) /*!< Protects Sector 53 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54_OFS (22) /*!< PROT54 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54 ((uint32_t)0x00400000) /*!< Protects Sector 54 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55_OFS (23) /*!< PROT55 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55 ((uint32_t)0x00800000) /*!< Protects Sector 55 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56_OFS (24) /*!< PROT56 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56 ((uint32_t)0x01000000) /*!< Protects Sector 56 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57_OFS (25) /*!< PROT57 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57 ((uint32_t)0x02000000) /*!< Protects Sector 57 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58_OFS (26) /*!< PROT58 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58 ((uint32_t)0x04000000) /*!< Protects Sector 58 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59_OFS (27) /*!< PROT59 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59 ((uint32_t)0x08000000) /*!< Protects Sector 59 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60_OFS (28) /*!< PROT60 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60 ((uint32_t)0x10000000) /*!< Protects Sector 60 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61_OFS (29) /*!< PROT61 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61 ((uint32_t)0x20000000) /*!< Protects Sector 61 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62_OFS (30) /*!< PROT62 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62 ((uint32_t)0x40000000) /*!< Protects Sector 62 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63_OFS (31) /*!< PROT63 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63 ((uint32_t)0x80000000) /*!< Protects Sector 63 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64_OFS ( 0) /*!< PROT64 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64 ((uint32_t)0x00000001) /*!< Protects Sector 64 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65_OFS ( 1) /*!< PROT65 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65 ((uint32_t)0x00000002) /*!< Protects Sector 65 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66_OFS ( 2) /*!< PROT66 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66 ((uint32_t)0x00000004) /*!< Protects Sector 66 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67_OFS ( 3) /*!< PROT67 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67 ((uint32_t)0x00000008) /*!< Protects Sector 67 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68_OFS ( 4) /*!< PROT68 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68 ((uint32_t)0x00000010) /*!< Protects Sector 68 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69_OFS ( 5) /*!< PROT69 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69 ((uint32_t)0x00000020) /*!< Protects Sector 69 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70_OFS ( 6) /*!< PROT70 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70 ((uint32_t)0x00000040) /*!< Protects Sector 70 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71_OFS ( 7) /*!< PROT71 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71 ((uint32_t)0x00000080) /*!< Protects Sector 71 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72_OFS ( 8) /*!< PROT72 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72 ((uint32_t)0x00000100) /*!< Protects Sector 72 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73_OFS ( 9) /*!< PROT73 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73 ((uint32_t)0x00000200) /*!< Protects Sector 73 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74_OFS (10) /*!< PROT74 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74 ((uint32_t)0x00000400) /*!< Protects Sector 74 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75_OFS (11) /*!< PROT75 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75 ((uint32_t)0x00000800) /*!< Protects Sector 75 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76_OFS (12) /*!< PROT76 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76 ((uint32_t)0x00001000) /*!< Protects Sector 76 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77_OFS (13) /*!< PROT77 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77 ((uint32_t)0x00002000) /*!< Protects Sector 77 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78_OFS (14) /*!< PROT78 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78 ((uint32_t)0x00004000) /*!< Protects Sector 78 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79_OFS (15) /*!< PROT79 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79 ((uint32_t)0x00008000) /*!< Protects Sector 79 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80_OFS (16) /*!< PROT80 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80 ((uint32_t)0x00010000) /*!< Protects Sector 80 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81_OFS (17) /*!< PROT81 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81 ((uint32_t)0x00020000) /*!< Protects Sector 81 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82_OFS (18) /*!< PROT82 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82 ((uint32_t)0x00040000) /*!< Protects Sector 82 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83_OFS (19) /*!< PROT83 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83 ((uint32_t)0x00080000) /*!< Protects Sector 83 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84_OFS (20) /*!< PROT84 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84 ((uint32_t)0x00100000) /*!< Protects Sector 84 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85_OFS (21) /*!< PROT85 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85 ((uint32_t)0x00200000) /*!< Protects Sector 85 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86_OFS (22) /*!< PROT86 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86 ((uint32_t)0x00400000) /*!< Protects Sector 86 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87_OFS (23) /*!< PROT87 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87 ((uint32_t)0x00800000) /*!< Protects Sector 87 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88_OFS (24) /*!< PROT88 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88 ((uint32_t)0x01000000) /*!< Protects Sector 88 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89_OFS (25) /*!< PROT89 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89 ((uint32_t)0x02000000) /*!< Protects Sector 89 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90_OFS (26) /*!< PROT90 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90 ((uint32_t)0x04000000) /*!< Protects Sector 90 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91_OFS (27) /*!< PROT91 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91 ((uint32_t)0x08000000) /*!< Protects Sector 91 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92_OFS (28) /*!< PROT92 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92 ((uint32_t)0x10000000) /*!< Protects Sector 92 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93_OFS (29) /*!< PROT93 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93 ((uint32_t)0x20000000) /*!< Protects Sector 93 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94_OFS (30) /*!< PROT94 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94 ((uint32_t)0x40000000) /*!< Protects Sector 94 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95_OFS (31) /*!< PROT95 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95 ((uint32_t)0x80000000) /*!< Protects Sector 95 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96_OFS ( 0) /*!< PROT96 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96 ((uint32_t)0x00000001) /*!< Protects Sector 96 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97_OFS ( 1) /*!< PROT97 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97 ((uint32_t)0x00000002) /*!< Protects Sector 97 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98_OFS ( 2) /*!< PROT98 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98 ((uint32_t)0x00000004) /*!< Protects Sector 98 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99_OFS ( 3) /*!< PROT99 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99 ((uint32_t)0x00000008) /*!< Protects Sector 99 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100_OFS ( 4) /*!< PROT100 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100 ((uint32_t)0x00000010) /*!< Protects Sector 100 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101_OFS ( 5) /*!< PROT101 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101 ((uint32_t)0x00000020) /*!< Protects Sector 101 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102_OFS ( 6) /*!< PROT102 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102 ((uint32_t)0x00000040) /*!< Protects Sector 102 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103_OFS ( 7) /*!< PROT103 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103 ((uint32_t)0x00000080) /*!< Protects Sector 103 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104_OFS ( 8) /*!< PROT104 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104 ((uint32_t)0x00000100) /*!< Protects Sector 104 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105_OFS ( 9) /*!< PROT105 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105 ((uint32_t)0x00000200) /*!< Protects Sector 105 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106_OFS (10) /*!< PROT106 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106 ((uint32_t)0x00000400) /*!< Protects Sector 106 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107_OFS (11) /*!< PROT107 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107 ((uint32_t)0x00000800) /*!< Protects Sector 107 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108_OFS (12) /*!< PROT108 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108 ((uint32_t)0x00001000) /*!< Protects Sector 108 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109_OFS (13) /*!< PROT109 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109 ((uint32_t)0x00002000) /*!< Protects Sector 109 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110_OFS (14) /*!< PROT110 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110 ((uint32_t)0x00004000) /*!< Protects Sector 110 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111_OFS (15) /*!< PROT111 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111 ((uint32_t)0x00008000) /*!< Protects Sector 111 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112_OFS (16) /*!< PROT112 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112 ((uint32_t)0x00010000) /*!< Protects Sector 112 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113_OFS (17) /*!< PROT113 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113 ((uint32_t)0x00020000) /*!< Protects Sector 113 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114_OFS (18) /*!< PROT114 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114 ((uint32_t)0x00040000) /*!< Protects Sector 114 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115_OFS (19) /*!< PROT115 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115 ((uint32_t)0x00080000) /*!< Protects Sector 115 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116_OFS (20) /*!< PROT116 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116 ((uint32_t)0x00100000) /*!< Protects Sector 116 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117_OFS (21) /*!< PROT117 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117 ((uint32_t)0x00200000) /*!< Protects Sector 117 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118_OFS (22) /*!< PROT118 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118 ((uint32_t)0x00400000) /*!< Protects Sector 118 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119_OFS (23) /*!< PROT119 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119 ((uint32_t)0x00800000) /*!< Protects Sector 119 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120_OFS (24) /*!< PROT120 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120 ((uint32_t)0x01000000) /*!< Protects Sector 120 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121_OFS (25) /*!< PROT121 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121 ((uint32_t)0x02000000) /*!< Protects Sector 121 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122_OFS (26) /*!< PROT122 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122 ((uint32_t)0x04000000) /*!< Protects Sector 122 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123_OFS (27) /*!< PROT123 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123 ((uint32_t)0x08000000) /*!< Protects Sector 123 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124_OFS (28) /*!< PROT124 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124 ((uint32_t)0x10000000) /*!< Protects Sector 124 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125_OFS (29) /*!< PROT125 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125 ((uint32_t)0x20000000) /*!< Protects Sector 125 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126_OFS (30) /*!< PROT126 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126 ((uint32_t)0x40000000) /*!< Protects Sector 126 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127_OFS (31) /*!< PROT127 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127 ((uint32_t)0x80000000) /*!< Protects Sector 127 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128_OFS ( 0) /*!< PROT128 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128 ((uint32_t)0x00000001) /*!< Protects Sector 128 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129_OFS ( 1) /*!< PROT129 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129 ((uint32_t)0x00000002) /*!< Protects Sector 129 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130_OFS ( 2) /*!< PROT130 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130 ((uint32_t)0x00000004) /*!< Protects Sector 130 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131_OFS ( 3) /*!< PROT131 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131 ((uint32_t)0x00000008) /*!< Protects Sector 131 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132_OFS ( 4) /*!< PROT132 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132 ((uint32_t)0x00000010) /*!< Protects Sector 132 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133_OFS ( 5) /*!< PROT133 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133 ((uint32_t)0x00000020) /*!< Protects Sector 133 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134_OFS ( 6) /*!< PROT134 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134 ((uint32_t)0x00000040) /*!< Protects Sector 134 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135_OFS ( 7) /*!< PROT135 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135 ((uint32_t)0x00000080) /*!< Protects Sector 135 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136_OFS ( 8) /*!< PROT136 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136 ((uint32_t)0x00000100) /*!< Protects Sector 136 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137_OFS ( 9) /*!< PROT137 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137 ((uint32_t)0x00000200) /*!< Protects Sector 137 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138_OFS (10) /*!< PROT138 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138 ((uint32_t)0x00000400) /*!< Protects Sector 138 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139_OFS (11) /*!< PROT139 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139 ((uint32_t)0x00000800) /*!< Protects Sector 139 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140_OFS (12) /*!< PROT140 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140 ((uint32_t)0x00001000) /*!< Protects Sector 140 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141_OFS (13) /*!< PROT141 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141 ((uint32_t)0x00002000) /*!< Protects Sector 141 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142_OFS (14) /*!< PROT142 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142 ((uint32_t)0x00004000) /*!< Protects Sector 142 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143_OFS (15) /*!< PROT143 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143 ((uint32_t)0x00008000) /*!< Protects Sector 143 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144_OFS (16) /*!< PROT144 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144 ((uint32_t)0x00010000) /*!< Protects Sector 144 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145_OFS (17) /*!< PROT145 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145 ((uint32_t)0x00020000) /*!< Protects Sector 145 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146_OFS (18) /*!< PROT146 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146 ((uint32_t)0x00040000) /*!< Protects Sector 146 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147_OFS (19) /*!< PROT147 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147 ((uint32_t)0x00080000) /*!< Protects Sector 147 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148_OFS (20) /*!< PROT148 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148 ((uint32_t)0x00100000) /*!< Protects Sector 148 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149_OFS (21) /*!< PROT149 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149 ((uint32_t)0x00200000) /*!< Protects Sector 149 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150_OFS (22) /*!< PROT150 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150 ((uint32_t)0x00400000) /*!< Protects Sector 150 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151_OFS (23) /*!< PROT151 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151 ((uint32_t)0x00800000) /*!< Protects Sector 151 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152_OFS (24) /*!< PROT152 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152 ((uint32_t)0x01000000) /*!< Protects Sector 152 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153_OFS (25) /*!< PROT153 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153 ((uint32_t)0x02000000) /*!< Protects Sector 153 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154_OFS (26) /*!< PROT154 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154 ((uint32_t)0x04000000) /*!< Protects Sector 154 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155_OFS (27) /*!< PROT155 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155 ((uint32_t)0x08000000) /*!< Protects Sector 155 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156_OFS (28) /*!< PROT156 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156 ((uint32_t)0x10000000) /*!< Protects Sector 156 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157_OFS (29) /*!< PROT157 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157 ((uint32_t)0x20000000) /*!< Protects Sector 157 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158_OFS (30) /*!< PROT158 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158 ((uint32_t)0x40000000) /*!< Protects Sector 158 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159_OFS (31) /*!< PROT159 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159 ((uint32_t)0x80000000) /*!< Protects Sector 159 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160_OFS ( 0) /*!< PROT160 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160 ((uint32_t)0x00000001) /*!< Protects Sector 160 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161_OFS ( 1) /*!< PROT161 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161 ((uint32_t)0x00000002) /*!< Protects Sector 161 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162_OFS ( 2) /*!< PROT162 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162 ((uint32_t)0x00000004) /*!< Protects Sector 162 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163_OFS ( 3) /*!< PROT163 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163 ((uint32_t)0x00000008) /*!< Protects Sector 163 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164_OFS ( 4) /*!< PROT164 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164 ((uint32_t)0x00000010) /*!< Protects Sector 164 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165_OFS ( 5) /*!< PROT165 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165 ((uint32_t)0x00000020) /*!< Protects Sector 165 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166_OFS ( 6) /*!< PROT166 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166 ((uint32_t)0x00000040) /*!< Protects Sector 166 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167_OFS ( 7) /*!< PROT167 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167 ((uint32_t)0x00000080) /*!< Protects Sector 167 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168_OFS ( 8) /*!< PROT168 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168 ((uint32_t)0x00000100) /*!< Protects Sector 168 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169_OFS ( 9) /*!< PROT169 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169 ((uint32_t)0x00000200) /*!< Protects Sector 169 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170_OFS (10) /*!< PROT170 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170 ((uint32_t)0x00000400) /*!< Protects Sector 170 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171_OFS (11) /*!< PROT171 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171 ((uint32_t)0x00000800) /*!< Protects Sector 171 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172_OFS (12) /*!< PROT172 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172 ((uint32_t)0x00001000) /*!< Protects Sector 172 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173_OFS (13) /*!< PROT173 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173 ((uint32_t)0x00002000) /*!< Protects Sector 173 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174_OFS (14) /*!< PROT174 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174 ((uint32_t)0x00004000) /*!< Protects Sector 174 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175_OFS (15) /*!< PROT175 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175 ((uint32_t)0x00008000) /*!< Protects Sector 175 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176_OFS (16) /*!< PROT176 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176 ((uint32_t)0x00010000) /*!< Protects Sector 176 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177_OFS (17) /*!< PROT177 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177 ((uint32_t)0x00020000) /*!< Protects Sector 177 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178_OFS (18) /*!< PROT178 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178 ((uint32_t)0x00040000) /*!< Protects Sector 178 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179_OFS (19) /*!< PROT179 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179 ((uint32_t)0x00080000) /*!< Protects Sector 179 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180_OFS (20) /*!< PROT180 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180 ((uint32_t)0x00100000) /*!< Protects Sector 180 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181_OFS (21) /*!< PROT181 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181 ((uint32_t)0x00200000) /*!< Protects Sector 181 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182_OFS (22) /*!< PROT182 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182 ((uint32_t)0x00400000) /*!< Protects Sector 182 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183_OFS (23) /*!< PROT183 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183 ((uint32_t)0x00800000) /*!< Protects Sector 183 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184_OFS (24) /*!< PROT184 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184 ((uint32_t)0x01000000) /*!< Protects Sector 184 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185_OFS (25) /*!< PROT185 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185 ((uint32_t)0x02000000) /*!< Protects Sector 185 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186_OFS (26) /*!< PROT186 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186 ((uint32_t)0x04000000) /*!< Protects Sector 186 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187_OFS (27) /*!< PROT187 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187 ((uint32_t)0x08000000) /*!< Protects Sector 187 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188_OFS (28) /*!< PROT188 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188 ((uint32_t)0x10000000) /*!< Protects Sector 188 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189_OFS (29) /*!< PROT189 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189 ((uint32_t)0x20000000) /*!< Protects Sector 189 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190_OFS (30) /*!< PROT190 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190 ((uint32_t)0x40000000) /*!< Protects Sector 190 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191_OFS (31) /*!< PROT191 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191 ((uint32_t)0x80000000) /*!< Protects Sector 191 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192_OFS ( 0) /*!< PROT192 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192 ((uint32_t)0x00000001) /*!< Protects Sector 192 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193_OFS ( 1) /*!< PROT193 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193 ((uint32_t)0x00000002) /*!< Protects Sector 193 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194_OFS ( 2) /*!< PROT194 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194 ((uint32_t)0x00000004) /*!< Protects Sector 194 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195_OFS ( 3) /*!< PROT195 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195 ((uint32_t)0x00000008) /*!< Protects Sector 195 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196_OFS ( 4) /*!< PROT196 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196 ((uint32_t)0x00000010) /*!< Protects Sector 196 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197_OFS ( 5) /*!< PROT197 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197 ((uint32_t)0x00000020) /*!< Protects Sector 197 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198_OFS ( 6) /*!< PROT198 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198 ((uint32_t)0x00000040) /*!< Protects Sector 198 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199_OFS ( 7) /*!< PROT199 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199 ((uint32_t)0x00000080) /*!< Protects Sector 199 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200_OFS ( 8) /*!< PROT200 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200 ((uint32_t)0x00000100) /*!< Protects Sector 200 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201_OFS ( 9) /*!< PROT201 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201 ((uint32_t)0x00000200) /*!< Protects Sector 201 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202_OFS (10) /*!< PROT202 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202 ((uint32_t)0x00000400) /*!< Protects Sector 202 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203_OFS (11) /*!< PROT203 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203 ((uint32_t)0x00000800) /*!< Protects Sector 203 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204_OFS (12) /*!< PROT204 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204 ((uint32_t)0x00001000) /*!< Protects Sector 204 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205_OFS (13) /*!< PROT205 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205 ((uint32_t)0x00002000) /*!< Protects Sector 205 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206_OFS (14) /*!< PROT206 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206 ((uint32_t)0x00004000) /*!< Protects Sector 206 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207_OFS (15) /*!< PROT207 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207 ((uint32_t)0x00008000) /*!< Protects Sector 207 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208_OFS (16) /*!< PROT208 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208 ((uint32_t)0x00010000) /*!< Protects Sector 208 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209_OFS (17) /*!< PROT209 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209 ((uint32_t)0x00020000) /*!< Protects Sector 209 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210_OFS (18) /*!< PROT210 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210 ((uint32_t)0x00040000) /*!< Protects Sector 210 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211_OFS (19) /*!< PROT211 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211 ((uint32_t)0x00080000) /*!< Protects Sector 211 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212_OFS (20) /*!< PROT212 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212 ((uint32_t)0x00100000) /*!< Protects Sector 212 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213_OFS (21) /*!< PROT213 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213 ((uint32_t)0x00200000) /*!< Protects Sector 213 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214_OFS (22) /*!< PROT214 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214 ((uint32_t)0x00400000) /*!< Protects Sector 214 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215_OFS (23) /*!< PROT215 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215 ((uint32_t)0x00800000) /*!< Protects Sector 215 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216_OFS (24) /*!< PROT216 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216 ((uint32_t)0x01000000) /*!< Protects Sector 216 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217_OFS (25) /*!< PROT217 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217 ((uint32_t)0x02000000) /*!< Protects Sector 217 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218_OFS (26) /*!< PROT218 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218 ((uint32_t)0x04000000) /*!< Protects Sector 218 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219_OFS (27) /*!< PROT219 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219 ((uint32_t)0x08000000) /*!< Protects Sector 219 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220_OFS (28) /*!< PROT220 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220 ((uint32_t)0x10000000) /*!< Protects Sector 220 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221_OFS (29) /*!< PROT221 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221 ((uint32_t)0x20000000) /*!< Protects Sector 221 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222_OFS (30) /*!< PROT222 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222 ((uint32_t)0x40000000) /*!< Protects Sector 222 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223_OFS (31) /*!< PROT223 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223 ((uint32_t)0x80000000) /*!< Protects Sector 223 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224_OFS ( 0) /*!< PROT224 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224 ((uint32_t)0x00000001) /*!< Protects Sector 224 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225_OFS ( 1) /*!< PROT225 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225 ((uint32_t)0x00000002) /*!< Protects Sector 225 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226_OFS ( 2) /*!< PROT226 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226 ((uint32_t)0x00000004) /*!< Protects Sector 226 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227_OFS ( 3) /*!< PROT227 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227 ((uint32_t)0x00000008) /*!< Protects Sector 227 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228_OFS ( 4) /*!< PROT228 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228 ((uint32_t)0x00000010) /*!< Protects Sector 228 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229_OFS ( 5) /*!< PROT229 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229 ((uint32_t)0x00000020) /*!< Protects Sector 229 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230_OFS ( 6) /*!< PROT230 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230 ((uint32_t)0x00000040) /*!< Protects Sector 230 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231_OFS ( 7) /*!< PROT231 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231 ((uint32_t)0x00000080) /*!< Protects Sector 231 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232_OFS ( 8) /*!< PROT232 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232 ((uint32_t)0x00000100) /*!< Protects Sector 232 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233_OFS ( 9) /*!< PROT233 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233 ((uint32_t)0x00000200) /*!< Protects Sector 233 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234_OFS (10) /*!< PROT234 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234 ((uint32_t)0x00000400) /*!< Protects Sector 234 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235_OFS (11) /*!< PROT235 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235 ((uint32_t)0x00000800) /*!< Protects Sector 235 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236_OFS (12) /*!< PROT236 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236 ((uint32_t)0x00001000) /*!< Protects Sector 236 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237_OFS (13) /*!< PROT237 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237 ((uint32_t)0x00002000) /*!< Protects Sector 237 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238_OFS (14) /*!< PROT238 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238 ((uint32_t)0x00004000) /*!< Protects Sector 238 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239_OFS (15) /*!< PROT239 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239 ((uint32_t)0x00008000) /*!< Protects Sector 239 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240_OFS (16) /*!< PROT240 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240 ((uint32_t)0x00010000) /*!< Protects Sector 240 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241_OFS (17) /*!< PROT241 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241 ((uint32_t)0x00020000) /*!< Protects Sector 241 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242_OFS (18) /*!< PROT242 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242 ((uint32_t)0x00040000) /*!< Protects Sector 242 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243_OFS (19) /*!< PROT243 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243 ((uint32_t)0x00080000) /*!< Protects Sector 243 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244_OFS (20) /*!< PROT244 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244 ((uint32_t)0x00100000) /*!< Protects Sector 244 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245_OFS (21) /*!< PROT245 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245 ((uint32_t)0x00200000) /*!< Protects Sector 245 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246_OFS (22) /*!< PROT246 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246 ((uint32_t)0x00400000) /*!< Protects Sector 246 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247_OFS (23) /*!< PROT247 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247 ((uint32_t)0x00800000) /*!< Protects Sector 247 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248_OFS (24) /*!< PROT248 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248 ((uint32_t)0x01000000) /*!< Protects Sector 248 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249_OFS (25) /*!< PROT249 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249 ((uint32_t)0x02000000) /*!< Protects Sector 249 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250_OFS (26) /*!< PROT250 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250 ((uint32_t)0x04000000) /*!< Protects Sector 250 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251_OFS (27) /*!< PROT251 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251 ((uint32_t)0x08000000) /*!< Protects Sector 251 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252_OFS (28) /*!< PROT252 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252 ((uint32_t)0x10000000) /*!< Protects Sector 252 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253_OFS (29) /*!< PROT253 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253 ((uint32_t)0x20000000) /*!< Protects Sector 253 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254_OFS (30) /*!< PROT254 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254 ((uint32_t)0x40000000) /*!< Protects Sector 254 from program or erase */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255_OFS (31) /*!< PROT255 Bit Offset */ -#define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255 ((uint32_t)0x80000000) /*!< Protects Sector 255 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10_OFS (10) /*!< PROT10 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11_OFS (11) /*!< PROT11 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12_OFS (12) /*!< PROT12 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13_OFS (13) /*!< PROT13 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14_OFS (14) /*!< PROT14 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15_OFS (15) /*!< PROT15 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16_OFS (16) /*!< PROT16 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17_OFS (17) /*!< PROT17 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18_OFS (18) /*!< PROT18 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19_OFS (19) /*!< PROT19 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20_OFS (20) /*!< PROT20 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21_OFS (21) /*!< PROT21 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22_OFS (22) /*!< PROT22 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23_OFS (23) /*!< PROT23 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24_OFS (24) /*!< PROT24 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25_OFS (25) /*!< PROT25 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26_OFS (26) /*!< PROT26 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27_OFS (27) /*!< PROT27 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28_OFS (28) /*!< PROT28 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29_OFS (29) /*!< PROT29 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30_OFS (30) /*!< PROT30 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31_OFS (31) /*!< PROT31 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32_OFS ( 0) /*!< PROT32 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32 ((uint32_t)0x00000001) /*!< Protects Sector 32 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33_OFS ( 1) /*!< PROT33 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33 ((uint32_t)0x00000002) /*!< Protects Sector 33 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34_OFS ( 2) /*!< PROT34 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34 ((uint32_t)0x00000004) /*!< Protects Sector 34 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35_OFS ( 3) /*!< PROT35 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35 ((uint32_t)0x00000008) /*!< Protects Sector 35 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36_OFS ( 4) /*!< PROT36 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36 ((uint32_t)0x00000010) /*!< Protects Sector 36 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37_OFS ( 5) /*!< PROT37 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37 ((uint32_t)0x00000020) /*!< Protects Sector 37 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38_OFS ( 6) /*!< PROT38 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38 ((uint32_t)0x00000040) /*!< Protects Sector 38 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39_OFS ( 7) /*!< PROT39 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39 ((uint32_t)0x00000080) /*!< Protects Sector 39 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40_OFS ( 8) /*!< PROT40 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40 ((uint32_t)0x00000100) /*!< Protects Sector 40 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41_OFS ( 9) /*!< PROT41 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41 ((uint32_t)0x00000200) /*!< Protects Sector 41 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42_OFS (10) /*!< PROT42 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42 ((uint32_t)0x00000400) /*!< Protects Sector 42 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43_OFS (11) /*!< PROT43 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43 ((uint32_t)0x00000800) /*!< Protects Sector 43 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44_OFS (12) /*!< PROT44 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44 ((uint32_t)0x00001000) /*!< Protects Sector 44 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45_OFS (13) /*!< PROT45 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45 ((uint32_t)0x00002000) /*!< Protects Sector 45 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46_OFS (14) /*!< PROT46 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46 ((uint32_t)0x00004000) /*!< Protects Sector 46 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47_OFS (15) /*!< PROT47 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47 ((uint32_t)0x00008000) /*!< Protects Sector 47 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48_OFS (16) /*!< PROT48 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48 ((uint32_t)0x00010000) /*!< Protects Sector 48 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49_OFS (17) /*!< PROT49 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49 ((uint32_t)0x00020000) /*!< Protects Sector 49 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50_OFS (18) /*!< PROT50 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50 ((uint32_t)0x00040000) /*!< Protects Sector 50 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51_OFS (19) /*!< PROT51 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51 ((uint32_t)0x00080000) /*!< Protects Sector 51 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52_OFS (20) /*!< PROT52 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52 ((uint32_t)0x00100000) /*!< Protects Sector 52 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53_OFS (21) /*!< PROT53 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53 ((uint32_t)0x00200000) /*!< Protects Sector 53 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54_OFS (22) /*!< PROT54 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54 ((uint32_t)0x00400000) /*!< Protects Sector 54 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55_OFS (23) /*!< PROT55 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55 ((uint32_t)0x00800000) /*!< Protects Sector 55 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56_OFS (24) /*!< PROT56 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56 ((uint32_t)0x01000000) /*!< Protects Sector 56 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57_OFS (25) /*!< PROT57 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57 ((uint32_t)0x02000000) /*!< Protects Sector 57 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58_OFS (26) /*!< PROT58 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58 ((uint32_t)0x04000000) /*!< Protects Sector 58 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59_OFS (27) /*!< PROT59 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59 ((uint32_t)0x08000000) /*!< Protects Sector 59 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60_OFS (28) /*!< PROT60 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60 ((uint32_t)0x10000000) /*!< Protects Sector 60 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61_OFS (29) /*!< PROT61 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61 ((uint32_t)0x20000000) /*!< Protects Sector 61 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62_OFS (30) /*!< PROT62 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62 ((uint32_t)0x40000000) /*!< Protects Sector 62 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63_OFS (31) /*!< PROT63 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63 ((uint32_t)0x80000000) /*!< Protects Sector 63 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64_OFS ( 0) /*!< PROT64 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64 ((uint32_t)0x00000001) /*!< Protects Sector 64 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65_OFS ( 1) /*!< PROT65 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65 ((uint32_t)0x00000002) /*!< Protects Sector 65 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66_OFS ( 2) /*!< PROT66 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66 ((uint32_t)0x00000004) /*!< Protects Sector 66 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67_OFS ( 3) /*!< PROT67 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67 ((uint32_t)0x00000008) /*!< Protects Sector 67 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68_OFS ( 4) /*!< PROT68 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68 ((uint32_t)0x00000010) /*!< Protects Sector 68 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69_OFS ( 5) /*!< PROT69 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69 ((uint32_t)0x00000020) /*!< Protects Sector 69 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70_OFS ( 6) /*!< PROT70 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70 ((uint32_t)0x00000040) /*!< Protects Sector 70 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71_OFS ( 7) /*!< PROT71 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71 ((uint32_t)0x00000080) /*!< Protects Sector 71 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72_OFS ( 8) /*!< PROT72 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72 ((uint32_t)0x00000100) /*!< Protects Sector 72 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73_OFS ( 9) /*!< PROT73 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73 ((uint32_t)0x00000200) /*!< Protects Sector 73 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74_OFS (10) /*!< PROT74 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74 ((uint32_t)0x00000400) /*!< Protects Sector 74 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75_OFS (11) /*!< PROT75 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75 ((uint32_t)0x00000800) /*!< Protects Sector 75 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76_OFS (12) /*!< PROT76 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76 ((uint32_t)0x00001000) /*!< Protects Sector 76 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77_OFS (13) /*!< PROT77 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77 ((uint32_t)0x00002000) /*!< Protects Sector 77 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78_OFS (14) /*!< PROT78 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78 ((uint32_t)0x00004000) /*!< Protects Sector 78 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79_OFS (15) /*!< PROT79 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79 ((uint32_t)0x00008000) /*!< Protects Sector 79 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80_OFS (16) /*!< PROT80 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80 ((uint32_t)0x00010000) /*!< Protects Sector 80 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81_OFS (17) /*!< PROT81 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81 ((uint32_t)0x00020000) /*!< Protects Sector 81 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82_OFS (18) /*!< PROT82 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82 ((uint32_t)0x00040000) /*!< Protects Sector 82 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83_OFS (19) /*!< PROT83 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83 ((uint32_t)0x00080000) /*!< Protects Sector 83 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84_OFS (20) /*!< PROT84 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84 ((uint32_t)0x00100000) /*!< Protects Sector 84 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85_OFS (21) /*!< PROT85 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85 ((uint32_t)0x00200000) /*!< Protects Sector 85 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86_OFS (22) /*!< PROT86 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86 ((uint32_t)0x00400000) /*!< Protects Sector 86 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87_OFS (23) /*!< PROT87 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87 ((uint32_t)0x00800000) /*!< Protects Sector 87 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88_OFS (24) /*!< PROT88 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88 ((uint32_t)0x01000000) /*!< Protects Sector 88 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89_OFS (25) /*!< PROT89 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89 ((uint32_t)0x02000000) /*!< Protects Sector 89 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90_OFS (26) /*!< PROT90 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90 ((uint32_t)0x04000000) /*!< Protects Sector 90 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91_OFS (27) /*!< PROT91 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91 ((uint32_t)0x08000000) /*!< Protects Sector 91 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92_OFS (28) /*!< PROT92 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92 ((uint32_t)0x10000000) /*!< Protects Sector 92 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93_OFS (29) /*!< PROT93 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93 ((uint32_t)0x20000000) /*!< Protects Sector 93 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94_OFS (30) /*!< PROT94 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94 ((uint32_t)0x40000000) /*!< Protects Sector 94 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95_OFS (31) /*!< PROT95 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95 ((uint32_t)0x80000000) /*!< Protects Sector 95 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96_OFS ( 0) /*!< PROT96 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96 ((uint32_t)0x00000001) /*!< Protects Sector 96 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97_OFS ( 1) /*!< PROT97 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97 ((uint32_t)0x00000002) /*!< Protects Sector 97 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98_OFS ( 2) /*!< PROT98 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98 ((uint32_t)0x00000004) /*!< Protects Sector 98 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99_OFS ( 3) /*!< PROT99 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99 ((uint32_t)0x00000008) /*!< Protects Sector 99 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100_OFS ( 4) /*!< PROT100 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100 ((uint32_t)0x00000010) /*!< Protects Sector 100 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101_OFS ( 5) /*!< PROT101 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101 ((uint32_t)0x00000020) /*!< Protects Sector 101 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102_OFS ( 6) /*!< PROT102 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102 ((uint32_t)0x00000040) /*!< Protects Sector 102 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103_OFS ( 7) /*!< PROT103 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103 ((uint32_t)0x00000080) /*!< Protects Sector 103 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104_OFS ( 8) /*!< PROT104 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104 ((uint32_t)0x00000100) /*!< Protects Sector 104 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105_OFS ( 9) /*!< PROT105 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105 ((uint32_t)0x00000200) /*!< Protects Sector 105 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106_OFS (10) /*!< PROT106 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106 ((uint32_t)0x00000400) /*!< Protects Sector 106 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107_OFS (11) /*!< PROT107 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107 ((uint32_t)0x00000800) /*!< Protects Sector 107 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108_OFS (12) /*!< PROT108 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108 ((uint32_t)0x00001000) /*!< Protects Sector 108 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109_OFS (13) /*!< PROT109 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109 ((uint32_t)0x00002000) /*!< Protects Sector 109 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110_OFS (14) /*!< PROT110 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110 ((uint32_t)0x00004000) /*!< Protects Sector 110 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111_OFS (15) /*!< PROT111 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111 ((uint32_t)0x00008000) /*!< Protects Sector 111 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112_OFS (16) /*!< PROT112 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112 ((uint32_t)0x00010000) /*!< Protects Sector 112 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113_OFS (17) /*!< PROT113 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113 ((uint32_t)0x00020000) /*!< Protects Sector 113 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114_OFS (18) /*!< PROT114 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114 ((uint32_t)0x00040000) /*!< Protects Sector 114 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115_OFS (19) /*!< PROT115 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115 ((uint32_t)0x00080000) /*!< Protects Sector 115 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116_OFS (20) /*!< PROT116 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116 ((uint32_t)0x00100000) /*!< Protects Sector 116 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117_OFS (21) /*!< PROT117 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117 ((uint32_t)0x00200000) /*!< Protects Sector 117 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118_OFS (22) /*!< PROT118 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118 ((uint32_t)0x00400000) /*!< Protects Sector 118 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119_OFS (23) /*!< PROT119 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119 ((uint32_t)0x00800000) /*!< Protects Sector 119 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120_OFS (24) /*!< PROT120 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120 ((uint32_t)0x01000000) /*!< Protects Sector 120 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121_OFS (25) /*!< PROT121 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121 ((uint32_t)0x02000000) /*!< Protects Sector 121 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122_OFS (26) /*!< PROT122 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122 ((uint32_t)0x04000000) /*!< Protects Sector 122 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123_OFS (27) /*!< PROT123 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123 ((uint32_t)0x08000000) /*!< Protects Sector 123 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124_OFS (28) /*!< PROT124 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124 ((uint32_t)0x10000000) /*!< Protects Sector 124 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125_OFS (29) /*!< PROT125 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125 ((uint32_t)0x20000000) /*!< Protects Sector 125 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126_OFS (30) /*!< PROT126 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126 ((uint32_t)0x40000000) /*!< Protects Sector 126 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127_OFS (31) /*!< PROT127 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127 ((uint32_t)0x80000000) /*!< Protects Sector 127 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128_OFS ( 0) /*!< PROT128 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128 ((uint32_t)0x00000001) /*!< Protects Sector 128 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129_OFS ( 1) /*!< PROT129 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129 ((uint32_t)0x00000002) /*!< Protects Sector 129 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130_OFS ( 2) /*!< PROT130 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130 ((uint32_t)0x00000004) /*!< Protects Sector 130 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131_OFS ( 3) /*!< PROT131 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131 ((uint32_t)0x00000008) /*!< Protects Sector 131 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132_OFS ( 4) /*!< PROT132 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132 ((uint32_t)0x00000010) /*!< Protects Sector 132 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133_OFS ( 5) /*!< PROT133 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133 ((uint32_t)0x00000020) /*!< Protects Sector 133 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134_OFS ( 6) /*!< PROT134 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134 ((uint32_t)0x00000040) /*!< Protects Sector 134 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135_OFS ( 7) /*!< PROT135 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135 ((uint32_t)0x00000080) /*!< Protects Sector 135 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136_OFS ( 8) /*!< PROT136 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136 ((uint32_t)0x00000100) /*!< Protects Sector 136 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137_OFS ( 9) /*!< PROT137 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137 ((uint32_t)0x00000200) /*!< Protects Sector 137 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138_OFS (10) /*!< PROT138 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138 ((uint32_t)0x00000400) /*!< Protects Sector 138 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139_OFS (11) /*!< PROT139 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139 ((uint32_t)0x00000800) /*!< Protects Sector 139 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140_OFS (12) /*!< PROT140 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140 ((uint32_t)0x00001000) /*!< Protects Sector 140 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141_OFS (13) /*!< PROT141 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141 ((uint32_t)0x00002000) /*!< Protects Sector 141 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142_OFS (14) /*!< PROT142 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142 ((uint32_t)0x00004000) /*!< Protects Sector 142 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143_OFS (15) /*!< PROT143 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143 ((uint32_t)0x00008000) /*!< Protects Sector 143 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144_OFS (16) /*!< PROT144 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144 ((uint32_t)0x00010000) /*!< Protects Sector 144 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145_OFS (17) /*!< PROT145 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145 ((uint32_t)0x00020000) /*!< Protects Sector 145 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146_OFS (18) /*!< PROT146 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146 ((uint32_t)0x00040000) /*!< Protects Sector 146 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147_OFS (19) /*!< PROT147 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147 ((uint32_t)0x00080000) /*!< Protects Sector 147 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148_OFS (20) /*!< PROT148 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148 ((uint32_t)0x00100000) /*!< Protects Sector 148 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149_OFS (21) /*!< PROT149 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149 ((uint32_t)0x00200000) /*!< Protects Sector 149 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150_OFS (22) /*!< PROT150 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150 ((uint32_t)0x00400000) /*!< Protects Sector 150 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151_OFS (23) /*!< PROT151 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151 ((uint32_t)0x00800000) /*!< Protects Sector 151 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152_OFS (24) /*!< PROT152 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152 ((uint32_t)0x01000000) /*!< Protects Sector 152 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153_OFS (25) /*!< PROT153 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153 ((uint32_t)0x02000000) /*!< Protects Sector 153 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154_OFS (26) /*!< PROT154 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154 ((uint32_t)0x04000000) /*!< Protects Sector 154 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155_OFS (27) /*!< PROT155 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155 ((uint32_t)0x08000000) /*!< Protects Sector 155 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156_OFS (28) /*!< PROT156 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156 ((uint32_t)0x10000000) /*!< Protects Sector 156 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157_OFS (29) /*!< PROT157 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157 ((uint32_t)0x20000000) /*!< Protects Sector 157 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158_OFS (30) /*!< PROT158 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158 ((uint32_t)0x40000000) /*!< Protects Sector 158 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159_OFS (31) /*!< PROT159 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159 ((uint32_t)0x80000000) /*!< Protects Sector 159 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160_OFS ( 0) /*!< PROT160 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160 ((uint32_t)0x00000001) /*!< Protects Sector 160 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161_OFS ( 1) /*!< PROT161 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161 ((uint32_t)0x00000002) /*!< Protects Sector 161 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162_OFS ( 2) /*!< PROT162 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162 ((uint32_t)0x00000004) /*!< Protects Sector 162 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163_OFS ( 3) /*!< PROT163 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163 ((uint32_t)0x00000008) /*!< Protects Sector 163 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164_OFS ( 4) /*!< PROT164 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164 ((uint32_t)0x00000010) /*!< Protects Sector 164 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165_OFS ( 5) /*!< PROT165 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165 ((uint32_t)0x00000020) /*!< Protects Sector 165 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166_OFS ( 6) /*!< PROT166 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166 ((uint32_t)0x00000040) /*!< Protects Sector 166 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167_OFS ( 7) /*!< PROT167 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167 ((uint32_t)0x00000080) /*!< Protects Sector 167 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168_OFS ( 8) /*!< PROT168 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168 ((uint32_t)0x00000100) /*!< Protects Sector 168 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169_OFS ( 9) /*!< PROT169 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169 ((uint32_t)0x00000200) /*!< Protects Sector 169 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170_OFS (10) /*!< PROT170 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170 ((uint32_t)0x00000400) /*!< Protects Sector 170 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171_OFS (11) /*!< PROT171 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171 ((uint32_t)0x00000800) /*!< Protects Sector 171 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172_OFS (12) /*!< PROT172 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172 ((uint32_t)0x00001000) /*!< Protects Sector 172 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173_OFS (13) /*!< PROT173 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173 ((uint32_t)0x00002000) /*!< Protects Sector 173 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174_OFS (14) /*!< PROT174 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174 ((uint32_t)0x00004000) /*!< Protects Sector 174 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175_OFS (15) /*!< PROT175 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175 ((uint32_t)0x00008000) /*!< Protects Sector 175 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176_OFS (16) /*!< PROT176 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176 ((uint32_t)0x00010000) /*!< Protects Sector 176 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177_OFS (17) /*!< PROT177 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177 ((uint32_t)0x00020000) /*!< Protects Sector 177 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178_OFS (18) /*!< PROT178 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178 ((uint32_t)0x00040000) /*!< Protects Sector 178 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179_OFS (19) /*!< PROT179 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179 ((uint32_t)0x00080000) /*!< Protects Sector 179 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180_OFS (20) /*!< PROT180 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180 ((uint32_t)0x00100000) /*!< Protects Sector 180 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181_OFS (21) /*!< PROT181 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181 ((uint32_t)0x00200000) /*!< Protects Sector 181 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182_OFS (22) /*!< PROT182 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182 ((uint32_t)0x00400000) /*!< Protects Sector 182 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183_OFS (23) /*!< PROT183 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183 ((uint32_t)0x00800000) /*!< Protects Sector 183 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184_OFS (24) /*!< PROT184 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184 ((uint32_t)0x01000000) /*!< Protects Sector 184 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185_OFS (25) /*!< PROT185 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185 ((uint32_t)0x02000000) /*!< Protects Sector 185 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186_OFS (26) /*!< PROT186 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186 ((uint32_t)0x04000000) /*!< Protects Sector 186 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187_OFS (27) /*!< PROT187 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187 ((uint32_t)0x08000000) /*!< Protects Sector 187 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188_OFS (28) /*!< PROT188 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188 ((uint32_t)0x10000000) /*!< Protects Sector 188 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189_OFS (29) /*!< PROT189 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189 ((uint32_t)0x20000000) /*!< Protects Sector 189 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190_OFS (30) /*!< PROT190 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190 ((uint32_t)0x40000000) /*!< Protects Sector 190 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191_OFS (31) /*!< PROT191 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191 ((uint32_t)0x80000000) /*!< Protects Sector 191 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192_OFS ( 0) /*!< PROT192 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192 ((uint32_t)0x00000001) /*!< Protects Sector 192 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193_OFS ( 1) /*!< PROT193 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193 ((uint32_t)0x00000002) /*!< Protects Sector 193 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194_OFS ( 2) /*!< PROT194 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194 ((uint32_t)0x00000004) /*!< Protects Sector 194 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195_OFS ( 3) /*!< PROT195 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195 ((uint32_t)0x00000008) /*!< Protects Sector 195 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196_OFS ( 4) /*!< PROT196 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196 ((uint32_t)0x00000010) /*!< Protects Sector 196 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197_OFS ( 5) /*!< PROT197 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197 ((uint32_t)0x00000020) /*!< Protects Sector 197 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198_OFS ( 6) /*!< PROT198 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198 ((uint32_t)0x00000040) /*!< Protects Sector 198 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199_OFS ( 7) /*!< PROT199 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199 ((uint32_t)0x00000080) /*!< Protects Sector 199 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200_OFS ( 8) /*!< PROT200 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200 ((uint32_t)0x00000100) /*!< Protects Sector 200 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201_OFS ( 9) /*!< PROT201 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201 ((uint32_t)0x00000200) /*!< Protects Sector 201 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202_OFS (10) /*!< PROT202 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202 ((uint32_t)0x00000400) /*!< Protects Sector 202 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203_OFS (11) /*!< PROT203 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203 ((uint32_t)0x00000800) /*!< Protects Sector 203 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204_OFS (12) /*!< PROT204 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204 ((uint32_t)0x00001000) /*!< Protects Sector 204 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205_OFS (13) /*!< PROT205 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205 ((uint32_t)0x00002000) /*!< Protects Sector 205 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206_OFS (14) /*!< PROT206 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206 ((uint32_t)0x00004000) /*!< Protects Sector 206 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207_OFS (15) /*!< PROT207 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207 ((uint32_t)0x00008000) /*!< Protects Sector 207 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208_OFS (16) /*!< PROT208 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208 ((uint32_t)0x00010000) /*!< Protects Sector 208 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209_OFS (17) /*!< PROT209 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209 ((uint32_t)0x00020000) /*!< Protects Sector 209 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210_OFS (18) /*!< PROT210 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210 ((uint32_t)0x00040000) /*!< Protects Sector 210 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211_OFS (19) /*!< PROT211 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211 ((uint32_t)0x00080000) /*!< Protects Sector 211 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212_OFS (20) /*!< PROT212 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212 ((uint32_t)0x00100000) /*!< Protects Sector 212 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213_OFS (21) /*!< PROT213 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213 ((uint32_t)0x00200000) /*!< Protects Sector 213 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214_OFS (22) /*!< PROT214 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214 ((uint32_t)0x00400000) /*!< Protects Sector 214 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215_OFS (23) /*!< PROT215 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215 ((uint32_t)0x00800000) /*!< Protects Sector 215 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216_OFS (24) /*!< PROT216 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216 ((uint32_t)0x01000000) /*!< Protects Sector 216 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217_OFS (25) /*!< PROT217 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217 ((uint32_t)0x02000000) /*!< Protects Sector 217 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218_OFS (26) /*!< PROT218 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218 ((uint32_t)0x04000000) /*!< Protects Sector 218 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219_OFS (27) /*!< PROT219 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219 ((uint32_t)0x08000000) /*!< Protects Sector 219 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220_OFS (28) /*!< PROT220 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220 ((uint32_t)0x10000000) /*!< Protects Sector 220 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221_OFS (29) /*!< PROT221 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221 ((uint32_t)0x20000000) /*!< Protects Sector 221 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222_OFS (30) /*!< PROT222 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222 ((uint32_t)0x40000000) /*!< Protects Sector 222 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223_OFS (31) /*!< PROT223 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223 ((uint32_t)0x80000000) /*!< Protects Sector 223 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224_OFS ( 0) /*!< PROT224 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224 ((uint32_t)0x00000001) /*!< Protects Sector 224 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225_OFS ( 1) /*!< PROT225 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225 ((uint32_t)0x00000002) /*!< Protects Sector 225 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226_OFS ( 2) /*!< PROT226 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226 ((uint32_t)0x00000004) /*!< Protects Sector 226 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227_OFS ( 3) /*!< PROT227 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227 ((uint32_t)0x00000008) /*!< Protects Sector 227 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228_OFS ( 4) /*!< PROT228 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228 ((uint32_t)0x00000010) /*!< Protects Sector 228 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229_OFS ( 5) /*!< PROT229 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229 ((uint32_t)0x00000020) /*!< Protects Sector 229 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230_OFS ( 6) /*!< PROT230 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230 ((uint32_t)0x00000040) /*!< Protects Sector 230 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231_OFS ( 7) /*!< PROT231 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231 ((uint32_t)0x00000080) /*!< Protects Sector 231 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232_OFS ( 8) /*!< PROT232 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232 ((uint32_t)0x00000100) /*!< Protects Sector 232 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233_OFS ( 9) /*!< PROT233 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233 ((uint32_t)0x00000200) /*!< Protects Sector 233 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234_OFS (10) /*!< PROT234 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234 ((uint32_t)0x00000400) /*!< Protects Sector 234 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235_OFS (11) /*!< PROT235 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235 ((uint32_t)0x00000800) /*!< Protects Sector 235 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236_OFS (12) /*!< PROT236 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236 ((uint32_t)0x00001000) /*!< Protects Sector 236 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237_OFS (13) /*!< PROT237 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237 ((uint32_t)0x00002000) /*!< Protects Sector 237 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238_OFS (14) /*!< PROT238 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238 ((uint32_t)0x00004000) /*!< Protects Sector 238 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239_OFS (15) /*!< PROT239 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239 ((uint32_t)0x00008000) /*!< Protects Sector 239 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240_OFS (16) /*!< PROT240 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240 ((uint32_t)0x00010000) /*!< Protects Sector 240 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241_OFS (17) /*!< PROT241 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241 ((uint32_t)0x00020000) /*!< Protects Sector 241 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242_OFS (18) /*!< PROT242 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242 ((uint32_t)0x00040000) /*!< Protects Sector 242 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243_OFS (19) /*!< PROT243 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243 ((uint32_t)0x00080000) /*!< Protects Sector 243 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244_OFS (20) /*!< PROT244 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244 ((uint32_t)0x00100000) /*!< Protects Sector 244 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245_OFS (21) /*!< PROT245 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245 ((uint32_t)0x00200000) /*!< Protects Sector 245 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246_OFS (22) /*!< PROT246 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246 ((uint32_t)0x00400000) /*!< Protects Sector 246 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247_OFS (23) /*!< PROT247 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247 ((uint32_t)0x00800000) /*!< Protects Sector 247 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248_OFS (24) /*!< PROT248 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248 ((uint32_t)0x01000000) /*!< Protects Sector 248 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249_OFS (25) /*!< PROT249 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249 ((uint32_t)0x02000000) /*!< Protects Sector 249 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250_OFS (26) /*!< PROT250 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250 ((uint32_t)0x04000000) /*!< Protects Sector 250 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251_OFS (27) /*!< PROT251 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251 ((uint32_t)0x08000000) /*!< Protects Sector 251 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252_OFS (28) /*!< PROT252 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252 ((uint32_t)0x10000000) /*!< Protects Sector 252 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253_OFS (29) /*!< PROT253 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253 ((uint32_t)0x20000000) /*!< Protects Sector 253 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254_OFS (30) /*!< PROT254 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254 ((uint32_t)0x40000000) /*!< Protects Sector 254 from program or erase */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255_OFS (31) /*!< PROT255 Bit Offset */ -#define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255 ((uint32_t)0x80000000) /*!< Protects Sector 255 from program or erase */ -#define LCD_F_CTL_ON_OFS ( 0) /*!< LCDON Bit Offset */ -#define LCD_F_CTL_ON ((uint32_t)0x00000001) /*!< LCD on */ -#define LCD_F_CTL_LP_OFS ( 1) /*!< LCDLP Bit Offset */ -#define LCD_F_CTL_LP ((uint32_t)0x00000002) /*!< LCD Low-power Waveform */ -#define LCD_F_CTL_SON_OFS ( 2) /*!< LCDSON Bit Offset */ -#define LCD_F_CTL_SON ((uint32_t)0x00000004) /*!< LCD segments on */ -#define LCD_F_CTL_MX_OFS ( 3) /*!< LCDMXx Bit Offset */ -#define LCD_F_CTL_MX_MASK ((uint32_t)0x00000038) /*!< LCDMXx Bit Mask */ -#define LCD_F_CTL_MX0 ((uint32_t)0x00000008) /*!< MX Bit 0 */ -#define LCD_F_CTL_MX1 ((uint32_t)0x00000010) /*!< MX Bit 1 */ -#define LCD_F_CTL_MX2 ((uint32_t)0x00000020) /*!< MX Bit 2 */ -#define LCD_F_CTL_MX_0 ((uint32_t)0x00000000) /*!< Static */ -#define LCD_F_CTL_MX_1 ((uint32_t)0x00000008) /*!< 2-mux */ -#define LCD_F_CTL_MX_2 ((uint32_t)0x00000010) /*!< 3-mux */ -#define LCD_F_CTL_MX_3 ((uint32_t)0x00000018) /*!< 4-mux */ -#define LCD_F_CTL_MX_4 ((uint32_t)0x00000020) /*!< 5-mux */ -#define LCD_F_CTL_MX_5 ((uint32_t)0x00000028) /*!< 6-mux */ -#define LCD_F_CTL_MX_6 ((uint32_t)0x00000030) /*!< 7-mux */ -#define LCD_F_CTL_MX_7 ((uint32_t)0x00000038) /*!< 8-mux */ -#define LCD_F_CTL_PRE_OFS ( 8) /*!< LCDPREx Bit Offset */ -#define LCD_F_CTL_PRE_MASK ((uint32_t)0x00000700) /*!< LCDPREx Bit Mask */ -#define LCD_F_CTL_PRE0 ((uint32_t)0x00000100) /*!< PRE Bit 0 */ -#define LCD_F_CTL_PRE1 ((uint32_t)0x00000200) /*!< PRE Bit 1 */ -#define LCD_F_CTL_PRE2 ((uint32_t)0x00000400) /*!< PRE Bit 2 */ -#define LCD_F_CTL_PRE_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_CTL_PRE_1 ((uint32_t)0x00000100) /*!< Divide by 2 */ -#define LCD_F_CTL_PRE_2 ((uint32_t)0x00000200) /*!< Divide by 4 */ -#define LCD_F_CTL_PRE_3 ((uint32_t)0x00000300) /*!< Divide by 8 */ -#define LCD_F_CTL_PRE_4 ((uint32_t)0x00000400) /*!< Divide by 16 */ -#define LCD_F_CTL_PRE_5 ((uint32_t)0x00000500) /*!< Divide by 32 */ -#define LCD_F_CTL_PRE_6 ((uint32_t)0x00000600) /*!< Reserved (defaults to divide by 32) */ -#define LCD_F_CTL_PRE_7 ((uint32_t)0x00000700) /*!< Reserved (defaults to divide by 32) */ -#define LCD_F_CTL_DIV_OFS (11) /*!< LCDDIVx Bit Offset */ -#define LCD_F_CTL_DIV_MASK ((uint32_t)0x0000F800) /*!< LCDDIVx Bit Mask */ -#define LCD_F_CTL_DIV0 ((uint32_t)0x00000800) /*!< DIV Bit 0 */ -#define LCD_F_CTL_DIV1 ((uint32_t)0x00001000) /*!< DIV Bit 1 */ -#define LCD_F_CTL_DIV2 ((uint32_t)0x00002000) /*!< DIV Bit 2 */ -#define LCD_F_CTL_DIV3 ((uint32_t)0x00004000) /*!< DIV Bit 3 */ -#define LCD_F_CTL_DIV4 ((uint32_t)0x00008000) /*!< DIV Bit 4 */ -#define LCD_F_CTL_DIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_CTL_DIV_1 ((uint32_t)0x00000800) /*!< Divide by 2 */ -#define LCD_F_CTL_DIV_2 ((uint32_t)0x00001000) /*!< Divide by 3 */ -#define LCD_F_CTL_DIV_3 ((uint32_t)0x00001800) /*!< Divide by 4 */ -#define LCD_F_CTL_DIV_4 ((uint32_t)0x00002000) /*!< Divide by 5 */ -#define LCD_F_CTL_DIV_5 ((uint32_t)0x00002800) /*!< Divide by 6 */ -#define LCD_F_CTL_DIV_6 ((uint32_t)0x00003000) /*!< Divide by 7 */ -#define LCD_F_CTL_DIV_7 ((uint32_t)0x00003800) /*!< Divide by 8 */ -#define LCD_F_CTL_DIV_8 ((uint32_t)0x00004000) /*!< Divide by 9 */ -#define LCD_F_CTL_DIV_9 ((uint32_t)0x00004800) /*!< Divide by 10 */ -#define LCD_F_CTL_DIV_10 ((uint32_t)0x00005000) /*!< Divide by 11 */ -#define LCD_F_CTL_DIV_11 ((uint32_t)0x00005800) /*!< Divide by 12 */ -#define LCD_F_CTL_DIV_12 ((uint32_t)0x00006000) /*!< Divide by 13 */ -#define LCD_F_CTL_DIV_13 ((uint32_t)0x00006800) /*!< Divide by 14 */ -#define LCD_F_CTL_DIV_14 ((uint32_t)0x00007000) /*!< Divide by 15 */ -#define LCD_F_CTL_DIV_15 ((uint32_t)0x00007800) /*!< Divide by 16 */ -#define LCD_F_CTL_DIV_16 ((uint32_t)0x00008000) /*!< Divide by 17 */ -#define LCD_F_CTL_DIV_17 ((uint32_t)0x00008800) /*!< Divide by 18 */ -#define LCD_F_CTL_DIV_18 ((uint32_t)0x00009000) /*!< Divide by 19 */ -#define LCD_F_CTL_DIV_19 ((uint32_t)0x00009800) /*!< Divide by 20 */ -#define LCD_F_CTL_DIV_20 ((uint32_t)0x0000A000) /*!< Divide by 21 */ -#define LCD_F_CTL_DIV_21 ((uint32_t)0x0000A800) /*!< Divide by 22 */ -#define LCD_F_CTL_DIV_22 ((uint32_t)0x0000B000) /*!< Divide by 23 */ -#define LCD_F_CTL_DIV_23 ((uint32_t)0x0000B800) /*!< Divide by 24 */ -#define LCD_F_CTL_DIV_24 ((uint32_t)0x0000C000) /*!< Divide by 25 */ -#define LCD_F_CTL_DIV_25 ((uint32_t)0x0000C800) /*!< Divide by 26 */ -#define LCD_F_CTL_DIV_26 ((uint32_t)0x0000D000) /*!< Divide by 27 */ -#define LCD_F_CTL_DIV_27 ((uint32_t)0x0000D800) /*!< Divide by 28 */ -#define LCD_F_CTL_DIV_28 ((uint32_t)0x0000E000) /*!< Divide by 29 */ -#define LCD_F_CTL_DIV_29 ((uint32_t)0x0000E800) /*!< Divide by 30 */ -#define LCD_F_CTL_DIV_30 ((uint32_t)0x0000F000) /*!< Divide by 31 */ -#define LCD_F_CTL_DIV_31 ((uint32_t)0x0000F800) /*!< Divide by 32 */ -#define LCD_F_CTL_SSEL_OFS (16) /*!< LCDSSEL Bit Offset */ -#define LCD_F_CTL_SSEL_MASK ((uint32_t)0x00030000) /*!< LCDSSEL Bit Mask */ -#define LCD_F_CTL_SSEL0 ((uint32_t)0x00010000) /*!< SSEL Bit 0 */ -#define LCD_F_CTL_SSEL1 ((uint32_t)0x00020000) /*!< SSEL Bit 1 */ -#define LCD_F_CTL_SSEL_0 ((uint32_t)0x00000000) /*!< ACLK */ -#define LCD_F_CTL_SSEL_1 ((uint32_t)0x00010000) /*!< VLOCLK */ -#define LCD_F_CTL_SSEL_2 ((uint32_t)0x00020000) /*!< REFOCLK */ -#define LCD_F_CTL_SSEL_3 ((uint32_t)0x00030000) /*!< LFXTCLK */ -#define LCD_F_BMCTL_BLKMOD_OFS ( 0) /*!< LCDBLKMODx Bit Offset */ -#define LCD_F_BMCTL_BLKMOD_MASK ((uint32_t)0x00000003) /*!< LCDBLKMODx Bit Mask */ -#define LCD_F_BMCTL_BLKMOD0 ((uint32_t)0x00000001) /*!< BLKMOD Bit 0 */ -#define LCD_F_BMCTL_BLKMOD1 ((uint32_t)0x00000002) /*!< BLKMOD Bit 1 */ -#define LCD_F_BMCTL_BLKMOD_0 ((uint32_t)0x00000000) /*!< Blinking disabled */ -#define LCD_F_BMCTL_BLKMOD_1 ((uint32_t)0x00000001) /*!< Blinking of individual segments as enabled in blinking memory register */ -#define LCD_F_BMCTL_BLKMOD_2 ((uint32_t)0x00000002) /*!< Blinking of all segments */ -#define LCD_F_BMCTL_BLKMOD_3 ((uint32_t)0x00000003) /*!< Switching between display contents as stored in LCDMx and LCDBMx memory */ -#define LCD_F_BMCTL_BLKPRE_OFS ( 2) /*!< LCDBLKPREx Bit Offset */ -#define LCD_F_BMCTL_BLKPRE_MASK ((uint32_t)0x0000001C) /*!< LCDBLKPREx Bit Mask */ -#define LCD_F_BMCTL_BLKPRE0 ((uint32_t)0x00000004) /*!< BLKPRE Bit 0 */ -#define LCD_F_BMCTL_BLKPRE1 ((uint32_t)0x00000008) /*!< BLKPRE Bit 1 */ -#define LCD_F_BMCTL_BLKPRE2 ((uint32_t)0x00000010) /*!< BLKPRE Bit 2 */ -#define LCD_F_BMCTL_BLKPRE_0 ((uint32_t)0x00000000) /*!< Divide by 512 */ -#define LCD_F_BMCTL_BLKPRE_1 ((uint32_t)0x00000004) /*!< Divide by 1024 */ -#define LCD_F_BMCTL_BLKPRE_2 ((uint32_t)0x00000008) /*!< Divide by 2048 */ -#define LCD_F_BMCTL_BLKPRE_3 ((uint32_t)0x0000000C) /*!< Divide by 4096 */ -#define LCD_F_BMCTL_BLKPRE_4 ((uint32_t)0x00000010) /*!< Divide by 8162 */ -#define LCD_F_BMCTL_BLKPRE_5 ((uint32_t)0x00000014) /*!< Divide by 16384 */ -#define LCD_F_BMCTL_BLKPRE_6 ((uint32_t)0x00000018) /*!< Divide by 32768 */ -#define LCD_F_BMCTL_BLKPRE_7 ((uint32_t)0x0000001C) /*!< Divide by 65536 */ -#define LCD_F_BMCTL_BLKDIV_OFS ( 5) /*!< LCDBLKDIVx Bit Offset */ -#define LCD_F_BMCTL_BLKDIV_MASK ((uint32_t)0x000000E0) /*!< LCDBLKDIVx Bit Mask */ -#define LCD_F_BMCTL_BLKDIV0 ((uint32_t)0x00000020) /*!< BLKDIV Bit 0 */ -#define LCD_F_BMCTL_BLKDIV1 ((uint32_t)0x00000040) /*!< BLKDIV Bit 1 */ -#define LCD_F_BMCTL_BLKDIV2 ((uint32_t)0x00000080) /*!< BLKDIV Bit 2 */ -#define LCD_F_BMCTL_BLKDIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_BMCTL_BLKDIV_1 ((uint32_t)0x00000020) /*!< Divide by 2 */ -#define LCD_F_BMCTL_BLKDIV_2 ((uint32_t)0x00000040) /*!< Divide by 3 */ -#define LCD_F_BMCTL_BLKDIV_3 ((uint32_t)0x00000060) /*!< Divide by 4 */ -#define LCD_F_BMCTL_BLKDIV_4 ((uint32_t)0x00000080) /*!< Divide by 5 */ -#define LCD_F_BMCTL_BLKDIV_5 ((uint32_t)0x000000A0) /*!< Divide by 6 */ -#define LCD_F_BMCTL_BLKDIV_6 ((uint32_t)0x000000C0) /*!< Divide by 7 */ -#define LCD_F_BMCTL_BLKDIV_7 ((uint32_t)0x000000E0) /*!< Divide by 8 */ -#define LCD_F_BMCTL_DISP_OFS (16) /*!< LCDDISP Bit Offset */ -#define LCD_F_BMCTL_DISP ((uint32_t)0x00010000) /*!< Select LCD memory registers for display */ -#define LCD_F_BMCTL_CLRM_OFS (17) /*!< LCDCLRM Bit Offset */ -#define LCD_F_BMCTL_CLRM ((uint32_t)0x00020000) /*!< Clear LCD memory */ -#define LCD_F_BMCTL_CLRBM_OFS (18) /*!< LCDCLRBM Bit Offset */ -#define LCD_F_BMCTL_CLRBM ((uint32_t)0x00040000) /*!< Clear LCD blinking memory */ -#define LCD_F_VCTL_LCD2B_OFS ( 0) /*!< LCD2B Bit Offset */ -#define LCD_F_VCTL_LCD2B ((uint32_t)0x00000001) /*!< Bias select. */ -#define LCD_F_VCTL_EXTBIAS_OFS ( 5) /*!< LCDEXTBIAS Bit Offset */ -#define LCD_F_VCTL_EXTBIAS ((uint32_t)0x00000020) /*!< V2 to V4 voltage select */ -#define LCD_F_VCTL_R03EXT_OFS ( 6) /*!< R03EXT Bit Offset */ -#define LCD_F_VCTL_R03EXT ((uint32_t)0x00000040) /*!< V5 voltage select */ -#define LCD_F_VCTL_REXT_OFS ( 7) /*!< LCDREXT Bit Offset */ -#define LCD_F_VCTL_REXT ((uint32_t)0x00000080) /*!< V2 to V4 voltage on external Rx3 pins */ -#define LCD_F_PCTL0_S0_OFS ( 0) /*!< LCDS0 Bit Offset */ -#define LCD_F_PCTL0_S0 ((uint32_t)0x00000001) /*!< LCD pin 0 enable */ -#define LCD_F_PCTL0_S1_OFS ( 1) /*!< LCDS1 Bit Offset */ -#define LCD_F_PCTL0_S1 ((uint32_t)0x00000002) /*!< LCD pin 1 enable */ -#define LCD_F_PCTL0_S2_OFS ( 2) /*!< LCDS2 Bit Offset */ -#define LCD_F_PCTL0_S2 ((uint32_t)0x00000004) /*!< LCD pin 2 enable */ -#define LCD_F_PCTL0_S3_OFS ( 3) /*!< LCDS3 Bit Offset */ -#define LCD_F_PCTL0_S3 ((uint32_t)0x00000008) /*!< LCD pin 3 enable */ -#define LCD_F_PCTL0_S4_OFS ( 4) /*!< LCDS4 Bit Offset */ -#define LCD_F_PCTL0_S4 ((uint32_t)0x00000010) /*!< LCD pin 4 enable */ -#define LCD_F_PCTL0_S5_OFS ( 5) /*!< LCDS5 Bit Offset */ -#define LCD_F_PCTL0_S5 ((uint32_t)0x00000020) /*!< LCD pin 5 enable */ -#define LCD_F_PCTL0_S6_OFS ( 6) /*!< LCDS6 Bit Offset */ -#define LCD_F_PCTL0_S6 ((uint32_t)0x00000040) /*!< LCD pin 6 enable */ -#define LCD_F_PCTL0_S7_OFS ( 7) /*!< LCDS7 Bit Offset */ -#define LCD_F_PCTL0_S7 ((uint32_t)0x00000080) /*!< LCD pin 7 enable */ -#define LCD_F_PCTL0_S8_OFS ( 8) /*!< LCDS8 Bit Offset */ -#define LCD_F_PCTL0_S8 ((uint32_t)0x00000100) /*!< LCD pin 8 enable */ -#define LCD_F_PCTL0_S9_OFS ( 9) /*!< LCDS9 Bit Offset */ -#define LCD_F_PCTL0_S9 ((uint32_t)0x00000200) /*!< LCD pin 9 enable */ -#define LCD_F_PCTL0_S10_OFS (10) /*!< LCDS10 Bit Offset */ -#define LCD_F_PCTL0_S10 ((uint32_t)0x00000400) /*!< LCD pin 10 enable */ -#define LCD_F_PCTL0_S11_OFS (11) /*!< LCDS11 Bit Offset */ -#define LCD_F_PCTL0_S11 ((uint32_t)0x00000800) /*!< LCD pin 11 enable */ -#define LCD_F_PCTL0_S12_OFS (12) /*!< LCDS12 Bit Offset */ -#define LCD_F_PCTL0_S12 ((uint32_t)0x00001000) /*!< LCD pin 12 enable */ -#define LCD_F_PCTL0_S13_OFS (13) /*!< LCDS13 Bit Offset */ -#define LCD_F_PCTL0_S13 ((uint32_t)0x00002000) /*!< LCD pin 13 enable */ -#define LCD_F_PCTL0_S14_OFS (14) /*!< LCDS14 Bit Offset */ -#define LCD_F_PCTL0_S14 ((uint32_t)0x00004000) /*!< LCD pin 14 enable */ -#define LCD_F_PCTL0_S15_OFS (15) /*!< LCDS15 Bit Offset */ -#define LCD_F_PCTL0_S15 ((uint32_t)0x00008000) /*!< LCD pin 15 enable */ -#define LCD_F_PCTL0_S16_OFS (16) /*!< LCDS16 Bit Offset */ -#define LCD_F_PCTL0_S16 ((uint32_t)0x00010000) /*!< LCD pin 16 enable */ -#define LCD_F_PCTL0_S17_OFS (17) /*!< LCDS17 Bit Offset */ -#define LCD_F_PCTL0_S17 ((uint32_t)0x00020000) /*!< LCD pin 17 enable */ -#define LCD_F_PCTL0_S18_OFS (18) /*!< LCDS18 Bit Offset */ -#define LCD_F_PCTL0_S18 ((uint32_t)0x00040000) /*!< LCD pin 18 enable */ -#define LCD_F_PCTL0_S19_OFS (19) /*!< LCDS19 Bit Offset */ -#define LCD_F_PCTL0_S19 ((uint32_t)0x00080000) /*!< LCD pin 19 enable */ -#define LCD_F_PCTL0_S20_OFS (20) /*!< LCDS20 Bit Offset */ -#define LCD_F_PCTL0_S20 ((uint32_t)0x00100000) /*!< LCD pin 20 enable */ -#define LCD_F_PCTL0_S21_OFS (21) /*!< LCDS21 Bit Offset */ -#define LCD_F_PCTL0_S21 ((uint32_t)0x00200000) /*!< LCD pin 21 enable */ -#define LCD_F_PCTL0_S22_OFS (22) /*!< LCDS22 Bit Offset */ -#define LCD_F_PCTL0_S22 ((uint32_t)0x00400000) /*!< LCD pin 22 enable */ -#define LCD_F_PCTL0_S23_OFS (23) /*!< LCDS23 Bit Offset */ -#define LCD_F_PCTL0_S23 ((uint32_t)0x00800000) /*!< LCD pin 23 enable */ -#define LCD_F_PCTL0_S24_OFS (24) /*!< LCDS24 Bit Offset */ -#define LCD_F_PCTL0_S24 ((uint32_t)0x01000000) /*!< LCD pin 24 enable */ -#define LCD_F_PCTL0_S25_OFS (25) /*!< LCDS25 Bit Offset */ -#define LCD_F_PCTL0_S25 ((uint32_t)0x02000000) /*!< LCD pin 25 enable */ -#define LCD_F_PCTL0_S26_OFS (26) /*!< LCDS26 Bit Offset */ -#define LCD_F_PCTL0_S26 ((uint32_t)0x04000000) /*!< LCD pin 26 enable */ -#define LCD_F_PCTL0_S27_OFS (27) /*!< LCDS27 Bit Offset */ -#define LCD_F_PCTL0_S27 ((uint32_t)0x08000000) /*!< LCD pin 27 enable */ -#define LCD_F_PCTL0_S28_OFS (28) /*!< LCDS28 Bit Offset */ -#define LCD_F_PCTL0_S28 ((uint32_t)0x10000000) /*!< LCD pin 28 enable */ -#define LCD_F_PCTL0_S29_OFS (29) /*!< LCDS29 Bit Offset */ -#define LCD_F_PCTL0_S29 ((uint32_t)0x20000000) /*!< LCD pin 29 enable */ -#define LCD_F_PCTL0_S30_OFS (30) /*!< LCDS30 Bit Offset */ -#define LCD_F_PCTL0_S30 ((uint32_t)0x40000000) /*!< LCD pin 30 enable */ -#define LCD_F_PCTL0_S31_OFS (31) /*!< LCDS31 Bit Offset */ -#define LCD_F_PCTL0_S31 ((uint32_t)0x80000000) /*!< LCD pin 31 enable */ -#define LCD_F_PCTL1_S32_OFS ( 0) /*!< LCDS32 Bit Offset */ -#define LCD_F_PCTL1_S32 ((uint32_t)0x00000001) /*!< LCD pin 32 enable */ -#define LCD_F_PCTL1_S33_OFS ( 1) /*!< LCDS33 Bit Offset */ -#define LCD_F_PCTL1_S33 ((uint32_t)0x00000002) /*!< LCD pin 33 enable */ -#define LCD_F_PCTL1_S34_OFS ( 2) /*!< LCDS34 Bit Offset */ -#define LCD_F_PCTL1_S34 ((uint32_t)0x00000004) /*!< LCD pin 34 enable */ -#define LCD_F_PCTL1_S35_OFS ( 3) /*!< LCDS35 Bit Offset */ -#define LCD_F_PCTL1_S35 ((uint32_t)0x00000008) /*!< LCD pin 35 enable */ -#define LCD_F_PCTL1_S36_OFS ( 4) /*!< LCDS36 Bit Offset */ -#define LCD_F_PCTL1_S36 ((uint32_t)0x00000010) /*!< LCD pin 36 enable */ -#define LCD_F_PCTL1_S37_OFS ( 5) /*!< LCDS37 Bit Offset */ -#define LCD_F_PCTL1_S37 ((uint32_t)0x00000020) /*!< LCD pin 37 enable */ -#define LCD_F_PCTL1_S38_OFS ( 6) /*!< LCDS38 Bit Offset */ -#define LCD_F_PCTL1_S38 ((uint32_t)0x00000040) /*!< LCD pin 38 enable */ -#define LCD_F_PCTL1_S39_OFS ( 7) /*!< LCDS39 Bit Offset */ -#define LCD_F_PCTL1_S39 ((uint32_t)0x00000080) /*!< LCD pin 39 enable */ -#define LCD_F_PCTL1_S40_OFS ( 8) /*!< LCDS40 Bit Offset */ -#define LCD_F_PCTL1_S40 ((uint32_t)0x00000100) /*!< LCD pin 40 enable */ -#define LCD_F_PCTL1_S41_OFS ( 9) /*!< LCDS41 Bit Offset */ -#define LCD_F_PCTL1_S41 ((uint32_t)0x00000200) /*!< LCD pin 41 enable */ -#define LCD_F_PCTL1_S42_OFS (10) /*!< LCDS42 Bit Offset */ -#define LCD_F_PCTL1_S42 ((uint32_t)0x00000400) /*!< LCD pin 42 enable */ -#define LCD_F_PCTL1_S43_OFS (11) /*!< LCDS43 Bit Offset */ -#define LCD_F_PCTL1_S43 ((uint32_t)0x00000800) /*!< LCD pin 43 enable */ -#define LCD_F_PCTL1_S44_OFS (12) /*!< LCDS44 Bit Offset */ -#define LCD_F_PCTL1_S44 ((uint32_t)0x00001000) /*!< LCD pin 44 enable */ -#define LCD_F_PCTL1_S45_OFS (13) /*!< LCDS45 Bit Offset */ -#define LCD_F_PCTL1_S45 ((uint32_t)0x00002000) /*!< LCD pin 45 enable */ -#define LCD_F_PCTL1_S46_OFS (14) /*!< LCDS46 Bit Offset */ -#define LCD_F_PCTL1_S46 ((uint32_t)0x00004000) /*!< LCD pin 46 enable */ -#define LCD_F_PCTL1_S47_OFS (15) /*!< LCDS47 Bit Offset */ -#define LCD_F_PCTL1_S47 ((uint32_t)0x00008000) /*!< LCD pin 47 enable */ -#define LCD_F_PCTL1_S48_OFS (16) /*!< LCDS48 Bit Offset */ -#define LCD_F_PCTL1_S48 ((uint32_t)0x00010000) /*!< LCD pin 48 enable */ -#define LCD_F_PCTL1_S49_OFS (17) /*!< LCDS49 Bit Offset */ -#define LCD_F_PCTL1_S49 ((uint32_t)0x00020000) /*!< LCD pin 49 enable */ -#define LCD_F_PCTL1_S50_OFS (18) /*!< LCDS50 Bit Offset */ -#define LCD_F_PCTL1_S50 ((uint32_t)0x00040000) /*!< LCD pin 50 enable */ -#define LCD_F_PCTL1_S51_OFS (19) /*!< LCDS51 Bit Offset */ -#define LCD_F_PCTL1_S51 ((uint32_t)0x00080000) /*!< LCD pin 51 enable */ -#define LCD_F_PCTL1_S52_OFS (20) /*!< LCDS52 Bit Offset */ -#define LCD_F_PCTL1_S52 ((uint32_t)0x00100000) /*!< LCD pin 52 enable */ -#define LCD_F_PCTL1_S53_OFS (21) /*!< LCDS53 Bit Offset */ -#define LCD_F_PCTL1_S53 ((uint32_t)0x00200000) /*!< LCD pin 53 enable */ -#define LCD_F_PCTL1_S54_OFS (22) /*!< LCDS54 Bit Offset */ -#define LCD_F_PCTL1_S54 ((uint32_t)0x00400000) /*!< LCD pin 54 enable */ -#define LCD_F_PCTL1_S55_OFS (23) /*!< LCDS55 Bit Offset */ -#define LCD_F_PCTL1_S55 ((uint32_t)0x00800000) /*!< LCD pin 55 enable */ -#define LCD_F_PCTL1_S56_OFS (24) /*!< LCDS56 Bit Offset */ -#define LCD_F_PCTL1_S56 ((uint32_t)0x01000000) /*!< LCD pin 56 enable */ -#define LCD_F_PCTL1_S57_OFS (25) /*!< LCDS57 Bit Offset */ -#define LCD_F_PCTL1_S57 ((uint32_t)0x02000000) /*!< LCD pin 57 enable */ -#define LCD_F_PCTL1_S58_OFS (26) /*!< LCDS58 Bit Offset */ -#define LCD_F_PCTL1_S58 ((uint32_t)0x04000000) /*!< LCD pin 58 enable */ -#define LCD_F_PCTL1_S59_OFS (27) /*!< LCDS59 Bit Offset */ -#define LCD_F_PCTL1_S59 ((uint32_t)0x08000000) /*!< LCD pin 59 enable */ -#define LCD_F_PCTL1_S60_OFS (28) /*!< LCDS60 Bit Offset */ -#define LCD_F_PCTL1_S60 ((uint32_t)0x10000000) /*!< LCD pin 60 enable */ -#define LCD_F_PCTL1_S61_OFS (29) /*!< LCDS61 Bit Offset */ -#define LCD_F_PCTL1_S61 ((uint32_t)0x20000000) /*!< LCD pin 61 enable */ -#define LCD_F_PCTL1_S62_OFS (30) /*!< LCDS62 Bit Offset */ -#define LCD_F_PCTL1_S62 ((uint32_t)0x40000000) /*!< LCD pin 62 enable */ -#define LCD_F_PCTL1_S63_OFS (31) /*!< LCDS63 Bit Offset */ -#define LCD_F_PCTL1_S63 ((uint32_t)0x80000000) /*!< LCD pin 63 enable */ -#define LCD_F_CSSEL0_CSS0_OFS ( 0) /*!< LCDCSS0 Bit Offset */ -#define LCD_F_CSSEL0_CSS0 ((uint32_t)0x00000001) /*!< L0 Com Seg select */ -#define LCD_F_CSSEL0_CSS1_OFS ( 1) /*!< LCDCSS1 Bit Offset */ -#define LCD_F_CSSEL0_CSS1 ((uint32_t)0x00000002) /*!< L1 Com Seg select */ -#define LCD_F_CSSEL0_CSS2_OFS ( 2) /*!< LCDCSS2 Bit Offset */ -#define LCD_F_CSSEL0_CSS2 ((uint32_t)0x00000004) /*!< L2 Com Seg select */ -#define LCD_F_CSSEL0_CSS3_OFS ( 3) /*!< LCDCSS3 Bit Offset */ -#define LCD_F_CSSEL0_CSS3 ((uint32_t)0x00000008) /*!< L3 Com Seg select */ -#define LCD_F_CSSEL0_CSS4_OFS ( 4) /*!< LCDCSS4 Bit Offset */ -#define LCD_F_CSSEL0_CSS4 ((uint32_t)0x00000010) /*!< L4 Com Seg select */ -#define LCD_F_CSSEL0_CSS5_OFS ( 5) /*!< LCDCSS5 Bit Offset */ -#define LCD_F_CSSEL0_CSS5 ((uint32_t)0x00000020) /*!< L5 Com Seg select */ -#define LCD_F_CSSEL0_CSS6_OFS ( 6) /*!< LCDCSS6 Bit Offset */ -#define LCD_F_CSSEL0_CSS6 ((uint32_t)0x00000040) /*!< L6 Com Seg select */ -#define LCD_F_CSSEL0_CSS7_OFS ( 7) /*!< LCDCSS7 Bit Offset */ -#define LCD_F_CSSEL0_CSS7 ((uint32_t)0x00000080) /*!< L7 Com Seg select */ -#define LCD_F_CSSEL0_CSS8_OFS ( 8) /*!< LCDCSS8 Bit Offset */ -#define LCD_F_CSSEL0_CSS8 ((uint32_t)0x00000100) /*!< L8 Com Seg select */ -#define LCD_F_CSSEL0_CSS9_OFS ( 9) /*!< LCDCSS9 Bit Offset */ -#define LCD_F_CSSEL0_CSS9 ((uint32_t)0x00000200) /*!< L9 Com Seg select */ -#define LCD_F_CSSEL0_CSS10_OFS (10) /*!< LCDCSS10 Bit Offset */ -#define LCD_F_CSSEL0_CSS10 ((uint32_t)0x00000400) /*!< L10 Com Seg select */ -#define LCD_F_CSSEL0_CSS11_OFS (11) /*!< LCDCSS11 Bit Offset */ -#define LCD_F_CSSEL0_CSS11 ((uint32_t)0x00000800) /*!< L11 Com Seg select */ -#define LCD_F_CSSEL0_CSS12_OFS (12) /*!< LCDCSS12 Bit Offset */ -#define LCD_F_CSSEL0_CSS12 ((uint32_t)0x00001000) /*!< L12 Com Seg select */ -#define LCD_F_CSSEL0_CSS13_OFS (13) /*!< LCDCSS13 Bit Offset */ -#define LCD_F_CSSEL0_CSS13 ((uint32_t)0x00002000) /*!< L13 Com Seg select */ -#define LCD_F_CSSEL0_CSS14_OFS (14) /*!< LCDCSS14 Bit Offset */ -#define LCD_F_CSSEL0_CSS14 ((uint32_t)0x00004000) /*!< L14 Com Seg select */ -#define LCD_F_CSSEL0_CSS15_OFS (15) /*!< LCDCSS15 Bit Offset */ -#define LCD_F_CSSEL0_CSS15 ((uint32_t)0x00008000) /*!< L15 Com Seg select */ -#define LCD_F_CSSEL0_CSS16_OFS (16) /*!< LCDCSS16 Bit Offset */ -#define LCD_F_CSSEL0_CSS16 ((uint32_t)0x00010000) /*!< L16 Com Seg select */ -#define LCD_F_CSSEL0_CSS17_OFS (17) /*!< LCDCSS17 Bit Offset */ -#define LCD_F_CSSEL0_CSS17 ((uint32_t)0x00020000) /*!< L17 Com Seg select */ -#define LCD_F_CSSEL0_CSS18_OFS (18) /*!< LCDCSS18 Bit Offset */ -#define LCD_F_CSSEL0_CSS18 ((uint32_t)0x00040000) /*!< L18 Com Seg select */ -#define LCD_F_CSSEL0_CSS19_OFS (19) /*!< LCDCSS19 Bit Offset */ -#define LCD_F_CSSEL0_CSS19 ((uint32_t)0x00080000) /*!< L19 Com Seg select */ -#define LCD_F_CSSEL0_CSS20_OFS (20) /*!< LCDCSS20 Bit Offset */ -#define LCD_F_CSSEL0_CSS20 ((uint32_t)0x00100000) /*!< L20 Com Seg select */ -#define LCD_F_CSSEL0_CSS21_OFS (21) /*!< LCDCSS21 Bit Offset */ -#define LCD_F_CSSEL0_CSS21 ((uint32_t)0x00200000) /*!< L21 Com Seg select */ -#define LCD_F_CSSEL0_CSS22_OFS (22) /*!< LCDCSS22 Bit Offset */ -#define LCD_F_CSSEL0_CSS22 ((uint32_t)0x00400000) /*!< L22 Com Seg select */ -#define LCD_F_CSSEL0_CSS23_OFS (23) /*!< LCDCSS23 Bit Offset */ -#define LCD_F_CSSEL0_CSS23 ((uint32_t)0x00800000) /*!< L23 Com Seg select */ -#define LCD_F_CSSEL0_CSS24_OFS (24) /*!< LCDCSS24 Bit Offset */ -#define LCD_F_CSSEL0_CSS24 ((uint32_t)0x01000000) /*!< L24 Com Seg select */ -#define LCD_F_CSSEL0_CSS25_OFS (25) /*!< LCDCSS25 Bit Offset */ -#define LCD_F_CSSEL0_CSS25 ((uint32_t)0x02000000) /*!< L25 Com Seg select */ -#define LCD_F_CSSEL0_CSS26_OFS (26) /*!< LCDCSS26 Bit Offset */ -#define LCD_F_CSSEL0_CSS26 ((uint32_t)0x04000000) /*!< L26 Com Seg select */ -#define LCD_F_CSSEL0_CSS27_OFS (27) /*!< LCDCSS27 Bit Offset */ -#define LCD_F_CSSEL0_CSS27 ((uint32_t)0x08000000) /*!< L27 Com Seg select */ -#define LCD_F_CSSEL0_CSS28_OFS (28) /*!< LCDCSS28 Bit Offset */ -#define LCD_F_CSSEL0_CSS28 ((uint32_t)0x10000000) /*!< L28 Com Seg select */ -#define LCD_F_CSSEL0_CSS29_OFS (29) /*!< LCDCSS29 Bit Offset */ -#define LCD_F_CSSEL0_CSS29 ((uint32_t)0x20000000) /*!< L29 Com Seg select */ -#define LCD_F_CSSEL0_CSS30_OFS (30) /*!< LCDCSS30 Bit Offset */ -#define LCD_F_CSSEL0_CSS30 ((uint32_t)0x40000000) /*!< L30 Com Seg select */ -#define LCD_F_CSSEL0_CSS31_OFS (31) /*!< LCDCSS31 Bit Offset */ -#define LCD_F_CSSEL0_CSS31 ((uint32_t)0x80000000) /*!< L31 Com Seg select */ -#define LCD_F_CSSEL1_CSS32_OFS ( 0) /*!< LCDCSS32 Bit Offset */ -#define LCD_F_CSSEL1_CSS32 ((uint32_t)0x00000001) /*!< L32 Com Seg select */ -#define LCD_F_CSSEL1_CSS33_OFS ( 1) /*!< LCDCSS33 Bit Offset */ -#define LCD_F_CSSEL1_CSS33 ((uint32_t)0x00000002) /*!< L33 Com Seg select */ -#define LCD_F_CSSEL1_CSS34_OFS ( 2) /*!< LCDCSS34 Bit Offset */ -#define LCD_F_CSSEL1_CSS34 ((uint32_t)0x00000004) /*!< L34 Com Seg select */ -#define LCD_F_CSSEL1_CSS35_OFS ( 3) /*!< LCDCSS35 Bit Offset */ -#define LCD_F_CSSEL1_CSS35 ((uint32_t)0x00000008) /*!< L35 Com Seg select */ -#define LCD_F_CSSEL1_CSS36_OFS ( 4) /*!< LCDCSS36 Bit Offset */ -#define LCD_F_CSSEL1_CSS36 ((uint32_t)0x00000010) /*!< L36 Com Seg select */ -#define LCD_F_CSSEL1_CSS37_OFS ( 5) /*!< LCDCSS37 Bit Offset */ -#define LCD_F_CSSEL1_CSS37 ((uint32_t)0x00000020) /*!< L37 Com Seg select */ -#define LCD_F_CSSEL1_CSS38_OFS ( 6) /*!< LCDCSS38 Bit Offset */ -#define LCD_F_CSSEL1_CSS38 ((uint32_t)0x00000040) /*!< L38 Com Seg select */ -#define LCD_F_CSSEL1_CSS39_OFS ( 7) /*!< LCDCSS39 Bit Offset */ -#define LCD_F_CSSEL1_CSS39 ((uint32_t)0x00000080) /*!< L39 Com Seg select */ -#define LCD_F_CSSEL1_CSS40_OFS ( 8) /*!< LCDCSS40 Bit Offset */ -#define LCD_F_CSSEL1_CSS40 ((uint32_t)0x00000100) /*!< L40 Com Seg select */ -#define LCD_F_CSSEL1_CSS41_OFS ( 9) /*!< LCDCSS41 Bit Offset */ -#define LCD_F_CSSEL1_CSS41 ((uint32_t)0x00000200) /*!< L41 Com Seg select */ -#define LCD_F_CSSEL1_CSS42_OFS (10) /*!< LCDCSS42 Bit Offset */ -#define LCD_F_CSSEL1_CSS42 ((uint32_t)0x00000400) /*!< L42 Com Seg select */ -#define LCD_F_CSSEL1_CSS43_OFS (11) /*!< LCDCSS43 Bit Offset */ -#define LCD_F_CSSEL1_CSS43 ((uint32_t)0x00000800) /*!< L43 Com Seg select */ -#define LCD_F_CSSEL1_CSS44_OFS (12) /*!< LCDCSS44 Bit Offset */ -#define LCD_F_CSSEL1_CSS44 ((uint32_t)0x00001000) /*!< L44 Com Seg select */ -#define LCD_F_CSSEL1_CSS45_OFS (13) /*!< LCDCSS45 Bit Offset */ -#define LCD_F_CSSEL1_CSS45 ((uint32_t)0x00002000) /*!< L45 Com Seg select */ -#define LCD_F_CSSEL1_CSS46_OFS (14) /*!< LCDCSS46 Bit Offset */ -#define LCD_F_CSSEL1_CSS46 ((uint32_t)0x00004000) /*!< L46 Com Seg select */ -#define LCD_F_CSSEL1_CSS47_OFS (15) /*!< LCDCSS47 Bit Offset */ -#define LCD_F_CSSEL1_CSS47 ((uint32_t)0x00008000) /*!< L47 Com Seg select */ -#define LCD_F_CSSEL1_CSS48_OFS (16) /*!< LCDCSS48 Bit Offset */ -#define LCD_F_CSSEL1_CSS48 ((uint32_t)0x00010000) /*!< L48 Com Seg select */ -#define LCD_F_CSSEL1_CSS49_OFS (17) /*!< LCDCSS49 Bit Offset */ -#define LCD_F_CSSEL1_CSS49 ((uint32_t)0x00020000) /*!< L49 Com Seg select */ -#define LCD_F_CSSEL1_CSS50_OFS (18) /*!< LCDCSS50 Bit Offset */ -#define LCD_F_CSSEL1_CSS50 ((uint32_t)0x00040000) /*!< L50 Com Seg select */ -#define LCD_F_CSSEL1_CSS51_OFS (19) /*!< LCDCSS51 Bit Offset */ -#define LCD_F_CSSEL1_CSS51 ((uint32_t)0x00080000) /*!< L51 Com Seg select */ -#define LCD_F_CSSEL1_CSS52_OFS (20) /*!< LCDCSS52 Bit Offset */ -#define LCD_F_CSSEL1_CSS52 ((uint32_t)0x00100000) /*!< L52 Com Seg select */ -#define LCD_F_CSSEL1_CSS53_OFS (21) /*!< LCDCSS53 Bit Offset */ -#define LCD_F_CSSEL1_CSS53 ((uint32_t)0x00200000) /*!< L53 Com Seg select */ -#define LCD_F_CSSEL1_CSS54_OFS (22) /*!< LCDCSS54 Bit Offset */ -#define LCD_F_CSSEL1_CSS54 ((uint32_t)0x00400000) /*!< L54 Com Seg select */ -#define LCD_F_CSSEL1_CSS55_OFS (23) /*!< LCDCSS55 Bit Offset */ -#define LCD_F_CSSEL1_CSS55 ((uint32_t)0x00800000) /*!< L55 Com Seg select */ -#define LCD_F_CSSEL1_CSS56_OFS (24) /*!< LCDCSS56 Bit Offset */ -#define LCD_F_CSSEL1_CSS56 ((uint32_t)0x01000000) /*!< L56 Com Seg select */ -#define LCD_F_CSSEL1_CSS57_OFS (25) /*!< LCDCSS57 Bit Offset */ -#define LCD_F_CSSEL1_CSS57 ((uint32_t)0x02000000) /*!< L57 Com Seg select */ -#define LCD_F_CSSEL1_CSS58_OFS (26) /*!< LCDCSS58 Bit Offset */ -#define LCD_F_CSSEL1_CSS58 ((uint32_t)0x04000000) /*!< L58 Com Seg select */ -#define LCD_F_CSSEL1_CSS59_OFS (27) /*!< LCDCSS59 Bit Offset */ -#define LCD_F_CSSEL1_CSS59 ((uint32_t)0x08000000) /*!< L59 Com Seg select */ -#define LCD_F_CSSEL1_CSS60_OFS (28) /*!< LCDCSS60 Bit Offset */ -#define LCD_F_CSSEL1_CSS60 ((uint32_t)0x10000000) /*!< L60 Com Seg select */ -#define LCD_F_CSSEL1_CSS61_OFS (29) /*!< LCDCSS61 Bit Offset */ -#define LCD_F_CSSEL1_CSS61 ((uint32_t)0x20000000) /*!< L61 Com Seg select */ -#define LCD_F_CSSEL1_CSS62_OFS (30) /*!< LCDCSS62 Bit Offset */ -#define LCD_F_CSSEL1_CSS62 ((uint32_t)0x40000000) /*!< L62 Com Seg select */ -#define LCD_F_CSSEL1_CSS63_OFS (31) /*!< LCDCSS63 Bit Offset */ -#define LCD_F_CSSEL1_CSS63 ((uint32_t)0x80000000) /*!< L63 Com Seg select */ -#define LCD_F_ANMCTL_ANMEN_OFS ( 0) /*!< LCDANMEN Bit Offset */ -#define LCD_F_ANMCTL_ANMEN ((uint32_t)0x00000001) /*!< Enable Animation */ -#define LCD_F_ANMCTL_ANMSTP_OFS ( 1) /*!< LCDANMSTP Bit Offset */ -#define LCD_F_ANMCTL_ANMSTP_MASK ((uint32_t)0x0000000E) /*!< LCDANMSTP Bit Mask */ -#define LCD_F_ANMCTL_ANMSTP0 ((uint32_t)0x00000002) /*!< ANMSTP Bit 0 */ -#define LCD_F_ANMCTL_ANMSTP1 ((uint32_t)0x00000004) /*!< ANMSTP Bit 1 */ -#define LCD_F_ANMCTL_ANMSTP2 ((uint32_t)0x00000008) /*!< ANMSTP Bit 2 */ -#define LCD_F_ANMCTL_ANMSTP_0 ((uint32_t)0x00000000) /*!< T0 */ -#define LCD_F_ANMCTL_ANMSTP_1 ((uint32_t)0x00000002) /*!< T0 to T1 */ -#define LCD_F_ANMCTL_ANMSTP_2 ((uint32_t)0x00000004) /*!< T0 to T2 */ -#define LCD_F_ANMCTL_ANMSTP_3 ((uint32_t)0x00000006) /*!< T0 to T3 */ -#define LCD_F_ANMCTL_ANMSTP_4 ((uint32_t)0x00000008) /*!< T0 to T4 */ -#define LCD_F_ANMCTL_ANMSTP_5 ((uint32_t)0x0000000A) /*!< T0 to T5 */ -#define LCD_F_ANMCTL_ANMSTP_6 ((uint32_t)0x0000000C) /*!< T0 to T6 */ -#define LCD_F_ANMCTL_ANMSTP_7 ((uint32_t)0x0000000E) /*!< T0 to T7 */ -#define LCD_F_ANMCTL_ANMCLR_OFS ( 7) /*!< LCDANMCLR Bit Offset */ -#define LCD_F_ANMCTL_ANMCLR ((uint32_t)0x00000080) /*!< Clear Animation Memory */ -#define LCD_F_ANMCTL_ANMPRE_OFS (16) /*!< LCDANMPREx Bit Offset */ -#define LCD_F_ANMCTL_ANMPRE_MASK ((uint32_t)0x00070000) /*!< LCDANMPREx Bit Mask */ -#define LCD_F_ANMCTL_ANMPRE0 ((uint32_t)0x00010000) /*!< ANMPRE Bit 0 */ -#define LCD_F_ANMCTL_ANMPRE1 ((uint32_t)0x00020000) /*!< ANMPRE Bit 1 */ -#define LCD_F_ANMCTL_ANMPRE2 ((uint32_t)0x00040000) /*!< ANMPRE Bit 2 */ -#define LCD_F_ANMCTL_ANMPRE_0 ((uint32_t)0x00000000) /*!< Divide by 512 */ -#define LCD_F_ANMCTL_ANMPRE_1 ((uint32_t)0x00010000) /*!< Divide by 1024 */ -#define LCD_F_ANMCTL_ANMPRE_2 ((uint32_t)0x00020000) /*!< Divide by 2048 */ -#define LCD_F_ANMCTL_ANMPRE_3 ((uint32_t)0x00030000) /*!< Divide by 4096 */ -#define LCD_F_ANMCTL_ANMPRE_4 ((uint32_t)0x00040000) /*!< Divide by 8162 */ -#define LCD_F_ANMCTL_ANMPRE_5 ((uint32_t)0x00050000) /*!< Divide by 16384 */ -#define LCD_F_ANMCTL_ANMPRE_6 ((uint32_t)0x00060000) /*!< Divide by 32768 */ -#define LCD_F_ANMCTL_ANMPRE_7 ((uint32_t)0x00070000) /*!< Divide by 65536 */ -#define LCD_F_ANMCTL_ANMDIV_OFS (19) /*!< LCDANMDIVx Bit Offset */ -#define LCD_F_ANMCTL_ANMDIV_MASK ((uint32_t)0x00380000) /*!< LCDANMDIVx Bit Mask */ -#define LCD_F_ANMCTL_ANMDIV0 ((uint32_t)0x00080000) /*!< ANMDIV Bit 0 */ -#define LCD_F_ANMCTL_ANMDIV1 ((uint32_t)0x00100000) /*!< ANMDIV Bit 1 */ -#define LCD_F_ANMCTL_ANMDIV2 ((uint32_t)0x00200000) /*!< ANMDIV Bit 2 */ -#define LCD_F_ANMCTL_ANMDIV_0 ((uint32_t)0x00000000) /*!< Divide by 1 */ -#define LCD_F_ANMCTL_ANMDIV_1 ((uint32_t)0x00080000) /*!< Divide by 2 */ -#define LCD_F_ANMCTL_ANMDIV_2 ((uint32_t)0x00100000) /*!< Divide by 3 */ -#define LCD_F_ANMCTL_ANMDIV_3 ((uint32_t)0x00180000) /*!< Divide by 4 */ -#define LCD_F_ANMCTL_ANMDIV_4 ((uint32_t)0x00200000) /*!< Divide by 5 */ -#define LCD_F_ANMCTL_ANMDIV_5 ((uint32_t)0x00280000) /*!< Divide by 6 */ -#define LCD_F_ANMCTL_ANMDIV_6 ((uint32_t)0x00300000) /*!< Divide by 7 */ -#define LCD_F_ANMCTL_ANMDIV_7 ((uint32_t)0x00380000) /*!< Divide by 8 */ -#define LCD_F_IE_BLKOFFIE_OFS ( 1) /*!< LCDBLKOFFIE Bit Offset */ -#define LCD_F_IE_BLKOFFIE ((uint32_t)0x00000002) /*!< LCD Blink, segments off interrupt enable */ -#define LCD_F_IE_BLKONIE_OFS ( 2) /*!< LCDBLKONIE Bit Offset */ -#define LCD_F_IE_BLKONIE ((uint32_t)0x00000004) /*!< LCD Blink, segments on interrupt enable */ -#define LCD_F_IE_FRMIE_OFS ( 3) /*!< LCDFRMIE Bit Offset */ -#define LCD_F_IE_FRMIE ((uint32_t)0x00000008) /*!< LCD Frame interrupt enable */ -#define LCD_F_IE_ANMSTPIE_OFS ( 8) /*!< LCDANMSTPIE Bit Offset */ -#define LCD_F_IE_ANMSTPIE ((uint32_t)0x00000100) /*!< LCD Animation step interrupt enable */ -#define LCD_F_IE_ANMLOOPIE_OFS ( 9) /*!< LCDANMLOOPIE Bit Offset */ -#define LCD_F_IE_ANMLOOPIE ((uint32_t)0x00000200) /*!< LCD Animation loop interrupt enable */ -#define LCD_F_IFG_BLKOFFIFG_OFS ( 1) /*!< LCDBLKOFFIFG Bit Offset */ -#define LCD_F_IFG_BLKOFFIFG ((uint32_t)0x00000002) /*!< LCD Blink, segments off interrupt flag */ -#define LCD_F_IFG_BLKONIFG_OFS ( 2) /*!< LCDBLKONIFG Bit Offset */ -#define LCD_F_IFG_BLKONIFG ((uint32_t)0x00000004) /*!< LCD Blink, segments on interrupt flag */ -#define LCD_F_IFG_FRMIFG_OFS ( 3) /*!< LCDFRMIFG Bit Offset */ -#define LCD_F_IFG_FRMIFG ((uint32_t)0x00000008) /*!< LCD Frame interrupt flag */ -#define LCD_F_IFG_ANMSTPIFG_OFS ( 8) /*!< LCDANMSTPIFG Bit Offset */ -#define LCD_F_IFG_ANMSTPIFG ((uint32_t)0x00000100) /*!< LCD Animation step interrupt flag */ -#define LCD_F_IFG_ANMLOOPIFG_OFS ( 9) /*!< LCDANMLOOPIFG Bit Offset */ -#define LCD_F_IFG_ANMLOOPIFG ((uint32_t)0x00000200) /*!< LCD Animation loop interrupt flag */ -#define LCD_F_SETIFG_SETLCDBLKOFFIFG_OFS ( 1) /*!< SETLCDBLKOFFIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDBLKOFFIFG ((uint32_t)0x00000002) /*!< Sets LCDBLKOFFIFG */ -#define LCD_F_SETIFG_SETLCDBLKONIFG_OFS ( 2) /*!< SETLCDBLKONIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDBLKONIFG ((uint32_t)0x00000004) /*!< Sets LCDBLKONIFG */ -#define LCD_F_SETIFG_SETLCDFRMIFG_OFS ( 3) /*!< SETLCDFRMIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDFRMIFG ((uint32_t)0x00000008) /*!< Sets LCDFRMIFG */ -#define LCD_F_SETIFG_SETLCDANMSTPIFG_OFS ( 8) /*!< SETLCDANMSTPIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDANMSTPIFG ((uint32_t)0x00000100) /*!< Sets LCDANMSTPIFG */ -#define LCD_F_SETIFG_SETLCDANMLOOPIFG_OFS ( 9) /*!< SETLCDANMLOOPIFG Bit Offset */ -#define LCD_F_SETIFG_SETLCDANMLOOPIFG ((uint32_t)0x00000200) /*!< Sets LCDANMLOOPIFG */ -#define LCD_F_CLRIFG_CLRLCDBLKOFFIFG_OFS ( 1) /*!< CLRLCDBLKOFFIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDBLKOFFIFG ((uint32_t)0x00000002) /*!< Clears LCDBLKOFFIFG */ -#define LCD_F_CLRIFG_CLRLCDBLKONIFG_OFS ( 2) /*!< CLRLCDBLKONIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDBLKONIFG ((uint32_t)0x00000004) /*!< Clears LCDBLKONIFG */ -#define LCD_F_CLRIFG_CLRLCDFRMIFG_OFS ( 3) /*!< CLRLCDFRMIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDFRMIFG ((uint32_t)0x00000008) /*!< Clears LCDFRMIFG */ -#define LCD_F_CLRIFG_CLRLCDANMSTPIFG_OFS ( 8) /*!< CLRLCDANMSTPIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDANMSTPIFG ((uint32_t)0x00000100) /*!< Clears LCDANMSTPIFG */ -#define LCD_F_CLRIFG_CLRLCDANMLOOPIFG_OFS ( 9) /*!< CLRLCDANMLOOPIFG Bit Offset */ -#define LCD_F_CLRIFG_CLRLCDANMLOOPIFG ((uint32_t)0x00000200) /*!< Clears LCDANMLOOPIFG */ -#define SYSCTL_A_REBOOT_CTL_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ -#define SYSCTL_A_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /*!< Write 1 initiates a Reboot of the device */ -#define SYSCTL_A_REBOOT_CTL_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_A_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -#define SYSCTL_A_NMI_CTLSTAT_CS_SRC_OFS ( 0) /*!< CS_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /*!< CS interrupt as a source of NMI */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /*!< PSS_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /*!< PSS interrupt as a source of NMI */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /*!< PCM_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /*!< PCM interrupt as a source of NMI */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /*!< PIN_SRC Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008) -#define SYSCTL_A_NMI_CTLSTAT_CS_FLG_OFS (16) /*!< CS_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /*!< CS interrupt was the source of NMI */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_FLG_OFS (17) /*!< PSS_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /*!< PSS interrupt was the source of NMI */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_FLG_OFS (18) /*!< PCM_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /*!< PCM interrupt was the source of NMI */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_FLG_OFS (19) /*!< PIN_FLG Bit Offset */ -#define SYSCTL_A_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /*!< RSTn/NMI pin was the source of NMI */ -#define SYSCTL_A_WDTRESET_CTL_TIMEOUT_OFS ( 0) /*!< TIMEOUT Bit Offset */ -#define SYSCTL_A_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /*!< WDT timeout reset type */ -#define SYSCTL_A_WDTRESET_CTL_VIOLATION_OFS ( 1) /*!< VIOLATION Bit Offset */ -#define SYSCTL_A_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /*!< WDT password violation reset type */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /*!< HALT_T16_0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /*!< HALT_T16_1 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /*!< HALT_T16_2 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /*!< HALT_T16_3 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /*!< HALT_T32_0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /*!< HALT_eUA0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /*!< HALT_eUA1 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /*!< HALT_eUA2 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /*!< HALT_eUA3 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /*!< HALT_eUB0 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB1_OFS (10) /*!< HALT_eUB1 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB2_OFS (11) /*!< HALT_eUB2 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB3_OFS (12) /*!< HALT_eUB3 Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_ADC_OFS (13) /*!< HALT_ADC Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_WDT_OFS (14) /*!< HALT_WDT Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_DMA_OFS (15) /*!< HALT_DMA Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_PERIHALT_CTL_HALT_LCD_OFS (16) /*!< HALT_LCD Bit Offset */ -#define SYSCTL_A_PERIHALT_CTL_HALT_LCD ((uint32_t)0x00010000) /*!< Freezes IP operation when CPU is halted */ -#define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /*!< GLTCH_EN Bit Offset */ -#define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /*!< Glitch filter enable */ -#define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN_OFS ( 0) /*!< BNK0_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank0 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN_OFS ( 1) /*!< BNK1_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank1 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN_OFS ( 2) /*!< BNK2_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank2 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN_OFS ( 3) /*!< BNK3_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank3 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN_OFS ( 4) /*!< BNK4_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank4 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN_OFS ( 5) /*!< BNK5_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank5 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN_OFS ( 6) /*!< BNK6_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank6 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN_OFS ( 7) /*!< BNK7_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank7 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN_OFS ( 8) /*!< BNK8_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank8 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN_OFS ( 9) /*!< BNK9_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank9 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN_OFS (10) /*!< BNK10_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank10 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN_OFS (11) /*!< BNK11_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank11 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN_OFS (12) /*!< BNK12_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank12 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN_OFS (13) /*!< BNK13_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank13 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN_OFS (14) /*!< BNK14_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank14 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN_OFS (15) /*!< BNK15_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank15 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN_OFS (16) /*!< BNK16_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank16 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN_OFS (17) /*!< BNK17_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank17 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN_OFS (18) /*!< BNK18_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank18 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN_OFS (19) /*!< BNK19_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank19 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN_OFS (20) /*!< BNK20_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank20 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN_OFS (21) /*!< BNK21_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank21 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN_OFS (22) /*!< BNK22_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank22 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN_OFS (23) /*!< BNK23_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank23 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN_OFS (24) /*!< BNK24_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank24 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN_OFS (25) /*!< BNK25_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank25 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN_OFS (26) /*!< BNK26_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank26 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN_OFS (27) /*!< BNK27_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank27 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN_OFS (28) /*!< BNK28_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank28 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN_OFS (29) /*!< BNK29_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank29 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN_OFS (30) /*!< BNK30_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank30 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN_OFS (31) /*!< BNK31_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank31 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN_OFS ( 0) /*!< BNK32_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank32 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN_OFS ( 1) /*!< BNK33_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank33 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN_OFS ( 2) /*!< BNK34_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank34 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN_OFS ( 3) /*!< BNK35_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank35 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN_OFS ( 4) /*!< BNK36_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank36 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN_OFS ( 5) /*!< BNK37_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank37 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN_OFS ( 6) /*!< BNK38_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank38 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN_OFS ( 7) /*!< BNK39_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank39 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN_OFS ( 8) /*!< BNK40_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank40 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN_OFS ( 9) /*!< BNK41_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank41 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN_OFS (10) /*!< BNK42_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank42 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN_OFS (11) /*!< BNK43_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank43 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN_OFS (12) /*!< BNK44_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank44 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN_OFS (13) /*!< BNK45_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank45 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN_OFS (14) /*!< BNK46_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank46 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN_OFS (15) /*!< BNK47_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank47 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN_OFS (16) /*!< BNK48_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank48 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN_OFS (17) /*!< BNK49_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank49 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN_OFS (18) /*!< BNK50_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank50 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN_OFS (19) /*!< BNK51_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank51 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN_OFS (20) /*!< BNK52_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank52 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN_OFS (21) /*!< BNK53_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank53 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN_OFS (22) /*!< BNK54_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank54 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN_OFS (23) /*!< BNK55_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank55 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN_OFS (24) /*!< BNK56_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank56 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN_OFS (25) /*!< BNK57_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank57 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN_OFS (26) /*!< BNK58_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank58 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN_OFS (27) /*!< BNK59_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank59 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN_OFS (28) /*!< BNK60_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank60 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN_OFS (29) /*!< BNK61_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank61 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN_OFS (30) /*!< BNK62_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank62 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN_OFS (31) /*!< BNK63_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank63 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN_OFS ( 0) /*!< BNK64_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank64 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN_OFS ( 1) /*!< BNK65_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank65 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN_OFS ( 2) /*!< BNK66_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank66 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN_OFS ( 3) /*!< BNK67_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank67 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN_OFS ( 4) /*!< BNK68_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank68 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN_OFS ( 5) /*!< BNK69_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank69 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN_OFS ( 6) /*!< BNK70_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank70 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN_OFS ( 7) /*!< BNK71_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank71 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN_OFS ( 8) /*!< BNK72_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank72 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN_OFS ( 9) /*!< BNK73_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank73 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN_OFS (10) /*!< BNK74_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank74 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN_OFS (11) /*!< BNK75_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank75 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN_OFS (12) /*!< BNK76_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank76 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN_OFS (13) /*!< BNK77_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank77 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN_OFS (14) /*!< BNK78_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank78 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN_OFS (15) /*!< BNK79_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank79 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN_OFS (16) /*!< BNK80_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank80 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN_OFS (17) /*!< BNK81_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank81 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN_OFS (18) /*!< BNK82_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank82 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN_OFS (19) /*!< BNK83_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank83 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN_OFS (20) /*!< BNK84_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank84 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN_OFS (21) /*!< BNK85_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank85 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN_OFS (22) /*!< BNK86_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank86 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN_OFS (23) /*!< BNK87_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank87 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN_OFS (24) /*!< BNK88_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank88 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN_OFS (25) /*!< BNK89_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank89 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN_OFS (26) /*!< BNK90_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank90 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN_OFS (27) /*!< BNK91_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank91 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN_OFS (28) /*!< BNK92_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank92 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN_OFS (29) /*!< BNK93_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank93 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN_OFS (30) /*!< BNK94_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank94 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN_OFS (31) /*!< BNK95_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank95 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN_OFS ( 0) /*!< BNK96_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN ((uint32_t)0x00000001) /*!< When 1, enables Bank96 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN_OFS ( 1) /*!< BNK97_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN ((uint32_t)0x00000002) /*!< When 1, enables Bank97 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN_OFS ( 2) /*!< BNK98_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN ((uint32_t)0x00000004) /*!< When 1, enables Bank98 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN_OFS ( 3) /*!< BNK99_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN ((uint32_t)0x00000008) /*!< When 1, enables Bank99 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN_OFS ( 4) /*!< BNK100_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN ((uint32_t)0x00000010) /*!< When 1, enables Bank100 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN_OFS ( 5) /*!< BNK101_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN ((uint32_t)0x00000020) /*!< When 1, enables Bank101 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN_OFS ( 6) /*!< BNK102_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN ((uint32_t)0x00000040) /*!< When 1, enables Bank102 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN_OFS ( 7) /*!< BNK103_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN ((uint32_t)0x00000080) /*!< When 1, enables Bank103 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN_OFS ( 8) /*!< BNK104_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN ((uint32_t)0x00000100) /*!< When 1, enables Bank104 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN_OFS ( 9) /*!< BNK105_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN ((uint32_t)0x00000200) /*!< When 1, enables Bank105 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN_OFS (10) /*!< BNK106_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN ((uint32_t)0x00000400) /*!< When 1, enables Bank106 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN_OFS (11) /*!< BNK107_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN ((uint32_t)0x00000800) /*!< When 1, enables Bank107 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN_OFS (12) /*!< BNK108_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN ((uint32_t)0x00001000) /*!< When 1, enables Bank108 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN_OFS (13) /*!< BNK109_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN ((uint32_t)0x00002000) /*!< When 1, enables Bank109 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN_OFS (14) /*!< BNK110_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN ((uint32_t)0x00004000) /*!< When 1, enables Bank110 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN_OFS (15) /*!< BNK111_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN ((uint32_t)0x00008000) /*!< When 1, enables Bank111 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN_OFS (16) /*!< BNK112_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN ((uint32_t)0x00010000) /*!< When 1, enables Bank112 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN_OFS (17) /*!< BNK113_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN ((uint32_t)0x00020000) /*!< When 1, enables Bank113 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN_OFS (18) /*!< BNK114_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN ((uint32_t)0x00040000) /*!< When 1, enables Bank114 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN_OFS (19) /*!< BNK115_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN ((uint32_t)0x00080000) /*!< When 1, enables Bank115 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN_OFS (20) /*!< BNK116_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN ((uint32_t)0x00100000) /*!< When 1, enables Bank116 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN_OFS (21) /*!< BNK117_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN ((uint32_t)0x00200000) /*!< When 1, enables Bank117 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN_OFS (22) /*!< BNK118_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN ((uint32_t)0x00400000) /*!< When 1, enables Bank118 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN_OFS (23) /*!< BNK119_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN ((uint32_t)0x00800000) /*!< When 1, enables Bank119 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN_OFS (24) /*!< BNK120_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN ((uint32_t)0x01000000) /*!< When 1, enables Bank120 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN_OFS (25) /*!< BNK121_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN ((uint32_t)0x02000000) /*!< When 1, enables Bank121 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN_OFS (26) /*!< BNK122_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN ((uint32_t)0x04000000) /*!< When 1, enables Bank122 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN_OFS (27) /*!< BNK123_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN ((uint32_t)0x08000000) /*!< When 1, enables Bank123 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN_OFS (28) /*!< BNK124_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN ((uint32_t)0x10000000) /*!< When 1, enables Bank124 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN_OFS (29) /*!< BNK125_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN ((uint32_t)0x20000000) /*!< When 1, enables Bank125 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN_OFS (30) /*!< BNK126_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN ((uint32_t)0x40000000) /*!< When 1, enables Bank126 of the SRAM */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN_OFS (31) /*!< BNK127_EN Bit Offset */ -#define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN ((uint32_t)0x80000000) /*!< When 1, enables Bank127 of the SRAM */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN_OFS ( 0) /*!< BLK0_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN ((uint32_t)0x00000001) /*!< Block0 is always retained in LPM3, LPM4 and LPM3.5 modes of operation */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN_OFS ( 1) /*!< BLK1_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN ((uint32_t)0x00000002) /*!< When 1, Block1 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN_OFS ( 2) /*!< BLK2_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN ((uint32_t)0x00000004) /*!< When 1, Block2 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN_OFS ( 3) /*!< BLK3_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN ((uint32_t)0x00000008) /*!< When 1, Block3 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN_OFS ( 4) /*!< BLK4_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN ((uint32_t)0x00000010) /*!< When 1, Block4 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN_OFS ( 5) /*!< BLK5_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN ((uint32_t)0x00000020) /*!< When 1, Block5 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN_OFS ( 6) /*!< BLK6_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN ((uint32_t)0x00000040) /*!< When 1, Block6 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN_OFS ( 7) /*!< BLK7_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN ((uint32_t)0x00000080) /*!< When 1, Block7 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN_OFS ( 8) /*!< BLK8_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN ((uint32_t)0x00000100) /*!< When 1, Block8 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN_OFS ( 9) /*!< BLK9_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN ((uint32_t)0x00000200) /*!< When 1, Block9 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN_OFS (10) /*!< BLK10_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN ((uint32_t)0x00000400) /*!< When 1, Block10 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN_OFS (11) /*!< BLK11_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN ((uint32_t)0x00000800) /*!< When 1, Block11 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN_OFS (12) /*!< BLK12_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN ((uint32_t)0x00001000) /*!< When 1, Block12 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN_OFS (13) /*!< BLK13_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN ((uint32_t)0x00002000) /*!< When 1, Block13 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN_OFS (14) /*!< BLK14_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN ((uint32_t)0x00004000) /*!< When 1, Block14 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN_OFS (15) /*!< BLK15_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN ((uint32_t)0x00008000) /*!< When 1, Block15 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN_OFS (16) /*!< BLK16_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN ((uint32_t)0x00010000) /*!< When 1, Block16 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN_OFS (17) /*!< BLK17_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN ((uint32_t)0x00020000) /*!< When 1, Block17 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN_OFS (18) /*!< BLK18_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN ((uint32_t)0x00040000) /*!< When 1, Block18 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN_OFS (19) /*!< BLK19_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN ((uint32_t)0x00080000) /*!< When 1, Block19 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN_OFS (20) /*!< BLK20_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN ((uint32_t)0x00100000) /*!< When 1, Block20 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN_OFS (21) /*!< BLK21_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN ((uint32_t)0x00200000) /*!< When 1, Block21 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN_OFS (22) /*!< BLK22_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN ((uint32_t)0x00400000) /*!< When 1, Block22 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN_OFS (23) /*!< BLK23_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN ((uint32_t)0x00800000) /*!< When 1, Block23 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN_OFS (24) /*!< BLK24_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN ((uint32_t)0x01000000) /*!< When 1, Block24 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN_OFS (25) /*!< BLK25_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN ((uint32_t)0x02000000) /*!< When 1, Block25 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN_OFS (26) /*!< BLK26_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN ((uint32_t)0x04000000) /*!< When 1, Block26 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN_OFS (27) /*!< BLK27_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN ((uint32_t)0x08000000) /*!< When 1, Block27 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN_OFS (28) /*!< BLK28_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN ((uint32_t)0x10000000) /*!< When 1, Block28 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN_OFS (29) /*!< BLK29_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN ((uint32_t)0x20000000) /*!< When 1, Block29 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN_OFS (30) /*!< BLK30_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN ((uint32_t)0x40000000) /*!< When 1, Block30 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN_OFS (31) /*!< BLK31_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN ((uint32_t)0x80000000) /*!< When 1, Block31 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN_OFS ( 0) /*!< BLK32_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN ((uint32_t)0x00000001) /*!< When 1, Block32 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN_OFS ( 1) /*!< BLK33_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN ((uint32_t)0x00000002) /*!< When 1, Block33 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN_OFS ( 2) /*!< BLK34_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN ((uint32_t)0x00000004) /*!< When 1, Block34 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN_OFS ( 3) /*!< BLK35_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN ((uint32_t)0x00000008) /*!< When 1, Block35 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN_OFS ( 4) /*!< BLK36_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN ((uint32_t)0x00000010) /*!< When 1, Block36 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN_OFS ( 5) /*!< BLK37_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN ((uint32_t)0x00000020) /*!< When 1, Block37 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN_OFS ( 6) /*!< BLK38_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN ((uint32_t)0x00000040) /*!< When 1, Block38 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN_OFS ( 7) /*!< BLK39_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN ((uint32_t)0x00000080) /*!< When 1, Block39 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN_OFS ( 8) /*!< BLK40_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN ((uint32_t)0x00000100) /*!< When 1, Block40 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN_OFS ( 9) /*!< BLK41_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN ((uint32_t)0x00000200) /*!< When 1, Block41 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN_OFS (10) /*!< BLK42_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN ((uint32_t)0x00000400) /*!< When 1, Block42 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN_OFS (11) /*!< BLK43_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN ((uint32_t)0x00000800) /*!< When 1, Block43 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN_OFS (12) /*!< BLK44_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN ((uint32_t)0x00001000) /*!< When 1, Block44 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN_OFS (13) /*!< BLK45_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN ((uint32_t)0x00002000) /*!< When 1, Block45 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN_OFS (14) /*!< BLK46_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN ((uint32_t)0x00004000) /*!< When 1, Block46 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN_OFS (15) /*!< BLK47_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN ((uint32_t)0x00008000) /*!< When 1, Block47 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN_OFS (16) /*!< BLK48_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN ((uint32_t)0x00010000) /*!< When 1, Block48 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN_OFS (17) /*!< BLK49_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN ((uint32_t)0x00020000) /*!< When 1, Block49 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN_OFS (18) /*!< BLK50_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN ((uint32_t)0x00040000) /*!< When 1, Block50 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN_OFS (19) /*!< BLK51_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN ((uint32_t)0x00080000) /*!< When 1, Block51 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN_OFS (20) /*!< BLK52_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN ((uint32_t)0x00100000) /*!< When 1, Block52 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN_OFS (21) /*!< BLK53_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN ((uint32_t)0x00200000) /*!< When 1, Block53 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN_OFS (22) /*!< BLK54_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN ((uint32_t)0x00400000) /*!< When 1, Block54 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN_OFS (23) /*!< BLK55_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN ((uint32_t)0x00800000) /*!< When 1, Block55 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN_OFS (24) /*!< BLK56_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN ((uint32_t)0x01000000) /*!< When 1, Block56 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN_OFS (25) /*!< BLK57_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN ((uint32_t)0x02000000) /*!< When 1, Block57 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN_OFS (26) /*!< BLK58_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN ((uint32_t)0x04000000) /*!< When 1, Block58 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN_OFS (27) /*!< BLK59_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN ((uint32_t)0x08000000) /*!< When 1, Block59 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN_OFS (28) /*!< BLK60_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN ((uint32_t)0x10000000) /*!< When 1, Block60 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN_OFS (29) /*!< BLK61_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN ((uint32_t)0x20000000) /*!< When 1, Block61 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN_OFS (30) /*!< BLK62_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN ((uint32_t)0x40000000) /*!< When 1, Block62 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN_OFS (31) /*!< BLK63_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN ((uint32_t)0x80000000) /*!< When 1, Block63 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN_OFS ( 0) /*!< BLK64_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN ((uint32_t)0x00000001) /*!< When 1, Block64 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN_OFS ( 1) /*!< BLK65_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN ((uint32_t)0x00000002) /*!< When 1, Block65 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN_OFS ( 2) /*!< BLK66_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN ((uint32_t)0x00000004) /*!< When 1, Block66 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN_OFS ( 3) /*!< BLK67_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN ((uint32_t)0x00000008) /*!< When 1, Block67 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN_OFS ( 4) /*!< BLK68_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN ((uint32_t)0x00000010) /*!< When 1, Block68 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN_OFS ( 5) /*!< BLK69_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN ((uint32_t)0x00000020) /*!< When 1, Block69 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN_OFS ( 6) /*!< BLK70_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN ((uint32_t)0x00000040) /*!< When 1, Block70 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN_OFS ( 7) /*!< BLK71_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN ((uint32_t)0x00000080) /*!< When 1, Block71 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN_OFS ( 8) /*!< BLK72_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN ((uint32_t)0x00000100) /*!< When 1, Block72 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN_OFS ( 9) /*!< BLK73_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN ((uint32_t)0x00000200) /*!< When 1, Block73 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN_OFS (10) /*!< BLK74_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN ((uint32_t)0x00000400) /*!< When 1, Block74 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN_OFS (11) /*!< BLK75_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN ((uint32_t)0x00000800) /*!< When 1, Block75 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN_OFS (12) /*!< BLK76_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN ((uint32_t)0x00001000) /*!< When 1, Block76 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN_OFS (13) /*!< BLK77_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN ((uint32_t)0x00002000) /*!< When 1, Block77 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN_OFS (14) /*!< BLK78_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN ((uint32_t)0x00004000) /*!< When 1, Block78 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN_OFS (15) /*!< BLK79_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN ((uint32_t)0x00008000) /*!< When 1, Block79 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN_OFS (16) /*!< BLK80_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN ((uint32_t)0x00010000) /*!< When 1, Block80 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN_OFS (17) /*!< BLK81_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN ((uint32_t)0x00020000) /*!< When 1, Block81 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN_OFS (18) /*!< BLK82_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN ((uint32_t)0x00040000) /*!< When 1, Block82 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN_OFS (19) /*!< BLK83_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN ((uint32_t)0x00080000) /*!< When 1, Block83 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN_OFS (20) /*!< BLK84_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN ((uint32_t)0x00100000) /*!< When 1, Block84 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN_OFS (21) /*!< BLK85_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN ((uint32_t)0x00200000) /*!< When 1, Block85 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN_OFS (22) /*!< BLK86_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN ((uint32_t)0x00400000) /*!< When 1, Block86 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN_OFS (23) /*!< BLK87_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN ((uint32_t)0x00800000) /*!< When 1, Block87 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN_OFS (24) /*!< BLK88_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN ((uint32_t)0x01000000) /*!< When 1, Block88 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN_OFS (25) /*!< BLK89_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN ((uint32_t)0x02000000) /*!< When 1, Block89 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN_OFS (26) /*!< BLK90_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN ((uint32_t)0x04000000) /*!< When 1, Block90 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN_OFS (27) /*!< BLK91_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN ((uint32_t)0x08000000) /*!< When 1, Block91 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN_OFS (28) /*!< BLK92_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN ((uint32_t)0x10000000) /*!< When 1, Block92 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN_OFS (29) /*!< BLK93_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN ((uint32_t)0x20000000) /*!< When 1, Block93 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN_OFS (30) /*!< BLK94_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN ((uint32_t)0x40000000) /*!< When 1, Block94 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN_OFS (31) /*!< BLK95_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN ((uint32_t)0x80000000) /*!< When 1, Block95 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN_OFS ( 0) /*!< BLK96_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN ((uint32_t)0x00000001) /*!< When 1, Block96 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN_OFS ( 1) /*!< BLK97_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN ((uint32_t)0x00000002) /*!< When 1, Block97 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN_OFS ( 2) /*!< BLK98_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN ((uint32_t)0x00000004) /*!< When 1, Block98 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN_OFS ( 3) /*!< BLK99_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN ((uint32_t)0x00000008) /*!< When 1, Block99 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN_OFS ( 4) /*!< BLK100_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN ((uint32_t)0x00000010) /*!< When 1, Block100 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN_OFS ( 5) /*!< BLK101_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN ((uint32_t)0x00000020) /*!< When 1, Block101 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN_OFS ( 6) /*!< BLK102_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN ((uint32_t)0x00000040) /*!< When 1, Block102 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN_OFS ( 7) /*!< BLK103_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN ((uint32_t)0x00000080) /*!< When 1, Block103 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN_OFS ( 8) /*!< BLK104_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN ((uint32_t)0x00000100) /*!< When 1, Block104 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN_OFS ( 9) /*!< BLK105_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN ((uint32_t)0x00000200) /*!< When 1, Block105 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN_OFS (10) /*!< BLK106_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN ((uint32_t)0x00000400) /*!< When 1, Block106 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN_OFS (11) /*!< BLK107_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN ((uint32_t)0x00000800) /*!< When 1, Block107 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN_OFS (12) /*!< BLK108_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN ((uint32_t)0x00001000) /*!< When 1, Block108 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN_OFS (13) /*!< BLK109_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN ((uint32_t)0x00002000) /*!< When 1, Block109 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN_OFS (14) /*!< BLK110_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN ((uint32_t)0x00004000) /*!< When 1, Block110 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN_OFS (15) /*!< BLK111_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN ((uint32_t)0x00008000) /*!< When 1, Block111 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN_OFS (16) /*!< BLK112_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN ((uint32_t)0x00010000) /*!< When 1, Block112 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN_OFS (17) /*!< BLK113_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN ((uint32_t)0x00020000) /*!< When 1, Block113 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN_OFS (18) /*!< BLK114_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN ((uint32_t)0x00040000) /*!< When 1, Block114 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN_OFS (19) /*!< BLK115_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN ((uint32_t)0x00080000) /*!< When 1, Block115 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN_OFS (20) /*!< BLK116_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN ((uint32_t)0x00100000) /*!< When 1, Block116 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN_OFS (21) /*!< BLK117_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN ((uint32_t)0x00200000) /*!< When 1, Block117 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN_OFS (22) /*!< BLK118_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN ((uint32_t)0x00400000) /*!< When 1, Block118 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN_OFS (23) /*!< BLK119_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN ((uint32_t)0x00800000) /*!< When 1, Block119 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN_OFS (24) /*!< BLK120_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN ((uint32_t)0x01000000) /*!< When 1, Block120 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN_OFS (25) /*!< BLK121_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN ((uint32_t)0x02000000) /*!< When 1, Block121 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN_OFS (26) /*!< BLK122_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN ((uint32_t)0x04000000) /*!< When 1, Block122 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN_OFS (27) /*!< BLK123_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN ((uint32_t)0x08000000) /*!< When 1, Block123 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN_OFS (28) /*!< BLK124_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN ((uint32_t)0x10000000) /*!< When 1, Block124 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN_OFS (29) /*!< BLK125_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN ((uint32_t)0x20000000) /*!< When 1, Block125 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN_OFS (30) /*!< BLK126_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN ((uint32_t)0x40000000) /*!< When 1, Block126 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN_OFS (31) /*!< BLK127_EN Bit Offset */ -#define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN ((uint32_t)0x80000000) /*!< When 1, Block127 of the SRAM is retained in LPM3 and LPM4 */ -#define SYSCTL_A_SRAM_STAT_BNKEN_RDY_OFS ( 0) /*!< BNKEN_RDY Bit Offset */ -#define SYSCTL_A_SRAM_STAT_BNKEN_RDY ((uint32_t)0x00000001) /*!< When 1, indicates SRAM is ready for access and banks can be */ -#define SYSCTL_A_SRAM_STAT_BLKRET_RDY_OFS ( 1) /*!< BLKRET_RDY Bit Offset */ -#define SYSCTL_A_SRAM_STAT_BLKRET_RDY ((uint32_t)0x00000002) /*!< When 1, indicates SRAM is ready for access and blocks can be */ -#define SYSCTL_A_MASTER_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ -#define SYSCTL_A_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ -#define SYSCTL_A_RESET_REQ_POR_OFS ( 0) /*!< POR Bit Offset */ -#define SYSCTL_A_RESET_REQ_POR ((uint32_t)0x00000001) /*!< Generate POR */ -#define SYSCTL_A_RESET_REQ_REBOOT_OFS ( 1) /*!< REBOOT Bit Offset */ -#define SYSCTL_A_RESET_REQ_REBOOT ((uint32_t)0x00000002) /*!< Generate Reboot_Reset */ -#define SYSCTL_A_RESET_REQ_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ -#define SYSCTL_A_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ -#define SYSCTL_A_RESET_STATOVER_SOFT_OFS ( 0) /*!< SOFT Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /*!< Indicates if SOFT Reset is active */ -#define SYSCTL_A_RESET_STATOVER_HARD_OFS ( 1) /*!< HARD Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_HARD ((uint32_t)0x00000002) /*!< Indicates if HARD Reset is active */ -#define SYSCTL_A_RESET_STATOVER_REBOOT_OFS ( 2) /*!< REBOOT Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /*!< Indicates if Reboot Reset is active */ -#define SYSCTL_A_RESET_STATOVER_SOFT_OVER_OFS ( 8) /*!< SOFT_OVER Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /*!< SOFT_Reset overwrite request */ -#define SYSCTL_A_RESET_STATOVER_HARD_OVER_OFS ( 9) /*!< HARD_OVER Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /*!< HARD_Reset overwrite request */ -#define SYSCTL_A_RESET_STATOVER_RBT_OVER_OFS (10) /*!< RBT_OVER Bit Offset */ -#define SYSCTL_A_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /*!< Reboot Reset overwrite request */ -#define SYSCTL_A_CSYS_MASTER_UNLOCK_UNLKEY_VAL ((uint32_t)0x0000695A) /*!< Unlock key value which when written, determines if accesses to other CPU_SYS register */ -#define SYSCTL_A_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ -#define SYSCTL_A_BOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ -#define SYSCTL_A_ETW_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to validate write to bit 0 */ -#define SYSCTL_A_SECDATA_UNLOCK_KEY_VAL ((uint32_t)0x0000695A) /*!< Unlock Key value, which requests for secure data region to be unlocked for data access */ - - -/****************************************************************************** -* BSL * -******************************************************************************/ -#define BSL_DEFAULT_PARAM ((uint32_t)0xFC48FFFF) /*!< I2C slave address = 0x48, Interface selection = Auto */ -#define BSL_API_TABLE_ADDR ((uint32_t)0x00202000) /*!< Address of BSL API table */ -#define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR)) - -#define BSL_AUTO_INTERFACE ((uint32_t)0x0000E0000) /*!< Auto detect interface */ -#define BSL_UART_INTERFACE ((uint32_t)0x0000C0000) /*!< UART interface */ -#define BSL_SPI_INTERFACE ((uint32_t)0x0000A0000) /*!< SPI interface */ -#define BSL_I2C_INTERFACE ((uint32_t)0x000080000) /*!< I2C interface */ - -#define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */ - - -/****************************************************************************** -* Mailbox struct legacy definition * -******************************************************************************/ -#define FLASH_MAILBOX_Type FL_BOOTOVER_MAILBOX_Type - -/****************************************************************************** -* Device Unlock Support * -******************************************************************************/ -/* unlock the device by: - * Load SYSCTL_SECDATA_UNLOCK register address into R0 - * Load SYSCTL_SECDATA_UNLOCK unlock key into R1 - * Write the unlock key to the SYSCTL_SECDATA_UNLOCK register - */ -#define UNLOCK_DEVICE\ - __asm(" MOVW.W R0, #0x3040");\ - __asm(" MOVT.W R0, #0xE004");\ - __asm(" MOVW.W R1, #0x695A");\ - __asm(" MOVT.W R1, #0x0000");\ - __asm(" STR R1, [R0]"); - -/****************************************************************************** -* -* The following are values that can be used to choose the command that will be -* run by the boot code. Perform a logical OR of these settings to create your -* general parameter command. -* -******************************************************************************/ -#define COMMAND_FACTORY_RESET ((uint32_t)0x00010000) -#define COMMAND_BSL_CONFIG ((uint32_t)0x00020000) -#define COMMAND_JTAG_SWD_LOCK_SECEN ((uint32_t)0x00080000) -#define COMMAND_SEC_ZONE0_EN ((uint32_t)0x00100000) -#define COMMAND_SEC_ZONE1_EN ((uint32_t)0x00200000) -#define COMMAND_SEC_ZONE2_EN ((uint32_t)0x00400000) -#define COMMAND_SEC_ZONE3_EN ((uint32_t)0x00800000) -#define COMMAND_SEC_ZONE0_UPDATE ((uint32_t)0x01000000) -#define COMMAND_SEC_ZONE1_UPDATE ((uint32_t)0x02000000) -#define COMMAND_SEC_ZONE2_UPDATE ((uint32_t)0x04000000) -#define COMMAND_SEC_ZONE3_UPDATE ((uint32_t)0x08000000) -#define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE ((uint32_t)0x10000000) -#define COMMAND_NONE ((uint32_t)0xFFFFFFFF) - -/****************************************************************************** -* -* The following are values that can be used to configure the BSL. Perform a -* logical OR of these settings to create your BSL parameter. -* -******************************************************************************/ -#define BSL_CONFIG_HW_INVOKE ((uint32_t)0x70000000) - -#define BSL_CONFIG_HW_INVOKE_PORT1 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PORT2 ((uint32_t)0x00000001) -#define BSL_CONFIG_HW_INVOKE_PORT3 ((uint32_t)0x00000002) - -#define BSL_CONFIG_HW_INVOKE_PIN0 ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN1 ((uint32_t)0x00000010) -#define BSL_CONFIG_HW_INVOKE_PIN2 ((uint32_t)0x00000020) -#define BSL_CONFIG_HW_INVOKE_PIN3 ((uint32_t)0x00000030) -#define BSL_CONFIG_HW_INVOKE_PIN4 ((uint32_t)0x00000040) -#define BSL_CONFIG_HW_INVOKE_PIN5 ((uint32_t)0x00000050) -#define BSL_CONFIG_HW_INVOKE_PIN6 ((uint32_t)0x00000060) -#define BSL_CONFIG_HW_INVOKE_PIN7 ((uint32_t)0x00000070) - -#define BSL_CONFIG_HW_INVOKE_PIN_LOW ((uint32_t)0x00000000) -#define BSL_CONFIG_HW_INVOKE_PIN_HIGH ((uint32_t)0x00001000) - -#define BSL_CONFIG_INTERFACE_I2C ((uint32_t)0x00008000) -#define BSL_CONFIG_INTERFACE_SPI ((uint32_t)0x0000A000) -#define BSL_CONFIG_INTERFACE_UART ((uint32_t)0x0000C000) -#define BSL_CONFIG_INTERFACE_AUTO ((uint32_t)0x0000E000) - -#define BSL_CONFIG_I2C_ADD_OFFSET (16) - - -/****************************************************************************** -* ULP Advisor * -******************************************************************************/ -#ifdef __TI_ARM__ -#pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8}) -#pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8}) -#pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8}) -#pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8}) -#pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8}) -#pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8}) -#pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8}) -#pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8}) -#pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8}) -#pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8}) -#endif - - -#ifdef __cplusplus -} -#endif - -#endif /* __MSP432P4XX_H__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp_compatibility.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp_compatibility.h deleted file mode 100644 index 5e29e527b4d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/msp_compatibility.h +++ /dev/null @@ -1,325 +0,0 @@ -//***************************************************************************** -// -// Copyright (C) 2013 - 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// MSP430 intrinsic redefinitions for use with MSP432 Family Devices -// -//**************************************************************************** - -/****************************************************************************** -* Definitions for 8/16/32-bit wide memory access * -******************************************************************************/ -#define HWREG8(x) (*((volatile uint8_t *)(x))) -#define HWREG16(x) (*((volatile uint16_t *)(x))) -#define HWREG32(x) (*((volatile uint32_t *)(x))) -#define HWREG(x) (HWREG16(x)) -#define HWREG8_L(x) (*((volatile uint8_t *)((uint8_t *)&x))) -#define HWREG8_H(x) (*((volatile uint8_t *)(((uint8_t *)&x)+1))) -#define HWREG16_L(x) (*((volatile uint16_t *)((uint16_t *)&x))) -#define HWREG16_H(x) (*((volatile uint16_t *)(((uint16_t *)&x)+1))) - -/****************************************************************************** -* Definitions for 8/16/32-bit wide bit band access * -******************************************************************************/ -#define HWREGBIT8(x, b) (HWREG8(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))) -#define HWREGBIT16(x, b) (HWREG16(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))) -#define HWREGBIT32(x, b) (HWREG32(((uint32_t)(x) & 0xF0000000) | 0x02000000 | (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))) - -// Intrinsics with ARM equivalents -#if defined ( __TI_ARM__ ) /* TI CGT Compiler */ - -#include - -#define __sleep() __wfi() -#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } -#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } -#define __get_SP_register() __get_MSP() -#define __set_SP_register(x) __set_MSP(x) -#define __get_interrupt_state() __get_PRIMASK() -#define __set_interrupt_state(x) __set_PRIMASK(x) -#define __enable_interrupt() _enable_IRQ() -#define __enable_interrupts() _enable_IRQ() -#define __disable_interrupt() _disable_IRQ() -#define __disable_interrupts() _disable_IRQ() -#define __no_operation() __asm(" nop") - -#elif defined ( __ICCARM__ ) /* IAR Compiler */ - -#include - -#define __INLINE inline -#include - -#define __sleep() __WFI() -#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __WFI(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } -#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } -#define __get_SP_register() __get_MSP() -#define __set_SP_register() __set_MSP() -#define __get_interrupt_state() __get_PRIMASK() -#define __set_interrupt_state(x) __set_PRIMASK(x) -#define __enable_interrupt() __asm(" cpsie i") -#define __enable_interrupts() __asm(" cpsie i") -#define __disable_interrupt() __asm(" cpsid i") -#define __disable_interrupts() __asm(" cpsid i") -#define __no_operation() __asm(" nop") - -// Intrinsics without ARM equivalents -#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } -#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } -#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ } - -#elif defined ( __CC_ARM ) /* ARM Compiler */ - -#define __sleep() __wfi() -#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } -#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } -#define __get_SP_register() __get_MSP() -#define __set_SP_register(x) __set_MSP(x) -#define __get_interrupt_state() __get_PRIMASK() -#define __set_interrupt_state(x) __set_PRIMASK(x) -#define __enable_interrupt() __asm(" cpsie i") -#define __enable_interrupts() __asm(" cpsie i") -#define __disable_interrupt() __asm(" cpsid i") -#define __disable_interrupts() __asm(" cpsid i") -#define __no_operation() __asm(" nop") - -// Intrinsics without ARM equivalents -#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } -#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } -#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ } - -#elif defined ( __GNUC__ ) /* GCC Compiler */ -#undef __wfi -#define __wfi() __asm(" wfi") -#define __sleep() __wfi() -#define __deep_sleep() { (*((volatile uint32_t *)(0xE000ED10))) |= 0x00000004; __wfi(); (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000004; } -#define __low_power_mode_off_on_exit() { (*((volatile uint32_t *)(0xE000ED10))) &= ~0x00000002; } -#define __get_SP_register() __get_MSP() -#define __set_SP_register(x) __set_MSP(x) -#define __get_interrupt_state() __get_PRIMASK() -#define __set_interrupt_state(x) __set_PRIMASK(x) -#define __enable_interrupt() __asm(" cpsie i") -#define __enable_interrupts() __asm(" cpsie i") -#define __disable_interrupt() __asm(" cpsid i") -#define __disable_interrupts() __asm(" cpsid i") -#define __no_operation() __asm(" nop") - -// Intrinsics without ARM equivalents -#define __bcd_add_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bcd_add_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bcd_add_long_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __even_in_range(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_char(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_short(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __data20_write_long(x,y) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __never_executed() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __op_code() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __code_distance() { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bic_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bis_SR_register(x) { while(1); /* Using not-supported MSP430 intrinsic. No replacement available. */ } -#define __bis_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } -#define __bic_SR_register_on_exit(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to write to SCS_SCR register. */ } -#define __delay_cycles(x) { while(1); /* Using not-supported MSP430 intrinsic. Recommended to use a timer or a custom for loop. */ } - -#endif - -// Intrinsics without ARM equivalents -#define __low_power_mode_0() { __sleep(); } -#define __low_power_mode_1() { __sleep(); } -#define __low_power_mode_2() { __sleep(); } -#define __low_power_mode_3() { __deep_sleep(); } -#define __low_power_mode_4() { __deep_sleep(); } -#define __data16_read_addr(x) (*((volatile uint32_t *)(x))) -#define __data20_read_char(x) (*((volatile uint8_t *)(x))) -#define __data20_read_short(x) (*((volatile uint16_t *)(x))) -#define __data20_read_long(x) (*((volatile uint32_t *)(x))) -#define __data16_write_addr(x,y) { (*((volatile uint32_t *)(x))) } -#define __get_SR_register() 0 -#define __get_SR_register_on_exit() 0 - -// the following defines are deprecated and will be removed in future releases -#define ATLBASE ALTBASE -#define CS_CTL1_SELM_7 ((uint32_t)0x00000007) /*!< for future use. Defaults to DCOCLK. Not recommended for use to ensure future */ - /* compatibilities. */ -#define CS_CTL1_SELS_7 ((uint32_t)0x00000070) /*!< for furture use. Defaults to DCOCLK. Do not use to ensure future */ - /* compatibilities. */ -#define CS_CTL1_SELA_3 ((uint32_t)0x00000300) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ - /* compatibilities. */ -#define CS_CTL1_SELA_4 ((uint32_t)0x00000400) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ - /* compatibilities. */ -#define CS_CTL1_SELA_5 ((uint32_t)0x00000500) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ - /* compatibilities. */ -#define CS_CTL1_SELA_6 ((uint32_t)0x00000600) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ - /* compatibilities. */ -#define CS_CTL1_SELA_7 ((uint32_t)0x00000700) /*!< for future use. Defaults to REFOCLK. Not recommended for use to ensure future */ - /* compatibilities. */ - /* CS_CTL2[LFXTAGCOFF] Bits */ -#define CS_CTL2_LFXTAGCOFF_OFS ( 7) /*!< LFXTAGCOFF Bit Offset */ -#define CS_CTL2_LFXTAGCOFF ((uint32_t)0x00000080) /*!< Disables the automatic gain control of the LFXT crystal */ - -/* CS_CTL3[FCNTHF2] Bits */ -#define CS_CTL3_FCNTHF2_OFS ( 8) /*!< FCNTHF2 Bit Offset */ -#define CS_CTL3_FCNTHF2_MASK ((uint32_t)0x00000300) /*!< FCNTHF2 Bit Mask */ -#define CS_CTL3_FCNTHF20 ((uint32_t)0x00000100) /*!< FCNTHF2 Bit 0 */ -#define CS_CTL3_FCNTHF21 ((uint32_t)0x00000200) /*!< FCNTHF2 Bit 1 */ -#define CS_CTL3_FCNTHF2_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF2_1 ((uint32_t)0x00000100) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF2_2 ((uint32_t)0x00000200) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF2_3 ((uint32_t)0x00000300) /*!< 16384 cycles */ -#define CS_CTL3_FCNTHF2__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ -#define CS_CTL3_FCNTHF2__4096 ((uint32_t)0x00000100) /*!< 4096 cycles */ -#define CS_CTL3_FCNTHF2__8192 ((uint32_t)0x00000200) /*!< 8192 cycles */ -#define CS_CTL3_FCNTHF2__16384 ((uint32_t)0x00000300) /*!< 16384 cycles */ -/* CS_CTL3[RFCNTHF2] Bits */ -#define CS_CTL3_RFCNTHF2_OFS (10) /*!< RFCNTHF2 Bit Offset */ -#define CS_CTL3_RFCNTHF2 ((uint32_t)0x00000400) /*!< Reset start fault counter for HFXT2 */ -/* CS_CTL3[FCNTHF2_EN] Bits */ -#define CS_CTL3_FCNTHF2_EN_OFS (11) /*!< FCNTHF2_EN Bit Offset */ -#define CS_CTL3_FCNTHF2_EN ((uint32_t)0x00000800) /*!< Enable start fault counter for HFXT2 */ -/* CS_STAT[HFXT2_ON] Bits */ -#define CS_STAT_HFXT2_ON_OFS ( 3) /*!< HFXT2_ON Bit Offset */ -#define CS_STAT_HFXT2_ON ((uint32_t)0x00000008) /*!< HFXT2 status */ -/* CS_IE[HFXT2IE] Bits */ -#define CS_IE_HFXT2IE_OFS ( 2) /*!< HFXT2IE Bit Offset */ -#define CS_IE_HFXT2IE ((uint32_t)0x00000004) /*!< HFXT2 oscillator fault flag interrupt enable */ -/* CS_IE[FCNTHF2IE] Bits */ -#define CS_IE_FCNTHF2IE_OFS (10) /*!< FCNTHF2IE Bit Offset */ -#define CS_IE_FCNTHF2IE ((uint32_t)0x00000400) /*!< Start fault counter interrupt enable HFXT2 */ -/* CS_IE[PLLOOLIE] Bits */ -#define CS_IE_PLLOOLIE_OFS (12) /*!< PLLOOLIE Bit Offset */ -#define CS_IE_PLLOOLIE ((uint32_t)0x00001000) /*!< PLL out-of-lock interrupt enable */ -/* CS_IE[PLLLOSIE] Bits */ -#define CS_IE_PLLLOSIE_OFS (13) /*!< PLLLOSIE Bit Offset */ -#define CS_IE_PLLLOSIE ((uint32_t)0x00002000) /*!< PLL loss-of-signal interrupt enable */ -/* CS_IE[PLLOORIE] Bits */ -#define CS_IE_PLLOORIE_OFS (14) /*!< PLLOORIE Bit Offset */ -#define CS_IE_PLLOORIE ((uint32_t)0x00004000) /*!< PLL out-of-range interrupt enable */ -/* CS_IE[CALIE] Bits */ -#define CS_IE_CALIE_OFS (15) /*!< CALIE Bit Offset */ -#define CS_IE_CALIE ((uint32_t)0x00008000) /*!< REFCNT period counter interrupt enable */ -/* CS_IFG[HFXT2IFG] Bits */ -#define CS_IFG_HFXT2IFG_OFS ( 2) /*!< HFXT2IFG Bit Offset */ -#define CS_IFG_HFXT2IFG ((uint32_t)0x00000004) /*!< HFXT2 oscillator fault flag */ -/* CS_IFG[FCNTHF2IFG] Bits */ -#define CS_IFG_FCNTHF2IFG_OFS (11) /*!< FCNTHF2IFG Bit Offset */ -#define CS_IFG_FCNTHF2IFG ((uint32_t)0x00000800) /*!< Start fault counter interrupt flag HFXT2 */ -/* CS_IFG[PLLOOLIFG] Bits */ -#define CS_IFG_PLLOOLIFG_OFS (12) /*!< PLLOOLIFG Bit Offset */ -#define CS_IFG_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock interrupt flag */ -/* CS_IFG[PLLLOSIFG] Bits */ -#define CS_IFG_PLLLOSIFG_OFS (13) /*!< PLLLOSIFG Bit Offset */ -#define CS_IFG_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal interrupt flag */ -/* CS_IFG[PLLOORIFG] Bits */ -#define CS_IFG_PLLOORIFG_OFS (14) /*!< PLLOORIFG Bit Offset */ -#define CS_IFG_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range interrupt flag */ -/* CS_IFG[CALIFG] Bits */ -#define CS_IFG_CALIFG_OFS (15) /*!< CALIFG Bit Offset */ -#define CS_IFG_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter expired */ -/* CS_CLRIFG[CLR_HFXT2IFG] Bits */ -#define CS_CLRIFG_CLR_HFXT2IFG_OFS ( 2) /*!< CLR_HFXT2IFG Bit Offset */ -#define CS_CLRIFG_CLR_HFXT2IFG ((uint32_t)0x00000004) /*!< Clear HFXT2 oscillator fault interrupt flag */ -/* CS_CLRIFG[CLR_CALIFG] Bits */ -#define CS_CLRIFG_CLR_CALIFG_OFS (15) /*!< CLR_CALIFG Bit Offset */ -#define CS_CLRIFG_CLR_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter clear interrupt flag */ -/* CS_CLRIFG[CLR_FCNTHF2IFG] Bits */ -#define CS_CLRIFG_CLR_FCNTHF2IFG_OFS (10) /*!< CLR_FCNTHF2IFG Bit Offset */ -#define CS_CLRIFG_CLR_FCNTHF2IFG ((uint32_t)0x00000400) /*!< Start fault counter clear interrupt flag HFXT2 */ -/* CS_CLRIFG[CLR_PLLOOLIFG] Bits */ -#define CS_CLRIFG_CLR_PLLOOLIFG_OFS (12) /*!< CLR_PLLOOLIFG Bit Offset */ -#define CS_CLRIFG_CLR_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock clear interrupt flag */ -/* CS_CLRIFG[CLR_PLLLOSIFG] Bits */ -#define CS_CLRIFG_CLR_PLLLOSIFG_OFS (13) /*!< CLR_PLLLOSIFG Bit Offset */ -#define CS_CLRIFG_CLR_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal clear interrupt flag */ -/* CS_CLRIFG[CLR_PLLOORIFG] Bits */ -#define CS_CLRIFG_CLR_PLLOORIFG_OFS (14) /*!< CLR_PLLOORIFG Bit Offset */ -#define CS_CLRIFG_CLR_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range clear interrupt flag */ -/* CS_SETIFG[SET_HFXT2IFG] Bits */ -#define CS_SETIFG_SET_HFXT2IFG_OFS ( 2) /*!< SET_HFXT2IFG Bit Offset */ -#define CS_SETIFG_SET_HFXT2IFG ((uint32_t)0x00000004) /*!< Set HFXT2 oscillator fault interrupt flag */ -/* CS_SETIFG[SET_CALIFG] Bits */ -#define CS_SETIFG_SET_CALIFG_OFS (15) /*!< SET_CALIFG Bit Offset */ -#define CS_SETIFG_SET_CALIFG ((uint32_t)0x00008000) /*!< REFCNT period counter set interrupt flag */ -/* CS_SETIFG[SET_FCNTHF2IFG] Bits */ -#define CS_SETIFG_SET_FCNTHF2IFG_OFS (10) /*!< SET_FCNTHF2IFG Bit Offset */ -#define CS_SETIFG_SET_FCNTHF2IFG ((uint32_t)0x00000400) /*!< Start fault counter set interrupt flag HFXT2 */ -/* CS_SETIFG[SET_PLLOOLIFG] Bits */ -#define CS_SETIFG_SET_PLLOOLIFG_OFS (12) /*!< SET_PLLOOLIFG Bit Offset */ -#define CS_SETIFG_SET_PLLOOLIFG ((uint32_t)0x00001000) /*!< PLL out-of-lock set interrupt flag */ -/* CS_SETIFG[SET_PLLLOSIFG] Bits */ -#define CS_SETIFG_SET_PLLLOSIFG_OFS (13) /*!< SET_PLLLOSIFG Bit Offset */ -#define CS_SETIFG_SET_PLLLOSIFG ((uint32_t)0x00002000) /*!< PLL loss-of-signal set interrupt flag */ -/* CS_SETIFG[SET_PLLOORIFG] Bits */ -#define CS_SETIFG_SET_PLLOORIFG_OFS (14) /*!< SET_PLLOORIFG Bit Offset */ -#define CS_SETIFG_SET_PLLOORIFG ((uint32_t)0x00004000) /*!< PLL out-of-range set interrupt flag */ - -/* EUSCI_x_CTLW0[SSEL] Bits */ -#define EUSCI_A_CTLW0_SSEL_0 ((uint16_t)0x0000) /*!< Reserved */ -#define EUSCI_B_CTLW0_SSEL_0 ((uint16_t)0x0000) /*!< Reserved */ -#define EUSCI_B_CTLW0_SSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ - -/* RSTCTL_PSSRESET_STAT[SVSL] Bits */ -#define RSTCTL_PSSRESET_STAT_SVSL_OFS ( 0) /*!< SVSL Bit Offset */ -#define RSTCTL_PSSRESET_STAT_SVSL ((uint32_t)0x00000001) /*!< Indicates if POR was caused by an SVSL trip condition in the PSS */ - -/* SYSCTL_SYSTEM_STAT[DBG_SEC_ACT] Bits */ -#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT_OFS ( 3) /*!< DBG_SEC_ACT Bit Offset */ -#define SYSCTL_SYSTEM_STAT_DBG_SEC_ACT ((uint32_t)0x00000008) /*!< Debug Security active */ -/* SYSCTL_SYSTEM_STAT[JTAG_SWD_LOCK_ACT] Bits */ -#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT_OFS ( 4) /*!< JTAG_SWD_LOCK_ACT Bit Offset */ -#define SYSCTL_SYSTEM_STAT_JTAG_SWD_LOCK_ACT ((uint32_t)0x00000010) /*!< Indicates if JTAG and SWD Lock is active */ -/* SYSCTL_SYSTEM_STAT[IP_PROT_ACT] Bits */ -#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT_OFS ( 5) /*!< IP_PROT_ACT Bit Offset */ -#define SYSCTL_SYSTEM_STAT_IP_PROT_ACT ((uint32_t)0x00000020) /*!< Indicates if IP protection is active */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p401m.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p401m.h deleted file mode 100644 index 4f2c0a5d686..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p401m.h +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************//** -* @file system_msp432p401m.h -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Header File for -* MSP432P401M -* @version 3.202 -* @date 08/03/17 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#ifndef SYSTEM_MSP432P401M_H -#define SYSTEM_MSP432P401M_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT - * 3. Enables all SRAM banks - * 4. Sets up power __REGULATOR and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_MSP432P401M_H */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p401r.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p401r.h deleted file mode 100644 index 09648a63901..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p401r.h +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************//** -* @file system_msp432p401r.h -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Header File for -* MSP432P401R -* @version 3.202 -* @date 08/03/17 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#ifndef SYSTEM_MSP432P401R_H -#define SYSTEM_MSP432P401R_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT - * 3. Enables all SRAM banks - * 4. Sets up power __REGULATOR and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_MSP432P401R_H */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p4111.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p4111.h deleted file mode 100644 index ea480e78bdd..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p4111.h +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************//** -* @file system_msp432p4111.h -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Header File for -* MSP432P4111 -* @version 3.202 -* @date 08/03/17 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#ifndef SYSTEM_MSP432P4111_H -#define SYSTEM_MSP432P4111_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT - * 3. Enables all SRAM banks - * 4. Sets up power __REGULATOR and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_MSP432P4111_H */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p411v.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p411v.h deleted file mode 100644 index 324259939b1..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p411v.h +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************//** -* @file system_msp432p411v.h -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Header File for -* MSP432P411V -* @version 3.202 -* @date 08/03/17 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#ifndef SYSTEM_MSP432P411V_H -#define SYSTEM_MSP432P411V_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT - * 3. Enables all SRAM banks - * 4. Sets up power __REGULATOR and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_MSP432P411V_H */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p411y.h b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p411y.h deleted file mode 100644 index 71d5b619644..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/inc/system_msp432p411y.h +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************//** -* @file system_msp432p411y.h -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Header File for -* MSP432P411Y -* @version 3.202 -* @date 08/03/17 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#ifndef SYSTEM_MSP432P411Y_H -#define SYSTEM_MSP432P411Y_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT - * 3. Enables all SRAM banks - * 4. Sets up power __REGULATOR and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_MSP432P411Y_H */ - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401m.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401m.c deleted file mode 100644 index a3a8c409162..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401m.c +++ /dev/null @@ -1,406 +0,0 @@ -/****************************************************************************** -* @file system_msp432p401m.c -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for -* MSP432P401M -* @version 3.202 -* @date 08/03/17 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#include -#include -#include - -/*--------------------- Configuration Instructions ---------------------------- - 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: - #define __HALT_WDT 1 - 2. Insert your desired CPU frequency in Hz at: - #define __SYSTEM_CLOCK 12000000 - 3. If you prefer the DC-DC power regulator (more efficient at higher - frequencies), set the __REGULATOR to 1: - #define __REGULATOR 1 - *---------------------------------------------------------------------------*/ - -/*--------------------- Watchdog Timer Configuration ------------------------*/ -// Halt the Watchdog Timer -// <0> Do not halt the WDT -// <1> Halt the WDT -#define __HALT_WDT 1 - -/*--------------------- CPU Frequency Configuration -------------------------*/ -// CPU Frequency -// <1500000> 1.5 MHz -// <3000000> 3 MHz -// <12000000> 12 MHz -// <24000000> 24 MHz -// <48000000> 48 MHz -#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY - -/*--------------------- Power Regulator Configuration -----------------------*/ -// Power Regulator Mode -// <0> LDO -// <1> DC-DC -#define __REGULATOR 0 - -/*---------------------------------------------------------------------------- - Define clocks, used for SystemCoreClockUpdate() - *---------------------------------------------------------------------------*/ -#define __VLOCLK 10000 -#define __MODCLK 24000000 -#define __LFXT 32768 -#define __HFXT 48000000 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - uint32_t source, divider; - uint8_t dividerValue; - - float dcoConst; - int32_t calVal; - uint32_t centeredFreq; - int16_t dcoTune; - - divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; - dividerValue = 1 << divider; - source = CS->CTL1 & CS_CTL1_SELM_MASK; - - switch(source) - { - case CS_CTL1_SELM__LFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - break; - case CS_CTL1_SELM__VLOCLK: - SystemCoreClock = __VLOCLK / dividerValue; - break; - case CS_CTL1_SELM__REFOCLK: - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - break; - case CS_CTL1_SELM__DCOCLK: - dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; - - switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - centeredFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - centeredFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - centeredFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - centeredFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - centeredFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - centeredFreq = 48000000; - break; - } - - if(dcoTune == 0) - { - SystemCoreClock = centeredFreq; - } - else - { - - if(dcoTune & 0x1000) - { - dcoTune = dcoTune | 0xF000; - } - - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); - calVal = TLV->DCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); - calVal = TLV->DCOIR_FCAL_RSEL04; - } - - SystemCoreClock = (uint32_t) ((centeredFreq) - / (1 - - ((dcoConst * dcoTune) - / (8 * (1 + dcoConst * (768 - calVal)))))); - } - break; - case CS_CTL1_SELM__MODOSC: - SystemCoreClock = __MODCLK / dividerValue; - break; - case CS_CTL1_SELM__HFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT if requested - * 3. Enables all SRAM banks - * 4. Sets up power regulator and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -void SystemInit(void) -{ - // Enable FPU if used - #if (__FPU_USED == 1) // __FPU_USED is defined in core_cm4.h - SCB->CPACR |= ((3UL << 10 * 2) | // Set CP10 Full Access - (3UL << 11 * 2)); // Set CP11 Full Access - #endif - - #if (__HALT_WDT == 1) - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT - #endif - - SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks - - #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 1.5 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz - CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK; - // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - #endif - - // No flash wait states necessary - - // DCO = 3 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz - CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK; - // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 12 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz - CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK; - // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 1 flash wait state (BANK0 VCORE0 max is 12 MHz) - FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1; - FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_1; - - // DCO = 24 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz - CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK; - // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz - // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - - // Switches LDO VCORE1 to DCDC VCORE1 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 1 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) - FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1; - FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_1; - - // DCO = 48 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz - CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK; - // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL | (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - #endif - -} - - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401r.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401r.c deleted file mode 100644 index 6b430f35766..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p401r.c +++ /dev/null @@ -1,406 +0,0 @@ -/****************************************************************************** -* @file system_msp432p401r.c -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for -* MSP432P401R -* @version 3.202 -* @date 08/03/17 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#include -#include -#include - -/*--------------------- Configuration Instructions ---------------------------- - 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: - #define __HALT_WDT 1 - 2. Insert your desired CPU frequency in Hz at: - #define __SYSTEM_CLOCK 12000000 - 3. If you prefer the DC-DC power regulator (more efficient at higher - frequencies), set the __REGULATOR to 1: - #define __REGULATOR 1 - *---------------------------------------------------------------------------*/ - -/*--------------------- Watchdog Timer Configuration ------------------------*/ -// Halt the Watchdog Timer -// <0> Do not halt the WDT -// <1> Halt the WDT -#define __HALT_WDT 1 - -/*--------------------- CPU Frequency Configuration -------------------------*/ -// CPU Frequency -// <1500000> 1.5 MHz -// <3000000> 3 MHz -// <12000000> 12 MHz -// <24000000> 24 MHz -// <48000000> 48 MHz -#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY - -/*--------------------- Power Regulator Configuration -----------------------*/ -// Power Regulator Mode -// <0> LDO -// <1> DC-DC -#define __REGULATOR 0 - -/*---------------------------------------------------------------------------- - Define clocks, used for SystemCoreClockUpdate() - *---------------------------------------------------------------------------*/ -#define __VLOCLK 10000 -#define __MODCLK 24000000 -#define __LFXT 32768 -#define __HFXT 48000000 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - uint32_t source, divider; - uint8_t dividerValue; - - float dcoConst; - int32_t calVal; - uint32_t centeredFreq = 1500000; // Default center freq - int16_t dcoTune; - - divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; - dividerValue = 1 << divider; - source = CS->CTL1 & CS_CTL1_SELM_MASK; - - switch(source) - { - case CS_CTL1_SELM__LFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - break; - case CS_CTL1_SELM__VLOCLK: - SystemCoreClock = __VLOCLK / dividerValue; - break; - case CS_CTL1_SELM__REFOCLK: - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - break; - case CS_CTL1_SELM__DCOCLK: - dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; - - switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - centeredFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - centeredFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - centeredFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - centeredFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - centeredFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - centeredFreq = 48000000; - break; - } - - if(dcoTune == 0) - { - SystemCoreClock = centeredFreq; - } - else - { - - if(dcoTune & 0x1000) - { - dcoTune = dcoTune | 0xF000; - } - - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); - calVal = TLV->DCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); - calVal = TLV->DCOIR_FCAL_RSEL04; - } - - SystemCoreClock = (uint32_t) ((centeredFreq) - / (1 - - ((dcoConst * dcoTune) - / (8 * (1 + dcoConst * (768 - calVal)))))); - } - break; - case CS_CTL1_SELM__MODOSC: - SystemCoreClock = __MODCLK / dividerValue; - break; - case CS_CTL1_SELM__HFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT if requested - * 3. Enables all SRAM banks - * 4. Sets up power regulator and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -void SystemInit(void) -{ - // Enable FPU if used - #if (__FPU_USED == 1) // __FPU_USED is defined in core_cm4.h - SCB->CPACR |= ((3UL << 10 * 2) | // Set CP10 Full Access - (3UL << 11 * 2)); // Set CP11 Full Access - #endif - - #if (__HALT_WDT == 1) - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT - #endif - - SYSCTL->SRAM_BANKEN = SYSCTL_SRAM_BANKEN_BNK7_EN; // Enable all SRAM banks - - #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 1.5 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz - CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK; - // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - #endif - - // No flash wait states necessary - - // DCO = 3 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz - CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK; - // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 12 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz - CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK; - // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 1 flash wait state (BANK0 VCORE0 max is 12 MHz) - FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1; - FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_1; - - // DCO = 24 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz - CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK; - // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz - // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - - // Switches LDO VCORE1 to DCDC VCORE1 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 1 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) - FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1; - FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~FLCTL_BANK1_RDCTL_WAIT_MASK) | FLCTL_BANK1_RDCTL_WAIT_1; - - // DCO = 48 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz - CS->CTL1 = (CS->CTL1 & ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK)) | CS_CTL1_SELM__DCOCLK; - // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL->BANK0_RDCTL = FLCTL->BANK0_RDCTL | (FLCTL_BANK0_RDCTL_BUFD | FLCTL_BANK0_RDCTL_BUFI); - FLCTL->BANK1_RDCTL = FLCTL->BANK1_RDCTL | (FLCTL_BANK1_RDCTL_BUFD | FLCTL_BANK1_RDCTL_BUFI); - #endif - -} - - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p4111.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p4111.c deleted file mode 100644 index c9c29c5ae54..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p4111.c +++ /dev/null @@ -1,410 +0,0 @@ -/****************************************************************************** -* @file system_msp432p4111.c -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for -* MSP432P4111 -* @version 3.202 -* @date 08/03/17 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#include -#include -#include - -/*--------------------- Configuration Instructions ---------------------------- - 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: - #define __HALT_WDT 1 - 2. Insert your desired CPU frequency in Hz at: - #define __SYSTEM_CLOCK 12000000 - 3. If you prefer the DC-DC power regulator (more efficient at higher - frequencies), set the __REGULATOR to 1: - #define __REGULATOR 1 - *---------------------------------------------------------------------------*/ - -/*--------------------- Watchdog Timer Configuration ------------------------*/ -// Halt the Watchdog Timer -// <0> Do not halt the WDT -// <1> Halt the WDT -#define __HALT_WDT 1 - -/*--------------------- CPU Frequency Configuration -------------------------*/ -// CPU Frequency -// <1500000> 1.5 MHz -// <3000000> 3 MHz -// <12000000> 12 MHz -// <24000000> 24 MHz -// <48000000> 48 MHz -#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY - -/*--------------------- Power Regulator Configuration -----------------------*/ -// Power Regulator Mode -// <0> LDO -// <1> DC-DC -#define __REGULATOR 0 - -/*---------------------------------------------------------------------------- - Define clocks, used for SystemCoreClockUpdate() - *---------------------------------------------------------------------------*/ -#define __VLOCLK 10000 -#define __MODCLK 24000000 -#define __LFXT 32768 -#define __HFXT 48000000 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - uint32_t source, divider; - uint8_t dividerValue; - - float dcoConst; - int32_t calVal; - uint32_t centeredFreq; - int16_t dcoTune; - - divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; - dividerValue = 1 << divider; - source = CS->CTL1 & CS_CTL1_SELM_MASK; - - switch(source) - { - case CS_CTL1_SELM__LFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - break; - case CS_CTL1_SELM__VLOCLK: - SystemCoreClock = __VLOCLK / dividerValue; - break; - case CS_CTL1_SELM__REFOCLK: - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - break; - case CS_CTL1_SELM__DCOCLK: - dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; - - switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - centeredFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - centeredFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - centeredFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - centeredFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - centeredFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - centeredFreq = 48000000; - break; - } - - if(dcoTune == 0) - { - SystemCoreClock = centeredFreq; - } - else - { - - if(dcoTune & 0x1000) - { - dcoTune = dcoTune | 0xF000; - } - - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); - calVal = TLV->DCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); - calVal = TLV->DCOIR_FCAL_RSEL04; - } - - SystemCoreClock = (uint32_t) ((centeredFreq) - / (1 - - ((dcoConst * dcoTune) - / (8 * (1 + dcoConst * (768 - calVal)))))); - } - break; - case CS_CTL1_SELM__MODOSC: - SystemCoreClock = __MODCLK / dividerValue; - break; - case CS_CTL1_SELM__HFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT if requested - * 3. Enables all SRAM banks - * 4. Sets up power regulator and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -void SystemInit(void) -{ - // Enable FPU if used - #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */ - SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */ - (3UL << 11 * 2)); /* Set CP11 Full Access */ - #endif - - #if (__HALT_WDT == 1) - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT - #endif - - // Enable all SRAM banks - while(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY)); - if (SYSCTL_A->SRAM_NUMBANKS == 4) - { - SYSCTL_A->SRAM_BANKEN_CTL0 = SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN; - } - else - { - SYSCTL_A->SRAM_BANKEN_CTL0 = SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN; - } - - - #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 1.5 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - #endif - - // No flash wait states necessary - - // DCO = 3 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 12 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 2 flash wait state (BANK0 VCORE0 max is 24 MHz) - FLCTL_A->BANK0_RDCTL &= ~FLCTL_A_BANK0_RDCTL_WAIT_MASK | FLCTL_A_BANK0_RDCTL_WAIT_2; - FLCTL_A->BANK1_RDCTL &= ~FLCTL_A_BANK0_RDCTL_WAIT_MASK | FLCTL_A_BANK0_RDCTL_WAIT_2; - - // DCO = 24 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL |= (FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz - // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - - // Switches LDO VCORE1 to DCDC VCORE1 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 3 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) - FLCTL_A->BANK0_RDCTL &= ~FLCTL_A_BANK0_RDCTL_WAIT_MASK | FLCTL_A_BANK0_RDCTL_WAIT_3; - FLCTL_A->BANK1_RDCTL &= ~FLCTL_A_BANK1_RDCTL_WAIT_MASK | FLCTL_A_BANK1_RDCTL_WAIT_3; - - // DCO = 48 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL |= (FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL |= (FLCTL_A_BANK1_RDCTL_BUFD | FLCTL_A_BANK1_RDCTL_BUFI); - #endif - -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411v.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411v.c deleted file mode 100644 index a212221bd02..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411v.c +++ /dev/null @@ -1,410 +0,0 @@ -/****************************************************************************** -* @file system_msp432p411v.c -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for -* MSP432P411V -* @version 3.202 -* @date 08/03/17 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#include -#include -#include - -/*--------------------- Configuration Instructions ---------------------------- - 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: - #define __HALT_WDT 1 - 2. Insert your desired CPU frequency in Hz at: - #define __SYSTEM_CLOCK 12000000 - 3. If you prefer the DC-DC power regulator (more efficient at higher - frequencies), set the __REGULATOR to 1: - #define __REGULATOR 1 - *---------------------------------------------------------------------------*/ - -/*--------------------- Watchdog Timer Configuration ------------------------*/ -// Halt the Watchdog Timer -// <0> Do not halt the WDT -// <1> Halt the WDT -#define __HALT_WDT 1 - -/*--------------------- CPU Frequency Configuration -------------------------*/ -// CPU Frequency -// <1500000> 1.5 MHz -// <3000000> 3 MHz -// <12000000> 12 MHz -// <24000000> 24 MHz -// <48000000> 48 MHz -#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY - -/*--------------------- Power Regulator Configuration -----------------------*/ -// Power Regulator Mode -// <0> LDO -// <1> DC-DC -#define __REGULATOR 0 - -/*---------------------------------------------------------------------------- - Define clocks, used for SystemCoreClockUpdate() - *---------------------------------------------------------------------------*/ -#define __VLOCLK 10000 -#define __MODCLK 24000000 -#define __LFXT 32768 -#define __HFXT 48000000 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - uint32_t source, divider; - uint8_t dividerValue; - - float dcoConst; - int32_t calVal; - uint32_t centeredFreq; - int16_t dcoTune; - - divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; - dividerValue = 1 << divider; - source = CS->CTL1 & CS_CTL1_SELM_MASK; - - switch(source) - { - case CS_CTL1_SELM__LFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - break; - case CS_CTL1_SELM__VLOCLK: - SystemCoreClock = __VLOCLK / dividerValue; - break; - case CS_CTL1_SELM__REFOCLK: - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - break; - case CS_CTL1_SELM__DCOCLK: - dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; - - switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - centeredFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - centeredFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - centeredFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - centeredFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - centeredFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - centeredFreq = 48000000; - break; - } - - if(dcoTune == 0) - { - SystemCoreClock = centeredFreq; - } - else - { - - if(dcoTune & 0x1000) - { - dcoTune = dcoTune | 0xF000; - } - - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); - calVal = TLV->DCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); - calVal = TLV->DCOIR_FCAL_RSEL04; - } - - SystemCoreClock = (uint32_t) ((centeredFreq) - / (1 - - ((dcoConst * dcoTune) - / (8 * (1 + dcoConst * (768 - calVal)))))); - } - break; - case CS_CTL1_SELM__MODOSC: - SystemCoreClock = __MODCLK / dividerValue; - break; - case CS_CTL1_SELM__HFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT if requested - * 3. Enables all SRAM banks - * 4. Sets up power regulator and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -void SystemInit(void) -{ - // Enable FPU if used - #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */ - SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */ - (3UL << 11 * 2)); /* Set CP11 Full Access */ - #endif - - #if (__HALT_WDT == 1) - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT - #endif - - // Enable all SRAM banks - while(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY)); - if (SYSCTL_A->SRAM_NUMBANKS == 4) - { - SYSCTL_A->SRAM_BANKEN_CTL0 = SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN; - } - else - { - SYSCTL_A->SRAM_BANKEN_CTL0 = SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN; - } - - - #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 1.5 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - #endif - - // No flash wait states necessary - - // DCO = 3 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 12 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 2 flash wait state (BANK0 VCORE0 max is 24 MHz) - FLCTL_A->BANK0_RDCTL &= ~FLCTL_A_BANK0_RDCTL_WAIT_MASK | FLCTL_A_BANK0_RDCTL_WAIT_2; - FLCTL_A->BANK1_RDCTL &= ~FLCTL_A_BANK0_RDCTL_WAIT_MASK | FLCTL_A_BANK0_RDCTL_WAIT_2; - - // DCO = 24 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL |= (FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz - // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - - // Switches LDO VCORE1 to DCDC VCORE1 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 3 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) - FLCTL_A->BANK0_RDCTL &= ~FLCTL_A_BANK0_RDCTL_WAIT_MASK | FLCTL_A_BANK0_RDCTL_WAIT_3; - FLCTL_A->BANK1_RDCTL &= ~FLCTL_A_BANK1_RDCTL_WAIT_MASK | FLCTL_A_BANK1_RDCTL_WAIT_3; - - // DCO = 48 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL |= (FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL |= (FLCTL_A_BANK1_RDCTL_BUFD | FLCTL_A_BANK1_RDCTL_BUFI); - #endif - -} - diff --git a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411y.c b/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411y.c deleted file mode 100644 index f5faa778966..00000000000 --- a/ext/hal/ti/simplelink/source/ti/devices/msp432p4xx/startup_system_files/system_msp432p411y.c +++ /dev/null @@ -1,410 +0,0 @@ -/****************************************************************************** -* @file system_msp432p411y.c -* @brief CMSIS Cortex-M4F Device Peripheral Access Layer Source File for -* MSP432P411Y -* @version 3.202 -* @date 08/03/17 -* -* @note View configuration instructions embedded in comments -* -******************************************************************************/ -//***************************************************************************** -// -// Copyright (C) 2015 - 2017 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -//***************************************************************************** - -#include -#include -#include - -/*--------------------- Configuration Instructions ---------------------------- - 1. If you prefer to halt the Watchdog Timer, set __HALT_WDT to 1: - #define __HALT_WDT 1 - 2. Insert your desired CPU frequency in Hz at: - #define __SYSTEM_CLOCK 12000000 - 3. If you prefer the DC-DC power regulator (more efficient at higher - frequencies), set the __REGULATOR to 1: - #define __REGULATOR 1 - *---------------------------------------------------------------------------*/ - -/*--------------------- Watchdog Timer Configuration ------------------------*/ -// Halt the Watchdog Timer -// <0> Do not halt the WDT -// <1> Halt the WDT -#define __HALT_WDT 1 - -/*--------------------- CPU Frequency Configuration -------------------------*/ -// CPU Frequency -// <1500000> 1.5 MHz -// <3000000> 3 MHz -// <12000000> 12 MHz -// <24000000> 24 MHz -// <48000000> 48 MHz -#define __SYSTEM_CLOCK DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY - -/*--------------------- Power Regulator Configuration -----------------------*/ -// Power Regulator Mode -// <0> LDO -// <1> DC-DC -#define __REGULATOR 0 - -/*---------------------------------------------------------------------------- - Define clocks, used for SystemCoreClockUpdate() - *---------------------------------------------------------------------------*/ -#define __VLOCLK 10000 -#define __MODCLK 24000000 -#define __LFXT 32768 -#define __HFXT 48000000 - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *---------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - uint32_t source, divider; - uint8_t dividerValue; - - float dcoConst; - int32_t calVal; - uint32_t centeredFreq; - int16_t dcoTune; - - divider = (CS->CTL1 & CS_CTL1_DIVM_MASK) >> CS_CTL1_DIVM_OFS; - dividerValue = 1 << divider; - source = CS->CTL1 & CS_CTL1_SELM_MASK; - - switch(source) - { - case CS_CTL1_SELM__LFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_LFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_LFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - } - else - { - SystemCoreClock = __LFXT / dividerValue; - } - break; - case CS_CTL1_SELM__VLOCLK: - SystemCoreClock = __VLOCLK / dividerValue; - break; - case CS_CTL1_SELM__REFOCLK: - if (BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - break; - case CS_CTL1_SELM__DCOCLK: - dcoTune = (CS->CTL0 & CS_CTL0_DCOTUNE_MASK) >> CS_CTL0_DCOTUNE_OFS; - - switch(CS->CTL0 & CS_CTL0_DCORSEL_MASK) - { - case CS_CTL0_DCORSEL_0: - centeredFreq = 1500000; - break; - case CS_CTL0_DCORSEL_1: - centeredFreq = 3000000; - break; - case CS_CTL0_DCORSEL_2: - centeredFreq = 6000000; - break; - case CS_CTL0_DCORSEL_3: - centeredFreq = 12000000; - break; - case CS_CTL0_DCORSEL_4: - centeredFreq = 24000000; - break; - case CS_CTL0_DCORSEL_5: - centeredFreq = 48000000; - break; - } - - if(dcoTune == 0) - { - SystemCoreClock = centeredFreq; - } - else - { - - if(dcoTune & 0x1000) - { - dcoTune = dcoTune | 0xF000; - } - - if (BITBAND_PERI(CS->CTL0, CS_CTL0_DCORES_OFS)) - { - dcoConst = *((float *) &TLV->DCOER_CONSTK_RSEL04); - calVal = TLV->DCOER_FCAL_RSEL04; - } - /* Internal Resistor */ - else - { - dcoConst = *((float *) &TLV->DCOIR_CONSTK_RSEL04); - calVal = TLV->DCOIR_FCAL_RSEL04; - } - - SystemCoreClock = (uint32_t) ((centeredFreq) - / (1 - - ((dcoConst * dcoTune) - / (8 * (1 + dcoConst * (768 - calVal)))))); - } - break; - case CS_CTL1_SELM__MODOSC: - SystemCoreClock = __MODCLK / dividerValue; - break; - case CS_CTL1_SELM__HFXTCLK: - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - // Clear interrupt flag - CS->KEY = CS_KEY_VAL; - CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG; - CS->KEY = 1; - - if(BITBAND_PERI(CS->IFG, CS_IFG_HFXTIFG_OFS)) - { - if(BITBAND_PERI(CS->CLKEN, CS_CLKEN_REFOFSEL_OFS)) - { - SystemCoreClock = (128000 / dividerValue); - } - else - { - SystemCoreClock = (32000 / dividerValue); - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - } - else - { - SystemCoreClock = __HFXT / dividerValue; - } - break; - } -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * - * Performs the following initialization steps: - * 1. Enables the FPU - * 2. Halts the WDT if requested - * 3. Enables all SRAM banks - * 4. Sets up power regulator and VCORE - * 5. Enable Flash wait states if needed - * 6. Change MCLK to desired frequency - * 7. Enable Flash read buffering - */ -void SystemInit(void) -{ - // Enable FPU if used - #if (__FPU_USED == 1) /* __FPU_USED is defined in core_cm4.h */ - SCB->CPACR |= ((3UL << 10 * 2) | /* Set CP10 Full Access */ - (3UL << 11 * 2)); /* Set CP11 Full Access */ - #endif - - #if (__HALT_WDT == 1) - WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // Halt the WDT - #endif - - // Enable all SRAM banks - while(!(SYSCTL_A->SRAM_STAT & SYSCTL_A_SRAM_STAT_BNKEN_RDY)); - if (SYSCTL_A->SRAM_NUMBANKS == 4) - { - SYSCTL_A->SRAM_BANKEN_CTL0 = SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN; - } - else - { - SYSCTL_A->SRAM_BANKEN_CTL0 = SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN; - } - - - #if (__SYSTEM_CLOCK == 1500000) // 1.5 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 1.5 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_0; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 3000000) // 3 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while(PCM->CTL1 & PCM_CTL1_PMR_BUSY); - #endif - - // No flash wait states necessary - - // DCO = 3 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_1; // Set DCO to 1.5MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 12000000) // 12 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // No flash wait states necessary - - // DCO = 12 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_3; // Set DCO to 12MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 24000000) // 24 MHz - // Default VCORE is LDO VCORE0 so no change necessary - - // Switches LDO VCORE0 to DCDC VCORE0 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_4; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 2 flash wait state (BANK0 VCORE0 max is 24 MHz) - FLCTL_A->BANK0_RDCTL &= ~FLCTL_A_BANK0_RDCTL_WAIT_MASK | FLCTL_A_BANK0_RDCTL_WAIT_2; - FLCTL_A->BANK1_RDCTL &= ~FLCTL_A_BANK0_RDCTL_WAIT_MASK | FLCTL_A_BANK0_RDCTL_WAIT_2; - - // DCO = 24 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_4; // Set DCO to 24MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL |= (FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL &= ~(FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - - #elif (__SYSTEM_CLOCK == 48000000) // 48 MHz - // Switches LDO VCORE0 to LDO VCORE1; mandatory for 48 MHz setting - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - - // Switches LDO VCORE1 to DCDC VCORE1 if requested - #if __REGULATOR - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_5; - while((PCM->CTL1 & PCM_CTL1_PMR_BUSY)); - #endif - - // 3 flash wait states (BANK0 VCORE1 max is 16 MHz, BANK1 VCORE1 max is 32 MHz) - FLCTL_A->BANK0_RDCTL &= ~FLCTL_A_BANK0_RDCTL_WAIT_MASK | FLCTL_A_BANK0_RDCTL_WAIT_3; - FLCTL_A->BANK1_RDCTL &= ~FLCTL_A_BANK1_RDCTL_WAIT_MASK | FLCTL_A_BANK1_RDCTL_WAIT_3; - - // DCO = 48 MHz; MCLK = source - CS->KEY = CS_KEY_VAL; // Unlock CS module for register access - CS->CTL0 = CS_CTL0_DCORSEL_5; // Set DCO to 48MHz - CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK) | CS_CTL1_SELM__DCOCLK; // Select MCLK as DCO source - CS->KEY = 0; - - // Set Flash Bank read buffering - FLCTL_A->BANK0_RDCTL |= (FLCTL_A_BANK0_RDCTL_BUFD | FLCTL_A_BANK0_RDCTL_BUFI); - FLCTL_A->BANK1_RDCTL |= (FLCTL_A_BANK1_RDCTL_BUFD | FLCTL_A_BANK1_RDCTL_BUFI); - #endif - -} - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/ADC.c b/ext/hal/ti/simplelink/source/ti/drivers/ADC.c deleted file mode 100644 index c408cc86070..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/ADC.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2016-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== ADC.c ======== - */ - -#include -#include -#include - -#include -#include - -extern const ADC_Config ADC_config[]; -extern const uint_least8_t ADC_count; - -/* Default ADC parameters structure */ -const ADC_Params ADC_defaultParams = { - .custom = NULL, - .isProtected = true -}; - -static bool isInitialized = false; - -/* - * ======== ADC_close ======== - */ -void ADC_close(ADC_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== ADC_control ======== - */ -int_fast16_t ADC_control(ADC_Handle handle, uint_fast16_t cmd, void *arg) -{ - return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); -} - -/* - * ======== ADC_convert ======== - */ -int_fast16_t ADC_convert(ADC_Handle handle, uint16_t *value) -{ - return (handle->fxnTablePtr->convertFxn(handle, value)); -} - -/* - * ======== ADC_convertToMicroVolts ======== - */ -uint32_t ADC_convertToMicroVolts(ADC_Handle handle, uint16_t adcValue) -{ - return (handle->fxnTablePtr->convertToMicroVolts(handle, adcValue)); -} - -/* - * ======== ADC_init ======== - */ -void ADC_init(void) -{ - uint_least8_t i; - uint_fast32_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - for (i = 0; i < ADC_count; i++) { - ADC_config[i].fxnTablePtr->initFxn((ADC_Handle)&(ADC_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== ADC_open ======== - */ -ADC_Handle ADC_open(uint_least8_t index, ADC_Params *params) -{ - ADC_Handle handle = NULL; - - if (isInitialized && (index < ADC_count)) { - /* If params are NULL use defaults */ - if (params == NULL) { - params = (ADC_Params *) &ADC_defaultParams; - } - - /* Get handle for this driver instance */ - handle = (ADC_Handle) &(ADC_config[index]); - handle = handle->fxnTablePtr->openFxn(handle, params); - } - - return (handle); -} - -/* - * ======== ADC_Params_init ======== - */ -void ADC_Params_init(ADC_Params *params) -{ - *params = ADC_defaultParams; -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/ADC.h b/ext/hal/ti/simplelink/source/ti/drivers/ADC.h deleted file mode 100644 index 6b1e18962b2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/ADC.h +++ /dev/null @@ -1,430 +0,0 @@ -/* - * Copyright (c) 2016-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file ADC.h - * - * @brief ADC driver interface - * - * The ADC header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * # Operation # - * The ADC driver operates as a simplified ADC module with only single channel - * sampling support. It also operates on blocking only mode which means users - * have to wait the current sampling finished before starting another sampling. - * The sampling channel needs to be specified in the ADC_open() before calling - * ADC_convert(). - * - * The APIs in this driver serve as an interface to a typical TI-RTOS - * application. The specific peripheral implementations are responsible to - * create all the SYS/BIOS specific primitives to allow for thread-safe - * operation. - * User can use the ADC driver or the ADCBuf driver that has more features. - * But both ADC and ADCBuf cannot be used together in an application. - * - * ## Opening the driver # - * - * @code - * ADC_Handle adc; - * ADC_Params params; - * - * ADC_Params_init(¶ms); - * adc = ADC_open(Board_ADC0, ¶ms); - * if (adc == NULL) { - * // ADC_open() failed - * while (1); - * } - * @endcode - * - * ## Converting # - * An ADC conversion with a ADC peripheral is started by calling ADC_convert(). - * The result value is returned by ADC_convert() once the conversion is - * finished. - * - * @code - * int_fast16_t res; - * uint_fast16_t adcValue; - * - * res = ADC_convert(adc, &adcValue); - * if (res == ADC_STATUS_SUCCESS) { - * //use adcValue - * } - * @endcode - * - * # Implementation # - * - * This module serves as the main interface for TI-RTOS - * applications. Its purpose is to redirect the module's APIs to specific - * peripheral implementations which are specified using a pointer to a - * ADC_FxnTable. - * - * The ADC driver interface module is joined (at link time) to a - * NULL-terminated array of ADC_Config data structures named *ADC_config*. - * *ADC_config* is implemented in the application with each entry being an - * instance of a ADC peripheral. Each entry in *ADC_config* contains a: - * - (ADC_FxnTable *) to a set of functions that implement a ADC peripheral - * - (void *) data object that is associated with the ADC_FxnTable - * - (void *) hardware attributes that are associated to the ADC_FxnTable - * - * # Instrumentation # - * The ADC driver interface produces log statements if instrumentation is - * enabled. - * - * Diagnostics Mask | Log details | - * ---------------- | ----------- | - * Diags_USER1 | basic operations performed | - * Diags_USER2 | detailed operations performed | - * - * ============================================================================ - */ - -#ifndef ti_drivers_ADC__include -#define ti_drivers_ADC__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/** - * @brief Define to support deprecated API ADC_convertRawToMicroVolts. - * - * It is succeeded by the generic ADC_convertToMicroVolts. - */ -#define ADC_convertRawToMicroVolts ADC_convertToMicroVolts - -/** - * @defgroup ADC_CONTROL ADC_control command and status codes - * These ADC macros are reservations for ADC.h - * @{ - */ - -/*! - * Common ADC_control command code reservation offset. - * ADC driver implementations should offset command codes with ADC_CMD_RESERVED - * growing positively - * - * Example implementation specific command codes: - * @code - * #define ADCXYZ_CMD_COMMAND0 ADC_CMD_RESERVED + 0 - * #define ADCXYZ_CMD_COMMAND1 ADC_CMD_RESERVED + 1 - * @endcode - */ -#define ADC_CMD_RESERVED (32) - -/*! - * Common ADC_control status code reservation offset. - * ADC driver implementations should offset status codes with - * ADC_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define ADCXYZ_STATUS_ERROR0 ADC_STATUS_RESERVED - 0 - * #define ADCXYZ_STATUS_ERROR1 ADC_STATUS_RESERVED - 1 - * #define ADCXYZ_STATUS_ERROR2 ADC_STATUS_RESERVED - 2 - * @endcode - */ -#define ADC_STATUS_RESERVED (-32) - -/*! - * @brief Successful status code returned by ADC_control(). - * - * ADC_control() returns ADC_STATUS_SUCCESS if the control code was executed - * successfully. - * @{ - * @ingroup ADC_CONTROL - */ -#define ADC_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by ADC_control(). - * - * ADC_control() returns ADC_STATUS_ERROR if the control code was not executed - * successfully. - */ -#define ADC_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by ADC_control() for undefined - * command codes. - * - * ADC_control() returns ADC_STATUS_UNDEFINEDCMD if the control code is not - * recognized by the driver implementation. - */ -#define ADC_STATUS_UNDEFINEDCMD (-2) -/** @}*/ - -/** - * @defgroup ADC_CMD Command Codes - * ADC_CMD_* macros are general command codes for ADC_control(). Not all ADC - * driver implementations support these command codes. - * @{ - * @ingroup ADC_CONTROL - */ - -/* Add ADC_CMD_ here */ - -/** @}*/ - -/** @}*/ - -/*! - * @brief A handle that is returned from a ADC_open() call. - */ -typedef struct ADC_Config_ *ADC_Handle; - -/*! - * @brief ADC Parameters - * - * ADC parameters are used to with the ADC_open() call. Only custom argument - * is supported in the parameters. Default values for these parameters are - * set using ADC_Params_init(). - * - * @sa ADC_Params_init() - */ -typedef struct ADC_Params_ { - void *custom; /*!< Custom argument used by driver - implementation */ - bool isProtected; /*!< By default ADC uses a semaphore - to guarantee thread safety. Setting - this parameter to 'false' will eliminate - the usage of a semaphore for thread - safety. The user is then responsible - for ensuring that parallel invocations - of ADC_convert() are thread safe. */ -} ADC_Params; - -/*! - * @brief A function pointer to a driver specific implementation of - * ADC_close(). - */ -typedef void (*ADC_CloseFxn) (ADC_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * ADC_control(). - */ -typedef int_fast16_t (*ADC_ControlFxn) (ADC_Handle handle, uint_fast16_t cmd, - void *arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * ADC_ConvertFxn(). - */ -typedef int_fast16_t (*ADC_ConvertFxn) (ADC_Handle handle, uint16_t *value); - -/*! - * @brief A function pointer to a driver specific implementation of - * ADC_convertToMicroVolts(). - */ -typedef uint32_t (*ADC_ConvertToMicroVoltsFxn) (ADC_Handle handle, - uint16_t adcValue); - -/*! - * @brief A function pointer to a driver specific implementation of - * ADC_init(). - */ -typedef void (*ADC_InitFxn) (ADC_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * ADC_open(). - */ -typedef ADC_Handle (*ADC_OpenFxn) (ADC_Handle handle, ADC_Params *params); - -/*! - * @brief The definition of a ADC function table that contains the - * required set of functions to control a specific ADC driver - * implementation. - */ -typedef struct ADC_FxnTable_ { - /*! Function to close the specified peripheral */ - ADC_CloseFxn closeFxn; - - /*! Function to perform implementation specific features */ - ADC_ControlFxn controlFxn; - - /*! Function to initiate a ADC single channel conversion */ - ADC_ConvertFxn convertFxn; - - /*! Function to convert ADC result to microvolts */ - ADC_ConvertToMicroVoltsFxn convertToMicroVolts; - - /*! Function to initialize the given data object */ - ADC_InitFxn initFxn; - - /*! Function to open the specified peripheral */ - ADC_OpenFxn openFxn; -} ADC_FxnTable; - -/*! - * @brief ADC Global configuration - * - * The ADC_Config structure contains a set of pointers used to characterize - * the ADC driver implementation. - * - * This structure needs to be defined before calling ADC_init() and it must - * not be changed thereafter. - * - * @sa ADC_init() - */ -typedef struct ADC_Config_ { - /*! Pointer to a table of driver-specific implementations of ADC APIs */ - ADC_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver specific data object */ - void *object; - - /*! Pointer to a driver specific hardware attributes structure */ - void const *hwAttrs; -} ADC_Config; - -/*! - * @brief Function to close a ADC driver - * - * @pre ADC_open() has to be called first. - * - * @param handle An ADC handle returned from ADC_open() - * - * @sa ADC_open() - */ -extern void ADC_close(ADC_Handle handle); - -/*! - * @brief Function performs implementation specific features on a given - * ADC_Handle. - * - * @pre ADC_open() has to be called first. - * - * @param handle A ADC handle returned from ADC_open() - * - * @param cmd A command value defined by the driver specific - * implementation - * - * @param arg An optional R/W (read/write) argument that is - * accompanied with cmd - * - * @return Implementation specific return codes. Negative values indicate - * unsuccessful operations. - * - * @sa ADC_open() - */ -extern int_fast16_t ADC_control(ADC_Handle handle, uint_fast16_t cmd, - void *arg); - -/*! - * @brief Function to perform ADC conversion - * - * Function to perform ADC single channel single sample conversion. - * - * @pre ADC_open() has been called - * - * @param handle An ADC_Handle - * @param value A pointer to the conversion result - * - * @return The return value indicates the conversion is succeeded or - * failed. The value could be ADC_STATUS_SUCCESS or - * ADC_STATUS_ERROR. - * - * @sa ADC_open() - * @sa ADC_close() - */ -extern int_fast16_t ADC_convert(ADC_Handle handle, uint16_t *value); - -/*! - * @brief Function performs conversion from ADC result to actual value in - * microvolts. - * - * @pre ADC_open() and ADC_convert() has to be called first. - * - * @param handle A ADC handle returned from ADC_open() - * - * @param adcValue A sampling result return from ADC_convert() - * - * @return The actual sampling result in micro volts unit. - * - * @sa ADC_open() - */ -extern uint32_t ADC_convertToMicroVolts(ADC_Handle handle, - uint16_t adcValue); - -/*! - * @brief Function to initializes the ADC driver - * - * @pre The ADC_config structure must exist and be persistent before this - * function can be called. This function must also be called before - * any other ADC driver APIs. - */ -extern void ADC_init(void); - -/*! - * @brief Function to initialize the ADC peripheral - * - * Function to initialize the ADC peripheral specified by the - * particular index value. - * - * @pre ADC_init() has been called - * - * @param index Logical peripheral number for the ADC indexed into - * the ADC_config table - * @param params Pointer to an parameter block, if NULL it will use - * default values. All the fields in this structure are - * RO (read-only). - * - * @return A ADC_Handle on success or a NULL on an error or if it has been - * opened already. - * - * @sa ADC_init() - * @sa ADC_close() - */ -extern ADC_Handle ADC_open(uint_least8_t index, ADC_Params *params); - -/*! - * @brief Function to initialize the ADC_Params struct to its defaults - * - * @param params An pointer to ADC_Params structure for - * initialization - * - * Defaults values are: - * custom = NULL - */ -extern void ADC_Params_init(ADC_Params *params); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_ADC__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/Camera.c b/ext/hal/ti/simplelink/source/ti/drivers/Camera.c deleted file mode 100644 index 4717b03f8d3..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/Camera.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== Camera.c ======== - */ - -#include -#include -#include -#include - -#include -#include - -extern const Camera_Config Camera_config[]; -extern const uint_least8_t Camera_count; - -/* Default Camera parameters structure */ -const Camera_Params Camera_defaultParams = { - Camera_MODE_BLOCKING, /* captureMode */ - 24000000, /* outputClock */ - Camera_HSYNC_POLARITY_HIGH, /* hsyncPolarity */ - Camera_VSYNC_POLARITY_HIGH, /* vsyncPolarity */ - Camera_PCLK_CONFIG_RISING_EDGE, /* pixelClkConfig */ - Camera_BYTE_ORDER_NORMAL, /* byteOrder */ - Camera_INTERFACE_SYNC_ON, /* interfaceSync */ - Camera_STOP_CAPTURE_FRAME_END, /* stopConfig */ - Camera_START_CAPTURE_FRAME_START, /* startConfig */ - Camera_WAIT_FOREVER, /* captureTimeout */ - NULL, /* captureCallback */ - NULL -}; - -static bool isInitialized = false; - -/* - * ======== Camera_close ======== - */ -void Camera_close(Camera_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== Camera_control ======== - */ -int_fast16_t Camera_control(Camera_Handle handle, uint_fast16_t cmd, void *arg) -{ - return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); -} - -/* - * ======== Camera_init ======== - */ -void Camera_init(void) -{ - uint_least8_t i; - uint_fast32_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - for (i = 0; i < Camera_count; i++) { - Camera_config[i].fxnTablePtr->initFxn((Camera_Handle)&(Camera_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== Camera_open ======== - */ -Camera_Handle Camera_open(uint_least8_t index, Camera_Params *params) -{ - Camera_Handle handle = NULL; - - /* Verify driver index and state */ - if (isInitialized && (index < Camera_count)) { - /* If params are NULL use defaults. */ - if (params == NULL) { - params = (Camera_Params *)&Camera_defaultParams; - } - - /* Get handle for this driver instance */ - handle = (Camera_Handle)&(Camera_config[index]); - handle = handle->fxnTablePtr->openFxn(handle, params); - } - - return (handle); -} - -/* - * ======== Camera_Params_init ======== - */ -void Camera_Params_init(Camera_Params *params) -{ - *params = Camera_defaultParams; -} - -/* - * ======== Camera_capture ======== - */ -int_fast16_t Camera_capture(Camera_Handle handle, void *buffer, - size_t bufferlen, size_t *frameLen) -{ - return (handle->fxnTablePtr->captureFxn(handle, buffer, bufferlen, frameLen)); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/Camera.h b/ext/hal/ti/simplelink/source/ti/drivers/Camera.h deleted file mode 100644 index 1c6072e0eb4..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/Camera.h +++ /dev/null @@ -1,651 +0,0 @@ -/* - * Copyright (c) 2015-2016, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file Camera.h - * - * @brief Camera driver interface - * - * The Camera header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * # Overview # - * The Camera driver is used to retrieve the data being transferred by the - * Camera sensor. - * This driver provides an API for capturing the image from the Camera sensor. - * The camera sensor control and implementation are the responsibility of the - * application using the interface. - * - * The Camera driver has been designed to operate in an RTOS environment. It - * protects its transactions with OS primitives supplied by the underlying - * RTOS. - * - * # Usage # - * - * The Camera driver includes the following APIs: - * - Camera_init(): Initialize the Camera driver. - * - Camera_Params_init(): Initialize a #Camera_Params structure with default - * vaules. - * - Camera_open(): Open an instance of the Camera driver. - * - Camera_control(): Performs implemenation-specific features on a given - * Camera peripheral. - * - Camera_capture(): Capture a frame. - * - Camera_close(): De-initialize a given Camera instance. - * - * - * ### Camera Driver Configuration # - * - * In order to use the Camera APIs, the application is required - * to provide device-specific Camera configuration in the Board.c file. - * The Camera driver interface defines a configuration data structure: - * - * @code - * typedef struct Camera_Config_ { - * Camera_FxnTable const *fxnTablePtr; - * void *object; - * void const *hwAttrs; - * } Camera_Config; - * @endcode - * - * The application must declare an array of Camera_Config elements, named - * Camera_config[]. Each element of Camera_config[] must be populated with - * pointers to a device specific Camera driver implementation's function - * table, driver object, and hardware attributes. The hardware attributes - * define properties such as the Camera peripheral's base address. - * Each element in Camera_config[] corresponds to - * a Camera instance, and none of the elements should have NULL pointers. - * There is no correlation between the index and the - * peripheral designation (such as Camera0 or Camera1). For example, it - * is possible to use Camera_config[0] for Camera1. - * - * Because the Camera configuration is very device dependent, you will need to - * check the doxygen for the device specific Camera implementation. There you - * will find a description of the Camera hardware attributes. Please also - * refer to the Board.c file of any of your examples to see the Camera - * configuration. - * - * ### Initializing the Camear Driver # - * The application initializes the Camera driver by calling Camera_init(). - * This function must be called before any other Camera API. Camera_init() - * iterates through the elements of the Camera_config[] array, calling - * the element's device implementation Camera initialization function. - * ### Camera Parameters - * - * The #Camera_Params structure is passed to Camera_open(). If NULL - * is passed for the parameters, Camera_open() uses default parameters. - * A #Camera_Params structure is initialized with default values by passing - * it to Camera_Params_init(). - * Some of the Camera parameters are described below. To see brief descriptions - * of all the parameters, see #Camera_Params. - * - * #### Camera Modes - * The Camera driver operates in either blocking mode or callback mode: - * - #Camera_MODE_BLOCKING: The call to Camera_capture() blocks until the - * capture has completed. - * - #Camera_MODE_CALLBACK: The call to Camera_capture() returns immediately. - * When the capture completes, the Camera driver will call a user- - * specified callback function. - * - * The capture mode is determined by the #Camera_Params.captureMode parameter - * passed to Camera_open(). The Camera driver defaults to blocking mode, if the - * application does not set it. - * - * Once a Camera driver instance is opened, the only way - * to change the capture mode is to close and re-open the Camera - * instance with the new capture mode. - * - * ### Opening the driver # - * The following example opens a Camera driver instance in blocking mode: - * @code - * Camera_Handle handle; - * Camera_Params params; - * - * Camera_Params_init(¶ms); - * params.captureMode = Camera_MODE_BLOCKING; - * < Change any other params as required > - * - * handle = Camera_open(someCamera_configIndexValue, ¶ms); - * if (!handle) { - * // Error opening the Camera driver - * } - * @endcode - * - * ### Capturing an Image # - * - * The following code example captures a frame. - * - * @code - * unsigned char captureBuffer[1920]; - * - * ret = Camera_capture(handle, &captureBuffer, sizeof(captureBuffer)); - * @endcode - * - * # Implementation # - * - * This module serves as the main interface for RTOS - * applications. Its purpose is to redirect the module's APIs to specific - * peripheral implementations which are specified using a pointer to a - * #Camera_FxnTable. - * - * The Camera driver interface module is joined (at link time) to an - * array of #Camera_Config data structures named *Camera_config*. - * *Camera_config* is implemented in the application with each entry being an - * instance of a Camera peripheral. Each entry in *Camera_config* contains a: - * - (Camera_FxnTable *) to a set of functions that implement a Camera - * peripheral - * - (void *) data object that is associated with the Camera_FxnTable - * - (void *) hardware attributes that are associated to the Camera_FxnTable - * - ******************************************************************************* - */ - -#ifndef ti_drivers_Camera__include -#define ti_drivers_Camera__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/** - * @defgroup CAMERA_CONTROL Camera_control command and status codes - * These Camera macros are reservations for Camera.h - * @{ - */ - -/*! - * Common Camera_control command code reservation offset. - * Camera driver implementations should offset command codes with - * CAMERA_CMD_RESERVED growing positively - * - * Example implementation specific command codes: - * @code - * #define CAMERAXYZ_CMD_COMMAND0 CAMERA_CMD_RESERVED + 0 - * #define CAMERAXYZ_CMD_COMMAND1 CAMERA_CMD_RESERVED + 1 - * @endcode - */ -#define CAMERA_CMD_RESERVED (32) - -/*! - * Common Camera_control status code reservation offset. - * Camera driver implementations should offset status codes with - * CAMERA_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define CAMERAXYZ_STATUS_ERROR0 CAMERA_STATUS_RESERVED - 0 - * #define CAMERAXYZ_STATUS_ERROR1 CAMERA_STATUS_RESERVED - 1 - * #define CAMERAXYZ_STATUS_ERROR2 CAMERA_STATUS_RESERVED - 2 - * @endcode - */ -#define CAMERA_STATUS_RESERVED (-32) - -/** - * @defgroup Camera_STATUS Status Codes - * Camera_STATUS_* macros are general status codes returned by Camera_control() - * @{ - * @ingroup Camera_CONTROL - */ - -/*! - * @brief Successful status code returned by Camera_control(). - * - * Camera_control() returns CAMERA_STATUS_SUCCESS if the control code was - * executed successfully. - */ -#define CAMERA_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by Camera_control(). - * - * Camera_control() returns CAMERA_STATUS_ERROR if the control code was not - * executed successfully. - */ -#define CAMERA_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by Camera_control() for undefined - * command codes. - * - * Camera_control() returns CAMERA_STATUS_UNDEFINEDCMD if the control code is - * not recognized by the driver implementation. - */ -#define CAMERA_STATUS_UNDEFINEDCMD (-2) -/** @}*/ - -/** - * @defgroup Camera_CMD Command Codes - * Camera_CMD_* macros are general command codes for Camera_control(). Not all - * Camera driver implementations support these command codes. - * @{ - * @ingroup Camera_CONTROL - */ - -/* Add Camera_CMD_ here */ - -/** @}*/ - -/** @}*/ - -/*! - * @brief Wait forever define - */ -#define Camera_WAIT_FOREVER (~(0U)) - -/*! - * @brief A handle that is returned from a Camera_open() call. - */ -typedef struct Camera_Config_ *Camera_Handle; - -/*! - * @brief The definition of a callback function used by the Camera driver - * when used in ::Camera_MODE_CALLBACK - * - * @param Camera_Handle Camera_Handle - * - * @param buf Pointer to capture buffer - * - * @param frameLength length of frame - * - */ -typedef void (*Camera_Callback) (Camera_Handle handle, void *buf, - size_t frameLength); - -/*! - * @brief Camera capture mode settings - * - * This enum defines the capture mode for the - * configured Camera. - */ -typedef enum Camera_CaptureMode_ { - /*! - * Uses a semaphore to block while data is being sent. Context of - * the call must be a Task. - */ - Camera_MODE_BLOCKING, - - /*! - * Non-blocking and will return immediately. When the capture - * by the interrupt is finished the configured callback function - * is called. - */ - Camera_MODE_CALLBACK -} Camera_CaptureMode; - -/*! - * @brief Camera HSync polarity - * - * This enum defines the polarity of the HSync signal. - */ -typedef enum Camera_HSyncPolarity_ { - Camera_HSYNC_POLARITY_HIGH = 0, - Camera_HSYNC_POLARITY_LOW -} Camera_HSyncPolarity; - -/*! - * @brief Camera VSync polarity - * - * This enum defines the polarity of the VSync signal. - */ -typedef enum Camera_VSyncPolarity_ { - Camera_VSYNC_POLARITY_HIGH = 0, - Camera_VSYNC_POLARITY_LOW -} Camera_VSyncPolarity; - -/*! - * @brief Camera pixel clock configuration - * - * This enum defines the pixel clock configuration. - */ -typedef enum Camera_PixelClkConfig_ { - Camera_PCLK_CONFIG_RISING_EDGE = 0, - Camera_PCLK_CONFIG_FALLING_EDGE -} Camera_PixelClkConfig; - -/*! - * @brief Camera byte order - * - * This enum defines the byte order of camera capture. - * - * In normal mode, the byte order is: - * | byte3 | byte2 | byte1 | byte0 | - * - * In swap mode, the bytes are ordered as: - * | byte2 | byte3 | byte0 | byte1 | - */ -typedef enum Camera_ByteOrder_ { - Camera_BYTE_ORDER_NORMAL = 0, - Camera_BYTE_ORDER_SWAP -} Camera_ByteOrder; - -/*! - * @brief Camera interface synchronization - * - * This enum defines the sensor to camera interface synchronization - * configuration. - */ -typedef enum Camera_IfSynchoronisation_ { - Camera_INTERFACE_SYNC_OFF = 0, - Camera_INTERFACE_SYNC_ON -} Camera_IfSynchoronisation; - -/*! - * @brief Camera stop capture configuration - * - * This enum defines the stop capture configuration. - */ -typedef enum Camera_StopCaptureConfig_ { - Camera_STOP_CAPTURE_IMMEDIATE = 0, - Camera_STOP_CAPTURE_FRAME_END -} Camera_StopCaptureConfig; - -/*! - * @brief Camera start capture configuration - * - * This enum defines the start capture configuration. - */ -typedef enum Camera_StartCaptureConfig_ { - Camera_START_CAPTURE_IMMEDIATE = 0, - Camera_START_CAPTURE_FRAME_START -} Camera_StartCaptureConfig; - -/*! - * @brief Camera Parameters - * - * Camera parameters are used to with the Camera_open() call. - * Default values for these parameters are set using Camera_Params_init(). - * - * If Camera_CaptureMode is set to Camera_MODE_BLOCKING then Camera_capture - * function calls will block thread execution until the capture has completed. - * - * If Camera_CaptureMode is set to Camera_MODE_CALLBACK then Camera_capture - * will not block thread execution and it will call the function specified by - * captureCallbackFxn. - * - * @sa Camera_Params_init() - */ -typedef struct Camera_Params_ { - /*!< Mode for camera capture */ - Camera_CaptureMode captureMode; - - /*!< Output clock to set divider */ - uint32_t outputClock; - - /*!< Polarity of Hsync */ - Camera_HSyncPolarity hsyncPolarity; - - /*!< Polarity of VSync */ - Camera_VSyncPolarity vsyncPolarity; - - /*!< Pixel clock configuration */ - Camera_PixelClkConfig pixelClkConfig; - - /*!< camera capture byte order */ - Camera_ByteOrder byteOrder; - - /*!< Camera-Sensor synchronization */ - Camera_IfSynchoronisation interfaceSync; - - /*!< Camera stop configuration */ - Camera_StopCaptureConfig stopConfig; - - /*!< Camera start configuration */ - Camera_StartCaptureConfig startConfig; - - /*!< Timeout for capture semaphore */ - uint32_t captureTimeout; - - /*!< Pointer to capture callback */ - Camera_Callback captureCallback; - - /*!< Custom argument used by driver implementation */ - void *custom; -} Camera_Params; - -/*! - * @brief A function pointer to a driver specific implementation of - * Camera_close(). - */ -typedef void (*Camera_CloseFxn) (Camera_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Camera_control(). - */ -typedef int_fast16_t (*Camera_ControlFxn) (Camera_Handle handle, - uint_fast16_t cmd, - void *arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * Camera_init(). - */ -typedef void (*Camera_InitFxn) (Camera_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Camera_open(). - */ -typedef Camera_Handle (*Camera_OpenFxn) (Camera_Handle handle, - Camera_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * Camera_capture(). - */ -typedef int_fast16_t (*Camera_CaptureFxn) (Camera_Handle handle, void *buffer, - size_t bufferlen, size_t *frameLen); - -/*! - * @brief The definition of a Camera function table that contains the - * required set of functions to control a specific Camera driver - * implementation. - */ -typedef struct Camera_FxnTable_ { - /*! Function to close the specified peripheral */ - Camera_CloseFxn closeFxn; - - /*! Function to implementation specific control function */ - Camera_ControlFxn controlFxn; - - /*! Function to initialize the given data object */ - Camera_InitFxn initFxn; - - /*! Function to open the specified peripheral */ - Camera_OpenFxn openFxn; - - /*! Function to initiate a Camera capture */ - Camera_CaptureFxn captureFxn; -} Camera_FxnTable; - -/*! - * @brief Camera Global configuration - * - * The Camera_Config structure contains a set of pointers used to characterize - * the Camera driver implementation. - * - * This structure needs to be defined before calling Camera_init() and it must - * not be changed thereafter. - * -* @sa Camera_init() - */ -typedef struct Camera_Config_ { - /*! Pointer to a table of driver-specific implementations of Camera APIs */ - Camera_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver specific data object */ - void *object; - - /*! Pointer to a driver specific hardware attributes structure */ - void const *hwAttrs; -} Camera_Config; - -/*! - * @brief Function to close a Camera peripheral specified by the Camera handle - * - * @pre Camera_open() had to be called first. - * - * @param handle A Camera_Handle returned from Camera_open - * - * @sa Camera_open() - */ -extern void Camera_close(Camera_Handle handle); - -/*! - * @brief Function performs implementation specific features on a given - * Camera_Handle. - * - * Commands for Camera_control can originate from Camera.h or from - * implementation specific Camera*.h (_CameraCC32XX.h_, etc.. ) files. - * While commands from Camera.h are API portable across driver implementations, - * not all implementations may support all these commands. - * Conversely, commands from driver implementation specific Camera*.h files add - * unique driver capabilities but are not API portable across all Camera driver - * implementations. - * - * Commands supported by Camera.h follow a Camera_CMD_\ naming - * convention.
- * Commands supported by Camera*.h follow a Camera*_CMD_\ naming - * convention.
- * Each control command defines @b arg differently. The types of @b arg are - * documented with each command. - * - * See @ref Camera_CMD "Camera_control command codes" for command codes. - * - * See @ref Camera_STATUS "Camera_control return status codes" for status codes. - * - * @pre Camera_open() has to be called first. - * - * @param handle A Camera handle returned from Camera_open() - * - * @param cmd Camera.h or Camera*.h commands. - * - * @param arg An optional R/W (read/write) command argument - * accompanied with cmd - * - * @return Implementation specific return codes. Negative values indicate - * unsuccessful operations. - * - * @sa Camera_open() - */ -extern int_fast16_t Camera_control(Camera_Handle handle, uint_fast16_t cmd, - void *arg); - -/*! - * @brief Function to initializes the Camera module - * - * @pre The Camera_config structure must exist and be persistent before this - * function can be called. This function must also be called before - * any other Camera driver APIs. This function call does not modify any - * peripheral registers. - */ -extern void Camera_init(void); - -/*! - * @brief Function to initialize a given Camera peripheral specified by the - * particular index value. The parameter specifies which mode the - * Camera will operate. - * - * @pre Camera controller has been initialized - * - * @param index Logical peripheral number for the Camera indexed into - * the Camera_config table - * - * @param params Pointer to an parameter block, if NULL it will use - * default values. All the fields in this structure are - * RO (read-only). - * - * @return A Camera_Handle on success or a NULL on an error or if it has been - * opened already. - * - * @sa Camera_init() - * @sa Camera_close() - */ -extern Camera_Handle Camera_open(uint_least8_t index, Camera_Params *params); - -/*! - * @brief Function to initialize the Camera_Params structure to its defaults - * - * @param params An pointer to Camera_Params structure for - * initialization - * - * Defaults values are: - * captureMode = Camera_MODE_BLOCKING; - * outputClock = 24000000; - * hsyncPolarity = Camera_HSYNC_POLARITY_HIGH; - * vsyncPolarity = Camera_VSYNC_POLARITY_HIGH; - * pixelClkConfig = Camera_PCLK_CONFIG_RISING_EDGE; - * byteOrder = Camera_BYTE_ORDER_NORMAL; - * interfaceSync = Camera_INTERFACE_SYNC_ON; - * stopConfig = Camera_STOP_CAPTURE_FRAME_END; - * startConfig = Camera_START_CAPTURE_FRAME_START; - * captureTimeout = Camera_WAIT_FOREVER; - * captureCallback = NULL; - */ -extern void Camera_Params_init(Camera_Params *params); - -/*! - * @brief Function that handles the Camera capture of a frame. - * - * In Camera_MODE_BLOCKING, Camera_capture will block task execution until - * the capture is complete. - * - * In Camera_MODE_CALLBACK, Camera_capture does not block task execution - * and calls a callback function specified by captureCallbackFxn. - * The Camera buffer must stay persistent until the Camera_capture - * function has completed! - * - * @param handle A Camera_Handle - * - * @param buffer A pointer to a WO (write-only) buffer into which the - * captured frame is placed - * - * @param bufferlen Length (in bytes) of the capture buffer - * - * @param frameLen Pointer to return number of bytes captured. - * - * @return CAMERA_STATUS_SUCCESS on successful capture, CAMERA_STATUS_ERROR if - * if otherwise. - * - * @sa Camera_open - */ -extern int_fast16_t Camera_capture(Camera_Handle handle, void *buffer, - size_t bufferlen, size_t *frameLen); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_Camera__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/Capture.c b/ext/hal/ti/simplelink/source/ti/drivers/Capture.c deleted file mode 100644 index b51c899c200..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/Capture.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2016-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -#include -#include - -extern const Capture_Config Capture_config[]; -extern const uint_least8_t Capture_count; - -/* Default Parameters */ -static const Capture_Params defaultParams = { - .callbackFxn = NULL, - .mode = Capture_RISING_EDGE, - .periodUnit = Capture_PERIOD_COUNTS -}; - -static bool isInitialized = false; - -/* - * ======== Capture_close ======== - */ -void Capture_close(Capture_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== Capture_control ======== - */ -int_fast16_t Capture_control(Capture_Handle handle, uint_fast16_t cmd, - void *arg) -{ - return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); -} - -/* - * ======== Capture_init ======== - */ -void Capture_init(void) -{ - uint_least8_t i; - uint_fast32_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - for (i = 0; i < Capture_count; i++) { - Capture_config[i].fxnTablePtr->initFxn((Capture_Handle) &(Capture_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== Capture_open ======== - */ -Capture_Handle Capture_open(uint_least8_t index, Capture_Params *params) -{ - Capture_Handle handle = NULL; - - /* Verify driver index and state */ - if (isInitialized && (index < Capture_count)) { - /* If parameters are NULL use defaults */ - if (params == NULL) { - params = (Capture_Params *) &defaultParams; - } - - /* Get handle for this driver instance */ - handle = (Capture_Handle) &(Capture_config[index]); - handle = handle->fxnTablePtr->openFxn(handle, params); - } - - return (handle); -} - -/* - * ======== Capture_Params_init ======== - */ -void Capture_Params_init(Capture_Params *params) -{ - *params = defaultParams; -} - -/* - * ======== Capture_start ======== - */ -int32_t Capture_start(Capture_Handle handle) -{ - return (handle->fxnTablePtr->startFxn(handle)); -} - -/* - * ======== Capture_stop ======== - */ -void Capture_stop(Capture_Handle handle) -{ - handle->fxnTablePtr->stopFxn(handle); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/Capture.h b/ext/hal/ti/simplelink/source/ti/drivers/Capture.h deleted file mode 100644 index fdde244bae0..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/Capture.h +++ /dev/null @@ -1,501 +0,0 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file Capture.h - * @brief Capture driver interface - * - * The capture header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * # Overview # - * The capture driver serves as the main interface for a typical RTOS - * application. Its purpose is to redirect the capture APIs to device specific - * implementations which are specified using a pointer to a #Capture_FxnTable. - * The device specific implementations are responsible for creating all the - * RTOS specific primitives to allow for thead-safe operation. The capture - * driver utilizes the general purpose timer hardware. - * - * The capture driver internally handles the general purpose timer resource - * allocation. For each capture driver instance, Capture_open() occupies the - * specified timer, and Capture_close() releases the occupied timer resource. - * - * # Usage# - * The capture driver is used to detect and time edge triggered events on a - * GPIO pin. The following example code opens a capture instance in falling - * edge mode. The interval returned in the callback function is in - * microseconds. - * - * @code - * Capture_Handle handle; - * Capture_Params params; - * - * Capture_Params_init(¶ms); - * params.mode = Capture_FALLING_EDGE; - * params.callbackFxn = someCaptureCallbackFunction; - * params.periodUnit = Capture_PERIOD_US; - * - * handle = Capture_open(Board_CAPTURE0, ¶ms); - * - * if (handle == NULL) { - * //Capture_open() failed - * while(1); - * } - * - * status = Capture_start(handle); - * - * if (status == Capture_STATUS_ERROR) { - * //Capture_start() failed - * while(1); - * } - * - * sleep(10000); - * - * Capture_stop(handle); - * @endcode - - * ### Capture Driver Configuration # - * - * In order to use the capture APIs, the application is required to provide - * device specific capture configuration in the Board.c file. The capture - * driver interface defines a configuration data structure: - * - * @code - * typedef struct Capture_Config_ { - * Capture_FxnTable const *fxnTablePtr; - * void *object; - * void const *hwAttrs; - * } Capture_Config; - * @endcode - * - * The application must declare an array of Capture_Config elements, named - * Capture_config[]. Each element of Capture_config[] is populated with - * pointers to a device specific capture driver implementation's function - * table, driver object, and hardware attributes. The hardware attributes - * define properties such as the timer peripheral's base address, interrupt - * number and interrupt priority. Each element in Capture_config[] corresponds - * to a capture instance, and none of the elements should have NULL pointers. - * There is no correlation between the index and the peripheral designation. - * - * You will need to check the device specific capture driver implementation's - * header file for example configuration. - * - * ### Initializing the Capture Driver # - * - * Capture_init() must be called before any other capture APIs. This function - * calls the device implementation's capture initialization function, for each - * element of Capture_config[]. - * - * ### Modes of Operation # - * - * The capture driver supports four modes of operation which may be specified - * in the Capture_Params. - * - * #Capture_RISING_EDGE will capture rising edge triggers. After - * Capture_start() is called, the callback function specified in - * Capture_Params will be called after each rising edge is detected on the - * GPIO pin. This behavior will continue until Capture_stop() is called. - * - * #Capture_FALLING_EDGE will capture falling edge triggers. After - * Capture_start() is called, the callback function specified in - * Capture_Params will be called after each falling edge is detected on the - * GPIO pin. This behavior will continue until Capture_stop() is called. - * - * #Capture_ANY_EDGE will capture both rising and falling edge triggers. After - * Capture_start() is called, the callback function specified in - * Capture_Params will be called after each rising or falling edge is detected - * on the GPIO pin. This behavior will continue until Capture_stop() is - * called. - * - * # Implementation # - * - * The capture driver interface module is joined (at link time) to an - * array of Capture_Config data structures named *Capture_config*. - * Capture_config is implemented in the application with each entry being an - * instance of a capture peripheral. Each entry in *Capture_config* contains a: - * - (Capture_FxnTable *) to a set of functions that implement a capture - * peripheral - * - (void *) data object that is associated with the Capture_FxnTable - * - (void *) hardware attributes that are associated with the Capture_FxnTable - * - * The capture APIs are redirected to the device specific implementations - * using the Capture_FxnTable pointer of the Capture_config entry. - * In order to use device specific functions of the capture driver directly, - * link in the correct driver library for your device and include the - * device specific capture driver header file (which in turn includes - * Capture.h). For example, for the MSP432 family of devices, you would - * include the following header file: - * - * @code - * #include - * @endcode - * - ******************************************************************************* - */ - -#ifndef ti_drivers_Capture__include -#define ti_drivers_Capture__include - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include - -/*! - * Common Capture_control command code reservation offset. - * Capture driver implementations should offset command codes with - * Capture_CMD_RESERVED growing positively. - * - * Example implementation specific command codes: - * @code - * #define CaptureXYZ_CMD_COMMAND0 Capture_CMD_RESERVED + 0 - * #define CaptureXYZ_CMD_COMMAND1 Capture_CMD_RESERVED + 1 - * @endcode - */ -#define Capture_CMD_RESERVED (32) - -/*! - * Common Capture_control status code reservation offset. - * Capture driver implementations should offset status codes with - * Capture_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define CaptureXYZ_STATUS_ERROR0 Capture_STATUS_RESERVED - 0 - * #define CaptureXYZ_STATUS_ERROR1 Capture_STATUS_RESERVED - 1 - * @endcode - */ -#define Capture_STATUS_RESERVED (-32) - -/*! - * @brief Successful status code. - */ -#define Capture_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code. - */ -#define Capture_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by Capture_control() for undefined - * command codes. - * - * Capture_control() returns Capture_STATUS_UNDEFINEDCMD if the control code is - * not recognized by the driver implementation. - */ -#define Capture_STATUS_UNDEFINEDCMD (-2) - -/*! - * @brief A handle that is returned from a Capture_open() call. - */ -typedef struct Capture_Config_ *Capture_Handle; - - -/*! - * @brief Capture mode settings - * - * This enum defines the capture modes that may be specified in - * #Capture_Params. - */ -typedef enum Capture_Mode_ { - Capture_RISING_EDGE, /*!< Capture is triggered on rising edges. */ - Capture_FALLING_EDGE, /*!< Capture is triggered on falling edges. */ - Capture_ANY_EDGE /*!< Capture is triggered on both rising and - falling edges. */ -} Capture_Mode; - -/*! - * @brief Capture period unit enum - * - * This enum defines the units that may be specified for the period - * in #Capture_Params. - */ -typedef enum Capture_PeriodUnits_ { - Capture_PERIOD_US, /*!< Period specified in micro seconds. */ - Capture_PERIOD_HZ, /*!< Period specified in hertz; interrupts per - second. */ - Capture_PERIOD_COUNTS /*!< Period specified in timer ticks. Varies - by board. */ -} Capture_PeriodUnits; - - -/*! - * @brief Capture callback function - * - * User definable callback function prototype. The capture driver will call - * the defined function and pass in the capture driver's handle and the - * pointer to the user-specified the argument. - * - * @param handle Capture_Handle - * - * @param interval Interval of two triggering edges in - * #Capture_PeriodUnits - */ -typedef void (*Capture_CallBackFxn)(Capture_Handle handle, uint32_t interval); - -/*! - * @brief Capture Parameters - * - * Capture parameters are used by the Capture_open() call. Default values for - * these parameters are set using Capture_Params_init(). - * - */ -typedef struct Capture_Params_ { - /*! Mode to be used by the timer driver. */ - Capture_Mode mode; - - /*! Callback function called when a trigger event occurs. */ - Capture_CallBackFxn callbackFxn; - - /*! Units used to specify the interval. */ - Capture_PeriodUnits periodUnit; -} Capture_Params; - -/*! - * @brief A function pointer to a driver specific implementation of - * Capture_close(). - */ -typedef void (*Capture_CloseFxn)(Capture_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Capture_control(). - */ -typedef int_fast16_t (*Capture_ControlFxn)(Capture_Handle handle, - uint_fast16_t cmd, void *arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * Capture_init(). - */ -typedef void (*Capture_InitFxn)(Capture_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Capture_open(). - */ -typedef Capture_Handle (*Capture_OpenFxn)(Capture_Handle handle, - Capture_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * Capture_start(). - */ -typedef int32_t (*Capture_StartFxn)(Capture_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Capture_stop(). - */ -typedef void (*Capture_StopFxn)(Capture_Handle handle); - -/*! - * @brief The definition of a capture function table that contains the - * required set of functions to control a specific capture driver - * implementation. - */ -typedef struct Capture_FxnTable_ { - /*! Function to close the specified peripheral. */ - Capture_CloseFxn closeFxn; - - /*! Function to implementation specific control function. */ - Capture_ControlFxn controlFxn; - - /*! Function to initialize the given data object. */ - Capture_InitFxn initFxn; - - /*! Function to open the specified peripheral. */ - Capture_OpenFxn openFxn; - - /*! Function to start the specified peripheral. */ - Capture_StartFxn startFxn; - - /*! Function to stop the specified peripheral. */ - Capture_StopFxn stopFxn; -} Capture_FxnTable; - -/*! - * @brief Capture Global configuration - * - * The Capture_Config structure contains a set of pointers used to - * characterize the capture driver implementation. - * - * This structure needs to be defined before calling Capture_init() and it - * must not be changed thereafter. - * - * @sa Capture_init() - */ -typedef struct Capture_Config_ { - /*! Pointer to a table of driver-specific implementations of capture - APIs. */ - Capture_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver specific data object. */ - void *object; - - /*! Pointer to a driver specific hardware attributes structure. */ - void const *hwAttrs; -} Capture_Config; - -/*! - * @brief Function to close a capture driver instance. The corresponding - * timer peripheral to Capture_handle becomes an available resource. - * - * @pre Capture_open() has been called. - * - * @param handle A Capture_Handle returned from Capture_open(). - * - * @sa Capture_open() - */ -extern void Capture_close(Capture_Handle handle); - -/*! - * @brief Function performs implementation specific features on a given - * Capture_Handle. - * - * @pre Capture_open() has been called. - * - * @param handle A Capture_Handle returned from Capture_open(). - * - * @param cmd A command value defined by the driver specific - * implementation. - * - * @param arg A pointer to an optional R/W (read/write) argument that - * is accompanied with cmd. - * - * @return A Capture_Status describing an error or success state. Negative - * values indicate an error occurred. - * - * @sa Capture_open() - */ -extern int_fast16_t Capture_control(Capture_Handle handle, uint_fast16_t cmd, - void *arg); - -/*! - * @brief Function to initialize the capture driver. This function will go - * through all available hardware resources and mark them as - * "available". - * - * @pre The Capture_config structure must exist and be persistent before - * this function can be called. This function must also be called - * before any other capture driver APIs. - * - * @sa Capture_open() - */ -extern void Capture_init(void); - -/*! - * @brief Function to open a given capture instance specified by the - * index argument. The Capture_Params specifies which mode the capture - * instance will operate. This function takes care of capture resource - * allocation. If the particular timer hardware is available to use, - * the capture driver acquires it and returns a Capture_Handle. - * - * @pre Capture_init() has been called. - * - * @param index Logical instance number for the capture indexed into - * the Capture_config table. - * - * @param params Pointer to a parameter block. Cannot be NULL. - * - * @return A Capture_Handle on success, or NULL if the timer peripheral is - * already in use. - * - * @sa Capture_init() - * @sa Capture_close() - */ -extern Capture_Handle Capture_open(uint_least8_t index, Capture_Params *params); - -/*! - * @brief Function to initialize the Capture_Params struct to its defaults. - * - * @param params An pointer to Capture_Params structure for - * initialization. - * - * Defaults values are: - * callbackFxn = NULL - * mode = Capture_RISING_EDGE - * periodUnit = Capture_PERIOD_COUNTS - */ -extern void Capture_Params_init(Capture_Params *params); - -/*! - * @brief Function to start the capture instance. - * - * @pre Capture_open() has been called. - * - * @param handle A Capture_Handle returned from Capture_open(). - * - * @return Capture_STATUS_SUCCESS or Capture_STATUS_ERROR. - * - * @sa Capture_stop(). - * - */ -extern int32_t Capture_start(Capture_Handle handle); - -/*! - * @brief Function to stop a capture instance. If the capture instance is - * already stopped, this function has no effect. - * - * @pre Capture_open() has been called. - * - * @param handle A Capture_Handle returned from Capture_open(). - * - * @sa Capture_start() - */ -extern void Capture_stop(Capture_Handle handle); - -/* The following are included for backwards compatibility. These should not be - * used by the application. - */ -#define CAPTURE_CMD_RESERVED Capture_CMD_RESERVED -#define CAPTURE_STATUS_RESERVED Capture_STATUS_RESERVED -#define CAPTURE_STATUS_SUCCESS Capture_STATUS_SUCCESS -#define CAPTURE_STATUS_ERROR Capture_STATUS_ERROR -#define CAPTURE_STATUS_UNDEFINEDCMD Capture_STATUS_UNDEFINEDCMD -#define CAPTURE_MODE_RISING_RISING Capture_RISING_EDGE -#define CAPTURE_MODE_FALLING_FALLING Capture_FALLING_EDGE -#define CAPTURE_MODE_ANY_EDGE Capture_ANY_EDGE -#define CAPTURE_PERIOD_US Capture_PERIOD_US -#define CAPTURE_PERIOD_HZ Capture_PERIOD_HZ -#define CAPTURE_PERIOD_COUNTS Capture_PERIOD_COUNTS -#define Capture_Period_Unit Capture_PeriodUnits - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_Capture__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/GPIO.h b/ext/hal/ti/simplelink/source/ti/drivers/GPIO.h deleted file mode 100644 index 8ca49dd6f41..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/GPIO.h +++ /dev/null @@ -1,494 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file GPIO.h - * - * @brief GPIO driver - * - * The GPIO header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * # Overview # - * The GPIO module allows you to manage General Purpose I/O pins via simple - * and portable APIs. GPIO pin behavior is usually configured statically, - * but can also be configured or reconfigured at runtime. - * - * Because of its simplicity, the GPIO driver does not follow the model of - * other TI-RTOS drivers in which a driver application interface has - * separate device-specific implementations. This difference is most - * apparent in the GPIOxxx_Config structure, which does not require you to - * specify a particular function table or object. - * - * # Usage # - * The following code example demonstrates how - * to configure a GPIO pin to generate an interrupt and how to toggle an - * an LED on and off within the registered interrupt callback function. - * - * @code - * #include - * #include - * - * // Driver Header file - * #include - * - * // Example/Board Header file - * #include "Board.h" - * - * main() - * { - * // Call GPIO driver init function - * GPIO_init(); - * - * // Turn on user LED - * GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); - * - * // install Button callback - * GPIO_setCallback(Board_GPIO_BUTTON0, gpioButtonFxn0); - * - * // Enable interrupts - * GPIO_enableInt(Board_GPIO_BUTTON0); - * } - * - * // - * // ======== gpioButtonFxn0 ======== - * // Callback function for the GPIO interrupt on Board_GPIO_BUTTON0. - * // - * void gpioButtonFxn0(uint_least8_t index) - * { - * // Toggle the LED - * GPIO_toggle(Board_GPIO_LED0); - * } - * - * @endcode - * - * Details for the example code above are described in the following - * subsections. - * - * ### GPIO Driver Configuration # - * - * In order to use the GPIO APIs, the application is required - * to provide 3 structures in the Board.c file: - * 1. An array of @ref GPIO_PinConfig elements that defines the - * initial configuration of each pin used by the application. A - * pin is referenced in the application by its corresponding index in this - * array. The pin type (that is, INPUT/OUTPUT), its initial state (that is - * OUTPUT_HIGH or LOW), interrupt behavior (RISING/FALLING edge, etc.), and - * device specific pin identification are configured in each element - * of this array (see @ref GPIO_PinConfigSettings). - * Below is an MSP432 device specific example of the GPIO_PinConfig array: - * @code - * // - * // Array of Pin configurations - * // NOTE: The order of the pin configurations must coincide with what was - * // defined in MSP_EXP432P401R.h - * // NOTE: Pins not used for interrupts should be placed at the end of the - * // array. Callback entries can be omitted from callbacks array to - * // reduce memory usage. - * // - * GPIO_PinConfig gpioPinConfigs[] = { - * // Input pins - * // MSP_EXP432P401R_GPIO_S1 - * GPIOMSP432_P1_1 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING, - * // MSP_EXP432P401R_GPIO_S2 - * GPIOMSP432_P1_4 | GPIO_CFG_IN_PU | GPIO_CFG_IN_INT_FALLING, - * - * // Output pins - * // MSP_EXP432P401R_GPIO_LED1 - * GPIOMSP432_P1_0 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, - * // MSP_EXP432P401R_GPIO_LED_RED - * GPIOMSP432_P2_0 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, - * }; - * @endcode - * - * 2. An array of @ref GPIO_CallbackFxn elements that is used to store - * callback function pointers for GPIO pins configured with interrupts. - * The indexes for these array elements correspond to the pins defined - * in the GPIO_pinConfig array. These function pointers can be defined - * statically by referencing the callback function name in the array - * element, or dynamically, by setting the array element to NULL and using - * GPIO_setCallback() at runtime to plug the callback entry. - * Pins not used for interrupts can be omitted from the callback array to - * reduce memory usage (if they are placed at the end of GPIO_pinConfig - * array). The callback function syntax should match the following: - * @code - * void (*GPIO_CallbackFxn)(uint_least8_t index); - * @endcode - * The index parameter is the same index that was passed to - * GPIO_setCallback(). This allows the same callback function to be used - * for multiple GPIO interrupts, by using the index to identify the GPIO - * that caused the interrupt. - * Keep in mind that the callback functions will be called in the context of - * an interrupt service routine and should be designed accordingly. When an - * interrupt is triggered, the interrupt status of all (interrupt enabled) pins - * on a port will be read, cleared, and the respective callbacks will be - * executed. Callbacks will be called in order from least significant bit to - * most significant bit. - * Below is an MSP432 device specific example of the GPIO_CallbackFxn array: - * @code - * // - * // Array of callback function pointers - * // NOTE: The order of the pin configurations must coincide with what was - * // defined in MSP_EXP432P401R.h - * // NOTE: Pins not used for interrupts can be omitted from callbacks array - * // to reduce memory usage (if placed at end of gpioPinConfigs - * // array). - * // - * GPIO_CallbackFxn gpioCallbackFunctions[] = { - * // MSP_EXP432P401R_GPIO_S1 - * NULL, - * // MSP_EXP432P401R_GPIO_S2 - * NULL - * }; - * @endcode - * - * 3. A device specific GPIOxxx_Config structure that tells the GPIO - * driver where the two aforementioned arrays are and the number of elements - * in each. The interrupt priority of all pins configured to generate - * interrupts is also specified here. Values for the interrupt priority are - * device-specific. You should be well-acquainted with the interrupt - * controller used in your device before setting this parameter to a - * non-default value. The sentinel value of (~0) (the default value) is - * used to indicate that the lowest possible priority should be used. - * Below is an MSP432 device specific example of a GPIOxxx_Config - * structure: - * @code - * // - * // MSP432 specific GPIOxxx_Config structure - * // - * const GPIOMSP432_Config GPIOMSP432_config = { - * .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, - * .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, - * .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), - * .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), - * .intPriority = (~0) - * }; - * @endcode - * - * ### Initializing the GPIO Driver # - * - * GPIO_init() must be called before any other GPIO APIs. This function - * configures each GPIO pin in the user-provided @ref GPIO_PinConfig - * array according to the defined settings. The user can also reconfigure - * a pin dynamically after GPIO_init() is called by using the - * GPIO_setConfig(), and GPIO_setCallback() APIs. - * - * # Implementation # - * - * Unlike most other TI-RTOS drivers, the GPIO driver has no generic function - * table with pointers to device-specific API implementations. All the generic - * GPIO APIs are implemented by the device-specific GPIO driver module. - * Additionally, there is no notion of an instance 'handle' with the GPIO driver. - * GPIO pins are referenced by their numeric index in the GPIO_PinConfig array. - * This design approach was used to enhance runtime and memory efficiency. - * - * ============================================================================ - */ - -#ifndef ti_drivers_GPIO__include -#define ti_drivers_GPIO__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * @name GPIO_STATUS_* macros are general status codes returned by GPIO driver APIs. - * @{ - */ - -/*! - * @brief Common GPIO status code reservation offset. - * - * GPIO driver implementations should offset status codes with - * GPIO_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define GPIOTXYZ_STATUS_ERROR1 GPIO_STATUS_RESERVED - 1 - * #define GPIOTXYZ_STATUS_ERROR0 GPIO_STATUS_RESERVED - 0 - * #define GPIOTXYZ_STATUS_ERROR2 GPIO_STATUS_RESERVED - 2 - * @endcode - */ -#define GPIO_STATUS_RESERVED (-32) - -/*! - * @brief Successful status code returned by GPI_setConfig(). - * - * GPI_setConfig() returns GPIO_STATUS_SUCCESS if the API was executed - * successfully. - */ -#define GPIO_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by GPI_setConfig(). - * - * GPI_setConfig() returns GPIO_STATUS_ERROR if the API was not executed - * successfully. - */ -#define GPIO_STATUS_ERROR (-1) -/** @}*/ - -/*! - * @brief GPIO pin configuration settings - * - * The upper 16 bits of the 32 bit PinConfig is reserved - * for pin configuration settings. - * - * The lower 16 bits are reserved for device-specific - * port/pin identifications - */ -typedef uint32_t GPIO_PinConfig; - -/*! - * @cond NODOC - * Internally used configuration bit access macros. - */ -#define GPIO_CFG_IO_MASK 0x00ff0000 -#define GPIO_CFG_IO_LSB 16 -#define GPIO_CFG_OUT_TYPE_MASK 0x00060000 -#define GPIO_CFG_OUT_TYPE_LSB 17 -#define GPIO_CFG_IN_TYPE_MASK 0x00060000 -#define GPIO_CFG_IN_TYPE_LSB 17 -#define GPIO_CFG_OUT_STRENGTH_MASK 0x00f00000 -#define GPIO_CFG_OUT_STRENGTH_LSB 20 -#define GPIO_CFG_INT_MASK 0x07000000 -#define GPIO_CFG_INT_LSB 24 -#define GPIO_CFG_OUT_BIT 19 -/*! @endcond */ - -/*! - * \defgroup GPIO_PinConfigSettings Macros used to configure GPIO pins - * @{ - */ -/** @name GPIO_PinConfig output pin configuration macros - * @{ - */ -#define GPIO_CFG_OUTPUT (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an output. */ -#define GPIO_CFG_OUT_STD (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is actively driven high and low */ -#define GPIO_CFG_OUT_OD_NOPULL (((uint32_t) 2) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain */ -#define GPIO_CFG_OUT_OD_PU (((uint32_t) 4) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull up */ -#define GPIO_CFG_OUT_OD_PD (((uint32_t) 6) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Output pin is Open Drain w/ pull dn */ - -#define GPIO_CFG_OUT_STR_LOW (((uint32_t) 0) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strength to low */ -#define GPIO_CFG_OUT_STR_MED (((uint32_t) 1) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strength to medium */ -#define GPIO_CFG_OUT_STR_HIGH (((uint32_t) 2) << GPIO_CFG_OUT_STRENGTH_LSB) /*!< @hideinitializer Set output pin strength to high */ - -#define GPIO_CFG_OUT_HIGH (((uint32_t) 1) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 1. */ -#define GPIO_CFG_OUT_LOW (((uint32_t) 0) << GPIO_CFG_OUT_BIT) /*!< @hideinitializer Set pin's output to 0. */ -/** @} */ - -/** @name GPIO_PinConfig input pin configuration macros - * @{ - */ -#define GPIO_CFG_INPUT (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Pin is an input. */ -#define GPIO_CFG_IN_NOPULL (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with no internal PU/PD */ -#define GPIO_CFG_IN_PU (((uint32_t) 3) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PU */ -#define GPIO_CFG_IN_PD (((uint32_t) 5) << GPIO_CFG_IO_LSB) /*!< @hideinitializer Input pin with internal PD */ -/** @} */ - -/** @name GPIO_PinConfig interrupt configuration macros - * @{ - */ -#define GPIO_CFG_IN_INT_NONE (((uint32_t) 0) << GPIO_CFG_INT_LSB) /*!< @hideinitializer No Interrupt */ -#define GPIO_CFG_IN_INT_FALLING (((uint32_t) 1) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on falling edge */ -#define GPIO_CFG_IN_INT_RISING (((uint32_t) 2) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on rising edge */ -#define GPIO_CFG_IN_INT_BOTH_EDGES (((uint32_t) 3) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on both edges */ -#define GPIO_CFG_IN_INT_LOW (((uint32_t) 4) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on low level */ -#define GPIO_CFG_IN_INT_HIGH (((uint32_t) 5) << GPIO_CFG_INT_LSB) /*!< @hideinitializer Interrupt on high level */ -/** @} */ - -/** @name Special GPIO_PinConfig configuration macros - * @{ - */ - -/*! - * @brief 'Or' in this @ref GPIO_PinConfig definition to inform GPIO_setConfig() - * to only configure the interrupt attributes of a GPIO input pin. - */ -#define GPIO_CFG_IN_INT_ONLY (((uint32_t) 1) << 27) /*!< @hideinitializer configure interrupt only */ - -/*! - * @brief Use this @ref GPIO_PinConfig definition to inform GPIO_init() - * NOT to configure the corresponding pin - */ -#define GPIO_DO_NOT_CONFIG 0x40000000 /*!< @hideinitializer Do not configure this Pin */ - -/** @} */ -/** @} end of GPIO_PinConfigSettings group */ - -/*! - * @brief GPIO callback function type - * - * @param index GPIO index. This is the same index that - * was passed to GPIO_setCallback(). This allows - * you to use the same callback function for multiple - * GPIO interrupts, by using the index to identify - * the GPIO that caused the interrupt. - */ -typedef void (*GPIO_CallbackFxn)(uint_least8_t index); - -/*! - * @brief Clear a GPIO pin interrupt flag - * - * Clears the GPIO interrupt for the specified index. - * - * Note: It is not necessary to call this API within a - * callback assigned to a pin. - * - * @param index GPIO index - */ -extern void GPIO_clearInt(uint_least8_t index); - -/*! - * @brief Disable a GPIO pin interrupt - * - * Disables interrupts for the specified GPIO index. - * - * @param index GPIO index - */ -extern void GPIO_disableInt(uint_least8_t index); - -/*! - * @brief Enable a GPIO pin interrupt - * - * Enables GPIO interrupts for the selected index to occur. - * - * Note: Prior to enabling a GPIO pin interrupt, make sure - * that a corresponding callback function has been provided. - * Use the GPIO_setCallback() API for this purpose at runtime. - * Alternatively, the callback function can be statically - * configured in the GPIO_CallbackFxn array provided. - * - * @param index GPIO index - */ -extern void GPIO_enableInt(uint_least8_t index); - -/*! - * @brief Get the current configuration for a gpio pin - * - * The pin configuration is provided in the static GPIO_PinConfig array, - * but can be changed with GPIO_setConfig(). GPIO_getConfig() gets the - * current pin configuration. - * - * @param index GPIO index - * @param pinConfig Location to store device specific pin - * configuration settings - */ -extern void GPIO_getConfig(uint_least8_t index, GPIO_PinConfig *pinConfig); - -/*! - * @brief Initializes the GPIO module - * - * The pins defined in the application-provided *GPIOXXX_config* structure - * are initialized accordingly. - * - * @pre The GPIO_config structure must exist and be persistent before this - * function can be called. This function must also be called before - * any other GPIO driver APIs. - */ -extern void GPIO_init(); - -/*! - * @brief Reads the value of a GPIO pin - * - * The value returned will either be zero or one depending on the - * state of the pin. - * - * @param index GPIO index - * - * @return 0 or 1, depending on the state of the pin. - */ -extern uint_fast8_t GPIO_read(uint_least8_t index); - -/*! - * @brief Bind a callback function to a GPIO pin interrupt - * - * Associate a callback function with a particular GPIO pin interrupt. - * - * Callbacks can be changed at any time, making it easy to switch between - * efficient, state-specific interrupt handlers. - * - * Note: The callback function is called within the context of an interrupt - * handler. - * - * Note: This API does not enable the GPIO pin interrupt. - * Use GPIO_enableInt() and GPIO_disableInt() to enable - * and disable the pin interrupt as necessary. - * - * Note: it is not necessary to call GPIO_clearInt() within a callback. - * That operation is performed internally before the callback is invoked. - * - * @param index GPIO index - * @param callback address of the callback function - */ -extern void GPIO_setCallback(uint_least8_t index, GPIO_CallbackFxn callback); - -/*! - * @brief Configure the gpio pin - * - * Dynamically configure a gpio pin to a device specific setting. - * For many applications, the pin configurations provided in the static - * GPIO_PinConfig array is sufficient. - * - * For input pins with interrupt configurations, a corresponding interrupt - * object will be created as needed. - * - * @param index GPIO index - * @param pinConfig device specific pin configuration settings - */ -extern int_fast16_t GPIO_setConfig(uint_least8_t index, - GPIO_PinConfig pinConfig); - -/*! - * @brief Toggles the current state of a GPIO - * - * @param index GPIO index - */ -extern void GPIO_toggle(uint_least8_t index); - -/*! - * @brief Writes the value to a GPIO pin - * - * @param index GPIO index - * @param value must be either 0 or 1 - */ -extern void GPIO_write(uint_least8_t index, unsigned int value); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_GPIO__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/I2C.c b/ext/hal/ti/simplelink/source/ti/drivers/I2C.c deleted file mode 100644 index f28b2acb53f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/I2C.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== I2C.c ======== - */ - -#include -#include -#include - -#include -#include - -extern const I2C_Config I2C_config[]; -extern const uint_least8_t I2C_count; - -/* Default I2C parameters structure */ -const I2C_Params I2C_defaultParams = { - I2C_MODE_BLOCKING, /* transferMode */ - NULL, /* transferCallbackFxn */ - I2C_100kHz, /* bitRate */ - NULL /* custom */ -}; - -static bool isInitialized = false; - -/* - * ======== I2C_cancel ======== - */ -void I2C_cancel(I2C_Handle handle) -{ - handle->fxnTablePtr->cancelFxn(handle); -} - -/* - * ======== I2C_close ======== - */ -void I2C_close(I2C_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== I2C_control ======== - */ -int_fast16_t I2C_control(I2C_Handle handle, uint_fast16_t cmd, void *controlArg) -{ - return (handle->fxnTablePtr->controlFxn(handle, cmd, controlArg)); -} - -/* - * ======== I2C_init ======== - */ -void I2C_init(void) -{ - uint_least8_t i; - uint_fast32_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - for (i = 0; i < I2C_count; i++) { - I2C_config[i].fxnTablePtr->initFxn((I2C_Handle)&(I2C_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== I2C_open ======== - */ -I2C_Handle I2C_open(uint_least8_t index, I2C_Params *params) -{ - I2C_Handle handle = NULL; - - if (isInitialized && (index < I2C_count)) { - /* If params are NULL use defaults. */ - if (params == NULL) { - params = (I2C_Params *) &I2C_defaultParams; - } - - /* Get handle for this driver instance */ - handle = (I2C_Handle)&(I2C_config[index]); - handle = handle->fxnTablePtr->openFxn(handle, params); - } - - return (handle); -} - -/* - * ======== I2C_Params_init ======= - */ -void I2C_Params_init(I2C_Params *params) -{ - *params = I2C_defaultParams; -} - -/* - * ======== I2C_transfer ======== - */ -bool I2C_transfer(I2C_Handle handle, I2C_Transaction *transaction) -{ - return (handle->fxnTablePtr->transferFxn(handle, transaction)); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/I2C.h b/ext/hal/ti/simplelink/source/ti/drivers/I2C.h deleted file mode 100644 index 791f40ff66e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/I2C.h +++ /dev/null @@ -1,787 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!**************************************************************************** - * @file I2C.h - * @brief Inter-Integrated Circuit driver interface. - * - * The I2C header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * This module serves as the main interface for applications using an - * underlying I2C peripheral. Its purpose is to redirect the I2C APIs to - * device specific driver implementations which are specified using a pointer - * to a #I2C_FxnTable. - * - * # Overview # - * - * This section assumes that you have prior knowledge about the I2C protocol. - * For the full I2C-bus specification and user manual, view the \b UM10204 - * document available online. - * - * This I2C driver is designed to operate as an I2C master and will not - * function as an I2C slave. Multi-master arbitration is not supported; - * therefore, this driver assumes it is the only I2C master on the bus. - * This I2C driver's API set provides the ability to transmit and receive - * data over an I2C bus between the I2C master and I2C slave(s). The - * application is responsible for manipulating and interpreting the data. - * - * # Thread Safety # - * - * This driver has been designed to operate with a Real-Time Operating System - * (RTOS). All I2C APIs are globally thread safe. - * - * # I2C Driver Configuration # - * - * In order to use the I2C APIs, the application is required to provide - * device-specific I2C configuration in the Board.c file. The I2C driver - * interface defines a configuration data structure, #I2C_Config. - * - * The application must declare an array of #I2C_Config elements, named - * \p I2C_config[]. Each element of \p I2C_config[] is populated with - * pointers to a device specific I2C driver implementation's function - * table, driver object, and hardware attributes. The hardware attributes - * define properties such as the I2C peripheral's base address and - * pins. Each element in \p I2C_config[] corresponds to an I2C instance, - * and none of the elements should have \p NULL pointers. - * - * The I2C configuration is device dependent. You will need to check the - * device specific I2C driver documentation. There you will find a - * description of the I2C hardware attributes. - * - * # Usage # - * - * For general usage, refer to the function documentation. - * - * ## Initializing the I2C Driver ## - * - * I2C_init() must be called before any other I2C API. This function - * calls the device specific implementation's I2C initialization function - * for each element of \p I2C_config[]. - * - * ## Opening the I2C Driver ## - * - * After calling I2C_init(), the application can open an I2C instance by - * calling I2C_open(). This function takes an index into the \p I2C_config[] - * array and an #I2C_Params structure. The #I2C_Handle returned from the - * I2C_open() is then associated with that index into the \p I2C_config[] - * array. The following code example opens an I2C instance with default - * parameters by passing \p NULL for the #I2C_Params argument. - * - * @code - * I2C_Handle i2cHandle; - * - * i2cHandle = I2C_open(Board_I2C0, NULL); - * - * if (i2cHandle == NULL) { - * // Error opening I2C - * while (1) {} - * } - * @endcode - * - * \note Each I2C index can only be opened exclusively. Calling I2C_open() - * multiple times with the same index will result in an error. The index can - * be re-used if I2C_close() is called first. - * - * This example shows opening an I2C driver instance in #I2C_MODE_CALLBACK - * with a bit rate of #I2C_400kHz. - * - * @code - * void myCallbackFxn(I2C_Handle handle, I2C_Transaction *msg, bool status) - * { - * if (status == false) { - * //transfer failed - * } - * } - * @endcode - * - * @code - * I2C_Handle i2cHandle; - * I2C_Params i2cParams; - * - * I2C_Params_init(&i2cParams); - * - * i2cParams.transferMode = I2C_MODE_CALLBACK; - * i2cParams.transferCallbackFxn = myCallbackFxn; - * i2cParams.bitRate = I2C_400kHz; - * - * i2cHandle = I2C_open(Board_I2C0, &i2cParams); - * - * if (i2cHandle == NULL) { - * // Error opening I2C - * while (1); - * } - * @endcode - * - * ## Transferring data ## - * - * An I2C data transfer is performed using the I2C_transfer() function. Three - * types of transactions are supported: write, read, and write + read. The - * details of each transaction are specified with an #I2C_Transaction - * structure. Each transfer is completed before another transfer is initiated. - * - * For write + read transactions, the specified data is first written to the - * peripheral, then a repeated start is sent by the driver, which initiates - * the read operation. This type of transfer is useful if an I2C peripheral - * has a pointer register that needs to be adjusted prior to reading from - * the referenced data register. - * - * The following examples assume an I2C instance has been opened in - * #I2C_MODE_BLOCKING mode. - * - * --------------------------------------------------------------------------- - * - * Sending three bytes of data. - * - * @code - * I2C_Transaction i2cTransaction; - * uint8_t writeBuffer[3]; - * - * writeBuffer[0] = 0xAB; - * writeBuffer[1] = 0xCD; - * writeBuffer[2] = 0xEF; - * - * i2cTransaction.slaveAddress = 0x50; - * i2cTransaction.writeBuf = writeBuffer; - * i2cTransaction.writeCount = 3; - * i2cTransaction.readBuf = NULL; - * i2cTransaction.readCount = 0; - * - * status = I2C_transfer(i2cHandle, &i2cTransaction); - * - * if (status == false) { - * // Unsuccessful I2C transfer - * } - * @endcode - * - * Reading five bytes of data. - * - * @code - * I2C_Transaction i2cTransaction; - * uint8_t readBuffer[5]; - * - * i2cTransaction.slaveAddress = 0x50; - * i2cTransaction.writeBuf = NULL; - * i2cTransaction.writeCount = 0; - * i2cTransaction.readBuf = readBuffer; - * i2cTransaction.readCount = 5; - * - * status = I2C_transfer(i2cHandle, &i2cTransaction); - * - * if (status == false) { - * // Unsuccessful I2C transfer - * } - * @endcode - * - * Writing two bytes and reading four bytes in a single transaction. - * - * @code - * I2C_Transaction i2cTransaction; - * uint8_t readBuffer[4]; - * uint8_t writeBuffer[2]; - * - * writeBuffer[0] = 0xAB; - * writeBuffer[1] = 0xCD; - * - * i2cTransaction.slaveAddress = 0x50; - * i2cTransaction.writeBuf = writeBuffer; - * i2cTransaction.writeCount = 2; - * i2cTransaction.readBuf = readBuffer; - * i2cTransaction.readCount = 4; - * - * status = I2C_transfer(i2cHandle, &i2cTransaction); - * - * if (status == false) { - * // Unsuccessful I2C transfer - * } - * @endcode - * - * --------------------------------------------------------------------------- - * - * This final example shows usage of #I2C_MODE_CALLBACK, with queuing - * of multiple transactions. Because multiple transactions are simultaneously - * queued, separate #I2C_Transaction structures must be used. Each - * #I2C_Transaction will contain a custom application argument of a - * semaphore handle. The #I2C_Transaction.arg will point to the semaphore - * handle. When the callback function is called, the #I2C_Transaction.arg is - * checked for \p NULL. If this value is not \p NULL, then it can be assumed - * the \p arg is pointing to a valid semaphore handle. The semaphore handle - * is then used to call \p sem_post(). Hypothetically, this can be used to - * signal transaction completion to the task(s) that queued the - * transaction(s). - * - * @code - * void callbackFxn(I2C_Handle handle, I2C_Transaction *msg, bool status) - * { - * - * if (status == false) { - * //transaction failed - * } - * - * // Check for a semaphore handle - * if (msg->arg != NULL) { - * - * // Perform a semaphore post - * sem_post((sem_t *) (msg->arg)); - * } - * } - * @endcode - * - * Snippets of the thread code that initiates the transactions are shown below. - * Note the use of multiple #I2C_Transaction structures. The handle of the - * semaphore to be posted is specified via \p i2cTransaction2.arg. - * I2C_transfer() is called three times to initiate each transaction. - * Since callback mode is used, these functions return immediately. After - * the transactions have been queued, other work can be done. Eventually, - * \p sem_wait() is called causing the thread to block until the transaction - * completes. When the transaction completes, the application's callback - * function, \p callbackFxn will be called. Once \p callbackFxn posts the - * semaphore, the thread will be unblocked and can resume execution. - * - * @code - * void thread(arg0, arg1) - * { - * - * I2C_Transaction i2cTransaction0; - * I2C_Transaction i2cTransaction1; - * I2C_Transaction i2cTransaction2; - * - * // ... - * - * i2cTransaction0.arg = NULL; - * i2cTransaction1.arg = NULL; - * i2cTransaction2.arg = semaphoreHandle; - * - * // ... - * - * I2C_transfer(i2c, &i2cTransaction0); - * I2C_transfer(i2c, &i2cTransaction1); - * I2C_transfer(i2c, &i2cTransaction2); - * - * // ... - * - * sem_wait(semaphoreHandle); - * } - * @endcode - * - * # Implementation # - * - * This top-level I2C module serves as the main interface for RTOS - * applications. Its purpose is to redirect the module's APIs to specific - * peripheral implementations which are specified using a pointer to an - * #I2C_FxnTable. - * - * The I2C driver interface module is joined (at link time) to an - * array of #I2C_Config data structures named \p I2C_config. - * \p I2C_config is typically defined in the Board.c file used for the - * application. If there are multiple instances of I2C peripherals on the - * device, there will typically be multiple #I2C_Config structures defined in - * the board file in the form of an array. Each entry in \p I2C_config - * contains a: - * - #I2C_FxnTable pointer to a set of functions that implement an I2C - * peripheral. - * - (\p void *) data object that is associated with the #I2C_FxnTable - * - (\p void *) hardware attributes that are associated to the #I2C_FxnTable - * - * - ****************************************************************************** - */ - -#ifndef ti_drivers_I2C__include -#define ti_drivers_I2C__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * @defgroup I2C_CONTROL I2C_control command and status codes - * These I2C macros are reservations for I2C.h - * @{ - */ - -/*! - * Common I2C_control command code reservation offset. - * I2C driver implementations should offset command codes with - * #I2C_CMD_RESERVED growing positively - * - * Example implementation specific command codes: - * @code - * #define I2CXYZ_CMD_COMMAND0 I2C_CMD_RESERVED + 0 - * #define I2CXYZ_CMD_COMMAND1 I2C_CMD_RESERVED + 1 - * @endcode - */ -#define I2C_CMD_RESERVED (32) - -/*! - * Common I2C_control status code reservation offset. - * I2C driver implementations should offset status codes with - * #I2C_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define I2CXYZ_STATUS_ERROR0 I2C_STATUS_RESERVED - 0 - * #define I2CXYZ_STATUS_ERROR1 I2C_STATUS_RESERVED - 1 - * #define I2CXYZ_STATUS_ERROR2 I2C_STATUS_RESERVED - 2 - * @endcode - */ -#define I2C_STATUS_RESERVED (-32) - -/** - * @defgroup I2C_STATUS Status Codes - * I2C_STATUS_* macros are general status codes returned by I2C_control() - * @{ - * @ingroup I2C_CONTROL - */ - -/*! - * @brief Successful status code returned by I2C_control(). - * - * I2C_control() returns #I2C_STATUS_SUCCESS if the control code was executed - * successfully. - */ -#define I2C_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by I2C_control(). - * - * I2C_control() returns #I2C_STATUS_ERROR if the control code was not executed - * successfully. - */ -#define I2C_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by I2C_control() for undefined - * command codes. - * - * I2C_control() returns #I2C_STATUS_UNDEFINEDCMD if the control code is not - * recognized by the driver implementation. - */ -#define I2C_STATUS_UNDEFINEDCMD (-2) -/** @}*/ - -/** - * @defgroup I2C_CMD Command Codes - * I2C_CMD_* macros are general command codes for I2C_control(). Not all I2C - * driver implementations support these command codes. - * @{ - * @ingroup I2C_CONTROL - */ - -/* Add I2C_CMD_ here */ - -/** @} end I2C commands */ - -/** @} end I2C_CONTROL group */ - -/*! - * @brief A handle that is returned from an I2C_open() call. - */ -typedef struct I2C_Config_ *I2C_Handle; - -/*! - * @brief Structure used to perform I2C bus transfers. - * - * The application is responsible for allocating and initializing an - * I2C_Transaction structure prior to passing it to I2C_Transfer(). This - * structure must persist in memory unmodified until the transfer is complete. - * This driver will always perform write operations first. Transmission of the - * I2C slave address with the appropriate read/write bit is handled internally - * by this driver. - * - * \note #I2C_Transaction structures cannot be re-used until the previous - * transaction has completed. - * - * @sa I2C_transfer() - */ -typedef struct I2C_Transaction_ { - /*! Pointer to a buffer of at least \p writeCount bytes. If \p writeCount - * is 0, this pointer may remain uninitialized. */ - void *writeBuf; - /*! Number of bytes to write to the I2C slave device. A value of 0 - * indicates no data will be written to the slave device. */ - size_t writeCount; - /*! Pointer to a buffer of at least \p readCount bytes. If \p readCount - * is 0, this pointer may remain uninitialized. */ - void *readBuf; - /*! Number of bytes to read from the I2C slave device. A value of 0 - * indicates no data will be read from the slave device. */ - size_t readCount; - /*! I2C slave address of the slave device */ - uint_least8_t slaveAddress; - /*! Optional application argument. This argument will be passed to the - * callback function specified by #I2C_Params.transferCallbackFxn when - * using #I2C_MODE_CALLBACK. */ - void *arg; - /*! This is reserved for use by the driver and must never be modified by - * the application. */ - void *nextPtr; -} I2C_Transaction; - -/*! - * @brief Specifies the behavior of I2C_Transfer(). - * - * The I2C_TransferMode is specified using the #I2C_Params.transferMode field. - */ -typedef enum I2C_TransferMode_ { - /*! In blocking mode, a thread calling I2C_transfer() is blocked until the - * #I2C_Transaction completes. Other threads requesting I2C transactions - * while a transaction is in progress are also placed into a blocked state. - * If multiple threads are blocked, the thread with the highest priority - * will be unblocked first. This implies that queued blocked transactions - * will not be executed in chronological order. */ - I2C_MODE_BLOCKING, - /*! In callback mode, a thread calling I2C_transfer() is not blocked. The - * application's callback function, #I2C_Params.transferCallbackFxn, is - * called when the transaction is complete. The callback function will be - * called from either a hardware or software interrupt context. This - * depends on the device specific driver implementation. Sequential calls - * to I2C_transfer() will place #I2C_Transaction structures into an - * internal queue. Queued transactions are automatically started after the - * previous transaction has completed. This queuing occurs regardless of - * any error state from previous transactions. The transactions are - * always executed in chronological order. The - * #I2C_Params.transferCallbackFxn function will be called as each - * transaction is completed. */ - I2C_MODE_CALLBACK -} I2C_TransferMode; - -/*! - * @brief I2C callback function prototype. - * - * The application is responsible for declaring a callback function when - * #I2C_Params.transferMode is #I2C_MODE_CALLBACK. The callback function is - * specified using the #I2C_Params.transferCallbackFxn parameter. The - * callback function will be called from either a hardware or software - * interrupt context. - * - * @param handle #I2C_Handle to the I2C instance that called the - * I2C_transfer(). - * - * @param transaction Pointer to the #I2C_Transaction that just - * completed. - * - * @param transferStatus Boolean indicating if the I2C transaction was - * successful. False indicates the transaction did - * not complete. - */ -typedef void (*I2C_CallbackFxn)(I2C_Handle handle, I2C_Transaction *transaction, - bool transferStatus); - -/*! - * @brief Specifies the standard I2C bus bit rate. - * - * The I2C_BitRate is specified using the #I2C_Params.bitRate parameter. - * You must check that the device specific implementation supports the - * desired #I2C_BitRate. - */ -typedef enum I2C_BitRate_ { - - I2C_100kHz = 0, /*!< I2C Standard-mode. Up to 100 kbit/s. */ - I2C_400kHz = 1, /*!< I2C Fast-mode. Up to 400 kbit/s. */ - I2C_1000kHz = 2, /*!< I2C Fast-mode Plus. Up to 1Mbit/s. */ - I2C_3330kHz = 3, /*!< I2C High-speed mode. Up to 3.4Mbit/s. */ - I2C_3400kHz = 3, /*!< I2C High-speed mode. Up to 3.4Mbit/s. */ -} I2C_BitRate; - -/*! - * @brief I2C Parameters - * - * I2C parameters are used with the I2C_open() call. Default values for - * these parameters are set using I2C_Params_init(). - * - * \note The I2C_Params for a #I2C_Handle cannot be changed after I2C_open() - * has been called. The #I2C_Handle can be closed and re-opened with - * new parameters. See I2C_open() and I2C_close(). - * - * @sa I2C_open() - * @sa I2C_Params_init() - */ -typedef struct I2C_Params_ { - /*! Specifies the #I2C_TransferMode. Default is blocking. */ - I2C_TransferMode transferMode; - /*! #I2C_CallbackFxn pointer used when #I2C_TransferMode is - * #I2C_MODE_CALLBACK. */ - I2C_CallbackFxn transferCallbackFxn; - /*! #I2C_BitRate. Default is #I2C_100kHz.*/ - I2C_BitRate bitRate; - /*! Custom argument used by device specific driver implementations. */ - void *custom; -} I2C_Params; - -/*! - * @brief A function pointer to a driver-specific implementation of - * I2C_cancel(). - */ -typedef void (*I2C_CancelFxn) (I2C_Handle handle); - -/*! - * @brief A function pointer to a driver-specific implementation of - * I2C_close(). - */ -typedef void (*I2C_CloseFxn) (I2C_Handle handle); - -/*! - * @brief A function pointer to a driver-specific implementation of - * I2C_control(). - */ -typedef int_fast16_t (*I2C_ControlFxn) (I2C_Handle handle, uint_fast16_t cmd, - void *controlArg); - -/*! - * @brief A function pointer to a driver-specific implementation of - * I2C_init(). - */ -typedef void (*I2C_InitFxn) (I2C_Handle handle); - -/*! - * @brief A function pointer to a driver-specific implementation of - * I2C_open(). - */ -typedef I2C_Handle (*I2C_OpenFxn) (I2C_Handle handle, I2C_Params *params); - -/*! - * @brief A function pointer to a driver-specific implementation of - * I2C_transfer(). - */ -typedef bool (*I2C_TransferFxn) (I2C_Handle handle, - I2C_Transaction *transaction); - -/*! - * @brief The definition of an I2C function table that contains the - * required set of functions to control a specific I2C driver - * implementation. - */ -typedef struct I2C_FxnTable_ { - I2C_CancelFxn cancelFxn; - I2C_CloseFxn closeFxn; - I2C_ControlFxn controlFxn; - I2C_InitFxn initFxn; - I2C_OpenFxn openFxn; - I2C_TransferFxn transferFxn; -} I2C_FxnTable; - -/*! - * @brief I2C global configuration - * - * The #I2C_Config structure contains a set of pointers used to characterize - * the I2C driver implementation. - * - * This structure needs to be defined before calling I2C_init() and it must - * not be changed thereafter. - * - * @sa I2C_init() - */ -typedef struct I2C_Config_ { - /*! Pointer to a table of driver-specific implementations of I2C APIs */ - I2C_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver-specific data object */ - void *object; - - /*! Pointer to a driver-specific hardware attributes structure */ - void const *hwAttrs; -} I2C_Config; - -/*! - * @brief Cancels all I2C transfers - * - * This function will cancel asynchronous I2C_transfer() operations, and is - * applicable only for #I2C_MODE_CALLBACK mode. The in progress transfer, as - * well as any queued transfers, will be canceled. The individual callback - * functions for each transfer will be called in chronological order. The - * callback functions are called in the same context as the I2C_cancel(). - * - * @pre I2C_Transfer() has been called. - * - * @param handle An #I2C_Handle returned from I2C_open() - * - * @note Different I2C slave devices will behave differently when an - * in-progress transfer fails and needs to be canceled. The slave - * may need to be reset, or there may be other slave-specific - * steps that can be used to successfully resume communication. - * - * @sa I2C_transfer() - */ -extern void I2C_cancel(I2C_Handle handle); - -/*! - * @brief Close an I2C driver instance specified by an #I2C_Handle - * - * @pre I2C_open() has been called. - * - * @param handle An #I2C_Handle returned from I2C_open() - * - * @sa I2C_open() - */ -extern void I2C_close(I2C_Handle handle); - -/*! - * @brief Perform implementation-specific features on a given - * #I2C_Handle. - * - * Commands for I2C_control() can originate from I2C.h or from device specific - * implementations files. - * While commands from I2C.h are API portable across driver implementations, - * not all implementations may support all these commands. - * Conversely, commands from driver implementation specific I2C*.h files add - * unique driver capabilities but are not API portable across all I2C driver - * implementations. - * - * Commands supported by I2C.h follow a I2C_CMD_\ naming - * convention.
- * Commands supported by I2C.h follow a I2C_CMD_\ naming - * convention.
- * Each control command defines @b arg differently. The types of @b arg are - * documented with each command. - * - * See \ref I2C_CONTROL "I2C_control command codes" for command codes. - * - * See \ref I2C_STATUS "I2C_control return status codes" for status codes. - * - * @pre I2C_open() has to be called first. - * - * @param handle An #I2C_Handle returned from I2C_open() - * - * @param cmd \ref I2C_CONTROL command. - * - * @param controlArg An optional R/W (read/write) command argument - * accompanied with cmd - * - * @return Implementation-specific return codes. Negative values indicate - * unsuccessful operations. - * - * @sa I2C_open() - */ -extern int_fast16_t I2C_control(I2C_Handle handle, uint_fast16_t cmd, - void *controlArg); - -/*! - * @brief Initializes the I2C module - * - * @pre The \p I2C_config structure must exist and be persistent before this - * function can be called. This function must also be called before - * any other I2C driver APIs. This function call does not modify any - * peripheral registers. - */ -extern void I2C_init(void); - -/*! - * @brief Open an I2C instance - * - * Initialize a given I2C driver instance as identified by an index value. - * - * @pre I2C_init() has been called. - * - * @param index Indexed into the I2C_config table - * - * @param params Pointer to a parameter block. Default values will be - * used if \p NULL is specified for \p params. - * - * @return An #I2C_Handle on success, or \p NULL on an error. - * - * @sa I2C_init() - * @sa I2C_close() - */ -extern I2C_Handle I2C_open(uint_least8_t index, I2C_Params *params); - -/*! - * @brief Initialize an #I2C_Params structure to its default values. - * - * @param params A pointer to #I2C_Params structure for - * initialization. - * - * Defaults values are: - * - #I2C_Params.transferMode = #I2C_MODE_BLOCKING - * - #I2C_Params.transferCallbackFxn = \p NULL - * - #I2C_Params.bitRate = #I2C_100kHz - * - #I2C_Params.custom = \p NULL - */ -extern void I2C_Params_init(I2C_Params *params); - -/*! - * @brief Perform an I2C transaction with an I2C slave peripheral. - * - * This function will perform an I2C transfer, as specified by an - * #I2C_Transaction structure. - * - * The data written to the peripheral is preceded with the peripheral's 7-bit - * I2C slave address (with the Write bit set). - * After all the data has been transmitted, the driver will evaluate if any - * data needs to be read from the device. - * If yes, another START bit is sent, along with the same 7-bit I2C slave - * address (with the Read bit). After the specified number of bytes have been - * read, the transfer is ended with a NACK and a STOP bit. Otherwise, if - * no data is to be read, the transfer is concluded with a STOP bit. - * - * In #I2C_MODE_BLOCKING, I2C_transfer() will block thread execution until the - * transaction completes. When using blocking mode, this function must be - * called from a thread context. - * - * In #I2C_MODE_CALLBACK, the I2C_transfer() call does not block thread - * execution. Success or failure of the transaction is reported - * via the #I2C_CallbackFxn \b bool argument. If a transfer is already in - * progress, the new transaction is put on an internal queue. The driver - * services the queue in a first come first served basis. When using callback - * mode, this function can be called from any context. - * - * @param handle An #I2C_Handle - * - * @param transaction A pointer to an #I2C_Transaction. All of the fields - * within the transaction structure should be considered - * write only, unless otherwise noted in the driver - * implementation. - * - * @note The #I2C_Transaction structure must persist unmodified until the - * corresponding call to I2C_transfer() has completed. - * - * @return In #I2C_MODE_BLOCKING: \p true for a successful transfer; \p false - * for an error (for example, an I2C bus fault (NACK)). - * - * @return In #I2C_MODE_CALLBACK: always \p true. The #I2C_CallbackFxn \p bool - * argument will be \p true to indicate success, and \p false to - * indicate an error. - * - * @sa I2C_open() - */ -extern bool I2C_transfer(I2C_Handle handle, I2C_Transaction *transaction); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_I2C__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/I2S.c b/ext/hal/ti/simplelink/source/ti/drivers/I2S.c deleted file mode 100644 index 5f7496adfd3..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/I2S.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== I2S.c ======== - */ - -#include -#include -#include - -#include -#include - -extern const I2S_Config I2S_config[]; -extern const uint_least8_t I2S_count; - -/* Default I2S parameters structure */ -const I2S_Params I2S_defaultParams = { - I2S_OPMODE_TX_RX_SYNC, /* I2SMode */ - 16000, /* Sampling Freq */ - 16, /* Slot length */ - 16, /* Bits/Sample */ - 2, /* Mono/Stero */ - I2S_MODE_ISSUERECLAIM, /* Read mode */ - NULL, /* Read callback */ - I2S_WAIT_FOREVER, /* Read timeout */ - I2S_MODE_ISSUERECLAIM, /* Write mode */ - NULL, /* Write callback */ - I2S_WAIT_FOREVER, /* Write timeout */ - NULL /* customParams */ -}; - -static bool isInitialized = false; - -/* - * ======== I2S_close ======== - */ -void I2S_close(I2S_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== I2S_control ======== - */ -int_fast16_t I2S_control(I2S_Handle handle, uint_fast16_t cmd, void *arg) -{ - return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); -} - -/* - * ======== I2S_init ======== - */ -void I2S_init(void) -{ - uint_least8_t i; - uint_fast32_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - for (i = 0; i < I2S_count; i++) { - I2S_config[i].fxnTablePtr->initFxn((I2S_Handle)&(I2S_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== I2S_open ======== - */ -I2S_Handle I2S_open(uint_least8_t index, I2S_Params *params) -{ - I2S_Handle handle = NULL; - - if (isInitialized && (index < I2S_count)) { - /* If params are NULL use defaults. */ - if (params == NULL) { - params = (I2S_Params *) &I2S_defaultParams; - } - - /* Get handle for this driver instance */ - handle = (I2S_Handle)&(I2S_config[index]); - handle = handle->fxnTablePtr->openFxn(handle, params); - } - - return (handle); -} - -/* - * ======== I2S_Params_init ======== - */ -void I2S_Params_init(I2S_Params *params) -{ - *params = I2S_defaultParams; -} - -/* - * ======== I2S_read ======== - */ -int_fast16_t I2S_read(I2S_Handle handle, I2S_BufDesc *desc) -{ - return (handle->fxnTablePtr->readIssueFxn(handle, desc)); -} - -/* - * ======== I2S_readIssue ======== - */ -int_fast16_t I2S_readIssue(I2S_Handle handle, I2S_BufDesc *desc) -{ - return (handle->fxnTablePtr->readIssueFxn(handle, desc)); -} - -/* - * ======== I2S_readReclaim ======== - */ -size_t I2S_readReclaim(I2S_Handle handle, I2S_BufDesc **pDesc) -{ - return (handle->fxnTablePtr->readReclaimFxn(handle, pDesc)); -} - -/* - * ======== I2S_write ======== - */ -int_fast16_t I2S_write(I2S_Handle handle, I2S_BufDesc *desc) -{ - return (handle->fxnTablePtr->writeIssueFxn(handle, desc)); -} - -/* - * ======== I2S_writeIssue ======== - */ -int_fast16_t I2S_writeIssue(I2S_Handle handle, I2S_BufDesc *desc) -{ - return (handle->fxnTablePtr->writeIssueFxn(handle, desc)); -} - -/* - * ======== I2S_writeReclaim ======== - */ -size_t I2S_writeReclaim(I2S_Handle handle, I2S_BufDesc **pDesc) -{ - return (handle->fxnTablePtr->writeReclaimFxn(handle, pDesc)); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/I2S.h b/ext/hal/ti/simplelink/source/ti/drivers/I2S.h deleted file mode 100644 index 5405fc43bf2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/I2S.h +++ /dev/null @@ -1,764 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file I2S.h - * - * @brief I2S driver interface - * - * The I2S header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * # Overview # - * The I2S driver facilitates the use of Inter-IC Sound (I2S), which is - * used to connect digital audio devices so that audio signals can be - * communicated between devices. The I2S driver simplifies reading and - * writing to any of the Multichannel Audio Serial Port (McASP) peripherals - * on the board with Receive and Transmit support. These include blocking, - * non-blocking, read and write characters on the McASP peripheral. - * - * The APIs in this driver serve as an interface to a typical RTOS - * application. Its purpose is to redirect the I2S APIs to specific - * driver implementations which are specified using a pointer to an - * #I2S_FxnTable. - * The specific peripheral implementations are responsible - * for creating all the RTOS specific primitives to allow for thread-safe - * operation. - * - * # Usage # - * - * To use the I2S driver for reaading and writing data to the I2S peripheral, - * the application calls the following APIs: - * - I2S_init(): Initialize the I2S driver. - * - I2S_Params_init(): Initialize a #I2S_Params structure with default - * vaules. Then change the parameters from non-default values as - * needed. - * - I2S_open(): Open an instance of the I2S driver, passing the - * initialized parameters, or NULL, and an index (described later). - * - If using callback mode, I2S_read() and I2S_write(). - * - If using issue/reclaim mode, I2S_readIssue(), I2S_readReclaim(), - * I2S_writeIssue() and I2S_writeReclaim(). - * - I2S_close(): De-initialize the I2S instance. - * - * ### I2S Driver Configuration # - * - * In order to use the I2S APIs, the application is required - * to provide device-specific I2S configuration in the Board.c file. - * The I2S driver interface defines a configuration data structure: - * - * @code - * typedef struct I2S_Config_ { - * // Pointer to driver-specific implementation of I2S functions - * I2S_FxnTable const *fxnTablePtr; - * void *object; // Driver specific data object - * void const *hwAttrs; // Driver specific hardware attributes - * } I2S_Config; - * @endcode - * - * The application must declare an array of I2S_Config elements, named - * I2S_config[]. Each element of I2S_config[] must be populated with - * pointers to a device specific I2S driver implementation's function - * table, driver object, and hardware attributes. The hardware attributes - * define properties such as the I2S peripheral's base address and pins. - * Each element in I2S_config[] corresponds to an I2S instance, and - * and none of the elements should have NULL pointers. - * There is no correlation between the index and the peripheral - * designation (such as I2S0 or I2S1). For example, it is possible - * to use I2S_config[0] for I2S1. - * - * Because I2S configuration is very device dependent, you will need to - * check the doxygen for the device specific I2S implementation. There you - * will find a description of the I2S hardware attributes. Please also - * refer to the board.c file of any of your examples to see the I2S - * configuration. - * - * ### Initializing the I2S Driver # - * - * I2S_init() must be called before any other I2S APIs. This function - * iterates through the elements of the I2S_config[] array, calling - * the element's device implementation I2S initialization function. - * - * ### I2S Parameters - * - * The #I2S_Params structure is passed to the I2S_open() call. If NULL - * is passed for the parameters, I2S_open() uses default parameters. - * An #I2S_Params structure is initialized with default values by passing - * it to I2S_Params_init(). - * Some of the I2S parameters are described below. To see brief descriptions - * of all the parameters, see #I2S_Params. - * - * #### I2S Operation Mode - * The I2S operation mode determines whether transmit and/or receive modes - * are enabled. The mode is specified with one of the following constants: - * - #I2S_OPMODE_TX_ONLY: Enable transmit only. - * - #I2S_OPMODE_RX_ONLY: Enable receive only. - * - #I2S_OPMODE_TX_RX_SYNC: Enable both receive and transmit. - * - * #### I2S Data Mode - * A separate data mode may be specified for read calls and write calls. - * The available modes are: - * - #I2S_MODE_CALLBACK: This mode is non-blocking. Calls to I2S_read() or - * I2S_write() return immediately. When the transfer is finished, the - * user configured callback function is called. - * - #I2S_MODE_ISSUERECLAIM: Call I2S_readIssue() and I2S_writeIssue() to - * queue buffers to the I2S. I2S_readReclaim() blocks until a buffer - * of data is available. I2S_writeReclaim() blocks until a buffer of - * data has been issued and the descriptor can be returned back to the - * caller. - * - * ### Opening the I2S Driver # - * After initializing the I2S driver by calling I2S_init(), the application - * can open an I2S instance by calling I2S_open(). This function - * takes an index into the I2S_config[] array, and an I2S parameters data - * structure. The I2S instance is specified by the index of the I2S in - * I2S_config[]. Only one I2S index can be used at a time; - * calling I2S_open() a second time with the same index previosly - * passed to I2S_open() will result in an error. You can, - * though, re-use the index if the instance is closed via I2S_close(). - * - * If NULL is passed for the I2S_Params structure to I2S_open(), default values - * are used. If the open call is successful, it returns a non-NULL value. - * - * Example opening an I2S driver instance: - * @code - * I2S_Handle handle; - * I2S_Params params; - * - * I2S_Params_init(¶ms); - * params.operationMode = I2S_MODE_TX_RX_SYNC; - * - * handle = I2S_open(Board_I2S0, ¶ms); - * if (handle == NULL) { - * // Error opening I2S - * while (1); - * } - * @endcode - * - * ### Writing Data # - * The following example calls I2S_writeIssue() to write to an I2S driver - * instance that has been opened. It first queues up two buffers of text. - * Within an infinite loop, it calls I2S_writeReclaim() to retrieve a - * buffer and then re-queues the buffer. - * - * @code - * const unsigned char hello[] = "Hello World\n"; - * const unsigned char hello1[] = "Hello World1\n"; - * I2S_BufDesc writeBuffer1; - * I2S_BufDesc writeBuffer2; - * I2S_BufDesc *pDesc = NULL; - * - * writeBuffer1.bufPtr = &hello; - * writeBuffer1.bufSize = sizeof(hello); - * writeBuffer2.bufPtr = &hello1; - * writeBuffer2.bufSize = sizeof(hello1); - * - * ret = I2S_writeIssue(handle, &writeBuffer1); - * ret = I2S_writeIssue(handle, &writeBuffer2); - * - * while(1) { - * ret = I2S_writeReclaim(handle, &pDesc); - * pDesc->bufPtr = &hello;; - * pDesc->bufSize = sizeof(hello); - * ret = I2S_writeIssue(handle, pDesc); - * } - * - * @endcode - * - * ### Reading Data # - * The following example calls I2S_readIssue() to queue a buffer for - * reading from an I2S driver instance. It first queues up two buffers of - * text. Within an infinite loop, it then calls I2S_readReclaim() to retrieve - * a full buffer of data. - * - * @code - * unsigned char rxBuffer[20]; - * unsigned char rxBuffer1[20]; - * I2S_BufDesc readBuffer1; - * I2S_BufDesc readBuffer2; - * I2S_BufDesc *pDesc = NULL; - * - * readBuffer1.bufPtr = &rxBuffer; - * readBuffer1.bufSize = 20; - * readBuffer2.bufPtr = &rxBuffer1; - * readBuffer2.bufSize = 20; - * - * ret = I2S_readIssue(handle, &readBuffer1); - * ret = I2S_readIssue(handle, &readBuffer2); - * - * while(1) - * { - * ret = I2S_readReclaim(handle, &pDesc); - * pDesc->bufPtr = &rxBuffer; - * pDesc->bufSize = 20; - * ret = I2S_readIssue(handle, pDesc); - * } - * @endcode - * - * # Implementation # - * - * The I2S driver interface module is joined (at link time) to an - * array of I2S_Config data structures named *I2S_config*. - * *I2S_config* is implemented in the application with each entry being an - * instance of a I2S peripheral. Each entry in *I2S_config* contains a: - * - (I2S_FxnTable *) to a set of functions that implement a I2S peripheral - * - (void *) data object that is associated with the I2S_FxnTable - * - (void *) hardware attributes that are associated to the I2S_FxnTable - * - ******************************************************************************* - */ - -#ifndef ti_drivers_I2S__include -#define ti_drivers_I2S__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#include - -/** - * @defgroup I2S_CONTROL I2S_control command and status codes - * These I2S macros are reservations for I2S.h - * @{ - */ - -/*! - * Common I2S_control command code reservation offset. - * I2S driver implementations should offset command codes with I2S_CMD_RESERVED - * growing positively - * - * Example implementation specific command codes: - * @code - * #define I2SXYZ_CMD_COMMAND0 I2S_CMD_RESERVED + 0 - * #define I2SXYZ_CMD_COMMAND1 I2S_CMD_RESERVED + 1 - * @endcode - */ -#define I2S_CMD_RESERVED (32) - -/*! - * Common I2S_control status code reservation offset. - * I2S driver implementations should offset status codes with - * I2S_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define I2SXYZ_STATUS_ERROR0 I2S_STATUS_RESERVED - 0 - * #define I2SXYZ_STATUS_ERROR1 I2S_STATUS_RESERVED - 1 - * #define I2SXYZ_STATUS_ERROR2 I2S_STATUS_RESERVED - 2 - * @endcode - */ -#define I2S_STATUS_RESERVED (-32) - -/** - * @defgroup I2S_STATUS Status Codes - * I2S_STATUS_* macros are general status codes returned by I2S_control() - * @{ - * @ingroup I2S_CONTROL - */ - -/*! - * @brief Successful status code returned by I2S_control(). - * - * I2S_control() returns I2S_STATUS_SUCCESS if the control code was executed - * successfully. - */ -#define I2S_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by I2S_control(). - * - * I2S_control() returns I2S_STATUS_ERROR if the control code was not executed - * successfully. - */ -#define I2S_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by I2S_control() for undefined - * command codes. - * - * I2S_control() returns I2S_STATUS_UNDEFINEDCMD if the control code is not - * recognized by the driver implementation. - */ -#define I2S_STATUS_UNDEFINEDCMD (-2) -/** @}*/ - -/** - * @defgroup I2S_CMD Command Codes - * I2S_CMD_* macros are general command codes for I2S_control(). Not all I2S - * driver implementations support these command codes. - * @{ - * @ingroup I2S_CONTROL - */ - -/* Add I2S_CMD_ here */ - -/** @}*/ - -/** @}*/ - -#define I2S_ERROR (I2S_STATUS_ERROR) - -/*! - * @brief Wait forever define - */ -#define I2S_WAIT_FOREVER (~(0U)) - -/*! - * @brief A handle that is returned from a I2S_open() call. - */ -typedef struct I2S_Config_ *I2S_Handle; - -/*! - * @brief I2S buffer descriptor for issue/reclaim mode. - */ -typedef struct I2S_BufDesc_ { - - /*! Used internally to link descriptors together */ - List_Elem qElem; - - /*! Pointer to the buffer */ - void *bufPtr; - - /*! Size of the buffer (target MAUs). */ - size_t bufSize; - - /*! Optional argument associated with the descriptor. */ - uintptr_t descArg; -} I2S_BufDesc; - -/*! - * @brief The definition of a callback function used by the I2S driver - * when used in ::I2S_MODE_CALLBACK - * - * @param I2S_Handle I2S_Handle - * - * @param buf Pointer to read/write buffer - * - * @param count Number of elements read/written - */ -typedef void (*I2S_Callback)(I2S_Handle handle, I2S_BufDesc *desc); - -/*! - * @brief I2S mode settings - * - * This enum defines the read and write modes for the - * configured I2S. - */ -typedef enum I2S_DataMode_ { - /*! - * Non-blocking and will return immediately. When the transfer by the intr - * is finished the configured callback function is called. - */ - I2S_MODE_CALLBACK, - - /*! - * Use I2S_readIssue, I2S_writeIssue calls to queue buffers to the - * I2S. I2S_readReclaim() blocks until a buffer of data is available. - * I2S_writeReclaim() blocks until a buffer of data has been written - * and the descriptor can be returned back to the caller. - */ - I2S_MODE_ISSUERECLAIM -} I2S_DataMode; - -/*! - * @brief I2S mode settings - * - * This enumeration defines the mode for I2S operation. - */ -typedef enum I2S_OpMode_ { - I2S_OPMODE_TX_ONLY, /*!< Only Transmit enabled */ - I2S_OPMODE_RX_ONLY, /*!< Only Receive enabled */ - I2S_OPMODE_TX_RX_SYNC /*!< Receive and Transmit are enabled in Sync */ -} I2S_OpMode; - -/*! - * @brief I2S Serializer InActive state settings - * - * This enumeration defines the Serializer configuration - * in inactive state. - */ -typedef enum I2S_SerInActiveConfig_ { - I2S_SERCONFIG_INACT_TRI_STATE, /*!< Inactive state to tristate */ - I2S_SERCONFIG_INACT_LOW_LEVEL, /*!< Inactive state to low */ - I2S_SERCONFIG_INACT_HIGH_LEVEL /*!< Inactive state to high */ -} I2S_SerInActiveConfig; - -/*! - * @brief I2S serial pin mode - * - * This enumeration defines the Serial pin configuration - */ -typedef enum I2S_PinMode_ { - I2S_PINMODE_RX, /*!< Operate the pin in Rx mode */ - I2S_PINMODE_TX, /*!< Operate the pin in Tx mode */ - I2S_PINMODE_INACTIVE /*!< Pin in inactive mode */ -} I2S_PinMode; - -/*! - * @brief Basic I2S Parameters - * - * I2S parameters are used to with the I2S_open() call. Default values for - * these parameters are set using I2S_Params_init(). - * - * @sa I2S_Params_init() - */ -typedef struct I2S_Params_ { - I2S_OpMode operationMode; - /*!< I2S operational mode */ - - uint32_t samplingFrequency; - /*!< I2S sampling frequency configuration in samples/second */ - - uint8_t slotLength; - /*!< Slot length */ - - uint8_t bitsPerSample; - /*!< Bits per sample (Word length) */ - - uint8_t numChannels; - /*!< Number of channels (slots per frame) */ - - I2S_DataMode readMode; - /*!< Mode for all read calls */ - - I2S_Callback readCallback; - /*!< Pointer to read callback */ - - uint32_t readTimeout; - /*!< Timeout for read semaphore */ - - I2S_DataMode writeMode; - /*!< Mode for all write calls */ - - I2S_Callback writeCallback; - /*!< Pointer to write callback */ - - uint32_t writeTimeout; - /*!< Timeout for write semaphore */ - - void *customParams; - /*!< Pointer to device specific custom params */ -} I2S_Params; - -/*! - * @brief A function pointer to a driver specific implementation of - * I2S_CloseFxn(). - */ -typedef void (*I2S_CloseFxn) (I2S_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * I2S_control(). - */ -typedef int_fast16_t (*I2S_ControlFxn)(I2S_Handle handle, - uint_fast16_t cmd, - void *arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * I2S_init(). - */ -typedef void (*I2S_InitFxn)(I2S_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * I2S_OpenFxn(). - */ -typedef I2S_Handle (*I2S_OpenFxn)(I2S_Handle handle, I2S_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * I2S_IssueFxn(). - */ -typedef int_fast16_t (*I2S_IssueFxn)(I2S_Handle handle, I2S_BufDesc *desc); - -/*! - * @brief A function pointer to a driver specific implementation of - * I2S_ReclaimFxn(). - */ -typedef size_t (*I2S_ReclaimFxn)(I2S_Handle handle, I2S_BufDesc **desc); - -/*! - * @brief The definition of a I2S function table that contains the - * required set of functions to control a specific I2S driver - * implementation. - */ -typedef struct I2S_FxnTable_ { - /*! Function to close the specified peripheral */ - I2S_CloseFxn closeFxn; - - /*! Function to implementation specific control function */ - I2S_ControlFxn controlFxn; - - /*! Function to initialize the given data object */ - I2S_InitFxn initFxn; - - /*! Function to open the specified peripheral */ - I2S_OpenFxn openFxn; - - /*! Function to queue a buffer for reading from the specified peripheral */ - I2S_IssueFxn readIssueFxn; - - /*! Function to retrieve a received buffer of data from the specified peripheral */ - I2S_ReclaimFxn readReclaimFxn; - - /*! Function to queue a buffer for writing from the specified peripheral */ - I2S_IssueFxn writeIssueFxn; - - /*! Function to retrieve a sent buffer of data from the specified peripheral */ - I2S_ReclaimFxn writeReclaimFxn; - -} I2S_FxnTable; - -/*! @brief I2S Global configuration - * - * The I2S_Config structure contains a set of pointers used to characterize - * the I2S driver implementation. - * - * This structure needs to be defined before calling I2S_init() and it must - * not be changed thereafter. - * - * @sa I2S_init() - */ -typedef struct I2S_Config_ { - /*! Pointer to a table of a driver-specific implementation of I2S - functions */ - I2S_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver specific data object */ - void *object; - - /*! Pointer to a driver specific hardware attributes structure */ - void const *hwAttrs; -} I2S_Config; - -/*! - * @brief Function to close a given I2S peripheral specified by the I2S - * handle. - * - * @pre I2S_open() had to be called first. - * - * @param handle A I2S_Handle returned from I2S_open - * - * @sa I2S_open() - */ -extern void I2S_close(I2S_Handle handle); - -/*! - * @brief Function performs implementation specific features on a given - * I2S_Handle. - * - * Commands for I2S_control can originate from I2S.h or from - * implementation specific I2S*.h (_I2SCC32XX.h_, etc.. ) files. - * While commands from I2S.h are API portable across driver implementations, - * not all implementations may support all these commands. - * Conversely, commands from driver implementation specific I2S*.h files add - * unique driver capabilities but are not API portable across all I2S driver - * implementations. - * - * Commands supported by I2S.h follow a I2S_CMD_\ naming - * convention.
- * Commands supported by I2S*.h follow a I2S*_CMD_\ naming - * convention.
- * Each control command defines @b arg differently. The types of @b arg are - * documented with each command. - * - * See @ref I2S_CMD "I2S_control command codes" for command codes. - * - * See @ref I2S_STATUS "I2S_control return status codes" for status codes. - * - * @pre I2S_open() has to be called first. - * - * @param handle A I2S handle returned from I2S_open() - * - * @param cmd I2S.h or I2S*.h commands. - * - * @param arg An optional R/W (read/write) command argument - * accompanied with cmd - * - * @return Implementation specific return codes. Negative values indicate - * unsuccessful operations. - * - * @sa I2S_open() - */ -extern int_fast16_t I2S_control(I2S_Handle handle, - uint_fast16_t cmd, - void *arg); - -/*! - * @brief Function to initializes the I2S module - * - * @pre The I2S_config structure must exist and be persistent before this - * function can be called. This function must also be called before - * any other I2S driver APIs. This function call does not modify any - * peripheral registers. - */ -extern void I2S_init(void); - -/*! - * @brief Function to initialize a given I2S peripheral specified by the - * particular index value. The parameter specifies which mode the I2S - * will operate. - * - * @pre I2S controller has been initialized - * - * @param index Logical peripheral number for the I2S indexed into - * the I2S_config table - * - * @param params Pointer to an parameter block, if NULL it will use - * default values. All the fields in this structure are - * RO (read-only). - * - * @return A I2S_Handle on success or a NULL on an error or if it has been - * opened already. - * - * @sa I2S_init() - * @sa I2S_close() - */ -extern I2S_Handle I2S_open(uint_least8_t index, I2S_Params *params); - -/*! - * @brief Function to initialize the I2S_Params struct to its defaults - * - * @param params An pointer to I2S_Params structure for - * initialization - * - * Defaults values are: - * @code - * params.operationMode = #I2S_OPMODE_TX_RX_SYNC; - * params.samplingFrequency = 16000; - * params.slotLength = 16; - * params.bitsPerSample = 16; - * params.numChannels = 2; - * params.readMode = #I2S_MODE_ISSUERECLAIM; - * params.readCallback = NULL; - * params.readTimeout = #I2S_WAIT_FOREVER; - * params.writeMode = #I2S_MODE_ISSUERECLAIM; - * params.writeCallback = NULL; - * params.writeTimeout = #I2S_WAIT_FOREVER; - * params.customParams = NULL; - * @endcode - * - * @param params Parameter structure to initialize - */ -extern void I2S_Params_init(I2S_Params *params); - -/*! - * @brief Function to queue a buffer of data to the I2S in callback mode - * for reading. - * - * @param handle A I2S_Handle - * - * @param desc A pointer to a I2S_BufDesc object. The bufPtr - * and bufSize fields must be set to a buffer and the - * size of the buffer before passing to this function. - * @return Returns 0 if successful else would return - * I2S_STATUS_UNDEFINEDCMD on an error. - */ -extern int_fast16_t I2S_read(I2S_Handle handle, I2S_BufDesc *desc); - -/*! - - * @brief Function to queue a buffer of data to the I2S in Issue/Reclaim - * mode for reading. - * - * @param handle A I2S_Handle - * - * @param desc A pointer to a I2S_BufDesc object. The bufPtr - * and bufSize fields must be set to a buffer and the - * size of the buffer before passing to this function. - * @return Returns 0 if successful else would return - * I2S_STATUS_UNDEFINEDCMD on an error. - */ - -extern int_fast16_t I2S_readIssue(I2S_Handle handle, I2S_BufDesc *desc); - -/*! - * @brief Function to retrieve a full buffer of data read by the I2S. - * - * @param handle A I2S_Handle - * - * @param pDesc A pointer to a I2S_BufDesc pointer. - * - * @return Returns the number of bytes read from the I2S, or 0 on timeout. - */ -extern size_t I2S_readReclaim(I2S_Handle handle, I2S_BufDesc **pDesc); - -/*! - * @brief Function to queue a buffer of data to the I2S in - * callback mode for writing. - * - * @param handle A I2S_Handle - * - * @param desc A pointer to a I2S_BufDesc object. The bufPtr - * and bufSize fields must be set to a buffer and the - * size of the buffer before passing to this function. - * @return Returns 0 if successful else would return - * I2S_STATUS_UNDEFINEDCMD on an error. - */ -extern int_fast16_t I2S_write(I2S_Handle handle, I2S_BufDesc *desc); - -/*! - * @brief Function to queue a buffer of data to the I2S in - * Issue/Reclaim mode for writing. - * - * @param handle A I2S_Handle - * - * @param desc A pointer to a I2S_BufDesc object. The bufPtr - * and bufSize fields must be set to a buffer and the - * size of the buffer before passing to this function. - * @return Returns 0 if successful else would return - * I2S_STATUS_UNDEFINEDCMD on an error. - */ -extern int_fast16_t I2S_writeIssue(I2S_Handle handle, I2S_BufDesc *desc); - -/*! - * @brief Function to retrieve a buffer that the I2S has finished writing. - * - * @param handle A I2S_Handle - * - * @param pDesc A pointer to a I2S_BufDesc pointer. - * - * @return Returns the number of bytes that have been written to the I2S, - * 0 on timeout. - */ -extern size_t I2S_writeReclaim(I2S_Handle handle, I2S_BufDesc **pDesc); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_I2S__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/NVS.c b/ext/hal/ti/simplelink/source/ti/drivers/NVS.c deleted file mode 100644 index 5737ff0512a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/NVS.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * ======== NVS.c ======== - */ -#include -#include -#include -#include - -#include -#include - -extern NVS_Config NVS_config[]; -extern const uint8_t NVS_count; - -static bool isInitialized = false; - -/* Default NVS parameters structure */ -const NVS_Params NVS_defaultParams = { - NULL /* custom */ -}; - -/* - * ======== NVS_close ======= - */ -void NVS_close(NVS_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== NVS_control ======== - */ -int_fast16_t NVS_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg) -{ - return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); -} - -/* - * ======== NVS_erase ======= - */ -int_fast16_t NVS_erase(NVS_Handle handle, size_t offset, size_t size) -{ - return (handle->fxnTablePtr->eraseFxn(handle, offset, size)); -} - -/* - * ======== NVS_getAttrs ======= - */ -void NVS_getAttrs(NVS_Handle handle, NVS_Attrs *attrs) -{ - handle->fxnTablePtr->getAttrsFxn(handle, attrs); -} - -/* - * ======== NVS_init ======= - */ -void NVS_init(void) -{ - uint_least8_t i; - - /* Call each driver's init function */ - for (i = 0; i < NVS_count; i++) { - NVS_config[i].fxnTablePtr->initFxn(); - } - - isInitialized = true; -} - -/* - * ======== NVS_open ======= - */ -NVS_Handle NVS_open(uint_least8_t index, NVS_Params *params) -{ - NVS_Handle handle = NULL; - - /* do init if not done yet */ - if (!isInitialized) { - NVS_init(); - } - - if (index < NVS_count) { - if (params == NULL) { - /* No params passed in, so use the defaults */ - params = (NVS_Params *)&NVS_defaultParams; - } - handle = NVS_config[index].fxnTablePtr->openFxn(index, params); - } - - return (handle); -} - -/* - * ======== NVS_Params_init ======= - */ -void NVS_Params_init(NVS_Params *params) -{ - *params = NVS_defaultParams; -} - -/* - * ======== NVS_read ======= - */ -int_fast16_t NVS_read(NVS_Handle handle, size_t offset, void *buffer, - size_t bufferSize) -{ - return (handle->fxnTablePtr->readFxn(handle, offset, buffer, bufferSize)); -} - -/* - * ======== NVS_write ======= - */ -int_fast16_t NVS_write(NVS_Handle handle, size_t offset, void *buffer, - size_t bufferSize, uint_fast16_t flags) -{ - return (handle->fxnTablePtr->writeFxn(handle, offset, buffer, - bufferSize, flags)); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/NVS.h b/ext/hal/ti/simplelink/source/ti/drivers/NVS.h deleted file mode 100644 index 2ac1cbc977e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/NVS.h +++ /dev/null @@ -1,769 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!**************************************************************************** - * @file NVS.h - * @brief Non-Volatile Storage driver interface - * - * To use the NVS driver, ensure that the correct driver library for your - * device is linked in and include this header file as follows: - * @code - * #include - * @endcode - * - * This module serves as the main interface for applications. Its purpose - * is to redirect the NVS APIs to specific driver implementations - * which are specified using a pointer to a #NVS_FxnTable. - * - * # Overview # - * - * The NVS module allows you to manage non-volatile memory. Using the - * NVS APIs, you can read and write data from and to persistent storage. - * - * Each NVS object manages a region of non-volatile memory. The size is - * specified in the device specific driver's hardware attributes. A sector - * is the smallest unit of non-volatile storage that can be erased at - * one time. The size of the sector, or sector size, is hardware specific and - * may be meaningless for some non-volatile storage hardware. For flash - * memory devices, the region must be aligned with the sector size. That is, - * the region must start on a sector boundary. Additionally, the overall size - * of the region must be an integer multiple of the sector size. - * - * # Thread Safety # - * - * All NVS APIs are globally thread safe. Consequently, only one write, - * erase, or read in the case of SPI flash operation is allowed to be - * performed at a time, even for distinct NVS regions. Threads initiating - * new NVS writes or erases will block until any current operation completes. - * - * # Interrupt Latency During Flash Operations # - * - * When writing to or erasing internal flash, interrupts must be disabled - * to avoid executing code in flash while the flash is being reprogrammed. - * This constraint is met internally by the driver. User code does not need - * to safeguard against this. - * - * Care must be taken by the user to not perform flash write or erase - * operations during latency critical phases of an application. See the - * NVS_lock() and NVS_unlock() API descriptions for more information. - * - * # Usage # - * - * The NVS driver interface provides device independent APIs, data types, - * and macros. The following code example opens an NVS region instance, - * writes a string into it, then prints the string after reading it back - * into a local buffer, and also prints the string from its directly - * addressable location in flash memory. - * - * @code - * NVS_Handle rHandle; - * NVS_Attrs regionAttrs; - * NVS_Params nvsParams; - * uint_fast16_t status; - * char buf[32]; - * - * // Initialize the NVS driver - * NVS_init(); - * - * // - * // Open the NVS region specified by the 0 element in the NVS_config[] - * // array defined in Board.c. - * // Use default NVS_Params to open this memory region, hence NULL - * // - * rHandle = NVS_open(Board_NVSINTERNAL, NULL); - * - * // confirm that the NVS region opened properly - * if (rHandle == NULL) { - * // Error opening NVS driver - * while (1); - * } - * - * // fetch the generic NVS region attributes - * NVS_getAttrs(rHandle, ®ionAttrs); - * - * // erase the first sector of the NVS region - * status = NVS_erase(rHandle, 0, regionAttrs.sectorSize); - * if (status != NVS_STATUS_SUCCESS) { - * // Error handling code - * } - * - * // write "Hello" to the base address of region 0, verify after write - * status = NVS_write(rHandle, 0, "Hello", strlen("Hello")+1, NVS_POST_VERIFY); - * if (status != NVS_STATUS_SUCCESS) { - * // Error handling code - * } - * - * // copy "Hello" from region0 into local 'buf' - * status = NVS_read(rHandle, 0, buf, strlen("Hello")+1); - * if (status != NVS_STATUS_SUCCESS) { - * // Error handling code - * } - * - * // print string from fetched NVS storage - * System_printf("%s\n", buf); - * - * // print string using direct address reference if valid - * if (regionAttrs.regionBase != NVS_REGION_NOT_ADDRESSABLE) { - * System_printf("%s\n", regionAttrs.regionBase); - * } - * - * // close the region - * NVS_close(rHandle); - * - * @endcode - * - * Details for the example code above are described in the following - * subsections. - * - * ### NVS Driver Configuration # - * - * In order to use the NVS APIs, the application is required - * to provide device-specific NVS configuration in the Board.c file. - * The NVS driver interface defines a configuration data structure, - * #NVS_Config. - * - * The application must declare an array of #NVS_Config elements, named - * \p NVS_config[]. Each element of \p NVS_config[] is populated with - * pointers to a device specific NVS driver implementation's function - * table, driver object, and hardware attributes. The hardware attributes - * define properties such as the NVS region's base address and size, - * Each element in \p NVS_config[] corresponds to a NVS instance, and none - * of the elements should have NULL pointers. - * - * You will need to check the device-specific NVS driver implementation's - * header file for example configuration. Please also refer to the - * Board.c file of any of the provided examples to see the NVS configuration. - * - * ### Initializing the NVS Driver # - * - * NVS_init() must be called before any other NVS APIs. This function - * calls the device implementation's NVS initialization function, for each - * element of \p NVS_config[]. - * - * ### Opening the NVS Driver # - * - * Opening a NVS requires four steps: - * 1. Optionally create and initialize a #NVS_Params structure. - * 2. Fill in the desired parameters. - * 3. Call NVS_open(), passing the index of the NVS region in the #NVS_Config - * structure, and the address of the #NVS_Params structure. - * 4. Check that the #NVS_Handle returned by NVS_open() is non-NULL, - * and save it. The handle will be used to read and write to the - * NVS you just opened. - * - * \note Each NVS index can only be opened exclusively. Calling NVS_open() - * multiple times with the same index will result in an error. The index can - * be re-used if NVS_close() is called first. - * - ***************************************************************************** - */ - -#ifndef ti_drivers_NVS__include -#define ti_drivers_NVS__include - -#include -#include -#include - -#if defined (__cplusplus) -extern "C" { -#endif - -/** - * @defgroup NVS_CONTROL NVS_control command and status codes - * These NVS macros are reservations for NVS.h - * @{ - */ - -/*! - * Common NVS_control command code reservation offset. - * NVS driver implementations should offset command codes with NVS_CMD_RESERVED - * growing positively - * - * Example implementation specific command codes: - * @code - * #define NVSXYZ_CMD_COMMAND0 NVS_CMD_RESERVED + 0 - * #define NVSXYZ_CMD_COMMAND1 NVS_CMD_RESERVED + 1 - * @endcode - */ -#define NVS_CMD_RESERVED (32) - -/*! - * Common NVS_control status code reservation offset. - * NVS driver implementations should offset status codes with - * NVS_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define NVSXYZ_STATUS_ERROR0 NVS_STATUS_RESERVED - 0 - * #define NVSXYZ_STATUS_ERROR1 NVS_STATUS_RESERVED - 1 - * #define NVSXYZ_STATUS_ERROR2 NVS_STATUS_RESERVED - 2 - * @endcode - */ -#define NVS_STATUS_RESERVED (-32) - -/** - * @defgroup NVS_STATUS Status Codes - * NVS_STATUS_* macros are general status codes returned by NVS_control() - * @{ - * @ingroup NVS_CONTROL - */ - -/*! - * @brief Successful status code returned by: - * NVS_control(), NVS_read(), NVS_write(), NVS_erase(), or - * NVS_lock(). - * - * APIs returns NVS_STATUS_SUCCESS if the API was executed - * successfully. - */ -#define NVS_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by: - * NVS_control(), NVS_erase(), or NVS_write(), - * - * APIs return NVS_STATUS_ERROR if the API was not executed - * successfully. - */ -#define NVS_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by NVS_control() for undefined - * command codes. - * - * NVS_control() returns #NVS_STATUS_UNDEFINEDCMD if the control code is not - * recognized by the driver implementation. - */ -#define NVS_STATUS_UNDEFINEDCMD (-2) - -/*! - * @brief An error status code returned by NVS_lock() - * - * NVS_lock() will return this value if the \p timeout has expired - */ -#define NVS_STATUS_TIMEOUT (-3) - -/*! - * @brief An error status code returned by NVS_read(), NVS_write(), or - * NVS_erase() - * - * Error status code returned if the \p offset argument is invalid - * (e.g., when offset + bufferSize exceeds the size of the region). - */ -#define NVS_STATUS_INV_OFFSET (-4) - -/*! - * @brief An error status code - * - * Error status code returned by NVS_erase() if the \p offset argument is - * not aligned on a flash sector address. - */ -#define NVS_STATUS_INV_ALIGNMENT (-5) - -/*! - * @brief An error status code returned by NVS_erase() and NVS_write() - * - * Error status code returned by NVS_erase() if the \p size argument is - * not a multiple of the flash sector size, or if \p offset + \p size - * extends past the end of the region. - */ -#define NVS_STATUS_INV_SIZE (-6) - -/*! - * @brief An error status code returned by NVS_write() - * - * NVS_write() will return this value if #NVS_WRITE_PRE_VERIFY is - * requested and a flash location can not be changed to the value - * desired. - */ -#define NVS_STATUS_INV_WRITE (-7) - -/** @}*/ - -/** - * @defgroup NVS_CMD Command Codes - * NVS_CMD_* macros are general command codes for NVS_control(). Not all NVS - * driver implementations support these command codes. - * @{ - * @ingroup NVS_CONTROL - */ - -/* Add NVS_CMD_ here */ - -/** @} end NVS commands */ - -/** @} end NVS_CONTROL group */ - - -/*! - * @brief NVS write flags - * - * The following flags can be or'd together and passed as a bit mask - * to NVS_write. - * @{ - */ - -/*! - * @brief Erase write flag. - * - * If #NVS_WRITE_ERASE is set in the flags passed to NVS_write(), the - * affected destination flash sectors will be erased prior to the - * start of the write operation. - */ -#define NVS_WRITE_ERASE (0x1) - -/*! - * @brief Validate write flag. - * - * If #NVS_WRITE_PRE_VERIFY is set in the flags passed to NVS_write(), the - * destination address range will be pre-tested to guarantee that the source - * data can be successfully written. If #NVS_WRITE_ERASE is also requested in - * the write flags, then the #NVS_WRITE_PRE_VERIFY modifier is ignored. - */ -#define NVS_WRITE_PRE_VERIFY (0x2) - -/*! - * @brief Validate write flag. - * - * If #NVS_WRITE_POST_VERIFY is set in the flags passed to NVS_write(), the - * destination address range will be tested after the write is finished to - * verify that the write operation was completed successfully. - */ -#define NVS_WRITE_POST_VERIFY (0x4) - -/** @} */ - -/*! - * @brief Special NVS_lock() timeout values - * @{ - */ - - /*! - * @brief NVS_lock() Wait forever define - */ -#define NVS_LOCK_WAIT_FOREVER (~(0U)) - -/*! - * @brief NVS_lock() No wait define - */ -#define NVS_LOCK_NO_WAIT (0U) - -/** @} */ - -/*! - * @brief Special NVS_Attrs.regionBase value - * @{ - */ - - /*! - * @brief This region is not directly addressable (e.g.,: SPI flash region) - * - * The NVS_Attrs.regionBase field returned by NVS_getAttrs() is set to this - * value by the NVSSPI driver to indicate that the region is not directly - * addressable. - */ -#define NVS_REGION_NOT_ADDRESSABLE ((void *)(~(0U))) - -/** @} */ - -/*! - * @brief NVS Parameters - * - * NVS parameters are used with the NVS_open() call. Default values for - * these parameters are set using NVS_Params_init(). - * - * @sa NVS_Params_init() - */ -typedef struct NVS_Params { - void *custom; /*!< Custom argument used by driver implementation */ -} NVS_Params; - -/*! - * @brief NVS attributes - * - * The address of an NVS_Attrs structure is passed to NVS_getAttrs(). - * - * @sa NVS_getAttrs() - */ -typedef struct NVS_Attrs { - void *regionBase; /*!< Base address of the NVS region. If the NVS - region is not directly accessible by the MCU - (such as SPI flash), this field will be set to - #NVS_REGION_NOT_ADDRESSABLE. */ - size_t regionSize; /*!< NVS region size in bytes. */ - size_t sectorSize; /*!< Erase sector size in bytes. This attribute is - device specific. */ -} NVS_Attrs; - -/*! - * @brief A handle that is returned from the NVS_open() call. - */ -typedef struct NVS_Config_ *NVS_Handle; - -/*! - * @brief A function pointer to a driver specific implementation of - * NVS_close(). - */ -typedef void (*NVS_CloseFxn) (NVS_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * NVS_control(). - */ -typedef int_fast16_t (*NVS_ControlFxn) (NVS_Handle handle, uint_fast16_t cmd, - uintptr_t arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * NVS_erase(). - */ -typedef int_fast16_t (*NVS_EraseFxn) (NVS_Handle handle, size_t offset, - size_t size); - -/*! - * @brief A function pointer to a driver specific implementation of - * NVS_getAttrs(). - */ -typedef void (*NVS_GetAttrsFxn) (NVS_Handle handle, NVS_Attrs *attrs); - -/*! - * @brief A function pointer to a driver specific implementation of - * NVS_init(). - */ -typedef void (*NVS_InitFxn) (void); - -/*! - * @brief A function pointer to a driver specific implementation of - * NVS_open(). - */ -typedef NVS_Handle (*NVS_OpenFxn) (uint_least8_t index, NVS_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * NVS_read(). - */ -typedef int_fast16_t (*NVS_ReadFxn) (NVS_Handle handle, size_t offset, - void *buffer, size_t bufferSize); - -/*! - * @brief A function pointer to a driver specific implementation of - * NVS_write(). - */ -typedef int_fast16_t (*NVS_WriteFxn) (NVS_Handle handle, size_t offset, - void *buffer, size_t bufferSize, - uint_fast16_t flags); - -/*! - * @brief A function pointer to a driver specific implementation of - * NVS_lock(). - */ -typedef int_fast16_t (*NVS_LockFxn) (NVS_Handle handle, uint32_t timeout); - -/*! - * @brief A function pointer to a driver specific implementation of - * NVS_unlock(). - */ -typedef void (*NVS_UnlockFxn) (NVS_Handle handle); - -/*! - * @brief The definition of an NVS function table that contains the - * required set of functions to control a specific NVS driver - * implementation. - */ -typedef struct NVS_FxnTable { - /*! Function to close the specified NVS region */ - NVS_CloseFxn closeFxn; - - /*! Function to apply control command to the specified NVS region */ - NVS_ControlFxn controlFxn; - - /*! Function to erase a portion of the specified NVS region */ - NVS_EraseFxn eraseFxn; - - /*! Function to get the NVS device-specific attributes */ - NVS_GetAttrsFxn getAttrsFxn; - - /*! Function to initialize the NVS module */ - NVS_InitFxn initFxn; - - /*! Function to lock the specified NVS flash region */ - NVS_LockFxn lockFxn; - - /*! Function to open an NVS region */ - NVS_OpenFxn openFxn; - - /*! Function to read from the specified NVS region */ - NVS_ReadFxn readFxn; - - /*! Function to unlock the specified NVS flash region */ - NVS_UnlockFxn unlockFxn; - - /*! Function to write to the specified NVS region */ - NVS_WriteFxn writeFxn; -} NVS_FxnTable; - -/*! - * @brief NVS Global configuration - * - * The NVS_Config structure contains a set of pointers used to characterize - * the NVS driver implementation. - * - * This structure needs to be defined before calling NVS_init() and it must - * not be changed thereafter. - * - * @sa NVS_init() - */ -typedef struct NVS_Config_ { - /*! Pointer to a table of driver-specific implementations of NVS APIs */ - NVS_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver specific data object */ - void *object; - - /*! Pointer to a driver specific hardware attributes structure */ - void const *hwAttrs; -} NVS_Config; - -/*! - * @brief Function to close an #NVS_Handle. - * - * @param handle A handle returned from NVS_open() - * - * @sa NVS_open() - */ -extern void NVS_close(NVS_Handle handle); - -/*! - * @brief Function performs implementation specific features on a given - * #NVS_Handle. - * - * @pre NVS_open() must be called first. - * - * @param handle An #NVS_Handle returned from NVS_open() - * - * @param cmd A command value defined by the driver specific - * implementation - * - * @param arg An optional read or write argument that is - * accompanied with \p cmd - * - * @return Implementation specific return codes. Negative values indicate - * unsuccessful operations. - * - * @sa NVS_open() - */ -extern int_fast16_t NVS_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg); - -/*! - * @brief Erase \p size bytes of the region beginning at \p offset bytes - * from the base of the region referenced by the #NVS_Handle. - * - * @warning Erasing internal flash on most devices can introduce - * significant interrupt latencies while the erase operation is in - * in progress. The user may want to surround certain real-time - * critical code sections with NVS_lock() and NVS_unlock() calls in order - * to prevent uncoordinated flash erase operations from negatively - * impacting performance. - * - * @param handle A handle returned from NVS_open() - * - * @param offset The byte offset into the NVS region to start - * erasing from (must be erase sector aligned) - * - * @param size The number of bytes to erase (must be integer - * multiple of sector size) - * - * @retval #NVS_STATUS_SUCCESS Success. - * @retval #NVS_STATUS_INV_ALIGNMENT If \p offset is not aligned on - * a sector boundary - * @retval #NVS_STATUS_INV_OFFSET If \p offset exceeds region size - * @retval #NVS_STATUS_INV_SIZE If \p size or \p offset + \p size - * exceeds region size, or if \p size - * is not an integer multiple of - * the flash sector size. - * @retval #NVS_STATUS_ERROR If an internal error occurred - * erasing the flash. - */ -extern int_fast16_t NVS_erase(NVS_Handle handle, size_t offset, size_t size); - -/*! - * @brief Function to get the NVS attributes - * - * This function will populate a #NVS_Attrs structure with attributes - * specific to the memory region associated with the #NVS_Handle. - * - * @param handle A handle returned from NVS_open() - * - * @param attrs Location to store attributes. - */ -extern void NVS_getAttrs(NVS_Handle handle, NVS_Attrs *attrs); - -/*! - * @brief Function to initialize the NVS module - * - * @pre The NVS_config structure must exist and be persistent before this - * function can be called. This function must also be called before - * any other NVS APIs. - */ -extern void NVS_init(void); - -/*! - * @brief Function to lock the NVS driver - * - * This function is provided in the event that the user needs to - * perform some flash related operation not provided by the NVS - * driver API set or if the user simply needs to block flash operations - * for a period of time. - * - * For example, the interrupt latency introduced - * by an uncoordinated flash write operation could interfere with some - * critical operation being performed by the application. - * - * NVS_lock() prevents any other thread from initiating - * read, write, or erase operations while the user is performing an - * operation which is incompatible with those functions. - * - * When the application no longer needs to block flash operations by - * other threads, NVS_unlock() must be called to allow NVS write or erase - * APIs to complete. - * - * @param handle A handle returned from NVS_open() - * - * @param timeout Timeout (in milliseconds) to wait, - * or #NVS_LOCK_WAIT_FOREVER, #NVS_LOCK_NO_WAIT - * - * @retval #NVS_STATUS_SUCCESS Success. - * @retval #NVS_STATUS_TIMEOUT If \p timeout has expired. - */ -extern int_fast16_t NVS_lock(NVS_Handle handle, uint32_t timeout); - -/*! - * @brief Open an NVS region for reading and writing. - * - * @pre NVS_init() was called. - * - * @param index Index in the #NVS_Config table of the region - * to manage. - * - * @param params Pointer to a parameter region. If NULL, default - * parameter values will be used. - * - * @return A non-zero handle on success, else NULL. - */ -extern NVS_Handle NVS_open(uint_least8_t index, NVS_Params *params); - -/*! - * @brief Function to initialize the NVS_Params struct to its defaults - * - * @param params A pointer to NVS_Params structure for - * initialization. - */ -extern void NVS_Params_init(NVS_Params *params); - -/*! - * @brief Read data from the NVS region associated with the #NVS_Handle. - * - * @param handle A handle returned from NVS_open() - * - * @param offset The byte offset into the NVS region to start - * reading from. - * - * @param buffer A buffer to copy the data to. - * - * @param bufferSize The size of the buffer (number of bytes to read). - * - * @retval #NVS_STATUS_SUCCESS Success. - * @retval #NVS_STATUS_INV_OFFSET If \p offset + \p size exceed the size - * of the region. - */ -extern int_fast16_t NVS_read(NVS_Handle handle, size_t offset, void *buffer, - size_t bufferSize); - -/*! - * @brief Function to unlock the NVS driver - * - * This function allows NVS write and erase operations to proceed after being - * temporarily inhibited by a call to NVS_lock(). - * - * @param handle A handle returned from NVS_open() - */ -extern void NVS_unlock(NVS_Handle handle); - -/*! - * @brief Write data to the NVS region associated with the #NVS_Handle. - * - * @warning Writing to internal flash on most devices can introduce - * significant interrupt latencies while the write operation is in - * in progress. The user may want to surround certain real-time - * critical code sections with NVS_lock() and NVS_unlock() calls in order - * to prevent uncoordinated flash write operations from negatively - * impacting performance. - * - * @param handle A handle returned from NVS_open() - * - * @param offset The byte offset into the NVS region to start - * writing. - * - * @param buffer A buffer containing data to write to - * the NVS region. - * - * @param bufferSize The size of the buffer (number of bytes to write). - * - * @param flags Write flags (#NVS_WRITE_ERASE, #NVS_WRITE_PRE_VERIFY, - * #NVS_WRITE_POST_VERIFY). - * - * @retval #NVS_STATUS_SUCCESS Success. - * @retval #NVS_STATUS_ERROR If the internal flash write operation - * failed, or if #NVS_WRITE_POST_VERIFY - * was requested and the destination flash - * range does not match the source - * \p buffer data. - * @retval #NVS_STATUS_INV_OFFSET If \p offset + \p size exceed the size - * of the region. - * @retval #NVS_STATUS_INV_WRITE If #NVS_WRITE_PRE_VERIFY is requested - * and the destination flash address range - * cannot be change to the values desired. - * @retval #NVS_STATUS_INV_ALIGNMENT If #NVS_WRITE_ERASE is requested - * and \p offset is not aligned on - * a sector boundary - * - * @remark This call may lock a region to ensure atomic access to the region. - */ -extern int_fast16_t NVS_write(NVS_Handle handle, size_t offset, void *buffer, - size_t bufferSize, uint_fast16_t flags); - -#if defined (__cplusplus) -} -#endif /* defined (__cplusplus) */ - -/*@}*/ -#endif /* ti_drivers_NVS__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/PWM.c b/ext/hal/ti/simplelink/source/ti/drivers/PWM.c deleted file mode 100644 index 373a3303afd..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/PWM.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== PWM.c ======== - */ - -#include -#include -#include - -#include -#include - -extern const PWM_Config PWM_config[]; -extern const uint_least8_t PWM_count; - -/* Default PWM parameters structure */ -const PWM_Params PWM_defaultParams = { - .periodUnits = PWM_PERIOD_HZ, /* Period is defined in Hz */ - .periodValue = 1e6, /* 1MHz */ - .dutyUnits = PWM_DUTY_FRACTION, /* Duty is fraction of period */ - .dutyValue = 0, /* 0% duty cycle */ - .idleLevel = PWM_IDLE_LOW, /* Low idle level */ - .custom = NULL /* No custom params */ -}; - -static bool isInitialized = false; - -/* - * ======== PWM_close ======== - */ -void PWM_close(PWM_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== PWM_control ======== - */ -int_fast16_t PWM_control(PWM_Handle handle, uint_fast16_t cmd, void *arg) -{ - return handle->fxnTablePtr->controlFxn(handle, cmd, arg); -} - -/* - * ======== PWM_init ======== - */ -void PWM_init(void) -{ - uint_least8_t i; - uint_fast32_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - for (i = 0; i < PWM_count; i++) { - PWM_config[i].fxnTablePtr->initFxn((PWM_Handle) &(PWM_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== PWM_open ======== - */ -PWM_Handle PWM_open(uint_least8_t index, PWM_Params *params) -{ - PWM_Handle handle = NULL; - - if (isInitialized && (index < PWM_count)) { - /* If params are NULL use defaults */ - if (params == NULL) { - params = (PWM_Params *) &PWM_defaultParams; - } - - /* Get handle for this driver instance */ - handle = (PWM_Handle) &(PWM_config[index]); - - handle = handle->fxnTablePtr->openFxn(handle, params); - } - - return (handle); -} - -/* - * ======== PWM_Params_init ======== - */ -void PWM_Params_init(PWM_Params *params) -{ - *params = PWM_defaultParams; -} - -/* - * ======== PWM_setDuty ======== - */ -int_fast16_t PWM_setDuty(PWM_Handle handle, uint32_t duty) -{ - return(handle->fxnTablePtr->setDutyFxn(handle, duty)); -} - -/* - * ======== PWM_setDuty ======== - */ -int_fast16_t PWM_setPeriod(PWM_Handle handle, uint32_t period) -{ - return(handle->fxnTablePtr->setPeriodFxn(handle, period)); -} -/* - * ======== PWM_setDutyandPeriod ======== - */ -int_fast16_t PWM_setDutyAndPeriod(PWM_Handle handle, uint32_t duty, uint32_t period) -{ - return(handle->fxnTablePtr->setDutyAndPeriodFxn(handle, duty, period)); -} - -/* - * ======== PWM_start ======== - */ -void PWM_start(PWM_Handle handle) -{ - handle->fxnTablePtr->startFxn(handle); -} - -/* - * ======== PWM_stop ======== - */ -void PWM_stop(PWM_Handle handle) -{ - handle->fxnTablePtr->stopFxn(handle); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/PWM.h b/ext/hal/ti/simplelink/source/ti/drivers/PWM.h deleted file mode 100644 index 3f4e545954d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/PWM.h +++ /dev/null @@ -1,660 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!**************************************************************************** - * @file PWM.h - * @brief PWM driver interface - * - * To use the PWM driver, ensure that the correct driver library for your - * device is linked in and include this header file as follows: - * @code - * #include - * @endcode - * - * This module serves as the main interface for applications. Its purpose - * is to redirect the PWM APIs to specific driver implementations - * which are specified using a pointer to a #PWM_FxnTable. - * - * # Overview # - * The PWM driver in TI-RTOS facilitates the generation of Pulse Width - * Modulated signals via simple and portable APIs. PWM instances must be - * opened by calling PWM_open() while passing in a PWM index and a parameters - * data structure. - * - * The driver APIs serve as an interface to a typical TI-RTOS application. - * The specific peripheral implementations are responsible for creating all OS - * specific primitives to allow for thread-safe operation. - * - * When a PWM instance is opened, the period, duty cycle and idle level are - * configured and the PWM is stopped (waveforms not generated until PWM_start() - * is called). The maximum period and duty supported is device dependent; - * refer to the implementation specific documentation for values. - * - * PWM outputs are active-high, meaning the duty will control the duration of - * high output on the pin (at 0% duty, the output is always low, at 100% duty, - * the output is always high). - * - * # Usage # - * - * @code - * PWM_Handle pwm; - * PWM_Params pwmParams; - * uint32_t dutyValue; - * - * // Initialize the PWM driver. - * PWM_init(); - * - * // Initialize the PWM parameters - * PWM_Params_init(&pwmParams); - * pwmParams.idleLevel = PWM_IDLE_LOW; // Output low when PWM is not running - * pwmParams.periodUnits = PWM_PERIOD_HZ; // Period is in Hz - * pwmParams.periodValue = 1e6; // 1MHz - * pwmParams.dutyUnits = PWM_DUTY_FRACTION; // Duty is in fractional percentage - * pwmParams.dutyValue = 0; // 0% initial duty cycle - * - * // Open the PWM instance - * pwm = PWM_open(Board_PWM0, &pwmParams); - * - * if (pwm == NULL) { - * // PWM_open() failed - * while (1); - * } - * - * PWM_start(pwm); // start PWM with 0% duty cycle - * - * dutyValue = (uint32_t) (((uint64_t) PWM_DUTY_FRACTION_MAX * 37) / 100); - * PWM_setDuty(pwm, dutyValue); // set duty cycle to 37% - * @endcode - * - * Details for the example code above are described in the following - * subsections. - * - * ### PWM Driver Configuration # - * - * In order to use the PWM APIs, the application is required - * to provide device-specific PWM configuration in the Board.c file. - * The PWM driver interface defines a configuration data structure: - * - * @code - * typedef struct PWM_Config_ { - * PWM_FxnTable const *fxnTablePtr; - * void *object; - * void const *hwAttrs; - * } PWM_Config; - * @endcode - * - * The application must declare an array of PWM_Config elements, named - * PWM_config[]. Each element of PWM_config[] is populated with - * pointers to a device specific PWM driver implementation's function - * table, driver object, and hardware attributes. The hardware attributes - * define properties such as which pin will be driven, and which timer peripheral - * will be used. Each element in PWM_config[] corresponds to - * a PWM instance, and none of the elements should have NULL pointers. - * - * Additionally, the PWM driver interface defines a global integer variable - * 'PWM_count' which is initialized to the number of PWM instances the - * application has defined in the PWM_Config array. - * - * You will need to check the device-specific PWM driver implementation's - * header file for example configuration. Please also refer to the - * Board.c file of any of your examples to see the PWM configuration. - * - * ### Initializing the PWM Driver # - * - * PWM_init() must be called before any other PWM APIs. This function - * calls the device implementation's PWM initialization function, for each - * element of PWM_config[]. - * - * ### Opening the PWM Driver # - * - * Opening a PWM requires four steps: - * 1. Create and initialize a PWM_Params structure. - * 2. Fill in the desired parameters. - * 3. Call PWM_open(), passing the index of the PWM in the PWM_config - * structure, and the address of the PWM_Params structure. The - * PWM instance is specified by the index in the PWM_config structure. - * 4. Check that the PWM handle returned by PWM_open() is non-NULL, - * and save it. The handle will be used to read and write to the - * PWM you just opened. - * - * Only one PWM index can be used at a time; calling PWM_open() a second - * time with the same index previously passed to PWM_open() will result in - * an error. You can, though, re-use the index if the instance is closed - * via PWM_close(). - * In the example code, Board_PWM0 is passed to PWM_open(). This macro - * is defined in the example's Board.h file. - * - * ### Modes of Operation # - * - * A PWM instance can be configured to interpret the period as one of three - * units: - * - #PWM_PERIOD_US: The period is in microseconds. - * - #PWM_PERIOD_HZ: The period is in (reciprocal) Hertz. - * - #PWM_PERIOD_COUNTS: The period is in timer counts. - * - * A PWM instance can be configured to interpret the duty as one of three - * units: - * - #PWM_DUTY_US: The duty is in microseconds. - * - #PWM_DUTY_FRACTION: The duty is in a fractional part of the period - * where 0 is 0% and #PWM_DUTY_FRACTION_MAX is 100%. - * - #PWM_DUTY_COUNTS: The period is in timer counts and must be less than - * the period. - * - * The idle level parameter is used to set the output to high/low when the - * PWM is not running (stopped or not started). The idle level can be - * set to: - * - #PWM_IDLE_LOW - * - #PWM_IDLE_HIGH - * - * The default PWM configuration is to set a duty of 0% with a 1MHz frequency. - * The default period units are in PWM_PERIOD_HZ and the default duty units - * are in PWM_DUTY_FRACTION. Finally, the default output idle level is - * PWM_IDLE_LOW. It is the application's responsibility to set the duty for - * each PWM output used. - * - * ### Controlling the PWM Duty Cycle # - * - * Once the PWM instance has been opened and started, the primary API used - * by the application will be #PWM_setDuty() to control the duty cycle of a - * PWM pin: - * - * Below demonstrates setting the duty cycle to 45%. - * - * @code - * uint32_t dutyCycle; - * - * dutyCycle = (uint32_t) (((uint64_t) PWM_DUTY_FRACTION_MAX * 45) / 100); - * PWM_setDuty(pwm, dutyCycle); - * @endcode - * - * ### Setting Duty and Period on a Running Instance ### - * - * If an application needs to modify the duty and period of a running timer, - * an API is available to set both with as little interim time as possible. - * This minimises the possibility that a timeout will occur between one set - * call and the other. For low periods or for instances close to timeout, this - * API will pause the instance output briefly and must only be called when the - * PWM is already running. - * - * Below demonstrates setting the duty cycle to 75% of the new period (100us). - * - * @code - * uint32_t dutyCycle; - * uint32_t periodUs = 100; - * - * dutyCycle = (uint32_t) (((uint64_t) PWM_DUTY_FRACTION_MAX * 75) / 100); - * PWM_setDutyAndPeriod(pwm, dutyCycle, periodUs); - * @endcode - * - * # Implementation # - * - * The PWM driver interface module is joined (at link time) to an - * array of PWM_Config data structures named *PWM_config*. - * PWM_config is implemented in the application with each entry being a - * PWM instance. Each entry in *PWM_config* contains a: - * - (PWM_FxnTable *) to a set of functions that implement a PWM peripheral - * - (void *) data object that is associated with the PWM_FxnTable - * - (void *) hardware attributes that are associated with the PWM_FxnTable - * - * The PWM APIs are redirected to the device specific implementations - * using the PWM_FxnTable pointer of the PWM_config entry. - * In order to use device specific functions of the PWM driver directly, - * link in the correct driver library for your device and include the - * device specific PWM driver header file (which in turn includes PWM.h). - * For example, for the MSP432 family of devices, you would include the - * following header file: - * @code - * #include - * @endcode - * - ***************************************************************************** - */ - -#ifndef ti_drivers_PWM__include -#define ti_drivers_PWM__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/*! - * @brief Maximum duty (100%) when configuring duty cycle as a fraction of - * period. - */ -#define PWM_DUTY_FRACTION_MAX ((uint32_t) ~0) - -/*! - * Common PWM_control command code reservation offset. - * PWM driver implementations should offset command codes with PWM_CMD_RESERVED - * growing positively. - * - * Example implementation specific command codes: - * @code - * #define PWMXYZ_COMMAND0 (PWM_CMD_RESERVED + 0) - * #define PWMXYZ_COMMAND1 (PWM_CMD_RESERVED + 1) - * @endcode - */ -#define PWM_CMD_RESERVED (32) - -/*! - * Common PWM_control status code reservation offset. - * PWM driver implementations should offset status codes with - * PWM_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define PWMXYZ_STATUS_ERROR0 (PWM_STATUS_RESERVED - 0) - * #define PWMXYZ_STATUS_ERROR1 (PWM_STATUS_RESERVED - 1) - * #define PWMXYZ_STATUS_ERROR2 (PWM_STATUS_RESERVED - 2) - * @endcode - */ -#define PWM_STATUS_RESERVED (-32) - -/*! - * @brief Success status code returned by: - * PWM_control(), PWM_setDuty(), PWM_setPeriod(). - * - * Functions return PWM_STATUS_SUCCESS if the call was executed - * successfully. - */ -#define PWM_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by PWM_control(). - * - * PWM_control() returns PWM_STATUS_ERROR if the control code was not executed - * successfully. - */ -#define PWM_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by PWM_control() for undefined - * command codes. - * - * PWM_control() returns PWM_STATUS_UNDEFINEDCMD if the control code is not - * recognized by the driver implementation. - */ -#define PWM_STATUS_UNDEFINEDCMD (-2) - -/*! - * @brief An error status code returned by PWM_setPeriod(). - * - * PWM_setPeriod() returns PWM_STATUS_INVALID_PERIOD if the period argument is - * invalid for the current configuration. - */ -#define PWM_STATUS_INVALID_PERIOD (-3) - -/*! - * @brief An error status code returned by PWM_setDuty(). - * - * PWM_setDuty() returns PWM_STATUS_INVALID_DUTY if the duty cycle argument is - * invalid for the current configuration. - */ -#define PWM_STATUS_INVALID_DUTY (-4) - -/*! - * @brief PWM period unit definitions. Refer to device specific - * implementation if using PWM_PERIOD_COUNTS (raw PWM/Timer counts). - */ -typedef enum PWM_Period_Units_ { - PWM_PERIOD_US, /*!< Period in microseconds */ - PWM_PERIOD_HZ, /*!< Period in (reciprocal) Hertz - (for example 2MHz = 0.5us period) */ - PWM_PERIOD_COUNTS /*!< Period in timer counts */ -} PWM_Period_Units; - -/*! - * @brief PWM duty cycle unit definitions. Refer to device specific - * implementation if using PWM_DUTY_COUNTS (raw PWM/Timer counts). - */ -typedef enum PWM_Duty_Units_ { - PWM_DUTY_US, /*!< Duty cycle in microseconds */ - PWM_DUTY_FRACTION, /*!< Duty as a fractional part of #PWM_DUTY_FRACTION_MAX. - * A duty cycle value of 0 will yield a 0% duty cycle - * while a duty cycle value of #PWM_DUTY_FRACTION_MAX - * will yield a duty cycle value of 100%. */ - PWM_DUTY_COUNTS /*!< Duty in timer counts */ -} PWM_Duty_Units; - -/*! - * @brief Idle output level when PWM is not running (stopped / not started). - */ -typedef enum PWM_IdleLevel_ { - PWM_IDLE_LOW = 0, - PWM_IDLE_HIGH = 1, -} PWM_IdleLevel; - -/*! - * @brief PWM Parameters - * - * PWM Parameters are used to with the PWM_open() call. Default values for - * these parameters are set using PWM_Params_init(). - * - * @sa PWM_Params_init() - */ -typedef struct PWM_Params_ { - PWM_Period_Units periodUnits; /*!< Units in which the period is specified */ - uint32_t periodValue; /*!< PWM initial period */ - PWM_Duty_Units dutyUnits; /*!< Units in which the duty is specified */ - uint32_t dutyValue; /*!< PWM initial duty */ - PWM_IdleLevel idleLevel; /*!< Pin output when PWM is stopped. */ - void *custom; /*!< Custom argument used by driver - implementation */ -} PWM_Params; - -/*! - * @brief A handle that is returned from a PWM_open() call. - */ -typedef struct PWM_Config_ *PWM_Handle; - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_close(). - */ -typedef void (*PWM_CloseFxn) (PWM_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_control(). - */ -typedef int_fast16_t (*PWM_ControlFxn) (PWM_Handle handle, uint_fast16_t cmd, - void *arg); -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_init(). - */ -typedef void (*PWM_InitFxn) (PWM_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_open(). - */ -typedef PWM_Handle (*PWM_OpenFxn) (PWM_Handle handle, PWM_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_setDuty(). - */ -typedef int_fast16_t (*PWM_SetDutyFxn) (PWM_Handle handle, - uint32_t duty); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_setPeriod(). - */ -typedef int_fast16_t (*PWM_SetPeriodFxn) (PWM_Handle handle, - uint32_t period); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_setDutyAndPeriod(). - */ -typedef int_fast16_t (*PWM_SetDutyAndPeriodFxn) (PWM_Handle handle, - uint32_t duty, uint32_t period); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_start(). - */ -typedef void (*PWM_StartFxn) (PWM_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * PWM_stop(). - */ -typedef void (*PWM_StopFxn) (PWM_Handle handle); - -/*! - * @brief The definition of a PWM function table that contains the - * required set of functions to control a specific PWM driver - * implementation. - */ -typedef struct PWM_FxnTable_ { - /*! Function to close the specified instance */ - PWM_CloseFxn closeFxn; - /*! Function to driver implementation specific control function */ - PWM_ControlFxn controlFxn; - /*! Function to initialize the given data object */ - PWM_InitFxn initFxn; - /*! Function to open the specified instance */ - PWM_OpenFxn openFxn; - /*! Function to set the duty cycle for a specific instance */ - PWM_SetDutyFxn setDutyFxn; - /*! Function to set the period for a specific instance */ - PWM_SetPeriodFxn setPeriodFxn; - /*! Function to set the duty and the period for a specific instance */ - PWM_SetDutyAndPeriodFxn setDutyAndPeriodFxn; - /*! Function to start the PWM output for a specific instance */ - PWM_StartFxn startFxn; - /*! Function to stop the PWM output for a specific instance */ - PWM_StopFxn stopFxn; -} PWM_FxnTable; - -/*! - * @brief PWM Global configuration. - * - * The PWM_Config structure contains a set of pointers used to characterize - * the PWM driver implementation. - * - */ -typedef struct PWM_Config_ { - /*! Pointer to a table of driver-specific implementations of PWM APIs */ - PWM_FxnTable const *fxnTablePtr; - /*! Pointer to a driver specific data object */ - void *object; - /*! Pointer to a driver specific hardware attributes structure */ - void const *hwAttrs; -} PWM_Config; - -/*! - * @brief Function to close a PWM instance specified by the PWM handle. - * - * @pre PWM_open() must have been called first. - * @pre PWM_stop() must have been called first if PWM was started. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @sa PWM_open() - * @sa PWM_start() - * @sa PWM_stop() - */ -extern void PWM_close(PWM_Handle handle); - -/*! - * @brief Function performs implementation specific features on a given - * PWM_Handle. - * - * @pre PWM_open() must have been called first. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @param cmd A command value defined by the driver specific - * implementation. - * - * @param arg A pointer to an optional R/W (read/write) argument that - * is accompanied with cmd. - * - * @return A PWM_Status describing an error or success state. Negative values - * indicate an error occurred. - * - * @sa PWM_open() - */ -extern int_fast16_t PWM_control(PWM_Handle handle, uint_fast16_t cmd, - void *arg); - -/*! - * @brief This function initializes the PWM module. - * - * @pre The PWM_config structure must exist and be persistent before this - * function can be called. This function must be called before any - * other PWM driver APIs. This function does not modify any peripheral - * registers & should only be called once. - */ -extern void PWM_init(void); - -/*! - * @brief This function opens a given PWM instance and sets the period, - * duty and idle level to those specified in the params argument. - * - * @param index Logical instance number for the PWM indexed into - * the PWM_config table. - * - * @param params Pointer to an parameter structure. If NULL default - * values are used. - * - * @return A PWM_Handle if successful or NULL on an error or if it has been - * opened already. If NULL is returned further PWM API calls will - * result in undefined behavior. - * - * @sa PWM_close() - */ -extern PWM_Handle PWM_open(uint_least8_t index, PWM_Params *params); - -/*! - * @brief Function to initialize the PWM_Params structure to default values. - * - * @param params A pointer to PWM_Params structure for initialization. - * - * Defaults values are: - * Period units: PWM_PERIOD_HZ - * Period: 1e6 (1MHz) - * Duty cycle units: PWM_DUTY_FRACTION - * Duty cycle: 0% - * Idle level: PWM_IDLE_LOW - */ -extern void PWM_Params_init(PWM_Params *params); - -/*! - * @brief Function to set the duty cycle of the specified PWM handle. PWM - * instances run in active high output mode; 0% is always low output, - * 100% is always high output. This API can be called while the PWM - * is running & duty must always be lower than or equal to the period. - * If an error occurs while calling the function the PWM duty cycle - * will remain unchanged. - * - * @pre PWM_open() must have been called first. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @param duty Duty cycle in the units specified by the params used - * in PWM_open(). - * - * @return A PWM status describing an error or success. Negative values - * indicate an error. - * - * @sa PWM_open() - */ -extern int_fast16_t PWM_setDuty(PWM_Handle handle, uint32_t duty); - -/*! - * @brief Function to set the period of the specified PWM handle. This API - * can be called while the PWM is running & the period must always be - * larger than the duty cycle. - * If an error occurs while calling the function the PWM period - * will remain unchanged. - * - * @pre PWM_open() must have been called first. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @param period Period in the units specified by the params used - * in PWM_open(). - * - * @return A PWM status describing an error or success state. Negative values - * indicate an error. - * - * @sa PWM_open() - */ -extern int_fast16_t PWM_setPeriod(PWM_Handle handle, uint32_t period); - -/*! - * @brief Function to set both the period and the duty cycle of the specified PWM handle. - * This API must be called while the PWM is running & the period must always be - * larger than the duty cycle. - * If an error occurs while calling the function the period and duty - * will remain unchanged. - * - * @note This API should only be called while the PWM is running. - * - * @note If the period is lower than a certain platform-specific amount, the output of the - * PWM timer may be paused to set these values. Some implementations may also pause - * the PWM if the remaining time before the next timeout is less than this value. This - * is to guard against an edge case where a timeout happens in between setting period - * and duty. - * - * @pre PWM_open() must have been called first. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @param duty Duty cycle in the units specified by the params used - * in PWM_open(). - * - * @param period Period in the units specified by the params used - * in PWM_open(). - * - * @return A PWM status describing an error or success state. Negative values - * indicate an error. - * - * @sa PWM_open() - */ -extern int_fast16_t PWM_setDutyAndPeriod(PWM_Handle handle, uint32_t duty, uint32_t period); - -/*! - * @brief Function to start the specified PWM handle with current settings. - * - * @pre PWM_open() has to have been called first. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @sa PWM_open() - * @sa PWM_stop() - */ -extern void PWM_start(PWM_Handle handle); - -/*! - * @brief Function to stop the specified PWM handle. Output will set to the - * idle level specified by params in PWM_open(). - * - * @pre PWM_open() has to have been called first. - * - * @param handle A PWM handle returned from PWM_open(). - * - * @sa PWM_open() - * @sa PWM_start() - */ -extern void PWM_stop(PWM_Handle handle); - -#ifdef __cplusplus -} -#endif -#endif /* ti_drivers_PWM__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/Power.h b/ext/hal/ti/simplelink/source/ti/drivers/Power.h deleted file mode 100644 index 04308ebab0d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/Power.h +++ /dev/null @@ -1,607 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file Power.h - * - * @brief Power Manager interface - * - * The Power header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * # Operation # - * The Power Manager facilitates the transition of the MCU from active states - * to sleep states and vice versa. It provides other drivers the - * ability to set and release dependencies on hardware resources, and keeps - * reference counts on each resource to know when to enable or disable the - * resource. It provides drivers the ability to register callback functions - * to be invoked upon specific power events. In addition, drivers and - * applications can set or release constraints to prevent the MCU from - * transitioning into specific active or sleep states. - * - * The Power Manager APIs and configuration parameters are described here. - * For a detailed description of terms and concepts, and usage by different - * types of software components (peripheral drivers, power policies, - * and applications) please see the - * SimpleLink SDK Power Management User's Guide. - * - * ============================================================================ - */ - -#ifndef ti_drivers_Power__include -#define ti_drivers_Power__include - -#include -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* Power latency types */ -#define Power_TOTAL (1U) /*!< total latency */ -#define Power_RESUME (2U) /*!< resume latency */ - -/* Power notify responses */ -#define Power_NOTIFYDONE (0) /*!< OK, notify completed */ -#define Power_NOTIFYERROR (-1) /*!< an error occurred during notify */ - -/* Power status */ -#define Power_SOK (0) /*!< OK, operation succeeded */ -#define Power_EFAIL (-1) /*!< general failure */ -#define Power_EINVALIDINPUT (-2) /*!< invalid data value */ -#define Power_EINVALIDPOINTER (-3) /*!< invalid pointer */ -#define Power_ECHANGE_NOT_ALLOWED (-4) /*!< change is not allowed */ -#define Power_EBUSY (-5) /*!< busy with another transition */ - -/* Power transition states */ -#define Power_ACTIVE (1U) /*!< normal active state */ -#define Power_ENTERING_SLEEP (2U) /*!< entering a sleep state */ -#define Power_EXITING_SLEEP (3U) /*!< exiting a sleep state */ -#define Power_ENTERING_SHUTDOWN (4U) /*!< entering a shutdown state */ -#define Power_CHANGING_PERF_LEVEL (5U) /*!< moving to new performance level */ - - -/*! - * @brief Power policy initialization function pointer - */ -typedef void (*Power_PolicyInitFxn)(void); - -/*! - * @brief Power policy function pointer - */ -typedef void (*Power_PolicyFxn)(void); - -/*! - * @brief Power notify function pointer - */ -typedef int_fast16_t (*Power_NotifyFxn)(uint_fast16_t eventType, - uintptr_t eventArg, uintptr_t clientArg); - -/*! - * @brief Power notify object structure. - * - * This struct specification is for internal use. Notification clients must - * pre-allocate a notify object when registering for a notification; - * Power_registerNotify() will take care initializing the internal elements - * appropriately. - */ -typedef struct Power_NotifyObj_ { - List_Elem link; /*!< for placing on the notify list */ - uint_fast16_t eventTypes; /*!< the event type */ - Power_NotifyFxn notifyFxn; /*!< notification function */ - uintptr_t clientArg; /*!< argument provided by client */ -} Power_NotifyObj; - -/*! - * @brief Disable the configured power policy from running when the CPU is - * idle - * - * Calling this function clears the flag that controls whether the configured - * power policy function is invoked on each pass through the Idle loop. - * This function call will override both a 'true' setting of the - * "enablePolicy" setting in the Power Manager configuration object, as well - * as a previous runtime call to the Power_enablePolicy() function. - * - * @return The old value of "enablePolicy". - * - * @sa Power_enablePolicy - */ -bool Power_disablePolicy(void); - -/*! - * @brief Enable the configured power policy to run when the CPU is idle - * - * Calling this function sets a flag that will cause the configured power - * policy function to be invoked on each pass through the Idle loop. This - * function call will override both a 'false' setting of the "enablePolicy" - * setting in the Power Manager configuration object, as well as a previous - * runtime call to the Power_disablePolicy() function. - * - * For some processor families, automatic power transitions can make initial - * application development more difficult, as well as being at odds with - * basic debugger operation. This convenience function allows an application - * to be initially configured, built, and debugged, without automatic power - * transitions during idle time. When the application is found to be working, - * this function can be called (typically in main()) to enable the policy - * to run, without having to change the application configuration. - * - * @sa Power_disablePolicy - */ -void Power_enablePolicy(void); - -/*! - * @brief Get the constraints that have been declared with Power - * - * This function returns a bitmask indicating the constraints that are - * currently declared to the Power Manager (via previous calls to - * Power_setConstraint()). For each constraint that is currently declared, - * the corresponding bit in the bitmask will be set. For example, if two - * clients have independently declared two different constraints, the returned - * bitmask will have two bits set. - * - * Constraint identifiers are device specific, and defined in the - * device-specific Power include file. For example, the constraints for - * MSP432 are defined in PowerMSP432.h. The corresponding bit in the - * bitmask returned by this function can be derived by a left-shift using - * the constraint identifier. For example, for MSP432, for the corresponding - * bit for the PowerMSP432_DISALLOW_SLEEP constraint, the bit position is - * determined by the operation: (1 << PowerMSP432_DISALLOW_SLEEP) - * - * @return A bitmask of the currently declared constraints. - * - * @sa Power_setConstraint - */ -uint_fast32_t Power_getConstraintMask(void); - -/*! - * @brief Get the current dependency count for a resource - * - * This function returns the number of dependencies that are currently - * declared upon a resource. - * - * Resource identifiers are device specific, and defined in the - * device-specific Power include file. For example, the resources for - * CC32XX are defined in PowerCC32XX.h. - * - * @param resourceId resource id - * - * @return The number of dependencies declared for the resource. - * Power_EINVALIDINPUT if the resourceId is invalid. - * - * @sa Power_setDependency - */ -int_fast16_t Power_getDependencyCount(uint_fast16_t resourceId); - -/*! - * @brief Get the current performance level - * - * This function returns the current device performance level in effect. - * - * If performance scaling is not supported for the device, this function - * will always indicate a performance level of zero. - * - * @return The current performance level. - * - * @sa Power_setPerformanceLevel - */ -uint_fast16_t Power_getPerformanceLevel(void); - -/*! - * @brief Get the hardware transition latency for a sleep state - * - * This function reports the minimal hardware transition latency for a specific - * sleep state. The reported latency is that for a direct transition, and does - * not include any additional latency that might occur due to software-based - * notifications. - * - * Sleep states are device specific, and defined in the device-specific Power - * include file. For example, the sleep states for CC32XX are defined in - * PowerCC32XX.h. - * - * This function is typically called by the power policy function. The latency - * is reported in units of microseconds. - * - * @param sleepState the sleep state - * - * @param type the latency type (Power_TOTAL or Power_RESUME) - * - * @return The latency value, in units of microseconds. - */ -uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, - uint_fast16_t type); - -/*! - * @brief Get the current transition state of the Power Manager - * - * This function returns the current transition state for the Power Manager. - * For example, when no transitions are in progress, a status of Power_ACTIVE - * is returned. Power_ENTERING_SLEEP is returned during the transition to - * sleep, before sleep has occurred. Power_EXITING_SLEEP is returned - * after wakeup, as the device is being transitioned back to Power_ACTIVE. - * And Power_CHANGING_PERF_LEVEL is returned when a change is being made - * to the performance level. - * - * @return The current Power Manager transition state. - */ -uint_fast16_t Power_getTransitionState(void); - -/*! - * @brief Power function to be added to the application idle loop - * - * This function should be added to the application idle loop. (The method to - * do this depends upon the operating system being used.) This function - * will invoke the configured power policy function when appropriate. The - * specific policy function to be invoked is configured as the 'policyFxn' - * in the application-defined Power configuration object. - * - */ -void Power_idleFunc(void); - -/*! - * @brief Power initialization function - * - * This function initializes Power Manager internal state. It must be called - * prior to any other Power API. This function is normally called as part - * of TI-RTOS board initialization, for example, from within the - * \_initGeneral() function. - * - * @return Power_SOK - */ -int_fast16_t Power_init(void); - -/*! - * @brief Register a function to be called upon a specific power event - * - * This function registers a function to be called when a Power event occurs. - * Registrations and the corresponding notifications are processed in - * first-in-first-out (FIFO) order. The function registered must behave as - * described later, below. - * - * The pNotifyObj parameter is a pointer to a pre-allocated, opaque object - * that will be used by Power to support the notification. This object could - * be dynamically allocated, or declared as a global object. This function - * will properly initialized the object's fields as appropriate; the caller - * just needs to provide a pointer to this pre-existing object. - * - * The eventTypes parameter identifies the type of power event(s) for which - * the notify function being registered is to be called. (Event identifiers are - * device specific, and defined in the device-specific Power include file. - * For example, the events for MSP432 are defined in PowerMSP432.h.) The - * eventTypes parameter for this function call is treated as a bitmask, so - * multiple event types can be registered at once, using a common callback - * function. For example, to call the specified notifyFxn when both - * the entering deepsleep and awake from deepsleep events occur, eventTypes - * should be specified as: PowerMSP432_ENTERING_DEEPSLEEP | - * PowerMSP432_AWAKE_DEEPSLEEP - * - * The notifyFxn parameter specifies a callback function to be called when the - * specified Power event occurs. The notifyFxn must implement the following - * signature: - * status = notifyFxn(eventType, eventArg, clientArg); - * - * Where: eventType identifies the event being signalled, eventArg is an - * optional event-specific argument, and clientArg is an abitrary argument - * specified by the client at registration. Note that multipe types of events - * can be specified when registering the notification callback function, - * but when the callback function is actually called by Power, only a - * single eventType will be specified for the callback (i.e., the current - * event). The status returned by the client notification function must - * be one of the following constants: Power_NOTIFYDONE if the client processed - * the notification successfully, or Power_NOTIFYERROR if an error occurred - * during notification. - * - * The clientArg parameter is an arbitrary, client-defined argument to be - * passed back to the client upon notification. This argument may allow one - * notify function to be used by multiple instances of a driver (that is, the - * clientArg can be used to identify the instance of the driver that is being - * notified). - * - * @param pNotifyObj notification object (preallocated by caller) - * - * @param eventTypes event type or types - * - * @param notifyFxn client's callback function - * - * @param clientArg client-specified argument to pass with notification - * - * @return Power_SOK on success. - * Power_EINVALIDPOINTER if either pNotifyObj or notifyFxn are NULL. - * - * @sa Power_unregisterNotify - */ -int_fast16_t Power_registerNotify(Power_NotifyObj *pNotifyObj, - uint_fast16_t eventTypes, - Power_NotifyFxn notifyFxn, - uintptr_t clientArg); - -/*! - * @brief Release a previously declared constraint - * - * This function releases a constraint that was previously declared with - * Power_setConstraint(). For example, if a device driver is starting an I/O - * transaction and wants to prohibit activation of a sleep state during the - * transaction, it uses Power_setConstraint() to declare the constraint, - * before starting the transaction. When the transaction completes, the - * driver calls this function to release the constraint, to allow the Power - * manager to once again allow transitions to sleep. - * - * Constraint identifiers are device specific, and defined in the - * device-specific Power include file. For example, the constraints for - * MSP432 are defined in PowerMSP432.h. - * - * Only one constraint can be specified with each call to this function; to - * release multiple constraints this function must be called multiple times. - * - * It is critical that clients call Power_releaseConstraint() when operational - * constraints no longer exists. Otherwise, Power may be left unnecessarily - * restricted from activating power savings. - * - * @param constraintId constraint id - * - * @return CC26XX/CC13XX only: Power_SOK. To minimize code size - * asserts are used internally to check that the constraintId is - * valid,valid, and that the constraint count is not already zero; - * the function always returns Power_SOK. - * - * @return All other devices: Power_SOK on success, - * Power_EINVALIDINPUT if the constraintId is invalid, and Power_EFAIL - * if the constraint count is already zero. - * - * @sa Power_setConstraint - */ -int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId); - -/*! - * @brief Release a previously declared dependency - * - * This function releases a dependency that had been previously declared upon - * a resource (by a call to Power_setDependency()). - * - * Resource identifiers are device specific, and defined in the - * device-specific Power include file. For example, the resources for - * CC32XX are defined in PowerCC32XX.h. - * - * @param resourceId resource id - * - * @return CC26XX/CC13XX only: Power_SOK. To minimize code size - * asserts are used internally to check that the resourceId is valid, - * and that the resource reference count is not already zero; - * the function always returns Power_SOK. - * - * @return All other devices: Power_SOK on success, - * Power_EINVALIDINPUT if the resourceId is invalid, and Power_EFAIL - * if the resource reference count is already zero. - * - * @sa Power_setDependency - */ -int_fast16_t Power_releaseDependency(uint_fast16_t resourceId); - -/*! - * @brief Declare an operational constraint - * - * Before taking certain actions, the Power Manager checks to see if the - * requested action would conflict with a client-declared constraint. If the - * action does conflict, Power will not proceed with the request. This is the - * function that allows clients to declare their constraints with Power. - * - * Constraint identifiers are device specific, and defined in the - * device-specific Power include file. For example, the constraints for - * MSP432 are defined in PowerMSP432.h. - * - * Only one constraint can be specified with each call to this function; to - * declare multiple constraints this function must be called multiple times. - * - * @param constraintId constraint id - * - * @return CC26XX/CC13XX only: Power_SOK. To minimize code size an - * assert is used internally to check that the constraintId is valid; - * the function always returns Power_SOK. - * - * @return All other devices: Power_SOK on success, - * Power_EINVALIDINPUT if the constraintId is invalid. - * - * @sa Power_releaseConstraint - */ -int_fast16_t Power_setConstraint(uint_fast16_t constraintId); - -/*! - * @brief Declare a dependency upon a resource - * - * This function declares a dependency upon a resource. For example, if a - * UART driver needs a specific UART peripheral, it uses this function to - * declare this to the Power Manager. If the resource had been inactive, - * then Power will activate the peripheral during this function call. - * - * What is needed to make a peripheral resource 'active' will vary by device - * family. For some devices this may be a simple enable of a clock to the - * specified peripheral. For others it may also require a power on of a - * power domain. In either case, the Power Manager will take care of these - * details, and will also implement reference counting for resources and their - * interdependencies. For example, if multiple UART peripherals reside in - * a shared serial power domain, the Power Manager will power up the serial - * domain when it is first needed, and then automatically power the domain off - * later, when all related dependencies for the relevant peripherals are - * released. - * - * Resource identifiers are device specific, and defined in the - * device-specific Power include file. For example, the resources for - * CC32XX are defined in PowerCC32XX.h. - * - * @param resourceId resource id - * - * @return CC26XX/CC13XX only: Power_SOK. To minimize code size an - * assert is used internally to check that the resourceId is valid; - * the function always returns Power_SOK. - * - * @return All other devices: Power_SOK on success, - * Power_EINVALIDINPUT if the reseourceId is invalid. - * - * @sa Power_releaseDependency - */ -int_fast16_t Power_setDependency(uint_fast16_t resourceId); - -/*! - * @brief Set the MCU performance level - * - * This function manages a transition to a new device performance level. - * Before the actual transition is initiated, notifications will be sent to - * any clients who've registered (with Power_registerNotify()) for a - * 'start change performance level' notification. The event name is device - * specific, and defined in the device-specific Power include file. For - * example, for MSP432, the event is "PowerMSP432_START_CHANGE_PERF_LEVEL", - * which is defined in PowerMSP432.h. Once notifications have been completed, - * the change to the performance level is initiated. After the level change - * is completed, there is a comparable event that can be used to signal a - * client that the change has completed. For example, on MSP432 the - * "PowerMSP432_DONE_CHANGE_PERF_LEVEL" event can be used to signal - * completion. - * - * This function will not return until the new performance level is in effect. - * If performance scaling is not supported for the device, or is prohibited - * by an active constraint, or if the specified level is invalid, then an - * error status will be returned. - * - * @param level the new performance level - * - * @return Power_SOK on success. - * Power_EINVALIDINPUT if the specified performance level is out of - * range of valid levels. - * Power_EBUSY if another transition is already in progress, or if - * a single constraint is set to prohibit any change to the - * performance level. - * Power_ECHANGE_NOT_ALLOWED if a level-specific constraint prohibits - * a change to the requested level. - * Power_EFAIL if performance scaling is not supported, if an - * error occurred during initialization, or if an error occurred - * during client notifications. - * - * @sa Power_getPerformanceLevel - */ -int_fast16_t Power_setPerformanceLevel(uint_fast16_t level); - -/*! - * @brief Set a new Power policy - * - * This function allows a new Power policy function to be selected at runtime. - * - * @param policy the new Power policy function - */ -void Power_setPolicy(Power_PolicyFxn policy); - -/*! - * @brief Put the device into a shutdown state - * - * This function will transition the device into a shutdown state. - * Before the actual transition is initiated, notifications will be sent to - * any clients who've registered (with Power_registerNotify()) for an - * 'entering shutdown' event. The event name is device specific, and defined - * in the device-specific Power include file. For example, for CC32XX, the - * event is "PowerCC32XX_ENTERING_SHUTDOWN", which is defined in - * PowerCC32XX.h. Once notifications have been completed, the device shutdown - * will commence. - * - * If the device is successfully transitioned to shutdown, this function - * call will never return. Upon wakeup, the device and application will - * be rebooted (through a device reset). If the transition is not - * successful, one of the error codes listed below will be returned. - * - * On some devices a timed wakeup from shutdown can be specified, using - * the shutdownTime parameter. This enables an autonomous application reboot - * at a future time. For example, an application can go to shutdown, and then - * automatically reboot at a future time to do some work. And once that work - * is done, the application can shutdown again, for another timed interval. - * The time interval is specified via the shutdownTime parameter. (On devices - * that do not support this feature, any value specified for shutdownTime will - * be ignored.) If the specified shutdownTime is less than the total - * shutdown latency for the device, then shutdownTime will be ignored. The - * shutdown latency for the device can be found in the device-specific Power - * include file. For example, for the CC32XX, this latency is defined in - * PowerCC32XX.h, as "PowerCC32XX_TOTALTIMESHUTDOWN".) - * - * @param shutdownState the device-specific shutdown state - * - * @param shutdownTime the amount of time (in milliseconds) to keep the - * the device in the shutdown state; this parameter - * is not supported on all device families - * - * @return Power_ECHANGE_NOT_ALLOWED if a constraint is prohibiting shutdown. - * Power_EFAIL if an error occurred during client notifications. - * Power_EINVALIDINPUT if the shutdownState is invalid. - * Power_EBUSY if another transition is already in progress. - */ -int_fast16_t Power_shutdown(uint_fast16_t shutdownState, - uint_fast32_t shutdownTime); - -/*! - * @brief Transition the device into a sleep state - * - * This function is called from the power policy when it has made a decision - * to put the device in a specific sleep state. This function returns to the - * caller (the policy function) once the device has awoken from sleep. - * - * This function must be called with interrupts disabled, and should not be - * called directly by the application, or by any drivers. - * This function does not check declared constraints; the policy function - * must check constraints before calling this function to initiate sleep. - * - * @param sleepState the sleep state - * - * @return Power_SOK on success, the device has slept and is awake again. - * Power_EFAIL if an error occurred during client notifications, or - * if a general failure occurred. - * Power_EINVALIDINPUT if the sleepState is invalid. - * Power_EBUSY if another transition is already in progress. - */ -int_fast16_t Power_sleep(uint_fast16_t sleepState); - -/*! - * @brief Unregister previously registered notifications - * - * This function unregisters for event notifications that were previously - * registered with Power_registerNotify(). The caller must specify a pointer - * to the same notification object used during registration. - * - * @param pNotifyObj notify object - * - * @sa Power_registerNotify - */ -void Power_unregisterNotify(Power_NotifyObj *pNotifyObj); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_Power__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/SD.c b/ext/hal/ti/simplelink/source/ti/drivers/SD.c deleted file mode 100644 index f12abc6f414..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/SD.c +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2016-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -#include -#include - -extern const SD_Config SD_config[]; -extern const uint_least8_t SD_count; - -/* Default SD parameters structure */ -const SD_Params SD_defaultParams = { - NULL /* custom */ -}; - -static bool isInitialized = false; - -/* - * ======== SD_close ======== - */ -void SD_close(SD_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== SD_control ======== - */ -int_fast16_t SD_control(SD_Handle handle, uint_fast16_t cmd, void *arg) -{ - return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); -} - -/* - * ======== SD_getNumSectors ======== - */ -uint_fast32_t SD_getNumSectors(SD_Handle handle) -{ - return (handle->fxnTablePtr->getNumSectorsFxn(handle)); -} - -/* - * ======== SD_getSectorSize ======== - */ -uint_fast32_t SD_getSectorSize(SD_Handle handle) -{ - return (handle->fxnTablePtr->getSectorSizeFxn(handle)); -} - -/* - * ======== SD_init ======== - */ -void SD_init(void) -{ - uint_least8_t i; - uint_fast32_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - for (i = 0; i < SD_count; i++) { - SD_config[i].fxnTablePtr->initFxn((SD_Handle)&(SD_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== SD_initialize ======== - */ -int_fast16_t SD_initialize(SD_Handle handle) -{ - return (handle->fxnTablePtr->initializeFxn(handle)); -} - -/* - * ======== SD_open ======== - */ -SD_Handle SD_open(uint_least8_t index, SD_Params *params) -{ - SD_Handle handle = NULL; - - /* Verify driver index and state */ - if (isInitialized && (index < SD_count)) { - /* If params are NULL use defaults */ - if (params == NULL) { - params = (SD_Params *) &SD_defaultParams; - } - - /* Get handle for this driver instance */ - handle = (SD_Handle)&(SD_config[index]); - handle = handle->fxnTablePtr->openFxn(handle, params); - } - - return (handle); -} - -/* - * ======== SD_Params_init ======== - */ -void SD_Params_init(SD_Params *params) -{ - *params = SD_defaultParams; -} - -/* - * ======== SD_read ======== - */ -int_fast16_t SD_read(SD_Handle handle, void *buf, - int_fast32_t sector, uint_fast32_t secCount) -{ - return (handle->fxnTablePtr->readFxn(handle, buf, sector, secCount)); -} - -/* - * ======== SD_write ======== - */ -int_fast16_t SD_write(SD_Handle handle, const void *buf, - int_fast32_t sector, uint_fast32_t secCount) -{ - return (handle->fxnTablePtr->writeFxn(handle, buf, sector, secCount)); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/SD.h b/ext/hal/ti/simplelink/source/ti/drivers/SD.h deleted file mode 100644 index a6a649b8ab3..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/SD.h +++ /dev/null @@ -1,491 +0,0 @@ -/* - * Copyright (c) 2016-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** ============================================================================ - * @file SD.h - * - * @brief SD driver interface - * - * The SD header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * # Operation # - * - * The SD driver is designed to serve as an interface to perform basic - * transfers directly to the SD card. - * - * ## Opening the driver # - * - * @code - * SD_Handle handle; - * - * handle = SD_open(Board_SD0, NULL); - * if (handle == NULL) { - * //Error opening SD driver - * while (1); - * } - * @endcode - * - * # Implementation # - * - * This module serves as the main interface for TI-RTOS applications. Its - * purpose is to redirect the module's APIs to specific peripheral - * implementations which are specified using a pointer to a - * SD_FxnTable. - * - * The SD driver interface module is joined (at link time) to a - * NULL-terminated array of SD_Config data structures named *SD_config*. - * *SD_config* is implemented in the application with each entry being an - * instance of a SD peripheral. Each entry in *SD_config* contains a: - * - (SD_FxnTable *) to a set of functions that implement a SD peripheral - * - (uintptr_t) data object that is associated with the SD_FxnTable - * - (uintptr_t) hardware attributes that are associated to the SD_FxnTable - * - * # Instrumentation # - * - * The SD driver interface produces log statements if - * instrumentation is enabled. - * - * Diagnostics Mask | Log details | - * ---------------- | ----------- | - * Diags_USER1 | basic operations performed | - * Diags_USER2 | detailed operations performed | - * - * ============================================================================ - */ - -#ifndef ti_drivers_SD__include -#define ti_drivers_SD__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * @defgroup SD_CONTROL SD_control command and status codes - * @{ - */ - -/*! - * Common SD_control command code reservation offset. - * SD driver implementations should offset command codes with - * SD_CMD_RESERVED growing positively. - * - * Example implementation specific command codes: - * @code - * #define SDXYZ_CMD_COMMAND0 (SD_CMD_RESERVED + 0) - * #define SDXYZ_CMD_COMMAND1 (SD_CMD_RESERVED + 1) - * @endcode - */ -#define SD_CMD_RESERVED (32) - -/*! - * Common SD_control status code reservation offset. - * SD driver implementations should offset status codes with - * SD_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define SDXYZ_STATUS_ERROR0 (SD_STATUS_RESERVED - 0) - * #define SDXYZ_STATUS_ERROR1 (SD_STATUS_RESERVED - 1) - * #define SDXYZ_STATUS_ERROR2 (SD_STATUS_RESERVED - 2) - * @endcode - */ -#define SD_STATUS_RESERVED (-32) - -/** - * @defgroup SD_STATUS Status Codes - * SD_STATUS_* macros are general status codes returned by SD_control() - * @{ - * @ingroup SD_CONTROL - */ - -/*! - * @brief Successful status code returned by SD_control(). - * - * SD_control() returns SD_STATUS_SUCCESS if the control code was executed - * successfully. - */ -#define SD_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by SD_control(). - * - * SD_control() returns SD_STATUS_ERROR if the control code - * was not executed successfully. - */ -#define SD_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by SD_control() for - * undefined command codes. - * - * SD_control() returns SD_STATUS_UNDEFINEDCMD if the - * control code is not recognized by the driver implementation. - */ -#define SD_STATUS_UNDEFINEDCMD (-2) -/** @}*/ - -/** - * @defgroup SD_CMD Command Codes - * SD_CMD_* macros are general command codes for SD_control(). Not all SD - * driver implementations support these command codes. - * @{ - * @ingroup SD_CONTROL - */ - -/* Add SD_CMD_ here */ - -/** @}*/ - -/** @}*/ - -/*! - * @brief SD Card type inserted - */ -typedef enum SD_CardType_ { - SD_NOCARD = 0, /*!< Unrecognized Card */ - SD_MMC = 1, /*!< Multi-media Memory Card (MMC) */ - SD_SDSC = 2, /*!< Standard SDCard (SDSC) */ - SD_SDHC = 3 /*!< High Capacity SDCard (SDHC) */ -} SD_CardType; - -/*! - * @brief A handle that is returned from a SD_open() call. - */ -typedef struct SD_Config_ *SD_Handle; - -/*! - * @brief SD Parameters - * - * SD Parameters are used to with the SD_open() call. - * Default values for these parameters are set using SD_Params_init(). - * - * @sa SD_Params_init() - */ - -/* SD Parameters */ -typedef struct SD_Params_ { - void *custom; /*!< Custom argument used by driver implementation */ -} SD_Params; - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_CloseFxn(). - */ -typedef void (*SD_CloseFxn) (SD_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_controlFxn(). - */ -typedef int_fast16_t (*SD_ControlFxn) (SD_Handle handle, - uint_fast16_t cmd, void *arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_getNumSectorsFxn(). - */ -typedef uint_fast32_t (*SD_getNumSectorsFxn) (SD_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_getSectorSizeFxn(). - */ -typedef uint_fast32_t (*SD_getSectorSizeFxn) (SD_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_InitFxn(). - */ -typedef void (*SD_InitFxn) (SD_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_initializeFxn(). - */ -typedef int_fast16_t (*SD_InitializeFxn) (SD_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_OpenFxn(). - */ -typedef SD_Handle (*SD_OpenFxn) (SD_Handle handle, SD_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_readFxn(). - */ -typedef int_fast16_t (*SD_ReadFxn) (SD_Handle handle, void *buf, - int_fast32_t sector, uint_fast32_t secCount); - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_writeFxn(). - */ -typedef int_fast16_t (*SD_WriteFxn) (SD_Handle handle, const void *buf, - int_fast32_t sector, uint_fast32_t secCount); - -/*! - * @brief The definition of a SD function table that contains the - * required set of functions to control a specific SD driver - * implementation. - */ -typedef struct SD_FxnTable_ { - /*! Function to close the specified peripheral */ - SD_CloseFxn closeFxn; - /*! Function to implementation specific control function */ - SD_ControlFxn controlFxn; - /*! Function to return the total number of sectors on the SD card */ - SD_getNumSectorsFxn getNumSectorsFxn; - /*! Function to return the sector size used to address the SD card */ - SD_getSectorSizeFxn getSectorSizeFxn; - /*! Function to initialize the given data object */ - SD_InitFxn initFxn; - /*! Function to initialize the SD card */ - SD_InitializeFxn initializeFxn; - /*! Function to open the specified peripheral */ - SD_OpenFxn openFxn; - /*! Function to read from the SD card */ - SD_ReadFxn readFxn; - /*! Function to write to the SD card */ - SD_WriteFxn writeFxn; -} SD_FxnTable; - -/*! - * @brief SD Global configuration - * - * The SD_Config structure contains a set of pointers used - * to characterize the SD driver implementation. - * - * This structure needs to be defined before calling SD_init() and it must - * not be changed thereafter. - * - * @sa SD_init() - */ -typedef struct SD_Config_ { - /*! Pointer to a table of driver-specific implementations of SD APIs */ - SD_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver specific data object */ - void *object; - - /*! Pointer to a driver specific hardware attributes structure */ - void const *hwAttrs; -} SD_Config; - -/*! - * @brief Function to close a SD peripheral specified by the SD handle. - * - * @pre SD_open() had to be called first. - * - * @param handle A SD handle returned from SD_open - * - * @sa SD_open() - */ -extern void SD_close(SD_Handle handle); - -/*! - * @brief Function performs implementation specific features on a given - * SD_Handle. - * - * Commands for SD_control can originate from SD.h or from implementation - * specific SD*.h (SDHostCC32XX.h etc.. ) files. - * While commands from SD.h are API portable across driver implementations, - * not all implementations may support all these commands. - * Conversely, commands from driver implementation specific SD*.h files add - * unique driver capabilities but are not API portable across all SD driver - * implementations. - * - * Commands supported by SD.h follow a SD*_CMD naming - * convention. - * - * Commands supported by SD*.h follow a SD*_CMD naming - * convention. - * Each control command defines arg differently. The types of arg are - * documented with each command. - * - * See @ref SD_CMD "SD_control command codes" for command codes. - * - * See @ref SD_STATUS "SD_control return status codes" for status codes. - * - * @pre SD_open() has to be called first. - * - * @param handle A SD handle returned from SD_open(). - * - * @param cmd SD.h or SD*.h commands. - * - * @param arg An optional R/W (read/write) command argument - * accompanied with cmd. - * - * @return Implementation specific return codes. Negative values indicate - * unsuccessful operations. - * - * @sa SD_open() - */ -extern int_fast16_t SD_control(SD_Handle handle, uint_fast16_t cmd, void *arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_getNumSectors(). - * Note: Total Card capacity is the (NumberOfSectors * SectorSize). - * - * @pre SD Card has been initialized using SD_initialize(). - * - * @param handle A SD handle returned from SD_open(). - * - * @return The total number of sectors on the SD card, - * or 0 if an error occurred. - * - * @sa SD_initialize() - */ -extern uint_fast32_t SD_getNumSectors(SD_Handle handle); - -/*! - * @brief Function to obtain the sector size used to access the SD card. - * - * @pre SD Card has been initialized using SD_initialize(). - * - * @param handle A SD handle returned from SD_open(). - * - * @return The sector size set for use during SD card read/write operations. - * - * @sa SD_initialize() - */ -extern uint_fast32_t SD_getSectorSize(SD_Handle handle); - -/*! - * @brief This function initializes the SD driver. - * - * @pre The SD_config structure must exist and be persistent before this - * function can be called. This function must also be called before - * any other SD driver APIs. This function call does not modify any - * peripheral registers. - */ -extern void SD_init(void); - -/*! - * @brief Function to initialize the SD_Params struct to its defaults. - * - * @param params A pointer to SD_Params structure for initialization. - */ -extern void SD_Params_init(SD_Params *params); - - /*! - * @brief A function pointer to a driver specific implementation of - * SD_initialize(). - * - * @pre SD controller has been opened by calling SD_open(). - * - * @param handle A SD handle returned from SD_open(). - * - * @return SD_STATUS_SUCCESS if no errors occurred during the initialization, - * SD_STATUS_ERROR otherwise. - */ -extern int_fast16_t SD_initialize(SD_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_open(). - * - * @pre SD controller has been initialized using SD_init(). - * - * @param index Logical peripheral number for the SD indexed into - * the SD_config table. - * - * @param params Pointer to a parameter block, if NULL it will use - * default values. All the fields in this structure are - * RO (read-only). - * - * @return A SD_Handle on success or a NULL on an error or if it has been - * opened already. - * - * @sa SD_init() - * @sa SD_close() - */ -extern SD_Handle SD_open(uint_least8_t index, SD_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_read(). - * - * @pre SD controller has been opened and initialized by calling SD_open() - * followed by SD_initialize(). - * - * @param handle A SD handle returned from SD_open(). - * - * @param buf Pointer to a buffer to read data into. - * - * @param sector Starting sector on the disk to read from. - * - * @param secCount Number of sectors to be read. - * - * @return SD_STATUS_SUCCESS if no errors occurred during the write, - * SD_STATUS_ERROR otherwise. - * - * @sa SD_initialize() - */ -extern int_fast16_t SD_read(SD_Handle handle, void *buf, - int_fast32_t sector, uint_fast32_t secCount); - -/*! - * @brief A function pointer to a driver specific implementation of - * SD_write(). - * - * @pre SD controller has been opened and initialized by calling SD_open() - * followed by SD_initialize(). - * - * @param handle A SD handle returned from SD_open(). - * - * @param buf Pointer to a buffer containing data to write to disk. - * - * @param sector Starting sector on the disk to write to. - * - * @param secCount Number of sectors to be written. - * - * @return SD_STATUS_SUCCESS if no errors occurred during the write, - * SD_STATUS_ERROR otherwise. - * - * @sa SD_initialize() - */ -extern int_fast16_t SD_write(SD_Handle handle, const void *buf, - int_fast32_t sector, uint_fast32_t secCount); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_SD__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/SDFatFS.c b/ext/hal/ti/simplelink/source/ti/drivers/SDFatFS.c deleted file mode 100644 index 12fcf10cce5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/SDFatFS.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif - -#include -#include -#include -#include - -#include - -/* SDFatFS Specific Defines */ -#define DRIVE_NOT_MOUNTED (~(0U)) - -extern const SDFatFS_Config SDFatFS_config[]; -extern const uint_least8_t SDFatFS_count; - -static bool isInitialized = false; - -/* - * Array of SDFatFS_Handles to determine the association of the - * FatFs drive number with a SDFatFS_Handle. - * FF_VOLUMES is defined in . - */ -static SDFatFS_Handle sdFatFSHandles[FF_VOLUMES]; - -/* FatFS function prototypes */ -DSTATUS SDFatFS_diskInitialize(BYTE drive); -DRESULT SDFatFS_diskIOctrl(BYTE drive, BYTE ctrl, void *buffer); -DRESULT SDFatFS_diskRead(BYTE drive, BYTE *buffer, - DWORD sector, UINT secCount); -DSTATUS SDFatFS_diskStatus(BYTE drive); -DRESULT SDFatFS_diskWrite(BYTE drive, const BYTE *buffer, - DWORD sector, UINT secCount); - -/* - * ======== SDFatFS_close ======== - */ -void SDFatFS_close(SDFatFS_Handle handle) -{ - TCHAR path[3]; - DRESULT dresult; - FRESULT fresult; - SDFatFS_Object *obj = handle->object; - - /* Construct base directory path */ - path[0] = (TCHAR)'0' + obj->driveNum; - path[1] = (TCHAR)':'; - path[2] = (TCHAR)'\0'; - - /* Close the SD driver */ - SD_close(obj->sdHandle); - - /* Unmount the FatFs drive */ - fresult = f_mount(NULL, path, 0); - if (fresult != FR_OK) { - DebugP_log1("SDFatFS: Could not unmount FatFs volume @ drive" - " number %d", obj->driveNum); - } - - /* Unregister the disk_*() functions */ - dresult = disk_unregister(obj->driveNum); - if (dresult != RES_OK) { - DebugP_log1("SDFatFS: Error unregistering disk" - " functions @ drive number %d", obj->driveNum); - } - - obj->driveNum = DRIVE_NOT_MOUNTED; - DebugP_log0("SDFatFS closed"); -} - -/* - * ======== SDFatFS_diskInitialize ======== - */ -DSTATUS SDFatFS_diskInitialize(BYTE drive) -{ - int_fast8_t result; - SDFatFS_Object *obj = sdFatFSHandles[drive]->object; - - result = SD_initialize(obj->sdHandle); - - /* Convert lower level driver status code */ - if (result == SD_STATUS_SUCCESS) { - obj->diskState = ((DSTATUS) obj->diskState) & ~((DSTATUS)STA_NOINIT); - } - - return (obj->diskState); -} - -/* - * ======== SDFatFS_diskIOctrl ======== - * Function to perform specified disk operations. This function is called by the - * FatFs module and must not be called by the application! - */ -DRESULT SDFatFS_diskIOctrl(BYTE drive, BYTE ctrl, void *buffer) -{ - SDFatFS_Object *obj = sdFatFSHandles[drive]->object; - DRESULT fatfsRes = RES_ERROR; - - switch (ctrl) { - case CTRL_SYNC: - fatfsRes = RES_OK; - break; - - case (BYTE)GET_SECTOR_COUNT: - *(uint32_t*)buffer = (uint32_t)SD_getNumSectors(obj->sdHandle); - - DebugP_log1("SDFatFS: Disk IO control: sector count: %d", - *(uint32_t*)buffer); - fatfsRes = RES_OK; - break; - - case (BYTE)GET_SECTOR_SIZE: - *(WORD*)buffer = (WORD)SD_getSectorSize(obj->sdHandle); - DebugP_log1("SDFatFS: Disk IO control: sector size: %d", - *(WORD*)buffer); - fatfsRes = RES_OK; - break; - - case (BYTE)GET_BLOCK_SIZE: - *(WORD*)buffer = (WORD)SD_getSectorSize(obj->sdHandle); - DebugP_log1("SDFatFS: Disk IO control: block size: %d", - *(WORD*)buffer); - fatfsRes = RES_OK; - break; - - default: - DebugP_log0("SDFatFS: Disk IO control parameter error"); - fatfsRes = RES_PARERR; - break; - } - return (fatfsRes); -} - -/* - * ======== SDFatFS_diskRead ======== - * Function to perform a disk read from the SDCard. This function is called by - * the FatFs module and must not be called by the application! - */ -DRESULT SDFatFS_diskRead(BYTE drive, BYTE *buffer, - DWORD sector, UINT secCount) -{ - int_fast32_t result; - DRESULT fatfsRes = RES_ERROR; - SDFatFS_Object *obj = sdFatFSHandles[drive]->object; - - /* Return if disk not initialized */ - if ((obj->diskState & (DSTATUS)STA_NOINIT) != 0) { - fatfsRes = RES_PARERR; - } - else { - result = SD_read(obj->sdHandle, (uint_least8_t *)buffer, - (int_least32_t)sector, (uint_least32_t)secCount); - - /* Convert lower level driver status code */ - if (result == SD_STATUS_SUCCESS) { - fatfsRes = RES_OK; - } - } - - return (fatfsRes); -} - -/* - * ======== SDFatFS_diskStatus ======== - * Function to return the current disk status. This function is called by - * the FatFs module and must not be called by the application! - */ -DSTATUS SDFatFS_diskStatus(BYTE drive) -{ - return (((SDFatFS_Object *)sdFatFSHandles[drive]->object)->diskState); -} - - -#if (_READONLY == 0) -/* - * ======== SDFatFS_diskWrite ======== - * Function to perform a write to the SDCard. This function is called by - * the FatFs module and must not be called by the application! - */ -DRESULT SDFatFS_diskWrite(BYTE drive, const BYTE *buffer, DWORD sector, - UINT secCount) -{ - int_fast32_t result; - DRESULT fatfsRes = RES_ERROR; - SDFatFS_Object *obj = sdFatFSHandles[drive]->object; - - /* Return if disk not initialized */ - if ((obj->diskState & (DSTATUS)STA_NOINIT) != 0) { - fatfsRes = RES_PARERR; - } - else { - result = SD_write(obj->sdHandle, (const uint_least8_t *)buffer, - (int_least32_t)sector, (uint_least32_t)secCount); - - /* Convert lower level driver status code */ - if (result == SD_STATUS_SUCCESS) { - fatfsRes = RES_OK; - } - } - - return (fatfsRes); -} -#endif - -/* - * ======== SDFatFS_init ======== - */ -void SDFatFS_init(void) -{ - uint_least8_t i; - uint_fast32_t key; - SDFatFS_Object *obj; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Initialize each SDFatFS object */ - for (i = 0; i < SDFatFS_count; i++) { - obj = ((SDFatFS_Handle)&(SDFatFS_config[i]))->object; - - obj->diskState = STA_NOINIT; - obj->driveNum = DRIVE_NOT_MOUNTED; - } - - /* Initialize the SD Driver */ - SD_init(); - } - - HwiP_restore(key); -} - - -/* - * ======== SDFatFS_open ======== - * Note: The index passed into this function must correspond directly - * to the SD driver index. - */ -SDFatFS_Handle SDFatFS_open(uint_least8_t idx, uint_least8_t drive) -{ - uintptr_t key; - DRESULT dresult; - FRESULT fresult; - TCHAR path[3]; - SDFatFS_Handle handle = NULL; - SDFatFS_Object *obj; - - /* Verify driver index and state */ - if (isInitialized && (idx < SDFatFS_count)) { - /* Get handle for this driver instance */ - handle = (SDFatFS_Handle)&(SDFatFS_config[idx]); - obj = handle->object; - - /* Determine if the device was already opened */ - key = HwiP_disable(); - if (obj->driveNum != DRIVE_NOT_MOUNTED) { - HwiP_restore(key); - DebugP_log1("SDFatFS Drive %d already in use!", obj->driveNum); - handle = NULL; - } - else { - obj->driveNum = drive; - - /* Open SD Driver */ - obj->sdHandle = SD_open(idx, NULL); - - HwiP_restore(key); - - if (obj->sdHandle == NULL) { - obj->driveNum = DRIVE_NOT_MOUNTED; - /* Error occurred in lower level driver */ - handle = NULL; - } - else { - - /* Register FATFS Functions */ - dresult = disk_register(obj->driveNum, - SDFatFS_diskInitialize, - SDFatFS_diskStatus, - SDFatFS_diskRead, - SDFatFS_diskWrite, - SDFatFS_diskIOctrl); - - /* Check for drive errors */ - if (dresult != RES_OK) { - DebugP_log0("SDFatFS: Disk functions not registered"); - SDFatFS_close(handle); - handle = NULL; - } - else { - - /* Construct base directory path */ - path[0] = (TCHAR)'0' + obj->driveNum; - path[1] = (TCHAR)':'; - path[2] = (TCHAR)'\0'; - - /* - * Register the filesystem with FatFs. This operation does - * not access the SDCard yet. - */ - fresult = f_mount(&(obj->filesystem), path, 0); - if (fresult != FR_OK) { - DebugP_log1("SDFatFS: Drive %d not mounted", - obj->driveNum); - - SDFatFS_close(handle); - handle = NULL; - } - else { - - /* - * Store the new sdfatfs handle for the input drive - * number - */ - sdFatFSHandles[obj->driveNum] = handle; - - DebugP_log0("SDFatFS: opened"); - } - } - } - } - } - - return (handle); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/SDFatFS.h b/ext/hal/ti/simplelink/source/ti/drivers/SDFatFS.h deleted file mode 100644 index 43cf494ba30..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/SDFatFS.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (c) 2016-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file SDFatFS.h - * - * @brief FATFS driver interface - * - * The SDFatFS header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * # Operation # - * - * The SDFatFS driver is designed to hook into FatFs by implementing a - * set of functions that FatFs needs to call to perform basic block data - * transfers. This driver makes use of the SD driver for lower level disk IO - * operations. - * - * The only functions that should be called by the application are the - * standard driver framework functions (_open, _close, etc...). - * - * The application may use the FatFs APIs or the standard C - * runtime file I/O calls (fopen, fclose, etc...) given that SDFatFS_open has - * has been successfully called. After the SDFatFS_close API is called, - * ensure the application does NOT make any file I/O calls. - * - * ## Opening the driver # - * - * @code - * SDFatFS_Handle handle; - * - * handle = SDFatFS_open(Board_SDFatFS0, driveNum, NULL); - * if (handle == NULL) { - * //Error opening SDFatFS driver - * while (1); - * } - * @endcode - * - * # Implementation # - * - * The SDFatFS driver interface module is joined (at link time) to a NULL - * terminated array of SDFatFS_Config data structures named *SDFatFS_config*. - * *SDFatFS_config* is implemented in the application with each entry being an - * instance of the driver. Each entry in *SDFatFS_config* contains a: - * - (void *) data object that contains internal driver data structures - * - * # Instrumentation # - * - * The SDFatFS driver interface produces log statements if - * instrumentation is enabled. - * - * Diagnostics Mask | Log details | - * ---------------- | ----------- | - * Diags_USER1 | basic operations performed | - * Diags_USER2 | detailed operations performed | - * ============================================================================ - */ - -#ifndef ti_drivers_SDFatFS__include -#define ti_drivers_SDFatFS__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#include - -#include -#include - -/*! - * @brief SDFatFS Object - * The application must not access any member variables of this structure! - */ -typedef struct SDFatFS_Object_ { - uint_fast32_t driveNum; - DSTATUS diskState; - FATFS filesystem; /* FATFS data object */ - SD_Handle sdHandle; -} SDFatFS_Object; - -/*! - * @brief A handle that is returned from a SDFatFS_open() call. - */ -typedef struct SDFatFS_Config_ *SDFatFS_Handle; - - -/*! - * @brief SDFatFS Global configuration - * - * The SDFatFS_Config structure contains a single pointer used to characterize - * the SDFatFS driver implementation. - * - * This structure needs to be defined before calling SDFatFS_init() and it must - * not be changed thereafter. - * - * @sa SDFatFS_init() - */ -typedef struct SDFatFS_Config_ { - /*! Pointer to a SDFatFS object */ - void *object; -} SDFatFS_Config; - -/*! - * @brief Function to open a SDFatFS instance on the specified drive. - * - * Function to mount the FatFs filesystem and register the SDFatFS disk - * I/O functions with the FatFS module. - * - * @param idx Logical peripheral number indexed into the HWAttrs - * table. - * @param drive Drive Number - */ -extern SDFatFS_Handle SDFatFS_open(uint_least8_t idx, uint_least8_t drive); - -/*! - * @brief Function to close a SDFatFS instance specified by the SDFatFS - * handle. - * - * This function unmounts the file system mounted by SDFatFS_open and - * unregisters the SDFatFS driver from the FatFs module. - * - * @pre SDFatFS_open() had to be called first. - * - * @param handle A SDFatFS handle returned from SDFatFS_open - * - * @sa SDFatFS_open() - */ -extern void SDFatFS_close(SDFatFS_Handle handle); - -/*! - * Function to initialize a SDFatFS instance - */ -extern void SDFatFS_init(void); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_SDFatFS__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/SPI.c b/ext/hal/ti/simplelink/source/ti/drivers/SPI.c deleted file mode 100644 index 947d1b0a2dd..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/SPI.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== SPI.c ======== - */ - -#include -#include -#include -#include - -#include -#include - -extern const SPI_Config SPI_config[]; -extern const uint_least8_t SPI_count; - -/* Default SPI parameters structure */ -const SPI_Params SPI_defaultParams = { - SPI_MODE_BLOCKING, /* transferMode */ - SPI_WAIT_FOREVER, /* transferTimeout */ - NULL, /* transferCallbackFxn */ - SPI_MASTER, /* mode */ - 1000000, /* bitRate */ - 8, /* dataSize */ - SPI_POL0_PHA0, /* frameFormat */ - NULL /* custom */ -}; - -static bool isInitialized = false; - -/* - * ======== SPI_close ======== - */ -void SPI_close(SPI_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== SPI_control ======== - */ -int_fast16_t SPI_control(SPI_Handle handle, uint_fast16_t cmd, void *controlArg) -{ - return (handle->fxnTablePtr->controlFxn(handle, cmd, controlArg)); -} - -/* - * ======== SPI_init ======== - */ -void SPI_init(void) -{ - uint_least8_t i; - uint_fast8_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - for (i = 0; i < SPI_count; i++) { - SPI_config[i].fxnTablePtr->initFxn((SPI_Handle)&(SPI_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== SPI_open ======== - */ -SPI_Handle SPI_open(uint_least8_t index, SPI_Params *params) -{ - SPI_Handle handle = NULL; - - if (isInitialized && (index < SPI_count)) { - /* If params are NULL use defaults */ - if (params == NULL) { - params = (SPI_Params *) &SPI_defaultParams; - } - - /* Get handle for this driver instance */ - handle = (SPI_Handle)&(SPI_config[index]); - handle = handle->fxnTablePtr->openFxn(handle, params); - } - - return (handle); -} - -/* - * ======== SPI_Params_init ======== - */ -void SPI_Params_init(SPI_Params *params) -{ - *params = SPI_defaultParams; -} - -/* - * ======== SPI_transfer ======== - */ -bool SPI_transfer(SPI_Handle handle, SPI_Transaction *transaction) -{ - return (handle->fxnTablePtr->transferFxn(handle, transaction)); -} - -/* - * ======== SPI_transferCancel ======== - */ -void SPI_transferCancel(SPI_Handle handle) -{ - handle->fxnTablePtr->transferCancelFxn(handle); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/SPI.h b/ext/hal/ti/simplelink/source/ti/drivers/SPI.h deleted file mode 100644 index 5b5c99d41b0..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/SPI.h +++ /dev/null @@ -1,892 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file SPI.h - * - * @brief SPI driver interface - * - * The SPI driver interface provides device independent APIs, data types, - * and macros. The SPI header file should be included in an application as - * follows: - * @code - * #include - * @endcode - * - * # Overview # - * The Serial Peripheral Interface (SPI) driver is a generic, full-duplex - * driver that transmits and receives data on a SPI bus. SPI is sometimes - * called SSI (Synchronous Serial Interface). - * The SPI protocol defines the format of a data transfer over the SPI bus, - * but it leaves flow control, data formatting, and handshaking mechanisms - * to higher-level software layers. - * - * The APIs in this driver serve as an interface to a typical RTOS - * application. Its purpose is to redirect the SPI APIs to specific - * driver implementations which are specified using a pointer to a - * #SPI_FxnTable. The specific SPI implementations are responsible for - * creating all the RTOS specific primitives to allow for thread-safe - * operation. - * - * The SPI driver operates on some key definitions and assumptions: - * - The driver operates transparently from the chip select. Some SPI - * controllers feature a hardware chip select to assert SPI slave - * peripherals. See the specific peripheral implementations on chip - * select requirements. - * - * - The SPI protocol does not account for a built-in handshaking mechanism - * and neither does this SPI driver. Therefore, when operating in - * ::SPI_SLAVE mode, the application must provide such a mechanism to - * ensure that the SPI slave is ready for the SPI master. The SPI slave - * must call SPI_transfer() *before* the SPI master starts transmitting. - * Some example application mechanisms could include: - * - Timed delays on the SPI master to guarantee the SPI slave is ready - * for a SPI transaction. - * - A form of GPIO flow control from the slave to the SPI master to notify - * the master when ready. - * - * # Usage # - * - * To use the SPI driver to send data over the SPI bus, the application - * calls the following APIs: - * - SPI_init(): Initialize the SPI driver. - * - SPI_Params_init(): Initialize a #SPI_Params structure with default - * values. Then change the parameters from non-default values as - * needed. - * - SPI_open(): Open an instance of the SPI driver, passing the - * initialized parameters, or NULL, and an index (described later). - * - SPI_transfer(): Transmit/receive data. This function takes a - * #SPI_Transaction argument that specifies buffers for data to be - * transmitted/received. - * - SPI_close(): De-initialize the SPI instance. - * - * The following code example opens a SPI instance as a master SPI, - * and issues a transaction. - * - * @code - * SPI_Handle spi; - * SPI_Params spiParams; - * SPI_Transaction spiTransaction; - * uint8_t transmitBuffer[MSGSIZE]; - * uint8_t receiveBuffer[MSGSIZE]; - * bool transferOK; - * - * SPI_init(); // Initialize the SPI driver - * - * SPI_Params_init(&spiParams); // Initialize SPI parameters - * spiParams.dataSize = 8; // 8-bit data size - * - * spi = SPI_open(Board_SPI0, &spiParams); - * if (spi == NULL) { - * while (1); // SPI_open() failed - * } - * - * // Fill in transmitBuffer - * - * spiTransaction.count = MSGSIZE; - * spiTransaction.txBuf = (void *)transmitBuffer; - * spiTransaction.rxBuf = (void *)receiveBuffer; - * - * transferOK = SPI_transfer(spi, &spiTransaction); - * if (!transferOK) { - * // Error in SPI or transfer already in progress. - * while (1); - * } - * @endcode - * - * More details on usage are provided in the following subsections. - * - * ### SPI Driver Configuration # - * - * In order to use the SPI APIs, the application is required - * to provide device-specific SPI configuration in the Board.c file. - * The SPI driver interface defines a configuration data structure: - * - * @code - * typedef struct SPI_Config_ { - * SPI_FxnTable const *fxnTablePtr; - * void *object; - * void const *hwAttrs; - * } SPI_Config; - * @endcode - * - * The application must declare an array of SPI_Config elements, named - * SPI_config[]. Each element of SPI_config[] must be populated with - * pointers to a device specific SPI driver implementation's function - * table, driver object, and hardware attributes. The hardware attributes - * define properties such as the SPI peripheral's base address, and - * the MOSI and MISO pins. Each element in SPI_config[] corresponds to - * a SPI instance, and none of the elements should have NULL pointers. - * There is no correlation between the index and the - * peripheral designation (such as SPI0 or SPI1). For example, it is - * possible to use SPI_config[0] for SPI1. - * - * Because the SPI configuration is very device dependent, you will need to - * check the doxygen for the device specific SPI implementation. There you - * will find a description of the SPI hardware attributes. Please also - * refer to the Board.c file of any of your examples to see the SPI - * configuration. - * - * ### Initializing the SPI Driver # - * - * SPI_init() must be called before any other SPI APIs. This function - * iterates through the elements of the SPI_config[] array, calling - * the element's device implementation SPI initialization function. - * - * ### SPI Parameters - * - * The #SPI_Params structure is passed to the SPI_open() call. If NULL - * is passed for the parameters, SPI_open() uses default parameters. - * A #SPI_Params structure is initialized with default values by passing - * it to SPI_Params_init(). - * Some of the SPI parameters are described below. To see brief descriptions - * of all the parameters, see #SPI_Params. - * - * #### SPI Mode - * The SPI driver operates in both SPI master and SPI slave modes. - * Logically, the implementation is identical, however the difference - * between these two modes is driven by hardware. The default mode is - * ::SPI_MASTER, but can be set to slave mode by setting ::SPI_Params.mode - * to ::SPI_SLAVE in the parameters passed to SPI_open(). See - * Master/Slave Modes for further - * details. - * - * #### SPI Transfer Mode - * The SPI driver supports two transfer modes of operation: blocking and - * callback. The transfer mode is determined by the transferMode parameter - * in the SPI_Params data structure. The SPI driver - * defaults to blocking mode, if the application does not set it. - * Once a SPI driver is opened, the only way to change the operation mode - * is to close and re-open the SPI instance with the new transfer mode. - * - * In blocking mode, a task's code execution is blocked until a SPI - * transaction has completed or a timeout has occurred. This ensures - * that only one SPI transfer operates at a given time. Other tasks requesting - * SPI transfers while a transfer is currently taking place will receive - * a FALSE return value. If a timeout occurs the transfer is canceled, the - * task is unblocked & will receive a FALSE return value. The transaction - * count field will have the amount of frames which were transferred - * successfully before the timeout. In blocking mode, transfers cannot be - * performed in software or hardware ISR context. - * - * In callback mode, a SPI transaction functions asynchronously, which - * means that it does not block code execution. After a SPI transaction - * has been completed, the SPI driver calls a user-provided hook function. - * Callback mode is supported in the execution context of tasks and - * hardware interrupt routines. However, if a SPI transaction is - * requested while a transaction is taking place, SPI_transfer() returns - * FALSE. - * - * #### SPI Frame Formats and Data Size - * The SPI driver can configure the device's SPI peripheral to transfer - * data in several SPI format options: SPI (with various polarity and phase - * settings), TI, and Micro-wire. The frame format is set with - * SPI_Params.frameFormat. Some SPI implementations may not support all frame - * formats & the SPI driver will fail to opened. Refer to the device specific - * implementation documentation for details on which frame formats are - * supported. - * - * The smallest single unit of data transmitted onto the SPI bus is called - * a SPI frame and is of size SPI_Params.dataSize. A series of SPI frames - * transmitted/received on a SPI bus is known as a SPI transaction. - * - * ### Opening the SPI Driver # - * After initializing the SPI driver by calling SPI_init(), the application - * can open a SPI instance by calling SPI_open(). This function - * takes an index into the SPI_config[] array, and a SPI parameters data - * structure. The SPI instance is specified by the index of the SPI in - * SPI_config[]. Only one SPI index can be used at a time; - * calling SPI_open() a second time with the same index previously - * passed to SPI_open() will result in an error. You can, - * though, re-use the index if the instance is closed via SPI_close(). - * - * If no SPI_Params structure is passed to SPI_open(), default values are - * used. If the open call is successful, it returns a non-NULL value. - * - * Example opening a SPI driver instance in blocking mode: - * @code - * SPI_Handle spi; - * SPI_Params spiParams; - * - * SPI_Params_init(&spiParams); - * spiParams.transferMode = SPI_MODE_BLOCKING; - * spi = SPI_open(Board_SPI0, &spiParams); - * - * if (spi == NULL) { - * // Error opening SPI - * while(1); - * } - * @endcode - * - * Example opening a SPI driver instance in callback mode: - * @code - * SPI_Handle spi; - * SPI_Params spiParams; - * - * SPI_Params_init(&spiParams); - * spiParams.transferMode = SPI_MODE_CALLBACK; - * spiParams.transferCallbackFxn = UserCallbackFxn; - * - * spi = SPI_open(Board_SPI0, &spiParams); - * if (spi == NULL) { - * // Error opening SPI - * while (1); - * } - * @endcode - * - * - * ### SPI Transactions # - * - * A SPI transaction consists of a series of SPI frames - * transmitted/received on a SPI bus. A SPI transaction is performed - * using SPI_transfer(). SPI_transfer() accepts a pointer to a - * #SPI_Transaction structure that dictates the quantity of data to be - * sent and received. - * The SPI_Transaction.txBuf and SPI_Transaction.rxBuf are both pointers - * to data buffers. If txBuf is NULL, the driver sends SPI frames with all - * data set to the default value specified in the hardware attributes. If - * rxBuf is NULL, the driver discards all SPI frames received. SPI_transfer() - * of a SPI transaction is performed atomically. - * - * @warning The use of NULL as a sentinel txBuf or rxBuf value to determine - * whether the SPI transaction includes a tx or rx component implies - * that it is not possible to perform a transmit or receive transfer - * directly from/to a buffer with a base address of 0x00000000. To support - * this rare use-case, the application will have to manually copy the - * contents of location 0x00000000 to/from a temporary buffer before/after - * the tx/rx SPI transaction. - * - * When the SPI is opened, the dataSize value determines the element types - * of txBuf and rxBuf. If the dataSize is from 4 to 8 bits, the driver - * assumes the data buffers are of type uint8_t (unsigned char). If the - * dataSize is from 8 to 16 bits, the driver assumes the data buffers are - * of type uint16_t (unsigned short). If the dataSize is greater than - * 16 bits, the driver assumes the data buffers are uint32_t (unsigned long). - * Some SPI driver implementations may not support all data sizes; refer - * to device specific SPI implementation documentation for details on - * what data sizes are supported. - * - * The optional SPI_Transaction.arg variable can only be used when the - * SPI driver has been opened in callback mode. This variable is used to - * pass a user-defined value into the user-defined callback function. - * - * SPI_transfer() always performs full-duplex SPI transactions. This means - * the SPI simultaneously receives data as it transmits data. The application - * is responsible for formatting the data to be transmitted as well as - * determining whether the data received is meaningful. - * Specifics about SPI frame formatting and data sizes are provided in - * device-specific data sheets and technical reference manuals. - * - * The following code snippets perform SPI transactions. - * - * Example transferring 6-bit SPI frames. The transmit and receive - * buffers are of type uint8_t. - * @code - * SPI_Transaction spiTransaction; - * uint8_t transmitBuffer[BUFSIZE]; - * uint8_t receiveBuffer[BUFSIZE]; - * bool transferOK; - * - * SPI_Params_init(&spiParams); - * spiParams.dataSize = 6; - * spi = SPI_open(Board_SPI0, &spiParams); - * ... - * spiTransaction.count = someIntegerValue; - * spiTransaction.txBuf = transmitBuffer; - * spiTransaction.rxBuf = receiveBuffer; - * - * transferOK = SPI_transfer(spi, &spiTransaction); - * if (!transferOK) { - * // Error in SPI or transfer already in progress. - * } - * @endcode - * - * Example transferring 12-bit SPI frames. The transmit and receive - * buffers are of type uint16_t. - * @code - * SPI_Transaction spiTransaction; - * uint16_t transmitBuffer[BUFSIZE]; - * uint16_t receiveBuffer[BUFSIZE]; - * bool transferOK; - * - * SPI_Params_init(&spiParams); - * spiParams.dataSize = 12; - * spi = SPI_open(Board_SPI0, &spiParams); - * ... - * spiTransaction.count = someIntegerValue; - * spiTransaction.txBuf = transmitBuffer; - * spiTransaction.rxBuf = receiveBuffer; - * - * transferOK = SPI_transfer(spi, &spiTransaction); - * if (!transferOK) { - * // Error in SPI or transfer already in progress. - * } - * @endcode - * - * ### Canceling a transaction # - * SPI_transferCancel() is used to cancel a SPI transaction when the driver is - * used in ::SPI_MODE_CALLBACK mode. - * - * Calling this API while no transfer is in progress has no effect. If a - * transfer is in progress, it is canceled and the callback functions is - * called. - * The ::SPI_Status status field in the ::SPI_Transaction structure - * can be examined within the callback to determine if the transaction - * succeeded. - * - * Example: - * @code - * SPI_transferCancel(spi); - * @endcode - * - * - *

Master/Slave Modes

- * This SPI driver functions in both SPI master and SPI slave modes. - * Logically, the implementation is identical, however the difference between - * these two modes is driven by hardware. As a SPI master, the peripheral is - * in control of the clock signal and therefore will commence communications - * to the SPI slave immediately. As a SPI slave, the SPI driver prepares - * the peripheral to transmit and receive data in a way such that the - * peripheral is ready to transfer data when the SPI master initiates a - * transaction. - * - * ### Asserting on Chip Select - * The SPI protocol requires that the SPI master asserts a SPI slave's chip - * select pin prior to starting a SPI transaction. While this protocol is - * generally followed, various types of SPI peripherals have different - * timing requirements as to when and for how long the chip select pin must - * remain asserted for a SPI transaction. - * - * Commonly, the SPI master uses a hardware chip select to assert and - * de-assert the SPI slave for every data frame. In other cases, a SPI slave - * imposes the requirement of asserting the chip select over several SPI - * data frames. This is generally accomplished by using a regular, - * general-purpose output pin. Due to the complexity of such SPI peripheral - * implementations, this SPI driver has been designed to operate - * transparently to the SPI chip select. When the hardware chip - * select is used, the peripheral automatically selects/enables the - * peripheral. When using a software chip select, the application needs to - * handle the proper chip select and pin configuration. Chip select support - * will vary per SPI peripheral, refer to the device specific implementation - * documentation for details on chip select support. - * - * - _Hardware chip select_ No additional action by the application is - * required. - * - _Software chip select_ The application needs to handle the chip select - * assertion and de-assertion for the proper SPI peripheral. - * - * # Implementation # - * - * This module serves as the main interface for RTOS applications. Its - * purpose is to redirect the module's APIs to specific peripheral - * implementations which are specified using a pointer to a #SPI_FxnTable. - * - * The SPI driver interface module is joined (at link time) to an - * array of SPI_Config data structures named *SPI_config*. - * The SPI_config array is implemented in the application with each entry - * being an instance of a SPI peripheral. Each entry in *SPI_config* contains - * the following: - * - (SPI_FxnTable *) A pointer to a set of functions that implement a - * SPI peripheral. - * - (void *) A data object that is associated with the SPI_FxnTable. - * - (void *) The hardware attributes that are associated with the - * SPI_FxnTable. - * - ******************************************************************************* - */ - -#ifndef ti_drivers_SPI__include -#define ti_drivers_SPI__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * @defgroup SPI_CONTROL SPI_control command and status codes - * These SPI macros are reservations for SPI.h - * @{ - */ - -/*! - * Common SPI_control command code reservation offset. - * SPI driver implementations should offset command codes with SPI_CMD_RESERVED - * growing positively - * - * Example implementation specific command codes: - * @code - * #define SPIXYZ_CMD_COMMAND0 SPI_CMD_RESERVED + 0 - * #define SPIXYZ_CMD_COMMAND1 SPI_CMD_RESERVED + 1 - * @endcode - */ -#define SPI_CMD_RESERVED (32) - -/*! - * Common SPI_control status code reservation offset. - * SPI driver implementations should offset status codes with - * SPI_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define SPIXYZ_STATUS_ERROR0 SPI_STATUS_RESERVED - 0 - * #define SPIXYZ_STATUS_ERROR1 SPI_STATUS_RESERVED - 1 - * #define SPIXYZ_STATUS_ERROR2 SPI_STATUS_RESERVED - 2 - * @endcode - */ -#define SPI_STATUS_RESERVED (-32) - -/** - * @defgroup SPI_STATUS Status Codes - * SPI_STATUS_* macros are general status codes returned by SPI_control() - * @{ - * @ingroup SPI_CONTROL - */ - -/*! - * @brief Successful status code returned by SPI_control(). - * - * SPI_control() returns SPI_STATUS_SUCCESS if the control code was executed - * successfully. - */ -#define SPI_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by SPI_control(). - * - * SPI_control() returns SPI_STATUS_ERROR if the control code was not executed - * successfully. - */ -#define SPI_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by SPI_control() for undefined - * command codes. - * - * SPI_control() returns SPI_STATUS_UNDEFINEDCMD if the control code is not - * recognized by the driver implementation. - */ -#define SPI_STATUS_UNDEFINEDCMD (-2) -/** @}*/ - -/** - * @defgroup SPI_CMD Command Codes - * SPI_CMD_* macros are general command codes for SPI_control(). Not all SPI - * driver implementations support these command codes. - * @{ - * @ingroup SPI_CONTROL - */ - -/* Add SPI_CMD_ here */ - -/** @}*/ - -/** @}*/ - -/*! - * @brief Wait forever define - */ -#define SPI_WAIT_FOREVER (~(0U)) - -/*! - * @brief A handle that is returned from a SPI_open() call. - */ -typedef struct SPI_Config_ *SPI_Handle; - -/*! - * @brief Status codes that are set by the SPI driver. - */ -typedef enum SPI_Status_ { - SPI_TRANSFER_COMPLETED = 0, /*!< SPI transfer completed */ - SPI_TRANSFER_STARTED, /*!< SPI transfer started and in progress */ - SPI_TRANSFER_CANCELED, /*!< SPI transfer was canceled */ - SPI_TRANSFER_FAILED, /*!< SPI transfer failed */ - SPI_TRANSFER_CSN_DEASSERT, /*!< SPI chip select was de-asserted */ - SPI_TRANSFER_PEND_CSN_ASSERT, /*!< SPI transfer is pending until the chip select is asserted */ - SPI_TRANSFER_QUEUED /*!< SPI transfer added to transaction queue */ -} SPI_Status; - -/*! - * @brief - * A ::SPI_Transaction data structure is used with SPI_transfer(). It indicates - * how many ::SPI_FrameFormat frames are sent and received from the buffers - * pointed to txBuf and rxBuf. - * The arg variable is an user-definable argument which gets passed to the - * ::SPI_CallbackFxn when the SPI driver is in ::SPI_MODE_CALLBACK. - */ -typedef struct SPI_Transaction_ { - /* User input (write-only) fields */ - size_t count; /*!< Number of frames for this transaction */ - void *txBuf; /*!< void * to a buffer with data to be transmitted */ - void *rxBuf; /*!< void * to a buffer to receive data */ - void *arg; /*!< Argument to be passed to the callback function */ - - /* User output (read-only) fields */ - SPI_Status status; /*!< Status code set by SPI_transfer */ - - void *nextPtr; /*!< Field used internally by the driver and must - never be accessed by the application. */ -} SPI_Transaction; - -/*! - * @brief The definition of a callback function used by the SPI driver - * when used in ::SPI_MODE_CALLBACK - * - * @param SPI_Handle SPI_Handle - * @param SPI_Transaction* SPI_Transaction* - */ -typedef void (*SPI_CallbackFxn) (SPI_Handle handle, - SPI_Transaction *transaction); -/*! - * @brief - * Definitions for various SPI modes of operation. - */ -typedef enum SPI_Mode_ { - SPI_MASTER = 0, /*!< SPI in master mode */ - SPI_SLAVE = 1 /*!< SPI in slave mode */ -} SPI_Mode; - -/*! - * @brief - * Definitions for various SPI data frame formats. - */ -typedef enum SPI_FrameFormat_ { - SPI_POL0_PHA0 = 0, /*!< SPI mode Polarity 0 Phase 0 */ - SPI_POL0_PHA1 = 1, /*!< SPI mode Polarity 0 Phase 1 */ - SPI_POL1_PHA0 = 2, /*!< SPI mode Polarity 1 Phase 0 */ - SPI_POL1_PHA1 = 3, /*!< SPI mode Polarity 1 Phase 1 */ - SPI_TI = 4, /*!< TI mode (not supported on all - implementations) */ - SPI_MW = 5 /*!< Micro-wire mode (not supported on all - implementations) */ -} SPI_FrameFormat; - -/*! - * @brief - * - * SPI transfer mode determines the whether the SPI controller operates - * synchronously or asynchronously. In ::SPI_MODE_BLOCKING mode SPI_transfer() - * blocks code execution until the SPI transaction has completed. In - * ::SPI_MODE_CALLBACK SPI_transfer() does not block code execution and instead - * calls a ::SPI_CallbackFxn callback function when the transaction has - * completed. - */ -typedef enum SPI_TransferMode_ { - /*! - * SPI_transfer() blocks execution. This mode can only be used when called - * within a Task context - */ - SPI_MODE_BLOCKING, - /*! - * SPI_transfer() does not block code execution and will call a - * ::SPI_CallbackFxn. This mode can be used in a Task, software or hardware - * interrupt context. - */ - SPI_MODE_CALLBACK -} SPI_TransferMode; - -/*! - * @brief SPI Parameters - * - * SPI Parameters are used to with the SPI_open() call. Default values for - * these parameters are set using SPI_Params_init(). - * - * @sa SPI_Params_init() - */ -typedef struct SPI_Params_ { - SPI_TransferMode transferMode; /*!< Blocking or Callback mode */ - uint32_t transferTimeout; /*!< Transfer timeout in system - ticks */ - SPI_CallbackFxn transferCallbackFxn;/*!< Callback function pointer */ - SPI_Mode mode; /*!< Master or Slave mode */ - uint32_t bitRate; /*!< SPI bit rate in Hz */ - uint32_t dataSize; /*!< SPI data frame size in bits */ - SPI_FrameFormat frameFormat; /*!< SPI frame format */ - void *custom; /*!< Custom argument used by driver - implementation */ -} SPI_Params; - -/*! - * @brief A function pointer to a driver specific implementation of - * SPI_close(). - */ -typedef void (*SPI_CloseFxn) (SPI_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * SPI_control(). - */ -typedef int_fast16_t (*SPI_ControlFxn) (SPI_Handle handle, uint_fast16_t cmd, - void *arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * SPI_init(). - */ -typedef void (*SPI_InitFxn) (SPI_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * SPI_open(). - */ -typedef SPI_Handle (*SPI_OpenFxn) (SPI_Handle handle, SPI_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * SPI_transfer(). - */ -typedef bool (*SPI_TransferFxn) (SPI_Handle handle, - SPI_Transaction *transaction); - -/*! - * @brief A function pointer to a driver specific implementation of - * SPI_transferCancel(). - */ -typedef void (*SPI_TransferCancelFxn) (SPI_Handle handle); - -/*! - * @brief The definition of a SPI function table that contains the - * required set of functions to control a specific SPI driver - * implementation. - */ -typedef struct SPI_FxnTable_ { - /*! Function to close the specified peripheral */ - SPI_CloseFxn closeFxn; - - /*! Function to implementation specific control function */ - SPI_ControlFxn controlFxn; - - /*! Function to initialize the given data object */ - SPI_InitFxn initFxn; - - /*! Function to open the specified peripheral */ - SPI_OpenFxn openFxn; - - /*! Function to initiate a SPI data transfer */ - SPI_TransferFxn transferFxn; - - /*! Function to cancel SPI data transfer */ - SPI_TransferCancelFxn transferCancelFxn; -} SPI_FxnTable; - -/*! - * @brief SPI Global configuration - * - * The SPI_Config structure contains a set of pointers used to characterize - * the SPI driver implementation. - * - * This structure needs to be defined before calling SPI_init() and it must - * not be changed thereafter. - * - * @sa SPI_init() - */ -typedef struct SPI_Config_ { - /*! Pointer to a table of driver-specific implementations of SPI APIs */ - SPI_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver specific data object */ - void *object; - - /*! Pointer to a driver specific hardware attributes structure */ - void const *hwAttrs; -} SPI_Config; - -/*! - * @brief Function to close a SPI peripheral specified by the SPI handle - * - * @pre SPI_open() has to be called first. - * - * @param handle A SPI handle returned from SPI_open() - * - * @sa SPI_open() - */ -extern void SPI_close(SPI_Handle handle); - -/*! - * @brief Function performs implementation specific features on a given - * SPI_Handle. - * - * Commands for SPI_control can originate from SPI.h or from implementation - * specific SPI*.h (_SPICC26XX.h_, _SPIMSP432.h_, etc.. ) files. - * While commands from SPI.h are API portable across driver implementations, - * not all implementations may support all these commands. - * Conversely, commands from driver implementation specific SPI*.h files add - * unique driver capabilities but are not API portable across all SPI driver - * implementations. - * - * Commands supported by SPI.h follow a SPI_CMD_\ naming - * convention.
- * Commands supported by SPI*.h follow a SPI*_CMD_\ naming - * convention.
- * Each control command defines @b arg differently. The types of @b arg are - * documented with each command. - * - * See @ref SPI_CMD "SPI_control command codes" for command codes. - * - * See @ref SPI_STATUS "SPI_control return status codes" for status codes. - * - * @pre SPI_open() has to be called first. - * - * @param handle A SPI handle returned from SPI_open() - * - * @param cmd SPI.h or SPI*.h commands. - * - * @param controlArg An optional R/W (read/write) command argument - * accompanied with cmd - * - * @return Implementation specific return codes. Negative values indicate - * unsuccessful operations. - * - * @sa SPI_open() - */ -extern int_fast16_t SPI_control(SPI_Handle handle, uint_fast16_t cmd, - void *controlArg); - -/*! - * @brief This function initializes the SPI module. - * - * @pre The SPI_config structure must exist and be persistent before this - * function can be called. This function must also be called before - * any other SPI driver APIs. This function call does not modify any - * peripheral registers. - */ -extern void SPI_init(void); - -/*! - * @brief This function opens a given SPI peripheral. - * - * @pre SPI controller has been initialized using SPI_init() - * - * @param index Logical peripheral number for the SPI indexed into - * the SPI_config table - * - * @param params Pointer to an parameter block, if NULL it will use - * default values. All the fields in this structure are - * RO (read-only). - * - * @return A SPI_Handle on success or a NULL on an error or if it has been - * opened already. - * - * @sa SPI_init() - * @sa SPI_close() - */ -extern SPI_Handle SPI_open(uint_least8_t index, SPI_Params *params); - -/*! - * @brief Function to initialize the SPI_Params struct to its defaults - * - * @param params An pointer to SPI_Params structure for - * initialization - * - * Defaults values are: - * transferMode = SPI_MODE_BLOCKING - * transferTimeout = SPI_WAIT_FOREVER - * transferCallbackFxn = NULL - * mode = SPI_MASTER - * bitRate = 1000000 (Hz) - * dataSize = 8 (bits) - * frameFormat = SPI_POL0_PHA0 - */ -extern void SPI_Params_init(SPI_Params *params); - -/*! - * @brief Function to perform SPI transactions - * - * If the SPI is in ::SPI_MASTER mode, it will immediately start the - * transaction. If the SPI is in ::SPI_SLAVE mode, it prepares the driver for - * a transaction with a SPI master device. The device will then wait until - * the master begins the transfer. - * - * In ::SPI_MODE_BLOCKING, %SPI_transfer() will block task execution until the - * transaction has completed or a timeout has occurred. - * - * In ::SPI_MODE_CALLBACK, %SPI_transfer() does not block task execution, but - * calls a ::SPI_CallbackFxn once the transfer has finished. This makes - * %SPI_tranfer() safe to be used within a Task, software or hardware - * interrupt context. If queued transactions are supported SPI_Transfer may - * be called multiple times to queue multiple transactions. If the driver does - * not support this functionality additional calls will return false. Refer to - * device specific SPI driver documentation for support information. - * - * From calling %SPI_transfer() until transfer completion, the SPI_Transaction - * structure must stay persistent and must not be altered by application code. - * It is also forbidden to modify the content of the SPI_Transaction.txBuffer - * during a transaction, even though the physical transfer might not have - * started yet. Doing this can result in data corruption. This is especially - * important for slave operations where %SPI_transfer() might be called a long - * time before the actual data transfer begins. - * - * @param handle A SPI_Handle - * - * @param transaction A pointer to a SPI_Transaction. All of the fields within - * transaction except SPI_Transaction.count and - * SPI_Transaction.status are WO (write-only) unless - * otherwise noted in the driver implementations. If a - * transaction timeout has occurred, SPI_Transaction.count - * will contain the number of frames that were transferred. - * Neither is it allowed to modify the transaction object nor - * the content of SPI_Transaction.txBuffer until the transfer - * has completed. - * - * @return \p true if started successfully; else \p false - * - * @sa SPI_open - * @sa SPI_transferCancel - */ -extern bool SPI_transfer(SPI_Handle handle, SPI_Transaction *transaction); - -/*! - * @brief Function to cancel SPI transactions - * - * In ::SPI_MODE_BLOCKING, SPI_transferCancel has no effect. - * - * In ::SPI_MODE_CALLBACK, SPI_transferCancel() will stop an SPI transfer if - * if one is in progress. - * If a transaction was in progress, its callback function will be called - * in context from which this API is called from. The ::SPI_CallbackFxn - * function can determine if the transaction was successful or not by reading - * the ::SPI_Status status value in the ::SPI_Transaction structure. - * - * @param handle A SPI_Handle - * - * @sa SPI_open - * @sa SPI_transfer - */ -extern void SPI_transferCancel(SPI_Handle handle); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_SPI__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/Timer.c b/ext/hal/ti/simplelink/source/ti/drivers/Timer.c deleted file mode 100644 index 4c4340bda0f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/Timer.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2016-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -#include -#include - -extern const Timer_Config Timer_config[]; -extern const uint_least8_t Timer_count; - -/* Default Parameters */ -static const Timer_Params defaultParams = { - .timerMode = Timer_ONESHOT_BLOCKING, - .periodUnits = Timer_PERIOD_COUNTS, - .timerCallback = NULL, - .period = (uint16_t) ~0 -}; - -static bool isInitialized = false; - -/* - * ======== Timer_control ======== - */ -int_fast16_t Timer_control(Timer_Handle handle, uint_fast16_t cmd, void *arg) -{ - return handle->fxnTablePtr->controlFxn(handle, cmd, arg); -} - -/* - * ======== Timer_close ======== - */ -void Timer_close(Timer_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== Timer_getCount ======== - */ -uint32_t Timer_getCount(Timer_Handle handle) -{ - return handle->fxnTablePtr->getCountFxn(handle); -} - -/* - * ======== Timer_init ======== - */ -void Timer_init(void) -{ - uint_least8_t i; - uint_fast32_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - for (i = 0; i < Timer_count; i++) { - Timer_config[i].fxnTablePtr->initFxn((Timer_Handle) &(Timer_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== Timer_open ======== - */ -Timer_Handle Timer_open(uint_least8_t index, Timer_Params *params) -{ - Timer_Handle handle = NULL; - - /* Verify driver index and state */ - if (isInitialized && (index < Timer_count)) { - /* If parameters are NULL use defaults */ - if (params == NULL) { - params = (Timer_Params *) &defaultParams; - } - - /* Get handle for this driver instance */ - handle = (Timer_Handle) &(Timer_config[index]); - handle = handle->fxnTablePtr->openFxn(handle, params); - } - - return (handle); -} - -/* - * ======== Timer_Params_init ======== - */ -void Timer_Params_init(Timer_Params *params) -{ - *params = defaultParams; -} - -/* - * ======== Timer_start ======== - */ -int32_t Timer_start(Timer_Handle handle) -{ - return handle->fxnTablePtr->startFxn(handle); -} - -/* - * ======== Timer_stop ======== - */ -void Timer_stop(Timer_Handle handle) -{ - handle->fxnTablePtr->stopFxn(handle); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/Timer.h b/ext/hal/ti/simplelink/source/ti/drivers/Timer.h deleted file mode 100644 index ed516e0fcf0..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/Timer.h +++ /dev/null @@ -1,549 +0,0 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file Timer.h - * @brief Timer driver interface - * - * The timer header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * # Overview # - * The timer driver serves as the main interface for a typical RTOS - * application. Its purpose is to redirect the timer APIs to device specific - * implementations which are specified using a pointer to a #Timer_FxnTable. - * The device specific implementations are responsible for creating all the - * RTOS specific primitives to allow for thead-safe operation. This driver - * does not have PWM or capture functionalities. These functionalities are - * addressed in both the capture and PWM driver. - * - * The timer driver also handles the general purpose timer resource allocation. - * For each driver that requires use of a general purpose timer, it calls - * Timer_open() to occupy the specified timer, and calls Timer_close() to - * release the occupied timer resource. - * - * # Usage # - * The following example code opens a timer in continuous callback mode. The - * period is set to 1000 Hz. - * - * @code - * Timer_Handle handle; - * Timer_Params params; - * - * Timer_Params_init(¶ms); - * params.periodUnits = Timer_PERIOD_HZ; - * params.period = 1000; - * params.timerMode = Timer_CONTINUOUS_CALLBACK; - * params.timerCallback = UserCallbackFunction; - * - * handle = Timer_open(Board_TIMER0, ¶ms); - * - * if (handle == NULL) { - * // Timer_open() failed - * while (1); - * } - * - * status = Timer_start(handle); - * - * if (status == Timer_STATUS_ERROR) { - * //Timer_start() failed - * while (1); - * } - * - * sleep(10000); - * - * Timer_stop(handle); - * @endcode - * - * ### Timer Driver Configuration # - * - * In order to use the timer APIs, the application is required to provide - * device specific timer configuration in the Board.c file. The timer driver - * interface defines a configuration data structure: - * - * @code - * typedef struct Timer_Config_ { - * Timer_FxnTable const *fxnTablePtr; - * void *object; - * void const *hwAttrs; - * } Timer_Config; - * @endcode - * - * The application must declare an array of Timer_Config elements, named - * Timer_config[]. Each element of Timer_config[] are populated with - * pointers to a device specific timer driver implementation's function - * table, driver object, and hardware attributes. The hardware attributes - * define properties such as the timer peripheral's base address, interrupt - * number and interrupt priority. Each element in Timer_config[] corresponds - * to a timer instance, and none of the elements should have NULL pointers. - * There is no correlation between the index and the peripheral designation - * (such as TIMER0 or TIMER1). For example, it is possible to use - * Timer_config[0] for TIMER1. - * - * You will need to check the device specific timer driver implementation's - * header file for example configuration. - * - * ### Initializing the Timer Driver # - * - * Timer_init() must be called before any other timer APIs. This function - * calls the device implementation's timer initialization function, for each - * element of Timer_config[]. - * - * ### Modes of Operation # - * - * The timer driver supports four modes of operation which may be specified in - * the Timer_Params. The device specific implementation may configure the timer - * peripheral as an up or down counter. In any case, Timer_getCount() will - * return a value characteristic of an up counter. - * - * #Timer_ONESHOT_CALLBACK is non-blocking. After Timer_start() is called, - * the calling thread will continue execution. When the timer interrupt - * is triggered, the specified callback function will be called. The timer - * will not generate another interrupt unless Timer_start() is called again. - * Calling Timer_stop() or Timer_close() after Timer_start() but, before the - * timer interrupt, will prevent the specified callback from ever being - * invoked. - * - * #Timer_ONESHOT_BLOCKING is a blocking call. A semaphore is used to block - * the calling thread's execution until the timer generates an interrupt. If - * Timer_stop() is called, the calling thread will become unblocked - * immediately. The behavior of the timer in this mode is similar to a sleep - * function. - * - * #Timer_CONTINUOUS_CALLBACK is non-blocking. After Timer_start() is called, - * the calling thread will continue execution. When the timer interrupt is - * treiggered, the specified callback function will be called. The timer is - * automatically restarted and will continue to periodically generate - * interrupts until Timer_stop() is called. - * - * #Timer_FREE_RUNNING is non-blocking. After Timer_start() is called, - * the calling thread will continue execution. The timer will not - * generate an interrupt in this mode. The timer hardware will run until - * Timer_stop() is called. - * - * # Implementation # - * - * The timer driver interface module is joined (at link time) to an - * array of Timer_Config data structures named *Timer_config*. - * Timer_config is implemented in the application with each entry being an - * instance of a timer peripheral. Each entry in *Timer_config* contains a: - * - (Timer_FxnTable *) to a set of functions that implement a timer peripheral - * - (void *) data object that is associated with the Timer_FxnTable - * - (void *) hardware attributes that are associated with the Timer_FxnTable - * - * The timer APIs are redirected to the device specific implementations - * using the Timer_FxnTable pointer of the Timer_config entry. - * In order to use device specific functions of the timer driver directly, - * link in the correct driver library for your device and include the - * device specific timer driver header file (which in turn includes Timer.h). - * For example, for the MSP432 family of devices, you would include the - * following header file: - * - * @code - * #include - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_drivers_Timer__include -#define ti_drivers_Timer__include - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include - -/*! - * Common Timer_control command code reservation offset. - * Timer driver implementations should offset command codes with Timer_CMD_RESERVED - * growing positively - * - * Example implementation specific command codes: - * @code - * #define TimerXYZ_CMD_COMMAND0 Timer_CMD_RESERVED + 0 - * #define TimerXYZ_CMD_COMMAND1 Timer_CMD_RESERVED + 1 - * @endcode - */ -#define Timer_CMD_RESERVED (32) - -/*! - * Common Timer_control status code reservation offset. - * Timer driver implementations should offset status codes with - * Timer_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define TimerXYZ_STATUS_ERROR0 Timer_STATUS_RESERVED - 0 - * #define TimerXYZ_STATUS_ERROR1 Timer_STATUS_RESERVED - 1 - * @endcode - */ -#define Timer_STATUS_RESERVED (-32) - -/*! - * @brief Successful status code. - */ -#define Timer_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code. - */ -#define Timer_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by Timer_control() for undefined - * command codes. - * - * Timer_control() returns Timer_STATUS_UNDEFINEDCMD if the control code is not - * recognized by the driver implementation. - */ -#define Timer_STATUS_UNDEFINEDCMD (-2) - -/*! - * @brief A handle that is returned from a Timer_open() call. - */ -typedef struct Timer_Config_ *Timer_Handle; - -/*! - * @brief Timer mode settings - * - * This enum defines the timer modes that may be specified in #Timer_Params. - */ -typedef enum Timer_Mode_ { - Timer_ONESHOT_CALLBACK, /*!< User routine doesn't get blocked and - user-specified callback function is - invoked once the timer interrupt happens - for only one time */ - Timer_ONESHOT_BLOCKING, /*!< User routine gets blocked until timer - interrupt happens for only one time. */ - Timer_CONTINUOUS_CALLBACK, /*!< User routine doesn't get blocked and - user-specified callback function is - invoked with every timer interrupt. */ - Timer_FREE_RUNNING -} Timer_Mode; - -/*! - * @brief Timer period unit enum - * - * This enum defines the units that may be specified for the period - * in #Timer_Params. This unit has no effect with Timer_getCounts. - */ -typedef enum Timer_PeriodUnits_ { - Timer_PERIOD_US, /*!< Period specified in micro seconds. */ - Timer_PERIOD_HZ, /*!< Period specified in hertz; interrupts per - second. */ - Timer_PERIOD_COUNTS /*!< Period specified in ticks or counts. Varies - from board to board. */ -} Timer_PeriodUnits; - -/*! - * @brief Timer callback function - * - * User definable callback function prototype. The timer driver will call the - * defined function and pass in the timer driver's handle and the pointer to the - * user-specified the argument. - * - * @param handle Timer_Handle - */ -typedef void (*Timer_CallBackFxn)(Timer_Handle handle); - -/*! - * @brief Timer Parameters - * - * Timer parameters are used to with the Timer_open() call. Default values for - * these parameters are set using Timer_Params_init(). - * - */ -typedef struct Timer_Params_ { - /*! Mode to be used by the timer driver. */ - Timer_Mode timerMode; - - /*! Units used to specify the period. */ - Timer_PeriodUnits periodUnits; - - /*! Callback function called when timerMode is Timer_ONESHOT_CALLBACK or - Timer_CONTINUOUS_CALLBACK. */ - Timer_CallBackFxn timerCallback; - - /*! Period in units of periodUnits. */ - uint32_t period; -} Timer_Params; - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_control(). - */ -typedef int_fast16_t (*Timer_ControlFxn)(Timer_Handle handle, - uint_fast16_t cmd, void *arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_close(). - */ -typedef void (*Timer_CloseFxn)(Timer_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_getCount(). - */ -typedef uint32_t (*Timer_GetCountFxn)(Timer_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_init(). - */ -typedef void (*Timer_InitFxn)(Timer_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_open(). - */ -typedef Timer_Handle (*Timer_OpenFxn)(Timer_Handle handle, - Timer_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_start(). - */ -typedef int32_t (*Timer_StartFxn)(Timer_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Timer_stop(). - */ -typedef void (*Timer_StopFxn)(Timer_Handle handle); - -/*! - * @brief The definition of a timer function table that contains the - * required set of functions to control a specific timer driver - * implementation. - */ -typedef struct Timer_FxnTable_ { - /*! Function to close the specified peripheral. */ - Timer_CloseFxn closeFxn; - - /*! Function to implementation specific control function. */ - Timer_ControlFxn controlFxn; - - /*! Function to get the count of the specified peripheral. */ - Timer_GetCountFxn getCountFxn; - - /*! Function to initialize the given data object. */ - Timer_InitFxn initFxn; - - /*! Function to open the specified peripheral. */ - Timer_OpenFxn openFxn; - - /*! Function to start the specified peripheral. */ - Timer_StartFxn startFxn; - - /*! Function to stop the specified peripheral. */ - Timer_StopFxn stopFxn; -} Timer_FxnTable; - -/*! - * @brief Timer Global configuration - * - * The Timer_Config structure contains a set of pointers used to characterize - * the timer driver implementation. - * - * This structure needs to be defined before calling Timer_init() and it must - * not be changed thereafter. - * - * @sa Timer_init() - */ -typedef struct Timer_Config_ { - /*! Pointer to a table of driver-specific implementations of timer APIs. */ - Timer_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver specific data object. */ - void *object; - - /*! Pointer to a driver specific hardware attributes structure. */ - void const *hwAttrs; -} Timer_Config; - -/*! - * @brief Function to close a timer. The corresponding timer to the - * Timer_Handle becomes an available timer resource. - * - * @pre Timer_open() has been called. - * - * @param handle A Timer_Handle returned from Timer_open(). - * - * @sa Timer_open() - */ -extern void Timer_close(Timer_Handle handle); - -/*! - * @brief Function performs device specific features on a given - * Timer_Handle. - * - * @pre Timer_open() has been called. - * - * @param handle A Timer_Handle returned from Timer_open(). - * - * @param cmd A command value defined by the driver specific - * implementation. - * - * @param arg A pointer to an optional R/W (read/write) argument that - * is accompanied with cmd. - * - * @return A Timer_Status describing an error or success state. Negative - * values indicate an error occurred. - * - * @sa Timer_open() - */ -extern int_fast16_t Timer_control(Timer_Handle handle, uint_fast16_t cmd, - void *arg); - -/*! - * @brief Function to get the current count of a timer. The value returned - * represents timer counts. The value returned is always - * characteristic of an up counter. This is true even if the timer - * peripheral is counting down. Some device specific implementations - * may employ a prescaler in addition to this timer count. - * - * @pre Timer_open() has been called. - * - * @param handle A Timer_Handle returned from Timer_open(). - * - * @sa Timer_open() - * - * @return The current count of the timer in timer ticks. - * - */ -extern uint32_t Timer_getCount(Timer_Handle handle); - - -/*! - * @brief Function to initialize a timer module. This function will go through - * all available hardware resources and mark them as "available". - * - * @pre The Timer_config structure must exist and be persistent before this - * function can be called. This function must also be called before - * any other timer driver APIs. - * - * @sa Timer_open() - */ -extern void Timer_init(void); - -/*! - * @brief Function to initialize a given timer peripheral specified by the - * index argument. The Timer_Params specifies which mode the timer - * will operate. The accuracy of the desired period is limited by the - * the clock. For example, a 100 MHz clock will have a tick resolution - * of 10 nanoseconds. This function takes care of timer resource - * allocation. If the particular timer is available to use, the timer - * driver owns it and returns a Timer_Handle. - * - * @pre Timer_init() has been called. - * - * @param index Logical peripheral number for the timer indexed into - * the Timer_config table. - * - * @param params Pointer to an parameter block, if NULL it will use - * default values. - * - * @return A Timer_Handle upon success or NULL. If the desired period results - * in overflow, or saturation, of the timer, NULL is returned. If the - * timer resource is already in use, NULL is returned. - * - * @sa Timer_init() - * @sa Timer_close() - */ -extern Timer_Handle Timer_open(uint_least8_t index, Timer_Params *params); - -/*! - * @brief Function to initialize the Timer_Params struct to its defaults. - * - * @param params A pointer to Timer_Params structure for - * initialization. - * - * Defaults values are: - * timerMode = Timer_ONESHOT_BLOCKING - * periodUnit = Timer_PERIOD_COUNTS - * timerCallback = NULL - * period = (uint16_t) ~0 - */ -extern void Timer_Params_init(Timer_Params *params); - -/*! - * @brief Function to start the timer. - * - * @pre Timer_open() has been called. - * - * @param handle A Timer_Handle returned from Timer_open(). - * - * @return Timer_STATUS_SUCCESS or Timer_STATUS_ERROR. - * - * @sa Timer_stop() - */ -extern int32_t Timer_start(Timer_Handle handle); - -/*! - * @brief Function to stop timer. If the timer is already stopped, this - * function has no effect. - * - * @pre Timer_open() has been called. - * - * @param handle A Timer_Handle returned from Timer_open(). - * - * @sa Timer_start() - */ -extern void Timer_stop(Timer_Handle handle); - -/* The following are included for backwards compatibility. These should not be - * used by the application. - */ -#define TIMER_CMD_RESERVED Timer_CMD_RESERVED -#define TIMER_STATUS_RESERVED Timer_STATUS_RESERVED -#define TIMER_STATUS_SUCCESS Timer_STATUS_SUCCESS -#define TIMER_STATUS_ERROR Timer_STATUS_ERROR -#define TIMER_STATUS_UNDEFINEDCMD Timer_STATUS_UNDEFINEDCMD -#define TIMER_ONESHOT_CB Timer_ONESHOT_CALLBACK -#define TIMER_ONESHOT_BLOCK Timer_ONESHOT_BLOCKING -#define TIMER_CONTINUOUS_CB Timer_CONTINUOUS_CALLBACK -#define TIMER_MODE_FREE_RUNNING Timer_FREE_RUNNING -#define TIMER_PERIOD_US Timer_PERIOD_US -#define TIMER_PERIOD_HZ Timer_PERIOD_HZ -#define TIMER_PERIOD_COUNTS Timer_PERIOD_COUNTS -#define Timer_Period_Units Timer_PeriodUnits - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_Timer__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/UART.c b/ext/hal/ti/simplelink/source/ti/drivers/UART.c deleted file mode 100644 index 10a09be6b2d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/UART.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== UART.c ======== - */ - -#include -#include -#include -#include - -#include -#include - -extern const UART_Config UART_config[]; -extern const uint_least8_t UART_count; - -/* Default UART parameters structure */ -const UART_Params UART_defaultParams = { - UART_MODE_BLOCKING, /* readMode */ - UART_MODE_BLOCKING, /* writeMode */ - UART_WAIT_FOREVER, /* readTimeout */ - UART_WAIT_FOREVER, /* writeTimeout */ - NULL, /* readCallback */ - NULL, /* writeCallback */ - UART_RETURN_NEWLINE, /* readReturnMode */ - UART_DATA_TEXT, /* readDataMode */ - UART_DATA_TEXT, /* writeDataMode */ - UART_ECHO_ON, /* readEcho */ - 115200, /* baudRate */ - UART_LEN_8, /* dataLength */ - UART_STOP_ONE, /* stopBits */ - UART_PAR_NONE, /* parityType */ - NULL /* custom */ -}; - -static bool isInitialized = false; - -/* - * ======== UART_close ======== - */ -void UART_close(UART_Handle handle) -{ - handle->fxnTablePtr->closeFxn(handle); -} - -/* - * ======== UART_control ======== - */ -int_fast16_t UART_control(UART_Handle handle, uint_fast16_t cmd, void *arg) -{ - return (handle->fxnTablePtr->controlFxn(handle, cmd, arg)); -} - -/* - * ======== UART_init ======== - */ -void UART_init(void) -{ - uint_least8_t i; - uint_fast32_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - for (i = 0; i < UART_count; i++) { - UART_config[i].fxnTablePtr->initFxn((UART_Handle) &(UART_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== UART_open ======== - */ -UART_Handle UART_open(uint_least8_t index, UART_Params *params) -{ - UART_Handle handle = NULL; - - if (isInitialized && (index < UART_count)) { - /* If params are NULL use defaults */ - if (params == NULL) { - params = (UART_Params *) &UART_defaultParams; - } - - /* Get handle for this driver instance */ - handle = (UART_Handle)&(UART_config[index]); - handle = handle->fxnTablePtr->openFxn(handle, params); - } - - return (handle); -} - -/* - * ======== UART_Params_init ======== - */ -void UART_Params_init(UART_Params *params) -{ - *params = UART_defaultParams; -} - -/* - * ======== UART_read ======== - */ -int_fast32_t UART_read(UART_Handle handle, void *buffer, size_t size) -{ - return (handle->fxnTablePtr->readFxn(handle, buffer, size)); -} - -/* - * ======== UART_readPolling ======== - */ -int_fast32_t UART_readPolling(UART_Handle handle, void *buffer, size_t size) -{ - return (handle->fxnTablePtr->readPollingFxn(handle, buffer, size)); -} - -/* - * ======== UART_readCancel ======== - */ -void UART_readCancel(UART_Handle handle) -{ - handle->fxnTablePtr->readCancelFxn(handle); -} - -/* - * ======== UART_write ======== - */ -int_fast32_t UART_write(UART_Handle handle, const void *buffer, size_t size) -{ - return (handle->fxnTablePtr->writeFxn(handle, buffer, size)); -} - -/* - * ======== UART_writePolling ======== - */ -int_fast32_t UART_writePolling(UART_Handle handle, const void *buffer, - size_t size) -{ - return (handle->fxnTablePtr->writePollingFxn(handle, buffer, size)); -} - -/* - * ======== UART_writeCancel ======== - */ -void UART_writeCancel(UART_Handle handle) -{ - handle->fxnTablePtr->writeCancelFxn(handle); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/UART.h b/ext/hal/ti/simplelink/source/ti/drivers/UART.h deleted file mode 100644 index 246198d7aa1..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/UART.h +++ /dev/null @@ -1,958 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file UART.h - * @brief UART driver interface - * - * To use the UART driver, ensure that the correct driver library for your - * device is linked in and include this header file as follows: - * @code - * #include - * @endcode - * - * This module serves as the main interface for applications. Its purpose - * is to redirect the UART APIs to specific driver implementations - * which are specified using a pointer to a #UART_FxnTable. - * - * # Overview # - * A UART is used to translate data between the chip and a serial port. - * The UART driver simplifies reading and writing to any of the UART - * peripherals on the board, with multiple modes of operation and performance. - * These include blocking, non-blocking, and polling, as well as text/binary - * mode, echo and return characters. - * - * The APIs in this driver serve as an interface to a typical RTOS - * application. The specific peripheral implementations are responsible for - * creating all the RTOS specific primitives to allow for thread-safe - * operation. - * - * # Usage # - * - * The UART driver interface provides device independent APIs, data types, - * and macros. The following code example opens a UART instance, reads - * a byte from the UART, and then writes the byte back to the UART. - * - * @code - * char input; - * UART_Handle uart; - * UART_Params uartParams; - * - * // Initialize the UART driver. - * UART_init(); - * - * // Create a UART with data processing off. - * UART_Params_init(&uartParams); - * uartParams.writeDataMode = UART_DATA_BINARY; - * uartParams.readDataMode = UART_DATA_BINARY; - * uartParams.readReturnMode = UART_RETURN_FULL; - * uartParams.readEcho = UART_ECHO_OFF; - * uartParams.baudRate = 115200; - * - * // Open an instance of the UART drivers - * uart = UART_open(Board_UART0, &uartParams); - * - * if (uart == NULL) { - * // UART_open() failed - * while (1); - * } - * - * // Loop forever echoing - * while (1) { - * UART_read(uart, &input, 1); - * UART_write(uart, &input, 1); - * } - * @endcode - * - * Details for the example code above are described in the following - * subsections. - * - * - * ### UART Driver Configuration # - * - * In order to use the UART APIs, the application is required - * to provide device-specific UART configuration in the Board.c file. - * The UART driver interface defines a configuration data structure: - * - * @code - * typedef struct UART_Config_ { - * UART_FxnTable const *fxnTablePtr; - * void *object; - * void const *hwAttrs; - * } UART_Config; - * @endcode - * - * The application must declare an array of UART_Config elements, named - * UART_config[]. Each element of UART_config[] are populated with - * pointers to a device specific UART driver implementation's function - * table, driver object, and hardware attributes. The hardware attributes - * define properties such as the UART peripheral's base address, and - * the pins for RX and TX. Each element in UART_config[] corresponds to - * a UART instance, and none of the elements should have NULL pointers. - * There is no correlation between the index and the peripheral designation - * (such as UART0 or UART1). For example, it is possible to use - * UART_config[0] for UART1. - * - * You will need to check the device-specific UART driver implementation's - * header file for example configuration. Please also refer to the - * Board.c file of any of your examples to see the UART configuration. - * - * ### Initializing the UART Driver # - * - * UART_init() must be called before any other UART APIs. This function - * calls the device implementation's UART initialization function, for each - * element of UART_config[]. - * - * ### Opening the UART Driver # - * - * Opening a UART requires four steps: - * 1. Create and initialize a UART_Params structure. - * 2. Fill in the desired parameters. - * 3. Call UART_open(), passing the index of the UART in the UART_config - * structure, and the address of the UART_Params structure. The - * UART instance is specified by the index in the UART_config structure. - * 4. Check that the UART handle returned by UART_open() is non-NULL, - * and save it. The handle will be used to read and write to the - * UART you just opened. - * - * Only one UART index can be used at a time; calling UART_open() a second - * time with the same index previosly passed to UART_open() will result in - * an error. You can, though, re-use the index if the instance is closed - * via UART_close(). - * In the example code, Board_UART0 is passed to UART_open(). This macro - * is defined in the example's Board.h file. - * - * - * ### Modes of Operation # - * - * The UART driver can operate in blocking mode or callback mode, by - * setting the writeMode and readMode parameters passed to UART_open(). - * If these parameters are not set, as in the example code, the UART - * driver defaults to blocking mode. Options for the writeMode and - * readMode parameters are #UART_MODE_BLOCKING and #UART_MODE_CALLBACK: - * - * - #UART_MODE_BLOCKING uses a semaphore to block while data is being sent. - * The context of calling UART_read() or UART_write() must be a Task when - * using #UART_MODE_BLOCKING. The UART_write() or UART_read() call - * will block until all data is sent or received, or the write timeout or - * read timeout expires, whichever happens first. - * - * - #UART_MODE_CALLBACK is non-blocking and UART_read() and UART_write() - * will return while data is being sent in the context of a hardware - * interrupt. When the read or write finishes, the UART driver will call - * the user's callback function. In some cases, the UART data transfer - * may have been canceled, or a newline may have been received, so the - * number of bytes sent/received are passed to the callback function. Your - * implementation of the callback function can use this information - * as needed. Since the user's callback may be called in the context of an - * ISR, the callback function must not make any RTOS blocking calls. - * The buffer passed to UART_write() in #UART_MODE_CALLBACK is not copied. - * The buffer must remain coherent until all the characters have been sent - * (ie until the tx callback has been called with a byte count equal to - * that passed to UART_write()). - * - * The example sets the writeDataMode and readDataMode parameters to - * #UART_DATA_BINARY. Options for these parameters are #UART_DATA_BINARY - * and #UART_DATA_TEXT: - * - * - #UART_DATA_BINARY: The data is passed as is, without processing. - * - * - #UART_DATA_TEXT: Write actions add a carriage return before a - * newline character, and read actions replace a return with a newline. - * This effectively treats all device line endings as LF and all host - * PC line endings as CRLF. - * - * Other parameters set by the example are readReturnMode and readEcho. - * Options for the readReturnMode parameter are #UART_RETURN_FULL and - * #UART_RETURN_NEWLINE: - * - * - #UART_RETURN_FULL: The read action unblocks or returns when the buffer - * is full. - * - #UART_RETURN_NEWLINE: The read action unblocks or returns when a - * newline character is read, before the buffer is full. - * - * Options for the readEcho parameter are #UART_ECHO_OFF and #UART_ECHO_ON. - * This parameter determines whether the driver echoes data back to the - * UART. When echo is turned on, each character that is read by the target - * is written back, independent of any write operations. If data is - * received in the middle of a write and echo is turned on, the echoed - * characters will be mixed in with the write data. - * - * ### Reading and Writing data # - * - * The example code reads one byte frome the UART instance, and then writes - * one byte back to the same instance: - * - * @code - * UART_read(uart, &input, 1); - * UART_write(uart, &input, 1); - * @endcode - * - * The UART driver allows full duplex data transfers. Therefore, it is - * possible to call UART_read() and UART_write() at the same time (for - * either blocking or callback modes). It is not possible, however, - * to issue multiple concurrent operations in the same direction. - * For example, if one thread calls UART_read(uart0, buffer0...), - * any other thread attempting UART_read(uart0, buffer1...) will result in - * an error of UART_STATUS_ERROR, until all the data from the first UART_read() - * has been transferred to buffer0. This applies to both blocking and - * and callback modes. So applications must either synchronize - * UART_read() (or UART_write()) calls that use the same UART handle, or - * check for the UART_STATUS_ERROR return code indicating that a transfer is - * still ongoing. - * - * # Implementation # - * - * The UART driver interface module is joined (at link time) to an - * array of UART_Config data structures named *UART_config*. - * UART_config is implemented in the application with each entry being an - * instance of a UART peripheral. Each entry in *UART_config* contains a: - * - (UART_FxnTable *) to a set of functions that implement a UART peripheral - * - (void *) data object that is associated with the UART_FxnTable - * - (void *) hardware attributes that are associated with the UART_FxnTable - * - * The UART APIs are redirected to the device specific implementations - * using the UART_FxnTable pointer of the UART_config entry. - * In order to use device specific functions of the UART driver directly, - * link in the correct driver library for your device and include the - * device specific UART driver header file (which in turn includes UART.h). - * For example, for the MSP432 family of devices, you would include the - * following header file: - * @code - * #include - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_drivers_UART__include -#define ti_drivers_UART__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/** - * @defgroup UART_CONTROL UART_control command and status codes - * These UART macros are reservations for UART.h - * @{ - */ - -/*! - * Common UART_control command code reservation offset. - * UART driver implementations should offset command codes with - * UART_CMD_RESERVED growing positively - * - * Example implementation specific command codes: - * @code - * #define UARTXYZ_CMD_COMMAND0 UART_CMD_RESERVED + 0 - * #define UARTXYZ_CMD_COMMAND1 UART_CMD_RESERVED + 1 - * @endcode - */ -#define UART_CMD_RESERVED (32) - -/*! - * Common UART_control status code reservation offset. - * UART driver implementations should offset status codes with - * UART_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define UARTXYZ_STATUS_ERROR0 UART_STATUS_RESERVED - 0 - * #define UARTXYZ_STATUS_ERROR1 UART_STATUS_RESERVED - 1 - * #define UARTXYZ_STATUS_ERROR2 UART_STATUS_RESERVED - 2 - * @endcode - */ -#define UART_STATUS_RESERVED (-32) - -/** - * @defgroup UART_STATUS Status Codes - * UART_STATUS_* macros are general status codes returned by UART_control() - * @{ - * @ingroup UART_CONTROL - */ - -/*! - * @brief Successful status code returned by UART_control(). - * - * UART_control() returns UART_STATUS_SUCCESS if the control code was executed - * successfully. - */ -#define UART_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by UART_control(). - * - * UART_control() returns UART_STATUS_ERROR if the control code was not executed - * successfully. - */ -#define UART_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by UART_control() for undefined - * command codes. - * - * UART_control() returns UART_STATUS_UNDEFINEDCMD if the control code is not - * recognized by the driver implementation. - */ -#define UART_STATUS_UNDEFINEDCMD (-2) -/** @}*/ - -/** - * @defgroup UART_CMD Command Codes - * UART_CMD_* macros are general command codes for UART_control(). Not all UART - * driver implementations support these command codes. - * @{ - * @ingroup UART_CONTROL - */ - -/*! - * @brief Command code used by UART_control() to read the next unsigned char. - * - * This command is used to read the next unsigned char from the UART's circular - * buffer without removing it. With this command code, @b arg is a pointer to an - * integer. @b *arg contains the next @c unsigned @c char read if data is - * present, else @b *arg is set to #UART_STATUS_ERROR. - */ -#define UART_CMD_PEEK (0) - -/*! - * @brief Command code used by UART_control() to determine if the read buffer - * is empty. - * - * This command is used to determine if there are any unsigned chars available - * to read from the UART's circular buffer using UART_read(). With this command - * code, @b arg is a pointer to a @c bool. @b *arg contains @c true if data is - * available, else @c false. - */ -#define UART_CMD_ISAVAILABLE (1) - -/*! - * @brief Command code used by UART_control() to determine how many unsigned - * chars are in the read buffer. - * - * This command is used to determine how many @c unsigned @c chars are available - * to read from the UART's circular buffer using UART_read(). With this command - * code, @b arg is a pointer to an @a integer. @b *arg contains the number of - * @c unsigned @c chars available to read. - */ -#define UART_CMD_GETRXCOUNT (2) - -/*! - * @brief Command code used by UART_control() to enable data receive by the - * UART. - * - * This command is used to enable the UART in such a way that it stores received - * unsigned chars into the circular buffer. For drivers that support power - * management, this typically means that the UART will set a power constraint - * while receive is enabled. UART_open() will always have this option - * enabled. With this command code, @b arg is @a don't @a care. - */ -#define UART_CMD_RXENABLE (3) - -/*! - * @brief Command code used by UART_control() to disable data received by the - * UART. - * - * This command is used to disable the UART in such a way that ignores the data - * it receives. For drivers that support power management, this typically means - * that the driver will release any power constraints, to permit the system to - * enter low power modes. With this command code, @b arg is @a don't @a care. - * - * @warning A call to UART_read() does @b NOT re-enable receive. - */ -#define UART_CMD_RXDISABLE (4) -/** @}*/ - -/** @}*/ - -#define UART_ERROR (UART_STATUS_ERROR) - -/*! - * @brief Wait forever define - */ -#define UART_WAIT_FOREVER (~(0U)) - -/*! - * @brief A handle that is returned from a UART_open() call. - */ -typedef struct UART_Config_ *UART_Handle; - -/*! - * @brief The definition of a callback function used by the UART driver - * when used in #UART_MODE_CALLBACK - * The callback can occur in task or HWI context. - * - * @param UART_Handle UART_Handle - * - * @param buf Pointer to read/write buffer - * - * @param count Number of elements read/written - */ -typedef void (*UART_Callback) (UART_Handle handle, void *buf, size_t count); - -/*! - * @brief UART mode settings - * - * This enum defines the read and write modes for the configured UART. - */ -typedef enum UART_Mode_ { - /*! - * Uses a semaphore to block while data is being sent. Context of the call - * must be a Task. - */ - UART_MODE_BLOCKING, - - /*! - * Non-blocking and will return immediately. When UART_write() or - * UART_read() has finished, the callback function is called from either - * the caller's context or from an interrupt context. - */ - UART_MODE_CALLBACK -} UART_Mode; - -/*! - * @brief UART return mode settings - * - * This enumeration defines the return modes for UART_read() and - * UART_readPolling(). This mode only functions when in #UART_DATA_TEXT mode. - * - * #UART_RETURN_FULL unblocks or performs a callback when the read buffer has - * been filled. - * #UART_RETURN_NEWLINE unblocks or performs a callback whenever a newline - * character has been received. - * - * UART operation | UART_RETURN_FULL | UART_RETURN_NEWLINE | - * -------------- | ---------------- | ------------------- | - * UART_read() | Returns when buffer is full | Returns when buffer is full or newline was read | - * UART_write() | Sends data as is | Sends data with an additional newline at the end | - * - * @pre UART driver must be used in #UART_DATA_TEXT mode. - */ -typedef enum UART_ReturnMode_ { - /*! Unblock/callback when buffer is full. */ - UART_RETURN_FULL, - - /*! Unblock/callback when newline character is received. */ - UART_RETURN_NEWLINE -} UART_ReturnMode; - -/*! - * @brief UART data mode settings - * - * This enumeration defines the data mode for reads and writes. - * - * In #UART_DATA_BINARY, data is passed as is, with no processing. - * - * In #UART_DATA_TEXT mode, the driver will examine the #UART_ReturnMode - * value, to determine whether or not to unblock/callback when a newline - * is received. Read actions replace a carriage return with a newline, - * and write actions add a carriage return before a newline. This - * effectively treats all device line endings as LF, and all host PC line - * endings as CRLF. - */ -typedef enum UART_DataMode_ { - UART_DATA_BINARY = 0, /*!< Data is not processed */ - UART_DATA_TEXT = 1 /*!< Data is processed according to above */ -} UART_DataMode; - -/*! - * @brief UART echo settings - * - * This enumeration defines if the driver will echo data when uses in - * #UART_DATA_TEXT mode. This only applies to data received by the UART. - * - * #UART_ECHO_ON will echo back characters it received while in #UART_DATA_TEXT - * mode. - * #UART_ECHO_OFF will not echo back characters it received in #UART_DATA_TEXT - * mode. - * - * @pre UART driver must be used in #UART_DATA_TEXT mode. - */ -typedef enum UART_Echo_ { - UART_ECHO_OFF = 0, /*!< Data is not echoed */ - UART_ECHO_ON = 1 /*!< Data is echoed */ -} UART_Echo; - -/*! - * @brief UART data length settings - * - * This enumeration defines the UART data lengths. - */ -typedef enum UART_LEN_ { - UART_LEN_5 = 0, /*!< Data length is 5 bits */ - UART_LEN_6 = 1, /*!< Data length is 6 bits */ - UART_LEN_7 = 2, /*!< Data length is 7 bits */ - UART_LEN_8 = 3 /*!< Data length is 8 bits */ -} UART_LEN; - -/*! - * @brief UART stop bit settings - * - * This enumeration defines the UART stop bits. - */ -typedef enum UART_STOP_ { - UART_STOP_ONE = 0, /*!< One stop bit */ - UART_STOP_TWO = 1 /*!< Two stop bits */ -} UART_STOP; - -/*! - * @brief UART parity type settings - * - * This enumeration defines the UART parity types. - */ -typedef enum UART_PAR_ { - UART_PAR_NONE = 0, /*!< No parity */ - UART_PAR_EVEN = 1, /*!< Parity bit is even */ - UART_PAR_ODD = 2, /*!< Parity bit is odd */ - UART_PAR_ZERO = 3, /*!< Parity bit is always zero */ - UART_PAR_ONE = 4 /*!< Parity bit is always one */ -} UART_PAR; - -/*! - * @brief UART Parameters - * - * UART parameters are used with the UART_open() call. Default values for - * these parameters are set using UART_Params_init(). - * - * @sa UART_Params_init() - */ -typedef struct UART_Params_ { - UART_Mode readMode; /*!< Mode for all read calls */ - UART_Mode writeMode; /*!< Mode for all write calls */ - uint32_t readTimeout; /*!< Timeout for read calls in blocking mode. */ - uint32_t writeTimeout; /*!< Timeout for write calls in blocking mode. */ - UART_Callback readCallback; /*!< Pointer to read callback function for callback mode. */ - UART_Callback writeCallback; /*!< Pointer to write callback function for callback mode. */ - UART_ReturnMode readReturnMode; /*!< Receive return mode */ - UART_DataMode readDataMode; /*!< Type of data being read */ - UART_DataMode writeDataMode; /*!< Type of data being written */ - UART_Echo readEcho; /*!< Echo received data back */ - uint32_t baudRate; /*!< Baud rate for UART */ - UART_LEN dataLength; /*!< Data length for UART */ - UART_STOP stopBits; /*!< Stop bits for UART */ - UART_PAR parityType; /*!< Parity bit type for UART */ - void *custom; /*!< Custom argument used by driver implementation */ -} UART_Params; - -/*! - * @brief A function pointer to a driver specific implementation of - * UART_CloseFxn(). - */ -typedef void (*UART_CloseFxn) (UART_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * UART_ControlFxn(). - */ -typedef int_fast16_t (*UART_ControlFxn) (UART_Handle handle, uint_fast16_t cmd, void *arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * UART_InitFxn(). - */ -typedef void (*UART_InitFxn) (UART_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * UART_OpenFxn(). - */ -typedef UART_Handle (*UART_OpenFxn) (UART_Handle handle, UART_Params *params); -/*! - * @brief A function pointer to a driver specific implementation of - * UART_ReadFxn(). - */ -typedef int_fast32_t (*UART_ReadFxn) (UART_Handle handle, void *buffer, - size_t size); - -/*! - * @brief A function pointer to a driver specific implementation of - * UART_ReadPollingFxn(). - */ -typedef int_fast32_t (*UART_ReadPollingFxn) (UART_Handle handle, void *buffer, - size_t size); - -/*! - * @brief A function pointer to a driver specific implementation of - * UART_ReadCancelFxn(). - */ -typedef void (*UART_ReadCancelFxn) (UART_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * UART_WriteFxn(). - */ -typedef int_fast32_t (*UART_WriteFxn) (UART_Handle handle, const void *buffer, - size_t size); - -/*! - * @brief A function pointer to a driver specific implementation of - * UART_WritePollingFxn(). - */ -typedef int_fast32_t (*UART_WritePollingFxn) (UART_Handle handle, - const void *buffer, size_t size); - -/*! - * @brief A function pointer to a driver specific implementation of - * UART_WriteCancelFxn(). - */ -typedef void (*UART_WriteCancelFxn) (UART_Handle handle); - -/*! - * @brief The definition of a UART function table that contains the - * required set of functions to control a specific UART driver - * implementation. - */ -typedef struct UART_FxnTable_ { - /*! Function to close the specified peripheral */ - UART_CloseFxn closeFxn; - - /*! Function to implementation specific control function */ - UART_ControlFxn controlFxn; - - /*! Function to initialize the given data object */ - UART_InitFxn initFxn; - - /*! Function to open the specified peripheral */ - UART_OpenFxn openFxn; - - /*! Function to read from the specified peripheral */ - UART_ReadFxn readFxn; - - /*! Function to read via polling from the specified peripheral */ - UART_ReadPollingFxn readPollingFxn; - - /*! Function to cancel a read from the specified peripheral */ - UART_ReadCancelFxn readCancelFxn; - - /*! Function to write from the specified peripheral */ - UART_WriteFxn writeFxn; - - /*! Function to write via polling from the specified peripheral */ - UART_WritePollingFxn writePollingFxn; - - /*! Function to cancel a write from the specified peripheral */ - UART_WriteCancelFxn writeCancelFxn; -} UART_FxnTable; - -/*! - * @brief UART Global configuration - * - * The UART_Config structure contains a set of pointers used to characterize - * the UART driver implementation. - * - * This structure needs to be defined before calling UART_init() and it must - * not be changed thereafter. - * - * @sa UART_init() - */ -typedef struct UART_Config_ { - /*! Pointer to a table of driver-specific implementations of UART APIs */ - UART_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver specific data object */ - void *object; - - /*! Pointer to a driver specific hardware attributes structure */ - void const *hwAttrs; -} UART_Config; - -/*! - * @brief Function to close a UART peripheral specified by the UART handle - * - * @pre UART_open() has been called. - * @pre Ongoing asynchronous read or write have been canceled using - * UART_readCancel() or UART_writeCancel() respectively. - * - * @param handle A #UART_Handle returned from UART_open() - * - * @sa UART_open() - */ -extern void UART_close(UART_Handle handle); - -/*! - * @brief Function performs implementation specific features on a given - * #UART_Handle. - * - * Commands for %UART_control() can originate from UART.h or from implementation - * specific UART*.h (_UARTCC26XX.h_, _UARTMSP432.h_, etc.. ) files. - * While commands from UART.h are API portable across driver implementations, - * not all implementations may support all these commands. - * Conversely, commands from driver implementation specific UART*.h files add - * unique driver capabilities but are not API portable across all UART driver - * implementations. - * - * Commands supported by UART.h follow a UART_CMD_\ naming - * convention.
- * Commands supported by UART*.h follow a UART*_CMD_\ naming - * convention.
- * Each control command defines @b arg differently. The types of @b arg are - * documented with each command. - * - * See @ref UART_CMD "UART_control command codes" for command codes. - * - * See @ref UART_STATUS "UART_control return status codes" for status codes. - * - * @pre UART_open() has to be called. - * - * @param handle A UART handle returned from UART_open() - * - * @param cmd UART.h or UART*.h commands. - * - * @param arg An optional R/W (read/write) command argument - * accompanied with cmd - * - * @return Implementation specific return codes. Negative values indicate - * unsuccessful operations. - * - * @sa UART_open() - */ -extern int_fast16_t UART_control(UART_Handle handle, uint_fast16_t cmd, void *arg); - -/*! - * @brief Function to initialize the UART module - * - * @pre The UART_config structure must exist and be persistent before this - * function can be called. This function must also be called before - * any other UART driver APIs. - */ -extern void UART_init(void); - -/*! - * @brief Function to initialize a given UART peripheral - * - * Function to initialize a given UART peripheral specified by the - * particular index value. - * - * @pre UART_init() has been called - * - * @param index Logical peripheral number for the UART indexed into - * the UART_config table - * - * @param params Pointer to a parameter block. If NULL, default - * parameter values will be used. All the fields in - * this structure are RO (read-only). - * - * @return A #UART_Handle upon success. NULL if an error occurs, or if the - * indexed UART peripheral is already opened. - * - * @sa UART_init() - * @sa UART_close() - */ -extern UART_Handle UART_open(uint_least8_t index, UART_Params *params); - -/*! - * @brief Function to initialize the UART_Params struct to its defaults - * - * @param params An pointer to UART_Params structure for - * initialization - * - * Defaults values are: - * readMode = UART_MODE_BLOCKING; - * writeMode = UART_MODE_BLOCKING; - * readTimeout = UART_WAIT_FOREVER; - * writeTimeout = UART_WAIT_FOREVER; - * readCallback = NULL; - * writeCallback = NULL; - * readReturnMode = UART_RETURN_NEWLINE; - * readDataMode = UART_DATA_TEXT; - * writeDataMode = UART_DATA_TEXT; - * readEcho = UART_ECHO_ON; - * baudRate = 115200; - * dataLength = UART_LEN_8; - * stopBits = UART_STOP_ONE; - * parityType = UART_PAR_NONE; - */ -extern void UART_Params_init(UART_Params *params); - -/*! - * @brief Function that writes data to a UART with interrupts enabled. - * - * %UART_write() writes data from a memory buffer to the UART interface. - * The source is specified by \a buffer and the number of bytes to write - * is given by \a size. - * - * In #UART_MODE_BLOCKING, UART_write() blocks task execution until all - * the data in buffer has been written. - * - * In #UART_MODE_CALLBACK, %UART_write() does not block task execution. - * Instead, a callback function specified by UART_Params::writeCallback is - * called when the transfer is finished. The buffer passed to UART_write() - * in #UART_MODE_CALLBACK is not copied. The buffer must remain coherent - * until all the characters have been sent (ie until the tx callback has - * been called with a byte count equal to that passed to UART_write()). - * The callback function can occur in the caller's task context or in a HWI or - * SWI context, depending on the device implementation. - * An unfinished asynchronous write operation must always be canceled using - * UART_writeCancel() before calling UART_close(). - * - * %UART_write() is mutually exclusive to UART_writePolling(). For an opened - * UART peripheral, either UART_write() or UART_writePolling() can be used, - * but not both. - * - * @warning Do not call %UART_write() from its own callback function when in - * #UART_MODE_CALLBACK. - * - * @sa UART_writePolling() - * - * @param handle A #UART_Handle returned by UART_open() - * - * @param buffer A read-only pointer to buffer containing data to - * be written to the UART - * - * @param size The number of bytes in the buffer that should be written - * to the UART - * - * @return Returns the number of bytes that have been written to the UART. - * If an error occurs, #UART_STATUS_ERROR is returned. - * In #UART_MODE_CALLBACK mode, the return value is always 0. - */ -extern int_fast32_t UART_write(UART_Handle handle, const void *buffer, size_t size); - -/*! - * @brief Function that writes data to a UART, polling the peripheral to - * wait until new data can be written. Usage of this API is mutually - * exclusive with usage of UART_write(). - * - * This function initiates an operation to write data to a UART controller. - * - * UART_writePolling() will not return until all the data was written to the - * UART (or to its FIFO if applicable). - * - * @sa UART_write() - * - * @param handle A #UART_Handle returned by UART_open() - * - * @param buffer A read-only pointer to the buffer containing the data to - * be written to the UART - * - * @param size The number of bytes in the buffer that should be written - * to the UART - * - * @return Returns the number of bytes that have been written to the UART. - * If an error occurs, #UART_STATUS_ERROR is returned. - */ -extern int_fast32_t UART_writePolling(UART_Handle handle, const void *buffer, size_t size); - -/*! - * @brief Function that cancels a UART_write() function call. - * - * This function cancels an asynchronous UART_write() operation and is only - * applicable in #UART_MODE_CALLBACK. - * UART_writeCancel() calls the registered TX callback function no matter how many bytes - * were sent. It is the application's responsibility to check the count argument in - * the callback function and handle cases where only a subset of the bytes were sent. - * - * @param handle A #UART_Handle returned by UART_open() - */ -extern void UART_writeCancel(UART_Handle handle); - -/*! - * @brief Function that reads data from a UART with interrupt enabled. - * - * %UART_read() reads data from a UART controller. The destination is specified - * by \a buffer and the number of bytes to read is given by \a size. - * - * In #UART_MODE_BLOCKING, %UART_read() blocks task execution until all - * the data in buffer has been read. - * - * In #UART_MODE_CALLBACK, %UART_read() does not block task execution. - * Instead, a callback function specified by UART_Params::readCallback - * is called when the transfer is finished. - * The callback function can occur in the caller's context or in HWI or SWI - * context, depending on the device-specific implementation. - * An unfinished asynchronous read operation must always be canceled using - * UART_readCancel() before calling UART_close(). - * - * %UART_read() is mutually exclusive to UART_readPolling(). For an opened - * UART peripheral, either %UART_read() or UART_readPolling() can be used, - * but not both. - * - * @warning Do not call %UART_read() from its own callback function when in - * #UART_MODE_CALLBACK. - * - * @sa UART_readPolling() - * - * @param handle A #UART_Handle returned by UART_open() - * - * @param buffer A pointer to an empty buffer to which - * received data should be written - * - * @param size The number of bytes to be written into buffer - * - * @return Returns the number of bytes that have been read from the UART, - * #UART_STATUS_ERROR on an error. - */ -extern int_fast32_t UART_read(UART_Handle handle, void *buffer, size_t size); - -/*! - * @brief Function that reads data from a UART without interrupts. This API - * must be used mutually exclusive with UART_read(). - * - * This function initiates an operation to read data from a UART peripheral. - * - * %UART_readPolling() will not return until size data was read to the UART. - * - * @sa UART_read() - * - * @param handle A #UART_Handle returned by UART_open() - * - * @param buffer A pointer to an empty buffer in which - * received data should be written to - * - * @param size The number of bytes to be written into buffer - * - * @return Returns the number of bytes that have been read from the UART, - * #UART_STATUS_ERROR on an error. - */ -extern int_fast32_t UART_readPolling(UART_Handle handle, void *buffer, size_t size); - -/*! - * @brief Function that cancels a UART_read() function call. - * - * This function cancels an asynchronous UART_read() operation and is only - * applicable in #UART_MODE_CALLBACK. - * UART_readCancel() calls the registered RX callback function no matter how many bytes - * were received. It is the application's responsibility to check the count argument in - * the callback function and handle cases where only a subset of the bytes were received. - * - * @param handle A #UART_Handle returned by UART_open() - */ -extern void UART_readCancel(UART_Handle handle); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_UART__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/Watchdog.c b/ext/hal/ti/simplelink/source/ti/drivers/Watchdog.c deleted file mode 100644 index 50c4e19509c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/Watchdog.c +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== Watchdog.c ======== - */ - -#include -#include -#include - -#include -#include - -extern const Watchdog_Config Watchdog_config[]; -extern const uint_least8_t Watchdog_count; - -/* Default Watchdog parameters structure */ -const Watchdog_Params Watchdog_defaultParams = { - NULL, /* callbackFxn */ - Watchdog_RESET_ON, /* resetMode */ - Watchdog_DEBUG_STALL_ON, /* debugStallMode */ - NULL /* custom */ -}; - -static bool isInitialized = false; - -/* - * ======== Watchdog_clear ======== - */ -void Watchdog_clear(Watchdog_Handle handle) -{ - handle->fxnTablePtr->watchdogClear(handle); -} - -/* - * ======== Watchdog_close ======== - */ -void Watchdog_close(Watchdog_Handle handle) -{ - handle->fxnTablePtr->watchdogClose(handle); -} - -/* - * ======== Watchdog_control ======== - */ -int_fast16_t Watchdog_control(Watchdog_Handle handle, uint_fast16_t cmd, - void *arg) -{ - return (handle->fxnTablePtr->watchdogControl(handle, cmd, arg)); -} - -/* - * ======== Watchdog_init ======== - */ -void Watchdog_init(void) -{ - uint_least8_t i; - uint_fast32_t key; - - key = HwiP_disable(); - - if (!isInitialized) { - isInitialized = (bool) true; - - /* Call each driver's init function */ - for (i = 0; i < Watchdog_count; i++) { - Watchdog_config[i].fxnTablePtr->watchdogInit((Watchdog_Handle)&(Watchdog_config[i])); - } - } - - HwiP_restore(key); -} - -/* - * ======== Watchdog_open ======== - */ -Watchdog_Handle Watchdog_open(uint_least8_t index, Watchdog_Params *params) -{ - Watchdog_Handle handle = NULL; - - /* Verify driver index and state */ - if (isInitialized && (index < Watchdog_count)) { - /* If params are NULL use defaults */ - if (params == NULL) { - params = (Watchdog_Params *) &Watchdog_defaultParams; - } - - handle = (Watchdog_Handle)&(Watchdog_config[index]); - handle = handle->fxnTablePtr->watchdogOpen(handle, params); - } - - return (handle); -} - -/* - * ======== Watchdog_Params_init ======== - */ -void Watchdog_Params_init(Watchdog_Params *params) -{ - *params = Watchdog_defaultParams; -} - - -/* - * ======== Watchdog_setReload ======== - */ -int_fast16_t Watchdog_setReload(Watchdog_Handle handle, uint32_t ticks) -{ - return (handle->fxnTablePtr->watchdogSetReload(handle, ticks)); -} - -/* - * ======== Watchdog_convertMsToTicks ======== - */ -uint32_t Watchdog_convertMsToTicks(Watchdog_Handle handle, uint32_t milliseconds) -{ - return (handle->fxnTablePtr->watchdogConvertMsToTicks(handle, milliseconds)); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/Watchdog.h b/ext/hal/ti/simplelink/source/ti/drivers/Watchdog.h deleted file mode 100644 index 6d4f7eeb927..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/Watchdog.h +++ /dev/null @@ -1,540 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file Watchdog.h - * - * @brief Watchdog driver interface - * - * The Watchdog header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * # Overview # - * - * A watchdog timer can be used to generate a reset signal if a system has - * become unresponsive. The Watchdog driver simplifies configuring and - * starting the watchdog peripherals. The watchdog peripheral can be - * configured with resets either on or off and a user-specified timeout - * period. - * - * When the watchdog peripheral is configured not to generate a reset, it - * can be used to cause a hardware interrupt at a programmable interval. - * The driver provides the ability to specify a user-provided callback - * function that is called when the watchdog causes an interrupt. - * - * # Operation # - * - * The Watchdog driver simplifies configuring and starting the Watchdog - * peripherals. The Watchdog can be set up to produce a reset signal after a - * timeout, or simply cause a hardware interrupt at a programmable interval. - * The driver provides the ability to specify a callback function that is - * called when the Watchdog causes an interrupt. - * - * When resets are turned on, it is the user application's responsibility to - * call Watchdog_clear() in order to clear the Watchdog and prevent a reset. - * Watchdog_clear() can be called at any time. - * - * # Usage # - * - * The Watchdog driver must be initialized by calling Watchdog_init(), - * before any other Watchdog APIs can be called. - * Once the watchdog is initialized, a Watchdog object can be created - * through the following steps: - * - Create and initialize the Watchdog_Params structure. - * - Assign desired values to parameters. - * - Call Watchdog_open(). - * - Save the Watchdog_Handle returned by Watchdog_open(). This will be - * used to interact with the Watchdog object just created. - * - * To have a user-defined function run at the hardware interrupt caused by - * a watchdog timer timeout, define a function of the following type: - * @code - * typedef void (*Watchdog_Callback)(uintptr_t); - * @endcode - * Then pass the function to Watchdog_open() through the Watchdog_Params - * structure. - * - * An example of the Watchdog creation process that uses a callback - * function: - * @code - * Watchdog_Params params; - * Watchdog_Handle watchdogHandle; - * - * Watchdog_init(); - * - * Watchdog_Params_init(¶ms); - * params.resetMode = Watchdog_RESET_ON; - * params.callbackFxn = (Watchdog_Callback) UserCallbackFxn; - * - * watchdogHandle = Watchdog_open(Board_WATCHDOG0, ¶ms); - * if (watchdogHandle == NULL) { - * // Error opening Watchdog - * while (1); - * } - * @endcode - * - * If no Watchdog_Params structure is passed to Watchdog_open(), the - * default values are used. By default, the Watchdog driver has resets - * turned on, no callback function specified, and stalls the timer at - * breakpoints during debugging. - * - * Options for the resetMode parameter are Watchdog_RESET_ON and - * Watchdog_RESET_OFF. The latter allows the watchdog to be used like - * another timer interrupt. When resetMode is Watchdog_RESET_ON, it is up - * to the application to call Watchdog_clear() to clear the Watchdog - * interrupt flag to prevent a reset. Watchdog_clear() can be called at - * any time. - * - * # Implementation # - * - * This module serves as the main interface for TI-RTOS applications. Its - * purpose is to redirect the module's APIs to specific peripheral - * implementations which are specified using a pointer to a - * Watchdog_FxnTable. - * - * The Watchdog driver interface module is joined (at link time) - * to a NULL-terminated array of Watchdog_Config data structures named - * *Watchdog_config*. *Watchdog_config* is implemented in the application with - * each entry being an instance of a Watchdog peripheral. Each entry in - * *Watchdog_config* contains a: - * - (Watchdog_FxnTable *) to a set of functions that implement a Watchdog - * peripheral - * - (void *) data object that is associated with the Watchdog_FxnTable - * - (void *) hardware attributes that are associated to the Watchdog_FxnTable - * - ******************************************************************************* - */ - -#ifndef ti_drivers_Watchdog__include -#define ti_drivers_Watchdog__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** - * @defgroup Watchdog_CONTROL Watchdog_control command and status codes - * These Watchdog macros are reservations for Watchdog.h - * @{ - */ - -/*! - * Common Watchdog_control command code reservation offset. - * Watchdog driver implementations should offset command codes with - * Watchdog_CMD_RESERVED growing positively - * - * Example implementation specific command codes: - * @code - * #define WatchdogXYZ_CMD_COMMAND0 Watchdog_CMD_RESERVED + 0 - * #define WatchdogXYZ_CMD_COMMAND1 Watchdog_CMD_RESERVED + 1 - * @endcode - */ -#define Watchdog_CMD_RESERVED (32) - -/*! - * Common Watchdog_control status code reservation offset. - * Watchdog driver implementations should offset status codes with - * Watchdog_STATUS_RESERVED growing negatively. - * - * Example implementation specific status codes: - * @code - * #define WatchdogXYZ_STATUS_ERROR0 Watchdog_STATUS_RESERVED - 0 - * #define WatchdogXYZ_STATUS_ERROR1 Watchdog_STATUS_RESERVED - 1 - * #define WatchdogXYZ_STATUS_ERROR2 Watchdog_STATUS_RESERVED - 2 - * @endcode - */ -#define Watchdog_STATUS_RESERVED (-32) - -/** - * @defgroup Watchdog_STATUS Status Codes - * Watchdog_STATUS_* macros are general status codes returned by Watchdog_control() - * @{ - * @ingroup Watchdog_CONTROL - */ - -/*! - * @brief Successful status code returned by Watchdog_control(). - * - * Watchdog_control() returns Watchdog_STATUS_SUCCESS if the control code was - * executed successfully. - */ -#define Watchdog_STATUS_SUCCESS (0) - -/*! - * @brief Generic error status code returned by Watchdog_control(). - * - * Watchdog_control() returns Watchdog_STATUS_ERROR if the control code was not - * executed successfully. - */ -#define Watchdog_STATUS_ERROR (-1) - -/*! - * @brief An error status code returned by Watchdog_control() for undefined - * command codes. - * - * Watchdog_control() returns Watchdog_STATUS_UNDEFINEDCMD if the control code - * is not recognized by the driver implementation. - */ -#define Watchdog_STATUS_UNDEFINEDCMD (-2) - -/*! - * @brief An error status code returned by Watchdog_setReload() for drivers - * which do not support the aforementioned API. - * - * Watchdog_setReload() returns Watchdog_STATUS_UNSUPPORTED if the driver - * implementation does not support the aforementioned API. - */ -#define Watchdog_STATUS_UNSUPPORTED (-3) -/** @}*/ - -/** - * @defgroup Watchdog_CMD Command Codes - * Watchdog_CMD_* macros are general command codes for Watchdog_control(). Not all Watchdog - * driver implementations support these command codes. - * @{ - * @ingroup Watchdog_CONTROL - */ - -/* Add Watchdog_CMD_ here */ - -/** @}*/ - -/** @}*/ - -/*! -* @brief Watchdog Handle -*/ -typedef struct Watchdog_Config_ *Watchdog_Handle; - -/*! - * @brief Watchdog debug stall settings - * - * This enumeration defines the debug stall modes for the Watchdog. On some - * targets, the Watchdog timer will continue to count down while a debugging - * session is halted. To avoid unwanted resets, the Watchdog can be set to - * stall while the processor is stopped by the debugger. - */ -typedef enum Watchdog_DebugMode_ { - Watchdog_DEBUG_STALL_ON, /*!< Watchdog will be stalled at breakpoints */ - Watchdog_DEBUG_STALL_OFF /*!< Watchdog will keep running at breakpoints */ -} Watchdog_DebugMode; - -/*! - * @brief Watchdog reset mode settings - * - * This enumeration defines the reset modes for the Watchdog. The Watchdog can - * be configured to either generate a reset upon timeout or simply produce a - * periodic interrupt. - */ -typedef enum Watchdog_ResetMode_ { - Watchdog_RESET_OFF, /*!< Timeouts generate interrupts only */ - Watchdog_RESET_ON /*!< Generates reset after timeout */ -} Watchdog_ResetMode; - -/*! - * @brief Watchdog callback pointer - * - * This is the typedef for the function pointer that will allow a callback - * function to be specified in the Watchdog_Params structure. The function - * will take a Watchdog_Handle of the Watchdog causing the interrupt (cast as - * a uintptr_t) as an argument. - */ -typedef void (*Watchdog_Callback)(uintptr_t handle); - -/*! - * @brief Watchdog Parameters - * - * Watchdog parameters are used to with the Watchdog_open() call. Default - * values for these parameters are set using Watchdog_Params_init(). - * - * @sa Watchdog_Params_init() - */ -typedef struct Watchdog_Params_ { - Watchdog_Callback callbackFxn; /*!< Pointer to callback. Not supported - on all targets. */ - Watchdog_ResetMode resetMode; /*!< Mode to enable resets. - Not supported on all targets. */ - Watchdog_DebugMode debugStallMode; /*!< Mode to stall WDT at breakpoints. - Not supported on all targets. */ - void *custom; /*!< Custom argument used by driver - implementation */ -} Watchdog_Params; - -/*! - * @brief A function pointer to a driver specific implementation of - * Watchdog_clear(). - */ -typedef void (*Watchdog_ClearFxn) (Watchdog_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Watchdog_close(). - */ -typedef void (*Watchdog_CloseFxn) (Watchdog_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Watchdog_control(). - */ -typedef int_fast16_t (*Watchdog_ControlFxn) (Watchdog_Handle handle, - uint_fast16_t cmd, - void *arg); - -/*! - * @brief A function pointer to a driver specific implementation of - * Watchdog_init(). - */ -typedef void (*Watchdog_InitFxn) (Watchdog_Handle handle); - -/*! - * @brief A function pointer to a driver specific implementation of - * Watchdog_open(). - */ -typedef Watchdog_Handle (*Watchdog_OpenFxn) (Watchdog_Handle handle, - Watchdog_Params *params); - -/*! - * @brief A function pointer to a driver specific implementation of - * Watchdog_setReload(). - */ -typedef int_fast16_t (*Watchdog_SetReloadFxn)(Watchdog_Handle handle, - uint32_t ticks); - -/*! - * @brief A function pointer to a driver specific implementation of - * Watchdog_ConvertMsToTicksFxn(). - */ -typedef uint32_t (*Watchdog_ConvertMsToTicksFxn) (Watchdog_Handle handle, - uint32_t milliseconds); - -/*! - * @brief The definition of a Watchdog function table that contains the - * required set of functions to control a specific Watchdog driver - * implementation. - */ -typedef struct Watchdog_FxnTable_ { - Watchdog_ClearFxn watchdogClear; - Watchdog_CloseFxn watchdogClose; - Watchdog_ControlFxn watchdogControl; - Watchdog_InitFxn watchdogInit; - Watchdog_OpenFxn watchdogOpen; - Watchdog_SetReloadFxn watchdogSetReload; - Watchdog_ConvertMsToTicksFxn watchdogConvertMsToTicks; -} Watchdog_FxnTable; - -/*! - * @brief Watchdog Global configuration - * - * The Watchdog_Config structure contains a set of pointers used to - * characterize the Watchdog driver implementation. - * - * This structure needs to be defined before calling Watchdog_init() and - * it must not be changed thereafter. - * - * @sa Watchdog_init() - */ -typedef struct Watchdog_Config_ { - /*! - * Pointer to a table of driver-specific implementations of Watchdog APIs - */ - Watchdog_FxnTable const *fxnTablePtr; - - /*! Pointer to a driver specific data object */ - void *object; - - /*! Pointer to a driver specific hardware attributes structure */ - void const *hwAttrs; -} Watchdog_Config; - -/*! - * @brief Clears the Watchdog - * - * Clears the Watchdog to to prevent a reset signal from being generated if the - * module is in Watchdog_RESET_ON reset mode. - * - * @param handle Watchdog Handle - */ -extern void Watchdog_clear(Watchdog_Handle handle); - -/*! - * @brief Function to close a Watchdog peripheral specified by the Watchdog - * handle.It stops (holds) the Watchdog counting on applicable - * platforms. - * - * @pre Watchdog_open() has to be called first. - * - * @param handle A Watchdog_Handle returned from Watchdog_open - * - * @sa Watchdog_open() - */ -extern void Watchdog_close(Watchdog_Handle handle); - -/*! - * @brief Function performs implementation specific features on a given - * Watchdog_Handle. - * - * Commands for Watchdog_control can originate from Watchdog.h or from implementation - * specific Watchdog*.h (_WatchdogCC26XX.h_, _WatchdogMSP432.h_, etc.. ) files. - * While commands from Watchdog.h are API portable across driver implementations, - * not all implementations may support all these commands. - * Conversely, commands from driver implementation specific Watchdog*.h files add - * unique driver capabilities but are not API portable across all Watchdog driver - * implementations. - * - * Commands supported by Watchdog.h follow a Watchdog_CMD_\ naming - * convention.
- * Commands supported by Watchdog*.h follow a Watchdog*_CMD_\ naming - * convention.
- * Each control command defines @b arg differently. The types of @b arg are - * documented with each command. - * - * See @ref Watchdog_CMD "Watchdog_control command codes" for command codes. - * - * See @ref Watchdog_STATUS "Watchdog_control return status codes" for status codes. - * - * @pre Watchdog_open() has to be called first. - * - * @param handle A Watchdog handle returned from Watchdog_open() - * - * @param cmd Watchdog.h or Watchdog*.h commands. - * - * @param arg An optional R/W (read/write) command argument - * accompanied with cmd - * - * @return Implementation specific return codes. Negative values indicate - * unsuccessful operations. - * - * @sa Watchdog_open() - */ -extern int_fast16_t Watchdog_control(Watchdog_Handle handle, - uint_fast16_t cmd, - void *arg); - -/*! - * @brief Initializes the Watchdog module - * - * The application-provided Watchdog_config must be present before the - * Watchdog_init function is called. The Watchdog_config must be persistent - * and not changed after Watchdog_init is called. This function must be called - * before any of the other Watchdog driver APIs. - */ -extern void Watchdog_init(void); - -/*! - * @brief Opens a Watchdog - * - * Opens a Watchdog object with the index and parameters specified, and - * returns a Watchdog_Handle. - * - * @param index Logical peripheral number for the Watchdog indexed - * into the Watchdog_config table - * - * @param params Pointer to an parameter block, if NULL it will use - * default values. All the fields in this structure are - * RO (read-only). - * - * @return A Watchdog_Handle on success or a NULL on an error or if it has - * been opened already. - * - * @sa Watchdog_init() - * @sa Watchdog_close() - */ -extern Watchdog_Handle Watchdog_open(uint_least8_t index, Watchdog_Params *params); - -/*! - * @brief Function to initialize the Watchdog_Params structure to its defaults - * - * @param params An pointer to Watchdog_Params structure for - * initialization - * - * Default parameters: - * callbackFxn = NULL - * resetMode = Watchdog_RESET_ON - * debugStallMode = Watchdog_DEBUG_STALL_ON - */ -extern void Watchdog_Params_init(Watchdog_Params *params); - -/*! - * @brief Sets the Watchdog reload value - * - * Sets the value from which the Watchdog will countdown after it reaches - * zero. This is how the reload value can be changed after the Watchdog has - * already been opened. The new reload value will be loaded into the Watchdog - * timer when this function is called. Watchdog_setReload is not reentrant. - * For CC13XX/CC26XX, if the parameter 'ticks' is set to zero (0), a Watchdog - * interrupt is immediately generated. - * - * This API is not applicable for all platforms. See the page for your - * specific driver implementation for details. - * - * @param handle Watchdog Handle - * - * @param ticks Value to be loaded into Watchdog timer - * Unit is in Watchdog clock ticks - * - * @return Watchdog_STATUS_SUCCESS if successful, Watchdog_STATUS_UNSUPPORTED - * if driver does not support this API. - */ -extern int_fast16_t Watchdog_setReload(Watchdog_Handle handle, uint32_t ticks); - -/*! - * @brief Converts milliseconds to Watchdog clock ticks - * - * Converts the input value into number of Watchdog clock ticks as close as - * possible. If the converted value exceeds 32 bits, a zero (0) will be - * returned to indicate overflow. The converted value can be used as the - * function parameter 'ticks' in Watchdog_setReload(). - * - * This API is not applicable for all platforms. See the page for your - * specific driver implementation for details. - * - * @param handle Watchdog Handle - * - * @param milliseconds Value to be converted - * - * @return Converted value in number of Watchdog clock ticks - * A value of zero (0) means the converted value exceeds 32 bits - * or that the operation is not supported for the specific device. - * - * @sa Watchdog_setReload() - */ -extern uint32_t Watchdog_convertMsToTicks(Watchdog_Handle handle, - uint32_t milliseconds); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_Watchdog__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/adc/ADCCC32XX.c b/ext/hal/ti/simplelink/source/ti/drivers/adc/ADCCC32XX.c deleted file mode 100644 index 3d78b5c66ee..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/adc/ADCCC32XX.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright (c) 2016-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif - -#include - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -/* Pad configuration register defaults */ -#define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) -#define PAD_RESET_DRIVE PIN_STRENGTH_6MA -#define PAD_RESET_TYPE PIN_TYPE_STD -#define PAD_RESET_STATE 0xC61 - -#define PinConfigChannel(config) (((config) >> 8) & 0xff) -#define PinConfigPin(config) ((config) & 0xff) - -void ADCCC32XX_close(ADC_Handle handle); -int_fast16_t ADCCC32XX_control(ADC_Handle handle, uint_fast16_t cmd, void *arg); -int_fast16_t ADCCC32XX_convert(ADC_Handle handle, uint16_t *value); -uint32_t ADCCC32XX_convertToMicroVolts(ADC_Handle handle, - uint16_t adcValue); -void ADCCC32XX_init(ADC_Handle handle); -ADC_Handle ADCCC32XX_open(ADC_Handle handle, ADC_Params *params); - -/* ADC function table for ADCCC32XX implementation */ -const ADC_FxnTable ADCCC32XX_fxnTable = { - ADCCC32XX_close, - ADCCC32XX_control, - ADCCC32XX_convert, - ADCCC32XX_convertToMicroVolts, - ADCCC32XX_init, - ADCCC32XX_open -}; - -/* Internal ADC status structure */ -static ADCCC32XX_State state = { - .baseAddr = ADC_BASE, - .numOpenChannels = 0 -}; - -/* - * ======== ADCCC32XX_close ======== - */ -void ADCCC32XX_close(ADC_Handle handle) -{ - uintptr_t key; - uint32_t pin; - uint32_t padRegister; - ADCCC32XX_Object *object = handle->object; - ADCCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - pin = PinConfigChannel(hwAttrs->adcPin); - - key = HwiP_disable(); - - MAP_ADCChannelDisable(state.baseAddr, pin); - state.numOpenChannels--; - - if (state.numOpenChannels == 0) { - MAP_ADCDisable(state.baseAddr); - } - - HwiP_restore(key); - - /* Call PinConfigSet to de-isolate the input */ - pin = PinConfigPin(hwAttrs->adcPin); - MAP_PinConfigSet(pin, PAD_RESET_DRIVE, PAD_RESET_TYPE); - /* Set reset state for the pad register */ - padRegister = (PinToPadGet(pin)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - - object->isOpen = false; - - DebugP_log0("ADC: (%p) closed"); -} - -/* - * ======== ADCCC32XX_control ======== - */ -int_fast16_t ADCCC32XX_control(ADC_Handle handle, uint_fast16_t cmd, void *arg) -{ - /* No implementation yet */ - return (ADC_STATUS_UNDEFINEDCMD); -} - -/* - * ======== ADCCC32XX_convert ======== - */ -int_fast16_t ADCCC32XX_convert(ADC_Handle handle, uint16_t *value) -{ - uintptr_t key; - uint16_t adcSample = 0; - uint_fast16_t adcChannel; - ADCCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - adcChannel = PinConfigChannel(hwAttrs->adcPin); - key = HwiP_disable(); - - /* Wait until the FIFO is not empty */ - while (MAP_ADCFIFOLvlGet(state.baseAddr, adcChannel) == 0) { - HwiP_restore(key); - key = HwiP_disable(); - } - - adcSample = MAP_ADCFIFORead(ADC_BASE, adcChannel); - - HwiP_restore(key); - - /* Strip time stamp & reserve bits from ADC sample */ - *value = ((adcSample >> 2) & 0x0FFF); - - return (ADC_STATUS_SUCCESS); -} - -/* - * ======== ADCCC32XX_convertToMicroVolts ======== - */ -uint32_t ADCCC32XX_convertToMicroVolts(ADC_Handle handle, - uint16_t adcValue) -{ - /* Internal voltage reference is 1.467V (1467000 uV) */ - return ((uint_fast32_t)(adcValue * (1467000.0 / 4095.0))); -} - -/* - * ======== ADCCC32XX_init ======== - */ -void ADCCC32XX_init(ADC_Handle handle) -{ - /* Mark the object as available */ - ((ADCCC32XX_Object *) handle->object)->isOpen = false; -} - -/* - * ======== ADCCC32XX_open ======== - */ -ADC_Handle ADCCC32XX_open(ADC_Handle handle, ADC_Params *params) -{ - uintptr_t key; - uint32_t pin; - ADCCC32XX_Object *object = handle->object; - ADCCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uint32_t i; - - key = HwiP_disable(); - - if (object->isOpen) { - HwiP_restore(key); - - DebugP_log1("ADC: (%p) already opened", (uintptr_t) handle); - return (NULL); - } - - object->isOpen = true; - state.numOpenChannels++; - - HwiP_restore(key); - - /* Configure pin as ADC input */ - pin = PinConfigPin(hwAttrs->adcPin); - MAP_PinTypeADC(pin, PIN_MODE_255); - - /* Enable ADC Peripheral and ADC Channel */ - pin = PinConfigChannel(hwAttrs->adcPin); - MAP_ADCEnable(state.baseAddr); - MAP_ADCChannelEnable(state.baseAddr, pin); - - /* Empty 5 samples from the FIFO */ - for (i = 0; i < 5; i++) { - while (MAP_ADCFIFOLvlGet(state.baseAddr, pin) == 0){ - } - MAP_ADCFIFORead(state.baseAddr, pin); - } - - DebugP_log1("ADC: (%p) instance opened.", (uintptr_t) handle); - - return (handle); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/adc/ADCCC32XX.h b/ext/hal/ti/simplelink/source/ti/drivers/adc/ADCCC32XX.h deleted file mode 100644 index 0e288e6e253..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/adc/ADCCC32XX.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2016-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file ADCCC32XX.h - * - * @brief ADC driver implementation for the ADC peripheral on CC32XX - * - * This ADC driver implementation is designed to operate on a CC32XX ADC - * peripheral. The ADCCC32XX header file should be included in an application - * as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref ADC.h for a complete description of APIs & example of use. - * - * ============================================================================ - */ -#ifndef ti_drivers_adc_ADCMSP432__include -#define ti_drivers_adc_ADCMSP432__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#include - -/* - * The bits in the pin mode macros are as follows: - * The lower 8 bits of the macro refer to the pin, offset by 1, to match - * driverlib pin defines. - * The upper 16 bits is the value that can be passed to APIs as the - * ulChannel parameter. - */ - -#define ADCCC32XX_PIN_57_CH_0 (ADC_CH_0 << 8) | 0x38 /*!< PIN 57 is used for ADC channel 0 */ -#define ADCCC32XX_PIN_58_CH_1 (ADC_CH_1 << 8) | 0x39 /*!< PIN 58 is used for ADC channel 1 */ -#define ADCCC32XX_PIN_59_CH_2 (ADC_CH_2 << 8) | 0x3a /*!< PIN 59 is used for ADC channel 2 */ -#define ADCCC32XX_PIN_60_CH_3 (ADC_CH_3 << 8) | 0x3b /*!< PIN 60 is used for ADC channel 3 */ - -/* ADC function table pointer */ -extern const ADC_FxnTable ADCCC32XX_fxnTable; - -/*! - * @brief ADCCC32XX Hardware attributes - * - * These fields are used by driverlib APIs and therefore must be populated by - * driverlib macro definitions. For CC32XXWare these definitions are found in: - * - ti/devices/cc32xx/driverlib/adc.h - * - * A sample structure is shown below: - * @code - * const ADCCC32XX_HWAttrsV1 adcCC32XXHWAttrs[Board_ADCCHANNELCOUNT] = { - * { - * .adcPin = ADCCC32XX_PIN_57 - * } - * }; - * @endcode - */ -typedef struct ADCCC32XX_HWAttrsV1 { - uint_fast16_t adcPin; -} ADCCC32XX_HWAttrsV1; - -/*! - * @brief ADCCC32XX_Status - * - * The application must not access any member variables of this structure! - */ -typedef struct ADCCC32XX_State { - uint_fast32_t baseAddr; - uint_least8_t numOpenChannels; -} ADCCC32XX_State; - -/*! - * @brief ADCCC32XX Object - * - * The application must not access any member variables of this structure! - */ -typedef struct ADCCC32XX_Object { - bool isOpen; -} ADCCC32XX_Object; - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_adc_ADCMSP432__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/camera/CameraCC32XXDMA.c b/ext/hal/ti/simplelink/source/ti/drivers/camera/CameraCC32XXDMA.c deleted file mode 100644 index f6f2f2b9c42..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/camera/CameraCC32XXDMA.c +++ /dev/null @@ -1,497 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif -#include -#include -#include - -#include -#include - -#include - -/* driverlib header files */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define CAM_BT_CORRECT_EN 0x00001000 - -/* CameraCC32XXDMA functions */ -void CameraCC32XXDMA_close(Camera_Handle handle); -int_fast16_t CameraCC32XXDMA_control(Camera_Handle handle, - uint_fast16_t cmd, void *arg); -void CameraCC32XXDMA_init(Camera_Handle handle); -Camera_Handle CameraCC32XXDMA_open(Camera_Handle handle, - Camera_Params *params); -int_fast16_t CameraCC32XXDMA_capture(Camera_Handle handle, void *buffer, - size_t bufferlen, size_t *frameLen); - -/* Camera function table for CameraCC32XXDMA implementation */ -const Camera_FxnTable CameraCC32XXDMA_fxnTable = { - CameraCC32XXDMA_close, - CameraCC32XXDMA_control, - CameraCC32XXDMA_init, - CameraCC32XXDMA_open, - CameraCC32XXDMA_capture -}; - -/* - * ======== CameraCC32XXDMA_configDMA ======== - */ -static void CameraCC32XXDMA_configDMA(Camera_Handle handle) -{ - CameraCC32XXDMA_Object *object = handle->object; - CameraCC32XXDMA_HWAttrs const *hwAttrs = handle->hwAttrs; - unsigned long **bufferPtr = (unsigned long**)&object->captureBuf; - - - /* Clear ALT SELECT Attribute */ - MAP_uDMAChannelAttributeDisable(hwAttrs->channelIndex,UDMA_ATTR_ALTSELECT); - - /* Setup ping-pong transfer */ - MAP_uDMAChannelControlSet(hwAttrs->channelIndex, - UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_8); - MAP_uDMAChannelAttributeEnable(hwAttrs->channelIndex,UDMA_ATTR_USEBURST); - MAP_uDMAChannelTransferSet(hwAttrs->channelIndex, UDMA_MODE_PINGPONG, - (void *)CAM_BUFFER_ADDR, (void *)*bufferPtr, - CameraCC32XXDMA_DMA_TRANSFER_SIZE); - - /* Pong Buffer */ - *bufferPtr += CameraCC32XXDMA_DMA_TRANSFER_SIZE; - MAP_uDMAChannelControlSet(hwAttrs->channelIndex | UDMA_ALT_SELECT, - UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_8); - MAP_uDMAChannelAttributeEnable(hwAttrs->channelIndex | UDMA_ALT_SELECT, - UDMA_ATTR_USEBURST); - MAP_uDMAChannelTransferSet(hwAttrs->channelIndex | UDMA_ALT_SELECT, - UDMA_MODE_PINGPONG, - (void *)CAM_BUFFER_ADDR, - (void *)*bufferPtr, - CameraCC32XXDMA_DMA_TRANSFER_SIZE); - MAP_uDMAChannelEnable(hwAttrs->channelIndex | UDMA_ALT_SELECT); - - /* Ping Buffer */ - *bufferPtr += CameraCC32XXDMA_DMA_TRANSFER_SIZE; - - DebugP_log1("Camera:(%p) DMA transfer enabled", hwAttrs->baseAddr); - - /* Set mode to Ping buffer initially */ - object->cameraDMA_PingPongMode = 0; - - /* Clear any pending interrupt */ - MAP_CameraIntClear(hwAttrs->baseAddr, CAM_INT_DMA); - - /* DMA Interrupt unmask from apps config */ - MAP_CameraIntEnable(hwAttrs->baseAddr, CAM_INT_DMA); - - DebugP_log3("Camera:(%p) DMA receive, " - "CaptureBuf: %p; Count: %d", - hwAttrs->baseAddr, - (uintptr_t)*bufferPtr, - (uintptr_t)object->bufferlength); -} - -/* - * ======== captureSemCallback ======== - * Simple callback to post a semaphore for the blocking mode. - */ -static void captureSemCallback(Camera_Handle handle, void *buffer, size_t count) -{ - CameraCC32XXDMA_Object *object = handle->object; - - SemaphoreP_post(object->captureSem); -} - -/* - * ======== CameraCC32XXDMA_hwiIntFxn ======== - * Hwi function that processes Camera interrupts. - * - * The Frame end,DMA interrupts is enabled for the camera. - * The DMA interrupt is triggered for every 64 elements. - * The ISR will check for Frame end interrupt to trigger the callback - * in the non-blocking mode/post a semaphore in the blocking mode to - * indicate capture complete. - * - * @param(arg) The Camera_Handle for this Hwi. - */ -static void CameraCC32XXDMA_hwiIntFxn(uintptr_t arg) -{ - uint32_t status; - CameraCC32XXDMA_Object *object = ((Camera_Handle)arg)->object; - CameraCC32XXDMA_HWAttrs const *hwAttrs = ((Camera_Handle)arg)->hwAttrs; - unsigned long **bufferPtr = (unsigned long**)&object->captureBuf; - - status = MAP_CameraIntStatus(hwAttrs->baseAddr); - if ((object->cameraDMAxIntrRcvd > 1) && (status & (CAM_INT_FE))) { - DebugP_log2("Camera:(%p) Interrupt with mask 0x%x", - hwAttrs->baseAddr,status); - - MAP_CameraIntClear(hwAttrs->baseAddr, CAM_INT_FE); - object->captureCallback((Camera_Handle)arg, *bufferPtr, - object->frameLength); - DebugP_log2("Camera:(%p) capture finished, %d bytes written", - hwAttrs->baseAddr, object->frameLength); - object->inUse = 0; - - MAP_CameraCaptureStop(hwAttrs->baseAddr, true); - - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - } - - if (status & CAM_INT_DMA) { - // Camera DMA Done clear - MAP_CameraIntClear(hwAttrs->baseAddr, CAM_INT_DMA); - - object->cameraDMAxIntrRcvd++; - - object->frameLength += - (CameraCC32XXDMA_DMA_TRANSFER_SIZE*sizeof(unsigned long)); - if (object->frameLength < object->bufferlength) { - if (object->cameraDMA_PingPongMode == 0) { - MAP_uDMAChannelControlSet(hwAttrs->channelIndex, - UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_8); - - MAP_uDMAChannelAttributeEnable(hwAttrs->channelIndex, - UDMA_ATTR_USEBURST); - MAP_uDMAChannelTransferSet(hwAttrs->channelIndex, - UDMA_MODE_PINGPONG, - (void *)CAM_BUFFER_ADDR, - (void *)*bufferPtr, - CameraCC32XXDMA_DMA_TRANSFER_SIZE); - MAP_uDMAChannelEnable(hwAttrs->channelIndex); - *bufferPtr += CameraCC32XXDMA_DMA_TRANSFER_SIZE; - object->cameraDMA_PingPongMode = 1; - } - else { - MAP_uDMAChannelControlSet(hwAttrs->channelIndex | UDMA_ALT_SELECT, - UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_8); - - MAP_uDMAChannelAttributeEnable( - hwAttrs->channelIndex | UDMA_ALT_SELECT, - UDMA_ATTR_USEBURST); - MAP_uDMAChannelTransferSet( - hwAttrs->channelIndex | UDMA_ALT_SELECT, - UDMA_MODE_PINGPONG, - (void *)CAM_BUFFER_ADDR, (void *)*bufferPtr, - CameraCC32XXDMA_DMA_TRANSFER_SIZE); - MAP_uDMAChannelEnable(hwAttrs->channelIndex | UDMA_ALT_SELECT); - *bufferPtr += CameraCC32XXDMA_DMA_TRANSFER_SIZE; - object->cameraDMA_PingPongMode = 0; - } - } - else { - // Disable DMA - ROM_UtilsDelayDirect(40000); - MAP_uDMAChannelDisable(hwAttrs->channelIndex); - MAP_CameraIntDisable(hwAttrs->baseAddr, CAM_INT_DMA); - object->cameraDMA_PingPongMode = 0; - object->captureCallback((Camera_Handle)arg, *bufferPtr, - object->frameLength); - DebugP_log2("Camera:(%p) capture finished, %d bytes written", - hwAttrs->baseAddr, object->frameLength); - - MAP_CameraCaptureStop(hwAttrs->baseAddr, true); - - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - } - } -} - -/* - * ======== CameraCC32XXDMA_init ======== - */ -void CameraCC32XXDMA_init(Camera_Handle handle) -{ - CameraCC32XXDMA_Object *object = handle->object; - - object->opened = false; -} - -/* - * ======== CameraCC32XXDMA_open ======== - */ -Camera_Handle CameraCC32XXDMA_open(Camera_Handle handle, Camera_Params *params) -{ - uintptr_t key; - CameraCC32XXDMA_Object *object = handle->object; - CameraCC32XXDMA_HWAttrs const *hwAttrs = handle->hwAttrs; - unsigned long hSyncPolarityConfig; - unsigned long vSyncPolarityConfig; - unsigned long byteOrderConfig; - unsigned long interfaceSync; - unsigned long pixelClkConfig; - HwiP_Params hwiParams; - SemaphoreP_Params semParams; - - /* Timeouts cannot be 0 */ - DebugP_assert((params->captureTimeout != 0)); - - /* Check that a callback is set */ - DebugP_assert((params->captureMode != Camera_MODE_CALLBACK) || - (params->captureCallback != NULL)); - - /* Disable preemption while checking if the Camera is open. */ - key = HwiP_disable(); - - /* Check if the Camera is open already with the base addr. */ - if (object->opened == true) { - HwiP_restore(key); - - DebugP_log1("Camera:(%p) already in use.", hwAttrs->baseAddr); - return (NULL); - } - - object->opened = true; - HwiP_restore(key); - - object->operationMode = params->captureMode; - object->captureCallback = params->captureCallback; - object->captureTimeout = params->captureTimeout; - - /* Set Camera variables to defaults. */ - object->captureBuf = NULL; - object->bufferlength = 0; - object->frameLength = 0; - object->inUse = 0; - - /* - * Register power dependency. Keeps the clock running in SLP - * and DSLP modes. - */ - Power_setDependency(PowerCC32XX_PERIPH_CAMERA); - Power_setDependency(PowerCC32XX_PERIPH_UDMA); - - /* Disable the Camera interrupt. */ - MAP_CameraIntDisable(hwAttrs->baseAddr, (CAM_INT_FE | CAM_INT_DMA)); - - HwiP_clearInterrupt(hwAttrs->intNum); - - /* Create Hwi object for the Camera peripheral. */ - /* Register the interrupt for this Camera peripheral. */ - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t)handle; - hwiParams.priority = hwAttrs->intPriority; - object->hwiHandle = HwiP_create(hwAttrs->intNum, CameraCC32XXDMA_hwiIntFxn, - &hwiParams); - if (object->hwiHandle == NULL) { - CameraCC32XXDMA_close(handle); - return (NULL); - } - - MAP_IntEnable(INT_CAMERA); - - SemaphoreP_Params_init(&semParams); - semParams.mode = SemaphoreP_Mode_BINARY; - - /* If capture is blocking create a semaphore and set callback. */ - if (object->operationMode == Camera_MODE_BLOCKING) { - object->captureSem = SemaphoreP_create(0, &semParams); - if (object->captureSem == NULL) { - CameraCC32XXDMA_close(handle); - return (NULL); - } - object->captureCallback = &captureSemCallback; - } - - MAP_CameraReset(hwAttrs->baseAddr); - - if (params->hsyncPolarity == Camera_HSYNC_POLARITY_HIGH) { - hSyncPolarityConfig = CAM_HS_POL_HI; - } - else { - hSyncPolarityConfig = CAM_HS_POL_LO; - } - - if (params->vsyncPolarity == Camera_VSYNC_POLARITY_HIGH) { - vSyncPolarityConfig = CAM_VS_POL_HI; - } - else { - vSyncPolarityConfig = CAM_VS_POL_LO; - } - - if (params->byteOrder == Camera_BYTE_ORDER_SWAP) { - byteOrderConfig = CAM_ORDERCAM_SWAP; - } - else { - byteOrderConfig = 0; - } - - if (params->interfaceSync == Camera_INTERFACE_SYNC_OFF) { - interfaceSync = CAM_NOBT_SYNCHRO; - } - else { - interfaceSync = CAM_NOBT_SYNCHRO | CAM_IF_SYNCHRO | CAM_BT_CORRECT_EN; - } - - if (params->pixelClkConfig == Camera_PCLK_CONFIG_RISING_EDGE) { - pixelClkConfig = CAM_PCLK_RISE_EDGE; - } - else { - pixelClkConfig = CAM_PCLK_FALL_EDGE; - } - - MAP_CameraParamsConfig(hwAttrs->baseAddr, hSyncPolarityConfig, - vSyncPolarityConfig, - byteOrderConfig | interfaceSync | pixelClkConfig); - - /*Set the clock divider based on the output clock */ - MAP_CameraXClkConfig(hwAttrs->baseAddr, - MAP_PRCMPeripheralClockGet(PRCM_CAMERA), - params->outputClock); - - /*Setting the FIFO threshold for a DMA request */ - MAP_CameraThresholdSet(hwAttrs->baseAddr, 8); - - MAP_CameraIntEnable(hwAttrs->baseAddr, (CAM_INT_FE | CAM_INT_DMA)); - MAP_CameraDMAEnable(hwAttrs->baseAddr); - - DebugP_log1("Camera:(%p) opened", hwAttrs->baseAddr); - - /* Return the handle */ - return (handle); -} - -/* - * ======== CameraCC32XXDMA_close ======== - */ -void CameraCC32XXDMA_close(Camera_Handle handle) -{ - CameraCC32XXDMA_Object *object = handle->object; - CameraCC32XXDMA_HWAttrs const *hwAttrs = handle->hwAttrs; - - /* Disable Camera and interrupts. */ - MAP_CameraIntDisable(hwAttrs->baseAddr,CAM_INT_FE); - MAP_CameraDMADisable(hwAttrs->baseAddr); - - if (object->hwiHandle) { - HwiP_delete(object->hwiHandle); - } - if (object->captureSem) { - SemaphoreP_delete(object->captureSem); - } - - Power_releaseDependency(PowerCC32XX_PERIPH_CAMERA); - Power_releaseDependency(PowerCC32XX_PERIPH_UDMA); - - object->opened = false; - - DebugP_log1("Camera:(%p) closed", hwAttrs->baseAddr); -} - -/* - * ======== CameraCC32XXDMA_control ======== - * @pre Function assumes that the handle is not NULL - */ -int_fast16_t CameraCC32XXDMA_control(Camera_Handle handle, uint_fast16_t cmd, - void *arg) -{ - /* No implementation yet */ - return (CAMERA_STATUS_UNDEFINEDCMD); -} - -/* - * ======== CameraCC32XXDMA_capture ======== - */ - -int_fast16_t CameraCC32XXDMA_capture(Camera_Handle handle, void *buffer, - size_t bufferlen, size_t *frameLen) -{ - CameraCC32XXDMA_Object *object = handle->object; - CameraCC32XXDMA_HWAttrs const *hwAttrs = handle->hwAttrs; - uintptr_t key; - - key = HwiP_disable(); - if (object->inUse) { - HwiP_restore(key); - DebugP_log1("Camera:(%p) Could not capture data, camera in use.", - ((CameraCC32XXDMA_HWAttrs const *) - (handle->hwAttrs))->baseAddr); - - return (CAMERA_STATUS_ERROR); - } - - object->captureBuf = buffer; - object->bufferlength = bufferlen; - object->frameLength = 0; - object->cameraDMAxIntrRcvd = 0; - object->inUse = 1; - object->cameraDMA_PingPongMode = 0; - - HwiP_restore(key); - - /* Set constraints to guarantee transaction */ - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* Start the DMA transfer */ - CameraCC32XXDMA_configDMA(handle); - MAP_CameraCaptureStart(hwAttrs->baseAddr); - - /* If operationMode is blocking, block and get the status. */ - if (object->operationMode == Camera_MODE_BLOCKING) { - /* Pend on semaphore and wait for Hwi to finish. */ - if (SemaphoreP_OK == SemaphoreP_pend(object->captureSem, - object->captureTimeout)) { - - DebugP_log2("Camera:(%p) Capture timed out, %d bytes captured", - ((CameraCC32XXDMA_HWAttrs const *) - (handle->hwAttrs))->baseAddr, - object->frameLength); - } - else { - MAP_CameraCaptureStop(hwAttrs->baseAddr, true); - *frameLen = object->frameLength; - return (CAMERA_STATUS_SUCCESS); - } - } - - *frameLen = 0; - return (CAMERA_STATUS_SUCCESS); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/camera/CameraCC32XXDMA.h b/ext/hal/ti/simplelink/source/ti/drivers/camera/CameraCC32XXDMA.h deleted file mode 100644 index 78a15412033..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/camera/CameraCC32XXDMA.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file CameraCC32XXDMA.h - * - * @brief Camera driver implementation for a CC32XX Camera controller - * - * The Camera header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref Camera.h for a complete description of APIs & example of use. - * - * ============================================================================ - */ - -#ifndef ti_drivers_Camera_CameraCC32XXDMA__include -#define ti_drivers_Camera_CameraCC32XXDMA__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include -#include - -/** - * @addtogroup Camera_STATUS - * CameraCC32XXDMA_STATUS_* macros are command codes only defined in the - * CameraCC32XXDMA.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add CameraCC32XXDMA_STATUS_* macros here */ - -/** @}*/ - -/** - * @addtogroup Camera_CMD - * CameraCC32XXDMA_CMD_* macros are command codes only defined in the - * CameraCC32XXDMA.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add CameraCC32XXDMA_CMD_* macros here */ - -/** @}*/ - -/* CC32XX camera DMA transfer size */ -#define CameraCC32XXDMA_DMA_TRANSFER_SIZE 64 - -/* Camera function table pointer */ -extern const Camera_FxnTable CameraCC32XXDMA_fxnTable; - -/*! - * @brief CameraCC32XXDMA Hardware attributes - * - * These fields, with the exception of intPriority, - * are used by driverlib APIs and therefore must be populated by - * driverlib macro definitions. For CC32XXWare these definitions are found in: - * - inc/hw_memmap.h - * - inc/hw_ints.h - * - * intPriority is the Camera peripheral's interrupt priority, as defined by the - * underlying OS. It is passed unmodified to the underlying OS's interrupt - * handler creation code, so you need to refer to the OS documentation - * for usage. If the driver uses the ti.dpl interface - * instead of making OS calls directly, then the HwiP port handles the - * interrupt priority in an OS specific way. In the case of the SYS/BIOS - * port, intPriority is passed unmodified to Hwi_create(). - * - * A sample structure is shown below: - * @code - * const CameraCC32XXDMA_HWAttrs CameraCC32XXDMAHWAttrs[] = { - * { - * .baseAddr = CAMERA_BASE, - * .intNum = INT_CAMERA, - * .intPriority = (~0), - * .channelIndex = UDMA_CH22_CAMERA - * } - * }; - * @endcode - */ -typedef struct CameraCC32XXDMA_HWAttrs { - /*! Camera Peripheral's base address */ - uint32_t baseAddr; - /*! Camera Peripheral's interrupt vector */ - uint32_t intNum; - /*! Camera Peripheral's interrupt priority */ - uint32_t intPriority; - /*! uDMA controlTable channel index */ - unsigned long channelIndex; -} CameraCC32XXDMA_HWAttrs; - -/*! - * @brief CameraCC32XXDMA Object - * - * The application must not access any member variables of this structure! - */ -typedef struct CameraCC32XXDMA_Object { - /* Camera control variables */ - bool opened; /* Has the obj been opened */ - Camera_CaptureMode operationMode; /* Mode of operation of Camera */ - - /* Camera capture variables */ - Camera_Callback captureCallback; /* Pointer to capture callback */ - uint32_t captureTimeout; /* Timeout for capture semaphore */ - void *captureBuf; /* Buffer data pointer */ - size_t bufferlength; /* Input Buffer length*/ - size_t frameLength; /* Captured frame length */ - - bool cameraDMA_PingPongMode; /* DMA ping pong mode */ - size_t cameraDMAxIntrRcvd; /* Number of DMA interrupts*/ - bool inUse; /* Camera in Use */ - - /* Camera OS objects */ - SemaphoreP_Handle captureSem; - HwiP_Handle hwiHandle; -} CameraCC32XXDMA_Object, *CameraCC32XXDMA_Handle; - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_Camera_CameraCC32XXDMA__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/capture/CaptureCC32XX.c b/ext/hal/ti/simplelink/source/ti/drivers/capture/CaptureCC32XX.c deleted file mode 100644 index 4128a63e20d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/capture/CaptureCC32XX.c +++ /dev/null @@ -1,435 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define getTimerBaseAddress(config) (TIMERA0_BASE | ((config >> 18) & 0x3000)) -#define getSubTimer(config) ((config >> 28) & 0x3) -#define getTimerIntNum(config) ((config >> 20) & 0xFF) -#define getPadOffset(config) ((config >> 4) & 0xFFF) -#define getPinMode(config) (config & 0xF) -#define getGPIOBaseAddress(config) (GPIOA0_BASE + ((config >> 4) & 0xF000)) - -#define PAD_RESET_STATE 0xC61 - -void CaptureCC32XX_close(Capture_Handle handle); -int_fast16_t CaptureCC32XX_control(Capture_Handle handle, - uint_fast16_t cmd, void *arg); -void CaptureCC32XX_init(Capture_Handle handle); -Capture_Handle CaptureCC32XX_open(Capture_Handle handle, Capture_Params *params); -int32_t CaptureCC32XX_start(Capture_Handle handle); -void CaptureCC32XX_stop(Capture_Handle handle); - -/* Internal static Functions */ -static void CaptureCC32XX_hwiIntFunction(uintptr_t arg); -static uint32_t getPowerMgrId(uint32_t baseAddress); -static void initHw(Capture_Handle handle); -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg); - -/* System Clock Frequency */ -static ClockP_FreqHz clockFreq; - -/* Function table for CaptureCC32XX implementation */ -const Capture_FxnTable CaptureCC32XX_fxnTable = { - .closeFxn = CaptureCC32XX_close, - .openFxn = CaptureCC32XX_open, - .startFxn = CaptureCC32XX_start, - .stopFxn = CaptureCC32XX_stop, - .initFxn = CaptureCC32XX_init, - .controlFxn = CaptureCC32XX_control -}; - -/* - * ======== CaptureCC32XX_close ======== - */ -void CaptureCC32XX_close(Capture_Handle handle) -{ - CaptureCC32XX_Object *object = handle->object; - CaptureCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - TimerCC32XX_SubTimer subTimer; - uint32_t baseAddress = getTimerBaseAddress(hwAttrs->capturePin); - - subTimer = (TimerCC32XX_SubTimer) getSubTimer(hwAttrs->capturePin); - - CaptureCC32XX_stop(handle); - - Power_unregisterNotify(&(object->notifyObj)); - Power_releaseDependency(getPowerMgrId(getGPIOBaseAddress(hwAttrs->capturePin))); - - if (object->hwiHandle) { - - HwiP_delete(object->hwiHandle); - object->hwiHandle = NULL; - } - - TimerCC32XX_freeTimerResource(baseAddress, subTimer); - - /* Restore the GPIO pad to its reset state */ - HWREG(OCP_SHARED_BASE + getPadOffset(hwAttrs->capturePin)) - = PAD_RESET_STATE; -} - -/* - * ======== CaptureCC32XX_control ======== - */ -int_fast16_t CaptureCC32XX_control(Capture_Handle handle, - uint_fast16_t cmd, void *arg) -{ - return (Capture_STATUS_UNDEFINEDCMD); -} - -/* - * ======== CaptureCC32XX_hwiIntFunction ======== - */ -void CaptureCC32XX_hwiIntFunction(uintptr_t arg) -{ - Capture_Handle handle = (Capture_Handle) arg; - CaptureCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - CaptureCC32XX_Object *object = handle->object; - uint32_t baseAddress = getTimerBaseAddress(hwAttrs->capturePin); - uint32_t interruptMask; - uint32_t interval, currentCount; - - /* Read the TXR register */ - currentCount = TimerValueGet(baseAddress, object->timer); - - /* Calculate the interval */ - if (currentCount < object->previousCount) { - - /* Calculate the difference if the timer rolled over */ - interval = currentCount + (0xFFFFFF - object->previousCount); - } - else if (currentCount > object->previousCount) { - - interval = currentCount - object->previousCount - 1; - } - else { - interval = 1; - } - - /* Store the interval for the next interrupt */ - object->previousCount = currentCount; - - /* Compensate for prescale register roll-over hardware issue */ - interval = interval - (interval / 0xFFFF); - - /* Clear the interrupts used by this driver instance */ - interruptMask = object->timer & (TIMER_CAPB_EVENT | TIMER_CAPA_EVENT); - TimerIntClear(baseAddress, interruptMask); - - /* Need to convert the interval to periodUnits if microseconds or hertz */ - if (object->periodUnits == Capture_PERIOD_US) { - - interval = interval / (clockFreq.lo / 1000000); - } - else if (object->periodUnits == Capture_PERIOD_HZ) { - - interval = clockFreq.lo / interval; - } - - /* Call the user callbackFxn */ - object->callBack(handle, interval); -} - -/* - * ======== CaptureCC32XX_init ======== - */ -void CaptureCC32XX_init(Capture_Handle handle) -{ - return; -} - -/* - * ======== CaptureCC32XX_open ======== - */ -Capture_Handle CaptureCC32XX_open(Capture_Handle handle, Capture_Params *params) -{ - CaptureCC32XX_Object *object = handle->object; - CaptureCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - HwiP_Params hwiParams; - uint32_t powerId; - - /* Check parameters. This driver requires a callback function. */ - if (params == NULL || - params->callbackFxn == NULL) { - - return (NULL); - } - - powerId = getPowerMgrId(getGPIOBaseAddress(hwAttrs->capturePin)); - - if (powerId == (uint32_t) -1) { - - return (NULL); - } - - /* Attempt to allocate timer hardware resource */ - if (!TimerCC32XX_allocateTimerResource(getTimerBaseAddress(hwAttrs->capturePin), - (TimerCC32XX_SubTimer) getSubTimer(hwAttrs->capturePin))) { - - return (NULL); - } - - /* Turn on Power to the GPIO */ - Power_setDependency(powerId); - - /* Function to re-initialize the timer after a low-power event */ - Power_registerNotify(&(object->notifyObj), PowerCC32XX_AWAKE_LPDS, - postNotifyFxn, (uintptr_t) handle); - - /* Determine which timer half will be used. */ - if (getSubTimer(hwAttrs->capturePin) == TimerCC32XX_timer16A) { - - object->timer = TIMER_A; - } - else { - - object->timer = TIMER_B; - } - - /* Set the mode */ - if (params->mode == Capture_RISING_EDGE) { - - object->mode = TIMER_EVENT_POS_EDGE; - } - else if (params->mode == Capture_FALLING_EDGE) { - - object->mode = TIMER_EVENT_NEG_EDGE; - } - else { - - object->mode = TIMER_EVENT_BOTH_EDGES; - } - - object->isRunning = false; - object->callBack = params->callbackFxn; - object->periodUnits = params->periodUnit; - - /* Setup the hardware interrupt function to handle timer interrupts */ - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t) handle; - hwiParams.priority = hwAttrs->intPriority; - - object->hwiHandle = HwiP_create(getTimerIntNum(hwAttrs->capturePin), - CaptureCC32XX_hwiIntFunction, &hwiParams); - - if (object->hwiHandle == NULL) { - - CaptureCC32XX_close(handle); - - return (NULL); - } - - /* Static global storing the CPU frequency */ - ClockP_getCpuFreq(&clockFreq); - - /* Initialize the timer hardware */ - initHw(handle); - - return (handle); -} - -/* - * ======== CaptureCC32XX_start ======== - */ -int32_t CaptureCC32XX_start(Capture_Handle handle) -{ - CaptureCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - CaptureCC32XX_Object *object = handle->object; - uint32_t baseAddress = getTimerBaseAddress(hwAttrs->capturePin); - uint32_t interruptMask; - uintptr_t key; - - interruptMask = object->timer & (TIMER_CAPB_EVENT | TIMER_CAPA_EVENT); - - key = HwiP_disable(); - - if (object->isRunning) { - - HwiP_restore(key); - - return (Capture_STATUS_ERROR); - } - - object->isRunning = true; - object->previousCount = 0; - - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - - TimerIntClear(baseAddress, interruptMask); - TimerIntEnable(baseAddress, interruptMask); - TimerValueSet(baseAddress, object->timer, 0); - TimerEnable(baseAddress, object->timer); - - HwiP_restore(key); - - return (Capture_STATUS_SUCCESS); -} - -/* - * ======== CaptureCC32XX_stop ======== - */ -void CaptureCC32XX_stop(Capture_Handle handle) -{ - CaptureCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - CaptureCC32XX_Object *object = handle->object; - uint32_t baseAddress = getTimerBaseAddress(hwAttrs->capturePin); - uint32_t interruptMask; - uintptr_t key; - - interruptMask = object->timer & (TIMER_CAPB_EVENT | TIMER_CAPA_EVENT); - - key = HwiP_disable(); - - if (object->isRunning) { - - object->isRunning = false; - - TimerDisable(baseAddress, object->timer); - TimerIntDisable(baseAddress, interruptMask); - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - } - - HwiP_restore(key); -} - - -/* - * ======== getPowerMgrId ======== - */ -static uint32_t getPowerMgrId(uint32_t baseAddress) -{ - switch (baseAddress) { - - case GPIOA0_BASE: - - return (PowerCC32XX_PERIPH_GPIOA0); - - case GPIOA1_BASE: - - return (PowerCC32XX_PERIPH_GPIOA1); - - case GPIOA2_BASE: - - return (PowerCC32XX_PERIPH_GPIOA2); - - case GPIOA3_BASE: - - return (PowerCC32XX_PERIPH_GPIOA3); - - case GPIOA4_BASE: - - return (PowerCC32XX_PERIPH_GPIOA4); - - default: - - return ((uint32_t) -1); - } -} - -/* - * ======== initHw ======== - */ -static void initHw(Capture_Handle handle) -{ - CaptureCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - CaptureCC32XX_Object const *object = handle->object; - uint32_t baseAddress = getTimerBaseAddress(hwAttrs->capturePin); - uintptr_t key; - - /* Enable external GPT trigger */ - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_GPT_TRIG_SEL) = 0xFF; - - /* Route the GPIO pad for capture usage */ - HWREG(OCP_SHARED_BASE + getPadOffset(hwAttrs->capturePin)) - = getPinMode(hwAttrs->capturePin); - - /* Read/Write modifications for shared registers */ - key = HwiP_disable(); - - /* Disable the timer */ - TimerDisable(baseAddress, object->timer); - - /* Set trigger event for the capture pin */ - TimerControlEvent(baseAddress, object->timer, object->mode); - - /* This function controls the stall response for the timer. When true, - * the timer stops counting if the processor is halted. The - * default setting for the hardware is false. - */ - TimerControlStall(baseAddress, object->timer, true); - - HwiP_restore(key); - - /* Configure in 16-bit mode */ - HWREG(baseAddress + TIMER_O_CFG) = TIMER_CFG_16_BIT; - - /* Configure in capture time edge mode, counting up */ - if (object->timer == TIMER_A) { - - HWREG(baseAddress + TIMER_O_TAMR) = TIMER_CFG_A_CAP_TIME_UP; - } - else { - - HWREG(baseAddress + TIMER_O_TBMR) = TIMER_CFG_A_CAP_TIME_UP; - } -} - -/* - * ======== postNotifyFxn ======== - * This function is called when a transition from LPDS mode is made. - * clientArg should be a handle of a previously opened Timer instance. - */ -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - initHw((Capture_Handle) clientArg); - - return (Power_NOTIFYDONE); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/capture/CaptureCC32XX.h b/ext/hal/ti/simplelink/source/ti/drivers/capture/CaptureCC32XX.h deleted file mode 100644 index 7f88ca140cb..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/capture/CaptureCC32XX.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file CaptureCC32XX.h - * @brief Capture driver interface for CC32XX devices - * - * # Operation # - * This driver uses a general purpose timer hardware peripheral to implement - * the capture functionality. The capture driver only uses half of a timer - * peripheral (16-bit timer). This is not a software limitation but due to the - * general purpose timer hardware implementation. For CC32XX devices, the - * system clock is 80 MHz. A 16-bit timer peripheral has 24-bits of - * resolution when the prescaler register is used as an 8-bit linear extension. - * - * # Resource Allocation # - * Each general purpose timer block contains two timers, Timer A and Timer B, - * that can be configured to operate independently. This behavior is managed - * through a set of resource allocation APIs. For example, the - * TimerCC32XX_allocateTimerResource API will allocate a timer for exclusive - * use. Any attempt to re-allocate this resource by the TimerCC32XX, PWMCC32XX, - * or CaptureCC32xx drivers will result in a false value being returned from - * the allocation API. To free a timer resource, the - * TimerCC32XX_freeTimerResource is used. The application is not responsible - * for calling these allocation APIs directly. - * - ******************************************************************************* - */ -#ifndef ti_drivers_capture_CaptureCC32XX__include -#define ti_drivers_capture_CaptureCC32XX__include - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#include -#include -#include -#include -#include - -/*! \cond */ -/* - * Capture port/pin defines for pin configuration. - * - * The timer id (0, 1, 2, or 3) is stored in bits 31 - 30 - * The timer half (1 = A, 2 = B) is stored in bits 29 - 28 - * The interrupt number is stored in bits 27 - 20 - * The GPIO port (0, 1, 2, or 3) is stored in bits 19 - 16 - * The GPIO pad offset is stored in bits 15 - 4 - * The pin mode is stored in bits 3 - 0 - * - * 31 - 30 29 - 28 27 - 20 19 - 16 15 - 4 3 - 0 - * -------------------------------------------------------------------------- - * | TimerId | Timer half | IntNum | GPIO Port | GPIO Pad Offset | Pin Mode | - * -------------------------------------------------------------------------- - * - * The CC32XX has fixed GPIO assignments and pin modes for a given pin. - * A Capture pin mode for a given pin has a fixed timer/timer-half. - */ -#define CaptureCC32XX_T0A (0x10000000 | (INT_TIMERA0A << 20)) -#define CaptureCC32XX_T0B (0x20000000 | (INT_TIMERA0B << 20)) -#define CaptureCC32XX_T1A (0x50000000 | (INT_TIMERA1A << 20)) -#define CaptureCC32XX_T1B (0x60000000 | (INT_TIMERA1B << 20)) -#define CaptureCC32XX_T2A (0x90000000 | (INT_TIMERA2A << 20)) -#define CaptureCC32XX_T2B (0xA0000000 | (INT_TIMERA2B << 20)) -#define CaptureCC32XX_T3A (0xD0000000 | (INT_TIMERA3A << 20)) -#define CaptureCC32XX_T3B (0xE0000000 | (INT_TIMERA3B << 20)) - -#define CaptureCC32XX_GPIO0 (0x00000000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_0 << 4)) -#define CaptureCC32XX_GPIO1 (0x00000000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_1 << 4)) -#define CaptureCC32XX_GPIO2 (0x00000000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_2 << 4)) -#define CaptureCC32XX_GPIO5 (0x00000000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_5 << 4)) -#define CaptureCC32XX_GPIO6 (0x00000000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_6 << 4)) -#define CaptureCC32XX_GPIO8 (0x00010000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_8 << 4)) -#define CaptureCC32XX_GPIO9 (0x00010000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_9 << 4)) -#define CaptureCC32XX_GPIO10 (0x00010000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_10 << 4)) -#define CaptureCC32XX_GPIO11 (0x00010000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_11 << 4)) -#define CaptureCC32XX_GPIO12 (0x00010000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_12 << 4)) -#define CaptureCC32XX_GPIO13 (0x00010000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_13 << 4)) -#define CaptureCC32XX_GPIO14 (0x00010000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_14 << 4)) -#define CaptureCC32XX_GPIO15 (0x00010000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_15 << 4)) -#define CaptureCC32XX_GPIO16 (0x00020000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_16 << 4)) -#define CaptureCC32XX_GPIO22 (0x00020000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_22 << 4)) -#define CaptureCC32XX_GPIO24 (0x00030000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_24 << 4)) -#define CaptureCC32XX_GPIO30 (0x00030000 | (OCP_SHARED_O_GPIO_PAD_CONFIG_30 << 4)) -/*! \endcond */ - -/*! - * \defgroup capturePinIdentifiersCC32XX CaptureCC32XX_HWAttrs 'capturePin' - * field options. - * @{ - */ -/*! - * @name PIN 01, GPIO10, uses Timer0B for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_01 CaptureCC32XX_T0B | CaptureCC32XX_GPIO10 | 0xC /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 02, GPIO11, uses Timer1A for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_02 CaptureCC32XX_T1A | CaptureCC32XX_GPIO11 | 0xC /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 03, GPIO12, uses Timer1B for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_03 CaptureCC32XX_T1B | CaptureCC32XX_GPIO12 | 0xC /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 04, GPIO13, uses Timer2A for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_04 CaptureCC32XX_T2A | CaptureCC32XX_GPIO13 | 0xC /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 05, GPIO14, uses Timer2B for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_05 CaptureCC32XX_T2B | CaptureCC32XX_GPIO14 | 0xC /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 06, GPIO15, uses Timer3A for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_06 CaptureCC32XX_T3A | CaptureCC32XX_GPIO15 | 0xD /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 07, GPIO16, uses Timer3B for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_07 CaptureCC32XX_T3B | CaptureCC32XX_GPIO16 | 0xD /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 15, GPIO22, uses Timer2A for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_15 CaptureCC32XX_T2A | CaptureCC32XX_GPIO22 | 0x5 /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 17, GPIO24 (TDO), uses Timer3A for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_17 CaptureCC32XX_T3A | CaptureCC32XX_GPIO24 | 0x4 /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 50, GPIO0, uses Timer0A for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_50 CaptureCC32XX_T0A | CaptureCC32XX_GPIO0 | 0x7 /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 53, GPIO30, uses Timer2B for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_53 CaptureCC32XX_T2B | CaptureCC32XX_GPIO30 | 0x4 /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 55, GPIO1, uses Timer0B for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_55 CaptureCC32XX_T0B | CaptureCC32XX_GPIO1 | 0x7 /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 57, GPIO2, uses Timer1A for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_57 CaptureCC32XX_T1A | CaptureCC32XX_GPIO2 | 0x7 /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 60, GPIO5, uses Timer2B for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_60 CaptureCC32XX_T2B | CaptureCC32XX_GPIO5 | 0x7 /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 61, GPIO6, uses Timer3A for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_61 CaptureCC32XX_T3A | CaptureCC32XX_GPIO6 | 0x7 /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 63, GPIO8, uses Timer3A for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_63 CaptureCC32XX_T3A | CaptureCC32XX_GPIO8 | 0xC /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 64, GPIO9, uses Timer0A for Capture. - * @{ - */ -#define CaptureCC32XX_PIN_64 CaptureCC32XX_T0A | CaptureCC32XX_GPIO9 | 0xC /*!< @hideinitializer */ -/*! @} */ -/*! @} */ - -extern const Capture_FxnTable CaptureCC32XX_fxnTable; - -/*! - * @brief CaptureCC32XX Hardware Attributes - * - * Timer hardware attributes that tell the CaptureCC32XX driver specific hardware - * configurations and interrupt/priority settings. - * - * A sample structure is shown below: - * @code - * const CaptureCC32XX_HWAttrs captureCC32XXHWAttrs[] = - * { - * { - * .capturePin = CaptureCC32XX_PIN_04, - * .intPriority = ~0 - * }, - * { - * .capturePin = CaptureCC32XX_PIN_05, - * .intPriority = ~0 - * }, - * }; - * @endcode - */ -typedef struct CaptureCC32XX_HWAttrs_ { - /*! Specifies the input pin for the capture event. There are 17 - pins available as inputs for capture functionality. Each - available pin must map to a specific general purpose timer - hardware instance. By specifying this attribute, a fixed - 16-bit timer peripheral is used. */ - uint32_t capturePin; - - /*! The interrupt priority. */ - uint32_t intPriority; -} CaptureCC32XX_HWAttrs; - -/*! - * @brief CaptureCC32XX_Object - * - * The application must not access any member variables of this structure! - */ -typedef struct CaptureCC32XX_Object_ { - HwiP_Handle hwiHandle; - Power_NotifyObj notifyObj; - Capture_CallBackFxn callBack; - Capture_PeriodUnits periodUnits; - uint32_t mode; - uint32_t timer; - uint32_t previousCount; - bool isRunning; -} CaptureCC32XX_Object; - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_capture_CaptureCC32XX__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/crypto/CryptoCC32XX.c b/ext/hal/ti/simplelink/source/ti/drivers/crypto/CryptoCC32XX.c deleted file mode 100644 index 405ec40d6f4..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/crypto/CryptoCC32XX.c +++ /dev/null @@ -1,889 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include - -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif - -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -#define CryptoCC32XX_SHAMD5_SIGNATURE_LEN_MD5 16 -#define CryptoCC32XX_SHAMD5_SIGNATURE_LEN_SHA1 20 -#define CryptoCC32XX_SHAMD5_SIGNATURE_LEN_SHA224 28 -#define CryptoCC32XX_SHAMD5_SIGNATURE_LEN_SHA256 32 - -#define CryptoCC32XX_CONTEXT_READY_MAX_COUNTER 1000 - -#define CryptoCC32XX_SHAMD5GetSignatureSize(_mode) ((_mode == SHAMD5_ALGO_MD5) ? CryptoCC32XX_SHAMD5_SIGNATURE_LEN_MD5: \ - (_mode == SHAMD5_ALGO_SHA1) ? CryptoCC32XX_SHAMD5_SIGNATURE_LEN_SHA1: \ - (_mode == SHAMD5_ALGO_SHA224) ? CryptoCC32XX_SHAMD5_SIGNATURE_LEN_SHA224: \ - (_mode == SHAMD5_ALGO_SHA256) ? CryptoCC32XX_SHAMD5_SIGNATURE_LEN_SHA256:0) - -#define SHAMD5_SIGNATURE_MAX_LEN CryptoCC32XX_SHAMD5_SIGNATURE_LEN_SHA256 -typedef int8_t CryptoCC32XX_SHAMD5Signature[SHAMD5_SIGNATURE_MAX_LEN]; - -typedef struct CryptoCC32XX_HwiP { - /*! Crypto Peripheral's interrupt handler */ - HwiP_Fxn hwiIntFxn; - /*! Crypto Peripheral's interrupt vector */ - uint32_t intNum; - /*! Crypto Peripheral's interrupt priority */ - uint32_t intPriority; -} CryptoCC32XX_HwiP; - -/* Prototypes */ -int32_t CryptoCC32XX_aesProcess(uint32_t cryptoMode , uint32_t cryptoDirection, uint8_t* pInBuff, uint16_t inLen, uint8_t* pOutBuff , CryptoCC32XX_EncryptParams* pParams); -int32_t CryptoCC32XX_desProcess(uint32_t cryptoMode , uint32_t cryptoDirection, uint8_t* pInBuff, uint16_t inLen, uint8_t* pOutBuff , CryptoCC32XX_EncryptParams* pParams); -int32_t CryptoCC32XX_shamd5Process(uint32_t cryptoMode , uint8_t* pBuff, uint32_t len, uint8_t *pSignature, CryptoCC32XX_HmacParams* pParams); -void CryptoCC32XX_aesIntHandler(void); -void CryptoCC32XX_desIntHandler(void); -void CryptoCC32XX_shamd5IntHandler(void); -HwiP_Handle CryptoCC32XX_register(CryptoCC32XX_Handle handle, CryptoCC32XX_HwiP *hwiP); -void CryptoCC32XX_unregister(HwiP_Handle handle); - - -/* Crypto CC32XX interrupts implementation */ -CryptoCC32XX_HwiP CryptoCC32XX_HwiPTable[] = { - { (HwiP_Fxn)CryptoCC32XX_aesIntHandler, INT_AES, (~0) }, /* AES */ - { (HwiP_Fxn)CryptoCC32XX_desIntHandler, INT_DES, (~0) }, /* DES */ - { (HwiP_Fxn)CryptoCC32XX_shamd5IntHandler, INT_SHA, (~0) } /* SHAMD5 */ -}; - -/* Crypto AES key size to Crypto CC32XX AES key size */ -#define CryptoCC32XX_getAesKeySize(_keySize) ( \ - (_keySize == CryptoCC32XX_AES_KEY_SIZE_128BIT)? AES_CFG_KEY_SIZE_128BIT: \ - (_keySize == CryptoCC32XX_AES_KEY_SIZE_192BIT)? AES_CFG_KEY_SIZE_192BIT: \ - (_keySize == CryptoCC32XX_AES_KEY_SIZE_256BIT)? AES_CFG_KEY_SIZE_256BIT: \ - CryptoCC32XX_STATUS_ERROR_NOT_SUPPORTED) - -/* Crypto DES key size to Crypto CC32XX DES key size */ -#define CryptoCC32XX_getDesKeySize(_keySize) ( \ - (_keySize == CryptoCC32XX_DES_KEY_SIZE_SINGLE)? DES_CFG_SINGLE: \ - (_keySize == CryptoCC32XX_DES_KEY_SIZE_TRIPLE)? DES_CFG_TRIPLE: \ - CryptoCC32XX_STATUS_ERROR_NOT_SUPPORTED) - -/* Crypto method to Crypto CC32XX mode */ -#define CryptoCC32XX_getMode(_method) ( \ - (_method == CryptoCC32XX_AES_ECB)? AES_CFG_MODE_ECB: \ - (_method == CryptoCC32XX_AES_CBC)? AES_CFG_MODE_CBC: \ - (_method == CryptoCC32XX_AES_CTR)? AES_CFG_MODE_CTR: \ - (_method == CryptoCC32XX_AES_ICM)? AES_CFG_MODE_ICM: \ - (_method == CryptoCC32XX_AES_CFB)? AES_CFG_MODE_CFB: \ - (_method == CryptoCC32XX_AES_GCM)? AES_CFG_MODE_GCM_HY0CALC: \ - (_method == CryptoCC32XX_AES_CCM)? AES_CFG_MODE_CCM: \ - (_method == CryptoCC32XX_DES_ECB)? DES_CFG_MODE_ECB: \ - (_method == CryptoCC32XX_DES_CBC)? DES_CFG_MODE_CBC: \ - (_method == CryptoCC32XX_DES_CFB)? DES_CFG_MODE_CFB: \ - (_method == CryptoCC32XX_HMAC_MD5)? SHAMD5_ALGO_MD5: \ - (_method == CryptoCC32XX_HMAC_SHA1)? SHAMD5_ALGO_SHA1: \ - (_method == CryptoCC32XX_HMAC_SHA224)? SHAMD5_ALGO_SHA224: \ - (_method == CryptoCC32XX_HMAC_SHA256)? SHAMD5_ALGO_SHA256: \ - CryptoCC32XX_STATUS_ERROR_NOT_SUPPORTED) - - -/* global variables for the interrupt handles */ -static volatile bool g_bAESReadyFlag; -static volatile bool g_bDESReadyFlag; -static volatile bool g_bSHAMD5ReadyFlag; - -/* Externs */ -extern const CryptoCC32XX_Config CryptoCC32XX_config[]; -extern const uint8_t CryptoCC32XX_count; - - -/* - * ======== CryptoCC32XX_close ======== - */ -void CryptoCC32XX_close(CryptoCC32XX_Handle handle) -{ - uintptr_t key; - CryptoCC32XX_Object *object = handle->object; - int32_t type; - - /* Mask Crypto interrupts */ - - - /* Power off the Crypto module */ - Power_releaseDependency(PowerCC32XX_PERIPH_DTHE); - - for (type = 0; type < CryptoCC32XX_MAX_TYPES;type++) - { - if (object->sem[type] != NULL) - { - SemaphoreP_delete(object->sem[type]); - } - if (object->hwiHandle[type] != NULL) - { - CryptoCC32XX_unregister(object->hwiHandle[type]); - } - } - - /* Mark the module as available */ - key = HwiP_disable(); - - object->isOpen = false; - - HwiP_restore(key); - - return; -} - - -/* - * ======== CryptoCC32XX_init ======== - */ -void CryptoCC32XX_init(void) -{ -} - -/* - * ======== CryptoCC32XX_open ======== - */ -CryptoCC32XX_Handle CryptoCC32XX_open(uint32_t index, uint32_t types) -{ - CryptoCC32XX_Handle handle; - uintptr_t key; - CryptoCC32XX_Object *object; - SemaphoreP_Params semParams; - int32_t type; - - - if (index >= CryptoCC32XX_count) - { - return (NULL); - } - - /* Get handle for this driver instance */ - handle = (CryptoCC32XX_Handle)&(CryptoCC32XX_config[index]); - object = handle->object; - - /* Determine if the device index was already opened */ - key = HwiP_disable(); - if(object->isOpen == true) - { - HwiP_restore(key); - return (NULL); - } - - /* Mark the handle as being used */ - object->isOpen = true; - HwiP_restore(key); - - /* Power on the Crypto module */ - Power_setDependency(PowerCC32XX_PERIPH_DTHE); - MAP_PRCMPeripheralReset(PRCM_DTHE); - - /* create the semaphore for each crypto type*/ - SemaphoreP_Params_init(&semParams); - semParams.mode = SemaphoreP_Mode_BINARY; - for (type=0 ;type < CryptoCC32XX_MAX_TYPES; type++) - { - if ((types & (1<sem[type] = SemaphoreP_create(1, &semParams); - if (object->sem[type] == NULL) - { - CryptoCC32XX_close(handle); - return (NULL); - } - /* interrupt handler */ - object->hwiHandle[type] = CryptoCC32XX_register(handle,&CryptoCC32XX_HwiPTable[type]); - if (object->hwiHandle[type] == NULL) - { - CryptoCC32XX_close(handle); - return (NULL); - } - } - else - { - object->sem[type] = NULL; - } - } - /* Return the address of the handle */ - return (handle); -} - -/* - * ======== CryptoCC32XX_HmacParams_init ======== - */ -void CryptoCC32XX_HmacParams_init(CryptoCC32XX_HmacParams *params) -{ - memset(params, 0, sizeof(CryptoCC32XX_HmacParams)); - params->first = 1; - /* All supported hashing algorithms block size are equal, set one as default */ - params->blockSize = CryptoCC32XX_SHA256_BLOCK_SIZE; -} - -/* - * ======== CryptoCC32XX_encrypt ======== - */ -int32_t CryptoCC32XX_encrypt(CryptoCC32XX_Handle handle, CryptoCC32XX_EncryptMethod method , void *pInBuff, size_t inLen, void *pOutBuff , size_t *outLen , CryptoCC32XX_EncryptParams *pParams) -{ - CryptoCC32XX_Object *object = handle->object; - uint8_t cryptoType = method >> 8; - uint32_t cryptoMode = CryptoCC32XX_getMode((uint32_t)method); - int32_t status = CryptoCC32XX_STATUS_ERROR; - /* Convert crypto type bitwise to index */ - uint8_t cryptoIndex = cryptoType >> 1; - - /* check semaphore created */ - if (object->sem[cryptoIndex] == NULL) - { - return CryptoCC32XX_STATUS_ERROR_NOT_SUPPORTED; - } - /* get the semaphore */ - if (SemaphoreP_OK == SemaphoreP_pend(object->sem[cryptoIndex], - SemaphoreP_WAIT_FOREVER)) - { - switch (cryptoType) - { - case CryptoCC32XX_AES: - status = CryptoCC32XX_aesProcess(cryptoMode , AES_CFG_DIR_ENCRYPT, pInBuff, inLen, pOutBuff , pParams); - break; - case CryptoCC32XX_DES: - status = CryptoCC32XX_desProcess(cryptoMode , DES_CFG_DIR_ENCRYPT, pInBuff, inLen, pOutBuff , pParams); - break; - default: - break; - } - - /* release the semaphore */ - SemaphoreP_post(object->sem[cryptoIndex]); - } - return status; -} - -/* - * ======== CryptoCC32XX_decrypt ======== - */ -int32_t CryptoCC32XX_decrypt(CryptoCC32XX_Handle handle, CryptoCC32XX_EncryptMethod method , void *pInBuff, size_t inLen, void *pOutBuff , size_t *outLen , CryptoCC32XX_EncryptParams *pParams) -{ - CryptoCC32XX_Object *object = handle->object; - uint8_t cryptoType = method >> 8; - uint32_t cryptoMode = CryptoCC32XX_getMode((uint32_t)method); - int32_t status = CryptoCC32XX_STATUS_ERROR; - /* Convert crypto type bitwise to index */ - uint8_t cryptoIndex = cryptoType >> 1; - - /* check semaphore created */ - if (object->sem[cryptoIndex] == NULL) - { - return CryptoCC32XX_STATUS_ERROR_NOT_SUPPORTED; - } - /* get the semaphore */ - if (SemaphoreP_OK == SemaphoreP_pend(object->sem[cryptoIndex], - SemaphoreP_WAIT_FOREVER)) - { - switch (cryptoType) - { - case CryptoCC32XX_AES: - status = CryptoCC32XX_aesProcess(cryptoMode , AES_CFG_DIR_DECRYPT, pInBuff, inLen, pOutBuff , pParams); - break; - case CryptoCC32XX_DES: - status = CryptoCC32XX_desProcess(cryptoMode , DES_CFG_DIR_DECRYPT, pInBuff, inLen, pOutBuff , pParams); - break; - default: - break; - } - /* release the semaphore */ - SemaphoreP_post(object->sem[cryptoIndex]); - } - return status; -} - - -/* - * ======== CryptoCC32XX_sign ======== - */ -int32_t CryptoCC32XX_sign(CryptoCC32XX_Handle handle, CryptoCC32XX_HmacMethod method , void *pBuff, size_t len, uint8_t *pSignature, CryptoCC32XX_HmacParams *pParams) -{ - CryptoCC32XX_Object *object = handle->object; - uint8_t cryptoType = CryptoCC32XX_HMAC; - uint32_t cryptoMode = CryptoCC32XX_getMode((uint32_t)method); - int32_t status = CryptoCC32XX_STATUS_ERROR; - /* Convert crypto type bitwise to index */ - uint8_t cryptoIndex = cryptoType >> 1; - - /* check semaphore created */ - if (object->sem[cryptoIndex] == NULL) - { - return CryptoCC32XX_STATUS_ERROR_NOT_SUPPORTED; - } - /* get the semaphore */ - if (SemaphoreP_OK == SemaphoreP_pend(object->sem[cryptoIndex], - SemaphoreP_WAIT_FOREVER)) - { - switch (cryptoType) - { - case CryptoCC32XX_HMAC: - status = CryptoCC32XX_shamd5Process(cryptoMode , pBuff, len, pSignature , pParams); - break; - default: - break; - } - /* release the semaphore */ - SemaphoreP_post(object->sem[cryptoIndex]); - } - return status; -} - -/* - * ======== CryptoCC32XX_verify ======== - */ -int32_t CryptoCC32XX_verify(CryptoCC32XX_Handle handle, CryptoCC32XX_HmacMethod method , void *pBuff, size_t len, uint8_t *pSignature, CryptoCC32XX_HmacParams *pParams) -{ - CryptoCC32XX_Object *object = handle->object; - uint8_t cryptoType = CryptoCC32XX_HMAC; - uint32_t cryptoMode = CryptoCC32XX_getMode((uint32_t)method); - int32_t status = CryptoCC32XX_STATUS_ERROR; - uint16_t shamd5SignatureSize; - CryptoCC32XX_SHAMD5Signature shamd5Signature; - /* Convert crypto type bitwise to index */ - uint8_t cryptoIndex = cryptoType >> 1; - - /* check semaphore created */ - if (object->sem[cryptoIndex] == NULL) - { - return CryptoCC32XX_STATUS_ERROR_NOT_SUPPORTED; - } - /* get the semaphore */ - if (SemaphoreP_OK == SemaphoreP_pend(object->sem[cryptoIndex], - SemaphoreP_WAIT_FOREVER)) - { - switch (cryptoType) - { - case CryptoCC32XX_HMAC: - shamd5SignatureSize = CryptoCC32XX_SHAMD5GetSignatureSize(cryptoMode); - if (shamd5SignatureSize > 0) - { - if (pParams->moreData == 0) - { - /* save the received signature */ - memcpy(shamd5Signature,pSignature,shamd5SignatureSize); - } - /* calculate the signature */ - status = CryptoCC32XX_shamd5Process(cryptoMode , pBuff, len, pSignature , pParams); - /* compare the calculated signature to the received signature */ - if (status == CryptoCC32XX_STATUS_SUCCESS) - { - if (pParams->moreData == 0) - { - if (memcmp(shamd5Signature,pSignature,shamd5SignatureSize) != 0) - { - status = CryptoCC32XX_STATUS_ERROR_VERIFY; - } - } - } - } - break; - default: - break; - } - /* release the semaphore */ - SemaphoreP_post(object->sem[cryptoIndex]); - } - return status; -} - -/* - * ======== CryptoCC32XX_shamd5Process ======== - */ -int32_t CryptoCC32XX_shamd5Process(uint32_t cryptoMode , uint8_t *pBuff, uint32_t len, uint8_t *pSignature, CryptoCC32XX_HmacParams *pParams) -{ - int32_t count = CryptoCC32XX_CONTEXT_READY_MAX_COUNTER; - uint32_t blockComplementLen = 0; - uint32_t newLen = 0; - uint32_t copyLen = 0; - uint32_t totalLen = 0; - uint32_t blockRemainder = 0; - /* - Step1: Enable Interrupts - Step2: Wait for Context Ready Interrupt - Step3: Set the Configuration Parameters (Hash Algorithm) - Step4: Set Key - Step5: Start Hash Generation - */ - - if((pBuff == NULL) || (0 == len)) - { - return CryptoCC32XX_STATUS_ERROR; - } - - /* Clear the flag */ - g_bSHAMD5ReadyFlag = false; - - /* Enable interrupts. */ - MAP_SHAMD5IntEnable(SHAMD5_BASE, SHAMD5_INT_CONTEXT_READY | - SHAMD5_INT_PARTHASH_READY | - SHAMD5_INT_INPUT_READY | - SHAMD5_INT_OUTPUT_READY); - - /* Wait for the context ready flag. */ - while ((!g_bSHAMD5ReadyFlag) && (count > 0)) - { - count --; - } - if (count == 0) - { - return CryptoCC32XX_STATUS_ERROR; - } - - if (pParams->moreData == 1) - { - /* Less than block size available. Copy the received data to the internal buffer and return */ - if((pParams->buffLen + len) < pParams->blockSize) - { - memcpy(&pParams->buff[pParams->buffLen], pBuff, len); - pParams->buffLen += len; - return CryptoCC32XX_STATUS_SUCCESS; - } - - if(pParams->first) - { - /* If Keyed Hashing is used, set Key */ - if (pParams->pKey != NULL) - { - MAP_SHAMD5HMACKeySet(SHAMD5_BASE, pParams->pKey); - MAP_SHAMD5ConfigSet(SHAMD5_BASE, cryptoMode, 0, 0, 1, 0); - } - else - { - MAP_SHAMD5ConfigSet(SHAMD5_BASE, cryptoMode, 1, 0, 0, 0); - } - - /* Will write data in this iteration. Unset first */ - pParams->first = 0; - } - else - { - MAP_SHAMD5ConfigSet(SHAMD5_BASE, cryptoMode, 0, 0, 0, 0); - /* Write the intermediate digest and count in case it isn't the first round */ - SHAMD5ResultWrite(SHAMD5_BASE, pParams->innerDigest); - SHAMD5WriteDigestCount(SHAMD5_BASE, pParams->digestCount); - } - } - else - { - if(pParams->first) - { - /* If Keyed Hashing is used, set Key */ - if (pParams->pKey != NULL) - { - MAP_SHAMD5HMACKeySet(SHAMD5_BASE, pParams->pKey); - MAP_SHAMD5ConfigSet(SHAMD5_BASE, cryptoMode, 0, 1, 1, 1); - } - else - { - MAP_SHAMD5ConfigSet(SHAMD5_BASE, cryptoMode, 1, 1, 0, 0); - } - } - else - { - /* Write the intermediate digest and count in case it isn't the first round */ - SHAMD5ResultWrite(SHAMD5_BASE, pParams->innerDigest); - SHAMD5WriteDigestCount(SHAMD5_BASE, pParams->digestCount); - if (pParams->pKey != NULL) - { - MAP_SHAMD5ConfigSet(SHAMD5_BASE, cryptoMode, 0, 1, 0, 1); - } - else - { - MAP_SHAMD5ConfigSet(SHAMD5_BASE, cryptoMode, 0, 1, 0, 0); - } - - /* This is the last iteration for the requested calculation */ - /* Set the first flag to 1 (initial value) for next calculations */ - pParams->first = 1; - } - } - - /* Set the length of the data that will be written to the SHA module in this iteration */ - /* In case it isn't the last iteration, it has to be an integer multiple of block size */ - if (pParams->moreData) - { - totalLen = ((pParams->buffLen + len) / pParams->blockSize) * pParams->blockSize; - } - else - { - totalLen = pParams->buffLen + len; - } - SHAMD5DataLengthSet(SHAMD5_BASE, totalLen); - - /* In case there is data in the internal buffer, complement to a block size (if the length is sufficient) and write */ - if (pParams->buffLen) - { - blockComplementLen = pParams->blockSize - pParams->buffLen; - /* Copy to the internal buffer */ - /* The length to copy is the minimum between the block complement and the data length */ - copyLen = len < blockComplementLen ? len : blockComplementLen; - memcpy(&pParams->buff[pParams->buffLen], pBuff, copyLen); - pParams->buffLen += copyLen; - - /* If buffLen is smaller than block size this must be the last iteration */ - /* Write and set the buffer and buffer length to zero */ - SHAMD5DataWriteMultiple(SHAMD5_BASE, pParams->buff, pParams->buffLen); - pParams->buffLen = 0; - memset(pParams->buff, 0, sizeof(pParams->buff)); - } - - /* If data length is greater than block complement, write the rest of the data */ - if (len > blockComplementLen) - { - newLen= len - blockComplementLen; - pBuff += blockComplementLen; - } - - if (pParams->moreData) - { - /* Remaining length is smaller than block size - Save data to the internal buffer */ - if (newLen < pParams->blockSize) - { - memcpy(&pParams->buff[pParams->buffLen], pBuff, newLen); - pParams->buffLen = newLen; - } - /* Remaining length is greater than block size - write blocks and save remainder to the internal buffer */ - else - { - blockRemainder = newLen % pParams->blockSize; - newLen -= blockRemainder; - SHAMD5DataWriteMultiple(SHAMD5_BASE, pBuff, newLen); - - if (blockRemainder) - { - pBuff += newLen; - memcpy(&pParams->buff[pParams->buffLen], pBuff, blockRemainder); - pParams->buffLen += blockRemainder; - } - } - } - else - { - /* Last iteration, write all the data */ - if (newLen) - { - SHAMD5DataWriteMultiple(SHAMD5_BASE, pBuff, newLen); - } - } - - /* Wait for the output to be ready */ - while((HWREG(SHAMD5_BASE + SHAMD5_O_IRQSTATUS) & SHAMD5_INT_OUTPUT_READY) == 0) - { - } - - /* Read the result */ - if (pParams->moreData == 1) - { - /* Read the digest and count to an internal parameter (will be used in the next iteration) */ - MAP_SHAMD5ResultRead(SHAMD5_BASE, pParams->innerDigest); - SHAMD5ReadDigestCount(SHAMD5_BASE, &(pParams->digestCount)); - } - else - { - /* Read the final digest result to an outer pointer */ - MAP_SHAMD5ResultRead(SHAMD5_BASE, pSignature); - } - - return CryptoCC32XX_STATUS_SUCCESS; -} - -/* - * ======== CryptoCC32XX_aesProcess ======== - */ -int32_t CryptoCC32XX_aesProcess(uint32_t cryptoMode , uint32_t cryptoDirection, uint8_t *pInBuff, uint16_t inLen, uint8_t *pOutBuff , CryptoCC32XX_EncryptParams *pParams) -{ - int32_t count = CryptoCC32XX_CONTEXT_READY_MAX_COUNTER; - /* - Step1: Enable Interrupts - Step2: Wait for Context Ready Interrupt - Step3: Set the Configuration Parameters (Direction,AES Mode and Key Size) - Step4: Set the Initialization Vector - Step5: Write Key - Step6: Start the Crypt Process - */ - - /* Clear the flag. */ - g_bAESReadyFlag = false; - - /* Enable all interrupts. */ - MAP_AESIntEnable(AES_BASE, AES_INT_CONTEXT_IN | AES_INT_CONTEXT_OUT | AES_INT_DATA_IN | AES_INT_DATA_OUT); - - /* Wait for the context in flag, the flag will be set in the Interrupt handler. */ - while((!g_bAESReadyFlag) && (count > 0)) - { - count --; - } - if (count == 0) - { - return CryptoCC32XX_STATUS_ERROR; - } - - /* Configure the AES module with direction (encryption or decryption) and */ - /* the key size. */ - MAP_AESConfigSet(AES_BASE, cryptoDirection | cryptoMode | CryptoCC32XX_getAesKeySize(pParams->aes.keySize)); - - /* Write the initial value registers if needed, depends on the mode. */ - if ((cryptoMode == AES_CFG_MODE_CBC) || (cryptoMode == AES_CFG_MODE_CFB) || - (cryptoMode == AES_CFG_MODE_CTR) || (cryptoMode == AES_CFG_MODE_ICM) || - (cryptoMode == AES_CFG_MODE_CCM) || (cryptoMode == AES_CFG_MODE_GCM_HY0CALC)) - { - MAP_AESIVSet(AES_BASE, pParams->aes.pIV); - } - - - /* Write key1. */ - MAP_AESKey1Set(AES_BASE, (uint8_t *)pParams->aes.pKey,CryptoCC32XX_getAesKeySize(pParams->aes.keySize)); - - /* Write key2. */ - if (cryptoMode == AES_CFG_MODE_CCM) - { - MAP_AESKey2Set(AES_BASE, pParams->aes.aadParams.input.pKey2, CryptoCC32XX_getAesKeySize(pParams->aes.aadParams.input.key2Size)); - } - - /* Start Crypt Process */ - if ((cryptoMode == AES_CFG_MODE_CCM) || (cryptoMode == AES_CFG_MODE_GCM_HY0CALC)) - { - MAP_AESDataProcessAE(AES_BASE, (uint8_t *)(pInBuff+(pParams->aes.aadParams.input.len)), pOutBuff ,inLen, pInBuff, pParams->aes.aadParams.input.len, pParams->aes.aadParams.tag); - - } - else - { - MAP_AESDataProcess(AES_BASE, pInBuff, pOutBuff, inLen); - } - - /* Read the initial value registers if needed, depends on the mode. */ - if ((cryptoMode == AES_CFG_MODE_CBC) || (cryptoMode == AES_CFG_MODE_CFB) || - (cryptoMode == AES_CFG_MODE_CTR) || (cryptoMode == AES_CFG_MODE_ICM) || - (cryptoMode == AES_CFG_MODE_CCM) || (cryptoMode == AES_CFG_MODE_GCM_HY0CALC)) - { - MAP_AESIVGet(AES_BASE, pParams->aes.pIV); - } - - return CryptoCC32XX_STATUS_SUCCESS; - -} - -/* - * ======== CryptoCC32XX_desProcess ======== - */ -int32_t CryptoCC32XX_desProcess(uint32_t cryptoMode , uint32_t cryptoDirection, uint8_t *pInBuff, uint16_t inLen, uint8_t *pOutBuff , CryptoCC32XX_EncryptParams *pParams) -{ - int32_t count = CryptoCC32XX_CONTEXT_READY_MAX_COUNTER; - - /* - Step1: Enable Interrupts - Step2: Wait for Context Ready Interrupt - Step3: Set the Configuration Parameters (Direction,AES Mode) - Step4: Set the Initialization Vector - Step5: Write Key - Step6: Start the Crypt Process - */ - - /* Clear the flag. */ - g_bDESReadyFlag = false; - - /* Enable all interrupts. */ - MAP_DESIntEnable(DES_BASE, DES_INT_CONTEXT_IN | DES_INT_DATA_IN | DES_INT_DATA_OUT); - - /* Wait for the context in flag. */ - while((!g_bDESReadyFlag) && (count > 0)) - { - count --; - } - if (count == 0) - { - return CryptoCC32XX_STATUS_ERROR; - } - - /* Configure the DES module. */ - MAP_DESConfigSet(DES_BASE, cryptoDirection | cryptoMode | CryptoCC32XX_getDesKeySize(pParams->des.keySize)); - - /* Set the key. */ - MAP_DESKeySet(DES_BASE, (uint8_t *)pParams->des.pKey); - - /* Write the initial value registers if needed. */ - if((cryptoMode & DES_CFG_MODE_CBC) || (cryptoMode & DES_CFG_MODE_CFB)) - { - MAP_DESIVSet(DES_BASE, pParams->des.pIV); - } - - MAP_DESDataProcess(DES_BASE, pInBuff, pOutBuff,inLen); - return CryptoCC32XX_STATUS_SUCCESS; -} - - -/* - * ======== CryptoCC32XX_aesIntHandler ======== - */ -void CryptoCC32XX_aesIntHandler(void) -{ - uint32_t uiIntStatus; - - /* Read the AES masked interrupt status. */ - uiIntStatus = MAP_AESIntStatus(AES_BASE, true); - - /* Set Different flags depending on the interrupt source. */ - if(uiIntStatus & AES_INT_CONTEXT_IN) - { - MAP_AESIntDisable(AES_BASE, AES_INT_CONTEXT_IN); - g_bAESReadyFlag = true; - } - if(uiIntStatus & AES_INT_DATA_IN) - { - MAP_AESIntDisable(AES_BASE, AES_INT_DATA_IN); - } - if(uiIntStatus & AES_INT_CONTEXT_OUT) - { - MAP_AESIntDisable(AES_BASE, AES_INT_CONTEXT_OUT); - } - if(uiIntStatus & AES_INT_DATA_OUT) - { - MAP_AESIntDisable(AES_BASE, AES_INT_DATA_OUT); - } -} - -/* - * ======== CryptoCC32XX_desIntHandler ======== - */ -void CryptoCC32XX_desIntHandler(void) -{ - uint32_t ui32IntStatus; - - /* Read the DES masked interrupt status. */ - ui32IntStatus = MAP_DESIntStatus(DES_BASE, true); - - /* set flags depending on the interrupt source. */ - if(ui32IntStatus & DES_INT_CONTEXT_IN) - { - MAP_DESIntDisable(DES_BASE, DES_INT_CONTEXT_IN); - g_bDESReadyFlag = true; - } - if(ui32IntStatus & DES_INT_DATA_IN) - { - MAP_DESIntDisable(DES_BASE, DES_INT_DATA_IN); - } - if(ui32IntStatus & DES_INT_DATA_OUT) - { - MAP_DESIntDisable(DES_BASE, DES_INT_DATA_OUT); - } -} - -/* - * ======== CryptoCC32XX_shamd5IntHandler ======== - */ -void CryptoCC32XX_shamd5IntHandler(void) -{ - uint32_t ui32IntStatus; - - /* Read the SHA/MD5 masked interrupt status. */ - ui32IntStatus = MAP_SHAMD5IntStatus(SHAMD5_BASE, true); - - if(ui32IntStatus & SHAMD5_INT_CONTEXT_READY) - { - MAP_SHAMD5IntDisable(SHAMD5_BASE, SHAMD5_INT_CONTEXT_READY); - g_bSHAMD5ReadyFlag = true; - } - if(ui32IntStatus & SHAMD5_INT_PARTHASH_READY) - { - MAP_SHAMD5IntDisable(SHAMD5_BASE, SHAMD5_INT_PARTHASH_READY); - } - if(ui32IntStatus & SHAMD5_INT_INPUT_READY) - { - MAP_SHAMD5IntDisable(SHAMD5_BASE, SHAMD5_INT_INPUT_READY); - } - if(ui32IntStatus & SHAMD5_INT_OUTPUT_READY) - { - MAP_SHAMD5IntDisable(SHAMD5_BASE, SHAMD5_INT_OUTPUT_READY); - } -} - -/* - * ======== CryptoCC32XX_register ======== - */ -HwiP_Handle CryptoCC32XX_register(CryptoCC32XX_Handle handle, CryptoCC32XX_HwiP *hwiP) -{ - HwiP_Params hwiParams; - HwiP_Handle hwiHandle = NULL; - - if (hwiP->hwiIntFxn != NULL) - { - /* Create Hwi object for this CryptoCC32XX peripheral. */ - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t)handle; - hwiParams.priority = hwiP->intPriority; - hwiHandle = HwiP_create(hwiP->intNum, hwiP->hwiIntFxn,&hwiParams); - } - return hwiHandle; -} - -/* - * ======== CryptoCC32XX_unregister ======== - */ -void CryptoCC32XX_unregister(HwiP_Handle handle) -{ - if (handle != NULL) - { - /* Delete Hwi object */ - HwiP_delete(handle); - } -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/crypto/CryptoCC32XX.h b/ext/hal/ti/simplelink/source/ti/drivers/crypto/CryptoCC32XX.h deleted file mode 100644 index 287e07e1626..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/crypto/CryptoCC32XX.h +++ /dev/null @@ -1,557 +0,0 @@ -/* - * Copyright (c) 2015-2016, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file CryptoCC32XX.h - * - * @brief Crypto driver implementation for a CC32XX Crypto controller. - * - * The Crypto header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * # Operation # - * - * The CryptoCC32XX driver is used several security methods (AES, DES and HMAC Hash functions). - * This driver provides API for encrypt/decrypt (AES and DES) - * and sign/verify (HMAC hash) - * - * The application initializes the CryptoCC32XX driver by calling CryptoCC32XX_init() - * and is then ready to open a Crypto by calling CryptoCC32XX_open(). - * - * The APIs in this driver serve as an interface to a typical TI-RTOS - * application. The specific peripheral implementations are responsible to - * create all the OSAL specific primitives to allow for thread-safe - * operation. - * - * ## Opening the driver # - * - * @code - * CryptoCC32XX_Handle handle; - * - * handle = CryptoCC32XX_open(CryptoCC32XX_configIndexValue, CryptoCC32XX_AES | - CryptoCC32XX_DES | - CryptoCC32XX_HMAC); - * if (!handle) { - * System_printf("CryptoCC32XX did not open"); - * } - * @endcode - * - * - * ## AES data encryption # - * - * @code - * CryptoCC32XX_EncryptMethod method = desiredMethod; - * CryptoCC32XX_Params params; - * unsigned char plainData[16] = "whatsoever123456"; - * unsigned int plainDataLen = sizeof(plainData); - * unsigned char cipherData[16]; - * unsigned int cipherDataLen; - * - * params.aes.keySize = desiredKeySize; - * params.aes.pKey = (CryptoCC32XX_KeyPtr)desiredKey; // desiredKey length should be as the desiredKeySize - * params.aes.pIV = (void *)pointerToInitVector; - * ret = CryptoCC32XX_encrypt(handle, method , plainData, plainDataLen, cipherData , &cipherDataLen , ¶ms); - * - * @endcode - * - * ## Generate HMAC Hash signature # - * - * @code - * CryptoCC32XX_HmacMethod hmacMethod = desiredHmacMethod; - * CryptoCC32XX_Params params; - * unsigned char dataBuff[] = "whatsoever"; - * unsigned int dataLength = sizeof(dataBuff); - * unsigned char signatureBuff[32]; - * - * params.pKey = pointerToHMACkey; - * params.moreData = 0; - * ret = CryptoCC32XX_sign(handle, hmacMethod , &dataBuff, dataLength, &signatureBuff, ¶ms); - * - * @endcode - * - * # Implementation # - * - * The CryptoCC32XX driver interface module is joined (at link time) to a - * NULL-terminated array of CryptoCC32XX_Config data structures named *CryptoCC32XX_config*. - * *CryptoCC32XX_config* is implemented in the application with each entry being an - * instance of a CryptoCC32XX peripheral. Each entry in *CryptoCC32XX_config* contains a: - * - (void *) data object that is pointed to CryptoCC32XX_Object - * - * - * ============================================================================ - */ - -#ifndef ti_drivers_crypto_CryptoCC32XX__include -#define ti_drivers_crypto_CryptoCC32XX__include - -#ifdef __cplusplus -extern "C" { -#endif - - -#include -#include -#include -#include -#include - - -#define CryptoCC32XX_CMD_RESERVED 32 - -#define CryptoCC32XX_STATUS_RESERVED -32 - -/*! - * @brief Successful status code returned by Crypto Common functions. - * - */ -#define CryptoCC32XX_STATUS_SUCCESS 0 - -/*! - * @brief Generic error status code returned by Crypto Common functions. - * - */ -#define CryptoCC32XX_STATUS_ERROR -1 - -/*! - * @brief An error status code returned by Crypto Common functions for undefined - * command codes. - * - */ -#define CryptoCC32XX_STATUS_UNDEFINEDCMD -2 - -/*! - * @brief An error status code returned by CryptoCC32XX_verify for define error in - * verifying a given Hash value. - * - */ -#define CryptoCC32XX_STATUS_ERROR_VERIFY -3 - -/*! - * @brief An error status code returned by Crypto Common functions for define - * cryptographic type not supported. - * - */ -#define CryptoCC32XX_STATUS_ERROR_NOT_SUPPORTED -4 - - -#define CryptoCC32XX_MAX_TYPES 3 - -#define CryptoCC32XX_MD5_BLOCK_SIZE 64 -#define CryptoCC32XX_SHA1_BLOCK_SIZE 64 -#define CryptoCC32XX_SHA256_BLOCK_SIZE 64 - -#define CryptoCC32XX_MD5_DIGEST_SIZE 16 -#define CryptoCC32XX_SHA1_DIGEST_SIZE 20 -#define CryptoCC32XX_SHA256_DIGEST_SIZE 32 - -#define CryptoCC32XX_MAX_DIGEST_SIZE CryptoCC32XX_SHA256_DIGEST_SIZE -#define CryptoCC32XX_MAX_BLOCK_SIZE CryptoCC32XX_SHA256_BLOCK_SIZE - - -/*! - * @brief Cryptography types configuration - * - * This enum defines bitwise Cryptography types. - */ -typedef enum -{ - CryptoCC32XX_AES = 0x01, /*!< Advanced Encryption Standard */ - CryptoCC32XX_DES = 0x02, /*!< Data Encryption Standard */ - CryptoCC32XX_HMAC = 0x04, /*!< Cryptographic hash function */ -}CryptoCC32XX_Type; - -/*! - * @brief AES and DES Cryptography methods configuration - * Keep the Crypto method in the lower 8 bit and - * Crypto type in the upper 8 bits - * - * This enum defines the AES and DES Cryptography modes. - */ -typedef enum -{ - CryptoCC32XX_AES_ECB = (CryptoCC32XX_AES << 8) | 1, /*!< AES Electronic CodeBook */ - CryptoCC32XX_AES_CBC, /*!< AES Cipher Block Chaining */ - CryptoCC32XX_AES_CTR, /*!< AES Counter */ - CryptoCC32XX_AES_ICM, /*!< AES Integer Counter Mode */ - CryptoCC32XX_AES_CFB, /*!< AES Cipher FeedBack */ - CryptoCC32XX_AES_GCM, /*!< AES Galois/Counter Mode */ - CryptoCC32XX_AES_CCM, /*!< AES Counter with CBC-MAC Mode */ - - CryptoCC32XX_DES_ECB = (CryptoCC32XX_DES << 8) | 1, /*!< DES Electronic CodeBook */ - CryptoCC32XX_DES_CBC, /*!< DES Cipher Block Chaining */ - CryptoCC32XX_DES_CFB, /*!< DES Cipher FeedBack */ - -}CryptoCC32XX_EncryptMethod; - -/*! - * @brief HMAC Cryptography methods configuration - * Keep the Crypto method in the lower 8 bit and - * Crypto type in the upper 8 bits - * - * This enum defines the HMAC HASH algorithms modes. - */ -typedef enum -{ - CryptoCC32XX_HMAC_MD5 = (CryptoCC32XX_HMAC << 8) | 1, /*!< MD5 used keyed-hash message authentication code */ - CryptoCC32XX_HMAC_SHA1, /*!< SHA1 used keyed-hash message authentication code */ - CryptoCC32XX_HMAC_SHA224, /*!< SHA224 used keyed-hash message authentication code */ - CryptoCC32XX_HMAC_SHA256 /*!< SHA256 used keyed-hash message authentication code */ - -}CryptoCC32XX_HmacMethod; - -/*! - * @brief AES Cryptography key size type configuration - * - * This enum defines the AES key size types - */ -typedef enum -{ - CryptoCC32XX_AES_KEY_SIZE_128BIT, - CryptoCC32XX_AES_KEY_SIZE_192BIT, - CryptoCC32XX_AES_KEY_SIZE_256BIT - -}CryptoCC32XX_AesKeySize; - -/*! - * @brief DES Cryptography key size type configuration - * - * This enum defines the DES key size types - */ -typedef enum -{ - CryptoCC32XX_DES_KEY_SIZE_SINGLE, - CryptoCC32XX_DES_KEY_SIZE_TRIPLE - -}CryptoCC32XX_DesKeySize; - - -/*! - * @brief AES Additional Authentication Data input parameters - * - * This structure defines the AES Additional Authentication Data input parameters used for - * CryptoCC32XX_AES_GCM and CryptoCC32XX_AES_CCM - */ -typedef struct -{ - uint8_t *pKey2; /*!< pointer to AES second key (CryptoCC32XX_AES_CCM) */ - CryptoCC32XX_AesKeySize key2Size; /*!< AES second Key size type (CryptoCC32XX_AES_CCM) */ - size_t len; /*!< length of the additional authentication data in bytes */ -}CryptoCC32XX_AesAadInputParams; - -/*! - * @brief AES Additional Authentication Data Parameters - * - * This union defines the AES additional authentication parameters used for - * CryptoCC32XX_AES_GCM and CryptoCC32XX_AES_CCM - */ -typedef union -{ - CryptoCC32XX_AesAadInputParams input; /*! -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -extern const UDMACC32XX_Config UDMACC32XX_config[]; - -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg); - -static bool dmaInitialized = false; -static Power_NotifyObj postNotifyObj; /* LPDS wake-up notify object */ - -/* Reference count for open calls */ -static uint32_t refCount = 0; - -/* - * ======== UDMACC32XX_close ======== - */ -void UDMACC32XX_close(UDMACC32XX_Handle handle) -{ - UDMACC32XX_Object *object = handle->object; - uintptr_t key; - - Power_releaseDependency(PowerCC32XX_PERIPH_UDMA); - - key = HwiP_disable(); - - refCount--; - - if (refCount == 0) { - Power_unregisterNotify(&postNotifyObj); - object->isOpen = false; - } - - HwiP_restore(key); -} - -/* - * ======== UDMACC32XX_init ======== - */ -void UDMACC32XX_init() -{ - HwiP_Params hwiParams; - UDMACC32XX_Handle handle = (UDMACC32XX_Handle)&(UDMACC32XX_config[0]); - UDMACC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - UDMACC32XX_Object *object = handle->object; - - if (!dmaInitialized) { - object->isOpen = false; - - HwiP_Params_init(&hwiParams); - hwiParams.priority = hwAttrs->intPriority; - - /* Will check in UDMACC32XX_open() if this failed */ - object->hwiHandle = HwiP_create(hwAttrs->intNum, hwAttrs->dmaErrorFxn, - &hwiParams); - if (object->hwiHandle == NULL) { - DebugP_log0("Failed to create uDMA error Hwi!!\n"); - } - else { - dmaInitialized = true; - } - } -} - -/* - * ======== UDMACC32XX_open ======== - */ -UDMACC32XX_Handle UDMACC32XX_open() -{ - UDMACC32XX_Handle handle = (UDMACC32XX_Handle)&(UDMACC32XX_config); - UDMACC32XX_Object *object = handle->object; - UDMACC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - uintptr_t key; - - if (!dmaInitialized) { - return (NULL); - } - - Power_setDependency(PowerCC32XX_PERIPH_UDMA); - - key = HwiP_disable(); - - /* - * If the UDMA has not been opened yet, create the error Hwi - * and initialize the control table base address. - */ - if (object->isOpen == false) { - MAP_PRCMPeripheralReset(PRCM_UDMA); - - MAP_uDMAEnable(); - MAP_uDMAControlBaseSet(hwAttrs->controlBaseAddr); - - Power_registerNotify(&postNotifyObj, PowerCC32XX_AWAKE_LPDS, - postNotifyFxn, (uintptr_t)handle); - - object->isOpen = true; - } - - refCount++; - - HwiP_restore(key); - - return (handle); -} - -/* - * ======== postNotifyFxn ======== - * Called by Power module when waking up from LPDS. - */ -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - UDMACC32XX_Handle handle = (UDMACC32XX_Handle)clientArg; - UDMACC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - - MAP_uDMAEnable(); - MAP_uDMAControlBaseSet(hwAttrs->controlBaseAddr); - - return (Power_NOTIFYDONE); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/dma/UDMACC32XX.h b/ext/hal/ti/simplelink/source/ti/drivers/dma/UDMACC32XX.h deleted file mode 100644 index a2e11508845..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/dma/UDMACC32XX.h +++ /dev/null @@ -1,200 +0,0 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file UDMACC32XX.h - * - * @brief uDMA driver implementation for CC32XX. - * - * This driver is intended for use only by drivers that use the uDMA - * peripheral (e.g., SPI and I2S). This driver is mainly used for Power - * management of the UDMA peripheral. - * - * The application should only define the memory for the control table and - * set up the UDMACC32XX_HWAttrs and UDMACC32XX_Config structures. - * - * The UDMACC32XX header file should be included in an application as follows: - * @code - * #include - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_drivers_dma_UDMACC32XX__include -#define ti_drivers_dma_UDMACC32XX__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/*! - * @brief UDMA error function pointer - */ -typedef void (*UDMACC32XX_ErrorFxn)(uintptr_t arg); - -/*! - * @brief UDMACC32XX Hardware attributes - * - * This structure contains the base address of the uDMA control - * table, and uDMA error interrupt attributes. - * - * The control table is used by the uDMA controller to store channel - * control structures. The control table can be located anywhere in - * system memory, but must be contiguous and aligned on a 1024-byte boundary. - * - * dmaErrorFxn is the uDMA peripheral's error interrupt handler. - * - * intPriority is priority of the uDMA peripheral's error interrupt, as - * defined by the underlying OS. It is passed unmodified to the - * underlying OS's interrupt handler creation code, so you need to - * refer to the OS documentation for usage. If the - * driver uses the ti.dpl interface instead of making OS - * calls directly, then the HwiP port handles the interrupt priority - * in an OS specific way. In the case of the SYS/BIOS port, - * intPriority is passed unmodified to Hwi_create(). - * - * A sample structure is shown below: - * @code - * - * #include - * - * static tDMAControlTable dmaControlTable[64] __attribute__ ((aligned (1024))); - * - * #include - * - * UDMACC32XX_Object udmaCC32XXObject; - * - * const UDMACC32XX_HWAttrs udmaCC32XXHWAttrs = { - * .controlBaseAddr = (void *)dmaControlTable, - * .dmaErrorFxn = UDMACC32XX_errorFxn, - * .intNum = INT_UDMAERR, - * .intPriority = (~0) - * }; - * @endcode - * - */ -typedef struct UDMACC32XX_HWAttrs { - void *controlBaseAddr; /*!< uDMA control registers base address */ - UDMACC32XX_ErrorFxn dmaErrorFxn; /*!< uDMA error interrupt handler */ - uint8_t intNum; /*!< uDMA error interrupt number */ - uint8_t intPriority; /*!< uDMA error interrupt priority. */ -} UDMACC32XX_HWAttrs; - -/*! - * @brief UDMACC32XX Global configuration - * - * The UDMACC32XX_Config structure contains pointers used by the UDMACC32XX - * driver. - * - * This structure needs to be defined before calling UDMACC32XX_init() and - * it must not be changed thereafter. - */ -typedef struct UDMACC32XX_Config { - void *object; /*!< Pointer to UDMACC32XX object */ - void const *hwAttrs; /*!< Pointer to hardware attributes */ -} UDMACC32XX_Config; - -/*! - * @brief A handle that is returned from a UDMACC32XX_open() call. - */ -typedef struct UDMACC32XX_Config *UDMACC32XX_Handle; - -/*! - * @brief UDMACC32XX object - * - * The application must not access any member variables of this structure! - */ -typedef struct UDMACC32XX_Object { - bool isOpen; /* Flag for open/close status */ - HwiP_Handle hwiHandle; /* DMA error Hwi */ -} UDMACC32XX_Object; - -/*! - * @brief Function to close the DMA driver. - * - * This function releases Power dependency on UDMA that was previously - * set with a call to UDMACC32XX_open(). If there is only one outstanding - * UDMACC32XX_open() call (i.e. all but one UDMACC32XX_open() calls have - * been matched by a corresponding call to UDMACC32XX_close()), this - * function will disable the UDMA. - * - * @pre UDMACC32XX_open() has to be called first. - * Calling context: Task - * - * @param handle A UDMACC32XX_Handle returned from UDMACC32XX_open() - * - * @return none - * - * @sa UDMACC32XX_open - */ -extern void UDMACC32XX_close(UDMACC32XX_Handle handle); - -/*! - * @brief Function to initialize the CC32XX DMA driver - * - * The function will set the isOpen flag to false, and should be called prior - * to opening the DMA driver. - * - * @return none - * - * @sa UDMACC32XX_open() - */ -extern void UDMACC32XX_init(); - -/*! - * @brief Function to initialize the CC32XX DMA peripheral - * - * UDMACC32XX_open() can be called multiple times. Each time the - * function is called, it will set a dependency on the peripheral and - * enable the clock. The Power dependency count on the UDMA will be - * equal to the number of outstanding calls to UDMACC32XX_open(). - * Calling UDMACC32XX_close() will decrement the Power dependency count, - * and the last call to UDMACC32XX_close() will disable the UDMA. - * - * @pre UDMACC32XX_init() has to be called first. - * Calling context: Task - * - * @return UDMACC32XX_Handle on success or NULL if an error has occurred. - * - * @sa UDMACC32XX_close() - */ -extern UDMACC32XX_Handle UDMACC32XX_open(); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_dma_UDMACC32XX__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/dpl/ClockP.h b/ext/hal/ti/simplelink/source/ti/drivers/dpl/ClockP.h deleted file mode 100644 index 76a0bd810b8..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/dpl/ClockP.h +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file ClockP.h - * - * @brief Clock interface for the RTOS Porting Interface - * - * The ClockP module can be used to schedule functions that run at intervals - * specified in the underlying kernel's system ticks. ClockP instances are - * one-shot. The one-shot function will be run once - * after the specified period has elapsed since calling ClockP_start(). - * - * The ClockP module can also be used to obtain the period of the kernel's - * system tick in microseconds. This is useful for determining the number of - * ticks needed for setting a Clock object's period. - * - * When using the TI-RTOS kernel, ClockP functions are run at software - * interrupt level. With FreeRTOS, the ClockP functions are run by a timer - * service task with priority configured by the application. - * - * A common use case is to post a semaphore in the clock function. There is a - * specific API for this: Semaphore_postFromClock(). This must be used in a - * clock function (instead of Semaphore_post). - * - * ============================================================================ - */ - -#ifndef ti_dpl_ClockP__include -#define ti_dpl_ClockP__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/*! - * @brief Number of bytes greater than or equal to the size of any RTOS - * ClockP object. - * - * nortos: 32 (biggest of the HW-specific ClockP instance structs) - * SysBIOS: 36 - */ -#define ClockP_STRUCT_SIZE (36) - -/*! - * @brief ClockP structure. - * - * Opaque structure that should be large enough to hold any of the - * RTOS specific ClockP objects. - */ -typedef union ClockP_Struct { - uint32_t dummy; /*!< Align object */ - char data[ClockP_STRUCT_SIZE]; -} ClockP_Struct; - -/*! - * @brief Frequency-in-hertz struct - */ -typedef struct ClockP_FreqHz { - uint32_t hi; /*!< most significant 32-bits of frequency */ - uint32_t lo; /*!< least significant 32-bits of frequency */ -} ClockP_FreqHz; - -/*! - * @brief Status codes for ClockP APIs - */ -typedef enum ClockP_Status { - ClockP_OK = 0, - ClockP_FAILURE = -1 -} ClockP_Status; - -/*! - * @brief Opaque client reference to an instance of a ClockP - * - * A ClockP_Handle returned from the ::ClockP_create represents that instance. - * and then is used in the other instance based functions (e.g. ::ClockP_start, - * ::ClockP_stop, etc.). - */ -typedef void *ClockP_Handle; - -#define ClockP_handle(x) ((ClockP_Handle)(x)) - -extern uint32_t ClockP_tickPeriod; - -/*! - * @brief Prototype for a ClockP function. - */ -typedef void (*ClockP_Fxn)(uintptr_t arg); - -/*! - * @brief Basic ClockP Parameters - * - * Structure that contains the parameters passed into ::ClockP_create - * when creating a ClockP instance. The ::ClockP_Params_init function should - * be used to initialize the fields to default values before the application - * sets the fields manually. The ClockP default parameters are noted in - * ClockP_Params_init. - * The default startFlag is false, meaning the user will have to call - * ClockP_start(). If startFlag is true, the clock instance will be - * started automatically when it is created. - * - * The default value of period is 0, indicating a one-shot clock object. - * A non-zero period indicates the clock function will be called - * periodically at the period rate (in system clock ticks), after the - * clock is initially started and set to expire with the 'timeout' - * argument. - */ -typedef struct ClockP_Params { - bool startFlag; /*!< Start immediately after instance is created. */ - uint32_t period; /*!< Period of clock object. */ - uintptr_t arg; /*!< Argument passed into the clock function. */ -} ClockP_Params; - - -/*! - * @brief Function to construct a clock object. - * - * @param clockP Pointer to ClockP_Struct object. - * @param timeout The startup timeout, if supported by the RTOS. - * @param clockFxn Function called when timeout or period expires. - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The ClockP default - * parameters are noted in ::SwiP_Params_init. - * - * @return A ClockP_Handle on success or a NULL on an error - */ -extern ClockP_Handle ClockP_construct(ClockP_Struct *clockP, - ClockP_Fxn clockFxn, - uint32_t timeout, - ClockP_Params *params); - -/*! - * @brief Function to destruct a clock object - * - * @param clockP Pointer to a ClockP_Struct object that was passed to - * ClockP_construct(). - * - * @return - */ -extern void ClockP_destruct(ClockP_Struct *clockP); - -/*! - * @brief Function to create a clock object. - * - * @param clockFxn Function called when timeout or period expires. - * @param timeout The startup timeout, if supported by the RTOS. - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The ClockP default - * parameters are noted in ::ClockP_Params_init. - * - * @return A ClockP_Handle on success or a NULL on an error. This handle can - * be passed to ClockP_start() - */ -extern ClockP_Handle ClockP_create(ClockP_Fxn clockFxn, - uint32_t timeout, - ClockP_Params *params); - -/*! - * @brief Function to delete a clock. - * - * @param handle A ClockP_Handle returned from ::ClockP_create - */ -extern void ClockP_delete(ClockP_Handle handle); - -/*! - * @brief Get CPU frequency in Hz - * - * @param freq Pointer to the FreqHz structure - */ -extern void ClockP_getCpuFreq(ClockP_FreqHz *freq); - -/*! - * @brief Get the system tick period in microseconds. - * - * @return The kernel's system tick period in microseconds. - */ -extern uint32_t ClockP_getSystemTickPeriod(); - -/*! - * @brief Get the current tick value - * - * The value returned will wrap back to zero after it reaches the max - * value that can be stored in 32 bits. - * - * @return Time in system clock ticks - */ -extern uint32_t ClockP_getSystemTicks(); - -/*! - * @brief Get number of ClockP tick periods expected to expire between - * now and the next interrupt from the timer peripheral - * - * Returns the number of ClockP tick periods that are expected to expore - * between now and the next interrupt from the timer peripheral. - * - * Used internally by PowerCC26XX module - * - * @return count in ticks - */ -extern uint32_t ClockP_getTicksUntilInterrupt(); - -/*! - * @brief Get timeout of clock instance. - * - * Returns the remaining time in clock ticks if the instance has - * been started. If the clock is not active, the initial timeout value - * is returned. - * - * @return remaining timeout in clock ticks. - * - * Cannot change the initial timeout if the clock has been started. - */ -extern uint32_t ClockP_getTimeout(ClockP_Handle handle); - -/*! - * @brief Determine if a clock object is currently active (i.e., running) - * - * Returns true if the clock object is currently active, otherwise - * returns false. - * - * @return active state - */ -extern bool ClockP_isActive(ClockP_Handle handle); - -/*! - * @brief Initialize params structure to default values. - * - * The default parameters are: - * - name: NULL - * - arg: 0 - * - * @param params Pointer to the instance configuration parameters. - */ -extern void ClockP_Params_init(ClockP_Params *params); - -/*! - * @brief Set the initial timeout - * - * @param timeout Initial timeout in ClockP ticks - * - * Cannot change the initial timeout if the clock has been started. - */ -extern void ClockP_setTimeout(ClockP_Handle handle, uint32_t timeout); - -/*! - * @brief Function to start a clock. - * - * @param handle A ClockP_Handle returned from ::ClockP_create - */ -extern void ClockP_start(ClockP_Handle handle); - -/*! - * @brief Function to stop a clock. - * - * @param handle A ClockP_Handle returned from ::ClockP_create - * - * It is ok to call ClockP_stop() for a clock that has not been started. - * - * @return Status of the functions - * - ClockP_OK: Stopped the clock function successfully - * - ClockP_FAILURE: The API failed. - */ -extern void ClockP_stop(ClockP_Handle handle); - -extern void ClockP_timestamp(ClockP_Handle handle); - -/*! - * @brief Set delay in microseconds - * - * @param usec A duration in micro seconds - * - * @return ClockP_OK - */ -extern void ClockP_usleep(uint32_t usec); - -/*! - * @brief Set delay in seconds - * - * @param sec A duration in seconds - * - * @return ClockP_OK - */ -extern void ClockP_sleep(uint32_t sec); - - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_ClockP__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/dpl/DebugP.h b/ext/hal/ti/simplelink/source/ti/drivers/dpl/DebugP.h deleted file mode 100644 index 51faa02c346..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/dpl/DebugP.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * Copyright (c) 2015, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file DebugP.h - * - * @brief Debug support - * - * The DebugP module allows application to do logging and assert checking. - * - * DebugP_assert calls can be added into code. If the code - * is compiled with the compiler define DebugP_ASSERT_ENABLED set to a - * non-zero value, the call is passed onto the underlying assert checking. - * If DebugP_ASSERT_ENABLED is zero (or not defined), the calls are - * resolved to nothing. - * - * This module sits on top of the assert checking of the underlying - * RTOS. Please refer to the underlying RTOS port implementation for - * more details. - * - * Similarly, DebugP_logN calls can be added into code. If the code - * is compiled with the compiler define DebugP_LOG_ENABLED set to a - * non-zero value, the call is passed onto the underlying assert checking. - * If DebugP_LOG_ENABLED is zero (or not defined), the calls are - * resolved to nothing. - - * This module sits on top of the logging of the underlying - * RTOS. Please refer to the underlying RTOS port implementation for - * more details. - * - * ============================================================================ - */ - -#ifndef ti_dpl_DebugP__include -#define ti_dpl_DebugP__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif - -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif - -#if DebugP_ASSERT_ENABLED -extern void _DebugP_assert(int expression, const char *file, int line); -/*! - * @brief Assert checking function - * - * If the expression is evaluated to true, the API does nothing. - * If it is evaluated to false, the underlying RTOS port implementation - * handles the assert via its mechanisms. - * - * @param expression Expression to evaluate - */ -#define DebugP_assert(expression) (_DebugP_assert(expression, \ - __FILE__, __LINE__)) -#else -#define DebugP_assert(expression) -#endif - -#if DebugP_LOG_ENABLED -/*! - * @brief Debug log function with 0 parameters - * - * The underlying RTOS port implementation handles the - * logging via its mechanisms. - * - * @param format "printf" format string - */ -extern void DebugP_log0(const char *format); - -/*! - * @brief Debug log function with 1 parameters - * - * The underlying RTOS port implementation handles the - * logging via its mechanisms. - * - * @param format "printf" format string - * @param p1 first parameter to format string - */ -extern void DebugP_log1(const char *format, uintptr_t p1); - -/*! - * @brief Debug log function with 2 parameters - * - * The underlying RTOS port implementation handles the - * logging via its mechanisms. - * - * @param format "printf" format string - * @param p1 first parameter to format string - * @param p2 second parameter to format string - */ -extern void DebugP_log2(const char *format, uintptr_t p1, uintptr_t p2); - -/*! - * @brief Debug log function with 3 parameters - * - * The underlying RTOS port implementation handles the - * logging via its mechanisms. - * - * @param format "printf" format string - * @param p1 first parameter to format string - * @param p2 second parameter to format string - * @param p3 third parameter to format string - */ -extern void DebugP_log3(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3); - -/*! - * @brief Debug log function with 4 parameters - * - * The underlying RTOS port implementation handles the - * logging via its mechanisms. - * - * @param format "printf" format string - * @param p1 first parameter to format string - * @param p2 second parameter to format string - * @param p3 third parameter to format string - * @param p4 fourth parameter to format string - */ -extern void DebugP_log4(const char *format, uintptr_t p1, uintptr_t p2, uintptr_t p3, uintptr_t p4); -#else -#define DebugP_log0(format) -#define DebugP_log1(format, p1) -#define DebugP_log2(format, p1, p2) -#define DebugP_log3(format, p1, p2, p3) -#define DebugP_log4(format, p1, p2, p3, p4) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_DebugP__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/dpl/HwiP.h b/ext/hal/ti/simplelink/source/ti/drivers/dpl/HwiP.h deleted file mode 100644 index fa6f1260490..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/dpl/HwiP.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file HwiP.h - * - * @brief Hardware Interrupt module for the RTOS Porting Interface - * - * The ::HwiP_disable/::HwiP_restore APIs can be called recursively. The order - * of the HwiP_restore calls, must be in reversed order. For example: - * @code - * uintptr_t key1, key2; - * key1 = HwiP_disable(); - * key2 = HwiP_disable(); - * HwiP_restore(key2); - * HwiP_restore(key1); - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_dpl_HwiP__include -#define ti_dpl_HwiP__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/*! - * @brief Number of bytes greater than or equal to the size of any RTOS - * HwiP object. - * - * nortos: 12 - * SysBIOS: 28 - */ -#define HwiP_STRUCT_SIZE (28) - -/*! - * @brief HwiP structure. - * - * Opaque structure that should be large enough to hold any of the RTOS - * specific HwiP objects. - */ -typedef union HwiP_Struct { - uint32_t dummy; /*!< Align object */ - char data[HwiP_STRUCT_SIZE]; -} HwiP_Struct; - -/*! - * @brief Opaque client reference to an instance of a HwiP - * - * A HwiP_Handle returned from the ::HwiP_create represents that instance. - */ -typedef void *HwiP_Handle; - -/*! - * @brief Status codes for HwiP APIs - */ -typedef enum HwiP_Status { - HwiP_OK = 0, - HwiP_FAILURE = -1 -} HwiP_Status; - -/*! - * @brief Prototype for the entry function for a hardware interrupt - */ -typedef void (*HwiP_Fxn)(uintptr_t arg); - -/*! - * @brief Basic HwiP Parameters - * - * Structure that contains the parameters passed into ::HwiP_create - * when creating a HwiP instance. The ::HwiP_Params_init function should - * be used to initialize the fields to default values before the application sets - * the fields manually. The HwiP default parameters are noted in - * HwiP_Params_init. - * - * Parameter enableInt specifies if the interrupt should be enabled - * upon creation of the HwiP object. The default is true. - */ -typedef struct HwiP_Params { - uintptr_t arg; /*!< Argument passed into the Hwi function. */ - uint32_t priority; /*!< Device specific priority. */ - bool enableInt; /*!< Enable interrupt on creation. */ -} HwiP_Params; - -/*! - * @brief Interrupt number posted by SwiP - * - * The SwiP module needs its scheduler to run at key points in SwiP - * processing. This is accomplished via an interrupt that is configured - * at the lowest possible interrupt priority level and is plugged with - * the SwiP scheduler. This interrupt must be the *only* interrupt at - * that lowest priority. SwiP will post this interrupt whenever its - * scheduler needs to run. - * - * The default value for your device should suffice, but if a different - * interrupt is needed to be used for SwiP scheduling then HwiP_swiPIntNum - * can be assigned with this interrupt (early on, before HwiPs are created - * and before any SwiP gets posted). - */ -extern int HwiP_swiPIntNum; - -/*! - * @brief Function to construct a hardware interrupt object. - * - * @param hwiP Pointer to HwiP_Struct object. - * @param interruptNum Interrupt Vector Id - * @param hwiFxn entry function of the hardware interrupt - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The HwiP default - * parameters are noted in ::HwiP_Params_init. - * - * @return A HwiP_Handle on success or a NULL on an error - */ -extern HwiP_Handle HwiP_construct(HwiP_Struct *hwiP, int interruptNum, - HwiP_Fxn hwiFxn, HwiP_Params *params); - -/*! - * @brief Function to destruct a hardware interrupt object - * - * @param hwiP Pointer to a HwiP_Struct object that was passed to - * HwiP_construct(). - * - * @return - */ -extern void HwiP_destruct(HwiP_Struct *hwiP); - -/*! - * @brief Function to clear a single interrupt - * - * @param interruptNum interrupt number to clear - */ -extern void HwiP_clearInterrupt(int interruptNum); - -/*! - * @brief Function to create an interrupt on CortexM devices - * - * @param interruptNum Interrupt Vector Id - * - * @param hwiFxn entry function of the hardware interrupt - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The HwiP default - * parameters are noted in ::HwiP_Params_init. - * - * @return A HwiP_Handle on success or a NULL on an error - */ -extern HwiP_Handle HwiP_create(int interruptNum, HwiP_Fxn hwiFxn, - HwiP_Params *params); - -/*! - * @brief Function to delete an interrupt on CortexM devices - * - * @param handle returned from the HwiP_create call - * - * @return - */ -extern void HwiP_delete(HwiP_Handle handle); - -/*! - * @brief Function to disable interrupts to enter a critical region - * - * This function can be called multiple times, but must unwound in the reverse - * order. For example - * @code - * uintptr_t key1, key2; - * key1 = HwiP_disable(); - * key2 = HwiP_disable(); - * HwiP_restore(key2); - * HwiP_restore(key1); - * @endcode - * - * @return A key that must be passed to HwiP_restore to re-enable interrupts. - */ -extern uintptr_t HwiP_disable(void); - -/*! - * @brief Function to enable interrupts - */ -extern void HwiP_enable(void); - -/*! - * @brief Function to disable a single interrupt - * - * @param interruptNum interrupt number to disable - */ -extern void HwiP_disableInterrupt(int interruptNum); - -/*! - * @brief Function to enable a single interrupt - * - * @param interruptNum interrupt number to enable - */ -extern void HwiP_enableInterrupt(int interruptNum); - -/*! - * @brief Function to return a status based on whether it is in an interrupt - * context. - * - * @return A status: indicating whether the function was called in an - * ISR (true) or at thread level (false). - */ -extern bool HwiP_inISR(void); - -/*! - * @brief Initialize params structure to default values. - * - * The default parameters are: - * - arg: 0 - * - priority: ~0 - * - enableInt: true - * - * @param params Pointer to the instance configuration parameters. - */ -extern void HwiP_Params_init(HwiP_Params *params); - -/*! - * @brief Function to plug an interrupt vector - * - * @param interruptNum ID of interrupt to plug - * @param fxn ISR that services plugged interrupt - */ -extern void HwiP_plug(int interruptNum, void *fxn); - -/*! - * @brief Function to generate an interrupt - * - * @param interruptNum ID of interrupt to generate - */ -extern void HwiP_post(int interruptNum); - -/*! - * @brief Function to restore interrupts to exit a critical region - * - * @param key return from HwiP_disable - */ -extern void HwiP_restore(uintptr_t key); - -/*! - * @brief Function to overwrite HwiP function and arg - * - * @param hwiP handle returned from the HwiP_create or construct call - * @param fxn pointer to ISR function - * @param arg argument to ISR function - */ -extern void HwiP_setFunc(HwiP_Handle hwiP, HwiP_Fxn fxn, uintptr_t arg); - -/*! - * @brief Function to set the priority of a hardware interrupt - * - * @param interruptNum id of the interrupt to change - * @param priority new priority - */ -extern void HwiP_setPriority(int interruptNum, uint32_t priority); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_HwiP__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/dpl/MutexP.h b/ext/hal/ti/simplelink/source/ti/drivers/dpl/MutexP.h deleted file mode 100644 index 037bb553327..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/dpl/MutexP.h +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file MutexP.h - * - * @brief Mutex module for the RTOS Porting Interface - * - * The MutexP module allows task to maintain critical region segments. The - * MutexP module has two main functions: ::MutexP_lock and ::MutexP_unlock. - * - * The MutexP module supports recursive calls to the MutexP_lock API by a - * single task. The same number of MutexP_unlock calls must be done for the - * mutex to be release. Note: the returned key must be provided in the LIFO - * order. For example: - * @code - * uintptr_t key1, key2; - * key1 = MutexP_lock(); - * key2 = MutexP_lock(); - * MutexP_lock(key2); - * MutexP_lock(key1); - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_dpl_MutexP__include -#define ti_dpl_MutexP__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/*! - * @brief Number of bytes greater than or equal to the size of any RTOS - * MutexP object. - * - * nortos: 12 - * SysBIOS: 40 - */ -#define MutexP_STRUCT_SIZE (40) - -/*! - * @brief MutexP structure. - * - * Opaque structure that should be large enough to hold any of the - * RTOS specific MutexP objects. - */ -typedef union MutexP_Struct { - uint32_t dummy; /*!< Align object */ - char data[MutexP_STRUCT_SIZE]; -} MutexP_Struct; - -/*! - * @brief Status codes for MutexP APIs - */ -typedef enum MutexP_Status { - /*! API completed successfully */ - MutexP_OK = 0, - /*! API failed */ - MutexP_FAILURE = -1 -} MutexP_Status; - -/*! - * @brief Opaque client reference to an instance of a MutexP - * - * A MutexP_Handle returned from the ::MutexP_create represents that instance. - * and then is used in the other instance based functions (e.g. ::MutexP_lock, - * ::MutexP_unlock, etc.). - */ -typedef void *MutexP_Handle; - -/*! - * @brief Basic MutexP Parameters - * - * Structure that contains the parameters are passed into ::MutexP_create - * when creating a MutexP instance. The ::MutexP_Params_init function should - * be used to initialize the fields to default values before the application - * sets the fields manually. The MutexP default parameters are noted in - * ::MutexP_Params_init. - */ -typedef struct MutexP_Params { - void (*callback)(void); /*!< Callback while waiting for mutex unlock */ -} MutexP_Params; - - -/*! - * @brief Function to construct a mutex. - * - * @param handle Pointer to a MutexP_Struct object - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters (MutexP default - * parameters as noted in ::MutexP_Params_init. - * - * @return A MutexP_Handle on success or a NULL on an error - */ -extern MutexP_Handle MutexP_construct(MutexP_Struct *handle, - MutexP_Params *params); - -/*! - * @brief Function to destruct a mutex object - * - * @param mutexP Pointer to a MutexP_Struct object that was passed to - * MutexP_construct(). - * - * @return - */ -extern void MutexP_destruct(MutexP_Struct *mutexP); - -/*! - * @brief Function to create a mutex. - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The MutexP default - * parameters are noted in ::MutexP_Params_init. - * - * @return A MutexP_Handle on success or a NULL on an error - */ -extern MutexP_Handle MutexP_create(MutexP_Params *params); - -/*! - * @brief Function to delete a mutex. - * - * @param handle A MutexP_Handle returned from MutexP_create - */ -extern void MutexP_delete(MutexP_Handle handle); - -/*! - * @brief Initialize params structure to default values. - * - * The default parameters are: - * callback - NULL. - * - * @param params Pointer to the instance configuration parameters. - */ -extern void MutexP_Params_init(MutexP_Params *params); - -/*! - * @brief Function to lock a mutex. - * - * This function can only be called from a Task. It cannot be called from - * an interrupt. The lock will block until the mutex is available. - * - * Users of a mutex should make every attempt to minimize the duration that - * that they have it locked. This is to minimize latency. It is recommended - * that the users of the mutex do not block while they have the mutex locked. - * - * This function unlocks the mutex. If the mutex is locked multiple times - * by the caller, the same number of unlocks must be called. - * - * @param handle A MutexP_Handle returned from ::MutexP_create - * - * @return A key is returned. This key must be passed into ::MutexP_unlock. - */ -extern uintptr_t MutexP_lock(MutexP_Handle handle); - -/*! - * @brief Function to unlock a mutex - * - * This function unlocks the mutex. If the mutex is locked multiple times - * by the caller, the same number of unlocks must be called. The order of - * the keys must be reversed. For example - * @code - * uintptr_t key1, key2; - * key1 = MutexP_lock(); - * key2 = MutexP_lock(); - * MutexP_lock(key2); - * MutexP_lock(key1); - * @endcode - * - * @param handle A MutexP_Handle returned from ::MutexP_create - * - * @param key Return from ::MutexP_lock. - */ -extern void MutexP_unlock(MutexP_Handle handle, uintptr_t key); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_MutexP__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/dpl/SemaphoreP.h b/ext/hal/ti/simplelink/source/ti/drivers/dpl/SemaphoreP.h deleted file mode 100644 index 7753e2d75f2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/dpl/SemaphoreP.h +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file SemaphoreP.h - * - * @brief Semaphore module for the RTOS Porting Interface - * - * Semaphores can be counting semaphores or binary semaphores. Counting - * semaphores keep track of the number of times the semaphore has been posted - * with post functions. This is useful, for example, if you have a group of - * resources that are shared between tasks. Such tasks might call pend() to see - * if a resource is available before using one. A count of zero for a counting - * semaphore denotes that it is not available. A positive count denotes - * how many times a SemaphoreP_pend can be called before it is blocked (or - * returns SemaphoreP_TIMEOUT). - * - * Binary semaphores can have only two states: available (count = 1) and - * unavailable (count = 0). They can be used to share a single resource - * between tasks. They can also be used for a basic signalling mechanism, where - * the semaphore can be posted multiple times. Binary semaphores do not keep - * track of the count; they simply track whether the semaphore has been posted - * or not. - * - * ============================================================================ - */ - -#ifndef ti_dpl_SemaphoreP__include -#define ti_dpl_SemaphoreP__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/*! - * @brief Number of bytes greater than or equal to the size of any RTOS - * SemaphoreP object. - * - * nortos: 16 - * SysBIOS: 28 - */ -#define SemaphoreP_STRUCT_SIZE (28) - -/*! - * @brief SemaphoreP structure. - * - * Opaque structure that should be large enough to hold any of the - * RTOS specific SemaphoreP objects. - */ -typedef union SemaphoreP_Struct { - uint32_t dummy; /*!< Align object */ - char data[SemaphoreP_STRUCT_SIZE]; -} SemaphoreP_Struct; - -/*! - * @brief Wait forever define - */ -#define SemaphoreP_WAIT_FOREVER ~(0) - -/*! - * @brief No wait define - */ -#define SemaphoreP_NO_WAIT (0) - -/*! - * @brief Status codes for SemaphoreP APIs (for backwards compatibility) - */ -typedef enum SemaphoreP_Status { - /*! API completed successfully */ - SemaphoreP_OK = 0, - /*! API failed because of a timeout */ - SemaphoreP_TIMEOUT = -1 -} SemaphoreP_Status; - -/*! - * @brief Opaque client reference to an instance of a SemaphoreP - * - * A SemaphoreP_Handle returned from the ::SemaphoreP_create represents that - * instance and is used in the other instance based functions (e.g. - * ::SemaphoreP_post or ::SemaphoreP_pend, etc.). - */ -typedef void *SemaphoreP_Handle; - -/*! - * @brief Mode of the semaphore - */ -typedef enum SemaphoreP_Mode { - SemaphoreP_Mode_COUNTING = 0x0, - SemaphoreP_Mode_BINARY = 0x1 -} SemaphoreP_Mode; - -/*! - * @brief Basic SemaphoreP Parameters - * - * Structure that contains the parameters are passed into ::SemaphoreP_create - * when creating a SemaphoreP instance. The ::SemaphoreP_Params_init function - * should be used to initialize the fields to default values before the - * application sets the fields manually. The SemaphoreP default parameters are - * noted in SemaphoreP_Params_init. - */ -typedef struct SemaphoreP_Params { - SemaphoreP_Mode mode; /*!< Mode for the semaphore */ - void (*callback)(void); /*!< Callback while pending for semaphore post */ -} SemaphoreP_Params; - -/*! - * @brief Default SemaphoreP instance parameters - * - * SemaphoreP_defaultParams represents the default parameters that are - * used when creating or constructing a SemaphoreP instance. - * SemaphoreP_Params_init() will use the contents of this structure for - * initializing the SemaphoreP_Params instance. - * - * SemaphoreP_defaultParams is exposed to the application for the purpose - * of allowing the application to change the default parameters for all - * SemaphoreP instances created thereafter. The main intent for allowing - * the default parameters to be changed is for setting a semaphore's - * callback function to Power_idleFunc(), so that the SOC can enter low - * power mode when pending on a semaphore. - */ -extern SemaphoreP_Params SemaphoreP_defaultParams; - - -/* - * SemaphoreP construct APIs can only be used if one of the OS's - * is defined. For FreeRTOS, configSUPPORT_STATIC_ALLOCATION also - * has to be set to 1 in FreeRTOSConfig.h. - */ -extern SemaphoreP_Handle SemaphoreP_construct(SemaphoreP_Struct *handle, - unsigned int count, SemaphoreP_Params *params); - -extern SemaphoreP_Handle SemaphoreP_constructBinary(SemaphoreP_Struct *handle, - unsigned int count); - -extern void SemaphoreP_destruct(SemaphoreP_Struct *semP); - -/*! - * @brief Function to create a semaphore. - * - * @param count Initial count of the semaphore. For binary semaphores, - * only values of 0 or 1 are valid. - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters (SemaphoreP default - * parameters as noted in ::SemaphoreP_Params_init. - * - * @return A SemaphoreP_Handle on success or a NULL on an error - */ -extern SemaphoreP_Handle SemaphoreP_create(unsigned int count, - SemaphoreP_Params *params); - -/*! - * @brief Function to create a binary semaphore. - * - * This can be used instead of SemaphoreP_create() to create a binary - * semaphore. - * - * @param count Initial count of the binary semaphore. Only values - * of 0 or 1 are valid. - * - * @return A SemaphoreP_Handle on success or a NULL on an error - */ -extern SemaphoreP_Handle SemaphoreP_createBinary(unsigned int count); - -/*! - * @brief Function to create a binary semaphore. - * - * This can be used instead of SemaphoreP_create() to create a binary - * semaphore. - * - * @param count Initial count of the binary semaphore. Only values - * of 0 or 1 are valid. - * - * @return A SemaphoreP_Handle on success or a NULL on an error - */ -extern SemaphoreP_Handle SemaphoreP_createBinaryCallback(unsigned int count, - void (*callback)(void)); - -/*! - * @brief Function to delete a semaphore. - * - * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create - */ -extern void SemaphoreP_delete(SemaphoreP_Handle handle); - -/*! - * @brief Initialize params structure to default values. - * - * The default parameters are: - * - mode: SemaphoreP_Mode_COUNTING - * - name: NULL - * - * @param params Pointer to the instance configuration parameters. - */ -extern void SemaphoreP_Params_init(SemaphoreP_Params *params); - -/*! - * @brief Function to pend (wait) on a semaphore. - * - * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create - * - * @param timeout Timeout (in ClockP ticks) to wait for the semaphore to - * be posted (signalled). - * - * @return Status of the functions - * - SemaphoreP_OK: Obtained the semaphore - * - SemaphoreP_TIMEOUT: Timed out. Semaphore was not obtained. - */ -extern SemaphoreP_Status SemaphoreP_pend(SemaphoreP_Handle handle, - uint32_t timeout); - -/*! - * @brief Function to post (signal) a semaphore from task of ISR context. - * - * @param handle A SemaphoreP_Handle returned from ::SemaphoreP_create - */ -extern void SemaphoreP_post(SemaphoreP_Handle handle); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_SemaphoreP__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/dpl/SwiP.h b/ext/hal/ti/simplelink/source/ti/drivers/dpl/SwiP.h deleted file mode 100644 index 4f2b3f11d4d..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/dpl/SwiP.h +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file SwiP.h - * - * @brief Software Interrupt module for the RTOS Porting Interface - * - * ============================================================================ - */ - -#ifndef ti_dpl_SwiP__include -#define ti_dpl_SwiP__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/*! - * @brief Number of bytes greater than or equal to the size of any RTOS - * SwiP object. - * - * nortos: 40 - * SysBIOS: 52 - */ -#define SwiP_STRUCT_SIZE (52) - -/*! - * @brief SemaphoreP structure. - * - * Opaque structure that should be large enough to hold any of the - * RTOS specific SwiP objects. - */ -typedef union SwiP_Struct { - uint32_t dummy; /*!< Align object */ - char data[SwiP_STRUCT_SIZE]; -} SwiP_Struct; - -#include -#include -#include - -/*! - * @brief Opaque client reference to an instance of a SwiP - * - * A SwiP_Handle returned from the ::SwiP_create represents that instance. - */ -typedef void *SwiP_Handle; - -/*! - * @brief Status codes for SwiP APIs - * TODO: See if we need more error codes. - */ -typedef enum SwiP_Status { - SwiP_OK = 0, - SwiP_FAILURE = -1 -} SwiP_Status; - -/*! - * @brief Prototype for the entry function for a hardware interrupt - */ -typedef void (*SwiP_Fxn)(uintptr_t arg0, uintptr_t arg1); - -/*! - * @brief Basic SwiP Parameters - * - * Structure that contains the parameters passed into ::SwiP_create - * and ::SwiP_construct when creating or constructing a SwiP instance. - * The ::SwiP_Params_init function should be used to initialize the - * fields to default values before the application sets the fields - * manually. The SwiP default parameters are noted in ::SwiP_Params_init. - * - * Each SwiP object has a "trigger" used either to determine whether to - * post the SwiP or as a value that can be evaluated within the SwiP's - * function. - * - * The SwiP_andn and SwiP_dec functions post the SwiP - * if the trigger value transitions to 0. The SwiP_or and - * SwiP_inc functions also modify the trigger value. SwiP_or - * sets bits, and SwiP_andn clears bits. - */ -typedef struct SwiP_Params { - uintptr_t arg0; /*!< Argument passed into the SwiP function. */ - uintptr_t arg1; /*!< Argument passed into the SwiP function. */ - uint32_t priority; /*!< priority, 0 is min, 1, 2, ..., ~0 for max */ - uint32_t trigger; /*!< Initial SwiP trigger value. */ -} SwiP_Params; - -/*! - * @brief Function to construct a software interrupt object. - * - * @param swiP Pointer to SwiP_Struct object. - * @param swiFxn entry function of the software interrupt - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The SwiP default - * parameters are noted in ::SwiP_Params_init. - * - * @return A SwiP_Handle on success or a NULL on an error - */ -extern SwiP_Handle SwiP_construct(SwiP_Struct *swiP, SwiP_Fxn swiFxn, - SwiP_Params *params); - -/*! - * @brief Function to destruct a software interrupt object - * - * @param swiP Pointer to a SwiP_Struct object that was passed to - * SwiP_construct(). - * - * @return - */ -extern void SwiP_destruct(SwiP_Struct *swiP); - -/*! - * @brief Initialize params structure to default values. - * - * The default parameters are: - * - name: NULL - * - * @param params Pointer to the instance configuration parameters. - */ -extern void SwiP_Params_init(SwiP_Params *params); - -/*! - * @brief Function to create a software interrupt object. - * - * @param swiFxn entry function of the software interrupt - * - * @param params Pointer to the instance configuration parameters. NULL - * denotes to use the default parameters. The SwiP default - * parameters are noted in ::SwiP_Params_init. - * - * @return A SwiP_Handle on success or a NULL on an error - */ -extern SwiP_Handle SwiP_create(SwiP_Fxn swiFxn, - SwiP_Params *params); - -/*! - * @brief Function to delete a software interrupt object - * - * @param handle returned from the SwiP_create call - * - */ -extern void SwiP_delete(SwiP_Handle handle); - -/*! - * @brief Function to disable software interrupts - * - * This function can be called multiple times, but must unwound in the reverse - * order. For example - * @code - * uintptr_t key1, key2; - * key1 = SwiP_disable(); - * key2 = SwiP_disable(); - * SwiP_restore(key2); - * SwiP_restore(key1); - * @endcode - * - * @return A key that must be passed to SwiP_restore to re-enable interrupts. - */ -extern uintptr_t SwiP_disable(void); - -/*! - * @brief Function to get the trigger value of the currently running SwiP. - * - */ -extern uint32_t SwiP_getTrigger(); - -/*! - * @brief Clear bits in SwiP's trigger. Post SwiP if trigger becomes 0. - * - * @param handle returned from the SwiP_create or SwiP_construct call - * @param mask inverse value to be ANDed - */ -extern void SwiP_andn(SwiP_Handle handle, uint32_t mask); - -/*! - * @brief Decrement SwiP's trigger value. Post SwiP if trigger becomes 0. - * - * @param handle returned from the SwiP_create or SwiP_construct call - */ -extern void SwiP_dec(SwiP_Handle handle); - -/*! - * @brief Increment the SwiP's trigger value and post the SwiP. - * - * @param handle returned from the SwiP_create or SwiP_construct call - */ -extern void SwiP_inc(SwiP_Handle handle); - -/*! - * @brief Function to return a status based on whether it is in a - * software interrupt context. - * - * @return A status: indicating whether the function was called in a - * software interrupt routine (true) or not (false). - */ -extern bool SwiP_inISR(void); - -/*! - * @brief Or the mask with the SwiP's trigger value and post the SwiP. - * - * @param handle returned from the SwiP_create or SwiP_construct call - * @param mask value to be ORed - */ -extern void SwiP_or(SwiP_Handle handle, uint32_t mask); - -/*! - * @brief Unconditionally post a software interrupt. - * - * @param handle returned from the SwiP_create or SwiP_construct call - */ -extern void SwiP_post(SwiP_Handle handle); - -/*! - * @brief Function to restore software interrupts - * - * @param key return from SwiP_disable - */ -extern void SwiP_restore(uintptr_t key); - -/*! - * @brief Function to set the priority of a software interrupt - * - * @param handle returned from the SwiP_create or SwiP_construct call - * @param priority new priority - */ -extern void SwiP_setPriority(SwiP_Handle handle, uint32_t priority); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_SwiP__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/dpl/SystemP.h b/ext/hal/ti/simplelink/source/ti/drivers/dpl/SystemP.h deleted file mode 100644 index b5aa4c1aea0..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/dpl/SystemP.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2016, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** =========================================================================== - * @file SystemP.h - * - * @brief System module for the RTOS Porting Interface - * - * Basic system services for supporting printf-like output. - * - * =========================================================================== - */ - -#ifndef ti_dpl_SystemP__include -#define ti_dpl_SystemP__include - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -extern int SystemP_snprintf(char *buf, size_t n, const char *format,...); -extern int SystemP_vsnprintf(char *buf, size_t n, const char *format, va_list va); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_dpl_SemaphoreP__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/gpio/GPIOCC32XX.c b/ext/hal/ti/simplelink/source/ti/drivers/gpio/GPIOCC32XX.c deleted file mode 100644 index 6812fb5721c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/gpio/GPIOCC32XX.c +++ /dev/null @@ -1,815 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#if defined(__IAR_SYSTEMS_ICC__) -#include -#endif - -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif - -#include -#include -#include -#include -#include -#include -#include - -/* driverlib header files */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Map GPIO_INT types to corresponding CC32XX interrupt options - */ -static const uint8_t interruptType[] = { - 0, /* Undefined interrupt type */ - GPIO_FALLING_EDGE, /* 1 = Interrupt on falling edge */ - GPIO_RISING_EDGE, /* 2 = Interrupt on rising edge */ - GPIO_BOTH_EDGES, /* 3 = Interrupt on both edges */ - GPIO_LOW_LEVEL, /* 4 = Interrupt on low level */ - GPIO_HIGH_LEVEL /* 5 = Interrupt on high level */ -}; - -/* - * Table of port interrupt vector numbers - * Used by setCallback() to create Hwis. - * Up to 4 port interrupts must be supported - */ -static const uint8_t portInterruptIds[] = { - INT_GPIOA0, INT_GPIOA1, - INT_GPIOA2, INT_GPIOA3 -}; - -/* Table of GPIO input types */ -const uint16_t inPinTypes [] = { - PIN_TYPE_STD, /* GPIO_CFG_IN_NOPULL */ - PIN_TYPE_STD_PU, /* GPIO_CFG_IN_PU */ - PIN_TYPE_STD_PD /* GPIO_CFG_IN_PD */ -}; - -/* Table of GPIO output types */ -const uint16_t outPinTypes [] = { - PIN_TYPE_STD, /* GPIO_CFG_OUT_STD */ - PIN_TYPE_OD, /* GPIO_CFG_OUT_OD_NOPULL */ - PIN_TYPE_OD_PU, /* GPIO_CFG_OUT_OD_PU */ - PIN_TYPE_OD_PD /* GPIO_CFG_OUT_OD_PD */ -}; - -/* Table of GPIO drive strengths */ -const uint16_t outPinStrengths [] = { - PIN_STRENGTH_2MA, /* GPIO_CFG_OUT_STR_LOW */ - PIN_STRENGTH_4MA, /* GPIO_CFG_OUT_STR_MED */ - PIN_STRENGTH_6MA /* GPIO_CFG_OUT_STR_HIGH */ -}; - -/* - * Table of pin numbers (physical device pins) for use with PinTypeGPIO() - * driverlib call. - * - * Indexed by GPIO number (0-31). - */ -#define PIN_XX 0xFF -static const uint8_t pinTable[] = { - /* 00 01 02 03 04 05 06 07 */ - PIN_50, PIN_55, PIN_57, PIN_58, PIN_59, PIN_60, PIN_61, PIN_62, - /* 08 09 10 11 12 13 14 15 */ - PIN_63, PIN_64, PIN_01, PIN_02, PIN_03, PIN_04, PIN_05, PIN_06, - /* 16 17 18 19 20 21 22 23 */ - PIN_07, PIN_08, PIN_XX, PIN_XX, PIN_XX, PIN_XX, PIN_15, PIN_16, - /* 24 25 26 27 28 29 30 31 */ - PIN_17, PIN_21, PIN_29, PIN_30, PIN_18, PIN_20, PIN_53, PIN_45, - /* 32 */ - PIN_52 -}; - -/* - * Table of port bases address. For use with most driverlib calls. - * Indexed by GPIO port number (0-3). - */ -static const uint32_t gpioBaseAddresses[] = { - GPIOA0_BASE, GPIOA1_BASE, - GPIOA2_BASE, GPIOA3_BASE, - GPIOA4_BASE -}; - -static const uint32_t powerResources[] = { - PowerCC32XX_PERIPH_GPIOA0, - PowerCC32XX_PERIPH_GPIOA1, - PowerCC32XX_PERIPH_GPIOA2, - PowerCC32XX_PERIPH_GPIOA3, - PowerCC32XX_PERIPH_GPIOA4 -}; - -#define NUM_PORTS 4 -#define NUM_PINS_PER_PORT 8 -#define PORT_MASK 0x3 - -/* Returns the GPIO port base address */ -#define getPortBase(port) (gpioBaseAddresses[(port) & PORT_MASK]) - -/* Returns the GPIO port number */ -#define getPort(port) (port & PORT_MASK) - -/* Returns the GPIO power resource ID */ -#define getPowerResource(port) (powerResources[port & PORT_MASK]) - -/* Returns GPIO number from the pinConfig */ -#define getGpioNumber(pinConfig) \ - (((pinConfig->port & PORT_MASK) * 8) + getPinNumber(pinConfig->pin)) - -/* Uninitialized callbackInfo pinIndex */ -#define CALLBACK_INDEX_NOT_CONFIGURED 0xFF - -/* - * Device specific interpretation of the GPIO_PinConfig content - */ -typedef struct PinConfig { - uint8_t pin; - uint8_t port; - uint16_t config; -} PinConfig; - -/* - * User defined pin indexes assigned to a port's 8 pins. - * Used by port interrupt function to locate callback assigned - * to a pin. - */ -typedef struct PortCallbackInfo { - /* - * the port's 8 corresponding - * user defined pinId indices - */ - uint8_t pinIndex[NUM_PINS_PER_PORT]; -} PortCallbackInfo; - -/* - * Table of portCallbackInfos. - * One for each port. - */ -static PortCallbackInfo gpioCallbackInfo[NUM_PORTS]; - -/* - * bit mask used to determine if a Hwi has been created/constructed - * for a port already. - * up to NUM_PORTS port interrupts must be supported - */ -static uint8_t portHwiCreatedBitMask = 0; - -/* - * Bit mask used to keep track of which of the GPIO objects in the config - * structure have interrupts enabled. This will be used to restore the - * interrupts after coming out of LPDS. - */ -static uint32_t configIntsEnabledMask = 0; - -/* - * Internal boolean to confirm that GPIO_init() has been called. - */ -static bool initCalled = false; - -/* Notification for going into and waking up from LPDS */ -static Power_NotifyObj powerNotifyObj; - -extern const GPIOCC32XX_Config GPIOCC32XX_config; - -static int powerNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg); - -/* - * ======== getPinNumber ======== - * - * Internal function to efficiently find the index of the right most set bit. - */ -static inline uint32_t getPinNumber(uint32_t x) { -#if defined(__TI_COMPILER_VERSION__) - return (uint32_t)(__clz(__rbit(x)) & 0x7); -#elif defined(__GNUC__) - return (uint32_t)(__builtin_ctz(x) & 0x7); -#elif defined(__IAR_SYSTEMS_ICC__) - return (uint32_t)(__CLZ(__RBIT(x)) & 0x7); -#else - #error "Unsupported compiler used" -#endif -} - -/* - * ======== getInterruptTypeIndex ======== - */ -static inline uint32_t getInterruptTypeIndex(uint32_t pinConfig) -{ - uint32_t index; - - index = (pinConfig & GPIO_CFG_INT_MASK) >> GPIO_CFG_INT_LSB; - - /* - * If index is out-of-range, default to 0. This should never - * happen, but it's needed to keep Klocwork checker happy. - */ - if (index >= sizeof(interruptType) / sizeof(interruptType[0])) { - index = 0; - } - - return (index); -}; - -/* - * ======== getInPinTypesIndex ======== - */ -static inline uint32_t getInPinTypesIndex(uint32_t pinConfig) -{ - uint32_t index; - - index = (pinConfig & GPIO_CFG_IN_TYPE_MASK) >> GPIO_CFG_IN_TYPE_LSB; - - /* - * If index is out-of-range, default to 0. This should never - * happen, but it's needed to keep Klocwork checker happy. - */ - if (index >= sizeof(inPinTypes) / sizeof(inPinTypes[0])) { - index = 0; - } - - return (index); -} - -/* - * ======== getOutPinTypesIndex ======== - */ -static inline uint32_t getOutPinTypesIndex(uint32_t pinConfig) -{ - uint32_t index; - - index = (pinConfig & GPIO_CFG_OUT_TYPE_MASK) >> GPIO_CFG_OUT_TYPE_LSB; - - /* - * If index is out-of-range, default to 0. This should never - * happen, but it's needed to keep Klocwork checker happy. - */ - if (index >= sizeof(outPinTypes) / sizeof(outPinTypes[0])) { - index = 0; - } - - return (index); -} - -/* - * ======== getOutPinStrengthsIndex ======== - */ -static inline uint32_t getOutPinStrengthsIndex(uint32_t pinConfig) -{ - uint32_t index; - - index = (pinConfig & GPIO_CFG_OUT_STRENGTH_MASK) >> - GPIO_CFG_OUT_STRENGTH_LSB; - - /* - * If index is out-of-range, default to 0. This should never - * happen, but it's needed to keep Klocwork checker happy. - */ - if (index >= sizeof(outPinStrengths) / sizeof(outPinStrengths[0])) { - index = 0; - } - - return (index); -} - -/* - * ======== GPIO_clearInt ======== - */ -void GPIO_clearInt(uint_least8_t index) -{ - PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; - - DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); - - /* Clear GPIO interrupt flag */ - MAP_GPIOIntClear(getPortBase(config->port), config->pin); - - DebugP_log2("GPIO: port 0x%x, pin 0x%x interrupt flag cleared", - getPort(config->port), config->pin); -} - -/* - * ======== GPIO_disableInt ======== - */ -void GPIO_disableInt(uint_least8_t index) -{ - uintptr_t key; - PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; - - DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); - - /* Make atomic update */ - key = HwiP_disable(); - - /* Disable GPIO interrupt */ - MAP_GPIOIntDisable(getPortBase(config->port), config->pin); - - configIntsEnabledMask &= ~(1 << index); - - HwiP_restore(key); - - DebugP_log2("GPIO: port 0x%x, pin 0x%x interrupts disabled", - getPort(config->port), config->pin); -} - -/* - * ======== GPIO_enableInt ======== - */ -void GPIO_enableInt(uint_least8_t index) -{ - uintptr_t key; - PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; - - DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); - DebugP_assert(*((uint16_t *) config) != GPIOCC32XX_GPIO_26 && - *((uint16_t *) config) != GPIOCC32XX_GPIO_27); - - /* Make atomic update */ - key = HwiP_disable(); - - /* Enable GPIO interrupt */ - MAP_GPIOIntEnable(getPortBase(config->port), config->pin); - - configIntsEnabledMask |= (1 << index); - - HwiP_restore(key); - - DebugP_log2("GPIO: port 0x%x, pin 0x%x interrupts enabled", - getPort(config->port), config->pin); -} - -/* - * ======== GPIO_getConfig ======== - */ -void GPIO_getConfig(uint_least8_t index, GPIO_PinConfig *pinConfig) -{ - DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); - - *pinConfig = GPIOCC32XX_config.pinConfigs[index]; -} - -/* - * ======== GPIO_hwiIntFxn ======== - * Hwi function that processes GPIO interrupts. - */ -void GPIO_hwiIntFxn(uintptr_t portIndex) -{ - unsigned int bitNum; - unsigned int pinIndex; - uint32_t pins; - uint32_t portBase; - PortCallbackInfo *portCallbackInfo; - - portCallbackInfo = &gpioCallbackInfo[portIndex]; - portBase = getPortBase(portIndex); - - /* Find out which pins have their interrupt flags set */ - pins = MAP_GPIOIntStatus(portBase, 0xFF) & 0xFF; - - /* clear all the set bits at once */ - MAP_GPIOIntClear(portBase, pins); - - /* Match the interrupt to its corresponding callback function */ - while (pins) { - /* Gets the lowest order set bit number */ - bitNum = getPinNumber(pins); - pinIndex = portCallbackInfo->pinIndex[bitNum & 0x7]; - /* only call plugged callbacks */ - if (pinIndex != CALLBACK_INDEX_NOT_CONFIGURED) { - GPIOCC32XX_config.callbacks[pinIndex](pinIndex); - } - pins &= ~(1 << bitNum); - } -} - -/* - * ======== GPIO_init ======== - */ -void GPIO_init() -{ - unsigned int i, j, hwiKey; - SemaphoreP_Handle sem; - static SemaphoreP_Handle initSem; - - /* speculatively create a binary semaphore */ - sem = SemaphoreP_createBinary(1); - - /* There is no way to inform user of this fatal error. */ - if (sem == NULL) return; - - hwiKey = HwiP_disable(); - - if (initSem == NULL) { - initSem = sem; - HwiP_restore(hwiKey); - } - else { - /* init already called */ - HwiP_restore(hwiKey); - /* delete unused Semaphore */ - if (sem) SemaphoreP_delete(sem); - } - - /* now use the semaphore to protect init code */ - SemaphoreP_pend(initSem, SemaphoreP_WAIT_FOREVER); - - /* Only perform init once */ - if (initCalled) { - SemaphoreP_post(initSem); - return; - } - - for (i = 0; i < NUM_PORTS; i++) { - for (j = 0; j < NUM_PINS_PER_PORT; j++) { - gpioCallbackInfo[i].pinIndex[j] = CALLBACK_INDEX_NOT_CONFIGURED; - } - } - - /* - * Configure pins and create Hwis per static array content - */ - for (i = 0; i < GPIOCC32XX_config.numberOfPinConfigs; i++) { - if (!(GPIOCC32XX_config.pinConfigs[i] & GPIO_DO_NOT_CONFIG)) { - - GPIO_setConfig(i, GPIOCC32XX_config.pinConfigs[i]); - } - if (i < GPIOCC32XX_config.numberOfCallbacks) { - if (GPIOCC32XX_config.callbacks[i] != NULL) { - /* create Hwi as necessary */ - GPIO_setCallback(i, GPIOCC32XX_config.callbacks[i]); - } - } - } - - Power_registerNotify(&powerNotifyObj, - PowerCC32XX_ENTERING_LPDS | PowerCC32XX_AWAKE_LPDS, - powerNotifyFxn, (uintptr_t) NULL); - - initCalled = true; - - SemaphoreP_post(initSem); -} - -/* - * ======== GPIO_read ======== - */ -uint_fast8_t GPIO_read(uint_least8_t index) -{ - unsigned int value; - - PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; - - DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); - DebugP_assert(*((uint16_t *) config) != GPIOCC32XX_GPIO_26 && - *((uint16_t *) config) != GPIOCC32XX_GPIO_27); - - value = MAP_GPIOPinRead(getPortBase(config->port), config->pin); - - DebugP_log3("GPIO: port 0x%x, pin 0x%x read 0x%x", - getPort(config->port), config->pin, value); - - value = (value & config->pin) ? 1 : 0; - - return (value); -} - -/* - * ======== GPIO_setCallback ======== - */ -void GPIO_setCallback(uint_least8_t index, GPIO_CallbackFxn callback) -{ - uint32_t pinNum; - uint32_t portIndex; - PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; - - DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfCallbacks); - DebugP_assert(*((uint16_t *) config) != GPIOCC32XX_GPIO_26 && - *((uint16_t *) config) != GPIOCC32XX_GPIO_27); - - /* - * plug the pin index into the corresponding - * port's callbackInfo pinIndex entry - */ - pinNum = getPinNumber(config->pin); - portIndex = config->port & PORT_MASK; - - if (callback == NULL) { - gpioCallbackInfo[portIndex].pinIndex[pinNum] = - CALLBACK_INDEX_NOT_CONFIGURED; - } - else { - gpioCallbackInfo[portIndex].pinIndex[pinNum] = index; - } - - /* - * Only update callBackFunctions entry if different. - * This allows the callBackFunctions array to be in flash for static systems. - */ - if (GPIOCC32XX_config.callbacks[index] != callback) { - GPIOCC32XX_config.callbacks[index] = callback; - } -} - -/* - * ======== GPIO_setConfig ======== - */ -int_fast16_t GPIO_setConfig(uint_least8_t index, GPIO_PinConfig pinConfig) -{ - uintptr_t key; - uint32_t pinMask; - uint32_t pin; - uint32_t portBase; - uint32_t portIndex; - uint32_t portBitMask; - uint16_t direction; - uint16_t strength; - uint16_t pinType; - HwiP_Handle hwiHandle; - HwiP_Params hwiParams; - GPIO_PinConfig gpioPinConfig; - PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; - - DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); - DebugP_assert(*((uint16_t *) config) != GPIOCC32XX_GPIO_26 && - *((uint16_t *) config) != GPIOCC32XX_GPIO_27 || - (pinConfig & GPIO_CFG_INPUT) == 0); - - if (pinConfig & GPIO_DO_NOT_CONFIG) { - return (GPIO_STATUS_SUCCESS); - } - - portBase = getPortBase(config->port); - pinMask = config->pin; - pin = pinTable[getGpioNumber(config)]; - - /* Make atomic update */ - key = HwiP_disable(); - - /* set the pin's pinType to GPIO */ - MAP_PinModeSet(pin, PIN_MODE_0); - - /* enable clocks for the GPIO port */ - Power_setDependency(getPowerResource(config->port)); - - HwiP_restore(key); - - if ((pinConfig & GPIO_CFG_IN_INT_ONLY) == 0) { - if (pinConfig & GPIO_CFG_INPUT) { - /* configure input */ - direction = GPIO_DIR_MODE_IN; - strength = PIN_STRENGTH_2MA; - pinType = inPinTypes[getInPinTypesIndex(pinConfig)]; - } - else { - /* configure output */ - direction = GPIO_DIR_MODE_OUT; - strength = outPinStrengths[getOutPinStrengthsIndex(pinConfig)]; - pinType = outPinTypes[getOutPinTypesIndex(pinConfig)]; - } - - key = HwiP_disable(); - - /* Configure the GPIO pin */ - MAP_GPIODirModeSet(portBase, pinMask, direction); - MAP_PinConfigSet(pin, strength, pinType); - - /* Set output value */ - if (direction == GPIO_DIR_MODE_OUT) { - MAP_GPIOPinWrite(portBase, pinMask, - ((pinConfig & GPIO_CFG_OUT_HIGH) ? 0xFF : 0)); - } - - /* - * Update pinConfig with the latest GPIO configuration and - * clear the GPIO_DO_NOT_CONFIG bit if it was set. - */ - gpioPinConfig = GPIOCC32XX_config.pinConfigs[index]; - gpioPinConfig &= ~(GPIO_CFG_IO_MASK | GPIO_DO_NOT_CONFIG); - gpioPinConfig |= (pinConfig & GPIO_CFG_IO_MASK); - GPIOCC32XX_config.pinConfigs[index] = gpioPinConfig; - - HwiP_restore(key); - } - - /* Set type of interrupt and then clear it */ - if (pinConfig & GPIO_CFG_INT_MASK) { - portIndex = config->port & PORT_MASK; - portBitMask = 1 << portIndex; - - /* if Hwi has not already been created, do so */ - if ((portHwiCreatedBitMask & portBitMask) == 0) { - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t) portIndex; - hwiParams.priority = GPIOCC32XX_config.intPriority; - hwiHandle = HwiP_create(portInterruptIds[portIndex], GPIO_hwiIntFxn, - &hwiParams); - if (hwiHandle == NULL) { - /* Error creating Hwi */ - DebugP_log1("GPIO: Error constructing Hwi for GPIO Port %d", - getPort(config->port)); - return (GPIO_STATUS_ERROR); - } - } - - key = HwiP_disable(); - - /* Mark the Hwi as created */ - portHwiCreatedBitMask |= portBitMask; - - MAP_GPIOIntTypeSet(portBase, pinMask, - interruptType[getInterruptTypeIndex(pinConfig)]); - MAP_GPIOIntClear(portBase, pinMask); - - /* - * Update pinConfig with the latest interrupt configuration and - * clear the GPIO_DO_NOT_CONFIG bit if it was set. - */ - gpioPinConfig = GPIOCC32XX_config.pinConfigs[index]; - gpioPinConfig &= ~(GPIO_CFG_INT_MASK | GPIO_DO_NOT_CONFIG); - gpioPinConfig |= (pinConfig & GPIO_CFG_INT_MASK); - GPIOCC32XX_config.pinConfigs[index] = gpioPinConfig; - - HwiP_restore(key); - } - - return (GPIO_STATUS_SUCCESS); -} - -/* - * ======== GPIO_toggle ======== - */ -void GPIO_toggle(uint_least8_t index) -{ - uintptr_t key; - uint32_t value; - PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; - - DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); - DebugP_assert((GPIOCC32XX_config.pinConfigs[index] & GPIO_CFG_INPUT) == - GPIO_CFG_OUTPUT); - - /* Make atomic update */ - key = HwiP_disable(); - - value = MAP_GPIOPinRead(getPortBase(config->port), config->pin); - value ^= (uint32_t)config->pin; - MAP_GPIOPinWrite(getPortBase(config->port), config->pin, value); - - /* Update config table entry with value written */ - GPIOCC32XX_config.pinConfigs[index] ^= GPIO_CFG_OUT_HIGH; - - HwiP_restore(key); - - DebugP_log2("GPIO: port 0x%x, pin 0x%x toggled", - getPort(config->port), config->pin); -} - -/* - * ======== GPIO_write ======== - */ -void GPIO_write(uint_least8_t index, unsigned int value) -{ - uintptr_t key; - uint32_t output; - PinConfig *config = (PinConfig *) &GPIOCC32XX_config.pinConfigs[index]; - - DebugP_assert(initCalled && index < GPIOCC32XX_config.numberOfPinConfigs); - DebugP_assert((GPIOCC32XX_config.pinConfigs[index] & GPIO_CFG_INPUT) == - GPIO_CFG_OUTPUT); - - key = HwiP_disable(); - - /* Clear output from pinConfig */ - GPIOCC32XX_config.pinConfigs[index] &= ~GPIO_CFG_OUT_HIGH; - - if (value) { - output = config->pin; - - /* Set the pinConfig output bit to high */ - GPIOCC32XX_config.pinConfigs[index] |= GPIO_CFG_OUT_HIGH; - } - else { - output = value; - } - - MAP_GPIOPinWrite(getPortBase(config->port), config->pin, output); - - HwiP_restore(key); - - DebugP_log3("GPIO: port 0x%x, pin 0x%x wrote 0x%x", - getPort(config->port), config->pin, value); -} - -/* - * ======== powerNotifyFxn ======== - */ -static int powerNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - unsigned int i; - GPIO_PinConfig config; - uint32_t output; - uint32_t pin; - PinConfig *pinConfig; - PowerCC32XX_ParkState state; - - if (eventType == PowerCC32XX_AWAKE_LPDS) { - - for (i = 0; i < GPIOCC32XX_config.numberOfPinConfigs; i++) { - if (!(GPIOCC32XX_config.pinConfigs[i] & GPIO_DO_NOT_CONFIG)) { - config = GPIOCC32XX_config.pinConfigs[i]; - - GPIO_setConfig(i, config); - - if (configIntsEnabledMask & (1 << i)) { - GPIO_enableInt(i); - } - } - } - } - else { - /* Entering LPDS */ - /* - * For pins configured as GPIO output, if the GPIOCC32XX_USE_STATIC - * configuration flag is *not* set, get the current pin state, and - * then call to the Power manager to define the state to be held - * during LPDS. - * If GPIOCC32XX_USE_STATIC *is* defined, do nothing, and the pin - * will be parked in the state statically defined in - * PowerCC32XX_config.pinParkDefs[] in the board file. - */ - for (i = 0; i < GPIOCC32XX_config.numberOfPinConfigs; i++) { - if (GPIOCC32XX_config.pinConfigs[i] & GPIO_DO_NOT_CONFIG) { - continue; - } - - config = GPIOCC32XX_config.pinConfigs[i]; - - /* if OUTPUT, and GPIOCC32XX_USE_STATIC flag is not set */ - if ((!(config & GPIO_CFG_INPUT)) && - (!(config & GPIOCC32XX_USE_STATIC))) { - - pinConfig = (PinConfig *) &GPIOCC32XX_config.pinConfigs[i]; - - /* determine state to be held */ - pin = pinTable[getGpioNumber(pinConfig)]; - output = config & GPIO_CFG_OUT_HIGH; - state = (PowerCC32XX_ParkState) ((output) ? 1 : 0); - - /* set the new park state */ - PowerCC32XX_setParkState((PowerCC32XX_Pin)pin, state); - } - } - } - - return (Power_NOTIFYDONE); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/gpio/GPIOCC32XX.h b/ext/hal/ti/simplelink/source/ti/drivers/gpio/GPIOCC32XX.h deleted file mode 100644 index 4c3c5b2d8ca..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/gpio/GPIOCC32XX.h +++ /dev/null @@ -1,263 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*! ============================================================================ - * @file GPIOCC32XX.h - * - * @brief GPIO driver implementation for CC32xx devices - * - * The GPIO header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref GPIO.h for a complete description of the GPIO - * driver APIs provided and examples of their use. - * - * ### CC32xx GPIO Driver Configuration # - * - * In order to use the GPIO APIs, the application is required - * to provide 3 structures in the Board.c file: - * - * 1. An array of @ref GPIO_PinConfig elements that defines the - * initial configuration of each pin used by the application. A - * pin is referenced in the application by its corresponding index in this - * array. The pin type (that is, INPUT/OUTPUT), its initial state (that is - * OUTPUT_HIGH or LOW), interrupt behavior (RISING/FALLING edge, etc.) - * (see @ref GPIO_PinConfigSettings), and - * device specific pin identification (see @ref GPIOCC32XX_PinConfigIds) - * are configured in each element of this array. - * Below is an CC32XX device specific example of the GPIO_PinConfig array: - * @code - * // - * // Array of Pin configurations - * // NOTE: The order of the pin configurations must coincide with what was - * // defined in CC3220SF_LAUNCHXL.h - * // NOTE: Pins not used for interrupts should be placed at the end of the - * // array. Callback entries can be omitted from callbacks array to - * // reduce memory usage. - * // - * GPIO_PinConfig gpioPinConfigs[] = { - * // input pins with callbacks - * // CC3220SF_LAUNCHXL_GPIO_SW2 - * GPIOCC32XX_GPIO_22 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING, - * // CC3220SF_LAUNCHXL_GPIO_SW3 - * GPIOCC32XX_GPIO_13 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING, - * - * // output pins - * // CC3220SF_LAUNCHXL_GPIO_LED_D7 - * GPIOCC32XX_GPIO_09 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, - * }; - * @endcode - * - * 2. An array of @ref GPIO_CallbackFxn elements that is used to store - * callback function pointers for GPIO pins configured with interrupts. - * The indexes for these array elements correspond to the pins defined - * in the @ref GPIO_PinConfig array. These function pointers can be defined - * statically by referencing the callback function name in the array - * element, or dynamically, by setting the array element to NULL and using - * GPIO_setCallback() at runtime to plug the callback entry. - * Pins not used for interrupts can be omitted from the callback array to - * reduce memory usage (if they are placed at the end of the @ref - * GPIO_PinConfig array). The callback function syntax should match the - * following: - * @code - * void (*GPIO_CallbackFxn)(unsigned int index); - * @endcode - * The index parameter is the same index that was passed to - * GPIO_setCallback(). This allows the same callback function to be used - * for multiple GPIO interrupts, by using the index to identify the GPIO - * that caused the interrupt. - * Below is a CC32XX device specific example of the @ref GPIO_CallbackFxn - * array: - * @code - * // - * // Array of callback function pointers - * // NOTE: The order of the pin configurations must coincide with what was - * // defined in CC3220SF_LAUNCHXL.h - * // NOTE: Pins not used for interrupts can be omitted from callbacks array to - * // reduce memory usage (if placed at end of gpioPinConfigs array). - * // - * GPIO_CallbackFxn gpioCallbackFunctions[] = { - * NULL, // CC3220SF_LAUNCHXL_GPIO_SW2 - * NULL // CC3220SF_LAUNCHXL_GPIO_SW3 - * }; - * @endcode - * - * 3. The device specific GPIOCC32XX_Config structure that tells the GPIO - * driver where the two aforementioned arrays are and the number of elements - * in each. The interrupt priority of all pins configured to generate - * interrupts is also specified here. Values for the interrupt priority are - * device-specific. You should be well-acquainted with the interrupt - * controller used in your device before setting this parameter to a - * non-default value. The sentinel value of (~0) (the default value) is - * used to indicate that the lowest possible priority should be used. - * Below is an example of an initialized GPIOCC32XX_Config - * structure: - * @code - * const GPIOCC32XX_Config GPIOCC32XX_config = { - * .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, - * .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, - * .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), - * .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), - * .intPriority = (~0) - * }; - * @endcode - * - * \note GPIOCC32XX_GPIO_26 & GPIOCC32XX_GPIO_27 can only be used as output - * pins. - * - * ============================================================================ - */ - -#ifndef ti_drivers_GPIOCC32XX__include -#define ti_drivers_GPIOCC32XX__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -/*! - * @brief GPIO device specific driver configuration structure - * - * The device specific GPIOCC32XX_Config structure that tells the GPIO - * driver where the two aforementioned arrays are and the number of elements - * in each. The interrupt priority of all pins configured to generate - * interrupts is also specified here. Values for the interrupt priority are - * device-specific. You should be well-acquainted with the interrupt - * controller used in your device before setting this parameter to a - * non-default value. The sentinel value of (~0) (the default value) is - * used to indicate that the lowest possible priority should be used. - * - * Below is an example of an initialized GPIOCC32XX_Config - * structure: - * @code - * const GPIOCC32XX_Config GPIOCC32XX_config = { - * .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, - * .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, - * .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), - * .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), - * .intPriority = (~0) - * }; - * @endcode - */ -typedef struct GPIOCC32XX_Config { - /*! Pointer to the board's GPIO_PinConfig array */ - GPIO_PinConfig *pinConfigs; - - /*! Pointer to the board's GPIO_CallbackFxn array */ - GPIO_CallbackFxn *callbacks; - - /*! Number of GPIO_PinConfigs defined */ - uint32_t numberOfPinConfigs; - - /*! Number of GPIO_Callbacks defined */ - uint32_t numberOfCallbacks; - - /*! - * Interrupt priority used for call back interrupts. - * - * intPriority is the interrupt priority, as defined by the - * underlying OS. It is passed unmodified to the underlying OS's - * interrupt handler creation code, so you need to refer to the OS - * documentation for usage. If the driver uses the ti.dpl - * interface instead of making OS calls directly, then the HwiP port - * handles the interrupt priority in an OS specific way. In the case - * of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create(). - * - * Setting ~0 will configure the lowest possible priority - */ - uint32_t intPriority; -} GPIOCC32XX_Config; - -/*! - * \defgroup GPIOCC32XX_PinConfigIds GPIO pin identification macros used to configure GPIO pins - * @{ - */ -/** - * @name Device specific GPIO port/pin identifiers to be used within the board's GPIO_PinConfig table. - * @{ -*/ -#define GPIOCC32XX_EMPTY_PIN 0x0000 /*!< @hideinitializer */ - -#define GPIOCC32XX_GPIO_00 0x0001 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_01 0x0002 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_02 0x0004 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_03 0x0008 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_04 0x0010 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_05 0x0020 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_06 0x0040 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_07 0x0080 /*!< @hideinitializer */ - -#define GPIOCC32XX_GPIO_08 0x0101 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_09 0x0102 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_10 0x0104 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_11 0x0108 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_12 0x0110 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_13 0x0120 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_14 0x0140 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_15 0x0180 /*!< @hideinitializer */ - -#define GPIOCC32XX_GPIO_16 0x0201 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_17 0x0202 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_22 0x0240 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_23 0x0280 /*!< @hideinitializer */ - -#define GPIOCC32XX_GPIO_24 0x0301 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_25 0x0302 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_26 0x0304 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_27 0x0308 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_28 0x0310 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_29 0x0320 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_30 0x0340 /*!< @hideinitializer */ -#define GPIOCC32XX_GPIO_31 0x0380 /*!< @hideinitializer */ - -#define GPIOCC32XX_GPIO_32 0x0401 /*!< @hideinitializer */ -/** @} */ - -/** - * @name CC32xx device specific GPIO_PinConfig macros - * @{ - */ -#define GPIOCC32XX_USE_STATIC 0x8000 /*!< @hideinitializer use statically-defined parking state */ -/** @} */ - -/** @} end of GPIOCC32XX_PinConfigIds group */ - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_GPIOCC32XX__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/i2c/I2CCC32XX.c b/ext/hal/ti/simplelink/source/ti/drivers/i2c/I2CCC32XX.c deleted file mode 100644 index 7f0cf143ac8..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/i2c/I2CCC32XX.c +++ /dev/null @@ -1,851 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include - -/* Pad configuration defines */ -#define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) -#define PAD_DEFAULT_STATE 0xC60 /* pad reset, plus set GPIO mode to free I2C */ - -/* - * Specific I2C CMD MACROs that are not defined in I2C.h are defined here. Their - * equivalent values are taken from the existing MACROs in I2C.h - */ -#ifndef I2C_MASTER_CMD_BURST_RECEIVE_START_NACK -#define I2C_MASTER_CMD_BURST_RECEIVE_START_NACK I2C_MASTER_CMD_BURST_SEND_START -#endif - -#ifndef I2C_MASTER_CMD_BURST_RECEIVE_STOP -#define I2C_MASTER_CMD_BURST_RECEIVE_STOP I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP -#endif - -#ifndef I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK -#define I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK I2C_MASTER_CMD_BURST_SEND_CONT -#endif - -/* Prototypes */ -static void I2CCC32XX_blockingCallback(I2C_Handle handle, I2C_Transaction *msg, - bool transferStatus); -void I2CCC32XX_cancel(I2C_Handle handle); -void I2CCC32XX_close(I2C_Handle handle); -int_fast16_t I2CCC32XX_control(I2C_Handle handle, uint_fast16_t cmd, void *arg); -void I2CCC32XX_init(I2C_Handle handle); -I2C_Handle I2CCC32XX_open(I2C_Handle handle, I2C_Params *params); -bool I2CCC32XX_transfer(I2C_Handle handle, I2C_Transaction *transaction); - -static void initHw(I2C_Handle handle); -static int postNotify(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg); -static void I2CCC32XX_primeTransfer(I2CCC32XX_Object *object, - I2CCC32XX_HWAttrsV1 const *hwAttrs, - I2C_Transaction *transaction); - -/* I2C function table for I2CCC32XX implementation */ -const I2C_FxnTable I2CCC32XX_fxnTable = { - I2CCC32XX_cancel, - I2CCC32XX_close, - I2CCC32XX_control, - I2CCC32XX_init, - I2CCC32XX_open, - I2CCC32XX_transfer -}; - -static const uint32_t bitRate[] = { - false, /* I2C_100kHz = 0 */ - true /* I2C_400kHz = 1 */ -}; - -/* - * ======== I2CC32XX_cancel ======== - */ -void I2CCC32XX_cancel(I2C_Handle handle) -{ - I2CCC32XX_Object *object = handle->object; - I2CCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uintptr_t key; - - /* just return if no transfer is in progress */ - if (!object->headPtr) { - return; - } - - /* disable interrupts, send STOP to complete any transfer */ - key = HwiP_disable(); - MAP_I2CMasterIntDisable(hwAttrs->baseAddr); - - MAP_I2CMasterControl(hwAttrs->baseAddr, - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP); - - /* call the transfer callback for the current transfer, indicate failure */ - object->transferCallbackFxn(handle, object->currentTransaction, false); - - /* also dequeue and call the transfer callbacks for any queued transfers */ - while (object->headPtr != object->tailPtr) { - object->headPtr = object->headPtr->nextPtr; - object->transferCallbackFxn(handle, object->headPtr, false); - } - - /* clean up object */ - object->currentTransaction = NULL; - object->headPtr = NULL; - object->tailPtr = NULL; - object->mode = I2CCC32XX_IDLE_MODE; - - /* disable and the re-initialize master mode */ - MAP_I2CMasterDisable(hwAttrs->baseAddr); - initHw(handle); - - HwiP_restore(key); -} - -/* - * ======== I2CCC32XX_close ======== - */ -void I2CCC32XX_close(I2C_Handle handle) -{ - I2CCC32XX_Object *object = handle->object; - I2CCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uint32_t padRegister; - - /* Check to see if a I2C transaction is in progress */ - DebugP_assert(object->headPtr == NULL); - - /* Mask I2C interrupts */ - MAP_I2CMasterIntDisable(hwAttrs->baseAddr); - - /* Disable the I2C Master */ - MAP_I2CMasterDisable(hwAttrs->baseAddr); - - /* Disable I2C module clocks */ - Power_releaseDependency(PowerCC32XX_PERIPH_I2CA0); - - Power_unregisterNotify(&(object->notifyObj)); - - /* Restore pin pads to their reset states */ - padRegister = (PinToPadGet((hwAttrs->clkPin) & 0xff)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_DEFAULT_STATE; - padRegister = (PinToPadGet((hwAttrs->dataPin) & 0xff)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_DEFAULT_STATE; - - if (object->hwiHandle) { - HwiP_delete(object->hwiHandle); - } - if (object->mutex) { - SemaphoreP_delete(object->mutex); - } - /* Destruct the Semaphore */ - if (object->transferComplete) { - SemaphoreP_delete(object->transferComplete); - } - - object->isOpen = false; - - DebugP_log1("I2C: Object closed 0x%x", hwAttrs->baseAddr); - - return; -} - -/* - * ======== I2CCC32XX_completeTransfer ======== - */ -static void I2CCC32XX_completeTransfer(I2C_Handle handle) -{ - /* Get the pointer to the object */ - I2CCC32XX_Object *object = handle->object; - - DebugP_log1("I2C:(%p) ISR Transfer Complete", - ((I2CCC32XX_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); - - /* See if we need to process any other transactions */ - if (object->headPtr == object->tailPtr) { - - /* No other transactions need to occur */ - object->headPtr = NULL; - object->tailPtr = NULL; - - /* - * Allow callback to run. If in CALLBACK mode, the application - * may initiate a transfer in the callback which will call - * primeTransfer(). - */ - object->transferCallbackFxn(handle, object->currentTransaction, - (object->mode == I2CCC32XX_IDLE_MODE)); - - /* release constraint since transaction is done */ - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - - DebugP_log1("I2C:(%p) ISR No other I2C transaction in queue", - ((I2CCC32XX_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); - } - else { - /* Another transfer needs to take place */ - object->headPtr = object->headPtr->nextPtr; - - /* - * Allow application callback to run. The application may - * initiate a transfer in the callback which will add an - * additional transfer to the queue. - */ - object->transferCallbackFxn(handle, object->currentTransaction, - (object->mode == I2CCC32XX_IDLE_MODE)); - - DebugP_log2("I2C:(%p) ISR Priming next I2C transaction (%p) from queue", - ((I2CCC32XX_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr, - (uintptr_t)object->headPtr); - - I2CCC32XX_primeTransfer(object, - (I2CCC32XX_HWAttrsV1 const *)handle->hwAttrs, - object->headPtr); - } -} - -/* - * ======== I2CCC32XX_control ======== - * @pre Function assumes that the handle is not NULL - */ -int_fast16_t I2CCC32XX_control(I2C_Handle handle, uint_fast16_t cmd, void *arg) -{ - /* No implementation yet */ - return (I2C_STATUS_UNDEFINEDCMD); -} - -/* - * ======== I2CCC32XX_hwiFxn ======== - * Hwi interrupt handler to service the I2C peripheral - * - * The handler is a generic handler for a I2C object. - */ -static void I2CCC32XX_hwiFxn(uintptr_t arg) -{ - /* Get the pointer to the object and hwAttrs */ - I2CCC32XX_Object *object = ((I2C_Handle)arg)->object; - I2CCC32XX_HWAttrsV1 const *hwAttrs = ((I2C_Handle)arg)->hwAttrs; - uint32_t errStatus; - - /* Get the interrupt status of the I2C controller */ - errStatus = MAP_I2CMasterErr(hwAttrs->baseAddr); - - /* Clear interrupt source to avoid additional interrupts */ - MAP_I2CMasterIntClear(hwAttrs->baseAddr); - - /* Check for I2C Errors */ - if ((errStatus == I2C_MASTER_ERR_NONE) || - (object->mode == I2CCC32XX_ERROR)) { - /* No errors, now check what we need to do next */ - switch (object->mode) { - /* - * ERROR case is OK because if an Error is detected, a STOP bit is - * sent; which in turn will call another interrupt. This interrupt - * call will then post the transferComplete semaphore to unblock the - * I2C_transfer function - */ - case I2CCC32XX_ERROR: - case I2CCC32XX_IDLE_MODE: - I2CCC32XX_completeTransfer((I2C_Handle) arg); - break; - - case I2CCC32XX_WRITE_MODE: - /* Decrement write Counter */ - object->writeCountIdx--; - - /* Check if more data needs to be sent */ - if (object->writeCountIdx) { - DebugP_log3("I2C:(%p) ISR I2CCC32XX_WRITE_MODE: Data to write: " - "0x%x; To slave: 0x%x", - hwAttrs->baseAddr, - *(object->writeBufIdx), - object->currentTransaction->slaveAddress); - - /* Write data contents into data register */ - MAP_I2CMasterDataPut(hwAttrs->baseAddr, *(object->writeBufIdx)); - object->writeBufIdx++; - - if ((object->writeCountIdx < 2) && !(object->readCountIdx)) { - /* Everything has been sent, nothing to receive */ - /* Next state: Idle mode */ - object->mode = I2CCC32XX_IDLE_MODE; - - /* Send last byte with STOP bit */ - MAP_I2CMasterControl(hwAttrs->baseAddr, - I2C_MASTER_CMD_BURST_SEND_FINISH); - - DebugP_log1("I2C:(%p) ISR I2CCC32XX_WRITE_MODE: ACK received; " - "Writing w/ STOP bit", - hwAttrs->baseAddr); - } - else { - /* - * Either there is more date to be transmitted or some - * data needs to be received next - */ - MAP_I2CMasterControl(hwAttrs->baseAddr, - I2C_MASTER_CMD_BURST_SEND_CONT); - - DebugP_log1("I2C:(%p) ISR I2CCC32XX_WRITE_MODE: ACK received; " - "Writing", hwAttrs->baseAddr); - } - } - - /* At this point, we know that we need to receive data */ - else { - /* - * We need to check after we are done transmitting data, if - * we need to receive any data. - * In a corner case when we have only one byte transmitted - * and no data to receive, the I2C will automatically send - * the STOP bit. In other words, here we only need to check - * if data needs to be received. If so, how much. - */ - if (object->readCountIdx) { - /* Next state: Receive mode */ - object->mode = I2CCC32XX_READ_MODE; - - /* Switch into Receive mode */ - MAP_I2CMasterSlaveAddrSet(hwAttrs->baseAddr, - object->currentTransaction->slaveAddress, - true); - - if (object->readCountIdx > 1) { - /* Send a repeated START */ - MAP_I2CMasterControl(hwAttrs->baseAddr, - I2C_MASTER_CMD_BURST_RECEIVE_START); - - DebugP_log1("I2C:(%p) ISR I2CCC32XX_WRITE_MODE: -> " - "I2CCC32XX_READ_MODE; Reading w/ RESTART and ACK", - hwAttrs->baseAddr); - } - else { - /* - * Send a repeated START with a NACK since it's the - * last byte to be received. - * I2C_MASTER_CMD_BURST_RECEIVE_START_NACK is - * is locally defined because there is no macro to - * receive data and send a NACK after sending a - * start bit (0x00000003) - */ - MAP_I2CMasterControl(hwAttrs->baseAddr, - I2C_MASTER_CMD_BURST_RECEIVE_START_NACK); - - DebugP_log1("I2C:(%p) ISR I2CCC32XX_WRITE_MODE: -> " - "I2CCC32XX_READ_MODE; Reading w/ RESTART and NACK", - hwAttrs->baseAddr); - } - } - else { - /* Done with all transmissions */ - object->mode = I2CCC32XX_IDLE_MODE; - /* - * No more data needs to be received, so follow up with - * a STOP bit - * Again, there is no equivalent macro (0x00000004) so - * I2C_MASTER_CMD_BURST_RECEIVE_STOP is used. - */ - MAP_I2CMasterControl(hwAttrs->baseAddr, - I2C_MASTER_CMD_BURST_RECEIVE_STOP); - - DebugP_log1("I2C:(%p) ISR I2CCC32XX_WRITE_MODE: -> " - "I2CCC32XX_IDLE_MODE; Sending STOP bit", - hwAttrs->baseAddr); - } - } - break; - - case I2CCC32XX_READ_MODE: - /* Save the received data */ - *(object->readBufIdx) = MAP_I2CMasterDataGet(hwAttrs->baseAddr); - - DebugP_log2("I2C:(%p) ISR I2CCC32XX_READ_MODE: Read data byte: 0x%x", - hwAttrs->baseAddr, *(object->readBufIdx)); - - object->readBufIdx++; - - /* Check if any data needs to be received */ - object->readCountIdx--; - if (object->readCountIdx) { - if (object->readCountIdx > 1) { - /* More data to be received */ - MAP_I2CMasterControl(hwAttrs->baseAddr, - I2C_MASTER_CMD_BURST_RECEIVE_CONT); - - DebugP_log1("I2C:(%p) ISR I2CCC32XX_READ_MODE: Reading w/ ACK", - hwAttrs->baseAddr); - } - else { - /* - * Send NACK because it's the last byte to be received - * There is no NACK macro equivalent (0x00000001) so - * I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK is used - */ - MAP_I2CMasterControl(hwAttrs->baseAddr, - I2C_MASTER_CMD_BURST_RECEIVE_CONT_NACK); - - DebugP_log1("I2C:(%p) ISR I2CCC32XX_READ_MODE: Reading w/ NACK", - hwAttrs->baseAddr); - } - } - else { - /* Next state: Idle mode */ - object->mode = I2CCC32XX_IDLE_MODE; - - /* - * No more data needs to be received, so follow up with a - * STOP bit - * Again, there is no equivalent macro (0x00000004) so - * I2C_MASTER_CMD_BURST_RECEIVE_STOP is used - */ - MAP_I2CMasterControl(hwAttrs->baseAddr, - I2C_MASTER_CMD_BURST_RECEIVE_STOP); - - DebugP_log1("I2C:(%p) ISR I2CCC32XX_READ_MODE: -> I2CCC32XX_IDLE_MODE; " - "Sending STOP bit", hwAttrs->baseAddr); - } - - break; - - default: - object->mode = I2CCC32XX_ERROR; - break; - } - - } - else { - /* Error Handling */ - if ((errStatus & (I2C_MASTER_ERR_ARB_LOST | I2C_MASTER_ERR_ADDR_ACK)) || - (object->mode == I2CCC32XX_IDLE_MODE)) { - - /* STOP condition already occurred, complete transfer */ - object->mode = I2CCC32XX_ERROR; - I2CCC32XX_completeTransfer((I2C_Handle) arg); - } - else { - - /* Error occurred during a transfer, send a STOP condition */ - object->mode = I2CCC32XX_ERROR; - MAP_I2CMasterControl(hwAttrs->baseAddr, - I2C_MASTER_CMD_BURST_SEND_ERROR_STOP); - } - - DebugP_log2("I2C:(%p) ISR I2C Bus fault (Status Reg: 0x%x)", - hwAttrs->baseAddr, errStatus); - } - - return; -} - -/* - * ======== I2CCC32XX_init ======== - */ -void I2CCC32XX_init(I2C_Handle handle) -{ - /* - * Relying on ELF to set - * ((I2CCC32XX_Object *)(handle->object))->isOpen = false - */ -} - -/* - * ======== I2CCC32XX_open ======== - */ -I2C_Handle I2CCC32XX_open(I2C_Handle handle, I2C_Params *params) -{ - uintptr_t key; - I2CCC32XX_Object *object = handle->object; - I2CCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - SemaphoreP_Params semParams; - HwiP_Params hwiParams; - uint16_t pin; - uint16_t mode; - - /* Check for valid bit rate */ - DebugP_assert(params->bitRate <= I2C_400kHz); - - /* Determine if the device index was already opened */ - key = HwiP_disable(); - if(object->isOpen == true){ - HwiP_restore(key); - return (NULL); - } - - /* Mark the handle as being used */ - object->isOpen = true; - HwiP_restore(key); - - /* Save parameters */ - object->transferMode = params->transferMode; - object->transferCallbackFxn = params->transferCallbackFxn; - object->bitRate = params->bitRate; - - /* Enable the I2C module clocks */ - Power_setDependency(PowerCC32XX_PERIPH_I2CA0); - - /* In case of app restart: disable I2C module, clear interrupt at NVIC */ - MAP_I2CMasterDisable(hwAttrs->baseAddr); - HwiP_clearInterrupt(hwAttrs->intNum); - - pin = hwAttrs->clkPin & 0xff; - mode = (hwAttrs->clkPin >> 8) & 0xff; - MAP_PinTypeI2C((unsigned long)pin, (unsigned long)mode); - - pin = hwAttrs->dataPin & 0xff; - mode = (hwAttrs->dataPin >> 8) & 0xff; - MAP_PinTypeI2C((unsigned long)pin, (unsigned long)mode); - - Power_registerNotify(&(object->notifyObj), PowerCC32XX_AWAKE_LPDS, - postNotify, (uint32_t)handle); - - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t)handle; - hwiParams.priority = hwAttrs->intPriority; - object->hwiHandle = HwiP_create(hwAttrs->intNum, - I2CCC32XX_hwiFxn, - &hwiParams); - if (object->hwiHandle == NULL) { - I2CCC32XX_close(handle); - return (NULL); - } - - /* - * Create threadsafe handles for this I2C peripheral - * Semaphore to provide exclusive access to the I2C peripheral - */ - SemaphoreP_Params_init(&semParams); - semParams.mode = SemaphoreP_Mode_BINARY; - object->mutex = SemaphoreP_create(1, &semParams); - if (object->mutex == NULL) { - I2CCC32XX_close(handle); - return (NULL); - } - - /* - * Store a callback function that posts the transfer complete - * semaphore for synchronous mode - */ - if (object->transferMode == I2C_MODE_BLOCKING) { - /* - * Semaphore to cause the waiting task to block for the I2C - * to finish - */ - object->transferComplete = SemaphoreP_create(0, &semParams); - if (object->transferComplete == NULL) { - I2CCC32XX_close(handle); - return (NULL); - } - - /* Store internal callback function */ - object->transferCallbackFxn = I2CCC32XX_blockingCallback; - } - else { - /* Check to see if a callback function was defined for async mode */ - DebugP_assert(object->transferCallbackFxn != NULL); - } - - /* Specify the idle state for this I2C peripheral */ - object->mode = I2CCC32XX_IDLE_MODE; - - /* Clear the head pointer */ - object->headPtr = NULL; - object->tailPtr = NULL; - - DebugP_log1("I2C: Object created 0x%x", hwAttrs->baseAddr); - - /* Set the I2C configuration */ - initHw(handle); - - /* Return the address of the handle */ - return (handle); -} - -/* - * ======== I2CCC32XX_primeTransfer ======= - */ -static void I2CCC32XX_primeTransfer(I2CCC32XX_Object *object, - I2CCC32XX_HWAttrsV1 const *hwAttrs, - I2C_Transaction *transaction) -{ - /* Store the new internal counters and pointers */ - object->currentTransaction = transaction; - - object->writeBufIdx = transaction->writeBuf; - object->writeCountIdx = transaction->writeCount; - - object->readBufIdx = transaction->readBuf; - object->readCountIdx = transaction->readCount; - - DebugP_log2("I2C:(%p) Starting transaction to slave: 0x%x", - hwAttrs->baseAddr, - object->currentTransaction->slaveAddress); - - /* Start transfer in Transmit mode */ - if (object->writeCountIdx) { - /* Specify the I2C slave address */ - MAP_I2CMasterSlaveAddrSet(hwAttrs->baseAddr, - object->currentTransaction->slaveAddress, - false); - - /* Update the I2C mode */ - object->mode = I2CCC32XX_WRITE_MODE; - - DebugP_log3("I2C:(%p) I2CCC32XX_IDLE_MODE: Data to write: 0x%x; To Slave: 0x%x", - hwAttrs->baseAddr, *(object->writeBufIdx), - object->currentTransaction->slaveAddress); - - /* Write data contents into data register */ - MAP_I2CMasterDataPut(hwAttrs->baseAddr, *((object->writeBufIdx)++)); - - /* Start the I2C transfer in master transmit mode */ - MAP_I2CMasterControl(hwAttrs->baseAddr, I2C_MASTER_CMD_BURST_SEND_START); - - DebugP_log1("I2C:(%p) I2CCC32XX_IDLE_MODE: -> I2CCC32XX_WRITE_MODE; Writing w/ START", - hwAttrs->baseAddr); - } - - /* Start transfer in Receive mode */ - else { - /* Specify the I2C slave address */ - MAP_I2CMasterSlaveAddrSet(hwAttrs->baseAddr, - object->currentTransaction->slaveAddress, - true); - - /* Update the I2C mode */ - object->mode = I2CCC32XX_READ_MODE; - - if (object->readCountIdx < 2) { - /* Start the I2C transfer in master receive mode */ - MAP_I2CMasterControl(hwAttrs->baseAddr, - I2C_MASTER_CMD_BURST_RECEIVE_START_NACK); - - DebugP_log1("I2C:(%p) I2CCC32XX_IDLE_MODE: -> I2CCC32XX_READ_MODE; Reading w/ " - "NACK", hwAttrs->baseAddr); - } - else { - /* Start the I2C transfer in master receive mode */ - MAP_I2CMasterControl(hwAttrs->baseAddr, - I2C_MASTER_CMD_BURST_RECEIVE_START); - - DebugP_log1("I2C:(%p) I2CCC32XX_IDLE_MODE: -> I2CCC32XX_READ_MODE; Reading w/ ACK", - hwAttrs->baseAddr); - } - } -} - -/* - * ======== I2CCC32XX_transfer ======== - */ -bool I2CCC32XX_transfer(I2C_Handle handle, I2C_Transaction *transaction) -{ - uintptr_t key; - bool ret = false; - I2CCC32XX_Object *object = handle->object; - I2CCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - /* Check if anything needs to be written or read */ - if ((!transaction->writeCount) && (!transaction->readCount)) { - /* Nothing to write or read */ - return (ret); - } - - key = HwiP_disable(); - - if (object->transferMode == I2C_MODE_CALLBACK) { - /* Check if a transfer is in progress */ - if (object->headPtr) { - /* Transfer in progress */ - - /* - * Update the message pointed by the tailPtr to point to the next - * message in the queue - */ - object->tailPtr->nextPtr = transaction; - - /* Update the tailPtr to point to the last message */ - object->tailPtr = transaction; - - /* I2C is still being used */ - HwiP_restore(key); - return (true); - } - } - - /* Store the headPtr indicating I2C is in use */ - object->headPtr = transaction; - object->tailPtr = transaction; - - HwiP_restore(key); - - /* Get the lock for this I2C handle */ - if (SemaphoreP_pend(object->mutex, SemaphoreP_NO_WAIT) == SemaphoreP_TIMEOUT) { - - /* An I2C_transfer() may complete before the calling thread post the - * mutex due to preemption. We must not block in this case. */ - if (object->transferMode == I2C_MODE_CALLBACK) { - return (false); - } - - SemaphoreP_pend(object->mutex, SemaphoreP_WAIT_FOREVER); - } - - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* - * I2CCC32XX_primeTransfer is a longer process and - * protection is needed from the I2C interrupt - */ - HwiP_disableInterrupt(hwAttrs->intNum); - I2CCC32XX_primeTransfer(object, hwAttrs, transaction); - HwiP_enableInterrupt(hwAttrs->intNum); - - if (object->transferMode == I2C_MODE_BLOCKING) { - DebugP_log1("I2C:(%p) Pending on transferComplete semaphore", - hwAttrs->baseAddr); - /* - * Wait for the transfer to complete here. - * It's OK to block from here because the I2C's Hwi will unblock - * upon errors - */ - SemaphoreP_pend(object->transferComplete, SemaphoreP_WAIT_FOREVER); - - DebugP_log1("I2C:(%p) Transaction completed", - hwAttrs->baseAddr); - - /* Hwi handle has posted a 'transferComplete' check for Errors */ - if (object->mode == I2CCC32XX_IDLE_MODE) { - DebugP_log1("I2C:(%p) Transfer OK", hwAttrs->baseAddr); - ret = true; - } - } - else { - /* Always return true if in Asynchronous mode */ - ret = true; - } - - /* Release the lock for this particular I2C handle */ - SemaphoreP_post(object->mutex); - - /* Return the number of bytes transfered by the I2C */ - return (ret); -} - -/* - * ======== I2CCC32XX_blockingCallback ======== - */ -static void I2CCC32XX_blockingCallback(I2C_Handle handle, - I2C_Transaction *msg, - bool transferStatus) -{ - I2CCC32XX_Object *object = handle->object; - - DebugP_log1("I2C:(%p) posting transferComplete semaphore", - ((I2CCC32XX_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); - - /* Indicate transfer complete */ - SemaphoreP_post(object->transferComplete); -} - -/* - * ======== initHw ======== - */ -static void initHw(I2C_Handle handle) -{ - ClockP_FreqHz freq; - I2CCC32XX_Object *object = handle->object; - I2CCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uint32_t ulRegVal; - - /* - * Take I2C hardware semaphore. This is needed when coming out - * of LPDS. This is done in initHw() instead of postNotify(), in - * case no I2C is open when coming out of LPDS, so that the open() - * call will take the semaphore. - */ - ulRegVal = HWREG(0x400F7000); - ulRegVal = (ulRegVal & ~0x3) | 0x1; - HWREG(0x400F7000) = ulRegVal; - - ClockP_getCpuFreq(&freq); - MAP_I2CMasterInitExpClk(hwAttrs->baseAddr, freq.lo, - bitRate[object->bitRate]); - - /* Clear any pending interrupts */ - MAP_I2CMasterIntClear(hwAttrs->baseAddr); - - /* Enable the I2C Master for operation */ - MAP_I2CMasterEnable(hwAttrs->baseAddr); - - /* Unmask I2C interrupts */ - MAP_I2CMasterIntEnable(hwAttrs->baseAddr); -} - -/* - * ======== postNotify ======== - * This functions is called to notify the I2C driver of an ongoing transition - * out of LPDS mode. - * clientArg should be pointing to a hardware module which has already - * been opened. - */ -static int postNotify(unsigned int eventType, - uintptr_t eventArg, uintptr_t clientArg) -{ - /* Reconfigure the hardware when returning from LPDS */ - initHw((I2C_Handle)clientArg); - - return (Power_NOTIFYDONE); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/i2c/I2CCC32XX.h b/ext/hal/ti/simplelink/source/ti/drivers/i2c/I2CCC32XX.h deleted file mode 100644 index ae8d216b19f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/i2c/I2CCC32XX.h +++ /dev/null @@ -1,225 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!**************************************************************************** - * @file I2CCC32XX.h - * - * @brief I2C driver implementation for a CC32XX I2C controller. - * - * The I2C header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref I2C.h for a complete description of APIs and usage. - * - * ## Supported Bit Rates ## - * - #I2C_100kHz - * - #I2C_400kHz - * - ****************************************************************************** - */ - -#ifndef ti_drivers_i2c_I2CCC32XX__include -#define ti_drivers_i2c_I2CCC32XX__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#include -#include -#include -#include - -/* - * Macros defining possible I2C signal pin mux options - * - * The bits in the pin mode macros are as follows: - * The lower 8 bits of the macro refer to the pin, offset by 1, to match - * driverlib pin defines. For example, I2CCC32XX_PIN_01_I2C_SCL & 0xff = 0, - * which equals PIN_01 in driverlib pin.h. By matching the PIN_xx defines in - * driverlib pin.h, we can pass the pin directly to the driverlib functions. - * The upper 8 bits of the macro correspond to the pin mux confg mode - * value for the pin to operate in the I2C mode. For example, pin 1 is - * configured with mode 1 to operate as I2C_SCL. - */ -#define I2CCC32XX_PIN_01_I2C_SCL 0x100 /*!< PIN 1 is used for I2C_SCL */ -#define I2CCC32XX_PIN_02_I2C_SDA 0x101 /*!< PIN 2 is used for I2C_SDA */ -#define I2CCC32XX_PIN_03_I2C_SCL 0x502 /*!< PIN 3 is used for I2C_SCL */ -#define I2CCC32XX_PIN_04_I2C_SDA 0x503 /*!< PIN 4 is used for I2C_SDA */ -#define I2CCC32XX_PIN_05_I2C_SCL 0x504 /*!< PIN 5 is used for I2C_SCL */ -#define I2CCC32XX_PIN_06_I2C_SDA 0x505 /*!< PIN 6 is used for I2C_SDA */ -#define I2CCC32XX_PIN_16_I2C_SCL 0x90F /*!< PIN 16 is used for I2C_SCL */ -#define I2CCC32XX_PIN_17_I2C_SDA 0x910 /*!< PIN 17 is used for I2C_SDA */ - -/** - * @addtogroup I2C_STATUS - * I2CCC32XX_STATUS_* macros are command codes only defined in the - * I2CCC32XX.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add I2CCC32XX_STATUS_* macros here */ - -/** @}*/ - -/** - * @addtogroup I2C_CMD - * I2CCC32XX_CMD_* macros are command codes only defined in the - * I2CCC32XX.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add I2CCC32XX_CMD_* macros here */ - -/** @}*/ - -/* I2C function table pointer */ -extern const I2C_FxnTable I2CCC32XX_fxnTable; - -/*! - * @cond NODOC - * I2CCC32XX mode - * - * This enum defines the state of the I2C driver's state machine. - */ -typedef enum I2CCC32XX_Mode { - /*! I2C is idle, and not performing a transaction */ - I2CCC32XX_IDLE_MODE = 0, - /*! I2C is currently performing a write operation */ - I2CCC32XX_WRITE_MODE, - /*! I2C is currently performing a read operation */ - I2CCC32XX_READ_MODE, - /*! I2C error has occurred */ - I2CCC32XX_ERROR = 0xFF -} I2CCC32XX_Mode; -/*! @endcond */ - -/*! - * @brief I2CCC32XX Hardware attributes - * - * The baseAddr and intNum fields define the base address and interrupt number - * of the I2C peripheral. These values are used by driverlib APIs and - * therefore must be populated by driverlib macro definitions. These - * definitions are found in the header files: - * - inc/hw_memmap.h - * - inc/hw_ints.h - * - * intPriority is the I2C peripheral's interrupt priority. - * This driver uses the ti.dpl interface instead of making OS calls directly, - * and the corresponding HwiP port handles the interrupt priority in an - * OS-specific way. For example, in the case of the TI-RTOS kernel port, - * the intPriority is passed unmodified to Hwi_create() provided by the - * ti.sysbios.family.arm.m3.Hwi module; so the documentation for the - * ti.sysbios.family.arm.m3.Hwi module should be referenced for a description - * of usage of priority. - * - * clkPin and dataPin define the pin multiplexing to be used for the SCL and - * SDA pins, respectively. Macro values defined in this header file should - * be used for these fields. - * - * A sample structure is shown below: - * @code - * const I2CCC32XX_HWAttrsV1 i2cCC32XXHWAttrs[] = { - * { - * .baseAddr = I2CA0_BASE, - * .intNum = INT_I2CA0, - * .intPriority = (~0), - * .clkPin = I2CCC32XX_PIN_01_I2C_SCL, - * .dataPin = I2CCC32XX_PIN_02_I2C_SDA, - * } - * }; - * @endcode - */ -typedef struct I2CCC32XX_HWAttrsV1 { - /*! I2C Peripheral's base address */ - unsigned int baseAddr; - /*! I2C Peripheral's interrupt vector */ - unsigned int intNum; - /*! I2C Peripheral's interrupt priority */ - unsigned int intPriority; - /*! I2C clock pin configuration */ - uint16_t clkPin; - /*! I2C data pin configuration */ - uint16_t dataPin; -} I2CCC32XX_HWAttrsV1; - -/*! - * @cond NODOC - * I2CCC32XX Object. Applications must not access any member variables of - * this structure! - */ -typedef struct I2CCC32XX_Object { - SemaphoreP_Handle mutex; /* Grants exclusive access to I2C */ - SemaphoreP_Handle transferComplete; /* Signals I2C transfer completion */ - - HwiP_Handle hwiHandle; - - I2C_TransferMode transferMode; /* Blocking or Callback mode */ - I2C_CallbackFxn transferCallbackFxn; /* Callback function pointer */ - - volatile I2CCC32XX_Mode mode; /* Stores the I2C state */ - - I2C_Transaction *currentTransaction; /* Pointer to current transaction */ - - uint8_t *writeBufIdx; /* Internal inc. writeBuf index */ - size_t writeCountIdx; /* Internal dec. writeCounter */ - - uint8_t *readBufIdx; /* Internal inc. readBuf index */ - size_t readCountIdx; /* Internal dec. readCounter */ - - /* I2C transaction pointers for I2C_MODE_CALLBACK */ - I2C_Transaction *headPtr; /* Head ptr for queued transactions */ - I2C_Transaction *tailPtr; /* Tail ptr for queued transactions */ - - bool isOpen; /* Flag to indicate module is open */ - - Power_NotifyObj notifyObj; /* For notification of wake from LPDS */ - I2C_BitRate bitRate; /* I2C bus bit rate */ -} I2CCC32XX_Object; -/*! @endcond */ - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_i2c_I2CCC32XX__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/i2s/I2SCC32XXDMA.c b/ext/hal/ti/simplelink/source/ti/drivers/i2s/I2SCC32XXDMA.c deleted file mode 100644 index d084134fb7e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/i2s/I2SCC32XXDMA.c +++ /dev/null @@ -1,827 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif -#include -#include -#include - -#include - -#include -#include - -#include - -#include - -/* driverlib header files */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PinConfigPinMode(config) (((config) >> 8) & 0xF) -#define PinConfigPin(config) (((config) >> 0) & 0x3F) - -#define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) -#define PAD_RESET_STATE 0xC61 - -/* I2SCC32XXDMA functions */ -void I2SCC32XXDMA_close(I2S_Handle handle); -int_fast16_t I2SCC32XXDMA_control(I2S_Handle handle, uint_fast16_t cmd, - void *arg); -void I2SCC32XXDMA_init(I2S_Handle handle); -I2S_Handle I2SCC32XXDMA_open(I2S_Handle handle, I2S_Params *params); -int_fast16_t I2SCC32XXDMA_readIssue(I2S_Handle handle, I2S_BufDesc *desc); -size_t I2SCC32XXDMA_readReclaim(I2S_Handle handle, I2S_BufDesc **desc); -int_fast16_t I2SCC32XXDMA_writeIssue(I2S_Handle handle, I2S_BufDesc *desc); -size_t I2SCC32XXDMA_writeReclaim(I2S_Handle handle, I2S_BufDesc **desc); - -/* I2S function table for I2SCC32XXDMA implementation */ -const I2S_FxnTable I2SCC32XXDMA_fxnTable = { - I2SCC32XXDMA_close, - I2SCC32XXDMA_control, - I2SCC32XXDMA_init, - I2SCC32XXDMA_open, - I2SCC32XXDMA_readIssue, - I2SCC32XXDMA_readReclaim, - I2SCC32XXDMA_writeIssue, - I2SCC32XXDMA_writeReclaim -}; - -/* - * This lookup table is used to configure the DMA channels for the appropriate - * (16bit or 32bit) transfer sizes. - * Table for an I2S DMA RX channel. - */ -static const uint32_t dmaRxConfig[] = { - UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_CHCTL_DSTINC_16 | UDMA_ARB_8, - UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_CHCTL_DSTINC_32 | UDMA_ARB_8 -}; - -/* - * This lookup table is used to configure the DMA channels for the appropriate - * (16bit or 32bit) transfer sizes. - * Table for an I2 DMA TX channel - */ -static const uint32_t dmaTxConfig[] = { - UDMA_SIZE_16 | UDMA_CHCTL_SRCINC_16 | UDMA_DST_INC_NONE | UDMA_ARB_8, - UDMA_SIZE_32 | UDMA_CHCTL_SRCINC_32 | UDMA_DST_INC_NONE | UDMA_ARB_8 -}; - -/*Zero buffer to write when there is no data from the application*/ -uint8_t I2SCC32XXDMA_zeroBuffer[128]; -static I2S_BufDesc I2SCC32XXDMA_zeroBufDesc; - -/*Empty buffer to read into when there is no data requested - from the application*/ -static uint8_t I2SCC32XXDMA_emptyBuffer[128]; -static I2S_BufDesc I2SCC32XXDMA_emptyBufDesc; - - -/* - * ======== I2SCC32XXDMA_configDMA ======== - */ -static void I2SCC32XXDMA_configDMA(I2S_Handle handle, I2S_BufDesc *desc, - bool isWrite) -{ - I2SCC32XXDMA_Object *object = handle->object; - I2SCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - unsigned long channelControlOptions; - uint32_t divider = 1; - - if (object->dmaSize == I2SCC32XXDMA_16bit) { - divider = 2; - } - else if (object->dmaSize == I2SCC32XXDMA_32bit) { - divider = 4; - } - - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - - if (isWrite) { - channelControlOptions = dmaTxConfig[object->dmaSize]; - - /* Setup ping-pong transfer */ - MAP_uDMAChannelControlSet(hwAttrs->txChannelIndex, - channelControlOptions); - - MAP_uDMAChannelTransferSet(hwAttrs->txChannelIndex, - UDMA_MODE_PINGPONG, (void *)desc->bufPtr, - (void *)I2S_TX_DMA_PORT, ((desc->bufSize / 2) / divider)); - - /* Pong Buffer */ - MAP_uDMAChannelControlSet(hwAttrs->txChannelIndex | UDMA_ALT_SELECT, - channelControlOptions); - - MAP_uDMAChannelTransferSet(hwAttrs->txChannelIndex | UDMA_ALT_SELECT, - UDMA_MODE_PINGPONG, - (void *)(((char *)desc->bufPtr) + (desc->bufSize / 2)), - (void *)I2S_TX_DMA_PORT, - ((desc->bufSize / 2) / divider)); - - MAP_uDMAChannelAttributeEnable(hwAttrs->txChannelIndex, UDMA_ATTR_USEBURST); - MAP_uDMAChannelEnable(hwAttrs->txChannelIndex); - - /* Configure TX FIFO */ - MAP_I2STxFIFOEnable(hwAttrs->baseAddr,8,1); - } - else { - - /* - * TX is always required so configure TX dma - * if 'read' is called first - */ - I2SCC32XXDMA_configDMA(handle, &I2SCC32XXDMA_zeroBufDesc, true); - - channelControlOptions = dmaRxConfig[object->dmaSize]; - - /* Setup ping-pong transfer */ - MAP_uDMAChannelControlSet(hwAttrs->rxChannelIndex, - channelControlOptions); - - MAP_uDMAChannelTransferSet(hwAttrs->rxChannelIndex, - UDMA_MODE_PINGPONG, (void *)I2S_RX_DMA_PORT, - (void *)desc->bufPtr, ((desc->bufSize / 2) / divider)); - - /* Pong Buffer */ - MAP_uDMAChannelControlSet(hwAttrs->rxChannelIndex | UDMA_ALT_SELECT, - channelControlOptions); - - MAP_uDMAChannelTransferSet(hwAttrs->rxChannelIndex | UDMA_ALT_SELECT, - UDMA_MODE_PINGPONG, (void *)I2S_RX_DMA_PORT, - (void *)(((char *)desc->bufPtr) + (desc->bufSize / 2)), - ((desc->bufSize / 2) / divider)); - - MAP_uDMAChannelAttributeEnable(hwAttrs->rxChannelIndex, UDMA_ATTR_USEBURST); - MAP_uDMAChannelEnable(hwAttrs->rxChannelIndex); - - /* Configure RX FIFO */ - MAP_I2SRxFIFOEnable(hwAttrs->baseAddr,8,1); - - } - - DebugP_log1("I2S:(%p) DMA transfer enabled", hwAttrs->baseAddr); - - if (isWrite) { - DebugP_log3("I2S:(%p) DMA transmit, txBuf: %p; Count: %d", - hwAttrs->baseAddr, (uintptr_t)(desc->bufPtr), desc->bufSize); - } - else { - DebugP_log3("I2S:(%p) DMA receive, rxBuf: %p; Count: %d", - hwAttrs->baseAddr, (uintptr_t)(desc->bufPtr), desc->bufSize); - } -} - -/* - * ======== I2SCC32XXDMA_hwiIntFxn ======== - * Hwi function that processes I2S interrupts. - * - * @param(arg) The I2S_Handle for this Hwi. - */ -static void I2SCC32XXDMA_hwiIntFxn(uintptr_t arg) -{ - I2SCC32XXDMA_Object *object = ((I2S_Handle)arg)->object; - I2SCC32XXDMA_HWAttrsV1 const *hwAttrs = ((I2S_Handle)arg)->hwAttrs; - uint32_t divider = 1; - uint32_t intStatus; - - if (object->dmaSize == I2SCC32XXDMA_16bit) { - divider = 2; - } - else if (object->dmaSize == I2SCC32XXDMA_32bit) { - divider = 4; - } - - /* Read the interrupt status */ - intStatus = MAP_I2SIntStatus(hwAttrs->baseAddr); - - /* Check for TX DMA done interrupt */ - if (intStatus & I2S_STS_XDMA) { - - - /* Clear the interrupt */ - MAP_I2SIntClear(hwAttrs->baseAddr,I2S_STS_XDMA); - - /* Check if ping is over */ - if (UDMA_MODE_STOP == MAP_uDMAChannelModeGet(hwAttrs->txChannelIndex)){ - - - /* Get the next user buffer from the write queue*/ - object->currentWriteBufDesc = (I2S_BufDesc *)List_get(&object->writeActiveQueue); - - /* If no user write buffer use the zero buffer */ - if(NULL == object->currentWriteBufDesc) - { - object->currentWriteBufDesc = &I2SCC32XXDMA_zeroBufDesc; - } - - /* Setup the DMA control table entry */ - MAP_uDMAChannelTransferSet(hwAttrs->txChannelIndex, - UDMA_MODE_PINGPONG, - (void *)object->currentWriteBufDesc->bufPtr, - (void *)I2S_TX_DMA_PORT, - ((object->currentWriteBufDesc->bufSize / 2) / divider)); - - } - else { - - /* If prevWriteBufDesc points to valid user buffer release it */ - if( (NULL != object->prevWriteBufDesc) && - (object->prevWriteBufDesc != &I2SCC32XXDMA_zeroBufDesc) ){ - - object->serialPinVars[object->writeIndex].readWriteCallback( - (I2S_Handle)arg, object->prevWriteBufDesc); - } - - /* Setup the DMA control table alternate entry */ - MAP_uDMAChannelTransferSet( - hwAttrs->txChannelIndex | UDMA_ALT_SELECT, - UDMA_MODE_PINGPONG, - (void *)((char*)object->currentWriteBufDesc->bufPtr + - (object->currentWriteBufDesc->bufSize / 2)), - (void *)I2S_TX_DMA_PORT, - ((object->currentWriteBufDesc->bufSize / 2) / divider)); - - /* Save pointer to issued buffer descriptor.*/ - object->prevWriteBufDesc = object->currentWriteBufDesc; - } - - DebugP_log2("I2S:(%p) Write finished, %d bytes written", - hwAttrs->baseAddr, object->currentWriteBufDesc->bufSize); - } - - /* Check if Rx DMA done interrupt */ - if (intStatus & I2S_STS_RDMA) { - - /* Clear the read interrupt */ - MAP_I2SIntClear(hwAttrs->baseAddr,I2S_STS_RDMA); - - /* Check if ping is over */ - if (UDMA_MODE_STOP == MAP_uDMAChannelModeGet(hwAttrs->rxChannelIndex)) { - - /* Get the next user buffer from the read queue*/ - object->currentReadBufDesc = (I2S_BufDesc *)List_get(&object->readActiveQueue); - - /* If no user read buffer use the empty buffer */ - if(NULL == object->currentReadBufDesc) - { - object->currentReadBufDesc = &I2SCC32XXDMA_emptyBufDesc; - } - - - MAP_uDMAChannelTransferSet(hwAttrs->rxChannelIndex, - UDMA_MODE_PINGPONG, - (void *)I2S_RX_DMA_PORT, - (void *)object->currentReadBufDesc->bufPtr, - ((object->currentReadBufDesc->bufSize / 2) / divider)); - - } - else { - - /* If prevReadBufDesc points to valid user buffer release it */ - if( (NULL != object->prevReadBufDesc) && - (object->prevReadBufDesc != &I2SCC32XXDMA_emptyBufDesc) ){ - - object->serialPinVars[object->readIndex].readWriteCallback( - (I2S_Handle)arg, object->prevReadBufDesc); - - } - - /* Setup the DMA control table alternate entry */ - MAP_uDMAChannelTransferSet( - hwAttrs->rxChannelIndex | UDMA_ALT_SELECT, - UDMA_MODE_PINGPONG, (void *)I2S_RX_DMA_PORT, - (void *)((char*)object->currentReadBufDesc->bufPtr + - (object->currentReadBufDesc->bufSize / 2)), - ((object->currentReadBufDesc->bufSize / 2) / divider)); - - /* Save pointer to issued buffer descriptor.*/ - object->prevReadBufDesc = object->currentReadBufDesc; - } - - DebugP_log2("I2S:(%p) Read finished, %d bytes read", - hwAttrs->baseAddr, object->currentReadBufDesc->bufSize); - } -} - -/* - * ======== I2SCC32XX_Params_init ======== - */ -void I2SCC32XXDMA_Params_init(I2SCC32XXDMA_SerialPinParams *params) -{ - DebugP_assert(params != NULL); - - params->serialPinConfig[0].pinNumber = 0; - params->serialPinConfig[0].pinMode = I2S_PINMODE_TX; - params->serialPinConfig[0].inActiveConfig = - I2S_SERCONFIG_INACT_LOW_LEVEL; - - - params->serialPinConfig[1].pinNumber = 1; - params->serialPinConfig[1].pinMode = I2S_PINMODE_RX; - params->serialPinConfig[1].inActiveConfig = - I2S_SERCONFIG_INACT_LOW_LEVEL; - -} - -/* - * ======== readIssueCallback ======== - * Simple callback to post a semaphore for the issue-reclaim mode. - */ -static void readIssueCallback(I2S_Handle handle, I2S_BufDesc *desc) -{ - I2SCC32XXDMA_Object *object = handle->object; - - List_put(&object->readDoneQueue, &(desc->qElem)); - SemaphoreP_post(object->readSem); -} - -/* - * ======== writeIssueCallback ======== - * Simple callback to post a semaphore for the issue-reclaim mode. - */ -static void writeIssueCallback(I2S_Handle handle, I2S_BufDesc *desc) -{ - I2SCC32XXDMA_Object *object = handle->object; - - List_put(&object->writeDoneQueue, &(desc->qElem)); - SemaphoreP_post(object->writeSem); -} - -/* - * ======== I2SCC32XXDMA_close ======== - */ -void I2SCC32XXDMA_close(I2S_Handle handle) -{ - I2SCC32XXDMA_Object *object = handle->object; - I2SCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uint32_t padRegister; - - /* Disable I2S and interrupts. */ - MAP_I2SDisable(hwAttrs->baseAddr); - - if (object->hwiHandle) { - HwiP_delete(object->hwiHandle); - } - if (object->writeSem != NULL) { - SemaphoreP_delete(object->writeSem); - } - if (object->readSem != NULL){ - SemaphoreP_delete(object->readSem); - } - if (object->dmaHandle != NULL) { - UDMACC32XX_close(object->dmaHandle); - } - - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - - Power_releaseDependency(PowerCC32XX_PERIPH_I2S); - - /* Restore pin pads to their reset states */ - padRegister = (PinToPadGet((hwAttrs->xr0Pin) & 0x3f)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - padRegister = (PinToPadGet((hwAttrs->xr1Pin) & 0x3f)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - padRegister = (PinToPadGet((hwAttrs->clkxPin) & 0x3f)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - padRegister = (PinToPadGet((hwAttrs->clkPin) & 0x3f)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - padRegister = (PinToPadGet((hwAttrs->fsxPin) & 0x3f)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - - object->opened = false; - - DebugP_log1("I2S:(%p) closed", hwAttrs->baseAddr); -} - -/* - * ======== I2SCC32XXDMA_control ======== - * @pre Function assumes that the handle is not NULL - */ -int_fast16_t I2SCC32XXDMA_control(I2S_Handle handle, uint_fast16_t cmd, void *arg) -{ - I2SCC32XXDMA_Object *object = handle->object; - uint32_t newSize = *(uint32_t *)arg; - - switch(cmd){ - case I2SCC32XXDMA_CMD_SET_ZEROBUF_LEN: - if (newSize > 32){ - return -1; - } - I2SCC32XXDMA_zeroBufDesc.bufSize = newSize; - object->zeroWriteBufLength = newSize; - return(I2SCC32XXDMA_CMD_SET_ZEROBUF_LEN); - - case I2SCC32XXDMA_CMD_SET_EMPTYBUF_LEN: - if (newSize > 32){ - return -1; - } - I2SCC32XXDMA_emptyBufDesc.bufSize = newSize; - object->emptyReadBufLength = newSize; - return(I2SCC32XXDMA_CMD_SET_EMPTYBUF_LEN); - - default: - return (I2S_STATUS_UNDEFINEDCMD); - } -} - -/* - * ======== I2SCC32XXDMA_init ======== - */ -void I2SCC32XXDMA_init(I2S_Handle handle) -{ - I2SCC32XXDMA_Object *object = handle->object; - - object->opened = false; - - UDMACC32XX_init(); -} - -/* - * ======== I2SCC32XXDMA_open ======== - */ -I2S_Handle I2SCC32XXDMA_open(I2S_Handle handle, I2S_Params *params) -{ - uintptr_t key; - unsigned int bitClock; - unsigned int slotConfig; - I2SCC32XXDMA_Object *object = handle->object; - I2SCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - I2SCC32XXDMA_SerialPinParams *cc3200CustomParams; - SemaphoreP_Params semParams; - HwiP_Params hwiParams; - int i; - uint32_t pin; - uint32_t mode; - unsigned long i2s_data_line[] = { - I2S_DATA_LINE_0, I2S_DATA_LINE_1 - }; - I2SCC32XXDMA_SerialPinParams defaultSerialPinParams; - - cc3200CustomParams = (I2SCC32XXDMA_SerialPinParams *)params->customParams; - - /* If customParams are NULL use defaults. */ - if (!params->customParams) { - - I2SCC32XXDMA_Params_init(&defaultSerialPinParams); - cc3200CustomParams = &defaultSerialPinParams; - } - - /* Disable preemption while checking if the I2S is open. */ - key = HwiP_disable(); - - /* Check if the I2S is open already with the base addr. */ - if (object->opened == true) { - HwiP_restore(key); - - DebugP_log1("I2S:(%p) already in use.", hwAttrs->baseAddr); - return (NULL); - } - object->opened = true; - - HwiP_restore(key); - - /* Set I2S variables to defaults. */ - object->readSem = NULL; - object->writeSem = NULL; - object->writeIndex = I2SCC32XXDMA_INDEX_INVALID; - object->readIndex = I2SCC32XXDMA_INDEX_INVALID; - object->dmaHandle = NULL; - object->currentWriteBufDesc = NULL; - object->currentReadBufDesc = NULL; - - object->emptyReadBufLength = sizeof(I2SCC32XXDMA_emptyBuffer); - object->zeroWriteBufLength = sizeof(I2SCC32XXDMA_zeroBuffer); - - memset(&I2SCC32XXDMA_zeroBuffer,0,sizeof(I2SCC32XXDMA_zeroBuffer)); - - I2SCC32XXDMA_zeroBufDesc.bufPtr = &I2SCC32XXDMA_zeroBuffer; - I2SCC32XXDMA_zeroBufDesc.bufSize = object->zeroWriteBufLength; - - I2SCC32XXDMA_emptyBufDesc.bufPtr = &I2SCC32XXDMA_emptyBuffer; - I2SCC32XXDMA_emptyBufDesc.bufSize = object->emptyReadBufLength; - - object->operationMode = params->operationMode; - - /* - * Register power dependency. Keeps the clock running in SLP - * and DSLP modes. - */ - Power_setDependency(PowerCC32XX_PERIPH_I2S); - MAP_PRCMPeripheralReset(PRCM_I2S); - - pin = PinConfigPin(hwAttrs->xr0Pin); - mode = PinConfigPinMode(hwAttrs->xr0Pin); - MAP_PinTypeI2S((unsigned long)pin, (unsigned long)mode); - - pin = PinConfigPin(hwAttrs->xr1Pin); - mode = PinConfigPinMode(hwAttrs->xr1Pin); - MAP_PinTypeI2S((unsigned long)pin, (unsigned long)mode); - - pin = PinConfigPin(hwAttrs->clkxPin); - mode = PinConfigPinMode(hwAttrs->clkxPin); - MAP_PinTypeI2S((unsigned long)pin, (unsigned long)mode); - - pin = PinConfigPin(hwAttrs->clkPin); - mode = PinConfigPinMode(hwAttrs->clkPin); - MAP_PinTypeI2S((unsigned long)pin, (unsigned long)mode); - - pin = PinConfigPin(hwAttrs->fsxPin); - mode = PinConfigPinMode(hwAttrs->fsxPin); - MAP_PinTypeI2S((unsigned long)pin, (unsigned long)mode); - - for (i = 0; i < 2; i++) { - if (cc3200CustomParams->serialPinConfig[i].pinMode != - I2S_PINMODE_INACTIVE) { - - if (cc3200CustomParams->serialPinConfig[i].pinMode == - I2S_PINMODE_RX) { - - object->readIndex = i; - object->serialPinVars[i].readWriteMode = params->readMode; - object->serialPinVars[i].readWriteCallback = - params->readCallback; - object->serialPinVars[i].readWriteTimeout = params->readTimeout; - - MAP_I2SSerializerConfig(hwAttrs->baseAddr,i2s_data_line[i], - I2S_SER_MODE_RX, I2S_INACT_LOW_LEVEL); - } - else if (cc3200CustomParams->serialPinConfig[i].pinMode == - I2S_PINMODE_TX) { - - object->writeIndex = i; - object->serialPinVars[i].readWriteMode = - params->writeMode; - object->serialPinVars[i].readWriteCallback = - params->writeCallback; - object->serialPinVars[i].readWriteTimeout = - params->writeTimeout; - MAP_I2SSerializerConfig(hwAttrs->baseAddr,i2s_data_line[i], - I2S_SER_MODE_TX, I2S_INACT_LOW_LEVEL); - } - } - } - - /* Disable the I2S interrupt. */ - MAP_I2SIntDisable(hwAttrs->baseAddr,I2S_INT_XDMA | I2S_INT_RDMA); - - HwiP_clearInterrupt(hwAttrs->intNum); - - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t)handle; - hwiParams.priority = hwAttrs->intPriority; - object->hwiHandle = HwiP_create(hwAttrs->intNum, - I2SCC32XXDMA_hwiIntFxn, - &hwiParams); - if (object->hwiHandle == NULL) { - I2SCC32XXDMA_close(handle); - return (NULL); - } - - object->dmaHandle = UDMACC32XX_open(); - if (object->dmaHandle == NULL) { - I2SCC32XXDMA_close(handle); - return (NULL); - } - - MAP_I2SIntEnable(hwAttrs->baseAddr,I2S_INT_XDMA | I2S_INT_RDMA); - - if (params->operationMode == I2S_OPMODE_TX_ONLY) { - object->operationMode = I2S_MODE_TX_ONLY; - } - else if (params->operationMode == I2S_OPMODE_TX_RX_SYNC) { - object->operationMode = I2S_MODE_TX_RX_SYNC; - } - else { - I2SCC32XXDMA_close(handle); - return (NULL); - } - if (params->slotLength == 16) { - slotConfig = I2S_SLOT_SIZE_16; - object->dmaSize = I2SCC32XXDMA_16bit; - } - else if (params->slotLength == 24) { - slotConfig = I2S_SLOT_SIZE_24; - object->dmaSize = I2SCC32XXDMA_32bit; - } - else { - I2SCC32XXDMA_close(handle); - return (NULL); - } - - SemaphoreP_Params_init(&semParams); - if (object->writeIndex != I2SCC32XXDMA_INDEX_INVALID) { - /* Initialize write Queue */ - List_clearList(&object->writeActiveQueue); - - if (object->serialPinVars[object->writeIndex].readWriteMode == - I2S_MODE_ISSUERECLAIM) { - object->serialPinVars[object->writeIndex].readWriteCallback = - &writeIssueCallback; - semParams.mode = SemaphoreP_Mode_COUNTING; - - object->writeSem = SemaphoreP_create(0, &semParams); - if (object->writeSem == NULL) { - DebugP_log1("I2S:(%p) Failed to create semaphore.", - hwAttrs->baseAddr); - I2SCC32XXDMA_close(handle); - return (NULL); - } - } - - /* Initialize write Queue */ - List_clearList(&object->writeDoneQueue); - } - - if (object->readIndex != I2SCC32XXDMA_INDEX_INVALID) { - List_clearList(&object->readActiveQueue); - - if (object->serialPinVars[object->readIndex].readWriteMode == - I2S_MODE_ISSUERECLAIM) { - object->serialPinVars[object->readIndex].readWriteCallback = - &readIssueCallback; - semParams.mode = SemaphoreP_Mode_COUNTING; - object->readSem = SemaphoreP_create(0, &semParams); - - if (object->readSem == NULL) { - if (object->writeSem) { - SemaphoreP_delete(object->writeSem); - - DebugP_log1("I2S:(%p) Failed to create semaphore.", - hwAttrs->baseAddr); - I2SCC32XXDMA_close(handle); - return (NULL); - } - - /* Initialize read Queues */ - List_clearList(&object->readDoneQueue); - } - } - } - - bitClock = (params->samplingFrequency * - params->slotLength * params->numChannels); - MAP_PRCMI2SClockFreqSet(bitClock); - - MAP_I2SConfigSetExpClk(hwAttrs->baseAddr,bitClock,bitClock,slotConfig | - I2S_PORT_DMA); - - MAP_uDMAChannelAssign(hwAttrs->rxChannelIndex); - MAP_uDMAChannelAttributeDisable(hwAttrs->rxChannelIndex, - UDMA_ATTR_ALTSELECT); - - MAP_uDMAChannelAssign(hwAttrs->txChannelIndex); - MAP_uDMAChannelAttributeDisable(hwAttrs->txChannelIndex, - UDMA_ATTR_ALTSELECT); - - - /* Configure the DMA with zero/empty buffers */ - if (params->operationMode == I2S_OPMODE_TX_ONLY){ - - I2SCC32XXDMA_configDMA(handle, &I2SCC32XXDMA_zeroBufDesc,true); - } - else{ - - I2SCC32XXDMA_configDMA(handle, &I2SCC32XXDMA_emptyBufDesc,false); - } - - /* Enable the I2S */ - MAP_I2SEnable(hwAttrs->baseAddr,object->operationMode); - - - DebugP_log1("I2S:(%p) opened", hwAttrs->baseAddr); - - /* Return the handle */ - return (handle); -} - -/* - * ======== I2SCC32XXDMA_readIssue ======== - */ -int_fast16_t I2SCC32XXDMA_readIssue(I2S_Handle handle, I2S_BufDesc *desc) -{ - I2SCC32XXDMA_Object *object = handle->object; - - if (object->readIndex == I2SCC32XXDMA_INDEX_INVALID) { - return (I2S_STATUS_UNDEFINEDCMD); - } - - List_put(&object->readActiveQueue, &(desc->qElem)); - - return (0); -} - -/* - * ======== I2SCC32XXDMA_readReclaim ======== - */ -size_t I2SCC32XXDMA_readReclaim(I2S_Handle handle, I2S_BufDesc **desc) -{ - I2SCC32XXDMA_Object *object = handle->object; - size_t size = 0; - - *desc = NULL; - if (SemaphoreP_OK != SemaphoreP_pend(object->readSem, - object->serialPinVars[object->readIndex].readWriteTimeout)) { - DebugP_log1("I2S:(%p) Read timed out", - ((I2SCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); - } - else { - - *desc = (I2S_BufDesc *)List_get(&object->readDoneQueue); - - DebugP_assert(*desc != NULL); - size = (*desc)->bufSize; - } - return (size); -} - -/* - * ======== I2SCC32XXDMA_writeIssue ======== - */ -int_fast16_t I2SCC32XXDMA_writeIssue(I2S_Handle handle, I2S_BufDesc *desc) -{ - I2SCC32XXDMA_Object *object = handle->object; - - if (object->writeIndex == I2SCC32XXDMA_INDEX_INVALID) { - return (I2S_STATUS_UNDEFINEDCMD); - } - - List_put(&object->writeActiveQueue, &(desc->qElem)); - - return (0); -} - -/* - * ======== I2SCC32XXDMA_writeReclaim ======== - */ -size_t I2SCC32XXDMA_writeReclaim(I2S_Handle handle, I2S_BufDesc **desc) -{ - I2SCC32XXDMA_Object *object = handle->object; - size_t size = 0; - - *desc = NULL; - - if (SemaphoreP_OK != SemaphoreP_pend(object->writeSem, - object->serialPinVars[object->writeIndex].readWriteTimeout)) { - DebugP_log1("I2S:(%p) Write timed out", - ((I2SCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); - - } - else { - - *desc = (I2S_BufDesc *)List_get(&object->writeDoneQueue); - - DebugP_assert(*desc != NULL); - size = (*desc)->bufSize; - } - return (size); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/i2s/I2SCC32XXDMA.h b/ext/hal/ti/simplelink/source/ti/drivers/i2s/I2SCC32XXDMA.h deleted file mode 100644 index f7dd84de0fa..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/i2s/I2SCC32XXDMA.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file I2SCC32XXDMA.h - * - * @brief I2S driver implementation for a CC32XX I2S controller - * - * The I2S header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref I2S.h for a complete description of APIs & example of use. - * - * ============================================================================ - */ - -#ifndef ti_drivers_i2s_I2SCC32XXDMA__include -#define ti_drivers_i2s_I2SCC32XXDMA__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include -#include -#include -#include - -/* - * Macros defining possible I2S signal pin mux options - * - * The bits in the pin mode macros are as follows: - * The lower 8 bits of the macro refer to the pin, offset by 1, to match - * driverlib pin defines. For example, I2SCC32XXDMA_PIN_02_McAFSX & 0xff = 1, - * which equals PIN_02 in driverlib pin.h. By matching the PIN_xx defines in - * driverlib pin.h, we can pass the pin directly to the driverlib functions. - * The upper 8 bits of the macro correspond to the pin mux confg mode - * value for the pin to operate in the I2S mode. For example, pin 2 is - * configured with mode 13 to operate as McAFSX. - */ -#define I2SCC32XXDMA_PIN_02_McAFSX 0x0d01 /*!< PIN 2 is used for McAFSX */ -#define I2SCC32XXDMA_PIN_03_McACLK 0x0302 /*!< PIN 3 is used for McCLK */ -#define I2SCC32XXDMA_PIN_15_McAFSX 0x070e /*!< PIN 15 is used for McAFSX */ -#define I2SCC32XXDMA_PIN_17_McAFSX 0x0610 /*!< PIN 17 is used for McAFSX */ -#define I2SCC32XXDMA_PIN_21_McAFSX 0x0214 /*!< PIN 21 is used for McAFSX */ -#define I2SCC32XXDMA_PIN_45_McAXR0 0x062c /*!< PIN 45 is used for McXR0 */ -#define I2SCC32XXDMA_PIN_45_McAFSX 0x0c2c /*!< PIN 45 is used for McAFSX */ -#define I2SCC32XXDMA_PIN_50_McAXR0 0x0431 /*!< PIN 50 is used for McXR0 */ -#define I2SCC32XXDMA_PIN_50_McAXR1 0x0631 /*!< PIN 50 is used for McXR1 */ -#define I2SCC32XXDMA_PIN_52_McACLK 0x0233 /*!< PIN 52 is used for McCLK */ -#define I2SCC32XXDMA_PIN_52_McAXR0 0x0433 /*!< PIN 52 is used for McXR0 */ -#define I2SCC32XXDMA_PIN_53_McACLK 0x0234 /*!< PIN 53 is used for McCLK */ -#define I2SCC32XXDMA_PIN_53_McAFSX 0x0334 /*!< PIN 53 is used for McAFSX */ -#define I2SCC32XXDMA_PIN_60_McAXR1 0x063b /*!< PIN 60 is used for McXR1 */ -#define I2SCC32XXDMA_PIN_62_McACLKX 0x0d3d /*!< PIN 62 is used for McCLKX */ -#define I2SCC32XXDMA_PIN_63_McAFSX 0x073e /*!< PIN 53 is used for McAFSX */ -#define I2SCC32XXDMA_PIN_64_McAXR0 0x073f /*!< PIN 64 is used for McXR0 */ - -/** - * @addtogroup I2S_STATUS - * I2SCC32XXDMA_STATUS_* macros are command codes only defined in the - * I2SCC32XXDMA.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add I2SCC32XXDMA_STATUS_* macros here */ - -/** @}*/ - -/** - * @addtogroup I2S_CMD - * I2SCC32XXDMA_CMD_* macros are command codes only defined in the - * I2SCC32XXDMA.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -#define I2SCC32XXDMA_CMD_SET_ZEROBUF_LEN (I2S_CMD_RESERVED + 0) -#define I2SCC32XXDMA_CMD_SET_EMPTYBUF_LEN (I2S_CMD_RESERVED + 1) - -/** @}*/ - -/* BACKWARDS COMPATIBILITY */ -#define I2SCC32XXDMA_SET_ZEROBUF_LEN I2SCC32XXDMA_CMD_SET_ZEROBUF_LEN -#define I2SCC32XXDMA_SET_EMPTYBUF_LEN I2SCC32XXDMA_CMD_SET_EMPTYBUF_LEN -/* END BACKWARDS COMPATIBILITY */ - -/* Value for Invalid Index */ -#define I2SCC32XXDMA_INDEX_INVALID 0xFF - -/*Number of Serial data pins supported*/ -#define I2SCC32XXDMA_NUM_SERIAL_PINS 2 - -/*! - * @brief - * I2SCC32XXDMA data size is used to determine how to configure the - * DMA data transfers. This field is to be only used internally. - * - * I2SCC32XXDMA_16bit: txBuf and rxBuf are arrays of uint16_t elements - * I2SCC32XXDMA_32bit: txBuf and rxBuf are arrays of uint32_t elements - */ -typedef enum I2SCC32XXDMA_DataSize { - I2SCC32XXDMA_16bit = 0, - I2SCC32XXDMA_32bit = 1 -} I2SCC32XXDMA_DataSize; - - -/* I2S function table pointer */ -extern const I2S_FxnTable I2SCC32XXDMA_fxnTable; - - -/*! - * @brief I2SCC32XXDMA Hardware attributes - * - * These fields, with the exception of intPriority, - * are used by driverlib APIs and therefore must be populated by - * driverlib macro definitions. For CC32XXWare these definitions are found in: - * - inc/hw_memmap.h - * - inc/hw_ints.h - * - * intPriority is the I2S peripheral's interrupt priority, as defined by the - * underlying OS. It is passed unmodified to the underlying OS's interrupt - * handler creation code, so you need to refer to the OS documentation - * for usage. For example, for SYS/BIOS applications, refer to the - * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of - * interrupt priorities. If the driver uses the ti.dpl interface - * instead of making OS calls directly, then the HwiP port handles the - * interrupt priority in an OS specific way. In the case of the SYS/BIOS - * port, intPriority is passed unmodified to Hwi_create(). - * - * A sample structure is shown below: - * @code - * const I2SCC32XXDMA_HWAttrsV1 i2sCC32XXHWAttrs[] = { - * { - * .baseAddr = I2S_BASE, - * .intNum = INT_I2S, - * .intPriority = (~0), - * .rxChannelIndex = UDMA_CH4_I2S_RX, - * .txChannelIndex = UDMA_CH5_I2S_TX, - * .xr0Pin = I2SCC32XXDMA_PIN_64_McAXR0, - * .xr1Pin = I2SCC32XXDMA_PIN_50_McAXR1, - * .clkxPin = I2SCC32XXDMA_PIN_62_McACLKX, - * .clkPin = I2SCC32XXDMA_PIN_53_McACLK, - * .fsxPin = I2SCC32XXDMA_PIN_63_McAFSX, - * } - * }; - * @endcode - */ -typedef struct I2SCC32XXDMA_HWAttrsV1 { - /*! I2S Peripheral's base address */ - uint32_t baseAddr; - /*! I2S Peripheral's interrupt vector */ - uint32_t intNum; - /*! I2S Peripheral's interrupt priority */ - uint32_t intPriority; - /*! uDMA controlTable receive channel index */ - unsigned long rxChannelIndex; - /*! uDMA controlTable transmit channel index */ - unsigned long txChannelIndex; - /*! I2S audio port data 0 pin */ - uint16_t xr0Pin; - /*! I2S audio port data 1 pin */ - uint16_t xr1Pin; - /*! I2S audio port clock O pin */ - uint16_t clkxPin; - /*! I2S audio port data pin */ - uint16_t clkPin; - /*! I2S audio port frame sync */ - uint16_t fsxPin; -} I2SCC32XXDMA_HWAttrsV1; - -/*! - * @brief CC32XX Serial Pin Configuration - */ -typedef struct I2SCC32XXDMA_SerialPinConfig { - /*! Pin number */ - unsigned char pinNumber; - - /*! Mode the pin will operate(Rx/Tx) */ - I2S_PinMode pinMode; - - /*! Pin configuration in inactive state */ - I2S_SerInActiveConfig inActiveConfig; - -} I2SCC32XXDMA_SerialPinConfig; - -/*! - * @brief CC32XX specific I2S Parameters - */ -typedef struct I2SCC32XXDMA_SerialPinParams { - - /*! CC32XX Serial Pin Configuration */ - I2SCC32XXDMA_SerialPinConfig serialPinConfig[I2SCC32XXDMA_NUM_SERIAL_PINS]; - -} I2SCC32XXDMA_SerialPinParams; - -/*! - * @brief I2SCC32XXDMA Serial pin variables - * - * The application must not access any member variables of this structure! - */ -typedef struct I2SCC32XXDMA_SerialPinVars { - I2S_DataMode readWriteMode; - /* Pointer to read/write callback */ - I2S_Callback readWriteCallback; - /* Timeout for read/write semaphore */ - uint32_t readWriteTimeout; - -}I2SCC32XXDMA_SerialPinVars; - -/*! - * @brief I2SCC32XXDMA Object - * - * The application must not access any member variables of this structure! - */ -typedef struct I2SCC32XXDMA_Object { - /* I2S control variables */ - bool opened; /* Has the obj been opened */ - uint32_t operationMode; /* Mode of operation of I2S */ - - /* I2S serial pin variables */ - I2SCC32XXDMA_SerialPinVars serialPinVars[I2SCC32XXDMA_NUM_SERIAL_PINS]; - - uint16_t readIndex; /* read channel Index */ - uint16_t writeIndex; /* write channel Index */ - - I2SCC32XXDMA_DataSize dmaSize; /* Config DMA word size */ - - /* I2S OSAL objects */ - SemaphoreP_Handle writeSem; /* I2S write semaphore*/ - SemaphoreP_Handle readSem; /* I2S read semaphore */ - HwiP_Handle hwiHandle; - - /* Length of zero buffer to write in case of no data */ - unsigned long zeroWriteBufLength; - - /* Length of empty buffer to read in case of no data - requested */ - unsigned long emptyReadBufLength; - - /* Current Write buffer descriptor pointer */ - I2S_BufDesc *currentWriteBufDesc; - - /* Previous Write Buffer descriptor pointer */ - I2S_BufDesc *prevWriteBufDesc; - - /* Current Read buffer descriptor pointer */ - I2S_BufDesc *currentReadBufDesc; - - /* Previous Read Buffer descriptor pointer */ - I2S_BufDesc *prevReadBufDesc; - - /* UDMA */ - UDMACC32XX_Handle dmaHandle; - - /* Lists for issue-reclaim mode */ - List_List readActiveQueue; - List_List readDoneQueue; - List_List writeActiveQueue; - List_List writeDoneQueue; -} I2SCC32XXDMA_Object, *I2SCC32XXDMA_Handle; - -/*! - * @brief Function to initialize the I2S_Params struct to its defaults - * - * params->serialPinConfig[0].pinNumber = 0; - * params->serialPinConfig[0].pinMode = I2S_PINMODE_RX; - * params->serialPinConfig[0].inActiveConfig = I2S_SERCONFIG_INACT_LOW_LEVEL; - * - * params->serialPinConfig[1].pinNumber = 1; - * params->serialPinConfig[1].pinMode = I2S_PINMODE_TX; - * params->serialPinConfig[1].inActiveConfig = I2S_SERCONFIG_INACT_LOW_LEVEL; - * - * @param params Parameter structure to initialize - */ -extern void I2SCC32XXDMA_Params_init(I2SCC32XXDMA_SerialPinParams *params); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_i2s_I2SCC32XXDMA__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/device.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/device.h deleted file mode 100644 index f7281896f90..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/device.h +++ /dev/null @@ -1,762 +0,0 @@ -/* - * device.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -#ifndef __DEVICE_H__ -#define __DEVICE_H__ - - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup Device - \short Controls the behaviour of the CC31xx/CC32xx device (start/stop, events masking and obtaining specific device status) - -*/ - -/*! - - \addtogroup Device - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -/* Convert event id to event mask to be used in sl_DeviceEventMaskSet and sl_DeviceEventMaskGet */ -#define SL_DEVICE_EVENT_BIT(EventId) (SL_WLAN_VAL_2_MASK(EventId,1) ) - - - -typedef enum -{ - SL_DEVICE_EVENT_FATAL_DEVICE_ABORT = 1, - SL_DEVICE_EVENT_FATAL_DRIVER_ABORT, - SL_DEVICE_EVENT_FATAL_SYNC_LOSS, - SL_DEVICE_EVENT_FATAL_NO_CMD_ACK, - SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT, - SL_DEVICE_EVENT_RESET_REQUEST, - SL_DEVICE_EVENT_ERROR, - SL_DEVICE_EVENT_MAX - -} SlDeviceEventId_e; - -typedef struct -{ - _i16 Status; - _u16 Caller; -}SlDeviceEventResetRequest_t; - -typedef enum -{ - SL_DEVICE_SOURCE_OTHER, - SL_DEVICE_SOURCE_WLAN, - SL_DEVICE_SOURCE_NETCFG, - SL_DEVICE_SOURCE_NETAPP, - SL_DEVICE_SOURCE_SECURITY, - - SL_DEVICE_SOURCE_LAST = 0xFF /* last one */ -}SlDeviceSource_e; - -typedef struct -{ - SlDeviceSource_e Source; - _i16 Code; -}SlDeviceEventError_t; - -typedef union -{ - SlDeviceEventResetRequest_t ResetRequest; - SlDeviceEventError_t Error; -}SlDeviceEventData_u; - - - -typedef enum -{ - SL_DEVICE_RESET_REQUEST_CALLER_PROVISIONING, - SL_DEVICE_RESET_REQUEST_CALLER_PROVISIONING_EXTERNAL_CONFIGURATION, - SL_DEVICE_RESET_REQUEST_NUM_OF_CALLERS -}SlDeviceResetRequestCaller_e; - -typedef struct -{ - _u32 Id; - SlDeviceEventData_u Data; -}SlDeviceEvent_t; - -/*! - \cond DOXYGEN_REMOVE -*/ -void slcb_DeviceEvtHdlr(SlDeviceEvent_t* pEvent); -/*! - \endcond -*/ - -typedef struct -{ - _u32 Code; - _u32 Value; -} SlDeviceFatalDeviceAssert_t; - - -typedef struct -{ - _u32 Code; -} SlDeviceFatalNoCmdAck_t, SlDeviceFatalCmdTimeout_t; - - -typedef union -{ - SlDeviceFatalDeviceAssert_t DeviceAssert; - SlDeviceFatalNoCmdAck_t NoCmdAck; - SlDeviceFatalCmdTimeout_t CmdTimeout; -}SlDeviceFatalData_u; - - -typedef struct -{ - _u32 Id; - SlDeviceFatalData_u Data; -}SlDeviceFatal_t; - - - -/* - Declare the different IDs for sl_DeviceGet and sl_DeviceSet - */ -#define SL_DEVICE_GENERAL (1) -#define SL_DEVICE_IOT (4) -#define SL_DEVICE_STATUS (2) -#define SL_DEVICE_FIPS (6) -/* - Declare the different Options for SL_DEVICE_GENERAL in sl_DeviceGet and sl_DeviceSet - */ -#define SL_DEVICE_GENERAL_DATE_TIME (11) -#define SL_DEVICE_GENERAL_PERSISTENT (5) -#define SL_DEVICE_GENERAL_VERSION (12) -#define SL_DEVICE_FIPS_ZEROIZATION (20) -/* - Declare the different Options for SL_DEVICE_IOT in sl_DeviceGet and sl_DeviceSet -*/ -#define SL_DEVICE_IOT_UDID (41) - -/* Events list to mask/unmask*/ -#define SL_DEVICE_EVENT_CLASS_DEVICE (1) -#define SL_DEVICE_EVENT_CLASS_WLAN (2) -#define SL_DEVICE_EVENT_CLASS_BSD (3) -#define SL_DEVICE_EVENT_CLASS_NETAPP (4) -#define SL_DEVICE_EVENT_CLASS_NETCFG (5) -#define SL_DEVICE_EVENT_CLASS_FS (6) -#define SL_DEVICE_EVENT_CLASS_NETUTIL (7) - -/****************** SYSCONFIG ****************/ -#define SL_DEVICE_SYSCONFIG_AS_CONFIGURED (99) - -/****************** DEVICE CLASS status ****************/ -#define SL_DEVICE_EVENT_DROPPED_DEVICE_ASYNC_GENERAL_ERROR (0x00000001L) -#define SL_DEVICE_STATUS_DEVICE_SMART_CONFIG_ACTIVE (0x80000000L) - -/****************** WLAN CLASS status ****************/ -#define SL_DEVICE_EVENT_DROPPED_WLAN_WLANASYNCONNECTEDRESPONSE (0x00000001L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_WLANASYNCDISCONNECTEDRESPONSE (0x00000002L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_STA_CONNECTED (0x00000004L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_STA_DISCONNECTED (0x00000008L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_P2P_DEV_FOUND (0x00000010L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_CONNECTION_FAILED (0x00000020L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_P2P_NEG_REQ_RECEIVED (0x00000040L) -#define SL_DEVICE_EVENT_DROPPED_WLAN_RX_FILTERS (0x00000080L) - -/****************** NETAPP CLASS status ****************/ -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IPACQUIRED (0x00000001L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IPACQUIRED_V6 (0x00000002L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IP_LEASED (0x00000004L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IP_RELEASED (0x00000008L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IPV4_LOST (0x00000010L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_DHCP_ACQUIRE_TIMEOUT (0x00000020L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IP_COLLISION (0x00000040L) -#define SL_DEVICE_EVENT_DROPPED_NETAPP_IPV6_LOST (0x00000080L) - -/****************** BSD CLASS status ****************/ -#define SL_DEVICE_EVENT_DROPPED_SOCKET_TXFAILEDASYNCRESPONSE (0x00000001L) - -/****************** FS CLASS ****************/ - - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -#ifdef SL_IF_TYPE_UART -typedef struct -{ - _u32 BaudRate; - _u8 FlowControlEnable; - _u8 CommPort; -} SlDeviceUartIfParams_t; -#endif - -#ifdef SL_IF_TYPE_UART - -#define SL_DEVICE_BAUD_9600 (9600L) -#define SL_DEVICE_BAUD_14400 (14400L) -#define SL_DEVICE_BAUD_19200 (19200L) -#define SL_DEVICE_BAUD_38400 (38400L) -#define SL_DEVICE_BAUD_57600 (57600L) -#define SL_DEVICE_BAUD_115200 (115200L) -#define SL_DEVICE_BAUD_230400 (230400L) -#define SL_DEVICE_BAUD_460800 (460800L) -#define SL_DEVICE_BAUD_921600 (921600L) - -#endif - -typedef struct -{ - _u32 ChipId; - _u8 FwVersion[4]; - _u8 PhyVersion[4]; - _u8 NwpVersion[4]; - _u16 RomVersion; - _u16 Padding; -}SlDeviceVersion_t; - - -typedef struct -{ - /* time */ - _u32 tm_sec; - _u32 tm_min; - _u32 tm_hour; - /* date */ - _u32 tm_day; /* 1-31 */ - _u32 tm_mon; /* 1-12 */ - _u32 tm_year; /* YYYY 4 digits */ - _u32 tm_week_day; /* not required */ - _u32 tm_year_day; /* not required */ - _u32 reserved[3]; -}SlDateTime_t; - - - - -/******************************************************************************/ -/* Type declarations */ -/******************************************************************************/ -typedef struct -{ - _u32 ChipId; - _u32 MoreData; -}SlDeviceInitInfo_t; - -typedef void (*P_INIT_CALLBACK)(_u32 Status, SlDeviceInitInfo_t *DeviceInitInfo); - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - \brief Start the SimpleLink device - - This function initialize the communication interface, set the enable pin - of the device, and call to the init complete callback. - - \param[in] pIfHdl Opened Interface Object. In case the interface - must be opened outside the SimpleLink Driver, the - user might give the handler to be used in \n - any access of the communication interface with the - device (UART/SPI). \n - The SimpleLink driver will open an interface port - only if this parameter is null! \n - \param[in] pDevName The name of the device to open. Could be used when - the pIfHdl is null, to transfer information to the - open interface function \n - This pointer could be used to pass additional information to - sl_IfOpen in case it is required (e.g. UART com port name) - \param[in] pInitCallBack Pointer to function that would be called - on completion of the initialization process.\n - If this parameter is NULL the function is - blocked until the device initialization - is completed, otherwise the function returns - immediately. - - \return Returns the current active role (STA/AP/P2P/TAG) or an error code: - - ROLE_STA, ROLE_AP, ROLE_P2P, ROLE_TAG in case of success, - otherwise in failure one of the following is return: - - SL_ERROR_ROLE_STA_ERR (Failure to load MAC/PHY in STA role) - - SL_ERROR_ROLE_AP_ERR (Failure to load MAC/PHY in AP role) - - SL_ERROR_ROLE_P2P_ERR (Failure to load MAC/PHY in P2P role) - - SL_ERROR_CALIB_FAIL (Failure of calibration) - - SL_ERROR_FS_CORRUPTED_ERR (FS is corrupted, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram)) - - SL_ERROR_FS_ALERT_ERR (Device is locked, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram)) - - SL_ERROR_RESTORE_IMAGE_COMPLETE (Return to factory image completed, perform reset) - - SL_ERROR_ROLE_TAG_ERR (Failure to start TAG role) - - SL_ERROR_FIPS_ERR (Failure to start with FIPS mode enabled) - - SL_ERROR_GENERAL_ERR (General error during init) - - \sa sl_Stop - - \note Belongs to \ref basic_api - - \warning This function must be called before any other SimpleLink API is used, or after sl_Stop is called for reinit the device - \par Example: - - - Open interface without callback routine. The interface name and handler are - handled by the sl_IfOpen routine: - \code - if( sl_Start(NULL, NULL, NULL) < 0 ) - { - LOG("Error opening interface to device\n"); - } - \endcode -
- - - Open interface with a callback routine: - \code - void SimpleLinkInitCallback(_u32 status) - { - LOG("Handle SimpleLink Interface acording to ststus %d\n", status); - } - - void main(void) - { - if (sl_Start(NULL, NULL, SimpleLinkInitCallback) < 0) - { - LOG("Error opening interface to device\n"); - } - } - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_Start) -_i16 sl_Start(const void* pIfHdl, _i8* pDevName, const P_INIT_CALLBACK pInitCallBack); -#endif - -/*! - \brief Stop the SimpleLink device - - This function clears the enable pin of the device, closes the communication \n - interface and invokes the stop complete callback - - \param[in] Timeout Stop timeout in msec. Should be used to give the device time to finish \n - any transmission/reception that is not completed when the function was called. \n - Additional options: - - 0 Enter to hibernate immediately \n - - 0xFFFF Host waits for device's response before \n - hibernating, without timeout protection \n - - 0 < Timeout[msec] < 0xFFFF Host waits for device's response before \n - hibernating, with a defined timeout protection \n - This timeout defines the max time to wait. The NWP \n - response can be sent earlier than this timeout. - - \return Zero on success, or a negative value if an error occurred - - \sa sl_Start - - \note This API will shutdown the device and invoke the "i/f close" function regardless \n - if it was opened implicitly or explicitly. \n - It is up to the platform interface library to properly handle interface close \n - routine \n - Belongs to \ref basic_api \n - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Stop) -_i16 sl_Stop(const _u16 Timeout); -#endif - - -/*! - \brief Setting device configurations - - \param[in] DeviceSetId configuration id: - - SL_DEVICE_GENERAL - - \param[in] Option configurations option: - - SL_DEVICE_GENERAL_DATE_TIME - - SL_DEVICE_GENERAL_PERSISTENT - \param[in] ConfigLen configurations len - \param[in] pValues configurations values - - \return Zero on success, or a negative value if an error occurred - \par Persistent - SL_DEVICE_GENERAL_DATE_TIME - System Persistent (kept during hibernate only, See Note for details) \n - SL_DEVICE_GENERAL_PERSISTENT - Persistent - \sa - \note Persistency for SL_DEVICE_GENERAL_DATE_TIME - The original setted value will be kept as System Persistence.\n - The updated date and time though, will be kept during hibernate only. - \warning - \par Examples: - - - Setting device time and date example: - \code - SlDateTime_t dateTime= {0}; - dateTime.tm_day = (_u32)23; // Day of month (DD format) range 1-31 - dateTime.tm_mon = (_u32)6; // Month (MM format) in the range of 1-12 - dateTime.tm_year = (_u32)2014; // Year (YYYY format) - dateTime.tm_hour = (_u32)17; // Hours in the range of 0-23 - dateTime.tm_min = (_u32)55; // Minutes in the range of 0-59 - dateTime.tm_sec = (_u32)22; // Seconds in the range of 0-59 - sl_DeviceSet(SL_DEVICE_GENERAL, - SL_DEVICE_GENERAL_DATE_TIME, - sizeof(SlDateTime_t), - (_u8 *)(&dateTime)); - \endcode -
- - - Setting system persistent configuration:
- Sets the default system-wide configuration persistence mode. - In case true, all APIs that follow 'system configured' persistence (see persistence attribute noted per API) shall maintain the configured settings. - In case false, all calls to APIs that follow 'system configured' persistence shall be volatile. Configuration should revert to default after reset or power recycle - \code - _u8 persistent = 1; - sl_DeviceSet(SL_DEVICE_GENERAL, - SL_DEVICE_GENERAL_PERSISTENT, - sizeof(_u8), - (_u8 *)(&persistent)); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_DeviceSet) -_i16 sl_DeviceSet(const _u8 DeviceSetId ,const _u8 Option,const _u16 ConfigLen,const _u8 *pValues); -#endif - -/*! - \brief Internal function for getting device configurations - \param[in] DeviceGetId configuration id: - - SL_DEVICE_STATUS - - SL_DEVICE_GENERAL - - SL_DEVICE_IOT - - \param[out] pOption Get configurations option: - - SL_DEVICE_STATUS: - - SL_DEVICE_EVENT_CLASS_DEVICE - - SL_DEVICE_EVENT_CLASS_WLAN - - SL_DEVICE_EVENT_CLASS_BSD - - SL_DEVICE_EVENT_CLASS_NETAPP - - SL_DEVICE_EVENT_CLASS_NETCFG - - SL_DEVICE_EVENT_CLASS_FS - - SL_DEVICE_GENERAL: - - SL_DEVICE_GENERAL_VERSION - - SL_DEVICE_GENERAL_DATE_TIME - - SL_DEVICE_GENERAL_PERSISTENT - - SL_DEVICE_IOT: - - SL_DEVICE_IOT_UDID - - \param[out] pConfigLen The length of the allocated memory as input, when the - function complete, the value of this parameter would be - the len that actually read from the device.\n - If the device return length that is longer from the input - value, the function will cut the end of the returned structure - and will return SL_ESMALLBUF - \param[out] pValues Get requested configurations values - \return Zero on success, or a negative value if an error occurred - \sa - \note - \warning - \par Examples - - - Getting WLAN class status (status is always cleared on read): - \code - _u32 statusWlan; - _u8 pConfigOpt; - _u16 pConfigLen; - pConfigOpt = SL_DEVICE_EVENT_CLASS_WLAN; - pConfigLen = sizeof(_u32); - sl_DeviceGet(SL_DEVICE_STATUS,&pConfigOpt,&pConfigLen,(_u8 *)(&statusWlan)); - if (SL_DEVICE_STATUS_WLAN_STA_CONNECTED & statusWlan ) - { - printf("Device is connected\n"); - } - if (SL_DEVICE_EVENT_DROPPED_WLAN_RX_FILTERS & statusWlan ) - { - printf("RX filer event dropped\n"); - } - - \endcode -
- - - Getting version: - \code - SlDeviceVersion_t ver; - pConfigLen = sizeof(ver); - pConfigOpt = SL_DEVICE_GENERAL_VERSION; - sl_DeviceGet(SL_DEVICE_GENERAL,&pConfigOpt,&pConfigLen,(_u8 *)(&ver)); - printf("CHIP %d\nMAC 31.%d.%d.%d.%d\nPHY %d.%d.%d.%d\nNWP %d.%d.%d.%d\nROM %d\nHOST %d.%d.%d.%d\n", - ver.ChipId, - ver.FwVersion[0],ver.FwVersion[1], - ver.FwVersion[2],ver.FwVersion[3], - ver.PhyVersion[0],ver.PhyVersion[1], - ver.PhyVersion[2],ver.PhyVersion[3], - ver.NwpVersion[0],ver.NwpVersion[1],ver.NwpVersion[2],ver.NwpVersion[3], - ver.RomVersion, - SL_MAJOR_VERSION_NUM,SL_MINOR_VERSION_NUM,SL_VERSION_NUM,SL_SUB_VERSION_NUM); - - \endcode -
- - - Getting Device time and date: - \code - SlDateTime_t dateTime = {0}; - _i16 configLen = sizeof(SlDateTime_t); - _i8 configOpt = SL_DEVICE_GENERAL_DATE_TIME; - sl_DeviceGet(SL_DEVICE_GENERAL,&configOpt, &configLen,(_u8 *)(&dateTime)); - - printf("Day %d,Mon %d,Year %d,Hour %,Min %d,Sec %d\n",dateTime.tm_day,dateTime.tm_mon,dateTime.tm_year, - dateTime.tm_hour,dateTime.tm_min,dateTime.tm_sec); - \endcode - - - Getting persistency system configuration: - \code - _i16 configLen = sizeof(_u8); - _i8 configOpt = SL_DEVICE_GENERAL_PERSISTENT; - sl_DeviceGet(SL_DEVICE_GENERAL,&configOpt, &configLen,&persistent); - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_DeviceGet) -_i16 sl_DeviceGet(const _u8 DeviceGetId, _u8 *pOption,_u16 *pConfigLen, _u8 *pValues); -#endif - - -/*! - \brief Set asynchronous event mask - - Mask asynchronous events from the device.\n - Masked events do not generate asynchronous messages from the device.\n - By default - all events are active - - - - \param[in] EventClass The classification groups that the - mask is referred to. Need to be one of - the following: - - SL_DEVICE_EVENT_CLASS_DEVICE - - SL_DEVICE_EVENT_CLASS_WLAN - - SL_DEVICE_EVENT_CLASS_BSD - - SL_DEVICE_EVENT_CLASS_NETAPP - - SL_DEVICE_EVENT_CLASS_NETCFG - - SL_DEVICE_EVENT_CLASS_FS - - - \param[in] Mask Event Mask bitmap. Valid mask are (per group): - - SL_DEVICE_EVENT_CLASS_WLAN user events - - SL_WLAN_EVENT_CONNECT - - SL_WLAN_EVENT_P2P_CONNECT - - SL_WLAN_EVENT_DISCONNECT - - SL_WLAN_EVENT_P2P_DISCONNECT - - SL_WLAN_EVENT_STA_ADDED - - SL_WLAN_EVENT_STA_REMOVED - - SL_WLAN_EVENT_P2P_CLIENT_ADDED - - SL_WLAN_EVENT_P2P_CLIENT_REMOVED - - SL_WLAN_EVENT_P2P_DEVFOUND - - SL_WLAN_EVENT_P2P_REQUEST - - SL_WLAN_EVENT_P2P_CONNECTFAIL - - SL_WLAN_EVENT_PROVISIONING_STATUS - - SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED - - SL_WLAN_EVENT_RXFILTER - - - SL_DEVICE_EVENT_CLASS_DEVICE user events - - SL_DEVICE_EVENT_ERROR - - - SL_DEVICE_EVENT_CLASS_BSD user events - - SL_SOCKET_TX_FAILED_EVENT - - SL_SOCKET_ASYNC_EVENT - - - SL_DEVICE_EVENT_CLASS_NETAPP user events - - SL_NETAPP_EVENT_IPV4_ACQUIRED - - SL_NETAPP_EVENT_IPV6_ACQUIRED - - SL_NETAPP_EVENT_DHCPV4_LEASED - - SL_NETAPP_EVENT_DHCPV4_RELEASED - - SL_NETAPP_EVENT_IP_COLLISION - - SL_NETAPP_EVENT_IPV4_LOST - - SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT - - SL_NETAPP_EVENT_IPV6_LOST - - - \return Zero on success, or a negative value if an error occurred - \par Persistent System Persistent - \sa sl_DeviceEventMaskGet - - \note Belongs to \ref ext_api \n - \warning - \par Example - - - Masking connection/disconnection async events from WLAN class: - \code - sl_DeviceEventMaskSet(SL_DEVICE_EVENT_CLASS_WLAN, (SL_DEVICE_EVENT_BIT(SL_WLAN_EVENT_CONNECT) | SL_DEVICE_EVENT_BIT(SL_WLAN_EVENT_DISCONNECT) ) ); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_DeviceEventMaskSet) -_i16 sl_DeviceEventMaskSet(const _u8 EventClass ,const _u32 Mask); -#endif - -/*! - \brief Get current event mask of the device - - Return the events bit mask from the device. In case event is - masked, the device will not send that event. - - \param[in] EventClass The classification groups that the - mask is referred to. Need to be one of - the following: - - SL_DEVICE_EVENT_CLASS_GLOBAL - - SL_DEVICE_EVENT_CLASS_DEVICE - - SL_DEVICE_EVENT_CLASS_WLAN - - SL_DEVICE_EVENT_CLASS_BSD - - SL_DEVICE_EVENT_CLASS_NETAPP - - SL_DEVICE_EVENT_CLASS_NETCFG - - SL_DEVICE_EVENT_CLASS_FS - - \param[out] pMask Pointer to mask bitmap where the - value should be stored. Bitmasks are the same as in \ref sl_DeviceEventMaskSet - - \return Zero on success, or a negative value if an error occurred - - \sa sl_DeviceEventMaskSet - - \note Belongs to \ref ext_api - - \warning - \par Example - - - Getting an event mask for WLAN class: - \code - _u32 maskWlan; - sl_DeviceEventMaskGet(SL_DEVICE_EVENT_CLASS_WLAN,&maskWlan); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_DeviceEventMaskGet) -_i16 sl_DeviceEventMaskGet(const _u8 EventClass,_u32 *pMask); -#endif - - -/*! - \brief The SimpleLink task entry - - This function must be called from the main loop or from dedicated thread in - the following cases: - - Non-Os Platform - should be called from the mail loop - - Multi Threaded Platform when the user does not implement the external spawn functions - - should be called from dedicated thread allocated to the SimpleLink driver. - In this mode the function never return. - - \par parameters - None - - \return None - \sa - \note Belongs to \ref basic_api - - \warning This function must be called from a thread that is start running before - any call to other SimpleLink API -*/ -#if _SL_INCLUDE_FUNC(sl_Task) -void* sl_Task(void* pEntry); -#endif - - - - -/*! - \brief Setting the internal uart mode - - \param[in] pUartParams Pointer to the uart configuration parameter set: - - baudrate - up to 711 Kbps - - flow control - enable/disable - - comm port - the comm port number - - \return On success zero is returned, otherwise - Failed. - \par Persistent Non- Persistent - \sa - \note Belongs to \ref basic_api - - \warning This function must consider the host uart capability -*/ -#ifdef SL_IF_TYPE_UART -#if _SL_INCLUDE_FUNC(sl_DeviceUartSetMode) -_i16 sl_DeviceUartSetMode(const SlDeviceUartIfParams_t* pUartParams); -#endif -#endif - -/*! - \brief Configure SimpleLink to default state. - - The sl_WifiConfig function allows to configure the device - to a pre-configured state by sysconfig UI\ ti_drivers_net_wifi_Config.c. - The configuration of the SimpleLink Wifi is usually persistent, - and can be reconfigured at runtime. - Reconfiguration should be performed only when needed since - the process involves flash writes and might impact - system lifetime (flash write endurance) and power consumption. - - It's important to note that this is one example for a - 'restore to default state' function, - which meet the needs of this application. - User who wish to incorporate this function into he's app, - must adjust the implementation - and make sure it meets he's needs. - - \return Upon successful completion, - the function shall return 0. - In case of failure, this function would return -1. - -*/ -_i32 sl_WifiConfig(); - -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __DEVICE_H__ */ - - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/errors.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/errors.h deleted file mode 100644 index 5f010298f99..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/errors.h +++ /dev/null @@ -1,755 +0,0 @@ -/* - * errors.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -#ifndef __ERROR_H__ -#define __ERROR_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - - -#define SL_RET_CODE_OK (0L) /* Success */ - -#define SL_ERROR_GENERAL_DEVICE (-6L) /* General device error */ - -/* BSD SOCKET ERRORS CODES */ - -#define SL_ERROR_BSD_SOC_ERROR (-1L) /* Failure */ -#define SL_ERROR_BSD_EINTR (-4L) /* Interrupted system call */ -#define SL_ERROR_BSD_E2BIG (-7L) /* length too big */ -#define SL_ERROR_BSD_INEXE (-8L) /* socket command in execution */ -#define SL_ERROR_BSD_EBADF (-9L) /* Bad file number */ -#define SL_ERROR_BSD_ENSOCK (-10L) /* The system limit on the total number of open socket, has been reached */ -#define SL_ERROR_BSD_EAGAIN (-11L) /* Try again */ -#define SL_ERROR_BSD_EWOULDBLOCK SL_ERROR_BSD_EAGAIN -#define SL_ERROR_BSD_ENOMEM (-12L) /* Out of memory */ -#define SL_ERROR_BSD_EACCES (-13L) /* Permission denied */ -#define SL_ERROR_BSD_EFAULT (-14L) /* Bad address */ -#define SL_ERROR_BSD_ECLOSE (-15L) /* close socket operation failed to transmit all queued packets */ -#define SL_ERROR_BSD_EALREADY_ENABLED (-21L) /* Transceiver - Transceiver already ON. there could be only one */ -#define SL_ERROR_BSD_EINVAL (-22L) /* Invalid argument */ -#define SL_ERROR_BSD_EAUTO_CONNECT_OR_CONNECTING (-69L) /* Transceiver - During connection, connected or auto mode started */ -#define SL_ERROR_BSD_CONNECTION_PENDING (-72L) /* Transceiver - Device is connected, disconnect first to open transceiver */ -#define SL_ERROR_BSD_EUNSUPPORTED_ROLE (-86L) /* Transceiver - Trying to start when WLAN role is AP or P2P GO */ -#define SL_ERROR_BSD_EDESTADDRREQ (-89L) /* Destination address required */ -#define SL_ERROR_BSD_EPROTOTYPE (-91L) /* Protocol wrong type for socket */ -#define SL_ERROR_BSD_ENOPROTOOPT (-92L) /* Protocol not available */ -#define SL_ERROR_BSD_EPROTONOSUPPORT (-93L) /* Protocol not supported */ -#define SL_ERROR_BSD_ESOCKTNOSUPPORT (-94L) /* Socket type not supported */ -#define SL_ERROR_BSD_EOPNOTSUPP (-95L) /* Operation not supported on transport endpoint */ -#define SL_ERROR_BSD_EAFNOSUPPORT (-97L) /* Address family not supported by protocol */ -#define SL_ERROR_BSD_EADDRINUSE (-98L) /* Address already in use */ -#define SL_ERROR_BSD_EADDRNOTAVAIL (-99L) /* Cannot assign requested address */ -#define SL_ERROR_BSD_ENETUNREACH (-101L) /* Network is unreachable */ -#define SL_ERROR_BSD_ENOBUFS (-105L) /* No buffer space available */ -#define SL_ERROR_BSD_EOBUFF SL_ENOBUFS -#define SL_ERROR_BSD_EISCONN (-106L) /* Transport endpoint is already connected */ -#define SL_ERROR_BSD_ENOTCONN (-107L) /* Transport endpoint is not connected */ -#define SL_ERROR_BSD_ETIMEDOUT (-110L) /* Connection timed out */ -#define SL_ERROR_BSD_ECONNREFUSED (-111L) /* Connection refused */ -#define SL_ERROR_BSD_EALREADY (-114L) /* Non blocking connect in progress, try again */ - -/* ssl tls security start with -300 offset */ -#define SL_ERROR_BSD_ESEC_CLOSE_NOTIFY (-300L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_UNEXPECTED_MESSAGE (-310L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_BAD_RECORD_MAC (-320L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_DECRYPTION_FAILED (-321L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_RECORD_OVERFLOW (-322L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_DECOMPRESSION_FAILURE (-330L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_HANDSHAKE_FAILURE (-340L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_NO_CERTIFICATE (-341L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_BAD_CERTIFICATE (-342L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_UNSUPPORTED_CERTIFICATE (-343L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_CERTIFICATE_REVOKED (-344L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_CERTIFICATE_EXPIRED (-345L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_CERTIFICATE_UNKNOWN (-346L) /* ssl/tls alerts */ - -#define SL_ERROR_BSD_ESEC_ILLEGAL_PARAMETER (-347L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_ACCESS_DENIED (-349L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_DECODE_ERROR (-350L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_DECRYPT_ERROR1 (-351L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_EXPORT_RESTRICTION (-360L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_PROTOCOL_VERSION (-370L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_INSUFFICIENT_SECURITY (-371L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_INTERNAL_ERROR (-380L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_USER_CANCELLED (-390L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_NO_RENEGOTIATION (-400L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_UNSUPPORTED_EXTENSION (-410L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_CERTIFICATE_UNOBTAINABLE (-411L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_UNRECOGNIZED_NAME (-412L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_BAD_CERTIFICATE_STATUS_RESPONSE (-413L) /* ssl/tls alerts */ -#define SL_ERROR_BSD_ESEC_BAD_CERTIFICATE_HASH_VALUE (-414L) /* ssl/tls alerts */ -/* propriety secure */ -#define SL_ERROR_BSD_ESECGENERAL (-450L) /* error secure level general error */ -#define SL_ERROR_BSD_ESECDECRYPT (-451L) /* error secure level, decrypt recv packet fail */ -#define SL_ERROR_BSD_ESECCLOSED (-452L) /* secure layrer is closed by other size , tcp is still connected */ -#define SL_ERROR_BSD_ESECSNOVERIFY (-453L) /* Connected without server verification */ -#define SL_ERROR_BSD_ESECNOCAFILE (-454L) /* error secure level CA file not found*/ -#define SL_ERROR_BSD_ESECMEMORY (-455L) /* error secure level No memory space available */ -#define SL_ERROR_BSD_ESECBADCAFILE (-456L) /* error secure level bad CA file */ -#define SL_ERROR_BSD_ESECBADCERTFILE (-457L) /* error secure level bad Certificate file */ -#define SL_ERROR_BSD_ESECBADPRIVATEFILE (-458L) /* error secure level bad private file */ -#define SL_ERROR_BSD_ESECBADDHFILE (-459L) /* error secure level bad DH file */ -#define SL_ERROR_BSD_ESECT00MANYSSLOPENED (-460L) /* MAX SSL Sockets are opened */ -#define SL_ERROR_BSD_ESECDATEERROR (-461L) /* connected with certificate date verification error */ -#define SL_ERROR_BSD_ESECHANDSHAKETIMEDOUT (-462L) /* connection timed out due to handshake time */ -#define SL_ERROR_BSD_ESECTXBUFFERNOTEMPTY (-463L) /* cannot start ssl connection while send buffer is full */ -#define SL_ERROR_BSD_ESECRXBUFFERNOTEMPTY (-464L) /* cannot start ssl connection while recv buffer is full */ -#define SL_ERROR_BSD_ESECSSLDURINGHANDSHAKE (-465L) /* cannot use while in hanshaking */ -#define SL_ERROR_BSD_ESECNOTALLOWEDWHENLISTENING (-466L) /* the operation is not allowed when listening, do before listen*/ -#define SL_ERROR_BSD_ESECCERTIFICATEREVOKED (-467L) /* connected but on of the certificates in the chain is revoked */ -#define SL_ERROR_BSD_ESECUNKNOWNROOTCA (-468L) /* connected but the root CA used to validate the peer is unknown */ -#define SL_ERROR_BSD_ESECWRONGPEERCERT (-469L) /* wrong peer cert (server cert) was received while trying to connect to server */ -#define SL_ERROR_BSD_ESECTCPDISCONNECTEDUNCOMPLETERECORD (-470L) /* the other side disconnected the TCP layer and didn't send the whole ssl record */ - -#define SL_ERROR_BSD_ESEC_BUFFER_E (-632L) /* output buffer too small or input too large */ -#define SL_ERROR_BSD_ESEC_ALGO_ID_E (-633L) /* setting algo id error */ -#define SL_ERROR_BSD_ESEC_PUBLIC_KEY_E (-634L) /* setting public key error */ -#define SL_ERROR_BSD_ESEC_DATE_E (-635L) /* setting date validity error */ -#define SL_ERROR_BSD_ESEC_SUBJECT_E (-636L) /* setting subject name error */ -#define SL_ERROR_BSD_ESEC_ISSUER_E (-637L) /* setting issuer name error */ -#define SL_ERROR_BSD_ESEC_CA_TRUE_E (-638L) /* setting CA basic constraint true error */ -#define SL_ERROR_BSD_ESEC_EXTENSIONS_E (-639L) /* setting extensions error */ -#define SL_ERROR_BSD_ESEC_ASN_PARSE_E (-640L) /* ASN parsing error, invalid input */ -#define SL_ERROR_BSD_ESEC_ASN_VERSION_E (-641L) /* ASN version error, invalid number */ -#define SL_ERROR_BSD_ESEC_ASN_GETINT_E (-642L) /* ASN get big int error, invalid data */ -#define SL_ERROR_BSD_ESEC_ASN_RSA_KEY_E (-643L) /* ASN key init error, invalid input */ -#define SL_ERROR_BSD_ESEC_ASN_OBJECT_ID_E (-644L) /* ASN object id error, invalid id */ -#define SL_ERROR_BSD_ESEC_ASN_TAG_NULL_E (-645L) /* ASN tag error, not null */ -#define SL_ERROR_BSD_ESEC_ASN_EXPECT_0_E (-646L) /* ASN expect error, not zero */ -#define SL_ERROR_BSD_ESEC_ASN_BITSTR_E (-647L) /* ASN bit string error, wrong id */ -#define SL_ERROR_BSD_ESEC_ASN_UNKNOWN_OID_E (-648L) /* ASN oid error, unknown sum id */ -#define SL_ERROR_BSD_ESEC_ASN_DATE_SZ_E (-649L) /* ASN date error, bad size */ -#define SL_ERROR_BSD_ESEC_ASN_BEFORE_DATE_E (-650L) /* ASN date error, current date before */ -#define SL_ERROR_BSD_ESEC_ASN_AFTER_DATE_E (-651L) /* ASN date error, current date after */ -#define SL_ERROR_BSD_ESEC_ASN_SIG_OID_E (-652L) /* ASN signature error, mismatched oid */ -#define SL_ERROR_BSD_ESEC_ASN_TIME_E (-653L) /* ASN time error, unknown time type */ -#define SL_ERROR_BSD_ESEC_ASN_INPUT_E (-654L) /* ASN input error, not enough data */ -#define SL_ERROR_BSD_ESEC_ASN_SIG_CONFIRM_E (-655L) /* ASN sig error, confirm failure */ -#define SL_ERROR_BSD_ESEC_ASN_SIG_HASH_E (-656L) /* ASN sig error, unsupported hash type */ -#define SL_ERROR_BSD_ESEC_ASN_SIG_KEY_E (-657L) /* ASN sig error, unsupported key type */ -#define SL_ERROR_BSD_ESEC_ASN_DH_KEY_E (-658L) /* ASN key init error, invalid input */ -#define SL_ERROR_BSD_ESEC_ASN_NTRU_KEY_E (-659L) /* ASN ntru key decode error, invalid input */ -#define SL_ERROR_BSD_ESEC_ASN_CRIT_EXT_E (-660L) /* ASN unsupported critical extension */ -#define SL_ERROR_BSD_ESEC_ECC_BAD_ARG_E (-670L) /* ECC input argument of wrong type */ -#define SL_ERROR_BSD_ESEC_ASN_ECC_KEY_E (-671L) /* ASN ECC bad input */ -#define SL_ERROR_BSD_ESEC_ECC_CURVE_OID_E (-672L) /* Unsupported ECC OID curve type */ -#define SL_ERROR_BSD_ESEC_BAD_FUNC_ARG (-673L) /* Bad function argument provided */ -#define SL_ERROR_BSD_ESEC_NOT_COMPILED_IN (-674L) /* Feature not compiled in */ -#define SL_ERROR_BSD_ESEC_UNICODE_SIZE_E (-675L) /* Unicode password too big */ -#define SL_ERROR_BSD_ESEC_NO_PASSWORD (-676L) /* no password provided by user */ -#define SL_ERROR_BSD_ESEC_ALT_NAME_E (-677L) /* alt name size problem, too big */ -#define SL_ERROR_BSD_ESEC_ASN_NO_SIGNER_E (-688L) /* ASN no signer to confirm failure */ -#define SL_ERROR_BSD_ESEC_ASN_CRL_CONFIRM_E (-689L) /* ASN CRL signature confirm failure */ -#define SL_ERROR_BSD_ESEC_ASN_CRL_NO_SIGNER_E (-690L) /* ASN CRL no signer to confirm failure */ -#define SL_ERROR_BSD_ESEC_ASN_OCSP_CONFIRM_E (-691L) /* ASN OCSP signature confirm failure */ -#define SL_ERROR_BSD_ESEC_VERIFY_FINISHED_ERROR (-704L) /* verify problem on finished */ -#define SL_ERROR_BSD_ESEC_VERIFY_MAC_ERROR (-705L) /* verify mac problem */ -#define SL_ERROR_BSD_ESEC_PARSE_ERROR (-706L) /* parse error on header */ -#define SL_ERROR_BSD_ESEC_UNKNOWN_HANDSHAKE_TYPE (-707L) /* weird handshake type */ -#define SL_ERROR_BSD_ESEC_SOCKET_ERROR_E (-708L) /* error state on socket */ -#define SL_ERROR_BSD_ESEC_SOCKET_NODATA (-709L) /* expected data, not there */ -#define SL_ERROR_BSD_ESEC_INCOMPLETE_DATA (-710L) /* don't have enough data to complete task */ -#define SL_ERROR_BSD_ESEC_UNKNOWN_RECORD_TYPE (-711L) /* unknown type in record hdr */ -#define SL_ERROR_BSD_ESEC_INNER_DECRYPT_ERROR (-712L) /* error during decryption */ -#define SL_ERROR_BSD_ESEC_FATAL_ERROR (-713L) /* recvd alert fatal error */ -#define SL_ERROR_BSD_ESEC_ENCRYPT_ERROR (-714L) /* error during encryption */ -#define SL_ERROR_BSD_ESEC_FREAD_ERROR (-715L) /* fread problem */ -#define SL_ERROR_BSD_ESEC_NO_PEER_KEY (-716L) /* need peer's key */ -#define SL_ERROR_BSD_ESEC_NO_PRIVATE_KEY (-717L) /* need the private key */ -#define SL_ERROR_BSD_ESEC_RSA_PRIVATE_ERROR (-718L) /* error during rsa priv op */ -#define SL_ERROR_BSD_ESEC_NO_DH_PARAMS (-719L) /* server missing DH params */ -#define SL_ERROR_BSD_ESEC_BUILD_MSG_ERROR (-720L) /* build message failure */ -#define SL_ERROR_BSD_ESEC_BAD_HELLO (-721L) /* client hello malformed */ -#define SL_ERROR_BSD_ESEC_DOMAIN_NAME_MISMATCH (-722L) /* peer subject name mismatch */ -#define SL_ERROR_BSD_ESEC_WANT_READ (-723L) /* want read, call again */ -#define SL_ERROR_BSD_ESEC_NOT_READY_ERROR (-724L) /* handshake layer not ready */ -#define SL_ERROR_BSD_ESEC_PMS_VERSION_ERROR (-725L) /* pre m secret version error */ -#define SL_ERROR_BSD_ESEC_WANT_WRITE (-727L) /* want write, call again */ -#define SL_ERROR_BSD_ESEC_BUFFER_ERROR (-728L) /* malformed buffer input */ -#define SL_ERROR_BSD_ESEC_VERIFY_CERT_ERROR (-729L) /* verify cert error */ -#define SL_ERROR_BSD_ESEC_VERIFY_SIGN_ERROR (-730L) /* verify sign error */ -#define SL_ERROR_BSD_ESEC_LENGTH_ERROR (-741L) /* record layer length error */ -#define SL_ERROR_BSD_ESEC_PEER_KEY_ERROR (-742L) /* can't decode peer key */ -#define SL_ERROR_BSD_ESEC_ZERO_RETURN (-743L) /* peer sent close notify */ -#define SL_ERROR_BSD_ESEC_SIDE_ERROR (-744L) /* wrong client/server type */ -#define SL_ERROR_BSD_ESEC_NO_PEER_CERT (-745L) /* peer didn't send key */ -#define SL_ERROR_BSD_ESEC_ECC_CURVETYPE_ERROR (-750L) /* Bad ECC Curve Type */ -#define SL_ERROR_BSD_ESEC_ECC_CURVE_ERROR (-751L) /* Bad ECC Curve */ -#define SL_ERROR_BSD_ESEC_ECC_PEERKEY_ERROR (-752L) /* Bad Peer ECC Key */ -#define SL_ERROR_BSD_ESEC_ECC_MAKEKEY_ERROR (-753L) /* Bad Make ECC Key */ -#define SL_ERROR_BSD_ESEC_ECC_EXPORT_ERROR (-754L) /* Bad ECC Export Key */ -#define SL_ERROR_BSD_ESEC_ECC_SHARED_ERROR (-755L) /* Bad ECC Shared Secret */ -#define SL_ERROR_BSD_ESEC_NOT_CA_ERROR (-757L) /* Not a CA cert error */ -#define SL_ERROR_BSD_ESEC_BAD_PATH_ERROR (-758L) /* Bad path for opendir */ -#define SL_ERROR_BSD_ESEC_BAD_CERT_MANAGER_ERROR (-759L) /* Bad Cert Manager */ -#define SL_ERROR_BSD_ESEC_OCSP_CERT_REVOKED (-760L) /* OCSP Certificate revoked */ -#define SL_ERROR_BSD_ESEC_CRL_CERT_REVOKED (-761L) /* CRL Certificate revoked */ -#define SL_ERROR_BSD_ESEC_CRL_MISSING (-762L) /* CRL Not loaded */ -#define SL_ERROR_BSD_ESEC_MONITOR_RUNNING_E (-763L) /* CRL Monitor already running */ -#define SL_ERROR_BSD_ESEC_THREAD_CREATE_E (-764L) /* Thread Create Error */ -#define SL_ERROR_BSD_ESEC_OCSP_NEED_URL (-765L) /* OCSP need an URL for lookup */ -#define SL_ERROR_BSD_ESEC_OCSP_CERT_UNKNOWN (-766L) /* OCSP responder doesn't know */ -#define SL_ERROR_BSD_ESEC_OCSP_LOOKUP_FAIL (-767L) /* OCSP lookup not successful */ -#define SL_ERROR_BSD_ESEC_MAX_CHAIN_ERROR (-768L) /* max chain depth exceeded */ -#define SL_ERROR_BSD_ESEC_NO_PEER_VERIFY (-778L) /* Need peer cert verify Error */ -#define SL_ERROR_BSD_ESEC_UNSUPPORTED_SUITE (-790L) /* unsupported cipher suite */ -#define SL_ERROR_BSD_ESEC_MATCH_SUITE_ERROR (-791L) /* can't match cipher suite */ - - -/* WLAN ERRORS CODES*/ -#define SL_ERROR_WLAN_KEY_ERROR (-2049L) -#define SL_ERROR_WLAN_INVALID_ROLE (-2050L) -#define SL_ERROR_WLAN_PREFERRED_NETWORKS_FILE_LOAD_FAILED (-2051L) -#define SL_ERROR_WLAN_CANNOT_CONFIG_SCAN_DURING_PROVISIONING (-2052L) -#define SL_ERROR_WLAN_INVALID_SECURITY_TYPE (-2054L) -#define SL_ERROR_WLAN_PASSPHRASE_TOO_LONG (-2055L) -#define SL_ERROR_WLAN_EAP_WRONG_METHOD (-2057L) -#define SL_ERROR_WLAN_PASSWORD_ERROR (-2058L) -#define SL_ERROR_WLAN_EAP_ANONYMOUS_LEN_ERROR (-2059L) -#define SL_ERROR_WLAN_SSID_LEN_ERROR (-2060L) -#define SL_ERROR_WLAN_USER_ID_LEN_ERROR (-2061L) -#define SL_ERROR_WLAN_PREFERRED_NETWORK_LIST_FULL (-2062L) -#define SL_ERROR_WLAN_PREFERRED_NETWORKS_FILE_WRITE_FAILED (-2063L) -#define SL_ERROR_WLAN_ILLEGAL_WEP_KEY_INDEX (-2064L) -#define SL_ERROR_WLAN_INVALID_DWELL_TIME_VALUES (-2065L) -#define SL_ERROR_WLAN_INVALID_POLICY_TYPE (-2066L) -#define SL_ERROR_WLAN_PM_POLICY_INVALID_OPTION (-2067L) -#define SL_ERROR_WLAN_PM_POLICY_INVALID_PARAMS (-2068L) -#define SL_ERROR_WLAN_WIFI_NOT_CONNECTED (-2069L) -#define SL_ERROR_WLAN_ILLEGAL_CHANNEL (-2070L) -#define SL_ERROR_WLAN_WIFI_ALREADY_DISCONNECTED (-2071L) -#define SL_ERROR_WLAN_TRANSCEIVER_ENABLED (-2072L) -#define SL_ERROR_WLAN_GET_NETWORK_LIST_EAGAIN (-2073L) -#define SL_ERROR_WLAN_GET_PROFILE_INVALID_INDEX (-2074L) -#define SL_ERROR_WLAN_FAST_CONN_DATA_INVALID (-2075L) -#define SL_ERROR_WLAN_NO_FREE_PROFILE (-2076L) -#define SL_ERROR_WLAN_AP_SCAN_INTERVAL_TOO_LOW (-2077L) -#define SL_ERROR_WLAN_SCAN_POLICY_INVALID_PARAMS (-2078L) - -#define SL_RXFL_OK (0L) /* O.K */ -#define SL_ERROR_RXFL_RANGE_COMPARE_PARAMS_ARE_INVALID (-2079L) -#define SL_ERROR_RXFL_RXFL_INVALID_PATTERN_LENGTH (-2080L) /* requested length for L1/L4 payload matching must not exceed 16 bytes */ -#define SL_ERROR_RXFL_ACTION_USER_EVENT_ID_TOO_BIG (-2081L) /* user action id for host event must not exceed SL_WLAN_RX_FILTER_MAX_USER_EVENT_ID */ -#define SL_ERROR_RXFL_OFFSET_TOO_BIG (-2082L) /* requested offset for L1/L4 payload matching must not exceed 1535 bytes */ -#define SL_ERROR_RXFL_STAT_UNSUPPORTED (-2083L) /* get rx filters statistics not supported */ -#define SL_ERROR_RXFL_INVALID_FILTER_ARG_UPDATE (-2084L) /* invalid filter args request */ -#define SL_ERROR_RXFL_INVALID_SYSTEM_STATE_TRIGGER_FOR_FILTER_TYPE (-2085L) /* system state not supported for this filter type */ -#define SL_ERROR_RXFL_INVALID_FUNC_ID_FOR_FILTER_TYPE (-2086L) /* function id not supported for this filter type */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_3 (-2087L) /* filter parent doesn't exist */ -#define SL_ERROR_RXFL_OUTPUT_OR_INPUT_BUFFER_LENGTH_TOO_SMALL (-2088L) /* ! The output buffer length is smaller than required for that operation */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_SOFTWARE_FILTER_NOT_FIT (-2089L) /* Node filter can't be child of software filter and vice_versa */ -#define SL_ERROR_RXFL_DEPENDENCY_IS_NOT_PERSISTENT (-2090L) /* Dependency filter is not persistent */ -#define SL_ERROR_RXFL_RXFL_ALLOCATION_PROBLEM (-2091L) -#define SL_ERROR_RXFL_SYSTEM_STATE_NOT_SUPPORTED_FOR_THIS_FILTER (-2092L) /* System state is not supported */ -#define SL_ERROR_RXFL_TRIGGER_USE_REG5_TO_REG8 (-2093L) /* Only counters 5 - 8 are allowed, for Tigger */ -#define SL_ERROR_RXFL_TRIGGER_USE_REG1_TO_REG4 (-2094L) /* Only counters 1 - 4 are allowed, for trigger */ -#define SL_ERROR_RXFL_ACTION_USE_REG5_TO_REG8 (-2095L) /* Only counters 5 - 8 are allowed, for action */ -#define SL_ERROR_RXFL_ACTION_USE_REG1_TO_REG4 (-2096L) /* Only counters 1 - 4 are allowed, for action */ -#define SL_ERROR_RXFL_FIELD_SUPPORT_ONLY_EQUAL_AND_NOTEQUAL (-2097L) /* Rule compare function Id is out of range */ -#define SL_ERROR_RXFL_WRONG_MULTICAST_BROADCAST_ADDRESS (-2098L) /* The address should be of type mutlicast or broadcast */ -#define SL_ERROR_RXFL_THE_FILTER_IS_NOT_OF_HEADER_TYPE (-2099L) /* The filter should be of header type */ -#define SL_ERROR_RXFL_WRONG_COMPARE_FUNC_FOR_BROADCAST_ADDRESS (-2100L) /* The compare funcion is not suitable for broadcast address */ -#define SL_ERROR_RXFL_WRONG_MULTICAST_ADDRESS (-2101L) /* The address should be of muticast type */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_IS_NOT_PERSISTENT (-2102L) /* The dependency filter is not persistent */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_IS_NOT_ENABLED (-2103L) /* The dependency filter is not enabled */ -#define SL_ERROR_RXFL_FILTER_HAS_CHILDS (-2104L) /* The filter has childs and can't be removed */ -#define SL_ERROR_RXFL_CHILD_IS_ENABLED (-2105L) /* Can't disable filter while the child is enabled */ -#define SL_ERROR_RXFL_DEPENDENCY_IS_DISABLED (-2106L) /* Can't enable filetr in case its depndency filter is disabled */ -#define SL_ERROR_RXFL_MAC_SEND_MATCHDB_FAILED (-2107L) -#define SL_ERROR_RXFL_MAC_SEND_ARG_DB_FAILED (-2108L) -#define SL_ERROR_RXFL_MAC_SEND_NODEDB_FAILED (-2109L) -#define SL_ERROR_RXFL_MAC_OPERTATION_RESUME_FAILED (-2110L) -#define SL_ERROR_RXFL_MAC_OPERTATION_HALT_FAILED (-2111L) -#define SL_ERROR_RXFL_NUMBER_OF_CONNECTION_POINTS_EXCEEDED (-2112L) /* Number of connection points exceeded */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_DEPENDENCY_ACTION_IS_DROP (-2113L) /* The dependent filter has Drop action, thus the filter can't be created */ -#define SL_ERROR_RXFL_FILTER_DO_NOT_EXISTS (-2114L) /* The filter doesn't exists */ -#define SL_ERROR_RXFL_DEPEDENCY_NOT_ON_THE_SAME_LAYER (-2115L) /* The filter and its dependency must be on the same layer */ -#define SL_ERROR_RXFL_NUMBER_OF_ARGS_EXCEEDED (-2116L) /* Number of arguments excceded */ -#define SL_ERROR_RXFL_ACTION_NO_REG_NUMBER (-2117L) /* Action require counter number */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_LAYER_DO_NOT_FIT (-2118L) /* the filter and its dependency should be from the same layer */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_SYSTEM_STATE_DO_NOT_FIT (-2119L) /* The filter and its dependency system state don't fit */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_2 (-2120L) /* The parent filter don't exist */ -#define SL_ERROR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_1 (-2121L) /* The parent filter is null */ -#define SL_ERROR_RXFL_RULE_HEADER_ACTION_TYPE_NOT_SUPPORTED (-2122L) /* The action type is not supported */ -#define SL_ERROR_RXFL_RULE_HEADER_TRIGGER_COMPARE_FUNC_OUT_OF_RANGE (-2123L) /* The Trigger comparision function is out of range */ -#define SL_ERROR_RXFL_RULE_HEADER_TRIGGER_OUT_OF_RANGE (-2124L) /* The Trigger is out of range */ -#define SL_ERROR_RXFL_RULE_HEADER_COMPARE_FUNC_OUT_OF_RANGE (-2125L) /* The rule compare function is out of range */ -#define SL_ERROR_RXFL_FRAME_TYPE_NOT_SUPPORTED (-2126L) /* ASCII frame type string is illegal */ -#define SL_ERROR_RXFL_RULE_FIELD_ID_NOT_SUPPORTED (-2127L) /* Rule field ID is out of range */ -#define SL_ERROR_RXFL_RULE_HEADER_FIELD_ID_ASCII_NOT_SUPPORTED (-2128L) /* This ASCII field ID is not supported */ -#define SL_ERROR_RXFL_RULE_HEADER_NOT_SUPPORTED (-2129L) /* The header rule is not supported on current release */ -#define SL_ERROR_RXFL_RULE_HEADER_OUT_OF_RANGE (-2130L) /* The header rule is out of range */ -#define SL_ERROR_RXFL_RULE_HEADER_COMBINATION_OPERATOR_OUT_OF_RANGE (-2131L) /* Combination function Id is out of ramge */ -#define SL_ERROR_RXFL_RULE_HEADER_FIELD_ID_OUT_OF_RANGE (-2132L) /* rule field Id is out of range */ -#define SL_ERROR_RXFL_UPDATE_NOT_SUPPORTED (-2133L) /* Update not supported */ -#define SL_ERROR_RXFL_NO_FILTER_DATABASE_ALLOCATE (-2134L) -#define SL_ERROR_RXFL_ALLOCATION_FOR_GLOBALS_STRUCTURE_FAILED (-2135L) -#define SL_ERROR_RXFL_ALLOCATION_FOR_DB_NODE_FAILED (-2136L) -#define SL_ERROR_RXFL_READ_FILE_FILTER_ID_ILLEGAL (-2137L) -#define SL_ERROR_RXFL_READ_FILE_NUMBER_OF_FILTER_FAILED (-2138L) -#define SL_ERROR_RXFL_READ_FILE_FAILED (-2139L) -#define SL_ERROR_RXFL_NO_FILTERS_ARE_DEFINED (-2140L) /* No filters are defined in the system */ -#define SL_ERROR_RXFL_NUMBER_OF_FILTER_EXCEEDED (-2141L) /* Number of max filters excceded */ -#define SL_ERROR_RXFL_BAD_FILE_MODE (-2142L) -#define SL_ERROR_RXFL_FAILED_READ_NVFILE (-2143L) -#define SL_ERROR_RXFL_FAILED_INIT_STORAGE (-2144L) -#define SL_ERROR_RXFL_CONTINUE_WRITE_MUST_BE_MOD_4 (-2145L) -#define SL_ERROR_RXFL_FAILED_LOAD_FILE (-2146L) -#define SL_ERROR_RXFL_INVALID_HANDLE (-2147L) -#define SL_ERROR_RXFL_FAILED_TO_WRITE (-2148L) -#define SL_ERROR_RXFL_OFFSET_OUT_OF_RANGE (-2149L) -#define SL_ERROR_RXFL_ALLOC (-2150L) -#define SL_ERROR_RXFL_READ_DATA_LENGTH (-2151L) -#define SL_ERROR_RXFL_INVALID_FILE_ID (-2152L) -#define SL_ERROR_RXFL_FILE_FILTERS_NOT_EXISTS (-2153L) -#define SL_ERROR_RXFL_FILE_ALREADY_IN_USE (-2154L) -#define SL_ERROR_RXFL_INVALID_ARGS (-2155L) -#define SL_ERROR_RXFL_FAILED_TO_CREATE_FILE (-2156L) -#define SL_ERROR_RXFL_FS_ALREADY_LOADED (-2157L) -#define SL_ERROR_RXFL_UNKNOWN (-2158L) -#define SL_ERROR_RXFL_FAILED_TO_CREATE_LOCK_OBJ (-2159L) -#define SL_ERROR_RXFL_DEVICE_NOT_LOADED (-2160L) -#define SL_ERROR_RXFL_INVALID_MAGIC_NUM (-2161L) -#define SL_ERROR_RXFL_FAILED_TO_READ (-2162L) -#define SL_ERROR_RXFL_NOT_SUPPORTED (-2163L) -#define SL_ERROR_WLAN_INVALID_COUNTRY_CODE (-2164L) -#define SL_ERROR_WLAN_NVMEM_ACCESS_FAILED (-2165L) -#define SL_ERROR_WLAN_OLD_FILE_VERSION (-2166L) -#define SL_ERROR_WLAN_TX_POWER_OUT_OF_RANGE (-2167L) -#define SL_ERROR_WLAN_INVALID_AP_PASSWORD_LENGTH (-2168L) -#define SL_ERROR_WLAN_PROVISIONING_ABORT_PROVISIONING_ALREADY_STARTED (-2169L) -#define SL_ERROR_WLAN_PROVISIONING_ABORT_HTTP_SERVER_DISABLED (-2170L) -#define SL_ERROR_WLAN_PROVISIONING_ABORT_PROFILE_LIST_FULL (-2171L) -#define SL_ERROR_WLAN_PROVISIONING_ABORT_INVALID_PARAM (-2172L) -#define SL_ERROR_WLAN_PROVISIONING_ABORT_GENERAL_ERROR (-2173L) -#define SL_ERROR_WLAN_MULTICAST_EXCEED_MAX_ADDR (-2174L) -#define SL_ERROR_WLAN_MULTICAST_INVAL_ADDR (-2175L) -#define SL_ERROR_WLAN_AP_SCAN_INTERVAL_TOO_SHORT (-2176L) -#define SL_ERROR_WLAN_PROVISIONING_CMD_NOT_EXPECTED (-2177L) - - -#define SL_ERROR_WLAN_AP_ACCESS_LIST_NO_ADDRESS_TO_DELETE (-2178L) /* List is empty, no address to delete */ -#define SL_ERROR_WLAN_AP_ACCESS_LIST_FULL (-2179L) /* access list is full */ -#define SL_ERROR_WLAN_AP_ACCESS_LIST_DISABLED (-2180L) /* access list is disabled */ -#define SL_ERROR_WLAN_AP_ACCESS_LIST_MODE_NOT_SUPPORTED (-2181L) /* Trying to switch to unsupported mode */ -#define SL_ERROR_WLAN_AP_STA_NOT_FOUND (-2182L) /* trying to disconnect station which is not connected */ -#define SL_ERROR_WLAN_DMS_REQUEST_DENIED (-2185L) /* Warning - DMS request was denied (IGMP process succeeded) */ -#define SL_ERROR_WLAN_DMS_REQUEST_TIMEOUT (-2186L) /* Warning - DMS request was timed out (IGMP process succeeded) */ -#define SL_ERROR_WLAN_DMS_NOT_SUPPORTED_BY_AP (-2187L) /* Warning - AP does not support DMS (IGMP process succeeded) */ - -/* DEVICE ERRORS CODES*/ -#define SL_ERROR_SUPPLICANT_ERROR (-4097L) -#define SL_ERROR_HOSTAPD_INIT_FAIL (-4098L) -#define SL_ERROR_HOSTAPD_INIT_IF_FAIL (-4099L) -#define SL_ERROR_WLAN_DRV_INIT_FAIL (-4100L) -#define SL_ERROR_FS_FILE_TABLE_LOAD_FAILED (-4102L) /* init file system failed */ -#define SL_ERROR_MDNS_ENABLE_FAIL (-4103L) /* mDNS enable failed */ -#define SL_ERROR_ROLE_STA_ERR (-4107L) /* Failure to load MAC/PHY in STA role */ -#define SL_ERROR_ROLE_AP_ERR (-4108L) /* Failure to load MAC/PHY in AP role */ -#define SL_ERROR_ROLE_P2P_ERR (-4109L) /* Failure to load MAC/PHY in P2P role */ -#define SL_ERROR_CALIB_FAIL (-4110L) /* Failure of calibration */ -#define SL_ERROR_FS_CORRUPTED_ERR (-4111L) /* FS is corrupted, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram) */ -#define SL_ERROR_FS_ALERT_ERR (-4112L) /* Device is locked, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram) */ -#define SL_ERROR_RESTORE_IMAGE_COMPLETE (-4113L) /* Return to factory image completed, perform reset */ -#define SL_ERROR_UNKNOWN_ERR (-4114L) -#define SL_ERROR_GENERAL_ERR (-4115L) /* General error during init */ -#define SL_ERROR_WRONG_ROLE (-4116L) -#define SL_ERROR_INCOMPLETE_PROGRAMMING (-4117L) /* Error during programming, Program new image should be invoked (see sl_FsProgram) */ - - -#define SL_ERROR_PENDING_TXRX_STOP_TIMEOUT_EXP (-4118L) /* Timeout expired before completing all TX\RX */ -#define SL_ERROR_PENDING_TXRX_NO_TIMEOUT (-4119L) /* No Timeout , still have pending TX\RX */ -#define SL_ERROR_INVALID_PERSISTENT_CONFIGURATION (-4120L) /* persistency configuration can only be set to 0 (disabled) or 1 (enabled) */ -#define SL_ERROR_ROLE_TAG_ERR (-4121L) /* Failure to start device in TAG role */ -#define SL_ERROR_FIPS_ERR (-4122L) /* Failure to start with FIPS mode enabled */ -/* NETAPP ERRORS CODES*/ -#define SL_ERROR_MDNS_CREATE_FAIL (-6145L) /* mDNS create failed */ -#define SL_ERROR_DEVICE_NAME_LEN_ERR (-6146L) /* Set Dev name error codes */ -#define SL_ERROR_DEVICE_NAME_INVALID (-6147L) /* Set Dev name error codes */ -#define SL_ERROR_DOMAIN_NAME_LEN_ERR (-6148L) /* Set domain name error codes */ -#define SL_ERROR_DOMAIN_NAME_INVALID (-6149L) /* Set domain name error codes */ -#define SL_ERROR_NET_APP_DNS_QUERY_NO_RESPONSE (-6150L) /* DNS query failed, no response */ -#define SL_ERROR_NET_APP_DNS_ERROR (-6151L) /* DNS internal error */ -#define SL_ERROR_NET_APP_DNS_NO_SERVER (-6152L) /* No DNS server was specified */ -#define SL_ERROR_NET_APP_DNS_TIMEOUTR (-6153L) /* mDNS parameters error */ -#define SL_ERROR_NET_APP_DNS_QUERY_FAILED (-6154L) /* DNS query failed; no DNS server sent an 'answer' */ -#define SL_ERROR_NET_APP_DNS_BAD_ADDRESS_ERROR (-6155L) /* Improperly formatted IPv4 or IPv6 address */ -#define SL_ERROR_NET_APP_DNS_SIZE_ERROR (-6156L) /* DNS destination size is too small */ -#define SL_ERROR_NET_APP_DNS_MALFORMED_PACKET (-6157L) /* Improperly formed or corrupted DNS packet received */ -#define SL_ERROR_NET_APP_DNS_BAD_ID_ERROR (-6158L) /* DNS packet from server does not match query ID */ -#define SL_ERROR_NET_APP_DNS_PARAM_ERROR (-6159L) /* Invalid params */ -#define SL_ERROR_NET_APP_DNS_SERVER_NOT_FOUND (-6160L) /* Server not found in Client list of DNS servers */ -#define SL_ERROR_NET_APP_DNS_PACKET_CREATE_ERROR (-6161L) /* Error creating DNS packet */ -#define SL_ERROR_NET_APP_DNS_EMPTY_DNS_SERVER_LIST (-6162L) /* DNS Client's list of DNS servers is empty */ -#define SL_ERROR_NET_APP_DNS_SERVER_AUTH_ERROR (-6163L) /* Server not able to authenticate answer/authority data */ -#define SL_ERROR_NET_APP_DNS_ZERO_GATEWAY_IP_ADDRESS (-6164L) /* DNS Client IP instance has a zero gateway IP address */ -#define SL_ERROR_NET_APP_DNS_MISMATCHED_RESPONSE (-6165L) /* Server response type does not match the query request */ -#define SL_ERROR_NET_APP_DNS_DUPLICATE_ENTRY (-6166L) /* Duplicate entry exists in DNS server table */ -#define SL_ERROR_NET_APP_DNS_RETRY_A_QUERY (-6167L) /* SOA status returned; web site only exists as IPv4 */ -#define SL_ERROR_NET_APP_DNS_INVALID_ADDRESS_TYPE (-6168L) /* IP address type (e.g. IPv6L) not supported */ -#define SL_ERROR_NET_APP_DNS_IPV6_NOT_SUPPORTED (-6169L) /* IPv6 disabled */ -#define SL_ERROR_NET_APP_DNS_NEED_MORE_RECORD_BUFFER (-6170L) /* The buffer size is not enough. */ -#define SL_ERROR_NET_APP_MDNS_ERROR (-6171L) /* MDNS internal error. */ -#define SL_ERROR_NET_APP_MDNS_PARAM_ERROR (-6172L) /* MDNS parameters error. */ -#define SL_ERROR_NET_APP_MDNS_CACHE_ERROR (-6173L) /* The Cache size is not enough. */ -#define SL_ERROR_NET_APP_MDNS_UNSUPPORTED_TYPE (-6174L) /* The unsupported resource record type. */ -#define SL_ERROR_NET_APP_MDNS_DATA_SIZE_ERROR (-6175L) /* The data size is too big. */ -#define SL_ERROR_NET_APP_MDNS_AUTH_ERROR (-6176L) /* Attempting to parse too large a data. */ -#define SL_ERROR_NET_APP_MDNS_PACKET_ERROR (-6177L) /* The packet can not add the resource record. */ -#define SL_ERROR_NET_APP_MDNS_DEST_ADDRESS_ERROR (-6178L) /* The destination address error. */ -#define SL_ERROR_NET_APP_MDNS_UDP_PORT_ERROR (-6179L) /* The udp port error. */ -#define SL_ERROR_NET_APP_MDNS_NOT_LOCAL_LINK (-6180L) /* The message that not originate from the local link. */ -#define SL_ERROR_NET_APP_MDNS_EXCEED_MAX_LABEL (-6181L) /* The data exceed the max laber size. */ -#define SL_ERROR_NET_APP_MDNS_EXIST_UNIQUE_RR (-6182L) /* At least one Unqiue record in the cache. */ -#define SL_ERROR_NET_APP_MDNS_EXIST_ANSWER (-6183L) /* At least one answer record in the cache. */ -#define SL_ERROR_NET_APP_MDNS_EXIST_SAME_QUERY (-6184L) /* Exist the same query. */ -#define SL_ERROR_NET_APP_MDNS_DUPLICATE_SERVICE (-6185L) /* Duplicate service. */ -#define SL_ERROR_NET_APP_MDNS_NO_ANSWER (-6186L) /* No response for one-shot query. */ -#define SL_ERROR_NET_APP_MDNS_NO_KNOWN_ANSWER (-6187L) /* No known answer for query. */ -#define SL_ERROR_NET_APP_MDNS_NAME_MISMATCH (-6188L) /* The name mismatch. */ -#define SL_ERROR_NET_APP_MDNS_NOT_STARTED (-6189L) /* MDNS does not start. */ -#define SL_ERROR_NET_APP_MDNS_HOST_NAME_ERROR (-6190L) /* MDNS host name error. */ -#define SL_ERROR_NET_APP_MDNS_NO_MORE_ENTRIES (-6191L) /* No more entries be found. */ -#define SL_ERROR_NET_APP_MDNS_SERVICE_TYPE_MISMATCH (-6192L) /* The service type mismatch */ -#define SL_ERROR_NET_APP_MDNS_LOOKUP_INDEX_ERROR (-6193L) /* Index is bigger than number of services. */ -#define SL_ERROR_NET_APP_MDNS_MAX_SERVICES_ERROR (-6194L) -#define SL_ERROR_NET_APP_MDNS_IDENTICAL_SERVICES_ERROR (-6195L) -#define SL_ERROR_NET_APP_MDNS_EXISTED_SERVICE_ERROR (-6196L) -#define SL_ERROR_NET_APP_MDNS_ERROR_SERVICE_NAME_ERROR (-6197L) -#define SL_ERROR_NET_APP_MDNS_RX_PACKET_ALLOCATION_ERROR (-6198L) -#define SL_ERROR_NET_APP_MDNS_BUFFER_SIZE_ERROR (-6199L) -#define SL_ERROR_NET_APP_MDNS_NET_APP_SET_ERROR (-6200L) -#define SL_ERROR_NET_APP_MDNS_GET_SERVICE_LIST_FLAG_ERROR (-6201L) -#define SL_ERROR_NET_APP_MDNS_MDNS_NO_CONFIGURATION_ERROR (-6202L) -#define SL_ERROR_NET_APP_MDNS_STATUS_ERROR (-6203L) -#define SL_ERROR_NET_APP_ENOBUFS (-6204L) -#define SL_ERROR_NET_APP_DNS_IPV6_REQ_BUT_IPV6_DISABLED (-6205L) /* trying to issue ipv6 DNS request but ipv6 is disabled */ -#define SL_ERROR_NET_APP_DNS_INVALID_FAMILY_TYPE (-6206L) /* Family type is not ipv4 and not ipv6 */ -#define SL_ERROR_NET_APP_DNS_REQ_TOO_BIG (-6207L) /* DNS request size is too big */ -#define SL_ERROR_NET_APP_DNS_ALLOC_ERROR (-6208L) /* Allocation error */ -#define SL_ERROR_NET_APP_DNS_EXECUTION_ERROR (-6209L) /* Execution error */ -#define SL_ERROR_NET_APP_P2P_ROLE_IS_NOT_CONFIGURED (-6210L) /* role p2p is not configured yet, should be CL or GO in order to execute command */ -#define SL_ERROR_NET_APP_INCORECT_ROLE_FOR_APP (-6211L) /* incorrect role for specific application */ -#define SL_ERROR_NET_APP_INCORECT_APP_MASK (-6212L) /* mask does not match any app */ -#define SL_ERROR_NET_APP_MDNS_ALREADY_STARTED (-6213L) /* mdns application already started */ -#define SL_ERROR_NET_APP_HTTP_SERVER_ALREADY_STARTED (-6214L) /* http server application already started */ - -#define SL_ERROR_NET_APP_HTTP_GENERAL_ERROR (-6216L) /* New error - Http handle request failed */ -#define SL_ERROR_NET_APP_HTTP_INVALID_TIMEOUT (-6217L) /* New error - Http timeout invalid argument */ -#define SL_ERROR_NET_APP_INVALID_URN_LENGTH (-6218L) /* invalid URN length */ -#define SL_ERROR_NET_APP_RX_BUFFER_LENGTH (-6219L) /* size of the requested services is smaller than size of the user buffer */ -#define SL_ERROR_NET_APP_CMD_PING_TOO_BIG (-6220L) /* Ping size is too big */ -#define SL_ERROR_NET_APP_CMD_PING_INTERNAL_FAILURE (-6221L) /* Ping internal failure */ -#define SL_ERROR_NET_APP_CMD_PING_NOT_CONNECTED (-6222L) /* Wifi is not connected */ -#define SL_ERROR_NET_APP_CMD_PING_FAILURE (-6223L) /* Ping failure */ -#define SL_ERROR_NET_APP_CMD_PING_OPERATION_FAILED (-6224L) /* Ping operation failed */ -#define SL_ERROR_NET_APP_CMD_PING_DELETE_FAILED (-6225L) /* Ping internal delete failed */ -#define SL_ERROR_NET_APP_CMD_PING_STATE_ERROR (-6226L) /* Ping state machine error */ -#define SL_ERROR_NET_APP_HTTP_INVALID_PARAMETER (-6227L) /* HTTP configuration with wrong value */ - -/* NETCFG ERRORS CODES*/ -#define SL_ERROR_STATIC_ADDR_SUBNET_ERROR (-8193L) -#define SL_ERROR_INCORRECT_IPV6_STATIC_LOCAL_ADDR (-8194L) /* Ipv6 Local address perfix is wrong */ -#define SL_ERROR_INCORRECT_IPV6_STATIC_GLOBAL_ADDR (-8195L) /* Ipv6 Global address perfix is wrong */ -#define SL_ERROR_IPV6_LOCAL_ADDR_SHOULD_BE_SET_FIRST (-8196L) /* Attempt to set ipv6 global address before ipv6 local address is set */ - - -/* FS ERRORS CODES*/ -#define SL_FS_OK (0L) -#define SL_ERROR_FS_EXTRACTION_WILL_START_AFTER_RESET (-10241L) -#define SL_ERROR_FS_NO_CERTIFICATE_STORE (-10242L) -#define SL_ERROR_FS_IMAGE_SHOULD_BE_AUTHENTICATE (-10243L) -#define SL_ERROR_FS_IMAGE_SHOULD_BE_ENCRYPTED (-10244L) -#define SL_ERROR_FS_IMAGE_CANT_BE_ENCRYPTED (-10245L) -#define SL_ERROR_FS_DEVELOPMENT_BOARD_WRONG_MAC (-10246L) -#define SL_ERROR_FS_DEVICE_NOT_SECURED (-10247L) -#define SL_ERROR_FS_SYSTEM_FILE_ACCESS_DENIED (-10248L) -#define SL_ERROR_FS_IMAGE_EXTRACT_EXPECTING_USER_KEY (-10249L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_CLOSE_FILE (-10250L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_WRITE_FILE (-10251L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_OPEN_FILE (-10252L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_GET_IMAGE_HEADER (-10253L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_GET_IMAGE_INFO (-10254L) -#define SL_ERROR_FS_IMAGE_EXTRACT_SET_ID_NOT_EXIST (-10255L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_DELETE_FILE (-10256L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_FORMAT_FS (-10257L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_LOAD_FS (-10258L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_GET_DEV_INFO (-10259L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_DELETE_STORAGE (-10260L) -#define SL_ERROR_FS_IMAGE_EXTRACT_INCORRECT_IMAGE_LOCATION (-10261L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_CREATE_IMAGE_FILE (-10262L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_INIT (-10263L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_LOAD_FILE_TABLE (-10264L) -#define SL_ERROR_FS_IMAGE_EXTRACT_ILLEGAL_COMMAND (-10266L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_WRITE_FAT (-10267L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_RET_FACTORY_DEFAULT (-10268L) -#define SL_ERROR_FS_IMAGE_EXTRACT_FAILED_TO_READ_NV (-10269L) -#define SL_ERROR_FS_PROGRAMMING_IMAGE_NOT_EXISTS (-10270L) -#define SL_ERROR_FS_PROGRAMMING_IN_PROCESS (-10271L) -#define SL_ERROR_FS_PROGRAMMING_ALREADY_STARTED (-10272L) -#define SL_ERROR_FS_CERT_IN_THE_CHAIN_REVOKED_SECURITY_ALERT (-10273L) -#define SL_ERROR_FS_INIT_CERTIFICATE_STORE (-10274L) -#define SL_ERROR_FS_PROGRAMMING_ILLEGAL_FILE (-10275L) -#define SL_ERROR_FS_PROGRAMMING_NOT_STARTED (-10276L) -#define SL_ERROR_FS_IMAGE_EXTRACT_NO_FILE_SYSTEM (-10277L) -#define SL_ERROR_FS_WRONG_INPUT_SIZE (-10278L) -#define SL_ERROR_FS_BUNDLE_FILE_SHOULD_BE_CREATED_WITH_FAILSAFE (-10279L) -#define SL_ERROR_FS_BUNDLE_NOT_CONTAIN_FILES (-10280L) -#define SL_ERROR_FS_BUNDLE_ALREADY_IN_STATE (-10281L) -#define SL_ERROR_FS_BUNDLE_NOT_IN_CORRECT_STATE (-10282L) -#define SL_ERROR_FS_BUNDLE_FILES_ARE_OPENED (-10283L) -#define SL_ERROR_FS_INCORRECT_FILE_STATE_FOR_OPERATION (-10284L) -#define SL_ERROR_FS_EMPTY_SFLASH (-10285L) -#define SL_ERROR_FS_FILE_IS_NOT_SECURE_AND_SIGN (-10286L) -#define SL_ERROR_FS_ROOT_CA_IS_UNKOWN (-10287L) -#define SL_ERROR_FS_FILE_HAS_NOT_BEEN_CLOSE_CORRECTLY (-10288L) -#define SL_ERROR_FS_WRONG_SIGNATURE_SECURITY_ALERT (-10289L) -#define SL_ERROR_FS_WRONG_SIGNATURE_OR_CERTIFIC_NAME_LENGTH (-10290L) -#define SL_ERROR_FS_NOT_16_ALIGNED (-10291L) -#define SL_ERROR_FS_CERT_CHAIN_ERROR_SECURITY_ALERT (-10292L) -#define SL_ERROR_FS_FILE_NAME_EXIST (-10293L) -#define SL_ERROR_FS_EXTENDED_BUF_ALREADY_ALLOC (-10294L) -#define SL_ERROR_FS_FILE_SYSTEM_NOT_SECURED (-10295L) -#define SL_ERROR_FS_OFFSET_NOT_16_BYTE_ALIGN (-10296L) -#define SL_ERROR_FS_FAILED_READ_NVMEM (-10297L) -#define SL_ERROR_FS_WRONG_FILE_NAME (-10298L) -#define SL_ERROR_FS_FILE_SYSTEM_IS_LOCKED (-10299L) -#define SL_ERROR_FS_SECURITY_ALERT (-10300L) -#define SL_ERROR_FS_FILE_INVALID_FILE_SIZE (-10301L) -#define SL_ERROR_FS_INVALID_TOKEN (-10302L) -#define SL_ERROR_FS_NO_DEVICE_IS_LOADED (-10303L) -#define SL_ERROR_FS_SECURE_CONTENT_INTEGRITY_FAILURE (-10304L) -#define SL_ERROR_FS_SECURE_CONTENT_RETRIVE_ASYMETRIC_KEY_ERROR (-10305L) -#define SL_ERROR_FS_OVERLAP_DETECTION_THRESHHOLD (-10306L) -#define SL_ERROR_FS_FILE_HAS_RESERVED_NV_INDEX (-10307L) -#define SL_ERROR_FS_FILE_MAX_SIZE_EXCEEDED (-10310L) -#define SL_ERROR_FS_INVALID_READ_BUFFER (-10311L) -#define SL_ERROR_FS_INVALID_WRITE_BUFFER (-10312L) -#define SL_ERROR_FS_FILE_IMAGE_IS_CORRUPTED (-10313L) -#define SL_ERROR_FS_SIZE_OF_FILE_EXT_EXCEEDED (-10314L) -#define SL_ERROR_FS_WARNING_FILE_NAME_NOT_KEPT (-10315L) -#define SL_ERROR_FS_MAX_OPENED_FILE_EXCEEDED (-10316L) -#define SL_ERROR_FS_FAILED_WRITE_NVMEM_HEADER (-10317L) -#define SL_ERROR_FS_NO_AVAILABLE_NV_INDEX (-10318L) -#define SL_ERROR_FS_FAILED_TO_ALLOCATE_MEM (-10319L) -#define SL_ERROR_FS_OPERATION_BLOCKED_BY_VENDOR (-10320L) -#define SL_ERROR_FS_FAILED_TO_READ_NVMEM_FILE_SYSTEM (-10321L) -#define SL_ERROR_FS_NOT_ENOUGH_STORAGE_SPACE (-10322L) -#define SL_ERROR_FS_INIT_WAS_NOT_CALLED (-10323L) -#define SL_ERROR_FS_FILE_SYSTEM_IS_BUSY (-10324L) -#define SL_ERROR_FS_INVALID_ACCESS_TYPE (-10325L) -#define SL_ERROR_FS_FILE_ALREADY_EXISTS (-10326L) -#define SL_ERROR_FS_PROGRAM_FAILURE (-10327L) -#define SL_ERROR_FS_NO_ENTRIES_AVAILABLE (-10328L) -#define SL_ERROR_FS_FILE_ACCESS_IS_DIFFERENT (-10329L) -#define SL_ERROR_FS_INVALID_FILE_MODE (-10330L) -#define SL_ERROR_FS_FAILED_READ_NVFILE (-10331L) -#define SL_ERROR_FS_FAILED_INIT_STORAGE (-10332L) -#define SL_ERROR_FS_FILE_HAS_NO_FAILSAFE (-10333L) -#define SL_ERROR_FS_NO_VALID_COPY_EXISTS (-10334L) -#define SL_ERROR_FS_INVALID_HANDLE (-10335L) -#define SL_ERROR_FS_FAILED_TO_WRITE (-10336L) -#define SL_ERROR_FS_OFFSET_OUT_OF_RANGE (-10337L) -#define SL_ERROR_FS_NO_MEMORY (-10338L) -#define SL_ERROR_FS_INVALID_LENGTH_FOR_READ (-10339L) -#define SL_ERROR_FS_WRONG_FILE_OPEN_FLAGS (-10340L) -#define SL_ERROR_FS_FILE_NOT_EXISTS (-10341L) -#define SL_ERROR_FS_IGNORE_COMMIT_ROLLBAC_FLAG (-10342L) /* commit rollback flag is not supported upon creation */ -#define SL_ERROR_FS_INVALID_ARGS (-10343L) -#define SL_ERROR_FS_FILE_IS_PENDING_COMMIT (-10344L) -#define SL_ERROR_FS_SECURE_CONTENT_SESSION_ALREADY_EXIST (-10345L) -#define SL_ERROR_FS_UNKNOWN (-10346L) -#define SL_ERROR_FS_FILE_NAME_RESERVED (-10347L) -#define SL_ERROR_FS_NO_FILE_SYSTEM (-10348L) -#define SL_ERROR_FS_INVALID_MAGIC_NUM (-10349L) -#define SL_ERROR_FS_FAILED_TO_READ_NVMEM (-10350L) -#define SL_ERROR_FS_NOT_SUPPORTED (-10351L) -#define SL_ERROR_FS_JTAG_IS_OPENED_NO_FORMAT_TO_PRDUCTION (-10352L) -#define SL_ERROR_FS_CONFIG_FILE_RET_READ_FAILED (-10353L) -#define SL_ERROR_FS_CONFIG_FILE_CHECSUM_ERROR_SECURITY_ALERT (-10354L) -#define SL_ERROR_FS_CONFIG_FILE_NO_SUCH_FILE (-10355L) -#define SL_ERROR_FS_CONFIG_FILE_MEMORY_ALLOCATION_FAILED (-10356L) -#define SL_ERROR_FS_IMAGE_HEADER_READ_FAILED (-10357L) -#define SL_ERROR_FS_CERT_STORE_OR_SP_DOWNGRADE (-10358L) -#define SL_ERROR_FS_PROGRAMMING_IMAGE_NOT_VALID (-10359L) -#define SL_ERROR_FS_PROGRAMMING_IMAGE_NOT_VERIFIED (-10360L) -#define SL_ERROR_FS_RESERVE_SIZE_IS_SMALLER (-10361L) -#define SL_ERROR_FS_WRONG_ALLOCATION_TABLE (-10362L) -#define SL_ERROR_FS_ILLEGAL_SIGNATURE (-10363L) -#define SL_ERROR_FS_FILE_ALREADY_OPENED_IN_PENDING_STATE (-10364L) -#define SL_ERROR_FS_INVALID_TOKEN_SECURITY_ALERT (-10365L) -#define SL_ERROR_FS_NOT_SECURE (-10366L) -#define SL_ERROR_FS_RESET_DURING_PROGRAMMING (-10367L) -#define SL_ERROR_FS_CONFIG_FILE_RET_WRITE_FAILED (-10368L) -#define SL_ERROR_FS_FILE_IS_ALREADY_OPENED (-10369L) -#define SL_ERROR_FS_FILE_IS_OPEN_FOR_WRITE (-10370L) -#define SL_ERROR_FS_ALERT_CANT_BE_SET_ON_NON_SECURE_DEVICE (-10371L) /* Alerts can be configured on non-secure device. */ -#define SL_ERROR_FS_WRONG_CERTIFICATE_FILE_NAME (-10372L) - - -/* NETUTIL ERRORS CODES */ -#define SL_ERROR_NETUTIL_CRYPTO_GENERAL (-12289L) -#define SL_ERROR_NETUTIL_CRYPTO_INVALID_INDEX (-12290L) -#define SL_ERROR_NETUTIL_CRYPTO_INVALID_PARAM (-12291L) -#define SL_ERROR_NETUTIL_CRYPTO_MEM_ALLOC (-12292L) -#define SL_ERROR_NETUTIL_CRYPTO_INVALID_DB_VER (-12293L) -#define SL_ERROR_NETUTIL_CRYPTO_UNSUPPORTED_OPTION (-12294L) -#define SL_ERROR_NETUTIL_CRYPTO_BUFFER_TOO_SMALL (-12295L) -#define SL_ERROR_NETUTIL_CRYPTO_EMPTY_DB_ENTRY (-12296L) -#define SL_ERROR_NETUTIL_CRYPTO_NON_TEMPORARY_KEY (-12297L) -#define SL_ERROR_NETUTIL_CRYPTO_DB_ENTRY_NOT_FREE (-12298L) -#define SL_ERROR_NETUTIL_CRYPTO_CORRUPTED_DB_FILE (-12299L) -#define SL_ERROR_UTILS_GENERAL (-12300L) -#define SL_ERROR_UTILS_INVALID_PARAM (-12301L) -#define SL_ERROR_UTILS_MEM_ALLOC (-12302L) -#define SL_ERROR_UTILS_IP_NOT_FOUND (-12303L) -#define SL_ERROR_UTILS_IP_NOT_ALLOWED (-12304L) - - -/* GENERAL ERRORS CODES*/ -#define SL_ERROR_INVALID_OPCODE (-14337L) -#define SL_ERROR_INVALID_PARAM (-14338L) -#define SL_ERROR_STATUS_ERROR (-14341L) -#define SL_ERROR_NVMEM_ACCESS_FAILED (-14342L) -#define SL_ERROR_NOT_ALLOWED_NWP_LOCKED (-14343L) /* Device is locked, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram) */ -#define SL_ERROR_RANDOM_TEST_FAILED (-14344L) - -/* SECURITY ERRORS CODE */ -#define SL_ERROR_LOADING_CERTIFICATE_STORE (-28673L) - -/* Device is Locked! Return to Factory Image or Program new - image should be invoked (see sl_FsCtl, sl_FsProgram) */ -#define SL_ERROR_DEVICE_LOCKED_SECURITY_ALERT (-28674L) - -#define SL_ERROR_LENGTH_ERROR_PREFIX (-30734L) -#define SL_ERROR_WAKELOCK_ERROR_PREFIX (-30735L) -#define SL_ERROR_DRV_START_FAIL (-30736L) -#define SL_ERROR_VALIDATION_ERROR (-30737L) -#define SL_ERROR_SETUP_FAILURE (-30738L) -#define SL_ERROR_HTTP_SERVER_ENABLE_FAILED (-30739L) -#define SL_ERROR_DHCP_SERVER_ENABLE_FAILED (-30740L) -#define SL_ERROR_WPS_NO_PIN_OR_WRONG_PIN_LEN (-30741L) - - -/* INTERNAL HOST ERRORS CODES*/ - -/* Receive this error in case there are no resources to issue the command - If possible, increase the number of MAX_CONCURRENT_ACTIONS (result in memory increaseL) - If not, try again later */ -#define SL_POOL_IS_EMPTY (-2000L) - -/* Receive this error in case a given length for RX buffer was too small. - Receive payload was bigger than the given buffer size. Therefore, payload is cut according to receive size - Recommend to increase buffer size */ -#define SL_ESMALLBUF (-2001L) - -/* Receive this error in case zero length is supplied to a "get" API - Recommend to supply length according to requested information (view options defines for helpL) */ -#define SL_EZEROLEN (-2002L) - -/* User supplied invalid parameter */ -#define SL_INVALPARAM (-2003L) - -/* Failed to open interface */ -#define SL_BAD_INTERFACE (-2004L) - -/* API has been aborted due to an error detected by host driver */ -#define SL_API_ABORTED (-2005L) - -/* Parameters are invalid */ -#define SL_RET_CODE_INVALID_INPUT (-2006L) - -/* Driver internal return value */ -#define SL_RET_OBJ_NOT_SET (-2007L) - -/* NWP internal error */ -#define SL_RET_CODE_NWP_IF_ERROR (-2008L) - -/* malloc error */ -#define SL_RET_CODE_MALLOC_ERROR (-2009L) - -/* protocol error */ -#define SL_RET_CODE_PROTOCOL_ERROR (-2010L) - -/* API has been aborted, command is not allowed in device lock state */ -#define SL_RET_CODE_DEV_LOCKED (-2011L) - -/* sl_Start cannot be invoked twice */ -#define SL_RET_CODE_DEV_ALREADY_STARTED (-2012L) - -/* SL API is in progress */ -#define SL_RET_CODE_API_COMMAND_IN_PROGRESS (-2013L) - -/* Provisioning is in progress - */ -#define SL_RET_CODE_PROVISIONING_IN_PROGRESS (-2014L) - -/* Wrong ping parameters - ping cannot be called with the following parameters: -1. infinite ping packet -2. report only when finished -3. no callback supplied */ -#define SL_RET_CODE_NET_APP_PING_INVALID_PARAMS (-2015L) - -/* SL select already in progress. - this error will be returned if app will try to call - sl_select blocking when there is already select trigger in progress */ -#define SL_RET_CODE_SOCKET_SELECT_IN_PROGRESS_ERROR (-2016L) - -#define SL_RET_CODE_STOP_IN_PROGRESS (-2017L) - -/* The device has not been started yet */ -#define SL_RET_CODE_DEV_NOT_STARTED (-2018L) - -/* The event link was not found in the list */ -#define SL_RET_CODE_EVENT_LINK_NOT_FOUND (-2019L) - -/* In case there are no free buffers for async event which arrived - during command context. In this case user needs to increase - MAX_CONCURRENT_ACTIONS at user.h */ -#define SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR (-2020L) - -/* SPI/UART interface closed */ -#define SL_RET_CODE_INTERFACE_CLOSED (-2021L) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __ERROR_H__ */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/eventreg.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/eventreg.c deleted file mode 100644 index 740aef035dd..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/eventreg.c +++ /dev/null @@ -1,381 +0,0 @@ -/* - * eventreg.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include - - -typedef void (*_pSlDeviceFatalErrorEvtHdlr_t)(SlDeviceFatal_t *pSlFatalErrorEvent); -typedef void (*_pSlDeviceGeneralEvtHdlr_t)(SlDeviceEvent_t *pSlDeviceEvent); -typedef void (*_pSlWlanEvtHdlr)(SlWlanEvent_t* pSlWlanEvent); -typedef void (*_pSlNetAppEvtHdlr)(SlNetAppEvent_t* pSlNetAppEvent); -typedef void (*_pSlSockEvtHdlr)(SlSockEvent_t* pSlSockEvent); -typedef void (*_pSlNetAppHttpServerHdlr)(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse); -typedef void (*_pSlNetAppRequestHdlr)(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); -typedef void (*_pSlNetAppRequestMemFree)(_u8 *buffer); -typedef void (*_pSlSocketTriggerEventHandler)(SlSockTriggerEvent_t* pSlSockTriggerEvent); - - -typedef _i32 (*_pSlPropogationDeviceFatalErrorEvtHdlr_t)(SlDeviceFatal_t *pSlFatalErrorEvent); -typedef _i32 (*_pSlPropogationDeviceGeneralEvtHdlr_t)(SlDeviceEvent_t *pSlDeviceEvent); -typedef _i32 (*_pSlPropogationWlanEvtHdlr)(SlWlanEvent_t* pSlWlanEvent); -typedef _i32 (*_pSlPropogationNetAppEvtHdlr)(SlNetAppEvent_t* pSlNetAppEvent); -typedef _i32 (*_pSlPropogationSockEvtHdlr)(SlSockEvent_t* pSlSockEvent); -typedef _i32 (*_pSlPropogationNetAppHttpServerHdlr)(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse); -typedef _i32 (*_pSlPropogationNetAppRequestHdlr)(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); -typedef _i32 (*_pSlPropogationNetAppRequestMemFree)(_u8 *buffer); -typedef _i32 (*_pSlPropogationSocketTriggerEventHandler)(SlSockTriggerEvent_t* pSlSockTriggerEvent); - -#ifdef SL_RUNTIME_EVENT_REGISTERATION - -void* g_UserEvents[SL_NUM_OF_EVENT_TYPES] = {0}; -SlEventsListNode_t* g_LibsEvents[SL_NUM_OF_EVENT_TYPES] = {0}; - -#endif - - -_i32 _SlIsEventRegistered(SlEventHandler_e EventHandlerType) -{ -#ifdef SL_RUNTIME_EVENT_REGISTERATION - if( (NULL != g_LibsEvents[EventHandlerType]) || (NULL != g_UserEvents[EventHandlerType]) ) - { - return 1; - } -#endif - if(SL_EVENT_HDL_MEM_FREE == EventHandlerType) - { -#ifdef slcb_NetAppRequestMemFree - return 1; -#endif - } - if(SL_EVENT_HDL_SOCKET_TRIGGER == EventHandlerType) - { -#ifdef slcb_SocketTriggerEventHandler - return 1; -#endif - } - - return 0; -} - -#ifdef SL_RUNTIME_EVENT_REGISTERATION - -_i32 sl_RegisterEventHandler(SlEventHandler_e EventHandlerType , void* EventHandler) -{ - g_UserEvents[EventHandlerType] = EventHandler; - return 0; -} - -_i32 sl_RegisterLibsEventHandler(SlEventHandler_e EventHandlerType , SlEventsListNode_t* EventHandlerNode) -{ - EventHandlerNode->next = NULL; - - if(g_LibsEvents[EventHandlerType] == NULL) - { - g_LibsEvents[EventHandlerType] = EventHandlerNode; - } - else - { - SlEventsListNode_t* currentNode = g_LibsEvents[EventHandlerType]; - while(currentNode->next != NULL) - { - currentNode = currentNode->next; - } - - currentNode->next = EventHandlerNode; - } - return 0; -} - -_i32 sl_UnregisterLibsEventHandler(SlEventHandler_e EventHandlerType , SlEventsListNode_t* EventHandlerNode) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[EventHandlerType]; - SlEventsListNode_t* lastNode = g_LibsEvents[EventHandlerType]; - int count = 0; - while(currentNode != NULL) - { - if(EventHandlerNode == currentNode) - { - if(count == 0) - { - g_LibsEvents[EventHandlerType] = g_LibsEvents[EventHandlerType]->next; - } - else - { - lastNode->next = currentNode->next; - } - return 0; - } - - if(count != 0) - { - lastNode = lastNode->next; - } - count++; - currentNode = currentNode->next; - } - - return SL_RET_CODE_EVENT_LINK_NOT_FOUND; -} - - -/* Event handlers section */ -void _SlDeviceFatalErrorEvtHdlr(SlDeviceFatal_t *pSlFatalErrorEvent) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_FATAL_ERROR]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationDeviceFatalErrorEvtHdlr_t)(currentNode->event))(pSlFatalErrorEvent)) - { - return; - } - currentNode = currentNode->next; - } - - if (NULL != g_UserEvents[SL_EVENT_HDL_FATAL_ERROR]) - { - ((_pSlDeviceFatalErrorEvtHdlr_t)g_UserEvents[SL_EVENT_HDL_FATAL_ERROR])(pSlFatalErrorEvent); - } - -#ifdef slcb_DeviceFatalErrorEvtHdlr - else - { - slcb_DeviceFatalErrorEvtHdlr(pSlFatalErrorEvent); - } -#endif -} - - -void _SlDeviceGeneralEvtHdlr(SlDeviceEvent_t *pSlDeviceEvent) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_DEVICE_GENERAL]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationDeviceGeneralEvtHdlr_t)(currentNode->event))(pSlDeviceEvent)) - { - return; - } - currentNode = currentNode->next; - } - - if (NULL != g_UserEvents[SL_EVENT_HDL_DEVICE_GENERAL]) - { - ((_pSlDeviceGeneralEvtHdlr_t)g_UserEvents[SL_EVENT_HDL_DEVICE_GENERAL])(pSlDeviceEvent); - } -#ifdef slcb_DeviceGeneralEvtHdlr - else - { - slcb_DeviceGeneralEvtHdlr(pSlDeviceEvent); - } -#endif -} - - -void _SlWlanEvtHdlr(SlWlanEvent_t* pSlWlanEvent) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_WLAN]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationWlanEvtHdlr)(currentNode->event))(pSlWlanEvent)) - { - return; - } - currentNode = currentNode->next; - } - - if (NULL != g_UserEvents[SL_EVENT_HDL_WLAN]) - { - ((_pSlWlanEvtHdlr)g_UserEvents[SL_EVENT_HDL_WLAN])(pSlWlanEvent); - } -#ifdef slcb_WlanEvtHdlr - else - { - slcb_WlanEvtHdlr(pSlWlanEvent); - } -#endif -} - - -void _SlNetAppEvtHdlr(SlNetAppEvent_t* pSlNetAppEvent) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_NETAPP]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationNetAppEvtHdlr)(currentNode->event))(pSlNetAppEvent)) - { - return; - } - currentNode = currentNode->next; - } - if (NULL != g_UserEvents[SL_EVENT_HDL_NETAPP]) - { - ((_pSlNetAppEvtHdlr)g_UserEvents[SL_EVENT_HDL_NETAPP])(pSlNetAppEvent); - } -#ifdef slcb_NetAppEvtHdlr - else - { - slcb_NetAppEvtHdlr(pSlNetAppEvent); - } -#endif -} - - -void _SlSockEvtHdlr(SlSockEvent_t* pSlSockEvent) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_SOCKET]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationSockEvtHdlr)(currentNode->event))(pSlSockEvent)) - { - return; - } - currentNode = currentNode->next; - } - if (NULL != g_UserEvents[SL_EVENT_HDL_SOCKET]) - { - ((_pSlSockEvtHdlr)g_UserEvents[SL_EVENT_HDL_SOCKET])(pSlSockEvent); - } - -#ifdef slcb_SockEvtHdlr - else - { - slcb_SockEvtHdlr(pSlSockEvent); - } -#endif -} - - -void _SlNetAppHttpServerHdlr(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_HTTP_SERVER]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationNetAppHttpServerHdlr)(currentNode->event))(pSlHttpServerEvent,pSlHttpServerResponse)) - { - return; - } - currentNode = currentNode->next; - } - if (NULL != g_UserEvents[SL_EVENT_HDL_HTTP_SERVER]) - { - ((_pSlNetAppHttpServerHdlr)g_UserEvents[SL_EVENT_HDL_HTTP_SERVER])(pSlHttpServerEvent,pSlHttpServerResponse); - } -#ifdef slcb_NetAppHttpServerHdlr - else - { - slcb_NetAppHttpServerHdlr(pSlHttpServerEvent,pSlHttpServerResponse); - } -#endif -} - - - -void _SlNetAppRequestHdlr(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_NETAPP_REQUEST]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationNetAppRequestHdlr)(currentNode->event))(pNetAppRequest,pNetAppResponse)) - { - return; - } - currentNode = currentNode->next; - } - if (NULL != g_UserEvents[SL_EVENT_HDL_NETAPP_REQUEST]) - { - ((_pSlNetAppRequestHdlr)g_UserEvents[SL_EVENT_HDL_NETAPP_REQUEST])(pNetAppRequest,pNetAppResponse); - } -#ifdef slcb_NetAppRequestHdlr - else - { - slcb_NetAppRequestHdlr(pNetAppRequest,pNetAppResponse); - } -#endif -} - - - -void _SlNetAppRequestMemFree (_u8 *buffer) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_MEM_FREE]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationNetAppRequestMemFree)(currentNode->event))(buffer)) - { - return; - } - currentNode = currentNode->next; - } - if (NULL != g_UserEvents[SL_EVENT_HDL_MEM_FREE]) - { - ((_pSlNetAppRequestMemFree)g_UserEvents[SL_EVENT_HDL_MEM_FREE])(buffer); - } -#ifdef slcb_NetAppRequestMemFree - else - { - slcb_NetAppRequestMemFree(buffer); - } -#endif -} - - -void _SlSocketTriggerEventHandler(SlSockTriggerEvent_t* pSlSockTriggerEvent) -{ - SlEventsListNode_t* currentNode = g_LibsEvents[SL_EVENT_HDL_SOCKET_TRIGGER]; - while(currentNode != NULL) - { - if(EVENT_PROPAGATION_BLOCK == ((_pSlPropogationSocketTriggerEventHandler)(currentNode->event))(pSlSockTriggerEvent)) - { - return; - } - currentNode = currentNode->next; - } - if (NULL != g_UserEvents[SL_EVENT_HDL_SOCKET_TRIGGER]) - { - ((_pSlSocketTriggerEventHandler)g_UserEvents[SL_EVENT_HDL_SOCKET_TRIGGER])(pSlSockTriggerEvent); - } -#ifdef slcb_SocketTriggerEventHandler - else - { - slcb_SocketTriggerEventHandler(pSlSockTriggerEvent); - } -#endif -} - -#endif /* SL_RUNTIME_EVENT_REGISTERATION */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/eventreg.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/eventreg.h deleted file mode 100644 index 4f2a66be7cc..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/eventreg.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * eventreg.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -#ifndef EVENTREG_H_ -#define EVENTREG_H_ - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! - \defgroup event_registration - \short Allows user to register event handlers dynamically. - -*/ -/*! - - \addtogroup event_registration - @{ - -*/ - -typedef enum -{ - SL_EVENT_HDL_FATAL_ERROR, - SL_EVENT_HDL_DEVICE_GENERAL, - SL_EVENT_HDL_WLAN, - SL_EVENT_HDL_NETAPP, - SL_EVENT_HDL_SOCKET, - SL_EVENT_HDL_HTTP_SERVER, - SL_EVENT_HDL_NETAPP_REQUEST, - SL_EVENT_HDL_MEM_FREE, - SL_EVENT_HDL_SOCKET_TRIGGER, - SL_NUM_OF_EVENT_TYPES -}SlEventHandler_e; - -typedef struct SlEventsListNode_s -{ - void *event; - struct SlEventsListNode_s *next; -}SlEventsListNode_t; - -#ifdef SL_RUNTIME_EVENT_REGISTERATION - -/*! - \brief register events in runtime - - this api enables registration of the SimpleLink host driver in runtime. - - \param[in] EventHandlerType event type - SlEventHandler_e - to register - - \param[in] EventHandler pointer to the event handler - - \return 0 on success, error otherwise - - \sa sl_RegisterEventHandler - - \note registration of event with NULL, clears any registered event. -*/ -_i32 sl_RegisterEventHandler(SlEventHandler_e EventHandlerType , void* EventHandler); - - - -_i32 _SlIsEventRegistered(SlEventHandler_e EventHandlerType); - -/****************************************************************************** - sl_RegisterLibsEventHandler - - \brief this function registers event handlers from external libraries in runtime. - - the allocation and memory maintenance of the SlEventsListNode_t is on the library - Responsibility. - - RETURNS: success or error code. -******************************************************************************/ - -_i32 sl_RegisterLibsEventHandler(SlEventHandler_e EventHandlerType , SlEventsListNode_t* EventHandlerNode); - -/****************************************************************************** - sl_UnregisterLibsEventHandler - - DESCRIPTION: - this function unregisters event handlers from external libraries in runtime. - the SlEventsListNode_t that was used for registration, must be used to unregister that event handler. - - the allocation and memory maintenance of the SlEventsListNode_t is on the library - Responsibility. - - RETURNS: success or error code. -******************************************************************************/ -_i32 sl_UnregisterLibsEventHandler(SlEventHandler_e EventHandlerType , SlEventsListNode_t* EventHandlerNode); - -/*! - - Close the Doxygen group. - @} - - */ - - -void _SlDeviceFatalErrorEvtHdlr(SlDeviceFatal_t *pSlFatalErrorEvent); -void _SlDeviceGeneralEvtHdlr(SlDeviceEvent_t *pSlDeviceEvent); -void _SlWlanEvtHdlr(SlWlanEvent_t* pSlWlanEvent); -void _SlNetAppEvtHdlr(SlNetAppEvent_t* pSlNetAppEvent); -void _SlSockEvtHdlr(SlSockEvent_t* pSlSockEvent); -void _SlNetAppHttpServerHdlr(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse); -void _SlNetAppRequestHdlr(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); -void _SlNetAppRequestMemFree (_u8 *buffer); -void _SlSocketTriggerEventHandler(SlSockTriggerEvent_t* pSlSockTriggerEvent); - -#endif /* SL_RUNTIME_EVENT_REGISTERATION */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - - -#endif /* EVENTREG_H_ */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/fs.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/fs.h deleted file mode 100644 index 6b95dc7f72a..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/fs.h +++ /dev/null @@ -1,850 +0,0 @@ -/* - * fs.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -#ifndef __FS_H__ -#define __FS_H__ - - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup FileSystem - \short Provides file system capabilities to TI's CC31XX that can be used by both the CC31XX device and the user - -*/ - -/*! - - \addtogroup FileSystem - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/* Create file max size mode */ -#define SL_FS_OPEN_MODE_BIT_MASK (0xF8000000) -#define SL_NUM_OF_MODE_BIT (5) - -#define SL_FS_OPEN_FLAGS_BIT_MASK (0x07FE0000) -#define SL_NUM_OF_FLAGS_BIT (10) - -#define SL_FS_OPEN_MAXSIZE_BIT_MASK (0x1FFFF) -#define SL_NUM_OF_MAXSIZE_BIT (17) - - -/* - sl_FsGetInfo and sl_FsGetFileList flags - ------------------ -*/ - -#define SL_FS_INFO_OPEN_WRITE 0x1000 /* File is opened for write */ -#define SL_FS_INFO_OPEN_READ 0x800 /* File is opened for read */ - -#define SL_FS_INFO_MUST_COMMIT 0x1 /* File is currently open with SL_FS_WRITE_MUST_COMMIT */ -#define SL_FS_INFO_BUNDLE_FILE 0x2 /* File is currently open with SL_FS_WRITE_BUNDLE_FILE */ - -#define SL_FS_INFO_PENDING_COMMIT 0x4 /* File that was open with SL_FS_WRITE_MUST_COMMIT is closed */ -#define SL_FS_INFO_PENDING_BUNDLE_COMMIT 0x8 /* File that was open with SL_FS_WRITE_BUNDLE_FILE is closed */ - -#define SL_FS_INFO_NOT_FAILSAFE 0x20 /* File was not created with SL_FS_CREATE_FAILSAFE */ -#define SL_FS_INFO_NOT_VALID 0x100 /* No valid image exists for the file */ -#define SL_FS_INFO_SYS_FILE 0x40 /* File is system file */ -#define SL_FS_INFO_SECURE 0x10 /* File is secured */ -#define SL_FS_INFO_NOSIGNATURE 0x2000 /* File is unsigned, the flag is returns only for sl_FsGetInfo function and not for sl_FsGetFileList */ -#define SL_FS_INFO_PUBLIC_WRITE 0x200 /* File is open for public write */ -#define SL_FS_INFO_PUBLIC_READ 0x400 /* File is open for public read */ - - -/* - fs_Open flags - -------------- -*/ - -/* mode */ -#define SL_FS_CREATE ((_u32)0x1<<(SL_NUM_OF_MAXSIZE_BIT+SL_NUM_OF_FLAGS_BIT)) -#define SL_FS_WRITE ((_u32)0x2<<(SL_NUM_OF_MAXSIZE_BIT+SL_NUM_OF_FLAGS_BIT)) -#define SL_FS_OVERWRITE ((_u32)0x4<<(SL_NUM_OF_MAXSIZE_BIT+SL_NUM_OF_FLAGS_BIT)) -#define SL_FS_READ ((_u32)0x8<<(SL_NUM_OF_MAXSIZE_BIT+SL_NUM_OF_FLAGS_BIT)) -/* creation flags */ -#define SL_FS_CREATE_FAILSAFE ((_u32)0x1< - - - Create a non secure file if not already exists and open it for write - \code - DeviceFileHandle = sl_FsOpen((unsigned char *)DeviceFileName, - SL_FS_CREATE|SL_FS_OVERWRITE| SL_FS_CREATE_MAX_SIZE( MaxSize ), - NULL); - \endcode - - \note Some of the flags are creation flags and can only be set when the file is created. When opening the file for write the creation flags are ignored. For more information, refer to chapter 8 in the user manual. - -*/ - -#if _SL_INCLUDE_FUNC(sl_FsOpen) -_i32 sl_FsOpen(const _u8 *pFileName,const _u32 AccessModeAndMaxSize,_u32 *pToken); -#endif - -/*! - \brief Close file in storage device - - \param[in] FileHdl Pointer to the file (assigned from sl_FsOpen) - \param[in] pCeritificateFileName Certificate file, or NULL if irrelevant. - \param[in] pSignature The signature is SHA-1, the certificate chain may include SHA-256 - \param[in] SignatureLen The signature actual length - - \return Zero on success, or a negative value if an error occurred - \sa sl_FsRead sl_FsWrite sl_FsOpen - \note Call the fs_Close with signature = 'A' signature len = 1 for activating an abort action\n - Creating signature : OpenSSL> dgst -binary -sha1 -sign \.pem -out \.sig \.txt - \warning - \par Examples - - - Closing file: - \code - _i16 RetVal; - RetVal = sl_FsClose(FileHandle,0,0,0); - \endcode -
- - - Aborting file: - \code - _u8 Signature; - Signature = 'A'; - sl_FsClose(FileHandle,0,&Signature, 1); - \endcode - - \note In case the file was opened as not secure file or as secure-not signed, any certificate or signature provided are ignored, those fields should be set to NULL. -*/ -#if _SL_INCLUDE_FUNC(sl_FsClose) -_i16 sl_FsClose(const _i32 FileHdl,const _u8* pCeritificateFileName,const _u8* pSignature,const _u32 SignatureLen); -#endif - -/*! - \brief Read block of data from a file in storage device - - \param[in] FileHdl Pointer to the file (assigned from sl_FsOpen) - \param[in] Offset Offset to specific read block - \param[out] pData Pointer for the received data - \param[in] Len Length of the received data - - \return Number of read bytes on success, negative error code on failure - - \sa sl_FsClose sl_FsWrite sl_FsOpen - \note belongs to \ref basic_api - \warning - \par Example - - - Reading File: - \code - Status = sl_FsRead(FileHandle, 0, &readBuff[0], readSize); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_FsRead) -_i32 sl_FsRead(const _i32 FileHdl,_u32 Offset ,_u8* pData,_u32 Len); -#endif - -/*! - \brief Write block of data to a file in storage device - - \param[in] FileHdl Pointer to the file (assigned from sl_FsOpen) - \param[in] Offset Offset to specific block to be written - \param[in] pData Pointer the transmitted data to the storage device - \param[in] Len Length of the transmitted data - - \return Number of wireted bytes on success, negative error code on failure - - \sa - \note belongs to \ref basic_api - \warning - \par Example - - - Writing file: - \code - Status = sl_FsWrite(FileHandle, 0, &buff[0], readSize); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_FsWrite) -_i32 sl_FsWrite(const _i32 FileHdl,_u32 Offset,_u8* pData,_u32 Len); -#endif - -/*! - \brief Get information of a file - - \param[in] pFileName File name - \param[in] Token File token. if irrelevant set to 0. - \param[out] pFsFileInfo Returns the File's Information (SlFsFileInfo_t) - - Flags - - File size - - Allocated size - - Tokens - - \return Zero on success, negative error code on failure \n - When file not exists : SL_ERROR_FS_FILE_NOT_EXISTS - \note - - If the return value is SL_ERROR_FS_FILE_HAS_NOT_BEEN_CLOSE_CORRECTLY or SL_ERROR_FS_FILE_IS_ALREADY_OPENED information about the file is valid. - - Belongs to \ref basic_api - - \sa sl_FsOpen - \warning - \par Example - - - Getting file info: - \code - Status = sl_FsGetInfo("FileName.html",Token,&FsFileInfo); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_FsGetInfo) -_i16 sl_FsGetInfo(const _u8 *pFileName,const _u32 Token,SlFsFileInfo_t* pFsFileInfo); -#endif - -/*! - \brief Delete specific file from a storage or all files from a storage (format) - - \param[in] pFileName File Name - \param[in] Token File token. if irrelevant set to 0 - \return Zero on success, or a negative value if an error occurred - - \sa - \note belongs to \ref basic_api - \warning - \par Example - - - Deleting file: - \code - Status = sl_FsDel("FileName.html",Token); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_FsDel) -_i16 sl_FsDel(const _u8 *pFileName,const _u32 Token); -#endif - - - -/*! - \brief Controls various file system operations - - \param[in] Command , the command to execute, \see SlFsCtl_e - SL_FS_CTL_RESTORE , Return to factory default, return to factory image , see fs programming - SL_FS_CTL_ROLLBACK , Roll-back file which was created with 'SL_FS_WRITE_MUST_COMMIT' - SL_FS_CTL_COMMIT,Commit file which was created with 'SL_FS_WRITE_MUST_COMMIT' - SL_FS_CTL_RENAME, Rename file - SL_FS_CTL_GET_STORAGE_INFO, Total size of storage , available size of storage - SL_FS_CTL_BUNDLE_ROLLBACK, Rollback bundle files - SL_FS_CTL_BUNDLE_COMMIT, Commit Bundle files - \param[in] Token Set to NULL if not relevant to the command - \param[in] pFileName Set to NULL if not relevant to the command - \param[in] pData The data according the command. - \param[in] DataLen Length of data buffer - \param[out] pOutputData Buffer for the output data - \param[out] OutputDataLen Length of the output data buffer - \param[out] pNewToken The new valid file token, if irrelevant can be set to NULL. - \return - - Zero on success, or a negative value if an error occurred - - For SL_FS_CTL_BUNDLE_ROLLBACK, On success bundle the new bundle state is returned (see SlFsBundleState_e) else negative error number - - For SL_FS_CTL_BUNDLE_COMMIT, On success the new bundle state is returned (see SlFsBundleState_e) else negative error number - - \sa - \note belongs to \ref ext_api - \warning - \par Examples - - - SL_FS_CTL_ROLLBACK: - \code - FsControl.IncludeFilters = 0; - slRetVal = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_FILE_ROLLBACK, Token, NWPfileName ,(_u8 *)&FsControl, sizeof(SlFsControl_t), NULL, 0 , pNewToken); - \endcode -
- - - SL_FS_CTL_COMMIT: - \code - FsControl.IncludeFilters = 0; - slRetVal = sl_FsCtl(SL_FS_CTL_COMMIT, Token, NWPfileName ,(_u8 *)&FsControl, sizeof(SlFsControl_t), NULL, 0, pNewToken ); - \endcode -
- - - SL_FS_CTL_RENAME: - \code - slRetVal = sl_FsCtl(SL_FS_CTL_RENAME, Token, NWPfileName, NewFileName, 0, NULL, 0, NULL ); - \endcode -
- - - SL_FS_CTL_GET_STORAGE_INFO: - \code - _i32 GetStorageInfo( SlFsControlGetStorageInfoResponse_t* pSlFsControlGetStorageInfoResponse ) - { - _i32 slRetVal; - - slRetVal = sl_FsCtl( ( SlFsCtl_e)SL_FS_CTL_GET_STORAGE_INFO, 0, NULL , NULL , 0, (_u8 *)pSlFsControlGetStorageInfoResponse, sizeof(SlFsControlGetStorageInfoResponse_t), NULL ); - return slRetVal; - } - \endcode -
- - - SL_FS_CTL_RESTORE: - \code - //Return 0 for OK, else Error - _i32 ProgramRetToImage( ) - { - _i32 slRetVal; - SlFsRetToFactoryCommand_t RetToFactoryCommand; - _i32 RetVal, ExtendedError; - - RetToFactoryCommand.Operation = SL_FS_FACTORY_RET_TO_IMAGE; - slRetVal = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_RESTORE, 0, NULL , (_u8 *)&RetToFactoryCommand , sizeof(SlFsRetToFactoryCommand_t), NULL, 0 , NULL ); - if ((_i32)slRetVal < 0) - { - //Pay attention, for this function the slRetVal is composed from Signed RetVal & extended error - RetVal = (_i16)slRetVal>> 16; - ExtendedError = (_u16)slRetVal& 0xFFFF; - printf("\tError SL_FS_FACTORY_RET_TO_IMAGE, 5d, %d\n", RetVal, ExtendedError); - return slRetVal; - } - //Reset - sl_Stop(0); - Sleep(1000); - sl_Start(NULL, NULL, NULL); - - return slRetVal; - } - \endcode -
- - - SL_FS_CTL_BUNDLE_ROLLBACK: - \code - //return 0 for O.K else negative - _i32 BundleRollback() - { - _i32 slRetVal = 0; - SlFsControl_t FsControl; - FsControl.IncludeFilters = 0; //Use default behaviour - slRetVal = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_BUNDLE_ROLLBACK, 0, NULL ,(_u8 *)&FsControl, sizeof(SlFsControl_t), NULL, 0 , NULL); - return slRetVal; - } - \endcode -
- - - SL_FS_CTL_BUNDLE_COMMIT: - \code - //return 0 for O.K else negative - _i32 BundleCommit() - { - _i32 slRetVal = 0; - SlFsControl_t FsControl; - FsControl.IncludeFilters = 0; //Use default behaviour - slRetVal = sl_FsCtl( (SlFsCtl_e)SL_FS_CTL_BUNDLE_COMMIT, 0, NULL ,(_u8 *)&FsControl, sizeof(SlFsControl_t), NULL, 0 , NULL); - return slRetVal; - } - \endcode - */ -#if _SL_INCLUDE_FUNC(sl_FsCtl) -_i32 sl_FsCtl( SlFsCtl_e Command, _u32 Token, _u8 *pFileName, const _u8 *pData, _u16 DataLen, _u8 *pOutputData, _u16 OutputDataLen,_u32 *pNewToken ); -#endif -/*! - \brief Enables to format and configure the device with pre-prepared configuration - - \param[in] Flags For future use - \param[in] pKey In case the ucf is encrypted the encryption key, otherwise NULL - \param[in] pData The file is download in data chunks, the chunk size should be aligned to 16 bytes, if no data Set to NULL - \param[in] Len The length of pData in bytes - \return The return value is: - - On error < 0 , contains the error number and extended error number - - On success > 0, represent the number of bytes received - - On successful end == 0 , when all file chunks are download - \sa - \note belongs to \ref ext_api - \warning - \par Example - - - FS programming: - \code - - //Return 0 for OK, else Error - _i32 ProgramImage( char* UcfFileName, char * KeyFileName ) - { - #define PROGRAMMING_CHUNK_SIZE 4096 - _i32 slRetVal = 0; - SlFsKey_t Key; - FILE *hostFileHandle = NULL; - _u16 bytesRead; - _u8 DataBuf[PROGRAMMING_CHUNK_SIZE]; - FILE *KeyFileHandle = NULL; - short ErrorNum; - unsigned short ExtendedErrorNum; - time_t start,end; - double dif; - _u8* pKey = NULL; - errno_t err; - - if (KeyFileName != "") - { - //Read key - err = fopen_s( &KeyFileHandle, KeyFileName, "rb"); - if (err != 0) - { - return __LINE__;//error - } - fread((_u8*)&Key, 1, sizeof(SlFsKey_t), KeyFileHandle); - fclose(KeyFileHandle); - pKey = (_u8*)&Key; - } - - // Downlaoding the Data with the key, the key can be set only in the first chunk,no need to download it with each chunk - if (UcfFileName != "") - { - //Read data - err = fopen_s( &hostFileHandle, UcfFileName, "rb"); - if (err != 0) - { - return __LINE__;//error - } - - time (&start); - - bytesRead = fread(DataBuf, 1, PROGRAMMING_CHUNK_SIZE, hostFileHandle); - - while ( bytesRead ) - { - slRetVal = sl_FsProgram( DataBuf , bytesRead , (_u8*)pKey, 0 ); - if(slRetVal == SL_API_ABORTED)//timeout - { - return( slRetVal ); - } - else if (slRetVal < 0 )//error - { - ErrorNum = (long)slRetVal >> 16; - ExtendedErrorNum = (_u16)(slRetVal & 0xFFFF); - printf("\tError sl_FsProgram = %d , %d \n", ErrorNum, ExtendedErrorNum); - fclose(hostFileHandle); - return( ErrorNum ); - } - if(slRetVal == 0)//finished succesfully - break; - pKey = NULL;//no need to download the key with each chunk; - bytesRead = fread(DataBuf, 1, PROGRAMMING_CHUNK_SIZE, hostFileHandle); - } - - - time (&end); - dif = difftime (end,start); - #ifdef PRINT - printf ("\tProgramming took %.2lf seconds to run.\n", dif ); - #endif - //The file was downloaded but it was not detected by the programming as the EOF. - if((bytesRead == 0 ) && (slRetVal > 0 )) - { - return __LINE__;//error - } - - - fclose(hostFileHandle); - }//if (UcfFileName != "") - - //this scenario is in case the image was already "burned" to the SFLASH by external tool and only the key is downloaded - else if (KeyFileName != "") - { - slRetVal = sl_FsProgram(NULL , 0 , (_u8*)pKey, 0 ); - if (slRetVal < 0)//error - { - ErrorNum = (long)slRetVal >> 16; - ExtendedErrorNum = (_u16)slRetVal && 0xFF;; - printf("\tError sl_FsProgram = %d , %d \n", ErrorNum, ExtendedErrorNum); - fclose(hostFileHandle); - return( ErrorNum ); - } - } - - if( slRetVal == 0 ) - { - //Reset the nWP - sl_Stop(100); - Sleep(1000); - sl_Start(NULL, NULL, NULL); - Sleep(2000); - } - - return slRetVal; - - } - - \endcode -*/ - -#if _SL_INCLUDE_FUNC(sl_FsProgram) -_i32 sl_FsProgram(const _u8* pData , _u16 Len , const _u8 * pKey , _u32 Flags ); -#endif -/*! - \brief The list of file names, the files are retrieve in chunks - - \param[in, out] pIndex The first chunk should start with value of -1, afterwards the Index from the previous call should be set as input\n - Returns current chunk intex, start the next chunk from that number - \param[in] Count Number of entries to retrieve - \param[in] MaxEntryLen The total size of the buffer is Count * MaxEntryLen - \param[out] pBuff The buffer contains list of SlFileAttributes_t + file name - \param[in] Flags Is to retrieve file attributes see SlFileAttributes_t. - \return The actual number of entries which are contained in the buffer. On error negative number which contains the error number. - \sa - \note belongs to \ref ext_api - \warning - \par Example - - - Getting file list - \code - typedef struct - { - SlFileAttributes_t attribute; - char fileName[SL_FS_MAX_FILE_NAME_LENGTH]; - }slGetfileList_t; - - #define COUNT 5 - - void PrintFileListProperty(_u16 prop); - - INT32 GetFileList() - { - _i32 NumOfEntriesOrError = 1; - _i32 Index = -1; - slGetfileList_t File[COUNT]; - _i32 i; - _i32 RetVal = 0; - - printf("%\n"); - while( NumOfEntriesOrError > 0 ) - { - NumOfEntriesOrError = sl_FsGetFileList( &Index, COUNT, (_u8)(SL_FS_MAX_FILE_NAME_LENGTH + sizeof(SlFileAttributes_t)), (unsigned char*)File, SL_FS_GET_FILE_ATTRIBUTES); - if (NumOfEntriesOrError < 0) - { - RetVal = NumOfEntriesOrError;//error - break; - } - for (i = 0; i < NumOfEntriesOrError; i++) - { - printf("Name: %s\n", File[i].fileName); - printf("AllocatedBlocks: %5d ",File[i].attribute.FileAllocatedBlocks); - printf("MaxSize(byte): %5d \n", File[i].attribute.FileMaxSize); - PrintFileListProperty((_u16)File[i].attribute.Properties); - printf("%\n\n"); - } - } - printf("%\n"); - return RetVal;//0 means O.K - } - - void PrintFileListProperty(_u16 prop) - { - printf("Flags : "); - if (prop & SL_FS_INFO_MUST_COMMIT) - printf("Open file commit,"); - if (prop & SL_FS_INFO_BUNDLE_FILE) - printf("Open bundle commit,"); - if (prop & SL_FS_INFO_PENDING_COMMIT) - printf("Pending file commit,"); - if (prop & SL_FS_INFO_PENDING_BUNDLE_COMMIT) - printf("Pending bundle commit,"); - if (prop & SL_FS_INFO_SECURE) - printf("Secure,"); - if (prop & SL_FS_INFO_NOT_FAILSAFE) - printf("File safe,"); - if (prop & SL_FS_INFO_SYS_FILE) - printf("System,"); - if (prop & SL_FS_INFO_NOT_VALID) - printf("No valid copy,"); - if (prop & SL_FS_INFO_PUBLIC_WRITE) - printf("Public write,"); - if (prop & SL_FS_INFO_PUBLIC_READ) - printf("Public read,"); - } - - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_FsGetFileList) -_i32 sl_FsGetFileList(_i32* pIndex, _u8 Count, _u8 MaxEntryLen , _u8* pBuff, SlFileListFlags_t Flags ); -#endif - -/*! - - Close the Doxygen group. - @} - - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __FS_H__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/netapp.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/netapp.h deleted file mode 100644 index b89b411d5d5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/netapp.h +++ /dev/null @@ -1,1424 +0,0 @@ -/* - * netapp.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -#ifndef __NETAPP_H__ -#define __NETAPP_H__ - - - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup NetApp - \short Activates networking applications, such as: HTTP Server, DHCP Server, Ping, DNS and mDNS - -*/ - -/*! - - \addtogroup NetApp - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/* NetApp user events */ -typedef enum -{ - SL_NETAPP_EVENT_IPV4_ACQUIRED = 1, - SL_NETAPP_EVENT_IPV6_ACQUIRED, - SL_NETAPP_EVENT_IP_COLLISION, - SL_NETAPP_EVENT_DHCPV4_LEASED, - SL_NETAPP_EVENT_DHCPV4_RELEASED, - SL_NETAPP_EVENT_HTTP_TOKEN_GET, - SL_NETAPP_EVENT_HTTP_TOKEN_POST, - SL_NETAPP_EVENT_IPV4_LOST, - SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT, - SL_NETAPP_EVENT_IPV6_LOST, - SL_NETAPP_EVENT_NO_IPV4_COLLISION_DETECTED, - SL_NETAPP_EVENT_NO_LOCAL_IPV6_COLLISION_DETECTED, - SL_NETAPP_EVENT_NO_GLOBAL_IPV6_COLLISION_DETECTED, - SL_NETAPP_EVENT_MAX -} SlNetAppEventId_e; - - -#define SL_NETAPP_MDNS_OPTIONS_IS_UNIQUE_BIT 0x1 -#define SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT ((_u32)0x1 << 31) -#define SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT ((_u32)0x1 << 30) -#define SL_NETAPP_MDNS_OPTION_UPDATE_TEXT ((_u32)0x1 << 29) -#define SL_NETAPP_MDNS_IPV4_ONLY_SERVICE (_u32)(0) /* default mode:zero bits 27,28*/ -#define SL_NETAPP_MDNS_IPV6_ONLY_SERVICE ((_u32)0x1 << 28) -#define SL_NETAPP_MDNS_IPV6_IPV4_SERVICE ((_u32)0x1 << 27) - - -/*ERROR code*/ -#define SL_NETAPP_RX_BUFFER_LENGTH_ERROR (-230) - -/* Http Server interface */ -#define SL_NETAPP_MAX_INPUT_STRING (64) /* because of WPA */ - -#define SL_NETAPP_MAX_AUTH_NAME_LEN (20) -#define SL_NETAPP_MAX_AUTH_PASSWORD_LEN (20) -#define SL_NETAPP_MAX_AUTH_REALM_LEN (20) - -#define SL_NETAPP_MAX_DEVICE_URN_LEN (32+1) -#define SL_NETAPP_MAX_DOMAIN_NAME_LEN (24+1) - -#define SL_NETAPP_MAX_ACTION_LEN (30) -#define SL_NETAPP_MAX_TOKEN_NAME_LEN (20) - - -#define SL_NETAPP_MAX_TOKEN_VALUE_LEN SL_NETAPP_MAX_INPUT_STRING - -#define SL_NETAPP_MAX_SERVICE_TEXT_SIZE (256) -#define SL_NETAPP_MAX_SERVICE_NAME_SIZE (60) -#define SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE (64) - - -/* Server Responses */ -#define SL_NETAPP_HTTPRESPONSE_NONE (0) -#define SL_NETAPP_HTTPSETTOKENVALUE (1) - -#define SL_NETAPP_FAMILY_MASK (0x80) - -/* mDNS types */ -#define SL_NETAPP_MASK_IPP_TYPE_OF_SERVICE (0x00000001) -#define SL_NETAPP_MASK_DEVICE_INFO_TYPE_OF_SERVICE (0x00000002) -#define SL_NETAPP_MASK_HTTP_TYPE_OF_SERVICE (0x00000004) -#define SL_NETAPP_MASK_HTTPS_TYPE_OF_SERVICE (0x00000008) -#define SL_NETAPP_MASK_WORKSATION_TYPE_OF_SERVICE (0x00000010) -#define SL_NETAPP_MASK_GUID_TYPE_OF_SERVICE (0x00000020) -#define SL_NETAPP_MASK_H323_TYPE_OF_SERVICE (0x00000040) -#define SL_NETAPP_MASK_NTP_TYPE_OF_SERVICE (0x00000080) -#define SL_NETAPP_MASK_OBJECITVE_TYPE_OF_SERVICE (0x00000100) -#define SL_NETAPP_MASK_RDP_TYPE_OF_SERVICE (0x00000200) -#define SL_NETAPP_MASK_REMOTE_TYPE_OF_SERVICE (0x00000400) -#define SL_NETAPP_MASK_RTSP_TYPE_OF_SERVICE (0x00000800) -#define SL_NETAPP_MASK_SIP_TYPE_OF_SERVICE (0x00001000) -#define SL_NETAPP_MASK_SMB_TYPE_OF_SERVICE (0x00002000) -#define SL_NETAPP_MASK_SOAP_TYPE_OF_SERVICE (0x00004000) -#define SL_NETAPP_MASK_SSH_TYPE_OF_SERVICE (0x00008000) -#define SL_NETAPP_MASK_TELNET_TYPE_OF_SERVICE (0x00010000) -#define SL_NETAPP_MASK_TFTP_TYPE_OF_SERVICE (0x00020000) -#define SL_NETAPP_MASK_XMPP_CLIENT_TYPE_OF_SERVICE (0x00040000) -#define SL_NETAPP_MASK_RAOP_TYPE_OF_SERVICE (0x00080000) -#define SL_NETAPP_MASK_ALL_TYPE_OF_SERVICE (0xFFFFFFFF) - -/********************************************************************************************************/ - -/* NetApp application IDs */ -#define SL_NETAPP_HTTP_SERVER_ID (0x01) -#define SL_NETAPP_DHCP_SERVER_ID (0x02) -#define SL_NETAPP_MDNS_ID (0x04) -#define SL_NETAPP_DNS_SERVER_ID (0x08) - -#define SL_NETAPP_DEVICE_ID (0x10) -#define SL_NETAPP_DNS_CLIENT_ID (0x20) -#define SL_NETAPP_STATUS (0x40) - -/* NetApp application set/get options */ -#define SL_NETAPP_DHCP_SRV_BASIC_OPT (0) - -/* HTTP server set/get options */ -#define SL_NETAPP_HTTP_PRIMARY_PORT_NUMBER (0) -#define SL_NETAPP_HTTP_AUTH_CHECK (1) -#define SL_NETAPP_HTTP_AUTH_NAME (2) -#define SL_NETAPP_HTTP_AUTH_PASSWORD (3) -#define SL_NETAPP_HTTP_AUTH_REALM (4) -#define SL_NETAPP_HTTP_ROM_PAGES_ACCESS (5) -#define SL_NETAPP_HTTP_SECONDARY_PORT_NUMBER (6) -#define SL_NETAPP_HTTP_SECONDARY_PORT_ENABLE (7) /*Enable / disable of secondary port */ -#define SL_NETAPP_HTTP_PRIMARY_PORT_SECURITY_MODE (8) -#define SL_NETAPP_HTTP_PRIVATE_KEY_FILENAME (9) -#define SL_NETAPP_HTTP_DEVICE_CERTIFICATE_FILENAME (10) -#define SL_NETAPP_HTTP_CA_CERTIFICATE_FILE_NAME (11) -#define SL_NETAPP_HTTP_TEMP_REGISTER_MDNS_SERVICE_NAME (12) -#define SL_NETAPP_HTTP_TEMP_UNREGISTER_MDNS_SERVICE_NAME (13) -#define SL_NETAPP_HTTP_TIMEOUT (14) - - -#define SL_NETAPP_MDNS_CONT_QUERY_OPT (1) -#define SL_NETAPP_MDNS_QEVETN_MASK_OPT (2) -#define SL_NETAPP_MDNS_TIMING_PARAMS_OPT (3) - -/* DNS server set/get options */ -#define SL_NETAPP_DNS_OPT_DOMAIN_NAME (0) - -/* Device Config set/get options */ -#define SL_NETAPP_DEVICE_URN (0) -#define SL_NETAPP_DEVICE_DOMAIN (1) -#define SL_NETAPP_DEVICE_NAME (2) - -/* DNS client set/get options */ -#define SL_NETAPP_DNS_CLIENT_TIME (0) -#define SL_NETAPP_DNS_CLIENT_CACHE_CLEAR (1) -#define SL_NETAPP_DNS_CLIENT_CACHE_ENABLE (2) - -/* Get active application bimap */ -#define SL_NETAPP_STATUS_ACTIVE_APP (0) - -#define SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH (255) - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -typedef struct -{ - _u32 Ip; - _u32 Gateway; - _u32 Dns; -}SlIpV4AcquiredAsync_t; - -typedef enum -{ - SL_BSD_IPV6_ACQUIRED_TYPE_LOCAL = 1, - SL_BSD_IPV6_ACQUIRED_TYPE_GLOBAL = 2 -}SlIpV6AcquiredAsyncType_e; - -typedef struct -{ - _u32 Ip[4]; - _u32 Dns[4]; -}SlIpV6AcquiredAsync_t; - -typedef struct -{ - _u32 IpAddress; - _u32 LeaseTime; - _u8 Mac[6]; - _u16 Padding; -}SlIpLeasedAsync_t; - -typedef struct -{ - _u32 IpAddress; - _u8 Mac[6]; - _u16 Reason; -}SlIpReleasedAsync_t; - -typedef struct -{ - _u32 IpAddress; - _u8 DhcpMac[6]; - _u8 ConflictMac[6]; -}SlIpCollisionAsync_t; - -typedef struct -{ - _u32 Ip; - _u8 Mac[6]; - _u16 AddMode; -}SlNoIpV4CollisionDetectedAsync_t; - -typedef struct -{ - _u32 Ip[4]; - _u8 Mac[6]; - _u16 AddMode; -}SlNoIpV6CollisionDetectedAsync_t; - - - -typedef struct -{ - _i16 Status; - _u16 Padding; -}SlIpV4Lost_t; - -typedef struct -{ - _u32 IpLost[4]; -}SlIpV6Lost_t; - -typedef struct -{ - _i16 Status; - _u16 Padding; -}SlDhcpIpAcquireTimeout_t; - -typedef union -{ - SlIpV4AcquiredAsync_t IpAcquiredV4; /* SL_NETAPP_EVENT_IPV4_ACQUIRED */ - SlIpV6AcquiredAsync_t IpAcquiredV6; /* SL_NETAPP_EVENT_IPV6_ACQUIRED */ - _u32 Sd; /* SL_SOCKET_TX_FAILED_EVENT */ - SlIpLeasedAsync_t IpLeased; /* SL_NETAPP_EVENT_DHCPV4_LEASED */ - SlIpReleasedAsync_t IpReleased; /* SL_NETAPP_EVENT_DHCPV4_RELEASED */ - SlIpV4Lost_t IpV4Lost; /* SL_NETAPP_EVENT_IPV4_LOST */ - SlDhcpIpAcquireTimeout_t DhcpIpAcquireTimeout; /* SL_NETAPP_DHCP_ACQUIRE_IPV4_TIMEOUT_EVENT */ - SlIpCollisionAsync_t IpCollision; /* SL_NETAPP_EVENT_IP_COLLISION */ - SlIpV6Lost_t IpV6Lost; /* SL_NETAPP_EVENT_IPV6_LOST */ - SlNoIpV4CollisionDetectedAsync_t Ipv4CollisionDetected; /* SL_NETAPP_EVENT_NO_IPV4_COLLISION_DETECTED */ - SlNoIpV6CollisionDetectedAsync_t Ipv6CollisionDetected; /* SL_NETAPP_EVENT_NO_IPV4_COLLISION_DETECTED */ -} SlNetAppEventData_u; - -typedef struct -{ - _u32 Id; - SlNetAppEventData_u Data; -}SlNetAppEvent_t; - -typedef struct -{ - _u32 PacketsSent; - _u32 PacketsReceived; - _u16 MinRoundTime; - _u16 MaxRoundTime; - _u16 AvgRoundTime; - _u32 TestTime; -}SlNetAppPingReport_t; - -typedef struct -{ - _u32 PingIntervalTime; /* delay between pings, in milliseconds */ - _u16 PingSize; /* ping packet size in bytes */ - _u16 PingRequestTimeout; /* timeout time for every ping in milliseconds */ - _u32 TotalNumberOfAttempts; /* max number of ping requests. 0 - forever */ - _u32 Flags; /* flag - 0 report only when finished, 1 - return response for every ping, 2 - stop after 1 successful ping. 4 - ipv4 header flag - don`t fragment packet */ - _u32 Ip; /* IPv4 address or IPv6 first 4 bytes */ - _u32 Ip1OrPadding; - _u32 Ip2OrPadding; - _u32 Ip3OrPadding; -}SlNetAppPingCommand_t; - -typedef struct -{ - _u8 Len; - _u8 *pData; -} SlNetAppHttpServerString_t; - -typedef struct -{ - _u8 ValueLen; - _u8 NameLen; - _u8 *pTokenValue; - _u8 *pTokenName; -} SlNetAppHttpServerData_t; - -typedef struct -{ - SlNetAppHttpServerString_t Action; - SlNetAppHttpServerString_t TokenName; - SlNetAppHttpServerString_t TokenValue; -}SlNetAppHttpServerPostData_t; - -typedef union -{ - SlNetAppHttpServerString_t HttpTokenName; /* SL_NETAPP_HTTPGETTOKENVALUE */ - SlNetAppHttpServerPostData_t HttpPostData; /* SL_NETAPP_HTTPPOSTTOKENVALUE */ -} SlNetAppHttpServerEventData_u; - -typedef union -{ - SlNetAppHttpServerString_t TokenValue; -} SlNetAppHttpServerResponsedata_u; - -typedef struct -{ - _u32 Event; - SlNetAppHttpServerEventData_u EventData; -}SlNetAppHttpServerEvent_t; - -typedef struct -{ - _u32 Response; - SlNetAppHttpServerResponsedata_u ResponseData; -}SlNetAppHttpServerResponse_t; - -/***************************************************************************************** -* NETAPP Request/Response/Send/Receive -******************************************************************************************/ -/* TODO: check what definitions are eventually needed */ -/* NETAPP http request types */ -#define SL_NETAPP_REQUEST_HTTP_GET 1 -#define SL_NETAPP_REQUEST_HTTP_POST 2 -#define SL_NETAPP_REQUEST_HTTP_PUT 3 -#define SL_NETAPP_REQUEST_HTTP_DELETE 4 - -#define SL_NETAPP_REQUEST_MAX_METADATA_LEN 1024 -#define SL_NETAPP_REQUEST_MAX_DATA_LEN 1364 /* Metadata + Payload */ - - -typedef enum -{ - SL_NETAPP_REQUEST_METADATA_TYPE_STATUS = 0, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_VERSION, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_REQUEST_URI, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_QUERY_STRING, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_LEN, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_TYPE, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_LOCATION, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_SERVER, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_USER_AGENT, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_COOKIE, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_SET_COOKIE, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_UPGRADE, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_REFERER, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_ACCEPT, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_ENCODING, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_DISPOSITION, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONNECTION, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_ETAG, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_DATE, - SL_NETAPP_REQUEST_METADATA_TYPE_HEADER_HOST, - SL_NETAPP_REQUEST_METADATA_TYPE_ACCEPT_ENCODING, - SL_NETAPP_REQUEST_METADATA_TYPE_ACCEPT_LANGUAGE, - SL_NETAPP_REQUEST_METADATA_TYPE_CONTENT_LANGUAGE, - SL_NETAPP_REQUEST_METADATA_TYPE_ORIGIN, - SL_NETAPP_REQUEST_METADATA_TYPE_ORIGIN_CONTROL_ACCESS, - SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_NONE -} SlNetAppMetadataHTTPTypes_e; - -typedef enum -{ - SL_NETAPP_RESPONSE_NONE = 0, /* No response */ - SL_NETAPP_RESPONSE_PENDING = 1, /* status will arrive in future NetApp Send call (in metadata) */ - - SL_NETAPP_HTTP_RESPONSE_101_SWITCHING_PROTOCOLS = 101, /* 101 Switching Protocol*/ - SL_NETAPP_HTTP_RESPONSE_200_OK = 200, /* 200 OK */ - SL_NETAPP_HTTP_RESPONSE_201_CREATED = 201, /* "HTTP/1.0 201 Created" */ - SL_NETAPP_HTTP_RESPONSE_202_ACCEPTED = 202, /* "HTTP/1.0 202 Accepted" */ - SL_NETAPP_HTTP_RESPONSE_204_OK_NO_CONTENT = 204, /* 204 No Content */ - SL_NETAPP_HTTP_RESPONSE_301_MOVED_PERMANENTLY = 301, /* "HTTP/1.0 301 Moved Permanently" */ - SL_NETAPP_HTTP_RESPONSE_302_MOVED_TEMPORARILY = 302, /* 302 Moved Temporarily (http 1.0) */ - SL_NETAPP_HTTP_RESPONSE_303_SEE_OTHER = 303, /* "HTTP/1.1 303 See Other" */ - SL_NETAPP_HTTP_RESPONSE_304_NOT_MODIFIED = 304, /* "HTTP/1.0 304 Not Modified" */ - SL_NETAPP_HTTP_RESPONSE_400_BAD_REQUEST = 400, /* "HTTP/1.0 400 Bad Request" */ - SL_NETAPP_HTTP_RESPONSE_403_FORBIDDEN = 403, /* "HTTP/1.0 403 Forbidden" */ - SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND = 404, /* 404 Not Found */ - SL_NETAPP_HTTP_RESPONSE_405_METHOD_NOT_ALLOWED = 405, /* "HTTP/1.0 405 Method Not Allowed" */ - SL_NETAPP_HTTP_RESPONSE_500_INTERNAL_SERVER_ERROR = 500, /* 500 Internal Server Error */ - SL_NETAPP_HTTP_RESPONSE_503_SERVICE_UNAVAILABLE = 503, /* "HTTP/1.0 503 Service Unavailable" */ - SL_NETAPP_HTTP_RESPONSE_504_GATEWAY_TIMEOUT = 504 /* "HTTP/1.0 504 Gateway Timeout" */ -} SlNetAppResponseCode_e; - - -#define SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION 0x00000001 -#define SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA 0x00000002 /* 0 - data is payload, 1 - data is metadata */ -#define SL_NETAPP_REQUEST_RESPONSE_FLAGS_ACCUMULATION 0x00000004 -#define SL_NETAPP_REQUEST_RESPONSE_FLAGS_ERROR 0x80000000 /* in that case the last two bytes represents the error code */ - -typedef struct -{ - _u16 MetadataLen; - _u8 *pMetadata; - _u16 PayloadLen; - _u8 *pPayload; - _u32 Flags; -} SlNetAppData_t; - -typedef struct -{ - _u8 AppId; - _u8 Type; - _u16 Handle; - SlNetAppData_t requestData; -} SlNetAppRequest_t; - -typedef struct -{ - _u16 Status; - SlNetAppData_t ResponseData; -} SlNetAppResponse_t; - -typedef struct -{ - _u32 lease_time; - _u32 ipv4_addr_start; - _u32 ipv4_addr_last; -}SlNetAppDhcpServerBasicOpt_t; - -/* mDNS parameters */ -typedef enum -{ - SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV4_TYPE = 1, - SL_NETAPP_FULL_SERVICE_IPV4_TYPE, - SL_NETAPP_SHORT_SERVICE_IPV4_TYPE, - SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV6_TYPE , - SL_NETAPP_FULL_SERVICE_IPV6_TYPE, - SL_NETAPP_SHORT_SERVICE_IPV6_TYPE -} SlNetAppGetServiceListType_e; - -typedef struct -{ - _u32 service_ipv4; - _u16 service_port; - _u16 Reserved; -}SlNetAppGetShortServiceIpv4List_t; - -typedef struct -{ - _u32 service_ipv4; - _u16 service_port; - _u16 Reserved; - _u8 service_name[SL_NETAPP_MAX_SERVICE_NAME_SIZE]; - _u8 service_host[SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE]; -}SlNetAppGetFullServiceIpv4List_t; - -typedef struct -{ - _u32 service_ipv4; - _u16 service_port; - _u16 Reserved; - _u8 service_name[SL_NETAPP_MAX_SERVICE_NAME_SIZE]; - _u8 service_host[SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE]; - _u8 service_text[SL_NETAPP_MAX_SERVICE_TEXT_SIZE]; -}SlNetAppGetFullServiceWithTextIpv4List_t; - -/* IPv6 entries */ -typedef struct -{ - _u32 service_ipv6[4]; - _u16 service_port; - _u16 Reserved; -}SlNetAppGetShortServiceIpv6List_t; - -typedef struct -{ - _u32 service_ipv6[4]; - _u16 service_port; - _u16 Reserved; - _u8 service_name[SL_NETAPP_MAX_SERVICE_NAME_SIZE]; - _u8 service_host[SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE]; -}SlNetAppGetFullServiceIpv6List_t; - -typedef struct -{ - _u32 service_ipv6[4]; - _u16 service_port; - _u16 Reserved; - _u8 service_name[SL_NETAPP_MAX_SERVICE_NAME_SIZE]; - _u8 service_host[SL_NETAPP_MAX_SERVICE_HOST_NAME_SIZE]; - _u8 service_text[SL_NETAPP_MAX_SERVICE_TEXT_SIZE]; -}SlNetAppGetFullServiceWithTextIpv6List_t; - -typedef struct -{ - /*The below parameters are used to configure the advertise times and interval - For example: - If: - Period is set to T - Repetitions are set to P - Telescopic factor is K=2 - The transmission shall be: - advertise P times - wait T - advertise P times - wait 4 * T - advertise P time - wait 16 * T ... (till max time reached / configuration changed / query issued) - */ - _u32 t; /* Number of ticks for the initial period. Default is 100 ticks for 1 second. */ - _u32 p; /* Number of repetitions. Default value is 1 */ - _u32 k; /* Telescopic factor. Default value is 2. */ - _u32 RetransInterval; /* Announcing retransmission interval */ - _u32 Maxinterval; /* Announcing max period interval */ - _u32 max_time; /* Announcing max time */ -}SlNetAppServiceAdvertiseTimingParameters_t; - -typedef struct -{ - _u16 MaxResponseTime; - _u16 NumOfRetries; -}SlNetAppDnsClientTime_t; - -/*****************************************************************************/ -/* Types declarations */ -/*****************************************************************************/ -typedef void (*P_SL_DEV_PING_CALLBACK)(SlNetAppPingReport_t*); - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - - -/*! - \brief Starts a network application - - Gets and starts network application for the current WLAN mode - - \param[in] AppBitMap Application bitmap, could be one or combination of the following: - - SL_NETAPP_HTTP_SERVER_ID - - SL_NETAPP_DHCP_SERVER_ID - - SL_NETAPP_MDNS_ID - - SL_NETAPP_DNS_SERVER_ID - - \par Persistent - System Persistent - \return Zero on success, or negative error code on failure - - \sa sl_NetAppStop - \note This command activates the application for the current WLAN mode (AP or STA) - \warning - \par Example - - - Starting internal HTTP server + DHCP server: - \code - sl_NetAppStart(SL_NETAPP_HTTP_SERVER_ID | SL_NETAPP_DHCP_SERVER_ID) - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppStart) -_i16 sl_NetAppStart(const _u32 AppBitMap); -#endif -/*! - \brief Stops a network application - - Gets and stops network application for the current WLAN mode - - \param[in] AppBitMap Application id, could be one of the following: \n - - SL_NETAPP_HTTP_SERVER_ID - - SL_NETAPP_DHCP_SERVER_ID - - SL_NETAPP_MDNS_ID - - SL_NETAPP_DNS_SERVER_ID - - \par Persistent - System Persistent - - \return Zero on success, or nagative error code on failure - - \sa sl_NetAppStart - \note This command disables the application for the current active WLAN mode (AP or STA) - \warning - \par Example - - - Stopping internal HTTP server: - \code - sl_NetAppStop(SL_NETAPP_HTTP_SERVER_ID); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppStop) -_i16 sl_NetAppStop(const _u32 AppBitMap); -#endif - -/*! - \brief Flush IPv4 ARP table - - - - \param[in] None \n - - - \return Zero on success, or negative error code on failure - - \sa sl_NetAppArpFlush - \note This command flush IPv4 ARP table - \warning - \par Example - - - \code - sl_NetAppArpFlush(); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppArpFlush) -_i16 sl_NetAppArpFlush(); -#endif - -/*! - \brief Flush IPv6 Neighbor Discovery table - - - - \param[in] None \n - - - \return Zero on success, or negative error code on failure - - \sa sl_NetAppNdFlush - \note This command flush IPv6 Neighbor Discovery table - \warning - \par Example - - - \code - sl_NetAppNdFlush(); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppNdFlush) -_i16 sl_NetAppNdFlush(); -#endif - -/*! - \brief Get host IP by name\n - Obtain the IP Address of machine on network, by machine name. - - \param[in] pHostName Host name - \param[in] NameLen Name length - \param[out] OutIpAddr This parameter is filled in with - host IP address. In case that host name is not - resolved, out_ip_addr is zero. - \param[in] Family Protocol family - - \return Zero on success, or negative on failure.\n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system\n - In this case try again later or increase MAX_CONCURRENT_ACTIONS - Possible DNS error codes: - - SL_NETAPP_DNS_QUERY_NO_RESPONSE - - SL_NETAPP_DNS_NO_SERVER - - SL_NETAPP_DNS_QUERY_FAILED - - SL_NETAPP_DNS_MALFORMED_PACKET - - SL_NETAPP_DNS_MISMATCHED_RESPONSE - - \sa - \note Only one sl_NetAppDnsGetHostByName can be handled at a time.\n - Calling this API while the same command is called from another thread, may result - in one of the two scenarios: - 1. The command will wait (internal) until the previous command finish, and then be executed. - 2. There are not enough resources and POOL_IS_EMPTY error will return.\n - In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try - again later to issue the command. - \warning - In case an IP address in a string format is set as input, without any prefix (e.g. "1.2.3.4") the device will not - try to access the DNS and it will return the input address on the 'out_ip_addr' field - \par Example - - - Getting host by name: - \code - _u32 DestinationIP; - _u32 AddrSize; - _i16 SockId; - SlSockAddrIn_t Addr; - - sl_NetAppDnsGetHostByName("www.google.com", strlen("www.google.com"), &DestinationIP,SL_AF_INET); - - Addr.sin_family = SL_AF_INET; - Addr.sin_port = sl_Htons(80); - Addr.sin_addr.s_addr = sl_Htonl(DestinationIP); - AddrSize = sizeof(SlSockAddrIn_t); - SockId = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, 0); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByName) -_i16 sl_NetAppDnsGetHostByName(_i8 * pHostName,const _u16 NameLen, _u32* OutIpAddr,const _u8 Family ); -#endif - -/*! - \brief Return service attributes like IP address, port and text according to service name\n - The user sets a service name Full/Part (see example below), and should get: - - IP of service - - The port of service - - The text of service - Hence it can make a connection to the specific service and use it. - It is similar to sl_NetAppDnsGetHostByName method.\n - It is done by a single shot ipv4 & ipv6 (if enabled) query with PTR type on the service name. - The command that is sent is from constant parameters and variables parameters. - - \param[in] pServiceName Service name can be full or partial. \n - Example for full service name: - 1. PC1._ipp._tcp.local - 2. PC2_server._ftp._tcp.local \n - . - Example for partial service name: - 1. _ipp._tcp.local - 2. _ftp._tcp.local - - \param[in] ServiceLen The length of the service name (in_pService). - \param[in] Family IPv4 or IPv6 (SL_AF_INET , SL_AF_INET6). - \param[out] pAddr Contains the IP address of the service. - \param[out] pPort Contains the port of the service. - \param[out] pTextLen Has 2 options. One as Input field and the other one as output: - - Input: \n - Contains the max length of the text that the user wants to get.\n - It means that if the text len of service is bigger that its value than - the text is cut to inout_TextLen value. - - Output: \n - Contain the length of the text that is returned. Can be full text or part of the text (see above). - - \param[out] pText Contains the text of the service full or partial - - \return Zero on success,\n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system, - In this case try again later or increase MAX_CONCURRENT_ACTIONS\n - In case No service is found error SL_NETAPP_DNS_NO_ANSWER will be returned - \sa sl_NetAppDnsGetHostByName - \note The returns attributes belongs to the first service found. - There may be other services with the same service name that will response to the query. - The results of these responses are saved in the peer cache of the Device and should be read by another API.\n - - Only one sl_NetAppDnsGetHostByService can be handled at a time.\n - Calling this API while the same command is called from another thread, may result - in one of the two scenarios: - 1. The command will wait (internal) until the previous command finish, and then be executed. - 2. There are not enough resources and SL_POOL_IS_EMPTY error will return. - In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try - again later to issue the command. - - \warning Text length can be 120 bytes only -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByService) -_i16 sl_NetAppDnsGetHostByService(_i8 *pServiceName, /* string containing all (or only part): name + subtype + service */ - const _u8 ServiceLen, - const _u8 Family, /* 4-IPv4 , 16-IPv6 */ - _u32 pAddr[], - _u32 *pPort, - _u16 *pTextLen, /* in: max len , out: actual len */ - _i8 *pText - ); - -#endif - -/*! - \brief Get service list\n - Insert into out pBuffer a list of peer's services that are in the NWP without issuing any queries (relying on previous collected data).\n - The list is in a form of service struct. The user should chose the type - of the service struct like: - - Full service parameters with text. - - Full service parameters. - - Short service parameters (port and IP only) especially for tiny hosts. - - The different types of struct are made to give the - possibility to save memory in the host.\n - - The user can also chose how many max services to get and start point index - NWP peer cache.\n - For example: - 1. Get max of 3 full services from index 0. - - Up to 3 full services from index 0 are inserted into pBuffer (services that are in indexes 0,1,2). - 2. Get max of 4 full services from index 3. - - Up to 4 full services from index 3 are inserted into pBuffer (services that are in indexes 3,4,5,6). - 3. Get max of 2 int services from index 6. - - Up to 2 int services from index 6 are inserted into pBuffer (services that are in indexes 6,7). - See below - command parameters. - - \param[in] IndexOffset - The start index in the peer cache that from it the first service is returned. - \param[in] MaxServiceCount - The Max services that can be returned if existed or if not exceed the max index - in the peer cache - \param[in] Flags - an ENUM number that means which service struct to use (means which types of service to fill) - - use SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV4_TYPE for SlNetAppGetFullServiceWithTextIpv4List_t - - use SL_NETAPP_FULL_SERVICE_IPV4_TYPE for SlNetAppGetFullServiceIpv4List_t - - use SL_NETAPP_SHORT_SERVICE_IPV4_TYP SlNetAppGetShortServiceIpv4List_t - - use SL_NETAPP_FULL_SERVICE_IPV6_TYPE, SlNetAppGetFullServiceIpv6List_t - - use SL_NETAPP_SHORT_SERVICE_IPV6_TYPE SlNetAppGetShortServiceIpv6List_t - - use SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV6_TYPE SlNetAppGetFullServiceWithTextIpv6List_t - - \param[out] pBuffer - The Services are inserted into this buffer. In the struct form according to the bit that is set in the Flags - input parameter. - - \param[in] BufferLength - The allocated buffer length (pointed by pBuffer). - - \return ServiceFoundCount - The number of the services that were inserted into the buffer.\n - Zero means no service is found negative number means an error - \sa sl_NetAppMDNSRegisterService - \note - \warning - If the out pBuffer size is bigger than an RX packet(1480), than - an error is returned because there is no place in the RX packet.\n - The size is a multiply of MaxServiceCount and size of service struct(that is set - according to flag value). -*/ - -#if _SL_INCLUDE_FUNC(sl_NetAppGetServiceList) -_i16 sl_NetAppGetServiceList(const _u8 IndexOffset, - const _u8 MaxServiceCount, - const _u8 Flags, - _i8 *pBuffer, - const _u32 BufferLength - ); - -#endif - -/*! - \brief Unregister mDNS service\n - This function deletes the mDNS service from the mDNS package and the database. - - The mDNS service that is to be unregistered is a service that the application no longer wishes to provide. \n - The service name should be the full service name according to RFC - of the DNS-SD - meaning the value in name field in the SRV answer. - - Examples for service names: - 1. PC1._ipp._tcp.local - 2. PC2_server._ftp._tcp.local - - \param[in] pServiceName Full service name. \n - \param[in] ServiceNameLen The length of the service. - \param[in] Options bitwise parameters: \n - - SL_NETAPP_MDNS_OPTIONS_IS_UNIQUE_BIT bit 0 - service is unique per interface (means that the service needs to be unique) - - SL_NETAPP_MDNS_IPV6_IPV4_SERVICE bit 27 - add this service to IPv6 interface, if exist (default is IPv4 service only) - - SL_NETAPP_MDNS_IPV6_ONLY_SERVICE bit 28 - add this service to IPv6 interface, but remove it from IPv4 (only IPv6 is available) - - SL_NETAPP_MDNS_OPTION_UPDATE_TEXT bit 29 - for update text fields (without reregister the service) - - SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT bit 30 - for setting a non persistent service - - SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT bit 31 - for internal use if the service should be added or deleted (set means ADD). - - \return Zero on success, or negative error code on failure - \par Persistent - Optionally persistent - \sa sl_NetAppMDNSRegisterService - \note - \warning - The size of the service length should be smaller than 255. -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppMDNSUnRegisterService) -_i16 sl_NetAppMDNSUnRegisterService(const _i8 *pServiceName,const _u8 ServiceNameLen,_u32 Options); -#endif - -/*! - \brief Register a new mDNS service\n - This function registers a new mDNS service to the mDNS package and the DB. \n - This registered service is a service offered by the application. - The service name should be full service name according to RFC - of the DNS-SD - meaning the value in name field in the SRV answer.\n - Example for service name: - 1. PC1._ipp._tcp.local - 2. PC2_server._ftp._tcp.local - - If the option is_unique is set, mDNS probes the service name to make sure - it is unique before starting to announce the service on the network. - Instance is the instance portion of the service name. - - \param[in] ServiceNameLen The length of the service. - \param[in] TextLen The length of the service should be smaller than 64. - \param[in] Port The port on this target host port. - \param[in] TTL The TTL of the service - \param[in] Options bitwise parameters: \n - - SL_NETAPP_MDNS_OPTIONS_IS_UNIQUE_BIT bit 0 - service is unique per interface (means that the service needs to be unique) - - SL_NETAPP_MDNS_IPV6_IPV4_SERVICE bit 27 - add this service to IPv6 interface, if exist (default is IPv4 service only) - - SL_NETAPP_MDNS_IPV6_ONLY_SERVICE bit 28 - add this service to IPv6 interface, but remove it from IPv4 (only IPv6 is available) - - SL_NETAPP_MDNS_OPTION_UPDATE_TEXT bit 29 - for update text fields (without reregister the service) - - SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT bit 30 - for setting a non persistent service - - SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT bit 31 - for internal use if the service should be added or deleted (set means ADD). - - \param[in] pServiceName The service name. - \param[in] pText The description of the service. - should be as mentioned in the RFC - (according to type of the service IPP,FTP...) - - \return Zero on success, or negative error code on failure - - \par Persistent - Optionally persistent - - \sa sl_NetAppMDNSUnRegisterService - - \warning 1) Temporary - there is an allocation on stack of internal buffer. - Its size is SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. \n - It means that the sum of the text length and service name length cannot be bigger than - SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH.\n - If it is - An error is returned. \n - 2) According to now from certain constraints the variables parameters are set in the - attribute part (contain constant parameters) - - \par Examples: - - - Register a new service: - \code - const signed char AddService[40] = "PC1._ipp._tcp.local"; - _u32 Options; - - Options = SL_NETAPP_MDNS_OPTIONS_IS_UNIQUE_BIT | SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT; - sl_NetAppMDNSRegisterService(AddService,sizeof(AddService),"Service 1;payper=A3;size=5",strlen("Service 1;payper=A3;size=5"),1000,120,Options); - \endcode -
- - - Update text for existing service: - \code - Please Note! Update is for text only! Important to apply the same persistent flag options as original service registration.\n - - Options = SL_NETAPP_MDNS_OPTION_UPDATE_TEXT | SL_NETAPP_MDNS_OPTIONS_IS_NOT_PERSISTENT; - sl_NetAppMDNSRegisterService(AddService,sizeof(AddService),"Service 5;payper=A4;size=10",strlen("Service 5;payper=A4;size=10"),1000,120,Options); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppMDNSRegisterService) -_i16 sl_NetAppMDNSRegisterService( const _i8* pServiceName, - const _u8 ServiceNameLen, - const _i8* pText, - const _u8 TextLen, - const _u16 Port, - const _u32 TTL, - _u32 Options); -#endif - -/*! - \brief send ICMP ECHO_REQUEST to network hosts - - Ping uses the ICMP protocol's mandatory ECHO_REQUEST - - \param[in] pPingParams Pointer to the ping request structure: - - If flags parameter is set to 0, ping will report back once all requested pings are done (as defined by TotalNumberOfAttempts). - - If flags parameter is set to 1, ping will report back after every ping, for TotalNumberOfAttempts. - - If flags parameter is set to 2, ping will stop after the first successful ping, and report back for the successful ping, as well as any preceding failed ones. \n - - If flags parameter is set to 4, for ipv4 - don`t fragment the ping packet. This flag can be set with other flags. - For stopping an ongoing ping activity, set parameters IP address to 0 - \param[in] Family SL_AF_INET or SL_AF_INET6 - \param[out] pReport Ping pReport - \param[out] pPingCallback Callback function upon completion.\n - If callback is NULL, the API is blocked until data arrives - - \return Zero on success, or negative error code on failure.\n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa - \note Only one sl_NetAppPing can be handled at a time. - Calling this API while the same command is called from another thread, may result - in one of the two scenarios: - 1. The command will wait (internal) until the previous command finish, and then be executed. - 2. There are not enough resources and SL_POOL_IS_EMPTY error will return. - In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try - again later to issue the command. - \warning - \par Example: - - - Sending 20 ping requests and reporting results to a callback routine when - all requests are sent: - \code - // callback routine - void pingRes(SlNetAppPingReport_t* pReport) - { - // handle ping results - } - - // ping activation - void PingTest() - { - SlNetAppPingReport_t report; - SlNetAppPingCommand_t pingCommand; - - pingCommand.Ip = SL_IPV4_VAL(10,1,1,200); // destination IP address is 10.1.1.200 - pingCommand.PingSize = 150; // size of ping, in bytes - pingCommand.PingIntervalTime = 100; // delay between pings, in milliseconds - pingCommand.PingRequestTimeout = 1000; // timeout for every ping in milliseconds - pingCommand.TotalNumberOfAttempts = 20; // max number of ping requests. 0 - forever - pingCommand.Flags = 0; // report only when finished - - sl_NetAppPing( &pingCommand, SL_AF_INET, &report, pingRes ); - } - \endcode -
- - - Stopping Ping command: - \code - Status = sl_NetAppPing(0, 0, 0, 0 ); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppPing) -_i16 sl_NetAppPing(const SlNetAppPingCommand_t* pPingParams,const _u8 Family, SlNetAppPingReport_t *pReport, const P_SL_DEV_PING_CALLBACK pPingCallback); -#endif - -/*! - \brief Setting network application configurations - - \param[in] AppId Application id, could be one of the following: - - SL_NETAPP_HTTP_SERVER_ID - - SL_NETAPP_DHCP_SERVER_ID (AP Role only) - - SL_NETAPP_MDNS_ID - - SL_NETAPP_DNS_SERVER_ID - - SL_NETAPP_DEVICE_ID - - SL_NETAPP_DNS_CLIENT_ID - - \param[in] Option Set option, could be one of the following: - - For SL_NETAPP_HTTP_SERVER_ID - - SL_NETAPP_HTTP_PRIMARY_PORT_NUMBER - - SL_NETAPP_HTTP_AUTH_CHECK - - SL_NETAPP_HTTP_AUTH_NAME - - SL_NETAPP_HTTP_AUTH_PASSWORD - - SL_NETAPP_HTTP_AUTH_REALM - - SL_NETAPP_HTTP_ROM_PAGES_ACCESS - - SL_NETAPP_HTTP_SECONDARY_PORT_NUMBER - - SL_NETAPP_HTTP_SECONDARY_PORT_ENABLE - - SL_NETAPP_HTTP_PRIMARY_PORT_SECURITY_MODE - - SL_NETAPP_HTTP_PRIVATE_KEY_FILENAME - - SL_NETAPP_HTTP_DEVICE_CERTIFICATE_FILENAME - - SL_NETAPP_HTTP_CA_CERTIFICATE_FILE_NAME - - SL_NETAPP_HTTP_TEMP_REGISTER_MDNS_SERVICE_NAME - - SL_NETAPP_HTTP_TEMP_UNREGISTER_MDNS_SERVICE_NAME - - SL_NETAPP_HTTP_TIMEOUT - - For SL_NETAPP_DHCP_SERVER_ID: - - SL_NETAPP_DHCP_SRV_BASIC_OPT - - For SL_NETAPP_MDNS_ID: - - SL_NETAPP_MDNS_CONT_QUERY_OPT - - SL_NETAPP_MDNS_QEVETN_MASK_OPT - - SL_NETAPP_MDNS_TIMING_PARAMS_OPT - - For SL_NETAPP_DEVICE_ID: - - SL_NETAPP_DEVICE_URN - - SL_NETAPP_DEVICE_DOMAIN - - SL_NETAPP_DEVICE_NAME - - For SL_NETAPP_DNS_CLIENT_ID: - - SL_NETAPP_DNS_CLIENT_TIME - - SL_NETAPP_DNS_CLIENT_CACHE_ENABLE - - SL_NETAPP_DNS_CLIENT_CACHE_CLEAR - \param[in] OptionLen Option structure length - - \param[in] pOptionValue Pointer to the option structure - - \par Persistent - \par - Reset: - - SL_NETAPP_DEVICE_DOMAIN - - SL_NETAPP_DHCP_SRV_BASIC_OPT \n - \par - Non- Persistent: - - SL_NETAPP_HTTP_TIMEOUT - - SL_NETAPP_HTTP_TEMP_REGISTER_MDNS_SERVICE_NAME - - SL_NETAPP_HTTP_TEMP_UNREGISTER_MDNS_SERVICE_NAME \n - \par - System Persistent: - - SL_NETAPP_HTTP_PRIMARY_PORT_NUMBER - - SL_NETAPP_HTTP_AUTH_CHECK - - SL_NETAPP_HTTP_AUTH_NAME - - SL_NETAPP_HTTP_AUTH_PASSWORD - - SL_NETAPP_HTTP_AUTH_REALM - - SL_NETAPP_HTTP_ROM_PAGES_ACCESS - - SL_NETAPP_HTTP_SECONDARY_PORT_NUMBER - - SL_NETAPP_HTTP_SECONDARY_PORT_ENABLE - - SL_NETAPP_HTTP_PRIMARY_PORT_SECURITY_MODE - - SL_NETAPP_HTTP_PRIVATE_KEY_FILENAME - - SL_NETAPP_HTTP_DEVICE_CERTIFICATE_FILENAME - - SL_NETAPP_HTTP_CA_CERTIFICATE_FILE_NAME - - SL_NETAPP_MDNS_CONT_QUERY_OPT - - SL_NETAPP_MDNS_QEVETN_MASK_OPT - - SL_NETAPP_MDNS_TIMING_PARAMS_OPT - - SL_NETAPP_DEVICE_URN - - SL_NETAPP_DEVICE_ID - - SL_NETAPP_DNS_CLIENT_ID - - \return Zero on success, or negative value if an error occurred. - \sa sl_NetAppGet - \note - \warning - \par Example - - - Setting DHCP Server (AP mode) parameters example: - \code - SlNetAppDhcpServerBasicOpt_t dhcpParams; - _u8 outLen = sizeof(SlNetAppDhcpServerBasicOpt_t); - dhcpParams.lease_time = 4096; // lease time (in seconds) of the IP Address - dhcpParams.ipv4_addr_start = SL_IPV4_VAL(192,168,1,10); // first IP Address for allocation. IP Address should be set as Hex number - i.e. 0A0B0C01 for (10.11.12.1) - dhcpParams.ipv4_addr_last = SL_IPV4_VAL(192,168,1,16); // last IP Address for allocation. IP Address should be set as Hex number - i.e. 0A0B0C01 for (10.11.12.1) - sl_NetAppStop(SL_NETAPP_DHCP_SERVER_ID); // Stop DHCP server before settings - sl_NetAppSet(SL_NETAPP_DHCP_SERVER_ID, SL_NETAPP_DHCP_SRV_BASIC_OPT, outLen, (_u8* )&dhcpParams); // set parameters - sl_NetAppStart(SL_NETAPP_DHCP_SERVER_ID); // Start DHCP server with new settings - \endcode -
- - - Setting Device URN name:
- Device name, maximum length of 32 characters - Device name affects URN name, and WPS file "device name" in WPS I.E (STA-WPS / P2P) - In case no device URN name set, the default name is "mysimplelink" - In case of setting the device name with length 0, device will return to default name "mysimplelink" - Allowed characters in device name are: 'a - z' , 'A - Z' , '0-9' and '-' - \code - _u8 *my_device = "MY-SIMPLELINK-DEV"; - sl_NetAppSet (SL_NETAPP_DEVICE_ID, SL_NETAPP_DEVICE_URN, strlen(my_device), (_u8 *) my_device); - \endcode -
- - - Register new temporary HTTP service name for MDNS (not persistent): - \code - _u8 *my_http_temp_name = "New - Bonjour Service Name"; - sl_NetAppSet (SL_NETAPP_HTTP_SERVER_ID, SL_NETAPP_HTTP_TEMP_REGISTER_MDNS_SERVICE_NAME, strlen(my_http_temp_name), (_u8 *) my_http_temp_name); - \endcode -
- - - Remove registration of current HTTP internal MDNS service (not persistent) : - \code - _u8 *old_http_name = "0800285A7891@mysimplelink-022"; - sl_NetAppSet (SL_NETAPP_HTTP_SERVER_ID, SL_NETAPP_HTTP_TEMP_UNREGISTER_MDNS_SERVICE_NAME, strlen(old_http_name), (_u8 *) old_http_name); - \endcode -
- - - Set DNS client time example:
- Set DNS client (sl_NetAppDnsGetHostByName) timeout, two parameters max_response_time and number_retries. - number_retries: Max number of DNS request before sl_NetAppDnsGetHostByName failed, (up to 100 retries). - max_response_time: DNS request timeout changed every retry, it`s start with 100 millisecond and increased every retry up to max_response_time milliseconds, (up to 2 seconds) - \code - SlNetAppDnsClientTime_t time; - time.MaxResponseTime = 2000; - time.NumOfRetries = 30; - sl_NetAppSet (SL_NETAPP_DNS_CLIENT_ID, SL_NETAPP_DNS_CLIENT_TIME, sizeof(time), (_u8 *)&time); - - \endcode -
- - - Clear the DNS caching:
- \code - sl_NetAppSet (SL_NETAPP_DNS_CLIENT_ID, SL_NETAPP_DNS_CLIENT_CACHE_CLEAR, 0, 0); - \endcode -
- - - Enable / Disable the DNS caching:
- By deafult the DNS caching is enabled, set 0 to disable the DNS caching. - \code - _u8 enabled = 1; - sl_NetAppSet (SL_NETAPP_DNS_CLIENT_ID, SL_NETAPP_DNS_CLIENT_CACHE_ENABLE,sizeof(enabled),&enabled); - \endcode -
- - - Start MDNS continuous querys:
- In a continuous mDNS query mode, the device keeps sending queries to the network according to a specific service name. - The query will be sent in IPv4 and IPv6 (if enabled) format. To see the completed list of responding services sl_NetAppGetServiceList() need to be called - \code - const signed char AddService[40] = "Printer._ipp._tcp.local"; - _i16 Status; - - Status = sl_NetAppSet(SL_NETAPP_MDNS_ID, SL_NETAPP_MDNS_CONT_QUERY_OPT,strlen(AddService) , &AddService); - \endcode -
- - - Stop MDNS: - \code - Status = sl_NetAppSet(SL_NETAPP_MDNS_ID, SL_NETAPP_MDNS_CONT_QUERY_OPT,0 , 0); - \endcode -
- - - Set MDNS timing parameters for service advertisement:
- This option allows to control and reconfigures the timing parameters for service advertisement - \code - SlNetAppServiceAdvertiseTimingParameters_t Timing; - _i16 Status; - - Timing.t = 200; // 2 seconds - Timing.p = 2; // 2 repetitions - Timing.k = 2; // Telescopic factor 2 - Timing.RetransInterval = 0; - Timing.Maxinterval = 0xFFFFFFFF; - Timing.max_time = 5; - - Status = sl_NetAppSet(SL_NETAPP_MDNS_ID, SL_NETAPP_MDNS_TIMING_PARAMS_OPT,sizeof(Timing),&Timing); - - \endcode -
- - - User-defined service types to monitor:
- In cases that the user decides not to get responses from certain - types of services it should set the adapt bit in the event mask that is related to: - \code - // bit 0: _ipp - // bit 1: _device-info - // bit 2: _http - // bit 3: _https - // bit 4: _workstation - // bit 5: _guid - // bit 6: _h323 - // bit 7: _ntp - // bit 8: _objective - // bit 9: _rdp - // bit 10: _remote - // bit 11: _rtsp - // bit 12: _sip - // bit 13: _smb - // bit 14: _soap - // bit 15: _ssh - // bit 16: _telnet - // bit 17: _tftp - // bit 18: _xmpp-client - // bit 19: _raop - - _u32 EventMask; - _i16 Status; - - EventMask = BIT0 | BIT1 | BIT18; - Status = sl_NetAppSet(SL_NETAPP_MDNS_ID, SL_NETAPP_MDNS_QEVETN_MASK_OPT,sizeof(EventMask),&EventMask); - \endcode -
-*/ -#if _SL_INCLUDE_FUNC(sl_NetAppSet) -_i16 sl_NetAppSet(const _u8 AppId ,const _u8 Option,const _u8 OptionLen,const _u8 *pOptionValue); -#endif - -/*! - \brief Getting network applications configurations - - \param[in] AppId Application id, could be one of the following: \n - - SL_NETAPP_HTTP_SERVER_ID - - SL_NETAPP_DHCP_SERVER_ID - - SL_NETAPP_DNS_SERVER_ID - - SL_NETAPP_DEVICE_ID - - SL_NETAPP_DNS_CLIENT_ID - - \param[in] Option Get option, could be one of the following: \n - - SL_NETAPP_DHCP_SERVER_ID: - - SL_NETAPP_DHCP_SRV_BASIC_OPT - - SL_NETAPP_HTTP_SERVER_ID: - - SL_NETAPP_HTTP_PRIMARY_PORT_NUMBER - - SL_NETAPP_HTTP_AUTH_CHECK - - SL_NETAPP_HTTP_AUTH_NAME - - SL_NETAPP_HTTP_AUTH_PASSWORD - - SL_NETAPP_HTTP_AUTH_REALM - - SL_NETAPP_HTTP_ROM_PAGES_ACCESS - - SL_NETAPP_HTTP_SECONDARY_PORT_NUMBER - - SL_NETAPP_HTTP_SECONDARY_PORT_ENABLE - - SL_NETAPP_HTTP_PRIMARY_PORT_SECURITY_MODE - - SL_NETAPP_MDNS_ID: - - SL_NETAPP_MDNS_CONT_QUERY_OPT - - SL_NETAPP_MDNS_QEVETN_MASK_OPT - - SL_NETAPP_MDNS_TIMING_PARAMS_OPT - - SL_NETAPP_DEVICE_ID: - - SL_NETAPP_DEVICE_URN - - SL_NETAPP_DEVICE_DOMAIN - - SL_NETAPP_DNS_CLIENT_ID: - - SL_NETAPP_DNS_CLIENT_TIME - - \param[in] pOptionLen The length of the allocated memory as input, when the - function complete, the value of this parameter would be - the len that actually read from the device.\n - If the device return length that is longer from the input - value, the function will cut the end of the returned structure - and will return ESMALLBUF - - \param[out] pOptionValue pointer to the option structure which will be filled with the response from the device - - \return Zero on success, or negative value if an error occurred. - - \sa sl_NetAppSet - \note - \warning - \par Example - - - Getting DHCP Server parameters example: - \code - SlNetAppDhcpServerBasicOpt_t dhcpParams; - _u8 outLen = sizeof(SlNetAppDhcpServerBasicOpt_t); - sl_NetAppGet(SL_NETAPP_DHCP_SERVER_ID, SL_NETAPP_SET_DHCP_SRV_BASIC_OPT, &outLen, (_u8* )&dhcpParams); - - printf("DHCP Start IP %d.%d.%d.%d End IP %d.%d.%d.%d Lease time seconds %d\n", - SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,3),SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,2), - SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,1),SL_IPV4_BYTE(dhcpParams.ipv4_addr_start,0), - SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,3),SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,2), - SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,1),SL_IPV4_BYTE(dhcpParams.ipv4_addr_last,0), - dhcpParams.lease_time); - \endcode -
- - - Getting device URN name:
- Maximum length of 32 characters of device name. - Device name affects URN name, own SSID name in AP mode, and WPS file "device name" in WPS I.E (STA-WPS / P2P) - in case no device URN name set, the default name is "mysimplelink" - \code - _u8 my_device_name[SL_NETAPP_MAX_DEVICE_URN_LEN]; - sl_NetAppGet (SL_NETAPP_DEVICE_ID, SL_NETAPP_DEVICE_URN, strlen(my_device_name), (_u8 *)my_device_name); - \endcode -
- - - Getting DNS client time:
- Get DNS client (sl_NetAppDnsGetHostByName) timeout, two parameters max_response_time and number_retries. - number_retries: Max number of DNS request before sl_NetAppDnsGetHostByName failed. - max_response_time: DNS request timeout changed every retry, it`s start with 100 millisecond and increased every retry up to max_response_time milliseconds - \code - SlNetAppDnsClientTime_t time; - _u8 pOptionLen = sizeof(time); - sl_NetAppGet (SL_NETAPP_DNS_CLIENT_ID, SL_NETAPP_DNS_CLIENT_TIME, &pOptionLen, (_u8 *)&time); - \endcode -
- - - get DNS caching mode:
- By deafult the DNS caching is enabled, 0 - disable, 1 - enabled. - \code - _u8 enabled; - _u8 pOptionLen = sizeof(enabled) - sl_NetAppGet (SL_NETAPP_DNS_CLIENT_ID, SL_NETAPP_DNS_CLIENT_CACHE_ENABLE, &pOptionLen,&enabled); - \endcode -
- - - Getting active applications:
- Get active applications for active role. return value is mask of the active application (similar defines as sl_NetAppStart\sl_NetAppStop): - \code - _u32 AppBitMap; - _u8 pOptionLen = sizeof(AppBitMap); - sl_NetAppGet (SL_NETAPP_STATUS, SL_NETAPP_STATUS_ACTIVE_APP, &pOptionLen, (_u8 *)&AppBitMap); - - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppGet) -_i16 sl_NetAppGet(const _u8 AppId, const _u8 Option,_u8 *pOptionLen, _u8 *pOptionValue); -#endif - -/*! - \brief Function for sending Netapp response or data following a Netapp request event (i.e. HTTP GET request) - - - \param[in] Handle Handle to send the data to. Should match the handle received in the Netapp request event - \param[in] DataLen Data Length - \param[in] pData Data to send. Can be just data payload or metadata (depends on flags) - \param[out] Flags Can have the following values: - - SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION - More data will arrive in subsequent calls to NetAppSend - - SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA - 0 - data is payload, 1 - data is metadata - - SL_NETAPP_REQUEST_RESPONSE_FLAGS_ACCUMULATION - The network processor should accumulate the data chunks and will process it when it is completelly received - - \return Zero on success, or negative error code on failure - - \sa sl_NetAppRecv - \note - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppSend) -_u16 sl_NetAppSend( _u16 Handle, _u16 DataLen, _u8 *pData, _u32 Flags); -#endif - -/*! - \brief Function for retrieving data from the network processor following a Netapp request event (i.e. HTTP POST request) - - \param[in] Handle Handle to receive data from. Should match the handle received in the Netapp request event - \param[in,out] *DataLen Max buffer size (in) / Actual data received (out) - \param[out] *pData Data received - \param[in,out] *Flags Can have the following values: - - SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION (out) - - More data is pending in the network processor. Application should continue reading the data by calling sl_NetAppRecv again - - \return Zero on success, or negative error code on failure - - \sa sl_NetAppSend - \note - \warning handle is received in the sl_NetAppRequestHandler callback. Handle is valid until all data is receive from the network processor. -*/ -#if _SL_INCLUDE_FUNC(sl_NetAppRecv) -_SlReturnVal_t sl_NetAppRecv( _u16 Handle, _u16 *DataLen, _u8 *pData, _u32 *Flags); -#endif - -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __NETAPP_H__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/netcfg.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/netcfg.h deleted file mode 100644 index fcec06104cc..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/netcfg.h +++ /dev/null @@ -1,698 +0,0 @@ -/* - * netcfg.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - - -#ifndef __NETCFG_H__ -#define __NETCFG_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup NetCfg - \short Controls the configuration of the device addresses (i.e. IP and MAC addresses) - -*/ - -/*! - - \addtogroup NetCfg - @{ - -*/ - - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#define SL_MAC_ADDR_LEN (6) -#define SL_IPV6_ADDR_LEN (16) -#define SL_IPV4_VAL(add_3,add_2,add_1,add_0) ((((_u32)add_3 << 24) & 0xFF000000) | (((_u32)add_2 << 16) & 0xFF0000) | (((_u32)add_1 << 8) & 0xFF00) | ((_u32)add_0 & 0xFF) ) -#define SL_IPV6_VAL(add_1,add_2) ((((_u32)add_1 << 16) & 0xFFFF0000) | (((_u32)add_2 ) & 0x0000FFFF) ) -#define SL_IPV4_BYTE(val,index) ( (val >> (index*8)) & 0xFF ) - - -#define SL_NETCFG_IF_IPV6_STA_LOCAL (0x4) /* disable ipv6 local */ -#define SL_NETCFG_IF_IPV6_STA_GLOBAL (0x8) /* disable ipv6 global */ -#define SL_NETCFG_IF_DISABLE_IPV4_DHCP (0x40) /* disable ipv4 dhcp */ -#define SL_NETCFG_IF_IPV6_LOCAL_STATIC (0x80) /* enable ipv6 local static */ -#define SL_NETCFG_IF_IPV6_LOCAL_STATELESS (0x100) /* enable ipv6 local stateless */ -#define SL_NETCFG_IF_IPV6_LOCAL_STATEFUL (0x200) /* enable ipv6 local statefull */ -#define SL_NETCFG_IF_IPV6_GLOBAL_STATIC (0x400) /* enable ipv6 global static */ -#define SL_NETCFG_IF_IPV6_GLOBAL_STATEFUL (0x800) /* enable ipv6 global statefull */ -#define SL_NETCFG_IF_DISABLE_IPV4_LLA (0x1000) /* disable LLA feature. Relevant only in IPV4 */ -#define SL_NETCFG_IF_ENABLE_DHCP_RELEASE (0x2000) /* Enables DHCP release when WLAN disconnect command is issued */ -#define SL_NETCFG_IF_IPV6_GLOBAL_STATELESS (0x4000) /* enable ipv6 global stateless */ -#define SL_NETCFG_IF_DISABLE_FAST_RENEW (0x8000) /* fast renew disabled */ - - -#define SL_NETCFG_IF_STATE (0) -#define SL_NETCFG_ADDR_DHCP (1) -#define SL_NETCFG_ADDR_DHCP_LLA (2) -#define SL_NETCFG_ADDR_STATIC (4) -#define SL_NETCFG_ADDR_STATELESS (5) -#define SL_NETCFG_ADDR_STATEFUL (6) -#define SL_NETCFG_ADDR_RELEASE_IP_SET (7) -#define SL_NETCFG_ADDR_RELEASE_IP_OFF (8) -#define SL_NETCFG_ADDR_ENABLE_FAST_RENEW (9) -#define SL_NETCFG_ADDR_DISABLE_FAST_RENEW (10) -#define SL_NETCFG_ADDR_FAST_RENEW_MODE_NO_WAIT_ACK (11) -#define SL_NETCFG_ADDR_FAST_RENEW_MODE_WAIT_ACK (12) - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ -typedef enum -{ - SL_NETCFG_MAC_ADDRESS_SET = 1, - SL_NETCFG_MAC_ADDRESS_GET = 2, - SL_NETCFG_AP_STATIONS_NUM_CONNECTED = 3, - SL_NETCFG_AP_STATIONS_INFO_LIST = 4, - SL_NETCFG_AP_STATION_DISCONNECT = 5, - SL_NETCFG_IF = 6, - SL_NETCFG_IPV4_STA_ADDR_MODE = 7, - SL_NETCFG_IPV4_AP_ADDR_MODE = 8, - SL_NETCFG_IPV6_ADDR_LOCAL = 9, - SL_NETCFG_IPV6_ADDR_GLOBAL = 10, - SL_NETCFG_IPV4_DHCP_CLIENT = 11, - SL_NETCFG_IPV4_DNS_CLIENT = 12, - SL_NETCFG_IPV6_DNS_CLIENT = 13, - MAX_SETTINGS = 0xFF -}SlNetCfg_e; - -typedef struct -{ - _u32 DnsSecondServerAddr; -}SlNetCfgIpV4DnsClientArgs_t; - -typedef struct -{ - _u32 DnsSecondServerAddr[4]; -}SlNetCfgIpV6DnsClientArgs_t; - - -typedef struct -{ - _u32 Ip; - _u32 Gateway; - _u32 Mask; - _u32 Dns[2]; - _u32 DhcpServer; - _u32 LeaseTime; - _u32 TimeToRenew; - _u8 DhcpState; - _u8 Reserved[3]; -} SlNetCfgIpv4DhcpClient_t; - -typedef enum -{ - SL_NETCFG_DHCP_CLIENT_UNKNOWN = 0, - SL_NETCFG_DHCP_CLIENT_DISABLED, - SL_NETCFG_DHCP_CLIENT_ENABLED, - SL_NETCFG_DHCP_CLIENT_BOUND, - SL_NETCFG_DHCP_CLIENT_RENEW, - SL_NETCFG_DHCP_CLIENT_REBIND -}SlNetCfgIpv4DhcpClientState_e; - - -typedef enum -{ - SL_NETCFG_DHCP_OPT_DISABLE_LLA = 0x2, /* 1=LLA disabled, 0=LLA enabled. */ - SL_NETCFG_DHCP_OPT_RELEASE_IP_BEFORE_DISCONNECT = 0x4, /* 1=DHCP release enabled, 0=DHCP release disabled */ - MAX_SL_NETCFG_DHCP_OPT = 0xFF -} SlNetCfgDhcpOption_e; - -typedef struct -{ - _u32 Ip; - _u32 IpMask; - _u32 IpGateway; - _u32 IpDnsServer; -}SlNetCfgIpV4Args_t; - -typedef struct -{ - _u32 Ip[4]; - _u32 IpDnsServer[4]; - _u32 IpV6Flags; /* bit 0: Indicate if the address is valid for use in the network (IPv6 DAD completed) . If not, try again later or set a different address. 1=Valid. Relevant for sl_NetCfgGet only. */ -}SlNetCfgIpV6Args_t; - -#define _SL_NETCFG_IPV6_ADDR_BIT_STATUS 0x01 -#define SL_IS_IPV6_ADDR_VALID(IpV6Flags) (IpV6Flags & _SL_NETCFG_IPV6_ADDR_BIT_STATUS) - -#define NET_CFG_STA_INFO_STATUS_DHCP_ADDR 1 - -typedef struct -{ - _u32 Ip; - _u8 MacAddr[6]; - _u16 Status; - _u8 Name[32]; -} SlNetCfgStaInfo_t; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - \brief Setting network configurations - - \param[in] ConfigId Configuration id: - - SL_NETCFG_IF - - SL_NETCFG_IPV4_STA_ADDR_MODE - - SL_NETCFG_IPV6_ADDR_LOCAL - - SL_NETCFG_IPV6_ADDR_GLOBAL - - SL_NETCFG_IPV4_AP_ADDR_MODE - - SL_NETCFG_MAC_ADDRESS_SET - - SL_NETCFG_AP_STATION_DISCONNECT - \param[in] ConfigOpt Configurations option: - - SL_NETCFG_IF_STATE - - SL_NETCFG_ADDR_DHCP - - SL_NETCFG_ADDR_DHCP_LLA - - SL_NETCFG_ADDR_STATIC - - SL_NETCFG_ADDR_STATELESS - - SL_NETCFG_ADDR_STATEFUL - - SL_NETCFG_ADDR_RELEASE_IP_SET - - SL_NETCFG_ADDR_RELEASE_IP_OFF - \param[in] ConfigLen Configurations len - \param[in] pValues Configurations values - \par Persistent - \par - Reset: - - SL_NETCFG_MAC_ADDRESS_SET - - SL_NETCFG_IPV4_AP_ADDR_MODE - \par - Non- Persistent: - - SL_NETCFG_AP_STATION_DISCONNECT - \par - System Persistent: - - SL_NETCFG_IPV4_STA_ADDR_MODE - - SL_NETCFG_IF - - SL_NETCFG_IPV6_ADDR_LOCAL - - SL_NETCFG_IPV6_ADDR_GLOBAL - - SL_NETCFG_IPV6_DNS_CLIENT - - \return Non-negative value on success, or -1 for failure - \sa sl_NetCfgGet - \note - \warning - - \par Examples - - - SL_NETCFG_MAC_ADDRESS_SET:
- Setting MAC address to the Device. - The new MAC address will override the default MAC address and it be saved in the FileSystem. - Requires restarting the device for updating this setting. - \code - _u8 MAC_Address[6]; - MAC_Address[0] = 0x8; - MAC_Address[1] = 0x0; - MAC_Address[2] = 0x28; - MAC_Address[3] = 0x22; - MAC_Address[4] = 0x69; - MAC_Address[5] = 0x31; - sl_NetCfgSet(SL_NETCFG_MAC_ADDRESS_SET,1,SL_MAC_ADDR_LEN,(_u8 *)MAC_Address); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV4_STA_ADDR_MODE
: - Setting/Releasing a DHCP/DHCP LLA /STATIC STA IP address - - - SL_NETCFG_ADDR_STATIC:
- Setting a static IP address to the device working in STA mode or P2P client. - The IP address will be stored in the FileSystem. - \code - SlNetCfgIpV4Args_t ipV4; - ipV4.Ip = (_u32)SL_IPV4_VAL(10,1,1,201); // _u32 IP address - ipV4.IpMask = (_u32)SL_IPV4_VAL(255,255,255,0); // _u32 Subnet mask for this STA/P2P - ipV4.IpGateway = (_u32)SL_IPV4_VAL(10,1,1,1); // _u32 Default gateway address - ipV4.IpDnsServer = (_u32)SL_IPV4_VAL(8,16,32,64); // _u32 DNS server address - - sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_STATIC,sizeof(SlNetCfgIpV4Args_t),(_u8 *)&ipV4); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_ADDR_DHCP:
- Setting IP address by DHCP to FileSystem using WLAN sta mode or P2P client. - This should be done once if using Serial Flash. - This is the system's default mode for acquiring an IP address after WLAN connection. - \code - sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_DHCP,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_ADDR_DHCP_LLA:
- Setting DHCP LLA will runs LLA mechanism in case DHCP fails to acquire an address - SL_NETCFG_DHCP_OPT_RELEASE_IP_BEFORE_DISCONNECT - If set, enables sending a DHCP release frame to the server if user issues a WLAN disconnect command. - \code - sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_DHCP_LLA,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_ADDR_RELEASE_IP_SET:
- Setting release ip before disconnect enables sending a DHCP release frame to the server if user issues a WLAN disconnect command. - \code - sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_RELEASE_IP_SET,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_ADDR_RELEASE_IP_OFF:
- Setting release ip before disconnect disables sending a DHCP release frame to the server if user issues a WLAN disconnect command. - \code - sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_RELEASE_IP_OFF,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV4_AP_ADDR_MODE:
- Setting a static IP address to the device working in AP mode or P2P go. - The IP address will be stored in the FileSystem. Requires restart. - \code - SlNetCfgIpV4Args_t ipV4; - ipV4.Ip = (_u32)SL_IPV4_VAL(10,1,1,201); // _u32 IP address - ipV4.IpMask = (_u32)SL_IPV4_VAL(255,255,255,0); // _u32 Subnet mask for this AP/P2P - ipV4.IpGateway = (_u32)SL_IPV4_VAL(10,1,1,1); // _u32 Default gateway address - ipV4.IpDnsServer = (_u32)SL_IPV4_VAL(8,16,32,64); // _u32 DNS server address - - sl_NetCfgSet(SL_NETCFG_IPV4_AP_ADDR_MODE,SL_NETCFG_ADDR_STATIC,sizeof(SlNetCfgIpV4Args_t),(_u8 *)&ipV4); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IF:
- Enable\Disable IPV6 interface - Local or/and Global address (Global could not be enabled without Local) - \code - _u32 IfBitmap = 0; - - IfBitmap = SL_NETCFG_IF_IPV6_STA_LOCAL | SL_NETCFG_IF_IPV6_STA_GLOBAL; - sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV6_ADDR_LOCAL:
- Setting a IPv6 Local static address to the device working in STA mode. - The IP address will be stored in the FileSystem. Requires restart. - \code - SlNetCfgIpV6Args_t ipV6; - _u32 IfBitmap = 0; - - IfBitmap = SL_NETCFG_IF_IPV6_STA_LOCAL; - sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); - - ipV6.Ip[0] = 0xfe800000; - ipV6.Ip[1] = 0x00000000; - ipV6.Ip[2] = 0x00004040; - ipV6.Ip[3] = 0x0000ce65; - - sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_LOCAL,SL_NETCFG_ADDR_STATIC,sizeof(SlNetCfgIpV6Args_t),(_u8 *)&ipV6); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV6_ADDR_LOCAL:
- Setting a IPv6 Local stateless address to the device working in STA mode. - The IP address will be stored in the FileSystem. Requires restart. - \code - _u32 IfBitmap = 0; - IfBitmap = SL_NETCFG_IF_IPV6_STA_LOCAL; - sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); - sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_LOCAL,SL_NETCFG_ADDR_STATELESS,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV6_ADDR_LOCAL:
- Setting a IPv6 Local statefull address to the device working in STA mode. - The IP address will be stored in the FileSystem. Requires restart. - \code - _u32 IfBitmap = 0; - - IfBitmap = SL_NETCFG_IF_IPV6_STA_LOCAL; - sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); - sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_LOCAL,SL_NETCFG_ADDR_STATEFUL,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV6_ADDR_GLOBAL:
- Setting a IPv6 Global static address to the device working in STA mode. - The IP address will be stored in the FileSystem. Requires restart. - \code - SlNetCfgIpV6Args_t ipV6; - _u32 IfBitmap = 0; - - ipV6.Ip[0] = 0xfe80; - ipV6.Ip[1] = 0x03a; - ipV6.Ip[2] = 0x4040; - ipV6.Ip[3] = 0xce65; - - ipV6.IpDnsServer[0] = 0xa780; - ipV6.IpDnsServer[1] = 0x65e; - ipV6.IpDnsServer[2] = 0x8; - ipV6.IpDnsServer[3] = 0xce00; - - IfBitmap = SL_NETCFG_IF_IPV6_STA_GLOBAL; - sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); - sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_GLOBAL,SL_NETCFG_ADDR_STATIC,sizeof(SlNetCfgIpV6Args_t),(_u8 *)&ipV6); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_IPV6_ADDR_GLOBAL:
- Setting a IPv6 Global statefull address to the device working in STA mode. - The IP address will be stored in the FileSystem. Requires restart. - \code - _u32 IfBitmap = 0; - IfBitmap = SL_NETCFG_IF_IPV6_STA_GLOBAL; - sl_NetCfgSet(SL_NETCFG_IF,SL_NETCFG_IF_STATE,sizeof(IfBitmap),&IfBitmap); - sl_NetCfgSet(SL_NETCFG_IPV6_ADDR_GLOBAL,SL_NETCFG_ADDR_STATEFUL,0,0); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode -
- - - SL_NETCFG_AP_STATION_DISCONNECT:
- Disconnect AP station by mac address. - The AP connected stations list can be read by sl_NetCfgGet with options: SL_AP_STATIONS_NUM_CONNECTED, SL_AP_STATIONS_INFO_LIST - \code - _u8 ap_sta_mac[6] = { 0x00, 0x22, 0x33, 0x44, 0x55, 0x66 }; - sl_NetCfgSet(SL_NETCFG_AP_STATION_DISCONNECT,1,SL_MAC_ADDR_LEN,(_u8 *)ap_sta_mac); - \endcode -
- - - SL_NETCFG_IPV4_DNS_CLIENT:
- Set additional IPv4 DNS address - \code - _i32 Status; - SlNetCfgIpV4DnsClientArgs_t DnsOpt; - DnsOpt.DnsSecondServerAddr = SL_IPV4_VAL(8,8,8,8); ; - Status = sl_NetCfgSet(SL_NETCFG_IPV4_DNS_CLIENT,0,sizeof(SlNetCfgIpV4DnsClientArgs_t),(unsigned char *)&DnsOpt); - if( Status ) - { - // error - } - \endcode -
- - - SL_NETCFG_IPV6_DNS_CLIENT:
- Set additional IPv6 DNS address - \code - _i32 Status; - SlNetCfgIpV6DnsClientArgs_t DnsOpt; - DnsOpt.DnsSecondServerAddr[0] = SL_IPV6_VAL(0x2001, 0x4860); - DnsOpt.DnsSecondServerAddr[1] = SL_IPV6_VAL(0x4860, 0x0); - DnsOpt.DnsSecondServerAddr[2] = SL_IPV6_VAL(0x0, 0x0); - DnsOpt.DnsSecondServerAddr[3] = SL_IPV6_VAL(0x0, 0x8844); - Status = sl_NetCfgSet(SL_NETCFG_IPV6_DNS_CLIENT,0,sizeof(SlNetCfgIpV6DnsClientArgs_t),(unsigned char *)&DnsOpt); - if( Status ) - { - // error - } - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_NetCfgSet) -_i16 sl_NetCfgSet(const _u16 ConfigId,const _u16 ConfigOpt,const _u16 ConfigLen,const _u8 *pValues); -#endif - - -/*! - \brief Getting network configurations - - \param[in] ConfigId Configuration id - - \param[out] pConfigOpt Get configurations option - - \param[out] pConfigLen The length of the allocated memory as input, when the - function complete, the value of this parameter would be - the len that actually read from the device.\n - If the device return length that is longer from the input - value, the function will cut the end of the returned structure - and will return ESMALLBUF - - \param[out] pValues - get configurations values - \return Zero on success, or -1 on failure - \sa sl_NetCfgSet - \note - \warning - \par Examples - - - SL_NETCFG_MAC_ADDRESS_GET:
- Get the device MAC address. - The returned MAC address is taken from FileSystem first. If the MAC address was not set by SL_MAC_ADDRESS_SET, the default MAC address - is retrieved from HW. - \code - _u8 macAddressVal[SL_MAC_ADDR_LEN]; - _u16 macAddressLen = SL_MAC_ADDR_LEN; - _u16 ConfigOpt = 0; - sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET,&ConfigOpt,&macAddressLen,(_u8 *)macAddressVal); - \endcode -
- - - SL_NETCFG_IPV4_STA_ADDR_MODE:
- Get IP address from WLAN station or P2P client. A DHCP flag is returned to indicate if the IP address is static or from DHCP. - \code - _u16 len = sizeof(SlNetCfgIpV4Args_t); - _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC - SlNetCfgIpV4Args_t ipV4 = {0}; - sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE,&ConfigOpt,&len,(_u8 *)&ipV4); - - printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", - (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", - SL_IPV4_BYTE(ipV4.Ip,3),SL_IPV4_BYTE(ipV4.Ip,2),SL_IPV4_BYTE(ipV4.Ip,1),SL_IPV4_BYTE(ipV4.Ip,0), - SL_IPV4_BYTE(ipV4.IpMask,3),SL_IPV4_BYTE(ipV4.IpMask,2),SL_IPV4_BYTE(ipV4.IpMask,1),SL_IPV4_BYTE(ipV4.IpMask,0), - SL_IPV4_BYTE(ipV4.IpGateway,3),SL_IPV4_BYTE(ipV4.IpGateway,2),SL_IPV4_BYTE(ipV4.IpGateway,1),SL_IPV4_BYTE(ipV4.IpGateway,0), - SL_IPV4_BYTE(ipV4.IpDnsServer,3),SL_IPV4_BYTE(ipV4.IpDnsServer,2),SL_IPV4_BYTE(ipV4.IpDnsServer,1),SL_IPV4_BYTE(ipV4.IpDnsServer,0)); - \endcode -
- - - SL_NETCFG_IPV4_AP_ADDR_MODE:
- Get static IP address for AP or P2P go. - \code - _u16 len = sizeof(SlNetCfgIpV4Args_t); - _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_DHCP / SL_NETCFG_ADDR_DHCP_LLA / SL_NETCFG_ADDR_STATIC - SlNetCfgIpV4Args_t ipV4 = {0}; - sl_NetCfgGet(SL_NETCFG_IPV4_AP_ADDR_MODE,&ConfigOpt,&len,(_u8 *)&ipV4); - - printf("DHCP is %s IP %d.%d.%d.%d MASK %d.%d.%d.%d GW %d.%d.%d.%d DNS %d.%d.%d.%d\n", - (ConfigOpt == SL_NETCFG_ADDR_DHCP) ? "ON" : "OFF", - SL_IPV4_BYTE(ipV4.Ip,3),SL_IPV4_BYTE(ipV4.Ip,2),SL_IPV4_BYTE(ipV4.Ip,1),SL_IPV4_BYTE(ipV4.Ip,0), - SL_IPV4_BYTE(ipV4.IpMask,3),SL_IPV4_BYTE(ipV4.IpMask,2),SL_IPV4_BYTE(ipV4.IpMask,1),SL_IPV4_BYTE(ipV4.IpMask,0), - SL_IPV4_BYTE(ipV4.IpGateway,3),SL_IPV4_BYTE(ipV4.IpGateway,2),SL_IPV4_BYTE(ipV4.IpGateway,1),SL_IPV4_BYTE(ipV4.IpGateway,0), - SL_IPV4_BYTE(ipV4.IpDnsServer,3),SL_IPV4_BYTE(ipV4.IpDnsServer,2),SL_IPV4_BYTE(ipV4.IpDnsServer,1),SL_IPV4_BYTE(ipV4.IpDnsServer,0)); - \endcode -
- - - SL_NETCFG_IF:
- Get interface bitmap - \code - _u16 len; - _u32 IfBitmap; - len = sizeof(IfBitmap); - sl_NetCfgGet(SL_NETCFG_IF,NULL,&len,(_u8 *)&IfBitmap); - \endcode -
- - - SL_NETCFG_IPV6_ADDR_LOCAL:
- Get IPV6 Local address (ipV6.ipV6IsValid holds the address status. 1=Valid, ipv6 DAD completed and address is valid for use) - \code - SlNetCfgIpV6Args_t ipV6; - _u16 len = sizeof(SlNetCfgIpV6Args_t); - _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_STATIC / SL_NETCFG_ADDR_STATELESS / SL_NETCFG_ADDR_STATEFUL - - sl_NetCfgGet(SL_NETCFG_IPV6_ADDR_LOCAL,&ConfigOpt,&len,(_u8 *)&ipV6); - if (SL_IS_IPV6_ADDR_VALID(ipV6.IpV6Flags)) - { - printf("Ipv6 Local Address is valid: %8x:%8x:%8x:%8x\n", ipV6.Ip[0],ipV6.Ip[0],ipV6.Ip[0],ipV6.Ip[0]); - } - else - { - printf("Ipv6 Local Address is not valid, wait for DAD to complete or configure a different address"); - } - - \endcode -
- - - SL_NETCFG_IPV6_ADDR_GLOBAL:
- Get IPV6 Global address (ipV6.ipV6IsValid holds the address status. 1=Valid, ipv6 DAD completed and address is valid for use) - \code - SlNetCfgIpV6Args_t ipV6; - _u16 len = sizeof(SlNetCfgIpV6Args_t); - _u16 ConfigOpt = 0; //return value could be one of the following: SL_NETCFG_ADDR_STATIC / SL_NETCFG_ADDR_STATEFUL - - if (SL_IS_IPV6_ADDR_VALID(ipV6.IpV6Flags)) - { - printf("Ipv6 Global Address is valid: %8x:%8x:%8x:%8x\n", ipV6.Ip[0],ipV6.Ip[0],ipV6.Ip[0],ipV6.Ip[0]); - } - else - { - printf("Ipv6 Global Address is not valid, wait for DAD to complete or configure a different address"); - } - - \endcode -
- - - SL_NETCFG_AP_STATIONS_NUM_CONNECTED:
- Get AP number of connected stations. - \code - _u8 num_ap_connected_sta; - _u16 len = sizeof(num_ap_connected_sta); - sl_NetCfgGet(SL_NETCFG_AP_STATIONS_NUM_CONNECTED, NULL, &len, &num_ap_connected_sta); - printf("AP number of connected stations = %d\n", num_ap_connected_sta); - - \endcode -
- - - SL_NETCFG_AP_STATIONS_INFO_LIST:
- Get AP full list of connected stationss. - \code - SlNetCfgStaInfo_t ApStaList[4]; - _u16 sta_info_len; - _u16 start_sta_index = 0; - int actual_num_sta; - int i; - - start_sta_index = 0; - sta_info_len = sizeof(ApStaList); - sl_NetCfgGet(SL_NETCFG_AP_STATIONS_INFO_LIST, &start_sta_index, &sta_info_len, (_u8 *)ApStaList); - - actual_num_sta = sta_info_len / sizeof(SlNetCfgStaInfo_t); - printf("-Print SL_NETCFG_AP_STATIONS_INFO_LIST actual num_stations = %d (upon sta_info_len = %d)\n", actual_num_sta, sta_info_len); - - for (i=0; iName); - printf(" MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", staInfo->MacAddr[0], staInfo->MacAddr[1], staInfo->MacAddr[2], staInfo->MacAddr[3], staInfo->MacAddr[4], staInfo->MacAddr[5]); - printf(" IP: %d.%d.%d.%d\n", SL_IPV4_BYTE(staInfo->Ip,3), SL_IPV4_BYTE(staInfo->Ip,2), SL_IPV4_BYTE(staInfo->Ip,1), SL_IPV4_BYTE(staInfo->Ip,0)); - } - - \endcode -
- - - SL_NETCFG_IPV4_DNS_CLIENT:
- Get secondary DNS address (DHCP and static configuration) - \code - _u16 ConfigOpt = 0; - _i32 Status; - _u16 pConfigLen = sizeof(SlNetCfgIpV4DnsClientArgs_t); - SlNetCfgIpV4DnsClientArgs_t DnsOpt; - Status = sl_NetCfgGet(SL_NETCFG_IPV4_DNS_CLIENT,&ConfigOpt,&pConfigLen,&DnsOpt); - if( Status ) - { - // error - } - \endcode -
- - - SL_NETCFG_IPV6_DNS_CLIENT:
- Get secondary DNS address (DHCP and static configuration) - \code - _u16 ConfigOpt = 0; - _i32 Status; - _u16 pConfigLen = sizeof(SlNetCfgIpV6DnsClientArgs_t); - SlNetCfgIpV6DnsClientArgs_t DnsOpt; - Status = sl_NetCfgGet(SL_NETCFG_IPV6_DNS_CLIENT,&ConfigOpt,&pConfigLen,&DnsOpt); - if( Status ) - { - // error - } - \endcode - - - SL_NETCFG_IPV4_DHCP_CLIENT:
- Get DHCP Client info - \code - _u16 ConfigOpt = 0; - _u16 pConfigLen = sizeof(SlNetCfgIpv4DhcpClient_t); - SlNetCfgIpv4DhcpClient_t dhcpCl; - SlNetCfgIpV4Args_t ipV4 = {0}; - - ret = sl_NetCfgGet(SL_NETCFG_IPV4_DHCP_CLIENT, &ConfigOpt, &pConfigLen, (_u8 *)&dhcpCl); - if(ret < 0) - { - printf("Error = %d\n", ret); - } - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_NetCfgGet) -_i16 sl_NetCfgGet(const _u16 ConfigId ,_u16 *pConfigOpt, _u16 *pConfigLen, _u8 *pValues); -#endif - -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __NETCFG_H__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/netutil.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/netutil.h deleted file mode 100644 index 8eb8ac65184..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/netutil.h +++ /dev/null @@ -1,546 +0,0 @@ -/* - * netutil.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -#ifndef __NETUTIL_H__ -#define __NETUTIL_H__ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup NetUtil - \short Networking related commands and configuration - -*/ - -/*! - - \addtogroup NetUtil - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/* Set/get options */ -#define SL_NETUTIL_CRYPTO_PUBLIC_KEY (1) -#define SL_NETUTIL_CRYPTO_PUBLIC_KEY_INFO (2) -#define SL_NETUTIL_TRUE_RANDOM (3) - -/* Commands */ -#define SL_NETUTIL_CRYPTO_CMD_CREATE_CERT (1) -#define SL_NETUTIL_CRYPTO_CMD_SIGN_MSG (2) -#define SL_NETUTIL_CRYPTO_CMD_VERIFY_MSG (3) -#define SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS (4) -#define SL_NETUTIL_CRYPTO_CMD_INSTALL_OP (5) -#define SL_NETUTIL_CMD_ARP_LOOKUP (6) - -/*****************************************************************************/ -/* Errors returned from the general error async event */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -typedef struct -{ - _u8 *pOutputValues; - _u16 *pOutputLen; - _i16 Status; -}_SlNetUtilCmdData_t; - -/* Defines the size of the buffer that will be allocated */ -/* (on the stack) by the sl_UtilsCmd API. */ -#define SL_NETUTIL_CMD_BUFFER_SIZE (256) - -/* Enumeration of Signature types */ -#define SL_NETUTIL_CRYPTO_SIG_SHAwDSA (0) -#define SL_NETUTIL_CRYPTO_SIG_MD2wRSA (1) -#define SL_NETUTIL_CRYPTO_SIG_MD5wRSA (2) -#define SL_NETUTIL_CRYPTO_SIG_SHAwRSA (3) -#define SL_NETUTIL_CRYPTO_SIG_SHAwECDSA (4) -#define SL_NETUTIL_CRYPTO_SIG_SHA256wRSA (5) -#define SL_NETUTIL_CRYPTO_SIG_SHA256wECDSA (6) -#define SL_NETUTIL_CRYPTO_SIG_SHA384wRSA (7) -#define SL_NETUTIL_CRYPTO_SIG_SHA384wECDSA (8) -#define SL_NETUTIL_CRYPTO_SIG_SHA512wRSA (9) -#define SL_NETUTIL_CRYPTO_SIG_SHA512wECDSA (10) -#define SL_NETUTIL_CRYPTO_SIG_DIGESTwECDSA (11) -/* Add more signature-Types here */ - -/* Digest length definitions */ -#define SL_NETUTIL_CRYPTO_DGST_MD2_LEN_BYTES (16) -#define SL_NETUTIL_CRYPTO_DGST_MD5_LEN_BYTES (16) -#define SL_NETUTIL_CRYPTO_DGST_SHA_LEN_BYTES (20) -#define SL_NETUTIL_CRYPTO_DGST_SHA256_LEN_BYTES (32) -#define SL_NETUTIL_CRYPTO_DGST_SHA384_LEN_BYTES (48) -#define SL_NETUTIL_CRYPTO_DGST_SHA512_LEN_BYTES (64) - - -/* Enumeration of Create-Certificate sub-commands */ -#define SL_NETUTIL_CRYPTO_CERT_INIT (1) -#define SL_NETUTIL_CRYPTO_CERT_SIGN_AND_SAVE (2) -#define SL_NETUTIL_CRYPTO_CERT_VER (3) -#define SL_NETUTIL_CRYPTO_CERT_SERIAL (4) -#define SL_NETUTIL_CRYPTO_CERT_SIG_TYPE (5) -#define SL_NETUTIL_CRYPTO_CSR_SIGN_AND_SAVE (6) -#if 0 /* reserved for Issuer information - currently not supported */ -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_COUNTRY (6) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_STATE (7) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_LOCALITY (8) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_SUR (9) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_ORG (10) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_ORG_UNIT (11) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_COMMON_NAME (12) -#define SL_NETUTIL_CRYPTO_CERT_ISSUER_EMAIL (13) -#endif /* End - issuer information */ -#define SL_NETUTIL_CRYPTO_CERT_DAYS_VALID (14) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_COUNTRY (15) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_STATE (16) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_LOCALITY (17) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_SUR (18) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_ORG (19) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_ORG_UNIT (20) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_COMMON_NAME (21) -#define SL_NETUTIL_CRYPTO_CERT_SUBJECT_EMAIL (22) -#define SL_NETUTIL_CRYPTO_CERT_IS_CA (23) - - -/* Enumeration of "Temp-Keys" commands */ -#define SL_NETUTIL_CRYPTO_TEMP_KEYS_CREATE (1) -#define SL_NETUTIL_CRYPTO_TEMP_KEYS_REMOVE (2) - -/* Enumeration of "Install/Uninstall" sub-commands */ -#define SL_NETUTIL_CRYPTO_INSTALL_SUB_CMD (1) -#define SL_NETUTIL_CRYPTO_UNINSTALL_SUB_CMD (2) - - -/* The reserved key for IOT Usage */ -#define SL_NETUTIL_CRYPTO_SERVICES_IOT_RESERVED_INDEX (0) - -/* The Temporary key for FS Usage */ -#define SL_NETUTIL_CRYPTO_FS_TEMP_KEYS_OBJ_ID (1) - - -/**********************************************/ -/* Public Key Info Structures and Definitions */ -/**********************************************/ - -/* Enumeration of Elliptic Curve "named" curves */ -#define SL_NETUTIL_CRYPTO_EC_NAMED_CURVE_NONE (0) -#define SL_NETUTIL_CRYPTO_EC_NAMED_CURVE_SECP256R1 (1) - -/* PLACE HOLDER for future definitions of custom-curve parameters */ -typedef struct -{ - _u8 Padding[4]; -} SlNetUtilCryptoEcCustomCurveParam_t; - - -/* Union holding the Elliptic Curve parameters. */ -typedef union -{ - _u8 NamedCurveParams; /* parameters for named-curve (the curve identifier) */ - SlNetUtilCryptoEcCustomCurveParam_t CustomCurveParams; /* parameters for custom curves */ -} SlNetUtilCryptoEcCurveParams_u; - - -/* ?curve-type? definitions */ -#define SL_NETUTIL_CRYPTO_EC_CURVE_TYPE_NAMED (1) /* ECC Named Curve type */ -#define SL_NETUTIL_CRYPTO_EC_CURVE_TYPE_CUSTOM (2) /* ECC Custom curve type */ - - -/* Enumeration of the supported public-key algorithms */ -#define SL_NETUTIL_CRYPTO_PUB_KEY_ALGO_NONE (0) -#define SL_NETUTIL_CRYPTO_PUB_KEY_ALGO_EC (1) - - -/* Structure for holding the Elliptic Curve Key parameters */ -typedef struct -{ - _u8 CurveType; /* defines curve type - custom or named */ - SlNetUtilCryptoEcCurveParams_u CurveParams; /* specific parameters of the curve (depends on curve_type) */ -} SlNetUtilCryptoEcKeyParams_t; - -/* Union for holding the Public Key parameters, depends on key algorithm */ -typedef union -{ - - SlNetUtilCryptoEcKeyParams_t EcParams; /* parameters for Elliptic Curve key */ - - /* add containers for other key types and algos here*/ -} SlNetUtilCryptoPubKeyParams_u; - -/* structure for holding all the meta-data about a key-pair */ -typedef struct -{ - _u8 KeyAlgo; - SlNetUtilCryptoPubKeyParams_u KeyParams; - _u8 KeyFileNameLen; - _u8 CertFileNameLen; -}SlNetUtilCryptoPubKeyInfo_t; - -/********************************************/ -/* NetUtil-Crypto Cmd "Attributes" structures */ -/********************************************/ -/* structure for holding all the attributes for a "Sign" Command */ -typedef struct -{ - _u32 ObjId; - _u32 SigType; - _u32 Flags; -} SlNetUtilCryptoCmdSignAttrib_t; - - -/* structure for holding all the attributes for a "Verify" Command */ -typedef struct -{ - _u32 ObjId; - _u32 SigType; - _u32 Flags; - _u16 MsgLen; - _u16 SigLen; -} SlNetUtilCryptoCmdVerifyAttrib_t; - -/* structure for holding all the attributes for a "Create Certificate" Command */ -typedef struct -{ - _u32 ObjId; - _u32 Flags; - _u16 SubCmd; -} SlNetUtilCryptoCmdCreateCertAttrib_t; - -/* structure for holding all the attributes for "Key management" Commands: */ -/* Temp-Key (create and delete), Install and un-Install. */ -typedef struct -{ - _u32 ObjId; - _u32 Flags; - _u16 SubCmd; -} SlNetUtilCryptoCmdKeyMgnt_t; - -/* structure for holding all the attributes for a "SL_NETUTIL_CMD_ARP_LOOKUP" Command */ -typedef struct -{ - _u16 NumOfRetries; /* number of retires for ARP request, range 1-20 */ - _u16 Timeout; /* timeout between ARP requests, range 10-500 mSec , 10 mSec resolution*/ -}NetUtilCmdArpLookupAttrib_t; - - -/******************************************************************************/ -/* Type declarations */ -/******************************************************************************/ - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - \brief Function for setting configurations of utilities - - \param[in] Option Identifier of the specific "set" operation to perform - \param[in] ObjID ID of the relevant object that this set operation will be performed on - \param[in] ValueLen Length of the value parameter - \param[in] pValues Pointer to the buffer holding the configurations values - - \return Zero on success, or negative error code on failure - \sa sl_NetUtilGet sl_NetUtilCmd - \note - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_NetUtilSet) -_i32 sl_NetUtilSet(const _u16 Option, const _u32 ObjID, const _u8 *pValues, const _u16 ValueLen); -#endif - -/*! - \brief Function for getting configurations of utilities - \param[in] Option Identifier of the specific "get" operation to perform - - SL_NETUTIL_CRYPTO_PUBLIC_KEY \n - Used to retrieve the public key from an installed key-pair. \n - Saved in a certain index. - - SL_NETUTIL_TRUE_RANDOM \n - Generates a random number using the internal TRNG of the NWP. \n - \param[in] ObjID ID of the relevant object that this set operation will be performed on - \param[in,out] pValueLen Pointer to the length of the value parameter\n - On input - provides the length of the buffer that the application allocates, and - will hold the output\n - On output - provides the actual length of the received data - \param[out] pValues Pointer to the buffer that the application allocates, and will hold - the received data. - \return Zero on success, or negative error code on failure. - \sa sl_NetUtilSet sl_NetUtilCmd - \note - \warning - \par Examples - - SL_NETUTIL_CRYPTO_PUBLIC_KEY: - \code - int16_t Status; - uint8_t configOpt = 0; - uint32_t objId = 0; - uint16_t configLen = 0; - uint8_t key_buf[256]; - - configOpt = SL_NETUTIL_CRYPTO_PUBLIC_KEY; - - objId = 1; - configLen = 255; - //get the Public key - Status = sl_NetUtilGet(configOpt, objId, key_buf, &configLen); - \endcode - - - SL_NETUTIL_TRUE_RANDOM: - \code - uint32_t randNum; - int32_t len = sizeof(uint32_t); - - sl_NetUtilGet(SL_NETUTIL_TRUE_RANDOM, 0, (uint8_t *)&randNum, &len); - \endcode -
-*/ -#if _SL_INCLUDE_FUNC(sl_NetUtilGet) -_i16 sl_NetUtilGet(const _u16 Option, const _u32 ObjID, _u8 *pValues, _u16 *pValueLen); -#endif - -/*! - \brief Function for performing utilities-related commands - \param[in] Cmd Identifier of the specific Command to perform - - SL_NETUTIL_CRYPTO_CMD_INSTALL_OP \n - Install / Uninstall key pairs in one or more of the crypto utils - key-pair management mechanism. \n - Key Must be an ECC key-pair using SECP256R1 curve and already programmed to file system, - in DER format.\n - Key installation is persistent. - - SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS \n - Creates or removes a temporary key pair. \n - Key pair is created internally by the NWP. - Key pair is not persistent over power cycle. - - SL_NETUTIL_CRYPTO_CMD_SIGN_MSG \n - Signs with a digital signature a data buffer using ECDSA algorithm. \n - - SL_NETUTIL_CRYPTO_CMD_VERIFY_MSG \n - Verify a digital signature given with a data buffer using ECDSA algorithm. \n - - SL_NETUTIL_CMD_ARP_LOOKUP \n - Mapping MAC address to IPv4 or IPv6 address. \n - \param[in] pAttrib Pointer to the buffer holding the Attribute values - \param[in] AttribLen Length of the Attribute-values - \param[in] pInputValues Pointer to the buffer holding the input-value - \param[in] InputLen Length of the input-value - \param[out] pOutputValues Pointer to the buffer that the application allocates, and will hold the received data. - \param[in,out] pOutputLen Length of the output-value \n - On input - provides the length of the buffer that the application allocates, and - will hold the output\n - On output - provides the actual length of the received output-values - \return Zero on success, or negative error code on failure - \sa sl_NetUtilGet sl_NetUtilSet - \note The host driver API sl_NetUtilCmd is not valid for use with the CC3220R device. - \warning - \par Examples - - - SL_NETUTIL_CRYPTO_CMD_INSTALL_OP (install / uninstall crypto keys): - \code - // Install a key - SlNetUtilCryptoCmdKeyMgnt_t keyAttrib; - SlNetUtilCryptoPubKeyInfo_t *pInfoKey; - uint8_t name[FILE_NAME_SIZE]; - int32_t Status; - int16_t resultLen; - - keyAttrib.ObjId = 5; // Key would be stored at index 5 - keyAttrib.SubCmd = SL_NETUTIL_CRYPTO_INSTALL_SUB_CMD; - pInfoKey->KeyAlgo = SL_NETUTIL_CRYPTO_PUB_KEY_ALGO_EC; - pInfoKey->KeyParams.EcParams.CurveType = SL_NETUTIL_CRYPTO_EC_CURVE_TYPE_NAMED; //ECC curve - pInfoKey->KeyParams.EcParams.CurveParams.NamedCurveParams = SL_NETUTIL_CRYPTO_EC_NAMED_CURVE_SECP256R1; // SECP256R1 curve only. - - pInfoKey->CertFileNameLen = 0; - name = ((uint8_t *)pInfoKey) + sizeof(SlNetUtilCryptoPubKeyInfo_t); - name += pInfoKey->CertFileNameLen; - strcpy((char *)name, "extkey.der"); // Private key name in file system. - pInfoKey->KeyFileNameLen = strlen("extkey.der")+1; - - Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_INSTALL_OP, - (uint8_t *)&keyAttrib, sizeof(SlNetUtilCryptoCmdKeyMgnt_t), - (uint8_t *)pInfo, - sizeof(SlNetUtilCryptoPubKeyInfo_t) + pInfoKey->KeyFileNameLen, - NULL, &resultLen); - - // Uninstall the Key: - resultLen = 0; - keyAttrib.ObjId = 5; - keyAttrib.SubCmd = SL_NETUTIL_CRYPTO_UNINSTALL_SUB_CMD; - - Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_INSTALL_OP, (uint8_t *)&keyAttrib, - sizeof(SlNetUtilCryptoCmdKeyMgnt_t), NULL, 0 , NULL, &resultLen); - \endcode - - - SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS, (Create a temporary key ): - \code - - SlNetUtilCryptoCmdKeyMgnt_t keyAttrib; - int32_t Status; - uint16_t resultLen; - keyAttrib.ObjId = 1; // key index is 1 - keyAttrib.SubCmd = SL_NETUTIL_CRYPTO_TEMP_KEYS_CREATE; - - Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS, - (uint8_t *)&keyAttrib, sizeof(SlNetUtilCryptoCmdKeyMgnt_t), - NULL, 0 , NULL, &resultLen); - \endcode - - - SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS, (Create a temporary key ): - \code - - SlNetUtilCryptoCmdKeyMgnt_t keyAttrib; - int32_t Status; - uint16_t resultLen; - keyAttrib.ObjId = 1; // key index is 1 - keyAttrib.SubCmd = SL_NETUTIL_CRYPTO_TEMP_KEYS_CREATE; - - Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_TEMP_KEYS, - (uint8_t *)&keyAttrib, sizeof(SlNetUtilCryptoCmdKeyMgnt_t), - NULL, 0 , NULL, &resultLen); - \endcode - - - SL_NETUTIL_CRYPTO_CMD_SIGN_MSG, (Sign a data buffer): - \code - int32_t Status; - int32_t configLen; - uint8_t messageBuff[1500]; - uint8_t sig_buf[256]; // This buffer shall contain the digital signature. - SlNetUtilCryptoCmdSignAttrib_t signAttrib; - - signAttrib.Flags = 0; - signAttrib.ObjId = 3; - signAttrib.SigType = SL_NETUTIL_CRYPTO_SIG_SHAwECDSA; // this is the only type supported - configLen = 255; - - Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_SIGN_MSG, (uint8_t *)&signAttrib, - sizeof(SlNetUtilCryptoCmdSignAttrib_t), - messageBuff, sizeof(messageBuf), sig_buf, &configLen); - \endcode - - - SL_NETUTIL_CRYPTO_CMD_VERIFY_MSG, (Verify a data buffer): - \code - - int32_t Status; - int32_t configLen; - uint8_t verifyBuf[2048]; - uint8_t messageBuff[1500]; - uint8_t sig_buf[256]; // This buffer contains the digital signature. - int32_t verifyResult; - SlNetUtilCryptoCmdVerifyAttrib_t verAttrib; - - memcpy(verifyBuf, messageBuf, sizeof(messageBuf)); // copy the message to verify buffer. - memcpy(verifyBuf + sizeof(messageBuff), sig_buf, configLen); // Append the signature to message buffer. - - verAttrib.Flags = 0; - verAttrib.ObjId = 3; - verAttrib.SigType = SL_NETUTIL_CRYPTO_SIG_SHAwECDSA; // this is the only type supported, if other hash algorithm - // is wanted, SL_NETUTIL_CRYPTO_SIG_DIGESTwECDSA is used and - // the verifyBuf should be the digest and MsgLen should be - // the digest size - verAttrib.MsgLen = sizeof(messageBuff); - verAttrib.SigLen = configLen; - configLen = 255; - resultLen = 4; - - Status = sl_NetUtilCmd(SL_NETUTIL_CRYPTO_CMD_VERIFY_MSG, (uint8_t *)&verAttrib, - sizeof(SlNetUtilCryptoCmdVerifyAttrib_t), - verifyBuf, sizeof(messageBuf) + configLen, - (uint8_t *)&verifyResult , &resultLen); - \endcode -
- - \endcode - - - SL_NETUTIL_CMD_ARP_LOOKUP, (Mapping MAC address to IPv4 or IPv6 address): - \code - - NetUtilCmdArpLookupAttrib_t arpAttr; - _u32 ipv4; - _u8 macAddr[6]; - _u16 outLen = sizeof(macAddr); - _i16 status; - - ipv4 = SL_IPV4_VAL(192,168,178,43); - arpAttr.NumOfRetries = 3; - arpAttr.Timeout = 50; - - status = sl_NetUtilCmd(SL_NETUTIL_CMD_ARP_LOOKUP, (uint8_t *)&arpAttr, sizeof(arpAttr), (_u8*)&ipv4 , sizeof(ipv4), macAddr,&outLen); - if(status != 0) - { - // MAC was not found - } - else - { - // IP address mapped to MAC - } - - \endcode -
- - - -*/ -#if _SL_INCLUDE_FUNC(sl_NetUtilCmd) -_i16 sl_NetUtilCmd(const _u16 Cmd, const _u8 *pAttrib, const _u16 AttribLen, - const _u8 *pInputValues, const _u16 InputLen, - _u8 *pOutputValues,_u16 *pOutputLen ); -#endif - -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __NETUTIL_H__ */ - - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/CC3220SF_LAUNCHXL.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/CC3220SF_LAUNCHXL.c deleted file mode 100644 index 7a5a469f961..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/CC3220SF_LAUNCHXL.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (c) 2017-2019, Texas Instruments Incorporated - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -/* =========================== SPI Driver Fxns ========================= */ -#include -#include -#include - -#include -#include -#include -#include -#include - -typedef enum CC3220SF_LAUNCHXL_SPIName { - CC3220SF_LAUNCHXL_SPI0 = 0, - CC3220SF_LAUNCHXL_SPI1 = 1, - CC3220SF_LAUNCHXL_SPICOUNT -} CC3220SF_LAUNCHXL_SPIName; - -#include -#include - -SPICC32XXDMA_Object spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPICOUNT]; - -uint32_t spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPICOUNT]; - -const SPICC32XXDMA_HWAttrsV1 spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPICOUNT] = { - /* index 0 is reserved for LSPI that links to the NWP */ - { - .baseAddr = LSPI_BASE, - .intNum = INT_LSPI, - .intPriority = (~0), - .spiPRCM = PRCM_LSPI, - .csControl = SPI_SW_CTRL_CS, - .csPolarity = SPI_CS_ACTIVEHIGH, - .pinMode = SPI_4PIN_MODE, - .turboMode = SPI_TURBO_OFF, - .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI0], - .defaultTxBufValue = 0, - .rxChannelIndex = UDMA_CH12_LSPI_RX, - .txChannelIndex = UDMA_CH13_LSPI_TX, - .minDmaTransferSize = 100, - .mosiPin = SPICC32XXDMA_PIN_NO_CONFIG, - .misoPin = SPICC32XXDMA_PIN_NO_CONFIG, - .clkPin = SPICC32XXDMA_PIN_NO_CONFIG, - .csPin = SPICC32XXDMA_PIN_NO_CONFIG - }, - { - .baseAddr = GSPI_BASE, - .intNum = INT_GSPI, - .intPriority = (~0), - .spiPRCM = PRCM_GSPI, - .csControl = SPI_HW_CTRL_CS, - .csPolarity = SPI_CS_ACTIVELOW, - .pinMode = SPI_4PIN_MODE, - .turboMode = SPI_TURBO_OFF, - .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI1], - .defaultTxBufValue = 0, - .rxChannelIndex = UDMA_CH6_GSPI_RX, - .txChannelIndex = UDMA_CH7_GSPI_TX, - .minDmaTransferSize = 10, - .mosiPin = SPICC32XXDMA_PIN_07_MOSI, - .misoPin = SPICC32XXDMA_PIN_06_MISO, - .clkPin = SPICC32XXDMA_PIN_05_CLK, - .csPin = SPICC32XXDMA_PIN_08_CS - } -}; - -const SPI_Config SPI_config[CC3220SF_LAUNCHXL_SPICOUNT] = { - { - .fxnTablePtr = &SPICC32XXDMA_fxnTable, - .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI0], - .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI0] - }, - { - .fxnTablePtr = &SPICC32XXDMA_fxnTable, - .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI1], - .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI1] - } -}; - -const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT; - -/* - * =============================== DMA =============================== - */ -#include - -static tDMAControlTable dmaControlTable[64] __attribute__ ((aligned (1024))); - -/* - * ======== dmaErrorFxn ======== - * This is the handler for the uDMA error interrupt. - */ -static void dmaErrorFxn(uintptr_t arg) -{ - int status = MAP_uDMAErrorStatusGet(); - MAP_uDMAErrorStatusClear(); - - /* Suppress unused variable warning */ - (void)status; - - while (1); -} - -UDMACC32XX_Object udmaCC3220SObject; - -const UDMACC32XX_HWAttrs udmaCC3220SHWAttrs = { - .controlBaseAddr = (void *)dmaControlTable, - .dmaErrorFxn = (UDMACC32XX_ErrorFxn)dmaErrorFxn, - .intNum = INT_UDMAERR, - .intPriority = (~0) -}; - -const UDMACC32XX_Config UDMACC32XX_config = { - .object = &udmaCC3220SObject, - .hwAttrs = &udmaCC3220SHWAttrs -}; - -/* - * ======== CC3220SF_LAUNCHXL_init ======== - * Zephyr-port-specific general initialization - */ -void CC3220SF_LAUNCHXL_init() -{ - MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_HOST_IRQ); - SPI_init(); -} - -/* - * ======== Board_debugHeader ======== - * This structure prevents the CC32XXSF bootloader from overwriting the - * internal FLASH; this allows us to flash a program that will not be - * overwritten by the bootloader with the encrypted program saved in - * "secure/serial flash". - * - * This structure must be placed at the beginning of internal FLASH (so - * the bootloader is able to recognize that it should not overwrite - * internal FLASH). - */ -#if defined (__SF_DEBUG__) || defined(__SF_NODEBUG__) -#if defined(__TI_COMPILER_VERSION__) -#pragma DATA_SECTION(Board_debugHeader, ".dbghdr") -#pragma RETAIN(Board_debugHeader) -#elif defined(__IAR_SYSTEMS_ICC__) -#pragma location=".dbghdr" -#elif defined(__GNUC__) -__attribute__ ((section (".dbghdr"))) -#endif -#if defined(__SF_DEBUG__) -const uint32_t Board_debugHeader[] = { - 0x5AA5A55A, - 0x000FF800, - 0xEFA3247D -}; -#elif defined (__SF_NODEBUG__) -const uint32_t Board_debugHeader[] = { - 0xFFFFFFFF, - 0xFFFFFFFF, - 0xFFFFFFFF -}; -#endif -#endif diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/CC3220SF_LAUNCHXL.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/CC3220SF_LAUNCHXL.h deleted file mode 100644 index c39e3081ab4..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/CC3220SF_LAUNCHXL.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -#ifndef _CC3220SF_LAUNCHXL_H_ -#define _CC3220SF_LAUNCHXL_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -extern void CC3220SF_LAUNCHXL_init(); - -#ifdef __cplusplus -} -#endif - -#endif /* _CC3220SF_LAUNCHXL_H_ */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/cc_pal.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/cc_pal.c deleted file mode 100644 index fc72df353d7..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/cc_pal.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * cc_pal.c - CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ -/****************************************************************************** -* cc_pal.c -* -* SimpleLink Wi-Fi abstraction file for CC32xx -******************************************************************************/ - -/* Board includes */ -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ti/devices/cc32xx/driverlib/rom.h" -#include "ti/devices/cc32xx/driverlib/rom_map.h" -#include -#include -#include -#include - -/* NWP_SPARE_REG_5 - (OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5) - - Bits 31:02 - Reserved - - Bits 01 - SLSTOP1 - NWP in Reset, Power Domain Down - - Bits 00 - Reserved -*/ -#define NWP_SPARE_REG_5 (OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_5) -#define NWP_SPARE_REG_5_SLSTOP (0x00000002) - -/* ANA_DCDC_PARAMS0 - (HIB1P2_BASE + HIB1P2_O_ANA_DCDC_PARAMETERS0) - - Bits 31:28 - Reserved - - Bits 27 - Override PWM mode (==> PFM) - - Bits 26:00 - Reserved -*/ -#define ANA_DCDC_PARAMS0 (HIB1P2_BASE + HIB1P2_O_ANA_DCDC_PARAMETERS0) -#define ANA_DCDC_PARAMS0_PWMOVERRIDE (0x08000000) - -/* WAKENWP - (ARCM_BASE + APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST) - - Bits 31:01 - Reserved - - Bits 00 - Wake Request to NWP -*/ -#define WAKENWP (ARCM_BASE + APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST) -#define WAKENWP_WAKEREQ (APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST) - -/* NWP_PWR_STATE - (GPRCM_BASE + GPRCM_O_NWP_PWR_STATE) - - Bits 31:12 - Reserved - - Bits 11:08 - Active (0x3) - - Bits 07:00 - Reserved -*/ -#define NWP_PWR_STATE (GPRCM_BASE + GPRCM_O_NWP_PWR_STATE) -#define NWP_PWR_STATE_PWRMASK (0x00000F00) -#define NWP_PWR_STATE_PWRACTIVE (0x00000300) - -/* NWP_LPDS_WAKEUPCFG - (GPRCM_BASE + GPRCM_O_NWP_LPDS_WAKEUP_CFG) - - Bits 31:08 - Reserved - - Bits 07:00 - WakeUp Config AppsToNwp Wake (0x20) - reset condition -*/ -#define NWP_LPDS_WAKEUPCFG (GPRCM_BASE + GPRCM_O_NWP_LPDS_WAKEUP_CFG) -#define NWP_LPDS_WAKEUPCFG_APPS2NWP (0x00000020) -#define NWP_LPDS_WAKEUPCFG_TIMEOUT_MSEC (600) - -/* N2A_INT_MASK_SET - (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_SET) */ -#define N2A_INT_MASK_SET (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_SET) -/* N2A_INT_MASK_CLR - (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_CLR) */ -#define N2A_INT_MASK_CLR (COMMON_REG_BASE + COMMON_REG_O_NW_INT_MASK_CLR) -/* N2A_INT_ACK - (COMMON_REG_BASE + COMMON_REG_O_NW_INT_ACK) */ -#define N2A_INT_ACK (COMMON_REG_BASE + COMMON_REG_O_NW_INT_ACK) -#define NWP_N2A_INT_ACK_TIMEOUT_MSEC (3000) - -/* A2N_INT_STS_CLR - (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_CLR) */ -#define A2N_INT_STS_CLR (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_CLR) -/* A2N_INT_TRIG - (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_TRIG) */ -#define A2N_INT_TRIG (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_TRIG) -/* A2N_INT_STS_RAW - (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_RAW) */ -#define A2N_INT_STS_RAW (COMMON_REG_BASE + COMMON_REG_O_APPS_INT_STS_RAW) - -#define uSEC_DELAY(x) (ROM_UtilsDelayDirect(x*80/3)) -#define MAX_DMA_RECV_TRANSACTION_SIZE (4096) -#define SPI_RATE_20M (20000000) -#define SPI_RATE_30M (30000000) - -HwiP_Handle g_intHandle = 0; - -//**************************************************************************** -// LOCAL FUNCTIONS -//**************************************************************************** - -Fd_t spi_Open(char *ifName, unsigned long flags) -{ - void *lspi_hndl; - unsigned int lspi_index; - SPI_Params SPI_Config; - SPI_Params_init(&SPI_Config); - - /* configure the SPI settings */ - SPI_Config.transferMode = SPI_MODE_BLOCKING; - SPI_Config.mode = SPI_MASTER; - - /* Check NWP generation */ - if((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_DIEID_READ_REG4) >> 24) & 0x02) - { - SPI_Config.bitRate = SPI_RATE_30M; - } - else - { - SPI_Config.bitRate = SPI_RATE_20M; - } - SPI_Config.dataSize = 32; - SPI_Config.frameFormat = SPI_POL0_PHA0; - - /* index of the link SPI initialization configuration in the SPI_Config table */ - lspi_index = 0; - lspi_hndl = SPI_open(lspi_index, &SPI_Config); - if(NULL == lspi_hndl) - { - return -1; - } - else - { - return (Fd_t)lspi_hndl; - } -} - - -int spi_Close(Fd_t fd) -{ - SPI_close((void *)fd); - return 0; -} - - -int spi_Read(Fd_t fd, unsigned char *pBuff, int len) -{ - SPI_Transaction transact_details; - int read_size = 0; - - /* check if the link SPI has been initialized successfully */ - if(fd < 0) - { - return -1; - } - - transact_details.txBuf = NULL; - transact_details.arg = NULL; - while(len > 0) - { - /* DMA can transfer upto a maximum of 1024 words in one go. So, if - the data to be read is more than 1024 words, it will be done in - parts */ - /* length is received in bytes, should be specified in words for the - * SPI driver. - */ - if(len > MAX_DMA_RECV_TRANSACTION_SIZE) - { - transact_details.count = (MAX_DMA_RECV_TRANSACTION_SIZE +3)>>2; - transact_details.rxBuf = (void*)(pBuff + read_size); - if(SPI_transfer((SPI_Handle)fd, &transact_details)) - { - read_size += MAX_DMA_RECV_TRANSACTION_SIZE; - len = len - MAX_DMA_RECV_TRANSACTION_SIZE; - } - else - { - return -1; - } - - } - else - { - transact_details.count = (len+3)>>2; - transact_details.rxBuf = (void*)(pBuff + read_size); - if(SPI_transfer((SPI_Handle)fd, &transact_details)) - { - read_size += len; - len = 0; - return read_size; - } - else - { - return -1; - } - } - } - - return(read_size); -} - - -int spi_Write(Fd_t fd, unsigned char *pBuff, int len) -{ - SPI_Transaction transact_details; - int write_size = 0; - - /* check if the link SPI has been initialized successfully */ - if(fd < 0) - { - return -1; - } - - transact_details.rxBuf = NULL; - transact_details.arg = NULL; - while(len > 0) - { - /* configure the transaction details. - * length is received in bytes, should be specified in words for the SPI - * driver. - */ - if(len > MAX_DMA_RECV_TRANSACTION_SIZE) - { - transact_details.count = (MAX_DMA_RECV_TRANSACTION_SIZE +3)>>2; - transact_details.txBuf = (void*)(pBuff + write_size); - if(SPI_transfer((SPI_Handle)fd, &transact_details)) - { - write_size += MAX_DMA_RECV_TRANSACTION_SIZE; - len = len - MAX_DMA_RECV_TRANSACTION_SIZE; - } - else - { - return -1; - } - } - else - { - transact_details.count = (len+3)>>2; - transact_details.txBuf = (void*)(pBuff + write_size); - if(SPI_transfer((SPI_Handle)fd, &transact_details)) - { - write_size += len; - len = 0; - return write_size; - } - else - { - return -1; - } - } - } - - return(write_size); -} - - -int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue) -{ - - HwiP_Params nwp_iParams; - - HwiP_Params_init(&nwp_iParams); - - HwiP_clearInterrupt(INT_NWPIC); - - if(!InterruptHdl) - { - HwiP_delete(g_intHandle); - return OS_OK; - } - else - { - nwp_iParams.priority = INT_PRIORITY_LVL_1 ; - - } - g_intHandle = HwiP_create(INT_NWPIC , (HwiP_Fxn)(InterruptHdl) , &nwp_iParams); - - if(!g_intHandle) - { - return -1; - } - else - { - return OS_OK ; - } -} - - -void NwpMaskInterrupt() -{ - (*(unsigned long *)N2A_INT_MASK_SET) = 0x1; -} - - -void NwpUnMaskInterrupt() -{ - (*(unsigned long *)N2A_INT_MASK_CLR) = 0x1; -} - - -void NwpPowerOn(void) -{ - /* bring the 1.32 eco out of reset */ - HWREG(NWP_SPARE_REG_5) &= ~NWP_SPARE_REG_5_SLSTOP; - - /* Clear host IRQ indication */ - HWREG(N2A_INT_ACK) = 1; - - /* NWP Wake-up */ - HWREG(WAKENWP) = WAKENWP_WAKEREQ; - - //UnMask Host Interrupt - NwpUnMaskInterrupt(); -} - - -void NwpPowerOff(void) -{ - - volatile unsigned long apps_int_sts_raw; - volatile unsigned long sl_stop_ind = HWREG(NWP_SPARE_REG_5); - volatile unsigned long nwp_lpds_wake_cfg = HWREG(NWP_LPDS_WAKEUPCFG); - _SlTimeoutParams_t SlTimeoutInfo = {0}; - - if((nwp_lpds_wake_cfg != NWP_LPDS_WAKEUPCFG_APPS2NWP) && /* Check for NWP POR condition - APPS2NWP is reset condition */ - !(sl_stop_ind & NWP_SPARE_REG_5_SLSTOP)) /* Check if sl_stop was executed */ - { - HWREG(0xE000E104) = 0x200; /* Enable the out of band interrupt, this is not a wake-up source*/ - HWREG(A2N_INT_TRIG) = 0x1; /* Trigger out of band interrupt */ - HWREG(WAKENWP) = WAKENWP_WAKEREQ; /* Wake-up the NWP */ - - _SlDrvStartMeasureTimeout(&SlTimeoutInfo, NWP_N2A_INT_ACK_TIMEOUT_MSEC); - - /* Wait for the A2N_INT_TRIG to be cleared by the NWP to indicate it's awake and ready for shutdown. - * poll until APPs->NWP interrupt is cleared or timeout : - * for service pack 3.1.99.1 or higher, this condition is fulfilled in less than 1 mSec. - * Otherwise, in some cases it may require up to 3000 mSec of waiting. */ - - apps_int_sts_raw = HWREG(A2N_INT_STS_RAW); - while(!(apps_int_sts_raw & 0x1)) - { - if(_SlDrvIsTimeoutExpired(&SlTimeoutInfo)) - { - break; - } - apps_int_sts_raw = HWREG(A2N_INT_STS_RAW); - } - - WAIT_NWP_SHUTDOWN_READY; - } - - /* Clear Out of band interrupt, Acked by the NWP */ - HWREG(A2N_INT_STS_CLR) = 0x1; - - /* Mask Host Interrupt */ - NwpMaskInterrupt(); - - /* Switch to PFM Mode */ - HWREG(ANA_DCDC_PARAMS0) &= ~ANA_DCDC_PARAMS0_PWMOVERRIDE; - - /* sl_stop ECO for PG1.32 devices */ - HWREG(NWP_SPARE_REG_5) |= NWP_SPARE_REG_5_SLSTOP; - - /* Wait for 20 uSec, which is the minimal time between on-off cycle */ - uSEC_DELAY(20); -} - -#if defined(SL_PLATFORM_MULTI_THREADED) - -int Semaphore_pend_handle(sem_t* pSemHandle, uint32_t timeout) -{ - if (OS_WAIT_FOREVER == timeout) - { - return sem_wait(pSemHandle); - } - else - { - struct timespec abstime; - abstime.tv_nsec = 0; - abstime.tv_sec = 0; - - /* Since POSIX timeout are relative and not absolute, - * take the current timestamp. */ - clock_gettime(CLOCK_REALTIME, &abstime); - if(abstime.tv_nsec < 0) - { - abstime.tv_sec = timeout; - return (sem_timedwait(pSemHandle, &abstime)); - } - - /* Add the amount of time to wait */ - abstime.tv_sec += timeout / 1000; - abstime.tv_nsec += (timeout % 1000) * 1000000; - - abstime.tv_sec += (abstime.tv_nsec / 1000000000); - abstime.tv_nsec = abstime.tv_nsec % 1000000000; - - /* Call the semaphore wait API */ - return(sem_timedwait(pSemHandle, &abstime)); - } -} - -int Mutex_create_handle(pthread_mutex_t *pMutexHandle) -{ - pthread_mutexattr_t attr; - pthread_mutexattr_init(&attr); - pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE); - - if (pthread_mutex_init(pMutexHandle, &attr) < 0) - { - return Mutex_FAILURE ; - } - - return Mutex_OK; -} - - -#else - -int Mutex_create_handle(MutexP_Handle* pMutexHandle) -{ - MutexP_Params params; - - MutexP_Params_init(¶ms); - - params.callback = tiDriverSpawnCallback; - - (*(pMutexHandle)) = MutexP_create(¶ms); - - if(!(*(pMutexHandle))) - { - return Mutex_FAILURE ; - } - - return Mutex_OK; -} - -int MutexP_delete_handle(MutexP_Handle* pMutexHandle) -{ - MutexP_delete(*(pMutexHandle)); - return(Mutex_OK); -} - -int Mutex_unlock(MutexP_Handle pMutexHandle) -{ - MutexP_unlock(pMutexHandle, 0); - return(Mutex_OK); -} - - -int Mutex_lock(MutexP_Handle pMutexHandle) -{ - MutexP_lock(pMutexHandle); - return(Mutex_OK); -} - -int SemaphoreP_create_handle(SemaphoreP_Handle* pSemHandle) -{ - SemaphoreP_Params params; - - SemaphoreP_Params_init(¶ms); - - params.mode = SemaphoreP_Mode_BINARY; - - params.callback = tiDriverSpawnCallback; - - (*(pSemHandle)) = SemaphoreP_create(1, ¶ms); - - if(!(*(pSemHandle))) - { - return Semaphore_FAILURE ; - } - - return Semaphore_OK; -} - -int SemaphoreP_delete_handle(SemaphoreP_Handle* pSemHandle) -{ - SemaphoreP_delete(*(pSemHandle)); - return Semaphore_OK; -} - -int SemaphoreP_post_handle(SemaphoreP_Handle* pSemHandle) -{ - SemaphoreP_post(*(pSemHandle)); - return Semaphore_OK; -} -#endif - - -unsigned long TimerGetCurrentTimestamp() -{ - return (ClockP_getSystemTicks()); -} - - -void NwpWaitForShutDownInd() -{ - volatile unsigned long nwp_wakup_ind = HWREG(NWP_LPDS_WAKEUPCFG); - _SlTimeoutParams_t SlTimeoutInfo = {0}; - - _SlDrvStartMeasureTimeout(&SlTimeoutInfo, NWP_LPDS_WAKEUPCFG_TIMEOUT_MSEC); - - while(nwp_wakup_ind != NWP_LPDS_WAKEUPCFG_APPS2NWP) - { - if(_SlDrvIsTimeoutExpired(&SlTimeoutInfo)) - { - return; - } - nwp_wakup_ind = HWREG(NWP_LPDS_WAKEUPCFG); - } - - return ; -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/cc_pal.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/cc_pal.h deleted file mode 100644 index 9afc8e05802..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/cc_pal.h +++ /dev/null @@ -1,444 +0,0 @@ -/* - * cc_pal.h - CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ -/****************************************************************************** -* cc_pal.h -* -* SimpleLink Wi-Fi abstraction file for CC32xx -******************************************************************************/ - -#ifndef __CC31xx_PAL_H__ -#define __CC31xx_PAL_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -#include -#if defined(SL_PLATFORM_MULTI_THREADED) -/* Use Zephyr posix headers */ - -/* - * Hacks to prevent redefining symbols in posix headers. Currently it is not - * possible to include both socket.h and some posix headers without build - * errors (issue #13444). So we are disabling some headers, and defining - * only what is necessary. We should remove these when the POSIX integration - * story has improved. - */ -#define ZEPHYR_INCLUDE_POSIX_TIME_H_ -#define ZEPHYR_INCLUDE_POSIX_UNISTD_H_ -#define ZEPHYR_INCLUDE_POSIX_SYS_STAT_H_ -#include -extern int clock_gettime(clockid_t clock_id, struct timespec *ts); -extern int usleep(useconds_t useconds); - -#include -#include -#include -#else //SL_PLATFORM_MULTI_THREADED -#include -#include - -#endif - - - - - -#define MAX_QUEUE_SIZE (4) -#define OS_WAIT_FOREVER (0xFFFFFFFF) -#define OS_NO_WAIT (0) -#define OS_OK (0) - -#define Semaphore_OK (0) -#define Semaphore_FAILURE (-1) - -#define Mutex_OK (0) -#define Mutex_FAILURE (-1) - - -/*! - \brief type definition for the SPI channel file descriptor - - \note On each porting or platform the type could be whatever is needed - integer, pointer to structure etc. -*/ -typedef int Fd_t; - - -/*! - \brief type definition for the host interrupt handler - - \param pValue - pointer to any memory strcuture. The value of this pointer is given on - registration of a new interrupt handler - - \note -*/ - -typedef void (*SL_P_EVENT_HANDLER)(void); - -#define P_EVENT_HANDLER SL_P_EVENT_HANDLER - -/*! - \brief type definition for the host spawn function - - \param pValue - pointer to any memory strcuture. The value of this pointer is given on - invoking the spawn function. - - \note -*/ - -typedef signed short (*P_OS_SPAWN_ENTRY)(void* pValue); - -typedef struct -{ - P_OS_SPAWN_ENTRY pEntry; - void* pValue; -}tSimpleLinkSpawnMsg; - -/*! - \brief open spi communication port to be used for communicating with a SimpleLink device - - Given an interface name and option flags, this function opens the spi communication port - and creates a file descriptor. This file descriptor can be used afterwards to read and - write data from and to this specific spi channel. - The SPI speed, clock polarity, clock phase, chip select and all other attributes are all - set to hardcoded values in this function. - - \param ifName - points to the interface name/path. The interface name is an - optional attributes that the SimpleLink driver receives - on opening the device. in systems that the spi channel is - not implemented as part of the os device drivers, this - parameter could be NULL. - \param flags - option flags - - \return upon successful completion, the function shall open the spi channel and return - a non-negative integer representing the file descriptor. - Otherwise, -1 shall be returned - - \sa spi_Close , spi_Read , spi_Write - \note - \warning -*/ -Fd_t spi_Open(char *ifName, unsigned long flags); - -/*! - \brief closes an opened SPI communication port - - \param fd - file descriptor of an opened SPI channel - - \return upon successful completion, the function shall return 0. - Otherwise, -1 shall be returned - - \sa spi_Open - \note - \warning -*/ -int spi_Close(Fd_t fd); - -/*! - \brief attempts to read up to len bytes from SPI channel into a buffer starting at pBuff. - - \param fd - file descriptor of an opened SPI channel - - \param pBuff - points to first location to start writing the data - - \param len - number of bytes to read from the SPI channel - - \return upon successful completion, the function shall return 0. - Otherwise, -1 shall be returned - - \sa spi_Open , spi_Write - \note - \warning -*/ -int spi_Read(Fd_t fd, unsigned char *pBuff, int len); - -/*! - \brief attempts to write up to len bytes to the SPI channel - - \param fd - file descriptor of an opened SPI channel - - \param pBuff - points to first location to start getting the data from - - \param len - number of bytes to write to the SPI channel - - \return upon successful completion, the function shall return 0. - Otherwise, -1 shall be returned - - \sa spi_Open , spi_Read - \note This function could be implemented as zero copy and return only upon successful completion - of writing the whole buffer, but in cases that memory allocation is not too tight, the - function could copy the data to internal buffer, return back and complete the write in - parallel to other activities as long as the other SPI activities would be blocked untill - the entire buffer write would be completed - \warning -*/ -int spi_Write(Fd_t fd, unsigned char *pBuff, int len); - -/*! - \brief register an interrupt handler for the host IRQ - - \param InterruptHdl - pointer to interrupt handler function - - \param pValue - pointer to a memory strcuture that is passed to the interrupt handler. - - \return upon successful registration, the function shall return 0. - Otherwise, -1 shall be returned - - \sa - \note If there is already registered interrupt handler, the function should overwrite the old handler - with the new one - \warning -*/ -int NwpRegisterInterruptHandler(P_EVENT_HANDLER InterruptHdl , void* pValue); - - -/*! - \brief Masks host IRQ - - - \sa NwpUnMaskInterrupt - - \warning -*/ -void NwpMaskInterrupt(); - - -/*! - \brief Unmasks host IRQ - - - \sa NwpMaskInterrupt - - \warning -*/ -void NwpUnMaskInterrupt(); - - -/*! - \brief Preamble to the enabling the Network Processor. - Placeholder to implement any pre-process operations - before enabling networking operations. - - \sa sl_DeviceEnable - - \note belongs to \ref ported_sec - -*/ - -void NwpPowerOnPreamble(void); - - - -/*! - \brief Disable the Network Processor - - \sa sl_DeviceEnable - - \note belongs to \ref ported_sec -*/ -void NwpPowerOff(void); - - -/*! - \brief Enable the Network Processor - - \sa sl_DeviceDisable - - \note belongs to \ref ported_sec - -*/ -void NwpPowerOn(void); - - - - -#if defined(SL_PLATFORM_MULTI_THREADED) - -/*! - \brief Time wait for a semaphore handle, using the driver porting layer of the core SDK. - - \param pSemHandle - pointer to a memory structure that would contain the handle. - - \param timeout - specify the time to wait for the signal - - \return The function shall return 0. - - \note belongs to \ref ported_sec -*/ -int Semaphore_pend_handle(sem_t* pSemHandle, uint32_t timeout); - -/*! - \brief Creates a mutex object handle, using the driver porting layer of the core SDK. - - \param pMutexHandle - pointer to a memory structure that would contain the handle. - - \return upon successful creation, the function shall return 0. - Otherwise, -1 shall be returned - - \note belongs to \ref ported_sec -*/ -int Mutex_create_handle(pthread_mutex_t* pMutexHandle); - - -/*! - \brief Deletes a mutex object handle, using the driver porting layer of the core SDK. - - \param pMutexHandle - pointer to a memory structure that would contain the handle. - - \return the function shall return 0. - - \note belongs to \ref ported_sec -*/ -int MutexP_delete_handle(pthread_mutex_t* pMutexHandle); - - -#else - -/*! - \brief Creates a semaphore handle, using the driver porting layer of the core SDK. - - \param pSemHandle - pointer to a memory structure that would contain the handle. - - \return upon successful creation, the function shall return 0. - Otherwise, -1 shall be returned - - \note belongs to \ref ported_sec -*/ -int SemaphoreP_create_handle(SemaphoreP_Handle* pSemHandle); - - -/*! - \brief Deletes a semaphore handle, using the driver porting layer of the core SDK. - - \param pSemHandle - pointer to a memory structure that would contain the handle. - - \return The function shall return 0. - - \note belongs to \ref ported_sec -*/ -int SemaphoreP_delete_handle(SemaphoreP_Handle* pSemHandle); - - -/*! - \brief Post (signal) a semaphore handle, using the driver porting layer of the core SDK. - - \param pSemHandle - pointer to a memory structure that would contain the handle. - - \return The function shall return 0. - - \note belongs to \ref ported_sec -*/ -int SemaphoreP_post_handle(SemaphoreP_Handle* pSemHandle); -/*! - \brief Creates a mutex object handle, using the driver porting layer of the core SDK. - - \param pMutexHandle - pointer to a memory structure that would contain the handle. - - \return upon successful creation, the function shall return 0. - Otherwise, -1 shall be returned - - \note belongs to \ref ported_sec -*/ -int Mutex_create_handle(MutexP_Handle* pMutexHandle); - - -/*! - \brief Deletes a mutex object handle, using the driver porting layer of the core SDK. - - \param pMutexHandle - pointer to a memory structure that would contain the handle. - - \return the function shall return 0. - - \note belongs to \ref ported_sec -*/ -int MutexP_delete_handle(MutexP_Handle* pMutexHandle); - -/*! - \brief Unlocks a mutex object. - - \param pMutexHandle - pointer to a memory structure that contains the object. - - \return upon successful unlocking, the function shall return 0. - - \note belongs to \ref ported_sec -*/ -int Mutex_unlock(MutexP_Handle pMutexHandle); - - -/*! - \brief Locks a mutex object. - - \param pMutexHandle - pointer to a memory structure that contains the object. - - \return upon successful locking, the function shall return 0. - - \note belongs to \ref ported_sec - - \warning The lock will block until the mutex is available. -*/ -int Mutex_lock(MutexP_Handle pMutexHandle); -#endif - -/*! - \brief Take a time stamp value. - - \return 32-bit value of the systick counter. - - \sa - - \warning -*/ -unsigned long TimerGetCurrentTimestamp(); - -/*! - \brief - - \return - - \sa - - \warning -*/ -void NwpWaitForShutDownInd(); - - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/user.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/user.h deleted file mode 100644 index e275cbe060c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/porting/user.h +++ /dev/null @@ -1,1533 +0,0 @@ -/* - * user.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017-2019 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -/****************************************************************************** -* user.h - CC31xx/CC32xx Host Driver Implementation -******************************************************************************/ - -#ifndef __USER_H__ -#define __USER_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -#include -#include - -typedef signed int _SlFd_t; - -#define SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS (_u32)(10) -#define SL_TIMESTAMP_MAX_VALUE (_u32)(0xFFFFFFFF) - -/*! - ****************************************************************************** - - \defgroup configuration_mem_mgm Configuration - Memory Management - - This section declare in which memory management model the SimpleLink driver - will run: - -# Static - -# Dynamic - - This section IS NOT REQUIRED in case Static model is selected. - - The default memory model is Static - - - @{ - - ***************************************************************************** -*/ - -/*! - \brief Defines whether the SimpleLink driver is working in dynamic - memory model or not - - When defined, the SimpleLink driver use dynamic allocations - if dynamic allocation is selected malloc and free functions - must be retrieved - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define SL_MEMORY_MGMT_DYNAMIC - -#ifdef SL_MEMORY_MGMT_DYNAMIC - - -#include -/*! - \brief - \sa - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_Malloc(Size) malloc(Size) - -/*! - \brief - \sa - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_Free(pMem) free(pMem) -#endif - - -/*! - - Close the Doxygen group. - @} - -*/ - -/*! - - \def MAX_CONCURRENT_ACTIONS - - \brief Defines the maximum number of concurrent action in the system - Min:1 , Max: 32 - - Actions which has async events as return, will be blocked until the event arrive - - \sa - - \note In case there are not enough resources for the actions needed in the system, - error is received: SL_POOL_IS_EMPTY - one option is to increase MAX_CONCURRENT_ACTIONS - (improves performance but results in memory consumption) - Other option is to call the API later (decrease performance) - - Async events which arrive during command context will be dynamically or static - allocated and handled in spawn context. If MAX_CONCURRENT_ACTIONS - is high, there will be more events which might arrive during this period. - Due to memory constrains MAX_CONCURRENT_ACTIONS is lower in static allocation mode. - - - \warning In case of setting to one, recommend to use non-blocking recv\recvfrom to allow - multiple socket recv -*/ - -#ifdef SL_MEMORY_MGMT_DYNAMIC -#define MAX_CONCURRENT_ACTIONS 18 -#else -#define MAX_CONCURRENT_ACTIONS 5 -#endif - - - /*! - \def SL_MAX_ASYNC_BUFFERS - - - - \brief Defines the maximum static buffers to store asycn events which - arrives during command context. The event is stored in a buffer (if free) - and handle in spwan cotext. value must be set to MAX_CONCURRENT_ACTIONS which - is the maximum simultaniuos async event which could arrive in command context. - value: MAX_CONCURRENT_ACTIONS - - \sa - - \note Events which arrive when there is no free buffer will be dropped. - If there is a command which is waiting on this event, it will be released - with error SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR. - In this case need to increase MAX_CONCURRENT_ACTIONS - (improves performance but results in memory consumption) - - - */ - -#define SL_MAX_ASYNC_BUFFERS MAX_CONCURRENT_ACTIONS -/*! - \def CPU_FREQ_IN_MHZ - \brief Defines CPU frequency for Host side, for better accuracy of busy loops, if any - \sa - \note - - \warning If not set the default CPU frequency is set to 200MHz - This option will be deprecated in future release -*/ - -/* #define CPU_FREQ_IN_MHZ 80 */ - - - -/*! - \def SL_RUNTIME_EVENT_REGISTERATION - - \brief Defines whether the SimpleLink driver uses dynamic event registration - or static precompiled event mechanism - \sa - - \note belongs to \ref configuration_sec - -*/ -#define SL_RUNTIME_EVENT_REGISTERATION - - -/*! - \def SL_INC_ARG_CHECK - - \brief Defines whether the SimpleLink driver perform argument check - or not - - When defined, the SimpleLink driver perform argument check on - function call. Removing this define could reduce some code - size and improve slightly the performances but may impact in - unpredictable behavior in case of invalid arguments - - \sa - - \note belongs to \ref configuration_sec - - \warning Removing argument check may cause unpredictable behavior in - case of invalid arguments. - In this case the user is responsible to argument validity - (for example all handlers must not be NULL) -*/ -#define SL_INC_ARG_CHECK - - -/*! - \brief Defines whether to include extended API in SimpleLink driver - or not - - When defined, the SimpleLink driver will include also all - extended API of the included packages - - \sa ext_api - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_EXT_API - - -/*! - \brief Defines whether to include WLAN package in SimpleLink driver - or not - - When defined, the SimpleLink driver will include also - the WLAN package - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_WLAN_PKG - - -/*! - \brief Defines whether to include SOCKET package in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also - the SOCKET package - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_SOCKET_PKG - - -/*! - \brief Defines whether to include NET_APP package in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also the - NET_APP package - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_NET_APP_PKG - - -/*! - \brief Defines whether to include NET_CFG package in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also - the NET_CFG package - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_NET_CFG_PKG - - -/*! - \brief Defines whether to include NVMEM package in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also the - NVMEM package - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_NVMEM_PKG - - -/*! - \brief Defines whether to include NVMEM extended package in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also the - NVMEM extended package - - \sa - - \note belongs to \ref nvmem_ext - - \warning -*/ -#define SL_INC_NVMEM_EXT_PKG - - -/*! - \brief Defines whether to include socket server side APIs - in SimpleLink driver or not - - When defined, the SimpleLink driver will include also socket - server side APIs - - \sa server_side - - \note - - \warning -*/ -#define SL_INC_SOCK_SERVER_SIDE_API - - -/*! - \brief Defines whether to include socket client side APIs in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also socket - client side APIs - - \sa client_side - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_SOCK_CLIENT_SIDE_API - - -/*! - \brief Defines whether to include socket receive APIs in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also socket - receive side APIs - - \sa recv_api - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_SOCK_RECV_API - - -/*! - \brief Defines whether to include socket send APIs in SimpleLink - driver or not - - When defined, the SimpleLink driver will include also socket - send side APIs - - \sa send_api - - \note belongs to \ref configuration_sec - - \warning -*/ -#define SL_INC_SOCK_SEND_API - - -/*! - - Close the Doxygen group. - @} - - */ - - -/*! - ****************************************************************************** - - \defgroup configuration_enable_device Configuration - Device Enable/Disable - - The enable/disable API provide mechanism to enable/disable the network processor - - - porting ACTION: - - None - @{ - - ****************************************************************************** - */ - -/*! - \brief Preamble to the enabling the Network Processor. - Placeholder to implement any pre-process operations - before enabling networking operations. - - \sa sl_DeviceEnable - - \note belongs to \ref configuration_sec - -*/ -#define sl_DeviceEnablePreamble() - - - -/*! - \brief Enable the Network Processor - - \sa sl_DeviceDisable - - \note belongs to \ref configuration_sec - -*/ -#define sl_DeviceEnable() NwpPowerOn() - - -/*! - \brief Disable the Network Processor - - \sa sl_DeviceEnable - - \note belongs to \ref configuration_sec -*/ -#define sl_DeviceDisable() NwpPowerOff() - - -/*! - - Close the Doxygen group. - @} - - */ - -/*! - ****************************************************************************** - - \defgroup configuration_interface Configuration - Communication Interface - - The SimpleLink device supports several standard communication protocol among SPI and - UART. CC32XX Host Driver implements SPI Communication Interface - - - \note In CC32XX, SPI implementation uses DMA in order to increase the utilization - of the communication channel. If user prefers to user UART, these interfaces - need to be redefined - - - porting ACTION: - - None - - @{ - - ****************************************************************************** -*/ - -#define _SlFd_t Fd_t - - -/*! - \brief Opens an interface communication port to be used for communicating - with a SimpleLink device - - Given an interface name and option flags, this function opens - the communication port and creates a file descriptor. - This file descriptor is used afterwards to read and write - data from and to this specific communication channel. - The speed, clock polarity, clock phase, chip select and all other - specific attributes of the channel are all should be set to hardcoded - in this function. - - \param ifName - points to the interface name/path. The interface name is an - optional attributes that the SimpleLink driver receives - on opening the driver (sl_Start). - In systems that the spi channel is not implemented as - part of the os device drivers, this parameter could be NULL. - - \param flags - optional flags parameters for future use - - \return upon successful completion, the function shall open the channel - and return a non-negative integer representing the file descriptor. - Otherwise, -1 shall be returned - - \sa sl_IfClose , sl_IfRead , sl_IfWrite - - \note The prototype of the function is as follow: - Fd_t xxx_IfOpen(char* pIfName , unsigned long flags); - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfOpen spi_Open - - -/*! - \brief Closes an opened interface communication port - - \param fd - file descriptor of opened communication channel - - \return upon successful completion, the function shall return 0. - Otherwise, -1 shall be returned - - \sa sl_IfOpen , sl_IfRead , sl_IfWrite - - \note The prototype of the function is as follow: - int xxx_IfClose(Fd_t Fd); - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfClose spi_Close - - -/*! - \brief Attempts to read up to len bytes from an opened communication channel - into a buffer starting at pBuff. - - \param fd - file descriptor of an opened communication channel - - \param pBuff - pointer to the first location of a buffer that contains enough - space for all expected data - - \param len - number of bytes to read from the communication channel - - \return upon successful completion, the function shall return the number of read bytes. - Otherwise, 0 shall be returned - - \sa sl_IfClose , sl_IfOpen , sl_IfWrite - - - \note The prototype of the function is as follow: - int xxx_IfRead(Fd_t Fd , char* pBuff , int Len); - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfRead spi_Read - - -/*! - \brief attempts to write up to len bytes to the SPI channel - - \param fd - file descriptor of an opened communication channel - - \param pBuff - pointer to the first location of a buffer that contains - the data to send over the communication channel - - \param len - number of bytes to write to the communication channel - - \return upon successful completion, the function shall return the number of sent bytes. - therwise, 0 shall be returned - - \sa sl_IfClose , sl_IfOpen , sl_IfRead - - \note This function could be implemented as zero copy and return only upon successful completion - of writing the whole buffer, but in cases that memory allocation is not too tight, the - function could copy the data to internal buffer, return back and complete the write in - parallel to other activities as long as the other SPI activities would be blocked until - the entire buffer write would be completed - - The prototype of the function is as follow: - int xxx_IfWrite(Fd_t Fd , char* pBuff , int Len); - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfWrite spi_Write - - -/*! - \brief register an interrupt handler routine for the host IRQ - - \param InterruptHdl - pointer to interrupt handler routine - - \param pValue - pointer to a memory structure that is passed - to the interrupt handler. - - \return upon successful registration, the function shall return 0. - Otherwise, -1 shall be returned - - \sa - - \note If there is already registered interrupt handler, the function - should overwrite the old handler with the new one - - \note If the handler is a null pointer, the function should un-register the - interrupt handler, and the interrupts can be disabled. - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfRegIntHdlr(InterruptHdl , pValue) NwpRegisterInterruptHandler(InterruptHdl , pValue) - - -/*! - \brief Masks the Host IRQ - - \sa sl_IfUnMaskIntHdlr - - - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfMaskIntHdlr() NwpMaskInterrupt() - - -/*! - \brief Unmasks the Host IRQ - - \sa sl_IfMaskIntHdlr - - - - \note belongs to \ref configuration_sec - - \warning -*/ -#define sl_IfUnMaskIntHdlr() NwpUnMaskInterrupt() - - -/*! - \brief Write Handers for statistics debug on write - - \param interface handler - pointer to interrupt handler routine - - - \return no return value - - \sa - - \note An optional hooks for monitoring before and after write info - - \note belongs to \ref configuration_sec - - \warning -*/ -/* #define SL_START_WRITE_STAT */ - -#ifdef SL_START_WRITE_STAT -#define sl_IfStartWriteSequence -#define sl_IfEndWriteSequence -#endif - - -/*! - \brief Get the timer counter value (timestamp). - The timer must count from zero to its MAX value. - - \param None. - - - \return Returns 32-bit timer counter value (ticks unit) - - \sa - - \note - - \note belongs to \ref porting_sec - - \warning -*/ - -#undef slcb_GetTimestamp -/* A timer must be started before using this function */ -#define slcb_GetTimestamp TimerGetCurrentTimestamp - - -/*! - \brief This macro wait for the NWP to raise a ready for shutdown indication. - - \param None. - - \note This function is unique for the CC32XX family - - \warning -*/ - -#define WAIT_NWP_SHUTDOWN_READY NwpWaitForShutDownInd() - -/*! - \brief User's errno setter function. User must provide an errno setter - in order to let the SimpleLink Wi-Fi driver to support BSD API - alongside the user's errno mechanism. - - \param None. - - \sa SL_INC_INTERNAL_ERRNO - - \note - - \note belongs to \ref porting_sec - - \warning -*/ -#ifndef SL_INC_INTERNAL_ERRNO -/* - * Zephyr Port: use Zephyr SDK's errno.h definitions, and supply those missing - * to allow the SimpleLink driver.c to compile - * Also, supply the external errno setter function. - */ -#include -#define ERROR EIO -#define INEXE EALREADY -#define ENSOCK ENFILE - -extern int dpl_set_errno(int err); -#define slcb_SetErrno dpl_set_errno - -#endif - -/*! - Close the Doxygen group. - @} - -*/ - -/*! - ****************************************************************************** - - \defgroup configuration_os Configuration - Operating System - - The SimpleLink driver could run on two kind of platforms: - -# Non-Os / Single Threaded (default) - -# Multi-Threaded - - CC32XX SimpleLink Host Driver is ported on both Non-Os and Multi Threaded OS enviroment. - The Host driver is made OS independent by implementing an OS Abstraction layer. - Reference implementation for OS Abstraction is available for FreeRTOS and TI-RTOS. - - - If you choose to work in multi-threaded environment under different operating system you - will have to provide some basic adaptation routines to allow the driver to protect access to - resources for different threads (locking object) and to allow synchronization between threads - (sync objects). In additional the driver support running without dedicated thread allocated solely - to the SimpleLink driver. If you choose to work in this mode, you should also supply a spawn - method that will enable to run function on a temporary context. - - \note - This Macro is defined in the IDE to generate Driver for both OS and Non-OS - - porting ACTION: - - None - - @{ - - ****************************************************************************** -*/ - -/* -#define SL_PLATFORM_MULTI_THREADED -*/ - -#ifdef SL_PLATFORM_MULTI_THREADED - -/*! - \brief - \sa - \note belongs to \ref configuration_sec - \warning -*/ -#define SL_OS_RET_CODE_OK ((int)OS_OK) - -/*! - \brief - \sa - \note belongs to \ref configuration_sec - \warning -*/ -#define SL_OS_WAIT_FOREVER ((uint32_t)OS_WAIT_FOREVER) - -/*! - \brief - \sa - \note belongs to \ref configuration_sec - \warning -*/ -#define SL_OS_NO_WAIT ((uint32_t)OS_NO_WAIT) - -/*! - \brief type definition for a time value - - \note On each configuration or platform the type could be whatever is needed - integer, pointer to structure etc. - - \note belongs to \ref configuration_sec -*/ -#define _SlTime_t uint32_t - - - - -/*! - \brief type definition for a sync object container - - Sync object is object used to synchronize between two threads or thread and interrupt handler. - One thread is waiting on the object and the other thread send a signal, which then - release the waiting thread. - The signal must be able to be sent from interrupt context. - This object is generally implemented by binary semaphore or events. - - \note On each configuration or platform the type could be whatever is needed - integer, structure etc. - - \note belongs to \ref configuration_sec -*/ -#define _SlSyncObj_t sem_t - - -/*! - \brief This function creates a sync object - - The sync object is used for synchronization between different thread or ISR and - a thread. - - \param pSyncObj - pointer to the sync object control block - - \return upon successful creation the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_SyncObjCreate(pSyncObj,pName) sem_init(pSyncObj, 0, 0) - - -/*! - \brief This function deletes a sync object - - \param pSyncObj - pointer to the sync object control block - - \return upon successful deletion the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_SyncObjDelete(pSyncObj) sem_destroy(pSyncObj) - - -/*! - \brief This function generates a sync signal for the object. - - All suspended threads waiting on this sync object are resumed - - \param pSyncObj - pointer to the sync object control block - - \return upon successful signaling the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note the function could be called from ISR context - \warning -*/ -#define sl_SyncObjSignal(pSyncObj) sem_post(pSyncObj) - - -/*! - \brief This function generates a sync signal for the object from Interrupt - - This is for RTOS that should signal from IRQ using a dedicated API - - \param pSyncObj - pointer to the sync object control block - - \return upon successful signaling the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note the function could be called from ISR context - \warning -*/ -#define sl_SyncObjSignalFromIRQ(pSyncObj) sem_post(pSyncObj) - - -/*! - \brief This function waits for a sync signal of the specific sync object - - \param pSyncObj - pointer to the sync object control block - \param Timeout - numeric value specifies the maximum number of mSec to - stay suspended while waiting for the sync signal - Currently, the SimpleLink driver uses these values: - - OSI_NO_WAIT - - SL_DRIVER_TIMEOUT_SHORT - - SL_DRIVER_TIMEOUT_LONG - - SL_OS_WAIT_FOREVER - \return upon successful reception of the signal within the timeout window return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_SyncObjWait(pSyncObj,Timeout) Semaphore_pend_handle(pSyncObj,Timeout) - - -/*! - \brief This function return the value for a counting semaphore - - \param pSyncObj - pointer to the sync object control block - \param pValue - return value for the counting semaphore - - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_SyncObjGetCount(pSyncObj,pValue) sem_getvalue(pSyncObj, pValue); - -/*! - \brief type definition for a locking object container - - Locking object are used to protect a resource from mutual accesses of two or more threads. - The locking object should support reentrant locks by a signal thread. - This object is generally implemented by mutex semaphore - - \note On each configuration or platform the type could be whatever is needed - integer, structure etc. - \note belongs to \ref configuration_sec -*/ -#define _SlLockObj_t pthread_mutex_t - -/*! - \brief This function creates a locking object. - - The locking object is used for protecting a shared resources between different - threads. - - \param pLockObj - pointer to the locking object control block - - \return upon successful creation the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_LockObjCreate(pLockObj, pName) Mutex_create_handle(pLockObj) - - -/*! - \brief This function deletes a locking object. - - \param pLockObj - pointer to the locking object control block - - \return upon successful deletion the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_LockObjDelete(pLockObj) pthread_mutex_destroy(pLockObj) - - -/*! - \brief This function locks a locking object. - - All other threads that call this function before this thread calls - the osi_LockObjUnlock would be suspended - - \param pLockObj - pointer to the locking object control block - \param Timeout - numeric value specifies the maximum number of mSec to - stay suspended while waiting for the locking object - Currently, the SimpleLink driver uses only two values: - - OSI_WAIT_FOREVER - - OSI_NO_WAIT - - - \return upon successful reception of the locking object the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_LockObjLock(pLockObj,Timeout) pthread_mutex_lock(pLockObj) - - -/*! - \brief This function unlock a locking object. - - \param pLockObj - pointer to the locking object control block - - \return upon successful unlocking the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_LockObjUnlock(pLockObj) pthread_mutex_unlock(pLockObj) - -#else - -/*! - \brief type definition for a sync object container - - Sync object is object used to synchronize between two threads or thread and interrupt handler. - One thread is waiting on the object and the other thread send a signal, which then - release the waiting thread. - The signal must be able to be sent from interrupt context. - This object is generally implemented by binary semaphore or events. - - \note On each configuration or platform the type could be whatever is needed - integer, structure etc. - - \note belongs to \ref configuration_sec -*/ -#define _SlSyncObj_t SemaphoreP_Handle - - -/*! - \brief This function creates a sync object - - The sync object is used for synchronization between different thread or ISR and - a thread. - - \param pSyncObj - pointer to the sync object control block - - \return upon successful creation the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_SyncObjCreate(pSyncObj,pName) SemaphoreP_create_handle(pSyncObj) - - -/*! - \brief This function deletes a sync object - - \param pSyncObj - pointer to the sync object control block - - \return upon successful deletion the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_SyncObjDelete(pSyncObj) SemaphoreP_delete_handle(pSyncObj) - - -/*! - \brief This function generates a sync signal for the object. - - All suspended threads waiting on this sync object are resumed - - \param pSyncObj - pointer to the sync object control block - - \return upon successful signaling the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note the function could be called from ISR context - \warning -*/ -#define sl_SyncObjSignal(pSyncObj) SemaphoreP_post_handle(pSyncObj) - - -/*! - \brief This function generates a sync signal for the object from Interrupt - - This is for RTOS that should signal from IRQ using a dedicated API - - \param pSyncObj - pointer to the sync object control block - - \return upon successful signaling the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note the function could be called from ISR context - \warning -*/ -#define sl_SyncObjSignalFromIRQ(pSyncObj) SemaphoreP_post_handle(pSyncObj) - - -/*! - \brief This function waits for a sync signal of the specific sync object - - \param pSyncObj - pointer to the sync object control block - \param Timeout - numeric value specifies the maximum number of mSec to - stay suspended while waiting for the sync signal - Currently, the SimpleLink driver uses only two values: - - OSI_WAIT_FOREVER - - OSI_NO_WAIT - - \return upon successful reception of the signal within the timeout window return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_SyncObjWait(pSyncObj,Timeout) SemaphoreP_pend((*(pSyncObj)),Timeout) - - - -#define sl_SyncObjGetCount(pSyncObj,pValue) -/*! - \brief type definition for a locking object container - - Locking object are used to protect a resource from mutual accesses of two or more threads. - The locking object should support reentrant locks by a signal thread. - This object is generally implemented by mutex semaphore - - \note On each configuration or platform the type could be whatever is needed - integer, structure etc. - \note belongs to \ref configuration_sec -*/ -#define _SlLockObj_t MutexP_Handle - -/*! - \brief This function creates a locking object. - - The locking object is used for protecting a shared resources between different - threads. - - \param pLockObj - pointer to the locking object control block - - \return upon successful creation the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_LockObjCreate(pLockObj, pName) Mutex_create_handle(pLockObj) - - -/*! - \brief This function deletes a locking object. - - \param pLockObj - pointer to the locking object control block - - \return upon successful deletion the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_LockObjDelete(pLockObj) MutexP_delete_handle(pLockObj) - - -/*! - \brief This function locks a locking object. - - All other threads that call this function before this thread calls - the osi_LockObjUnlock would be suspended - - \param pLockObj - pointer to the locking object control block - \param Timeout - numeric value specifies the maximum number of mSec to - stay suspended while waiting for the locking object - Currently, the SimpleLink driver uses only two values: - - OSI_WAIT_FOREVER - - OSI_NO_WAIT - - - \return upon successful reception of the locking object the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_LockObjLock(pLockObj,Timeout) Mutex_lock(*(pLockObj)) - - -/*! - \brief This function unlock a locking object. - - \param pLockObj - pointer to the locking object control block - - \return upon successful unlocking the function should return 0 - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - \warning -*/ -#define sl_LockObjUnlock(pLockObj) Mutex_unlock(*(pLockObj)) - -#endif - -/*! - \brief This function call the pEntry callback from a different context - - \param pEntry - pointer to the entry callback function - - \param pValue - pointer to any type of memory structure that would be - passed to pEntry callback from the execution thread. - - \param flags - execution flags - reserved for future usage - - \return upon successful registration of the spawn the function should return 0 - (the function is not blocked till the end of the execution of the function - and could be returned before the execution is actually completed) - Otherwise, a negative value indicating the error code shall be returned - \note belongs to \ref configuration_sec - - \warning User must implement it's own 'os_Spawn' function. -*/ -/* Zephyr Port provides its own os_Spawn() implementation */ -#define SL_PLATFORM_EXTERNAL_SPAWN - -#ifdef SL_PLATFORM_EXTERNAL_SPAWN -extern _i16 os_Spawn(P_OS_SPAWN_ENTRY pEntry, void *pValue, unsigned long flags); -#define sl_Spawn(pEntry,pValue,flags) os_Spawn(pEntry,pValue,flags) -#endif - -/*! - * - Close the Doxygen group. - @} - - */ - -/*! - ****************************************************************************** - - \defgroup configuration_events Configuration - Event Handlers - - This section includes the asynchronous event handlers routines - - porting ACTION: - -define your routine as the value of this handler - - @{ - - ****************************************************************************** - */ - - - -/*! - \brief Fatal Error async event for inspecting fatal error events. - This event handles events/errors reported from the device/host driver - - \param[out] pSlFatalErrorEvent - - \par - Parameters: - - - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_DEVICE_ABORT , - - - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_DRIVER_ABORT , - - - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_NO_CMD_ACK , - - - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_SYNC_LOSS , - - - slFatalErrorEvent->Id = SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT , - - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define slcb_DeviceFatalErrorEvtHdlr SimpleLinkFatalErrorEventHandler - -/*! - \brief General async event for inspecting general events. - This event handles events/errors reported from the device/host driver - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define slcb_DeviceGeneralEvtHdlr SimpleLinkGeneralEventHandler - -/*! - \brief WLAN Async event handler - - \param[out] pSlWlanEvent pointer to SlWlanEvent_t data - - \par - Parameters: - - - pSlWlanEvent->Event = SL_WLAN_CONNECT_EVENT , STA or P2P client connection indication event - - pSlWlanEvent->EventData.STAandP2PModeWlanConnected main fields: - - ssid_name - - ssid_len - - bssid - - go_peer_device_name - - go_peer_device_name_len - - - pSlWlanEvent->Event = SL_WLAN_DISCONNECT_EVENT , STA or P2P client disconnection event - - pSlWlanEvent->EventData.STAandP2PModeDisconnected main fields: - - ssid_name - - ssid_len - - reason_code - - - pSlWlanEvent->Event = SL_WLAN_STA_CONNECTED_EVENT , AP/P2P(Go) connected STA/P2P(Client) - - pSlWlanEvent->EventData.APModeStaConnected fields: - - go_peer_device_name - - mac - - go_peer_device_name_len - - wps_dev_password_id - - own_ssid: relevant for event sta-connected only - - own_ssid_len: relevant for event sta-connected only - - - pSlWlanEvent->Event = SL_WLAN_STA_DISCONNECTED_EVENT , AP/P2P(Go) disconnected STA/P2P(Client) - - pSlWlanEvent->EventData.APModestaDisconnected fields: - - go_peer_device_name - - mac - - go_peer_device_name_len - - wps_dev_password_id - - own_ssid: relevant for event sta-connected only - - own_ssid_len: relevant for event sta-connected only - - - pSlWlanEvent->Event = SL_WLAN_SMART_CONFIG_COMPLETE_EVENT - - pSlWlanEvent->EventData.smartConfigStartResponse fields: - - status - - ssid_len - - ssid - - private_token_len - - private_token - - - pSlWlanEvent->Event = SL_WLAN_SMART_CONFIG_STOP_EVENT - - pSlWlanEvent->EventData.smartConfigStopResponse fields: - - status - - - pSlWlanEvent->Event = SL_WLAN_P2P_DEV_FOUND_EVENT - - pSlWlanEvent->EventData.P2PModeDevFound fields: - - go_peer_device_name - - mac - - go_peer_device_name_len - - wps_dev_password_id - - own_ssid: relevant for event sta-connected only - - own_ssid_len: relevant for event sta-connected only - - - pSlWlanEvent->Event = SL_WLAN_P2P_NEG_REQ_RECEIVED_EVENT - - pSlWlanEvent->EventData.P2PModeNegReqReceived fields - - go_peer_device_name - - mac - - go_peer_device_name_len - - wps_dev_password_id - - own_ssid: relevant for event sta-connected only - - - pSlWlanEvent->Event = SL_WLAN_CONNECTION_FAILED_EVENT , P2P only - - pSlWlanEvent->EventData.P2PModewlanConnectionFailure fields: - - status - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define slcb_WlanEvtHdlr SimpleLinkWlanEventHandler - - -/*! - \brief NETAPP Async event handler - - \param[out] pSlNetApp pointer to SlNetAppEvent_t data - - \par - Parameters: - - pSlWlanEvent->Event = SL_NETAPP_IPV4_IPACQUIRED_EVENT, IPV4 acquired event - - pSlWlanEvent->EventData.ipAcquiredV4 fields: - - ip - - gateway - - dns - - - pSlWlanEvent->Event = SL_NETAPP_IP_LEASED_EVENT, AP or P2P go dhcp lease event - - pSlWlanEvent->EventData.ipLeased fields: - - ip_address - - lease_time - - mac - - - pSlWlanEvent->Event = SL_NETAPP_IP_RELEASED_EVENT, AP or P2P go dhcp ip release event - - pSlWlanEvent->EventData.ipReleased fields - - ip_address - - mac - - reason - - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define slcb_NetAppEvtHdlr SimpleLinkNetAppEventHandler - -/*! - \brief HTTP server async event - - \param[out] pSlHttpServerEvent pointer to SlHttpServerEvent_t - \param[in] pSlHttpServerResponse pointer to SlHttpServerResponse_t - - \par - Parameters: \n - - - pSlHttpServerEvent->Event = SL_NETAPP_HTTPGETTOKENVALUE_EVENT - - pSlHttpServerEvent->EventData fields: - - httpTokenName - - data - - len - - pSlHttpServerResponse->ResponseData fields: - - data - - len - - - pSlHttpServerEvent->Event = SL_NETAPP_HTTPPOSTTOKENVALUE_EVENT - - pSlHttpServerEvent->EventData.httpPostData fields: - - action - - token_name - - token_value - - pSlHttpServerResponse->ResponseData fields: - - data - - len - - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define slcb_NetAppHttpServerHdlr SimpleLinkHttpServerEventHandler - - - -/*! - \brief A handler for handling Netapp requests. - Netapp request types: - For HTTP server: GET / POST (future: PUT / DELETE) - - \param - - \param - - \sa - - \note belongs to \ref porting_sec - - \warning -*/ - -#define slcb_NetAppRequestHdlr SimpleLinkNetAppRequestEventHandler - - - -/*! - \brief A handler for freeing the memory of the NetApp response. - - \param - - \param - - \sa - - \note belongs to \ref porting_sec - - \warning -*/ - -#define slcb_NetAppRequestMemFree SimpleLinkNetAppRequestMemFreeEventHandler - - - -/*! - \brief Socket Async event handler - - \param[out] pSlSockEvent pointer to SlSockEvent_t data - - \par - Parameters:\n - - pSlSockEvent->Event = SL_SOCKET_TX_FAILED_EVENT - - pSlSockEvent->EventData fields: - - sd - - status - - pSlSockEvent->Event = SL_SOCKET_ASYNC_EVENT - - pSlSockEvent->EventData fields: - - sd - - type: SSL_ACCEPT or RX_FRAGMENTATION_TOO_BIG or OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED - - val - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ - -#define slcb_SockEvtHdlr SimpleLinkSockEventHandler - - -/*! - \brief Trigger Async event handler. If define, sl_Select operates only in trigger mode. - To disable trigger mode, handler should not be defined. - - \param[out] pSlTriggerEvent pointer to SlSockTriggerEvent_t data - - \par - Parameters:\n - - pSlTriggerEvent->Event = SL_SOCKET_TRIGGER_EVENT_SELECT - - pSlTriggerEvent->EventData: Not in use - - - \sa - - \note belongs to \ref configuration_sec - - \warning -*/ -#ifndef SL_PLATFORM_MULTI_THREADED -#define slcb_SocketTriggerEventHandler SimpleLinkSocketTriggerEventHandler -#endif -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif // __cplusplus - -#endif // __USER_H__ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/simplelink.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/simplelink.h deleted file mode 100644 index 1428e824a51..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/simplelink.h +++ /dev/null @@ -1,1195 +0,0 @@ -/* - * simplelink.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*! - \mainpage SimpleLink Driver - - \section intro_sec Introduction - - The SimpleLink(tm) CC31xx/CC32xx family allows to add Wi-Fi and networking capabilities - to low-cost embedded products without having prior Wi-Fi, RF or networking expertise.\n - The CC31xx/CC32xx is an ideal solution for microcontroller-based sensor and control - applications such as home appliances, home automation and smart metering.\n - The CC31xx/CC32xx has integrated a comprehensive TCP/IP network stack, Wi-Fi driver and - security supplicant leading to easier portability to microcontrollers, to an - ultra-low memory footprint, all without compromising the capabilities and robustness - of the final application. - - - - \section modules_sec Module Names - To make it simple, TI's SimpleLink CC31xx/CC32xx platform capabilities were divided into modules by topic (Silo).\n - These capabilities range from basic device management through wireless - network configuration, standard BSD socket and much more.\n - Listed below are the various modules in the SimpleLink CC31xx/CC32xx driver: - -# \ref Device - Controls the behaviour of the CC31xx/CC32xx device (start/stop, events masking and obtaining specific device status) - -# \ref FileSystem - Provides file system capabilities to TI's CC31XX that can be used by both the CC31XX device and the user. - -# \ref NetApp - Activates networking applications, such as: HTTP Server, DHCP Server, Ping, DNS and mDNS. - -# \ref NetCfg - Controls the configuration of the device addresses (i.e. IP and MAC addresses) - -# \ref NetUtil - Networking related commands and configuration - -# \ref Socket - Controls standard client/server sockets programming options and capabilities - -# \ref Wlan - Controls the use of the WiFi WLAN module including: - - Connection features, such as: profiles, policies, SmartConfig(tm) - - Advanced WLAN features, such as: scans, rx filters and rx statistics collection - -# \ref UserEvents - Function prototypes for event callback handlers - - \section persistency_sec Persistency - The SimpleLink(tm) device support few different persistency types for settings and configurations:\n - - Temporary - Effective immediately but returned to default after reset\n - - System Persistent - Effective immediately and kept after reset according\n - to system persistent mode\n - - Persistent - Effective immediately and kept after reset regardless the system persistent mode\n - - Optionally Persistent - Effective immediately and kept after reset according to a parameter in the API call\n - - Reset - Persistent but effective only after reset\n - \n - For all Set/Get function in this guide, the type of persistency per relevant parameters will be - described as part of the function description\n - - \section proting_sec Porting Guide - - The porting of the SimpleLink host driver to any new platform is based on few simple steps.\n - This guide takes you through this process step by step. Please follow the instructions - carefully to avoid any problems during this process and to enable efficient and proper - work with the device.\n - Please notice that all modifications and porting adjustments of the driver should be - made in the user.h header file only. Keeping this method ensure smoothly -transaction to new versions of the driver in the future!\n - -The porting process consists of few simple steps: --# Create user.h for the target platform --# Select the capabilities set --# Bind the device enable/disable line --# Writing your interface communication driver --# Choose your memory management model --# OS adaptation --# Set your asynchronous event handlers --# Testing - -For host interface details please refer to: -http://processors.wiki.ti.com/index.php/CC31xx_Host_Interface - -Please see the rest of the page for more details about the different steps. - - \subsection porting_step1 Step 1 - Create your own user.h file - - The first step is to create a user.h file that will include your configurations and - adjustments. \n - The file should be located in the porting directory (the porting directory is in the same level as the source directory)\n - It is recommended to use the empty template provided as part of this driver or - file of other platform such as MSP432 or CC32xx, from one of the wide range - of example applications provided by Texas Instruments. - - \subsection porting_step2 Step 2 - Bind the device enable/disable output line - - The CC31xx has two external hardware lines that can be used to enable/disable the device. - - nReset - - nHib - provides mechanism to enter the device into the least current consumption mode. In - this mode the RTC value is kept. - - The driver manipulates the enable/disable line automatically during sl_Start / sl_Stop.\n - Not connecting one these lines means that the driver could start only once (sl_Stop will not - work correctly and might lead to failure latter on) and the internal provisioning mechanism - could not be used.\n - - To bind these lines the following defines should be defined correctly: - - sl_DeviceEnable - - sl_DeviceDisable - - If some initializations required before the enable/disable macros are called the user can use also the following optional define - - sl_DeviceEnablePreamble - - \subsection porting_step4 Step 4 - Writing your interface communication driver - - The SimpleLink CC31xx has two standard communication interfaces - - SPI - - UART - - The device detects automatically the active interface during initialization. After the detection, the second interface could not be used.\n - - To wrap the driver for the communication channel the following functions should be implemented: - -# sl_IfOpen - -# sl_IfClose - -# sl_IfRead - -# sl_IfWrite - -# sl_IfRegIntHdlr - - The way these functions are implemented has direct effect on the performances of the SimpleLink - device on this target platform. DMA and Jitter Buffer should be considered.\n - - In some platforms the user need to mask the IRQ line when this interrupt could be masked. \n - The driver can call the mask/unmask whenever is needed. To allow this functionality the - user should implement also the following defines: - - sl_IfMaskIntHdlr - - sl_IfUnMaskIntHdlr - - By default the driver is writing the command in few transactions to allow zero-copy mechanism. \n - To enable a Jitter buffer for improving the communication line utilization, the can implement - also the following defines: - - sl_IfStartWriteSequence - - sl_IfEndWriteSequence - - \subsection porting_step5 Step 5 - Choose your memory management model - - The SimpleLink driver support two memory models: - - Static (default) - - Dynamic - - To enable the dynamic memory, the following pre-processor define should be set: \n - #define SL_MEMORY_MGMT_DYNAMIC - - And the following macros should be defined and supplied: - - sl_Malloc - - sl_Free - - Using the dynamic mode will allocate the required resources on sl_Start and release these resource on sl_Stop. - - \subsection porting_step6 Step 6 - OS adaptation - - The SimpleLink driver could run on two kind of platforms: - -# Non-Os / Single Threaded (default) - -# Multi-Threaded - - When building a multi-threaded application. the following pre-processor define must be set: \n - #define SL_PLATFORM_MULTI_THREADED - - If you choose to work in multi-threaded environment under operating system you will have to - provide some basic adaptation routines to allow the driver to protect access to resources - for different threads (locking object) and to allow synchronization between threads (sync objects). - In additional the driver support running without dedicated thread allocated solely to the - SimpleLink driver. If you choose to work in this mode, you should also supply a spawn method that - will enable to run function on a temporary context. - - - \subsection porting_step7 Step 7 - Set your asynchronous event handlers routines - - The SimpleLink device generate asynchronous events in several situations. - These asynchronous events could be masked. - In order to catch these events you have to provide handler routines. - Please notice that if you not provide a handler routine and the event is received, - the driver will drop this event without any indication of this drop. - - - \subsection porting_step8 Step 8 - Run diagnostic tools to validate the correctness of your porting - - The driver is delivered with some porting diagnostic tools to simplify the porting validation process - and to reduce issues latter. It is very important to follow carefully this process. - - The diagnostic process include: - -# Validating interface communication driver - -# Validating basic work with the device - - - \section annex_step Annex Persistency - The SimpleLink(tm) device support few different persistency types for settings and configurations:\n - - Temporary - Effective immediately but returned to default after reset\n - - System Persistent - Effective immediately and kept after reset according\n - - to system persistent mode\n - - Persistent - Effective immediately and kept after reset regardless the system persistent mode\n - - Optionally Persistent - Effective immediately and kept after reset according to a parameter in the API call\n - - Reset - Persistent but effective only after reset\n - -*/ - -#ifndef __SIMPLELINK_H__ -#define __SIMPLELINK_H__ - -/* define the default types - * If user wants to overwrite it, - * he need to undef and define again */ -#define _u8 unsigned char -#define _i8 signed char -#define _u16 unsigned short -#define _i16 signed short -#define _u32 unsigned long -#define _i32 signed long - -#define _volatile volatile -#define _const const - -#include - -#ifdef __cplusplus -extern "C" -{ -#endif - -/*! - \defgroup UserEvents - \short Function prototypes for event callback handlers - -*/ - -/*! \attention Async event activation notes\n - Function prototypes for event callback handlers\n - Event handler function names should be defined in the user.h file\n - e.g.\n - "#define slcb_WlanEvtHdlr SLWlanEventHandler"\n - Indicates all WLAN events are handled by User func "SLWlanEventHandler"\n - Important notes:\n - 1. Event handlers cannot activate another SimpleLink API from the event's context - 2. Event's data is valid during event's context. Any application data - which is required for the user application should be copied or marked - into user's variables - 3. It is not recommended to delay the execution of the event callback handler - -*/ - -/*! - - \addtogroup UserEvents - @{ - -*/ - - -/*****************************************************************************/ -/* Macro declarations for Host Driver version */ -/*****************************************************************************/ -#define SL_DRIVER_VERSION "3.0.1.46" -#define SL_MAJOR_VERSION_NUM 3L -#define SL_MINOR_VERSION_NUM 0L -#define SL_VERSION_NUM 1L -#define SL_SUB_VERSION_NUM 46L - -/*****************************************************************************/ -/* Macro declarations for predefined configurations */ -/*****************************************************************************/ - - -/* #define sl_Memcpy memcpy */ -#define sl_Memset(addr, val, len) memset(addr, val, (size_t)len) -#define sl_Memcpy(dest, src, len) memcpy(dest, src, (size_t)len) -#define sl_Memmove(dest, src, len) memmove(dest, src, (size_t)len) - -#define SL_MAX_SOCKETS (_u8)(16) - - -/*****************************************************************************/ -/* Types definitions */ -/*****************************************************************************/ - -#ifndef NULL -#define NULL (0) -#endif - -#ifndef FALSE -#define FALSE (0) -#endif - -#ifndef TRUE -#define TRUE (!FALSE) -#endif - -typedef _u16 _SlOpcode_t; -typedef _u8 _SlArgSize_t; -typedef _i16 _SlDataSize_t; -typedef _i16 _SlReturnVal_t; - -/* - * This event status used to block or continue the event propagation - * through all the registered external libs/user application - * - */ - - typedef enum { - EVENT_PROPAGATION_BLOCK = 0, - EVENT_PROPAGATION_CONTINUE - } _SlEventPropogationStatus_e; - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - - -/* - objInclusion.h and user.h must be included before all api header files - objInclusion.h must be the last arrangement just before including the API header files - since it based on the other configurations to decide which object should be included -*/ -#include "source/objInclusion.h" -#include "trace.h" -#include "fs.h" -#include "sl_socket.h" -#include "netapp.h" -#include "wlan.h" -#include "device.h" -#include "netcfg.h" -#include "netutil.h" -#include "errors.h" -#include "eventreg.h" -#include "wlanconfig.h" -/*! - \cond DOXYGEN_IGNORE -*/ - /* In case of use dynamic event registration - * redirect the event to the internal mechanism */ -#if (defined(SL_RUNTIME_EVENT_REGISTERATION)) - -#define _SlDrvHandleFatalErrorEvents _SlDeviceFatalErrorEvtHdlr -#define _SlDrvHandleGeneralEvents _SlDeviceGeneralEvtHdlr -#define _SlDrvHandleWlanEvents _SlWlanEvtHdlr -#define _SlDrvHandleNetAppEvents _SlNetAppEvtHdlr -#define _SlDrvHandleSockEvents _SlSockEvtHdlr -#define _SlDrvHandleHttpServerEvents _SlNetAppHttpServerHdlr -#define _SlDrvHandleNetAppRequestEvents _SlNetAppRequestHdlr -#define _SlDrvHandleNetAppRequestMemFreeEvents _SlNetAppRequestMemFree -#define _SlDrvHandleSocketTriggerEvents _SlSocketTriggerEventHandler - -#else - - /* The fatal error events dispatcher which is - * initialized to the user handler */ -#ifdef slcb_DeviceFatalErrorEvtHdlr -#define _SlDrvHandleFatalErrorEvents slcb_DeviceFatalErrorEvtHdlr -#endif - - /* The general events dispatcher which is - * initialized to the user handler */ -#ifdef slcb_DeviceGeneralEvtHdlr -#define _SlDrvHandleGeneralEvents slcb_DeviceGeneralEvtHdlr -#endif - - /* The wlan events dispatcher which is - * initialized to the user handler */ -#ifdef slcb_WlanEvtHdlr -#define _SlDrvHandleWlanEvents slcb_WlanEvtHdlr -#endif - - /* The NetApp events dispatcher which is - * initialized to the user handler */ -#ifdef slcb_NetAppEvtHdlr -#define _SlDrvHandleNetAppEvents slcb_NetAppEvtHdlr -#endif - - /* The http server events dispatcher which is - * initialized to the user handler if exists */ -#ifdef slcb_NetAppHttpServerHdlr -#define _SlDrvHandleHttpServerEvents slcb_NetAppHttpServerHdlr -#endif - - /* The socket events dispatcher which is - * initialized to the user handler */ -#ifdef slcb_SockEvtHdlr -#define _SlDrvHandleSockEvents slcb_SockEvtHdlr -#endif - - -/* The netapp requests dispatcher which is - * initialized to the user handler if exists */ -#ifdef slcb_NetAppRequestHdlr -#define _SlDrvHandleNetAppRequestEvents slcb_NetAppRequestHdlr -#endif - -/* The netapp request mem free requests dispatcher which is -* initialized to the user handler if exists */ -#ifdef slcb_NetAppRequestMemFree -#define _SlDrvHandleNetAppRequestMemFreeEvents slcb_NetAppRequestMemFree -#endif - -/* The netapp requests dispatcher which is -* initialized to the user handler if exists */ -#ifdef slcb_SocketTriggerEventHandler -#define _SlDrvHandleSocketTriggerEvents slcb_SocketTriggerEventHandler -#endif - - -#endif - -#define SL_CONCAT(x,y) x ## y -#define SL_CONCAT2(x,y) SL_CONCAT(x,y) - - -#if (!defined(SL_RUNTIME_EVENT_REGISTERATION)) - -/* - * The section below handles the external lib event registration - * according to the desired events it specified in its API header file. - * The external lib should be first installed by the user (see user.h) - */ -#ifdef SL_EXT_LIB_1 - -/* General Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_GENERAL_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _GeneralEventHdl) (SlDeviceEvent_t *); - #define SlExtLib1GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_1, _GeneralEventHdl) - - #undef EXT_LIB_REGISTERED_GENERAL_EVENTS - #define EXT_LIB_REGISTERED_GENERAL_EVENTS - #endif - - /* Wlan Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_WLAN_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _WlanEventHdl) (SlWlanEvent_t *); - #define SlExtLib1WlanEventHandler SL_CONCAT2(SL_EXT_LIB_1, _WlanEventHdl) - - #undef EXT_LIB_REGISTERED_WLAN_EVENTS - #define EXT_LIB_REGISTERED_WLAN_EVENTS - #endif - - /* NetApp Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_NETAPP_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _NetAppEventHdl) (SlNetAppEvent_t *); - #define SlExtLib1NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_1, _NetAppEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_EVENTS - #endif - - /* Http Server Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_HTTP_SERVER_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); - #define SlExtLib1HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_1, _HttpServerEventHdl) - - #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #endif - - /* Socket Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_SOCK_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _SockEventHdl) (SlSockEvent_t *); - #define SlExtLib1SockEventHandler SL_CONCAT2(SL_EXT_LIB_1, _SockEventHdl) - - #undef EXT_LIB_REGISTERED_SOCK_EVENTS - #define EXT_LIB_REGISTERED_SOCK_EVENTS - #endif - - /* Fatal Error Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_FATAL_ERROR_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _FatalErrorEventHdl) (SlDeviceEvent_t *); - #define SlExtLib1FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_1, _FatalErrorEventHdl) - - #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #endif - - /* NetApp requests events registration */ - #if SL_CONCAT2(SL_EXT_LIB_1, _NOTIFY_NETAPP_REQUEST_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_1, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); - #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_1, _NetAppRequestEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #endif - -#endif - - -#ifdef SL_EXT_LIB_2 - - /* General Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_GENERAL_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _GeneralEventHdl) (SlDeviceEvent_t *); - #define SlExtLib2GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_2, _GeneralEventHdl) - - #undef EXT_LIB_REGISTERED_GENERAL_EVENTS - #define EXT_LIB_REGISTERED_GENERAL_EVENTS - #endif - - /* Wlan Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_WLAN_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _WlanEventHdl) (SlWlanEvent_t *); - #define SlExtLib2WlanEventHandler SL_CONCAT2(SL_EXT_LIB_2, _WlanEventHdl) - - #undef EXT_LIB_REGISTERED_WLAN_EVENTS - #define EXT_LIB_REGISTERED_WLAN_EVENTS - #endif - - /* NetApp Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_NETAPP_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _NetAppEventHdl) (SlNetAppEvent_t *); - #define SlExtLib2NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_2, _NetAppEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_EVENTS - #endif - - /* Http Server Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_HTTP_SERVER_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); - #define SlExtLib2HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_2, _HttpServerEventHdl) - - #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #endif - - /* Socket Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_SOCK_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _SockEventHdl) (SlSockEvent_t *); - #define SlExtLib2SockEventHandler SL_CONCAT2(SL_EXT_LIB_2, _SockEventHdl) - - #undef EXT_LIB_REGISTERED_SOCK_EVENTS - #define EXT_LIB_REGISTERED_SOCK_EVENTS - #endif - - /* Fatal Error Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_FATAL_ERROR_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _FatalErrorEventHdl) (SlDeviceEvent_t *); - #define SlExtLib2FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_2, _FatalErrorEventHdl) - - #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #endif - - /* NetApp requests events registration */ - #if SL_CONCAT2(SL_EXT_LIB_2, _NOTIFY_NETAPP_REQUEST_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_2, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); - #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_2, _NetAppRequestEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #endif - -#endif - -#ifdef SL_EXT_LIB_3 - - /* General Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_GENERAL_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _GeneralEventHdl) (SlDeviceEvent_t *); - #define SlExtLib3GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_3, _GeneralEventHdl) - - #undef EXT_LIB_REGISTERED_GENERAL_EVENTS - #define EXT_LIB_REGISTERED_GENERAL_EVENTS - #endif - - /* Wlan Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_WLAN_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _WlanEventHdl) (SlWlanEvent_t *); - #define SlExtLib3WlanEventHandler SL_CONCAT2(SL_EXT_LIB_3, _WlanEventHdl) - - #undef EXT_LIB_REGISTERED_WLAN_EVENTS - #define EXT_LIB_REGISTERED_WLAN_EVENTS - #endif - - /* NetApp Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_NETAPP_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _NetAppEventHdl) (SlNetAppEvent_t *); - #define SlExtLib3NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_3, _NetAppEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_EVENTS - #endif - - /* Http Server Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_HTTP_SERVER_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); - #define SlExtLib3HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_3, _HttpServerEventHdl) - - #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #endif - - /* Socket Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_SOCK_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _SockEventHdl) (SlSockEvent_t *); - #define SlExtLib3SockEventHandler SL_CONCAT2(SL_EXT_LIB_3, _SockEventHdl) - - #undef EXT_LIB_REGISTERED_SOCK_EVENTS - #define EXT_LIB_REGISTERED_SOCK_EVENTS - #endif - - - /* Fatal Error Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_FATAL_ERROR_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _FatalErrorEventHdl) (SlDeviceEvent_t *); - #define SlExtLib3FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_3, _FatalErrorEventHdl) - - #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #endif - - /* NetApp requests events registration */ - #if SL_CONCAT2(SL_EXT_LIB_3, _NOTIFY_NETAPP_REQUEST_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_3, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); - #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_3, _NetAppRequestEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #endif - -#endif - -#ifdef SL_EXT_LIB_4 - - /* General Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_GENERAL_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _GeneralEventHdl) (SlDeviceEvent_t *); - #define SlExtLib4GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_4, _GeneralEventHdl) - - #undef EXT_LIB_REGISTERED_GENERAL_EVENTS - #define EXT_LIB_REGISTERED_GENERAL_EVENTS - #endif - - /* Wlan Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_WLAN_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _WlanEventHdl) (SlWlanEvent_t *); - #define SlExtLib4WlanEventHandler SL_CONCAT2(SL_EXT_LIB_4, _WlanEventHdl) - - #undef EXT_LIB_REGISTERED_WLAN_EVENTS - #define EXT_LIB_REGISTERED_WLAN_EVENTS - #endif - - /* NetApp Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_NETAPP_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _NetAppEventHdl) (SlNetAppEvent_t *); - #define SlExtLib4NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_4, _NetAppEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_EVENTS - #endif - - /* Http Server Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_HTTP_SERVER_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); - #define SlExtLib4HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_4, _HttpServerEventHdl) - - #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #endif - - /* Socket Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_SOCK_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _SockEventHdl) (SlSockEvent_t *); - #define SlExtLib4SockEventHandler SL_CONCAT2(SL_EXT_LIB_4, _SockEventHdl) - - #undef EXT_LIB_REGISTERED_SOCK_EVENTS - #define EXT_LIB_REGISTERED_SOCK_EVENTS - #endif - - /* Fatal Error Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_FATAL_ERROR_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _FatalErrorEventHdl) (SlDeviceEvent_t *); - #define SlExtLib4FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_4, _FatalErrorEventHdl) - - #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #endif - - /* NetApp requests events registration */ - #if SL_CONCAT2(SL_EXT_LIB_4, _NOTIFY_NETAPP_REQUEST_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_4, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); - #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_4, _NetAppRequestEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #endif - -#endif - -#ifdef SL_EXT_LIB_5 - - /* General Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_GENERAL_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _GeneralEventHdl) (SlDeviceEvent_t *); - #define SlExtLib5GeneralEventHandler SL_CONCAT2(SL_EXT_LIB_5, _GeneralEventHdl) - - #undef EXT_LIB_REGISTERED_GENERAL_EVENTS - #define EXT_LIB_REGISTERED_GENERAL_EVENTS - #endif - - /* Wlan Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_WLAN_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _WlanEventHdl) (SlWlanEvent_t *); - #define SlExtLib5WlanEventHandler SL_CONCAT2(SL_EXT_LIB_5, _WlanEventHdl) - - #undef EXT_LIB_REGISTERED_WLAN_EVENTS - #define EXT_LIB_REGISTERED_WLAN_EVENTS - #endif - - /* NetApp Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_NETAPP_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _NetAppEventHdl) (SlNetAppEvent_t *); - #define SlExtLib5NetAppEventHandler SL_CONCAT2(SL_EXT_LIB_5, _NetAppEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_EVENTS - #endif - - /* Http Server Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_HTTP_SERVER_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _HttpServerEventHdl) (SlNetAppHttpServerEvent_t* , SlNetAppHttpServerResponse_t*); - #define SlExtLib5HttpServerEventHandler SL_CONCAT2(SL_EXT_LIB_5, _HttpServerEventHdl) - - #undef EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #define EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS - #endif - - /* Socket Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_SOCK_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _SockEventHdl) (SlSockEvent_t *); - #define SlExtLib5SockEventHandler SL_CONCAT2(SL_EXT_LIB_5, _SockEventHdl) - - #undef EXT_LIB_REGISTERED_SOCK_EVENTS - #define EXT_LIB_REGISTERED_SOCK_EVENTS - #endif - - /* Fatal Error Event Registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_FATAL_ERROR_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _FatalErrorEventHdl) (SlDeviceEvent_t *); - #define SlExtLib5FatalErrorEventHandler SL_CONCAT2(SL_EXT_LIB_5, _FatalErrorEventHdl) - - #undef EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #define EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS - #endif - - /* NetApp requests events registration */ - #if SL_CONCAT2(SL_EXT_LIB_5, _NOTIFY_NETAPP_REQUEST_EVENT) - extern _SlEventPropogationStatus_e SL_CONCAT2(SL_EXT_LIB_5, _NetAppRequestEventHdl) (SlNetAppRequest_t*, SlNetAppResponse_t *); - #define SlExtLib1NetAppRequestEventHandler SL_CONCAT2(SL_EXT_LIB_5, _NetAppRequestEventHdl) - - #undef EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #define EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS - #endif - -#endif - -#if defined(EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS) -extern void _SlDrvHandleFatalErrorEvents(SlDeviceEvent_t *slFatalErrorEvent); -#endif - -#if defined(EXT_LIB_REGISTERED_GENERAL_EVENTS) -extern void _SlDrvHandleGeneralEvents(SlDeviceEvent_t *slGeneralEvent); -#endif - -#if defined(EXT_LIB_REGISTERED_WLAN_EVENTS) -extern void _SlDrvHandleWlanEvents(SlWlanEvent_t *slWlanEvent); -#endif - -#if defined (EXT_LIB_REGISTERED_NETAPP_EVENTS) -extern void _SlDrvHandleNetAppEvents(SlNetAppEvent_t *slNetAppEvent); -#endif - -#if defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) -extern void _SlDrvHandleHttpServerEvents(SlNetAppHttpServerEvent_t *slHttpServerEvent, SlNetAppHttpServerResponse_t *slHttpServerResponse); -#endif - -#if defined(EXT_LIB_REGISTERED_SOCK_EVENTS) -extern void _SlDrvHandleSockEvents(SlSockEvent_t *slSockEvent); -#endif - -#if defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) -extern void _SlDrvHandleNetAppRequestEvents(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); -#endif - -#endif //#if (defined(SL_RUNTIME_EVENT_REGISTERATION)) - -typedef _SlReturnVal_t (*_SlSpawnEntryFunc_t)(void* pValue); - -#define SL_SPAWN_FLAG_FROM_SL_IRQ_HANDLER (0x1) -#define SL_SPAWN_FLAG_FROM_CMD_CTX (0x2) -#define SL_SPAWN_FLAG_FROM_CMD_PROCESS (0x3) - -#ifdef SL_PLATFORM_MULTI_THREADED - #include "source/spawn.h" -#else - #include "source/nonos.h" -#endif - -/*! - \endcond -*/ - - -/* Async functions description*/ - - -/*! - \brief Fatal Error event for inspecting fatal error - - \param[out] pSlFatalErrorEvent pointer to SlDeviceFatal_t - \return None - \sa - \note - \warning - \par Example - \code - For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_DEVICE_ABORT - Indicates a severe error occured and the device stopped - Use pSlDeviceFatal->Data.DeviceAssert fields - - Code: An idication of the abort type - - Value: The abort data - - - For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_NO_CMD_ACK - Indicates that the command sent to the device had no ack - Use pSlDeviceFatal->Data.NoCmdAck fields - - Code: An idication of the cmd opcode - - For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT - Indicates that the command got a timeout while waiting for its async response - Use pSlDeviceFatal->Data.CmdTimeout fields - - Code: An idication of the asyncevent opcode - - - For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_DRIVER_ABORT - Indicates a severe error occured in the driver - Use pSlDeviceFatal->Data.DeviceAssert fields - - None. - - For pSlDeviceFatal->Id = SL_DEVICE_EVENT_FATAL_SYNC_LOSS - Indicates a sync loss with the device - Use pSlDeviceFatal->Data.DeviceAssert fields - - None. - \endcode - \code - Example for fatal error - printf(Abort type =%d Abort Data=0x%x\n\n", - pSlDeviceFatal->Data.deviceReport.AbortType, - pSlDeviceFatal->Data.deviceReport.AbortData); - \endcode -*/ -#if (defined(slcb_DeviceFatalErrorEvtHdlr)) -extern void slcb_DeviceFatalErrorEvtHdlr(SlDeviceFatal_t *pSlFatalErrorEvent); -#endif - - -/*! - \brief General async event for inspecting general events - - \param[out] pSlDeviceEvent pointer to SlDeviceEvent_t - \return None - \sa - \note - \warning - \par Example - \code - For pSlDeviceEvent->Id = SL_DEVICE_EVENT_RESET_REQUEST - Use pSlDeviceEvent->Data.ResetRequest fields - - Status: An error code indication from the device - - Source: The sender originator which is based on SlDeviceSource_e enum - - For pSlDeviceEvent->Id = SL_DEVICE_EVENT_ERROR - Use pSlDeviceEvent->Data.Error fields - - Code: An error code indication from the device - - Source: The sender originator which is based on SlErrorSender_e enum - \endcode - \code - Example for error event: - printf(General Event Handler - ID=%d Sender=%d\n\n", - pSlDeviceEvent->Data.Error.Code, // the error code - pSlDeviceEvent->Data.Error.Source); // the error source - \endcode - -*/ -#if (defined(slcb_DeviceGeneralEvtHdlr)) -extern void slcb_DeviceGeneralEvtHdlr(SlDeviceEvent_t *pSlDeviceEvent); -#endif - -/*! - \brief WLAN Async event handler - - \param[out] pSlWlanEvent pointer to SlWlanEvent_t data - \return None - \sa - \note - \warning - \par Example - \code - For pSlWlanEvent->Id = SL_WLAN_EVENT_CONNECT, STA connection indication event - Use pSlWlanEvent->Data.Connect main fields - - SsidLen - - SsidName - - Bssid - - For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_CONNECT, P2P client connection indication event - Use pSlWlanEvent->Data.P2PConnect main fields - - SsidLen - - SsidName - - Bssid - - GoDeviceNameLen - - GoDeviceName - - For pSlWlanEvent->Id = SL_WLAN_EVENT_DISCONNECT, STA client disconnection event - Use pSlWlanEvent->Data.Disconnect main fields: - - SsidLen - - SsidName - - Bssid - - ReasonCode - - For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_DISCONNECT, P2P client disconnection event - Use pSlWlanEvent->Data.P2PDisconnect main fields: - - SsidLen - - SsidName - - Bssid - - ReasonCode - - GoDeviceNameLen - - GoDeviceName - - For pSlWlanEvent->Id = SL_WLAN_EVENT_STA_ADDED, AP connected STA - Use pSlWlanEvent->Data.STAAdded fields: - - Mac - - For pSlWlanEvent->Id = SL_WLAN_EVENT_STA_REMOVED, AP disconnected STA - Use pSlWlanEvent->Data.STARemoved fields: - - Mac - - For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_CLIENT_ADDED, P2P(Go) connected P2P(Client) - Use pSlWlanEvent->Data.P2PClientAdded fields: - - Mac - - GoDeviceNameLen - - GoDeviceName - - OwnSsidLen - - OwnSsid - - For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_CLIENT_REMOVED, P2P(Go) disconnected P2P(Client) - Use pSlWlanEvent->Data.P2PClientRemoved fields: - - Mac - - GoDeviceNameLen - - GoDeviceName - - OwnSsidLen - - OwnSsid - - For pSlWlanEvent->Id = SL_WLAN_P2P_DEV_FOUND_EVENT - Use pSlWlanEvent->Data.P2PDevFound fields: - - GoDeviceNameLen - - GoDeviceName - - Mac - - WpsMethod - - For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_REQUEST - Use pSlWlanEvent->Data.P2PRequest fields - - GoDeviceNameLen - - GoDeviceName - - Mac - - WpsMethod - - For pSlWlanEvent->Id = SL_WLAN_EVENT_P2P_CONNECTFAIL, P2P only - Use pSlWlanEvent->Data.P2PConnectFail fields: - - Status - - For pSlWlanEvent->Id = SL_WLAN_EVENT_PROVISIONING_STATUS - Use pSlWlanEvent->Data.ProvisioningStatus fields - - Status - - For pSlWlanEvent->Id = SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED - Use pSlWlanEvent->Data.ProvisioningProfileAdded fields: - - Status - - SsidLen - - Ssid - - Reserved - For pSlWlanEvent->Id = SL_WLAN_EVENT_LINK_QUALITY_TRIGGER - Use pSlWlanEvent->Data.LinkQualityTrigger fields: - - Data - - TriggerId - - \endcode -*/ -#if (defined(slcb_WlanEvtHdlr)) -extern void slcb_WlanEvtHdlr(SlWlanEvent_t* pSlWlanEvent); -#endif - - -/*! - \brief NETAPP Async event handler - - \param[out] pSlNetAppEvent pointer to SlNetAppEvent_t data - \return None - \sa - \note - \warning - \par Example - \code - For pSlNetAppEvent->Id = SL_NETAPP_EVENT_IPV4_ACQUIRED/SL_NETAPP_EVENT_IPV6_ACQUIRED - Use pSlNetAppEvent->Data.ipAcquiredV4 (V6) fields - - ip - - gateway - - dns - - For pSlNetAppEvent->Id = SL_NETAPP_IP_LEASED_EVENT, AP or P2P go dhcp lease event - Use pSlNetAppEvent->Data.ipLeased fields - - ip_address - - lease_time - - mac - - For pSlNetApp->Id = SL_NETAPP_IP_RELEASED_EVENT, AP or P2P go dhcp ip release event - Use pSlNetAppEvent->Data.ipReleased fields - - ip_address - - mac - - reason - \endcode -*/ -#if (defined(slcb_NetAppEvtHdlr)) -extern void slcb_NetAppEvtHdlr(SlNetAppEvent_t* pSlNetAppEvent); -#endif - -/*! - \brief Socket Async event handler - - \param[out] pSlSockEvent pointer to SlSockEvent_t data - \return None - \sa - \note - \warning - \par Example - \code - For pSlSockEvent->Event = SL_SOCKET_TX_FAILED_EVENT - Use pSlSockEvent->SockTxFailData fields - - sd - - status - For pSlSockEvent->Event = SL_SOCKET_ASYNC_EVENT - Use pSlSockEvent->SockAsyncData fields - - sd - - type - - SL_SSL_ACCEPT - - SL_WLAN_RX_FRAGMENTATION_TOO_BIG - - SL_OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED - - val - \endcode - -*/ -#if (defined(slcb_SockEvtHdlr)) -extern void slcb_SockEvtHdlr(SlSockEvent_t* pSlSockEvent); -#endif - -/*! - \brief HTTP server async event - - \param[out] pSlHttpServerEvent Pointer to SlNetAppHttpServerEvent_t - \param[in] pSlHttpServerResponse Pointer to SlNetAppHttpServerResponse_t - - \return None - \sa slcb_NetAppRequestHdlr - \note - \warning - \par Example - \code - For pSlHttpServerResponse->Event = SL_NETAPP_HTTPGETTOKENVALUE_EVENT - Use pSlHttpServerEvent->EventData fields - - httpTokenName - - data - - len - And pSlHttpServerResponse->ResponseData fields - - data - - len - - For pSlHttpServerEvent->Event = SL_NETAPP_HTTPPOSTTOKENVALUE_EVENT - Use pSlHttpServerEvent->EventData.httpPostData fields - - action - - token_name - - token_value - And pSlHttpServerResponse->ResponseData fields: - - data - - len - \endcode -*/ -#if (defined(slcb_NetAppHttpServerHdlr)) -extern void slcb_NetAppHttpServerHdlr(SlNetAppHttpServerEvent_t *pSlHttpServerEvent, SlNetAppHttpServerResponse_t *pSlHttpServerResponse); -#endif - -/*! - \brief General netapp async event - - \param[out] pNetAppRequest Pointer to SlNetAppRequest_t - \param[in] pNetAppResponse Pointer to SlNetAppResponse_t - - \return None - \sa slcb_NetAppHttpServerHdlr - \note - \warning - \par Example - \code - TBD - \endcode -*/ -#if (defined(slcb_NetAppRequestHdlr)) -extern void slcb_NetAppRequestHdlr(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse); -#endif - -/*! - \brief A handler for freeing the memory of the NetApp response. - - \param[in,out] buffer Pointer to the buffer to free - - \return None - \sa - \note - \warning - \par Example - \code - TBD - \endcode -*/ -#if (defined(slcb_NetAppRequestMemFree)) -extern void slcb_NetAppRequestMemFree (_u8 *buffer); -#endif - -/*! - \brief Get the timer counter value (timestamp).\n - The timer must count from zero to its MAX value. - For non-os application, this routine must be implemented. - \param None - \return Returns 32-bit timer counter value (ticks unit) - \sa - \note - \note belongs to \ref porting_sec - \warning -*/ -#if defined (slcb_GetTimestamp) -extern _u32 slcb_GetTimestamp(void); -#endif - - -/*! - \brief Socket trigger routine. - This routine will notify the application that a netwrok activity has - been completed on the required socket/s. - - \param[out] pSlSockTriggerEvent pointer to SlSockTriggerEvent_t data - \return None. - \sa - \note - \note belongs to \ref porting_sec - \warning -*/ -#if (defined(slcb_SocketTriggerEventHandler)) -extern void slcb_SocketTriggerEventHandler(SlSockTriggerEvent_t* pSlSockTriggerEvent); -#endif - - -/*! - Close the Doxygen group. - @} - - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __SIMPLELINK_H__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/sl_socket.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/sl_socket.h deleted file mode 100644 index 4aa0d5c198e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/sl_socket.h +++ /dev/null @@ -1,1619 +0,0 @@ -/* - * sl_socket.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -#ifndef __SL_SOCKET_H__ -#define __SL_SOCKET_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup Socket - \short Controls standard client/server sockets programming options and capabilities - -*/ -/*! - - \addtogroup Socket - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -#undef SL_FD_SETSIZE -#define SL_FD_SETSIZE SL_MAX_SOCKETS /* Number of sockets to select on - same is max sockets! */ -#define SL_BSD_SOCKET_ID_MASK (0x1F) /* Index using the LBS 4 bits for socket id 0-7 */ - -/* Define some BSD protocol constants. */ -#define SL_SOCK_STREAM (1) /* TCP Socket */ -#define SL_SOCK_DGRAM (2) /* UDP Socket */ -#define SL_SOCK_RAW (3) /* Raw socket */ -#define SL_SOCK_RX_MTR (4) /* Used for traffic RX metrics */ -#define SL_IPPROTO_TCP (6) /* TCP Raw Socket */ -#define SL_IPPROTO_UDP (17) /* UDP Raw Socket */ -#define SL_IPPROTO_RAW (255) /* Raw Socket */ -#define SL_SEC_SOCKET (100) /* Secured Socket Layer (SSL,TLS) */ - -/* Address families. */ -#define SL_AF_INET (2) /* IPv4 socket (UDP, TCP, etc) */ -#define SL_AF_INET6 (3) /* IPv6 socket (UDP, TCP, etc) */ -#define SL_AF_RF (6) /* data include RF parameter, All layer by user (Wifi could be disconnected) */ -#define SL_AF_PACKET (17) -/* Protocol families, same as address families. */ -#define SL_PF_INET AF_INET -#define SL_PF_INET6 AF_INET6 -#define SL_INADDR_ANY (0) /* bind any address */ -#define SL_IN6ADDR_ANY (0) - - -/* Max payload size by protocol */ -#define SL_SOCKET_PAYLOAD_TYPE_MASK (0xF0) /*4 bits type, 4 bits sockets id */ -#define SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER (0x80) /* 1536 bytes */ - -/* SL_SOCKET_EVENT_CLASS_BSD user events */ -#define SL_SOCKET_TX_FAILED_EVENT (1) -#define SL_SOCKET_ASYNC_EVENT (2) - - -/* SL_SOCKET_EVENT_CLASS_BSD user trigger events */ -#define SL_SOCKET_TRIGGER_EVENT_SELECT (1) - -#define SL_SOL_SOCKET (1) /* Define the socket option category. */ -#define SL_IPPROTO_IP (2) /* Define the IP option category. */ -#define SL_SOL_PHY_OPT (3) /* Define the PHY option category. */ - -#define SL_SO_RCVBUF (8) /* Setting TCP receive buffer size */ -#define SL_SO_KEEPALIVE (9) /* Connections are kept alive with periodic messages */ -#define SL_SO_LINGER (13) /* Socket lingers on close pending remaining send/receive packets. */ -#define SL_SO_RCVTIMEO (20) /* Enable receive timeout */ -#define SL_SO_NONBLOCKING (24) /* Enable . disable nonblocking mode */ -#define SL_SO_SECMETHOD (25) /* security metohd */ -#define SL_SO_SECURE_MASK (26) /* security mask */ -#define SL_SO_SECURE_FILES (27) /* security files */ -#define SL_SO_CHANGE_CHANNEL (28) /* This option is available only when transceiver started */ -#define SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME (30) /* This option used to configue secure file */ -#define SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME (31) /* This option used to configue secure file */ -#define SL_SO_SECURE_FILES_CA_FILE_NAME (32) /* This option used to configue secure file */ -#define SL_SO_SECURE_FILES_PEER_CERT_OR_DH_KEY_FILE_NAME (33) /* This option used to configue secure file - in server mode DH params file, and in client mode peer cert for domain verification */ -#define SL_SO_STARTTLS (35) /* initiate STARTTLS on non secure socket */ -#define SL_SO_SSL_CONNECTION_PARAMS (36) /* retrieve by getsockopt the connection params of the current SSL connection in to SlSockSSLConnectionParams_t*/ -#define SL_SO_KEEPALIVETIME (37) /* keepalive time out */ -#define SL_SO_SECURE_DISABLE_CERTIFICATE_STORE (38) /* disable certificate store */ -#define SL_SO_RX_NO_IP_BOUNDARY (39) /* connectionless socket disable rx boundary */ -#define SL_SO_SECURE_ALPN (40) /* set the ALPN bitmap list */ -#define SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP (41) /*set external challange for client certificate */ -#define SL_SO_SECURE_DOMAIN_NAME_VERIFICATION (42) /* set a domain name for verification */ -#define SL_SO_SECURE_ENABLE_OCSP (43) /* enable OCSP and OCSP stapling */ -#define SL_SO_SECURE_ALPN_GENERAL (44) /* set ALPN protocol name by string - only one protocol name can be set */ - -#define SL_IP_MULTICAST_IF (60) /* Specify outgoing multicast interface */ -#define SL_IP_MULTICAST_TTL (61) /* Specify the TTL value to use for outgoing multicast packet. */ -#define SL_IP_ADD_MEMBERSHIP (65) /* Join IPv4 multicast membership */ -#define SL_IP_DROP_MEMBERSHIP (66) /* Leave IPv4 multicast membership */ -#define SL_IP_HDRINCL (67) /* Raw socket IPv4 header included. */ -#define SL_IP_RAW_RX_NO_HEADER (68) /* Proprietary socket option that does not includeIPv4/IPv6 header (and extension headers) on received raw sockets*/ -#define SL_IP_RAW_IPV6_HDRINCL (69) /* Transmitted buffer over IPv6 socket contains IPv6 header. */ -#define SL_IPV6_ADD_MEMBERSHIP (70) /* Join IPv6 multicast membership */ -#define SL_IPV6_DROP_MEMBERSHIP (71) /* Leave IPv6 multicast membership */ -#define SL_IPV6_MULTICAST_HOPS (72) /* Specify the hops value to use for outgoing multicast packet. */ - -#define SL_SO_PHY_RATE (100) /* WLAN Transmit rate */ -#define SL_SO_PHY_TX_POWER (101) /* TX Power level */ -#define SL_SO_PHY_NUM_FRAMES_TO_TX (102) /* Number of frames to transmit */ -#define SL_SO_PHY_PREAMBLE (103) /* Preamble for transmission */ -#define SL_SO_PHY_TX_INHIBIT_THRESHOLD (104) /* TX Inhibit Threshold (CCA) */ -#define SL_SO_PHY_TX_TIMEOUT (105) /* TX timeout for Transceiver frames (lifetime) in miliseconds (max value is 100ms) */ -#define SL_SO_PHY_ALLOW_ACKS (106) /* Enable sending ACKs in transceiver mode */ -#define SL_SO_PHY_RX_BSSID_DATA_FRAMES (107) /* Collect mertics from all data frames in the BSS on the RX metrics socket */ - -typedef enum -{ - SL_TX_INHIBIT_THRESHOLD_MIN = 1, - SL_TX_INHIBIT_THRESHOLD_LOW = 2, - SL_TX_INHIBIT_THRESHOLD_DEFAULT = 3, - SL_TX_INHIBIT_THRESHOLD_MED = 4, - SL_TX_INHIBIT_THRESHOLD_HIGH = 5, - SL_TX_INHIBIT_THRESHOLD_MAX = 6 -} SlTxInhibitThreshold_e; - -#define SL_SO_SEC_METHOD_SSLV3 (0) /* security metohd SSL v3*/ -#define SL_SO_SEC_METHOD_TLSV1 (1) /* security metohd TLS v1*/ -#define SL_SO_SEC_METHOD_TLSV1_1 (2) /* security metohd TLS v1_1*/ -#define SL_SO_SEC_METHOD_TLSV1_2 (3) /* security metohd TLS v1_2*/ -#define SL_SO_SEC_METHOD_SSLv3_TLSV1_2 (4) /* use highest possible version from SSLv3 - TLS 1.2*/ -#define SL_SO_SEC_METHOD_DLSV1 (5) /* security metohd DTL v1 */ - -#define SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA (1 << 0) -#define SL_SEC_MASK_SSL_RSA_WITH_RC4_128_MD5 (1 << 1) -#define SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA (1 << 2) -#define SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_CBC_SHA (1 << 3) -#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA (1 << 4) -#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_RC4_128_SHA (1 << 5) -#define SL_SEC_MASK_TLS_RSA_WITH_AES_128_CBC_SHA256 (1 << 6) -#define SL_SEC_MASK_TLS_RSA_WITH_AES_256_CBC_SHA256 (1 << 7) -#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (1 << 8) -#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (1 << 9) -#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA (1 << 10) -#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA (1 << 11) -#define SL_SEC_MASK_TLS_RSA_WITH_AES_128_GCM_SHA256 (1 << 12) -#define SL_SEC_MASK_TLS_RSA_WITH_AES_256_GCM_SHA384 (1 << 13) -#define SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 (1 << 14) -#define SL_SEC_MASK_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 (1 << 15) -#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (1 << 16) -#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (1 << 17) -#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (1 << 18) -#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 (1 << 19) -#define SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 20) -#define SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 21) -#define SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 22) - -#define SL_SEC_MASK_SECURE_DEFAULT ((SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 << 1) - 1) - -#define SL_SECURE_ALPN_H1 (1 << 0) -#define SL_SECURE_ALPN_H2 (1 << 1) -#define SL_SECURE_ALPN_H2C (1 << 2) -#define SL_SECURE_ALPN_H2_14 (1 << 3) -#define SL_SECURE_ALPN_H2_16 (1 << 4) -#define SL_SECURE_ALPN_FULL_LIST ((SL_SECURE_ALPN_H2_16 << 1 ) - 1) - -#define SL_MSG_DONTWAIT (0x00000008) /* Nonblocking IO */ - -/* AP DHCP Server - IP Release reason code */ -#define SL_IP_LEASE_PEER_RELEASE (0) -#define SL_IP_LEASE_PEER_DECLINE (1) -#define SL_IP_LEASE_EXPIRED (2) - -/* possible types when receiving SL_SOCKET_ASYNC_EVENT*/ -#define SL_SSL_ACCEPT (0) /* accept failed due to ssl issue ( tcp pass) */ -#define SL_RX_FRAGMENTATION_TOO_BIG (1) /* connection less mode, rx packet fragmentation > 16K, packet is being released */ -#define SL_OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED (2) /* remote side down from secure to unsecure */ -#define SL_SSL_NOTIFICATION_CONNECTED_SECURED (3) /* STARTTLS success */ -#define SL_SSL_NOTIFICATION_HANDSHAKE_FAILED (4) /* STARTTLS handshake faild */ -#define SL_SSL_NOTIFICATION_WRONG_ROOT_CA (5) /* Root CA configured is wrong, the name is in SocketAsyncEvent.EventData.extraInfo */ -#define SL_SOCKET_ASYNC_EVENT_SSL_NOTIFICATION_WRONG_ROOT_CA (5) -#define SL_MAX_ISSUER_AND_SUBJECT_NAME_LEN (16) - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -/* Internet address */ -typedef struct SlInAddr_t -{ -#ifndef s_addr - _u32 s_addr; /* Internet address 32 bits */ -#else - union S_un { - struct { _u8 s_b1,s_b2,s_b3,s_b4; } S_un_b; - struct { _u16 s_w1,s_w2; } S_un_w; - _u32 S_addr; - } S_un; -#endif -}SlInAddr_t; - -/* IpV6 or Ipv6 EUI64 */ -typedef struct SlIn6Addr_t -{ - union - { - _u8 _S6_u8[16]; - _u32 _S6_u32[4]; - } _S6_un; -}SlIn6Addr_t; - - -/* sockopt */ -typedef struct -{ - _u32 KeepaliveEnabled; /* 0 = disabled;1 = enabled; default = 1*/ -}SlSockKeepalive_t; - -typedef struct -{ - _u32 ReuseaddrEnabled; /* 0 = disabled; 1 = enabled; default = 1*/ -}SlSockReuseaddr_t; - -typedef struct -{ - _i32 RxIpNoBoundaryEnabled; /* 0 = keep IP boundary; 1 = don`t keep ip boundary; default = 0; */ -} SlSockRxNoIpBoundary_t; - -typedef struct -{ - _u32 WinSize; /* receive window size for tcp sockets */ -}SlSockWinsize_t; - -typedef struct -{ - _u32 NonBlockingEnabled;/* 0 = disabled;1 = enabled;default = 1*/ -}SlSockNonblocking_t; - -typedef struct -{ - _u8 Sd; - _u8 Type; - _i16 Val; - _i8 pExtraInfo[128]; -} SlSocketAsyncEvent_t; - -typedef struct -{ - _i16 Status; - _u8 Sd; - _u8 Padding; -} SlSockTxFailEventData_t; - - -typedef union -{ - SlSockTxFailEventData_t SockTxFailData; - SlSocketAsyncEvent_t SockAsyncData; -} SlSockEventData_u; - - -typedef struct -{ - _u32 Event; - SlSockEventData_u SocketAsyncEvent; -} SlSockEvent_t; - -typedef struct -{ - _u32 Event; - _u32 EventData; -} SlSockTriggerEvent_t; - - -typedef struct -{ - _u32 SecureALPN; -} SlSockSecureALPN_t; - -typedef struct -{ - _u32 SecureMask; -} SlSockSecureMask_t; - -typedef struct -{ - _u8 SecureMethod; -} SlSockSecureMethod_t; - -typedef struct -{ - _u16 SubjectNameXoredSha1; - _u16 IssuerNameXoredSha1; - _i8 FromDate[8]; - _i8 ToDate[8]; - _i8 SubjectName[SL_MAX_ISSUER_AND_SUBJECT_NAME_LEN]; - _i8 IssuerName[SL_MAX_ISSUER_AND_SUBJECT_NAME_LEN]; - _i8 SubjectNameLen; - _i8 IssuerNameLen; - _i8 Padding[2]; -} SlSockSSLCertInfo_t; - - -typedef struct -{ - _u32 SecureVersion; /* what version of SSL decided in the handshake */ - _u32 SecureCipherSuit; /* what Cipher Index was decided in the handshake */ - _u32 SecureIsPeerValidated; /* was the other peer verified */ - _u32 SecureALPNChosenProtocol; /* bit indicate one of the protocol defined above - SL_SECURE_ALPN_H1 - SL_SECURE_ALPN_H2 - SL_SECURE_ALPN_H2C - SL_SECURE_ALPN_H2_14 - SL_SECURE_ALPN_H2_16 - */ - SlSockSSLCertInfo_t SecurePeerCertinfo; -} SlSockSSLConnectionParams_t; - - -typedef struct -{ - _u16 type; /* holds the type of the info frame, currently only value 1 indicating DATA frame */ - _u16 length; /* holds the length of the info frame recevied */ -}SlRxMetrics_TLV_t; - - -typedef enum -{ - SL_SOCK_TX_RATE_1M = 1, - SL_SOCK_TX_RATE_2M = 2, - SL_SOCK_TX_RATE_5_5M = 3, - SL_SOCK_TX_RATE_11M = 4, - SL_SOCK_TX_RATE_6M = 6, - SL_SOCK_TX_RATE_9M = 7, - SL_SOCK_TX_RATE_12M = 8, - SL_SOCK_TX_RATE_18M = 9, - SL_SOCK_TX_RATE_24M = 10, - SL_SOCK_TX_RATE_36M = 11, - SL_SOCK_TX_RATE_48M = 12, - SL_SOCK_TX_RATE_54M = 13, - SL_SOCK_TX_RATE_MCS_0 = 14, - SL_SOCK_TX_RATE_MCS_1 = 15, - SL_SOCK_TX_RATE_MCS_2 = 16, - SL_SOCK_TX_RATE_MCS_3 = 17, - SL_SOCK_TX_RATE_MCS_4 = 18, - SL_SOCK_TX_RATE_MCS_5 = 19, - SL_SOCK_TX_RATE_MCS_6 = 20, - SL_SOCK_TX_RATE_MCS_7 = 21, - SL_SOCK_TX_MAX_NUM_RATES = 0xFF -}slSockTransceiverTXRateTable_e; - - -typedef enum -{ - SL_SOCK_RX_RATE_1M = 0, - SL_SOCK_RX_RATE_2M = 1, - SL_SOCK_RX_RATE_5_5M = 2, - SL_SOCK_RX_RATE_11M = 3, - SL_SOCK_RX_RATE_6M = 4, - SL_SOCK_RX_RATE_9M = 5, - SL_SOCK_RX_RATE_12M = 6, - SL_SOCK_RX_RATE_18M = 7, - SL_SOCK_RX_RATE_24M = 8, - SL_SOCK_RX_RATE_36M = 9, - SL_SOCK_RX_RATE_48M = 10, - SL_SOCK_RX_RATE_54M = 11, - SL_SOCK_RX_RATE_MCS0 = 12, /* 6.5Mbps */ - SL_SOCK_RX_RATE_MCS1 = 13, /* 13Mbps */ - SL_SOCK_RX_RATE_MCS2 = 14, /* 19.5Mbps */ - SL_SOCK_RX_RATE_MCS3 = 15, /* 26Mbps */ - SL_SOCK_RX_RATE_MCS4 = 16, /* 39Mbps */ - SL_SOCK_RX_RATE_MCS5 = 17, /* 52Mbps */ - SL_SOCK_RX_RATE_MCS6 = 18, /* 58.5Mbps */ - SL_SOCK_RX_RATE_MCS7 = 19, /* 65Mbps */ - SL_SOCK_RX_RATE_MCS7_SGI = 20, /* 65Mbps+10% */ - -}SlSockTransceiverRXRates_e; - -typedef enum -{ - SL_BSD_SECURED_PRIVATE_KEY_IDX = 0, - SL_BSD_SECURED_CERTIFICATE_IDX, - SL_BSD_SECURED_CA_IDX, - SL_BSD_SECURED_DH_IDX -}SlSockSecureSocketFilesIndex_e; - -typedef struct -{ - SlInAddr_t imr_multiaddr; /* The IPv4 multicast address to join */ - SlInAddr_t imr_interface; /* The interface to use for this group */ -}SlSockIpMreq_t; - -typedef struct{ - SlIn6Addr_t ipv6mr_multiaddr; /* IPv6 multicast address of group */ - _u32 ipv6mr_interface; /*should be 0 to choose the default multicast interface*/ -}SlSockIpV6Mreq_t; - -typedef struct -{ - _u32 l_onoff; /* 0 = disabled; 1 = enabled; default = 0;*/ - _u32 l_linger; /* linger time in seconds; default = 0;*/ -}SlSocklinger_t; - -/* sockopt */ -typedef _i32 SlTime_t; -typedef _i32 SlSuseconds_t; - -typedef struct SlTimeval_t -{ - SlTime_t tv_sec; /* Seconds */ - SlSuseconds_t tv_usec; /* Microseconds */ -}SlTimeval_t; - -typedef _u16 SlSocklen_t; - -/* IpV4 socket address */ -typedef struct SlSockAddr_t -{ - _u16 sa_family; /* Address family (e.g. , AF_INET) */ - _u8 sa_data[14]; /* Protocol- specific address information*/ -}SlSockAddr_t; - -typedef struct SlSockAddrIn6_t -{ - _u16 sin6_family; /* AF_INET6 || AF_INET6_EUI_48*/ - _u16 sin6_port; /* Transport layer port. */ - _u32 sin6_flowinfo; /* IPv6 flow information. */ - SlIn6Addr_t sin6_addr; /* IPv6 address. */ - _u32 sin6_scope_id; /* set of interfaces for a scope. */ -}SlSockAddrIn6_t; - -/* Socket address, Internet style. */ - -typedef struct SlSockAddrIn_t -{ - _u16 sin_family; /* Internet Protocol (AF_INET). */ - _u16 sin_port; /* Address port (16 bits). */ - SlInAddr_t sin_addr; /* Internet address (32 bits). */ - _i8 sin_zero[8]; /* Not used. */ -}SlSockAddrIn_t; - -typedef struct -{ - _u8 SecureFiles[4]; -}SlSockSecureFiles_t; - -typedef struct SlFdSet_t /* The select socket array manager */ -{ - _u32 fd_array[(SL_FD_SETSIZE + (_u8)31)/(_u8)32]; /* Bit map of SOCKET Descriptors */ -} SlFdSet_t; - -typedef struct -{ - _u8 Rate; /* Received Rate, refer to slSockTransceiverRXRateTable_e */ - _u8 Channel; /* The received channel*/ - _i8 Rssi; /* The computed RSSI value in db of current frame */ - _u8 Padding; /* pad to align to 32 bits */ - _u32 Timestamp; /* Timestamp in microseconds */ -}SlTransceiverRxOverHead_t; - -typedef struct -{ - _u32 enableDisable; /* 1 to enable collecting metrics from BSS, 0 - collecting metrics from AP only. (0 is the default state) */ -}SlRxMetricsEnableDisableRXOnBSS_t; - - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - - \brief Create an endpoint for communication - - The socket function creates a new socket of a certain socket type, identified - by an integer number, and allocates system resources to it.\n - This function is called by the application layer to obtain a socket handle. - - \param[in] Domain Specifies the protocol family of the created socket. - For example: - - SL_AF_INET for network protocol IPv4 - - SL_AF_INET6 for network protocol IPv6 - - SL_AF_RF for starting transceiver mode. Notes: - - sending and receiving any packet overriding 802.11 header - - for optimized power consumption the socket will be started in TX - only mode until receive command is activated - - \param[in] Type specifies the communication semantic, one of: - - SL_SOCK_STREAM (reliable stream-oriented service or Stream Sockets) - - SL_SOCK_DGRAM (datagram service or Datagram Sockets) - - SL_SOCK_RAW (raw protocols atop the network layer) - - when used with AF_RF: - - SL_SOCK_DGRAM - L2 socket - - SL_SOCK_RAW - L1 socket - bypass WLAN CCA (Clear Channel Assessment) - The Protocol parameter is used to set the channel number. - Within this parameter, low power low rate flag can be set by using the macro SL_WLAN_RAW_RF_SOCKET_CHANNEL. - i.e sl_Socket(SL_AF_RF, SL_SOCK_RAW, SL_WLAN_RAW_RF_SOCKET_CHANNEL(36, TRANSCEIVER_5G_LOW_POWER_LOW_RATE)); - - SL_SOCK_RX_MTR - opening socket to receive information frames with the following format in STA and P2P client only. - | SlRxMetrics_TLV_t | SlTransceiverRxOverHead_t | WLAN header (24 / 26 bytes depending on QOS) payload | - collecting WLAN headers and RX metrics between the device and the AP. - if used with the setsockopt - SL_SO_PHY_RX_BSSID_DATA_FRAMES, the device start collecting - WLAN headers of other devices in the BSS - - \param[in] Protocol specifies a particular transport to be used with - the socket. \n - The most common are - - SL_IPPROTO_TCP - - SL_IPPROTO_UDP - The value 0 may be used to select a default - protocol from the selected domain and type - - \return On success, socket handle that is used for consequent socket operations. \n - A successful return code should be a positive number (int16)\n - On error, a negative (int16) value will be returned specifying the error code. - - SL_EAFNOSUPPORT - illegal domain parameter - - SL_EPROTOTYPE - illegal type parameter - - SL_EACCES - permission denied - - SL_ENSOCK - exceeded maximal number of socket - - SL_ENOMEM - memory allocation error - - SL_EINVAL - error in socket configuration - - SL_EPROTONOSUPPORT - illegal protocol parameter - - SL_EOPNOTSUPP - illegal combination of protocol and type parameters - - \sa sl_Close - \note belongs to \ref basic_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Socket) -_i16 sl_Socket(_i16 Domain, _i16 Type, _i16 Protocol); -#endif - -/*! - \brief Gracefully close socket - - This function causes the system to release resources allocated to a socket. \n - In case of TCP, the connection is terminated. - - \param[in] sd Socket handle (received in sl_Socket) - - \return Zero on success, or negative error code on failure - - \sa sl_Socket - \note belongs to \ref ext_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Close) -_i16 sl_Close(_i16 sd); -#endif - -/*! - \brief Accept a connection on a socket - - This function is used with connection-based socket types (SOCK_STREAM).\n - It extracts the first connection request on the queue of pending - connections, creates a new connected socket, and returns a new file - descriptor referring to that socket.\n - The newly created socket is not in the listening state. The - original socket sd is unaffected by this call. \n - The argument sd is a socket that has been created with - sl_Socket(), bound to a local address with sl_Bind(), and is - listening for connections after a sl_Listen(). The argument \b - \e addr is a pointer to a sockaddr structure. This structure - is filled in with the address of the peer socket, as known to - the communications layer. The exact format of the address - returned addr is determined by the socket's address family. \n - The \b \e addrlen argument is a value-result argument: it - should initially contain the size of the structure pointed to - by addr, on return it will contain the actual length (in - bytes) of the address returned. - - \param[in] sd Socket descriptor (handle) - \param[out] addr The argument addr is a pointer - to a sockaddr structure. This - structure is filled in with the - address of the peer socket, as - known to the communications - layer. The exact format of the - address returned addr is - determined by the socket's - address\n - sockaddr:\n - code for the - address format. On this version - only AF_INET is supported.\n - - socket address, the length - depends on the code format - \param[out] addrlen The addrlen argument is a value-result - argument: it should initially contain the - size of the structure pointed to by addr - - \return On success, a socket handle.\n - On a non-blocking accept a possible negative value is SL_EAGAIN.\n - On failure, negative error code.\n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa sl_Socket sl_Bind sl_Listen - \note Belongs to \ref server_side - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Accept) -_i16 sl_Accept(_i16 sd, SlSockAddr_t *addr, SlSocklen_t *addrlen); -#endif - -/*! - \brief Assign a name to a socket - - This function gives the socket the local address addr. - addr is addrlen bytes long. Traditionally, this is called - When a socket is created with socket, it exists in a name - space (address family) but has no name assigned. - It is necessary to assign a local address before a SOCK_STREAM - socket may receive connections. - - \param[in] sd Socket descriptor (handle) - \param[in] addr Specifies the destination - addrs\n sockaddr:\n - code for - the address format. On this - version only SL_AF_INET is - supported.\n - socket address, - the length depends on the code - format - \param[in] addrlen Contains the size of the structure pointed to by addr - - \return Zero on success, or negative error code on failure - - \sa sl_Socket sl_Accept sl_Listen - \note belongs to \ref basic_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Bind) -_i16 sl_Bind(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen); -#endif - -/*! - \brief Listen for connections on a socket - - The willingness to accept incoming connections and a queue - limit for incoming connections are specified with listen(), - and then the connections are accepted with accept. - The listen() call applies only to sockets of type SOCK_STREAM - The backlog parameter defines the maximum length the queue of - pending connections may grow to. - - \param[in] sd Socket descriptor (handle) - \param[in] backlog Specifies the listen queue depth. - - \return Zero on success, or negative error code on failure - - \sa sl_Socket sl_Accept sl_Bind - \note Belongs to \ref server_side - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Listen) -_i16 sl_Listen(_i16 sd, _i16 backlog); -#endif - -/*! - \brief Initiate a connection on a socket - - Function connects the socket referred to by the socket - descriptor sd, to the address specified by addr. The addrlen - argument specifies the size of addr. The format of the - address in addr is determined by the address space of the - socket. If it is of type SOCK_DGRAM, this call specifies the - peer with which the socket is to be associated; this address - is that to which datagrams are to be sent, and the only - address from which datagrams are to be received. If the - socket is of type SOCK_STREAM, this call attempts to make a - connection to another socket. The other socket is specified - by address, which is an address in the communications space - of the socket. - - - \param[in] sd Socket descriptor (handle) - \param[in] addr Specifies the destination addr\n - sockaddr:\n - code for the - address format. On this version - only AF_INET is supported.\n - - socket address, the length - depends on the code format - - \param[in] addrlen Contains the size of the structure pointed - to by addr - - \return On success, a socket handle.\n - On a non-blocking connect a possible negative value is SL_EALREADY. - On failure, negative value.\n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa sl_Socket - \note belongs to \ref client_side - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Connect) -_i16 sl_Connect(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen); -#endif - -/*! - \brief Monitor socket activity - - Select allow a program to monitor multiple file descriptors, - waiting until one or more of the file descriptors become - "ready" for some class of I/O operation. - If trigger mode is enabled the active fdset is the one that was retrieved in the first triggered call. - To enable the trigger mode, an handler must be statically registered as slcb_SocketTriggerEventHandler in user.h - - - \param[in] nfds The highest-numbered file descriptor in any of the - three sets, plus 1. - \param[out] readsds Socket descriptors list for read monitoring and accept monitoring - \param[out] writesds Socket descriptors list for connect monitoring only, write monitoring is not supported - \param[out] exceptsds Socket descriptors list for exception monitoring, not supported. - \param[in] timeout Is an upper bound on the amount of time elapsed - before select() returns. Null or above 0xffff seconds means - infinity timeout. The minimum timeout is 10 milliseconds, - less than 10 milliseconds will be set automatically to 10 milliseconds. - Max microseconds supported is 0xfffc00. - In trigger mode the timout fields must be set to zero. - - \return On success, select() returns the number of - file descriptors contained in the three returned - descriptor sets (that is, the total number of bits that - are set in readfds, writefds, exceptfds) which may be - zero if the timeout expires before anything interesting - happens.\n On error, a negative value is returned. - readsds - return the sockets on which read request will - return without delay with valid data.\n - writesds - return the sockets on which write request - will return without delay.\n - exceptsds - return the sockets closed recently. \n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa sl_Socket - \note If the timeout value set to less than 10ms it will automatically set - to 10ms to prevent overload of the system\n - Belongs to \ref basic_api - - Several threads can call sl_Select at the same time.\b - Calling this API while the same command is called from another thread, may result - in one of the following scenarios: - 1. The command will be executed alongside other select callers (success). - 2. The command will wait (internal) until the previous sl_select finish, and then be executed. - 3. There are not enough resources and SL_POOL_IS_EMPTY error will return. - In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try - again later to issue the command. - - In case all the user sockets are open, sl_Select will exhibit the behavior mentioned in (2) - This is due to the fact sl_select supports multiple callers by utilizing one user socket internally. - User who wish to ensure multiple select calls at any given time, must reserve one socket out of the 16 given. - - \warning - multiple select calls aren't supported when trigger mode is active. The two are mutually exclusive. -*/ -#if _SL_INCLUDE_FUNC(sl_Select) -_i16 sl_Select(_i16 nfds, SlFdSet_t *readsds, SlFdSet_t *writesds, SlFdSet_t *exceptsds, struct SlTimeval_t *timeout); -#endif - - - -/*! - \brief Set socket options- - - This function manipulate the options associated with a socket.\n - Options may exist at multiple protocol levels; they are always - present at the uppermost socket level.\n - - When manipulating socket options the level at which the option resides - and the name of the option must be specified. To manipulate options at - the socket level, level is specified as SOL_SOCKET. To manipulate - options at any other level the protocol number of the appropriate proto- - col controlling the option is supplied. For example, to indicate that an - option is to be interpreted by the TCP protocol, level should be set to - the protocol number of TCP; \n - - The parameters optval and optlen are used to access optval - - ues for setsockopt(). For getsockopt() they identify a - buffer in which the value for the requested option(s) are to - be returned. For getsockopt(), optlen is a value-result - parameter, initially containing the size of the buffer - pointed to by option_value, and modified on return to - indicate the actual size of the value returned. If no option - value is to be supplied or returned, option_value may be - NULL. - - \param[in] sd Socket handle - \param[in] level Defines the protocol level for this option - - SL_SOL_SOCKET Socket level configurations (L4, transport layer) - - SL_IPPROTO_IP IP level configurations (L3, network layer) - - SL_SOL_PHY_OPT Link level configurations (L2, link layer) - \param[in] optname Defines the option name to interrogate - - SL_SOL_SOCKET - - SL_SO_KEEPALIVE \n - Enable/Disable periodic keep alive. - Keeps TCP connections active by enabling the periodic transmission of messages \n - Timeout is 5 minutes.\n - Default: Enabled \n - This options takes SlSockKeepalive_t struct as parameter - - SL_SO_KEEPALIVETIME \n - Set keep alive timeout. - Value is in seconds \n - Default: 5 minutes \n - - SL_SO_RX_NO_IP_BOUNDARY \n - Enable/Disable rx ip boundary. - In connectionless socket (udp/raw), unread data is dropped (when recvfrom len parameter < data size), Enable this option in order to read the left data on the next recvfrom iteration - Default: Disabled, IP boundary kept, \n - This options takes SlSockRxNoIpBoundary_t struct as parameter - - SL_SO_RCVTIMEO \n - Sets the timeout value that specifies the maximum amount of time an input function waits until it completes. \n - Default: No timeout \n - This options takes SlTimeval_t struct as parameter - - SL_SO_RCVBUF \n - Sets tcp max recv window size. \n - This options takes SlSockWinsize_t struct as parameter - - SL_SO_NONBLOCKING \n - Sets socket to non-blocking operation Impacts: connect, accept, send, sendto, recv and recvfrom. \n - Default: Blocking. - This options takes SlSockNonblocking_t struct as parameter - - SL_SO_SECMETHOD \n - Sets method to tcp secured socket (SL_SEC_SOCKET) \n - Default: SL_SO_SEC_METHOD_SSLv3_TLSV1_2 \n - This options takes SlSockSecureMethod_t struct as parameter - - SL_SO_SECURE_MASK \n - Sets specific cipher to tcp secured socket (SL_SEC_SOCKET) \n - Default: "Best" cipher suitable to method \n - This options takes SlSockSecureMask_t struct as parameter - - SL_SO_SECURE_FILES_CA_FILE_NAME \n - Map secured socket to CA file by name \n - This options takes _u8 buffer as parameter - - SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME \n - Map secured socket to private key by name \n - This options takes _u8 buffer as parameter - - SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME \n - Map secured socket to certificate file by name \n - This options takes _u8 buffer as parameter - - SL_SO_SECURE_FILES_DH_KEY_FILE_NAME \n - Map secured socket to Diffie Hellman file by name \n - This options takes _u8 buffer as parameter - - SL_SO_CHANGE_CHANNEL \n - Sets channel in transceiver mode. - This options takes _u32 as channel number parameter - - SL_SO_SECURE_ALPN \n - Sets the ALPN list. the parameter is a bit map consist of or of the following values - - SL_SECURE_ALPN_H1 - SL_SECURE_ALPN_H2 - SL_SECURE_ALPN_H2C - SL_SECURE_ALPN_H2_14 - SL_SECURE_ALPN_H2_16 - SL_SECURE_ALPN_FULL_LIST - Use getsockopt with the SL_SO_SECURE_ALPN to indicate what protocol is picked by the server after - the connection. the bit that stayed set is the one the server picked, if no bit is set, then the server did not pick - any protocol. - - SL_SO_SECURE_ALPN_GENERAL \n - Set one free text protocol name - - can be used alone too add the ALPN extension to the client hello message and also - can be combined with the list of fixed ALPN protocol names if used along with SL_SO_SECURE_ALPN option. - This option is available only in client mode. - Errors that could return from usage of this API- - SL_ERROR_BSD_ESOCKTNOSUPPORT - been used on non tcp socket or server accept socket - SL_ERROR_BSD_ESECNOTALLOWEDWHENLISTENING - cannot be used on listener socket - SL_ERROR_BSD_EINVAL - length of ALPN name must be less than 256 bytes - To retrieve the resault from the server after connection (indicate if this protocol been selected or not), - use getsockopt with this opt ID. - If the SL_SO_SECURE_ALPN is also used, issue a getsockopt with the SL_SO_SECURE_ALPN, to indicate - if the server picked one of the fixed protocol names. - - SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP \n - Set with no parameter to indicate that the client uses external signature using netapp request.\n - needs netapp request handler\n - - SL_SO_SECURE_DOMAIN_NAME_VERIFICATION \n - Set a domain name, to check in ssl client connection. - - SL_SO_SECURE_ENABLE_OCSP \name - Enable OCSP check on a secured client socket - - supports OCSP legacy,stapling and stapling v2. the method is automatically negotiated with the server. - - SL_IPPROTO_IP - - SL_IP_MULTICAST_TTL \n - Set the time-to-live value of outgoing multicast packets for this socket. \n - This options takes _u8 as parameter - - SL_IP_ADD_MEMBERSHIP \n - UDP socket, Join a multicast group. \n - This options takes SlSockIpMreq_t struct as parameter - - SL_IP_DROP_MEMBERSHIP \n - UDP socket, Leave a multicast group \n - This options takes SlSockIpMreq_t struct as parameter - - SL_IP_RAW_RX_NO_HEADER \n - Raw socket remove IP header from received data. \n - Default: data includes ip header \n - This options takes _u32 as parameter - - SL_IP_HDRINCL \n - RAW socket only, the IPv4 layer generates an IP header when sending a packet unless \n - the IP_HDRINCL socket option is enabled on the socket. \n - When it is enabled, the packet must contain an IP header. \n - Default: disabled, IPv4 header generated by Network Stack \n - This options takes _u32 as parameter - - SL_IP_RAW_IPV6_HDRINCL (inactive) \n - RAW socket only, the IPv6 layer generates an IP header when sending a packet unless \n - the IP_HDRINCL socket option is enabled on the socket. When it is enabled, the packet must contain an IP header \n - Default: disabled, IPv4 header generated by Network Stack \n - This options takes _u32 as parameter - - SL_SOL_PHY_OPT - - SL_SO_PHY_RATE \n - RAW socket, set WLAN PHY transmit rate \n - The values are based on SlWlanRateIndex_e \n - This options takes _u32 as parameter - - SL_SO_PHY_TX_POWER \n - RAW socket, set WLAN PHY TX power \n - Valid rage is 1-15 \n - This options takes _u32 as parameter - - SL_SO_PHY_NUM_FRAMES_TO_TX \n - RAW socket, set number of frames to transmit in transceiver mode. - Default: 1 packet - This options takes _u32 as parameter - - SL_SO_PHY_PREAMBLE \n - RAW socket, set WLAN PHY preamble for Long/Short\n - This options takes _u32 as parameter - - SL_SO_PHY_TX_INHIBIT_THRESHOLD \n - RAW socket, set WLAN Tx – Set CCA threshold. \n - The values are based on SlTxInhibitThreshold_e \n - This options takes _u32 as parameter - - SL_SO_PHY_TX_TIMEOUT \n - RAW socket, set WLAN Tx – changes the TX timeout (lifetime) of transceiver frames. \n - Value in Ms, maximum value is 100ms \n - This options takes _u32 as parameter - - SL_SO_PHY_ALLOW_ACKS \n - RAW socket, set WLAN Tx – Enable\Disable sending ACKs in transceiver mode \n - 0 = disabled / 1 = enabled \n - This options takes _u32 as parameter - - SL_SO_LINGER \n - Socket lingers on close pending remaining send/receive packets\n - - \param[in] optval Specifies a value for the option - \param[in] optlen Specifies the length of the - option value - - \return Zero on success, or negative error code on failure - - \par Persistent - All params are Non- Persistent - \sa sl_getsockopt - \note Belongs to \ref basic_api - \warning - \par Examples - - - SL_SO_KEEPALIVE (disable Keepalive): - \code - SlSockKeepalive_t enableOption; - enableOption.KeepaliveEnabled = 0; - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_KEEPALIVE, (_u8 *)&enableOption,sizeof(enableOption)); - \endcode -
- - - SL_SO_KEEPALIVETIME (Set Keepalive timeout): - \code - _i16 Status; - _u32 TimeOut = 120; - sl_SetSockOpt(Sd, SL_SOL_SOCKET, SL_SO_KEEPALIVETIME,( _u8*) &TimeOut, sizeof(TimeOut)); - \endcode -
- - - SL_SO_RX_NO_IP_BOUNDARY (disable boundary): - \code - SlSockRxNoIpBoundary_t enableOption; - enableOption.RxIpNoBoundaryEnabled = 1; - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_RX_NO_IP_BOUNDARY, (_u8 *)&enableOption,sizeof(enableOption)); - \endcode -
- - - SL_SO_RCVTIMEO: - \code - struct SlTimeval_t timeVal; - timeVal.tv_sec = 1; // Seconds - timeVal.tv_usec = 0; // Microseconds. 10000 microseconds resolution - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_RCVTIMEO, (_u8 *)&timeVal, sizeof(timeVal)); // Enable receive timeout - \endcode -
- - - SL_SO_RCVBUF: - \code - SlSockWinsize_t size; - size.Winsize = 3000; // bytes - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_RCVBUF, (_u8 *)&size, sizeof(size)); - \endcode -
- - - SL_SO_NONBLOCKING: - \code - - SlSockNonblocking_t enableOption; - enableOption.NonblockingEnabled = 1; - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_NONBLOCKING, (_u8 *)&enableOption,sizeof(enableOption)); // Enable/disable nonblocking mode - \endcode -
- - - SL_SO_SECMETHOD: - \code - SlSockSecureMethod_t method; - method.SecureMethod = SL_SO_SEC_METHOD_SSLV3; // security method we want to use - SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, SL_SEC_SOCKET); - sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECMETHOD, (_u8 *)&method, sizeof(method)); - \endcode -
- - - SL_SO_SECURE_MASK: - \code - SlSockSecureMask_t cipher; - cipher.SecureMask = SL_SEC_MASK_SSL_RSA_WITH_RC4_128_SHA; // cipher type - SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, SL_SEC_SOCKET); - sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECURE_MASK,(_u8 *)&cipher, sizeof(cipher)); - \endcode -
- - - SL_SO_SECURE_FILES_CA_FILE_NAME: - \code - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_CA_FILE_NAME,"exuifaxCaCert.der",strlen("exuifaxCaCert.der")); - \endcode -
- - - SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME; - \code - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME,"myPrivateKey.der",strlen("myPrivateKey.der")); - \endcode -
- - - SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME: - \code - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME,"myCertificate.der",strlen("myCertificate.der")); - \endcode -
- - - SL_SO_SECURE_FILES_DH_KEY_FILE_NAME: - \code - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_FILES_DH_KEY_FILE_NAME,"myDHinServerMode.der",strlen("myDHinServerMode.der")); - \endcode -
- - - SL_SO_SECURE_ENABLE_OCSP - \code - _u32 enable; - enable = 1; - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_ENABLE_OCSP,&enable,sizeof(_u32)); - \endcode -
- - - SL_IP_MULTICAST_TTL: - \code - _u8 ttl = 20; - sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_MULTICAST_TTL, &ttl, sizeof(ttl)); - \endcode -
- - - SL_IP_ADD_MEMBERSHIP: - \code - SlSockIpMreq_t mreq; - sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_ADD_MEMBERSHIP, &mreq, sizeof(mreq)); - \endcode -
- - - SL_IP_DROP_MEMBERSHIP: - \code - SlSockIpMreq_t mreq; - sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_DROP_MEMBERSHIP, &mreq, sizeof(mreq)); - \endcode -
- - - SL_SO_CHANGE_CHANNEL: - \code - _u32 newChannel = 6; // range is 1-13 - sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_CHANGE_CHANNEL, &newChannel, sizeof(newChannel)); - \endcode -
- - - SL_SO_SECURE_ALPN: - \code - SlSockSecureALPN_t alpn; - alpn.SecureALPN = SL_SECURE_ALPN_H2 | SL_SECURE_ALPN_H2_14; - sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECURE_ALPN, &alpn, sizeof(SlSockSecureALPN_t)); - \endcode - - SL_SO_SECURE_ALPN_GENERAL - \code - sl_SetSockOpt(sd,SL_SOL_SOCKET,SL_SO_SECURE_ALPN_GENERAL,"h2",strlen("h2")); - sl_Connect(sd, ( SlSockAddr_t *)&addr, addrSize); - length = 10; - sl_GetSockOpt(sd,SL_SOL_SOCKET,SL_SO_SECURE_ALPN_GENERAL,buf,&length); - if(length == 0) - { - //this protocol was not selected by the server - } - else if(memcmp(buf,"h2",length) == 0) - { - //the protocol that was set was picked by the server - } - \endcode -
- - - SL_IP_RAW_RX_NO_HEADER: - \code - _u32 header = 1; // remove ip header - sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_RAW_RX_NO_HEADER, &header, sizeof(header)); - \endcode -
- - - SL_IP_HDRINCL: - \code - _u32 header = 1; - sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_HDRINCL, &header, sizeof(header)); - \endcode -
- - - SL_IP_RAW_IPV6_HDRINCL: - \code - _u32 header = 1; - sl_SetSockOpt(SockID, SL_IPPROTO_IP, SL_IP_RAW_IPV6_HDRINCL, &header, sizeof(header)); - \endcode -
- - - SL_SO_PHY_RATE: - \code - _u32 rate = 6; // see wlan.h SlWlanRateIndex_e for values - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_RATE, &rate, sizeof(rate)); - \endcode -
- - - SL_SO_PHY_TX_POWER: - \code - _u32 txpower = 1; // valid range is 1-15 - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_TX_POWER, &txpower, sizeof(txpower)); - \endcode -
- - - SL_SO_PHY_NUM_FRAMES_TO_TX: - \code - _u32 numframes = 1; - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_NUM_FRAMES_TO_TX, &numframes, sizeof(numframes)); - \endcode -
- - - SL_SO_PHY_PREAMBLE: - \code - _u32 preamble = 1; - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_PREAMBLE, &preamble, sizeof(preamble)); - \endcode -
- - - SL_SO_PHY_TX_INHIBIT_THRESHOLD: - \code - _u32 thrshld = SL_TX_INHIBIT_THRESHOLD_MED; - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_TX_INHIBIT_THRESHOLD , &thrshld, sizeof(thrshld)); - \endcode -
- - - SL_SO_PHY_TX_TIMEOUT: - \code - _u32 timeout = 50; - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_TX_TIMEOUT , &timeout, sizeof(timeout)); - \endcode -
- - - SL_SO_PHY_ALLOW_ACKS: - \code - _u32 acks = 1; // 0 = disabled / 1 = enabled - sl_SetSockOpt(SockID, SL_SOL_PHY_OPT, SL_SO_PHY_ALLOW_ACKS, &acks, sizeof(acks)); - \endcode -
- - SL_SO_PHY_RX_BSSID_DATA_FRAMES - \code - SlRxMetricsEnableDisableRXOnBSS_t flag; - flag.enableDisable = 1; - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_PHY_RX_BSSID_DATA_FRAMES,&flag,sizeof(SlRxMetricsEnableDisableRXOnBSS_t)); - \endcode -
- - - SL_SO_LINGER: - \code - SlSocklinger_t linger; - linger.l_onoff = 1; - linger.l_linger = 10; - sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_LINGER, &linger, sizeof(linger)); - \endcode -
- - - SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP: - \code - int dummy; - sl_SetSockOpt(SockID, SL_SOL_SOCKET, SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP, &dummy, sizeof(dummy)); - \endcode -
- - - SL_SO_SECURE_DOMAIN_NAME_VERIFICATION: - \code - sl_SetSockOpt(SockID,SL_SOL_SOCKET,SL_SO_SECURE_DOMAIN_NAME_VERIFICATION,"www.google.co.il",strlen("www.google.co.il")); - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_SetSockOpt) -_i16 sl_SetSockOpt(_i16 sd, _i16 level, _i16 optname, const void *optval, SlSocklen_t optlen); -#endif - -/*! - \brief Get socket options - - This function manipulate the options associated with a socket. - Options may exist at multiple protocol levels; they are always - present at the uppermost socket level.\n - - When manipulating socket options the level at which the option resides - and the name of the option must be specified. To manipulate options at - the socket level, level is specified as SOL_SOCKET. To manipulate - options at any other level the protocol number of the appropriate - protocol controlling the option is supplied. For example, to indicate - that an option is to be interpreted by the TCP protocol, level should - be set to the protocol number of TCP; \n - - The parameters optval and optlen are used to access optvalues - for setsockopt(). For getsockopt() they identify a - buffer in which the value for the requested option(s) are to - be returned. For getsockopt(), optlen is a value-result - parameter, initially containing the size of the buffer - pointed to by option_value, and modified on return to - indicate the actual size of the value returned. If no option - value is to be supplied or returned, option_value may be - NULL. - - - \param[in] sd Socket handle - \param[in] level Defines the protocol level for this option - \param[in] optname defines the option name to interrogate - \param[out] optval Specifies a value for the option - \param[out] optlen Specifies the length of the - option value - - \return Zero on success, or negative error code on failure - \sa sl_SetSockOpt - \note See sl_SetSockOpt - Belongs to \ref ext_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_GetSockOpt) -_i16 sl_GetSockOpt(_i16 sd, _i16 level, _i16 optname, void *optval, SlSocklen_t *optlen); -#endif - -/*! - \brief Read data from TCP socket - - Function receives a message from a connection-mode socket - - \param[in] sd Socket handle - \param[out] buf Points to the buffer where the - message should be stored. - \param[in] len Specifies the length in bytes of - the buffer pointed to by the buffer argument. - Range: 1-16000 bytes - \param[in] flags Specifies the type of message - reception. On this version, this parameter is not - supported. - - \return Return the number of bytes received, - or a negative value if an error occurred.\n - Using a non-blocking recv a possible negative value is SL_EAGAIN.\n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa sl_RecvFrom - \note Belongs to \ref recv_api - \warning - \par Examples - - - Receiving data using TCP socket: - \code - SlSockAddrIn_t Addr; - SlSockAddrIn_t LocalAddr; - _i16 AddrSize = sizeof(SlSockAddrIn_t); - _i16 SockID, newSockID; - _i16 Status; - _i8 Buf[RECV_BUF_LEN]; - - LocalAddr.sin_family = SL_AF_INET; - LocalAddr.sin_port = sl_Htons(5001); - LocalAddr.sin_addr.s_addr = 0; - - Addr.sin_family = SL_AF_INET; - Addr.sin_port = sl_Htons(5001); - Addr.sin_addr.s_addr = sl_Htonl(SL_IPV4_VAL(10,1,1,200)); - - SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, 0); - Status = sl_Bind(SockID, (SlSockAddr_t *)&LocalAddr, AddrSize); - Status = sl_Listen(SockID, 0); - newSockID = sl_Accept(SockID, (SlSockAddr_t*)&Addr, (SlSocklen_t*) &AddrSize); - Status = sl_Recv(newSockID, Buf, 1460, 0); - \endcode -
- - - Rx transceiver mode using a raw socket: - \code - _i8 buffer[1536]; - _i16 sd; - _u16 size; - SlTransceiverRxOverHead_t *transHeader; - sd = sl_Socket(SL_AF_RF,SL_SOCK_RAW,11); // channel 11 - while(1) - { - size = sl_Recv(sd,buffer,1536,0); - transHeader = (SlTransceiverRxOverHead_t *)buffer; - printf("RSSI is %d frame type is 0x%x size %d\n",transHeader->rssi,buffer[sizeof(SlTransceiverRxOverHead_t)],size); - } - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_Recv) -_i16 sl_Recv(_i16 sd, void *buf, _i16 len, _i16 flags); -#endif - -/*! - \brief Read data from socket - - Function receives a message from a connection-mode or - connectionless-mode socket - - \param[in] sd Socket handle - \param[out] buf Points to the buffer where the message should be stored. - \param[in] len Specifies the length in bytes of the buffer pointed to by the buffer argument. - Range: 1-16000 bytes - \param[in] flags Specifies the type of message - reception. On this version, this parameter is not - supported. - \param[in] from Pointer to an address structure - indicating the source - address.\n sockaddr:\n - code - for the address format. On this - version only AF_INET is - supported.\n - socket address, - the length depends on the code - format - \param[in] fromlen Source address structure - size. This parameter MUST be set to the size of the structure pointed to by addr. - - - \return Return the number of bytes received, - or a negative value if an error occurred.\n - Using a non-blocking recv a possible negative value is SL_EAGAIN. - SL_RET_CODE_INVALID_INPUT (-2) will be returned if fromlen has incorrect length. \n - SL_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa sl_Recv - \note Belongs to \ref recv_api - \warning - \par Example - - - Receiving data: - \code - SlSockAddrIn_t Addr; - SlSockAddrIn_t LocalAddr; - _i16 AddrSize = sizeof(SlSockAddrIn_t); - _i16 SockID; - _i16 Status; - _i8 Buf[RECV_BUF_LEN]; - - LocalAddr.sin_family = SL_AF_INET; - LocalAddr.sin_port = sl_Htons(5001); - LocalAddr.sin_addr.s_addr = 0; - - SockID = sl_Socket(SL_AF_INET,SL_SOCK_DGRAM, 0); - Status = sl_Bind(SockID, (SlSockAddr_t *)&LocalAddr, AddrSize); - Status = sl_RecvFrom(SockID, Buf, 1472, 0, (SlSockAddr_t *)&Addr, (SlSocklen_t*)&AddrSize); - - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_RecvFrom) -_i16 sl_RecvFrom(_i16 sd, void *buf, _i16 len, _i16 flags, SlSockAddr_t *from, SlSocklen_t *fromlen); -#endif - -/*! - \brief Write data to TCP socket - - This function is used to transmit a message to another socket. - Returns immediately after sending data to device. - In case of TCP failure an async event SL_SOCKET_TX_FAILED_EVENT is going to - be received.\n - In case of a RAW socket (transceiver mode), extra 4 bytes should be reserved at the end of the - frame data buffer for WLAN FCS - - \param[in] sd Socket handle - \param[in] buf Points to a buffer containing - the message to be sent - \param[in] len Message size in bytes. - \param[in] flags Specifies the type of message - transmission. On this version, this parameter is not - supported for TCP. - For transceiver mode, the SL_WLAN_RAW_RF_TX_PARAMS macro can be used to determine - transmission parameters (channel,rate,tx_power,preamble) - -rate need to be define using slSockTransceiverTXRateTable_e - - - \return On success, number of transmitted bytes is return, or negative error code on failure - - \sa sl_SendTo - \note Belongs to \ref send_api - \warning - \par Example - - - Sending data: - \code - SlSockAddrIn_t Addr; - _i16 AddrSize = sizeof(SlSockAddrIn_t); - _i16 SockID; - _i16 Status; - _i8 Buf[SEND_BUF_LEN]; - - Addr.sin_family = SL_AF_INET; - Addr.sin_port = sl_Htons(5001); - Addr.sin_addr.s_addr = sl_Htonl(SL_IPV4_VAL(10,1,1,200)); - - SockID = sl_Socket(SL_AF_INET,SL_SOCK_STREAM, 0); - Status = sl_Connect(SockID, (SlSockAddr_t *)&Addr, AddrSize); - Status = sl_Send(SockID, Buf, 1460, 0 ); - \endcode - */ -#if _SL_INCLUDE_FUNC(sl_Send ) -_i16 sl_Send(_i16 sd, const void *buf, _i16 len, _i16 flags); -#endif - -/*! - \brief Write data to socket - - This function is used to transmit a message to another socket - (connection less socket SOCK_DGRAM, SOCK_RAW).\n - Returns immediately after sending data to device.\n - In case of transmission failure an async event SL_SOCKET_TX_FAILED_EVENT is going to - be received. - - \param[in] sd Socket handle - \param[in] buf Points to a buffer containing - the message to be sent - \param[in] len message size in bytes. - \param[in] flags Specifies the type of message - transmission. On this version, this parameter is not - supported - \param[in] to Pointer to an address structure - indicating the destination - address.\n sockaddr:\n - code - for the address format. On this - version only AF_INET is - supported.\n - socket address, - the length depends on the code - format - \param[in] tolen Destination address structure size - - \return On success, number of transmitted bytes is return, or negative error code on failure - - \sa sl_Send - \note Belongs to \ref send_api - \warning - \par Example - - - Sending data: - \code - SlSockAddrIn_t Addr; - _i16 AddrSize = sizeof(SlSockAddrIn_t); - _i16 SockID; - _i16 Status; - _i8 Buf[SEND_BUF_LEN]; - - Addr.sin_family = SL_AF_INET; - Addr.sin_port = sl_Htons(5001); - Addr.sin_addr.s_addr = sl_Htonl(SL_IPV4_VAL(10,1,1,200)); - - SockID = sl_Socket(SL_AF_INET,SL_SOCK_DGRAM, 0); - Status = sl_SendTo(SockID, Buf, 1472, 0, (SlSockAddr_t *)&Addr, AddrSize); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_SendTo) -_i16 sl_SendTo(_i16 sd, const void *buf, _i16 len, _i16 flags, const SlSockAddr_t *to, SlSocklen_t tolen); -#endif - -/*! - \brief Initiate TLS connection on a socket - - Function Initiate TLS connection on the socket referred to by - the socket descriptor sd. This function will works on blocking - mode until the TLS handshake success or fails. - - \param[in] sd Socket descriptor (handle) - - \return Zero on success, or negative error code on failure - - \sa sl_Socket - \note belongs to \ref client_side - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_StartTLS) -_i16 sl_StartTLS(_i16 sd); -#endif - -/*! - \brief Reorder the bytes of a 32-bit unsigned value - - This function is used to Reorder the bytes of a 32-bit unsigned value from processor order to network order. - - \param[in] val Variable to reorder - - \return Return the reorder variable, - - \sa sl_SendTo sl_Bind sl_Connect sl_RecvFrom sl_Accept - \note Belongs to \ref send_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Htonl ) -_u32 sl_Htonl( _u32 val ); - -#define sl_Ntohl sl_Htonl /* Reorder the bytes of a 16-bit unsigned value from network order to processor orde. */ -#endif - -/*! - \brief Reorder the bytes of a 16-bit unsigned value - - This function is used to Reorder the bytes of a 16-bit unsigned value from processor order to network order. - - \param[in] val Variable to reorder - - \return Return the reorder variable, - - \sa sl_SendTo sl_Bind sl_Connect sl_RecvFrom sl_Accept - \note Belongs to \ref send_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_Htons ) -_u16 sl_Htons( _u16 val ); - -#define sl_Ntohs sl_Htons /* Reorder the bytes of a 16-bit unsigned value from network order to processor orde. */ -#endif - -/*! - \cond DOXYGEN_IGNORE -*/ - -/*! - \brief Select's SlFdSet_t SET function - - Sets current socket descriptor on SlFdSet_t container -*/ -void SL_SOCKET_FD_SET(_i16 fd, SlFdSet_t *fdset); - -/*! - \brief Select's SlFdSet_t CLR function - - Clears current socket descriptor on SlFdSet_t container -*/ -void SL_SOCKET_FD_CLR(_i16 fd, SlFdSet_t *fdset); - - -/*! - \brief Select's SlFdSet_t ISSET function - - Checks if current socket descriptor is set (TRUE/FALSE) - - \return Returns TRUE if set, FALSE if unset - -*/ -_i16 SL_SOCKET_FD_ISSET(_i16 fd, SlFdSet_t *fdset); - -/*! - \brief Select's SlFdSet_t ZERO function - - Clears all socket descriptors from SlFdSet_t -*/ -void SL_SOCKET_FD_ZERO(SlFdSet_t *fdset); - -/*! - \endcond -*/ - -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __SOCKET_H__ */ - - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/slnetif/slnetifwifi.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/slnetif/slnetifwifi.c deleted file mode 100644 index ee6b20d7be9..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/slnetif/slnetifwifi.c +++ /dev/null @@ -1,604 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -#include - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/* Macro which split the 8bit security flags from the input flags */ -#define SPLIT_SEC_AND_INPUT_FLAGS(inputFlags, secFlags) (secFlags = inputFlags >> 24) - -/* Disable the 8bit security flags */ -#define SECURITY_FLAGS_IN_32BIT_REPRESENTATION (0xFF000000) -#define DISABLE_SEC_BITS_FROM_INPUT_FLAGS(inputFlags) (inputFlags &= ~SECURITY_FLAGS_IN_32BIT_REPRESENTATION) - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Global declarations */ -/*****************************************************************************/ - -/*! - SlNetIfConfigWifi structure contains all the function callbacks that are expected to be filled by the relevant network stack interface - Each interface has different capabilities, so not all the API's must be supported. - Interface that is not supporting a non-mandatory API are set to NULL -*/ -SlNetIf_Config_t SlNetIfConfigWifi = -{ - SlNetIfWifi_socket, // Callback function sockCreate in slnetif module - SlNetIfWifi_close, // Callback function sockClose in slnetif module - NULL, // Callback function sockShutdown in slnetif module - SlNetIfWifi_accept, // Callback function sockAccept in slnetif module - SlNetIfWifi_bind, // Callback function sockBind in slnetif module - SlNetIfWifi_listen, // Callback function sockListen in slnetif module - SlNetIfWifi_connect, // Callback function sockConnect in slnetif module - NULL, // Callback function sockGetPeerName in slnetif module - NULL, // Callback function sockGetLocalName in slnetif module - SlNetIfWifi_select, // Callback function sockSelect in slnetif module - SlNetIfWifi_setSockOpt, // Callback function sockSetOpt in slnetif module - SlNetIfWifi_getSockOpt, // Callback function sockGetOpt in slnetif module - SlNetIfWifi_recv, // Callback function sockRecv in slnetif module - SlNetIfWifi_recvFrom, // Callback function sockRecvFrom in slnetif module - SlNetIfWifi_send, // Callback function sockSend in slnetif module - SlNetIfWifi_sendTo, // Callback function sockSendTo in slnetif module - SlNetIfWifi_sockstartSec, // Callback function sockstartSec in slnetif module - SlNetIfWifi_getHostByName, // Callback function utilGetHostByName in slnetif module - SlNetIfWifi_getIPAddr, // Callback function ifGetIPAddr in slnetif module - SlNetIfWifi_getConnectionStatus, // Callback function ifGetConnectionStatus in slnetif module - SlNetIfWifi_loadSecObj, // Callback function ifLoadSecObj in slnetif module - NULL // Callback function ifCreateContext in slnetif module -}; - -static const int16_t StartSecOptName[10] = -{ - SL_SO_SECURE_FILES_PRIVATE_KEY_FILE_NAME, - SL_SO_SECURE_FILES_CERTIFICATE_FILE_NAME, - SL_SO_SECURE_FILES_CA_FILE_NAME, - SL_SO_SECURE_FILES_PEER_CERT_OR_DH_KEY_FILE_NAME, - SL_SO_SECMETHOD, - SL_SO_SECURE_MASK, - SL_SO_SECURE_ALPN, - SL_SO_SECURE_EXT_CLIENT_CHLNG_RESP, - SL_SO_SECURE_DOMAIN_NAME_VERIFICATION, - SL_SO_SECURE_DISABLE_CERTIFICATE_STORE -}; - -static const int16_t socketType[8] = -{ - SL_SOCK_STREAM, - SL_SOCK_DGRAM, - SL_SOCK_RAW, - SLNETSOCK_SOCK_RX_MTR, - SL_SOCK_DGRAM, - SL_SOCK_RAW, - SLNETSOCK_SOCK_BRIDGE, - SLNETSOCK_SOCK_ROUTER, -}; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -//***************************************************************************** -// -// SlNetIfWifi_socket - Create an endpoint for communication -// -//***************************************************************************** -int16_t SlNetIfWifi_socket(void *ifContext, int16_t Domain, int16_t Type, int16_t Protocol, void **sdContext) -{ - /* Create socket and return the return value of the function */ - int16_t mappedSocketType = socketType[Type - 1]; - return (sl_Socket(Domain, mappedSocketType, Protocol)); -} - - -//***************************************************************************** -// -// SlNetIfWifi_close - Gracefully close socket -// -//***************************************************************************** -int32_t SlNetIfWifi_close(int16_t sd, void *sdContext) -{ - /* Close socket and return the return value of the function */ - return sl_Close(sd); -} - - -//***************************************************************************** -// -// SlNetIfWifi_accept - Accept a connection on a socket -// -//***************************************************************************** -int16_t SlNetIfWifi_accept(int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen, uint8_t flags, void **acceptedSdContext) -{ - return sl_Accept(sd, (SlSockAddr_t *)addr, addrlen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_bind - Assign a name to a socket -// -//***************************************************************************** -int32_t SlNetIfWifi_bind(int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, int16_t addrlen) -{ - return sl_Bind(sd, (const SlSockAddr_t *)addr, addrlen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_listen - Listen for connections on a socket -// -//***************************************************************************** -int32_t SlNetIfWifi_listen(int16_t sd, void *sdContext, int16_t backlog) -{ - return sl_Listen(sd, backlog); -} - - -//***************************************************************************** -// -// SlNetIfWifi_connect - Initiate a connection on a socket -// -//***************************************************************************** -int32_t SlNetIfWifi_connect(int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen, uint8_t flags) -{ - return sl_Connect(sd, (const SlSockAddr_t *)addr, addrlen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_getSockName - Returns the local address info of the socket -// descriptor -// -//***************************************************************************** -int32_t SlNetIfWifi_getSockName(int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen) -{ -// Not implemented in NWP - return SLNETERR_INVALPARAM; -} - - -//***************************************************************************** -// -// SlNetIfWifi_select - Monitor socket activity -// -//***************************************************************************** -int32_t SlNetIfWifi_select(void *ifContext, int16_t nfds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout) -{ - SlNetSock_Timeval_t *slNetSockTimeVal; - SlTimeval_t tv; - /* Translate from SlNetSock_Timeval_t into SlTimeval_t */ - slNetSockTimeVal = (SlNetSock_Timeval_t *)timeout; - tv.tv_sec = slNetSockTimeVal->tv_sec; - tv.tv_usec = slNetSockTimeVal->tv_usec; - return sl_Select(nfds, (SlFdSet_t *)readsds, (SlFdSet_t *)writesds, (SlFdSet_t *)exceptsds, &tv); -} - - -//***************************************************************************** -// -// SlNetIfWifi_setSockOpt - Set socket options -// -//***************************************************************************** -int32_t SlNetIfWifi_setSockOpt(int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen) -{ - SlNetSock_Timeval_t *slNetSockTimeVal; - SlTimeval_t tv; - - switch (level) - { - case SLNETSOCK_LVL_SOCKET: - { - switch (optname) - { - case SLNETSOCK_OPSOCK_RCV_TIMEO: - { - /* Translate from SlNetSock_Timeval_t into SlTimeval_t */ - slNetSockTimeVal = (SlNetSock_Timeval_t *)optval; - tv.tv_sec = slNetSockTimeVal->tv_sec; - tv.tv_usec = slNetSockTimeVal->tv_usec; - optval = (void *)&tv; - optlen = sizeof(SlTimeval_t); - break; - } - default: - /* Pass values into sl_SetSockOpt directly */ - break; - } - break; - } - default: - /* Pass values into sl_SetSockOpt directly */ - break; - } - - return sl_SetSockOpt(sd, level, optname, optval, optlen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_getSockOpt - Get socket options -// -//***************************************************************************** -int32_t SlNetIfWifi_getSockOpt(int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen) -{ - SlSocklen_t len; - int32_t status = 0; - SlNetSock_Timeval_t *slNetSockTimeVal; - SlTimeval_t tv; - - switch (level) - { - case SLNETSOCK_LVL_SOCKET: - { - switch (optname) - { - case SLNETSOCK_OPSOCK_RCV_TIMEO: - { - if (*optlen < sizeof(SlNetSock_Timeval_t)) - { - return (SLNETERR_RET_CODE_INVALID_INPUT); - } - len = sizeof(SlTimeval_t); - status = - sl_GetSockOpt(sd, level, optname, (void *)&tv, &len); - - slNetSockTimeVal = (SlNetSock_Timeval_t *)optval; - slNetSockTimeVal->tv_sec = tv.tv_sec; - slNetSockTimeVal->tv_usec = tv.tv_usec; - *optlen = sizeof(SlNetSock_Timeval_t); - break; - } - - default: - { - /* Pass values into sl_SetSockOpt directly */ - status = sl_GetSockOpt(sd, level, optname, optval, optlen); - break; - } - - } - break; - } - default: - { - /* Pass values into sl_SetSockOpt directly */ - status = sl_GetSockOpt(sd, level, optname, optval, optlen); - break; - } - } - - return (status); -} - - -//***************************************************************************** -// -// SlNetIfWifi_recv - Read data from TCP socket -// -//***************************************************************************** -int32_t SlNetIfWifi_recv(int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags) -{ - DISABLE_SEC_BITS_FROM_INPUT_FLAGS(flags); - return sl_Recv(sd, buf, len, flags); -} - - -//***************************************************************************** -// -// SlNetIfWifi_recvFrom - Read data from socket -// -//***************************************************************************** -int32_t SlNetIfWifi_recvFrom(int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen) -{ - DISABLE_SEC_BITS_FROM_INPUT_FLAGS(flags); - return sl_RecvFrom(sd, buf, len, flags, (SlSockAddr_t *)from, fromlen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_send - Write data to TCP socket -// -//***************************************************************************** -int32_t SlNetIfWifi_send(int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags) -{ - DISABLE_SEC_BITS_FROM_INPUT_FLAGS(flags); - return sl_Send(sd, buf, len, flags); -} - - -//***************************************************************************** -// -// SlNetIfWifi_sendTo - Write data to socket -// -//***************************************************************************** -int32_t SlNetIfWifi_sendTo(int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen) -{ - DISABLE_SEC_BITS_FROM_INPUT_FLAGS(flags); - return sl_SendTo(sd, buf, len, flags, (const SlSockAddr_t *)to, tolen); -} - - -//***************************************************************************** -// -// SlNetIfWifi_sockstartSec - Start a security session on an opened socket -// -//***************************************************************************** -int32_t SlNetIfWifi_sockstartSec(int16_t sd, void *sdContext, SlNetSockSecAttrib_t *secAttrib, uint8_t flags) -{ - SlNetSock_SecAttribNode_t *tempSecAttrib = *secAttrib; - int32_t retVal = SLNETERR_RET_CODE_OK; - - if ( 0 != (flags & SLNETSOCK_SEC_BIND_CONTEXT_ONLY) ) - { - /* run over all attributes and set them */ - while (NULL != tempSecAttrib) - { - if ( tempSecAttrib->attribName <= SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE) - { - retVal = sl_SetSockOpt(sd, SL_SOL_SOCKET, StartSecOptName[tempSecAttrib->attribName], tempSecAttrib->attribBuff, tempSecAttrib->attribBuffLen); - } - else - { - return SLNETERR_RET_CODE_INVALID_INPUT; - } - tempSecAttrib = tempSecAttrib->next; - } - } - - if ( 0 != (flags & SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY) ) - { - /* Start TLS session */ - retVal = sl_StartTLS(sd); - } - - return retVal; -} - - -//***************************************************************************** -// -// SlNetIfWifi_getHostByName - Obtain the IP Address of machine on network, by -// machine name -// -//***************************************************************************** -int32_t SlNetIfWifi_getHostByName(void *ifContext, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - - /* sl_NetAppDnsGetHostByName can receive only one ipAddr variable, so - only the first slot of the array will be used and the ipAddrLen will - be updated to 1 when function is successfully */ - retVal = sl_NetAppDnsGetHostByName((signed char *)name, nameLen, (_u32 *)ipAddr, family); - - if (retVal == SLNETERR_RET_CODE_OK) - { - *ipAddrLen = 1; - } - - return retVal; - -} - - -//***************************************************************************** -// -// matchModeByRole - Service function used by SlNetIfWifi_getIPAddr for matching SlNetIfAddressType_e to SlNetCfg_e -// -//***************************************************************************** -int32_t matchModeByRole(SlNetIfAddressType_e addrType, - SlNetCfg_e *newAddrType , - uint16_t *ipAddrLen ) -{ - SlWlanConnStatusParam_t WlanConnectInfo; - uint16_t Len; - int32_t retVal; - - switch(addrType) - { - - case SLNETIF_IPV6_ADDR_LOCAL: - *newAddrType = SL_NETCFG_IPV6_ADDR_LOCAL; - *ipAddrLen = sizeof(SlNetCfgIpV6Args_t); - retVal = SLNETERR_RET_CODE_OK; - break; - - case SLNETIF_IPV6_ADDR_GLOBAL: - *newAddrType = SL_NETCFG_IPV6_ADDR_GLOBAL; - *ipAddrLen = sizeof(SlNetCfgIpV6Args_t); - retVal = SLNETERR_RET_CODE_OK; - break; - - /* IPv4 or P2P (GO and CL) */ - case SLNETIF_IPV4_ADDR: - Len = sizeof(SlWlanConnStatusParam_t); - *ipAddrLen = sizeof(SlNetCfgIpV4Args_t); - retVal = sl_WlanGet(SL_WLAN_CONNECTION_INFO, NULL , &Len, (uint8_t*)&WlanConnectInfo); - if(retVal != SLNETERR_RET_CODE_OK) - { - return retVal; - } - if(WlanConnectInfo.ConnStatus == SL_WLAN_CONNECTED_STA || WlanConnectInfo.ConnStatus == SL_WLAN_CONNECTED_P2PCL) - { - *newAddrType = SL_NETCFG_IPV4_STA_ADDR_MODE; - retVal = SLNETERR_RET_CODE_OK; - } - else if(WlanConnectInfo.ConnStatus == SL_WLAN_CONNECTED_P2PGO || WlanConnectInfo.ConnStatus == SL_WLAN_AP_CONNECTED_STATIONS) - { - *newAddrType = SL_NETCFG_IPV4_AP_ADDR_MODE; - retVal = SLNETERR_RET_CODE_OK; - } - else - { - retVal = SLNETERR_BSD_ENOTCONN; - } - - } - return retVal; -} - - -//***************************************************************************** -// -// SlNetIfWifi_getIPAddr - Get IP Address of specific interface -// -//***************************************************************************** -int32_t SlNetIfWifi_getIPAddr(void *ifContext, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr) -{ - int32_t retVal; - uint16_t ipAddrLen; - SlNetCfg_e newAddrType; - - /* Translate the addrType of SlNetSock type to addrType of SlNetSockIfWifi type */ - retVal = matchModeByRole(addrType, &newAddrType, &ipAddrLen); - if(retVal == SLNETERR_RET_CODE_OK) - { - retVal = sl_NetCfgGet(newAddrType, addrConfig, &ipAddrLen, (unsigned char *)ipAddr); - } - return retVal; -} - - -//***************************************************************************** -// -// SlNetIfWifi_getConnectionStatus - Get interface connection status -// -//***************************************************************************** -int32_t SlNetIfWifi_getConnectionStatus(void *ifContext) -{ - SlWlanConnStatusParam_t connectionParams; - uint16_t Opt = 0; - int32_t retVal = 0; - uint16_t Size = 0; - - Size = sizeof(SlWlanConnStatusParam_t); - memset(&connectionParams, 0, Size); - - retVal = sl_WlanGet(SL_WLAN_CONNECTION_INFO, &Opt, &Size, (uint8_t *)&connectionParams); - - /* Check if the function returned an error */ - if (retVal < SLNETERR_RET_CODE_OK) - { - /* Return error code */ - return retVal; - } - return connectionParams.ConnStatus; -} - - -//***************************************************************************** -// -// SlNetIfWifi_loadSecObj - Load secured buffer to the network stack -// -//***************************************************************************** -int32_t SlNetIfWifi_loadSecObj(void *ifContext, uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen) -{ - int32_t retVal; /* negative retVal is an error */ - uint16_t i; - uint32_t Offset = 0; - uint32_t MasterToken = 0; - int32_t OpenFlags = 0; - int32_t DeviceFileHandle = (-1); - uint16_t macAddressLen = SL_MAC_ADDR_LEN; - char *deviceFileName = objName; - uint8_t macAddress[SL_MAC_ADDR_LEN]; - - /* Check if the inputs exists */ - if ((NULL == objName) || (NULL == objBuff)) - { - /* input not valid, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - /* Print device MAC address */ - retVal = sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET, 0, &macAddressLen, &macAddress[0]); - - /* Generating Random MasterPassword but constant per deviceFileName */ - for (i = 0; i < strlen(deviceFileName); i++) - { - MasterToken = ((MasterToken << 8) ^ deviceFileName[i]); - } - - /* Create a file and write data. The file is secured, without - signature and with a fail safe commit, with vendor token which is - a XOR combination between the MAC address of the device and the - object file name */ - OpenFlags = SL_FS_CREATE; - OpenFlags |= SL_FS_OVERWRITE; - OpenFlags |= SL_FS_CREATE_SECURE; - OpenFlags |= SL_FS_CREATE_VENDOR_TOKEN; - OpenFlags |= SL_FS_CREATE_NOSIGNATURE; - OpenFlags |= SL_FS_CREATE_FAILSAFE; - - /* Create a secure file if not exists and open it for write. */ - DeviceFileHandle = sl_FsOpen((unsigned char *)deviceFileName, OpenFlags | SL_FS_CREATE_MAX_SIZE( objBuffLen ), (unsigned long *)&MasterToken); - - /* Check if file created successfully */ - if ( DeviceFileHandle < SLNETERR_RET_CODE_OK ) - { - return DeviceFileHandle; - } - - Offset = 0; - /* Write the buffer to the new file */ - retVal = sl_FsWrite(DeviceFileHandle, Offset, (unsigned char *)objBuff, objBuffLen); - - /* Close the file */ - retVal = sl_FsClose(DeviceFileHandle, NULL, NULL , 0); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetIfWifi_CreateContext - Allocate and store interface data -// -//***************************************************************************** -int32_t SlNetIfWifi_CreateContext(uint16_t ifID, const char *ifName, void **context) -{ - return SLNETERR_RET_CODE_OK; -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/slnetifwifi.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/slnetifwifi.h deleted file mode 100644 index 21b365a27f2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/slnetifwifi.h +++ /dev/null @@ -1,1230 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include -#include -#include - -#ifndef __SLNETWIFI_SOCKET_H__ -#define __SLNETWIFI_SOCKET_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup WiFi Socket Stack - \short Controls standard client/server sockets programming options and capabilities - -*/ -/*! - - \addtogroup Socket - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/* prototype ifConf */ -extern SlNetIf_Config_t SlNetIfConfigWifi; - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - - \brief Create an endpoint for communication - - The SlNetIfWifi_socket function creates a new socket of a certain socket - type, identified by an integer number, and allocates system resources to - it.\n - This function is called by the application layer to obtain a socket descriptor (handle). - - \param[in] ifContext Stores interface data if CreateContext function - supported and implemented. - \param[in] domain Specifies the protocol family of the created socket. - For example: - - SLNETSOCK_AF_INET for network protocol IPv4 - - SLNETSOCK_AF_INET6 for network protocol IPv6 - - SLNETSOCK_AF_RF for starting transceiver mode. - Notes: - - sending and receiving any packet overriding 802.11 header - - for optimized power consumption the socket will be started in TX - only mode until receive command is activated - \param[in] type Specifies the socket type, which determines the semantics of communication over - the socket. The socket types supported by the system are implementation-dependent. - Possible socket types include: - - SLNETSOCK_SOCK_STREAM (reliable stream-oriented service or Stream Sockets) - - SLNETSOCK_SOCK_DGRAM (datagram service or Datagram Sockets) - - SLNETSOCK_SOCK_RAW (raw protocols atop the network layer) - - when used with AF_RF: - - SLNETSOCK_SOCK_RX_MTR - - SLNETSOCK_SOCK_MAC_WITH_CCA - - SLNETSOCK_SOCK_MAC_WITH_NO_CCA - - SLNETSOCK_SOCK_BRIDGE - - SLNETSOCK_SOCK_ROUTER - \param[in] protocol Specifies a particular transport to be used with the socket.\n - The most common are - - SLNETSOCK_PROTO_TCP - - SLNETSOCK_PROTO_UDP - - SLNETSOCK_PROTO_RAW - - SLNETSOCK_PROTO_SECURE - The value 0 may be used to select a default - protocol from the selected domain and type - \param[in] sdContext Allocate and store socket data if needed for - using in other slnetwifi socket functions - - \return On success, socket descriptor (handle) that is used for consequent socket operations. \n - A successful return code should be a positive number (int16)\n - On error, a negative value will be returned specifying the error code. - - SLNETERR_BSD_EAFNOSUPPORT - illegal domain parameter - - SLNETERR_BSD_EPROTOTYPE - illegal type parameter - - SLNETERR_BSD_EACCES - permission denied - - SLNETERR_BSD_ENSOCK - exceeded maximal number of socket - - SLNETERR_BSD_ENOMEM - memory allocation error - - SLNETERR_BSD_EINVAL - error in socket configuration - - SLNETERR_BSD_EPROTONOSUPPORT - illegal protocol parameter - - SLNETERR_BSD_EOPNOTSUPP - illegal combination of protocol and type parameters - - \sa SlNetIfWifi_socket - \note - \warning -*/ -int16_t SlNetIfWifi_socket(void *ifContext, int16_t Domain, int16_t Type, int16_t Protocol, void **sdContext); - -/*! - \brief Gracefully close socket - - The SlNetIfWifi_close function causes the system to release resources allocated to a socket. \n - In case of TCP, the connection is terminated. - - \param[in] sd Socket descriptor (handle), received in SlNetIfWifi_socket - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - - \return Zero on success, or negative error code on failure - - \sa SlNetIfWifi_socket - \note - \warning -*/ -int32_t SlNetIfWifi_close(int16_t sd, void *sdContext); - -/*! - \brief Accept a connection on a socket - - The SlNetIfWifi_accept function is used with connection-based socket types (SOCK_STREAM).\n - It extracts the first connection request on the queue of pending - connections, creates a new connected socket, and returns a new file - descriptor referring to that socket.\n - The newly created socket is not in the listening state. The - original socket sd is unaffected by this call. \n - The argument sd is a socket that has been created with - SlNetIfWifi_socket(), bound to a local address with SlNetIfWifi_bind(), and is - listening for connections after a SlNetIfWifi_listen(). \n The argument - \e addr is a pointer to a sockaddr structure. This structure - is filled in with the address of the peer socket, as known to - the communications layer. \n The exact format of the address - returned addr is determined by the socket's address family. \n - The \b \e addrlen argument is a value-result argument: it - should initially contain the size of the structure pointed to - by addr, on return it will contain the actual length (in - bytes) of the address returned. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[out] addr The argument addr is a pointer - to a sockaddr structure. This - structure is filled in with the - address of the peer socket, as - known to the communications - layer. The exact format of the - address returned addr is - determined by the socket's - address\n - sockaddr:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[out] addrlen The addrlen argument is a value-result - argument: it should initially contain the - size of the structure pointed to by addr - \param[in] flags Specifies socket descriptor flags. \n - The available flags are: - - SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY - - SLNETSOCK_SEC_BIND_CONTEXT_ONLY - Note: This flags can be used in order to start - security session if needed - \param[in] acceptedSdContext Allocate and store data for the new socket - if needed in other to use it in other - slnetwifi socket functions - - \return On success, a socket descriptor.\n - On a non-blocking accept a possible negative value is SLNETERR_BSD_EAGAIN.\n - On failure, negative error code.\n - SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa SlNetIfWifi_Socket SlNetIfWifi_Bind SlNetIfWifi_Listen - \note - \warning -*/ -int16_t SlNetIfWifi_accept(int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen, uint8_t flags, void **acceptedSdContext); - -/*! - \brief Assign a name to a socket - - This SlNetIfWifi_bind function gives the socket the local address addr. - addr is addrlen bytes long. \n Traditionally, this is called - When a socket is created with socket, it exists in a name - space (address family) but has no name assigned. \n - It is necessary to assign a local address before a SOCK_STREAM - socket may receive connections. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] addr Specifies the destination - addrs\n sockaddr:\n - code for - the address format.\n - socket address, - the length depends on the code - format - \param[in] addrlen Contains the size of the structure pointed to by addr - - \return Zero on success, or negative error code on failure - - \sa SlNetIfWifi_Socket SlNetIfWifi_accept SlNetIfWifi_Listen - \note - \warning -*/ -int32_t SlNetIfWifi_bind(int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, int16_t addrlen); - -/*! - \brief Listen for connections on a socket - - The willingness to accept incoming connections and a queue - limit for incoming connections are specified with SlNetIfWifi_listen(), - and then the connections are accepted with SlNetIfWifi_accept(). \n - The SlNetIfWifi_listen() call applies only to sockets of type SOCK_STREAM - The backlog parameter defines the maximum length the queue of - pending connections may grow to. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] backlog Specifies the listen queue depth. - - \return Zero on success, or negative error code on failure - - \sa SlNetIfWifi_Socket SlNetIfWifi_accept SlNetIfWifi_bind - \note - \warning -*/ -int32_t SlNetIfWifi_listen(int16_t sd, void *sdContext, int16_t backlog); - -/*! - \brief Initiate a connection on a socket - - Function connects the socket referred to by the socket - descriptor sd, to the address specified by addr. \n The addrlen - argument specifies the size of addr. \n The format of the - address in addr is determined by the address space of the - socket. \n If it is of type SLNETSOCK_SOCK_DGRAM, this call - specifies the peer with which the socket is to be associated; - this address is that to which datagrams are to be sent, and - the only address from which datagrams are to be received. \n If - the socket is of type SLNETSOCK_SOCK_STREAM, this call - attempts to make a connection to another socket. \n The other - socket is specified by address, which is an address in the - communications space of the socket. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] addr Specifies the destination addr\n - sockaddr:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[in] addrlen Contains the size of the structure pointed - to by addr - \param[in] flags Specifies socket descriptor flags. \n - The available flags are: - - SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY - - SLNETSOCK_SEC_BIND_CONTEXT_ONLY - Note: This flags can be used in order to start - security session if needed - - \return On success, a socket descriptor (handle).\n - On a non-blocking connect a possible negative value is NETSCOK_EALREADY. - On failure, negative value.\n - NETSCOK_POOL_IS_EMPTY may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa SlNetIfWifi_socket - \note - \warning -*/ -int32_t SlNetIfWifi_connect(int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen, uint8_t flags); - -/*! - \brief Get local address info by socket descriptor\n - Returns the local address info of the socket descriptor. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[out] addr The argument addr is a pointer - to a SlNetSock_Addr_t structure. This - structure is filled in with the - address of the peer socket, as - known to the communications - layer. The exact format of the - address returned addr is - determined by the socket's - address\n - SlNetSock_Addr_t:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[out] addrlen The addrlen argument is a value-result - argument: it should initially contain the - size of the structure pointed to by addr - - \return Zero on success, or negative on failure.\n - - - \sa SlNetSock_create SlNetSock_bind - \note If the provided buffer is too small the returned address will be - truncated and the addrlen will contain the actual size of the - socket address - \warning -*/ -int32_t SlNetIfWifi_getSockName(int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); - -/*! - \brief Monitor socket activity - - SlNetIfWifi_send allow a program to monitor multiple file descriptors, - waiting until one or more of the file descriptors become - "ready" for some class of I/O operation. - If trigger mode is enabled the active sdset is the one that retrieved in the first triggered call. - To enable the trigger mode, an handler must be statically registered to the slcb_SocketTriggerEventHandler (user.h) - - \param[in] ifContext Stores interface data if CreateContext function - supported and implemented. - Can be used in all SlNetIf_Config_t functions - \param[in] nsds The highest-numbered file descriptor in any of the - three sets, plus 1. - \param[in,out] readsds Socket descriptors list for read monitoring and accept monitoring - \param[in,out] writesds Socket descriptors list for connect monitoring only, write monitoring is not supported - \param[in,out] exceptsds Socket descriptors list for exception monitoring, not supported. - \param[in] timeout Is an upper bound on the amount of time elapsed - before SlNetIfWifi_send() returns. Null or above 0xffff seconds means - infinity timeout. The minimum timeout is 10 milliseconds, - less than 10 milliseconds will be set automatically to 10 milliseconds. - Max microseconds supported is 0xfffc00. - In trigger mode the timeout fields must be set to zero. - - \return On success, SlNetIfWifi_send() returns the number of - file descriptors contained in the three returned - descriptor sets (that is, the total number of bits that - are set in readsds, writesds, exceptsds) which may be - zero if the timeout expires before anything interesting - happens.\n On error, a negative value is returned. - readsds - return the sockets on which Read request will - return without delay with valid data.\n - writesds - return the sockets on which Write request - will return without delay.\n - exceptsds - return the sockets closed recently. \n - SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa SlNetIfWifi_socket - \note If the timeout value set to less than 10ms it will automatically set - to 10ms to prevent overload of the system\n - - Only one SlNetIfWifi_send can be handled at a time. \b - Calling this API while the same command is called from another thread, may result - in one of the following scenarios: - 1. The command will wait (internal) until the previous command finish, and then be executed. - 2. There are not enough resources and SLNETERR_BSD_ENOMEM error will return. - In this case, MAX_CONCURRENT_ACTIONS can be increased (result in memory increase) or try - again later to issue the command. - 3. In case there is already a triggered SlNetIfWifi_send in progress, the following call will return - with SLNETSOCK_RET_CODE_SOCKET_SELECT_IN_PROGRESS_ERROR. - - \warning -*/ -int32_t SlNetIfWifi_select(void *ifContext, int16_t nfds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout); - - -/*! - \brief Set socket options- - - The SlNetIfWifi_setSockOpt function manipulate the options associated with a socket.\n - Options may exist at multiple protocol levels; they are always - present at the uppermost socket level.\n - - When manipulating socket options the level at which the option resides - and the name of the option must be specified. To manipulate options at - the socket level, level is specified as SOL_SOCKET. To manipulate - options at any other level the protocol number of the appropriate protocol - controlling the option is supplied. For example, to indicate that an - option is to be interpreted by the TCP protocol, level should be set to - the protocol number of TCP; \n - - The parameters optval and optlen are used to access opt_values - for SlNetIfWifi_setSockOpt(). For SlNetIfWifi_getSockOpt() they identify a - buffer in which the value for the requested option(s) are to - be returned. For SlNetIfWifi_getSockOpt(), optlen is a value-result - parameter, initially containing the size of the buffer - pointed to by option_value, and modified on return to - indicate the actual size of the value returned. If no option - value is to be supplied or returned, option_value may be - NULL. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] level Defines the protocol level for this option - - SLNETSOCK_LVL_SOCKET Socket level configurations (L4, transport layer) - - SLNETSOCK_LVL_IP IP level configurations (L3, network layer) - - SLNETSOCK_LVL_PHY Link level configurations (L2, link layer) - \param[in] optname Defines the option name to interrogate - - SLNETSOCK_LVL_SOCKET - - SLNETSOCK_OPSOCK_RCV_BUF \n - Sets tcp max recv window size. \n - This options takes SlNetSock_Winsize_t struct as parameter - - SLNETSOCK_OPSOCK_RCV_TIMEO \n - Sets the timeout value that specifies the maximum amount of time an input function waits until it completes. \n - Default: No timeout \n - This options takes SlNetSock_Timeval_t struct as parameter - - SLNETSOCK_OPSOCK_KEEPALIVE \n - Enable or Disable periodic keep alive. - Keeps TCP connections active by enabling the periodic transmission of messages \n - Timeout is 5 minutes.\n - Default: Enabled \n - This options takes SlNetSock_Keepalive_t struct as parameter - - SLNETSOCK_OPSOCK_KEEPALIVE_TIME \n - Set keep alive timeout. - Value is in seconds \n - Default: 5 minutes \n - - SLNETSOCK_OPSOCK_LINGER \n - Socket lingers on close pending remaining send/receive packets\n - - SLNETSOCK_OPSOCK_NON_BLOCKING \n - Sets socket to non-blocking operation Impacts: connect, accept, send, sendto, recv and recvfrom. \n - Default: Blocking. - This options takes SlNetSock_Nonblocking_t struct as parameter - - SLNETSOCK_OPSOCK_NON_IP_BOUNDARY \n - Enable or Disable rx ip boundary. - In connectionless socket (udp/raw), unread data is dropped (when SlNetIfWifi_recvfrom len parameter < data size), Enable this option in order to read the left data on the next SlNetIfWifi_recvfrom iteration - Default: Disabled, IP boundary kept, \n - This options takes SlNetSock_NonIpBoundary_t struct as parameter - - SLNETSOCK_LVL_IP - - SLNETSOCK_OPIP_MULTICAST_TTL \n - Set the time-to-live value of outgoing multicast packets for this socket. \n - This options takes uint8_t as parameter - - SLNETSOCK_OPIP_ADD_MEMBERSHIP \n - UDP socket, Join a multicast group. \n - This options takes SlNetSock_IpMreq_t struct as parameter - - SLNETSOCK_OPIP_DROP_MEMBERSHIP \n - UDP socket, Leave a multicast group \n - This options takes SlNetSock_IpMreq_t struct as parameter - - SLNETSOCK_OPIP_HDRINCL \n - RAW socket only, the IPv4 layer generates an IP header when sending a packet unless \n - the IP_HDRINCL socket option is enabled on the socket. \n - When it is enabled, the packet must contain an IP header. \n - Default: disabled, IPv4 header generated by Network Stack \n - This options takes uint32_t as parameter - - SLNETSOCK_OPIP_RAW_RX_NO_HEADER \n - Raw socket remove IP header from received data. \n - Default: data includes ip header \n - This options takes uint32_t as parameter - - SLNETSOCK_OPIP_RAW_IPV6_HDRINCL (inactive) \n - RAW socket only, the IPv6 layer generates an IP header when sending a packet unless \n - the IP_HDRINCL socket option is enabled on the socket. When it is enabled, the packet must contain an IP header \n - Default: disabled, IPv4 header generated by Network Stack \n - This options takes uint32_t as parameter - - SLNETSOCK_LVL_PHY - - SLNETSOCK_OPPHY_CHANNEL \n - Sets channel in transceiver mode. - This options takes uint32_t as channel number parameter - - SLNETSOCK_OPPHY_RATE \n - RAW socket, set WLAN PHY transmit rate \n - The values are based on SlWlanRateIndex_e \n - This options takes uint32_t as parameter - - SLNETSOCK_OPPHY_TX_POWER \n - RAW socket, set WLAN PHY TX power \n - Valid rage is 1-15 \n - This options takes uint32_t as parameter - - SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX \n - RAW socket, set number of frames to transmit in transceiver mode. - Default: 1 packet - This options takes uint32_t as parameter - - SLNETSOCK_OPPHY_PREAMBLE \n - RAW socket, set WLAN PHY preamble for Long/Short\n - This options takes uint32_t as parameter - - SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD \n - RAW socket, set WLAN Tx - Set CCA threshold. \n - The values are based on SlNetSockTxInhibitThreshold_e \n - This options takes uint32_t as parameter - - SLNETSOCK_OPPHY_TX_TIMEOUT \n - RAW socket, set WLAN Tx - changes the TX timeout (lifetime) of transceiver frames. \n - Value in Ms, maximum value is 10ms \n - This options takes uint32_t as parameter - - SLNETSOCK_OPPHY_ALLOW_ACKS \n - RAW socket, set WLAN Tx - Enable or Disable sending ACKs in transceiver mode \n - 0 = disabled / 1 = enabled \n - This options takes uint32_t as parameter - - - \param[in] optval Specifies a value for the option - \param[in] optlen Specifies the length of the - option value - - \return Zero on success, or negative error code on failure - - \par Persistent - All params are Non- Persistent - \sa SlNetIfWifi_getSockOpt - \note - \warning - \par Examples - - - SLNETSOCK_OPSOCK_RCV_BUF: - \code - SlNetSock_Winsize_t size; - size.winsize = 3000; // bytes - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_BUF, (uint8_t *)&size, sizeof(size)); - \endcode -
- - - SLNETSOCK_OPSOCK_RCV_TIMEO: - \code - struct SlNetSock_Timeval_t timeVal; - timeVal.tv_sec = 1; // Seconds - timeVal.tv_usec = 0; // Microseconds. 10000 microseconds resolution - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_TIMEO, (uint8_t *)&timeVal, sizeof(timeVal)); // Enable receive timeout - \endcode -
- - - SLNETSOCK_OPSOCK_KEEPALIVE: //disable Keepalive - \code - SlNetSock_Keepalive_t enableOption; - enableOption.keepaliveEnabled = 0; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_KEEPALIVE, (uint8_t *)&enableOption, sizeof(enableOption)); - \endcode -
- - - SLNETSOCK_OPSOCK_KEEPALIVE_TIME: //Set Keepalive timeout - \code - int16_t Status; - uint32_t TimeOut = 120; - SlNetIfWifi_setSockOpt(Sd, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_KEEPALIVE_TIME, (uint8_t *)&TimeOut, sizeof(TimeOut)); - \endcode -
- - - SLNETSOCK_OPSOCK_NON_BLOCKING: //Enable or disable nonblocking mode - \code - SlNetSock_Nonblocking_t enableOption; - enableOption.nonBlockingEnabled = 1; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_BLOCKING, (uint8_t *)&enableOption, sizeof(enableOption)); - \endcode -
- - - SLNETSOCK_OPSOCK_NON_IP_BOUNDARY: //disable boundary - \code - SlNetSock_NonIpBoundary_t enableOption; - enableOption.nonIpBoundaryEnabled = 1; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_IP_BOUNDARY, (uint8_t *)&enableOption, sizeof(enableOption)); - \endcode -
- - - SLNETSOCK_OPSOCK_LINGER: - \code - SlNetSock_linger_t linger; - linger.l_onoff = 1; - linger.l_linger = 10; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_LINGER, &linger, sizeof(linger)); - \endcode -
- - - SLNETSOCK_OPIP_MULTICAST_TTL: - \code - uint8_t ttl = 20; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_MULTICAST_TTL, &ttl, sizeof(ttl)); - \endcode -
- - - SLNETSOCK_OPIP_ADD_MEMBERSHIP: - \code - SlNetSock_IpMreq_t mreq; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_ADD_MEMBERSHIP, &mreq, sizeof(mreq)); - \endcode -
- - - SLNETSOCK_OPIP_DROP_MEMBERSHIP: - \code - SlNetSock_IpMreq_t mreq; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_DROP_MEMBERSHIP, &mreq, sizeof(mreq)); - \endcode -
- - - SLNETSOCK_OPIP_RAW_RX_NO_HEADER: - \code - uint32_t header = 1; // remove ip header - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_RAW_RX_NO_HEADER, &header, sizeof(header)); - \endcode -
- - - SLNETSOCK_OPIP_HDRINCL: - \code - uint32_t header = 1; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_HDRINCL, &header, sizeof(header)); - \endcode -
- - - SLNETSOCK_OPIP_RAW_IPV6_HDRINCL: - \code - uint32_t header = 1; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_RAW_IPV6_HDRINCL, &header, sizeof(header)); - \endcode -
- - - SLNETSOCK_OPPHY_CHANNEL: - \code - uint32_t newChannel = 6; // range is 1-13 - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPPHY_CHANNEL, &newChannel, sizeof(newChannel)); - \endcode -
- - - SLNETSOCK_OPPHY_RATE: - \code - uint32_t rate = 6; // see wlan.h SlWlanRateIndex_e for values - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_RATE, &rate, sizeof(rate)); - \endcode -
- - - SLNETSOCK_OPPHY_TX_POWER: - \code - uint32_t txpower = 1; // valid range is 1-15 - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_POWER, &txpower, sizeof(txpower)); - \endcode -
- - - SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX: - \code - uint32_t numframes = 1; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX, &numframes, sizeof(numframes)); - \endcode -
- - - SLNETSOCK_OPPHY_PREAMBLE: - \code - uint32_t preamble = 1; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_PREAMBLE, &preamble, sizeof(preamble)); - \endcode -
- - - SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD: - \code - uint32_t thrshld = SLNETSOCK_TX_INHIBIT_THRESHOLD_MED; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD , &thrshld, sizeof(thrshld)); - \endcode -
- - - SLNETSOCK_OPPHY_TX_TIMEOUT: - \code - uint32_t timeout = 50; - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_TIMEOUT , &timeout, sizeof(timeout)); - \endcode -
- - - SLNETSOCK_OPPHY_ALLOW_ACKS: - \code - uint32_t acks = 1; // 0 = disabled / 1 = enabled - SlNetIfWifi_setSockOpt(SockID, sdContext, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_ALLOW_ACKS, &acks, sizeof(acks)); - \endcode -
- -*/ -int32_t SlNetIfWifi_setSockOpt(int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen); - -/*! - \brief Get socket options - - The SlNetIfWifi_getSockOpt function gets the options associated with a socket. - Options may exist at multiple protocol levels; they are always - present at the uppermost socket level.\n - - The parameters optval and optlen identify a - buffer in which the value for the requested option(s) are to - be returned. optlen is a value-result - parameter, initially containing the size of the buffer - pointed to by option_value, and modified on return to - indicate the actual size of the value returned. If no option - value is to be supplied or returned, option_value may be - NULL. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] level Defines the protocol level for this option - \param[in] optname defines the option name to interrogate - \param[out] optval Specifies a value for the option - \param[out] optlen Specifies the length of the - option value - - \return Zero on success, or negative error code on failure - \sa SlNetIfWifi_setSockOpt - \note - \warning -*/ -int32_t SlNetIfWifi_getSockOpt(int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen); - -/*! - \brief Read data from TCP socket - - The SlNetIfWifi_recv function receives a message from a connection-mode socket - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[out] buf Points to the buffer where the - message should be stored. - \param[in] len Specifies the length in bytes of - the buffer pointed to by the buffer argument. - Range: 1-16000 bytes - \param[in] flags Upper 8 bits specifies the security flags - Lower 24 bits specifies the type of message - reception. On this version, the lower 24 bits are not - supported - - \return Return the number of bytes received, - or a negative value if an error occurred.\n - Using a non-blocking recv a possible negative value is SLNETERR_BSD_EAGAIN.\n - SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa SlNetIfWifi_recvFrom - \note - \warning - \par Examples - - - Receiving data using TCP socket: - \code - SlNetSock_AddrIn_t Addr; - SlNetSock_AddrIn_t LocalAddr; - int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); - int16_t SockID, newSockID; - int16_t Status; - int8_t Buf[RECV_BUF_LEN]; - - LocalAddr.sin_family = SLNETSOCK_AF_INET; - LocalAddr.sin_port = SlNetSock_htons(5001); - LocalAddr.sin_addr.s_addr = 0; - - Addr.sin_family = SLNETSOCK_AF_INET; - Addr.sin_port = SlNetSock_htons(5001); - Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); - - SockID = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, 0, 0, 0); - Status = SlNetIfWifi_bind(SockID, (SlNetSock_Addr_t *)&LocalAddr, AddrSize); - Status = SlNetIfWifi_listen(SockID, 0); - newSockID = SlNetIfWifi_accept(SockID, (SlNetSock_Addr_t*)&Addr, (SlNetSocklen_t*) &AddrSize); - Status = SlNetIfWifi_recv(newSockID, Buf, 1460, 0); - \endcode -
- - - Rx transceiver mode using a raw socket: - \code - int8_t buffer[1536]; - int16_t sd; - uint16_t size; - SlNetSock_TransceiverRxOverHead_t *transHeader; - sd = SlNetIfWifi_socket(SLNETSOCK_AF_RF, SLNETSOCK_SOCK_RAW, 11, 0, 0); // channel 11 - while(1) - { - size = SlNetIfWifi_recv(sd,buffer,1536,0); - transHeader = (SlNetSock_TransceiverRxOverHead_t *)buffer; - printf("RSSI is %d frame type is 0x%x size %d\n",transHeader->rssi,buffer[sizeof(SlNetSock_TransceiverRxOverHead_t)],size); - } - \endcode -*/ -int32_t SlNetIfWifi_recv(int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags); - -/*! - \brief Read data from socket - - SlNetIfWifi_recvFrom function receives a message from a connection-mode or - connectionless-mode socket - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[out] buf Points to the buffer where the message should be stored. - \param[in] len Specifies the length in bytes of the buffer pointed to by the buffer argument. - Range: 1-16000 bytes - \param[in] flags Upper 8 bits specifies the security flags - Lower 24 bits specifies the type of message - reception. On this version, the lower 24 bits are not - supported - \param[in] from Pointer to an address structure - indicating the source - address.\n sockaddr:\n - code - for the address format.\n - socket address, - the length depends on the code - format - \param[in] fromlen Source address structure - size. This parameter MUST be set to the size of the structure pointed to by addr. - - - \return Return the number of bytes received, - or a negative value if an error occurred.\n - Using a non-blocking recv a possible negative value is SLNETERR_BSD_EAGAIN. - SLNETSOCK_RET_CODE_INVALID_INPUT (-2) will be returned if fromlen has incorrect length. \n - SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - In this case try again later or increase MAX_CONCURRENT_ACTIONS - - \sa SlNetIfWifi_recv - \note - \warning - \par Example - - - Receiving data: - \code - SlNetSock_AddrIn_t Addr; - SlNetSock_AddrIn_t LocalAddr; - int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); - int16_t SockID; - int16_t Status; - int8_t Buf[RECV_BUF_LEN]; - - LocalAddr.sin_family = SLNETSOCK_AF_INET; - LocalAddr.sin_port = SlNetSock_htons(5001); - LocalAddr.sin_addr.s_addr = 0; - - SockID = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_DGRAM, 0, 0, 0); - Status = SlNetIfWifi_bind(SockID, (SlNetSock_Addr_t *)&LocalAddr, AddrSize); - Status = SlNetIfWifi_recvFrom(SockID, Buf, 1472, 0, (SlNetSock_Addr_t *)&Addr, (SlNetSocklen_t*)&AddrSize); - - \endcode -*/ -int32_t SlNetIfWifi_recvFrom(int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen); - -/*! - \brief Write data to TCP socket - - The SlNetIfWifi_send function is used to transmit a message to another socket. - Returns immediately after sending data to device. - In case of TCP failure an async event SLNETSOCK_SOCKET_TX_FAILED_EVENT is going to - be received.\n - In case of a RAW socket (transceiver mode), extra 4 bytes should be reserved at the end of the - frame data buffer for WLAN FCS - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] buf Points to a buffer containing - the message to be sent - \param[in] len Message size in bytes. Range: 1-1460 bytes - \param[in] flags Upper 8 bits specifies the security flags - Lower 24 bits specifies the type of message - reception. On this version, the lower 24 bits are not - supported for TCP. - For transceiver mode, the SLNETSOCK_WLAN_RAW_RF_TX_PARAMS macro can be used to determine - transmission parameters (channel,rate,tx_power,preamble) - - \return Zero on success, or negative error code on failure - - \sa SlNetIfWifi_sendTo - \note - \warning - \par Example - - - Sending data: - \code - SlNetSock_AddrIn_t Addr; - int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); - int16_t SockID; - int16_t Status; - int8_t Buf[SEND_BUF_LEN]; - - Addr.sin_family = SLNETSOCK_AF_INET; - Addr.sin_port = SlNetSock_htons(5001); - Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); - - SockID = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, 0, 0, 0); - Status = SlNetIfWifi_connect(SockID, (SlNetSock_Addr_t *)&Addr, AddrSize); - Status = SlNetIfWifi_send(SockID, Buf, 1460, 0 ); - \endcode -*/ -int32_t SlNetIfWifi_send(int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags); - -/*! - \brief Write data to socket - - The SlNetIfWifi_sendTo function is used to transmit a message on a connectionless socket - (connection less socket SLNETSOCK_SOCK_DGRAM, SLNETSOCK_SOCK_RAW).\n - Returns immediately after sending data to device.\n - In case of transmission failure an async event SLNETSOCK_SOCKET_TX_FAILED_EVENT is going to - be received. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] buf Points to a buffer containing - the message to be sent - \param[in] len message size in bytes. Range: 1-1460 bytes - \param[in] flags Upper 8 bits specifies the security flags - Lower 24 bits specifies the type of message - reception. On this version, the lower 24 bits are not - supported - \param[in] to Pointer to an address structure - indicating the destination - address.\n sockaddr:\n - code - for the address format.\n - socket address, - the length depends on the code - format - \param[in] tolen Destination address structure size - - \return Zero on success, or negative error code on failure - - \sa SlNetIfWifi_send - \note - \warning - \par Example - - - Sending data: - \code - SlNetSock_AddrIn_t Addr; - int16_t AddrSize = sizeof(SlNetSock_AddrIn_t); - int16_t SockID; - int16_t Status; - int8_t Buf[SEND_BUF_LEN]; - - Addr.sin_family = SLNETSOCK_AF_INET; - Addr.sin_port = SlNetSock_htons(5001); - Addr.sin_addr.s_addr = SlNetSock_htonl(SLNETSOCK_IPV4_VAL(10,1,1,200)); - - SockID = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_DGRAM, 0, 0, 0); - Status = SlNetIfWifi_sendTo(SockID, Buf, 1472, 0, (SlNetSock_Addr_t *)&Addr, AddrSize); - \endcode -*/ -int32_t SlNetIfWifi_sendTo(int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen); - - -/*! - \brief Start a security session on an opened socket - - The SlNetIfWifi_sockstartSec function is used start a security session on - an opened socket. If the security handle is NULL the session would - be started with the default security settings. - - \param[in] sd Socket descriptor (handle) - \param[in] sdContext May store socket data if implemented in the - SlNetIfWifi_socket function. - \param[in] secAttrib Secure attribute handle - \param[in] flags Specifies flags. \n - The available flags are: - - SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY - - SLNETSOCK_SEC_BIND_CONTEXT_ONLY - - SLNETSOCK_SEC_IS_SERVER - - \return Zero on success, or negative error code - on failure - - \sa - \note - \warning - \par Example - - - start security session on an opened socket: - \code - - \endcode -*/ -int32_t SlNetIfWifi_sockstartSec(int16_t sd, void *sdContext, SlNetSockSecAttrib_t *secAttrib, uint8_t flags); - - -/*! - \brief Get host IP by name\n - Obtain the IP Address of machine on network, by machine name. - - \param[in] ifContext Stores interface data if CreateContext function - supported and implemented. - Can be used in all SlNetIf_Config_t functions - \param[in] ifBitmap Specifies the interfaces which the host ip - needs to be retrieved from (according to - the priority until one of them will return - an answer).\n - The values of the interface identifiers - is defined with the prefix SLNETIF_ID_ - which defined in slnetif.h - \param[in] name Host name - \param[in] nameLen Name length - \param[out] ipAddr This parameter is filled in with - host IP addresses. In case that host name is not - resolved, out_ip_addr is zero. - \param[in,out] ipAddrLen Holds the size of the ipAddr array, when function - successful, the ipAddrLen parameter will be updated with - the number of the IP addresses found. - \param[in] family Protocol family - - \return Zero on success, or negative on failure.\n - SLNETUTIL_POOL_IS_EMPTY may be return in case - there are no resources in the system\n - In this case try again later or increase - MAX_CONCURRENT_ACTIONS - Possible DNS error codes: - - SLNETUTIL_DNS_QUERY_NO_RESPONSE - - SLNETUTIL_DNS_NO_SERVER - - SLNETUTIL_DNS_QUERY_FAILED - - SLNETUTIL_DNS_MALFORMED_PACKET - - SLNETUTIL_DNS_MISMATCHED_RESPONSE - - \sa - \note Only one sl_NetAppDnsGetHostByName can be handled at a time.\n - Calling this API while the same command is called from another - thread, may result in one of the two scenarios: - 1. The command will wait (internal) until the previous command - finish, and then be executed. - 2. There are not enough resources and POOL_IS_EMPTY error will - return.\n - In this case, MAX_CONCURRENT_ACTIONS can be increased (result - in memory increase) or try again later to issue the command. - \warning - In case an IP address in a string format is set as input, without - any prefix (e.g. "1.2.3.4") the device will not try to access the - DNS and it will return the input address on the 'out_ip_addr' field - \par Example - - Getting host by name: - \code - uint16_t DestIPListSize = 1; - uint32_t DestIP[1]; - uint32_t ifID; - int16_t SockId; - SlNetSock_AddrIn_t LocalAddr; //address of the server to connect to - int32_t LocalAddrSize; - - SlNetIfWifi_getHostByName(0, "www.google.com", strlen("www.google.com"), (uint32_t *)DestIP, &DestIPListSize, SLNETSOCK_PF_INET); - - LocalAddr.sin_family = SLNETSOCK_AF_INET; - LocalAddr.sin_addr.s_addr = SlNetUtil_htonl(DestIP[0]); - LocalAddr.sin_port = SlNetUtil_htons(80); - LocalAddrSize = sizeof(SlNetSock_AddrIn_t); - - SockId = SlNetIfWifi_socket(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, ifID, 0); - - if (SockId >= 0) - { - status = SlNetIfWifi_connect(SockId, (SlNetSock_Addr_t *) &LocalAddr, LocalAddrSize); - } - \endcode -*/ -int32_t SlNetIfWifi_getHostByName(void *ifContext, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family); - - -/*! - \brief Get IP Address of specific interface - - The SlNetIfWifi_getIPAddr function retrieve the IP address of a specific - interface according to the Address Type, IPv4, IPv6 LOCAL - or IPv6 GLOBAL.\n - - \n - - \param[in] ifContext Stores interface data if CreateContext function - supported and implemented. - Can be used in all SlNetIf_Config_t functions - \param[in] ifID Specifies the interface which its connection - state needs to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - \param[in] addrType Address type: - - SLNETIF_IPV4_ADDR - - SLNETIF_IPV6_ADDR_LOCAL - - SLNETIF_IPV6_ADDR_GLOBAL - \param[out] addrConfig Address config: - - SLNETIF_ADDR_CFG_UNKNOWN - - SLNETIF_ADDR_CFG_DHCP - - SLNETIF_ADDR_CFG_DHCP_LLA - - SLNETIF_ADDR_CFG_STATIC - - SLNETIF_ADDR_CFG_STATELESS - - SLNETIF_ADDR_CFG_STATEFUL - \param[out] ipAddr IP Address according to the Address Type - - \return Zero on success, or negative error code on failure - - \sa SlNetIfAddressType_e - \note - \warning - \par Examples - - \code - SlNetSock_In6Addr_t IPAdd; - uint16_t addressConfig = 0; - SlNetIfWifi_getIPAddr(SLNETIF_ID_1 ,SLNETIF_IPV6_ADDR_LOCAL ,&addressConfig ,(uint8_t *)ipAddr); - \endcode -
-*/ -int32_t SlNetIfWifi_getIPAddr(void *ifContext, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr); - - -/*! - \brief Get interface connection status - - The SlNetIfWifi_getConnectionStatus function gets the connection status of the - interface (connected Or disconnected).\n - - \param[in] ifContext Stores interface data if CreateContext function - supported and implemented. - Can be used in all SlNetIf_Config_t functions - - \return Connection status of the interface on success, - or negative error code on failure - - \sa - \note - \warning - \par Examples - - \code - int16_t connection_status - connection_status = SlNetIfWifi_getConnectionStatus(); - \endcode -
-*/ -int32_t SlNetIfWifi_getConnectionStatus(void *ifContext); - - -/*! - \brief Load secured buffer to the network stack - - The SlNetSock_secLoadObj function loads buffer/files into the inputted - network stack for future usage of the socket SSL/TLS connection. - This option is relevant for network stacks with file system and also for - network stacks that lack file system that can store the secured files. - - \param[in] ifContext Stores interface data if CreateContext function - supported and implemented. - Can be used in all SlNetIf_Config_t functions - \param[in] objType Specifies the security object type which - could be one of the following:\n - - SLNETIF_SEC_OBJ_TYPE_RSA_PRIVATE_KEY - - SLNETIF_SEC_OBJ_TYPE_CERTIFICATE - - SLNETIF_SEC_OBJ_TYPE_DH_KEY - \param[in] objName Specifies the name/input identifier of the - secured buffer loaded - for file systems - this can be the file name - for plain text buffer loading this can be the - name of the object - \param[in] objNameLen Specifies the buffer name length to be loaded.\n - \param[in] objBuff Specifies the pointer to the secured buffer to - be loaded.\n - \param[in] objBuffLen Specifies the buffer length to be loaded.\n - - \return On success, buffer type handler index to be - used when attaching the secured buffer to a - socket.\n - A successful return code should be a positive - number (int16)\n - On error, a negative value will be returned - specifying the error code. - - SLNETERR_STATUS_ERROR - load operation failed - - \sa SlNetIfWifi_setSockOpt - \note - \warning -*/ -int32_t SlNetIfWifi_loadSecObj(void *ifContext, uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen); - - -/*! - \brief Allocate and store interface data - - The SlNetIfWifi_CreateContext function stores interface related data.\n - - \param[in] ifContext Allocate and store interface data if needed. - Can be used in all slnetwifi interface functions - - \return Zero on success, or negative error code on failure. - - \sa - \note - \warning - \par Examples - - \code - void *ifContext; - connection_status = SlNetIfWifi_CreateContext(&context); - \endcode -
-*/ -int32_t SlNetIfWifi_CreateContext(uint16_t ifID, const char *ifName, void **ifContext); - - -/*! - - Close the Doxygen group. - @} - - */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __SOCKET_H__ */ - - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/device.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/device.c deleted file mode 100644 index 217dacf4217..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/device.c +++ /dev/null @@ -1,768 +0,0 @@ -/* - * device.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include -#include - -/*****************************************************************************/ -/* Internal functions */ -/*****************************************************************************/ - -static _i16 _SlDeviceGetStartResponseConvert(_i32 Status); -void _SlDeviceHandleResetRequestInternally(void); -void _SlDeviceResetRequestInitCompletedCB(_u32 Status, SlDeviceInitInfo_t *DeviceInitInfo); - -#define RESET_REQUEST_STOP_TIMEOUT (300) - -#ifndef SL_IF_OPEN_FLAGS -#define SL_IF_OPEN_FLAGS (0x0) -#endif - -#ifndef SL_IF_UART_REOPEN_FLAGS -#define SL_IF_UART_REOPEN_FLAGS (0x1) -#endif - -typedef struct -{ - const void *pIfHdl; /* Holds the last opened interface handle */ - _i8 *pDevName; /* Holds the last opened interface parameters */ - _u32 ResetRequestSessionNumber; /* Special session number to be verified upon every reset request during provisioning */ -} _SlDeviceCb_t; - -_SlDeviceCb_t DeviceCB; /* the device control block */ - -static const _i16 StartResponseLUT[16] = -{ - ROLE_RESERVED, - ROLE_STA, - SL_ERROR_ROLE_STA_ERR, - ROLE_AP, - SL_ERROR_ROLE_AP_ERR, - ROLE_P2P, - SL_ERROR_ROLE_P2P_ERR, - SL_ERROR_CALIB_FAIL, - SL_ERROR_FS_CORRUPTED_ERR, - SL_ERROR_FS_ALERT_ERR, - SL_ERROR_RESTORE_IMAGE_COMPLETE, - SL_ERROR_INCOMPLETE_PROGRAMMING, - ROLE_TAG, - SL_ERROR_ROLE_TAG_ERR, - SL_ERROR_FIPS_ERR, - SL_ERROR_GENERAL_ERR -}; - -static _i16 _SlDeviceGetStartResponseConvert(_i32 Status) -{ - return StartResponseLUT[Status & 0xF]; -} - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* sl_Task */ -/*****************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_Task) -void* sl_Task(void* pEntry) -{ -#ifdef _SlTaskEntry - return (void*)_SlTaskEntry(); -#else - return (void*)0; -#endif -} -#endif - -/*****************************************************************************/ -/* sl_Start */ -/*****************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_Start) -_i16 sl_Start(const void* pIfHdl, _i8* pDevName, const P_INIT_CALLBACK pInitCallBack) -{ - _u8 ObjIdx = MAX_CONCURRENT_ACTIONS; - InitComplete_t AsyncRsp; - - _SlDrvMemZero(&AsyncRsp, sizeof(InitComplete_t)); - - /* verify no error handling in progress. if in progress than - ignore the API execution and return immediately with an error */ - VERIFY_NO_ERROR_HANDLING_IN_PROGRESS(); - if (SL_IS_DEVICE_STARTED) - { - return SL_RET_CODE_DEV_ALREADY_STARTED; - } - /* Perform any preprocessing before enable networking services */ -#ifdef sl_DeviceEnablePreamble - sl_DeviceEnablePreamble(); -#endif - - /* ControlBlock init */ - (void)_SlDrvDriverCBInit(); - - /* open the interface: usually SPI or UART */ - if (NULL == pIfHdl) - { - g_pCB->FD = sl_IfOpen((void *)pDevName, SL_IF_OPEN_FLAGS); - } - else - { - g_pCB->FD = (_SlFd_t)pIfHdl; - } - - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8 *)&AsyncRsp, START_STOP_ID, SL_MAX_SOCKETS); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - if( g_pCB->FD >= (_SlFd_t)0) - { - /* store the interface parameters for the internal call of the - sl_start to be called upon reset request handling */ - DeviceCB.pIfHdl = pIfHdl; - DeviceCB.pDevName = pDevName; - - /* Mark that device is in progress! */ - SL_SET_DEVICE_START_IN_PROGRESS; - - sl_DeviceDisable(); - - sl_IfRegIntHdlr((SL_P_EVENT_HANDLER)_SlDrvRxIrqHandler, NULL); - - g_pCB->pInitCallback = pInitCallBack; - sl_DeviceEnable(); - - if (NULL == pInitCallBack) - { - - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, INIT_COMPLETE_TIMEOUT, SL_OPCODE_DEVICE_INITCOMPLETE)); - - SL_UNSET_DEVICE_START_IN_PROGRESS; - - SL_SET_DEVICE_STARTED; - - /* release Pool Object */ - _SlDrvReleasePoolObj(g_pCB->FunctionParams.AsyncExt.ActionIndex); - return _SlDeviceGetStartResponseConvert(AsyncRsp.Status); - } - else - { - return SL_RET_CODE_OK; - } - } - return SL_BAD_INTERFACE; -} -#endif - -/*************************************************************************** -_SlDeviceHandleAsync_InitComplete - handles init complete signalling to -a waiting object -****************************************************************************/ -_SlReturnVal_t _SlDeviceHandleAsync_InitComplete(void *pVoidBuf) -{ - InitComplete_t *pMsgArgs = (InitComplete_t *)_SL_RESP_ARGS_START(pVoidBuf); - SlDeviceInitInfo_t DeviceInitInfo; - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - if(g_pCB->pInitCallback) - { - DeviceInitInfo.ChipId = pMsgArgs->ChipId; - DeviceInitInfo.MoreData = pMsgArgs->MoreData; - g_pCB->pInitCallback(_SlDeviceGetStartResponseConvert(pMsgArgs->Status), &DeviceInitInfo); - } - else - { - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(InitComplete_t)); - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - } - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - if(g_pCB->pInitCallback) - { - SL_SET_DEVICE_STARTED; - SL_UNSET_DEVICE_START_IN_PROGRESS; - _SlDrvReleasePoolObj(g_pCB->FunctionParams.AsyncExt.ActionIndex); - } - - return SL_OS_RET_CODE_OK; - } - - -/*************************************************************************** -_SlDeviceHandleAsync_Stop - handles stop signalling to -a waiting object -****************************************************************************/ -void _SlDeviceHandleAsync_Stop(void *pVoidBuf) -{ - _BasicResponse_t *pMsgArgs = (_BasicResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - - VERIFY_SOCKET_CB(NULL != g_pCB->StopCB.pAsyncRsp); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - if (g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs != NULL) - { - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(_BasicResponse_t)); - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - } - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return; -} - - -/***************************************************************************** -sl_stop -******************************************************************************/ -typedef union -{ - SlDeviceStopCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlStopMsg_u; - -static const _SlCmdCtrl_t _SlStopCmdCtrl = -{ - SL_OPCODE_DEVICE_STOP_COMMAND, - (_SlArgSize_t)sizeof(SlDeviceStopCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -#if _SL_INCLUDE_FUNC(sl_Stop) -_i16 sl_Stop(const _u16 Timeout) -{ - _i16 RetVal=0; - _SlStopMsg_u Msg; - _BasicResponse_t AsyncRsp; - _u8 ObjIdx = MAX_CONCURRENT_ACTIONS; - _u8 ReleasePoolObject = FALSE; - _u8 IsProvInProgress = FALSE; - - /* NOTE: don't check VERIFY_API_ALLOWED(), this command is not - * filtered in error handling and also not filtered in NWP lock state. - * If we are in the middle of assert handling than ignore stopping - * the device with timeout and force immediate shutdown as we would like - * to avoid any additional commands to the NWP */ - if( (Timeout != 0) && (SL_IS_DEVICE_STARTED) - && (!SL_IS_RESTART_REQUIRED)) - { - /* Clear the Async response structure */ - _SlDrvMemZero(&AsyncRsp, sizeof(_BasicResponse_t)); - - /* let the device make the shutdown using the defined timeout */ - Msg.Cmd.Timeout = Timeout; - - IsProvInProgress = SL_IS_PROVISIONING_IN_PROGRESS; - - /* if provisioning in progress do not take pool object as we are not going to wait for it */ - if (!IsProvInProgress) - { - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8 *)&AsyncRsp, START_STOP_ID, SL_MAX_SOCKETS); - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - ReleasePoolObject = TRUE; - } - - /* Set the stop-in-progress flag */ - SL_SET_DEVICE_STOP_IN_PROGRESS; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlStopCmdCtrl, &Msg, NULL)); - - /* Do not wait for stop async event if provisioning is in progress */ - if((SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status) && (!(IsProvInProgress))) - { - /* Wait for sync object to be signaled */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, STOP_DEVICE_TIMEOUT, SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE)); - Msg.Rsp.status = AsyncRsp.status; - RetVal = Msg.Rsp.status; - } - - /* Release pool object only if taken */ - if (ReleasePoolObject == TRUE) - { - _SlDrvReleasePoolObj(ObjIdx); - } - - /* This macro wait for the NWP to raise a ready for shutdown indication. - * This function is unique for the CC32XX family, and expected to return - * in less than 600 mSec, which is the time takes for NWP to gracefully shutdown. */ - WAIT_NWP_SHUTDOWN_READY; - } - else - { - if ((!SL_IS_DEVICE_STARTED) - && (!SL_IS_RESTART_REQUIRED)) - { - sl_DeviceDisable(); - return SL_RET_CODE_DEV_NOT_STARTED; - } - /* Set the stop-in-progress flag */ - SL_SET_DEVICE_STOP_IN_PROGRESS; - } - /* Release (signal) all active and pending commands */ - _SlDrvReleaseAllActivePendingPoolObj(); - -#ifdef SL_PLATFORM_MULTI_THREADED - /* Do not continue until all sync object deleted (in relevant context) */ - while (g_pCB->NumOfDeletedSyncObj < MAX_CONCURRENT_ACTIONS) - { - usleep(100000); - } -#endif - - /* Lock during stopping the interface */ - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_NONE); - - sl_IfRegIntHdlr(NULL, NULL); - sl_DeviceDisable(); - RetVal = sl_IfClose(g_pCB->FD); - - (void)_SlDrvDriverCBDeinit(); - - /* clear the stop-in-progress flag */ - SL_UNSET_DEVICE_STOP_IN_PROGRESS; - - /* clear the device started flag */ - SL_UNSET_DEVICE_STARTED; - - SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); - - return RetVal; -} -#endif - - -/***************************************************************************** -sl_DeviceEventMaskSet -*****************************************************************************/ -typedef union -{ - SlDeviceMaskEventSetCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlEventMaskSetMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_DeviceEventMaskSet) - -static const _SlCmdCtrl_t _SlEventMaskSetCmdCtrl = -{ - SL_OPCODE_DEVICE_EVENTMASKSET, - (_SlArgSize_t)sizeof(SlDeviceMaskEventSetCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - - -_i16 sl_DeviceEventMaskSet(const _u8 EventClass ,const _u32 Mask) -{ - _SlEventMaskSetMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_DEVICE); - - Msg.Cmd.Group = EventClass; - Msg.Cmd.Mask = Mask; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlEventMaskSetCmdCtrl, &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/****************************************************************************** -sl_EventMaskGet -******************************************************************************/ -typedef union -{ - SlDeviceMaskEventGetCommand_t Cmd; - SlDeviceMaskEventGetResponse_t Rsp; -}_SlEventMaskGetMsg_u; - - - -#if _SL_INCLUDE_FUNC(sl_DeviceEventMaskGet) - -static const _SlCmdCtrl_t _SlEventMaskGetCmdCtrl = -{ - SL_OPCODE_DEVICE_EVENTMASKGET, - (_SlArgSize_t)sizeof(SlDeviceMaskEventGetCommand_t), - (_SlArgSize_t)sizeof(SlDeviceMaskEventGetResponse_t) -}; - - -_i16 sl_DeviceEventMaskGet(const _u8 EventClass,_u32 *pMask) -{ - _SlEventMaskGetMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_DEVICE); - - Msg.Cmd.Group = EventClass; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlEventMaskGetCmdCtrl, &Msg, NULL)); - - *pMask = Msg.Rsp.Mask; - - return SL_RET_CODE_OK; -} -#endif - - - -/****************************************************************************** -sl_DeviceGet -******************************************************************************/ - -typedef union -{ - SlDeviceSetGet_t Cmd; - SlDeviceSetGet_t Rsp; -}_SlDeviceMsgGet_u; - - - -#if _SL_INCLUDE_FUNC(sl_DeviceGet) - -static const _SlCmdCtrl_t _SlDeviceGetCmdCtrl = -{ - SL_OPCODE_DEVICE_DEVICEGET, - (_SlArgSize_t)sizeof(SlDeviceSetGet_t), - (_SlArgSize_t)sizeof(SlDeviceSetGet_t) -}; - -_i16 sl_DeviceGet(const _u8 DeviceGetId, _u8 *pOption,_u16 *pConfigLen, _u8 *pValues) -{ - _SlDeviceMsgGet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_DEVICE); - - if (*pConfigLen == 0) - { - return SL_EZEROLEN; - } - - if( pOption ) - { - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)*pConfigLen; - CmdExt.pRxPayload = (_u8 *)pValues; - - Msg.Cmd.DeviceSetId = DeviceGetId; - - Msg.Cmd.Option = (_u16)*pOption; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlDeviceGetCmdCtrl, &Msg, &CmdExt)); - - if( pOption ) - { - *pOption = (_u8)Msg.Rsp.Option; - } - - if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *pConfigLen = (_u16)CmdExt.RxPayloadLen; - - return SL_ESMALLBUF; - } - else - { - *pConfigLen = (_u16)CmdExt.ActualRxPayloadLen; - } - - return (_i16)Msg.Rsp.Status; - } - else - { - return SL_RET_CODE_INVALID_INPUT; - } -} -#endif - -/****************************************************************************** -sl_DeviceSet -******************************************************************************/ -typedef union -{ - SlDeviceSetGet_t Cmd; - _BasicResponse_t Rsp; -}_SlDeviceMsgSet_u; - - - -#if _SL_INCLUDE_FUNC(sl_DeviceSet) - -static const _SlCmdCtrl_t _SlDeviceSetCmdCtrl = -{ - SL_OPCODE_DEVICE_DEVICESET, - (_SlArgSize_t)sizeof(SlDeviceSetGet_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_DeviceSet(const _u8 DeviceSetId ,const _u8 Option,const _u16 ConfigLen,const _u8 *pValues) -{ - _SlDeviceMsgSet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_DEVICE); - - _SlDrvResetCmdExt(&CmdExt); - - CmdExt.TxPayload1Len = (ConfigLen+3) & (~3); - CmdExt.pTxPayload1 = (_u8 *)pValues; - - Msg.Cmd.DeviceSetId = DeviceSetId; - Msg.Cmd.ConfigLen = ConfigLen; - Msg.Cmd.Option = Option; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlDeviceSetCmdCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.status; -} -#endif - - -/****************************************************************************** -_SlDeviceEventHandler - handles internally device async events -******************************************************************************/ -_SlReturnVal_t _SlDeviceEventHandler(void* pEventInfo) -{ - DeviceEventInfo_t* pInfo = (DeviceEventInfo_t*)pEventInfo; - _SlResponseHeader_t* pHdr = (_SlResponseHeader_t *)pInfo->pAsyncMsgBuff; - _BasicResponse_t *pMsgArgs = (_BasicResponse_t *)_SL_RESP_ARGS_START(pHdr); - SlDeviceEvent_t DeviceEvent; - - _SlDrvMemZero(&DeviceEvent, sizeof(DeviceEvent)); - - switch(pHdr->GenHeader.Opcode) - { - case SL_OPCODE_DEVICE_INITCOMPLETE: - _SlDeviceHandleAsync_InitComplete(pHdr); - break; - case SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE: - _SlDeviceHandleAsync_Stop(pHdr); - break; - case SL_OPCODE_DEVICE_RESET_REQUEST_ASYNC_EVENT: - { - SlDeviceResetRequestData_t *pResetRequestData = (SlDeviceResetRequestData_t*)pMsgArgs; - -#if defined(slcb_DeviceGeneralEvtHdlr) || defined (EXT_LIB_REGISTERED_GENERAL_EVENTS) - if (pResetRequestData->Caller == SL_DEVICE_RESET_REQUEST_CALLER_PROVISIONING_EXTERNAL_CONFIGURATION) - { - /* call the registered events handlers (application/external lib) */ - DeviceEvent.Id = SL_DEVICE_EVENT_RESET_REQUEST; - DeviceEvent.Data.ResetRequest.Status = 0; - DeviceEvent.Data.ResetRequest.Caller = pResetRequestData->Caller; - _SlDrvHandleGeneralEvents(&DeviceEvent); - break; - } -#endif - - if (!_SlDrvIsApiInProgress() && SL_IS_PROVISIONING_IN_PROGRESS) - { - if (pResetRequestData->SessionNumber != DeviceCB.ResetRequestSessionNumber) - { - /* store the last session number */ - DeviceCB.ResetRequestSessionNumber = pResetRequestData->SessionNumber; - - /* perform the reset request */ - _SlDeviceHandleResetRequestInternally(); - } - } - } - break; - - case SL_OPCODE_DEVICE_ABORT: - { - /* release global lock of cmd context */ - if (pInfo->bInCmdContext == TRUE) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - } - - _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_DEVICE_ABORT, - *((_u32*)pMsgArgs - 1), /* Abort type */ - *((_u32*)pMsgArgs)); /* Abort data */ - } - break; - - case SL_OPCODE_DEVICE_DEVICE_ASYNC_GENERAL_ERROR: - { -#if defined(slcb_DeviceGeneralEvtHdlr) || defined (EXT_LIB_REGISTERED_GENERAL_EVENTS) - - DeviceEvent.Id = SL_DEVICE_EVENT_ERROR; - DeviceEvent.Data.Error.Code = pMsgArgs->status; - DeviceEvent.Data.Error.Source = (SlDeviceSource_e)pMsgArgs->sender; - _SlDrvHandleGeneralEvents(&DeviceEvent); -#endif - } - break; - - case SL_OPCODE_DEVICE_FLOW_CTRL_ASYNC_EVENT: - _SlFlowContSet((void *)pHdr); - break; - default: - SL_ERROR_TRACE2(MSG_306, "ASSERT: _SlDeviceEventHandler : invalid opcode = 0x%x = %1", pHdr->GenHeader.Opcode, pHdr->GenHeader.Opcode); - } - - return SL_OS_RET_CODE_OK; -} - - -void _SlDeviceResetRequestInitCompletedCB(_u32 Status, SlDeviceInitInfo_t *DeviceInitInfo) -{ - /* Do nothing...*/ -} - - -void _SlDeviceHandleResetRequestInternally(void) -{ - _u8 irqCountLast = RxIrqCnt; -#if (defined(slcb_GetTimestamp)) - _SlTimeoutParams_t TimeoutInfo={0}; - - _SlDrvStartMeasureTimeout(&TimeoutInfo, 2*RESET_REQUEST_STOP_TIMEOUT); -#endif - - /* Here we send stop command with timeout, but the API will not blocked - Till the stop complete event is received as we in the middle of async event handling */ - sl_Stop(RESET_REQUEST_STOP_TIMEOUT); - - /* wait till the stop complete cmd & async - event messages are received (2 Irqs) */ - do - { -#if (defined(slcb_GetTimestamp)) - if (_SlDrvIsTimeoutExpired(&TimeoutInfo)) - { - break; - } -#endif - } - while((RxIrqCnt - irqCountLast) < 2); - - /* start the device again */ - sl_Start(DeviceCB.pIfHdl, DeviceCB.pDevName ,_SlDeviceResetRequestInitCompletedCB); - -} - - -/****************************************************************************** -sl_DeviceUartSetMode -******************************************************************************/ -#ifdef SL_IF_TYPE_UART -typedef union -{ - SlDeviceUartSetModeCommand_t Cmd; - SlDeviceUartSetModeResponse_t Rsp; -}_SlUartSetModeMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_DeviceUartSetMode) - - -const _SlCmdCtrl_t _SlUartSetModeCmdCtrl = -{ - SL_OPCODE_DEVICE_SETUARTMODECOMMAND, - (_SlArgSize_t)sizeof(SlDeviceUartSetModeCommand_t), - (_SlArgSize_t)sizeof(SlDeviceUartSetModeResponse_t) -}; - -_i16 sl_DeviceUartSetMode(const SlDeviceUartIfParams_t *pUartParams) -{ - _SlUartSetModeMsg_u Msg; - _u32 magicCode = (_u32)0xFFFFFFFF; - - Msg.Cmd.BaudRate = pUartParams->BaudRate; - Msg.Cmd.FlowControlEnable = pUartParams->FlowControlEnable; - - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlUartSetModeCmdCtrl, &Msg, NULL)); - - /* cmd response OK, we can continue with the handshake */ - if (SL_RET_CODE_OK == Msg.Rsp.status) - { - sl_IfMaskIntHdlr(); - - /* Close the comm port */ - sl_IfClose(g_pCB->FD); - - /* Re-open the comm port */ - sl_IfOpen((void * )pUartParams, SL_IF_UART_REOPEN_FLAGS); - - sl_IfUnMaskIntHdlr(); - - /* send the magic code and wait for the response */ - sl_IfWrite(g_pCB->FD, (_u8* )&magicCode, 4); - - magicCode = UART_SET_MODE_MAGIC_CODE; - sl_IfWrite(g_pCB->FD, (_u8* )&magicCode, 4); - - /* clear magic code */ - magicCode = 0; - - /* wait (blocking) till the magic code to be returned from device */ - sl_IfRead(g_pCB->FD, (_u8* )&magicCode, 4); - - /* check for the received magic code matching */ - if (UART_SET_MODE_MAGIC_CODE != magicCode) - { - _SL_ASSERT(0); - } - } - - return (_i16)Msg.Rsp.status; -} -#endif -#endif - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/driver.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/driver.c deleted file mode 100644 index 5e2131f20b8..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/driver.c +++ /dev/null @@ -1,3179 +0,0 @@ -/* - * driver.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include -#include -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#ifndef SL_PLATFORM_MULTI_THREADED - -#define GLOBAL_LOCK_CONTEXT_OWNER_APP (1) -#define GLOBAL_LOCK_CONTEXT_OWNER_SPAWN (2) - -_u8 gGlobalLockContextOwner = GLOBAL_LOCK_CONTEXT_OWNER_APP; - -#endif - -_u8 gGlobalLockCntRequested=0; -_u8 gGlobalLockCntReleased=0; - - -/* static functions declaration */ -static void _SlDrvUpdateApiInProgress(_i8 Value); - -#define API_IN_PROGRESS_UPDATE_NONE (0) -#define API_IN_PROGRESS_UPDATE_INCREMENT (1) -#define API_IN_PROGRESS_UPDATE_DECREMENT (-1) - - -/* 2 LSB of the N2H_SYNC_PATTERN are for sequence number -only in SPI interface -support backward sync pattern */ -#define N2H_SYNC_PATTERN_SEQ_NUM_BITS ((_u32)0x00000003) /* Bits 0..1 - use the 2 LBS for seq num */ -#define N2H_SYNC_PATTERN_SEQ_NUM_EXISTS ((_u32)0x00000004) /* Bit 2 - sign that sequence number exists in the sync pattern */ -#define N2H_SYNC_PATTERN_MASK ((_u32)0xFFFFFFF8) /* Bits 3..31 - constant SYNC PATTERN */ -#define N2H_SYNC_SPI_BUGS_MASK ((_u32)0x7FFF7F7F) /* Bits 7,15,31 - ignore the SPI (8,16,32 bites bus) error bits */ -#define BUF_SYNC_SPIM(pBuf) ((*(_u32 *)(pBuf)) & N2H_SYNC_SPI_BUGS_MASK) - -#define N2H_SYNC_SPIM (N2H_SYNC_PATTERN & N2H_SYNC_SPI_BUGS_MASK) -#define N2H_SYNC_SPIM_WITH_SEQ(TxSeqNum) ((N2H_SYNC_SPIM & N2H_SYNC_PATTERN_MASK) | N2H_SYNC_PATTERN_SEQ_NUM_EXISTS | ((TxSeqNum) & (N2H_SYNC_PATTERN_SEQ_NUM_BITS))) -#define MATCH_WOUT_SEQ_NUM(pBuf) ( BUF_SYNC_SPIM(pBuf) == N2H_SYNC_SPIM ) -#define MATCH_WITH_SEQ_NUM(pBuf, TxSeqNum) ( BUF_SYNC_SPIM(pBuf) == (N2H_SYNC_SPIM_WITH_SEQ(TxSeqNum)) ) -#define N2H_SYNC_PATTERN_MATCH(pBuf, TxSeqNum) \ - ( \ - ( (*((_u32 *)pBuf) & N2H_SYNC_PATTERN_SEQ_NUM_EXISTS) && ( MATCH_WITH_SEQ_NUM(pBuf, TxSeqNum) ) ) || \ - ( !(*((_u32 *)pBuf) & N2H_SYNC_PATTERN_SEQ_NUM_EXISTS) && ( MATCH_WOUT_SEQ_NUM(pBuf ) ) ) \ - ) - -#define OPCODE(_ptr) (((_SlResponseHeader_t *)(_ptr))->GenHeader.Opcode) -#define RSP_PAYLOAD_LEN(_ptr) (((_SlResponseHeader_t *)(_ptr))->GenHeader.Len - _SL_RESP_SPEC_HDR_SIZE) -#define SD(_ptr) (((SlSocketAddrResponse_u *)(_ptr))->IpV4.Sd) -/* Actual size of Recv/Recvfrom response data */ -#define ACT_DATA_SIZE(_ptr) (((SlSocketAddrResponse_u *)(_ptr))->IpV4.StatusOrLen) - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) -#define MULTI_SELECT_MASK (~(1 << SELECT_ID)) -#else -#define MULTI_SELECT_MASK (0xFFFFFFFF) -#endif -/* Internal function prototype declaration */ - - -/* General Events handling*/ -#if defined (EXT_LIB_REGISTERED_GENERAL_EVENTS) - -typedef _SlEventPropogationStatus_e (*general_callback) (SlDeviceEvent_t *); - -static const general_callback general_callbacks[] = -{ -#ifdef SlExtLib1GeneralEventHandler - SlExtLib1GeneralEventHandler, -#endif - -#ifdef SlExtLib2GeneralEventHandler - SlExtLib2GeneralEventHandler, -#endif - -#ifdef SlExtLib3GeneralEventHandler - SlExtLib3GeneralEventHandler, -#endif - -#ifdef SlExtLib4GeneralEventHandler - SlExtLib4GeneralEventHandler, -#endif - -#ifdef SlExtLib5GeneralEventHandler - SlExtLib5GeneralEventHandler, -#endif -}; - -#undef _SlDrvHandleGeneralEvents - -/******************************************************************** - _SlDrvHandleGeneralEvents - Iterates through all the general(device) event handlers which are - registered by the external libs/user application. -*********************************************************************/ -void _SlDrvHandleGeneralEvents(SlDeviceEvent_t *slGeneralEvent) -{ - _u8 i; - - /* Iterate over all the extenal libs handlers */ - for ( i = 0 ; i < sizeof(general_callbacks)/sizeof(general_callbacks[0]) ; i++ ) - { - if (EVENT_PROPAGATION_BLOCK == general_callbacks[i](slGeneralEvent) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_DeviceGeneralEvtHdlr - slcb_DeviceGeneralEvtHdlr(slGeneralEvent); -#endif - -} -#endif - - -/* WLAN Events handling*/ - -#if defined (EXT_LIB_REGISTERED_WLAN_EVENTS) - -typedef _SlEventPropogationStatus_e (*wlan_callback) (SlWlanEvent_t *); - -static wlan_callback wlan_callbacks[] = -{ -#ifdef SlExtLib1WlanEventHandler - SlExtLib1WlanEventHandler, -#endif - -#ifdef SlExtLib2WlanEventHandler - SlExtLib2WlanEventHandler, -#endif - -#ifdef SlExtLib3WlanEventHandler - SlExtLib3WlanEventHandler, -#endif - -#ifdef SlExtLib4WlanEventHandler - SlExtLib4WlanEventHandler, -#endif - -#ifdef SlExtLib5WlanEventHandler - SlExtLib5WlanEventHandler, -#endif -}; - -#undef _SlDrvHandleWlanEvents - -/*********************************************************** - _SlDrvHandleWlanEvents - Iterates through all the wlan event handlers which are - registered by the external libs/user application. -************************************************************/ -void _SlDrvHandleWlanEvents(SlWlanEvent_t *slWlanEvent) -{ - _u8 i; - - /* Iterate over all the extenal libs handlers */ - for ( i = 0 ; i < sizeof(wlan_callbacks)/sizeof(wlan_callbacks[0]) ; i++ ) - { - if ( EVENT_PROPAGATION_BLOCK == wlan_callbacks[i](slWlanEvent) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_WlanEvtHdlr - slcb_WlanEvtHdlr(slWlanEvent); -#endif - -} -#endif - - -/* NetApp Events handling */ -#if defined (EXT_LIB_REGISTERED_NETAPP_EVENTS) - -typedef _SlEventPropogationStatus_e (*netApp_callback) (SlNetAppEvent_t *); - -static const netApp_callback netApp_callbacks[] = -{ -#ifdef SlExtLib1NetAppEventHandler - SlExtLib1NetAppEventHandler, -#endif - -#ifdef SlExtLib2NetAppEventHandler - SlExtLib2NetAppEventHandler, -#endif - -#ifdef SlExtLib3NetAppEventHandler - SlExtLib3NetAppEventHandler, -#endif - -#ifdef SlExtLib4NetAppEventHandler - SlExtLib4NetAppEventHandler, -#endif - -#ifdef SlExtLib5NetAppEventHandler - SlExtLib5NetAppEventHandler, -#endif -}; - -#undef _SlDrvHandleNetAppEvents - -/************************************************************ - _SlDrvHandleNetAppEvents - Iterates through all the net app event handlers which are - registered by the external libs/user application. -************************************************************/ -void _SlDrvHandleNetAppEvents(SlNetAppEvent_t *slNetAppEvent) -{ - _u8 i; - - /* Iterate over all the extenal libs handlers */ - for ( i = 0 ; i < sizeof(netApp_callbacks)/sizeof(netApp_callbacks[0]) ; i++ ) - { - if (EVENT_PROPAGATION_BLOCK == netApp_callbacks[i](slNetAppEvent) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_NetAppEvtHdlr - slcb_NetAppEvtHdlr(slNetAppEvent); -#endif - -} -#endif - - -/* Http Server Events handling */ -#if defined (EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) - -typedef _SlEventPropogationStatus_e (*httpServer_callback) (SlNetAppHttpServerEvent_t*, SlNetAppHttpServerResponse_t*); - -static const httpServer_callback httpServer_callbacks[] = -{ -#ifdef SlExtLib1HttpServerEventHandler - SlExtLib1HttpServerEventHandler, -#endif - -#ifdef SlExtLib2HttpServerEventHandler - SlExtLib2HttpServerEventHandler, -#endif - -#ifdef SlExtLib3HttpServerEventHandler - SlExtLib3HttpServerEventHandler, -#endif - -#ifdef SlExtLib4HttpServerEventHandler - SlExtLib4HttpServerEventHandler, -#endif - -#ifdef SlExtLib5HttpServerEventHandler - SlExtLib5HttpServerEventHandler, -#endif -}; - -#undef _SlDrvHandleHttpServerEvents - -/******************************************************************* - _SlDrvHandleHttpServerEvents - Iterates through all the http server event handlers which are - registered by the external libs/user application. -********************************************************************/ -void _SlDrvHandleHttpServerEvents(SlNetAppHttpServerEvent_t *slHttpServerEvent, SlNetAppHttpServerResponse_t *slHttpServerResponse) -{ - _u8 i; - - /* Iterate over all the external libs handlers */ - for ( i = 0 ; i < sizeof(httpServer_callbacks)/sizeof(httpServer_callbacks[0]) ; i++ ) - { - if ( EVENT_PROPAGATION_BLOCK == httpServer_callbacks[i](slHttpServerEvent, slHttpServerResponse) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_NetAppHttpServerHdlr - slcb_NetAppHttpServerHdlr(slHttpServerEvent, slHttpServerResponse); -#endif - -} -#endif - - -/* Socket Events */ -#if defined (EXT_LIB_REGISTERED_SOCK_EVENTS) - -typedef _SlEventPropogationStatus_e (*sock_callback) (SlSockEvent_t *); - -static const sock_callback sock_callbacks[] = -{ -#ifdef SlExtLib1SockEventHandler - SlExtLib1SockEventHandler, -#endif - -#ifdef SlExtLib2SockEventHandler - SlExtLib2SockEventHandler, -#endif - -#ifdef SlExtLib3SockEventHandler - SlExtLib3SockEventHandler, -#endif - -#ifdef SlExtLib4SockEventHandler - SlExtLib4SockEventHandler, -#endif - -#ifdef SlExtLib5SockEventHandler - SlExtLib5SockEventHandler, -#endif -}; - -/************************************************************* - _SlDrvHandleSockEvents - Iterates through all the socket event handlers which are - registered by the external libs/user application. -**************************************************************/ -void _SlDrvHandleSockEvents(SlSockEvent_t *slSockEvent) -{ - _u8 i; - - /* Iterate over all the external libs handlers */ - for ( i = 0 ; i < sizeof(sock_callbacks)/sizeof(sock_callbacks[0]) ; i++ ) - { - if ( EVENT_PROPAGATION_BLOCK == sock_callbacks[i](slSockEvent) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_SockEvtHdlr - slcb_SockEvtHdlr(slSockEvent); -#endif - -} - -#endif - -/* Fatal Error Events handling*/ -#if defined (EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS) - -typedef _SlEventPropogationStatus_e (*fatal_error_callback) (SlDeviceEvent_t *); - -static const fatal_error_callback fatal_error_callbacks[] = -{ -#ifdef SlExtLib1FatalErrorEventHandler - SlExtLib1FatalErrorEventHandler, -#endif - -#ifdef SlExtLib2FatalErrorEventHandler - SlExtLib2FatalErrorEventHandler, -#endif - -#ifdef SlExtLib3FatalErrorEventHandler - SlExtLib3FatalErrorEventHandler, -#endif - -#ifdef SlExtLib4FatalErrorEventHandler - SlExtLib4FatalErrorEventHandler, -#endif - -#ifdef SlExtLib5FatalErrorEventHandler - SlExtLib5FatalErrorEventHandler, -#endif -}; - -#undef _SlDrvHandleFatalErrorEvents - -/******************************************************************** - _SlDrvHandleFatalErrorEvents - Iterates through all the fatal error (device) event handlers which are - registered by the external libs/user application. -*********************************************************************/ -void _SlDrvHandleFatalErrorEvents(SlDeviceFatal_t *slFatalErrorEvent) -{ - _u8 i; - - /* Iterate over all the extenal libs handlers */ - for ( i = 0 ; i < sizeof(fatal_error_callbacks)/sizeof(fatal_error_callbacks[0]) ; i++ ) - { - if (EVENT_PROPAGATION_BLOCK == fatal_error_callbacks[i](slFatalErrorEvent) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_DeviceFatalErrorEvtHdlr - slcb_DeviceFatalErrorEvtHdlr(slFatalErrorEvent); -#endif - -} -#endif - -/* NetApp request handler */ -#if defined (EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) - -typedef _SlEventPropogationStatus_e (*netapp_request_callback) (SlNetAppRequest_t*, SlNetAppResponse_t*); - -static const netapp_request_callback netapp_request_callbacks[] = -{ -#ifdef SlExtLib1NetAppRequestEventHandler - SlExtLib1NetAppRequestEventHandler, -#endif - -#ifdef SlExtLib2NetAppRequestEventHandler - SlExtLib2NetAppRequestEventHandler, -#endif - -#ifdef SlExtLib3NetAppRequestEventHandler - SlExtLib3NetAppRequestEventHandler, -#endif - -#ifdef SlExtLib4NetAppRequestEventHandler - SlExtLib4NetAppRequestEventHandler, -#endif - -#ifdef SlExtLib5NetAppRequestEventHandler - SlExtLib5NetAppRequestEventHandler, -#endif -}; - -#undef _SlDrvHandleNetAppRequestEvents - -/******************************************************************** - _SlDrvHandleNetAppRequest - Iterates through all the netapp request handlers which are - registered by the external libs/user application. -*********************************************************************/ -void _SlDrvHandleNetAppRequestEvents(SlNetAppRequest_t *pNetAppRequest, SlNetAppResponse_t *pNetAppResponse) -{ - _u8 i; - - /* Iterate over all the extenal libs handlers */ - for ( i = 0 ; i < sizeof(netapp_request_callbacks)/sizeof(netapp_request_callbacks[0]) ; i++ ) - { - if (EVENT_PROPAGATION_BLOCK == netapp_request_callbacks[i](pNetAppRequest, pNetAppResponse) ) - { - /* exit immediately and do not call the user specific handler as well */ - return; - } - } - -/* At last call the Application specific handler if registered */ -#ifdef slcb_NetAppRequestHdlr - slcb_NetAppRequestHdlr(pNetAppRequest, pNetAppResponse); -#endif - -} -#endif - - -#ifndef SL_MEMORY_MGMT_DYNAMIC -typedef struct -{ - _u32 Align; -#ifdef SL_PLATFORM_MULTI_THREADED - _SlAsyncRespBuf_t AsyncBufPool[SL_MAX_ASYNC_BUFFERS]; -#endif - _u8 AsyncRespBuf[SL_ASYNC_MAX_MSG_LEN]; -}_SlStatMem_t; - -static _SlStatMem_t g_StatMem; -#endif - - -/*****************************************************************************/ -/* Variables */ -/*****************************************************************************/ -_SlDriverCb_t g_CB; -static const _SlSyncPattern_t g_H2NSyncPattern = H2N_SYNC_PATTERN; - -#ifndef SL_IF_TYPE_UART -static const _SlSyncPattern_t g_H2NCnysPattern = H2N_CNYS_PATTERN; -#endif -_volatile _u8 RxIrqCnt; - -_u16 g_SlDeviceStatus = 0; -_SlLockObj_t GlobalLockObj; - -const _SlActionLookup_t _SlActionLookupTable[] = -{ - {ACCEPT_ID, SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE, (_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Accept}, - {CONNECT_ID, SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Connect}, - {SELECT_ID, SL_OPCODE_SOCKET_SELECTASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Select}, - {GETHOSYBYNAME_ID, SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_DnsGetHostByName}, - {GETHOSYBYSERVICE_ID, SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_DnsGetHostByService}, - {PING_ID, SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE, (_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_PingResponse}, - {NETAPP_RECEIVE_ID, SL_OPCODE_NETAPP_RECEIVE, (_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_NetAppReceive}, - {START_STOP_ID, SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE,(_SlSpawnEntryFunc_t)_SlDeviceHandleAsync_Stop}, - {NETUTIL_CMD_ID, SL_OPCODE_NETUTIL_COMMANDASYNCRESPONSE,(_SlSpawnEntryFunc_t)_SlNetUtilHandleAsync_Cmd}, - {CLOSE_ID, SL_OPCODE_SOCKET_SOCKETCLOSEASYNCEVENT,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_Close}, - {START_TLS_ID, SL_OPCODE_SOCKET_SOCKETASYNCEVENT,(_SlSpawnEntryFunc_t)_SlSocketHandleAsync_StartTLS} -}; - - -typedef struct -{ - _u16 opcode; - _u8 event; -} OpcodeKeyVal_t; - - -/* The table translates opcode to user's event type */ -const OpcodeKeyVal_t OpcodeTranslateTable[] = -{ - {SL_OPCODE_WLAN_STA_ASYNCCONNECTEDRESPONSE, SL_WLAN_EVENT_CONNECT}, - {SL_OPCODE_WLAN_P2PCL_ASYNCCONNECTEDRESPONSE, SL_WLAN_EVENT_P2P_CONNECT}, - {SL_OPCODE_WLAN_STA_ASYNCDISCONNECTEDRESPONSE, SL_WLAN_EVENT_DISCONNECT}, - {SL_OPCODE_WLAN_P2PCL_ASYNCDISCONNECTEDRESPONSE,SL_WLAN_EVENT_P2P_DISCONNECT}, - {SL_OPCODE_WLAN_ASYNC_STA_ADDED, SL_WLAN_EVENT_STA_ADDED}, - {SL_OPCODE_WLAN_ASYNC_P2PCL_ADDED,SL_WLAN_EVENT_P2P_CLIENT_ADDED}, - {SL_OPCODE_WLAN_ASYNC_STA_REMOVED, SL_WLAN_EVENT_STA_REMOVED}, - {SL_OPCODE_WLAN_ASYNC_P2PCL_REMOVED,SL_WLAN_EVENT_P2P_CLIENT_REMOVED}, - {SL_OPCODE_WLAN_P2P_DEV_FOUND,SL_WLAN_EVENT_P2P_DEVFOUND}, - {SL_OPCODE_WLAN_P2P_NEG_REQ_RECEIVED, SL_WLAN_EVENT_P2P_REQUEST}, - {SL_OPCODE_WLAN_P2P_CONNECTION_FAILED, SL_WLAN_EVENT_P2P_CONNECTFAIL}, - {SL_OPCODE_WLAN_PROVISIONING_STATUS_ASYNC_EVENT, SL_WLAN_EVENT_PROVISIONING_STATUS}, - {SL_OPCODE_WLAN_PROVISIONING_PROFILE_ADDED_ASYNC_RESPONSE, SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED}, - {SL_OPCODE_WLAN_RX_FILTER_ASYNC_RESPONSE,SL_WLAN_EVENT_RXFILTER}, - {SL_OPCODE_WLAN_LINK_QUALITY_RESPONSE, SL_WLAN_EVENT_LINK_QUALITY_TRIGGER}, - - {SL_OPCODE_NETAPP_IPACQUIRED, SL_NETAPP_EVENT_IPV4_ACQUIRED}, - {SL_OPCODE_NETAPP_IPACQUIRED_V6, SL_NETAPP_EVENT_IPV6_ACQUIRED}, - {SL_OPCODE_NETAPP_IP_LEASED, SL_NETAPP_EVENT_DHCPV4_LEASED}, - {SL_OPCODE_NETAPP_IP_RELEASED, SL_NETAPP_EVENT_DHCPV4_RELEASED}, - {SL_OPCODE_NETAPP_IP_COLLISION, SL_NETAPP_EVENT_IP_COLLISION}, - {SL_OPCODE_NETAPP_IPV4_LOST, SL_NETAPP_EVENT_IPV4_LOST}, - {SL_OPCODE_NETAPP_DHCP_IPV4_ACQUIRE_TIMEOUT, SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT}, - {SL_OPCODE_NETAPP_IPV6_LOST_V6, SL_NETAPP_EVENT_IPV6_LOST}, - {SL_OPCODE_NETAPP_NO_IP_COLLISION_DETECTED, SL_NETAPP_EVENT_NO_IPV4_COLLISION_DETECTED}, - {SL_OPCODE_NETAPP_NO_LOCAL_IP_COLLISION_DETECTED_V6, SL_NETAPP_EVENT_NO_LOCAL_IPV6_COLLISION_DETECTED}, - {SL_OPCODE_NETAPP_NO_GLOBAL_IP_COLLISION_DETECTED_V6, SL_NETAPP_EVENT_NO_GLOBAL_IPV6_COLLISION_DETECTED}, - {SL_OPCODE_SOCKET_TXFAILEDASYNCRESPONSE, SL_SOCKET_TX_FAILED_EVENT}, - {SL_OPCODE_SOCKET_SOCKETASYNCEVENT, SL_SOCKET_ASYNC_EVENT} - -}; - - - -_SlDriverCb_t* g_pCB = NULL; -P_SL_DEV_PING_CALLBACK pPingCallBackFunc = NULL; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ -static _SlReturnVal_t _SlDrvMsgRead(_u16* outMsgReadLen, _u8** pAsyncBuf); -static _SlReturnVal_t _SlDrvMsgWrite(_SlCmdCtrl_t *pCmdCtrl,_SlCmdExt_t *pCmdExt, _u8 *pTxRxDescBuff); -static _SlReturnVal_t _SlDrvMsgReadCmdCtx(_u16 cmdOpcode, _u8 IsLockRequired); -static _SlReturnVal_t _SlDrvClassifyRxMsg(_SlOpcode_t Opcode ); -static _SlReturnVal_t _SlDrvRxHdrRead(_u8 *pBuf); -static void _SlDrvAsyncEventGenericHandler(_u8 bInCmdContext, _u8 *pAsyncBuffer); -static void _SlDrvRemoveFromList(_u8* ListIndex, _u8 ItemIndex); -static _SlReturnVal_t _SlDrvFindAndSetActiveObj(_SlOpcode_t Opcode, _u8 Sd); - -/*****************************************************************************/ -/* Internal functions */ -/*****************************************************************************/ - - -/***************************************************************************** -_SlDrvDriverCBInit - init Driver Control Block -*****************************************************************************/ - -_SlReturnVal_t _SlDrvDriverCBInit(void) -{ - _u8 Idx =0; - - g_pCB = &g_CB; - -#ifndef SL_PLATFORM_MULTI_THREADED - { - extern _SlNonOsCB_t g__SlNonOsCB; - sl_Memset(&g__SlNonOsCB, 0, sizeof(g__SlNonOsCB)); - } -#endif - - _SlDrvMemZero(g_pCB, (_u16)sizeof(_SlDriverCb_t)); - RxIrqCnt = 0; - OSI_RET_OK_CHECK( sl_SyncObjCreate(&g_pCB->CmdSyncObj, "CmdSyncObj") ); - SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->CmdSyncObj); - - if (!SL_IS_GLOBAL_LOCK_INIT) - { - OSI_RET_OK_CHECK( sl_LockObjCreate(&GlobalLockObj, "GlobalLockObj") ); - SL_SET_GLOBAL_LOCK_INIT; - } - - OSI_RET_OK_CHECK( sl_LockObjCreate(&g_pCB->ProtectionLockObj, "ProtectionLockObj") ); - g_pCB->NumOfDeletedSyncObj = 0; -#if defined(slcb_SocketTriggerEventHandler) - g_pCB->SocketTriggerSelect.Info.ObjPoolIdx = MAX_CONCURRENT_ACTIONS; -#endif - /* Init Drv object */ - _SlDrvMemZero(&g_pCB->ObjPool[0], (_u16)(MAX_CONCURRENT_ACTIONS*sizeof(_SlPoolObj_t))); - /* place all Obj in the free list*/ - g_pCB->FreePoolIdx = 0; - - for (Idx = 0 ; Idx < MAX_CONCURRENT_ACTIONS ; Idx++) - { - g_pCB->ObjPool[Idx].NextIndex = Idx + 1; - g_pCB->ObjPool[Idx].AdditionalData = SL_MAX_SOCKETS; - - OSI_RET_OK_CHECK( sl_SyncObjCreate(&g_pCB->ObjPool[Idx].SyncObj, "SyncObj")); - SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->ObjPool[Idx].SyncObj); - } - - g_pCB->ActivePoolIdx = MAX_CONCURRENT_ACTIONS; - g_pCB->PendingPoolIdx = MAX_CONCURRENT_ACTIONS; - -#ifdef SL_PLATFORM_MULTI_THREADED - -#ifdef SL_MEMORY_MGMT_DYNAMIC - /* reset the spawn messages list */ - g_pCB->spawnMsgList = NULL; -#else - for (Idx = 0; Idx < SL_MAX_ASYNC_BUFFERS; Idx++) - { - g_StatMem.AsyncBufPool[Idx].ActionIndex = 0xFF; - g_StatMem.AsyncBufPool[Idx].AsyncHndlr = NULL; - } -#endif -#else - /* clear the global lock owner */ - _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_APP); -#endif - /* Flow control init */ - g_pCB->FlowContCB.TxPoolCnt = FLOW_CONT_MIN; - OSI_RET_OK_CHECK(sl_LockObjCreate(&g_pCB->FlowContCB.TxLockObj, "TxLockObj")); - OSI_RET_OK_CHECK(sl_SyncObjCreate(&g_pCB->FlowContCB.TxSyncObj, "TxSyncObj")); - g_pCB->FlowContCB.MinTxPayloadSize = 1536; /* init maximum length */ - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - OSI_RET_OK_CHECK(sl_LockObjCreate(&g_pCB->MultiSelectCB.SelectLockObj, "SelectLockObj")); - OSI_RET_OK_CHECK(sl_SyncObjCreate(&g_pCB->MultiSelectCB.SelectSyncObj, "SelectSyncObj")); - SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->MultiSelectCB.SelectSyncObj); - g_pCB->MultiSelectCB.CtrlSockFD = 0xFF; -#endif - return SL_OS_RET_CODE_OK; -} - -/***************************************************************************** -_SlDrvDriverCBDeinit - De init Driver Control Block -*****************************************************************************/ -_SlReturnVal_t _SlDrvDriverCBDeinit(void) -{ - _SlSpawnMsgItem_t* pCurr; - _SlSpawnMsgItem_t* pNext; - - /* Flow control de-init */ - g_pCB->FlowContCB.TxPoolCnt = 0; - - SL_SET_DEVICE_STATUS(0); - - SL_UNSET_DEVICE_STARTED; - - OSI_RET_OK_CHECK(sl_LockObjDelete(&g_pCB->FlowContCB.TxLockObj)); - OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->FlowContCB.TxSyncObj)); -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - OSI_RET_OK_CHECK(sl_LockObjDelete(&g_pCB->MultiSelectCB.SelectLockObj)); - OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->MultiSelectCB.SelectSyncObj)); -#endif - OSI_RET_OK_CHECK( sl_SyncObjDelete(&g_pCB->CmdSyncObj)); - - OSI_RET_OK_CHECK( sl_LockObjDelete(&g_pCB->ProtectionLockObj) ); - - g_pCB->FreePoolIdx = 0; - g_pCB->PendingPoolIdx = MAX_CONCURRENT_ACTIONS; - g_pCB->ActivePoolIdx = MAX_CONCURRENT_ACTIONS; - -#ifdef SL_MEMORY_MGMT_DYNAMIC - /* Release linked list of async buffers */ - pCurr = g_pCB->spawnMsgList; - while (NULL != pCurr) - { - pNext = pCurr->next; - sl_Free(pCurr->Buffer); - sl_Free(pCurr); - pCurr = pNext; - } - g_pCB->spawnMsgList = NULL; - -#endif - - g_pCB = NULL; - - /* Clear the restart device flag */ - SL_UNSET_RESTART_REQUIRED; - - return SL_OS_RET_CODE_OK; -} - -/***************************************************************************** -_SlDrvRxIrqHandler - Interrupt handler -*****************************************************************************/ -_SlReturnVal_t _SlDrvRxIrqHandler(void *pValue) -{ - (void)pValue; - - sl_IfMaskIntHdlr(); - - RxIrqCnt++; - - if (TRUE == g_pCB->WaitForCmdResp) - { - OSI_RET_OK_CHECK( sl_SyncObjSignalFromIRQ(&g_pCB->CmdSyncObj) ); - } - else - { - (void)sl_Spawn((_SlSpawnEntryFunc_t)_SlDrvMsgReadSpawnCtx, NULL, SL_SPAWN_FLAG_FROM_SL_IRQ_HANDLER); - } - return SL_OS_RET_CODE_OK; -} - -/***************************************************************************** -_SlDrvDriverIsApiAllowed - on LOCKED state, only 3 commands are allowed -*****************************************************************************/ -_SlReturnVal_t _SlDrvDriverIsApiAllowed(_u16 Silo) -{ - if (!SL_IS_COMMAND_ALLOWED) - { - if (SL_IS_DEVICE_STOP_IN_PROGRESS) - { - return SL_RET_CODE_STOP_IN_PROGRESS; - } - - if ((SL_IS_DEVICE_LOCKED) && (SL_OPCODE_SILO_FS != Silo)) - { - /* All APIs except the FS ones must be aborted if device is locked */ - return SL_RET_CODE_DEV_LOCKED; - } - if (SL_IS_RESTART_REQUIRED) - { - /* API has been aborted due command not allowed when Restart required */ - /* The opcodes allowed are: SL_OPCODE_DEVICE_STOP_COMMAND */ - return SL_API_ABORTED; - } - - if (!SL_IS_DEVICE_STARTED) - { - return SL_RET_CODE_DEV_NOT_STARTED; - } - - if (( SL_IS_PROVISIONING_ACTIVE || SL_IS_PROVISIONING_INITIATED_BY_USER) && !(SL_IS_PROVISIONING_API_ALLOWED)) - { - /* API has ignored due to provisioning in progress */ - return SL_RET_CODE_PROVISIONING_IN_PROGRESS; - } - - } - - return SL_OS_RET_CODE_OK; -} - - -/***************************************************************************** -_SlDrvCmdOp -*****************************************************************************/ -_SlReturnVal_t _SlDrvCmdOp( - _SlCmdCtrl_t *pCmdCtrl , - void *pTxRxDescBuff , - _SlCmdExt_t *pCmdExt) -{ - _SlReturnVal_t RetVal; - _u8 IsLockRequired = TRUE; - - IsLockRequired = (SL_IS_PROVISIONING_IN_PROGRESS && (pCmdCtrl->Opcode == SL_OPCODE_DEVICE_STOP_COMMAND)) ? FALSE: TRUE; - - if (IsLockRequired) - { - _u32 GlobalLockFlags = GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS; - - /* check the special case of provisioning stop command */ - if (pCmdCtrl->Opcode == SL_OPCODE_WLAN_PROVISIONING_COMMAND) - { - SlWlanProvisioningParams_t *pParams = (SlWlanProvisioningParams_t *)pTxRxDescBuff; - - /* No timeout specifies it is a stop provisioning command */ - if (pParams->InactivityTimeoutSec == 0) - { - GlobalLockFlags |= GLOBAL_LOCK_FLAGS_PROVISIONING_STOP_API; - } - - } - - GlobalLockFlags |= (((_u32)pCmdCtrl->Opcode) << 16); - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GlobalLockFlags); - } - - /* In case the global was successfully taken but error in progress - it means it has been released as part of an error handling and we should abort immediately */ - if (SL_IS_RESTART_REQUIRED) - { - if (IsLockRequired) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - } - - return SL_API_ABORTED; - } - - g_pCB->WaitForCmdResp = TRUE; - - SL_TRACE1(DBG_MSG, MSG_312, "\n\r_SlDrvCmdOp: call _SlDrvMsgWrite: %x\n\r", pCmdCtrl->Opcode); - - /* send the message */ - RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); - - if(SL_OS_RET_CODE_OK == RetVal) - { - /* wait for respond */ - RetVal = _SlDrvMsgReadCmdCtx(pCmdCtrl->Opcode, IsLockRequired); /* will free global lock */ - SL_TRACE1(DBG_MSG, MSG_314, "\n\r_SlDrvCmdOp: exited _SlDrvMsgReadCmdCtx: %x\n\r", pCmdCtrl->Opcode); - } - else - { - if (IsLockRequired) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - } - - } - - return RetVal; -} - -/***************************************************************************** -_SlDrvDataReadOp -*****************************************************************************/ -_SlReturnVal_t _SlDrvDataReadOp( - _SlSd_t Sd, - _SlCmdCtrl_t *pCmdCtrl , - void *pTxRxDescBuff , - _SlCmdExt_t *pCmdExt) -{ - _SlReturnVal_t RetVal; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - _SlArgsData_t pArgsData; - - /* Validate input arguments */ - _SL_ASSERT_ERROR(NULL != pCmdExt->pRxPayload, SL_RET_CODE_INVALID_INPUT); - - /* If zero bytes is requested, return error. */ - /* This allows us not to fill remote socket's IP address in return arguments */ - VERIFY_PROTOCOL(0 != pCmdExt->RxPayloadLen); - - /* Validate socket */ - if((Sd & SL_BSD_SOCKET_ID_MASK) >= SL_MAX_SOCKETS) - { - return SL_ERROR_BSD_EBADF; - } - - /*Use Obj to issue the command, if not available try later*/ - ObjIdx = _SlDrvWaitForPoolObj(RECV_ID, Sd & SL_BSD_SOCKET_ID_MASK); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) - { - return SL_RET_CODE_STOP_IN_PROGRESS; - } - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - pArgsData.pData = pCmdExt->pRxPayload; - pArgsData.pArgs = (_u8 *)pTxRxDescBuff; - g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&pArgsData; - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - - /* Do Flow Control check/update for DataWrite operation */ - SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->FlowContCB.TxLockObj); - - - /* Clear SyncObj for the case it was signaled before TxPoolCnt */ - /* dropped below '1' (last Data buffer was taken) */ - /* OSI_RET_OK_CHECK( sl_SyncObjClear(&g_pCB->FlowContCB.TxSyncObj) ); */ - SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->FlowContCB.TxSyncObj); - - if(g_pCB->FlowContCB.TxPoolCnt <= FLOW_CONT_MIN) - { - - /* If TxPoolCnt was increased by other thread at this moment, - TxSyncObj won't wait here */ -#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) - if (_SlDrvIsSpawnOwnGlobalLock()) - { - while (TRUE) - { - /* If we are in spawn context, this is an API which was called from event handler, - read any async event and check if we got signaled */ - _SlInternalSpawnWaitForEvent(); - /* is it mine? */ - if (0 == sl_SyncObjWait(&g_pCB->FlowContCB.TxSyncObj, SL_OS_NO_WAIT)) - { - break; - } - } - } - else -#endif - { - SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->FlowContCB.TxSyncObj); - } - - } - - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS); - - /* In case the global was successfully taken but error in progress - it means it has been released as part of an error handling and we should abort immediately */ - if (SL_IS_RESTART_REQUIRED) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - return SL_API_ABORTED; - } - - /* Here we consider the case in which some cmd has been sent to the NWP, - And its allocated packet has not been freed yet. */ - VERIFY_PROTOCOL(g_pCB->FlowContCB.TxPoolCnt > (FLOW_CONT_MIN - 1)); - g_pCB->FlowContCB.TxPoolCnt--; - - SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); - - /* send the message */ - RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, (_u8 *)pTxRxDescBuff); - - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - - if(SL_OS_RET_CODE_OK == RetVal) - { - /* in case socket is non-blocking one, the async event should be received immediately */ - if( g_pCB->SocketNonBlocking & (1<<(Sd & SL_BSD_SOCKET_ID_MASK) )) - { - _u16 opcodeAsyncEvent = (pCmdCtrl->Opcode == SL_OPCODE_SOCKET_RECV) ? SL_OPCODE_SOCKET_RECVASYNCRESPONSE : SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE; - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, SL_DRIVER_TIMEOUT_SHORT, opcodeAsyncEvent)); - } - else - { - /* Wait for response message. Will be signaled by _SlDrvMsgRead. */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, 0, 0)); - } - - } - - _SlDrvReleasePoolObj(ObjIdx); - return RetVal; -} - -/* ******************************************************************************/ -/* _SlDrvDataWriteOp */ -/* ******************************************************************************/ -_SlReturnVal_t _SlDrvDataWriteOp( - _SlSd_t Sd, - _SlCmdCtrl_t *pCmdCtrl , - void *pTxRxDescBuff , - _SlCmdExt_t *pCmdExt) -{ - _SlReturnVal_t RetVal = SL_ERROR_BSD_EAGAIN; /* initiated as SL_EAGAIN for the non blocking mode */ - _u32 allocTxPoolPkts; - - while( 1 ) - { - /* Do Flow Control check/update for DataWrite operation */ - SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->FlowContCB.TxLockObj); - - /* Clear SyncObj for the case it was signaled before TxPoolCnt */ - /* dropped below '1' (last Data buffer was taken) */ - /* OSI_RET_OK_CHECK( sl_SyncObjClear(&g_pCB->FlowContCB.TxSyncObj) ); */ - SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->FlowContCB.TxSyncObj); - - /* number of tx pool packet that will be used */ - allocTxPoolPkts = 1 + (pCmdExt->TxPayload1Len-1) / g_pCB->FlowContCB.MinTxPayloadSize; /* MinTxPayloadSize will be updated by Asunc event from NWP */ - /* we have indication that the last send has failed - socket is no longer valid for operations */ - if(g_pCB->SocketTXFailure & (1<<(Sd & SL_BSD_SOCKET_ID_MASK))) - { - SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); - return SL_ERROR_BSD_SOC_ERROR; - } - if(g_pCB->FlowContCB.TxPoolCnt <= FLOW_CONT_MIN + allocTxPoolPkts) - { - /* we have indication that this socket is set as blocking and we try to */ - /* unblock it - return an error */ - if( g_pCB->SocketNonBlocking & (1<<(Sd & SL_BSD_SOCKET_ID_MASK) )) - { -#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) - if (_SlDrvIsSpawnOwnGlobalLock()) - { - _SlInternalSpawnWaitForEvent(); - } -#endif - SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); - return RetVal; - } - /* If TxPoolCnt was increased by other thread at this moment, */ - /* TxSyncObj won't wait here */ -#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) - if (_SlDrvIsSpawnOwnGlobalLock()) - { - while (TRUE) - { - /* If we are in spawn context, this is an API which was called from event handler, - read any async event and check if we got signaled */ - _SlInternalSpawnWaitForEvent(); - /* is it mine? */ - if (0 == sl_SyncObjWait(&g_pCB->FlowContCB.TxSyncObj, SL_OS_NO_WAIT)) - { - break; - } - } - } - else -#endif - { - SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->FlowContCB.TxSyncObj); - } - } - if(g_pCB->FlowContCB.TxPoolCnt > FLOW_CONT_MIN + allocTxPoolPkts ) - { - break; - } - else - { - SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); - } - } - - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS); - - /* In case the global was succesffully taken but error in progress - it means it has been released as part of an error handling and we should abort immediately */ - if (SL_IS_RESTART_REQUIRED) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - return SL_API_ABORTED; - } - - /* Here we consider the case in which some cmd has been sent to the NWP, - And its allocated packet has not been freed yet. */ - VERIFY_PROTOCOL(g_pCB->FlowContCB.TxPoolCnt > (FLOW_CONT_MIN + allocTxPoolPkts -1) ); - g_pCB->FlowContCB.TxPoolCnt -= (_u8)allocTxPoolPkts; - - SL_DRV_OBJ_UNLOCK(&g_pCB->FlowContCB.TxLockObj); - - SL_TRACE1(DBG_MSG, MSG_312, "\n\r_SlDrvCmdOp: call _SlDrvMsgWrite: %x\n\r", pCmdCtrl->Opcode); - - /* send the message */ - RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - - return RetVal; -} - -/* ******************************************************************************/ -/* _SlDrvMsgWrite */ -/* ******************************************************************************/ -static _SlReturnVal_t _SlDrvMsgWrite(_SlCmdCtrl_t *pCmdCtrl,_SlCmdExt_t *pCmdExt, _u8 *pTxRxDescBuff) -{ - _u8 sendRxPayload = FALSE; - _SL_ASSERT_ERROR(NULL != pCmdCtrl, SL_API_ABORTED); - - g_pCB->FunctionParams.pCmdCtrl = pCmdCtrl; - g_pCB->FunctionParams.pTxRxDescBuff = pTxRxDescBuff; - g_pCB->FunctionParams.pCmdExt = pCmdExt; - - g_pCB->TempProtocolHeader.Opcode = pCmdCtrl->Opcode; - g_pCB->TempProtocolHeader.Len = (_u16)(_SL_PROTOCOL_CALC_LEN(pCmdCtrl, pCmdExt)); - - if (pCmdExt && pCmdExt->RxPayloadLen < 0 ) - { - pCmdExt->RxPayloadLen = pCmdExt->RxPayloadLen * (-1); /* change sign */ - sendRxPayload = TRUE; - g_pCB->TempProtocolHeader.Len = g_pCB->TempProtocolHeader.Len + pCmdExt->RxPayloadLen; - } - -#ifdef SL_START_WRITE_STAT - sl_IfStartWriteSequence(g_pCB->FD); -#endif - -#ifdef SL_IF_TYPE_UART - /* Write long sync pattern */ - NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_H2NSyncPattern.Long, 2*SYNC_PATTERN_LEN); -#else - /* Write short sync pattern */ - NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_H2NSyncPattern.Short, SYNC_PATTERN_LEN); -#endif - - /* Header */ - NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_pCB->TempProtocolHeader, _SL_CMD_HDR_SIZE); - - /* Descriptors */ - if (pTxRxDescBuff && pCmdCtrl->TxDescLen > 0) - { - NWP_IF_WRITE_CHECK(g_pCB->FD, pTxRxDescBuff, - _SL_PROTOCOL_ALIGN_SIZE(pCmdCtrl->TxDescLen)); - } - - /* A special mode where Rx payload and Rx length are used as Tx as well */ - /* This mode requires no Rx payload on the response and currently used by fs_Close and sl_Send on */ - /* transceiver mode */ - if (sendRxPayload == TRUE ) - { - NWP_IF_WRITE_CHECK(g_pCB->FD, pCmdExt->pRxPayload, - _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->RxPayloadLen)); - } - - - /* if the message has some payload */ - if (pCmdExt) - { - /* If the message has payload, it is mandatory that the message's arguments are protocol aligned. */ - /* Otherwise the aligning of arguments will create a gap between arguments and payload. */ - VERIFY_PROTOCOL(_SL_IS_PROTOCOL_ALIGNED_SIZE(pCmdCtrl->TxDescLen)); - - /* In case two seperated buffers were supplied we should merge the two buffers*/ - if ((pCmdExt->TxPayload1Len > 0) && (pCmdExt->TxPayload2Len > 0)) - { - _u8 BuffInTheMiddle[4]; - _u8 FirstPayloadReminder = 0; - _u8 SecondPayloadOffset = 0; - - FirstPayloadReminder = pCmdExt->TxPayload1Len & 3; /* calulate the first payload reminder */ - - /* we first write the 4-bytes aligned payload part */ - pCmdExt->TxPayload1Len -= FirstPayloadReminder; - - /* writing the first transaction*/ - NWP_IF_WRITE_CHECK(g_pCB->FD, pCmdExt->pTxPayload1, pCmdExt->TxPayload1Len); - - /* Only if we the first payload is not aligned we need the intermediate transaction */ - if (FirstPayloadReminder != 0) - { - /* here we count how many bytes we need to take from the second buffer */ - SecondPayloadOffset = 4 - FirstPayloadReminder; - - /* copy the first payload reminder */ - sl_Memcpy(&BuffInTheMiddle[0], pCmdExt->pTxPayload1 + pCmdExt->TxPayload1Len, FirstPayloadReminder); - - /* add the beginning of the second payload to complete 4-bytes transaction */ - sl_Memcpy(&BuffInTheMiddle[FirstPayloadReminder], pCmdExt->pTxPayload2, SecondPayloadOffset); - - /* write the second transaction of the 4-bytes buffer */ - NWP_IF_WRITE_CHECK(g_pCB->FD, &BuffInTheMiddle[0], 4); - } - - - /* if we still has bytes to write in the second buffer */ - if (pCmdExt->TxPayload2Len > SecondPayloadOffset) - { - /* write the third transaction (truncated second payload) */ - NWP_IF_WRITE_CHECK(g_pCB->FD, - pCmdExt->pTxPayload2 + SecondPayloadOffset, - _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayload2Len - SecondPayloadOffset)); - } - - } - else if (pCmdExt->TxPayload1Len > 0) - { - /* Only 1 payload supplied (Payload1) so just align to 4 bytes and send it */ - NWP_IF_WRITE_CHECK(g_pCB->FD, pCmdExt->pTxPayload1, - _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayload1Len)); - } - else if (pCmdExt->TxPayload2Len > 0) - { - /* Only 1 payload supplied (Payload2) so just align to 4 bytes and send it */ - NWP_IF_WRITE_CHECK(g_pCB->FD, pCmdExt->pTxPayload2, - _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayload2Len)); - - } - } - - _SL_DBG_CNT_INC(MsgCnt.Write); - -#ifdef SL_START_WRITE_STAT - sl_IfEndWriteSequence(g_pCB->FD); -#endif - - return SL_OS_RET_CODE_OK; -} - -/* ******************************************************************************/ -/* _SlDrvMsgRead */ -/* ******************************************************************************/ -_SlReturnVal_t _SlDrvMsgRead(_u16* outMsgReadLen, _u8** pOutAsyncBuf) -{ - /* alignment for small memory models */ - union - { - _u8 TempBuf[_SL_RESP_HDR_SIZE]; - _u32 DummyBuf[2]; - } uBuf; - _u8 TailBuffer[4]; - _u16 LengthToCopy; - _u16 AlignedLengthRecv; - _u8 *pAsyncBuf = NULL; - _u16 OpCode; - _u16 RespPayloadLen; - _u8 sd = SL_MAX_SOCKETS; - _SlReturnVal_t RetVal; - _SlRxMsgClass_e RxMsgClass; - int32_t Count = 0; - /* Save parameters in global CB */ - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = NULL; - _SlDrvMemZero(&TailBuffer[0], sizeof(TailBuffer)); - - if (_SlDrvRxHdrRead((_u8*)(uBuf.TempBuf)) == SL_API_ABORTED) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - - _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_SYNC_LOSS, 0, 0); - return SL_API_ABORTED; - } - - OpCode = OPCODE(uBuf.TempBuf); - RespPayloadLen = (_u16)(RSP_PAYLOAD_LEN(uBuf.TempBuf)); - - /* Update the NWP status */ - g_pCB->FlowContCB.TxPoolCnt = ((_SlResponseHeader_t *)uBuf.TempBuf)->TxPoolCnt; - g_pCB->SocketNonBlocking = ((_SlResponseHeader_t *)uBuf.TempBuf)->SocketNonBlocking; - g_pCB->SocketTXFailure = ((_SlResponseHeader_t *)uBuf.TempBuf)->SocketTXFailure; - g_pCB->FlowContCB.MinTxPayloadSize = ((_SlResponseHeader_t *)uBuf.TempBuf)->MinMaxPayload; - - SL_SET_DEVICE_STATUS(((_SlResponseHeader_t *)uBuf.TempBuf)->DevStatus); - - if(g_pCB->FlowContCB.TxPoolCnt > FLOW_CONT_MIN) - { - sl_SyncObjGetCount(&g_pCB->FlowContCB.TxSyncObj, &Count); - if (0 == Count) - { - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->FlowContCB.TxSyncObj); - } - } - - /* Find the RX message class and set its Async event handler */ - _SlDrvClassifyRxMsg(OpCode); - - RxMsgClass = g_pCB->FunctionParams.AsyncExt.RxMsgClass; - - switch(RxMsgClass) - { - case ASYNC_EVT_CLASS: - { - VERIFY_PROTOCOL(NULL == pAsyncBuf); - -#ifdef SL_MEMORY_MGMT_DYNAMIC - *pOutAsyncBuf = (_u8*)sl_Malloc(SL_ASYNC_MAX_MSG_LEN); - -#else - *pOutAsyncBuf = g_StatMem.AsyncRespBuf; -#endif - /* set the local pointer to the allocated one */ - pAsyncBuf = *pOutAsyncBuf; - - MALLOC_OK_CHECK(pAsyncBuf); - - /* clear the async buffer */ - _SlDrvMemZero(pAsyncBuf, (_u16)SL_ASYNC_MAX_MSG_LEN); - sl_Memcpy(pAsyncBuf, uBuf.TempBuf, _SL_RESP_HDR_SIZE); - - /* add the protocol header length */ - *outMsgReadLen = _SL_RESP_HDR_SIZE; - - if (_SL_PROTOCOL_ALIGN_SIZE(RespPayloadLen) <= SL_ASYNC_MAX_PAYLOAD_LEN) - { - AlignedLengthRecv = (_u16)_SL_PROTOCOL_ALIGN_SIZE(RespPayloadLen); - } - else - { - AlignedLengthRecv = (_u16)_SL_PROTOCOL_ALIGN_SIZE(SL_ASYNC_MAX_PAYLOAD_LEN); - } - - /* complete the read of the entire message to the async buffer */ - if (RespPayloadLen > 0) - { - NWP_IF_READ_CHECK(g_pCB->FD, - pAsyncBuf + _SL_RESP_HDR_SIZE, - AlignedLengthRecv); - *outMsgReadLen += AlignedLengthRecv; - } - /* In case ASYNC RX buffer length is smaller then the received data length, dump the rest */ - if ((_SL_PROTOCOL_ALIGN_SIZE(RespPayloadLen) > SL_ASYNC_MAX_PAYLOAD_LEN)) - { - AlignedLengthRecv = (_u16)(_SL_PROTOCOL_ALIGN_SIZE(RespPayloadLen) - SL_ASYNC_MAX_PAYLOAD_LEN); - while (AlignedLengthRecv > 0) - { - NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4); - AlignedLengthRecv = AlignedLengthRecv - 4; - } - } - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - if ( - (SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE == OpCode) || - (SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE_V6 == OpCode) || - (SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE == OpCode) || - (SL_OPCODE_SOCKET_SOCKETCLOSEASYNCEVENT == OpCode) - ) - { - /* go over the active list if exist to find obj waiting for this Async event */ - sd = ((((SlSocketResponse_t *)(pAsyncBuf + _SL_RESP_HDR_SIZE))->Sd) & SL_BSD_SOCKET_ID_MASK); - } - if (SL_OPCODE_SOCKET_SOCKETASYNCEVENT == OpCode) - { - /* Save the socket descriptor which has been waiting for this opcode */ - sd = ((((SlSocketAsyncEvent_t *)(pAsyncBuf + _SL_RESP_HDR_SIZE))->Sd) & SL_BSD_SOCKET_ID_MASK); - } - - _SlDrvFindAndSetActiveObj(OpCode, sd); - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - break; - } - - case RECV_RESP_CLASS: - { - _u8 ExpArgSize; /* Expected size of Recv/Recvfrom arguments */ - - switch(OpCode) - { - case SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE: - ExpArgSize = (_u8)RECVFROM_IPV4_ARGS_SIZE; - break; - case SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6: - ExpArgSize = (_u8)RECVFROM_IPV6_ARGS_SIZE; - break; - default: - /* SL_OPCODE_SOCKET_RECVASYNCRESPONSE: */ - ExpArgSize = (_u8)RECV_ARGS_SIZE; - } - - /* Read first 4 bytes of Recv/Recvfrom response to get SocketId and actual */ - /* response data length */ - NWP_IF_READ_CHECK(g_pCB->FD, &uBuf.TempBuf[4], RECV_ARGS_SIZE); - - /* Validate Socket ID and Received Length value. */ - VERIFY_PROTOCOL((SD(&uBuf.TempBuf[4])& SL_BSD_SOCKET_ID_MASK) < SL_MAX_SOCKETS); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - /* go over the active list if exist to find obj waiting for this Async event */ - RetVal = _SlDrvFindAndSetActiveObj(OpCode, SD(&uBuf.TempBuf[4]) & SL_BSD_SOCKET_ID_MASK); - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - /* This case is for reading the receive response sent by clearing the control socket. */ - if((RetVal == SL_RET_OBJ_NOT_SET) && (SD(&uBuf.TempBuf[4]) == g_pCB->MultiSelectCB.CtrlSockFD)) - { - _u8 buffer[16]; - - sl_Memcpy(&buffer[0], &uBuf.TempBuf[4], RECV_ARGS_SIZE); - - if(ExpArgSize > (_u8)RECV_ARGS_SIZE) - { - NWP_IF_READ_CHECK(g_pCB->FD, - &buffer[RECV_ARGS_SIZE], - ExpArgSize - RECV_ARGS_SIZE); - } - - /* Here g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pData contains requested(expected) Recv/Recvfrom DataSize. */ - /* Overwrite requested DataSize with actual one. */ - /* If error is received, this information will be read from arguments. */ - if(ACT_DATA_SIZE(&uBuf.TempBuf[4]) > 0) - { - - /* Read 4 bytes aligned from interface */ - /* therefore check the requested length and read only */ - /* 4 bytes aligned data. The rest unaligned (if any) will be read */ - /* and copied to a TailBuffer */ - LengthToCopy = (_u16)(ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (3)); - AlignedLengthRecv = (_u16)(ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (~3)); - if( AlignedLengthRecv >= 4) - { - NWP_IF_READ_CHECK(g_pCB->FD, &buffer[ExpArgSize], AlignedLengthRecv); - } - /* copy the unaligned part, if any */ - if( LengthToCopy > 0) - { - NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4); - /* copy TailBuffer unaligned part (1/2/3 bytes) */ - sl_Memcpy(&buffer[ExpArgSize + AlignedLengthRecv], TailBuffer, LengthToCopy); - } - } - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - } - else -#endif - { - /* if _SlDrvFindAndSetActiveObj returned an error, release the protection lock, and return. */ - if(RetVal < 0) - { - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return SL_API_ABORTED; - } - - /* Verify data is waited on this socket. The pArgs should have been set by _SlDrvDataReadOp(). */ - VERIFY_SOCKET_CB(NULL != ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pData))->pArgs); - - sl_Memcpy( ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pArgs, &uBuf.TempBuf[4], RECV_ARGS_SIZE); - - if(ExpArgSize > (_u8)RECV_ARGS_SIZE) - { - NWP_IF_READ_CHECK(g_pCB->FD, - ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pArgs + RECV_ARGS_SIZE, - ExpArgSize - RECV_ARGS_SIZE); - } - - /* Here g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pData contains requested(expected) Recv/Recvfrom DataSize. */ - /* Overwrite requested DataSize with actual one. */ - /* If error is received, this information will be read from arguments. */ - if(ACT_DATA_SIZE(&uBuf.TempBuf[4]) > 0) - { - VERIFY_SOCKET_CB(NULL != ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pData); - - /* Read 4 bytes aligned from interface */ - /* therefore check the requested length and read only */ - /* 4 bytes aligned data. The rest unaligned (if any) will be read */ - /* and copied to a TailBuffer */ - LengthToCopy = (_u16)(ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (3)); - AlignedLengthRecv = (_u16)(ACT_DATA_SIZE(&uBuf.TempBuf[4]) & (~3)); - if( AlignedLengthRecv >= 4) - { - NWP_IF_READ_CHECK(g_pCB->FD,((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pData, AlignedLengthRecv); - } - /* copy the unaligned part, if any */ - if( LengthToCopy > 0) - { - NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4); - /* copy TailBuffer unaligned part (1/2/3 bytes) */ - sl_Memcpy(((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->pData + AlignedLengthRecv,TailBuffer,LengthToCopy); - } - } - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - SL_DRV_PROTECTION_OBJ_UNLOCK(); - } - - break; - } - - case CMD_RESP_CLASS: - { - /* Some commands pass a maximum arguments size. */ - /* In this case Driver will send extra dummy patterns to NWP if */ - /* the response message is smaller than maximum. */ - /* When RxDescLen is not exact, using RxPayloadLen is forbidden! */ - /* If such case cannot be avoided - parse message here to detect */ - /* arguments/payload border. */ - NWP_IF_READ_CHECK(g_pCB->FD, - g_pCB->FunctionParams.pTxRxDescBuff, - _SL_PROTOCOL_ALIGN_SIZE(g_pCB->FunctionParams.pCmdCtrl->RxDescLen)); - - if((NULL != g_pCB->FunctionParams.pCmdExt) && (0 != g_pCB->FunctionParams.pCmdExt->RxPayloadLen)) - { - /* Actual size of command's response payload: - */ - _i16 ActDataSize = (_i16)(RSP_PAYLOAD_LEN(uBuf.TempBuf) - g_pCB->FunctionParams.pCmdCtrl->RxDescLen); - - g_pCB->FunctionParams.pCmdExt->ActualRxPayloadLen = ActDataSize; - - /* Check that the space prepared by user for the response data is sufficient. */ - if(ActDataSize <= 0) - { - g_pCB->FunctionParams.pCmdExt->RxPayloadLen = 0; - } - else - { - /* In case the user supplied Rx buffer length which is smaller then the received data length, copy according to user length */ - if (ActDataSize > g_pCB->FunctionParams.pCmdExt->RxPayloadLen) - { - LengthToCopy = (_u16)(g_pCB->FunctionParams.pCmdExt->RxPayloadLen & (3)); - AlignedLengthRecv = (_u16)(g_pCB->FunctionParams.pCmdExt->RxPayloadLen & (~3)); - } - else - { - LengthToCopy = (_u16)(ActDataSize & (3)); - AlignedLengthRecv = (_u16)(ActDataSize & (~3)); - } - /* Read 4 bytes aligned from interface */ - /* therefore check the requested length and read only */ - /* 4 bytes aligned data. The rest unaligned (if any) will be read */ - /* and copied to a TailBuffer */ - - if( AlignedLengthRecv >= 4) - { - NWP_IF_READ_CHECK(g_pCB->FD, - g_pCB->FunctionParams.pCmdExt->pRxPayload, - AlignedLengthRecv ); - - } - /* copy the unaligned part, if any */ - if( LengthToCopy > 0) - { - NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer,4); - /* copy TailBuffer unaligned part (1/2/3 bytes) */ - sl_Memcpy(g_pCB->FunctionParams.pCmdExt->pRxPayload + AlignedLengthRecv, - TailBuffer, - LengthToCopy); - ActDataSize = ActDataSize-4; - } - /* In case the user supplied Rx buffer length which is smaller then the received data length, dump the rest */ - if (ActDataSize > g_pCB->FunctionParams.pCmdExt->RxPayloadLen) - { - /* calculate the rest of the data size to dump */ - AlignedLengthRecv = (_u16)( (ActDataSize + 3 - g_pCB->FunctionParams.pCmdExt->RxPayloadLen) & (~3) ); - while( AlignedLengthRecv > 0) - { - NWP_IF_READ_CHECK(g_pCB->FD,TailBuffer, 4 ); - AlignedLengthRecv = AlignedLengthRecv - 4; - } - } - } - } - - break; - } - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - case MULTI_SELECT_RESP_CLASS: - { - /* In case we read Select Response from NWP, and we're not waiting for - * command complete, that means that a select command was send for a select Joiner. */ - - _u8 Idx; - - NWP_IF_READ_CHECK(g_pCB->FD, - (_u8*)(&g_pCB->MultiSelectCB.SelectCmdResp), - _SL_PROTOCOL_ALIGN_SIZE(sizeof(_BasicResponse_t))); - - if(g_pCB->MultiSelectCB.SelectCmdResp.status != SL_RET_CODE_OK) - { - /* If a select response returns without Status O.K, this means that - * something terribly wrong have happen. So we stop all waiting select callers, - * and return command error. */ - g_pCB->MultiSelectCB.ActiveSelect = FALSE; - - for(Idx = 0 ; Idx < MAX_CONCURRENT_ACTIONS ; Idx++) - { - if(g_pCB->MultiSelectCB.SelectEntry[Idx] != NULL) - { - sl_SyncObjSignal(&g_pCB->ObjPool[Idx].SyncObj); - } - } - /* Clean all table entries, and clear the global read/write fds */ - _SlDrvMemZero(&g_pCB->MultiSelectCB, sizeof(_SlMultiSelectCB_t)); - } - - break; - } -#endif - - default: - /* DUMMY_MSG_CLASS: Flow control message has no payload. */ - break; - } - - _SL_DBG_CNT_INC(MsgCnt.Read); - - /* Unmask Interrupt call */ - sl_IfUnMaskIntHdlr(); - - return SL_OS_RET_CODE_OK; -} - - -/* ******************************************************************************/ -/* _SlDrvAsyncEventGenericHandler */ -/* ******************************************************************************/ -static void _SlDrvAsyncEventGenericHandler(_u8 bInCmdContext, _u8 *pAsyncBuffer) -{ - _u32 SlAsyncEvent = 0; - _u8 OpcodeFound = FALSE; - _u8 i; - - _u32* pEventLocation = NULL; /* This pointer will override the async buffer with the translated event type */ - _SlResponseHeader_t *pHdr = (_SlResponseHeader_t *)pAsyncBuffer; - - - /* if no async event registered nothing to do..*/ - if (g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler == NULL) - { - return; - } - - /* In case we in the middle of the provisioning, filter out - all the async events except the provisioning ones */ - if ( (( SL_IS_PROVISIONING_ACTIVE || SL_IS_PROVISIONING_INITIATED_BY_USER) && !(SL_IS_PROVISIONING_API_ALLOWED)) && - (pHdr->GenHeader.Opcode != SL_OPCODE_WLAN_PROVISIONING_STATUS_ASYNC_EVENT) && - (pHdr->GenHeader.Opcode != SL_OPCODE_DEVICE_RESET_REQUEST_ASYNC_EVENT) && - (pHdr->GenHeader.Opcode != SL_OPCODE_DEVICE_INITCOMPLETE) && - (pHdr->GenHeader.Opcode != SL_OPCODE_WLAN_PROVISIONING_PROFILE_ADDED_ASYNC_RESPONSE) && - (pHdr->GenHeader.Opcode != SL_OPCODE_NETAPP_REQUEST) ) - { - return; - } - - /* Iterate through all the opcode in the table */ - for (i=0; i< (_u8)(sizeof(OpcodeTranslateTable) / sizeof(OpcodeKeyVal_t)); i++) - { - if (OpcodeTranslateTable[i].opcode == pHdr->GenHeader.Opcode) - { - SlAsyncEvent = OpcodeTranslateTable[i].event; - OpcodeFound = TRUE; - break; - } - } - - /* No Async event found in the table */ - if (OpcodeFound == FALSE) - { - if ((pHdr->GenHeader.Opcode & SL_OPCODE_SILO_MASK) == SL_OPCODE_SILO_DEVICE) - { - DeviceEventInfo_t deviceEvent; - - deviceEvent.pAsyncMsgBuff = pAsyncBuffer; - deviceEvent.bInCmdContext = bInCmdContext; - - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(&deviceEvent); - } - else - { - /* This case handles all the async events handlers of the DEVICE & SOCK Silos which are handled internally. - For these cases we send the async even buffer as is */ - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(pAsyncBuffer); - } - } - else - { - /* calculate the event type location to be filled in the async buffer */ - pEventLocation = (_u32*)(pAsyncBuffer + sizeof (_SlResponseHeader_t) - sizeof(SlAsyncEvent)); - - /* Override the async buffer (before the data starts ) with our event type */ - *pEventLocation = SlAsyncEvent; - - /* call the event handler registered by the user with our async buffer which now holds - the User's event type and its related data */ - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler(pEventLocation); - - } -} - -/* ******************************************************************************/ -/* _SlDrvMsgReadCmdCtx */ -/* ******************************************************************************/ -static _SlReturnVal_t _SlDrvMsgReadCmdCtx(_u16 cmdOpcode, _u8 IsLockRequired) -{ - _u32 CmdCmpltTimeout; - _i16 RetVal=0; - _u8 *pAsyncBuf = NULL; - - /* the sl_FsOpen/sl_FsProgram APIs may take long time */ - if ((cmdOpcode == SL_OPCODE_NVMEM_FILEOPEN) || (cmdOpcode == SL_OPCODE_NVMEM_NVMEMFSPROGRAMMINGCOMMAND)) - { - CmdCmpltTimeout = ((_u32)SL_DRIVER_TIMEOUT_LONG * 10); - } - else - { - /* For any FS command, the timeout will be the long one as the commnad response holds the full response data */ - CmdCmpltTimeout = (SL_OPCODE_SILO_FS & cmdOpcode)? (_u32)(SL_DRIVER_TIMEOUT_LONG) : (_u32)SL_DRIVER_TIMEOUT_SHORT; - } - - /* after command response is received and WaitForCmdResp */ - /* flag is set FALSE, it is necessary to read out all */ - /* Async messages in Commands context, because ssiDma_IsrHandleSignalFromSlave */ - /* could have dispatched some Async messages to g_NwpIf.CmdSyncObj */ - /* after command response but before this response has been processed */ - /* by spi_singleRead and WaitForCmdResp was set FALSE. */ - while (TRUE == g_pCB->WaitForCmdResp) - { - if(_SL_PENDING_RX_MSG(g_pCB)) - { - _u16 outMsgLen = 0; - - RetVal = _SlDrvMsgRead(&outMsgLen,&pAsyncBuf); - - if (RetVal != SL_OS_RET_CODE_OK) - { - g_pCB->WaitForCmdResp = FALSE; - - if ((IsLockRequired) && (RetVal != SL_API_ABORTED)) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - } - - return SL_API_ABORTED; - } - g_pCB->RxDoneCnt++; - - if (CMD_RESP_CLASS == g_pCB->FunctionParams.AsyncExt.RxMsgClass) - { - g_pCB->WaitForCmdResp = FALSE; - /* In case CmdResp has been read without waiting on CmdSyncObj - that */ - /* Sync object. That to prevent old signal to be processed. */ - SL_DRV_SYNC_OBJ_CLEAR(&g_pCB->CmdSyncObj); - } - else if (ASYNC_EVT_CLASS == g_pCB->FunctionParams.AsyncExt.RxMsgClass) - { - -#ifdef SL_PLATFORM_MULTI_THREADED - /* Do not handle async events in command context */ - /* All async events data will be stored in list and handled in spawn context */ - RetVal = _SlSpawnMsgListInsert(outMsgLen, pAsyncBuf); - if (SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR == RetVal) - { - _SlFindAndReleasePendingCmd(); - } - -#else - _SlDrvAsyncEventGenericHandler(TRUE, pAsyncBuf); -#endif - -#ifdef SL_MEMORY_MGMT_DYNAMIC - sl_Free(pAsyncBuf); -#else - pAsyncBuf = NULL; -#endif - } -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - else if(MULTI_SELECT_RESP_CLASS == g_pCB->FunctionParams.AsyncExt.RxMsgClass) - { - sl_SyncObjSignal(&g_pCB->MultiSelectCB.SelectSyncObj); - } -#endif - } - else - { - /* CmdSyncObj will be signaled by IRQ */ - RetVal = sl_SyncObjWait(&g_pCB->CmdSyncObj, CmdCmpltTimeout); - if (RetVal != 0) - { - g_pCB->WaitForCmdResp = FALSE; - - if (IsLockRequired) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - } - - /* only if device started handle the fatal error */ - if (SL_IS_DEVICE_STARTED) - { - _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_NO_CMD_ACK, cmdOpcode, (_u32)CmdCmpltTimeout); - } - - return SL_API_ABORTED; - } - } - } - -#ifdef SL_PLATFORM_MULTI_THREADED - if (_SlSpawnMsgListGetCount() > 0) - { - /* signal the spawn task to process the pending async events received during the cmd */ - sl_Spawn((_SlSpawnEntryFunc_t)_SlDrvMsgReadSpawnCtx, NULL, SL_SPAWN_FLAG_FROM_CMD_PROCESS); - } -#endif - - /* If there are more pending Rx Msgs after CmdResp is received, */ - /* that means that these are Async, Dummy or Read Data Msgs. */ - /* Spawn _SlDrvMsgReadSpawnCtx to trigger reading these messages from */ - /* Temporary context. */ - /* sl_Spawn is activated, using a different context */ - if (IsLockRequired) - { - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - } - - if(_SL_PENDING_RX_MSG(g_pCB)) - { - sl_Spawn((_SlSpawnEntryFunc_t)_SlDrvMsgReadSpawnCtx, NULL, SL_SPAWN_FLAG_FROM_CMD_CTX); - } - - return SL_OS_RET_CODE_OK; -} - -/* ******************************************************************************/ -/* _SlDrvMsgReadSpawnCtx */ -/* ******************************************************************************/ -_SlReturnVal_t _SlDrvMsgReadSpawnCtx(void *pValue) -{ - _SlReturnVal_t RetVal = SL_OS_RET_CODE_OK; - _u16 outMsgLen = 0; - _u8 *pAsyncBuf = NULL; - -#ifdef SL_POLLING_MODE_USED - - /* for polling based systems */ - do - { - if (GlobalLockObj != NULL) - { - RetVal = sl_LockObjLock(&GlobalLockObj, 0); - - if (SL_OS_RET_CODE_OK != RetVal ) - { - if (TRUE == g_pCB->WaitForCmdResp) - { - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->CmdSyncObj); - return SL_RET_CODE_OK; - } - } - - } - - } - while (SL_OS_RET_CODE_OK != RetVal); - -#else - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_NONE); -#endif - -#ifndef SL_PLATFORM_MULTI_THREADED - /* set the global lock owner (spawn context) */ - _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_SPAWN); -#endif - /* pValue parameter is currently not in use */ - (void)pValue; - - /* Messages might have been read by CmdResp context. Therefore after */ - /* getting LockObj, check again where the Pending RX Msg is still present. */ - if(FALSE == (_SL_PENDING_RX_MSG(g_pCB))) - { -#ifndef SL_PLATFORM_MULTI_THREADED - /* clear the global lock owner (spawn context) */ - _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_APP); -#endif - SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); - - return SL_RET_CODE_OK; - } - - if (SL_IS_DEVICE_STARTED || SL_IS_DEVICE_START_IN_PROGRESS) - { - - RetVal = _SlDrvMsgRead(&outMsgLen, &pAsyncBuf); - - if (RetVal != SL_OS_RET_CODE_OK) - { - if (RetVal != SL_API_ABORTED) - { - #ifndef SL_PLATFORM_MULTI_THREADED - /* clear the global lock owner (spawn context) */ - _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_APP); - #endif - SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); - } - return SL_API_ABORTED; - } - - g_pCB->RxDoneCnt++; - - switch(g_pCB->FunctionParams.AsyncExt.RxMsgClass) - { - case ASYNC_EVT_CLASS: - /* If got here and protected by LockObj a message is waiting */ - /* to be read */ - VERIFY_PROTOCOL(NULL != pAsyncBuf); - - - _SlDrvAsyncEventGenericHandler(FALSE, pAsyncBuf); - - #ifdef SL_MEMORY_MGMT_DYNAMIC - sl_Free(pAsyncBuf); - #else - pAsyncBuf = NULL; - #endif - break; - case DUMMY_MSG_CLASS: - case RECV_RESP_CLASS: - /* These types are legal in this context. Do nothing */ - break; - case CMD_RESP_CLASS: - /* Command response is illegal in this context - */ - /* One exception exists though: 'Select' response (SL_OPCODE_SOCKET_SELECTRESPONSE) Opcode = 0x1407 */ - break; - #if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - case MULTI_SELECT_RESP_CLASS: - /* If everything's OK, we signal for any other joiners to call 'Select'.*/ - sl_SyncObjSignal(&g_pCB->MultiSelectCB.SelectSyncObj); - break; - #endif - default: - _SL_ASSERT_ERROR(0, SL_API_ABORTED); - } - #ifndef SL_PLATFORM_MULTI_THREADED - /* clear the global lock owner (spawn context) */ - _SlDrvSetGlobalLockOwner(GLOBAL_LOCK_CONTEXT_OWNER_APP); - #endif - SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); - return(SL_RET_CODE_OK); - } - return(SL_RET_CODE_INTERFACE_CLOSED); -} - -/* - -#define SL_OPCODE_SILO_DEVICE ( 0x0 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_WLAN ( 0x1 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_SOCKET ( 0x2 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_NETAPP ( 0x3 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_FS ( 0x4 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_NETCFG ( 0x5 << SL_OPCODE_SILO_OFFSET ) - -*/ - -/* The Lookup table below holds the event handlers to be called according to the incoming - RX message SILO type */ -static const _SlSpawnEntryFunc_t RxMsgClassLUT[] = { - (_SlSpawnEntryFunc_t)_SlDeviceEventHandler, /* SL_OPCODE_SILO_DEVICE */ -#if defined(slcb_WlanEvtHdlr) || defined(EXT_LIB_REGISTERED_WLAN_EVENTS) - (_SlSpawnEntryFunc_t)_SlDrvHandleWlanEvents, /* SL_OPCODE_SILO_WLAN */ -#else - NULL, -#endif -#if defined (slcb_SockEvtHdlr) || defined(EXT_LIB_REGISTERED_SOCK_EVENTS) - (_SlSpawnEntryFunc_t)_SlDrvHandleSockEvents, /* SL_OPCODE_SILO_SOCKET */ -#else - NULL, -#endif -#if defined(slcb_NetAppEvtHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_EVENTS) - (_SlSpawnEntryFunc_t)_SlDrvHandleNetAppEvents, /* SL_OPCODE_SILO_NETAPP */ -#else - NULL, -#endif - NULL, /* SL_OPCODE_SILO_FS */ - NULL, /* SL_OPCODE_SILO_NETCFG */ - (_SlSpawnEntryFunc_t)_SlNetUtilHandleAsync_Cmd, /* SL_OPCODE_SILO_NETUTIL */ - NULL -}; - - -/* ******************************************************************************/ -/* _SlDrvClassifyRxMsg */ -/* ******************************************************************************/ -static _SlReturnVal_t _SlDrvClassifyRxMsg( - _SlOpcode_t Opcode) -{ - _SlSpawnEntryFunc_t AsyncEvtHandler = NULL; - _SlRxMsgClass_e RxMsgClass = CMD_RESP_CLASS; - _u8 Silo; - - - if (0 == (SL_OPCODE_SYNC & Opcode)) - { /* Async event has received */ - - if (SL_OPCODE_DEVICE_DEVICEASYNCDUMMY == Opcode) - { - RxMsgClass = DUMMY_MSG_CLASS; - } - else if ( (SL_OPCODE_SOCKET_RECVASYNCRESPONSE == Opcode) || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE == Opcode) - || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6 == Opcode) - ) - { - RxMsgClass = RECV_RESP_CLASS; - } - else - { - /* This is Async Event class message */ - RxMsgClass = ASYNC_EVT_CLASS; - - /* Despite the fact that 4 bits are allocated in the SILO field, we actually have only 6 SILOs - So we can use the 8 options of SILO in look up table */ - Silo = (_u8)((Opcode >> SL_OPCODE_SILO_OFFSET) & 0x7); - - VERIFY_PROTOCOL(Silo < (_u8)(sizeof(RxMsgClassLUT)/sizeof(_SlSpawnEntryFunc_t))); - - /* Set the SILO's async event handler according to the LUT - If this specific event requires a direct async event handler, the - async event handler will be overwrite according to the action table */ - AsyncEvtHandler = RxMsgClassLUT[Silo]; - - if ((SL_OPCODE_NETAPP_HTTPGETTOKENVALUE == Opcode) || (SL_OPCODE_NETAPP_HTTPPOSTTOKENVALUE == Opcode) || - (SL_OPCODE_NETAPP_REQUEST == Opcode) || (SL_OPCODE_NETAPP_RESPONSE == Opcode) || (SL_OPCODE_NETAPP_SEND == Opcode)) - { - AsyncEvtHandler = _SlNetAppEventHandler; - } - else if (SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE == Opcode) - { - AsyncEvtHandler = (_SlSpawnEntryFunc_t)_SlNetAppHandleAsync_PingResponse; - } - } - } -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - else if((Opcode == SL_OPCODE_SOCKET_SELECTRESPONSE) && - (g_pCB->FunctionParams.pCmdCtrl->Opcode != SL_OPCODE_SOCKET_SELECT)) - { - /* Only in case this response came from a 'Select' sent in an Async event, Mark the message as MULTI_SELECT_RESPONSE */ - RxMsgClass = MULTI_SELECT_RESP_CLASS; - } -#endif - g_pCB->FunctionParams.AsyncExt.RxMsgClass = RxMsgClass; - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = AsyncEvtHandler; - - return SL_RET_CODE_OK; -} - - -/* ******************************************************************************/ -/* _SlDrvRxHdrRead */ -/* ******************************************************************************/ -static _SlReturnVal_t _SlDrvRxHdrRead(_u8 *pBuf) -{ - _u8 ShiftIdx; - _u8 TimeoutState = TIMEOUT_STATE_INIT_VAL; - _u8 SearchSync = TRUE; - _u8 SyncPattern[4]; -#if (defined(slcb_GetTimestamp)) - _SlTimeoutParams_t TimeoutInfo={0}; -#endif - -#ifndef SL_IF_TYPE_UART - /* 1. Write CNYS pattern to NWP when working in SPI mode only */ - NWP_IF_WRITE_CHECK(g_pCB->FD, (_u8 *)&g_H2NCnysPattern.Short, SYNC_PATTERN_LEN); -#endif - -#if (defined(slcb_GetTimestamp)) - _SlDrvStartMeasureTimeout(&TimeoutInfo, SYNC_PATTERN_TIMEOUT_IN_MSEC); -#endif - - /* 2. Read 8 bytes (protocol aligned) - expected to be the sync pattern */ - NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[0], 8); - - /* read while first 4 bytes are different than last 4 bytes */ - while ( *(_u32 *)&pBuf[0] == *(_u32 *)&pBuf[4]) - { - NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[4], 4); -#if (defined(slcb_GetTimestamp)) - if (_SlDrvIsTimeoutExpired(&TimeoutInfo)) - { - return SL_API_ABORTED; - } -#endif - } - - /* scan for the sync pattern till found or timeout elapsed (if configured) */ - while (SearchSync && TimeoutState) - { - /* scan till we get the real sync pattern */ - for (ShiftIdx =0; ShiftIdx <=4 ; ShiftIdx++) - { - /* copy to local variable to ensure starting address which is 4-bytes aligned */ - sl_Memcpy(&SyncPattern[0], &pBuf[ShiftIdx], 4); - - /* sync pattern found so complete the read to 4 bytes aligned */ - if (N2H_SYNC_PATTERN_MATCH(&SyncPattern[0], g_pCB->TxSeqNum)) - { - /* copy the bytes following the sync pattern to the buffer start */ - sl_Memcpy(&pBuf[0], &pBuf[ShiftIdx + SYNC_PATTERN_LEN], 4); - - if (ShiftIdx != 0) - { - /* read the rest of the bytes (only if wer'e not aligned) (expected to complete the opcode + length fields ) */ - NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[SYNC_PATTERN_LEN - ShiftIdx], ShiftIdx); - } - - /* here we except to get the opcode + length or false doubled sync..*/ - SearchSync = FALSE; - break; - } - } - - if (SearchSync == TRUE) - { - /* sync not found move top 4 bytes to bottom */ - *(_u32 *)&pBuf[0] = *(_u32 *)&pBuf[4]; - - /* read 4 more bytes to the buffer top */ - NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[4], 4); - } - - #if (defined (slcb_GetTimestamp)) - - /* if we got here after first timeout detection, it means that we gave - one more chance, and we can now exit the loop with timeout expiry */ - if (TIMEOUT_ONE_MORE_SHOT == TimeoutState) - { - TimeoutState = TIMEOUT_STATE_EXPIRY; - break; - } - - /* Timeout occurred. do not break now as we want to give one more chance in case - the timeout occurred due to some external context switch */ - if (_SlDrvIsTimeoutExpired(&TimeoutInfo)) - { - TimeoutState = TIMEOUT_ONE_MORE_SHOT; - } - -#endif - } /* end of while */ - -#if (defined (slcb_GetTimestamp)) - if (TIMEOUT_STATE_EXPIRY == TimeoutState) - { - return SL_API_ABORTED; - } -#endif - - /* 6. Scan for Double pattern. */ - while ( N2H_SYNC_PATTERN_MATCH(pBuf, g_pCB->TxSeqNum) ) - { - _SL_DBG_CNT_INC(Work.DoubleSyncPattern); - NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[0], SYNC_PATTERN_LEN); - } - g_pCB->TxSeqNum++; - - /* 7. Here we've read Generic Header (4 bytes opcode+length). - * Now Read the Resp Specific header (4 more bytes). */ - NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[SYNC_PATTERN_LEN], _SL_RESP_SPEC_HDR_SIZE); - - return SL_RET_CODE_OK; -} - -/* ***************************************************************************** */ -/* _SlDrvBasicCmd */ -/* ***************************************************************************** */ -typedef union -{ - _BasicResponse_t Rsp; -}_SlBasicCmdMsg_u; - - -_SlReturnVal_t _SlDrvBasicCmd(_SlOpcode_t Opcode) -{ - _SlBasicCmdMsg_u Msg; - _SlCmdCtrl_t CmdCtrl; - - _SlDrvMemZero(&Msg, (_u16)sizeof(_SlBasicCmdMsg_u)); - CmdCtrl.Opcode = Opcode; - CmdCtrl.TxDescLen = 0; - CmdCtrl.RxDescLen = (_SlArgSize_t)sizeof(_BasicResponse_t); - - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, &Msg, NULL)); - - return (_SlReturnVal_t)Msg.Rsp.status; -} - -/***************************************************************************** - _SlDrvCmdSend_noLock - Send SL command without waiting for command response - This function is unprotected and the caller should make - sure global lock is active. Used to send data within async event handler, where the driver is already locked. -*****************************************************************************/ -_SlReturnVal_t _SlDrvCmdSend_noLock( - _SlCmdCtrl_t *pCmdCtrl , - void *pTxRxDescBuff , - _SlCmdExt_t *pCmdExt) -{ - _SlReturnVal_t RetVal; - _u8 WaitForCmdRespOriginalVal; - - _SlFunctionParams_t originalFuncParms; - - /* save the current RespWait flag before clearing it */ - WaitForCmdRespOriginalVal = g_pCB->WaitForCmdResp; - - /* save the current command paramaters */ - sl_Memcpy(&originalFuncParms, &g_pCB->FunctionParams, sizeof(_SlFunctionParams_t)); - - g_pCB->WaitForCmdResp = FALSE; - - SL_TRACE0(DBG_MSG, MSG_312, "_SlDrvCmdSend_noLock: call _SlDrvMsgWrite"); - - /* send the message */ - RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); - - /* restore the original RespWait flag */ - g_pCB->WaitForCmdResp = WaitForCmdRespOriginalVal; - - /* restore the original command paramaters */ - sl_Memcpy(&g_pCB->FunctionParams, &originalFuncParms, sizeof(_SlFunctionParams_t)); - - return RetVal; -} -/***************************************************************************** - _SlDrvCmdSend_noWait - Send SL command without waiting for command response - This function send command form any possiable context, without waiting. -*****************************************************************************/ -_SlReturnVal_t _SlDrvCmdSend_noWait( - _SlCmdCtrl_t *pCmdCtrl , - void *pTxRxDescBuff , - _SlCmdExt_t *pCmdExt) -{ - _SlReturnVal_t RetVal; - - _SlFunctionParams_t originalFuncParms; - - SL_TRACE1(DBG_MSG, MSG_312, "\n\r_SlDrvCmdSend_noLock: call _SlDrvMsgWrite: %x\n\r", pCmdCtrl->Opcode); - - /* Save the current function parameters */ - sl_Memcpy(&originalFuncParms, &g_pCB->FunctionParams, sizeof(_SlFunctionParams_t)); - - /* send the message */ - RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); - - /* Restore */ - sl_Memcpy(&g_pCB->FunctionParams, &originalFuncParms, sizeof(_SlFunctionParams_t)); - - return RetVal; -} - -/***************************************************************************** - _SlDrvCmdSend - Send SL command without waiting for command response -*****************************************************************************/ -_SlReturnVal_t _SlDrvCmdSend( - _SlCmdCtrl_t *pCmdCtrl , - void *pTxRxDescBuff , - _SlCmdExt_t *pCmdExt) -{ - _SlReturnVal_t RetVal; - - _SlDrvObjLockWaitForever(&GlobalLockObj); - - g_pCB->WaitForCmdResp = FALSE; - - SL_TRACE1(DBG_MSG, MSG_312, "_SlDrvCmdSend: call _SlDrvMsgWrite:%x", pCmdCtrl->Opcode); - - /* send the message */ - RetVal = _SlDrvMsgWrite(pCmdCtrl, pCmdExt, pTxRxDescBuff); - - _SlDrvObjUnLock(&GlobalLockObj); - - return RetVal; -} - - -/* ***************************************************************************** */ -/* _SlDrvProtectAsyncRespSetting */ -/* ***************************************************************************** */ -_SlReturnVal_t _SlDrvProtectAsyncRespSetting(_u8 *pAsyncRsp, _SlActionID_e ActionID, _u8 SocketID) -{ - _i16 ObjIdx; - - /* Use Obj to issue the command, if not available try later */ - ObjIdx = _SlDrvWaitForPoolObj(ActionID, SocketID); - - if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) - { - return SL_RET_CODE_STOP_IN_PROGRESS; - } - else if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return MAX_CONCURRENT_ACTIONS; - } - else - { - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - g_pCB->ObjPool[ObjIdx].pRespArgs = pAsyncRsp; - SL_DRV_PROTECTION_OBJ_UNLOCK(); - } - - return ObjIdx; -} - - -/* ***************************************************************************** */ -/* _SlDrvIsSpawnOwnGlobalLock */ -/* ***************************************************************************** */ -#if (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) -_u8 _SlDrvIsSpawnOwnGlobalLock() -{ -#ifdef SL_PLATFORM_MULTI_THREADED - _u32 ThreadId = (_i32)pthread_self(); - return _SlInternalIsItSpawnThread(ThreadId); -#else - return (gGlobalLockContextOwner == GLOBAL_LOCK_CONTEXT_OWNER_SPAWN); -#endif -} -#endif -/* ***************************************************************************** */ -/* _SlDrvWaitForPoolObj */ -/* ***************************************************************************** */ -_SlReturnVal_t _SlDrvWaitForPoolObj(_u8 ActionID, _u8 SocketID) -{ - _u8 CurrObjIndex = MAX_CONCURRENT_ACTIONS; - - /* Get free object */ - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - if (MAX_CONCURRENT_ACTIONS > g_pCB->FreePoolIdx) - { - /* save the current obj index */ - CurrObjIndex = g_pCB->FreePoolIdx; - /* set the new free index */ - if (MAX_CONCURRENT_ACTIONS > g_pCB->ObjPool[CurrObjIndex].NextIndex) - { - g_pCB->FreePoolIdx = g_pCB->ObjPool[CurrObjIndex].NextIndex; - } - else - { - /* No further free actions available */ - g_pCB->FreePoolIdx = MAX_CONCURRENT_ACTIONS; - } - } - else - { - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return CurrObjIndex; - } - g_pCB->ObjPool[CurrObjIndex].ActionID = (_u8)ActionID; - if (SL_MAX_SOCKETS > SocketID) - { - g_pCB->ObjPool[CurrObjIndex].AdditionalData = SocketID; - } - /*In case this action is socket related, SocketID bit will be on - In case SocketID is set to SL_MAX_SOCKETS, the socket is not relevant to the action. In that case ActionID bit will be on */ - while ( ( (SL_MAX_SOCKETS > SocketID) && (g_pCB->ActiveActionsBitmap & (1<ActiveActionsBitmap & ( MULTI_SELECT_MASK & (1<ObjPool[CurrObjIndex].ActionID = 0; - g_pCB->ObjPool[CurrObjIndex].AdditionalData = SL_MAX_SOCKETS; - g_pCB->FreePoolIdx = CurrObjIndex; - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return MAX_CONCURRENT_ACTIONS; - } -#endif - /* action in progress - move to pending list */ - g_pCB->ObjPool[CurrObjIndex].NextIndex = g_pCB->PendingPoolIdx; - g_pCB->PendingPoolIdx = CurrObjIndex; - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - /* wait for action to be free */ - (void)_SlDrvSyncObjWaitForever(&g_pCB->ObjPool[CurrObjIndex].SyncObj); - if (SL_IS_DEVICE_STOP_IN_PROGRESS) - { - OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->ObjPool[CurrObjIndex].SyncObj)); - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - g_pCB->NumOfDeletedSyncObj++; - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return SL_RET_CODE_STOP_IN_PROGRESS; - } - - /* set params and move to active (remove from pending list at _SlDrvReleasePoolObj) */ - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - } - - /* mark as active. Set socket as active if action is on socket, otherwise mark action as active */ - if (SL_MAX_SOCKETS > SocketID) - { - g_pCB->ActiveActionsBitmap |= (1<ActiveActionsBitmap |= (1<ObjPool[CurrObjIndex].NextIndex = g_pCB->ActivePoolIdx; - g_pCB->ActivePoolIdx = CurrObjIndex; - - /* unlock */ - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - /* Increment the API in progress counter as this routine is called for every - API, which will be waiting for async event to be released */ - _SlDrvUpdateApiInProgress(API_IN_PROGRESS_UPDATE_INCREMENT); - - return CurrObjIndex; -} - -/* ******************************************************************************/ -/* _SlDrvReleasePoolObj */ -/* ******************************************************************************/ -_SlReturnVal_t _SlDrvReleasePoolObj(_u8 ObjIdx) -{ - _u8 PendingIndex; - - /* Delete sync obj in case stop in progress and return */ - if (SL_IS_DEVICE_STOP_IN_PROGRESS) - { - OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->ObjPool[ObjIdx].SyncObj)); - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - g_pCB->NumOfDeletedSyncObj++; - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return SL_RET_CODE_OK; - } - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - /* go over the pending list and release other pending action if needed */ - PendingIndex = g_pCB->PendingPoolIdx; - - while(MAX_CONCURRENT_ACTIONS > PendingIndex) - { - /* In case this action is socket related, SocketID is in use, otherwise will be set to SL_MAX_SOCKETS */ - if ( (g_pCB->ObjPool[PendingIndex].ActionID == g_pCB->ObjPool[ObjIdx].ActionID) && - ( (SL_MAX_SOCKETS == (g_pCB->ObjPool[PendingIndex].AdditionalData & SL_BSD_SOCKET_ID_MASK)) || - ((SL_MAX_SOCKETS > (g_pCB->ObjPool[ObjIdx].AdditionalData & SL_BSD_SOCKET_ID_MASK)) && ( (g_pCB->ObjPool[PendingIndex].AdditionalData & SL_BSD_SOCKET_ID_MASK) == (g_pCB->ObjPool[ObjIdx].AdditionalData & SL_BSD_SOCKET_ID_MASK) ))) ) - { - /* remove from pending list */ - _SlDrvRemoveFromList(&g_pCB->PendingPoolIdx, PendingIndex); - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[PendingIndex].SyncObj); - break; - } - PendingIndex = g_pCB->ObjPool[PendingIndex].NextIndex; - } - - if (SL_MAX_SOCKETS > (g_pCB->ObjPool[ObjIdx].AdditionalData & SL_BSD_SOCKET_ID_MASK)) - { - /* unset socketID */ - g_pCB->ActiveActionsBitmap &= ~(1<<(g_pCB->ObjPool[ObjIdx].AdditionalData & SL_BSD_SOCKET_ID_MASK)); - } - else - { - /* unset actionID */ - g_pCB->ActiveActionsBitmap &= ~(1<ObjPool[ObjIdx].ActionID); - } - - /* delete old data */ - g_pCB->ObjPool[ObjIdx].pRespArgs = NULL; - g_pCB->ObjPool[ObjIdx].ActionID = 0; - g_pCB->ObjPool[ObjIdx].AdditionalData = SL_MAX_SOCKETS; - - /* remove from active list */ - _SlDrvRemoveFromList(&g_pCB->ActivePoolIdx, ObjIdx); - - /* move to free list */ - g_pCB->ObjPool[ObjIdx].NextIndex = g_pCB->FreePoolIdx; - g_pCB->FreePoolIdx = ObjIdx; - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - /* Here we decrement the API in progrees counter as we just released the pool object, - which is held till the API is finished (async event received) */ - _SlDrvUpdateApiInProgress(API_IN_PROGRESS_UPDATE_DECREMENT); - return SL_RET_CODE_OK; -} - -/* ******************************************************************************/ -/* _SlDrvReleaseAllActivePendingPoolObj */ -/* ******************************************************************************/ -_SlReturnVal_t _SlDrvReleaseAllActivePendingPoolObj() -{ - _u8 ActiveIndex; - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - /* go over the active list and release each action with error */ - ActiveIndex = g_pCB->ActivePoolIdx; - - while (MAX_CONCURRENT_ACTIONS > ActiveIndex) - { - /* Set error in case sync objects release due to stop device command */ - if (g_pCB->ObjPool[ActiveIndex].ActionID == NETUTIL_CMD_ID) - { - ((_SlNetUtilCmdData_t *)(g_pCB->ObjPool[ActiveIndex].pRespArgs))->Status = SL_RET_CODE_STOP_IN_PROGRESS; - } - else if (g_pCB->ObjPool[ActiveIndex].ActionID == RECV_ID) - { - ((SlSocketResponse_t *)((_SlArgsData_t *)(g_pCB->ObjPool[ActiveIndex].pRespArgs))->pArgs)->StatusOrLen = SL_RET_CODE_STOP_IN_PROGRESS; - } - /* First 2 bytes of all async response holds the status except with NETUTIL_CMD_ID and RECV_ID */ - else - { - ((SlSocketResponse_t *)(g_pCB->ObjPool[ActiveIndex].pRespArgs))->StatusOrLen = SL_RET_CODE_STOP_IN_PROGRESS; - } - /* Signal the pool obj*/ - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[ActiveIndex].SyncObj); - ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex; - } - - /* go over the pending list and release each action */ - ActiveIndex = g_pCB->PendingPoolIdx; - - while (MAX_CONCURRENT_ACTIONS > ActiveIndex) - { - /* Signal the pool obj*/ - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[ActiveIndex].SyncObj); - ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex; - } - - /* Delete only unoccupied objects from the Free list, other obj (pending and active) - will be deleted from the relevant context */ - ActiveIndex = g_pCB->FreePoolIdx; - while(MAX_CONCURRENT_ACTIONS > ActiveIndex) - { - OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->ObjPool[ActiveIndex].SyncObj)); - g_pCB->NumOfDeletedSyncObj++; - ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex; - } - /* In case trigger select in progress, delete the sync obj */ -#if defined(slcb_SocketTriggerEventHandler) - if (MAX_CONCURRENT_ACTIONS != g_pCB->SocketTriggerSelect.Info.ObjPoolIdx) - { - OSI_RET_OK_CHECK(sl_SyncObjDelete(&g_pCB->ObjPool[g_pCB->SocketTriggerSelect.Info.ObjPoolIdx].SyncObj)); - g_pCB->NumOfDeletedSyncObj++; - } -#endif - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return SL_RET_CODE_OK; -} - -/* ******************************************************************************/ -/* _SlDrvRemoveFromList */ -/* ******************************************************************************/ -static void _SlDrvRemoveFromList(_u8 *ListIndex, _u8 ItemIndex) -{ - _u8 Idx; - - if (MAX_CONCURRENT_ACTIONS == g_pCB->ObjPool[*ListIndex].NextIndex) - { - *ListIndex = MAX_CONCURRENT_ACTIONS; - } - /* need to remove the first item in the list and therefore update the global which holds this index */ - else if (*ListIndex == ItemIndex) - { - *ListIndex = g_pCB->ObjPool[ItemIndex].NextIndex; - } - else - { - Idx = *ListIndex; - - while(MAX_CONCURRENT_ACTIONS > Idx) - { - /* remove from list */ - if (g_pCB->ObjPool[Idx].NextIndex == ItemIndex) - { - g_pCB->ObjPool[Idx].NextIndex = g_pCB->ObjPool[ItemIndex].NextIndex; - break; - } - - Idx = g_pCB->ObjPool[Idx].NextIndex; - } - } -} - - -/* ******************************************************************************/ -/* _SlDrvFindAndSetActiveObj */ -/* ******************************************************************************/ -static _SlReturnVal_t _SlDrvFindAndSetActiveObj(_SlOpcode_t Opcode, _u8 Sd) -{ - _u8 ActiveIndex; - - ActiveIndex = g_pCB->ActivePoolIdx; - /* go over the active list if exist to find obj waiting for this Async event */ - - while (MAX_CONCURRENT_ACTIONS > ActiveIndex) - { - /* unset the Ipv4\IPv6 bit in the opcode if family bit was set */ - if (g_pCB->ObjPool[ActiveIndex].AdditionalData & SL_NETAPP_FAMILY_MASK) - { - Opcode &= ~SL_OPCODE_IPV6; - } - - if ((g_pCB->ObjPool[ActiveIndex].ActionID == RECV_ID) && (Sd == g_pCB->ObjPool[ActiveIndex].AdditionalData) && - ( (SL_OPCODE_SOCKET_RECVASYNCRESPONSE == Opcode) || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE == Opcode) - || (SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6 == Opcode)) - ) - { - g_pCB->FunctionParams.AsyncExt.ActionIndex = ActiveIndex; - return SL_RET_CODE_OK; - } - /* In case this action is socket related, SocketID is in use, otherwise will be set to SL_MAX_SOCKETS */ - if ( (_SlActionLookupTable[ g_pCB->ObjPool[ActiveIndex].ActionID - MAX_SOCKET_ENUM_IDX].ActionAsyncOpcode == Opcode) && - ( ((Sd == (g_pCB->ObjPool[ActiveIndex].AdditionalData & SL_BSD_SOCKET_ID_MASK) ) && (SL_MAX_SOCKETS > Sd)) || (SL_MAX_SOCKETS == (g_pCB->ObjPool[ActiveIndex].AdditionalData & SL_BSD_SOCKET_ID_MASK)) ) ) - { - /* set handler */ - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = _SlActionLookupTable[ g_pCB->ObjPool[ActiveIndex].ActionID - MAX_SOCKET_ENUM_IDX].AsyncEventHandler; - g_pCB->FunctionParams.AsyncExt.ActionIndex = ActiveIndex; - return SL_RET_CODE_OK; - } - ActiveIndex = g_pCB->ObjPool[ActiveIndex].NextIndex; - } - - return SL_RET_OBJ_NOT_SET; -} - -#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) -void _SlDrvDispatchHttpServerEvents(SlNetAppHttpServerEvent_t *slHttpServerEvent, SlNetAppHttpServerResponse_t *slHttpServerResponse) -{ - _SlDrvHandleHttpServerEvents (slHttpServerEvent, slHttpServerResponse); -} -#endif - -#if defined(slcb_NetAppRequestHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) -void _SlDrvDispatchNetAppRequestEvents(SlNetAppRequest_t *slNetAppRequestEvent, SlNetAppResponse_t *slNetAppResponse) -{ - _SlDrvHandleNetAppRequestEvents (slNetAppRequestEvent, slNetAppResponse); -} -#endif - - -/* Wrappers for the object functions */ -_SlReturnVal_t _SlDrvSyncObjSignal(_SlSyncObj_t *pSyncObj) -{ - OSI_RET_OK_CHECK(sl_SyncObjSignal(pSyncObj)); - return SL_OS_RET_CODE_OK; -} - -_SlReturnVal_t _SlDrvObjLockWaitForever(_SlLockObj_t *pLockObj) -{ - OSI_RET_OK_CHECK(sl_LockObjLock(pLockObj, SL_OS_WAIT_FOREVER)); - return SL_OS_RET_CODE_OK; -} - -_SlReturnVal_t _SlDrvProtectionObjLockWaitForever(void) -{ - OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER)); - - return SL_OS_RET_CODE_OK; -} - -_SlReturnVal_t _SlDrvObjUnLock(_SlLockObj_t *pLockObj) -{ - OSI_RET_OK_CHECK(sl_LockObjUnlock(pLockObj)); - - return SL_OS_RET_CODE_OK; -} - -_SlReturnVal_t _SlDrvProtectionObjUnLock(void) -{ - OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj)); - return SL_OS_RET_CODE_OK; -} - -_SlReturnVal_t _SlDrvObjGlobalLockWaitForever(_u32 Flags) -{ - _SlReturnVal_t ret; - _u16 Opcode; - _u16 Silo; - _u8 UpdateApiInProgress = (Flags & GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS); - _u16 IsProvStopApi = (Flags & GLOBAL_LOCK_FLAGS_PROVISIONING_STOP_API); - - if (SL_IS_RESTART_REQUIRED) - { - return SL_API_ABORTED; - } - - gGlobalLockCntRequested++; - - ret = sl_LockObjLock(&GlobalLockObj, SL_OS_WAIT_FOREVER); - - /* start/stop device is in progress so return right away */ - if (SL_IS_DEVICE_START_IN_PROGRESS || SL_IS_DEVICE_STOP_IN_PROGRESS || SL_IS_PROVISIONING_IN_PROGRESS) - { - return ret; - } - - /* after the lock acquired check if API is allowed */ - if (0 == ret) - { - - Opcode = (Flags >> 16); - Silo = Opcode & ((0xF << SL_OPCODE_SILO_OFFSET)); - - /* After acquiring the lock, check if there is stop in progress */ - if (Opcode != SL_OPCODE_DEVICE_STOP_COMMAND) - { - _i16 Status = _SlDrvDriverIsApiAllowed(Silo); - - if (Status) - { - sl_LockObjUnlock(&GlobalLockObj); - return Status; - } - } - } - - /* if lock was successfully taken and increment of the API in progress is required */ - if ((0 == ret) && (UpdateApiInProgress)) - { - if (!SL_IS_PROVISIONING_ACTIVE || SL_IS_PROVISIONING_API_ALLOWED) - { - /* Increment the API in progress counter */ - _SlDrvUpdateApiInProgress(API_IN_PROGRESS_UPDATE_INCREMENT); - } - /* if we are in provisioning than don't abort the stop provisioning cmd.. */ - else if (FALSE == IsProvStopApi ) - { - /* Provisioning is active so release the lock immediately as - we do not want to allow more APIs to run. */ - SL_DRV_LOCK_GLOBAL_UNLOCK(TRUE); - return SL_RET_CODE_PROVISIONING_IN_PROGRESS; - } - } - - return ret; -} -_SlReturnVal_t _SlDrvGlobalObjUnLock(_u8 bDecrementApiInProgress) -{ - gGlobalLockCntReleased++; - - OSI_RET_OK_CHECK(sl_LockObjUnlock(&GlobalLockObj)); - - if (bDecrementApiInProgress) - { - _SlDrvUpdateApiInProgress(API_IN_PROGRESS_UPDATE_DECREMENT); - } - - return SL_OS_RET_CODE_OK; -} - -void _SlDrvMemZero(void* Addr, _u16 size) -{ - sl_Memset(Addr, 0, size); -} - - -void _SlDrvResetCmdExt(_SlCmdExt_t* pCmdExt) -{ - _SlDrvMemZero(pCmdExt, (_u16)sizeof (_SlCmdExt_t)); -} - - - -_SlReturnVal_t _SlDrvSyncObjWaitForever(_SlSyncObj_t *pSyncObj) -{ - _SlReturnVal_t RetVal = sl_SyncObjWait(pSyncObj, SL_OS_WAIT_FOREVER); - - /* if the wait is finished and we detect that restart is required (we in the middle of error handling), - than we should abort immediately from the current API command execution - */ - if (SL_IS_RESTART_REQUIRED) - { - return SL_API_ABORTED; - } - - return RetVal; -} - - -#if (defined(slcb_GetTimestamp)) - -void _SlDrvStartMeasureTimeout(_SlTimeoutParams_t *pTimeoutInfo, _u32 TimeoutInMsec) -{ - _SlDrvMemZero(pTimeoutInfo, sizeof (_SlTimeoutParams_t)); - - pTimeoutInfo->Total10MSecUnits = TimeoutInMsec / 10; - pTimeoutInfo->TSPrev = slcb_GetTimestamp(); -} - -_u8 _SlDrvIsTimeoutExpired(_SlTimeoutParams_t *pTimeoutInfo) -{ - _u32 TSCount; - - pTimeoutInfo->TSCurr = slcb_GetTimestamp(); - - if (pTimeoutInfo->TSCurr >= pTimeoutInfo->TSPrev) - { - pTimeoutInfo->DeltaTicks = pTimeoutInfo->TSCurr - pTimeoutInfo->TSPrev; - } - else - { - pTimeoutInfo->DeltaTicks = (SL_TIMESTAMP_MAX_VALUE - pTimeoutInfo->TSPrev) + pTimeoutInfo->TSCurr; - } - - TSCount = pTimeoutInfo->DeltaTicksReminder + pTimeoutInfo->DeltaTicks; - - - if (TSCount > SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS) - { - pTimeoutInfo->Total10MSecUnits -= (TSCount / SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS); - pTimeoutInfo->DeltaTicksReminder = TSCount % SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS; - - if (pTimeoutInfo->Total10MSecUnits > 0) - { - pTimeoutInfo->TSPrev = pTimeoutInfo->TSCurr; - } - else - { - return TRUE; - } - } - - return FALSE; -} - -#endif - -void _SlDrvHandleFatalError(_u32 errorId, _u32 info1, _u32 info2) -{ - _u8 i; - SlDeviceFatal_t FatalEvent; - - _SlDrvMemZero(&FatalEvent, sizeof(FatalEvent)); - - if (SL_IS_RESTART_REQUIRED) - { - return; - } - - /* set the restart flag */ - SL_SET_RESTART_REQUIRED; - - /* Upon the deletion of the mutex, all thread waiting on this - mutex will return immediately with an error (i.e. MUTEX_DELETED status) */ - (void)sl_LockObjDelete(&GlobalLockObj); - - /* Mark the global lock as deleted */ - SL_UNSET_GLOBAL_LOCK_INIT; - - /* signal all waiting sync objects */ - for (i=0; i< MAX_CONCURRENT_ACTIONS; i++) - { - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[i].SyncObj); - } - - /* prepare the event and notify the user app/ext libraries */ - FatalEvent.Id = errorId; - - switch (errorId) - { - case SL_DEVICE_EVENT_FATAL_DEVICE_ABORT: - { - /* set the Abort Type */ - FatalEvent.Data.DeviceAssert.Code = info1; - - /* set the Abort Data */ - FatalEvent.Data.DeviceAssert.Value = info2; - } - break; - - case SL_DEVICE_EVENT_FATAL_NO_CMD_ACK: - { - /* set the command opcode */ - FatalEvent.Data.NoCmdAck.Code = info1; - } - break; - - case SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT: - { - /* set the expected async event opcode */ - FatalEvent.Data.CmdTimeout.Code = info1; - } - break; - - case SL_DEVICE_EVENT_FATAL_SYNC_LOSS: - case SL_DEVICE_EVENT_FATAL_DRIVER_ABORT: - /* No Info to transport */ - break; - - } - -#if defined(slcb_DeviceFatalErrorEvtHdlr) || defined (EXT_LIB_REGISTERED_FATAL_ERROR_EVENTS) - /* call the registered fatal error handlers */ - _SlDrvHandleFatalErrorEvents(&FatalEvent); -#endif -} - -_SlReturnVal_t _SlDrvSyncObjWaitTimeout(_SlSyncObj_t *pSyncObj, _u32 timeoutVal, _u32 asyncEventOpcode) -{ - _SlReturnVal_t ret = sl_SyncObjWait(pSyncObj, timeoutVal); - - /* if timeout occured...*/ - if (ret) - { - _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT, asyncEventOpcode, timeoutVal); - return SL_API_ABORTED; - } - else if (SL_IS_RESTART_REQUIRED) - { - return SL_API_ABORTED; - } - - return SL_RET_CODE_OK; -} - - -static void _SlDrvUpdateApiInProgress(_i8 Value) -{ - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - g_pCB->ApiInProgressCnt += Value; - - SL_DRV_PROTECTION_OBJ_UNLOCK(); -} - -_i8 _SlDrvIsApiInProgress(void) -{ - if (g_pCB != NULL) - { - return (g_pCB->ApiInProgressCnt > 0); - } - - return TRUE; -} - - -#ifdef slcb_GetTimestamp - -void _SlDrvSleep(_u16 DurationInMsec) -{ - _SlTimeoutParams_t TimeoutInfo={0}; - - _SlDrvStartMeasureTimeout(&TimeoutInfo, DurationInMsec); - - while(!_SlDrvIsTimeoutExpired(&TimeoutInfo)); -} -#endif - -#ifndef SL_PLATFORM_MULTI_THREADED -void _SlDrvSetGlobalLockOwner(_u8 Owner) -{ - gGlobalLockContextOwner = Owner; -} -#endif - - -_SlReturnVal_t _SlDrvWaitForInternalAsyncEvent(_u8 ObjIdx , _u32 Timeout, _SlOpcode_t Opcode) -{ - -#if (defined(SL_PLATFORM_EXTERNAL_SPAWN) || !defined(SL_PLATFORM_MULTI_THREADED)) - SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->ObjPool[ObjIdx].SyncObj); - return SL_OS_RET_CODE_OK; -#else - _SlTimeoutParams_t SlTimeoutInfo = { 0 }; - if (_SlDrvIsSpawnOwnGlobalLock()) - { -#if (defined(slcb_GetTimestamp)) - _SlDrvStartMeasureTimeout(&SlTimeoutInfo, Timeout); - while (!Timeout || !_SlDrvIsTimeoutExpired(&SlTimeoutInfo)) -#endif - { - /* If we are in spawn context, this is an API which was called from event handler, - read any async event and check if we got signaled */ - _SlInternalSpawnWaitForEvent(); - /* is it mine? */ - if (0 == sl_SyncObjWait(&g_pCB->ObjPool[ObjIdx].SyncObj, SL_OS_NO_WAIT)) - { - return SL_OS_RET_CODE_OK; - } - } - /* if timeout occured...*/ - _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT, Opcode, Timeout); - return SL_API_ABORTED; - } - else - { - if (Timeout) - { - SL_DRV_SYNC_OBJ_WAIT_TIMEOUT(&g_pCB->ObjPool[ObjIdx].SyncObj, Timeout, Opcode); - } - else - { - SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->ObjPool[ObjIdx].SyncObj); - } - return SL_OS_RET_CODE_OK; - } - -#endif -} - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(SL_MEMORY_MGMT_DYNAMIC)) -_SlAsyncRespBuf_t* _SlGetStatSpawnListItem(_u16 AsyncEventLen) -{ - _u8 Idx = 0; - /* Find free buffer from the pool */ - while (Idx < SL_MAX_ASYNC_BUFFERS) - { - if (0xFF == g_StatMem.AsyncBufPool[Idx].ActionIndex) - { - /* copy buffer */ - return &g_StatMem.AsyncBufPool[Idx]; - } - Idx++; - } - return NULL; -} -#endif - -#if defined(SL_PLATFORM_MULTI_THREADED) -_SlReturnVal_t _SlSpawnMsgListInsert(_u16 AsyncEventLen, _u8 *pAsyncBuf) -{ - _SlReturnVal_t RetVal = SL_OS_RET_CODE_OK; - - /* protect the item insertion */ - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - -#ifdef SL_MEMORY_MGMT_DYNAMIC - _SlSpawnMsgItem_t* pCurr = NULL; - _SlSpawnMsgItem_t* pItem; - - pItem = (_SlSpawnMsgItem_t*)sl_Malloc(sizeof(_SlSpawnMsgItem_t)); - /* now allocate the buffer itself */ - pItem->Buffer = (void*)sl_Malloc(AsyncEventLen); - pItem->next = NULL; - /* if list is empty point to the allocated one */ - if (g_pCB->spawnMsgList == NULL) - { - g_pCB->spawnMsgList = pItem; - } - else - { - pCurr = g_pCB->spawnMsgList; - /* go to end of list */ - while (pCurr->next != NULL) - { - pCurr = pCurr->next; - } - /* we point to last item in list - add the new one */ - pCurr->next = pItem; - } -#else - _SlAsyncRespBuf_t* pItem = (_SlAsyncRespBuf_t*)_SlGetStatSpawnListItem(AsyncEventLen); -#endif - if ((NULL != pItem) && (NULL != pItem->Buffer)) - { - /* save the action idx */ - pItem->ActionIndex = g_pCB->FunctionParams.AsyncExt.ActionIndex; - /* save the corresponding AsyncHndlr (if registered) */ - pItem->AsyncHndlr = g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler; - /* copy the async event that we read to the buffer */ - sl_Memcpy(pItem->Buffer, pAsyncBuf, AsyncEventLen); - } - else - { - RetVal = SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR; - } - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return RetVal; -} - -_SlReturnVal_t _SlSpawnMsgListProcess() -{ - -#ifdef SL_MEMORY_MGMT_DYNAMIC - _SlSpawnMsgItem_t* pHead = g_pCB->spawnMsgList; - _SlSpawnMsgItem_t* pCurr = pHead; - _SlSpawnMsgItem_t* pLast = pHead; - - while (pCurr != NULL) - { - /* lock during action */ - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_NONE); - /* load the async event params */ - g_pCB->FunctionParams.AsyncExt.ActionIndex = pCurr->ActionIndex; - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = pCurr->AsyncHndlr; - - pLast = pCurr; - pCurr = pCurr->next; - - /* move the list head to point to the next item (or null) */ - g_pCB->spawnMsgList = pCurr; - /* Handle async event: here we are in spawn context, after context - * switch from command context. */ - _SlDrvAsyncEventGenericHandler(FALSE, pLast->Buffer); - - /* free the copied buffer inside the item */ - sl_Free(pLast->Buffer); - - /* free the spawn msg item */ - sl_Free(pLast); - - SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); - } - -#else - _u8 i; - - for (i = 0; i < SL_MAX_ASYNC_BUFFERS; i++) - { - if (0xFF != g_StatMem.AsyncBufPool[i].ActionIndex) - { - /* lock during action */ - - SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(GLOBAL_LOCK_FLAGS_NONE); - - /* load the async event params */ - g_pCB->FunctionParams.AsyncExt.ActionIndex = g_StatMem.AsyncBufPool[i].ActionIndex; - g_pCB->FunctionParams.AsyncExt.AsyncEvtHandler = g_StatMem.AsyncBufPool[i].AsyncHndlr; - - /* Handle async event: here we are in spawn context, after context - * switch from command context. */ - _SlDrvAsyncEventGenericHandler(FALSE, (unsigned char *)&(g_StatMem.AsyncBufPool[i].Buffer)); - - SL_DRV_LOCK_GLOBAL_UNLOCK(FALSE); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - g_StatMem.AsyncBufPool[i].ActionIndex = 0xFF; - SL_DRV_PROTECTION_OBJ_UNLOCK(); - } - } -#endif - return SL_OS_RET_CODE_OK; -} - -_u16 _SlSpawnMsgListGetCount() -{ - _u16 NumOfItems = 0; -#ifdef SL_MEMORY_MGMT_DYNAMIC - _SlSpawnMsgItem_t* pCurr = g_pCB->spawnMsgList; - - /* protect the item insertion */ - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - while (pCurr != NULL) - { - NumOfItems++; - - pCurr = pCurr->next; - } - SL_DRV_PROTECTION_OBJ_UNLOCK(); - -#else - _u8 i; - /* protect counting parameters */ - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - for (i = 0; i < SL_MAX_ASYNC_BUFFERS; i++) - { - if (0xFF != g_StatMem.AsyncBufPool[i].ActionIndex) - { - NumOfItems++; - } - } - SL_DRV_PROTECTION_OBJ_UNLOCK(); -#endif - return NumOfItems; -} - - -void _SlFindAndReleasePendingCmd() -{ - /* In case there is no free buffer to store the async event until context switch release the command and return specific error */ - ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->StatusOrLen = SL_RET_CODE_NO_FREE_ASYNC_BUFFERS_ERROR; - /* signal pending cmd */ - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); -} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/driver.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/driver.h deleted file mode 100644 index c94be6394d7..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/driver.h +++ /dev/null @@ -1,508 +0,0 @@ -/* - * driver.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -#ifndef __DRIVER_INT_H__ -#define __DRIVER_INT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -#define TIMEOUT_STATE_EXPIRY (0) -#define TIMEOUT_ONE_MORE_SHOT (1) -#define TIMEOUT_STATE_INIT_VAL (2) - -/* Timeouts for the sync objects */ -#ifndef SL_DRIVER_TIMEOUT_SHORT -#define SL_DRIVER_TIMEOUT_SHORT (10000) /* msec units */ -#endif -#ifndef SL_DRIVER_TIMEOUT_LONG -#define SL_DRIVER_TIMEOUT_LONG (65535) /* msec units */ -#endif - -#define INIT_COMPLETE_TIMEOUT SL_DRIVER_TIMEOUT_LONG -#define STOP_DEVICE_TIMEOUT SL_DRIVER_TIMEOUT_LONG - -#ifndef SYNC_PATTERN_TIMEOUT_IN_MSEC -#define SYNC_PATTERN_TIMEOUT_IN_MSEC (50) /* the sync patttern timeout in milliseconds units */ -#endif - -#define GLOBAL_LOCK_FLAGS_NONE (0x0) -#define GLOBAL_LOCK_FLAGS_UPDATE_API_IN_PROGRESS (0x1) /* Bit 0 */ -#define GLOBAL_LOCK_FLAGS_PROVISIONING_STOP_API (0x2) /* Bit 1*/ -#define GLOBAL_LOCK_FLAGS_STARTING_DEVICE (0x4) /* Bit 2 */ -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#ifndef CPU_FREQ_IN_MHZ - #define CPU_FREQ_IN_MHZ (200) -#endif -#define USEC_DELAY (50) - -#define SL_DRV_PROTECTION_OBJ_UNLOCK() LOCK_OK_CHECK(_SlDrvProtectionObjUnLock()); -#define SL_DRV_PROTECTION_OBJ_LOCK_FOREVER() LOCK_OK_CHECK(_SlDrvProtectionObjLockWaitForever()); -#define SL_DRV_OBJ_UNLOCK(pObj) LOCK_OK_CHECK(_SlDrvObjUnLock(pObj)); -#define SL_DRV_OBJ_LOCK_FOREVER(pObj) LOCK_OK_CHECK(_SlDrvObjLockWaitForever(pObj)); -#define SL_DRV_SYNC_OBJ_SIGNAL(pObj) _SlDrvSyncObjSignal(pObj); -#define SL_DRV_SYNC_OBJ_CLEAR(pObj) sl_SyncObjWait(pObj,SL_OS_NO_WAIT); - -#define SL_DRV_SYNC_OBJ_WAIT_FOREVER(SyncObj) { \ -if (SL_API_ABORTED == _SlDrvSyncObjWaitForever(SyncObj)) \ -{ \ - return SL_API_ABORTED; \ -} \ -} -#define SL_DRV_SYNC_OBJ_WAIT_TIMEOUT(SyncObj, timeoutVal, opcode) { \ -if (SL_API_ABORTED == _SlDrvSyncObjWaitTimeout(SyncObj, timeoutVal, opcode)) \ -{ \ - _SlDrvReleasePoolObj(g_pCB->FunctionParams.AsyncExt.ActionIndex); \ - return SL_API_ABORTED; \ -} \ -} -#define SL_DRV_LOCK_GLOBAL_LOCK_FOREVER(Flags) { \ -_SlReturnVal_t retVal; \ - \ -retVal = _SlDrvObjGlobalLockWaitForever(Flags); \ -if (retVal) \ -{ \ - return retVal; \ -} \ -} - -#define SL_DRV_LOCK_GLOBAL_UNLOCK(bDecrementApiInProgress) { \ -_SlReturnVal_t retVal; \ - \ -retVal = _SlDrvGlobalObjUnLock(bDecrementApiInProgress); \ -if (retVal) \ -{ \ - return retVal; \ -} \ -} - - -#define SL_IS_RESTART_REQUIRED (g_SlDeviceStatus & _SL_DRV_STATUS_BIT_RESTART_REQUIRED) /* bit 8 indicates restart is required due to fatal error */ -#define SL_IS_DEVICE_STARTED (g_SlDeviceStatus & _SL_DRV_STATUS_BIT_DEVICE_STARTED) /* bit 9 indicates device is started */ -#define SL_IS_DEVICE_LOCKED (g_SlDeviceStatus & _SL_DEV_STATUS_BIT_LOCKED) /* bits 0-7 devStatus from NWP, bit 2 = device locked */ -#define SL_IS_PROVISIONING_ACTIVE (!!(g_SlDeviceStatus & _SL_DEV_STATUS_BIT_PROVISIONING_ACTIVE)) /* bits 0-7 devStatus from NWP, bit 3 = provisioning active */ -#define SL_IS_PROVISIONING_INITIATED_BY_USER (!!(g_SlDeviceStatus & _SL_DEV_STATUS_BIT_PROVISIONING_USER_INITIATED)) /* bits 0-7 devStatus from NWP, bit 4 = provisioning initiated by the user */ -#define SL_IS_PROVISIONING_API_ALLOWED (!!(g_SlDeviceStatus & _SL_DEV_STATUS_BIT_PROVISIONING_ENABLE_API)) -#define SL_IS_DEVICE_STOP_IN_PROGRESS (!!(g_SlDeviceStatus & _SL_DRV_STATUS_BIT_STOP_IN_PROGRESS)) -#define SL_IS_DEVICE_START_IN_PROGRESS (!!(g_SlDeviceStatus & _SL_DRV_STATUS_BIT_START_IN_PROGRESS)) - -#define SL_IS_PROVISIONING_IN_PROGRESS (!!(g_SlDeviceStatus & ( _SL_DEV_STATUS_BIT_PROVISIONING_USER_INITIATED | _SL_DEV_STATUS_BIT_PROVISIONING_ACTIVE))) -/* Check the following conditions: - 1. Device started - 2. Restart device is not required - 3. Provisioning is active - 4. Provisioning was already initiated by the user - 5. Device is not locked -*/ -#define SL_IS_COMMAND_ALLOWED ((g_SlDeviceStatus & (_SL_DRV_STATUS_BIT_DEVICE_STARTED | \ - _SL_DRV_STATUS_BIT_RESTART_REQUIRED | \ - _SL_DEV_STATUS_BIT_PROVISIONING_ACTIVE | \ - _SL_DEV_STATUS_BIT_PROVISIONING_USER_INITIATED | \ - _SL_DRV_STATUS_BIT_STOP_IN_PROGRESS | \ - _SL_DEV_STATUS_BIT_LOCKED)) == 0x200) - -#define SL_IS_GLOBAL_LOCK_INIT (g_SlDeviceStatus & _SL_DRV_STATUS_BIT_GLOBAL_LOCK_INIT) -#define SL_SET_GLOBAL_LOCK_INIT (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_GLOBAL_LOCK_INIT) -#define SL_UNSET_GLOBAL_LOCK_INIT (g_SlDeviceStatus &= (~ _SL_DRV_STATUS_BIT_GLOBAL_LOCK_INIT)) - -#define SL_SET_RESTART_REQUIRED (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_RESTART_REQUIRED) /* bit 8 indicates restart is required due to fatal error */ -#define SL_UNSET_RESTART_REQUIRED (g_SlDeviceStatus &= (~_SL_DRV_STATUS_BIT_RESTART_REQUIRED)) /* bit 8 indicates restart is required due to fatal error */ -#define SL_SET_DEVICE_STARTED (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_DEVICE_STARTED) /* bit 9 indicates device is started */ -#define SL_UNSET_DEVICE_STARTED (g_SlDeviceStatus &= (~_SL_DRV_STATUS_BIT_DEVICE_STARTED)) /* bit 9 indicates device is started */ - -#define SL_SET_DEVICE_STOP_IN_PROGRESS (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_STOP_IN_PROGRESS) /* bit 10 indicates there is stop in progress */ -#define SL_UNSET_DEVICE_STOP_IN_PROGRESS (g_SlDeviceStatus &= (~_SL_DRV_STATUS_BIT_STOP_IN_PROGRESS)) /* bit 10 indicates there is stop in progress */ - -/* Start in progress */ -#define SL_SET_DEVICE_START_IN_PROGRESS (g_SlDeviceStatus |= _SL_DRV_STATUS_BIT_START_IN_PROGRESS) /* bit 11 indicates there is start in progress */ -#define SL_UNSET_DEVICE_START_IN_PROGRESS (g_SlDeviceStatus &= (~_SL_DRV_STATUS_BIT_START_IN_PROGRESS)) /* bit 11 indicates there is start in progress */ - -#define SL_SET_DEVICE_STATUS(x) (g_SlDeviceStatus = ((g_SlDeviceStatus & 0xFF00) | (_u16)x) ) /* bits 0-7 devStatus from NWP */ - -#define _SL_PENDING_RX_MSG(pDriverCB) (RxIrqCnt != (pDriverCB)->RxDoneCnt) - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -typedef struct _SlSpawnMsgItem_s -{ - _SlSpawnEntryFunc_t AsyncHndlr; - _u8 ActionIndex; - void *Buffer; - struct _SlSpawnMsgItem_s *next; -} _SlSpawnMsgItem_t; - - -typedef struct -{ - _u32 TSPrev; - _u32 TSCurr; - _u32 DeltaTicks; - _u32 DeltaTicksReminder; - _i32 Total10MSecUnits; -} _SlTimeoutParams_t; - -typedef struct -{ - _u8 *pAsyncMsgBuff; - _u8 bInCmdContext; -} DeviceEventInfo_t; - -typedef struct -{ - _SlOpcode_t Opcode; - _SlArgSize_t TxDescLen; - _SlArgSize_t RxDescLen; -}_SlCmdCtrl_t; - -typedef struct -{ - _u16 TxPayload1Len; - _u16 TxPayload2Len; - _i16 RxPayloadLen; - _i16 ActualRxPayloadLen; - _u8 *pTxPayload1; - _u8 *pTxPayload2; - _u8 *pRxPayload; -}_SlCmdExt_t; - -typedef struct _SlArgsData_t -{ - _u8 *pArgs; - _u8 *pData; -} _SlArgsData_t; - -typedef struct _SlPoolObj_t -{ - _SlSyncObj_t SyncObj; - _u8 *pRespArgs; - _u8 ActionID; - _u8 AdditionalData; /* use for socketID and one bit which indicate supprt IPV6 or not (1=support, 0 otherwise) */ - _u8 NextIndex; -} _SlPoolObj_t; - -typedef enum -{ - SOCKET_0, - SOCKET_1, - SOCKET_2, - SOCKET_3, - SOCKET_4, - SOCKET_5, - SOCKET_6, - SOCKET_7, - SOCKET_8, - SOCKET_9, - SOCKET_10, - SOCKET_11, - SOCKET_12, - SOCKET_13, - SOCKET_14, - SOCKET_15, - MAX_SOCKET_ENUM_IDX, - ACCEPT_ID = MAX_SOCKET_ENUM_IDX, - CONNECT_ID, - SELECT_ID, - GETHOSYBYNAME_ID, - GETHOSYBYSERVICE_ID, - PING_ID, - NETAPP_RECEIVE_ID, - START_STOP_ID, - NETUTIL_CMD_ID, - CLOSE_ID, - START_TLS_ID, - /**********/ - RECV_ID /* Please note!! this member must be the last in this action enum */ -}_SlActionID_e; - -typedef struct _SlActionLookup_t -{ - _u8 ActionID; - _u16 ActionAsyncOpcode; - _SlSpawnEntryFunc_t AsyncEventHandler; - -} _SlActionLookup_t; - -typedef struct -{ - _u8 TxPoolCnt; - _u16 MinTxPayloadSize; - _SlLockObj_t TxLockObj; - _SlSyncObj_t TxSyncObj; -}_SlFlowContCB_t; - -typedef enum -{ - RECV_RESP_CLASS, - CMD_RESP_CLASS, - ASYNC_EVT_CLASS, -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - MULTI_SELECT_RESP_CLASS, -#endif - DUMMY_MSG_CLASS -}_SlRxMsgClass_e; - -typedef struct -{ - _u8 ActionIndex; - _SlSpawnEntryFunc_t AsyncEvtHandler; /* place to write pointer to AsyncEvent handler (calc-ed by Opcode) */ - _SlRxMsgClass_e RxMsgClass; /* type of Rx message */ -} AsyncExt_t; - -typedef _u8 _SlSd_t; - -typedef struct -{ - _SlCmdCtrl_t *pCmdCtrl; - _u8 *pTxRxDescBuff; - _SlCmdExt_t *pCmdExt; - AsyncExt_t AsyncExt; -}_SlFunctionParams_t; - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - -typedef struct SlSelectEntry_t -{ - SlSelectAsyncResponse_t Response; - _u32 TimeStamp; - _u16 readlist; - _u16 writelist; - _u8 ObjIdx; -}_SlSelectEntry_t; - -typedef struct _SlMultiSelectCB_t -{ - _u16 readsds; - _u16 writesds; - _u16 CtrlSockFD; - _u8 ActiveSelect; - _u8 ActiveWaiters; - _BasicResponse_t SelectCmdResp; - _SlSyncObj_t SelectSyncObj; - _SlLockObj_t SelectLockObj; - _SlSelectEntry_t* SelectEntry[MAX_CONCURRENT_ACTIONS]; -}_SlMultiSelectCB_t; - -#else - -typedef enum -{ - SOCK_TRIGGER_READY, - SOCK_TRIGGER_WAITING_FOR_RESP, - SOCK_TRIGGER_RESP_RECEIVED -} _SlSockTriggerState_e; - -typedef struct -{ - _SlSockTriggerState_e State; - _u8 ObjPoolIdx; -} _SlSockTriggerData_t; - -typedef struct -{ - _SlSockTriggerData_t Info; - SlSelectAsyncResponse_t Resp; -} _SlSockTriggerSelect_t; - -#endif - -typedef struct -{ - _SlFd_t FD; - _SlCommandHeader_t TempProtocolHeader; - P_INIT_CALLBACK pInitCallback; - - _SlPoolObj_t ObjPool[MAX_CONCURRENT_ACTIONS]; - _u8 FreePoolIdx; - _u8 PendingPoolIdx; - _u8 ActivePoolIdx; - _u32 ActiveActionsBitmap; - _SlLockObj_t ProtectionLockObj; - - _SlSyncObj_t CmdSyncObj; - _u8 WaitForCmdResp; - _SlFlowContCB_t FlowContCB; - _u8 TxSeqNum; - _u8 RxDoneCnt; - _u16 SocketNonBlocking; - _u16 SocketTXFailure; - /* for stack reduction the parameters are globals */ - _SlFunctionParams_t FunctionParams; - - _u8 ActionIndex; - _i8 ApiInProgressCnt; /* Counts how many APIs are in progress */ - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - /* Multiple Select Control block */ - _SlMultiSelectCB_t MultiSelectCB; -#endif - -#if defined(slcb_SocketTriggerEventHandler) - /* Trigger mode control block */ - _SlSockTriggerSelect_t SocketTriggerSelect; -#endif - -#ifdef SL_MEMORY_MGMT_DYNAMIC - _SlSpawnMsgItem_t *spawnMsgList; -#endif - _u8 NumOfDeletedSyncObj; -}_SlDriverCb_t; - -typedef struct -{ - _SlSpawnEntryFunc_t AsyncHndlr; - _u8 ActionIndex; - _u8 Buffer[SL_ASYNC_MAX_MSG_LEN]; -}_SlAsyncRespBuf_t; - -extern _volatile _u8 RxIrqCnt; - -extern _SlLockObj_t GlobalLockObj; -extern _u16 g_SlDeviceStatus; - -extern _SlDriverCb_t* g_pCB; -extern P_SL_DEV_PING_CALLBACK pPingCallBackFunc; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ -extern _SlReturnVal_t _SlDrvDriverCBInit(void); -extern _SlReturnVal_t _SlDrvDriverCBDeinit(void); -extern _SlReturnVal_t _SlDrvRxIrqHandler(void *pValue); -extern _SlReturnVal_t _SlDrvCmdOp(_SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); -extern _SlReturnVal_t _SlDrvCmdSend_noLock(_SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); -extern _SlReturnVal_t _SlDrvCmdSend_noWait(_SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); -extern _SlReturnVal_t _SlDrvCmdSend(_SlCmdCtrl_t *pCmdCtrl , void *pTxRxDescBuff , _SlCmdExt_t *pCmdExt); -extern _SlReturnVal_t _SlDrvDataReadOp(_SlSd_t Sd, _SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); -extern _SlReturnVal_t _SlDrvDataWriteOp(_SlSd_t Sd, _SlCmdCtrl_t *pCmdCtrl , void* pTxRxDescBuff , _SlCmdExt_t* pCmdExt); -extern _SlReturnVal_t _SlDeviceHandleAsync_InitComplete(void *pVoidBuf); -extern _SlReturnVal_t _SlSocketHandleAsync_Connect(void *pVoidBuf); -extern _SlReturnVal_t _SlSocketHandleAsync_Close(void *pVoidBuf); -extern _SlReturnVal_t _SlDrvGlobalObjUnLock(_u8 bDecrementApiInProgress); -extern _SlReturnVal_t _SlDrvObjGlobalLockWaitForever(_u32 Flags); -extern _SlReturnVal_t _SlDrvDriverIsApiAllowed(_u16 Silo); -extern _SlReturnVal_t _SlDrvMsgReadSpawnCtx(void *pValue); -extern void _SlInternalSpawnWaitForEvent(void); -extern void _SlDrvSetGlobalLockOwner(_u8 Owner); -#if (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) -extern _u8 _SlDrvIsSpawnOwnGlobalLock(); -#endif -extern _SlReturnVal_t _SlDrvBasicCmd(_SlOpcode_t Opcode); -extern _SlReturnVal_t _SlSocketHandleAsync_Accept(void *pVoidBuf); -extern _SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByService(void *pVoidBuf); -extern _SlReturnVal_t _SlSocketHandleAsync_Select(void *pVoidBuf); -extern _SlReturnVal_t _SlSocketHandleAsync_StartTLS(void *pVoidBuf); -extern _SlReturnVal_t _SlDrvReleaseAllActivePendingPoolObj(); - -#ifdef slcb_GetTimestamp -extern void _SlDrvStartMeasureTimeout(_SlTimeoutParams_t *pTimeoutInfo, _u32 TimeoutInMsec); -extern _u8 _SlDrvIsTimeoutExpired(_SlTimeoutParams_t *pTimeoutInfo); -extern void _SlDrvSleep(_u16 DurationInMsec); -#endif - -#if defined(SL_PLATFORM_MULTI_THREADED) -extern void * pthread_self(void); -#endif - -extern _SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByName(void *pVoidBuf); -extern _SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByAddr(void *pVoidBuf); -extern _SlReturnVal_t _SlNetAppHandleAsync_PingResponse(void *pVoidBuf); -extern _SlReturnVal_t _SlNetAppEventHandler(void* pArgs); - -#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) -extern void _SlDrvDispatchHttpServerEvents(SlNetAppHttpServerEvent_t *slHttpServerEvent, SlNetAppHttpServerResponse_t *slHttpServerResponse); -#endif - -#if defined(slcb_NetAppRequestHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) -extern void _SlDrvDispatchNetAppRequestEvents(SlNetAppRequest_t *slNetAppRequestEvent, SlNetAppResponse_t *slNetAppResponse); -#endif - -extern void _SlDeviceHandleAsync_Stop(void *pVoidBuf); -extern void _SlNetUtilHandleAsync_Cmd(void *pVoidBuf); -extern _SlReturnVal_t _SlDrvWaitForPoolObj(_u8 ActionID, _u8 SocketID); -extern _SlReturnVal_t _SlDrvReleasePoolObj(_u8 pObj); -extern void _SlDrvReleaseAllPendingPoolObj(); -extern _SlReturnVal_t _SlDrvAlignSize(_u16 msgLen); -extern _SlReturnVal_t _SlDrvProtectAsyncRespSetting(_u8 *pAsyncRsp, _SlActionID_e ActionID, _u8 SocketID); -extern void _SlNetAppHandleAsync_NetAppReceive(void *pVoidBuf); - - -extern _SlReturnVal_t _SlDeviceEventHandler(void* pEventInfo); -extern _SlReturnVal_t _SlDrvSyncObjWaitForever(_SlSyncObj_t *pSyncObj); -extern _SlReturnVal_t _SlDrvObjLockWaitForever(_SlLockObj_t *pLockObj); -extern _SlReturnVal_t _SlDrvSyncObjWaitTimeout(_SlSyncObj_t *pSyncObj, - _u32 timeoutVal, - _u32 asyncEventOpcode); - -extern _SlReturnVal_t _SlDrvSyncObjSignal(_SlSyncObj_t *pSyncObj); -extern _SlReturnVal_t _SlDrvObjLock(_SlLockObj_t *pLockObj, _SlTime_t Timeout); -extern _SlReturnVal_t _SlDrvProtectionObjLockWaitForever(void); -extern _SlReturnVal_t _SlDrvObjUnLock(_SlLockObj_t *pLockObj); -extern _SlReturnVal_t _SlDrvProtectionObjUnLock(void); - -extern void _SlDrvMemZero(void* Addr, _u16 size); -extern void _SlDrvResetCmdExt(_SlCmdExt_t* pCmdExt); - -extern _i8 _SlDrvIsApiInProgress(void); -extern void _SlDrvHandleResetRequest(const void* pIfHdl, _i8* pDevName); -extern _SlReturnVal_t _SlDrvWaitForInternalAsyncEvent(_u8 ObjIdx, _u32 Timeout, _SlOpcode_t Opcode); -extern _SlReturnVal_t _SlSpawnMsgListInsert(_u16 AsyncEventLen, _u8 *pAsyncBuf); -extern _SlReturnVal_t _SlSpawnMsgListProcess(void); -extern _u16 _SlSpawnMsgListGetCount(void); -extern void _SlDrvHandleFatalError(_u32 errorId, _u32 info1, _u32 info2); -extern void _SlDrvHandleAssert(void); -extern void _SlFindAndReleasePendingCmd(); - -#define _SL_PROTOCOL_ALIGN_SIZE(msgLen) (((msgLen)+3) & (~3)) -#define _SL_IS_PROTOCOL_ALIGNED_SIZE(msgLen) (!((msgLen) & 3)) - - -#define _SL_PROTOCOL_CALC_LEN(pCmdCtrl,pCmdExt) ((pCmdExt) ? \ - (_SL_PROTOCOL_ALIGN_SIZE(pCmdCtrl->TxDescLen) + _SL_PROTOCOL_ALIGN_SIZE(pCmdExt->TxPayload1Len + pCmdExt->TxPayload2Len)) : \ - (_SL_PROTOCOL_ALIGN_SIZE(pCmdCtrl->TxDescLen))) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __DRIVER_INT_H__ */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/flowcont.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/flowcont.c deleted file mode 100644 index 5bdf01552af..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/flowcont.c +++ /dev/null @@ -1,61 +0,0 @@ -/* - * flowcont.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include -#include - - -/*****************************************************************************/ -/* _SlDrvFlowContInit */ -/*****************************************************************************/ -void _SlFlowContSet(void *pVoidBuf) -{ - SlDeviceFlowCtrlAsyncEvent_t *pFlowCtrlAsyncEvent = (SlDeviceFlowCtrlAsyncEvent_t *)_SL_RESP_ARGS_START(pVoidBuf); - - if (pFlowCtrlAsyncEvent->MinTxPayloadSize != 0) - { - g_pCB->FlowContCB.MinTxPayloadSize = pFlowCtrlAsyncEvent->MinTxPayloadSize; - } - -} - - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/flowcont.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/flowcont.h deleted file mode 100644 index 24670a6d4f5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/flowcont.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * flowcont.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -#ifndef __FLOWCONT_H__ -#define __FLOWCONT_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -#define FLOW_CONT_MIN 2 - -extern void _SlFlowContSet(void *pVoidBuf); - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __FLOWCONT_H__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/fs.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/fs.c deleted file mode 100644 index af1e41af6ba..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/fs.c +++ /dev/null @@ -1,824 +0,0 @@ -/* - * fs.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -#define sl_min(a,b) (((a) < (b)) ? (a) : (b)) -#define MAX_NVMEM_CHUNK_SIZE 1456 /*should be 16 bytes align, because of encryption data*/ - -/*****************************************************************************/ -/* Internal functions */ -/*****************************************************************************/ - -static _u16 _SlFsStrlen(const _u8 *buffer); - -static _u32 FsGetCreateFsMode(_u8 Mode, _u32 MaxSizeInBytes,_u32 AccessFlags); - -/*****************************************************************************/ -/* _SlFsStrlen */ -/*****************************************************************************/ -static _u16 _SlFsStrlen(const _u8 *buffer) -{ - _u16 len = 0; - if( buffer != NULL ) - { - while(*buffer++) len++; - } - return len; -} -/*****************************************************************************/ -/* _SlFsGetCreateFsMode */ -/*****************************************************************************/ - -/* Convert the user flag to the file System flag */ -#define FS_CONVERT_FLAGS( ModeAndMaxSize ) (((_u32)ModeAndMaxSize & SL_FS_OPEN_FLAGS_BIT_MASK)>>SL_NUM_OF_MAXSIZE_BIT) - -typedef enum -{ - FS_MODE_OPEN_READ = 0, - FS_MODE_OPEN_WRITE, - FS_MODE_OPEN_CREATE, - FS_MODE_OPEN_WRITE_CREATE_IF_NOT_EXIST -}FsFileOpenAccessType_e; - -#define FS_MODE_ACCESS_RESERVED_OFFSET (27) -#define FS_MODE_ACCESS_RESERVED_MASK (0x1F) -#define FS_MODE_ACCESS_FLAGS_OFFSET (16) -#define FS_MODE_ACCESS_FLAGS_MASK (0x7FF) -#define FS_MODE_ACCESS_OFFSET (12) -#define FS_MODE_ACCESS_MASK (0xF) -#define FS_MODE_OPEN_SIZE_GRAN_OFFSET (8) -#define FS_MODE_OPEN_SIZE_GRAN_MASK (0xF) -#define FS_MODE_OPEN_SIZE_OFFSET (0) -#define FS_MODE_OPEN_SIZE_MASK (0xFF) -#define FS_MAX_MODE_SIZE (0xFF) - -/* SizeGran is up to 4 bit , Size can be up to 8 bit */ -#define FS_MODE(Access, SizeGran, Size,Flags) (_u32)(((_u32)((Access) &FS_MODE_ACCESS_MASK)<= MaxSizeInBytes ) - break; - } - granNum = MaxSizeInBytes/granTable[granIdx]; - if( MaxSizeInBytes % granTable[granIdx] != 0 ) - granNum++; - - return (_u32)FS_MODE( Mode, granIdx, granNum, AccessFlags ); - -} - -/*****************************************************************************/ -/* API functions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* sl_FsOpen */ -/*****************************************************************************/ -typedef union -{ - SlFsOpenCommand_t Cmd; - SlFsOpenResponse_t Rsp; -}_SlFsOpenMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsOpen) - -static const _SlCmdCtrl_t _SlFsOpenCmdCtrl = -{ - SL_OPCODE_NVMEM_FILEOPEN, - (_SlArgSize_t)sizeof(SlFsOpenCommand_t), - (_SlArgSize_t)sizeof(SlFsOpenResponse_t) -}; - -_i32 sl_FsOpen(const _u8 *pFileName,const _u32 ModeAndMaxSize, _u32 *pToken) -{ - - _SlFsOpenMsg_u Msg; - _SlCmdExt_t CmdExt; - _i32 FileHandle; - _u32 MaxSizeInBytes; - _u32 OpenMode; - _u8 CreateMode; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) - { - return SL_ERROR_FS_WRONG_FILE_NAME; - } - - CmdExt.TxPayload1Len = (_u16)((_SlFsStrlen(pFileName)+4) & (~3)); /* add 4: 1 for NULL and the 3 for align */ - CmdExt.pTxPayload1 = (_u8*)pFileName; - - OpenMode = ModeAndMaxSize & SL_FS_OPEN_MODE_BIT_MASK; - - /*convert from the interface flags to the device flags*/ - if( OpenMode == SL_FS_READ ) - { - Msg.Cmd.Mode = FS_MODE(FS_MODE_OPEN_READ, 0, 0, 0); - } - else if (( OpenMode == SL_FS_WRITE ) ||( OpenMode == SL_FS_OVERWRITE)) - { - Msg.Cmd.Mode = FS_MODE(FS_MODE_OPEN_WRITE, 0, 0, FS_CONVERT_FLAGS ( ModeAndMaxSize)); - } - /* one of the creation mode */ - else if ( ( OpenMode == (SL_FS_CREATE | SL_FS_OVERWRITE )) || ( OpenMode == SL_FS_CREATE) ||(OpenMode == (SL_FS_CREATE | SL_FS_WRITE ))) - { - /* test that the size is correct */ - MaxSizeInBytes = (ModeAndMaxSize & SL_FS_OPEN_MAXSIZE_BIT_MASK) * 256; - if (MaxSizeInBytes > 0xFF0000 ) - { - return SL_ERROR_FS_FILE_MAX_SIZE_EXCEEDED; - } - - CreateMode = ((OpenMode == (SL_FS_CREATE | SL_FS_OVERWRITE )) ? FS_MODE_OPEN_WRITE_CREATE_IF_NOT_EXIST : FS_MODE_OPEN_CREATE ); - - Msg.Cmd.Mode = FsGetCreateFsMode( CreateMode ,MaxSizeInBytes, FS_CONVERT_FLAGS ( ModeAndMaxSize) ); - } - else - { - return SL_ERROR_FS_INVALID_FILE_MODE; - } - - if(pToken != NULL) - { - Msg.Cmd.Token = *pToken; - } - else - { - Msg.Cmd.Token = 0; - } - - _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsOpenCmdCtrl, &Msg, &CmdExt); - FileHandle = (_i32)Msg.Rsp.FileHandle; - if (pToken != NULL) - { - *pToken = Msg.Rsp.Token; - } - - /* in case of an error, return the erros file handler as an error code */ - return FileHandle; -} -#endif - -/*****************************************************************************/ -/* sl_FsClose */ -/*****************************************************************************/ -typedef union -{ - SlFsCloseCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlFsCloseMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsClose) - -static const _SlCmdCtrl_t _SlFsCloseCmdCtrl = -{ - SL_OPCODE_NVMEM_FILECLOSE, - (_SlArgSize_t)sizeof(SlFsCloseCommand_t), - (_SlArgSize_t)sizeof(SlFsCloseResponse_t) -}; - -_i16 sl_FsClose(const _i32 FileHdl, const _u8* pCeritificateFileName,const _u8* pSignature ,const _u32 SignatureLen) -{ - _SlFsCloseMsg_u Msg; - _SlCmdExt_t ExtCtrl; - - _SlDrvMemZero(&Msg, (_u16)sizeof(SlFsCloseCommand_t)); - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - Msg.Cmd.FileHandle = (_u32)FileHdl; - if( pCeritificateFileName != NULL ) - { - Msg.Cmd.CertificFileNameLength = (_u32)((_SlFsStrlen(pCeritificateFileName)+4) & (~3)); /* add 4: 1 for NULL and the 3 for align */ - } - Msg.Cmd.SignatureLen = SignatureLen; - - _SlDrvMemZero(&ExtCtrl, (_u16)sizeof(_SlCmdExt_t)); - - ExtCtrl.TxPayload1Len = (_u16)(((SignatureLen+3) & (~3))); /* align */ - ExtCtrl.pTxPayload1 = (_u8*)pSignature; - ExtCtrl.RxPayloadLen = (_i16)Msg.Cmd.CertificFileNameLength; - ExtCtrl.pRxPayload = (_u8*)pCeritificateFileName; /* Add signature */ - - if(ExtCtrl.pRxPayload != NULL && ExtCtrl.RxPayloadLen != 0) - { - ExtCtrl.RxPayloadLen = ExtCtrl.RxPayloadLen * (-1); - } - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsCloseCmdCtrl, &Msg, &ExtCtrl)); - - return (_i16)((_i16)Msg.Rsp.status); -} -#endif - - -/*****************************************************************************/ -/* sl_FsRead */ -/*****************************************************************************/ -typedef union -{ - SlFsReadCommand_t Cmd; - SlFsReadResponse_t Rsp; -}_SlFsReadMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsRead) - -static const _SlCmdCtrl_t _SlFsReadCmdCtrl = -{ - SL_OPCODE_NVMEM_FILEREADCOMMAND, - (_SlArgSize_t)sizeof(SlFsReadCommand_t), - (_SlArgSize_t)sizeof(SlFsReadResponse_t) -}; - -_i32 sl_FsRead(const _i32 FileHdl,_u32 Offset, _u8* pData,_u32 Len) -{ - _SlFsReadMsg_u Msg; - _SlCmdExt_t ExtCtrl; - _u16 ChunkLen; - _SlReturnVal_t RetVal =0; - _i32 RetCount = 0; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - _SlDrvMemZero(&ExtCtrl, (_u16)sizeof(_SlCmdExt_t)); - - ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len); - ExtCtrl.RxPayloadLen = (_i16)ChunkLen; - ExtCtrl.pRxPayload = (_u8 *)(pData); - Msg.Cmd.Offset = Offset; - Msg.Cmd.Len = ChunkLen; - Msg.Cmd.FileHandle = (_u32)FileHdl; - do - { - RetVal = _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsReadCmdCtrl, &Msg, &ExtCtrl); - if(SL_OS_RET_CODE_OK == RetVal) - { - if( Msg.Rsp.status < 0) - { - if( RetCount > 0) - { - return RetCount; - } - else - { - return Msg.Rsp.status; - } - } - RetCount += (_i32)Msg.Rsp.status; - Len -= ChunkLen; - Offset += ChunkLen; - Msg.Cmd.Offset = Offset; - ExtCtrl.pRxPayload += ChunkLen; - ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len); - ExtCtrl.RxPayloadLen = (_i16)ChunkLen; - Msg.Cmd.Len = ChunkLen; - Msg.Cmd.FileHandle = (_u32)FileHdl; - } - else - { - return RetVal; - } - }while(ChunkLen > 0); - - return (_i32)RetCount; -} -#endif - -/*****************************************************************************/ -/* sl_FsWrite */ -/*****************************************************************************/ -typedef union -{ - SlFsWriteCommand_t Cmd; - SlFsWriteResponse_t Rsp; -}_SlFsWriteMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsWrite) - -static const _SlCmdCtrl_t _SlFsWriteCmdCtrl = -{ - SL_OPCODE_NVMEM_FILEWRITECOMMAND, - (_SlArgSize_t)sizeof(SlFsWriteCommand_t), - (_SlArgSize_t)sizeof(SlFsWriteResponse_t) -}; - -_i32 sl_FsWrite(const _i32 FileHdl,_u32 Offset, _u8* pData,_u32 Len) -{ - _SlFsWriteMsg_u Msg; - _SlCmdExt_t ExtCtrl; - _u16 ChunkLen; - _SlReturnVal_t RetVal; - _i32 RetCount = 0; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - _SlDrvMemZero(&ExtCtrl, (_u16)sizeof(_SlCmdExt_t)); - - ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len); - ExtCtrl.TxPayload1Len = ChunkLen; - ExtCtrl.pTxPayload1 = (_u8 *)(pData); - Msg.Cmd.Offset = Offset; - Msg.Cmd.Len = ChunkLen; - Msg.Cmd.FileHandle = (_u32)FileHdl; - - do - { - RetVal = _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsWriteCmdCtrl, &Msg, &ExtCtrl); - if(SL_OS_RET_CODE_OK == RetVal) - { - if( Msg.Rsp.status < 0) - { - if( RetCount > 0) - { - return RetCount; - } - else - { - return Msg.Rsp.status; - } - } - - RetCount += (_i32)Msg.Rsp.status; - Len -= ChunkLen; - Offset += ChunkLen; - Msg.Cmd.Offset = Offset; - ExtCtrl.pTxPayload1 += ChunkLen; - ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE,Len); - ExtCtrl.TxPayload1Len = ChunkLen; - Msg.Cmd.Len = ChunkLen; - Msg.Cmd.FileHandle = (_u32)FileHdl; - } - else - { - return RetVal; - } - }while(ChunkLen > 0); - - return (_i32)RetCount; -} -#endif - -/*****************************************************************************/ -/* sl_FsGetInfo */ -/*****************************************************************************/ -typedef union -{ - SlFsGetInfoCommand_t Cmd; - SlFsGetInfoResponse_t Rsp; -}_SlFsGetInfoMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsGetInfo) - -static const _SlCmdCtrl_t _SlFsGetInfoCmdCtrl = -{ - SL_OPCODE_NVMEM_FILEGETINFOCOMMAND, - (_SlArgSize_t)sizeof(SlFsGetInfoCommand_t), - (_SlArgSize_t)sizeof(SlFsGetInfoResponse_t) -}; - -const _u16 FlagsTranslate[] = -{ - SL_FS_INFO_OPEN_WRITE, - SL_FS_INFO_OPEN_READ, - SL_FS_INFO_NOT_FAILSAFE, - SL_FS_INFO_NOT_VALID, - SL_FS_INFO_SYS_FILE, - SL_FS_INFO_MUST_COMMIT, - SL_FS_INFO_BUNDLE_FILE, - SL_FS_INFO_PENDING_COMMIT, - SL_FS_INFO_PENDING_BUNDLE_COMMIT, - 0, - SL_FS_INFO_SECURE, - SL_FS_INFO_NOSIGNATURE, - SL_FS_INFO_PUBLIC_WRITE, - SL_FS_INFO_PUBLIC_READ, - 0, - 0 -}; - -_i16 sl_FsGetInfo(const _u8 *pFileName,const _u32 Token,SlFsFileInfo_t* pFsFileInfo) -{ - _SlFsGetInfoMsg_u Msg; - _SlCmdExt_t CmdExt; - _u16 BitNum; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) - { - return SL_ERROR_FS_WRONG_FILE_NAME; - } - - CmdExt.TxPayload1Len = (_u16)((_SlFsStrlen(pFileName)+4) & (~3)); /* add 4: 1 for NULL and the 3 for align */ - CmdExt.pTxPayload1 = (_u8*)pFileName; - - Msg.Cmd.Token = Token; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsGetInfoCmdCtrl, &Msg, &CmdExt)); - - /* convert flags */ - pFsFileInfo->Flags = 0; - for (BitNum = 0; BitNum < 16; BitNum++ ) - { - if (( Msg.Rsp.Flags >> BitNum) & 0x1 ) - { - pFsFileInfo->Flags |= FlagsTranslate[BitNum]; - } - } - - pFsFileInfo->Len = Msg.Rsp.FileLen; - pFsFileInfo->MaxSize = Msg.Rsp.AllocatedLen; - pFsFileInfo->Token[0] = Msg.Rsp.Token[0]; - pFsFileInfo->Token[1] = Msg.Rsp.Token[1]; - pFsFileInfo->Token[2] = Msg.Rsp.Token[2]; - pFsFileInfo->Token[3] = Msg.Rsp.Token[3]; - pFsFileInfo->StorageSize = Msg.Rsp.FileStorageSize; - pFsFileInfo->WriteCounter = Msg.Rsp.FileWriteCounter; - - return (_i16)((_i16)Msg.Rsp.Status); -} -#endif - -/*****************************************************************************/ -/* sl_FsDel */ -/*****************************************************************************/ -typedef union -{ - SlFsDeleteCommand_t Cmd; - SlFsDeleteResponse_t Rsp; -}_SlFsDeleteMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_FsDel) - -static const _SlCmdCtrl_t _SlFsDeleteCmdCtrl = -{ - SL_OPCODE_NVMEM_FILEDELCOMMAND, - (_SlArgSize_t)sizeof(SlFsDeleteCommand_t), - (_SlArgSize_t)sizeof(SlFsDeleteResponse_t) -}; - -_i16 sl_FsDel(const _u8 *pFileName,const _u32 Token) -{ - _SlFsDeleteMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) - { - return SL_ERROR_FS_WRONG_FILE_NAME; - } - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - CmdExt.TxPayload1Len = (_u16)((_SlFsStrlen(pFileName)+4) & (~3)); /* add 4: 1 for NULL and the 3 for align */ - CmdExt.pTxPayload1 = (_u8*)pFileName; - Msg.Cmd.Token = Token; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsDeleteCmdCtrl, &Msg, &CmdExt)); - - return (_i16)((_i16)Msg.Rsp.status); -} -#endif - -/*****************************************************************************/ -/* sl_FsCtl */ -/*****************************************************************************/ -typedef union -{ - SlFsFileSysControlCommand_t Cmd; - SlFsFileSysControlResponse_t Rsp; -}_SlFsFileSysControlMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsCtl) - -const _SlCmdCtrl_t _SlFsFileSysControlCmdCtrl = -{ - SL_OPCODE_NVMEM_NVMEMFILESYSTEMCONTROLCOMMAND, - sizeof(SlFsFileSysControlCommand_t), - sizeof(SlFsFileSysControlResponse_t) -}; - -_i32 sl_FsCtl( SlFsCtl_e Command, _u32 Token, _u8 *pFileName, const _u8 *pData, _u16 DataLen, _u8 *pOutputData, _u16 OutputDataLen,_u32 *pNewToken ) -{ - _SlFsFileSysControlMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - Msg.Cmd.Token = Token; - Msg.Cmd.Operation = (_u8)Command; - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - if ((SL_FS_CTL_ROLLBACK == Command) || (SL_FS_CTL_COMMIT == Command )) - { - Msg.Cmd.FileNameLength = _SlFsStrlen(pFileName) + 1 ; - - if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) - { - return SL_ERROR_FS_WRONG_FILE_NAME; - } - - /*the data is aligned*/ - CmdExt.RxPayloadLen = DataLen; - CmdExt.pRxPayload = (_u8 *)(pData); - - CmdExt.TxPayload1Len = (_SlFsStrlen(pFileName) + 4) & (~3); - CmdExt.pTxPayload1 = pFileName; - - Msg.Cmd.BufferLength = CmdExt.RxPayloadLen + CmdExt.TxPayload1Len; - - if(CmdExt.pRxPayload != NULL && CmdExt.RxPayloadLen != 0) - { - CmdExt.RxPayloadLen = CmdExt.RxPayloadLen * (-1); - } - } - else if( SL_FS_CTL_RENAME == Command ) - { - if ( _SlFsStrlen(pFileName) >= SL_FS_MAX_FILE_NAME_LENGTH ) - { - return SL_ERROR_FS_WRONG_FILE_NAME; - } - - Msg.Cmd.FileNameLength = (_SlFsStrlen(pFileName) + 4) & (~3); - - /*current file name*/ - CmdExt.RxPayloadLen = (_u16)Msg.Cmd.FileNameLength; - CmdExt.pRxPayload = pFileName; - - /*New file name*/ - CmdExt.TxPayload1Len = (_SlFsStrlen(pData) + 4) & (~3);; - CmdExt.pTxPayload1 = (_u8 *)(pData); - - Msg.Cmd.BufferLength = CmdExt.RxPayloadLen + CmdExt.TxPayload1Len; - - if(CmdExt.pRxPayload != NULL && CmdExt.RxPayloadLen != 0) - { - CmdExt.RxPayloadLen = CmdExt.RxPayloadLen * (-1); - } - } - else - { - Msg.Cmd.FileNameLength = 0; - - CmdExt.TxPayload1Len = (DataLen + 3) & (~3); - CmdExt.pTxPayload1 = (_u8 *)(pData); - - CmdExt.RxPayloadLen = OutputDataLen; - CmdExt.pRxPayload = pOutputData; - - Msg.Cmd.BufferLength = CmdExt.TxPayload1Len; - } - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsFileSysControlCmdCtrl, &Msg, &CmdExt)); - - if( pNewToken != NULL ) - { - *pNewToken = Msg.Rsp.Token; - } - - return (_i32)((_i32)Msg.Rsp.Status); -} -#endif - - -/*****************************************************************************/ -/* sl_FsProgram */ -/*****************************************************************************/ -typedef union -{ - SlFsProgramCommand_t Cmd; - SlFsProgramResponse_t Rsp; -}_SlFsProgrammingMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsProgram) - -const _SlCmdCtrl_t _SlFsProgrammingCmdCtrl = -{ - SL_OPCODE_NVMEM_NVMEMFSPROGRAMMINGCOMMAND, - sizeof(SlFsProgramCommand_t), - sizeof(SlFsProgramResponse_t) -}; - -_i32 sl_FsProgram(const _u8* pData , _u16 DataLen ,const _u8 * pKey , _u32 Flags ) -{ - _SlFsProgrammingMsg_u Msg; - _SlCmdExt_t CmdExt; - _u16 ChunkLen; - - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - Msg.Cmd.Flags = (_u32)Flags; - - _SlDrvResetCmdExt(&CmdExt); - - /* no data and no key, called only for extracting the image */ - if( (DataLen == 0) && (pKey == NULL) ) - { - Msg.Cmd.ChunkLen = 0; - Msg.Cmd.KeyLen = 0; - Msg.Cmd.Flags = Flags; - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsProgrammingCmdCtrl, &Msg, &CmdExt)); - } - else if( (DataLen> 0) && ( pData == NULL)) - { - return( ((_i32)SL_ERROR_FS_WRONG_INPUT_SIZE) << 16 ); - } - else if( (DataLen == 0) && (pKey != NULL) ) - { - Msg.Cmd.ChunkLen = 0; - Msg.Cmd.KeyLen = sizeof(SlFsKey_t);; - Msg.Cmd.Flags = Flags; - CmdExt.pTxPayload1 = (_u8*)pKey; - CmdExt.TxPayload1Len = sizeof(SlFsKey_t); - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsProgrammingCmdCtrl, &Msg, &CmdExt)); - } - else /* DataLen > 0 */ - { - if( (DataLen & 0xF) > 0) - { - return( ((_i32)SL_ERROR_FS_NOT_16_ALIGNED) << 16 ); - } - Msg.Cmd.Flags = Flags; - - CmdExt.pTxPayload1 = (_u8 *)pData; - ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE, DataLen); - - while(ChunkLen > 0) - { - Msg.Cmd.ChunkLen = ChunkLen; - CmdExt.TxPayload1Len = ChunkLen; - if( pKey != NULL ) - { - Msg.Cmd.KeyLen = sizeof(SlFsKey_t); - CmdExt.RxPayloadLen = sizeof(SlFsKey_t); - CmdExt.pRxPayload = (_u8 *)pKey; - - if(CmdExt.pRxPayload != NULL && CmdExt.RxPayloadLen != 0) - { - CmdExt.RxPayloadLen = CmdExt.RxPayloadLen * (-1); - } - } - else /* No key */ - { - Msg.Cmd.KeyLen = 0; - CmdExt.RxPayloadLen = 0; - CmdExt.pRxPayload = NULL; - } - - VERIFY_RET_OK( _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsProgrammingCmdCtrl, &Msg, &CmdExt)); - - if( Msg.Rsp.Status <= 0 ) /* Error or finished */ - { - return (_i32)(Msg.Rsp.Status); - } - - DataLen -= ChunkLen; - CmdExt.pTxPayload1 += ChunkLen; - - ChunkLen = (_u16)sl_min(MAX_NVMEM_CHUNK_SIZE, DataLen); - } - } - - return (_i32)(Msg.Rsp.Status); -} -#endif - -/*****************************************************************************/ -/* sl_FsGetFileList */ -/*****************************************************************************/ -typedef union -{ - SlFsGetFileListCommand_t Cmd; - SlFsGetFileListResponse_t Rsp; -}_SlFsGetFileListMsg_u; - -#if _SL_INCLUDE_FUNC(sl_FsGetFileList) - -const _SlCmdCtrl_t _SlFsGetFileListCmdCtrl = -{ - SL_OPCODE_NVMEM_NVMEMGETFILELISTCOMMAND, - sizeof(SlFsGetFileListCommand_t), - sizeof(SlFsGetFileListResponse_t) -}; - -_i32 sl_FsGetFileList(_i32* pIndex, _u8 Count, _u8 MaxEntryLen , _u8* pBuff, SlFileListFlags_t Flags ) -{ - _SlFsGetFileListMsg_u Msg; - _SlCmdExt_t CmdExt; - _u16 OutputBufferSize; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_FS); - - _SlDrvResetCmdExt(&CmdExt); - - Msg.Cmd.Index = *pIndex; - Msg.Cmd.MaxEntryLen = MaxEntryLen & (~3); /* round to modulu 4 */ - Msg.Cmd.Count = Count; - Msg.Cmd.Flags = (_u8)Flags; - - OutputBufferSize = Msg.Cmd.Count * Msg.Cmd.MaxEntryLen; - if( OutputBufferSize > MAX_NVMEM_CHUNK_SIZE ) - { - return SL_ERROR_FS_WRONG_INPUT_SIZE; - } - - CmdExt.RxPayloadLen = OutputBufferSize; - CmdExt.pRxPayload = pBuff; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlFsGetFileListCmdCtrl, &Msg, &CmdExt)); - - *pIndex = Msg.Rsp.Index; - - return (_i32)((_i32)Msg.Rsp.NumOfEntriesOrError); -} -#endif - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/netapp.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/netapp.c deleted file mode 100644 index d7bd525817c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/netapp.c +++ /dev/null @@ -1,1654 +0,0 @@ -/* - * netapp.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* Functions prototypes */ -/*****************************************************************************/ -_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByName(void *pVoidBuf); - -_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByService(void *pVoidBuf); -_SlReturnVal_t _SlNetAppHandleAsync_PingResponse(void *pVoidBuf); -static void _SlNetAppCopyPingResultsToReport(SlPingReportResponse_t *pResults,SlNetAppPingReport_t *pReport); - -_i16 _SlNetAppMDNSRegisterUnregisterService(const _i8* pServiceName, - const _u8 ServiceNameLen, - const _i8* pText, - const _u8 TextLen, - const _u16 Port, - const _u32 TTL, - const _u32 Options); - - -_u16 _SlNetAppSendTokenValue(SlNetAppHttpServerData_t * Token); - -_u16 _SlNetAppSendResponse( _u16 handle, SlNetAppResponse_t *NetAppResponse); - -#define SL_NETAPP_SERVICE_SIZE_MASK (0x7) -#define SL_NETAPP_PING_GUARD_INTERVAL (20000) - -static _u16 NetAppServiceSizeLUT[] = -{ - (_u16)sizeof(_BasicResponse_t), /* 0 - Default value */ - (_u16)sizeof(SlNetAppGetFullServiceWithTextIpv4List_t), /* 1 - SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV4_TYPE */ - (_u16)sizeof(SlNetAppGetFullServiceIpv4List_t), /* 2 - SL_NETAPP_FULL_SERVICE_IPV4_TYPE */ - (_u16)sizeof(SlNetAppGetShortServiceIpv4List_t), /* 3 - SL_NETAPP_SHORT_SERVICE_IPV4_TYPE */ - (_u16)sizeof(SlNetAppGetFullServiceWithTextIpv6List_t), /* 4 - SL_NETAPP_FULL_SERVICE_WITH_TEXT_IPV6_TYPE */ - (_u16)sizeof(SlNetAppGetFullServiceIpv6List_t), /* 5 - SL_NETAPP_FULL_SERVICE_IPV6_TYPE */ - (_u16)sizeof(SlNetAppGetShortServiceIpv6List_t), /* 6 - SL_NETAPP_SHORT_SERVICE_IPV6_TYPE */ - (_u16)sizeof(_BasicResponse_t), /* 7 - Default value */ -}; - -typedef union -{ - _NetAppStartStopCommand_t Cmd; - _NetAppStartStopResponse_t Rsp; -}_SlNetAppStartStopMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_NetAppStart) - -static const _SlCmdCtrl_t _SlNetAppStartCtrl = -{ - SL_OPCODE_NETAPP_START_COMMAND, - (_SlArgSize_t)sizeof(_NetAppStartStopCommand_t), - (_SlArgSize_t)sizeof(_NetAppStartStopResponse_t) -}; - -_i16 sl_NetAppStart(const _u32 AppBitMap) -{ - _SlNetAppStartStopMsg_u Msg; - Msg.Cmd.AppId = AppBitMap; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppStartCtrl, &Msg, NULL)); - - return Msg.Rsp.status; -} -#endif - -/***************************************************************************** - sl_NetAppStop -*****************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_NetAppStop) - -static const _SlCmdCtrl_t _SlNetAppStopCtrl = -{ - SL_OPCODE_NETAPP_STOP_COMMAND, - (_SlArgSize_t)sizeof(_NetAppStartStopCommand_t), - (_SlArgSize_t)sizeof(_NetAppStartStopResponse_t) -}; - -_i16 sl_NetAppStop(const _u32 AppBitMap) -{ - _SlNetAppStartStopMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - Msg.Cmd.AppId = AppBitMap; - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppStopCtrl, &Msg, NULL)); - - return Msg.Rsp.status; -} -#endif - - -/***************************************************************************** - sl_NetAppArpFlush -*****************************************************************************/ - -#if _SL_INCLUDE_FUNC(sl_NetAppArpFlush) - - -_i16 sl_NetAppArpFlush(void) -{ - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - return _SlDrvBasicCmd(SL_OPCODE_NETAPP_ARPFLUSH); -} -#endif - -/***************************************************************************** - sl_NetAppNdFlush -*****************************************************************************/ - -#if _SL_INCLUDE_FUNC(sl_NetAppNdFlush) - - -_i16 sl_NetAppNdFlush(void) -{ - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - return _SlDrvBasicCmd(SL_OPCODE_NETAPP_NDFLUSH_V6); -} -#endif - -/******************************************************************************/ -/* sl_NetAppGetServiceList */ -/******************************************************************************/ -typedef struct -{ - _u8 IndexOffest; - _u8 MaxServiceCount; - _u8 Flags; - _i8 Padding; -}NetappGetServiceListCMD_t; - -typedef union -{ - NetappGetServiceListCMD_t Cmd; - _BasicResponse_t Rsp; -}_SlNetappGetServiceListMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_NetAppGetServiceList) - -static const _SlCmdCtrl_t _SlGetServiceListeCtrl = -{ - SL_OPCODE_NETAPP_NETAPP_MDNS_LOOKUP_SERVICE, - (_SlArgSize_t)sizeof(NetappGetServiceListCMD_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_NetAppGetServiceList(const _u8 IndexOffest, - const _u8 MaxServiceCount, - const _u8 Flags, - _i8 *pBuffer, - const _u32 BufferLength - ) -{ - - _i32 retVal= 0; - _SlNetappGetServiceListMsg_u Msg; - _SlCmdExt_t CmdExt; - _u16 ServiceSize = 0; - _u16 BufferSize = 0; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - /* - Calculate RX pBuffer size - WARNING: - if this size is BufferSize than 1480 error should be returned because there - is no place in the RX packet. - */ - ServiceSize = NetAppServiceSizeLUT[Flags & SL_NETAPP_SERVICE_SIZE_MASK]; - BufferSize = MaxServiceCount * ServiceSize; - - /* Check the size of the requested services is smaller than size of the user buffer. - If not an error is returned in order to avoid overwriting memory. */ - if(BufferLength < BufferSize) - { - return SL_ERROR_NET_APP_RX_BUFFER_LENGTH; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)BufferSize; - CmdExt.pRxPayload = (_u8 *)pBuffer; - - Msg.Cmd.IndexOffest = IndexOffest; - Msg.Cmd.MaxServiceCount = MaxServiceCount; - Msg.Cmd.Flags = Flags; - Msg.Cmd.Padding = 0; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetServiceListeCtrl, &Msg, &CmdExt)); - retVal = Msg.Rsp.status; - - return (_i16)retVal; -} - -#endif - -/*****************************************************************************/ -/* sl_mDNSRegisterService */ -/*****************************************************************************/ -/* - * The below struct depicts the constant parameters of the command/API RegisterService. - * - 1. ServiceLen - The length of the service should be smaller than SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - 2. TextLen - The length of the text should be smaller than SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - 3. port - The port on this target host. - 4. TTL - The TTL of the service - 5. Options - bitwise parameters: - bit 0 - is unique (means if the service needs to be unique) - bit 31 - for internal use if the service should be added or deleted (set means ADD). - bit 1-30 for future. - - NOTE: - - 1. There are another variable parameter is this API which is the service name and the text. - 2. According to now there is no warning and Async event to user on if the service is a unique. -* - */ - -typedef struct -{ - _u8 ServiceNameLen; - _u8 TextLen; - _u16 Port; - _u32 TTL; - _u32 Options; -}NetappMdnsSetService_t; - -typedef union -{ - NetappMdnsSetService_t Cmd; - _BasicResponse_t Rsp; -}_SlNetappMdnsRegisterServiceMsg_u; - -#if (_SL_INCLUDE_FUNC(sl_NetAppMDNSRegisterService) || _SL_INCLUDE_FUNC(sl_NetAppMDNSUnregisterService)) - -static const _SlCmdCtrl_t _SlRegisterServiceCtrl = -{ - SL_OPCODE_NETAPP_MDNSREGISTERSERVICE, - (_SlArgSize_t)sizeof(NetappMdnsSetService_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -/****************************************************************************** - - sl_NetAppMDNSRegisterService - - CALLER user from its host - - - DESCRIPTION: - Add/delete service - The function manipulates the command that register the service and call - to the NWP in order to add/delete the service to/from the mDNS package and to/from the DB. - - This register service is a service offered by the application. - This unregister service is a service offered by the application before. - - The service name should be full service name according to RFC - of the DNS-SD - means the value in name field in SRV answer. - - Example for service name: - 1. PC1._ipp._tcp.local - 2. PC2_server._ftp._tcp.local - - If the option is_unique is set, mDNS probes the service name to make sure - it is unique before starting to announce the service on the network. - Instance is the instance portion of the service name. - - - - - PARAMETERS: - - The command is from constant parameters and variables parameters. - - Constant parameters are: - - ServiceLen - The length of the service. - TextLen - The length of the service should be smaller than 64. - port - The port on this target host. - TTL - The TTL of the service - Options - bitwise parameters: - bit 0 - is unique (means if the service needs to be unique) - bit 31 - for internal use if the service should be added or deleted (set means ADD). - bit 1-30 for future. - - The variables parameters are: - - Service name(full service name) - The service name. - Example for service name: - 1. PC1._ipp._tcp.local - 2. PC2_server._ftp._tcp.local - - Text - The description of the service. - should be as mentioned in the RFC - (according to type of the service IPP,FTP...) - - NOTE - pay attention - - 1. Temporary - there is an allocation on stack of internal buffer. - Its size is SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - It means that the sum of the text length and service name length cannot be bigger than - SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - If it is - An error is returned. - - 2. According to now from certain constraints the variables parameters are set in the - attribute part (contain constant parameters) - - - - RETURNS: Status - the immediate response of the command status. - 0 means success. - -******************************************************************************/ -_i16 _SlNetAppMDNSRegisterUnregisterService(const _i8* pServiceName, - const _u8 ServiceNameLen, - const _i8* pText, - const _u8 TextLen, - const _u16 Port, - const _u32 TTL, - const _u32 Options) -{ - _SlNetappMdnsRegisterServiceMsg_u Msg; - _SlCmdExt_t CmdExt ; - _i8 ServiceNameAndTextBuffer[SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH]; - _i8 *TextPtr; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - /* - - NOTE - pay attention - - 1. Temporary - there is an allocation on stack of internal buffer. - Its size is SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - It means that the sum of the text length and service name length cannot be bigger than - SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - If it is - An error is returned. - - 2. According to now from certain constraints the variables parameters are set in the - attribute part (contain constant parameters) - - */ - - /*build the attribute part of the command. - It contains the constant parameters of the command*/ - - Msg.Cmd.ServiceNameLen = ServiceNameLen; - Msg.Cmd.Options = Options; - Msg.Cmd.Port = Port; - Msg.Cmd.TextLen = TextLen; - Msg.Cmd.TTL = TTL; - - /*Build the payload part of the command - Copy the service name and text to one buffer. - NOTE - pay attention - The size of the service length + the text length should be smaller than 255, - Until the simplelink drive supports to variable length through SPI command. */ - if(TextLen + ServiceNameLen > (SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH - 1 )) /*-1 is for giving a place to set null termination at the end of the text*/ - { - return -1; - } - - _SlDrvMemZero(ServiceNameAndTextBuffer, (_u16)SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH); - - /*Copy the service name*/ - sl_Memcpy(ServiceNameAndTextBuffer, - pServiceName, - ServiceNameLen); - - if(TextLen > 0 ) - { - TextPtr = &ServiceNameAndTextBuffer[ServiceNameLen]; - /*Copy the text just after the service name*/ - sl_Memcpy(TextPtr, - pText, - TextLen); - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = (TextLen + ServiceNameLen); - CmdExt.pTxPayload1 = (_u8 *)ServiceNameAndTextBuffer; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlRegisterServiceCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/**********************************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_NetAppMDNSRegisterService) - -_i16 sl_NetAppMDNSRegisterService(const _i8* pServiceName, - const _u8 ServiceNameLen, - const _i8* pText, - const _u8 TextLen, - const _u16 Port, - const _u32 TTL, - _u32 Options) -{ - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - /* - - NOTE - pay attention - - 1. Temporary - there is an allocation on stack of internal buffer. - Its size is SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - It means that the sum of the text length and service name length cannot be bigger than - SL_NETAPP_MDNS_MAX_SERVICE_NAME_AND_TEXT_LENGTH. - If it is - An error is returned. - - 2. According to now from certain constraints the variables parameters are set in the - attribute part (contain constant parameters) - - */ - - /*Set the add service bit in the options parameter. - In order not use different opcodes for the register service and unregister service - bit 31 in option is taken for this purpose. if it is set it means in NWP that the service should be added - if it is cleared it means that the service should be deleted and there is only meaning to pServiceName - and ServiceNameLen values. */ - Options |= SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT; - - return _SlNetAppMDNSRegisterUnregisterService(pServiceName, - ServiceNameLen, - pText, - TextLen, - Port, - TTL, - Options); -} -#endif -/**********************************************************************************************/ - - -/**********************************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_NetAppMDNSUnRegisterService) - -_i16 sl_NetAppMDNSUnRegisterService(const _i8* pServiceName, - const _u8 ServiceNameLen,_u32 Options) -{ - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - /* - - NOTE - pay attention - - The size of the service length should be smaller than 255, - Until the simplelink drive supports to variable length through SPI command. - - - */ - - /*Clear the add service bit in the options parameter. - In order not use different opcodes for the register service and unregister service - bit 31 in option is taken for this purpose. if it is set it means in NWP that the service should be added - if it is cleared it means that the service should be deleted and there is only meaning to pServiceName - and ServiceNameLen values.*/ - - Options &= (~SL_NETAPP_MDNS_OPTIONS_ADD_SERVICE_BIT); - - return _SlNetAppMDNSRegisterUnregisterService( pServiceName, - ServiceNameLen, - NULL, - 0, - 0, - 0, - Options); - - -} -#endif -/**********************************************************************************************/ - - -/*****************************************************************************/ -/* sl_DnsGetHostByService */ -/*****************************************************************************/ -/* - * The below struct depicts the constant parameters of the command/API sl_DnsGetHostByService. - * - 1. ServiceLen - The length of the service should be smaller than 255. - 2. AddrLen - TIPv4 or IPv6 (SL_AF_INET , SL_AF_INET6). -* - */ - -typedef struct -{ - _u8 ServiceLen; - _u8 AddrLen; - _u16 Padding; -}_GetHostByServiceCommand_t; - -/* - * The below structure depict the constant parameters that are returned in the Async event answer - * according to command/API sl_DnsGetHostByService for IPv4 and IPv6. - * - 1Status - The status of the response. - 2.Address - Contains the IP address of the service. - 3.Port - Contains the port of the service. - 4.TextLen - Contains the max length of the text that the user wants to get. - it means that if the test of service is bigger that its value than - the text is cut to inout_TextLen value. - Output: Contain the length of the text that is returned. Can be full text or part - of the text (see above). -* -*/ - -typedef struct -{ - _u16 Status; - _u16 TextLen; - _u32 Port; - _u32 Address[4]; -}_GetHostByServiceIPv6AsyncResponse_t; - -/* - * The below struct contains pointers to the output parameters that the user gives - * - */ -typedef struct -{ - _i16 Status; - _u32 *out_pAddr; - _u32 *out_pPort; - _u16 *inout_TextLen; /* in: max len , out: actual len */ - _i8 *out_pText; -}_GetHostByServiceAsyncResponse_t; - -typedef union -{ - _GetHostByServiceCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlGetHostByServiceMsg_u; - -#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByService) - -static const _SlCmdCtrl_t _SlGetHostByServiceCtrl = -{ - SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICE, - (_SlArgSize_t)sizeof(_GetHostByServiceCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -/******************************************************************************/ - -_i16 sl_NetAppDnsGetHostByService(_i8 *pServiceName, /* string containing all (or only part): name + subtype + service */ - const _u8 ServiceLen, - const _u8 Family, /* 4-IPv4 , 16-IPv6 */ - _u32 pAddr[], - _u32 *pPort, - _u16 *pTextLen, /* in: max len , out: actual len */ - _i8 *pText - ) -{ - _SlGetHostByServiceMsg_u Msg; - _SlCmdExt_t CmdExt ; - _GetHostByServiceAsyncResponse_t AsyncRsp; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - _SlDrvMemZero(&AsyncRsp, sizeof(_GetHostByServiceAsyncResponse_t)); - -/* - Note: - 1. The return's attributes are belonged to first service that is found. - It can be other services with the same service name will response to - the query. The results of these responses are saved in the peer cache of the NWP, and - should be read by another API. - - 2. Text length can be 120 bytes only - not more - It is because of constraints in the NWP on the buffer that is allocated for the Async event. - - 3.The API waits to Async event by blocking. It means that the API is finished only after an Async event - is sent by the NWP. - - 4.No rolling option!!! - only PTR type is sent. - -*/ - /*build the attribute part of the command. - It contains the constant parameters of the command */ - - Msg.Cmd.ServiceLen = ServiceLen; - Msg.Cmd.AddrLen = Family; - - /*Build the payload part of the command - Copy the service name and text to one buffer.*/ - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = ServiceLen; - CmdExt.pTxPayload1 = (_u8 *)pServiceName; - - /*set pointers to the output parameters (the returned parameters). - This pointers are belonged to local struct that is set to global Async response parameter. - It is done in order not to run more than one sl_DnsGetHostByService at the same time. - The API should be run only if global parameter is pointed to NULL. */ - AsyncRsp.out_pText = pText; - AsyncRsp.inout_TextLen = (_u16* )pTextLen; - AsyncRsp.out_pPort = pPort; - AsyncRsp.out_pAddr = (_u32 *)&pAddr[0]; - - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, GETHOSYBYSERVICE_ID, SL_MAX_SOCKETS); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - if (SL_AF_INET6 == Family) - { - g_pCB->ObjPool[ObjIdx].AdditionalData |= SL_NETAPP_FAMILY_MASK; - } - /* Send the command */ - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetHostByServiceCtrl, &Msg, &CmdExt)); - - /* If the immediate reponse is O.K. than wait for aSYNC event response. */ - if(SL_RET_CODE_OK == Msg.Rsp.status) - { - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); - - /* If we are - it means that Async event was sent. - The results are copied in the Async handle return functions */ - - Msg.Rsp.status = AsyncRsp.Status; - } - - _SlDrvReleasePoolObj(ObjIdx); - return Msg.Rsp.status; -} -#endif - -/******************************************************************************/ - -/****************************************************************************** - _SlNetAppHandleAsync_DnsGetHostByService - - CALLER NWP - Async event on sl_DnsGetHostByService with IPv4 Family - - - DESCRIPTION: - - Async event on sl_DnsGetHostByService command with IPv4 Family. - Return service attributes like IP address, port and text according to service name. - The user sets a service name Full/Part (see example below), and should get the: - 1. IP of the service - 2. The port of service. - 3. The text of service. - - Hence it can make a connection to the specific service and use it. - It is similar to get host by name method. - - It is done by a single shot query with PTR type on the service name. - - - - Note: - 1. The return's attributes are belonged to first service that is found. - It can be other services with the same service name will response to - the query. The results of these responses are saved in the peer cache of the NWP, and - should be read by another API. - - - PARAMETERS: - - pVoidBuf - is point to opcode of the event. - it contains the outputs that are given to the user - - outputs description: - - 1.out_pAddr[] - output: Contain the IP address of the service. - 2.out_pPort - output: Contain the port of the service. - 3.inout_TextLen - Input: Contain the max length of the text that the user wants to get. - it means that if the test of service is bigger that its value than - the text is cut to inout_TextLen value. - Output: Contain the length of the text that is returned. Can be full text or part - of the text (see above). - - 4.out_pText - Contain the text of the service (full or part see above- inout_TextLen description). - - * - - - RETURNS: success or fail. - -******************************************************************************/ -_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByService(void *pVoidBuf) -{ - _u16 TextLen; - _u16 UserTextLen; - _GetHostByServiceAsyncResponse_t* Res= NULL; - _GetHostByServiceIPv6AsyncResponse_t *pMsgArgs = (_GetHostByServiceIPv6AsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - /*Res pointed to mDNS global object struct */ - Res = (_GetHostByServiceAsyncResponse_t*)g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs; - /*IPv6*/ - if(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].AdditionalData & SL_NETAPP_FAMILY_MASK) - { - Res->out_pAddr[1] = pMsgArgs->Address[1]; /* Copy data from IPv6 address to Host user's pAddr. The array must be at least 4 cells of _u32 */ - Res->out_pAddr[2] = pMsgArgs->Address[2]; - Res->out_pAddr[3] = pMsgArgs->Address[3]; - } - - TextLen = pMsgArgs->TextLen; - - /*It is 4 bytes so we avoid from memcpy*/ - Res->out_pAddr[0] = pMsgArgs->Address[0]; /* Copy first cell data from IPv4/6 address to Host user's pAddr */ - Res->out_pPort[0] = pMsgArgs->Port; - Res->Status = (_i16)pMsgArgs->Status; - /*set to TextLen the text length of the user (input fromthe user).*/ - UserTextLen = Res->inout_TextLen[0]; - - /*Cut the service text if the user requested for smaller text.*/ - UserTextLen = (TextLen <= UserTextLen) ? TextLen : UserTextLen; - Res->inout_TextLen[0] = UserTextLen ; - - /************************************************************************************************** - - 2. Copy the payload part of the evnt (the text) to the payload part of the response - the lenght of the copy is according to the text length in the attribute part. */ - - /*IPv6*/ - if (g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].AdditionalData & SL_NETAPP_FAMILY_MASK) - { - sl_Memcpy(Res->out_pText, - (_i8 *)(& pMsgArgs[1]), /* & pMsgArgs[1] -> 1st byte after the fixed header = 1st byte of variable text.*/ - UserTextLen); - } - else - { - sl_Memcpy(Res->out_pText, - (_i8 *)(& pMsgArgs->Address[1]), /* & pMsgArgs[1] -> 1st byte after the fixed header = 1st byte of variable text.*/ - UserTextLen); - } - - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - - return SL_OS_RET_CODE_OK; -} - -/*****************************************************************************/ -/* _SlNetAppHandleAsync_DnsGetHostByAddr */ -/*****************************************************************************/ -_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByAddr(void *pVoidBuf) -{ - SL_TRACE0(DBG_MSG, MSG_303, "STUB: _SlNetAppHandleAsync_DnsGetHostByAddr not implemented yet!"); - return SL_OS_RET_CODE_OK; -} - -/*****************************************************************************/ -/* sl_DnsGetHostByName */ -/*****************************************************************************/ -typedef union -{ - NetAppGetHostByNameIPv4AsyncResponse_t IpV4; - NetAppGetHostByNameIPv6AsyncResponse_t IpV6; -}_GetHostByNameAsyncResponse_u; - -typedef union -{ - NetAppGetHostByNameCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlGetHostByNameMsg_u; - -#if _SL_INCLUDE_FUNC(sl_NetAppDnsGetHostByName) -static const _SlCmdCtrl_t _SlGetHostByNameCtrl = -{ - SL_OPCODE_NETAPP_DNSGETHOSTBYNAME, - (_SlArgSize_t)sizeof(NetAppGetHostByNameCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_NetAppDnsGetHostByName(_i8 * pHostName,const _u16 NameLen, _u32* OutIpAddr,const _u8 Family ) -{ - _SlGetHostByNameMsg_u Msg; - _SlCmdExt_t ExtCtrl; - _GetHostByNameAsyncResponse_u AsyncRsp; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - _SlDrvResetCmdExt(&ExtCtrl); - ExtCtrl.TxPayload1Len = NameLen; - ExtCtrl.pTxPayload1 = (_u8 *)pHostName; - - Msg.Cmd.Len = NameLen; - Msg.Cmd.Family = Family; - - /*Use Obj to issue the command, if not available try later */ - ObjIdx = _SlDrvWaitForPoolObj(GETHOSYBYNAME_ID,SL_MAX_SOCKETS); - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) - { - return SL_RET_CODE_STOP_IN_PROGRESS; - } - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&AsyncRsp; - /*set bit to indicate IPv6 address is expected */ - if (SL_AF_INET6 == Family) - { - g_pCB->ObjPool[ObjIdx].AdditionalData |= SL_NETAPP_FAMILY_MASK; - } - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetHostByNameCtrl, &Msg, &ExtCtrl)); - - if(SL_RET_CODE_OK == Msg.Rsp.status) - { - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); - - Msg.Rsp.status = (_i16)AsyncRsp.IpV4.Status; - - if(SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status) - { - sl_Memcpy((_i8 *)OutIpAddr, - (_i8 *)&AsyncRsp.IpV4.Ip0, - (SL_AF_INET == Family) ? SL_IPV4_ADDRESS_SIZE : SL_IPV6_ADDRESS_SIZE); - } - } - _SlDrvReleasePoolObj(ObjIdx); - return Msg.Rsp.status; -} -#endif - - -/******************************************************************************/ -/* _SlNetAppHandleAsync_DnsGetHostByName */ -/******************************************************************************/ -_SlReturnVal_t _SlNetAppHandleAsync_DnsGetHostByName(void *pVoidBuf) -{ - NetAppGetHostByNameIPv4AsyncResponse_t *pMsgArgs = (NetAppGetHostByNameIPv4AsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - /*IPv6 */ - if(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].AdditionalData & SL_NETAPP_FAMILY_MASK) - { - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(NetAppGetHostByNameIPv6AsyncResponse_t)); - } - /*IPv4 */ - else - { - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(NetAppGetHostByNameIPv4AsyncResponse_t)); - } - - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return SL_OS_RET_CODE_OK; -} - -static void _SlNetAppCopyPingResultsToReport(SlPingReportResponse_t *pResults,SlNetAppPingReport_t *pReport) -{ - pReport->PacketsSent = pResults->NumSendsPings; - pReport->PacketsReceived = pResults->NumSuccsessPings; - pReport->MinRoundTime = pResults->RttMin; - pReport->MaxRoundTime = pResults->RttMax; - pReport->AvgRoundTime = pResults->RttAvg; - pReport->TestTime = pResults->TestTime; -} - -/*****************************************************************************/ -/* _SlNetAppHandleAsync_PingResponse */ -/*****************************************************************************/ -_SlReturnVal_t _SlNetAppHandleAsync_PingResponse(void *pVoidBuf) -{ - SlPingReportResponse_t *pMsgArgs = (SlPingReportResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - SlNetAppPingReport_t pingReport; - - if(pPingCallBackFunc) - { - _SlNetAppCopyPingResultsToReport(pMsgArgs,&pingReport); - pPingCallBackFunc(&pingReport); - } - else - { - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_SOCKET_CB(NULL != g_pCB->PingCB.PingAsync.pAsyncRsp); - - if (NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs) - { - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(SlPingReportResponse_t)); - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - } - SL_DRV_PROTECTION_OBJ_UNLOCK(); - } - - return SL_OS_RET_CODE_OK; -} - -/*****************************************************************************/ -/* sl_NetAppPing */ -/*****************************************************************************/ -typedef union -{ - SlNetAppPingCommand_t Cmd; - SlPingReportResponse_t Rsp; -}_SlPingStartMsg_u; - -typedef enum -{ - CMD_PING_TEST_RUNNING = 0, - CMD_PING_TEST_STOPPED -}_SlPingStatus_e; - -#if _SL_INCLUDE_FUNC(sl_NetAppPing) -_i16 sl_NetAppPing(const SlNetAppPingCommand_t* pPingParams, const _u8 Family, SlNetAppPingReport_t *pReport, const P_SL_DEV_PING_CALLBACK pPingCallback) -{ - _SlCmdCtrl_t CmdCtrl = {0, (_SlArgSize_t)sizeof(SlNetAppPingCommand_t), (_SlArgSize_t)sizeof(_BasicResponse_t)}; - _SlPingStartMsg_u Msg; - SlPingReportResponse_t PingRsp; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - _u32 PingTimeout = 0; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - if(NULL != pPingParams) - { - if(SL_AF_INET == Family) - { - CmdCtrl.Opcode = SL_OPCODE_NETAPP_PINGSTART; - sl_Memcpy(&Msg.Cmd.Ip, &pPingParams->Ip, SL_IPV4_ADDRESS_SIZE); - } - else - { - CmdCtrl.Opcode = SL_OPCODE_NETAPP_PINGSTART_V6; - sl_Memcpy(&Msg.Cmd.Ip, &pPingParams->Ip, SL_IPV6_ADDRESS_SIZE); - } - - Msg.Cmd.PingIntervalTime = pPingParams->PingIntervalTime; - Msg.Cmd.PingSize = pPingParams->PingSize; - Msg.Cmd.PingRequestTimeout = pPingParams->PingRequestTimeout; - Msg.Cmd.TotalNumberOfAttempts = pPingParams->TotalNumberOfAttempts; - Msg.Cmd.Flags = pPingParams->Flags; - - - /* calculate the ping timeout according to the parmas + the guard interval */ - PingTimeout = SL_NETAPP_PING_GUARD_INTERVAL + (pPingParams->PingIntervalTime * pPingParams->TotalNumberOfAttempts); - - if (Msg.Cmd.Ip != 0) - { - /* If the following conditions are met, return an error - Wrong ping parameters - ping cannot be called with the following parameters: - 1. infinite ping packet - 2. report only when finished - 3. no callback supplied */ - if ((pPingCallback == NULL) && (pPingParams->Flags == 0) && (pPingParams->TotalNumberOfAttempts == 0)) - { - return SL_RET_CODE_NET_APP_PING_INVALID_PARAMS; - } - - if( pPingCallback ) - { - pPingCallBackFunc = pPingCallback; - } - else - { - /* Use Obj to issue the command, if not available try later */ - ObjIdx = _SlDrvWaitForPoolObj(PING_ID,SL_MAX_SOCKETS); - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) - { - return SL_RET_CODE_STOP_IN_PROGRESS; - } - OSI_RET_OK_CHECK(sl_LockObjLock(&g_pCB->ProtectionLockObj, SL_OS_WAIT_FOREVER)); - /* async response handler for non callback mode */ - g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&PingRsp; - pPingCallBackFunc = NULL; - OSI_RET_OK_CHECK(sl_LockObjUnlock(&g_pCB->ProtectionLockObj)); - } - } - } - /* Issue Stop Command */ - else - { - CmdCtrl.Opcode = SL_OPCODE_NETAPP_PINGSTART; - Msg.Cmd.Ip = 0; - } - /* send the command */ - VERIFY_RET_OK(_SlDrvCmdOp(&CmdCtrl, &Msg, NULL)); - if (Msg.Cmd.Ip != 0) - { - if(CMD_PING_TEST_RUNNING == (_i16)Msg.Rsp.Status || CMD_PING_TEST_STOPPED == (_i16)Msg.Rsp.Status ) - { - /* block waiting for results if no callback function is used */ - if( NULL == pPingCallback ) - { - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, PingTimeout, SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE)); - - if( SL_OS_RET_CODE_OK == (_i16)PingRsp.Status ) - { - _SlNetAppCopyPingResultsToReport(&PingRsp,pReport); - } - _SlDrvReleasePoolObj(ObjIdx); - } - } - else - { /* ping failure, no async response */ - if( NULL == pPingCallback ) - { - _SlDrvReleasePoolObj(ObjIdx); - } - } - } - return (_i16)Msg.Rsp.Status; -} -#endif - -/*****************************************************************************/ -/* sl_NetAppSet */ -/*****************************************************************************/ -typedef union -{ - SlNetAppSetGet_t Cmd; - _BasicResponse_t Rsp; -}_SlNetAppMsgSet_u; - -#if _SL_INCLUDE_FUNC(sl_NetAppSet) - -static const _SlCmdCtrl_t _SlNetAppSetCmdCtrl = -{ - SL_OPCODE_NETAPP_NETAPPSET, - (_SlArgSize_t)sizeof(SlNetAppSetGet_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_NetAppSet(const _u8 AppId ,const _u8 Option, const _u8 OptionLen, const _u8 *pOptionValue) -{ - _SlNetAppMsgSet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = (OptionLen+3) & (~3); - CmdExt.pTxPayload1 = (_u8 *)pOptionValue; - - Msg.Cmd.AppId = AppId; - Msg.Cmd.ConfigLen = OptionLen; - Msg.Cmd.ConfigOpt = Option; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppSetCmdCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/*****************************************************************************/ -/* sl_NetAppSendTokenValue */ -/*****************************************************************************/ -typedef union -{ - SlNetAppHttpServerSendToken_t Cmd; - _BasicResponse_t Rsp; -}_SlNetAppMsgSendTokenValue_u; - -const _SlCmdCtrl_t _SlNetAppSendTokenValueCmdCtrl = -{ - SL_OPCODE_NETAPP_HTTPSENDTOKENVALUE, - (_SlArgSize_t)sizeof(SlNetAppHttpServerSendToken_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_u16 _SlNetAppSendTokenValue(SlNetAppHttpServerData_t * Token_value) -{ - _SlNetAppMsgSendTokenValue_u Msg; - _SlCmdExt_t CmdExt; - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - CmdExt.TxPayload1Len = (Token_value->ValueLen+3) & (~3); - CmdExt.pTxPayload1 = (_u8 *) Token_value->pTokenValue; - - Msg.Cmd.TokenValueLen = Token_value->ValueLen; - Msg.Cmd.TokenNameLen = Token_value->NameLen; - sl_Memcpy(&Msg.Cmd.TokenName[0], Token_value->pTokenName, Token_value->NameLen); - - VERIFY_RET_OK(_SlDrvCmdSend_noLock((_SlCmdCtrl_t *)&_SlNetAppSendTokenValueCmdCtrl, &Msg, &CmdExt)); - - return Msg.Rsp.status; -} - -/*****************************************************************************/ -/* sl_NetAppSendResponse */ -/*****************************************************************************/ -typedef union -{ - SlProtocolNetAppResponse_t Cmd; - _BasicResponse_t Rsp; -}_SlNetAppMsgSendResponse_u; - -const _SlCmdCtrl_t _SlNetAppSendResponseCmdCtrl = -{ - SL_OPCODE_NETAPP_RESPONSE, - sizeof(SlProtocolNetAppResponse_t), - sizeof(_BasicResponse_t) -}; - -_u16 _SlNetAppSendResponse( _u16 handle, SlNetAppResponse_t *NetAppResponse) -{ - _SlNetAppMsgSendResponse_u Msg; - _SlCmdExt_t CmdExt; - _SlReturnVal_t RetVal; - _u16 dataLen; - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - dataLen = NetAppResponse->ResponseData.MetadataLen + NetAppResponse->ResponseData.PayloadLen; - - if ((NetAppResponse->ResponseData.MetadataLen <= SL_NETAPP_REQUEST_MAX_METADATA_LEN) && (dataLen <= SL_NETAPP_REQUEST_MAX_DATA_LEN)) - { - if (dataLen > 0) - { - /* Zero copy of the two parts: metadata + payload */ - CmdExt.pTxPayload1 = NetAppResponse->ResponseData.pMetadata; - CmdExt.TxPayload1Len = NetAppResponse->ResponseData.MetadataLen; - - CmdExt.pTxPayload2 = NetAppResponse->ResponseData.pPayload; - CmdExt.TxPayload2Len = NetAppResponse->ResponseData.PayloadLen; - } - else - { - CmdExt.pTxPayload1 = NULL; - CmdExt.pTxPayload2 = NULL; - } - - CmdExt.RxPayloadLen = 0; - CmdExt.pRxPayload = NULL; - - Msg.Cmd.Handle = handle; - Msg.Cmd.status = NetAppResponse->Status; - Msg.Cmd.MetadataLen = NetAppResponse->ResponseData.MetadataLen; - Msg.Cmd.PayloadLen = NetAppResponse->ResponseData.PayloadLen; - Msg.Cmd.Flags = NetAppResponse->ResponseData.Flags; - - RetVal = _SlDrvCmdSend_noLock((_SlCmdCtrl_t *)&_SlNetAppSendResponseCmdCtrl, &Msg, &CmdExt); - } - else - { - /* TODO: how to return the error code asynchronously? */ - RetVal = SL_ERROR_BSD_ENOMEM; - } - - return RetVal; -} - -/*****************************************************************************/ -/* sl_NetAppRecv */ -/*****************************************************************************/ -typedef union -{ - SlProtocolNetAppReceiveRequest_t Cmd; - _BasicResponse_t Rsp; /* Not used. do we need it? */ -}_SlNetAppReceiveMsg_u; - -#if _SL_INCLUDE_FUNC(sl_NetAppRecv) - -const _SlCmdCtrl_t _SlNetAppReceiveCmdCtrl = -{ - SL_OPCODE_NETAPP_RECEIVEREQUEST, - sizeof(SlProtocolNetAppReceiveRequest_t), - sizeof(_BasicResponse_t) /* Where is this used? */ -}; - -_SlReturnVal_t sl_NetAppRecv( _u16 Handle, _u16 *DataLen, _u8 *pData, _u32 *Flags) -{ - _SlNetAppReceiveMsg_u Msg; - _SlCmdExt_t CmdExt; - SlProtocolNetAppReceive_t AsyncRsp; /* Will be filled when SL_OPCODE_NETAPP_RECEIVE async event is arrived */ - - _SlReturnVal_t RetVal; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - _SlArgsData_t pArgsData; - - /* Validate input arguments */ - if ((NULL == pData) || (0==DataLen)) - { - return SL_ERROR_BSD_EINVAL; - } - - /* Save the user RX bufer. Rx data will be copied into it on the SL_OPCODE_NETAPP_RECEIVE async event */ - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = *DataLen; - CmdExt.pRxPayload = pData; - - /* Prepare the command args */ - Msg.Cmd.Handle = Handle; - Msg.Cmd.MaxBufferLen = *DataLen; - Msg.Cmd.Flags = *Flags; - - /* Use Obj to issue the command, if not available try later */ - ObjIdx = _SlDrvWaitForPoolObj(NETAPP_RECEIVE_ID, SL_MAX_SOCKETS); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - if (SL_RET_CODE_STOP_IN_PROGRESS == ObjIdx) - { - return SL_RET_CODE_STOP_IN_PROGRESS; - } - - /* Save the AsyncRsp and cmdExt information for the SL_OPCODE_NETAPP_RECEIVE async event */ - AsyncRsp.Handle = Handle; /* Handle we are waiting for */ - AsyncRsp.Flags = 0; - AsyncRsp.PayloadLen = 0; /* 0 will indicate an error in the SL_OPCODE_NETAPP_RECEIVE async event and that no data arrived. */ - - _SlDrvProtectionObjLockWaitForever(); - - pArgsData.pData = (_u8 *) &CmdExt; - pArgsData.pArgs = (_u8 *) &AsyncRsp; - - g_pCB->ObjPool[ObjIdx].pRespArgs = (_u8 *)&pArgsData; - - _SlDrvProtectionObjUnLock(); - - /* Send the command */ - RetVal = _SlDrvCmdSend((_SlCmdCtrl_t *)&_SlNetAppReceiveCmdCtrl, &Msg, &CmdExt); - - if(SL_OS_RET_CODE_OK == RetVal) - { - /* Wait for SL_OPCODE_NETAPP_RECEIVE async event. Will be signaled by _SlNetAppHandleAsync_NetAppReceive. */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, 0, 0)); - - /* Update information for the user */ - *DataLen = AsyncRsp.PayloadLen; - *Flags = AsyncRsp.Flags; - } - - _SlDrvReleasePoolObj(ObjIdx); - - return RetVal; -} - - -/*****************************************************************************/ -/* _SlNetAppHandleAsync_NetAppReceive */ -/*****************************************************************************/ -void _SlNetAppHandleAsync_NetAppReceive(void *pVoidBuf) -{ - _u8 *pData; - _u16 len; - SlProtocolNetAppReceive_t *AsyncRsp; - _SlCmdExt_t *CmdExt; - SlProtocolNetAppReceive_t *pMsgArgs = (SlProtocolNetAppReceive_t *)_SL_RESP_ARGS_START(pVoidBuf); - - pData = (_u8 *)((SlProtocolNetAppReceive_t *)pMsgArgs + 1); /* Points to the netapp receive payload */ - - _SlDrvProtectionObjLockWaitForever(); - - if (NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs) - { - AsyncRsp = (SlProtocolNetAppReceive_t *) ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))-> pArgs; - CmdExt = (_SlCmdExt_t *) ((_SlArgsData_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))-> pData; - - if (pMsgArgs->Handle == AsyncRsp->Handle) - { - if (pMsgArgs->PayloadLen <= CmdExt->RxPayloadLen) - { - len = pMsgArgs->PayloadLen; - } - else - { - len = CmdExt->RxPayloadLen; - } - - /* Copy the data to the user buffer */ - sl_Memcpy (CmdExt->pRxPayload, pData, len); - - /* Update len and flags */ - AsyncRsp->PayloadLen = len; - AsyncRsp->Flags = pMsgArgs->Flags; - } - } - - _SlDrvSyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - _SlDrvProtectionObjUnLock(); - - return; -} - -#endif - -/*****************************************************************************/ -/* sl_NetAppSend */ -/*****************************************************************************/ -typedef union -{ - SlProtocolNetAppSend_t Cmd; - _BasicResponse_t Rsp; -}_SlNetAppMsgSend_u; - -const _SlCmdCtrl_t _SlNetAppSendCmdCtrl = -{ - SL_OPCODE_NETAPP_SEND, - sizeof(SlProtocolNetAppSend_t), - sizeof(_BasicResponse_t) -}; - -_u16 sl_NetAppSend( _u16 Handle, _u16 DataLen, _u8* pData, _u32 Flags) -{ - _SlNetAppMsgSend_u Msg; - _SlCmdExt_t CmdExt; - - _SlDrvMemZero(&CmdExt, (_u16)sizeof(_SlCmdExt_t)); - - if ((((Flags & SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA) == SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA) && (DataLen <= SL_NETAPP_REQUEST_MAX_METADATA_LEN)) || - (((Flags & SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA) == 0) && (DataLen <= SL_NETAPP_REQUEST_MAX_DATA_LEN))) - { - CmdExt.TxPayload1Len = (DataLen+3) & (~3); - CmdExt.pTxPayload1 = (_u8 *) pData; - - Msg.Cmd.Handle = Handle; - Msg.Cmd.DataLen = DataLen; - Msg.Cmd.Flags = Flags; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppSendCmdCtrl, &Msg, &CmdExt)); - } - else - { - Msg.Rsp.status = SL_ERROR_BSD_ENOMEM; - } - - return Msg.Rsp.status; -} - -/*****************************************************************************/ -/* sl_NetAppGet */ -/*****************************************************************************/ -typedef union -{ - SlNetAppSetGet_t Cmd; - SlNetAppSetGet_t Rsp; -}_SlNetAppMsgGet_u; - -#if _SL_INCLUDE_FUNC(sl_NetAppGet) -static const _SlCmdCtrl_t _SlNetAppGetCmdCtrl = -{ - SL_OPCODE_NETAPP_NETAPPGET, - (_SlArgSize_t)sizeof(SlNetAppSetGet_t), - (_SlArgSize_t)sizeof(SlNetAppSetGet_t) -}; - -_i16 sl_NetAppGet(const _u8 AppId, const _u8 Option,_u8 *pOptionLen, _u8 *pOptionValue) -{ - _SlNetAppMsgGet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETAPP); - - if (*pOptionLen == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)(*pOptionLen); - CmdExt.pRxPayload = (_u8 *)pOptionValue; - - Msg.Cmd.AppId = AppId; - Msg.Cmd.ConfigOpt = Option; - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetAppGetCmdCtrl, &Msg, &CmdExt)); - - - if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *pOptionLen = (_u8)CmdExt.RxPayloadLen; - return SL_ESMALLBUF; - } - else - { - *pOptionLen = (_u8)CmdExt.ActualRxPayloadLen; - } - - return (_i16)Msg.Rsp.Status; -} -#endif - -/*****************************************************************************/ -/* _SlNetAppEventHandler */ -/*****************************************************************************/ -_SlReturnVal_t _SlNetAppEventHandler(void* pArgs) -{ - _SlResponseHeader_t *pHdr = (_SlResponseHeader_t *)pArgs; -#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) - SlNetAppHttpServerEvent_t httpServerEvent; - SlNetAppHttpServerResponse_t httpServerResponse; -#endif - switch(pHdr->GenHeader.Opcode) - { - case SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE: - case SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE_V6: - _SlNetAppHandleAsync_DnsGetHostByName(pArgs); - break; - case SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE: - case SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE_V6: - _SlNetAppHandleAsync_DnsGetHostByService(pArgs); - break; - case SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE: - _SlNetAppHandleAsync_PingResponse(pArgs); - break; - - case SL_OPCODE_NETAPP_HTTPGETTOKENVALUE: - { -#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) - _u8 *pTokenName; - SlNetAppHttpServerData_t Token_value; - SlNetAppHttpServerGetToken_t *httpGetToken = (SlNetAppHttpServerGetToken_t *)_SL_RESP_ARGS_START(pHdr); - pTokenName = (_u8 *)((SlNetAppHttpServerGetToken_t *)httpGetToken + 1); - - httpServerResponse.Response = SL_NETAPP_HTTPSETTOKENVALUE; - httpServerResponse.ResponseData.TokenValue.Len = SL_NETAPP_MAX_TOKEN_VALUE_LEN; - - /* Reuse the async buffer for getting the token value response from the user */ - httpServerResponse.ResponseData.TokenValue.pData = (_u8 *)_SL_RESP_ARGS_START(pHdr) + SL_NETAPP_MAX_TOKEN_NAME_LEN; - - httpServerEvent.Event = SL_NETAPP_EVENT_HTTP_TOKEN_GET; - httpServerEvent.EventData.HttpTokenName.Len = httpGetToken->TokenNameLen; - httpServerEvent.EventData.HttpTokenName.pData = pTokenName; - - Token_value.pTokenName = pTokenName; - - _SlDrvDispatchHttpServerEvents (&httpServerEvent, &httpServerResponse); - - Token_value.ValueLen = httpServerResponse.ResponseData.TokenValue.Len; - Token_value.NameLen = httpServerEvent.EventData.HttpTokenName.Len; - Token_value.pTokenValue = httpServerResponse.ResponseData.TokenValue.pData; - - _SlNetAppSendTokenValue(&Token_value); -#else - - _u8 *pTokenName; - SlNetAppHttpServerData_t Token_value; - SlNetAppHttpServerGetToken_t *httpGetToken = (SlNetAppHttpServerGetToken_t*)_SL_RESP_ARGS_START(pHdr); - pTokenName = (_u8 *)((SlNetAppHttpServerGetToken_t *)httpGetToken + 1); - - Token_value.pTokenName = pTokenName; - Token_value.ValueLen = 0; - Token_value.NameLen = httpGetToken->TokenNameLen; - Token_value.pTokenValue = NULL; - - _SlNetAppSendTokenValue(&Token_value); -#endif - } - break; - - case SL_OPCODE_NETAPP_HTTPPOSTTOKENVALUE: - { -#if defined(slcb_NetAppHttpServerHdlr) || defined(EXT_LIB_REGISTERED_HTTP_SERVER_EVENTS) - _u8 *pPostParams; - - SlNetAppHttpServerPostToken_t *httpPostTokenArgs = (SlNetAppHttpServerPostToken_t *)_SL_RESP_ARGS_START(pHdr); - pPostParams = (_u8 *)((SlNetAppHttpServerPostToken_t *)httpPostTokenArgs + 1); - - httpServerEvent.Event = SL_NETAPP_EVENT_HTTP_TOKEN_POST; - - httpServerEvent.EventData.HttpPostData.Action.Len = httpPostTokenArgs->PostActionLen; - httpServerEvent.EventData.HttpPostData.Action.pData = pPostParams; - pPostParams+=httpPostTokenArgs->PostActionLen; - - httpServerEvent.EventData.HttpPostData.TokenName.Len = httpPostTokenArgs->TokenNameLen; - httpServerEvent.EventData.HttpPostData.TokenName.pData = pPostParams; - pPostParams+=httpPostTokenArgs->TokenNameLen; - - httpServerEvent.EventData.HttpPostData.TokenValue.Len = httpPostTokenArgs->TokenValueLen; - httpServerEvent.EventData.HttpPostData.TokenValue.pData = pPostParams; - - httpServerResponse.Response = SL_NETAPP_HTTPRESPONSE_NONE; - - _SlDrvDispatchHttpServerEvents (&httpServerEvent, &httpServerResponse); -#endif - } - break; - - case SL_OPCODE_NETAPP_REQUEST: - { -#if defined(slcb_NetAppRequestHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) - _u8 *pData; - SlNetAppRequest_t NetAppRequest; - SlNetAppResponse_t NetAppResponse; - _u16 status; - - /* Points to the Netapp request Arguments */ - SlProtocolNetAppRequest_t *protocol_NetAppRequest = (SlProtocolNetAppRequest_t*)_SL_RESP_ARGS_START(pHdr); - - NetAppRequest.AppId = protocol_NetAppRequest->AppId; - NetAppRequest.Type = protocol_NetAppRequest->RequestType; - NetAppRequest.Handle = protocol_NetAppRequest->Handle; - NetAppRequest.requestData.Flags = protocol_NetAppRequest->Flags; - - /* Prepare the Metadata*/ - pData = (_u8 *)((SlProtocolNetAppRequest_t *)protocol_NetAppRequest + 1);/* Points to the netapp request Data (start of Metadata + payload) */ - NetAppRequest.requestData.pMetadata = pData; /* Just pass the pointer */ - NetAppRequest.requestData.MetadataLen = protocol_NetAppRequest->MetadataLen; - - /* Preare the Payload */ - pData+=protocol_NetAppRequest->MetadataLen; - NetAppRequest.requestData.pPayload = pData; /* Just pass the pointer */ - NetAppRequest.requestData.PayloadLen = protocol_NetAppRequest->PayloadLen; - - /* Just in case - clear the response outout data */ - sl_Memset(&NetAppResponse, 0, sizeof (NetAppResponse)); - NetAppResponse.Status = SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; - - /* Call the request handler dispatcher */ - _SlDrvDispatchNetAppRequestEvents (&NetAppRequest, &NetAppResponse); - - /* Handle the response */ - status = _SlNetAppSendResponse(protocol_NetAppRequest->Handle, &NetAppResponse); - -#if (defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_NetAppRequestMemFree)) - if(1 == _SlIsEventRegistered(SL_EVENT_HDL_MEM_FREE)) - { - if ((NetAppResponse.ResponseData.MetadataLen > 0) && (NetAppResponse.ResponseData.pMetadata != NULL)) - { - _SlDrvHandleNetAppRequestMemFreeEvents (NetAppResponse.ResponseData.pMetadata); - } - - if ((NetAppResponse.ResponseData.PayloadLen > 0) && (NetAppResponse.ResponseData.pPayload != NULL)) - { - _SlDrvHandleNetAppRequestMemFreeEvents (NetAppResponse.ResponseData.pPayload); - } - } -#endif - - if (status != 0 ) - { - /* Error - just send resource not found */ - NetAppResponse.Status = SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; - NetAppResponse.ResponseData.pMetadata = NULL; - NetAppResponse.ResponseData.MetadataLen = 0; - NetAppResponse.ResponseData.pPayload = NULL; - NetAppResponse.ResponseData.PayloadLen = 0; - NetAppResponse.ResponseData.Flags = 0; - - /* Handle the response */ - _SlNetAppSendResponse(protocol_NetAppRequest->Handle, &NetAppResponse); - } -#else - - SlNetAppResponse_t NetAppResponse; - - /* Points to the Netapp request Arguments */ - SlProtocolNetAppRequest_t *protocol_NetAppRequest = (SlProtocolNetAppRequest_t *)_SL_RESP_ARGS_START(pHdr); - - /* Prepare the response */ - NetAppResponse.Status = SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; - NetAppResponse.ResponseData.pMetadata = NULL; - NetAppResponse.ResponseData.MetadataLen = 0; - NetAppResponse.ResponseData.pPayload = NULL; - NetAppResponse.ResponseData.PayloadLen = 0; - NetAppResponse.ResponseData.Flags = 0; - - /* Handle the response */ - _SlNetAppSendResponse(protocol_NetAppRequest->Handle, &NetAppResponse); -#endif - - } - break; - - default: - // SL_ERROR_TRACE2(MSG_305, "ASSERT: _SlNetAppEventHandler : invalid opcode = 0x%x = %1", pHdr->GenHeader.Opcode, pHdr->GenHeader.Opcode); - VERIFY_PROTOCOL(0); - } - - return SL_OS_RET_CODE_OK; -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/netcfg.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/netcfg.c deleted file mode 100644 index 702fc0a0038..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/netcfg.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * netcfg.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -/*****************************************************************************/ -/* sl_NetCfgSet */ -/*****************************************************************************/ -typedef union -{ - SlNetCfgSetGet_t Cmd; - _BasicResponse_t Rsp; -}_SlNetCfgMsgSet_u; - -#if _SL_INCLUDE_FUNC(sl_NetCfgSet) - -static const _SlCmdCtrl_t _SlNetCfgSetCmdCtrl = -{ - SL_OPCODE_DEVICE_NETCFG_SET_COMMAND, - (_SlArgSize_t)sizeof(SlNetCfgSetGet_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_NetCfgSet(const _u16 ConfigId,const _u16 ConfigOpt,const _u16 ConfigLen,const _u8 *pValues) -{ - _SlNetCfgMsgSet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETCFG); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = (ConfigLen+3) & (~3); - CmdExt.pTxPayload1 = (_u8 *)pValues; - - Msg.Cmd.ConfigId = ConfigId; - Msg.Cmd.ConfigLen = ConfigLen; - Msg.Cmd.ConfigOpt = ConfigOpt; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetCfgSetCmdCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/*****************************************************************************/ -/* sl_NetCfgGet */ -/*****************************************************************************/ -typedef union -{ - SlNetCfgSetGet_t Cmd; - SlNetCfgSetGet_t Rsp; -}_SlNetCfgMsgGet_u; - -#if _SL_INCLUDE_FUNC(sl_NetCfgGet) - -static const _SlCmdCtrl_t _SlNetCfgGetCmdCtrl = -{ - SL_OPCODE_DEVICE_NETCFG_GET_COMMAND, - (_SlArgSize_t)sizeof(SlNetCfgSetGet_t), - (_SlArgSize_t)sizeof(SlNetCfgSetGet_t) -}; - -_i16 sl_NetCfgGet(const _u16 ConfigId, _u16 *pConfigOpt,_u16 *pConfigLen, _u8 *pValues) -{ - _SlNetCfgMsgGet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_NETCFG); - - if (*pConfigLen == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)(*pConfigLen); - CmdExt.pRxPayload = (_u8 *)pValues; - - _SlDrvMemZero((void*) &Msg, sizeof(Msg)); - - Msg.Cmd.ConfigLen = *pConfigLen; - Msg.Cmd.ConfigId = ConfigId; - - if( pConfigOpt ) - { - Msg.Cmd.ConfigOpt = (_u16)*pConfigOpt; - } - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetCfgGetCmdCtrl, &Msg, &CmdExt)); - - if( pConfigOpt ) - { - *pConfigOpt = (_u8)Msg.Rsp.ConfigOpt; - } - if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *pConfigLen = (_u8)CmdExt.RxPayloadLen; - return SL_ESMALLBUF; - } - else - { - *pConfigLen = (_u8)CmdExt.ActualRxPayloadLen; - } - - return Msg.Rsp.Status; -} -#endif - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/netutil.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/netutil.c deleted file mode 100644 index ff498794080..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/netutil.c +++ /dev/null @@ -1,223 +0,0 @@ -/* - * netutil.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include -#include - -/*****************************************************************************/ -/* Internal functions */ -/*****************************************************************************/ - -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ - - -/****************************************************************************** -sl_UtilsGet -******************************************************************************/ - -typedef union -{ - SlNetUtilSetGet_t Cmd; - SlNetUtilSetGet_t Rsp; -} SlNetUtilMsgGet_u; - -#if _SL_INCLUDE_FUNC(sl_NetUtilGet) - -const _SlCmdCtrl_t _SlNetUtilGetCmdCtrl = -{ - SL_OPCODE_NETUTIL_GET, - sizeof(SlNetUtilSetGet_t), - sizeof(SlNetUtilSetGet_t) -}; - -_i16 sl_NetUtilGet(const _u16 Option, const _u32 ObjID, _u8 *pValues, _u16 *pValueLen) -{ - SlNetUtilMsgGet_u Msg; - _SlCmdExt_t CmdExt; - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = *pValueLen; - CmdExt.pRxPayload = (_u8 *)pValues; - - Msg.Cmd.Option = Option; - Msg.Cmd.ObjId = ObjID; - Msg.Cmd.ValueLen = *pValueLen; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetUtilGetCmdCtrl, &Msg, &CmdExt)); - - if(CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *pValueLen = CmdExt.RxPayloadLen; - return SL_ESMALLBUF; - } - else - { - *pValueLen = CmdExt.ActualRxPayloadLen; - } - - return (_i16)Msg.Rsp.Status; -} -#endif - - -/*************************************************************************** -_SlNetUtilHandleAsync_Cmd - handles NetUtil Cmd response, signalling to -a waiting object -****************************************************************************/ -void _SlNetUtilHandleAsync_Cmd(void *pVoidBuf) -{ - _SlNetUtilCmdData_t *pOutData; - SlNetUtilCmdRsp_t *pMsgArgs = (SlNetUtilCmdRsp_t *)_SL_RESP_ARGS_START(pVoidBuf); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - pOutData = (_SlNetUtilCmdData_t*)g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs; - - pOutData->Status = pMsgArgs->Status; - - if(SL_RET_CODE_OK == pMsgArgs->Status) - { - if (*(pOutData->pOutputLen) < pMsgArgs->OutputLen) - { - pOutData->Status = SL_ESMALLBUF; - } - else - { - *(pOutData->pOutputLen) = pMsgArgs->OutputLen; - - if(*(pOutData->pOutputLen) > 0) - { - /* copy only the data from the global async buffer */ - sl_Memcpy(pOutData->pOutputValues, (char*)pMsgArgs + sizeof(SlNetUtilCmdRsp_t), *(pOutData->pOutputLen)); - } - } - } - - _SlDrvSyncObjSignal(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - _SlDrvProtectionObjUnLock(); - return; -} - - -/***************************************************************************** -sl_NetUtilCmd -******************************************************************************/ -typedef union -{ - SlNetUtilCmd_t Cmd; - _BasicResponse_t Rsp; -} SlNetUtilCmdMsg_u; - -#if _SL_INCLUDE_FUNC(sl_NetUtilCmd) -const _SlCmdCtrl_t _SlNetUtilCmdCtrl = -{ - SL_OPCODE_NETUTIL_COMMAND, - sizeof(SlNetUtilCmd_t), - sizeof(_BasicResponse_t) -}; - -_i16 sl_NetUtilCmd(const _u16 Cmd, const _u8 *pAttrib, const _u16 AttribLen, - const _u8 *pInputValues, const _u16 InputLen, - _u8 *pOutputValues, _u16 *pOutputLen) -{ - _i16 RetVal=0; - SlNetUtilCmdMsg_u Msg; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - _SlCmdExt_t CmdExt; - _SlNetUtilCmdData_t OutData; - - /* prepare the Cmd (control structure and data-buffer) */ - Msg.Cmd.Cmd = Cmd; - Msg.Cmd.AttribLen = AttribLen; - Msg.Cmd.InputLen = InputLen; - Msg.Cmd.OutputLen = *pOutputLen; - - _SlDrvResetCmdExt(&CmdExt); - _SlDrvMemZero(&OutData, sizeof(_SlNetUtilCmdData_t)); - - if(AttribLen > 0) - { - CmdExt.pTxPayload1 = (_u8*)pAttrib; - CmdExt.TxPayload1Len = AttribLen; - } - - if (InputLen > 0) - { - CmdExt.pTxPayload2 = (_u8*)pInputValues; - CmdExt.TxPayload2Len = InputLen; - } - - /* Set the pointers to be filled upon the async event reception */ - OutData.pOutputValues = pOutputValues; - OutData.pOutputLen = pOutputLen; - - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&OutData, NETUTIL_CMD_ID, SL_MAX_SOCKETS); - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - /* send the command */ - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlNetUtilCmdCtrl, &Msg, &CmdExt)); - - if(SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status) - { - /* after the async event is signaled, the data will be copied to the pOutputValues buffer */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, 0, 0)); - - /* the response header status */ - RetVal = OutData.Status; - - } - else - { - RetVal = Msg.Rsp.status; - } - _SlDrvReleasePoolObj((_u8)ObjIdx); - - return RetVal; -} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/nonos.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/nonos.c deleted file mode 100644 index 104522ba8e6..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/nonos.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * nonos.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -#ifndef SL_PLATFORM_MULTI_THREADED - -#include "nonos.h" - -_SlNonOsCB_t g__SlNonOsCB; - -_SlNonOsRetVal_t _SlNonOsSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags) -{ - _i8 i = 0; - - /* The parameter is currently not in use */ - (void)flags; - - - for (i=0 ; iIsAllocated == FALSE) - { - pE->pValue = pValue; - pE->pEntry = pEntry; - pE->IsAllocated = TRUE; - break; - } - } - - return NONOS_RET_OK; -} - -_SlNonOsRetVal_t _SlNonOsHandleSpawnTask(void) -{ - _i8 i=0; - void* pValue; - - for (i=0 ; iIsAllocated == TRUE) - { - _SlSpawnEntryFunc_t pF = pE->pEntry; - pValue = pE->pValue; - - /* Clear the entry */ - pE->pEntry = NULL; - pE->pValue = NULL; - pE->IsAllocated = FALSE; - - /* execute the spawn function */ - pF(pValue); - } - } - return NONOS_RET_OK; -} - -void tiDriverSpawnCallback(void) -{ - /* If we are in cmd context and waiting for its cmd response - * do not handle async events from spawn, as the global lock was already taken when sending the command, - * and the Async event would be handled in read cmd context, so we do nothing. - */ - if (FALSE == g_pCB->WaitForCmdResp) - { - (void)_SlNonOsHandleSpawnTask(); - } -} - -#endif - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/nonos.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/nonos.h deleted file mode 100644 index 1ece7cdbf39..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/nonos.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * nonos.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - -#ifndef __NONOS_H__ -#define __NONOS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef SL_PLATFORM_MULTI_THREADED - -/* This function call the user defined function, if defined, from the sync wait loop */ -/* The use case of this function is to allow nonos system to call a user function to put the device into sleep */ -/* The wake up should be activated after getting an interrupt from the device to Host */ -/* The user function must return without blocking to prevent a delay on the event handling */ -/* -#define _SlSyncWaitLoopCallback UserSleepFunction -*/ - -#define NONOS_MAX_SPAWN_ENTRIES (5) - -#define NONOS_WAIT_FOREVER ~(0UL) -#define NONOS_NO_WAIT (0x0) - -#define NONOS_RET_OK (0) -#define NONOS_RET_ERR (0xFF) -#define OSI_OK (NONOS_RET_OK) - -typedef struct -{ - _SlSpawnEntryFunc_t pEntry; - void* pValue; - _u8 IsAllocated; -}_SlNonOsSpawnEntry_t; - -typedef struct -{ - _SlNonOsSpawnEntry_t SpawnEntries[NONOS_MAX_SPAWN_ENTRIES]; -}_SlNonOsCB_t; - - -/*! - \brief type definition for the return values of this adaptation layer -*/ -typedef _u32 _SlNonOsRetVal_t; - -/*! - \brief type definition for a time value -*/ -typedef _u32 _SlNonOsTime_t; - - -#define _SlTime_t _SlNonOsTime_t - -#define SL_OS_WAIT_FOREVER NONOS_WAIT_FOREVER - -#define SL_OS_RET_CODE_OK NONOS_RET_OK - -#define SL_OS_NO_WAIT NONOS_NO_WAIT - - -/*! - \brief This function call the pEntry callback from a different context - - \param pEntry - pointer to the entry callback function - - \param pValue - pointer to any type of memory structure that would be - passed to pEntry callback from the execution thread. - - \param flags - execution flags - reserved for future usage - - \return upon successful registration of the spawn the function return 0 - (the function is not blocked till the end of the execution of the function - and could be returned before the execution is actually completed) - Otherwise, a negative value indicating the error code shall be returned - \note - \warning -*/ -_SlNonOsRetVal_t _SlNonOsSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags); - - -/*! - \brief This function is called form the main context, while waiting on a sync object. - - \param None - - \return None - - \note - \warning -*/ -void tiDriverSpawnCallback(void); - - -/*! - \brief This function is called directly the main context, while in main task loop. - - \param None - - \return None - - \note - \warning -*/ -_SlNonOsRetVal_t _SlNonOsHandleSpawnTask(void); - -extern _SlNonOsRetVal_t _SlNonOsSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags); - -/***************************************************************************** - - Overwrite SimpleLink driver OS adaptation functions - - *****************************************************************************/ - -#undef sl_Spawn -#define sl_Spawn(pEntry,pValue,flags) _SlNonOsSpawn(pEntry,pValue,flags) - -#undef _SlTaskEntry -#define _SlTaskEntry _SlNonOsHandleSpawnTask - -#endif /* !SL_PLATFORM_MULTI_THREADED */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/objInclusion.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/objInclusion.h deleted file mode 100644 index 5a164970222..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/objInclusion.h +++ /dev/null @@ -1,345 +0,0 @@ -/* - * objInclusion.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -#include - - -#ifndef OBJINCLUSION_H_ -#define OBJINCLUSION_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/****************************************************************************** - - For future use - -*******************************************************************************/ - -#define __inln /* if inline functions requiered: #define __inln inline */ - -#define SL_DEVICE /* Device silo is currently always mandatory */ - - -/****************************************************************************** - - Qualifiers for package customizations - -*******************************************************************************/ - -#if defined (SL_DEVICE) -#define __dev 1 -#else -#define __dev 0 -#endif - -#if defined (SL_DEVICE) && defined (SL_INC_EXT_API) -#define __dev__ext 1 -#else -#define __dev__ext 0 -#endif - - -#if (!defined (SL_PLATFORM_MULTI_THREADED)) || (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) -#define __int__spwn 1 -#else -#define __int__spwn 0 -#endif - -#if defined (SL_INC_NET_APP_PKG) -#define __nap 1 -#else -#define __nap 0 -#endif - -#if defined (SL_INC_NET_APP_PKG) && defined (SL_INC_SOCK_CLIENT_SIDE_API) -#define __nap__clt 1 -#else -#define __nap__clt 0 -#endif - -#if defined (SL_INC_NET_APP_PKG) && defined (SL_INC_EXT_API) -#define __nap__ext 1 -#else -#define __nap__ext 0 -#endif - -#if defined (SL_INC_NET_CFG_PKG) -#define __ncg 1 -#else -#define __ncg 0 -#endif - -#if defined (SL_INC_NET_CFG_PKG) && defined (SL_INC_EXT_API) -#define __ncg__ext 1 -#else -#define __ncg__ext 0 -#endif - -#if defined (SL_INC_NVMEM_PKG) -#define __nvm 1 -#else -#define __nvm 0 -#endif - -#if defined (SL_INC_NVMEM_EXT_PKG) && defined (SL_INC_EXT_API) -#define __nvm__ext 1 -#else -#define __nvm__ext 0 -#endif - -#if defined (SL_INC_SOCKET_PKG) -#define __sck 1 -#else -#define __sck 0 -#endif - -#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_EXT_API) -#define __sck__ext 1 -#else -#define __sck__ext 0 -#endif - -#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_SERVER_SIDE_API) -#define __sck__srv 1 -#else -#define __sck__srv 0 -#endif - -#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_CLIENT_SIDE_API) -#define __sck__clt 1 -#else -#define __sck__clt 0 -#endif - -#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_RECV_API) -#define __sck__rcv 1 -#else -#define __sck__rcv 0 -#endif - -#if defined (SL_INC_SOCKET_PKG) && defined (SL_INC_SOCK_SEND_API) -#define __sck__snd 1 -#else -#define __sck__snd 0 -#endif - -#if defined (SL_INC_WLAN_PKG) -#define __wln 1 -#else -#define __wln 0 -#endif - -#if defined (SL_INC_WLAN_PKG) && defined (SL_INC_EXT_API) -#define __wln__ext 1 -#else -#define __wln__ext 0 -#endif - -/* The return 1 is the function need to be included in the output */ -#define _SL_INCLUDE_FUNC(Name) (_SL_INC_##Name) - -/* Driver */ -#define _SL_INC_sl_NetAppStart __nap__ext -#define _SL_INC_sl_NetAppStop __nap__ext - -#define _SL_INC_sl_NetAppDnsGetHostByName __nap__clt - - -#define _SL_INC_sl_NetAppDnsGetHostByService __nap__ext -#define _SL_INC_sl_NetAppMDNSRegisterService __nap__ext -#define _SL_INC_sl_NetAppMDNSUnRegisterService __nap__ext -#define _SL_INC_sl_NetAppGetServiceList __nap__ext - - -#define _SL_INC_sl_DnsGetHostByAddr __nap__ext -#define _SL_INC_sl_NetAppPing __nap__ext -#define _SL_INC_sl_NetAppSet __nap__ext -#define _SL_INC_sl_NetAppGet __nap__ext -#define _SL_INC_sl_NetAppRecv __nap__ext -#define _SL_INC_sl_NetAppArpFlush __nap__ext -#define _SL_INC_sl_NetAppNdFlush __nap__ext - -#define _SL_INC_sl_NetAppSend __nap__ext - -/* FS */ -#define _SL_INC_sl_FsOpen __nvm - -#define _SL_INC_sl_FsClose __nvm - -#define _SL_INC_sl_FsRead __nvm - -#define _SL_INC_sl_FsWrite __nvm - -#define _SL_INC_sl_FsGetInfo __nvm - -#define _SL_INC_sl_FsDel __nvm - -#define _SL_INC_sl_FsCtl __nvm__ext - -#define _SL_INC_sl_FsProgram __nvm__ext - -#define _SL_INC_sl_FsGetFileList __nvm__ext - -/* netcfg */ -#define _SL_INC_sl_MacAdrrSet __ncg - -#define _SL_INC_sl_MacAdrrGet __ncg - -#define _SL_INC_sl_NetCfgGet __ncg - -#define _SL_INC_sl_NetCfgSet __ncg - -/* socket */ -#define _SL_INC_sl_Socket __sck - -#define _SL_INC_sl_Close __sck - -#define _SL_INC_sl_Accept __sck__srv - -#define _SL_INC_sl_Bind __sck - -#define _SL_INC_sl_Listen __sck__srv - -#define _SL_INC_sl_Connect __sck__clt - -#define _SL_INC_sl_Select __sck - -#define _SL_INC_sl_SetSockOpt __sck - -#define _SL_INC_sl_GetSockOpt __sck__ext - -#define _SL_INC_sl_Recv __sck__rcv - -#define _SL_INC_sl_RecvFrom __sck__rcv - -#define _SL_INC_sl_Write __sck__snd - -#define _SL_INC_sl_Send __sck__snd - -#define _SL_INC_sl_SendTo __sck__snd - -#define _SL_INC_sl_StartTLS __sck - -#define _SL_INC_sl_Htonl __sck - -#define _SL_INC_sl_Htons __sck - -/* wlan */ -#define _SL_INC_sl_WlanConnect __wln__ext - -#define _SL_INC_sl_WlanDisconnect __wln__ext - -#define _SL_INC_sl_WlanProfileAdd __wln__ext - -#define _SL_INC_sl_WlanProfileUpdate __wln__ext - -#define _SL_INC_sl_WlanProfileGet __wln__ext - -#define _SL_INC_sl_WlanProfileDel __wln__ext - -#define _SL_INC_sl_WlanPolicySet __wln__ext - -#define _SL_INC_sl_WlanPolicyGet __wln__ext - -#define _SL_INC_sl_WlanGetNetworkList __wln__ext - -#define _SL_INC_sl_WlanGetExtNetworkList __wln__ext - -#define _SL_INC_sl_WlanRxFilterAdd __wln__ext - -#define _SL_INC_sl_WlanRxFilterSet __wln__ext - -#define _SL_INC_sl_WlanRxFilterGet __wln__ext - -#define _SL_INC_sl_SmartConfigStart __wln - -#define _SL_INC_sl_SmartConfigOptSet __wln__ext - -#define _SL_INC_sl_WlanProvisioning __wln - -#define _SL_INC_sl_WlanSetMode __wln - -#define _SL_INC_sl_WlanSet __wln - -#define _SL_INC_sl_WlanGet __wln - -#define _SL_INC_sl_SmartConfigOptSet __wln__ext - -#define _SL_INC_sl_SmartConfigOptGet __wln__ext - -#define _SL_INC_sl_WlanRxStatStart __wln__ext - -#define _SL_INC_sl_WlanRxStatStop __wln__ext - -#define _SL_INC_sl_WlanRxStatGet __wln__ext - - -/* device */ -#define _SL_INC_sl_Task __int__spwn - -#define _SL_INC_sl_Start __dev - -#define _SL_INC_sl_Stop __dev - -#define _SL_INC_sl_StatusGet __dev - -#ifdef SL_IF_TYPE_UART -#define _SL_INC_sl_DeviceUartSetMode __dev__ext -#endif - -#define _SL_INC_sl_DeviceEventMaskGet __dev__ext - -#define _SL_INC_sl_DeviceEventMaskSet __dev__ext - -#define _SL_INC_sl_DeviceGet __dev__ext - -#define _SL_INC_sl_DeviceSet __dev__ext - -/* netutil */ -#define _SL_INC_sl_NetUtilGet __dev__ext - -#define _SL_INC_sl_NetUtilSet __dev__ext - -#define _SL_INC_sl_NetUtilCmd __dev__ext - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /*OBJINCLUSION_H_ */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/protocol.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/protocol.h deleted file mode 100644 index fb35f9c4ce9..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/protocol.h +++ /dev/null @@ -1,1338 +0,0 @@ -/* - * protocol.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*******************************************************************************\ -* -* FILE NAME: protocol.h -* -* DESCRIPTION: Constant and data structure definitions and function -* prototypes for the SL protocol module, which implements -* processing of SimpleLink Commands. -* -* AUTHOR: -* -\*******************************************************************************/ - -#ifndef _SL_PROTOCOL_TYPES_H_ -#define _SL_PROTOCOL_TYPES_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/**************************************************************************** -** -** User I/F pools definitions -** -****************************************************************************/ - -/**************************************************************************** -** -** Definitions for SimpleLink Commands -** -****************************************************************************/ - - -/* pattern for LE 8/16/32 or BE*/ -#define H2N_SYNC_PATTERN {0xBBDDEEFF,0x4321,0x34,0x12} -#define H2N_CNYS_PATTERN {0xBBDDEEFF,0x8765,0x78,0x56} - -#define H2N_DUMMY_PATTERN (_u32)0xFFFFFFFF -#define N2H_SYNC_PATTERN (_u32)0xABCDDCBA -#define SYNC_PATTERN_LEN (_u32)sizeof(_u32) -#define UART_SET_MODE_MAGIC_CODE (_u32)0xAA55AA55 -#define SPI_16BITS_BUG(pattern) (_u32)((_u32)pattern & (_u32)0xFFFF7FFF) -#define SPI_8BITS_BUG(pattern) (_u32)((_u32)pattern & (_u32)0xFFFFFF7F) - - -typedef struct -{ - _u16 Opcode; - _u16 Len; -}_SlGenericHeader_t; - - -typedef struct -{ - _u32 Long; - _u16 Short; - _u8 Byte1; - _u8 Byte2; -}_SlSyncPattern_t; - -typedef _SlGenericHeader_t _SlCommandHeader_t; - -typedef struct -{ - _SlGenericHeader_t GenHeader; - _u8 TxPoolCnt; - _u8 DevStatus; - _u16 MinMaxPayload; - _u16 SocketTXFailure; - _u16 SocketNonBlocking; -}_SlResponseHeader_t; - -#define _SL_RESP_SPEC_HDR_SIZE (sizeof(_SlResponseHeader_t) - sizeof(_SlGenericHeader_t)) -#define _SL_RESP_HDR_SIZE sizeof(_SlResponseHeader_t) -#define _SL_CMD_HDR_SIZE sizeof(_SlCommandHeader_t) - -#define _SL_RESP_ARGS_START(_pMsg) (((_SlResponseHeader_t *)(_pMsg)) + 1) - -/* Used only in NWP! */ -typedef struct -{ - _SlCommandHeader_t sl_hdr; - _u8 func_args_start; -} T_SCMD; - -/* _SlResponseHeader_t DevStatus bits */ -#define _SL_DEV_STATUS_BIT_WLAN_CONN 0x01 -#define _SL_DEV_STATUS_BIT_DROPPED_EVENTS 0x02 -#define _SL_DEV_STATUS_BIT_LOCKED 0x04 -#define _SL_DEV_STATUS_BIT_PROVISIONING_ACTIVE 0x08 -#define _SL_DEV_STATUS_BIT_PROVISIONING_USER_INITIATED 0x10 -#define _SL_DEV_STATUS_BIT_PRESERVATION 0x20 -#define _SL_DEV_STATUS_BIT_PROVISIONING_ENABLE_API 0x40 - - -/* Internal driver bits status (g_SlDeviceStatus) */ -#define _SL_DRV_STATUS_BIT_RESTART_REQUIRED 0x100 -#define _SL_DRV_STATUS_BIT_DEVICE_STARTED 0x200 -#define _SL_DRV_STATUS_BIT_STOP_IN_PROGRESS 0x400 -#define _SL_DRV_STATUS_BIT_START_IN_PROGRESS 0x800 -#define _SL_DRV_STATUS_BIT_GLOBAL_LOCK_INIT 0x1000 -/**************************************************************************** -** OPCODES -****************************************************************************/ -#define SL_IPV4_IPV6_OFFSET ( 9 ) -#define SL_OPCODE_IPV4 ( 0x0 << SL_IPV4_IPV6_OFFSET ) -#define SL_OPCODE_IPV6 ( 0x1 << SL_IPV4_IPV6_OFFSET ) - -#define SL_SYNC_ASYNC_OFFSET ( 10 ) -#define SL_OPCODE_SYNC (0x1 << SL_SYNC_ASYNC_OFFSET ) -#define SL_OPCODE_SILO_OFFSET ( 11 ) -#define SL_OPCODE_SILO_MASK ( 0xF << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_DEVICE ( 0x0 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_WLAN ( 0x1 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_SOCKET ( 0x2 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_NETAPP ( 0x3 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_FS ( 0x4 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_NETCFG ( 0x5 << SL_OPCODE_SILO_OFFSET ) -#define SL_OPCODE_SILO_NETUTIL ( 0x6 << SL_OPCODE_SILO_OFFSET ) - -#define SL_FAMILY_SHIFT (0x4) -#define SL_FLAGS_MASK (0xF) - -#define SL_OPCODE_DEVICE_INITCOMPLETE 0x0008 -#define SL_OPCODE_DEVICE_ABORT 0x000C -#define SL_OPCODE_DEVICE_STOP_COMMAND 0x8473 -#define SL_OPCODE_DEVICE_STOP_RESPONSE 0x0473 -#define SL_OPCODE_DEVICE_STOP_ASYNC_RESPONSE 0x0073 -#define SL_OPCODE_DEVICE_DEVICEASYNCDUMMY 0x0063 - -#define SL_OPCODE_DEVICE_VERSIONREADCOMMAND 0x8470 -#define SL_OPCODE_DEVICE_VERSIONREADRESPONSE 0x0470 -#define SL_OPCODE_DEVICE_DEVICE_ASYNC_GENERAL_ERROR 0x0078 -#define SL_OPCODE_DEVICE_FLOW_CTRL_ASYNC_EVENT 0x0079 - -#define SL_OPCODE_WLAN_WLANCONNECTCOMMAND 0x8C80 -#define SL_OPCODE_WLAN_WLANCONNECTRESPONSE 0x0C80 -#define SL_OPCODE_WLAN_STA_ASYNCCONNECTEDRESPONSE 0x0880 -#define SL_OPCODE_WLAN_P2PCL_ASYNCCONNECTEDRESPONSE 0x0892 - -#define SL_OPCODE_WLAN_WLANDISCONNECTCOMMAND 0x8C81 -#define SL_OPCODE_WLAN_WLANDISCONNECTRESPONSE 0x0C81 -#define SL_OPCODE_WLAN_STA_ASYNCDISCONNECTEDRESPONSE 0x0881 -#define SL_OPCODE_WLAN_P2PCL_ASYNCDISCONNECTEDRESPONSE 0x0894 - -#define SL_OPCODE_WLAN_ASYNC_STA_ADDED 0x082E -#define SL_OPCODE_WLAN_ASYNC_P2PCL_ADDED 0x0896 -#define SL_OPCODE_WLAN_ASYNC_STA_REMOVED 0x082F -#define SL_OPCODE_WLAN_ASYNC_P2PCL_REMOVED 0x0898 - -#define SL_OPCODE_WLAN_P2P_DEV_FOUND 0x0830 -#define SL_OPCODE_WLAN_P2P_CONNECTION_FAILED 0x0831 -#define SL_OPCODE_WLAN_P2P_NEG_REQ_RECEIVED 0x0832 - -#define SL_OPCODE_WLAN_WLANCONNECTEAPCOMMAND 0x8C82 -#define SL_OPCODE_WLAN_WLANCONNECTEAPCRESPONSE 0x0C82 -#define SL_OPCODE_WLAN_PROFILEADDCOMMAND 0x8C83 -#define SL_OPCODE_WLAN_PROFILEADDRESPONSE 0x0C83 -#define SL_OPCODE_WLAN_PROFILEUPDATECOMMAND 0x8CC2 -#define SL_OPCODE_WLAN_PROFILEUPDATERESPONSE 0x0CC2 -#define SL_OPCODE_WLAN_PROFILEEAPUPDATECOMMAND 0x8CC3 -#define SL_OPCODE_WLAN_PROFILEEAPUPDATERESPONSE 0x0CC0 -#define SL_OPCODE_WLAN_PROFILEGETCOMMAND 0x8C84 -#define SL_OPCODE_WLAN_PROFILEGETRESPONSE 0x0C84 -#define SL_OPCODE_WLAN_PROFILEDELCOMMAND 0x8C85 -#define SL_OPCODE_WLAN_PROFILEDELRESPONSE 0x0C85 -#define SL_OPCODE_WLAN_POLICYSETCOMMAND 0x8C86 -#define SL_OPCODE_WLAN_POLICYSETRESPONSE 0x0C86 -#define SL_OPCODE_WLAN_POLICYGETCOMMAND 0x8C87 -#define SL_OPCODE_WLAN_POLICYGETRESPONSE 0x0C87 -#define SL_OPCODE_WLAN_FILTERADD 0x8C88 -#define SL_OPCODE_WLAN_FILTERADDRESPONSE 0x0C88 -#define SL_OPCODE_WLAN_FILTERGET 0x8C89 -#define SL_OPCODE_WLAN_FILTERGETRESPONSE 0x0C89 -#define SL_OPCODE_WLAN_FILTERDELETE 0x8C8A -#define SL_OPCODE_WLAN_FILTERDELETERESPOSNE 0x0C8A -#define SL_OPCODE_WLAN_WLANGETSTATUSCOMMAND 0x8C8F -#define SL_OPCODE_WLAN_WLANGETSTATUSRESPONSE 0x0C8F -#define SL_OPCODE_WLAN_STARTTXCONTINUESCOMMAND 0x8CAA -#define SL_OPCODE_WLAN_STARTTXCONTINUESRESPONSE 0x0CAA -#define SL_OPCODE_WLAN_STOPTXCONTINUESCOMMAND 0x8CAB -#define SL_OPCODE_WLAN_STOPTXCONTINUESRESPONSE 0x0CAB -#define SL_OPCODE_WLAN_STARTRXSTATCOMMAND 0x8CAC -#define SL_OPCODE_WLAN_STARTRXSTATRESPONSE 0x0CAC -#define SL_OPCODE_WLAN_STOPRXSTATCOMMAND 0x8CAD -#define SL_OPCODE_WLAN_STOPRXSTATRESPONSE 0x0CAD -#define SL_OPCODE_WLAN_GETRXSTATCOMMAND 0x8CAF -#define SL_OPCODE_WLAN_GETRXSTATRESPONSE 0x0CAF -#define SL_OPCODE_WLAN_POLICYSETCOMMANDNEW 0x8CB0 -#define SL_OPCODE_WLAN_POLICYSETRESPONSENEW 0x0CB0 -#define SL_OPCODE_WLAN_POLICYGETCOMMANDNEW 0x8CB1 -#define SL_OPCODE_WLAN_POLICYGETRESPONSENEW 0x0CB1 - -#define SL_OPCODE_WLAN_PROVISIONING_PROFILE_ADDED_ASYNC_RESPONSE 0x08B2 -#define SL_OPCODE_WLAN_SET_MODE 0x8CB4 -#define SL_OPCODE_WLAN_SET_MODE_RESPONSE 0x0CB4 -#define SL_OPCODE_WLAN_CFG_SET 0x8CB5 -#define SL_OPCODE_WLAN_CFG_SET_RESPONSE 0x0CB5 -#define SL_OPCODE_WLAN_CFG_GET 0x8CB6 -#define SL_OPCODE_WLAN_CFG_GET_RESPONSE 0x0CB6 -#define SL_OPCODE_WLAN_EAP_PROFILEADDCOMMAND 0x8C67 -#define SL_OPCODE_WLAN_EAP_PROFILEADDCOMMAND_RESPONSE 0x0C67 -#define SL_OPCODE_WLAN_LINK_QUALITY_RESPONSE 0x08BA - -#define SL_OPCODE_SOCKET_SOCKET 0x9401 -#define SL_OPCODE_SOCKET_SOCKETRESPONSE 0x1401 -#define SL_OPCODE_SOCKET_CLOSE 0x9402 -#define SL_OPCODE_SOCKET_CLOSERESPONSE 0x1402 -#define SL_OPCODE_SOCKET_ACCEPT 0x9403 -#define SL_OPCODE_SOCKET_ACCEPTRESPONSE 0x1403 -#define SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE 0x1003 -#define SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE_V6 0x1203 -#define SL_OPCODE_SOCKET_BIND 0x9404 -#define SL_OPCODE_SOCKET_BIND_V6 0x9604 -#define SL_OPCODE_SOCKET_BINDRESPONSE 0x1404 -#define SL_OPCODE_SOCKET_LISTEN 0x9405 -#define SL_OPCODE_SOCKET_LISTENRESPONSE 0x1405 -#define SL_OPCODE_SOCKET_CONNECT 0x9406 -#define SL_OPCODE_SOCKET_CONNECT_V6 0x9606 -#define SL_OPCODE_SOCKET_CONNECTRESPONSE 0x1406 -#define SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE 0x1006 -#define SL_OPCODE_SOCKET_SELECT 0x9407 -#define SL_OPCODE_SOCKET_SELECTRESPONSE 0x1407 -#define SL_OPCODE_SOCKET_SELECTASYNCRESPONSE 0x1007 -#define SL_OPCODE_SOCKET_SETSOCKOPT 0x9408 -#define SL_OPCODE_SOCKET_SETSOCKOPTRESPONSE 0x1408 -#define SL_OPCODE_SOCKET_GETSOCKOPT 0x9409 -#define SL_OPCODE_SOCKET_GETSOCKOPTRESPONSE 0x1409 -#define SL_OPCODE_SOCKET_RECV 0x940A -#define SL_OPCODE_SOCKET_RECVASYNCRESPONSE 0x100A -#define SL_OPCODE_SOCKET_RECVFROM 0x940B -#define SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE 0x100B -#define SL_OPCODE_SOCKET_RECVFROMASYNCRESPONSE_V6 0x120B -#define SL_OPCODE_SOCKET_SEND 0x940C -#define SL_OPCODE_SOCKET_SENDTO 0x940D -#define SL_OPCODE_SOCKET_SENDTO_V6 0x960D -#define SL_OPCODE_SOCKET_TXFAILEDASYNCRESPONSE 0x100E -#define SL_OPCODE_SOCKET_SOCKETASYNCEVENT 0x100F -#define SL_OPCODE_SOCKET_SOCKETCLOSEASYNCEVENT 0x1010 -#define SL_OPCODE_NETAPP_START_COMMAND 0x9C0A -#define SL_OPCODE_NETAPP_START_RESPONSE 0x1C0A -#define SL_OPCODE_NETAPP_NETAPPSTARTRESPONSE 0x1C0A -#define SL_OPCODE_NETAPP_STOP_COMMAND 0x9C61 -#define SL_OPCODE_NETAPP_STOP_RESPONSE 0x1C61 -#define SL_OPCODE_NETAPP_NETAPPSET 0x9C0B -#define SL_OPCODE_NETAPP_NETAPPSETRESPONSE 0x1C0B -#define SL_OPCODE_NETAPP_NETAPPGET 0x9C27 -#define SL_OPCODE_NETAPP_NETAPPGETRESPONSE 0x1C27 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAME 0x9C20 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAMERESPONSE 0x1C20 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE 0x1820 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYNAMEASYNCRESPONSE_V6 0x1A20 -#define SL_OPCODE_NETAPP_NETAPP_MDNS_LOOKUP_SERVICE 0x9C71 -#define SL_OPCODE_NETAPP_NETAPP_MDNS_LOOKUP_SERVICE_RESPONSE 0x1C72 -#define SL_OPCODE_NETAPP_MDNSREGISTERSERVICE 0x9C34 -#define SL_OPCODE_NETAPP_MDNSREGISTERSERVICERESPONSE 0x1C34 -#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICE 0x9C35 -#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICERESPONSE 0x1C35 -#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE 0x1835 -#define SL_OPCODE_NETAPP_MDNSGETHOSTBYSERVICEASYNCRESPONSE_V6 0x1A35 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDR 0x9C26 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDR_V6 0x9E26 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDRRESPONSE 0x1C26 -#define SL_OPCODE_NETAPP_DNSGETHOSTBYADDRASYNCRESPONSE 0x1826 -#define SL_OPCODE_NETAPP_PINGSTART 0x9C21 -#define SL_OPCODE_NETAPP_PINGSTART_V6 0x9E21 -#define SL_OPCODE_NETAPP_PINGSTARTRESPONSE 0x1C21 -#define SL_OPCODE_NETAPP_PINGREPORTREQUEST 0x9C22 -#define SL_OPCODE_NETAPP_PINGREPORTREQUESTRESPONSE 0x1822 -#define SL_OPCODE_NETAPP_ARPFLUSH 0x9C24 -#define SL_OPCODE_NETAPP_ARPFLUSHRESPONSE 0x1C24 -#define SL_OPCODE_NETAPP_NDFLUSH_V6 0x9EC2 -#define SL_OPCODE_NETAPP_NDFLUSHHRESPONSE_V6 0x1EC3 -#define SL_OPCODE_NETAPP_IPACQUIRED 0x1825 -#define SL_OPCODE_NETAPP_IPV4_LOST 0x1832 -#define SL_OPCODE_NETAPP_DHCP_IPV4_ACQUIRE_TIMEOUT 0x1833 -#define SL_OPCODE_LINK_QUALITY_EVENT 0x1834 -#define SL_OPCODE_NETAPP_IPACQUIRED_V6 0x1A25 -#define SL_OPCODE_NETAPP_IPV6_LOST_V6 0x1A32 -#define SL_OPCODE_NETAPP_IPERFSTARTCOMMAND 0x9C28 -#define SL_OPCODE_NETAPP_IPERFSTARTRESPONSE 0x1C28 -#define SL_OPCODE_NETAPP_IPERFSTOPCOMMAND 0x9C29 -#define SL_OPCODE_NETAPP_IPERFSTOPRESPONSE 0x1C29 -#define SL_OPCODE_NETAPP_CTESTSTARTCOMMAND 0x9C2A -#define SL_OPCODE_NETAPP_CTESTSTARTRESPONSE 0x1C2A -#define SL_OPCODE_NETAPP_CTESTASYNCRESPONSE 0x182A -#define SL_OPCODE_NETAPP_CTESTSTOPCOMMAND 0x9C2B -#define SL_OPCODE_NETAPP_CTESTSTOPRESPONSE 0x1C2B -#define SL_OPCODE_NETAPP_IP_LEASED 0x182C -#define SL_OPCODE_NETAPP_IP_RELEASED 0x182D -#define SL_OPCODE_NETAPP_HTTPGETTOKENVALUE 0x182E -#define SL_OPCODE_NETAPP_HTTPSENDTOKENVALUE 0x9C2F -#define SL_OPCODE_NETAPP_HTTPPOSTTOKENVALUE 0x1830 -#define SL_OPCODE_NETAPP_IP_COLLISION 0x1831 -#define SL_OPCODE_NETAPP_NO_IP_COLLISION_DETECTED 0x18C4 -#define SL_OPCODE_NETAPP_NO_LOCAL_IP_COLLISION_DETECTED_V6 0x1AC5 -#define SL_OPCODE_NETAPP_NO_GLOBAL_IP_COLLISION_DETECTED_V6 0x1AC6 - -#define SL_OPCODE_NETAPP_REQUEST 0x1878 -#define SL_OPCODE_NETAPP_RESPONSE 0x9C78 -#define SL_OPCODE_NETAPP_SEND 0x9C79 -#define SL_OPCODE_NETAPP_SENDRESPONSE 0x1C79 -#define SL_OPCODE_NETAPP_RECEIVEREQUEST 0x9C7A -#define SL_OPCODE_NETAPP_RECEIVE 0x187B - -#define SL_OPCODE_NVMEM_FILEOPEN 0xA43C -#define SL_OPCODE_NVMEM_FILEOPENRESPONSE 0x243C -#define SL_OPCODE_NVMEM_FILECLOSE 0xA43D -#define SL_OPCODE_NVMEM_FILECLOSERESPONSE 0x243D -#define SL_OPCODE_NVMEM_FILEREADCOMMAND 0xA440 -#define SL_OPCODE_NVMEM_FILEREADRESPONSE 0x2440 -#define SL_OPCODE_NVMEM_FILEWRITECOMMAND 0xA441 -#define SL_OPCODE_NVMEM_FILEWRITERESPONSE 0x2441 -#define SL_OPCODE_NVMEM_FILEGETINFOCOMMAND 0xA442 -#define SL_OPCODE_NVMEM_FILEGETINFORESPONSE 0x2442 -#define SL_OPCODE_NVMEM_FILEDELCOMMAND 0xA443 -#define SL_OPCODE_NVMEM_FILEDELRESPONSE 0x2443 -#define SL_OPCODE_NVMEM_NVMEMFORMATCOMMAND 0xA444 -#define SL_OPCODE_NVMEM_NVMEMFORMATRESPONSE 0x2444 -#define SL_OPCODE_NVMEM_NVMEMGETFILELISTCOMMAND 0xA448 -#define SL_OPCODE_NVMEM_NVMEMGETFILELISTRESPONSE 0x2448 - -#define SL_OPCODE_NVMEM_NVMEMFSPROGRAMMINGCOMMAND 0xA44A -#define SL_OPCODE_NVMEM_NVMEMFSPROGRAMMINGRESPONSE 0x244A -#define SL_OPCODE_NVMEM_NVMEMFILESYSTEMCONTROLCOMMAND 0xA44B -#define SL_OPCODE_NVMEM_NVMEMFILESYSTEMCONTROLRESPONSE 0x244B -#define SL_OPCODE_NVMEM_NVMEMBUNDLECONTROLCOMMAND 0xA44C -#define SL_OPCODE_NVMEM_NVMEMBUNDLECONTROLRESPONSE 0x244C - - -#define SL_OPCODE_DEVICE_SETDEBUGLEVELCOMMAND 0x846A -#define SL_OPCODE_DEVICE_SETDEBUGLEVELRESPONSE 0x046A - -#define SL_OPCODE_DEVICE_NETCFG_SET_COMMAND 0x8432 -#define SL_OPCODE_DEVICE_NETCFG_SET_RESPONSE 0x0432 -#define SL_OPCODE_DEVICE_NETCFG_GET_COMMAND 0x8433 -#define SL_OPCODE_DEVICE_NETCFG_GET_RESPONSE 0x0433 -/* */ -#define SL_OPCODE_DEVICE_SETUARTMODECOMMAND 0x846B -#define SL_OPCODE_DEVICE_SETUARTMODERESPONSE 0x046B -#define SL_OPCODE_DEVICE_SSISIZESETCOMMAND 0x846B -#define SL_OPCODE_DEVICE_SSISIZESETRESPONSE 0x046B - -/* */ -#define SL_OPCODE_DEVICE_EVENTMASKSET 0x8464 -#define SL_OPCODE_DEVICE_EVENTMASKSETRESPONSE 0x0464 -#define SL_OPCODE_DEVICE_EVENTMASKGET 0x8465 -#define SL_OPCODE_DEVICE_EVENTMASKGETRESPONSE 0x0465 - -#define SL_OPCODE_DEVICE_DEVICEGET 0x8466 -#define SL_OPCODE_DEVICE_DEVICEGETRESPONSE 0x0466 -#define SL_OPCODE_DEVICE_DEVICESET 0x84B7 -#define SL_OPCODE_DEVICE_DEVICESETRESPONSE 0x04B7 - -#define SL_OPCODE_WLAN_SCANRESULTSGETCOMMAND 0x8C8C -#define SL_OPCODE_WLAN_SCANRESULTSGETRESPONSE 0x0C8C -#define SL_OPCODE_WLAN_EXTSCANRESULTSGETCOMMAND 0x8C8D -#define SL_OPCODE_WLAN_EXTSCANRESULTSGETRESPONSE 0x0C8D -#define SL_OPCODE_WLAN_SMARTCONFIGOPTGET 0x8C8E -#define SL_OPCODE_WLAN_SMARTCONFIGOPTGETRESPONSE 0x0C8E - -#define SL_OPCODE_WLAN_PROVISIONING_COMMAND 0x8C98 -#define SL_OPCODE_WLAN_PROVISIONING_RESPONSE 0x0C98 -#define SL_OPCODE_DEVICE_RESET_REQUEST_ASYNC_EVENT 0x0099 -#define SL_OPCODE_WLAN_PROVISIONING_STATUS_ASYNC_EVENT 0x089A - -#define SL_OPCODE_FREE_BSD_RECV_BUFFER 0xCCCB -#define SL_OPCODE_FREE_NON_BSD_READ_BUFFER 0xCCCD - - -/* Rx Filters opcodes */ -#define SL_OPCODE_WLAN_WLANRXFILTERADDCOMMAND 0x8C6C -#define SL_OPCODE_WLAN_WLANRXFILTERADDRESPONSE 0x0C6C -#define SL_OPCODE_WLAN_WLANRXFILTERGETSTATISTICSINFOCOMMAND 0x8C6E -#define SL_OPCODE_WLAN_WLANRXFILTERGETSTATISTICSINFORESPONSE 0x0C6E -#define SL_OPCODE_WLAN_WLANRXFILTERGETINFO 0x8C70 -#define SL_OPCODE_WLAN_WLANRXFILTERGETINFORESPONSE 0x0C70 -#define SL_OPCODE_WLAN_RX_FILTER_ASYNC_RESPONSE 0x089D - -/* Utils */ -#define SL_OPCODE_NETUTIL_SET 0xB4BE -#define SL_OPCODE_NETUTIL_SETRESPONSE 0x34BE -#define SL_OPCODE_NETUTIL_GET 0xB4C0 -#define SL_OPCODE_NETUTIL_GETRESPONSE 0x34C0 -#define SL_OPCODE_NETUTIL_COMMAND 0xB4C1 -#define SL_OPCODE_NETUTIL_COMMANDRESPONSE 0x34C1 -#define SL_OPCODE_NETUTIL_COMMANDASYNCRESPONSE 0x30C1 - -/******************************************************************************************/ -/* Device structs */ -/******************************************************************************************/ -typedef _u32 InitStatus_t; - -typedef struct -{ - _i32 Status; - _i32 ChipId; - _i32 MoreData; -}InitComplete_t; - -typedef struct -{ - _i16 status; - _u16 sender; -}_BasicResponse_t; - -typedef struct -{ - _u32 SessionNumber; - _u16 Caller; - _u16 Padding; -}SlDeviceResetRequestData_t; - -typedef struct -{ - _u16 Timeout; - _u16 Padding; -}SlDeviceStopCommand_t; - -typedef struct -{ - _u32 Group; - _u32 Mask; -}SlDeviceMaskEventSetCommand_t; - -typedef _BasicResponse_t _DevMaskEventSetResponse_t; - -typedef struct -{ - _u32 Group; -} SlDeviceMaskEventGetCommand_t; - -typedef struct -{ - _u32 Group; - _u32 Mask; -} SlDeviceMaskEventGetResponse_t; - -typedef struct -{ - _u32 Group; -} SlDeviceStatusGetCommand_t; - -typedef struct -{ - _u32 Group; - _u32 Status; -} SlDeviceStatusGetResponse_t; - -typedef struct -{ - _u32 ChipId; - _u32 FwVersion[4]; - _u8 PhyVersion[4]; -} SlDeviceVersionReadResponsePart_t; - -typedef struct -{ - SlDeviceVersionReadResponsePart_t part; - _u32 NwpVersion[4]; - _u16 RomVersion; - _u16 Padding; -} SlDeviceVersionReadResponseFull_t; - -typedef struct -{ - _u16 MinTxPayloadSize; - _u8 padding[6]; -} SlDeviceFlowCtrlAsyncEvent_t; - -typedef struct -{ - _u32 BaudRate; - _u8 FlowControlEnable; -} SlDeviceUartSetModeCommand_t; - -typedef _BasicResponse_t SlDeviceUartSetModeResponse_t; - -/******************************************************/ - -typedef struct -{ - _u8 SsiSizeInBytes; - _u8 Padding[3]; -}_StellarisSsiSizeSet_t; - -/*****************************************************************************************/ -/* WLAN structs */ -/*****************************************************************************************/ -#define MAXIMAL_PASSWORD_LENGTH (64) - -typedef struct -{ - _u8 ProvisioningCmd; - _u8 RequestedRoleAfterSuccess; - _u16 InactivityTimeoutSec; - _u32 Flags; -} SlWlanProvisioningParams_t; - -typedef struct{ - _u8 SecType; - _u8 SsidLen; - _u8 Bssid[6]; - _u8 PasswordLen; -} SlWlanConnectCommon_t; - -#define SSID_STRING(pCmd) (_i8 *)((SlWlanConnectCommon_t *)(pCmd) + 1) -#define PASSWORD_STRING(pCmd) (SSID_STRING(pCmd) + ((SlWlanConnectCommon_t *)(pCmd))->SsidLen) - -typedef struct{ - SlWlanConnectCommon_t Common; - _u8 UserLen; - _u8 AnonUserLen; - _u8 CertIndex; - _u32 EapBitmask; -} SlWlanConnectEapCommand_t; - -#define EAP_SSID_STRING(pCmd) (_i8 *)((SlWlanConnectEapCommand_t *)(pCmd) + 1) -#define EAP_PASSWORD_STRING(pCmd) (EAP_SSID_STRING(pCmd) + ((SlWlanConnectEapCommand_t *)(pCmd))->Common.SsidLen) -#define EAP_USER_STRING(pCmd) (EAP_PASSWORD_STRING(pCmd) + ((SlWlanConnectEapCommand_t *)(pCmd))->Common.PasswordLen) -#define EAP_ANON_USER_STRING(pCmd) (EAP_USER_STRING(pCmd) + ((SlWlanConnectEapCommand_t *)(pCmd))->UserLen) - -typedef struct -{ - _u8 PolicyType; - _u8 Padding; - _u8 PolicyOption; - _u8 PolicyOptionLen; -} SlWlanPolicySetGet_t; - -typedef struct{ - _u32 MinDwellTime; - _u32 MaxDwellTime; - _u32 NumProbeResponse; - _u32 G_Channels_mask; - _i32 RssiThershold; - _i32 SnrThershold; - _i32 DefaultTXPower; - _u16 IntervalList[16]; -} SlWlanScanParamSetCommand_t; - -typedef struct{ - _i16 SecType; - _u8 SsidLen; - _u8 Priority; - _u8 Bssid[6]; - _u8 PasswordLen; - _u8 WepKeyId; -} SlWlanAddGetProfile_t; - -typedef struct{ - SlWlanAddGetProfile_t Common; - _u8 UserLen; - _u8 AnonUserLen; - _u8 CertIndex; - _u8 padding; - _u32 EapBitmask; -} SlWlanAddGetEapProfile_t; - - -typedef struct{ - _i16 SecType; - _u8 SsidLen; - _u8 Priority; - _u8 Bssid[6]; - _u8 PasswordLen; - _u8 WepKeyId; - _u32 Index; - _u8 UserLen; - _u8 AnonUserLen; - _u8 CertIndex; - _u8 padding; - _u32 EapBitmask; -} SlWlanUpdateProfile_t; - -#define PROFILE_SSID_STRING(pCmd) ((_i8 *)((SlWlanAddGetProfile_t *)(pCmd) + 1)) -#define PROFILE_PASSWORD_STRING(pCmd) (PROFILE_SSID_STRING(pCmd) + ((SlWlanAddGetProfile_t *)(pCmd))->SsidLen) - -#define EAP_PROFILE_SSID_STRING(pCmd) (_i8 *)((SlWlanAddGetEapProfile_t *)(pCmd) + 1) -#define EAP_PROFILE_PASSWORD_STRING(pCmd) (EAP_PROFILE_SSID_STRING(pCmd) + ((SlWlanAddGetEapProfile_t *)(pCmd))->Common.SsidLen) -#define EAP_PROFILE_USER_STRING(pCmd) (EAP_PROFILE_PASSWORD_STRING(pCmd) + ((SlWlanAddGetEapProfile_t *)(pCmd))->Common.PasswordLen) -#define EAP_PROFILE_ANON_USER_STRING(pCmd) (EAP_PROFILE_USER_STRING(pCmd) + ((SlWlanAddGetEapProfile_t *)(pCmd))->UserLen) - -#define PROFILE_SSID_STRING(pCmd) ((_i8 *)((SlWlanAddGetProfile_t *)(pCmd) + 1)) -#define PROFILE_PASSWORD_STRING(pCmd) (PROFILE_SSID_STRING(pCmd) + ((SlWlanAddGetProfile_t *)(pCmd))->SsidLen) - -#define UPDATE_PROFILE_SSID_STRING(pCmd) (_i8 *)((SlWlanUpdateProfile_t *)(pCmd) + 1) -#define UPDATE_PROFILE_PASSWORD_STRING(pCmd) (UPDATE_PROFILE_SSID_STRING(pCmd) + ((SlWlanUpdateProfile_t *)(pCmd))->SsidLen) -#define UPDATE_PROFILE_USER_STRING(pCmd) (UPDATE_PROFILE_PASSWORD_STRING(pCmd) + ((SlWlanUpdateProfile_t *)(pCmd))->PasswordLen) -#define UPDATE_PROFILE_ANON_USER_STRING(pCmd) (UPDATE_PROFILE_USER_STRING(pCmd) + ((SlWlanUpdateProfile_t *)(pCmd))->UserLen) - - -typedef struct -{ - _u8 Index; - _u8 Padding[3]; -} SlWlanProfileDelGetCommand_t; - -typedef _BasicResponse_t _WlanGetNetworkListResponse_t; - -typedef struct -{ - _u8 Index; - _u8 Count; - _i8 padding[2]; -} SlWlanGetNetworkListCommand_t; - -typedef _BasicResponse_t _WlanGetExtNetworkListResponse_t; - -typedef struct -{ - _u8 Index; - _u8 Count; - _i8 padding[2]; -} SlWlanGetExtNetworkListCommand_t; - -typedef struct -{ - _u32 GroupIdBitmask; - _u8 Cipher; - _u8 PublicKeyLen; - _u8 Padding[2]; -} SlWlanSmartConfigParams_t; - -#define SMART_CONFIG_START_PUBLIC_KEY_STRING(pCmd) ((_i8 *)((SlWlanSmartConfigParams_t *)(pCmd) + 1)) - -typedef struct -{ - _u8 Mode; - _u8 Padding[3]; -} SlWlanSetMode_t; - -typedef struct -{ - _u16 Status; - _u16 ConfigId; - _u16 ConfigOpt; - _u16 ConfigLen; -} SlWlanCfgSetGet_t; - - -/* ******************************************************************************/ -/* RX filters - Start */ -/* ******************************************************************************/ - -typedef struct -{ - SlWlanRxFilterRuleType_t RuleType; - SlWlanRxFilterFlags_u Flags; - SlWlanRxFilterID_t FilterId; - _u8 Padding; - SlWlanRxFilterRule_u Rule; - SlWlanRxFilterTrigger_t Trigger; - SlWlanRxFilterAction_t Action; -} SlWlanRxFilterAddCommand_t; - -typedef struct -{ - SlWlanRxFilterID_t FilterId; - _i16 Status; - _u8 Padding[1]; -} SlWlanRxFilterAddCommandReponse_t; - -typedef struct -{ - _i16 Status; - _u8 Padding[2]; -} SlWlanRxFilterSetCommandReponse_t; - -typedef struct -{ - _i16 Status; - _u16 OutputBufferLength; - -} SlWlanRxFilterGetCommandReponse_t; - - -/* ******************************************************************************/ -/* RX filters -- End */ -/* ******************************************************************************/ - -typedef struct -{ - _u16 Status; - _u8 WlanRole; /* 0 = station, 2 = AP */ - _u8 Ipv6Enabled; - _u8 DhcpEnabled; - - _u32 Global[4]; - _u32 Local[4]; - _u32 DnsServer[4]; - _u8 DhcpState; -} SlNetappIpV6configRetArgs_t; - -typedef struct -{ - _u8 Ip[4]; - _u8 IpMask[4]; - _u8 IpGateway[4]; - _u8 IpDnsServer[4]; - _u8 IpStart[4]; - _u8 IpEnd[4]; -} SlNetCfgIpV4APArgs_t; - -typedef struct -{ - _u16 Status; - _u8 MacAddr[6]; -} SlMacAddressSetGet_t; - -typedef struct -{ - _u16 Status; - _u16 ConfigId; - _u16 ConfigOpt; - _u16 ConfigLen; -} SlNetCfgSetGet_t; - -typedef struct -{ - _u16 Status; - _u16 DeviceSetId; - _u16 Option; - _u16 ConfigLen; -} SlDeviceSetGet_t; - - -/******************************************************************************************/ -/* Socket structs */ -/******************************************************************************************/ - -typedef struct -{ - _u8 Domain; - _u8 Type; - _u8 Protocol; - _u8 Padding; -} SlSocketCommand_t; - -typedef struct -{ - _i16 StatusOrLen; - _u8 Sd; - _u8 Padding; -} SlSocketResponse_t; - -typedef struct -{ - _u8 Sd; - _u8 Family; - _u8 Padding1; - _u8 Padding2; -} SlAcceptCommand_t; - -typedef struct -{ - _i16 StatusOrLen; - _u8 Sd; - _u8 Family; - _u16 Port; - _u16 PaddingOrAddr; - _u32 Address; -} SlSocketAddrAsyncIPv4Response_t; - -typedef struct -{ - _i16 StatusOrLen; - _u8 Sd; - _u8 Family; - _u16 Port; - _u8 Address[6]; -} SlSocketAddrAsyncIPv6EUI48Response_t; - -typedef struct -{ - _i16 StatusOrLen; - _u8 Sd; - _u8 Family; - _u16 Port; - _u16 PaddingOrAddr; - _u32 Address[4]; -} SlSocketAddrAsyncIPv6Response_t; - -typedef struct -{ - _i16 LenOrPadding; - _u8 Sd; - _u8 FamilyAndFlags; - _u16 Port; - _u16 PaddingOrAddr; - _u32 Address; -} SlSocketAddrIPv4Command_t; - -typedef struct -{ - _i16 LenOrPadding; - _u8 Sd; - _u8 FamilyAndFlags; - _u16 Port; - _u8 Address[6]; -} SlSocketAddrIPv6EUI48Command_t; - -typedef struct -{ - _i16 LenOrPadding; - _u8 Sd; - _u8 FamilyAndFlags; - _u16 Port; - _u16 PaddingOrAddr; - _u32 Address[4]; -} SlSocketAddrIPv6Command_t; - -typedef union { - SlSocketAddrIPv4Command_t IpV4; - SlSocketAddrIPv6EUI48Command_t IpV6EUI48; -#ifdef SL_SUPPORT_IPV6 - SlSocketAddrIPv6Command_t IpV6; -#endif -} SlSocketAddrCommand_u; - -typedef union { - SlSocketAddrAsyncIPv4Response_t IpV4; - SlSocketAddrAsyncIPv6EUI48Response_t IpV6EUI48; -#ifdef SL_SUPPORT_IPV6 - SlSocketAddrAsyncIPv6Response_t IpV6; -#endif -} SlSocketAddrResponse_u; - -typedef struct -{ - _u8 Sd; - _u8 Backlog; - _u8 Padding1; - _u8 Padding2; -} SlListenCommand_t; - -typedef struct -{ - _u8 Sd; - _u8 Padding0; - _u8 Padding1; - _u8 Padding2; -} SlCloseCommand_t; - -typedef struct -{ - _u8 Nfds; - _u8 ReadFdsCount; - _u8 WriteFdsCount; - _u8 Padding; - _u16 ReadFds; - _u16 WriteFds; - _u16 tv_usec; - _u16 tv_sec; -} SlSelectCommand_t; - -typedef struct -{ - _u16 Status; - _u8 ReadFdsCount; - _u8 WriteFdsCount; - _u16 ReadFds; - _u16 WriteFds; -} SlSelectAsyncResponse_t; - -typedef struct -{ - _u8 Sd; - _u8 Level; - _u8 OptionName; - _u8 OptionLen; -} SlSetSockOptCommand_t; - -typedef struct -{ - _u8 Sd; - _u8 Level; - _u8 OptionName; - _u8 OptionLen; -} SlGetSockOptCommand_t; - -typedef struct -{ - _i16 Status; - _u8 Sd; - _u8 OptionLen; -} SlGetSockOptResponse_t; - -typedef struct -{ - _u16 StatusOrLen; - _u8 Sd; - _u8 FamilyAndFlags; -} SlSendRecvCommand_t; - -/***************************************************************************************** -* NETAPP structs -******************************************************************************************/ - -typedef _BasicResponse_t _NetAppStartStopResponse_t; - -typedef struct -{ - _u32 AppId; -}_NetAppStartStopCommand_t; - -typedef struct -{ - _u16 Status; - _u16 AppId; - _u16 ConfigOpt; - _u16 ConfigLen; -} SlNetAppSetGet_t; -typedef struct -{ - _u16 PortNumber; -} SlNetAppHttpServerGetSetPortNum_t; - -typedef struct -{ - _u8 AuthEnable; -} SlNetAppHttpServerGetSetAuthEnable_t; - -typedef struct _SlNetAppHttpServerGetToken_t -{ - _u8 TokenNameLen; - _u8 Padd1; - _u16 Padd2; -}SlNetAppHttpServerGetToken_t; - -typedef struct _SlNetAppHttpServerSendToken_t -{ - _u8 TokenValueLen; - _u8 TokenNameLen; - _u8 TokenName[SL_NETAPP_MAX_TOKEN_NAME_LEN]; - _u16 Padd; -} SlNetAppHttpServerSendToken_t; - -typedef struct _SlNetAppHttpServerPostToken_t -{ - _u8 PostActionLen; - _u8 TokenNameLen; - _u8 TokenValueLen; - _u8 padding; -} SlNetAppHttpServerPostToken_t; - -/***************************************************************************************** -* NETAPP Request/Response/Send/Receive -******************************************************************************************/ -typedef struct _SlProtocolNetAppRequest_t -{ - _u8 AppId; - _u8 RequestType; - _u16 Handle; - _u16 MetadataLen; - _u16 PayloadLen; - _u32 Flags; -} SlProtocolNetAppRequest_t; - -typedef struct _SlProtocolNetAppResponse_t -{ - _u16 Handle; - _u16 status; - _u16 MetadataLen; - _u16 PayloadLen; - _u32 Flags; -} SlProtocolNetAppResponse_t; - -typedef struct _SlProtocolNetAppSend_t -{ - _u16 Handle; - _u16 DataLen; /* can be data payload or metadata, depends on bit 1 in flags */ - _u32 Flags; -} SlProtocolNetAppSend_t; - -typedef struct _SlProtocolNetAppReceiveRequest_t -{ - _u16 Handle; - _u16 MaxBufferLen; - _u32 Flags; -} SlProtocolNetAppReceiveRequest_t; - -typedef struct _SlProtocolNetAppReceive_t -{ - _u16 Handle; - _u16 PayloadLen; - _u32 Flags; -} SlProtocolNetAppReceive_t; - -typedef struct -{ - _u16 Len; - _u8 Family; - _u8 Padding; -} NetAppGetHostByNameCommand_t; - -typedef struct -{ - _u16 Status; - _u16 Padding; - _u32 Ip0; - _u32 Ip1; - _u32 Ip2; - _u32 Ip3; -} NetAppGetHostByNameIPv6AsyncResponse_t; - -typedef struct -{ - _u16 Status; - _u8 Padding1; - _u8 Padding2; - _u32 Ip0; -} NetAppGetHostByNameIPv4AsyncResponse_t; - -typedef enum -{ - CTST_BSD_UDP_TX, - CTST_BSD_UDP_RX, - CTST_BSD_TCP_TX, - CTST_BSD_TCP_RX, - CTST_BSD_TCP_SERVER_BI_DIR, - CTST_BSD_TCP_CLIENT_BI_DIR, - CTST_BSD_UDP_BI_DIR, - CTST_BSD_RAW_TX, - CTST_BSD_RAW_RX, - CTST_BSD_RAW_BI_DIR, - CTST_BSD_SECURED_TCP_TX, - CTST_BSD_SECURED_TCP_RX, - CTST_BSD_SECURED_TCP_SERVER_BI_DIR, - CTST_BSD_SECURED_TCP_CLIENT_BI_DIR, - CTST_BSD_UDP_TX_IPV6, - CTST_BSD_UDP_RX_IPV6, - CTST_BSD_TCP_TX_IPV6, - CTST_BSD_TCP_RX_IPV6, - CTST_BSD_TCP_SERVER_BI_DIR_IPV6, - CTST_BSD_TCP_CLIENT_BI_DIR_IPV6, - CTST_BSD_UDP_BI_DIR_IPV6, - CTST_BSD_RAW_TX_IPV6, - CTST_BSD_RAW_RX_IPV6, - CTST_BSD_RAW_BI_DIR_IPV6, - CTST_BSD_SECURED_TCP_TX_IPV6, - CTST_BSD_SECURED_TCP_RX_IPV6, - CTST_BSD_SECURED_TCP_SERVER_BI_DIR_IPV6, - CTST_BSD_SECURED_TCP_CLIENT_BI_DIR_IPV6, - CTST_RAW_TX, - CTST_RAW_RX - }CommTest_e; - -typedef struct _sl_protocol_CtestStartCommand_t -{ - _u32 Test; - _u16 DestPort; - _u16 SrcPort; - _u32 DestAddr[4]; - _u32 PayloadSize; - _u32 Timeout; - _u32 CsEnabled; - _u32 Secure; - _u32 RawProtocol; - _u8 Reserved1[4]; -}_CtestStartCommand_t; - -typedef struct -{ - _u8 Test; - _u8 Socket; - _i16 Status; - _u32 StartTime; - _u32 EndTime; - _u16 TxKbitsSec; - _u16 RxKbitsSec; - _u32 OutOfOrderPackets; - _u32 MissedPackets; - _i16 Token; -}_CtestAsyncResponse_t; - -typedef struct -{ - _u16 Status; - _u16 RttMin; - _u16 RttMax; - _u16 RttAvg; - _u32 NumSuccsessPings; - _u32 NumSendsPings; - _u32 TestTime; -} SlPingReportResponse_t; - -typedef struct -{ - _u32 Ip; - _u32 Gateway; - _u32 Dns; -} IpV4AcquiredAsync_t; - -typedef enum -{ - ACQUIRED_IPV6_LOCAL = 1, - ACQUIRED_IPV6_GLOBAL -}IpV6AcquiredType_e; - -typedef struct -{ - _u32 Type; - _u32 Ip[4]; - _u32 Gateway[4]; - _u32 Dns[4]; -} IpV6AcquiredAsync_t; - -typedef union -{ - SlSocketCommand_t EventMask; - SlSendRecvCommand_t DeviceInit; -}_device_commands_t; - -/***************************************************************************************** -* FS structs -******************************************************************************************/ - -typedef struct -{ - _u32 FileHandle; - _u32 Offset; - _u16 Len; - _u16 Padding; -} SlFsReadCommand_t; - -typedef struct -{ - _u32 Mode; - _u32 Token; -} SlFsOpenCommand_t; - -typedef struct -{ - _u32 FileHandle; - _u32 Token; -} SlFsOpenResponse_t; - - -typedef struct -{ - _u32 FileHandle; - _u32 CertificFileNameLength; - _u32 SignatureLen; -} SlFsCloseCommand_t; - -typedef _BasicResponse_t SlFsReadResponse_t; -typedef _BasicResponse_t SlFsDeleteResponse_t; -typedef _BasicResponse_t SlFsCloseResponse_t; - -typedef struct -{ - _u16 Status; - _u16 Flags; - _u32 FileLen; - _u32 AllocatedLen; - _u32 Token[4]; - _u32 FileStorageSize; /* The total size that the file required on the storage */ - _u32 FileWriteCounter; /* number of times in which the file have been written successfully */ -} SlFsGetInfoResponse_t; - -typedef struct -{ - _u8 DeviceID; - _u8 Padding[3]; -} SlFsFormatCommand_t; - -typedef _BasicResponse_t SlFsFormatResponse_t; - -typedef struct -{ - _u32 Token; -} SlFsDeleteCommand_t; - -typedef SlFsDeleteCommand_t SlFsGetInfoCommand_t; - -typedef struct -{ - _u32 FileHandle; - _u32 Offset; - _u16 Len; - _u16 Padding; -} SlFsWriteCommand_t; - -typedef _BasicResponse_t SlFsWriteResponse_t; - -typedef struct -{ - _u32 Token; - _u8 Operation; - _u8 Padding[3]; - _u32 FileNameLength; - _u32 BufferLength; -} SlFsFileSysControlCommand_t; - -typedef struct -{ - _i32 Status; - _u32 Token; - _u32 Len; -} SlFsFileSysControlResponse_t; - -typedef struct -{ - _u16 IncludeFileFilters; - _u8 Operation; - _u8 Padding; -} SlFsBundleControlCommand_t; - -typedef struct -{ - _i32 Status; - _u8 BundleState; - _u8 Padding[3]; -} SlFsBundleControlResponse_t; - -typedef struct -{ - _u16 KeyLen; - _u16 ChunkLen; - _u32 Flags; -} SlFsProgramCommand_t; - -typedef struct -{ - _i32 Status; -} SlFsProgramResponse_t; - -typedef struct -{ - _i32 Index; /* start point is -1 */ - _u8 Count; - _u8 MaxEntryLen; - _u8 Flags; - _u8 Padding; -} SlFsGetFileListCommand_t; - -typedef struct -{ - _i32 NumOfEntriesOrError; - _i32 Index; /* -1 , nothing was read */ - _u32 OutputBufferLength; -} SlFsGetFileListResponse_t; - -/* TODO: Set MAx Async Payload length depending on flavor (Tiny, Small, etc.) */ - -#define SL_ASYNC_HTTP_SRV_EVENT_LEN 1600 /* size must be aligned to 4 */ - -#if defined(slcb_NetAppRequestHdlr) || defined(EXT_LIB_REGISTERED_NETAPP_REQUEST_EVENTS) -#define SL_ASYNC_MAX_PAYLOAD_LEN SL_ASYNC_HTTP_SRV_EVENT_LEN -#else -#define SL_ASYNC_MAX_PAYLOAD_LEN 220 /* size must be aligned to 4 */ -#endif - -#define SL_ASYNC_MAX_MSG_LEN (_SL_RESP_HDR_SIZE + SL_ASYNC_MAX_PAYLOAD_LEN) - -#define RECV_ARGS_SIZE (sizeof(SlSocketResponse_t)) -#define RECVFROM_IPV4_ARGS_SIZE (sizeof(SlSocketAddrAsyncIPv4Response_t)) -#define RECVFROM_IPV6_ARGS_SIZE (sizeof(SlSocketAddrAsyncIPv6Response_t)) - -#define SL_IPV4_ADDRESS_SIZE (sizeof(_u32)) -#define SL_IPV6_ADDRESS_SIZE (4 * sizeof(_u32)) - - -/***************************************************************************************** -* NetUtil structures -******************************************************************************************/ -/* Utils Set Get Header */ -typedef struct -{ - _u32 ObjId; - _i16 Status; - _u16 Option; - _u16 ValueLen; - _u8 Padding[2]; -} SlNetUtilSetGet_t; - - -/* NetUtil Command Header */ -typedef struct -{ - _u16 Cmd; - _u16 AttribLen; - _u16 InputLen; - _u16 OutputLen; -} SlNetUtilCmd_t; - -/* NetUtil Command Response Header */ -typedef struct -{ - _u32 ObjId; - _i16 Status; - _u16 Cmd; - _u16 OutputLen; - _u8 Padding[2]; -} SlNetUtilCmdRsp_t; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* _SL_PROTOCOL_TYPES_H_ */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/sl_socket.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/sl_socket.c deleted file mode 100644 index 3bbdd1be243..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/sl_socket.c +++ /dev/null @@ -1,2001 +0,0 @@ -/* - * sl_socket.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -static void _SlSocketBuildAddress(const SlSockAddr_t *addr, SlSocketAddrCommand_u *pCmd); -_SlReturnVal_t _SlSocketHandleAsync_Connect(void *pVoidBuf); -_SlReturnVal_t _SlSocketHandleAsync_Close(void *pVoidBuf); - -void _SlSocketParseAddress(SlSocketAddrResponse_u *pRsp, SlSockAddr_t *addr, SlSocklen_t *addrlen); -_SlReturnVal_t _SlSocketHandleAsync_Accept(void *pVoidBuf); -_SlReturnVal_t _SlSocketHandleAsync_Select(void *pVoidBuf); -_SlReturnVal_t _SlSocketHandleAsync_StartTLS(void *pVoidBuf); - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) -static _i16 _SlDrvClearCtrlSocket(void); -static _i8 _SlDrvGetNextTimeoutValue(void); -#endif - -/*******************************************************************************/ -/* Functions */ -/*******************************************************************************/ - - -/* ******************************************************************************/ -/* _SlSocketBuildAddress */ -/* ******************************************************************************/ -static void _SlSocketBuildAddress(const SlSockAddr_t *addr, SlSocketAddrCommand_u *pCmd) -{ - - /* Note: parsing of family and port in the generic way for all IPV4, IPV6 and EUI48 - is possible as long as these parameters are in the same offset and size for these - three families. */ - pCmd->IpV4.FamilyAndFlags = (_u8)((addr->sa_family << 4) & 0xF0); - pCmd->IpV4.Port = ((SlSockAddrIn_t *)addr)->sin_port; - - if(SL_AF_INET == addr->sa_family) - { - pCmd->IpV4.Address = ((SlSockAddrIn_t *)addr)->sin_addr.s_addr; - } -#ifdef SL_SUPPORT_IPV6 - else - { - sl_Memcpy(pCmd->IpV6.Address, ((SlSockAddrIn6_t *)addr)->sin6_addr._S6_un._S6_u32, 16 ); - } -#endif -} - -/*******************************************************************************/ -/* _SlSocketParseAddress */ -/*******************************************************************************/ -void _SlSocketParseAddress(SlSocketAddrResponse_u *pRsp, SlSockAddr_t *addr, SlSocklen_t *addrlen) -{ - /* Note: parsing of family and port in the generic way for all IPV4, IPV6 and EUI48 */ - /* is possible as long as these parameters are in the same offset and size for these */ - /* three families. */ - addr->sa_family = pRsp->IpV4.Family; - ((SlSockAddrIn_t *)addr)->sin_port = pRsp->IpV4.Port; - - *addrlen = (SL_AF_INET == addr->sa_family) ? sizeof(SlSockAddrIn_t) : sizeof(SlSockAddrIn6_t); - - if(SL_AF_INET == addr->sa_family) - { - ((SlSockAddrIn_t *)addr)->sin_addr.s_addr = pRsp->IpV4.Address; - } -#ifdef SL_SUPPORT_IPV6 - else - { - sl_Memcpy(((SlSockAddrIn6_t *)addr)->sin6_addr._S6_un._S6_u32, pRsp->IpV6.Address, 16); - } -#endif -} - -/*******************************************************************************/ -/* sl_Socket */ -/*******************************************************************************/ -typedef union -{ - _u32 Dummy; - SlSocketCommand_t Cmd; - SlSocketResponse_t Rsp; -}_SlSockSocketMsg_u; - -#if _SL_INCLUDE_FUNC(sl_Socket) - -static const _SlCmdCtrl_t _SlSockSocketCmdCtrl = -{ - SL_OPCODE_SOCKET_SOCKET, - (_SlArgSize_t)sizeof(SlSocketCommand_t), - (_SlArgSize_t)sizeof(SlSocketResponse_t) -}; - -_i16 sl_Socket(_i16 Domain, _i16 Type, _i16 Protocol) -{ - _SlSockSocketMsg_u Msg; - - Msg.Cmd.Domain = (_u8)Domain; - Msg.Cmd.Type = (_u8)Type; - Msg.Cmd.Protocol = (_u8)Protocol; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSockSocketCmdCtrl, &Msg, NULL)); - - if( Msg.Rsp.StatusOrLen < 0 ) - { - return ( Msg.Rsp.StatusOrLen); - } - else - { - return (_i16)((_u8)Msg.Rsp.Sd); - } -} -#endif - -/*******************************************************************************/ -/* sl_Close */ -/*******************************************************************************/ -typedef union -{ - SlCloseCommand_t Cmd; - SlSocketResponse_t Rsp; -}_SlSockCloseMsg_u; - -#if _SL_INCLUDE_FUNC(sl_Close) - -static const _SlCmdCtrl_t _SlSockCloseCmdCtrl = -{ - SL_OPCODE_SOCKET_CLOSE, - (_SlArgSize_t)sizeof(SlCloseCommand_t), - (_SlArgSize_t)sizeof(SlSocketResponse_t) -}; - -_i16 sl_Close(_i16 sd) -{ - _SlSockCloseMsg_u Msg; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - SlSocketResponse_t AsyncRsp; - _SlReturnVal_t RetVal; - _u8 bSocketInAction = FALSE; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - Msg.Cmd.Sd = (_u8)sd; - _SlDrvMemZero(&AsyncRsp, sizeof(SlSocketResponse_t)); - - /* check if the socket has already action in progress */ - bSocketInAction = !!(g_pCB->ActiveActionsBitmap & (1<sa_family) - { - case SL_AF_INET: - CmdCtrl.Opcode = SL_OPCODE_SOCKET_BIND; - CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv4Command_t); - break; -#ifdef SL_SUPPORT_IPV6 - case SL_AF_INET6: - CmdCtrl.Opcode = SL_OPCODE_SOCKET_BIND_V6; - CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv6Command_t); - break; -#endif - case SL_AF_RF: - default: - return SL_RET_CODE_INVALID_INPUT; - } - - Msg.Cmd.IpV4.LenOrPadding = 0; - Msg.Cmd.IpV4.Sd = (_u8)sd; - - _SlSocketBuildAddress(addr, &Msg.Cmd); - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, &Msg, NULL)); - - return Msg.Rsp.StatusOrLen; -} -#endif - -/*******************************************************************************/ -/* sl_Sendto */ -/*******************************************************************************/ -typedef union -{ - SlSocketAddrCommand_u Cmd; - /* no response for 'sendto' commands*/ -}_SlSendtoMsg_u; - -#if _SL_INCLUDE_FUNC(sl_SendTo) -_i16 sl_SendTo(_i16 sd, const void *pBuf, _i16 Len, _i16 flags, const SlSockAddr_t *to, SlSocklen_t tolen) -{ - _SlSendtoMsg_u Msg; - _SlCmdCtrl_t CmdCtrl = {0, 0, 0}; - _SlCmdExt_t CmdExt; - _i16 RetVal; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - /* RAW transceiver use only sl_Send */ - if ((sd & SL_SOCKET_PAYLOAD_TYPE_MASK) == SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER) - { - return SL_ERROR_BSD_SOC_ERROR; - } - else - { - if (Len < 1) - { - /* ignore */ - return 0; - } - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = (_u16)Len; - CmdExt.pTxPayload1 = (_u8 *)pBuf; - - switch(to->sa_family) - { - case SL_AF_INET: - CmdCtrl.Opcode = SL_OPCODE_SOCKET_SENDTO; - CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv4Command_t); - break; -#ifdef SL_SUPPORT_IPV6 - case SL_AF_INET6: - CmdCtrl.Opcode = SL_OPCODE_SOCKET_SENDTO_V6; - CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv6Command_t); - break; -#endif - case SL_AF_RF: - default: - return SL_RET_CODE_INVALID_INPUT; - } - - Msg.Cmd.IpV4.LenOrPadding = Len; - Msg.Cmd.IpV4.Sd = (_u8)sd; - _SlSocketBuildAddress(to, &Msg.Cmd); - Msg.Cmd.IpV4.FamilyAndFlags |= flags & 0x0F; - - RetVal = _SlDrvDataWriteOp((_SlSd_t)sd, &CmdCtrl, &Msg, &CmdExt); - if(SL_OS_RET_CODE_OK != RetVal) - { - return RetVal; - } - - return (_i16)Len; -} -#endif - -/*******************************************************************************/ -/* sl_Recvfrom */ -/*******************************************************************************/ -typedef union -{ - SlSendRecvCommand_t Cmd; - SlSocketAddrResponse_u Rsp; -}_SlRecvfromMsg_u; - -static const _SlCmdCtrl_t _SlRecvfomCmdCtrl = -{ - SL_OPCODE_SOCKET_RECVFROM, - (_SlArgSize_t)sizeof(SlSendRecvCommand_t), - (_SlArgSize_t)sizeof(SlSocketAddrResponse_u) -}; - -#if _SL_INCLUDE_FUNC(sl_RecvFrom) -_i16 sl_RecvFrom(_i16 sd, void *buf, _i16 Len, _i16 flags, SlSockAddr_t *from, SlSocklen_t *fromlen) -{ - _SlRecvfromMsg_u Msg; - _SlCmdExt_t CmdExt; - _i16 RetVal; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - /* RAW transceiver use only sl_Recv */ - if ((sd & SL_SOCKET_PAYLOAD_TYPE_MASK) == SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER) - { - return SL_ERROR_BSD_SOC_ERROR; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = Len; - CmdExt.pRxPayload = (_u8 *)buf; - - Msg.Cmd.Sd = (_u8)sd; - Msg.Cmd.StatusOrLen = (_u16)Len; - - /* no size truncation in recv path */ - CmdExt.RxPayloadLen = (_i16)Msg.Cmd.StatusOrLen; - - Msg.Cmd.FamilyAndFlags = (_u8)(flags & 0x0F); - - if(sizeof(SlSockAddrIn_t) == *fromlen) - { - Msg.Cmd.FamilyAndFlags |= (SL_AF_INET << 4); - } - else if (sizeof(SlSockAddrIn6_t) == *fromlen) - { - Msg.Cmd.FamilyAndFlags |= (SL_AF_INET6 << 4); - } - else - { - return SL_RET_CODE_INVALID_INPUT; - } - - RetVal = _SlDrvDataReadOp((_SlSd_t)sd, (_SlCmdCtrl_t *)&_SlRecvfomCmdCtrl, &Msg, &CmdExt); - if( RetVal != SL_OS_RET_CODE_OK ) - { - return RetVal; - } - - RetVal = Msg.Rsp.IpV4.StatusOrLen; - - if(RetVal >= 0) - { - VERIFY_PROTOCOL(sd == (_i16)Msg.Rsp.IpV4.Sd); -#if 0 - _SlSocketParseAddress(&Msg.Rsp, from, fromlen); -#else - from->sa_family = Msg.Rsp.IpV4.Family; - if(SL_AF_INET == from->sa_family) - { - ((SlSockAddrIn_t *)from)->sin_port = Msg.Rsp.IpV4.Port; - ((SlSockAddrIn_t *)from)->sin_addr.s_addr = Msg.Rsp.IpV4.Address; - *fromlen = (SlSocklen_t)sizeof(SlSockAddrIn_t); - } -#ifdef SL_SUPPORT_IPV6 - else if(SL_AF_INET6 == from->sa_family) - { - VERIFY_PROTOCOL(*fromlen >= sizeof(SlSockAddrIn6_t)); - - ((SlSockAddrIn6_t *)from)->sin6_port = Msg.Rsp.IpV6.Port; - sl_Memcpy(((SlSockAddrIn6_t *)from)->sin6_addr._S6_un._S6_u32, Msg.Rsp.IpV6.Address, 16); - *fromlen = sizeof(SlSockAddrIn6_t); - } -#endif -#endif - } - - return (_i16)RetVal; -} -#endif - -/*******************************************************************************/ -/* sl_Connect */ -/*******************************************************************************/ -typedef union -{ - SlSocketAddrCommand_u Cmd; - SlSocketResponse_t Rsp; -}_SlSockConnectMsg_u; - -#if _SL_INCLUDE_FUNC(sl_Connect) -_i16 sl_Connect(_i16 sd, const SlSockAddr_t *addr, _i16 addrlen) -{ - _SlSockConnectMsg_u Msg; - _SlReturnVal_t RetVal; - _SlCmdCtrl_t CmdCtrl = {0, (_SlArgSize_t)0, (_SlArgSize_t)sizeof(SlSocketResponse_t)}; - SlSocketResponse_t AsyncRsp; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - _SlDrvMemZero(&AsyncRsp, sizeof(SlSocketResponse_t)); - - switch(addr->sa_family) - { - case SL_AF_INET : - CmdCtrl.Opcode = SL_OPCODE_SOCKET_CONNECT; - CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv4Command_t); - /* Do nothing - cmd already initialized to this type */ - break; -#ifdef SL_SUPPORT_IPV6 - case SL_AF_INET6: - CmdCtrl.Opcode = SL_OPCODE_SOCKET_CONNECT_V6; - CmdCtrl.TxDescLen = (_SlArgSize_t)sizeof(SlSocketAddrIPv6Command_t); - break; -#endif - case SL_AF_RF: - default: - return SL_RET_CODE_INVALID_INPUT; - } - - Msg.Cmd.IpV4.LenOrPadding = 0; - Msg.Cmd.IpV4.Sd = (_u8)sd; - - _SlSocketBuildAddress(addr, &Msg.Cmd); - - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, CONNECT_ID, (_u8)(sd & SL_BSD_SOCKET_ID_MASK)); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - /* send the command */ - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, &Msg, NULL)); - VERIFY_PROTOCOL(Msg.Rsp.Sd == (_u8)sd); - - RetVal = Msg.Rsp.StatusOrLen; - - if(SL_RET_CODE_OK == RetVal) - { - /*In case socket is non-blocking one, the async event should be received immediately */ - if( g_pCB->SocketNonBlocking & (1<<(sd & SL_BSD_SOCKET_ID_MASK) )) - { - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, SL_DRIVER_TIMEOUT_SHORT, SL_OPCODE_SOCKET_CONNECTASYNCRESPONSE)); - } - else - { - - /* wait for async and get Data Read parameters */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, 0, 0)); - } - - RetVal = AsyncRsp.StatusOrLen; - - if (0 <= RetVal) - { - VERIFY_PROTOCOL(AsyncRsp.Sd == (_u8)sd); - } - } - - _SlDrvReleasePoolObj(ObjIdx); - return RetVal; -} - -#endif - - -/*******************************************************************************/ -/* _SlSocketHandleAsync_Connect */ -/*******************************************************************************/ -_SlReturnVal_t _SlSocketHandleAsync_Connect(void *pVoidBuf) -{ - SlSocketResponse_t *pMsgArgs = (SlSocketResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_PROTOCOL((pMsgArgs->Sd & SL_BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS); - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Sd = pMsgArgs->Sd; - ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->StatusOrLen = pMsgArgs->StatusOrLen; - - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return SL_OS_RET_CODE_OK; -} - -/*******************************************************************************/ -/* _SlSocketHandleAsync_Close */ -/*******************************************************************************/ -_SlReturnVal_t _SlSocketHandleAsync_Close(void *pVoidBuf) -{ - SlSocketResponse_t *pMsgArgs = (SlSocketResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_PROTOCOL((pMsgArgs->Sd & SL_BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS); - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Sd = pMsgArgs->Sd; - ((SlSocketResponse_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->StatusOrLen = pMsgArgs->StatusOrLen; - - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return SL_OS_RET_CODE_OK; -} - -/*******************************************************************************/ -/* sl_Send */ -/*******************************************************************************/ -typedef union -{ - SlSendRecvCommand_t Cmd; - /* no response for 'sendto' commands*/ -}_SlSendMsg_u; - -static const _SlCmdCtrl_t _SlSendCmdCtrl = -{ - SL_OPCODE_SOCKET_SEND, - (_SlArgSize_t)sizeof(SlSendRecvCommand_t), - (_SlArgSize_t)0 -}; - -#if _SL_INCLUDE_FUNC(sl_Send) -_i16 sl_Send(_i16 sd, const void *pBuf, _i16 Len, _i16 flags) -{ - _SlSendMsg_u Msg; - _SlCmdExt_t CmdExt; - _i16 RetVal; - _u32 tempVal; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = (_u16)Len; - CmdExt.pTxPayload1 = (_u8 *)pBuf; - - /* Only for RAW transceiver type socket, relay the flags parameter in the 2 bytes (4 byte aligned) before the actual payload */ - if ((sd & SL_SOCKET_PAYLOAD_TYPE_MASK) == SL_SOCKET_PAYLOAD_TYPE_RAW_TRANCEIVER) - { - tempVal = (_u32)flags; - CmdExt.pRxPayload = (_u8 *)&tempVal; - CmdExt.RxPayloadLen = -4; /* the (-) sign is used to mark the rx buff as output buff as well*/ - } - else - { - CmdExt.pRxPayload = NULL; - if (Len < 1) - { - /* ignore */ - return 0; - } - } - - Msg.Cmd.StatusOrLen = Len; - Msg.Cmd.Sd = (_u8)sd; - Msg.Cmd.FamilyAndFlags |= flags & 0x0F; - - RetVal = _SlDrvDataWriteOp((_u8)sd, (_SlCmdCtrl_t *)&_SlSendCmdCtrl, &Msg, &CmdExt); - if(SL_OS_RET_CODE_OK != RetVal) - { - return RetVal; - } - - return (_i16)Len; -} -#endif - -/*******************************************************************************/ -/* sl_Listen */ -/*******************************************************************************/ -typedef union -{ - SlListenCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlListenMsg_u; - -#if _SL_INCLUDE_FUNC(sl_Listen) - -static const _SlCmdCtrl_t _SlListenCmdCtrl = -{ - SL_OPCODE_SOCKET_LISTEN, - (_SlArgSize_t)sizeof(SlListenCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t), -}; - -_i16 sl_Listen(_i16 sd, _i16 backlog) -{ - _SlListenMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - Msg.Cmd.Sd = (_u8)sd; - Msg.Cmd.Backlog = (_u8)backlog; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlListenCmdCtrl, &Msg, NULL)); - return (_i16)Msg.Rsp.status; -} -#endif - -/*******************************************************************************/ -/* sl_Accept */ -/*******************************************************************************/ -typedef union -{ - SlAcceptCommand_t Cmd; - SlSocketResponse_t Rsp; -}_SlSockAcceptMsg_u; - -#if _SL_INCLUDE_FUNC(sl_Accept) - -static const _SlCmdCtrl_t _SlAcceptCmdCtrl = -{ - SL_OPCODE_SOCKET_ACCEPT, - (_SlArgSize_t)sizeof(SlAcceptCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t), -}; - -_i16 sl_Accept(_i16 sd, SlSockAddr_t *addr, SlSocklen_t *addrlen) -{ - _SlSockAcceptMsg_u Msg; - _SlReturnVal_t RetVal; - SlSocketAddrResponse_u AsyncRsp; - - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - Msg.Cmd.Sd = (_u8)sd; - - if((addr != NULL) && (addrlen != NULL)) - { - /* If addr is present, addrlen has to be provided */ - Msg.Cmd.Family = (_u8)((sizeof(SlSockAddrIn_t) == *addrlen) ? SL_AF_INET : SL_AF_INET6); - } - else - { - /* In any other case, addrlen is ignored */ - Msg.Cmd.Family = (_u8)0; - } - - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, ACCEPT_ID, (_u8)sd & SL_BSD_SOCKET_ID_MASK); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - /* send the command */ - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlAcceptCmdCtrl, &Msg, NULL)); - VERIFY_PROTOCOL(Msg.Rsp.Sd == (_u8)sd); - - RetVal = Msg.Rsp.StatusOrLen; - - if(SL_OS_RET_CODE_OK == RetVal) - { - /* in case socket is non-blocking one, the async event should be received immediately */ - if( g_pCB->SocketNonBlocking & (1<<(sd & SL_BSD_SOCKET_ID_MASK) )) - { - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx, SL_DRIVER_TIMEOUT_SHORT, SL_OPCODE_SOCKET_ACCEPTASYNCRESPONSE)); - } - else - { - /* wait for async and get Data Read parameters */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); - } - - RetVal = AsyncRsp.IpV4.StatusOrLen; - - if (0 <= RetVal) - { - VERIFY_PROTOCOL(AsyncRsp.IpV4.Sd == (_u8)sd); - } - - -#if 0 /* Kept for backup */ - _SlSocketParseAddress(&AsyncRsp, addr, addrlen); -#else - if((addr != NULL) && (addrlen != NULL)) - { - addr->sa_family = AsyncRsp.IpV4.Family; - - if(SL_AF_INET == addr->sa_family) - { - if( *addrlen == (SlSocklen_t)sizeof( SlSockAddrIn_t ) ) - { - ((SlSockAddrIn_t *)addr)->sin_port = AsyncRsp.IpV4.Port; - ((SlSockAddrIn_t *)addr)->sin_addr.s_addr = AsyncRsp.IpV4.Address; - } - else - { - *addrlen = 0; - } - } -#ifdef SL_SUPPORT_IPV6 - else if(SL_AF_INET6 == addr->sa_family) - { - if( *addrlen == sizeof( SlSockAddrIn6_t ) ) - { - ((SlSockAddrIn6_t *)addr)->sin6_port = AsyncRsp.IpV6.Port ; - sl_Memcpy(((SlSockAddrIn6_t *)addr)->sin6_addr._S6_un._S6_u32, AsyncRsp.IpV6.Address, 16); - } - else - { - *addrlen = 0; - } - } -#endif - } -#endif - } - - _SlDrvReleasePoolObj(ObjIdx); - return (_i16)RetVal; -} -#endif - - -/*******************************************************************************/ -/* sl_Htonl */ -/*******************************************************************************/ -_u32 sl_Htonl( _u32 val ) -{ - _u32 i = 1; - _i8 *p = (_i8 *)&i; - if (p[0] == 1) /* little endian */ - { - p[0] = ((_i8* )&val)[3]; - p[1] = ((_i8* )&val)[2]; - p[2] = ((_i8* )&val)[1]; - p[3] = ((_i8* )&val)[0]; - return i; - } - else /* big endian */ - { - return val; - } -} - -/*******************************************************************************/ -/* sl_Htonl */ -/*******************************************************************************/ -_u16 sl_Htons( _u16 val ) -{ - _i16 i = 1; - _i8 *p = (_i8 *)&i; - if (p[0] == 1) /* little endian */ - { - p[0] = ((_i8* )&val)[1]; - p[1] = ((_i8* )&val)[0]; - return (_u16)i; - } - else /* big endian */ - { - return val; - } -} - -/*******************************************************************************/ -/* _SlSocketHandleAsync_Accept */ -/*******************************************************************************/ -_SlReturnVal_t _SlSocketHandleAsync_Accept(void *pVoidBuf) -{ - SlSocketAddrResponse_u *pMsgArgs = (SlSocketAddrResponse_u *)_SL_RESP_ARGS_START(pVoidBuf); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_PROTOCOL(( pMsgArgs->IpV4.Sd & SL_BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS); - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs,sizeof(SlSocketAddrResponse_u)); - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return SL_OS_RET_CODE_OK; -} - -/*******************************************************************************/ -/* sl_Recv */ -/*******************************************************************************/ -typedef union -{ - SlSendRecvCommand_t Cmd; - SlSocketResponse_t Rsp; -}_SlRecvMsg_u; - -#if _SL_INCLUDE_FUNC(sl_Recv) - -static const _SlCmdCtrl_t _SlRecvCmdCtrl = -{ - SL_OPCODE_SOCKET_RECV, - (_SlArgSize_t)sizeof(SlSendRecvCommand_t), - (_SlArgSize_t)sizeof(SlSocketResponse_t) -}; - -_i16 sl_Recv(_i16 sd, void *pBuf, _i16 Len, _i16 flags) -{ - _SlRecvMsg_u Msg; - _SlCmdExt_t CmdExt; - _SlReturnVal_t status; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = Len; - CmdExt.pRxPayload = (_u8 *)pBuf; - - Msg.Cmd.Sd = (_u8)sd; - Msg.Cmd.StatusOrLen = (_u16)Len; - - /* no size truncation in recv path */ - CmdExt.RxPayloadLen = (_i16)Msg.Cmd.StatusOrLen; - - Msg.Cmd.FamilyAndFlags = (_u8)(flags & 0x0F); - - status = _SlDrvDataReadOp((_SlSd_t)sd, (_SlCmdCtrl_t *)&_SlRecvCmdCtrl, &Msg, &CmdExt); - if( status != SL_OS_RET_CODE_OK ) - { - return status; - } - - /* if the Device side sends less than expected it is not the Driver's role */ - /* the returned value could be smaller than the requested size */ - return (_i16)Msg.Rsp.StatusOrLen; -} -#endif - -/*******************************************************************************/ -/* sl_SetSockOpt */ -/*******************************************************************************/ -typedef union -{ - SlSetSockOptCommand_t Cmd; - SlSocketResponse_t Rsp; -}_SlSetSockOptMsg_u; - -static const _SlCmdCtrl_t _SlSetSockOptCmdCtrl = -{ - SL_OPCODE_SOCKET_SETSOCKOPT, - (_SlArgSize_t)sizeof(SlSetSockOptCommand_t), - (_SlArgSize_t)sizeof(SlSocketResponse_t) -}; - -#if _SL_INCLUDE_FUNC(sl_SetSockOpt) -_i16 sl_SetSockOpt(_i16 sd, _i16 level, _i16 optname, const void *optval, SlSocklen_t optlen) -{ - _SlSetSockOptMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = optlen; - CmdExt.pTxPayload1 = (_u8 *)optval; - - Msg.Cmd.Sd = (_u8)sd; - Msg.Cmd.Level = (_u8)level; - Msg.Cmd.OptionLen = (_u8)optlen; - Msg.Cmd.OptionName = (_u8)optname; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSetSockOptCmdCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.StatusOrLen; -} -#endif - -/*******************************************************************************/ -/* sl_GetSockOpt */ -/*******************************************************************************/ -typedef union -{ - SlGetSockOptCommand_t Cmd; - SlGetSockOptResponse_t Rsp; -}_SlGetSockOptMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_GetSockOpt) - -static const _SlCmdCtrl_t _SlGetSockOptCmdCtrl = -{ - SL_OPCODE_SOCKET_GETSOCKOPT, - (_SlArgSize_t)sizeof(SlGetSockOptCommand_t), - (_SlArgSize_t)sizeof(SlGetSockOptResponse_t) -}; - -_i16 sl_GetSockOpt(_i16 sd, _i16 level, _i16 optname, void *optval, SlSocklen_t *optlen) -{ - _SlGetSockOptMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - if (*optlen == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)(*optlen); - CmdExt.pRxPayload = optval; - - Msg.Cmd.Sd = (_u8)sd; - Msg.Cmd.Level = (_u8)level; - Msg.Cmd.OptionLen = (_u8)(*optlen); - Msg.Cmd.OptionName = (_u8)optname; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlGetSockOptCmdCtrl, &Msg, &CmdExt)); - - if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *optlen = Msg.Rsp.OptionLen; - return SL_ESMALLBUF; - } - else - { - *optlen = (_u8)CmdExt.ActualRxPayloadLen; - } - return (_i16)Msg.Rsp.Status; -} -#endif - -/********************************************************************************/ -/* sl_Select */ -/* ******************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_Select) - -typedef union -{ - SlSelectCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlSelectMsg_u; - -static const _SlCmdCtrl_t _SlSelectCmdCtrl = -{ - SL_OPCODE_SOCKET_SELECT, - (_SlArgSize_t)sizeof(SlSelectCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -/********************************************************************************/ -/* SL_SOCKET_FD_SET */ -/* ******************************************************************************/ -void SL_SOCKET_FD_SET(_i16 fd, SlFdSet_t *fdset) -{ - fdset->fd_array[0] |= (1<< (fd & SL_BSD_SOCKET_ID_MASK)); -} - -/*******************************************************************************/ -/* SL_SOCKET_FD_CLR */ -/*******************************************************************************/ -void SL_SOCKET_FD_CLR(_i16 fd, SlFdSet_t *fdset) -{ - fdset->fd_array[0] &= ~(1<< (fd & SL_BSD_SOCKET_ID_MASK)); -} - -/*******************************************************************************/ -/* SL_SOCKET_FD_ISSET */ -/*******************************************************************************/ -_i16 SL_SOCKET_FD_ISSET(_i16 fd, SlFdSet_t *fdset) -{ - if( fdset->fd_array[0] & (1<< (fd & SL_BSD_SOCKET_ID_MASK)) ) - { - return 1; - } - return 0; -} - -/*******************************************************************************/ -/* SL_SOCKET_FD_ZERO */ -/*******************************************************************************/ -void SL_SOCKET_FD_ZERO(SlFdSet_t *fdset) -{ - fdset->fd_array[0] = 0; -} - -#if (defined(SL_PLATFORM_MULTI_THREADED) && !defined(slcb_SocketTriggerEventHandler)) - -/*******************************************************************************/ -/* Multiple Select */ -/*******************************************************************************/ - -/* Multiple Select Defines */ -#define LOCAL_CTRL_PORT (3632) -#define SL_LOOPBACK_ADDR (0x0100007F) -#define DUMMY_BUF_SIZE (4) -#define CTRL_SOCK_FD (((_u16)(1)) << g_pCB->MultiSelectCB.CtrlSockFD) -#define SELECT_TIMEOUT ((_u16)0) -#define SELECT_NO_TIMEOUT (0xFFFFFFFF) - -/* Multiple Select Structures */ -_SlSelectMsg_u Msg; - -static const SlSockAddrIn_t _SlCtrlSockAddr = -{ - SL_AF_INET, - LOCAL_CTRL_PORT, - {SL_INADDR_ANY}, - {0,0,0,0,0,0,0,0} -}; - -static const SlSockAddrIn_t _SlCtrlSockRelease = -{ - SL_AF_INET, - LOCAL_CTRL_PORT, - {SL_LOOPBACK_ADDR}, - {0,0,0,0,0,0,0,0} -}; - -/*******************************************************************************/ -/* CountSetBits */ -/*******************************************************************************/ -static inline _u8 CountSetBits(_u16 fdList) -{ - _u8 Count = 0; - - while(fdList) - { - Count += (fdList & ((_u16)1)); - fdList = fdList >> 1; - } - - return Count; -} - -/*******************************************************************************/ -/* _SlSocketHandleAsync_Select */ -/*******************************************************************************/ -_SlReturnVal_t _SlSocketHandleAsync_Select(void *pVoidBuf) -{ - _SlReturnVal_t RetVal; - SlSelectAsyncResponse_t *pMsgArgs = (SlSelectAsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); - _u8 RegIdx = 0; - _u32 time_now; - _u8 TimeoutEvent = 0; - _u16 SelectEvent = 0; - _u8 PendingSelect = FALSE; - - _SlDrvMemZero(&Msg, sizeof(_SlSelectMsg_u)); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->MultiSelectCB.SelectLockObj); - - /* Check if this context was triggered by a 'select joiner' only, - * without timeout occurring, in order to launch the next select as quick as possible */ - if((CTRL_SOCK_FD == pMsgArgs->ReadFds) && (pMsgArgs->Status != SELECT_TIMEOUT)) - { - RetVal = _SlDrvClearCtrlSocket(); - Msg.Cmd.ReadFds = g_pCB->MultiSelectCB.readsds; - Msg.Cmd.WriteFds = g_pCB->MultiSelectCB.writesds; - Msg.Cmd.ReadFds |= CTRL_SOCK_FD; - Msg.Cmd.tv_sec = 0xFFFF; - Msg.Cmd.tv_usec = 0xFFFF; - - RegIdx = _SlDrvGetNextTimeoutValue(); - - SL_TRACE3(DBG_MSG, MSG_312, "\n\rAdded caller: call Select with: Write:%x Sec:%d uSec:%d\n\r", - Msg.Cmd.WriteFds, Msg.Cmd.tv_sec, Msg.Cmd.tv_usec); - - RetVal = _SlDrvCmdSend_noWait((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL); - - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return RetVal; - } - - /* If we're triggered by the NWP, take time-stamps to monitor the time-outs */ - time_now = ((slcb_GetTimestamp() / SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS) * 10); - - /* If it's a proper select response, or if timeout occurred, release the relevant waiters */ - for(RegIdx = 0 ; RegIdx < MAX_CONCURRENT_ACTIONS ; RegIdx++) - { - if(g_pCB->MultiSelectCB.SelectEntry[RegIdx] != NULL) - { - /* In case a certain entry has 100 mSec or less until it's timeout, the overhead - * caused by calling select again with it's fd lists is redundant, just return a time-out. */ - - TimeoutEvent = ((time_now + 100) >= g_pCB->MultiSelectCB.SelectEntry[RegIdx]->TimeStamp); - - if(pMsgArgs->Status != SELECT_TIMEOUT) - { - SelectEvent = ((g_pCB->MultiSelectCB.SelectEntry[RegIdx]->readlist & pMsgArgs->ReadFds) || - (g_pCB->MultiSelectCB.SelectEntry[RegIdx]->writelist & pMsgArgs->WriteFds)); - } - - if(SelectEvent || TimeoutEvent) - { - - - /* Clear the global select socket descriptor bitmaps */ - g_pCB->MultiSelectCB.readsds &= ~(g_pCB->MultiSelectCB.SelectEntry[RegIdx]->readlist); - g_pCB->MultiSelectCB.writesds &= ~(g_pCB->MultiSelectCB.SelectEntry[RegIdx]->writelist); - - if(SelectEvent) - { - /* set the corresponding fd lists. */ - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.ReadFds = (pMsgArgs->ReadFds & g_pCB->MultiSelectCB.SelectEntry[RegIdx]->readlist); - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.WriteFds = (pMsgArgs->WriteFds & g_pCB->MultiSelectCB.SelectEntry[RegIdx]->writelist); - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.ReadFdsCount = CountSetBits(g_pCB->MultiSelectCB.SelectEntry[RegIdx]->readlist); - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.WriteFdsCount = CountSetBits(g_pCB->MultiSelectCB.SelectEntry[RegIdx]->writelist); - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.Status = (g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.ReadFdsCount + - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.WriteFdsCount); - } - else - { - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.Status = SELECT_TIMEOUT; - } - - g_pCB->MultiSelectCB.SelectEntry[RegIdx]->Response.ReadFds &= ~(CTRL_SOCK_FD); - - /* Signal the waiting caller. */ - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->MultiSelectCB.SelectEntry[RegIdx]->ObjIdx].SyncObj); - - /* Clean it's table entry */ - g_pCB->MultiSelectCB.SelectEntry[RegIdx] = NULL; - } - else - { - PendingSelect = TRUE; - } - } - } - - /* In case where A caller was added, but also some sockfd were set on the NWP, - * We clear the control socket. */ - if((pMsgArgs->ReadFds & CTRL_SOCK_FD) && (pMsgArgs->Status != SELECT_TIMEOUT)) - { - RetVal = _SlDrvClearCtrlSocket(); - } - - /* If more readers/Writers are present, send select again */ - if((0 != g_pCB->MultiSelectCB.readsds) || (0 != g_pCB->MultiSelectCB.writesds) || (TRUE == PendingSelect)) - { - Msg.Cmd.ReadFds = g_pCB->MultiSelectCB.readsds; - Msg.Cmd.ReadFds |= CTRL_SOCK_FD; - Msg.Cmd.WriteFds = g_pCB->MultiSelectCB.writesds; - - /* Set timeout to blocking, in case there is no caller with timeout value. */ - Msg.Cmd.tv_sec = 0xFFFF; - Msg.Cmd.tv_usec = 0xFFFF; - - /* Get the next awaiting timeout caller */ - RegIdx = _SlDrvGetNextTimeoutValue(); - - SL_TRACE3(DBG_MSG, MSG_312, "\n\rRelease Partial: call Select with: Read:%x Sec:%d uSec:%d\n\r", - Msg.Cmd.ReadFds, Msg.Cmd.tv_sec, Msg.Cmd.tv_usec); - - RetVal = _SlDrvCmdSend_noWait((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL); - } - else - { - while(g_pCB->MultiSelectCB.ActiveWaiters) - { - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->MultiSelectCB.SelectSyncObj); - g_pCB->MultiSelectCB.ActiveWaiters--; - } - - g_pCB->MultiSelectCB.ActiveSelect = FALSE; - - SL_TRACE1(DBG_MSG, MSG_312, "\n\rSelect isn't Active: %d\n\r", g_pCB->MultiSelectCB.ActiveSelect); - } - - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return SL_OS_RET_CODE_OK; -} - -/*******************************************************************************/ -/* SlDrvGetNextTimeoutValue */ -/*******************************************************************************/ -static _i8 _SlDrvGetNextTimeoutValue(void) -{ - _u32 time_now; - _i8 Found = -1; - _u8 idx = 0; - - /* Take a timestamp */ - time_now = ((slcb_GetTimestamp() / SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS) * 10); - - /* Go through all waiting time-outs, and select the closest */ - for(idx = 0 ; idx < MAX_CONCURRENT_ACTIONS ; idx++) - { - if(NULL != g_pCB->MultiSelectCB.SelectEntry[idx]) - { - /* Check if the time-stamp is bigger or equal to current time, and if it's the minimal time-stamp (closest event) */ - if(g_pCB->MultiSelectCB.SelectEntry[idx]->TimeStamp >= time_now) - { - if(Found == -1) - { - Found = idx; - } - else - { - if(g_pCB->MultiSelectCB.SelectEntry[idx]->TimeStamp <= g_pCB->MultiSelectCB.SelectEntry[Found]->TimeStamp) - { - Found = idx; - } - } - } - } - } - - /* If a non-wait-forever index was found, calculate delta until closest event */ - if(g_pCB->MultiSelectCB.SelectEntry[Found]->TimeStamp != SELECT_NO_TIMEOUT) - { - _i32 delta = (g_pCB->MultiSelectCB.SelectEntry[Found]->TimeStamp - time_now); - - if(delta >= 0) - { - Msg.Cmd.tv_sec = (delta / 1000); - Msg.Cmd.tv_usec = (((delta % 1000) * 1000) >> 10); - } - else - { - /* if delta time calculated is negative, call a non-blocking select */ - Msg.Cmd.tv_sec = 0; - Msg.Cmd.tv_usec = 0; - } - } - - return Found; -} - -/*******************************************************************************/ -/* _SlDrvClearCtrlSocket */ -/*******************************************************************************/ -static _i16 _SlDrvClearCtrlSocket(void) -{ - _SlRecvfromMsg_u Msg; - _SlCmdExt_t CmdExt; - _u8 dummyBuf[DUMMY_BUF_SIZE]; - _SlReturnVal_t RetVal; - - /* Prepare a recvFrom Cmd */ - _SlDrvResetCmdExt(&CmdExt); - _SlDrvMemZero(&Msg, sizeof(_SlRecvfromMsg_u)); - - CmdExt.RxPayloadLen = DUMMY_BUF_SIZE; - CmdExt.pRxPayload = (_u8 *)&dummyBuf; - - Msg.Cmd.Sd = (_u8)g_pCB->MultiSelectCB.CtrlSockFD; - Msg.Cmd.StatusOrLen = (_u16)DUMMY_BUF_SIZE; - Msg.Cmd.FamilyAndFlags = (SL_AF_INET << 4); - - RetVal = _SlDrvCmdSend_noWait((_SlCmdCtrl_t *)&_SlRecvfomCmdCtrl, &Msg, &CmdExt); - - return RetVal; -} - -/*******************************************************************************/ -/* _SlDrvOpenCtrlSocket */ -/*******************************************************************************/ -static _i16 _SlDrvOpenCtrlSocket(void) -{ - _i16 retVal; - - /* In case a control socket is already open, return. */ - if(g_pCB->MultiSelectCB.CtrlSockFD != 0xFF) - { - return 0; - } - - /* Open a local control socket */ - retVal = sl_Socket(SL_AF_INET, SL_SOCK_DGRAM, 0); - - if(retVal == SL_ERROR_BSD_ENSOCK) - { - return 0; - } - else if(retVal < 0) - { - return retVal; - } - else - { - g_pCB->MultiSelectCB.CtrlSockFD = retVal; - } - - /* Bind it to local control port */ - retVal = sl_Bind(g_pCB->MultiSelectCB.CtrlSockFD, (const SlSockAddr_t *)&_SlCtrlSockAddr, sizeof(SlSockAddrIn_t)); - - return retVal; -} - -/*******************************************************************************/ -/* _SlDrvCloseCtrlSocket */ -/*******************************************************************************/ -static _i16 _SlDrvCloseCtrlSocket(void) -{ - _i16 retVal = 0; - _i16 sockfd = 0xFF; - - /* Close the internal Control socket */ - sockfd = g_pCB->MultiSelectCB.CtrlSockFD; - - if(sockfd != 0xFF) - { - /* Close the local control socket */ - retVal = sl_Close(sockfd); - } - - g_pCB->MultiSelectCB.CtrlSockFD = 0xFF; - - if(retVal < 0) - { - return SL_ERROR_BSD_SOC_ERROR; - } - - return retVal; -} - -/*******************************************************************************/ -/* to_Msec */ -/*******************************************************************************/ -static inline _u32 to_mSec(struct SlTimeval_t* timeout) -{ - return (((slcb_GetTimestamp() / SL_TIMESTAMP_TICKS_IN_10_MILLISECONDS) * 10) + (timeout->tv_sec * 1000) + (timeout->tv_usec / 1000)); -} - -/*******************************************************************************/ -/* _SlDrvUnRegisterForSelectAsync */ -/*******************************************************************************/ -static _i16 _SlDrvUnRegisterForSelectAsync(_SlSelectEntry_t* pEntry, _u8 SelectInProgress) -{ - SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->MultiSelectCB.SelectLockObj); - - /* Clear the global select fd lists */ - g_pCB->MultiSelectCB.readsds &= ~(pEntry->readlist); - g_pCB->MultiSelectCB.writesds &= ~(pEntry->writelist); - - /* Empty the caller's table entry. */ - g_pCB->MultiSelectCB.SelectEntry[pEntry->ObjIdx] = NULL; - - if(g_pCB->MultiSelectCB.ActiveSelect == FALSE) - { - _SlDrvCloseCtrlSocket(); - } - - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - - /* Release it's pool object */ - _SlDrvReleasePoolObj(pEntry->ObjIdx); - - return SL_ERROR_BSD_SOC_ERROR; -} - -/*******************************************************************************/ -/* _SlDrvRegisterForSelectAsync */ -/*******************************************************************************/ -static _i16 _SlDrvRegisterForSelectAsync(_SlSelectEntry_t* pEntry, _SlSelectMsg_u* pMsg, struct SlTimeval_t *timeout, _u8 SelectInProgress) -{ - _SlReturnVal_t _RetVal = 0; - _u8 dummyBuf[4] = {0}; - - /* Register this caller's parameters */ - pEntry->readlist = pMsg->Cmd.ReadFds; - pEntry->writelist = pMsg->Cmd.WriteFds; - - if((pMsg->Cmd.tv_sec != 0xFFFF) && (timeout != NULL)) - { - pEntry->TimeStamp = to_mSec(timeout); - } - else - { - pEntry->TimeStamp = SELECT_NO_TIMEOUT; - } - - g_pCB->MultiSelectCB.readsds |= pMsg->Cmd.ReadFds; - g_pCB->MultiSelectCB.writesds |= pMsg->Cmd.WriteFds; - g_pCB->MultiSelectCB.SelectEntry[pEntry->ObjIdx] = pEntry; - - SL_TRACE3(DBG_MSG, MSG_312, "\n\rRegistered: Objidx:%d, sec:%d, usec%d\n\r", - pEntry->ObjIdx, pMsg->Cmd.tv_sec, pMsg->Cmd.tv_usec); - - if((!SelectInProgress) || (g_pCB->MultiSelectCB.ActiveSelect == FALSE)) - { - /* Add ctrl socket to the read list for this 'select' call */ - pMsg->Cmd.ReadFds |= CTRL_SOCK_FD; - - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - - _RetVal = _SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, pMsg, NULL); - - if((_RetVal == SL_RET_CODE_OK) && (g_pCB->MultiSelectCB.CtrlSockFD != 0xFF)) - { - /* Signal any waiting "Select" callers */ - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->MultiSelectCB.SelectSyncObj); - } - } - else - { - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); -#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) - /* Wait here to be signaled by a successfully completed select caller */ - if (_SlDrvIsSpawnOwnGlobalLock()) - { - while (TRUE) - { - /* If we are in spawn context, this is an API which was called from event handler, - read any async event and check if we got signaled */ - _SlInternalSpawnWaitForEvent(); - /* is it mine? */ - if (0 == sl_SyncObjWait(&g_pCB->MultiSelectCB.SelectSyncObj, SL_OS_NO_WAIT)) - { - break; - } - } - } - else -#endif - { - SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->MultiSelectCB.SelectSyncObj); - } - - _RetVal = sl_SendTo(g_pCB->MultiSelectCB.CtrlSockFD, - &dummyBuf[0], - sizeof(dummyBuf), - 0, - (const SlSockAddr_t *)&_SlCtrlSockRelease, - sizeof(SlSockAddrIn_t)); - } - - return _RetVal; -} - -/********************************************************************************/ -/* sl_Select */ -/* ******************************************************************************/ -_i16 sl_Select(_i16 nfds, SlFdSet_t *readsds, SlFdSet_t *writesds, SlFdSet_t *exceptsds, struct SlTimeval_t *timeout) -{ - _i16 ret; - _u8 isCaller = FALSE; - _SlSelectMsg_u Msg; - _SlSelectEntry_t SelectParams; - _u8 SelectInProgress = FALSE; - - /* verify that this API is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - _SlDrvMemZero(&Msg, sizeof(_SlSelectMsg_u)); - _SlDrvMemZero(&SelectParams, sizeof(_SlSelectEntry_t)); - - Msg.Cmd.Nfds = (_u8)nfds; - - if(readsds) - { - Msg.Cmd.ReadFds = (_u16)readsds->fd_array[0]; - } - - if(writesds) - { - Msg.Cmd.WriteFds = (_u16)writesds->fd_array[0]; - } - - if(NULL == timeout) - { - Msg.Cmd.tv_sec = 0xffff; - Msg.Cmd.tv_usec = 0xffff; - } - else - { - if(0xffff <= timeout->tv_sec) - { - Msg.Cmd.tv_sec = 0xffff; - } - else - { - Msg.Cmd.tv_sec = (_u16)timeout->tv_sec; - } - - /* this divides by 1024 to fit the result in a int16_t. - * Upon receiving, the NWP multiply this value by 1024. */ - timeout->tv_usec = (timeout->tv_usec >> 10); - - if(0xffff <= timeout->tv_usec) - { - Msg.Cmd.tv_usec = 0xffff; - } - else - { - Msg.Cmd.tv_usec = (_u16)timeout->tv_usec; - } - } - - while(FALSE == isCaller) - { - SelectParams.ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&SelectParams.Response, SELECT_ID, SL_MAX_SOCKETS); - - if(MAX_CONCURRENT_ACTIONS == SelectParams.ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - SL_DRV_OBJ_LOCK_FOREVER(&g_pCB->MultiSelectCB.SelectLockObj); - - /* Check if no other 'Select' calls are in progress */ - if(FALSE == g_pCB->MultiSelectCB.ActiveSelect) - { - g_pCB->MultiSelectCB.ActiveSelect = TRUE; - } - else - { - SelectInProgress = TRUE; - } - - if(!SelectInProgress) - { - ret = _SlDrvOpenCtrlSocket(); - - if(ret < 0) - { - _SlDrvCloseCtrlSocket(); - g_pCB->MultiSelectCB.ActiveSelect = FALSE; - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - _SlDrvReleasePoolObj(SelectParams.ObjIdx); - return ret; - } - else - { - /* All conditions are met for calling "Select" */ - isCaller = TRUE; - } - } - else if(g_pCB->MultiSelectCB.CtrlSockFD == 0xFF) - { - _SlDrvReleasePoolObj(SelectParams.ObjIdx); - - /* This is not a first select caller and all sockets are open, - * caller is expected to wait until select is inactive, - * before trying to register again. */ - g_pCB->MultiSelectCB.ActiveWaiters++; - - SL_DRV_OBJ_UNLOCK(&g_pCB->MultiSelectCB.SelectLockObj); - - /* Wait here to be signaled by a successfully completed select caller */ -#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) - if (_SlDrvIsSpawnOwnGlobalLock()) - { - while (TRUE) - { - /* If we are in spawn context, this is an API which was called from event handler, - read any async event and check if we got signaled */ - _SlInternalSpawnWaitForEvent(); - /* is it mine? */ - if (0 == sl_SyncObjWait(&g_pCB->MultiSelectCB.SelectSyncObj, SL_OS_NO_WAIT)) - { - break; - } - } - } - else -#endif - { - SL_DRV_SYNC_OBJ_WAIT_FOREVER(&g_pCB->MultiSelectCB.SelectSyncObj); - } - - - if((_i16)g_pCB->MultiSelectCB.SelectCmdResp.status != SL_RET_CODE_OK) - { - return (_i16)(g_pCB->MultiSelectCB.SelectCmdResp.status); - } - - SelectInProgress = FALSE; - } - else - { - /* All conditions are met for calling "Select" */ - isCaller = TRUE; - } - } - - /* Register this caller details for an select Async event. - * SelectLockObj is released inside this function, - * right before sending 'Select' command. */ - ret = _SlDrvRegisterForSelectAsync(&SelectParams, &Msg, timeout, SelectInProgress); - - if(ret < 0) - { - return (_SlDrvUnRegisterForSelectAsync(&SelectParams, SelectInProgress)); - } - - /* Wait here for a Async event, or command response in case select fails.*/ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(SelectParams.ObjIdx, 0, 0)); - _SlDrvReleasePoolObj(SelectParams.ObjIdx); - - ret = (_i16)g_pCB->MultiSelectCB.SelectCmdResp.status; - - if(ret == SL_RET_CODE_OK) - { - ret = (_i16)SelectParams.Response.Status; - - if(ret > SELECT_TIMEOUT) - { - if(readsds) - { - readsds->fd_array[0] = SelectParams.Response.ReadFds; - } - - if(writesds) - { - writesds->fd_array[0] = SelectParams.Response.WriteFds; - } - } - } - - return ret; -} - -#else - -/*******************************************************************************/ -/* _SlSocketHandleAsync_Select */ -/*******************************************************************************/ -_SlReturnVal_t _SlSocketHandleAsync_Select(void *pVoidBuf) -{ - SlSelectAsyncResponse_t *pMsgArgs = (SlSelectAsyncResponse_t *)_SL_RESP_ARGS_START(pVoidBuf); -#if ((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) - SlSockTriggerEvent_t SockTriggerEvent; -#endif - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - sl_Memcpy(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs, pMsgArgs, sizeof(SlSelectAsyncResponse_t)); - -#if ((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) - if(1 == _SlIsEventRegistered(SL_EVENT_HDL_SOCKET_TRIGGER)) - { - if (g_pCB->SocketTriggerSelect.Info.State == SOCK_TRIGGER_WAITING_FOR_RESP) - { - - SockTriggerEvent.Event = SL_SOCKET_TRIGGER_EVENT_SELECT; - SockTriggerEvent.EventData = 0; - - g_pCB->SocketTriggerSelect.Info.State = SOCK_TRIGGER_RESP_RECEIVED; - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - /* call the user handler */ - _SlDrvHandleSocketTriggerEvents(&SockTriggerEvent); - - return SL_OS_RET_CODE_OK; - } - else - { - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - } - } - else -#endif - { - - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - } - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return SL_OS_RET_CODE_OK; -} - -_i16 sl_Select(_i16 nfds, SlFdSet_t *readsds, SlFdSet_t *writesds, SlFdSet_t *exceptsds, struct SlTimeval_t *timeout) -{ - _SlSelectMsg_u Msg; - SlSelectAsyncResponse_t AsyncRsp; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; -#if ((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) - _u8 IsNonBlocking = FALSE; -#endif - - /* verify that this API is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - -#if ((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) - if(1 == _SlIsEventRegistered(SL_EVENT_HDL_SOCKET_TRIGGER)) - { - if( NULL != timeout ) - { - /* Set that we are in Non-Blocking mode */ - if ( (0 == timeout->tv_sec) && (0 == timeout->tv_usec) ) - { - IsNonBlocking = TRUE; - } - else - { - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - /* If there is a trigger select running in the progress abort the new blocking request */ - if (g_pCB->SocketTriggerSelect.Info.State > SOCK_TRIGGER_READY) - { - SL_DRV_PROTECTION_OBJ_UNLOCK(); - return SL_RET_CODE_SOCKET_SELECT_IN_PROGRESS_ERROR; - } - - SL_DRV_PROTECTION_OBJ_UNLOCK(); - } - - if (IsNonBlocking == TRUE) - { - /* return EAGAIN if we alreay have select trigger in progress */ - if (g_pCB->SocketTriggerSelect.Info.State == SOCK_TRIGGER_WAITING_FOR_RESP) - { - return SL_ERROR_BSD_EAGAIN; - } - /* return the stored response if already received */ - else if (g_pCB->SocketTriggerSelect.Info.State == SOCK_TRIGGER_RESP_RECEIVED) - { - if( ((_i16)g_pCB->SocketTriggerSelect.Resp.Status) >= 0 ) - { - if( readsds ) - { - readsds->fd_array[0] = g_pCB->SocketTriggerSelect.Resp.ReadFds; - } - if( writesds ) - { - writesds->fd_array[0] = g_pCB->SocketTriggerSelect.Resp.WriteFds; - } - } - - /* Now relaese the pool object */ - _SlDrvReleasePoolObj(g_pCB->SocketTriggerSelect.Info.ObjPoolIdx); - - g_pCB->SocketTriggerSelect.Info.ObjPoolIdx = MAX_CONCURRENT_ACTIONS; - - /* Reset the socket select trigger object */ - g_pCB->SocketTriggerSelect.Info.State = SOCK_TRIGGER_READY; - - return (_i16)g_pCB->SocketTriggerSelect.Resp.Status; - } - } - } - } -#endif - - Msg.Cmd.Nfds = (_u8)nfds; - Msg.Cmd.ReadFdsCount = 0; - Msg.Cmd.WriteFdsCount = 0; - - Msg.Cmd.ReadFds = 0; - Msg.Cmd.WriteFds = 0; - - - if( readsds ) - { - Msg.Cmd.ReadFds = (_u16)readsds->fd_array[0]; - } - if( writesds ) - { - Msg.Cmd.WriteFds = (_u16)writesds->fd_array[0]; - } - if( NULL == timeout ) - { - Msg.Cmd.tv_sec = 0xffff; - Msg.Cmd.tv_usec = 0xffff; - } - else - { - if( 0xffff <= timeout->tv_sec ) - { - Msg.Cmd.tv_sec = 0xffff; - } - else - { - Msg.Cmd.tv_sec = (_u16)timeout->tv_sec; - } - - /* convert to milliseconds */ - timeout->tv_usec = timeout->tv_usec >> 10; - - if( 0xffff <= timeout->tv_usec ) - { - Msg.Cmd.tv_usec = 0xffff; - } - else - { - Msg.Cmd.tv_usec = (_u16)timeout->tv_usec; - } - - } - - /* Use Obj to issue the command, if not available try later */ - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, SELECT_ID, SL_MAX_SOCKETS); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - /* send the command */ - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL)); - - if(SL_OS_RET_CODE_OK == (_i16)Msg.Rsp.status) - { - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); - - Msg.Rsp.status = (_i16)AsyncRsp.Status; - - /* this code handles the socket trigger mode case */ -#if((defined(SL_RUNTIME_EVENT_REGISTERATION) || defined(slcb_SocketTriggerEventHandler))) - if(1 == _SlIsEventRegistered(SL_EVENT_HDL_SOCKET_TRIGGER)) - { - /* if no data returned and we are in trigger mode, - send another select cmd but now with timeout infinite, - and return immediately with EAGAIN to the user */ - if ((IsNonBlocking == TRUE) && (AsyncRsp.Status == 0)) - { - /* set the select trigger-in-progress bit */ - g_pCB->SocketTriggerSelect.Info.State = SOCK_TRIGGER_WAITING_FOR_RESP; - - Msg.Cmd.tv_sec = 0xffff; - Msg.Cmd.tv_usec = 0xffff; - - /* Release pool object and try to take another call */ - _SlDrvReleasePoolObj(ObjIdx); - - /* Use Obj to issue the command, if not available try later */ - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&g_pCB->SocketTriggerSelect.Resp, SELECT_ID, SL_MAX_SOCKETS); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - /* Save the pool index to be released only after the user read the response */ - g_pCB->SocketTriggerSelect.Info.ObjPoolIdx = ObjIdx; - - /* send the command */ - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlSelectCmdCtrl, &Msg, NULL)); - return SL_ERROR_BSD_EAGAIN; - - } - } -#endif - - if( ((_i16)Msg.Rsp.status) >= 0 ) - { - if( readsds ) - { - readsds->fd_array[0] = AsyncRsp.ReadFds; - } - if( writesds ) - { - writesds->fd_array[0] = AsyncRsp.WriteFds; - } - } - } - - _SlDrvReleasePoolObj(ObjIdx); - return (_i16)Msg.Rsp.status; -} - -#endif /* defined(SL_PLATFORM_MULTI_THREADED) || !defined(slcb_SocketTriggerEventHandler) */ -#endif /* _SL_INCLUDE_FUNC(sl_Select) */ - -/*******************************************************************************/ -/* sl_StartTLS */ -/*******************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_StartTLS) -_i16 sl_StartTLS(_i16 sd) -{ - _SlReturnVal_t RetVal; - SlSocketAsyncEvent_t AsyncRsp; - _u32 tempValue; - _i16 ObjIdx = MAX_CONCURRENT_ACTIONS; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_SOCKET); - _SlDrvMemZero(&AsyncRsp, sizeof(SlSocketAsyncEvent_t)); - - ObjIdx = _SlDrvProtectAsyncRespSetting((_u8*)&AsyncRsp, START_TLS_ID, (_u8)(sd & SL_BSD_SOCKET_ID_MASK)); - - if (MAX_CONCURRENT_ACTIONS == ObjIdx) - { - return SL_POOL_IS_EMPTY; - } - - /* send Start TLS to sl_SetSockOpt */ - RetVal = sl_SetSockOpt(sd, SL_SOL_SOCKET, SL_SO_STARTTLS, &tempValue, sizeof(tempValue)); - - if(SL_RET_CODE_OK == RetVal) - { - /* wait for async and get Data Read parameters */ - VERIFY_RET_OK(_SlDrvWaitForInternalAsyncEvent(ObjIdx,0,0)); - - VERIFY_PROTOCOL(AsyncRsp.Sd == (_u8)sd); - - /* Some of the errors retrieved from the NWP are treated as warnings, - that means that although the type is ssl notification connected secured there - can be a warning behind it, so we need to check the value as well and - retrieve it to the host */ - if ( (SL_SSL_NOTIFICATION_CONNECTED_SECURED == AsyncRsp.Type) && (AsyncRsp.Val >= 0) ) - { - RetVal = SL_RET_CODE_OK; - } - else - { - RetVal = AsyncRsp.Val; - } - } - - _SlDrvReleasePoolObj(ObjIdx); - return RetVal; -} - -/*******************************************************************************/ -/* _SlSocketHandleAsync_StartTLS */ -/*******************************************************************************/ -_SlReturnVal_t _SlSocketHandleAsync_StartTLS(void *pVoidBuf) -{ - SlSocketAsyncEvent_t *pMsgArgs = (SlSocketAsyncEvent_t *)((_u32)pVoidBuf+sizeof(_u32)); - - SL_DRV_PROTECTION_OBJ_LOCK_FOREVER(); - - VERIFY_PROTOCOL((pMsgArgs->Sd & SL_BSD_SOCKET_ID_MASK) <= SL_MAX_SOCKETS); - VERIFY_SOCKET_CB(NULL != g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs); - - ((SlSocketAsyncEvent_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Sd = pMsgArgs->Sd; - ((SlSocketAsyncEvent_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Type = pMsgArgs->Type; - ((SlSocketAsyncEvent_t *)(g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].pRespArgs))->Val = pMsgArgs->Val; - - SL_DRV_SYNC_OBJ_SIGNAL(&g_pCB->ObjPool[g_pCB->FunctionParams.AsyncExt.ActionIndex].SyncObj); - SL_DRV_PROTECTION_OBJ_UNLOCK(); - - return SL_OS_RET_CODE_OK; -} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/spawn.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/spawn.c deleted file mode 100644 index 59de8aac6a5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/spawn.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * spawn.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) - - -typedef struct -{ - _SlSyncObj_t SyncObj; - _u8 IrqWriteCnt; - _u8 IrqReadCnt; - void* pIrqFuncValue; - -#ifdef SL_PLATFORM_MULTI_THREADED - _u32 ThreadId; -#endif -}_SlInternalSpawnCB_t; - -_SlInternalSpawnCB_t g_SlInternalSpawnCB; - -_u8 _SlInternalIsItSpawnThread(_u32 ThreadId) -{ - return (ThreadId == g_SlInternalSpawnCB.ThreadId); -} - -void _SlInternalSpawnWaitForEvent(void) -{ - - sl_SyncObjWait(&g_SlInternalSpawnCB.SyncObj, SL_OS_WAIT_FOREVER); - - /* - * call the processQ function will handle the pending async - * events already read from NWP, and only wait for handling - * the events that have been read only during command execution. */ - _SlSpawnMsgListProcess(); - - /* handle IRQ requests */ - while (g_SlInternalSpawnCB.IrqWriteCnt != g_SlInternalSpawnCB.IrqReadCnt) - { - /* handle the ones that came from ISR context*/ - _SlDrvMsgReadSpawnCtx(g_SlInternalSpawnCB.pIrqFuncValue); - g_SlInternalSpawnCB.IrqReadCnt++; - } - -} - -void* _SlInternalSpawnTaskEntry() -{ - - /* create and clear the sync object */ - sl_SyncObjCreate(&g_SlInternalSpawnCB.SyncObj,"SlSpawnSync"); - sl_SyncObjWait(&g_SlInternalSpawnCB.SyncObj,SL_OS_NO_WAIT); - - g_SlInternalSpawnCB.ThreadId = 0xFFFFFFFF; - -#ifdef SL_PLATFORM_MULTI_THREADED - g_SlInternalSpawnCB.ThreadId = (_i32)pthread_self(); -#endif - - g_SlInternalSpawnCB.IrqWriteCnt = 0; - g_SlInternalSpawnCB.IrqReadCnt = 0; - g_SlInternalSpawnCB.pIrqFuncValue = NULL; - - /* here we ready to execute entries */ - while (TRUE) - { - /* wait for event */ - _SlInternalSpawnWaitForEvent(); - } -} - -_i16 _SlInternalSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags) -{ - _i16 Res = 0; - - /* Increment the counter that specifies that async event has recived - from interrupt context and should be handled by the internal spawn task */ - if ((flags & SL_SPAWN_FLAG_FROM_SL_IRQ_HANDLER) || (flags & SL_SPAWN_FLAG_FROM_CMD_CTX)) - { - g_SlInternalSpawnCB.IrqWriteCnt++; - g_SlInternalSpawnCB.pIrqFuncValue = pValue; - SL_DRV_SYNC_OBJ_SIGNAL(&g_SlInternalSpawnCB.SyncObj); - return Res; - } - else if (flags & SL_SPAWN_FLAG_FROM_CMD_PROCESS) - { - SL_DRV_SYNC_OBJ_SIGNAL(&g_SlInternalSpawnCB.SyncObj); - } - - return Res; -} - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/spawn.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/spawn.h deleted file mode 100644 index e9410bd3e56..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/spawn.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * spawn.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ -#ifndef __SPAWN_H__ -#define __SPAWN_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#if (defined (SL_PLATFORM_MULTI_THREADED)) && (!defined (SL_PLATFORM_EXTERNAL_SPAWN)) - -extern void* _SlInternalSpawnTaskEntry(); -extern _i16 _SlInternalSpawn(_SlSpawnEntryFunc_t pEntry , void* pValue , _u32 flags); -extern _u8 _SlInternalIsItSpawnThread(_u32 ThreadId); -#undef sl_Spawn -#define sl_Spawn(pEntry,pValue,flags) _SlInternalSpawn(pEntry,pValue,flags) - -#undef _SlTaskEntry -#define _SlTaskEntry _SlInternalSpawnTaskEntry - -#endif - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/wlan.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/wlan.c deleted file mode 100644 index 9f0643b6cc2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/wlan.c +++ /dev/null @@ -1,1208 +0,0 @@ -/* - * wlan.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include -#include -#include - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -#define MAX_SSID_LEN (32) -#define MAX_KEY_LEN (64) -#define MAX_USER_LEN (64) -#define MAX_ANON_USER_LEN (64) -#define MAX_SMART_CONFIG_KEY (16) - - -/***************************************************************************** -sl_WlanConnect -*****************************************************************************/ -typedef struct -{ - SlWlanConnectEapCommand_t Args; - _i8 Strings[SL_WLAN_SSID_MAX_LENGTH + MAX_KEY_LEN + MAX_USER_LEN + MAX_ANON_USER_LEN]; -}_WlanConnectCmd_t; - -typedef union -{ - _WlanConnectCmd_t Cmd; - _BasicResponse_t Rsp; -}_SlWlanConnectMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanConnect) -_i16 sl_WlanConnect(const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams) -{ - _SlWlanConnectMsg_u Msg; - _SlCmdCtrl_t CmdCtrl = {0,0,0}; - - _SlDrvMemZero(&Msg, (_u16)sizeof(_SlWlanConnectMsg_u)); - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - CmdCtrl.TxDescLen = 0;/* init */ - CmdCtrl.RxDescLen = (_SlArgSize_t)sizeof(_BasicResponse_t); - - /* verify SSID length */ - VERIFY_PROTOCOL(NameLen <= SL_WLAN_SSID_MAX_LENGTH); - /* verify SSID is not NULL */ - if( NULL == pName ) - { - return SL_INVALPARAM; - } - /* update SSID length */ - Msg.Cmd.Args.Common.SsidLen = (_u8)NameLen; - - /* Profile with no security */ - /* Enterprise security profile */ - if (NULL != pSecExtParams) - { - /* Update command opcode */ - CmdCtrl.Opcode = SL_OPCODE_WLAN_WLANCONNECTEAPCOMMAND; - CmdCtrl.TxDescLen += sizeof(SlWlanConnectEapCommand_t); - /* copy SSID */ - sl_Memcpy(EAP_SSID_STRING(&Msg), pName, NameLen); - CmdCtrl.TxDescLen += NameLen; - /* Copy password if supplied */ - if ((NULL != pSecParams) && (pSecParams->KeyLen > 0)) - { - /* update security type */ - Msg.Cmd.Args.Common.SecType = pSecParams->Type; - /* verify key length */ - if (pSecParams->KeyLen > MAX_KEY_LEN) - { - return SL_INVALPARAM; - } - /* update key length */ - Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen; - ARG_CHECK_PTR(pSecParams->Key); - /* copy key */ - sl_Memcpy(EAP_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); - CmdCtrl.TxDescLen += pSecParams->KeyLen; - } - else - { - Msg.Cmd.Args.Common.PasswordLen = 0; - } - - ARG_CHECK_PTR(pSecExtParams); - /* Update Eap bitmask */ - Msg.Cmd.Args.EapBitmask = pSecExtParams->EapMethod; - /* Update Certificate file ID index - currently not supported */ - Msg.Cmd.Args.CertIndex = pSecExtParams->CertIndex; - /* verify user length */ - if (pSecExtParams->UserLen > MAX_USER_LEN) - { - return SL_INVALPARAM; - } - Msg.Cmd.Args.UserLen = pSecExtParams->UserLen; - /* copy user name (identity) */ - if(pSecExtParams->UserLen > 0) - { - sl_Memcpy(EAP_USER_STRING(&Msg), pSecExtParams->User, pSecExtParams->UserLen); - CmdCtrl.TxDescLen += pSecExtParams->UserLen; - } - /* verify Anonymous user length */ - if (pSecExtParams->AnonUserLen > MAX_ANON_USER_LEN) - { - return SL_INVALPARAM; - } - Msg.Cmd.Args.AnonUserLen = pSecExtParams->AnonUserLen; - /* copy Anonymous user */ - if(pSecExtParams->AnonUserLen > 0) - { - sl_Memcpy(EAP_ANON_USER_STRING(&Msg), pSecExtParams->AnonUser, pSecExtParams->AnonUserLen); - CmdCtrl.TxDescLen += pSecExtParams->AnonUserLen; - } - - } - - /* Regular or open security profile */ - else - { - /* Update command opcode */ - CmdCtrl.Opcode = SL_OPCODE_WLAN_WLANCONNECTCOMMAND; - CmdCtrl.TxDescLen += sizeof(SlWlanConnectCommon_t); - /* copy SSID */ - sl_Memcpy(SSID_STRING(&Msg), pName, NameLen); - CmdCtrl.TxDescLen += NameLen; - /* Copy password if supplied */ - if( NULL != pSecParams ) - { - /* update security type */ - Msg.Cmd.Args.Common.SecType = pSecParams->Type; - /* verify key length is valid */ - if (pSecParams->KeyLen > MAX_KEY_LEN) - { - return SL_INVALPARAM; - } - /* update key length */ - Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen; - CmdCtrl.TxDescLen += pSecParams->KeyLen; - /* copy key (could be no key in case of WPS pin) */ - if( NULL != pSecParams->Key ) - { - sl_Memcpy(PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); - } - } - /* Profile with no security */ - else - { - Msg.Cmd.Args.Common.PasswordLen = 0; - Msg.Cmd.Args.Common.SecType = SL_WLAN_SEC_TYPE_OPEN; - } - } - /* If BSSID is not null, copy to buffer, otherwise set to 0 */ - if(NULL != pMacAddr) - { - sl_Memcpy(Msg.Cmd.Args.Common.Bssid, pMacAddr, sizeof(Msg.Cmd.Args.Common.Bssid)); - } - else - { - _SlDrvMemZero(Msg.Cmd.Args.Common.Bssid, (_u16)sizeof(Msg.Cmd.Args.Common.Bssid)); - } - - VERIFY_RET_OK ( _SlDrvCmdOp(&CmdCtrl, &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/*******************************************************************************/ -/* sl_Disconnect */ -/* ******************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_WlanDisconnect) -_i16 sl_WlanDisconnect(void) -{ - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - return _SlDrvBasicCmd(SL_OPCODE_WLAN_WLANDISCONNECTCOMMAND); -} -#endif - -/******************************************************************************/ -/* sl_PolicySet */ -/******************************************************************************/ -typedef union -{ - SlWlanPolicySetGet_t Cmd; - _BasicResponse_t Rsp; -}_SlPolicyMsg_u; - -#if _SL_INCLUDE_FUNC(sl_WlanPolicySet) - -static const _SlCmdCtrl_t _SlPolicySetCmdCtrl = -{ - SL_OPCODE_WLAN_POLICYSETCOMMAND, - (_SlArgSize_t)sizeof(SlWlanPolicySetGet_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_WlanPolicySet(const _u8 Type , const _u8 Policy, _u8 *pVal,const _u8 ValLen) -{ - _SlPolicyMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = ValLen; - CmdExt.pTxPayload1 = (_u8 *)pVal; - - Msg.Cmd.PolicyType = Type; - Msg.Cmd.PolicyOption = Policy; - Msg.Cmd.PolicyOptionLen = ValLen; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlPolicySetCmdCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.status; -} -#endif - - -/******************************************************************************/ -/* sl_PolicyGet */ -/******************************************************************************/ -typedef union -{ - SlWlanPolicySetGet_t Cmd; - SlWlanPolicySetGet_t Rsp; -}_SlPolicyGetMsg_u; - -#if _SL_INCLUDE_FUNC(sl_WlanPolicyGet) - -static const _SlCmdCtrl_t _SlPolicyGetCmdCtrl = -{ - SL_OPCODE_WLAN_POLICYGETCOMMAND, - (_SlArgSize_t)sizeof(SlWlanPolicySetGet_t), - (_SlArgSize_t)sizeof(SlWlanPolicySetGet_t) -}; - -_i16 sl_WlanPolicyGet(const _u8 Type ,_u8 *pPolicy,_u8 *pVal,_u8 *pValLen) -{ - _SlPolicyGetMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - if (*pValLen == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)(*pValLen); - CmdExt.pRxPayload = pVal; - - Msg.Cmd.PolicyType = Type; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlPolicyGetCmdCtrl, &Msg, &CmdExt)); - - - if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *pValLen = Msg.Rsp.PolicyOptionLen; - return SL_ESMALLBUF; - } - else - { - /* no pointer valus, fill the results into _i8 */ - *pValLen = (_u8)CmdExt.ActualRxPayloadLen; - *pPolicy = Msg.Rsp.PolicyOption; - - if( 0 == CmdExt.ActualRxPayloadLen ) - { - *pValLen = 1; - } - - } - return (_i16)SL_OS_RET_CODE_OK; -} -#endif - - -/*******************************************************************************/ -/* sl_ProfileAdd */ -/*******************************************************************************/ -typedef struct -{ - SlWlanAddGetEapProfile_t Args; - _i8 Strings[SL_WLAN_SSID_MAX_LENGTH + MAX_KEY_LEN + MAX_USER_LEN + MAX_ANON_USER_LEN]; -}_SlProfileParams_t; - -typedef union -{ - _SlProfileParams_t Cmd; - _BasicResponse_t Rsp; -}_SlProfileAddMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanProfileAdd) -_i16 sl_WlanProfileAdd(const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams,const _u32 Priority,const _u32 Options) -{ - _SlProfileAddMsg_u Msg; - _SlCmdCtrl_t CmdCtrl = {0,0,0}; - CmdCtrl.TxDescLen = 0;/* init */ - CmdCtrl.RxDescLen = (_SlArgSize_t)(sizeof(_BasicResponse_t)); - - - /* Options parameter is currently not in use */ - (void)Options; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - _SlDrvMemZero(&Msg,sizeof(_SlProfileAddMsg_u)); - - /* update priority */ - Msg.Cmd.Args.Common.Priority = (_u8)Priority; - /* verify SSID is not NULL */ - if( NULL == pName ) - { - return SL_INVALPARAM; - } - /* verify SSID length */ - VERIFY_PROTOCOL(NameLen <= SL_WLAN_SSID_MAX_LENGTH); - /* update SSID length */ - Msg.Cmd.Args.Common.SsidLen = (_u8)NameLen; - - /* Enterprise security profile */ - if (NULL != pSecExtParams) - { - /* Update command opcode */ - CmdCtrl.Opcode = SL_OPCODE_WLAN_EAP_PROFILEADDCOMMAND; - CmdCtrl.TxDescLen += sizeof(SlWlanAddGetEapProfile_t); - - /* copy SSID */ - sl_Memcpy(EAP_PROFILE_SSID_STRING(&Msg), pName, NameLen); - CmdCtrl.TxDescLen += NameLen; - - /* Copy password if supplied */ - if ((NULL != pSecParams) && (pSecParams->KeyLen > 0)) - { - /* update security type */ - Msg.Cmd.Args.Common.SecType = (_i8)(pSecParams->Type); - - if( SL_WLAN_SEC_TYPE_WEP == Msg.Cmd.Args.Common.SecType ) - { - Msg.Cmd.Args.Common.WepKeyId = 0; - } - - /* verify key length */ - if (pSecParams->KeyLen > MAX_KEY_LEN) - { - return SL_INVALPARAM; - } - VERIFY_PROTOCOL(pSecParams->KeyLen <= MAX_KEY_LEN); - /* update key length */ - Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen; - CmdCtrl.TxDescLen += pSecParams->KeyLen; - ARG_CHECK_PTR(pSecParams->Key); - /* copy key */ - sl_Memcpy(EAP_PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); - } - else - { - Msg.Cmd.Args.Common.PasswordLen = 0; - } - - ARG_CHECK_PTR(pSecExtParams); - /* Update Eap bitmask */ - Msg.Cmd.Args.EapBitmask = pSecExtParams->EapMethod; - /* Update Certificate file ID index - currently not supported */ - Msg.Cmd.Args.CertIndex = pSecExtParams->CertIndex; - /* verify user length */ - if (pSecExtParams->UserLen > MAX_USER_LEN) - { - return SL_INVALPARAM; - } - Msg.Cmd.Args.UserLen = pSecExtParams->UserLen; - /* copy user name (identity) */ - if(pSecExtParams->UserLen > 0) - { - sl_Memcpy(EAP_PROFILE_USER_STRING(&Msg), pSecExtParams->User, pSecExtParams->UserLen); - CmdCtrl.TxDescLen += pSecExtParams->UserLen; - } - - /* verify Anonymous user length (for tunneled) */ - if (pSecExtParams->AnonUserLen > MAX_ANON_USER_LEN) - { - return SL_INVALPARAM; - } - Msg.Cmd.Args.AnonUserLen = pSecExtParams->AnonUserLen; - - /* copy Anonymous user */ - if(pSecExtParams->AnonUserLen > 0) - { - sl_Memcpy(EAP_PROFILE_ANON_USER_STRING(&Msg), pSecExtParams->AnonUser, pSecExtParams->AnonUserLen); - CmdCtrl.TxDescLen += pSecExtParams->AnonUserLen; - } - - } - /* Regular or open security profile */ - else - { - /* Update command opcode */ - CmdCtrl.Opcode = SL_OPCODE_WLAN_PROFILEADDCOMMAND; - /* update commnad length */ - CmdCtrl.TxDescLen += sizeof(SlWlanAddGetProfile_t); - - if (NULL != pName) - { - /* copy SSID */ - sl_Memcpy(PROFILE_SSID_STRING(&Msg), pName, NameLen); - CmdCtrl.TxDescLen += NameLen; - } - - /* Copy password if supplied */ - if( NULL != pSecParams ) - { - /* update security type */ - Msg.Cmd.Args.Common.SecType = (_i8)(pSecParams->Type); - - if( SL_WLAN_SEC_TYPE_WEP == Msg.Cmd.Args.Common.SecType ) - { - Msg.Cmd.Args.Common.WepKeyId = 0; - } - - /* verify key length */ - if (pSecParams->KeyLen > MAX_KEY_LEN) - { - return SL_INVALPARAM; - } - /* update key length */ - Msg.Cmd.Args.Common.PasswordLen = pSecParams->KeyLen; - CmdCtrl.TxDescLen += pSecParams->KeyLen; - /* copy key (could be no key in case of WPS pin) */ - if( NULL != pSecParams->Key ) - { - sl_Memcpy(PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); - } - } - else - { - Msg.Cmd.Args.Common.SecType = SL_WLAN_SEC_TYPE_OPEN; - Msg.Cmd.Args.Common.PasswordLen = 0; - } - } - - /* If BSSID is not null, copy to buffer, otherwise set to 0 */ - if(NULL != pMacAddr) - { - sl_Memcpy(Msg.Cmd.Args.Common.Bssid, pMacAddr, sizeof(Msg.Cmd.Args.Common.Bssid)); - } - else - { - _SlDrvMemZero(Msg.Cmd.Args.Common.Bssid, (_u16)sizeof(Msg.Cmd.Args.Common.Bssid)); - } - - VERIFY_RET_OK(_SlDrvCmdOp(&CmdCtrl, &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif - - -/*******************************************************************************/ -/* sl_ProfileUpdate */ -/*******************************************************************************/ - -typedef struct -{ - SlWlanUpdateProfile_t Args; - _i8 Strings[MAX_SSID_LEN + MAX_KEY_LEN + MAX_USER_LEN + MAX_ANON_USER_LEN]; -}_SlProfileUpdateParams_t; - -typedef union -{ - _SlProfileUpdateParams_t Cmd; - _BasicResponse_t Rsp; -}_SlProfileUpdateMsg_u; - -#if _SL_INCLUDE_FUNC(sl_WlanProfileUpdate) -_i16 sl_WlanProfileUpdate(const _u32 Index, const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams,const _u32 Priority) -{ - _SlProfileUpdateMsg_u Msg; - _SlCmdCtrl_t CmdCtrl = {0,0,0}; - CmdCtrl.TxDescLen = 0;/* init */ - CmdCtrl.RxDescLen = (_SlArgSize_t)(sizeof(_BasicResponse_t)); - - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - _SlDrvMemZero(&Msg,sizeof(_SlProfileUpdateParams_t)); - - Msg.Cmd.Args.Index = Index; - /* update priority */ - Msg.Cmd.Args.Priority = (_u8)Priority; - - /* verify SSID length */ - VERIFY_PROTOCOL(NameLen <= MAX_SSID_LEN); - /* update SSID length */ - Msg.Cmd.Args.SsidLen = (_u8)NameLen; - - - /* Enterprise security profile */ - if (NULL != pSecExtParams) - { - /* Update command opcode */ - CmdCtrl.Opcode = SL_OPCODE_WLAN_PROFILEEAPUPDATECOMMAND; - CmdCtrl.TxDescLen += sizeof(SlWlanUpdateProfile_t); - - /* If SSID is supplied, copy it */ - if (NULL != pName) - { - sl_Memcpy(UPDATE_PROFILE_SSID_STRING(&Msg), pName, NameLen); - CmdCtrl.TxDescLen += NameLen; - } - else - { - Msg.Cmd.Args.SsidLen = 0; - } - - - /* Copy password if supplied */ - if ((NULL != pSecParams) && (pSecParams->KeyLen > 0)) - { - /* update security type */ - Msg.Cmd.Args.SecType = (_i8)(pSecParams->Type); - - if( SL_WLAN_SEC_TYPE_WEP == Msg.Cmd.Args.SecType ) - { - Msg.Cmd.Args.WepKeyId = 0; - } - - /* verify key length */ - if (pSecParams->KeyLen > MAX_KEY_LEN) - { - return SL_INVALPARAM; - } - VERIFY_PROTOCOL(pSecParams->KeyLen <= MAX_KEY_LEN); - /* update key length */ - Msg.Cmd.Args.PasswordLen = pSecParams->KeyLen; - CmdCtrl.TxDescLen += pSecParams->KeyLen; - ARG_CHECK_PTR(pSecParams->Key); - /* copy key */ - sl_Memcpy(UPDATE_PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); - } - else - { - Msg.Cmd.Args.PasswordLen = 0; - } - - ARG_CHECK_PTR(pSecExtParams); - /* Update Eap bitmask */ - Msg.Cmd.Args.EapBitmask = pSecExtParams->EapMethod; - /* Update Certificate file ID index - currently not supported */ - Msg.Cmd.Args.CertIndex = pSecExtParams->CertIndex; - /* verify user length */ - if (pSecExtParams->UserLen > MAX_USER_LEN) - { - return SL_INVALPARAM; - } - Msg.Cmd.Args.UserLen = pSecExtParams->UserLen; - /* copy user name (identity) */ - if(pSecExtParams->UserLen > 0) - { - sl_Memcpy(UPDATE_PROFILE_USER_STRING(&Msg), pSecExtParams->User, pSecExtParams->UserLen); - CmdCtrl.TxDescLen += pSecExtParams->UserLen; - } - - /* verify Anonymous user length (for tunneled) */ - if (pSecExtParams->AnonUserLen > MAX_ANON_USER_LEN) - { - return SL_INVALPARAM; - } - Msg.Cmd.Args.AnonUserLen = pSecExtParams->AnonUserLen; - - /* copy Anonymous user */ - if(pSecExtParams->AnonUserLen > 0) - { - sl_Memcpy(UPDATE_PROFILE_ANON_USER_STRING(&Msg), pSecExtParams->AnonUser, pSecExtParams->AnonUserLen); - CmdCtrl.TxDescLen += pSecExtParams->AnonUserLen; - } - - } - /* Regular or open security profile */ - else - { - /* Update command opcode */ - CmdCtrl.Opcode = SL_OPCODE_WLAN_PROFILEUPDATECOMMAND; - /* update commnad length */ - CmdCtrl.TxDescLen += sizeof(SlWlanUpdateProfile_t); - - if (NULL != pName) - { - /* copy SSID */ - sl_Memcpy(UPDATE_PROFILE_SSID_STRING(&Msg), pName, NameLen); - CmdCtrl.TxDescLen += NameLen; - } - else - { - Msg.Cmd.Args.SsidLen = 0; - } - - /* Copy password if supplied */ - if( NULL != pSecParams ) - { - /* update security type */ - Msg.Cmd.Args.SecType = (_i8)(pSecParams->Type); - - if( SL_WLAN_SEC_TYPE_WEP == Msg.Cmd.Args.SecType ) - { - Msg.Cmd.Args.WepKeyId = 0; - } - - /* verify key length */ - if (pSecParams->KeyLen > MAX_KEY_LEN) - { - return SL_INVALPARAM; - } - /* update key length */ - Msg.Cmd.Args.PasswordLen = pSecParams->KeyLen; - CmdCtrl.TxDescLen += pSecParams->KeyLen; - /* copy key (could be no key in case of WPS pin) */ - if( NULL != pSecParams->Key ) - { - sl_Memcpy(UPDATE_PROFILE_PASSWORD_STRING(&Msg), pSecParams->Key, pSecParams->KeyLen); - } - } - else - { - Msg.Cmd.Args.SecType = SL_WLAN_SEC_TYPE_OPEN; - Msg.Cmd.Args.PasswordLen = 0; - } - - } - - - /* If BSSID is not null, copy to buffer, otherwise set to 0 */ - if(NULL != pMacAddr) - { - sl_Memcpy(Msg.Cmd.Args.Bssid, pMacAddr, sizeof(Msg.Cmd.Args.Bssid)); - } - else - { - _SlDrvMemZero(Msg.Cmd.Args.Bssid, (_u16)sizeof(Msg.Cmd.Args.Bssid)); - } - - VERIFY_RET_OK(_SlDrvCmdOp(&CmdCtrl, &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif -/*******************************************************************************/ -/* sl_ProfileGet */ -/*******************************************************************************/ -typedef union -{ - SlWlanProfileDelGetCommand_t Cmd; - _SlProfileParams_t Rsp; -}_SlProfileGetMsg_u; - -#if _SL_INCLUDE_FUNC(sl_WlanProfileGet) - -static const _SlCmdCtrl_t _SlProfileGetCmdCtrl = -{ - SL_OPCODE_WLAN_PROFILEGETCOMMAND, - (_SlArgSize_t)sizeof(SlWlanProfileDelGetCommand_t), - (_SlArgSize_t)sizeof(_SlProfileParams_t) -}; - -_i16 sl_WlanProfileGet(const _i16 Index,_i8* pName, _i16 *pNameLen, _u8 *pMacAddr, SlWlanSecParams_t* pSecParams, SlWlanGetSecParamsExt_t* pEntParams, _u32 *pPriority) -{ - _SlProfileGetMsg_u Msg; - Msg.Cmd.Index = (_u8)Index; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlProfileGetCmdCtrl, &Msg, NULL)); - - pSecParams->Type = (_u8)(Msg.Rsp.Args.Common.SecType); - if (Msg.Rsp.Args.Common.SecType >= 0) - { - /* since password is not transferred in getprofile, password length should always be zero */ - pSecParams->KeyLen = Msg.Rsp.Args.Common.PasswordLen; - if (NULL != pEntParams) - { - pEntParams->EapMethod = Msg.Rsp.Args.EapBitmask; - pEntParams->UserLen = Msg.Rsp.Args.UserLen; - /* copy user name */ - if (pEntParams->UserLen > 0) - { - sl_Memcpy(pEntParams->User, EAP_PROFILE_USER_STRING(&Msg), pEntParams->UserLen); - } - pEntParams->AnonUserLen = Msg.Rsp.Args.AnonUserLen; - /* copy anonymous user name */ - if (pEntParams->AnonUserLen > 0) - { - sl_Memcpy(pEntParams->AnonUser, EAP_PROFILE_ANON_USER_STRING(&Msg), pEntParams->AnonUserLen); - } - } - - *pNameLen = (_i16)(Msg.Rsp.Args.Common.SsidLen); - *pPriority = Msg.Rsp.Args.Common.Priority; - - if (NULL != Msg.Rsp.Args.Common.Bssid) - { - sl_Memcpy(pMacAddr, Msg.Rsp.Args.Common.Bssid, sizeof(Msg.Rsp.Args.Common.Bssid)); - } - - sl_Memset(pName, 0, SL_WLAN_SSID_MAX_LENGTH); - sl_Memcpy(pName, EAP_PROFILE_SSID_STRING(&Msg), *pNameLen); - } - return (_i16)Msg.Rsp.Args.Common.SecType; -} -#endif -/*******************************************************************************/ -/* sl_ProfileDel */ -/*******************************************************************************/ -typedef union -{ - SlWlanProfileDelGetCommand_t Cmd; - _BasicResponse_t Rsp; -}_SlProfileDelMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanProfileDel) - -static const _SlCmdCtrl_t _SlProfileDelCmdCtrl = -{ - SL_OPCODE_WLAN_PROFILEDELCOMMAND, - (_SlArgSize_t)sizeof(SlWlanProfileDelGetCommand_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_WlanProfileDel(const _i16 Index) -{ - _SlProfileDelMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - Msg.Cmd.Index = (_u8)Index; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlProfileDelCmdCtrl, &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif - - -/******************************************************************************/ -/* sl_WlanGetNetworkList */ -/******************************************************************************/ -typedef union -{ - SlWlanGetNetworkListCommand_t Cmd; - _WlanGetNetworkListResponse_t Rsp; -}_SlWlanGetNetworkListMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanGetNetworkList) - -static const _SlCmdCtrl_t _SlWlanGetNetworkListCtrl = -{ - SL_OPCODE_WLAN_SCANRESULTSGETCOMMAND, - (_SlArgSize_t)sizeof(SlWlanGetNetworkListCommand_t), - (_SlArgSize_t)sizeof(_WlanGetNetworkListResponse_t) -}; - -_i16 sl_WlanGetNetworkList(const _u8 Index,const _u8 Count, SlWlanNetworkEntry_t *pEntries) -{ - _i16 retVal = 0; - _SlWlanGetNetworkListMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - if (Count == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)(sizeof(SlWlanNetworkEntry_t)*(Count)); - CmdExt.pRxPayload = (_u8 *)pEntries; - - Msg.Cmd.Index = Index; - Msg.Cmd.Count = Count; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanGetNetworkListCtrl, &Msg, &CmdExt)); - retVal = Msg.Rsp.status; - - return (_i16)retVal; -} -#endif - -/******************************************************************************/ -/* sl_WlanGetExtNetworkList */ -/******************************************************************************/ -typedef union -{ - SlWlanGetExtNetworkListCommand_t Cmd; - _WlanGetExtNetworkListResponse_t Rsp; -}_SlWlanGetExtNetworkListMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanGetExtNetworkList) - -static const _SlCmdCtrl_t _SlWlanGetExtNetworkListCtrl = -{ - SL_OPCODE_WLAN_EXTSCANRESULTSGETCOMMAND, - (_SlArgSize_t)sizeof(SlWlanGetExtNetworkListCommand_t), - (_SlArgSize_t)sizeof(_WlanGetExtNetworkListResponse_t) -}; - -_i16 sl_WlanGetExtNetworkList(const _u8 Index,const _u8 Count, SlWlanExtNetworkEntry_t *pEntries) -{ - _i16 retVal = 0; - _SlWlanGetExtNetworkListMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - if (Count == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)(sizeof(SlWlanExtNetworkEntry_t)*(Count)); - CmdExt.pRxPayload = (_u8 *)pEntries; - - Msg.Cmd.Index = Index; - Msg.Cmd.Count = Count; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanGetExtNetworkListCtrl, &Msg, &CmdExt)); - retVal = Msg.Rsp.status; - - return (_i16)retVal; -} -#endif - - -/******************************************************************************/ -/* RX filters message command response structures */ -/******************************************************************************/ - - -typedef union -{ - SlWlanRxFilterAddCommand_t Cmd; - SlWlanRxFilterAddCommandReponse_t Rsp; -}_SlWlanRxFilterAddMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanRxFilterAdd) - -static const _SlCmdCtrl_t _SlWlanRxFilterAddtCmdCtrl = -{ - SL_OPCODE_WLAN_WLANRXFILTERADDCOMMAND, - (_SlArgSize_t)sizeof(SlWlanRxFilterAddCommand_t), - (_SlArgSize_t)sizeof(SlWlanRxFilterAddCommandReponse_t) -}; - - -/***************************************************************************** - RX filters -*****************************************************************************/ -_i16 sl_WlanRxFilterAdd(SlWlanRxFilterRuleType_t RuleType, - SlWlanRxFilterFlags_u Flags, - const SlWlanRxFilterRule_u* const pRule, - const SlWlanRxFilterTrigger_t* const pTrigger, - const SlWlanRxFilterAction_t* const pAction, - SlWlanRxFilterID_t* pFilterId) -{ - _SlWlanRxFilterAddMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - Msg.Cmd.RuleType = RuleType; - /* filterId is zero */ - Msg.Cmd.FilterId = 0; - Msg.Cmd.Flags = Flags; - sl_Memcpy( &(Msg.Cmd.Rule), pRule, sizeof(SlWlanRxFilterRule_u) ); - sl_Memcpy( &(Msg.Cmd.Trigger), pTrigger, sizeof(SlWlanRxFilterTrigger_t) ); - sl_Memcpy( &(Msg.Cmd.Action), pAction, sizeof(SlWlanRxFilterAction_t) ); - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanRxFilterAddtCmdCtrl, &Msg, NULL) ); - *pFilterId = Msg.Rsp.FilterId; - return (_i16)Msg.Rsp.Status; -} -#endif - - -/*******************************************************************************/ -/* sl_WlanRxStatStart */ -/*******************************************************************************/ -#if _SL_INCLUDE_FUNC(sl_WlanRxStatStart) -_i16 sl_WlanRxStatStart(void) -{ - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - return _SlDrvBasicCmd(SL_OPCODE_WLAN_STARTRXSTATCOMMAND); -} -#endif - -#if _SL_INCLUDE_FUNC(sl_WlanRxStatStop) -_i16 sl_WlanRxStatStop(void) -{ - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - return _SlDrvBasicCmd(SL_OPCODE_WLAN_STOPRXSTATCOMMAND); -} -#endif - -#if _SL_INCLUDE_FUNC(sl_WlanRxStatGet) -_i16 sl_WlanRxStatGet(SlWlanGetRxStatResponse_t *pRxStat,const _u32 Flags) -{ - _SlCmdCtrl_t CmdCtrl = {SL_OPCODE_WLAN_GETRXSTATCOMMAND, 0, (_SlArgSize_t)sizeof(SlWlanGetRxStatResponse_t)}; - /* Flags parameter is currently not in use */ - (void)Flags; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - _SlDrvMemZero(pRxStat, (_u16)sizeof(SlWlanGetRxStatResponse_t)); - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&CmdCtrl, pRxStat, NULL)); - - return 0; -} -#endif - -/******************************************************************************/ -/* sl_WlanProvisioning */ -/******************************************************************************/ - -typedef struct -{ - SlWlanSmartConfigParams_t Args; - _i8 Key[MAX_SMART_CONFIG_KEY]; /* public key + groupId1 key + groupId2 key */ -}_SlSmartConfigArgs_t; - -typedef struct -{ - SlWlanProvisioningParams_t ProvParams; - _SlSmartConfigArgs_t SmartConfigParams; -}_SlProvisioning_t; - -typedef union -{ - _SlProvisioning_t Cmd; - _BasicResponse_t Rsp; -}_SlProvisioningStartMsg_u; - -#if _SL_INCLUDE_FUNC(sl_WlanProvisioning) - -const _SlCmdCtrl_t _SlProvisioningCmdCtrl = -{ - SL_OPCODE_WLAN_PROVISIONING_COMMAND, - sizeof(_SlProvisioning_t), - sizeof(_BasicResponse_t) -}; - -_i16 sl_WlanProvisioning(_u8 ProvisioningCmd, _u8 RequestedRoleAfterSuccess, _u16 InactivityTimeoutSec, char *pSmartConfigKey, _u32 Flags) -{ - _SlProvisioningStartMsg_u Msg; - - /* Verify if we can send this command to the NWP - We can send only prov. stop command if command is not allowed */ - if ((!SL_IS_COMMAND_ALLOWED) && (!SL_IS_PROVISIONING_ACTIVE) && (InactivityTimeoutSec != 0)) - { - /* return with the correct error code */ - return _SlDrvDriverIsApiAllowed(SL_OPCODE_SILO_WLAN); - } - - /* If there is an API in progress and the timeout is not zero (it means the - command is not prov. stop) then abort and return an error code */ - if (_SlDrvIsApiInProgress() && (InactivityTimeoutSec !=0)) - { - return SL_RET_CODE_API_COMMAND_IN_PROGRESS; - } - - _SlDrvMemZero(&Msg, (_u16)sizeof (_SlProvisioningStartMsg_u)); - - Msg.Cmd.ProvParams.ProvisioningCmd = (_u8)ProvisioningCmd; - Msg.Cmd.ProvParams.RequestedRoleAfterSuccess = (_u8)RequestedRoleAfterSuccess; - Msg.Cmd.ProvParams.InactivityTimeoutSec = (_u16)InactivityTimeoutSec; - Msg.Cmd.ProvParams.Flags = Flags; - - /* Smart Config parameters */ - if (NULL != pSmartConfigKey) - { - Msg.Cmd.SmartConfigParams.Args.GroupIdBitmask = SL_WLAN_SMART_CONFIG_DEFAULT_GROUP; - Msg.Cmd.SmartConfigParams.Args.Cipher = SL_WLAN_SMART_CONFIG_DEFAULT_CIPHER; - Msg.Cmd.SmartConfigParams.Args.PublicKeyLen = SL_WLAN_SMART_CONFIG_KEY_LENGTH; - - /* copy keys (if exist) after command (one after another) */ - sl_Memcpy(Msg.Cmd.SmartConfigParams.Key, pSmartConfigKey, SL_WLAN_SMART_CONFIG_KEY_LENGTH); - } - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlProvisioningCmdCtrl , &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/*******************************************************************************/ -/* sl_WlanSetMode */ -/*******************************************************************************/ -typedef union -{ - SlWlanSetMode_t Cmd; - _BasicResponse_t Rsp; -}_SlwlanSetModeMsg_u; - -#if _SL_INCLUDE_FUNC(sl_WlanSetMode) - -static const _SlCmdCtrl_t _SlWlanSetModeCmdCtrl = -{ - SL_OPCODE_WLAN_SET_MODE, - (_SlArgSize_t)sizeof(SlWlanSetMode_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -/* possible values are: -WLAN_SET_STA_MODE = 1 -WLAN_SET_AP_MODE = 2 -WLAN_SET_P2P_MODE = 3 */ -_i16 sl_WlanSetMode(const _u8 Mode) -{ - _SlwlanSetModeMsg_u Msg; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - Msg.Cmd.Mode = Mode; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanSetModeCmdCtrl , &Msg, NULL)); - - return (_i16)Msg.Rsp.status; -} -#endif - -/*******************************************************************************/ -/* sl_WlanSet */ -/* ******************************************************************************/ -typedef union -{ - SlWlanCfgSetGet_t Cmd; - _BasicResponse_t Rsp; -}_SlWlanCfgSetMsg_u; - - -#if _SL_INCLUDE_FUNC(sl_WlanSet) - -static const _SlCmdCtrl_t _SlWlanCfgSetCmdCtrl = -{ - SL_OPCODE_WLAN_CFG_SET, - (_SlArgSize_t)sizeof(SlWlanCfgSetGet_t), - (_SlArgSize_t)sizeof(_BasicResponse_t) -}; - -_i16 sl_WlanSet(const _u16 ConfigId ,const _u16 ConfigOpt,const _u16 ConfigLen,const _u8 *pValues) -{ - _SlWlanCfgSetMsg_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.TxPayload1Len = (_u16)((ConfigLen+3) & (~3)); - CmdExt.pTxPayload1 = (_u8 *)pValues; - - Msg.Cmd.ConfigId = ConfigId; - Msg.Cmd.ConfigLen = ConfigLen; - Msg.Cmd.ConfigOpt = ConfigOpt; - - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanCfgSetCmdCtrl, &Msg, &CmdExt)); - - return (_i16)Msg.Rsp.status; -} -#endif - - -/******************************************************************************/ -/* sl_WlanGet */ -/******************************************************************************/ -typedef union -{ - SlWlanCfgSetGet_t Cmd; - SlWlanCfgSetGet_t Rsp; -}_SlWlanCfgMsgGet_u; - -#if _SL_INCLUDE_FUNC(sl_WlanGet) - -static const _SlCmdCtrl_t _SlWlanCfgGetCmdCtrl = -{ - SL_OPCODE_WLAN_CFG_GET, - (_SlArgSize_t)sizeof(SlWlanCfgSetGet_t), - (_SlArgSize_t)sizeof(SlWlanCfgSetGet_t) -}; - -_i16 sl_WlanGet(const _u16 ConfigId, _u16 *pConfigOpt,_u16 *pConfigLen, _u8 *pValues) -{ - _SlWlanCfgMsgGet_u Msg; - _SlCmdExt_t CmdExt; - - /* verify that this api is allowed. if not allowed then - ignore the API execution and return immediately with an error */ - VERIFY_API_ALLOWED(SL_OPCODE_SILO_WLAN); - - if (*pConfigLen == 0) - { - return SL_EZEROLEN; - } - - _SlDrvResetCmdExt(&CmdExt); - CmdExt.RxPayloadLen = (_i16)*pConfigLen; - CmdExt.pRxPayload = (_u8 *)pValues; - Msg.Cmd.ConfigLen = *pConfigLen; - Msg.Cmd.ConfigId = ConfigId; - if( pConfigOpt ) - { - Msg.Cmd.ConfigOpt = (_u16)*pConfigOpt; - } - VERIFY_RET_OK(_SlDrvCmdOp((_SlCmdCtrl_t *)&_SlWlanCfgGetCmdCtrl, &Msg, &CmdExt)); - - if( pConfigOpt ) - { - *pConfigOpt = (_u8)Msg.Rsp.ConfigOpt; - } - if (CmdExt.RxPayloadLen < CmdExt.ActualRxPayloadLen) - { - *pConfigLen = (_u8)CmdExt.RxPayloadLen; - return SL_ESMALLBUF; - } - else - { - *pConfigLen = (_u8)CmdExt.ActualRxPayloadLen; - } - - return (_i16)Msg.Rsp.Status; -} -#endif diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/wlanconfig.c b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/wlanconfig.c deleted file mode 100644 index b373d31b639..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/source/wlanconfig.c +++ /dev/null @@ -1,246 +0,0 @@ -/* - * wlan.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - - -extern SlWifiCC32XXConfig_t SimpleLinkWifiCC32XX_config; - -_i32 sl_WifiConfig() -{ - _u8 ucConfigOpt; - _u16 uIPMode; - _i32 RetVal = -1; - _i32 RetVal_stop = -1; - _i32 Mode = -1; - SlNetCfgIpV4Args_t *ipV4 = NULL; - SlNetCfgIpV4Args_t localIpV4; - _u16 ipConfigSize = 0; - - - /* Turn NWP on */ - Mode = sl_Start(NULL, NULL, NULL); - if (Mode < 0) - { - return Mode; - } - - while (1) - { - if ((SimpleLinkWifiCC32XX_config.Mode != SL_DEVICE_SYSCONFIG_AS_CONFIGURED) && (SimpleLinkWifiCC32XX_config.Mode != Mode)) - { - /* Set NWP role */ - RetVal = sl_WlanSetMode(SimpleLinkWifiCC32XX_config.Mode); - if (RetVal < 0) - { - break; - } - - /* For changes to take affect, we restart the NWP */ - RetVal = sl_Stop(200); - if (RetVal < 0) - { - break; - } - - RetVal = sl_Start(NULL, NULL, NULL); - if (RetVal < 0) - { - break; - } - - if(SimpleLinkWifiCC32XX_config.Mode != RetVal) - { - RetVal = -1; - break; - } - } - - /* Set connection policy */ - if (SimpleLinkWifiCC32XX_config.ConnectionPolicy != SL_DEVICE_SYSCONFIG_AS_CONFIGURED) - { - RetVal = - sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION, - SimpleLinkWifiCC32XX_config.ConnectionPolicy, - NULL,0); - if (RetVal < 0) - { - break; - } - } - if (SimpleLinkWifiCC32XX_config.ProvisioningStop) - { - /* Stop Provisioning */ - RetVal = sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_STOP, - 0xFF, - 0, - NULL, - 0x0); - if (RetVal < 0) - { - break; - } - } - if (SimpleLinkWifiCC32XX_config.DeleteAllProfile) - { - /* Delete existing profiles */ - RetVal = sl_WlanProfileDel(SL_WLAN_DEL_ALL_PROFILES); - if (RetVal < 0) - { - break; - } - } - - /* Configure ipv4/DHCP */ - if (SimpleLinkWifiCC32XX_config.Ipv4Config != SL_DEVICE_SYSCONFIG_AS_CONFIGURED) - { - if (SimpleLinkWifiCC32XX_config.Mode == ROLE_STA) - { - uIPMode = SL_NETCFG_IPV4_STA_ADDR_MODE; - } - else if (SimpleLinkWifiCC32XX_config.Mode == ROLE_AP) - { - uIPMode = SL_NETCFG_IPV4_AP_ADDR_MODE; - } - if (SimpleLinkWifiCC32XX_config.Ipv4Config == SL_NETCFG_ADDR_STATIC) - { - ipV4 = &localIpV4; - ipConfigSize = sizeof(SlNetCfgIpV4Args_t); - - localIpV4.Ip = (_u32)SimpleLinkWifiCC32XX_config.Ipv4; // _u32 IP address - localIpV4.IpMask = (_u32)SimpleLinkWifiCC32XX_config.IpMask; // _u32 Subnet mask for this AP/P2P - localIpV4.IpGateway = (_u32)SimpleLinkWifiCC32XX_config.IpGateway; // _u32 Default gateway address - localIpV4.IpDnsServer = (_u32)SimpleLinkWifiCC32XX_config.IpDnsServer; // _u32 DNS server address - } - else if (SimpleLinkWifiCC32XX_config.Ipv4Config != SL_NETCFG_ADDR_DHCP) - { - RetVal = -1; - if (RetVal < 0) - { - break; - } - } - - RetVal = sl_NetCfgSet(uIPMode, SimpleLinkWifiCC32XX_config.Ipv4Config, ipConfigSize, (_u8 *)ipV4); - if (RetVal < 0) - { - break; - } - } - - /* Set scan policy */ - if (SimpleLinkWifiCC32XX_config.ScanPolicy != SL_DEVICE_SYSCONFIG_AS_CONFIGURED) - { - _u32 intervalInSeconds = SimpleLinkWifiCC32XX_config.ScanIntervalInSeconds; - ucConfigOpt = SimpleLinkWifiCC32XX_config.ScanPolicy; - RetVal = sl_WlanPolicySet(SL_WLAN_POLICY_SCAN, ucConfigOpt, (_u8 *)&intervalInSeconds, sizeof(intervalInSeconds)); - if (RetVal < 0) - { - break; - } - } - - /* Set NWP Power Management Policy */ - if (SimpleLinkWifiCC32XX_config.PMPolicy != SL_DEVICE_SYSCONFIG_AS_CONFIGURED) - { - if (SimpleLinkWifiCC32XX_config.PMPolicy != SL_WLAN_LONG_SLEEP_INTERVAL_POLICY) - { - RetVal = sl_WlanPolicySet(SL_WLAN_POLICY_PM, SimpleLinkWifiCC32XX_config.PMPolicy, NULL,0); - if (RetVal < 0) - { - break; - } - } - else - { - SlWlanPmPolicyParams_t PmPolicyParams; - memset(&PmPolicyParams,0,sizeof(SlWlanPmPolicyParams_t)); - PmPolicyParams.MaxSleepTimeMs = SimpleLinkWifiCC32XX_config.MaxSleepTimeMS; //max sleep time in mSec - RetVal = sl_WlanPolicySet(SL_WLAN_POLICY_PM, SimpleLinkWifiCC32XX_config.PMPolicy, (_u8*)&PmPolicyParams, sizeof(PmPolicyParams)); - if (RetVal < 0) - { - break; - } - } - } - - /* Set DHCP Server Configuration */ - if (SimpleLinkWifiCC32XX_config.DHCPServer) - { - SlNetAppDhcpServerBasicOpt_t dhcpParams; - _u8 outLen = sizeof(SlNetAppDhcpServerBasicOpt_t); - dhcpParams.lease_time = SimpleLinkWifiCC32XX_config.LeaseTime; // lease time (in seconds) of the IP Address - dhcpParams.ipv4_addr_start = (_u32)SimpleLinkWifiCC32XX_config.StartAddress; // first IP Address for allocation. IP Address should be set as Hex number - i.e. 0A0B0C01 for (10.11.12.1) - dhcpParams.ipv4_addr_last = (_u32)SimpleLinkWifiCC32XX_config.LastAddress; // last IP Address for allocation. IP Address should be set as Hex number - i.e. 0A0B0C01 for (10.11.12.1) - RetVal = sl_NetAppStop(SL_NETAPP_DHCP_SERVER_ID); // Stop DHCP server before settings - if (RetVal < 0) - { - break; - } - RetVal = sl_NetAppSet(SL_NETAPP_DHCP_SERVER_ID, SL_NETAPP_DHCP_SRV_BASIC_OPT, outLen, (_u8* )&dhcpParams); // set parameters - if (RetVal < 0) - { - break; - } - if (SimpleLinkWifiCC32XX_config.Mode == ROLE_AP) - { - RetVal = sl_NetAppStart(SL_NETAPP_DHCP_SERVER_ID); // Start DHCP server with new settings - if (RetVal < 0) - { - break; - } - } - } - else - { - sl_NetAppStop(SL_NETAPP_HTTP_SERVER_ID); - } - break; - } - /* Jump here if error occurred or after all the configurations was set successfully */ - /* For changes to take affect, we restart the NWP - sl_start will be call by application */ - RetVal_stop = sl_Stop(200); - if (RetVal_stop < 0) - { - return RetVal_stop; - } - return(RetVal); -} - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/trace.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/trace.h deleted file mode 100644 index d99cd6d6d5c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/trace.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * trace.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -#include - -#ifndef __SIMPLELINK_TRACE_H__ -#define __SIMPLELINK_TRACE_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#define SL_SYNC_SCAN_THRESHOLD (( _u32 )2000) - -#define _SlDrvAssert() _SlDrvHandleFatalError(SL_DEVICE_EVENT_FATAL_DRIVER_ABORT, 0, 0) - -#define _SL_ASSERT(expr) {if(!(expr)){ _SlDrvAssert();}} -#define _SL_ERROR(expr, error) {if(!(expr)){return (error);}} - -#define _SL_ASSERT_ERROR(expr, error) {if(!(expr)){_SlDrvAssert(); return (error);}} - -#define SL_HANDLING_ASSERT 2 -#define SL_HANDLING_ERROR 1 -#define SL_HANDLING_NONE 0 - -#define SL_SELF_COND_HANDLING SL_HANDLING_ASSERT -#define SL_PROTOCOL_HANDLING SL_HANDLING_ASSERT -#define SL_DRV_RET_CODE_HANDLING SL_HANDLING_ERROR -#define SL_NWP_IF_HANDLING SL_HANDLING_ASSERT -#define SL_OSI_RET_OK_HANDLING SL_HANDLING_ERROR -#define SL_MALLOC_OK_HANDLING SL_HANDLING_ASSERT -#define SL_USER_ARGS_HANDLING SL_HANDLING_ASSERT -#define SL_ERR_IN_PROGRESS_HANDLING SL_HANDLING_ERROR -#define SL_ERR_IN_API_ALLOWED SL_HANDLING_ERROR -#define SL_LOCK_OK_HANDLING SL_HANDLING_ASSERT - -#if (SL_ERR_IN_PROGRESS_HANDLING == SL_HANDLING_ERROR) -#define VERIFY_NO_ERROR_HANDLING_IN_PROGRESS() { \ - if (SL_IS_RESTART_REQUIRED) return SL_API_ABORTED; } -#else -#define VERIFY_NO_ERROR_HANDLING_IN_PROGRESS() -#endif - -#if (SL_ERR_IN_API_ALLOWED == SL_HANDLING_ERROR) -#define VERIFY_API_ALLOWED(Silo) { \ - _SlReturnVal_t status = _SlDrvDriverIsApiAllowed(Silo); \ - if ( status ) return status; } -#else -#define VERIFY_API_ALLOWED(Silo) -#endif - -#if (SL_DRV_RET_CODE_HANDLING == SL_HANDLING_ASSERT) -#define VERIFY_RET_OK(Func) {_SlReturnVal_t _RetVal = (Func); _SL_ASSERT((_SlReturnVal_t)SL_OS_RET_CODE_OK == _RetVal)} -#elif (SL_DRV_RET_CODE_HANDLING == SL_HANDLING_ERROR) -#define VERIFY_RET_OK(Func) {_SlReturnVal_t _RetVal = (Func); if (SL_OS_RET_CODE_OK != _RetVal) return (_SlReturnVal_t)_RetVal;} -#else -#define VERIFY_RET_OK(Func) (Func); -#endif - -#if (SL_PROTOCOL_HANDLING == SL_HANDLING_ASSERT) -#define VERIFY_PROTOCOL(expr) _SL_ASSERT(expr) -#elif (SL_PROTOCOL_HANDLING == SL_HANDLING_ERROR) -#define VERIFY_PROTOCOL(expr) _SL_ERROR(expr, SL_RET_CODE_PROTOCOL_ERROR) -#else -#define VERIFY_PROTOCOL(expr) -#endif - -#if (defined(PROTECT_SOCKET_ASYNC_RESP) && (SL_SELF_COND_HANDLING == SL_HANDLING_ASSERT)) -#define VERIFY_SOCKET_CB(expr) _SL_ASSERT(expr) -#elif (defined(PROTECT_SOCKET_ASYNC_RESP) && (SL_SELF_COND_HANDLING == SL_HANDLING_ERROR)) -#define VERIFY_SOCKET_CB(expr) _SL_ERROR(expr, SL_RET_CODE_SELF_ERROR) -#else -#define VERIFY_SOCKET_CB(expr) -#endif - -#if (SL_NWP_IF_HANDLING == SL_HANDLING_ASSERT) -#define NWP_IF_WRITE_CHECK(fd,pBuff,len) { _i16 RetSize, ExpSize = (_i16)(len); RetSize = sl_IfWrite((fd),(pBuff),ExpSize); _SL_ASSERT(ExpSize == RetSize)} -#define NWP_IF_READ_CHECK(fd,pBuff,len) { _i16 RetSize, ExpSize = (_i16)(len); RetSize = sl_IfRead((fd),(pBuff),ExpSize); _SL_ASSERT(ExpSize == RetSize)} -#elif (SL_NWP_IF_HANDLING == SL_HANDLING_ERROR) -#define NWP_IF_WRITE_CHECK(fd,pBuff,len) { _SL_ERROR((len == sl_IfWrite((fd),(pBuff),(len))), SL_RET_CODE_NWP_IF_ERROR);} -#define NWP_IF_READ_CHECK(fd,pBuff,len) { _SL_ERROR((len == sl_IfRead((fd),(pBuff),(len))), SL_RET_CODE_NWP_IF_ERROR);} -#else -#define NWP_IF_WRITE_CHECK(fd,pBuff,len) { sl_IfWrite((fd),(pBuff),(len));} -#define NWP_IF_READ_CHECK(fd,pBuff,len) { sl_IfRead((fd),(pBuff),(len));} -#endif - -#if (SL_OSI_RET_OK_HANDLING == SL_HANDLING_ASSERT) -#define OSI_RET_OK_CHECK(Func) {_SlReturnVal_t _RetVal = (Func); _SL_ASSERT((_SlReturnVal_t)SL_OS_RET_CODE_OK == _RetVal)} -#elif (SL_OSI_RET_OK_HANDLING == SL_HANDLING_ERROR) -#define OSI_RET_OK_CHECK(Func) {_SlReturnVal_t _RetVal = (Func); if (SL_OS_RET_CODE_OK != _RetVal) return _RetVal;} -#else -#define OSI_RET_OK_CHECK(Func) (Func); -#endif - -#if (SL_MALLOC_OK_HANDLING == SL_HANDLING_ASSERT) -#define MALLOC_OK_CHECK(Ptr) _SL_ASSERT(NULL != Ptr) -#elif (SL_MALLOC_OK_HANDLING == SL_HANDLING_ERROR) -#define MALLOC_OK_CHECK(Ptr) _SL_ERROR((NULL != Ptr), SL_RET_CODE_MALLOC_ERROR) -#else -#define MALLOC_OK_CHECK(Ptr) -#endif - - -#if (SL_LOCK_OK_HANDLING == SL_HANDLING_ASSERT) -#define LOCK_OK_CHECK(Func) {_SlReturnVal_t _RetVal = (Func); _SL_ASSERT((_SlReturnVal_t)SL_OS_RET_CODE_OK == _RetVal)} -#elif (SL_LOCK_OK_HANDLING == SL_HANDLING_ERROR) -#define LOCK_OK_CHECK(Func) {_SlReturnVal_t _RetVal = (Func); if (SL_OS_RET_CODE_OK != _RetVal) return _RetVal;} -#else -#define LOCK_OK_CHECK(Func) (Func); -#endif - - -#ifdef SL_INC_ARG_CHECK - -#if (SL_USER_ARGS_HANDLING == SL_HANDLING_ASSERT) -#define ARG_CHECK_PTR(Ptr) _SL_ASSERT(NULL != Ptr) -#elif (SL_USER_ARGS_HANDLING == SL_HANDLING_ERROR) -#define ARG_CHECK_PTR(Ptr) _SL_ERROR((NULL != Ptr), SL_RET_CODE_INVALID_INPUT) -#else -#define ARG_CHECK_PTR(Ptr) -#endif - -#else -#define ARG_CHECK_PTR(Ptr) -#endif - -/*#define SL_DBG_TRACE_ENABLE*/ -#ifdef SL_DBG_TRACE_ENABLE -#define SL_TRACE0(level,msg_id,str) printf(str) -#define SL_TRACE1(level,msg_id,str,p1) printf(str,(p1)) -#define SL_TRACE2(level,msg_id,str,p1,p2) printf(str,(p1),(p2)) -#define SL_TRACE3(level,msg_id,str,p1,p2,p3) printf(str,(p1),(p2),(p3)) -#define SL_TRACE4(level,msg_id,str,p1,p2,p3,p4) printf(str,(p1),(p2),(p3),(p4)) -#define SL_ERROR_TRACE(msg_id,str) printf(str) -#define SL_ERROR_TRACE1(msg_id,str,p1) printf(str,(p1)) -#define SL_ERROR_TRACE2(msg_id,str,p1,p2) printf(str,(p1),(p2)) -#define SL_ERROR_TRACE3(msg_id,str,p1,p2,p3) printf(str,(p1),(p2),(p3)) -#define SL_ERROR_TRACE4(msg_id,str,p1,p2,p3,p4) printf(str,(p1),(p2),(p3),(p4)) -#define SL_TRACE_FLUSH() -#else -#define SL_TRACE0(level,msg_id,str) -#define SL_TRACE1(level,msg_id,str,p1) -#define SL_TRACE2(level,msg_id,str,p1,p2) -#define SL_TRACE3(level,msg_id,str,p1,p2,p3) -#define SL_TRACE4(level,msg_id,str,p1,p2,p3,p4) -#define SL_ERROR_TRACE(msg_id,str) -#define SL_ERROR_TRACE1(msg_id,str,p1) -#define SL_ERROR_TRACE2(msg_id,str,p1,p2) -#define SL_ERROR_TRACE3(msg_id,str,p1,p2,p3) -#define SL_ERROR_TRACE4(msg_id,str,p1,p2,p3,p4) -#define SL_TRACE_FLUSH() -#endif - -/* #define SL_DBG_CNT_ENABLE */ -#ifdef SL_DBG_CNT_ENABLE -#define _SL_DBG_CNT_INC(Cnt) g_DbgCnt. ## Cnt++ -#define _SL_DBG_SYNC_LOG(index,value) {if(index < SL_DBG_SYNC_LOG_SIZE){*(_u32 *)&g_DbgCnt.SyncLog[index] = *(_u32 *)(value);}} - -#else -#define _SL_DBG_CNT_INC(Cnt) -#define _SL_DBG_SYNC_LOG(index,value) -#endif - -#define SL_DBG_LEVEL_1 1 -#define SL_DBG_LEVEL_2 2 -#define SL_DBG_LEVEL_3 4 -#define SL_DBG_LEVEL_MASK (SL_DBG_LEVEL_2|SL_DBG_LEVEL_3) - -#define SL_INCLUDE_DBG_FUNC(Name) ((Name ## _DBG_LEVEL) & SL_DBG_LEVEL_MASK) - -#define _SlDrvPrintStat_DBG_LEVEL SL_DBG_LEVEL_3 -#define _SlDrvOtherFunc_DBG_LEVEL SL_DBG_LEVEL_1 - -#ifdef __cplusplus -} -#endif - - -#endif /*__SIMPLELINK_TRACE_H__*/ - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/wlan.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/wlan.h deleted file mode 100644 index 74db4d9af8c..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/wlan.h +++ /dev/null @@ -1,2660 +0,0 @@ -/* - * wlan.h - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -#ifndef __WLAN_H__ -#define __WLAN_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -/*! - \defgroup Wlan - \short Controls the use of the WiFi WLAN module - -*/ -/*! - - \addtogroup Wlan - - Connection features, such as: profiles, policies, SmartConfig(tm) - - Advanced WLAN features, such as: scans, rx filters and rx statistics collection - - @{ - -*/ - -#define SL_WLAN_BSSID_LENGTH (6) -#define SL_WLAN_SSID_MAX_LENGTH (32) - -#define SL_WLAN_NUM_OF_RATE_INDEXES (20) -#define SL_WLAN_SIZE_OF_RSSI_HISTOGRAM (6) -#define SL_WLAN_SMART_CONFIG_KEY_LENGTH (16) -#define SL_WLAN_SMART_CONFIG_DEFAULT_CIPHER (1) -#define SL_WLAN_SMART_CONFIG_DEFAULT_GROUP (0) - -#define SL_WLAN_MAX_PROFILES (7) -#define SL_WLAN_DEL_ALL_PROFILES (255) - -typedef enum -{ - SL_WLAN_P2P_WPS_METHOD_DEFAULT, - SL_WLAN_P2P_WPS_METHOD_PIN_USER, - SL_WLAN_P2P_WPS_METHOD_PIN_MACHINE, - SL_WLAN_P2P_WPS_METHOD_REKEY, - SL_WLAN_P2P_WPS_METHOD_PBC, - SL_WLAN_P2P_WPS_METHOD_REGISTRAR -} SlWlanP2PWpsMethod_e; - -/* WLAN user events */ -typedef enum -{ - SL_WLAN_EVENT_CONNECT = 1, - SL_WLAN_EVENT_DISCONNECT, - SL_WLAN_EVENT_STA_ADDED, - SL_WLAN_EVENT_STA_REMOVED, - - SL_WLAN_EVENT_P2P_CONNECT, - SL_WLAN_EVENT_P2P_DISCONNECT, - SL_WLAN_EVENT_P2P_CLIENT_ADDED, - SL_WLAN_EVENT_P2P_CLIENT_REMOVED, - SL_WLAN_EVENT_P2P_DEVFOUND, - SL_WLAN_EVENT_P2P_REQUEST, - SL_WLAN_EVENT_P2P_CONNECTFAIL, - - SL_WLAN_EVENT_RXFILTER, - SL_WLAN_EVENT_PROVISIONING_STATUS, - SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED, - SL_WLAN_EVENT_LINK_QUALITY_TRIGGER, - SL_WLAN_EVENT_MAX - -} SlWlanEventId_e; - - -/* WLAN Disconnect Reason Codes */ -#define SL_WLAN_DISCONNECT_UNSPECIFIED (1) - #define SL_WLAN_DISCONNECT_AUTH_NO_LONGER_VALID (2) - #define SL_WLAN_DISCONNECT_DEAUTH_SENDING_STA_LEAVING (3) - #define SL_WLAN_DISCONNECT_INACTIVITY (4) - #define SL_WLAN_DISCONNECT_TOO_MANY_STA (5) - #define SL_WLAN_DISCONNECT_FRAME_FROM_NONAUTH_STA (6) - #define SL_WLAN_DISCONNECT_FRAME_FROM_NONASSOC_STA (7) - #define SL_WLAN_DISCONNECT_DISS_SENDING_STA_LEAVING (8) - #define SL_WLAN_DISCONNECT_STA_NOT_AUTH (9) - #define SL_WLAN_DISCONNECT_POWER_CAPABILITY_INVALID (10) - #define SL_WLAN_DISCONNECT_SUPPORTED_CHANNELS_INVALID (11) - #define SL_WLAN_DISCONNECT_INVALID_IE (13) - #define SL_WLAN_DISCONNECT_MIC_FAILURE (14) - #define SL_WLAN_DISCONNECT_FOURWAY_HANDSHAKE_TIMEOUT (15) - #define SL_WLAN_DISCONNECT_GROUPKEY_HANDSHAKE_TIMEOUT (16) - #define SL_WLAN_DISCONNECT_REASSOC_INVALID_IE (17) - #define SL_WLAN_DISCONNECT_INVALID_GROUP_CIPHER (18) - #define SL_WLAN_DISCONNECT_INVALID_PAIRWISE_CIPHER (19) - #define SL_WLAN_DISCONNECT_INVALID_AKMP (20) - #define SL_WLAN_DISCONNECT_UNSUPPORTED_RSN_VERSION (21) - #define SL_WLAN_DISCONNECT_INVALID_RSN_CAPABILITIES (22) - #define SL_WLAN_DISCONNECT_IEEE_802_1X_AUTHENTICATION_FAILED (23) - #define SL_WLAN_DISCONNECT_CIPHER_SUITE_REJECTED (24) - #define SL_WLAN_DISCONNECT_DISASSOC_QOS (32) - #define SL_WLAN_DISCONNECT_DISASSOC_QOS_BANDWIDTH (33) - #define SL_WLAN_DISCONNECT_DISASSOC_EXCESSIVE_ACK_PENDING (34) - #define SL_WLAN_DISCONNECT_DISASSOC_TXOP_LIMIT (35) - #define SL_WLAN_DISCONNECT_STA_LEAVING (36) - #define SL_WLAN_DISCONNECT_STA_DECLINED (37) - #define SL_WLAN_DISCONNECT_STA_UNKNOWN_BA (38) - #define SL_WLAN_DISCONNECT_STA_TIMEOUT (39) - #define SL_WLAN_DISCONNECT_STA_UNSUPPORTED_CIPHER_SUITE (40) - #define SL_WLAN_DISCONNECT_USER_INITIATED (200) - #define SL_WLAN_DISCONNECT_AUTH_TIMEOUT (202) - #define SL_WLAN_DISCONNECT_ASSOC_TIMEOUT (203) - #define SL_WLAN_DISCONNECT_SECURITY_FAILURE (204) - #define SL_WLAN_DISCONNECT_WHILE_CONNNECTING (208) - #define SL_WLAN_DISCONNECT_MISSING_CERT (209) - #define SL_WLAN_DISCONNECT_CERTIFICATE_EXPIRED (210) - - - -#define SL_WLAN_STATUS_DISCONNECTED (0) -#define SL_WLAN_STATUS_SCANING (1) -#define SL_WLAN_STATUS_CONNECTING (2) -#define SL_WLAN_STATUS_CONNECTED (3) - -#define SL_WLAN_PROVISIONING_GENERAL_ERROR (0) -#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_NETWORK_NOT_FOUND (1) -#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_CONNECTION_FAILED (2) -#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_CONNECTION_SUCCESS_IP_NOT_ACQUIRED (3) -#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS_FEEDBACK_FAILED (4) -#define SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS (5) -#define SL_WLAN_PROVISIONING_ERROR_ABORT (6) -#define SL_WLAN_PROVISIONING_ERROR_ABORT_INVALID_PARAM (7) -#define SL_WLAN_PROVISIONING_ERROR_ABORT_HTTP_SERVER_DISABLED (8) -#define SL_WLAN_PROVISIONING_ERROR_ABORT_PROFILE_LIST_FULL (9) -#define SL_WLAN_PROVISIONING_ERROR_ABORT_PROVISIONING_ALREADY_STARTED (10) -#define SL_WLAN_PROVISIONING_AUTO_STARTED (11) -#define SL_WLAN_PROVISIONING_STOPPED (12) -#define SL_WLAN_PROVISIONING_SMART_CONFIG_SYNCED (13) -#define SL_WLAN_PROVISIONING_SMART_CONFIG_SYNC_TIMEOUT (14) -#define SL_WLAN_PROVISIONING_CONFIRMATION_WLAN_CONNECT (15) -#define SL_WLAN_PROVISIONING_CONFIRMATION_IP_ACQUIRED (16) -#define SL_WLAN_PROVISIONING_EXTERNAL_CONFIGURATION_READY (17) - -#define SL_WLAN_SEC_TYPE_OPEN (0) -#define SL_WLAN_SEC_TYPE_WEP (1) -#define SL_WLAN_SEC_TYPE_WPA (2) /* deprecated */ -#define SL_WLAN_SEC_TYPE_WPA_WPA2 (2) -#define SL_WLAN_SEC_TYPE_WPS_PBC (3) -#define SL_WLAN_SEC_TYPE_WPS_PIN (4) -#define SL_WLAN_SEC_TYPE_WPA_ENT (5) -#define SL_WLAN_SEC_TYPE_P2P_PBC (6) -#define SL_WLAN_SEC_TYPE_P2P_PIN_KEYPAD (7) -#define SL_WLAN_SEC_TYPE_P2P_PIN_DISPLAY (8) -#define SL_WLAN_SEC_TYPE_P2P_PIN_AUTO (9) /* NOT Supported yet */ -#define SL_WLAN_SEC_TYPE_WEP_SHARED (10) - -#define SL_TLS (0x1) -#define SL_MSCHAP (0x0) -#define SL_PSK (0x2) -#define SL_TTLS (0x10) -#define SL_PEAP0 (0x20) -#define SL_PEAP1 (0x40) -#define SL_FAST (0x80) - -#define SL_WLAN_FAST_AUTH_PROVISIONING (0x02) -#define SL_WLAN_FAST_UNAUTH_PROVISIONING (0x01) -#define SL_WLAN_FAST_NO_PROVISIONING (0x00) - -#define SL_WLAN_PROVISIONING_CMD_START_MODE_AP (0) -#define SL_WLAN_PROVISIONING_CMD_START_MODE_SC (1) -#define SL_WLAN_PROVISIONING_CMD_START_MODE_APSC (2) -#define SL_WLAN_PROVISIONING_CMD_START_MODE_APSC_EXTERNAL_CONFIGURATION (3) -#define SL_WLAN_PROVISIONING_CMD_STOP (4) -#define SL_WLAN_PROVISIONING_CMD_ABORT_EXTERNAL_CONFIRMATION (5) - -/* Provisioning API Flags */ -#define SL_WLAN_PROVISIONING_CMD_FLAG_EXTERNAL_CONFIRMATION (0x00000001) - -/* to be used only in provisioning stop command */ -#define SL_WLAN_PROVISIONING_REMAIN_IN_CURRENT_ROLE (0xFF) - - -#define SL_WLAN_EAPMETHOD_PHASE2_SHIFT (8) -#define SL_WLAN_EAPMETHOD_PAIRWISE_CIPHER_SHIFT (19) -#define SL_WLAN_EAPMETHOD_GROUP_CIPHER_SHIFT (27) - -#define SL_WLAN_WPA_CIPHER_CCMP (0x1) -#define SL_WLAN_WPA_CIPHER_TKIP (0x2) -#define SL_WLAN_CC31XX_DEFAULT_CIPHER (SL_WLAN_WPA_CIPHER_CCMP | SL_WLAN_WPA_CIPHER_TKIP) - -#define SL_WLAN_EAPMETHOD(phase1,phase2,pairwise_cipher,group_cipher) \ - ((phase1) | \ - ((phase2) << SL_WLAN_EAPMETHOD_PHASE2_SHIFT ) |\ - ((_u32)(pairwise_cipher) << SL_WLAN_EAPMETHOD_PAIRWISE_CIPHER_SHIFT ) |\ - ((_u32)(group_cipher) << SL_WLAN_EAPMETHOD_GROUP_CIPHER_SHIFT )) - -/* phase1 phase2 pairwise_cipher group_cipher */ -#define SL_WLAN_ENT_EAP_METHOD_TLS SL_WLAN_EAPMETHOD(SL_TLS, 0, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_TTLS_TLS SL_WLAN_EAPMETHOD(SL_TTLS, SL_TLS, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_TTLS_MSCHAPv2 SL_WLAN_EAPMETHOD(SL_TTLS, SL_MSCHAP, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_TTLS_PSK SL_WLAN_EAPMETHOD(SL_TTLS, SL_PSK, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_PEAP0_TLS SL_WLAN_EAPMETHOD(SL_PEAP0, SL_TLS, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_PEAP0_MSCHAPv2 SL_WLAN_EAPMETHOD(SL_PEAP0, SL_MSCHAP, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_PEAP0_PSK SL_WLAN_EAPMETHOD(SL_PEAP0, SL_PSK, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_PEAP1_TLS SL_WLAN_EAPMETHOD(SL_PEAP1, SL_TLS, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_PEAP1_PSK SL_WLAN_EAPMETHOD(SL_PEAP1, SL_PSK, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_FAST_AUTH_PROVISIONING SL_WLAN_EAPMETHOD(SL_FAST, SL_WLAN_FAST_AUTH_PROVISIONING, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_FAST_UNAUTH_PROVISIONING SL_WLAN_EAPMETHOD(SL_FAST, SL_WLAN_FAST_UNAUTH_PROVISIONING, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) -#define SL_WLAN_ENT_EAP_METHOD_FAST_NO_PROVISIONING SL_WLAN_EAPMETHOD(SL_FAST, SL_WLAN_FAST_NO_PROVISIONING, SL_WLAN_CC31XX_DEFAULT_CIPHER , SL_WLAN_CC31XX_DEFAULT_CIPHER) - -#define SL_WLAN_LONG_PREAMBLE (0) -#define SL_WLAN_SHORT_PREAMBLE (1) - -/* 2.4G - 1 bit band = 0 , 5 remaining bits for channel (1..14) */ -#define SL_WLAN_RAW_RF_TX_PARAMS_CHANNEL_SHIFT (0) -#define SL_WLAN_RAW_RF_TX_PARAMS_BAND_SHIFT (5) -#define SL_WLAN_RAW_RF_TX_PARAMS_RATE_SHIFT (6) -#define SL_WLAN_RAW_RF_TX_PARAMS_POWER_SHIFT (11) -#define SL_WLAN_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT (15) - -/* 5.0G – 1 bit band = 1, split the 5G 8 bit channel into 2 places LO, HI */ -#define SL_WLAN_RAW_RF_TX_PARAMS_5G_RATE_SHIFT (9) -#define SL_WLAN_RAW_RF_TX_PARAMS_5G_CHANNEL_SHIFT_HI (12) -#define SL_WLAN_RAW_RF_TX_PARAMS_5G_POWER_SHIFT (14) -#define SL_WLAN_RAW_RF_TX_PARAMS_5G_PREAMBLE_SHIFT (15) - -/* 5.0 G - 8bit channel */ -#define CHANNEL_DECODE_MASK_LO (0x1f) /* 5 LSB of 5G channel */ -#define CHANNEL_DECODE_SHIFT_HI (5) /* 5 LSB of 5G channel */ -#define CHANNEL_DECODE_MASK_HI (0xe0) /* 3 MSB of 5G channel */ -#define POWER_DECODE_MASK_LO (0x01) /* 1 bit of 5G power */ -#define MAX_2_4G_CHANNEL_NUMBER (14) -#define BAND_2_4G (0) -#define BAND_5_0G (1) - -#define SL_WLAN_RAW_RF_TX_PARAMS(chan,rate,power,preamble) \ - ((unsigned char)(chan) <= MAX_2_4G_CHANNEL_NUMBER) ? ( \ - (chan << SL_WLAN_RAW_RF_TX_PARAMS_CHANNEL_SHIFT) | \ - (BAND_2_4G<< SL_WLAN_RAW_RF_TX_PARAMS_BAND_SHIFT) | \ - (rate << SL_WLAN_RAW_RF_TX_PARAMS_RATE_SHIFT) | \ - (power << SL_WLAN_RAW_RF_TX_PARAMS_POWER_SHIFT) | \ - (preamble << SL_WLAN_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT) \ - ) : ( \ - ( (chan & CHANNEL_DECODE_MASK_LO) << SL_WLAN_RAW_RF_TX_PARAMS_CHANNEL_SHIFT) | \ - (BAND_5_0G<< SL_WLAN_RAW_RF_TX_PARAMS_BAND_SHIFT) | \ - (rate << SL_WLAN_RAW_RF_TX_PARAMS_RATE_SHIFT) | \ - (((chan & CHANNEL_DECODE_MASK_HI) >> CHANNEL_DECODE_SHIFT_HI) << SL_WLAN_RAW_RF_TX_PARAMS_5G_CHANNEL_SHIFT_HI) | \ - ((power & POWER_DECODE_MASK_LO) << SL_WLAN_RAW_RF_TX_PARAMS_POWER_SHIFT) | \ - (preamble << SL_WLAN_RAW_RF_TX_PARAMS_PREAMBLE_SHIFT) \ - ) - -/* Open 5G transceiver socket parameters */ -#define TRANSCEIVER_5G_LOW_POWER_LOW_RATE 0x01 /* bit 0*/ -#define SL_WLAN_RAW_RF_SOCKET_CHANNEL(channel, flags) (channel&0xFF | (flags&0xFF)<<8) - -/* wlan config application IDs */ -#define SL_WLAN_CFG_AP_ID (0) -#define SL_WLAN_CFG_GENERAL_PARAM_ID (1) -#define SL_WLAN_CFG_P2P_PARAM_ID (2) -#define SL_WLAN_CFG_AP_ACCESS_LIST_ID (3) -#define SL_WLAN_RX_FILTERS_ID (4) -#define SL_WLAN_CONNECTION_INFO (5) - -/* wlan AP Config set/get options */ -#define SL_WLAN_AP_OPT_SSID (0) -#define SL_WLAN_AP_OPT_CHANNEL (3) -#define SL_WLAN_AP_OPT_HIDDEN_SSID (4) -#define SL_WLAN_AP_OPT_SECURITY_TYPE (6) -#define SL_WLAN_AP_OPT_PASSWORD (7) -#define SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE (9) -#define SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER (10) -#define SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER (11) - - - -#define SL_WLAN_P2P_OPT_DEV_NAME (12) -#define SL_WLAN_P2P_OPT_DEV_TYPE (13) -#define SL_WLAN_P2P_OPT_CHANNEL_N_REGS (14) -#define SL_WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT (16) -#define SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS (18) /* change the scan channels and RSSI threshold using this configuration option */ -#define SL_WLAN_AP_OPT_MAX_STATIONS (19) -#define SL_WLAN_AP_ACCESS_LIST_ADD_MAC (20) -#define SL_WLAN_AP_ACCESS_LIST_DEL_MAC (21) -#define SL_WLAN_AP_ACCESS_LIST_DEL_IDX (22) -#define SL_WLAN_AP_ACCESS_LIST_NUM_ENTRIES (24) -#define SL_WLAN_AP_ACCESS_LIST_MODE (25) -#define SL_WLAN_AP_OPT_MAX_STA_AGING (26) - -#define SL_WLAN_RX_FILTER_STATE (27) -#define SL_WLAN_RX_FILTER_REMOVE (28) -#define SL_WLAN_RX_FILTER_STORE (29) -#define SL_WLAN_RX_FILTER_UPDATE_ARGS (30) -#define SL_WLAN_RX_FILTER_SYS_STATE (31) -#define SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH (32) -#define SL_WLAN_GENERAL_PARAM_OPT_SUSPEND_PROFILES (33) -#define SL_WLAN_GENERAL_PARAM_OPT_ENABLE_5G (34) -#define SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS_5G (35) -#define SL_WLAN_GENERAL_PARAM_OPT_USER_COUNTRY_ATTRIB (36) -#define SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_ATTRIB (37) -#define SL_WLAN_GENERAL_PARAM_REGISTER_LINK_QUALITY_EVENT (38) -#define SL_WLAN_GENERAL_PARAM_COEX_CONFIG (39) -#define SL_WLAN_GENERAL_PARAM_ANT_SELECTION_CONFIG (40) -#define SL_WLAN_GENERAL_PARAM_ANT_SELECTION_SET (41) -#define SL_WLAN_GENERAL_PARAM_ANT_SELECTION_GET (42) - - -/* SmartConfig CIPHER options */ -#define SL_WLAN_SMART_CONFIG_CIPHER_SFLASH (0) /* password is not delivered by the application. The Simple Manager should - check if the keys are stored in the Flash. */ -#define SL_WLAN_SMART_CONFIG_CIPHER_AES (1) /* AES (other types are not supported) */ -#define SL_WLAN_SMART_CONFIG_CIPHER_NONE (0xFF) /* do not check in the flash */ - - -#define SL_WLAN_POLICY_CONNECTION (0x10) -#define SL_WLAN_POLICY_SCAN (0x20) -#define SL_WLAN_POLICY_PM (0x30) -#define SL_WLAN_POLICY_P2P (0x40) - -#define SL_WLAN_VAL_2_MASK(position,value) ((1 & (value))<<(position)) -#define SL_WLAN_MASK_2_VAL(position,mask) (((1 << position) & (mask)) >> (position)) - -#define SL_WLAN_CONNECTION_POLICY(Auto,Fast,anyP2P,autoProvisioning) (SL_WLAN_VAL_2_MASK(0,Auto) | SL_WLAN_VAL_2_MASK(1,Fast) | SL_WLAN_VAL_2_MASK(2,0) | SL_WLAN_VAL_2_MASK(3,anyP2P) | SL_WLAN_VAL_2_MASK(4,0) | SL_WLAN_VAL_2_MASK(5,autoProvisioning)) -#define SL_WLAN_SCAN_POLICY_EN(policy) (SL_WLAN_MASK_2_VAL(0,policy)) -#define SL_WLAN_SCAN_POLICY(Enable,Enable_Hidden) (SL_WLAN_VAL_2_MASK(0,Enable) | SL_WLAN_VAL_2_MASK(1,Enable_Hidden)) - - -#define SL_WLAN_ENABLE_SCAN (1) -#define SL_WLAN_DISABLE_SCAN (0) -#define SL_WLAN_ALLOW_HIDDEN_SSID_RESULTS (1) -#define SL_WLAN_BLOCK_HIDDEN_SSID_RESULTS (0) - -#define SL_WLAN_NORMAL_POLICY (0) -#define SL_WLAN_LOW_LATENCY_POLICY (1) -#define SL_WLAN_LOW_POWER_POLICY (2) -#define SL_WLAN_ALWAYS_ON_POLICY (3) -#define SL_WLAN_LONG_SLEEP_INTERVAL_POLICY (4) -#define SL_WLAN_IOT_LOW_POWER_POLICY (6) - -#define SL_WLAN_P2P_ROLE_NEGOTIATE (3) -#define SL_WLAN_P2P_ROLE_GROUP_OWNER (15) -#define SL_WLAN_P2P_ROLE_CLIENT (0) - -#define SL_WLAN_P2P_NEG_INITIATOR_ACTIVE (0) -#define SL_WLAN_P2P_NEG_INITIATOR_PASSIVE (1) -#define SL_WLAN_P2P_NEG_INITIATOR_RAND_BACKOFF (2) - -#define SL_WLAN_POLICY_VAL_2_OPTIONS(position,mask,policy) ((mask & policy) << position ) - -#define SL_WLAN_P2P_POLICY(p2pNegType,p2pNegInitiator) (SL_WLAN_POLICY_VAL_2_OPTIONS(0,0xF,(p2pNegType > SL_WLAN_P2P_ROLE_GROUP_OWNER ? SL_WLAN_P2P_ROLE_GROUP_OWNER : p2pNegType)) | \ - SL_WLAN_POLICY_VAL_2_OPTIONS(4,0x1,(p2pNegType > SL_WLAN_P2P_ROLE_GROUP_OWNER ? 1:0)) | \ - SL_WLAN_POLICY_VAL_2_OPTIONS(5,0x3, p2pNegInitiator)) - - -/* Info elements */ -#define SL_WLAN_INFO_ELEMENT_DEFAULT_ID (0) /* 221 will be used */ - -/* info element size is up to 252 bytes (+ 3 bytes of OUI). */ -#define SL_WLAN_INFO_ELEMENT_MAX_SIZE (252) - -/* For AP - the total length of all info elements is 300 bytes (for example - 4 info elements of 75 bytes each) */ -#define SL_WLAN_INFO_ELEMENT_MAX_TOTAL_LENGTH_AP (300) - -/* For P2P - the total length of all info elements is 160 bytes (for example - 4 info elements of 40 bytes each) */ -#define SL_WLAN_INFO_ELEMENT_MAX_TOTAL_LENGTH_P2P_GO (160) - -#define SL_WLAN_INFO_ELEMENT_AP_ROLE (0) -#define SL_WLAN_INFO_ELEMENT_P2P_GO_ROLE (1) - -/* we support up to 4 info elements per Role. */ -#define SL_WLAN_MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED (4) - -#define SL_WLAN_INFO_ELEMENT_DEFAULT_OUI_0 (0x08) -#define SL_WLAN_INFO_ELEMENT_DEFAULT_OUI_1 (0x00) -#define SL_WLAN_INFO_ELEMENT_DEFAULT_OUI_2 (0x28) - -#define SL_WLAN_INFO_ELEMENT_DEFAULT_OUI (0x000000) /* 08, 00, 28 will be used */ - -#define SL_WLAN_AP_ACCESS_LIST_MODE_DISABLED 0 -#define SL_WLAN_AP_ACCESS_LIST_MODE_DENY_LIST 1 -#define SL_WLAN_MAX_ACCESS_LIST_STATIONS 8 - -#define SL_WLAN_IOTLP_BITMAP_FORCE_DMS 0X40 -#define SL_WLAN_IOTLP_BITMAP_FORCE_PROXY_ARP 0X80 - -/* Scan results security information */ -#define SL_WLAN_SCAN_RESULT_GROUP_CIPHER(SecurityInfo) (SecurityInfo & 0xF) /* Possible values: NONE,SL_WLAN_CIPHER_BITMAP_TKIP,SL_WLAN_CIPHER_BITMAP_CCMP */ -#define SL_WLAN_SCAN_RESULT_UNICAST_CIPHER_BITMAP(SecurityInfo) ((SecurityInfo & 0xF0) >> 4 ) /* Possible values: NONE,SL_WLAN_CIPHER_BITMAP_WEP40,SL_WLAN_CIPHER_BITMAP_WEP104,SL_WLAN_CIPHER_BITMAP_TKIP,SL_WLAN_CIPHER_BITMAP_CCMP*/ -#define SL_WLAN_SCAN_RESULT_HIDDEN_SSID(SecurityInfo) (SecurityInfo & 0x2000 ) >> 13 /* Possible values: TRUE/FALSE */ -#define SL_WLAN_SCAN_RESULT_KEY_MGMT_SUITES_BITMAP(SecurityInfo) (SecurityInfo & 0x1800 ) >> 11 /* Possible values: SL_WLAN_KEY_MGMT_SUITE_802_1_X, SL_WLAN_KEY_MGMT_SUITE_PSK */ -#define SL_WLAN_SCAN_RESULT_SEC_TYPE_BITMAP(SecurityInfo) (SecurityInfo & 0x700 ) >> 8 /* Possible values: SL_WLAN_SECURITY_TYPE_BITMAP_OPEN, SL_WLAN_SECURITY_TYPE_BITMAP_WEP, SL_WLAN_SECURITY_TYPE_BITMAP_WPA, SL_WLAN_SECURITY_TYPE_BITMAP_WPA2, 0x6 (mix mode) SL_WLAN_SECURITY_TYPE_BITMAP_WPA | SL_WLAN_SECURITY_TYPE_BITMAP_WPA2 */ - -#define SL_WLAN_SECURITY_TYPE_BITMAP_OPEN 0x0 -#define SL_WLAN_SECURITY_TYPE_BITMAP_WEP 0x1 -#define SL_WLAN_SECURITY_TYPE_BITMAP_WPA 0x2 -#define SL_WLAN_SECURITY_TYPE_BITMAP_WPA2 0x4 - -#define SL_WLAN_CIPHER_BITMAP_WEP40 0x1 -#define SL_WLAN_CIPHER_BITMAP_WEP104 0x2 -#define SL_WLAN_CIPHER_BITMAP_TKIP 0x4 -#define SL_WLAN_CIPHER_BITMAP_CCMP 0x8 - -#define SL_WLAN_KEY_MGMT_SUITE_802_1_X 1 -#define SL_WLAN_KEY_MGMT_SUITE_PSK 2 - - - -#define SL_WLAN_RX_FILTER_MAX_FILTERS (64) /* Max number of filters is 64 filters */ -#define SL_WLAN_RX_FILTER_MAX_SYS_FILTERS_SETS (32) /* The Max number of system filters */ -#define SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS (2) -#define SL_WLAN_RX_FILTER_NUM_OF_FILTER_PAYLOAD_ARGS (2) -#define SL_WLAN_RX_FILTER_RANGE_ARGS (2) -#define SL_WLAN_RX_FILTER_NUM_USER_EVENT_ID (64) -#define SL_WLAN_RX_FILTER_MAX_USER_EVENT_ID ( ( SL_WLAN_RX_FILTER_NUM_USER_EVENT_ID ) - 1 ) - -/* Bit manipulation for 8 bit */ -#define SL_WLAN_ISBITSET8(x,i) ((x[i>>3] & (0x80>>(i&7)))!=0) /* Is bit set, 8 bit unsigned numbers = x , location = i */ -#define SL_WLAN_SETBIT8(x,i) x[i>>3]|=(0x80>>(i&7)); /* Set bit,8 bit unsigned numbers = x , location = i */ -#define SL_WLAN_CLEARBIT8(x,i) x[i>>3]&=(0x80>>(i&7))^0xFF; /* Clear bit,8 bit unsigned numbers = x , location = i */ - -#define SL_WLAN_DONT_UPDATE (0x1F) -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -typedef enum -{ - SL_WLAN_RATE_1M = 1, - SL_WLAN_RATE_2M = 2, - SL_WLAN_RATE_5_5M = 3, - SL_WLAN_RATE_11M = 4, - SL_WLAN_RATE_6M = 6, - SL_WLAN_RATE_9M = 7, - SL_WLAN_RATE_12M = 8, - SL_WLAN_RATE_18M = 9, - SL_WLAN_RATE_24M = 10, - SL_WLAN_RATE_36M = 11, - SL_WLAN_RATE_48M = 12, - SL_WLAN_RATE_54M = 13, - SL_WLAN_RATE_MCS_0 = 14, - SL_WLAN_RATE_MCS_1 = 15, - SL_WLAN_RATE_MCS_2 = 16, - SL_WLAN_RATE_MCS_3 = 17, - SL_WLAN_RATE_MCS_4 = 18, - SL_WLAN_RATE_MCS_5 = 19, - SL_WLAN_RATE_MCS_6 = 20, - SL_WLAN_RATE_MCS_7 = 21, - SL_WLAN_MAX_NUM_RATES = 0xFF -}SlWlanRateIndex_e; - -typedef enum -{ - SL_WLAN_DEV_PW_DEFAULT = 0, - SL_WLAN_DEV_PW_PIN_KEYPAD = 1, - SL_WLAN_DEV_PW_PUSH_BUTTON = 4, - SL_WLAN_DEV_PW_PIN_DISPLAY = 5 -} SlWlanP2pDevPwdMethod_e; - -typedef struct -{ - _u32 Status; - _u32 SsidLen; - _u8 Ssid[32]; - _u32 PrivateTokenLen; - _u8 PrivateToken[32]; -}SlWlanSmartConfigStartAsyncResponse_t; - -typedef struct -{ - _u16 Status; - _u16 Padding; -}SlWlanSmartConfigStopAsyncResponse_t; - -typedef struct -{ - _u16 Status; - _u16 Padding; -}SlWlanConnFailureAsyncResponse_t; - -typedef struct -{ - _u16 Status; - _u16 Padding; -}SlWlanProvisioningStatusAsyncResponse_t; - -/* rx filter event struct - this event will be sent from the SL device - as a result of a passed rx filter - example: - suppose we have a filter with an action and we set the following: - SlWlanRxFilterAction_t Action; - Action.UserId = 2; - When the filter result is pass, an SlWlanEventRxFilterInfo_t event will be passed to the user as follows: - Type will be set to 0 - bit 2 in UserActionIdBitmap will be set in this event, because 2 is the user input for the action arg above. - an SlWlanEventRxFilterInfo_t event may have several bits set as a result of several rx filters causing different - events to pass */ - -typedef struct -{ - _u8 Type; /* Currently only event type 0 is supported. */ - _u8 UserActionIdBitmap[SL_WLAN_RX_FILTER_NUM_USER_EVENT_ID / 8]; /* Bit X is set indicates that the filter with event action arg X passed. */ -}SlWlanEventRxFilterInfo_t; - -typedef enum -{ - ROLE_STA = 0, - ROLE_RESERVED = 1, - ROLE_AP = 2, - ROLE_P2P = 3, - ROLE_TAG = 4 -}SlWlanMode_e; - -typedef struct -{ - _u8 SsidLen; - _u8 SsidName[32]; - _u8 Bssid[6]; - _u8 Padding; -} SlWlanEventConnect_t; - -typedef struct -{ - _u8 SsidLen; - _u8 SsidName[32]; - _u8 Bssid[6]; - _u8 ReasonCode; -} SlWlanEventDisconnect_t; - -typedef struct -{ - _u8 Mac[6]; - _u8 Padding[2]; -}SlWlanEventSTAAdded_t, SlWlanEventSTARemoved_t; - - -typedef struct -{ - _u8 SsidLen; - _u8 SsidName[32]; - _u8 Bssid[6]; - _u8 Reserved; - _u8 GoDeviceNameLen; - _u8 GoDeviceName[32]; - _u8 Padding[3]; -} SlWlanEventP2PConnect_t; - -typedef struct -{ - _u8 SsidLen; - _u8 SsidName[32]; - _u8 Bssid[6]; - _u8 ReasonCode; - _u8 GoDeviceNameLen; - _u8 GoDeviceName[32]; - _u8 Padding[3]; -} SlWlanEventP2PDisconnect_t; - -typedef struct -{ - _u8 Mac[6]; - _u8 ClDeviceNameLen; - _u8 ClDeviceName[32]; - _u8 OwnSsidLen; - _u8 OwnSsid[32]; -}SlWlanEventP2PClientAdded_t, SlWlanEventP2PClientRemoved_t; - -typedef struct -{ - _u8 GoDeviceNameLen; - _u8 GoDeviceName[32]; - _u8 Mac[6]; - _u8 WpsMethod; -}SlWlanEventP2PDevFound_t, SlWlanEventP2PRequest_t; - -/**************************************************/ -typedef struct -{ - _u16 Status; - _u16 Padding; -}SlWlanEventP2PConnectFail_t; - -typedef struct -{ - _u8 ProvisioningStatus; - _u8 Role; - _u8 WlanStatus; - _u8 Ssidlen; - _u8 Ssid[32]; - _u32 Reserved; -}SlWlanEventProvisioningStatus_t; - -typedef struct -{ - _u32 Status; - _u32 SsidLen; - _u8 Ssid[32]; - _u32 ReservedLen; - _u8 Reserved[32]; -} SlWlanEventProvisioningProfileAdded_t; - -typedef struct -{ - _u8 Data; /* The values which cause the trigger */ - _u8 TriggerId; /* Trigger index (0 .. 1) */ - _u8 Padding[2]; -}SlWlanLinkQualityAsyncEvent_t; - -typedef union -{ - SlWlanEventConnect_t Connect; /* SL_WLAN_EVENT_CONNECT */ - SlWlanEventDisconnect_t Disconnect; /* SL_WLAN_EVENT_DISCONNECT */ - SlWlanEventSTAAdded_t STAAdded; /* SL_WLAN_EVENT_STA_ADDED */ - SlWlanEventSTARemoved_t STARemoved; /* SL_WLAN_EVENT_STA_REMOVED */ - SlWlanEventP2PConnect_t P2PConnect; /* SL_WLAN_EVENT_P2P_CONNECT */ - SlWlanEventP2PDisconnect_t P2PDisconnect; /* SL_WLAN_EVENT_P2P_DISCONNECT */ - SlWlanEventP2PClientAdded_t P2PClientAdded; /* SL_WLAN_EVENT_P2P_CLIENT_ADDED */ - SlWlanEventP2PClientRemoved_t P2PClientRemoved; /* SL_WLAN_EVENT_P2P_CLIENT_REMOVED */ - SlWlanEventP2PDevFound_t P2PDevFound; /* SL_WLAN_EVENT_P2P_DEVFOUND */ - SlWlanEventP2PRequest_t P2PRequest; /* SL_WLAN_EVENT_P2P_REQUEST */ - SlWlanEventP2PConnectFail_t P2PConnectFail; /* SL_WLAN_EVENT_P2P_CONNECTFAIL */ - SlWlanEventRxFilterInfo_t RxFilterInfo; /* SL_WLAN_EVENT_RXFILTER */ - SlWlanEventProvisioningStatus_t ProvisioningStatus; /* SL_WLAN_EVENT_PROVISIONING_STATUS */ - SlWlanEventProvisioningProfileAdded_t ProvisioningProfileAdded; /* SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED */ - SlWlanLinkQualityAsyncEvent_t LinkQualityTrigger; /* SL_WLAN_EVENT_LINK_QUALITY_TRIGGER */ -} SlWlanEventData_u; - -typedef struct -{ - _u32 Id; - SlWlanEventData_u Data; -} SlWlanEvent_t; - -typedef struct -{ - _u32 ReceivedValidPacketsNumber; /* sum of the packets that been received OK (include filtered) */ - _u32 ReceivedFcsErrorPacketsNumber; /* sum of the packets that been dropped due to FCS error */ - _u32 ReceivedAddressMismatchPacketsNumber; /* sum of the packets that been received but filtered out by one of the HW filters */ - _i16 AvarageDataCtrlRssi; /* average RSSI for all valid data packets received */ - _i16 AvarageMgMntRssi; /* average RSSI for all valid management packets received */ - _u16 RateHistogram[SL_WLAN_NUM_OF_RATE_INDEXES]; /* rate histogram for all valid packets received */ - _u16 RssiHistogram[SL_WLAN_SIZE_OF_RSSI_HISTOGRAM]; /* RSSI histogram from -40 until -87 (all below and above\n RSSI will appear in the first and last cells */ - _u32 StartTimeStamp; /* the time stamp started collecting the statistics in uSec */ - _u32 GetTimeStamp; /* the time stamp called the get statistics command */ -}SlWlanGetRxStatResponse_t; - -typedef struct -{ - _u8 Ssid[SL_WLAN_SSID_MAX_LENGTH]; - _u8 Bssid[SL_WLAN_BSSID_LENGTH]; - _u8 SsidLen; - _i8 Rssi; - _i16 SecurityInfo; - _u8 Channel; - _i8 Reserved[1]; -}SlWlanNetworkEntry_t; - -typedef struct -{ - _u8 Ssid[SL_WLAN_SSID_MAX_LENGTH]; - _u8 Bssid[SL_WLAN_BSSID_LENGTH]; - _u8 SsidLen; - _i8 Rssi; - _i16 SecurityInfo; - _u8 Channel; - _i8 Reserved[1]; - /* country info extended area */ - _u8 CountryStr[2]; - _u16 Supported_2_4G_Channels; - _u32 Supported_5_0G_Channels; -}SlWlanExtNetworkEntry_t; - -typedef struct -{ - _u8 Type; - _i8* Key; - _u8 KeyLen; -}SlWlanSecParams_t; - -typedef struct -{ - _i8* User; - _u8 UserLen; - _i8* AnonUser; - _u8 AnonUserLen; - _u8 CertIndex; /* not supported */ - _u32 EapMethod; -}SlWlanSecParamsExt_t; - -typedef struct -{ - _i8 User[64]; - _u8 UserLen; - _i8 AnonUser[64]; - _u8 AnonUserLen; - _u8 CertIndex; /* not supported */ - _u32 EapMethod; -}SlWlanGetSecParamsExt_t; - -#define SL_WLAN_CONNECTION_PROTOCOL_STA 1 -#define SL_WLAN_CONNECTION_PROTOCOL_P2PCL 2 - -typedef union -{ - SlWlanEventConnect_t StaConnect; - SlWlanEventP2PConnect_t P2PConnect; -} SlWlanConnectionInfo_u; - -typedef enum -{ - SL_WLAN_DISCONNECTED = 0, - SL_WLAN_CONNECTED_STA, - SL_WLAN_CONNECTED_P2PCL, - SL_WLAN_CONNECTED_P2PGO, - SL_WLAN_AP_CONNECTED_STATIONS -}SlWlanConnStatusFlags_e; - -typedef struct -{ - _u8 Mode; /* ROLE_STA, ROLE_AP, ROLE_P2P */ - _u8 ConnStatus; /* SlWlanConnStatusFlags_e */ - _u8 SecType; /* Current connection security type - (0 in case of disconnect or AP mode) SL_WLAN_SEC_TYPE_OPEN, SL_WLAN_SEC_TYPE_WEP, SL_WLAN_SEC_TYPE_WPA_WPA2, SL_WLAN_SEC_TYPE_WPA_ENT, SL_WLAN_SEC_TYPE_WPS_PBC, SL_WLAN_SEC_TYPE_WPS_PIN */ - _u8 Reserved; - SlWlanConnectionInfo_u ConnectionInfo; -}SlWlanConnStatusParam_t; - -typedef struct -{ - _u32 ChannelsMask; - _i32 RssiThreshold; -}SlWlanScanParamCommand_t; - -typedef struct -{ - _u32 ChannelsMask; - _i32 RssiThreshold; -}SlWlanScanParam2GCommand_t; - -typedef struct -{ - _u32 ChannelsMask; - _i32 RssiThreshold; -}SlWlanScanParam5GCommand_t; - -typedef enum { - REGION_FCC = 0, - REGION_ETSI, - REGION_JP, - REGION_WW, - REGION_NO_LIMIT -} Region_e; - -typedef struct{ - _u8 Region; /* (0-FCC, 1-ETSI, 2-JP) */ - _u8 Padding[3]; - _u32 Active_2_4G_Channels; - _u32 Active_5_0G_Channels; - _u32 Dfs_5_0G_Channels; -}SlWlanUserCountryAttrib_t; - -typedef struct -{ - _u8 Id; - _u8 Oui[3]; - _u16 Length; - _u8 Data[252]; -} SlWlanInfoElement_t; - -typedef struct -{ - _u8 Index; /* 0 - SL_WLAN_MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED */ - _u8 Role; /* bit0: AP = 0, GO = 1 */ - SlWlanInfoElement_t IE; -} SlWlanSetInfoElement_t; - -typedef struct -{ - _u8 PowerMgtBitMask; /* Allows the user to activate the IoT LP feature only if several features are supported by the AP */ - /* SL_WLAN_IOTLP_BITMAP_FORCE_DMS, SL_WLAN_IOTLP_BITMAP_FORCE_PROXY_ARP */ - _u8 Reserved; - _u16 Reserved2; - _u16 MaxSleepTimeMs; /* max sleep time in mSec For setting Long Sleep Interval policy use */ - _u16 Reserved3; -} SlWlanPmPolicyParams_t; - -typedef enum -{ - SL_WLAN_METRIC_EVENT_RSSI_BEACON = 0, - SL_WLAN_METRIC_EVENT_RSSI_DATA = 1 -} SlWlanMetricEvent_e; - -typedef enum -{ - SL_WLAN_RX_QUALITY_EVENT_LEVEL = 0, /* The event is a "Level" indication which keeps */ - /* triggering as long as the average RSSI is below*/ - /* the threshold.*/ - - SL_WLAN_RX_QUALITY_EVENT_EDGE = 1 /* The event is an "Edge" indication which triggers*/ - /* only when the RSSI threshold is crossed from above.*/ -} SlWlanRxQualityEventType_e; - -typedef enum -{ - SL_WLAN_RSSI_EVENT_DIR_LOW = 0, - SL_WLAN_RSSI_EVENT_DIR_HIGH = 1, - SL_WLAN_RSSI_EVENT_DIR_BIDIR = 2, - SL_WLAN_RSSI_EVENT_SHIFT = 3 -} SlWlanRssiEventDir_e; - -typedef struct -{ - _i16 Threshold; /* Input event Threshold. Units: dBm / dB ; Range: (-100 .. 100) */ - _u16 Pacing; /* Minimum delay between consecutive events. Units: milliseconds ; Range: (0 .. 60000) */ - _u8 Metric; /* 0 - RSSI Beacon, 1 - RSSI Packet. Applicable only for CC3x35 SL devices */ - _u8 Type; /* 0 - Level, 1 - Edge. Applicable only for CC3x35 SL devices */ - _u8 Direction; /* 0 - Low, 1 - High, 2 - Bidirectional. Applicable only for CC3x35 SL devices */ - _u8 Hysteresis; /* Hysteresis range around the threshold value. Units: dB ; Threshold range: (0 .. 255) */ - _u8 TriggerId; /* Trigger index (0 .. 1). Applicable only for CC3x35 SL devices */ - _u8 Enable; /* Event Enable. 0 - Disable, 1 - Enable */ - _u8 Padding[2]; -} SlWlanRegisterLinkQualityEvents_t; - -typedef enum -{ - SL_WLAN_COEX_MODE_DISABLED, - SL_WLAN_COEX_BASIC_SINGLE_ANTENNA /*BLE coex with shared antenna (switch)*/ -}SlWlanCoexMode_e; - -typedef struct -{ - _u8 Mode; /* see SlWlanCoexMode_e */ - _u8 InputPad; /* Input pad from external syncing device */ - _u8 OutputPad; /* Output pad to external synced device (or switch)*/ - _u8 Reserved; - _u32 Options; /* Set to zero - not supported */ -}SlWlanCoexConfig_t; - -typedef enum -{ - SL_WLAN_ANT_SELECTION_DISABLED, /* Antenna selection disabled */ - SL_WLAN_ANT_SELECTION_ANT1, /* Antenna selection - use only antenna 1 */ - SL_WLAN_ANT_SELECTION_ANT2, /* Antenna selection - use only antenna 2 */ - SL_WLAN_ANT_SELECTION_AUTO, /* Antenna selection - automatic antenna selection during connection. Applicable only for CC3x35 SL devices */ - SL_WLAN_ANT_SELECTION_MANUAL /* Antenna selection - manual antenna selection while connected. Applicable only for CC3x20 SL devices */ -}SlWlanAntSelectionMode_e; - -typedef struct -{ - _u8 Mode; /* see SlWlanAntSelectionMode_e */ - _u8 Ant1Pad; /* Antenna selection pad (not pin!) */ - _u8 Ant2Pad; /* Antenna selection pad (not pin!) */ - _u8 Reserved; - _u32 Options; /* Set to zero - not supported */ -}SlWlanAntSelectionConfig_t; - -typedef enum -{ - SL_WLAN_ANT_IDX_1 = 1, /* Antenna index 1 */ - SL_WLAN_ANT_IDX_2, /* Antenna index 2 */ - SL_WLAN_ANT_TOGGLE, /* Antenna toggle */ - SL_WLAN_ANT_NUM_OF_IDXS -}SlWlanAntIndex_e; - -typedef struct SetAntennaCmd -{ - SlWlanAntIndex_e AntIndex; /* antenna index - 1, 2 or toggle*/ -}SetAntennaIndex_t; - - -typedef _i8 SlWlanRxFilterID_t; /* Unique filter ID which is allocated by the system , negative number means error */ - -/* Representation of filters Id as a bit field - The bit field is used to declare which filters are involved - in operation. Number of filter can be up to 128 filters. - i.e. 128 bits are needed. On the current release, up to 64 filters can be defined. */ -typedef _u8 SlWlanRxFilterIdMask_t[128/8]; - -typedef _u8 SlWlanRxFilterSysFilters_t; /* Describes the supported system filter sets*/ -/* possible values for SlWlanRxFilterSysFilters_t */ -#define SL_WLAN_RX_FILTER_ARP_AUTO_REPLY_SYS_FILTERS (0) -#define SL_WLAN_RX_FILTER_MULTICASTSIPV4_SYS_FILTERS (1) -#define SL_WLAN_RX_FILTER_MULTICASTSIPV6_SYS_FILTERS (2) -#define SL_WLAN_RX_FILTER_MULTICASTSWIFI_SYS_FILTERS (3) -#define SL_WLAN_RX_FILTER_SELF_MAC_ADDR_DROP_SYS_FILTERS (4) - -/* Describes the supported system filter sets, each bit represents different system filter set - The filter sets are defined at SlWlanRxFilterSysFilters_t */ -typedef _u8 SlWlanRxFilterSysFiltersMask_t[SL_WLAN_RX_FILTER_MAX_SYS_FILTERS_SETS/8]; - -typedef struct -{ - _u16 Offset; /* Offset in payload - Where in the payload to search for the pattern */ - _u8 Length; /* Pattern Length */ - _u8 Reserved; - _u8 Value[16]; /* Up to 16 bytes long (based on pattern length above) */ -}SlWlanRxFilterPatternArg_t; - -typedef _u8 SlWlanRxFilterRuleType_t; /* Different filter types */ -/* possible values for SlWlanRxFilterRuleType_t */ -#define SL_WLAN_RX_FILTER_HEADER (0) -#define SL_WLAN_RX_FILTER_COMBINATION (1) - -typedef _u8 SlWlanRxFilterFlags_u; -/* Possible values for SlWlanRxFilterFlags_u */ -#define SL_WLAN_RX_FILTER_BINARY (0x1) -#define SL_WLAN_RX_FILTER_PERSISTENT (0x8) -#define SL_WLAN_RX_FILTER_ENABLE (0x10) - -/* Used as comparison function for the header type arguments */ -typedef _u8 SlWlanRxFilterRuleHeaderCompareFunction_t; -/* Possible values for SlWlanRxFilterRuleHeaderCompareFunction_t */ -#define SL_WLAN_RX_FILTER_CMP_FUNC_IN_BETWEEN (0) -#define SL_WLAN_RX_FILTER_CMP_FUNC_EQUAL (1) -#define SL_WLAN_RX_FILTER_CMP_FUNC_NOT_EQUAL_TO (2) -#define SL_WLAN_RX_FILTER_CMP_FUNC_NOT_IN_BETWEEN (3) - -typedef _u8 SlWlanRxFilterTriggerCompareFunction_t; -/* Possible values for SlWlanRxFilterTriggerCompareFunction_t */ -#define SL_WLAN_RX_FILTER_TRIGGER_CMP_FUNC_EQUAL (0) -#define SL_WLAN_RX_FILTER_TRIGGER_CMP_FUNC_NOT_EQUAL_TO (1) /* arg1 == protocolVal ,not supported in current release */ -#define SL_WLAN_RX_FILTER_TRIGGER_CMP_FUNC_SMALLER_THAN (2) /* arg1 == protocolVal */ -#define SL_WLAN_RX_FILTER_TRIGGER_CMP_FUNC_BIGGER_THAN (3) /* arg1 == protocolVal */ - -typedef _u8 SlWlanRxFilterRuleHeaderField_t; /* Provides list of possible header types which may be defined as part of the rule */ -/* Possible values for SlWlanRxFilterRuleHeaderField_t */ -#define SL_WLAN_RX_FILTER_HFIELD_NULL (0) -#define SL_WLAN_RX_FILTER_HFIELD_FRAME_TYPE (1) /* 802.11 control\data\management */ -#define SL_WLAN_RX_FILTER_HFIELD_FRAME_SUBTYPE (2) /* 802.11 beacon\probe\.. */ -#define SL_WLAN_RX_FILTER_HFIELD_BSSID (3) /* 802.11 bssid type */ -#define SL_WLAN_RX_FILTER_HFIELD_MAC_SRC_ADDR (4) -#define SL_WLAN_RX_FILTER_HFIELD_MAC_DST_ADDR (5) -#define SL_WLAN_RX_FILTER_HFIELD_FRAME_LENGTH (6) -#define SL_WLAN_RX_FILTER_HFIELD_ETHER_TYPE (7) -#define SL_WLAN_RX_FILTER_HFIELD_IP_VERSION (8) -#define SL_WLAN_RX_FILTER_HFIELD_IP_PROTOCOL (9) /* TCP / UDP / ICMP / ICMPv6 / IGMP */ -#define SL_WLAN_RX_FILTER_HFIELD_IPV4_SRC_ADDR (10) -#define SL_WLAN_RX_FILTER_HFIELD_IPV4_DST_ADDR (11) -#define SL_WLAN_RX_FILTER_HFIELD_IPV6_SRC_ADRR (12) -#define SL_WLAN_RX_FILTER_HFIELD_IPV6_DST_ADDR (13) -#define SL_WLAN_RX_FILTER_HFIELD_PORT_SRC (14) -#define SL_WLAN_RX_FILTER_HFIELD_PORT_DST (15) -#define SL_WLAN_RX_FILTER_HFIELD_L4_PAYLOAD_PATTERN (19) /* use to look for patterns on the TCP and UDP payloads (after TCP/UDP header) */ -#define SL_WLAN_RX_FILTER_HFIELD_L1_PAYLOAD_PATTERN (20) /* use to look for patterns on the PHY payload (i.e. beginning of WLAN MAC header) */ -#define SL_WLAN_RX_FILTER_HFIELD_MAX_FIELD (21) /* Definition */ - -/* Holds the header ARGS which are used in case of HDR rule */ -typedef union -{ - /* buffer for pattern matching in payload up to 16 bytes (Binary Values) */ - SlWlanRxFilterPatternArg_t Pattern; - - /* Buffer for ipv4 address filter. binary arguments, number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ - _u8 Ipv4[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][4]; /* Binary Values for comparison */ - - /* Buffer for ipv4 address filter. Ascii arguments - IPv4 address: 4 bytes: ddd.ddd.ddd.ddd - 15 chars. Number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ - _u8 Ipv4Ascii[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][16]; /* Ascii Values for comparison */ - - /* Buffer for ipv6 address filter. binary arguments, Ascii format is not supported. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ - _u8 Ipv6[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][16]; /* Binary Values for comparison */ - - /* Buffer for mac address filter. binary arguments. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ - _u8 Mac[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][6]; /* Binary Values for comparison */ - - /* Buffer for mac address filter. Ascii arguments - MAC address: 6 bytes: xx:xx:xx:xx:xx:xx - 17 chars. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS */ - _u8 MacAscii[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][18]; /* Ascii Values for comparison */ - - /* Buffer for BSSID address filter. binary arguments. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS*/ - _u8 Bssid[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][6]; /* Binary Values for comparison */ - - /* Buffer for frame length filter. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS */ - _u32 FrameLength[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; /* Binary Values for comparison */ - - /* Buffer for port filter. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS */ - _u32 Port[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; /* Binary Values for comparison */ - - /* Buffer for Ether filter. number of argument may be up to SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS (according to host endianity) */ - _u32 EtherType[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; /* Binary Values for comparison */ - - /* Buffer for ip version filter. Buffer for binary arguments. IP Version - 4 for IPV4 and 6 for IPV6 */ - _u8 IpVersion; - - /* Buffer for frame type filter. Buffer for binary arguments. Frame Type (0 - management, 1 - Control, 2 - Data) */ - _u8 Frametype[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; - - /* Buffer for frame subtype filter. Buffer for binary arguments. Frame Sub Type (checkout the full list in the 802.11 spec). e.g. Beacon=0x80, Data=0x08, Qos-Data=0x04, ACK=0xD4, etc. */ - _u8 FrameSubtype[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; - - /* Buffer for protocol type filter. Buffer for binary arguments. e.g. 1 – ICMP (IPV4 only), 2 - IGMP (IPV4 only), 6 – TCP. 17 – UDP, 58 – ICMPV6 */ - _u8 IpProtocol[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS]; - - /* Buffer for ip version filter. Buffer for ASCII arguments. Use for IP version field comparison settings: "IPV4", "IPV6" */ - _u8 IpVersionAscii[4]; - - /* Buffer for frame type filter. Buffer for ASCII arguments. Use for Frame type field comparison settings: "MGMT", "CTRL", "DATA" */ - _u8 FrametypeAscii[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][4]; - - /* Buffer for protocol type filter. Buffer for ASCII arguments. Use for protocol field comparison settings: "ICMP", "IGMP", "TCP, "UDP", "ICMP6" */ - /* Note: Use memcpy with these strings instead of strcpy (no \0 should be at the end, as the array is 5 bytes long and ICMP6 is already 5 bytes long without the \0) */ - _u8 IpProtocolAscii[SL_WLAN_RX_FILTER_NUM_OF_FILTER_HEADER_ARGS][5]; - -}SlWlanRxFilterHeaderArg_u; - -/* Defines the Header Args and mask */ -typedef struct -{ - SlWlanRxFilterHeaderArg_u Value; /* Argument for the comparison function */ - _u8 Mask[16]; /* the mask is used in order to enable partial comparison (bit level), Use the 0xFFFFFFFF in case you don't want to use mask */ - -}SlWlanRxFilterRuleHeaderArgs_t; - -/* defines the Header rule. The header rule defines the compare function on the protocol header - For example destMacAddre is between ( 12:6::78:77, 12:6::78:90 ) */ -typedef struct -{ - SlWlanRxFilterRuleHeaderArgs_t Args; /* Filter arguments */ - SlWlanRxFilterRuleHeaderField_t Field; /* Packet HDR field which will be compared to the argument */ - SlWlanRxFilterRuleHeaderCompareFunction_t CompareFunc; /* type of the comparison function */ - _u8 Padding[2]; -}SlWlanRxFilterRuleHeader_t; - -/* Optional operators for the combination type filterID1 is located in the first arg , filterId2 is the second arg */ -typedef _u8 SlWlanRxFilterRuleCombinationOperator_t; -/* Possible values for SlWlanRxFilterRuleCombinationOperator_t */ -#define SL_WLAN_RX_FILTER_COMBINED_FUNC_NOT (0) /* filterID1 */ -#define SL_WLAN_RX_FILTER_COMBINED_FUNC_AND (1) /* filterID1 && filterID2 */ -#define SL_WLAN_RX_FILTER_COMBINED_FUNC_OR (2) /* filterID1 && filterID2 */ - -/* Defines the structure which define the combination type filter - The combined filter enable to make operation on one or two filter, - for example filterId1 or and(filterId2,filterId3). */ -typedef struct -{ - SlWlanRxFilterRuleCombinationOperator_t Operator; /* combination operator */ - SlWlanRxFilterID_t CombinationFilterId[SL_WLAN_RX_FILTER_RANGE_ARGS]; /* filterID, may be one or two depends on the combination operator type */ - _u8 Padding; -}SlWlanRxFilterRuleCombination_t; - -/* Rule structure composed of behavioral flags and the filter rule definitions */ -typedef union -{ - SlWlanRxFilterRuleHeader_t Header; /* Filter is from type Header */ - SlWlanRxFilterRuleCombination_t Combination; /* Filter is from type Combination */ -}SlWlanRxFilterRule_u; - -/* Bit field which represents the roleId possible values - In the current release only Station (with or without promiscuous modes) and AP roles are supported. - Activating filters before P2P negotiations (i.e. decision whether role is CL or GO) may result with - unexpected behaviour. After this stage, filters can be activated whereas STA role is the equivalent of P2P CL role - AP role is the equivalent of P2P GO role. - */ -typedef _u8 SlWlanRxFilterTriggerRoles_t; -/* Possible values for SlWlanRxFilterTriggerRoles_t */ -#define SL_WLAN_RX_FILTER_ROLE_AP (1) -#define SL_WLAN_RX_FILTER_ROLE_STA (2) -#define SL_WLAN_RX_FILTER_ROLE_TRANCIEVER (4) -#define SL_WLAN_RX_FILTER_ROLE_NULL (0) - -typedef _u8 SlWlanRxFilterTriggerConnectionStates_t; -/* Possible values for SlWlanRxFilterTriggerConnectionStates_t */ -#define SL_WLAN_RX_FILTER_STATE_STA_CONNECTED (0x1) -#define SL_WLAN_RX_FILTER_STATE_STA_NOT_CONNECTED (0x2) -#define SL_WLAN_RX_FILTER_STATE_STA_HAS_IP (0x4) -#define SL_WLAN_RX_FILTER_STATE_STA_HAS_NO_IP (0x8) - -/* There are 8 possible counter. if no counter is needed set to NO_TRIGGER_COUNTER */ -typedef _u8 SlWlanRxFilterCounterId_t; -/* Possible values for SlWlanRxFilterCounterId_t */ -#define SL_WLAN_RX_FILTER_NO_TRIGGER_COUNTER (0) -#define SL_WLAN_RX_FILTER_COUNTER1 (1) -#define SL_WLAN_RX_FILTER_COUNTER2 (2) -#define SL_WLAN_RX_FILTER_COUNTER3 (3) -#define SL_WLAN_RX_FILTER_COUNTER4 (4) -#define SL_WLAN_RX_FILTER_COUNTER5 (5) -#define SL_WLAN_RX_FILTER_COUNTER6 (6) -#define SL_WLAN_RX_FILTER_COUNTER7 (7) -#define SL_WLAN_RX_FILTER_COUNTER8 (8) -#define SL_WLAN_RX_FILTER_MAX_COUNTER (9) - -/* The filter trigger, determine when the filter is triggered, - The filter is triggered in the following condition :\n - 1. The filter parent is triggered\n - 2. The requested connection type exists, i.e. wlan_connect\n - 3. The filter role is the same as the system role\n */ -typedef struct -{ - SlWlanRxFilterID_t ParentFilterID; /* The parent filter ID, this is the way to build filter tree. NULL value means tree root */ - SlWlanRxFilterCounterId_t Counter; /* Trigger only when reach counter threshold */ - SlWlanRxFilterTriggerConnectionStates_t ConnectionState; /* Trigger only with specific connection state */ - SlWlanRxFilterTriggerRoles_t Role; /* Trigger only with specific role */ - _u32 CounterVal; /* Value for the counter if set */ - SlWlanRxFilterTriggerCompareFunction_t CompareFunction; /* The compare function refers to the counter if set */ - _u8 Padding[3]; -} SlWlanRxFilterTrigger_t; - -/* The actions are executed only if the filter is matched,\n - * In case of false match the packet is transferred to the HOST. \n - * The action is composed of bit field structure, up to 2 actions can be defined per filter.\n */ -typedef _u8 SlWlanRxFilterActionType_t; -/* Possible values for SlWlanRxFilterActionType_t */ -#define SL_WLAN_RX_FILTER_ACTION_NULL (0x0) /* No action to execute*/ -#define SL_WLAN_RX_FILTER_ACTION_DROP (0x1) /* If not dropped ,The packet is passed to the next filter or in case it is the last filter to the host */ -#define SL_WLAN_RX_FILTER_ACTION_ON_REG_INCREASE (0x4) /* action increase counter registers */ -#define SL_WLAN_RX_FILTER_ACTION_ON_REG_DECREASE (0x8) /* action decrease counter registers */ -#define SL_WLAN_RX_FILTER_ACTION_ON_REG_RESET (0x10)/* action reset counter registers */ -#define SL_WLAN_RX_FILTER_ACTION_SEND_TEMPLATE (0x20)/* unsupported */ -#define SL_WLAN_RX_FILTER_ACTION_EVENT_TO_HOST (0x40)/* action can send events to host */ - -/* Several actions can be defined The action is executed in case the filter rule is matched. */ -typedef struct -{ - SlWlanRxFilterActionType_t Type; /* Determine which actions are supported */ - _u8 Counter; /* The counter in use. In case the action is of type increase\decrease\reset this arg will contain the counter number, The counter number values are as in ::SlWlanRxFilterCounterId_t.\n*/ - _u16 Reserved; /* Must be set to zero */ - _u8 UserId; /* In case action set to host event, user can set id which will return in the event arguments */ - _u8 Padding[3]; - -} SlWlanRxFilterAction_t; - -/* The supported operation: SL_WLAN_RX_FILTER_STATE, SL_WLAN_RX_FILTER_REMOVE */ -typedef struct -{ - SlWlanRxFilterIdMask_t FilterBitmap; - _u8 Padding[4]; - -} SlWlanRxFilterOperationCommandBuff_t; - -/* The supported operation: SL_WLAN_RX_FILTER_UPDATE_ARGS */ -typedef struct -{ - _u8 FilterId; - _u8 BinaryOrAscii; /* Set 1 for Binary argument representation, 0 - for Ascii representation */ - _u8 Padding[2]; - SlWlanRxFilterRuleHeaderArgs_t Args; - - -} SlWlanRxFilterUpdateArgsCommandBuff_t; - -/* Filters bitmap enable\disable status return value */ -typedef struct -{ - SlWlanRxFilterIdMask_t FilterIdMask; /* The filter set bit map */ - -}SlWlanRxFilterRetrieveStateBuff_t; - -/* Disbale/Enable system filters */ -typedef struct -{ - SlWlanRxFilterSysFiltersMask_t FilterBitmap; /* The filter set bit map */ - -} SlWlanRxFilterSysFiltersSetStateBuff_t; - -/* System filters status return value */ -typedef struct -{ - SlWlanRxFilterSysFiltersMask_t FilterBitmap; /* The filter get bit map */ - -} SlWlanRxFilterSysFiltersRetrieveStateBuff_t; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - - -/*! - \brief Connect to wlan network as a station - - \param[in] pName Up to 32 bytes in case of STA the name is the SSID of the Access Point - \param[in] NameLen Name length - \param[in] pMacAddr 6 bytes for MAC address - \param[in] pSecParams Security parameters (use NULL key for SL_WLAN_SEC_TYPE_OPEN)\n - security types options: - - SL_WLAN_SEC_TYPE_OPEN - - SL_WLAN_SEC_TYPE_WEP - - SL_WLAN_SEC_TYPE_WEP_SHARED - - SL_WLAN_SEC_TYPE_WPA_WPA2 - - SL_WLAN_SEC_TYPE_WPA_ENT - - SL_WLAN_SEC_TYPE_WPS_PBC - - SL_WLAN_SEC_TYPE_WPS_PIN - - \param[in] pSecExtParams Enterprise parameters (set NULL in case Enterprise parameters is not in use) - - \return Zero on success, or negative error code on failure - - - \sa sl_WlanDisconnect - \note Belongs to \ref ext_api - \warning In this version only single enterprise mode could be used\n - SL_WLAN_SEC_TYPE_WPA is a deprecated definition, the new definition is SL_WLAN_SEC_TYPE_WPA_WPA2 - \par Example - - - Connect without security: - \code - SlWlanSecParams_t secParams; - secParams.Key = ""; - secParams.KeyLen = 0; - secParams.Type = SL_WLAN_SEC_TYPE_OPEN; - sl_WlanConnect("ssid_name", strlen("ssid_name"),0,&secParams,0); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_WlanConnect) -_i16 sl_WlanConnect(const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams); -#endif - -/*! - \brief Wlan disconnect - - Disconnect connection - - \return Zero disconnected done successfully, other already disconnected - - \sa sl_WlanConnect - \note belongs to \ref ext_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_WlanDisconnect) -_i16 sl_WlanDisconnect(void); -#endif - -/*! - \brief Add profile - - When auto start is enabled, the device connects to a - station from the profiles table. Up to 7 profiles (SL_WLAN_MAX_PROFILES) are - supported.\n If several profiles configured the device chose - the highest priority profile, within each priority group, - device will chose profile based on security policy, signal - strength, etc parameters. - - \param[in] pName Up to 32 bytes in case of STA the name is the - SSID of the Access Point.\n - In case of P2P the name is the remote device name. - \param[in] NameLen Name length - \param[in] pMacAddr 6 bytes for MAC address - \param[in] pSecParams Security parameters (use NULL key for SL_WLAN_SEC_TYPE_OPEN)\n - Security types options: - - SL_WLAN_SEC_TYPE_OPEN - - SL_WLAN_SEC_TYPE_WEP - - SL_WLAN_SEC_TYPE_WEP_SHARED - - SL_WLAN_SEC_TYPE_WPA_WPA2 - - SL_WLAN_SEC_TYPE_WPA_ENT - - SL_WLAN_SEC_TYPE_WPS_PBC - - SL_WLAN_SEC_TYPE_WPS_PIN - - \param[in] pSecExtParams Enterprise parameters - identity, identity length, - Anonymous, Anonymous length, CertIndex (not supported, - certificates need to be placed in a specific file ID), - EapMethod.\n Use NULL in case Enterprise parameters is not in use - - \param[in] Priority Profile priority. Lowest priority: 0, Highest priority: 15. - \param[in] Options Not supported - - \return Profile stored index on success, or negative error code on failure. - \par Persistent - Profiles are Persistent - \sa sl_WlanProfileGet , sl_WlanProfileDel - \note belongs to \ref ext_api - \warning Only one Enterprise profile is supported.\n - Please Note that in case of adding an existing profile (compared by pName,pMACAddr and security type) - the old profile will be deleted and the same index will be returned.\n - SL_WLAN_SEC_TYPE_WPA is a deprecated definition, the new definition is SL_WLAN_SEC_TYPE_WPA_WPA2 - -*/ -#if _SL_INCLUDE_FUNC(sl_WlanProfileAdd) -_i16 sl_WlanProfileAdd(const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams,const _u32 Priority,const _u32 Options); -#endif - -/*! - \brief Profile Update - - Update one or more of the existing profile parameters: SSID, BSSID, priority, security parameters - - \param[in] Index Profile index to update - \param[in] pName Up to 32 bytes in case of STA the name is the - SSID of the Access Point. In case of P2P the name is the remote device name. - NULL in case update is not needed\n - - \param[in] NameLen Name length. zero in case update is not needed\n - \param[in] pMacAddr 6 bytes for MAC address, NULL in case update is not needed\n - \param[in] pSecParams Security parameters (use NULL key for SL_WLAN_SEC_TYPE_OPEN)\n - Security types options: - - SL_WLAN_SEC_TYPE_OPEN - - SL_WLAN_SEC_TYPE_WEP - - SL_WLAN_SEC_TYPE_WEP_SHARED - - SL_WLAN_SEC_TYPE_WPA_WPA2 - - SL_WLAN_SEC_TYPE_WPA_ENT - - SL_WLAN_SEC_TYPE_WPS_PBC - - SL_WLAN_SEC_TYPE_WPS_PIN \n - - In case update is not needed, set to SL_WLAN_DONT_UPDATE - - \param[in] pSecExtParams Enterprise parameters - identity, identity length, - Anonymous, Anonymous length, CertIndex (not supported, - certificates need to be placed in a specific file ID), - EapMethod.\n Use NULL in case Enterprise parameters is not in use or does not need to be updated - - \param[in] Priority Profile priority. Lowest priority: 0, Highest priority: 15. In case update is not needed, set to SL_WLAN_DONT_UPDATE - - \return Zero on success or a negative error code on failure - \par Persistent - Profiles are Persistent - \sa sl_WlanProfileGet , sl_WlanProfileDel, sl_WlanProfileAdd - \note belongs to \ref ext_api - \warning In order to keep original security or priority values, set value to SL_WLAN_DONT_UPDATE - Note: If WPA profile SSID is being updated, security parameters including the password must be supplied as well. - \par Example - Update priority in profile index 0:
- \code - SlWlanSecParams_t SecParams; - _u32 Priority; - _u32 index; - - SecParams.Key = ""; - SecParams.KeyLen = 0; - SecParams.Type = SL_WLAN_DONT_UPDATE; - Priority = 4; - index = 0; - - RetVal = sl_WlanProfileUpdate(index, NULL,0,NULL,&SecParams ,NULL,Priority); - \endcode -*/ - -#if _SL_INCLUDE_FUNC(sl_WlanProfileUpdate) -_i16 sl_WlanProfileUpdate(const _u32 Index, const _i8* pName,const _i16 NameLen,const _u8 *pMacAddr,const SlWlanSecParams_t* pSecParams ,const SlWlanSecParamsExt_t* pSecExtParams,const _u32 Priority); -#endif -/*! - \brief Get profile - - Read profile from the device - - \param[in] Index Profile stored index, if index does not exists error is return - \param[out] pName Up to 32 bytes, in case of sta mode the name of the Access Point\n - In case of p2p mode the name of the Remote Device - \param[out] pNameLen Name length - \param[out] pMacAddr 6 bytes for MAC address - \param[out] pSecParams Security parameters. Security types options: - - SL_WLAN_SEC_TYPE_OPEN - - SL_WLAN_SEC_TYPE_WEP - - SL_WLAN_SEC_TYPE_WEP_SHARED - - SL_WLAN_SEC_TYPE_WPA_WPA2 - - SL_WLAN_SEC_TYPE_WPA_ENT - - SL_WLAN_SEC_TYPE_WPS_PBC - - SL_WLAN_SEC_TYPE_WPS_PIN - Key and key length are not return. In case of p2p security type pin the key refers to pin code - return due to security reasons. - \param[out] pSecExtParams Enterprise parameters - identity, identity - length, Anonymous, Anonymous length - CertIndex (not supported), EapMethod. - \param[out] pPriority Profile priority - - \return Profile security type is returned (0 or positive number) on success, or negative error code on failure - SL_ERROR_WLAN_GET_PROFILE_INVALID_INDEX is return is profile index does not exist - - \sa sl_WlanProfileAdd , sl_WlanProfileDel - \note belongs to \ref ext_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_WlanProfileGet) -_i16 sl_WlanProfileGet(const _i16 Index,_i8* pName, _i16 *pNameLen, _u8 *pMacAddr, SlWlanSecParams_t* pSecParams, SlWlanGetSecParamsExt_t* pSecExtParams, _u32 *pPriority); -#endif - -/*! - \brief Delete WLAN profile - - Delete WLAN profile - - \param[in] Index number of profile to delete. Possible values are 0 to 6.\n - Index value SL_WLAN_DEL_ALL_PROFILES will delete all saved profiles - - \return Zero on success or a negative error code on failure - \par Persistent - Profile deletion is Persistent - \sa sl_WlanProfileAdd , sl_WlanProfileGet - \note belongs to \ref ext_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_WlanProfileDel) -_i16 sl_WlanProfileDel(const _i16 Index); -#endif - -/*! - \brief Set policy values - - \param[in] Type Type of policy to be modified. The Options are: - - SL_WLAN_POLICY_CONNECTION - - SL_WLAN_POLICY_SCAN - - SL_WLAN_POLICY_PM - - SL_WLAN_POLICY_P2P - \param[in] Policy The option value which depends on action type - \param[in] pVal An optional value pointer - \param[in] ValLen An optional value length, in bytes - \return Zero on success or negative error code on failure. - \par Persistent - All parameters are System Persistent\n - Note that for SL_WLAN_POLICY_SCAN - Interval and Policy will be System persistent, but the hidden SSID option will not be persistent - - \sa sl_WlanPolicyGet - \note belongs to \ref ext_api - \warning - \par Example - - SL_WLAN_POLICY_CONNECTION:
defines options available to connect the CC31xx device to the AP: - The options below could be combined to a single action, if more than one action is required. - - - Auto Connect: If is set, the CC31xx device tries to automatically reconnect to one of its stored profiles, - each time the connection fails or the device is rebooted. To set this option, use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION,SL_WLAN_CONNECTION_POLICY(1,0,0,0),NULL,0) - \endcode -
- - - - Fast Connect: If is set, the CC31xx device tries to establish a fast connection to AP. - To set this option, use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION,SL_WLAN_CONNECTION_POLICY(0,1,0,0),NULL,0) - \endcode -
- - - P2P: If is set (relevant for P2P mode only), CC31xx/CC32xx device tries to automatically - connect to the first P2P device available, supporting push button only. To set this option, use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION,SL_WLAN_CONNECTION_POLICY(0,0,1,0),NULL,0) - \endcode -
- - - Auto Provisioning - If is set, the CC31xx device will automatically start the provisioning process - after a long period of disconnection when profiles exist to set this option, use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION,SL_WLAN_CONNECTION_POLICY(0,0,0,1),NULL,0) - \endcode \n - - - SL_WLAN_POLICY_SCAN:
defines system scan time interval. \nDefault interval is 10 minutes. - After settings scan interval, an immediate scan is activated.\n The next scan will be based on the interval settings. - For AP scan, minimum interval is 10 seconds. - - - With hidden SSID: For example, setting scan interval to 1 minute interval use including hidden ssid: - \code - _u32 intervalInSeconds = 60; - sl_WlanPolicySet(SL_WLAN_POLICY_SCAN,SL_WLAN_SCAN_POLICY(1,1), (_u8 *)&intervalInSeconds,sizeof(intervalInSeconds)); - \endcode -
- - - No hidden SSID: setting scan interval to 1 minute interval use, not including hidden ssid: - \code - _u32 intervalInSeconds = 60; - sl_WlanPolicySet(SL_WLAN_POLICY_SCAN,SL_WLAN_SCAN_POLICY(1,0), (_u8 *)&intervalInSeconds,sizeof(intervalInSeconds)); - \endcode -
- - - Disable scan: - \code - #define SL_WLAN_DISABLE_SCAN 0 - _u32 intervalInSeconds = 0; - sl_WlanPolicySet(SL_WLAN_POLICY_SCAN,SL_WLAN_DISABLE_SCAN,(_u8 *)&intervalInSeconds,sizeof(intervalInSeconds)); - \endcode -
- - SL_WLAN_POLICY_PM:
defines a power management policy for Station mode only: - - Normal power management (default) policy use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_NORMAL_POLICY, NULL,0) - \endcode -
- - - Low latency power management policy use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_LOW_LATENCY_POLICY, NULL,0) - \endcode -
- - - Low power management policy use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_LOW_POWER_POLICY, NULL,0) - \endcode -
- - - Always on power management policy use: - \code - sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_ALWAYS_ON_POLICY, NULL,0) - \endcode -
- - - Long Sleep Interval policy use: - \code - SlWlanPmPolicyParams_t PmPolicyParams; - memset(&PmPolicyParams,0,sizeof(SlWlanPmPolicyParams_t)); - PmPolicyParams.MaxSleepTimeMs = 800; //max sleep time in mSec - sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_LONG_SLEEP_INTERVAL_POLICY, (_u8*)&PmPolicyParams,sizeof(PmPolicyParams)); - \endcode -
- - - IOT low power policy use: - \code - SlWlanPmPolicyParams_t PmPolicyParams; - memset(&PmPolicyParams,0,sizeof(SlWlanPmPolicyParams_t)); - PmPolicyParams.MaxSleepTimeMs = IOTLP_MIN_DURATION_IN_MSEC; //min sleep duration in mSec - sl_WlanPolicySet(SL_WLAN_POLICY_PM , SL_WLAN_IOT_LOW_POWER_POLICY, (uint8_t *)&PmPolicyParams, sizeof(PmPolicyParams)); - \endcode -
- - SL_WLAN_POLICY_P2P:
defines p2p negotiation policy parameters for P2P role: - - To set intent negotiation value, set on of the following:\n - SL_WLAN_P2P_ROLE_NEGOTIATE - intent 3 \n - SL_WLAN_P2P_ROLE_GROUP_OWNER - intent 15 \n - SL_WLAN_P2P_ROLE_CLIENT - intent 0 \n -
- - To set negotiation initiator value (initiator policy of first negotiation action frame), set on of the following: \n - SL_WLAN_P2P_NEG_INITIATOR_ACTIVE \n - SL_WLAN_P2P_NEG_INITIATOR_PASSIVE \n - SL_WLAN_P2P_NEG_INITIATOR_RAND_BACKOFF \n - \code - sl_WlanPolicySet(SL_WLAN_POLICY_P2P, SL_WLAN_P2P_POLICY(SL_WLAN_P2P_ROLE_NEGOTIATE,SL_WLAN_P2P_NEG_INITIATOR_RAND_BACKOFF),NULL,0); - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_WlanPolicySet) -_i16 sl_WlanPolicySet(const _u8 Type , const _u8 Policy, _u8 *pVal,const _u8 ValLen); -#endif -/*! - \brief Get policy values - - \param[in] Type - - SL_WLAN_POLICY_CONNECTION - - SL_WLAN_POLICY_SCAN - - SL_WLAN_POLICY_PM, SL_WLAN_POLICY_P2P - \param[out] pPolicy argument may be set to any value - \param[out] pVal The returned values, depends on each policy type, will be stored in the allocated buffer pointed by pVal - with a maximum buffer length set by the calling function and pointed to by argument *pValLen - \param[out] pValLen actual value length - \return Zero on success, or negative error code on failure - - \sa sl_WlanPolicySet - - \note belongs to \ref ext_api - - \warning The value pointed by the argument *pValLen should be set to a value different from 0 and - greater than the buffer length returned from the SL device. Otherwise, an error will be returned. - - \par Example - - - SL_WLAN_POLICY_CONNECTION - Get connection policy: - \code - _u8 Policy = 0; - int length = sizeof(PolicyOption); - int ret; - ret = sl_WlanPolicyGet(SL_WLAN_POLICY_CONNECTION ,&Policy,0,(_u8*)&length); - - if (Policy & SL_WLAN_CONNECTION_POLICY(1, 1 , 0 , 0 )) - { - printf("Connection Policy is set to Auto + Fast"); - } - \endcode -
- - - SL_WLAN_POLICY_SCAN - Get scan policy: - \code - int ScanInterval = 0; //default value is 600 seconds - _u8 Policy = 0; //default value is 0 (disabled) - int ret; - length = sizeof(ScanInterval); - ret = sl_WlanPolicyGet(SL_WLAN_POLICY_SCAN ,&Policy,(_u8*)&ScanInterval,(_u8*)&length); - - if (Policy & SL_WLAN_SCAN_POLICY(0 ,1)) - { - printf("Scan Policy is set to Scan visible ssid "); - } - if (Policy & SL_WLAN_SCAN_POLICY(1, 0)) - { - printf("Scan Policy is set to Scan hidden ssid "); - } - \endcode -
- - - SL_WLAN_POLICY_PM - Get power management policy: - \code - _u8 Policy = 0; - int ret; - SlWlanPmPolicyParams_t PmPolicyParams; - length = sizeof(PmPolicyParams); - ret = sl_WlanPolicyGet(SL_POLICY_PM ,&Policy,&PmPolicyParams,(_u8*)&length); - if (Policy == SL_WLAN_LONG_SLEEP_INTERVAL_POLICY ) - { - printf("Connection Policy is set to LONG SLEEP INTERVAL POLICY with interval = %d ",PmPolicyParams.MaxSleepTimeMs); - } - \endcode -
- - - SL_WLAN_POLICY_P2P - Get P2P policy: - \code - _u8 Policy = 0; - int ret; - length = sizeof(Policy); - ret = sl_WlanPolicyGet(SL_WLAN_POLICY_P2P ,&Policy,0,(_u8*)&length); - //SL_WLAN_P2P_POLICY(p2pNegType, p2pNegInitiator) - if (Policy & SL_WLAN_P2P_POLICY(0,SL_WLAN_P2P_NEG_INITIATOR_RAND_BACKOFF)) - { - printf("P2P Policy is set to Rand backoff"); - } - if (Policy & SL_WLAN_P2P_POLICY(SL_WLAN_P2P_ROLE_NEGOTIATE,0)) - { - printf("P2P Policy is set to Role Negotiate"); - } - \endcode -
- -*/ -#if _SL_INCLUDE_FUNC(sl_WlanPolicyGet) -_i16 sl_WlanPolicyGet(const _u8 Type ,_u8 *pPolicy,_u8 *pVal,_u8 *pValLen); -#endif -/*! - \brief Gets the WLAN scan operation results - - Gets scan results , gets entry from scan result table - - \param[in] Index Starting index identifier (range 0-29) for getting scan results - \param[in] Count How many entries to fetch. Max is (30-"Index"). - \param[out] pEntries Pointer to an allocated SlWlanNetworkEntry_t. - The number of array items should match "Count" \n - sec_type: - - SL_WLAN_SCAN_SEC_TYPE_OPEN - - SL_WLAN_SCAN_SEC_TYPE_WEP - - SL_WLAN_SCAN_SEC_TYPE_WPA - - SL_WLAN_SCAN_SEC_TYPE_WPA2 - - \return Number of valid networks list items - \sa - \note belongs to \ref ext_api - \warning This command do not initiate any active scanning action - \par Example - - - Fetching max 10 results: - \code - SlWlanNetworkEntry_t netEntries[10]; - _u8 i; - _i16 resultsCount = sl_WlanGetNetworkList(0,10,&netEntries[0]); - for(i=0; i< resultsCount; i++) - { - printf("%d. ",i+1); - printf("SSID: %.32s ",netEntries[i].Ssid); - printf("BSSID: %x:%x:%x:%x:%x:%x ",netEntries[i].Bssid[0],netEntries[i].Bssid[1],netEntries[i].Bssid[2],netEntries[i].Bssid[3],netEntries[i].Bssid[4],netEntries[i].Bssid[5]); - printf("Channel: %d ",netEntries[i].Channel); - printf("RSSI: %d ",netEntries[i].Rssi); - printf("Security type: %d ",SL_WLAN_SCAN_RESULT_SEC_TYPE_BITMAP(netEntries[i].SecurityInfo)); - printf("Group Cipher: %d ",SL_WLAN_SCAN_RESULT_GROUP_CIPHER(netEntries[i].SecurityInfo)); - printf("Unicast Cipher bitmap: %d ",SL_WLAN_SCAN_RESULT_UNICAST_CIPHER_BITMAP(netEntries[i].SecurityInfo)); - printf("Key Mgmt suites bitmap: %d ",SL_WLAN_SCAN_RESULT_KEY_MGMT_SUITES_BITMAP(netEntries[i].SecurityInfo)); - printf("Hidden SSID: %d\r\n",SL_WLAN_SCAN_RESULT_HIDDEN_SSID(netEntries[i].SecurityInfo)); - } - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_WlanGetNetworkList) -_i16 sl_WlanGetNetworkList(const _u8 Index,const _u8 Count, SlWlanNetworkEntry_t *pEntries); -#endif - -/*! - \brief Gets the WLAN scan operation results - - Gets scan results with extended information (Country info), gets entry from scan result table - - \param[in] Index Starting index identifier (range 0-29) for getting scan results - \param[in] Count How many entries to fetch. Max is (30-"Index"). - \param[out] pEntries Pointer to an allocated SlWlanExtNetworkEntry_t. - The number of array items should match "Count" \n - sec_type: - - SL_WLAN_SCAN_SEC_TYPE_OPEN - - SL_WLAN_SCAN_SEC_TYPE_WEP - - SL_WLAN_SCAN_SEC_TYPE_WPA - - SL_WLAN_SCAN_SEC_TYPE_WPA2 - - \return Number of valid networks list items - \sa - \note belongs to \ref ext_api - \warning This command do not initiate any active scanning action - \par Example - - - Fetching max 10 results: - \code - SlWlanExtNetworkEntry_t netEntries[10]; - _u8 i; - _i16 resultsCount = sl_WlanGetExtNetworkList(0,10,&netEntries[0]); - for(i=0; i< resultsCount; i++) - { - printf("%d. ",i+1); - printf("SSID: %.32s ",netEntries[i].Ssid); - printf("BSSID: %x:%x:%x:%x:%x:%x ",netEntries[i].Bssid[0],netEntries[i].Bssid[1],netEntries[i].Bssid[2],netEntries[i].Bssid[3],netEntries[i].Bssid[4],netEntries[i].Bssid[5]); - printf("Channel: %d ",netEntries[i].Channel); - printf("RSSI: %d ",netEntries[i].Rssi); - printf("Security type: %d ",SL_WLAN_SCAN_RESULT_SEC_TYPE_BITMAP(netEntries[i].SecurityInfo)); - printf("Group Cipher: %d ",SL_WLAN_SCAN_RESULT_GROUP_CIPHER(netEntries[i].SecurityInfo)); - printf("Unicast Cipher bitmap: %d ",SL_WLAN_SCAN_RESULT_UNICAST_CIPHER_BITMAP(netEntries[i].SecurityInfo)); - printf("Key Mgmt suites bitmap: %d ",SL_WLAN_SCAN_RESULT_KEY_MGMT_SUITES_BITMAP(netEntries[i].SecurityInfo)); - printf("Hidden SSID: %d\r\n",SL_WLAN_SCAN_RESULT_HIDDEN_SSID(netEntries[i].SecurityInfo)); - // extended area - printf("CountryStr=%c%c\r\n", netEntries[i].CountryStr[0], netEntries[i].CountryStr[1]); - printf("0x%04x \r\n", netEntries[i].Supported_2_4G_Channels); - printf("0x%08x \r\n", netEntries[i].Supported_5_0G_Channels); - } - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_WlanGetExtNetworkList) -_i16 sl_WlanGetExtNetworkList(const _u8 Index,const _u8 Count, SlWlanExtNetworkEntry_t *pEntries); -#endif - -/*! - \brief Start collecting wlan RX statistics, for unlimited time. - - \par Parameters - None - \return Zero on success, or negative error code on failure - - \sa sl_WlanRxStatStop sl_WlanRxStatGet - \note Belongs to \ref ext_api - \warning This API is deprecated and should be removed for next release - \par Example - - - Getting wlan RX statistics: - \code - void RxStatCollectTwice() - { - SlWlanGetRxStatResponse_t rxStat; - _i16 rawSocket; - _i8 DataFrame[200]; - struct SlTimeval_t timeval; - timeval.tv_sec = 0; // Seconds - timeval.tv_usec = 20000; // Microseconds. 10000 microseconds resolution - - sl_WlanRxStatStart(); // set statistics mode - - rawSocket = sl_Socket(SL_AF_RF, SL_SOCK_RAW, eChannel); - // set timeout - in case we have no activity for the specified channel - sl_SetSockOpt(rawSocket,SL_SOL_SOCKET,SL_SO_RCVTIMEO, &timeval, sizeof(timeval)); // Enable receive timeout - status = sl_Recv(rawSocket, DataFrame, sizeof(DataFrame), 0); - - Sleep(1000); // sleep for 1 sec - sl_WlanRxStatGet(&rxStat,0); // statistics has been cleared upon read - Sleep(1000); // sleep for 1 sec - sl_WlanRxStatGet(&rxStat,0); - } - \endcode -*/ -#if _SL_INCLUDE_FUNC(sl_WlanRxStatStart) -_i16 sl_WlanRxStatStart(void); -#endif - -/*! - \brief Stop collecting wlan RX statistic, (if previous called sl_WlanRxStatStart) - - \par Parameters - None - \return Zero on success, or negative error code on failure - - \sa sl_WlanRxStatStart sl_WlanRxStatGet - \note Belongs to \ref ext_api - \warning This API is deprecated and should be removed for next release -*/ -#if _SL_INCLUDE_FUNC(sl_WlanRxStatStop) -_i16 sl_WlanRxStatStop(void); -#endif - - -/*! - \brief Get wlan RX statistics. Upon calling this command, the statistics counters will be cleared. - - \param[in] pRxStat Pointer to SlWlanGetRxStatResponse_t filled with Rx statistics results - \param[in] Flags Should be 0 ( not applicable right now, will be added the future ) - \return Zero on success, or negative error code on failure - - \sa sl_WlanRxStatStart sl_WlanRxStatStop - \note Belongs to \ref ext_api - \warning -*/ -#if _SL_INCLUDE_FUNC(sl_WlanRxStatGet) -_i16 sl_WlanRxStatGet(SlWlanGetRxStatResponse_t *pRxStat,const _u32 Flags); -#endif - - -/*! - \brief The simpleLink will switch to the appropriate role according to the provisioning mode requested - and will start the provisioning process. - - \param[in] ProvisioningCmd - - SL_WLAN_PROVISIONING_CMD_START_MODE_AP 0: Start AP provisioning (AP role) - - SL_WLAN_PROVISIONING_CMD_START_MODE_SC 1: Start Smart Config provisioning (STA role) - - SL_WLAN_PROVISIONING_CMD_START_MODE_APSC 2: Start AP+Smart Config provisioning (AP role) - - SL_WLAN_PROVISIONING_CMD_START_MODE_APSC_EXTERNAL_CONFIGURATION 3: Start AP + Smart Config + WAC provisioning (AP role) - - SL_WLAN_PROVISIONING_CMD_STOP 4: Stop provisioning - - SL_WLAN_PROVISIONING_CMD_ABORT_EXTERNAL_CONFIGURATIONC 5: - \param[in] RequestedRoleAfterSuccess The role that the SimpleLink will switch to in case of a successful provisioning. - 0: STA - 2: AP - 0xFF: stay in current role (relevant only in provisioning_stop) - \param[in] InactivityTimeoutSec - The period of time (in seconds) the system waits before it automatically - stops the provisioning process when no activity is detected. - set to 0 in order to stop provisioning. Minimum InactivityTimeoutSec is 30 seconds. - \param[in] pSmartConfigKey Smart Config key: public key for smart config process (relevant for smart config only) - \param[in] Flags Can have the following values: - - SL_WLAN_PROVISIONING_CMD_FLAG_EXTERNAL_CONFIRMATION - Confirmation phase will be completed externally by host (e.g. via cloud assist) - - - \return Zero on success, or negative error code on failure - - \sa - \warning - \par Example - - - Start Provisioning - start as STA after success with inactivity timeout of 10 minutes: - \code - sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_START_MODE_APSC, ROLE_STA, 600, "Key0Key0Key0Key0", 0x0); - \endcode -
- - - Stop Provisioning: - \code - sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_STOP,0xFF,0,NULL, 0x0); - \endcode -
- - - Start AP Provisioning with inactivity timeout of 10 minutes - \code - sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_START_MODE_APSC,ROLE_AP,600,NULL, 0x0); - \endcode -
- - - Start AP Provisioning with inactivity timeout of 10 minutes and complete confirmation via user cloud assist - \code - sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_START_MODE_APSC, ROLE_AP, 600, NULL, SL_WLAN_PROVISIONING_CMD_FLAG_EXTERNAL_CONFIRMATION); - \endcode -
- -*/ - -#if _SL_INCLUDE_FUNC(sl_WlanProvisioning) -_i16 sl_WlanProvisioning(_u8 ProvisioningCmd, _u8 RequestedRoleAfterSuccess, _u16 InactivityTimeoutSec, char *pSmartConfigKey, _u32 Flags); -#endif - - - -/*! - \brief Wlan set mode - - Setting WLAN mode - - \param[in] Mode WLAN mode to start the CC31xx device. Possible options are - - ROLE_STA - for WLAN station mode - - ROLE_AP - for WLAN AP mode - - ROLE_P2P -for WLAN P2P mode - - ROLE_TAG -for TAG mode - WLAN STA not connected - \return Zero on success, or negative error code on failure - \par Persistent - Mode is Persistent - \sa sl_Start sl_Stop - \note Belongs to \ref ext_api - \warning After setting the mode the system must be restarted for activating the new mode - \par Example - - - Switch from any role to STA: - \code - sl_WlanSetMode(ROLE_STA); - sl_Stop(0); - sl_Start(NULL,NULL,NULL); - \endcode - -*/ -#if _SL_INCLUDE_FUNC(sl_WlanSetMode) -_i16 sl_WlanSetMode(const _u8 Mode); -#endif - - -/*! - \brief Setting WLAN configurations - - \param[in] ConfigId - configuration id - - SL_WLAN_CFG_AP_ID - - SL_WLAN_CFG_GENERAL_PARAM_ID - - SL_WLAN_CFG_P2P_PARAM_ID - - SL_WLAN_RX_FILTERS_ID - - \param[in] ConfigOpt - configurations option - - SL_WLAN_CFG_AP_ID - - SL_WLAN_AP_OPT_SSID \n - Set SSID for AP mode. \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_OPT_CHANNEL \n - Set channel for AP mode. \n - The channel is dependant on the country code which is set. i.e. for "US" the channel should be in the range of [1-11] \n - This option takes _u8 as a parameter - - SL_WLAN_AP_OPT_HIDDEN_SSID \n - Set Hidden SSID Mode for AP mode.Hidden options: \n - 0: disabled \n - 1: Send empty (length=0) SSID in beacon and ignore probe request for broadcast SSID \n - 2: Clear SSID (ASCII 0), but keep the original length (this may be required with some \n - clients that do not support empty SSID) and ignore probe requests for broadcast SSID \n - This option takes _u8 as a parameter - - SL_WLAN_AP_OPT_SECURITY_TYPE \n - Set Security type for AP mode. Security options are: - - Open security: SL_WLAN_SEC_TYPE_OPEN - - WEP security: SL_WLAN_SEC_TYPE_WEP - - WPA security: SL_WLAN_SEC_TYPE_WPA_WPA2 \n - This option takes _u8 pointer as a parameter - - SL_WLAN_AP_OPT_PASSWORD \n - Set Password for for AP mode (for WEP or for WPA): \n - Password - for WPA: 8 - 63 characters \n - for WEP: 5 / 13 characters (ascii) \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_OPT_MAX_STATIONS \n - Set Max AP stations - 1..4 - Note: can be less than the number of currently connected stations \n - max_stations - 1 characters \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_OPT_MAX_STA_AGING \n - Set Max station ageing time - default is 60 seconds \n - max_stations - 2 characters \n - This options takes _u16 buffer as parameter - - SL_WLAN_AP_ACCESS_LIST_MODE \n - Set AP access list mode - DISABLE, DENY_LIST \n - mode - 1 characters \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_ACCESS_LIST_ADD_MAC \n - Add MAC address to the AP access list: \n - mac_addr - 6 characters \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_ACCESS_LIST_DEL_MAC \n - Del MAC address from the AP access list: \n - mac_addr - 6 characters \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_ACCESS_LIST_DEL_IDX \n - Delete MAC address from index in the AP access list: \n - index - 1 character \n - This options takes _u8 buffer as parameter - - - SL_WLAN_CFG_GENERAL_PARAM_ID - - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE \n - Set Country Code for AP mode \n - This options takes _u8 2 bytes buffer as parameter - - SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER \n - Set STA mode Tx power level \n - Number between 0-15, as dB offset from max power (0 will set MAX power) \n - This options takes _u8 as parameter - - SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER - Set AP mode Tx power level for 2.4GHz channels only \n - Number between 0-15, as dB offset from max power (0 will set MAX power) \n - This options takes _u8 as parameter - - SL_WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT - Set Info Element for AP mode. \n - The Application can set up to SL_WLAN_MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED info elements per Role (AP / P2P GO). \n - To delete an info element use the relevant index and length = 0. \n - For AP - no more than SL_WLAN_INFO_ELEMENT_MAX_TOTAL_LENGTH_AP bytes can be stored for all info elements. \n - For P2P GO - no more than SL_WLAN_INFO_ELEMENT_MAX_TOTAL_LENGTH_P2P_GO bytes can be stored for all info elements. \n - This option takes SlWlanSetInfoElement_t as parameter - - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS - Set scan parameters: RSSI threshold and channel mask. - - SL_WLAN_GENERAL_PARAM_OPT_SUSPEND_PROFILES - Set suspended profiles mask (set bits 2 and 4 to suspend profiles 2 and 4). - - SL_WLAN_GENERAL_PARAM_REGISTER_LINK_QUALITY_EVENT - Register to receive events regarding the link quality - - SL_WLAN_GENERAL_PARAM_COEX_CONFIG - Configure co-existing to work with both WIFI and BLE - Enables the feature and define the GPIO to work with. - - SL_WLAN_GENERAL_PARAM_ANT_SELECTION_CONFIG - Enable using 2 Antennas ,configure which pad to use for each antenna and the configuration mode. - - SL_WLAN_GENERAL_PARAM_ANT_SELECTION_SET - Setting the desired antenna when antenna selection is set to manual mode. Applicable to CC3x20 devices only. - - SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH - This option enables to skip server authentication and is valid for one - use, when manually connection to an enterprise network - - SL_WLAN_GENERAL_PARAM_OPT_ENABLE_5G - This option allowes to enable or disable the 5Ghz functionallity - - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS_5G - Configure 5G scan parameters - - SL_WLAN_GENERAL_PARAM_OPT_USER_COUNTRY_ATTRIB - Set user country region attributes - - - SL_WLAN_CFG_P2P_PARAM_ID - - SL_WLAN_P2P_OPT_DEV_TYPE \n - Set P2P Device type.Maximum length of 17 characters. Device type is published under P2P I.E, \n - allows to make devices easier to recognize. \n - In case no device type is set, the default type is "1-0050F204-1" \n - This options takes _u8 buffer as parameter - - SL_WLAN_P2P_OPT_CHANNEL_N_REGS \n - Set P2P Channels. \n - listen channel (either 1/6/11 for 2.4GHz) \n - listen regulatory class (81 for 2.4GHz) \n - oper channel (either 1/6/11 for 2.4GHz) \n - oper regulatory class (81 for 2.4GHz) \n - listen channel and regulatory class will determine the device listen channel during p2p find listen phase \n - oper channel and regulatory class will determine the operating channel preferred by this device (in case it is group owner this will be the operating channel) \n - channels should be one of the social channels (1/6/11). In case no listen/oper channel selected, a random 1/6/11 will be selected. - This option takes pointer to _u8[4] as parameter - - - SL_WLAN_RX_FILTERS_ID - - SL_WLAN_RX_FILTER_STATE \n - Enable or disable filters. The buffer input is SlWlanRxFilterOperationCommandBuff_t\n - - SL_WLAN_RX_FILTER_SYS_STATE \n - Enable or disable system filters. The buffer input is SlWlanRxFilterSysFiltersSetStateBuff_t\n - - SL_WLAN_RX_FILTER_REMOVE \n - Remove filters. The buffer input is SlWlanRxFilterOperationCommandBuff_t\n - - SL_WLAN_RX_FILTER_STORE \n - Save the filters as persistent. \n - - SL_WLAN_RX_FILTER_UPDATE_ARGS \n - Update filter arguments. The buffer input is SlWlanRxFilterUpdateArgsCommandBuff_t\n - - \param[in] ConfigLen - configurations len - - \param[in] pValues - configurations values - - \return Zero on success, or negative error code on failure - - \par Persistent - System Persistent: - - SL_WLAN_CFG_GENERAL_PARAM_ID - - SL_WLAN_CFG_P2P_PARAM_ID - - Reset: - - SL_WLAN_CFG_AP_ID - - Non- Persistent: - - SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH - \sa - \note - \warning - \par Examples - - - SL_WLAN_AP_OPT_SSID: - \code - _u8 str[33]; - memset(str, 0, 33); - memcpy(str, ssid, len); // ssid string of 32 characters - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_SSID, strlen(ssid), str); - \endcode -
- - - SL_WLAN_AP_OPT_CHANNEL: - \code - _u8 val = channel; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_CHANNEL, 1, (_u8 *)&val); - \endcode -
- - - SL_WLAN_AP_OPT_HIDDEN_SSID: - \code - _u8 val = hidden; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_HIDDEN_SSID, 1, (_u8 *)&val); - \endcode -
- - - SL_WLAN_AP_OPT_SECURITY_TYPE: - \code - _u8 val = SL_WLAN_SEC_TYPE_WPA_WPA2; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_SECURITY_TYPE, 1, (_u8 *)&val); - \endcode -
- - - SL_WLAN_AP_OPT_PASSWORD: - \code - _u8 str[65]; - _u16 len = strlen(password); - memset(str, 0, 65); - memcpy(str, password, len); - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_PASSWORD, len, (_u8 *)str); - \endcode -
- - - SL_WLAN_AP_OPT_MAX_STATIONS: - \code - _u8 max_ap_stations = 3; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_MAX_STATIONS, sizeof(max_ap_stations), (_u8 *)&max_ap_stations); - \endcode -
- - - SL_WLAN_AP_OPT_MAX_STA_AGING: - \code - _u16 max_ap_sta_aging = 60; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_OPT_MAX_STA_AGING, sizeof(max_ap_sta_aging), (_u8 *)&max_ap_sta_aging); - \endcode -
- - - SL_WLAN_AP_ACCESS_LIST_MODE: - \code - _u8 access list_mode = SL_WLAN_AP_ACCESS_LIST_MODE_DENY_LIST; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_ACCESS_LIST_MODE, sizeof(access list_mode), (_u8 *)&access list_mode); - \endcode -
- - - SL_WLAN_AP_ACCESS_LIST_ADD_MAC: - \code - _u8 sta_mac[6] = { 0x00, 0x22, 0x33, 0x44, 0x55, 0x66 }; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_ACCESS_LIST_ADD_MAC, sizeof(sta_mac), (_u8 *)&sta_mac); - \endcode -
- - - SL_WLAN_AP_ACCESS_LIST_DEL_MAC: - \code - _u8 sta_mac[6] = { 0x00, 0x22, 0x33, 0x44, 0x55, 0x66 }; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_ACCESS_LIST_DEL_MAC, sizeof(sta_mac), (_u8 *)&sta_mac); - \endcode -
- - - SL_WLAN_AP_ACCESS_LIST_DEL_IDX: - \code - _u8 sta_index = 0; - sl_WlanSet(SL_WLAN_CFG_AP_ID, SL_WLAN_AP_ACCESS_LIST_DEL_IDX, sizeof(sta_index), (_u8 *)&sta_index); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER: - \code - _u8 stapower=(_u8)power; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER,1,(_u8 *)&stapower); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE: - \code - _u8* str = (_u8 *) country; // string of 2 characters. i.e. - "US" - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE, 2, str); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER: - \code - _u8 appower=(_u8)power; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER,1,(_u8 *)&appower); - \endcode -
- - - WLAN_GENERAL_PARAM_REGISTER_LINK_QUALITY_EVENT: - \code - SlWlanRegisterLinkQualityEvents_t RegisterLinkQuality; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, WLAN_GENERAL_PARAM_REGISTER_LINK_QUALITY_EVENT,sizeof(SlWlanRegisterLinkQualityEvents_t),(_u8 *)&RegisterLinkQuality); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_SUSPEND_PROFILES - \code - _u32 suspendedProfilesMask=(_u32)mask; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, SL_WLAN_GENERAL_PARAM_OPT_SUSPEND_PROFILES,sizeof(suspendedProfilesMask),(_u32 *)&suspendedProfilesMask); - \endcode -
- - - SL_WLAN_P2P_OPT_DEV_TYPE: - \code - _u8 str[17]; - _u16 len = strlen(device_type); - memset(str, 0, 17); - memcpy(str, device_type, len); - sl_WlanSet(SL_WLAN_CFG_P2P_PARAM_ID, SL_WLAN_P2P_OPT_DEV_TYPE, len, str); - \endcode -
- - - SL_WLAN_P2P_OPT_CHANNEL_N_REGS - \code - _u8 str[4]; - str[0] = (_u8)11; // listen channel - str[1] = (_u8)81; // listen regulatory class - str[2] = (_u8)6; // oper channel - str[3] = (_u8)81; // oper regulatory class - sl_WlanSet(SL_WLAN_CFG_P2P_PARAM_ID, SL_WLAN_P2P_OPT_CHANNEL_N_REGS, 4, str); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT: - \code - SlWlanSetInfoElement_t infoele; - infoele.Index = Index; // Index of the info element. range: 0 - SL_WLAN_MAX_PRIVATE_INFO_ELEMENTS_SUPPROTED - infoele.Role = Role; // SL_WLAN_INFO_ELEMENT_AP_ROLE (0) or SL_WLAN_INFO_ELEMENT_P2P_GO_ROLE (1) - infoele.IE.Id = Id; // Info element ID. if SL_WLAN_INFO_ELEMENT_DEFAULT_ID (0) is set, ID will be set to 221. - // Organization unique ID. If all 3 bytes are zero - it will be replaced with 08,00,28. - infoele.IE.Oui[0] = Oui0; // Organization unique ID first Byte - infoele.IE.Oui[1] = Oui1; // Organization unique ID second Byte - infoele.IE.Oui[2] = Oui2; // Organization unique ID third Byte - infoele.IE.Length = Len; // Length of the info element. must be smaller than 253 bytes - memset(infoele.IE.Data, 0, SL_WLAN_INFO_ELEMENT_MAX_SIZE); - if ( Len <= SL_WLAN_INFO_ELEMENT_MAX_SIZE ) - { - memcpy(infoele.IE.Data, IE, Len); // Info element. length of the info element is [0-252] - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID,SL_WLAN_GENERAL_PARAM_OPT_INFO_ELEMENT,sizeof(SlWlanSetInfoElement_t),(_u8* ) &infoele); - } - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS: - \code - SlWlanScanParamCommand_t ScanParamConfig; - _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS; - _u16 OptionLen = sizeof(ScanParamConfig); - // 2.4G channels bits order: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 - - ScanParamConfig.RssiThreshold = -70; - ScanParamConfig.ChannelsMask = 0x1FFF; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, &Option, &OptionLen, (_u8 *)&ScanParamConfig); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS: - \code - SlWlanScanParam5GCommand_t ScanParamConfig5G; - _u16 Option = WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS_5G; - _u16 OptionLen = sizeof(SlWlanScanParam5GCommand_t); - // 5.0G channels bits order: 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, - // 136, 140, 144, 149, 153, 157, 161, 165, 169, 184, 188, 192, 196 - - ScanParamConfig5G.ChannelsMask = 0x0000000F; // Select ChannelsMask for channels 36, 40, 44, 48 - ScanParamConfig5G.RssiThershold = -70; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, &Option, &OptionLen, (_u8 *)&ScanParamConfig5G); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH: - \code - _u8 param = 1; // 1 means disable the server authentication - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID,SL_WLAN_GENERAL_PARAM_DISABLE_ENT_SERVER_AUTH,1,¶m); - \endcode -
- - SL_WLAN_RX_FILTER_STORE: - \code - sl_WlanSet(SL_WLAN_RX_FILTERS_ID, SL_WLAN_RX_FILTER_STORE, 0, NULL); - \endcode - - - SL_WLAN_GENERAL_PARAM_ANT_SELECTION_CONFIG: - \code - //The configuration will take place after soft reset of the networking subsystem( sl_stop(),sl_star()) - SlWlanAntSelectionConfig_t param; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID,WLAN_GENERAL_PARAM_ANT_SELECTION_CONFIG,sizeof(SlWlanAntSelectionConfig_t), (_u8* )¶m); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_ANT_SELECTION_SET: - \code - SetAntennaIndex_t param; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID,SL_WLAN_GENERAL_PARAM_ANT_SELECTION_SET,sizeof(SetAntennaIndex_t), (_u8* )¶m); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_COEX_CONFIG: - \code - //The configuration will take place after soft reset of the networking subsystem( sl_stop(),sl_star()) - SlWlanCoexConfig_t param; - sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID,SL_WLAN_GENERAL_PARAM_COEX_CONFIG,sizeof(SlWlanCoexConfig_t),¶m); - \endcode -
-*/ -#if _SL_INCLUDE_FUNC(sl_WlanSet) -_i16 sl_WlanSet(const _u16 ConfigId ,const _u16 ConfigOpt,const _u16 ConfigLen,const _u8 *pValues); -#endif - -/*! - \brief Getting WLAN configurations - - \param[in] ConfigId - configuration id - - SL_WLAN_CFG_AP_ID - - SL_WLAN_CFG_GENERAL_PARAM_ID - - SL_WLAN_CFG_P2P_PARAM_ID - - SL_WLAN_CFG_AP_ACCESS_LIST_ID - - SL_WLAN_RX_FILTERS_ID - - \param[out] pConfigOpt - get configurations option - - SL_WLAN_CFG_AP_ID - - SL_WLAN_AP_OPT_SSID \n - Get SSID for AP mode. \n - Get up to 32 characters of SSID \n - This options takes _u8 as parameter - - SL_WLAN_AP_OPT_CHANNEL \n - Get channel for AP mode. \n - This option takes _u8 as a parameter - - SL_WLAN_AP_OPT_HIDDEN_SSID \n - Get Hidden SSID Mode for AP mode.Hidden options: \n - 0: disabled \n - 1: Send empty (length=0) SSID in beacon and ignore probe request for broadcast SSID \n - 2: Clear SSID (ASCII 0), but keep the original length (this may be required with some \n - clients that do not support empty SSID) and ignore probe requests for broadcast SSID \n - This option takes _u8 as a parameter - - SL_WLAN_AP_OPT_SECURITY_TYPE \n - Get Security type for AP mode. Security options are: - - Open security: SL_WLAN_SEC_TYPE_OPEN - - WEP security: SL_WLAN_SEC_TYPE_WEP - - WPA security: SL_WLAN_SEC_TYPE_WPA_WPA2 \n - This option takes _u8 as a parameter - - SL_WLAN_AP_OPT_PASSWORD \n - Get Password for for AP mode (for WEP or for WPA): \n - Returns password - string, fills up to 64 characters. \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_OPT_MAX_STATIONS \n - Get Max AP allowed stations: \n - This options takes _u8 buffer as parameter - - SL_WLAN_AP_OPT_MAX_STA_AGING \n - Get AP aging time in seconds: \n - This options takes _u16 buffer as parameter - - SL_WLAN_AP_ACCESS_LIST_NUM_ENTRIES \n - Get AP access list number of entries: \n - This options takes _u8 buffer as parameter - - SL_WLAN_CFG_AP_ACCESS_LIST_ID - - The option is the start index in the access list \n - Get the AP access list from start index, the number of entries in the list is extracted from the request length. - - SL_WLAN_GENERAL_PARAM_ANT_SELECTION_GET - Getting the desired antenna when antenna selection is set to manual mode. Applicable to CC3x20 devices only. - - SL_WLAN_CFG_GENERAL_PARAM_ID - - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS \n - Get scan parameters. - This option uses SlWlanScanParamCommand_t as parameter - - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE \n - Get Country Code for AP mode \n - This options takes _u8 buffer as parameter - - SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER \n - Get STA mode Tx power level \n - Number between 0-15, as dB offset from max power (0 indicates MAX power) \n - This options takes _u8 as parameter - - SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER - Get AP mode Tx power level \n - Number between 0-15, as dB offset from max power (0 indicates MAX power) \n - This options takes _u8 as parameter - - SL_WLAN_GENERAL_PARAM_OPT_ENABLE_5G - Get current state of 5G mode - - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS_5G - Get 5G user scan parameters - - SL_WLAN_GENERAL_PARAM_OPT_USER_COUNTRY_ATTRIB - Get user user country attributes - - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_ATTRIB - Get current country attributes (No way to set country attributes, See also country list in Appendix C) - - SL_WLAN_CFG_P2P_PARAM_ID - - SL_WLAN_P2P_OPT_CHANNEL_N_REGS \n - Get P2P Channels. \n - listen channel (either 1/6/11 for 2.4GHz) \n - listen regulatory class (81 for 2.4GHz) \n - oper channel (either 1/6/11 for 2.4GHz) \n - oper regulatory class (81 for 2.4GHz) \n - listen channel and regulatory class will determine the device listen channel during p2p find listen phase \n - oper channel and regulatory class will determine the operating channel preferred by this device (in case it is group owner this will be the operating channel) \n - channels should be one of the social channels (1/6/11). In case no listen/oper channel selected, a random 1/6/11 will be selected. \n - This option takes pointer to _u8[4] as parameter - - SL_WLAN_RX_FILTERS_ID - - SL_WLAN_RX_FILTER_STATE \n - Retrieves the filters enable/disable status. The buffer input is SlWlanRxFilterRetrieveStateBuff_t \n - - SL_WLAN_RX_FILTER_SYS_STATE \n - Retrieves the system filters enable/disable status. The buffer input is SlWlanRxFilterSysFiltersRetrieveStateBuff_t: - - \param[out] pConfigLen - The length of the allocated memory as input, when the - function complete, the value of this parameter would be - the len that actually read from the device. - If the device return length that is longer from the input - value, the function will cut the end of the returned structure - and will return SL_ESMALLBUF. - - - \param[out] pValues - get configurations values - \return Zero on success, or negative error code on failure - \sa sl_WlanSet - \note - In case the device was started as AP mode, but no SSID was set, the Get SSID will return "mysimplelink" and not "mysimplelink-xxyyzz" - \warning - \par Examples - - - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS: - \code - SlWlanScanParamCommand_t ScanParamConfig; - _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS; - _u16 OptionLen = sizeof(SlWlanScanParamCommand_t); - sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&ScanParamConfig); - \endcode -
- - - WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS_5G: - \code - SlWlanScanParamCommand_t ScanParamConfig; - _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS; - _u16 OptionLen = sizeof(SlWlanScanParamCommand_t); - sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&ScanParamConfig); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS: - \code - SlWlanScanParamCommand_t ScanParamConfig; - _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_SCAN_PARAMS; - _u16 OptionLen = sizeof(SlWlanScanParamCommand_t); - sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&ScanParamConfig); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER: - \code - _i32 TXPower = 0; - _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_AP_TX_POWER; - _u16 OptionLen = sizeof(TXPower); - sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&TXPower); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPTSTA_TX_POWER: - \code - _i32 TXPower = 0; - _u16 Option = SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER; - _u16 OptionLen = sizeof(TXPower); - sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID ,&Option,&OptionLen,(_u8 *)&TXPower); - \endcode -
- - - SL_WLAN_P2P_OPT_DEV_TYPE: - \code - _i8 device_type[18]; - _u16 len = 18; - _u16 config_opt = SL_WLAN_P2P_OPT_DEV_TYPE; - sl_WlanGet(SL_WLAN_CFG_P2P_PARAM_ID, &config_opt , &len, (_u8* )device_type); - \endcode -
- - - SL_WLAN_AP_OPT_SSID: - \code - _i8 ssid[33]; - _u16 len = 33; - sl_Memset(ssid,0,33); - _u16 config_opt = SL_WLAN_AP_OPT_SSID; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt , &len, (_u8* )ssid); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE: - \code - _i8 country[3]; - _u16 len = 3; - _u16 config_opt = SL_WLAN_GENERAL_PARAM_OPT_COUNTRY_CODE; - sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID, &config_opt, &len, (_u8* )country); - \endcode -
- - - SL_WLAN_AP_OPT_CHANNEL: - \code - _i8 channel; - _u16 len = 1; - _u16 config_opt = SL_WLAN_AP_OPT_CHANNEL; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )&channel); - \endcode -
- - - SL_WLAN_AP_OPT_HIDDEN_SSID: - \code - _u8 hidden; - _u16 len = 1; - _u16 config_opt = SL_WLAN_AP_OPT_HIDDEN_SSID; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )&hidden); - \endcode -
- - - SL_WLAN_AP_OPT_SECURITY_TYPE: - \code - _u8 sec_type; - _u16 len = 1; - _u16 config_opt = SL_WLAN_AP_OPT_SECURITY_TYPE; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )&sec_type); - \endcode -
- - - SL_WLAN_AP_OPT_PASSWORD: - \code - _u8 password[64]; - _u16 len = 64; - sl_Memset(password,0,64); - _u16 config_opt = SL_WLAN_AP_OPT_PASSWORD; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8* )password); - \endcode -
- - - SL_WLAN_AP_OPT_MAX_STATIONS: - \code - _u8 max_ap_stations - _u16 len = 1; - _u16 config_opt = SL_WLAN_AP_OPT_MAX_STATIONS; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8 *)&max_ap_stations); - \endcode -
- - - SL_WLAN_AP_OPT_MAX_STA_AGING: - \code - _u16 ap_sta_aging; - _u16 len = 2; - _u16 config_opt = SL_WLAN_AP_OPT_MAX_STA_AGING; - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8 *)&ap_sta_aging); - \endcode -
- - - SL_WLAN_AP_ACCESS_LIST_NUM_ENTRIES: - \code - _u8 aclist_num_entries; - _u16 config_opt = SL_WLAN_AP_ACCESS_LIST_NUM_ENTRIES; - _u16 len = sizeof(aclist_num_entries); - sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, (_u8 *)&aclist_num_entries); - \endcode -
- - - SL_WLAN_CFG_AP_ACCESS_LIST_ID: - \code - _u8 aclist_mac[SL_WLAN_MAX_ACCESS_LIST_STATIONS][MAC_LEN]; - unsigned char aclist_num_entries; - unsigned short config_opt; - unsigned short len; - int actual_aclist_num_entries; - unsigned short start_aclist_index; - unsigned short aclist_info_len; - int i; - - start_aclist_index = 0; - aclist_info_len = 2*MAC_LEN; - sl_WlanGet(SL_WLAN_CFG_AP_ACCESS_LIST_ID, &start_aclist_index, &aclist_info_len, (_u8 *)&aclist_mac[start_aclist_index]); - - actual_aclist_num_entries = aclist_info_len / MAC_LEN; - printf("-Print AP Deny list, num stations = %d\n", actual_aclist_num_entries); - for (i=0; i - - - SL_WLAN_P2P_OPT_CHANNEL_N_REGS: - \code - _u16 listen_channel,listen_reg,oper_channel,oper_reg; - _u16 len = 4; - _u16 config_opt = SL_WLAN_P2P_OPT_CHANNEL_N_REGS; - _u8 channel_n_regs[4]; - sl_WlanGet(SL_WLAN_CFG_P2P_PARAM_ID, &config_opt, &len, (_u8* )channel_n_regs); - listen_channel = channel_n_regs[0]; - listen_reg = channel_n_regs[1]; - oper_channel = channel_n_regs[2]; - oper_reg = channel_n_regs[3]; - \endcode -
- - - SL_WLAN_RX_FILTER_STATE: - \code - int ret = 0; - SlWlanRxFilterIdMask_t FilterIdMask; - _u16 len = sizeof(SlWlanRxFilterIdMask_t);; - _u16 config_opt = SL_WLAN_RX_FILTER_STATE; - memset(FilterIdMask,0,sizeof(FilterIdMask)); - ret = sl_WlanGet(SL_WLAN_RX_FILTERS_ID, &config_opt , &len, (_u8* )FilterIdMask); - \endcode -
- - - SL_WLAN_RX_FILTER_SYS_STATE: - \code - int ret = 0; - SlWlanRxFilterSysFiltersMask_t FilterSysIdMask; - _u16 len = sizeof(SlWlanRxFilterSysFiltersMask_t);; - _u16 config_opt = SL_WLAN_RX_FILTER_SYS_STATE; - memset(FilterSysIdMask,0,sizeof(FilterSysIdMask)); - ret = sl_WlanGet(SL_WLAN_RX_FILTERS_ID, &config_opt , &len, (_u8* )FilterSysIdMask); - \endcode -
- - - SL_WLAN_CONNECTION_INFO: - \code - _i16 RetVal = 0 ; - _u16 Len = sizeof(SlWlanConnStatusParam_t) ; - SlWlanConnStatusParam_t WlanConnectInfo ; - RetVal = sl_WlanGet(SL_WLAN_CONNECTION_INFO, NULL , &Len, (_u8*)&WlanConnectInfo); - \endcode -
- - - SL_WLAN_GENERAL_PARAM_ANT_SELECTION_GET: - \code - _i16 RetVal = 0 ; - _u16 config_opt = SL_WLAN_GENERAL_PARAM_ANT_SELECTION_GET; - _u16 len = sizeof(SetAntennaIndex_t); - SetAntennaIndex_t SetAntennaParams; - RetVal = sl_WlanGet(SL_WLAN_CFG_GENERAL_PARAM_ID,&config_opt,&len, (_u8* )&SetAntennaParams); - \endcode -
- -*/ - -#if _SL_INCLUDE_FUNC(sl_WlanGet) -_i16 sl_WlanGet(const _u16 ConfigId, _u16 *pConfigOpt,_u16 *pConfigLen, _u8 *pValues); -#endif - -/*! - \brief Adds new filter rule to the system - - \param[in] RuleType The rule type - - SL_WLAN_RX_FILTER_HEADER - - SL_WLAN_RX_FILTER_COMBINATION - - \param[in] Flags Flags which set the type of header rule Args and sets the persistent flag - - SL_WLAN_RX_FILTER_BINARY - - SL_WLAN_RX_FILTER_PERSISTENT - - SL_WLAN_RX_FILTER_ENABLE - - \param[in] pRule Determine the filter rule logic - \param[in] pTrigger Determine when the rule is triggered also sets rule parent. - \param[in] pAction Sets the action to be executed in case the match functions pass - \param[out] pFilterId The filterId which was created - - \par Persistent Save the filters for persistent can be done by calling with SL_WLAN_RX_FILTER_STORE - - \return Zero on success, or negative error code on failure - \sa - \note - \warning - */ -#if _SL_INCLUDE_FUNC(sl_WlanRxFilterAdd) -_i16 sl_WlanRxFilterAdd( SlWlanRxFilterRuleType_t RuleType, - SlWlanRxFilterFlags_u Flags, - const SlWlanRxFilterRule_u* const pRule, - const SlWlanRxFilterTrigger_t* const pTrigger, - const SlWlanRxFilterAction_t* const pAction, - SlWlanRxFilterID_t* pFilterId); - -#endif - -/*! - - Close the Doxygen group. - @} - - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __WLAN_H__ */ - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/wlanconfig.h b/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/wlanconfig.h deleted file mode 100644 index 06fc3751fe5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/net/wifi/wlanconfig.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * wlan.c - CC31xx/CC32xx Host Driver Implementation - * - * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ - * - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the - * distribution. - * - * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * -*/ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ -#include - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ -typedef struct -{ - _u8 const Mode; - _u8 const ConnectionPolicy; - _u8 const PMPolicy; - _u16 const MaxSleepTimeMS; - _u8 const ScanPolicy; - _u32 const ScanIntervalInSeconds ; - _u8 const Ipv4Mode; - _u8 const Ipv4Config; - _u32 const Ipv4; - _u32 const IpMask; - _u32 const IpGateway; - _u32 const IpDnsServer; - _u8 const DHCPServer; - _u32 const StartAddress; - _u32 const LastAddress; - _u32 const LeaseTime; - _u8 const ProvisioningStop; - _u8 const DeleteAllProfile; -}SlWifiCC32XXConfig_t; diff --git a/ext/hal/ti/simplelink/source/ti/drivers/nvs/NVSRAM.c b/ext/hal/ti/simplelink/source/ti/drivers/nvs/NVSRAM.c deleted file mode 100644 index 008358f8bd6..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/nvs/NVSRAM.c +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * ======== NVSRAM.c ======== - */ - -#include -#include -#include - -#include -#include - -#include -#include - -static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size); -static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size); - -extern NVS_Config NVS_config[]; -extern const uint8_t NVS_count; - -/* NVS function table for NVSRAM implementation */ -const NVS_FxnTable NVSRAM_fxnTable = { - NVSRAM_close, - NVSRAM_control, - NVSRAM_erase, - NVSRAM_getAttrs, - NVSRAM_init, - NVSRAM_lock, - NVSRAM_open, - NVSRAM_read, - NVSRAM_unlock, - NVSRAM_write -}; - -/* - * Semaphore to synchronize access to the region. - */ -static SemaphoreP_Handle writeSem; - -/* - * ======== NVSRAM_close ======== - */ -void NVSRAM_close(NVS_Handle handle) -{ - ((NVSRAM_Object *) handle->object)->isOpen = false; -} - -/* - * ======== NVSRAM_control ======== - */ -int_fast16_t NVSRAM_control(NVS_Handle handle, uint_fast16_t cmd, - uintptr_t arg) -{ - return (NVS_STATUS_UNDEFINEDCMD); -} - -/* - * ======== NVSRAM_erase ======== - */ -int_fast16_t NVSRAM_erase(NVS_Handle handle, size_t offset, size_t size) -{ - int_fast16_t status; - - SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); - - status = doErase(handle, offset, size); - - SemaphoreP_post(writeSem); - - return (status); -} - -/* - * ======== NVSRAM_getAttrs ======== - */ -void NVSRAM_getAttrs(NVS_Handle handle, NVS_Attrs *attrs) -{ - NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; - - attrs->regionBase = hwAttrs->regionBase; - attrs->regionSize = hwAttrs->regionSize; - attrs->sectorSize = hwAttrs->sectorSize; -} - -/* - * ======== NVSRAM_init ======== - */ -void NVSRAM_init() -{ - uintptr_t key; - SemaphoreP_Handle sem; - - /* speculatively create a binary semaphore for thread safety */ - sem = SemaphoreP_createBinary(1); - /* sem == NULL will be detected in 'open' */ - - key = HwiP_disable(); - - if (writeSem == NULL) { - /* use the binary sem created above */ - writeSem = sem; - HwiP_restore(key); - } - else { - /* init already called */ - HwiP_restore(key); - - /* delete unused Semaphore */ - if (sem) { - SemaphoreP_delete(sem); - } - } -} - -/* - * ======== NVSRAM_lock ======= - */ -int_fast16_t NVSRAM_lock(NVS_Handle handle, uint32_t timeout) -{ - if (SemaphoreP_pend(writeSem, timeout) != SemaphoreP_OK) { - return (NVS_STATUS_TIMEOUT); - } - return (NVS_STATUS_SUCCESS); -} - -/* - * ======== NVSRAM_open ======= - */ -NVS_Handle NVSRAM_open(uint_least8_t index, NVS_Params *params) -{ - NVS_Handle handle; - NVSRAM_Object *object; - NVSRAM_HWAttrs const *hwAttrs; - - /* Confirm that 'init' has successfully completed */ - if (writeSem == NULL) { - NVSRAM_init(); - if (writeSem == NULL) { - return (NULL); - } - } - - /* verify NVS region index */ - if (index >= NVS_count) { - return (NULL); - } - - handle = &NVS_config[index]; - object = NVS_config[index].object; - hwAttrs = NVS_config[index].hwAttrs; - - /* for efficient argument checking */ - object->sectorBaseMask = ~(hwAttrs->sectorSize - 1); - - SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); - - if (object->isOpen) { - SemaphoreP_post(writeSem); - - return (NULL); - } - - /* The regionBase must be aligned on a page boundary */ - if ((size_t) (hwAttrs->regionBase) & (hwAttrs->sectorSize - 1)) { - SemaphoreP_post(writeSem); - - return (NULL); - } - - /* The region cannot be smaller than a sector size */ - if (hwAttrs->regionSize < hwAttrs->sectorSize) { - SemaphoreP_post(writeSem); - - return (NULL); - } - - /* The region size must be a multiple of sector size */ - if (hwAttrs->regionSize != - (hwAttrs->regionSize & object->sectorBaseMask)) { - SemaphoreP_post(writeSem); - return (NULL); - } - - object->isOpen = true; - - SemaphoreP_post(writeSem); - - return (handle); -} - -/* - * ======== NVSRAM_read ======= - */ -int_fast16_t NVSRAM_read(NVS_Handle handle, size_t offset, void *buffer, - size_t bufferSize) -{ - NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; - - /* Validate offset and bufferSize */ - if (offset + bufferSize > hwAttrs->regionSize) { - return (NVS_STATUS_INV_OFFSET); - } - - /* - * Get exclusive access to the region. We don't want someone - * else to erase the region while we are reading it. - */ - SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); - - memcpy(buffer, (char *)(hwAttrs->regionBase) + offset, bufferSize); - - SemaphoreP_post(writeSem); - - return (NVS_STATUS_SUCCESS); -} - -/* - * ======== NVSRAM_unlock ======= - */ -void NVSRAM_unlock(NVS_Handle handle) -{ - SemaphoreP_post(writeSem); -} - -/* - * ======== NVSRAM_write ======= - */ -int_fast16_t NVSRAM_write(NVS_Handle handle, size_t offset, void *buffer, - size_t bufferSize, uint_fast16_t flags) -{ - size_t i; - uint8_t *dstBuf; - uint8_t *srcBuf; - int_fast16_t result; - size_t size; - NVSRAM_Object *object = handle->object; - NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; - - /* Validate offset and bufferSize */ - if (offset + bufferSize > hwAttrs->regionSize) { - return (NVS_STATUS_INV_OFFSET); - } - - /* Get exclusive access to the Flash region */ - SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); - - /* If erase is set, erase destination sector(s) first */ - if (flags & NVS_WRITE_ERASE) { - size = bufferSize & object->sectorBaseMask; - if (bufferSize & (~object->sectorBaseMask)) { - size += hwAttrs->sectorSize; - } - - result = doErase(handle, offset & object->sectorBaseMask, size); - if (result != NVS_STATUS_SUCCESS) { - SemaphoreP_post(writeSem); - - return (result); - } - } - else if (flags & NVS_WRITE_PRE_VERIFY) { - /* - * If pre-verify, each destination byte must be able to be changed to the - * source byte (1s to 0s, not 0s to 1s). - * this is satisfied by the following test: - * src == (src & dst) - */ - dstBuf = (uint8_t *)((uint32_t)(hwAttrs->regionBase) + offset); - srcBuf = buffer; - for (i = 0; i < bufferSize; i++) { - if (srcBuf[i] != (srcBuf[i] & dstBuf[i])) { - SemaphoreP_post(writeSem); - return (NVS_STATUS_INV_WRITE); - } - } - } - - dstBuf = (uint8_t *)((uint32_t)(hwAttrs->regionBase) + offset); - srcBuf = buffer; - memcpy((void *) dstBuf, (void *) srcBuf, bufferSize); - - SemaphoreP_post(writeSem); - - return (NVS_STATUS_SUCCESS); -} - -/* - * ======== checkEraseRange ======== - */ -static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size) -{ - NVSRAM_Object *object = handle->object; - NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; - - if (offset != (offset & object->sectorBaseMask)) { - /* poorly aligned start address */ - return (NVS_STATUS_INV_ALIGNMENT); - } - - if (offset >= hwAttrs->regionSize) { - /* offset is past end of region */ - return (NVS_STATUS_INV_OFFSET); - } - - if (offset + size > hwAttrs->regionSize) { - /* size is too big */ - return (NVS_STATUS_INV_SIZE); - } - - if (size != (size & object->sectorBaseMask)) { - /* size is not a multiple of sector size */ - return (NVS_STATUS_INV_SIZE); - } - - return (NVS_STATUS_SUCCESS); -} - -/* - * ======== doErase ======== - */ -static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size) -{ - void * sectorBase; - int_fast16_t rangeStatus; - NVSRAM_HWAttrs const *hwAttrs = handle->hwAttrs; - - /* sanity test the erase args */ - rangeStatus = checkEraseRange(handle, offset, size); - if (rangeStatus != NVS_STATUS_SUCCESS) { - return (rangeStatus); - } - - sectorBase = (void *) ((uint32_t) hwAttrs->regionBase + offset); - - memset(sectorBase, 0xFF, size); - - return (NVS_STATUS_SUCCESS); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/nvs/NVSRAM.h b/ext/hal/ti/simplelink/source/ti/drivers/nvs/NVSRAM.h deleted file mode 100644 index f42e92d6ab8..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/nvs/NVSRAM.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file NVSRAM.h - * - * @brief RAM implementation of the NVS driver - * - * This NVS driver implementation makes use of RAM instead of FLASH memory. - * It can be used for developing code which relies the NVS driver without - * wearing down FLASH memory. - * - * The NVS header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_drivers_nvs_NVSRAM__include -#define ti_drivers_nvs_NVSRAM__include - -#include -#include - -#if defined (__cplusplus) -extern "C" { -#endif - -/*! - * @internal @brief NVS function pointer table - * - * 'NVSRAM_fxnTable' is a fully populated function pointer table - * that can be referenced in the NVS_config[] array entries. - * - * Users can minimize their application code size by providing their - * own custom NVS function pointer table that contains only those APIs - * used by the application. - * - * An example of a custom NVS function table is shown below: - * @code - * // - * // Since the application does not use the - * // NVS_control(), NVS_lock(), and NVS_unlock() APIs, - * // these APIs are removed from the function - * // pointer table and replaced with NULL - * // - * const NVS_FxnTable myNVS_fxnTable = { - * NVSRAM_close, - * NULL, // remove NVSRAM_control(), - * NVSRAM_erase, - * NVSRAM_getAttrs, - * NVSRAM_init, - * NULL, // remove NVSRAM_lock(), - * NVSRAM_open, - * NVSRAM_read, - * NULL, // remove NVSRAM_unlock(), - * NVSRAM_write - * }; - * @endcode - */ -extern const NVS_FxnTable NVSRAM_fxnTable; - -/*! - * @brief NVSRAM Hardware Attributes - * - * The 'sectorSize' is the minimal amount of data to that is cleared on an - * erase operation. Devices which feature internal FLASH memory usually - * have a 4096 byte sector size (refer to device specific documentation). It - * is recommended that the 'sectorSize' used match the FLASH memory sector - * size. - * - * The 'regionBase' field must point to the base address of the region - * to be managed. It is also required that the region be aligned on a - * sectorSize boundary (example below to demonstrate how to do this). - * - * The 'regionSize' must be an integer multiple of the 'sectorSize'. - * - * Defining and reserving RAM memory regions can be done entirely within the - * Board.c file. - * - * The example below defines a char array, 'ramBuf' and uses compiler - * pragmas to place 'ramBuf' at an aligned address within RAM. - * - * @code - * #define SECTORSIZE (4096) - * - * static char ramBuf[SECTORSIZE * 4] __attribute__ ((aligned (4096))); - * - * NVSRAM_HWAttrs NVSRAMHWAttrs[1] = { - * { - * .regionBase = (void *) ramBuf, - * .regionSize = SECTORSIZE * 4, - * .sectorSize = SECTORSIZE - * } - * }; - * - * - * @endcode - */ -typedef struct NVSRAM_HWAttrs { - void *regionBase; /*!< Base address of RAM region */ - size_t regionSize; /*!< The size of the region in bytes */ - size_t sectorSize; /*!< Sector size in bytes */ -} NVSRAM_HWAttrs; - -/* - * @brief NVSRAM Object - * - * The application must not access any member variables of this structure! - */ -typedef struct NVSRAM_Object { - size_t sectorBaseMask; - bool isOpen; -} NVSRAM_Object; - -/* - * @cond NODOC - * NVSRAM driver public APIs - */ - -extern void NVSRAM_close(NVS_Handle handle); -extern int_fast16_t NVSRAM_control(NVS_Handle handle, uint_fast16_t cmd, - uintptr_t arg); -extern int_fast16_t NVSRAM_erase(NVS_Handle handle, size_t offset, - size_t size); -extern void NVSRAM_getAttrs(NVS_Handle handle, NVS_Attrs *attrs); -extern void NVSRAM_init(); -extern int_fast16_t NVSRAM_lock(NVS_Handle handle, uint32_t timeout); -extern NVS_Handle NVSRAM_open(uint_least8_t index, NVS_Params *params); -extern int_fast16_t NVSRAM_read(NVS_Handle handle, size_t offset, - void *buffer, size_t bufferSize); -extern void NVSRAM_unlock(NVS_Handle handle); -extern int_fast16_t NVSRAM_write(NVS_Handle handle, size_t offset, - void *buffer, size_t bufferSize, uint_fast16_t flags); - -/*! @endcond */ - -#if defined (__cplusplus) -} -#endif /* defined (__cplusplus) */ - -/*@}*/ -#endif /* ti_drivers_nvs_NVSRAM__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/nvs/NVSSPI25X.c b/ext/hal/ti/simplelink/source/ti/drivers/nvs/NVSSPI25X.c deleted file mode 100644 index 1a243c2806f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/nvs/NVSSPI25X.c +++ /dev/null @@ -1,995 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * ======== NVSSPI25X.c ======== - */ - -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include - -/* Instruction codes */ -#define SPIFLASH_WRITE 0x02 /**< Page Program */ -#define SPIFLASH_READ 0x03 /**< Read Data */ -#define SPIFLASH_READ_STATUS 0x05 /**< Read Status Register */ -#define SPIFLASH_WRITE_ENABLE 0x06 /**< Write Enable */ -#define SPIFLASH_SUBSECTOR_ERASE 0x20 /**< SubSector (4K Byte) Erase */ -#define SPIFLASH_SECTOR_ERASE 0xD8 /**< Sector (64K Byte) Erase */ -#define SPIFLASH_MASS_ERASE 0xC7 /**< Erase entire flash */ - -#define SPIFLASH_RDP 0xAB /**< Release from Deep Power Down */ -#define SPIFLASH_DP 0xB9 /**< Deep Power Down */ - -/* Bitmasks of the status register */ -#define SPIFLASH_STATUS_BIT_BUSY 0x01 /**< Busy bit of status register */ - -/* Write page size assumed by this driver */ -#define SPIFLASH_PROGRAM_PAGE_SIZE 256 - -/* Highest supported SPI instance index */ -#define MAX_SPI_INDEX 3 - -/* Size of hardware sector erased by SPIFLASH_SECTOR_ERASE */ -#define SPIFLASH_SECTOR_SIZE 0x10000 - -static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size); -static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size); -static int_fast16_t doRead(NVS_Handle handle, size_t offset, void *buffer, - size_t bufferSize); -static int_fast16_t doWriteVerify(NVS_Handle handle, size_t offset, - void *src, size_t srcBufSize, void *dst, - size_t dstBufSize, bool preFlag); - -static int_fast16_t extFlashSpiWrite(const uint8_t *buf, size_t len); -static int_fast16_t extFlashSpiRead(uint8_t *buf, size_t len); -static int_fast16_t extFlashPowerDown(NVS_Handle nvsHandle); -static int_fast16_t extFlashPowerStandby(NVS_Handle nvsHandle); -static int_fast16_t extFlashWaitReady(NVS_Handle nvsHandle); -static int_fast16_t extFlashWriteEnable(NVS_Handle nvsHandle); -static int_fast16_t extFlashMassErase(NVS_Handle nvsHandle); - -extern NVS_Config NVS_config[]; -extern const uint8_t NVS_count; - -/* NVS function table for NVSSPI25X implementation */ -const NVS_FxnTable NVSSPI25X_fxnTable = { - NVSSPI25X_close, - NVSSPI25X_control, - NVSSPI25X_erase, - NVSSPI25X_getAttrs, - NVSSPI25X_init, - NVSSPI25X_lock, - NVSSPI25X_open, - NVSSPI25X_read, - NVSSPI25X_unlock, - NVSSPI25X_write -}; - -/* Manage SPI indexes */ -static SPI_Handle spiHandles[MAX_SPI_INDEX + 1]; -static uint8_t spiHandleUsers[MAX_SPI_INDEX + 1]; - -/* - * Currently active (protected within Semaphore_pend() block) - * SPI handle, and CSN pin - */ -static SPI_Handle spiHandle; -static uint32_t spiCsnGpioIndex; - -/* - * Semaphore to synchronize access to flash region. - */ -static SemaphoreP_Handle writeSem; - -/* - * ======== NVSSPI25X_close ======== - */ -void NVSSPI25X_close(NVS_Handle handle) -{ - NVSSPI25X_HWAttrs const *hwAttrs; - NVSSPI25X_Object *object; - - SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); - - hwAttrs = handle->hwAttrs; - object = handle->object; - - spiHandle = object->spiHandle; - spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; - - /* Close the SPI if we opened it */ - if (hwAttrs->spiHandle == NULL) { - spiHandleUsers[hwAttrs->spiIndex] -= 1; - - /* Close SPI if this is the last region that uses it */ - if (spiHandleUsers[hwAttrs->spiIndex] == 0) { - /* Ensure part is responsive */ - extFlashWaitReady(handle); - - /* Put the part in low power mode */ - extFlashPowerDown(handle); - - SPI_close(object->spiHandle); - spiHandles[hwAttrs->spiIndex] = NULL; - } - } - - NVSSPI25X_deinitSpiCs(handle, spiCsnGpioIndex); - - object->opened = false; - - SemaphoreP_post(writeSem); -} - -/* - * ======== NVSSPI25X_control ======== - */ -int_fast16_t NVSSPI25X_control(NVS_Handle handle, uint_fast16_t cmd, uintptr_t arg) -{ - NVSSPI25X_HWAttrs const *hwAttrs; - NVSSPI25X_Object *object; - - if (cmd != NVSSPI25X_CMD_MASS_ERASE) return (NVS_STATUS_UNDEFINEDCMD); - - hwAttrs = handle->hwAttrs; - object = handle->object; - - /* Set protected global variables */ - spiHandle = object->spiHandle; - spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; - - return (extFlashMassErase(handle)); -} - -/* - * ======== NVSSPI25X_erase ======== - */ -int_fast16_t NVSSPI25X_erase(NVS_Handle handle, size_t offset, size_t size) -{ - int_fast16_t status; - - SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); - - status = doErase(handle, offset, size); - - SemaphoreP_post(writeSem); - - return (status); -} - -/* - * ======== NVSSPI25X_getAttrs ======== - */ -void NVSSPI25X_getAttrs(NVS_Handle handle, NVS_Attrs *attrs) -{ - NVSSPI25X_HWAttrs const *hwAttrs; - - hwAttrs = handle->hwAttrs; - - /* FlashSectorSizeGet() returns the size of a flash sector in bytes. */ - attrs->regionBase = NVS_REGION_NOT_ADDRESSABLE; - attrs->regionSize = hwAttrs->regionSize; - attrs->sectorSize = hwAttrs->sectorSize; -} - -/* - * ======== NVSSPI25X_init ======== - */ -void NVSSPI25X_init() -{ - unsigned int key; - SemaphoreP_Handle tempSem; - - SPI_init(); - - /* Speculatively create semaphore so critical section is faster */ - tempSem = SemaphoreP_createBinary(1); - /* tempSem == NULL will be detected in 'open' */ - - key = HwiP_disable(); - - if (writeSem == NULL) { - /* First time init, assign handle */ - writeSem = tempSem; - - HwiP_restore(key); - } - else { - /* Init already called */ - HwiP_restore(key); - - /* Delete unused Semaphores */ - if (tempSem) { - SemaphoreP_delete(tempSem); - } - } -} - -/* - * ======== NVSSPI25X_lock ======= - */ -int_fast16_t NVSSPI25X_lock(NVS_Handle handle, uint32_t timeout) -{ - if (SemaphoreP_pend(writeSem, timeout) != SemaphoreP_OK) { - return (NVS_STATUS_TIMEOUT); - } - return (NVS_STATUS_SUCCESS); -} - -/* - * ======== NVSSPI25X_open ======= - */ -NVS_Handle NVSSPI25X_open(uint_least8_t index, NVS_Params *params) -{ - NVSSPI25X_Object *object; - NVSSPI25X_HWAttrs const *hwAttrs; - size_t sectorSize; - NVS_Handle handle; - SPI_Params spiParams; - - /* Confirm that 'init' has successfully completed */ - if (writeSem == NULL) { - NVSSPI25X_init(); - if (writeSem == NULL) { - return (NULL); - } - } - - /* Verify NVS region index */ - if (index >= NVS_count) { - return (NULL); - } - - SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); - - handle = &NVS_config[index]; - object = NVS_config[index].object; - hwAttrs = NVS_config[index].hwAttrs; - - if (object->opened == true) { - SemaphoreP_post(writeSem); - return (NULL); - } - - sectorSize = hwAttrs->sectorSize; - object->sectorBaseMask = ~(sectorSize - 1); - - /* The regionBase must be aligned on a flash page boundary */ - if ((hwAttrs->regionBaseOffset) & (sectorSize - 1)) { - SemaphoreP_post(writeSem); - return (NULL); - } - - /* The region cannot be smaller than a sector size */ - if (hwAttrs->regionSize < sectorSize) { - SemaphoreP_post(writeSem); - return (NULL); - } - - /* The region size must be a multiple of sector size */ - if (hwAttrs->regionSize != (hwAttrs->regionSize & object->sectorBaseMask)) { - SemaphoreP_post(writeSem); - return (NULL); - } - - if (hwAttrs->spiHandle) { - /* Use the provided SPI Handle */ - object->spiHandle = *hwAttrs->spiHandle; - } - else { - if (hwAttrs->spiIndex > MAX_SPI_INDEX) { - SemaphoreP_post(writeSem); - return (NULL); - } - /* Open SPI if this driver hasn't already opened this SPI instance */ - if (spiHandles[hwAttrs->spiIndex] == NULL) { - SPI_Handle spi; - - SPI_Params_init(&spiParams); - spiParams.bitRate = hwAttrs->spiBitRate; - spiParams.mode = SPI_MASTER; - spiParams.transferMode = SPI_MODE_BLOCKING; - - /* Attempt to open SPI. */ - spi = SPI_open(hwAttrs->spiIndex, &spiParams); - - if (spi == NULL) { - SemaphoreP_post(writeSem); - return (NULL); - } - - spiHandles[hwAttrs->spiIndex] = spi; - } - object->spiHandle = spiHandles[hwAttrs->spiIndex]; - /* Keep track of how many regions use the same SPI handle */ - spiHandleUsers[hwAttrs->spiIndex] += 1; - } - - /* Set protected global variables */ - spiHandle = object->spiHandle; - spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; - - - /* Initialize chip select output */ - NVSSPI25X_initSpiCs(handle, spiCsnGpioIndex); - - object->opened = true; - - /* Put the part in standby mode */ - extFlashPowerStandby(handle); - - SemaphoreP_post(writeSem); - - return (handle); -} - -/* - * ======== NVSSPI25X_read ======= - */ -int_fast16_t NVSSPI25X_read(NVS_Handle handle, size_t offset, void *buffer, - size_t bufferSize) -{ - NVSSPI25X_HWAttrs const *hwAttrs; - int retval = NVS_STATUS_SUCCESS; - - hwAttrs = handle->hwAttrs; - - /* Validate offset and bufferSize */ - if (offset + bufferSize > hwAttrs->regionSize) { - return (NVS_STATUS_INV_OFFSET); - } - - /* - * Get exclusive access to the region. We don't want someone - * else to erase the region while we are reading it. - */ - SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); - - retval = doRead(handle, offset, buffer, bufferSize); - - SemaphoreP_post(writeSem); - - return (retval); -} - -/* - * ======== NVSSPI25X_unlock ======= - */ -void NVSSPI25X_unlock(NVS_Handle handle) -{ - SemaphoreP_post(writeSem); -} - -/* - * ======== NVSSPI25X_write ======= - */ -int_fast16_t NVSSPI25X_write(NVS_Handle handle, size_t offset, void *buffer, - size_t bufferSize, uint_fast16_t flags) -{ - NVSSPI25X_Object *object; - NVSSPI25X_HWAttrs const *hwAttrs; - size_t length, foffset; - uint32_t status = true; - uint8_t *srcBuf; - int retval = NVS_STATUS_SUCCESS; - uint8_t wbuf[4]; - - hwAttrs = handle->hwAttrs; - object = handle->object; - - /* Validate offset and bufferSize */ - if (offset + bufferSize > hwAttrs->regionSize) { - return (NVS_STATUS_INV_OFFSET); - } - - /* Get exclusive access to the Flash region */ - SemaphoreP_pend(writeSem, SemaphoreP_WAIT_FOREVER); - - /* Set protected global variables */ - spiHandle = object->spiHandle; - spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; - - /* If erase is set, erase destination sector(s) first */ - if (flags & NVS_WRITE_ERASE) { - length = bufferSize & object->sectorBaseMask; - if (bufferSize & (~object->sectorBaseMask)) { - length += hwAttrs->sectorSize; - } - - retval = doErase(handle, offset & object->sectorBaseMask, length); - if (retval != NVS_STATUS_SUCCESS) { - SemaphoreP_post(writeSem); - return (retval); - } - } - else if (flags & NVS_WRITE_PRE_VERIFY) { - if ((hwAttrs->verifyBuf == NULL) || (hwAttrs->verifyBufSize == 0)) { - SemaphoreP_post(writeSem); - return (NVS_STATUS_ERROR); - } - - retval = doWriteVerify(handle, offset, buffer, bufferSize, - hwAttrs->verifyBuf, hwAttrs->verifyBufSize, true); - - if (retval != NVS_STATUS_SUCCESS) { - SemaphoreP_post(writeSem); - return (retval); - } - } - - srcBuf = buffer; - length = bufferSize; - foffset = (size_t)hwAttrs->regionBaseOffset + offset; - - while (length > 0) - { - size_t ilen; /* Interim length per instruction */ - - /* Wait till previous erase/program operation completes */ - int ret = extFlashWaitReady(handle); - - if (ret) { - status = false; - break; - } - - ret = extFlashWriteEnable(handle); - - if (ret) { - status = false; - break; - } - - ilen = SPIFLASH_PROGRAM_PAGE_SIZE - (foffset % SPIFLASH_PROGRAM_PAGE_SIZE); - if (length < ilen) { - ilen = length; - } - - wbuf[0] = SPIFLASH_WRITE; - wbuf[1] = (foffset >> 16) & 0xff; - wbuf[2] = (foffset >> 8) & 0xff; - wbuf[3] = foffset & 0xff; - - foffset += ilen; - length -= ilen; - - /* - * Up to 100ns CS hold time (which is not clear - * whether it's application only in between reads) - * is not imposed here since above instructions - * should be enough to delay - * as much. - */ - NVSSPI25X_assertSpiCs(handle, spiCsnGpioIndex); - - if (extFlashSpiWrite(wbuf, sizeof(wbuf)) != NVS_STATUS_SUCCESS) { - status = false; - break; - } - - if (extFlashSpiWrite(srcBuf, ilen) != NVS_STATUS_SUCCESS) { - status = false; - break; - } - - srcBuf += ilen; - NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); - } - - if (status == false) { - retval = NVS_STATUS_ERROR; - } - else if (flags & NVS_WRITE_POST_VERIFY) { - if ((hwAttrs->verifyBuf == NULL) || (hwAttrs->verifyBufSize == 0)) { - SemaphoreP_post(writeSem); - return (NVS_STATUS_ERROR); - } - - retval = doWriteVerify(handle, offset, buffer, bufferSize, - hwAttrs->verifyBuf, hwAttrs->verifyBufSize, false); - } - - SemaphoreP_post(writeSem); - - return (retval); -} - -/* - * ======== doWriteVerify ======= - */ -static int_fast16_t doWriteVerify(NVS_Handle handle, size_t offset, void *src, - size_t srcBufSize, void *dst, size_t dstBufSize, bool preFlag) -{ - size_t i, j; - uint8_t *srcBuf, *dstBuf; - bool bad; - int_fast16_t retval; - - srcBuf = src; - dstBuf = dst; - - j = dstBufSize; - - for (i = 0; i < srcBufSize; i++, j++) { - if (j == dstBufSize) { - retval = doRead(handle, offset + i, dstBuf, j); - if (retval != NVS_STATUS_SUCCESS) { - break; - } - j = 0; - } - if (preFlag) { - bad = srcBuf[i] != (srcBuf[i] & dstBuf[j]); - } - else { - bad = srcBuf[i] != dstBuf[j]; - } - if (bad) return (NVS_STATUS_INV_WRITE); - } - return (NVS_STATUS_SUCCESS); -} - -/* - * ======== checkEraseRange ======== - */ -static int_fast16_t checkEraseRange(NVS_Handle handle, size_t offset, size_t size) -{ - NVSSPI25X_Object *object; - NVSSPI25X_HWAttrs const *hwAttrs; - - object = handle->object; - hwAttrs = handle->hwAttrs; - - if (offset != (offset & object->sectorBaseMask)) { - return (NVS_STATUS_INV_ALIGNMENT); /* Poorly aligned start address */ - } - - if (offset >= hwAttrs->regionSize) { - return (NVS_STATUS_INV_OFFSET); /* Offset is past end of region */ - } - - if (offset + size > hwAttrs->regionSize) { - return (NVS_STATUS_INV_SIZE); /* Size is too big */ - } - - if (size != (size & object->sectorBaseMask)) { - return (NVS_STATUS_INV_SIZE); /* Size is not a multiple of sector size */ - } - - return (NVS_STATUS_SUCCESS); -} - -/* - * ======== doErase ======== - */ -static int_fast16_t doErase(NVS_Handle handle, size_t offset, size_t size) -{ - NVSSPI25X_HWAttrs const *hwAttrs; - NVSSPI25X_Object *object; - uint32_t sectorBase; - size_t eraseSize; - int_fast16_t rangeStatus; - uint8_t wbuf[4]; - - /* Sanity test the erase args */ - rangeStatus = checkEraseRange(handle, offset, size); - - if (rangeStatus != NVS_STATUS_SUCCESS) { - return (rangeStatus); - } - - hwAttrs = handle->hwAttrs; - object = handle->object; - - /* Set protected global variables */ - spiHandle = object->spiHandle; - spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; - - /* Start erase at this address */ - sectorBase = (uint32_t)hwAttrs->regionBaseOffset + offset; - - while (size) { - /* Wait till previous erase/program operation completes */ - int ret = extFlashWaitReady(handle); - if (ret) { - return (NVS_STATUS_ERROR); - } - - ret = extFlashWriteEnable(handle); - if (ret) { - return (NVS_STATUS_ERROR); - } - - - /* Determine which erase command to use */ - if (size >= SPIFLASH_SECTOR_SIZE && - ((sectorBase & (SPIFLASH_SECTOR_SIZE - 1)) == 0)){ - /* Erase size is one sector (64kB) */ - eraseSize = SPIFLASH_SECTOR_SIZE; - wbuf[0] = SPIFLASH_SECTOR_ERASE; - } - else{ - /* Erase size is one sub-sector (4kB)*/ - eraseSize = hwAttrs->sectorSize; - wbuf[0] = SPIFLASH_SUBSECTOR_ERASE; - } - - - /* Format command to send over SPI */ - wbuf[1] = (sectorBase >> 16) & 0xff; - wbuf[2] = (sectorBase >> 8) & 0xff; - wbuf[3] = sectorBase & 0xff; - - /* Send erase command to external flash */ - NVSSPI25X_assertSpiCs(handle, spiCsnGpioIndex); - if (extFlashSpiWrite(wbuf, sizeof(wbuf))) { - NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); - return (NVS_STATUS_ERROR); - } - NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); - - sectorBase += eraseSize; - size -= eraseSize; - } - - return (NVS_STATUS_SUCCESS); -} - -/* - * ======== doRead ======= - */ -static int_fast16_t doRead(NVS_Handle handle, size_t offset, void *buffer, - size_t bufferSize) -{ - NVSSPI25X_Object *object; - NVSSPI25X_HWAttrs const *hwAttrs; - size_t loffset; - uint8_t wbuf[4]; - int retval = NVS_STATUS_SUCCESS; - - hwAttrs = handle->hwAttrs; - object = handle->object; - - /* Set protected global variables */ - spiHandle = object->spiHandle; - spiCsnGpioIndex = hwAttrs->spiCsnGpioIndex; - - loffset = offset + hwAttrs->regionBaseOffset; - - /* Wait till previous erase/program operation completes */ - retval = extFlashWaitReady(handle); - if (retval) { - return (retval); - } - - /* - * SPI is driven with very low frequency (1MHz < 33MHz fR spec) - * in this temporary implementation. - * and hence it is not necessary to use fast read. - */ - wbuf[0] = SPIFLASH_READ; - wbuf[1] = (loffset >> 16) & 0xff; - wbuf[2] = (loffset >> 8) & 0xff; - wbuf[3] = loffset & 0xff; - - NVSSPI25X_assertSpiCs(handle, spiCsnGpioIndex); - - if (extFlashSpiWrite(wbuf, sizeof(wbuf))) { - NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); - return (NVS_STATUS_ERROR); - } - - retval = extFlashSpiRead(buffer, bufferSize); - - NVSSPI25X_deassertSpiCs(handle, spiCsnGpioIndex); - - return (retval); -} - -/* - * ======== extFlashPowerDown ======= - * Issue power down command - */ -static int_fast16_t extFlashPowerDown(NVS_Handle nvsHandle) -{ - uint8_t cmd; - int_fast16_t status; - - cmd = SPIFLASH_DP; - NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); - status = extFlashSpiWrite(&cmd,sizeof(cmd)); - NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); - - return (status); -} - -/* - * ======== extFlashPowerStandby ======= - * Issue standby command - */ -static int_fast16_t extFlashPowerStandby(NVS_Handle nvsHandle) -{ - uint8_t cmd; - int_fast16_t status; - - cmd = SPIFLASH_RDP; - NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); - status = extFlashSpiWrite(&cmd, sizeof(cmd)); - NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); - - if (status == NVS_STATUS_SUCCESS) { - status = extFlashWaitReady(nvsHandle); - } - - return (status); -} - -/* - * ======== extFlashMassErase ======= - * Issue mass erase command - */ -static int_fast16_t extFlashMassErase(NVS_Handle nvsHandle) -{ - uint8_t cmd; - int_fast16_t status; - - /* Wait for previous operation to complete */ - if (extFlashWaitReady(nvsHandle)) { - return (NVS_STATUS_ERROR); - } - - cmd = SPIFLASH_MASS_ERASE; - NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); - status = extFlashSpiWrite(&cmd,sizeof(cmd)); - NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); - - if (status != NVS_STATUS_SUCCESS) { - return (status); - } - - /* Wait for mass erase to complete */ - return (extFlashWaitReady(nvsHandle)); -} - -/* - * ======== extFlashWaitReady ======= - * Wait for any previous job to complete. - */ -static int_fast16_t extFlashWaitReady(NVS_Handle nvsHandle) -{ - const uint8_t wbuf[1] = { SPIFLASH_READ_STATUS }; - int_fast16_t ret; - uint8_t buf; - - NVSSPI25X_HWAttrs const *hwAttrs; - hwAttrs = nvsHandle->hwAttrs; - - for (;;) { - NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); - extFlashSpiWrite(wbuf, sizeof(wbuf)); - ret = extFlashSpiRead(&buf,sizeof(buf)); - NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); - - if (ret != NVS_STATUS_SUCCESS) { - /* Error */ - return (ret); - } - if (!(buf & SPIFLASH_STATUS_BIT_BUSY)) { - /* Now ready */ - break; - } - if (hwAttrs->statusPollDelayUs){ - /* Sleep to avoid excessive polling and starvation */ - ClockP_usleep(hwAttrs->statusPollDelayUs); - } - } - - return (NVS_STATUS_SUCCESS); -} - -/* - * ======== extFlashWriteEnable ======= - * Issue SPIFLASH_WRITE_ENABLE command - */ -static int_fast16_t extFlashWriteEnable(NVS_Handle nvsHandle) -{ - const uint8_t wbuf[] = { SPIFLASH_WRITE_ENABLE }; - int_fast16_t ret; - - NVSSPI25X_assertSpiCs(nvsHandle, spiCsnGpioIndex); - ret = extFlashSpiWrite(wbuf,sizeof(wbuf)); - NVSSPI25X_deassertSpiCs(nvsHandle, spiCsnGpioIndex); - - return (ret); -} - -/* - * ======== extFlashSpiWrite ======= - */ -static int_fast16_t extFlashSpiWrite(const uint8_t *buf, size_t len) -{ - SPI_Transaction masterTransaction; - - masterTransaction.rxBuf = NULL; - - /* - * Work around SPI transfer from address 0x0 - * transfer first byte from local buffer - */ - if (buf == NULL) { - uint8_t byte0; - byte0 = *buf++; - masterTransaction.count = 1; - masterTransaction.txBuf = (void*)&byte0; - if (!SPI_transfer(spiHandle, &masterTransaction)) { - return (NVS_STATUS_ERROR); - } - len = len - 1; - if (len == 0) { - return (NVS_STATUS_SUCCESS); - } - } - - masterTransaction.count = len; - masterTransaction.txBuf = (void*)buf; - - return (SPI_transfer(spiHandle, &masterTransaction) ? NVS_STATUS_SUCCESS : NVS_STATUS_ERROR); -} - - -/* - * ======== extFlashSpiRead ======= - */ -static int_fast16_t extFlashSpiRead(uint8_t *buf, size_t len) -{ - SPI_Transaction masterTransaction; - - masterTransaction.txBuf = NULL; - - /* - * Work around SPI transfer to address 0x0 - * transfer first byte into local buffer - */ - if (buf == NULL) { - uint8_t byte0; - masterTransaction.count = 1; - masterTransaction.rxBuf = (void*)&byte0; - if (!SPI_transfer(spiHandle, &masterTransaction)) { - return (NVS_STATUS_ERROR); - } - *buf++ = byte0; - len = len - 1; - if (len == 0) { - return (NVS_STATUS_SUCCESS); - } - } - - masterTransaction.count = len; - masterTransaction.rxBuf = buf; - - return (SPI_transfer(spiHandle, &masterTransaction) ? NVS_STATUS_SUCCESS : NVS_STATUS_ERROR); -} - -/* - * Below are the default (weak) GPIO-driver based implementations of: - * NVSSPI25X_initSpiCs() - * NVSSPI25X_deinitSpiCs() - * NVSSPI25X_assertSpiCs() - * NVSSPI25X_deassertSpiCs() - */ - -/* - * ======== NVSSPI25X_initSpiCs ======= - */ -#if defined(__IAR_SYSTEMS_ICC__) -__weak void NVSSPI25X_initSpiCs(NVS_Handle nvsHandle, uint16_t csId) -#elif defined(__GNUC__) && !defined(__ti__) -void __attribute__((weak)) NVSSPI25X_initSpiCs(NVS_Handle nvsHandle, uint16_t csId) -#else -#pragma WEAK (NVSSPI25X_initSpiCs) -void NVSSPI25X_initSpiCs(NVS_Handle nvsHandle, uint16_t csId) -#endif -{ - if (csId != NVSSPI25X_SPI_MANAGES_CS) { - GPIO_init(); - - /* - * Make SPI Chip Select GPIO an output, and set it high. - * Since the same device may be used for multiple regions, configuring - * the same Chip Select pin may be done multiple times. No harm done. - */ - GPIO_setConfig(csId, GPIO_CFG_OUT_STD | GPIO_CFG_OUT_HIGH); - } -} - -/* - * ======== NVSSPI25X_deinitSpiCs ======= - */ -#if defined(__IAR_SYSTEMS_ICC__) -__weak void NVSSPI25X_deinitSpiCs(NVS_Handle nvsHandle, uint16_t csId) -#elif defined(__GNUC__) && !defined(__ti__) -void __attribute__((weak)) NVSSPI25X_deinitSpiCs(NVS_Handle nvsHandle, uint16_t csId) -#else -#pragma WEAK (NVSSPI25X_deinitSpiCs) -void NVSSPI25X_deinitSpiCs(NVS_Handle nvsHandle, uint16_t csId) -#endif -{ -} - -/* - * ======== NVSSPI25X_assertSpiCs ======= - * Assert SPI flash /CS - */ -#if defined(__IAR_SYSTEMS_ICC__) -__weak void NVSSPI25X_assertSpiCs(NVS_Handle nvsHandle, uint16_t csId) -#elif defined(__GNUC__) && !defined(__ti__) -void __attribute__((weak)) NVSSPI25X_assertSpiCs(NVS_Handle nvsHandle, uint16_t csId) -#else -#pragma WEAK (NVSSPI25X_assertSpiCs) -void NVSSPI25X_assertSpiCs(NVS_Handle nvsHandle, uint16_t csId) -#endif -{ - if (csId != NVSSPI25X_SPI_MANAGES_CS) { - GPIO_write(csId, 0); - } -} - -/* - * ======== NVSSPI25X_deassertSpiCs ======= - * De-assert SPI flash /CS - */ -#if defined(__IAR_SYSTEMS_ICC__) -__weak void NVSSPI25X_deassertSpiCs(NVS_Handle nvsHandle, uint16_t csId) -#elif defined(__GNUC__) && !defined(__ti__) -void __attribute__((weak)) NVSSPI25X_deassertSpiCs(NVS_Handle nvsHandle, uint16_t csId) -#else -#pragma WEAK (NVSSPI25X_deassertSpiCs) -void NVSSPI25X_deassertSpiCs(NVS_Handle nvsHandle, uint16_t csId) -#endif -{ - if (csId != NVSSPI25X_SPI_MANAGES_CS) { - GPIO_write(csId, 1); - } -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/nvs/NVSSPI25X.h b/ext/hal/ti/simplelink/source/ti/drivers/nvs/NVSSPI25X.h deleted file mode 100644 index 99b4e8a2263..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/nvs/NVSSPI25X.h +++ /dev/null @@ -1,367 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*!***************************************************************************** - * @file NVSSPI25X.h - * @brief Non-Volatile Storage driver implementation - * for SPI flash peripherals - * - * # Overview # - * - * The NVSSPI25X module allows you to manage SPI flash memory. - * This driver works with most 256 byte/page SPI flash memory devices - * such as: - * - * Winbond W25xx family - * Macronics MX25Rxx family - * Micron N25Qxx family - * - * The SPI flash commands used by this driver are as follows: - * - * @code - * #define SPIFLASH_PAGE_WRITE 0x02 // Page Program (up to 256 bytes) - * #define SPIFLASH_READ 0x03 // Read Data - * #define SPIFLASH_READ_STATUS 0x05 // Read Status Register - * #define SPIFLASH_WRITE_ENABLE 0x06 // Write Enable - * #define SPIFLASH_SUBSECTOR_ERASE 0x20 // SubSector (4K bytes) Erase - * #define SPIFLASH_SECTOR_ERASE 0xD8 // Sector (usually 64K bytes) Erase - * #define SPIFLASH_RDP 0xAB // Release from Deep Power Down - * #define SPIFLASH_DP 0xB9 // Deep Power Down - * #define SPIFLASH_MASS_ERASE 0xC7 // Erase entire flash. - * @endcode - * - * It is assumed that the SPI flash device used by this driver supports - * the byte programmability of the SPIFLASH_PAGE_WRITE command and that - * write page size is 256 bytes. The erase sector and subsector sizes are - * assumed to be 64K and 4K respectively. - * - * The NVS_erase() command will issue a sector or subsector erase command - * based on the input size and offset. - * - * The driver must query the SPI flash to ensure that the part is ready before - * commands are issued. If the part responds as busy, the poll function sleeps - * for a number of microseconds determined by the - * #NVSSPI25X_HWAttrs.statusPollDelayUs field. A value of 0 means that the - * driver will continuously poll the external flash until it is ready, which - * may affect other threads ability to execute. - * - * ## SPI Interface Management ## - * - * For each managed flash region, a corresponding SPI instance must be - * provided to the NVSSPI25X driver. - * - * The SPI instance can be opened and closed - * internally by the NVSSPI25X driver, or alternatively, a SPI handle can be - * provided to the NVSSPI25X driver, indicating that the SPI instance is being - * opened and closed elsewhere within the application. This mode is useful - * when the SPI bus is share by more than just the SPI flash device. - * - * If the SPI instance is to be managed internally by the NVSSPI25X driver, a SPI - * instance index and bit rate must be configured in the region's HWAttrs. - * If the same SPI instance is referenced by multiple flash regions - * the driver will ensure that SPI_open() is invoked only once, and that - * SPI_close() will only be invoked when all flash regions using the SPI - * instance have been closed. - * - * If the SPI bus that the SPI flash device is on is shared with other - * devices accessed by an application, then the SPI handle used to manage - * a SPI flash region can be provided in the region's HWAttrs "spiHandle" - * field. Keep in mind that the "spiHandle" field is a POINTER to a - * SPI Handle, NOT a SPI Handle. This allows the user to simply initialize - * this field with the name of the global variable used for the SPI handle. - * In this mode, the user MUST open the SPI instance prior to opening the NVS - * region instance so that the referenced spiHandle is valid. - * - * By default, the "spiHandle" field is set to NULL, indicating that the user - * expects the NVS driver to open and close the SPI instance internally using - * the 'spiIndex' and 'spiBitRate' provided in the HWAttrs. - * - * ## @anchor SPI_CS_MGMT SPI Flash Chip Select Management ## - * - * ### Option 1: NVSSPI25X Driver Manages Chip Select ### - * By default, the NVSSPI25X driver will assert and de-assert a GPIO - * driver managed pin to select the SPI flash device before and after - * each SPI transfer to and from the device. - * - * To enable this behavior, a valid GPIO driver instance index must be - * provided in the NVS region's [spiCsnGpioIndex] - * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) field of the - * NVSSPI25X_HWAttrs structure. The corresponding GPIO pin will be - * configured at runtime by the NVSSPI25X driver as "GPIO_CFG_OUT_STD" - * and assertion of this pin is assumed to be active LOW. - * - * ### Option 2: SPI Driver Manages Chip Select ### - * Some SPI peripherals can be configured to manage their own chip - * select. Setting the [spiCsnGpioIndex] - * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) field of the NVSSPI25X_HWAttrs - * structure to #NVSSPI25X_SPI_MANAGES_CS informs the NVSSPI25X driver - * that the SPI peripheral used by the NVS driver has been configured - * that way. - * - * ### Option 3: User Manages Chip Select ### - * Alternatively, the user can manage the assertion and de-assertion of - * the SPI flash chip select entirely themselves by providing implementations - * of the following 4 APIs in their application code: - * - * @code - * void NVSSPI25X_initSpiCs(NVS_Handle nvsHandle, uint16_t csId); - * @endcode - * - This function is invoked within the NVS_open() API and is where the - * user should do whatever is required to initialize the hardware - * used for asserting and de-assering the SPI chip select signal. - * - The 'nvsHandle` argument is the NVS handle associated with the - * corresponding NVS region. - * - The 'csId' argument passed to this API is a copy of the [spiCsnGpioIndex] - * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) - * field of the corresponding NVS region's NVSSPI25X_HWAttrs structure. - * - * @code - * void NVSSPI25X_deinitSpiCs(NVS_Handle nvsHandle, uint16_t csId); - * @endcode - * - This function is invoked within the NVS_close() API and is where the - * user should do whatever is required to de-initialize the hardware - * used for asserting and de-assering the SPI chip select signal. - * - The 'nvsHandle` argument is the NVS handle associated with the - * corresponding NVS region. - * - The 'csId' argument passed to this API is a copy of the [spiCsnGpioIndex] - * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) - * field of the corresponding NVS region's NVSSPI25X_HWAttrs structure. - * - * @code - * void NVSSPI25X_assertSpiCs(NVS_Handle nvsHandle, uint16_t csId); - * @endcode - * - This function is called PRIOR to every SPI transfer to and from the SPI - * flash device performed by the NVSSPI25X driver. The user code should - * perform the corresponding action required to select the SPI flash - * device to prepare for the SPI transfer. - * - The 'nvsHandle` argument is the NVS handle associated with the - * corresponding NVS region. - * - The 'csId' argument passed to this API is a copy of the [spiCsnGpioIndex] - * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) - * field of the corresponding NVS region's NVSSPI25X_HWAttrs structure. - * - * @code - * void NVSSPI25X_deassertSpiCs(NVS_Handle nvsHandle, uint16_t csId); - * @endcode - * - This function is called AFTER every SPI transfer to and from the SPI - * flash device performed by the NVSSPI25X driver. The user code should - * perform the corresponding action required to de-select the SPI flash - * device. - * following the SPI transfer. - * - The 'nvsHandle` argument is the NVS handle associated with the - * corresponding NVS region. - * - The 'csId' argument passed to this API is a copy of the [spiCsnGpioIndex] - * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) - * field of the corresponding NVS region's NVSSPI25X_HWAttrs structure. - * - * @warning All 4 of the above APIs must be provided by the user if this - * option is used, otherwise default internal implementations of the APIs - * will be called that will likely lead to application failure. - */ - -#ifndef ti_drivers_nvs_NVSSPI25X__include -#define ti_drivers_nvs_NVSSPI25X__include - -#include -#include - -#include - -#if defined (__cplusplus) -extern "C" { -#endif - -/*! - * @brief Command to perform mass erase of entire flash - * - * As this command can erase flash memory outside the region associated - * with the NVS_Handle passed to the control command, the user must - * carefully orchestrate the use of the command. - * - * Mass Erase is the only control command supported. - */ -#define NVSSPI25X_CMD_MASS_ERASE (NVS_CMD_RESERVED + 0) - -/*! - * @brief Disable internal management of SPI chip select - * - * Some SPI peripherals can be configured to manage their own chip - * select. Setting the [spiCsnGpioIndex] - * (@ref NVSSPI25X_HWAttrs.spiCsnGpioIndex) field of the NVSSPI25X_HWAttrs - * structure to #NVSSPI25X_SPI_MANAGES_CS informs the NVSSPI25X driver - * that the SPI peripheral used by the NVS driver is configured - * to manage its own chip select signal. - */ -#define NVSSPI25X_SPI_MANAGES_CS ((uint16_t)(~0)) - -/*! - * @internal @brief NVS function pointer table - * - * 'NVSSPI25X_fxnTable' is a fully populated function pointer table - * that can be referenced in the NVS_config[] array entries. - * - * Users can minimize their application code size by providing their - * own custom NVS function pointer table that contains only those APIs - * used by the application. - */ -extern const NVS_FxnTable NVSSPI25X_fxnTable; - -/*! - * @brief NVSSPI25X attributes - * - * The 'regionBaseOffset' is the offset, in bytes, from the base of the - * SPI flash, of the flash region to be managed. - * - * The 'regionSize' must be an integer multiple of the flash sector size. - * - * The 'sectorSize' is SPI flash device specific. This parameter should - * correspond to the number of bytes erased when the - * 'SPIFLASH_SUBSECTOR_ERASE' (0x20) command is issued to the device. - * - * The 'verifyBuf' and 'verifyBufSize' parameters are used by the - * NVS_write() command when either 'NVS_WRITE_PRE_VERIFY' or - * 'NVS_WRITE_POST_VERIFY' functions are requested in the 'flags' - * argument. The 'verifyBuf' is used to successively read back portions - * of the flash to compare with the data being written to it. - * - * @code - * // - * // Only one region write operation is performed at a time - * // so a single verifyBuf can be shared by all the regions. - * // - * uint8_t verifyBuf[256]; - * - * NVSSPI25X_HWAttrs nvsSPIHWAttrs[2] = { - * // - * // region 0 is 1 flash sector in length. - * // - * { - * .regionBaseOffset = 0, - * .regionSize = 4096, - * .sectorSize = 4096, - * .verifyBuf = verifyBuf; - * .verifyBufSize = 256; - * .spiHandle = NULL, - * .spiIndex = 0, - * .spiBitRate = 40000000, - * .spiCsnGpioIndex = 12, - * }, - * // - * // region 1 is 3 flash sectors in length. - * // - * { - * .regionBaseOffset = 4096, - * .regionSize = 4096 * 3, - * .sectorSize = 4096, - * .verifyBuf = verifyBuf; // use shared verifyBuf - * .verifyBufSize = 256; - * .spiHandle = NULL, - * .spiIndex = 0, - * .spiBitRate = 40000000, - * .spiCsnGpioIndex = 12, - * } - * }; - * @endcode - */ -typedef struct NVSSPI25X_HWAttrs { - size_t regionBaseOffset; /*!< Offset from base of SPI flash */ - size_t regionSize; /*!< The size of the region in bytes */ - size_t sectorSize; /*!< Erase sector size */ - uint8_t *verifyBuf; /*!< Write Pre/Post verify buffer */ - size_t verifyBufSize; /*!< Write Pre/Post verify buffer size */ - SPI_Handle *spiHandle; /*!< ptr to SPI handle if provided by user. */ - uint16_t spiIndex; /*!< SPI instance index from Board file */ - uint32_t spiBitRate; /*!< SPI bit rate in Hz */ - /*! @brief SPI Flash Chip Select GPIO index - - This field should be set to either an index within the - GPIO driver's GPIO_Config table, or to #NVSSPI25X_SPI_MANAGES_CS. - see [SPI Flash Chip Select Management] (@ref SPI_CS_MGMT) for more - details. - */ - uint16_t spiCsnGpioIndex; - /*! @brief External Flash Status Poll Delay - * - * This field determines how many microseconds the driver waits after - * querying the external flash status. Increasing this value can help - * mitigate CPU starvation if the external flash is busy for long periods - * of time, but may also result in increased latency. - */ - uint32_t statusPollDelayUs; -} NVSSPI25X_HWAttrs; - -/* - * @brief NVSSPI25X Object - * - * The application must not access any member variables of this structure! - */ -typedef struct NVSSPI25X_Object { - bool opened; /* Has this region been opened */ - SPI_Handle spiHandle; - size_t sectorBaseMask; -} NVSSPI25X_Object; - -/* - * @cond NODOC - * NVSSPI25X driver public APIs - */ - -extern void NVSSPI25X_close(NVS_Handle handle); -extern int_fast16_t NVSSPI25X_control(NVS_Handle handle, uint_fast16_t cmd, - uintptr_t arg); -extern int_fast16_t NVSSPI25X_erase(NVS_Handle handle, size_t offset, - size_t size); -extern void NVSSPI25X_getAttrs(NVS_Handle handle, NVS_Attrs *attrs); -extern void NVSSPI25X_init(); -extern int_fast16_t NVSSPI25X_lock(NVS_Handle handle, uint32_t timeout); -extern NVS_Handle NVSSPI25X_open(uint_least8_t index, NVS_Params *params); -extern int_fast16_t NVSSPI25X_read(NVS_Handle handle, size_t offset, - void *buffer, size_t bufferSize); -extern void NVSSPI25X_unlock(NVS_Handle handle); -extern int_fast16_t NVSSPI25X_write(NVS_Handle handle, size_t offset, - void *buffer, size_t bufferSize, uint_fast16_t flags); -/* - * Weakly defined APIs that can be overridden by the user - */ -extern void NVSSPI25X_initSpiCs(NVS_Handle spiHandle, uint16_t csId); -extern void NVSSPI25X_deinitSpiCs(NVS_Handle spiHandle, uint16_t csId); -extern void NVSSPI25X_assertSpiCs(NVS_Handle spiHandle, uint16_t csId); -extern void NVSSPI25X_deassertSpiCs(NVS_Handle spiHandle, uint16_t csId); - -/*! @endcond */ - -#if defined (__cplusplus) -} -#endif /* defined (__cplusplus) */ - -/** @}*/ -#endif /* ti_drivers_nvs_NVSSPI25X__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/package/internal/Power.xdc.h b/ext/hal/ti/simplelink/source/ti/drivers/package/internal/Power.xdc.h deleted file mode 100644 index 94e9ad2c0bf..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/package/internal/Power.xdc.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Do not modify this file; it is automatically - * generated and any modifications will be overwritten. - * - * @(#) xdc-F07 - */ - -#ifndef ti_drivers_Power__INTERNAL__ -#define ti_drivers_Power__INTERNAL__ - -#ifndef ti_drivers_Power__internalaccess -#define ti_drivers_Power__internalaccess -#endif - -#include - -#undef xdc_FILE__ -#ifndef xdc_FILE -#define xdc_FILE__ NULL -#else -#define xdc_FILE__ xdc_FILE -#endif - - - -#endif /* ti_drivers_Power__INTERNAL____ */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/package/package.defs.h b/ext/hal/ti/simplelink/source/ti/drivers/package/package.defs.h deleted file mode 100644 index 3e28f22be45..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/package/package.defs.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Do not modify this file; it is automatically - * generated and any modifications will be overwritten. - * - * @(#) xdc-F07 - */ - -#ifndef ti_drivers__ -#define ti_drivers__ - - -/* - * ======== module ti.drivers.Power ======== - */ - - - -#endif /* ti_drivers__ */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/package/package_ti.drivers.c b/ext/hal/ti/simplelink/source/ti/drivers/package/package_ti.drivers.c deleted file mode 100644 index 52def396367..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/package/package_ti.drivers.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Do not modify this file; it is automatically - * generated and any modifications will be overwritten. - * - * @(#) xdc-F07 - */ - -#include - -__FAR__ char ti_drivers__dummy__; - -#define __xdc_PKGVERS 1, 0, 0 -#define __xdc_PKGNAME ti.drivers -#define __xdc_PKGPREFIX ti_drivers_ - -#ifdef __xdc_bld_pkg_c__ -#define __stringify(a) #a -#define __local_include(a) __stringify(a) -#include __local_include(__xdc_bld_pkg_c__) -#endif - diff --git a/ext/hal/ti/simplelink/source/ti/drivers/power/PowerCC32XX.c b/ext/hal/ti/simplelink/source/ti/drivers/power/PowerCC32XX.c deleted file mode 100644 index d42f8b76903..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/power/PowerCC32XX.c +++ /dev/null @@ -1,1435 +0,0 @@ -/* - * Copyright (c) 2015-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== PowerCC32XX.c ======== - */ - -#include - -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif -#include -#include - -#include - -#include -#include - -#if defined(__IAR_SYSTEMS_ICC__) -#include -#endif - -/* driverlib header files */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define TRUE 1 -#define FALSE 0 -#define STATUS_BUSY 0x01 - -#define PowerCC32XX_SSPIReadStatusInstruction (0x05) -#define PowerCC32XX_SSPIPowerDownInstruction (0xB9) -#define PowerCC32XX_SSPISemaphoreTakeTries (4000000) -#define PowerCC32XX_SSPICSDelay 33 -#define uSEC_DELAY(x) (ROM_UtilsDelayDirect(x*80/3)) - -#define SYNCBARRIER() { \ - __asm(" dsb \n" \ - " isb \n"); \ -} - -/* Externs */ -extern const PowerCC32XX_ConfigV1 PowerCC32XX_config; - -/* Module_State */ -PowerCC32XX_ModuleState PowerCC32XX_module = { - { NULL, NULL}, /* list */ - 0, /* constraintsMask */ - Power_ACTIVE, /* state */ - /* dbRecords */ - { - PRCM_CAMERA, /* PERIPH_CAMERA */ - PRCM_I2S, /* PERIPH_MCASP */ - PRCM_SDHOST, /* PERIPH_MMCHS */ - PRCM_GSPI, /* PERIPH_MCSPI_A1 */ - PRCM_LSPI, /* PERIPH_MCSPI_A2 */ - PRCM_UDMA, /* PERIPH_UDMA_A */ - PRCM_GPIOA0, /* PERIPH_GPIO_A */ - PRCM_GPIOA1, /* PERIPH_GPIO_B */ - PRCM_GPIOA2, /* PERIPH_GPIO_C */ - PRCM_GPIOA3, /* PERIPH_GPIO_D */ - PRCM_GPIOA4, /* PERIPH_GPIO_E */ - PRCM_WDT, /* PERIPH_WDOG_A */ - PRCM_UARTA0, /* PERIPH_UART_A0 */ - PRCM_UARTA1, /* PERIPH_UART_A1 */ - PRCM_TIMERA0, /* PERIPH_GPT_A0 */ - PRCM_TIMERA1, /* PERIPH_GPT_A1 */ - PRCM_TIMERA2, /* PERIPH_GPT_A2 */ - PRCM_TIMERA3, /* PERIPH_GPT_A3 */ - PRCM_DTHE, /* PERIPH_CRYPTO */ - PRCM_SSPI, /* PERIPH_MCSPI_S0 */ - PRCM_I2CA0 /* PERIPH_I2C */ - }, - /* enablePolicy */ - FALSE, - /* initialized */ - FALSE, - /* refCount */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, - /* constraintCounts */ - { 0, 0 }, - /* policyFxn */ - NULL -}; - -/* context save variable */ -PowerCC32XX_SaveRegisters PowerCC32XX_contextSave; - -typedef void (*LPDSFunc)(void); - -/* enter LPDS is an assembly function */ -extern void PowerCC32XX_enterLPDS(LPDSFunc driverlibFunc); - -/* pin parking functions */ -void PowerCC32XX_parkPin(PowerCC32XX_Pin pin, PowerCC32XX_ParkState parkState, - uint32_t * previousState, uint16_t * previousDirection); -void PowerCC32XX_restoreParkedPin(PowerCC32XX_Pin pin, uint32_t type, - uint16_t direction); -void PowerCC32XX_shutdownSSPI(void); - -/* internal functions */ -static int_fast16_t notify(uint_fast16_t eventType); -static void restoreNVICRegs(void); -static void restorePeriphClocks(void); -static void saveNVICRegs(void); -static void parkPins(void); -static void restoreParkedPins(void); - -/* - * ======== Power_disablePolicy ======== - * Do not run the configured policy - */ -bool Power_disablePolicy(void) -{ - bool enablePolicy = PowerCC32XX_module.enablePolicy; - PowerCC32XX_module.enablePolicy = FALSE; - - DebugP_log0("Power: disable policy"); - - return (enablePolicy); -} - -/* - * ======== Power_enablePolicy ======== - * Run the configured policy - */ -void Power_enablePolicy(void) -{ - PowerCC32XX_module.enablePolicy = TRUE; - - DebugP_log0("Power: enable policy"); -} - -/* - * ======== Power_getConstraintMask ======== - * Get a bitmask indicating the constraints that have been registered with - * Power. - */ -uint_fast32_t Power_getConstraintMask(void) -{ - return (PowerCC32XX_module.constraintMask); -} - -/* - * ======== Power_getDependencyCount ======== - * Get the count of dependencies that are currently declared upon a resource. - */ -int_fast16_t Power_getDependencyCount(uint_fast16_t resourceId) -{ - int_fast16_t status; - - if (resourceId >= PowerCC32XX_NUMRESOURCES) { - status = Power_EINVALIDINPUT; - } - else { - status = PowerCC32XX_module.refCount[resourceId]; - } - - return (status); -} - -/* - * ======== Power_getTransitionLatency ======== - * Get the transition latency for a sleep state. The latency is reported - * in units of microseconds. - */ -uint_fast32_t Power_getTransitionLatency(uint_fast16_t sleepState, - uint_fast16_t type) -{ - uint32_t latency = 0; - - if (type == Power_RESUME) { - latency = PowerCC32XX_RESUMETIMELPDS; - } - else { - latency = PowerCC32XX_TOTALTIMELPDS; - } - - return (latency); -} - -/* - * ======== Power_getTransitionState ======== - * Get the current sleep transition state. - */ -uint_fast16_t Power_getTransitionState(void) -{ - return (PowerCC32XX_module.state); -} - -/* - * ======== Power_idleFunc ======== - * Function needs to be plugged into the idle loop. - * It calls the configured policy function if the - * 'enablePolicy' flag is set. - */ -void Power_idleFunc() -{ - if (PowerCC32XX_module.enablePolicy) { - if (PowerCC32XX_module.policyFxn != NULL) { - DebugP_log1("Power: calling policy function (%p)", - (uintptr_t) PowerCC32XX_module.policyFxn); - (*(PowerCC32XX_module.policyFxn))(); - } - } -} - -/* - * ======== Power_init ======== - */ -int_fast16_t Power_init() -{ - /* if this function has already been called, just return */ - if (PowerCC32XX_module.initialized) { - return (Power_SOK); - } - - /* set module state field 'initialized' to true */ - PowerCC32XX_module.initialized = TRUE; - - /* set the module state enablePolicy field */ - PowerCC32XX_module.enablePolicy = PowerCC32XX_config.enablePolicy; - - /* call the config policy init function if its not null */ - if (PowerCC32XX_config.policyInitFxn != NULL) { - (*(PowerCC32XX_config.policyInitFxn))(); - } - - /* copy wakeup settings to module state */ - PowerCC32XX_module.wakeupConfig.enableGPIOWakeupLPDS = - PowerCC32XX_config.enableGPIOWakeupLPDS; - PowerCC32XX_module.wakeupConfig.enableGPIOWakeupShutdown = - PowerCC32XX_config.enableGPIOWakeupShutdown; - PowerCC32XX_module.wakeupConfig.enableNetworkWakeupLPDS = - PowerCC32XX_config.enableNetworkWakeupLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceLPDS = - PowerCC32XX_config.wakeupGPIOSourceLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeLPDS = - PowerCC32XX_config.wakeupGPIOTypeLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS = - PowerCC32XX_config.wakeupGPIOFxnLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDSArg = - PowerCC32XX_config.wakeupGPIOFxnLPDSArg; - PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceShutdown = - PowerCC32XX_config.wakeupGPIOSourceShutdown; - PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeShutdown = - PowerCC32XX_config.wakeupGPIOTypeShutdown; - - /* now configure these wakeup settings in the device... */ - PowerCC32XX_configureWakeup(&PowerCC32XX_module.wakeupConfig); - - /* copy the Power policy function to module state */ - PowerCC32XX_module.policyFxn = PowerCC32XX_config.policyFxn; - - /* spin if too many pins were specified in the pin park array */ - if (PowerCC32XX_config.numPins > PowerCC32XX_NUMPINS) { - while(1){} - } - - /* Initialize CLK GPIO */ - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_18) = 0x281; - - /* Initialize DOUT GPIO */ - HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_19) = 0x281; - - return (Power_SOK); -} - -/* - * ======== Power_registerNotify ======== - * Register a function to be called on a specific power event. - */ -int_fast16_t Power_registerNotify(Power_NotifyObj * pNotifyObj, - uint_fast16_t eventTypes, Power_NotifyFxn notifyFxn, uintptr_t clientArg) -{ - int_fast16_t status = Power_SOK; - - /* check for NULL pointers */ - if ((pNotifyObj == NULL) || (notifyFxn == NULL)) { - status = Power_EINVALIDPOINTER; - } - - else { - /* fill in notify object elements */ - pNotifyObj->eventTypes = eventTypes; - pNotifyObj->notifyFxn = notifyFxn; - pNotifyObj->clientArg = clientArg; - - /* place notify object on event notification queue */ - List_put(&PowerCC32XX_module.notifyList, (List_Elem*)pNotifyObj); - } - - DebugP_log3( - "Power: register notify (%p), eventTypes (0x%x), notifyFxn (%p)", - (uintptr_t) pNotifyObj, eventTypes, (uintptr_t) notifyFxn); - - return (status); -} - -/* - * ======== Power_releaseConstraint ======== - * Release a previously declared constraint. - */ -int_fast16_t Power_releaseConstraint(uint_fast16_t constraintId) -{ - int_fast16_t status = Power_SOK; - uintptr_t key; - uint8_t count; - - /* first ensure constraintId is valid */ - if (constraintId >= PowerCC32XX_NUMCONSTRAINTS) { - status = Power_EINVALIDINPUT; - } - - /* if constraintId is OK ... */ - else { - - /* disable interrupts */ - key = HwiP_disable(); - - /* get the count of the constraint */ - count = PowerCC32XX_module.constraintCounts[constraintId]; - - /* ensure constraint count is not already zero */ - if (count == 0) { - status = Power_EFAIL; - } - - /* if not already zero ... */ - else { - /* decrement the count */ - count--; - - /* save the updated count */ - PowerCC32XX_module.constraintCounts[constraintId] = count; - - /* if constraint count reaches zero, remove constraint from mask */ - if (count == 0) { - PowerCC32XX_module.constraintMask &= ~(1 << constraintId); - } - } - - /* restore interrupts */ - HwiP_restore(key); - - DebugP_log1("Power: release constraint (%d)", constraintId); - } - - return (status); -} - -/* - * ======== Power_releaseDependency ======== - * Release a previously declared dependency. - */ -int_fast16_t Power_releaseDependency(uint_fast16_t resourceId) -{ - int_fast16_t status = Power_SOK; - uint8_t count; - uint32_t id; - uintptr_t key; - - /* first check that resourceId is valid */ - if (resourceId >= PowerCC32XX_NUMRESOURCES) { - status = Power_EINVALIDINPUT; - } - - /* if resourceId is OK ... */ - else { - - /* disable interrupts */ - key = HwiP_disable(); - - /* read the reference count */ - count = PowerCC32XX_module.refCount[resourceId]; - - /* ensure dependency count is not already zero */ - if (count == 0) { - status = Power_EFAIL; - } - - /* if not already zero ... */ - else { - - /* decrement the reference count */ - count--; - - /* if this was the last dependency being released.., */ - if (count == 0) { - /* deactivate this resource ... */ - id = PowerCC32XX_module.dbRecords[resourceId]; - - /* disable clk to peripheral */ - MAP_PRCMPeripheralClkDisable(id, - PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); - } - - /* save the updated count */ - PowerCC32XX_module.refCount[resourceId] = count; - } - - /* restore interrupts */ - HwiP_restore(key); - - DebugP_log1("Power: release dependency (%d)", resourceId); - } - - return (status); -} - -/* - * ======== Power_setConstraint ======== - * Declare an operational constraint. - */ -int_fast16_t Power_setConstraint(uint_fast16_t constraintId) -{ - int_fast16_t status = Power_SOK; - uintptr_t key; - - /* ensure that constraintId is valid */ - if (constraintId >= PowerCC32XX_NUMCONSTRAINTS) { - status = Power_EINVALIDINPUT; - } - - else { - - /* disable interrupts */ - key = HwiP_disable(); - - /* set the specified constraint in the constraintMask */ - PowerCC32XX_module.constraintMask |= 1 << constraintId; - - /* increment the specified constraint count */ - PowerCC32XX_module.constraintCounts[constraintId]++; - - /* restore interrupts */ - HwiP_restore(key); - - DebugP_log1("Power: set constraint (%d)", constraintId); - } - - return (status); -} - -/* - * ======== Power_setDependency ======== - * Declare a dependency upon a resource. - */ -int_fast16_t Power_setDependency(uint_fast16_t resourceId) -{ - int_fast16_t status = Power_SOK; - uint8_t count; - uint32_t id; - uintptr_t key; - - /* ensure resourceId is valid */ - if (resourceId >= PowerCC32XX_NUMRESOURCES) { - status = Power_EINVALIDINPUT; - } - - /* resourceId is OK ... */ - else { - - /* disable interrupts */ - key = HwiP_disable(); - - /* read and increment reference count */ - count = PowerCC32XX_module.refCount[resourceId]++; - - /* if resource was NOT activated previously ... */ - if (count == 0) { - /* now activate this resource ... */ - id = PowerCC32XX_module.dbRecords[resourceId]; - - if(id == PowerCC32XX_PERIPH_LSPI) - { - /* Check NWP generation */ - if((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_DIEID_READ_REG4) >> 24) & 0x02) - { - HWREG(ARCM_BASE + APPS_RCM_O_MCSPI_A2_CLK_GEN) = 0x10303; - } - else - { - HWREG(ARCM_BASE + APPS_RCM_O_MCSPI_A2_CLK_GEN) = 0x00; - } - } - /* enable the peripheral clock to the resource */ - MAP_PRCMPeripheralClkEnable(id, - PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); - - /* spin here until status returns TRUE */ - while(!MAP_PRCMPeripheralStatusGet(id)) { - } - } - - /* restore interrupts */ - HwiP_restore(key); - DebugP_log1("Power: set dependency (%d)", resourceId); - } - - return (status); -} - -/* - * ======== Power_setPolicy ======== - * Set the Power policy function - */ -void Power_setPolicy(Power_PolicyFxn policy) -{ - PowerCC32XX_module.policyFxn = policy; -} - -/* - * ======== Power_shutdown ======== - */ -int_fast16_t Power_shutdown(uint_fast16_t shutdownState, - uint_fast32_t shutdownTime) -{ - int_fast16_t status = Power_EFAIL; - uint32_t constraints; - uintptr_t hwiKey; - uint64_t counts; - - /* disable interrupts */ - hwiKey = HwiP_disable(); - - /* make sure shutdown request doesn't violate a constraint */ - constraints = Power_getConstraintMask(); - if (constraints & (1 << PowerCC32XX_DISALLOW_SHUTDOWN)) { - status = Power_ECHANGE_NOT_ALLOWED; - } - else { - if (PowerCC32XX_module.state == Power_ACTIVE) { - /* set new transition state to entering shutdown */ - PowerCC32XX_module.state = Power_ENTERING_SHUTDOWN; - - /* signal all clients registered for pre-shutdown notification */ - status = notify(PowerCC32XX_ENTERING_SHUTDOWN); - /* check for timeout or any other error */ - if (status != Power_SOK) { - PowerCC32XX_module.state = Power_ACTIVE; - HwiP_restore(hwiKey); - return (status); - } - /* shutdown the flash */ - PowerCC32XX_shutdownSSPI(); - /* if shutdown wakeup time was configured to be large enough */ - if (shutdownTime > (PowerCC32XX_TOTALTIMESHUTDOWN / 1000)) { - /* calculate the wakeup time for hibernate in RTC counts */ - counts = - (((uint64_t)(shutdownTime - - (PowerCC32XX_TOTALTIMESHUTDOWN / 1000)) - * 32768) / 1000); - - /* set the hibernate wakeup time */ - MAP_PRCMHibernateIntervalSet(counts); - - /* enable the wake source to be RTC */ - MAP_PRCMHibernateWakeupSourceEnable(PRCM_HIB_SLOW_CLK_CTR); - } - - /* enable IO retention */ - if (PowerCC32XX_config.ioRetentionShutdown) { - MAP_PRCMIORetentionEnable( - PowerCC32XX_config.ioRetentionShutdown); - } - - DebugP_log2( - "Power: entering shutdown state (%d), shutdownTime (%d)", - shutdownState, shutdownTime); - - /* enter hibernate - we should never return from here */ - MAP_PRCMHibernateEnter(); - } - else { - status = Power_EBUSY; - } - } - - /* set state to Power_ACTIVE */ - PowerCC32XX_module.state = Power_ACTIVE; - - /* re-enable interrupts */ - HwiP_restore(hwiKey); - - /* if get here, failed to shutdown, return error code */ - return (status); -} - -/* - * ======== Power_sleep ======== - */ -int_fast16_t Power_sleep(uint_fast16_t sleepState) -{ - int_fast16_t status = Power_SOK; - uint32_t romMajorVer; - uint32_t romMinorVer; - uint32_t preEvent; - uint32_t postEvent; - uint32_t semBits; - bool earlyPG = true; - - /* first validate the sleep state */ - if (sleepState != PowerCC32XX_LPDS) { - status = Power_EINVALIDINPUT; - } - - else if (PowerCC32XX_module.state == Power_ACTIVE) { - - /* set transition state to entering sleep */ - PowerCC32XX_module.state = Power_ENTERING_SLEEP; - - /* setup sleep vars */ - preEvent = PowerCC32XX_ENTERING_LPDS; - postEvent = PowerCC32XX_AWAKE_LPDS; - - /* signal all clients registered for pre-sleep notification */ - status = notify(preEvent); - - /* check for timeout or any other error */ - if (status != Power_SOK) { - PowerCC32XX_module.state = Power_ACTIVE; - return (status); - } - - DebugP_log1("Power: sleep, sleepState (%d)", sleepState); - - /* invoke specific sequence to activate LPDS ...*/ - - /* enable RAM retention */ - MAP_PRCMSRAMRetentionEnable( - PowerCC32XX_config.ramRetentionMaskLPDS, - PRCM_SRAM_LPDS_RET); - - /* call the enter LPDS hook function if configured */ - if (PowerCC32XX_config.enterLPDSHookFxn != NULL) { - (*(PowerCC32XX_config.enterLPDSHookFxn))(); - } - - /* park pins, based upon board file definitions */ - if (PowerCC32XX_config.pinParkDefs != NULL) { - parkPins(); - } - - /* save the NVIC registers */ - saveNVICRegs(); - - /* check if PG >= 2.01 */ - romMajorVer = HWREG(0x00000400) & 0xFFFF; - romMinorVer = HWREG(0x00000400) >> 16; - if ((romMajorVer >= 3) || ((romMajorVer == 2) && (romMinorVer >= 1))) { - earlyPG = false; - } - - /* call sync barrier */ - SYNCBARRIER(); - - /* now enter LPDS - function does not return... */ - if (PowerCC32XX_config.keepDebugActiveDuringLPDS == TRUE) { - if (earlyPG) { - PowerCC32XX_enterLPDS(PRCMLPDSEnterKeepDebugIf); - } - else { - PowerCC32XX_enterLPDS(ROM_PRCMLPDSEnterKeepDebugIfDirect); - } - } - else { - if (earlyPG) { - PowerCC32XX_enterLPDS(PRCMLPDSEnter); - } - else { - PowerCC32XX_enterLPDS(ROM_PRCMLPDSEnterDirect); - } - } - - /* return here after reset, from Power_resumeLPDS() */ - - /* restore NVIC registers */ - restoreNVICRegs(); - - /* restore clock to those peripherals with dependecy set */ - restorePeriphClocks(); - - /* call PRCMCC3200MCUInit() for any necessary post-LPDS restore */ - MAP_PRCMCC3200MCUInit(); - - /* take the GPIO semaphore bits for the MCU */ - semBits = HWREG(0x400F703C); - semBits = (semBits & ~0x3FF) | 0x155; - HWREG(0x400F703C) = semBits; - - /* call the resume LPDS hook function if configured */ - if (PowerCC32XX_config.resumeLPDSHookFxn != NULL) { - (*(PowerCC32XX_config.resumeLPDSHookFxn))(); - } - - /* re-enable Slow Clock Counter Interrupt */ - MAP_PRCMIntEnable(PRCM_INT_SLOW_CLK_CTR); - - /* set transition state to EXITING_SLEEP */ - PowerCC32XX_module.state = Power_EXITING_SLEEP; - - /* - * signal clients registered for post-sleep notification; for example, - * a driver that needs to reinitialize its peripheral state, that was - * lost during LPDS - */ - status = notify(postEvent); - - /* restore pins parked before LPDS to their previous states */ - if (PowerCC32XX_config.pinParkDefs != NULL) { - restoreParkedPins(); - } - - /* if wake source was GPIO, optionally call wakeup function */ - if (MAP_PRCMLPDSWakeupCauseGet() == PRCM_LPDS_GPIO) { - if (PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS != NULL) { - (*(PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS)) - (PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDSArg); - } - } - - /* now clear the transition state before re-enabling scheduler */ - PowerCC32XX_module.state = Power_ACTIVE; - } - else { - status = Power_EBUSY; - } - - return (status); -} - -/* - * ======== Power_unregisterNotify ======== - * Unregister for a power notification. - * - */ -void Power_unregisterNotify(Power_NotifyObj * pNotifyObj) -{ - uintptr_t key; - - /* disable interrupts */ - key = HwiP_disable(); - - /* remove notify object from its event queue */ - List_remove(&PowerCC32XX_module.notifyList, (List_Elem *)pNotifyObj); - - /* re-enable interrupts */ - HwiP_restore(key); - - DebugP_log1("Power: unregister notify (%p)", (uintptr_t) pNotifyObj); -} - -/*********************** CC32XX-specific functions **************************/ - -/* - * ======== PowerCC32XX_configureWakeup ======== - * Configure LPDS and shutdown wakeups; copy settings into driver state - */ -void PowerCC32XX_configureWakeup(PowerCC32XX_Wakeup *wakeup) -{ - /* configure network (Host IRQ) as wakeup source for LPDS */ - if (wakeup->enableNetworkWakeupLPDS) { - MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_HOST_IRQ); - } - else { - MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_HOST_IRQ); - } - PowerCC32XX_module.wakeupConfig.enableNetworkWakeupLPDS = - wakeup->enableNetworkWakeupLPDS; - - /* configure GPIO as wakeup source for LPDS */ - if (wakeup->enableGPIOWakeupLPDS) { - MAP_PRCMLPDSWakeUpGPIOSelect( - wakeup->wakeupGPIOSourceLPDS, - wakeup->wakeupGPIOTypeLPDS); - MAP_PRCMLPDSWakeupSourceEnable(PRCM_LPDS_GPIO); - } - else { - MAP_PRCMLPDSWakeupSourceDisable(PRCM_LPDS_GPIO); - } - PowerCC32XX_module.wakeupConfig.enableGPIOWakeupLPDS = - wakeup->enableGPIOWakeupLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceLPDS = - wakeup->wakeupGPIOSourceLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeLPDS = - wakeup->wakeupGPIOTypeLPDS; - - /* configure GPIO as wakeup source for Shutdown */ - if (wakeup->enableGPIOWakeupShutdown) { - MAP_PRCMHibernateWakeUpGPIOSelect( - wakeup->wakeupGPIOSourceShutdown, - wakeup->wakeupGPIOTypeShutdown); - MAP_PRCMHibernateWakeupSourceEnable( - wakeup->wakeupGPIOSourceShutdown); - } - else { - MAP_PRCMHibernateWakeupSourceDisable( - wakeup->wakeupGPIOSourceShutdown); - } - PowerCC32XX_module.wakeupConfig.enableGPIOWakeupShutdown = - wakeup->enableGPIOWakeupShutdown; - PowerCC32XX_module.wakeupConfig.wakeupGPIOSourceShutdown = - wakeup->wakeupGPIOSourceShutdown; - PowerCC32XX_module.wakeupConfig.wakeupGPIOTypeShutdown = - wakeup->wakeupGPIOTypeShutdown; - - /* copy the LPDS GPIO wakeup function and arg to module state */ - PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDS = - wakeup->wakeupGPIOFxnLPDS; - PowerCC32XX_module.wakeupConfig.wakeupGPIOFxnLPDSArg = - wakeup->wakeupGPIOFxnLPDSArg; -} - -/* - * ======== PowerCC32XX_disableIORetention ======== - * Disable IO retention and unlock pins after exit from Shutdown - */ -void PowerCC32XX_disableIORetention(unsigned long groupFlags) -{ - MAP_PRCMIORetentionDisable(groupFlags); -} - -/* - * ======== PowerCC32XX_getParkState ======== - * Get the current LPDS park state for a pin - */ -PowerCC32XX_ParkState PowerCC32XX_getParkState(PowerCC32XX_Pin pin) -{ - PowerCC32XX_ParkInfo parkInfo; - PowerCC32XX_ParkState state = PowerCC32XX_DONT_PARK; - uint32_t i; - - DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); - - /* step thru the pin park array until find the pin */ - for (i = 0; i < PowerCC32XX_config.numPins; i++) { - - parkInfo = PowerCC32XX_config.pinParkDefs[i]; - - /* if this is the pin to be checked... */ - if (parkInfo.pin == pin) { - state = (PowerCC32XX_ParkState) parkInfo.parkState; - break; - } - } - - return (state); -} - -/* - * ======== PowerCC32XX_getWakeup ======== - * Get the current LPDS and shutdown wakeup configuration - */ -void PowerCC32XX_getWakeup(PowerCC32XX_Wakeup *wakeup) -{ - *wakeup = PowerCC32XX_module.wakeupConfig; -} - -/* - * ======== PowerCC32XX_parkPin ======== - * Park a device pin in preparation for LPDS - */ -void PowerCC32XX_parkPin(PowerCC32XX_Pin pin, PowerCC32XX_ParkState parkState, - uint32_t * previousType, uint16_t * previousDirection) -{ - unsigned long strength; - unsigned long type; - - /* get the current pin configuration */ - MAP_PinConfigGet(pin, &strength, &type); - - /* stash the current pin type */ - *previousType = type; - - /* get and stash the current pin direction */ - *previousDirection = (uint16_t)MAP_PinDirModeGet(pin); - - /* set pin type to the parking state */ - MAP_PinConfigSet(pin, strength, (unsigned long) parkState); - - /* set pin direction to input to HiZ the pin */ - MAP_PinDirModeSet(pin, PIN_DIR_MODE_IN); -} - -/* - * ======== PowerCC32XX_restoreParkedPin ======== - * Restore a pin that was previously parked with PowerCC32XX_parkPin - */ -void PowerCC32XX_restoreParkedPin(PowerCC32XX_Pin pin, uint32_t type, - uint16_t direction) -{ - unsigned long strength; - unsigned long currentType; - - /* get the current pin configuration */ - MAP_PinConfigGet(pin, &strength, ¤tType); - - /* restore the pin type */ - MAP_PinConfigSet(pin, strength, type); - - /* restore the pin direction */ - MAP_PinDirModeSet(pin, (unsigned long)direction); -} - -/* - * ======== PowerCC32XX_restoreParkState ======== - * Restore the LPDS park state for a pin - */ -void PowerCC32XX_restoreParkState(PowerCC32XX_Pin pin, - PowerCC32XX_ParkState state) -{ - PowerCC32XX_ParkInfo parkInfo; - uint32_t i; - - DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); - - /* step thru the park array until find the pin to be updated */ - for (i = 0; i < PowerCC32XX_config.numPins; i++) { - - parkInfo = PowerCC32XX_config.pinParkDefs[i]; - - /* if this is the pin to be restored... */ - if (parkInfo.pin == pin) { - parkInfo.parkState = state; - PowerCC32XX_config.pinParkDefs[i] = parkInfo; - break; - } - } -} - -/* - * ======== PowerCC32XX_setParkState ======== - * Set a new LPDS park state for a pin - */ -void PowerCC32XX_setParkState(PowerCC32XX_Pin pin, uint32_t level) -{ - PowerCC32XX_ParkInfo parkInfo; - PowerCC32XX_ParkState state; - uint32_t i; - - DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); - - /* first check if level indicates "don't park" */ - if (level == ~1) { - state = PowerCC32XX_DONT_PARK; - } - - /* else, check device revision to choose park state */ - /* if ES2.00 or later, drive the pin */ - else if((HWREG(0x00000400) & 0xFFFF) >= 2) { - state = (level) ? PowerCC32XX_DRIVE_HIGH : PowerCC32XX_DRIVE_LOW; - } - /* else, for earlier devices use the weak pull resistor */ - else { - state = (level) ? PowerCC32XX_WEAK_PULL_UP_STD : - PowerCC32XX_WEAK_PULL_DOWN_STD; - } - - /* step thru the park array until find the pin to be updated */ - for (i = 0; i < PowerCC32XX_config.numPins; i++) { - - parkInfo = PowerCC32XX_config.pinParkDefs[i]; - - /* if this is the pin to be updated... */ - if (parkInfo.pin == pin) { - parkInfo.parkState = state; - PowerCC32XX_config.pinParkDefs[i] = parkInfo; - break; - } - } -} - -/* - * ======== PowerCC32XX_shutdownSSPI ======== - * Put SPI flash into Deep Power Down mode - */ -void PowerCC32XX_shutdownSSPI(void) -{ - unsigned long status = 0; - - /* Acquire SSPI HwSpinlock. */ - if (0 != MAP_HwSpinLockTryAcquire(HWSPINLOCK_SSPI, PowerCC32XX_SSPISemaphoreTakeTries)){ - return; - } - - //Gate MCSPI clock - HWREG(ARCM_BASE + APPS_RCM_O_MCSPI_S0_CLK_GATING) = 0x0; - - /* Enable clock for SSPI module */ - MAP_PRCMPeripheralClkEnable(PRCM_SSPI, PRCM_RUN_MODE_CLK); - - /* Reset SSPI at PRCM level and wait for reset to complete */ - MAP_PRCMPeripheralReset(PRCM_SSPI); - while(MAP_PRCMPeripheralStatusGet(PRCM_SSPI)== false){ - } - - /* Reset SSPI at module level */ - MAP_SPIReset(SSPI_BASE); - - /* Configure SSPI module */ - MAP_SPIConfigSetExpClk(SSPI_BASE,PRCMPeripheralClockGet(PRCM_SSPI), - 20000000,SPI_MODE_MASTER,SPI_SUB_MODE_0, - (SPI_SW_CTRL_CS | - SPI_4PIN_MODE | - SPI_TURBO_OFF | - SPI_CS_ACTIVELOW | - SPI_WL_8)); - - /* Enable SSPI module */ - MAP_SPIEnable(SSPI_BASE); - - // Ungate MCSPI clock - HWREG(ARCM_BASE + APPS_RCM_O_MCSPI_S0_CLK_GATING) = 0x1; - - /* Allow settling before enabling chip select */ - uSEC_DELAY(PowerCC32XX_SSPICSDelay); - - /* Enable chip select for the spi flash. */ - MAP_SPICSEnable(SSPI_BASE); - - /* Wait for spi flash. */ - do{ - /* Send status register read instruction and read back a dummy byte. */ - MAP_SPIDataPut(SSPI_BASE,PowerCC32XX_SSPIReadStatusInstruction); - MAP_SPIDataGet(SSPI_BASE,&status); - - /* Write a dummy byte then read back the actual status. */ - MAP_SPIDataPut(SSPI_BASE,0xFF); - MAP_SPIDataGet(SSPI_BASE,&status); - } while((status & 0xFF )== STATUS_BUSY); - - /* Disable chip select for the spi flash. */ - MAP_SPICSDisable(SSPI_BASE); - - /* Start another CS enable sequence for Power down command. */ - MAP_SPICSEnable(SSPI_BASE); - - /* Send Deep Power Down command to spi flash */ - MAP_SPIDataPut(SSPI_BASE,PowerCC32XX_SSPIPowerDownInstruction); - - /* Disable chip select for the spi flash. */ - MAP_SPICSDisable(SSPI_BASE); - - /* Release SSPI HwSpinlock. */ - MAP_HwSpinLockRelease(HWSPINLOCK_SSPI); - - return; -} - -/* - * ======== PowerCC32XX_reset ======== - * Software reset of specific peripheral. - */ -int_fast16_t PowerCC32XX_reset(uint_fast16_t resourceId) -{ - int_fast16_t status = Power_SOK; - uint32_t id; - - /* Ensure resourceId is valid */ - if (resourceId >= PowerCC32XX_NUMRESOURCES) { - status = Power_EINVALIDINPUT; - } - - /* resourceId is OK ... */ - else { - - id = PowerCC32XX_module.dbRecords[resourceId]; - /* Reset the peripheral */ - MAP_PRCMPeripheralReset(id); - } - return (status); -} - -/*************************internal functions ****************************/ - -/* - * ======== notify ======== - * Note: When this function is called hardware interrupts are disabled - */ -static int_fast16_t notify(uint_fast16_t eventType) -{ - int_fast16_t notifyStatus; - Power_NotifyFxn notifyFxn; - uintptr_t clientArg; - List_Elem *elem; - - /* if queue is empty, return immediately */ - if (!List_empty(&PowerCC32XX_module.notifyList)) { - /* point to first client notify object */ - elem = List_head(&PowerCC32XX_module.notifyList); - - /* walk the queue and notify each registered client of the event */ - do { - if (((Power_NotifyObj *)elem)->eventTypes & eventType) { - /* pull params from notify object */ - notifyFxn = ((Power_NotifyObj *)elem)->notifyFxn; - clientArg = ((Power_NotifyObj *)elem)->clientArg; - - /* call the client's notification function */ - notifyStatus = (int_fast16_t) (*(Power_NotifyFxn)notifyFxn)( - eventType, 0, clientArg); - - /* if client declared error stop all further notifications */ - if (notifyStatus != Power_NOTIFYDONE) { - return (Power_EFAIL); - } - } - - /* get next element in the notification queue */ - elem = List_next(elem); - - } while (elem != NULL); - } - - return (Power_SOK); -} - -/* - * ======== restoreNVICRegs ======== - * Restore the NVIC registers - */ -static void restoreNVICRegs(void) -{ - uint32_t i; - uint32_t *base_reg_addr; - - /* Restore the NVIC control registers */ - HWREG(NVIC_VTABLE) = PowerCC32XX_contextSave.nvicRegs.vectorTable; - HWREG(NVIC_ACTLR) = PowerCC32XX_contextSave.nvicRegs.auxCtrl; - HWREG(NVIC_APINT) = PowerCC32XX_contextSave.nvicRegs.appInt; - HWREG(NVIC_INT_CTRL) = PowerCC32XX_contextSave.nvicRegs.intCtrlState; - HWREG(NVIC_SYS_CTRL) = PowerCC32XX_contextSave.nvicRegs.sysCtrl; - HWREG(NVIC_CFG_CTRL) = PowerCC32XX_contextSave.nvicRegs.configCtrl; - HWREG(NVIC_SYS_PRI1) = PowerCC32XX_contextSave.nvicRegs.sysPri1; - HWREG(NVIC_SYS_PRI2) = PowerCC32XX_contextSave.nvicRegs.sysPri2; - HWREG(NVIC_SYS_PRI3) = PowerCC32XX_contextSave.nvicRegs.sysPri3; - HWREG(NVIC_SYS_HND_CTRL) = PowerCC32XX_contextSave.nvicRegs.sysHcrs; - - /* Systick registers */ - HWREG(NVIC_ST_CTRL) = PowerCC32XX_contextSave.nvicRegs.systickCtrl; - HWREG(NVIC_ST_RELOAD) = PowerCC32XX_contextSave.nvicRegs.systickReload; - HWREG(NVIC_ST_CAL) = PowerCC32XX_contextSave.nvicRegs.systickCalib; - - /* Restore the interrupt priority registers */ - base_reg_addr = (uint32_t *)NVIC_PRI0; - for(i = 0; i < PowerCC32XX_numNVICIntPriority; i++) { - base_reg_addr[i] = PowerCC32XX_contextSave.nvicRegs.intPriority[i]; - } - - /* Restore the interrupt enable registers */ - base_reg_addr = (uint32_t *)NVIC_EN0; - for(i = 0; i < PowerCC32XX_numNVICSetEnableRegs; i++) { - base_reg_addr[i] = PowerCC32XX_contextSave.nvicRegs.intSetEn[i]; - } - - /* Data and instruction sync barriers */ - SYNCBARRIER(); -} - -/* - * ======== restorePeriphClocks ======== - * Restores the peripheral clocks that had dependency set - */ -static void restorePeriphClocks(void) -{ - uint32_t dependCount; - uint32_t i; - - /* need to re-enable peripheral clocks to those with set dependency */ - for (i = 0; i < PowerCC32XX_NUMRESOURCES; i++) { - dependCount = Power_getDependencyCount(i); - if (dependCount > 0) { - MAP_PRCMPeripheralClkEnable(PowerCC32XX_module.dbRecords[i], - PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK); - - while(!MAP_PRCMPeripheralStatusGet(PowerCC32XX_module.dbRecords[i])) { - } - } - } -} - -/* - * ======== saveNVICRegs ======== - * Save away the NVIC registers for LPDS mode. - */ -static void saveNVICRegs(void) -{ - uint32_t i; - uint32_t *base_reg_addr; - - /* Save the NVIC control registers */ - PowerCC32XX_contextSave.nvicRegs.vectorTable = HWREG(NVIC_VTABLE); - PowerCC32XX_contextSave.nvicRegs.auxCtrl = HWREG(NVIC_ACTLR); - PowerCC32XX_contextSave.nvicRegs.intCtrlState = HWREG(NVIC_INT_CTRL); - PowerCC32XX_contextSave.nvicRegs.appInt = HWREG(NVIC_APINT); - PowerCC32XX_contextSave.nvicRegs.sysCtrl = HWREG(NVIC_SYS_CTRL); - PowerCC32XX_contextSave.nvicRegs.configCtrl = HWREG(NVIC_CFG_CTRL); - PowerCC32XX_contextSave.nvicRegs.sysPri1 = HWREG(NVIC_SYS_PRI1); - PowerCC32XX_contextSave.nvicRegs.sysPri2 = HWREG(NVIC_SYS_PRI2); - PowerCC32XX_contextSave.nvicRegs.sysPri3 = HWREG(NVIC_SYS_PRI3); - PowerCC32XX_contextSave.nvicRegs.sysHcrs = HWREG(NVIC_SYS_HND_CTRL); - - /* Systick registers */ - PowerCC32XX_contextSave.nvicRegs.systickCtrl = HWREG(NVIC_ST_CTRL); - PowerCC32XX_contextSave.nvicRegs.systickReload = HWREG(NVIC_ST_RELOAD); - PowerCC32XX_contextSave.nvicRegs.systickCalib = HWREG(NVIC_ST_CAL); - - /* Save the interrupt enable registers */ - base_reg_addr = (uint32_t *)NVIC_EN0; - for (i = 0; i < PowerCC32XX_numNVICSetEnableRegs; i++) { - PowerCC32XX_contextSave.nvicRegs.intSetEn[i] = base_reg_addr[i]; - } - - /* Save the interrupt priority registers */ - base_reg_addr = (uint32_t *)NVIC_PRI0; - for (i = 0; i < PowerCC32XX_numNVICIntPriority; i++) { - PowerCC32XX_contextSave.nvicRegs.intPriority[i] = base_reg_addr[i]; - } -} - -/* - * ======== parkPins ======== - */ -static void parkPins(void) -{ - PowerCC32XX_ParkInfo parkInfo; - uint32_t antpadreg; - uint32_t i; - - DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); - - /* for each pin in the park array ... */ - for (i = 0; i < PowerCC32XX_config.numPins; i++) { - - parkInfo = PowerCC32XX_config.pinParkDefs[i]; - - /* skip this pin if "don't park" is specified */ - if (parkInfo.parkState == PowerCC32XX_DONT_PARK) { - continue; - } - - /* if this is a special antenna select pin, stash current pad state */ - if (parkInfo.pin == PowerCC32XX_PIN29) { - antpadreg = 0x4402E108; - PowerCC32XX_module.stateAntPin29 = (uint16_t) HWREG(antpadreg); - } - else if (parkInfo.pin == PowerCC32XX_PIN30) { - antpadreg = 0x4402E10C; - PowerCC32XX_module.stateAntPin30 = (uint16_t) HWREG(antpadreg); - } - else { - antpadreg = 0; - } - - /* if this is antenna select pin, park via direct writes to pad reg */ - if (antpadreg != 0) { - HWREG(antpadreg) &= 0xFFFFF0EF; /* first clear bits 4, 8-11 */ - if (parkInfo.parkState == PowerCC32XX_NO_PULL_HIZ) { - HWREG(antpadreg) |= 0x00000C00; - } - else if (parkInfo.parkState == PowerCC32XX_WEAK_PULL_UP_STD) { - HWREG(antpadreg) |= 0x00000D00; - } - else if (parkInfo.parkState == PowerCC32XX_WEAK_PULL_DOWN_STD) { - HWREG(antpadreg) |= 0x00000E00; - } - else if (parkInfo.parkState == PowerCC32XX_WEAK_PULL_UP_OPENDRAIN) { - HWREG(antpadreg) |= 0x00000D10; - } - else if (parkInfo.parkState == - PowerCC32XX_WEAK_PULL_DOWN_OPENDRAIN) { - HWREG(antpadreg) |= 0x00000E10; - } - } - - /* else, for all other pins */ - else { - - /* if pin is NOT to be driven, park it to the specified state... */ - if ((parkInfo.parkState != PowerCC32XX_DRIVE_LOW) && - (parkInfo.parkState != PowerCC32XX_DRIVE_HIGH)) { - - PowerCC32XX_parkPin( - (PowerCC32XX_Pin)parkInfo.pin, - (PowerCC32XX_ParkState)parkInfo.parkState, - &PowerCC32XX_module.pinType[i], - &PowerCC32XX_module.pinDir[i]); - } - - /* - * else, now check if the pin CAN be driven (pins 45, 53, and 55 - * can't be driven) - */ - else if ((parkInfo.pin != PowerCC32XX_PIN45) && - (parkInfo.pin != PowerCC32XX_PIN53) && - (parkInfo.pin != PowerCC32XX_PIN55)){ - - /* - * must ensure pin mode is zero; first get/stash current mode, - * then set mode to zero - */ - PowerCC32XX_module.pinMode[i] = - (uint8_t)MAP_PinModeGet(parkInfo.pin); - MAP_PinModeSet(parkInfo.pin, 0); - - /* if pin is to be driven low, set the lock level to 0 */ - if (parkInfo.parkState == PowerCC32XX_DRIVE_LOW) { - MAP_PinLockLevelSet((PowerCC32XX_Pin)parkInfo.pin, 0); - PowerCC32XX_module.pinLockMask |= 1 << - PinToPadGet(parkInfo.pin); - } - - /* else, pin to be driven high, set lock level to 1 */ - else { - MAP_PinLockLevelSet((PowerCC32XX_Pin)parkInfo.pin, 1); - PowerCC32XX_module.pinLockMask |= 1 << - PinToPadGet(parkInfo.pin); - } - } - } - } - - /* if any pins are to be driven, lock them now */ - if (PowerCC32XX_module.pinLockMask) { - MAP_PinLock(PowerCC32XX_module.pinLockMask); - } -} - -/* - * ======== restoreParkedPins ======== - */ -static void restoreParkedPins(void) -{ - PowerCC32XX_ParkInfo parkInfo; - uint32_t i; - - DebugP_assert(PowerCC32XX_config.numPins < PowerCC32XX_NUMPINS + 1); - - /* first, unlock any locked pins (that were driven high or low) */ - if (PowerCC32XX_module.pinLockMask) { - MAP_PinUnlock(); - } - - /* now, for each pin in the park array ... */ - for (i = 0; i < PowerCC32XX_config.numPins; i++) { - - parkInfo = PowerCC32XX_config.pinParkDefs[i]; - - /* skip this pin if "don't park" is specified */ - if (parkInfo.parkState == PowerCC32XX_DONT_PARK) { - continue; - } - - /* if this is special antenna select pin: restore the saved pad state */ - if (parkInfo.pin == PowerCC32XX_PIN29) { - HWREG(0x4402E108) = ((HWREG(0x4402E108) & 0xFFFFF000) | - (PowerCC32XX_module.stateAntPin29 & 0x00000FFF)); - } - - else if (parkInfo.pin == PowerCC32XX_PIN30) { - HWREG(0x4402E10C) = ((HWREG(0x4402E10C) & 0xFFFFF000) | - (PowerCC32XX_module.stateAntPin30 & 0x00000FFF)); - } - - /* else if pin was driven during LPDS, restore the pin mode */ - else if ((parkInfo.parkState == PowerCC32XX_DRIVE_LOW) || - (parkInfo.parkState == PowerCC32XX_DRIVE_HIGH)) { - MAP_PinModeSet(parkInfo.pin, - (unsigned long)PowerCC32XX_module.pinMode[i]); - } - - /* else, restore all others */ - else { - /* if pin parked in a non-driven state, restore type & direction */ - if ((parkInfo.parkState != PowerCC32XX_DRIVE_LOW) && - (parkInfo.parkState != PowerCC32XX_DRIVE_HIGH)) { - - PowerCC32XX_restoreParkedPin( - (PowerCC32XX_Pin)parkInfo.pin, - PowerCC32XX_module.pinType[i], - PowerCC32XX_module.pinDir[i]); - } - } - } -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/power/PowerCC32XX.h b/ext/hal/ti/simplelink/source/ti/drivers/power/PowerCC32XX.h deleted file mode 100644 index 25db541469f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/power/PowerCC32XX.h +++ /dev/null @@ -1,660 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file PowerCC32XX.h - * - * @brief Power manager interface for the CC32XX - * - * The Power header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref Power.h for a complete description of APIs. - * - * ## Implementation # - * This module defines the power resources, constraints, events, sleep - * states and transition latencies for CC32XX. - * - * A reference power policy is provided which can transition the MCU from the - * active state to one of two sleep states: LPDS or Sleep. - * The policy looks at the estimated idle time remaining, and the active - * constraints, and determine which sleep state to transition to. The - * policy will give first preference to choosing LPDS, but if that is not - * appropriate (e.g., not enough idle time), it will choose Sleep. - * - * ============================================================================ - */ - -#ifndef ti_drivers_power_PowerCC32XX__include -#define ti_drivers_power_PowerCC32XX__include - -#include -#include -#include - -/* driverlib header files */ -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/* latency values were measured with a logic analyzer, and rounded up */ - -/*! The latency to reserve for resuming from LPDS (usec) */ -#define PowerCC32XX_RESUMETIMELPDS 2500 - -/*! The total latency to reserve for entry to and exit from LPDS (usec) */ -#define PowerCC32XX_TOTALTIMELPDS 20000 - -/*! The total latency to reserve for entry to and exit from Shutdown (usec) */ -#define PowerCC32XX_TOTALTIMESHUTDOWN 500000 - -/* Power resources */ -#define PowerCC32XX_PERIPH_CAMERA 0 -/*!< Resource ID: Camera */ - -#define PowerCC32XX_PERIPH_I2S 1 -/*!< Resource ID: I2S */ - -#define PowerCC32XX_PERIPH_SDHOST 2 -/*!< Resource ID: SDHost */ - -#define PowerCC32XX_PERIPH_GSPI 3 -/*!< Resource ID: General Purpose SPI (GSPI) */ - -#define PowerCC32XX_PERIPH_LSPI 4 -/*!< Resource ID: LSPI */ - -#define PowerCC32XX_PERIPH_UDMA 5 -/*!< Resource ID: uDMA Controller */ - -#define PowerCC32XX_PERIPH_GPIOA0 6 -/*!< Resource ID: General Purpose I/O Port A0 */ - -#define PowerCC32XX_PERIPH_GPIOA1 7 -/*!< Resource ID: General Purpose I/O Port A1 */ - -#define PowerCC32XX_PERIPH_GPIOA2 8 -/*!< Resource ID: General Purpose I/O Port A2 */ - -#define PowerCC32XX_PERIPH_GPIOA3 9 -/*!< Resource ID: General Purpose I/O Port A3 */ - -#define PowerCC32XX_PERIPH_GPIOA4 10 -/*!< Resource ID: General Purpose I/O Port A4 */ - -#define PowerCC32XX_PERIPH_WDT 11 -/*!< Resource ID: Watchdog module */ - -#define PowerCC32XX_PERIPH_UARTA0 12 -/*!< Resource ID: UART 0 */ - -#define PowerCC32XX_PERIPH_UARTA1 13 -/*!< Resource ID: UART 1 */ - -#define PowerCC32XX_PERIPH_TIMERA0 14 -/*!< Resource ID: General Purpose Timer A0 */ - -#define PowerCC32XX_PERIPH_TIMERA1 15 -/*!< Resource ID: General Purpose Timer A1 */ - -#define PowerCC32XX_PERIPH_TIMERA2 16 -/*!< Resource ID: General Purpose Timer A2 */ - -#define PowerCC32XX_PERIPH_TIMERA3 17 -/*!< Resource ID: General Purpose Timer A3 */ - -#define PowerCC32XX_PERIPH_DTHE 18 -/*!< Resource ID: Cryptography Accelerator (DTHE) */ - -#define PowerCC32XX_PERIPH_SSPI 19 -/*!< Resource ID: Serial Flash SPI (SSPI) */ - -#define PowerCC32XX_PERIPH_I2CA0 20 -/*!< Resource ID: I2C */ - -/* \cond */ -#define PowerCC32XX_NUMRESOURCES 21 /* Number of resources in database */ -/* \endcond */ - -/* - * Power constraints on the CC32XX device - */ -#define PowerCC32XX_DISALLOW_LPDS 0 -/*!< Constraint: Disallow entry to Low Power Deep Sleep (LPDS) */ - -#define PowerCC32XX_DISALLOW_SHUTDOWN 1 -/*!< Constraint: Disallow entry to Shutdown */ - -/* \cond */ -#define PowerCC32XX_NUMCONSTRAINTS 2 /*!< number of constraints */ -/* \endcond */ - -/* - * Power events on the CC32XX device - * - * Each event must be a power of two, and the event IDs must be sequential - * without any gaps. - */ -#define PowerCC32XX_ENTERING_LPDS 0x1 -/*!< Power event: The device is entering the LPDS sleep state */ - -#define PowerCC32XX_ENTERING_SHUTDOWN 0x2 -/*!< Power event: The device is entering the Shutdown state */ - -#define PowerCC32XX_AWAKE_LPDS 0x4 -/*!< Power event: The device is waking from the LPDS sleep state */ - -/* \cond */ -#define PowerCC32XX_NUMEVENTS 3 /*!< number of events */ -/* \endcond */ - -/* Power sleep states */ -#define PowerCC32XX_LPDS 0x1 /*!< The LPDS sleep state */ - -/* \cond */ -/* Use by NVIC Register structure */ -#define PowerCC32XX_numNVICSetEnableRegs 6 -#define PowerCC32XX_numNVICIntPriority 49 -/* \endcond */ - -/* \cond */ -/* Number of pins that can be parked in LPDS */ -#define PowerCC32XX_NUMPINS 34 -/* \endcond */ - -/*! @brief Used to specify parking of a pin during LPDS */ -typedef struct PowerCC32XX_ParkInfo { - uint32_t pin; - /*!< The pin to be parked */ - uint32_t parkState; - /*!< The state to park the pin (an enumerated PowerCC32XX_ParkState) */ -} PowerCC32XX_ParkInfo; - -/*! @brief Power global configuration */ -typedef struct PowerCC32XX_ConfigV1 { - /*! Initialization function for the power policy */ - Power_PolicyInitFxn policyInitFxn; - /*! The power policy function */ - Power_PolicyFxn policyFxn; - /*! - * @brief Hook function called before entering LPDS - * - * This function is called after any notifications are complete, - * and before any pins are parked, just before entry to LPDS. - */ - void (*enterLPDSHookFxn)(void); - /*! - * @brief Hook function called when resuming from LPDS - * - * This function is called early in the wake sequence, before any - * notification functions are run. - */ - void (*resumeLPDSHookFxn)(void); - /*! Determines whether to run the power policy function */ - bool enablePolicy; - /*! Enable GPIO as a wakeup source for LPDS */ - bool enableGPIOWakeupLPDS; - /*! Enable GPIO as a wakeup source for shutdown */ - bool enableGPIOWakeupShutdown; - /*! Enable Network activity as a wakeup source for LPDS */ - bool enableNetworkWakeupLPDS; - /*! - * @brief The GPIO source for wakeup from LPDS - * - * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source - * for LPDS. The GPIO must be specified as one of the following (as - * defined in driverlib/prcm.h): PRCM_LPDS_GPIO2, PRCM_LPDS_GPIO4, - * PRCM_LPDS_GPIO11, PRCM_LPDS_GPIO13, PRCM_LPDS_GPIO17, PRCM_LPDS_GPIO24, - * PRCM_LPDS_GPIO26 - */ - uint32_t wakeupGPIOSourceLPDS; - /*! - * @brief The GPIO trigger type for wakeup from LPDS - * - * Value can be one of the following (defined in driverlib/prcm.h): - * PRCM_LPDS_LOW_LEVEL, PRCM_LPDS_HIGH_LEVEL, - * PRCM_LPDS_FALL_EDGE, PRCM_LPDS_RISE_EDGE - */ - uint32_t wakeupGPIOTypeLPDS; - /*! - * @brief Function to be called when the configured GPIO triggers wakeup - * from LPDS - * - * During LPDS the internal GPIO module is powered off, and special - * periphery logic is used instead to detect the trigger and wake the - * device. No GPIO interrupt service routine will be triggered in this - * case (even if an ISR is configured, and used normally to detect GPIO - * interrupts when not in LPDS). This function can be used in lieu of a - * GPIO ISR, to take specific action upon LPDS wakeup. - * - * A value of NULL indicates no GPIO wakeup function will be called. - * - * An argument for this wakeup function can be specified via - * wakeupGPIOFxnLPDSArg. - * - * Note that this wakeup function will be called as one of the last steps - * in Power_sleep(), after all notifications have been sent out, and after - * pins have been restored to their previous (non-parked) states. - */ - void (*wakeupGPIOFxnLPDS)(uint_least8_t argument); - /*! - * @brief The argument to be passed to wakeupGPIOFxnLPDS() - */ - uint_least8_t wakeupGPIOFxnLPDSArg; - /*! - * @brief The GPIO sources for wakeup from shutdown - * - * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source - * for Shutdown. The GPIO must be specified as one of the following (as - * defined in driverlib/prcm.h): PRCM_HIB_GPIO2, PRCM_HIB_GPIO4, - * PRCM_HIB_GPIO11, PRCM_HIB_GPIO13, PRCM_HIB_GPIO17, PRCM_HIB_GPIO24, - * PRCM_HIB_GPIO26 - */ - uint32_t wakeupGPIOSourceShutdown; - /*! - * @brief The GPIO trigger type for wakeup from shutdown - * - * Value can be one of the following (defined in driverlib/prcm.h): - * PRCM_HIB_LOW_LEVEL, PRCM_HIB_HIGH_LEVEL, - * PRCM_HIB_FALL_EDGE, PRCM_HIB_RISE_EDGE - */ - uint32_t wakeupGPIOTypeShutdown; - /*! - * @brief SRAM retention mask for LPDS - * - * Value can be a mask of the following (defined in driverlib/prcm.h): - * PRCM_SRAM_COL_1, PRCM_SRAM_COL_2, PRCM_SRAM_COL_3, - * PRCM_SRAM_COL_4 - */ - uint32_t ramRetentionMaskLPDS; - /*! - * @brief Keep debug interface active during LPDS - * - * This Boolean controls whether the debug interface will be left active - * when LPDS is entered. For best power savings this flag should be set - * to false. Setting the flag to true will enable better debug - * capability, but will prevent full LPDS, and will result in increased - * power consumption. - */ - bool keepDebugActiveDuringLPDS; - /*! - * @brief IO retention mask for Shutdown - * - * Value can be a mask of the following (defined in driverlib/prcm.h): - * PRCM_IO_RET_GRP_0, PRCM_IO_RET_GRP_1, PRCM_IO_RET_GRP_2 - * PRCM_IO_RET_GRP_3 - */ - uint32_t ioRetentionShutdown; - /*! - * @brief Pointer to an array of pins to be parked during LPDS - * - * A value of NULL will disable parking of any pins during LPDS - */ - PowerCC32XX_ParkInfo * pinParkDefs; - /*! - * @brief Number of pins to be parked during LPDS - */ - uint32_t numPins; -} PowerCC32XX_ConfigV1; - -/*! - * @cond NODOC - * NVIC registers that need to be saved before entering LPDS. - */ -typedef struct PowerCC32XX_NVICRegisters { - uint32_t vectorTable; - uint32_t auxCtrl; - uint32_t intCtrlState; - uint32_t appInt; - uint32_t sysCtrl; - uint32_t configCtrl; - uint32_t sysPri1; - uint32_t sysPri2; - uint32_t sysPri3; - uint32_t sysHcrs; - uint32_t systickCtrl; - uint32_t systickReload; - uint32_t systickCalib; - uint32_t intSetEn[PowerCC32XX_numNVICSetEnableRegs]; - uint32_t intPriority[PowerCC32XX_numNVICIntPriority]; -} PowerCC32XX_NVICRegisters; -/*! @endcond */ - -/*! - * @cond NODOC - * MCU core registers that need to be save before entering LPDS. - */ -typedef struct PowerCC32XX_MCURegisters { - uint32_t msp; - uint32_t psp; - uint32_t psr; - uint32_t primask; - uint32_t faultmask; - uint32_t basepri; - uint32_t control; -} PowerCC32XX_MCURegisters; -/*! @endcond */ - -/*! - * @cond NODOC - * Structure of context registers to save before entering LPDS. - */ -typedef struct PowerCC32XX_SaveRegisters { - PowerCC32XX_MCURegisters m4Regs; - PowerCC32XX_NVICRegisters nvicRegs; -} PowerCC32XX_SaveRegisters; -/*! @endcond */ - -/*! @brief Enumeration of states a pin can be parked in */ -typedef enum { - /*! No pull resistor, leave pin in a HIZ state */ - PowerCC32XX_NO_PULL_HIZ = PIN_TYPE_STD, - /*! Pull-up resistor for standard pin type */ - PowerCC32XX_WEAK_PULL_UP_STD = PIN_TYPE_STD_PU, - /*! Pull-down resistor for standard pin type */ - PowerCC32XX_WEAK_PULL_DOWN_STD = PIN_TYPE_STD_PD, - /*! Pull-up resistor for open drain pin type */ - PowerCC32XX_WEAK_PULL_UP_OPENDRAIN = PIN_TYPE_OD_PU, - /*! Pull-down resistor for open drain pin type */ - PowerCC32XX_WEAK_PULL_DOWN_OPENDRAIN = PIN_TYPE_OD_PD, - /*! Drive pin to a low logic state */ - PowerCC32XX_DRIVE_LOW, - /*! Drive pin to a high logic state */ - PowerCC32XX_DRIVE_HIGH, - /*! Take no action; do not park the pin */ - PowerCC32XX_DONT_PARK -} PowerCC32XX_ParkState; - -/*! @brief Enumeration of pins that can be parked */ -typedef enum { - /*! PIN_01 */ - PowerCC32XX_PIN01 = PIN_01, - /*! PIN_02 */ - PowerCC32XX_PIN02 = PIN_02, - /*! PIN_03 */ - PowerCC32XX_PIN03 = PIN_03, - /*! PIN_04 */ - PowerCC32XX_PIN04 = PIN_04, - /*! PIN_05 */ - PowerCC32XX_PIN05 = PIN_05, - /*! PIN_06 */ - PowerCC32XX_PIN06 = PIN_06, - /*! PIN_07 */ - PowerCC32XX_PIN07 = PIN_07, - /*! PIN_08 */ - PowerCC32XX_PIN08 = PIN_08, - /*! PIN_11 */ - PowerCC32XX_PIN11 = PIN_11, - /*! PIN_12 */ - PowerCC32XX_PIN12 = PIN_12, - /*! PIN_13 */ - PowerCC32XX_PIN13 = PIN_13, - /*! PIN_14 */ - PowerCC32XX_PIN14 = PIN_14, - /*! PIN_15 */ - PowerCC32XX_PIN15 = PIN_15, - /*! PIN_16 */ - PowerCC32XX_PIN16 = PIN_16, - /*! PIN_17 */ - PowerCC32XX_PIN17 = PIN_17, - /*! PIN_18 */ - PowerCC32XX_PIN18 = PIN_18, - /*! PIN_19 */ - PowerCC32XX_PIN19 = PIN_19, - /*! PIN_20 */ - PowerCC32XX_PIN20 = PIN_20, - /*! PIN_21 */ - PowerCC32XX_PIN21 = PIN_21, - /*! PIN_29 */ - PowerCC32XX_PIN29 = 0x1C, - /*! PIN_30 */ - PowerCC32XX_PIN30 = 0x1D, - /*! PIN_45 */ - PowerCC32XX_PIN45 = PIN_45, - /*! PIN_50 */ - PowerCC32XX_PIN50 = PIN_50, - /*! PIN_52 */ - PowerCC32XX_PIN52 = PIN_52, - /*! PIN_53 */ - PowerCC32XX_PIN53 = PIN_53, - /*! PIN_55 */ - PowerCC32XX_PIN55 = PIN_55, - /*! PIN_57 */ - PowerCC32XX_PIN57 = PIN_57, - /*! PIN_58 */ - PowerCC32XX_PIN58 = PIN_58, - /*! PIN_59 */ - PowerCC32XX_PIN59 = PIN_59, - /*! PIN_60 */ - PowerCC32XX_PIN60 = PIN_60, - /*! PIN_61 */ - PowerCC32XX_PIN61 = PIN_61, - /*! PIN_62 */ - PowerCC32XX_PIN62 = PIN_62, - /*! PIN_63 */ - PowerCC32XX_PIN63 = PIN_63, - /*! PIN_64 */ - PowerCC32XX_PIN64 = PIN_64 -} PowerCC32XX_Pin; - -/*! - * @brief Specify the wakeup sources for LPDS and Shutdown - * - * The wakeup sources for LPDS and Shutdown can be dynamically changed - * at runtime, via PowerCC32XX_configureWakeup(). The application - * should fill a structure of this type, and pass it as the parameter - * to PowerCC32XX_configureWakeup() to specify the new wakeup settings. - */ -typedef struct PowerCC32XX_Wakeup { - /*! Enable GPIO as a wakeup source for LPDS */ - bool enableGPIOWakeupLPDS; - /*! Enable GPIO as a wakeup source for shutdown */ - bool enableGPIOWakeupShutdown; - /*! Enable Network activity as a wakeup source for LPDS */ - bool enableNetworkWakeupLPDS; - /*! - * @brief The GPIO source for wakeup from LPDS - * - * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source - * for LPDS. The GPIO must be specified as one of the following (as - * defined in driverlib/prcm.h): PRCM_LPDS_GPIO2, PRCM_LPDS_GPIO4, - * PRCM_LPDS_GPIO11, PRCM_LPDS_GPIO13, PRCM_LPDS_GPIO17, PRCM_LPDS_GPIO24, - * PRCM_LPDS_GPIO26 - */ - uint32_t wakeupGPIOSourceLPDS; - /*! - * @brief The GPIO trigger type for wakeup from LPDS - * - * Value can be one of the following (defined in driverlib/prcm.h): - * PRCM_LPDS_LOW_LEVEL, PRCM_LPDS_HIGH_LEVEL, - * PRCM_LPDS_FALL_EDGE, PRCM_LPDS_RISE_EDGE - */ - uint32_t wakeupGPIOTypeLPDS; - /*! - * @brief Function to be called when the configured GPIO triggers wakeup - * from LPDS - * - * During LPDS the internal GPIO module is powered off, and special - * periphery logic is used instead to detect the trigger and wake the - * device. No GPIO interrupt service routine will be triggered in this - * case (even if an ISR is configured, and used normally to detect GPIO - * interrupts when not in LPDS). This function can be used in lieu of a - * GPIO ISR, to take specific action upon LPDS wakeup. - * - * A value of NULL indicates no GPIO wakeup function will be called. - * - * An argument for this wakeup function can be specified via - * wakeupGPIOFxnLPDSArg. - * - * Note that this wakeup function will be called as one of the last steps - * in Power_sleep(), after all notifications have been sent out, and after - * pins have been restored to their previous (non-parked) states. - */ - void (*wakeupGPIOFxnLPDS)(uint_least8_t argument); - /*! - * @brief The argument to be passed to wakeupGPIOFxnLPDS() - */ - uint_least8_t wakeupGPIOFxnLPDSArg; - /*! - * @brief The GPIO sources for wakeup from shutdown - * - * Only one GPIO {2,4,11,13,17,24,26} can be specified as a wake source - * for Shutdown. The GPIO must be specified as one of the following (as - * defined in driverlib/prcm.h): PRCM_HIB_GPIO2, PRCM_HIB_GPIO4, - * PRCM_HIB_GPIO11, PRCM_HIB_GPIO13, PRCM_HIB_GPIO17, PRCM_HIB_GPIO24, - * PRCM_HIB_GPIO26 - */ - uint32_t wakeupGPIOSourceShutdown; - /*! - * @brief The GPIO trigger type for wakeup from shutdown - * - * Value can be one of the following (defined in driverlib/prcm.h): - * PRCM_HIB_LOW_LEVEL, PRCM_HIB_HIGH_LEVEL, - * PRCM_HIB_FALL_EDGE, PRCM_HIB_RISE_EDGE - */ - uint32_t wakeupGPIOTypeShutdown; -} PowerCC32XX_Wakeup; - -/*! - * @cond NODOC - * Internal structure defining Power module state. - */ -typedef struct PowerCC32XX_ModuleState { - List_List notifyList; - uint32_t constraintMask; - uint32_t state; - uint16_t dbRecords[PowerCC32XX_NUMRESOURCES]; - bool enablePolicy; - bool initialized; - uint8_t refCount[PowerCC32XX_NUMRESOURCES]; - uint8_t constraintCounts[PowerCC32XX_NUMCONSTRAINTS]; - Power_PolicyFxn policyFxn; - uint32_t pinType[PowerCC32XX_NUMPINS]; - uint16_t pinDir[PowerCC32XX_NUMPINS]; - uint8_t pinMode[PowerCC32XX_NUMPINS]; - uint16_t stateAntPin29; - uint16_t stateAntPin30; - uint32_t pinLockMask; - PowerCC32XX_Wakeup wakeupConfig; -} PowerCC32XX_ModuleState; -/*! @endcond */ - -/*! - * @brief Function configures wakeup for LPDS and shutdown - * - * This function allows the app to configure the GPIO source and - * type for waking up from LPDS and shutdown and the network host - * as a wakeup source for LPDS. This overwrites any previous - * wakeup settings. - * - * @param wakeup Settings applied to wakeup configuration - */ -void PowerCC32XX_configureWakeup(PowerCC32XX_Wakeup *wakeup); - -/*! OS-specific power policy initialization function */ -void PowerCC32XX_initPolicy(void); - -/*! - * @brief Function to get wakeup configuration settings - * - * This function allows an app to query the current LPDS and shutdown - * wakeup configuration settings. - * - * @param wakeup A PowerCC32XX_Wakeup structure to be written into - */ -void PowerCC32XX_getWakeup(PowerCC32XX_Wakeup *wakeup); - -/*! CC32XX-specific function to query the LPDS park state for a pin */ -PowerCC32XX_ParkState PowerCC32XX_getParkState(PowerCC32XX_Pin pin); - -/*! CC32XX-specific function to restore the LPDS park state for a pin */ -void PowerCC32XX_restoreParkState(PowerCC32XX_Pin pin, - PowerCC32XX_ParkState state); - -/*! CC32XX-specific function to dynamically set the LPDS park state for a pin */ -void PowerCC32XX_setParkState(PowerCC32XX_Pin pin, uint32_t level); - -/*! - * @brief Function to disable IO retention and unlock pin groups following - * exit from Shutdown. - * - * PowerCC32XX_ConfigV1.ioRetentionShutdown can be used to specify locking and - * retention of pin groups during Shutdown. Upon exit from Shutdown, and - * when appropriate, an application can call this function, to - * correspondingly disable IO retention, and unlock the specified pin groups. - * - * @param groupFlags A logical OR of one or more of the following - * flags (defined in driverlib/prcm.h): - * PRCM_IO_RET_GRP_0 - all pins except sFlash and JTAG interface - * PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14 - * PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17 - * PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20 - */ -void PowerCC32XX_disableIORetention(unsigned long groupFlags); - -/*! OS-specific power policy function */ -void PowerCC32XX_sleepPolicy(void); - -/*! - * @brief Software reset of a resource - * - * This function performs a software reset of a resource. - * - * Resource identifiers are device specific, and defined in the - * device-specific Power include file. For example, the resources for - * CC32XX are defined in PowerCC32XX.h. - * - * @param resourceId resource id - * - * @return Power_SOK on success, - * Power_EINVALIDINPUT if the reseourceId is invalid. - * - */ - int_fast16_t PowerCC32XX_reset(uint_fast16_t resourceId); - -/* \cond */ -#define Power_getPerformanceLevel(void) 0 -#define Power_setPerformanceLevel(level) Power_EFAIL -/* \endcond */ - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_power_PowerCC32XX__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/pwm/PWMTimerCC32XX.c b/ext/hal/ti/simplelink/source/ti/drivers/pwm/PWMTimerCC32XX.c deleted file mode 100644 index 66fe2392113..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/pwm/PWMTimerCC32XX.c +++ /dev/null @@ -1,823 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) -#define PAD_RESET_STATE 0xC61 - -/*! - * @brief If the PWM period is lower than this value, setDutyAndPeriod - * will briefly disable the PWM channel to set the new values. - * - * This is to prevent the case where the period, but not the duty, is - * applied before the timeout and the next cycle is in an undetermined state. - */ -#define PWM_PERIOD_FOR_GLITCH_PROTECTION 0xF - -void PWMTimerCC32XX_close(PWM_Handle handle); -int_fast16_t PWMTimerCC32XX_control(PWM_Handle handle, uint_fast16_t cmd, - void *arg); -void PWMTimerCC32XX_init(PWM_Handle handle); -PWM_Handle PWMTimerCC32XX_open(PWM_Handle handle, PWM_Params *params); -int_fast16_t PWMTimerCC32XX_setDuty(PWM_Handle handle, uint32_t dutyValue); -int_fast16_t PWMTimerCC32XX_setPeriod(PWM_Handle handle, uint32_t periodValue); -int_fast16_t PWMTimerCC32XX_setDutyAndPeriod(PWM_Handle handle, uint32_t dutyValue, uint32_t periodValue); -void PWMTimerCC32XX_start(PWM_Handle handle); -void PWMTimerCC32XX_stop(PWM_Handle handle); - -/* PWM function table for PWMTimerCC32XX implementation */ -const PWM_FxnTable PWMTimerCC32XX_fxnTable = { - PWMTimerCC32XX_close, - PWMTimerCC32XX_control, - PWMTimerCC32XX_init, - PWMTimerCC32XX_open, - PWMTimerCC32XX_setDuty, - PWMTimerCC32XX_setPeriod, - PWMTimerCC32XX_setDutyAndPeriod, - PWMTimerCC32XX_start, - PWMTimerCC32XX_stop -}; - -/* - * Internal value to notify an error has occurred while calculating a duty - * or period. - */ -static const uint32_t PWM_INVALID_VALUE = (~0); - -/* - * GPT peripheral load & match registers are 16 bits wide. Max value which - * can be set is 65535. - */ -static const uint16_t PWM_MAX_MATCH_REG_VALUE = (~0); - -/* - * GPT peripherals have 24 bit resolution. The max period value which be - * set is 16777215. - */ -static const uint32_t PWM_MAX_PERIOD_COUNT = (0xFFFFFF); - -/* - * The following fields are used by CC32XX driverlib APIs and therefore - * must be populated by driverlib macro definitions. For CC32XX driverlib - * these definitions are found in: - * - inc/hw_memmap.h - * - driverlib/gpio.h - * - driverlib/pin.h - * - driverlib/timer.h - */ -static const uint32_t timerBaseAddresses[4] = { - TIMERA0_BASE, - TIMERA1_BASE, - TIMERA2_BASE, - TIMERA3_BASE, -}; - -static const uint32_t timerHalves[2] = { - TIMER_A, - TIMER_B, -}; - -#define NUMGPIOPORTS 4 -static const uint32_t gpioBaseAddresses[NUMGPIOPORTS] = { - GPIOA0_BASE, - GPIOA1_BASE, - GPIOA2_BASE, - GPIOA3_BASE, -}; - -#define NUMGPIOPINS 8 -static const uint32_t gpioPinIndexes[NUMGPIOPINS] = { - GPIO_PIN_0, - GPIO_PIN_1, - GPIO_PIN_2, - GPIO_PIN_3, - GPIO_PIN_4, - GPIO_PIN_5, - GPIO_PIN_6, - GPIO_PIN_7, -}; - -#define PinConfigTimerPort(config) (((config) >> 28) & 0xF) -#define PinConfigTimerHalf(config) (((config) >> 24) & 0xF) -#define PinConfigGPIOPort(config) (((config) >> 20) & 0xF) -#define PinConfigGPIOPinIndex(config) (((config) >> 16) & 0xF) -#define PinConfigPinMode(config) (((config) >> 8) & 0xF) -#define PinConfigPin(config) (((config) >> 0) & 0x3F) - -/* - * ======== getDutyCounts ======== - */ -static uint32_t getDutyCounts(PWM_Duty_Units dutyUnits, uint32_t dutyValue, - uint32_t periodCounts) -{ - uint32_t duty = 0; - ClockP_FreqHz freq; - - ClockP_getCpuFreq(&freq); - - switch (dutyUnits) { - case PWM_DUTY_COUNTS: - duty = dutyValue; - break; - - case PWM_DUTY_FRACTION: - duty = (((uint64_t) dutyValue) * ((uint64_t) periodCounts)) / - PWM_DUTY_FRACTION_MAX; - break; - - case PWM_DUTY_US: - duty = (dutyValue != 0) ? (dutyValue * (freq.lo/1000000)) - 1 : 0; - break; - - default: - /* Unsupported duty units return an invalid duty */ - duty = PWM_INVALID_VALUE; - } - - return (duty); -} - -/* - * ======== getPeriodCounts ======== - */ -static uint32_t getPeriodCounts(PWM_Period_Units periodUnits, - uint32_t periodValue) -{ - uint32_t period = 0; - ClockP_FreqHz freq; - - ClockP_getCpuFreq(&freq); - - switch (periodUnits) { - case PWM_PERIOD_COUNTS: - period = periodValue; - break; - - case PWM_PERIOD_HZ: - if (periodValue && periodValue <= freq.lo) { - period = (freq.lo / periodValue) - 1; - } - break; - - case PWM_PERIOD_US: - period = (periodValue * (freq.lo/1000000)) - 1; - break; - - default: - /* Unsupported period units return an invalid period */ - period = PWM_INVALID_VALUE; - } - - return (period); -} - -/* - * ======== getPowerMgrId ======== - */ -static uint_fast16_t getPowerMgrId(uint32_t baseAddr) -{ - switch (baseAddr) { - case GPIOA0_BASE: - return (PowerCC32XX_PERIPH_GPIOA0); - case GPIOA1_BASE: - return (PowerCC32XX_PERIPH_GPIOA1); - case GPIOA2_BASE: - return (PowerCC32XX_PERIPH_GPIOA2); - case GPIOA3_BASE: - return (PowerCC32XX_PERIPH_GPIOA3); - case GPIOA4_BASE: - return (PowerCC32XX_PERIPH_GPIOA4); - default: - /* Should never get here */ - return ((unsigned int) -1); - } -} - -/* - * ======== initHw ======== - */ -static int initHw(PWM_Handle handle, uint32_t period, uint32_t duty) -{ - uintptr_t key; - int32_t result; - uint32_t timerConfigVal; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - uint32_t timerBaseAddr; - uint16_t halfTimer; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; - - key = HwiP_disable(); - - MAP_TimerDisable(timerBaseAddr, halfTimer); - - /* - * The CC32XX SDK TimerConfigure API halts both timers when it is - * used to configure a single half timer. The code below performs - * the register operations necessary to configure each half timer - * individually. - */ - /* Enable CCP to IO path */ - HWREG(APPS_CONFIG_BASE + APPS_CONFIG_O_GPT_TRIG_SEL) = 0xFF; - - /* Split the timer and configure it as a PWM */ - timerConfigVal = ((halfTimer & (TIMER_CFG_A_PWM | TIMER_CFG_B_PWM)) | - TIMER_CFG_SPLIT_PAIR); - HWREG(timerBaseAddr + TIMER_O_CFG) |= (timerConfigVal >> 24); - if (halfTimer & TIMER_A) { - HWREG(timerBaseAddr + TIMER_O_TAMR) = timerConfigVal & 255; - } - else { - HWREG(timerBaseAddr + TIMER_O_TBMR) = (timerConfigVal >> 8) & 255; - } - - /* Set the peripheral output to active-high */ - MAP_TimerControlLevel(timerBaseAddr, halfTimer, true); - - HwiP_restore(key); - - result = PWMTimerCC32XX_setPeriod(handle, period); - if (result != PWM_STATUS_SUCCESS) { - return (result); - } - - result = PWMTimerCC32XX_setDuty(handle, duty); - if (result != PWM_STATUS_SUCCESS) { - return (result); - } - - return (PWM_STATUS_SUCCESS); -} - -/* - * ======== postNotifyFxn ======== - * Called by Power module when waking up from LPDS. - */ -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - PWM_Handle handle = (PWM_Handle) clientArg; - PWMTimerCC32XX_Object *object = handle->object; - - initHw(handle, object->period, object->duty); - - return (Power_NOTIFYDONE); -} - -/* - * ======== PWMTimerCC32XX_close ======== - * @pre Function assumes that the handle is not NULL - */ -void PWMTimerCC32XX_close(PWM_Handle handle) -{ - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - TimerCC32XX_SubTimer subTimer; - uint32_t timerBaseAddr; - uint32_t gpioBaseAddr; - uint32_t padRegister; - uintptr_t key; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - - subTimer = (TimerCC32XX_SubTimer) (TimerCC32XX_timer16A + - PinConfigTimerHalf(hwAttrs->pwmPin)); - - /* - * Some PWM pins may not have GPIO capability; in these cases gpioBaseAddr - * is set to 0 & the GPIO power dependencies are not released. - */ - gpioBaseAddr = (PinConfigGPIOPort(hwAttrs->pwmPin) >= NUMGPIOPORTS) ? - 0 : gpioBaseAddresses[PinConfigGPIOPort(hwAttrs->pwmPin)]; - - PWMTimerCC32XX_stop(handle); - - key = HwiP_disable(); - - TimerCC32XX_freeTimerResource(timerBaseAddr, subTimer); - - /* Remove GPIO power dependency if pin is GPIO capable */ - if (gpioBaseAddr) { - Power_releaseDependency(getPowerMgrId(gpioBaseAddr)); - } - - Power_unregisterNotify(&object->postNotify); - - padRegister = (PinToPadGet((hwAttrs->pwmPin) & 0x3f)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - - object->isOpen = false; - - HwiP_restore(key); - - DebugP_log1("PWM:(%p) is closed", (uintptr_t) handle); -} - -/* - * ======== PWMTimerCC32XX_control ======== - * @pre Function assumes that the handle is not NULL - */ -int_fast16_t PWMTimerCC32XX_control(PWM_Handle handle, uint_fast16_t cmd, - void *arg) -{ - /* No implementation yet */ - return (PWM_STATUS_UNDEFINEDCMD); -} - -/* - * ======== PWMTimerCC32XX_init ======== - * @pre Function assumes that the handle is not NULL - */ -void PWMTimerCC32XX_init(PWM_Handle handle) -{ -} - -/* - * ======== PWMTimerCC32XX_open ======== - * @pre Function assumes that the handle is not NULL - */ -PWM_Handle PWMTimerCC32XX_open(PWM_Handle handle, PWM_Params *params) -{ - uintptr_t key; - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - TimerCC32XX_SubTimer subTimer; - uint32_t timerBaseAddr; - uint32_t gpioBaseAddr; - uint16_t pin; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - pin = PinConfigPin(hwAttrs->pwmPin); - - subTimer = (TimerCC32XX_SubTimer) (TimerCC32XX_timer16A + - PinConfigTimerHalf(hwAttrs->pwmPin)); - - key = HwiP_disable(); - - if (object->isOpen) { - HwiP_restore(key); - - DebugP_log1("PWM:(%p) already opened.", (uintptr_t) handle); - - return (NULL); - } - - if (!TimerCC32XX_allocateTimerResource(timerBaseAddr, subTimer)) { - HwiP_restore(key); - - DebugP_log1("Timer: 0x%X unavailable.", timerBaseAddr); - - return (NULL); - } - - object->isOpen = true; - - HwiP_restore(key); - - /* - * Some PWM pins may not have GPIO capability; in these cases gpioBaseAddr - * is set to 0 & the GPIO power dependencies are not set. - */ - gpioBaseAddr = (PinConfigGPIOPort(hwAttrs->pwmPin) >= NUMGPIOPORTS) ? - 0 : gpioBaseAddresses[PinConfigGPIOPort(hwAttrs->pwmPin)]; - - /* Set GPIO power dependency if pin is GPIO capable */ - if (gpioBaseAddr) { - /* Check GPIO power resource Id */ - if (getPowerMgrId(gpioBaseAddr) == ((unsigned int) -1)) { - TimerCC32XX_freeTimerResource(timerBaseAddr, subTimer); - - object->isOpen = false; - - DebugP_log1("PWM:(%p) Failed to determine GPIO power resource ID.", - (uintptr_t) handle); - - return (NULL); - } - - /* Register power dependency for GPIO port */ - Power_setDependency(getPowerMgrId(gpioBaseAddr)); - } - - Power_registerNotify(&object->postNotify, PowerCC32XX_AWAKE_LPDS, - postNotifyFxn, (uintptr_t) handle); - - /* - * Set PWM duty to initial value (not 0) - required when inverting - * output polarity to generate a duty equal to 0 or period. See comments in - * PWMTimerCC32XX_setDuty for more information. - */ - object->duty = 0; - object->period = 0; - object->dutyUnits = params->dutyUnits; - object->idleLevel = params->idleLevel; - object->periodUnits = params->periodUnits; - object->pwmStarted = 0; - - /* Initialize the peripheral & set the period & duty */ - if (initHw(handle, params->periodValue, params->dutyValue) != - PWM_STATUS_SUCCESS) { - PWMTimerCC32XX_close(handle); - - DebugP_log1("PWM:(%p) Failed set initial PWM configuration.", - (uintptr_t) handle); - - return (NULL); - } - - /* Configure the Power_pinParkState based on idleLevel param */ - PowerCC32XX_setParkState((PowerCC32XX_Pin) pin, - (object->idleLevel == PWM_IDLE_HIGH)); - - /* Called to set the initial idleLevel */ - PWMTimerCC32XX_stop(handle); - - DebugP_log3("PWM:(%p) opened; period set to: %d; duty set to: %d", - (uintptr_t) handle, params->periodValue, params->dutyValue); - - return (handle); -} - -/* - * ======== PWMTimerCC32XX_setDuty ======== - * @pre Function assumes that handle is not NULL - */ -int_fast16_t PWMTimerCC32XX_setDuty(PWM_Handle handle, uint32_t dutyValue) -{ - uintptr_t key; - uint32_t duty; - uint32_t period; - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - uint32_t timerBaseAddr; - uint16_t halfTimer; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; - - key = HwiP_disable(); - - period = object->period; - duty = getDutyCounts(object->dutyUnits, dutyValue, period); - - if (duty == PWM_INVALID_VALUE) { - HwiP_restore(key); - - DebugP_log1("PWM:(%p) duty units could not be determined.", - (uintptr_t) handle); - - return (PWM_STATUS_ERROR); - } - - if (duty > period) { - HwiP_restore(key); - - DebugP_log1("PWM:(%p) duty is out of range.", (uintptr_t) handle); - - return (PWM_STATUS_INVALID_DUTY); - } - - /* - * The timer peripheral cannot generate a duty equal to the period when - * the timer is counting down. In these cases the PWM duty is set to the - * period value (output remains low) and output polarity is inverted. - * Additionally, if the output is changed from the period the PWM output - * polarity must be inverted again. - * - * The code below uses the previous duty (object->duty) and the new duty to - * determine if the polarity should be inverted. - * For more details refer to the device specific datasheet and the following - * E2E post: - * http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/354826.aspx - */ - if (((duty == period) && (object->duty != period)) || - ((duty != period) && (object->duty == period))) { - HWREG(timerBaseAddr + TIMER_O_CTL) ^= - (halfTimer & (TIMER_CTL_TAPWML | TIMER_CTL_TBPWML)); - } - - /* - * Set & store the new duty. IMPORTANT: this must be saved after output - * inversion is determined and before the duty = 0 corner case. - */ - object->duty = duty; - - /* - * Special corner case, if duty is 0 we set it to the period without - * inverting output - */ - if (duty == 0) { - duty = period; - } - - MAP_TimerPrescaleMatchSet(timerBaseAddr, halfTimer, - duty / PWM_MAX_MATCH_REG_VALUE); - MAP_TimerMatchSet(timerBaseAddr, halfTimer, - duty % PWM_MAX_MATCH_REG_VALUE); - - HwiP_restore(key); - - DebugP_log2("PWM:(%p) duty set to: %d", (uintptr_t) handle, dutyValue); - - return (PWM_STATUS_SUCCESS); -} - -/* - * ======== PWMTimerCC32XX_setPeriod ======== - * @pre Function assumes that handle is not NULL - */ -int_fast16_t PWMTimerCC32XX_setPeriod(PWM_Handle handle, uint32_t periodValue) -{ - uintptr_t key; - uint32_t duty; - uint32_t period; - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - uint32_t timerBaseAddr; - uint16_t halfTimer; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; - - key = HwiP_disable(); - - duty = object->duty; - period = getPeriodCounts(object->periodUnits, periodValue); - - if (period == PWM_INVALID_VALUE) { - HwiP_restore(key); - - DebugP_log1("PWM:(%p) period units could not be determined.", - (uintptr_t) handle); - - return (PWM_STATUS_ERROR); - } - - if ((period == 0) || (period <= duty) || (period > PWM_MAX_PERIOD_COUNT)) { - HwiP_restore(key); - - DebugP_log1("PWM:(%p) period is out of range.", (uintptr_t) handle); - - return (PWM_STATUS_INVALID_PERIOD); - } - - /* Set the new period */ - object->period = period; - MAP_TimerPrescaleSet(timerBaseAddr, halfTimer, - period / PWM_MAX_MATCH_REG_VALUE); - MAP_TimerLoadSet(timerBaseAddr, halfTimer, - period % PWM_MAX_MATCH_REG_VALUE); - - HwiP_restore(key); - - DebugP_log2("PWM:(%p) period set to: %d", (uintptr_t) handle, periodValue); - - return (PWM_STATUS_SUCCESS); -} - -/* - * ======== PWMTimerCC32XX_setDutyAndPeriod ======== - * @pre Function assumes that handle is not NULL - */ -int_fast16_t PWMTimerCC32XX_setDutyAndPeriod(PWM_Handle handle, uint32_t dutyValue, uint32_t periodValue) -{ - uintptr_t key; - uint32_t duty; - uint32_t period; - bool stopped = false; - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - uint32_t oldPeriod; - uint32_t timerBaseAddr; - uint16_t halfTimer; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; - - key = HwiP_disable(); - - oldPeriod = getPeriodCounts(object->periodUnits, object->period); - period = getPeriodCounts(object->periodUnits, periodValue); - duty = getDutyCounts(object->dutyUnits, dutyValue, period); - - if (period == PWM_INVALID_VALUE) { - HwiP_restore(key); - - DebugP_log1("PWM:(%p) period units could not be determined.", (uintptr_t) handle); - - return (PWM_STATUS_ERROR); - } - - if ((period == 0) || (period < duty) || (period > PWM_MAX_PERIOD_COUNT)) { - HwiP_restore(key); - - DebugP_log1("PWM:(%p) period is out of range.", (uintptr_t) handle); - - return (PWM_STATUS_INVALID_PERIOD); - } - - /* Set the new period */ - object->period = period; - - /* - * The timer peripheral cannot generate a duty equal to the period when - * the timer is counting down. In these cases the PWM duty is set to the - * period value (output remains low) and output polarity is inverted. - * Additionally, if the output is changed from the period the PWM output - * polarity must be inverted again. - * - * The code below uses the previous duty (object->duty) and the new duty to - * determine if the polarity should be inverted. - * For more details refer to the device specific datasheet and the following - * E2E post: - * http://e2e.ti.com/support/microcontrollers/tiva_arm/f/908/t/354826.aspx - */ - if (((duty == period) && (object->duty != period)) || - ((duty != period) && (object->duty == period))) { - HWREG(timerBaseAddr + TIMER_O_CTL) ^= - (halfTimer & (TIMER_CTL_TAPWML | TIMER_CTL_TBPWML)); - } - - /* - * Set & store the new duty. IMPORTANT: this must be saved after output - * inversion is determined and before the duty = 0 corner case. - */ - object->duty = duty; - - /* - * Special corner case, if duty is 0 we set it to the period without - * inverting output - */ - if (duty == 0) { - duty = period; - } - - if (object->pwmStarted && oldPeriod <= PWM_PERIOD_FOR_GLITCH_PROTECTION) { - stopped = true; - MAP_TimerDisable(timerBaseAddr, halfTimer); - } - - MAP_TimerPrescaleSet(timerBaseAddr, halfTimer, period / PWM_MAX_MATCH_REG_VALUE); - MAP_TimerPrescaleMatchSet(timerBaseAddr, halfTimer, duty / PWM_MAX_MATCH_REG_VALUE); - - MAP_TimerLoadSet(timerBaseAddr, halfTimer, period % PWM_MAX_MATCH_REG_VALUE); - MAP_TimerMatchSet(timerBaseAddr, halfTimer, duty % PWM_MAX_MATCH_REG_VALUE); - - if (stopped) { - MAP_TimerEnable(timerBaseAddr, halfTimer); - } - - HwiP_restore(key); - return (PWM_STATUS_SUCCESS); -} - -/* - * ======== PWMTimerCC32XX_start ======== - * @pre Function assumes that handle is not NULL - */ -void PWMTimerCC32XX_start(PWM_Handle handle) -{ - uintptr_t key; - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - uint32_t timerBaseAddr; - uint16_t halfTimer; - uint16_t pin; - uint16_t mode; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; - pin = PinConfigPin(hwAttrs->pwmPin); - mode = PinConfigPinMode(hwAttrs->pwmPin); - - key = HwiP_disable(); - - /* - * GP timer ticks only in Active mode. Cannot be used in HIB or LPDS. - * Set constraint to disallow LPDS. - */ - if (!(object->pwmStarted)) { - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - object->pwmStarted = true; - } - - /* Start the timer & set pinmux to PWM mode */ - MAP_TimerEnable(timerBaseAddr, halfTimer); - MAP_PinTypeTimer((unsigned long)pin, (unsigned long)mode); - - HwiP_restore(key); -} - -/* - * ======== PWMTimerCC32XX_stop ======== - * @pre Function assumes that handle is not NULL - */ -void PWMTimerCC32XX_stop(PWM_Handle handle) -{ - uintptr_t key; - uint8_t output; - PWMTimerCC32XX_Object *object = handle->object; - PWMTimerCC32XX_HWAttrsV2 const *hwAttrs = handle->hwAttrs; - uint32_t timerBaseAddr; - uint16_t halfTimer; - uint32_t gpioBaseAddr; - uint8_t gpioPinIndex; - uint16_t pin; - - timerBaseAddr = timerBaseAddresses[PinConfigTimerPort(hwAttrs->pwmPin)]; - halfTimer = timerHalves[PinConfigTimerHalf(hwAttrs->pwmPin)]; - pin = PinConfigPin(hwAttrs->pwmPin); - - /* - * Some PWM pins may not have GPIO capability; in these cases gpioBaseAddr - * is set to 0 & the GPIO power dependencies are not set. - */ - gpioBaseAddr = (PinConfigGPIOPort(hwAttrs->pwmPin) >= NUMGPIOPORTS) ? - 0 : gpioBaseAddresses[PinConfigGPIOPort(hwAttrs->pwmPin)]; - gpioPinIndex = (PinConfigGPIOPinIndex(hwAttrs->pwmPin) >= NUMGPIOPINS) ? - 0 : gpioPinIndexes[PinConfigGPIOPinIndex(hwAttrs->pwmPin)]; - - key = HwiP_disable(); - - /* Remove the dependency to allow LPDS */ - if (object->pwmStarted) { - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - object->pwmStarted = false; - } - - /* Set pin as GPIO with IdleLevel value & stop the timer */ - output = (object->idleLevel) ? gpioPinIndex : 0; - MAP_PinTypeGPIO((unsigned long)pin, PIN_MODE_0, false); - - /* Only configure the pin as GPIO if the pin is GPIO capable */ - if (gpioBaseAddr) { - MAP_GPIODirModeSet(gpioBaseAddr, gpioPinIndex, GPIO_DIR_MODE_OUT); - MAP_GPIOPinWrite(gpioBaseAddr, gpioPinIndex, output); - } - - /* Stop the Timer */ - MAP_TimerDisable(timerBaseAddr, halfTimer); - HwiP_restore(key); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/pwm/PWMTimerCC32XX.h b/ext/hal/ti/simplelink/source/ti/drivers/pwm/PWMTimerCC32XX.h deleted file mode 100644 index 40c7fd1a860..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/pwm/PWMTimerCC32XX.h +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*! ============================================================================ - * @file PWMTimerCC32XX.h - * - * @brief PWM driver implementation using CC32XX General Purpose Timers. - * - * The PWM header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref PWM.h for a complete description of the PWM - * driver APIs provided and examples of their use. - * - * ## Overview # - * This driver configures a CC32XX General Purpose Timer (GPT) in PWM mode. - * When in PWM mode, each GPT is divided into 2 PWM outputs. This driver - * manages each output as an independent PWM instance. The timer is - * automatically configured in count-down mode using the system clock as - * the source. - * - * The timers operate at the system clock frequency (80 MHz). So each timer - * tick is 12.5 ns. The period and duty registers are 16 bits wide; thus - * 8-bit prescalars are used to extend period and duty registers. The - * maximum value supported is 16777215 timer counts ((2^24) - 1) or - * 209715 microseconds. Updates to a PWM's period or duty will occur - * instantaneously (GPT peripherals do not have shadow registers). - * - * When stopped, the driver will configure the pin in GPIO mode & set the - * output to the PWM_IdleLevel specified in the params used during open. Users - * need be aware that while PIN 19 can be used for PWM it is not GPIO capable, - * so it cannot be set to the PWM_IdleLevel. Output voltage will be PWM output - * at the moment it is stopped. - * - * Finally, when this driver is opened, it automatically changes the - * PWM pin's parking configuration (used when entering low power modes) to - * correspond with the PWM_IDLE_LEVEL set in the PWM_params. However, this - * setting is not reverted once the driver is closed, it is the users - * responsibility to change the parking configuration if necessary. - * - * ### CC32xx PWM Driver Configuration # - * - * In order to use the PWM APIs, the application is required - * to define 4 configuration items in the application Board.c file: - * - * 1. An array of PWMTimerCC32XX_Object elements, which will be used by - * by the driver to maintain instance state. - * Below is an example PWMTimerCC32XX_Object array appropriate for the CC3220SF LaunchPad - * board: - * @code - * #include - * #include - * - * PWMTimerCC32XX_Object pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWMCOUNT]; - * @endcode - * - * 2. An array of PWMTimerCC32XX_HWAttrsV2 elements that defines which - * pin will be used by the corresponding PWM instance - * (see @ref pwmPinIdentifiersCC32XX). - * Below is an example PWMTimerCC32XX_HWAttrsV2 array appropriate for the CC3220SF LaunchPad - * board: - * @code - * const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWMCOUNT] = { - * { - * .pwmPin = PWMTimerCC32XX_PIN_01 - * }, - * { - * .pwmPin = PWMTimerCC32XX_PIN_02 - * } - * }; - * @endcode - * - * 3. An array of @ref PWM_Config elements, one for each PWM instance. Each - * element of this array identifies the device-specific API function table, - * the device specific PWM object instance, and the device specific Hardware - * Attributes to be used for each PWM channel. - * Below is an example @ref PWM_Config array appropriate for the CC3220SF LaunchPad - * board: - * @code - * const PWM_Config PWM_config[CC3220SF_LAUNCHXL_PWMCOUNT] = { - * { - * .fxnTablePtr = &PWMTimerCC32XX_fxnTable, - * .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM6], - * .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM6] - * }, - * { - * .fxnTablePtr = &PWMTimerCC32XX_fxnTable, - * .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM7], - * .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM7] - * } - * }; - * @endcode - * - * 4. A global variable, PWM_count, that informs the driver how many PWM - * instances are defined: - * @code - * const uint_least8_t PWM_count = CC3220SF_LAUNCHXL_PWMCOUNT; - * @endcode - * - * ### Power Management # - * The TI-RTOS power management framework will try to put the device into the most - * power efficient mode whenever possible. Please see the technical reference - * manual for further details on each power mode. - * - * The PWMTimerCC32XX driver explicitly sets a power constraint when the - * PWM is running to prevent LPDS. - * The following statements are valid: - * - After PWM_open(): Clocks are enabled to the timer resource and the - * configured pwmPin. The device is still allowed - * to enter LPDS. - * - After PWM_start(): LPDS is disabled when PWM is running. - * - After PWM_stop(): Conditions are equal as for after PWM_open - * - After PWM_close(): The underlying GPTimer is turned off, and the clocks - * to the timer and pin are disabled.. - * - * ============================================================================= - */ - -#ifndef ti_driver_pwm_PWMTimerCC32XX__include -#define ti_driver_pwm_PWMTimerCC32XX__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/*! \cond */ -/* - * PWMTimer port/pin defines for pin configuration. - * - * The timer id (0, 1, 2, or 3) is stored in bits 31 - 28 - * The timer half (0 = A, 1 = B) is stored in bits 27 - 24 - * The GPIO port (0, 1, 2, or 3) is stored in bits 23 - 20 - * The GPIO pin index within the port (0 - 7) is stored in bits 19 - 16 - * The pin mode is stored in bits 11 - 8 - * The pin number is stored in bits 7 - 0 - * - * - * 31 - 28 27 - 24 23 - 20 19 - 16 11 - 8 7 - 0 - * ----------------------------------------------------------------------- - * | Timer id | Timer half | GPIO port | GPIO pin index | pin mode | pin | - * ----------------------------------------------------------------------- - * - * The CC32XX has fixed GPIO assignments and pin modes for a given pin. - * A PWM pin mode for a given pin has a fixed timer/timer-half. - */ -#define PWMTimerCC32XX_T0A (0x00 << 24) -#define PWMTimerCC32XX_T0B (0x01 << 24) -#define PWMTimerCC32XX_T1A (0x10 << 24) -#define PWMTimerCC32XX_T1B (0x11 << 24) -#define PWMTimerCC32XX_T2A (0x20 << 24) -#define PWMTimerCC32XX_T2B (0x21 << 24) -#define PWMTimerCC32XX_T3A (0x30 << 24) -#define PWMTimerCC32XX_T3B (0x31 << 24) - -#define PWMTimerCC32XX_GPIO9 (0x11 << 16) -#define PWMTimerCC32XX_GPIO10 (0x12 << 16) -#define PWMTimerCC32XX_GPIO11 (0x13 << 16) -#define PWMTimerCC32XX_GPIO24 (0x30 << 16) -#define PWMTimerCC32XX_GPIO25 (0x31 << 16) - -#define PWMTimerCC32XX_GPIONONE (0xFF << 16) -/*! \endcond */ - -/*! - * \defgroup pwmPinIdentifiersCC32XX PWMTimerCC32XX_HWAttrs 'pwmPin' field options - * @{ - */ -/*! - * @name PIN 01, GPIO10, uses Timer3A for PWM. - * @{ - */ -#define PWMTimerCC32XX_PIN_01 (PWMTimerCC32XX_T3A | PWMTimerCC32XX_GPIO10 | 0x0300) /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 02, GPIO11, uses Timer3B for PWM. - * @{ - */ -#define PWMTimerCC32XX_PIN_02 (PWMTimerCC32XX_T3B | PWMTimerCC32XX_GPIO11 | 0x0301) /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 17, GPIO24, uses Timer0A for PWM. - * @{ - */ -#define PWMTimerCC32XX_PIN_17 (PWMTimerCC32XX_T0A | PWMTimerCC32XX_GPIO24 | 0x0510) /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 19, uses Timer1B for PWM. - * @{ - */ -#define PWMTimerCC32XX_PIN_19 (PWMTimerCC32XX_T1B | PWMTimerCC32XX_GPIONONE | 0x0812) /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 21, GPIO25, uses Timer1A for PWM. - * @{ - */ -#define PWMTimerCC32XX_PIN_21 (PWMTimerCC32XX_T1A | PWMTimerCC32XX_GPIO25 | 0x0914) /*!< @hideinitializer */ -/*! @} */ -/*! - * @name PIN 64, GPIO9, uses Timer2B for PWM. - * @{ - */ -#define PWMTimerCC32XX_PIN_64 (PWMTimerCC32XX_T2B | PWMTimerCC32XX_GPIO9 | 0x033F) /*!< @hideinitializer */ -/*! @} */ -/*! @} */ - -/** - * @addtogroup PWM_STATUS - * PWMTimerCC32XX_STATUS_* macros are command codes only defined in the - * PWMTimerCC32XX.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add PWMTimerCC32XX_STATUS_* macros here */ - -/** @}*/ - -/** - * @addtogroup PWM_CMD - * PWMTimerCC32XX_CMD_* macros are command codes only defined in the - * PWMTimerCC32XX.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add PWMTimerCC32XX_CMD_* macros here */ - -/** @}*/ - -/* PWM function table pointer */ -extern const PWM_FxnTable PWMTimerCC32XX_fxnTable; - -/*! - * @brief PWMTimerCC32XX Hardware attributes - * - * The 'pwmPin' field identifies which physical pin to use for a - * particular PWM channel as well as the corresponding Timer resource used - * to source the PWM signal. The encoded pin identifier macros for - * initializing the 'pwmPin' field must be selected from the - * @ref pwmPinIdentifiersCC32XX macros. - * - * A sample structure is shown below: - * @code - * const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC32XXHWAttrs[] = { - * { - * .pwmPin = PWMTimerCC32XX_PIN_01, - * }, - * { - * .pwmPin = PWMTimerCC32XX_PIN_02, - * } - * }; - * @endcode - */ -typedef struct PWMTimerCC32XX_HWAttrsV2 { - uint32_t pwmPin; /*!< Pin to output PWM signal on - (see @ref pwmPinIdentifiersCC32XX) */ -} PWMTimerCC32XX_HWAttrsV2; - -/*! - * @brief PWMTimerCC32XX Object - * - * The application must not access any member variables of this structure! - */ -typedef struct PWMTimerCC32XX_Object { - Power_NotifyObj postNotify; - uint32_t duty; /* Current duty cycle in Duty_Unites */ - uint32_t period; /* Current period PERIOD_Units */ - PWM_Duty_Units dutyUnits; /* Current duty cycle unit */ - PWM_Period_Units periodUnits; /* Current period unit */ - PWM_IdleLevel idleLevel; /* PWM idle level when stopped / not started */ - bool pwmStarted; /* Used to gate Power_set/releaseConstraint() calls */ - bool isOpen; /* open flag used to check if PWM is opened */ -} PWMTimerCC32XX_Object; - -#ifdef __cplusplus -} -#endif - -#endif /* ti_driver_pwm_PWMTimerCC32XX__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/sd/SDHostCC32XX.c b/ext/hal/ti/simplelink/source/ti/drivers/sd/SDHostCC32XX.c deleted file mode 100644 index 241bc3fc525..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/sd/SDHostCC32XX.c +++ /dev/null @@ -1,1132 +0,0 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif - -#include -#include -#include -#include -#include -#include -#include - -/* Driverlib header files */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PinConfigPinMode(config) (((config) >> 8) & 0xF) -#define PinConfigPin(config) (((config) >> 0) & 0x3F) - -#define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) -#define PAD_RESET_STATE 0xC61 - -/* Definitions for SDC driverlib commands */ -#define CMD_GO_IDLE_STATE (SDHOST_CMD_0) -#define CMD_SEND_OP_COND (SDHOST_CMD_1 | SDHOST_RESP_LEN_48) -#define CMD_ALL_SEND_CID (SDHOST_CMD_2 | SDHOST_RESP_LEN_136) -#define CMD_SEND_REL_ADDR (SDHOST_CMD_3 | SDHOST_RESP_LEN_48) -#define CMD_SELECT_CARD (SDHOST_CMD_7 | SDHOST_RESP_LEN_48B) -#define CMD_DESELECT_CARD (SDHOST_CMD_7) -#define CMD_SEND_IF_COND (SDHOST_CMD_8 | SDHOST_RESP_LEN_48) -#define CMD_SEND_CSD (SDHOST_CMD_9 | SDHOST_RESP_LEN_136) -#define CMD_STOP_TRANS (SDHOST_CMD_12 | SDHOST_RESP_LEN_48B) -#define CMD_READ_SINGLE_BLK (SDHOST_CMD_17 | SDHOST_RD_CMD | SDHOST_RESP_LEN_48) -#define CMD_READ_MULTI_BLK (SDHOST_CMD_18 | SDHOST_RD_CMD | \ - SDHOST_RESP_LEN_48 | SDHOST_MULTI_BLK) -#define CMD_SET_BLK_CNT (SDHOST_CMD_23 | SDHOST_RESP_LEN_48) -#define CMD_WRITE_SINGLE_BLK (SDHOST_CMD_24 | SDHOST_WR_CMD | SDHOST_RESP_LEN_48) -#define CMD_WRITE_MULTI_BLK (SDHOST_CMD_25 | SDHOST_WR_CMD | \ - SDHOST_RESP_LEN_48 | SDHOST_MULTI_BLK) -#define CMD_SD_SEND_OP_COND (SDHOST_CMD_41 | SDHOST_RESP_LEN_48) -#define CMD_APP_CMD (SDHOST_CMD_55 | SDHOST_RESP_LEN_48) - -/* Group of all possible SD command and data error flags */ -#define CMDERROR (SDHOST_INT_CTO | SDHOST_INT_CEB) - -#define DATAERROR (SDHOST_INT_DTO | SDHOST_INT_DCRC | \ - SDHOST_INT_DEB | SDHOST_INT_CERR | \ - SDHOST_INT_BADA) - -#define SECTORSIZE (512) - -/* Voltage window (VDD) used on this device (3.3-3.6 V) */ -#define VOLTAGEWINDOW (0x00E00000) - -/* Bit set to indicate the host controller has high capacity support */ -#define HIGHCAPSUPPORT (0x40000000) - -/* Voltage supplied 2.7-3.6V */ -#define SUPPLYVOLTAGE (0x00000100) - -/* Checksum to validate SD command responses */ -#define CHECKSUM (0xA5) - -/* Setup the UDMA controller to either read or write to the SDHost buffer */ -#define UDMAWRITE (0x01) - -#define UDMAREAD (0x00) - -/* Define used for commands that do not require an argument */ -#define NULLARG (0x00) - -/* SDHostCC32XX configuration - initialized in the board file */ -extern const SD_Config SD_config[]; - -/* SDHostCC32XX functions */ -void SDHostCC32XX_close(SD_Handle handle); -int_fast16_t SDHostCC32XX_control(SD_Handle handle, uint_fast16_t cmd, - void *arg); -uint_fast32_t SDHostCC32XX_getNumSectors(SD_Handle handle); -uint_fast32_t SDHostCC32XX_getSectorSize(SD_Handle handle); -int_fast16_t SDHostCC32XX_initialize(SD_Handle handle); -void SDHostCC32XX_init(SD_Handle handle); -SD_Handle SDHostCC32XX_open(SD_Handle handle, SD_Params *params); -int_fast16_t SDHostCC32XX_read(SD_Handle handle, void *buf, - int_fast32_t sector, uint_fast32_t secCount); -int_fast16_t SDHostCC32XX_write(SD_Handle handle, const void *buf, - int_fast32_t sector, uint_fast32_t secCount); - -/* Local Functions */ -static void configDMAChannel(SD_Handle handle, uint_fast32_t channelSel, - uint_fast32_t operation); -static int_fast32_t deSelectCard(SD_Handle handle); -static uint_fast32_t getPowerMgrId(uint_fast32_t baseAddr); -static void hwiIntFxn(uintptr_t handle); -static void initHw(SD_Handle handle); -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg); -static int_fast32_t send_cmd(SD_Handle handle, uint_fast32_t cmd, - uint_fast32_t arg); -static int_fast32_t selectCard(SD_Handle handle); - -/* SDHostCC32XX function table for SDSPICC32XX implementation */ -const SD_FxnTable sdHostCC32XX_fxnTable = { - SDHostCC32XX_close, - SDHostCC32XX_control, - SDHostCC32XX_getNumSectors, - SDHostCC32XX_getSectorSize, - SDHostCC32XX_init, - SDHostCC32XX_initialize, - SDHostCC32XX_open, - SDHostCC32XX_read, - SDHostCC32XX_write -}; - -/* - * ======== SDHostCC32XX_close ======== - */ -void SDHostCC32XX_close(SD_Handle handle) -{ - SDHostCC32XX_Object *object = handle->object; - SDHostCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uint32_t padRegister; - - if (object->cardType != SD_NOCARD) { - /* De-select the SD Card, move back to standby state */ - if (deSelectCard(handle) != SD_STATUS_SUCCESS) { - DebugP_log1("SDHost:(%p) Failed to de-select SD Card", - hwAttrs->baseAddr); - } - } - - /* Disable SD Host interrupts */ - MAP_SDHostIntDisable(hwAttrs->baseAddr, DATAERROR | CMDERROR); - - if (object->dmaHandle) { - UDMACC32XX_close(object->dmaHandle); - } - if (object->cmdSem) { - SemaphoreP_delete(object->cmdSem); - } - if (object->hwiHandle) { - HwiP_delete(object->hwiHandle); - } - - /* Remove Power driver settings */ - if (object->clkPin != (uint16_t)-1) { - PowerCC32XX_restoreParkState((PowerCC32XX_Pin)object->clkPin, - object->prevParkCLK); - object->clkPin = (uint16_t)-1; - } - Power_unregisterNotify(&object->postNotify); - Power_releaseDependency(object->powerMgrId); - - /* Restore pin pads to their reset states */ - padRegister = (PinToPadGet((hwAttrs->dataPin) & 0x3f)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - padRegister = (PinToPadGet((hwAttrs->cmdPin) & 0x3f)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - padRegister = (PinToPadGet((hwAttrs->clkPin) & 0x3f)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - - object->isOpen = false; - - DebugP_log1("SDHost:(%p) closed and released power dependency", - hwAttrs->baseAddr); -} - -/* - * ======== SDHostCC32XX_control ======== - * @pre Function assumes that the handle is not NULL. - */ -int_fast16_t SDHostCC32XX_control(SD_Handle handle, uint_fast32_t cmd, - void *arg) -{ - /* No implementation yet */ - return (SD_STATUS_UNDEFINEDCMD); -} - -/* - * ======== SDHostCC32XX_getNumSectors ======== - * Function to read the CSD register of the SD card on the drive specified - * by the SD_Handle and calculate the total card capacity in sectors. - */ -uint_fast32_t SDHostCC32XX_getNumSectors(SD_Handle handle) -{ - uint_fast32_t sectors = 0; - uint_fast32_t cSize; /* Device size */ - uint_fast32_t blockSize; /* Read block length */ - uint_fast32_t sizeMult; - uint_fast32_t resp[4]; - SDHostCC32XX_Object *object = handle->object; - SDHostCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_log1("SDHost:(%p) SDHostCC32XX_getNumSectors set command" - " power constraint", hwAttrs->baseAddr); - - /* De-Select the card on the input drive(Stand-by state) */ - if (deSelectCard(handle) != SD_STATUS_SUCCESS) { - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_log1("SDHost:(%p) SDHostCC32XX_getNumSectors released command" - " power constraint", hwAttrs->baseAddr); - return (0); - } - - if (send_cmd(handle, CMD_SEND_CSD, (object->rca << 16)) == - SD_STATUS_SUCCESS) { - - MAP_SDHostRespGet(hwAttrs->baseAddr, (unsigned long *)resp); - - /* - * 136 bit CSD register is read into an array of 4 words - * Note: Does not include 8 bit CRC - * resp[0] = CSD[31:0] - * resp[1] = CSD[63:32] - * resp[2] = CSD[95:64] - * resp[3] = CSD[127:96] - */ - if(((resp[3] >> 30) & 0x01) == 1) { - sectors = (resp[1] >> 16 | ((resp[2] & 0x3F) << 16)) + 1; - sectors *= 1024; - } - else { - blockSize = 1 << ((resp[2] >> 16) & 0x0F); - sizeMult = ((resp[1] >> 15) & 0x07); - cSize = ((resp[1] >> 30) | (resp[2] & 0x3FF) << 2); - sectors = (cSize + 1) * (1 << (sizeMult + 2)); - sectors = (sectors * blockSize) / SECTORSIZE; - - } - } - - /* Select the card on the input drive(Transfer state) */ - if (selectCard(handle) != SD_STATUS_SUCCESS) { - sectors = 0; - } - - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_log1("SDHost:(%p) SDHostCC32XX_getNumSectors released command" - " power constraint", hwAttrs->baseAddr); - - return (sectors); -} - -/* - * ======== SDHostCC32XX_getSectorSize ======== - * Function to perform a disk read from the SD Card on the specifed drive. - */ -uint_fast32_t SDHostCC32XX_getSectorSize(SD_Handle handle) -{ - return (SECTORSIZE); -} - -/* - * ======== SDHostCC32XX_initialize ======== - * Function to initialize the SD Card. - */ -int_fast16_t SDHostCC32XX_initialize(SD_Handle handle) -{ - int_fast32_t result; - uint_fast32_t resp[4]; - SDHostCC32XX_Object *object = handle->object; - SDHostCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_log1("SDHost:(%p) SDHostCC32XX_initialize set read/write" - " power constraint", hwAttrs->baseAddr); - - /* Send go to IDLE command */ - result = send_cmd(handle, CMD_GO_IDLE_STATE, NULLARG); - - if (result == SD_STATUS_SUCCESS) { - /* Get interface operating condition for the card */ - result = send_cmd(handle, CMD_SEND_IF_COND, - SUPPLYVOLTAGE | CHECKSUM); - /* Verify response will be valid */ - if (result == SD_STATUS_SUCCESS) { - MAP_SDHostRespGet(hwAttrs->baseAddr, (unsigned long *)resp); - } - } - - /* SD ver 2.0 or higher card */ - if ((result == SD_STATUS_SUCCESS) && ((resp[0] & 0xFF) == - CHECKSUM)) { - object->cardType = SD_SDSC; - - /* Wait for card to be ready */ - do { - /* Send ACMD41 */ - result = send_cmd(handle, CMD_APP_CMD, NULLARG); - - if (result == SD_STATUS_SUCCESS) { - result = send_cmd(handle, CMD_SD_SEND_OP_COND, - HIGHCAPSUPPORT | VOLTAGEWINDOW); - /* Response contains 32-bit OCR register */ - MAP_SDHostRespGet(hwAttrs->baseAddr, (unsigned long *)resp); - } - - /* Wait until card is ready, spool on busy bit */ - } while((result == SD_STATUS_SUCCESS) && ((resp[0] >> 31) == 0)); - - /* Card capacity status bit */ - if ((result == SD_STATUS_SUCCESS) && (resp[0] & (1UL << 30))) { - object->cardType = SD_SDHC; - } - } - /* It's a MMC or SD 1.x card */ - else { - /* Wait for card to be ready */ - do { - /* Send ACMD41 */ - result = send_cmd(handle, CMD_APP_CMD, NULLARG); - - if (result == SD_STATUS_SUCCESS) { - result = send_cmd(handle, CMD_SD_SEND_OP_COND, VOLTAGEWINDOW); - } - - if (result == SD_STATUS_SUCCESS) { - /* Response contains 32-bit OCR register */ - MAP_SDHostRespGet(hwAttrs->baseAddr, (unsigned long *)resp); - } - - /* Wait until card is ready, spool on busy bit */ - } while((result == SD_STATUS_SUCCESS) && ((resp[0] >> 31) == 0)); - - if (result == SD_STATUS_SUCCESS) { - object->cardType = SD_SDSC; - } - else if (send_cmd(handle, CMD_SEND_OP_COND, NULLARG) == - SD_STATUS_SUCCESS) { - object->cardType = SD_MMC; - } - /* No command responses */ - else { - object->cardType = SD_NOCARD; - } - } - - /* Get the relative card address (RCA) of the attached card */ - if (object->cardType != SD_NOCARD) { - result = send_cmd(handle, CMD_ALL_SEND_CID, NULLARG); - - if (result == SD_STATUS_SUCCESS) { - result = send_cmd(handle, CMD_SEND_REL_ADDR, NULLARG); - } - - if (result == SD_STATUS_SUCCESS) { - /* Fill in the RCA */ - MAP_SDHostRespGet(hwAttrs->baseAddr, (unsigned long *)resp); - - object->rca = resp[0] >> 16; - - /* Select the card on the input drive(Transfer state) */ - result = selectCard(handle); - if (result == SD_STATUS_SUCCESS) { - /* Set card read/write block length */ - MAP_SDHostBlockSizeSet(hwAttrs->baseAddr, SECTORSIZE); - - /* Initialization succeeded */ - result = SD_STATUS_SUCCESS; - } - } - } - else { - DebugP_log1("SDHost:(%p) Could not select card", - hwAttrs->baseAddr); - result = SD_STATUS_ERROR; - } - - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_log1("SDHost:(%p) SDHostCC32XX_initialize released read/write" - " power constraint", hwAttrs->baseAddr); - - return (result); -} - -/* - * ======== SDHostCC32XX_init ======== - * Function to initialize the SDHost module - */ -void SDHostCC32XX_init(SD_Handle handle) -{ - SDHostCC32XX_Object *object = handle->object; - - object->writeBuf = NULL; - object->readBuf = NULL; - object->writeSecCount = 0; - object->readSecCount = 0; - object->cardType = SD_NOCARD; - object->isOpen = false; - - UDMACC32XX_init(); -} - -/* - * ======== SDHostCC32XX_open ======== - */ -SD_Handle SDHostCC32XX_open(SD_Handle handle, SD_Params *params) -{ - uintptr_t key; - SemaphoreP_Params semParams; - HwiP_Params hwiParams; - SDHostCC32XX_Object *object = handle->object; - SDHostCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uint16_t pin; - - key = HwiP_disable(); - - if (object->isOpen) { - HwiP_restore(key); - - DebugP_log1("SDHost:(%p) already in use.", hwAttrs->baseAddr); - return (NULL); - } - object->isOpen = true; - - HwiP_restore(key); - - /* Initialize the SDCARD_CLK pin ID to undefined */ - object->clkPin = (uint16_t)-1; - - /* Get the Power resource Id from the base address */ - object->powerMgrId = getPowerMgrId(hwAttrs->baseAddr); - if (object->powerMgrId == (unsigned int)-1) { - DebugP_log1("SDHost:(%p) Failed to determine Power resource id", - hwAttrs->baseAddr); - return (NULL); - } - - /* - * Register power dependency. Keeps the clock running in SLP - * and DSLP modes. - */ - Power_setDependency(object->powerMgrId); - - Power_registerNotify(&object->postNotify, PowerCC32XX_AWAKE_LPDS, - postNotifyFxn, (uintptr_t)handle); - - object->dmaHandle = UDMACC32XX_open(); - if (object->dmaHandle == NULL) { - DebugP_log1("SDHost:(%p) UDMACC32XX_open() failed.", - hwAttrs->baseAddr); - SDHostCC32XX_close(handle); - return (NULL); - } - - SemaphoreP_Params_init(&semParams); - semParams.mode = SemaphoreP_Mode_BINARY; - object->cmdSem = SemaphoreP_create(0, &semParams); - - if (object->cmdSem == NULL) { - DebugP_log1("SDHost:(%p) SemaphoreP_create() failed.", - hwAttrs->baseAddr); - SDHostCC32XX_close(handle); - return (NULL); - } - - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t)handle; - hwiParams.priority = hwAttrs->intPriority; - object->hwiHandle = HwiP_create(INT_MMCHS, hwiIntFxn, - &hwiParams); - if (object->hwiHandle == NULL) { - DebugP_log1("SDHostT:(%p) HwiP_create() failed", hwAttrs->baseAddr); - SDHostCC32XX_close(handle); - return (NULL); - } - - /* Initialize the hardware */ - initHw(handle); - - /* Save clkPin park state; set to logic '0' during LPDS */ - pin = PinConfigPin(hwAttrs->clkPin); - object->prevParkCLK = - (PowerCC32XX_ParkState) PowerCC32XX_getParkState((PowerCC32XX_Pin)pin); - PowerCC32XX_setParkState((PowerCC32XX_Pin)pin, 0); - object->clkPin = pin; - - DebugP_log1("SDHost:(%p) opened", hwAttrs->baseAddr); - - return (handle); -} - -/* - * ======== SDHostCC32XX_read ======== - */ -int_fast16_t SDHostCC32XX_read(SD_Handle handle, void *buf, - int_fast32_t sector, uint_fast32_t secCount) -{ - int_fast32_t result; - uint_fast32_t ret; - uint_fast32_t size; - SDHostCC32XX_Object *object = handle->object; - SDHostCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - object->stat = SD_STATUS_ERROR; - - /* Check for valid sector count */ - if (secCount == 0) { - return (SD_STATUS_ERROR); - } - - /* SDSC uses linear address, SDHC uses block address */ - if (object->cardType == SD_SDSC) { - sector = sector * SECTORSIZE; - } - - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_log1("SDHost:(%p) SDHostCC32XX_read set read power constraint", - hwAttrs->baseAddr); - - /* Set the block count */ - MAP_SDHostBlockCountSet(hwAttrs->baseAddr, secCount); - - /* If input buffer is word aligned use DMA */ - if (!(((uint_fast32_t)buf) & 0x03)) { - object->readBuf = (uint_fast32_t *)buf; - object->readSecCount = secCount; - - /* Configure Primary structure */ - configDMAChannel(handle, UDMA_PRI_SELECT , UDMAREAD); - - /* Add offset to input buffer */ - object->readBuf = (uint_fast32_t *)((uint_least8_t *)buf + - SECTORSIZE); - - /* Configure alternate control structure */ - configDMAChannel(handle, UDMA_ALT_SELECT , UDMAREAD); - - MAP_SDHostIntClear(hwAttrs->baseAddr, SDHOST_INT_DMARD); - - /* Send multi block read command */ - result = send_cmd(handle, CMD_READ_MULTI_BLK | SDHOST_DMA_EN, sector); - - if (result == SD_STATUS_SUCCESS) { - MAP_SDHostIntEnable(hwAttrs->baseAddr, SDHOST_INT_DMARD); - - /* Wait for DMA read(s) to complete */ - SemaphoreP_pend(object->cmdSem, SemaphoreP_WAIT_FOREVER); - - MAP_SDHostIntDisable(hwAttrs->baseAddr, SDHOST_INT_DMARD); - } - } - /* Poll buffer for new data */ - else { - /* Compute the number of words to read */ - size = (SECTORSIZE * secCount) / 4; - - /* Send multi block read command */ - result = send_cmd(handle, CMD_READ_MULTI_BLK, sector); - - if (result == SD_STATUS_SUCCESS) { - /* Read single word of data */ - while (size > 0) { - ret = MAP_SDHostDataNonBlockingRead(hwAttrs->baseAddr, - (unsigned long *)buf); - /* Block until buffer is ready */ - if (ret == 0) { - MAP_SDHostIntEnable(hwAttrs->baseAddr, SDHOST_INT_BRR); - - SemaphoreP_pend(object->cmdSem, SemaphoreP_WAIT_FOREVER); - - MAP_SDHostIntDisable(hwAttrs->baseAddr, SDHOST_INT_BRR); - } - else { - buf = (uint_least8_t *)buf + 4; - size--; - } - } - } - } - - /* Verify host controller errors didn't occur */ - if (object->stat == SD_STATUS_SUCCESS) { - - MAP_SDHostIntEnable(hwAttrs->baseAddr, SDHOST_INT_TC); - - /* Wait for full data transfer to complete */ - SemaphoreP_pend(object->cmdSem, SemaphoreP_WAIT_FOREVER); - - MAP_SDHostIntDisable(hwAttrs->baseAddr, SDHOST_INT_TC); - } - - /* Verify host controller errors didn't occur */ - if (object->stat == SD_STATUS_SUCCESS) { - - /* Wait for command transfer stop acknowledgement */ - result = send_cmd(handle, CMD_STOP_TRANS, NULLARG); - - if (result == SD_STATUS_SUCCESS) { - MAP_SDHostIntEnable(hwAttrs->baseAddr, SDHOST_INT_TC); - - SemaphoreP_pend(object->cmdSem, SemaphoreP_WAIT_FOREVER); - - MAP_SDHostIntDisable(hwAttrs->baseAddr, SDHOST_INT_TC); - } - } - - if (object->stat != SD_STATUS_SUCCESS) { - result = SD_STATUS_ERROR; - } - - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_log1("SDHost:(%p) SDHostCC32XX_read released read power" - " constraint", hwAttrs->baseAddr); - - return (result); -} - -/* - * ======== SDHostCC32XX_write ======== - */ -int_fast16_t SDHostCC32XX_write(SD_Handle handle, const void *buf, - int_fast32_t sector, uint_fast32_t secCount) -{ - int_fast32_t result; - uint_fast32_t ret; - uint_fast32_t size; - SDHostCC32XX_Object *object = handle->object; - SDHostCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - object->stat = SD_STATUS_ERROR; - - /* Check for valid sector count */ - if (secCount == 0) { - return (SD_STATUS_ERROR); - } - - /* SDSC uses linear address, SDHC uses block address */ - if(object->cardType == SD_SDSC) { - sector = sector * SECTORSIZE; - } - - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_log1("SDHost:(%p) SDHostCC32XX_write set write power" - " constraint", hwAttrs->baseAddr); - - /* Set the block count */ - MAP_SDHostBlockCountSet(hwAttrs->baseAddr, secCount); - - /* Set the card write block count */ - result = send_cmd(handle, CMD_APP_CMD, object->rca << 16); - - if (result == SD_STATUS_SUCCESS) { - result = send_cmd(handle, CMD_SET_BLK_CNT, secCount); - } - - /* If input buffer is word aligned use DMA */ - if (!(((uint_fast32_t)buf) & 0x03)) { - object->writeBuf = (uint_fast32_t *)buf; - object->writeSecCount = secCount; - - /* Configure Primary structure */ - configDMAChannel(handle, UDMA_PRI_SELECT, UDMAWRITE); - - /* Add offset to input buffer */ - object->writeBuf = (uint_fast32_t *)((uint_least8_t *)buf + - SECTORSIZE); - /* Configure alternate control structure */ - configDMAChannel(handle, UDMA_ALT_SELECT, UDMAWRITE); - - /* Verify that the block count had been previous set */ - if (result == SD_STATUS_SUCCESS) { - result = send_cmd(handle, CMD_WRITE_MULTI_BLK | SDHOST_DMA_EN, - sector); - } - - if (result == SD_STATUS_SUCCESS) { - /* Wait for DMA write(s) to complete */ - MAP_SDHostIntEnable(hwAttrs->baseAddr, SDHOST_INT_DMAWR); - - SemaphoreP_pend(object->cmdSem, SemaphoreP_WAIT_FOREVER); - - MAP_SDHostIntDisable(hwAttrs->baseAddr, SDHOST_INT_DMAWR); - } - - } - else { - /* Compute the number of words to write */ - size = (SECTORSIZE * secCount) / 4; - - /* Verify that the block count had been previous set */ - if (result == SD_STATUS_SUCCESS) { - result = send_cmd(handle, CMD_WRITE_MULTI_BLK, sector); - } - - if (result == SD_STATUS_SUCCESS) { - /* Write single word of data */ - while (size > 0) { - ret = MAP_SDHostDataNonBlockingWrite(hwAttrs->baseAddr, - (*(unsigned long *)buf)); - - /* Block until buffer is ready */ - if (ret == 0) { - MAP_SDHostIntEnable(hwAttrs->baseAddr, SDHOST_INT_BWR); - - SemaphoreP_pend(object->cmdSem, SemaphoreP_WAIT_FOREVER); - - MAP_SDHostIntDisable(hwAttrs->baseAddr, SDHOST_INT_BWR); - } - else { - buf = (uint_least8_t *)buf + 4; - size--; - } - } - } - } - - /* Verify host controller errors didn't occur */ - if (object->stat == SD_STATUS_SUCCESS) { - /* Wait for the full data transfer to complete */ - MAP_SDHostIntEnable(hwAttrs->baseAddr, SDHOST_INT_TC); - - SemaphoreP_pend(object->cmdSem, SemaphoreP_WAIT_FOREVER); - - MAP_SDHostIntDisable(hwAttrs->baseAddr, SDHOST_INT_TC); - } - - /* Verify host controller errors didn't occur */ - if (object->stat == SD_STATUS_SUCCESS) { - /* Wait for command transfer stop acknowledgement */ - result = send_cmd(handle, CMD_STOP_TRANS, NULLARG); - - if (result == SD_STATUS_SUCCESS) { - MAP_SDHostIntEnable(hwAttrs->baseAddr, SDHOST_INT_TC); - - SemaphoreP_pend(object->cmdSem, SemaphoreP_WAIT_FOREVER); - - MAP_SDHostIntDisable(hwAttrs->baseAddr, SDHOST_INT_TC); - } - } - - if (object->stat != SD_STATUS_SUCCESS) { - result = SD_STATUS_ERROR; - } - - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_log1("SDHost:(%p) SDHostCC32XX_write released write power" - " constraint", hwAttrs->baseAddr); - - return (result); -} - -/* - * ======== configDMAChannel ======== - * Configures either the primary or alternate DMA control structures in - * ping-pong mode. - * channelSel is the PRI or ALT channel select flag - */ -static void configDMAChannel(SD_Handle handle, uint_fast32_t channelSel, - uint_fast32_t operation) -{ - unsigned long channelControlOptions; - SDHostCC32XX_Object *object = handle->object; - SDHostCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - if (operation == UDMAWRITE) { - channelControlOptions = UDMA_SIZE_32 | UDMA_SRC_INC_32 | - UDMA_DST_INC_NONE | UDMA_ARB_512; - - /* Primary control structure set-up */ - MAP_uDMAChannelControlSet(hwAttrs->txChIdx | - channelSel, channelControlOptions); - - /* Transfer size is the sector size in words */ - MAP_uDMAChannelTransferSet(hwAttrs->txChIdx | channelSel, - UDMA_MODE_PINGPONG, (void *)object->writeBuf, - (void *)(hwAttrs->baseAddr + MMCHS_O_DATA), SECTORSIZE / 4); - - /* Enable the DMA channel */ - MAP_uDMAChannelEnable(hwAttrs->txChIdx); - } - else { - channelControlOptions = UDMA_SIZE_32 | UDMA_SRC_INC_NONE | - UDMA_DST_INC_32 | UDMA_ARB_512; - - /* Primary control structure set-up */ - MAP_uDMAChannelControlSet(hwAttrs->rxChIdx | - channelSel, channelControlOptions); - - /* Transfer size is the sector size in words */ - MAP_uDMAChannelTransferSet(hwAttrs->rxChIdx | channelSel, - UDMA_MODE_PINGPONG, (void *)(hwAttrs->baseAddr + MMCHS_O_DATA), - (void *)object->readBuf, SECTORSIZE / 4); - - /* Enable the DMA channel */ - MAP_uDMAChannelEnable(hwAttrs->rxChIdx); - } -} - -/* - * ======== deSelectCard ======== - * Function to de-select a card on the drive specified by the handle. - */ -static int_fast32_t deSelectCard(SD_Handle handle) -{ - int_fast32_t result; - - /* De-select the card */ - result = send_cmd(handle, CMD_DESELECT_CARD, NULLARG); - - return (result); -} - -/* - * ======== getPowerMgrId ======== - */ -static uint_fast32_t getPowerMgrId(uint_fast32_t baseAddr) -{ - if (baseAddr == SDHOST_BASE) { - return (PowerCC32XX_PERIPH_SDHOST); - } - else { - return ((uint_fast32_t)-1); - } -} - -/* - * ======== hwiIntFxn ======== - * ISR to service pending SD or DMA commands. - */ -static void hwiIntFxn(uintptr_t handle) -{ - uint_fast32_t ret; - uint_fast32_t priChannelMode; - uint_fast32_t altChannelMode; - SDHostCC32XX_Object *object = ((SD_Handle)handle)->object; - SDHostCC32XX_HWAttrsV1 const *hwAttrs = ((SD_Handle)handle)->hwAttrs; - - /* Get interrupt status */ - ret = MAP_SDHostIntStatus(hwAttrs->baseAddr); - - /* Don't unblock if an error occurred */ - if (ret & SDHOST_INT_ERRI) { - /* Clear any spurious interrupts caused by the error */ - MAP_SDHostIntClear(hwAttrs->baseAddr, SDHOST_INT_CC | SDHOST_INT_TC | - DATAERROR | CMDERROR); - - /* Error or unsupported interrupt occurred */ - object->stat = SD_STATUS_ERROR; - SemaphoreP_post(object->cmdSem); - } - /* Command complete flag */ - else if (ret & SDHOST_INT_CC) { - object->stat = SD_STATUS_SUCCESS; - MAP_SDHostIntClear(hwAttrs->baseAddr, SDHOST_INT_CC); - SemaphoreP_post(object->cmdSem); - } - /* DMA read complete flag */ - else if (ret & SDHOST_INT_DMARD) { - object->readSecCount--; - - priChannelMode = MAP_uDMAChannelModeGet(hwAttrs->rxChIdx | - UDMA_PRI_SELECT); - altChannelMode = MAP_uDMAChannelModeGet(hwAttrs->rxChIdx | - UDMA_ALT_SELECT); - - /* Corner case in which a DMA interrupt is missed, (both completed) */ - if ((priChannelMode != UDMA_MODE_STOP) || - (altChannelMode != UDMA_MODE_STOP)) { - MAP_SDHostIntClear(hwAttrs->baseAddr, SDHOST_INT_DMARD); - } - - /* Check if transfer is complete */ - if (object->readSecCount == 0) { - MAP_SDHostIntClear(hwAttrs->baseAddr, SDHOST_INT_DMARD); - - object->stat = SD_STATUS_SUCCESS; - - /* Reset to primary channel */ - MAP_uDMAChannelAttributeDisable(hwAttrs->rxChIdx, - UDMA_ATTR_ALTSELECT); - SemaphoreP_post(object->cmdSem); - } - else { - /* Set-up next portion of buffer to be written to */ - object->readBuf = object->readBuf + (SECTORSIZE / 4); - - /* Check if primary channel completed */ - if (priChannelMode == UDMA_MODE_STOP) { - configDMAChannel((SD_Handle)handle, UDMA_PRI_SELECT, UDMAREAD); - } - /* Secondary completed */ - else { - configDMAChannel((SD_Handle)handle, UDMA_ALT_SELECT, UDMAREAD); - } - } - } - /* DMA write complete flag */ - else if (ret & SDHOST_INT_DMAWR) { - object->writeSecCount--; - - priChannelMode = MAP_uDMAChannelModeGet(hwAttrs->txChIdx | - UDMA_PRI_SELECT); - altChannelMode = MAP_uDMAChannelModeGet(hwAttrs->txChIdx | - UDMA_ALT_SELECT); - - /* Corner case in which a DMA interrupt is missed (both completed) */ - if ((priChannelMode != UDMA_MODE_STOP) || - (altChannelMode != UDMA_MODE_STOP)) { - MAP_SDHostIntClear(hwAttrs->baseAddr, SDHOST_INT_DMAWR); - } - - /* Check if transfer is complete */ - if (object->writeSecCount == 0) { - MAP_SDHostIntClear(hwAttrs->baseAddr, SDHOST_INT_DMAWR); - - object->stat = SD_STATUS_SUCCESS; - - /* Reset to primary channel */ - MAP_uDMAChannelAttributeDisable(hwAttrs->txChIdx, - UDMA_ATTR_ALTSELECT); - SemaphoreP_post(object->cmdSem); - } - else { - /* Set-up next portion of buffer to be written to */ - object->writeBuf = object->writeBuf + (SECTORSIZE / 4); - - /* Check if primary channel completed */ - if (priChannelMode == UDMA_MODE_STOP) { - configDMAChannel((SD_Handle)handle, UDMA_PRI_SELECT, - UDMAWRITE); - } - /* Secondary completed */ - else { - configDMAChannel((SD_Handle)handle, UDMA_ALT_SELECT, - UDMAWRITE); - } - } - } - else { - /* Transfer complete flag */ - if (ret & SDHOST_INT_TC) { - MAP_SDHostIntClear(hwAttrs->baseAddr, SDHOST_INT_TC); - } - /* Data buffer read ready flag */ - else if (ret & SDHOST_INT_BRR) { - MAP_SDHostIntClear(hwAttrs->baseAddr, SDHOST_INT_BRR); - } - /* Data buffer write ready flag */ - else if (ret & SDHOST_INT_BWR) { - MAP_SDHostIntClear(hwAttrs->baseAddr, SDHOST_INT_BWR); - } - object->stat = SD_STATUS_SUCCESS; - SemaphoreP_post(object->cmdSem); - } -} - -/* - * ======== initHw ======== - */ -static void initHw(SD_Handle handle) -{ - SDHostCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uint32_t pin; - uint32_t mode; - - /* Configure for SDHost Data */ - pin = PinConfigPin(hwAttrs->dataPin); - mode = PinConfigPinMode(hwAttrs->dataPin); - MAP_PinTypeSDHost(pin, mode); - MAP_PinConfigSet(pin, PIN_STRENGTH_4MA, PIN_TYPE_STD_PU); - - /* Configure for SDHost Command */ - pin = PinConfigPin(hwAttrs->cmdPin); - mode = PinConfigPinMode(hwAttrs->cmdPin); - MAP_PinTypeSDHost(pin, mode); - MAP_PinConfigSet(pin, PIN_STRENGTH_4MA, PIN_TYPE_STD_PU); - - /* Configure for SDHost clock output */ - pin = PinConfigPin(hwAttrs->clkPin); - mode = PinConfigPinMode(hwAttrs->clkPin); - MAP_PinTypeSDHost(pin, mode); - MAP_PinDirModeSet(pin, PIN_DIR_MODE_OUT); - - MAP_PRCMPeripheralReset(PRCM_SDHOST); - MAP_SDHostInit(hwAttrs->baseAddr); - - MAP_SDHostIntDisable(hwAttrs->baseAddr, SDHOST_INT_CC | SDHOST_INT_TC | - SDHOST_INT_DMAWR | SDHOST_INT_DMARD | SDHOST_INT_BRR | SDHOST_INT_BWR); - - /* Configure card clock */ - MAP_SDHostSetExpClk(hwAttrs->baseAddr, - MAP_PRCMPeripheralClockGet(PRCM_SDHOST), hwAttrs->clkRate); - - MAP_SDHostIntClear(hwAttrs->baseAddr, SDHOST_INT_CC | SDHOST_INT_TC | - DATAERROR | CMDERROR | SDHOST_INT_DMAWR | SDHOST_INT_DMARD | - SDHOST_INT_BRR | SDHOST_INT_BWR); - - /* - * DMA channels 23 and 24 are connected to the SD peripheral by default. - * If someone hasn't remapped them to something else already, we remap - * them to SW. - */ - if (!(HWREG(UDMA_BASE + UDMA_O_CHMAP2) & UDMA_CHMAP2_CH23SEL_M)) { - MAP_uDMAChannelAssign(UDMA_CH23_SW); - } - if (!(HWREG(UDMA_BASE + UDMA_O_CHMAP3) & UDMA_CHMAP3_CH24SEL_M)) { - MAP_uDMAChannelAssign(UDMA_CH24_SW); - } - - /* Configure DMA for TX and RX */ - MAP_uDMAChannelAssign(hwAttrs->txChIdx); - MAP_uDMAChannelAssign(hwAttrs->rxChIdx); - - /* Enable SDHost Error Interrupts */ - MAP_SDHostIntEnable(hwAttrs->baseAddr, DATAERROR | CMDERROR); -} - - -/* - * ======== postNotifyFxn ======== - * Called by Power module when waking up from LPDS. - */ -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - initHw((SD_Handle)clientArg); - - return (Power_NOTIFYDONE); -} - -/* - * ======== send_cmd ======== - * Function to send a command to the SD Card - */ -static int_fast32_t send_cmd(SD_Handle handle, uint_fast32_t cmd, - uint_fast32_t arg) -{ - int_fast32_t result = SD_STATUS_SUCCESS; - SDHostCC32XX_Object *object = handle->object; - SDHostCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - /* Send the command */ - MAP_SDHostCmdSend(hwAttrs->baseAddr, cmd, arg); - - /* Enable command complete interrupts */ - MAP_SDHostIntEnable(hwAttrs->baseAddr, SDHOST_INT_CC); - - SemaphoreP_pend(object->cmdSem, SemaphoreP_WAIT_FOREVER); - - MAP_SDHostIntDisable(hwAttrs->baseAddr, SDHOST_INT_CC); - - /* SD Card Error, reset the command line */ - if (object->stat == SD_STATUS_ERROR) { - MAP_SDHostCmdReset(hwAttrs->baseAddr); - result = SD_STATUS_ERROR; - } - - return (result); -} - -/* - * ======== selectCard ======== - * Function to select a card on the specified drive. - */ -static int_fast32_t selectCard(SD_Handle handle) -{ - int_fast32_t result; - SDHostCC32XX_Object *object = handle->object; - SDHostCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - /* Select the card */ - result = send_cmd(handle, CMD_SELECT_CARD, object->rca << 16); - - if (result == SD_STATUS_SUCCESS) { - /* Wait for transfer compelte interrupt */ - MAP_SDHostIntEnable(hwAttrs->baseAddr, SDHOST_INT_TC); - - SemaphoreP_pend(object->cmdSem, SemaphoreP_WAIT_FOREVER); - - MAP_SDHostIntDisable(hwAttrs->baseAddr, SDHOST_INT_TC); - - /* Host controller error occurred */ - if (object->stat != SD_STATUS_SUCCESS) { - result = SD_STATUS_ERROR; - } - } - return (result); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/sd/SDHostCC32XX.h b/ext/hal/ti/simplelink/source/ti/drivers/sd/SDHostCC32XX.h deleted file mode 100644 index d728809fb70..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/sd/SDHostCC32XX.h +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2016-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/** ============================================================================ - * @file SDHostCC32XX.h - * - * @brief SDHost driver implementation for CC32XX devices. - * - * The SDHost header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref SD.h for a complete description of APIs & example of use. - * - * This SDHost driver implementation is designed to operate on a CC32XX - * SD Host controller using a micro DMA controller. - * - * Note: The driver API's are not thread safe and must not be accessed through - * multiple threads without the use of mutexes. - * - * ## DMA buffer alignment # - * - * When performing disk operations with a word aligned buffer the driver will - * make transfers using the DMA controller. Alternatively, if the buffer is - * not aligned, the data will be copied to the internal SD Host controller - * buffer using a polling method. - * - * ## DMA Interrupts # - * - * When DMA is used, the micro DMA controller generates and IRQ on the - * perpheral's interrupt vector. This implementation automatically installs - * a DMA interrupt to service the assigned micro DMA channels. - * - * ## DMA accessible memory # - * - * When DMA is used, it is the responsibility of the application to ensure - * that read/write buffers reside in memory that is accessible by the DMA. - * - * ============================================================================ - */ - -#ifndef ti_drivers_sd_SDHostCC32XX__include -#define ti_drivers_sd_SDHostCC32XX__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#include -#include -#include -#include -#include - -#define SDHostCC32XX_PIN_06_SDCARD_DATA 0x0805 -#define SDHostCC32XX_PIN_07_SDCARD_CLK 0x0806 -#define SDHostCC32XX_PIN_08_SDCARD_CMD 0x0807 -#define SDHostCC32XX_PIN_01_SDCARD_CLK 0x0600 -#define SDHostCC32XX_PIN_02_SDCARD_CMD 0x0601 -#define SDHostCC32XX_PIN_64_SDCARD_DATA 0x063f - -/* SDHost function table */ -extern const SD_FxnTable sdHostCC32XX_fxnTable; - -/*! - * @brief SDHostCC32XX Hardware attributes - * - * The SDHostCC32XX configuration structure is passed to the SDHostCC32XX - * driver implementation with hardware specifics regarding GPIO Pins and Ports - * to be used. - * - * The SDHostCC32XX driver uses this information to: - * - Configure and reconfigure specific ports/pins to initialize the SD Card - * for SD mode - * - Identify which GPIO port and pin is used for the SDHost clock, data and - * command lines - * - * These fields are used by driverlib APIs and therefore must be populated by - * driverlib macro definitions. For CC32xxWare these definitions are found in: - * - inc/hw_memmap.h - * - driverlib/pin.h - * - * @struct SDHostCC32XX_HWAttrs - * An example configuration structure could look as the following: - * @code - * const SDHostCC32XX_HWAttrsV1 sdhostCC32XXHWattrs[] = { - * { - * .clkRate = 8000000, - * .intPriority = ~0, - * .baseAddr = SDHOST_BASE, - * .rxChIdx = UDMA_CH23_SDHOST_RX, - * .txChIdx = UDMA_CH24_SDHOST_TX, - * .dataPin = SDHostCC32XX_PIN_06_SDCARD_DATA, - * .cmdPin = SDHostCC32XX_PIN_08_SDCARD_CMD, - * .clkPin = SDHostCC32XX_PIN_07_SDCARD_CLK, - * } - * }; - * @endcode - */ -typedef struct SDHostCC32XX_HWAttrsV1 { - /*! SD interface clock rate */ - uint_fast32_t clkRate; - - /*! Internal SDHost ISR command/transfer priorty */ - int_fast32_t intPriority; - - /*! SDHost Peripheral base address */ - uint_fast32_t baseAddr; - - /*! uDMA controlTable receive channel index */ - unsigned long rxChIdx; - - /*! uDMA controlTable transmit channel index */ - unsigned long txChIdx; - - /*! SD Host Data pin */ - uint32_t dataPin; - - /*! SD Host CMD pin */ - uint32_t cmdPin; - - /*! SD Host CLK pin */ - uint32_t clkPin; -} SDHostCC32XX_HWAttrsV1; - -/*! - * @brief SDHostCC32XX Object - * - * The application must not access any member variables of this structure! - */ -typedef struct SDHostCC32XX_Object { - /* Relative Card Address */ - uint_fast32_t rca; - /* Write data pointer */ - const uint_fast32_t *writeBuf; - /* Number of sectors written */ - volatile uint_fast32_t writeSecCount; - /* Read data pointer */ - uint_fast32_t *readBuf; - /* Number of sectors read */ - volatile uint_fast32_t readSecCount; - /* - * Semaphore to suspend thread execution when waiting for SD Commands - * or data transfers to complete. - */ - SemaphoreP_Handle cmdSem; - /* - * SD Card interrupt handle. - */ - HwiP_Handle hwiHandle; - /* Determined from base address */ - unsigned int powerMgrId; - /* LPDS wake-up notify object */ - Power_NotifyObj postNotify; - /* Previous park state SDCARD_CLK pin */ - PowerCC32XX_ParkState prevParkCLK; - /* SDCARD_CLK pin */ - uint16_t clkPin; - /* UDMA Handle */ - UDMACC32XX_Handle dmaHandle; - /* SD Card command state */ - volatile int_fast8_t stat; - /* State of the driver (open or closed) */ - bool isOpen; - /* SDCard Card Command Class(CCC) */ - SD_CardType cardType; -} SDHostCC32XX_Object; - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_sd_SDHostCC32XX__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/sd/SDSPI.c b/ext/hal/ti/simplelink/source/ti/drivers/sd/SDSPI.c deleted file mode 100644 index 85bc6758232..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/sd/SDSPI.c +++ /dev/null @@ -1,785 +0,0 @@ -/* - * Copyright (c) 2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* - * ======== SDSPI.c ======== - */ - -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -/* Definitions for MMC/SDC command */ -#define CMD0 (0x40+0) /* GO_IDLE_STATE */ -#define CMD1 (0x40+1) /* SEND_OP_COND */ -#define CMD8 (0x40+8) /* SEND_IF_COND */ -#define CMD9 (0x40+9) /* SEND_CSD */ -#define CMD10 (0x40+10) /* SEND_CID */ -#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ -#define CMD16 (0x40+16) /* SET_BLOCKLEN */ -#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ -#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ -#define CMD23 (0x40+23) /* SET_BLOCK_COUNT */ -#define CMD24 (0x40+24) /* WRITE_BLOCK */ -#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ -#define CMD41 (0x40+41) /* SEND_OP_COND (ACMD) */ -#define CMD55 (0x40+55) /* APP_CMD */ -#define CMD58 (0x40+58) /* READ_OCR */ -#define START_BLOCK_TOKEN (0xFE) -#define START_MULTIBLOCK_TOKEN (0xFC) -#define STOP_MULTIBLOCK_TOKEN (0xFD) - -#define SD_SECTOR_SIZE (512) - -#define DRIVE_NOT_MOUNTED ((uint16_t) ~0) - -void SDSPI_close(SD_Handle handle); -int_fast16_t SDSPI_control(SD_Handle handle, uint_fast16_t cmd, - void *arg); -uint_fast32_t SDSPI_getNumSectors(SD_Handle handle); -uint_fast32_t SDSPI_getSectorSize(SD_Handle handle); -int_fast16_t SDSPI_initialize(SD_Handle handle); -void SDSPI_init(SD_Handle handle); -SD_Handle SDSPI_open(SD_Handle handle, SD_Params *params); -int_fast16_t SDSPI_read(SD_Handle handle, void *buf, - int_fast32_t sector, uint_fast32_t sectorCount); -int_fast16_t SDSPI_write(SD_Handle handle, const void *buf, - int_fast32_t sector, uint_fast32_t sectorCount); - -static inline void assertCS(SDSPI_HWAttrs const *hwAttrs); -static inline void deassertCS(SDSPI_HWAttrs const *hwAttrs); -static bool recvDataBlock(SPI_Handle handle, void *buf, uint32_t count); -static uint8_t sendCmd(SPI_Handle handle, uint8_t cmd, uint32_t arg); -static int_fast16_t sendInitialClockTrain(SPI_Handle handle); -static int_fast16_t spiTransfer(SPI_Handle handle, void *rxBuf, - void *txBuf, size_t count); -static bool waitUntilReady(SPI_Handle handle); -static bool transmitDataBlock(SPI_Handle handle, void *buf, uint32_t count, - uint8_t token); - -/* SDSPI function table for SDSPIMSP432 implementation */ -const SD_FxnTable SDSPI_fxnTable = { - SDSPI_close, - SDSPI_control, - SDSPI_getNumSectors, - SDSPI_getSectorSize, - SDSPI_init, - SDSPI_initialize, - SDSPI_open, - SDSPI_read, - SDSPI_write -}; - -/* - * ======== SDSPI_close ======== - */ -void SDSPI_close(SD_Handle handle) -{ - SDSPI_Object *object = handle->object; - - if (object->spiHandle) { - SPI_close(object->spiHandle); - object->spiHandle = NULL; - } - - if (object->lockSem) { - SemaphoreP_delete(object->lockSem); - object->lockSem = NULL; - } - - object->cardType = SD_NOCARD; - object->isOpen = false; -} - -/* - * ======== SDSPI_control ======== - */ -int_fast16_t SDSPI_control(SD_Handle handle, uint_fast16_t cmd, - void *arg) -{ - return (SD_STATUS_UNDEFINEDCMD); -} - -/* - * ======== SDSPI_getNumSectors ======== - */ -uint_fast32_t SDSPI_getNumSectors(SD_Handle handle) -{ - uint8_t n; - uint8_t csd[16]; - uint16_t csize; - uint32_t sectors = 0; - SDSPI_Object *object = handle->object; - SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; - - SemaphoreP_pend(object->lockSem, SemaphoreP_WAIT_FOREVER); - - assertCS(hwAttrs); - - /* Get number of sectors on the disk (uint32_t) */ - if ((sendCmd(object->spiHandle, CMD9, 0) == 0) && - recvDataBlock(object->spiHandle, csd, 16)) { - /* SDC ver 2.00 */ - if ((csd[0] >> 6) == 1) { - csize = csd[9] + (csd[8] << 8) + 1; - sectors = csize << 10; - } - /* MMC or SDC ver 1.XX */ - else { - n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + - ((csd[9] & 3) << 1) + 2; - - csize = (csd[8] >> 6) + ((uint16_t) csd[7] << 2) + - ((uint16_t) (csd[6] & 3) << 10) + 1; - sectors = (uint32_t)csize << (n - 9); - } - } - - deassertCS(hwAttrs); - - SemaphoreP_post(object->lockSem); - - return (sectors); -} - -/* - * ======== SDSPI_getSectorSize ======== - */ -uint_fast32_t SDSPI_getSectorSize(SD_Handle handle) -{ - return (SD_SECTOR_SIZE); -} - -/* - * ======== SDSPI_init ======== - */ -void SDSPI_init(SD_Handle handle) -{ - GPIO_init(); - SPI_init(); -} - -/* - * ======== SDSPI_initialize ======== - */ -int_fast16_t SDSPI_initialize(SD_Handle handle) -{ - SD_CardType cardType = SD_NOCARD; - uint8_t i; - uint8_t ocr[4]; - uint8_t txDummy[4] = {0xFF, 0xFF, 0xFF, 0xFF}; - int_fast16_t status; - uint32_t currentTime; - uint32_t startTime; - uint32_t timeout; - SPI_Params spiParams; - SDSPI_Object *object = handle->object; - SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; - - SemaphoreP_pend(object->lockSem, SemaphoreP_WAIT_FOREVER); - - /* - * Part of the process to initialize the SD Card to SPI mode - Do not - * assert CS during this time - */ - sendInitialClockTrain(object->spiHandle); - - /* Now select the SD Card's chip select to send CMD0 command */ - assertCS(hwAttrs); - - /* - * Send CMD0 to put the SD card in idle SPI mode. Some SD cards may not - * respond correctly to CMD0 on the first attempt; so we will try for up - * to 10 attempts (cards will usually respond correctly on the 3rd or 4th - * attempt). Failure is returned if the card does not return the correct - * response with the 10 attempts. - */ - i = 10; - do { - status = sendCmd(object->spiHandle, CMD0, 0); - } while ((status != 1) && (--i)); - - /* Proceed with initialization only if SD Card is in "Idle" state */ - if (status == 1) { - /* - * Determine what SD Card version we are dealing with - * Depending on which SD Card version, we need to send different SD - * commands to the SD Card, which will have different response fields. - */ - if (sendCmd(object->spiHandle, CMD8, 0x1AA) == 1) { - /* SD Version 2.0 or higher */ - status = spiTransfer(object->spiHandle, &ocr, &txDummy, 4); - if (status == SD_STATUS_SUCCESS) { - /* - * Ensure that the card's voltage range is valid - * The card can work at VDD range of 2.7-3.6V - */ - if ((ocr[2] == 0x01) && (ocr[3] == 0xAA)) { - /* - * Wait for data packet in timeout of 1s - status used to - * indicate if a timeout occurred before operation - * completed. - */ - status = SD_STATUS_ERROR; - timeout = 1000000/ClockP_getSystemTickPeriod(); - startTime = ClockP_getSystemTicks(); - - do { - /* ACMD41 with HCS bit */ - if ((sendCmd(object->spiHandle, CMD55, 0) <= 1) && - (sendCmd(object->spiHandle, CMD41, 1UL << 30) == 0)) { - status = SD_STATUS_SUCCESS; - break; - } - currentTime = ClockP_getSystemTicks(); - } while ((currentTime - startTime) < timeout); - - /* - * Check CCS bit to determine which type of capacity we are - * dealing with - */ - if ((status == SD_STATUS_SUCCESS) && - sendCmd(object->spiHandle, CMD58, 0) == 0) { - status = spiTransfer(object->spiHandle, &ocr, &txDummy, 4); - if (status == SD_STATUS_SUCCESS) { - cardType = (ocr[0] & 0x40) ? SD_SDHC : SD_SDSC; - } - } - } - } - } - else { - /* SDC Ver1 or MMC */ - /* - * The card version is not SDC V2+ so check if we are dealing with a - * SDC or MMC card - */ - if ((sendCmd(object->spiHandle, CMD55, 0) <= 1) && - (sendCmd(object->spiHandle, CMD41, 0) <= 1)) { - cardType = SD_SDSC; - } - else { - cardType = SD_MMC; - } - - /* - * Wait for data packet in timeout of 1s - status used to - * indicate if a timeout occurred before operation - * completed. - */ - status = SD_STATUS_ERROR; - timeout = 1000000/ClockP_getSystemTickPeriod(); - startTime = ClockP_getSystemTicks(); - do { - if (cardType == SD_SDSC) { - /* ACMD41 */ - if ((sendCmd(object->spiHandle, CMD55, 0) <= 1) && - (sendCmd(object->spiHandle, CMD41, 0) == 0)) { - status = SD_STATUS_SUCCESS; - break; - } - } - else { - /* CMD1 */ - if (sendCmd(object->spiHandle, CMD1, 0) == 0) { - status = SD_STATUS_SUCCESS; - break; - } - } - currentTime = ClockP_getSystemTicks(); - } while ((currentTime - startTime) < timeout); - - /* Select R/W block length */ - if ((status == SD_STATUS_ERROR) || - (sendCmd(object->spiHandle, CMD16, SD_SECTOR_SIZE) != 0)) { - cardType = SD_NOCARD; - } - } - } - - object->cardType = cardType; - - deassertCS(hwAttrs); - - /* Check to see if a card type was determined */ - if (cardType == SD_NOCARD) { - status = SD_STATUS_ERROR; - } - else { - /* Reconfigure the SPI to operate @ 2.5 MHz */ - SPI_close(object->spiHandle); - - SPI_Params_init(&spiParams); - spiParams.bitRate = 2500000; - object->spiHandle = SPI_open(hwAttrs->spiIndex, &spiParams); - status = (object->spiHandle == NULL) ? SD_STATUS_ERROR : - SD_STATUS_SUCCESS; - } - - SemaphoreP_post(object->lockSem); - - return (status); -} - -/* - * ======== SDSPI_open ======== - */ -SD_Handle SDSPI_open(SD_Handle handle, SD_Params *params) -{ - uintptr_t key; - SPI_Params spiParams; - SDSPI_Object *object = handle->object; - SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; - - key = HwiP_disable(); - - if (object->isOpen) { - HwiP_restore(key); - - return (NULL); - } - object->isOpen = true; - - HwiP_restore(key); - - object->lockSem = SemaphoreP_createBinary(1); - if (object->lockSem == NULL) { - object->isOpen = false; - - return (NULL); - } - - /* - * SPI is initially set to 400 kHz to perform SD initialization. This is - * is done to ensure compatibility with older SD cards. Once the card has - * been initialized (in SPI mode) the SPI peripheral will be closed & - * reopened at 2.5 MHz. - */ - SPI_Params_init(&spiParams); - spiParams.bitRate = 400000; - object->spiHandle = SPI_open(hwAttrs->spiIndex, &spiParams); - if (object->spiHandle == NULL) { - SDSPI_close(handle); - - return (NULL); - } - - /* Configure the SPI CS pin as output set high */ - GPIO_setConfig(hwAttrs->spiCsGpioIndex, - GPIO_CFG_OUT_STD | GPIO_CFG_OUT_HIGH); - - return (handle); -} - -/* - * ======== SDSPI_read ======== - */ -int_fast16_t SDSPI_read(SD_Handle handle, void *buf, int_fast32_t sector, - uint_fast32_t sectorCount) -{ - int_fast16_t status = SD_STATUS_ERROR; - SDSPI_Object *object = handle->object; - SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; - - if (sectorCount == 0) { - return (SD_STATUS_ERROR); - } - - SemaphoreP_pend(object->lockSem, SemaphoreP_WAIT_FOREVER); - - /* - * On a SDSC card, the sector address is a byte address on the SD Card - * On a SDHC card, the sector addressing is via sector blocks - */ - if (object->cardType != SD_SDHC) { - /* Convert to byte address */ - sector *= SD_SECTOR_SIZE; - } - - assertCS(hwAttrs); - - /* Single block read */ - if (sectorCount == 1) { - if ((sendCmd(object->spiHandle, CMD17, sector) == 0) && - recvDataBlock(object->spiHandle, buf, SD_SECTOR_SIZE)) { - status = SD_STATUS_SUCCESS; - } - } - /* Multiple block read */ - else { - if (sendCmd(object->spiHandle, CMD18, sector) == 0) { - do { - if (!recvDataBlock(object->spiHandle, buf, SD_SECTOR_SIZE)) { - break; - } - buf = (void *) (((uint32_t) buf) + SD_SECTOR_SIZE); - } while (--sectorCount); - - /* - * STOP_TRANSMISSION - order is important; always want to send - * stop signal - */ - if (sendCmd(object->spiHandle, CMD12, 0) == 0 && sectorCount == 0) { - status = SD_STATUS_SUCCESS; - } - } - } - - deassertCS(hwAttrs); - - SemaphoreP_post(object->lockSem); - - return (status); -} - -/* - * ======== SDSPI_write ======== - */ -int_fast16_t SDSPI_write(SD_Handle handle, const void *buf, - int_fast32_t sector, uint_fast32_t sectorCount) -{ - int_fast16_t status = SD_STATUS_SUCCESS; - SDSPI_Object *object = handle->object; - SDSPI_HWAttrs const *hwAttrs = handle->hwAttrs; - - if (sectorCount == 0) { - return (SD_STATUS_ERROR); - } - - SemaphoreP_pend(object->lockSem, SemaphoreP_WAIT_FOREVER); - - /* - * On a SDSC card, the sector address is a byte address on the SD Card - * On a SDHC card, the sector addressing is via sector blocks - */ - if (object->cardType != SD_SDHC) { - /* Convert to byte address if needed */ - sector *= SD_SECTOR_SIZE; - } - - assertCS(hwAttrs); - - /* Single block write */ - if (sectorCount == 1) { - if ((sendCmd(object->spiHandle, CMD24, sector) == 0) && - transmitDataBlock(object->spiHandle, (void *) buf, SD_SECTOR_SIZE, - START_BLOCK_TOKEN)) { - sectorCount = 0; - } - } - /* Multiple block write */ - else { - if ((object->cardType == SD_SDSC) || (object->cardType == SD_SDHC)) { - if (sendCmd(object->spiHandle, CMD55, 0) != 0) { - status = SD_STATUS_ERROR; - } - - /* ACMD23 */ - if ((status == SD_STATUS_SUCCESS) && - (sendCmd(object->spiHandle, CMD23, sectorCount) != 0)) { - status = SD_STATUS_ERROR; - } - } - - /* WRITE_MULTIPLE_BLOCK command */ - if ((status == SD_STATUS_SUCCESS) && - (sendCmd(object->spiHandle, CMD25, sector) == 0)) { - do { - if (!transmitDataBlock(object->spiHandle, (void *) buf, - SD_SECTOR_SIZE, START_MULTIBLOCK_TOKEN)) { - break; - } - buf = (void *) (((uint32_t) buf) + SD_SECTOR_SIZE); - } while (--sectorCount); - - /* STOP_TRAN token */ - if (!transmitDataBlock(object->spiHandle, NULL, 0, - STOP_MULTIBLOCK_TOKEN)) { - sectorCount = 1; - } - } - } - - deassertCS(hwAttrs); - - SemaphoreP_post(object->lockSem); - - return ((sectorCount) ? SD_STATUS_ERROR : SD_STATUS_SUCCESS); -} - -/* - * ======== assertCS ======== - */ -static inline void assertCS(SDSPI_HWAttrs const *hwAttrs) -{ - GPIO_write(hwAttrs->spiCsGpioIndex, 0); -} - -/* - * ======== deassertCS ======== - */ -static inline void deassertCS(SDSPI_HWAttrs const *hwAttrs) -{ - GPIO_write(hwAttrs->spiCsGpioIndex, 1); -} - -/* - * ======== recvDataBlock ======== - * Function to receive a block of data from the SDCard - */ -static bool recvDataBlock(SPI_Handle handle, void *buf, uint32_t count) -{ - uint8_t rxBuf[2]; - uint8_t txBuf[2] = {0xFF, 0xFF}; - int_fast16_t status; - uint32_t currentTime; - uint32_t startTime; - uint32_t timeout; - - /* - * Wait for SD card to be ready up to 1s. SD card is ready when the - * START_BLOCK_TOKEN is received. - */ - timeout = 1000000/ClockP_getSystemTickPeriod(); - startTime = ClockP_getSystemTicks(); - do { - status = spiTransfer(handle, &rxBuf, &txBuf, 1); - currentTime = ClockP_getSystemTicks(); - } while ((status == SD_STATUS_SUCCESS) && (rxBuf[0] == 0xFF) && - (currentTime - startTime) < timeout); - - if (rxBuf[0] != START_BLOCK_TOKEN) { - /* Return error if valid data token was not received */ - return (false); - } - - /* Receive the data block into buffer */ - if (spiTransfer(handle, buf, NULL, count) != SD_STATUS_SUCCESS) { - return (false); - } - - /* Read the 16 bit CRC, but discard it */ - if (spiTransfer(handle, &rxBuf, &txBuf, 2) != SD_STATUS_SUCCESS) { - return (false); - } - - /* Return with success */ - return (true); -} - -/* - * ======== sendCmd ======== - * Function to send a command to the SD card. Command responses from - * SD card are returned. (0xFF) is returned on failures. - */ -static uint8_t sendCmd(SPI_Handle handle, uint8_t cmd, uint32_t arg) -{ - uint8_t i; - uint8_t rxBuf; - uint8_t txBuf[6]; - int_fast16_t status; - - if ((cmd != CMD0) && !waitUntilReady(handle)) { - return (0xFF); - } - - /* Setup SPI transaction */ - txBuf[0] = cmd; /* Command */ - txBuf[1] = (uint8_t)(arg >> 24); /* Argument[31..24] */ - txBuf[2] = (uint8_t)(arg >> 16); /* Argument[23..16] */ - txBuf[3] = (uint8_t)(arg >> 8); /* Argument[15..8] */ - txBuf[4] = (uint8_t) arg; /* Argument[7..0] */ - - if (cmd == CMD0) { - /* CRC for CMD0(0) */ - txBuf[5] = 0x95; - } - else if (cmd == CMD8) { - /* CRC for CMD8(0x1AA) */ - txBuf[5] = 0x87; - } - else { - /* Default CRC should be at least 0x01 */ - txBuf[5] = 0x01; - } - - if (spiTransfer(handle, NULL, &txBuf, 6) != SD_STATUS_SUCCESS) { - return (0xFF); - } - - /* Prepare to receive SD card response (send 0xFF) */ - txBuf[0] = 0xFF; - - /* - * CMD 12 has R1b response which transfers an additional - * "busy" byte - */ - if ((cmd == CMD12) && - (spiTransfer(handle, &rxBuf, &txBuf, 1) != SD_STATUS_SUCCESS)) { - return (0xFF); - } - - /* Wait for a valid response; 10 attempts */ - i = 10; - do { - status = spiTransfer(handle, &rxBuf, &txBuf, 1); - } while ((status == SD_STATUS_SUCCESS) && (rxBuf & 0x80) && (--i)); - - /* Return with the response value */ - return (rxBuf); -} - -/* - * ======== sendInitialClockTrain ======== - * Function to get the SDCard into SPI mode - */ -static int_fast16_t sendInitialClockTrain(SPI_Handle handle) -{ - uint8_t txBuf[10] = { - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF - }; - - /* - * To put the SD card in SPI mode we must keep the TX line high while - * toggling the clock line several times. To do this we transmit 0xFF - * 10 times. - */ - return (spiTransfer(handle, NULL, &txBuf, 10)); -} - -/* - * ======== spiTransfer ======== - * Returns SD_STATUS_SUCCESS when transfer is completed; - * SD_STATUS_ERROR otherwise. - */ -static int_fast16_t spiTransfer(SPI_Handle handle, void *rxBuf, - void *txBuf, size_t count) { - int_fast16_t status; - SPI_Transaction transaction; - - transaction.rxBuf = rxBuf; - transaction.txBuf = txBuf; - transaction.count = count; - - status = (SPI_transfer(handle, &transaction)) ? - SD_STATUS_SUCCESS : SD_STATUS_ERROR; - - return (status); -} - -/* - * ======== transmitDataBlock ======== - * Function to transmit a block of data to the SD card. A valid command - * token must be sent to the SD card prior to sending the data block. - * The available tokens are: - * START_BLOCK_TOKEN - * START_MULTIBLOCK_TOKEN - * STOP_MULTIBLOCK_TOKEN - */ -static bool transmitDataBlock(SPI_Handle handle, void *buf, uint32_t count, - uint8_t token) -{ - uint8_t rxBuf; - uint8_t txBuf[2] = {0xFF, 0xFF}; - - if (!waitUntilReady(handle)) { - return (false); - } - - /* transmit data token */ - txBuf[0] = token; - if (spiTransfer(handle, NULL, &txBuf, 1) != SD_STATUS_SUCCESS) { - return (false); - } - - /* Send data only when token != STOP_MULTIBLOCK_TOKEN */ - if (token != STOP_MULTIBLOCK_TOKEN) { - /* Write data to the SD card */ - if (spiTransfer(handle, NULL, buf, count) != SD_STATUS_SUCCESS) { - return (false); - } - - /* Receive the 16 bit CRC, but discard it */ - txBuf[0] = (0xFF); - if (spiTransfer(handle, NULL, &txBuf, 2) != SD_STATUS_SUCCESS) { - return (false); - } - - /* Receive data response token from SD card */ - if (spiTransfer(handle, &rxBuf, &txBuf, 1) != SD_STATUS_SUCCESS) { - return (false); - } - - /* Check data response; return error if data was rejected */ - if ((rxBuf & 0x1F) != 0x05) { - return (false); - } - } - - return (true); -} - -/* - * ======== waitUntilReady ======== - * Function to check if the SD card is busy. - * - * Returns true if SD card is ready; false indicates the SD card is still busy - * & a timeout occurred. - */ -static bool waitUntilReady(SPI_Handle handle) -{ - uint8_t rxDummy; - uint8_t txDummy = 0xFF; - int_fast16_t status; - uint32_t currentTime; - uint32_t startTime; - uint32_t timeout; - - /* Wait up to 1s for data packet */ - timeout = 1000000/ClockP_getSystemTickPeriod(); - startTime = ClockP_getSystemTicks(); - do { - status = spiTransfer(handle, &rxDummy, &txDummy, 1); - currentTime = ClockP_getSystemTicks(); - } while ((status == SD_STATUS_SUCCESS) && (rxDummy != 0xFF) && - (currentTime - startTime) < timeout); - - return (rxDummy == 0xFF); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/sd/SDSPI.h b/ext/hal/ti/simplelink/source/ti/drivers/sd/SDSPI.h deleted file mode 100644 index dd10ecef332..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/sd/SDSPI.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file SDSPI.h - * - * @brief SD driver implementation built on the TI SPI driver. - * - * The SDSPI header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref SD.h for a complete description of APIs & example of use. - * - * This SD driver implementation can be used to communicate with SD cards - * via a SPI peripheral. This driver leverages the TI SPI driver to transfer - * data to/from the host processor to the SD card. The SD card chip select - * is also handled by this driver via the TI GPIO driver. Both the SPI - * driver instance & the GPIO pin (used as chip select) must be specified - * in the SDSPI hardware attributes. - * - * Note: This driver requires that the 'defaultTxBufValue' field in the SPI - * driver hardware attributes be set to '0xFF'. - * - * ## Data location & alignment # - * - * This driver relies on the TI SPI driver to configure the SPI peripheral & - * perform data transfers. This means that data to be transferred must comply - * with rules & restrictions set SPI driver (memory alignment & DMA - * accessibility requirements). Refer to @ref SPI.h & the device specific - * SPI implementation header files for details. - * - * ============================================================================ - */ - -#ifndef ti_drivers_sd_SDSPI__include -#define ti_drivers_sd_SDSPI__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include - -/* SDSPI function table */ -extern const SD_FxnTable SDSPI_fxnTable; - -/*! - * @brief SDSPI Hardware attributes - * - * The SDSPI HWAttrs configuration structure contains the index of the SPI - * peripheral to be used for data transfers & the index of the GPIO Pin which - * will act as chip select. This driver uses this information to: - * - configure & open the SPI driver instance for data transfers - * - select the SD card (via chip select) when performing data transfers - * - * @struct SDSPI_HWAttrs - * An example configuration structure could look as the following: - * @code - * const SDSPI_HWAttrs sdspiHWAttrs[1] = { - * { - * // SPI driver index - * .spiIndex = 0, - * - * // GPIO driver pin index - * .spiCsGpioIndex = 3 - * } - * }; - * @endcode - */ -typedef struct SDSPI_HWAttrs_ { - uint_least8_t spiIndex; - uint16_t spiCsGpioIndex; -} SDSPI_HWAttrs; - -/*! - * @brief SDSPI Object - * - * The application must not access any member variables of this structure! - */ -typedef struct SDSPI_Object_ { - SemaphoreP_Handle lockSem; - SPI_Handle spiHandle; - SD_CardType cardType; - bool isOpen; -} SDSPI_Object; - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_sd_SDSPI__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/spi/SPICC32XXDMA.c b/ext/hal/ti/simplelink/source/ti/drivers/spi/SPICC32XXDMA.c deleted file mode 100644 index 68fb3b550bc..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/spi/SPICC32XXDMA.c +++ /dev/null @@ -1,820 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#define MAX_DMA_TRANSFER_AMOUNT (1024) - -#define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) -#define PAD_RESET_STATE 0xC61 - -void SPICC32XXDMA_close(SPI_Handle handle); -int_fast16_t SPICC32XXDMA_control(SPI_Handle handle, uint_fast16_t cmd, - void *arg); -void SPICC32XXDMA_init(SPI_Handle handle); -SPI_Handle SPICC32XXDMA_open(SPI_Handle handle, SPI_Params *params); -bool SPICC32XXDMA_transfer(SPI_Handle handle, SPI_Transaction *transaction); -void SPICC32XXDMA_transferCancel(SPI_Handle handle); - -/* SPI function table for SPICC32XXDMA implementation */ -const SPI_FxnTable SPICC32XXDMA_fxnTable = { - SPICC32XXDMA_close, - SPICC32XXDMA_control, - SPICC32XXDMA_init, - SPICC32XXDMA_open, - SPICC32XXDMA_transfer, - SPICC32XXDMA_transferCancel -}; - -static const uint32_t mode[] = { - SPI_MODE_MASTER, - SPI_MODE_SLAVE -}; - -/* - * This lookup table is used to configure the DMA channels for the appropriate - * (8bit, 16bit or 32bit) transfer sizes. - * Table for an SPI DMA RX channel. - */ -static const uint32_t dmaRxConfig[] = { - UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 | UDMA_ARB_1, - UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_16 | UDMA_ARB_1, - UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_32 | UDMA_ARB_1 -}; - -/* - * This lookup table is used to configure the DMA channels for the appropriate - * (8bit, 16bit or 32bit) transfer sizes. - * Table for an SPI DMA TX channel - */ -static const uint32_t dmaTxConfig[] = { - UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE | UDMA_ARB_1, - UDMA_SIZE_16 | UDMA_SRC_INC_16 | UDMA_DST_INC_NONE | UDMA_ARB_1, - UDMA_SIZE_32 | UDMA_SRC_INC_32 | UDMA_DST_INC_NONE | UDMA_ARB_1 -}; - -/* - * This lookup table is used to configure the DMA channels for the appropriate - * (8bit, 16bit or 32bit) transfer sizes when either txBuf or rxBuf are NULL. - */ -static const uint32_t dmaNullConfig[] = { - UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1, - UDMA_SIZE_16 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1, - UDMA_SIZE_32 | UDMA_SRC_INC_NONE | UDMA_DST_INC_NONE | UDMA_ARB_1 -}; - -/* - * ======== blockingTransferCallback ======== - */ -static void blockingTransferCallback(SPI_Handle handle, - SPI_Transaction *transaction) -{ - SPICC32XXDMA_Object *object = handle->object; - - SemaphoreP_post(object->transferComplete); -} - -/* - * ======== configDMA ======== - * This functions configures the transmit and receive DMA channels for a given - * SPI_Handle and SPI_Transaction - */ -static void configDMA(SPICC32XXDMA_Object *object, - SPICC32XXDMA_HWAttrsV1 const *hwAttrs, SPI_Transaction *transaction) -{ - uintptr_t key; - void *buf; - uint32_t channelControlOptions; - uint8_t dataFrameSizeInBytes; - uint8_t optionsIndex; - - /* DMA options used vary according to data size. */ - if (object->dataSize < 9) { - optionsIndex = 0; - dataFrameSizeInBytes = sizeof(uint8_t); - } - else if (object->dataSize < 17) { - optionsIndex = 1; - dataFrameSizeInBytes = sizeof(uint16_t);; - } - else { - optionsIndex = 2; - dataFrameSizeInBytes = sizeof(uint32_t); - } - - /* - * The DMA has a max transfer amount of 1024. If the transaction is - * greater; we must transfer it in chunks. object->amtDataXferred has - * how much data has already been sent. - */ - if ((transaction->count - object->amtDataXferred) > MAX_DMA_TRANSFER_AMOUNT) { - object->currentXferAmt = MAX_DMA_TRANSFER_AMOUNT; - } - else { - object->currentXferAmt = (transaction->count - object->amtDataXferred); - } - - if (transaction->txBuf) { - channelControlOptions = dmaTxConfig[optionsIndex]; - /* - * Add an offset for the amount of data transfered. The offset is - * calculated by: object->amtDataXferred * (dataFrameSizeInBytes). - * This accounts for 8, 16 or 32-bit sized transfers. - */ - buf = (void *) ((uint32_t) transaction->txBuf + - ((uint32_t) object->amtDataXferred * dataFrameSizeInBytes)); - } - else { - channelControlOptions = dmaNullConfig[optionsIndex]; - *hwAttrs->scratchBufPtr = hwAttrs->defaultTxBufValue; - buf = hwAttrs->scratchBufPtr; - } - - /* Setup the TX transfer characteristics & buffers */ - MAP_uDMAChannelControlSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT, - channelControlOptions); - MAP_uDMAChannelAttributeDisable(hwAttrs->txChannelIndex, - UDMA_ATTR_ALTSELECT); - MAP_uDMAChannelTransferSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT, - UDMA_MODE_BASIC, buf, (void *) (hwAttrs->baseAddr + MCSPI_O_TX0), - object->currentXferAmt); - - if (transaction->rxBuf) { - channelControlOptions = dmaRxConfig[optionsIndex]; - /* - * Add an offset for the amount of data transfered. The offset is - * calculated by: object->amtDataXferred * (dataFrameSizeInBytes). - * This accounts for 8 or 16-bit sized transfers. - */ - buf = (void *) ((uint32_t) transaction->rxBuf + - ((uint32_t) object->amtDataXferred * dataFrameSizeInBytes)); - } - else { - channelControlOptions = dmaNullConfig[optionsIndex]; - buf = hwAttrs->scratchBufPtr; - } - - /* Setup the RX transfer characteristics & buffers */ - MAP_uDMAChannelControlSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT, - channelControlOptions); - MAP_uDMAChannelAttributeDisable(hwAttrs->rxChannelIndex, - UDMA_ATTR_ALTSELECT); - MAP_uDMAChannelTransferSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT, - UDMA_MODE_BASIC, (void *) (hwAttrs->baseAddr + MCSPI_O_RX0), buf, - object->currentXferAmt); - - /* A lock is needed because we are accessing shared uDMA memory */ - key = HwiP_disable(); - - /* - * DMA channels 30 and 31 are connected to the SPI peripheral by default. - * If someone hasn't remapped them to something else already, we remap - * them to SW. - */ - if (!(HWREG(UDMA_BASE + UDMA_O_CHMAP3) & UDMA_CHMAP3_CH30SEL_M)) { - MAP_uDMAChannelAssign(UDMA_CH30_SW); - } - if (!(HWREG(UDMA_BASE + UDMA_O_CHMAP3) & UDMA_CHMAP3_CH31SEL_M)) { - MAP_uDMAChannelAssign(UDMA_CH31_SW); - } - - /* Assign the requested DMA channels */ - MAP_uDMAChannelAssign(hwAttrs->rxChannelIndex); - MAP_uDMAChannelAssign(hwAttrs->txChannelIndex); - - /* Enable DMA to generate interrupt on SPI peripheral */ - MAP_SPIDmaEnable(hwAttrs->baseAddr, SPI_RX_DMA | SPI_TX_DMA); - MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMARX); - MAP_SPIIntEnable(hwAttrs->baseAddr, SPI_INT_DMARX); - MAP_SPIWordCountSet(hwAttrs->baseAddr, object->currentXferAmt); - - /* Enable channels & start DMA transfers */ - MAP_uDMAChannelEnable(hwAttrs->txChannelIndex); - MAP_uDMAChannelEnable(hwAttrs->rxChannelIndex); - - HwiP_restore(key); - - MAP_SPIEnable(hwAttrs->baseAddr); - MAP_SPICSEnable(hwAttrs->baseAddr); -} - -/* - * ======== getDmaRemainingXfers ======== - */ -static inline uint32_t getDmaRemainingXfers(SPICC32XXDMA_HWAttrsV1 const *hwAttrs) { - uint32_t controlWord; - tDMAControlTable *controlTable; - - controlTable = MAP_uDMAControlBaseGet(); - controlWord = controlTable[(hwAttrs->rxChannelIndex & 0x3f)].ulControl; - - return (((controlWord & UDMA_CHCTL_XFERSIZE_M) >> 4) + 1); -} - -/* - * ======== getPowerMgrId ======== - */ -static uint16_t getPowerMgrId(uint32_t baseAddr) -{ - switch (baseAddr) { - case GSPI_BASE: - return (PowerCC32XX_PERIPH_GSPI); - case LSPI_BASE: - return (PowerCC32XX_PERIPH_LSPI); - default: - return (~0); - } -} - -/* - * ======== initHw ======== - */ -static void initHw(SPICC32XXDMA_Object *object, - SPICC32XXDMA_HWAttrsV1 const *hwAttrs) -{ - /* - * SPI peripheral should remain disabled until a transfer is requested. - * This is done to prevent the RX FIFO from gathering data from other - * transfers. - */ - MAP_SPICSDisable(hwAttrs->baseAddr); - MAP_SPIDisable(hwAttrs->baseAddr); - MAP_SPIReset(hwAttrs->baseAddr); - - MAP_SPIConfigSetExpClk(hwAttrs->baseAddr, - MAP_PRCMPeripheralClockGet(hwAttrs->spiPRCM), object->bitRate, - mode[object->spiMode], object->frameFormat, - (hwAttrs->csControl | hwAttrs->pinMode | hwAttrs->turboMode | - hwAttrs->csPolarity | ((object->dataSize - 1) << 7))); - - MAP_SPIFIFOEnable(hwAttrs->baseAddr, SPI_RX_FIFO | SPI_TX_FIFO); - MAP_SPIFIFOLevelSet(hwAttrs->baseAddr, object->txFifoTrigger, - object->rxFifoTrigger); -} - -/* - * ======== postNotifyFxn ======== - */ -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - SPICC32XXDMA_Object *object = ((SPI_Handle) clientArg)->object; - SPICC32XXDMA_HWAttrsV1 const *hwAttrs = ((SPI_Handle) clientArg)->hwAttrs; - - initHw(object, hwAttrs); - - return (Power_NOTIFYDONE); -} - -/* - * ======== spiHwiFxn ======== - */ -static void spiHwiFxn(uintptr_t arg) -{ - uint32_t intFlags; - SPI_Transaction *msg; - SPICC32XXDMA_Object *object = ((SPI_Handle)arg)->object; - SPICC32XXDMA_HWAttrsV1 const *hwAttrs = ((SPI_Handle)arg)->hwAttrs; - - /* - * Although the DMATX interrupt is not used by this driver, it seems like - * it is still triggering DMA interrupts. The code below will clear & - * disable the interrupt thus reducing the amount of spurious interrupts. - */ - intFlags = MAP_SPIIntStatus(hwAttrs->baseAddr, false); - if (intFlags & SPI_INT_DMATX) { - MAP_SPIIntDisable(hwAttrs->baseAddr, SPI_INT_DMATX); - MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMATX); - } - - if (MAP_uDMAChannelIsEnabled(hwAttrs->rxChannelIndex)) { - /* DMA has not completed if the channel is still enabled */ - return; - } - - /* RX DMA channel has completed; disable peripheral */ - MAP_SPIDmaDisable(hwAttrs->baseAddr, SPI_RX_DMA | SPI_TX_DMA); - MAP_SPIIntDisable(hwAttrs->baseAddr, SPI_INT_DMARX); - MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMARX); - MAP_SPICSDisable(hwAttrs->baseAddr); - MAP_SPIDisable(hwAttrs->baseAddr); - - if (object->transaction->count - object->amtDataXferred > - MAX_DMA_TRANSFER_AMOUNT) { - /* Data still remaining, configure another DMA transfer */ - object->amtDataXferred += object->currentXferAmt; - - configDMA(object, hwAttrs, object->transaction); - } - else { - /* All data sent; set status, perform callback & return */ - object->transaction->status = SPI_TRANSFER_COMPLETED; - - /* Release constraint since transaction is done */ - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* - * Use a temporary transaction pointer in case the callback function - * attempts to perform another SPI_transfer call - */ - msg = object->transaction; - - /* Indicate we are done with this transfer */ - object->transaction = NULL; - - object->transferCallbackFxn((SPI_Handle) arg, msg); - } -} - -/* - * ======== spiPollingTransfer ======== - */ -static inline void spiPollingTransfer(SPICC32XXDMA_Object *object, - SPICC32XXDMA_HWAttrsV1 const *hwAttrs, SPI_Transaction *transaction) -{ - uint8_t increment; - uint32_t dummyBuffer; - size_t transferCount; - void *rxBuf; - void *txBuf; - - if (transaction->rxBuf) { - rxBuf = transaction->rxBuf; - } - else { - rxBuf = hwAttrs->scratchBufPtr; - } - - if (transaction->txBuf) { - txBuf = transaction->txBuf; - } - else { - *hwAttrs->scratchBufPtr = hwAttrs->defaultTxBufValue; - txBuf = hwAttrs->scratchBufPtr; - } - - if (object->dataSize < 9) { - increment = sizeof(uint8_t); - } - else if (object->dataSize < 17) { - increment = sizeof(uint16_t); - } - else { - increment = sizeof(uint32_t); - } - - transferCount = transaction->count; - - /* - * Start the polling transfer - we MUST set word count to 0; not doing so - * will raise spurious RX interrupts flags (though interrupts are not - * enabled). - */ - MAP_SPIWordCountSet(hwAttrs->baseAddr, 0); - MAP_SPIEnable(hwAttrs->baseAddr); - MAP_SPICSEnable(hwAttrs->baseAddr); - - while (transferCount--) { - if (object->dataSize < 9) { - MAP_SPIDataPut(hwAttrs->baseAddr, *((uint8_t *) txBuf)); - MAP_SPIDataGet(hwAttrs->baseAddr, (unsigned long *)&dummyBuffer); - *((uint8_t *) rxBuf) = (uint8_t) dummyBuffer; - } - else if (object->dataSize < 17) { - MAP_SPIDataPut(hwAttrs->baseAddr, *((uint16_t *) txBuf)); - MAP_SPIDataGet(hwAttrs->baseAddr, (unsigned long *) &dummyBuffer); - *((uint16_t *) rxBuf) = (uint16_t) dummyBuffer; - } - else { - MAP_SPIDataPut(hwAttrs->baseAddr, *((uint32_t *) txBuf)); - MAP_SPIDataGet(hwAttrs->baseAddr, (unsigned long * ) rxBuf); - } - - /* Only increment source & destination if buffers were provided */ - if (transaction->rxBuf) { - rxBuf = (void *) (((uint32_t) rxBuf) + increment); - } - if (transaction->txBuf) { - txBuf = (void *) (((uint32_t) txBuf) + increment); - } - } - - MAP_SPICSDisable(hwAttrs->baseAddr); - MAP_SPIDisable(hwAttrs->baseAddr); -} - -/* - * ======== SPICC32XXDMA_close ======== - */ -void SPICC32XXDMA_close(SPI_Handle handle) -{ - uint32_t padRegister; - SPICC32XXDMA_Object *object = handle->object; - SPICC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - MAP_SPICSDisable(hwAttrs->baseAddr); - MAP_SPIDisable(hwAttrs->baseAddr); - MAP_SPIFIFODisable(hwAttrs->baseAddr, SPI_RX_FIFO | SPI_TX_FIFO); - - /* Release power dependency on SPI. */ - Power_releaseDependency(getPowerMgrId(hwAttrs->baseAddr)); - Power_unregisterNotify(&(object->notifyObj)); - - if (object->hwiHandle) { - HwiP_delete(object->hwiHandle); - object->hwiHandle = NULL; - } - if (object->transferComplete) { - SemaphoreP_delete(object->transferComplete); - object->transferComplete = NULL; - } - - if (object->dmaHandle) { - UDMACC32XX_close(object->dmaHandle); - object->dmaHandle = NULL; - } - - /* Restore pin pads to their reset states */ - if (hwAttrs->mosiPin != SPICC32XXDMA_PIN_NO_CONFIG) { - padRegister = (PinToPadGet((hwAttrs->mosiPin) & 0xff)<<2) - + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - } - if (hwAttrs->misoPin != SPICC32XXDMA_PIN_NO_CONFIG) { - padRegister = (PinToPadGet((hwAttrs->misoPin) & 0xff)<<2) - + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - } - if (hwAttrs->clkPin != SPICC32XXDMA_PIN_NO_CONFIG) { - padRegister = (PinToPadGet((hwAttrs->clkPin) & 0xff)<<2) - + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - } - if ((hwAttrs->pinMode == SPI_4PIN_MODE) && - (hwAttrs->csPin != SPICC32XXDMA_PIN_NO_CONFIG)) { - padRegister = (PinToPadGet((hwAttrs->csPin) & 0xff)<<2) - + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - } - - object->isOpen = false; -} - -/* - * ======== SPICC32XXDMA_control ======== - */ -int_fast16_t SPICC32XXDMA_control(SPI_Handle handle, uint_fast16_t cmd, void *arg) -{ - return (SPI_STATUS_UNDEFINEDCMD); -} - -/* - * ======== SPICC32XXDMA_init ======== - */ -void SPICC32XXDMA_init(SPI_Handle handle) -{ - UDMACC32XX_init(); -} - -/* - * ======== SPICC32XXDMA_open ======== - */ -SPI_Handle SPICC32XXDMA_open(SPI_Handle handle, SPI_Params *params) -{ - uintptr_t key; - uint16_t pin; - uint16_t mode; - uint8_t powerMgrId; - HwiP_Params hwiParams; - SPICC32XXDMA_Object *object = handle->object; - SPICC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - key = HwiP_disable(); - - if (object->isOpen) { - HwiP_restore(key); - - return (NULL); - } - object->isOpen = true; - - HwiP_restore(key); - - /* SPI_TI & SPI_MW are not supported */ - if (params->frameFormat == SPI_TI || params->frameFormat == SPI_MW) { - object->isOpen = false; - - return (NULL); - } - - /* Register power dependency - i.e. power up and enable clock for SPI. */ - powerMgrId = getPowerMgrId(hwAttrs->baseAddr); - if (powerMgrId > PowerCC32XX_NUMRESOURCES) { - object->isOpen = false; - - return (NULL); - } - Power_setDependency(powerMgrId); - Power_registerNotify(&(object->notifyObj), PowerCC32XX_AWAKE_LPDS, - postNotifyFxn, (uintptr_t) handle); - - /* Configure the pins */ - if (hwAttrs->mosiPin != SPICC32XXDMA_PIN_NO_CONFIG) { - pin = (hwAttrs->mosiPin) & 0xff; - mode = (hwAttrs->mosiPin >> 8) & 0xff; - MAP_PinTypeSPI((unsigned long) pin, (unsigned long) mode); - } - - if (hwAttrs->misoPin != SPICC32XXDMA_PIN_NO_CONFIG) { - pin = (hwAttrs->misoPin) & 0xff; - mode = (hwAttrs->misoPin >> 8) & 0xff; - MAP_PinTypeSPI((unsigned long) pin, (unsigned long) mode); - } - - if (hwAttrs->clkPin != SPICC32XXDMA_PIN_NO_CONFIG) { - pin = (hwAttrs->clkPin) & 0xff; - mode = (hwAttrs->clkPin >> 8) & 0xff; - MAP_PinTypeSPI((unsigned long) pin, (unsigned long) mode); - } - - if (hwAttrs->pinMode == SPI_4PIN_MODE) { - if (hwAttrs->csPin != SPICC32XXDMA_PIN_NO_CONFIG) { - pin = (hwAttrs->csPin) & 0xff; - mode = (hwAttrs->csPin >> 8) & 0xff; - MAP_PinTypeSPI((unsigned long) pin, (unsigned long) mode); - } - } - - object->dmaHandle = UDMACC32XX_open(); - if (object->dmaHandle == NULL) { - SPICC32XXDMA_close(handle); - - return (NULL); - } - - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t) handle; - hwiParams.priority = hwAttrs->intPriority; - object->hwiHandle = HwiP_create(hwAttrs->intNum, spiHwiFxn, &hwiParams); - if (object->hwiHandle == NULL) { - SPICC32XXDMA_close(handle); - - return (NULL); - } - - if (params->transferMode == SPI_MODE_BLOCKING) { - /* - * Create a semaphore to block task execution for the duration of the - * SPI transfer - */ - object->transferComplete = SemaphoreP_createBinary(0); - if (object->transferComplete == NULL) { - SPICC32XXDMA_close(handle); - - return (NULL); - } - - object->transferCallbackFxn = blockingTransferCallback; - } - else { - if (params->transferCallbackFxn == NULL) { - SPICC32XXDMA_close(handle); - - return (NULL); - } - - object->transferCallbackFxn = params->transferCallbackFxn; - } - - object->bitRate = params->bitRate; - object->dataSize = params->dataSize; - object->frameFormat = params->frameFormat; - object->spiMode = params->mode; - object->transaction = NULL; - object->transferMode = params->transferMode; - object->transferTimeout = params->transferTimeout; - - /* SPI FIFO trigger sizes vary based on data frame size */ - if (object->dataSize < 9) { - object->rxFifoTrigger = sizeof(uint8_t); - object->txFifoTrigger = sizeof(uint8_t); - } - else if (object->dataSize < 17) { - object->rxFifoTrigger = sizeof(uint16_t); - object->txFifoTrigger = sizeof(uint16_t); - } - else { - object->rxFifoTrigger = sizeof(uint32_t); - object->txFifoTrigger = sizeof(uint32_t); - } - - initHw(object, hwAttrs); - - return (handle); -} - -/* - * ======== SPICC32XXDMA_transfer ======== - */ -bool SPICC32XXDMA_transfer(SPI_Handle handle, SPI_Transaction *transaction) -{ - uintptr_t key; - uint8_t alignMask; - bool buffersAligned; - SPICC32XXDMA_Object *object = handle->object; - SPICC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - if ((transaction->count == 0) || - (transaction->rxBuf == NULL && transaction->txBuf == NULL) || - (hwAttrs->scratchBufPtr == NULL && (transaction->rxBuf == NULL || - transaction->txBuf == NULL))) { - return (false); - } - - key = HwiP_disable(); - - /* - * alignMask is used to determine if the RX/TX buffers addresses are - * aligned to the data frame size. - */ - alignMask = (object->rxFifoTrigger - 1); - buffersAligned = ((((uint32_t) transaction->rxBuf & alignMask) == 0) && - (((uint32_t) transaction->txBuf & alignMask) == 0)); - - if (object->transaction) { - HwiP_restore(key); - - return (false); - } - else { - object->transaction = transaction; - object->transaction->status = SPI_TRANSFER_STARTED; - object->amtDataXferred = 0; - object->currentXferAmt = 0; - } - - HwiP_restore(key); - - /* Set constraints to guarantee transaction */ - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* Polling transfer if BLOCKING mode & transaction->count < threshold */ - if ((object->transferMode == SPI_MODE_BLOCKING && - transaction->count < hwAttrs->minDmaTransferSize) || !buffersAligned) { - spiPollingTransfer(object, hwAttrs, transaction); - - /* Transaction completed; set status & mark SPI ready */ - object->transaction->status = SPI_TRANSFER_COMPLETED; - object->transaction = NULL; - - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - } - else { - /* Perform a DMA backed SPI transfer */ - configDMA(object, hwAttrs, transaction); - - if (object->transferMode == SPI_MODE_BLOCKING) { - if (SemaphoreP_pend(object->transferComplete, - object->transferTimeout) != SemaphoreP_OK) { - /* Timeout occurred; cancel the transfer */ - object->transaction->status = SPI_TRANSFER_FAILED; - SPICC32XXDMA_transferCancel(handle); - - /* - * TransferCancel() performs callback which posts - * transferComplete semaphore. This call consumes this extra post. - */ - SemaphoreP_pend(object->transferComplete, SemaphoreP_NO_WAIT); - - return (false); - } - } - } - - return (true); -} - -/* - * ======== SPICC32XXDMA_transferCancel ======== - */ -void SPICC32XXDMA_transferCancel(SPI_Handle handle) -{ - uintptr_t key; - SPI_Transaction *msg; - SPICC32XXDMA_Object *object = handle->object; - SPICC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - /* - * There are 2 use cases in which to call transferCancel(): - * 1. The driver is in CALLBACK mode. - * 2. The driver is in BLOCKING mode & there has been a transfer timeout. - */ - if (object->transferMode == SPI_MODE_CALLBACK || - object->transaction->status == SPI_TRANSFER_FAILED) { - - key = HwiP_disable(); - - if (object->transaction == NULL || object->cancelInProgress) { - HwiP_restore(key); - - return; - } - object->cancelInProgress = true; - - /* Prevent interrupt from occurring while canceling the transfer */ - HwiP_disableInterrupt(hwAttrs->intNum); - HwiP_clearInterrupt(hwAttrs->intNum); - - /* Clear DMA configuration */ - MAP_uDMAChannelDisable(hwAttrs->rxChannelIndex); - MAP_uDMAChannelDisable(hwAttrs->txChannelIndex); - - MAP_SPIIntDisable(hwAttrs->baseAddr, SPI_INT_DMARX); - MAP_SPIIntClear(hwAttrs->baseAddr, SPI_INT_DMARX); - MAP_SPIDmaDisable(hwAttrs->baseAddr, SPI_RX_DMA | SPI_TX_DMA); - - HwiP_restore(key); - - /* - * Disables peripheral, clears all registers & reinitializes it to - * parameters used in SPI_open() - */ - initHw(object, hwAttrs); - - HwiP_enableInterrupt(hwAttrs->intNum); - - /* - * Calculate amount of data which has already been sent & store - * it in transaction->count - */ - object->transaction->count = object->amtDataXferred + - (object->currentXferAmt - getDmaRemainingXfers(hwAttrs)); - - /* Set status CANCELED if we did not cancel due to timeout */ - if (object->transaction->status == SPI_TRANSFER_STARTED) { - object->transaction->status = SPI_TRANSFER_CANCELED; - } - - /* Release constraint set during transaction */ - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* - * Use a temporary transaction pointer in case the callback function - * attempts to perform another SPI_transfer call - */ - msg = object->transaction; - - /* Indicate we are done with this transfer */ - object->transaction = NULL; - object->cancelInProgress = false; - object->transferCallbackFxn(handle, msg); - } -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/spi/SPICC32XXDMA.h b/ext/hal/ti/simplelink/source/ti/drivers/spi/SPICC32XXDMA.h deleted file mode 100644 index 260941b9597..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/spi/SPICC32XXDMA.h +++ /dev/null @@ -1,352 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file SPICC32XXDMA.h - * - * @brief SPI driver implementation for a CC32XX SPI controller using the - * micro DMA controller. - * - * The SPI header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref SPI.h for a complete description of APIs & example of use. - * - * This SPI driver implementation is designed to operate on a CC32XX SPI - * controller using a micro DMA controller. - * - * @warning This driver does not support queueing multiple SPI transactions. - * - * ## Frame Formats # - * This SPI controller supports 4 phase & polarity formats. Refer to the device - * specific data sheets & technical reference manuals for specifics on each - * format. - * - * ## SPI Chip Select # - * This SPI controller supports a hardware chip select pin. Refer to the - * device's user manual on how this hardware chip select pin behaves in regards - * to the SPI frame format. - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - * - *
Chip select typeSPI_MASTER modeSPI_SLAVE mode
Hardware chip selectNo action is needed by the application to select the peripheral.See the device documentation on it's chip select requirements.
Software chip selectThe application is responsible to ensure that correct SPI slave is - * selected before performing a SPI_transfer().See the device documentation on it's chip select requirements.
- * - * ## SPI data frames # - * SPI data frames can be any size from 4-bits to 32-bits. The SPI data - * frame size is set in ::SPI_Params.dataSize passed to SPI_open. - * The SPICC32XXDMA driver implementation makes assumptions on the element - * size of the ::SPI_Transaction txBuf and rxBuf arrays, based on the data - * frame size. If the data frame size is less than or equal to 8 bits, - * txBuf and rxBuf are assumed to be arrays of 8-bit uint8_t elements. - * If the data frame size is greater than 8 bits, but less than or equal - * to 16 bits, txBuf and rxBuf are assumed to be arrays of 16-bit uint16_t - * elements. Otherwise, txBuf and rxBuf are assumed to point to 32-bit - * uint32_t elements. - * - * data frame size | buffer element size | - * -------------- | ------------------- | - * 4-8 bits | uint8_t | - * 9-16 bits | uint16_t | - * 17-32 bits | uint32_t | - * - * Data buffers in transactions (rxBuf & txBuf) must be address aligned - * according to the data frame size. For example, if data frame is 9-bit - * (driver assumes buffers are uint16_t) rxBuf & txBuf must be aligned - * on a 16-bit address boundary, if data frame is 20-bit (driver assumes - * buffers are uint32_t) rxBuf & txBuf must be aligned on a 32-bit address - * boundary. - * - * ## DMA Interrupts # - * This driver is designed to operate with the micro DMA. The micro DMA - * generates an interrupt on the perpheral's interrupt vector. This - * implementation automatically installs a DMA aware hardware ISR to service - * the assigned micro DMA channels. - * - * ## DMA accessible memory # - * As this driver uses uDMA to transfer data/from data buffers, it is the - * responsibility of the application to ensure that these buffers reside in - * memory that is accessible by the DMA. - * - * ## Scratch Buffers # - * A uint32_t scratch buffer is used to allow SPI_transfers where txBuf or - * rxBuf are NULL. Rather than requiring txBuf or rxBuf to have a dummy buffer - * of size of the transfer count, a single DMA accessible uint32_t scratch - * buffer is used. When rxBuf is NULL, the uDMA will transfer all the SPI data - * receives into the scratch buffer as a "bit-bucket". When txBuf is NULL, the - * scratch buffer is initialized to defaultTxBufValue so the uDMA will send - * some known value. Each SPI driver instance must have its own scratch buffer. - * - * ## Polling SPI transfers # - * When used in blocking mode small SPI transfers are can be done by polling - * the peripheral & sending data frame-by-frame. This will not block the task - * which requested the transfer, but instead immediately perform the transfer - * & return. The minDmaTransferSize field in the hardware attributes is - * the threshold; if the transaction count is below the threshold a polling - * transfer is performed; otherwise a DMA transfer is done. This is intended - * to reduce the overhead of setting up a DMA transfer to only send a few - * data frames. Keep in mind that during polling transfers the current task - * is still being executed; there is no context switch to another task. - ******************************************************************************* - */ - -#ifndef ti_drivers_spi_SPICC32XXDMA__include -#define ti_drivers_spi_SPICC32XXDMA__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include -#include -#include - -/** - * @addtogroup SPI_STATUS - * SPICC32XXDMA_STATUS_* macros are command codes only defined in the - * SPICC32XXDMA.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add SPICC32XXDMA_STATUS_* macros here */ - -/** @}*/ - -/** - * @addtogroup SPI_CMD - * SPICC32XXDMA_CMD_* macros are command codes only defined in the - * SPICC32XXDMA.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add SPICC32XXDMA_CMD_* macros here */ - -/** @}*/ - -/* - * Macros defining possible SPI signal pin mux options - * - * The lower 8 bits of the macro refer to the pin, offset by 1, to match - * driverlib pin defines. For example, SPICC32XXDMA_PIN_05_CLK & 0xff = 4, - * which equals PIN_05 in driverlib pin.h. By matching the PIN_xx defines in - * driverlib pin.h, we can pass the pin directly to the driverlib functions. - * The upper 8 bits of the macro correspond to the pin mux confg mode - * value for the pin to operate in the SPI mode. - * - * PIN_62 is special for the SDSPI driver when using an SD BoosterPack, - * as PIN_62 doesn't have an assigned SPI function yet the SD BoosterPack - * has it tied to the CS signal. - */ -#define SPICC32XXDMA_PIN_05_CLK 0x0704 /*!< PIN 5 is used for SPI CLK */ -#define SPICC32XXDMA_PIN_06_MISO 0x0705 /*!< PIN 6 is used for MISO */ -#define SPICC32XXDMA_PIN_07_MOSI 0x0706 /*!< PIN 7 is used for MOSI */ -#define SPICC32XXDMA_PIN_08_CS 0x0707 /*!< PIN 8 is used for CS */ -#define SPICC32XXDMA_PIN_45_CLK 0x072C /*!< PIN 45 is used for SPI CLK */ -#define SPICC32XXDMA_PIN_50_CS 0x0931 /*!< PIN 50 is used for CS */ -#define SPICC32XXDMA_PIN_52_MOSI 0x0833 /*!< PIN 52 is used for MOSI */ -#define SPICC32XXDMA_PIN_53_MISO 0x0734 /*!< PIN 53 is used for MISO */ - -/*! - * @brief Indicates a pin is not to be configured by the SPICC32XXDMA driver. - */ -#define SPICC32XXDMA_PIN_NO_CONFIG 0xFFFF - -/* SPI function table pointer */ -extern const SPI_FxnTable SPICC32XXDMA_fxnTable; - -/*! - * @brief SPICC32XXDMA Hardware attributes - * - * These fields, with the exception of intPriority, - * are used by driverlib APIs and therefore must be populated by - * driverlib macro definitions. For CCWare these definitions are found in: - * - driverlib/prcm.h - * - driverlib/spi.h - * - driverlib/udma.h - * - inc/hw_memmap.h - * - inc/hw_ints.h - * - * intPriority is the SPI peripheral's interrupt priority, as defined by the - * underlying OS. It is passed unmodified to the underlying OS's interrupt - * handler creation code, so you need to refer to the OS documentation - * for usage. For example, for SYS/BIOS applications, refer to the - * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of - * interrupt priorities. If the driver uses the ti.dpl interface - * instead of making OS calls directly, then the HwiP port handles the - * interrupt priority in an OS specific way. In the case of the SYS/BIOS - * port, intPriority is passed unmodified to Hwi_create(). - * - * A sample structure is shown below: - * @code - * #if defined(__TI_COMPILER_VERSION__) - * #pragma DATA_ALIGN(scratchBuf, 32) - * #elif defined(__IAR_SYSTEMS_ICC__) - * #pragma data_alignment=32 - * #elif defined(__GNUC__) - * __attribute__ ((aligned (32))) - * #endif - * uint32_t scratchBuf; - * - * const SPICC32XXDMA_HWAttrsV1 SPICC32XXDMAHWAttrs[] = { - * { - * .baseAddr = GSPI_BASE, - * .intNum = INT_GSPI, - * .intPriority = (~0), - * .spiPRCM = PRCM_GSPI, - * .csControl = SPI_HW_CTRL_CS, - * .csPolarity = SPI_CS_ACTIVELOW, - * .pinMode = SPI_4PIN_MODE, - * .turboMode = SPI_TURBO_OFF, - * .scratchBufPtr = &scratchBuf, - * .defaultTxBufValue = 0, - * .rxChannelIndex = UDMA_CH6_GSPI_RX, - * .txChannelIndex = UDMA_CH7_GSPI_TX, - * .minDmaTransferSize = 100, - * .mosiPin = SPICC32XXDMA_PIN_07_MOSI, - * .misoPin = SPICC32XXDMA_PIN_06_MISO, - * .clkPin = SPICC32XXDMA_PIN_05_CLK, - * .csPin = SPICC32XXDMA_PIN_08_CS, - * }, - * ... - * }; - * @endcode - */ -typedef struct SPICC32XXDMA_HWAttrsV1 { - /*! SPICC32XXDMA Peripheral's base address */ - uint32_t baseAddr; - - /*! SPICC32XXDMA Peripheral's interrupt vector */ - uint32_t intNum; - - /*! SPICC32XXDMA Peripheral's interrupt priority */ - uint32_t intPriority; - - /*! SPI PRCM peripheral number */ - uint32_t spiPRCM; - - /*! Specify if chip select line will be controlled by SW or HW */ - uint32_t csControl; - - uint32_t csPolarity; - - /*! Set peripheral to work in 3-pin or 4-pin mode */ - uint32_t pinMode; - - /*! Enable or disable SPI TURBO mode */ - uint32_t turboMode; - - /*! Address of a scratch buffer of size uint32_t */ - uint32_t *scratchBufPtr; - - /*! Default TX value if txBuf == NULL */ - uint32_t defaultTxBufValue; - - /*! uDMA RX channel index */ - uint32_t rxChannelIndex; - - /*! uDMA TX channel index */ - uint32_t txChannelIndex; - - /*! Minimum amout of data to start a uDMA transfer */ - uint32_t minDmaTransferSize; - - /*! GSPI MOSI pin assignment */ - uint16_t mosiPin; - - /*! GSPI MISO pin assignment */ - uint16_t misoPin; - - /*! GSPI CLK pin assignment */ - uint16_t clkPin; - - /*! GSPI CS pin assignment */ - uint16_t csPin; -} SPICC32XXDMA_HWAttrsV1; - -/*! - * @brief SPICC32XXDMA Object - * - * The application must not access any member variables of this structure! - */ -typedef struct SPICC32XXDMA_Object { - HwiP_Handle hwiHandle; - Power_NotifyObj notifyObj; - SemaphoreP_Handle transferComplete; - SPI_CallbackFxn transferCallbackFxn; - SPI_Transaction *transaction; - UDMACC32XX_Handle dmaHandle; - - size_t amtDataXferred; - size_t currentXferAmt; - uint32_t bitRate; - uint32_t dataSize; - uint32_t transferTimeout; - - SPI_Mode spiMode; - SPI_TransferMode transferMode; - SPI_FrameFormat frameFormat; - - bool cancelInProgress; - bool isOpen; - uint8_t rxFifoTrigger; - uint8_t txFifoTrigger; -} SPICC32XXDMA_Object, *SPICC32XXDMA_Handle; - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_spi_SPICC32XXDMA__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/timer/TimerCC32XX.c b/ext/hal/ti/simplelink/source/ti/drivers/timer/TimerCC32XX.c deleted file mode 100644 index 99aef26a54b..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/timer/TimerCC32XX.c +++ /dev/null @@ -1,605 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -/* - * This macro is used to determine a logical shift value for the - * timerState.bitMask. Each timer peripheral occupies two bits in - * timerState.bitMask. - * - * The timer peripherals' base addresses have an offset of 0x1000 starting at - * 0x40030000. That byte is masked using 0xF000 which can result in a value - * ranging from 0x0000 to 0x3000 for this particular hardware instance. This - * value is then shifted right by 12 into the LSB. Lastly, the value is - * multiplied by two because there are two bits in the timerState.bitMask for - * each timer. The value returned is used for the logical shift. - */ -#define timerMaskShift(baseAddress) ((((baseAddress) & 0XF000) >> 12) * 2) - -void TimerCC32XX_close(Timer_Handle handle); -int_fast16_t TimerCC32XX_control(Timer_Handle handle, - uint_fast16_t cmd, void *arg); -uint32_t TimerCC32XX_getCount(Timer_Handle handle); -void TimerCC32XX_init(Timer_Handle handle); -Timer_Handle TimerCC32XX_open(Timer_Handle handle, Timer_Params *params); -int32_t TimerCC32XX_start(Timer_Handle handle); -void TimerCC32XX_stop(Timer_Handle handle); - -/* Internal static Functions */ -static void initHw(Timer_Handle handle); -static void getPrescaler(Timer_Handle handle); -static uint32_t getPowerMgrId(uint32_t baseAddress); -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg); -static void TimerCC32XX_hwiIntFunction(uintptr_t arg); - -/* Function table for TimerCC32XX implementation */ -const Timer_FxnTable TimerCC32XX_fxnTable = { - .closeFxn = TimerCC32XX_close, - .openFxn = TimerCC32XX_open, - .startFxn = TimerCC32XX_start, - .stopFxn = TimerCC32XX_stop, - .initFxn = TimerCC32XX_init, - .getCountFxn = TimerCC32XX_getCount, - .controlFxn = TimerCC32XX_control -}; - -/* - * Internal Timer status structure - * - * bitMask: Each timer peripheral occupies two bits in the bitMask. The least - * significant bit represents the first half width timer, TimerCC32XX_timer16A - * and the most significant bit represents the second half width timer, - * TimerCC32XX_timer16B. If the full width timer, TimerCC32XX_timer32, is used, - * both bits are set to 1. - - * 31 - 8 7 - 6 5 - 4 3 - 2 1 - 0 - * ------------------------------------------------ - * | Reserved | Timer3 | Timer2 | Timer1 | Timer0 | - * ------------------------------------------------ - */ -static struct { - uint32_t bitMask; -} timerState; - -/* - * ======== initHw ======== - */ -static void initHw(Timer_Handle handle) -{ - TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - TimerCC32XX_Object const *object = handle->object; - - /* Ensure the timer is disabled */ - TimerDisable(hwAttrs->baseAddress, object->timer); - - if (object->timer == TIMER_A) { - - HWREG(hwAttrs->baseAddress + TIMER_O_TAMR) = TIMER_TAMR_TAMR_PERIOD; - } - else { - - HWREG(hwAttrs->baseAddress + TIMER_O_TBMR) = TIMER_TBMR_TBMR_PERIOD; - } - - if (hwAttrs->subTimer == TimerCC32XX_timer32) { - - HWREG(hwAttrs->baseAddress + TIMER_O_CFG) = TIMER_CFG_32_BIT_TIMER; - } - else { - - HWREG(hwAttrs->baseAddress + TIMER_O_CFG) = TIMER_CFG_16_BIT; - } - - /* Disable all interrupts */ - HWREG(hwAttrs->baseAddress + TIMER_O_IMR) = ~object->timer; - - /* Writing the PSR Register has no effect for full width 32-bit mode */ - TimerPrescaleSet(hwAttrs->baseAddress, object->timer, object->prescaler); - TimerLoadSet(hwAttrs->baseAddress, object->timer, object->period); - - /* This function controls the stall response for the timer. When true, - * the timer stops counting if the processor enters debug mode. The - * default setting for the hardware is false. - */ - TimerControlStall(hwAttrs->baseAddress, object->timer, true); -} - -/* - * ========= getPrescaler ========= - * This function calculates the prescaler and timer interval load register - * for a half timer. The handle is assumed to contain a object->period which - * represents the number of clock cycles in the desired period. The calling - * function, TimerCC32XX_open() checks for overflow before calling this function. - * Therefore, this function is guaranteed to never fail. - */ -static void getPrescaler(Timer_Handle handle) -{ - TimerCC32XX_Object *object = handle->object; - uint32_t bestDiff = ~0, bestPsr = 0, bestIload = 0; - uint32_t diff, intervalLoad, prescaler; - - /* Loop over the 8-bit prescaler */ - for (prescaler = 1; prescaler < 256; prescaler++) { - - /* Calculate timer interval load */ - intervalLoad = object->period / (prescaler + 1); - - /* Will this fit in 16-bits? */ - if (intervalLoad > (uint16_t) ~0) { - continue; - } - - /* How close is the intervalLoad to what we actually want? */ - diff = object->period - intervalLoad * (prescaler + 1); - - /* If it is closer to what we want */ - if (diff <= bestDiff) { - - /* If its a perfect match */ - if (diff == 0) { - object->period = intervalLoad; - object->prescaler = prescaler; - - return; - } - - /* Snapshot in case we don't find something better */ - bestDiff = diff; - bestPsr = prescaler; - bestIload = intervalLoad; - } - } - - /* Never found a perfect match, settle for the best */ - object->period = bestIload; - object->prescaler = bestPsr; -} - -/* - * ======== getPowerMgrId ======== - */ -static uint32_t getPowerMgrId(uint32_t baseAddress) -{ - switch (baseAddress) { - - case TIMERA0_BASE: - - return (PowerCC32XX_PERIPH_TIMERA0); - - case TIMERA1_BASE: - - return (PowerCC32XX_PERIPH_TIMERA1); - - case TIMERA2_BASE: - - return (PowerCC32XX_PERIPH_TIMERA2); - - case TIMERA3_BASE: - - return (PowerCC32XX_PERIPH_TIMERA3); - - default: - - return ((uint32_t) -1); - } -} - -/* - * ======== postNotifyFxn ======== - * This functions is called when a transition from LPDS mode is made. - * clientArg should be a handle of a previously opened Timer instance. - */ -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - initHw((Timer_Handle) clientArg); - - return (Power_NOTIFYDONE); -} - -/* - * ======== TimerCC32XX_allocateTimerResource ======== - */ -bool TimerCC32XX_allocateTimerResource(uint32_t baseAddress, - TimerCC32XX_SubTimer subTimer) -{ - uintptr_t key; - uint32_t mask; - uint32_t powerMgrId; - bool status; - - powerMgrId = getPowerMgrId(baseAddress); - - if (powerMgrId == (uint32_t) -1) { - - return (false); - } - - mask = subTimer << timerMaskShift(baseAddress); - - key = HwiP_disable(); - - if (timerState.bitMask & mask) { - - status = false; - } - else { - - Power_setDependency(powerMgrId); - timerState.bitMask = timerState.bitMask | mask; - status = true; - } - - HwiP_restore(key); - - return (status); -} - -/* - * ======== TimerCC32XX_close ======== - */ -void TimerCC32XX_close(Timer_Handle handle) -{ - TimerCC32XX_Object *object = handle->object; - TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - - /* Stopping the Timer before closing it */ - TimerCC32XX_stop(handle); - - Power_unregisterNotify(&(object->notifyObj)); - - if (object->hwiHandle) { - - HwiP_clearInterrupt(hwAttrs->intNum); - HwiP_delete(object->hwiHandle); - object->hwiHandle = NULL; - } - - if (object->timerSem) { - - SemaphoreP_delete(object->timerSem); - object->timerSem = NULL; - } - - TimerCC32XX_freeTimerResource(hwAttrs->baseAddress, hwAttrs->subTimer); -} - -/* - * ======== TimerCC32XX_control ======== - */ -int_fast16_t TimerCC32XX_control(Timer_Handle handle, - uint_fast16_t cmd, void *arg) -{ - return (Timer_STATUS_UNDEFINEDCMD); -} - -/* - * ======== TimerCC32XX_freeTimerResource ======== - */ -void TimerCC32XX_freeTimerResource(uint32_t baseAddress, - TimerCC32XX_SubTimer subTimer) -{ - uintptr_t key; - uint32_t mask; - - mask = subTimer << timerMaskShift(baseAddress); - - key = HwiP_disable(); - - timerState.bitMask = (timerState.bitMask & ~mask); - - Power_releaseDependency(getPowerMgrId(baseAddress)); - - HwiP_restore(key); -} - -/* - * ======== TimerCC32XX_getCount ======== - */ -uint32_t TimerCC32XX_getCount(Timer_Handle handle) -{ - TimerCC32XX_HWAttrs const *hWAttrs = handle->hwAttrs; - TimerCC32XX_Object const *object = handle->object; - uint32_t count; - - if (object->timer == TIMER_A) { - count = HWREG(hWAttrs->baseAddress + TIMER_O_TAR); - } - else { - count = HWREG(hWAttrs->baseAddress + TIMER_O_TBR); - } - - /* Virtual up counter */ - count = object->period - count; - - return (count); -} - -/* - * ======== TimerCC32XX_hwiIntFunction ======== - */ -void TimerCC32XX_hwiIntFunction(uintptr_t arg) -{ - Timer_Handle handle = (Timer_Handle) arg; - TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - TimerCC32XX_Object const *object = handle->object; - uint32_t interruptMask; - - /* Only clear the interrupt for this->object->timer */ - interruptMask = object->timer & (TIMER_TIMA_TIMEOUT | TIMER_TIMB_TIMEOUT); - TimerIntClear(hwAttrs->baseAddress, interruptMask); - - /* Hwi is not created when using Timer_FREE_RUNNING */ - if (object->mode != Timer_CONTINUOUS_CALLBACK) { - TimerCC32XX_stop(handle); - } - - if (object-> mode != Timer_ONESHOT_BLOCKING) { - object->callBack(handle); - } -} - -/* - * ======== TimerCC32XX_init ======== - */ -void TimerCC32XX_init(Timer_Handle handle) -{ - return; -} - -/* - * ======== TimerCC32XX_open ======== - */ -Timer_Handle TimerCC32XX_open(Timer_Handle handle, Timer_Params *params) -{ - TimerCC32XX_Object *object = handle->object; - TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - SemaphoreP_Params semParams; - HwiP_Params hwiParams; - ClockP_FreqHz clockFreq; - - /* Check for valid parameters */ - if (((params->timerMode == Timer_ONESHOT_CALLBACK || - params->timerMode == Timer_CONTINUOUS_CALLBACK) && - params->timerCallback == NULL) || - params->period == 0) { - - return (NULL); - } - - if (!TimerCC32XX_allocateTimerResource(hwAttrs->baseAddress, - hwAttrs->subTimer)) { - - return (NULL); - } - - Power_registerNotify(&(object->notifyObj), PowerCC32XX_AWAKE_LPDS, - postNotifyFxn, (uintptr_t) handle); - - object->mode = params->timerMode; - object->isRunning = false; - object->callBack = params->timerCallback; - object->period = params->period; - object->prescaler = 0; - - if (hwAttrs->subTimer == TimerCC32XX_timer16B) { - - object->timer = TIMER_B; - } - else { - - object->timer = TIMER_A; - } - - if (object->mode != Timer_FREE_RUNNING) { - - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t) handle; - hwiParams.priority = hwAttrs->intPriority; - object->hwiHandle = HwiP_create(hwAttrs->intNum, - TimerCC32XX_hwiIntFunction, &hwiParams); - - if (object->hwiHandle == NULL) { - - TimerCC32XX_close(handle); - - return (NULL); - } - - } - - /* Creating the semaphore if mode is blocking */ - if (params->timerMode == Timer_ONESHOT_BLOCKING) { - - SemaphoreP_Params_init(&semParams); - semParams.mode = SemaphoreP_Mode_BINARY; - object->timerSem = SemaphoreP_create(0, &semParams); - - if (object->timerSem == NULL) { - - TimerCC32XX_close(handle); - - return (NULL); - } - } - - /* Formality; CC32XX System Clock fixed to 80.0 MHz */ - ClockP_getCpuFreq(&clockFreq); - - if (params->periodUnits == Timer_PERIOD_US) { - - /* Checks if the calculated period will fit in 32-bits */ - if (object->period >= ((uint32_t) ~0) / (clockFreq.lo / 1000000)) { - - TimerCC32XX_close(handle); - - return (NULL); - } - - object->period = object->period * (clockFreq.lo / 1000000); - } - else if (params->periodUnits == Timer_PERIOD_HZ) { - - /* If (object->period) > clockFreq */ - if ((object->period = clockFreq.lo / object->period) == 0) { - - TimerCC32XX_close(handle); - - return (NULL); - } - } - - /* If using a half timer */ - if (hwAttrs->subTimer != TimerCC32XX_timer32) { - - if (object->period > 0xFFFF) { - - /* 24-bit resolution for the half timer */ - if (object->period >= (1 << 24)) { - - TimerCC32XX_close(handle); - - return (NULL); - } - - getPrescaler(handle); - } - } - - initHw(handle); - - return (handle); -} - -/* - * ======== TimerCC32XX_start ======== - */ -int32_t TimerCC32XX_start(Timer_Handle handle) -{ - TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - TimerCC32XX_Object *object = handle->object; - uint32_t interruptMask; - uintptr_t key; - - interruptMask = object->timer & (TIMER_TIMB_TIMEOUT | TIMER_TIMA_TIMEOUT); - - key = HwiP_disable(); - - if (object->isRunning) { - - HwiP_restore(key); - - return (Timer_STATUS_ERROR); - } - - object->isRunning = true; - - if (object->hwiHandle) { - - TimerIntEnable(hwAttrs->baseAddress, interruptMask); - } - - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* Reload the timer */ - if (object->timer == TIMER_A) { - HWREG(hwAttrs->baseAddress + TIMER_O_TAMR) |= TIMER_TAMR_TAILD; - } - else { - HWREG(hwAttrs->baseAddress + TIMER_O_TBMR) |= TIMER_TBMR_TBILD; - } - - TimerEnable(hwAttrs->baseAddress, object->timer); - - HwiP_restore(key); - - if (object->mode == Timer_ONESHOT_BLOCKING) { - - /* Pend forever, ~0 */ - SemaphoreP_pend(object->timerSem, ~0); - } - - return (Timer_STATUS_SUCCESS); -} - -/* - * ======== TimerCC32XX_stop ======== - */ -void TimerCC32XX_stop(Timer_Handle handle) -{ - TimerCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - TimerCC32XX_Object *object = handle->object; - uint32_t interruptMask; - uintptr_t key; - bool flag = false; - - interruptMask = object->timer & (TIMER_TIMB_TIMEOUT | TIMER_TIMA_TIMEOUT); - - key = HwiP_disable(); - - if (object->isRunning) { - - object->isRunning = false; - - /* Post the Semaphore when called from the Hwi */ - if (object->mode == Timer_ONESHOT_BLOCKING) { - flag = true; - } - - TimerDisable(hwAttrs->baseAddress, object->timer); - TimerIntDisable(hwAttrs->baseAddress, interruptMask); - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - } - - HwiP_restore(key); - - if (flag) { - SemaphoreP_post(object->timerSem); - } -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/timer/TimerCC32XX.h b/ext/hal/ti/simplelink/source/ti/drivers/timer/TimerCC32XX.h deleted file mode 100644 index f8f3a0de91f..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/timer/TimerCC32XX.h +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!***************************************************************************** - * @file TimerCC32XX.h - * @brief Timer driver interface for CC32XX devices - * - * # Operation # - * This driver implements half and full width general purpose timers for the - * CC32XX device. For CC32XX devices, the system clock is 80 MHz and a 16-bit - * timer has an 8-bit prescaler. The desired period may not always be - * achieved due to hardware limitations, such as the aforementioned. The timer - * resolution is limited to 12.5ns due to the 80 MHz clock. A timer period no - * greater than 209,714us can be achieved when operating in 16-bit mode. - * Similarly, a period no greater than 53,687,090us can be achieved when - * operating in 32-bit mode. The same time constraints apply to the 16-bit - * timer when attempting to use a frequency less than 5 Hertz. For additional - * details, refer to the device's technical reference manual. - * - * The timer always operates in count down mode. When using a half width timer, - * an 8-bit prescaler will be implemented by the driver if necessary. If the - * timer is operating in Timer_FREE_RUNNING, the timer will count down from the - * specified period to 0 before restarting. - * - * When using a half width timer, Timer_getCount() will return the - * value of the counter in bits 15:0 and bits 23:16 will contain the - * current free-running value of the prescaler. Bits 31:24 are always 0. - * When using a full width timer, Timer_getCount() will return the - * the value of the 32-bit timer. - * - * #Timer_ONESHOT_CALLBACK is non-blocking. After Timer_start() is called, - * the calling thread will continue execution. When the timer interrupt - * is triggered, the specified callback function will be called. The timer - * will not generate another interrupt unless Timer_start() is called again. - * Calling Timer_stop() or Timer_close() after Timer_start() but, before the - * timer interrupt, will prevent the specified callback from ever being - * invoked. - * - * #Timer_ONESHOT_BLOCKING is a blocking call. A semaphore is used to block - * the calling thead's execution until the timer generates an interrupt. If - * Timer_stop() is called, the calling thread will become unblocked - * immediately. The behavior of the timer in this mode is similar to a sleep - * function. - * - * #Timer_CONTINUOUS_CALLBACK is non-blocking. After Timer_start() is called, - * the calling thread will continue execution. When the timer interrupt is - * treiggered, the specified callback function will be called. The timer is - * automatically restarted and will continue to periodically generate - * interrupts until Timer_stop() is called. - * - * #Timer_FREE_RUNNING is non-blocking. After Timer_start() is called, - * the calling thread will continue execution. The timer will not - * generate an interrupt in this mode. The timer will count down from the - * specified period until it reaches 0. The timer will automatically reload - * the period and start over. The timer will continue running until - * Timer_stop() is called. - * - * # Resource Allocation # - * Each general purpose timer block contains two timers, Timer A and Timer B, - * that can be configured to operate independently; or concatenated to operate - * as one 32-bit timer. This behavior is managed through a set of resource - * allocation APIs. For example, the TimerCC32XX_allocateTimerResource API - * will allocate a timer for exclusive use. Any attempt to allocate this - * resource in the future will result in a false value being returned from the - * allocation API. To free a timer resource, the TimerCC32XX_freeTimerResource - * is used. The application is not responsible for calling these allocation - * APIs directly. - * - * ============================================================================ - */ - -#ifndef ti_drivers_timer_TimerCC32XX__include -#define ti_drivers_timer_TimerCC32XX__include - -#ifdef __cplusplus -extern "C" -{ -#endif - -#include -#include - -#include -#include -#include -#include - -/*! - * @def TimerCC32XX_SubTimer - * - * @brief Sub-timers on the CC32XX - * - * The timer peripheral supports full width and half width timer operation. - * Use the definitions in this enumerated type to specify a full width timer - * (32-bit) or half width timer (16-bit) in the hardware attributes. There are - * two half width timers per single timer peripheral. A 16-bit timer on this - * device has an 8-bit prescaler. - */ -typedef enum TimerCC32XX_SubTimer_ { - TimerCC32XX_timer16A = 0x0001, /*!< Half width timer A */ - TimerCC32XX_timer16B = 0x0002, /*!< Half width timer B */ - TimerCC32XX_timer32 = 0x0003, /*!< Full width timer */ -} TimerCC32XX_SubTimer; - -extern const Timer_FxnTable TimerCC32XX_fxnTable; - -/*! - * @brief TimerCC32XX Hardware Attributes - * - * Timer hardware attributes that tell the TimerCC32XX driver specific hardware - * configurations and interrupt/priority settings. - * - * A sample structure is shown below: - * @code - * const TimerCC32XX_HWAttrs timerCC32XXHWAttrs[] = - * { - * { - * .baseAddress = TIMERA0_BASE, - * .subTimer = TimerCC32XX_timer32, - * .intNum = INT_TIMERA0A, - * .intPriority = ~0 - * }, - * { - * .baseAddress = TIMERA1_BASE, - * .subTimer = TimerCC32XX_timer16A, - * .intNum = INT_TIMERA1A, - * .intPriority = ~0 - * }, - * { - * .baseAddress = TIMERA1_BASE, - * .subTimer = TimerCC32XX_timer16B, - * .intNum = INT_TIMERA1B, - * .intPriority = ~0 - * } - * }; - * @endcode - */ -typedef struct TimerCC32XX_HWAttrs_ { - /*! The base address of the timer peripheral. */ - uint32_t baseAddress; - - /*! Specifies a full width timer or half-width timer. */ - TimerCC32XX_SubTimer subTimer; - - /*! The hardware interrupt number for the timer peripheral. */ - uint32_t intNum; - - /*! The interrupt priority. */ - uint32_t intPriority; -} TimerCC32XX_HWAttrs; - -/*! - * @brief TimerCC32XX_Object - * - * The application must not access any member variables of this structure! - */ -typedef struct TimerCC32XX_Object_ { - HwiP_Handle hwiHandle; - Power_NotifyObj notifyObj; - SemaphoreP_Handle timerSem; - Timer_CallBackFxn callBack; - Timer_Mode mode; - uint32_t timer; - uint32_t period; - uint32_t prescaler; - bool isRunning; -} TimerCC32XX_Object; - -/*! - * @brief Function to allocate a timer peripheral. - * - * This function is intended to be used by any driver which implements a - * timer hardware peripheral. Calling this function will enable power to the - * timer peripheral specified by the parameter, baseAddress. - * - * @param baseAddress The base address of a timer hardware peripheral. - * - * @param subTimer The TimerCC32XX_subTimer to be allocated. - * - * @return A bool returning true if the timer resource was successfully - * allocated. If the base address is not valid or if the resource is - * not available, false is returned. - * - * @sa TimerCC32XX_freeTimerResource() - */ -extern bool TimerCC32XX_allocateTimerResource(uint32_t baseAddress, - TimerCC32XX_SubTimer subTimer); - -/*! - * @brief Function to de-allocate a timer peripheral. - * - * This function is intended to be used by any driver which implements a - * timer hardware peripheral. Calling this function will disable power to the - * timer peripheral specified by the parameter, baseAddress, if and only if - * the timer peripheral is no longer in use. - * - * @pre A successful call to TimerCC32XX_allocateTimerResource() using the - * baseAddress and subTimer must have been made prior to calling this - * API. - * - * @param baseAddress The base address of a timer hardware peripheral. - * - * @param subTimer The TimerCC32XX_subTimer to be freed. - * - * @sa TimerCC32XX_allocateTimerResource() - */ -extern void TimerCC32XX_freeTimerResource(uint32_t baseAddress, - TimerCC32XX_SubTimer subTimer); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_timer_TimerCC32XX__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XX.c b/ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XX.c deleted file mode 100644 index 2fb1d03ef61..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XX.c +++ /dev/null @@ -1,1335 +0,0 @@ -/* - * Copyright (c) 2014-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include - -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif - -#include -#include -#include -#include - -#include - -/* driverlib header files */ -#include -#include -#include -#include -#include -#include -#include -#include - -/* Pad configuration defines */ -#define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) -#define PAD_RESET_STATE 0xC61 - -/* UARTCC32XX functions */ -void UARTCC32XX_close(UART_Handle handle); -int_fast16_t UARTCC32XX_control(UART_Handle handle, uint_fast16_t cmd, - void *arg); -void UARTCC32XX_init(UART_Handle handle); -UART_Handle UARTCC32XX_open(UART_Handle handle, UART_Params *params); -int_fast32_t UARTCC32XX_read(UART_Handle handle, void *buffer, size_t size); -void UARTCC32XX_readCancel(UART_Handle handle); -int_fast32_t UARTCC32XX_readPolling(UART_Handle handle, void *buffer, - size_t size); -int_fast32_t UARTCC32XX_write(UART_Handle handle, const void *buffer, - size_t size); -void UARTCC32XX_writeCancel(UART_Handle handle); -int_fast32_t UARTCC32XX_writePolling(UART_Handle handle, const void *buffer, - size_t size); - -/* Static functions */ -static unsigned int getPowerMgrId(unsigned int baseAddr); -static void initHw(UART_Handle handle); -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg); -static void readBlockingTimeout(uintptr_t arg); -static bool readIsrBinaryBlocking(UART_Handle handle); -static bool readIsrBinaryCallback(UART_Handle handle); -static bool readIsrTextBlocking(UART_Handle handle); -static bool readIsrTextCallback(UART_Handle handle); -static void readSemCallback(UART_Handle handle, void *buffer, size_t count); -static int readTaskBlocking(UART_Handle handle); -static int readTaskCallback(UART_Handle handle); -static void releasePowerConstraint(UART_Handle handle); -static int ringBufGet(UART_Handle object, unsigned char *data); -static void writeData(UART_Handle handle, bool inISR); -static void writeSemCallback(UART_Handle handle, void *buffer, size_t count); - -/* - * Function for checking whether flow control is enabled. - */ -static inline bool isFlowControlEnabled(UARTCC32XX_HWAttrsV1 const *hwAttrs) { - return ((hwAttrs->flowControl == UARTCC32XX_FLOWCTRL_HARDWARE) && - (hwAttrs->ctsPin != UARTCC32XX_PIN_UNASSIGNED) && - (hwAttrs->rtsPin != UARTCC32XX_PIN_UNASSIGNED)); -} - -/* UART function table for UARTCC32XX implementation */ -const UART_FxnTable UARTCC32XX_fxnTable = { - UARTCC32XX_close, - UARTCC32XX_control, - UARTCC32XX_init, - UARTCC32XX_open, - UARTCC32XX_read, - UARTCC32XX_readPolling, - UARTCC32XX_readCancel, - UARTCC32XX_write, - UARTCC32XX_writePolling, - UARTCC32XX_writeCancel -}; - -static const uint32_t dataLength[] = { - UART_CONFIG_WLEN_5, /* UART_LEN_5 */ - UART_CONFIG_WLEN_6, /* UART_LEN_6 */ - UART_CONFIG_WLEN_7, /* UART_LEN_7 */ - UART_CONFIG_WLEN_8 /* UART_LEN_8 */ -}; - -static const uint32_t stopBits[] = { - UART_CONFIG_STOP_ONE, /* UART_STOP_ONE */ - UART_CONFIG_STOP_TWO /* UART_STOP_TWO */ -}; - -static const uint32_t parityType[] = { - UART_CONFIG_PAR_NONE, /* UART_PAR_NONE */ - UART_CONFIG_PAR_EVEN, /* UART_PAR_EVEN */ - UART_CONFIG_PAR_ODD, /* UART_PAR_ODD */ - UART_CONFIG_PAR_ZERO, /* UART_PAR_ZERO */ - UART_CONFIG_PAR_ONE /* UART_PAR_ONE */ -}; - -/* - * ======== staticFxnTable ======== - * This is a function lookup table to simplify the UART driver modes. - */ -static const UARTCC32XX_FxnSet staticFxnTable[2][2] = { - {/* UART_MODE_BLOCKING */ - {/* UART_DATA_BINARY */ - .readIsrFxn = readIsrBinaryBlocking, - .readTaskFxn = readTaskBlocking - }, - {/* UART_DATA_TEXT */ - .readIsrFxn = readIsrTextBlocking, - .readTaskFxn = readTaskBlocking - } - }, - {/* UART_MODE_CALLBACK */ - {/* UART_DATA_BINARY */ - .readIsrFxn = readIsrBinaryCallback, - .readTaskFxn = readTaskCallback - - }, - {/* UART_DATA_TEXT */ - .readIsrFxn = readIsrTextCallback, - .readTaskFxn = readTaskCallback, - } - } -}; - -/* - * ======== UARTCC32XX_close ======== - */ -void UARTCC32XX_close(UART_Handle handle) -{ - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uint_fast16_t retVal; - uint32_t padRegister; - - /* Disable UART and interrupts. */ - MAP_UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX | UART_INT_RX | - UART_INT_RT | UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); - MAP_UARTDisable(hwAttrs->baseAddr); - - if (object->hwiHandle) { - HwiP_delete(object->hwiHandle); - } - if (object->writeSem) { - SemaphoreP_delete(object->writeSem); - } - if (object->readSem) { - SemaphoreP_delete(object->readSem); - } - if (object->timeoutClk) { - ClockP_delete(object->timeoutClk); - } - - if (object->state.txEnabled) { - retVal = Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_assert(retVal == Power_SOK); - object->state.txEnabled = false; - } - - Power_unregisterNotify(&object->postNotify); - if (object->state.rxEnabled) { - retVal = Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_assert(retVal == Power_SOK); - object->state.rxEnabled = false; - - DebugP_log1("UART:(%p) UART_close released read power constraint", - hwAttrs->baseAddr); - } - Power_releaseDependency(object->powerMgrId); - - if (object->txPin != (uint16_t)-1) { - PowerCC32XX_restoreParkState((PowerCC32XX_Pin)object->txPin, - object->prevParkTX); - object->txPin = (uint16_t)-1; - } - - if (object->rtsPin != (uint16_t)-1) { - PowerCC32XX_restoreParkState((PowerCC32XX_Pin)object->rtsPin, - object->prevParkRTS); - object->rtsPin = (uint16_t)-1; - } - - /* Restore pin pads to their reset states */ - padRegister = (PinToPadGet((hwAttrs->rxPin) & 0xff)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - padRegister = (PinToPadGet((hwAttrs->txPin) & 0xff)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - if (isFlowControlEnabled(hwAttrs)) { - padRegister = (PinToPadGet((hwAttrs->ctsPin) & 0xff)<<2) - + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - padRegister = (PinToPadGet((hwAttrs->rtsPin) & 0xff)<<2) - + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - } - - object->state.opened = false; - - DebugP_log1("UART:(%p) closed", hwAttrs->baseAddr); - - (void)retVal; -} - -/* - * ======== UARTCC32XX_control ======== - * @pre Function assumes that the handle is not NULL - */ -int_fast16_t UARTCC32XX_control(UART_Handle handle, uint_fast16_t cmd, - void *arg) -{ - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - unsigned char data; - int bufferCount; - uint_fast16_t retVal; - - bufferCount = RingBuf_peek(&object->ringBuffer, &data); - - switch (cmd) { - /* Common UART CMDs */ - case (UART_CMD_PEEK): - *(int *)arg = (bufferCount) ? data : UART_ERROR; - DebugP_log2("UART:(%p) UART_CMD_PEEK: %d", hwAttrs->baseAddr, - *(uintptr_t*)arg); - return (UART_STATUS_SUCCESS); - - case (UART_CMD_ISAVAILABLE): - *(bool *)arg = (bufferCount != 0); - DebugP_log2("UART:(%p) UART_CMD_ISAVAILABLE: %d", hwAttrs->baseAddr, - *(uintptr_t*)arg); - return (UART_STATUS_SUCCESS); - - case (UART_CMD_GETRXCOUNT): - *(int *)arg = bufferCount; - DebugP_log2("UART:(%p) UART_CMD_GETRXCOUNT: %d", hwAttrs->baseAddr, - *(uintptr_t*)arg); - return (UART_STATUS_SUCCESS); - - case (UART_CMD_RXENABLE): - if (!object->state.rxEnabled) { - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - MAP_UARTIntEnable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | - UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); - object->state.rxEnabled = true; - DebugP_log1("UART:(%p) UART_CMD_RXENABLE: Enabled", - hwAttrs->baseAddr); - DebugP_log1("UART:(%p) UART_control set read power constraint", - hwAttrs->baseAddr); - return (UART_STATUS_SUCCESS); - } - DebugP_log1("UART:(%p) UART_CMD_RXENABLE: Already enabled", - hwAttrs->baseAddr); - return (UART_STATUS_ERROR); - - case (UART_CMD_RXDISABLE): - if (object->state.rxEnabled) { - MAP_UARTIntDisable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | - UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); - retVal = Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_assert(retVal == Power_SOK); - object->state.rxEnabled = false; - DebugP_log1("UART:(%p) UART_CMD_RXDISABLE: Disabled", - hwAttrs->baseAddr); - DebugP_log1("UART:(%p) UART_control released read power " - "constraint", hwAttrs->baseAddr); - - (void)retVal; - return (UART_STATUS_SUCCESS); - } - DebugP_log1("UART:(%p) UART_CMD_RXDISABLE: Already disabled", - hwAttrs->baseAddr); - return (UART_STATUS_ERROR); - - /* Specific UART CMDs */ - case (UARTCC32XX_CMD_IS_BUSY): - *(bool *)arg = MAP_UARTBusy(hwAttrs->baseAddr); - return (UART_STATUS_SUCCESS); - - case (UARTCC32XX_CMD_IS_RX_DATA_AVAILABLE): - *(bool *)arg = MAP_UARTCharsAvail(hwAttrs->baseAddr); - return (UART_STATUS_SUCCESS); - - case (UARTCC32XX_CMD_IS_TX_SPACE_AVAILABLE): - *(bool *)arg = MAP_UARTSpaceAvail(hwAttrs->baseAddr); - return (UART_STATUS_SUCCESS); - - default: - DebugP_log2("UART:(%p) UART CMD undefined: %d", - hwAttrs->baseAddr, cmd); - return (UART_STATUS_UNDEFINEDCMD); - } -} - -/* - * ======== UARTCC32XX_hwiIntFxn ======== - * Hwi function that processes UART interrupts. - * - * @param(arg) The UART_Handle for this Hwi. - */ -static void UARTCC32XX_hwiIntFxn(uintptr_t arg) -{ - uint32_t status; - UARTCC32XX_Object *object = ((UART_Handle)arg)->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = ((UART_Handle)arg)->hwAttrs; - uint32_t rxErrors; - - /* Clear interrupts */ - status = MAP_UARTIntStatus(hwAttrs->baseAddr, true); - MAP_UARTIntClear(hwAttrs->baseAddr, status); - - if (status & (UART_INT_RX | UART_INT_RT | UART_INT_OE | UART_INT_BE | - UART_INT_PE | UART_INT_FE)) { - object->readFxns.readIsrFxn((UART_Handle)arg); - } - - /* Reading the data from the FIFO doesn't mean we caught an overrrun! */ - rxErrors = MAP_UARTRxErrorGet(hwAttrs->baseAddr); - if (rxErrors) { - MAP_UARTRxErrorClear(hwAttrs->baseAddr); - if (hwAttrs->errorFxn) { - hwAttrs->errorFxn((UART_Handle)arg, rxErrors); - } - } - - if (status & UART_INT_TX) { - writeData((UART_Handle)arg, true); - } -} - -/* - * ======== UARTCC32XX_init ======== - */ -void UARTCC32XX_init(UART_Handle handle) -{ -} - -/* - * ======== UARTCC32XX_open ======== - */ -UART_Handle UARTCC32XX_open(UART_Handle handle, UART_Params *params) -{ - uintptr_t key; - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - SemaphoreP_Params semParams; - HwiP_Params hwiParams; - ClockP_Params clockParams; - uint16_t pin; - uint16_t mode; - - /* Check for callback when in UART_MODE_CALLBACK */ - DebugP_assert((params->readMode != UART_MODE_CALLBACK) || - (params->readCallback != NULL)); - DebugP_assert((params->writeMode != UART_MODE_CALLBACK) || - (params->writeCallback != NULL)); - - key = HwiP_disable(); - - if (object->state.opened == true) { - HwiP_restore(key); - - DebugP_log1("UART:(%p) already in use.", hwAttrs->baseAddr); - return (NULL); - } - object->state.opened = true; - - HwiP_restore(key); - - object->state.readMode = params->readMode; - object->state.writeMode = params->writeMode; - object->state.readReturnMode = params->readReturnMode; - object->state.readDataMode = params->readDataMode; - object->state.writeDataMode = params->writeDataMode; - object->state.readEcho = params->readEcho; - object->readTimeout = params->readTimeout; - object->writeTimeout = params->writeTimeout; - object->readCallback = params->readCallback; - object->writeCallback = params->writeCallback; - object->baudRate = params->baudRate; - object->stopBits = params->stopBits; - object->dataLength = params->dataLength; - object->parityType = params->parityType; - object->readFxns = - staticFxnTable[object->state.readMode][object->state.readDataMode]; - - /* Set UART variables to defaults. */ - object->writeBuf = NULL; - object->readBuf = NULL; - object->writeCount = 0; - object->readCount = 0; - object->writeSize = 0; - object->readSize = 0; - object->state.txEnabled = false; - object->txPin = (uint16_t)-1; - object->rtsPin = (uint16_t)-1; - - RingBuf_construct(&object->ringBuffer, hwAttrs->ringBufPtr, - hwAttrs->ringBufSize); - - /* Get the Power resource Id from the base address */ - object->powerMgrId = getPowerMgrId(hwAttrs->baseAddr); - if (object->powerMgrId == (unsigned int)-1) { - DebugP_log1("UART:(%p) Failed to determine Power resource id", - hwAttrs->baseAddr); - return (NULL); - } - - /* - * Register power dependency. Keeps the clock running in SLP - * and DSLP modes. - */ - Power_setDependency(object->powerMgrId); - - pin = (hwAttrs->rxPin) & 0xff; - mode = (hwAttrs->rxPin >> 8) & 0xff; - - MAP_PinTypeUART((unsigned long)pin, (unsigned long)mode); - - pin = (hwAttrs->txPin) & 0xff; - mode = (hwAttrs->txPin >> 8) & 0xff; - - MAP_PinTypeUART((unsigned long)pin, (unsigned long)mode); - - /* - * Read and save TX pin park state; set to "don't park" while UART is - * open as device default is logic '1' during LPDS - */ - object->prevParkTX = - (PowerCC32XX_ParkState) PowerCC32XX_getParkState((PowerCC32XX_Pin)pin); - PowerCC32XX_setParkState((PowerCC32XX_Pin)pin, ~1); - object->txPin = pin; - - if (isFlowControlEnabled(hwAttrs)) { - pin = (hwAttrs->ctsPin) & 0xff; - mode = (hwAttrs->ctsPin >> 8) & 0xff; - MAP_PinTypeUART((unsigned long)pin, (unsigned long)mode); - - pin = (hwAttrs->rtsPin) & 0xff; - mode = (hwAttrs->rtsPin >> 8) & 0xff; - MAP_PinTypeUART((unsigned long)pin, (unsigned long)mode); - - /* - * Read and save RTS pin park state; set to "don't park" while UART is - * open as device default is logic '1' during LPDS - */ - object->prevParkRTS = (PowerCC32XX_ParkState)PowerCC32XX_getParkState( - (PowerCC32XX_Pin)pin); - PowerCC32XX_setParkState((PowerCC32XX_Pin)pin, ~1); - object->rtsPin = pin; - - /* Flow control will be enabled in initHw() */ - } - - Power_registerNotify(&object->postNotify, PowerCC32XX_AWAKE_LPDS, - postNotifyFxn, (uintptr_t)handle); - - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - object->state.rxEnabled = true; - - DebugP_log1("UART:(%p) UART_open set read power constraint", - hwAttrs->baseAddr); - - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t)handle; - hwiParams.priority = hwAttrs->intPriority; - object->hwiHandle = HwiP_create(hwAttrs->intNum, UARTCC32XX_hwiIntFxn, - &hwiParams); - if (object->hwiHandle == NULL) { - DebugP_log1("UART:(%p) HwiP_create() failed", hwAttrs->baseAddr); - UARTCC32XX_close(handle); - return (NULL); - } - - SemaphoreP_Params_init(&semParams); - semParams.mode = SemaphoreP_Mode_BINARY; - - /* If write mode is blocking create a semaphore and set callback. */ - if (object->state.writeMode == UART_MODE_BLOCKING) { - if ((object->writeSem = SemaphoreP_create(0, &semParams)) == NULL) { - DebugP_log1("UART:(%p) SemaphoreP_create() failed.", - hwAttrs->baseAddr); - UARTCC32XX_close(handle); - return (NULL); - } - object->writeCallback = &writeSemCallback; - } - - ClockP_Params_init(&clockParams); - clockParams.arg = (uintptr_t)handle; - - /* If read mode is blocking create a semaphore and set callback. */ - if (object->state.readMode == UART_MODE_BLOCKING) { - object->readSem = SemaphoreP_create(0, &semParams); - if (object->readSem == NULL) { - DebugP_log1("UART:(%p) SemaphoreP_create() failed.", - hwAttrs->baseAddr); - UARTCC32XX_close(handle); - return (NULL); - } - object->readCallback = &readSemCallback; - object->timeoutClk = - ClockP_create((ClockP_Fxn)&readBlockingTimeout, - 0 /* timeout */, &(clockParams)); - if (object->timeoutClk == NULL) { - DebugP_log1("UART:(%p) ClockP_create() failed.", - hwAttrs->baseAddr); - UARTCC32XX_close(handle); - return (NULL); - } - } - else { - object->state.drainByISR = false; - } - - /* Initialize the hardware */ - initHw(handle); - - DebugP_log1("UART:(%p) opened", hwAttrs->baseAddr); - - /* Return the handle */ - return (handle); -} - -/* - * ======== UARTCC32XX_read ======== - */ -int_fast32_t UARTCC32XX_read(UART_Handle handle, void *buffer, size_t size) -{ - uintptr_t key; - UARTCC32XX_Object *object = handle->object; - - key = HwiP_disable(); - - if ((object->state.readMode == UART_MODE_CALLBACK) && object->readSize) { - HwiP_restore(key); - - DebugP_log1("UART:(%p) Could not read data, uart in use.", - ((UARTCC32XX_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); - return (UART_ERROR); - } - - /* Save the data to be read and restore interrupts. */ - object->readBuf = buffer; - object->readSize = size; - object->readCount = size; - - HwiP_restore(key); - - return (object->readFxns.readTaskFxn(handle)); -} - -/* - * ======== UARTCC32XX_readCancel ======== - */ -void UARTCC32XX_readCancel(UART_Handle handle) -{ - uintptr_t key; - UARTCC32XX_Object *object = handle->object; - - if ((object->state.readMode != UART_MODE_CALLBACK) || - (object->readSize == 0)) { - return; - } - - key = HwiP_disable(); - - object->state.drainByISR = false; - /* - * Indicate that what we've currently received is what we asked for so that - * the existing logic handles the completion. - */ - object->readSize -= object->readCount; - object->readCount = 0; - - HwiP_restore(key); - - object->readFxns.readTaskFxn(handle); -} - -/* - * ======== UARTCC32XX_readPolling ======== - */ -int_fast32_t UARTCC32XX_readPolling(UART_Handle handle, void *buf, size_t size) -{ - int32_t count = 0; - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - unsigned char *buffer = (unsigned char *)buf; - - /* Read characters. */ - while (size) { - /* Grab data from the RingBuf before getting it from the RX data reg */ - MAP_UARTIntDisable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT); - if (RingBuf_get(&object->ringBuffer, buffer) == -1) { - *buffer = MAP_UARTCharGet(hwAttrs->baseAddr); - } - if (object->state.rxEnabled) { - MAP_UARTIntEnable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT); - } - - DebugP_log2("UART:(%p) Read character 0x%x", hwAttrs->baseAddr, - *buffer); - count++; - size--; - - if (object->state.readDataMode == UART_DATA_TEXT && *buffer == '\r') { - /* Echo character if enabled. */ - if (object->state.readEcho) { - MAP_UARTCharPut(hwAttrs->baseAddr, '\r'); - } - *buffer = '\n'; - } - - /* Echo character if enabled. */ - if (object->state.readDataMode == UART_DATA_TEXT && - object->state.readEcho) { - MAP_UARTCharPut(hwAttrs->baseAddr, *buffer); - } - - /* If read return mode is newline, finish if a newline was received. */ - if (object->state.readDataMode == UART_DATA_TEXT && - object->state.readReturnMode == UART_RETURN_NEWLINE && - *buffer == '\n') { - return (count); - } - - buffer++; - } - - DebugP_log2("UART:(%p) Read polling finished, %d bytes read", - hwAttrs->baseAddr, count); - - return (count); -} - -/* - * ======== UARTCC32XX_write ======== - */ -int_fast32_t UARTCC32XX_write(UART_Handle handle, const void *buffer, - size_t size) -{ - unsigned int key; - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - if (!size) { - return 0; - } - - key = HwiP_disable(); - - if (object->writeCount) { - HwiP_restore(key); - DebugP_log1("UART:(%p) Could not write data, uart in use.", - hwAttrs->baseAddr); - - return (UART_ERROR); - } - - /* Save the data to be written and restore interrupts. */ - object->writeBuf = buffer; - object->writeSize = size; - object->writeCount = size; - - if (object->state.txEnabled == false){ - object->state.txEnabled = true; - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_log1("UART:(%p) UART_write set write power constraint", - hwAttrs->baseAddr); - } - - HwiP_restore(key); - - if (!(MAP_UARTIntStatus(hwAttrs->baseAddr, false) & UART_INT_TX)) { - /* - * Start the transfer going if the raw interrupt status TX bit - * is 0. This will cause the ISR to fire when we enable - * UART_INT_TX. If the RIS TX bit is not cleared, we don't - * need to call writeData(), since the ISR will fire once we - * enable the interrupt, causing the transfer to start. - */ - writeData(handle, false); - } - if (object->writeCount) { - MAP_UARTTxIntModeSet(hwAttrs->baseAddr, UART_TXINT_MODE_FIFO); - MAP_UARTIntEnable(hwAttrs->baseAddr, UART_INT_TX); - } - - /* If writeMode is blocking, block and get the state. */ - if (object->state.writeMode == UART_MODE_BLOCKING) { - /* Pend on semaphore and wait for Hwi to finish. */ - if (SemaphoreP_OK != SemaphoreP_pend(object->writeSem, - object->writeTimeout)) { - /* Semaphore timed out, make the write empty and log the write. */ - MAP_UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX); - MAP_UARTIntClear(hwAttrs->baseAddr, UART_INT_TX); - object->writeCount = 0; - - DebugP_log2("UART:(%p) Write timed out, %d bytes written", - hwAttrs->baseAddr, object->writeCount); - } - return (object->writeSize - object->writeCount); - } - - return (0); -} - -/* - * ======== UARTCC32XX_writeCancel ======== - */ -void UARTCC32XX_writeCancel(UART_Handle handle) -{ - uintptr_t key; - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - unsigned int written; - uint_fast16_t retVal; - - key = HwiP_disable(); - - /* Return if there is no write. */ - if (!object->writeCount) { - HwiP_restore(key); - return; - } - - /* Set size = 0 to prevent writing and restore interrupts. */ - written = object->writeCount; - object->writeCount = 0; - MAP_UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX); - MAP_UARTIntClear(hwAttrs->baseAddr, UART_INT_TX); - - retVal = Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_assert(retVal == Power_SOK); - object->state.txEnabled = false; - - HwiP_restore(key); - - /* Reset the write buffer so we can pass it back */ - object->writeCallback(handle, (void *)object->writeBuf, - object->writeSize - written); - - DebugP_log2("UART:(%p) Write canceled, %d bytes written", - hwAttrs->baseAddr, object->writeSize - written); - - (void)retVal; -} - -/* - * ======== UARTCC32XX_writePolling ======== - */ -int_fast32_t UARTCC32XX_writePolling(UART_Handle handle, const void *buf, - size_t size) -{ - int32_t count = 0; - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - unsigned char *buffer = (unsigned char *)buf; - - /* Write characters. */ - while (size) { - if (object->state.writeDataMode == UART_DATA_TEXT && *buffer == '\n') { - MAP_UARTCharPut(hwAttrs->baseAddr, '\r'); - count++; - } - MAP_UARTCharPut(hwAttrs->baseAddr, *buffer); - - DebugP_log2("UART:(%p) Wrote character 0x%x", hwAttrs->baseAddr, - *buffer); - buffer++; - count++; - size--; - } - - while (MAP_UARTBusy(hwAttrs->baseAddr)) { - ; - } - - DebugP_log2("UART:(%p) Write polling finished, %d bytes written", - hwAttrs->baseAddr, count); - - return (count); -} - -/* - * ======== getPowerMgrId ======== - */ -static unsigned int getPowerMgrId(unsigned int baseAddr) -{ - switch (baseAddr) { - case UARTA0_BASE: - return (PowerCC32XX_PERIPH_UARTA0); - case UARTA1_BASE: - return (PowerCC32XX_PERIPH_UARTA1); - default: - return ((unsigned int)-1); - } -} - -/* - * ======== initHw ======== - */ -static void initHw(UART_Handle handle) -{ - ClockP_FreqHz freq; - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - /* Enable UART and its interrupt. */ - MAP_UARTIntClear(hwAttrs->baseAddr, UART_INT_TX | UART_INT_RX | - UART_INT_RT); - MAP_UARTEnable(hwAttrs->baseAddr); - - /* Set the FIFO level to 7/8 empty and 4/8 full. */ - MAP_UARTFIFOLevelSet(hwAttrs->baseAddr, UART_FIFO_TX1_8, UART_FIFO_RX1_8); - - if (isFlowControlEnabled(hwAttrs)) { - /* Set flow control */ - MAP_UARTFlowControlSet(hwAttrs->baseAddr, - UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX); - } - else { - MAP_UARTFlowControlSet(hwAttrs->baseAddr, UART_FLOWCONTROL_NONE); - } - - ClockP_getCpuFreq(&freq); - MAP_UARTConfigSetExpClk(hwAttrs->baseAddr, freq.lo, object->baudRate, - dataLength[object->dataLength] | stopBits[object->stopBits] | - parityType[object->parityType]); - - MAP_UARTIntEnable(hwAttrs->baseAddr, UART_INT_RX | UART_INT_RT | - UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE); -} - -/* - * ======== postNotifyFxn ======== - * Called by Power module when waking up from LPDS. - */ -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - initHw((UART_Handle)clientArg); - - return (Power_NOTIFYDONE); -} - -/* - * ======== readBlockingTimeout ======== - */ -static void readBlockingTimeout(uintptr_t arg) -{ - UARTCC32XX_Object *object = ((UART_Handle)arg)->object; - object->state.bufTimeout = true; - SemaphoreP_post(object->readSem); -} - -/* - * ======== readIsrBinaryBlocking ======== - * Function that is called by the ISR - */ -static bool readIsrBinaryBlocking(UART_Handle handle) -{ - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - int readIn; - - while (MAP_UARTCharsAvail(hwAttrs->baseAddr)) { - /* - * If the Ring buffer is full, leave the data in the FIFO. - * This will allow flow control to work, if it is enabled. - */ - if (RingBuf_isFull(&object->ringBuffer)) { - return (false); - } - - readIn = MAP_UARTCharGetNonBlocking(hwAttrs->baseAddr); - /* - * Bits 0-7 contain the data, bits 8-11 are used for error codes. - * (Bits 12-31 are reserved and read as 0) If readIn > 0xFF, an - * error has occurred. - */ - if (readIn > 0xFF) { - if (hwAttrs->errorFxn) { - hwAttrs->errorFxn(handle, (uint32_t)((readIn >> 8) & 0xF)); - } - MAP_UARTRxErrorClear(hwAttrs->baseAddr); - return (false); - } - - RingBuf_put(&object->ringBuffer, (unsigned char)readIn); - - if (object->state.callCallback) { - object->state.callCallback = false; - object->readCallback(handle, NULL, 0); - } - } - return (true); -} - -/* - * ======== readIsrBinaryCallback ======== - */ -static bool readIsrBinaryCallback(UART_Handle handle) -{ - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - int readIn; - bool ret = true; - - while (MAP_UARTCharsAvail(hwAttrs->baseAddr)) { - if (RingBuf_isFull(&object->ringBuffer)) { - ret = false; - break; - } - - readIn = MAP_UARTCharGetNonBlocking(hwAttrs->baseAddr); - if (readIn > 0xFF) { - if (hwAttrs->errorFxn) { - hwAttrs->errorFxn(handle, (uint32_t)((readIn >> 8) & 0xF)); - } - MAP_UARTRxErrorClear(hwAttrs->baseAddr); - ret = false; - break; - } - - RingBuf_put(&object->ringBuffer, (unsigned char)readIn); - } - - /* - * Check and see if a UART_read in callback mode told use to continue - * servicing the user buffer... - */ - if (object->state.drainByISR) { - readTaskCallback(handle); - } - - return (ret); -} - -/* - * ======== readIsrTextBlocking ======== - */ -static bool readIsrTextBlocking(UART_Handle handle) -{ - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - int readIn; - - while (MAP_UARTCharsAvail(hwAttrs->baseAddr)) { - /* - * If the Ring buffer is full, leave the data in the FIFO. - * This will allow flow control to work, if it is enabled. - */ - if (RingBuf_isFull(&object->ringBuffer)) { - return (false); - } - - readIn = MAP_UARTCharGetNonBlocking(hwAttrs->baseAddr); - if (readIn > 0xFF) { - if (hwAttrs->errorFxn) { - hwAttrs->errorFxn(handle, (uint32_t)((readIn >> 8) & 0xF)); - } - MAP_UARTRxErrorClear(hwAttrs->baseAddr); - return (false); - } - - if (readIn == '\r') { - /* Echo character if enabled. */ - if (object->state.readEcho) { - MAP_UARTCharPut(hwAttrs->baseAddr, '\r'); - } - readIn = '\n'; - } - RingBuf_put(&object->ringBuffer, (unsigned char)readIn); - - if (object->state.readEcho) { - MAP_UARTCharPut(hwAttrs->baseAddr, (unsigned char)readIn); - } - if (object->state.callCallback) { - object->state.callCallback = false; - object->readCallback(handle, NULL, 0); - } - } - return (true); -} - -/* - * ======== readIsrTextCallback ======== - */ -static bool readIsrTextCallback(UART_Handle handle) -{ - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - int readIn; - bool ret = true; - - while (MAP_UARTCharsAvail(hwAttrs->baseAddr)) { - /* - * If the Ring buffer is full, leave the data in the FIFO. - * This will allow flow control to work, if it is enabled. - */ - if (RingBuf_isFull(&object->ringBuffer)) { - ret = false; - break; - } - - readIn = MAP_UARTCharGetNonBlocking(hwAttrs->baseAddr); - if (readIn > 0xFF) { - if (hwAttrs->errorFxn) { - hwAttrs->errorFxn(handle, (uint32_t)((readIn >> 8) & 0xF)); - } - MAP_UARTRxErrorClear(hwAttrs->baseAddr); - ret = false; - break; - } - - if (readIn == '\r') { - /* Echo character if enabled. */ - if (object->state.readEcho) { - MAP_UARTCharPut(hwAttrs->baseAddr, '\r'); - } - readIn = '\n'; - } - RingBuf_put(&object->ringBuffer, (unsigned char)readIn); - - if (object->state.readEcho) { - MAP_UARTCharPut(hwAttrs->baseAddr, (unsigned char)readIn); - } - } - - /* - * Check and see if a UART_read in callback mode told use to continue - * servicing the user buffer... - */ - if (object->state.drainByISR) { - readTaskCallback(handle); - } - - return (ret); -} - -/* - * ======== readSemCallback ======== - * Simple callback to post a semaphore for the blocking mode. - */ -static void readSemCallback(UART_Handle handle, void *buffer, size_t count) -{ - UARTCC32XX_Object *object = handle->object; - - SemaphoreP_post(object->readSem); -} - -/* - * ======== readTaskBlocking ======== - */ -static int readTaskBlocking(UART_Handle handle) -{ - unsigned char readIn; - uintptr_t key; - UARTCC32XX_Object *object = handle->object; - unsigned char *buffer = object->readBuf; - - object->state.bufTimeout = false; - /* - * It is possible for the object->timeoutClk and the callback function to - * have posted the object->readSem Semaphore from the previous UART_read - * call (if the code below didn't get to stop the clock object in time). - * To clear this, we simply do a NO_WAIT pend on (binary) object->readSem - * so that it resets the Semaphore count. - */ - SemaphoreP_pend(object->readSem, SemaphoreP_NO_WAIT); - - if ((object->readTimeout != 0) && - (object->readTimeout != UART_WAIT_FOREVER)) { - ClockP_setTimeout(object->timeoutClk, object->readTimeout); - ClockP_start(object->timeoutClk); - } - - while (object->readCount) { - key = HwiP_disable(); - - if (ringBufGet(handle, &readIn) < 0) { - object->state.callCallback = true; - HwiP_restore(key); - - if (object->readTimeout == 0) { - break; - } - - SemaphoreP_pend(object->readSem, SemaphoreP_WAIT_FOREVER); - if (object->state.bufTimeout == true) { - break; - } - ringBufGet(handle, &readIn); - } - else { - HwiP_restore(key); - } - - *buffer = readIn; - buffer++; - /* In blocking mode, readCount doesn't not need a lock */ - object->readCount--; - - if (object->state.readDataMode == UART_DATA_TEXT && - object->state.readReturnMode == UART_RETURN_NEWLINE && - readIn == '\n') { - break; - } - } - - ClockP_stop(object->timeoutClk); - return (object->readSize - object->readCount); -} - -/* - * ======== readTaskCallback ======== - * This function is called the first time by the UART_read task and tries to - * get all the data it can get from the ringBuffer. If it finished, it will - * perform the user supplied callback. If it didn't finish, the ISR must handle - * the remaining data. By setting the drainByISR flag, the UART_read function - * handed over the responsibility to get the remaining data to the ISR. - */ -static int readTaskCallback(UART_Handle handle) -{ - unsigned int key; - UARTCC32XX_Object *object = handle->object; - unsigned char readIn; - unsigned char *bufferEnd; - bool makeCallback = false; - size_t tempCount; - - object->state.drainByISR = false; - bufferEnd = (unsigned char*) object->readBuf + object->readSize; - - while (object->readCount) { - key = HwiP_disable(); - if (ringBufGet(handle, &readIn) < 0) { - /* Not all data has been read */ - object->state.drainByISR = true; - HwiP_restore(key); - break; - } - HwiP_restore(key); - - *(unsigned char *) (bufferEnd - object->readCount * - sizeof(unsigned char)) = readIn; - - object->readCount--; - - if ((object->state.readDataMode == UART_DATA_TEXT) && - (object->state.readReturnMode == UART_RETURN_NEWLINE) && - (readIn == '\n')) { - makeCallback = true; - break; - } - } - - if (!object->readCount || makeCallback) { - object->state.readCallbackPending = true; - if (object->state.inReadCallback == false) { - while (object->state.readCallbackPending) { - object->state.readCallbackPending = false; - tempCount = object->readSize; - object->readSize = 0; - - object->state.inReadCallback = true; - object->readCallback(handle, object->readBuf, - tempCount - object->readCount); - object->state.inReadCallback = false; - } - } - } - - return (0); -} - -/* - * ======== releasePowerConstraint ======== - */ -static void releasePowerConstraint(UART_Handle handle) -{ - UARTCC32XX_Object *object = handle->object; - uint_fast16_t retVal; - - retVal = Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - DebugP_assert(retVal == Power_SOK); - object->state.txEnabled = false; - - DebugP_log1("UART:(%p) UART released write power constraint", - ((UARTCC32XX_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); - - (void)retVal; -} - - -/* - * ======== ringBufGet ======== - */ -static int ringBufGet(UART_Handle handle, unsigned char *data) -{ - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uintptr_t key; - int32_t readIn; - int count; - - key = HwiP_disable(); - - if (RingBuf_isFull(&object->ringBuffer)) { - count = RingBuf_get(&object->ringBuffer, data); - - readIn = MAP_UARTCharGetNonBlocking(hwAttrs->baseAddr); - if (readIn != -1) { - RingBuf_put(&object->ringBuffer, (unsigned char)readIn); - count++; - } - HwiP_restore(key); - } - else { - count = RingBuf_get(&object->ringBuffer, data); - HwiP_restore(key); - } - - return (count); -} - -/* - * ======== writeData ======== - */ -static void writeData(UART_Handle handle, bool inISR) -{ - UARTCC32XX_Object *object = handle->object; - UARTCC32XX_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - unsigned char *writeOffset; - - writeOffset = (unsigned char *)object->writeBuf + - object->writeSize * sizeof(unsigned char); - while (object->writeCount) { - if (!MAP_UARTCharPutNonBlocking(hwAttrs->baseAddr, - *(writeOffset - object->writeCount))) { - /* TX FIFO is FULL */ - break; - } - if ((object->state.writeDataMode == UART_DATA_TEXT) && - (*(writeOffset - object->writeCount) == '\n')) { - MAP_UARTCharPut(hwAttrs->baseAddr, '\r'); - } - object->writeCount--; - } - - if (!object->writeCount) { - MAP_UARTIntDisable(hwAttrs->baseAddr, UART_INT_TX); - MAP_UARTIntClear(hwAttrs->baseAddr, UART_INT_TX); - - /* - * Set TX interrupt for end of transmission mode. - * The TXRIS bit will be set only when all the data - * (including stop bits) have left the serializer. - */ - MAP_UARTTxIntModeSet(hwAttrs->baseAddr, UART_TXINT_MODE_EOT); - - if (!UARTBusy(hwAttrs->baseAddr)) { - object->writeCallback(handle, (void *)object->writeBuf, - object->writeSize); - releasePowerConstraint(handle); - } - else { - UARTIntEnable(hwAttrs->baseAddr, UART_INT_TX); - } - - DebugP_log2("UART:(%p) Write finished, %d bytes written", - hwAttrs->baseAddr, object->writeSize - object->writeCount); - } -} - -/* - * ======== writeSemCallback ======== - * Simple callback to post a semaphore for the blocking mode. - */ -static void writeSemCallback(UART_Handle handle, void *buffer, size_t count) -{ - UARTCC32XX_Object *object = handle->object; - - SemaphoreP_post(object->writeSem); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XX.h b/ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XX.h deleted file mode 100644 index af7cb486355..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XX.h +++ /dev/null @@ -1,397 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file UARTCC32XX.h - * - * @brief UART driver implementation for a CC32XX UART controller - * - * The UART header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref UART.h for a complete description of APIs & example of use. - * - * # Device Specific Pin Mode Macros # - * This header file contains pin mode definitions used to specify the - * UART TX and RX pin assignment in the UARTCC32XX_HWAttrsV1 structure. - * Please refer to the CC32XX Techincal Reference Manual for details on pin - * multiplexing. - * - * # Flow Control # - * To enable Flow Control, the RTS and CTS pins must be assigned in the - * ::UARTCC32XX_HWAttrsV1. - * - * ============================================================================ - */ - -#ifndef ti_drivers_uart_UARTCC32XX__include -#define ti_drivers_uart_UARTCC32XX__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#include -#include -#include -#include -#include -#include -#include - - -/*! - * @brief Indicates a pin is not being used - * - * If hardware flow control is not being used, the UART CTS and RTS - * pins should be set to UARTCC32XX_PIN_UNASSIGNED. - */ -#define UARTCC32XX_PIN_UNASSIGNED 0xFFF - -/* - * The bits in the pin mode macros are as follows: - * The lower 8 bits of the macro refer to the pin, offset by 1, to match - * driverlib pin defines. For example, UARTCC32XX_PIN_01_UART1_TX & 0xff = 0, - * which equals PIN_01 in driverlib pin.h. By matching the PIN_xx defines in - * driverlib pin.h, we can pass the pin directly to the driverlib functions. - * The upper 8 bits of the macro correspond to the pin mux confg mode - * value for the pin to operate in the UART mode. For example, pin 1 is - * configured with mode 7 to operate as UART1 TX. - */ -#define UARTCC32XX_PIN_01_UART1_TX 0x700 /*!< PIN 1 is used for UART1 TX */ -#define UARTCC32XX_PIN_02_UART1_RX 0x701 /*!< PIN 2 is used for UART1 RX */ -#define UARTCC32XX_PIN_03_UART0_TX 0x702 /*!< PIN 3 is used for UART0 TX */ -#define UARTCC32XX_PIN_04_UART0_RX 0x703 /*!< PIN 4 is used for UART0 RX */ -#define UARTCC32XX_PIN_07_UART1_TX 0x506 /*!< PIN 7 is used for UART1 TX */ -#define UARTCC32XX_PIN_08_UART1_RX 0x507 /*!< PIN 8 is used for UART1 RX */ -#define UARTCC32XX_PIN_16_UART1_TX 0x20F /*!< PIN 16 is used for UART1 TX */ -#define UARTCC32XX_PIN_17_UART1_RX 0x210 /*!< PIN 17 is used for UART1 RX */ -#define UARTCC32XX_PIN_45_UART0_RX 0x92C /*!< PIN 45 is used for UART0 RX */ -#define UARTCC32XX_PIN_45_UART1_RX 0x22C /*!< PIN 45 is used for UART1 RX */ -#define UARTCC32XX_PIN_53_UART0_TX 0x934 /*!< PIN 53 is used for UART0 TX */ -#define UARTCC32XX_PIN_55_UART0_TX 0x336 /*!< PIN 55 is used for UART0 TX */ -#define UARTCC32XX_PIN_55_UART1_TX 0x636 /*!< PIN 55 is used for UART1 TX */ -#define UARTCC32XX_PIN_57_UART0_RX 0x338 /*!< PIN 57 is used for UART0 RX */ -#define UARTCC32XX_PIN_57_UART1_RX 0x638 /*!< PIN 57 is used for UART1 RX */ -#define UARTCC32XX_PIN_58_UART1_TX 0x639 /*!< PIN 58 is used for UART1 TX */ -#define UARTCC32XX_PIN_59_UART1_RX 0x63A /*!< PIN 59 is used for UART1 RX */ -#define UARTCC32XX_PIN_62_UART0_TX 0xB3D /*!< PIN 62 is used for UART0 TX */ - -/* - * Flow control pins. - */ -#define UARTCC32XX_PIN_50_UART0_CTS 0xC31 /*!< PIN 50 is used for UART0 CTS */ -#define UARTCC32XX_PIN_50_UART0_RTS 0x331 /*!< PIN 50 is used for UART0 RTS */ -#define UARTCC32XX_PIN_50_UART1_RTS 0xA31 /*!< PIN 50 is used for UART1 RTS */ -#define UARTCC32XX_PIN_52_UART0_RTS 0x633 /*!< PIN 52 is used for UART0 RTS */ -#define UARTCC32XX_PIN_61_UART0_RTS 0x53C /*!< PIN 61 is used for UART0 RTS */ -#define UARTCC32XX_PIN_61_UART0_CTS 0x63C /*!< PIN 61 is used for UART0 CTS */ -#define UARTCC32XX_PIN_61_UART1_CTS 0x33C /*!< PIN 61 is used for UART1 CTS */ -#define UARTCC32XX_PIN_62_UART0_RTS 0xA3D /*!< PIN 62 is used for UART0 RTS */ -#define UARTCC32XX_PIN_62_UART1_RTS 0x33D /*!< PIN 62 is used for UART1 RTS */ - -/*! - * @brief No hardware flow control - */ -#define UARTCC32XX_FLOWCTRL_NONE 0 - -/*! - * @brief Hardware flow control - */ -#define UARTCC32XX_FLOWCTRL_HARDWARE 1 - -/** - * @addtogroup UART_STATUS - * UARTCC32XX_STATUS_* macros are command codes only defined in the - * UARTCC32XX.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add UARTCC32XX_STATUS_* macros here */ - -/** @}*/ - -/** - * @addtogroup UART_CMD - * UARTCC32XX_CMD_* macros are command codes only defined in the - * UARTCC32XX.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/*! - * @brief Command used by UART_control to determines - * whether the UART transmitter is busy or not - * - * With this command code, @b arg is a pointer to a @c bool. - * @b *arg contains @c true if the UART is transmitting, - * else @c false if all transmissions are complete. - */ -#define UARTCC32XX_CMD_IS_BUSY (UART_CMD_RESERVED + 0) - - -/*! - * @brief Command used by UART_control to determines - * if there are any characters in the receive FIFO - * - * With this command code, @b arg is a pointer to a @c bool. - * @b *arg contains @c true if there is data in the receive FIFO, - * or @c false if there is no data in the receive FIFO. - */ -#define UARTCC32XX_CMD_IS_RX_DATA_AVAILABLE (UART_CMD_RESERVED + 1) - - -/*! - * @brief Command used by UART_control to determines - * if there is any space in the transmit FIFO - * - * With this command code, @b arg is a pointer to a @c bool. - * @b *arg contains @c true if there is space available in the transmit FIFO, - * or @c false if there is no space available in the transmit FIFO. - */ -#define UARTCC32XX_CMD_IS_TX_SPACE_AVAILABLE (UART_CMD_RESERVED + 2) - - -/** @}*/ - -/* UART function table pointer */ -extern const UART_FxnTable UARTCC32XX_fxnTable; - -/*! - * @brief Complement set of read functions to be used by the UART ISR and - * UARTCC32XX_read(). Internal use only. - * - * These functions are solely intended for the UARTCC32XX driver, and should - * not be used by the application. - * The UARTCC32XX_FxnSet is a pair of complement functions that are design to - * operate with one another in a task context and in an ISR context. The - * readTaskFxn is called by UARTCC32XX_read() to drain a circular buffer, - * whereas the readIsrFxn is used by the UARTCC32XX_hwiIntFxn to fill up the - * circular buffer. - * - * readTaskFxn: Function called by UART read - * These variables are set and avilalable for use to the - * readTaskFxn. - * object->readBuf = buffer; //Pointer to a user buffer - * object->readSize = size; //Desired no. of bytes to read - * object->readCount = size; //Remaining no. of bytes to read - * - * readIsrFxn: The required ISR counterpart to readTaskFxn - */ -typedef struct UARTCC32XX_FxnSet { - bool (*readIsrFxn) (UART_Handle handle); - int (*readTaskFxn) (UART_Handle handle); -} UARTCC32XX_FxnSet; - -/*! - * @brief The definition of an optional callback function used by the UART - * driver to notify the application when a receive error (FIFO overrun, - * parity error, etc) occurs. - * - * @param UART_Handle UART_Handle - * - * @param error The current value of the receive - * status register. Please refer to the - * device data sheet to interpret this - * value. - */ -typedef void (*UARTCC32XX_ErrorCallback) (UART_Handle handle, uint32_t error); - -/*! - * @brief UARTCC32XX Hardware attributes - * - * The fields, baseAddr, intNum, and flowControl, are used by driverlib - * APIs and therefore must be populated by - * driverlib macro definitions. For CC32XXWare these definitions are found in: - * - inc/hw_memmap.h - * - inc/hw_ints.h - * - driverlib/uart.h - * - * intPriority is the UART peripheral's interrupt priority, as defined by the - * underlying OS. It is passed unmodified to the underlying OS's interrupt - * handler creation code, so you need to refer to the OS documentation - * for usage. For example, for SYS/BIOS applications, refer to the - * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of - * interrupt priorities. If the driver uses the ti.dpl interface - * instead of making OS calls directly, then the HwiP port handles the - * interrupt priority in an OS specific way. In the case of the SYS/BIOS - * port, intPriority is passed unmodified to Hwi_create(). - * - * A sample structure is shown below: - * @code - * unsigned char uartCC32XXRingBuffer[2][32]; - * - * const UARTCC32XX_HWAttrsV1 uartCC32XXHWAttrs[] = { - * { - * .baseAddr = UARTA0_BASE, - * .intNum = INT_UARTA0, - * .intPriority = (~0), - * .flowControl = UARTCC32XX_FLOWCTRL_NONE, - * .ringBufPtr = uartCC32XXRingBuffer[0], - * .ringBufSize = sizeof(uartCC32XXRingBuffer[0]), - * .rxPin = UARTCC32XX_PIN_57_UART0_RX, - * .txPin = UARTCC32XX_PIN_55_UART0_TX, - * .rtsPin = UARTCC32XX_PIN_UNASSIGNED, - * .ctsPin = UARTCC32XX_PIN_UNASSIGNED, - * .errorFxn = NULL - * }, - * { - * .baseAddr = UARTA1_BASE, - * .intNum = INT_UARTA1, - * .intPriority = (~0), - * .flowControl = UARTCC32XX_FLOWCTRL_HARDWARE, - * .ringBufPtr = uartCC32XXRingBuffer[1], - * .ringBufSize = sizeof(uartCC32XXRingBuffer[1]), - * .rxPin = UARTCC32XX_PIN_08_UART1_RX, - * .txPin = UARTCC32XX_PIN_07_UART1_TX, - * .rtsPin = UARTCC32XX_PIN_50_UART1_RTS, - * .ctsPin = UARTCC32XX_PIN_61_UART1_CTS, - * .errorFxn = NULL - * }, - * }; - * @endcode - */ -typedef struct UARTCC32XX_HWAttrsV1 { - /*! UART Peripheral's base address */ - unsigned int baseAddr; - /*! UART Peripheral's interrupt vector */ - unsigned int intNum; - /*! UART Peripheral's interrupt priority */ - unsigned int intPriority; - /*! Hardware flow control setting defined by driverlib */ - uint32_t flowControl; - /*! Pointer to an application ring buffer */ - unsigned char *ringBufPtr; - /*! Size of ringBufPtr */ - size_t ringBufSize; - /*! UART RX pin assignment */ - uint16_t rxPin; - /*! UART TX pin assignment */ - uint16_t txPin; - /*! UART clear to send (CTS) pin assignment */ - uint16_t ctsPin; - /*! UART request to send (RTS) pin assignment */ - uint16_t rtsPin; - /*! Application error function to be called on receive errors */ - UARTCC32XX_ErrorCallback errorFxn; -} UARTCC32XX_HWAttrsV1; - -/*! - * @brief UARTCC32XX Object - * - * The application must not access any member variables of this structure! - */ -typedef struct UARTCC32XX_Object { - /* UART state variable */ - struct { - bool opened:1; /* Has the obj been opened */ - UART_Mode readMode:1; /* Mode for all read calls */ - UART_Mode writeMode:1; /* Mode for all write calls */ - UART_DataMode readDataMode:1; /* Type of data being read */ - UART_DataMode writeDataMode:1; /* Type of data being written */ - UART_ReturnMode readReturnMode:1; /* Receive return mode */ - UART_Echo readEcho:1; /* Echo received data back */ - /* - * Flag to determine if a timeout has occurred when the user called - * UART_read(). This flag is set by the timeoutClk clock object. - */ - bool bufTimeout:1; - /* - * Flag to determine when an ISR needs to perform a callback; in both - * UART_MODE_BLOCKING or UART_MODE_CALLBACK - */ - bool callCallback:1; - /* - * Flag to determine if the ISR is in control draining the ring buffer - * when in UART_MODE_CALLBACK - */ - bool drainByISR:1; - /* Flag to keep the state of the read Power constraints */ - bool rxEnabled:1; - /* Flag to keep the state of the write Power constraints */ - bool txEnabled:1; - - /* Flags to prevent recursion in read callback mode */ - bool inReadCallback:1; - volatile bool readCallbackPending:1; - } state; - - HwiP_Handle hwiHandle; /* Hwi handle for interrupts */ - ClockP_Handle timeoutClk; /* Clock object to for timeouts */ - uint32_t baudRate; /* Baud rate for UART */ - UART_LEN dataLength; /* Data length for UART */ - UART_STOP stopBits; /* Stop bits for UART */ - UART_PAR parityType; /* Parity bit type for UART */ - - /* UART read variables */ - RingBuf_Object ringBuffer; /* local circular buffer object */ - /* A complement pair of read functions for both the ISR and UART_read() */ - UARTCC32XX_FxnSet readFxns; - unsigned char *readBuf; /* Buffer data pointer */ - size_t readSize; /* Desired number of bytes to read */ - size_t readCount; /* Number of bytes left to read */ - SemaphoreP_Handle readSem; /* UART read semaphore */ - unsigned int readTimeout; /* Timeout for read semaphore */ - UART_Callback readCallback; /* Pointer to read callback */ - - /* UART write variables */ - const unsigned char *writeBuf; /* Buffer data pointer */ - size_t writeSize; /* Desired number of bytes to write*/ - size_t writeCount; /* Number of bytes left to write */ - SemaphoreP_Handle writeSem; /* UART write semaphore*/ - unsigned int writeTimeout; /* Timeout for write semaphore */ - UART_Callback writeCallback; /* Pointer to write callback */ - - /* For Power management */ - Power_NotifyObj postNotify; /* LPDS wake-up notify object */ - unsigned int powerMgrId; /* Determined from base address */ - PowerCC32XX_ParkState prevParkTX; /* Previous park state TX pin */ - uint16_t txPin; /* TX pin ID */ - PowerCC32XX_ParkState prevParkRTS; /* Previous park state of RTS pin */ - uint16_t rtsPin; /* RTS pin ID */ -} UARTCC32XX_Object, *UARTCC32XX_Handle; - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_uart_UARTCC32XX__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XXDMA.c b/ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XXDMA.c deleted file mode 100644 index 3a2d5d49077..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XXDMA.c +++ /dev/null @@ -1,1130 +0,0 @@ -/* - * Copyright (c) 2014-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include - -/* - * By default disable both asserts and log for this module. - * This must be done before DebugP.h is included. - */ -#ifndef DebugP_ASSERT_ENABLED -#define DebugP_ASSERT_ENABLED 0 -#endif -#ifndef DebugP_LOG_ENABLED -#define DebugP_LOG_ENABLED 0 -#endif - -#include -#include -#include -#include - -#include -#include -#include -#include - -/* driverlib header files */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* DMA can handle transfers of at most 1024 elements */ -#define MAXXFERSIZE 1024 - -/* Pad configuration defines */ -#define PAD_CONFIG_BASE (OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CONFIG_0) -#define PAD_RESET_STATE 0xC61 - -/* UARTCC32XXDMA functions */ -void UARTCC32XXDMA_close(UART_Handle handle); -int_fast16_t UARTCC32XXDMA_control(UART_Handle handle, uint_fast16_t cmd, - void *arg); -void UARTCC32XXDMA_init(UART_Handle handle); -UART_Handle UARTCC32XXDMA_open(UART_Handle handle, UART_Params *params); -int_fast32_t UARTCC32XXDMA_read(UART_Handle handle, void *buffer, size_t size); -void UARTCC32XXDMA_readCancel(UART_Handle handle); -int_fast32_t UARTCC32XXDMA_readPolling(UART_Handle handle, void *buffer, - size_t size); -int_fast32_t UARTCC32XXDMA_write(UART_Handle handle, const void *buffer, - size_t size); -void UARTCC32XXDMA_writeCancel(UART_Handle handle); -int_fast32_t UARTCC32XXDMA_writePolling(UART_Handle handle, const void *buffer, - size_t size); - -/* UART function table for UARTCC32XXDMA implementation */ -const UART_FxnTable UARTCC32XXDMA_fxnTable = { - UARTCC32XXDMA_close, - UARTCC32XXDMA_control, - UARTCC32XXDMA_init, - UARTCC32XXDMA_open, - UARTCC32XXDMA_read, - UARTCC32XXDMA_readPolling, - UARTCC32XXDMA_readCancel, - UARTCC32XXDMA_write, - UARTCC32XXDMA_writePolling, - UARTCC32XXDMA_writeCancel -}; - -/* Static functions */ -static void UARTCC32XXDMA_configDMA(UART_Handle handle, bool isWrite); -static void UARTCC32XXDMA_hwiIntFxn(uintptr_t arg); - -static unsigned int getPowerMgrId(unsigned int baseAddr); -static void initHw(UART_Handle handle); -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg); - -static size_t readCancel(UART_Handle handle); -static void readSemCallback(UART_Handle handle, void *buffer, size_t count); -static void startTxFifoEmptyClk(UART_Handle handle, unsigned int size); -static size_t writeCancel(UART_Handle handle); -static void writeFinishedDoCallback(UART_Handle handle); -static void writeSemCallback(UART_Handle handle, void *buffer, size_t count); - -/* - * Function for checking whether flow control is enabled. - */ -static inline bool isFlowControlEnabled(UARTCC32XXDMA_HWAttrsV1 const *hwAttrs) { - return ((hwAttrs->flowControl == UARTCC32XXDMA_FLOWCTRL_HARDWARE) && - (hwAttrs->ctsPin != UARTCC32XXDMA_PIN_UNASSIGNED) && - (hwAttrs->rtsPin != UARTCC32XXDMA_PIN_UNASSIGNED)); -} - - -static const uint32_t dataLength[] = { - UART_CONFIG_WLEN_5, /* UART_LEN_5 */ - UART_CONFIG_WLEN_6, /* UART_LEN_6 */ - UART_CONFIG_WLEN_7, /* UART_LEN_7 */ - UART_CONFIG_WLEN_8 /* UART_LEN_8 */ -}; - -static const uint32_t stopBits[] = { - UART_CONFIG_STOP_ONE, /* UART_STOP_ONE */ - UART_CONFIG_STOP_TWO /* UART_STOP_TWO */ -}; - -static const uint32_t parityType[] = { - UART_CONFIG_PAR_NONE, /* UART_PAR_NONE */ - UART_CONFIG_PAR_EVEN, /* UART_PAR_EVEN */ - UART_CONFIG_PAR_ODD, /* UART_PAR_ODD */ - UART_CONFIG_PAR_ZERO, /* UART_PAR_ZERO */ - UART_CONFIG_PAR_ONE /* UART_PAR_ONE */ -}; - -/* - * ======== UARTCC32XXDMA_close ======== - */ -void UARTCC32XXDMA_close(UART_Handle handle) -{ - UARTCC32XXDMA_Object *object = handle->object; - UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uint32_t padRegister; - - /* Disable UART and interrupts. */ - MAP_UARTDMADisable(hwAttrs->baseAddr, UART_DMA_TX | UART_DMA_RX); - MAP_UARTDisable(hwAttrs->baseAddr); - - if (object->hwiHandle) { - HwiP_delete(object->hwiHandle); - } - if (object->writeSem) { - SemaphoreP_delete(object->writeSem); - } - if (object->readSem) { - SemaphoreP_delete(object->readSem); - } - if (object->txFifoEmptyClk) { - ClockP_delete(object->txFifoEmptyClk); - } - - if (object->dmaHandle) { - UDMACC32XX_close(object->dmaHandle); - } - - Power_unregisterNotify(&object->postNotify); - Power_releaseDependency(object->powerMgrId); - - if (object->txPin != (uint16_t)-1) { - PowerCC32XX_restoreParkState((PowerCC32XX_Pin)object->txPin, - object->prevParkTX); - object->txPin = (uint16_t)-1; - } - - if (object->rtsPin != (uint16_t)-1) { - PowerCC32XX_restoreParkState((PowerCC32XX_Pin)object->rtsPin, - object->prevParkRTS); - object->rtsPin = (uint16_t)-1; - } - - /* Restore pin pads to their reset states */ - padRegister = (PinToPadGet((hwAttrs->rxPin) & 0xff)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - padRegister = (PinToPadGet((hwAttrs->txPin) & 0xff)<<2) + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - if (isFlowControlEnabled(hwAttrs)) { - padRegister = (PinToPadGet((hwAttrs->ctsPin) & 0xff)<<2) - + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - padRegister = (PinToPadGet((hwAttrs->rtsPin) & 0xff)<<2) - + PAD_CONFIG_BASE; - HWREG(padRegister) = PAD_RESET_STATE; - } - - object->opened = false; - - DebugP_log1("UART:(%p) closed", hwAttrs->baseAddr); -} - -/* - * ======== UARTCC32XXDMA_control ======== - * @pre Function assumes that the handle is not NULL - */ -int_fast16_t UARTCC32XXDMA_control(UART_Handle handle, uint_fast16_t cmd, - void *arg) -{ - UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - switch (cmd) { - /* Specific UART CMDs */ - case (UARTCC32XXDMA_CMD_IS_BUSY): - *(bool *)arg = MAP_UARTBusy(hwAttrs->baseAddr); - return (UART_STATUS_SUCCESS); - - case (UARTCC32XXDMA_CMD_IS_RX_DATA_AVAILABLE): - *(bool *)arg = MAP_UARTCharsAvail(hwAttrs->baseAddr); - return (UART_STATUS_SUCCESS); - - case (UARTCC32XXDMA_CMD_IS_TX_SPACE_AVAILABLE): - *(bool *)arg = MAP_UARTSpaceAvail(hwAttrs->baseAddr); - return (UART_STATUS_SUCCESS); - - default: - DebugP_log2("UART:(%p) UART CMD undefined: %d", - hwAttrs->baseAddr, cmd); - return (UART_STATUS_UNDEFINEDCMD); - } -} - -/* - * ======== UARTCC32XXDMA_init ======== - */ -void UARTCC32XXDMA_init(UART_Handle handle) -{ -} - -/* - * ======== UARTCC32XXDMA_open ======== - */ -UART_Handle UARTCC32XXDMA_open(UART_Handle handle, UART_Params *params) -{ - uintptr_t key; - UARTCC32XXDMA_Object *object = handle->object; - UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - SemaphoreP_Params semParams; - HwiP_Params hwiParams; - ClockP_Params clockParams; - uint16_t pin; - uint16_t mode; - - /* Timeouts cannot be 0 */ - DebugP_assert((params->writeTimeout != 0) && (params->readTimeout != 0)); - - /* Check that a callback is set */ - DebugP_assert((params->readMode != UART_MODE_CALLBACK) || - (params->readCallback != NULL)); - DebugP_assert((params->writeMode != UART_MODE_CALLBACK) || - (params->writeCallback != NULL)); - - /* Initialize the DMA */ - UDMACC32XX_init(); - - object->powerMgrId = getPowerMgrId(hwAttrs->baseAddr); - if (object->powerMgrId == (unsigned int)-1) { - DebugP_log1("UART:(%p) Failed to determine power resource id", - hwAttrs->baseAddr); - return (NULL); - } - - /* Disable preemption while checking if the UART is open. */ - key = HwiP_disable(); - - /* Check if the UART is open already with the base addr. */ - if (object->opened == true) { - HwiP_restore(key); - - DebugP_log1("UART:(%p) already in use.", hwAttrs->baseAddr); - return (NULL); - } - - object->opened = true; - HwiP_restore(key); - - /* - * Register power dependency. Keeps the clock running in SLP - * and DSLP modes. - */ - - Power_setDependency(object->powerMgrId); - - Power_registerNotify(&object->postNotify, PowerCC32XX_AWAKE_LPDS, - postNotifyFxn, (uintptr_t)handle); - - object->readMode = params->readMode; - object->writeMode = params->writeMode; - object->readTimeout = params->readTimeout; - object->writeTimeout = params->writeTimeout; - object->readCallback = params->readCallback; - object->writeCallback = params->writeCallback; - object->readReturnMode = params->readReturnMode; - object->readDataMode = params->readDataMode; - object->writeDataMode = params->writeDataMode; - object->readEcho = params->readEcho; - object->baudRate = params->baudRate; - object->stopBits = params->stopBits; - object->dataLength = params->dataLength; - object->parityType = params->parityType; - - /* Set UART variables to defaults. */ - object->writeBuf = NULL; - object->readBuf = NULL; - object->writeCount = 0; - object->readCount = 0; - object->writeSize = 0; - object->readSize = 0; - object->readSem = NULL; - object->writeSem = NULL; - object->txFifoEmptyClk = NULL; - object->txPin = (uint16_t)-1; - - /* DMA first */ - object->dmaHandle = UDMACC32XX_open(); - if (object->dmaHandle == NULL) { - UARTCC32XXDMA_close(handle); - DebugP_log1("UART:(%p) UDMACC32XX_open() failed.", hwAttrs->baseAddr); - return (NULL); - } - - pin = (hwAttrs->rxPin) & 0xff; - mode = (hwAttrs->rxPin >> 8) & 0xff; - - MAP_PinTypeUART((unsigned long)pin, (unsigned long)mode); - - pin = (hwAttrs->txPin) & 0xff; - mode = (hwAttrs->txPin >> 8) & 0xff; - - MAP_PinTypeUART((unsigned long)pin, (unsigned long)mode); - - /* - * Read and save TX pin park state; set to "don't park" while UART is - * open as device default is logic '1' during LPDS - */ - object->prevParkTX = - (PowerCC32XX_ParkState) PowerCC32XX_getParkState((PowerCC32XX_Pin)pin); - PowerCC32XX_setParkState((PowerCC32XX_Pin)pin, ~1); - object->txPin = pin; - - if (isFlowControlEnabled(hwAttrs)) { - pin = (hwAttrs->ctsPin) & 0xff; - mode = (hwAttrs->ctsPin >> 8) & 0xff; - MAP_PinTypeUART((unsigned long)pin, (unsigned long)mode); - - pin = (hwAttrs->rtsPin) & 0xff; - mode = (hwAttrs->rtsPin >> 8) & 0xff; - MAP_PinTypeUART((unsigned long)pin, (unsigned long)mode); - - /* - * Read and save RTS pin park state; set to "don't park" while UART is - * open as device default is logic '1' during LPDS - */ - object->prevParkRTS = (PowerCC32XX_ParkState)PowerCC32XX_getParkState( - (PowerCC32XX_Pin)pin); - PowerCC32XX_setParkState((PowerCC32XX_Pin)pin, ~1); - object->rtsPin = pin; - - /* Flow control will be enabled in initHw() */ - } - HwiP_clearInterrupt(hwAttrs->intNum); - - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t)handle; - hwiParams.priority = hwAttrs->intPriority; - object->hwiHandle = HwiP_create(hwAttrs->intNum, - UARTCC32XXDMA_hwiIntFxn, - &hwiParams); - if (object->hwiHandle == NULL) { - DebugP_log1("UART:(%p) HwiP_create() failed", hwAttrs->baseAddr); - UARTCC32XXDMA_close(handle); - return (NULL); - } - - /* Disable the UART interrupt. */ - MAP_UARTIntDisable(hwAttrs->baseAddr, - (UART_INT_TX | UART_INT_RX | UART_INT_RT)); - - SemaphoreP_Params_init(&semParams); - semParams.mode = SemaphoreP_Mode_BINARY; - - /* Create semaphores and set callbacks for BLOCKING modes. */ - if (object->writeMode == UART_MODE_BLOCKING) { - object->writeCallback = &writeSemCallback; - - object->writeSem = SemaphoreP_create(0, &semParams); - if (object->writeSem == NULL) { - UARTCC32XXDMA_close(handle); - DebugP_log1("UART:(%p) Failed to create semaphore.", - hwAttrs->baseAddr); - return (NULL); - } - } - - if (object->readMode == UART_MODE_BLOCKING) { - object->readCallback = &readSemCallback; - - object->readSem = SemaphoreP_create(0, &semParams); - if (object->readSem == NULL) { - UARTCC32XXDMA_close(handle); - DebugP_log1("UART:(%p) Failed to create semaphore.", - hwAttrs->baseAddr); - return (NULL); - } - } - - /* - * Clock object to ensure FIFO is drained before releasing Power - * constraints. - */ - ClockP_Params_init(&clockParams); - clockParams.arg = (uintptr_t)handle; - - object->txFifoEmptyClk = ClockP_create((ClockP_Fxn)&writeFinishedDoCallback, - 0 /* timeout */, &(clockParams)); - - if (object->txFifoEmptyClk == NULL) { - UARTCC32XXDMA_close(handle); - DebugP_log1("UART:(%p) ClockP_create() failed.", - hwAttrs->baseAddr); - return (NULL); - } - - /* Initialize the hardware */ - initHw(handle); - - - DebugP_log1("UART:(%p) opened", hwAttrs->baseAddr); - - /* Return the handle */ - return (handle); -} - -/* - * ======== UARTCC32XXDMA_read ======== - */ -int_fast32_t UARTCC32XXDMA_read(UART_Handle handle, void *buffer, size_t size) -{ - uintptr_t key; - UARTCC32XXDMA_Object *object = handle->object; - - /* DMA cannot handle transfer sizes > 1024 elements */ - if (size > MAXXFERSIZE) { - DebugP_log1("UART:(%p) Data size too large.", - ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); - - return (UART_ERROR); - } - - /* Disable preemption while checking if the uart is in use. */ - key = HwiP_disable(); - if (object->readSize) { - HwiP_restore(key); - - DebugP_log1("UART:(%p) Could not read data, uart in use.", - ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); - return (UART_ERROR); - } - - /* Save the data to be read and restore interrupts. */ - object->readBuf = buffer; - object->readSize = size; - object->readCount = 0; - - /* Set constraints to guarantee transaction */ - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* - * Start the DMA transfer. Do this inside the critical - * section to prevent UARTCC32XXDMA_readCancel() being called - * after object->readSize is set, but before the DMA is - * configured. If that happened, the size in the DMA control - * register would be 0, causing UARTCC32XXDMA_readCancel() - * to assume all bytes were transferred. - */ - UARTCC32XXDMA_configDMA(handle, false /* isWrite */); - - HwiP_restore(key); - - /* If readMode is blocking, block and get the status. */ - if (object->readMode == UART_MODE_BLOCKING) { - - /* Pend on semaphore and wait for Hwi to finish. */ - if (SemaphoreP_OK != SemaphoreP_pend(object->readSem, - object->readTimeout)) { - key = HwiP_disable(); - - /* Cancel the DMA without posting the semaphore */ - (void)readCancel(handle); - - /* - * If ISR ran after timeout, but before the call to - * readCancel(), readSem would be posted. Pend on - * the semaphore with 0 timeout so the next read - * will block. - */ - if (object->readCount == size) { - SemaphoreP_pend(object->readSem, 0); - } - - HwiP_restore(key); - - DebugP_log2("UART:(%p) Read timed out, %d bytes read", - ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr, - object->readCount); - - } - return (object->readCount); - } - - return (0); -} - -/* - * ======== UARTCC32XXDMA_readPolling ======== - */ -int_fast32_t UARTCC32XXDMA_readPolling(UART_Handle handle, void *buf, - size_t size) -{ - int32_t count = 0; - UARTCC32XXDMA_Object *object = handle->object; - UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - unsigned char *buffer = (unsigned char *)buf; - - /* Read characters. */ - while (size) { - *buffer = MAP_UARTCharGet(hwAttrs->baseAddr); - DebugP_log2("UART:(%p) Read character 0x%x", - hwAttrs->baseAddr, *buffer); - count++; - size--; - - if (object->readDataMode == UART_DATA_TEXT && *buffer == '\r') { - /* Echo character if enabled. */ - if (object->readEcho) { - MAP_UARTCharPut(hwAttrs->baseAddr, '\r'); - } - *buffer = '\n'; - } - - /* Echo character if enabled. */ - if (object->readEcho) { - MAP_UARTCharPut(hwAttrs->baseAddr, *buffer); - } - - /* If read return mode is newline, finish if a newline was received. */ - if (object->readReturnMode == UART_RETURN_NEWLINE && - *buffer == '\n') { - return (count); - } - - buffer++; - } - - DebugP_log2("UART:(%p) Read polling finished, %d bytes read", - hwAttrs->baseAddr, count); - - return (count); -} - -/* - * ======== UARTCC32XXDMA_readCancel ======== - */ -void UARTCC32XXDMA_readCancel(UART_Handle handle) -{ - UARTCC32XXDMA_Object *object = handle->object; - size_t size; - - /* Stop any ongoing DMA read */ - size = readCancel(handle); - - if (size == 0) { - return; - } - - if (object->readMode == UART_MODE_CALLBACK) { - object->readCallback(handle, object->readBuf, object->readCount); - } - else if (object->readMode == UART_MODE_BLOCKING) { - /* We don't know if we're in an ISR, but we'll assume not. */ - SemaphoreP_post(object->readSem); - } - - DebugP_log1("UART:(%p) Read canceled, 0 bytes read", - ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); -} - -/* - * ======== UARTCC32XXDMA_write ======== - */ -int_fast32_t UARTCC32XXDMA_write(UART_Handle handle, const void *buffer, - size_t size) -{ - uintptr_t key; - UARTCC32XXDMA_Object *object = handle->object; - - /* DMA cannot handle transfer sizes > 1024 elements */ - if (size > MAXXFERSIZE) { - DebugP_log1("UART:(%p) Data size too large.", - ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); - - return (UART_ERROR); - } - - /* Disable preemption while checking if the uart is in use. */ - key = HwiP_disable(); - if (object->writeSize) { - HwiP_restore(key); - DebugP_log1("UART:(%p) Could not write data, uart in use.", - ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr); - - return (UART_ERROR); - } - - /* Save the data to be written and restore interrupts. */ - object->writeBuf = buffer; - object->writeCount = 0; - object->writeSize = size; - - /* Set constraints to guarantee transaction */ - Power_setConstraint(PowerCC32XX_DISALLOW_LPDS); - - UARTCC32XXDMA_configDMA(handle, true /* isWrite */); - - HwiP_restore(key); - - /* If writeMode is blocking, block and get the status. */ - if (object->writeMode == UART_MODE_BLOCKING) { - /* Pend on semaphore and wait for Hwi to finish. */ - if (SemaphoreP_OK != SemaphoreP_pend(object->writeSem, - object->writeTimeout)) { - - key = HwiP_disable(); - - /* Stop any ongoing DMA writes and release Power constraints. */ - (void)writeCancel(handle); - - /* - * If ISR ran after timeout, but before the call to - * writeCancel(), writeSem would be posted. Pend on - * the semaphore so the next write call will block. - */ - if (object->writeCount == size) { - SemaphoreP_pend(object->writeSem, 0); - } - - HwiP_restore(key); - - DebugP_log2("UART:(%p) Write timed out, %d bytes written", - ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr, - object->writeCount); - - } - return (object->writeCount); - } - - return (0); -} - -/* - * ======== UARTCC32XXDMA_writePolling ======== - */ -int_fast32_t UARTCC32XXDMA_writePolling(UART_Handle handle, const void *buf, - size_t size) -{ - int32_t count = 0; - UARTCC32XXDMA_Object *object = handle->object; - UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - unsigned char *buffer = (unsigned char *)buf; - - /* Write characters. */ - while (size) { - if (object->writeDataMode == UART_DATA_TEXT && *buffer == '\n') { - MAP_UARTCharPut(hwAttrs->baseAddr, '\r'); - count++; - } - MAP_UARTCharPut(hwAttrs->baseAddr, *buffer); - - DebugP_log2("UART:(%p) Wrote character 0x%x", - ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr, - *buffer); - buffer++; - count++; - size--; - } - - DebugP_log2("UART:(%p) Write polling finished, %d bytes written", - ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr, - count); - - return (count); -} - -/* - * ======== UARTCC32XXDMA_writeCancel ======== - */ -void UARTCC32XXDMA_writeCancel(UART_Handle handle) -{ - UARTCC32XXDMA_Object *object = handle->object; - size_t size; - - /* Stop any ongoing DMA transmits */ - size = writeCancel(handle); - - if (size == 0) { - return; - } - - if (object->writeMode == UART_MODE_CALLBACK) { - object->writeCallback(handle, (uint8_t*)object->writeBuf, - object->writeCount); - } - else if (object->writeMode == UART_MODE_BLOCKING) { - /* We don't know if we're in an ISR, but we'll assume not. */ - SemaphoreP_post(object->writeSem); - } - - DebugP_log2("UART:(%p) Write canceled, %d bytes written", - ((UARTCC32XXDMA_HWAttrsV1 const *)(handle->hwAttrs))->baseAddr, - object->writeCount); -} - -/* - * ======== UARTCC32XXDMA_configDMA ======== - * Call with interrupts disabled. - */ -static void UARTCC32XXDMA_configDMA(UART_Handle handle, bool isWrite) -{ - UARTCC32XXDMA_Object *object = handle->object; - UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - unsigned long channelControlOptions; - - if (isWrite) { - channelControlOptions = UDMA_SIZE_8 | UDMA_SRC_INC_8 | - UDMA_DST_INC_NONE | UDMA_ARB_4; - - MAP_uDMAChannelControlSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT, - channelControlOptions); - - MAP_uDMAChannelTransferSet(hwAttrs->txChannelIndex | UDMA_PRI_SELECT, - UDMA_MODE_BASIC, - (void *)object->writeBuf, - (void *)(hwAttrs->baseAddr + UART_O_DR), - object->writeSize); - - /* - * Enable the DMA channel - * This sets the channel's corresponding bit in the uDMA ENASET register. - * The bit will be cleared when the transfer completes. - */ - MAP_uDMAChannelEnable(hwAttrs->txChannelIndex); - - MAP_UARTIntClear(hwAttrs->baseAddr, UART_INT_DMATX); - MAP_UARTIntEnable(hwAttrs->baseAddr, UART_INT_DMATX); - } - else { - channelControlOptions = UDMA_SIZE_8 | UDMA_SRC_INC_NONE | - UDMA_DST_INC_8 | UDMA_ARB_4; - - MAP_uDMAChannelControlSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT, - channelControlOptions); - - MAP_uDMAChannelTransferSet(hwAttrs->rxChannelIndex | UDMA_PRI_SELECT, - UDMA_MODE_BASIC, - (void *)(hwAttrs->baseAddr + UART_O_DR), - object->readBuf, - object->readSize); - - /* Enable DMA Channel */ - MAP_uDMAChannelEnable(hwAttrs->rxChannelIndex); - - MAP_UARTIntClear(hwAttrs->baseAddr, UART_INT_DMARX); - MAP_UARTIntEnable(hwAttrs->baseAddr, UART_INT_DMARX); - } - - DebugP_log1("UART:(%p) DMA transfer enabled", hwAttrs->baseAddr); - - if (isWrite) { - DebugP_log3("UART:(%p) DMA transmit, txBuf: %p; Count: %d", - hwAttrs->baseAddr, (uintptr_t)(object->writeBuf), - object->writeSize); - } - else { - DebugP_log3("UART:(%p) DMA receive, rxBuf: %p; Count: %d", - hwAttrs->baseAddr, (uintptr_t)(object->readBuf), - object->readSize); - } -} - -/* - * ======== UARTCC32XXDMA_hwiIntFxn ======== - * Hwi function that processes UART interrupts. - * - * Three UART interrupts are enabled: Transmit FIFO is 4/8 empty, - * receive FIFO is 4/8 full and a receive timeout between the time - * the last character was received. - * - * @param(arg) The UART_Handle for this Hwi. - */ -static void UARTCC32XXDMA_hwiIntFxn(uintptr_t arg) -{ - uint32_t status; - UARTCC32XXDMA_Object *object = ((UART_Handle)arg)->object; - UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = ((UART_Handle)arg)->hwAttrs; - - /* - * Clear interrupts - * UARTIntStatus(base, false) - read the raw interrupt status - * UARTIntStatus(base, true) - read masked interrupt status - */ - status = MAP_UARTIntStatus(hwAttrs->baseAddr, false); - if (status & UART_INT_DMATX) { - MAP_UARTIntDisable(hwAttrs->baseAddr, UART_INT_DMATX); - MAP_UARTIntClear(hwAttrs->baseAddr, UART_INT_DMATX); - } - - if (status & UART_INT_DMARX) { - MAP_UARTIntDisable(hwAttrs->baseAddr, UART_INT_DMARX); - MAP_UARTIntClear(hwAttrs->baseAddr, UART_INT_DMARX); - } - - DebugP_log2("UART:(%p) Interrupt with mask 0x%x", - hwAttrs->baseAddr, status); - - /* Read data if characters are available. */ - if (object->readSize && - !MAP_uDMAChannelIsEnabled(hwAttrs->rxChannelIndex)) { - object->readCount = object->readSize; - object->readSize = 0; - object->readCallback((UART_Handle)arg, object->readBuf, - object->readCount); - - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - - DebugP_log2("UART:(%p) Read finished, %d bytes read", - hwAttrs->baseAddr, object->readCount); - } - - /* Write completed. */ - if (object->writeSize && - !MAP_uDMAChannelIsEnabled(hwAttrs->txChannelIndex)) { - object->writeCount = object->writeSize; - object->writeSize = 0; - /* - * No more to write, but data is not shifted out yet. - * Start TX FIFO Empty clock. - * + 4 because it is 4 bytes left in TX FIFO when the TX FIFO - * threshold interrupt occurs. - */ - startTxFifoEmptyClk((UART_Handle)arg, 4); - - DebugP_log2("UART:(%p) Write finished, %d bytes written", - hwAttrs->baseAddr, object->writeCount); - } -} - -/* - * ======== getPowerMgrId ======== - */ -static unsigned int getPowerMgrId(unsigned int baseAddr) -{ - switch (baseAddr) { - case UARTA0_BASE: - return (PowerCC32XX_PERIPH_UARTA0); - case UARTA1_BASE: - return (PowerCC32XX_PERIPH_UARTA1); - default: - return ((unsigned int)-1); - } -} - -/* - * ======== initHw ======== - * Initialize the hardware. - */ -static void initHw(UART_Handle handle) -{ - ClockP_FreqHz freq; - UARTCC32XXDMA_Object *object = handle->object; - UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - - /* - * Set the FIFO level to 4/8 empty and 4/8 full. - * The UART generates a burst request based on the FIFO trigger - * level. The arbitration size should be set to the amount - * of data that the FIFO can transfer when the trigger level is reached. - * Since arbitration size is a power of 2, we'll set the FIFO levels - * to 4_8 so they can match the arbitration size of 4. - */ - MAP_UARTFIFOLevelSet(hwAttrs->baseAddr, UART_FIFO_TX4_8, UART_FIFO_RX4_8); - - if (isFlowControlEnabled(hwAttrs)) { - /* Set flow control */ - MAP_UARTFlowControlSet(hwAttrs->baseAddr, - UART_FLOWCONTROL_TX | UART_FLOWCONTROL_RX); - } - else { - MAP_UARTFlowControlSet(hwAttrs->baseAddr, UART_FLOWCONTROL_NONE); - } - - ClockP_getCpuFreq(&freq); - MAP_UARTConfigSetExpClk(hwAttrs->baseAddr, - freq.lo, - object->baudRate, - dataLength[object->dataLength] | - stopBits[object->stopBits] | - parityType[object->parityType]); - - MAP_UARTDMAEnable(hwAttrs->baseAddr, UART_DMA_TX | UART_DMA_RX); - - /* Configure DMA for TX and RX */ - MAP_uDMAChannelAssign(hwAttrs->txChannelIndex); - MAP_uDMAChannelAttributeDisable(hwAttrs->txChannelIndex, UDMA_ATTR_ALTSELECT); - - MAP_uDMAChannelAssign(hwAttrs->rxChannelIndex); - MAP_uDMAChannelAttributeDisable(hwAttrs->rxChannelIndex, UDMA_ATTR_ALTSELECT); - MAP_UARTEnable(hwAttrs->baseAddr); -} - -/* - * ======== postNotifyFxn ======== - * Called by Power module when waking up from LPDS. - */ -static int postNotifyFxn(unsigned int eventType, uintptr_t eventArg, - uintptr_t clientArg) -{ - initHw((UART_Handle)clientArg); - - return (Power_NOTIFYDONE); -} - -/* - * ======== readCancel ======== - * Stop the current DMA receive transfer. - */ -static size_t readCancel(UART_Handle handle) -{ - uintptr_t key; - UARTCC32XXDMA_Object *object = handle->object; - UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uint32_t remainder; - int bytesTransferred; - size_t size; - - /* Disable interrupts to avoid reading data while changing state. */ - key = HwiP_disable(); - - size = object->readSize; - - /* Return if there is no read. */ - if (!object->readSize) { - HwiP_restore(key); - return (size); - } - - /* Set channel bit in the ENACLR register */ - MAP_uDMAChannelDisable(hwAttrs->rxChannelIndex); - - remainder = MAP_uDMAChannelSizeGet(hwAttrs->rxChannelIndex); - bytesTransferred = object->readSize - remainder; - - /* - * Since object->readSize != 0, the ISR has not run and released - * the Power constraint. Release the constraint here. Setting - * object->readSize to 0 will prevent the ISR from releasing the - * constraint in case it is pending. - */ - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* Set size = 0 to prevent reading and restore interrupts. */ - object->readSize = 0; - object->readCount = bytesTransferred; - - HwiP_restore(key); - - return (size); -} - -/* - * ======== readSemCallback ======== - * Simple callback to post a semaphore for the blocking mode. - */ -static void readSemCallback(UART_Handle handle, void *buffer, size_t count) -{ - UARTCC32XXDMA_Object *object = handle->object; - - SemaphoreP_post(object->readSem); -} - -/* - * ======== writeSemCallback ======== - * Simple callback to post a semaphore for the blocking mode. - */ -static void writeSemCallback(UART_Handle handle, void *buffer, size_t count) -{ - UARTCC32XXDMA_Object *object = handle->object; - - SemaphoreP_post(object->writeSem); -} - -/* - * ======== writeCancel ======== - */ -static size_t writeCancel(UART_Handle handle) -{ - uintptr_t key; - UARTCC32XXDMA_Object *object = handle->object; - UARTCC32XXDMA_HWAttrsV1 const *hwAttrs = handle->hwAttrs; - uint32_t remainder; - int bytesTransferred; - size_t size; - - /* Disable interrupts to avoid writing data while changing state. */ - key = HwiP_disable(); - - size = object->writeSize; - - /* Set channel bit in the ENACLR register */ - MAP_uDMAChannelDisable(hwAttrs->txChannelIndex); - - remainder = MAP_uDMAChannelSizeGet(hwAttrs->txChannelIndex); - bytesTransferred = object->writeSize - remainder; - - /* Return if there is no write. */ - if (!object->writeSize) { - HwiP_restore(key); - - return (size); - } - - /* - * If the transfer didn't complete, the ISR will not run to - * release the Power constraint, so do it here. - */ - if (bytesTransferred < object->writeSize) { - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - } - - /* Set size = 0 to prevent writing and restore interrupts. */ - object->writeSize = 0; - object->writeCount = bytesTransferred; - - HwiP_restore(key); - - return (size); -} - -/* - * ======== startTxFifoEmptyClk ======== - * Last write to TX FIFO is done, but not shifted out yet. Start a clock - * which will trigger when the TX FIFO should be empty. - * - * @param(handle) The UART_Handle for ongoing write. - * @param(numData) The number of data present in FIFO after last write - */ -static void startTxFifoEmptyClk(UART_Handle handle, unsigned int numData) -{ - UARTCC32XXDMA_Object *object = handle->object; - unsigned int writeTimeout; - unsigned int ticksPerSec; - - /* No more to write, but data is not shiftet out properly yet. - * 1. Compute appropriate wait time for FIFO to empty out - * - 8 - for maximum data length - * - 3 - for one start bit and maximum of two stop bits - */ - ticksPerSec = 1000000 / ClockP_getSystemTickPeriod(); - writeTimeout = ((numData * (8 + 3) * ticksPerSec) + object->baudRate - 1) - / object->baudRate; - - /* 2. Configure clock object to trigger when FIFO is empty */ - ClockP_setTimeout(object->txFifoEmptyClk, writeTimeout); - ClockP_start(object->txFifoEmptyClk); -} - -/* - * ======== writeFinishedDoCallback ======== - * Write finished - make callback - * - * This function is called when the txFifoEmptyClk times out. The TX FIFO - * should now be empty. Standby is allowed again. - * - * @param(handle) The UART_Handle for ongoing write. - */ -static void writeFinishedDoCallback(UART_Handle handle) -{ - UARTCC32XXDMA_Object *object; - UARTCC32XXDMA_HWAttrsV1 const *hwAttrs; - - /* Get the pointer to the object and hwAttrs */ - object = handle->object; - hwAttrs = handle->hwAttrs; - - /* Stop the txFifoEmpty clock */ - ClockP_stop((ClockP_Handle)object->txFifoEmptyClk); - - /* 1. Function verifies that the FIFO is empty via BUSY flag */ - /* 2. Polls this flag if not yet ready (should not be necessary) */ - while (MAP_UARTBusy(hwAttrs->baseAddr)); - - /* Release constraint since transaction is done */ - Power_releaseConstraint(PowerCC32XX_DISALLOW_LPDS); - - /* Make callback */ - object->writeCallback(handle, (uint8_t *)object->writeBuf, - object->writeCount); - DebugP_log2("UART:(%p) Write finished, %d bytes written", - hwAttrs->baseAddr, object->writeCount); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XXDMA.h b/ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XXDMA.h deleted file mode 100644 index 94429c21f10..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/uart/UARTCC32XXDMA.h +++ /dev/null @@ -1,350 +0,0 @@ -/* - * Copyright (c) 2014-2017, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file UARTCC32XXDMA.h - * - * @brief UART driver implementation for a CC32XX UART controller, using - * the micro DMA controller. - * - * The UART header file should be included in an application as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref UART.h for a complete description of APIs & example of use. - * - * - * # Device Specific Pin Mode Macros # - * This header file contains pin mode definitions used to specify the - * UART TX and RX pin assignment in the UARTCC32XXDMA_HWAttrsV1 structure. - * Please refer to the CC32XX Techincal Reference Manual for details on pin - * multiplexing. - * - * # Flow Control # - * To enable Flow Control, the RTS and CTS pins must be assigned in the - * ::UARTCC32XX_HWAttrsV1. - * - * ============================================================================ - */ - -#ifndef ti_drivers_uart_UARTCC32XXDMA__include -#define ti_drivers_uart_UARTCC32XXDMA__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - - -/*! - * @brief Indicates a pin is not being used - * - * If hardware flow control is not being used, the UART CTS and RTS - * pins should be set to UARTCC32XX_PIN_UNASSIGNED. - */ -#define UARTCC32XXDMA_PIN_UNASSIGNED 0xFFF -/* - * The bits in the pin mode macros are as follows: - * The lower 8 bits of the macro refer to the pin, offset by 1, to match - * driverlib pin defines. For example, UARTCC32XXDMA_PIN_01_UART1_TX & 0xff = 0, - * which equals PIN_01 in driverlib pin.h. By matching the PIN_xx defines in - * driverlib pin.h, we can pass the pin directly to the driverlib functions. - * The upper 8 bits of the macro correspond to the pin mux confg mode - * value for the pin to operate in the UART mode. For example, pin 1 is - * configured with mode 7 to operate as UART1 TX. - */ -#define UARTCC32XXDMA_PIN_01_UART1_TX 0x700 /*!< PIN 1 is used for UART1 TX */ -#define UARTCC32XXDMA_PIN_02_UART1_RX 0x701 /*!< PIN 2 is used for UART1 RX */ -#define UARTCC32XXDMA_PIN_03_UART0_TX 0x702 /*!< PIN 3 is used for UART0 TX */ -#define UARTCC32XXDMA_PIN_04_UART0_RX 0x703 /*!< PIN 4 is used for UART0 RX */ -#define UARTCC32XXDMA_PIN_07_UART1_TX 0x506 /*!< PIN 7 is used for UART1 TX */ -#define UARTCC32XXDMA_PIN_08_UART1_RX 0x507 /*!< PIN 8 is used for UART1 RX */ -#define UARTCC32XXDMA_PIN_16_UART1_TX 0x20F /*!< PIN 16 is used for UART1 TX */ -#define UARTCC32XXDMA_PIN_17_UART1_RX 0x210 /*!< PIN 17 is used for UART1 RX */ -#define UARTCC32XXDMA_PIN_45_UART0_RX 0x92C /*!< PIN 45 is used for UART0 RX */ -#define UARTCC32XXDMA_PIN_45_UART1_RX 0x22C /*!< PIN 45 is used for UART1 RX */ -#define UARTCC32XXDMA_PIN_53_UART0_TX 0x934 /*!< PIN 53 is used for UART0 TX */ -#define UARTCC32XXDMA_PIN_55_UART0_TX 0x336 /*!< PIN 55 is used for UART0 TX */ -#define UARTCC32XXDMA_PIN_55_UART1_TX 0x636 /*!< PIN 55 is used for UART1 TX */ -#define UARTCC32XXDMA_PIN_57_UART0_RX 0x338 /*!< PIN 57 is used for UART0 RX */ -#define UARTCC32XXDMA_PIN_57_UART1_RX 0x638 /*!< PIN 57 is used for UART1 RX */ -#define UARTCC32XXDMA_PIN_58_UART1_TX 0x639 /*!< PIN 58 is used for UART1 TX */ -#define UARTCC32XXDMA_PIN_59_UART1_RX 0x63A /*!< PIN 59 is used for UART1 RX */ -#define UARTCC32XXDMA_PIN_62_UART0_TX 0xB3D /*!< PIN 62 is used for UART0 TX */ - -/* - * Flow control pins. - */ -#define UARTCC32XXDMA_PIN_50_UART0_CTS 0xC31 /*!< PIN 50 is used for UART0 CTS */ -#define UARTCC32XXDMA_PIN_50_UART0_RTS 0x331 /*!< PIN 50 is used for UART0 RTS */ -#define UARTCC32XXDMA_PIN_50_UART1_RTS 0xA31 /*!< PIN 50 is used for UART1 RTS */ -#define UARTCC32XXDMA_PIN_52_UART0_RTS 0x633 /*!< PIN 52 is used for UART0 RTS */ -#define UARTCC32XXDMA_PIN_61_UART0_RTS 0x53C /*!< PIN 61 is used for UART0 RTS */ -#define UARTCC32XXDMA_PIN_61_UART0_CTS 0x63C /*!< PIN 61 is used for UART0 CTS */ -#define UARTCC32XXDMA_PIN_61_UART1_CTS 0x33C /*!< PIN 61 is used for UART1 CTS */ -#define UARTCC32XXDMA_PIN_62_UART0_RTS 0xA3D /*!< PIN 62 is used for UART0 RTS */ -#define UARTCC32XXDMA_PIN_62_UART1_RTS 0x33D /*!< PIN 62 is used for UART1 RTS */ - -/*! - * @brief No hardware flow control - */ -#define UARTCC32XXDMA_FLOWCTRL_NONE 0 - -/*! - * @brief Hardware flow control - */ -#define UARTCC32XXDMA_FLOWCTRL_HARDWARE 1 - -/** - * @addtogroup UART_STATUS - * UARTCC32XXDMA_STATUS_* macros are command codes only defined in the - * UARTCC32XXDMA.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add UARTCC32XXDMA_STATUS_* macros here */ - -/** @}*/ - -/** - * @addtogroup UART_CMD - * UARTCC32XXDMA_CMD_* macros are command codes only defined in the - * UARTCC32XXDMA.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/*! - * @brief Command used by UART_control to determines - * whether the UART transmitter is busy or not - * - * With this command code, @b arg is a pointer to a @c bool. - * @b *arg contains @c true if the UART is transmitting, - * else @c false if all transmissions are complete. - */ -#define UARTCC32XXDMA_CMD_IS_BUSY (UART_CMD_RESERVED + 0) - - -/*! - * @brief Command used by UART_control to determines - * if there are any characters in the receive FIFO - * - * With this command code, @b arg is a pointer to a @c bool. - * @b *arg contains @c true if there is data in the receive FIFO, - * or @c false if there is no data in the receive FIFO. - */ -#define UARTCC32XXDMA_CMD_IS_RX_DATA_AVAILABLE (UART_CMD_RESERVED + 1) - - -/*! - * @brief Command used by UART_control to determines - * if there is any space in the transmit FIFO - * - * With this command code, @b arg is a pointer to a @c bool. - * @b *arg contains @c true if there is space available in the transmit FIFO, - * or @c false if there is no space available in the transmit FIFO. - */ -#define UARTCC32XXDMA_CMD_IS_TX_SPACE_AVAILABLE (UART_CMD_RESERVED + 2) - - -/** @}*/ - -/* UART function table pointer */ -extern const UART_FxnTable UARTCC32XXDMA_fxnTable; - -/*! - * @brief The definition of an optional callback function used by the UART - * driver to notify the application when a receive error (FIFO overrun, - * parity error, etc) occurs. - * - * @param UART_Handle UART_Handle - * - * @param error The current value of the receive - * status register. Please refer to the - * device data sheet to interpret this - * value. - */ -typedef void (*UARTCC32XXDMA_ErrorCallback) (UART_Handle handle, uint32_t error); - -/*! - * @brief UARTCC32XXDMA Hardware attributes - * - * These fields, with the exception of intPriority, - * are used by driverlib APIs and therefore must be populated by - * driverlib macro definitions. For CC32XXWare these definitions are found in: - * - inc/hw_memmap.h - * - inc/hw_ints.h - * - * intPriority is the UART peripheral's interrupt priority, as defined by the - * underlying OS. It is passed unmodified to the underlying OS's interrupt - * handler creation code, so you need to refer to the OS documentation - * for usage. For example, for SYS/BIOS applications, refer to the - * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of - * interrupt priorities. If the driver uses the ti.dpl interface - * instead of making OS calls directly, then the HwiP port handles the - * interrupt priority in an OS specific way. In the case of the SYS/BIOS - * port, intPriority is passed unmodified to Hwi_create(). - * - * A sample structure is shown below: - * @code - * const UARTCC32XXDMA_HWAttrsV1 uartCC32XXHWAttrs[] = { - * { - * .baseAddr = UARTA0_BASE, - * .intNum = INT_UARTA0, - * .intPriority = (~0), - * .flowControl = UARTCC32XXDMA_FLOWCTRL_NONE, - * .rxChannelIndex = DMA_CH8_UARTA0_RX, - * .txChannelIndex = UDMA_CH9_UARTA0_TX, - * .rxPin = UARTCC32XXDMA_PIN_57_UART0_RX, - * .txPin = UARTCC32XXDMA_PIN_55_UART0_TX, - * .rtsPin = UARTCC32XXDMA_PIN_UNASSIGNED, - * .ctsPin = UARTCC32XX_DMA_PIN_UNASSIGNED, - * .errorFxn = NULL - * }, - * { - * .baseAddr = UARTA1_BASE, - * .intNum = INT_UARTA1, - * .intPriority = (~0), - * .flowControl = UARTCC32XXDMA_FLOWCTRL_HARDWARE, - * .rxChannelIndex = UDMA_CH10_UARTA1_RX, - * .txChannelIndex = UDMA_CH11_UARTA1_TX, - * .rxPin = UARTCC32XXDMA_PIN_08_UART1_RX, - * .txPin = UARTCC32XXDMA_PIN_07_UART1_TX, - * .rtsPin = UARTCC32XXDMA_PIN_50_UART1_RTS, - * .ctsPin = UARTCC32XXDMA_PIN_61_UART1_CTS, - * .errorFxn = NULL - * }, - * }; - * @endcode - */ -typedef struct UARTCC32XXDMA_HWAttrsV1 { - /*! UART Peripheral's base address */ - unsigned int baseAddr; - /*! UART Peripheral's interrupt vector */ - unsigned int intNum; - /*! UART Peripheral's interrupt priority */ - unsigned int intPriority; - /*! Hardware flow control setting defined by driverlib */ - uint32_t flowControl; - /*! uDMA controlTable receive channel index */ - unsigned long rxChannelIndex; - /*! uDMA controlTable transmit channel index */ - unsigned long txChannelIndex; - /*! UART RX pin assignment */ - uint16_t rxPin; - /*! UART TX pin assignment */ - uint16_t txPin; - /*! UART clear to send (CTS) pin assignment */ - uint16_t ctsPin; - /*! UART request to send (RTS) pin assignment */ - uint16_t rtsPin; - /*! - * Application error function to be called on receive errors. - * Note: The UARTCC32XXDMA driver currently does not use this function. - */ - UARTCC32XXDMA_ErrorCallback errorFxn; -} UARTCC32XXDMA_HWAttrsV1; - -/*! - * @brief UARTCC32XXDMA Object - * - * The application must not access any member variables of this structure! - */ -typedef struct UARTCC32XXDMA_Object { - /* UART control variables */ - bool opened; /* Has the obj been opened */ - UART_Mode readMode; /* Mode for all read calls */ - UART_Mode writeMode; /* Mode for all write calls */ - unsigned int readTimeout; /* Timeout for read semaphore */ - unsigned int writeTimeout; /* Timeout for write semaphore */ - UART_Callback readCallback; /* Pointer to read callback */ - UART_Callback writeCallback; /* Pointer to write callback */ - UART_ReturnMode readReturnMode; /* Receive return mode */ - UART_DataMode readDataMode; /* Type of data being read */ - UART_DataMode writeDataMode; /* Type of data being written */ - uint32_t baudRate; /* Baud rate for UART */ - UART_LEN dataLength; /* Data length for UART */ - UART_STOP stopBits; /* Stop bits for UART */ - UART_PAR parityType; /* Parity bit type for UART */ - UART_Echo readEcho; /* Echo received data back */ - - /* UART write variables */ - const void *writeBuf; /* Buffer data pointer */ - size_t writeCount; /* Number of Chars sent */ - size_t writeSize; /* Chars remaining in buffer */ - - /* UART receive variables */ - void *readBuf; /* Buffer data pointer */ - size_t readCount; /* Number of Chars read */ - size_t readSize; /* Chars remaining in buffer */ - - /* Semaphores for blocking mode */ - SemaphoreP_Handle writeSem; /* UART write semaphore */ - SemaphoreP_Handle readSem; /* UART read semaphore */ - - HwiP_Handle hwiHandle; - - /* For Power management */ - ClockP_Handle txFifoEmptyClk; /* UART TX FIFO empty clock */ - Power_NotifyObj postNotify; /* LPDS wake-up notify object */ - unsigned int powerMgrId; /* Determined from base address */ - PowerCC32XX_ParkState prevParkTX; /* Previous park state TX pin */ - uint16_t txPin; /* TX pin ID */ - PowerCC32XX_ParkState prevParkRTS; /* Previous park state of RTS pin */ - uint16_t rtsPin; /* RTS pin ID */ - - /* UDMA */ - UDMACC32XX_Handle dmaHandle; -} UARTCC32XXDMA_Object, *UARTCC32XXDMA_Handle; - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_uart_UARTCC32XXDMA__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/utils/List.c b/ext/hal/ti/simplelink/source/ti/drivers/utils/List.c deleted file mode 100644 index 970ae162263..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/utils/List.c +++ /dev/null @@ -1,182 +0,0 @@ -/* - * Copyright (c) 2015, 2017 Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/* - * ======== List.c ======== - */ -#include -#include - -#include -#include -#include - -/* - * ======== List_clearList ======== - */ -void List_clearList(List_List *list) -{ - uintptr_t key; - - key = HwiP_disable(); - - list->head = list->tail = NULL; - - HwiP_restore(key); -} - - - -/* - * ======== List_get ======== - */ -List_Elem *List_get(List_List *list) -{ - List_Elem *elem; - uintptr_t key; - - key = HwiP_disable(); - - elem = list->head; - - /* See if the List was empty */ - if (elem != NULL) { - list->head = elem->next; - if (elem->next != NULL) { - elem->next->prev = NULL; - } - else { - list->tail = NULL; - } - } - - HwiP_restore(key); - - return (elem); -} - - -/* - * ======== List_insert ======== - */ -void List_insert(List_List *list, List_Elem *newElem, List_Elem *curElem) -{ - uintptr_t key; - - key = HwiP_disable(); - - newElem->next = curElem; - newElem->prev = curElem->prev; - if (curElem->prev != NULL) { - curElem->prev->next = newElem; - } - else { - list->head = newElem; - } - curElem->prev = newElem; - - HwiP_restore(key); -} - - -/* - * ======== List_put ======== - */ -void List_put(List_List *list, List_Elem *elem) -{ - uintptr_t key; - - key = HwiP_disable(); - - elem->next = NULL; - elem->prev = list->tail; - if (list->tail != NULL) { - list->tail->next = elem; - } - else { - list->head = elem; - } - - list->tail = elem; - - HwiP_restore(key); -} - -/* - * ======== List_putHead ======== - */ -void List_putHead(List_List *list, List_Elem *elem) -{ - uintptr_t key; - - key = HwiP_disable(); - - elem->next = list->head; - elem->prev = NULL; - if (list->head != NULL) { - list->head->prev = elem; - } - else { - list->tail = elem; - } - - list->head = elem; - - HwiP_restore(key); -} - -/* - * ======== List_remove ======== - */ -void List_remove(List_List *list, List_Elem *elem) -{ - uintptr_t key; - - key = HwiP_disable(); - - /* Handle the case where the elem to remove is the last one */ - if (elem->next == NULL) { - list->tail = elem->prev; - } - else { - elem->next->prev = elem->prev; - } - - /* Handle the case where the elem to remove is the first one */ - if (elem->prev == NULL) { - list->head = elem->next; - } - else { - elem->prev->next = elem->next; - } - - HwiP_restore(key); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/utils/List.h b/ext/hal/ti/simplelink/source/ti/drivers/utils/List.h deleted file mode 100644 index db99729a8c9..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/utils/List.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/** ============================================================================ - * @file List.h - * - * @brief Linked List interface for use in drivers - * - * This module provides simple doubly-link list implementation. There are two - * main structures: - * - ::List_List: The structure that holds the start of a linked list. There - * is no API to create one. It is up to the driver to provide the structure - * itself. - * - ::List_Elem: The structure that must be in the structure that is placed - * onto a linked list. Generally it is the first field in the structure. For - * example: - * @code - * typedef struct MyStruct { - * List_Elem elem; - * void *buffer; - * } MyStruct; - * @endcode - * - * The following shows how to create a linked list with three elements. - * - * @code - * + denotes null-terminated - * _______ _______ _______ _______ - * |_______|----->|_______|----->|_______|--->|_______|--//---, - * ,----|_______| ,-|_______|<-----|_______|<---|_______|<-//-, + - * | List + elem elem elem | - * |_____________________________________________________________| - * @endcode - * - * The APIs ::List_get, ::List_put, and ::List_putHead are - * atomic. The other APIs are not necessarily atomic. In other words, when - * traversing a linked list, it is up to the application to provide - * thread-safety (e.g. HwiP_disable/restore or MutexP_pend/post). - * - * Initializing and adding an element to the tail and removing it - * @code - * typedef struct MyStruct { - * List_Elem elem; - * void *buffer; - * } MyStruct; - * - * List_List list; - * MyStruct foo; - * MyStruct *bar; - * - * List_clearList(&list); - * List_put(&list, (List_Elem *)&foo); - * bar = (MyStruct *)List_get(&list); - * @endcode - * - * The ::List_put and ::List_get APIs are used to maintain a first-in first-out - * (FIFO) linked list. - * - * The ::List_putHead and ::List_get APIs are used to maintain a last-in first-out - * (LIFO) linked list. - * - * Traversing a list from head to tail. Note: thread-safety calls are - * not shown here. - * @code - * List_List list; - * List_Elem *temp; - * - * for (temp = List_head(&list); temp != NULL; temp = List_next(temp)) { - * printf("address = 0x%x\n", temp); - * } - * @endcode - * - * Traversing a list from tail to head. Note: thread-safety calls are - * not shown here. - * @code - * List_List list; - * List_Elem *temp; - * - * for (temp = List_tail(&list); temp != NULL; temp = List_prev(temp)) { - * printf("address = 0x%x\n", temp); - * } - * @endcode - * - * ============================================================================ - */ - -#ifndef ti_drivers_utils_List__include -#define ti_drivers_utils_List__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -typedef struct List_Elem { - struct List_Elem *next; - struct List_Elem *prev; -} List_Elem; - -typedef struct List_List { - List_Elem *head; - List_Elem *tail; -} List_List; - -/*! - * @brief Function to initialize the contents of a List_List - * - * @param list Pointer to a List_List structure that will be used to - * maintain a linked list - */ -extern void List_clearList(List_List *list); - -/*! - * @brief Function to test whether a linked list is empty - * - * @param list A pointer to a linked list - * - * @return true if empty, false if not empty - */ -static inline bool List_empty(List_List *list) -{ - return (list->head == NULL); -} - -/*! - * @brief Function to atomically get the first elem in a linked list - * - * @param list A pointer to a linked list - * - * @return Pointer the first elem in the linked list or NULL if empty - */ -extern List_Elem *List_get(List_List *list); - -/*! - * @brief Function to return the head of a linked list - * - * This function does not remove the head, it simply returns a pointer to - * it. This function is typically used when traversing a linked list. - * - * @param list A pointer to the linked list - * - * @return Pointer to the first elem in the linked list or NULL if empty - */ -static inline List_Elem *List_head(List_List *list) -{ - return (list->head); -} - -/*! - * @brief Function to insert an elem into a linked list - * - * @param list A pointer to the linked list - * - * @param newElem New elem to insert - * - * @param curElem Elem to insert the newElem in front of. - * This value cannot be NULL. - */ -extern void List_insert(List_List *list, List_Elem *newElem, - List_Elem *curElem); - -/*! - * @brief Function to return the next elem in a linked list - * - * This function does not remove the elem, it simply returns a pointer to - * next one. This function is typically used when traversing a linked list. - * - * @param elem Elem in the list - * - * @return Pointer to the next elem in linked list or NULL if at the end - */ -static inline List_Elem *List_next(List_Elem *elem) -{ - return (elem->next); -} - -/*! - * @brief Function to return the prev elem in a linked list - * - * This function does not remove the elem, it simply returns a pointer to - * prev one. This function is typically used when traversing a linked list. - * - * @param elem Elem in the list - * - * @return Pointer to the prev elem in linked list or NULL if at the beginning - */ -static inline List_Elem *List_prev(List_Elem *elem) -{ - return (elem->prev); -} - -/*! - * @brief Function to atomically put an elem onto the end of a linked list - * - * @param list A pointer to the linked list - * - * @param elem Element to place onto the end of the linked list - */ -extern void List_put(List_List *list, List_Elem *elem); - -/*! - * @brief Function to atomically put an elem onto the head of a linked list - * - * @param list A pointer to the linked list - * - * @param elem Element to place onto the beginning of the linked list - */ -extern void List_putHead(List_List *list, List_Elem *elem); - -/*! - * @brief Function to remove an elem from a linked list - * - * @param list A pointer to the linked list - * - * @param elem Element to be removed from a linked list - */ -extern void List_remove(List_List *list, List_Elem *elem); - -/*! - * @brief Function to return the tail of a linked list - * - * This function does not remove the tail, it simply returns a pointer to - * it. This function is typically used when traversing a linked list. - * - * @param list A pointer to the linked list - * - * @return Pointer to the last elem in the linked list or NULL if empty - */ -static inline List_Elem *List_tail(List_List *list) -{ - return (list->tail); -} - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_utils_List__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/utils/RingBuf.c b/ext/hal/ti/simplelink/source/ti/drivers/utils/RingBuf.c deleted file mode 100644 index ace4f012c59..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/utils/RingBuf.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2015-2016, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include - -/* - * ======== RingBuf_construct ======== - */ -void RingBuf_construct(RingBuf_Handle object, unsigned char *bufPtr, - size_t bufSize) -{ - object->buffer = bufPtr; - object->length = bufSize; - object->count = 0; - object->head = bufSize - 1; - object->tail = 0; - object->maxCount = 0; -} - -/* - * ======== RingBuf_get ======== - */ -int RingBuf_get(RingBuf_Handle object, unsigned char *data) -{ - unsigned int key; - - key = HwiP_disable(); - - if (!object->count) { - HwiP_restore(key); - return -1; - } - - *data = object->buffer[object->tail]; - object->tail = (object->tail + 1) % object->length; - object->count--; - - HwiP_restore(key); - - return (object->count); -} - -/* - * ======== RingBuf_getCount ======== - */ -int RingBuf_getCount(RingBuf_Handle object) -{ - return (object->count); -} - -/* - * ======== RingBuf_isFull ======== - */ -bool RingBuf_isFull(RingBuf_Handle object) -{ - return (object->count == object->length); -} - -/* - * ======== RingBuf_getMaxCount ======== - */ -int RingBuf_getMaxCount(RingBuf_Handle object) -{ - return (object->maxCount); -} - -/* - * ======== RingBuf_peek ======== - */ -int RingBuf_peek(RingBuf_Handle object, unsigned char *data) -{ - unsigned int key; - int retCount; - - key = HwiP_disable(); - - *data = object->buffer[object->tail]; - retCount = object->count; - - HwiP_restore(key); - - return (retCount); -} - -/* - * ======== RingBuf_put ======== - */ -int RingBuf_put(RingBuf_Handle object, unsigned char data) -{ - unsigned int key; - unsigned int next; - - key = HwiP_disable(); - - if (object->count != object->length) { - next = (object->head + 1) % object->length; - object->buffer[next] = data; - object->head = next; - object->count++; - object->maxCount = (object->count > object->maxCount) ? - object->count : - object->maxCount; - } - else { - - HwiP_restore(key); - return (-1); - } - - HwiP_restore(key); - - return (object->count); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/utils/RingBuf.h b/ext/hal/ti/simplelink/source/ti/drivers/utils/RingBuf.h deleted file mode 100644 index 29e8c82433e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/utils/RingBuf.h +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2015, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef ti_drivers_uart_RingBuf__include -#define ti_drivers_uart_RingBuf__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -typedef struct RingBuf_Object { - unsigned char *buffer; - size_t length; - size_t count; - size_t head; - size_t tail; - size_t maxCount; -} RingBuf_Object, *RingBuf_Handle; - -/*! - * @brief Initialize circular buffer - * - * @param object Pointer to a RingBuf Object that contains the member - * variables to operate a circular buffer. - * - * @param bufPtr Pointer to data buffer to be used for the circular buffer. - * The buffer is NOT stored in RingBuf_Object. - * - * @param bufSize The size of bufPtr in number of unsigned chars. - */ -void RingBuf_construct(RingBuf_Handle object, unsigned char *bufPtr, - size_t bufSize); - -/*! - * @brief Get an unsigned char from the end of the circular buffer and remove - * it. - * - * @param object Pointer to a RingBuf Object that contains the member - * variables to operate a circular buffer. - * - * @param data Pointer to an unsigned char to be filled with the data from - * the front of the circular buffer. - * - * @return Number of unsigned chars on the buffer after taking it out - * of the circular buffer. If it returns -1, the circular - * buffer was already empty and data is invalid. - */ -int RingBuf_get(RingBuf_Handle object, unsigned char *data); - -/*! - * @brief Get the number of unsigned chars currently stored on the circular - * buffer. - * - * @param object Pointer to a RingBuf Object that contains the member - * variables to operate a circular buffer. - * - * @return Number of unsigned chars on the circular buffer. - */ -int RingBuf_getCount(RingBuf_Handle object); - -/*! - * @brief Function to determine if the circular buffer is full or not. - * - * @param object Pointer to a RingBuf Object that contains the member - * variables to operate a circular buffer. - * - * @return true if circular buffer is full, else false. - */ -bool RingBuf_isFull(RingBuf_Handle object); - -/*! - * @brief A high-water mark indicating the largest number of unsigned chars - * stored on the circular buffer since it was constructed. - * - * @return Get the largest number of unsigned chars that were at one - * point in the circular buffer. - */ -int RingBuf_getMaxCount(RingBuf_Handle object); - -/*! - * @brief Get an unsigned char from the end of the circular buffer without - * removing it. - * - * @param object Pointer to a RingBuf Object that contains the member - * variables to operate a circular buffer. - * - * @param data Pointer to an unsigned char to be filled with the data from - * the front of the circular buffer. This function does not - * remove the data from the circular buffer. Do not evaluate - * data if the count returned is equal to 0. - * - * @return Number of unsigned chars on the circular buffer. If the - * number != 0, then data will contain the unsigned char at the - * end of the circular buffer. - */ -int RingBuf_peek(RingBuf_Handle object, unsigned char *data); - -/*! - * @brief Put an unsigned char into the end of the circular buffer. - * - * @param object Pointer to a RingBuf Object that contains the member - * variables to operate a circular buffer. - * - * @param data unsigned char to be placed at the end of the circular - * buffer. - * - * @return Number of unsigned chars on the buffer after it was added, - * or -1 if it's already full. - */ -int RingBuf_put(RingBuf_Handle object, unsigned char data); - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_uart_RingBuf__include */ diff --git a/ext/hal/ti/simplelink/source/ti/drivers/watchdog/WatchdogCC32XX.c b/ext/hal/ti/simplelink/source/ti/drivers/watchdog/WatchdogCC32XX.c deleted file mode 100644 index 59d887cf305..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/watchdog/WatchdogCC32XX.c +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include - -#include -#include - -#include -#include - -#include - -#include -#include -#include -#include - -/* Function prototypes */ -void WatchdogCC32XX_clear(Watchdog_Handle handle); -void WatchdogCC32XX_close(Watchdog_Handle handle); -int_fast16_t WatchdogCC32XX_control(Watchdog_Handle handle, - uint_fast16_t cmd, void *arg); -void WatchdogCC32XX_init(Watchdog_Handle handle); -Watchdog_Handle WatchdogCC32XX_open(Watchdog_Handle handle, Watchdog_Params *params); -int_fast16_t WatchdogCC32XX_setReload(Watchdog_Handle handle, - uint32_t value); -uint32_t WatchdogCC32XX_convertMsToTicks(Watchdog_Handle handle, - uint32_t milliseconds); - -/* Internal functions */ -static void WatchdogCC32XX_initHardware(Watchdog_Handle handle); -static int WatchdogCC32XX_postNotifyFxn(unsigned int eventType, - uintptr_t eventArg, uintptr_t clientArg); - -/* Watchdog function table for CC32XX implementation */ -const Watchdog_FxnTable WatchdogCC32XX_fxnTable = { - WatchdogCC32XX_clear, - WatchdogCC32XX_close, - WatchdogCC32XX_control, - WatchdogCC32XX_init, - WatchdogCC32XX_open, - WatchdogCC32XX_setReload, - WatchdogCC32XX_convertMsToTicks -}; - -/* Maximum allowable setReload value */ -#define MAX_RELOAD_VALUE 0xFFFFFFFF - -/* Millisecond to second ratio */ -#define MS_RATIO 1000 - -/* - * ======== WatchdogCC32XX_initHardware ======== - */ -static void WatchdogCC32XX_initHardware(Watchdog_Handle handle) -{ - WatchdogCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - WatchdogCC32XX_Object const *object = handle->object; - - MAP_WatchdogUnlock(hwAttrs->baseAddr); - MAP_WatchdogReloadSet(hwAttrs->baseAddr, object->reloadValue); - MAP_WatchdogIntClear(hwAttrs->baseAddr); - - /* Set debug stall mode */ - if (object->debugMode == Watchdog_DEBUG_STALL_ON) { - MAP_WatchdogStallEnable(hwAttrs->baseAddr); - } - else { - MAP_WatchdogStallDisable(hwAttrs->baseAddr); - } - - MAP_WatchdogEnable(hwAttrs->baseAddr); - - MAP_WatchdogLock(hwAttrs->baseAddr); -} - -/* - * ======== WatchdogCC32XX_postNotifyFxn ======== - * This functions is called when a transition from LPDS mode is made. - * clientArg is a handle of a previously opened Watchdog instance. - */ -static int WatchdogCC32XX_postNotifyFxn(unsigned int eventType, - uintptr_t eventArg, uintptr_t clientArg) -{ - WatchdogCC32XX_initHardware((Watchdog_Handle) clientArg); - - return (Power_NOTIFYDONE); -} - -/* - * ======== WatchdogCC32XX_clear ======== - */ -void WatchdogCC32XX_clear(Watchdog_Handle handle) -{ - WatchdogCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - - MAP_WatchdogIntClear(hwAttrs->baseAddr); -} - -/* - * ======== WatchdogCC32XX_close ======== - */ -void WatchdogCC32XX_close(Watchdog_Handle handle) -{ - /* - * Not supported for CC32XX - Once the INTEN bit of the WDTCTL - * register has been set, it can only be cleared by a hardware - * reset. - */ -} - -/* - * ======== WatchdogCC32XX_control ======== - * @pre Function assumes that the handle is not NULL - */ -int_fast16_t WatchdogCC32XX_control(Watchdog_Handle handle, uint_fast16_t cmd, - void *arg) -{ - WatchdogCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - - switch (cmd) { - /* Specific Watchdog CMDs */ - case (WatchdogCC32XX_CMD_IS_TIMER_ENABLE): - *(bool *)arg = MAP_WatchdogRunning(hwAttrs->baseAddr); - return (Watchdog_STATUS_SUCCESS); - - case (WatchdogCC32XX_CMD_GET_TIMER_VALUE): - *(uint32_t *)arg = MAP_WatchdogValueGet(hwAttrs->baseAddr); - return (Watchdog_STATUS_SUCCESS); - - case (WatchdogCC32XX_CMD_IS_TIMER_LOCKED): - *(bool *)arg = MAP_WatchdogLockState(hwAttrs->baseAddr); - return (Watchdog_STATUS_SUCCESS); - - case (WatchdogCC32XX_CMD_GET_TIMER_RELOAD_VALUE): - *(uint32_t *)arg = MAP_WatchdogReloadGet(hwAttrs->baseAddr); - return (Watchdog_STATUS_SUCCESS); - - default: - return (Watchdog_STATUS_UNDEFINEDCMD); - } -} - -/* - * ======== WatchdogCC32XX_init ======== - */ -void WatchdogCC32XX_init(Watchdog_Handle handle) -{ - WatchdogCC32XX_Object *object = handle->object; - - object->isOpen = false; -} - -/* - * ======== WatchdogCC32XX_open ======== - */ -Watchdog_Handle WatchdogCC32XX_open(Watchdog_Handle handle, Watchdog_Params *params) -{ - uintptr_t key; - HwiP_Handle hwiHandle; - HwiP_Params hwiParams; - WatchdogCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - WatchdogCC32XX_Object *object = handle->object; - - key = HwiP_disable(); - - if (object->isOpen == true) { - HwiP_restore(key); - return (NULL); - } - - object->isOpen = true; - HwiP_restore(key); - - /* Register the hardware interrupt for this watchdog */ - if (params->callbackFxn) { - HwiP_Params_init(&hwiParams); - hwiParams.arg = (uintptr_t) handle; - hwiParams.priority = hwAttrs->intPriority; - hwiHandle = HwiP_create(hwAttrs->intNum, params->callbackFxn, - &hwiParams); - if (hwiHandle == NULL) { - object->isOpen = false; - return (NULL); - } - } - - Power_setDependency(PowerCC32XX_PERIPH_WDT); - Power_registerNotify(&(object->notifyObj), PowerCC32XX_AWAKE_LPDS, - WatchdogCC32XX_postNotifyFxn, (uintptr_t) handle); - - object->debugMode = params->debugStallMode; - object->reloadValue = hwAttrs->reloadValue; - - WatchdogCC32XX_initHardware(handle); - - return (handle); -} - -/* - * ======== WatchdogCC32XX_setReload ======== - */ -int_fast16_t WatchdogCC32XX_setReload(Watchdog_Handle handle, uint32_t value) -{ - WatchdogCC32XX_HWAttrs const *hwAttrs = handle->hwAttrs; - WatchdogCC32XX_Object *object = handle->object; - - /* Set value */ - MAP_WatchdogUnlock(hwAttrs->baseAddr); - MAP_WatchdogReloadSet(hwAttrs->baseAddr, value); - MAP_WatchdogLock(hwAttrs->baseAddr); - object->reloadValue = value; - - return (Watchdog_STATUS_SUCCESS); -} - -/* - * ======== WatchdogCC32XX_convertMsToTicks ======== - * This function converts the input value from milliseconds to - * Watchdog clock ticks. - */ -uint32_t WatchdogCC32XX_convertMsToTicks(Watchdog_Handle handle, - uint32_t milliseconds) -{ - uint32_t tickValue; - uint32_t convertRatio; - uint32_t maxConvertMs; - ClockP_FreqHz freq; - - /* Determine milliseconds to clock ticks conversion ratio */ - ClockP_getCpuFreq(&freq); - - /* Watchdog clock ticks/ms = CPU clock / MS_RATIO */ - convertRatio = freq.lo / MS_RATIO; - maxConvertMs = MAX_RELOAD_VALUE / convertRatio; - - /* Convert milliseconds to watchdog timer ticks */ - /* Check if value exceeds maximum */ - if (milliseconds > maxConvertMs) { - tickValue = 0; /* Return zero to indicate overflow */ - } - else { - tickValue = (uint32_t)(milliseconds * convertRatio); - } - - return(tickValue); -} diff --git a/ext/hal/ti/simplelink/source/ti/drivers/watchdog/WatchdogCC32XX.h b/ext/hal/ti/simplelink/source/ti/drivers/watchdog/WatchdogCC32XX.h deleted file mode 100644 index 7f4c0e1d124..00000000000 --- a/ext/hal/ti/simplelink/source/ti/drivers/watchdog/WatchdogCC32XX.h +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2015-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -/*!**************************************************************************** - * @file WatchdogCC32XX.h - * @brief Watchdog timer driver implementation for CC32XX - * - * The Watchdog header file for CC32XX should be included in an application - * as follows: - * @code - * #include - * #include - * @endcode - * - * Refer to @ref Watchdog.h for a complete description of APIs. - * - * This Watchdog driver implementation is designed to operate on a CC32XX - * device. Once opened, CC32XX Watchdog will count down from the reload - * value specified in the WatchdogCC32XX_HWAttrs. If it times out, the - * Watchdog interrupt flag will be set, and a user-provided callback function - * will be called. If the Watchdog Timer is allowed to time out again while - * the interrupt flag is still pending, a reset signal will be generated. - * To prevent a reset, Watchdog_clear() must be called to clear the interrupt - * flag. - * - * The reload value from which the Watchdog Timer counts down may be changed - * during runtime using Watchdog_setReload(). - * - * Watchdog_close() is not supported by this driver implementation. - * - * By default the Watchdog driver has resets turned on. This feature cannot - * be disabled. - * - * To have a user-defined function run at the warning interrupt, first define - * a void-type function that takes a Watchdog_Handle cast to a UArg as an - * argument. The callback and code to start the Watchdog timer are shown below. - * - * @code - * void watchdogCallback(UArg handle); - * - * ... - * - * Watchdog_Handle handle; - * Watchdog_Params params; - * uint32_t tickValue; - * - * Watchdog_Params_init(¶ms); - * params.callbackFxn = watchdogCallback; - * handle = Watchdog_open(Watchdog_configIndex, ¶ms); - * // Set timeout period to 100 ms - * tickValue = Watchdog_convertMsToTicks(handle, 100); - * Watchdog_setReload(handle, tickValue); - * - * ... - * - * void watchdogCallback(UArg handle) - * { - * // User-defined code here - * ... - * - * } - * @endcode - * - * # Power Driver Usage # - * - * The watchdog timer driver does not set any power constraints. If the power - * driver is enabled, the application will continue to aggressively attempt - * to place the device into the lowest power state possible. - * - * When the device enters Low Power Deep Sleep, the peripheral registers are - * reset. After a transition from Low Power Deep Sleep, the watchdog timer will - * be re-initialized automatically with the most recently set reload value. If - * Watchdog_setReload() was never called, the - * #WatchdogCC32XX_HWAttrs.reloadValue is used. With each transition to and - * from Low Power Deep Sleep, the watchdog timer is implicitly cleared. - * - ****************************************************************************** - */ - -#ifndef ti_drivers_watchdog_WatchdogCC32XX__include -#define ti_drivers_watchdog_WatchdogCC32XX__include - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include -#include - -/** - * @addtogroup Watchdog_STATUS - * WatchdogCC32XX_STATUS_* macros are command codes only defined in the - * WatchdogCC32XX.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/* Add WatchdogCC32XX_STATUS_* macros here */ - -/** @}*/ - -/** - * @addtogroup Watchdog_CMD - * WatchdogCC32XX_CMD_* macros are command codes only defined in the - * WatchdogCC32XX.h driver implementation and need to: - * @code - * #include - * @endcode - * @{ - */ - -/*! - * @brief Command used by Watchdog_control to determines - * whether the watchdog timer is enabled - * - * With this command code, @b arg is a pointer to a @c bool. - * @b *arg contains @c true if the watchdog timer is enabled, - * else @c false if it is not. - */ -#define WatchdogCC32XX_CMD_IS_TIMER_ENABLE (Watchdog_CMD_RESERVED + 0) - - -/*! - * @brief Command used by Watchdog_control - * to gets the current watchdog timer value - * - * With this command code, @b arg is a pointer to an @a integer. - * @b *arg contains the current value of the watchdog timer. - */ -#define WatchdogCC32XX_CMD_GET_TIMER_VALUE (Watchdog_CMD_RESERVED + 1) - - -/*! - * @brief Command used by Watchdog_control to determines - * whether the watchdog timer is locked - * - * With this command code, @b arg is a pointer to a @c bool. - * @b *arg contains @c true if the watchdog timer is locked, - * else @c false if it is not. - */ -#define WatchdogCC32XX_CMD_IS_TIMER_LOCKED (Watchdog_CMD_RESERVED + 2) - - -/*! - * @brief Command used by Watchdog_control - * to gets the current watchdog timer reload value - * - * With this command code, @b arg is a pointer to an @a integer. - * @b *arg contains the current value loaded into the watchdog timer when - * the count reaches zero for the first time. - */ -#define WatchdogCC32XX_CMD_GET_TIMER_RELOAD_VALUE (Watchdog_CMD_RESERVED + 3) - - -/** @}*/ - -/*! @brief Watchdog function table for CC32XX */ -extern const Watchdog_FxnTable WatchdogCC32XX_fxnTable; - -/*! - * @brief Watchdog hardware attributes for CC32XX - * - * intPriority is the Watchdog timer's interrupt priority, as defined by the - * underlying OS. It is passed unmodified to the underlying OS's interrupt - * handler creation code, so you need to refer to the OS documentation - * for usage. For example, for SYS/BIOS applications, refer to the - * ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of - * interrupt priorities. If the driver uses the ti.dpl interface - * instead of making OS calls directly, then the HwiP port handles the - * interrupt priority in an OS specific way. In the case of the SYS/BIOS - * port, intPriority is passed unmodified to Hwi_create(). - */ -typedef struct WatchdogCC32XX_HWAttrs { - unsigned int baseAddr; /*!< Base address for Watchdog */ - unsigned int intNum; /*!< WDT interrupt number */ - unsigned int intPriority; /*!< WDT interrupt priority */ - uint32_t reloadValue; /*!< Reload value for Watchdog */ -} WatchdogCC32XX_HWAttrs; - -/*! - * @brief Watchdog Object for CC32XX - * - * Not to be accessed by the user. - */ -typedef struct WatchdogCC32XX_Object { - Power_NotifyObj notifyObj; - /* - * The reload value can be set at runtime; therefore we can't rely - * on the reload value supplied in the HWAttrs after a LPDS transition. - */ - uint32_t reloadValue; - Watchdog_DebugMode debugMode; - bool isOpen; -} WatchdogCC32XX_Object; - -#ifdef __cplusplus -} -#endif - -#endif /* ti_drivers_watchdog_WatchdogCC32XX__include */ diff --git a/ext/hal/ti/simplelink/source/ti/net/slneterr.h b/ext/hal/ti/simplelink/source/ti/net/slneterr.h deleted file mode 100644 index c0ed17c3ec4..00000000000 --- a/ext/hal/ti/simplelink/source/ti/net/slneterr.h +++ /dev/null @@ -1,698 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -#ifndef __SL_NET_ERR_H__ -#define __SL_NET_ERR_H__ - - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup SlNetErr SlNetErr group - - \short Provide BSD and proprietary errors - -*/ -/*! - - \addtogroup SlNetErr - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#define SLNETERR_RET_CODE_OK (0L) /**< Success */ - -#define SLNETERR_GENERAL_DEVICE (-6L) /**< General device error */ - -/* BSD SOCKET ERRORS CODES */ - -#define SLNETERR_BSD_SOC_ERROR (-1L) /**< Failure */ -#define SLNETERR_BSD_ENXIO (-6L) /**< No such device or address */ -#define SLNETERR_BSD_INEXE (-8L) /**< socket command in execution */ -#define SLNETERR_BSD_EBADF (-9L) /**< Bad file number */ -#define SLNETERR_BSD_ENSOCK (-10L) /**< The system limit on the total number of open sockets, has been reached */ -#define SLNETERR_BSD_EAGAIN (-11L) /**< Try again */ -#define SLNETERR_BSD_EWOULDBLOCK SLNETERR_BSD_EAGAIN -#define SLNETERR_BSD_ENOMEM (-12L) /**< Out of memory */ -#define SLNETERR_BSD_EACCES (-13L) /**< Permission denied */ -#define SLNETERR_BSD_EFAULT (-14L) /**< Bad address */ -#define SLNETERR_BSD_ECLOSE (-15L) /**< close socket operation failed to transmit all queued packets */ -#define SLNETERR_BSD_EALREADY_ENABLED (-21L) /**< Transceiver - Transceiver already ON. there could be only one */ -#define SLNETERR_BSD_EINVAL (-22L) /**< Invalid argument */ -#define SLNETERR_BSD_EAUTO_CONNECT_OR_CONNECTING (-69L) /**< Transceiver - During connection, connected or auto mode started */ -#define SLNETERR_BSD_CONNECTION_PENDING (-72L) /**< Transceiver - Device is connected, disconnect first to open transceiver */ -#define SLNETERR_BSD_EUNSUPPORTED_ROLE (-86L) /**< Transceiver - Trying to start when WLAN role is AP or P2P GO */ -#define SLNETERR_BSD_ENOTSOCK (-88L) /**< Socket operation on non-socket */ -#define SLNETERR_BSD_EDESTADDRREQ (-89L) /**< Destination address required */ -#define SLNETERR_BSD_EMSGSIZE (-90L) /**< Message too long */ -#define SLNETERR_BSD_EPROTOTYPE (-91L) /**< Protocol wrong type for socket */ -#define SLNETERR_BSD_ENOPROTOOPT (-92L) /**< Protocol not available */ -#define SLNETERR_BSD_EPROTONOSUPPORT (-93L) /**< Protocol not supported */ -#define SLNETERR_BSD_ESOCKTNOSUPPORT (-94L) /**< Socket type not supported */ -#define SLNETERR_BSD_EOPNOTSUPP (-95L) /**< Operation not supported on transport endpoint */ -#define SLNETERR_BSD_EAFNOSUPPORT (-97L) /**< Address family not supported by protocol */ -#define SLNETERR_BSD_EADDRINUSE (-98L) /**< Address already in use */ -#define SLNETERR_BSD_EADDRNOTAVAIL (-99L) /**< Cannot assign requested address */ -#define SLNETERR_BSD_ENETDOWN (-100L) /**< Network is down */ -#define SLNETERR_BSD_ENETUNREACH (-101L) /**< Network is unreachable */ -#define SLNETERR_BSD_ECONNABORTED (-103L) /**< Software caused connection abort */ -#define SLNETERR_BSD_ECONNRESET (-104L) /**< Connection reset by peer */ -#define SLNETERR_BSD_ENOBUFS (-105L) /**< No buffer space available */ -#define SLNETERR_BSD_EOBUFF SLNETERR_BSD_ENOBUFS -#define SLNETERR_BSD_EISCONN (-106L) /**< Transport endpoint is already connected */ -#define SLNETERR_BSD_ENOTCONN (-107L) /**< Transport endpoint is not connected */ -#define SLNETERR_BSD_ESHUTDOWN (-108L) /**< Cannot send after transport endpoint shutdown */ -#define SLNETERR_BSD_ETIMEDOUT (-110L) /**< Connection timed out */ -#define SLNETERR_BSD_ECONNREFUSED (-111L) /**< Connection refused */ -#define SLNETERR_BSD_EHOSTDOWN (-112L) /**< Host is down */ -#define SLNETERR_BSD_EHOSTUNREACH (-113L) /**< No route to host */ -#define SLNETERR_BSD_EALREADY (-114L) /**< Non blocking connect in progress, try again */ - -/* ssl tls security start with -300 offset */ -#define SLNETERR_ESEC_CLOSE_NOTIFY (-300L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_UNEXPECTED_MESSAGE (-310L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_BAD_RECORD_MAC (-320L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_DECRYPTION_FAILED (-321L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_RECORD_OVERFLOW (-322L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_DECOMPRESSION_FAILURE (-330L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_HANDSHAKE_FAILURE (-340L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_NO_CERTIFICATE (-341L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_BAD_CERTIFICATE (-342L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_UNSUPPORTED_CERTIFICATE (-343L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_ILLEGAL_PARAMETER (-347L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_ACCESS_DENIED (-349L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_DECODE_ERROR (-350L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_DECRYPT_ERROR1 (-351L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_EXPORT_RESTRICTION (-360L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_PROTOCOL_VERSION (-370L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_INSUFFICIENT_SECURITY (-371L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_INTERNAL_ERROR (-380L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_USER_CANCELLED (-390L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_NO_RENEGOTIATION (-400L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_UNSUPPORTED_EXTENSION (-410L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_CERTIFICATE_UNOBTAINABLE (-411L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_UNRECOGNIZED_NAME (-412L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_BAD_CERTIFICATE_STATUS_RESPONSE (-413L) /**< ssl/tls alerts */ -#define SLNETERR_ESEC_BAD_CERTIFICATE_HASH_VALUE (-414L) /**< ssl/tls alerts */ - - -/* proprietary secure */ -#define SLNETERR_ESEC_GENERAL (-450L) /**< error secure level general error */ -#define SLNETERR_ESEC_DECRYPT (-451L) /**< error secure level, decrypt recv packet fail */ -#define SLNETERR_ESEC_CLOSED (-452L) /**< secure layer is closed by other size, tcp is still connected */ -#define SLNETERR_ESEC_SNO_VERIFY (-453L) /**< Connected without server verification */ -#define SLNETERR_ESEC_NO_CA_FILE (-454L) /**< error secure level CA file not found */ -#define SLNETERR_ESEC_MEMORY (-455L) /**< error secure level No memory space available */ -#define SLNETERR_ESEC_BAD_CA_FILE (-456L) /**< error secure level bad CA file */ -#define SLNETERR_ESEC_BAD_CERT_FILE (-457L) /**< error secure level bad Certificate file */ -#define SLNETERR_ESEC_BAD_PRIVATE_FILE (-458L) /**< error secure level bad private file */ -#define SLNETERR_ESEC_BAD_DH_FILE (-459L) /**< error secure level bad DH file */ -#define SLNETERR_ESEC_T00_MANY_SSL_OPENED (-460L) /**< MAX SSL Sockets are opened */ -#define SLNETERR_ESEC_DATE_ERROR (-461L) /**< connected with certificate date verification error */ -#define SLNETERR_ESEC_HAND_SHAKE_TIMED_OUT (-462L) /**< connection timed out due to handshake time */ -#define SLNETERR_ESEC_TX_BUFFER_NOT_EMPTY (-463L) /**< cannot start ssl connection while send buffer is full */ -#define SLNETERR_ESEC_RX_BUFFER_NOT_EMPTY (-464L) /**< cannot start ssl connection while recv buffer is full */ -#define SLNETERR_ESEC_SSL_DURING_HAND_SHAKE (-465L) /**< cannot use while in handshaking */ -#define SLNETERR_ESEC_NOT_ALLOWED_WHEN_LISTENING (-466L) /**< the operation is not allowed when listening, do before listen */ -#define SLNETERR_ESEC_CERTIFICATE_REVOKED (-467L) /**< connected but on of the certificates in the chain is revoked */ -#define SLNETERR_ESEC_UNKNOWN_ROOT_CA (-468L) /**< connected but the root CA used to validate the peer is unknown */ -#define SLNETERR_ESEC_WRONG_PEER_CERT (-469L) /**< wrong peer cert (server cert) was received while trying to connect to server */ -#define SLNETERR_ESEC_TCP_DISCONNECTED_UNCOMPLETE_RECORD (-470L) /**< the other side disconnected the TCP layer and didn't send the whole ssl record */ -#define SLNETERR_ESEC_HELLO_VERIFY_ERROR (-471L) /**< Hello verification failed in DTLS */ - -#define SLNETERR_ESEC_BUFFER_E (-632L) /**< output buffer too small or input too large */ -#define SLNETERR_ESEC_ALGO_ID_E (-633L) /**< setting algo id error */ -#define SLNETERR_ESEC_PUBLIC_KEY_E (-634L) /**< setting public key error */ -#define SLNETERR_ESEC_DATE_E (-635L) /**< setting date validity error */ -#define SLNETERR_ESEC_SUBJECT_E (-636L) /**< setting subject name error */ -#define SLNETERR_ESEC_ISSUER_E (-637L) /**< setting issuer name error */ -#define SLNETERR_ESEC_CA_TRUE_E (-638L) /**< setting CA basic constraint true error */ -#define SLNETERR_ESEC_EXTENSIONS_E (-639L) /**< setting extensions error */ -#define SLNETERR_ESEC_ASN_PARSE_E (-640L) /**< ASN parsing error, invalid input */ -#define SLNETERR_ESEC_ASN_VERSION_E (-641L) /**< ASN version error, invalid number */ -#define SLNETERR_ESEC_ASN_GETINT_E (-642L) /**< ASN get big int error, invalid data */ -#define SLNETERR_ESEC_ASN_RSA_KEY_E (-643L) /**< ASN key init error, invalid input */ -#define SLNETERR_ESEC_ASN_OBJECT_ID_E (-644L) /**< ASN object id error, invalid id */ -#define SLNETERR_ESEC_ASN_TAG_NULL_E (-645L) /**< ASN tag error, not null */ -#define SLNETERR_ESEC_ASN_EXPECT_0_E (-646L) /**< ASN expect error, not zero */ -#define SLNETERR_ESEC_ASN_BITSTR_E (-647L) /**< ASN bit string error, wrong id */ -#define SLNETERR_ESEC_ASN_UNKNOWN_OID_E (-648L) /**< ASN oid error, unknown sum id */ -#define SLNETERR_ESEC_ASN_DATE_SZ_E (-649L) /**< ASN date error, bad size */ -#define SLNETERR_ESEC_ASN_BEFORE_DATE_E (-650L) /**< ASN date error, current date before */ -#define SLNETERR_ESEC_ASN_AFTER_DATE_E (-651L) /**< ASN date error, current date after */ -#define SLNETERR_ESEC_ASN_SIG_OID_E (-652L) /**< ASN signature error, mismatched oid */ -#define SLNETERR_ESEC_ASN_TIME_E (-653L) /**< ASN time error, unknown time type */ -#define SLNETERR_ESEC_ASN_INPUT_E (-654L) /**< ASN input error, not enough data */ -#define SLNETERR_ESEC_ASN_SIG_CONFIRM_E (-655L) /**< ASN sig error, confirm failure */ -#define SLNETERR_ESEC_ASN_SIG_HASH_E (-656L) /**< ASN sig error, unsupported hash type */ -#define SLNETERR_ESEC_ASN_SIG_KEY_E (-657L) /**< ASN sig error, unsupported key type */ -#define SLNETERR_ESEC_ASN_DH_KEY_E (-658L) /**< ASN key init error, invalid input */ -#define SLNETERR_ESEC_ASN_NTRU_KEY_E (-659L) /**< ASN ntru key decode error, invalid input */ -#define SLNETERR_ESEC_ASN_CRIT_EXT_E (-660L) /**< ASN unsupported critical extension */ -#define SLNETERR_ESEC_ECC_BAD_ARG_E (-670L) /**< ECC input argument of wrong type */ -#define SLNETERR_ESEC_ASN_ECC_KEY_E (-671L) /**< ASN ECC bad input */ -#define SLNETERR_ESEC_ECC_CURVE_OID_E (-672L) /**< Unsupported ECC OID curve type */ -#define SLNETERR_ESEC_BAD_FUNC_ARG (-673L) /**< Bad function argument provided */ -#define SLNETERR_ESEC_NOT_COMPILED_IN (-674L) /**< Feature not compiled in */ -#define SLNETERR_ESEC_UNICODE_SIZE_E (-675L) /**< Unicode password too big */ -#define SLNETERR_ESEC_NO_PASSWORD (-676L) /**< no password provided by user */ -#define SLNETERR_ESEC_ALT_NAME_E (-677L) /**< alt name size problem, too big */ -#define SLNETERR_ESEC_ASN_NO_SIGNER_E (-688L) /**< ASN no signer to confirm failure */ -#define SLNETERR_ESEC_ASN_CRL_CONFIRM_E (-689L) /**< ASN CRL signature confirm failure */ -#define SLNETERR_ESEC_ASN_CRL_NO_SIGNER_E (-690L) /**< ASN CRL no signer to confirm failure */ -#define SLNETERR_ESEC_ASN_OCSP_CONFIRM_E (-691L) /**< ASN OCSP signature confirm failure */ -#define SLNETERR_ESEC_VERIFY_FINISHED_ERROR (-704L) /**< verify problem on finished */ -#define SLNETERR_ESEC_VERIFY_MAC_ERROR (-705L) /**< verify mac problem */ -#define SLNETERR_ESEC_PARSE_ERROR (-706L) /**< parse error on header */ -#define SLNETERR_ESEC_UNKNOWN_HANDSHAKE_TYPE (-707L) /**< weird handshake type */ -#define SLNETERR_ESEC_SOCKET_ERROR_E (-708L) /**< error state on socket */ -#define SLNETERR_ESEC_SOCKET_NODATA (-709L) /**< expected data, not there */ -#define SLNETERR_ESEC_INCOMPLETE_DATA (-710L) /**< don't have enough data to complete task */ -#define SLNETERR_ESEC_UNKNOWN_RECORD_TYPE (-711L) /**< unknown type in record hdr */ -#define SLNETERR_ESEC_INNER_DECRYPT_ERROR (-712L) /**< error during decryption */ -#define SLNETERR_ESEC_FATAL_ERROR (-713L) /**< recvd alert fatal error */ -#define SLNETERR_ESEC_ENCRYPT_ERROR (-714L) /**< error during encryption */ -#define SLNETERR_ESEC_FREAD_ERROR (-715L) /**< fread problem */ -#define SLNETERR_ESEC_NO_PEER_KEY (-716L) /**< need peer's key */ -#define SLNETERR_ESEC_NO_PRIVATE_KEY (-717L) /**< need the private key */ -#define SLNETERR_ESEC_RSA_PRIVATE_ERROR (-718L) /**< error during rsa priv op */ -#define SLNETERR_ESEC_NO_DH_PARAMS (-719L) /**< server missing DH params */ -#define SLNETERR_ESEC_BUILD_MSG_ERROR (-720L) /**< build message failure */ -#define SLNETERR_ESEC_BAD_HELLO (-721L) /**< client hello malformed */ -#define SLNETERR_ESEC_DOMAIN_NAME_MISMATCH (-722L) /**< peer subject name mismatch */ -#define SLNETERR_ESEC_WANT_READ (-723L) /**< want read, call again */ -#define SLNETERR_ESEC_NOT_READY_ERROR (-724L) /**< handshake layer not ready */ -#define SLNETERR_ESEC_PMS_VERSION_ERROR (-725L) /**< pre m secret version error */ -#define SLNETERR_ESEC_WANT_WRITE (-727L) /**< want write, call again */ -#define SLNETERR_ESEC_BUFFER_ERROR (-728L) /**< malformed buffer input */ -#define SLNETERR_ESEC_VERIFY_CERT_ERROR (-729L) /**< verify cert error */ -#define SLNETERR_ESEC_VERIFY_SIGN_ERROR (-730L) /**< verify sign error */ -#define SLNETERR_ESEC_LENGTH_ERROR (-741L) /**< record layer length error */ -#define SLNETERR_ESEC_PEER_KEY_ERROR (-742L) /**< can't decode peer key */ -#define SLNETERR_ESEC_ZERO_RETURN (-743L) /**< peer sent close notify */ -#define SLNETERR_ESEC_SIDE_ERROR (-744L) /**< wrong client/server type */ -#define SLNETERR_ESEC_NO_PEER_CERT (-745L) /**< peer didn't send key */ -#define SLNETERR_ESEC_ECC_CURVETYPE_ERROR (-750L) /**< Bad ECC Curve Type */ -#define SLNETERR_ESEC_ECC_CURVE_ERROR (-751L) /**< Bad ECC Curve */ -#define SLNETERR_ESEC_ECC_PEERKEY_ERROR (-752L) /**< Bad Peer ECC Key */ -#define SLNETERR_ESEC_ECC_MAKEKEY_ERROR (-753L) /**< Bad Make ECC Key */ -#define SLNETERR_ESEC_ECC_EXPORT_ERROR (-754L) /**< Bad ECC Export Key */ -#define SLNETERR_ESEC_ECC_SHARED_ERROR (-755L) /**< Bad ECC Shared Secret */ -#define SLNETERR_ESEC_NOT_CA_ERROR (-757L) /**< Not a CA cert error */ -#define SLNETERR_ESEC_BAD_PATH_ERROR (-758L) /**< Bad path for opendir */ -#define SLNETERR_ESEC_BAD_CERT_MANAGER_ERROR (-759L) /**< Bad Cert Manager */ -#define SLNETERR_ESEC_OCSP_CERT_REVOKED (-760L) /**< OCSP Certificate revoked */ -#define SLNETERR_ESEC_CRL_CERT_REVOKED (-761L) /**< CRL Certificate revoked */ -#define SLNETERR_ESEC_CRL_MISSING (-762L) /**< CRL Not loaded */ -#define SLNETERR_ESEC_MONITOR_RUNNING_E (-763L) /**< CRL Monitor already running */ -#define SLNETERR_ESEC_THREAD_CREATE_E (-764L) /**< Thread Create Error */ -#define SLNETERR_ESEC_OCSP_NEED_URL (-765L) /**< OCSP need an URL for lookup */ -#define SLNETERR_ESEC_OCSP_CERT_UNKNOWN (-766L) /**< OCSP responder doesn't know */ -#define SLNETERR_ESEC_OCSP_LOOKUP_FAIL (-767L) /**< OCSP lookup not successful */ -#define SLNETERR_ESEC_MAX_CHAIN_ERROR (-768L) /**< max chain depth exceeded */ -#define SLNETERR_ESEC_NO_PEER_VERIFY (-778L) /**< Need peer cert verify Error */ -#define SLNETERR_ESEC_UNSUPPORTED_SUITE (-790L) /**< unsupported cipher suite */ -#define SLNETERR_ESEC_MATCH_SUITE_ERROR (-791L) /**< can't match cipher suite */ - - - -/* WLAN ERRORS CODES*/ - -#define SLNETERR_WLAN_KEY_ERROR (-2049L) -#define SLNETERR_WLAN_INVALID_ROLE (-2050L) -#define SLNETERR_WLAN_PREFERRED_NETWORKS_FILE_LOAD_FAILED (-2051L) -#define SLNETERR_WLAN_CANNOT_CONFIG_SCAN_DURING_PROVISIONING (-2052L) -#define SLNETERR_WLAN_INVALID_SECURITY_TYPE (-2054L) -#define SLNETERR_WLAN_PASSPHRASE_TOO_LONG (-2055L) -#define SLNETERR_WLAN_EAP_WRONG_METHOD (-2057L) -#define SLNETERR_WLAN_PASSWORD_ERROR (-2058L) -#define SLNETERR_WLAN_EAP_ANONYMOUS_LEN_ERROR (-2059L) -#define SLNETERR_WLAN_SSID_LEN_ERROR (-2060L) -#define SLNETERR_WLAN_USER_ID_LEN_ERROR (-2061L) -#define SLNETERR_WLAN_PREFERRED_NETWORK_LIST_FULL (-2062L) -#define SLNETERR_WLAN_PREFERRED_NETWORKS_FILE_WRITE_FAILED (-2063L) -#define SLNETERR_WLAN_ILLEGAL_WEP_KEY_INDEX (-2064L) -#define SLNETERR_WLAN_INVALID_DWELL_TIME_VALUES (-2065L) -#define SLNETERR_WLAN_INVALID_POLICY_TYPE (-2066L) -#define SLNETERR_WLAN_PM_POLICY_INVALID_OPTION (-2067L) -#define SLNETERR_WLAN_PM_POLICY_INVALID_PARAMS (-2068L) -#define SLNETERR_WLAN_WIFI_NOT_CONNECTED (-2069L) -#define SLNETERR_WLAN_ILLEGAL_CHANNEL (-2070L) -#define SLNETERR_WLAN_WIFI_ALREADY_DISCONNECTED (-2071L) -#define SLNETERR_WLAN_TRANSCEIVER_ENABLED (-2072L) -#define SLNETERR_WLAN_GET_NETWORK_LIST_EAGAIN (-2073L) -#define SLNETERR_WLAN_GET_PROFILE_INVALID_INDEX (-2074L) -#define SLNETERR_WLAN_FAST_CONN_DATA_INVALID (-2075L) -#define SLNETERR_WLAN_NO_FREE_PROFILE (-2076L) -#define SLNETERR_WLAN_AP_SCAN_INTERVAL_TOO_LOW (-2077L) -#define SLNETERR_WLAN_SCAN_POLICY_INVALID_PARAMS (-2078L) - -#define SLNETERR_RXFL_OK (0L) /**< O.K */ -#define SLNETERR_RXFL_RANGE_COMPARE_PARAMS_ARE_INVALID (-2079L) -#define SLNETERR_RXFL_RXFL_INVALID_PATTERN_LENGTH (-2080L) /**< requested length for L1/L4 payload matching must not exceed 16 bytes */ -#define SLNETERR_RXFL_ACTION_USER_EVENT_ID_TOO_BIG (-2081L) /**< user action id for host event must not exceed SLNETERR_WLAN_RX_FILTER_MAX_USER_EVENT_ID */ -#define SLNETERR_RXFL_OFFSET_TOO_BIG (-2082L) /**< requested offset for L1/L4 payload matching must not exceed 1535 bytes */ -#define SLNETERR_RXFL_STAT_UNSUPPORTED (-2083L) /**< get rx filters statistics not supported */ -#define SLNETERR_RXFL_INVALID_FILTER_ARG_UPDATE (-2084L) /**< invalid filter args request */ -#define SLNETERR_RXFL_INVALID_SYSTEM_STATE_TRIGGER_FOR_FILTER_TYPE (-2085L) /**< system state not supported for this filter type */ -#define SLNETERR_RXFL_INVALID_FUNC_ID_FOR_FILTER_TYPE (-2086L) /**< function id not supported for this filter type */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_3 (-2087L) /**< filter parent doesn't exist */ -#define SLNETERR_RXFL_OUTPUT_OR_INPUT_BUFFER_LENGTH_TOO_SMALL (-2088L) /**< ! The output buffer length is smaller than required for that operation */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_SOFTWARE_FILTER_NOT_FIT (-2089L) /**< Node filter can't be child of software filter and vice_versa */ -#define SLNETERR_RXFL_DEPENDENCY_IS_NOT_PERSISTENT (-2090L) /**< Dependency filter is not persistent */ -#define SLNETERR_RXFL_RXFL_ALLOCATION_PROBLEM (-2091L) -#define SLNETERR_RXFL_SYSTEM_STATE_NOT_SUPPORTED_FOR_THIS_FILTER (-2092L) /**< System state is not supported */ -#define SLNETERR_RXFL_TRIGGER_USE_REG5_TO_REG8 (-2093L) /**< Only counters 5 - 8 are allowed, for trigger */ -#define SLNETERR_RXFL_TRIGGER_USE_REG1_TO_REG4 (-2094L) /**< Only counters 1 - 4 are allowed, for trigger */ -#define SLNETERR_RXFL_ACTION_USE_REG5_TO_REG8 (-2095L) /**< Only counters 5 - 8 are allowed, for action */ -#define SLNETERR_RXFL_ACTION_USE_REG1_TO_REG4 (-2096L) /**< Only counters 1 - 4 are allowed, for action */ -#define SLNETERR_RXFL_FIELD_SUPPORT_ONLY_EQUAL_AND_NOTEQUAL (-2097L) /**< Rule compare function Id is out of range */ -#define SLNETERR_RXFL_WRONG_MULTICAST_BROADCAST_ADDRESS (-2098L) /**< The address should be of type multicast or broadcast */ -#define SLNETERR_RXFL_THE_FILTER_IS_NOT_OF_HEADER_TYPE (-2099L) /**< The filter should be of header type */ -#define SLNETERR_RXFL_WRONG_COMPARE_FUNC_FOR_BROADCAST_ADDRESS (-2100L) /**< The compare function is not suitable for broadcast address */ -#define SLNETERR_RXFL_WRONG_MULTICAST_ADDRESS (-2101L) /**< The address should be of multicast type */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_IS_NOT_PERSISTENT (-2102L) /**< The dependency filter is not persistent */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_IS_NOT_ENABLED (-2103L) /**< The dependency filter is not enabled */ -#define SLNETERR_RXFL_FILTER_HAS_CHILDS (-2104L) /**< The filter has childs and can't be removed */ -#define SLNETERR_RXFL_CHILD_IS_ENABLED (-2105L) /**< Can't disable filter while the child is enabled */ -#define SLNETERR_RXFL_DEPENDENCY_IS_DISABLED (-2106L) /**< Can't enable filter in case its dependency filter is disabled */ -#define SLNETERR_RXFL_MAC_SEND_MATCHDB_FAILED (-2107L) -#define SLNETERR_RXFL_MAC_SEND_ARG_DB_FAILED (-2108L) -#define SLNETERR_RXFL_MAC_SEND_NODEDB_FAILED (-2109L) -#define SLNETERR_RXFL_MAC_OPERTATION_RESUME_FAILED (-2110L) -#define SLNETERR_RXFL_MAC_OPERTATION_HALT_FAILED (-2111L) -#define SLNETERR_RXFL_NUMBER_OF_CONNECTION_POINTS_EXCEEDED (-2112L) /**< Number of connection points exceeded */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_DEPENDENCY_ACTION_IS_DROP (-2113L) /**< The dependent filter has Drop action, thus the filter can't be created */ -#define SLNETERR_RXFL_FILTER_DO_NOT_EXISTS (-2114L) /**< The filter doesn't exists */ -#define SLNETERR_RXFL_DEPEDENCY_NOT_ON_THE_SAME_LAYER (-2115L) /**< The filter and its dependency must be on the same layer */ -#define SLNETERR_RXFL_NUMBER_OF_ARGS_EXCEEDED (-2116L) /**< Number of arguments exceeded */ -#define SLNETERR_RXFL_ACTION_NO_REG_NUMBER (-2117L) /**< Action require counter number */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_LAYER_DO_NOT_FIT (-2118L) /**< the filter and its dependency should be from the same layer */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_SYSTEM_STATE_DO_NOT_FIT (-2119L) /**< The filter and its dependency system state don't fit */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_2 (-2120L) /**< The parent filter don't exist */ -#define SLNETERR_RXFL_DEPENDENT_FILTER_DO_NOT_EXIST_1 (-2121L) /**< The parent filter is null */ -#define SLNETERR_RXFL_RULE_HEADER_ACTION_TYPE_NOT_SUPPORTED (-2122L) /**< The action type is not supported */ -#define SLNETERR_RXFL_RULE_HEADER_TRIGGER_COMPARE_FUNC_OUT_OF_RANGE (-2123L) /**< The Trigger comparison function is out of range */ -#define SLNETERR_RXFL_RULE_HEADER_TRIGGER_OUT_OF_RANGE (-2124L) /**< The Trigger is out of range */ -#define SLNETERR_RXFL_RULE_HEADER_COMPARE_FUNC_OUT_OF_RANGE (-2125L) /**< The rule compare function is out of range */ -#define SLNETERR_RXFL_FRAME_TYPE_NOT_SUPPORTED (-2126L) /**< ASCII frame type string is illegal */ -#define SLNETERR_RXFL_RULE_FIELD_ID_NOT_SUPPORTED (-2127L) /**< Rule field ID is out of range */ -#define SLNETERR_RXFL_RULE_HEADER_FIELD_ID_ASCII_NOT_SUPPORTED (-2128L) /**< This ASCII field ID is not supported */ -#define SLNETERR_RXFL_RULE_HEADER_NOT_SUPPORTED (-2129L) /**< The header rule is not supported on current release */ -#define SLNETERR_RXFL_RULE_HEADER_OUT_OF_RANGE (-2130L) /**< The header rule is out of range */ -#define SLNETERR_RXFL_RULE_HEADER_COMBINATION_OPERATOR_OUT_OF_RANGE (-2131L) /**< Combination function Id is out of range */ -#define SLNETERR_RXFL_RULE_HEADER_FIELD_ID_OUT_OF_RANGE (-2132L) /**< rule field Id is out of range */ -#define SLNETERR_RXFL_UPDATE_NOT_SUPPORTED (-2133L) /**< Update not supported */ -#define SLNETERR_RXFL_NO_FILTER_DATABASE_ALLOCATE (-2134L) -#define SLNETERR_RXFL_ALLOCATION_FOR_GLOBALS_STRUCTURE_FAILED (-2135L) -#define SLNETERR_RXFL_ALLOCATION_FOR_DB_NODE_FAILED (-2136L) -#define SLNETERR_RXFL_READ_FILE_FILTER_ID_ILLEGAL (-2137L) -#define SLNETERR_RXFL_READ_FILE_NUMBER_OF_FILTER_FAILED (-2138L) -#define SLNETERR_RXFL_READ_FILE_FAILED (-2139L) -#define SLNETERR_RXFL_NO_FILTERS_ARE_DEFINED (-2140L) /**< No filters are defined in the system */ -#define SLNETERR_RXFL_NUMBER_OF_FILTER_EXCEEDED (-2141L) /**< Number of max filters exceeded */ -#define SLNETERR_RXFL_BAD_FILE_MODE (-2142L) -#define SLNETERR_RXFL_FAILED_READ_NVFILE (-2143L) -#define SLNETERR_RXFL_FAILED_INIT_STORAGE (-2144L) -#define SLNETERR_RXFL_CONTINUE_WRITE_MUST_BE_MOD_4 (-2145L) -#define SLNETERR_RXFL_FAILED_LOAD_FILE (-2146L) -#define SLNETERR_RXFL_INVALID_HANDLE (-2147L) -#define SLNETERR_RXFL_FAILED_TO_WRITE (-2148L) -#define SLNETERR_RXFL_OFFSET_OUT_OF_RANGE (-2149L) -#define SLNETERR_RXFL_ALLOC (-2150L) -#define SLNETERR_RXFL_READ_DATA_LENGTH (-2151L) -#define SLNETERR_RXFL_INVALID_FILE_ID (-2152L) -#define SLNETERR_RXFL_FILE_FILTERS_NOT_EXISTS (-2153L) -#define SLNETERR_RXFL_FILE_ALREADY_IN_USE (-2154L) -#define SLNETERR_RXFL_INVALID_ARGS (-2155L) -#define SLNETERR_RXFL_FAILED_TO_CREATE_FILE (-2156L) -#define SLNETERR_RXFL_FS_ALREADY_LOADED (-2157L) -#define SLNETERR_RXFL_UNKNOWN (-2158L) -#define SLNETERR_RXFL_FAILED_TO_CREATE_LOCK_OBJ (-2159L) -#define SLNETERR_RXFL_DEVICE_NOT_LOADED (-2160L) -#define SLNETERR_RXFL_INVALID_MAGIC_NUM (-2161L) -#define SLNETERR_RXFL_FAILED_TO_READ (-2162L) -#define SLNETERR_RXFL_NOT_SUPPORTED (-2163L) -#define SLNETERR_WLAN_INVALID_COUNTRY_CODE (-2164L) -#define SLNETERR_WLAN_NVMEM_ACCESS_FAILED (-2165L) -#define SLNETERR_WLAN_OLD_FILE_VERSION (-2166L) -#define SLNETERR_WLAN_TX_POWER_OUT_OF_RANGE (-2167L) -#define SLNETERR_WLAN_INVALID_AP_PASSWORD_LENGTH (-2168L) -#define SLNETERR_WLAN_PROVISIONING_ABORT_PROVISIONING_ALREADY_STARTED (-2169L) -#define SLNETERR_WLAN_PROVISIONING_ABORT_HTTP_SERVER_DISABLED (-2170L) -#define SLNETERR_WLAN_PROVISIONING_ABORT_PROFILE_LIST_FULL (-2171L) -#define SLNETERR_WLAN_PROVISIONING_ABORT_INVALID_PARAM (-2172L) -#define SLNETERR_WLAN_PROVISIONING_ABORT_GENERAL_ERROR (-2173L) -#define SLNETERR_WLAN_MULTICAST_EXCEED_MAX_ADDR (-2174L) -#define SLNETERR_WLAN_MULTICAST_INVAL_ADDR (-2175L) -#define SLNETERR_WLAN_AP_SCAN_INTERVAL_TOO_SHORT (-2176L) -#define SLNETERR_WLAN_PROVISIONING_CMD_NOT_EXPECTED (-2177L) - - -#define SLNETERR_WLAN_AP_ACCESS_LIST_NO_ADDRESS_TO_DELETE (-2178L) /**< List is empty, no address to delete */ -#define SLNETERR_WLAN_AP_ACCESS_LIST_FULL (-2179L) /**< access list is full */ -#define SLNETERR_WLAN_AP_ACCESS_LIST_DISABLED (-2180L) /**< access list is disabled */ -#define SLNETERR_WLAN_AP_ACCESS_LIST_MODE_NOT_SUPPORTED (-2181L) /**< Trying to switch to unsupported mode */ -#define SLNETERR_WLAN_AP_STA_NOT_FOUND (-2182L) /**< trying to disconnect station which is not connected */ - - - -/* DEVICE ERRORS CODES*/ -#define SLNETERR_SUPPLICANT_ERROR (-4097L) -#define SLNETERR_HOSTAPD_INIT_FAIL (-4098L) -#define SLNETERR_HOSTAPD_INIT_IF_FAIL (-4099L) -#define SLNETERR_WLAN_DRV_INIT_FAIL (-4100L) -#define SLNETERR_MDNS_ENABLE_FAIL (-4103L) /**< mDNS enable failed */ -#define SLNETERR_ROLE_STA_ERR (-4107L) /**< Failure to load MAC/PHY in STA role */ -#define SLNETERR_ROLE_AP_ERR (-4108L) /**< Failure to load MAC/PHY in AP role */ -#define SLNETERR_ROLE_P2P_ERR (-4109L) /**< Failure to load MAC/PHY in P2P role */ -#define SLNETERR_CALIB_FAIL (-4110L) /**< Failure of calibration */ -#define SLNETERR_RESTORE_IMAGE_COMPLETE (-4113L) /**< Return to factory image completed, perform reset */ -#define SLNETERR_UNKNOWN_ERR (-4114L) -#define SLNETERR_GENERAL_ERR (-4115L) /**< General error during init */ -#define SLNETERR_WRONG_ROLE (-4116L) -#define SLNETERR_INCOMPLETE_PROGRAMMING (-4117L) /**< Error during programming, Program new image should be invoked (see sl_FsProgram) */ - - -#define SLNETERR_PENDING_TXRX_STOP_TIMEOUT_EXP (-4118L) /**< Timeout expired before completing all TX/RX */ -#define SLNETERR_PENDING_TXRX_NO_TIMEOUT (-4119L) /**< No Timeout, still have pending TX/RX */ -#define SLNETERR_INVALID_PERSISTENT_CONFIGURATION (-4120L) /**< persistent configuration can only be set to 0 (disabled) or 1 (enabled) */ - - - -/* NETAPP ERRORS CODES*/ -#define SLNETERR_MDNS_CREATE_FAIL (-6145L) /**< mDNS create failed */ -#define SLNETERR_DEVICE_NAME_LEN_ERR (-6146L) /**< Set Dev name error codes */ -#define SLNETERR_DEVICE_NAME_INVALID (-6147L) /**< Set Dev name error codes */ -#define SLNETERR_DOMAIN_NAME_LEN_ERR (-6148L) /**< Set domain name error codes */ -#define SLNETERR_DOMAIN_NAME_INVALID (-6149L) /**< Set domain name error codes */ -#define SLNETERR_NET_APP_DNS_QUERY_NO_RESPONSE (-6150L) /**< DNS query failed, no response */ -#define SLNETERR_NET_APP_DNS_ERROR (-6151L) /**< DNS internal error */ -#define SLNETERR_NET_APP_DNS_NO_SERVER (-6152L) /**< No DNS server was specified */ -#define SLNETERR_NET_APP_DNS_TIMEOUTR (-6153L) /**< mDNS parameters error */ -#define SLNETERR_NET_APP_DNS_QUERY_FAILED (-6154L) /**< DNS query failed; no DNS server sent an 'answer' */ -#define SLNETERR_NET_APP_DNS_BAD_ADDRESS_ERROR (-6155L) /**< Improperly formatted IPv4 or IPv6 address */ -#define SLNETERR_NET_APP_DNS_SIZE_ERROR (-6156L) /**< DNS destination size is too small */ -#define SLNETERR_NET_APP_DNS_MALFORMED_PACKET (-6157L) /**< Improperly formed or corrupted DNS packet received */ -#define SLNETERR_NET_APP_DNS_BAD_ID_ERROR (-6158L) /**< DNS packet from server does not match query ID */ -#define SLNETERR_NET_APP_DNS_PARAM_ERROR (-6159L) /**< Invalid params */ -#define SLNETERR_NET_APP_DNS_SERVER_NOT_FOUND (-6160L) /**< Server not found in Client list of DNS servers */ -#define SLNETERR_NET_APP_DNS_PACKET_CREATE_ERROR (-6161L) /**< Error creating DNS packet */ -#define SLNETERR_NET_APP_DNS_EMPTY_DNS_SERVER_LIST (-6162L) /**< DNS Client's list of DNS servers is empty */ -#define SLNETERR_NET_APP_DNS_SERVER_AUTH_ERROR (-6163L) /**< Server not able to authenticate answer/authority data*/ -#define SLNETERR_NET_APP_DNS_ZERO_GATEWAY_IP_ADDRESS (-6164L) /**< DNS Client IP instance has a zero gateway IP address */ -#define SLNETERR_NET_APP_DNS_MISMATCHED_RESPONSE (-6165L) /**< Server response type does not match the query request*/ -#define SLNETERR_NET_APP_DNS_DUPLICATE_ENTRY (-6166L) /**< Duplicate entry exists in DNS server table */ -#define SLNETERR_NET_APP_DNS_RETRY_A_QUERY (-6167L) /**< SOA status returned; web site only exists as IPv4 */ -#define SLNETERR_NET_APP_DNS_INVALID_ADDRESS_TYPE (-6168L) /**< IP address type (e.g. IPv6L) not supported */ -#define SLNETERR_NET_APP_DNS_IPV6_NOT_SUPPORTED (-6169L) /**< IPv6 disabled */ -#define SLNETERR_NET_APP_DNS_NEED_MORE_RECORD_BUFFER (-6170L) /**< The buffer size is not enough. */ -#define SLNETERR_NET_APP_MDNS_ERROR (-6171L) /**< MDNS internal error. */ -#define SLNETERR_NET_APP_MDNS_PARAM_ERROR (-6172L) /**< MDNS parameters error. */ -#define SLNETERR_NET_APP_MDNS_CACHE_ERROR (-6173L) /**< The Cache size is not enough. */ -#define SLNETERR_NET_APP_MDNS_UNSUPPORTED_TYPE (-6174L) /**< The unsupported resource record type. */ -#define SLNETERR_NET_APP_MDNS_DATA_SIZE_ERROR (-6175L) /**< The data size is too big. */ -#define SLNETERR_NET_APP_MDNS_AUTH_ERROR (-6176L) /**< Attempting to parse too large a data. */ -#define SLNETERR_NET_APP_MDNS_PACKET_ERROR (-6177L) /**< The packet can not add the resource record. */ -#define SLNETERR_NET_APP_MDNS_DEST_ADDRESS_ERROR (-6178L) /**< The destination address error. */ -#define SLNETERR_NET_APP_MDNS_UDP_PORT_ERROR (-6179L) /**< The udp port error. */ -#define SLNETERR_NET_APP_MDNS_NOT_LOCAL_LINK (-6180L) /**< The message that not originate from the local link. */ -#define SLNETERR_NET_APP_MDNS_EXCEED_MAX_LABEL (-6181L) /**< The data exceed the max label size. */ -#define SLNETERR_NET_APP_MDNS_EXIST_UNIQUE_RR (-6182L) /**< At least one unique record in the cache. */ -#define SLNETERR_NET_APP_MDNS_EXIST_ANSWER (-6183L) /**< At least one answer record in the cache. */ -#define SLNETERR_NET_APP_MDNS_EXIST_SAME_QUERY (-6184L) /**< Exist the same query. */ -#define SLNETERR_NET_APP_MDNS_DUPLICATE_SERVICE (-6185L) /**< Duplicate service. */ -#define SLNETERR_NET_APP_MDNS_NO_ANSWER (-6186L) /**< No response for one-shot query. */ -#define SLNETERR_NET_APP_MDNS_NO_KNOWN_ANSWER (-6187L) /**< No known answer for query. */ -#define SLNETERR_NET_APP_MDNS_NAME_MISMATCH (-6188L) /**< The name mismatch. */ -#define SLNETERR_NET_APP_MDNS_NOT_STARTED (-6189L) /**< MDNS does not start. */ -#define SLNETERR_NET_APP_MDNS_HOST_NAME_ERROR (-6190L) /**< MDNS host name error. */ -#define SLNETERR_NET_APP_MDNS_NO_MORE_ENTRIES (-6191L) /**< No more entries be found. */ -#define SLNETERR_NET_APP_MDNS_SERVICE_TYPE_MISMATCH (-6192L) /**< The service type mismatch */ -#define SLNETERR_NET_APP_MDNS_LOOKUP_INDEX_ERROR (-6193L) /**< Index is bigger than number of services. */ -#define SLNETERR_NET_APP_MDNS_MAX_SERVICES_ERROR (-6194L) -#define SLNETERR_NET_APP_MDNS_IDENTICAL_SERVICES_ERROR (-6195L) -#define SLNETERR_NET_APP_MDNS_EXISTED_SERVICE_ERROR (-6196L) -#define SLNETERR_NET_APP_MDNS_ERROR_SERVICE_NAME_ERROR (-6197L) -#define SLNETERR_NET_APP_MDNS_RX_PACKET_ALLOCATION_ERROR (-6198L) -#define SLNETERR_NET_APP_MDNS_BUFFER_SIZE_ERROR (-6199L) -#define SLNETERR_NET_APP_MDNS_NET_APP_SET_ERROR (-6200L) -#define SLNETERR_NET_APP_MDNS_GET_SERVICE_LIST_FLAG_ERROR (-6201L) -#define SLNETERR_NET_APP_MDNS_MDNS_NO_CONFIGURATION_ERROR (-6202L) -#define SLNETERR_NET_APP_MDNS_STATUS_ERROR (-6203L) -#define SLNETERR_NET_APP_ENOBUFS (-6204L) -#define SLNETERR_NET_APP_DNS_IPV6_REQ_BUT_IPV6_DISABLED (-6205L) /**< trying to issue ipv6 DNS request but ipv6 is disabled */ -#define SLNETERR_NET_APP_DNS_INVALID_FAMILY_TYPE (-6206L) /**< Family type is not ipv4 and not ipv6 */ -#define SLNETERR_NET_APP_DNS_REQ_TOO_BIG (-6207L) /**< DNS request size is too big */ -#define SLNETERR_NET_APP_DNS_ALLOC_ERROR (-6208L) /**< Allocation error */ -#define SLNETERR_NET_APP_DNS_EXECUTION_ERROR (-6209L) /**< Execution error */ -#define SLNETERR_NET_APP_P2P_ROLE_IS_NOT_CONFIGURED (-6210L) /**< role p2p is not configured yet, should be CL or GO in order to execute command */ -#define SLNETERR_NET_APP_INCORECT_ROLE_FOR_APP (-6211L) /**< incorrect role for specific application */ -#define SLNETERR_NET_APP_INCORECT_APP_MASK (-6212L) /**< mask does not match any app */ -#define SLNETERR_NET_APP_MDNS_ALREADY_STARTED (-6213L) /**< mdns application already started */ -#define SLNETERR_NET_APP_HTTP_SERVER_ALREADY_STARTED (-6214L) /**< http server application already started */ - -#define SLNETERR_NET_APP_HTTP_GENERAL_ERROR (-6216L) /**< New error - Http handle request failed */ -#define SLNETERR_NET_APP_HTTP_INVALID_TIMEOUT (-6217L) /**< New error - Http timeout invalid argument */ -#define SLNETERR_NET_APP_INVALID_URN_LENGTH (-6218L) /**< invalid URN length */ -#define SLNETERR_NET_APP_RX_BUFFER_LENGTH (-6219L) /**< size of the requested services is smaller than size of the user buffer */ - - - -/*< NETCFG ERRORS CODES*/ -#define SLNETERR_STATIC_ADDR_SUBNET_ERROR (-8193L) -#define SLNETERR_INCORRECT_IPV6_STATIC_LOCAL_ADDR (-8194L) /**< Ipv6 Local address prefix is wrong */ -#define SLNETERR_INCORRECT_IPV6_STATIC_GLOBAL_ADDR (-8195L) /**< Ipv6 Global address prefix is wrong */ -#define SLNETERR_IPV6_LOCAL_ADDR_SHOULD_BE_SET_FIRST (-8195L) /**< Attempt to set ipv6 global address before ipv6 local address is set */ - - - -/* NETUTIL ERRORS CODES */ -#define SLNETERR_NETUTIL_CRYPTO_GENERAL (-12289L) -#define SLNETERR_NETUTIL_CRYPTO_INVALID_INDEX (-12290L) -#define SLNETERR_NETUTIL_CRYPTO_INVALID_PARAM (-12291L) -#define SLNETERR_NETUTIL_CRYPTO_MEM_ALLOC (-12292L) -#define SLNETERR_NETUTIL_CRYPTO_INVALID_DB_VER (-12293L) -#define SLNETERR_NETUTIL_CRYPTO_UNSUPPORTED_OPTION (-12294L) -#define SLNETERR_NETUTIL_CRYPTO_BUFFER_TOO_SMALL (-12295L) -#define SLNETERR_NETUTIL_CRYPTO_EMPTY_DB_ENTRY (-12296L) -#define SLNETERR_NETUTIL_CRYPTO_NON_TEMPORARY_KEY (-12297L) -#define SLNETERR_NETUTIL_CRYPTO_DB_ENTRY_NOT_FREE (-12298L) -#define SLNETERR_NETUTIL_CRYPTO_CORRUPTED_DB_FILE (-12299L) - - - -/* GENERAL ERRORS CODES*/ -#define SLNETERR_INVALID_OPCODE (-14337L) -#define SLNETERR_INVALID_PARAM (-14338L) -#define SLNETERR_STATUS_ERROR (-14341L) -#define SLNETERR_NVMEM_ACCESS_FAILED (-14342L) -#define SLNETERR_NOT_ALLOWED_NWP_LOCKED (-14343L) /**< Device is locked, Return to Factory Image or Program new image should be invoked (see sl_FsCtl, sl_FsProgram) */ - -/* SECURITY ERRORS CODE */ -#define SLNETERR_LOADING_CERTIFICATE_STORE (-28673L) - -/* Device is Locked! Return to Factory Image or Program new - image should be invoked (see sl_FsCtl, sl_FsProgram) */ -#define SLNETERR_DEVICE_LOCKED_SECURITY_ALERT (-28674L) - - - -/* INTERNAL HOST ERRORS CODES*/ - -/* Receive this error in case there are no resources to issue the command - If possible, increase the number of MAX_CONCURRENT_ACTIONS (result in memory increase) - If not, try again later */ -#define SLNETERR_POOL_IS_EMPTY (-2000L) - -/* Receive this error in case a given length for RX buffer was too small. - Receive payload was bigger than the given buffer size. Therefore, payload is cut according to receive size - Recommend to increase buffer size */ -#define SLNETERR_ESMALLBUF (-2001L) - -/* Receive this error in case zero length is supplied to a "get" API - Recommend to supply length according to requested information (view options defines for help) */ -#define SLNETERR_EZEROLEN (-2002L) - -/* User supplied invalid parameter */ -#define SLNETERR_INVALPARAM (-2003L) - -/* Failed to open interface */ -#define SLNETERR_BAD_INTERFACE (-2004L) - -/* API has been aborted due to an error detected by host driver */ -#define SLNETERR_API_ABORTED (-2005L) - -/* Parameters are invalid */ -#define SLNETERR_RET_CODE_INVALID_INPUT (-2006L) - -/* Driver internal error */ -#define SLNETERR_RET_CODE_SELF_ERROR (-2007L) - -/* NWP internal error */ -#define SLNETERR_RET_CODE_NWP_IF_ERROR (-2008L) - -/* malloc error */ -#define SLNETERR_RET_CODE_MALLOC_ERROR (-2009L) - -/* protocol error */ -#define SLNETERR_RET_CODE_PROTOCOL_ERROR (-2010L) - -/* API has been aborted, command is not allowed in device lock state */ -#define SLNETERR_RET_CODE_DEV_LOCKED (-2011L) - -/* SlNetSock_Start cannot be invoked twice */ -#define SLNETERR_RET_CODE_DEV_ALREADY_STARTED (-2012L) - -/* SL Net API is in progress */ -#define SLNETERR_RET_CODE_API_COMMAND_IN_PROGRESS (-2013L) - -/* Provisioning is in progress - */ -#define SLNETERR_RET_CODE_PROVISIONING_IN_PROGRESS (-2014L) - -/* Wrong ping parameters - ping cannot be called with the following parameters: -1. infinite ping packet -2. report only when finished -3. no callback supplied */ -#define SLNETERR_RET_CODE_NET_APP_PING_INVALID_PARAMS (-2015L) - - -/* SlNetSock select already in progress. - this error will be returned if app will try to call - SlNetSock_select blocking when there is already select trigger in progress */ -#define SLNETERR_RET_CODE_SOCKET_SELECT_IN_PROGRESS_ERROR (-2016L) - -#define SLNETERR_RET_CODE_STOP_IN_PROGRESS (-2017L) - - -/* The device has not been started yet */ -#define SLNETERR_RET_CODE_DEV_NOT_STARTED (-2018L) - -/* The event link was not found in the list */ -#define SLNETERR_RET_CODE_EVENT_LINK_NOT_FOUND (-2019L) - -/* Function couldn't find any free space/location */ -#define SLNETERR_RET_CODE_NO_FREE_SPACE (-2020L) - -/* Function couldn't execute correctly */ -#define SLNETERR_RET_CODE_FUNCTION_FAILED (-2021L) - -/* Mutex creation failed */ -#define SLNETERR_RET_CODE_MUTEX_CREATION_FAILED (-2022L) - -/* Function couldn't find the requested resource */ -#define SLNETERR_RET_CODE_COULDNT_FIND_RESOURCE (-2023L) - -/* Interface doesn't support the non mandatory function */ -#define SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN (-2024L) - -/* Socket creation in progress */ -#define SLNETERR_RET_CODE_SOCKET_CREATION_IN_PROGRESS (-2025L) - -/* Unsupported scenario, option or feature */ -#define SLNETERR_RET_CODE_UNSUPPORTED (-2026L) - - -/* sock related API's from SlNetIf_Config_t failed */ -#define SLNETSOCK_ERR_SOCKCREATE_FAILED (-3000L) -#define SLNETSOCK_ERR_SOCKCLOSE_FAILED (-3001L) -#define SLNETSOCK_ERR_SOCKSELECT_FAILED (-3002L) -#define SLNETSOCK_ERR_SOCKSETOPT_FAILED (-3003L) -#define SLNETSOCK_ERR_SOCKGETOPT_FAILED (-3004L) -#define SLNETSOCK_ERR_SOCKRECVFROM_FAILED (-3005L) -#define SLNETSOCK_ERR_SOCKSENDTO_FAILED (-3006L) -#define SLNETSOCK_ERR_SOCKSHUTDOWN_FAILED (-3007L) -#define SLNETSOCK_ERR_SOCKACCEPT_FAILED (-3008L) -#define SLNETSOCK_ERR_SOCKBIND_FAILED (-3009L) -#define SLNETSOCK_ERR_SOCKLISTEN_FAILED (-3000L) -#define SLNETSOCK_ERR_SOCKCONNECT_FAILED (-3001L) -#define SLNETSOCK_ERR_SOCKGETPEERNAME_FAILED (-3002L) -#define SLNETSOCK_ERR_SOCKGETLOCALNAME_FAILED (-3003L) -#define SLNETSOCK_ERR_SOCKRECV_FAILED (-3004L) -#define SLNETSOCK_ERR_SOCKSEND_FAILED (-3005L) -#define SLNETSOCK_ERR_SOCKSTARTSEC_FAILED (-3006L) - -/* util related API's from SlNetIf_Config_t failed */ -#define SLNETUTIL_ERR_UTILGETHOSTBYNAME_FAILED (-3100L) - -/* - * base for util error codes related to SlNetUtil_getAddrInfo and - * SlNetUtil_gaiStrErr - */ -#define SLNETUTIL_EAI_BASE (-3120L) - -/* - * util error codes related to SlNetUtil_getAddrInfo and SlNetUtil_gaiStrErr - * The numbering of these codes MUST match the order of the strErrorMsgs array - * in - */ -#define SLNETUTIL_EAI_AGAIN (-3121L) -#define SLNETUTIL_EAI_BADFLAGS (-3122L) -#define SLNETUTIL_EAI_FAIL (-3123L) -#define SLNETUTIL_EAI_FAMILY (-3124L) -#define SLNETUTIL_EAI_MEMORY (-3125L) -#define SLNETUTIL_EAI_NONAME (-3126L) -#define SLNETUTIL_EAI_SERVICE (-3127L) -#define SLNETUTIL_EAI_SOCKTYPE (-3128L) -#define SLNETUTIL_EAI_SYSTEM (-3129L) -#define SLNETUTIL_EAI_OVERFLOW (-3130L) -#define SLNETUTIL_EAI_ADDRFAMILY (-3131L) - -/* if related API's from SlNetIf_Config_t failed */ -#define SLNETIF_ERR_IFLOADSECOBJ_FAILED (-3200L) -#define SLNETIF_ERR_IFGETIPADDR_FAILED (-3201L) -#define SLNETIF_ERR_IFGETCONNECTIONSTATUS_FAILED (-3202L) -#define SLNETIF_ERR_IFCREATECONTEXT_FAILED (-3203L) - -/*! - - Close the Doxygen group. - @} - -*/ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __SL_NET_ERR_H__ */ diff --git a/ext/hal/ti/simplelink/source/ti/net/slnetif.c b/ext/hal/ti/simplelink/source/ti/net/slnetif.c deleted file mode 100644 index 2fbb616d55e..00000000000 --- a/ext/hal/ti/simplelink/source/ti/net/slnetif.c +++ /dev/null @@ -1,853 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -/* Global includes */ -#include -#include -#include -#include - -#include -#include - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#define SLNETIF_NORMALIZE_NEEDED 0 -#if SLNETIF_NORMALIZE_NEEDED - #define SLNETIF_NORMALIZE_RET_VAL(retVal,err) ((retVal < 0)?(retVal = err):(retVal)) -#else - #define SLNETIF_NORMALIZE_RET_VAL(retVal,err) -#endif - -/* Interface maximum priority */ -#define SLNETIF_MAX_PRIORITY (15) - -/* The 32bit interface flags structure: - Bits 0-3 : interface priority - Bit 4 : Interface state - Bits 5-31 : Reserved -*/ -#define IF_PRIORITY_BITS (0x000f) -#define IF_STATE_BIT (0x0010) - -/* this macro returns the priority of the interface */ -#define GET_IF_PRIORITY(netIf) ((netIf).flags & IF_PRIORITY_BITS) - -/* this macro reset the priority of the interface */ -#define RESET_IF_PRIORITY(netIf) ((netIf).flags &= ~IF_PRIORITY_BITS) - -/* this macro set the priority of the interface */ -#define SET_IF_PRIORITY(netIf, priority) ((netIf).flags |= ((int32_t)priority)) - -/* this macro returns the state of the interface */ -#define GET_IF_STATE(netIf) (((netIf).flags & IF_STATE_BIT)?SLNETIF_STATE_ENABLE:SLNETIF_STATE_DISABLE) - -/* this macro set the interface to enable state */ -#define SET_IF_STATE_ENABLE(netIf) ((netIf).flags |= IF_STATE_BIT) - -/* this macro set the interface to disable state */ -#define SET_IF_STATE_DISABLE(netIf) ((netIf).flags &= ~IF_STATE_BIT) - -/* Check if the state bit is set */ -#define IS_STATE_BIT_SET(queryBitmap) (0 != (queryBitmap & SLNETIF_QUERY_IF_STATE_BIT)) - -/* Check if the connection status bit is set */ -#define IS_CONNECTION_STATUS_BIT_SET(queryBitmap) (0 != (queryBitmap & SLNETIF_QUERY_IF_CONNECTION_STATUS_BIT)) - -/* Return last found netIf, if none of the existing interfaces answers - the query */ -#define IS_ALLOW_PARTIAL_MATCH_BIT_SET(queryBitmap) (0 != (queryBitmap & SLNETIF_QUERY_IF_ALLOW_PARTIAL_MATCH_BIT)) - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - - -/* Interface Node */ -typedef struct SlNetIf_Node_t -{ - SlNetIf_t netIf; - struct SlNetIf_Node_t *next; -} SlNetIf_Node_t; - -/*****************************************************************************/ -/* Global declarations */ -/*****************************************************************************/ - -static SlNetIf_Node_t * SlNetIf_listHead = NULL; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -static int32_t SlNetIf_configCheck(const SlNetIf_Config_t *ifConf); - -//***************************************************************************** -// -// SlNetIf_configCheck - Checks that all mandatory configuration exists -// -//***************************************************************************** - -static int32_t SlNetIf_configCheck(const SlNetIf_Config_t *ifConf) -{ - /* Check if the mandatory configuration exists - This configuration needs to be updated when new mandatory is added */ - if ((NULL != ifConf) && - (NULL != ifConf->sockCreate) && - (NULL != ifConf->sockClose) && - (NULL != ifConf->sockSelect) && - (NULL != ifConf->sockSetOpt) && - (NULL != ifConf->sockGetOpt) && - (NULL != ifConf->sockRecvFrom) && - (NULL != ifConf->sockSendTo) && - (NULL != ifConf->ifGetIPAddr) && - (NULL != ifConf->ifGetConnectionStatus) ) - { - /* All mandatory configuration exists - return success */ - return SLNETERR_RET_CODE_OK; - } - else - { - /* Not all mandatory configuration exists - return error code */ - return SLNETERR_INVALPARAM; - } - -} - -//***************************************************************************** -// -// SlNetIf_init - Initialize the SlNetIf module -// -//***************************************************************************** -int32_t SlNetIf_init(int32_t flags) -{ - return SLNETERR_RET_CODE_OK; -} - - -//***************************************************************************** -// -// SlNetIf_add - Adding new interface -// -//***************************************************************************** -int32_t SlNetIf_add(uint16_t ifID, char *ifName, const SlNetIf_Config_t *ifConf, uint8_t priority) -{ - SlNetIf_Node_t *ifNode = SlNetIf_listHead; - SlNetIf_Node_t *prvNode = NULL; - char *allocName = NULL; - int16_t strLen; - int32_t retVal; - - /* Check if ifID is a valid input - Only one bit is set (Pow of 2) or if - the priority isn't a valid input */ - if ( (false == ONLY_ONE_BIT_IS_SET(ifID)) || (priority > SLNETIF_MAX_PRIORITY) ) - { - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* Run over the interface list until finding the required ifID or Until - reaching the end of the list */ - while (NULL != ifNode) - { - /* Check if the identifier of the interface is equal to the input */ - if ((ifNode->netIf).ifID == ifID) - { - /* Required interface found, ifID cannot be used again */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - /* Check if the identifier of the interface is equal to the input */ - if ((GET_IF_PRIORITY(ifNode->netIf)) > priority) - { - /* Higher priority interface found, save location */ - prvNode = ifNode; - } - else - { - break; - } - ifNode = ifNode->next; - } - - - /* Check if all required configuration exists */ - retVal = SlNetIf_configCheck(ifConf); - - /* Check retVal in order to continue with adding the interface */ - if (SLNETERR_RET_CODE_OK == retVal) - { - /* Interface node memory allocation */ - /* Allocate memory for new interface node for the interface list */ - ifNode = malloc(sizeof(SlNetIf_Node_t)); - - /* Check if the memory allocated successfully */ - if (NULL == ifNode) - { - /* Allocation failed, return error code */ - return SLNETERR_RET_CODE_MALLOC_ERROR; - } - - /* Interface name memory allocation */ - /* Check if memory allocation for the name of the string is required */ - if (NULL != ifName) - { - /* Store the length of the interface name */ - strLen = strlen(ifName); - - /* Allocate memory that will store the name of the interface */ - allocName = malloc(strLen + 1); - - /* Check if the memory allocated successfully */ - if (NULL == allocName) - { - /* Allocation failed, free ifNode before returning from - function */ - free(ifNode); - return SLNETERR_RET_CODE_MALLOC_ERROR; - } - /* Copy the input name into the allocated memory */ - strncpy(allocName, ifName, strLen + 1); - } - - /* Fill the allocated interface node with the input parameters */ - - /* Copy the interface ID */ - (ifNode->netIf).ifID = ifID; - /* Connect the string allocated memory into the allocated interface */ - (ifNode->netIf).ifName = allocName; - /* Copy the interface configuration */ - (ifNode->netIf).ifConf = (SlNetIf_Config_t *)ifConf; - /* Reset the flags, set state to ENABLE and set the priority */ - (ifNode->netIf).flags = 0; - SET_IF_PRIORITY(ifNode->netIf, priority); - SET_IF_STATE_ENABLE(ifNode->netIf); - - /* Check if CreateContext function exists */ - if (NULL != ifConf->ifCreateContext) - { - /* Function exists, run it and fill the context */ - retVal = ifConf->ifCreateContext(ifID, allocName, &((ifNode->netIf).ifContext)); - } - - /* Check retVal before continuing */ - if (SLNETERR_RET_CODE_OK == retVal) - { - /* After creating and filling the interface, add it to the right - place in the list according to its priority */ - - /* Check if there isn't any higher priority node */ - if (NULL == prvNode) - { - /* there isn't any higher priority node so check if list is - empty */ - if (NULL != SlNetIf_listHead) - { - /* List isn't empty, so use the new allocated interface - as the new head and connect the old list head as the - following node */ - ifNode->next = SlNetIf_listHead; - } - else - { - /* List is empty, so the new allocated interface will be - the head list */ - ifNode->next = NULL; - } - SlNetIf_listHead = ifNode; - } - else - { - /* Higher priority exists, connect the allocated node after - the prvNode and the next node (if exists) of prvNode to - the next of the node */ - ifNode->next = prvNode->next; - prvNode->next = ifNode; - } - } - } - - return retVal; -} - - -//***************************************************************************** -// -// SlNetIf_getIfByID - Get interface configuration from interface ID -// -//***************************************************************************** -SlNetIf_t * SlNetIf_getIfByID(uint16_t ifID) -{ - SlNetIf_Node_t *ifNode = SlNetIf_listHead; - - /* Check if ifID is a valid input - Only one bit is set (Pow of 2) */ - if (false == ONLY_ONE_BIT_IS_SET(ifID)) - { - return NULL; - } - - /* Run over the interface list until finding the required ifID or Until - reaching the end of the list */ - while (NULL != ifNode) - { - /* Check if the identifier of the interface is equal to the input */ - if ((ifNode->netIf).ifID == ifID) - { - /* Required interface found, return the interface pointer */ - return &(ifNode->netIf); - } - ifNode = ifNode->next; - } - - /* Interface identifier was not found */ - return NULL; -} - -//***************************************************************************** -// -// SlNetIf_queryIf - Get interface configuration with the highest priority -// from the provided interface bitmap -// Note: ifBitmap - 0 is not a valid input -// -//***************************************************************************** -SlNetIf_t * SlNetIf_queryIf(uint32_t ifBitmap, uint32_t queryBitmap) -{ - SlNetIf_Node_t *ifNode = SlNetIf_listHead; - SlNetIf_t *bestPartialMatchIf = NULL; - - if (0 == ifBitmap) - { - return NULL; - } - - /* Run over the interface list until finding the first ifID that is - set in the ifBitmap or Until reaching the end of the list if no - ifID were found */ - while (NULL != ifNode) - { - /* Check if the identifier of the interface is equal to the input */ - if (((ifNode->netIf).ifID) & ifBitmap) - { - /* Save the netIf only at the first match */ - if (NULL == bestPartialMatchIf) - { - bestPartialMatchIf = &(ifNode->netIf); - } - /* Skip over Bitmap queries */ - if ( 0 != queryBitmap) - { - /* Check if the state bit needs to be set and if it is */ - if ( (true == IS_STATE_BIT_SET(queryBitmap)) && - (SLNETIF_STATE_DISABLE == (GET_IF_STATE(ifNode->netIf))) ) - { - /* State is disabled when needed to be set, continue - to the next interface */ - ifNode = ifNode->next; - continue; - } - /* Check if the connection status bit needs to be set - and if it is */ - if ( (true == IS_CONNECTION_STATUS_BIT_SET(queryBitmap)) && - (SLNETIF_STATUS_DISCONNECTED == SlNetIf_getConnectionStatus((ifNode->netIf).ifID)) ) - { - /* Connection status is disconnected when needed to - be connected, continue to the next interface */ - ifNode = ifNode->next; - continue; - } - } - /* Required interface found, return the interface pointer */ - return &(ifNode->netIf); - } - ifNode = ifNode->next; - } - - /* When bit is set, return the last interface found if there isn't - an existing interface that answers the query return the last - netIf that was found */ - if (true == IS_ALLOW_PARTIAL_MATCH_BIT_SET(queryBitmap)) - { - return bestPartialMatchIf; - } - else - { - return NULL; - } - -} - - -//***************************************************************************** -// -// SlNetIf_getNameByID - Get interface Name from interface ID -// -//***************************************************************************** -const char * SlNetIf_getNameByID(uint16_t ifID) -{ - SlNetIf_t *netIf; - - /* Run validity check and find the requested interface */ - netIf = SlNetIf_getIfByID(ifID); - - /* Check if the requested interface exists or the function returned NULL */ - if (NULL == netIf) - { - /* Interface doesn't exists or invalid input, return NULL */ - return NULL; - } - else - { - /* Interface exists, return the interface name */ - return netIf->ifName; - } -} - - -//***************************************************************************** -// -// SlNetIf_getIDByName - Get interface ID from interface name -// -//***************************************************************************** -int32_t SlNetIf_getIDByName(char *ifName) -{ - SlNetIf_Node_t *ifNode = SlNetIf_listHead; - - /* Check if ifName is a valid input */ - if (NULL == ifName) - { - return(SLNETERR_RET_CODE_INVALID_INPUT); - } - - /* Run over the interface list until finding the required ifID or Until - reaching the end of the list */ - while (NULL != ifNode) - { - /* Check if the identifier of the interface is equal to the input */ - if (strcmp((ifNode->netIf).ifName, ifName) == 0) - { - /* Required interface found, return the interface identifier */ - return ((ifNode->netIf).ifID); - } - ifNode = ifNode->next; - } - - /* Interface identifier was not found, return error code */ - return(SLNETERR_RET_CODE_INVALID_INPUT); -} - - -//***************************************************************************** -// -// SlNetIf_getPriority - Get interface priority -// -//***************************************************************************** -int32_t SlNetIf_getPriority(uint16_t ifID) -{ - SlNetIf_t *netIf; - - /* Run validity check and find the requested interface */ - netIf = SlNetIf_getIfByID(ifID); - - /* Check if the requested interface exists or the function returned NULL */ - if (NULL == netIf) - { - /* Interface doesn't exists or invalid input, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - else - { - /* Interface exists, return interface priority */ - return GET_IF_PRIORITY(*netIf); - } -} - - -//***************************************************************************** -// -// SlNetIf_setPriority - Set interface priority -// -//***************************************************************************** -int32_t SlNetIf_setPriority(uint16_t ifID, uint8_t priority) -{ - SlNetIf_Node_t *ifListNode = SlNetIf_listHead; - SlNetIf_Node_t *prvIfListNode = SlNetIf_listHead; - SlNetIf_Node_t *reqIfListNode = NULL; - bool connectAgain = false; - - if (priority > SLNETIF_MAX_PRIORITY) - { - /* Run validity check and find the requested interface */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* Find the location of required interface */ - while (NULL != ifListNode) - { - /* If the location of the required interface found, store the - location */ - if ((ifListNode->netIf.ifID) == ifID) - { - reqIfListNode = ifListNode; - /* Check if the required interface is the last node and needs - lower priority than the previous node, only update of the - priority is required for this node */ - if (NULL == ifListNode->next) - { - if (GET_IF_PRIORITY(prvIfListNode->netIf) >= priority) - { - /* The required interface is the last node and needs - lower priority than the previous node, only update - of the priority is required for this node */ - break; - } - else - { - /* The required interface is the last node but has - higher priority than the previous node, disconnect - the interface from the list. connect the previous node - to the end of the list - If this is not the only node in the list, find where - it now belongs based on its new priority. */ - if (reqIfListNode != SlNetIf_listHead) - { - prvIfListNode->next = NULL; - connectAgain = true; - /* This is the end of the list, so stop looping */ - break; - } - } - } - /* Check if the required interface is the first node in the list */ - else if (SlNetIf_listHead == ifListNode) - { - if ( (NULL == ifListNode->next) || ((GET_IF_PRIORITY(ifListNode->next->netIf)) <= priority) ) - { - /* The required interface is the first node and needs - higher priority than the following node, only update - of the priority is required for this node */ - break; - } - /* The required interface is the first node but doesn't need - higher priority than the following node so the following - node will be the first node of the list */ - else - { - SlNetIf_listHead = ifListNode->next; - connectAgain = true; - } - } - /* The required interface isn't the first or last node and needs - priority change but is in the correct location, only update - of the priority is required for this node */ - else if ( (GET_IF_PRIORITY(prvIfListNode->netIf) >= priority) && ((GET_IF_PRIORITY(ifListNode->next->netIf)) <= priority) ) - { - break; - } - /* The required interface isn't the first or last node and needs - priority change, disconnect it from the list. connect the - previous node with the following node */ - else - { - prvIfListNode->next = prvIfListNode->next->next; - connectAgain = true; - } - } - else - { - prvIfListNode = ifListNode; - } - ifListNode = ifListNode->next; - } - - /* When connectAgain is set, there's a need to find where to add back - the required interface according to the priority */ - if (connectAgain == true) - { - ifListNode = SlNetIf_listHead; - while (NULL != ifListNode) - { - /* If the incoming priority is higher than any present */ - if ( (ifListNode == SlNetIf_listHead) ) - { - if ((GET_IF_PRIORITY(ifListNode->netIf)) <= priority) - { - reqIfListNode->next = ifListNode; - SlNetIf_listHead = reqIfListNode; - break; - } - } - - /* Check if the priority of the current interface is higher of - the required priority, if so, store it as the previous - interface and continue to search until finding interface with - lower priority and than connect the required interface to the - prior interface */ - if ((GET_IF_PRIORITY(ifListNode->netIf)) > priority) - { - prvIfListNode = ifListNode; - - } - else - { - reqIfListNode->next = prvIfListNode->next; - prvIfListNode->next = reqIfListNode; - break; - } - ifListNode = ifListNode->next; - - if (NULL == ifListNode) - { - /* All interfaces have higher priorities than reqIfListNode */ - prvIfListNode->next = reqIfListNode; - reqIfListNode->next = NULL; - break; - } - } - } - - if (NULL != reqIfListNode) - { - /* Interface exists, set the interface priority */ - RESET_IF_PRIORITY(reqIfListNode->netIf); - SET_IF_PRIORITY(reqIfListNode->netIf, priority); - } - - return SLNETERR_RET_CODE_OK; -} - - -//***************************************************************************** -// -// SlNetIf_setState - Set interface state -// -//***************************************************************************** -int32_t SlNetIf_setState(uint16_t ifID, SlNetIfState_e ifState) -{ - SlNetIf_t *netIf; - - /* Run validity check and find the requested interface */ - netIf = SlNetIf_getIfByID(ifID); - - /* Check if the requested interface exists or the function returned NULL */ - if (NULL == netIf) - { - /* Interface doesn't exists or invalid input, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - else - { - /* Interface exists, set the interface state */ - if (ifState == SLNETIF_STATE_DISABLE) - { - /* Interface state - Disable */ - SET_IF_STATE_DISABLE(*netIf); - } - else - { - /* Interface state - Enable */ - SET_IF_STATE_ENABLE(*netIf); - } - } - return SLNETERR_RET_CODE_OK; -} - - -//***************************************************************************** -// -// SlNetIf_getState - Get interface state -// -//***************************************************************************** -int32_t SlNetIf_getState(uint16_t ifID) -{ - SlNetIf_t *netIf; - - /* Run validity check and find the requested interface */ - netIf = SlNetIf_getIfByID(ifID); - - /* Check if the requested interface exists or the function returned NULL */ - if (NULL == netIf) - { - /* Interface doesn't exists or invalid input, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - else - { - /* Interface exists, return interface state */ - return GET_IF_STATE(*netIf); - } -} - - -//***************************************************************************** -// -// SlNetIf_getIPAddr - Get IP Address of specific interface -// -//***************************************************************************** -int32_t SlNetIf_getIPAddr(uint16_t ifID, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr) -{ - SlNetIf_t *netIf; - int32_t retVal; - - /* Run validity check and find the requested interface */ - netIf = SlNetIf_getIfByID(ifID); - - /* Check if the requested interface exists or the function returned NULL */ - if (NULL == netIf) - { - /* Interface doesn't exists or invalid input, return NULL */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - else - { - /* Interface exists, return interface IP address */ - retVal = (netIf->ifConf)->ifGetIPAddr(netIf->ifContext, addrType, addrConfig, ipAddr); - SLNETIF_NORMALIZE_RET_VAL(retVal,SLNETIF_ERR_IFGETIPADDR_FAILED); - - /* Check retVal for error codes */ - if (retVal < SLNETERR_RET_CODE_OK) - { - /* Return retVal, function error */ - return retVal; - } - else - { - /* Return success */ - return SLNETERR_RET_CODE_OK; - } - } -} - - -//***************************************************************************** -// -// SlNetIf_getConnectionStatus - Get interface connection status -// -//***************************************************************************** -int32_t SlNetIf_getConnectionStatus(uint16_t ifID) -{ - SlNetIf_t *netIf; - int16_t connectionStatus; - - /* Run validity check and find the requested interface */ - netIf = SlNetIf_getIfByID(ifID); - - /* Check if the requested interface exists or the function returned NULL */ - if (NULL == netIf) - { - /* Interface doesn't exists or invalid input, return NULL */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - else - { - /* Interface exists, return interface connection status */ - connectionStatus = (netIf->ifConf)->ifGetConnectionStatus(netIf->ifContext); - - /* Interface exists, set the interface state */ - if (connectionStatus == SLNETIF_STATUS_DISCONNECTED) - { - /* Interface is disconnected */ - return SLNETIF_STATUS_DISCONNECTED; - } - else if (connectionStatus > SLNETIF_STATUS_DISCONNECTED) - { - SLNETIF_NORMALIZE_RET_VAL(connectionStatus,SLNETIF_STATUS_CONNECTED); - } - else - { - SLNETIF_NORMALIZE_RET_VAL(connectionStatus,SLNETIF_ERR_IFGETCONNECTIONSTATUS_FAILED); - } - return connectionStatus; - } -} - - -//***************************************************************************** -// -// SlNetIf_loadSecObj - Load secured buffer to the network stack -// -//***************************************************************************** -int32_t SlNetIf_loadSecObj(uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen, uint32_t ifBitmap) -{ - SlNetIf_t *netIf; - int32_t retVal; - uint32_t ifIDIndex = 1; /* Set value to highest bit in uint32_t */ - uint32_t maxIDIndex = (uint32_t)1 << SLNETIF_MAX_IF; - - if ((NULL == objName) || (NULL == objBuff)) - { - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* bitmap 0 entered, load sec obj to all available interfaces */ - if (0 == ifBitmap) - { - ifBitmap = ~ifBitmap; - } - - while ( ifIDIndex < maxIDIndex ) - { - /* Check if ifIDIndex is a required ifID from the ifBitmap */ - if ( ifIDIndex & ifBitmap ) - { - /* Run validity check and find the requested interface */ - netIf = SlNetIf_getIfByID(ifIDIndex & ifBitmap); - - /* Check if the requested interface exists or the function - returned NULL */ - if ( (NULL != netIf) && (NULL != (netIf->ifConf)->ifLoadSecObj) ) - { - /* Interface exists, return interface IP address */ - retVal = (netIf->ifConf)->ifLoadSecObj(netIf->ifContext, objType, objName, objNameLen, objBuff, objBuffLen); - SLNETIF_NORMALIZE_RET_VAL(retVal,SLNETIF_ERR_IFLOADSECOBJ_FAILED); - - /* Check retVal for error codes */ - if (retVal < SLNETERR_RET_CODE_OK) - { - /* Return retVal, function error */ - return retVal; - } - else - { - /* Return success */ - return SLNETERR_RET_CODE_OK; - } - } - } - ifIDIndex <<= 1; - } - /* Interface doesn't exists or invalid input, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; -} diff --git a/ext/hal/ti/simplelink/source/ti/net/slnetif.h b/ext/hal/ti/simplelink/source/ti/net/slnetif.h deleted file mode 100644 index cb07c665bc2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/net/slnetif.h +++ /dev/null @@ -1,588 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -#ifndef __SL_NET_IF_H__ -#define __SL_NET_IF_H__ - -#include -#include - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup SlNetIf SlNetIf group - - \short Controls standard stack/interface options and capabilities - -*/ -/*! - \addtogroup SlNetIf - @{ -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -/* Interface ID bit pool to be used in interface add and in socket creation */ -#define SLNETIF_ID_1 (1 << 0) /**< Interface ID 1 */ -#define SLNETIF_ID_2 (1 << 1) /**< Interface ID 2 */ -#define SLNETIF_ID_3 (1 << 2) /**< Interface ID 3 */ -#define SLNETIF_ID_4 (1 << 3) /**< Interface ID 4 */ -#define SLNETIF_ID_5 (1 << 4) /**< Interface ID 5 */ -#define SLNETIF_ID_6 (1 << 5) /**< Interface ID 6 */ -#define SLNETIF_ID_7 (1 << 6) /**< Interface ID 7 */ -#define SLNETIF_ID_8 (1 << 7) /**< Interface ID 8 */ -#define SLNETIF_ID_9 (1 << 8) /**< Interface ID 9 */ -#define SLNETIF_ID_10 (1 << 9) /**< Interface ID 10 */ -#define SLNETIF_ID_11 (1 << 10) /**< Interface ID 11 */ -#define SLNETIF_ID_12 (1 << 11) /**< Interface ID 12 */ -#define SLNETIF_ID_13 (1 << 12) /**< Interface ID 13 */ -#define SLNETIF_ID_14 (1 << 13) /**< Interface ID 14 */ -#define SLNETIF_ID_15 (1 << 14) /**< Interface ID 15 */ -#define SLNETIF_ID_16 (1 << 15) /**< Interface ID 16 */ - -#define SLNETIF_MAX_IF (16) /**< Maximum interface */ - -/* this macro returns 0 when only one bit is set and a number when it isn't */ -#define ONLY_ONE_BIT_IS_SET(x) (((x > 0) && ((x & (x - 1)) == 0))?true:false) - - -/* Interface connection status bit pool to be used in set interface connection status function */ - -#define SLNETIF_STATUS_DISCONNECTED (0) -#define SLNETIF_STATUS_CONNECTED (1) - -/*! - \brief Interface state bit pool to be used in set interface state function -*/ -typedef enum -{ - SLNETIF_STATE_DISABLE = 0, - SLNETIF_STATE_ENABLE = 1 -} SlNetIfState_e; - -/*! - \brief Address type enum to be used in get ip address function -*/ -typedef enum -{ - SLNETIF_IPV4_ADDR = 0, - SLNETIF_IPV6_ADDR_LOCAL = 1, - SLNETIF_IPV6_ADDR_GLOBAL = 2 -} SlNetIfAddressType_e; - -/* Address config return values that can be retrieved in get ip address function */ -#define SLNETIF_ADDR_CFG_UNKNOWN (0) -#define SLNETIF_ADDR_CFG_DHCP (1) -#define SLNETIF_ADDR_CFG_DHCP_LLA (2) -#define SLNETIF_ADDR_CFG_STATIC (4) -#define SLNETIF_ADDR_CFG_STATELESS (5) -#define SLNETIF_ADDR_CFG_STATEFUL (6) - -/* Security object types for load Sec Obj function */ -#define SLNETIF_SEC_OBJ_TYPE_RSA_PRIVATE_KEY (1) -#define SLNETIF_SEC_OBJ_TYPE_CERTIFICATE (2) -#define SLNETIF_SEC_OBJ_TYPE_DH_KEY (3) - - -/*! - Check if interface state is enabled. - - \sa SlNetIf_queryIf() - */ -#define SLNETIF_QUERY_IF_STATE_BIT (1 << 0) -/*! - Check if interface connection status is connected. - - \sa SlNetIf_queryIf() - */ -#define SLNETIF_QUERY_IF_CONNECTION_STATUS_BIT (1 << 1) -/*! - Enable last partial match in an interface search, if no existing - interface matches the query completely. - - \sa SlNetIf_queryIf() - */ -#define SLNETIF_QUERY_IF_ALLOW_PARTIAL_MATCH_BIT (1 << 2) - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -/*! - \brief SlNetIf_Config_t structure contains all the function callbacks that are expected to be filled by the relevant network stack interface \n - Each interface has different capabilities, so not all the API's must be supported therefore an API's can be defined as: - - Mandatory API's - must be supported by the interface in order to be part of SlNetSock layer - - Non-Mandatory API's - can be supported, but not mandatory for basic SlNetSock proper operation - - \note Interface that is not supporting a non-mandatory API should set it to \b NULL in its function list - - \sa SlNetIf_Config_t -*/ -typedef struct SlNetIf_Config_t -{ - /* socket related API's */ - int16_t (*sockCreate) (void *ifContext, int16_t domain, int16_t type, int16_t protocol, void **sdContext); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_create */ - int32_t (*sockClose) (int16_t sd, void *sdContext); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_close */ - int32_t (*sockShutdown) (int16_t sd, void *sdContext, int16_t how); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_shutdown */ - int16_t (*sockAccept) (int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen, uint8_t flags, void **acceptedSdContext); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_accept */ - int32_t (*sockBind) (int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, int16_t addrlen); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_bind */ - int32_t (*sockListen) (int16_t sd, void *sdContext, int16_t backlog); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_listen */ - int32_t (*sockConnect) (int16_t sd, void *sdContext, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen, uint8_t flags); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_connect */ - int32_t (*sockGetPeerName) (int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_getPeerName */ - int32_t (*sockGetLocalName) (int16_t sd, void *sdContext, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_getSockName */ - int32_t (*sockSelect) (void *ifContext, int16_t nsds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_select */ - int32_t (*sockSetOpt) (int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_setOpt */ - int32_t (*sockGetOpt) (int16_t sd, void *sdContext, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_getOpt */ - int32_t (*sockRecv) (int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_recv */ - int32_t (*sockRecvFrom) (int16_t sd, void *sdContext, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_recvFrom */ - int32_t (*sockSend) (int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_send */ - int32_t (*sockSendTo) (int16_t sd, void *sdContext, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetSock_sendTo */ - int32_t (*sockstartSec) (int16_t sd, void *sdContext, SlNetSockSecAttrib_t *secAttrib, uint8_t flags); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetSock_startSec */ - - /* util related API's */ - int32_t (*utilGetHostByName) (void *ifContext, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetUtil_getHostByName */ - - /* if related API's */ - int32_t (*ifGetIPAddr) (void *ifContext, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetIf_getIPAddr */ - int32_t (*ifGetConnectionStatus) (void *ifContext); /*!< \b Mandatory API \n The actual implementation of the interface for ::SlNetIf_getConnectionStatus */ - int32_t (*ifLoadSecObj) (void *ifContext, uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetIf_loadSecObj */ - int32_t (*ifCreateContext) (uint16_t ifID, const char *ifName, void **ifContext); /*!< \b Non-Mandatory API \n The actual implementation of the interface for ::SlNetIf_add */ - -} SlNetIf_Config_t; - - -/*! - \brief The SlNetIf_t structure holds the configuration of the interface - Its ID, name, flags and the configuration list - ::SlNetIf_Config_t. -*/ -typedef struct SlNetIf_t -{ - uint32_t ifID; - char *ifName; - int32_t flags; - SlNetIf_Config_t *ifConf; - void *ifContext; -} SlNetIf_t; - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - - \brief Initialize the SlNetIf module - - \param[in] flags For future usage, - The value 0 may be used in order to run the - default flags - - \return Zero on success, or negative error code on failure - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetIf_init snippet -*/ -int32_t SlNetIf_init(int32_t flags); - -/*! - \brief Add a new SlNetIf-compatible interface to the system - - The SlNetIf_add function allows the application to add specific interfaces - with their priorities and function list.\n - This function gives full control to the application on the interfaces. - - \param[in] ifID Specifies the interface which needs - to be added.\n - The values of the interface identifier - is defined with the prefix SLNETIF_ID_ - which defined in slnetif.h - \param[in] ifName Specifies the name of the interface, - \b Note: Can be set to NULL, but when set to NULL - cannot be used with SlNetIf_getIDByName - \param[in] ifConf Specifies the function list for the - interface - \param[in] priority Specifies the priority needs to be - set (In ascending order). - Note: maximum priority is 15 - - \return Zero on success, or negative error code on failure - - \slnetif_not_threadsafe - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetIf_add wifi snippet - \snippet ti/net/test/snippets/slnetif.c SlNetIf_add NDK snippet - \snippet ti/net/test/snippets/slnetif.c SlNetIf_add NDKSec snippet -*/ -int32_t SlNetIf_add(uint16_t ifID, char *ifName, const SlNetIf_Config_t *ifConf, uint8_t priority); - - -/*! - \brief Get interface configuration from interface ID - - The SlNetIf_getIfByID function retrieves the configuration of the - requested interface. - - \param[in] ifID Specifies the interface which its configuration - needs to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - - \return A pointer to the configuration of the - interface on success, or NULL on failure - - \sa SlNetIf_add() - - \slnetif_not_threadsafe - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetIf_getIfByID snippet -*/ -SlNetIf_t * SlNetIf_getIfByID(uint16_t ifID); - - -/*! - \brief Query for the highest priority interface, given a list of - interfaces and properties. - - \param[in] ifBitmap The bit-wise OR of interfaces to be searched.\n - Note: Zero is currently not valid. - \param[in] queryBitmap The bit-wise OR of additional query criteria. - - \remarks @c queryBitmap can be set to : - - #SLNETIF_QUERY_IF_STATE_BIT - - #SLNETIF_QUERY_IF_CONNECTION_STATUS_BIT - - #SLNETIF_QUERY_IF_ALLOW_PARTIAL_MATCH_BIT - - \return A pointer to the configuration of a found - interface on success, or NULL on failure - - \sa SlNetIf_add() - \slnetif_not_threadsafe - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetIf_queryIf snippet -*/ -SlNetIf_t * SlNetIf_queryIf(uint32_t ifBitmap, uint32_t queryBitmap); - - -/*! - \brief Get interface Name from interface ID - - The SlNetIf_getNameByID function retrieves the name of the requested - interface. - - \param[in] ifID Specifies the interface which its name needs - to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - - \return A pointer to the name of the interface on - success, or NULL on failure - - \sa SlNetIf_add() - \sa SlNetIf_getIDByName() - - \slnetif_not_threadsafe - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetIf_getNameByID snippet -*/ -const char * SlNetIf_getNameByID(uint16_t ifID); - - -/*! - \brief Get interface ID from interface name - - The SlNetIf_getIDByName function retrieves the interface identifier of the - requested interface name. - - \param[in] ifName Specifies the interface which its interface - identifier needs to be retrieved.\n - - \return The interface identifier value of the interface - on success, or negative error code on failure - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - - \sa SlNetIf_add() - \sa SlNetIf_getNameByID() - \sa SlNetSock_getIfID() - - \note - Input NULL as ifName will return error code. - - When using more than one interface with the same - name, the ID of the highest priority interface - will be returned - \slnetif_not_threadsafe - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetIf_getIDByName snippet -*/ -int32_t SlNetIf_getIDByName(char *ifName); - - -/*! - \brief Get interface priority - - The SlNetIf_getPriority function retrieves the priority of the - interface. - - \param[in] ifID Specifies the interface which its priority - needs to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - - \return The priority value of the interface on success, - or negative error code on failure - - \sa SlNetIf_add() - \sa SlNetIf_setPriority() - - \slnetif_not_threadsafe - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetIf_getPriority snippet -*/ -int32_t SlNetIf_getPriority(uint16_t ifID); - - -/*! - \brief Set interface priority - - The SlNetIf_setPriority function sets new priority to the requested interface. - - \param[in] ifID Specifies the interface which its priority - needs to be changed.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - \param[in] priority Specifies the priority needs to be set. - (In ascending order) - Note: maximum priority is 15 - - \return Zero on success, or negative error code on - failure - - \sa SlNetIf_add() - \sa SlNetIf_getPriority() - - \slnetif_not_threadsafe - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetIf_setPriority snippet -*/ -int32_t SlNetIf_setPriority(uint16_t ifID, uint8_t priority); - - -/*! - \brief Set interface state - - Enable or disable the interface. - - \param[in] ifID Specifies the interface which its state - needs to be changed.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - \param[in] ifState Specifies the interface state.\n - The values of the interface state are defined - with the prefix SLNETIF_INTERFACE_ which - defined in slnetif.h - - \return Zero on success, or negative error code on - failure - - \sa SlNetIf_add() - \sa SlNetIf_getState() - - \slnetif_not_threadsafe - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetIf_setState snippet -*/ -int32_t SlNetIf_setState(uint16_t ifID, SlNetIfState_e ifState); - - -/*! - \brief Get interface state - - Obtain the current state of the interface. - - \param[in] ifID Specifies the interface which its state needs - to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - - \return State of the interface on success, or negative - error code on failure - - \sa SlNetIf_add() - \sa SlNetIf_setState() - - \slnetif_not_threadsafe - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetIf_getState snippet -*/ -int32_t SlNetIf_getState(uint16_t ifID); - - -/*! - \brief Get the connection status of an interface - - \param[in] ifID Interface ID - - \return @c SLNETIF_STATUS_ value on success, - or negative error code on failure - - \remark @c ifID should be a value with the @c SLNETIF_ID_ - prefix - - \sa SlNetIf_add() - \sa SLNETIF_STATUS_CONNECTED - \sa SLNETIF_STATUS_DISCONNECTED - - \slnetif_not_threadsafe - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetIf_getConnectionStatus snippet -*/ -int32_t SlNetIf_getConnectionStatus(uint16_t ifID); - - -/*! - \brief Get IP Address of specific interface - - The SlNetIf_getIPAddr function retrieve the IP address of a specific - interface according to the Address Type, IPv4, IPv6 LOCAL - or IPv6 GLOBAL. - - \param[in] ifID Specifies the interface which its connection - state needs to be retrieved.\n - The values of the interface identifier is - defined with the prefix SLNETIF_ID_ which - defined in slnetif.h - \param[in] addrType Address type: - - #SLNETIF_IPV4_ADDR - - #SLNETIF_IPV6_ADDR_LOCAL - - #SLNETIF_IPV6_ADDR_GLOBAL - \param[out] addrConfig Address config: - - #SLNETIF_ADDR_CFG_UNKNOWN - - #SLNETIF_ADDR_CFG_DHCP - - #SLNETIF_ADDR_CFG_DHCP_LLA - - #SLNETIF_ADDR_CFG_STATIC - - #SLNETIF_ADDR_CFG_STATELESS - - #SLNETIF_ADDR_CFG_STATEFUL - \param[out] ipAddr IP Address according to the Address Type - - \return Zero on success, or negative error code on failure - - \sa SlNetIfAddressType_e - - \slnetif_not_threadsafe - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetIf_getIPAddr snippet -*/ -int32_t SlNetIf_getIPAddr(uint16_t ifID, SlNetIfAddressType_e addrType, uint16_t *addrConfig, uint32_t *ipAddr); - - -/*! - \brief Load secured buffer to the network stack - - The SlNetSock_secLoadObj function loads buffer/files into the inputted - network stack for future usage of the socket SSL/TLS connection. - This option is relevant for network stacks with file system and also for - network stacks that lack file system that can store the secured files. - - \param[in] objType Specifies the security object type which - could be one of the following:\n - - #SLNETIF_SEC_OBJ_TYPE_RSA_PRIVATE_KEY - - #SLNETIF_SEC_OBJ_TYPE_CERTIFICATE - - #SLNETIF_SEC_OBJ_TYPE_DH_KEY - \param[in] objName Specifies the name/input identifier of the - secured buffer loaded - for file systems - this can be the file name - for plain text buffer loading this can be the - name of the object - \param[in] objNameLen Specifies the buffer name length to be loaded.\n - \param[in] objBuff Specifies the pointer to the secured buffer to - be loaded.\n - \param[in] objBuffLen Specifies the buffer length to be loaded.\n - \param[in] ifBitmap Specifies the interfaces which the security - objects needs to be added to.\n - The values of the interface identifiers - is defined with the prefix SLNETIF_ID_ - which defined in slnetif.h - - \return On success, buffer type handler index to be - used when attaching the secured buffer to a - socket.\n - A successful return code should be a positive - number (int16)\n - On error, a negative value will be returned - specifying the error code. - - #SLNETERR_STATUS_ERROR - load operation failed - - \sa SlNetSock_setOpt() - - \slnetif_not_threadsafe - -*/ -int32_t SlNetIf_loadSecObj(uint16_t objType, char *objName, int16_t objNameLen, uint8_t *objBuff, int16_t objBuffLen, uint32_t ifBitmap); - -/*! - - Close the Doxygen group. - @} - -*/ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __SL_NET_IF_H__ */ diff --git a/ext/hal/ti/simplelink/source/ti/net/slnetsock.c b/ext/hal/ti/simplelink/source/ti/net/slnetsock.c deleted file mode 100644 index 885ce72b824..00000000000 --- a/ext/hal/ti/simplelink/source/ti/net/slnetsock.c +++ /dev/null @@ -1,1514 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/* POSIX Header files */ -#include - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -#define SLNETSOCK_NORMALIZE_NEEDED 0 -#if SLNETSOCK_NORMALIZE_NEEDED - #define SLNETSOCK_NORMALIZE_RET_VAL(retVal,err) ((retVal < 0)?(retVal = err):(retVal)) -#else - #define SLNETSOCK_NORMALIZE_RET_VAL(retVal,err) -#endif - -#define SLNETSOCK_IPV4_ADDR_LEN (4) -#define SLNETSOCK_IPV6_ADDR_LEN (16) - -#define SLNETSOCK_SIZEOF_ONE_SDSETBITMAP_SLOT_IN_BITS (sizeof(uint32_t)*8) - -#define SLNETSOCK_LOCK() pthread_mutex_lock(&VirtualSocketMutex) // forever -#define SLNETSOCK_UNLOCK() pthread_mutex_unlock(&VirtualSocketMutex) - -#define ENABLE_DEFAULT_QUERY_FLAGS() (SLNETSOCK_CREATE_IF_STATE_ENABLE | SLNETSOCK_CREATE_IF_STATUS_CONNECTED | SLNETSOCK_CREATE_ALLOW_PARTIAL_MATCH) -#define GET_QUERY_FLAGS(flags) (flags & (SLNETSOCK_CREATE_IF_STATE_ENABLE | SLNETSOCK_CREATE_IF_STATUS_CONNECTED | SLNETSOCK_CREATE_ALLOW_PARTIAL_MATCH)) - -/* Macro which merge the 8bit security flags to the upper bits of the 32 bit - input flags */ -#define MERGE_SEC_INTO_INPUT_FLAGS(inputFlags, secFlags) (inputFlags |= (secFlags << 24)) - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - - -/* Socket Endpoint */ -typedef struct SlNetSock_VirtualSocket_t -{ - int16_t realSd; - uint8_t sdFlags; - void *sdContext; - SlNetIf_t *netIf; -} SlNetSock_VirtualSocket_t; - -/* Structure which holds the realSd and the virtualSd indexes */ -typedef struct SlNetSock_RealToVirtualIndexes_t -{ - int16_t realSd; - int16_t virtualSd; - struct SlNetSock_RealToVirtualIndexes_t *next; -} SlNetSock_RealToVirtualIndexes_t; - -/*****************************************************************************/ -/* Global declarations */ -/*****************************************************************************/ - -static SlNetSock_VirtualSocket_t *VirtualSockets[SLNETSOCK_MAX_CONCURRENT_SOCKETS]; - -/* Variable That is true when the SlNetSock layer is initialized (Mutex - created and VirtualSockets array initialized) and false when the layer - isn't initialized. */ -static uint8_t SlNetSock_Initialized = false; - -/* Lock Object to secure access to the Virtual Sockets array */ -static pthread_mutex_t VirtualSocketMutex; - - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -static int32_t SlNetSock_getVirtualSdConf(int16_t virtualSdIndex, int16_t *realSd, uint8_t *sdFlags, void **sdContext, SlNetIf_t **netIf); -static int32_t SlNetSock_AllocVirtualSocket(int16_t *virtualSdIndex, SlNetSock_VirtualSocket_t **newSocketNode); -static int32_t SlNetSock_freeVirtualSocket(int16_t virtualSdIndex); - -//***************************************************************************** -// -// SlNetSock_getVirtualSdConf - This function search and returns the -// configuration of virtual socket. -// -//***************************************************************************** -static int32_t SlNetSock_getVirtualSdConf(int16_t virtualSdIndex, int16_t *realSd, uint8_t *sdFlags, void **sdContext, SlNetIf_t **netIf) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - - /* Check if the SlNetSock layer initialized, means that the mutex exists */ - if (false == SlNetSock_Initialized) - { - return SLNETERR_RET_CODE_MUTEX_CREATION_FAILED; - } - - SLNETSOCK_LOCK(); - - /* Check if the input is valid and if real socket descriptor exists */ - if ( (virtualSdIndex >= SLNETSOCK_MAX_CONCURRENT_SOCKETS) || (virtualSdIndex < 0) || (NULL == netIf) ) - { - retVal = SLNETERR_RET_CODE_INVALID_INPUT; - } - else if (NULL == VirtualSockets[virtualSdIndex]) - { - /* Socket was not found, return error code */ - retVal = SLNETERR_RET_CODE_COULDNT_FIND_RESOURCE; - } - else - { - /* Socket found, copy and return its content */ - *netIf = VirtualSockets[virtualSdIndex]->netIf; - *realSd = VirtualSockets[virtualSdIndex]->realSd; - - /* If sdContext pointer supplied, copy into it the sdContext of the - socket */ - if ( NULL != sdContext ) - { - *sdContext = VirtualSockets[virtualSdIndex]->sdContext; - } - - /* If sdFlags pointer supplied, copy into it the sdFlags of the - socket */ - if ( NULL != sdFlags ) - { - *sdFlags = VirtualSockets[virtualSdIndex]->sdFlags; - } - - /* Check if the interface of the socket is declared */ - if ( (NULL == (*netIf)) || (NULL == (*netIf)->ifConf) ) - { - /* Interface was not found or config list is missing, - return error code */ - retVal = SLNETERR_RET_CODE_SOCKET_CREATION_IN_PROGRESS; - } - } - - SLNETSOCK_UNLOCK(); - - return retVal; -} - -//***************************************************************************** -// -// SlNetSock_AllocVirtualSocket - Search for free space in the VirtualSockets -// array and allocate a socket in this location -// -//***************************************************************************** -static int32_t SlNetSock_AllocVirtualSocket(int16_t *virtualSdIndex, SlNetSock_VirtualSocket_t **newSocketNode) -{ - uint16_t arrayIndex = 0; - int32_t retVal = SLNETERR_RET_CODE_NO_FREE_SPACE; - - /* Check if the SlNetSock layer initialized, means that the mutex exists */ - if (false == SlNetSock_Initialized) - { - return SLNETERR_RET_CODE_MUTEX_CREATION_FAILED; - } - - SLNETSOCK_LOCK(); - - /* Search for free space in the VirtualSockets array */ - while ( arrayIndex < SLNETSOCK_MAX_CONCURRENT_SOCKETS ) - { - /* Check if the arrayIndex in VirtualSockets is free */ - if ( NULL == VirtualSockets[arrayIndex] ) - { - /* Allocate memory for new socket node for the socket list */ - *newSocketNode = (SlNetSock_VirtualSocket_t *)calloc(1, sizeof(SlNetSock_VirtualSocket_t)); - - /* Check if the memory allocated successfully */ - if (NULL == *newSocketNode) - { - /* Allocation failed, return error code */ - retVal = SLNETERR_RET_CODE_MALLOC_ERROR; - break; - } - else - { - /* Location free, return the Index and function success */ - *virtualSdIndex = arrayIndex; - - VirtualSockets[arrayIndex] = *newSocketNode; - - retVal = SLNETERR_RET_CODE_OK; - break; - } - } - else - { - /* Location isn't free, continue to next location */ - arrayIndex++; - } - } - - SLNETSOCK_UNLOCK(); - - return retVal; -} - -//***************************************************************************** -// -// SlNetSock_freeVirtualSocket - free allocated socket and initialize the array -// in the virtual socket location -// -//***************************************************************************** -static int32_t SlNetSock_freeVirtualSocket(int16_t virtualSdIndex) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - - /* Check if the SlNetSock layer initialized, means that the mutex exists */ - if (false == SlNetSock_Initialized) - { - return SLNETERR_RET_CODE_MUTEX_CREATION_FAILED; - } - - SLNETSOCK_LOCK(); - - /* Check if the input is valid and if real socket descriptor exists */ - if ( (virtualSdIndex >= SLNETSOCK_MAX_CONCURRENT_SOCKETS) || (virtualSdIndex < 0) ) - { - retVal = SLNETERR_RET_CODE_INVALID_INPUT; - } - else if (NULL == VirtualSockets[virtualSdIndex]) - { - /* Socket was not found, return error code */ - retVal = SLNETERR_RET_CODE_COULDNT_FIND_RESOURCE; - } - else - { - /* Free Socket Context allocated memory */ - if (NULL != VirtualSockets[virtualSdIndex]->sdContext) - { - free((void *)VirtualSockets[virtualSdIndex]->sdContext); - } - - /* Free Socket Node allocated memory and delete it from the - VirtualSockets array */ - free((void *)VirtualSockets[virtualSdIndex]); - - VirtualSockets[virtualSdIndex] = NULL; - } - - SLNETSOCK_UNLOCK(); - - return retVal; -} - -//***************************************************************************** -// -// SlNetSock_init - init the SlNetSock module -// -//***************************************************************************** -int32_t SlNetSock_init(int32_t flags) -{ - int16_t Index = SLNETSOCK_MAX_CONCURRENT_SOCKETS; - int32_t retVal; - - /* If the SlNetSock layer isn't initialized, initialize it */ - if (false == SlNetSock_Initialized) - { - /* Setup the mutex operations */ - retVal = pthread_mutex_init(&VirtualSocketMutex, (const pthread_mutexattr_t *)NULL); - if (0 != retVal) - { - return SLNETERR_RET_CODE_MUTEX_CREATION_FAILED; - } - else - { - /* Initialize the VirtualSockets array */ - while (Index--) - { - VirtualSockets[Index] = NULL; - } - SlNetSock_Initialized = true; - } - } - return SLNETERR_RET_CODE_OK; -} - - -//***************************************************************************** -// -// SlNetSock_create - Create an endpoint for communication -// -//***************************************************************************** -int16_t SlNetSock_create(int16_t domain, int16_t type, int16_t protocol, uint32_t ifBitmap, int16_t flags) -{ - SlNetIf_t *netIf; - SlNetSock_VirtualSocket_t *sdNode; - int16_t socketIndex; - int16_t createdSd; - int16_t queryFlags; - int32_t retVal; - - - /* if flags is zero, enable the default bits */ - if (0 == flags) - { - queryFlags = ENABLE_DEFAULT_QUERY_FLAGS(); - } - else - { - queryFlags = GET_QUERY_FLAGS(flags); - } - - /* Search for free place in the array */ - retVal = SlNetSock_AllocVirtualSocket(&socketIndex, &sdNode); - - /* Before creating a socket, check if there is a free place in the array */ - if ( retVal < SLNETERR_RET_CODE_OK ) - { - /* There isn't a free space in the array, return error code */ - return retVal; - } - - if (protocol == 0) { - switch (type) { - case SLNETSOCK_SOCK_STREAM: - protocol = SLNETSOCK_PROTO_TCP; - break; - case SLNETSOCK_SOCK_DGRAM: - protocol = SLNETSOCK_PROTO_UDP; - break; - case SLNETSOCK_SOCK_RAW: - default: - /* Keep protocol as is for other types */ - break; - } - } - - /* When ifBitmap is 0, that means automatic selection of all interfaces - is required, enable all bits in ifBitmap */ - if (0 == ifBitmap) - { - ifBitmap = ~ifBitmap; - } - - /* This loop tries to create a socket on the required interface with the - required queryFlags. - When multiple interfaces, in addition to the queryFlags it will try - to create the socket on the interface with the highest priority */ - while ( ifBitmap > 0 ) - { - /* Search for the highest priority interface according to the - ifBitmap and the queryFlags */ - netIf = SlNetIf_queryIf(ifBitmap, queryFlags); - - /* Check if the function returned NULL or the requested interface - exists */ - if (NULL == netIf) - { - /* Free the captured VirtualSockets location */ - SlNetSock_freeVirtualSocket(socketIndex); - - /* Interface doesn't exists, save error code */ - return retVal; - } - else - { - - /* Disable the ifID bit from the ifBitmap after finding the - netIf */ - ifBitmap &= ~(netIf->ifID); - - /* Interface exists, try to create new socket */ - createdSd = (netIf->ifConf)->sockCreate(netIf->ifContext, domain, type, protocol, &(sdNode->sdContext)); - - /* Check createdSd for error codes */ - if (createdSd < 0) - { - /* sockCreate failed, continue to the next ifID */ - retVal = createdSd; - } - else - { - /* Real socket created, fill the allocated socket node */ - sdNode->realSd = createdSd; - sdNode->netIf = netIf; - - /* Socket created, allocated and connected to the - VirtualSockets array, return VirtualSockets index */ - return socketIndex; - } - } - } - - /* Free the captured VirtualSockets location */ - SlNetSock_freeVirtualSocket(socketIndex); - - /* There isn't a free space in the array or socket couldn't be opened, - return error code */ - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_close - Gracefully close socket -// -//***************************************************************************** -int32_t SlNetSock_close(int16_t sd) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, NULL, &sdContext, &netIf); - - /* Check if sd found */ - if (SLNETERR_RET_CODE_OK != retVal) - { - /* Validation failed, return error code */ - return retVal; - } - - /* Function exists in the interface of the socket descriptor, dispatch - the Close command */ - retVal = (netIf->ifConf)->sockClose(realSd, sdContext); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKCLOSE_FAILED); - - if (retVal == SLNETERR_RET_CODE_OK) - { - /* When freeing the virtual socket, it will free allocated memory - of the sdContext and of the socket node, if other threads will - try to use this socket or the retrieved data of the socket the - stack needs to return an error */ - SlNetSock_freeVirtualSocket(sd); - } - return retVal; - - -} - - -//***************************************************************************** -// -// SlNetSock_shutdown - Shutting down parts of a full-duplex connection -// -//***************************************************************************** -int32_t SlNetSock_shutdown(int16_t sd, int16_t how) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, NULL, &sdContext, &netIf); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if (NULL == (netIf->ifConf)->sockShutdown) - { - /* Non mandatory function doesn't exists, return error code */ - return SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN; - } - - /* Function exists in the interface of the socket descriptor, dispatch - the Shutdown command */ - retVal = (netIf->ifConf)->sockShutdown(realSd, sdContext, how); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKSHUTDOWN_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_accept - Accept a connection on a socket -// -//***************************************************************************** -int16_t SlNetSock_accept(int16_t sd, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen) -{ - SlNetSock_VirtualSocket_t *allocSdNode; - void *sdContext; - int16_t realSd; - int16_t socketIndex; - int32_t retVal = SLNETERR_RET_CODE_OK; - - /* Search for free place in the array */ - retVal = SlNetSock_AllocVirtualSocket(&socketIndex, &allocSdNode); - - /* Before creating a socket, check if there is a free place in the array */ - if ( retVal < SLNETERR_RET_CODE_OK ) - { - /* There isn't a free space in the array, return error code */ - return retVal; - } - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, &(allocSdNode->sdFlags), &sdContext, &(allocSdNode->netIf)); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if (NULL == ((allocSdNode->netIf)->ifConf)->sockAccept) - { - /* Free the captured VirtualSockets location */ - SlNetSock_freeVirtualSocket(socketIndex); - - /* Validation failed, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* Function exists in the interface of the socket descriptor, dispatch - the Accept command */ - retVal = ((allocSdNode->netIf)->ifConf)->sockAccept(realSd, sdContext, addr, addrlen, allocSdNode->sdFlags, &(allocSdNode->sdContext)); - - /* Check retVal for error codes */ - if (retVal < SLNETERR_RET_CODE_OK) - { - /* Free the captured VirtualSockets location */ - SlNetSock_freeVirtualSocket(socketIndex); - - /* sockAccept failed, return error code */ - return retVal; - } - else - { - /* Real socket created, fill the allocated socket node */ - allocSdNode->realSd = retVal; - - /* Socket created, allocated and connected to the - VirtualSockets array, return VirtualSockets index */ - return socketIndex; - } - -} - - -//***************************************************************************** -// -// SlNetSock_bind - Assign a name to a socket -// -//***************************************************************************** -int32_t SlNetSock_bind(int16_t sd, const SlNetSock_Addr_t *addr, int16_t addrlen) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, NULL, &sdContext, &netIf); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if (NULL == (netIf->ifConf)->sockBind) - { - /* Non mandatory function doesn't exists, return error code */ - return SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN; - } - - /* Function exists in the interface of the socket descriptor, dispatch - the Bind command */ - retVal = (netIf->ifConf)->sockBind(realSd, sdContext, addr, addrlen); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKBIND_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_listen - Listen for connections on a socket -// -//***************************************************************************** -int32_t SlNetSock_listen(int16_t sd, int16_t backlog) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, NULL, &sdContext, &netIf); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if (NULL == (netIf->ifConf)->sockListen) - { - /* Non mandatory function doesn't exists, return error code */ - return SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN; - } - - /* Function exists in the interface of the socket descriptor, dispatch - the Listen command */ - retVal = (netIf->ifConf)->sockListen(realSd, sdContext, backlog); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKLISTEN_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_connect - Initiate a connection on a socket -// -//***************************************************************************** -int32_t SlNetSock_connect(int16_t sd, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - uint8_t sdFlags; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, &sdFlags, &sdContext, &netIf); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if (NULL == (netIf->ifConf)->sockConnect) - { - /* Non mandatory function doesn't exists, return error code */ - return SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN; - } - - /* Function exists in the interface of the socket descriptor, dispatch - the Connect command */ - retVal = (netIf->ifConf)->sockConnect(realSd, sdContext, addr, addrlen, sdFlags); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKCONNECT_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_connectUrl - Initiate a connection on a socket by URL -// -//***************************************************************************** -int32_t SlNetSock_connectUrl(int16_t sd, const char *url) -{ - uint32_t addr[4]; - uint16_t ipAddrLen; - SlNetSock_AddrIn_t localAddr; //address of the server to connect to - SlNetSocklen_t localAddrSize; - int16_t realSd; - uint8_t sdFlags; - SlNetIf_t *netIf; - void *sdContext; - int32_t retVal = SLNETERR_RET_CODE_OK; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, &sdFlags, &sdContext, &netIf); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if ( (NULL == (netIf->ifConf)->sockConnect) || (NULL == (netIf->ifConf)->utilGetHostByName) ) - { - /* Non mandatory function doesn't exists, return error code */ - return SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN; - } - - /* Query DNS for IPv4 address. */ - retVal = (netIf->ifConf)->utilGetHostByName(netIf->ifContext, (char *)url, strlen(url), addr, &ipAddrLen, SLNETSOCK_AF_INET); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETUTIL_ERR_UTILGETHOSTBYNAME_FAILED); - if(retVal < 0) - { - /* If call fails, try again for IPv6. */ - retVal = (netIf->ifConf)->utilGetHostByName(netIf->ifContext, (char *)url, strlen(url), addr, &ipAddrLen, SLNETSOCK_AF_INET6); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETUTIL_ERR_UTILGETHOSTBYNAME_FAILED); - if(retVal < 0) - { - /* if the request failed twice, return error code. */ - return retVal; - } - else - { - /* fill the answer fields with IPv6 parameters */ - localAddr.sin_family = SLNETSOCK_AF_INET6; - localAddrSize = sizeof(SlNetSock_AddrIn6_t); - } - } - else - { - /* fill the answer fields with IPv4 parameters */ - localAddr.sin_family = SLNETSOCK_AF_INET; - localAddrSize = sizeof(SlNetSock_AddrIn_t); - - /* convert the IPv4 address from host byte order to network byte - order */ - localAddr.sin_addr.s_addr = SlNetUtil_htonl(addr[0]); - } - - - /* Function exists in the interface of the socket descriptor, dispatch - the Connect command */ - retVal = (netIf->ifConf)->sockConnect(realSd, sdContext, (const SlNetSock_Addr_t *)&localAddr, localAddrSize, sdFlags); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKCONNECT_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_getPeerName - Return address info about the remote side of the -// connection -// -//***************************************************************************** -int32_t SlNetSock_getPeerName(int16_t sd, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, NULL, &sdContext, &netIf); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if (NULL == (netIf->ifConf)->sockGetPeerName) - { - /* Non mandatory function doesn't exists, return error code */ - return SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN; - } - - /* Function exists in the interface of the socket descriptor, dispatch - the GetPeerName command */ - retVal = (netIf->ifConf)->sockGetPeerName(realSd, sdContext, addr, addrlen); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKGETPEERNAME_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_getSockName - Returns the local address info of the socket -// descriptor -// -//***************************************************************************** -int32_t SlNetSock_getSockName(int16_t sd, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, NULL, &sdContext, &netIf); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if (NULL == (netIf->ifConf)->sockGetLocalName) - { - /* Non mandatory function doesn't exists, return error code */ - return SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN; - } - - /* Function exists in the interface of the socket descriptor, dispatch - the GetLocalName command */ - retVal = (netIf->ifConf)->sockGetLocalName(realSd, sdContext, addr, addrlen); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKGETLOCALNAME_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_select - Monitor socket activity -// -//***************************************************************************** -int32_t SlNetSock_select(int16_t nsds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int32_t sdIndex = 0; - int16_t realSd; - int16_t ifNsds = 0; - bool skipToNext = true; - SlNetIf_t *firstIfID = NULL; - SlNetIf_t *netIf; - void *sdContext; - SlNetSock_SdSet_t ifReadsds; - SlNetSock_SdSet_t ifWritesds; - SlNetSock_SdSet_t ifExceptsds; - SlNetSock_RealToVirtualIndexes_t *tempNode = NULL; - SlNetSock_RealToVirtualIndexes_t *realSdToVirtual = NULL; - - /* Initialize sds parameters */ - SlNetSock_sdsClrAll(&ifReadsds); - SlNetSock_sdsClrAll(&ifWritesds); - SlNetSock_sdsClrAll(&ifExceptsds); - - /* Run over all possible sd indexes */ - while ( sdIndex < nsds ) - { - /* get interface ID from the socket identifier */ - retVal = SlNetSock_getVirtualSdConf(sdIndex, &realSd, NULL, &sdContext, &netIf); - - /* Check if sd found */ - if (SLNETERR_RET_CODE_OK == retVal) - { - /* Check if sdIndex is set in read/write/except virtual sd sets, - if so, set the real sd set and set skipToNext to false - for further use */ - if (SlNetSock_sdsIsSet(sdIndex, readsds) == 1) - { - SlNetSock_sdsSet(realSd, &ifReadsds); - skipToNext = false; - } - if (SlNetSock_sdsIsSet(sdIndex, writesds) == 1) - { - SlNetSock_sdsSet(realSd, &ifWritesds); - skipToNext = false; - } - if (SlNetSock_sdsIsSet(sdIndex, exceptsds) == 1) - { - SlNetSock_sdsSet(realSd, &ifExceptsds); - skipToNext = false; - } - - if (false == skipToNext) - { - - /* Create a node which stores the relation between the virtual - sd index and the real sd index and connect it to the list */ - tempNode = (SlNetSock_RealToVirtualIndexes_t *)malloc(sizeof(SlNetSock_RealToVirtualIndexes_t)); - - /* Check if the malloc function failed */ - if (NULL == tempNode) - { - firstIfID = NULL; - retVal = SLNETERR_RET_CODE_MALLOC_ERROR; - break; - } - - tempNode->realSd = realSd; - tempNode->virtualSd = sdIndex; - tempNode->next = realSdToVirtual; - realSdToVirtual = tempNode; - - /* Check if the stored interface ID is different from the - interface ID of the socket */ - if (netIf != firstIfID) - { - /* Check if the stored interface ID is still initialized */ - if (NULL == firstIfID) - { - /* Store the interface ID */ - firstIfID = netIf; - } - else - { - /* Different interface ID from the stored interface - ID, that means more than one interface supplied - in the read sd set */ - firstIfID = NULL; - break; - } - } - if (ifNsds <= realSd) - { - ifNsds = realSd + 1; - } - skipToNext = true; - } - } - - /* Continue to next sd index */ - sdIndex++; - } - - /* Check if non mandatory function exists */ - if ( (NULL != firstIfID) && (NULL != (firstIfID->ifConf)->sockSelect) ) - { - /* Function exists in the interface of the socket descriptor, - dispatch the Select command */ - retVal = (firstIfID->ifConf)->sockSelect(firstIfID->ifContext, ifNsds, &ifReadsds, &ifWritesds, &ifExceptsds, timeout); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKSELECT_FAILED); - - /* Clear all virtual sd sets before setting the sockets that are set */ - SlNetSock_sdsClrAll(readsds); - SlNetSock_sdsClrAll(writesds); - SlNetSock_sdsClrAll(exceptsds); - - /* check if the sockselect returned positive value, this value - represents how many socket descriptors are set */ - if (retVal > 0) - { - /* Run over all the socket descriptors in the list and check if - the sockSelect function set them, if so, set the virtual - socket descriptors sets */ - tempNode = realSdToVirtual; - while ( NULL != tempNode ) - { - if (SlNetSock_sdsIsSet(tempNode->realSd, &ifReadsds) == 1) - { - SlNetSock_sdsSet(tempNode->virtualSd, readsds); - } - if (SlNetSock_sdsIsSet(tempNode->realSd, &ifWritesds) == 1) - { - SlNetSock_sdsSet(tempNode->virtualSd, writesds); - } - if (SlNetSock_sdsIsSet(tempNode->realSd, &ifExceptsds) == 1) - { - SlNetSock_sdsSet(tempNode->virtualSd, exceptsds); - } - tempNode = tempNode->next; - } - } - } - else - { - if ( SLNETERR_RET_CODE_MALLOC_ERROR != retVal ) - { - /* Validation failed, return error code */ - retVal = SLNETERR_RET_CODE_INVALID_INPUT; - } - } - - /* List isn't needed anymore, free it from the head of the list */ - while (NULL != realSdToVirtual) - { - tempNode = realSdToVirtual->next; - free(realSdToVirtual); - realSdToVirtual = tempNode; - } - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_sdsSet - SlNetSock_select's SlNetSock_SdSet_t SET function -// -//***************************************************************************** -int32_t SlNetSock_sdsSet(int16_t sd, SlNetSock_SdSet_t *sdset) -{ - int sdArrayIndex; - - /* Validation check */ - if ( (NULL == sdset) || (sd >= SLNETSOCK_MAX_CONCURRENT_SOCKETS) ) - { - /* Validation failed, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* Check in which sdset index the input socket exists */ - sdArrayIndex = (sd / SLNETSOCK_SIZEOF_ONE_SDSETBITMAP_SLOT_IN_BITS); - - /* Set the socket in the sd set */ - sdset->sdSetBitmap[sdArrayIndex] |= ( 1 << (sd % SLNETSOCK_SIZEOF_ONE_SDSETBITMAP_SLOT_IN_BITS) ); - - return SLNETERR_RET_CODE_OK; - -} - - -//***************************************************************************** -// -// SlNetSock_sdsClr - SlNetSock_select's SlNetSock_SdSet_t CLR function -// -//***************************************************************************** -int32_t SlNetSock_sdsClr(int16_t sd, SlNetSock_SdSet_t *sdset) -{ - int sdArrayIndex; - - /* Validation check */ - if ( (NULL == sdset) || (sd >= SLNETSOCK_MAX_CONCURRENT_SOCKETS) ) - { - /* Validation failed, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - /* Check in which sdset index the input socket exists */ - sdArrayIndex = (sd / SLNETSOCK_SIZEOF_ONE_SDSETBITMAP_SLOT_IN_BITS); - - /* Set the socket in the sd set */ - sdset->sdSetBitmap[sdArrayIndex] &= ~( 1 << (sd % SLNETSOCK_SIZEOF_ONE_SDSETBITMAP_SLOT_IN_BITS) ); - - return SLNETERR_RET_CODE_OK; -} - - -//***************************************************************************** -// -// SlNetSock_sdsClrAll - SlNetSock_select's SlNetSock_SdSet_t ZERO function -// -//***************************************************************************** -int32_t SlNetSock_sdsClrAll(SlNetSock_SdSet_t *sdset) -{ - int sdArrayIndex; - - /* Validation check */ - if (NULL == sdset) - { - /* Validation failed, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* Check the size of the sdArrayIndex */ - sdArrayIndex = (((sizeof(sdset)*8)-1) / SLNETSOCK_SIZEOF_ONE_SDSETBITMAP_SLOT_IN_BITS); - - while (sdArrayIndex >= 0) - { - /* Set to 0 the sd set */ - sdset->sdSetBitmap[sdArrayIndex] = 0; - sdArrayIndex --; - } - - return SLNETERR_RET_CODE_OK; -} - - - -//***************************************************************************** -// -// SlNetSock_sdsIsSet - SlNetSock_select's SlNetSock_SdSet_t ISSET function -// -//***************************************************************************** -int32_t SlNetSock_sdsIsSet(int16_t sd, SlNetSock_SdSet_t *sdset) -{ - int sdArrayIndex; - - /* Validation check */ - if ( (NULL == sdset) || (sd >= SLNETSOCK_MAX_CONCURRENT_SOCKETS) ) - { - /* Validation failed, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* Check in which sdset index the input socket exists */ - sdArrayIndex = (sd / SLNETSOCK_SIZEOF_ONE_SDSETBITMAP_SLOT_IN_BITS); - - /* Check if the sd is set in the sdSetBitmap */ - if ( (sdset->sdSetBitmap[sdArrayIndex]) & (1 << (sd % SLNETSOCK_SIZEOF_ONE_SDSETBITMAP_SLOT_IN_BITS)) ) - { - /* Bit is set, return 1 */ - return 1; - } - else - { - /* Bit is not set, return 0 */ - return 0; - } -} - - -//***************************************************************************** -// -// SlNetSock_setOpt - Set socket options -// -//***************************************************************************** -int32_t SlNetSock_setOpt(int16_t sd, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, NULL, &sdContext, &netIf); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if (NULL == (netIf->ifConf)->sockSetOpt) - { - /* Non mandatory function doesn't exists, return error code */ - return SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN; - } - - /* Function exists in the interface of the socket descriptor, dispatch - the SetOpt command */ - retVal = (netIf->ifConf)->sockSetOpt(realSd, sdContext, level, optname, optval, optlen); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKSETOPT_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_getOpt - Get socket options -// -//***************************************************************************** -int32_t SlNetSock_getOpt(int16_t sd, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, NULL, &sdContext, &netIf); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if (NULL == (netIf->ifConf)->sockGetOpt) - { - /* Non mandatory function doesn't exists, return error code */ - return SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN; - } - - /* Function exists in the interface of the socket descriptor, dispatch - the GetOpt command */ - retVal = (netIf->ifConf)->sockGetOpt(realSd, sdContext, level, optname, optval, optlen); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKGETOPT_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_recv - Read data from TCP socket -// -//***************************************************************************** -int32_t SlNetSock_recv(int16_t sd, void *buf, uint32_t len, uint32_t flags) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - uint8_t sdFlags; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, &sdFlags, &sdContext, &netIf); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if (NULL == (netIf->ifConf)->sockRecv) - { - /* Non mandatory function doesn't exists, return error code */ - return SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN; - } - if ((flags & 0xff000000) != 0) - { - /* invalid user flags */ - return SLNETERR_BSD_EOPNOTSUPP; - } - - /* Macro which merge the 8bit security flags to the upper bits of the - 32bit input flags */ - MERGE_SEC_INTO_INPUT_FLAGS(flags, sdFlags); - - /* Function exists in the interface of the socket descriptor, dispatch - the Recv command */ - retVal = (netIf->ifConf)->sockRecv(realSd, sdContext, buf, len, flags); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKRECV_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_recvFrom - Read data from socket -// -//***************************************************************************** -int32_t SlNetSock_recvFrom(int16_t sd, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - uint8_t sdFlags; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, &sdFlags, &sdContext, &netIf); - - /* Check if sd found */ - if (SLNETERR_RET_CODE_OK != retVal) - { - /* Validation failed, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - if ((flags & 0xff000000) != 0) - { - /* invalid user flags */ - return SLNETERR_BSD_EOPNOTSUPP; - } - - /* Macro which merge the 8bit security flags to the upper bits of the - 32bit input flags */ - MERGE_SEC_INTO_INPUT_FLAGS(flags, sdFlags); - - /* Function exists in the interface of the socket descriptor, dispatch - the RecvFrom command */ - retVal = (netIf->ifConf)->sockRecvFrom(realSd, sdContext, buf, len, flags, from, fromlen); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKRECVFROM_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_send - Write data to TCP socket -// -//***************************************************************************** -int32_t SlNetSock_send(int16_t sd, const void *buf, uint32_t len, uint32_t flags) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - uint8_t sdFlags; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, &sdFlags, &sdContext, &netIf); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if (NULL == (netIf->ifConf)->sockSend) - { - /* Non mandatory function doesn't exists, return error code */ - return SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN; - } - if ((flags & 0xff000000) != 0) - { - /* invalid user flags */ - return SLNETERR_BSD_EOPNOTSUPP; - } - - /* Macro which merge the 8bit security flags to the upper bits of the - 32bit input flags */ - MERGE_SEC_INTO_INPUT_FLAGS(flags, sdFlags); - - /* Function exists in the interface of the socket descriptor, dispatch - the Send command */ - retVal = (netIf->ifConf)->sockSend(realSd, sdContext, buf, len, flags); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKSEND_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_sendTo - Write data to socket -// -//***************************************************************************** -int32_t SlNetSock_sendTo(int16_t sd, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - uint8_t sdFlags; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, &sdFlags, &sdContext, &netIf); - - /* Check if sd found */ - if (SLNETERR_RET_CODE_OK != retVal) - { - /* Validation failed, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - if ((flags & 0xff000000) != 0) - { - /* invalid user flags */ - return SLNETERR_BSD_EOPNOTSUPP; - } - - /* Macro which merge the 8bit security flags to the upper bits of the - 32bit input flags */ - MERGE_SEC_INTO_INPUT_FLAGS(flags, sdFlags); - - /* Function exists in the interface of the socket descriptor, dispatch - the SendTo command */ - retVal = (netIf->ifConf)->sockSendTo(realSd, sdContext, buf, len, flags, to, tolen); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKSENDTO_FAILED); - - return retVal; -} - - -//***************************************************************************** -// -// SlNetSock_getIfID - Get interface ID from socket descriptor (sd) -// -//***************************************************************************** -int32_t SlNetSock_getIfID(uint16_t sd) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - SlNetIf_t *netIf; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, NULL, NULL, &netIf); - - /* Check if sd found */ - if (SLNETERR_RET_CODE_OK != retVal) - { - /* Validation failed, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* Return interface identifier */ - return netIf->ifID; -} - - -//***************************************************************************** -// -// SlNetSock_secAttribCreate - Creates a security attributes object -// -//***************************************************************************** -SlNetSockSecAttrib_t *SlNetSock_secAttribCreate(void) -{ - SlNetSockSecAttrib_t *secAttribHandler; - - /* Allocate and initialize dynamic memory for security attribute handler */ - secAttribHandler = (SlNetSockSecAttrib_t *)calloc(1, sizeof(SlNetSockSecAttrib_t)); - - /* Check if the calloc function failed */ - if (NULL == secAttribHandler) - { - /* Function failed, return error code */ - return NULL; - } - - return (secAttribHandler); -} - - -//***************************************************************************** -// -// SlNetSock_secAttribDelete - Deletes a security attributes object -// -//***************************************************************************** -int32_t SlNetSock_secAttribDelete(SlNetSockSecAttrib_t *secAttrib) -{ - SlNetSock_SecAttribNode_t *nextSecAttrib; - SlNetSock_SecAttribNode_t *tempSecAttrib; - - /* Check if the input doesn't exist */ - if (NULL == secAttrib) - { - /* Function failed, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - else - { - nextSecAttrib = (SlNetSock_SecAttribNode_t *)*secAttrib; - tempSecAttrib = (SlNetSock_SecAttribNode_t *)*secAttrib; - } - - /* Free all SecAttrib list nodes */ - while (NULL != nextSecAttrib) - { - nextSecAttrib = tempSecAttrib->next; - free((void *)tempSecAttrib); - tempSecAttrib = nextSecAttrib; - } - - free(secAttrib); - - return SLNETERR_RET_CODE_OK; -} - - -//***************************************************************************** -// -// SlNetSock_secAttribSet - used to set a security attribute of a security -// attributes object -// -//***************************************************************************** -int32_t SlNetSock_secAttribSet(SlNetSockSecAttrib_t *secAttrib, SlNetSockSecAttrib_e attribName, void *val, uint16_t len) -{ - SlNetSock_SecAttribNode_t *secAttribObj; - - /* Check if the inputs doesn't exists or not valid */ - if ( (NULL == secAttrib) || (0 == len) || (NULL == val) ) - { - /* Function failed, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* Allocate dynamic memory for security attribute handler */ - secAttribObj = (SlNetSock_SecAttribNode_t *)malloc(sizeof(SlNetSock_SecAttribNode_t)); - - /* Check if the malloc function failed */ - if (NULL == secAttribObj) - { - /* Function failed, return error code */ - return SLNETERR_RET_CODE_MALLOC_ERROR; - } - - /* Set the inputs in the allocated security attribute handler */ - secAttribObj->attribName = attribName; - secAttribObj->attribBuff = val; - secAttribObj->attribBuffLen = len; - secAttribObj->next = *secAttrib; - - /* Connect the security attribute to the secAttrib list */ - *secAttrib = secAttribObj; - - - - return SLNETERR_RET_CODE_OK; -} - - -//***************************************************************************** -// -// SlNetSock_startSec - Start a security session on an opened socket -// -//***************************************************************************** -int32_t SlNetSock_startSec(int16_t sd, SlNetSockSecAttrib_t *secAttrib, uint8_t flags) -{ - int32_t retVal = SLNETERR_RET_CODE_OK; - int16_t realSd; - uint8_t sdFlags; - SlNetIf_t *netIf; - void *sdContext; - - /* Check if the sd input exists and return it */ - retVal = SlNetSock_getVirtualSdConf(sd, &realSd, &sdFlags, &sdContext, &netIf); - - /* Check if sd found or if the non mandatory function exists */ - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - if (NULL == (netIf->ifConf)->sockstartSec) - { - /* Non mandatory function doesn't exists, return error code */ - return SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN; - } - /* StartSec function called, set bit */ - sdFlags |= flags; - /* Function exists in the interface of the socket descriptor, dispatch - the startSec command */ - retVal = (netIf->ifConf)->sockstartSec(realSd, sdContext, secAttrib, flags); - SLNETSOCK_NORMALIZE_RET_VAL(retVal,SLNETSOCK_ERR_SOCKSTARTSEC_FAILED); - - return retVal; -} diff --git a/ext/hal/ti/simplelink/source/ti/net/slnetsock.h b/ext/hal/ti/simplelink/source/ti/net/slnetsock.h deleted file mode 100644 index 0e62d6f4df5..00000000000 --- a/ext/hal/ti/simplelink/source/ti/net/slnetsock.h +++ /dev/null @@ -1,1853 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - - /*! - - - \page SlNetSock_overview SlNetSock - - \section intro_sec Introduction - -SlNetSock provides a standard BSD API for TCP and UDP transport -layers, and a lower-level SlNetSock API for basic and extended -usage. Supported use cases include: - - - Support of multi interface (WiFi NS, Ethernet NDK) - - Selecting which interfaces the host will use, one or more. - - Support of different types of sockets (TCP, TLS, UDP, RAW, RF, etc.) - - BSD and proprietary errors - - The SlNetSock API's lead to easier portability to microcontrollers, - without compromising the capabilities and robustness of the final - application. - - - \section modules_sec Module Names - TI's SlNetSock layer is divided into the following software modules: - -# \ref SlNetSock - Controls standard client/server sockets options and capabilities - -# \ref SlNetIf - Controls standard stack/interface options and capabilities - -# \ref SlNetUtils - Provides sockets related commands and configuration - -# \ref SlNetErr - Provide BSD and proprietary errors - -In addition, SlNetSock provides a standard BSD API, built atop the -SlNet* APIs. The BSD headers are placed in ti/net/bsd directory, -which users should place on their include path. - -Also, there is a light -\subpage porting_guide "SL Interface Porting Guide" -with information available for adding SlNetSock support for other stacks. - - \page porting_guide SL Interface Porting Guide - - \section Introduction - -The generic SlNetSock layer sits between the application/service and -the interface stack. This guide describes the details of adding a network stack into the SlNetSock environment. - -The porting steps for adding new interface: - -# Create slnetifxxx file for the new interface - -# Select the capabilities set - -# Adding the interface to your application/service - -# Add the relevant functions to your application/service - -# Test your code to validate the correctness of your porting - - \subsection porting_step1 Step 1 - slnetifxxx.c and slnetifxxx.h file for your interface - - - Create slnetifxxx file (replace xxx with your interface/stack - name). Likely you will copy from an existing port. - - - Implement the needed API's. - -Each interface needs to provide a set of API's to work with the -interface. Some are mandatory, others are optional (but recommended). - - - Mandatory API's: - - \ref SlNetIf_Config_t.sockCreate "sockCreate" - - \ref SlNetIf_Config_t.sockClose "sockClose" - - \ref SlNetIf_Config_t.sockSelect "sockSelect" - - \ref SlNetIf_Config_t.sockSetOpt "sockSetOpt" - - \ref SlNetIf_Config_t.sockGetOpt "sockGetOpt" - - \ref SlNetIf_Config_t.sockRecvFrom "sockRecvFrom" - - \ref SlNetIf_Config_t.sockSendTo "sockSendTo" - - \ref SlNetIf_Config_t.ifGetIPAddr "ifGetIPAddr" - - \ref SlNetIf_Config_t.ifGetConnectionStatus "ifGetConnectionStatus" - - - The non-mandatory API's set: - - \ref SlNetIf_Config_t.sockShutdown "sockShutdown" - - \ref SlNetIf_Config_t.sockAccept "sockAccept" - - \ref SlNetIf_Config_t.sockBind "sockBind" - - \ref SlNetIf_Config_t.sockListen "sockListen" - - \ref SlNetIf_Config_t.sockConnect "sockConnect" - - \ref SlNetIf_Config_t.sockGetPeerName "sockGetPeerName" - - \ref SlNetIf_Config_t.sockGetLocalName "sockGetLocalName" - - \ref SlNetIf_Config_t.sockRecv "sockRecv" - - \ref SlNetIf_Config_t.sockSend "sockSend" - - \ref SlNetIf_Config_t.sockstartSec "sockstartSec" - - \ref SlNetIf_Config_t.utilGetHostByName "utilGetHostByName" - - \ref SlNetIf_Config_t.ifLoadSecObj "ifLoadSecOjb" - - \ref SlNetIf_Config_t.ifCreateContext "ifCreateContext" - - - \note The list of API's and more data can be found in ::SlNetIf_Config_t structure in SlNetIf module \n \n - - \subsection porting_step2 Step 2 - Select the capabilities set - - The capabilities prototype should be declared in your slnetifxxx.h and implemented in your slnetifxxx.c - - Each mandatory API's must be set, additional API's can be set or must - be set to NULL. - - An example config declaration for TI's SimpleLink CC31XX/CC32xx - - \code - SlNetIfConfig SlNetIfConfigWiFi = - { - SlNetIfWifi_socket, // Callback function sockCreate in slnetif module - SlNetIfWifi_close, // Callback function sockClose in slnetif module - NULL, // Callback function sockShutdown in slnetif module - SlNetIfWifi_accept, // Callback function sockAccept in slnetif module - SlNetIfWifi_bind, // Callback function sockBind in slnetif module - SlNetIfWifi_listen, // Callback function sockListen in slnetif module - SlNetIfWifi_connect, // Callback function sockConnect in slnetif module - NULL, // Callback function sockGetPeerName in slnetif module - NULL, // Callback function sockGetLocalName in slnetif module - SlNetIfWifi_select, // Callback function sockSelect in slnetif module - SlNetIfWifi_setSockOpt, // Callback function sockSetOpt in slnetif module - SlNetIfWifi_getSockOpt, // Callback function sockGetOpt in slnetif module - SlNetIfWifi_recv, // Callback function sockRecv in slnetif module - SlNetIfWifi_recvFrom, // Callback function sockRecvFrom in slnetif module - SlNetIfWifi_send, // Callback function sockSend in slnetif module - SlNetIfWifi_sendTo, // Callback function sockSendTo in slnetif module - SlNetIfWifi_sockstartSec, // Callback function sockstartSec in slnetif module - SlNetIfWifi_getHostByName, // Callback function utilGetHostByName in slnetif module - SlNetIfWifi_getIPAddr, // Callback function ifGetIPAddr in slnetif module - SlNetIfWifi_getConnectionStatus, // Callback function ifGetConnectionStatus in slnetif module - SlNetIfWifi_loadSecObj, // Callback function ifLoadSecObj in slnetif module - NULL // Callback function ifCreateContext in slnetif module - }; - \endcode - - In the example above the following API's are not supported by the interface, - and are set to NULL: - - sockShutdown - - sockGetPeerName - - sockGetLocalName - - utilGetHostByName - - ifCreateContext - - \subsection porting_step3 Step 3 - Adding the interface to your application/service - - \b Include the new file in the board header file in the application. - - \subsection porting_step4 Step 4 - Add the relevant functions to your application/service - - After configuring the capabilities of the interface, Adding the interface to the SlNetSock - is required. - - Use ::SlNetIf_add in order to add the interface and set his ID, Name, function list and priority. - Later on you need to use the BSD API's or SlNetSock API's for socket handling. - - \subsection porting_step5 Step 5 - Test your code to validate the correctness of your porting - - After porting the layer into your setup, validate that your code work as expected - -*/ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -#ifndef __SL_NET_SOCK_H__ -#define __SL_NET_SOCK_H__ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - - -/*! - \defgroup SlNetSock SlNetSock group - - \short Controls standard client/server sockets options and capabilities - -*/ -/*! - - \addtogroup SlNetSock - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#define SLNETSOCK_MAX_CONCURRENT_SOCKETS (32) /**< Declares the maximum sockets that can be opened */ - -/* Address families. */ -#define SLNETSOCK_AF_UNSPEC (0) /**< Unspecified address family */ -#define SLNETSOCK_AF_INET (2) /**< IPv4 socket (UDP, TCP, etc) */ -#define SLNETSOCK_AF_INET6 (3) /**< IPv6 socket (UDP, TCP, etc) */ -#define SLNETSOCK_AF_RF (6) /**< Data include RF parameter, All layer by user (Wifi could be disconnected) */ -#define SLNETSOCK_AF_PACKET (17) /**< Network bypass */ - -/* Protocol families, same as address families. */ -#define SLNETSOCK_PF_UNSPEC SLNETSOCK_AF_UNSPEC -#define SLNETSOCK_PF_INET SLNETSOCK_AF_INET -#define SLNETSOCK_PF_INET6 SLNETSOCK_AF_INET6 - -/* Define argument types specifies the socket type. */ -#define SLNETSOCK_SOCK_STREAM (1) /**< TCP Socket */ -#define SLNETSOCK_SOCK_DGRAM (2) /**< UDP Socket */ -#define SLNETSOCK_SOCK_RAW (3) /**< Raw socket */ -#define SLNETSOCK_SOCK_RX_MTR (4) /**< RX Metrics socket */ -#define SLNETSOCK_SOCK_MAC_WITH_CCA (5) -#define SLNETSOCK_SOCK_MAC_WITH_NO_CCA (6) -#define SLNETSOCK_SOCK_BRIDGE (7) -#define SLNETSOCK_SOCK_ROUTER (8) - -/* Define some BSD protocol constants. */ -#define SLNETSOCK_PROTO_TCP (6) /**< TCP Raw Socket */ -#define SLNETSOCK_PROTO_UDP (17) /**< UDP Raw Socket */ -#define SLNETSOCK_PROTO_RAW (255) /**< Raw Socket */ -#define SLNETSOCK_PROTO_SECURE (100) /**< Secured Socket Layer (SSL,TLS) */ - -/* bind any addresses */ -#define SLNETSOCK_INADDR_ANY (0) -#define SLNETSOCK_IN6ADDR_ANY (0) - - -/* socket options */ - -/* possible values for the level parameter in slNetSock_setOpt / slNetSock_getOpt */ -#define SLNETSOCK_LVL_SOCKET (1) /**< Define the socket option category. */ -#define SLNETSOCK_LVL_IP (2) /**< Define the IP option category. */ -#define SLNETSOCK_LVL_PHY (3) /**< Define the PHY option category. */ - -/* possible values for the option parameter in slNetSock_setOpt / slNetSock_getOpt */ - -/* socket level options (SLNETSOCK_LVL_SOCKET) */ -#define SLNETSOCK_OPSOCK_RCV_BUF (8) /**< Setting TCP receive buffer size (window size) - This options takes SlNetSock_Winsize_t struct as parameter */ -#define SLNETSOCK_OPSOCK_RCV_TIMEO (20) /**< Enable receive timeout - This options takes SlNetSock_Timeval_t struct as parameter */ -#define SLNETSOCK_OPSOCK_KEEPALIVE (9) /**< Connections are kept alive with periodic messages - This options takes SlNetSock_Keepalive_t struct as parameter */ -#define SLNETSOCK_OPSOCK_KEEPALIVE_TIME (37) /**< keepalive time out - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPSOCK_LINGER (13) /**< Socket lingers on close pending remaining send/receive packets - This options takes SlNetSock_linger_t struct as parameter */ -#define SLNETSOCK_OPSOCK_NON_BLOCKING (24) /**< Enable/disable nonblocking mode - This options takes SlNetSock_Nonblocking_t struct as parameter */ -#define SLNETSOCK_OPSOCK_NON_IP_BOUNDARY (39) /**< connectionless socket disable rx boundary - This options takes SlNetSock_NonIpBoundary_t struct as parameter */ -#define SLNETSOCK_OPSOCK_ERROR (58) /**< Socket level error code */ -#define SLNETSOCK_OPSOCK_SLNETSOCKSD (59) /**< Used by the BSD layer in order to retrieve the slnetsock sd */ -#define SLNETSOCK_OPSOCK_BROADCAST (200) /**< Enable/disable broadcast signals - This option takes SlNetSock_Broadcast_t struct as parameters */ - -/* IP level options (SLNETSOCK_LVL_IP) */ -#define SLNETSOCK_OPIP_MULTICAST_TTL (61) /**< Specify the TTL value to use for outgoing multicast packet. - This options takes uint8_t as parameter */ -#define SLNETSOCK_OPIP_ADD_MEMBERSHIP (65) /**< Join IPv4 multicast membership - This options takes SlNetSock_IpMreq_t struct as parameter */ -#define SLNETSOCK_OPIP_DROP_MEMBERSHIP (66) /**< Leave IPv4 multicast membership - This options takes SlNetSock_IpMreq_t struct as parameter */ -#define SLNETSOCK_OPIP_HDRINCL (67) /**< Raw socket IPv4 header included - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPIP_RAW_RX_NO_HEADER (68) /**< Proprietary socket option that does not includeIPv4/IPv6 header (and extension headers) on received raw sockets - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPIP_RAW_IPV6_HDRINCL (69) /**< Transmitted buffer over IPv6 socket contains IPv6 header - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPIPV6_ADD_MEMBERSHIP (70) /**< Join IPv6 multicast membership - This options takes SlNetSock_IpV6Mreq_t struct as parameter */ -#define SLNETSOCK_OPIPV6_DROP_MEMBERSHIP (71) /**< Leave IPv6 multicast membership - This options takes SlNetSock_IpV6Mreq_t struct as parameter */ -#define SLNETSOCK_OPIPV6_MULTICAST_HOPS (72) /**< Specify the hops value to use for outgoing multicast packet. */ - -/* PHY level options (SLNETSOCK_LVL_PHY) */ -#define SLNETSOCK_OPPHY_CHANNEL (28) /**< This option is available only when transceiver started - This options takes uint32_t as channel number parameter */ -#define SLNETSOCK_OPPHY_RATE (100) /**< WLAN Transmit rate - This options takes uint32_t as parameter based on SlWlanRateIndex_e */ -#define SLNETSOCK_OPPHY_TX_POWER (101) /**< TX Power level - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX (102) /**< Number of frames to transmit - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPPHY_PREAMBLE (103) /**< Preamble for transmission - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD (104) /**< TX Inhibit Threshold (CCA) - This options takes uint32_t as parameter based on SlNetSockTxInhibitThreshold_e */ -#define SLNETSOCK_OPPHY_TX_TIMEOUT (105) /**< TX timeout for Transceiver frames (lifetime) in miliseconds (max value is 100ms) - This options takes uint32_t as parameter */ -#define SLNETSOCK_OPPHY_ALLOW_ACKS (106) /**< Enable sending ACKs in transceiver mode - This options takes uint32_t as parameter */ - -/* TCP level options (SLNETSOCK_PROTO_TCP) */ -#define SLNETSOCK_TCP_NODELAY (203) /**< Disables TCP send delay/coalesce algorithm - This option takes SLNetSock_NoDelay_t struct as a parameter */ -#define SLNETSOCK_TCP_MAXSEG (204) /**< Set the maximum TCP segment size - This option takes SLNetSock_MaxSeg_t struct as a parameter */ -#define SLNETSOCK_TCP_NOPUSH (205) /**< Do not send data just to finish a data block (attempt to coalesce). - This option takes SLNetSock_NoPush_t struct as a parameter */ -#define SLNETSOCK_TCP_NOOPT (206) /**< Do not use TCP options. - This option takes SLNetSock_NoOpt_t struct as a parameter */ -#define SLNETSOCK_TCP_SACKPERMITTED (207) /**< Permit RFC-2018 Selective Acknowledgment(SACK) conformant connection - This option takes SLNetSock_SackPermitted_t struct as a parameter */ -#define SLNETSOCK_TCP_MAXRTT (208) /**< The maximum TCP Round Trip Time value allowed in the determination of the estimated TCP RTT - This option takes SLNetSock_MaxRtt_t struct as a parameter */ - -/*! - \brief The SlNetSockTxInhibitThreshold_e enumerations is used in SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD PHY level option -*/ -typedef enum -{ - SLNETSOCK_TX_INHIBIT_THRESHOLD_MIN = 1, - SLNETSOCK_TX_INHIBIT_THRESHOLD_LOW = 2, - SLNETSOCK_TX_INHIBIT_THRESHOLD_DEFAULT = 3, - SLNETSOCK_TX_INHIBIT_THRESHOLD_MED = 4, - SLNETSOCK_TX_INHIBIT_THRESHOLD_HIGH = 5, - SLNETSOCK_TX_INHIBIT_THRESHOLD_MAX = 6 -} SlNetSockTxInhibitThreshold_e; - -/*! - \brief The SlNetSockSecAttrib_e enumerations are used to declare security - attribute objects in SlNetSock_secAttribSet(). - - \sa SlNetSock_secAttribSet() -*/ -typedef enum -{ - SLNETSOCK_SEC_ATTRIB_PRIVATE_KEY = 0, - SLNETSOCK_SEC_ATTRIB_LOCAL_CERT = 1, - SLNETSOCK_SEC_ATTRIB_PEER_ROOT_CA = 2, - SLNETSOCK_SEC_ATTRIB_DH_KEY = 3, - SLNETSOCK_SEC_ATTRIB_METHOD = 4, - SLNETSOCK_SEC_ATTRIB_CIPHERS = 5, - SLNETSOCK_SEC_ATTRIB_ALPN = 6, - SLNETSOCK_SEC_ATTRIB_EXT_CLIENT_CHLNG_RESP = 7, - SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME = 8, - - /*! - @c SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE is - currently only supported on CC3x20 devices. - - The certificate store is a file, provided by TI, - containing a list of known and trusted root CAs by TI. - For more information, see the CC3x20 documentation. - - The certificate store is used only in client mode. Servers - use a proprietary root CA to authenticate clients, and - therefore cannot use the certificate store. - - Using this attribute allows using root CA which isn't a - part of the provided certificate store. - */ - - SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE = 9 -} SlNetSockSecAttrib_e; - -/* available values for SLNETSOCK_SEC_ATTRIB_METHOD */ -#define SLNETSOCK_SEC_METHOD_SSLV3 (0) /**< security method SSL v3 */ -#define SLNETSOCK_SEC_METHOD_TLSV1 (1) /**< security method TLS v1 */ -#define SLNETSOCK_SEC_METHOD_TLSV1_1 (2) /**< security method TLS v1_1 */ -#define SLNETSOCK_SEC_METHOD_TLSV1_2 (3) /**< security method TLS v1_2 */ -#define SLNETSOCK_SEC_METHOD_SSLv3_TLSV1_2 (4) /**< use highest possible version from SSLv3 - TLS 1.2 */ -#define SLNETSOCK_SEC_METHOD_DLSV1 (5) /**< security method DTL v1 */ - -/* available values for SLNETSOCK_SEC_ATTRIB_CIPHERS. The value is bitmap! */ -#define SLNETSOCK_SEC_CIPHER_SSL_RSA_WITH_RC4_128_SHA (1 << 0) -#define SLNETSOCK_SEC_CIPHER_SSL_RSA_WITH_RC4_128_MD5 (1 << 1) -#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_256_CBC_SHA (1 << 2) -#define SLNETSOCK_SEC_CIPHER_TLS_DHE_RSA_WITH_AES_256_CBC_SHA (1 << 3) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA (1 << 4) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_RC4_128_SHA (1 << 5) -#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_128_CBC_SHA256 (1 << 6) -#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_256_CBC_SHA256 (1 << 7) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (1 << 8) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (1 << 9) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA (1 << 10) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA (1 << 11) -#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_128_GCM_SHA256 (1 << 12) -#define SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_256_GCM_SHA384 (1 << 13) -#define SLNETSOCK_SEC_CIPHER_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 (1 << 14) -#define SLNETSOCK_SEC_CIPHER_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 (1 << 15) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (1 << 16) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (1 << 17) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (1 << 18) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 (1 << 19) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 20) -#define SLNETSOCK_SEC_CIPHER_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 21) -#define SLNETSOCK_SEC_CIPHER_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 (1 << 22) -#define SLNETSOCK_SEC_CIPHER_FULL_LIST (0xFFFFFFFF) - -/* available values for SLNETSOCK_SEC_ATTRIB_ALPN */ -#define SLNETSOCK_SEC_ALPN_H1 (1 << 0) -#define SLNETSOCK_SEC_ALPN_H2 (1 << 1) -#define SLNETSOCK_SEC_ALPN_H2C (1 << 2) -#define SLNETSOCK_SEC_ALPN_H2_14 (1 << 3) -#define SLNETSOCK_SEC_ALPN_H2_16 (1 << 4) -#define SLNETSOCK_SEC_ALPN_FULL_LIST ((SLNETSOCK_SEC_ALPN_H2_16 << 1 ) - 1) - -/* available values for the flags of the SlNetSock_startSec function */ -#define SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY (1 << 0) /**< Sends the command that will start the security session for a specific socket descriptor */ -#define SLNETSOCK_SEC_BIND_CONTEXT_ONLY (1 << 1) /**< Binds the security context to a specific socket descriptor */ -#define SLNETSOCK_SEC_IS_SERVER (1 << 2) /**< Used to define if the socket is client/server socket */ - -/* available values for the flags of the SlNetSock_create function */ - -#define SLNETSOCK_CREATE_IF_STATE_ENABLE (1 << 0) /**< Creation of the socket will be on enabled state */ -#define SLNETSOCK_CREATE_IF_STATUS_CONNECTED (1 << 1) /**< Creation of the socket will be on status connected */ -#define SLNETSOCK_CREATE_ALLOW_PARTIAL_MATCH (1 << 2) /**< Creation of the socket will be on the interface with - the highest priority if the other flags will fail */ - -/* Definitions for shutting down some or all parts of a full duplex connection */ -#define SLNETSOCK_SHUT_RD (0) /**< Further receptions will be disallowed */ -#define SLNETSOCK_SHUT_WR (1) /**< Further transmissions will be disallowed */ -#define SLNETSOCK_SHUT_RDWR (2) /**< Further receptions and transmissions will be disallowed */ - -/* Length of address string representation */ -#define SLNETSOCK_INET6_ADDRSTRLEN (46) -#define SLNETSOCK_INET_ADDRSTRLEN (16) - -/* flags used in send/recv and friends. - * - * Note these flags must not exceed 24-bits. The implementation will - * OR the 8-bits of security flags into the remaining high 8 bits of - * 32-bit flag variables. - */ -#define SLNETSOCK_MSG_OOB (0x0001) -#define SLNETSOCK_MSG_PEEK (0x0002) -#define SLNETSOCK_MSG_WAITALL (0x0004) -#define SLNETSOCK_MSG_DONTWAIT (0x0008) -#define SLNETSOCK_MSG_DONTROUTE (0x0010) -#define SLNETSOCK_MSG_NOSIGNAL (0x0020) - - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -/*! - \brief Internet address -*/ -typedef struct SlNetSock_InAddr_t -{ -#ifndef s_addr - uint32_t s_addr; /* Internet address 32 bits */ -#else -/*! - \brief Different representations for in addr for different hosts. -*/ - union S_un - { - uint32_t S_addr; - struct - { - uint8_t s_b1,s_b2,s_b3,s_b4; - } S_un_b; - struct - { - uint16_t s_w1,s_w2; - } S_un_w; - } S_un; -#endif -} SlNetSock_InAddr_t; - -/*! - \brief IpV6 or Ipv6 EUI64 -*/ -typedef struct SlNetSock_In6Addr_t -{ - union - { - uint8_t _S6_u8[16]; - uint16_t _S6_u16[8]; - uint32_t _S6_u32[4]; - } _S6_un; -} SlNetSock_In6Addr_t; - -/*! - \brief The SlNetSock_NoDelay_t structure is used in #SLNETSOCK_TCP_NODELAY TCP level option -*/ -typedef struct SlNetSock_NoDelay_t -{ - uint32_t noDelayEnabled; /**< 0 = disabled;1 = enabled; default = 0 */ -} SlNetSock_NoDelay_t; - -/*! - \brief The SlNetSock_MaxSeg_t structure is used in #SLNETSOCK_TCP_MAXSEG TCP level option -*/ -typedef struct SlNetSock_MaxSeg_t -{ - uint32_t maxSeg; /**< Maximum TCP segment size. Default = 536 */ -} SlNetSock_MaxSeg_t; - -/*! - \brief The SlNetSock_NoPush_t structure is used in #SLNETSOCK_TCP_NOPUSH TCP level option -*/ -typedef struct SlNetSock_NoPush_t -{ - uint32_t noPushEnabled; /**< 0 = disabled;1 = enabled; default = 0 */ -} SlNetSock_NoPush_t; - -/*! - \brief The SlNetSock_NoOpt_t structure is used in #SLNETSOCK_TCP_NOOPT TCP level option -*/ -typedef struct SlNetSock_NoOpt_t -{ - uint32_t noOptEnabled; /**< 0 = disabled;1 = enabled; default = 0 */ -} SlNetSock_NoOpt_t; - -/*! - \brief The SlNetSock_SackPermitted_t structure is used in #SLNETSOCK_TCP_NOPUSH TCP level option -*/ -typedef struct SlNetSock_SackPermitted_t -{ - uint32_t sackPermittedEnabled; /**< 0 = disabled;1 = enabled; default = 0 */ -} SlNetSock_SackPermitted_t; - -/*! - \brief The SlNetSock_MaxRtt_t structure is used in #SLNETSOCK_TCP_MAXRTT TCP level option -*/ -typedef struct SlNetSock_MaxRtt_t -{ - uint32_t maxRtt; /**< Maximum TCP Round Trip Time value allowed; Default = 360000000 */ -} SlNetSock_MaxRtt_t; - -/*! - \brief The SlNetSock_Keepalive_t structure is used in #SLNETSOCK_OPSOCK_KEEPALIVE socket level option -*/ -typedef struct SlNetSock_Keepalive_t -{ - uint32_t keepaliveEnabled; /**< 0 = disabled;1 = enabled; default = 1 */ -} SlNetSock_Keepalive_t; - -/*! - \brief The SlNetSock_NonIpBoundary_t structure is used in #SLNETSOCK_OPSOCK_NON_IP_BOUNDARY socket level option -*/ -typedef struct SlNetSock_NonIpBoundary_t -{ - int32_t nonIpBoundaryEnabled; /**< 0 = keep IP boundary; 1 = don`t keep ip boundary; default = 0; */ -} SlNetSock_NonIpBoundary_t; - -/*! - \brief The SlNetSock_Winsize_t structure is used in #SLNETSOCK_OPSOCK_RCV_BUF socket level option -*/ -typedef struct SlNetSock_Winsize_t -{ - uint32_t winSize; /**< receive window size for tcp sockets */ -} SlNetSock_Winsize_t; - -/*! - \brief The SlNetSock_Nonblocking_t structure is used in #SLNETSOCK_OPSOCK_NON_BLOCKING socket level option -*/ -typedef struct SlNetSock_Nonblocking_t -{ - uint32_t nonBlockingEnabled; /**< 0 = disabled, 1 = enabled, default = 1*/ -} SlNetSock_Nonblocking_t; - -/*! - \brief The SlNetSock_Broadcast_t structure is used in #SLNETSOCK_OPSOCK_BROADCAST socket level option -*/ -typedef struct SlNetSock_Broadcast_t -{ - uint32_t broadcastEnabled; /**< 0 = disabled, 1 = enabled, default = 0*/ -} SlNetSock_Broadcast_t; - -/*! - \brief Secure socket attribute context -*/ -typedef struct SlNetSock_SecAttribNode_t -{ - SlNetSockSecAttrib_e attribName; /**< Security attribute name */ - uint8_t *attribBuff; /**< Security attribute buffer */ - uint16_t attribBuffLen; /**< Security attribute buffer length */ - struct SlNetSock_SecAttribNode_t *next; -} SlNetSock_SecAttribNode_t; - -/*! - \brief Secure socket attribute handler -*/ -typedef SlNetSock_SecAttribNode_t * SlNetSockSecAttrib_t; - -/*! - \brief Secure ALPN structure -*/ -typedef struct SlNetSock_SecureALPN_t -{ - uint32_t secureALPN; -} SlNetSock_SecureALPN_t; - -/*! - \brief Secure Mask structure -*/ -typedef struct SlNetSock_SecureMask_t -{ - uint32_t secureMask; -} SlNetSock_SecureMask_t; - -/*! - \brief Secure Method structure -*/ -typedef struct SlNetSock_SecureMethod_t -{ - uint8_t secureMethod; -} SlNetSock_SecureMethod_t; - -/*! - \brief The SlNetSock_IpMreq_t structure is used in #SLNETSOCK_OPIP_ADD_MEMBERSHIP and #SLNETSOCK_OPIP_DROP_MEMBERSHIP IP level option -*/ -typedef struct SlNetSock_IpMreq_t -{ - SlNetSock_InAddr_t imr_multiaddr; /**< The IPv4 multicast address to join */ - uint32_t imr_interface; /**< The interface to use for this group */ -} SlNetSock_IpMreq_t; - -/*! - \brief The SlNetSock_IpV6Mreq_t structure is used in #SLNETSOCK_OPIPV6_ADD_MEMBERSHIP and #SLNETSOCK_OPIPV6_DROP_MEMBERSHIP IP level option -*/ -typedef struct SlNetSock_IpV6Mreq_t -{ - SlNetSock_In6Addr_t ipv6mr_multiaddr; /**< IPv6 multicast address of group */ - uint32_t ipv6mr_interface; /**< should be 0 to choose the default multicast interface */ -} SlNetSock_IpV6Mreq_t; - -/*! - \brief The SlNetSock_linger_t structure is used in #SLNETSOCK_OPSOCK_LINGER socket level option -*/ -typedef struct SlNetSock_linger_t -{ - uint32_t l_onoff; /**< 0 = disabled; 1 = enabled; default = 0; */ - uint32_t l_linger; /**< linger time in seconds; default = 0; */ -} SlNetSock_linger_t; - -/*! - \brief The @c SlNetSock_Timeval_t structure is used in - #SLNETSOCK_OPSOCK_RCV_TIMEO socket level option - - \remarks Note that @c SlNetSock_Timeval_t is intentionally defined - to be equivalent to the POSIX-defined struct - timeval data type. -*/ -typedef struct timeval SlNetSock_Timeval_t; - -/*! - \brief The SlNetSocklen_t is used for declaring the socket length parameter -*/ -typedef uint16_t SlNetSocklen_t; - -/*! - \brief IpV4 socket address -*/ -typedef struct SlNetSock_Addr_t -{ - uint16_t sa_family; /**< Address family (e.g. AF_INET) */ - uint8_t sa_data[14]; /**< Protocol- specific address information */ -} SlNetSock_Addr_t; - -/*! - \brief SlNetSock IPv6 address, Internet style -*/ -typedef struct SlNetSock_AddrIn6_t -{ - uint16_t sin6_family; /**< SLNETSOCK_AF_INET6 */ - uint16_t sin6_port; /**< Transport layer port. */ - uint32_t sin6_flowinfo; /**< IPv6 flow information. */ - SlNetSock_In6Addr_t sin6_addr; /**< IPv6 address. */ - uint32_t sin6_scope_id; /**< set of interfaces for a scope. */ -} SlNetSock_AddrIn6_t; - -/*! - \brief SlNetSock IPv4 address, Internet style -*/ -typedef struct SlNetSock_AddrIn_t -{ - uint16_t sin_family; /**< Internet Protocol (AF_INET). */ - uint16_t sin_port; /**< Address port (16 bits). */ - SlNetSock_InAddr_t sin_addr; /**< Internet address (32 bits). */ - int8_t sin_zero[8]; /**< Not used. */ -} SlNetSock_AddrIn_t; - -/* ss_family + pad must be large enough to hold max of - * _SlNetSock_AddrIn6_t or _SlNetSock_AddrIn_t - */ -/*! - \brief Generic socket address type to hold either IPv4 or IPv6 address -*/ -typedef struct SlNetSock_SockAddrStorage_t -{ - uint16_t ss_family; - uint8_t pad[26]; -} SlNetSock_SockAddrStorage_t; - -/*! - \brief The SlNetSock_SdSet_t structure holds the sd array for SlNetSock_select function -*/ -typedef struct SlNetSock_SdSet_t /**< The select socket array manager */ -{ - uint32_t sdSetBitmap[(SLNETSOCK_MAX_CONCURRENT_SOCKETS + (uint8_t)31)/(uint8_t)32]; /* Bitmap of SOCKET Descriptors */ -} SlNetSock_SdSet_t; - - -/*! - \brief The SlNetSock_TransceiverRxOverHead_t structure holds the data for Rx transceiver mode using a raw socket when using SlNetSock_recv function -*/ -typedef struct SlNetSock_TransceiverRxOverHead_t -{ - uint8_t rate; /**< Received Rate */ - uint8_t channel; /**< The received channel */ - int8_t rssi; /**< The computed RSSI value in db of current frame */ - uint8_t padding; /**< pad to align to 32 bits */ - uint32_t timestamp; /**< Timestamp in microseconds */ -} SlNetSock_TransceiverRxOverHead_t; - - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - - \brief Initialize the SlNetSock module - - \param[in] flags Reserved - - \return Zero on success, or negative error code on failure - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetSock_init snippet - -*/ -int32_t SlNetSock_init(int32_t flags); - -/*! - - \brief Create an endpoint for communication - - SlNetSock_create() creates a new socket of a certain socket type, - identified by an integer number, and allocates system resources to it.\n - This function is called by the application layer to obtain a socket descriptor (handle). - - \param[in] domain Specifies the protocol family of the created socket. - For example: - - #SLNETSOCK_AF_INET for network protocol IPv4 - - #SLNETSOCK_AF_INET6 for network protocol IPv6 - - #SLNETSOCK_AF_RF for starting transceiver mode. - Notes: - - sending and receiving any packet overriding 802.11 header - - for optimized power consumption the socket will be started in TX - only mode until receive command is activated - \param[in] type Specifies the socket type, which determines the semantics of communication over - the socket. The socket types supported by the system are implementation-dependent. - Possible socket types include: - - #SLNETSOCK_SOCK_STREAM (reliable stream-oriented service or Stream Sockets) - - #SLNETSOCK_SOCK_DGRAM (datagram service or Datagram Sockets) - - #SLNETSOCK_SOCK_RAW (raw protocols atop the network layer) - - when used with AF_RF: - - #SLNETSOCK_SOCK_RX_MTR - - #SLNETSOCK_SOCK_MAC_WITH_CCA - - #SLNETSOCK_SOCK_MAC_WITH_NO_CCA - - #SLNETSOCK_SOCK_BRIDGE - - #SLNETSOCK_SOCK_ROUTER - \param[in] protocol Specifies a particular transport to be used with the socket.\n - The most common are - - #SLNETSOCK_PROTO_TCP - - #SLNETSOCK_PROTO_UDP - - #SLNETSOCK_PROTO_RAW - - #SLNETSOCK_PROTO_SECURE - \param[in] ifBitmap Specifies the interface(s) which the socket will be created on - according to priority until one of them will return an answer.\n - Value 0 is used in order to choose automatic interfaces selection - according to the priority interface list. - Value can be a combination of interfaces by OR'ing multiple interfaces bit identifiers - (SLNETIFC_IDENT_ defined in slnetif.h) - Note: interface identifier bit must be configured prior to this socket creation - using SlNetIf_add(). - \param[in] flags Specifies flags. - - #SLNETSOCK_CREATE_IF_STATE_ENABLE - Creation of the socket will be on enabled state - - #SLNETSOCK_CREATE_IF_STATUS_CONNECTED - Creation of the socket will be on status connected - - #SLNETSOCK_CREATE_ALLOW_PARTIAL_MATCH - Creation of the socket will be on the interface with - the highest priority if the other flags will fail - The value 0 may be used in order to run the default flags: - - #SLNETSOCK_CREATE_IF_STATE_ENABLE - - #SLNETSOCK_CREATE_IF_STATUS_CONNECTED - - \return On success, socket descriptor (handle) that is used for consequent socket operations. \n - A successful return code should be a positive number\n - On error, a negative value will be returned specifying the error code. - - #SLNETERR_BSD_EAFNOSUPPORT - illegal domain parameter - - #SLNETERR_BSD_EPROTOTYPE - illegal type parameter - - #SLNETERR_BSD_EACCES - permission denied - - #SLNETERR_BSD_ENSOCK - exceeded maximal number of socket - - #SLNETERR_BSD_ENOMEM - memory allocation error - - #SLNETERR_BSD_EINVAL - error in socket configuration - - #SLNETERR_BSD_EPROTONOSUPPORT - illegal protocol parameter - - #SLNETERR_BSD_EOPNOTSUPP - illegal combination of protocol and type parameters - - \slnetsock_init_precondition - - \remark Not all platforms support all options. - - \remark A @c protocol value of zero can be used to select the default protocol from the selected @c domain and @c type. - - \remark SlNetSock_create() uses the highest priority interface from the ifBitmap, subject to the constraints specified - in the flags parameter. An interface that does not satisfy the constraints is ignored, without regards to its - priority level. - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetSock_create TCP IPv4 snippet - \snippet ti/net/test/snippets/slnetif.c SlNetSock_create TCP IPv6 snippet - \snippet ti/net/test/snippets/slnetif.c SlNetSock_create UDP IPv4 snippet - - \sa SlNetSock_close() -*/ -int16_t SlNetSock_create(int16_t domain, int16_t type, int16_t protocol, uint32_t ifBitmap, int16_t flags); - - -/*! - \brief Gracefully close socket - - Release resources allocated to a socket. - - \param[in] sd Socket descriptor (handle), received in SlNetSock_create() - - \return Zero on success, or negative error code on failure - - \slnetsock_init_precondition - - \remark In the case of TCP, the connection is terminated. - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetSock_close snippet - - \sa SlNetSock_create() -*/ -int32_t SlNetSock_close(int16_t sd); - - -/*! - \brief Shutting down parts of a full-duplex connection - - Shuts down parts of a full-duplex connection according to how parameter.\n - - \param[in] sd Socket descriptor (handle), received in SlNetSock_create - \param[in] how Specifies which part of a full-duplex connection to shutdown. \n - The options are - - #SLNETSOCK_SHUT_RD - further receptions will be disallowed - - #SLNETSOCK_SHUT_WR - further transmissions will be disallowed - - #SLNETSOCK_SHUT_RDWR - further receptions and transmissions will be disallowed - - \return Zero on success, or negative error code on failure - - \slnetsock_init_precondition - - \sa SlNetSock_create() - \sa SlNetSock_connect() - \sa SlNetSock_accept() -*/ -int32_t SlNetSock_shutdown(int16_t sd, int16_t how); - - -/*! - \brief Accept a connection on a socket - - The SlNetSock_accept function is used with connection-based socket types (#SLNETSOCK_SOCK_STREAM). - - It extracts the first connection request on the queue of pending - connections, creates a new connected socket, and returns a new file - descriptor referring to that socket. - - The newly created socket is not in the listening state. The - original socket sd is unaffected by this call. - - The argument sd is a socket that has been created with - SlNetSock_create(), bound to a local address with - SlNetSock_bind(), and is listening for connections after a - SlNetSock_listen(). - - The argument \c addr is a pointer to a sockaddr structure. This - structure is filled in with the address of the peer socket, as - known to the communications layer. - - The exact format of the address returned \c addr is determined by the socket's address family. - - \c addrlen is a value-result argument: it should initially contain - the size of the structure pointed to by addr, on return it will - contain the actual length (in bytes) of the address returned. - - \param[in] sd Socket descriptor (handle) - \param[out] addr The argument addr is a pointer - to a sockaddr structure. This - structure is filled in with the - address of the peer socket, as - known to the communications - layer. The exact format of the - address returned addr is - determined by the socket's - address\n - sockaddr:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[out] addrlen The addrlen argument is a value-result - argument: it should initially contain the - size of the structure pointed to by addr - - \return On success, a socket descriptor.\n - On a non-blocking accept a possible negative value is #SLNETERR_BSD_EAGAIN.\n - On failure, negative error code.\n - #SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - - \slnetsock_init_precondition - - \sa SlNetSock_create() - \sa SlNetSock_bind() - \sa SlNetSock_listen() -*/ -int16_t SlNetSock_accept(int16_t sd, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); - - -/*! - \brief Assign a name to a socket - - This SlNetSock_bind function gives the socket the local address - addr. addr is addrlen bytes long. - - Traditionally, this is called when a socket is created with - socket, it exists in a name space (address family) but has no name - assigned. - - It is necessary to assign a local address before a #SLNETSOCK_SOCK_STREAM - socket may receive connections. - - \param[in] sd Socket descriptor (handle) - \param[in] addr Specifies the destination - addrs\n sockaddr:\n - code for - the address format.\n - socket address, - the length depends on the code - format - \param[in] addrlen Contains the size of the structure pointed to by addr - - \return Zero on success, or negative error code on failure - - \slnetsock_init_precondition - - \sa SlNetSock_create() - \sa SlNetSock_accept() - \sa SlNetSock_listen() -*/ -int32_t SlNetSock_bind(int16_t sd, const SlNetSock_Addr_t *addr, int16_t addrlen); - - -/*! - \brief Listen for connections on a socket - - The willingness to accept incoming connections and a queue - limit for incoming connections are specified with SlNetSock_listen(), - and then the connections are accepted with SlNetSock_accept(). - - \param[in] sd Socket descriptor (handle) - \param[in] backlog Specifies the listen queue depth. - - \return Zero on success, or negative error code on failure - - \slnetsock_init_precondition - - \remark The SlNetSock_listen() call applies only to sockets of - type #SLNETSOCK_SOCK_STREAM. - - \remark The \c backlog parameter defines the maximum length the queue of - pending connections may grow to. - - \sa SlNetSock_create() - \sa SlNetSock_accept() - \sa SlNetSock_bind() -*/ -int32_t SlNetSock_listen(int16_t sd, int16_t backlog); - - -/*! - \brief Initiate a connection on a socket - - Function connects the socket referred to by the socket - descriptor sd, to the address specified by \c addr. - - The format of the address in addr is determined by the address - space of the socket. - - If it is of type #SLNETSOCK_SOCK_DGRAM, this call specifies the - peer with which the socket is to be associated; this address is - that to which datagrams are to be sent, and the only address from - which datagrams are to be received. - - If the socket is of type #SLNETSOCK_SOCK_STREAM, this call - attempts to make a connection to another socket. - - The other socket is specified by address, which is an address in - the communications space of the socket. - - \param[in] sd Socket descriptor (handle) - \param[in] addr Specifies the destination addr\n - sockaddr:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[in] addrlen Contains the size of the structure pointed - to by addr - - \return On success, a socket descriptor (handle).\n - On failure, negative value.\n - On a non-blocking connect a possible negative value is #SLNETERR_BSD_EALREADY. - #SLNETERR_POOL_IS_EMPTY may be returned in case there are no resources in the system - - \slnetsock_init_precondition - - \sa SlNetSock_create() -*/ -int32_t SlNetSock_connect(int16_t sd, const SlNetSock_Addr_t *addr, SlNetSocklen_t addrlen); - -/*! - \brief Return address info about the remote side of the connection - - Returns a struct SlNetSock_AddrIn_t - filled with information about the peer device that is connected - on the other side of the socket descriptor. - - \param[in] sd Socket descriptor (handle) - \param[out] addr returns the struct addr\n - SlNetSockAddrIn filled with information - about the peer device:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[out] addrlen Contains the size of the structure pointed - to by addr - - \return Zero on success, or negative error code on failure - - \slnetsock_init_precondition - - \sa SlNetSock_accept() - \sa SlNetSock_connect() -*/ -int32_t SlNetSock_getPeerName(int16_t sd, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); - - -/*! - \brief Get local address info by socket descriptor - - Returns the local address info of the socket descriptor. - - \param[in] sd Socket descriptor (handle) - \param[out] addr The argument addr is a pointer - to a SlNetSock_Addr_t structure. This - structure is filled in with the - address of the peer socket, as - known to the communications - layer. The exact format of the - address returned addr is - determined by the socket's - address\n - SlNetSock_Addr_t:\n - code for the - address format.\n - - socket address, the length - depends on the code format - \param[out] addrlen The addrlen argument is a value-result - argument: it should initially contain the - size of the structure pointed to by addr - - \return Zero on success, or negative on failure. - - \slnetsock_init_precondition - - \remark If the provided buffer is too small the returned address - will be truncated and \c addrlen will contain the - actual size of the socket address. - - \sa SlNetSock_create() - \sa SlNetSock_bind() -*/ -int32_t SlNetSock_getSockName(int16_t sd, SlNetSock_Addr_t *addr, SlNetSocklen_t *addrlen); - - -/*! - \brief Monitor socket activity - - SlNetSock_select() allow a program to monitor multiple file descriptors, - waiting until one or more of the file descriptors become - "ready" for some class of I/O operation. - - \param[in] nsds The highest-numbered file descriptor in any of the - three sets, plus 1. - \param[in,out] readsds Socket descriptors list for read monitoring and accept monitoring - \param[in,out] writesds Socket descriptors list for connect monitoring only, write monitoring is not supported - \param[in,out] exceptsds Socket descriptors list for exception monitoring, not supported. - \param[in] timeout Is an upper bound on the amount of time elapsed - before SlNetSock_select() returns. Null or above 0xffff seconds means - infinity timeout. The minimum timeout is 10 milliseconds, - less than 10 milliseconds will be set automatically to 10 milliseconds. - Max microseconds supported is 0xfffc00. - In trigger mode the timeout fields must be set to zero. - - \return On success, SlNetSock_select() returns the number of - file descriptors contained in the three returned - descriptor sets (that is, the total number of bits that - are set in readsds, writesds, exceptsds) which may be - zero if the timeout expires before anything interesting - happens.\n On error, a negative value is returned. - readsds - return the sockets on which Read request will - return without delay with valid data.\n - writesds - return the sockets on which Write request - will return without delay.\n - exceptsds - return the sockets closed recently. \n - #SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - - \slnetsock_init_precondition - - \remark If \c timeout is set to less than 10ms it will - automatically set to 10ms to prevent overload of the - system - - \sa SlNetSock_create() -*/ -int32_t SlNetSock_select(int16_t nsds, SlNetSock_SdSet_t *readsds, SlNetSock_SdSet_t *writesds, SlNetSock_SdSet_t *exceptsds, SlNetSock_Timeval_t *timeout); - - -/*! - \brief SlNetSock_select's SlNetSock_SdSet_t SET function - - Sets current socket descriptor on SlNetSock_SdSet_t container -*/ -int32_t SlNetSock_sdsSet(int16_t sd, SlNetSock_SdSet_t *sdset); - - -/*! - \brief SlNetSock_select's SlNetSock_SdSet_t CLR function - - Clears current socket descriptor on SlNetSock_SdSet_t container -*/ -int32_t SlNetSock_sdsClr(int16_t sd, SlNetSock_SdSet_t *sdset); - - -/*! - \brief SlNetSock_select's SlNetSock_SdSet_t ZERO function - - Clears all socket descriptors from SlNetSock_SdSet_t -*/ -int32_t SlNetSock_sdsClrAll(SlNetSock_SdSet_t *sdset); - - -/*! - \brief SlNetSock_select's SlNetSock_SdSet_t ISSET function - - Checks if current socket descriptor is set (true/false) - - \return Returns true if set, false if unset - -*/ -int32_t SlNetSock_sdsIsSet(int16_t sd, SlNetSock_SdSet_t *sdset); - - -/*! - \brief Set socket options - - SlNetSock_setOpt() manipulates the options associated with a socket. - - Options may exist at multiple protocol levels; they are always - present at the uppermost socket level. - - When manipulating socket options the level at which the option resides - and the name of the option must be specified. To manipulate options at - the socket level, level is specified as #SLNETSOCK_LVL_SOCKET. To manipulate - options at any other level the protocol number of the appropriate protocol - controlling the option is supplied. For example, to indicate that an - option is to be interpreted by the TCP protocol, level should be set to - the protocol number of TCP. - - \c optval and \c optlen are used to access opt_values - for SlNetSock_setOpt(). For SlNetSock_getOpt() they identify a - buffer in which the value for the requested option(s) are to - be returned. For SlNetSock_getOpt(), \c optlen is a value-result - parameter, initially containing the size of the buffer - pointed to by option_value, and modified on return to - indicate the actual size of the value returned. If no option - value is to be supplied or returned, \c optval may be \c NULL. - - \param[in] sd Socket descriptor (handle) - \param[in] level Defines the protocol level for this option - - #SLNETSOCK_LVL_SOCKET - Socket level configurations (L4, transport layer) - - #SLNETSOCK_LVL_IP - IP level configurations (L3, network layer) - - #SLNETSOCK_LVL_PHY - Link level configurations (L2, link layer) - \param[in] optname Defines the option name to interrogate - - #SLNETSOCK_LVL_SOCKET - - #SLNETSOCK_OPSOCK_RCV_BUF\n - Sets tcp max recv window size.\n - This options takes SlNetSock_Winsize_t struct as parameter - - #SLNETSOCK_OPSOCK_RCV_TIMEO\n - Sets the timeout value that specifies the maximum amount of time an input function waits until it completes.\n - Default: No timeout\n - This options takes SlNetSock_Timeval_t struct as parameter - - #SLNETSOCK_OPSOCK_KEEPALIVE\n - Enable or Disable periodic keep alive. - Keeps TCP connections active by enabling the periodic transmission of messages \n - Timeout is 5 minutes.\n - Default: Enabled \n - This options takes SlNetSock_Keepalive_t struct as parameter - - #SLNETSOCK_OPSOCK_KEEPALIVE_TIME\n - Set keep alive timeout. - Value is in seconds \n - Default: 5 minutes \n - - #SLNETSOCK_OPSOCK_LINGER\n - Socket lingers on close pending remaining send/receive packets\n - - #SLNETSOCK_OPSOCK_NON_BLOCKING\n - Sets socket to non-blocking operation Impacts: connect, accept, send, sendto, recv and recvfrom. \n - Default: Blocking. - This options takes SlNetSock_Nonblocking_t struct as parameter - - #SLNETSOCK_OPSOCK_NON_IP_BOUNDARY\n - Enable or Disable rx ip boundary. - In connectionless socket (udp/raw), unread data is dropped (when SlNetSock_recvFrom() len parameter < data size), Enable this option in order to read the left data on the next SlNetSock_recvFrom() iteration\n - Default: Disabled, IP boundary kept\n - This options takes SlNetSock_NonIpBoundary_t struct as parameter - - #SLNETSOCK_LVL_IP - - #SLNETSOCK_OPIP_MULTICAST_TTL\n - Set the time-to-live value of outgoing multicast packets for this socket. \n - This options takes uint8_t as parameter - - #SLNETSOCK_OPIP_ADD_MEMBERSHIP \n - UDP socket, Join a multicast group. \n - This options takes SlNetSock_IpMreq_t struct as parameter - - #SLNETSOCK_OPIP_DROP_MEMBERSHIP \n - UDP socket, Leave a multicast group \n - This options takes SlNetSock_IpMreq_t struct as parameter - - #SLNETSOCK_OPIP_HDRINCL \n - RAW socket only, the IPv4 layer generates an IP header when sending a packet unless \n - the IP_HDRINCL socket option is enabled on the socket. \n - When it is enabled, the packet must contain an IP header. \n - Default: disabled, IPv4 header generated by Network Stack \n - This options takes uint32_t as parameter - - #SLNETSOCK_OPIP_RAW_RX_NO_HEADER \n - Raw socket remove IP header from received data. \n - Default: data includes ip header \n - This options takes uint32_t as parameter - - #SLNETSOCK_OPIP_RAW_IPV6_HDRINCL (inactive) \n - RAW socket only, the IPv6 layer generates an IP header when sending a packet unless \n - the IP_HDRINCL socket option is enabled on the socket. When it is enabled, the packet must contain an IP header \n - Default: disabled, IPv4 header generated by Network Stack \n - This options takes uint32_t as parameter - - #SLNETSOCK_LVL_PHY - - #SLNETSOCK_OPPHY_CHANNEL \n - Sets channel in transceiver mode. - This options takes uint32_t as channel number parameter - - #SLNETSOCK_OPPHY_RATE \n - RAW socket, set WLAN PHY transmit rate \n - The values are based on SlWlanRateIndex_e \n - This options takes uint32_t as parameter - - #SLNETSOCK_OPPHY_TX_POWER \n - RAW socket, set WLAN PHY TX power \n - Valid rage is 1-15 \n - This options takes uint32_t as parameter - - #SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX \n - RAW socket, set number of frames to transmit in transceiver mode. - Default: 1 packet - This options takes uint32_t as parameter - - #SLNETSOCK_OPPHY_PREAMBLE \n - RAW socket, set WLAN PHY preamble for Long/Short\n - This options takes uint32_t as parameter - - #SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD \n - RAW socket, set WLAN Tx - Set CCA threshold. \n - The values are based on SlNetSockTxInhibitThreshold_e \n - This options takes uint32_t as parameter - - #SLNETSOCK_OPPHY_TX_TIMEOUT \n - RAW socket, set WLAN Tx - changes the TX timeout (lifetime) of transceiver frames. \n - Value in Ms, maximum value is 10ms \n - This options takes uint32_t as parameter - - #SLNETSOCK_OPPHY_ALLOW_ACKS \n - RAW socket, set WLAN Tx - Enable or Disable sending ACKs in transceiver mode \n - 0 = disabled / 1 = enabled \n - This options takes uint32_t as parameter - - #SLNETSOCK_PROTO_TCP - - #SLNETSOCK_TCP_NODELAY \n - Disables TCP send delay/coalesce algorithm. \n - This option takes SLNetSock_NoDelay_t struct as a parameter. - - #SLNETSOCK_TCP_MAXSEG \n - Set the maximum TCP segment size \n - This option takes SLNetSock_MaxSeg_t struct as a parameter. - - #SLNETSOCK_TCP_NOPUSH \n - Do not send data just to finish a data block (attempt to coalesce). \n - This option takes SLNetSock_NoPush_t struct as a parameter - - #SLNETSOCK_TCP_NOOPT \n - Do not use TCP options. \n - This option takes SLNetSock_NoOpt_t struct as a parameter. - - #SLNETSOCK_TCP_SACKPERMITTED \n - Permit RFC-2018 Selective Acknowledgment(SACK) conformant connection - This option takes SLNetSock_SackPermitted_t struct as a parameter - - #SLNETSOCK_TCP_MAXRTT \n - The maximum TCP Round Trip Time value allowed in the determination of the estimated TCP RTT. \n - This option takes SLNetSock_MaxRtt_t struct as a parameter - - \param[in] optval Specifies a value for the option - \param[in] optlen Specifies the length of the - option value - - \return Zero on success, or negative error code on failure - - \par Persistent - All params are Non- Persistent - - \slnetsock_init_precondition - - \par Examples - - - SLNETSOCK_OPSOCK_RCV_BUF: - \code - SlNetSock_Winsize_t size; - size.winsize = 3000; // bytes - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_BUF, (uint8_t *)&size, sizeof(size)); - \endcode -
- - - SLNETSOCK_OPSOCK_RCV_TIMEO: - \code - struct SlNetSock_Timeval_t timeVal; - timeVal.tv_sec = 1; // Seconds - timeVal.tv_usec = 0; // Microseconds. 10000 microseconds resolution - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_TIMEO, (uint8_t *)&timeVal, sizeof(timeVal)); // Enable receive timeout - \endcode -
- - - SLNETSOCK_OPSOCK_KEEPALIVE: //disable Keepalive - \code - SlNetSock_Keepalive_t enableOption; - enableOption.keepaliveEnabled = 0; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_KEEPALIVE, (uint8_t *)&enableOption, sizeof(enableOption)); - \endcode -
- - - SLNETSOCK_OPSOCK_KEEPALIVE_TIME: //Set Keepalive timeout - \code - int16_t Status; - uint32_t TimeOut = 120; - SlNetSock_setOpt(Sd, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_KEEPALIVE_TIME, (uint8_t *)&TimeOut, sizeof(TimeOut)); - \endcode -
- - - SLNETSOCK_OPSOCK_NON_BLOCKING: //Enable or disable nonblocking mode - \code - SlNetSock_Nonblocking_t enableOption; - enableOption.nonBlockingEnabled = 1; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_BLOCKING, (uint8_t *)&enableOption, sizeof(enableOption)); - \endcode -
- - - SLNETSOCK_OPSOCK_NON_IP_BOUNDARY: //disable boundary - \code - SlNetSock_NonIpBoundary_t enableOption; - enableOption.nonIpBoundaryEnabled = 1; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_IP_BOUNDARY, (uint8_t *)&enableOption, sizeof(enableOption)); - \endcode -
- - - SLNETSOCK_OPSOCK_LINGER: - \code - SlNetSock_linger_t linger; - linger.l_onoff = 1; - linger.l_linger = 10; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_LINGER, &linger, sizeof(linger)); - \endcode -
- - - SLNETSOCK_OPIP_MULTICAST_TTL: - \code - uint8_t ttl = 20; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_MULTICAST_TTL, &ttl, sizeof(ttl)); - \endcode -
- - - SLNETSOCK_OPIP_ADD_MEMBERSHIP: - \code - SlNetSock_IpMreq_t mreq; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_ADD_MEMBERSHIP, &mreq, sizeof(mreq)); - \endcode -
- - - SLNETSOCK_OPIP_DROP_MEMBERSHIP: - \code - SlNetSock_IpMreq_t mreq; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_DROP_MEMBERSHIP, &mreq, sizeof(mreq)); - \endcode -
- - - SLNETSOCK_OPIP_RAW_RX_NO_HEADER: - \code - uint32_t header = 1; // remove ip header - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_RAW_RX_NO_HEADER, &header, sizeof(header)); - \endcode -
- - - SLNETSOCK_OPIP_HDRINCL: - \code - uint32_t header = 1; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_HDRINCL, &header, sizeof(header)); - \endcode -
- - - SLNETSOCK_OPIP_RAW_IPV6_HDRINCL: - \code - uint32_t header = 1; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_IP, SLNETSOCK_OPIP_RAW_IPV6_HDRINCL, &header, sizeof(header)); - \endcode -
- - - SLNETSOCK_OPPHY_CHANNEL: - \code - uint32_t newChannel = 6; // range is 1-13 - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPPHY_CHANNEL, &newChannel, sizeof(newChannel)); - \endcode -
- - - SLNETSOCK_OPPHY_RATE: - \code - uint32_t rate = 6; // see wlan.h SlWlanRateIndex_e for values - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_RATE, &rate, sizeof(rate)); - \endcode -
- - - SLNETSOCK_OPPHY_TX_POWER: - \code - uint32_t txpower = 1; // valid range is 1-15 - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_POWER, &txpower, sizeof(txpower)); - \endcode -
- - - SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX: - \code - uint32_t numframes = 1; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_NUM_FRAMES_TO_TX, &numframes, sizeof(numframes)); - \endcode -
- - - SLNETSOCK_OPPHY_PREAMBLE: - \code - uint32_t preamble = 1; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_PREAMBLE, &preamble, sizeof(preamble)); - \endcode -
- - - SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD: - \code - uint32_t thrshld = SLNETSOCK_TX_INHIBIT_THRESHOLD_MED; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_INHIBIT_THRESHOLD, &thrshld, sizeof(thrshld)); - \endcode -
- - - SLNETSOCK_OPPHY_TX_TIMEOUT: - \code - uint32_t timeout = 50; - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_TX_TIMEOUT, &timeout, sizeof(timeout)); - \endcode -
- - - SLNETSOCK_OPPHY_ALLOW_ACKS: - \code - uint32_t acks = 1; // 0 = disabled / 1 = enabled - SlNetSock_setOpt(SockID, SLNETSOCK_LVL_PHY, SLNETSOCK_OPPHY_ALLOW_ACKS, &acks, sizeof(acks)); - \endcode - - \sa slNetSock_create() - \sa SlNetSock_getOpt() -*/ -int32_t SlNetSock_setOpt(int16_t sd, int16_t level, int16_t optname, void *optval, SlNetSocklen_t optlen); - - -/*! - \brief Get socket options - - The SlNetSock_getOpt function gets the options associated with a socket. - Options may exist at multiple protocol levels; they are always - present at the uppermost socket level. - - The parameters optval and optlen identify a - buffer in which the value for the requested option(s) are to - be returned. \c optlen is a value-result - parameter, initially containing the size of the buffer - pointed to by option_value, and modified on return to - indicate the actual size of the value returned. If no option - value is to be supplied or returned, \c optval may be \c NULL. - - - \param[in] sd Socket descriptor (handle) - \param[in] level Defines the protocol level for this option - \param[in] optname defines the option name to interrogate - \param[out] optval Specifies a value for the option - \param[out] optlen Specifies the length of the - option value - - \return Zero on success, or negative error code on failure - - \slnetsock_init_precondition - - \sa SlNetSock_create() - \sa SlNetSock_setOpt() -*/ -int32_t SlNetSock_getOpt(int16_t sd, int16_t level, int16_t optname, void *optval, SlNetSocklen_t *optlen); - - -/*! - \brief Read data from TCP socket - - The SlNetSock_recv function receives a message from a connection-mode socket - - \param[in] sd Socket descriptor (handle) - \param[out] buf Points to the buffer where the - message should be stored. - \param[in] len Specifies the length in bytes of - the buffer pointed to by the buffer argument. - Range: 1-16000 bytes - \param[in] flags Specifies the type of message - reception. On this version, this parameter is not - supported. - - \return Return the number of bytes received, - or a negative value if an error occurred.\n - Using a non-blocking recv a possible negative value is #SLNETERR_BSD_EAGAIN.\n - #SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - - \slnetsock_init_precondition - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetSock_recv snippet - - \sa SlNetSock_create() - \sa SlNetSock_recvFrom() -*/ -int32_t SlNetSock_recv(int16_t sd, void *buf, uint32_t len, uint32_t flags); - - -/*! - \brief Read data from socket - - SlNetSock_recvFrom function receives a message from a connection-mode or - connectionless-mode socket - - \param[in] sd Socket descriptor (handle) - \param[out] buf Points to the buffer where the message should be stored. - \param[in] len Specifies the length in bytes of the buffer pointed to by the buffer argument. - Range: 1-16000 bytes - \param[in] flags Specifies the type of message - reception. On this version, this parameter is not - supported - \param[in] from Pointer to an address structure - indicating the source - address.\n sockaddr:\n - code - for the address format.\n - socket address, - the length depends on the code - format - \param[in] fromlen Source address structure - size. This parameter MUST be set to the size of the structure pointed to by addr. - - - \return Return the number of bytes received, - or a negative value if an error occurred.\n - Using a non-blocking recv a possible negative value is #SLNETERR_BSD_EAGAIN. - #SLNETERR_RET_CODE_INVALID_INPUT will be returned if fromlen has incorrect length.\n - #SLNETERR_BSD_ENOMEM may be return in case there are no resources in the system - - \slnetsock_init_precondition - - \par Example - \snippet ti/net/test/snippets/slnetif.c SlNetSock_recvFrom snippet - - \sa SlNetSock_create() - \sa SlNetSock_recv() -*/ -int32_t SlNetSock_recvFrom(int16_t sd, void *buf, uint32_t len, uint32_t flags, SlNetSock_Addr_t *from, SlNetSocklen_t *fromlen); - - -/*! - \brief Write data to TCP socket - - Transmits a message to another socket. - Returns immediately after sending data to device. - In case of a RAW socket (transceiver mode), extra 4 bytes should be reserved at the end of the - frame data buffer for WLAN FCS - - \param[in] sd Socket descriptor (handle) - \param[in] buf Points to a buffer containing - the message to be sent - \param[in] len Message size in bytes. - \param[in] flags Specifies the type of message - transmission. On this version, this parameter is not - supported for TCP. - - \return Return the number of bytes sent, - or a negative value if an error occurred. - - \slnetsock_init_precondition - - \par Example - \snippet ti/net/test/snippets/slnetif.c SlNetSock_send snippet - - \sa SlNetSock_create() - \sa SlNetSock_sendTo() -*/ -int32_t SlNetSock_send(int16_t sd, const void *buf, uint32_t len, uint32_t flags); - - -/*! - \brief Write data to socket - - The SlNetSock_sendTo function is used to transmit a message on a connectionless socket - (connection less socket #SLNETSOCK_SOCK_DGRAM, #SLNETSOCK_SOCK_RAW). - - Returns immediately after sending data to device. - - \param[in] sd Socket descriptor (handle) - \param[in] buf Points to a buffer containing - the message to be sent - \param[in] len message size in bytes. - \param[in] flags Specifies the type of message - transmission. On this version, this parameter is not - supported - \param[in] to Pointer to an address structure - indicating the destination - address.\n sockaddr:\n - code - for the address format.\n - socket address, - the length depends on the code - format - \param[in] tolen Destination address structure size - - \return Return the number of bytes sent, - or a negative value if an error occurred.\n - - \slnetsock_init_precondition - - \par Example - \snippet ti/net/test/snippets/slnetif.c SlNetSock_sendTo snippet - - \sa SlNetSock_create() - \sa SlNetSock_send() -*/ -int32_t SlNetSock_sendTo(int16_t sd, const void *buf, uint32_t len, uint32_t flags, const SlNetSock_Addr_t *to, SlNetSocklen_t tolen); - - -/*! - \brief Get interface ID from socket descriptor (sd) - - \param[in] sd Specifies the socket descriptor which its - interface identifier needs to be retrieved.\n - - \return The interface identifier value of the - interface on success, or negative error code - on failure. The values of the interface - identifier is defined with the prefix - @c SLNETIF_ID_ in slnetif.h. - - \slnetsock_init_precondition - - \par Examples - \snippet ti/net/test/snippets/slnetif.c SlNetSock_getIfID snippet - - \sa SlNetSock_create() - \sa SlNetIf_add() - \sa SlNetIf_getIDByName() -*/ -int32_t SlNetSock_getIfID(uint16_t sd); - - -/*! - \brief Creates a security attributes object - - Create a security attribute, which is required in order to start a secure session. - - \remark When the security attributes object is no longer needed, call - SlNetSock_secAttribDelete() to destroy it. - - \remark A single security object can be used to initiate several secure - sessions (provided they all have the same security attributes). - - \slnetsock_init_precondition - - \sa SlNetSock_startSec() - \sa SlNetSock_secAttribDelete() -*/ -SlNetSockSecAttrib_t *SlNetSock_secAttribCreate(void); - - -/*! - \brief Deletes a security attributes object - - \param[in] secAttrib Secure attribute handle - - \return Zero on success, or negative error code - on failure - - \slnetsock_init_precondition - - \remark \c secAttrib must be created using SlNetSock_secAttribCreate() - - \sa SlNetSock_secAttribCreate() - \sa SlNetSock_secAttribSet() - \sa SlNetSock_startSec() -*/ -int32_t SlNetSock_secAttribDelete(SlNetSockSecAttrib_t *secAttrib); - - -/*! - \brief set a security attribute - - The SlNetSock_secAttribSet function is used to set a security - attribute of a security attribute object. - - \param[in] secAttrib Secure attribute handle - \param[in] attribName Define the actual attribute to set. Applicable values: - - #SLNETSOCK_SEC_ATTRIB_PRIVATE_KEY \n - Sets the private key corresponding to the local certificate \n - This attribute takes the name of security object containing the private key and the name's length (including the NULL terminating character) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_LOCAL_CERT \n - Sets the local certificate chain \n - This attribute takes the name of the security object containing the certificate and the name's length (including the NULL terminating character) as parameters \n - For certificate chains, each certificate in the chain can be added via a separate call to SlNetSock_secAttribSet, starting with the root certificate of the chain \n - - #SLNETSOCK_SEC_ATTRIB_PEER_ROOT_CA \n - Sets the root CA certificate \n - This attribute takes the name of the security object containing the certificate and the name's length (including the NULL terminating character) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_DH_KEY \n - Sets the DH Key \n - This attribute takes the name of the security object containing the DH Key and the name's length (including the NULL terminating character) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_METHOD \n - Sets the TLS protocol version \n - This attribute takes a SLNETSOCK_SEC_METHOD_* option and sizeof(uint8_t) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_CIPHERS \n - Sets the ciphersuites to be used for the connection \n - This attribute takes a bit mask formed using SLNETSOCK_SEC_CIPHER_* options and sizeof(uint32_t) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_ALPN \n - Sets the ALPN \n - This attribute takes a bit mask formed using SLNETSOCK_SEC_ALPN_* options and sizeof(uint32_t) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_EXT_CLIENT_CHLNG_RESP \n - Sets the EXT CLIENT CHLNG RESP \n - Format TBD \n - - #SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME \n - Sets the domain name for verification during connection \n - This attribute takes a string with the domain name and the string's length (including the NULL-terminating character) as parameters \n - - #SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE\n - Sets whether to disable the certificate store \n - This attribute takes 1 (disable) or 0 (enable) and sizeof(uint32_t) as parameters \n - - \param[in] val - \param[in] len - - \return Zero on success, or negative error code - on failure - - \slnetsock_init_precondition - - \note Once an attribute is set, it cannot be unset or set to something - different. Doing so may result in undefined behavior. - Instead, SlNetSock_secAttribDelete() should be called on the - existing object, and a new security object should be created with - the new attribute set. - - \note The #SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE value - is currently being evaluated, and may be removed in a - future release. It is currently only supported on CC3xxx - devices. - - \par Examples - - - SLNETSOCK_SEC_ATTRIB_PRIVATE_KEY: - \code - #define PRIVATE_KEY_FILE "DummyKey" - SlNetIf_loadSecObj(SLNETIF_SEC_OBJ_TYPE_RSA_PRIVATE_KEY, PRIVATE_KEY_FILE, strlen(PRIVATE_KEY_FILE), srvKeyPem, srvKeyPemLen, SLNETIF_ID_2); - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_PRIVATE_KEY, PRIVATE_KEY_FILE, sizeof(PRIVATE_KEY_FILE)); - \endcode -
- - - SLNETSOCK_SEC_ATTRIB_LOCAL_CERT: - \code - #define ROOT_CA_CERT_FILE "DummyCA" - #define TRUSTED_CERT_FILE "DummyTrustedCert" - - // create a local certificate chain - SlNetIf_loadSecObj(SLNETIF_SEC_OBJ_TYPE_CERTIFICATE, ROOT_CA_CERT_FILE, strlen(ROOT_CA_CERT_FILE), srvCAPem, srvCAPemLen, SLNETIF_ID_2); - SlNetIf_loadSecObj(SLNETIF_SEC_OBJ_TYPE_CERTIFICATE, TRUSTED_CERT_FILE, strlen(TRUSTED_CERT_FILE), srvCertPem, srvCertPemLen, SLNETIF_ID_2); - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_LOCAL_CERT, ROOT_CA_CERT_FILE, sizeof(ROOT_CA_CERT_FILE)); - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_LOCAL_CERT, TRUSTED_CERT_FILE, sizeof(TRUSTED_CERT_FILE)); - \endcode -
- - - SLNETSOCK_SEC_ATTRIB_PEER_ROOT_CA: - \code - #define ROOT_CA_CERT_FILE "DummyCA" - SlNetIf_loadSecObj(SLNETIF_SEC_OBJ_TYPE_CERTIFICATE, ROOT_CA_CERT_FILE, strlen(ROOT_CA_CERT_FILE), srvCAPem, srvCAPemLen, SLNETIF_ID_2); - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_PEER_ROOT_CA, ROOT_CA_CERT_FILE, sizeof(ROOT_CA_CERT_FILE)); - \endcode -
- - - SLNETSOCK_SEC_ATTRIB_METHOD: - \code - uint8_t SecurityMethod = SLNETSOCK_SEC_METHOD_SSLV3; - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_METHOD, (void *)&(SecurityMethod), sizeof(SecurityMethod)); - \endcode -
- - - SLNETSOCK_SEC_ATTRIB_CIPHERS: - \code - uint32_t SecurityCipher = SLNETSOCK_SEC_CIPHER_SSL_RSA_WITH_RC4_128_SHA | SLNETSOCK_SEC_CIPHER_TLS_RSA_WITH_AES_256_CBC_SHA; - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_METHOD, (void *)&(SecurityCipher), sizeof(SecurityCipher)); - \endcode -
- - - SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME: - \code - char addr[] = "www.ti.com"; - SlNetSock_secAttribSet(secAttrib, SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME, (void *)addr, strlen(addr) + 1); - \endcode -
- - - \sa SlNetSock_secAttribCreate() -*/ -int32_t SlNetSock_secAttribSet(SlNetSockSecAttrib_t *secAttrib, SlNetSockSecAttrib_e attribName, void *val, uint16_t len); - - -/*! - \brief Start a security session on an opened socket - - \param[in] sd Socket descriptor (handle) - \param[in] secAttrib Secure attribute handle. This can be NULL only - if the SLNETSOCK_SEC_BIND_CONTEXT_ONLY flag is - not thrown. - \param[in] flags Specifies flags. \n - The available flags are: - - #SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY - - #SLNETSOCK_SEC_BIND_CONTEXT_ONLY - - #SLNETSOCK_SEC_IS_SERVER - - \return Zero on success, or negative error code - on failure - - \slnetsock_init_precondition - - \remark If \c secAttrib is \c NULL, the session will be started with - default security settings. - - \sa SlNetSock_create() - \sa SlNetSock_secAttribCreate() -*/ -int32_t SlNetSock_startSec(int16_t sd, SlNetSockSecAttrib_t *secAttrib, uint8_t flags); - - -/*! - - Close the Doxygen group. - @} - -*/ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __NET_SOCK_H__ */ diff --git a/ext/hal/ti/simplelink/source/ti/net/slnetutils.c b/ext/hal/ti/simplelink/source/ti/net/slnetutils.c deleted file mode 100644 index da49ea6d918..00000000000 --- a/ext/hal/ti/simplelink/source/ti/net/slnetutils.c +++ /dev/null @@ -1,1510 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -#include /* needed? */ -#include -#include - -#include -#include -#include - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ - -#define SLNETUTIL_NORMALIZE_NEEDED 0 -#if SLNETUTIL_NORMALIZE_NEEDED - #define SLNETUTIL_NORMALIZE_RET_VAL(retVal,err) ((retVal < 0)?(retVal = err):(retVal)) -#else - #define SLNETUTIL_NORMALIZE_RET_VAL(retVal,err) -#endif - -/* Size needed for getaddrinfo mem allocation */ -#define SLNETUTIL_ADDRINFO_ALLOCSZ ((sizeof(SlNetUtil_addrInfo_t)) + \ - (sizeof(SlNetSock_AddrIn6_t))) - -/* Cap number of mem allocations in case of large number of results from DNS */ -#define SLNETUTIL_ADDRINFO_MAX_DNS_NODES 10 - -#define SLNETUTIL_DNSBUFSIZE ((SLNETUTIL_ADDRINFO_MAX_DNS_NODES) * \ - (sizeof(uint32_t))) - -#define LL_PREFIX 0xFE80 - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -static int32_t SlNetUtil_UTOA(uint16_t value, char * string, uint16_t base); -static int32_t SlNetUtil_bin2StrIpV4(SlNetSock_InAddr_t *binaryAddr, char *strAddr, uint16_t strAddrLen); -static int32_t SlNetUtil_bin2StrIpV6(SlNetSock_In6Addr_t *binaryAddr, char *strAddr, uint16_t strAddrLen); -static int32_t SlNetUtil_strTok(char **string, char *returnstring, const char *delimiter); -static int32_t SlNetUtil_str2BinIpV4(char *strAddr, SlNetSock_InAddr_t *binaryAddr); -static int32_t SlNetUtil_str2BinIpV6(char *strAddr, SlNetSock_In6Addr_t *binaryAddr); - -/* Local SlNetUtil_getAddrInfo utility functions */ -static SlNetUtil_addrInfo_t *setAddrInfo(uint16_t ifID, SlNetSock_Addr_t *addr, - int family, const char *service, const SlNetUtil_addrInfo_t *hints); - -static SlNetUtil_addrInfo_t *createAddrInfo(uint16_t ifID, - SlNetSock_Addr_t *addr, int family, const char *service, int flags, - int socktype, int protocol); - -static int mergeLists(SlNetUtil_addrInfo_t **curList, - SlNetUtil_addrInfo_t **newList); - -//***************************************************************************** -// -// SlNetUtil_init - Initialize the slnetutil module -// -//***************************************************************************** -int32_t SlNetUtil_init(int32_t flags) -{ - return 0; -} - - -//***************************************************************************** -// SlNetUtil_gaiStrErr -//***************************************************************************** - -/* - * Error codes for gai_strerror - * The order of this array MUST match the numbering of the SLNETUTIL_EAI_CODE - * defines in - */ -static const char *strErrorMsgs[] = -{ - "Temporary failure in name resolution", /* SLNETUTIL_EAI_AGAIN */ - "Bad value for ai_flags", /* SLNETUTIL_EAI_BADFLAGS */ - "Non-recoverable failure in name resolution", /* SLNETUTIL_EAI_FAIL */ - "ai_family not supported", /* SLNETUTIL_EAI_FAMILY */ - "Memory allocation failure", /* SLNETUTIL_EAI_MEMORY */ - "Node or service not known, " /* SLNETUTIL_EAI_NONAME */ - "or both node and service are NULL", - "Service (port number) not supported " /* SLNETUTIL_EAI_SERVICE */ - "for ai_socktype", - "ai_socktype not supported", /* SLNETUTIL_EAI_SOCKTYPE */ - "System error", /* SLNETUTIL_EAI_SYSTEM */ - "An argument buffer overflowed", /* SLNETUTIL_EAI_OVERFLOW */ - "Address family for node not supported" /* SLNETUTIL_EAI_ADDRFAMILY */ -}; - -const char *SlNetUtil_gaiStrErr(int32_t errorCode) -{ - /* - * Error codes are negative starting with -3121 so - * ~(errorCode - SLNETUTIL_EAI_BASE) takes the one's compliment of the code - * minus the base of the error codes to convert the code into a positive - * value that matches the StrerrorMsgs array index. - */ - int msgsIndex = ~(errorCode - SLNETUTIL_EAI_BASE); - int msgsRange = sizeof(strErrorMsgs) / sizeof(strErrorMsgs[0]); - - if ((msgsIndex < msgsRange) && (msgsIndex >= 0)) - { - return strErrorMsgs[msgsIndex]; - } - else - { - return "Unknown error"; - } -} - -//***************************************************************************** -// -// SlNetUtil_getHostByName - Obtain the IP Address of machine on network, by -// machine name -// -//***************************************************************************** -int32_t SlNetUtil_getHostByName(uint32_t ifBitmap, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family) -{ - uint16_t origIpAddrLen; - SlNetIf_t *netIf; - int32_t retVal; - - /* When ifBitmap is 0, that means automatic selection of all interfaces - is required, enable all bits in ifBitmap */ - if (0 == ifBitmap) - { - ifBitmap = ~ifBitmap; - } - - /* - * Save original value of ipAddrLen. If DNS resolution fails, ipAddrLen - * will be overwritten with zero, which is problematic for next iteration - * of the while loop. - */ - origIpAddrLen = *ipAddrLen; - - /* This loop tries to run get host by name on the required interface - only if it in state enable and connected status - When multiple interfaces, in addition to the enable and connected it - will try to run the function on the interface from the highest - priority until an answer will return or until no interfaces left */ - do - { - /* Search for the highest priority interface according to the - ifBitmap and the queryFlags */ - netIf = SlNetIf_queryIf(ifBitmap, SLNETIF_QUERY_IF_STATE_BIT | SLNETIF_QUERY_IF_CONNECTION_STATUS_BIT); - - /* Check if the function returned NULL or the requested interface - exists */ - if ( (NULL == netIf) || ( NULL == (netIf->ifConf)->utilGetHostByName) ) - { - /* Interface doesn't exists, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - else - { - /* Disable the ifID bit from the ifBitmap after finding the netIf*/ - ifBitmap &= ~(netIf->ifID); - - /* Interface exists, return interface IP address */ - retVal = (netIf->ifConf)->utilGetHostByName(netIf->ifContext, name, nameLen, ipAddr, ipAddrLen, family); - SLNETUTIL_NORMALIZE_RET_VAL(retVal, SLNETUTIL_ERR_UTILGETHOSTBYNAME_FAILED); - - /* Check retVal for error codes */ - if (retVal < SLNETERR_RET_CODE_OK) - { - /* - * utilGetHostByName failed. Restore the size of the ipAddr - * array and continue to the next ifID - */ - *ipAddrLen = origIpAddrLen; - continue; - } - else - { - /* Return success */ - return netIf->ifID; - } - } - }while ( ifBitmap > 0 ); - /* Interface doesn't exists, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; -} - -//***************************************************************************** -// SlNetUtil_getAddrInfo -//***************************************************************************** -int32_t SlNetUtil_getAddrInfo(uint16_t ifID, const char *node, - const char *service, const struct SlNetUtil_addrInfo_t *hints, - struct SlNetUtil_addrInfo_t **res) -{ - int i; - int retval = 0; - int resolved = 0; - int numNodes = 0; - char *buffer = NULL; - char *currAddr = NULL; - uint16_t numIpAddrs; - int32_t selectedIfId; - int32_t ipv4DnsError = 0; - int32_t ipv6DnsError = 0; - - SlNetUtil_addrInfo_t *ai = NULL; - SlNetUtil_addrInfo_t *aiTmp = NULL; - SlNetSock_AddrIn_t sin; - SlNetSock_AddrIn6_t sin6; - - /* check args passed in for errors */ - if (!node && !service) { - /* Error: node and service args cannot both be NULL */ - return (SLNETUTIL_EAI_NONAME); - } - - if (!service) { - service = "0"; - } - - if (!res) { - /* Error: res cannot be NULL */ - return (SLNETUTIL_EAI_NONAME); - } - - if (!hints) { - /* User passed NULL hints. Create a hints for them with all 0 values */ - static const SlNetUtil_addrInfo_t defHints = { - 0, /* ai_flags */ - SLNETSOCK_AF_UNSPEC, /* ai_family */ - 0, /* ai_socktype */ - 0, /* ai_protocol */ - 0, /* ai_addrlen */ - NULL, /* ai_addr */ - NULL, /* ai_canonname */ - NULL /* ai_next */ - }; - hints = &defHints; - } - else { - /* Check the user's hints for invalid settings */ - if (hints->ai_socktype != SLNETSOCK_SOCK_STREAM && - hints->ai_socktype != SLNETSOCK_SOCK_DGRAM && - hints->ai_socktype != 0) { - /* Error: invalid or unknown socktype */ - return (SLNETUTIL_EAI_SOCKTYPE); - } - else if (hints->ai_protocol != SLNETSOCK_PROTO_TCP && - hints->ai_protocol != SLNETSOCK_PROTO_UDP && - hints->ai_protocol != 0) { - /* Error: invalid or unknown protocol */ - return (SLNETUTIL_EAI_SOCKTYPE); - } - else if ((hints->ai_family != SLNETSOCK_AF_INET) && - (hints->ai_family != SLNETSOCK_AF_INET6) && - (hints->ai_family != SLNETSOCK_AF_UNSPEC)) { - /* Error: invalid or unknown family */ - return (SLNETUTIL_EAI_FAMILY); - } - } - - if (node) { - /* - * Client case. User needs an address structure to call connect() with. - * - * Determine what caller has passed to us for 'node'. Should be either: - * - an IPv4 address - * - an IPv6 address - * - or a hostname - */ - - /* Test if 'node' is an IPv4 address */ - retval = SlNetUtil_inetAton(node, &(sin.sin_addr)); - if (retval) { - /* Ensure address family matches */ - if (hints->ai_family != SLNETSOCK_AF_INET && - hints->ai_family != SLNETSOCK_AF_UNSPEC) { - return (SLNETUTIL_EAI_ADDRFAMILY); - } - - /* - * Create addrinfo struct(s) containing this IPv4 address. If ai - * is NULL, this will be caught at end of getaddrinfo - * - * Pass zero for IF ID. This is a don't care for the case of node - * being set to an IPv4 address - */ - ai = setAddrInfo(0, (SlNetSock_Addr_t *)&sin, SLNETSOCK_AF_INET, - service, hints); - } - else { - /* 'node' is either an IPv6 address or a hostname (or invalid) */ - - /* Test if 'node' is an IPv6 address */ - retval = SlNetUtil_inetPton(SLNETSOCK_AF_INET6, node, - &(sin6.sin6_addr)); - if (retval > 0) { - /* Ensure address family matches */ - if (hints->ai_family != SLNETSOCK_AF_INET6 && - hints->ai_family != SLNETSOCK_AF_UNSPEC) { - return (SLNETUTIL_EAI_ADDRFAMILY); - } - - /* - * If we were given a link local address and corresponding IF, - * pass the IF number through. It must be used for the scope ID - */ - if ((SlNetUtil_ntohs(sin6.sin6_addr._S6_un._S6_u16[0]) == - LL_PREFIX) && ifID != 0) { - selectedIfId = ifID; - } - else { - /* - * Set scope ID to zero for these cases: - * - Link local addr and ifID == 0: - * (caller responsibe for setting scope ID) - * - * - Non-local addr with ifID == 0: - * - Non-local addr with ifID == 1: - * scope ID not used and should be set to 0 - */ - selectedIfId = 0; - } - - /* - * Create addrinfo struct(s) containing this IPv6 address. If - * ai is NULL, this will be caught at end of getaddrinfo - */ - ai = setAddrInfo(selectedIfId, (SlNetSock_Addr_t *)&sin6, - SLNETSOCK_AF_INET6, service, hints); - } - else { - /* Test if 'node' is a host name. Use DNS to resolve it. */ - - /* - * Per RFC 2553, if node is not a valid numeric address string - * and AI_NUMERICHOST is set, return error (and prevent call to - * DNS). - */ - if (hints->ai_flags & SLNETUTIL_AI_NUMERICHOST) { - return (SLNETUTIL_EAI_NONAME); - } - - buffer = malloc(SLNETUTIL_DNSBUFSIZE); - if (!buffer) { - /* Error: couldn't alloc DNS buffer */ - return (SLNETUTIL_EAI_MEMORY); - } - - /* IPv4 DNS lookup */ - if (hints->ai_family == SLNETSOCK_AF_INET || - hints->ai_family == SLNETSOCK_AF_UNSPEC) { - /* - * Set the size of the buffer to the number of 32-bit IPv4 - * addresses this buffer can hold - */ - numIpAddrs = SLNETUTIL_DNSBUFSIZE / sizeof(uint32_t); - - selectedIfId = SlNetUtil_getHostByName(ifID, (char *)node, - strlen(node), (uint32_t *)buffer, &numIpAddrs, - SLNETSOCK_AF_INET); - - if (selectedIfId > 0) { - - /* - * Process the results returned by DNS. Upon success, - * numIpAddrs contains the number of IP addresses stored - * into the buffer - */ - resolved = 1; - currAddr = buffer; - for (i = 0; i < numIpAddrs && - numNodes < SLNETUTIL_ADDRINFO_MAX_DNS_NODES; - i++) { - sin.sin_addr.s_addr = - SlNetUtil_htonl(*((uint32_t *)currAddr)); - /* - * Create addrinfo struct(s) containing this IPv4 - * address. This can return a list with multiple - * nodes, depending on hints provided. Empty lists - * are handled before returning. - * - * Pass zero for IF ID. This is a don't care for - * the case of node being set to an IPv4 address. - */ - aiTmp = setAddrInfo(0, (SlNetSock_Addr_t *)&sin, - SLNETSOCK_AF_INET, service, hints); - - if (aiTmp) { - /* - * Merge the results into the main list - * for each loop iteration: - */ - numNodes += mergeLists(&ai, &aiTmp); - } - - /* move to the next IPv4 address */ - currAddr += sizeof(uint32_t); - } - } - else { - /* save the IPv4 error code */ - ipv4DnsError = selectedIfId; - } - } - - /* IPv6 DNS lookup */ - if (hints->ai_family == SLNETSOCK_AF_INET6 || - hints->ai_family == SLNETSOCK_AF_UNSPEC) { - /* - * Set the size of the buffer to the number of 128-bit IPv6 - * addresses this buffer can hold - */ - numIpAddrs = - SLNETUTIL_DNSBUFSIZE / sizeof(SlNetSock_In6Addr_t); - - selectedIfId = SlNetUtil_getHostByName(ifID, (char *)node, - strlen(node), (uint32_t *)buffer, &numIpAddrs, - SLNETSOCK_AF_INET6); - - if (selectedIfId > 0) { - - /* - * Process the results returned by DNS. Upon success, - * numIpAddrs contains the number of IP addresses stored - * into the buffer - */ - resolved = 1; - currAddr = buffer; - for (i = 0; i < numIpAddrs && - numNodes < SLNETUTIL_ADDRINFO_MAX_DNS_NODES; - i++) { - - /* Copy the IPv6 address out of the buffer */ - memcpy(&(sin6.sin6_addr), currAddr, - sizeof(SlNetSock_In6Addr_t)); - - /* - * Is this address non-local? If so, IF ID is a - * don't care - */ - if (sin6.sin6_addr._S6_un._S6_u16[0] != LL_PREFIX) { - selectedIfId = 0; - } - - /* Change byte ordering to net byte order */ - sin6.sin6_addr._S6_un._S6_u16[0] = SlNetUtil_htons( - sin6.sin6_addr._S6_un._S6_u16[0]); - sin6.sin6_addr._S6_un._S6_u16[1] = SlNetUtil_htons( - sin6.sin6_addr._S6_un._S6_u16[1]); - sin6.sin6_addr._S6_un._S6_u16[2] = SlNetUtil_htons( - sin6.sin6_addr._S6_un._S6_u16[2]); - sin6.sin6_addr._S6_un._S6_u16[3] = SlNetUtil_htons( - sin6.sin6_addr._S6_un._S6_u16[3]); - sin6.sin6_addr._S6_un._S6_u16[4] = SlNetUtil_htons( - sin6.sin6_addr._S6_un._S6_u16[4]); - sin6.sin6_addr._S6_un._S6_u16[5] = SlNetUtil_htons( - sin6.sin6_addr._S6_un._S6_u16[5]); - sin6.sin6_addr._S6_un._S6_u16[6] = SlNetUtil_htons( - sin6.sin6_addr._S6_un._S6_u16[6]); - sin6.sin6_addr._S6_un._S6_u16[7] = SlNetUtil_htons( - sin6.sin6_addr._S6_un._S6_u16[7]); - - /* - * Create addrinfo struct(s) containing this IPv6 - * address. This can return a list with multiple - * nodes, depending on hints provided. Empty lists - * are handled before returning. - * - * Pass down the appropriate IF number or zero, - * depending on whether this address is - * local or not - */ - - aiTmp = setAddrInfo(selectedIfId, - (SlNetSock_Addr_t *)&sin6, - SLNETSOCK_AF_INET6, service, hints); - - if (aiTmp) { - /* - * Merge the results into the main list - * for each loop iteration: - */ - numNodes += mergeLists(&ai, &aiTmp); - } - - /* move to the next IPv6 address */ - currAddr += sizeof(SlNetSock_In6Addr_t); - } - } - else { - /* save the IPv6 error code */ - ipv6DnsError = selectedIfId; - } - } - - free(buffer); - - if (!resolved) { - /* - * Error: couldn't resolve host name - * Translate the SlNetSock error code to a GAI error code. - * Give the IPv4 error precedence: - */ - retval = (ipv4DnsError != 0) ? ipv4DnsError : ipv6DnsError; - - switch (retval) { - case SLNETERR_NET_APP_DNS_ALLOC_ERROR: - retval = SLNETUTIL_EAI_MEMORY; - break; - case SLNETERR_NET_APP_DNS_INVALID_FAMILY_TYPE: - retval = SLNETUTIL_EAI_FAMILY; - break; - case SLNETERR_NET_APP_DNS_IPV6_REQ_BUT_IPV6_DISABLED: - retval = SLNETUTIL_EAI_SERVICE; - break; - case SLNETERR_NET_APP_DNS_PARAM_ERROR: - case SLNETERR_NET_APP_DNS_QUERY_FAILED: - default: - retval = SLNETUTIL_EAI_FAIL; - break; - } - return (retval); - } - } - } - } - else { - /* Server case. User needs an address structure to call bind() with. */ - if (hints->ai_family == SLNETSOCK_AF_INET || - hints->ai_family == SLNETSOCK_AF_UNSPEC) { - if (hints->ai_flags & SLNETUTIL_AI_PASSIVE) { - /* Per RFC 2553, accept connections on any IF */ - sin.sin_addr.s_addr = SlNetUtil_htonl(SLNETSOCK_INADDR_ANY); - } - else { - /* Per RFC 2553, accept connections on loopback IF */ - retval = SlNetUtil_inetPton(SLNETSOCK_AF_INET, "127.0.0.1", - &(sin.sin_addr.s_addr)); - if (retval <= 0) { - return (SLNETUTIL_EAI_SYSTEM); - } - } - - /* - * Create addrinfo struct(s) containing this IPv4 address. If ai - * is NULL, this will be caught at end of getaddrinfo - * - * Pass zero for IF ID. This is a don't care for - * the case of setting up a server socket. - */ - ai = setAddrInfo(0, (SlNetSock_Addr_t *)&sin, - SLNETSOCK_AF_INET, service, hints); - } - - if (hints->ai_family == SLNETSOCK_AF_INET6 || - hints->ai_family == SLNETSOCK_AF_UNSPEC) { - if (hints->ai_flags & SLNETUTIL_AI_PASSIVE) { - /* - * Per RFC 2553, accept connections on any IF - * (The IPv6 unspecified address is all zeroes) - */ - /* TODO: use in6addr_any, once available (NS-84) */ - memset(&(sin6.sin6_addr), 0, sizeof(SlNetSock_In6Addr_t)); - } - else { - /* - * Per RFC 2553, accept connections on loopback IF - * (The IPv6 loopback address is a 1 preceded by all zeroes) - */ - /* TODO: use in6addr_loopback, once available (NS-84) */ - sin6.sin6_addr._S6_un._S6_u32[0] = 0; - sin6.sin6_addr._S6_un._S6_u32[1] = 0; - sin6.sin6_addr._S6_un._S6_u32[2] = 0; - sin6.sin6_addr._S6_un._S6_u32[3] = SlNetUtil_htonl(1); - } - - /* - * Create addrinfo struct(s) containing this IPv6 address. If ai - * is NULL, this will be caught at end of getaddrinfo - * - * Pass zero for IF ID. This is a don't care for - * the case of setting up a server socket. - */ - aiTmp = setAddrInfo(0, (SlNetSock_Addr_t *)&sin6, - SLNETSOCK_AF_INET6, service, hints); - - if (aiTmp) { - /* - * The current list (ai) may not be empty. Merge the new - * results (aiTmp) into the existing ai to handle this case. - */ - mergeLists(&ai, &aiTmp); - } - } - } - - /* Give user our allocated and initialized addrinfo struct(s) */ - *res = ai; - - if (!ai) { - /* Our list is empty - memory allocations failed */ - return (SLNETUTIL_EAI_MEMORY); - } - - return (0); -} - -//***************************************************************************** -// SlNetUtil_freeAddrInfo -//***************************************************************************** -void SlNetUtil_freeAddrInfo(struct SlNetUtil_addrInfo_t *res) -{ - SlNetUtil_addrInfo_t *aiTmp; - - /* Delete all nodes in linked list */ - while (res) { - aiTmp = res->ai_next; - free((void *)res); - res = aiTmp; - } -} - -//***************************************************************************** -// setAddrInfo -// Intermediate step to handle permutations of ai_socktype and ai_protocol -// hints fields, passed by the user. If both socktype and protocol are 0, must -// create a results struct for each socktype and protocol. -// Returns an empty list (NULL) or a list with one or more nodes. -//***************************************************************************** -static SlNetUtil_addrInfo_t *setAddrInfo(uint16_t ifID, SlNetSock_Addr_t *addr, - int family, const char *service, - const SlNetUtil_addrInfo_t *hints) -{ - SlNetUtil_addrInfo_t *ai = NULL; - SlNetUtil_addrInfo_t *aiTmp = NULL; - - if ((hints->ai_socktype == 0 && hints->ai_protocol == 0) || - (hints->ai_socktype == 0 && hints->ai_protocol == SLNETSOCK_PROTO_UDP) - || (hints->ai_socktype == SLNETSOCK_SOCK_DGRAM && - hints->ai_protocol == 0) || (hints->ai_socktype == SLNETSOCK_SOCK_DGRAM - && hints->ai_protocol == SLNETSOCK_PROTO_UDP)) { - - ai = createAddrInfo(ifID, addr, family, service, hints->ai_flags, - SLNETSOCK_SOCK_DGRAM, SLNETSOCK_PROTO_UDP); - } - - if ((hints->ai_socktype == 0 && hints->ai_protocol == 0) || - (hints->ai_socktype == 0 && hints->ai_protocol == SLNETSOCK_PROTO_TCP) - || (hints->ai_socktype == SLNETSOCK_SOCK_STREAM && - hints->ai_protocol == 0) || (hints->ai_socktype == SLNETSOCK_SOCK_STREAM - && hints->ai_protocol == SLNETSOCK_PROTO_TCP)) { - - aiTmp = createAddrInfo(ifID, addr, family, service, hints->ai_flags, - SLNETSOCK_SOCK_STREAM, SLNETSOCK_PROTO_TCP); - - if (aiTmp) { - /* Insert into front of list (assume UDP node was added above) */ - aiTmp->ai_next = ai; - ai = aiTmp; - } - } - - return (ai); -} - -//***************************************************************************** -// createAddrInfo -// Create new address info structure. Returns a single node. -//***************************************************************************** -static SlNetUtil_addrInfo_t *createAddrInfo(uint16_t ifID, - SlNetSock_Addr_t *addr, int family, const char *service, int flags, - int socktype, int protocol) -{ - SlNetUtil_addrInfo_t *ai = NULL; - - /* - * Allocate memory for the addrinfo struct, which we must fill out and - * return to the caller. This struct also has a pointer to a generic socket - * address struct, which will point to either struct sockaddr_in, or - * struct sockaddr_in6, depending. Need to allocate enough space to hold - * that struct, too. - */ - ai = (SlNetUtil_addrInfo_t *)calloc(1, SLNETUTIL_ADDRINFO_ALLOCSZ); - if (!ai) { - /* Error: memory allocation failed */ - return (NULL); - } - - ai->ai_flags = flags; - ai->ai_socktype = socktype; - ai->ai_protocol = protocol; - ai->ai_canonname = NULL; - ai->ai_next = NULL; - - /* Store socket addr struct after the addrinfo struct in our memory block */ - ai->ai_addr = (SlNetSock_Addr_t *)(ai + 1); - - if (family == SLNETSOCK_AF_INET) { - /* Fill in structure for IPv4 */ - ai->ai_family = SLNETSOCK_AF_INET; - ai->ai_addrlen = sizeof(SlNetSock_AddrIn_t); - - /* Write values to addrinfo's socket struct as an sockaddr_in struct */ - ((SlNetSock_AddrIn_t *)ai->ai_addr)->sin_family = SLNETSOCK_AF_INET; - - ((SlNetSock_AddrIn_t *)ai->ai_addr)->sin_port = - SlNetUtil_htons(atoi(service)); - - ((SlNetSock_AddrIn_t *)ai->ai_addr)->sin_addr = - ((SlNetSock_AddrIn_t *)addr)->sin_addr; - } - else { - /* Fill in structure for IPv6 */ - ai->ai_family = SLNETSOCK_AF_INET6; - ai->ai_addrlen = sizeof(SlNetSock_AddrIn6_t); - - /* Write values to addrinfo's socket struct as an sockaddr_in6 struct */ - ((SlNetSock_AddrIn6_t *)ai->ai_addr)->sin6_family = SLNETSOCK_AF_INET6; - - ((SlNetSock_AddrIn6_t *)ai->ai_addr)->sin6_port = - SlNetUtil_htons(atoi(service)); - - memcpy(&(((SlNetSock_AddrIn6_t *)ai->ai_addr)->sin6_addr), - &(((SlNetSock_AddrIn6_t *)addr)->sin6_addr), - sizeof(SlNetSock_In6Addr_t)); - - /* Scope ID should have been determined correctly by the caller */ - ((SlNetSock_AddrIn6_t *)ai->ai_addr)->sin6_scope_id = (uint32_t)ifID; - } - - return (ai); -} - -//***************************************************************************** -// mergeLists -// Combines an existing linked list of addrinfo structs (curList) and a newly -// obtained list (newList) into a single list. If the existing list is empty, -// it will be initialized to the new list. If both lists are empty, no action -// is taken. -//***************************************************************************** -static int mergeLists(SlNetUtil_addrInfo_t **curList, - SlNetUtil_addrInfo_t **newList) -{ - int numNodes = 0; - SlNetUtil_addrInfo_t *tail = NULL; - - /* Check params */ - if (!curList || !newList || !(*newList)) { - return (numNodes); - } - - /* Update node count & find end of new list */ - for (tail = *newList; tail != NULL;) { - numNodes++; - if (tail->ai_next != NULL) { - /* Not the tail, keep traversing */ - tail = tail->ai_next; - } - else { - /* Tail found, quit loop */ - break; - } - } - - /* Append current list to end of new list */ - tail->ai_next = *curList; - *curList = *newList; - - return (numNodes); -} - -//***************************************************************************** -// -// SlNetUtil_htonl - Reorder the bytes of a 32-bit unsigned value from host -// order to network order(Big endian) -// -//***************************************************************************** -uint32_t SlNetUtil_htonl(uint32_t val) -{ - uint32_t i = 1; - int8_t *p = (int8_t *)&i; - - /* When the LSB of i stored in the smallest address of *p */ - if (p[0] == 1) /* little endian */ - { - /* Swap the places of the value */ - p[0] = ((int8_t *)&val)[3]; - p[1] = ((int8_t *)&val)[2]; - p[2] = ((int8_t *)&val)[1]; - p[3] = ((int8_t *)&val)[0]; - - /* return the reordered bytes */ - return i; - } - else /* big endian */ - { - /* return the input without any changes */ - return val; - } -} - - -//***************************************************************************** -// -// SlNetUtil_ntohl - Reorder the bytes of a 32-bit unsigned value from network -// order(Big endian) to host order -// -//***************************************************************************** -uint32_t SlNetUtil_ntohl(uint32_t val) -{ - /* return the reordered bytes */ - return SlNetUtil_htonl(val); -} - - -//***************************************************************************** -// -// SlNetUtil_htons - Reorder the bytes of a 16-bit unsigned value from host -// order to network order(Big endian) -// -//***************************************************************************** -uint16_t SlNetUtil_htons(uint16_t val) -{ - int16_t i = 1; - int8_t *p = (int8_t *)&i; - - /* When the LSB of i stored in the smallest address of *p */ - if (p[0] == 1) /* little endian */ - { - /* Swap the places of the value */ - p[0] = ((int8_t *)&val)[1]; - p[1] = ((int8_t *)&val)[0]; - - /* return the reordered bytes */ - return (uint16_t)i; - } - else /* big endian */ - { - /* return the input without any changes */ - return val; - } -} - - -//***************************************************************************** -// -// SlNetUtil_ntohs - Reorder the bytes of a 16-bit unsigned value from network -// order(Big endian) to host order -// -//***************************************************************************** -uint16_t SlNetUtil_ntohs(uint16_t val) -{ - /* return the reordered bytes */ - return SlNetUtil_htons(val); -} - -//***************************************************************************** -// -// SlNetUtil_UTOA - converts unsigned 16 bits binary number to string with -// maximum of 4 characters + 1 NULL terminated -// -//***************************************************************************** -static int32_t SlNetUtil_UTOA(uint16_t value, char * string, uint16_t base) -{ - uint16_t Index = 4; - char tempString[5] = { 0 }; - char * ptempString = tempString; - char * pString = string; - - /* Check if the inputs valid */ - if ( (NULL == string) || ((base < 2 ) && (base > 16 )) ) - { - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* If value is zero, that means that the returned string needs to be zero*/ - if (0 == value) - { - *ptempString = '0'; - ptempString++; - Index--; - } - - /* Run until all value digits are 0 or until Index get to 0 */ - for (; (value && (Index > 0)); Index--, value /= base) - { - *ptempString = "0123456789abcdef"[value % base]; - ptempString++; - } - /* Invalid value input */ - if (0 != value) - { - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* Reverse the string and initialize temporary array */ - while (Index < 4) - { - *(pString++) = *(--ptempString); - *ptempString = '\0'; - *pString = '\0'; - Index++; - } - - return 0; -} - -//***************************************************************************** -// -// SlNetUtil_bin2StrIpV4 - converts IPv4 address in binary representation -// (network byte order) to IP address in string -// representation -// -//***************************************************************************** -static int32_t SlNetUtil_bin2StrIpV4(SlNetSock_InAddr_t *binaryAddr, char *strAddr, uint16_t strAddrLen) -{ - uint8_t tempOctet; - uint32_t tempBinAddr; - int32_t octetIndex = 0; - char tempStrOctet[4] = { 0 }; - - /* Check if the strAddr buffer is at least in the minimum required size */ - if (strAddrLen < SLNETSOCK_INET_ADDRSTRLEN) - { - /* Return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* initialize strAddr to an empty string (so we can strcat() later) */ - strAddr[0] = '\0'; - - /* Copy the address value for further use */ - memcpy(&tempBinAddr, binaryAddr, sizeof(SlNetSock_InAddr_t)); - - /* Run over all octets (in network byte order), starting with the - most significant octet and ending with the least significant octet */ - while ( octetIndex <= 3 ) - { - /* Save octet on tempOctet for further usage. - When converting from binary representation to string - representation, the MSO of the binary number is the first char - of the string, so it needs to copied to the first location of - the array */ - tempOctet = ((int8_t *)&tempBinAddr)[octetIndex]; - - /* Initialize the octet for validation after copying the value */ - ((int8_t *)&tempBinAddr)[octetIndex] = 0; - - /* Convert tempOctet to string */ - SlNetUtil_UTOA(tempOctet, tempStrOctet, 10); - - /* Appends the tempStrOctet to strAddr */ - strcat(strAddr, tempStrOctet); - - /* Appends the "." to strAddr for the first 3 octets */ - if ( octetIndex < 3) - { - strcat(strAddr, "."); - } - - /* Move to the next octet */ - octetIndex ++; - - } - - /* Check if the address had only 4 octets, this was done by initializing - each octet that was copied and than checking if the number equal to 0 */ - if ( 0 == tempBinAddr ) - { - /* Return success */ - return SLNETERR_RET_CODE_OK; - } - else - { - /* Return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } -} - - -//***************************************************************************** -// -// SlNetUtil_bin2StrIpV6 - converts IPv6 address in binary representation to -// IP address in string representation -// -//***************************************************************************** -static int32_t SlNetUtil_bin2StrIpV6(SlNetSock_In6Addr_t *binaryAddr, char *strAddr, uint16_t strAddrLen) -{ - uint16_t tempHextet; - int32_t hextetIndex = 0; - uint8_t tempBinAddr[16] = { 0 }; - char tempStrHextet[5] = { 0 }; - - /* Check if the strAddr buffer is at least in the minimum required size */ - if (strAddrLen < SLNETSOCK_INET6_ADDRSTRLEN) - { - /* Return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* initialize strAddr to an empty string (so we can strcat() later) */ - strAddr[0] = '\0'; - - /* Copy the address value for further use */ - memcpy(tempBinAddr, binaryAddr, sizeof(SlNetSock_In6Addr_t)); - - /* Run over all octets, from the latest hextet (the most significant - hextet) until the first one (the least significant hextet) */ - while (hextetIndex < 8) - { - /* Save hextet on tempHextet for further usage. - When converting from binary representation to string - representation, the most significant hextet of the binary number - is the first char of the string, so it needs to copied to the - first location of the array */ - tempHextet = (tempBinAddr[hextetIndex * 2] << 8) | - (tempBinAddr[(hextetIndex * 2) + 1]); - - /* Convert tempHextet to string */ - SlNetUtil_UTOA(tempHextet, tempStrHextet, 16); - - /* Appends the tempStrHextet to strAddr */ - strcat(strAddr, tempStrHextet); - - /* Appends the ":" after each hextet (without the last one) */ - if (hextetIndex < 7) - { - strcat(strAddr, ":"); - } - - /* Move to the next hextet */ - hextetIndex++; - - } - - /* Return success */ - return SLNETERR_RET_CODE_OK; -} - - -//***************************************************************************** -// -// SlNetUtil_inetNtop - converts IP address in binary representation to IP -// address in string representation -// -//***************************************************************************** -const char *SlNetUtil_inetNtop(int16_t addrFamily, const void *binaryAddr, char *strAddr, SlNetSocklen_t strAddrLen) -{ - int32_t retVal; - - /* Switch according to the address family */ - switch(addrFamily) - { - case SLNETSOCK_AF_INET: - /* Convert from IPv4 string to numeric/binary representation */ - retVal = SlNetUtil_bin2StrIpV4((SlNetSock_InAddr_t *)binaryAddr, strAddr, strAddrLen); - - break; - case SLNETSOCK_AF_INET6: - /* Convert from IPv6 string to numeric/binary representation */ - retVal = SlNetUtil_bin2StrIpV6((SlNetSock_In6Addr_t *)binaryAddr, strAddr, strAddrLen); - - break; - default: - /* wrong address family - function error, return NULL error */ - return NULL; - } - - /* Check if conversion was successful */ - if (retVal != SLNETERR_RET_CODE_OK) - { - /* Conversion failed, return NULL as error code */ - return NULL; - } - /* Conversion success - return strAddr for success */ - return strAddr; -} - -//***************************************************************************** -// -// SlNetUtil_strTok - Split a string up into tokens -// -//***************************************************************************** -static int32_t SlNetUtil_strTok(char **string, char *returnstring, const char *delimiter) -{ - char * retStr; - - retStr = returnstring; - - while ( (**string !='\0') && (**string != *delimiter) ) - { - *retStr = **string; - retStr++; - (*string)++; - } - if (**string !='\0') - { - (*string)++; - } - *retStr = '\0'; - - return SLNETERR_RET_CODE_OK; -} - -//***************************************************************************** -// -// SlNetUtil_str2BinIpV4 - converts IPv4 address in string representation to -// IP address in binary representation -// -//***************************************************************************** -static int32_t SlNetUtil_str2BinIpV4(char *strAddr, SlNetSock_InAddr_t *binaryAddr) -{ - uint32_t decNumber; - char token[4]; - int32_t retVal; - int32_t ipOctet = 0; - uint32_t ipv4Address = 0; - char *modifiedStr = strAddr; - - /* split strAddr into tokens separated by "." */ - retVal = SlNetUtil_strTok(&modifiedStr, token, "."); - if (SLNETERR_RET_CODE_OK != retVal) - { - return retVal; - } - - /* run 4 times as IPv4 contain of four octets and separated by periods */ - while(ipOctet < 4) - { - /* Check Whether IP is valid */ - if(token != NULL) - { - /* Parses the token strAddr, interpreting its content as an integral - number of the specified base 10 */ - decNumber = (int)strtoul(token, 0, 10); - - /* Check if the octet holds valid number between the range 0-255 */ - if (decNumber < 256) - { - /* manually place each byte in network order */ - ((int8_t *)&ipv4Address)[ipOctet] = (uint8_t)decNumber; - - /* split strAddr into tokens separated by "." */ - SlNetUtil_strTok(&modifiedStr, token, "."); - ipOctet++; - } - else - { - return SLNETERR_RET_CODE_INVALID_INPUT; - } - } - else - { - return SLNETERR_RET_CODE_INVALID_INPUT; - } - } - - /* Copy the temporary variable to the input variable */ - memcpy(binaryAddr, &ipv4Address, sizeof(SlNetSock_InAddr_t)); - - return SLNETERR_RET_CODE_OK; -} - - -//***************************************************************************** -// -// SlNetUtil_str2BinIpV6 - converts IPv6 address in string representation to -// IP address in binary representation -// -//***************************************************************************** -static int32_t SlNetUtil_str2BinIpV6(char *strAddr, SlNetSock_In6Addr_t *binaryAddr) -{ - - int32_t octetIndex = 0; - int32_t octetTailIndex; - uint8_t *pLocalStr; - uint8_t tmp[16]; - int32_t zeroCompressPos = -1; - uint16_t value = 0; - uint8_t asciiCharacter = 0; - - /* Copy the first address of the string */ - pLocalStr = (uint8_t *)strAddr; - - /* Initialize tmp parameter */ - memset(tmp, 0, sizeof(tmp)); - - /* Check if the IP starts with "::" */ - if(*pLocalStr==':') - { - /* If the IP starts with ":", check if it doesn't have the second ":" - If so, return an error */ - if(*++pLocalStr!=':') - { - return SLNETERR_RET_CODE_INVALID_INPUT; - } - } - - /* run over the remaining two octets */ - while(*pLocalStr && (octetIndex < 16)) - { - /* Check if the ASCII character is a number between "0" to "9" */ - if(*pLocalStr >= '0' && *pLocalStr <= '9') - { - /* Each ASCII character can be max 4 bits, shift the number - 4 bits and copy the new converted number */ - value = (value << 4) | (*pLocalStr - '0'); - - /* Set the flag for ASCII character */ - asciiCharacter = 1; - } - /* Check if the ASCII character is a hex character between "a" to "f"*/ - else if(*pLocalStr >= 'a' && *pLocalStr <= 'f') - { - /* Each ASCII character can be max 4 bits, shift the number - 4 bits and copy the new converted number */ - value = (value << 4) | ((*pLocalStr - 'a') + 10); - - /* Set the flag for ASCII character */ - asciiCharacter = 1; - } - /* Check if the ASCII character is a hex character between "A" to "F"*/ - else if(*pLocalStr >= 'A' && *pLocalStr <= 'F') - { - /* Each ASCII character can be max 4 bits, shift the number - 4 bits and copy the new converted number */ - value = (value << 4) | ((*pLocalStr - 'A') + 10); - - /* Set the flag for ASCII character */ - asciiCharacter = 1; - } - /* Check if the hextet (two octets) finished with ":" and still a - part of the IP */ - else if((*pLocalStr == ':') && (octetIndex < 14)) - { - /* Check if the hextet contain ASCII character */ - if(asciiCharacter) - { - /* ASCII character exists, store the converted number in tmp - and reset the value and ascii character parameters */ - tmp[octetIndex++] = (value >> 8) & 0xFF; - tmp[octetIndex++] = (value) & 0xFF; - asciiCharacter = 0; - value = 0; - } - else - { - /* ASCII character doesn't exists, compressed hextet found */ - if(zeroCompressPos < 0) - { - /* first compressed hextet found, sore the octet Index */ - zeroCompressPos = octetIndex; - } - else - { - /* Second compressed hextet found, return error code */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - } - } - /* Continue to the next ASCII character */ - pLocalStr++; - } - - /* if more than 15 octets found, return error code */ - if(octetIndex > 15) - { - return SLNETERR_RET_CODE_INVALID_INPUT; - } - /* if less than 14 octets found, and without any compress hextet, - return error code */ - else if(asciiCharacter && (zeroCompressPos < 0) && (octetIndex < 14)) - { - return SLNETERR_RET_CODE_INVALID_INPUT; - } - /* if all octets found, but still found compressed hextet, - return error code */ - else if((zeroCompressPos >= 0) && octetIndex >= 14) - { - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* copy the last available hextet to the tmp array */ - if((asciiCharacter) && (octetIndex <= 14)) - { - /* Store the converted number in tmp and reset the value and - ascii character parameters */ - tmp[octetIndex++] = (value >> 8) & 0xFF; - tmp[octetIndex++] = (value) & 0xFF; - asciiCharacter = 0; - value = 0; - } - - /* compressed position found, add zeros in the compressed sections */ - if(zeroCompressPos >= 0) - { - /* compressed position found, add zeros in the compressed sections */ - octetIndex--; - octetTailIndex = 15; - /* Move the converted octets from the position they are located on - to the end of the array and add zero instead */ - while(octetIndex >= zeroCompressPos) - { - /* Check if the indexes are still in range */ - if ((octetTailIndex >= 0) && (octetIndex >= 0)) - { - /* Move all the octets after the zero compress position to - the end of the array */ - tmp[octetTailIndex] = tmp[octetIndex]; - tmp[octetIndex] = 0; - octetTailIndex--; - octetIndex--; - } - } - } - - /* Copy the temporary variable to the input variable */ - memcpy(binaryAddr, tmp, sizeof(tmp)); - - return SLNETERR_RET_CODE_OK; - -} - -//***************************************************************************** -// -// SlNetUtil_inetAton - Converts a string to a network address structure -// -//***************************************************************************** -int SlNetUtil_inetAton(const char *str, SlNetSock_InAddr_t *addr) -{ - uint32_t val[4]; - uint32_t base; - int sect; - char c; - - sect = -1; - while (*str) { - /* New section */ - sect++; - - /* Get the base for this number */ - base = 10; - if (*str == '0') - { - if (*(str + 1) == 'x' || *(str + 1) == 'X') { - base = 16; - str += 2; - } - else { - base = 8; - str++; - } - } - - /* Now decode this number */ - val[sect] = 0; - for (;;) { - c = *str++; - - if ((c >= '0' && c <= '9')) { - val[sect] = (val[sect] * base) + (c - '0'); - } - else if (base == 16 && (c >= 'A' && c <= 'F')) { - val[sect] = (val[sect] * 16) + (c - 'A') + 10; - } - else if (base == 16 && (c >= 'a' && c <= 'f')) { - val[sect] = (val[sect] * 16) + (c - 'a') + 10; - } - else if (c == '.') { - /* validate value */ - if(val[sect] > 255) { - return (0); - } - - /* - * Once we have four sections, quit. - * We want to accept: "1.2.3.4.in-addr.arpa" - */ - if (sect == 3) { - goto done; - } - - /* Break this section */ - break; - } - else if (!c) { - goto done; - } - else if (c != ' ') { - return (0); - } - } - } - -done: - /* What we do changes based on the number of sections */ - switch (sect) { - case 0: - addr->s_addr = val[0]; - break; - case 1: - if (val[1] > 0xffffff) { - return (0); - } - addr->s_addr = val[0] << 24; - addr->s_addr += val[1]; - break; - case 2: - if (val[2] > 0xffff) { - return (0); - } - addr->s_addr = val[0] << 24; - addr->s_addr += (val[1] << 16); - addr->s_addr += val[2]; - break; - case 3: - if (val[3] > 0xff) { - return (0); - } - addr->s_addr = val[0] << 24; - addr->s_addr += (val[1] << 16); - addr->s_addr += (val[2] << 8); - addr->s_addr += val[3]; - break; - default: - return (0); - } - - addr->s_addr = SlNetUtil_htonl(addr->s_addr); - return (1); -} - -//***************************************************************************** -// -// SlNetUtil_inetPton - converts IP address in string representation to IP -// address in binary representation -// -//***************************************************************************** -int32_t SlNetUtil_inetPton(int16_t addrFamily, const char *strAddr, void *binaryAddr) -{ - int32_t retVal; - - /* Switch according to the address family */ - switch(addrFamily) - { - case SLNETSOCK_AF_INET: - /* Convert from IPv4 string to numeric/binary representation */ - retVal = SlNetUtil_str2BinIpV4((char *)strAddr, (SlNetSock_InAddr_t *)binaryAddr); - break; - - case SLNETSOCK_AF_INET6: - /* Convert from IPv6 string to numeric/binary representation */ - retVal = SlNetUtil_str2BinIpV6((char *)strAddr, (SlNetSock_In6Addr_t *)binaryAddr); - break; - - default: - /* wrong address family - function error, return -1 error */ - return SLNETERR_RET_CODE_INVALID_INPUT; - } - - /* Check if conversion was successful */ - if (retVal != SLNETERR_RET_CODE_OK) - { - /* Conversion failed, that means the input wasn't a - valid IP address, return 0 as error code */ - return 0; - } - /* Conversion success - return 1 for success */ - return 1; -} diff --git a/ext/hal/ti/simplelink/source/ti/net/slnetutils.h b/ext/hal/ti/simplelink/source/ti/net/slnetutils.h deleted file mode 100644 index e4372f615d2..00000000000 --- a/ext/hal/ti/simplelink/source/ti/net/slnetutils.h +++ /dev/null @@ -1,427 +0,0 @@ -/* - * Copyright (c) 2017-2018, Texas Instruments Incorporated - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * * Neither the name of Texas Instruments Incorporated nor the names of - * its contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, - * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/*****************************************************************************/ -/* Include files */ -/*****************************************************************************/ - -#ifndef __SL_NET_UTILS_H__ -#define __SL_NET_UTILS_H__ - -#include - -#include "slnetsock.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/*! - \defgroup SlNetUtils SlNetUtils group - - \short Sockets related commands and configuration - -*/ -/*! - - \addtogroup SlNetUtils - @{ - -*/ - -/*****************************************************************************/ -/* Macro declarations */ -/*****************************************************************************/ -#define SLNETUTIL_AI_PASSIVE 0x00000001 -#define SLNETUTIL_AI_NUMERICHOST 0x00000004 - -/*****************************************************************************/ -/* Structure/Enum declarations */ -/*****************************************************************************/ - -typedef struct SlNetUtil_addrInfo_t { - int ai_flags; - int ai_family; - int ai_socktype; - int ai_protocol; - size_t ai_addrlen; - struct SlNetSock_Addr_t *ai_addr; - char *ai_canonname; - struct SlNetUtil_addrInfo_t *ai_next; -} SlNetUtil_addrInfo_t; - -/* Creating one address parameter from 4 separate address parameters */ -#define SLNETUTIL_IPV4_VAL(add_3,add_2,add_1,add_0) ((((uint32_t)add_3 << 24) & 0xFF000000) | (((uint32_t)add_2 << 16) & 0xFF0000) | (((uint32_t)add_1 << 8) & 0xFF00) | ((uint32_t)add_0 & 0xFF) ) - -/*****************************************************************************/ -/* Function prototypes */ -/*****************************************************************************/ - -/*! - - \brief Initialize the SlNetUtil module - - \param[in] flags Reserved - - \return Zero on success, or negative error code on failure -*/ -int32_t SlNetUtil_init(int32_t flags); - -/*! - \brief Return text descriptions of getAddrInfo error codes - - \param[in] errorCode A getAddrInfo error code - - \return Text description of the passed in getAddrInfo error code. - If the error code does not exist returns "Unknown Error" - */ -const char *SlNetUtil_gaiStrErr(int32_t errorCode); - -/*! - \brief Get host IP by name\n - Obtain the IP Address of machine on network, by machine name. - - \param[in] ifBitmap Specifies the interfaces which the host ip - needs to be retrieved from according to the - priority until one of them will return an answer.\n - Value 0 is used in order to choose automatic - interfaces selection according to the priority - interface list. - Value can be combination of interfaces by OR'ing - multiple interfaces bit identifiers (SLNETIFC_IDENT_ - defined in slnetif.h) - Note: interface identifier bit must be configured - prior to this socket creation using SlNetIf_add(). - \param[in] name Host name - \param[in] nameLen Name length - \param[out] ipAddr A buffer used to store the IP address(es) from - the resulting DNS resolution. The caller is - responsible for allocating this buffer. Upon - return, this buffer can be accessed as an array - of IPv4 or IPv6 addresses, depending on the - protocol passed in for the family parameter. - Addresses are stored in host byte order. - \param[in,out] ipAddrLen Initially holds the number of IP addresses - that the ipAddr buffer parameter is capable of - storing. Upon successful return, the ipAddrLen - parameter contains the number of IP addresses - that were actually written into the ipAddr - buffer, as a result of successful DNS - resolution, or zero if DNS resolution failed. - \param[in] family Protocol family - - \return The interface ID of the interface which was - able to successfully run the function, or - negative on failure.\n - #SLNETERR_POOL_IS_EMPTY may be return in case - there are no resources in the system\n - Possible DNS error codes: - - #SLNETERR_NET_APP_DNS_QUERY_NO_RESPONSE - - #SLNETERR_NET_APP_DNS_NO_SERVER - - #SLNETERR_NET_APP_DNS_QUERY_FAILED - - #SLNETERR_NET_APP_DNS_MALFORMED_PACKET - - #SLNETERR_NET_APP_DNS_MISMATCHED_RESPONSE - - \slnetutil_init_precondition - - \warning - In case an IP address in a string format is set as input, without - any prefix (e.g. "1.2.3.4") the device will not try to access the - DNS and it will return the input address in the \c ipAddr field - \par Example - - Getting IPv4 using get host by name: - \code - // A buffer capable of storing a single 32-bit IPv4 address - uint32_t DestIP[1]; - - // The number of IP addresses that DestIP can hold - uint16_t DestIPListSize = 1; - - int32_t ifID; - int16_t SockId; - SlNetSock_AddrIn_t LocalAddr; //address of the server to connect to - int32_t LocalAddrSize; - - ifID = SlNetUtil_getHostByName(0, "www.ti.com", strlen("www.ti.com"), DestIP, &DestIPListSize, SLNETSOCK_PF_INET); - - LocalAddr.sin_family = SLNETSOCK_AF_INET; - LocalAddr.sin_addr.s_addr = SlNetUtil_htonl(DestIP[0]); - LocalAddr.sin_port = SlNetUtil_htons(80); - LocalAddrSize = sizeof(SlNetSock_AddrIn_t); - - SockId = SlNetSock_create(SLNETSOCK_AF_INET, SLNETSOCK_SOCK_STREAM, ifID, 0); - - if (SockId >= 0) - { - status = SlNetSock_connect(SockId, (SlNetSock_Addr_t *)&LocalAddr, LocalAddrSize); - } - \endcode -*/ -int32_t SlNetUtil_getHostByName(uint32_t ifBitmap, char *name, const uint16_t nameLen, uint32_t *ipAddr, uint16_t *ipAddrLen, const uint8_t family); - - -/*! - \brief Network address and service translation - - Create an IPv4 or IPv6 socket address structure, to be used with bind() - and/or connect() to create a client or server socket - - This is a "minimal" version for support on embedded devices. Supports a - host name or an IPv4 or IPv6 address string passed in via the 'node' - parameter for creating a client socket. A value of NULL should be passed - for 'node' with AI_PASSIVE flag set to create a (non-loopback) server - socket. - - The caller is responsible for freeing the allocated results by calling - SlNetUtil_freeAddrInfo(). - - \param[in] ifID Specifies the interface which needs - to used for socket operations.\n - The values of the interface identifier - is defined with the prefix SLNETIF_ID_ - which defined in slnetif.h - - \param[in] node An IP address or a host name. - - \param[in] service The port number of the service to bind or connect to. - - \param[in] hints An SlNetUtil_addrInfo_t struct used to filter the - results returned. - - \param[out] res one or more SlNetUtil_addrInfo_t structs, each of which - can be used to bind or connect a socket. - - \return Returns 0 on success, or an error code on failure. - - \sa SlNetUtil_freeAddrInfo() -*/ -int32_t SlNetUtil_getAddrInfo(uint16_t ifID, const char *node, - const char *service, const struct SlNetUtil_addrInfo_t *hints, - struct SlNetUtil_addrInfo_t **res); - -/*! - \brief Free the results returned from SlNetUtil_getAddrInfo - - Free the chain of SlNetUtil_addrInfo_t structs allocated and returned by - SlNetUtil_getAddrInfo - - \param[in] res linked list of results returned from SlNetUtil_getAddrInfo - - \return None. - - \sa SlNetUtil_getAddrInfo() -*/ -void SlNetUtil_freeAddrInfo(struct SlNetUtil_addrInfo_t *res); - -/*! - \brief Reorder the bytes of a 32-bit unsigned value - - This function is used to reorder the bytes of a 32-bit unsigned value - from host order to network order. - - \param[in] val Variable in host order - - \return Return the variable in network order - - \slnetutil_init_precondition - - \sa SlNetSock_bind() - \sa SlNetSock_connect() - \sa SlNetSock_recvFrom() - \sa SlNetSock_accept() -*/ -uint32_t SlNetUtil_htonl(uint32_t val); - - -/*! - \brief Reorder the bytes of a 32-bit unsigned value - - This function is used to reorder the bytes of a 32-bit unsigned - value from network order to host order. - - \param[in] val Variable in network order - - \return Return the variable in host order - - \slnetutil_init_precondition - - \sa SlNetSock_bind() - \sa SlNetSock_connect() - \sa SlNetSock_recvFrom() - \sa SlNetSock_accept() -*/ -uint32_t SlNetUtil_ntohl(uint32_t val); - - -/*! - \brief Reorder the bytes of a 16-bit unsigned value - - This functions is used to reorder the bytes of a 16-bit unsigned - value from host order to network order. - - \param[in] val Variable in host order - - \return Return the variable in network order - - \slnetutil_init_precondition - - \sa SlNetSock_bind() - \sa SlNetSock_connect() - \sa SlNetSock_recvFrom() - \sa SlNetSock_accept() -*/ -uint16_t SlNetUtil_htons(uint16_t val); - - -/*! - \brief Reorder the bytes of a 16-bit unsigned value - - This functions is used to reorder the bytes of a 16-bit unsigned value - from network order to host order. - - \param[in] val Variable in network order - - \return Return the variable in host order - - \slnetutil_init_precondition - - \sa SlNetSock_bind() - \sa SlNetSock_connect() - \sa SlNetSock_recvFrom() - \sa SlNetSock_accept() -*/ -uint16_t SlNetUtil_ntohs(uint16_t val); - -/*! - \brief Convert an IPv4 address in string format to binary format - - This function converts an IPv4 address stored as a character string to a - 32-bit binary value in network byte order. Note that a leading zero or a - "0x" in the address string are interpreted as octal or hexadecimal, - respectively. The function stores the IPv4 address in the address structure - pointed to by the addr parameter. - - \param[in] str IPv4 address string in dotted decimal format - - \param[out] addr pointer to an IPv4 address structure. The converted binary - address is stored in this structure upon return (in network byte order) - - \return returns nonzero if the address string is valid, zero if not -*/ -int SlNetUtil_inetAton(const char *str, struct SlNetSock_InAddr_t *addr); - -/*! - \brief Converts IP address in binary representation to string representation - - This functions is used to converts IP address in binary representation - to IP address in string representation. - - \param[in] addrFamily Specifies the address family of the created - socket - For example: - - #SLNETSOCK_AF_INET for network address IPv4 - - #SLNETSOCK_AF_INET6 for network address IPv6 - \param[in] binaryAddr Pointer to an IP address structure indicating the - address in binary representation - \param[out] strAddr Pointer to the address string representation - for IPv4 or IPv6 according to the address - family - \param[in] strAddrLen Specifies the length of the StrAddress_dst, - the maximum length of the address in string - representation for IPv4 or IPv6 according to - the address family - - \return strAddr on success, or NULL on failure - - \slnetutil_init_precondition - - \par Example - - IPv4 demo of inet_ntop() - \code - SlNetSock_AddrIn_t sa; - char str[SLNETSOCK_INET_ADDRSTRLEN]; - - // store this IP address in sa: - SlNetUtil_inetPton(SLNETSOCK_AF_INET, "192.0.2.33", &(sa.sin_addr)); - // now get it back and print it - SlNetUtil_inetNtop(SLNETSOCK_AF_INET, &(sa.sin_addr), str, SLNETSOCK_INET_ADDRSTRLEN); - \endcode -*/ -const char *SlNetUtil_inetNtop(int16_t addrFamily, const void *binaryAddr, char *strAddr, SlNetSocklen_t strAddrLen); - - -/*! - \brief Converts IP address in string representation to binary representation - - This functions is used to converts IP address in string representation - to IP address in binary representation. - - \param[in] addrFamily Specifies the address family of the created - socket - For example: - - #SLNETSOCK_AF_INET for network address IPv4 - - #SLNETSOCK_AF_INET6 for network address IPv6 - \param[out] strAddr Specifies the IP address in string representation - for IPv4 or IPv6 according to the address - family - \param[in] binaryAddr Pointer to an address structure that will be - filled by the IP address in Binary representation - - \return 1 on success, -1 on failure, or 0 if the input - isn't a valid IP address - - \slnetutil_init_precondition - - \par Example - - IPv6 demo of inet_pton() - \code - SlNetSock_AddrIn6_t sa; - - // store this IP address in sa: - SlNetUtil_inetPton(SLNETSOCK_AF_INET6, "0:0:0:0:0:0:0:0", &(sa.sin6_addr)); - \endcode -*/ -int32_t SlNetUtil_inetPton(int16_t addrFamily, const char *strAddr, void *binaryAddr); - -/*! - - Close the Doxygen group. - @} - -*/ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __SL_NET_UTILS_H__ */ diff --git a/ext/hal/ti/simplelink/Kconfig b/modules/Kconfig.simplelink similarity index 100% rename from ext/hal/ti/simplelink/Kconfig rename to modules/Kconfig.simplelink diff --git a/west.yml b/west.yml index b9e0317333f..0d318b02794 100644 --- a/west.yml +++ b/west.yml @@ -55,6 +55,9 @@ manifest: - name: hal_stm32 revision: 272281a1990ec7097f1844778955ed60fe28662a path: modules/hal/stm32 + - name: hal_ti + revision: 7a82e93e14766ef6e42df9915ea2ab8e3b952a8b + path: modules/hal/ti - name: libmetal revision: 45e630d6152824f807d3f919958605c4626cbdff path: modules/hal/libmetal